1988_Standard_Microsystems_Components_Catalog 1988 Standard Microsystems Components Catalog

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INDEX

PAGE

PART NUMBER

3

FUNCTIONAL

5-10

CROSS REFERENCE

11-14

GENERAL INFORMATION
INTRODUCTION

15-22

CUSTOM CAPABILITIES

23-28

QUALITY ASSURANCE & QUALITY CONTROL

29-36

DATA COMMUNICATION PRODUCTS

....

37-268

BAUD RATE GENERATOR

. . .. 269-292

DISPLAY PRODUCTS

.. .. 293-452

FLOPPY DISK

.. .. 453-566

HARD DISK

. . .. 567-736

KEYBOARD ENCODER

. . .. 737-752

MICROPROCESSOR PRODUCTS

. . .. 753-760

TABLE

OF
CONTENTS

SHIFT REGISTER

ORDERING INFORMATION
©1988 STANDARD MICROSYSTEMS CORP.

. . ..

761-766

. . .. 767-776

PART NUMBER INDEX
PART NUMBER
COM1553A
COM1553B
COM1671
COM1863/8018
COM2651
COM2661
COM5016/5036
COM5025
COM5026/5046
COM52C50
COM7210
COM78C802
COM78C804
COM78808
COM78C808
COM8004
COM8017/8502
COM8046
COM8116/8136
COM81C17
COM8126/8146
COM8156
COM81 C66/67/68
COM82C11
COM8251A
COM82C501
COM82C502
COM82586
COM9026
COM90C26
COM90C32
COM9046
COM90C56
COM90C62
COM9064
COM91C32
COM92C32
CRT5027/37/57
CRT5047

PAGE
39
41
57
59
61
63
271
65

PART NUMBER
CRT7220A
CRT8002
CRT8002H
CRT8021/8021-003
CRT9006
CRT9007
CRT9021
CRT9028/9128
CRT9041
CRT9053/9153
CRT92C07
CRT9212
CRT94C12
CRT97C11
FDC765A/7265
FDC1791-02
FDC72C65
FDC91 C36/92C36
FDC9216
FDC9229
FDC92C38
FDC92C39
FDC9266
FDC9268
FDC92C81
FDC9791
HDC1100-01
HDC1100-12
HDC1100-03
HDC1100-04
HDC1100-05
HDC7260
HDC7261A
HDC9223
HDC9224
HDC9225
HDC92C26
HDC9227
HDC9234

273
77
95
107
121
135
137
151
153
275
277
161
279
287
291
169
177
197
201
193
205
207
223
229
233
235
239
247
253
295
297
3

PAGE
299
323
325
327
329
335
357
369
385
401
417
421
427
433
455
471
473
497
501
505
513
517
525
541
557
565
569
571
573
575
577
579
583
585
589
625
627
635
637

PART NUMBER
HVC9058
HVC9068
HVC9078
KR9600/9601/9602
MPU800
MPU810A

PART NUMBER
MPU830/831 .

PAGE
257
263
267
739
755
757

MSD7262
MSD95COO
MSD95C02
SR5015
SR5017/5018

4

PAGE
759

6n
681
693
763
765

FUNCTIONAL INDEX
Data Communication Products
COM 1553A

COM 1563B
COM 1671.

Mn,·S'l'l)·
1553A

~ Data Oommunication ProductsoollT.

_
Part

:reaw.re.

De
Dua.l Baud &te Generator

lI'1Imber
COM 8116
COMSl15T<')
COM8126
COM 8126T(»
COM8136
COM 8136T<')
COM8146
COM 8146Tm
COM815e

(1

Baud BaH Generator COJre
Sirutle + 6 volt Vl!l'S1on of COM 6016
Sirutle + 5 volt version of COM 50laT
Sl.ngle + 5 volt version of COM 6026
Single + 6 volt version ofOOM 6026T
Single + 5 volt version of COM 6036
Single. + 6 volt vereion of OOM 5036T
Single + 6 volt version ofOOM 5046
S1ngl!;! + 6 volt version of COM 5046T
High.frequency CloCk input version of
COM 8116 with additional outputs of
inPUt freauen.o.v + 2 and + 8
External OloCk input version of
COM 8166
CMOS User Prog),'a.:mmable Clocka.nd Timer
Externa.l Frequency Input version
of COM 8166T
CMOSUser Programmable Clock and Timer.
Bu.iJ.t..in XTAL oso1lla.tor 2 timEI1'S
TTL CloCk Driver Version ofths COMSlC67
with 3 timere

Dual Baud &te Generator
S1N!le Baud Ra.te Generator
S1N!le Baud &te Generator
Dua.l Baud &te Generator
Dual Baud &te Genel'lif,tor
Single Baud Ra.te Generator
Singli;! Baud &te Generator
Dual Baud &te Generator

COM 8166T<')

Dua.l Baud Rate Generator

OOM 81066(0)
COM 81C6aT
     and VT220@>
intensity
levels
C-25.6MHz
lie~~,12blt
cOnl-oat1bie
shift
tel'
CRTamll

+6

»age

26MRz

VIDEO..M.'TllIBU".rES COlftBDLLEBS
Put
JhabU

IhDlY hC!k84e

:::.

hokUe

.»age

+6.

.28 DIP

327-328

+6

28 DIP

367-368

+6

40 DIP

386-400

. Provides a.tla'ibutes
andgraph1C$ cOntrol

BOW BUFl'BB.
:tart

:III'1I.mbel'
CRT 9006-83
CRT 9006-136
oBT9212

1low~

·:De~OIl.

8 bit Wide seria.1 oasca.da.ble single rqw
buffer memorY tor CRT orprlntel'
8 bit Wide seris;l C~le double raw
buffer mei:noryfOr CRT or 'Orintel'
8 bit wide ser1a.l, qjlad rr:JW~·msmory
CRT94Cl2
for CRT or Printer
VT100® and VT220® are registered trademarks ofD1g1tal Equipment Corp.

8

83 characters
136ohara.otsrs
136ohara.otsl'S
138.cha.rll.oters

1toweJi~'

hGkage

Page

+6

24 DIP

329-334

+6

25 DIP'

421425

+5

40 DIP

,

'427:432

l'art

Ma.:It. BecommeJUled
Data
Software
CompatabUlty
Disk Data ~anafer Bate seParator
IBM® PC/ATII!>,PCIXT, PSI2®
600 Kbfsec
16 MHz Digital

l'I'tunber
FDC9268

~

Il'a.c1caIe

40 DIP,
44PLCC
FDC9266
IBM® PC/AT®, PCIXT, PS/2®
260 Kb/seo
8 MHz Digital
40 DIP,
+5V
44PLCC
IBM® PClAT®, PCIXT, PS/2®
FDC 766.A, 7B6A·2,
500 Kb/sea
40 DIP,
extel'Il.al
+5V
7265
44PLCC
IBM® PCIAT®, PCIXT, PSf2®
FDC 72C85, 72C86
40 DIP,
Up to 1 Mb/sec
+6V
exter:na.l
44PLCC
IBM® PC/AT®, PCIXT, PS/2®
FDC92C81
Up to 1 Mblseo
24 DIP,
+6V
28PLCC
FDC 91C38IB. 92C3BIB IBM PC/AT® PC!.X:'r PSI2®
8 DIP
2501600 Kb/seo
16 MHz DiItiteJ
+5V
IBM® PClAT®.PClXT. PSI2® 260/500/500/260 Kb/seo 16 MHz Dil!ital
FDC92C38/B
14 DIP
+6V
IBM® PClAT®, PCIXT, PS/2® 250/500/5001250 Kblseo
FDC 92C391B1BTIT
20 DIP,
16 MHz Digital
+6V
28PLCC
IBM® PC/ATII!>, PCIXT, PS/2®
FDC 9229TIBT
1261250 Kb/sec
8 MHz Digital
20 DIP,
+6V
25PLCC
FDC92161B
IBM® PClAT® PCIXT, PBl2®
126/260 Kb/seo
8 MHz Digital
8 DIP
+6V
FDC 9791, 9793, 9795, 179X
40 DIP,
250 Kblseo
external
+5V
9797
44PLCC
FDC 1791. 1793.1796, 179X
250 Kbfseo
extel'Il.al
+ 5V, +12V 40 DIP,
1797
44PLC
+5V

~

l'aP.
641·666
626-540
466-470
473-496
557·564
497-500
513-516
617·524
506·612
601·604
666-588
471·472

~BardDisk
Max. Disk

Data~er

~~

JIard:Oisk

Power

external
external
external

+5V
+5V
+5V
+5V

l'art
l'I'tunber

Disk I'ormat

MSD95COO
M8D95C02
MSD7262
HDC9234

SCSI
User Defined
ESDI
IBM® PCfAT®. ST·506

HDC92C25

ST·608

MFM,FM

6 Mb/seo

.Analog,
extel'Il.al VCO

+6V

HDC9223
HDC9224

ST-506
DEC VAX®, MICROVA:x:®.
ST-506
ST·508

MFMFM
MFM.FM

6 Mb/seo
5 Mb/seo

VCOonly
external

+6V
+6V

MFM.FM

5 Mb/seo

Analog,

+6V

6 Mb/seo
12 Mblsec
8Mb/sec
6 Mb/seo

extel'Il.al VCO
external
external
external
extel'Il.al

+6V
+6V
+6V
+5V

HDC9S27
HDC9226 ,
HDC7251
HDC7250
HDC 1100·01,
·12 ·03 -06

ST·606
NEOST·5OB
NECST·606
BAlOOO, 8'1'-506

MFM,FM
MFMFM
MFM.FM
NRZ,MFM,FM

extel'Il.al

e l'age
6BPLCC 661-692
66PLCC 893-736
40 DIP 677-680
637-676

~~

24 DIP. 627·634
25PLCC
14 DIP 586-688
40 DiP, 689·624
44PLCC
25 DIP, 636-636
28PLCC
48 DIP 825-625
40 DIP 583-664
40 DIP 579-652
20 DIP 569·678

...

.0.
of
Keys

JIlodes

KR-9800 n ( l )

90

4

KR-9601 n O )

90

4

90

Data ..

,.;'-v,,~~
Keyboard Encoder
"""

l'art
l'I'tunb81'

KR-9602 x::x;t"

RLL 2 71MFM1liTRZlGCR
RLL 2.7/MFWNRZlGCR
NRZ
MFM,FM

Bate
20 Mb/seo
24 Mb/seo
18 Mb/seo
5 Mb/seo

4

l'eatares
20rNKey
Rollover
2 or N Key
Rollovel\
caps-look,
auto-repeat
20rNKey
Roliovell
caps·lOOk,
a.uto-repee.t,
serial outPUt

hff':bI:Standardr=:n
:Oeser
BlnM'y Sequential
·PRO
ASCII
-STD
-STD
-O12,2}

BlnM'y Sequential
ASCII

-BTD

BlnM'y Sequential
ASCII

-012(2)

9

':::s

~.

+6

l'a.c1caIe
40DIPI
44SMT

+5

40 DIP/
44SMT

739·752

+6

28DIPI
28SMT

789-'1'52

739-752

~ Microprocessor Products
,~

DeB"""

~..

M P t J 8 O O ' , 8 Bit
''MPU$OO~1 , ' 8 & : '·...SBlt
;mtrBOO"4,' '.:M:icr, ,76$;.75e
'. OliOS
' 4:0:MH:z··· ',';" .. 5V.)/./·,;·,'4,b'Dll> .. · . 755.'7B6
OM:OS2.5MHZ
.. '. 'av'" '.··,40DIP'l'5r,,76S;

,OM:OS

' l:OKHlll ···..:'5V<'"

..:' " '::B.OMAIO;;'.;;. ....., S : 8 i t . ,OM:OS '-4;O'lnIz

l4W831

. .I/O'

8 Blt

.CMOS

i;"",:,ev;;"

··l.OMHz . . , ' 5V,

IBM@,l\T@ andPS/2@ are regiStered trademarks of the International Business Maclllnes Corporation.
VAX@ IS a regIStered tra.damark of the Digital Equipment Corporation.

10

<'ii,' ,~niP

:'·40DIP

'l'5g,.,'760
.759-'760

,", 4ODIl>··

7$-760.

SMC CROSS REFERENCE GUIDE-STORAGE IC'S
NEe

Description
IBM" Compatible Floppy Disk Controller

IJ,PD765A1B

Hi-Speed Floppy Disk Controller

f!.PD765A-2

Western
Dlgltsl

Siemens

Fujitsu

Sony Microfloppy Disk Controller
CMOS Floppy Disk Controller
CMOS Sony Microfloppy Disk Controller

f!.PD72065

ESDI Disk Controller
ST-506 Winchester Disk Controller

f!.PD7261A

ST-506 Winchester Disk Controller
ST-506 Winchester/Floppy Disk Controller
CMOS Floppy Disk Data Separator

FD9216/B

Floppy Disk Data Separator

FD9216/B

Floppy Disk Controller

FD1791-02

SAB-1791

MB8876

Floppy Disk Controller

FD1793-02

SAB-1793

MB8877

Floppy Disk Controller

FD1795-02

SAB-1795

Floppy Disk Controller

FD1797-02

SAB-1797

Floppy Disk Controller

FD1791-02

SAB-1791

MB8876

Floppy Disk Controller

FD1793-02

SAB-1793

MB8877

Floppy Disk Controller

FD1795-02

SAB-1795

Floppy Disk Controller

FD1797-02

SAB-1797

ST-506 Winchester Disk Controller

WD1100-01

ST-506 Winchester Disk Controller

WD1100-12

ST-506 Winchester Disk Controller

WD1100-03

ST-506 Winchester Disk Controller

HDC1.100-05

WD1100-05

11

SMC CROSS REFERENCE
AMD

Fairchild

General
Instrument

Harris

Intel

F3846'
F3856'
F68488'
96LS488'

8291/92'

AY5-8116/36
F4702'

AY5-8126

HD4702'
HD6405'

SMC CROSS REFERENCE
Description

CRT Controller

AMI

AMD

Fairchild

General
Instrument

Harris

Intel

, CRT5Cl37 .....

8275

.CRT72201.

82720

Character Generator
Display Controller
Graphics Controller
Video Processor and
Controller
Video Attributes Controller

C~TmOA

CAT9007 .....,
.cRT9p41.·.·

'Functional equivalent.
"Most UART'S are interchangeable; consult the factory for detailed information on interchangeability.

12

GUIDE-DATA COMMUNICATIONS
Motorola

National

MC6850'

NSC858'

-

-

-

-

-

-

-

2536'

-

-

INS1671

-

-

-

INS2651

-

2651

-

-

2661

INS8251

."PD8251A

-

MC2661'

2652'
MC68B488'

MC14411'

-

NEC

Signetics

Solid
State
Scientific

DEC

Texas
Instruments

Western
Digital

SCR1854'

-

TMS6011'

TR1602

-

-

-

TR1983'

-

78808

TR1863

-

-

-

UC1671

-

-

-

SD1933'
WD9914'

-

-

2652

SND5025

-

-

-

-

TMS9914'

-

-

-

-

-

-

-

-

-

-

WD2840'

-

-

-

-

-

-

-

-

-

-

-

MM307'

-

-

-

-

-

MM5740'

-

-

-

-

TMS5001

-

NSC800

-

-

-

NSC810A

-

-

NSC830

-

-

-

-

-

-

-

NSC831

-

-

-

-

-

-

6852'

DP8340/41 ,
DP8344'

DP8344'

-

."PD7210

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

TR1983'

-

WD1941
WD1943/5

-

-

-

-

-

-

DEC

Texas
Instruments
TMS9927/37

-

-

-

-

GUIDE-DISPLAY PRODUCTS
Motorola

National

MC6845'

DP8350'

NEC

Signetics

Solid
State
Scientific

-

-

-

-

-

-

UPD7220
UPD7220A

-

-

-

-

-

-

-

-

SCN2674'

-

SCN2675'

-

NS455'

-

-

-

-

-

-

-

-

-

13

-

-

-

Western
Digital

-

-

14

Innovation in Microelectronic
Technology is the Key to Growth at
Standard Microsystems.
Since its inception, Standard Microsystems has been a leader in creating
new technology for metal oxide semiconductor large scale integrated
(MOS/LSI) and very large scale integrated (MOS/VLSI) circuits.
Standard Microsystems' COPLAMOS® silicon gate n-channel process,
licensed to over 15 prominent semiconductor companies, is the de facto
standard for high speed, high density integrated circuits.
COPLAMOS® utilizes a self-aligned, field-doped, locally oxidized structure to
eliminate parasitic currents and shunt capacitance. This allows the tight
packing of circuitry essential for VLSI, yet with performance rivaling that of
bipolar technologies.
In addition, on-chip generation of substrate bias, also pioneered by Standard
Microsystems, when added to the COPLAMOS® technology, results in the
ability to design dense, high-speed, low-power n-channel MOS integrated
circuits through the use of one external power supply voltage.

Engineering. marketing and sales personnel occupy SMOIl'S 50,000 square foot facility at
300 Kennedy Drive.

This 43,000 square foot building Is the center of SMC®'s research and development and
wafer fabrication operations.

15

These innovations in both process and circuit technology have received
widespread industry recognition. In fact. many of the world's most prominent
semiconductor companies have been granted patent and
patent Itechnology licenses covering various aspects of these technologies.
The companies include Texas Instruments. IBM. General Motors. ITT. Western
Electric. Hitachi. Fujitsu. National Semiconductor. Mitsubishi Electric. NEC.
AT&T. Data General. Oki Electric, Gouldl AMI. Sprague Electric. Toshiba. NCR
and Intel.
Over the past few years, scientists and engineers at Standard Microsystems
have been developing a technology to significantly reduce the sheet
resistivity of the gate material used in MOS, dramatically decreasing internal
time constants in MOS devices.
This technology replaces the polycrystalline silicon normally used in
n-channel MOS devices with an alternate material. titanium disilicide. This has
enabled Standard Microsystems to become the first semiconductor
manufacturer to market and sell MOS/VLSI circuits which employ a metal
silicide to replace the conventional doped polycrystalline silicon layer.
Standard Microsystems has continued its technological leadership with the
introduction of new products utilizing an advanced low-power, high-speed
two micron n-well CMOS process. With its 1.6 micron effective channel
lengths and its double layer metal option. this process is ideally suited for
standard products, standard cells and full custom designs. Another
processing option which incorporates analog 9apacitors on the device
allows for efficient, high-speed analog applications.
In CMOS circuitry. an obvious reliability concern is latch up. To avoid the
problem with the two micron n-well CMOS process. Standard Microsystems'
design, processing and quality engineers have worked together to create
layout and processing specifications which assure latch-up-free design in
accordance with the proposed JEDEC 7A specification.

State-of-the-art wafer stepper projects MOSIVLSI circuit patterns onto silicon wafers.

16

Wfive Established a Position as the
Industry Leader in Microperipherals
with a Steady String of Industry "Firsts':
Standard Microsystems Corporation has made significant contributions in
addressing the challenges inherently associated with connectivity: "That is
the creation of a path from one computer system to another, so that
information can be meaningfully exchanged between those systems."
In local area networking (LANs), SMC® was the first to introduce a single-chip
local area network controller. This device (the COM9026) implements the
ARCNET® LAN protocol, and is now a de facto standard. This early
introduction has placed Standard Microsystems' ARCNET® products very
high on the price/performance curve. Over 500,000 ARCNET® nodes are
currently installed, giving this mature, reliable LAN close to a 50% market
share. Standard Microsystems continues to maintain its position as premier
supplier of ARCNET® LAN products. The revolutionary High Impedance
Transceiver (HIPM) introduced in 1986, which enabled the implementation of a
new bus topology for ARCNET® , has achieved strong market acceptance.
But SMC® is far from resting on its laurels and is readying several new
products to further increase ARCNET® performance while reducing its cost.
These include: the COM90C62 (which integrates the COM90C26 LAN
Controller and the COM90C32 LAN Transceiver) and the ELANC
COM90C56 (Enhanced LAN controller that doubles the data bit rate and
offers, among other features, LAN Management and LAN Diagnostics).
As a result of the second source agreement recently signed with Intel Corp.,
SMC® will also be able to offer the chip set required to implement Ethernet™
Local Area Networks. The chip set will include the industry standard
COM82586 LANC as well as the COM82C501 transceiver and the
COM82C502 serial interface chip. Standard Microsystems Corporation thus
becomes the only supplier of components for the two LAN
implementations with the largest installed market base.

SMC® 's ARCNET® LAN supports a star topology, bus topology or combination of both.
17

Standard Microsystems Corporation is also at the forefront of the micro-tomainframe connectivity in an IBM® environment. No matter which IBM®
mainframe connection is considered, the IBM® 3270 or IBM® System/3X,
SMC® interface devices are the most cost-effective design approach
availabl.e in the market. SMC® was first to introduce 3270 COAX and 5250
TWINAX interface devices. The COM9064 and COM52C50 are unique
single-chip solutions that enable PC, terminal and printer manufacturers to
provide communication links within the IBM® mainframe environment at
reasonable cost.
Standard Microsystems Corporation, known worldwide for mony industry
firsts in the field of UARTs, is continuing its tradition with the introduction of two
new products that will definitely change the design implementation of
asynchronous data communications. The COM81C17, the only 20-pin CMOS
UART in the market, has a size which is overshadowed only by its speed. The
COM81C17 features a lOOK bits-per-second transfer rate-a far cry from the
usual 19.2 Kbits per second offered by most UARTs currently available.
However, it is our new family of multiple UARTs, designated COM78C80X, that
will bring the asynchronous data communication market to new heights.
These VLSI devices, which integrate 2, 4 or 8 complete channel interfaces in
one chip, revolutionize the distribution of data communication.
In another area, CRT display systems have traditionally required a great deal
of support circuitry for the complex timing, refresh and control functions. This
need led the engineers at SMC® to develop the CRT5027 VT AC, the first CRT
controller to provide all of these functions on a single chip. A second
generation CRT controller, the CRT9007 VPAC was then introduced, and
became an industry standard when it was designed into the DEC VT220
terminal. The CRT9007 is the heart of a complete high performance CRT
controller family, which includes single, double and quad row buffers, and a
variety of video attribute controllers. Various elements of the VPAC family

SMC'~'s

•

chip and boord-level products offer definite space, cost and performance
advantages in a wide range of applications.

18

can be selected to provide the optimal video control solution from low-end
to high-end systems.
For lower cost designs, a family of single-chip solutions exists which Integrates
the entire timing. video and attribute control functions on a single VLSI circuit.
Two of the devices In this family are the CRT9028/9128 VTLC and the
CRT9053/9153 EVTLC which are mask programmable and, by also Including
the character generator on the chip, provide the lowest cost solution. The
latest edition to this single-chip family Is the CRT92C07 A TLC (Advanced
Terminal Logic Controller) which Is fully register programmable and supports
all the features of higher performance terminals, Including the ability to
emulate the DEC VT100 and VT220 environments. A complete terminal can
be built using these devices with just the Inclusion of a RAM and
microprocessor.
One of the most popular features appearing In PC and terminal display
interfaces is the capability of windowing. This feature Is now supported by a
third generation CRT controller, the CRT97Cll VIEW (Video Engine for
Windows). This device Is capable of generating up to 127 hardware windows
on screen and provides the ability to pan Images behind windows in real
time. The overhead associated with the management of windows on-screen
is highly simplified when compared to software techniques.
Standard Microsystems Corporation has also spearheaded many
developments In the areas of disk controllers and data separators for both
Winchester and floppy disks. SMC® offers more Industry standard floppy disk
ICs than any other source. These Include the FDC765A controller, the CMOS
FDC72C65 and the FDC9216, FDC9229 and FDC9239 series of data
separators.
Only SMC® offers the licensed Industry standard FDC765A and a patented
high resolution digital data separator in a single Ie. Called FDC9268, this
single chip offers deSigners of personal home computers the lowest cost
floppy disk controller possible.
Extracting the actual stored data and clock signals from the distorted and
jittery Signal provided by a disk drive, has historically required a trade off
between data Integrity and the need to use additional off-chip analog
components which sometimes required production line adjustments.
However, SMC®'s advanced Digital Floppy Disk Data Separators with built-In
write precompensation (like the one in the FDC9268) assure reliable data
transfers to and from disk, even when reading and writing high denSity floppy
disk on different disk drives.
SMC® also offers the most advanced self-tuning Analog Floppy Disk Data
Separator for the ultimate in data integrity. The FDC92C81 CMOS Dual Gain
Analog Floppy Disk Data Separator adjusts its gain automatically when
attempting to lock to data, guaranteeing both optimal bit shift tolerance
and quick locking to data. This results in the greatest tolerance to bit shift in
the industry for IBM® PCI AT® compatible environments. These advances in
data separator technology should come as no surprise from the company
that invented the present-day digital data separator.
IBM® compatible hard disk controllers can be designed at a very low cost
using SMC®'s HDC9234 Winchester Controller IC. Used with the HDC92C26
Hard Disk Data Separator and the HDC9223 VCO, the HDC9234 may be used
on the motherboard of an A T® or XFM type personal computer or on a
separate controller card. Combined with the HDC9234, the FDC9268 Floppy
Disk Controller adds floppy disk and tape backup capability to the controller
card.
19

•

For space-conscious designs requiring a single controller for both
Winchester and floppy disks, the HDC9224 is ideal. When used with the
HDC9227, which performs data separation on data from both Winchester
and floppy disks, and with the HDC9223 VCO, the HDC9224 provides a
truly optimal multi-media controller for Winchester, floppy and tape drives.
An embedded SCSI (Small Computer System Interface) disk drive, that
sustains a continuous 20 M bits per second disk transfer rate
simultaneously across both the SCSI bus and the media, is possible when the
disk controller is SMC®'s MSD95C02 and the SCSI bus controller is SMC®'s
MSD95COO. Individual data busses for processor, disk, and SCSI
information allow 5 Mbyte per second SCSI bus transfers to continue
uninterrupted by processor bus accesses. Zero latency reads, multiple sector
read look-ahead, fully programmable disk format and error correction onthe-fly all contribute to saving disk revolutions and decreasing the disk
access time. The MSD95C02 handles GCR formatted tape as well, and can
also be used in non-SCSI applications.
SMC®'s MSD95C02 VLSI Storage Controller is built from a set of highly
advanced dedicated SuperCelis™. Each SuperCeWM performs a specialized
function (e.g., DMA, Microsequencer, disk encoder/decoder, microprocessor
interface, or error correction). By modifying a particular SuperCeWM, or by
substituting a user defined cell, it is possible to build a peripheral controller for
specialized applications with minimum modification. This technique results in
an optimal solution for each application and offers the advantage of
allowing deSign engineers to build in special features necessary for product
differentiation.
Standard Microsystems' long list of successes in the microperipheral area has,
in many cases, allowed us to satisfy specific customer requirements by
modifying our standard products offerings accordingly. As Illustrated in our
modular deSign approach to the MSD95C02, SMC® has gone a step beyond
the Standard Cell by defining and building Standard Products made up of
SuperCelis™. These SuperCelis™, which are highly complex pieces of logic in
thelr own right can provide the customer with a set of high level building
blocks which have been defined specifically for end-user applications.

SMC® 's CUSTOMATIONTM standard cell library and ASIC development tools are compatible
with virtually all industry-standard workstations.

20

These cells may be combined with other SuperCelis™, or user defined logic,
resulting in fast turnaround, highly area efficient ASIC circuits. This approach
offers the customer system level tools to which he can relate. It is now
possible for Standard Microsystems Corporation to tailor our systems
expertise, acquired over years of designing and fabricating standard
microperipherals, to the customer's specific needs to add that additional
measure of assurance that the best possible solution is attained.

Improvements in Processing and
Manufacturing Keep Pace with
Advances in Semiconductors.
With the phenomenal growth of the electronics industry, processing
innovations are critical. But, if the products are to perform as designed, they
also have to be reliable.
At Standard Microsystems Corporation, we make every effort to ensure the
highest degree of quality and reliability in our products. Consequently, "stateof-the-art" applies not only to our products, but to the manufacturing
processes as well.
Self-aligned, fully ion-implanted, short channel NMOS, p-well CMOS and
n-well CMOS technologies require the most modern wafer fabrication
equipment and facilities. Consequently, Standard Microsystems has
continued to upgrade its wafer fabrication facility with the latest state-ofthe-art technologies. Requirements for better incoming raw material quality
control have necessitated the purchase of the latest KLA and Leitz
inspection systems. The correct tolerances are achieved with the use of Perkin
Elmer's scanning projection printers, ASET's 5X reduction steppers, and Tegal's

Latest computer-controlled furnaces automatically regulate several diffusion and oxidation
processes simultaneously.
21

plasma etching systems, Improvements in the clean room atmosphere of
Standard Microsystems Corporation's wafer fabrication facility and in the
gas distribution system have been achieved.
SMC® 's commitment to excellence is further demonstrated in the use of the
latest Sentry, Gen Rad and Megatest test equipment, Our components tests
are derived from extensive logic simulations which ensure maximum fault
coverage on each circuit. These simulations are run on our variety of inhouse workstations as well as our VAX 111785 computer cluster system. This
service capability allows us to make full use of the technologies we develop.
We can produce any quantity of semiconductors customers require. What's
more, we can provide our customers with the fast delivery times that they
demand in today's increasingly competitive environment.
Throughout its history, Standard Microsystems Corporation has been at the
forefront in the design, development and manufacturing of highly complex
integrated circuits for the computer, microperipheral and data
communications fields, Breakthrough technologies such as those previously
outlined have certainly contributed to our success, but even more important
is our ability to satisfy our customers.
Quality is our bottom line and the responsibility of each and every employee
at SMC® . We are constantly striving to make sure that our products'
performance meets your highest expectations. Our unprecedented growth
over the last decade is proof that we're doing the job.
With five modern buildings on Long Island alone, including state-of-the-art
design, test and wafer fabrication facilities, we have the people, resources
and dedication to fill your design needs quickly, at competitive prices and
with the highest degree of reliability.
Design the name Standard Mlcrosystems Corporation Into your next project.
Our leading edge could provide just the competitive edge you need when
you take your product to market.

The laser cutter in SMC®'s Special Analysis Laboratory helps isolate small sections of
complex circuitry for investigation.
SMCI!> and COPLAMOS

Remote Terminal should be less than 14 f1s. If the response
is greater than 14 f1s. the response error bit is set in the
error register.

Error Detection Logic
The error detection logic of the COM1553B detects the
following errors:

Address Mismatch
An address mismatch occurs when a Bus Controller
detects a mismatch between the address of the Status Word
reply from a Remote Terminal and the Remote Terminal
address of the Command.

Improper Sync
One or more words have been received with incorrect
sync polarity (For example a Status Word with Data Sync).
Invalid Manchester II Code
One or more words have been received with a missing
transition during the 17 f1s. data and parity bit time.

Internal Register Description

Information Field Greater Than 16 Bits
The decoder has detected transition within one bit time
(1 f1s.) following the parity bit in one or more words.

Remote Terminal Address And Status Code Register
This register is loaded when the processor issues a load
Remote Terminal Address (RTA) command. The word that
is loaded in this register consists of 9 bits of status information (00-08) and the 5-bit address (011-015). The
Remote Terminal Address may be checked any time by
reading out the Error register. The RTA and Status Code
register must be loaded before the COM1553B may respond
as a Remote Terminal.
Table 1 defines the data bus bits which correspond to the
Remote Terminal Address and Status Code register and
Status Word that transmitted. Bits DO, 02, 03 and 08 are
double buffered to allow the RT to retain this information
after the Status Code register is updated. For all legal commands, other than Transmit Last Status and Transmit Last
Command Mode command, the Status Word register is
updated with these four bits, Any Error and the Broadcast
flag. The Dynamic Bus Control and Terminal Flag bits are
modified by the appropriate Mode Code commands
whereas, the Broadcast Flag and Any Error bits are set by
the COM1553B internal logic. The Reserved Bits and the
RT address bits are transferred directly into the Status Word
register during the RTA and Status Code command.
Bits DO, 02, 03, and 05-09 are cleared after transmission for all commands except Transmit Last Status and
Transmit Last Command Mode Code.

a

Odd Parity Error
One or more words have been received with a parity error.
Improper Word Count
An improper word count error occurs when the number
of Data Words received is not equal to the number of words
indicated in the word count field of the Command Word. In
the case of a Mode Code without data, no Data Words
should follow the Mode command. Mode Codes with data
should consist of only one Data Word. If the contents of the
word counter are not zero, and there is no contiguous Data
Word, them the receive message is considered incomplete
(e.g., fewer words were received than indicated by the word
count in the Command word). If the contents of the word
counter are zero and there is a transition detected 2 f1s. after
the parity transition of the last Data Word, then this also will
cause all improper word count. In either case, the Message
Error bit of the Status Word is set and not transmitted and
the invalid message (1M) ou~ pin pulsed at the same time
as the message complete (MC) signal output.
Response Time
The amount of time between the end of transmission of
a Command or Data Word and the Status Word reply by a

TABLE A:
COMMAND CONTROL CODE BIT DEFINITION

RT/BC 0 '5 0 ,• 0 '3 0 '2 0 "

DATA BITS
0 '0 0 9 DB 0 7 D. 0 5

X

X

X

X

X

X

X

X

X

X X

X

X

X

X

X

X

X

X

X

X

X X

X

X

X

X

X

X

X

X

X

X

X X

X

X

X

X

X

X

X

X

X

X

X

X

X

0

X

X

X

X

X

X

X

X

X

X

X

0

X

X

X

X

X

X

X

X

X

X

X

X-DON'T CARE

45

CONTROL
BITS
CB2-CBO
D. 0 3 O2 0 , Do FUNCTION
READ DATA
X X 1 1 X
REGISTER
LOAD RT ADDRESS
REGISTER AND
X X 1 0 X STATUS
CODE
REGISTER
X X 0 0 0 READ LAST CMD
READ ERROR AND
REMOTE TERMINAL
X X 0 0 1
ADDRESS
REGISTERS
BUS CONTROLLER
X X 0 1 0
TRANSMISSION
BUS CONTROLLER
X X 0 1 1 RT TO RT TRANSFER

TABLE 1
Data Bus Bit
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1

DO (LSB)

RTA and Status
Code Reg. Bits
RTA Bit 4 (MSB)
RTABit3
RTABit2
RTA Bit 1
RTA Bit 0 (LSB)
Not used
Instrumentation Bit
Service Request Bit
Reserved
Reserved
Reserved
Not Used
Busy
Subsystem Flag Bit
Dynamic Bus Control
Acceptance Enable Bit
(See Note)
Terminal Flag Enable
Bit (See Note)

Internal Logic
Signals

Any Error

-

Broadcast Flag

Dynamic Bus Mode Code
command
Inhibit Terminal Flag (set)
or
Override Terminal
Flag (reset)
Mode Code command

Status Word
Transmitted
RTA Bit 4 (MSB)
RTABit3
RTABit2
RTA Bit 1
RTA Bit 0 (LSB)
Message Error
Instrumentation
Service Request
Reserved
Reserved
Reserved
Broadcast Flag
Busy
Subsystem Flag
Dynamic Bus Control Bit

Terminal Flag

Note: When the Dynamic Bus Control Acceptance Enable bit is set, the RT will accept a Dynamic Bus Mode code
request. If this bit is reset the RT will reject a Dynamic Bus Mode Code command request. The Terminal Flag
Bit (if enabled) is only set high if no Inhibit Terminal Mode Code command has been received, or if an Override
Inhibit Terminal bit command is received.

Last Command Word Register
The last valid Command Word received by a Remote
Terminal is stored in an internal 16 bit Last Command Register. This makes it readily available for transmission onto
the data bus whenever the Remote Terminal receives a
Mode Command to transmit the last Command Word. The
Last Command Register contents are automatically written into external memory following a receive or a transmit
message.
As a bus controller (BC), the Last Command Register is
used to hold the command transmitted before the present
command. In RT -RT transfers this register of the BC holds
the receive command while the transmit command is being
transmitted.
The processor has the option of reading the Last Command Register of either a bus controller or remote terminal,
by issuing a Read Last Command Register command code.
Error Register And RTA Register
(Error Register)
A 7 -bit error register is provided in the COM 1553B to hold
any errors associated with the previous message. If one
or more of the 7 error types exists, the COM1553B asserts
the Invalid Message ~ut pin (1M) at the same time that
Message Complete (MC) is asserted, cueing either a Remote Terminal or a Bus Controller that an error occurred in
the previous message. If desired, the processor may read
out the 16-bit error word by issuing a read error register
command code. When operating as a Remote Terminal, the
COM1553B will write the Receive register, Error register and

Last Command register automatically into external memory
at the end of each command message because these registers may change before the processor has determined
the necessity of reading them. The Error register may be
read anytime during a message except during message
transfers.

TABLE 2
The 16-bit error word is defined as follows:
DATA BUS
LINE
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DO
'Unused bits are set high.
46

ERROR BIT
DEFINITION
RT Address Bit 4
RT Address Bit 3
RT Address Bit 2
RT Address Bit 1
RT Address Bit 0
Unused
Improper Sync
Address Mismatch Error
Improper Word Count
Response Time Error
Information Field> 16 Bits
Unused
Invalid Manchester II
Parity Error
Unused
Unused

Mode Detection Logic

The Override/lnhibit Terminal Flag and Dynamic Bus
Control Mode Code commands, when received by the
COM1553B, may change the state of the Terminal Flag and
Dynamic Bus Control bits of the Status Word register. The
Inhibit Terminal Flag Bit Mode Code command resets the
Terminal Flag bit.
The Override Inhibit Terminal Flag Mode Code command enables the Terminal Flag bit if it was previously disabled. Finally, Dynamic Bus Control Mode Code command
sets the Dynamic Bus Control bit in the Status Word if the
Dynamic Bus Control Enable bit is high. If the enable bit is
low, the Dynamic Bus Control bit in the Status Word remains
low when a Dynamic Bus Control Mode Code command is
received.

Both receive and transmit Command Words for a Remote
Terminal and Bus Controller are decoded by the Mode
Detection Logic. The Mode Detection Logic examines the
following Command Word field to establish the correct
operating mode for the COM1553B (Refer to TABLE B).
Subaddress/Mode Code Field (05-09)
and Data Word Count/Mode Code (00-04)
This field Determines if the command is a normal command or a Mode command. A subaddress field of 00000 or
11111 implies a Mode command. All other codes are interpreted as a subaddress. Once a Mode Command is
detected the most significant bit of the Data Word Countl
Mode Code field is decoded. A most significant bit of "zero"
implies no associated data with the Code Command. A
"one" in this position implies that a Data Word will follow.
The COM1553B recognizes five Mode Code commands
(Refer to TABLE B). Transmit Last Command or Transmit
Last Status word Mode Code commands, when received
by the COM1553B, will automatically transfer the contents
of the Transmit Last Command orTransmit Last Status register onto the 1553B serial bus.

Broadcast Mode Code
Bro~dcast Mode Code ~ommands are acknowledged if
the T/R bit is low. If the T/R bit is high all Broadcast Mode
Code commands without associated Data words are
acknowledged except Dynamic Bus Control and Transmit
Last Status Word.
'
Illegal Broadcast Commands are not acknowledged; the
1M output pin is, however, pulsed low.

TABLE B
MODE CODE DEFINITION
FUNCTION
Broadcast

Mode Codes

DETECT
CONDITION
All ones in RT
address field of
CMDWD
All zeros or
ones in subaddress field
ofCMDWD

DETECTED
BY
Broadcast
Decode Logic
Mode Code
Decode Logic

SPECIAL
CONDITIONS
Status word is
written into Memory
but not transmitted
MSB of Word Count
= No data Word
1 = With Data Word

o

(1) Dynamic
Bus
Control

Word Count
Field = 00000

(2) Transmit
Last
Status
Word
(3) Inhibit
Terminal
Flag Bit
(4) Override
Inhibit
Terminal
Flag Bit
(5) Transmit
Last
Command

Word Count
Field = 00010

Word Count
Field = 00110
Word Count
Field = 00111

Word Count
Field = 10010

47

COMMENTS
Address compare
must recognize all
ones as Broadcast
Word Count
is Decoded
as mode code
Dynamic Bus Accept
Bit of Status word
enabled for
transmission
Status Word remains
unchanged

Terminal Flag Bit of
Status word inhibited
until overriden
Removes Inhibit from
Terminal Flag Bit of
Status Word
Status Word
Transmitted followed
by Last Command
Register. Status Word
remains unchanged.

OPERATION
When operating as either a Bus Controller or Remote
Terminal, the COM1553B decodes the Command Word and
determines the type of message transfer. Having determined the type of message transfer, the COM1553B
generates the proper control and timing signals to complete the transfer (refer to Figure 2). The types of messages
are listed below:
.
1) Bus Controller to Remote Terminal
2) Remote Terminal to Bus Controller

3)
4)
5)
6)
7)
8)
9)
10)

Remote Terminal to Remote Terminal
Mode Code without Data Word
Mode Code with Data Word (transmit)
Mode Code with Data Word (receive)
Broadcast Bus Controller to Remote Terminal
Broadcast Remote Terminal to Remote Terminal
Broadcast Mode Code without data
Broadcast Mode Code with data

Bus Controller Transaction (RTIBC of the COM1553B set low)
prior to transmitting the Command Word.
The first memory cycle loads the Command Control Code
bits CB2-CBO from external memory into the COM1553B
functioning as Bus Controller (BC). The BC decodes this
command to determine the type of memory transaction to
perform (refer to TABLE A). The next read cycle loads the
Command Word into the BC command register and then
transmits it onto the 1553B bus. This Command Word, while
in the command register, determines the .Be mode of operation. The BC then completes this BC to RT transaction by
issuing a predetermined number of read cycles (determined by the value in the word count field of the Command
Word) and transmitting the data onto the 1553B bus. After
transmission of the last Data word, the BC initializes its
response timer, expecting a Status Word from the remote
terminal within 14 fLS.
After the reception of the Status Word, the BC initiates a
memory write cycle which writes the Status Word into the
external memory. If the BC doesn't receive the Status Word
within the allowed response time the message error bit
is set.

The following section describes each 1553B information
transfer format from the Bus Controller viewpoint. A table
showing external memory operation is also provided for
each message format.
Note that all MIL-STO-15538 serial bus activity is initiated by the Bus Controller.
Bus Controller-to-Remote Terminal Transfer (BC to RT)
This message format covers transactions where the Bus
Controller transmits a receive Command and Data Words
to a Remote Terminal. Initializing the COM1553B is accomplished by the processor loading an external memory
address counter with the starting address of the COM1553B
memory control block (address where the Command Control Code CB2-CBO resides). The Bus Controller processor
next issues a Command Strobe (CSTR) and holds it
low until the COM1553B issues a Command Strobe Acknowledge (CSTRA). The COM1553B then responds with a
Data Transfer Request (DTR) which initiates a normal
memory cycle.
Refer to figure i for timing associated with loading the
Command Control Codes (CB2-CBO) into the COM1553B

110

1.---1;.--------....., ~g'ZJ'rILr---------.'--_--',.......------

o
o

~D ------r-------~

o

R/'ii

LOW UNTIL DTACK

LOW UNTIL
SOON AFTER
D"i"iCi(

iiGiCK - - - - '

o

WE

~ -----~-_V

DATA BUS

_____

~~~;_---------<=~DA~T~A=>--------<
WORD

COMMAND WRITE TO MEMORY

DATA WRITE TO MEMORY

FIGURE2
48

DATA READ FROM MEMORY

TABLE 5
RTto RT

TABLE 3
BC to RT (The BC transmits a receive
command to the RT)
MEMORY
ADDRESS
1
2
3

··

34
35

MEMORY
CONTENTS
XXX2 H
RECEIVE
COMMAND
DATA
DATA
DATA
DATA
**
STATUS

COM1553B
MEMORY
OPERATION

I

MEMORY
ADDRESS

1
2

READ*
READ

3
READ
READ
READ
READ

4

..5

WRITE

*reads command control code bits CB2-CBO
** response time
X = don't care

36
37

Remote Terminal Transfer to Bus Controller
This message format covers transactions where the Bus
Controller sends a transmit command toa Remote Terminal
and requests data from it. Initialization of the BC for normal
memory cycles is the same as the previous transfer. The
difference between this transfer and the previous transfer
is that after the Command Word is transmitted, the BC waits
14 fJ,s for the Status Word and the requested number of Data
Words. The Status and Data Words are written into external
memory via write cycles as they are received by the BC.

1
2

3
4

··

35

MEMORY
CONTENTS
XXX2 H
TRANSMIT
COMMAND
**
STATUS
DATA
DATA
DATA
DATA

COM1553B
MEMORY
OPERATION

XXX3 H
RECEIVE
COMMAND
TRANSMIT
COMMAND

READ"
READ

STATUS
(transmitting
RT)
DATA
DATA
DATA
DATA

WRITE

**
STATUS
(receiving RT)

READ

WRITE
WRITE
WRITE
WRITE
WRITE

*reads command control code bits CB2-CBO
** response time
X = don'!'care
Mode Code Command without Data
The Bus Controller transmits a specific Mode Command
and expects a Status Word back from the addressed
Remote Terminal.

TABLE 6

TABLE 4
BC to RT (The BC transmits a Transmit
Command to an RT)
MEMORY
ADDRESS

MEMORY
CONTENTS

MEMORY
ADDRESS

1
2

COM1553B
MEMORY
OPERATION

3

READ*
READ

MEMORY
CONTENTS
XXX2 H
COMMAND
**
STATUS

COM1553B
MEMORY
OPERATION
READ"
READ
WRITE

*reads command control code bits CB2-CBO
*.*response time
X = don't care
Mode Command with Data
(BC receives a single word)
In this mode the Bus Controller issues a transmit Mode
Command to an RT. The addressed Terminal responds to
the Bus Controller with aStatus Word and a single Data
Word.

WRITE
WRITE
WRITE
WRITE
WRITE

*reads command control code bits CB2-CBO
**response time
X = don't care

TABLE 7
MEMORY
ADDRESS

RT-to-RT Transfer
In this message format, the Bus Controller first issues a
receive Command Word to the receiving Remote Terminal,
followed by a transmit Command Word to the transmitting
terminal. Next, the transmitting RT responds with a Status
Word and the requested number of Data Words to both the
receiving RT and BC. The receiving RT at the end of the
message sends a Status Word to the BC. As Status and
Data Words are received by the BC they are written into
external memory.

MEMORY
CONTENTS

COM1553B
MEMORY
OPERATION

READ*
XXX2 H
COMMAND
READ
**
WRITE
3
STATUS
4
DATA
WRITE
*reads command control code bits CB2-CBO
**response time
X = don't care
1
2

49

Mode Command with Data
(BC transmits a single word)
The Bus Controller issues a receive Mode Command and
one Data Wqrd to a Remote Terminal. A Status Word is
returned by the Remote Terminal to the Bus Controller.

RT to RT Transfer (Broadcast)
This transfer is similar to the normal RT to RT transfer
with the exception that the Status Word is not returned by
the receiving RT.

TABLE 8

TABLE 10

MEMORY
ADDRESS
1
2
3

MEMORY
CONTENTS
XXX2 H
COMMAND
.DATA
**
STATUS

4

COM1553B
MEMORY
OPERATION

MEMORY
ADDRESS
1
2

READ'
READ
READ

3
WRITE

'reads command control code bits CB2-CBO
"response time
X = don't care

4
5

..

MEMORY
CONTENTS
XXX3 H
RECEIVE
COMMAND
TRANSMIT
COMMAND
**
STATUS
DATA
DATA
DATA
DATA

COM1553B
MEMORY
OPERATION
READ'
READ
READ
WRITE
WRITE
WRITE
WRITE
WRITE

Bus Controller (Broadcast) to Remote Terminal Transfer
36
In this mode the Bus Controller issues a Broadcast Com'reads command control code bits CB2-CBO
mand followed by a number of Data Words. In all Broadcast
Command transfers a BC will not expect to receive a Status . **responsetime
X = don't care
Word back.

TABLE 9
MEMORY
ADDRESS
1
2

..
3

34

MEMORY
CONTENTS
XXX2 H
RECEIVE
COMMAND
DATA
DATA
DATA
DATA

THE FOLLOWING NOTE APPLIES TO THE CURRENT
VERSION OF THE COM 1553B:
When operating as a Bus Controller in a RT (Remote
Terminal) to RT transfer, the COM1553B may incorrectly set
the Invalid Sync Bit in the Error Register if the status word
response from the receiving RT occurs between 4 and 7
microseconds.
The Bus Controller (BC) may confirm that an error free
message transmission occurred by requesting that the
receiving RT transmit the last status word. If this status word
matches the previous status word, then an error-free trans-·
mission occurred.

COM1553B
MEMORY
OPERATION
READ'
READ
READ
READ
READ
READ

'reads command control code bits CB2-CBO
**response time
X = don't care

Remote Terminal Transaction (RT/BC input of the COM1553B set high)
The following section addresses each COM1553B
information transfer format from the Remote Terminal
viewpoint.

The Subaddress field is thereafter decoded by external
logic and the Command word is written into external
memory. The RTthen receives a predetermined number of
Data Words (specified by the word count field). As each Data
Word is received it is written into external memory. After the
reception of the last Data Word the RT transmits the Status
Word, the Message Error, Broadcast Flag, Terminal Flag,
Subsystem Flag, Busy, and Service Request bits are
updated for all commands except for the Transmit Status
Word and Transmit Last Command Code commands. While
transmitting the Status, the RT writes it into memory. The
RT also writes the Last Command Register, Error Register
and Receive Register into memory and then asserts Message complete.
Note that the receive register of the RT will contain the
transmitted Status Word.

Bus Controller to Remote Terminal Transfer
(BC to RT, where RT receives data)
In this transfer the COM1553B designated as the RT
receives a command to receive data. As the Command
Word is completely shifted into the receive shift register, the
RT compares the Command Word address field with the
preloaded Remote Terminal address. This determines if the
message is addressed to the receiving RT. If the Command
Word is valid, the RT issues a Data Transfer Request (DTR)
to initiate a memory cycle. Once the processor relinquishes
control of the data bus, during the Bus Acknowledge
(BGACK) time, the Command Word is placed on the data
bus.

50

TABLE 11
BC TO RT (RT receives data from BC)
MEMORY
ADDRESS
1
2
3

··

34

35
36
37
38

MEMORY
CONTENTS
COMMAND
DATA
DATA

..

DATA
**
STATUS
LAST
COMMAND
ERROR
REGISTER
RECEIVE
REGISTER

COM1553B
MEMORY
OPERATION
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE

transfers. The only exception is that the receiving terminal
waits for the first Data Word from the transmitting terminal.
This satisfies the protocol requirement that the transmitting
terminal first send its status to the controller before it transmits the data to the receiving terminal.

Mode Command with Data
(RT receives a Mode Code Command to transmit)
In this transfer, after the Transmit Mode Command is
received, the RT transmits the Status and one Data Word.

TABLE 13

WRITE
WRITE
WRITE

MEMORY
ADDRESS

WRITE

1

2
3
4

Remote Terminal-to-Bus Controller Transfer
(RT transmits data to BC)
The Remote Terminal receives a Transmit Command
Word from the Bus Controller. The RT will then proceed to
decode the Command Word, as in the previous case and
within the response time transmits the Status Word.
While the Status Word is being transmitted the RT issues
a write memory cycle to write the Status Word into external
memory. Thereafter, the Data words are read from memory
and transmitted. After the last word is transmitted the RT
writes the contents of the Last Command Register, Error
Register and the Receive Register into memory.

5
6

MEMORY
CONTENTS
COMMAND
**
STATUS
DATA
LAST
COMMAND
ERROR
REGISTER
RECEIVE
REGISTER

COM1553B
MEMORY
OPERATION
WRITE
WRITE
READ*
WRITE
WRITE
WRITE

*For a Transmit Last command Mode Code, Data is not
read from memory but transmitted from the internal Last
Command register.
** response time

Mode Code Command with Data
(RT receives a Mode Command to receive)
This transfer is similar to a Receive Command having only
one Data Word.

TABLE 12
Remote Terminal to Bus Controller
(RT Transmits Data to BC)
MEMORY
ADDRESS
1

2
3

··

34
35
36
37

MEMORY
CONTENTS
COMMAND
**
STATUS
DATA
DATA
DATA
DATA
LAST
COMMAND
ERROR
REGISTER
RECEIVE
REGISTER

COM1553B
MEMORY
OPERATION

TABLE 14
MEMORY
ADDRESS

WRITE
WRITE
READ
READ
READ
READ
WRITE

1

2
3
4

5

WRITE

6

WRITE

**'response time

MEMORY
CONTENTS
COMMAND
DATA
**
STATUS
LAST
COMMAND
ERROR
REGISTER
RECEIVE
REGISTER

COM1553B
MEMORY
OPERATION
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE

** response time

Bus Controller Broadcast Transfer to RT
Remote Terminal-to-Remote Terminal Transfers

The RT receives a Broadcast Command to receive data.
If data received during a broadcast message is invalid, the
COM1553B will set the message error bit.

From the Remote Terminal viewpoint, RT-to-RT transfers are similar to the RT to BC receive or transmit data
51

Broadcast Mode Code Command Without Data
This Mode Code command is detected if the MSB of
the word count field is zero. This transaction is the same as
the previous transfer except that there is no Data Word
trans.fer.

TABLE 15
RT RECEIVE
MEMORY
ADDRESS
1
2

..
32
33
34
35

MEMORY
CONTENTS
COMMAND
DATA
DATA
DATA
DATA
STATUS
LAST
COMMAND
ERROR
REGISTER

COM1553B
MEMORY
OPERATION
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE'
WRITE

TABLE 17
MEMORY
ADDRESS
1
2
3

WRITE

'In all broadcast transfers, a memory cycle is shown for the
Status Word but the RT does not transmit it on the 1553B
bus.

4

1
2
3
4
5

COMMAND
DATA
STATUS
LAST
COMMAND
ERROR
REGISTER

WRITE
WRITE'
WRITE
WRITE

Broadcast RT to RT Transfer
For this message transfer a Broadcast Command
to receive is issued by the Bus Controller. This is followed
by a normal Transmit Command to the transmitting Remote Terminal. The Remote Terminal responds with a normal transmit message format of Status Word and Data
Word(s). The receiving terminals do not transmit a Status
Word after receiving the data. However, they do go through
a memory cycle to load the Status Word into their respective memories.
For the Remote Terminal receive transfer refer to Table
15. The only difference in this transfer is that there is a gap
time between the Command and Data word.
For the Remote Terminal transmit transfer refer to Table
12. The only difference in this transfer is that the Receive
Register is not written into memory.

TABLE 16
RT RECEIVE
MEMORY
CONTENTS

COMMAND
STATUS
LAST
COMMAND
ERROR
REGISTER

COM1553B
MEMORY
OPERATION

'In all broadcast transfers, a memory cycle is shown for
the Status Word but the RT does not transmit it on the
1553B bus.

Broadcast Mode Code Command with Data
This Broadcast Mode Code command is detected if the
MSB of the word count field is a logical high.
Transmission of the Status Word is suppressed as in the
previous case but is loaded into external memory.

MEMORY
ADDRESS

MEMORY
CONTENTS

COM1553B
MEMORY
OPERATION
WRITE
WRITE
WRITE'
WRITE
WRITE

'In all broadcast transfers, a memory cycle is shown for
the Status Word but the RT does not transmit it on the
1553B bus.

52

MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range......
...................................... ........ - 55 to + 125°C
. ........ - 55 to + 150°C
Storage Temperature Range.................................................................
Lead Temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. ............... + 325°C
Positive Voltage on any pin ............................................................................................. + 15V
Negative Voltage on any pin except VBB, with respect to ground .......
. .......................................... - .3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is
suggested that a clamp circuit be used.

DC ELECTRICAL CHARACTERISTICS TA
PARAMETER

VIL
V'H
VOL
VOH
IL
C"
Co
CL
Pw

Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Leakage Current
Input CapaCitance
Output Capacitance
Load Capacitance
Power Dissipation

MIN
-0.3
3
2.4

= -

55 to 125°C, Vee
TVP

=

MAX

40
100
5

UNITS
V
V
V
V
j1.A
pf
pf
pf
W
mA
mA
mA

MAX

UNITS

0.8
Vee
0.4
5
10
25
15
150

4
10
10
100
0.8

IDD

Icc

IBB

5.0V ± 5%, Voo

=

12V ± 5%, V BB

= -

5V ± 5%

COMMENTS

IOL = -3.2 mA
10H = .8mA

AC ELECTRICAL CHARACTERISTICS

clk
t,
tf
t,
t2
t3
t,
t,
t,
t7
tB
t9
t"
t"
t"
t"
t'4
t"
t"
t"
t"
t"
t20

t"
t"
t23
t24
t25
t26

PARAMETER
clock frequency
Clk, rise time
Clk, fall time
DTRandWE
BGACK to DTR
WEtoDATA
DTACK to WE
DTACK to R/W
DTACK to C/O
CSTR to CSTRA
CSTRA to CSTR
CSTRA width
C/O to DATA
CMDto 1M
1M width
VCwidth
VCto 1M
C/OtoMC
C/O to 1M
C/OtoMC
C/OtoMC
CMD to MCF reset
CMD to MCF set
CMDtoVC
C/O to MCF reset
C/O to MCF set
paR width
Receive CMD to DTR
Transmit CMD to DTR

MIN

TVP

0.5
0.8
50

12
6
6
0.6
1.3
100
1.5
1
1.5

o

1
2
2
1.5
2.5
673
1.5

500
3.25
500
1
1.75
700
2.25
750
1.25
3.75
4.75
2.75
1.5
1

2.5
4.25
5.75

53

MHz
ns
ns
j1.S
j1.s
ns
j1.S
j1.S
j1.S
j1.s
j1.s
ns
j1.S
ns
j1.s
j1.s
ns
j1.S
ns
j1.S
j1.S
j1.S
j1.S
j1.s
j1.s
j1.s
j1.s
j1.S

COMMENTS
50% duty cycle

FIGURE 3:
RECEIVER LOGIC WAVEFORMS
,

1

I

I

0

I

MANIN

FIGURE 5:
CONTIGUOUS WORD
1
!-PARITY

"I_

-II

SYNC - -....

I

LINE TO LINE

DTR VS COMMAND WORD
RECEIVE ......,--t---r-y-~
CMD
L..1,.....I_ _t-_-L..I,.....
sl,-19....
I-;--IpI
WD
I-IH--\

LINE TO LINE

'--_. . . I

L

DTR

I

MANOUT

lrf\Ji
I

I

I

I

I

I

OVERLAP I.,

= 10 ns TYP.

FIGURE 4:
DRIVER LOGIC WAVEFORMS
MODE CODE FLAG (MCF)
ASART

C:~D:D L..ll~I_ _ _f-l_ _....-Lll,-sL.;.119;;.t.I..,....pI

111

:NEXTCMDI'SI'9Ip I

I - - I.. ---I;-_ _-f-_ _ _---=.'___...;;;.I,_-;"I

MCF
VC

_____________________~I

L-

f

____________r_~':h~~_______
ASABC
I - CDMMAND WORD - I

' - - - -3 BIT CDMMAND CONTRDL CODE-----,
..------READ FRDM MEMORY
- I

C/O

1~

________________~1
-I

I

READ FROM MEMORY

~
I"

r--__________________
--l

POR

AFTER POWER IS
STABLE

54

I

__________~r--

~I

MCF

.

In

I-

~r_

AC CHARACTERISTICS

B G A C K - - -_____

t-'--____
:

BGACK

DTR~

I

' - ' , .-l

-----"""\)~I________

DTR _ _ _ _ _I_~~

I

1-,,-11

I

DTACK _ _ _ _ _ _ _,

'1-._-,

l-',~

,

M---;I--------~~~ ~,,~/

I

DATA

I

Iii

I

I-',-{

I

----!-I---------«,---ti---~>C
I

R/W~

I
I

r-

I

II r-

I

l---"~(i"

c/o

~~t10-

:

I

(

DATA

I

I

;l--

i~----------+L.-".J-J,

OTACK

I

CSTR _ _ _ _ _ _ _ _

I

~

iI
I

J-"~

I

I

C-ST-RA

I

t--"..y-

I

I

r-

C/D~I

I

~

-----''-'----LJr--I

_______-,1-"".,I
I

IL______

DTR

READ CYCLE

WRITE CYCLE

IA

-~

CONTROL

DMA
CONTROLLER

TRANSCEIVERI
TRANSFORMER "I~'---"'r"l
COM1553B

~

A

DMA
MEMORY

•

ilL-

TYPICAL SYSTEM IMPLEMENTATION

55

"

~DRr-v

JJ.
L...-_ _'\I"

•

M68000
MICROPROCESSOR
SYSTEM

MESSAGE COMPLETE (MC)
ASART

INVALID MESSAGE (1M)
ASART
CASE 1
CMD WD

CASE 1 AT THE COMPLETION OF AN ERROR FREE BRO~D­
CAST COMMAND TRANSACTION AFTER THE
ERROR REGISTER IS WRITTEN INTO MEMORY.

L.ll...I_-t_ _ _L-11S...I.c.;19CIL...
pI
1-1,,--1

~

1

1M

C/O

-IITHE T/R BIT IN THE BROADCAST
CMD IS SET HIGH.

CASE 2

BROADCAST WD

L.ll...I'--_+-__-Lll"'SLll"'91...,pr:;!1

MC

I"

- I tI"

I"

,,-1 I------------~~
I
rL----------------~r~,,~·i
1 -1

VC
1M

C/O
1M
MC

CASE 2 AT THE COMPLETION OF A TRANSMIT OR RECEIVE
COMMAND TRANSACTION AFTER THE DATA REGIST.ER IS WRITTEN INTO MEMORY.

C/O
MC

I

~n~

______

CASE 3 WHEN THE BC ISSUES A RECEIVE COMMAND,THE
MC SIGNAL OCCURS AFTER THE STATUS WORD IS
WRITTEN INTO MEMORY.
OR
WHEN THE BC ISSUES A TRANSMIT COMMAND,
THE MC SIGNAL OCCURS AFTER THE LAST DATA
WORD IS WRITTEN INTO MEMORY.

__________-!'
1.... 11fL--------IIf-'1
I"

____________-wl~

-ll-

C/O

I"

CASE 4

_________
ASABC

AN ERROR OCCURReD DURING
A BROADCAST CMD

CASE 3

--1 ,,1-

'
__________~n~
___

MC

NON BROADCAST CMD

I

: f1---------------,If--.~.I
I"

C/O
1M
MC

CASE 5

ASABCOR RT

-------'~

CASE 4 AT THE COMPLETION OF LOADING THE RT
ADDRESS REGISTER OR
READING THE DATA REGISTER.

------------'~
ASABC

C/O

A TRANSMIT OR RECEIVE BC TRANSFER

MC

_ _ _ _ _ _ _ _ _ _----J~

C/O
1M

------------~~~
1-1"-1

MC

--------------~~

CASE 5 AFTER READING THE ERROR REGISTER.

C/O

-l

MC

I"

NOTE: Message complete and invalid message outputs.Q!.
the COM 15538 are negative pulses i.e. MC and 1M.

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

56

I-

------------~~

COM1671
J.L PC FAMILY

Asynchronous/Synchronous Transmitter-Receiver

ASTRO
FEATURES
SYNCHRONOUS AND
ASYNCHRONOUS
Full Duplex Operations
o SYNCHRONOUS MODE
Selectable 5-8 Bit Characters
Two Successive, SYN Characters Sets
Synchronization
Programmable SYN and DLE Character
Stripping
Programmable SYN and DLE-SYN Fill
o ASYNCHRONOUS MODE
Selectable 5-8 Bit Characters
Line Break Detection and Generation
1-, 1V2-, or 2-Stop Bit Selection
Start Bit Verification
Automatic Serial Echo Mode
o BAUD RATE-DC TO 1M BAUD
o 8 SELECTABLE CLOCK RATES
Accepts 1X Clock and Up To 4 Different
32X Baud Rate Clock Inputs
Up to 47% Distortion Allowance With 32X
Clock
o SYSTEM COMPATIBILITY
Double Buffering of Data
8-Bit Bi-Directional Bus For Data, Status,
and Control Words
All Inputs and Outputs TTL Compatible
Up To 32 ASTROS Can Be Addressed
On Bus
On-Line Diagnostic Capability
o ERROR DETECTION
Parity, Overrun and Framing

PIN CONFIGURATION

o

Voo

FiE
CA
IACKO

RPLY
INTR

iill0
0AI:3

R4
R3
R2
R1

DAL4
OAL5

cc (OS"R)

DAL1
OAL2

I5:iil
OAL7

("Oi'I!)

CD
il57

(~) CE
MISC
(V,,)GNO

o
o
o

(1rnl)

BA (TSO)
Cii (r:T5)
DB (lXTC)
DO (lXRC)

CF (CARR)

BB (ASI)
103
104
105
MR
106
Vee

COPLAMOS® n-Channel Silicon
Gate Technology
Pin for Pin replacement for
Western Digital UC1671 and
National INS 1671
Baud Rate Clocks Generated by
COM5036 @ 1X and
COM5016-6@ 32X
APPLICATIONS
Synchronous Communications
Asynchronous Communications
Serial/Parallel Communications

General Description
The COM1671 (ASTRO) is a MOS/LSI device which performs the functions of interfacing a serial data communication
channel to a parallel digital system. The device is capable of full duplex communications (receiving and transmitting) with
synchronous or asynchronous systems. The ASTRO is designed to operate on a multiplexed bus with other bus-oriented
devices. Its operation is programmed by a processor or controller via the bus and all parallel data transfers with these
machines are accomplished over the bus lines,
The ASTRO contains several "handshaking" signals to insure easy interfacing with modems or other peripheral devices
such as display terminals. In addition, a programmable diagnostic mode allows the selection of an internal looping feature
which allows the device to be internally connected for processor testing.
The COM1671 provides the system communication designer with a software responsive device capable of handling
complex communication formats in a variety of system applications,

57

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.

STANDARD MICROSVSTEMS Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
ATlnll.1
applications: consequently complete information sufficient for construction purposes is not necessarily giveh.
CORPOR,",IIVI"
The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
",,,,,,",," 0,"""",", "'" assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
"'"' m "00 . ;w, '00 no"" semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve deSign and supply the best product possible.

58

COM 1863
COM 8018
j1PC FAMILY

Universal Asynchronous Receiver/Transmitter
UART
PIN CONFIGURATION
FEATURES

Voo

o Compatible with TR1863 timing
o High accuracy 32X clock mode: 48.4375% Receiver Distortion
o
o
o
o

'HIACC
Gnd

RITE

Immunity and improved RDA/ROR operation (COM 8018 only)
High Speed Operation-62.5K baud, 200ns strobes
Single +5V Power Supply
Direct TTL Compatibility-no interfacing circuits required
Input pull-up options: COM 8018 has low current pull-up
resistors; COM 1863 has no pull up resistors

AD8
RD?
RD6
RDS
RD4
RD3
RD2
RDl
RPE
RFE
ROR
SWE
RCP
RDAR
RDA
RS!

o Full or Half Duplex Operation'-can receive and transmit
simultaneously at different baud rates

o Fully Double Buffered-eliminates need for precise external
timing

o Improved Start Bit Verification-decreases error rate
046.875% Receiver Distortion Immunity
o Fully Programmable-data word length; parity mode; number
of stop bits: one, one and one-half, or two
o Master Reset-Resets all status outputs and Receiver Buffer
Register
I;J Three State Outputs-bus structure oriented
Low Power-minimum power requirements
Input Protected-eliminates handling problems
o Ceramic or Plastic DIP Package-easy board insertion
Baud Rates available from SMC's COM 8046, COM 8116,
COM 8126, COM 8136, COM 8146 baud rate generators

ffiS
TBMT
MR

PACKAGE: 40-Pin D.I.P.

FUNCTIONAL BLOCK DIAGRAM

o
o
o

TCP
POE
NDBl
NDB2
NSB
NPB
CS'
TD8
TD?
TD6
TDS
TD4
TD3
TD2
TDl
TSO
TEOC

TDl TD2 TD3 TD4 TDS TD6 TD? TD8

TDS

TSO

GENERAL DESCRIPTION

TCP

The Universal Asynchronous Receiver/Transmitter is an
MaS/LSI monol ithic circuit that performs all the receiving and
transmitting functions associated with asynchronous data
communications. This circuit is fabricated using SMC's
patented COPLAMOS® technQlogy and employs depletion
mode loads, allowing operation from a Single +5V supply. The
duplex mode, baud rate, data word length, parity mode, and
number of stop bits are independently programmable through
the use of external controls. There may be 5,6,7, or 8 data
bits, odd/even or no parity, and 1 or 2 stop bits or 1.5 stop bits
when utilizing a 5-bit code. These programmable features
provide the user with the ability to interface with all
asynchronous peripherals.

CS
NPB
NSB
NDB2
NDBl
POE

TEOC
SWE
TBMT
APE
AFE
ROA
ADA
RDAR

MR

voo

f - -......;-i HIACC'
Gnd

*If pin 2 is taken to a logic 1 the COM 8018 will operate in a high
accuracy mode. If pin 2 is connected to -12V, GND, a valid logic
zero, or left unconnected, the high accuracy feature is disabled,
and the UART will operate in a 16X clock mode. Pin 2 is not connected on the COM 1863.

59

ADE

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
IIPPlications: consequently complete information sufficient for construction purposes is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsitillity is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the best product possible.

60

COM 2651
ILPC FAMilY

Programmable Communication Interface
PCI
FEATURES

PIN CONFIGURATION

o Synchronous and Asynchronous Full Duplex or

Half Duplex Operations
ORe-programmable ROM on-chip baud
rate generator
.Synchronous Mode Capabilities
- Selectable 5 to a-Bit Characters
- Selectable 1 or 2 SYNC Characters
-Internal Character Synchronization
- Transparent or Non-Transparent Mode
-Automatic SYNC or DLE-SYNC Insertion
- SYNC or DLE Stripping
- Odd, Even, or No Parity
- Local or remote maintenance loop back mode
Asynchronous Mode Capabilities
- Selectable 5 to a-Bit Characters
- 3 Selectable Clock Rates (1 X, 16X, 64X the
Baud Rate)
- Line Break Detection and Generation
-1, 1'h, or 2-Stop Bit Detection and Generation
- False Start Bit Detection
- Odd, Even, or No Parity
- Parity, Overrun, and framing error detect
- Local or remote maintenance loop back mode
- Automatic serial echo mode
Baud Rates
- DC to 1.OM Baud (Synchronous)
- DC to 1.OM Baud (1 X, Asynchronous)
- DC to 62.5K Baud (16X, Asynchronous)
- DC to 15.625K Baud (64X, Asynchronous)
Double Buffering of Data

o

02 1

2801

03 2

27 DO

RxO 3

26 Vee

GNO 4

25RxC

04 5

240TR

05 6

23RTS

06 7

220SR

07 8

21 RESET

TxC 9

20BRCLK

A110

o

19TxO

CE11

18 TxEMT/OSCHG

A012

17CTS
16DCO
15TxROY

R/W13

RxROY 14

Package: 28-pin O.I.P.

o Internal or External Baud Rate Clock
-16 Internal Rates:50 to 19,200 Baud
o Single +5 volt Power Supply
o TTL Compatible
o No System Clock Required
o Compatible with 2651, INS2651

o

o

GENERAL DESCRIPTION
The COM 2651 is an MaS/LSI device fabricated
Asynchronous Receiver/Transmitter (USART)
using SMC's patented COPLAMOS® technology
designed for microcomputer system data comthat meets the majority of asynchronous and
munications. The USART is used as a peripheral
synchronous data communication requirements,
and is programmed by the processor to comby interfacing parallel digital systems to asynmunicate in commonly used asynchronous and
chronous and synchronous data communication
synchronous serial data transmission techniques
channels while requiring a minimum of processor
including IBM Bi-Sync. The USART receives serial
data streams and converts them into parallel data
overhead. The COM 2651 contains a baud rate
generator which can be programmed to either
characters for the processor. While receiving serial
accept an external clock or to generate internal
data, the USART will also accept data characters
transmit or receive clocks. Sixteen different baud
from the processor in parallel format, convert them
to serial format and transmit. The USART will sigrates can be selected under program control when
operating in the internal clock mode. The on-chip
nal the processor when it has completely received
baud rate generator can be ROM reprogrammed to
or transmitted a character and requires service.
accommodate different baud rates and different
Complete USART status including data format
starting frequencies.
errors and control signals is available to the
processor at any time.
The COM 2651 is a Universal Synchronous/

61

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.

STANDARD MICROSYSTEMS Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor

1\'T'II'\lI,1
CORPORMIIVI't

applications: consequently complete information sufficient for construction purposes is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However. no responsibility is
"",,"''''' "'""""''' """ assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
"'" ",·"00 . 'W,""""""" semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the best product possible.

62

COM 2661-1
COM 2661-2
COM 2661-3
IlPC FAMILY

Enhanced Programmable
Communication Interface
EPCI
FEATURES

PIN CONFIGURATION

o Synchronous and Asynchronous Full Duplex or

Half Duplex Operations
ORe-programmable ROM on-chip baud
rate generator
o Synchronous Mode Gapabilities
-Selectable 5 to 8-Bit Characters
-Selectable 1 or 2 SYNC Characters
-Internal or External Character Synchronization
- Transparent or Non-Transparent Mode
- Transparent mode DLE stuffing (Tx)
and detection (Rx)
-Automatic SYNC or DLE-SYNC Insertion
-SYNC, DLE and DLE-SYNC stripping
-Odd, Even, or No Parity
-Local or remote maintenance loop back mode
Asynchronous Mode Capabilities
-Selectable 5 to 8-Bit Characters plus parity
-3 Selectable Clock Rates (1X, 16X, 64X the
Baud Rate)
-Line Break Detection and Generation
-1,1'12, or 2-Stop Bit Detection and Generation
-False Start Bit Detection
-Odd, Even, or No Parity
-Parity, Overrun, and framing error detect
- Local or remote maintenance loop back mode
-Automatic serial echo mode (echoplex)
o Baud Rates
-DC to 1.0M Baud (Synchronous)
-DC to lOM Baud (1X, Asynchronous)
-DC to 62.5K Baud (16X, Asynchronous)
-DC to 15.625K Baud (64X, Asynchronous)

D2 1

28D1

D3 2

27DO

RxD 3

26 Vee
25 RXC/BKDET

GND 4

o

D4 5

24DTR

D5 6

23RTS

D6 7

22DSR

D7 8

21 RESET

TxC/XSYNC 9
A110

20BRCLK
19TxD

CE11

18 TxEMT/DSCHG

A012

17CTS

R/W13

16DCD

RxRDY 14

15TxRDY
Package: 28-pin D.I.P.

o Double Buffering of Data
o RxC and TxC pins are short circuit protected
o Internal or External Baud Rate Clock
03 baud rate sets (2661-1, -2, -3)
o 16 internal rates for each version
o Single +5 volt Power Supply
o TTL Compatible
o No System Clock Required
o Compatible with EPCI 2661

GENERAL DESCRIPTION

The COM 2661 is an MaS/LSI device fabricated
using SMC's patented COPLAMOS® technology.
It is an enhanced pin and register compatible
version of the COM 2651 that meets the majority of
asynchronous and synchronous data communication requirements, by interfacing parallel digital
systems to asynchronous and synchronous data
communication channels while requiring a minimum of processor overhead. The COM2661
contains a baud rate generator which can be
programmed to either accept an external clock or
to generate internal transmit or receive clocks.
Sixteen different baud rates can be selected under
program control when operating in the internal
clock mode. Each version of the COM 2661 (-1,
-2, -3) has a different set of baud rates. Custom
baud rates can be ROM reprogrammed to accommodate different baud rates and different starting
frequencies.

The COM 2661 is a Universal Synchronous/
Asynchronous Receiver/Transmitter (USART)
designed for microcomputer system data communications. The USART is used as a peripheral
and is programmed by the processor to communicate in commonly used asynchronous and
synchronous serial data transmission techniques
including IBM Bi-Sync. The USART receives serial
data streams and converts them into parallel data
characters for the processor. While receiving serial
data, the USART will also accept data characters
from the processor in parallel format, convertthem
to serial format and transmit. The USART will signal the processor when it has completely received
or transmitted a character and requires service.
Complete USART status including data format
errors and control signals is available to the
processor at any time.

63

For additional information, consult your 1986 catalog or contact our product marketing department at (516) 273-3100.
o:::"'I-I\."n'I\.~n MIIO~S'fS1'E'1IIS

•

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
• • • • • applications: consequen~y complete infonnation sufficient for construction purposes is not necessarily given.
The infonnatiOn has been carefully checked and is believed to be entirely reliable. However, no responsibility is
"'"!l:"~ """M assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
, •. "'0;''''! semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the best product possible.

64

COM 5025
jLPCFAMILY

Multi-Protocol
Universal Synchronous Receiver/Transmitter
USYNR/T
PIN CONFIGURATION

FEATURES
D
D
D
D
D
D
D

Selectable Protocol-Bit or Byte oriented
Direct TTL Compatibility
Three-state Input/Output BUS
Processor Compatible-8 or 16 bit
High Speed Operation-1.5 M Baud-typical
Fully Double Buffered-Data, Status, and Control Registers
Full or Half Duplex Operation-independent Transmitter and
Receiver Clocks
-individually selectable data
length for Receiver and
Transmitter
D Master Reset-resets all Data, Status, and Control Registers
D Maintenance Select-built-in self checking

MSEL
ACP

TCP

rso
TXENA
RXACT
RDA

TSA
TBMT
TXACT
MR

GND

Vee

DB"a

DBI2I~

DB~9

OB~1

DBH!I

OB02
OB~3

DB04

0813

OB¢5
OB06
OB0 7
DPENA
BYTE OP
A¢

PACKAGE 40-Pin D.I.P

BIT ORIENTED PROTOCOLS-SDLC, HDLC, ADCCP
D Automatic bit stuffing and stripping
D Automatic frame character detection and generation
D Valid message protection-a valid received message is
protected from overrun
D Residue Handling-for messages which terminate with a
partial data byte, the number of valid
data bits is available

BYTE ORIENTED PROTOCOLS-BiSync, DDCMP
D Automatic detection and generation of SYNC characters
SELECTABLE OPTIONS:
D Variable Length Data-1 to 8 bit bytes
D Variable SYNC character-5, 6, 7, or 8 bits
D Error Checking-CRC (CRC16, CCITT-O, or CCITT-1)
-VRC (odd/even parity)
-None
D Strip Sync-deletion of leading SYNC characters after
synchronization
D !dle Mode-idle SYNC characters or MARK the line

SELECTABLE OPTIONS:
D Variable Length Data-1 to 8 bit bytes
D Error Checking-CRC (CRC16, CCITT-O, or CCITT-1)
-None
D Primary or Secondary Station Address Mode
D All Parties Address-APA
D Extendable Address Field-to any number of bytes
D Extendable Control Field-to 2 bytes
D Idle Mode-idle FLAG characters or MARK the line
D Point to Point, Multi-drop, or Loop Configuration

APPLICATIONS
D Intelligent Terminals

D Remote Data Concentractors

D Line Controllers

D Communication Test Equipment

D Network Processors

D Computer to Computer Links
D Hard Disk Data Handler

D Front End Communications
65

General Description
The COM 5025 is a COPLAMOS® n channel silicon gate MOS/LSI device that meets the majority of
synchronous communications requirements, by interfacing parallel digital systems to synchronous serial
data communication channels while requiring a minimum of controller overhead.
The COM 5025 is well suited for applications such as computer to modem interfaces, computer to computer
serial links and in terminal applications. Since higher level decisions and responses are made or initiated by the
controller, some degree of intelligence in each controller of the device is necessary.
Newly emerging protocols such as SOLC, HOLC, and AOCCP will be able to utilize the COM 5025 with a
high degree of efficiency as zero insertion for transmission and zero deletion for reception are done
automatically. These protocols will be referred to as Bit Oriented Protocols (BOP). Any differences between
them will be discussed in their respective sections. Conventional synchronous protocols that are control
character oriented such as BISYNC can also utilize this device. Control Character oriented protocols will be
referred to as CCP protocols. Other types of protocols that operate on a byte or character count basis can
also utilize the COM 5025 with a high degree of efficiency in most cases. These protocols, such as OOCMP
will also be referred to as CCP protocols.
The COM 5025 is designed to operate in a synchronous communications system where some external
source is expected to provide the necessary received serial data, and all clock signals properly
synchronized according to EIA standard RS334. The external controller of the chip will provide the
necessary control signals, intelligence in interpreting control signals from the device and data to be
transmitted in accord with RS334.
The receiver and transmitter are as symmetrical as possible without loss of efficiency. The controller of the
device will be responsible for all higher level decisions and interpretation of some fields within message
frames. The degree'to which this occurs is dependent on the protocol being implemented. The receiver and
transmitter logic operate as two totally independent sections with a minimum of common logic.

References:
1. ANSI-American National Standards Institute
X353, XS34/589
202-466-2299

3. EIA-Electronic Industries Association
TR30, RS334
202-659-2200

2. CCITT-Consultative Committee for International
Telephone and Telegraph
X.25
202-632-1007

4. IBM
General Information Brochure, GA27-3093
Loop Interface-OEM Information, GA27-3098
System Journal-Vol. 15, No.1, 1976; G321-0044

Terminology
Term

Definition

Term

Definition

BOP

Bit Oriented Protocols: SDlC, HDlC, ADCCP

GA

01111111 (0 (lSB) followed by 7-1 's)

CCP

Control Character Protocols: BiSync, DDCMP

lSB

First transmitted bit, First received bit

TDB

Transmitter Data Buffer

MSB

Last transmitted bit, last received bit

ROB

Receiver Data Buffer

RDP

Receiver Data Path

TDSR

Transmitter Data Shift Register

TDP

Transmitter Data Path

FLAG

01111110

lM

loop Mode

ABORT

11111111 (7 or more contiguous 1's)

66

BLOCK DIAGRAM
MASTER

RESET

RCP
RXENA
RXACT
RDA
RSA

SFR

t

h

=r ,.".-~

I:

:i~~
TaMT

O.....
--f------~

RSI

MAINT
SEL

~
TSD

0815

DBH

0813

0812

DB11

DBlt

DI¥9

OBl8

Ao

Al

A2

DPENA BYTE OP

DBI?

DBJ6

D~5

DBp4

OBtl3

DBj1'2

DBg't

DBN

Description of Pin Functions
PinNa. Symbol

Nama

11O

Function

+ 12 volt Power Supply.
The pos~ive-golng edge 01 this clock shifts data into the receiver shift register.
This input accepts the serial bit input stream.
This output is set high, for 1 clock time of the
RCP, each time a sync or flag character is received.
This output is asserted when the RDP presents the first data character of the
message to the controller. In the BOP mode the first data character is the first
non-flag character (address byte). In the'CCP mode: 1. if strip-sync is set; the
first non-sync character is the first data character 2. if strip-sync is not set; the
first data character is the character following the second sync. In the BOP
mode the trailing (next) FLAG resets RXACT. In the CCP mode RXACT
is never reset, it can be cleared via RXENA.
0
This output is set high when the RDP has assembled an entire character and
transferred it into theiRDB. This output is reset by reading the ROB.
This output is set high: 1. CCP-in the event of receiver over run (ROR)
0
or parity error (if selected), 2. BOP-in the event of ROR, CRC error (if selected)
receiving REOM or RAB/GA. This output is reset by reading the
receiver status register or dropping of RXENA.
A high level input allows the processing of RSI data. A low
level disables the RDP and resets RDA, RSA and RXACT.
GND Ground
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
Wire "OR" with DB9II-DBI/J7
For a bit data bus
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
Controls direction of data port. W/R= I, Write. W/R=O, Read.
Address input-MSB.
Address input.
Address input-LSB.
If asserted, byte operation (data port is a bits wide) is
selected. I! BYTE OP=O, data port is 16 bits wide.
Strobe for data port. After address, byte op, W/R and data are set-up DPENA
may be strobed. If reading the port, DPENA may reset (depending on register
selected by address) RDA or RSA. I! writing into the port, DPENA may reset
(depending on register selected by address) TBMT.
I/O Bidirectional Data Bus-MSB.
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus.
I/O Bidirectional Data Bus-LSB.
PS + 5 volt Power Supply.
This input should be pulsed high after power turn on. This will: clear all flags, and
status conditions, set TBMT = I, TSO= 1 and place the device in the primary
BOP mode with 8 bit TX/RX data length, CRC CCITT initialized to alii's.
This
output indicates the status of the TOP. TXACT will go high after asserting
0
TXENA and TSOM coinsidently with the first TSO bit. This output will reset one
hal! clock after the byte during which TXENA is dropped.
This output is at a high level when the TDB
0
or the TX Status and Control Register may be loaded with
the new data. TBMT =0 on any write access to TDB or TX Status and
Control Register. TBMT returns high when the TDSR is loaded.
TERR bit, Indicating transmitter underflow.
0
Reset by MR or assertion of TSOM.
A high level input allows the processing of transmitter
data.
0
This output is the transmitted character.

PS
Power Supply
Receiver Clock
I
Receiver Serial Input I
Sync/Flag
0
Received
Receiver Active
0

2
3
4

VDD
RCP
RSI
SFR

5

RXACT

6

RDA

7

RSA

a

RXENA

Receiver Enable

9
10
11
12
13
14
15
16
17
18
19
20
21
22

GND
DBSa
DBIl9
OBIS
DBII
DB12
DB13
DB14
OBIS
W/R
A2
AI
AS
BYTEOP

Ground
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Write/Read
Address 2
Address 1
Address 0
Byte Operation

23

DPENA

Data Port Enable

24
25
26
27
28
29
30
31
32
33

DBIl7
DBRl6
DBIl5
DBtt4
DB¢3
DB/l2
DB¢I
DB/I/I
Vce
MR

Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Power Supply
Master Reset

34

TXACT

Transmitter Active

35

TBMT

Transmitter Buffer
Empty

36

TSA

37

TXENA

Transmitter Status
Available
Transmitter Enable

38

TSO

39

TCP

40

MSEL

Receiver Data
Available
Receiver Status
Available

Transmitter Serial
Output
Transmitter Clock
Maintenance
Select

The positive going edge of this clock shifts data out olthe
transmitter shift register.
Internally RSI becomes TSO and RCP becomes i'CP.
Externally RSlls disabled and TSO= 1.

68

Definition of Terms

Register Bit Assignment Chart 1 and 2
'ajaBu

Term

Definition

OB08

RSOM

DB09

REOM

OB10

RABIGA

OBll

ROR

Receiver Start of Message-read only bit. In BOP mode only, goes high when first non-flag (address byte)
character loaded into RDB. It is cleared when the second byte is loaded into the RDB.
Receiver End of Message-read only bit. In BOP mode only, set high when last byte of data loaded into ROB, or
when an ABORT character is received. It is cleared on reading of Receiver Status Register or dropping of RXENA.
Received ABORT or GO AHEAD character, read only bit. In BOP mode only, if LM=O this bit is set on receiving an
ABORT character; If LM= 1 this bit is set on receiving a GO AHEAD character. This is cleared on reading of
Receiver Status Register or dropping of RXENA.
Receiver Over Run-read only bit. Set high when received data transferred into ROB and previous data has not
been read, indicating failure to service RDA within one character time. Cleared on reading of Receiver Status
Register or dropping of RXENA.
Assembled B" Count-read only bits. In BOP mode only, examine when REOM=l. ABC=O, message·terminated
on stated boundary. ABC=XXX, message terminated (by FLAG or GA) on unstated boundary, binary value of ABC
= number of valid bits available in RDB (right hand justified).
Error CheCk-read only bit. In BOP set high if CRC selected and received in error, examine when REOM= 1. In
CCP mode: 1. set high if parity selected and received in error, 2. if CRC selected (tested at end of each byte) ERR
CHK = 1 if CRC GOOD, ERR CHK = 0 if CRC NOT GOOD. Controller must determine the last byte of the
message.

)B12-14

A,B,C

DB15

ERRCHK

DB8

TSOM

DB9

OB10
OBll
DB15

DB8-10

OBll

DB12
OB13
DB14
DB15
)B13-15

Transmitter Start of Message-W/R bit. Provided TXENA-l, TSOM initiates start of message. In BOP, TSOM-l
generates FLAG and continues to send FLAG's until TSOM=O, then begin data. In CCP: 1. IDLE=O, transm" out of
SYNC register, continue until TSOM=O, then begin data. 2. IDLE=ltransmit out of TDB. In BOP mode there is also
a SpeCial Space Sequence of 16-0's initiated by TSOM= 1 and TEOM= 1. SSS is followed by FLAG.
TEOM
Transmit End of Message-W/R bit. Used to terminate a message. In BOP mode, TEOM=l sends CRC, then
FLAG; ifTXENA= 1 and TEOM= 1 continue to send FLAG's, if TXENA=O and TEOM=l MARK line. In CCP: 1.
IDLE=O, TEOM= 1 send SYNC, ifTXENA=l and TEOM= 1 cOntinue to send SYNC's, if TXENA=O and TEOM= 1
MARK line. 2.IDLE=l, TEOM=l, MARK line.
.
TXAB
Transmitter Abort-W/R bit. In BOP mode only, TXAB= 1 finish present character then: 1. IDLE =0, transm" ABORT
2.IDLE=l, transmit FLAG.
TXGA
Transmit Go Ahead-W/R bit. In BOP mode only, modifies character called for by TEOM. GA sent in place of FLAG.
Allows loop termination-GA character.
TERR
Transmitter Error-read only bit. Underflow, set high when TDB not loaded in time to maintain continuous
transmission. In BOP automatically transmit: 1. IDLE=O, ABORT 2. IDLE=l, FLAG. In CCP automatically transm":
1.IDLE=O, SYNC2.IDLE=l, MARK. Cleared by TSOM.
X,Y,Z
Y
X
-W/R bits. These are the error control bits.
0
0
X'6+ X12+ X5+ 1 CCITT-lnitializeto"l"
0
1
X'6+ X"+ X5+ 1 CCITT-Initialize to "0"
o
1
0
Not used
X'6+ X'5+ X'+ l-CRC16
o
1
1
1
0
0
Odd Parity-CCP Only
1
0
1
Even Parlty-CCP Only
1
1
0
Not Used
I
Inhibit all error delection and transmission
1
1
Note: Do not modify XYZ until both data paths are idle
IDLE
IDLE mode select-W/R bit. Affects transmitter only. In BOP-controlthe type of character sent when TXAB
asserted or in the event of data underflow. In CCP-controls the method of in"ial SYNC character transmission and
underflow, "1" = transmit SYNC from TDB., "O"=transmit SYNC from SYNC/ADDRESS register.
SEC ADD
Secondary Address Mode-W/R bH. In BOP mode only-after FLAG looks for address match prior to activating
RDP, if no match found, begin FLAG search again. SEC ADD bit should not be set if EXADD= 1 or EXCON= 1.
STRIP SYNC/LOOP Strip Sync or Loop Mode-W/R bit. Effects receiver only. In BOP mode-allows recognition of a GA character. In
CCP-after second SYNC, strip SYNC; when first data character detected, set RXACT = 1, stop stripping.
PROTOCOL
PROTOCOL-W/R bit. BOP=O, CCP= I
All Parties Address-W/R bit. If selected, modifies secondary mode so that the secondary address or 8-1's will
•APA
activate the RDP.

z

o
o

TXDL

Transmitter Data Length-W/R bits.
TXDL3 TXDL2 TXDL 1
LENGTH
0
0
Eight bits per character
I
Seven bits per character
1
1
I
0
Six bits per character
1
0
I
Five bits per character
1
0
0
Four bits per character·
1
o
1
I
Three bits per character·
o
1
0
Two bits per character·
o
0
lOne bit per character"
·For data length only, not to be used for SYNC character (CCP mode).
Receiver Data Length-W/R bits.
RXDL3 RXDL2 RXDL I
LENGTH
0
0
Eight bits per character
I
I
1
Seven bits per character
I
I
0
Six bits per character
I
0
1
Five bits per character
I
0
0
Four bits per character
I
1
Three bits per character
I
0
Two bits per character
0
lOne bit per character
Extended Control Field-W/R bit. In receiver only; if set, will receive control field as two 8-bit bytes. Execn bit should
not be set if SEC ADD =1.
Extended Address Field-W/R bit. In receiver only; LSB of address byte tested for a "1". "NO--continue receiving
address bytes, if YES go into control field. EXADD bit should not be set if SEC ADD = 1.

o

OB8-1~

RXDL

o

o
o
o

DB11

EXCON

OB12

EXADD

'Note: Product manufactured before lQ79 may not have this feature.

69

Register Bit Assignment Chart 1
REGISTER
Receiver Data
Buffer
(Read OnlyRight JustifiedUnused Bits= 0)
Transmitter Data
Register
(Read/WriteUnused Inputs=X)

DPB7

DPI6

DP;S

DPII4

DP,3

DPS2

DPS1

DPH

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RDS

SynC/Secondary
Address
(Read/WriteRight JustifiedUnused Inputs=X)

SSA7

MSB

LSB

T06

TD7

TD5

T04

TD3

T02

TD1

MSB

TD0
LSB

SSA6

SSA4

SSA5

SSA3

SSA2

SSA1

MSB

SSAg
LSB

Register Bit Assignment Chart 2
REGISTER

DP15

DP14

DP13

DP12

DP11

DP1;

DPJJ9

DP;a

Receiver Status
(Read Only)

ERRCHK

C

B

A

ROR

RAB/GA

REOM

RSOM

TXStatus
and Control
(Read/Write)

TERR
(Read Only)

0

0

0

TXGA

TXAB

TEOM

TSOM

Mode Control
(Read/Write)

*APA

PROTOCOL

STRIP
SYNC/
LOOP

SEC ADD

IDLE

Z

Y

X

Data Length
Select
(Read/Write)

TXDL3

TXDL2

TXDL1

EXADD

EXCON

RXDL3

RXDL2

RXDL1

• Note: Product manufactured before 1Q79 may not have this feature.

Register Address Selection
1) BYTE OP = 0, data port 16 bits wide
A1
A0
A2

o
o

0
1

o

X
X
X
X

Register
Receiver Status Register and Receiver Data Buffer
Trar,lsmitter Status and Control Register and Transmitter Data Buffer
Mode Control Register and SYNC/Address Register
Data Length Select Register

X = don't care

2) BYTE OP = 1, data port 8 bits wide
A1
A0
A2

0 0 0
0 0 1

o
o

0
1

o
o

o
1

Register
Receiver Data Buffer
Receiver Status Register
Transmitter Data Buffer
Transmitter Status and Control Register
SYNC/Address Register
Mode Control Register

o
Data Length Select Register

70

BOP TRANSMITTER OPERATION

CCP TRANSMITTER OPERATION

(PROCESSOR LOAD OR MASTER AE:5ET)

1------..!(0
(PROTOCOL

YES

NO

71

= 1: XYZ = CRe 16)

CCP RECEIVER TIMING
RCP

JULJl,J~j

JL

uu-

~

J~J

~

W/R =1

n

-----',

(not clock edge related)

RXENA

SFR

~

RDA

------;1

-.lL J L
l

[l

r=m= -=c-

DATA 1

I
I
I
I
I
I

f-+---SYNC--..J_SYNC-!
RSI

.mEAD

EAD
STX

DATA 1 _ _' - _

L-

ETX

J~

~J

WIR=O

W/R=O

..IU

NOTE 1

.....JC

DPENA

f~f

W/R=O W/R=Q

JlITEAD
READ

ETX

L
I
I
I

II

~

CRC

~

JL

SL

-=r=

SL
I
I

G"on2

~
RXACT~

RSA

~

L
r;;~2

ROR
ERR CHK

NOTE I-Mode set for CCP with CRG selected
NOTE 2-lf overrun had occured-no READ STX
NOTE 3-ERR CHK must be sampled before next byte or before RXENA brought low

---r---c:

~
CCP TRANSMITTER OPERATION
Tep

MR

TXENA

""""

~
~
I I
I

Jl

---

,---

-----"

NOTEt

TSOM::;1

";';' ';';'

n

- - l LJ L---J

I

I I
r r

I
I
I

II I,
I ''TSQMol
I

,.

n

r;"""""
,m'

r

-~

In

TSO

~

r

I

I
I
rI
I

n

~NOTE2~

LOAD
STX

LOAD1
DATA

---'

I L-J C -

h
,

L~t),n i Ln -

II
I

TEOMol

r

'-;I

iY"d'

""

II

'".n

Y

~

r
rr

!
L

I

II

,

r---

NOTE I-Mode IS CCP with CRG selected
NOTE 2- Trailing edge 01 DPENA musl occur at least one-hall

clock pulse prior to T6MT=1 to avoid underrun

u/ rv-L

I
I

=-----LJ

~

n

TSOM,O

'-----;'-SECOND SYNC

,",,"'-"""'

TXACT

'lsI'" 'lI

I

I I

I'

~p'

SYNC

Fx

~
I

~ ,..

SYNC

~

I

DATA

CRC

..---J

MARK

BOP RECEIVER TIMING

JULf1~

Rep

JL

MR

LfU-1' Lf~ u#lj# Lf-Y UU#L,f'L,.yLJ~ULJLf
W/R=O
Address Byte

W/R= 1

DPENA~

W/R=O
Read Status

W/R ... O
Control Byte

W/R=Q
W/R=O
Data Byte /I 1 Data Byte #2

WfR=O
Data Byte #3

W/R=O
Data Byte #4

W/R=O
Read Status

---l!--JL~ ~ ~ ~ ~
,

no! cloc:kedgerelated

,--,

RX.ENA~
~

SFR

r

I---FlAG ...

77T}~=rrm
RSI

I

JL
.•. FLAG- -l

l~

~
~

Data
Byte #1

~

~

~

1=#4

sLJ

~

RDA

--ro.;:-:--

RSA

~

RXACT

;<~L-

I--FLAG...

~

EEL l
LSlIln
_J

NOTE2

s-

_ _ _ __

••• FLAG-J

~

~

~
~

~~

RSCM

REOM

ERR,CHK, ABC,

(j

L: __

;NO~E2

ROR,RABIGA

,

NOTE 1-11 required-but nol done In thiS example
NOTE 2--1f no DPENA to read Dala Byte # 2

~
:--- - --...,
__I

II

BOP TRANSMITTER OPERATION

ruut...JLr1 JLJ#lJLJL//JlJ //LflSl // JLS1SL

~

TCP

I

MA

~ .•.

:

TXENA

~--

,

If,

I

--~

,

T50M", 1

not cloctl. edge related

I

::
Load:
, I TSOM=O Address
I

ole

OPENA

I

I

'--I

Load
Control

rl.-

,I
I

IL
TXACT~
_--'---__ Ilu
TBMT@l

Load

DataLengIh

Load
Data Byte

~

--.fL

~,r-

L

TEOM=!

~---

-.lL
__ L

J
I

~

I

TSO~
Note I-Trailing edge of OPENA must occur at least one-halt clock
pulse prior to T8MT'" ,. To avoid underrun.

l

~ ICom""B~
Address Byte

i----FLAG .[ Last Data_

~

CRC1

r-

~I~

---I

MARK

~

AC TIMING DIAGRAMS

TCP~
TBMT

~
----.!

1....___

RCP

I~O~r
RXACT

--

x=

~r--

RDA,RSA ~

DPENA

DPENA

W/R=1

W/R=O

\'-----

to Receiver
RegIsters

to Transmitter
Registers

TBMT

~

RDA'RSA~

TCP

1,50 ns
TSO

lc

RXENAJ

~300ns,min

Resets: RDP-RDA, RSA,
RXACT, receiver
into search
mode (lor FLAG)

1_3oons,
TXACT

Note: Unless otherwise specified all times are maximum.

Data Port Timing

READ FROM USYNR/T

WRITE TO USYNR/T

74

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range .....................................,..........................O°C to + 70°C
Storage Temperature Range ............. , ................................................. -55°Cto +150°C
Lead Temperature (soldering, 10 sec.) ...............................................................+325°C
Positive Voltage on any Pin, with respect to ground ..................................................... +18.0V
Negative Voltage on any Pin, wlth respect to ground ..................................................... -0.3V
·Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transients on the AC power line may appear on the DC output. For example, the
bench power supply programmed to deliver + 12 volts may have large voltage transients when the
AC power is switched on and off. If this possibility exists it is suggested that a clamp circuit be used.
ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C, Vee= +5V±5%, Voo=+ 12V±5%, unless otherwise noted)
Parameter
D.C. Characteristics
INPUT VOLTAGE LEVELS
Low Level, V,L
High Level, V,H
OUTPUT VOLTAGE LEVELS
Low Level, VOL
High Level, VOH
INPUT LEAKAGE
Data Bus
All others
INPUT CAPACITANCE
Data Bus, C,N
Address Bus, C,N
Clock, C,N
All other, CIN
POWER SUPPLY CURRENT
Icc

Min.

Typ.

2.0

Unit

0.8
Vce

V
V

0.4

V

IOL=1.6ma
IOH=40/La

50.0

/La
/La

0",VIN",5v, DPENA=·O or W/R=I
V'N=+5v

2.4
5.0

Comments

pf
pf
pf
pf
70
gO

100

A.C. Characteristics
CLOCK-RCP, TCP
frequency
PWH
PWL
tr, tl
DPENA, TwoPENA
Set-up Time, TAS
ByteOp, W/R
A2,A1, Ao
Hold Time, TAH
Byte Op, WIR,
A2, A1,Ao
DATA BUS ACCESS, TOPA
DATA BUS DISABLE DELAY, Topo
DATA BUS SET-UPTIME, TOBS
DATA BUS HOLD TIME, TOBH
MASTER RESET, MR

Max.

ma
ma
TA=25°C

1.5

DC
325
325
10
250
0

50/Ls

MHz
ns
ns
ns
ns
ns
ns

0
150

100
0
100
350

75

ns
ns
ns
ns
ns

Receiver Data

and
Receiver Status
Access Sequence
Preferred reading sequence of receiver RDA and RSA.

YES

CCP RECEIVER OPERATION

BOP RECEIVER OPERATION
PROCESSOR LOAD
OR M.R

TEST MADE AFTER 8 AXCLK'S

24 RXCLK'S
(PIPELINE DELAY)

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore. such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the rightto make changes
at any time in order to improve design and supply the best product possible.

76

COM52C50
PRELIMINARY

TWINAX Interface Circuit (TIC)
FEATURES

PIN CONFIGURATION

o Conforms to IBM® 5250 Standard used in IBM System
/36 and /38.

D,
D,
WR
TXEN
DTX
TX
TXDMA
AX
D,
D,
RESET
XTAL"
XTAL,
GND

o Operates at 1Mbps Data Rate
o Transmits and Receives Manchester II Encoded Data

o On Chip Odd or Even Parity Generation and Checking
o

Programmable Interframe Zero Bit Insertion

o Handles Multi Byte and Single Byte Transfers
o Multiple Address Select Register Allows for Up to 7
o
o

o
o

o

o
o
o
o
o
o

o
o
o
o

Node Address Emulation
Programmable Extended TX Enable
Internal/External Loopback Capability for Self Test
Diagnostics
On Board Predistortion Circuitry
Low Power CMOS
On Board Crystal Oscillator Simplifies Clock
Generation
8 MHz Clock Output for General Use
Incorporates a Three Level Receive FIFO to Simplify
Processor Interface
Compatible with high speed microprocessor with no
wait state up to 10 MHz (80186, 68000 etc ... )
Programmable DMA and Jump Vectoring Interface
Independent RX DMA and TX DMA Request Signals
Programmable Interrupt Selection
28 Pin Plastic Dual In Line and Chip Carrier Packages
Open Drain Output on Interrupt Pins
TIL Compatible Inputs and Outputs
Single +5v Supply

Vee
D,
Do

C§
RD
Ao
A,
A,

INT,
INT,
AXDMA
CLKOUT
D,
DB

PACKAGE: 28-pin DIP

I'"()a:--

'"
UJ

a:

PACKAGE: 28-pin PLCC

GENERAL DESCRIPTION
The COM52C50 TWINAX controller is a CMOS device that
performs the communications interface to the IBM 5250
TWINAXIAL bus. It interfaces to a general purpose microprocessor on one side and to the IBM 5250 TWINAXIAL
bus on the other side. The COM52C50 handles the parallel
to serial and serial to parallel conversion of data to and from
the TWINAXIAL bus and the encoding and decoding of

data in Manchester II format. The COM52C50 consists ora
RECEIVE BLOCK, a TRANSMIT BLOCK, and CONTROL
circuitry. The Receive and Transmit sections of the
COM52C50 are separate and may be used independent of
one another. The COM52C50 generates and detects the bit
sync, frame sync, parity, and the fill zero bit patterns
according to the IBM 5250 standard.

IBM® is a registered trademark of the International Business Machines
Corporation.

77

cs
RD
WR
AO - A2

•

ADDRESS
DECODE
AND
CONTROL

_RST
-VCC
_GND

Fig. 1- COM52C50 INTERNAL BLOCK DIAGRAM

RXDMA
TXDMA

I
DATA
BUS
ADDRESS
BUS-

11

1\

<,

V

I

DO-D7

I

,A

DECODE

TXD
CS

COM52C50

AO-A2

TWINAX
INTERFACE
CHIP

• WR
RD
INTERRUPT
REQUEST

TX
ENABLE

INT1
RX
INT2
RESET CLKOUT XTAL1

SYSTEM
RESET

TX

XTAL2

~D~

I

16 MHZ

8MHZ

Fig. 2-TYPICAL COM52C50 INTERFACE

78

1 .)

~

t..(>

r

TWINAXIAL
CABLE

TABLE 1 - COM52C50 TWINAX DESCRIPTION OF PIN FUNCTIONS
PIN NO.
1,2,9,
10,1S,16,
26,27

NAME

DESCRIPTION

SYMBOL

Bidirectional
Data Bus

Do-D7

An 8 bit DATA BUS is used to interface the COMS2CSO to the
processor Data Bus.

3

Write Data
Strobe

WR

A low pulse on this input (when CS is lowl enables the COMS2CSO
to accept the data or control information from the DATA BUS into
the COMS2C50.

4

TX Enable

TXEN

This output is active low when the transmit data is valid. It is used to
enable the external TX driver circuitry.

S

Delayed TX

DTX

Delayed TX Manchester encoded.

6
7

TX Data

TX

TX Buffer

TXDMA

Transmit data Manchester encoded.
The TX Buffer Empty signal is used as a transmit DMA request.

8

RX Data

RX

This input accepts the receive Manchester II encoded bit stream.

11

Reset

RST

This pin resets the COMS2CSO to a known state. In addition, it disables
the TX and puts an inactive state on the interrupt lines.

12
13

Crystal 2
Crystal 1

XTAL2
XTAL,

An external 16 MHz crystal is connected to these two pins. If an external
16 MHz TTL clock is used, it should be connected to XTAL, with a
390 ohm pullup resistor; XTAL2 must be left floating.

14

Ground

GND

Ground

17

Clock Out

CLKOUT

This is a divide by two of the XTAL" 16 MHz input clock. It has a SO/SO
duty cycle and can be used as a clock input to the host microprocessor.

18
19

RX Buffer

RXDMA

The RX Buffer Full signal is used as a receive DMA request.

Error Related
Interrupt

INT2

This active low, open drain output provides the interrupt signal for
error related operations.

20

Data Related
Interrupt

INT,

This active low, open drain output provides the interrupt signal for
data related operations.

21
22
23

Register
Address Select

A2
A,
Ao

During processor to COMS2CSO communications, these inputs are
used to indicate which internal register will be selected for access by
the processor.

24

Read Data
Strobe

RD

A low pulse on this input (when CS is lowl enables the COMS2CSO to
place the data or status information on the DATA BUS.

2S

Chip Select

CS

A low level on this input enables the COMS2CSO for reading and
writing by the processor. When CS is high, the DATA BUS is in high
impedance and the WR and RD will have. no effect on the ·chip.

28

Power Supply

Vcc

+SV Power Supply.

FUNCTIONAL DESCRIPTION
RECEIVE BLOCK

TRANSMIT BLOCK

The COM52C50 recovers frames that conform to the IBM
5250 protocol. It also checks the received frame for proper
sync, parity and trailing zeros. The RX input is sampled at 8
times the bit rate. The receive logic is brought into
synchronization during bit and frame synchronization
patterns. The internal receive clock is adjusted after each
RX transition to compensate for bit jitter and distortion in the
received data signal. In addition to the Receive Shift
Register, the Receive block incorporates a two level Firstin-First-out (FIFO) buffer. At the start of a message, the
host microprocessor is alerted by handshake signals like
Line Idle, Frame Sync Detect, Poll Command Detect, and
Address Match. Thereafter, the RX Buffer Full signal
informs the host microprocessor of the availability of
received data. The end of a receive message is marked by
either the detection of 1) End Of Message sequence 2) Line
Idle or 3) Receive Error.

The COM52C50 transmits data frames that conform to the
IBM 5250 protocol. The transmit block consists of an 8 bit
data buffer register, a present address register, .16 bit
parallel to serial shift register, and parity generation logic. A
transmit operation is initiated by loading the transmit buffer
register. The transmitted frame will consist of the sync bit,
the 8 bits loaded by the host microprocessor into the buffer
register, the present address from the PRESENT
ADDRESS REG ISTER, or the (111 ) end of message code if
the last frame is being transmitted, followed by a parity and
three zero fill bits. After the host microprocessor loads the
transmit buffer register, the TRANSMIT BUFFER EMPTY
bit in the status register will become inactive. After a
transfer of a data frame from the buffer register to the shift,
register is accomplished, the TRANSMIT BUFFER EMPTY
bit inthe INTERRUPT AND TRANSMIT STATUS REGISTER
becomes active.
79

BIT STREAM
The bit stream is serially transmitted to (or received from)
the System Unit at a transmission bit rate of 1 Mbps (±2%).
Therefore,1 microsecond is required for each bit, and 16
microseconds are required for each frame. All information
between a station and the System Unit is transmitted on the
twinaxial cable. The COM52C50 provides the transmitted
serial data in Manchester encoded format where a "1"
(one) bit is represented by a half bit cell of logical high
followed by a half .bit cell of logical low, and a 0 (zero) bit is
represented by a half bit cell of logical low followed by a half
bit cell of logical high. In addition, the COM52C50 provides
a Delayed Transmit Data signal which is delayed by 1/4 of
a bit time to simplify the interface to the external driver
circuitry.

I+-- 1 - -.....+1.0-----

--~·I~·--o ~

!---l/.1S - -....t-ol.~--l/.1s --+-.I,...--l/.1s----..j
A message contains a bit sync pattern, a frame sync
pattern, and a frame. The bit sync and the frame sync
patterns establish synchronization between the station and
the System Unit, and are transmitted prior to transmission of
the first frame.

TABLE 2 - IBM 5250 FRAME FORMAT
The frame format for command and data to and from the IBM 5250 attachment is a fixed 16 bit frame. Only 13 bits
contain information. The general format is as follows:
One 5250 frame (16 bits)

Transmission start sequence

-.

~--------~
8-bit data/command word

I

,. . _-

r~r/--~------------'~~---""----~.....

~ ·~-r n n ~, I
IUUUU~
Bit synchronization

BIT

0-2
3

4-6

7-14
15

-

- -.... -

---

,

DESCRIPTION

These bits are always O.
This is designated as the parity bit and will be set to ensure even parity in each frame.
These are the. physical station address. Valid addresses are 000 to 110, and 111 is the end of message
delimiter for ihe cable. A frame containing a 111 station address causes the station to ignore all following cable
activity until a bit and frame synchronization is detected following a line turnaround. In addition, if only one frame
is sent from the system unrt, these bits represent the station address. If only one frame is sent from the work
station, these bits are set to 111.
These bits contain command or data information. They represent a data byte or a status byte from the station, or
they represent a data byte or a command from the system unit.
This is the sync bit. It is the first bit on the line and it is always set to 1.

RESETIING THE COM52C50
The COM52C.50 must be reset on power up .. This is
accomplished by either of two methods: Hardware Reset or
Software Reset.
Hardware Reset:

On the COM52C50 a RE$ET pin is dedicated to allow
resetting of the device by applying a low level on the
RST pin. The RESET signal should have a minimum
duration of 1tIs.
Software Reset:
The chip will also be reset when the Software Reset
bit in the Control Register is asserted. The host
microprocessor asserts Software Reset by writing a
"zero" in bit 0 of the Control Register. To take the
COM52C50 out of reset, the host microprocessor

should write a "one" in bit 0 of the Control Register.
Writes to the Control Register bit 0 should be spaced
such that the Internal Reset signal has a minimum
duration of 1tIs.
Upon reset, all of the internal registers of the COM52C50
will be cleared. In addition, the COM52C50 enters an idle
state in which it can neither transmit nor receive data. To
disable undesired interrupts, the Interrupt Mask Register is
set to 00 and the Status Registers bits are all inactive.
INITIALIZING THE COM52C50
Following RESET, the COM52C50 should be initialized by
writing a valid bit pattern to the Interrupt Mask Register, the
Mode Register, the Station Address Select Register. At this
point, the Control Register can be used to enable Receive
and Transmit.

80

TABLE 3 - REGISTER DECODE & TRUTH TABLE FOR INTERNAL REGISTER SELECT

ADDRESS

A2

A1

AD

RD

WR

00

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
1
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

0
1

01

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

02
03
04
05
06
07

0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1

Mode Register
Not Used
Interrupt Mask Register
Interrupt Status Register
Address Select Register
RX Status Register
Control Register
RX Buffer
Zero Fill
Not Used
Present Address Register
Present Address Register
TX Buffer
TX Status Register
TX BufferEOM
TX Status Register

W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R

frames. Up to 255 zero bits may be inserted in between
frames. If no zero bit fill is required, this register should be
cleared by writing a zero. The host microprocessor may not
write to this register during data transmission. This register
is cleared following RESET.

REGISTER DESCRIPTIONS
RXBUFFER
This is the second level of a two byte deep Receive FIFO
where the COM52C50 Receive Block provides new data
and the microprocessor reads it. This register contains the
8 bit information field of an IBM5250 frame (bits 14-7}.lt is
read by the host microprocessor after each frame reception
which is indicated by the RX Buffer Full bit. This is an 8 bit
read only register.

INTERRUPT MASK REGISTER
This is an 8 bit write only register which is loaded by the host
microprocessor. ThifNigtster controls interrupt generation
on both the Tf\/Tf and
2 interrulJ! Qirls. The most significant
5 bits enable the generation of TI'ITl, the least significant
3 bits enable the generation of INT2.

TXBUFFER
This register contains the 8 bit information field of an
IBM5250 frame (bits 14-7). It is written to by the host
microprocessor and contains the information to be sent out
in the next frame. This is an 8 bit write only register.

INT1
A logical one in a particular bit position will enable the
corresponding bit in the Interrupt Status Register (bits 7-3)
to cause an interrupt when it is set.

ZERO FILL REGISTER
This eight bit register is loaded by the host microprocessor
and contains the number of zero bits that should be filled
between two frames. The host microprocessor would read
a Set Mode Command and find out how many zero bytes
must be padded on the next reply and then convert it to bits
and write it to this register. The COM52C50 takes care of
inserting the programmed number of zero bits between two

INT2
A logical one in a bits (2-1-0) will enable bits (7 -6-5) in the
RX Status Register to cause an INT2 interrupt when it is set.

ADDRESS SELECT REGISTER
This is an eight bit Write Only Register that controls address
bit recognition of any of the seven possible node
addresses. A node may emulate more than one address at

a time by programming a "one" in the corresponding bit of
the Address Register.
A "one" in anyone or more olthe Address Select bits allows
the COM52C50 to respond to that group of addresses.

Upon Reset, this register is cleared to all zeros thereby
disabling interrupts. This is an 8 bit write only register.

07

06

05

04

03

02

01

DO

ONE

106

105

104

103

102

101

100

Examples'
Emulate one address: 13)

1

0

0

0

1

0

0

0

Emulate four addresses: (6-4-3-0)

l'

1

0

1

1

0

0

1

Emulate All Addresses: (6-5-4-3-2-1 -0)

1

1

1

1

i

1

1

1

81

TABLE 4 - REGISTER DIAGRAMS

WRITE REGISTERS

READ REGISTERS

ADDRESS

DESCRIPTION

CBi!7TElIT 6
00

Bri" 5

r

BIT 4-

I

ADDRESS
BIT 3

BIT 2

BIT 1

DESCRIPTION
BIT 7

BIT 0

Not Used

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT

0]

00

01

01

r.

I.

generate interrupt 1 - - -_ _-<

-1- Interrupt 2 Mask ---l

Interrupt 1 Mask

Address Select Register
02
CD

02

r--generate interrupt 2

I\)

lone

1

A6 I··· As-I

A4

1-

A3-1 A2

1-

Al-l:oJ

--1

RX Buffer

03

1 RX7 1 RX6 1 RX5 1 RX4 1 RX3 1 RX2 1 RX1IR~J

03
Zero Fill Register

04

Not Used

04

1

zero

1

zero

1

zero

D7

I~

1

D5

1

-~ID3J ~2

r~~1

DO

1

AO

I

Present Address Register

Present Address Register

05

1

1

zero

1

zero

1

A2

1

A1I!il

05

l~er:j

zero

I-zer~-I

zero

1-zer:-I

TX5

TX4

TX3

A2

1 AI-I

TX Buffer

06

06

[xJ TX6

[xl ~~ ITXJ T~4 1-T~~l T;2 rTX] ~~oJ
TX Buffer EOM

07

07

TX2 TffiJ~oJ

PRESENT ADDRESS REGISTER

microprocessor prior to initiating a Transmit sequence. The
contents of this register are fed to the address compare
logic which compares the Present Address to the Address
Select Register. If a valid compare is detected, the Address
Match bit in the Interrupt Status Register is set.
During a receive session, the contents of this register are
valid only after the RX Buffer Full bit is set "one".
This is an eight bit read/write register.

This register holds the present address information of the
first frame fOllowing frame sync. It is used to convey the
address information to the host microprocessor and has the
address field information on all outgoing frames. This
register is loaded by the Receive Block with the address
information from the first frame following frame sync detect.
This register can also be written to by the host

TABLE 5-COM52C50 INTERRUPT STATUS REGISTER (BITS 0-7)
This is an eight bit register that can be read by the host
microprocessor. The Interrupt Status Register is cleared
BIT
0

1

2

3

4

following software or hardware reset. The bits in this
register are used to indicate the following information:

DESCRIPTION
RX PARITY ERROR
Signals the microprocessor that the frame received contained an incorrect number .of binary "1" bits. This bit is
set when the received frame has an incorrect parity bit and parity is enabled.
This bit is cleared by:
a. clearing RX Enable in the Control Register.
b. setting Reset Errors in the Control Register.
c. asserting internal RESET.
d. asserting external hardware Reset.
RX BIPHASE ERROR
Signals the microprocessor that a bit within a received frame has violated Biphase Manchester code (Le. the two
half bit cells of a bit were not complements). This bit is set when a Biphase error occurs during bits 0-15 of a
frame.
This bit is cleared by:
a. clearing RX Enable in the Control Register.
b. setting Reset Errors in the Control Register.
c. asserting internal RESET.
d. asserting external hardware Reset.
RX OVERRUN ERROR
Signals the microprocessor that an Overrun condition has occured. This bit is set when a byte stored in the
Receive Holding Register is overwritten with a new byte from the Receive Shift Register before the
microprocessor has read the Receive Holding Register.
This bit is cleared by:
a. clearing RX Enable in the Control Register.
b. setting Reset Errors in the Control Register.
c. asserting Internal RESET.
d. asserting External Hardware Reset.
e. Frame Sync Detect going active.
TX BUFFER EMPTY
Signals the processor that the Transmit Character Buffer is empty and that the COM52C50 can accept a new
character for transmission. This bit is set when a character has been loaded from the Transmit Holding Register
to the Transmit Shift Register.
This bit is cleared by:
a. writing to the Transmit Buffer Register
b. clearing TX Enable in the Control Register
c. asserting internal RESET.
d. asserting external hardware Reset.
This bit is initially set when the transmitter logic is enabled by setting the TXenable bit in the Control Register
(also TX BUFFER is empty because of reset). Data can be overwritten if a consecutive write is performed while
TX buffer empty is zero.
RX BUFFER FULL
Signals the processor that a completed character is present in the Receive Buffer Register for transfer to the
processor. This bit is set when a character has been loaded from the receive deserialization logic to the Receive
Holding Register.
This bit is cleared by:
a. reading the Receive Holding Register
b. clearing RX Enable in the Control register
c. Frame Sync Detect going active
d. asserting internal RESET.
e. asserting external hardware Reset.

83

TABLE 5-COM52C50 INTERRUPT STATUS REGISTER (BITS 0-7) CONTINUED
BIT
5

6

7

DESCRIPTION
POLL COMMAND DETECTED
Signals the microprocessor that the command in the Receive Holding Register is a POLL command.
(xxx10000) This bit is set when the first frame following Frame Sync has the binary 10000 pattern in the least
significant 5 bits of the data section.
This bit is cleared by:
a. reading the RX Buffer Register when RX Buffer Full is set.
b. Frame Sync Detect going active.
c. asserting internal RESET.
d. asserting external hardware Reset.
ADDRESS MATCH
Signals the microprocessor that a match has occured between the address field of the first frame following Frame
Sync and any bit within the Address Select Register. This bit is set after a valid compare has occured between
the address field of the first frame following frame sync and any bit of the Address Select Register.
This bit is cleared by:
a. reading the RX Buffer Register when RX Buffer Full is set.
b. Frame Sync Detect going active.
c. asserting internal RESET.
d. asserting external hardware Reset.
FRAME SYNC DETECTED
Signals the microprocessor that a Frame Sync has been detected on the RX pin of the COM52C50. The Frame
Sync detect circuitry checks for one "1" bit (10 half bit) followed by a three half bit times of ones followed by a
three half bit times of zeros (111000). This bit is set when a Valid Frame Sync pattern is detected.
This bit is cleared by:
a. reading the Interrupt Status Register.
b. Line Idle going active.
c. asserting internal RESET.
d. asserting external hardware Reset.

RESETTING OF INTERRUPTS
The INT1 and INT2 signals feature an automatic interrupt
acknowledge that will take interrupt away when the proper
When the interrupt is caused by:
Frame Sync Detect

Address Match

Poll Command Detect

RX Buffer Full

TX Buffer Empty

RX Errors

Line Idle Detect

End of Message
(EOM) Detect

action is taken by the processor. The following describes
how each of the eight interrupting conditions get cleared.

The interrupt is cleared by:
Reading the Interrupt Status Register twice
Line Idle going active
Internal Reset
External Reset
Frame Sync Detect
Reading the RX Buffer Register when the RX Buffer is full
Internal Reset
External Reset
Frame Sync Detect
Reading the RX Buffer Register when RX Buffer is full
Internal Reset
External Reset
Clearing the RX Enable bit
Reading the RX Buffer Register when the RX Buffer is full
Internal Reset
External' Reset
Writing to the TX Buffer Register
Clearing the TX ENable bit
Internal Reset
External Reset
Asserting Reset Errots
Clearing RX Enable
Internal Reset
External Reset
Reading the RX Status Register twice
Internal Reset
External Reset
Reading the RX Status Register twice
Internal Reset
External Reset

84

TABLE 6-COMS2CSO RX STATUS REGISTER (BITS 0-7)
This is an eight bit register that can be read by the host
microprocessor. The bits in this register are used to
indicate the following information'
BIT

DESCRIPTION

0

FIXED ZERO

1-3

PRESENT ADDRESS BIT 0-1-2
These three bits hold the value of the Present Address. They are the same as the bits 1, 2, 3, of the Present
Address Register.

4

RX BUFFER FULL
Signals the processor that a completed character is present in the Receive Buffer Register for transfer to the
processor. This bit is set when a character has been loaded from the receive deserialization logic to the Receive
Buffer Register.
This bit is cleared by:
a. reading the Receive Buffer Register
d. asserting internal RESET
b. clearing RX Enable in the Control register
e. asserting external hardware RESET
c. Frame Sync Detect going active

5

LAST FRAME/End Of Message (EOM)
Signals the microprocessor that a "1 1 1" pattern has been detected in the address field of an incoming frame.
This bit is propagated through the RX FIFO logic and it corresponds to the data byte immediately available to the
processor. This bit is set when the 3 bit address field of a frame·gets a match with a constant "1 1 1" pattern.
This bit is cleared by:
a. Frame Sync Detect going active.
c. asserting internal RESET.
b. clearing RX Enable in the Control Register.
d. asserting external hardware RESET

6

LINE IDLE
Signals the microprocessor that the RX line has not seen a transition for the past 3f.ls time interval. This can be
used by the microprocessor to learn that the RX line is idle. This bit is set when the RX line remains idle for a 3
microseconds duration.
This bit is cleared by:
a. activity on the RX line.
c. asserting Internal RESET.
b. clearing RX Enable in the Control Register
d. asserting External Hardware Reset.

7

RX ERRORS
Signals the microprocessor that a Receive Error condition has occured. This bit is set when anyone or both of
the Interrupt Status Register bits 0 and 1 are set.
This bit is cleared by:
a. asserting Reset Errors in the Control Register
c. asserting Internal Software RESET.
b. clearing RX Enable in the Control Register.
d. asserting External Hardware RESET.

TABLE 7-COMS2CSO TX STATUS REGISTER (BITS 0-7)
BIT

DESCRIPTION

0

Fixed at Zero

1

TX BUFFER EMPTY
Signals the processor that the Transmit Buffer Register is empty and that the COM52C50 can accept a new
character for transmission. This bit is set when a character has been loaded from the Transmit Buffer Register to
the Transmit Shift Register.
This bit is cleared by:
a. writing to the Transmit Buffer Register
c. asserting internal software RESET.
b. clearing TX Enable in the Control Register
d. asserting external hardware RESET.
This bit is initially set when the transmitter logic is enabled by setting the TXenable bit in the Control Register. Data
can be overwritten if a consecutive write is performed while TX buffer empty is "zero".

2

TX UNDERRUN ERROR
Signals the microprocessor that an Underrun condition has occured. This bit is set when, during a transmission
process, the microprocessor writes to the TX Holding Register after the TX Shift Register has already shifted its
last bit out.
This bit is cleared by:
a. clearing TX Enable in the Control Register.
c. asserting Internal RESET.
b. setting Reset Errors in the Control Register.
d. asserting External Hardware RESET.

3-7

These bits are fixed zeros.

The TX Status Register is cleared following software or hardware reset.

85

TABLE 8-COM52C50 CONTROL REGISTER (BITS 0-7)
The Control Register is an eight bit write only register that is cleared to "zero" except for the Software Reset bit. Internal
used by the microprocessor to control the COM52C50. Reset does not affect any of the Control Register bits. The
Following External Reset all bits ofthe Control Register are bits of the Control Register are defined as follows:
BIT
0
1

2

3

4

5
6
7

DESCRIPTION
SOFTWARE RESET
This bit is used by the microprocessor to reset the COM52C50 via a software command. When this bit is cleared,
Internal Reset is asserted and the COM52C50 is reset. This bit should be set to "one" during normal operations.
ENABLE RECEIVE
This bit is used by the microprocessor to enable the Receive Logic in the COM52C50 to function. When this bit is
cleared, the RX BUFFER FULL bit in the Status Register will be disabled. This bit should be set to "one" during
normal operations.
ENABLE TRANSMIT
Data transmission cannot take place via the COM52C50 unless this bit is set to logic "one". When this bit is reset
(disabled), transmission will be disabled only after the previously written data has been transmitted. (This simply
disables loading of the TX Buffer Register).
ENABLE RX DMA
This bit, when set, will enable the RX DMA handshake signal on the COM52C50. When this bit is cleared, the RX
DMA signal on the COM52C50 is kept low.
ENABLE TX DMA
This bit, when set, will enable the TX DMA handshake signal on the COM52C50. When this bit is cleared, the TX
DMA signal is kept low.
DISABLE BIPHASE ERRORS
This bit, when set, will disable the detection of biphase errors in the receive block. This bit is cleared upon power
up and biphase error detection is enabled.
NOT USED-MUST BE ZERO
RESET ERRORS
This bit, when set, will clear the Receive Error Status bits in the Interrupt Status Register (Parity, Biphase,
Overrun). As a result of this, the RX Error bit in the RX Status Register will be cleared. Reset Errors also resets the
TX Underrun status bit in the TX Status Register. No latch is provided in the Control Register for saving the state
of this bit; therefore there is no need for clearing it.

RXDMA
Following an active read command, the host microprocessor would initialize the RX DMA channel and enable RX
DMA by writing a one in the Control Register bit 3. The
COM52C50 will automatically generate the RX DMA
Request signal as soon as a received frame is moved from
the Receiver Shift Register to the Receiver FIFO. At this
time, the DMA channel will initiate a Read Receive Buffer
cycle which in turn will be used as an automatic DMA
Acknowledgment. When a new frame arrives and is ready
A TIL clock can also be used to supply the clock signal to to be read by the DMA channel, the COM52C50 will assert
the COM52C50. This is done by supplying a TIL level clock the RX DMA Request signal and inform the DMA channel of
to the XTAL1 pin of the COM52C50 along with a 390 ohm the availability of the next word. The Receiver FIFO will be
resistor from the XTAL 1 pin to Vcc. The XTAL2 pin should in use during DMA operations. This gives the DMA channel
not be connected when an external clock is supplied. (see a maximum of three frame times for DMA latency. On the
figure 19, RECOMMENDED EXTERNAL TTL CLOCK average, however, the DMA channel must be able to keep
CONNECTION)
up with the COM52C50 byte rate.

THE COM52C50 ON CHIP CRYSTAL OSCILLATOR
The COM52C50 incorporates an on chip crystal oscillator.
A 16 MHZ parallel resonant crystal is connected to the
XTAL 1 and the XTAL2 pins of the COM52C50 along with a
1.0 MOhm resistor across the crystal and two 22pf
capacitors from each node of the crystal to ground. (see
figure 18, CONNECTION DIAGRAM FOR PARALLEL
RESONANT CRYSTAL)

DMA OPERATION
The COM52C50 features two independent DMA Request
signals. These signals are provided to allow the
COM52C50 to interface to one or two channels of a DMA
controller such as that of the 80188 and the 80186. Each of
the RX DMA and TX DMA request signals can be
individually enabled via software commands in the Control
Register. DMA interface is most useful when moving blocks
of data following an activate read or an activate write
command.
86

TXDMA
When transmitting blocks of data, the host microprocessor
would initialize the TX DMA channel and enable TX DMA
by writing a one in the Control Register bit 4. The
COM52C50 will automatically generate the TX DMA
Request signal when the TX Buffer is empty. YVhen the DMA
channel performs a write cycle to the COM52C50 TX
Buffer, the TX DMA Request signal will be inactive until the
TX Buffer becomes empty again. After writing the last data
frame to the TX Buffer, the host microprocessor can disable
the TX DMA Request signal by writing to the Control
Register.

TABLE 9-COM52C50 MODE REGISTER DESCRIPTION (BITS 0-7)
DESCRIPTION

BIT
0

NORMALILOOPBACK MODE
This bit when set will put the COM52C50 in loopback mode. When in loopback mode, bit 1 of the Mode Register
specifies Internal or Externalloopback modes.
NORMAL OPERATION

0
1

1

LOOPBACK MODE

EXTERNAL/INTERNAL LOOPBACK
This bit specifies External or Internal loopback Modes. When bit 0 of the Mode Register specifies normal mode of
operation, this bit is a don't care.
0

2

EXTERNAL LOOPBACK

1

INTERNAL LOOPBACK

EVEN/ODD RX PARITY
This bit specifies Even or Odd parity for the receive section 01 the COM52C50.
EVEN RX PARITY

0
3

ODD RX PARITY

1

EVEN/ODD TX PARITY
This bit specifies Even or Odd parity for the transmit section of the COM52C50.
0

4

EVEN TX PARITY

1

ODD TX PARITY

NORMALITEST MODE
This bit when set puts the COM52C50 in a VLSI test mode. This bit is cleared upon Reset and should be cleared
for normal operation.
NORMAL OPERATION

0
5

1

TEST MODE

TX ENABLE 250ns/16ps
This bit controls the amount of time the Transmit Enable Signal will remain active after the last TX bit is shifted out.
When set to "zero", the TX Enable signal goes inactive after 250ns following the last TX data bit. When set to
"one", the TX Enable signal goes inactive after 16ps following the last TX data bit. This can be used to drive the
Twinax Cable after a transmission in order to reduce line reflection effect.
TX enable 250ns

0

1

TX enable 16ps

EOM/Auto 111

6

This bit determines if Automatic 111 address should be inserted on a transmitted message upon transmitter
underrun. When this bit is a "zero", the microprocessor has to write to TX Buffer EOM to force a 1~ 1 address on
the last frame of transmitted data.
Auto 111
0
EOM 111
1
7

NORMALITEST MODe
This bit when set puts the COM52C50 in a VLSI test mode. This bit is cleared upon Reset and should be cleared
for normal operation.
0

NORMAL OPERATION

1

TEST MODE

Following RESET, the mode register will be cleared to all "zero's" and the default Mode Setting will be:
BITO -

0

NORMAL OPERATION

BIT 1 -

0

EXTERNAL LOOPBACK

BIT 2 -

0

EVEN RX PARITY

BIT 3 -

0

EVEN TX PARITY

BIT4 -

0

NORMAL OPERATION

BIT 5 -

0

TX ENABLE .250

BIT 6 -

0

EOM111

BIT 7 -

0

NORMAL OPERATION

87

ELECTRICAL CHARACTERISTICS
MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range ............................................................• 0 to 70°C
Storage Temperature Range .................................................•............• -55 to 150°C
Lead Temperature (soldering, 10 seconds) ................................................... +325°C
Positive Voltage on any pin ......•......•...•...........•..........•.....•.•.•.•.•..•........ Vee + 0.3V
Negative Voltage on any pin, with respect to ground ......•........•.•..•.•.•.•.•............... -0.3V
Maximum Vee ..................•.••.•.•.......•...................•••......•.....•........ +7.0V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operations of the device at these or any other condition above those indicated in the operational sections of this
specifications is not implied.
NOTE: When powering this device from the laboratory or system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or
"glitches" on their outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line
may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.

±5~1 P!.~IiiARYJ

TABLE 11-ELECTRICAL CHARACTERISTICS IT, • O·C 10 '7O"C, Vtc • '5V
FIG. NO.

PARAMETER

SYMBOL

DC CHARACTERISTICS
LOW INPUT VOLTAGE

V,L ,

HIGH INPUT VOLTAGE

V'H'

LOW INPUT VOLTAGE
HIGH INPUT VOLTAGE
LOW OUTPUT VOLTAGE
HIGH OUTPUT VOLTAGE
LOW OUTPUT VOLTAGE
HIGH OUTPUT VOLTAGE
INPUT LEAKAGE CURRENT
INPUT CAPACITANCE
POWER SUPPLY CURRENT

V,L 2
V,H 2
VOL'
VOH'
VOL 2
VOH 2
IL
C'N
Icc

FIG. NO.

PARAMETER

SYMBOL

MIN

TYp.

MAX
0.8

2.0

I,;...~ /lOr..,.,
V
V

1.0
Vcc-0.5V
0.4
2.4
3.0
3.0

MIN

±10
25
20

30

TYp·

MAX

V
V
V
V
V
V
pA
pF
mA
UNITS

AC CHARACTERISTICS
Fig.
Fig.
Fig.
Fig.
Fig.

.

3
3
3
3
3

Fig. 4
i=ig.4
Fig. 4
Fig. 4
Fig. 4
Fig. 5

Fig. 6

Fig. 7
Fig. 8

WRITE CYCLE
Address Setup Time
Address Hold Time
WR Pulse Width
Data Setup Time
Data Hold Time
READ CYCLE
Address Setup Time
Address Hold Time
RD Pulse Width
Tzx

t,
t2

..to

Is

ns
ns
ns
ns
ns

50
0
150
75
10

,
ns
ns
ns
ns
ns

T"

t9
t,D

50
0
150
0
0

READ WRITE INTERVAL

t'3

100

INTERRUPT
ACKNOWLEDGE TIMING
Read Int. Status Reg. to
INT inactive

t"

300

ns

t,S

200

ns

t,.

200

ns

DMA ACKNOWLEDGE
TIMING
Read RX Buffer to
RXDMA inactive
Write TX Buffer to
TXDMA inactive

Is
h

Is

80
80

ns

88

•

;~.
Except TLL Input
Clock
Except TTL Input
Clock
TTL Clock Input
TTL Clock Input
IOL= 3.5ma
IOH = 200pa
For Clock Output
For Clock Output

COMMENTS

FIG. NO.
Fig.
Fig.
Fig.
Fig.
Fig.

9
9
9
9
9

SYMBOL PARAMETER

SYMBOL

TTL CLOCK INPUT TIMING
Inpul Clock fall lime
Inpul Clock rise lime
Inpul Clock high lime
Inpul Clock low lime
Inpul Clock period

TYP'

MIN.

MAX

UNITS

10
10

120
121
1.2
123

ns
ns
ns
ns
ns

20
20
62.5

I..

COMMENTS

Vcc-1.0V
@0.6V
@1.5V

CLOCK OUT TIMING
Fig.
Fig.
Fig.
Fig.
Fig.

10
10
10
10
10

Fig. 11
Fig. 11
Fig.
Fig.
Fig.
Fig.
Fig.

11
11
11
11
11

Clock Oul fall lime
Clock Oul rise lime
Clock Oul high lime
Clock Oul low lime
Clock Oul period

10
10

129

125

ns
ns
ns
ns
ns

100

1500

ns

10,
102
103

250
250
250
500
1000

ns
ns
ns
ns
ns
ns
ns

1.5
126
127

55
55

I.e

TX DATA TIMING
WRlo Ix Buffer
TX ENABLE
TX ENABLE aclive 10
TX DELAY
DTX 10 TX ENABLE inaclive
TX 10 DTX delay
TX, DTX half bil cell
TX, DTX full bil cell
TX, DTX rise lime
TX, DTX fall lime

b.
105

10
10

RX DATA TIMING
RX half bil cell pulse widlh
RX bil cell pulse widlh

Fig. 12
Fig. 13

RESET TIMING
Inlernal Resel pulse widlh
Exlernal Resel pulse widlh
Inpul Clock Frequency

1.0
1.0

1.0
1.,

j1S

MHZ

=5.0 V

\

/

I

1

~I

14
I

t,

~1

I

~

~I

.1

I-

~

I
{

1
II

D-IN

j1S

16

'ALL TYPICAL VALUES ARE AT 25°C AND Vce

A-IN

ns
ns

500
1000

--------------4~
I

I.

I

1
Is'

·1- .1
I

~I
'

Fig. 3-PROCESSOR WRITE COM52C50 CYCLE

89

@50pFmax
@50pFmax
@50pFmax
@50pFmax
@50pfmax

(Jitter Tolerance ±20%)

\L....-_ _ _----I/
I

A-IN

I

-------*~------------~¥~------,
,"

Is

b'
P

I

I

~~-I-------

\

~

dI

I

I I

D-OUT

h

!-lI
~I.----------~.I
Is

-------(~_ _ _ _ _ ____I)~:- - - - Fig.4-PROCESSOR READ COM52C50 CYCLE

\

I

,

1""----------'\

~----~I

/

I~----~

I

,

Fig. 5-PROCESSOR ACCESS COMS2C50 REPETITION

INTn

I

I
\~-------+--------'

I

1

I..
I

1

RDINT
STATUS REG.

\I
Fig. 6-INTERRUPT ACKNOWLEDGE TIMING

90

114

I

"/
1

-I

I
I
I
I

I

I

/

RXDMA

I

I
1
1
1

t
t15

I"

1

I

RD RX
BUFFER

I

.1
1

\I

I
I

/

I

I

Fig. 7-RX DMA ACKNOWLEDGE TIMING

I
I
I
I

/

TXDMA

I
1

1
1

I~

\'6

1

WRTX
BUFFER

~I

~I
.1

I

1
I
1

I

I

Fig. 8-TX DMA ACKNOWLEDGE TIMING

to.
t22

ClKIN

I

1

--

I

_ _ _ _ O.6V

~----t-

I

1
1to, I

M

111~--.1
tool
to3

""'I·~·I"'·----.,

Fig. 9-TTL INPUT CLOCK TIMING

ClKOUT

Fig. 10-8 MHZ CLOCK OUT TIMING

91

WRITE to
TX BUFFER

~r-----'I--------------~!Ir(----------------------1

1

I

I.

I
I

I"

:

'I

I

1

I I~--;-__----:_---:-_-j( r(----+-1--!I
I

I

1

I

1

H",
HI"
1 I I !

I
I

1 I

I I

H'"
1 I
I

I

TX

1
1
I
I
I
I

TBMT

(

:,..1"...,I
II

I

LJ

I

1

I

~,_ _ _ _ _ _~r-----~(r(------------------------))

I

Fig. 11-TX, DTX, TX ENABLE TIMING

1.0

,

"1Ir------

/
internal

RESET

\\

1/

\

/

\

/

Fig. 12-INTERNAL RESET TIMING

I

I.,

I"

1

external

\

RESET

1
Fig. 13-EXTERNAL RESET TIMING

-,I
1

1
1

2xCLK

TXCLK

TX ENABLE
I+-l---J-l~I~I-t.....-j~Frame Synchronization~_I-t_DO-+l_Dl-+l

TX

----~
Fig. 14- COM52C50 TRANSMIT START TIMING

92

2x ClK

TXClK

TX ENABLE - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----l

LJL..rl

TX

r:rJ

11...Jl......JIL--_ _ _ __

Fig. 15-COM52C50 TRANSMIT END TIMING

RXDATA

_ _ _ _r L . . . . . . J L . . . . r

!

LINE IDLE GOES AWAY

FSD VALID

Fig. 16-COM52C50 RECEIVE START TIMING

L.JLJI'---IcrJ'---IL--L......JILJ"""LJIL--_ _ _ __

RXDATA

PARITYVA~

POll COMMAND DET

I

ID MATCH

!

RX BUFFER FUll
EOM DET

RXOVERN

Fig. 17-COM52C50 RECEIVE END TIMING

xtal2

xtall
+5 V

22 pF

~D~

I.

C

390 Ohm

C . I 22pF
Xtall

Xtal2

10. Mohm

No Connection

C =2 times Crystal load Capacitance

----E)

Fig. 19-RECOMMENDED EXTERNAL TTL CLOCK
CONNECTJON

Fig. 18-CONNECTION DIAGRAM FOR PARALLEL
RESONANT CRYSTAL

93

z

z

~
z

o
~
z

a:

llJ

o

~

~

a:

o

llJ

I-

I-

DD
DO
DD

DD
DD
DD
DO
DO
DO
DO
DO
,~

D

J===========~ ~

:2

o

() a:

r----..,

W

I-

Z

o

o

o

tw

X
X

J=======:J" ~

:2
w

z

a:
a..
C\J

:2

z
z

L()

()

o

~
:2

U

o

...J

«
U
o...J

()

--I

><


C/)

Ki

L()

M

W

:2
w

o

o

:2

:E
III

X

X

~

~

(')

(')

w

W

l-

I-

(J)

(J)

(J)

(J)

:2
£Q

:2
£Q

>-

>-

D

D
Circuit diagrams utilizing SMC products are included as a means of illustrating typical applications; consequently complete
information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is
believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information
does not convey to the purchaser of the products described any license under the patent rights of SMC or others. SMC
reserves the right to make changes at any time in order to Improve design and supply the best product possible.

94

COM 7210

Intelligent GPIB Interface Controller
FEATURES

PIN CONFIGURATION

o All Functional Interface Capability Meeting IEEE
Standard 488-1978
-SH1 (Source Handshake)
-AH1 (Acceptor Handshake)
- T5 or TE5 (Talker or Extended Talker)
-L3 or LE3 (Listener or Extended Listener)
-SR1 (Service Request)
-RL 1 (Remote Local)
-PP1 or PP2 (Parallel Poll) (Remote or Local
Configuration)
-DC1 (Device Clear)
-DT1 (Device Trigger)
-C1-5 ((Controller) (All Functions))
Programmable Data Transfer Rate
016 MPU Accessible Registers-8 Read/8 Write
2 Address Registers
-Detection of MTA, MLA, MSA (My Talk/Listen/
Secondary Address)
-2 Device Addresses
EOS Message Automatic Detection
Command (IEEE Standard 488-78) Automatic
Processing and Undefined Command Read Capability
DMA Capability
Programmable Bus Transceiver I/O Specification
(Works with T.I.IMotorola/lntel)
b 1 to 8 MHz Clock Range
TTL Compatible

T/R1
T/R2

CLOCK
RESET
T/R3
OMAREQ

1
2
3
4
5
6

'-'

~7

CS
AD

8
9
Wi'! 10 (
INT 11
DO 12 [
01 13 (
0214 (
03 15 [
04 16 [
05 17!
0618 C
0719 C
GNO 20 [

o
o

o
o
o
o

D

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Vee

'EOf
NDAC

lilRrn
D1W
[jJOlj

UIITi'

moe

Di05
Di04

om

Iii02
Di01
Sm::i

7i.'I"III
REN

lFC
RS2
RS1
RSO

PACKAGE: 4().pin D.I.P.

o COPLAMOS®n-Channel Silicon Gate Technology

o + 5V Single Power Supply
o 40-Pin DIP
o 8080/85/86 Compatible

o

GENERAL DESCRIPTION
The COM7210 TLC is an intelligent GPIB Interface Controller designed to meet all of the functional requirements
for Talkers, Listeners, and Controllers as specified by the
IEEE Standard 488-1978. Connected between a processor
bus and the GPIB, the TLC provides high level manage-

ment ofthe GPIB to unburden the processor and to simplify
both hardware and software design. Fully compatible with
most processor architectures, Bus Driver/Receivers are the
only additional components required to implement any type
of GPIB intl'lrface.

95

BLOCK DIAGRAM

96

DESCRIPTION OF PIN FUNCTIONS
PIN

1/0

DESCRIPTION

1

T/Rl

0

2

T/R2

0

3

ClK

I

4
5

RST
T/R3

I
0

6

DMAREO

0

7

DMAACK

I

8

CS

I

9

RD

I

10

WR

I

Transmit/Receive Control-Input/Output Control Signal for the GPIB
Bus Transceivers.
Transmit/Receive Control-The functions of TlR2, T/R3 are determined
by the values of TRM1, TRMO of the address mode register.
Clock-(1-8 MHz) Reference Clock for generating the state change
prohibit times Tl, T6, T7, T9 specified in IEEE Standard 488-1978.
Reset-Resets 7210 to an idle state when high (active high).
Transmit/Receive Control-Function determined by TRMI and TRMO of
address mode register (See T/R2).
DMA Request-7210 requests data transfer to the computer system,
becomes low on irlQUt of DMA acknowledge signal DACK.
DMA Acknowledge-(Active low) Signal connects the computer system
data bus to the data register of the 7210.
Chip Select-(Active Low) Enables access to th., register selected by
RSO-2 (read or write operation).
Read-(Active low) Places contents of read register specified by
RSO-2-on DO-7 (Computer Bus).
Write-(Active Low) writes data on DO-7 into the write register specified
by RSO-2.
Interrupt Request-(Active High/low) Becomes active due to any 1 of 13
internal interrupt factors (unmasked) active state software configurable,
active high on chip reset.
Data Bus-8-bit bidirectional data bus, for interface to computer system.
Ground.
Register Select-These lines select one of eight read (write) registers
during a read (write) operation.
Interface Clear-Control line used for clearing the interface functions.
Remote Enable-Control line used to select remote or local control of
the devices.
Attention-Control line which indicates whether data on DIO lines is an
interface message or device dependent message.
Service Request-Control line used to request the controller for service.
Data Input/Output-8-bit bidirectional bus for transfer of message on
the GPIB.
Data Valid-Handshake line indicating that data on DIO lines is valid.
Ready for Data-Handshake line indicating that device is ready for data.
Data Accepted-Handshake line indicating completion of message
reception.
End or Identify-Control line used to indicate the end of multiple byte
transfer sequence or to execute a parallel polling in conjunction with ATN.
+5VDC

11

SYMBOL

~

0

INT

12-19
20
21-23

DO-7
GND
RSO-2

1/0

24
25

IFC
REN

1/0
1/0

26

ATN

1/0

27
28-35

SRO
D101-8

I/O
I/O

36
37
38

DAV
NRFD
NDAC

1/0
1/0
1/0

39

EOI

I/O

40

Vee

I

FUNCTIONAL DESCRIPTION
Introduction
The IEEE Standard 488 describes a "Standard Digital
Interface for Programmable Instrumentation" which, since
its introduction in 1975, has become the most popular means
of interconnecting instruments and controllers in laboratory, automatic test and even industrial applications. Refined
over several years, the 488-1978 Standard, also known as
the General Purpose Interface Bus (GPIB), is a highly
sophisticated standard providing a high degree of flexibility
to meet virtually most all instrumentation requirements. The
COM 721 0 TLC implements all of the functions that are
required to interface to the GPIB. While it is beyond the
scope of this document to provide a complete explanation
of the IEEE 488 Standard, a basic description follows:
The GPIB interconnects up to 15 devices over a common
set of data control lines. Three types of devices are defined
by the standard: Talkers, Listeners, and Controllers,
although some devices may combine functions such as
Talker/Listener or Talker/Controller.

Data on the GPIB is transferred in a bit parallel, byte serial
fashion over 8 Data I/O lines (0101-0108). A 3 wire handshake is used to ensure synchronization of transmission and
reception. In order to permit more than one device to receive
data at the same time, these control lines are "Open Collector" so that the slowest device controls the data rate. A
number of other control lines perform a variety of functions
such as device addressing, interrupt generation, etc.
The COM7210 TLC implements all functional aspects of
Talker, Listener and Controller functions as defined by the
488-1978 Standard, and on a single chip.
The COM 721 0 TLC is an intelligent controller designed to
provide high level protocol management of the GPIB, freeing
the host processor for other tasks. Control of the TLC is
accomplished via 16 internal registers. Data may be transferred either under program control or via DMA using the
TLC's DMA control facilities to further reduce processor
97

overhead. The processor interface of the TLC is general in
nature and may be readily interfaced to most processor
lines.
In addition to providing all control and data lines necessary
for a complete GPIB implementation, the TLC also provides a unique set of bus transceiver controls permitting the

-

REGISTER NAME

a

use of variety of different transceiver configurations ·for
maximum flexibility.

Internal Registers
The TLC has 16 registers, 8 of which are read and 8 write.

SPECIFICATION

ADDRESSING
R R R W R C
S S S R D S
2 1 0

o

o

I
I
I

I
I
I

Serial Poll Status (3R)

0 1 1 1 0 0

S8

PEND

S6

SS

Address Status (4R)

1 0 0 1 0 0

CIC

ATN

SPMS

LPAS

Command Pass Through (SR)

1 0 1 1 0 0

CPT7

CPT6

CPTS

CPT4

Address 0 (6R)

1 1 0 1 0 0

X

DTO

DLO

ADS-O

I D12
I ERR
CO I LOKC
S4 I S3
TPAS I LA
CPT3 I CPT2
AD4-0 I AD3-0

Address 1 (7R)

1 1 1 1 0 0

E01

DT1

DL1

ADS-1

AD4-1

Data In (OR)

0 0

Interrupt Status 1 (1 R)

0 0 1 1 0 0

Interrupt Status 2 (2R)

0 1 0 1 0 0

1

0

I

I

D17

D16

CPT

APT

INT

SR01

I

D1S

D14

DET

END

LOK

REM

Byte Out (OW)

0 0 0 0 1 0

B07

B06

BOS

B04

Interrupt Mask 1 (1W)

0 0 1 0 1 0

CPT

END

Interrupt Mask 2 (2W)

0 1 0 0 1 0

0

I
I SROI

DET
DMAO

DMAI

Serial Poll Mode (3W)

APT

I
I

D13

D11

DEC

DO

D1

REMC

ADSC

D10

S2

S1

TA

MJMN

CPT1
AD2-0

I CPTO

I AD1-0

I AD3-1 I AD2-1 I AD1-1

B03

B02

B01

DEC

ERR

DO

BOO
DI

CO

LOKC

REMC

ADSC

0 1 1 0 1 0

S8

rsv

S6

SS

S4

S3

S2

S1

. Address Mode (4W)

1 0 0 0 1 0

ton

Ion

TRM1

TRMO

0

0

ADM1

ADMO

Auxiliary Mode (SW)

1 0 1 0 1 0

CNT2

CNT1

CNTO

COM4

COM3

COM2

COM1

COMO

Address 0/1 (6W)

1 1 0 0 1 0

ARS

DT

DL

I

ADS

AD4

AD3

I

AD2

AD1

End of String (7W)

1 1 1 0 1 0

EC7

EC6

ECS

I

EC4

EC3

EC2

I

EC1

ECO I

DI3

DI2

DI1

DIO

I

Data Registers
The data registers are used for data and command transfers between the GPIB and the microcomputer system.
DATA IN (OR)

I

DI7

I

DI6

I

DIS

DI4

Holds data sent from the GPIB to the computer
BYTE OUT (OW)

I~B~0-7-'I~B~0~6-'I~BO~5-'~B~0~4-'~B~0~3-'-B~0~2-'~B70-1-'-B~0~0-'

Holds information written into it for transfer to the GPIB

Interrupt Registers
The interrupt re!;1isters are composed of interrupt status bits,
interrupt mask bits, and some other noninterrupt related bits.

READ
INTERRUPT
STATUS.1 (1 R).

CPT

APT

DET

END

DEC

INTERRUPT
STATUS 2 (2R)

INT

SROI

LOK

REM

CO

ERR

DO

DI

I LOKC I REMC I ADSC

I

WRITE
INTERRUPT
MASK 1 (1W)

CPT

APT

INTERRUPT
MASK 2 (2W)

0

SROI

DET

END

DEC

I DMAO I DMAI

CO

98

ERR

DO

DI

I LOKC I REMC I ADSC

I

Interrupt Status Bits

INT
CPT
APT
DET
END
DEC
ERR
DO
DI
SRQI
LOKC
REMC
ADSC
CO

There are thirteen factors which can generate an interrupt from the COM 721 0, each with their own status bit and
mask bit.

OR of All Unmasked Interrupt Status Bits
Command Pass Through
Address Pass Through
Device Trigger
End (END or EOS Message Received)
Device Clear
Error
Data Out
Data In
Service Request Input
Lockout Change
Remote Change
Address Status Change
Command Output

The interrupt status bits are always set to one if the interrupt
condition is met. The interrupt mask bits decide whether the
INT bit and the interrupt pin will be active for that condition.

Noninterrupt Related Bits

LOK
REM
DMAO
DMAI

Lockout
Remote/Local
Enable/Disable DMA Out
Enable/Disable DMA In

Serial Poll Registers
READ

SERIAL POLL
STATUS (3R)

S8

I PEND I

S6

S5

S4

S3

S1

SO

S3

S2

S1

I SPMS I LPAS I TPAS

LA

TA

I MJMN I

I TRM1 I TRMO I

0

WRITE

SERIAL POLL
MODE (3W)

S8

rsv

I

S5

S6

S4

The Serial Poll Mode register holds the STB (status byte:
S8, S6-S1) sent over the GPIB and the local message rsv
(request service). The Serial Poll Mode register may be read
through the Serial Poll Status register. The PEND is set by
rsv = 1,andclearedbyNPRS'rsv = 1 (NPRS = Negative
Poll Response State).

Address Mode/Status Registers
ADDRESS STATUS (4R)

CIC

ATN

ADDRESS MODE (4W)

ton

Ion

The Address Mode register selects the address mode of
the devic.e and also sets the mode for T/R3 and T/R2 the
transceiver control lines.
The functions of T/R2, T/R3 terminals (2 and 5) are determined as below by the TRM1, TRMO values of the address
mode register.
T/R2
EOIOE
CIC
CIC
CIC
EOIOE = TACS

T/R3
TRIG
TRIG
EOIOE
PE

+

SPAS

TRM1
0
0
1
1

TRMO
0
1
0
1

0

I ADM1 I ADMO 1

CIC = CIDS + CADS
This denotes if the controller interface function is active or
not.
When "1 ": ATN = output. SRQ = input
When "0": ATN = input, SRQ = output
PE = CIC + PPAS
This indicates the type of bus driver connected to 0108 to
0101 and DAV lines.
When "1": 3 state type
When "0": Open collector type
TRIG: When DTAs state is initiated or when a trigger auxiliary command is issued, a high pulse is generated.

+ CIC· CSBS

Upon RESET, TRMO and TRM1 become "0" (TRMO =
TRM1 = 0) and local message port is provided, so that TI
R2 and T/R3 both become "LOW:'

This denotes the input/output of EOI terminal.
When "1": Output
When "0": Input

99

Address Modes
ton
1

Ion
0

ADM1
0

ADMD
0

0

1

0

0

0

0

0

1

ADDRESS
MODE
Talk only
mode
Listen only
mode
Address mode 1

0

0

1

0

Address mode 2

0

0

1

1

Address mode 3

r8

@

@

CONTENTS OF
ADDRESS (1)
REGISTER

CONTENTS OF
ADDRESS (D)
REGISTER

Address Identification Not Necessary
(No controller on the GPIB)
Not Used
' Major talk address or
Major listen address
Primary address
(talk or listen)
Primary address (major
talk or major listen)

Minor talk address or
Minor listen address
Secondary address
(talk or listen)
Primary address (minor
talk or minor listen)

Combinations other than above indicated Prohibited.
Notes:

@

@
@

-Either MTA or MLA reception is indicated by coincidence of either address with the received address.
Interface function T or L.

-Address register 0 = primary, Address register 1 =
secondary, interface function TE or LE.
-CPU must read secondary address via Command
Pass Through Register interface function (TE or LE).

Address Status Bits
ATN
LPAS
TPAS
CIC
LA

TA
MJMN

Data Transfer Cycle (device in CSBS)
Listener Primary Addressed State
Talker Primary Addressed State
Controller Active
Listener Addressed

SPMS

Talker Addressed
Sets minor TIL address Reset = Major TIL
address
Serial Poll Mode State

Address Registers
ADDRESS 0 (6R)

x

DTO

DLO

ADDRESS 1 (7R)

EOI

DT1

DL1

ADDRESS 0/1 (6W)

ARS

DT

DL

I ADS-O I AD4-0 I AD3-0 I AD2-0 I AD1-0 I
I ADS-1 I AD4-1 I AD3-1 I AD2-1 I AD1-1 I
I ADS I AD4 I AD3 I AD2 I AD1 I
Address settings are made by writing into the address 0/1
register. The function of each bit is described below,

The TLC is able to automatically detect two types of
addresses which are held in address registers 0 and 1. The
addressing modes are outlined below.

Address 0/1 Register Bit Selections
ARS
DT
DL

-Selects which address register, 0 or 1
-Permits or Prohibits address to be detected
as Talk
-Permits or Prohibits address to be detected
as Listen

AD5-AD1 -Device address value
EOI
,-Holds the value of EOI line when data is
received

Command Pass Through Register
COMMAND PASS
THROUGH (SR)

I

CPT7

I

CPT6

I

CPTS

I

CPT4

I

The CPT register is used such that the CPU may read the
010 lines in the cases of undefined command, secondary

CPT3

I

CPT2

I

CP1

I

CPTO

I

address, or parallel poll response.

End of String Register
ENDOF
STRING (7W)

I

EC7

I

EC6

I

ECS

I

EC4

This register holds either a 7- or a-bit EOS message byte
used in the GPIB system to detect the end of a data block,

I

EC3

I

EC2

I

EC1

I

ECO

I

AuxModeRegisterAcontrolsthespecificuseofthisregister,

Auxiliary Mode Register
AUXILIARY
MODE (SW)

CNT2

CNT1

CNTO

I COM4 I COM3 I COM2 I COM1 I COMO I
100

This is a multipurpose register. A write to this register generates one of the following operations according to the values of the CNT bits.
CNT

COM

2 1 0 4 3 2 1 0
0 0 0 C, C, C, C, Co
0 0 1

o F, F, F,

Fo

0 1 1 U S P, P, P,
1 0 0

A" A, A, A,

Ao

1 0 1 B, B, B, B, Bo
1 1 0

BIT
NAME

o

0 0 E, Eo

OPERATION
Issues an auxiliary command
specified by C. to Co.
The reference clock frequency is
specified and T" T., T7 , T. are
determined as a result.
Makes write operation to the parallel
poll register.
Makes write operation to the aux.
(A) register.
Makes write operation to the aux.
(B) register.
Makes write operation to the aux.
(E) register.

A,

0
1

Prohibit
Permit

A,

0
1

Prohibit
Permit

A,

0
1

7bitEOS
8bitEOS

Auxiliary B Register

iepon

-

BIT
NAME

00010

crst

-

00011
00100
00101

rrfd
trig
rll

-

00110
00111

seoi
nvid

-

01111

vid

-

Bo

OXOOl
10000
10001

sppf
gts
tca

-

10010
11010

tcs
tcse

-

10011
11011

Itn
Itnc

-

11100
11101
lXll0
lXlll
10100

lun
epp
sifc
sren
dsc

-

Immediate Execute ponGenerate local pon
Message
Chip Reset-Same as
External Reset
Release RFD
Trigger
Return to Local Message
Generation
Send EOI Message
Non Valid (OSA reception)Release DAC Holdoff
Valid (MSA reception, CPT,
DEC, DET)-Release DAC
Holdoff
Set/Reset Parallel Poll Flag
Go To Standby
Take Control
Asynchronously
Take Control Synchronously
Take Control Synchronously
on End
Listen
Listen with Continuous
Mode
Local Unlisten
Execute Parallel Poll
SeVReset IFC
SeVReset REN
Disable System Control

Makes the 8 bits/7 bits of EOS
register the valid EOS message.

1 0 1 B4 B3 B2 B, Bo

The Auxiliary B Register is much like the A Register in that
it controls the special operating features of the device.

o 0 0 C4 Cs C2 C1 Co

Auxiliary Commands
COM
43210
00000

FUNCTION
Permits (prohibits) the setting of
the END bit by reception of the
EOS message.
Permits (prohibits) automatic
transmission of END message
simultaneously with the
transmission of EOS message
TACS.

B,

1

B,

Permit
Prohibit

0
1

B,

Permit
Prohibit

~

0

0
1
0

T,
(high-speed)
T,
(low-speed)
INT
INT
ist

1

= SROS

B,
0

ist

= Parallel
Poll Flag

Auxiliary E Register

FUNCTION
Permits (prohibits) the detection
of undefined command. In other
words, it permits ~rohibitS)
the setting of the PT bit on
reception of an undefined
command.
Permits (prohibits) the
transmission of the END
message when in serial poll
active state (SPAS).
T, (high speed) as T, of
handshake after transmission of
2nd byte following data
transmission.
~cifies the

active level of

INTpin.
SROS indicates the value of ist
level local message (the value of
the parallel poll flag is ignored).
SROS = 1 ... ist = 1.
SROS = 0 ... ist = O.
The value of the parallel poll flag
is taken as the ist local message.

1 1 0 0 0 0 E1 Eo

This register controls the Data Acceptance Modes of the
TLC.
BIT
Eo
E,

FUNCTION
1
0
1
0

Enable
Disable
Enable
Disable

DAC Holdoff by initiation of DCAS
DAC Holdoff by initiation of DTAS

Internal Counter 0 0 1 0 Fs F2 F1 Fo

Parallel Poll Register

The internal counter generates the state change prohibit
times (T" T6 , T7 , T9 ) specified in the IEEE std 488-1978 with
reference to the clock frequency.

The Parallel Poll Register defines the parallel poll response
oftheCOri!l7210.

Auxiliary A Register

o

1 0 0 A4 As A2 A, Ao

Of the 5 bits that may be specified as part of its access word,
2 bits control the GPIB data receiving modes of the 7210
and 3 bits control how the EOS message is used.
A,
0
0
1
1

A.
0
1
0
1

iP'~~~lji'~~,s(D16\'~16108J

I I

SPECIFYING STATUS BIT
POLARITY
S = 1: IN PHASE
S = 0: REVERSE PHASE

DATA RECEIVING MODE
Normal Handshake Mode
RFD Holdoff on all Data Modes
RFD Holdoff on End Mode
Continuous Mode

{ U = 1: NO RESPONSE TO PARALLEL POLL
U = 0: RESPONSE TO PARALLEL POLL
101

~
A18-8

rrDECDDER~

I

I

I

AD7-8

I,;)"

.<~
101M
8085

RD
WR
ALE

RESET OUT

0

I\)

CLK
RST7.5

~
,!f
RST 6.5

INTo
.

6
0

~ ~

Oil uv (;
~
~

(J)

~I:EI ~ ~
~10:D~rn

~

en

COM7210

RST 5.5 WDMAREQ

•. 1
RESrlN I

~I:EI
~ 0
o::orn5

TIMER OUT

i5MAACK
T/R3-1

"H"

8155

m

1

-i 0
ml

~

m
~

MINIMUM 8085 SYSTEM
WITH COM7210

8355

Z

DEVICE CONTROL

I

~Q

~
- 0~I-01 ~ ~ 0 -n,;
0
~
en;;;;:1 :E~m~mI
m
~

o

-i

PA7-O, P87-O

CE/--"H"
IORI--"H"

~

[SWI~~HES]

J

DISPLAY

COM7210

GPIB

MC344SAX4

1510a
Q!.Qz.

~
01 5
i5i54

15m3
010 2
01°1
T/RI
T/R3 (EOIOEI

m

l5Ai7
mm:5

Nl5Ac"

T/R2 (CICI

mr
AT1iI"

lIDi
~

DATA A
DATA B
OATAC
DATA 0

BUS A
BUS B
BUS C
BUS 0

S/RA_O

PEA-O

DATA A
DATA B
OATAC
DATA 0
S/RA_O

BUSA
BUS B
BUSC
BUS 0
PEA-O

0104
01°3
01°2
010 1

BUS A

EOI

H>-ri>

S/RA
DATA A
S/RB
OATAB
I - S/Rc
OATAC
' - - - S/Ro
DATA 0

S/RA
r-£>- DATA
A

BUS B

OAV

BUSC

NRFO

BUS 0
PEA-O

NOAC

BUS A

SRO

L - - S/RB
OATAB
;- S/Rc
OATAC
~ SIRo
OATAO

BUS B

ATN

BUSC

REN

BUS 0
PEA-O

IFC

TT

.. H· .. ·L ..

Note:

"L"

In this example. high-speed data transfer cannot be made since the bus
transceiver is of the open collector type (Set B,
0).

=

Os

Ba

DI~

07
06
05
04
03

B7
B6
B5
SN75160 B4
B3
B281-

5rn5

i5TCl4

0103

5i02

oro,

02
01

T/R3 (PEl

PE

COM7210

--

5iOa
llTCi6

--

TE

,
I

T/RI

T/R2 (CICI

SRQ
ATN

Em
l5Ai7
NRFO
NOAC

"'"
REN
Note:

OIOS
01°7
01°6
01°5

r---£>o----

OPIB

TE
DC

-

SRO
ATN
EOI SN75161
OAV
NRFO
NOAC
IFC
REN

-

--

--

1---

=

In the case of low-speed data transfer (B,
0). the T/R'Jin can be used as a
TRIG output. The PE input of SN75160 should be cleare to "0."

MINIMUM 8085 SYSTEM
WITH COM 7210 (CONT.)

103

ELECTRICAL CHARACTERISTICS
MAXIMUM GUARANTEED RATINGS (T. = 25°C)
PARAMETER

SYMBOL

Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature

Vee
V,
Va
Tot

1'"

RATINGS

UNIT

-0.5 - +7.0
-0.5-+7.0
-0.5- +7.0
0- +70
-65- +125

V
V
V
°C
°C

DC CHARACTERISTICS (T. = 0 to + 70°C, Vee = 5V ± 10%)
PARAMETER

Input Low Voltage
Input High Voltage
Low Level
Output Voltage
Hi~ Level

utput Voltage

High Level
Output Voltage
(INTPin)
Input Leakage
Current
Output Leakage
Current
Supply Current

SYMBOL

LIMITS
TYP

MIN

-0.5
+2.0

V"
V,H

UNIT

+0.8
Vee + 0.5

V
V

+0.45

V

10L = 2mA
(4 mA: T/R1 Pin)

V

10H = - 400 fJoA
(Except INT)
10H = - 400 fJoA

VOL
+2.4

VOH1

TEST CONDITIONS

MAX

+2.4
V

VOH2
+3.5

10H = -50 fJoA

III

-10

+10

fJoA

V,N = OV - Vee

10L
Icc

-10

+10
+180

fJoA
mA

VOUT = 0.45V - Vee

MAX

UNIT

10
15
20

pF
pF
pF

CAPACITANCE (T. = 25°C, Vee = GND = OV)
PARAMETER
I~ut

Capacitance
Ou~ut Capacitance
I/O Capacitance

SYMBOL

LIMITS
TYP

MIN

C'N
COUT
CliO

TEST CONDITIONS

f = 1 MHz
All Pins Except Pin Under Test Tied to
ACGround

CS, RS2-0

---+-----ol t-o---tRR - - - . . - (

1,..._ _ _ _ _ _ _ _ _.
~---tRV---~

07-0

\l
OMAREQ

tAKO

~k'Q~~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ ____

TIMING DIAGRAM

104

AC CHARACTERISTICS, ~T,

= 0 to 70°C, Vee = 5V'±

10%)

LIMITS
PARAMETER
EOI i --+010
EOI i --+ T/R1 i
EOI i --+T/Rli
ATN i --+ NDACi
ATNi --+ T/R1 i
ATN i --+ T/R2i
DAV i --+ DMAREQ
DAV i --+ NFRD i
DAV j --+NDACT
DAVi --+ NDAC i
DAVi --+DRFD i

SYMBOL
tECDI

MIN

MAX
250
155
200
155
155
200
600
350
650
350
350

tEOT11
tEOT12
tATND
tATTl

tATT2
tOVRQ

tOVNRl

tOVNDl

tovND2
tOVNR2

RD i --+NRFD i

tANA

UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

500

ns

NDAC T--+ DMAREQ T

tNDRQ

400

ns

NDAC i --+ DAVi

tNODV

350

ns

WR i--+ 010

tWD!

250

ns

NRFD i--+ DAV i

tNRDV

350

ns

WRT --+ DAV i

tWDv

830
+tSYNC

ns

TRIG
Pulse Width

hR'G

Address Setup to RD

tAA

Address Hold from RD
RD Pulse Width
Data Delay from Address
Data Delay from RD i
Output Float Delay from RD T
RD Recovery Time
Address Setup to WR
Address Hold from WR
WR Pulse Width
Data Setup to WR
Data Hold from WR
WR Recovery Time
DMAREQ j Delay from DMAACK
Data Del,ay from DMMCK

tAA
tAA
tAD
tAD
tDF
tAv
tAW
tWA
tww
tow
two
tAV

CS, RS2 - 0

50

ns

85
0
0
170

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

250
150
80

0
250
0
0
170
150
0
250

130
200

tAKRQ
tAKD

=t='AW~

_________~II-o:---tww

t=tow

--------------~X

TIMING DIAGRAM

105

RSO - RS2
CS

3ftWA~X
_______--.,

"'--------

07 - 0

CONDITIONS
PPSS --+ PPAS, ATN = True
PPSS --+ PPAS, ATN = True
PPAS --+ PPSS, ATN = False
AIDS --+ ANRS, LIDS
TACS + SPAS --+ TAOS, CIDS
TACS + SPAS --+ TAOS, CIDS
ACRS --+ ACDS, LACS
ACRS--+ACDS
ACRS --+ ACDS --+ AWNS
AWNS--+ANRS
AWNS --+ ANRS --+ ACRS
ANRS--+ACRS
LACS, 01 reg, selected
STRS --+ SWNS --+ SGNS,
TACS
STRS --+ SWNS --+ SGNS
SGNS --+ SDYS, BO
reg, selected
SDYS --+ STRS, T, = True
SGNS --+ SDYS --+ STRS
BO reg, selected, RFD = True
NF = fc = 8MHz,
T, (High Speed)

tRV

twO:

.}-

)(~_.===========

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for 'construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

106

COM78C802
PRELIMINARY

Two-channel Universal
Asynchronous Receiver/Transmitter
Dual UART
FEATURES

PfN CONFIGURATION

D Two independent full duplex serial data lines
DCD1
RXD,
N/C
DL7
DL,
DL,
D14
ROY
RST
VSs.

D Programmable baud rates individually selectable for
each line's transmitter/receiver (50 to 19,200 baud)

D Summary registers that allow a single read to detect a
data set change or to determine the cause of an interrupt on any line

D Triple buffers for each receiver

cs

WR

D Device scanner mechanism that reports interrupt

55,

request due transmitter/receiver interrupts

Db
DL2
DL1
DLo
N/C

D Independently programmable lines for interrupt-driven
operation

D Modem status change detection for Data Set Ready

TXD~

DSRf

(DSR) and Data Carrier Detect (DCD) signals

1
2
3
4
5
6

'-"

10
9
0
11
12
13
14
15
16
17

18
19
20

40 ~ DSR1
39 ~ TXD,
38 N/C
37 N/C
36 ~ VSS,
35 CLK
34 MRST
33 ADD.

P

P
P
P

32
31
30
29
28
27
26
25
24
23
22
21

ADD2
ADD1
ADD~

P IRO
IROTXRX
N/C
IRQ LN.
VDD
VSS2
N/C
RXD,
DCD,

PACKAGE: 40- Pin DIP

D Programmable interrupts for modem status changes

><

I--M("N~O

D Synchronizes critical read-only registers

X

.

~

d:2~~~5i~~~z~

D Single 5V Power Supply
D TTL Compatible
D Compatible with SMC COM78C808 OCTAL UART
and COM78C804 QUART

0::

"'~OOOOOIOO()O

VSS,
TXD,
DSR,
DCD,
RXD,

N/C
N/C
N/C
N/C
OL7
OL,

393837363534333231 3029
40
28
27
26
25

21
4
5
6
7 8 9 10 11 12 13 14 151617

18

VDD
VSS2
N/C
N/C
N/C
N/C
RXD•
.DCD.
DSR,
TXD.
DLo

.:r
JIi5It;Icil'I~I~ I'"
.:r 0J..J
000::a:~
00
0
PACKAGE: 44 Pin PLCC
'Muet be connected together

GENERAL DESCRIPTION
. The COM78C802 Two-channel Asynchronous Receiver/ operations necessary for simultaneous reception and
Transmitter (Dual UART) is a VLSI device for new genera- transmission of asynchronous messages on two independtions of asynchronous serial communication designs and ent lines. Figure 1 is a functional block diagram of the
for microcomputer systems. This device performs the basic COM78C802 Dual UART.
107

ROY

--~---..,

INTERRUPT
SUMMARY
REGISTER

TxOO
RxOO
OSRO
OCOO
DATA SET
CHANGE
SUMMARY
REGISTER

Tx01
Rx01
OSR1
OCD1

FIGURE 1: COM78C802 DUAL UART FUNCTIONAL BLOCK DIAGRAM
TABLE 1-COM78C802 PIN AND SIGNAL SUMMARY
Pln-PLCC Pin-Dip Signal
5-8,15-18 4-7,14-17. Dl<7:0>

Input/Output
input/output

33-37

30-33

ADD<3:0>

input

12

11

CS

input

14

13

OS

input

13

12

WR

input

9

8

ROY

output

10
38
39
20,42

9
34
35
20,40

RESET
MRsrT
ClK
DSR<1:0>

input
input
input
inputs

21,43

1,21

DCD<1:0>

inputs

32
29

29
26

IRQ
IRQlN

output
output

31

28

IRQTxRx

output

19,41

19,39

TxD<1:0>

outputs

22.t44

2,22

RxD<1:0>

input

28
11,27,40

25
10,24,36

Voo
Vss

Input
input

Definition/Function
Data lines <7:0>-Receives and transmits the parallel
data.
Address<3:0>-Selects the internal regi.sters in the Dual
UART. (Pins 36 and 37 must be connected in PlCC package.)
Chip select-Activates the Dual UART to receive and transmit data over the Dl<7:0> lines.
Data strobe-Receives timing information for data transfers.
Write-Specifies direction of data transfer on the Dl<7:0>
lines.
Ready-Indicates when the Dual UART is ready to participate in data transfer cycles.
Reset-Initializes the internal logic.
Manufacturing reset-For manufacturing use.
Clock-Clock input for timing.
Data set ready Monitor data set ready (DSR) signals from
modems.
Data set carrier detect Monitor data set carrier detect
(DC D) signals from modems.
Interrupt request-Requests a processor in,errupt.
Interrupt request line number-Indicates the line number of
originating interrupt request.
Interrupt request transmit/receive-Indicates whether an
interrupt request is for transmitting or receiving data.
Transmit data-Provides asynchronous bit-serial data output streams.
Receive data-Accepts asynchronous bit-serial data input
streams.
Voltage-Power supply voltage + 5 Vdc.
Ground-Ground reference
108

DATA AND ADDRESS
Data lines (DL<7:0»-These lines are used for the parallel transmission and reception of data between the CPU
and the Dual UART. The receivers are active when the data
strobe (OS) signal is asserted. The output drivers are active
only when the chip select (CS) signal is asserted, the data
strobe (OS) signal is asserted, and the write (WR) signal is
deasserted. The drivers will become inactive (high-impedance) within 50 nanoseconds when one or more of the following occurs: the chip select (CS) signal is deasserted,
the data strobe (00) signal is deasserted, orthe write (WR)
signal is asserted.

ADD Line'

Address (ADD<3:0»-These lines select which Dual
UART internal register is accessible through the data I/O
lines (DL <7:0» when the data strobe (00) and chip select
(CS) signals are asserted. Table 2 lists the addresses corresponding to each register. The receiver buffer and transmitter hold!!!9!egister for each line have the same address.
When the (WR) signal is deasserted, the address accesses
the receiver buffer register and when asserted, it accesses
the transmitter holding register.

TABLE 2-COM78C80~ REGISTERS ADDRESS SELECTION
ReadlWrite
Register
<1>
<0>
<3>
<2>
0
0
0
0
0

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
ReadIWrite
ReadIWrite

Line 0 Receiver Buffer
Line 0 Transmitter Holding
Line 0 Status
Line 0 Mode Registers 1,2
Line 0 Command

1
1
1
1
1

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
ReadIWrite
ReadIWrite

Line 1 Receiver Buffer
Line 1 Transmitter Holding
Line 1 Status
Line 1 Mode Register 1,2
Line 1 Command

X
X

1
1

0
0

0
1

Read
Read

Interrupt Summary
Data Set Change Summary

'X= EitherOor 1.

BUS TRANSACTION CONTROL
Chip select (CS)-This signal is asserted to permit data
transfers through the DL<7:0> lines to or from the internal
registers. Data transfer is controlled by the data strobe (OS)
signal and write (WR) signal.
Data strobe (DS)- This input receives timing information
for data transfers. During a write cycle, the CPU asserts the
data strobe signal when valid output data is available and
deasserts the data strobe signal before the data is removed.
During a read cycle, the CPU asserts the data strobe signal
and the Dual UART transfers the valid data. When the data
strobe signal is deasserted, the DL<7:0> lines become a
high impedance.

INTERRUPT REQUEST
Interrupt request IRQ-The IRQ pin is an open drain output. The integral interrupt scanner asserts the IRQ signal
when it has detected an interrupt condition on one of the
two serial data lines.
Interrupt Request transmit/receive (IRQTxRx)-This
signal indicates when the interrupt scanner in the Dual
UART stops and asserts TAO because of a transmitter
interrupt condition (the IRQTxRx signal is asserted) or
because of a receiver interrupt condition (the IRQTxRx signal is deasserted). The signal is valid only while IRQ is
asserted. The state of IRQTxRx signal also appears as bit
oof the interrupt summary register.

Interrupt request line number (IRQLN pins. If the WR signal is signal. The number on this line is valid only while the TAO
asserted during a data transfer (the CS and OS signals signal is asserted. The state of this signal also appears a
asser~, the Dual UART is receiving data from DL <7:0>. bit in the interrupt summary register: IRQLN as bit 1.
If the WR signal is deasserted during a write data transfer, Table 3 shows the line numbers corresponding to settings
the Dual UART is driving data onto the DL<7:0> lines.
of IRQ LN.
109

TABLE 3-COM78C802 INTERRUPT REQUEST
LINE ASSIGNMENTS
IRQ Line

Line

o

o

1

1

SERIAL DATA
Transmit data (TxD<1 :0»-These outputs transmit the
asynchronous bit-serial data streams. They remain at a high
level when no data is being transmitted and a low level when
the TxBRK bit in the associated line's command register is
set.
Receive data (RxD<1 :0»-These lines accept asynchronous bit-serial data streams. The input signals must
remain in the high state for at least one-half bit time before
a high-to-Iow transition is recognized. ( A high-to-Iow transition is required to signal the beginning of a "start" bit and
initiate data reception).
MODEM SIGNALS
Data set ready (DSR<1 :0»-These two input pins, one
for each serial data line on the COM78C802, are typically
connected via intervening level converters to the data set
ready outputs of modems. A TTL low at a DSR pin causes
the DSR bit (bit 7) in the corresponding line's status register
to be asserted. A TTL high at a DSR pin causes the DSR
bit in the corresponding line's status register to be deasserted. A change of this input from high-to-Iow, or low-tohigh, causes the assertion of the data set change
(DSCHNG) bit that corresponds to this line in the data set
change summary register. Changes from one state to the
other and back again that occur within one microsecond may
not be detected.
carrier detect (DCD<1 :0»-These two input pins, one for
each serial data line of the Dual UART, are typically connected through intervening level converters to the received
line signal detect (also called carrier detect) outputs of
modems. A TTL low at a DCD pin causes the DCD bit of the
corresponding line's status register to be deasserted. A
change of this input from high-to-low, or low~to-high, causes
the assertion of the data set change (DSCHNG) bit corresponding to this line in the data set change summary re~­
ister. Changes from one state to the other and back again
that occur within one microsecond may not be detected.
GENERAL CONTROL SIGNALS
Ready (RDY)-The RDY pin is an open drain output. Upon
detecting a negative transition of chip select (CS), the Dual
UART asserts the RDY signal to indicate readiness to take
part in data transfergcles. The RDY signal deasserts after
the trailing edge of CS.I
Reset (RESEn-When the RESET input in asserted, the
TxD<1 :0> lines are asserted and all internal status bits
listed in the "Architecture Summary" discussion are cleared.

POWER AND GROUND
Voltage (VDD)-Power supply 5 Vdc
Ground (Vss)-Ground reference

ARCHITECTURE SUMMARY
The Dual UART functions as a serial-to-parallel, parallel-toserial converter/controller. It can be programmed by a
microprocessor to provide different characteristics for each
of its two serial data lines (stop bits, parity, character length,
split baud rates, etc.)
Each serial line functions the same as a one-line UARTtype device thereby reducing the number of chips and conserving space on communication devices that require multiple communications lines.
An integral interrupt scanner checks for device interrupt
conditions on the two lines. Its scanning algorithm gives
priority to receivers over transmitters. The scanner can also
check for interrupts resulting from changes in modem control signals DSR and DCD.
Line-specific Registers
Each of the two serial data lines in the Dual UART has a set
of registers for buffering data into and out of the line and for
external control of the line's characteristics. These registers are selected for access by selling the appropriate
address on lines ADD<3:0>. Lines ADD<4:3> select one
of the two data lines. Lines ADD<2:0> selects the specific
register for that line. Refer to Table 2 for the register address
aSSignments.
Receiver buffer register-Each line's receiver consists of
a character assembly register and a two-entry FIFO that is
the receiver buffer register. When the RxEN bit in a line's
command register is set, receilted characters are moved
automatically into the line's receiver buffer as soon as they
have been deserialized from the associated communications line. When there are characters in this FIFO, the
RxRDY bit is set in the status register for the line.
The assertion of the RxRDY signal for a line that already
has the RxlE bit of its command register set causes the
interrupt scanner logic to stop and generate an interrupt
condition (the IRQ Signal is asserted). When the receiver
buffer is read, the interrupt condition is cleared (the iRa signal is deasserted) and the interrupt scanner resumes
operation.
If there is another entry in a line's FIFO, the RxRDY bit
remains asserted. When the interrupt scanner reaches this
line again, the assertion of RxRDY causes the scanner to
halt and assert the IRQ again.
Asserting the RESET signal or clearing the RxEN bit initializes the receiver logic of Dual UART. The RxRDY flag is
cleared and the receiver buffer register outputs become
undefined. Any data in the FIFO at that time is lost.

Transmitter holding register-Each line has a writable
transmitter holding register. When the TxEN bit in the line's
command register is set, characters are moved automatically from the output of this register into the transmitter serialization logic whenever the serialization logic becomes idle.
When this register is empty, the TxRDY bit in the line's status register is set. If the transmitter interrupt enable (TxIE)
MISCELLANEOUS SIGNALS
bit in the line's command register is also set, the interrupt
Clock in (CLK)-AII baud rates and internal clocks are scanner logic halts and generates an interrupt condition. If
derived from this input. Normal operating frequency is 4.9152 a character is then loaded into the register, the interrupt is
.MHz ± 0.1 percent and duty cycle is 50 percent ± 5 percent.
cleared and the scanner resumes operation.
110
Manufacturing reset (MRESET)-This Signal is for manufacturing use .only and the input should be connected to
ground for normal operation.

Assertion of the RESET signal initializes the transmitter logic
of the Dual UART. The TxRDY flag is cleared and the transmitter holding register's contents are lost. The transmitter
enable (TXEN)Sbit in the line's command register is also
cleared by RE ET. If at the end of the reset process, the
TxEN is reasserted and TxRDY bit is reasserted. Software
clearin~ of TxEN alone produces results different from the
full RE ET in that the transmitter holding register's contents are not lost; they are transmitted when TxEN is set
again.
Status register-Each line has a read-only status register
that provides information about the current state of the given
line. This register indicates a line's readiness for transmission or reception of data and flags error conditions in its bit
fields. Figure 3 shows the format of the status register. Table
3 lists the flag bits in each status register.

DSR
DCD-----'
F E R - - - - - -......
ORR-------~
PER---------~

TxEMT-------------'
RxRDY------------~

TxRDY----------------'

FIGURE 3: COM78C802 STATUS REGISTERS
(LINE 0:1) FORMAT

TABLE 4-COM78C802 STATUS REGISTERS (LINES 0-1) DESCRIPTION
Bit
7
6
5

4

3

2

1

0

Description
DSR (Data set ready)-This bit is the inverted state of the DSR line.
DCD (Data set carrier detect)-This bit is the inverted state of the DCD line.
FER (Frame error)-Set when the received character currently displayed in the receiver buffer register was not
framed by a stop bit. Only the first stop bit is checked to determine that a framing error exists. Subsequent
reading of the receiver buffer register that indicates all zeros (including the parity bit, if any) can be interpreted
as a Break condition. This bit is cleared by clearing RxEN (bit 2) of the command register, by asserting the
RESET input, or by setting the reset error RERR (bit 4) of the command register.
ORR (Overrun error)-Set when the character in the receiver buffer register was not read before another character was received. Cleared by clearing RxEN (bit 2) of the command register, by asserting the RESET input,
or by setting reset error RERR (bit 4) of the command register.
PER (Parity error)-If parity is enabled and this bit is set, the received character in the receiver buffer register
has an incorrect parity bit. This bit is cleared by clearing RxEN (bit 2) of the command register, by asserting the
RESET input, by setting reset error RERR (bit 2) of the command register, or by reading the current character
in the receiver buffer register.
TxEMT (Transmitter empty)-Set when the transmitter serialization logic for the associated line has completed
transmission of a character, and no new character has been loaded into the transmitter holding ~ister.
Cleared by loading the transmitter holding register, by clearing TxEN (0) of the command register, or by asserting the RESET input.
RxRDY (Receiver buffer ready)-When set, a character has been loaded into the FIFO buffer from the deserialization logic. Cleared by reading the receiver buffer register, by clearing RxEN (bit 2) in the command register,
or by asserting the RESET input.
TxRDY (Transmitter holding register ready)-When set, this bit indicates that the transmitter holding register is
empty. Cleared when the program has loaded a character into the transmitter holding register, when the transmitter for this line is disabled by clearing TxEN (bit 0) in the command register, or by asserting the RESET
input. This bit is initially set when the transmitter logic is enabled by the setting of TxEN (bit 0) and the transmitter holding register is empty. This bit is not set when the automatic echo or remote loopback modes are programmed. Data can be overwritten if a consecutive write is performed while TxRDY is cleared.

Mode registers 1 and 2-These read/write registers control the attributes (including parity, character length, and line
speed) of the communications line.
Each of the two communications lines has two ofthese registers, both accessed by the same address on ADD<3:0>.
Successive access operations (either read or write, in any
combination) alternate between the two registers at that
address by use of an internal pointer. The first operation
addresses mode register 1, the next address mode register
2, and another after that would recycle the pointer to mode
re~is~r 1. The pointer is reset to pOint to mode register 1 by
R S T or by a read of the command register for this line.
These registers should not be accessed by bit-oriented
instructions that do read/modify/write cycles.
Figure 4 shows the format of mode registers 1 and Table 5
describes the function of the register information.
111

~ r;-:R-E~-:.G-T- H-:._~- - - - - - -:. .J- - - 'i

RSRV--------------'
MCIE - - - - - - - - - - - - - - - - - '

FIGURE 4-COM78C802 MODE
REGISTERS 1 (LINE 0:1) FORMAT

TABLE 5-COM78C802 MODE REGISTERS 1 (LINES 0-1) DESCRIPTION
Bit

Description

7,6

STOP-These bits determine the number of stop' bits that are appended to the transmitted characters as
follows. These bits are cleared by asserting the RESET input.
Bits
Stop Bits

5,4

3,2

7

6

0
0
1
1

0
1
0
1

Invalid
1.0
1.5
2.0

PAR CTRL (Parity control)-These bits determine parity as follows and are cleared by asserting the RESET
input. X = either 1 or O.
Bits
Parity 1\tpe

5

4

1
0
X

1
1
0

Even
Odd
Disabled

CHAR LENGTH (Character length)-These bits determine the length (excluding start bit, parity, and stop
bits) of the characters received and sent. Received characters of less than 8 bits are "right aligned" in the
receiver buffer with unused high-order bits equal to zero. Parity bits are not shown in the receiver buffer. The
character length bits are cleared by asserting the RESET input. The character length bits are defined as
follows:
Bit
Bit Length

3

2

0
0
1
1

0
1
0
1

5

6
7
8

1

RSRV (Reserved and cleared by asserting the RESET input.)

0

MCIE (Modem control interrupt enable)-When set and RxlE (bit 5) of the command register is set, the
modem control interrupts are enabled. Refer to the Interrupt Scanner and Interrupt Handling information.
Cleared by asserting the RESET input.

Figure 5 shows the format of mode registers 2 and Table
6 indicates the baud rate selections of the register. Bits 7
through 4 of the mode register 2 control the transmitter
baud rate and bits 3 through 0 control the receiver baud
rate. These registers are cleared by asserting RESET input.

Command register-These read/write registers control
various functions on the selected line. Figure 6 shows'the
format of the command registers and Table 7 describes
the function of the register information.

o
I

I

T
XMIT RATE
RECV RATE

I

"

I

I

I

I

I

I

I

~

I

OPER

.,

RxlE

MODE~

I

RERR

I

TxBR K

RxEN
TxlE
TxEN

FIGURE 6-COM78C802 COMMAND
REGISTERS (LINE 0-1) FORMAT

FIGURE 5-COM78C802 MODE
REGISTERS 2 (LINE 0-1) FORMAT

112

I

TABLE 6-COM78C802 MODE REGISTERS 2 (LINES 0-1) DESCRIPTION
Bit

Description

7:0

XMIT RATE/RECV RATE (Transmitter/Receiver
receiver (bits 3:0) as follows:
Transmitter Bits
Receiver
2
7
5
4
3
6
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
0
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
0
1
1
0
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1

Rate)-Selects the baud rate of the transmitter (bits 7:4) and
Bits
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Nominal
Rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200

Actual
Rate
same
same
109.09
133.33
same
same
same
same
1745.45
2021.05
same
3490.91
same
6981.81
same
same

Error"
(percent)

-

0.826
0.867

-

-

3.03
1.05

-

3.03

-

3.03

-

'The frequency of the clock input (ClK) is 4.9152 MHz. The clock input may vary by 0.1 percent. This variance results in an error
that must be added to the error listed.

TABLE 7-COM78C802 COMMAND REGISTERS (LINES 0-1) DESCRIPTION
Bit

Description

7,6

OPER MODE (Operating mode)-These bits control the operating mode of the channel as follows. These
bits are cleared by asserting the RESET input.
Operating Mode
Bit
7
6
Normal operation
0
0
1
Automatic echo
0
1
0
local loopback
1
Remote loopback
1

5

RxlE (Receiver interrupt enable)-When set, the RxRDY flag (bit 1) of the status register for this line will
generate an interrupt.

4

RERR (Reset error)-When set, this bit clears the framing error, overrun error, and parity error of the status
register associated with this line. This bit is cleared by asserting the RESET input (not self-clearing) ..
TxBRK (Transmit break)-When set, this bit forces the appropriate TxD<1 :0> line to the spacing state at the
conclusion of the character presently being transmitted. When the program clears this bit, normal operation
is restored, and any character pending in the transmitter holding register is moved into the serialization logic
and transmitted. The minimum break length obtainable is twice the character length plus 1 bit time. The
maximum break length depends on the amount of time between the program setting and clearing this bit,
but is an integral number of bit times. This bit is cleared by asserting the RESET inpu).

3

2

RxEN (Receiver enable)-When set, this bit enables the receiver logic. When cleared, it stops the assembling of the received character, clears all receiver error bits and the RxRDY (bit 1) of the status register,
clears any receiver interrupt conditions associated with this line, and initializes ali receiver logic. This bit is
cleared by asserting the RESET input.

1

TxlE (Transmit interrupt enable)-When set, the state of the associated TxRDY flag (bit 0) of the status register is made available to the interrupt scanner logic. When the interrupt scanner logic scans this line, it
determines if the TxRDY flag is asserted and generates an interrupt by asserting the IRQ signal.

0

TxEN (Transmitter enable)-When set, this bit enables the transmitter logic. When cleared, it inhibits the
serialization of the characters that foliow but the serialization of the current character is completed. It also
clears the TxRDY flag (bit 0) of the status register, clears any transmitter interrupt conditions associated with
this line, and initializes ali transmitter logic except that associated with the transmitter holding register. The
character in the transmitter holding register is retained so that XON/XOFF situations can be properly processed. This bit is cleared by asserting the RESET input.

Bits 5 through 0 enable the line's receiver and transmitter,
enable handling of interrupts, initiate the transmission of
break characters, and reset error bits for the line. Refer to
"Interrupt Scanner" and "Interrupt Handling" paragraphs
for detailed interrupt information. Bits 7 and 6 control the
operating mode of the line. The four modes that can be
set are:
113

o Normal operation-The serial data received is assem-

bled in the receiver logic and transferred in parallel to the
receiver buffer register. (The RxEN bit must be set.) Data
to be transmitted is loaded in parallel into the transmitter
hdlding register, then automatically transferred into the
transmitter logic and serialized for transmission. (The
TxEN bit must be set.)

o Automatic echo-The serial data received .is assembled

SUMMARY REGISTERS
The Dual UART contains two register~ that summarize the
current status of all two serial data lines, making it possible
to determine that a line's status has, changed with a single
read operation. These registers are selected for access by
setting the appropriate address on pins ADD <2:0>.
Because the registers are shared by two serial lines, the
Localloopback-The serial data from the RxD input line-selection bits (ADD <4:3» are ignored when these
is ignored and the receiver serial input receives data from . registers are accessed. Refer to "Interrupt Scanner and
the transmitter serial output. The data is assembled into Interrupt Handling" for'detailed interrupt information.
parallel form in the receiver logic (the RxEN bit must be Interrupt summary register-This read-only register indi,
set) and transferred to the receiver buffer register where cates that a transmitter or receiver interrupt condition has
it can be read by the program. Data to be transmitted to occurred, and indicates the line number that generated the
the receiver is loaded in parallel form into the transmitter interrupt. Figure 7 shows the format of the interrupt sumhOlding register from which it is automatically moved into mary register and Table 8 describes register information.
the transmitter logic and serialized for transmission. (The
TxEN bit must be set.) The transmission goes only to the
receiver serial input; the TxD output is held high. As
in normal operation, transmission and reception baud
rates are controlled by the transmitter speed and receiver
speed entries in mode register 2.
Remote loopback-The serial data received on the
IRQ
RxD line is returned to the TxD line without
RAZ - - - - - - - - '
INT LINE NQ _ _ _ _ _ _ _ _ _ _---'
further action. No data is received or transmitted. The
Tx/Rx _ _ _ _ _ _ _ _ _ _ _ _ _---'
RxRDY, TxRDY, and TxEMT flags are disabled. The
TxEN and RxEN bits of the command register are held
FIGURE 7-COM78C802
cleared, causing the transmitter and receiver logic to be
INTERRUPT SUMMARY REGISTER FORMAT
disabled.
into parallel in the receiver logic (the RxEN bit must be
set) and transferred to the receiver buffer register. Arriving serial data is also routed to the line's TxD pin for
serial output. TxEN is ignored and the transmitter logic
is disabled. TxRDY flags and TxEMT indications are
cleared. No transmitter interrupts are generated.

o

o

TABLE 8-COM78C802 INTERRUPT SUMMARY REGISTER OESCRIPTION
Description
IRQ (Interrupt request)-When set, this bit indicates that the interrupt scanner has found an interrupting condition among the two serial lines of the Dual UART. These conditions also result in the Dual UART asserting
the IRQ signal.
RAZ (Read as zero)-Not used
6:2
INT LINE NO (Interrupting line number)-This bit indicates the line number upon which an interrupting condition
1"
was found. Refer to Table 3.
D·
TX/Rx (Transmitlreceive)-This bit indicates whether the interrupting condition was caused by a transmitter (Tx/
Ax equals 1) or a receiver (TX/Rx equals 0). This bit corresponds to the IRQTxAx signal of the Dual UART
and is set when IRQTxRx is asserted.
'Bits 1-0 above represent the outputs of a free-running counter and are valid only when bit 7 is set.
Bit
7

Data set change summary register-When the DSR or
DCD inputs that are associated with a line change state,
the bit corresponding to that line in this read-only register
is set. The current state of the DSR and DCD inputs can

then be obtained from that line's status register, If the state
of a line changes twice within one microsecond, the change
in state may not be detected. Figure 8 shows the format
of the data set change summary register.
When the MCIE bit in a line's mode register 1 is set and
RxlE is also set, the modem control interrupts are enabled
for that line. IfDSCHNG for that line is then set, the interrupt
scanner will halt and assert the IRQ Signal. The data set
change summary register bits are cleared by writing a 1 into
the bit position. A program that uses this register should read
~
and save a copy of its contents. The copy can then be written back to the register to clear the bits that were set. The
DSCHNG1-0
system interrupts should be disabled and writeback should
directly follow the read operation.
Assertion of the RESET signal disables and initializes the
FIGURE 8-COM78C802 DATA SET CHANGE
data set change logic. When the RESET signal is deasSUMMARY REGISTER FORMAT
serted, future changes in DSR and DCD are reported as
they occur.
114

-------------11

INTERRUPT SCANNER AND INTERRUPT HANDLING
The interrupt scanner sequentially checks each line for a
receive interrupt and then checks each one in the same
order for a transmitter interrupt. If the scanner detects an
interrupt condition, it stops and the IRQ signal is asserted.
An interrupt must be serviced by software or no other interrupt request can be posted.
The scanner determines that a line has a receiver interrupt
if the line's receiver buffer is ready and receiver interrupts
are enabled for that line (RxRDY and RxlE = 1) or either of
the line's modem status signals has changed state and both
receiver and modem control interrupts are enabled for that
line (DSCHNG and RxlE and MCIE = 1).
The scanner determines that a line has a transmitter interrupt if the line's transmitter holding the register is empty and
transmitter interrupts are enabled for that line (TxRDY and
TxIE=1).
When the scanner detects an interrupt, it reports the line
number on the IRQ line. The IRQTxRx signal is
asserted for a transmitter interrupt and deasserted for a
receiver interrupt. The appropriate bits are also updated in
the interrupt summary register. The IRQ line is deasserted
and the scanner is restarted for each of the following three
types of interrupt conditions.

o Reading the receiver buffer or resetting the RxlE bit of

the interrupting line for the first type of receiver interrupt
previously described.

o Resetting the MCIE, RxIE, or DSCHNG bit of the interrupting line for the second type of receiver interrupt previously described.

o Loading the transmitter holding register or resetting the
TxlE bit of the interrupting line for transmitter interrupts.

If the scanner was originally stopped by a receiver interrupt
condition, the scanner resumes sequential operation from
where it stopped, thus providing receivers with equal prior-

ity. If the scanner was stopped by a transmitter condition,
the scanner restarts from position 0 (line O's receiver), thus
giving receivers priority over transmitters.

EDGE-TRIGGERED AND LEVEL-TRIGGERED INTERRUPT SYTSTEMS
If the interrupt system of the Dual UART is used only for
generating interrupts for the RxRDY and/or TxRDY flags,
the IRQ line can be connected to a processor having either
edge-triggered or level-triggered interrupt capability. If the
modem control interrupts are being used (MCIE in mode
register 1 = 1), the IRQ line can be connected only to a processor that uses level-triggered interrupts.

MODEM HANDLING
The TxEMT (transmitter empty) bit of the status register is
typically used to indicate when a program can disable the
transmission medium, as when deasserting the request-tosend line of a modem. A typical program will load the last
character for transmission and then monitor the TxEMT bit
of the status register.
The assertion of the TxEMT bit to indicate the transmission
is complete may occur a substantial time after the loading
of the last character. After the last character is loaded, one
character is in the transmitter holding register and one
character is in the serialization logic. Therefore, it will be
two character times before the transmission process is
completed. Waiting for the TxRDY signal to assert' before
monitoring the TxEMT status shortens this by one character time because the TxRDY status bit indicates that there
are no characters in the transmitter holding register. The
times involved are calculated by taking the reciprocal of the
baud rate being used, multiplying by the number of bits per
character (a starter bit-5,6,7, or 8 data bits; plus parity bit
if enabled; and 1,1.5, or 2 stop bits), and multiplying by either
two characters or one, depending on when TxEMT monitoring begins.

TEST
POINT
TEST
POINT

V DD

V DD
IUl

FROM
OUTPUT

,

FROM
,
OUTPUT

I k 52

,

~

,

T

r

[

CC

"....

I kS2

S1 CLOSED: PULL UP
S2 CLOSED: PULL DOWN
S1 AND S2 CLOSED. DIVIDER

LOAD B - THREE-STATE OUTPUTS

LOAD A - STANDARD OUTPUTS

FIGURE 9-COM78C802 OUTPUT LOAD CIRCUITS
115

,
,

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range .................................................................................. O°C to + 70°C
Storage Temperature Range ................................................................................. - 55° to + 125°C
Lead Temperature (soldering, 10 sec.) ................................................................................ + 300°C
Positive Voltage on any 1/0 Pin, with respect to ground .............................................................. Vee + 0.3V
Negative Voltage on any 1/0 Pin, with respect to ground ................................................................. - 0.3V
Maximum Vee ............................................................................................................ + 7V
·Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicaled in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. For example, the bench
power supply programmed to deliver +5 volts may have large voltage transients when the AC power is switched on and off. If this
possibility exists it is suggested that a clamp circuit be used.

TABLE 9-COM78C802
DC ELECTRICAL CHARACTERISTICS
Symbol

Parameter

V'H
V IL

High-level input voltage

V OH

High-level output voltage

Voo=Min.
10H =.3.5 mA for OL <7:0>
IOH=2.0 mA for all
remaining output except IRQ
and ROY

VOL

Low-level output voltage

Voo=Min.
10L = 5.5 mA for OL <7:0>
10L = 3.5 mA for all remaining
outputs

I,H'

Input current at maximum
input voltage

Voo=Max.
V, = Voo(Max.)

III

Input current at miminum
input voltage

Voo=Max.
V,=O.OV

los1

Short-circuit output
current for OL <7:0> all
remainin9.Q!d!puts except
IRQ and ROY

Voo=Max.

Three-state output
current

Voo=Max.
Va = O.4V

Three-state output
current

Voo=Max.
Va = 2.4V

Supply current

Voo=Max.
TA=O°

IOZL2

IOZH2

100

Test Condition

Requirements
Min.
Typ. Max.
2.0

Units
V

Low-level input voltage

0.8

V
V

2.4

0.4

V

10

flA

-10

flA

-50

-180

mA

-30

-110

mA

10

flA

10

flA
mA

15

C,"

Input capacitance

4

pF

C 10 3

Inputloutput capacitance

5

pF

'No more than one ouput should be short circuited at a time, and the duration of the short should not exceed 1 second.
'All three-state output drivers are wired in an I/O configuration. The parameters include the driver and input receiver leakage currents.
'The parameters include the capacitive loads of the output driver and the input receiver.

TIMING PARAMETERS
shows the signal timing for a write cycle to transfer inforFigure 10 shows the signal timing for a read cycle to transfer mation from the processor to the Dual UART. Table 11 lists
information from the Dual UART to the processor. Figure 11 the timing parameters for the read and write cycles.
116

.~

1\

DS

, _ tOPWLR - - +

ADO<3:C

~I

tOPWH

IX

VALID ADDRESS

X

~h

tASU

I--J-

JL

twsu

~tWHO

tcsu

f---I-o f- tCHO

WR

~

.;

"\J

DL...-:: 7:0 >

I

r-..

--------I-

tAHO

__

!- tRDL

tRDH~
~

".-..

~ VALID

DATA O U T M

tOOl l . tOOZH

I-- tDD-ooI

~~DF.....I
I

tDDLZ, tDDHZ

IRO

f+- tlD::::J

FIGURE 10-COM78C802 BUS READ CYCLE TIMING

OS
_tDPWLW___

XI

...--.+-

tASU

\

X

~

VALID ADDRESS

1.---

1\

lOPWH

tAHO

/
-twsu

~

tcsu

-

tWHO

--4 r-

\

tCHO

~tRD~

...... tRDL\.-

OL<7:0>

VALID DATA IN

~tDSU--.ll--tDHO_1
iRa

~tlD:I
FIGURE 11-COM78C802 BUS WRITE CYCLE TIMING
117

TABLE 10-COM78C802 BUS READ AND WRITE TIMING PARAMETERS
Symbol

Definition

tAHO

Hold time of a valid AOO <3:0> to a valid high level of
OS.

tABu

Setup time of a valid AOO <3:0> to the falling edge of
OS.
Hold time of a valid low level of CS to a valid high level of
OS.

leHO
leou

Setup time of a valid low level of CS to the falling edge of
OS.

tDD

Prop~tion delay of a valid.low level on OS (if CS is low

tDOLZ2

Prop~tion delay of a valid high level on OS (if CS is low

and WR is high) to valid high or low data on OL <0>.

Requirements (ns)
Min.
Max.

Load
Circuit'

10
30
10
30
165

CL=150 pF

and WR is high) to OL <0> output drivers disabled.
tODL2
tOOHZ

tooLZ
tOOHZ

tooLZ
tOOHZ

tOOZL

50
50
60
60
65
65

CL=50pF
CL=50pF
CL= 100pF
CL= 100pF
CL= 150pF
CL= 150pF

165
165

CL= 150pF
CL=150pF

Prop~tion

delay of a valid low level on OS (if CS is low
and WR is high) to OL <7:0> output driver enabled.
tooZL
tOOZH

0

tDF

Hold time provided during a read cycle by Oual UART of
valid high or low data on OL <7:0> after the rising edge
ofOS.

0

tDHO

Hold time of a valid OL <7:0> to a valid high level of OS.

30

tDPWH

Pulse width high of OS.

tDPWLR

Pulse width low of OS when WR is high (read operation).
Refer to timing parameter tDPWLW also.
Pulse width low of OS when WR is low (write operation).
Refer to timing parameter tDPWLR also.

180

10,000

130

10,000

tasu

Setup time of a valid OL <;7:0> to the rising edge of OS.

50

t103

Propagation delay..QLa valid low level on OS (if CS is low)
to a high level on IRQ.

635

C L=50pF

Propagation ~ of a valid high level of CS to a valid
high level on ROY.

210

CL=50pF

tRilL

Propagation delay of a valid low level on CS to a valid
low level on ROY.

90

CL=50pF

tWHO

Hold time of a valid high or low level of WR to a valid high
level of OS.

10

twsu

Setup time of a valid high or low level of WR to the falling
edge of OS.

30

tOPWLW

tRDH4

450

'Refer to Figure 9 for the load circuits used with these measurements.
"The tDDl2 and tDoHZ parameters are measured with CL = 150 pF. The values of tODl2 and tOIlHZ for CL = 50pF and CL = 100 pF have been derived for user
convenience.
'Total rise time depends on internal delay plus the pullup delay introduced by the external resistor being used. The t,o parameter can be calculated
by the following: tID =500 + RCL where R =value of the resistor that connects to capacitor CL in load A, Figure 9.
'Total rise time depends on internal delay plus the pullup delay introduced by the external resistor being used. The tROH parameter can be calculated
by the following: tROH = 75 + RCL where R = value of the resistor that connects to capacitor CL in load A, Figure 9.

Figure 12 shows the signal timing for the clock input, intertiming, and the transmit data outputtiming. Table 11 lists the
rupt timing, effect of the RESET input on data strobe, data
timing parameters for Figure 12.
set carner detect (OCO) and data set ready (OSR) input
118

elK

CLOCK

D(

>L

IROLN/IRQTxAx

i-,J

L,,"~

IRQ

INTERRUPT

RESET

1

tRES

DS

1·

tORSU

~.

.~

tDRHO

EFFECT OF RESET ON DATA STROBE

DCD/DSR<1:0>

XJ

VALID DCD/DSR DATA

IX

"-----''1-1j..-=--=--=--=--=--=-~~';;"tD;;';S;;';PW;":-"';'-':'-";'----'--------1.11...----------oeD/DSA INPUT

TxO <1:0

>

\C::=tTXSK==:LtTXSK~~------';-TRANSMIT DATA OUTPUT

FIGURE 12-COM78C802 MISCELLANEOUS SIGNAL TIMING
TABLE 11-MISCELLANEOUS WRITE TIMING PARAMETERS
Symbol

Definition

Ie,
Ie'WH
IePWL

Period of ClK.

IoRHO

Requirements (ns)
Min.
203.45 (4.9152 MHz)

Pulse width high of ClK.

Load Circuit'

95

Pulse width low of ClK.

95

Hold time of a valid high level of DS to a valid high level
of RESET.

t ORSU

Setup time of a valid high level of DS to the rising edge of
RESET.

1,000
900

tospw

Pulse width high or low of DCD < 1 :0> and DSR < 1 :0>.

t lHO

Hold time provided by Dual UART from a valid IRQlN
and IRQTxRx to a valid high level of IRQ.

1,000
100

CL=50pF

t lSU

Setup time provided by Dual UART from a valid IRQlN
and IRQTxRx to a valid low level of IRQ.

100

CL=50pF

t RES
tTXSK

Pulse width low of RESET.

1,000

Pulse width high or low provided by Dual UART on the
TxD <1 :0> lines. At each baud rate, the actual pulse
widths provided vary by tTXSK ' This timing parameter
should be used to determine cumulative reception/transmission errors.

'Refer to Figure 9 for the load circuits used with these measurements.

119

250

CL=50pF

Figure 13 shows the input and output voltage waveforms
for the propagation delay and setup and hold measure-

ments. Figure 14 shows the waveforms for the three-state
outputs measurement.

VIH(~'~~'=::::'::I
INPUT

0.8 V
VIL (0.4 V)

::.7-1---------rtL·H

j

\

-"'-1

\;'

PH't
L

~'~~'::::ul~
,.~~,'::'''m.
I-~~\l

-'I

SET·UP AND HOLD

Vo (0.8 V) ---~.

PROPAGATION DelAY

FIGURE 13-COM78C802 PROPAGATION DELAY
AND SETUP AND HOLD VOLTAGE WAVEFORMS

r

VIN (2.4 V)
2.0V
OUTPUT CONTROL

VIL

a.sv

(~Z: :OT~ ~:

VOH (45V)
OUTPUT (SEE NOTE 1) 1 5V

VOl+05
VOUT (AS MEASURED)

--

lt

-

-j- ----- -

----

tlZ

-

-

(NOTE 3C)

--- VOL+O.5V

- - - - - - -

tlH (NOTE 38)

VOUT (AS MEASURED)
VOH -0.5 V
1.SV
OUTPUT VOL (NOTE 2)
(O.OV)

THREE-STATE OUTPUTS
NOTES:
1. INTERNAL CONDITIONS ARE SUCH THAT THE OUTPUT IS LOW EXCEPT WHEN DISABLED BY

THE OUTPUT CONTROl.
2.

INTERNAL CONDITIONS ARE SUCH THAT THE OUTPUT IS HIGH EXCEPT WHEN DISABLED BY
THE OUTPUT CONTROL.

3.

REFER TO FIGURE 9. A :: 51 CLOSED, B = 52 CLOSED. C = S 1 AND 52 CLOSED.

FIGURE 14-COM78C802 THREE-STATE OUTPUT VOLTAGE WAVEFORMS
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications: consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the right to
make changes at any time in order to improve design and supply the best product possible.

120

STANDARD MICROSYSTEMS
CORPORATION

COM78C804
PRELIMINARY

Four-channel Universal
Asynchronous Receiver/Transmitter
QuadUART
PIN CONFIGURATION

FEATURES

D Four independent full duplex serial data lines
DCD 2
DSR2

D Programmable baud rates individually selectable for

TXD 2

each line's transmitter/receiver (50 to 19,200 baud)

VDD
DL,
DLo
DL,

D Summary registers that allow a single read to detect a
data set change or to determine the cause of an interrupt on any line

48 AXD2
47 RXD 3

3
4
5
6

0 ....
ROY

9

RST 10
11
12
WR 13
os· 14
DL3 15
el2 16
Dl, 17
DL~ 18
VDD 19
TXD~ 20
DSR~ 21
DCD~ 22
RXD~ 23
RXD, 24
VSS~

os

D Triple buffers for each receiver
D Device scanner mechanism that reports interrupt
request due transmitter/receiver interrupts

D Independently programmable lines for interrupt-driven
operation

D Modem status change detection for Data Set Ready
(DSR) and Data Carrier Detect (DCD) signals

46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

DCD3
DSR3
TXD3
VSS,
elK
MRST
ADD.

ADD3
OS·

ADD2
ADD,
ADD~

IRQ
IRQTXRX
IRQLN,
IRQLN~

VDD
NIC

vss,
TXD,
DSR,
DCD,

PACKAGE: 48-pin DIP

><
"must be connected together
a: _ "

D Programmable interrupts for modem status changes

~'M~_" ~33
"'a: C cc CCIO 0 0 0
d::;~~~~~g;g;g;g;

D Synchronizes critical read-only registers
D Single 5V Power Supply

vss,
TXD,
DSR,
DCD,
RXD,
RXD,

D TTL Compatible
D Low Power CMOS Technology

DCD,
DSR,
TXD,

D Compatible with SMC's COM78C808
and COM78C802

DL,
DL,

40

3938373635343332313029
28
27
26
25

. 1
2

3
4
5
6

VDD
VSS,

TXD,
DSR,
DCD,
RXD,
RXD.
DCD.
DSR.

TXD.
7 8 9 10 11 121314151617

18

D4

.:r
JI~ I~ etl'1"'1a: I'"
.2..J J
C ccc
CCa:a:g1U3:
PACKAGE: 44- pin PLCC

GENERAL DESCRIPTION

The COM78C804 Four-channel Asynchronous Receiver/
Transmitter (Quad UART) is a VLSI device for new generations of asynchronous serial communication designs and
for microcomputer systems. This device performs the basic

operations necessary for simultaneous reception and
transmission of asynchronous messages on four independent lines. Figure 1 is a functional block diagram of the
COM78C804 Quad UART.

121

TxDO
RxDO
DSRO
DCDO
INTE RRUPT
SUMMARY
REGISTER

TxDI
RxDI
DSRI
DCDI
TxD2
RxD2
DSR2
DCD2
TxD3
RxD3
DSR3
DCD3

DATA SET
CHANGE
SUMMARY
REGISTER

DATA BUS

CLK

CONTROL BUS

MRESET

FIGURE 1: COM78C804 QUAD UART FUNCTIONAL BLOCK DIAGRAM
TABLE 1-COM78C804 PIN AND SIGNAL SUMMARY
Pin-PLCC

Signal

Input/Output

Definition/Function

5-8,15-18

Pin-DIP
5-8,15-18

Dl<7:0>

input/output

Data lines <7:0>-Receives and transmits the parallel
data.

33-37

35-37,39,40

ADD<0:4>

input

Address<0:4>-Selects the internal registers in the Quad
UART.

12

12

CS

input

Chip select-Activates the Quad UART to receive and transmit data over the Dl<7:0> lines.

14

14,38

DS

input

Data strObe-Receives timing information for data transfers.

13

13

WR

input

Write-Specifies direction of data transfer on the DL <7:0>
lines.

9

9

RDY

output

Ready-Indicates when the Quad UART is ready to participate in data transfer cycles.

10

10

RESET

input

Reset-Initializes the internal logic.

38

41

MRESET

input

Manufacturing reset-For manufacturing use.

39

42

ClK

input

Clock-Clock input for timing.

3,20,25,42

2,21,26,45

DSR<3:0>

inputs

Data set ready-Monitor data set ready (DSR) signals from
modems.

2,21,24,43

1,22,25,46

DCD<3:0>

inputs

Data set carrier detect-Monitor data set carrier detect
(DCD) signals from modems.

32

34

IRQ

output

Interrupt request-Requests a processor interrupt.

29,30

31,32

lRQlN<0:1>

output

Interrupt request line number-Indicates the line number of
originating interrupt request.

31

33

IRQTxRx

output

Interrupt request transmit/receive-Indicates whether an
interrupt request is for transmitting or receiving data.

4,19,26,41

3,20,27,44

TxD<3:0>

outputs

Transmit data-Provides asynchronous bit-serial data output streams.

1,22,23,44

23,24,47,48

RxD<3:0>

input

Receive data-Accepts asynchronous bit-serial data input
streams.

28

4,19,30

Voo

input

Voltage-Power supply voltage

11,27,40

11,28,43

V••

input

Ground-Ground reference

122

+ 5 Vdc.

DATA AND ADDRESS
Data lines (DL<7:0»-These lines are used for the paraile I transmission and reception of data between the CPU
and the Quad UART. The receivers are active when the data
strobe (OS) signal is asserted. The output drivers are active
only when the chip select (CS) signal is asserted, the data
strobe (OS) signal is asserted, and the write (WR) signal is
deasserted. The drivers will become inactive (high-impedailce) within 50 nanoseconds when one or more of the following occurs: the chip select (CS) Signal is deasserted,
the data strobe (OS) signal is deasserted, or the write (WR)
signal is asserted.

Address (ADD<4:0»-These lines select which Quad
UART internal register is accessible through the data I/O
lines (OL <7:0» when the data strobe (OS) and chip select
(CS) signals are asserted. Table 2 lists the addresses corresponding to each register. The receiver buffer and transmitter holdi!!fl!egister for each line have the same address.
When the (WR) signal is deasserted, the address accesses
the receiver buffer register and when asserted, it accesses
the transmitter holding register.

TABLE 2-COM78C804 REGISTERS ADDRESS SELECTION
ADD Line*
<4>

<3>

<2>

<1>

<0>

ReadlWrite

Register

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
ReadlWrite
Read/Write

Line 0 Receiver Buffer
Line 0 Transmitter Holding
Line 0 Status
Line 0 Mode Registers 1,2
Line 0 Command

0
0
0
0
0

1
1
1
1
1

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
Read/Write
ReadlWrite

Line 1 Receiver Buffer
Line 1 Transmitter Holding
Line 1 Status
Line 1 Mode Register 1,2
Line 1 Command

1
1
1
1
1

0
0
0
0
0

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
Read/Write
Read/Write

Line 2 Receiver Buffer
Line 2 Transmitter Holding
Line 2 Status
Line 2 Mode Register 1 ,2
Line 2 Command

1
1
1
1
1

1
1
1
1
1

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
ReadlWrite
ReadlWrite

Line 3 Receiver Buffer
Line 3 Transmitter Holding
Line 3 Status
Line 3 Mode Register 1 ,2
Line 3 Command

X
X

X
X

1
1

0
0

0
1

Read
Read

Interrupt Summary
Data Set Change Summary

'X= Either 0 or 1.

BUS TRANSACTION CONTROL

INTERRUPT REQUEST

Chip select (CS)-This Signal is asserted to permit data Interrupt request IRQ-The IRQ pin is an open drain outtransfers through the OL <7:0> lines to or from the internal put. The integral interrupt scanner asserts the IRQ signal
registers. Oata transfer is controlled by the data strobe (OS) when it has detected an interrupt condition on one of the
signal and write (WR) signal.
four serial data lines.
Data strobe (DS)- This input receives timing information
for data transfers. During a write cycle, the CPU asserts the
data strobe signal when valid Qutput data is available and
deasserts the data strobe signal before the data is removed.
Ouring a read cycle, the CPU asserts the data strobe signal
and the Quad UART transfers the valid data. When the data
strobe signal is deasserted, the DL<7:0> lines become a
high impedance.

o

Write (WR)-The write (WR) signal specifies the direction
of data transfer on the DL<7:0> pinsJ!..the WB...signal is
asserted during a data transfer (the CS and DS signals
assert~ the Quad UART is receiving data from DL<7:0>.
If the WR signal is deasserted during a write data transfer,
the Quad UART is driving data onto the DL <7:0> lines.

Interrupt request line number (IRQLN<1 :0»-These
lines indicate the line number at which the Quad UART
interrupt scanner stopped and asserted the interrupt request
(IR~nal. The number on these lines is valid only while
the IRQ signal is asserted. Line IRQLN<1 > is the highorder bit and the IRQLN line is the low-order bit. The

123

Interrupt Request transmit/receive (IRQTxRx)-This
Signal indicates when the interrupt scanner in the Quad
UART stops and asserts IRQ because of a transmitter
interrupt condition (the IRQTxRx signal is asserted) or
because of a receiver interrupt condition (the IRQTxRx signal is deasserted). The signal is valid only while IRQ is
asserted. The state of IRQTxRx signal also appears as bit
of the interrupt summary register.

I

state of these signals also appears as bits in the interrupt
summary register: IRQLN<1 > as bit 2, and IRQLN as
bit 1. Table 3 shows the line numbers corresponding to settings of IRQLN<1 :0>.

TABLE 3-COM78C804 INTERRUPT REQUEST
LINE ASSIGNMENTS
Line
IRQ Line
<1>
<0>
0
0
0
1
1
0
0
2
1
1
1
3
SERIAL DATA
Transmit data (TxD<3:0»-These outputs transmit the
asynchronous bit-serial data streams. They remain at a high
level when no data is being transmitted and a low level when
the TxBRK bit in the associated line's command register is
set.
Receive data (RxD<3:0»-These lines accept asynchronous bit-serial data streams. The input signals must
remain in the high state for at least one-half bit time before
a high-to-Iow transition is recognized. ( A high-to-Iow transition is required to si9nal the beginning of a "start" bit and
initiate data reception).

MISCELLANEOUS SIGNALS
Clock in (CLK)-AII baud rates and internal clocks are
derived from this input. Normal operating frequency is 4.9152
MHz ± 0.1 percent and duty cycle is 50 percent ± 5 percent.

POWER AND GROUND·
Voltage (Voo)-Power supply 5 Vdc
Ground (Vss)-Ground reference

ARCHITECTURE SUMMARY
The Quad UART functions as a serial-to-parallel, parallelto-serial converter/controller. It can be programmed by a
microprocessor to provide different characteristics for each
of its four serial data lines (stop bits, parity, character length,
split baud rates, etc.)
Each serial line functions the same as a one-line UARTtype device thereby reducing the number of chips and conserving space on communication devices that require mUltiple communications lines.
An integral interrupt scanner checks for device interrupt
conditions on the four lines. Its scanning algorithm gives
priority to receivers over transmitters. The scanner can also
check for interrupts resulting from changes in modem control signals DSR and DCD.
Line-specific Registers
Each of the four serial data lines in the Quad UART has a
set of registers for buffering data into and out of the line and
for external control of the line's characteristics. These registers are selected for access by setting the appropriate
address on lines ADD<4:0>. Lines ADD<4:3> select one
of the four data lines. Lines ADD<2:0> select the specific
register for that line. Refer to Table 2 for the register address
assignments.

MODEM SIGNALS
Data set ready (DSR<3:0»-These four input pins, one
for each serial data line on the COM78C804, are typically
connected via intervening level converters to the data set
ready outputs of modems. A TTL low at a DSR pin causes
the DSR bit (bit 7) in the corresponding line's status register to be asserted. A TTL high at a DSR pin causes the Receiver buffer register-Each line's receiver consists of
DSR bit in the corresponding line's status register to be a character assembly register and a two-entry FIFO that is
deasserted. A change of this input from high-to-Iow, or low- the receiver buffer register. When the RxEN bit in a line's
to-high, causes the assertion of the data set change command register is set, received characters are moved
(DSCHNG) bit that corresponds to this line in the data set automatically into the line's receiver buffer as soon as they
change summa,ry register. Changes from one state to the have been deserialized from the associated communicaother and back again that occur within one microsecond tions line. When there are characters in this FIFO, the
may not be detected.
RxRDY bit is set in the status register for the line.
Carrier detect (DCD<3:0»-These four input pins, one The assertion of the RxRDY signal for a line that already.
for each serial data line of the Quad UART, are typically has the RxlE bit of its command register set causes the
connected through intervening level converters to the interrupt scanner logic to stop and generate an interrupt
received line signal detect (also called carrier detect) out- condition (the IRQ Signal is asserted). When the receiver
puts of modems. A TTL low at a DCD pin causes the DCD buffer is read, the interrupt condition is cleared (the IRQ sigbit of the corresponding line's status register to be deas- nal is deasserted) and the interrupt scanner resumes
serted. A change of this input from high-to-Iow, or low-to- operation.
high, causes the assertion of the data set change If there is another entry in a line's FIFO, the RxRDY bit
(DSCHNG) bit corresponding to this line in the data set
remains asserted. When the interrupt scanner reaches this
change summary register. Changes from one state to the
other and back again that occur within one microsecond may line again, the assertion of RxRDY causes the scanner to
halt and assert the IRQ again.
.
not be detected.
Asserting the RESET signal or clearing the RxEN bit iniGENERAL CONTROL SIGNALS
tializes the receiver logic of Quad UART. The RxRDY flag
Ready (RDY)-The RDY pin is an open drain output. Upon is cleared and the receiver buffer register outputs become
detecting a negative transition of chip select (CS), the Quad undefined. Any data in the FIFO at that time is lost.
UART asserts the RDY signal to indicate readiness to take
part in data transfergcles. The RDY Signal deasserts after Transmitter holding register-Each line has a writable
transmitter holding register. When the TxEN bit in the line's
the trailing edge of CS.
command register is set, characters are moved automatiReset (RESEn-When the RESET input in asserted, the cally from the output of this register into the transmitter seriTxD<3:0> lines are asserted and all internal status bits alization logic whenever the serialization logic becomes idle.
listed in the "Architecture Summary" discussion are cleared.
When this register is empty, the TxRDY bit in the line's staManufacturing reset (MRESET)-This signal is for man- tus register is set. If the transmitter interrupt .enable (TxIE)
ufacturing use only and the input should be connected to bit in the line's command register is also set, the interrupt
ground for normal operation.
scanner logic halts and generates an interrupt condition. If
124

a character is then loaded into the register, the interrupt is
cleared and the scanner resumes operation.
Assertion of the RESET signal initializes the transmitter logic
of the Quad UART. The TxRDY flag is cleared and the
transmitter holding register's contents are lost. The transmitter enable (TxEN) bit in the line's command register is
also cleared by RESET. If at the end of the reset process,
the TxEN is reasserted and TxRDY bit is reasserted. Software clearing ofTxEN alone produces results differentfrom
the full RESET in that the transmitter holding register's contents are not lost; they are transmitted when TxEN is set
again.
Status register-Each line has a read-only status register
that provides information about the current state of the given
line. This register indicates a line's readiness for transmission or reception of data and flags error conditions in its bit
fields. Figure 3 shows the format of the status register. Table
3 lists the flag bits in each status register.

OSR
OCD-----'

FER - - - - - - - '
ORR--------~

PER---------~

TxEMT - - - - - - - - - - - - '
RxROY--------------'
TxROY----------------'

FIGURE 3: COM78C804 STATUS REGISTERS
(LINE 0-3) FORMAT

TABLE 4-COM78C804 STATUS REGISTERS (LINES 0-3) DESCRIPTION
Bit

7
6
5

Description
DSR (Data set ready)-This bit is the inverted state of the DSR line.
DCD (Data set carrier detect)-This bit is the inverted state of the DCD line.
FER (Frame error)-Set when the received character currently displayed in the receiver buffer register was not
framed by a stop bit. Only the first stop bit is checked to determine that a framing error exists. Subsequent
reading of the receiver buffer register that indicates all zeros (including the parity bit, if any) can be interpreted
as a Break condition. This bit is cleared by clearing RxEN (bit 2) of the command register, by asserting the
RESET input, or by setting the reset error RERR (bit 4) of the command register.

4

ORR (Overrun error)-Set when the character in the receiver buffer register was not read before another character was received. Cleared by clearing RxEN (bit 2) of the command register, by asserting the RESET input,
or by setting reset error RERR (bit 4) of the command register.

3

PER (Parity error)-If parity is enabled and this bit is set, the received character in the receiver buffer register
has an incorrect parity bit. This bit is cleared by clearing RxEN (bit 2) of the command register, by asserting the
RESET input, by setting reset error RERR (bit 2) of the command register, or by reading the current character
in the receiver buffer register.

2

TxEMT (Transmitter empty)-Set when the transmitter serialization logic for the associated line has completed
transmission of a character, and no new character has been loaded into the transmitter holding register.
Cleared by loading the transmitter holding register, by clearing TxEN (0) of the command register, or by asserting the RESET input.

1

RxRDY (Receiver buffer ready)-When set, a character has been loaded into the FIFO buffer from the deserialization logic. Cleared by reading the receiver buffer register, by clearing RxEN (bit 2) in the command register,
or by asserting the RESET input.

0

TxRDY (Transmitter holding register ready)-When set, this bit indicates that the transmitter holding register is
empty. Cleared when the program has loaded a character into the transmitter holding register, when the transmitter for this line is disabled by clearing TxEN (bit 0) in the command register, or by asserting the RESET
input. This bit is initially set when the transmitter logic is enabled by the setting of TxEN (bit 0) and the transmitter holding register is empty. This bit is not set when the automatic echo or remote loopback modes are programmed. Data can be overwritten if a consecutive write is performed while TxRDY is cleared.

Mode registers 1 and 2-These read/write registers control the attributes (including parity, character length, and line
speed) of the communications line.
Each of the four communications lines has two ofthese registers, both accessed by the same address on ADD<4:0>.
Successive access operations (either read or write, in any
combination) alternate between the two registers at that
address by use of an internal pointer. The first operation
addresses mode register 1 , the next address mode register
2, and another after that would recycle the pointer to mode
register 1. The pointer is reset to point to mode register 1 by
RESET or by a read of the command register for this line.
These registers should not be accessed by bit-oriented
instructions that do read/modify/write cycles such as the
PDP-11 BIS, BIC, and BIT instructions.
Figure 4 shows the format of mode registers 1 and Table 5
describes the function of the register information.
125

STOP----'
PAR C T R L - - - - - - - '

CHAR LENGTH ---~-----'
RSRV--------------'
MCIE - - - - - - - - - - - - - - - - '

FIGURE 4-COM78C804 MODE
REGISTERS 1 (LINE 0-3) FORMAT

TABLE 5-COM78C804 MODE REGISTERS 1 (LINES 0-3) DESCRIPTION
Bit
7,6

Description
STOP-These bits determine the number of stop' bits that are appended to the transmitted characters as
follows. These bits are cleared by asserting the RESET input.

Bits

5,4

Stop Bits

7
0
0

6
0

Invalid

1

1.0

1
1

0

1.5

1

2.0

PAR CTRL (Parity control)-These bits determine parity as follows and are cleared by asserting the RESET
input. X = either 1 or O.

Bits

3,2

Parity Type

5

4

1

0

1
1

X

0

Even
Odd
Disabled

CHAR LENGTH (Character length)-These bits determine the length (excluding start bit, parity, and stop
bits) of the characters received and sent. Received characters of less than 8 bits are "right aligned" in the
receiver buffer with unused high-order bits equal to zero. Parity bits are not shown in the receiver buffer. The
character length bits are cleared by asserting the RESET input. The character length bits are defined as
follows:

Bit Length

Bit
3

2
0

0
0

5

1

1
1

0

6
7

1

8

1

RSRV (Reserved and cleared by asserting the RESET input.)

0

MCIE (Modem control interrupt enable)-When set and RxlE (bit 5) of the command register is set, the
modem control interrupts are enabled. Refer to the Interrupt Scanner and Interrupt Handling information.
Cleared by asserting the RESET input.

Figure 5 shows the format of mode registers 2 and Table
5 indicates the baud rate selections of the register. Bits 7
through 4 of the mode register 2 control the transmitter
baud rate and bits 3 through 0 control the receiver baud
rate. These registers are cleared by asserting RESET input.

Command register- These read/write registers control
various functions on the selected line. Figure 6 shows the
format of the command registers and Table 6 describes
the function of the register information.

l I I I I I I I I
~

OPER

i

"

Rxl E

MOOE~

I

RERR
TxBR K

XMIT RATE _ _ _..J.

RxEN

RECV RATE - - - - - - - - - - - - - '

Txl E
TxEN

FIGURE 5-COM78C804 MODE
REGISTERS 2 (LINE 0-3) FORMAT

FIGURE 6-COM78C804 COMMAND
REGISTERS (LINE 0-3) FORMAT

126

TABLE 6-COM78C804 MODE REGISTERS 2 (LINES 0-3) DESCRIPTION
Bit

Description

7:0

XMIT RATE/RECV RATE (Transmitter/Receiver Rate)-Selects the baud rate of the transmitter (bits 7:4) and
receiver (bits 3:0) as follows:
ErrorTransmitter Bits
Receiver Bits
Nominal
Actual
4
1
Rate
Rate
(percent)
7
6
5
3
2
0
same
0
0
0
0
0
0
0
0
50
1
0
1
75
same
0
0
0
0
0
1
0.826
110
109.09
0
0
1
0
0
0
0
1
1
1
1
134.5
133.33
0.867
0
0
0
0
same
0
1
0
0
0
1
0
0
150
1
1
1
300
same
0
1
0
0
0
1
1
1
1
0
600
same
0
0
0
1
1
1
1
1
1200
same
0
1
0
1745.45
3.03
1
1
0
1800
0
0
0
0
0
2021.05
1.05
1
0
0
1
1
1
2000
0
0
2400
1
1
same
0
0
1
0
0
1
1
1
1
1
1
1
3600
3490.91
3.03
0
0
same
4800
0
0
1
1
0
0
1
1
1
1
1
1
1
1
7200
6981.81
3.03
0
0
same
1
1
1
1
0
1
1
0
9600
1
1
1
1
1
1
1
1
19200
same

-

·The frequency of the clock input (ClK) is 4.9152 MHz. The clock input may vary by 0.1 percent. This variance results in an error
that must be added to the error listed.

TABLE 7-COM78C804 COMMAND REGISTERS (LINES 0-3) DESCRIPTION
Bit

Description

7,6

OPER MODE (Operating mode)-These bits control the operating mode of the channel as follows. These
bits are cleared by asserting the RESET input.
Bit
Operating Mode

7

6

0
0
1
1

0
1
0
1

Normal operation
Automatic echo
local loopback
Remote loopback

5

RxlE (Receiver interrupt enable)-When set, the RxRDY flag (bit 1) of the status register for this line will
generate an interrupt.

4

RERR (Reset error)-When set, this bit clears the framing error, overrun error, and parity error of the status
register associated with this line. This bit is cleared by asserting the RESET input (not self-clearing).

3

TxBRK (Transmit break)-When set, this bit forces the appropriate TxD<3:0> line to the spacing state at the
conclusion of the character presently being transmitted. When the program clears this bit, normal operation
is restored, and any character pending in the transmitter holding register is moved into the serialization logic
and transmitted. The minimum break length obtainable is twice the character length plus 1 bit time. The
maximum break length depends on the amount of time between the program setting and clearing this bit,
but is an integral number of bit times. This bit is cleared by asserting the RESET input.

2

RxEN (Receiver enable)-When set, this bit enables the receiver logic. When cleared, it stops the assembling of the received character, clears all receiver error bits and the RxRDY (bit 1) of the status register,
clears any receiver interrupt conditions associated with this line, and initializes all receiver logic. This bit is
cleared by asserting the RESET input.

1

TxlE (Transmit interrupt enable)-When set, the state of the associated TxRDY flag (bit 0) of the status register is made available to the interrupt scanner logic. When the interrupt scanner logic scans this line, it
determines if the TxRDY flag is asserted and generates an interrupt by asserting the IRQ signal.

0

TxEN (Transmitter enable)-When set, this bit enables the transmitter logic. When cleared, it inhibits the
serialization of the characters that follow but the serialization of the current character is completed. It also
clears the TxRDY flag (bit 0) of the status register, clears any transmitter interrupt conditions associated with
this line, and initializes all transmitter logic except that associated with the transmitter holding register. The
character in the transmitter holding register is retained so that XON/XOFF situations can be properly processed. This bit is cleared by asserting the RESET input.

Bits 5 through 0 enable the line's receiver and transmitter,
enable handling of interrupts, initiate the transmission of
break characters, and reset error bits for the line. Refer to
"Interrupt Scanner" and "Interrupt Handling" paragraphs
for detailed interrupt information. Bits 7 and 6 control the
operating mode of the line. The four modes that can be
set are:

127

o Normal operation-The serial data received is assembled in the receiver logic and transferred in parallel to the
receiver buffer register. (The RxEN bit must be set.) Data
to be transmitted is loaded in parallel into the transmitter
holding register, then automatically transferred into the
transmitter logic and serialized for transmission. (The
TxEN bit must be set.)

o Automatic echo-The serial data received is assembled

into parallel in the receiver logic (the RxEN bit must be
set) and transferred to the receiver buffer register. Arriving serial data is also routed to the line's TxD pin for
serial output. TxEN is ignored and the transmitter logic
is disabled. TxRDY flags and TxEMT indications are
cleared. No transmitter interrupts are generated.

o Localloopback-The serial data from the RxD input
is ignored and the receiver serial input receives data from
the transmitter serial output. The data is assembled into
parallel form in the receiver logic (the RxEN bit must be
set) and transferred to the receiver buffer register where
it can be read by the program. Data to be transmitted to
the receiver is loaded in parallel form into the transmitter
holding register from which it is automatically moved into
the transmitter logic and serialized for transmission. (The
TxEN bit must be set.) The transmission goes only to the
receiver serial input; the TxD output is held high. As
in normal operation, transmission and reception baud
rates are controlled by the transmitter speed and receiver
speed entries in mode register 2.

o

Remote loopback-The serial data received on the
RxD line is returned to the TxD line without
further action. No data is received or transmitted. The
RxRDY, TxRDY, and TxEMT flags are disabled. The
TxEN and RxEN bits of the command register are held
cleared, causing the transmitter and receiver logic to be
disabled.

SUMMARY REGISTERS

The Quad UART contains two registers that summarize the
current status of all four serial data lines, making it possible
to determine that a line's status has changed with a single
read operation. These registers are selected for access by
setting the appropriate address on pins ADD <2:0>.
Because the registers are shared by four serial lines, the
line-selection bits (ADD <4:3» are ignored when these
registers are accessed. Refer to "Interrupt Scanner and
Interrupt Handling" for detailed interrupt information.
Interrupt summary register-This read-only register indicates that a transmitter or receiver interrupt condition has
occurred, and indicates the line number that generated the
interrupt. Figure 7 shows the format of the interrupt summary register and Table 8 describes register information.

FIGURE 7- COM78C804
INTERRUPT SUMMARY REGISTER FORMAT

TABLE 8-COM78C804 INTERRUPT SUMMARY REGISTER DESCRIPTION
Description
IRQ (Interrupt request)-When set, this bit indicates that the interrupt scanner has found an interrupting con-'
7
dition among the four serial lines of the Quad UART. These conditions also result in the Quad UART asserting the IRQ signal.
6:4
RAZ (Read as zero)-Not used
INT LINE NO (Interrupting line number)-These bits indicate the line number upon which an interrupting con3:1'
dition was found. These bits correspond to the IRQLN <1 :0> signals-bit 2 = IRQLN<1 >, and bit 1= IRQLN.
Refer to Table 3.
TxlRx (Transmitlreceive)-This bit indicates whether the interrupting condition was caused by a transmitter (TxI
0'
Rx equals 1) or a receiver (TxlRx equals 0). This bit corresponds to the IRQTxRx signal of the Quad UART
and is set when IRQTxRx is asserted.
'Bits 3-0 above represent the outputs of a free-running counter and are valid only when bit 7 is set.
Bit

then be obtained from that line's status register. If the state
of a line changes twice within one microsecond, the change
in state may not be detected. Figure 8 shows the format
of the data set change summary register.
When the MCIE bit in a line's mode register 1 is set and
LiNumber
ne ------3·-----,2 -----------------------------------1 -----·0---RxlE is also set, the modem control interrupts are enabled
t
f
for that line. If DSCHNG for that line is then set, the interrupt
o
7
6
scanner will halt and assert the IRQ signal. The data set
change summary register bits are cleared by writing a 1 into
the'bit position. A program that uses this register should read
'--y---I
and save a copy of its contents. The copy can then be writI
ten back to the register to clear the bits that were set. The
DSCHNG3-0 - - - - - - - - - '
system interrupts should be disabled and write back should
directly follow the read operation.
Assertion of the RESET signal disables and initializes the
FIGURE 8-COM78C804 DATA SET CHANGE
data set change logic. When the RESET signal is deasserted, future changes in DSR and DCD are reported as
SUMMARY REGISTER FORMAT
they occur_
128

Data set change summary register-When the DSR or
OeD inputs that are associated with a line change state,
the bit corresponding to that line in this read-only register
is set. The current state of the DSR and DCD inputs can

,

INTERRUPT SCANNER AND INTERRUPT HANDLING
The interrupt scanner sequentially checks each line for a
receive interrupt and then checks each one in the same
order for a transmitter interrupt. If the scanner detects an
interrupt condition, it stops and the IRQ signal is asserted.
An interrupt must be serviced by software or no other interrupt request can be posted.
The scanner determines that a line has a receiver interrupt
if the line's receiver buffer is ready and receiver interrupts
are enabled for that line (RxRDY and RxlE = 1) or either of
the line's modem status signals has changed state and both
receiver and modem control interrupts are enabled for that
line (DSCHNG and RxlE and MCIE = 1).
The scanner determines that a line has a transmitter interrupt if the line's transmitter holding the register is empty and
transmitter interrupts are enabled for that line (TxRDY and
TxlE = 1).
When the scanner detects an interrupt, it reports the line
number on the IRQ<1 :0> lines. The IRQTxRx signal is
asserted for a transmitter interrupt and deasserted for a
receiver interrupt. The appropriate bits are also updated in
the interrupt summary register. The IRQ line is deasserted
and the scanner is restarted for each of the following three
types of interrupt conditions.

o Reading the receiver buffer or resetting the RxlE bit of

the interrupting line for the first type of receiver interrupt
previously described.

o Resetting the MCIE, RxIE, or DSCHNG bit of the interrupting line for the second type of receiver interrupt previously described.

o Loading the transmitter holding register or resetting the
TxlE bit of the interrupting line for transmitter interrupts.

If the scanner was originally stopped by a receiver interrupt
condition, the scanner resumes sequential operation from
where it stopped, thus providing receivers with equal prior-

ity. If the scanner was stopped by a transmitter condition,
the scanner restarts from position 0 (line D's receiver), thus
giving receivers priority over transmitters.
EDGE-TRIGGERED AND LEVEL-TRIGGERED INTERRUPT SVTSTEMS
If the interrupt system of the Quad UART is used only for
generating interrupts for the RxRDY and/or TxRDY flags,
the IRQ line can be connected to a processor having either
edge-triggered or level-triggered interrupt capability. If the
modem control interrupts are being used (MCIE in mode
register 1 = 1), the IRQ line can be connected only to a processor that uses level-triggered interrupts.

MODEM HANDLING
The TxEMT (transmitter empty) bit of the status register is
typically used to indicate when a program can disable the
transmission medium, as when deasserting the request-tosend line of a modem. A typical program will load the last
character for transmission and then monitor the TxEMT bit
of the status register.
The assertion of the TxEMT bit to indicate the transmission
is complete may occur a substantial time after the loading
of the last character. After the last character is loaded, one
character is in the transmitter holding register and one
character is in the serialization logic. Therefore, it will be
two character times before the transmission process is
completed. Waiting for the TxRDY signal to assert before
monitoring the TxEMT status shortens this by one character time because the TxRDY status bit indicates that there
are no characters in the transmitter holding register. The
times involved are calculated by taking the reciprocal of the
baud rate being used, multiplying by the number of bits per
character (a starter bit-5,6,?, or 8 data bits; plus parity bit
if enabled; and 1,1.5, or 2 stop bits), and multiplying by either
two characters or one, depending on when TxEMT monitoring begins.

V DD

t

TEST
POINT
TEST
POINT

Ik

,

FROM
OUTPUT"

Sl

V DD

V DD

n

I kSl

FROM
,
OUTPUT

I k Sl

1

c..o

1

I k rl
1

1

T
CC

If'

l'....
Sl CLOSED: PULL UP
S2 CLOSED: PULL DOWN
S1 AND S2 CLOSED: DIVIDER
LOAD 8 - THREE-STATE OUTPUTS

LOAD A - STANDARD OUTPUTS

FIGURE 9-COM78C804 OUTPUT LOAD CIRCUITS
129

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range .................................................................................. O°C to + 700C
Storage Temperature Range ................................................................................. - 55° to + 125°C
Lead Temperature (soldering, 10 sec.) ................................................................................ + 300°C
Positive Voltage on any I/O Pin, with respectto ground ............................................................... Vee + 0.3V
Negative Voltage on any I/O Pin, with respect to ground .................................................................. - 0.3V
Maximum Vee ........................................................................................................... + 7V
·Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. For example, the bench
power supply programmed to deliver +5 volts may have large voltage transients when the AC power is switched on and off. If this
possibility exists it is suggested that a clamp circuit be used.
'

TABLE 9-COM78C804
DC ELECTRICAL CHARACTERISTICS
Symbol

Parameter

V,H
V,L
VOH

High-level input voltage
Low-level input voltage
High-level output voltage

VOL

I'H
I'L
los'

IOZ!'
1000'
100

C1n.
CI03

Test Condition

Voo=Min.
10H = 3.5 rnA for DL <7:0>
IOH = 2.0 rnA for all
remaining output except IRQ
andRDY
Low-level output voltage
Voo=Min.
10L = 5.5 rnA for DL <7:0>
IOL = 3.5 rnA for all remaining
outputs
Input current at maximum Voo=Max.
input voltage
V, = Voo(Max.)
Input current at miminum Voo=Max.
input voltage
V,=O.OV
Short-circuit output
Voo=Max.
current for DL<7:0> all
remaininQ..Qillputs except
IRQandRDY
Three-state output
Voo = Max.
current
Vo=O.4V
Three-state output
Voo=Max.
current
Vo=2.4V
Supply current
Voo=Max.
TA=O°
Input capacitance
Input/output capacitance

Requirements
Min. Typ. Max.
2.0
0.8
2.4

0.4

Units
V
V
V

V

10

I1A

-10

!LA

-50

-180

rnA

-30

-110
10

rnA

10

I1A

20

rnA

4
5

pF
pF

!LA

'No more than one ouput should be short circuited at a time, and the duration of the short should not exceed 1 second.
'All three-state output drivers are wired in an I/O configuration, The parameters include the driver and input receiver leakage currents.
"The parameters include the capacitive loads of the output driver and the input receiver,

TIMING PARAMETERS

11 shows the signal timing for a write cycle to transfer inforFigure 10 shows the signal timing for a read cycle to transfer mation from the processor to the Quad UART. Table 11 lists
information from the Quad UART to the processor. Figure the timing parameters for the read and write cycles.
130

.~

DS

~tDPWLR_
AOD<4:0 ~

tOPWH

IX

VALID ADDRESS

X

-I.-.

tASU

~tAHO

~L

twsu

~tWHO

tesu

f--l- _tCHO

~

~

\J

~
Ol < 7:0

tADL

...

tRD~

~VALID DATAOUT~
tDDZL, tDDZH If~OF....!
]

>

~ tDD-.j

tDOLZ, t.[JOHZ

I--t,O

FIGURE 10-COM78C804 BUS READ CYCLE TIMING

os
_tOPWLW _ _

J(J

ADO<4:0>

~

VALID ADDRESS

h

tASU

X

-+tAHO

j

'\
_·wsu

-

tWHO

J

-

tcsu

~ r tCHO

'\
_

-~

tOPWH

j.tRD~

tRDL\.-

DL<7:0>

VALID DATA IN
j.-'OSU-ll--'DHO-/

~tlj
FIGURE 11-COM78C804 BUS WRITE CYCLE TIMING
131

TABLE 10-COM78C804 BUS READ AND WRITE TIMING PARAMETERS
Symbol

Definition

tAHO

Hold time of a valid AOO <4:0> to a valid high level of
OS.
Setup time of a valid AOO <4:0> to the falling edge of
OS.
Hold time of a valid low level of CS to a valid high level of
OS.
Setup time of a valid low level of CS to the falling edge of
OS.
Prop~tion delay of a valid low level on OS (if CS is low
and WR is high) to valid high or low data on OL <7:0>.
Prop~tion delay of a valid high level on OS (if CS is low
and WR is high) to OL <7:0> output drivers disabled.

tASU

IeHO

lesu
too
t ODt.z2

Requirements (ns)
Min.
Max.
10
30
10
30
165

tODL2
tOOHZ

tODl2
tOOHZ

tDDl2
tOOHZ

tODZL

tOPWH
tOPWLR

tOPWLW

tosu

t l03
tADH4

tROl

tWHO

twsu

50
50
60
60
65
65

CL=50pF
CL=50pF
CL=100pF
CL=100pF
CL=150pF
CL=150pF

165
165

CL=150pF
CL= 150pF

delay of a valid low level on OS (if CS is low
and WR is high) to OL <7:0> output driver enabled.
tOOZH

t OHO

CL=150 pF

Prop~tion

tOOZL

tDF

Load
Circuit'

Hold time provided during a read cycle by Quad UART of
valid high or low data on OL <7:0> after the rising edge
of OS.'
Hold time of a valid OL <7:0> to a valid high level of OS.
Pulse width high of OS.
Pulse width low of OS when WR is high (read operation).
Refer to timing parameter tDPWLW also.
Pulse width low of OS when WR is low (write operation).
Refer to timing parameter tDPWLR also.
Setup time of a valid OL <7:0> to the rising edge of OS.
Propagation delay....QLa valid low level on OS (if CS is low)
to a high level on IRQ.
Propagation ~ of a valid high level of CS to a valid
high level on ROY.
Propagation delay of a valid low level on CS to a valid
low level on ROY.
Hold time of a valid high or low level of WR to a valid high
level of OS.
Setup time of a valid high or low level of WR to the falling
edge of OS.

0

0
30
450
180

10,000

130
50

10,000

635

CL=50pF

210

CL=50pF

90

CL=50pF

10
30

'Refer to Figure 9 for the load circuits used with these measurements.
'The tDDl2 and tDDHZ parameters are measured with CL=150 pF. The values of tDDLZ and tDDHZ for CL=50pF and CL=100 pF have been derived for user
convenience.
'Total rise time depends on internal delay plus the pullup delay introduced by the external resistor being used. The t'D parameter can be calculated
by the following: t'D =500 + RCLwhere R=value of the resistor that connects to capacitor CLin load A, Figure 9.
'Total rise time depends on internal delay plus the pullup delay introduced by the external resistor being used. The tRDH parameter can be calculated
by the following: tRDH =75 + RC Lwhere R=value of the resistor that connects to capacitor CLin load A, Figure 9.

Figure 12 shows the signal timing for the clock input, inter- timing, and the transmit data output timing. Table 11 lists the
rupt timing, effect of the RESET input on data strobe, data timing parameters for Figure 12.
set carrier detect (OCO) and data set ready (OSR) input
132

ClK

CLOCK

IROLN

J

XL

< 1 0 > IAQTxAx

t-,J

L",eJ

IRO

INTERRUPT

RESET

1.

tRES

1.

DS

tORSU

:~.

.~

tORHO

EFFECT OF RESET ON DATA STROBE

DCD DSR < 3:0 >

XI'i-__...;V...;A::.LI..:;D..:;D.:;CD;..,;;,:DS::;R..:;D;.:.AT;.:.A:...-_-i'lXl.._ _ _ _ _ _ _ _ _ __

- - - - - ' 1/4.----tDSPW-----.j.1

DCD'DSR INPUT

TxD

< 3:0 >

LtTXSK_LtTXSK~-------,rTRANSMIT DATA OUTPUT

FIGURE 12-COM78C804 MISCELLANEOUS SIGNAL TIMING
TABLE 11-MISCELLANEOUS WRITE TIMING PARAMETERS
Symbol

Definition

Requirements (ns)
Min.

tcp

Period of ClK

203,45 (4,9152 MHz)

tCPWH

Pulse width high of ClK,

t CPWL

Pulse width low of ClK,

tDAHO

Hold time of a valid high level of DS to a valid high level
of RESET.

t OASU

Setup time of a valid high level of DS to the rising edge of
RESET,

Load Circuit'

95
95
1,000
900

tospw

Pulse width high or low of DCD <3:0> and DSR <3:0>,

tlHO

Hold time provided by Quad UART from a valid IRQlN
<1 :0> and IRQTxRx to a valid high level of IRQ,

100

CL =50pF

tlSU

Setup time provided by Quad UART from a valid IRQlN
<1 :0> and IRQTxRx to a valid low level of IRQ,

100

CL =50pF

tRES

tTXSK

Pulse width low of RESET,

1,000

1,000

Pulse width high or low provided by Quad UART on the
TxD <3:0> lines, At each baud rate, the actual pulse
widths provided vary by tmK , This timing parameter
should be used to determine cumulative reception/transmission errors,

·Refer to Figure 9 for the load circuits used with these measurements,

133

250

CL =50pF

Figure 13 shows the input and output voltage waveforms
for the propagation delay and setup and hold measure-

ments. Figure 14 shows the waveforms for the three-state
outputs measurement.

VIH(~~~'=::::::J(
INPUT

0.8V

J-i-

VIL (0.4 VI

r
u

-

j

\

~

______

'L.H

~·'-~:=u-lu'\
~L~H -J
va (20 VI ______

IN·PHASE OUTPUT

SET-UP AND HOLD

__

P-'H'L-""-,

I

f.-

;-

/

1

\L

'H·L

Va (0.8 VI ---~.
PROPAGATION DELAY

FIGURE 13-COM78C804 PROPAGATION DELAY
AND SETUP AND HOLD VOLTAGE WAVEFORMS

VIN (2.4 VI
2.0V
dUTPUT CONTROL

0.8 V

(NOTE 3C)

'-_-----:J- ---

VOL+0.5V

VOUT (AS MEASUREDI
VOH -0.5 V
1.5 V
OUTPUT VOL (NOTE 21
(0.0 VI
THREE·STATE OUTPUTS
NOTES,
1. INTERNAL CONDITIONS ARE SUCH THAT THE OUTPUT IS LOW EXCEPT WHEN DISABLED BY
THE OUTPUT CONTROL.

2. INTERNAL CONDITIONS ARE SUCH THAT THE OUTPUT IS HIGH EXCEPT WHEN DISABLED BY
TH E OUTPUT CONTROL.
3.

REFER TO FIGURE 9. A", 51 CLOSED, B = 52 CLOSED. C "" 51 AND 52 CLOSED.

FIGURE 14-COM78C804 THREE-STATE OUTPUT VOLTAGE WAVEFORMS

~

~.~~~:: Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications: consequently complete info(mation sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
il.T,"~i"~:. ~"1:~"'I,,1,\,"':~~ assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the right to
make changes at any time in order to improve design and supply the best product possible.

134

COM78808
PRELIMINARY

Eight-channel Universal
Asynchronous Receiver/Transmitter
Octal UART
PIN CONFIGURATION

FEATURES

D Eight independent full duplex serial data lines

D Programmable baud rates individually selectable for
each line's transmitter/receiver (50 to 19,200 baud)

D Summary registers that allow a single read to detect a
data set change or to determine the cause of an interrupt on any line

D Triple buffers for each receiver

D Device scanner mechanism that reports interrupt
request due transmitter/receiver interrupts

TxD7

61

43

VSS2

DSR7

62

42

DeD?

63

41

Tx03
DSA3

RxD7

64

40

DCD3

RxD6

65

39

DCD6

66

38

RxD3
RxD2

OSR6

67

37

Tx06

68

DSR2

35

Tx02

34

Tx01

33

DSR1

32

DCD1

RxD4

31

RxD1

DCD4
DSR4

6
7

30

RxDO

29

DC DO

Tx04
VOO

8
9

5SR5
DCD5
RxD5

D Independently programmable lines for interrupt-driven
operation

D Modem status change detection for Data Set Ready
(DSR) and Data Carrier Detect (DCD) signals

DCD2

36

78808

Tx05

CAVITY DOWN CONNECTIONS

2
3

28

DSRO

27

TxDO

1011121314151617181920212223242526

D Programmable interrupts for modem status changes

1"-

'"

~ -1>- 0 I'"
(j (j I~
N
~ 0 0
6B55~~~O~zz~5B06~
a:

D Synchronizes critical read-only registers

PACKAGES: 68-pin PLCC

GENERAL DESCRIPTION
The COM78808 Eight-channel Asynchronous Receiver/
Transmitter (Octal UART) is a VLSI device for new generations of asynchronGus serial communication designs and
for microcomputer systems. This 58-pin device performs the

basic operations necessary for simultaneous reception and
transmission of asynchronous messages on eight independent lines. Figure 1 is a functional block diagram of the
COM78808 Octal UART.

135

For additional information, consult your 1986 catalog or contact our product marketing department at (516) 273-3100.

~

~,~~~::~ Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
applications: consequently complete information sufficient for construction purposes is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsilillity is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design and supply the best product possible.

136

COM78C808
PRELIMINARY

Eight-channel Universal
Asynchronous Receiver/Transmitter
Octal UART
FEATURES

I

PIN CONFIGURATION

o Eight independent full duplex serial data lines
o Programmable baud rates individually selectable for
each line's transmitter/receiver (50 to 19,200 baud)

o Summary registers that allow a single read to detect a
data set change or to determine the cause of an interrupt on any line

o Triple buffers for each receiver
o Device scanner mechanism that reports interrupt
request due transmitter/receiver interrupts

COM78C808

o Independently programmable lines for interrupt-driven
operation

o Modem status change detection for Data Set Ready
(DSR) and Data Carrier Detect (DCD) signals

o Programmable interrupts for modem status changes
o Synchronizes critical read-only registers
o Low power CMOS technology
o + 5V only power supply
o Compatible with COM78C804 and COM78C802

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27

PACKAGE: B8-pin PLCC

GENERAL DESCRIPTION
The COM78C808 Eight-channel Asynchronous Receiver/ basic operations necessary for simultaneous reception and
Transmitter (Octal UART) is a VLSI device for new gener- transmission of asynchronous messages on eight indeations of asynchronous serial communication designs and pendent lines. Figure 1 is a functional block diagram of the
for microcomputer systems. This 68-pin device performs the COM78C808 Octal UART.

137

TxDO

RxDO
DSRO

DCDO
INTERRUPT
SUMMARY
REGISTER

Tx01

RxD1
DSRl
DCDl
TxD2

RxD2
DSR2
DCD:!

TxD3
RxD3
DSR3
DCD3

DATA SET
CHANGE
SUMMARY
REGISTER

TxD4
RxD4
DSR4
DCD4

TxD5
RxD5
DSR5
DCD5

TxD6
RxD6
DSR6
DCD6

TxD7

RxD7
DSR7
' -_ _ _~.---- DCD7

FIGURE 1 - COM78C808 OCTAL UART FUNCTIONAL BLOCK DIAGRAM
TABLE 1 - COM78C808 PIN AND SIGNAL SUMMARY
Pin

Signal

Input/Output

Definition/Function

10-13,22-25

Dl<7:0>

input/output

Data lines <7:0>-Receives and transmits the parallel
data.

50-52,54-56

ADD <0:5>

input

Address-Selects the internal registers in the Octal
UART.

17

CS

input

Chip select-Activates the Octal UART to receive and transmit data over the Dl<7:0> lines.

21,53

DS1,DS2

input

Data strobe 1 and 2-Receives timing information for data
transfers. The DS1 and DS2 inputs must be connected
together.

18

WR

input

Write-Specifies direction of data transfer on the Dl<7:0>
lines.

14

ROY

output

Ready-Indicates when the Octal UART is ready to participate in data transfer cycles.
Reset-Initializes the internal logic.

15

RESET

input

57

MRESET

input

Manufacturing reset-For manufacturing use.

58

ClK

input

Clock-Clock input for timing.

62,67,2,7,
41,36,33,28

DSR<7:0>

inputs

Data set ready-Monitor data set ready (DSR) signals from
modems.

63,66,3,6,
40,37,32,29

DCD<7:0>

inputs

Data set carrier detect-Monitor data set carrier detect
(DCD) signals from modems.

49

IRQ

output

interrupt request-Requests a processor interrupt.

45-47

IRQlN <0:2>

output

Interrupt request line number-Indicates the line number of
originating interrupt request.

48

IRQTxRx

output

Interrupt request transmit/receive-Indicates whether an
interrupt request is for transmitting or receiving data.

61,68,1,8,
42,35,34,27

TxD<7:0>

outputs

Transmit data-Provides asynchronous bit-serial data output streams.

64,65,4,5,
39,38,31,30

RxD<7:0>

inputs

Receive data-Accepts asynchronous bit-serial data input
streams.

44,26,9

Vee

input

Voltage-Power supply voltage

16,59,43

Vss

input

Ground-Ground reference

138

+ 5 Vdc.

DATA AND ADDRESS
Data lines (DL<7:0»-These lines are used for the parallel transmission and reception of data between the CPU
and the Octal UART. The receivers are active when the data
strobe (DSf, OS2) signal is asserted. The output drivers are
active only when the chip select (CS) signal is asserted, the
data strobe (OSl, OS2) signal is asserted, and the write
(WFi) signal is deasserted. The drivers will become inactive
(high-impedance) within 50 nanoseconds when one or more
of the following occurs: the ch.!P..§!llect (CS) signal is deasserted, the data strobe (OS 1, OS2) signal is deasserted, or
the write (WR) signal is asserted.

Address (ADD<5:0»-These lines select which Octal
UART internal register is accessible through the data I/O
lines (OL <7:0» when the data strobe (OSl, OS2) and chip
select (CS) signals are asserted. Table 2 lists the addresses
corresponding to each register. The receiver buffer and
transmitter holding @9lster for each line have the same
address. When the (WR) signal is deasserted, the address
accesses the receiver buffer register and when asserted, it
accesses the transmitter holding register.

TABLE 2 - COM78C808 REGISTERS ADDRESS SELECTION
ADD Line*

Read/Write

Register

0
0
1
0
1

Read
Write
Read
Read/Write
Read/Write

Line 0 Receiver Buffer
Line 0 Transmitter Holding
Line 0 Status
Line 0 Mode Registers 1,2
Line 0 Command

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
Read/Write
ReadlWrite

Line 1 Receiver Buffer
Line 1 Transmitter Holding
Line 1 Status
Line 1 Mode Register 1 ,2
Line 1 Command

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
ReadlWrite
ReadlWrite

Line 2 Receiver Buffer
Line 2 Transmitter Holding
Line 2 Status
Line 2 Mode Register 1.2
Line 2 Command

1
1
1
1
1

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
ReadlWrite
Read/Write

Line 3 Receiver Buffer
Line 3 Transmitter Holding
Line 3 Status
Line 3 Mode Register 1,2
Line 3 Command

0
0
0
0
0
1
1
1
1

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
Read/Write
ReadlWrite

Line 4 Receiver Buffer
Line 4 Transmitter Holding
Line 4 Status
Line 4 Mode Register 1.2
Line 4 Command

0
0
0
1
1

0
0
1
0

1

0
0
0
0
0

1

Read
Write
Read
Read/Write
Read/Write

Line 5 Receiver Buffer
Line 5 Transmitter Holding
Line 5 Status
Line 5 Mode Register 1,2
Line 5 Command

0
0
0
0
0

0
0
0
0
0

0
0
0
1
1

0
0
1
0
1

Read
Write
Read
Read
Read/Write

Line 6 Receiver Buffer
Line 6 Transmitter Holding
Line 6 Status
Line 6 Mode Register 1,2
Line 6 Command

1
1
1
1
1

1
1

0
0
0
1
1

0
0

1

0
0
0
0
0

Read
Write
Read
Read/Write
ReadlWrite

Line 7 Receiver Buffer
Line 7 Transmitter Holding
Line 7 Status
Line 7 Mode Register 1.2
Line 7 Command

X
X

X
X

1
1

0
0

Read
Read

Interrupt Summary
Data Set Change Summary

<5>

<4>

<3>

<2>

<1>

<0>

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
1
1

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0
1
1
1
1
1

0
0
0
0
0

0
0
0
0
0

1
1
1
1
1

0
0
0
0
0

0
0
0
0
0

1
1
1
1
1

1
1
1
1
1

0
0
0
0
0

1
1
1
1
1

0
0
0
0
0

1
1
1
1
1

1
1
1
1
1

1
1
1
1
1

X
X

1
1

1

0
1

0
1

*X= Either 0 or 1.

BUS TRANSACTION CONTROL
Chip select (CS)-This signal is asserted to permit data ing information for data transfers. During a write cycle, the
transfers through the OL <7:0> lines to or from the internal CPU asserts the data strobe signal when valid output data
registers. Data transfer is controlled by the data strobe (081, is available and deasserts the data strobe signal before the
082) signal and write (WR) signal.
data is removed. During a read cycle, the CPU asserts the
____
data strobe signal and the Octal UART transfers the valid
Data strobe(DS1, DS2)- The data strobe inputs (081 and data. When the data strobe signal is deasserted, the
082) must be connected together. This input receives tim- OL<7:0> lines become a high impedance.
139

Write (WR)-The write (WR) signal specifies the direction
of data transfer on the DL<7:0> Rins by controlling the
direction of their transceiversJUhe WR signal is asserted
during a data transfer (the CS, DS1, and DS2 signals
assert~ the Octal UART is receiving data from DL<7:0>.
If the WR signal is deasserted during a write data transfer,
the Octal UART is driving data onto the DL <7:0> lin.es.
INTERRUPT REQUEST
Interrupt request IRQ-The IRQ pin is an open drain output. The integral interrupt scanner asserts the IRQ signal
when it has detected an interrupt condition on one of the
eight serial data lines.

to be asserted. A TTL high at a DSR pin causes the DSR
bit in the corresponding line's status register to be deasserted. A change of this input from high-to-Iow, or low-tohigh, causes the assertion of the data set change
(DSCHNG) bit that corresponds to this line in the data set
change summary register. Changes from one state to the
other and back again that occur within one microsecond may
not be detected.
Carrier detect (DCD<7:0»-These eight input pins, one
for each serial data line of the Octal UART, are typically connected through intervening level converters to the received
line signal detect (also called carrier detect) outputs of
modems. A TTL low at a DCD pin causes the DCD bit of the
corresponding line's status register to be deasserted. A
change of this input from high-to-Iow, or low-to-high, causes
the assertion of the data set change (DSCHNG) bit corresponding to this line in the data set change summary register. Changes from one state to the other and back again
that occur within one microsecond may not be detected.

Interrupt Request transmit/receive (IRQTxRx)-This
signal indicates when the interrupt scanner in the Octal
UART stops and asserts fRO because of a transmitter
interrupt condition (the IRQTxRx signal is asserted) or
because of ~ receiver interrupt condition (the IRQTxRx signal is deasserted). The signal is valid only while IRQ is
asserted. The state of IRQTxRx signal also appears as bit GENERAL CONTROL SIGNALS
o of the interrupt summary register.
Ready (RDV)-The ROY pin is an open drain output. Upon
detecting a negative transition of chip select (CS), the Octal
Interrupt request line number (IRQLN<2:0»-These UART asserts the ROY signal to indicate readiness to take
lines indicate the line number at which the Octal UART part in data transfer~cles. The ROY signal deasserts after
interrupt scanner stopped and asserted the interrupt request the trailing edge of CS.
(IR~nal. The number on these lines is valid only while
the IRQ signal is asserted. Line IRQLN<2> is the high- Reset (RESET)-When the RESET input is asserted, the
order bit and the IRQLN line is the low-order bit. The TxD<7:0> lines are asserted and all internal status bits
state of these signals also appears as bits in the interrupt listed in the "Architecture Summary" discussion are cleared.
summary register: IRQLN<2> as bit 3, IRQLN<1 > as bit Manufacturing reset (MRESET)-This signal is for man2, and IRQLN as bit 1. Table 3 shows the line numbers ufacturing use only and the input should be connected to
corresponding to settings of IRQLN<2:0>.
ground for normal operation.

MISCELLANEOUS SIGNALS
TABLE 3 - COM78C808 INTERRUPT REQUEST
LINE ASSIGNMENTS
IRQ Line

Line

<2>

<1>

<0>

0

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
1
1
1

0
1
2
3
4
5
6
7

Clock In (CLK)-AII baud rates and internal clocks are
derived from this input. Normal operating frequency is
4.9152 MHz ± 0.1 percent and duty cycle is 50 percent ± 5
percent.

POWER AND GROUND
Voltage (Voo)-Power supply 5 Vdc
Ground (Vss)-Ground reference

ARCHITECTURE SUMMARY

The Octal UART functions as a serial-to-parallel, parallelto-serial converter/controller. It can be programmed by a
microprocessor to provide different characteristics for each
of its eight serial data lines (stop bits, parity, character length,
split baud rates, etc.)
SERIAL DATA
Each serial line functions the same as a one-line UARTTransmit data (TxD<7:0»-These outputs transmit the type device thereby reducing the number of chips and conasynchronous bit-serial data streams. They remain at a high serving space on communication devices that require mullevel when no data is being transmitted and a low level when tiple communications lines.
the TxBRK bit in the associated line's command register is An integral interrupt scanner checks for device interrupt
set.
conditions on the eight lines. Its scanning algorithm gives
Receive data (RxD<7:0»-These lines accept asyn- priority to receivers overtransmitters. The scanner can also
chronous bit-serial data streams. The input siQnals must check for interrupts resulting from changes in modem conremain in the high state for at least one-half bit time before trol signals DSR and DCD.
·fl R 1
a high-to-Iow transition is recognized. (A high-to-Iow tran- L·
sition is required to signal the beginning of a "start" bit and
me-speci c eg sters
initiate data reception).
Each of the eight serial data lines in the Octal UART has a
set of registers for buffering data into and out of the line and
MODEM SIGNALS
for external control of the line's characteristics. These regData set ready (DSR<7:0»-These eight input pins, one isters are selected for access by setting the appropriate
Tor each seriar data Irne on the COM78C808, are typically address on lines ADD<5:0>. Lines ADD<5:3> select one
connected via intervening level converters to the data set of the eight data lines. Lines ADD<2:0> select the specific
ready outputs of modems. A TTL low at a DSR pin causes register for that line. Refer to Table 2 for the register address
the DSR bit (bit 7) in the corresponding line's status register assignments.
140

Receiver buffer register-Each line's receiver consists of
a character assembly register and a two-entry FIFO that is
the receiver buffer register. When the RxEN bit in a line's
command register is set, received characters are moved
automatically into the line's receiver buffer as soon as they
have been deserialized from the associated communications line. When there are characters in this FIFO, the
RxRDY bit is set in the status register for the line.
The assertion of the RxRDY signal for a line that already
has the RxlE bit of its command register set causes the
interrupt scan~ogic to stop and generate an interrupt
condition (the IRQ signal is asserted). When the receiver
buffer is read, the interrupt condition is cleared (the IRQ
signal is deasserted) and the interrupt scanner resumes
operation.
If there is another entry in a line's FIFO, the RxRDY bit
remains asserted. When the interrupt scanner reaches this
line again, the assertion of RxRDY causes the scanner to
halt and assert the IRQ again.
Asserting the RESET signal or clearing the RxEN bit initializes the receiver logic of Octal UART. The RxRDY flag is
cleared and the receiver buffer register outputs become
undefined. Any data in the FIFO at that time is lost.

Assertion of the RESET signal initializes the transmitter logic
of the Octal UART. The TxRDY flag is cleared and the transmitter holding register's contents are lost. The transmitter
enable (TxEN) bit in the line's command register is also
cleared by RESET. If at the end of the reset process, the
TxEN is reasserted and TxRDY bit is reasserted. Software
clearing of TxEN alone produces results different from the
full RESET in that the transmitter holding register's contents are not lost; they are transmitted when TxEN is set
again.
Status register-Each line has a read-only status register
that provides information about the current state of the given
line. This register indicates a line's readiness for transmission or reception of data and flags error conditions in its bit
fields. Figure 3 shows the format of the status register. Table
3 lists the flag bits in each status register.

Transmitter holding register-Each line has a writable
transmitter holding register. When the TxEN bit in the line's
command register is set, characters are moved automatically from the output of this register into the transmitter serialization logic whenever the serialization logic becomes idle.
When this register is empty, the TxRDY bit in the line's status register is set. If the transmitter interrupt enable (TxIE)
bit in the line's command register is also set, the interrupt
scanner logic halts and generates an interrupt condition. If
a character is then loaded into the register, the interrupt is
cleared and the scanner resumes operation.

DSR
DCD-----'

FER - - - - - - - '
ORR-------~

PER

----------..!

TxEMT-------------'
RxROy-----------------'
TxRDY------------------'

FIGURE 3 - COM78C808 STATUS REGISTERS
(LINE 0-7) FORMAT

TABLE 4 - COM78C808 STATUS REGISTERS (LINES 0-7) DESCRIPTION
Bit

Description

7

DSR (Data set ready)-This bit is the inverted state of the DSR line.

6

DCD (Data set carrier detect)-This bit is the inverted state of the DCD line.

5

FER (Frame error)-Set when the received character currently displayed in the receiver buffer register was not
framed by a stop bit. Only the first stop bit is checked to determine that a framing error exists. Subsequent
reading of the receiver buffer register that indicates all zeros (including the parity bit, if any) can be interpreted
as a Break condition. This bit is cleared by clearing RxEN (bit 2) of the command register, by asserting the
RESET input, or by setting the reset error RERR (bit 4) of the command register.

4

ORR (Overrun error)-Set when the character in the receiver buffer register was not read before another character was received. Cleared by clearing RxEN (bit 2) of the command register, by asserting the RESET input,
or by setting reset error RERR (bit 4) of the command register.

3

PER (Parity error)-If parity is enabled and this bit is set, the received character in the receiver buffer register
has an incorrect parity bit. This bit is cleared by clearing RxEN (bit 2) of the command register, by asserting the
RESET input, by setting reset error RERR (bit 2) of the command register, or by reading the current character
in the receiver buffer register.

2

TxEMT (Transmitter empty)-Set when the transmitter serialization logic for the associated line has completed
transmission of a character, and no new character has been loaded into the transmitter holding register.
Cleared by loading the transmitter holding register, by clearing TxEN (0) of the command register, or by asserting the RESET input.

1

RxRDY (Receiver buffer ready)-When set, a character has been loaded into the FIFO buffer from the deserialization logic. Cleared by reading the receiver buffer register, by clearing RxEN (bit 2) in the command register,
or by asserting the RESET input.

0

TxRDY (Transmitter holding register ready)-When set, this bit indicates that the transmitter holding register is
empty. Cleared when the program has loaded a character into the transmitter holding register, when the transmitter for this line is disabled by clearing TxEN (bit 0) in the command register, or by asserting the RESET
input. This bit is initially set when the transmitter logic is enabled by the setting of TxEN (bit 0) and the transmitter holding register is empty. This bit is not set when the automatic echo or remote loopback modes are programmed. Data can be overwritten if a consecutive write is performed while TxRDY is cleared.

141

Mode registers 1 and 2- These read/write registers con- Figure 4 shows the format of mode registers 1 and Table 5
trol the attributes (including parity, character length, and line describes the function of the register information.
speed) of the communications line.
Each of the eight communications lines has two of these
registers, both accessed by the same address on
AOO<5:0>. Successive access operations (either read or
write, in any combination) alternate between the two registers at that address by use of an internal pointer. The first
STOP-----'
operation addresses mode register 1, the next address
PARCTRL--------'
mode register 2, and another after that would recycle the
CH.AR LENGTH - - - - - - - - - - '
R
- -_
--_
- -_
---_
- -_
-' _--J
pointer to mode register 1. The pointer is reset to point to
MCIES
_R
_V
__
_
_
_
_
mode register 1 by ~ or by a read of the command
register for this line. These registers should not be accessed
FIGURE 4 - COM78C808 MODE
by bit-oriented instructions that do read/modify/write cycles
REGISTERS 1 (LINE 0-7) FORMAT
such as the POP-11 BIS, BIC, and BIT instructions.

TABLE 5 - COM78C808 MODE REGISTERS 1 (LINES 0-7) DESCRIPTION
Bit

Description

7,6

STOP-These bits determine the number of stoR bits that are appended to the transmitted characters as
follows. These bits are cleared by asserting the RESET input.
Bits
Stop Bits

7
0
0
1
1
5,4

6
0
1
0
1

Invalid
1.0
1.5
2.0

PAR CTRL (Parity control)-These bits determine parity as follows and are cleared by asserting the RESET
input. X = either 1 or O.
Bits
Parity Type

5

4

1
0
X
3,2

1
Even
1
Odd
Disabled
0
CHAR LENGTH (Character length)-These bits determine the length (excluding start bit, parity, and stop
bits) of the characters received and sent. Received characters of less than 8 bits are "right aligned" in the
receiver buffer with unused high-order bits equal to zero. Parity bits are not shown in the receiver buffer. The
character length bits are cleared by asserting the RESET input. The character length bits are defined as
follows:
Bit
Bit Length

3

2

0
0
1
1

0
1
0
1

5

6
7
8

1

RSRV (Reserved and cleared by asserting the RESET input.)

0

MCIE (Modem control interrupt enable)-When set and RxlE (bit 5) of the command register is set, the
modem control interrupts are enabled. Refer to the Interrupt Scanner and Interrupt Handling information.
Cleared by asserting the RESET input.

Figure 5 shows the format of mode registers 2 and Table
6 indicates the baud rate selections of the register. Bits 7
through 4 of the mode register 2 control the transmitter
baud rate and bits 3 through 0 control the receiver baud
rate. These registers are cleared by asserting RESET input.

Command register-These read/write registers control
various functions on the selected line. Figure 6 shows the
format of the command registers and Table 6 describes
the function of the register information.

I

I

I

OPER M O D E Y
Rx I E

"

I

I

I

I

I

I

RERR
TxBR K

XMIT RATE _ _ _--J

RxEN

RECV RATE - - - - - - - - - - - '

Tx I E

TxEN

FIGURE 5 - COM78C808 MODE
REGISTERS 2 (LINE 0-7) FORMAT

FIGURE 6 - COM78C808 COMMAND
REGISTERS (LINE 0-7) FORMAT
142

I

TABLE 6 - COM78C808 MODE REGISTERS 2 (LINES 0-7) DESCRIPTION
Bit

Description

7:0

XMIT RATE/RECV RATE (Transmitter/Receiver Rate)-Selects the baud rate of the
receiver (bits 3:0) as follows:
Transmitter Bits
Receiver Bits
Nominal
7
4
Rate
6
5
3
2
1
0
0
0
0
0
0
0
0
50
0
1
1
0
0
0
0
0
0
75
0
110
0
1
1
0
0
0
0
1
1
134.5
0
0
1
0
0
1
0
0
150
0
1
1
0
0
0
1
1
1
1
0
0
0
0
300
0
1
1
0
0
1
1
0
600
0
1
1
1
1
1
1
1200
0
0
1800
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
2000
2400
1
1
1
1
0
0
0
0
1
0
1
1
1
0
1
1
3600
1
1
1
1
0
4800
0
0
0
1
1
1
1
1
1
0
0
7200
1
1
1
1
1
1
0
9600
0
1
1
1
1
1
1
1
1
19200

transmitter (bits 7:4) and
Actual
Rate
same
same
109.09
133.33
same
same
same
same
1745.45
2021.05
same
3490.91
same
6981.81
same
same

Error"
(percent)

-

0.826
0.867

-

3.03
1.05

-

3.03

-

3.03

'The frequency of the clock input (CLK) is 4.9152 MHz. The clock input may vary by 0.1 percent. This variance results in an error
that must be added to the error listed.

TABLE 7 - COM78C808 COMMAND REGISTERS (LINES 0-7) DESCRIPTION
Bit
7,6

5
4
3

Description
OPER MODE (Operating mode)-These bits control the operating mode of the channel as follows. These
bits are cleared by asserting the RESET input.
Bit
Operating Mode
7
6
Normal operation
0
0
1
Automatic echo
0
1
0
Local loopback
1
1
Remote loopback
RxlE (Receiver interrupt enable)-When set, the RxRDY flag (bit 1) of the status register for this line will
generate an interrupt.
RERR (Reset error)-When set, this bit clears the framing error, overrun error, and parity error of the status
register associated with this line. This bit is cleared by asserting the RESET input (not self-clearing).
TxBRK (Transmit break)-When set, this bit forces the appropriate TxD<7:0> line to the spacing state at
the conclusion of the character presently being transmjtted. When the program clears this bit, normal operation is restored, and any character pending in the transmitter holding register is moved into the serialization
logic and transmitted. The minimum break length obtainable is twice the character length plus 1 bit time.
The maximum break length depends on the amount of time between the program setting and clearing this
bit, but is an integral number of bit times. This bit is cleared by asserting the RESET input.

2

RxEN (Receiver enable)-When set, this bit enables the receiver logic. When cleared, it stops the assembling of the received character, clears all receiver error bits and the RxRDY (bit 1) of the status register,
clears any receiver interrupt conditions associated with this line, and initializes all receiver logic. This bit is
cleared by asserting the RESET input.

1

TxlE (Transmit interrupt enable)-When set, the state of the associated TxRDY flag (bit 0) of the status register is made available to the interrupt scanner logic. When the interrupt scanner logic scans this line, it
determines if the TxRDY flag is asserted and generates an interrupt by asserting the IRQ signal.
TxEN (Transmitter enable)-When set, this bit enables the transmitter logic. When cleared, it inhibits the
serialization of the characters that follow but the serialization of the current character is completed. It also
clears the TxRDY flag (bit 0) of the status register, clears any transmitter interrupt conditions associated with
this line, and initializes all transmitter logic except that associated with the transmitter holding register. The
character in the transmitter holding register is retained so that XON/XOFF situations can be properly processed. This bit is cleared by asserting the RESET input.

0

Bits 5 through 0 enable the line's receiver and transmitter,
enable handling of interrupts, initiate the transmission of
break characters, and reset error bits for the line. Refer to
"Interrupt Scanner" and "Interrupt Handling" paragraphs
for detailed interrupt information. Bits 7 and 6 control the
operating mode of the line. The four modes that can be
set are:

o Normal operation-The serial data received is assem-

143

bled in the receiver logic and transferred in parallel to the
receiver buffer register; (The RxEN bit must be set.) Data
to be transmitted is loaded in parallel into the transmitter
holding register, then automatically transferred into the
transmitter logic and serialized for transmission. (The
TxEN bit must be set.)

o Automatic echo-The serial data received is assembled

into parallel in the receiver logic (the RxEN bit must be
set) and transferred to the receiver buffer register. Arriving serial data is also routed to the line's TxD pin for
serial output. TxEN is ignored and the transmitter logic
is disabled. TxRDY flags and TxEMT indications are
cleared. No transmitter interrupts are generated.

o Localloopback-The serial data from the RxD input
is ignored and the receiver serial input receives data from
the transmitter serial output. The data is assembled into
parallel form in the receiver logic (the RxEN bit must be
set) and transferred to the receiver buffer register where
it can be read by the program. Data to be transmitted to
the receiver is loaded in parallel form into the transmitter
holding register from which it is automatically moved into
the transmitter logic and serialized for transmission. (The
TxEN bit must be set.) The transmission goes only to the
receiver serial input; the TxD output is held high. As
in normal operation, transmission and reception baud
rates are controlled by the transmitter speed and receiver
speed entries in mode register 2.

SUMMARY REGISTERS
The Octal UART contains two registers that summarize the
current status of all eight serial data lines, making it possible to determine that a line's status has changed with a single read operation. These registers are selected for access
by setting the appropriate address on pins ADD <2:0>.
Because the registers are shared by eight serial lines, the
line-selection bits (ADD <5:3» are ignored when these
registers are accessed. Refer ·to "Interrupt Scanner and
Interrupt Handling" for detailed interrupt information.

Interrupt summary register- This read-only register indicates that a transmitter or receiver interrupt condition has
occured, and indicates the line number that generated the
interrupt. Figure 7 shows the format of the interrupt summary register and Table 8 describes register information.

J
~RA~ ~-----,'-y-----''-------'---I

rlllill
::-----'---T'--+-r-'I

o Remote loopback-The serial data received on the
RxD line is returned to the TxD line without
further action. No data is received or transmitted. The
RxRDY, TxRDY, and TxEMT flags are disabled. The
TxEN and RxEN bits of the command register are held
cleared, causing the transmitter and receiver logic to be
disabled.

INT LINE NO

.

Tx.'Rx _ _ _ _ _ _ _ _ _ _ _ _ _ _----'

FIGURE 7 - COM78C808
INTERRUPT SUMMARY REGISTER FORMAT

TABLE 8 - COM78C808 INTERRUPT SUMMARY REGISTER DESCRIPTION
Bit

Description

7

IRQ (Interrupt request)-When set, this bit indicates that the interrupt scanner has found an interrupting condition among the eight serial lines of the Octal UART. These conditions also result in the Octal UART asserting the IRQ signal.
RAZ (Read as zero)-Not used
INT LINE NO (Interrupting line number)-These bits indicate the line number upon which an interrupting condition was found. These bits correspond tothe IRQLN <2:0> signals-(bit 3 = IRQLN<2>, bit 2= IRQLN,
and bit 1 = IRQLN. Refer to Table 3.
Tx/Rx (Transmitlreceive)-This bit indicates whether the interrupting condition was caused by a transmitter (Txl
Rx equals 1) or a receiver (Tx/Rx equals 0). This bit corresponds to the IRQTxRx signal of the Octal UART
and is set when IRQTxRx is asserted.

6:4
3:1*

0*

*Bits 3-0 above represent the outputs of a free-running counter and are valid only when bit 7 is set.

Data set change summary register-When the DSR or
DCD inputs that are associated with a line change state,
the bit corresponding to that line in this read-only register
is set. The current state of the DSR and DCD inputs can

DSCHNG 7 0 - - - - - - - - - '

FIGURE 8 - COM78C808 DATA SET CHANGE
SUMMARY REGISTER FORMAT

then be obtained from that line's status register. If the state
of a line changes twice within one microsecond, the change
in state may not be detected. Figure 8 shows the format
of the data set change summary register.
When the MCIE bit in a line's mode register 1 is set and
RxlE is also set, the modem control interrupts are enabled
for that line. If DSCHNG for that line is then set, the interrupt
scanner will halt and assert the IRQ signal. The data set
change summary register bits are cleared by writing a 1 into
the bit position. A program that uses this register should read
and save a copy of its contents. The copy can then be written back to the register to clear the bits that were set. The
system interrupts should be disabled and writeback should
directly follow the read operation.
Assertion of the RESET signal disables and initializes the
data set change logic. When the RESET signal is deasserted, future changes in DSR and DCD are reported as
they occur.

144

INTERRUPT SCANNER AND INTERRUPT HANDLING
The interrupt scanner is a four-bit counter that sequentially
checks lines 0 through 7 for a receiver interrupt (counter
positions (0-7) and then checks the lines in the same order
for a transmitter interrupt (counter positions 8-15). If the
scanner detects an interrupt condition, it stops and the IRQ
signal is asserted. An interrupt must be serviced by software or no other interrupt request can be posted.
The scanner determines that a line has a receiver interrupt
if the line's receiver buffer is ready and receiver interrupts
are enabled for that line (RxRDY and RxlE = 1) or either of
the line's modem status signals has changed state and both
receiver and modem control interrupts are enabled for that
line (DSCHNG and RxlE and MCIE = 1).
The scanner determines that a line has a transmitter interrupt if the line's transmitter holding the register is empty and
transmitter interrupts are enabled for that line (TxRDY and
TxIE=1).
When the scanner detects an interrupt, it reports the line
number on the IRQ<2:0> lines. The IRQTxRx signal is
asserted for a transmitter interrupt and deasserted for a
receiver interrupt. The appropriate bits are also updated in
the interrupt summary register. The IRQ line is deasserted
and the scanner is restarted for each of the following three
types of interrupt conditions.

o Reading the receiver buffer or resetting the RxlE bit of

the interrupting line for the first type of receiver interrupt
previously described.

o Resetting the MCIE, RxIE, or DSCHNG bit of the interrupting line for the second type of receiver interrupt previously described.

o Loading the transmitter holding register or resetting the
TxlE bit of the interrupting line for transmitter interrupts.

If the scanner was originally stopped by a receiver interrupt
condition, the scanner resumes sequential operation from

TEST
POINT

EDGE-TRIGGERED AND LEVEL-TRIGGERED INTERRUPT SYTSTEMS
If the interrupt system of the Octal UART is used only for
generating interrupts for the RxRDY and/or TxRDY flags,
the IRQ line can be connected to a processor having either
edge-triggered or level-triggered interrupt capability. If the
modem control interrupts are being used (MCIE in mode
register 1 = 1), the IRQ line can be connected only to a processor that uses level-triggered interrupts.

MODEM HANDLING
The TxEMT (transmitter empty) bit of the status register is
typically used to indicate when a program can disable the
transmission medium, as when deasserting the request-tosend line of a modem. A typical program will load the last
character for transmission and then monitor the TxEMT bit
of the statl,ls register.
The assertion of the TxEMT bitto indicate that transmission
is complete may occur a substantial time after the loading
of the last character. After the last character is loaded, one
character is in the transmitter holding register and one
character is in the serialization logic. Therefore, it will be
two character times before the transmission process is
completed. Waiting for the TxRDY signal to assert before
monitoring the TxEMT status shortens this by one character time because the TxRDY status bit indicates that there
are no characters in the transmitter holding register. The
times involved are calculated by taking the reciprocal of the
baud rate being used, multiplying by the number of bits per
character (a starter bit-5,6,7, or 8 data bits; plus parity bit
if enabled; and 1,1.5, or 2 stop bits), and multiplying by either
two characters or one, depending on when TxEMT monitoring begins.

TEST
POINT

V DD

V DD
IkQ

FROM
"OUTPUT'

where it stopped, thus providing receivers with equal priority. If the scanner was stopped by a transmitter condition,
the scanner restarts from position 0 (line O's receiver), thus
giving receivers priority over transmitters.

I kQ

........

FROM
OUTPUT

~

ICC

Sl

~

~

IkQ

~

;~

'i

S2

.,..

Sl CLOSED: PULL UP
S2 CLOSED: PULL DOWN
Sl ANDS2CLOSED: DIVIDER
LOAD A - STANDARD OUTPUTS

LOAD B - THREE-STATE OUTPUTS

FIGURE 9 - COM78C808 OUTPUT LOAD CIRCUITS
145

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range .................................................................................. O°C to + 70°C
Storage Temperature Range .......................'.......................................................... - 55° to + 125°C
Lead Temperature (soldering, 10 sec.) ........................................................................ ; ....... + 300°C
Positive Voltage on any 1/0 Pin, with respect to ground .............................................................. Vee + 0.3
Negative Voltage on any 1/0 Pin, with respect to ground ................................................................. - 0.3V
Maximum Vcc ........................................................................................................... + 7V
·Stresses above those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power suppHes, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. For example, the bench
power supply programmed to deliver + 5 volts may have large voltage transients when the AC power is switched on and off. If this
possibility exists it is suggested that a clamp circuit be used.

TABLE 9 - COM78C808
DC ELECTRICAL CHARACTERISTICS T. = 0°Ct070OC, Voo = +5V ±5%
Symbol

Parameter

V..
V,L
VOH

High-level input voltage
Low-level input voltage
High-level output voltage

Va..

Low-level output voltage

I'H

Input current at maximum
input voltage
Input current at miminum
input voltage
Short-circuit outpu1
current for DL <7:0> all
remainin9..Q!!!puts except
IRQandRDY
Three-state output
current
Three-state outpu1
current
Supply current

I'L
los'

1='
1000'
100

en,
CI03

Test Condition

Voo=Min.
10H = 3.5 mA for DL <7:0>
10H = 2.0 mA for all
remaining output except IRQ
andRDY
Voo=Min.
101. = 5.5 mA for DL<7:0>
10<. = 3.5 mA for all remaining
outputs
Voo=Max.
V, = Voo(Max.)
Voo=Max.
V, = O.OV
Voo=Max.

VOD=Max.
Vo =O.4V
Voo=Max.
Vo=2.4V
VDD=Max.
T.=oo

Input capacitance
Input/output capacitance

Requirements
Min.
Max.
2.0
0.8
2.4

0.4

Units
V
V
V

V

10

JLA

-10

JLA

-50

-180

mA

-30

-110
10

mA

10

!LA

25

mA

4
5

pF
pF

JLA

'No more than one ouput should be short circuited at a time, and the duration of the short should not exceed 1 second.
'All three-state output drivers are wired in an I/O configuration. The parameters include the driver and input receiver leakage currents.
'The parameters include the capacitive loads of the output driver and the input receiver.

TIMING PARAMETERS
11 shows the signal timing for a write cycle to transfer inforFigure 10 shows the signal timing for a read cycle to transfer mation from the processor to the Octal UART. Table 11 lists
information from the Octal UART to the processor. Figure the timing parameters for the read and write cycles.

146

I+-- tDPWlR ____

AOO < 5:0

.1'

1\

DS1/DS2

~I.--.

tDPWH

-----'L

X

]X

VALID ADDRESS
tASU

~tAHO

t wsu

i="t

tcsu

--l. t- tCHO

1\

WHO

~

I---\I

1------1-

tROl

.... tROH

XI

OL<7:0>

VALID DATA OUT

~DZL, 'OOZH
4-

IX.

'1'OF-I

tOO......j

J

tOOlZ, tOOHZ

1--"0::1
FIGURE 10 - COM78C808 BUS READ CYCLE TIMING

r

OS1/0S2

I--- 'DPWLW--<>
XI

ADD<5:0>

Jl<.

VALID ADDRESS

1----WR

tOPWH

f- tASU

\

--I
1-------.

/
f-twsu

f- 'csu

-

tWHO

H

DL<. 7.0

-'CHO

.tRDH~

\.
~

A

H - tAHO

'RoLI_ f-

>

VALID DATA IN
I+-'osu----ll--'OHO·,-I

IRQ

_,,!-l
FIGURE 11 - COM78C808 BUS WRITE CYCLE TIMING
147

TABLE 10 - COM78C808 BUS READ AND WRITE TIMING PARAMETERS
Symbol

Definition

tAHO

Hold time~ valid AOO <5:0> to a valid high level of
OSI and OS2.

10

tASU

Setup tim.!LQf.a valid AOO <5:0> to the falling edge of
OSI and OS2.

30

IeHO

Hold time~ valid low level of CS to a valid high level of
OSI and OS2.

10

leou

Setup tim.!LQf.a valid low level of CS to the falling edge of
OSI and OS2.

30

too

Propagation d~ of a valid low level on OS1 and OS2 (if
CS is low and WR is high) to valid high or low data on OL
<7:0>.

165

tODLZ2
tOOHZ

Requirements (ns)
Min.
Max.

C L=150 pF

PrQQl!gation delaY.Q! a valid high level on OSI and OS2
(if CS is low and WR is high) to OL <7:0> output drivers
disabled.
tooLZ
tooHZ

tomz
tOOHZ
tODLZ
tOOHZ

tooZL

50
50
60
60
65
65

C L=50pF
C L=50pF
C L= 100pF
C L= 100pF
C L= 150pF
C L= 150pF

165
165

C L = 150pF
C L= 150pF

Propagation d~ of a valid low level on OS1 and OS2 (if
CS is low and WR is high) to OL <7:0> output driver
enabled.
tOOZL
tOOZH

0
0

to,

Hold time provided during a read cycle by Octal UART of
valid high or low data on OL <7:0> after the rising edge
of OSI and OS2.

t OHO

Hold time of a valid OL <7:0> to a valid high level of
OSI or OS2.

t OPWH

Pulse width high of OS! and OS2.

450

Pulse width low of OSI and OS2 when WR is high (read
operation). Refer to timing parameter tOPWLW also.

180

10,000

t oPWlW

Pulse width low of OSI and OS2 when WR is low (write
operation). Refer to timing parameter tOPWLR also.

130

10,000

tosu

Setup tim.!LQf.a valid OL <7:0> to the rising edge of
OSI and OS2.

tOPWLA

'tl03

tROH 4
tADL

Load
Circuit'

0
30

50

Propagation delay of a valid low level on OSI and OS2 (if
CS is low) to a high level on IRQ.

635

C L=50pF

Propagation ~ of a valid high level of CS to a valid
high level on ROY.

210

C L=50pF

Propagation delay of a valid low level on CS to a valid
low level on ROY.

90

C L=50pF

tWHO

Hold time of a valid high or low level of WR to a valid high
level of OSI and OS2.

10

twsu

Setup time of a valid high or low level of WR to the falling
edge of OSI or OS2.

30

'Refer to Figure 9 for the load circuits used with these measurements.
'The toOLZ and tOOHZ parameters are measured with CL= 150 pF. The values of tOOLZ and tOOHZ for CL= 50pF and CL= 100 pF have been derived for
user convenience.
'Total rise time depends on internal delay plus the pullup delay introduced by the external resistor being used. The t,o parameter can be calculated
by the following: t,o = 500 + RCL where R = value of the resistor that connects to capacitor CL in load A, Figure 9.
'Total rise time depends on internal delay plus the pullup delay introduced by the external resistor being used. The tROH parameter can be calculated
by the following: tROH = 75 + RCL where R = value of the resistor that connects to capacitor CLin load A, Figure 9.

Figure 12 shows the signal timing forthe clock input, inter- timing, and the transmit data outputtiming. Table 11 lists the
rupt timing, effect of the RESET input on data strobe, data timing parameters for Figure 12.
set carrier detect (OCO) and data set ready (OSR) input
148

elK

CLOCK

,.0"",,,,,,",

IRQ

~

~

-----tt-t-sU_"""""I~I----~/'l_-tl-HO---_I-t---INTERRUPT

RESeT

1

.

1..

DS1/DS2

.~

tRES

tORSU

.j

.~

\'--_tDRHO

EFFECT OF RESET ON DATA STROBE

DCD/DSA

< 7:0 '> _ _ _ _

..J~'1-~.:::::V:A-=-Ll-=-D.:.~D.:.;e:;;,.:::..;s-""R~D:::A-T-A==::~.~I..___________
OCO/OSR INPUT

TxD< 7:0>

"!.-----tTXSK_L tTXSK--J------...IrTRANSMIT DATA OUTPUT

FIGURE 12-COM'78C808 MISCELLANEOUS SIGNAL TIMING
TABLE 11-MISCELLANEOUS WRITE TIMING PARAMETERS
Symbol

Definition

Requirements (ns)
Min.

tep

Period of ClK.

203.45 (4.9152 MHz)

IcPWH

Pulse width high of ClK.

95

tCPWL

Pulse width low of ClK.

95

tDAHO

Hold time of a valid high level of DS1 and DS2 to a valid
high level of RESET.

t OASU

Setup time of a valid high level of DS1 and DS2 to the
rising edge of RESET.

Load Circuit'

1,000
900

tospw

Pulse width high or low of DCD <7:0> and DSR <7:0>.

tlHO

Hold time provided by Octal UART from a valid IRQlN
<2:0> and IRQTxRx to a valid high level of IRQ.

100

C L =50pF

tlSU

Setup time provided by Octal UART from a valid IRQlN
<2:0> and IRQTxRx to a valid low level of IRQ.

100

CL =50pF

tRES

hXSK

Pulse width low of RESET.

1,000

1,000

Pulse width high or low provided by Octal UART on the
TxD <7:0> lines. At each baud rate, the actual pulse
This timing parameter
widths provided vary by t
should be used to determine cumulative reception/transmission errors.

TXSK.

'Refer to Figure 9 for the load circuits used with these measurements.

149

250

C L =50pF

Figure 13 shows the input and output voltage waveforms
for the propagation delay and setup and hold measure-

ments. Figure 14 shows the waveforms for the three-state
outputs measurement.

SET·UP AND HOLD

PROPAGATION DELAY

FIGURE 13 - COM78C808 PROPAGATION DELAY
AND SETUP AND HOLD VOLTAGE WAVEFORMS

V,N 12.4 V)

2.0V
OUTPUT CONTROL

O.BV

VILI~Z::OT~~:~I

VOH 14 5 V)

OUTPUT(SEENOTElj15V
VOL+05
VOUT lAS MEASURED)

r

INOTE 3C)

tlZ

---j-' ---------- ------- - - - - - -

tZH INOTE 3B)
tHZ

-

--~ VOL+O.5V

--iI

VOUT lAS MEASURED)
VOH -0.5 V
1.5 V
OUTPUT VOL (NOTE 2)
ID.DV)

THREE-STATE OUTPUTS
NOTES:
1. INTERNAL CONDITIONS ARE SUCH THAT THE OUTPUT IS LOW EXCEPT WHEN DISABLED BY
THE OUTPUT CONTROL.
2.

INTERNAL CONDITIONS ARE SUCH THAT THE OUTPUT IS HIGH EXCEPT WHEN DISABLED BY
THE OUTPUT CONTROL.

3.

REFER TO FIGURE 9. A = 51 CLOSED, B = 52 CLOSED. C = S1 AND 52 CLOSED.

FIGURE 14 - COM78C808 THREE-STATE OUTPUT VOLTAGE WAVEFORMS
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The Information has been
carefully checked and is believed to be entirely reliable. However. no responsibility IS assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under
the patent rights of SMC or others. SMC reserves the right to make changes at any time in order to improve design and
supply the best product possible.

150

COM 8004
jLPCFAMILY

Oual32 Bit CRC SOLC Generator/Checker
CRC-32
FEATURES

PIN CONFIGURATION

o SDlC 32 bit CRC

o COM 5025 USYNRT Companion
o Data Rate-2MHz typical
o

o

o

MRA

"-.J

19 EFLGRB

CLKINA 2

All Inputs and Outputs are TTL Compatible
Single +5 Volt Supply
COPlAMOS® N-Channel MOS Technology

CLKOUTA 3

18 EFLGB

SERINA 4

17 MODEB

SEROUTA 5

16 ENAB

ENAA 6

GENERAL DESCRIPTION
SMC's COM 8004 is a dual 32-bit CRC Generator/
Checker for use with SDle protocols. It is a
companion device to SMC's COM 5025 USYNRT.
It operates at bit rates from DC to 2.0 MHz from a
single +5v supply and is housed in a 20 lead x 0.3
inch DIP. All inputs and outputs are TTL compatible
with full noise immunity.
The COM 8004 is comprised of two independent
halves, and each half may be operated in the check
or generate mode. The polynominal used in
computations is:
X32 + X26 + X23 + X22 + X'6 + X'2 + X" + X'D + XB + X7 + X5 +
X' + X2 + X + 1.
The CRC register is initialized to all ones and the
result is inverted before being appended to the
message. The expected remainder is:
X3' + X3D+ X26 + X25 + X2. + X'B+ X'5+ X14+ X'2+ X" + X'D+
XB + X6 + X5 + X' + X3 + X + 1.
Each half has a nine-bit serial data shift register.
Data moves on the positive edge of the clock, and all
clocked inputs are designed for zero-hold-time
(e.g. 7474). A "clock out" pin provides gated clocks
to the accompanying USYNRT (COM 5025).
In the generate mode, computation is initiated upon
detection of a flag character in the serial bit stream.
CRC computation proceeds upon the serial data
until a second flag is detected. ClK OUT to the
SDlCtransmitter is then halted, and the32-bitCRC
is passed out; ClK OUT is then resumed, and the
flag character is passed out. Nonsignificant zeros
are automatically stripped and stuffed, and shared
flags are supported. If the data between flags is less
than two full bytes, the CRC is discarded and the
serial data stream remains unaltered.
In the check mode, computation is similarly
initiated upon detection of a flag. Detection of a
second flag causes the conditional setting of the
error flag. A separate reset pin is provided for the
error flag. No error is flagged on messages of less
than two full bytes between flags. Detection of an
abort character (7 consecutive ones) in either mode
causes computation to be reset and a search for an
opening flag resumed.

20 Vee

15SEROUTB
14SERINB

MODEA 7

13 CLKOUTB

EFLGA 8
EFLGRA 9

12 CLKINB

GND10

11 MRB

PACKAGE: 20 pin D.I.P.

BLOCK DIAGRAM
FOR ONE-HALF OF THE COM 8004
32 BITCRC

SEA OUT

8-BIT SIR
FLAG/ABORT DET

SEA IN

MR
eLKIN
ENA
MODE
EFLGR

CONTROL LOGIC

elK OUT

ERG

TYPICAL SYSTEM
~

TSO

SERIN •

~SEROUT

~~I...:.TC:::.P_ _.=:CL::.:K",O::.:UTc...,~CLKIN
TX

SEA IN

elKIN

SER IN

elK IN

151

For additional information, consult your 1986 catalog or contact our product marketing department at (516) 273-3100.

STANDARD MICROSYSTEMS

ATV,\IU
CORPOR1"\11VI1I

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
applications: consequently complete information sufficient for construction purposes is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
"",,,,,,,, " _ " ",,, assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
·""m ,,00, ow, "0 m",~ semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the best product possible.

152

COM 8017
COM 8502

Universal Asynchronous Receiver/Transmitter
UART
Pin Configuration
FEATURES

Vee

o Single +5V Power Supply
o Direct TTL Compatibility- no interfacing circuits

NC
Gnd

R5E
ROB
R07
R06
R05
R04
R03
R02
ROl
RPE
RFE
ROR
SWE
RCP
ROAR
ROA
RSI

required

o Full or Half Duplex Operation-can receive and
transmit simultaneously at different baud rates

o Fully Double Buffered-eliminates need for precise
external timing

o Start Bit Verification - decreases error rate
o Fully Programmable-data word length; parity mode;
number of stop bits: one, one and one-half, or two

o High Speed Operation-40K baud, 200ns strobes
o Master Reset- Resets all status outputs
o Tri-State Outputs- bus structure oriented
o Low Power- minimum power requirements

TCP
POE
NOBl
NOB2
NSB
NPB
CS
TOB
TD7
T06
T05
T04
T03
T02
TOl
TSO
TEOC

'fi5S
TBMT
MR

PACKAGE: 40-Pin D.I.P.

Functional Block Diagram

o Input Protected-eliminates handling problems

o Ceramic or Plastic Dip Package-easy board insertion
o Compatible with COM 2017, COM 2502

o Compatible with COM 8116, COM 8126, COM 8136,

TSO

COM 8146, COM 8046 Baud Rate Generators
TEOC
SWE

GENERAL DESCRIPTION

The Universal Asynchronous Receiver/Transmitter is
an MOS/LSI monolithic circuit that performs all the
receiving and transmitting functions associated with
asynchronous data communications. This circuit is
fabricated using SMC's patented COPLAMOS® technology and employs depletion mode loads, allowing
operation from a single +5V supply. The duplex mode,
baud rate, data word length, parity mode, and number
of stop bits are independently programmable through
the use of external controls. There may be 5,6,7 or 8
data bits, odd/even or no parity, and 1, or 2 stop bits. In
addition the COM 8017 will provide 1.5 stop bits when
programmed for 5 dllta bits and 2 stop bits. The UART
can operate in either the full or half duplex mode. These
programmable features provide the user with the ability
to interface with all asynchronous peripherals.
153

NPB
NSB
NOB2
NOBl
POE

35
36
37
3B
39

CONTROL
REGISTER

TBMT
RPE
RFE
ROR
ROA

STATUS
WORO
BUFFER
REGISTER

ROAR

21

MR

Vee
NC
Gnd

DESCRIPTION OF OPERATION- TRANSMITTER
commences. TSO goes low (the start bit), TEOC
goes low, the TBMT goes high indicating that the
data in the data bits buffer register has been loaded
into the transmitter shift register and that the data
bits buffer register is available to be loaded with
new data.
If new data is loaded into the data bits bufferregister
at this time, TBMT goes low and remains in this state
until the present transmission is completed. One
full character time is available for loading the next
character with no loss in speed oftransmission. This
is an advantage of double buffering.
Data transmission proceeds in an orderly manner:
start bit, data bits, parity bit (if selected), and the
stop bit(s). When the last stop bit has been on the
line for one bit time TEOC goes high. If TBMT is
low, transmission begins immediately. If TBMT is
high the transmitter is completely at rest and, if
desired, new control bits may be loaded prior to the
next data transmission.

At start-up the power is turned on, a clock whose
frequency is 16 times the desired baud rate is
applied and master reset is pulsed. Under these
conditions TBMT, TEOC, and TSO are all at a high
level (the line is marking).
When TBMT and TEOC are high, the control bits
may be set. After this has been done the data bits
may be set. Normally, the control bits are strobed
into the transmitter prior to the data bits. However,
as long as minimum pulse width specifications
are not violated, TDS and CS may occur simultaneously. Once the date strobe (TDS) has been
pulsed the TBMT signal goes low, indicating that
the data bits buffer register is full and unavailable to
receive new data.
If the transmitter shift register is transmitting previously loaded data the TBMT signal remains low.
If the transmitter shift register is empty, or when it is
through transmitting the previous character, the
data in the buffer register is loaded immediately into
the transmitter shift register and data transmission

TRANSMITTER BLOCK DIAGRAM

ODD/EVEN
PARITY SELECT

CONTROL
STROBE

.......- -

If-~

DATA STROBE

TRANSMITTER
BUFFER
EMPTY

16xT
CLOCK

SERIAL
OUTPUT

END OF
CHARACTER

DESCRIPTION OF OPERATION-RECEIVER
ing condition priortoa 1/2 bit time, the start bit verification process begins again. A mark to space
transition must occur in order to initiate start bit
verification. Once a start bit has been verified, data
reception proceeds in an orderly manner: start bit
verified and received, data bits received, parity bit
received (if selected) and the stop bit(s) received.
If the transmitted parity bit does not agree with the
received parity bit, the parity error flip-flop of the

At start-up the power is turned on, a clock whose
frequency is 16 times the desired baud rate is applied
and master reset is pulsed. Thedataavailable(RDA)
signal is now low. There is one set of control bits for
both the receiver and transmitter.
Data reception begins when the serial input line
transitions from mark (high) to space (low). If the
RSlline remains spacing for a 112 bittime, a genuine
start bit is verified. Should the line return to a mark154

status word buffer register is set high, indicating a
parity error. However, if the no parity mode is selected, the parity error flip-flop is unconditionally
held low, inhibiting a parity error indication. If a
stop bit is not received, due to an improperlyframed
character, the framing error flip-flop is set high,
indicating a framing error.
Once a full character has been received internal
logic looks at the data available (RDA) signal. If, at
this instant, the RDA signal is high the receiver
assumes that the previously received character has

not been read out and the over-run flip-flop is set
high. The only way the receiver is aware that data
has been read out is by having the data available
reset low.
At this time the RDA output goes high indicating
that all outputs are available to be examined. The
receiver shift register is now available to begin receiving the next character. Due to the double buffered receiver, a full character time is available to
remove the received character.

RECEIVER BLOCK DIAGRAM
FRAMING
ERROR
ADB R07 AD6 ADS RD4 AD3 AD2 AD1

BITS FROM
HOLDING _____________
CONTROL
AEGISTER

TRANSMITTER
BUFFER EMPTY

J:::::::;:::::~==~~~==========~~====l

SERIAL
INPUT

16 x R
CLOCK

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

NAME

FUNCTION

Vce

Power Supply

+5 volt Supply

2

NC

No Connection

No Connection

3

GND

Ground

Ground

4

ROE

Received Data
Enable

A low-level input enables the outputs (RD8-RD1) of the
receiver buffer register.

5-12

RD8-RD1

Receiver Data
Outputs

These are the 8 tri-state data outputs enabled by ROE.
Unused data output lines, as selected by NDB1 and NDB2,
have a low-level output, and received characters are right
justified, i.e. the LSB always appears on the RD1 output.

13

RPE

Receiver Parity
Error

This tri-state output (enabled by SWE) is at a high-level if
the received character parity bit does not agree with the
selected parity.

14

RFE

Receiver Framing
Error

This tri-state output (enabled by SWE) is at a high-level if
the received character has no valid stop bit.
155

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

NAME

FUNCTION

15

ROR

Receiver Over
Run

This tri-state output (enabled by SWE) is at a high-level if
the previously received character is not read (RDA output
not reset) before the present character is transferred into
the receiver buffer register.

16

SWE

Status Word
Enable

A low-level input enables the outputs (RPE, RFE, ROR,
RDA, and TBMT) of the status word buffer register.

17

RCP

Receiver Clock

This input is a clock whose frequency is 16 times (16X) the
desired receiver baud rate.

18

ROAR

Receiver Data
Available Reset

A low-level input resets the RDA output to a low-level.

19

RDA

Receiver Data
Available

This tri-state output (enabled by SWE) is at a high-level
when an entire character has been received and transferred
into the receiver buffer register.

20

RSI

Receiver Serial
Input

This input accepts the serial bit input stream. A high-level
(mark) to low-level (space) transition is required to initiate
data reception.

21

MR

Master Reset

This input should be pulsed to a high-level after power
turn-on. This sets TSO, TEOC, and TBMT to a high-level
and resets RDA, RPE, RFE and ROR to a low-level.

22

TBMT

Transmitter
Buffer Empty

This tri-state output (enabled by SWE) is at a high-level
when the transmitter buffer register may be loaded with
new data.

23

TDS

Transmitter
Data Strobe

A low-level input strobe enters the data bits into the
transmitter buffer register.

24

TEOC

Transmitter End
of Character

This output appears as a high-level each timea full character
is transmitted. It remains at this level until the start of
transmission of the next character or for one-half of a TCP
period in the case of continuous transmission.

25

TSO

Transmitter
Serial Output

This output serially provides the entire transmitted
character. TSO remains at a high-level when no data is
being transmitted.

26-33

TD1-TD8

Transmitter
Data Inputs

There are 8 data input lines (strobed by TDS) available.
Unused data input lines, as selected by NDB1 and NDB2,
may be in either logic state. The LSB should always be
placed on TD1.

34

CS

Control Strobe

A high-level input enters the control bits (NDB1, NDB2,
NSB, POE and NPB) into the control bits holding register.
This line may be strobed or hard wired to a high-level.

35

NPB

No Parity Bit

A high-level input eliminates the parity bit from being
transmitted; the stop bit(s) immediately follow the last data
bit. In addition, the receiver requires the stop bit(s) to follow
immediately after the last data bit. Also, the RPE output is
forced to a low-level. See pin 39, POE.
156

DESCRIPTION OF PIN FUNCTION
PIN NO.

SYMBOL

NAME

FUNCTION

36

NSB

Number of
Stop Bits

This input selects the nl!mber of stop bits. A low-level input
selects 1 stop bit; a high-level input selects 2 stop bits.
Selection of 2 stop bits when programming a 5 data bit word
generates 1.5 stop bits from the COM 8017 or COM 8017/H.

37-38

NDB2,
NDB1

Number of Data
Bits/Character

These 2 inputs are internally decoded to select either 5,6,7,
or 8 data bits/character as per the following truth table:
data bits/character
NDB2 NDB1
L
L
5
H
6
L
H
L
7
H
8
H

39

POE

Odd/Even Parity
Select

The logic level on this input, in conjunction with the NPB
input, determines the parity mode for both the receiver and
transmitter, as per the following truth table:
MODE
NPB POE
L
L
odd parity
L
H
even parity
X
H
no parity
X = don't care

Transmitter
Clock

This input is a clock whose frequency is 16 times (16X) the
desired transmitter baud rate.

40

TCP

TRANSMITTER TIMING-8 BIT, PARITY, 2 STOP BITS
TD5
TBMT

I
~

__________

~r---

TRANSMITTER START-UP

JL.JULI
I
I

TCP

~

1/16

Bit

time

f-

Upon data transmission initiation, or when not transmitting at 100% line utilization, thestsrt bit will be placed
on the TSO line at the high to low transition of the TCP clock following the trailing edge of TDS.

RECEIVER TIMING-8 BIT, PARITY, 2 STOP BITS
ASI

~~;:-.i .. ·.. ID~T~?~A~~SToP;sToP*TAAT

CENTEA BIT
SAMPLE

________L-__~______~L-__~__~~~~~~.___

~

ADA"

I

~~~~-

--------------------11

"The RDA line was previously not reset (RDA = high-level).
··The ADA line was previously reset (ROR low-level).

=

START BIT DETECT/VERIFY
ACP
ASI

~~B.ginv.rifY

If the ASlline remains spacing for a 1/2 bit time, a genuine start bit is verified. Should the line return to a
marking condition prior to a 112 bit time, the start bit verification process begins again.

157

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range •.•....•..............................•.•.....•...... 0° C to + 70° C
Storage Temperature Range .•.................................................. -55° C to +150° C
Lead Temperature (soldering, 10 sec.) ...........................................••.....•.. +325° C
Positive Voltage on any Pin, with respect to ground •..................................•....... +8.0V
Negative Voltage on any Pin. with respect to ground .......................................... -0.3V
Stresses above those listed may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or at any other condition above
those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system powersupplies, it is important
that the Absolute Maximum Ratings not be exceeded or device failure can result. Some
power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power is
switched on and off. In addition, voltage transients on the AC power line may appear on the
DC output. If this possibility exists it is suggested that at clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA == 0° C to 70° C, Vec == +5V ±5%, unless otherwise noted)
Parameter
D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, Vil
High-level, VIH
OUTPUT VOLTAGE LEVELS
Low-level, VOL
High-level, VOH
INPUT CURRENT
Low-level, III
OUTPUT CURRENT
Leakage, lLo
Short circuit, los""
INPUT CAPACITANCE
All inputs, CIN
OUTPUT CAPACITANCE
All outputs, COUT
POWER SUPPLY CURRENT
Icc
A.C. CHARACTERISTICS
CLOCK FREQUENCY
COM8502, COM 8017
PULSE WIDTH
Clock
Master reset
Control strobe
Transmitter data strobe
Receiver data available reset
INPUT SET-UP TIME
Data bits
Control bits
INPUT HOLD TIME
Data bits
Control bits
STROBE TO OUTPUT DELAY
Receive data enable
Status word enable
OUTPUT DISABLE DELAY

Min.

Typ.

Max.

Unit

0.8
Vce

V
V

0.4

V
V

300

J,lA

VIN == GND

±10
30

J,lA
mA

SWE == ROE == VIH, 0 :5 VouT:5 +5V
VOUT ==OV

5

10

pf

10

20

pf

25

mA

0
2.0

2.4

Comments

IOl == 1.6mA
IOH == -100J,lA

SWE == ROE == VIH
All outputs == VOH, All inputs == Vee
TA == +25°C

DC

640

KHz RCP, TCP

0.7
500
200
200
200

J,lS
ns
ns
ns
ns

iDS
ROAR

~O
~O

ns
ns

T01-T08
NPB, NSB, NOB2, NOB1, POE

~O
~O

ns
ns

T01-T08
NPB, NSB, NOB2, NOB1, POE
Load == 20pf +1 TTL input
ROE: TPD1, TPDO
SWE: TPD1, TpDO
ROE,SWE

350
350
350

ns
ns
ns

RCP, TCP
MR
CS

""Not.more than one output should be shorted at a lime.
NOTES: 1. If the transmitter is inactive (TEOC and TBMT are at a high-level) the start bit will appear on the TSO line within
one clock period (TCP) after the trailing edge of TOS.
2. The start bit (mark to space transition) will always be detected within one clock period of RCP, guaranteeing
a maximum start bit slippage of 1/16th of a bit time.
3. The tri-state output has 3 states: 1) low impedance to vcc~b~w impedance to GNO 3) high impedance OFF eo
10M ohms The "OFF" state is controlled by the SWE and
inputs.
158

DATA/CONTROL TIMING DIAGRAM

DATA INPUTS
tr = tf = 20 ns
TSET-UP2;:O
THOLD 2;:0

~:~_ .J=

CS

CONTROL INPUTS

T....

~1,

;:3-L----------1---£ T~,"

"Input information (Data/Control) need onl~_~~..valid during
the last Tpw, min time of the input strobes (TDS, CS).

OUTPUT TIMING DIAGRAM

Outputs Disabled
OUTPUTS
(RD1-RD8, RDA,
RPE, ROR, RFE, TBMT)

VOH
VOL
TPD1, TPDO

NOTE: Waveform drawings not to scale for clarity.

ROAR
200ns
VIL

TDS

TMBT
RDA

VIH

----------

300ns

159

VOL

FLOW CHART-TRANSMITTER

FLOW CHART-RECEIVER

1 TURN POWER ON
2 PULSE EXTERNAL RESET
3 SELECT BAUD RATE-16 x eLK

SET CONTROL BITS-PULSE CS

YES

"-_=--<,.

HAS
A START
BIT BEEN VERIFIED
8-16xCLK

HAS THE

" - _....N"O'-< 3~lci'A~~E~fsu~E8E~
REC;IVED

YES

YES

" -_ _ _ _ _- ' YES

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

160

COM81C17
PRELIMINARY

Twenty Pin UART (TPUART)
FEATURES

PIN CONFIGURATION

o Single Chip UART With Baud Rate Generator
o Asynchronous Operation

-16 Selectable Baud Rate Clock Frequencies
(Internal)
-External16x Clock (100 KBaud)
-Character Length: 7 or 8 Bits
-1 or 2 Stop Bit Selection

16~ ~ ~I~

o Small 20 Pin DIP (300 mil) or PLCC
o Full or Half Duplex Operation
o Double Buffering of Data
o Programmable Interrupt Generation
o Programmable ModemlTerminal Signals
o Odd or Even Parity Generate and Detect
o Parity, Overrun and Framing Error Detection
o TTL Compatible Inputs and Outputs
o High Speed Host Bus Operation

18 17161514
19
13
12

cp'
Vee

Do
D,
C§

11
10

9

CLOCK
D,
D,
GND
D,

4 5 6 7 8

I&! 0' 0' 0l~

Vee

Do
D,
C§
RO
D,
D,
D,
WR
D,
GND

CP,
CP,
TX
RX
RS
INT
CLOCK
D,
D,
Package 20-pin DIP

Package: 20-pin PLCC

(with no wait state)

o Low Power CMOS
o Single + 5V Power Supply
GENERAL DESCRIPTION
The COM81C17 TPUART is an asynchronous only receiver I transmitter with a built in programmable baud rate generator housed in a twenty pin package. The TPUART
receives serial data streams and converts them into parallel data characters for the processor. While receiving serial
data, the TPUARTwili also accept data characters from the
processor in parallel format and convert them into serial format along with start, stop and optional parity bits. The

DATA
BUS
ADDRESS
BUS

TPUART will signal the processor via interrupt when it has·
completely transmitted or received a character and requires
service. Complete status information is available to the processor through the status register. The TPUART features
two general purpose control pins that can be individually
programmed to perform as terminal or modem control
handshake signals.

~

A

,

CP1 '"

DO-D7

r
DECODE

CP2 ::::

--l
--l

CS

r

COM81C17

lAO

RS

WRITE
READ

WR
RD

INTERRUPT
REQUEST

INT

...

TWENTY
PIN
UART

~

TX

::D

en

N

w
I\)

0
RX

5.0688 MHZ
OSCILLATOR
OR
TTL CLOCK

i
FIG 1. TYPICAL TPUART INTERFACE
161

IA
DO-D7

I'

~

~

DATA
BUS
V TRANS.

~

V

~

TRANSMIT
SHIFT REGISTER

-

"r

CS

READ

RD

WRITE

WR
RS

DECODE

TRANSMIT
BUFFER

TX

TRANSMIT CONTROL
MODE
REGISTER

0

~

LOGIC

III

c
en

~

r

MASK
REGISTER
& LOGIC

VCC

-

CONTROL
REGISTER

I-I--

BAUD RATE
CLOCK
GENERATOR

tL----

v---

A.
~

GND

BAUD
RATE
SELECT
REGISTER

STATUS
REGISTER
RECEIVE CONTROL
RECEIVE
SHIFT REGISTER

J.--

v---

A

RX

RECEIVE
BUFFER

:~

it
FIG. 2. BLOCK DIAGRAM OF COM81C17

560 OHM

1800 OHM

220 OHM

7404

7404

L...--~.tV\r----I
220 OHM

1-----11 0

30pF

7404

I----J

5.0688 MHz

FIG.2A. 5.0688 MHz CRYSTAL OSCILLATOR CIRCUIT
162

7404

TABLE 1 - DESCRIPTION OF PIN FUNCTIONS
DIPPIN NO.

NAME

SYMBOL

DESCRIPTION

1,2,5-7
9,11-12

DATA BUS

0 0 -0,

An 8 bit bi-directional DATA BUS is used to interface the TPUART to the
processor Data Bus.

3

CHIP SELECT

CS

A low level on this input enables the TPUART for reading and writing to
the processor. When CS is high, the DATA BUS is in high impedance
and the WR and RD will have no effect on the chip.

4

READ DATA
STROBE

RD

A low pulse on this input (when CS is low) enables the TPUART to place
the data or the status information on the DATA BUS.

8

WRITE DATA
STROBE

WR

A low pulse on this input (when CS is low) enables the TPUART to
accept the data or control word from the DATA BUS into the TPUART.

10

GROUND

GND

Power Supply Return

13

CLOCK

ClK

14

INTERRUPT
REQUEST

INT

External TTL Clock Input (See Table 2)
An interrupt request is asserted by the TPUART when an enabled condition has occurred in the Status Register. This is an active low, open drain
output. This pin has an internal pullup register.

15

REGISTER
SELECT

RS

During processor to TPUART communications, this input is used to indicate which internal register will be selected for access by the processor.
When this input is low, data can be written to the TX Holding Buffer or
data can be read from the RX Holding Register. When this input is high
control words can be written to the Control Register or status information
can be read from the Status Register.

16

RECEIVER
DATA

RX

This input is the receiver serial data. A high to low transition is required to
initiate data reception.

17

TRANSMITTER
DATA

TX

This output is the transmitted serial data from the TPUART. When a
transmission is concluded, the TX line will always return to the mark
(High) state.

18

CONTROL
PIN1

CP1

This control pin is an input only pin. It can be programmed to perform the
functions of CTS or DSR/DCD.

19

CONTROL
PIN2

CP2

This control pin can be programmed to be either an input or an output.
When in input mode, this pin can perform the functions of DSR/DCD.
When in output mode this pin can perform the functions of DTR
orRTS.

20

POWER
SUPPLY

Vee

+ 5V Supply Voltage

FUNCTIONAL DESCRIPTION

words. This is following an internal reset. Following initialization, the TPUART is ready to communicate.

RESETTING THE TPUART

PROGRAMMABLE CONTROL PINS

The TPUART must be reset on power up. Since there is no
external pin allocated for hardware reset, this is accomplished by writing a One (H IGH) followed by writing a Zero
(LOW) to the Control Register bit 7. Following reset, the
TPUART enters an idle state in which it can neither transmit
nor receive data.

The TPUART provides two programmable control pins that
can be configured to perform as modem or terminal control
handshake signals. If no handshake signal is required, these
pins can be used as general purpose one bit Input or Output
ports.

The TPUART is initialized by writing three control words from
the processor. Only a single address is set aside for Mode,
Baud Rate Select, Interrupt Mask and TX Buffer Registers.
For this to be possible, logic internal to the chip directs information to its proper destination based on the sequence in

CP1 - is an input only pin that can be programmed to act
as the CTS (Clear To Send) handshake Signal, where it will
disable data transmission by the TPUART after the contents of the Transmit Shift Register is completely flushed
out. When programmed as 1 , CP1 will serve as a general
purpose 1 bit input port. The inverted state will be reflected
in Status Register bit 0 (when programmed as CTS or general purpose input bit).

which it is written.
Following internal reset, the first write to address zero (Le.
RS = 0) is interpreted as a Mode Control word. The second
write is interpreted as Interrupt Mask word. The third write
is interpreted as Baud Rate Select. The fourth and all subsequent writes are interpreted as writes to the TX Buffer
Register.
There is one way in which control logic may return to anticipating a Mode, Interrupt Mask, and Baud Rate Select

CP2 _ is an Input/Output pin. When configured as Output,
its state is directly controlled by the host processor via writes
to the Control Register. This will serve the purpose of modem
and terminal handshake signals as RTS (Request To Send),
and DTR (Data Terminal Ready). When configured as Input,
its inverted state is reflected in the Status Register bit 1 and
read by the processor. This will serve the purpose of handshake signals as DCD (Data Carrier Detect) and DSR (Data
Set Ready).

IN ITIALIZING THE TPUART

163

MODE REGISTER

THE ON CHIP BAUD RATE GENERATOR

BIT1

BIT2

o
o

o

The TPUART incorporates an on chip Baud Rate Generator that can be programmed to generate sixteen of the most
popular baud rates. The TPUART also allows the bypassing of the Baud Rate Generator by programming Mode
Register bit 3 to accept a 16X external clock. The Baud Rate
Generator will not assume any given baud rate upon power
up, therefore it must be programmed as desired. The following cha,rt is based on a 5.0688 MHz CLOCK frequency.

CP2 is RTS output
CP2 is GP output
CP2 is GP input
CP2 is GP input

1

X
X

1
1

TABLE 2 -16X CLOCK
Clock Frequency 5.0688 MHz

=

Baud Rate
Select Register

03

D.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0,

0,

Baud
Rate

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

50
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19.200
38.400

Theoretical
Frequency
16XCIock
0.8 KHz
1.76
2.152
2.4
4.8
9.6
19.2
28.8
32.0
38.4
57.6
76.8
115.2
153.6
307.2
614.4

REGISTER DESCRIPTIONS
TABLE 3 - COM81C17 MODE REGISTER
DESCRIPTION (BITS 0-7)
BIT
0

1

2

3

Actual
Frequency
16XCIock
0.8 KHz
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8
633.6

Percent
Error

-

-

0.016

-

-

0.253

-

3.125
3.125

Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
48/52
50/50
50/50

Divisor
6336
2880
2356
2112
1056
528
264
176
158
132
88
66
44
33
16
8

PARITY ENABLE-The Mode Register bit 4 determines whether parity generation and checking will be
enabled.
= PARITY DISABLE
1 = PARITY ENABLE
PARITY-The Mode Register bit 5 determines whether
odd or even parity will be generated and checked.
= EVEN PARITY
1 = ODD PARITY
# OF DATA BITS-The Mode Register bit 6 determines the number of data bit that will be presented in
each data character (i.e. 7 or 8).
1 = 8 BITS PER
= 7 BITS PER CHARACTER
CHARACTER
STOP BITS-The Mode Register bit 7 determines how
many stop bits will trail each data unit (i.e. 1 or 2).
0= 1 STOP BIT
1 = 2 STOP BITS
A data frame will consist of a start bit, 7 or 8 data bits,
an optional parity bit, and 1 or 2 stop bits.

4

o

5

DESCRIPTION
CP1-The Mode Register bit 0 determines whether the
CP1 pin will be configured to provide the function of
CTS or will serve as a general purpose 1 bit input port.
In either case, its state will be reflected in Status RegisterbitO.
0--7CP1 = CTS
1--7CP1 = GP INPUT
CP21/0-The Mode Register bit 1 determines whether
the CP2 pin will be configured as a general purpose 1
bit output port or will serve as a general purpose 1 bit
input port. When used as an input, its state is reflected
in the Status Register bit 1. When used as an output,
its state is controlled by the processor via the Control
Register bit 1.
HCP2 = INPUT
0--7CP2 = OUTPUT
CP2-The mode register bit 2 determines whether the
CP2 pin will be configured to provide the function of
RTS or will serve as a general purpose 1 bit output
port.
HCP2 = GP OUTPUT
0--7CP2 = RTS
CLOCK SELECT-The Mode Register bit 3 determines whether the internal Baud Rate Gener~tor will
supply the TX and RX clocks or the clock on the clock
pin will be used as a 16X clock. The Baud Rate Select
Register contents will be bypassed when an external
16X clock is used.
= INTERNAL CLOCK 1 = EXTERNAL CLOCK
(16X)

o

6

o

7

TABLE 4 - COM81C17 STATUS REGISTERS
DESCRIPTION (BITS 0-7)
BIT
0
1

o

164

DESCRIPTION
CP1-This reflects the inverted state of the control
pin CP1.
CP2-This is active only when the CP2 pin is programmed to be an input. It is set by its corresponding
input pin and reflects the inverted state of the control pin CP2. When the CP2 pin is programmed as an
. output, this bit is forced to a zero.

2

3

TABLE 5 - COM81C17 CONTROL REGISTER
DESCRIPTION (BITS 0-7)

TX SHIFT REGISTER EMPTY-This signals the processor that the Transmit Shift Register is empty. A
typical program will usually load the last character
of a transmission and then monitor the TX SHIFT
REGISTER EMPTY bitto determine when it is a safe
time for disabling transmission. This bit is set when the
Transmitter Shift Register has completed transmission of a character, and no new character has been
loaded in the Transmit Buffer Register. This bit is also
set by asserting internal reset. This bit is cleared by:
a. loading the TX Buffer Register

BIT

5

3
4
5

S

OVERRUN ERROR-This is set whenever a byte
stored in the Receive Character Buffer is overwritten
with a new byte from the Receive Shift Register
before being transferred to the processor. This bit is
cleared by:
a. setting Reset Errors in the Control Register
b. asserting internal reset

a. a character has been loaded from the Transmit
Buffer Register to the Transmit Shift Register
b. asserting the TRANSMITTER RESET bit in the
Control Register
c. asserting internal reset
This bit is cleared by:
a. writing to the Transmit Buffer Register
This bit is initially set when the transmitter logic is
enabled by setting the TX Enable bit in the Control
Register (also TX Buffer is empty because of reset).

7

Data can be overwritten if a consecutive write is performed while TX Buffer Empty is zero.
RX BUFFER FULL-This signals the processor that a
completed character is present in the Receive Buffer
Register for transfer to the processor. This bit is set
when a character has been loaded from the receive
deserialization logic to the Receive Buffer Register.
This bit is cleared by:
a. reading the Receive Buffer Register
b. asserting the RECEIVER RESET bit in the
Control Register
c. assertinQ internal reset

INTERRUPT MASK REGISTER DESCRIPTION
This is an eight bit write only register which is loaded by the
processor. These bits are used to enable interrupts from the
corresponding bits in the Status Register. This register is
reset with internal reset.
REGISTER DECODE & TRUTH TABLE
The TPUART provides unique decode capability to three of
the seven internal processor accessible register. These are
the RX Buffer Register (read only), the Status Register (read
only) and the Control Register (write only). The other four
registers (write only) are decoded in a sequential manner
following reset.
DECODE TRUTH TABLE
RS

o

o
1
1

X

AD WR
0
1

o

0
1

o

0
0
0
1

1

X

cs
0

1

X

READ RX BUFFER REGISTER
WRITE TO TX BUFFER REGISTER
READ STATUS REGISTER
WRITE TO CONTROL REGISTER
DATA BUS IN TRI STATE

The first write to address zero (RS = 0) will access the Mode
Register, the second will access the Interrupt Mask Register, the third will access the Baud Rate Select Register, the
fourth and all subsequent writes will access the TX Buffer
Register.
R
S

RSO RS1 RS2 RS3 -

1
1
1
1

selects the Mode Control Register
selects the Interrupt Mask Register
selects the Baud Rate Select Register
selects the TX Buffer Register

TX ENABLE-Data transmission cannot take place by
the TPUART unless this bit is set. When this bit is reset
(disable), transmission will be disabled only after the
previouslywritten data has been transmitted.
RESET ERRORS-This bit when set will reset the parity, overrun, and framing error bits in the Status Register. No latch is provided in the Control Register for
saving this bit; therefore there is no need to clear it
(error reset = dS.RS. WR).
INTERNAL RESET-This bit enables the resetting of
the internal circuitry and initializes access to address 0
to be sequential.

7

INTERNAL REGISTER SELECT
Following reset, the decode sequence of writes to address
is as follows:

o

RX RESET-This will reset the receiver block only.
TX RESET-This will reset the transmitter block only.

S

FRAMING ERROR-This is set whenever a byte in the
Receive Character Buffer was received with an incorrect bit format ("0" stop bits). This bit is cleared by:
a. setting Reset Errors in the Control Register
b. asserting internal reset
TX BUFFER EMPTY-This signals the processor that
the Transmit Buffer Register is empty and that the
TPUART can accept a new character for transmission.
This bit is set when:

CP2-This bit controls the CP2 output pin. Data at the
output is the logical complement of the register data.
When the CP2 bit is set, the CP2 pin is forced low.
When CP2 is RTS, a 1 to 0 transition of the CP2 bit will
cause the CP2 pin to go high one TXc time after the
last serial bit has been transmitted.
RX ENABLE-This bit when reset will disable the setting of the RX BUFFER FULL bit in the Status Register
which informs the processor of the availability of a
received character in the Receive Buffer Register. The
error bits in the Status Register will be cleared and will
remain cleared when RX is disabled.

2

PARITY ERROR-This signals the processor that the
character stored in the Receive Character Buffer was
received with an incorrect number of binary "1" bits.
This bit is set when the received character in the
Receiver Buffer Register has an incorrect parity bit
and parity has been enabled. This bit is cleared by:
a. setting Reset Errors in the Control Register
b. asserting internal reset

4

DESCRIPTION
Not Used (test mode bit, must be Zero)

0
1

0
0

165

R
S
1
1

0
1
1
1

R
S
2
1
1

0

R
S
3
1
1
1

1
1

0
0

AFTER RESET
AFTER FIRST WRITE
AFTER SECOND WRITE
AFTER THIRD WRITE
ALL SUBSEQUENT WRITES

MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range ...................................................................................... 0 to 70°C
Storage Temperature Range. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 to 150°C
Lead Temperature (soldering, 10 seconds) ........................................................................... + 325°C
Positive Voltage on any pin ......................................................................................... Vcc + 0.3V
Neg!\tive Voltage on any pin, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3V
Maximum Vee ..................... , ..................................................................................... + 7V
·Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from the laboratory or system power supplies, it is important that the Absolute Maximum Ratings
not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC
power is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists,
it is suggested that a clamp circuit be used.

TABLE 6 - ELECTRICAL CHARACTERISTICS
T = O°Cto +70°CVcc = 5.0V ± 5%
PARAMETER
DC CHARACTERISTICS

SYMBOL

MIN

LOW INPUT VOLTAGE
HIGH INPUT VOLTAGE
LOW OUTPUT VOLTAGE

V"
V,H
VOL

2.0

HIGH OUTPUT VOLTAGE
INPUT LEAKAGE CURRENT
INPUT CAPACITANCE
POWER SUPPLY CURRENT

VOH
IL
C'N
Icc

SYMBOL
DESCRIPTION
AC CHARACTERISTICS
WRITE CYCLE
t,

t..
Is
t,

t.
READ CYCLE
t.
t7

t.

t.

t,.

TYP

MAX
0.8

V
V
V

0.4
2.4

V
jJ.A
pF
ma

±10
10
15

MIN

TYP

10L = 5.0ma 0.-07
10L = 3.5ma
10H = 100 jJ.a

MAX

UNITS

CS, RS to WR ! setup time
CS, RS hold time to WR i
WR pulse width
Data BUS in setup time to WR i
Data BUS in hold time to WR i

50
0
100
75
10

ns
ns
ns
ns
ns

CS, RS to RD ! setup time
CS, RS hold time to RD i
RD pulse width
Data access time from RD !
Data hold time from RD i

50
0
100
0
0

ns
ns
ns
ns
ns

60
60

@50pfmax
@50pfmax

GENERAL TIMING
t"
t"
t13
t,.

t,.
CP1, CP2 data

Reset Pulse Width
CP1 active to INT
WR rising edge to CP2 change
CP1, CP2 pulse width
Read Write Interval

1.0
300
200
1.0
100

Rise Time
Fall Time

jJ.s
ns
ns
jJ.s
ns

30
30

ns
ns

30
30
11.0
1.6
40/60

ns
ns
MHz
MHz

Clock Frequency
Rise Time
Fall Time
Internal Baud Rate Mode
External Baud Rate Mode
Duty Cycle

166

%

@25pf

@25pf
@25pf

CS

RS

~,

/
I

*
I

1

:.- t,--J
I

WR

I

*
I

,

l~t2

I.,
1

t3

-,

~.

~
I

I+-t.

1

~,

D'N

t'5

1

.,,,1
I

I

t5

L

•I

1

I

:~
I

I
FIG. 3. PROCESSOR TO TPUART WRITE CYCLE

CS

1

'\

/

I

1
I

RS

I

~

iI ~,

I

1

I
I+- I.-+t
I
I""

~17

Is

I

RD

~I 1
r- 19 1

G~~!

DOUT

I

.1
I

I

1.

I
I

I,s

I I
~11O

I

valid dala

I

L,
I

I

! ~1
I

FIG.4. PROCESSOR "FROM TPUART READ CYCLE

WR------.
TO CONTROL
REGISTER

\

1/

\\

INTERNAL - - - - - - - , \
/
RESET ______________~_~______J"
FIG. S.INTERNAL RESET TIMING
167

I
\\..---

I

I

1

1

1

I

=========%'~------------------~I --------I
I
11(E-------t
...
12 -------i.~1

1
:
INT--------~:---------------.\

1'-----FIG. 6. CP1 TRANSITION TO INT

y

WR - - - - - , \_______-..J

:

~

1

t 13 -----.j

1

- - - - - - - - - - - - - - - 1!
1

I

*

I~------

I

FIG. 7. CP2 OUTPUT TIMING

1

1

I

I
I

~::-------t~----------~*r~==========
:
1
....
1.:;------

t14

-----.~I

1

1

FIG. 8. CP1, CP2 INPUT TIMING

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficientfor construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the right to
make changes at any time in order to improve design and supply the best product possible.

168

COM82C11
PRELIMINARY

Printer Adapter Interface (PAl)
FEATURES

PIN CONFIGURATION

o Fits Popular Centronics Printer Interface
o Programmable parallel printer interface
o Completely TTL-compatible 1/0
o Reduces system package count
o User-controlled interrupt request
o Fully compatible with Z-80 and 8086 microprocessor
o
o
o
o
o

'-'

x,
x,
ClK
DClK
RST
lOW
lOR
DIR
Do

family
High current, direct drive printer interface pins
On-chip oscillator can be used to generate 1.5 MHz to
20 MHz oscillation
Baud rate generation for serial communication
Single 5V supply
Low power CMOS

0,
0,
0,
D.

0,
0,
D,
IRQ
CSI
CS2

v"

7

8
9
10
11
12
13
14
15
16

0

17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22.
21

Voo
A,
AD
Po

p,
P,

p,
P.
P.

p,
p,
ERROR
SlCT
PE
ACK
BUSY
STROB
AUTOFD
INIT
SlCT

PACKAGE: 40-PIN D.I.P.

GENERAL DESCRIPTION
The COM82C11, Printer Adapter Interface (PAl),
fabricated with a silicon gate CMOS process, offers parallel
port interface between the CPU and the printer, and is
especially suitable to printer adapter for industry-standard
personal computers.
The COM82C11 can directly connect to a parallel printer
connector. Printer data bus pins can each source 2.6 mA
and sink 24 mAo Each of the four printer control pins can
source 500pA and sink 7mA. The COM82C11 fits the well-

known Centronics printer interface.
The PAl is also suitable for a personal computer interface
board which contains RS-232C interface or display
interface. The on-chip oscillator and 710 divider can be
used to offer the BAUD-rate clock with RS-232C interface
or the dot clock with monochrome Idi~lay interface.
The user can use the Data Bus, 0 ,lOW, IRQ, CSf and
CS2 pins to interface the PAl with 8086 or Z-80
microprocessors.

x,

x"
eLK

FIGURE 1 BLOCK DIAGRAM

1----:-....1>,. !~~g~g
SLCT

RST

-+------+J
ERROR

BUSY

SLCT
PE

IRO

169

TABLE 1 - COM82C11 PIN DESCRIPTION
PIN NO.
1
2

SYMBOL
X1
X2

3

ClK

4
5

DClK
RST

6

lOW

7

NAME
Crystal In

I/O
I

Clock Out

0

Divided Clock
Reset

0

DESCRIPTION
X1, X2 are the pins to which a crystal (whose frequency is
between 1.5 MHz and 20 MHz) is attached. A TTL clock can be
used on Pin 2 (X2) through a pull up resistor. Pin 1 is left open.
A buffer oscillating clock output whose frequency is the same as
the crystal.
A buffer clock output whose frequency is one-tenth that of Pin 3.

I

An active high RESET pin.
When activa~rinter control outputs STROB, AUTOFD, SlCT
are inactive, INIT is active, and IRO is disabled remaining high
impedence.

I/O Write

I

A "low" on this pin permits the CPU to write data or control words
to the "PAl".

lOR

I/O Read

I

A "low" on this pin permits the "PAl" to send data, control words
or printer status to the CPU. It allows the CPU to read from
the PAl.

8

DIR

Direction

0

This output pin is active high only when CS1 , CS2 and lOR are
activated. It is low for all other cases.
/! indicates the direction of data transfer between CPU data bus
and the PAL
When activated the PAl sends data, control words or printer status
to CPU.

9-16

DO-D7

System Data Bus

I/O

These bidirectional 8-bit data bus pins are connected to the
system data bus.
Data or control words are transmitted or received upon execution
of input or output instructions by the CPU. Status information of
the printer is also received through the data bus.

17

IRQ

Interrupt
Request

Z/O

This is an interrupt request output pin, which is generated when
ACK is activated low.
This pin is enabled by writing D4 = 1 in the control word, and is
high impedance when D4 = O.
When RST is activated, this pin is put into a high impedance state.

18
19
20

CS1
CS2

Chip Select

21

SlCT

22

INIT

23

I

When CS1 = 0 and CS2 = 0, it enables the communication
between the CPU and the PAl.
Power ground pin.

Printer Select

0

Initiate

0

AUTOFD

Auto Feed

0

24

STROB

DataStrob

0

25

BUSY

Busy State

I

26

ACK

Acknowledge

I

When activated low, the printer is selected.
This pin is programmable in bit D3 by writing a control command.
Writing a one to D3 outputs a low on the SlCT pin.
When activatEid low, the printer buffer is cleared. This pin is
programmable in bit D2 by writing a control command and the PAl
outputs D2 signal to this pin.
The pulse width of the !NiT must be more than 50 ps for initiation
of the printer.
When this pin is low, the printer is fed automatically, one line after
printing.
_
This pin is programmable in D1 by writin~Lc¥ntrol command.
Writing a one to D1 outputs allow on the
pin.
When activated low, the printer reads in the data on printer data
bus PO- P7.
It syncronizes data strobe between PAl and printer. This pin is
programmable in bit DO by writingl control command, and writing
a one to DO outputs a low on the lCT pin. Read-in of data is
performed at the low level of this signal.
This is an output from the printer.
A "High" indicates that the printer can't receive data "During Data
Entry", "During Part of Paper Feed", "During Printer Error Status",
"During Printing" or "In OIl-line State". The CPU can read this
status in D7 by "Reading Status".
This is an output from the printer.
A "low" indicates that data bus has been received and that the
printer is ready to accept other data. The CPU can read this status
in D6 by a "Read Status" command.

V••

Ground

170

TABLE 1 - COM82C11 PIN DESCRIPTION
1/0

PIN NO.

SYMBOL

27

PE

28

SLCT

29

ERROR

Error Status

30-37

PO- P7

Printer Data Bus

0

These output pins send out the data to the printer as specified by
the CPU in a "Write Data" command. They are compatible with
TTL logic level. The CPU can also "Read Back" the data which
the CPU last wrote by a "Read Data" command.

38
39

AO
A1

Address

I

These input addresses in conjunction with iQR, lOW, CS1 and
CS2 control the selection of one of the five commands.

Vee

Power Supply

40
Note:

NAME

DESCRIPTION

Paper End

I

This is an output from the printer. A "High" indicates that the
printer is out of paper. The CPU can read this status in 05 by a
"Read Status" command.

Printer Selected
Status

I

This is always "High" unless the printer power is down. The CPU
can read this status in 04 by a "Read Status" command.
This is an output from the printer.
It is "Low" only when the printer is in error status as shown below:
(1) Paper end status.
(2) Abnormal motor operation.
(3) Off-line state.
The CPU can read this status in 03 by a "Read Status"
command.

+5V.

The CPU can "Read Back" the control command it last wrote by reading the contr.ol word. There are STROB, AUTOFD INIT,
SLCT and IRQEN on the data bus DO - 07.

FUNCTIONAL DESCRIPTION
When reset is activated (RST=1), STROBE=1, AUTOFO=1,
INIT=O, SLCT=1, and Interrupt Request "IRQ" is disabled.
Input
CS1

PAl offers five kinds of commands selected by AO, A 1, lOW,
lOR and CS1, CS2 as shown below:
Output

CS2

A1

AD

lOR

lOW

OIR

x
x

x
x

0*

Operation

1

x

x

1

x
x

x
x

0

0

0

0

1

0

0

Write data to the printer.

0

0

0

0

0

1

1

Read data on printer data bus.

0

0

0

1

0

1

1

Read status from the printer.

0

0

1

0

1

0

0

Write control word to the printer.

0

0

1

0

0

1

1

0

0

Notes:

PAl not activated.

0*

Read control word on printer control bus.
(No operation.**)

Others

* When CS1 = 1 or CS2 = 1, DIR = 0, indicates that DO - D7 remain "I/O Write" state even though intennal data bus is not used.
** It is illegal to read anything when chip select is active and AO = A1 = 1.

WRITE DATA to the PRINTER
Data on DO ~ 07 are present on the PO ~ P7 bus and sent to
the printer. At the rising edge of lOW, data is latched on the
PO ~ P7 bus until the next falling edge of lOW.
READ STATUS from the PRINTER
Data

READ DATA on PRINTER DATA BUS
At the falling edge of lOR, data latched on PO ~ P7 is set
back to the CPU through DO ~ 07. The CPU reads back the
printer data.

CPU reads the real-time status of the printer. The states are:
06

05

04

03

STATE
Note: The BUSY state is inverted on D7.

WRITE CONTROL WORD to the PRINTER
CPU writes the control word to the printer. The control signals are:

The control signals are latched on printer control bus at the rising edge of lOW.
Note:

"Interrupt Request Enable (IRQEN)" is not present on any output pin, but enables the output pin IRQ when D4 = 1, and disables IRQ (high
impedance) when D4 = O. SLCT, AUTOFD and STROB are inverted on D3, D1 and DO individually.

READ CONTROL WORD on PRINTER CONTROL BUS
At the falling edge of lOR, IRQEN control bit SLCT pin, INIT pin, AUTOFO pin and STROB pin are sent back to the CPU on
04, 03, 02, 01 and DO individually.
(1) When writing control words 04 = 0 - - - - - IRQ pin floating.
(2) When writing control words 04 = 1 - - - - - IRQ = ACK.
171

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ..............•........................................•..•.. O°C to + 70°C
Storage Temperature Range ................•.................................•...........•.-65°C -150°C
Lead Temperaiure (soldering 10 sec.) ...........•..............................•....•.•........... +300°C
Positive Voltage on any I/O Pin, with respect to ground .................•........................... Vee + O.3V
Negative Voltage on any liD Pin, with respect to ground ....................•.......•................... -O.3V
Maximum Vee ....•..............•...........................•..................................... +7V
" Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their
outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may appear on the DC
output. For example, the bench power supply programmed to deliver +5 volts may have large voltage transients when the
AC power is switched on and off. If this possibility exists it is suggested that a clamp circuit be used.

TABLE 2 - ELECTRICAL CHARACTERISTICS (Ta
D.C. Characteristics
SYMBOL
V,L
V,H
VOL
VOH
liN
10Lo
10Ho
10Le
10He
IFL
lop

PARAMETER
Input low Voltage
Input High Voltage
Output low Voltage
Output High Voltage
Max. Input Current
Output Sink Current
Printer Data Bus =0
Output Source Current
Printer Data Bus =1
Output Sink Current
Printer Control Bus =0
Output Source Current
Printer Control Bus =1
Floating Pin leakage
Operation Current

=Co -70°C, Vec =+5V ± 5%, C, =50pF)

MIN.

TYP.

MAX.

UNITS

-

0.4
2.4
0.4

0.8

V
V
V
V
/1V

10L = Max
10H = Max
V,N =Vee or GND

2.0

0.5

-

-

20

24

-

ma

VOL =0.45V

2.0

2.6

-

ma

VOH

7.0

-

-

ma

VOL =0.45V

-

0.5

1.5
±10
30

ma
/1a
ma

VOH =3.0V
VFL =Vee or GND

2.4

-

10

-

COMMENTS

±10

=3.0V

A.C. Characteristics
SYMBOL

PARAMETER

MIN.

MAX.

UNIT

-

ns
ns
ns
ns
ns
ns

-

ns
ns
ns
ns
ns
ns
ns
ns

-

ns
ns
ns
ns
ns
ns
ns
ns
ns

WRITE
Tww
TAW
TWA
Tow
Two
TwoL
READ

Write Pulse Width
Address to lOW Set-up Time
Address Hold Time after lOW
Data to lOW Set-up Time
Data Hold Time after lOW
lOW = 1 to Data latched

200
0
20
70
30

TRR
Too
TAR
TRA
TPR
TRP
TROS
TROR

Read Pulse Width
DIR Delay after lOR
Address to lOR Set-up Time
Address Hold Time after lOR
Printer Bus to lOR Set-up Time
Printer Bus Hold Time after lOR
lOR to DO - D7 Output
DO - D7 Released after lOR

300

-

90

-

35

-

70
30

0
20
0
0

"Note: When CPU reads the printer's status, it is real-time stale.

OTHERS
TRSW
TRscH
TRSIN 1
TRSIR Z
T,D
T,z
T,E
TRSIZ
TocKo

Reset Pulse Width
Reset to Control Bus =-1.jSTROB, AUTOFD, SlCT) Propagation Delay
Reset to Control Bus INIT = 0 Propagation Delay
IRQ MIGH -z after RST
ACK to IRQ Propagation Delay
IRQ Disable Time
IRQ Enable Time
IRQ High-z after RST
ClK to OClK Propagation Delay

172

40

-

150
60
50
45
50
50
50
10

X

X

2.4

_ _ _ _--'

0.45

2.0V
20·.OS
O.SV TEST POINT
_ '_ _ _ _ _ _ _ _ _ _ _ _ __
OUTPUT LOAD:

50 pF

FIGURE 2-A.C. TESTING INPUT WAVEFORM

Tww

"

I

~

_ T AW _

AO
A1

TWA

~

(
Tow

DO~D7

DATA BUS

V

, _Two . .

K

).

TwoL _
PO~P7

OR
PRINTER

~

CONTROL BUS

FIGURE 3-WRITE CYCLE WAVEFORM

IRQEN (D4)

'-

IRQ

T,E

~-----....:...~l::::F::.::::-~,,:r-----­
FLOATING

FIGURE 4-INTERRUPT REQUEST WAVEFORM
173

TRR
j~

""I

-'"

Too

Ar/J,A1

~

- TAR __

TRA

~
TpR

DATA ON
PRINTER DATA BUS
OR CONTROL BUS
OR STATUS BUS

~

r£

DIR

CS1,CS2

IJo~

f-

--

"
'V
)\

~TRP-

~~
)\

J

*______

DO-D7_~_·

--TRoR~

-TRos

FIGURE 5-READ CYCLE WAVEFORM

I
RST

TRsw

-------"V
I

TRSCH

I"

1
"I

I
"I

~

I~----------------------------

I

-----------~!~--------------------------

IRQ

•

')~

______
FL_O_A_J____

FIGURE 6-RESET WAVEFORM
174

~(~

__________________

TYPICAL APPLICATIONS
PRINTER 25-PIN

-

r--

A31
A30

Al
ADDRESS

"..

00
01
D2
03
04
05
06
D7

DECODERIr CS2

A9
AS
A7
A6
A5
A4
A3
A2

B2

lOIR
Bl
B2
B3
B4
B5
B6
B7
B8

Al

00

A2

01

A3

02

A4

03

B13

~
~
~
~
~
~

~
~
~
~
~

STROB
AUTOFO
INIT
SLCT

05
06
07

RST

lOR

.--:;0

ACK
BUSY
PE
SLCT
ERROR

-lOW

lOW

B14

DATAO
DATAl
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7

~

PAl

04

A5
A6
A7
~ OE AS
='
LS245
RESET

7

PO
Pl
P2
P3
P4
P5
P6
P7

CSl

OIR

PSLOT

DSHELL
CONNECTOR

AO

ACK
BUSY
PE
SLCT
ERROR

>-tf"""
>-it"'
>-;3"C
~
~

lOR

B21

IRQ

-

~

FIGURE 7-PAI ON PRINTER CARD

-

ADDRESS

~

f-I

~DECOOER~

I

AO
Al

Xl

Bl
B2
B3
B4
B5
B6
B7
B8

G

LS
245

UART

....

...

RS232C
SERIAL CONNECTION

1.8432 MHZl
CSl
AO
Al

Dg

CK -+-NC
Xl
X2

Al
A2
A3
A4
A5
A6
A7
A8

DO
Dl
D2
D3
D4
05
D6
D7

r- DIR

lOR
lOW
RESET

30PF

.;J;.

PO
Pl
P2
P3
P4
P5
P6
P7

S'TROB
AO'fOFD
ro;r

lOR
lOW
RST

r

~ 18.4313
MHz

~~PF
,1;.

m

IRQ7

-

...

8250

19

00
Dl
D2
3
04
D5
D6
07

SLOT

r

CS

IRQ

SLCT
BUSY
PE

CS2

ER~g~

1IIIIIIIIJr

11122~
"'1"_

.......

-

DATAO
DATAl
DATA2
DATA:)
DATA4
DATA5
DATA6

-~

4

:....

m

SLCT
BUSY

1

.........

-- L

L...-PRINTER 25-PIN
D-SHELL CONNECTOR

FIGURE 8-PAI ON MULTIFUNCTION CARD
175

PACKAGE INFORMATION - MILLIMETER (INCH)
40 LEAD PLASTIC DIP

o

o

T

14.22 (0.560)
13.72 (0.540)

~
\+- 15.49 (0.610) --l
I r 14.99 (0.590), I

51.5 (2.080)
51.0 (2.050)

3.43 (0.135)
3.05 (0.120)

2.16 (0.085)
1.65 (0.065)

2.79 (0.110)
2.29 (0.090)

0.53 (0.021)
0.36 (0.015)

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications: consequently complete information sufficient for construction purposes is not necessarily given. The information has been carefully
checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such

~~b"6~t~~g~~e~~'1l ~~~:J.,~t~:r?~~~~a~e;~d~~~~~~~~~~~~~~f~~r~~~ro":;;;~;:'~!l~f;~~~~~~~~l~~~eal!~ ~~~~~

possible.

176

COM 8251 A
J,LPC FAMILY

Universal Synchronous IAsynchronous
ReceiverITransmitter
USART

FEATURES

PIN CONFIGURATION

o Asynchronous or Synchronous Operation

o
o
o
o

o
o
o

- Asynchronous:
5-8 Bit Characters
Clock Rate -1, 16 or 64 X Baud Rate
Break Character Generation
1,1'12 or 2 Stop Bits
False Start Bit Detection
Automatic Break Detect and Handling
-Synchronous
5-8 Bit Characters
Internal or External Character Synchronization
Automatic Sync Insertion
Single or Double Sync Characters
Programmable Sync Character(s)
Baud Rate - Synchronous - DC to 64K Baud
-Asynchronous-DC to 19.2K Baud
Baud Rates available from SMC's COM 8116,
COM 8126, COM 8136, COM 8146, and COM 8046
Full Duplex, Double Buffered Transmitter and
Receiver
Odd parity, even parity or no parity bit
Parity, Overrun and Framing Error Flags
Modem Interface Controlled by Processor
All Inputs and Outputs are TTL Compatible

02 1

2801

03 2

2700

RxO 3
GNO 4

26 Vee
25 RxC

04 5

24 OTR

05 6

23 RTS

06 7

22 OSR

07 8
TxC 9

21 RESET

WR 10

20 ClK
19 TxO

CS 11
C/i) 12

18 TxEMPTY
17 Cf§

RO 13
RxROY 14

16 SYNOET/BO
15 TxROY

o Compatable with Intel 8251A, NEC pPD8251A

o Single +5 Volt Supply
o Separate Receive and Transmit TTL Clocks
o Enhanced version of 8251
028 Pin Plastic or Ceramic DIP Package
o COPLAMOS® N-Channel MaS Technology
BLOCK DIAGRAM

GENERAL DESCRIPTION
The COM 8251A is an MaS/LSI device fabricated
using SMC's patented COPLAMOS® technology that
meets the majority of asynchronous and synchronous
data communication requirements by interfacing
parallel digital systems to asynchronous and
synchronous data communication channels while
requiring a minimum of processor overhead. The
COM 8251A is an enhanced version of the 8251.
The COM 8251A is a Universal Synchronous!
Asynchronous Receiver/Transmitter (USART)
designed for microcomputer system data
communications. The USART is used as a peripheral
and is programmed by the processor to communicate
in commonly used asychronous and synchronous
serial data transmission techniques including IBM
Bi-Sync. The USART receives serial data streams and
converts them into parallel data characters for the
processor. While receiving serial data, the USART
will also accept data characters from the processor in
parallel format, convert them to serial format and
transmit. The USART will signal the processor when it
has completely received or transmitted a character
and requires service. Complete USART status,
including data format errors and control signals such
as TxE and SYNDET, is available to the processor at
anytime.

177

D7-00

TxADY

TxEMPTY

T,C

AxRDV

R,C
SYNDETI
8RKOET

DESCRIPTION OF PIN FUNCTIONS
PIN NO. SYMBOL

NAME

INPUT/
OUTPUT

1,2,27,
28,5-8

02,03, DO·
01,04-07

DATA BUS

1/0

3

RxD

RECEIVER DATA

I

FUNCTION
An 8-bit, 3-state bi-directional DATA BUS used to interface the
COM 8251A to the processor data bus. Data is transmitted or
received by the bus in response to input/output or Read/Write
instructions from the processor. The DATA BUS also transfers
Control words, Command words, and Status.
This input receives serial data into the USART.

4

GND

GROUND

GND

9

TxC

TRANSMITTER

I

The TRANSMITTER CLOCK controls the serial charactertransmission rate. In the Asynchronous mode, the TxC frequency is
a multiple ofthe actual Baud Rate. Two bits of the Mode I nstruction selectthe multipletobe1X, 16X,or64Xthe Baud Raie.lnthe
Synchronous mode, the TxC frequency is automatically selected to equal the actual Baud Rate.
Note that for both Synchronous and Asynchronous modes,
serial data is shifted out oftheUSART by the falling edgeof~.

10

WR

WRITE DATA

I

A "zero" on this input instructs the COM 8251A to accept the
data or control word which the processor is writing out to the
USART via the DATA BUS.

11

CS

CHIP SELECT

I

A "zero" on this input enables the USART for reading and writing
to the processor. When CS is high, the DATA BUS is in the float
state and RD andWR will have no effect on the chip.

12

C/O

CONTROL/DATA

I

The Control/lJaiii input, in conjunction with the WR and RD
inputs, informs the USART to accept or provide either a data
character, control word or status information via the DATA BUS.
o= Data; 1 = Control/Status

13

RD

READ DATA

I

A "zero" on this input instructs the COM 8251A to place the data
or status information onto the DATA BUS for the processor
to read.

14

RxRDY

RECEIVER READY

a

The RECEIVER READY output indicates that the Receiver
Buffer is ready with an "assembled" character for input to the
processor. For polled operation, the processor can check
RxRDY using a Status Read or RxROY can be connected to the
processor interrupt structure. Note that reading the character
to the processor automatically resets RxRDY.

15

TxRDY

TRANSMITTER READY

a

TRANSMITTER READY signals the processor that the transmitter is ready to accept a data character. TxROY can be used
as an interrupt or may be tested through the Status information
polled ~aton. TxRDY is automatically reset by the leading
edge of
when a data character is loaded from the processor.

16

SYNDET/
BRKDET

SYNC DETECT/
BREAK DETECT

I/O

The SYNDET feature is only used in the Synchronous mode.
The USART may be programmed throughtheMode Instruction
to operate in either the internal or external Sync mode and
SYNDET then functions as an output or input respectively. In
the internal SYNC mode, the SYNDET output will go to a "one"
when the COM 8251A has located the SYNC character in the
Receive mode. If double SYNC character (bi-sync) operation
has been programmed, SYNDET will go to "one" in the middle
of the last bit of the second contiguously detected SYNC character. SYNDET is automatically reset to "zero" upon a Status
Read or RESET. In the external SYNC mode, a "zero" to "one"
transition on the SYNDET input is sampled during the negative
half cycle of RxC and will cause the COM 8251A to start assembling data character on the next rising edge of RxC. The
length of the SYNDET input should be at least one RxC period,
but may be removed once the COM 8251A is in SYNC. When
external SYNC DETECT is programmed, the internal SYNC
DETECT is disabled.

~

Ground

178

PIN NO. SYMBOL

NAME

INPUTI
OUTPUT

16
(cont.)

FUNCTION
The SYNDET/BRKDET pin is used in both Synchronous and
Asynchronous modes. When in SYNC mode the features for
the SYNDET pin described above apply. When inAsynchronous
mode, the BREAK DETECT output will go high when an all zero
word of the programmed length is received. This word consists
of: start bit, data bit, parity bit and onestop bit.Resetonlyoccurs
when Rx Data returns to a logic one state or upon chip RESET.
The state of BREAK DETECT can also be read as a status bit.

17

CTS

CLEAR TO SEND

I

A "zero" on the CLEAR TO SEND input enables the USART to
transmit serial data if the TxEN bit in the Command Instruction
register is enabled (one).
If either a TxEN off or CTS off condition occurs while the Tx is
in operation, the Tx will transm it all the data in the USARTwritten
prior to the Tx Disable command before shutting down.

18

TxE

TRANSMITTER EMPTY

0

The TRANSMITTER EMPTY output signals the processor that
the USART has no further characters to transmit. TxE is automatically reset upon receiving adatacharacterfrom the processor. In half-duplex, TxE can be used to signal end of a transmission and request the processor to "turn the line around".
The TxEN bit in the command instruction does not effect TxE.
In the Synchronous mode, a "one" on this output indicates that
a SYNC character or characters are about to be automatically
transmitted as "fillers" because the next data character has not
been loaded; an underflow condition. If the US ART is operati ng in the two SYNC character mode, both SYNC characters will
be transmitted before the message can resume. TxE does not
go low when the SYNC characters are being shifted out. TxE
goes low upon the processor writing a character to the USART.

19

TxD

TRANSMITTER DATA

0

This output is the transmitted serial datafromthe USART. When
a transmission is concluded the TxD line will always return to
the marking state unless SBRK is programmed.

20

ClK

CLOCK PULSE

I

The ClK input provides for internal device timing. External
inputs and outputs are not referenced to ClK, but the ClK
frequency must be greater than 30 times the RECEIVER or
TRANSMITTER CLOCKS in the 1X mode and greater than 4.5
times forthe 16X and 64X modes.

21

RESET

RESET

I

A "one" on this input forces the USART into the "idle" mode
where it will remain until reinitialized with a new set of control
words. RESET causes: RxRDY=TxRDY=TxEmpty=SYNDET/
BRKDET = 0; TxD = DTR = RST = 1. Minimum RESET pulse
width is 6 tCY, ClK must be running during RESET.

22

DSR

DATA SET READY

I

The DATA SET READY inp'ut can be tested by the processor
via Status information. The DSR input is normally used to test
Modem Data Set Ready condition.

23

RTS

REQUEST TO SEND

0

The REQUEST TO SEND output is controlled via the Command
word. The RTS output is normally used to drive the Modem
Request to Send line.

24

DTR

DATA TERMINAL
READY

0

The DATA TERMINAL READY output is controlled via the
Command word. The r5i'R output is normally used to drive
Modem Data Terminal Ready or Rate Select lines.

25

RxC

RECEIVER CLOCK

I

The RECEIVER CLOCK is the rate at which the i.ncoming character is received. I n the Asynchronous mode, the RXC frequency
may be 1, 16 or 64 times the actual Baud Rate but in the Synchronous mode the RxC frequency must equal the Baud Rate.
Two bits in the mode instruction select Asynchronous at 1X,
16X or 64X or Synchronous operation at 1X the Baud Rate.
Data is sampled into the USART on the riSing edge of RxC.

26

Vcc

Vcc SUPPLY VOLTAGE

PS

+5 volt supply

179

DESCRIPTION OF OPERATION-ASYNCHRONOUS
Transmlssion-

Recelve-

When a data character is written into the US ART, it automatically adds a START bit (low level or "space") and the
number of STOP bits (high level or "mark") specified by
the Mode Instruction. If Parity has been enabled, an odd
or even Parity bit is inserted just before the STOP bit(s),
as specified by the Mode Instruction. Then, depending
on CTS and TxEN, the character may be transmitted as a
serial data stream at the TxD output. Data is shifted out by
the falling edge of TxC at a transmission rate of TxC,
TxC/16 or TxC/64, as defined by the Mode Instruction.

The RxD input line is normally held "high" (marking) by
the transmitting device. A falling edge (high to low transition) at RxD signals the possible beginning of a START bit
and a new character. The receiver is thus prevented from
starting in a "BREAK" state. The START bit is verified by
testing for a "low" at its nominal center as specified by the
BAUD RATE. If a "low" is detected, it is considered valid,
and the bit assembling counter starts counting. The bit
counter locates the approximate center of the data, parity
(if specified), and' STOP bits. The parity error flag (PE) is
set, if a parity error occurs. Input bits are sampled at the
RxD pin with the rising edge of RxC. If a high is not detected for the STOP bit, which normally signals the end
of an input character, a framing error (FE) will be set. After
the STOP bit time, the input character is loaded into the
paralled Data Bus Buffer of the USART and the RxRDY
signal is raised to indicate to the processor that a character
is ready to be fetched. If the processor has failed to fetch
the previous character, the new character replaces the old
and overrun flag (OE) is set. All the error flags can be reset
by setting a bit in the Command Instruction. Error flag
conditions will not stop subsequent USART operation.

If no data characters have been loaded into the USART, or
if all available characters have been transmitted, the TxD
output remains "high" (marking) in preparation for sending the START bit of the next character provided by the
processor. TxD may be forced to send a BREAK (continuously low) by setting the correct bit in the Command
Instruction.

DESCRIPTION OF OPERATION-SYNCHRONOUS

Transmission As in Asynchronous transmission, the TxD output remains "high" (marking) until the USART receives the first
character (usually a SYNC character) from the processor.
After a Command Instruction has set TxEN and after
Clear to Send (CTS) goes low, thefirstcharacterisser~
transmitted. Data is shifted out on the falling edge ofTxC
at the same rate as TxC.
Once transmission has started, Synchronous Data Protocols require that the serial data stream at TxD continue
at the TxC rate or SYNC will be lost. If a data character is
not provided by the processor before the USARTTransmit
Buffer becomes empty, the SYNC character(s) loaded
directly following the Mode Instruction will be automatically inserted in the TxD data stream. The SYNC character( s) are inserted to fill the Ii ne and mai ntai n synch ronization until the new data characters are available for
transmission. If the U8ART becomes empty, and must
send the SYNC character(s), the TxEMPTY output is
raised to signal the processor that the Transmitter Buffer
is empty and SYNC characters are being transmitted.
TxEMPTY is automatically reset by the next character
from the processor.

ReceiveIn Synchronous receive, character synchronization can
be either external or internal. If the internal SYNC mode

has been selected, the ENTER HUNT (EH) bit has been
set by a Command Instruction, the receiver goes into the
HUNT mode.
Incoming data on the RxD input is sampled on the rising
edge of Rxe, and the contents of the Receive Buffer are
compared with the first SYNC character after each bit has
been loaded until a match is found. IftwoSYNCcharacters
have been programmed, the next received character is
also compared. When the (two contiguous) SYNC character(s) programmed have been detected, the USART
leaves the HUNT mode and is in character synchronization. Atthistime, theSYNDET (output) issethigh.SYNDET
is automatically reset by a STATUS READ.
If external SYNC has been specified in the Mode Instruction, a "one" applied to the SYNDET (input) for at least
one Rxe cycle will synchronize the USART.
Parity and Overrun Errors are treated the same in the
Synchronous as in the Asynchronous Mode. If not in
HUNT, parity will continue to be checked even if the receiver is not enabled. Framing errors do not apply in the
Synchronous format.
The processor may command the receiver to enter the
HUNT mode with a Command Instruction which sets
Enter HUNT (EH) if synchronization is lost. Under this
condition the Rx register will be cleared to all "ones".
180

OPERATION AND PROGRAMMING
The microprocessor program controlling the COM 8251A
performs these tasks:

Control codes determine the mode in which the COM
8251A will operate and are used to set or reset control
signals output by the COM 8251A
The Status register contents will be read by the program
monitoring this device's operation in order to determine
error conditions, when and how to read data, write data or
output control codes. Program logic may be based on
reading status bit levels, or control signals may be used
to request interrupts.

• Outputs control codes
- Inputs status
- Outputs data to be transmitted
-Inputs data which has been received

INITIALIZING THE COM 8251A
Figure 1. Control Word Sequences for Initialization
MODE CONTROL

C/ll=, {

}

MODE CONTROL

INITIALING
SEQUENCE

COMMAND

SYNC#'

c/ll=,

SYNC #2
(OPTIONAL)

DATA

C/ll=O{
C/ll=,

··

INITIALING
SEQUENCE

COMMAND

COMMAND

DATA

C/ll=o

··

~

DATA

··

COMMAND

C/D='

C/D=O

{

DATA

··

ASYNCHRONOUS OPERATION

SYNCHRONOUS OPERATION

The COM 8251A may be initialized following a system
RESET or prior to starting a new seralllO sequence. The
USART must be RESET (external or internal) following
power up and subsequently may be reset at any time
following completion of one activity and preceding a
new set of operations. Following a reset, the COM 8251A
enters ari idle state in which it can neither transmit nor
receive data.

mode byte) output as control codes will be interpreted as
SYNC characters. For either asynchronous or synchronous operation, the next byte output as a control code is
interpreted as a command. All subsequent bytes output
as control codes are interpreted as commands. There are
two ways in which control logic may return to anticipating
a mode control input; following aRESET inputorfollowing
an internal reset command. A reset operation (internal via
IR or external via RESET) will cause the USART to interpret the next "control write", which should immediately
follow the reset, as a Mode Instruction.
After receiving the control words the USART is ready to
communicate. TxRDY is raised to signal the processor
that the USART is ready to receive a character for transmission. Concurrently, the USART is ready to receive
serial data.

The COM 8251A is initialized with two, three or four control words from the processor. Figure 1 shows the sequence
of control words needed to initialize the COM 8251A, for
synchronous or for asynchronous operation. Note that
in asynchronous operation a mode control is output to
the device followed by a command. For synchronous
operation, the mode control is followed by one or two
SYNC characters, and then a command.
Only a single address is set aside for mode control bytes,
command bytes and SYNC character bytes. For this to be
possible, logic internal tothe chip directs control information to its proper destination based on the sequence in
which it is received. Following a RESET (external or internal), the first control code output is interpreted as a mode
control. If the mode control specifies synchronousoperation, then the next one or two bytes (as determined by the
181

C/D

RD

0
0

0

WR
1

1

0

1
1

0

1

1

X
X

X

0
X

1

1

CS
0
0
0
0

USART - Data Bus
Data Bus - USART
Status - Data Bus
Data Bus - Control

1
0

Data Bus - 3-State

MODE CONTROL CODES
The COM 8251A interprets mode control codes as illustrated in Figures 2 and 3.

determine whether there will be a parity bit in each character, and if so, whether odd or even parity will beadopted.
Thus in synchronous mode a character will consist offive,
six, seven or eight data bits, plus an optional parity bit. In
asynchronous mode, the data unit will consist offive, six,
seven or eight data bits, an optional parity bit, a preceedlng
start bit, plus 1, 11f2 or 2 trailing stop bits. Interpretation of
subsequent bits differs for synchronous or asynchronous
modes.

Control code bits Oand 1 determinewhethersynchronous
or asynchronous operation is specified. A non-zero value
in bits 0 and 1 specifies asynchronous operation and defines the relationship between data transfer baud rate and
receiver or transmitter clock rate. Asynchronous serial
data may be received ortransmitted on every clock pulse,
on every 16th clock pulse, or on every 64th clock pulse,
as programmed. A zero in both bits 0 and 1 defines the
mode of operation' as synchronous.

Control code bits 6 and 7 in asynchronous mode determine
how many stop bits will trail each data unit. 1112 stop bits
can only be specified with a 16X or 64X baud rate factor.
In these two cases, the half stop bit will be equivanlent to
8 or32 clock pulses, respectively.

For synchronous and asynchronous modes, control bits
2 and 3 determine the number of data bits which will be
present in each data character. In the case of a programmed
character length of less than 8 bits, the least significant
DATA BUS unused bits are "don't care" when writing data
to the USART and will be "zeros" when reading data. Rx
data will be right justified onto DO and the LSB forTx data
is DO.

In synchronous mode, control bits 6 and 7 determine
how character synchronization will be achieved. When
SYN DET is an output, internal synchronization is specified;
one or two SYNC characters, as specified by control bit 7,
must be detected at the head of a data stream in order to
establish synchronization.

For synchronous and asynchronous modes, bits 4 and 5

COMMAND WORDS
specific functions are to be initialized within the communication circuit.

Command words are used to initiate specific functions
within the COM 8251A such as, "reset all error flags" or
"start searching for sync". Consequently, Command
Words may be issued by the processor to the COM 8251 A
at any time during the execution of a program in which

Figure 4 shows the format for the Command Word.

Figure 4. COM 8251A Control Command
765432

I

I

I

I

I

I

O_BitNo.

I

I

I

~

TxEN
1 = Enable transmission
o = Disable transmission
DTR
1 = DTR output is forced to 0
RxE
1 = Enable RxRDY
0= Disable RxRDY
SBRK
1 = TxD is forced low
o = Normal operation
ER
1 = Resets all error flags in
Status register (PE. OE, FE)
RTS
1 = RTS output is forced to 0

IR
1 = Reset format
EH
1 = Enter HUNT mode

182

Figure 2. Synchronous Mode Control Code.

7

6

I

5

4

I I I

3

2

1

O~BitNo.

I0 I0 I
~

~

~sY",mod'
00
01
10
11

5 bits per character
6 bits per character
7 bits per character
8 bits per character

0= Parity disable, 1 = Parity enable
0= Odd parity, 1 = Even parity
0= SYNDET output
1 = SYNDET input
0= 2 SYNC characters
1 = 1 SYNC character

Figure 3. Asynchronous Mode Control Code.

7

I

6

~

5

4

I I I

3

2

~

1

O~BitNo.

I I I
~

t

00
01
10
11

Invalid (SYNC mode)
Async mode, 1 X Baud rate factor
Async mode, l6X Baud rate factor
Async mode, 64X Baud rate factor

00 5 bits per character
01 6 bits per character
10 7 bits per character
11 8 bits per character
0= Parity disable, 1 = Parity enable
0= Odd parity, 1 = Even parity
00
01
10
11

183

Invalid
1 stop bit.
1'1. stop bits
2 stop bits

Bit 2 is the Receiver Enable Command bit (RxE). RxE is
used to enable the RxRDY output signal. RxE, when zero,
prevents the RxRDY signal from being generated to notify
the processor that a complete character is framed in the
Receive Character Buffer. It does not inhibitthe assembly
of data characters at the input, however. Consequently,
if communication circuits are active, characters will be
assembled by the receiver and transferred to the Receiver
Buffer. If RxE is disabled, the overrun error (OE) will probably be set; to insure proper operation, the overrun error
is usually reset with the same com mand that enables RxE.

Bit 0 of the Command Word is the Transmit Enable bit
(TxEN). Data transmission for the COM 8251A cannot
take place unless TxEN is set (assuming CTS = 0) in the
command register. The TX Disable command is prevented
from halting transmission by the Tx Enable logic until all
data previously written has been transmitted. Figure 5
defines the way in which TxEN, TxE and TxRDY combines
to control transmitter operations.
Bit 1 is the Data Terminal Ready (DTR) bit. When the DTR
command bit is set, the DTR output connection is activ.e
(low). DTR is used to advise a modem thatthe data terminal
is prepared to accept or transmit data.

Figure 5.
Operation of the TransmiHer Section as a Function of TxE, TxRDY and TxEN
TxEN
1

TxE
1

TxRDY
Transmit Output Register and Transmit Character Buffer empty.
1
TxD continues to mark if COM 8251A is in the asynchronous mode.
TxD will send SYNC pattern if COM 8251A is in the Synchronous
Mode. Data can be entered into Buffer.

o

o

Transmit Output Register is shifting a character. Transmit Character
Buffer is available to receive a new byte from the processor.

o

Transmit Register has finished sending. A new character is waiting
for transmission. This is a transient condition.

o

0

Transmit Register is currently sending and an additional character
is stored in the Transmit Character Buffer for transmission.

0/1

0/1

Transmitter is disabled.
return to the Idle mode. All functions within the COM
8251A cease and no new operation can be resumed until
the circuit is reinitialized. If the operating mode is to be
altered during the execution of a processor program, the
COM 8251A must first be reset. Either the RESET input
can be activated, or the Internal Reset Command can be
sent to the COM 8251A. Internal Reset is a momentary
function performed only when the command is issued.

Bit3 is the Send Break Command bit (SBRK). When SBRK
is set, the transmitter output (TxD) is interrupted and a
continuous binary "0" level, (spacing) isappliedtotheTxD
output signal. The break will continue until a subsequent
Command Word is senttotheCOM 8251 A to removeSBRK.
Bit 4 is the Error Reset bit (ER). When a Command Word
is Uansferred with the ER bit set, all three error flags (PE,
OE, FE) in the Status Register are reset. Error Reset occurs
when the Command Word is loaded into the COM 8251A.
No latch is provided in the Command Registerto save the
ER command bit.

Bit 7 is the Enter Hunt command bit (EH). The Enter Hunt
mode command is only effective for the COM 8251A when
it is operating in the Synchronous mode. EH causes the
receiver to stop assembling characters at the RxD input,
clear the Rx register to all "ones", and start searching for
the prescribed sync pattern. Once the "Enter Hunt" mode
has been initiated, the search for the sync pattern will
continue indefinitely until EH is reset when a subsequent
Command Word is sent, when the IR command is sent to
the COM 8251 A, or when SYNC characters are recognized.
Parity is not checked in the EH mode.

Bit 5, the -=R"'-eq-u-e-s""t-=T""o""'S""'e-n"';'d Command bit (RTS), sets a
latch to reflect the RTS signal level. The output of this
latch is created independently of other signals in the
COM 8251A. As a result, data transfers may be made by
the processor to the Transmit Register, and data may be
actively transmitted to the communication line through
TxD regardless of the status of RTS.
Bit 6, the Internal Reset (IR), causes the COM 8251A to

STATUS REGISTER
totally equivalent to the TxRDY output pin, the relationship
The Status Register maintains information about the
is as follows:
current operational status of the COM 8251A. Status can
be read at any time, however, the status update will be
TxRDY (status bit) = Tx Character Buffer Empty
inhibited during status read. Figure 6 shows the format of
TxRDY (pin 15) = Tx Character Buffer Empty. CTS • TxEN
the Status Register.
TxRDY signals the processor that the Transmit Character
Buffer is empty and that the COM 8251A can accept a new
character for transmission. The TxRDY status bit is not
184

RxRDY signals the proceljsor that a completed character
is holding in the Receive Character Buffer Register for
transfer to the processor.

Figure 6. The COM 8251A Status Register

7
I

6
I

5
I

4
I

3
I

2
I

O-+-BitNo.

I

I

I

i

TxRDY
RxRDY
TxE
PE
Parity error

OE
Overrun error

FE
Framing error

SYNDET/BRKDET
DSR

TxE signals the processor that the Transmit Register
is empty.

SYNDET is the synchronous mode status bit associated
with internal or external sync detection.

PE is the Parity Error signal indicating to the CPU that the
character stored in the Receive Character Buffer was
received with an incorrect number of binary "1" bits. PE
does not inhibit USART operation. PE is reset by the ER bit.
OE isthe receiver Overrun Error. OE issetwheneverabyte
stored in the Receiver Character Register is overwritten
with a new byte before being transferred to the processor.
OE does not inhibit USART operation. OE is reset by the
ER bit.

DSR is the status bit set by the external "'D"'a7""taCCS"e""t'-;R"e'-'a'--d'y
signal to indicate that the communication Data Set is
operational.
All status bits are set by the functions described for
them. SYNDET is reset whenever the processor reads the
Status Register. OE, FE, PE are reset by the error reset
command or the internal reset command or the RESET
input. OE, FE, or PE being set does not inhibit USART
operation.

FE (Async only) is the character framing error which indicates that the asynchronous mode byte stored in the
Receiver Character Buffer was received with incorrect bit
format ("0'; stop bit), as specified by the current mode. FE
does not inhibit USART operaton. FE is reset by the ER bit.

Many olthe bits in the status register are copies of external
pins. This dual status arrangement allows the USART to
be used in both Polled and Interrupt driven environments.
Status update can have a maximum delay of 16 tCY periods.

Note:

1. While operating the receiver it is important to realize
that the RxE bit of the Command Instruction only inhibits the assertion of RxRDY; it does not inhibit the
actual reception of characters. As the receiver is constantly running, it is possible for it to contain extraneous
data when it is enabled. To avoid problems this data
should be read from the USART and discarded. This
read should be done immediately following the setting
olthe RxE bit in the asynchronous mode, and following
the setting of EH in the synchronous mode. It is not
necessary to wait for RxRDY before executing the
clummy read.

3. The USART may provide faulty RxRDY for the first read
after power-on or for the first read after the receiver is
re-enabled by a command instruction (RxE). A dummy
read is recommended to clear faulty RxRDY. This is not
the case for the first read after hardware or software
reset after the device opration has been established.
4. Internal Sync Detect is disabled when External Sync
Detect is programmed. An External Sync Detect Status
is provided through an internal flip-flop which clears
itself, assuming the External Sync Detect assertion has
removed, upon a status read. As long as External Sync
Detect is asserted, External Sync Detect Status will
remain high.

2. ER should be performed whenever RxE of EH are programmed. ER resets all error flags, even if RxE = O.

185

MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range ............................................................ O°C to +70°C
Storage Temperature Range .......................................................... -55°C to +150°C
Lead Temperature (soldering, 10 sec) ........................................................... +325°C
Positive Voltage on any Pin, with respect to ground ................................................. +8.0V
Negative Voltage on any Pin, with respect to ground ................................................ -0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit
voltage spikes or "glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transients on the AC power line may appear on the DC output. If this
possibility exists it is suggested that as clamp circuit be used.
ELECTRICAL CHARACTERISTICS (TA = O°C to 70°C, Vee = +5V ±5%, unless otherwise noted)
PARAMETER

SYMBOLI

I MIN. I

MAX.

TEST CONDITIONS

UNIT I

D.C. Characteristics
V,L

Input Low Voltage

-0.3

0.8

V

V,H

Input High Voltage

2.0

Vee

V

VOL

Output Low Voltage

0.45

V

IOL=2.2 mA

VOH

Output High Voltage

V

IOH=-400pA

IOFL

Output Float Leakage

±10

pA

VOUT = Vee TO 0.45V

hL

Input Leakage

±10

pA

V,N = Vee TO 0.45V

lee

Power Supply Current

100

mA

All Outputs = High

10

pF

20

pF

2.4

CapaCitance
C,N
CliO

TA=25°C,Vee=GND

I

Input Capacitance

I

1/0 Capacitance

I

IfC=1MHZ
Unmeasured pins returned to GND

A.C. Characteristics
Bus Parameters (Note 1)
Read Cycle:
tAR

Address Stable Before READ (CS,

CiiS)

0

ns

Note 2

tAA

Address Hold Time for READ (CS, C/O)

0

ns

Note 2

tAR

READ Pulse Width

250

ns

tRO

Data Delay from READ

tOF

READ to Data Floating

10

200

ns

100

ns

Note 3, CL = 150 pF

Write Cycle:
tAW

Address Stable Before WRITE

0

ns

tWA

Address Hold Time for WRITE

0

ns

tww

WRITE Pulse Width

250

ns

tow

Data Set Up Time for WRITE

150

ns

two

Data Hold Time for WRITE

0

ns

tRY

Recovery Time Between WRITES

6

tev

Note 4

Notes 5, 6

Other Timings:
tev

Clock Period

.320

1.35

ps

t~

Clock High Pulse Width

120

tcv-90

ns

t;j;

Clock Low PUlse Width

gO
186

ns

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

20

ns

1

Jis

tA, tF

Clock Rise and Fall Time

tOTx

TxD Delay from Falling Edge of TxC

tSAx

Rx Data Set-Up Time to Sampling Pulse

2

Jis

tHAx

Rx Data Hold Time to Sampling Pulse

2

JiS

fTx

Transmitter Input Clock Frequency
1X Baud Rate
16X Baud Rate
64X Baud Rate

hpw

hpo

fAx

tAPW

tAPO

hxAOY

5

DC
DC
DC

kHz
kHz
kHz

Transmitter Input Clock Width
1X Baud Rate
16X and 64X Baud Rate

12
1

tCY
tCY

Transmitter Input Clock Pulse Delay
1X Baud Rate
16X and 64X Baud Rate

15
3

tCY
tCY

Receiver Input Clock Frequency
1X Baud Rate
16X Baud Rate
64X Baud Rate

DC
DC
DC

64
310
615

kHz
kHz
kHz

Receiver Input Clock Pulse Width
1X Baud Rate
16X and 64X Baud Rate

12
1

tCY
tCY

Receiver Input Clock Pulse Delay
1X Baud Rate
16X and 64X Baud Rate

15
3

tCY
tCY

TxRDY Pin Delay from Center of last Bit

hxAOY CLEAA TxRDY I from Leading Edge of WR
tAxAOY

64
310
615

RxRDY Pin Delay from Center of last Bit

tAxAOY CLEAA RxRDY I from Leading Edge of RD

TEST CONDITIONS

8

tCy

Note 7

150

ns

Note 7

24

tCY

Note 7

150

ns

Note 7

tiS

Internal SYNDET Delay from Rising
Edge of RxC

24

tCY

Note 7

tES

External SYNDET Set-Up Time Before
Falling Edge of RxC

16

tCY

Note 7

hxEMPTY

TxEMPTY Delay from Center of Data Bit

20

tCY

Note 7

twc

Control Delay from Rising Edge of
WRITE (TxEn, DTR, RTS)

8

tCY

Note 7

tCA

Control to READ Set-Up Time (DSR, CTS)

20

tCY

Note 7

=

NOTES: 1. AC timings m~sured VOH 2.0, \!Qb::. 0.8, and with load circuit of Figure 1.
2. Chip Select (CS) and Command/Data (C/15) are considered as Addresses.
3. Assumes that Address is valid before RDI.
4. This recovery time is for RESET and Mode Initialization. Write Data is allowed only when TxRDY = 1. Recovery Time between
Writes for Asynchronous Mode is 8 tCY and for Synchronous Mode is 16 tCY.
5. The TxC and RxC frequencies have the following limitations with respect to ClK.
For 1X Baud Rate, fTxorfRx:S 11(30 tCY)
For 16X and 64X Baud Rate, fTX orfRx:S 1/(4.5 tCY)
6. Reset Pulse Width = 6 tCY minimum; System Clock must be running during RESET.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
+20

2V

Typical ~ Output
Delay Versus
~ Capacitance (pF)

/

+10

/

-10

Figure 1.

-20
-100

TEST LOAD CIRCUIT

187

/
....

SPEC

/
-50

+50

.<1 CAPACITANCE (pF)

+100

WAVEFORMS

System Clock Input

CLOCK ¢

Transmitter Clock & Data

TxC (lx MODE)

TXC (1SxMODE)

Tx DATA

Receiver Clock & Data

(Ax BAUD COUNTER STARTS HERE)

DATA BIT

START BIT

Rx DATA

"~-~tRPw---1---tAPO~

__

Rxe (1x MODE)
_8A"XCPERtODS-_ _
(16x MODE)

-~16R)(CPERIODS(11'-6-M-O-O-E-I---------11
x

RxC 116x MODEl

tNT SAMPLING
PULSE

188

DATA BIT

Write Data Cycle (CPU --. USART)

TxROY

-~

\J,

i=-;l

I

tT,RDY CLEAR

L:j
1--+ ~b

ViA

tDW

DATA IN (O.B.)

DON'TeARE

os-

~

~

Read Data Cycle (CPU

RxRDV

CS"

USART)

I~'RDYCLEARI
t RR _

~

_I

c/o

+-

\J,

/

lffi

DATA OUT (O.B,)

DON'T CARE

,

i-;;;
F

c/o

tWD

DATA STABLE

DATA FLOAT

l~tRD
I

-

1

l - tDF
DATA FLOAT

DATA OUT ACTIVE

~~

.~
~

4-

Write Control or Output Port Cycle (CPU --. USART)

X

OTR, RTS
(NOTE #1)

t-tww-jC tWC::..j

1-----J1

ViA

l - t D W - : : i tWD
,

DATA IN (D.B.)

I~
c/o

os

tAW

/I
l~tAW

'4

---:"L

tWA

'K

i----l,ty

wA

NOTE:t:l: Twc INCLUDES THE RESPONSE TIMING OF A CONTROL BYTE.

189

Read Control or Input Port (CPU ..... USART)
OSR,CTS
(NOTE #11

----------~~------------------------------------

1~ --+1 ~
'CR

'RR-I

~=

RO

~
DATA OUT
(O,B,)

-I 'AR

ilI'----

I-'RO

-

-

I-'OF

-

-I

r--

'RA

L-

CIO __________________j iii

'AR -

-

I---

'RA

~ --------------,~L_ _ _ _ _ _ _~y_____
NOTE #1; TCR INCLUDES THE EFFECT OF

ffi ON THE TxENBL CIRCUITRY.

Transmitter Control & Flag Timing (ASYNC Mode)

'TxEMPTY

11}-----~

Tx EMPTY

I'------+---~

Tx READY
(STATUS BITI

Tx READY
(PIN)

CID
WrSBRK

Ix DATA
DATA CHAR 1

DATA CHAR 2

-e..-NMOIItItlID

DATA CHAR 3

!::: tfATA CHAR 4

~:

iii

g

~~

I;; c

EXAMPLE FORMAT = 7 BIT CHARACTER WITH PARITY & 2 STOP BITS.

I-

.,

Receiver Control & Flag Timing (ASYNC Mode)
~

BREAK DeTECT

- r:-

OVERRUN ERROR
ISTATUSBlT)

R"RDY

r---

~
tRIIRDV

CHAR 2

LOST

1,--

f----

RdDATA

C/O
WrERR

--drRIIEnl

"d

W. RIIEn

V

DATA CHAR 1

~

wrRII~

--v-

~

~
AKOATA

V

~~
DATA CHAR 2
DATA CHAR 3

EXAMPLE FORMAT = 7 BIT CHARACTER WITH PARITY & 2 STOP BITS

190

>--<>-"NI')"Ll'I~

BREAK

Transmitter Control & Flag Timing (SYNC Mode)

-------.

f-I'L-

THREADV
(STATUS BIT)

THREADY
(PIN!

WrDATA
CHARJ

~2
DA;~

SV!C\
CHAR 1

DATA
CHAR2

CHAR 1

"" "il"""
~

WrCDMMAND
SBRK,

I

WrDATA ,W,DATA

...

~
'L

~

r-

II

c/o

EXAMPLE FORMAT

r-

1

_~'LMARKING STATE

~

n..
j

"j

0,,3'

WrDATA
CHAR4

SVNCCHAR2

...

a'

2

J'

C~~TRA~

AT:\
CHARJ

...

0"

W,DATA

wrcoMMA1!

J'

...

a' 2 3 '

~5I~~

MARKING
STATE

...

SPACING
STATE

MAR
STATE

DATA
CHAR ~
0"3'

SYNC
CHAR

...

0'

no

2

3,

... " ..

5 BIT CHARACTER WITH PARITy' 2 SYNC CHARACTERS

Receiver Control & Flag Timing (SYNC Mode)

SVNDET
(PIN! NOTE 1
'IS---+
SVNDET IS,B!

-

.~TE·.!....J

tES_

OVERRUN
ERROR IS,BI

c/o

r-----<

''---

,---

~

~

(t:Ls

--.i'f!rRHEn'
EH'

Rd DATA
CHAR 1

Rd DATA
CHAR 3

-V
DON'T
CARE
Rx DATA

0-

.~

-RdSTATUS

Rd:rT::~S

r--

\...

Rd SYNC
CHAR 1

RdDATA

L

SYNC
CHAR 1

SYNC
CHAR2

." ','J." •• , , • ;."X' , , ,
T [1 I I fTTTTTT I

DATA
CHAR'
co,

l[J
CHAR 2

>--DATA
CHAR3

2 3 ' cO 1 2 3 ' cD'

~CHARASsn,1,JsT

23'

'TTTTT

\C'i\..i \,J
CHAR 1

COl

2

SYNC CHAR 2

>X' CO, 23'

• , , , "x- -

LEXIT HUNT MODE
SET SYNC DET

HD 1 2 3 '

/

EXIT HUNT MODE)
SET SYN Del (STATUS BIT)

INTERNAL SYNC, 2 SYNC CHARACTERS, 5 BITS, WITH PARITY
EXTERNAL SYNC, 5 BITS, WITH PARITV

191

DATA \..
CHAR 2

DATA
CHAR'

DON'T CARE

JUl

Jlf\I1Jlf
NOTE·'

c--

fu

C,OX, 2 "

CHAR ASSY
BEGINS

1JUl

I~

.

M

SET SVNDET (STATUSBITf'

ETC,

,X

APPLICATION OF THE COM8251A

Asynchronous Serial Interface to CRT Terminal,
DC to 9600 Baud

Synchronous Interface to Terminal or Peripheral Device

SYNCHRONOUS

TERMINAL
OR PERIPHERAL

OEVICE
SYNDET

Asynchronous Interface to Telephone Lines

Synchronous Interface to Telephone Lines

PHONE

PHONE

D'i"R
COM82S1A

rn

LINE

LINE
INTER

INTER·

FACE

SYNC

FACE

MODEM

ill

1

TELEPHONE
LINE

COM8251A Interface to IlP Standard System Bus

.,

ADDRESS BUS

CONTROL BUS
110 R

i70Wl RESET

DATA BUS

e/fi

a-

17
°1--00

Ifij"

WR

RESET

elK

COMI251A

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is

~~~~~:~~~~~7b~d~~~:Tcie~~;t~~de~;~e ~a~~~~~f~~:t~~~~OC6~6\~~~s~SV~c}~:s~~;~~~~:rr~~~ros~~~~6~~~~~~

at any time in order to improve design and supply the best product possible.

192

COM82586
PRELIMINARY

Ethernet™Local Area Network
Coprocessor
FEATURES
o Performs Complete CSMA/CD Medium
Access Control Functions
Independently of CPU
-High Level Command Interface
o Supports Established LAN Standards
-IEEE 802.3/EtherneFM (10BASE5)
-IEEE 802.3/Cheapernet (10BASE2)
-IBM PC Network
-IEEE 802.3/StarLAN (1BASE5)
-Proprietary CSMNCD Networks up
to 10 Mbps
o On-Chip Memory Management
-Automatic Buffer Chaining
-Buffer Reclaim After Receipt of Bad
Frames
-Save Bad Frames, Optionally
o Interfaces to 8-bit and 16-bit
Microprocessors
o Supports Minimum Component
Systems
-Shared Bus Configuration
-Interface to IAPX 186 and 188
Microprocessors without Glue
o Supports High Performance Systems
-Bus Master, with On-Chip DMA
-5 MBytesiSec Bus Bandwidth
-Compatible with Dual Port Memory
-Back to Back Frame Reception at 10
Mbps
o 48 Pin DIP and 68 Pin PLCC

PIN CONFIGURATION

~~~31W~~~2625~232221~191B

NC
AD5
ADs
AD?,
ADa
AD9
Vss
Vss

35
36
37
38
3CJ
40
1\1
42

17

NC

MN/MX
RST

Vss
V'l5
ADm
NC
NC

43
44
4.,
46
47

5

RDY (ALE)

AD" [

48

4

AD,2
AD!]

49
50

3

00 (DEN)
51 (OT/A)

Vee
ARDYISRDY
INT

,
2

~(~

52~5455565758~OO6'~~M~~~~

~~§~~1tJ~~~~I~I~~~
,.
:=.m.....

.NY1""

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
I!Pplications: consequentty complete information sufficient for construction purposes is not necessarily given.
The Information has been carefully checked and is believed to be entirely reliable. However, no responslbllitv Is
assumed for inaccuracies. Furthermore, such information does not convey to the urchaser of ·the
semiconductor devices described any license under the patent rights of $MC or others. ~MC reserves the
right to make changes at any time In order to improve deSign and supply the best product possible.

196

COM82C501
PRELIMINARY

Ethernet™Serial Interface
FEATURES

PIN CONFIGURATION

o Direct Replacement for Intel 82501
and 82C501, or SEEQ 8023A
o Compatible with IE!:E 802.3 10BASE5

o

o
o
o
o
o
o

o
o
o

(EtherneFM) and 10BASE2 (Cheapernet)
Specifications
10 Mbps Operation
Replaces 8 to 12 MSI Components
Manchester Encoding/Decoding and
Receive Clock Recovery
10 MHz Transmit Clock Generator
Drives/Receives IEEE 802.3
Transceiver Cable (AUI)
Defeatable Watchdog Timer Circuit to
Prevent Continuous Transmissions
Diagnostic Loopback for Network Node
Fault Detection and Isolation
Direct Interface to the COM82586 LAN
Coprocessor and COM82C502 Transceiver
Low Power CMOS
+5 Volt Only Operation

ENETV1 ~ 1

20 Pvec

NOOFH 2

19pTRMT

LPBKlWDTD [ 3

18p TRMT

RCV [ 4

17P TXD

ReV [ 582C50116P,TxC
CRS [ 6
15p'TEN
CoT[ 7

14J X1

RXC[ 8

13JX2

RXD[ 9

12 J CLSN

GND [ 10

11 J CLSN

Package: 20·pin DIP

GENERAL DESCRIPTION
The COM82C501 EtherneFMSeriallnterface(ESI) chip is
designed to work directly with the COM82586 LAN
Coprocessor in IEEE 802.3 (10BASE5 and 10BASE2), 10
Mbps, Local Area Network applications. The major
functions of the COM82C501 are to generate the 10 MHz
transmit clock for the COM82586, perform Manchester
encoding/decoding of the transmitted/received frames,
and pro'>(ide the electrical fnterface to the EtherneFM
transceiver cable (AU I). Diagnostic loopback control
enables the COM82C501 to route the signal to be

transmitted from the COM82586 through its Manchester
encoding and decoding circuitry and back to the
COM82586. The combined loopback capabilities of the
COM82586 and COM82C501 result in efficient fault
detection and isolation by providing sequential testing of
the communications interface. An on-chip watchdog timer
circuit (defeatable) prevents the station from locking up in
a continuous transmit mode. The COM82C501 is socket
compatible with the bipolar Intel 82501, the Seeq 8023A,
and the CMOS Intel 82C501.

Ethernet™ is a trademark of the Xerox Corporation.

197

a2986

Vee

.IN TERFACE

GND

TRANSCEIVER CABLE
INTERFACE

I

I

COLLISIONPRESENCE
GENERATION

XCVR CABLE
INTERFACE &
NOISE FILTER

CLSN

I

\

\

/

I
\

-

~
l

RXD

CARRIER-PRESENCE GENERATION

1

/-

XCVR.CABLE
INTERFACE AND
NOISE FILTER

+2 COUNTER

CLOCK
GENERATION

TXD

.----

TRANSCEIVER
CABLE DRIVER

I

J

J

MANCHESTER
DECODER AND
CLOCK
RECOVERY

MANCHESTER
ENCODER

\

I
WATCHDOG
TIMER

,

\
\

RCV

I

\

,_/'
X,

~CRYSTAL
X2
\

I

I

I

\

-

TRMT

,
\

/

LPB

FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION OF PIN FUNCTIONS
NAME
Ethernet
Version 1.0

SYMBOL
ENETVl

2

Carrier Sense Option

NOOR

3

Loopback/Watchdog
Timer Disable

LPBKI
WDTD

4
5

Receiver Pair

RCV
RCV

PIN NO.
1

FUNCTION
An active low, MOS-Ievel input. When ENETVl is asserted, the
TRMT/TRMT pair remains at high differential voltage at the end of
transmission. This operation is compatible with the Ethernet Version
1.0 specification. If the ENETVl pin is left floating, an internal pullup resistor biases the input inactive high.
An active low, MOS-Ievel input. When NOOR is asserted a valid
~al on the COllision-fQoence pa~SN/CLSN) will not force
active low. With N R active
can only be assert~g~
the presence of valid data bits on the RCV/R(W pair. If the
pin is floating, an internal pull-up resistor biases the input
inactive high.
An active low, TIL-level control signal enables the loopback mode.
In loopback mode serial data on the TXD input is routed through
the 82C501 internal circuits and back to the RXD output without
driving the TRMTITRMT output pair to the transceiver cable. During
loopback CDT is asserted at the end of each transmission to
simulate the SOE test.
An input voltage of 12V ± 10% through a 4 KO resistor will disable
the on-chip watchdog timer.
A differentially driven input pair which is tied to the receive pair of
the Ethernet transceiver cable. The first transition on RCV will be
negative-going to indicate the beginning of a frame. The last
transition should be positive-going to indicate the end of the frame.
The received bit stream is assumed to be Manchester encoded.

198

PIN NO.
6

NAME

SYMBOL

FUNCTION

Carrier Sense

CRS

7

Collision Detect

COT

8

Receive Clock

RXC

9

Receive Data

RXD

10

Ground

GND

12

Collision Pair

CLSN
CLSN

A differentially driven input pair tied to the collision-presence pair of
the Ethernet transceiver cable. The collision-presence signal is a
10 MHz square wave. The first transition at CLSN is negativegoing to indicate the beginning of the signal; the last transition is
positive-going to indicate the end of the signal.

14
13
15

Clock Crystal
Transmit Enable

X,
X2
TEN

16

Transmit Clock

TXC

17

Transmit Data

TXD

19
18

Transmit Pair

TRMT
TRMT

20 MHz crystal inputs. When X2 is floated, X, can be used as an
external MOS level input clock.
An active low, TTL level signal synchronous to TXC that enables
data transmission to the transceiver cable and starts the watchdog
timer. TEN can be driven by the RTS from the COM82586.
A 10 MHz MOS level clock output with 5 ns rise and fall times. This
clock is connected directly to the TXC input of the COM82586.
A TTL-level input signal that is directly connected to the serial data
output, TXD, of the COM82586.
A differential output driver pair that drives the transmit pair of the
transceiver cable. The output bit stream is Manchester encoded.
Following the last transmission, which is always positive at TRMT,
the differential voltage is slowly reduced to zero volts in a series of
steps. If ENETVI is asserted this voltage stepping is disabled.

20

Power Supply

Vee

11

An active low, MOS-Ievel output to notify the COM82586 that there
is activity on the coaxial cable. The signal is asserted when valid
data or a collision-presence signal from the transceiver is present.
It is deasserted at the end of a frame; or when the end of the
collision-presence signal is detected, synchronous with RXC. After
transmission, once deasserted, CRS will not be reasserted again
for a period of 5 /lS minimum or 7 /lS maximum, regardless of any
activi~the collision-presence signal (CLSN/CLSN) and
RCV/RCV inputs.
An active-low, MOS-Ievel signal which drives the COT input of the
COM82586 controller. It is asserted as long as there is activity on
the collision pair (CLSN/CLSN), and during SQE (heartbeat) test
in loopback.
A 10 MHz MOS level clock output with 5 ns rise and fall times. This
output is connected to the COM82586 receive clock input RXC.
There is a maximum 1.2 /lS delay at the beginning of a frame
reception before the clock recovery circuit gains lock. During idle
(no incoming frames) RXC is forced low.
A MOS-Ievel output tied directly to the RXD input of the COM82586
controller and sampled by the COM82586 at the negative edge of
RXC. The bit stream received from the transceiver cable is
Manchester decoded prior to being transferred to the controller.
This output remains high during idle.
Reference.

+5V ± 10%.

199

NOTE: For an updated data sheet please fill out the reply card in
the back of this catalog or call SMC at (516) 273-3100.
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications: conse·
quently complete information sufficient for construction purposes is not necessarily given. The information has been carefully
checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such
information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of
SMC or others. SMC reserves the right to make changes at any time in order to improve design and supply the best product
possible.

200

COM82C502
PRELIMINARY

EthernefMTransceiver Chip
FEATURES

o

Conforms to the Following Standards:
-IEEE 802.3, 10BASE5 (Ethernet'M)
-IEEE 802.3, 10BASE2 (Cheapernet)
-EtherneFM Version 2.0

o

Jabber Function

o

Receive Based Collision Detection

o

Defeatable Signal Quality Error
(Heartbeat) Test

o
o
o
o

PIN CONFIGURATION

REXT [
TRMT

~

TRMT

~

:~:~

CLSN

CLSN
Vss

Requires Minimum Board Space
-On-Chip Voltage Reference
-16 Pin DIP

1
2
3
4
5
6

~ 7

a

'-'

16
15
14
13
12
11
10

9

~~
~
~

VDD
RTSO

CXRD
HBD

AVec
AVss

Package: 16-pin DIP

No External Adjustments Required
Low Power CMOS
Direct Replacement for Intel's 82502

GENERAL DESCRIPTION
The COM82C502 EtherneFM Transceiver Chip is a CMOS
LSI device that provides the complete set of transmit,
receive and collision detection functions specified by the
IEEE 802.3, 10 BASE5 (EtherneFM) and 10BASE2
(Cheapernet) 10 Mbps baseband standards for the Media
Attachment Unit (MAU). The COM82C502 teams up the
COM82586 CSMA/CD LAN Coprocessor and the
COM82C501 EtherneFM Serial Interface enabling the
designer to implement highly integrated IEEE 802.3
systems.
Three basic functional blocks make up the COM82C502:
transmit, receive and collision detection. The transmit and
receive sections transfer data from the transceiver drop

(Access Unit Interface or AUI) cable to the coaxial cable
of the network and vice-versa. The collision detection
section senses simultaneous transmissions by two or more
network stations (collisions) on the coaxial cable and
reacts by sending a 10 MHz signal across the transceiver
drop cable to the station that it front ends.
When used in an Ethernet™ application, the COM82C502
can drive a transceiver cable up to 50 meters in length
(for Cheapernet, there is no transceiver cable). The
COM82C502 provides all active communications circuitry
for the transceiver function in the Ethernet'M Cheapernet
environment. It is an ideal companion to the COM82C501.

201

TRANSCEIVER
CABLE
INTERFACE

·COAX CABLE
INTERFACE

TRMT
TRMT

CXTD

HBD-t:-;~---i

CLSN

CLSN
CXRD

RCV
RCV

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION OF PIN FUNCTIONS
NAME

SYMBOL

FUNCTION

PIN NO.
2
3

Transmit Data
Pair

TRMT,
TRMT

A differentially driven input tied to the transmit pair of the transceiver
cable. The transmit pair of the transceiver cable is driven with 10
Mbps Manchester encoded data from the serial interface of the
data link (82501). TRMT/TRMT must be isolated from the
transceiver cable by a pulse transformer. The last transition is
expected to be positive indicating end of packet.

4
5

Receive Data
Pair

RCV,
RCV

An output driver pair that generates an ECl AC signal level to drive
the transceiver cable receive pair with the 10 Mbps Manchester
encoded data received from the coaxial cable of the network.
RCV IRCV must be isolated from the transceiver cable by a pulse
transformer. The last transition is always positive indicating the end
of the packet. The current from the RCV pin is incrementally
decreased after the last transition.

7
6

Collision
Presence Pair

ClSN,
ClSN

An output driver pair that generates a 10 MHz ECl AC signal level
square wave on the collision presence pair of the transceiver cable
when: a collision is detected 011 the coaxial cable of the network,
during self-test as the collision circuit heartbeat indication, or after
the watchdog timer has expired to indicate that the coaxial cable
transmitter is disabled.

15

Coaxial Cable
Transmit Data

CXTD

An output pin that transmits data onto the coaxial cable of the
network by sinking current from the center conductor of the coaxial
cable. The last data transition at the end of a packet is always low
to high.

12

Coaxial Cable
Receive Data

CXRD

An input pin that receives data from the coaxial cable of the
network. Typical signal levels (referenced to Voo) received on
CXRD are -200 mV for high, -1.8V for a low and OV during idle.
The last data transition received is expected to be positive
indicating the end of packet.

202

DESCRIPTION OF PIN FUNCTIONS
PIN NO.
11

NAME
Heartbeat Disable

SYMBOL
HBD

FUNCTION

1

External Resistor

REXT

A 2430 0.5% resistor is attached between REXT and ground (Vss)
to provide precision internal current levels.

13

Redundant Transmit
Squelch

RTSQ

16

Power Supply

Vee "

An open drain output that indicates the operational state of the
82502 transmitter. The output can be used to provide a redundant
method of disabling the transceiver (MAU) transmitter for greater
network reliability.
+5 ± 10% volts.

8
14
10

Ground
Power Coax Shield
Analog Power

Vss "
Vee "
AVee "

g

Analog Ground

AVss "

A strapping option that when tied low (Vss), allows the transceiver to
generate a collision detect heartbeat signal after each packet. A
high (Vee) on this pin disables the heartbeat circuitry as well as the
6.4 /1S transmit inhibit timer but keeps the collision circuit enabled
for use in repeater applications.

GROUND
+10 ± 10% volts.
+5 ± 10% volts. Included to reduce the effects of the current
fluctuations in the Vee pin.
Included to reduce the effects of current fluctuations in the Vss pin.

"NOTE:
These voltages are referenced to Vss. The shield of the coaxial cable of the Ethernet™channel (Voo) is connected to earth ground.

Design Example
POWER PAIR

1~-+~~----~~~~~--------~--------~

O.D1ILF

soo
TRANSCEIVER CABLE SHIELD

ETHERNET
COAX

0.D1f).F,2KV

TRANSMIT PAIR

: 8 ·ill
:8
:8
RECEIVE PAIR

COLLISION PAIR

2

•

Voo

TRMT

14

0.22ILF~

78!l
TRMT

5V
COM82C502
43.2U
4

CXTD

RCV
CXRD

15

12

RCV
RTSQ
43.211
7

6

13

1001'1
FUSIBLE
1/8W

CLSN
HBD

11

CLSN

NOTES:
1. Pulse transformer indUctance 2':50 pH, typically 75pH
2. Isolated power supply: Pulse Engineering Inc. part no. PE·64369
Reliability Inc. part nos. 2E12R10·5, 2VA12U10-5, and 2VA5U10-5.
3. Isolated power supply may require additional decoupling on its inputs and outputs.

Typical10BASE5 (Ethernet™) Transceiver Implementation Using the COM82C502.

203

COTE

LTRANSCEIVER
TAP BOX

IEEE 802.3 10 Base 2 (Cheapernet):
This configuration supports 30 users per
segment, each segment being 185 meters long.

NETWORK COAXIAL CABLE

IEEE 802.3 10 Base 5 (Ethernet):
This configuration supports 100 users per
segment, each segment b~ing .500 meters long.

NOTE: For an updated data sheet please fill out the reply card in
the back of this catalog or call SMC at (516) 273-3100.
EthernetrM is a trademark of Xerox Corporation.

SJ~~~~~ ~H~~~~~= Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor appli·

;.

cations: consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore. such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights 'of SMC or others_ SMC reserves the right to
make changes at any time in order to improve design and supply the best product possible.

204

COM 9026

Local Area Network Controller
LANCTM
FEATURES

o 2_5 M bit data rate
o ARCNET® local area network controller
o Modified token passing protocol
o Self-reconfiguring as nodes are added
or deleted from network
o Handles variable length data packets
o 16 bit CRC check and generation
o System efficiency increases with
network loading
o Standard microprocessor interface
o Supports up to 255 nodes per network
segment
o Ability to interrupt processor at
conclUSion of commands
o Interfaces to an external 1K or 2K
RAM buffer
o Arbitrates buffer accesses between
processor and COM 9026
o Replaces over 100 MSI/SSI parts
o Ability to transmit broadcast messages
o Compatible with broadband or baseband
systems.
o Compatible with any interconnect media

PIN CONFIGURATION

~IO
.('0;5

I~ ~
~u!zoool;>
0

_

ET2
CA
ET1
TEST2
TEST1

•

-_«w_«I~
~I ~n°
ll! ll! C/l<
Q::O

ll! !::I!!!I!!!
~ < 5!
0

PACKAGE: 44-pin PLCC

1...1

N/C
AD,
AD,
AD,
AD,
AD,
GND
CLK
ILE
WE
DE

BWR
RiW
IOAEO
MAEO
AS
AEO
WAIT
Ai[
ADIE

BE
WE
iIT
ClK
GND

.....,

8

40
39
38
37
36
35
34
33

10
9
0
11
12
13
14
15
16
17
18
19
20

32
31
30
29
28
27
26
25
24
23
22
21

1
2
3
4
5
6
7

POA
VC~

Ai(

'fX
DSYNC
AS
IDDAT
IDlD
A9
A10
ECHO
INTA
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7

PACKAGE: 40-pin DIP

o Arbitrary network configurations can be used
(star, tree, etc_)
o Single + 5 volt supply

(twisted pair, coax, etc_)

GENERAL DESCRIPTION
The COM 90C26 is a special purpose communications
adapter for interconnecting processors and intelligent
peripherals using the ARCNET local area network_ The
ARCNET local area network is a self-polling "modified token
passing" network operating at a 2_5 M bit data rate_ A "modified token passing" scheme is one in which all token passes
are acknowledged by the node accepting the token_ The
token passing network scheme avoids the fluctuating channel access times caused by data collisions in so-called
CSMAlCD schemes such as Ethernet
The Com 90C26 circuit contains a microprogrammed sequencer and all the logic necessary to control the token
passing mechanism on the network and send and receive
data packets at the appropriate time_ A maximum of 255
~odes may be connected to the network with each node
being assigned a unique ID_

The COM 9OC26 establishes the network configuration, and
automatically re-configures the network as new nodes are
added or deleted from the network. The COM 90C26 performs address decode, CRC checking and generation, and
packet acknowledgement, as well as other network management functions_ The COM 90C26 interfaces directly to
the host processor through a standard multiplexed addressl
data bus.
An external RAM buffer of up to 2K locations is used to hold
up to four data packets with a maximum length of 508 bytes
per message_ The .RAM buffer is accessed both by the processor and the COM 90C26_ The processor can write commands to the COM 9OC26 and also read COM 90C26 status.
The COM 90C26 will provide all signals necessary to allow
smooth arbitration of all RAM buffer 9perations.
ARCNET" is a'registered trademark of the Datapolnt Corporation.

205

ii;;;i!;

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
applications: consequently complete information sufficient for construction purposes is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the best product possible.

206

COM90C26
PRELIMINARY

Local Area Network Controller
LANCTM
FEATURES

o 2.5 M bit data rate
o ARCNET® local area network controller
o Modified token passing protocol
o Self-reconfiguring as nodes are added
or deleted from network
o Handles variable length data packets
o 16 bit CRC check and generation
o System efficiency increases with
network loading
o Standard microprocessor interface
o Supports up to 255 nodes per network
segment
o Ability to interrupt processor at
conclusion of commands
o Interfaces to an external 1K or 2K
RAM buffer
o Arbitrates buffer accesses between
processor and COM 90C26
o Replaces over 100 MSI/SSI parts
o Ability to transmit broadcast messages
o Compatible with broadband or baseband
systems
o Compatible with any interconnect media
(twisted pair, coax, etc.)
o Low power CMOS technology

PIN CONFIGURATION

~IO
I~ ---<'-__
>---<

C~O;....M....:9_'_OC;:,,:2_'_6....
HI_A;;;.DD"_'R_~~I~------

HI ADDR

I A D 7 - 0 - - - - - - - - - - !t~RAMDOUT

r

WAIT _ _ _ _ _ _...J
AD IE

1

COM90C26
LOW ADDR

)

\

H

!~

It

l~
OE-------~\l

ATE - - - - - - - - 1

t~

~l

I

\

'--;1

\

I

\

~l

n

I

FIGURE 5-PROCESSOR READ RAM FOLLOWED BY COM 90C26 READ RAM
213

and driven out via the logic function RD ended with REQ.
For ~rocessor I/O read cycles from the COM 90C26, ADIE
and AlE are used to enable the processor address into the
COM 90C26. Data out of the COM 90C26 is gated through
the transparent latch and appears on the processor's data
bus with the same control signals used for RAM read cycles;
For processor write cycle~fter the falling edge of C. the
COM 90C26 produces a WE (write enable) output to the
RAM buffer, and the IlE output from the COM 90C26 allows
the processor data to source the interface address/data bus
(IAD7-IADO). At this time the COM 90C26 waits for DWR
before concluding the cycle by removing the WAIT output.
DWR should only be used if the processor cannot deliver
the data to be written in enough time to satisfy the write setup
time requirements of the RAM buffer. By delaying the activation of DWR, the period of the write cycle will be extended
until the write data is valid. Since the architecture and operation of the COM 90C26 requires periodic reading and writing ofthe RAM buffer in a timely manner, holding the DWR
input off for a long period of time, or likewise by running the
processor at a slow speed, can result in a data overflow
condition. It is therefore recommended that ifthe processor
write data setup time to the RAM buffer is met, then the DWR
input should be grounded.
For processor I/O write cycles to the COM 90C26, ADIE and
AlE are used to enable the processor's address onto the
interface data bus. IlE is used to enable the processor's
write data into the COM 90C26. Delaying the activation of
DWR will hold up the COM 90C26 cycle requiring the same
precautions as stated for Processor RAM Write cycles.

As stated previously, processor requests occur atthe falling
edge of AS if either 10REQ or MREQ are active. COM 90C26
requests occur when the transmitter or receiver need to read
or write the RAM buffer in the course of executing the command. If the COM 90C26 requests a bus cycle at the same
time as the processor, or shortly after the processor, the
COM 90C26 cycle will follow immediately after the processor cycle. Figure 5 illustrates the timing relationship of a
Processor RAM Read cycle followed by a COM 90C26 RAM
. read cycle. Once the AS signal captures the processor
address to the RAM buffer and requests a bus cycle, it takes
4 ClK periods for the processor cycle to end. Figure 5, breaks
up these 4 ClK periods into 8 half clock interval labeled 1P
through 8P. A COM 90C26 access cycle will take 5 ClK
periods to end. FigureS breaks up these 5 ClK periods into
10 half intervals labeled 1C through 10C.
If a processor cycle request occurs after a COM 90C26
request has already been granted, the COM 90C26 cycle
will occur first, as shown in figure 5. Figure 6 illustrates the
timing relationship of a COM 90C26 RAM Write cycle followed by a Processor RAM Write cycle. Due to the asynchronous nature of the bus requests (AS and ClK), the
transition from the end of the COM 90C26 cycle to the
beginning of the processor cycle might have some dead
time. Refering to figure 6, if AS falling edge occurs after the
start of half ClK interval 9C, no real contention exists and
it will take between 200 and 500 nanoseconds before the
processor cycle can start. The start of the processor cycle
is defined as the time when the COM 90C26 produces a
leading edge on both ADIE and AlE. If the processor request

ClK
AS ____~r----\L_______________________________4I.~
PA 15-8

:::=======~X.(-:::C~Hc:!.11A-;:CD:::D~R~-=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=-~tI-~-----'L _ _ _ __

PAD7-0 _ _ _ _

_'l lO ADDR XPROCESSOR WRITE DATA

X'------l::==x:::::::=

RWMREQ _ _ _~\~\\~\~_ _L'ZUZ~_______________~~~
REQ _ _ _ _ _ulnZ~ZZ.------------------------------------~I~

-....J'

1I

)

II

\L__________________
IA1O-8

---<

COM 90C26 HI ADOR

>----<

HI ADDR

WAIT __________,

\

ADIE.AIE--------------,\'___________~,

II
II

I-----.\~__________~~~________~lr----~l~l-----\~

____Jlr----------,\'_ _____',

II
II

ILE

FIGURE 6-COM 90C26 WRITE RAM FOLLOWED BY PROCESSOR WRITE RAM
214

BIT 2 (RECON) set to a logic "0".
BIT 1 (TMA) set to a logic "0".
BIT 0 (TA) set to a logic "1".

occurs before the end of half ClK interval5C (figure 6 illustrates this situation), then the processor cycle will always
start at half ClK interval 1P. The uncertainty is introduced
when the processor request occurs during half ClK intervals 6C, 7C or ac. In this case, the processor cycle will start
between 200 and 500 nanoseconds later depending on the
particular timing relation between AS and ClK. The maximum time between processor request and processor cycle
start, which occurs when the processor request comes just
after a COM 90C26 request, is 1300 nanoseconds. It should
be noted that all times specified above assume a nominal
ClK period of 200 nanoseconds.

In addition the DSYNC output is reset inactive high and the
interrupt mask register is reset (no maskable interrupts
enabled). Page 00 is selected for both the receive and the
transmit RAM buffer. After the paR signal is removed, the
COM 90C26 will generate an interrupt from the nonmaskable Power On Reset interrupt. The COM 90C26 will start
operation four CA clock cycles after the paR signal is
removed. At this time, the COM 90C26, after reading its ID
from the external shift register, will execute two write cycles
to the RAM buffer. Address 00 HEX will be written with the
data D1 HEX and address 01 HEX will be written with the
ID number as previously read from the external shift register. The processor may then read RAM buffer address 01
to determine the COM 90C261D. It should be noted thatthe
data pattern D1 written into the RAM has been chosen arbitrarily. Only if the D1 pattern appears in the RAM buffer can
proper operation be assured.

Figures 7 and a illustrate timing for Processor Read COM
90C26 and Processor Write COM 90C26 respectively.
These cycles are also shown divided into a half clock intervals (1P through ap) and can be inserted within figures 5
and 6 if these processor cycles occur.

POWER UP AND INITIALIZATION
The COM 90C26 has the following power up requirements:
1-The paR input must be active for at least 100
milliseconds.
2-The ClK input must run for at least 10 clock cycles before
the paR input is removed.
3-While paR is asserted, the CA input may be running or
held high. If the CA input is running, paR may be
released asynchronously with respect to CA. If the CA
input is held high, paR may be released before CA
begins running.

CLOCK GENERATOR
The COM 90C26 uses two separate clock inputs namely
CA and ClK. The ClK input is a 5 MHz free running clock
and the CA input is a start/stop clock periodically stopped
and started to allow the COM 90C26 to synchronize to the
incoming data that appears on the RX input.
Figure 9 illustrates the timing of the CA clock generator and
its relationship to the DSYNC output and the RX input. The
DSYNC output is used to control the stopping of the CA clock.
On the next rising edge of the CA input after DSYNC is
asserted, CA will remain in the high state. The CA clock
remains halted in the high state as long as the RX signal
remains high. When the RX signal goes low, the CA clock
is restarted and remains running until the next falling
edge of DSYNC. (See figure 10 for an implementation of
this circuit.)

During paR the status register will assume the following
state:
BIT 7 (RI) set to a logic "1".
BIT 6 (ETS2) not affected
BIT 5 (ETS1) not affected
BIT 4 (PaR) set to a logic "1".
BIT 3 (TEST) set to a logic "0".

CLK~~

CLK~

AS~~!------------------­
PA1S-8 ~

PAD7-0

-===x

LOW ADOR

PA1S-8

x:=:!~PROCESSOR WRITE DATA

rrr-:

R Vi IDREO -----s\S\

AS~~!--------------------

II

HI ADDR

PA07-0

1

~

-===x

:I-~l___________________

HI AODR

LOW ADDR

x:=:!~PROCESSOR

WRITE DATA

~~l--------RWiOREO_-----s\S\~~____~UL
_____________________

\'~l--------------~r---

wR------\,~l-------~r--­

REo----1..1.1..ln"TT""------ll~1- - - - - - - - -

REo----1..1.1..l17Tr-------lll-l- - - - - - - - - - - - - - - - - - -

WR

IAlO·8

-------------4n--.

~

74lS166

~

I II I I I II
SWITCH

20 MHZ
SQUARE
WAVE
Fiber Optic Driver
Raycom Systems
6395 Gunpark Drive
Boulder, Colorado 80301
"COM91C32 - Improved local Area Network
Transceiver is also compatible
with the COM 9026/90C26.
See page 247

FIGURE 2-COM90C32 SYSTEM INTERFACE

,.
'1

"'

DESCRIPTION OF PIN FUNCTIONS
(Refer to figure 2)
COM 9026/COM 90C26 INTERFACE
PIN NO.
1,2

NAME
PULSE 2
PULSE 1

SYMBOL
PULS2
PULS1

3

BLANK

BLNK

10

RECEIVE IN

RXIN

11

RECEIVE
OUT
DELAYED
SYNC
CA

12
13
14
15

TRANSMIT
DATA
TRANSMIT
INHIBIT

RXOUT
DSYNC
CA
TX
INHTX

FUNCTION
PULS2 and PULS 1 are two nonoverlapP-iOl negative pulses which occur every
time the TX input is pulsed. PULS2 and P LS1 are used to feed an external
driver as shown in figure 2.
When used with the circuitr~ shown in figure 2, this output should be left
unconnected. The timing 0 this signal is shown in figure 4.
This input is the recovered receive data from the network. For each dipulse
appearing on the network, the comparator shown in figure 2 will produce a
positive pulse which directly feeds this input.
This output is the NRZ data generated as a function of the RXIN ~ulse waveform
which directly feeds the RX input of the COM9026/COM90C26, pin 38).
This active low input, which is asserted by the COM9026/COM90C26, will halt
the CA clock output.
This output is a 5 MHz start/stop clock that is halted when DSYNC goes active
low and restarted by a low signal on the RXOUT output. This clo<;i< is capable of
driving 70 pf plus one LS load with 20 nanoseconds rise and fall times.
This input, which is asserted by the COM9026/COM90C26, is the serial data
transmitted by the node.
This active low input inhibits the TX signal from initiating transmit signals ~
forcing PULS1 and PULS2 to a high and BLNK to a low. This signal shaul be
asserted during a power on reset condition.

SYSTEM CLOCK INTERFACE
PIN NO.
4

5

NAME
CPU CLOCK

CLOCK
SELECT

SYMBOL
CPUCLK

CKSEL

FUNCTION
This output is a 4 MHz free running clock capable of drivin~ 130 pf with 30
nanosecond rise and fall times. It is identical to the TlLCL input when CKSEL is
high. When CKSEL is low, this output becomes the inversion of the signal that is
fed into the TTLCLK input.
This input selects the clock interface option for the TTLCLK and CPUCLK. When
this signal is high, both the TTLCLK and CPUCLK are identical 4 MHz free
running clock outputs which areveenerated from the 20 MHz input clock (OSC) via
a divide by 5 frequenc divider. hen this input is low, the TTLCLK pin becomes
an input and the CPU LK output will produce the inversion of the Signal
appearing on TTLCLK input.
This ~in can be either an inEut or an output dependinR"on the state of the
CKS L input. When CKSE is high, a free running 4 Hz clock is ouput. When
CKSEL is low, the pin becomes an input which drives an inverter that feeds the
CPUCLK output.
This input requires a 20 MHz clock. (See COM91C32 for built-in oscillator).
This outgut will supply the free runnin9 5 MHz clock to the COM90261
COM90 26, pin 19. It is capable of driving 70 pf plus one LS load with 20
nanoseconds rise and fall times.
Ground
Power Supply

t

6

TTL CLOCK

TTLCLK

7

OSCILLATOR
LOCAL AREA
NETWORK
CLOCK
GROUND
+5 VOLT
SUPPLY

OSC
LANCLK

'9
8
16

GND
Vee

FUNCTIONAL DESCRIPTION
Transmit logic (refer to figures 2 and 4)
_The COM 9026/COM 90C26, when transmitting data on
TX, will produce a negative pulse of 200 nanoseconds in
duration to indicate a logic "1" and no pulse to indicate a
!Q1lic "0". Refering to figure 4, a 200 nanosecond pulse on
TX is converted to two,100 nanosecond non over~
pulses shown as PULS1 and PULS2. The signals PULS1
and PULS2 are used to create a 200 nanosecond wide
dipulse by driving opposite ends of the RF transformer
shown in figure 2.
Receive logic (refer to figures 2 and 5)
As each dipulse appears on the cable, it is coupled
through the RF transformer, passes through the matched
filter, and feeds the 751088 comparator. The 751088 pro-

225

duces a positive pulse for each dipulse received from the
cable. These pulses are captured by the COM 90C32 and
are converted to NRZ data with the NRZ data bit boundaries being delayed by 5 OSC clock periods as shown in figure 5. As each byte is received by the COM 9026/COM
90C26, the CA clock is stopped by the COM 9026/COM
90C26 (via DSYNC) until the first bit of the next byte is
received which will automatically restart the CA clock. The
COM 9026/COM 90C26 uses the CA clock to sample the
NRZ data and these sample points are shown in figure 5.
Typically, RXIN pulses occur at multiples olthe transmission rate of 2.5 MHz (400 nanoseconds). The COM 90C32
can tolerate distortion of plus or minus 100 nanoseconds
and still correctly capture and convert the RXIN pulses to
NRZformat.

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range .................................................................................... O°C to 70°C
Storage Temperature Range ................................................................................... - 55° to 150°C
Lead Temperature (soldering, 10 sec.) .................................................................................. 325°C
Positive Voltage on any Pin ........................................................................................ Vee + 0.3V
Negative Voltage on any Pin ............................................................................................ - 0.3V
Maximum Vee ................. : .......................................................................................... + 7V
'Stresses above those listed may ca!Jse permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
DC ELECTRICAL CHARACTERISTICS (TA = O°Cto + 70°C, Vee = 5V ±5%)
PARAMETER
INPUT VOLTAGES
VIH
VIL
OUTPUT VOLTAGES
VOH '

MIN

TYP

VOL'
VOH3

UNIT

0.8

V
V

2.7
2.4

V

VOL'
VOH2

MAX

Vee-0.5

0.4

V

0.4

V
V
V

0.4

V

50
10

I1A
I1A

20

pf

20

rnA

MAX

UNIT

Vee-0.5

VOL>
LEAKAGE CURRENT
I"
I"
INPUT CAPACITANCE
CIN
SUPPLY CURRENT
Icc

COMMENTS

10H= -0.4 rnA, PULS1, PULS2,
BLNK, RXOUT and TTLCLK
outputs.
____
10L = 4.0 rnA, PULS1, PULS2,
BLNK, RXOUT and TTLCLK
outputs.
10H = - 0.1 rnA, CPUCLK output.
10L = 0.1 rnA, CPUCLK output.
10H = - 0.1 rnA, CA and LANCLK
outputs.
10L = 0.4 rnA, CA and LANCLK
outputs.
TTLCLK input with CKSEL low.
all other inputs.

at 20 MHz OSC frequency.

AC CHARACTERISTICS
PARAMETER
OSClnput
Icy,
tCH1

tel1

MIN

TYP
50

ns
ns
ns

200

ns
ns
ns
ns
ns

20
20

COMMENTS

CA, LANCLK
t CY2
tCH2

teL2
tF2
tR,
TTLCLK

1cY3

IcH3
IcL3
CPUCLK (CKSEL is high)
Icy,

1cH4

IcL4
tF'
tR4
tOCK
TRANSMIT TIMING
tsTC
tHTC
top
tp1W
twa
tp2W
tRST
RECEIVE TIMING

'tootRW"-

t RO
tsso

!sse

,"ow

75
75
20
20
250

ns
ns
ns

250

ns
ns
ns
ns
ns
ns

110
110
110
110
30
30
45
50
10

30
60
2tey,
Icy,
2tey,
40

30
10
70
10

5lcy, +,too
20
400

226

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
' ns

for CKSEL low.

(c~liEt~w)-J I",
CPUCLK
(CKSEL HIGH)

t
.

f

1:'-1---

---1'

,e,

---

FIGURE 3: CLOCK TIMING

DSC

CA

FIGURE 4: TRANSMIT TIMING PARAMETERS

~~
':"'
RXIN

I"

1_

DSYNC

I

I

SAMPLE

SAMPLE

t

1=

FIGURE 5: RECEIVE TIMING PARAMETERS
227

+

Circuit diagrams utilizing' SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given, The

~n;~~~:~~~r rna:c~~~a~i;:~~~~~he~~gr~~~u~di~~o~~i~ii~~dtge~~~n~~~!~;i~~~~ep~~~aeSv:rrOfth;~:~~bi~~I~t6t~~
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible:

228

COM9046
PRELIMINARY

Single Side Band Speech Scrambler

PIN CONFIGURATION

FEATURES
D Speech Scrambling/Descrambling
D High Dynamic Range
D Low Voltage Operation
D Low Power Consumption
D On Board Crystal Oscillator
D Uses Common Color Burst Crystal
D Full Duplex Operation
D Selectable Scramble Enable/Disable
D Switched Capacitor Filter
D COPLAMOS® n-Channel Silicon Gate Technology

N/C
Scramble 2
Vss

3

Ref 4
In-S 5
Out-S 6
Vdd. 7

14
13
12
11
10

XTAL,

N/C
XTAL,
In-A
Out-A

9 Vdd
8 Vss.

GENERAL DESCRIPTION
The COM9046 is a monolithic integrated circuit containing a voice scrambler, a descrambler and a crystal oscillator. It is designed to provide speech communication
equipment with a privacy feature. The COM9046 is also
designed to operate with power supply voltages as low as
± 2Volts. The low voltage operation and low power consumption of the COM9046 make it ideal for use in portable
equipment.
Two identical speech channels are contained in the
COM9046 for full duplex operation. Either channel is capa- .

229

ble of performing the scrambling or descrambling function.
These functions can be enabled or disabled via an external
pin. The on-board oscillator employs an inexpensive 3.58
MHz TV color-burst crystal. Switched capacitor techniques
are used to perform analog signal processing in the
COM9046.
Typical applications for the COM9046 are Voice
Communications, Cellular Phones, Wireless Phones,
PBX's, Dictation Machines, Two-way Radios and Audio
Recording Equipment.

SPEECH
INPUT

SPEECH
INPUT

DOUBLE
SIDEBAND
MODULATOR

LOW PASS
FILTER

DOUBLE
SIDEBAND
MODULATOR

LOW PASS
FILTER

10

OUT·A

6

OUT·B

2

SCRAMBLE

9
Vdd
+2.6V

7
VddA

Vss

VssA

-2.6V

10M

15pf ±10%

PSPf ±10°1'

Figure 1 BLOCK DIAGRAM

DESCRIPTION OF PIN FUNCTIONS
PIN#
1
2
3
4
5
6
7
8
9
10
11

13

NAME
N/C
Scramble
Digital Supply
Ref Input
Audio Input B
Audio Output B
Analog Supply
Analog Supply
Digital Supply
Audio Output A
Audio Input A
Crystal inpuV
Ext Clock
N/C

14

Crystal input

12

SYMBOL

Vss
Ref
In-B
Out-B
Vdd A
Vss A
Vdd
Out-A
In-A
XTAL,

XTAL2

DESCRIPTION
No Connection
Vss applied to this pin asserts the scramble; Vdd asserts non-scramble.
Negative digital supply. Vss is typically - 2.6 volts with respect to pin 4.
Analog ground or mid-supply voltage. This is the chip 0 volt reference.
Channel B audio input. D.C. voltage must be OV with respect to pin 4.
Channel B audio output. DC voltage is OV typical with respect to pin 4.
Positive analog supply. Vdd is typically + 2.6 volts with respect to pin 4.
Negative analog supply. Vss A is typically - 2.6 volts with respect to pin 4.
Positive digital supply. Vss is typically + 2.6 volts with respect to pin 4.
Channel A audio output. DC voltage is OV typical with respect to pin 4.
Channel B audio input. D.C. voltage must be OV with respect to pin 4.
Crystal Oscillator input or external clock. External clock frequency should
be 3.58MHz with an amplitude of 4Vp-p and OVDC.
No connection
Crystal Oscillator output. This pin is left floating when external clock is
applied to pin 12.
230

OPERATION
Figure '1 shows a block diagram of the chip. Also shown
in Figure 1 are the required external components.

ing the output of the oscillator by 1024. The modulator output contains two sidebands centered at the suppressed
switching frequency of 3.5KHz. The upper sideband is
attenuated by a 4th order Butterworth lowpass filter. The
filter, conSisting of two biquad switched capacitor filters in
cascade, is clocked at 111.9KHz. The inverted input speech
spectrum appears at the filter output, and is available at the
Audio Output pin. The filter output circuit is designed to drive
a maximum capacitive load of 5pf in parallel with a minimum resistance of 15K ohms.

Since switched-capacitor filters are used on the chip, the
input speech signal must first be filtered by an anti-aliasing
one-pole low pass filter before it is applied to the Audio input
pin. The filter 3dB break point, which is determined by the
product of C1 and R1 plus the output impedance of the audio
source, should be less than 20KHz. This filter is required
only if high frequency noise is present at the input. To maintain an output signal to noise ratio of 40dB, any unwanted
signal higher than 3.5KHz contained in the speech input
must be filtered to 40dB below the nominal speech input
level, due to the fact that the on-chip modulator is switched
at3.5KHz.

A parallel resonant crystal oscillator is employed in the
device. The parallel resonant crystal should have a maximum series resistance of 150 ohms with a shunt capacitance of 5pf. To insure reliable oscillator performance, the
components shown connected to XTAL pins 14 and 12 in
Figure 1 should be used.

The on-chip double sideband modulator can be turned
on or off by asserting the SCRAMBLE input pin. The 3.5KHz
switching frequency of the modulator is generated by divid-

ELECTRICAL CHARACTERISTICS

COM9046

MAXIMUM GUARANTEED RATINGS*:
Operating Temperature Range ......................................................................... -15°C to +55°C
Storage Temperature Range ........................................................................... -55°C to +125°C
Lead Temperature (soldering, 10 sec.) .................................................................
+325°C
Positive Voltage on any pin with respect to Vss ........................................................
+ 6.5 V
Negative Voltage on any pin with respect to Vss . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . .
- 0.3 V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other condition above those indicated in the operational sections of this specifications is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their
outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may appear on
the DC output. If this possibility exists, it is suggested that a clamp circuit be used.

ELECTRICAL CHARACTERISTICS (Ta
±5%.)

Parameter
Supply Current
Insertion Loss
Audio Voltage Swing
SIN Ratio
Modulation Frequency
Bandedge of Sideband Filter
Scramble Input High
Scramble Logic Low
Input Resistance
Dynamic Output Resistance
3.5KHz Feedthrough

.

=

-10°C to + 50°C, Vdd

Min

= VddA

= +2.6V ±5%, Vss = VssA

Typ

Max

Units

5
0
0.8

8
1
1

ma
db
Vp-p
db
KHz
KHz
V
V
MOhm
Ohm
db

40
3.5
3.2
Vdd-1.0
Vss

Vdd
Vss+.3
5
900
-60

231

-50

Comments

=

-2.6V

l~~L

~.
COM 9046

RADIO OR WIRE
TRANSMISSION
MEDIUM

wt

~.
COM 9046

..

En

E,"

~)) ]
E.

Em

'.~.

Lt

~. ~.
Figure 2 TYPICAL APPLICATION
'Inverted Frequency Spectrum of the Inspect Signals
are Transmitted on the Transmission Medium.

15pF±10%

~I
T
0.1 /iF

4K

Audio~

inA

15pF±1O%

,.D.~
10M

12

""TI

~

1
T
14

11

10---7 Out A

5

6 ----70utB

2000pFt
0.1 /iF

+5V

4K

Audio'II
InB7I I

2000PFt
COM9046

lOOK

. . 1'

Scramble

10K

2
±Ol/iF

lOOK

Vdd

9

Vdda
7_

4

Ref

3
Vss

8

,+5V

-p~'~

1

2.2K

Vssa

u lOpF

~ T ""
" .1/iF
2.2K

RECOMMENDED CONNECTION FOR SINGLE +5V SUPPLY OPERATION
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given, The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is

assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply tne best product possible ....

232

COM90C56
PRELIMINARY

Enhanced Local Area Network Controller
ELANC
FEATURES

PIN CONFIGURATION*

D 5.0/2.5 M bit data rates
D 100% compatible with COM9026 (in slow mode)
ARCNET local area network controller

D 64 K byte shared buffer memory
D Handles variable length data packets (up to 2 K long)
D Supports up to 255 nodes per network segment
D Allows 8/16 bit word per sync to enhance line efficiency
D Supports event scheduling via buffer descriptors
D On chip network diagnostics

XTAL1
XTAL2
REO
ACK
NC

RfiJ

cs
AO
A1

D Duplicate 10 detection/prevention

A2
A3
A4
A5
A6
A7
AS
A9
A10
A11
A12
A13
A14
A15
GROUND

D Supports group broadcast messages
D Provides the hooks for broadband systems (modem)
D Internal loop back capability for self test
D On board oscillator
D Low power CMOS technology
D 48 pih D.I.P. plastic package or PLCC
D Single + 5v Suppiy
D Compatible with HYC9058, HYC9068, HYC9078
D RAM buffer test capability

vcc
GNO
RECON
ECHO
NC
RESET

os
RELAYCON
PULSE2
PULSE1
TXC
RXC
RX
IDLD
INTR2
INTR1
D7
D6
D5
D4
D3
D2
D1
DO

PACKAGE: 48-pin D.I.P.

• Available in PLCC
Pin configuration subject to change, contact factory for details.

GENERAL DESCRIPTION
The ELANC is a general purpose communications adapter
designed to provide high speed intercommunication
between a number of intelligent electrical machines. Data
is carried over a variable media (twisted pair, coax, or fiber
optics) in variable size packets up to 2048 bytes long at

speeds of up to 5.0 Mbps. The interconnection of several
nodes through their associated ELANCs forms an enhanced
local area network. Each node has a unique 10 number from
1 to 255 to distinguish it from other nodes on the same
network.

233

~-~
......--53

0
w
---....-1

CND

IIGND

AlE
AS

~--++~===;;;==========~
+5V

PAD7'()

'\r--"""7~'V1

WAIT
WE

REO

RD

S
W
I

10
T

OUT

C

H
E

S

FIGURE 2-TYPICAL COM90C62 INTERFACE
236

DESCRIPTION OF PIN FUNCTIONS (refer to figure 2)
DIP PIN NO.
31
32
35

NAME
ADDRESS 10, 9, B

SYMBOL
A10,A9,AB

ADDRESS/DATA 7-0

AD7-ADO

S

1/0 REQUEST

10REQ

9

MEMORY REQUEST

MREQ

7

READ/WRITE

RIW

10

ADDRESS STROBE

AS

11

REQUEST

REQ

12

WAIT

WAIT

6

DELAYED
WRITE

DWR

29

INTERRUPT
REQUEST

INTR

1S

INTERFACE lATCH
ENABLE

ILE

14

ADDRESS DATA
INPUT ENABLE

ADIE

13

AlE

15

ADDRESS INPUT
ENABLE
lATCH

17

WRITE ENABLE

WE

16

OUTPUT
ENABLE

OE

33

ID lOAD

IDlD

34

ID DATA IN

IDDAT

21-2S

1,3

L

EXTENDED
ET2, ET1
TIMEOUT FUNCTION
2,

FUNCTION
These three output signals are the three most significant bits of the
RAM buffer address. These signals are in their high impedance state
except during COM 90C62 access cycles to the RAM buffer. A10 and
A9 will take on the value nn as specified in the ENABLE RECEIVE or
ENABLE TRANSMIT commands to or from page nn and should be
viewed as page select bits. For packets less than 256 bytes, a 1K
buffer can be used with AS unconnected. For packets greater than
256 bytes, a 2K buffer is needed with AS connected.
These S bidirectional signals are the lower S bits of the RAM buffer
address and the S bit data path in and out of the COM 90C62. ADO
is also used for 1/0 command decoding of the processor control or
status commands to the COM 90C62.
This input signal indicates that the processor is requesting the use of
the data bus to receive status information or to issue a command to
the COM 90C62. This signal is sampled internally on the falling edge
ofAS.
This input signal indicates that the processor is requesting the use of
the data bus to transfer data to or from the RAM buffer. This signal is
sampled internally on the falling edge of AS.
A high level on this input signal indicates that the processor's access
cycle to the COM 90C62 or the RAM buffer will be a read cycle. A
low level indicates that a write cycle will be performed to either the
RAM buffer or the COM 90C62. The write cycle will not be completed, however, until the DWR input is asserted. This signal is an
internal transparent latch gated with AS.
This input signal is used by the COM 90C62 to sample the state of
the 10REQ, MREQ and RIW inputs. The COM 90C62 bus arbitration
is initiated on the falling edge of this signal.
This output signal acknowledges the fact that the processor's 1/0 or
memory cycle has been sampled. The Signal is equal to MREQ or
10REQ passed through an internal transparent latch gated with AS.
This output signal is asserted by the COM 90C62 at the start of a
processor access cycle to indicate that it is not ready to transfer
data. WAIT returns to its inactive state when the COM 90C62 is
ready for the processor to complete this cycle.
This input signal informs the COM 90C62 that valid data is present
on the processor's data bus for write cycles. The COM 90C62 will
remain in the WAIT state until this signal is asserted. DWR has no
effect on read cycles. If the processor is able to satisfy the write data
setup time, it is recommended that this Signal be grounded.
This output signal is asserted when an enabled interrupt condition
has occured. INTR returns to its inactive state by resetting the
interrupting status condition or the corresponding interrupt mask bit.
This output Signal, in conjunction with ADIE, gates the processor's
addressldata bus (PAD7-PADO) onto the interface address data bus
(IAD7-IADO) during the data valid portion of a Processor Write RAM
or Processor Write COM 90C62 operation.
This output signal enables the processor's address data bus (PAD7~ADO) cap~).red by AS or ILE onto the interface address data bus
IAD7-IADO.
This output signal enables the processor's upper 3 address bits
(PA1O-PAS) onto the interface address bus (IA10-IAS).
This output signal latches the interface address data bus (IAD7IADO) into a latch which feeds the lower S address bits of the RAM
buffer during address valid time of all RAM buffer access cycles.
This output signal is used as a write pulse to the external RAM
buffer. Data is referenced to the trailing edge of WE.
This output signal enables the RAM buffer output data onto the interface address data bus (IAD7-IADO) during the data valid portion of
all RAM buffer read operations.
This output signal synchronously loads the value selected by the ID
switches into an external shift register in preparation for shifting the
ID into the COM 90C62. The shift register is clocked with the same
signal that feeds the COM 90C62 on pin 19 (ClK). The timing associated with this signal and IDDAT (pin 34) is illustrated in figure 2.
This input signal is the serialized output from the external.lD shift
register. The ID is shifted in most significant bit first. A high level is
defined as a logic "1 ".
The levels on these two input pins specify the timeout durations used
by the COM 90C62 in its network protocol. Refer to the section entitied "Extended Timeout Function" for details.
237

DESCRIPTION OF PIN FUNCTIONS (refer to figure 2)
DIP PIN NO.

NAME

'37
36
38

INHTX
PULSE1
PULSE2
RXIN

30

ECHO DIAGNOSTIC
ENABLE

ECHO

19

CLOCK

CLK

CRYSTAL

XTAL1
XTAL2

40

POWER ON
RESET

POR

39
20

+5 VOLT SUPPLY
GROUND

Vcc
GND

4, 5
r

SYMBOL

TRANSMIT
INHIBIT
PULSE 1
PULSE 2
RECEIVE IN

2

FUNCTION
This active low input inhibits t~e COM 91C32 from transmitting by
forcing PULSE1 and PULSE2 high.
PULS1 and PULS2 carry the transmit data information encoded in
pulse format.
This input carries the receive data information from the cable
interface circuitry.
.
When this input signal is low, the COM 90C62 will re-transmit all
messages of length less than 254 bytes. This input should be tied
high for normal clip operation and is only utilized when performing
chip level testing.
A continuous 5 MHz clock input used for timing of the COM 9OC62
bus cycles, bus arbitration, serial ID input, and the internal timers.
An external 20 MHz crystal is connected to these pins. If an ex1ernal
20 MHz TTL clock is used, it should be connected to XTAL1 with a
390 ohm pullup resistor.
This input signals clears the COM 90C62 microcoded sequencer
program counter to zero and initializes various internal control flags
and status bits. The POR status bit is also set which causes the
INTR output to be asserted. Repeated assertion of this signal will
degrade the performance of the network.
Power Supply
Ground

OR

TWISTED
PAIR
or
COAX
or
FIBER
OPTICS

HYC9058*
(HIT)

f;)

R.3101*
OTPO

PULSE1
PULSE2

COM90C62

RX

OR
I,PORIN

..----1 IDLD

r-

L.::;t

HYC9068*
(LAND)

-m-

IDDAT

74LS166

~

I

11111111
SWITCH·

'HYC 9058-High Impedance
Transceiver (HIT)
See page 257 of
Data Catalog.
HYC 9068-Local Area Network
Driver (LAI:-lD)
See page 263 of
Data Catalog.
R. 3101 -Pin compatible fiber
optic driver from
Raycom Systems
6395 Gunpark Drive
Boulder, Colorado 80301

FIGURE 3-COM 90C62 TYPICAL DRJVER INTERFACE

NOTE: For an updated data sheet please fill out the reply card in
the back of this catalog or call SMC at (516) 273-3100:

STANDARD MICROSVSTEMS

~
' '.273·3100 ""'·"'·217·_
~

35 ...... ~.~MV \1188

Circuit diagrams utilizing SMC products are included as a means of illustrating ~Pical semiconductor ap~lications: conse-

~~~~d~~g\~tg~7;~,::r~o~:~~~f~~t~~":~~t~gt~~~~r:s~~~~~~~~r~~~J~~~o;~~~~~f:~~FU~~.,":O~~~~

information does not convey to the purchaser of the semiconductor devices described any licl!fnse under the patent rights of
SMC or others. SMC reserves the nght to make changes at any time in order to improve design and supply the best product
possible.
238

COM 9064
PRELIMINARY

IBM® 3274/3276
Compatible COAX Receiver/Transmitter
FEATURES
D Conforms to the IBM® 3270 Interface Display
System Standard
D Transmits and Receives Manchester II Code
D Detects and Generates Line Quiesce, Code
Violation, Sync, Parity, and Ending Sequence
(Mini Code Violation)
D Multi Byte or Single Byte Transfers
D Double Buffer Receiver and Transmitter
D Separate Data and Status Select
D Operates at 2.3587 MHz
D TTL Compatible Inputs and Outputs
D COPLAMOS® n-Channel Silicon Gate
Technology
D Single + 5 Volt power supply

PIN CONFIGURATION,

~

I

n.

ow~«

s>
9 ClICllu Cl 9 ~ dlCl s>
ZClI-I--I-a:c:ea::mo:z
TDS

40

39383736 35 34 33 32 31 3029
28

N/C
N/C

26

TBMT

25

T9

24

27

no

23

GND
VCC
GND
TP
T9S

22
21

20
19
18

7 8 91011121314151617

Vee ~

CVD
RTA
DA
N/C
N/C
MR
GND
SCLK
RP
SWE
N/C

GNO
TP
T9S

ROE·
DO
01
02
03
04
05
06
D7
R9
R10
SWE
RP
SCLK
NIC
GND

~

~

~

'-'

1
2
3
4
5

6
7
8

40~

~oD~~

11
12
13
14
15

16

[

17
18
19
20

GNO

39 ~ no
38 ~ T9
37 ~ TBMT
36 ~ TOS
35
NIC'
34
33
TD

TIl
i'C

30
29
28
27
26
25
24
23

RD

22

NIC

21

MR

ALOOP
RSSE
BCLK

RDA
CVD

RTA
DA

PACKAGE: 44-pin PLCC
PACKAGE: 40-pin D.LP.

'Internally conneCted. Not for external use.

GENERAL DESCRIPTION
The COM 9064 is an MOSILSI circuit which may be used
to facilitate high speed data transmission. The COM 9064
is fabricated using SMC's patented COPLAMOS® technology and may be used to implement an interface between
. IBM® 3274/3276 compatible control units and 3278/32871
3289 compatible terminal units. The receiver and transmitter sections of the COM 9064 are separate and may be used
independently of each other.

The COM 9064 generates and detects the line quiesce,
code violation, parity, and mini code violation bit patterns.
The on-chip parity logic is capable of generating and
checking either ~ven or odd parity for the entire 10 bit data
word. In addition, parity may be generated for the least significant 8 bits of the data word (this parity b.it would replace
the ninth data bit).

lOS
T9

TlO
T19

TD

D'
D'

D1

D3

D.

DS
DS
D7

"D
"P
RSSE
"10

""

"TA
TBMT

DA

V"

CVD

GND
SWE

BCLK
SCLK

IBM(!l is a registered trademark of the International Business Machines Corporation

239

ORGANIZATION
The COM 9064 is organized into 9 major sections. Communication between each section is achieved via internal
data and control busses.

Transmitter Holding Register
The transmit holding register is a 12 bit latch. This latch is
loaded with the transmit data and parity generation information from the system bus.

transmit circuitry. It also generates the Line Quiesce, Code
Violation, sync bits and Mini Code Violation patterns.

Transmitter Shift Register
The transmitter shift register is an 11 bit parallel to serial
shift register. It accepts data from the transmitter holding
register and the parity generation logiC and converts it into
serial form for transmission.

Tri-State Buffers

Receive Control/Parity Check

These buffers allow gating of the COM 9064's status word
onto the system data bus.

This logic checks the received character for the specified
parity and ensures that no Transmit Check conditions
occurred. It also handles the self test mode and generates
a strobe when the complete data word is received.

Bus Transceiver
The bus transceiver allows bi-directional data transfer
between the system data bus and the transmit and receive
holding registers.

Parity Generator
This logic determines and generates the correct parity for
the data in the transmitter holding register.

Transmitter Control
This logic generates signals required to enable external

Receiver Shift Register
This logic is a serial to parallel shift register that converts
the received information into a 10 bit data word and RTA
status bit.

Receiver Holding Register
This register holds the assembled data word until it is read
by the processor.

DESCRIPTION OF PIN FUNCTIONS
Processor Related Signals
PIN NO.
6-13

SYMBOL
DO-D7

38

NAME
Transmit/
Receive Data
Bits
Transmit Bit 9
Select
Transmit Bit 9

39
3

Transmit Bit 10
Transmit Parity

Tl0
TP*

18

System Clock

SCLK

36

Transmitter
Data Strobe
Reset Data
Available
Status Word
Enable

TOS

4

26
16

T9S
T9

RDA
SWE

23

Receive Data
Available

DA

25

Code Violation
Detected

CVD

37

Transmit
Buffer Empty
Receive Bit 9
Receive Bit 10
ReceverTurnaround

TBMT

Receive Data
Enable
Receiver
Parity

RDE

14
15
24
5
17

R9
Rl0
RTA

RP*

FUNCTION
Bidirectional: 8 bit, three state data port used to transfer data between the COM
9064 and the processor.
DO is the first bit transmitted.
Input: A low level on this pin enables T9 to be transmitted as bit 9. A high level on
this pin causes T9 to determine the type of parity bit generated for bits DO-D7.
Input: If T9S is low, this supplies transmit bit 9. If T9S is high, then T9 low forces
odd parity and T9 high forces even parity to be generated for DO-D7. In this case
the parity bit generated is transmit bit 9.
Input: This pin supplies transmit bit 10.
Input: This input controls the parity bit for transmit bits 1-10. A low level on this pin
causes odd parity and a high level on this pin causes even parity to be generated
for bits 1-10. The parity bit generated is transmit bit 11.
Input: This signal is used to synchronize the COM 9064. The transmitter is
loaded and started on the low to high transition of SCLK if TDS is low. DA is reset
on the low to high transition of SCLK if RDA is low.
Input: This input and SCLK are used to load the transmitter holding register and
start the transmit sequence. Code Violation Detect (CVD) is reset at this time.
Input: This input and SCLK are used to reset DA.
Input: A low level at this pin enables the status word buffer outputs (DA, CVD,
TBMT, R9, Rl0, and RTA). A high level on SWE places the status word buffer
outputs in a high impedance state.
This three-state output si\jnal is at a high level when an entire word has been
received and transferred Into the receiver buffer register. It is only set if a Transmit
Check Condition did not occur.
This three-state output signal is at a high level if a valid Code Violation was
detected at the receiver since the last time the transmitter was loaded. It is reset
when the transmitter is loaded.
This three-state output signal is at a high level when the transmit holding register
may be loaded with new data.
This three-state output si_gnal is receiver data bit 9.
This three-state output signal is receiver data bit 10.
This three-state output signal is set to a high level when a valid Mini Code
Violation is detected. It is only set if a Transmit Check did not occur. It is reset
when the transmitter is loaded.
Input: A low level enables the outputs of the receive data register DO-D7.
Input: This input determines 'Nhether the entire received word will be checked for
even or odd parity. A low at this pin will cause a check for odd parity and a high at
this pin will cause a check for even parity. This input has an internal pull-up
resistor.

*The SYNC bit is included in parity checking.

240

DESCRIPTION OF PIN FUNCTIONS (cont.)
PIN NO.
29

NAME
Analog
loopback

SYMBOL
AlOOP

34

Digital
loopback

DLOOP

21

Master Reset

1
19,22,35
2,20,40

Supply Voltage

MR
V~

NIC
Ground

GND

FUNCTION
Input: A low level on this pin disables the receiver except when the transmitter
is active. A high level on this pin and DlOOP will cause the receiver to be
disabled while the transmitter is active.
AlOOP is used to allow loop-back through the line drivers and receivers. This
input has an internal pull-up resistor.
Input: A low level on this pin disables the receiver except when the transmitter
is active. TG is forced to a high level to disable the external coax driver. Data
input to the receiver is internally wrapped from the transmitter data output.
This input has an internal puil-up resistor.
Input: This input shol!!Q be pulsed low after power-on. This si~nal resets DA to
a low level and sets TG and TBMT to a high level. This input as an internal
pull-up.
+ 5 volt supply
No Connection
GROUND

Device Related Signals
PIN NO.
27

NAME
Baud Rate
Clock

SYMBOL
BClK

33

Transmit Data

TD

31

Transmit Clock

TC

30
32

Receive Data
Transmit Gate

RD
TG

28

Receive
Single Shot
Enable

RSSE

FUNCTION
This input is a clock whose frequency is 8 times the desired transmitter and
receiver baud rate (typically 18.8696 MHz for 3274/3276 operation). This input
is not TTL compatible.
Output: Serial data from the transmitter. This signal is a biphase Manchester II
encoded bit stream. This output is low when no data is beil'lll transmitted.
The Transmit Clock output is V. the frequency of BClK. It is synchronized with
TO and used to provide external pre-distortion timing.
Input: Accepts the serial biphase Manchester II encoded bit stream.
Output: This signal is low during the time that the transmit data is valid. TG is
used to turn on the external transmit circuitry.
Input: A high level on this pin enables an internal digital single shot on RD. This
limits a high level on RD to 3 clock times. Also when high it will cause the
receiver not to detect a valid Code Violation. A low level disables the single shot
causing no reshaping of the RD input signal.

COM 9064 OPERATION
The COM 9064 consists of a receiver section that converts
Manchester II phase encoded serial data to parallel data
and a transmitter section that converts parallel data to
Manchester II phase encoded serial data.

The Code Violation Detect signal (CVD) goes active high
after a line Quiesce, Code Violation and sync bit have been
detected by the receiver. It is reset when the transmitter of
the COM 9064 is asserted. By examining this signal, the
processor can determine whether a timeout or Transmit
Check condition caused a receiver error.

Receiver
Message transfers must conform to the IBM 3270 protocol
in order for the COM 9064 to acknowledge them.

The receive input is sampled at 8 times the data rate. The
receiver logiC is brought into bit synchronization during the
Line Quiesce pattern. Once the Code Violation following the
Line Quiesce is detected, the receiver is brought into bit and
word synchronization. The internal receiver clock is adjusted
after each transition to compensate for jitter and distortion
in the received data signal.

The received message is checked for the Code Violation
sequence (start sequence) bit pattern, preceding the first
data word, and Mini Code Violation (end sequence)
following the last data word.
The data word consists of 10 data bits, a sync bit and a parity
bit. Receiving data in multiple byte format is functional only
when even parity is selected.

Transmitter

The data word along with the first bit of the next word or
ending zero (bit 13) is shifted into a shift register. Once it is
assembled it is transferred and held in the holding register
until another data word is assembled. The 13th bit is inverted
. and presented to the bus or RTA (receiver turn-around).
Therefore RTA is set high on the last word of a message
and is reset when the transmitter is loaded with the
response.
Once the data word is in the holding register and parity is
correct the data available (DA) status signal is set high.
241

The transmitter section basically consists of a 12-bit holding
register, parallel to serial shift register and a parity generator.
The firmware initiates a transmit sequence by strobing TDS
low. The data is loaded into the holding register on the rising
edge of SCLK while TDS is low. Nine bits of data (DO-D7
and T10) are transferred without change to the transmit shift
register. The logic level of T9S determines whether T9 will be
transmitted as parity on the preceding eight bits, or as data.
After the processor loads the transmit holding register with
data, status signal TBMT is driven inactive low until the COM
9064 transfers the data from the transmit holding register

to the transmit shift register. After the transfer, TBMT is
driven high. The processor should not try to load data into
the COM 9064 while TBMT is low. When initiating a data
transmission, the COM 9064 automatically transmits a Une
Quiesce pattern and a Code Violation. The data is then
shifted out of the shift register with a sync bit (1) inserted
before the data word, and a parity bit appended after the
data word.

Diagnostic Modes.
NORMAL OPERATION (ALOOP AND DLOOP HIGH)

Internal read data signal follows the RD input as long as the
COM 9064's transmitter is off. The receiver will be disabled
while the transmitter is active.
ANALOG LOOPBACK (ALOOP LOW AND DLOOP
HIGH)
The internal read data signal follows the RD input as long
as the COM 9064's transmitter is active.
DIGITAL LOOPBACK ALOOP HIGH AND [)[()()P LOW)
The internal read data signal follows an internally generated
and latched valid transmit signal (only when the transmitter
is active.) The output TG is disabled in digital loopback
mode.
DISABLE RECEIVER (ALOOP AND DLOOP LOW)
The internal read data signal is held low and output TG
is disabled.

If a new word is loaded into the COM 9064 before the parity
bit of the previous word has been transmitted, a sync bit (1)
followed by the new data bits is transmitted. If not, after the
COM 9064 transmits the last data word (no more transmit
sequences are started), a sync bit (0) and a Mini Code
Violation is appended to the end of the message.
Output fG goes active low one-half bit cell time before the
first Une Quiesce character is output. It is made inactive
(high) during the transmission of the Mini Code Violation.

MESSAGE FORMATS

CODE
VIOLATION

ENDING
SEQUENCE

CODE
VIOLATION

SYNC
BIT

SYNC
BIT

PARITY

BIT

ENDING
SEQUENCE

DATAN
(10 BITS)

Bits on the coax appear as positive and negative going
pulses. A positive pulse to negative pulse transition in the
middle of the bit cell is interpreted as a logical '0' . A negative
pulse to positive pulse transition in the middle of a bit cell is

interpreted as a logical '1'. A predistortion pulse is generated
for every pulse transition from an up to down level or a down
to up level.

Line Quiesce Pattern

1

I
_ _ II

,, ,

1__ 1I

I

,
I

one bit
time

1

I
I
I
I
I
I_I
I
I

I

I
_ _ II

1

_ _ II

,

, , ,
,
I
I

I

1

'_I

I
I
I
I
I_I

I

I

I

I

The Une. Quiesce pattern consists of five contiguous logical
ones. It establishes an equilibrium condition on the coax
following line turnaround.
.

242

I

_ _ II

,
I

I
I
--I
I
I
I

I
I _ -I
I

,

,
I
I
I

Code Violation Pattern

I

I
I

1

-,

1

_I

I
1

I
1

I
I

"I

'____ 1

1I

1

last "1"
of linequiesce

I

I--

code

1
,

,

violation

,
1

1

1

1_ _ 1

1

1

1

1

sync bit

1

The Code Violation pattern is a bit sequence containing
no mid-bit time level transition in two of its three bit
cells. It is a unique pattern that violates the encoding
rules and indicates the start of valid data.

Mini Code Violation Pattern

bit times:

11

1

12

0

p

2
mcv

"1 "
or
"0"

last data
byte

Ending Sequence

The Mini Code Violation (MCV) pattern is a bit
sequence containing no mid-bit time level transition
in either of its bit cells. It is a unique code that violates
the encoding rules and indicates the end of valid
transmit data.

Transmit Check
A Transmit Check is defined as follows:
1) A logical zero sync bit in the ending sequence not
followed by a Mini Code Violation.
2) Loss of a level transition at the mid-bit time during
other than a normal ending sequence.
3) A transmission parity error.

243

3
mcv

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range .................................................................................. O°C to + 70°C
Storage Temperature Range ................................................................................. - 55° to + 150°C
Lead Temperature (soldering, 10 sec.) ............................. ,........ , ...... , ....... , .......................... , + 300°C
Positive Voltage on any 1/0 Pin, with respect to ground .......................... '.' ........................ , ............. + S.OV
Negative Voltage on any 1/0 Pin, with respect to ground ... , ....................... , ..................................... - 0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. For example, the bench
power supply programmed to deliver +5 volts may have large voltage transients when the AC power is switched on and off. If this
possibility exists it is suggested that a clamp circuit be used.
DC ELECTRICAL CHARACTERISTICS (TA = O°C to 70°C, Vee = + 5V ± 5%)
PARAMETER
DC CHARACTERISTICS
INPUT VOLTAGE
V,LLow
V'HHigh
V,HHigh
V,HHigh
OUTPUT VOLTAGE
VOL Low.
VOHHigh
POWER SUPPLY CURRENT
Icc
INPUT LEAKAGE CURRENT
All input pins
CAPACITANCE
C'N
C'N

MIN

TYP

-0.3
2.0
Vee- 0.7
3.5

MAX

UNIT

.S
Vee
Vee+·3
Vee+.3

V
V
V
V

(Except BCLK and MR)
(BCLKonly)
(MRonly)
10L = 2.0mA
10H = -.25mA

.4
2.4
125

COMMENTS

mA

All outputs

.01

mA

V,N

10
35

pf
pf

= VOH

= OtoVee

(Except BCLK)
(BCLKonly)

-

AC ELECTRICAL CHARACTERISTICS (TA = O°C to 70°C, Vee = +5V ±5%)
. PARAMETER
Clock Frequency
BCLK

SeLK
Clock Width
tSKH SCLKHigh
SCLKLow
tSKL
t8KH BCLKHigh
BCLKLow
tBKL
t,
BCLK rise time
BCLK fall time
tF
RDE to Data Valid Delay
tROD
tSDD SWE to Data Valid Delay
toF Data Read to Bus Float
los Data Setup Time
tOH Data Hold Time
tOAV DA to receive data
valid delay
tTO TC clock period
t'fOLD TC to TG low delay
t'fOHo TC to TG high del~
tTOS Transmit data to T
setup time
Transmit data to TC
tTDH
hold time
TBMT
active to de-active
to
tTDDe TBMT cycle
too TBMT de-activated
toss IQ.S. set up
toSH TDS hold
t..R MR pulse width

MIN

TYP

MAX

UNIT

7
DC

1S.S696
4.7474

1S,9
5

MHz
MHz

6
6
50
50
50

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

SO
SO
20
20

100
10
-100

100
106

-53

30
30

10
20

ns
ns
ns
ns
ns

200
3.2
2
200
100

1
100
20
300

244

ns
.,.s
.,.s
ns
ns
ns

CONDITIONS

TIMING DIAGRAMS

MISC. TIMING

BUS INPUT TIMING

tr

SCLK

BCLK

TDS/RDA*

L

MR

tOH

,---t05 --I.......

DATA

VALID DATA

RECEIVE DATA TIMING

OA _ _ _ _

TBMT /

A
I

tOAV*:

00-07.

~

R9. R10 ~----I(L=::YVA~Ldllo2jD~A~:rAL=

'Only one rising edge of SCLK within this pulse width.

BUS OUTPUT TIMING

·OA may occurfrom 100 ns before 10 100 ns aller dala is valid.

ROE

TRANSMITTER TIMING
TC

TO

'"""1_1-----1

.rl

BIT CEll - - - - -..

DATA,
STATUS
VALID

t500

-------<~~______

TBMT CYCLE

TBMT

-.J

I
II'"....- - - - t o o c - - - -...........l
l=---too

245

~

J>---

,

~

0

!;Q

0
r-Z~

:;5

I C!lg

0
w

>~

Sill

a:
0

~

~

"1i'z
w
w

z

az 1ii

w
w

~

...

:J

0

(/l

...J

«

":s

a:

I-

a:

;:

;b

~

0

<

0

A:

>
t-

E~8
I-'~

0

....

+

W

t-


III

~

a::

a:
IZ

W

::;

0

...J

...J

0

er:

~

W

0

m

~

Ig

0

W

0

~
I-

I

f-

'z<'

-'

0

I~

Z

Q

z

0

;;!

a.

ci

0

:i

'"

~~!:2
~

"-l

N'"

"'~

0

...

r-N

...JI

~::;;

(/lID

>-m
er: ID
o~

D

~

.......

0

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications:
consequently complete information sufficient for construction purposes is not necessarily' given. The Information
has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described
any license under the patent rights of SMC or others. SMC reserves the right to make changes at any time in order
to Improve design and supply tfle best product possible.

246

COM91C32
PRELIMINARY

COM91C32
Local Area Network Transceiver
LANT
PIN CONFIGURATION*

FEATURES

o Compatible with the COM9026 and COM90C26 LANCs

o Compatible with the HYC9058 HIT
o Compatible with the HYC9068 LAND
o Functionally compatible with the COM90C32
o Reduces node chip count
o Built-in 20MHz crystal oscillator
o Internal Power On Reset for COM9026/COM90C26

o Provides all clocks for COM9026/COM90C26
o Low power CMOS technology

o TTL compatible
o 5V only power supply

PULS2

1 \"..Jlb

V"

PULS1

2

15

'iNRTX

RESET OUT

3

14

TX

PORIN

4

13

CA

RESET IN

5

12

DSYNC

XTAL 2

6

11

RXOUT

XTAL,/TrLCLK

7

10

RXIN

GND

8

9

LANCLK

·Check with factory for SMT package. availability

GENERAL DESCRIPTION
The COM91 C32 local area network transceiver (LANT) is
an improved version of the COM90C32. It reduces both
node cost and board real estate. The COM91 C32 is a
companion chip to either the COM9026 or COM90C26 local
area network controller (LANC), the HYC9068 local area
network driver (LAND), and the HYC9058 high impedance
transceiver (HIT).

local area networks. The COM91 C32 produces two 5MHz
clocks for the COM9026/COM90C26. The first one
(LANCLK) is free running and feeds the clock input (pin 19)
of the COM9026/COM90C26. The second one (CA) has
start/stop capability controlled by the DSYNC output of the
COM9026/COM90C26 as well as the data received from
the network.

The COM91 C32 contains two circuits not available on the
COM90C32. A 20MHz crystal oscillator has been built in to
eliminate the need for an external oscillator. In addition, the
external power on reset circuit required by the COM9026/
COM90C26 has been integrated inside the COM91 C32 to
reduce the number of components, their related costs, and
board real estate.

During data reception, the COM91 C32 will convert incoming
serial receive data from the HIT or LAND circuitto NRZ form
which will directly feed the RX input of the COM9026/
COM90C26 (pin 38). During transmission, the COM91 C32
converts the transmit data from the COM9026/COM90C26
TX, (pin 37) into the Waveforms necessary to drive the
HYC9058 or HYC9068 as shown in figure 2.

The COM91 C32 performs the functions necessary to allow
simple interface to the transmission media for ARCNET®

247

TX

PULS1

INHTX

PD[S2

LANCLK
CA
DSYNC

RXIN

RXOUT

PORIN
RESET IN

Figure 1: COM.91C32 INTERNAL BLOCK DIAGRAM
DESCRIPTION OF PIN FUNCTIONS (refer to figure 2)
COM 9026 Interface
PIN NO.

2

NAME
PULSE 1

SYMBOL
PULS 1

1

PULSE 2

PULS2

3

RESET OUT

RESET OUT

10

RECEIVE
IN
RECEIVE
OUT

RXIN

11

RXOUT

FUNCTION
PULS1 AND PULS2 carry the transmit data information encoded
in pulse format.
This output signal provides a reset signal capable of ensuring
proper reset of the COM9026/COM90C26. It is TIL compatible.
The RESETOUT pulse width equals 102.4psec + (RESETIN or
PORIN pulse width).
This input carries the receive data information from the cable
interface circuitry.
This output provides the NRZ encoded receive data to the
COM9026/COM90C26.

12

DELAYED
SYNC

DSYNC

This active low input is asserted by the COM9026 and is used to
synchronize the CA clock.

13

CA

CA

14

TRANSMIT
DATA
TRANSMIT
INHIBIT

TX

This output is a 5 MHz start/stop clock that halts when DSYNC
goes active. It is used to synchronize the CA clock output to the
RX OUT received data.
This input represents the serial data transmitted by the
COM9026/COM90C26.
This active low input inhibits the COM91 C32 from transmitting
by forcing PULS1 and PULS2 high.

15

INHTX

System Clock Interface
4

POWER ON
RESET IN

PORIN

5

RESET IN

RESET IN

7
6

CRYSTAL

XTAL1
XTAL2

9

8
16

LAN
CLOCK
GROUND
+5V
SUPPLY

LANCLK
GND
VCC

This input signal, which is controlled by C, (fig. 2) on Power up,
disables the transmitter portion of the COM91 C32 and generates
the RESET OUT signal. This pin has a schmitt trigger input.
This input signal disables the transmitter portion of the
COM91 C32 and generates the RESET OUT signal. This pin has
a TTL compatible input.
An external 20 MHz crystal is connected to these pins. If an
external 20 MHz TTL clock is used, it should be connected to
XTAL 1 (pin 7) with a 390 ohm pullup resistor; XTAL2 must be left
floating.
This output supplies a 5 MHz free running clock for the
COM9026/COM90C26.
Ground
+5 Volt Power Supply

248

,

FUNCTIONAJ,. DESCRIPTION
In addition to initializing the COM91 C32 to an idle state, the
RESET IN signal disables the transmitter portion of the
COM91 C32 during reset.

The COM9026/COM90C26, when transmitting data on TX,
will produce a negative pulse of 200 nanoseconds to
indicate a logic "1" and no pulse to indicate a 10giCO."
Referring to figure 4, a 200 nanosecond pulse on TX is
converted ~OO nanosecond nonoverlapQiD.9...Qulses
shown as PULS1 and PULS2. The signals PULS1 and
PULS2 drive the HYC9058 or the HYC9068 which in turn
creates a 200 nanosecond dipulse signal on the cable as
shown in figure 2.

During reset, the COM91 C32 output pins are as follows:
PULS1 - is inactive (high)
PULS2 - is inactive (high)
LANCLK - is free running during and after reset
CA - is free running during and after reset

At the receiving nodes, each dipulse appearing on the cable
is coupled through the RF transformer of the HYC9058 or
HYC9068 to produce a positive pulse. These pulses are
captured by the COM91 C32 and are converted to NRZ data.
As each byte is received by the COM91 C32, the CA clock
is stopped by the COM9026/COM90C26 (via DSYNC)
until the zero bit of the next byte is received.
This will automatically restart the CA clock. The
COM9026/COM90C26 uses the CA clock to sample the
NRZ data and these samples points are shown in figure 5.

The minimum RESET IN pulse width is 120 nanoseconds
(or 2T + 20 nanoseconds for input clocks different than 20
MHz). For the 20 MHz clocks, T equals 50 nanoseconds.

RESET IN/OUT TIMING
The COM91 C32 incorJ;!orates a digital filter that will
suppress glitches on the RESET IN and POR IN pins. The
digital filter will filter all RESET IN and PORIN glitches that
are narrower than 40ns (1 T -1 Ons). It will allow RESET IN
and POR IN pulses that are wider than 120 ns (2T +20ns).
The RESET OUT pulse width is equal to the RESET IN pulse
width plus 102.4 microseconds.

Typically, RXIN pulses occur at multiples of 400
nanoseconds. The COM91 C32 can tolerate distortion of
plus or minus 100 nanoseconds and still correctly capture
and convert the RXIN pulses·to NRZ format.

THE INTERNAL OSCILLATOR

RESETTING THE COM91 C32

The COM91 C32 incorporates on-board circuitry which, in
conjunction with an external parallel resonant crystal, forms
an oscillator. The oscillator frequency may vary between 8
MHz and 20 MHz to allow for a variable data rate from 1.0
Mbps to 2.5 Mbps.

The PORIN active low input signal is generated by turning
the power on to generate the RESET OUT signal to the
COM9026/COM90C26. The recommended capacitor
value (C1 in figure 2) required to properly reset the
COM9026/COM90C26 on power up is 0.1 f.1F.

The oscillator input is divided by 4 to produce the CA and the
LANCLK output clocks to the COM9026/COM90C26.

The RESET IN active low input signal is provided to
generate the RESET OUT signal used to reset the
COM9026/COM90C26. The pulse width of the RESET OUT
signal is 102.4 microseconds, which is wide enough to
properly reset the COM9026/COM90C26 local area
network controller device.

The COM91 C32 XTAL oscillator has been designed to work
with a parallel resonant crystal and does not require an
external resistor. Only two capacitors are needed (one from
each leg of the XTAL to ground.) The values of the
capacitors are two times the load capacitance ofthe crystal.
Typical capacitor values are 22 pF.

RESET OUT = RESET IN (pulse width) + 102.4
microseconds
RESET OUT =PORIN (pulse width) + 102.4
microseconds

COM9026!
COM90C26

.,,

,,
I

COM
9

o

CLOCK

S

o

C

C

The external crystal must have an accuracy of 0.020% or
better.

COM
9
1
C

COM9026!
COM90C26

3
2

I I I I CRYSTAL
f--T

3
2
RESET
PULSE

RESET PULSE

I+-

RESET IN

RESET IN

C

R

FIGURE 2: COM90C32 AND 91C32 IMPLEMENTATION DIFFERENCES
249

COM9026

COM91C32

OR

COM90C26

-

-

TX

TX

CA

CA

PULS2

PULS2

DSYNC

DSYNC

PULS1

PULS1

RX

RXOUT

POR

RESET OUT

CLK

LANCLK

,..--.

IDLD
IDDAT

RESET IN
XTAL1
ITTLCLK

l--=+t.
Jo~J !JI~C~
74LS166

22pF

RXIN

PORIN
XTAL2

RX

-

bod

:;b

:;b 22pF

I
-=

COAX
or
FIBER
OPTIC S

HYC9058*
(HITI)

f)

OR

7#

HYC9068*
(LAND)
OR

R-3101*
(OPTO)
PORIN
CAPACITOR

(C1=0.1 JlF)

Ib

'HYC9058

- High Impedance
Transceiver (HITI)
Seepage 257

HYC9068

- Local Area Network
Driver (LAND)
See page 263

R-3101

- Pin compatible
Fiber Optic Driver
Raycom Systems
6395 Gunpark Drive
Boulder Colorado 80301

RESET IN

FIGURE 3: COM91C32 SYSTEM INTERFACE

TIL INPUT
CLOCK

I
I'

I,
I

CA
LANCLK

J

18
16

,i

.1II,1

t

14 ___

L

t,

4.5
0.5

Ii

r-

.11

-'--15

FIGURE 4: COM91C32 CLOCK TIMING

TABLE 1 - COM91 C32 ELECTRICAL CHARACTERISTICS
MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ............................................................... O°C to 70°C
Storage Temperature Range .............................................................. -55°C to 150°C
Lead Temperature (soldering, 10 sec.) .............................................................. 325°C
Positive Voltage on any Pin ..................................................................... Vee + 0.3
Negative Voltage on any Pin ...................................................................... -0.3V
Maximum Vee ................................................................................... + 7.0V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied.
250

DC CHARACTERISTICS (T. = O°C to +70°C, Vee =5V ± 5%)
MAX
MIN
TYP
PARAMETER
INPUT VOLTAGES
VIH1 High Input Voltage
2.7
0.8
VIL1 Low Input Voltage
VIH2 High Input Voltage
Vee-0.5V
1
VIL2 Low Input Voltage
VIH3 High Input Voltage
3.6
1.0
VIL3 Low Input Voltage
OUTPUT VOLTAGES
VOH1 High Output Voltage
Vee-1.0
VOL1 Low Output Voltage
0.4
VOH2 High Output Voltage
Vee-0.5
VOL2 Low Output Voltage
0.4
INPUT LEAKAGE CURRENT
IL
±10
INPUT CAPACITANCE
15
CIN
POWER SUPPLY CURRENT
20
Icc
AC CHARACTERISTICS (T. = O°C to +70°C, Vee =5V ± 5%)
FIG
PARAMETER
MIN
NO.

UNIT
V
V
V
V
V
V
V
V
V
V

except for TTL CLK and PORIN
for TTL CLK IN
for PORIN

IOH = 400 JiA except for CA, LANCLK
IOL = 4.0 mA except for CA, LANCLK
IOH = 100 JiA for CA, LANCLK
IOL = 100 JiA for CA, LANCLK

JiA
pF
mA

TYP

TTL CLOCK INPUT TIMING
Fig. 3
t, Input Clock High Time
20
h Input Clock Low Time
20
b Input Clock Period
50
CA, LANCLK OUTPUT TIMING
Fig. 3
t4 Clock Out Fall Time
t5 Clock Out Rise Time
Is Clock Out High Time
75
h Clock Out Low Time
75
Is Clock Out Period
200
TRANSMIT TIMING
Fig. 4
t9 TX Setup to CA falling edge
50
tlO TX Hold after CA falling edge
10
t11 Xtal rising edge to PULS1/2
60
t'2 PULS1/2 Pulse Width
2 (b)
t'3 INHTX to Pulse inactive
RECEIVE TIMING
Fig. 5
t' 5 RXIN Pulse Width
10
5 (b) + 70
t'6 RXIN to RXOUT delay
t17 RXOUT Pulse Width
400
t'B XTAL RISING EDGE TO RXOUT
DSYNC, CA TIMING
Fig. 5
t' 9 DSYNC Setup to CA rising edge
20
RESET TIMING
Fig. 6
bo RESET IN Pulse Width
120
b1 RESET IN falling edge to
RESET OUT falling edge
b2 RESET IN rising edge to
102
102.4
RESET OUT rising edge
b3 RESET OUT Pulse Width
1:30+b2-2b
INPUT CLOCK FREQUENCY
8.0
NOTE 1: For Input clock frequencies of less than 20 MHz, 1:30 = 21:3 + 20 ns
NOTE 2: For Input clock frequencies of less than 20 MHz, 1:3, = 21:! = 70 ns
-ALL TYPICAL VALUES ARE AT Vee = 5.0 V and TEMPERATURE = 25°C
251

COMMENTS

MAX

20
20

UNIT

COMMENTS

ns
ns
ns

@Vee-0.5V
@1V

ns
ns
ns
ns
ns

@50pFmax
@50pFmax
@50pFmax
@50pFmax
@50pFmax

100

ns
ns
ns
ns
ns

70

ns
ns
ns
ns
ns

170

ns
ns

103

us

20

MHz

(NOTE 1)
(NOTE 2)

OSC

I
I

CA

I,--_~

I

~~~€J;~~----~----------------------------------------~~
\~--~I!I~~

------~--------~---,~I'2
I

~t.,

t-111

I I

I I
j5{J[S2.----------..L.,1I

1= I

I

I

I

I

+-~'3

t=:

I
I

111

+1

-..l 1'3 L

'4"1

I

FIGURE 5: TRANSMIT TIMING PARAMETERS

OSC
RXIN

J1I

1'8 I'--+i-I'5 __________________ I

+I__J "

~~

~---------------------------

RXOUT_~I:'~I'~61[==j:J------------____------~~~[t-=~I~'8_________~==~==~~
I

CA·

DSYNC

1'7

___

~

~~-

I

1'9

I

1

SAMPLE

SAMPLE

FIGURE 6: RECEIVE TIMING PARAMETERS

lao

I

I.

RESET IN

i

i la,

I

:.

I

RESET OUT

I

.:

!++

1a2

I

1a3

I~

I

·1

i

~I

FIGURE 7: RESET IN - TO - RESET OUT TIMING

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications. consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey tothe purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supp!y the best product possible.

252

COM92C32
ADVANCED INFORMATION
PRELIMINARY

Enhanced Local Area Network Transceiver

FEATURES

PIN CONFIGURATION

D Compatible with the COM9026 and COM90C26
ARCNET® ILAN controllers
D Compatible with COM90C56 Enhanced LAN Controller
D Converts transmit data to NRZ or Manchester format
D Converts receive Manchester II data to NRZ format
D High performance DPLL for high bit jitter tolerance
D Receiver blanking circuit for ignoring line reflections,
ringing and inductive effects
D Compatible with HYC 9078
On board predistortion circuitry
On board crystal oscillator simplifies clock generation
o CLK/CA clock generation for the COM9026 and
COM90C26
o 5V only power supply
Compatible with RS-422/RS485 Transceivers
Low power CMOS
o Modem control signals
o 16 pin DIP and PLCC packages

TXOUT
TXOUT

VCC
TXENABLE

MODE

TX

RESET OUT

CA

RESET IN
XTAL2

o
o

'-..J

XTAL1fTTLCLK
GND

DSYNC/2XCLK
RXOUT
RXIN
LANCLK

'Preliminary Pin Out

o
o

GENERAL DESCRIPTION
The COM92C32 is a companion chip to the COM9026
and COM90C26 Local Area Network Controllers (LANC). It
contains all the necessary logic to interface the COM9026
and COM90C26 to baseband or broadband Local Area
Networks. It is also compatible with the COM90C56
Enhanced LANC.
During data transmission, the COM92C32 converts the
pulsed TX data signal from the COM9026 and COM90C26
to NRZ (Non Returned to Zero) format for Broadband
networks, and to Differential Manchester format for
baseband networks. It also generates a TX ENABLE
signal to enable the media driver circuitry during data
transmission.

The use of Manchester encoded data allows bus topologies
in the order of 20 nodes and 2000 feet on coaxial cables
without active repeaters. In addition, the COM92C32 can be
used with discrete RS4221485 drivers to implement the
physical layer of the ARCNET® local area network over
telephone grade twisted pair media.
When receiving data, the COM92C32 samples and
recovers the incoming receive data and presents it
synchronously to either the COM9026, COM90C26 or
COM90C56. It also performs the necessary handshake and
generation of the Bit Clock (CA) for the COM9026 and
COM90C26.
The chip incorporates a 25 MHz internal oscillator which
simplifies clock generation.

ARCNET'" is a registered trademark of the Datapoint Corporation

253

VCC t-GND t-MODE
TX

DSYNC/2XCLK
RXOUT
CA

RETIMING
~
AND
HANDSHAKE

t+-

RESET IN

fXOUf
TX ENABLE

DIFFERENTIAL
MANCHESTER TO NRZ
DECODER AND
RECEIVE CONTROL
LOGIC

RXIN

~

DIVIDE BY
FIVE

LAN CLK

RESET OUT

TXOUT

NRZ TO DIFFERENTIAL
MANCHESTER
DECODER AND
TRANSMIT CONTROL
LOGIC

r--

RESET
LOGIC

I

OSCILLATOR

XTAL1/TTLCLK

I IOXCLK

I

XTAL2

FIG. 1 - COM92C32 INTERNAL BLOCK DIAGRAM
254

TABLE 1 - COM92C32 DESCRIPTION OF PIN FUNCTIONS
PIN
NO

SYMBOL

I/O

NAME AND FUNCTION

TXOUT

0

TRANSMIT OUT-This output signal carries the transmitted serial data encoded
in either differential Manchester format or NRZ formal. In the Manchester mode
of operation, this pin will idle high when the COM92C32 is not transmitting. In the
NRZ mode, this pin will idle low when the COM902C32 is not transmitting.

TXOUT

0

TRANSMIT OUT-This output signal carries the transmitted serial data encoded
in either differential Manchester format or NRZ formal. In the Manchester mode
of operation, this pin will idle high when the COM92C32 is not transmitting. In the
NRZ mode, this pin will idle low when the COM92C32 is not transmitting.

TXENABLE

0

TRANSMIT ENABLE-This output signal is active low when the transmitted data
on TXOUT and TXOUT is valid. It is used to enable the external media driver
circuitry.

TX

I

TRANSMIT DATA-This input represents the serial data transmitted by either the
COM9026 or COM90C26.

DSYNC/
2XCLK

I

DSYNC-This active low input is asserted by the COM9026"or COM90C26 and
is used to synchronize the CA clock output of the COM92C32 to the received
data.
When the COM92C32 is used with the COM90C56 ELANC chip, this pin
becomes the 2XCLK signal from the ELANC.

CA

0

BIT CLOCK-This output is a 5 MHz start/stop clock that halts when DSYNC
goes active. DSYNC is used to synchronize the CA clock output to the RX OUT
received data.

LANCLK

0

LAN CLOCK-This output supplies a 5 MHz free runriing clock for the COM9026
or COM90C26, pin 19. It is capable of driving 50pF plus one LS/TTL load with .
20ns rise and fall times.

RXOUT

0

RECEIVE DATA OUT-This output provides tbe NRZ encoded receive data to
the COM9026 and COM90C26. This output is synchronous to the CA clock.

RXIN

I

RECEIVE DATA IN-This input receives data from the cable interface circuitry.

XTAL1ITTLCLK
XTAL2

I

CRYSTAL-An external 25 MHz crystal is connected to these pins. If an external
25 MHz TTL clock is used, it should be connected to the XTAL 1 with a 390 ohm
pullup resistor; XTAL2 must be left floating.

RESET IN

I

RESET- This signal resets the COM92C32 to a known state. In addition, it
disables the transmitter and generates the RESET OUT signal to the COM9026
and COM90C26.

RESET OUT

0

RESET OUT- This output signal provides a 102.4ps Reset signal to the
COM9026 and COM90C26.

MODE

I

MODE SELECT-This pin is used to select the mode of operation of the
COM92C32. The three possible modes are:
1) Vcc - Differential Manchester with COM9026 or COM90C26.
2) GND - NRZ Mode with COM9026 and COM90C26.
3) RESET OUT - Differential Manchester with COM90C56 (ELANC).

Vcc

-

GND

+5 Volt Power Supply
Ground

·Pin numbers to be determined

NOTE: For an updated data sheet please fill out the reply card in
the back of this catalog or call SMC at (516) 273-3100.
255

C

ClK

0

0

M

M

CA

9
0

DSYNC

9
0
2

or

C

TX

TX

C

AX

lANClK

g

TXOUT

CA

M

TXOUT

DSYNC

9
2

AXIN

AXOUT

2

6

COAX

C

f)
.......

9
0

C

7
8

3
2

6

H

y

11
0

22pF

I

I

22pF

fiG. 2 - COM92C32 TO COAX SYSTEM INTERFACE

TX

C

C

0

0

ClK

M

M

CA

9
0
2
6

or

TX

C TXENABlE

lANClK

0

CA

M

TXOUT

9
2

TXOUT

C

AXIN

9
0

DSYNC

DSYNC

C

AX

AXOUT

2
6

3
2

TWISTED
PAIR
RS-485
INTERFACE

-,("")--

-~

lOr

22pF

:c :c

22pF

FIG. 3 - COM92C32 TO TWISTED PAIR SYSTEM INTERFACE
~~~~,~ ~~.~.~:i Circuit diagrams utilizing SMC products are Included as a means of illustrating typical semiconductor appli·
;;
cations: consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
r.;~~~~.~::r..~.~;;:: assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the right to
make changes at any time in order to improve design and supply the best product possible.

256

HYC9058
PRELIMINARY

ARCNET® High Impedance Transceiver

H ITT"

PIN CONFIGURATION

FEATURES
D Compatible with existing ARCNET® installations

1
2

D Compatible with ARCNET® coax drivers
D Pin Compatible with ARCNET® fiber-optic drivers

-5v

4
5

Gnd
Rei Volt

6

D Enables Bus topology on ARCNET® LAN's

7
8
9
10
11
12
13
14

D Provides network expansion without any additional
repeaters or major rewiring

D Multi-media drive capability
D Space saving economy

15
16
17
18
19
20
L -_ _---.I

D 20 pin single in line package (SIP)
D Straight or right angle lead frame

NC
NC

3

+5v
Rx
TPA
NC
TPD
OutputS
OutputC
Gnd
Gnd
TPC
TPB
Gnd
PULS2
Disable
PULS1

D Built in filters for noise immunity

GENERAL DESCRIPTION
The High Impedance Transceiver (H IT) providesARCNET®
LAN's designers with a new bus configuration option, while
reducing hardware and installation costs. The HIT offers
ARCNET® LAN's with the ability to provide the highest node
performance/cost ratio available heretofore. The bus topology and the reduced need for HUB's (active repeaters)
eliminate the excessive costs usually associated with
installing a new LAN or modifying an existing one.

high output impedance enables it to drive several types
of media cables.

The HIT is compatible with SMC monolithic LAN controller
chip set the COM90261COM90C26 and the COM90C32.
However It can work with other controllers and its inherent

The HIT contains all the necessary filtering to guarantee
noise-immunity for interference-free data transfers at
2.5 Mbps.

The HIT is easily incorporated into existing ARCNET®
LAN's. The HIT is pin-compatible with other media drivers,
like the COAX driver currently used in most ARCNET®
baseband applications and the fiber optic driver manufactured by Raycom Systems.

257

Disable
19
-

I

-1--

-.......:!-NC

I

20
Puls1 --l...,I--I

I

PUiS2

I

Isolation
Transformer

I

18
--l-f--I

~NC

0(

Filter
and
Amplifier

2

I -NC

...
...

I12

I

FJ

~'----------L------IJ',,'y~-

I

COAX

I

I

I

I
Rx Data _-+----1
7

I

Threshold
Voltage
Detector

1---1

,I:
I.

-

I

L - - - -rs- - -t-6-F F - 13r'f
Voltage
Threshold
Adjust
(should be left open
in normal operatton)

8

~TPA

Filter

+5V

GND -5V

16

TPB

15

TPC

,r
10

lPO

GND GND GND

Figure 1-HIT Block Diagram

DESCRIPTION OF PIN FUNCTIONS
PIN#

NAME

SYMBOL

FUNCTION

1,2,9
3
4,13,14,17
5

-

NC
VDD
GND
REFV

Not used. No connection.
- 5 Volts Power Supply.
Ground
Internal Set Reference Voltage can be used to
adjust Internal Voltage Detector Threshold in
Special Situations.
Normally, this pin should not be connected.

6

VCC
RX

+ 5 Volt Power Supply.
Received Data, goes to RXIN of COM90C32 (TTL).

8,10,15,16

Power Supply
Received
Data Output
Test Points

Test Points. Make no connection to these pins.

11

COAX 1/0

TPA,TPB
TPD, TPC
OUTPUT .s

12
18
19

COAX 1/0
Pulse 2
Disable

OUTPUT C
PULS2
Disable

20

Pulse 1

PULSI

7

Power Supply
Ground
Threshold
Voltage

258

Connect to Coax Cable Shield (Outer Conductor).
Bypass to GND is recommended.
Connect to Coax Cable Inner Conductor (Center)
TTL Level Input to the Transmitter Section (Active Low).
Normally connected to ground a high
disables the transmitting.
TTL Level Input to the. Transmitter Section (Actiye Low) ...

FUNCTIONAL DESCRIPTION
The HIT integrates a host of discrete components onto a
hybrid microcircuit to provide the Local Area Network design
with space and cost reductions as well as the enhanced
reliability of a single component.
Transmit section:

Referring to the block diagram of figure 1, Pulse 1 and Pulse
2 signals can be TTL pulses of 100 nsec each with Pulse 2
delayed by 100 nsec. The optimum timing for these signals
can be obtained from SMC's COM90C32. Amplification and
filtering is used to eliminate undesirable frequencies from
the signals, while providing them with the necessary drive,
before transmitting onto the line through an isolation transformer. The driving circuitry has been designed to present
a very high impedance to the line for minimum loading. The
transformer typical voltage output is 20 volts peak to peak.
In most applications, it is recommended that the shield of
the coaxial cable be bypassed to ground by a parallel R-C
combination.
Receive section:
The received dipulse signal from the line is DC isolated by
the transformer. It is filtered to reduce noise, voltage transients and intersymbol interference. It is then recovered by
a threshold voltage detector. The minimum signal amplitude necessary for reliable operation is 6 volts peak to peak.
The TTL Rx Data output is then sent to the receive input of

the COM90C32. A voltage threshold pin can be used to vary
the threshold voltage for special situations.
In normal operation, the "disable" at pin 19 should be tied
to ground. However, in certain cases, this pin can be used
to prevent transmission.

APPLICATION INFORMATION
The hit is designed to eliminate the need for Hubs in small
(8 nodes) installations extending up to 1000 feet as shown
in figure 2. However the number of nodes is inversely proportional to the bus length.

Figure 2-Typical Small Hubless Network
'HYC 9058

Figures 3 and 4 show alternative ARCNET® local area network implementation using the "LAND" and the HIT. As can
be easily observed the straight forward approach of the HIT
version results in very low per node cost as well as ease of
installation.

Figure 3-Typical 64 Node Network Using HUBs and LANDs

259

ELECTRICAL CHARACTERISTICS
MAXIMUM GUARANTEED RATINGS":
Operating Temperature Range ..................................................................................... 0 C to + 70 C
Storage Temperature Range .................................................................................. - 40 C to + 125 C
Lead Temperature (soldering, 10 sec.) .................................................................................. + 325 C
Positive Voltage on any pin with respect to Gnd ............................................................................... 8 V
Negative Voltage on any pin except Vdd with respect to Gnd .............................................................. - 0.3 V
·Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists it is
suggested that a clamp circuit be used.

Electrical Characteristics Ta = 0 to 70 C, Vee =
Parameter
INPUT VOLTAGE LEVELS
Pulse 1, 2, DSBL inputs
Low-level, VIL
High-level, VIH
Received signal amplitude
OUTPUT VOLTAGE LEVELS
Rx Data output
Low-level, VOL
High-level, VOH
Transformer output

Min.

+ 5V ± 5%, Vdd
lYP·

= - 5V

Comments

Max

Unit

0.8

V
V
Vp-p

Iii = -.8ma
lih = .2ma

0.4

V
V
Vp-p

One TTL load
One TTL load
HYC 9058

285
270

mA
mA

2.0
6

2.4
16

POWER SUPPLY CURRENT
Icc
Idd
PULSE WIDTH
Pulse 1, 2 inputs

± 5%.

190
180
100

nsec

Shorting the transformer output can cause permanent damage to the device.

A.

B
C

H

Termination

ACTIVE HUB

Termination

G

0
E

F

Maximum Distance:
HYC 9058: 1000 ft.

Figure 4-TypIcal 64 Node Network Using HIT

260

COM90C26

COM90C32*

OR

HYC9058
(HIT)

OR

COM9026

_COM91C32

TX

TX

CA

CA

PULS2

PULS2

DSYNC

DSYNC

PULS1

PULS1

RX

RXOUT

OUTPUT C
RX

RXIN
ClK

COAX

OUTPUT S

lANClK

IDlD
IDDAT
OSC

20 MHZ
SQUARE
WAVE

SWITCH

COM90C32 - local Area Network Transceiver
See page 223
COM91C32 - Improved local Area
Network Transceiver
See page 247

Figure 5-HYC9058 System Interface

11-------- 2.080 MAX -------+i-I

1-'1
..

HYC9058

I- .100 TYP

T ~
I ;
N

COMPONENT SIDE

-.j

Lead Frame-Right Angle
Straight
-.1.400 L--IMAxlC

--+i

~- .093 MAX

Mechanical Specification
261

HYC9058R
HYC9058S

T

1.15 MAX

~ -~
.090 MAX.

ARCNET'" is a registered trademark 01 the Datapolnt Corporation

~~mCR05't'STEMS
-~==.==

~~~~il~?~~~f~~sati~~z~~fti~~n~ fg~~~~t~u~t1o~g~:O~::i: n~;~~~e~~!~~~t~~!~~ r~~~~~oa~~t\g~~~ ti~:~~~~e~~1:~

checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore,
such information does not convey to the purchaser of the products described any license under the patent rights of
SMC or others. SMC reserves the right to make changes at any time in order to improve design and supply the best
product poseible.

262

HVC9068
PRELIMINARY

ARCNET® Local Area Network Driver
LANDTM

FEATURES

PIN CONFIGURATION

o Compatible with existing ARCNET® installations
o Compatible with ARCNET® coax drivers
o Pin Compatible with ARCNET® fiber-optic drivers
o Space saving economy

-12vReturn
-12v

-5v
Gnd

TPE
+5v
Rx

TPF
TPD
TPC

020 pin single in line package (SIP)

o Straight or right angle lead frame

OutputS
outputC
Gnd
Gnd

o Built in filters for noise immunity
o Drives up to 2,000 ft. of Coax
o Replaces more than 25 discrete

TPB
TPA
Gnd
Puls2
Disable

components and IC's

Puiii1

GENERAL DESCRIPTION
The HYC9068 is a Coax Driver for ARCNET Local Area
Networks. The HYC9068 is compatible with SMC's
COM9026ICOM9OC26 Local Area Network Controller (LANC)
and the COM90C32 Local Area Network Transceiver (LANl).
The HYC9068 simplifies network implementation while pro-

263

viding considerable space and cost savings plus the high
reliability of a single component.
The HYC9068 contains both receive and transmit filters to
guarantee interference-free data transfer over 2,000 ft. of
RG-62 coaxial cable at 2.5 Mbps data rate.

_f9Disable

I

~
Isolation
Transformer

Pulsl ---j20--+!_---1

I

18
Puls2

I

1--1_

Filter
and
Amplifier

9_

12V

TPD

'''F~J

---j~----1

~,----~!,,:y C~

I

I
I
I

Threshold
Rx Data _7....,11-----1 Voltage
Detector

I~TPF

I

Filter

16

I: "

I
1

L

-12V RETURN

1 2

10

---~-t-6 FF-"f'f,r
TPE

+5V

GND -5V

TPA

TP8
TPC

GND GND GND

FIGURE 1-HYC9068-LAND BLOCK DIAGRAM

DESCRIPTION OF PIN FUNCTIONS
PIN#
1

NAME
-12V Return

SYMBOL
GND

FUNCTION
-12V Return
-12V Power Supply

2

Power Supply

Vss

3

Power Supply

VDD

-5 Volts Power Supply.

4,13,14,17

Ground

GND

Ground

6

Power Supply

VCC

+ 5 Volt Power Supply.

7

Received
Data Output

RX

Received Data, goes to RXIN of COM9OC32 (TTL).

8,10,15,16,5,9

Test Points

TPA, TPB, TPE
TPD, TPC, TPF

Test Points. Make no connection to these pins.

11

COAX I/O

OUTPUT S

Connect to Coax Cable Shield (Outer Conductor).
Bypass to GND is recommended.

12

COAX 110

OUTPUT C

Connect to Coax Cable
Inner Conductor (Center).

18

Pulse 2

PULS2

TTL Level Input to the Transmitter
Section (Active Low).

19

Disable

Disable

Normally connected to ground a high
disables the transmitting.

20

Pulse 1

PULSl

TTL Level Input to the Transmitter
Section (Active Low).

264

FUNCTIONAL DESCRIPTION
When using the optional -12V supply, Pin 3 must not be
connected. Pin 1 must be grounded and -12V must be
applied to Pin 2.
The easiest way to create the optimsm input is to use the
SMC COM9OC32 to provide PUL 1 and PlJCS2. The
DISABLE (Pin 19) should be grounded during normal

operation.
In order to inhibit surge damage as well as limit spurious
radiation, it is suggested that the shield of the COAXIAL
CABLE be bypassed to ground by a parallel R-C Network
(0.005 JLFd/1 Kv in parallel with two 5.6K ohm/%W resistors
in series) as shown in typical interconnect diagram.

ELECTRICAL CHARACTERISTICS
MAXIMUM GUARANTEED RATINGS*:
Operating Temperature Range ............................................................................ 0 C to + 70 C
Storage Temperature Range .......................................................................... - 40 C to + 125 C
Lead Temperature (soldering, 10 sec.) .......................................................................... + 325 C
Positive Voltage on any pin with respect to Gnd ....................................................................... 8 V
Negative Voltage on any pin except Vdd and Vss with respect to Gnd .......................................... - 0.3 V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these
or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or
device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off. In addition,
voltage transients on the AC power line may appear on the DC output. If this possibility exists it is suggested that a clamp circuit be used.

Electrical Characteristics Ta
Parameter
INPUT VOLTAGE LEVELS
Pulse 1, 2, DSBL inputs
Low-level, VIL
High-level, VIH
Received signal amplitude
OUT.PUT VOLTAGE LEVELS
Rx Data output
Low-level, VOL
High-Level, VOH
Transformer output
Cable noise amplitude
POWER SUPPLY CURRENT
Icc
Idd
Iss
PULSE WIDTH
Pulse 1, 2 inputs
COAXIAL CABLE
Type RG-62 (930)

= 0 to 70 C, Vcc = + 5V
Min.

Typ.

± 5%, Vdd

= - 5V

-12V ± 5%

0.8

V
V
Vp-p

iii = -.8ma
lih = .2ma

0.4

One TTL load
One TTL load

4

V
V
Vp-p
Vp-p

250
20
50

mA
mA
mA

20

100

nsec
2,000

265

=

Unit

2.0
6

2.4
15.4

± 5%, or V ss

Max

It

Comments

COM9026

HYC9068

COM91C32*

(LAND)

OR

COM90C26
TX .......- - - - -......~TX
CA
DSYNC
RX

CA

PULS2 I-------'~ PULS2

DSYNC

PULS1 I------~ PULS1

COAX

1+_ _ _ _ _ _-\ RXOUT

POR

RESET OUT

ClK

LANClK

......-+-1 RESET IN

......---iIDlD
IDDAT

OUTPUT C
RXIN ~------I RX

OUTPUT S .......-.----4

POR IN

PORIN

~ CAPACITOR

SWITCH

* COM90C32· -Local Area Network

Transceiver is also
compatible

w~h

the

COM9026 or COM9OC26
and HYC9068.

FIGURE 2-TYPICAL HYC9068 INTERCONNECT

1
...•. . - - - - - - - 2.080 MAX -------+l~1

HYC9068

Lead Frame-Right Angle
Straight
-...J .400 I--'MAX'~·

T

I

COMPONENT SIDE

-+l I-- .100TYP

""'- .093 MAX

HYC9068R
HYC90685

C

~

N

~

T

1.15 MAX

I
D
E
.090 MAX.

FIGURE 3-MECHANICAL SPECIFICATION
ARCNET8 is a registered trademark of the Datapoint Corporation

SU\NDt\RO MICROSVSTEMS
_
maN
35Mim.15B1vi:1.I1aAIqe.IfYl1188

(5*273·3100 1Wl(·51O·227·889B

~~~~il~~~~~f~~sa~~~Z~~~i~~n~ f~~~~~~~ua~t~o~~I~~6~::i: :or~~6e~~~~Y,i~~!~R. ~~!~~~6r~~tjg~~~~ ~~;~~~i:'~}:~

checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore,
such information does not convey to the purchaser of the products described any license under the patent rights of
SMC or others. SMC reserves the right to make changes at any time in order to improve design and supply the best

product possible.

266

HYC9078
PRELIMINARY

High Impedance Transceiver
HITTM 2

FEATURES

PIN CONFIGURATION

o Compatible with SMC's COM9056 Enhanced Local
Area Network Controller (ELANC)

NC
NC

o 5 MHz operation
o High impedance
o Enables Bus topology on LAN's
o Provides network expansion without any additional

-5v
Gnd

Ref Volt

+5v
Rx

TPA

repeaters or major rewiring

NC

o Multi-media drive capability

TPD

o Space saving economy
o 20 pin single in line package (SIP)
o Straight or right angle lead frame
o Built in filters for noise immunity
o Common mode isolation
o Wide dynamic range
o Very low level receiver sensitivity

OUtput S
OutputC
Gnd
Gnd

TPC
TPB
Gnd

Pulse 2
Disable
Pulse 1
PACKAGE: 2O-pin S.l.P.

GENERAL DESCRIPTION
The HIT2 is a new media interface hybrid which works with
the ELANC in the new high speed 5Mbps mode of signalling. The HIT2 will be available in a 20pin SIP hybrid
package.
The HIT2 has been tuned to operate with the ELANC's high
speed mode and includes a specially designed receive circuit to receive data in the manchester signalling scheme.
without introducing a significant amount of bit jitter. The HIT2

also includes a transmit signal amplifier and high frequency
filter so that it generates clean signals that are free from
high order harmonics that might cause EMI problems. Both
the transmit section and receive circuit are transformer
coupled to the output and have both been designed with
very high input impedances which allow the HIT2 to be used
in bus topologies. Additionally, the large dynamic range of
the HIT2 provides very relaxed cabling restrictions.

NOTE: For an updated data sheet please fill out the reply card in
the back of this catalog or call SMC at (516) 273-3100.

267

-- f -- -- -- -- ---- -- -- -- -!
19

Disabl

I
20
Pulse 1

II
I

18 ,

i-1---

.j

Pulse 2

I
,

RxData

I

Threshold
Voltage
Detector

,

- •.
---=

Filter

l-

I

L ---- - - - - -5

-t- F F - r'f
13

+5V

-*-

NETWORK BUFFER
MANAGEMENT LOGIC

~ ili

~ ~r-In ~

III

~

C/l

~

r

TPA
TPB

15

lPC

10

TPD

GND GND

ERQ
EACK

1

~

GND

GND -5V

16

HIO/HMEM
HR
WAIT

a:
w

8

Figure 1-HIT Block Diagram

HACK~

W

i:

COAX

FIGURE 2:
ELANC INTERFACE WITH DYNAMIC BUFFER
BLOCK DIAGRAM

-

()

,

I--

6

Voltage
Threshold
Adjust

NC

1"9
1',:

~

I,

7

2
,-NC

0<

Filter
and
Amplifier

"'1---1-- NC

I

Isolation
Transformer

r--

lLS374
-

fjj

IIQ$TROBE

1-

DS
CS

I~

ERQ

a:

1-

8

-

DATA BUS

II I
II

I

RiW

8
8

cs

IS~a:~~

8

ROW ADDRESS BUS
COLUMN ADDRESS BUS

0

J:

I'{'

I

I I

ROLUCOLUMN
ADDRESSMUX

~

I

8

ELANC
COM90C56

~

a:

~

~~
~
l-

~

w
2:

'---

8}
ADDRESS

~~f5

-

64K DYNAMIC RAM

STAN~RD

_

MICROSVSTEMS
ATION
35PoWCU1Et«1,HaIppeugI.NYt178a

(51Sl2n·3IOO TWlI·Stcl·227.88!IB

Circuit diagrams utilizing SMC products are included as a means of illustrating typical applications; consequently
complete information sufficient for construction purposes is not necessarily given. The information has been carefully
checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore.
such information does not convey to the purchaser of the products described any license under the patent rights of
SMC or others. SMC reserves the right to make changes at any time in order to improve design, and supply the best
product possible.

268

- . Baud Rate Generator
D

em.

DuaJ. BaUd Rate Glrn.er&tor

18 DiP

271-2'72

14 DIP .

273-274

.+5,+12

18 DIP

271-272

+6, +12.

18 DIP

271·272

+6, +12

14 DIP

273-274

+5, +12

14 DIP

27M174

+5

WDIP

275-276

+5
+5
+5

WDIP

276-276

+6

l8DIP
l8DIP
14 DIP
l4DlP
18 DIP
18 DIP

+5

.14 DIP

277-278
277·278
279-286
279-286
277-278
277-278
279-28e

+6

~4DIP

+5

l8DIP

287-290
··267"290

COM 60l6Tm
COM5026

COM5036

COM 6016 with a.dd1t1one.l output of
inputfre~oy+ 4 (use 8136 Ol'&1C~

Dual BaUd Rate Generator

fornewdEisiJros)

COM 5016TWitJ:l. a.dd1t1one.l output of
inoot freOuenoy. +·4
COM 5026 With a.dditional output of
inPUtfre~OY + 4 (uee8146for
new desiins J
~O~.~~~With a.dd1t1onal output of
lllJ'U.t U"'I.uenoy + 4

CO:M5048
COM5046T<1l

Single Ba.ud Rate Generator

COM8046

Single Baud Rate Generator
Single BaUd Rate Generator

COM8ll6
COM8126
COM8136
C01l4.8146
COM 8146T<')
COM8166
.

COM 81066T<')

Dua.l BaUd Rate Generator
Dual Ba.ud Rate Generator.
Single Ba.ud Rate Generstor
. Single Baud Rate Generator
Dual Ba'Ud Rate Generator
Dual Ba.ud Rate Genera.tor
SIJlgleBaud Rate Genera.tor
SIJlgle :saud Rate Generator
Dual BaudRate Generator
.

Timer/mock Generator
T1n;ler/Clock Generstor

..

COM 5048 with external frequency
inoot onlv
. .
Bin/Ue +8voltversiOn of COM 6016
S:I.rutle +6 volt Vlll'Slon of COl[ 5016T
Single +5 volt VersiOn of COM 6025
Sj,pgle + 5 volt version of COM 5026T
81ngle +8 volt versiOn ofOOM6036
.8ing1e +5 volt versiOn of COM 8036T
Single + 6 volt ve:t'sion of COM 5046
Single +5 volt versiOn of COM 5046T
High-frequency oloCk input version of
COM 8116 with additiOnal output/! of
inVut.freQueno:v. + 2 and +.8
.Externe.l clock inpU~ VersiOn of
OOM8156·
.
ClIIOSU$el' Pro
Ie Olocll; and Timer
Externe.l Frequ~oy Input Vlll'Slon
Of COM 8166T

TimerlOlook Generator
COM81066,"l

Timer/Clock Genera.tor

+6

+5

+6

+6

18.DII?

+6

16 DIP

291~292 .

+5

16 DIP

291-292

8 DIP

291-292

.+6

TTL CloCk Drivel' Version of the COM81067
with 3 timers

)MB8be custom mask programmed '''For future release

269

+6

270

COM 5016
cOM5016T
COM 5036
cOM5036T
Dual Baud Rate Generator
Programmable Divider
FEATURES

PIN CONFIGURATION

o On chip crystal oscillator or external
frequency input
o Choice of 2 x 16 output frequencies
o 16 asynchronous/synchronous baud rates
o DIRECT UART/USRT/ASTRO/USYNRT
compatibility
o Full duplex communication capability
o High frequency reference output'
o TTL, MOS compatibility

XTALlEXT1 1

18 XTAL/EXT2

\..J

+5v 2

17 fT

fR 3

16 TA

RA 4

15 T,

R, 5

14 Tc

Rc 6

13 TD

RD 7

12 STT

STR 8

11 GND

+12v 9

10 fx/4*

BLOCK DIAGRAM
SIT
T,

REPROGRAMMABLE
FREQUENCY SELECT

T,
Tc

To

XTAUEXT1

DIVIDER

+2

fT

DIVIDER

... 2

fR

XTAl

~

CLOCK
BUFFER

XTALIEXT2

A A )..

+5v

*COM 5036/T only

271

GND +12v

General Description
The Standard Microsystems COM 5016/COM 5036 Dual Baud Rate Generator/Programmable Divider is an N-channel
COPLAMOS® MaS/LSI device which, from a single crystal (on-chip oscillator) or input frequency is capable of generating
32 externally selectable frequencies.
The COM 5016/COM 5036 is specifically dedicated to generating the full spectrum of 16 asynchronous/synchronous data
communication frequencies as shown in Table 1. One of the sixteen output frequencies is externally selected by four address
inputs, on each of the independent dividers, as shown in Table 1.
Internal re-programmable ROM allows the generation of other frequencies from other crystal frequencies or input frequencies. The four address inputs on each divider section may be strobe (150ns) or DC loaded. As the COM 5016/COM 5036
is a dual baud rate generator, full duplex (independent receive and transmit frequencies) operation is possible.
The COM 5016/COM 5036 is basically a programmable 15-stage feedback shift register capable of dividing any modulo
upto (2 15 -1).
By using one of the frequen€y outputs it is possible to generate additional divisions of the master clock frequency by
cascading COM 5016/COM 5036's. The frequency output is fed into the XTALlEXT input on a subsequent device. In this way
one crystal or input frequency may be used to generate numerous output frequencies.
The COM 5016/COM 5036 can be driven by either an external crystal or TTL logic level inputs; COM 5016T /COM 5036T
is driven by TTL logic level inputs only.
The COM 5036 provides a high frequency reference output at one-quarter (1 /4) the XTALlEXT input frequency.

Description of Pin Functions
Pin No.

Symbol

Name

XTALlEXT1

2
3
4-7
8

Crystal or
External Input 1
Power Supply
Vee
Receiver Output
fo
Frequency
RA, RB, Re, RD Receiver-Divisor
Select Data Bits
Strobe-Receiver
STR

10
11
12

V DD
fx/4GND
STT

Power Supply
fx/4
Ground
StrobeTransmitter

13-16

T D, T e, T B, TA

17

IT

18

XTALlEXT2

TransmitterDivider
Select Data Bits
Transmitter
Output
Frequency
Crystal or
External Input 2

9

Function

This input is either one pin of the crystal package or one polarity
of the external input.
+ 5 volt supply
This output runs at a frequency selected by the Receiver divisor
select data bits.
The logic level on these inputs, as shown in Table 1, selects the
receiver output frequency, fo'
A high level input strobe loads the receiver data (RA' R B, Re, RD) into
the receiver divisor select register. This input may be strobed or
hard-wired to a high level.
+ 12 volt supply
V4 crystal/ clock frequency reference output.
Ground
A high level input strobe loads the transmitter data (TA' T B, T e, T D)
into the transmitter divisor select register. This input may be
strobed or hard-wired to a high level.
The logic level on these inputs, as shown in Table 1, selects the
transmitter output frequency, fT'
This output runs at a frequency selected by the Transmitter divisor
select data bits.
This input is either the other pin of the crystal package or the
other polarity of the external input.

-COM 5036/T only

272

COM 5026
cOM5026T
COM 5046
cOM5046T
Baud Rate Generator
Programmable Divider
FEATURES

PIN CONFIGURATION

o On chip crystal oscillator or external
frequency input

o Choice of 16 output frequencies
o 16 asynchronous/synchronous baud rates
o Direct UART/USRT/ASTRO/USYNRT
compatibility
o High frequency reference output'
o TTL, MOS compatibility

XTAL/EXT1 1

\..J

14 fouT

XTAL/EXT2 2

13 A

+5v 3

12 B

NC 4

11 C

GND 5

10 D

NC 6

9

ST

+12v 7

B

fxl4*

BLOCK DIAGRAM

A
B
C

REPROGRAM MABLE
FREQUENCY SELECT

o

ROM

XTALlExn
DIVIDER

XTAL

~
~-----.----~
CLOCK

+2

lOUT

BUFFER

XTALlEXT2

I

L

---------------,

.,

---------

~_-----~J
A A A
+5v

*COM 5046/T only

273

GND

+12v

For additional information, consult your 1986 catalog or contact our product marketing department at (516) 273-3100.
diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
applications: consequenHy complete information sufficient for construction purposes is not necessarily given.
t~i~~~~&;~~~:= Circuit
The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is

""= .. '"1iIl'I "'''M assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
'"'' ""'00 . . "."'.... semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the best product possible.

274

COM 8046
cOM8046T

Baud Rate Generator
Programmable Divider
FEATURES

o On chip crystal oscillator or external
frequency input
o Single + 5v power supply
o Choice of 32 output frequencies
o 32 asynchronousl synchronous baud rates
o Direct UART/USRT/ASTRO/USYNRT

compatibility
ORe-programmable ROM via CLASp®
technology allows generation of other
frequencies
o TTL, MaS compatible
o 1XClockviafo/160utput
o Crystal frequency output via fx and fxl 4
outputs
o Output disable via FENA

PIN CONFIGURATION
XTAL/EXT1
XTALlEXT2 2
+5v 3
fx 4
GND 5
fo/16 6
FENA 7
E 8

"-J

16
15
14
13
12
11
10

fo
A
B

C
D
ST
fx/4
9 NC

BLOCK DIAGRAM
ST>--"'"

A
B
C
D

REPROGRAM MABLE
FREQUENCY SELECT
DIVIDER
ROM

E

10
XTALlEXT1
XTAL/EXT2

XTAL

L

DIVIDER

CLOCK
BUFFER

10/16
FENA

Ix

~

+5v

A

Ix/4

GND

275

General Description
The Standard Microsystems COM 8046 is an enhanced version of the COM 5046 Baud Rate
Generator. It is fabricated using SMC's patented
COPLAMO~® and CLASP,®. technologies and employs depletion mode loads, allowing operation from
a single + 5v supply.
The standard COM 8046 is specifically dedicated to
generating the full spectrum of 16 asynchronousl
synchronous data communication frequencies for 1X,
16X and 32X UARTIUSRT1ASTR.O/USYNRT devices.
The COM 8046 features an internal crystal oscillator
which may be used to provide the master reference
frequency. Alternatively, an external reference may be
supplied by applying complementary TTL level signals to pins 1 and 2. Parts suitable for use only with an
external TTL reference are marked COM 8046T. TTL
outputs used to drive the COM 8046 or COM 8046T
should not be used to drive other TIL inputs, as noise
immunity may be compromised due to excessive
loading.
The reference frequency (fx) is used to provide two
high frequency outputs: one at fx and the other at
fx/4. The fx/4 output will drive one standard 7400
load, while the fx output will drive two 74LS loads.
The output of the oscillatorlbuffer is applied to the
divider for generation of the output frequency fa. The
divider is capable of dividing by any integer from 6

to 2" + 1, inclusive. If the divisor is even, the output
will be square; otherwise the output will be high
longer than it is low by one fx clock period. The output
of the divider is also divided internally by 16 and made
available at the fo/16 output pin. The fo/16 output will
drive one and the fa output will drive two standard
7400 TTL loads. Both the fa and fo/16 outputs can be
disabled by supplying a low logic level to the FENA
input pin. Note that the FENA input has an internal
pull-up which will cause the pin to rise to approximately Vee if left unconnected.
The divisor ROM contains 32 divisors, each 19 bits
wide, and is fabricated· using SMC's unique CLASp®
technology. This process permits reduction of turnaround-time for ROM patterns.
The five divisor select bits are held in an externally
strobed data latch. The strobe input is level sensitive:
while the strobe is high, data is passed directly
through to the ROM. Initiation of a new frequency is
effected within 3.51's of a change in any of the five
divisor select bits; strobe activity is not required.
This feature may be disabled through a CLASP® programming option causing new frequency initiation to
be delayed until the end of the current fa half-cycle
All five data inputs have pull-ups identical to that
of the FENA input, while the strobe input has no
pull-up.

Description of Pin Functions
Pin No.

Symbol

Name

Function

XTALlEXT1

Crystal or
External Input 1
Crystal or
External Input 2
Power Supply
fx
Ground

This input is either one pin of the crystal package or one polarity
of the external input.
This input is either the other pin of the crystal package or the other
polarity of the external input.
+ 5 volt supply
Crystall clock frequency reference output
Ground
1X clock output
A low level at this input causes the fa and fo/16 outputs to be
held high. An open or a high level at the FENA input enables the
fa and fo/16 outputs.
Most significant divisor select data bit. An open at this input is
equivalent to a logic high.
No connection
V4 crystal 1clock frequency reference output.
Divisor select data strobe. Data is sampled when this input is high,
preserved when this input is low.
Divisor select data bits. A = LSB. An open circuit at these inputs
is equivalent to a logic high.
16X clock output

2

XTALlEXT2

3
4
5
6
7

Vee
fx
GND
fo/16

fo/16

FENA

Enable

8

E

E

9
10
11

NC

NC

fx/4

fx/4

ST

Strobe

12-15

D,C,B,A

D,C,B,A

16

fa

fa

For electrical characteristics, see page 281.

276

COM 8116
COM 8116T
COM 8136
COM 8136T
Dual Baud Rate Generator
Programmable Divider
PIN CONFIGURATION

FEATURES

D On chip crystal oscillator or external

XTALlEXT1 1

frequency input
D Single + 5v power supply
D Choice of 2 x 16 output frequencies
D 16 asynchronous/synchronous baud rates
D Direct UART/USRT/ASTRO/USYNRT
compatibility
D Full duplex communication capability
D High frequency reference outputD Re-programmable ROM via CLASp®
technology allows generation of other
frequencies
D TTL, MaS compatibility
D Compatible with COM 5016/COM 5036

18 XTALlEXT2

\.J

17 fT

+5v 2

fR 3

16 TA

RA 4

15 TB

RB 5

14 Tc

Rc 6

13 TD

RD 7

12 STT

STR 8

11 GND

NC 9

10 fx/4"

BLOCK DIAGRAM
STT

T,

REPROGRAMMABLE
FREQUENCY SELECT

T.
Tc
To

XTAUEXTl

DIVIDER

+2

fr

DIVIDER

+2

f.

XTAL

~

CLOCK
BUFFER

XTAL'EXT2

A A

+5v
STR

"COM 8136fT only

277

GND

General Description
The Standard Microsystem's COM 8116/COM 8136 is an
enhanced version of the COM 5016/COM 5036 Dual Baud
Rate Generator. It is fabricated using SMC's patented
COPLAMOS$ and CLASP$ technologies and employs
depletion mode loads, allowing operation from a single +5v
supply.

other TTL inputs, as noise immunity may be compromised
due to excessive loading.
The output of the oscillator/buffer is applied to the dividers
for generation of the output frequencies fn fRo The dividers
are capable of dividing by any integer from 6 to 2'· + 1,
inclusive. If the divisor is even, the output will be square;
otherwise the output will be high longer than it is low by one
Ix clock period.

The standard COM 8116/COM 8136 is specifically dedicated to generating the full spectrum of 16 asynchronous!
synchronous data communication frequencies for 16X
UART/USRT devices. A large number of the frequencies
available are also useful for 1X and 32X ASTRO/USYNRT
devices.

The reference frequency (Ix) is used to provide a high frequency output at fxl4 on the COM 81361T.
Each of the two divisor ROMs contains 16 divisors, each 19
bits wide, and is fabricated using SMC's unique CLASp®
technology allowing up to 32 different divisors on custom
parts. This process permits reduction of turn-around time
for ROM patterns. Each group of four divisor select bits is
held in an externally strobed data latch. The strobe input is
level sensitive: while the strobe is high, data is passed directly
through to the ROM. Initiation of a new frequency is effectedwithin 3.5fLS of a change in any of the four divisor select bits
(strobe activity is not required). The divisor select inputs have
pull-up resistors; the strobe inputs do not.

The COM 8116/COM 8136 features an internal crystal oscillator which may be used to provide the master reference
frequency. Alternatively, an external reference may be supplied by applying complementary TTL level signals to pins
1 and 18. Parts suitable for use only with an external TTL
reference are marked COM 8116T/COM 8136T. TTL outputs used to drive the COM 8116/COM 8136 or COM 8116TI
COM 8136T XTALlEXT inputs should not be used to drive

Description of Pin Functions
Pin No.

Symbol

2

3
4-7

8

Crystal or
External Input 1
Power Supply
Receiver Output
Frequency
RA, RB, Re, RD Receiver-Divisor
Select Data Bits
STR
Strobe-Receiver

9

NC

10
11
12

fx/4"

fx/4

GND
STT

Ground
StrobeTransmitter

13-16

17
18

XTALlEXT2

"COM 81361T only

Function

Name

XTALlEXT1

This input is either one pin of the crystal package or one polarity
olthe external input.
+ 5 volt supply
This output runs at a frequency selected by the Receiver divisor
select data bits.
The logic level on these inputs, as shown in Table 1, selects the
receiver output frequency, fRo
A high level input strobe loads the receiver data (R A, RB, Re , RD) into
the receiver divisor select register. This input may be strobed or
hard-wired to a high level.

No Connection

TransmitterDivider
Select Data Bits
Transmitter
Output
Frequency
Crystal or
External Input 2

V4 crystall clock frequency reference output.
Ground
A high level input strobe loads the transmitter data (TA' T B, T e , To)
into the transmitter divisor select register. This input may be
strobed or hard-wired to a high level.
The logic level on these inputs, as shown in Table 1, selects the
transmitter output frequency, fT'
This output runs at a frequency selected by the Transmitter divisor
select data bits.
This input is either the other pin of the crystal package or the
other polarity of the external input.

For electrical characteristics, see page 281.
278

COM 8126
COM 8126T
COM 8146
COM 8146T

Baud Rate Generator
Programmable Divider
FEATURES

PIN CONFIGURATION

D On chip crystal oscillator or external
frequency input

D Single + 5v power supply
D Choice of 16 output frequencies
D 16 asynchronous/synchronous baud rates

XTAUEXT1 1

\..J

14 fouT

XTAUEXT2 2

13 A

D Direct UART/USRT/ASTRO/USYNRT

+5v 3

12 B

compatibility
D High frequency reference outputD Re-programmable ROM via CLASp®
technology allows generation of other
frequencies
TTL, MaS compatibility
D Compatible with COM 5026/COM 5046

NC 4

11 C

GND 5

o

10 0

NC 6

9

ST

NC 7

8

fx/4 *

BLOCK DIAGRAM

ST'---

A
8
C

REPROGRAMMABLE
FREQUENCY SELECT

D

ROM

XTAUEXT1
DIVIDER

XTAL

~
~-----.~----~
CLOCK

+2

fOUT

BUFFER

XTAUEXT2

1--------------------------,
I

I

I

+4

I

fx/4* I

~----------~

L ___________ ~ __ J

k A

+5v

*COM 8146IT only

279

GND

General Description
The Standard Microsystem's COM 8126/COM 8146 is
an enhanced version of the COM 5026/COM 5046 Baud
Rate Generator. It is fabricated using SMC's patended
COPLAMOS® and CLASp® technologies and employs
depletion mode loads, allowing operation from a single
+5vsupply.
The standard COM 8126/COM 8146 is specifically dedicated to generating the full spectrum of 16 asynchronous/
synchronous data communication frequencies for 16X
UART/USRT devices. A large number of the frequencies
available are also useful for IX and 32X ASTRO/USYNRT
devices.
The COM 8126/COM 8146 features an internal crystal oscillator which may be used to provide the master reference
frequency. Alternatively, an external reference may be supplied by applying complementary TTL level signals to pins
1 and 2. Parts suitable for use only with an external TTL reference are marked COM 8126T/COM 8146T. TTL outputs
used to drive the COM 8126/COM 8146 or COM 8126T/COM
8146T XTALlEXT inputs should not be used to drive other
TTL inputs, as noise immunity may be compromised due to
excessive loading.

The output of the oscillator/buffer is applied to the divider
for generation of the output frequency. The divider is capable of dil/iding by any integer from 6 to 2 19 + 1, inclusive. If
the divisor is even, the output will be square; otherwise the
output will be high longer than it is low by one fx clock period.
The reference frequency (fx) is used to provide a high frequency output at fxl4 on the COM 81461T.
The divisor ROM contains 16 divisors, each 19 bits wide,
and is fabricated using SMC's unique CLASp® technology.
This process permits reduction of turnaround time for ROM
patterns. The four divisor select bits are held in an externally strobed data latch. The strobe input is level sensitive:
while the strobe is high, data is passed directly through to
the ROM. Initiation of a new frequency is affected within
3.5f1s of a change in any of the four divisor select bits (strobe
activity is not required). This feature may be disabled through
a CLASp® programming option causing new frequency initiation to be delayed until the end of the current fouT half-cycle.
The divisor select inputs have pull-up resistors; the strobe
input does not.

Description of Pin Functions
Pin No_

Symbol

Name

Function

XTALlEXTl

Crystal or
External Input 1
Crystal or
External Input 2
Power Supply
No Connection
Ground
fx/4
Strobe

This input is either one 'pin of the crystal package or one polarity
of the external input.
This input is either ttie other pin of the crystal package or the other
polarity of the external input.
+ 5 volt supply

2

XTALlEXT2

3
4,6,7
5
8
9

Vee
NC
GND
fx/4 •
ST

10-13

D,C,B,A

14

fOUT

Divisor Select
Data Bits
Output
Frequency

Ground
V4 crystal/ clock frequency reference output.
A high level strobe loads the input data (A, B, C, D) into the input
divisor select register. This input may be strobed or hard-wired to
a high level.
The logic level on these inputs as shown in Table 1, selects the
output frequency.
This output runs at a frequency selected by the divisor select
data bits.

'COM 8146/T only

280

ELECTRICAL CHARACTERISTICS COM8046, COM8046T, COM8116, COM8116T, COM8126,
COM8126T, COM8136, COM8136T, COM8146, COM8146T

MAXIMUM GUARANTEED RATINGS"
Operating Temperature Range
,,,,,,,' ,' ,,,..
' . , ... , ..... O°C to + 70°C
Storage Temperature Range
... , .. , .... -55°C to + 150°C
Lead Temperature (soldering. 10 sec.) ......
. ..... , .. . .
. . , ..... , . .
. . , ............... +325°C
Positive Voltage on any Pin. with respect to ground
.. , , , , ..... , . .
, . . . . . . . . . .. + 8.0V
Negative Voltage on any Pin. with respect to ground ......... ,....
,., ...... , .............. -0.3V
• Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transients on the AC power line may appear on the DC output. If this possibility
exists it is suggested that a clamp circuit be used.
ELECTRICAL CHARACTERISTICS (TA=O°C to 70°C. Vcc= +5V :':5%. unless otherwise noted)
Parameter

Min.

D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, V"
High-level, V'H
OUTPUT VOLTAGE LEVELS
Low-level, Va'

High-level, VOH
INPUT CURRENT
Low-level, I"
INPUT CAPACITANCE
All inputs, C'N
EXT INPUT LOAD
POWER SUPPLY CURRENT

Typ.

Max.

Unit

0.8

V
V

excluding XTAL inputs

0.4
0.4
0.4

V
V
V
V

1.6mA, for fx/4, fo/16
IOL = 3.2mA, for fa, fR' fT
10L = 0.8mA, for fx
IOH=-100I'A; for fx, IOH=-50I'A

-0.1

mA

V'N=GND, excluding XTAL inputs

10
10

pF

V'N = GND, excluding XTAL inputs
Series 7400 equivalent loads

bO

mA

0.01

7.0

MHz

0.01

5.1

MHz

150

DC

ns

2.0

3.5

5
8

Icc
A.C. CHARACTERISTICS
CLOCK FREQUENCY, f'N

STROBE PULSE WIDTH, t pw
INPUT SET-UP TIME
tDS
INPUT HOLD TIME
tOH
STROBE TO NEW FREQUENCY DELAY

Comments

10L =

TA= +25°C
XTALlEXT,50% Duty Cycle ±5%
COM 8046, COM 8126, COM 8146
XTAL/EXT,50% Duty Cycle ±5%
COM 8116, COM 8136

ns

200
50
3.5

ns
I'S

@f,=5.0MHz

TIMING DIAGRAM

t------- I p w - - - - - - - I
STROBE

1 - - - - - - - - - 1 0 5 --------_~

DIVISOR
SELECT
DATA

V'H

281

External Input Operation
COM 8116/COM 8116T
COM 8136/COM 8136T

Crystal Operation
COM 8116
COM 8136

74XX

74XX

TTL

TTL

74XX-totem pole or open collector output (external
pull-up resistor required)

Crystal Operation
COM 8126
COM 8146
COM 8046

External Input Operation
COM 8126/COM 8126T
COM 8146/COM 8146T
COM 8046/COM 8046T

74XX
TTL

74XX
TTL

74XX-totem pole or open collector output (external
pull-up resistor required)

For ROM re-programming SMC has a computer program available whereby the customer
need only supply Ihe input Irequency and Ihe desired output frequencies.
The ROM programming is automatically generaled.

Crystal Specifications
User must specify termination (pin, wire, other)
Prefer: HC-18/U or HC-25/U
Frequency - 5.0688 MHz, AT cut
Temperature range O°C 10 70°C
Series resistance <50

n

Series Resonant
Overall tolerance:!: .01 %
or as required

282

Crystal manufacturers (Partial List)
Northern Engineering Laboratories
357 Beloit Street
Burlington, Wisconsin 53105
(414) 763-3591
Bulova Frequency Control Products
61-20 Woodside Avenue
Woodside, New York 11377
(212) 335-6000
CTS Knights Inc.
101 East Church Street
Sandwich, Illinois 60548
(815) 786-8411
Crystek Crystals Corporation
1000 Crystal Drive
Fort Myers, Florida 33901
(813) 936-2109

COM 8046
cOM8046T

Table 2
REFERENCE FREQUENCY = 5.068800MHz
Divisor
Select

EDCBA
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

Desired
Baud
Rate
50.00
75.00
110.00
134.50
150.00
200.00
300.00
600.00
1200.00
1800.00
2400.00
3600.00
4800.00
7200.00
9600.00
19200.00
50.00
75.00
110.00
134.50
150.00
300.00
600.00
1200.00
1800.00
2000.00
2400.00
3600.00
4800.00
7200.00
9600.00
19200.00

Clock
Factor
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
32X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X
16X

Desired
Frequency
(KHz)
1.60000
2.40000
3.52000
4.30400
4.80000
6.40000
9.60000
19.20000
38.40000
57.60000
76.80000
115.20000
153.60000
230.40000
307.20000
614.40000
0.80000
1.20000
1.76000
2.15200
2.40000
4.80000
9.60000
19.20000
28.80000
32.00000
38.40000
57.60000
76.80000
115.20000
153.60000
307.20000

Divisor
3168
2112
1440
1177
1056
792
528
264
132
88
66
44
33
22
16
8
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16

283

Actual
Baud
Rate
50.00
. 75.00
110.00
134.58
150.00
200.00
300.00
600.00
1200.00
1800.00
2400.00
3600.00
4800.00
7200.00
9900.00
19800.00
50.00
75.00
110.00
134.52
150.00
300.00
600.00
1200.00
1800.00
2005.06
2400.00
3600.00
4800.00
7200.00
9600.00
19800.00

Actual
Frequency
(KHz)
1.600000
2.400000
3.520000
4.306542
4.800000
6.400000
9.600000
19.200000
38.400000
57.600000
76.800000
115.200000
153.600000
230.400000
316.800000
633.600000
0.800000
1.200000
1.760000
2.152357
2.400000
4.800000
9.600000
19.200000
28.800000
32.081013
38.400000
57.600000
76.800000
115.200000
153.600000
316.800000

Deviation
0.0000%
0.0000%
0.0000%
0.0591%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
3.1250%
3.1250%
0.0000%
0.0000%
0.0000%
0,0166%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.2532%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
3.1250%

284

COM 8116T

Baud Rate Generator Output
Frequency Options
COM 8116T·OO3

COM 8116T·013
CRYSTAL FREQUENCY
Transmit!
Receive
Address
0 C B A

0
0
0
0

a
0
0
0
1
1
1
1
1
1
1
1

0
0
0

a
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1

a
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1

= 2.76480 MHz

Baud

Theoretical
Frequency

Actual
Frequency

Rate

16XCIock

16XCIock

50
75
110
134.5
150
200
300
600
1200
1800
2000
2400
a 3600
1
4800
0
9600
1 19,200

Percent
Error

0.8 KHz
0.8 KHz
1.2
1.2
1.76
1.76
2.152
2.152
2.4
2.4
3.2
3.2
4.8
4.8
9.6
9.6
19.2
19.2
28.8
28.8
32.0
32.149
38.4
38.4
57.6
57.6
76.8
76.8
153.6
153.6
307.2
307.2

0
0
-.006
-.019
0
0
0
0
0
0
+.465

a
0
0

a
a

CRYSTAL FREQUENCIES

8:~r8
%

Divisor

50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50150
44/56

3456
2304
1571
1285
1152
864
576
288
144
96
86
72
48
36
18
9

Transmit!
Receive
Address
0 C B A

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0

a
a
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0

a
1
1

Baud

Frequency

Rate

16XCIock

16XCIock

0
50
75
1
110
0
1
134.5
150
0
200
1
0
300
1
600
1200
0
1800
1
0
2000
1
2400
3600
0
4800
1
9600
0
1 19,200

0.8 KHz
799.9Hz
1.2
1200.0
1.76
1759.7
2.152
2151.7
2399.6
2.4
3.2
3199.5
4.8
4799.3
9598.6
9.6
19227.9
19.2
28.8
28795.9
32.0
32012.5
38333.4
38.4
57868.7
57.6
76.8
77158.3
153.6
154316.6
307.2
300917.5

COM 8116T·013A
CRYSTAL FREQUENCY-5.52960 MHz
Transmit!
Receive
Address
0 C B A

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0

a
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Baud
Rate

100
150
220
269
300
400
600
1200
2400
3600
4000
4800
7200
9600
19,200
38,400

Theoretical
Frequency

Frequency

16XCIock

16XCIock

106KHz
2.4
3.52
4.304
4.8
6.4
9.6
19.2
38.4
57.6
64.0
76.8
115.2
153.6
307.2
614.8

1.6KHz
2.4
3.5197
4.3032
4.8
6.4
9.6
19.2
38.4
57.6
64.298
76.8
115.2
153.6
307.2
614.8

Duty

Actual

285

Percent
Error

Cycle
%

Divisor

0
0
-.006
-.019
0
0
0
0
0
0
+.466
0
0
0

50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
44/56

3456
2304
1571
1285
1152
864
576
288
144
96
86
72
48
36
18
9

a
a

= 6.01835 MHz

Actual

Theoretical
Frequency

Duty
Percent
Error

0
0
0
0
0
0
0
0
+0.14
0
0
-0.17
+0.46
+0.46
+0.46
2.04

Cycle
Divisor
%

50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50lSO
50/50
50150
50/50
50/50
50/50
50/50

7523
5015
3420
2797
2508
1881
1254
627
313
209
188
157
104
78
39
20

f,

~

~

RCP

RSI
COM 8017
COM 2017

DUAL
BAUD RATE GENERATOR

UART

fT

TCP

TSO

t

I

Typical UART-Dual Baud Rate Generator Configuration
Full Duplex-Split Speed

R.
R,
R,

BA

TSO

BB

RSI

COM 1671
ASTRO

XTAL

.-------l

D

1-----,

R

R
'><>----~XTAL/EXTI

""~--'- XTAL/EXT2

Typical External Oscillator Hook·Up

L-_ _ _ _ _. -

To System

+v
XTALlEXT1

~

c:::JXTAL
COM 8XXX

TT

To System

50-100 PF

XTAL/EXT2

I

Generation of Communication Reference Frequency and
System Clock from a single crystal

i

iiiil~~;!;!!! Circuit
diagrams
utilizing oomplete
SMC products
are included
means of illustrating
semiconductor
applications:
oonsequently
information
sufficientas
foraoonstruction
purposes istypical
not necessarily
given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsiDllity is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design anCi supply the best product possible.

286

COM 8156
COM 8156T
PRELIMINARY

Dual Baud Rate Generator
Programmable Divider
PIN CONFIGURATION

FEATURES

o On chip crystal oscillator or external frequency input
. 0 High crystal/clock frequency operation

Rb
Rc
Rd
STR
XTAL"

o Choice of 2 x 16 output frequencies
016 asynchronous/synchronous baud rates

o High frequency reference outputs
o Direct UART/USRT/ASTRO/USYNRT compatibility
o Full duplex communication capability

10/4

ON-channel silicon gate technology

GND

o Single + 5v power supply
o TTL, MOS compatibility

STT
Td

2
3
4
5
6
7
8
9

18
17
16
15
14
13
12
11
10

Ra
IA

Vee
XTAL,
10
IT

Ta
Tb
Te

ORe-programmable ROM technology allows generation
of other frequencies

BLOCK DIAGRAM

T,
Tb
T,
Td

XTAU
EXT 1

BUFFER
C
I
L
L

·XTAU
EXT2

IT

0
S
10

A
T
0
R

10 -;- 4

BUFFER

+5V~

GINO

287

IR

GENERAL DESCRIPTION
The Standard Microsystem's COM8156 is a dual baud rate
generator that operates at twice the crystal/clock frequency
of the COM8116/36. It is fabricated using SMC's patented
COPLAMOS'· technology and employs depletion mode
loads allowing operation from a single + 5V supply.
The standard COM8156 is specifically dedicated to generating the full spectrum of 16 asynchronous/synchronous
data communication frequencies for 16X UART/USRT
devices. A large number of the frequencies available are
also useful for 1X and 32X ASTRO/USYNRT devices.
The COM8156 features an internal crystal oscillator which
may be used to provide the master reference frequency.
Alternatively. an external reference may be supplied by
applying complementary TTL level signals to pins 1 and·9.
Parts suitable for use only with an external TTL reference
are marked COM 8156T. TTL outputs used to drive the
COM8156 or COM8156T XTAUEXT inputs should not be
used to drive other TTL inputs. as noise immunity may be
compromised due to excessive loading.

The output of the oscillator/buffer is applied to the dividers
for generation of the output frequencies fTo fRo The dividers
are capable of dividing by an integer from 6to 2 '9 + 1. inclusive. If the divisor is even. the output will be square; otherwise the output will be high longer that it is low by one fo
clock period.
The crystal frequency is divided by two to give (fel and again
by four to give (fo/4)' The transmit (fT) and receive (fR) frequencies are obtained by dividing (fo) by N. Up to 32 different divisors can be mask-programmed on custom parts to
accommodate different crystal frequencies and divider
schemes. Each group of four divisor select bits is held in an
externally strobed data latch. The strobe input is level sensitive: while the strobe is high. data is passed directly through
to the ROM. Initiation of a new frequency is effected within
3.5us of a change in any of the four divisor select bits (strobe
activity is not required). The divisor select bits (strobe activity is not required). The divisor select inputs and the strobe
inputs have pull-up resistors.

DESCRIPTION OF PIN FUNCTIONS
PIN NO.
15
16
17

SYMBOL
XTAUEXT1

NAME
Crystal

FUNCTION
This input receives one pin of the crystal package.

Vee
fR

Power Supply
Receiver Output

+ 5 Volt Supply.
This output runs at a frequency selected by the Receiver
Address Inputs.

18
1-3

RaRb Re. Rd

The logic level on these inputs as shown in Table 1. selects
the receiver output frequency. f R'

4

STR

Receiver
Divisor Select
Address
Strobe-Receiver
Address

5

XTAUEXT2

6

fO/4

7
8

GND
STT

Ground
Strobe-Transmitter
Address

9-12

Td Te. Tb Ta

13

fT

Transmitter
Divisor Select
Address
Transmitter
Output Frequency

14

fo

Crystal
Oscillator
Output

Oscillator
Output Frequency

A high-level input strobe loads the receiver address (R•• Rb•
Re. Rd ) into the receiver address register. This input may be
strobed or hard wired to + 5V.
This input receives one pin of the crystal package.
This output runs at a frequency selected by the crystal + 8.
Ground
A high-level input strobe loads the transmitter address (T••.
T b• Te. Td) into the transmitter address register. This input
may be strobed or hard wired to + 5V.
The logiC level on these inputs. as shown in Table 1. selects
the transmitter output frequency. h.
This output runs at a frequency selected by the Transmitter
Address inputs.
This output runs at a frequency selected by the crystal + 2.

288

COM8156, COM8156T

ELECTRICAL CHARACTERISTICS
MAXIMUM GUARANTEED RATINGS'

Operating Temperature Range ...................................................................... O°C to + 70°C
Storage Temperature Range ..................................................................... -55°to + 150°C
Lead Temperature (soldering, 10 sec.) .................................................................... + 325°C
Positive Voltage on any Pin, with respect to ground .......................................................... + 8.0V
Negative Voltage on any Pin, with respect to ground ......................................................... - 0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their
outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may appear on the
DC output. If this possibility exists it is suggested that a clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA = O°C to 70°C, Vee
PARAMETER
DC CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low Level V"
High Level V,H
OUTPUT VOLTAGE LEVELS
Low Level VOL

MIN

= + 5V ± 5%, unless otherwise noted)
TYP

UNIT

0.8

V
V

excluding XTAL inputs

0.4
0.4
0.5

V
V
V
V

10L
10L
10L
10H

-0.1

mA

Y'N = GND, excluding XTAL inputs

10
10

pF

Y'N = GND, excluding XTAL inputs
Series 7400 equivalent loads

60

mA

11.0
DC

MHz
ns

2.0

High Level VOH
2.4
INPUT CURRENT
Low-level, I"
INPUT CAPACITANCE
All inputs, C'N
EXT INPUT LOAD
POWER SUPPLY CURRENT
Icc
AC CHARACTERISTICS
CLOCK FREQUENCY, fiN
STROBE PULSE WIDTH, tpw
INPUT SET-UP TIME
tDS
INPUT HOLD TIME
TOH
STROBE TO NEW FREQ. DELAY
OUTPUT CLOCKS DUTY CYCLE
fo
fOl4

fA, fT
CRYSTAL CHARACTERISTICS
Series Crystal Resistance
Crystal Shunt CapaCitance

5
8

5.0
150

=
=
=
=

1.6 mA, for fO/4
3.2 mA, for fA, fT
3.2 mA, for fo
-100 floA

XTAUEXT, 50% Duty Cycle ± 5%

ns

50
50

40
45
48
30
2

COMMENTS

MAX

5

289

3.5

ns
flos

60
55
52

%
%
%

70
10

pf

@1.5VLEVEL
@1.5VLEVEL
@1.5VLEVEL
@Resonance

I~.~-------~~--------~

TIMING DIAGRAM
STROBE

.7V

+-

DIVISOR
SELECT
DATA

Baud Rate Generator Output Frequency Options
COM8156/COM8156T
CRYSTAL FREQUENCY
1l"'mltlRecelve
Address
Baud
DCBARate

~~~:~~~
16X Clock

(16X clock)

COM8156-005/COM8156T-005
CRYSTAL FREQUENCY

=10.1376 MHz
F,!q'7.~~CY Percent 8;::re
16X Clock Error
% Divisor

Tr'mitiReceive
Address
Baud
DCBARate

~~::~~~
16X Clock

o

0.8 KHz
0.8 KHz
0 0 0
50
1.2
1.2
0 0 1
75
1.76
1.7589
0 1 0 110
2.152
2.152
0 1 1 134.5
2.4
2.4
1 0 0 150
4.8
4.8
0101300
9.6
9.6
0110600
19.2
o 1 1 1 1200 19.2
28.8
28.7438
1 0 0 0 1800
32.0
31.9168
10012000
38.4
38.4
10102400
57.6
57.8258
10113600
76.8
76.8
11004800
114.306
115.2
11017200
153.6
153.6
11109600
307.2
1 1 1 1 19.200 307.2

000050
0.8 KHz
0.8 KHz 50/50 6336
o 0 0 1 75
50/50 4224
1.2
1.2
o 0 1 0 110
50/50 2880
1 .76
1 .76
o 0 1 1 134.5 2.152
2.1523 0.016 50/50 2355
2.4
2.4
o 1 0 0 150
50/50 2112
4.8
4.8
0101300
50/50 1056
0110600
9.6
9.6
50/50 528
19.2
19.2
o 1 1 1 1200
50/50 264
28.8
28.8
1 0 0 0 1800
50/50 176
10012000
32.0
32.081
0.253 50/50 158
10102400
50/50 132
38.4
38.4
50/50
88
10113600
57.6
57.6
11004800
50/50
66
76.8
76.8
11017200
50/50
44
115.2
115.2
11109600
153.6
153.6
48/52
33
1 1 1 1 19.200 307.2
316.8
3.125 50/50
16

o
o
o
o

Crystal Operation

(16X clock)

=9.8304 MHz
F'::"~~CY Percent g:,:re
16X Clock Error
% Divisor
-

50/50
50/50
•
50/50
50/50
50/50
50/50
50/50
-0.19'
-0.2650/50
50/50
0.39'
50/50
-0.77
50/50
50/50
-0.01

6144
4096
2793
2284
2048
1024
512
256
171
154
128
85
64
43
32
16

External Input Operation
74XX

TTL

74XX-totem pole or open collector output (external
pull·up resistor required)

For ROM re-programming SMC has a computer program available whereby the customer
need only supply the input frequency and the desired output frequencies.
The ROM programming is automatically generated.

Crystal Specifications
User must specify termination (pin, wire, other)
Prefer: HC-18/U or HC-25/U
Frequency: 10.1376 MHz, AT cut
Temperature range O°C to 70°C
Series resistance <50 n
Series Resonant
Overall tolerance ± .01 %
or as required

Crystal manufacturers (Partial List)
Northern Engineering Laboratories
357 Beloit Street
Burlington, Wisconsin 53105
(414) 763-3591
Bulova Frequency Control Products
61-20 Woodside Avenue
Woodside, New York 11377
(212) 335-6000

CTS Knights Inc.
101 East Church Street
Sandwich, Illinois 60548
(815) 786-8411
Crystek Crystals Corporation
1000 Crystal Drive
Fort Myers, Florida 33901
(813) 936-2109

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; con~equently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is

:~~c~~~~~i~;JU;~~~r~e~~~~~d~~;he ~~~~~r~?~~:t~~s~06so~~~~~~W~bt~:s~~:;~f~:rr~~~::'~~~~~h~~~~~

at any time in order to improve design and supply the best product possible.

290

COM81C66
COM81C67
COM81C68
PRELIMINARY

Universal Rate Generator and Timer
FEATURES

PIN CONFIGURATIONS

o

Three independent 20 bit programmable counters
All counters are cascadeable
o Clock input up to 16 MHz
o Square wave, pulse, one shot modes of operation
o Inpu1 clock prescalers divide by 2, 32, or 64
o Low power CMOS
08 and 16 D.I.P. packages
o Crystal or TTL frequency source
o Single +5 Volt power supply

COMB1C66 -16 PIN VERSION

o

DO

Vee
XTAL1
XTAL2
RATE3
RATE2
D7

D1
D2

CS
RATEl
D3
D4

D6

GND

GENERAL DESCRIPTION

D5

DoOe
DoOe

COMB1C67 - CRYSTAL OSCILLATOR VERSION

The TIMER chip is a device designed to provide a
convenient and inexpensive solution to applications
requiring programmable multiple clock divider sources. The
source frequency can be either an internal crystal controlled
oscillator, or an external TTL signal. The TIMER consists of a
data input portion, a register addressing block and three
counter blocks.
The Counter blocks are accessed and programmed
independently and they can be configured to operate in
various modes simultaneously.
The TIMER chip serves a broad range of applications
some of which are: programmable rate generation, pulse
generation, motor control, real time clock, interrupt
applications and others.

DATA BUS

BSf-----'----+I

vee
GND

291

CS
RATEl
GND

2
3
4

7
6
5

Vee
XTAL1
XTAL2
RATE2

COMBl C6B - TTL CLOCK VERSION

CS2
RATEl
3
GND
4

Vee
7CLK
6 RATE3
5 RATE2

TABLE 1 - COM81C67 AND COM81C68, DESCRIPTION OF PIN FUNCTIONS
The COM81 C67 and COM81 C68 are two eight pin versions of the TIMER chip. The COM81 C68 is a TIL clock input
only and the COM81 C67 is a crystal oscillator pin connection.
PIN NO.
81C68 81C67
1
1
3
5
6
2

SYMBOL

TYPE

3
5

NAME AND FUNCTION

DO

I

DATA BUS-This input only pin is used to program and initialize the Timer.

RATE1
RATE2
RATE3

0

RATE OUTPUT-These outputs will supply the programmable rate outputs
according to the mode and preload on the specified Timer Block.

CS
XTAL1
XTAL2

I

CHIP SELECT-A low level on this input enables the processor to write to the
TIMER. When CS is high, the Data input pin is high impedance.

I

CRYSTAL-An external crystal is connected to these pins on the COM81 C67.
An external TIL clock can be used on pin 7. Pin 8 must be left floating open.
CLOCK-This is a TTL clock input used as the main clock for the COM81 C68.

2

-

7,6

7

-

CLK

I

8
4

8
4

VCC
GND

I

-

POWER-This is a +5V power supply.
GROUND

TABLE 2 - COM81C66, DESCRIPTION OF PIN FUNCTIONS
The COM81 C66 is a sixteen pin version with an internal crystal oscillator.
PIN NO.
81C66
1-3
6,7
9-11

SIGNAL

TYPE

DO-D7

I

5
12
13

RATE1
RATE2
RATE3

0

RATE OUTPUT-This output will supply the programmable rate output according to
the mode and preload on the specified Timer Block.

CS

I

CHIP SELECT-A low level on this input enables the processor to write to the
TIMER. When CS the Data input(s) are don't cares.

15
14
16

XTAL1
XTAL2

I

VCC

8

GND

-

NAME AND FUNCTION
DATA BUS-The Timer is programmed by write operations via the Data Bus.

4

CRYSTAL-An external crystal is connected to these pins on the COM81C66. An
external TIL clock can be used on XTAL1.
POWER-There is a +5V power supply.
GROUND

S)i~~~~ i~;!!.;; Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor appli,.
cations: consequently complete information s.uffici!!'nt for construction purposes is not necessarily gi,,!,~ .. T~e
Information has been carefully checked and IS believed to be entirely reliable. However, no responsibility IS
" assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the right to
make changes at any time in order to improve design and supply the best product possible.

292

Display Products
TIMING CONTllOLLBBS

TBlUIIINAL LOGIC COlV'l'B.OLLBBS

(l)M8¥be custom mask programmed

293

""""",. Display Products CONT.
VDAC~

DISPLAr COlftl\OLLBBS

("Also available as CRT8002A, B, C-001 Kata.ka.na.
CRT8002A, B, C-003, -018 6 x 7 dot matrix

VIDBO~TBZBUTESCOlftl\OLLB.S
~="::!

BOWBUFJ'EB.

VT 100 and VT220 are registered trademarks of Digital Equipment Corp.

294

CRT 5027
CRT 5037
CRT 5057

CRT Video Timer and Controller
VTAC®
FEATURES

PIN CONFIGURATION

o Fully Programmable Display Format
o

o
o

o
o
o
o
o
o
o
o
o

Characters per data row (1-200)
Data rows per frame (1-64)
Raster scans per data row (1-16)
Programmable Monitor Sync Format
Raster Scans/ Frame (256-1023)
"Front Porch"
Sync Width
"Back Porch"
I nterl ace/ Non-I nterlace
Vertical Blanking
Lock Line Input (CRT 5057)
Direct Outputs to CRT Monitor
Horizontal Sync
Vertical Sync
Composite Sync (CRT 5027, CRT 5037)
Blanking
Cursor coincidence
Programmed via:
Processor data bus
External PROM
Mask'Option ROM
Standard or Non-Standard CRT Monitor Compatible
Refresh Rate: 60Hz, 50Hz""
Scrolling
Single Line
Multi-Line
Cursor Position Registers
Character Format: 5x7, 7x9""
Programmable Vertical Data Positioning
Balanced Beam Current Interlace (CRT 5037)
Graphics Compatible

A2 [ 1
A3 [ 2
cs [ 3
R3 [ 4
R2 [ 5
GND [ 6
Rl [ 7
R~ [ 8

'-'

i5S[
10
LLl/CSYN [ 9
0
VSYN'( 11
DCC [ 12
Vee [ 13
Vee [ 14
HSYN,C 15
CRV C 16
BL[ 17
OB7 C 18
DB6 C 19
20
DB5

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Al
A0
H0
HI
H2
H3
H4
H5
H6
H7!DR5
DR4
DR3
DR2
DRI
DR~

OB~

OBI
DB2
DB3
DB4

PACKAGE: 40-Pin D,I.P,

o Split-Screen Applications
o
o
o
o
o
o
o

Horizontal
Vertical
Interlace or Non-Interlace operation
TTL Compatibility
BUS Oriented
High Speed Operation
COPLAMOS·' N-Channel Silicon
Gate Technology
Compatible with CRT 8002 VDACTM
Compatible with CRT 7004

GENERAL DESCRIPTION
The CRT Video Timer and Controller Chip (VTAC)® is a user programmable 40-pin COPLAMOS® n channel MOS/LSI
device containing the logic functions required to generate all the timing signals for the presentation and formatting of
interlaced and non-interlaced video data on a standard or non-standard CRT monitor,
With the exception of the dot counter, which may be clocked at a video frequency above 25 MHz and therefore not
recommended for MOS implementation, all frame formatting, such as horizontal, vertical, and composite sync, characters
per data row, data rows per frame, and raster scans per data row and per frame are totally user program mable, The data row
counter has been designed to facilitate scrolling,
Programming is effected by loading seven 8 bit control registersdirectlyoffan8bitbidirectionaldatabus, Fourregister
address lines and a chip select line provide complete microprocessor compatibility for program controlled setup, The device
can be "self loaded" via an external PROM tied onthe data bus as described inthe OPERATION section, Formatting can also
be programmed by a single mask option,
In addition to the seven control registers two additional registers are provided to store the cursor character and data
row addresses for generation olthe cursor video signal. The contents of these two registers can also be read out onto the
bus for update by the program,
Three versions of the VTAC® are available, The CRT 5027 provides non-interlaced operation with an even or odd
number of scan lines per data row, or interlaced operation with an even number of scan lines per data row, The CRT5037
may be programmed for an odd or even number of scan lines per data row in both interlaced and non-interlaced modes,
Programming the CRT 5037 for an odd number of scan lines per data row eliminates character distortion caused by the
uneven beam current normally associated with odd field/even field interlacing of alphanumeric displays,
The CRT 5057 provides the ability to lock a CRT's vertical refresh rate, as controlled by the VTAC's® vertical sync
pulse, to the 50 Hz or 60 Hz line frequency thereby eliminating the so called "swim" phenomenon, This is particularly
well suited for European system requirements, The line frequency waveform, processed to conform to the VTAC's®
specified logic levels, is applied to the line lock input. The VTAC® will inhibit generation of vertical sync until a zero to.
one transition on this input is detected, The vertical sync pulse is then initiated within onescan line after this transition
rises above the logic threshold of the VTAC,®
To provide the pin required for the line lock input, the composite sync output is not provided in 'the CRT 5057,

295

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.
~~~~i~~_~~~.; Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
applications: consequently complete information sufficient for construction purposes is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsitillity is
",,,'",,,,"'",,,,. "''''' assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
"", ",.,,"" . "',."',.",.... semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the best product possible.

5

296

CRT 5047

Preprogrammed CRT Video Timer and Controller
VTAC®
FEATURES

PIN CONFIGURATION

o Preprogrammed (Mask-Programmed)
o

Display Format

BO Characters Per Data Row
24 Data Rows Per Frame
9 Scan Lines Per Data Row
Preprogrammed Monitor Sync Format
262 Scan Lines Per Frame
6 Character Times for Horizontal Front Porch
B Character Times for Horizontal Sync Width
6 Character Times for Horizontal Back Porch
16 Scan Lines for Vertical Front Porch
3 Scan Lines for Vertical Sync Width
27 Scan Lines for Vertical Back Porch
Non-I nterlace
15.720KHz Horizontal Scan Rate
60Hz Frame Refresh Rate

A2

A1

A3

A0
H0

cs

o Fixed Character Rate
1.572MHz Character Rate (636.13ns/Character)
11.004MHz Dot Rate (90.BBns/Dot) for 7 Dot
Wide Character Block

o Character Format
5 X 7 Character in a 7 X 9 Block
o Compatible with CRT B002B-003 VDACTM
o Compatible with CRT 7004B-003
o May be mask-programmed with other display formats

R3

H1

R2

H2

GND

H3

R1

H4

R0

H5

Os

HB

CSYN

H7/DR5

VSYN

DR4

DCC

DR3

Voo

DR2

Vee

DR1

HSYN

DR0

CRV

DB0

BL

DB1

DB?
DBB

DB2
DB3

DB5

DB4

PACKAGE: 40-pin O.I.P.

GENERAL DESCRIPTION
The two chip combination of SMC's CRT 5047 and
CRT 8002B-003 effectively provide all of the video electronics for a CRT terminal. This chip set along with a
f.lC form the basis for a minimum chip count CRT
terminal.

sible by the processor. The CRT 5047 is easily initialized
by the following sequence of commands:
Reset

The CRT 5047 Video Timer and Controller is a special
version of the CRT 5037 VTAC® which has been ROMprogrammed with a fixed format. It is especially effective
for low-cost CRT terminals using an 80 X 24 display
format with a 5 X 7 character matrix. The use of a fixed
ROM program in the CRT 5047 eliminates the software
overhead normally required to specify the display
parameters and simplifies terminal software design.
The Cursor Character Address Register and the Cursor
Row Address Register are the only two registers acces-

Load Control Register 6

Start Timing Chain

The parameters of the CRT 5047 have been selected to
be compatible with most CRT monitors. The horizontal
timing is programmed so that when the two character
skew delay of the CRT 8002 VDACTM is taken into account,
the effective timing is: Horizontal Front Porch -four
characters, and Horizontal Back Porch-eight characters.
Figure 1 shows the contents of the internal CRT 5047
registers. Other mask-programmed versions of the CRT
5037 are available. Consult SMC for more information.

297

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.

i

iiii~i~;;~!;; Circuit
diagrams
utilizing comj)lete
SMC products
are included
means of illustrating
semiconductor
applications:
consequently
information
sufficientas
foraconstruction
purposes istypical
not necessarily
given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furlhermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the best product possible.

298

CRT 7220A
CRT 7220A-1
CRT 7220A-2

High-Performance
Graphics Display Controller
FEATURES

PIN CONFIGURATION

o Microprocesser Interface
o

o
o
o
o
o
o

o

2xWCLK

DMA transfers with 8257- or 8237-type controllers
FIFO Command Buffering
Display Memory Interface
Up to 256K words of 16 bits
Read-Modify-Write (RMW) Display Memory cycles
as fast as 500ns
Dynamic RAM refresh cycles for nonaccessed memory
Light Pen Input
External video synchronization mode
Graphics Mode
Four megabit, bit-mapped display memory
Character Mode
8K character code and attributes display memory
Mixed Graphics and Character Mode
64K if all characters
1 megapixel if all graphics
Graphics Capabilities
Figure drawing of lines, arc/circles, rectangles, and
graphics characters in 500ns per pixel
Display 1024-by-1 024 pixels with 4 planes of color
or grayscale
Two independently scrollable areas
Character Capabilities
Auto cursor advance
Four independently scrollable areas
Programmable cursor height
Characters per row: up to 256
Character rows per screen: up to 100

DSIN
HSYNC
V/EXTSYNC
BLANK
ALE
ORO

3
4
5
6
7
~ 8
R!i 9
WR 10
AO 11
DBO 12
DB1 13
DB2
DB3
DB4 16
DB5 17
DB6 18
DB7 19
GND 20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Vee
A17
A16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
ADO
LPEN/DH

PACKAGE: 4O-pin D.I.P.

o Video Display Format

o
o
o
o

Zoom magnification factors of 1 to 16
Panning
Command-settable video raster parameters
Technology
Single + 5 volt Power Supply
COPLAMOS® n-Channel Silicon Gate Technology
DMA Capability
Bytes or word transfers
4 clock periods per byte transferred

GENERAL DESCRIPTION
The CRT 7220A High-performance Graphics Display Controller (HGDC) is an intelligent microprocessor peripheral
designed to be the heart of a high-performance raster-scan
computer graphics and character display system. Positioned between the video display memory and the microprocessor bus, the HGDC performs the tasks needed to
generate the raster display and manage the display memory. Processor software overhead is minimized by the
HGDC's sophisticated instruction set, graphics figure
drawing, and DMA transfer capabilities. The display 'memory supported by the HGDC can be configured in any number of formats and sizes up to 256K 16-bit words. The display
can be zoomed and panned, while partitioned screen areas
can be independently scrolled. With its light pen input and
multiple controller capability, the HGDC is ideal for advanced
computer graphics applications.

puter graphics system. Through the division of labor established by the HGDC's design, each of the system
components is used to the maximum extent through a sixlevel hierarchy of simultaneous tasks. At the lowest level,
the HGDC generates the basic video raster timing, including sync and blanking signals. Partitioned areas on the
screen and zooming are also accomplished at this level. At
the next level, video display memory is modified during the
figure drawing operations and data moves. Third, display
memory addresses are calculated pixel by pixel as drawing
progresses. Outside the HGDC at the next level, preliminary calculations are done to prepare drawing parameters.
At the fifth level, the picture must be represented as a list of
graphics figures drawable by the HGDC. Finally, this representation must be manipulated, stored, and communicated. By handling the first three levels, the HGDC takes
care of the high-speed and repetitive tasks required to
implement a graphics system.

The HGDC is designed to work with a general purpose
microprocessor to implement a high-performance com-

299

r-;;D;M;A-""1:--------:r;,;.;;;;.;;;...,~HSYNC
Control
~~!~:YNC

ALE
iiBiJj

Command
Processor
wHh
Control ROM
128x 14

A-17

A-16
AD-IS
AD-14
AD-13

Parameter

RAM

16xB

+5Vo----

ILPENlDH

GNOo----2xWCLKo---.

DESCRIPTION OF PIN FUNCTIONS
PIN NO_

SYMBOL
2XWCLK
DBIN
HSYNC
V/EXTSYNC
BLANK
ALE (RAS)
DRQ
DACK
RD
WR
AO
DBO-DB7
GND
LPENIDH
ADO-AD12
AD13-AD15

IN/OUT

1
2
3
4
5
6
7
8
9
10
11
12-19
20
21
22-34
35-37

38

A16

OUT

39

A17

OUT

40

VCC

FUNCTION
Clock Input
Display Memory Read Input Flag
Horizontal Video Sync Output
Vertical Video Sync Output or External VSYNC Input
CRT Blanking Output
Address Latch Enable Output
DMA Request Output
DMA Acknowledge Input
Read Strobe Input for Microprocessor Interface
Write Strobe Input for Microprocessor Interface
Address Select Input for Microprocessor Interface
Bidirectional data bus to Host Microprocessor
Ground.
Light Pen Detect Input/Drawing Hold Input
Address and Data Lines to Display Memory
Character Mode: Line Counter Outputs, Bits 0-2
Mixed Mode: Address and Data Bits 13-15
Graphics Mode: Address and Data Bits 13-15
Character Mode: Line Counter Output, Bit 3
Mixed Mode: Attribute Blink and Clear Line Counter Output
Graphics Mode: Address Bit 16 Output_
Character Mode: Cursor Output and Line Counter Bit 4
Mixed Mode: Cursor and Bit Map Area Flag Output
Graphics Mode: Address Bit 17 Output
+ 5 Volt Power Supply

IN
OUT
OUT
IN/OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN/OUT

IN
IN/OUT
IN/OUT

300

FUNCTIONAL DESCRIPTION
Microprocessor Bus Interface
Control of the HGDC by the system microprocessor is
achieved through an 8-bit bidirectional interface. The status register is readable at any time. Access to the FIFO buffer
is coordinated through flags in the status register and operates independently of the various internal HGDC operations, due to the separate data bus connecting the interface
and the FIFO buffer.

Command Processor
The contents of the FIFO are interpreted by the command
processor. The command bytes are decoded, and the
succeeding parameters are distributed to their proper
destinations within the HGDC. The command processor
yields to the bus interface when both access the FIFO
simultaneously.

DMAControl
The DMA control circuitry in the HGDC coordinates transfers over the microprocessor interface when using an
external DMA controller. The DMA Request and Acknowledge handshake lines directly interface with a DMA controller, so that display data can be moved between the
microprocessor memory and the display memory.

Parameter RAM
The 16-byte RAM stores parameters that are used repetitively during the display and drawing processes. In character mode, this RAM holds four sets of partitioned display
area parameters; in graphics mode, the drawing pattern
and graphics character take the place of two of the sets
of parameters.

Drawing Controller
The drawing processor contains the logic necessary to calculate the addresses and positions of the pixels of the various graphics figures. Given a starting point and the
appropriate drawin!il parameters, the dra,«ing contr~lIer
needs no further assistance to complete the figure drawing.

Display Memory Controller
The display memory controller's tasks are numerous. Its
primary purpose is to multiplex the address and data information in and out of the display memory. It also contains the
16-bit logic unit used to modify the display memory contents during RMW cycles, the character mode line counter,
and the refresh counter for dynamic RAMs. The memory
controller apportions the video field time between the various types of cycles.

Light Pen Deglitcher
Only if two rising edges on the light pen input occur at the
same point during successive video fields are the pulses
accepted as a valid light pen detection. A status bit indicates to the system microprocessor that the light pen register contains a valid address. Ifthis input is hElld high for a
period greater than four 2xWCLK cycles, drawing execution is halted.

PROGRAMMER'S VIEW OF HGDC
The HGDC occupies two addresses on the system microprocessor bus through which the HGDC's status register
and FIFO are accessed. Commands and parameters are
written into the HGDC's FIFO and are differentiated based
on address bit AO. The status register or the FIFO can be
read as selected by the address line.
AD

Video Sync Generator
Based on the clock input, the sync logic generates the raster timing signals for almost any interlaced, non-interlaced,
or "repeat field" interlaced video format. The generator
is programmed during the idle period following a reset. In
video sync slave mode, it coordinates timing between
multiple HGDC's.

READ

WRITE

Status Register

Parameter Into FIFO

0

I

I

I

1

I

I

I

I

I

I

I

I

I I

I

I

I

I I

I

I

I

I

I

I

I

I

I

Command Into FIFO

FIFO Read
I

I

I

I

I

I

I

I

I

HGDC Microprocessor Bus Interface Registers

The memory timing circuitry provides two memory c;ycle
types: a two-clock period refresh cycle and the read-modify-write (RMW) cycle which takes four clock periods. The
memory control signals needed to drive the diSplay memory devices are easily generated from the HGDC's ALE and
DBIN outputs.

Commands to the HGDC take the form of a command byte
followed by a series of parameter bytes as needed for specifying the details of the command. The command processor
decodes the commands, unpacks the parameters, loads
them into the appropriate reigsters within the HGDC, and
initiates the required operations.
The commands available in the HGDC can be organized
into five categories as described in the following section.

Zoom & Pan Controller

HGDC COMMAND SUMMARY

Memory Timing Generator

Based on the programmable zoom display factor and the
display area entries in the parameter RAM, the zoom and
pan controller determines when to advance to the next
memory address for display refresh and when to go on to
the next display area. A horizontal zoom is produced by
slowing down the display refresh rate while maintaining the
video sync rates. Vertical zoom is accomplished by repeatedly accessing each line a number of times equal to the
horizontal repeat. Once the line count for a display area is
exhausted, the controller accesses the starting address and
line count of the next display area from the parameter RAM.
The system microprocessor, by modifying a display area
starting address, can pan in any direction, independently of
the other display areas.

Video Control Commands
1. RESET 1 Resets the HGDC to its idle state.
2. RESET 2 Resets the HGDC to its idle state. Does
not resynchronize video timing. Blanks
the display.
3. RESET 3 Resets the HGDC to its idle state. Does
not resynchronize video timing. Does not
blank the display.
4. SYNC
Specifies the video display format.
5. VSYNC
Selects master or slave video synchronization mode.
6. CCHAR
Specifies the cursor and character row
heights.

301

SR-3: Drawing In Progress

Display Control Commands
1. START
Ends Idle mode and unblanks the display.
2. BLANK 1 Controls the blanking and unblanking
of the display, along with video
resynchronization.
3. BLANK 2 Controls the blanking and unblanking of
the display. Does not blank the display.
4. ZOOM
Specifies zoom factors for the display and
graphics .characters writing.
5. CURS
Sets the position of the cursor in display
memory.
6. PRAM
Defines starting addresses and lengths
of the display areas and specifies the
eight bytes for the graphics character.
7. PITCH
Specifies the width ofthe X dimension of
display memory.

Drawing Control Commands
1. WDAT
2. MASK
3. FIGS
4. FIGD
5. GCHRD

Writes data words or bytes into display
memory.
Sets the mask register contents.
Specifies the parameters for the drawing
controller.
Draws the figure as specified above.
Draws the graphics character into display memory.

Data Read Commands
1. RDAT:

Reads data words or bytes from display
memory.
Reads the cursor position.
Reads the light pen address.

2. CURD:
3. LPRD:

DMA Control Commands
1. DMAR
2. DMAW

Requests a DMA read transfer.
Requests a DMA write transfer.

STATUS REGISTER FLAGS

III I

tt

lDataReadY
FIFO Full
FIFO Empty

L - - - - D r a w i n g In Progress

L..
_ _ _ _ _ _ _ _ _ DMA Execute

'--_ _ _ _ _ _ _ _ _ Vertlcal Sync Active

Horizontal Blank Actlve/
Vertical Blank Active

' - - - - - - - - - - - - - - - L i g h t P e n Detect

Status Register (SR)

SR-7: Light Pen Detect
When this bit is set to 1, the light pen address (LAD) register
contains a deglitched value that the system microprocessor
may read. This flag is reset after the 3-byte LAD is moved
into the FIFO in response to the light pen read command.

SR-6: Horizontal Blanking ActiveNertical Blank
Active
A 1 value for this flag signifies that horizontal retrace blanking or vertical retrace blanking is currently underway
dependent on the status of the VH bit in SYNC or the
RESETx parameter 6.

SR-S: Vertical Sync
Vertical retrace sync occurs while this flag is a 1. The vertical sync flag coordinates display format modifying commands to the blanked interval surrounding vertical sync. This
eliminates display disturbances.

SR-4: DMA Execute
This bit is a 1 during DMA data transfers.

While the HGDC is drawing a graphics figure, this status bit
is a 1.

SR-2: FIFO Empty
This bit and the FIFO Full flag coordinate system microprocessor accesses with the HGDC FIFO. When it is 1, the
Empty flag ensures that all the commands and parameters
previously sent to the HGDC have been interpreted.

SF-1: FIFO Full
A 1 at this flag indicates a full FIFO in the HGDC. A 0 ensures
that there is room for at least one byte. This flag needs to
be checked out before each write into the HGDC.

SR-O: Data Ready
When this flag is a 1, it indicates that a byte is available to
be read by the system microprocessor. This bit must be
tested before each read operation. It drops to a 0 while the
data is transferred from the FIFO into the microprocessor
interface data register.

FIFO OPERATION & COMMAND PROTOCOL
The first-in, first-out buffer (FIFO) in the HGDC handles the
command dialogue with the system microprocessor. This
flow of information uses a half-duplex technique, in which
the single 16-location FIFO is used for both directions of
data movement, one direction at a time. The FIFO's direction is controlled by the system microprocessor through the
HGDC's command set. The host microprocessor coordinates these transfers by checking the appropriate status
register bits.
The command protocol used by the HGDC requires differentiation of the first byte of a command sequence from the
succeeding bytes. The first byte contains the operation code
and the remaining bytes carry parameters. Writing into the
HGDC causes the FIFO to store a flag value alongside the
data byte to signify whether the byte was written into the
command or the parameter address. The command processor in the HGDC tests this bit as it interprets the entries
in the FIFO.
The receipt of a command byte by the command processor
marks the end of any previous operation. The number of
parameter bytes supplied with a command is cut short by
the receipt of the next command byte. A read operation from
the HGDC to the microprocessor can be terminated at any
time by the next command.
The FIFO changes direction under the control of the system
microprocessor. Commands written into the HGDC always
put the FIFO into write mode if it wasn't in it already.
If it was in read mode, any read data in the FIFO at the time
ofthe turnaround is lost. Commands which require a HGDC
response, such as RDAT, CURD and LPRD, put the FIFO
into read mode after the command is interpreted by the
HGDC's command processor. Any commands and parameters behind the read-evoking command are discarded
when the FIFO direction is reversed.
RE~D-MODIFY-WRITE

CYCLE

Data transfers between the HGDC and the display memory
are accomplished using a read-modify-write (RMW) memory cycle. The four clock period timing of the RMW cycle is
used to: 1) output the address, 2) read data from the memory, 3) modify the data, and 4) write the modified data back
into the initially selected memory address. This type of

302

memory cycle is used for all interactions with display memory including DMA transfers, except for the two clock period
display and RAM refresh cycles.
The operations performed during the modify portion of the
RMW cycle merit additional explanation. The circuitry in the
HGDC uses three main elements: the Pattern register, the
Mask register, and the 16-bit Logic Unit. The Pattern register holds the data pattern to be moved into memory. It is
loaded by the WDAT parameters or, during drawing, from
the parameter RAM. The Mask register contents determine
which bits of the read data will be modified. Based on the
contents of these registers, the Logic Unit performs the
selected operations of REPLACE, COMPLEMENT, SET, or
CLEAR on the data read from display memory.
The Pattern register contents are ANDed with the Mask
register contents to enable the actual modification of the
memory read data, on a bit-by-bit basis. For graphics drawing, one bit at a time from the Pattern register is combined
with the Mask. When ANDed with the bit set to a 1 in the
Mask register, the proper single pixel is modified by the logiC
Unit. For the next pixel in the figure, the next bit in the Pattern register is selected and the Mask register bit is moved
to identify the pixel's location within the word. The Execution word address pointer register, EAD, is also adjusted as
required to address the word containing the next pixel.
In character mode, all of the bits in the Pattern register are
used in parallel to form the respective bits of the modify data
word. Since the bits of the character code word are used in
parallel, unlike the one-bit-at-a-time graphics drawing process, this facility allows any or all of the bits in a memory
word to be modified in one RMW memory cycle. The Mask
register must be loaded with 1s in the positions where modification is to be permitted.
The Mask register can be loaded in either of two ways. In
graphics mode, the CURS command contains a four-bit dAD
field to specify the dot address. The command processor
converts this parame'(er into the one-of-16 format used in
the Mask register for figure drawing. A full 16 bits can be
loaded into the Mask register using the MASK command.
In addition to the character mode use mentioned above, the
16-bit MASK load is convenient in graphics mode when all
of the piXels of a word areto be set to the same value.
The Logic Unit combines the data read from display memory, the Pattern Register, and the Mask register to generate
the data to be written back into display memory. Anyone of
four operations can be selected: REPLACE, COMPLEMENT, CLEAR or SET. In each case, if the respective Mask
bit is 0, that particular bit of the read data is returned to
memory unmodified. If the Mask bit is 1, the modification is
enabled. With the REPLACE operation, the Pattern Register data simply takes the place of the read data for modification enabled bits. For the other three operations, a 0 in
the modify data allows the read data bit to be returned to
memory. A 1 value causes the specified operation to be
performed in the bit positions with set Mask bits.

FIGURE DRAWINGS
The HGDC draws graphics figures at the rate of one pixel
per read-modify-write (RMW) display memory cycle. These
cycles take four clock periods to complete. At a clock frequency of 8MHz, this is equal to 500ns. During the RMW
cycle the HGDC simultaneously calculates the address 'and
position of the next pixel to be drawn.
The graphics figure drawing process depends on the display memory addressing structure. Groups of 16 horizontally adjacent pixels form the 16-bit words which are handled
by the HGDC. Display memory is organized as a linearly

addressed space of these words. Addressing of individual
pixels is handled by the HGDC's internal RMW logic.
During the drawing process, the HGDC finds the next pixel
of the figure which is one of the eight nearest neighbors of
the last pixel drawn. The HGDC assigns each ofthese eight
directions a number from 0 to 7, starting with straight down
aRd proceeding counterclockwise.

Drawing Directions

Figure drawing requires the proper manipulation of the
address and the pixel bit position according to the drawing
direction to determine the next pixel of the figure. To move
to the word above or below the current one, it is necessary
to subtract or add the number of words per line in display
memory. This parameter is called the pitch. To move to the
word to either side, the Execute word address cursor, EAD,
must be incremented or decremented as the dot address
pointer bit reaches the LSB or the MSB of the Mask register.
To move to a pixel within the same word, it is necessary to
rotate the dot address pOinter register to the right or left.
The table below summarizes these operations for each
direction.
Dlr

Operations to Add,.•• the Next Pixel

000

EAD P-+EAD

001

EAD-P .... EAD
dAD (MSB) = 1:EAD -1 .... EAD dAD .... LR

010

dAD (MSB)1 :EAD -1 .... EAD dAD .... LR

011

EAD-P_EAD
dAD(MSB)=I:EAD-l .... EADdAD .... LR

100

EAD-P .... EAD

101

EAD-P-+EAD
dAD (LSB) = 1:EAD -1 .... EAD dAD .... RR

110

dAD(LSB)-I:EAD-l .... EAD dAD .... RR

EAD-P .... EAD
dAD (LSB) = 1:EAD -1 .... EAD dAD .... RR
Where P Pitch, LR Left Rotate, RR Right Rotate,
EAD = Execute Word Address, and
dAD = Dot Address stored in the Mask Register.
111

Whole word drawing is useful for filling areas in memory with
a single value. By setting the Mask register to all 1s with the
MASK command, both the LSB and MSB of the dAD will
always be 1, so that the EAD value will be incremented or
decremented for each cycle regardless of direction. One
RMW cycle will be able to effect all 16 bits of the word for
any drawing type. One bit in the Pattern register is used per
RMW cycle to write all the bits ofthe word to the same value.
The next Pattern bit is used for the word, etc.

303

,
I,

Forthe various figures, the effect ofthe initial direction upon
the resulting drawing is shown below:
Olr

Line

Arc

Character Slant Char Rectangle

000

~#

001

~

010

JIj L> ~

011

100

101

110

111

~,)7

r> ~ ~
~/.

"
,',

"•

C:~~

~

';:,-,)

~~

fIT

UUlJ1J

/J rumn

,/'1

~

n",J

[J

i'N

0

~

ff 0
~ ~ 0

~,~~--

~
~

~

ff

OMA

D

z:
~

CJ

~
~

~ ~ (>

Drawing Type

~
I'N

0

HGDC Drawing Controller coordinates the RMW circuitry
and address registers to draw the specified figure pixel by
pixel.
The algorithms used by the processor for figure drawing are
designed to optimize its drawing speed. To this end, the
specified details about the figure to be drawn are reduced
by the microprocessor to a form conducive to high-speed
address calculations within the HGDC. In this way the
repetitive, pixel-by-pixel calculations can be done quickly,
thereby minimizing the overall figure drawing time. The table
below summarizes the parameters.
DC

D

D2

D1

DM

Initial Value·

0

8

8

-1

-1

Line

1<1.11

Arc··

rain 4»

Graphic Characte"""
_d

+ wrl1e De1e

2(j """ 45?
8= Angle from major axis to start of the arc. 8 .... 45?
i = Round up to the next higher integer.
~ = Round down to the next lower integer.
A= Number of pixels in the initially specified direction.
B"" Number of pixels In the direction at right angles to the
initially specified direction.
W= Number of words to be accessed.
C=: Number of bytes to be transferred in the initially specified
direction. (Two bytes per word If word transfer mode
is selected.)
0= Number of words to be accessed In the direction at right
angles to the Initially specified direction.
DC == Drawing count parameter which Is one less than the num·
ber of RMW cycles to be executed.
DM= Dots masked from drawing during arc drawing.
t==- Needed only for word reads.

GRAPHICS CHARACTER DRAWING
Graphics characters can be drawn into display memory
pixel-by-pixel. The up to 8-by-8 character display is loaded
'into the HGDC's parameter RAM by the system microprocessor. Consequently, there are no limitations on the character set used. By varying the drawing parameters and
drawing direction, numerous drawing options are available.
In area fill applications, a character can be written into display memory as many times as desired without reloading
the parameter RAM.
Once the parameter RAM has been loaded with up to eight
graphics character bytes by the appropriate PRAM command, the GCHRD command can be used to draw the bytes
into display memory starting at the cursor. The zoom magnification factor for writing, set by the zoom command, controls the size of the character written into the display memory
in int~ger multiples of 1 through 16. The bit values in the

PRAM are repeated horizontally and vertically the number
of times specified by the zoom factor.
The movement ofthese PRAM bytes to the display memory
is controlled by the parameters of the FIGS command.
Based on the specified height and width of the area to be
drawn, the parameter RAM is scanned to fill the required
area.
For an 8-by-8 graphics character, the first pixel drawn uses
the LSB of RA-15, the second pixel uses bit 1 of RA-15, and
so on, until the MSB of RA-15 is reached.
The HGDC jumps to the corresponding bit in RA-14 to continue the drawing. The progression then advances toward
the LSB of RA-14. This snaking sequence is continued for
the other 6 PRAM bytes. This progression matches the
sequence of display memory addresses calculated by the

304

drawing processor as shown above. If the area is narrower
than 8 pixels wide" the snaking will advance to the next
PRAM byte before the MSB is reached. If the area is narrower than 8 lines high, fewer bytes in the parameter RAM
will be scanned. If the area is larger than 8 by 8, the HGDC
will repeat the contents of the parameter RAM in two
dimensions, as required to fill the area with the 8-by-8 mozaic. (Fractions of the 8-by-8 pattern will be used to fill areas
which are not multiples of 8 by 8).

PARAMETER RAM CONTENTS: RAM ADDRESS
RAOT015
The parameters stored in the parameter RAM, PRAM,.are
available for the HGDC to refer to repeatedly during figure
drawing and raster-scanning. In each mode of operation the
values in the PRAM are interpreted by the HGDC in a predetermined fashion. The host microprocessor must load the
appropriate parameters into the proper PRAM locations.
PRAM loading command allows the host to write into any
location of the PRAM and transfer as many bytes as desired.

Graphics and Mixed Graphics and Character Modes

Character Mode

I

0

0

In this way any stored parameter byte or bytes may be
changed without influencing the other bytes.
The PRAM stores two types of information. For specifying
the details of the display area partitions, blocks of four bytes
are used. The four parameters stored in each block include
the starting address in display memory of each display area,
and its length. In addition, there are two mode bits for each
area which specify whether the area is a bit-mapped graphics area or a coded character area, and whether a 16-bit or
a 32-bit wide display cycle is to be used for that area.
The other use for the PRAM contents is to supply the pattern for figure drawing when in a bit-mapped graphics area
or mode. In these situations, PRAM bytes 8 through 16 are
reserved for this patterning information. For line, arc, and
rectangle drawing (linear figures) locations 8 and 9 are
loaded into the Pattern Register to allow the HGDC to draw
dotted, dashed, etc. lines. For area filling and graphics bitmapped character drawing locations 8 through 15 are referenced for the pattern or character to be drawn.
Details of the bit assignments are shown for the various
modes of operation.

RA-O

I. .

1

...
1

I

'--;=~=;=~~=~~~=~

I--

SAD1~

--'_""---"_-'--'-_"'--'-~

I--,_L~EN_"--,,_~I_O-'-_0-LI_SA~~_,~I

2 ...

Length of Display Partition
Area 1 with low and high
Significance fields (line count)

Length 01 Display PartHlon 1

(line count) with high and
low significance fields

LEN1 tt

In mixed mode, a 1 Indicates an

A Wide Display cycle width

'--------- :~:'!~:~:~:~~r::~~na

of two words per memory cycle

is then incremented

by

2 for each display scan
cycle. Other memory cycle
types are not Influenced.

0

0

o

I

WD21 0

I

I

14

15

0

0

o I

I

wool

0

0

0

I

0

0

LEN3 H

o

LEN4L

WD41 0

I

1

0

LEN2,

or

or

GCHR8

GCHR7

GCHR6

11

GCHR5

12

GCHR4

ii!
-

r--

0

o I SAD2,

RA-l0

Display Partnton 4

starling address
and length

13

GCHR3

14

GCHR2

15

GCHRI

SAD4H

I

PTN,

PTN H

Display PartHlon 3

0

SAD4l

0

cl

0

atartlng addresa
and length

SAD3 ..

LEN3~

I

WD2IIM I

0

r--

Display Partition Area 2
starting address and
length with Image
bH a8 in area 1

SAD2M
LEN2L

RA-8

RA-12

13

0

SAD3l

10
11

Display Partition 2
starting address

0

-

SAD2l

r-- and length

LEN2H

RA-8

0

RA-4

SA02H

LEN2L

0

0

graphics mode thts bit must be O.
When 1, the DAD Is Incremented
every other display cycle.

The display add,... counter

SAD2L

:~d~(~~~: :::rr:.~)lflcance

--,_",,---,,_S.A_~_.-,--,-_~~

'--__________ ~s,:~~:s:'I~h!:td~:~I~~

RA-4

Display Partition Area 1
starting address with low•

0

LEN4H

305

/

Pattern of 16 bits used for
figure drawing to pattern
dotted, dashed, etc. lines

Graphics character bytes
to be moved into display
memory with graphics
character drawing

VIDEO CONTROL COMMANDS

Command Bytes Summary
RESET 1

RESET2

RESET3

BLANKI

BLANK2

SYNC

VSYNC

CCHAR

START

I
I
I
I
I

I
I
I

I

0

o , 0

0

o

0

o

0

o

0

o

0

o , 0

0

o

0

o

I

0·, 0

I

Reset
o

0

l'
l'
I

1

I

1

I

DE

DE

0

l'
l'

I

DE

I

I

I

~ "L_0..J-~~--'---''----'---'_--'-o--,•

-FIFO
- Command Processor
-Internal COunters

This command can be executed at any time and does not
modify any ofthe parameters already loaded into the HGDC.
If followed by parameter bytes, this command also sets the
sync generator parameters as described below. Idle mode
is exited with the START command.
RESET 1: Resync video timing in slave mode.
RESET 2: Blank the display and do not resync.
RESET 3: Unblank the display and do not resync.

M
Mode 01 Operation select bits

P1

l'

See below

P2

Active Olsplay Words per
line _ 2 Must be even
number with bit 0 == 0

P3

0

Horizontal Sync Width - 1
' - - - - - - - - - - Vertical Sync Width, low bits

ZOOM

CURS

P4

PRAM

L-..J---J'--H_F'-P..--L..-..J----''--_VS'-"---II-- Vartlcal Sync Width, high bit.

\'-'----

SA

-

PITCH

WDAT

.0

1

I II
TYPE

0

P5

DH

PH

P6

VH

VL

MOD

.Horizontal Front Porch Width - 1

-

HBP

--

VFP

o

FIGS

P8

A~

YBP

j..-

Active Display Lines per

'-..J-~'--~''<',_,__
'0..._-_-_0..._-_oJ_L.._-_-_0..._-_....1_._Video Field,

FIGD

.
GCHRD

RDAT

1

CURD

DMAW

Vertical Front Porch Width

Video Field, low btts

MASK

DMAR

Horizontal Back Porch Width - 1

i-- Active Display Lines per

AL,

P7

LPRD

Blank the display, enter
Idle
modo, and Innlan...
within the HGDC:

,.
1

1

I II
I
I
I 1'1
I l'
TYPE

o

0

o

0

0

MOD

TYPE

MOD

TYPE

MOD

high bR.

Vertical Back Porch Width

In graphics mode, a word is a group of 16 pixels. In character mode, a word is one character code and its attributes,
if any. The number of active words per line must be an even
number from 2 to 256. An all-zero parameter value selects
a count equal to 2" where n = number of bits in the parameter field for vertical parameters. All horizontal widths are
counted in display words. All vertical intervals are counted
in lines.
If the Drawing Hold (DH) is set to one, pin 21 (LPEN/DH) is
used as the drawing hold control pin. When the input to
LPEN/DH is held high for over four 2 x WCLK clocks, the
drawing address output is temporarily held and the display
address is output.
The HGDC allows an even or odd number of lines per frame.
Selection is via the VL flag, the seventh bit of the sixth
parameter byte following a RESET or SYNC command.
When VL is 0, an odd number of display lines is generated.
306

VL

o

Interlaced Framing:

2 Field Sequence with 'i2line offset. Each field displays alternate
lines.
Noninterlaced Framing: 1 field brings all of the information to the screen.

Number 01 lines In Interlaced mode
Odd, as in 7220
Even

When VH = 0, status operation is as in CRT 7220.

D

VH

o

Blank Status Bit Dellnltlon
Status register bit 6 indicates Horizontal Blank
Status register bit6 indicates Vertical Blank

No Refresh - STATIC RAM
Refresh - Dynamic RAM

Dynamic RAM refresh is important when high display
zoom factors or DMA are used in such a way that not all of
the rows in the RAMs are regularly accessed during display raster generation and for otherwise inactive display
memory.

PH is the most significant bit (9) of the display pitch
parameter. Use the PITCH command to set the lower
eight bits,

Drawing during acllve dlep'.Y time and ret,ace blanking

SYNC GENERATOR PERIOD CONSTRAINTS

Drawing only during ret,ace blanking

Access to display memory can be limited to retrace blanking intervals only, so that no disruptions of the image are
seen on the screen.

Horizontal Back Porch Constraints
1. In general:
HBP;;.3 Display Word Cycles (6 clock cycles).
2. If the Image bit or WD modes change within one video
field:
HBP;;.5 Display Word Cycles (10 clock cycles).
3. If interlace, mixed mode, or split screen is used:
HBP;;.5 Display Word Cycles (10 clock cycles).

R~ET3 L..1_o--'-----'-_"--o_I'--,

Both commands allow a reset while presenting reinitialization of the internal sync generator by an externaf sync source
(slave mode).

Cursor & Character Characteristics

CCHAR:I

Horizontal SYNC Constraints

P3

°° °,
,, °,

Display Cursor if 1

line number

L-"-...JC....B~OT-'---'----JL.-....r.....B-R"-'-~\-- Blink Rata, upper bRa

,'-'-----Cursor Bottom lina number in
tha row CBOT LR
<

In graphics mode, LR should be set to O. The blink rate
parameter controls both the cursor and attribute blink rates.
The cursor blink-on time = blink-off time = 2 x BR (video
frames). The attribute blink rate is always '12 the cursor
rate but with a % on -% off duty cycle. All three parameter
bytes must be output for interlace displays, regardless of
mode. For interlace displays in graphics mode, the parameter BRL = 3.

Inyalid

Video Framing

per character row-1

0 - Blinking Cursor
1 - Steady Cursor
' - - - - - - - - - - Blink Rata, lower bits

Graphics Mode

Noninterlaced

IDt'-E_I_o_I___L_R_---~-Llnes

-

Character Mode

I S

oj

P2 I B~~~~~---CT-D-P----~-~U:::~::p

Modes of Operation Bits

°° °,
,, °,

!

-

1. If interlaced display mode is used:
HS;;.5 Display Word Cycles (10 clock cycles).
2. If DRAM Refresh is enabled:
HS;;'2 Display Word Cycles (4 clock cycles).

Mixed Graphics & Character

°. ' , 0 °

.-T""'''!!!i=::::;:=======;-- ExternalSYNe Enable

p,

Display Mode

. .JI

--'-0----'-_'--'

Horizontal Front Porch Constraints
1. In general:
HFP;;.2 Display Word Cycles (4 clock cycles).
2. If the HGDC is used in the video sync Slave mode:
HFP;;.4 Display Word Cycles (8 clock cycles).
3. If the Light Pen is used:
HFP;;.6 Display Word Cycles (12 clock cycles).
4. If interlace mode, DMA, or ZOOM is used:
HFP;;.3 Display Word Cycles (6 clock cycles).

C G

L..I_O--'-----'-_.l.-°...JI'--o...1..-----,----,,--'1

RESET2

Invalid
Interlaced Repeat Field for Character Displays

Interlaced

Repeat Field Framing:

2 Field Sequence with '12 line offset between otherwise identical
fields.
307

When SE = 0, the HGDC, in slave mode, detects the falling
edge of EX. SYNC on the first frame. When SE = 1, the
HGDC, in slave mode, detects the falling edge of EX. SYNC
on every frame.

DISPLAY CONTROL COMMANDS

SYNC Format Specify

l1D~

Start Display & End Idle Mode
The display Is enabled by
a 1, and blanked by a O.

PI

START:lo,l,t . 0 , 1 , 0 , 1 . 1 1

Mode of Operation selecl bits
See below

° °

P2

Active Display Words per
line Must be even
number with bit 0 == 0

P3

Display Blanking Control

~ IL._'---'----'----''---'--'--'----'.'---l.
1 DE I-Thedllplaylsonabled
~~ 1, and blanked by

Horizontal Sync Width

' - -_ _ _ _ _ _ _ _ Vertical Sync Width, low bits

P4

,'-._---

L--,--,-_H_F,-Pr_-'-~--'VS'-"--II-- Vertical Sync Width. high bits

P5

DH PH

HBP

P6

VH VL

VFP

rr--

VBP

Horizontal Front Porch Width

BLANK 2 does not cause the resyncing of an HGDC in
slave mode. BLANK 1 does cause the resyncing of an
HGDC in slave mode.

Horizontal Back Porch Width
Vertical Front Porch Width

Zoom Factors Specify

Display Lines per
I-- Active
Video Field, low bits

AL,

P7

P8

The START command generates the video signals as
specified by the RESETX or SYNC command.

ALH

f--

~_D~I_l-'-~ L--,-~__~o~1

ZOOM: 1
Active Display Lines per

L-......--'-_"'\_,~_.==:==~=::=~._ Video Field,

__

high bits

Vertical Back Porch Width

PI

1

GCHR

DISP

I--

~---"_'~\"'_L--'-~_-'-~

This command also loads parameters into the sync generator. The various parameter fields and bits are identical
to those at the RESET command. The HGDC is not reset
nor does it enter idle mode.

Vertical Sync Mode

\

Zoom 'actor lor graphics
character writing and area
filling

' - - - - - - - - - - O i s p l a y zoom factor

Zoom magnification factors of 1 through 16 are available
using codes 0 through 15, respectively.

Cursor Position Specify

VSYNc:l~o~._l~_ _ _~~--,_'~I_M~~
o -Accept External Vertical

Sync - Slave Mode
1 -Generate & Output Vertical

Sync - Master Mode

When using two or more HGDCs to contribute to one image,
one HGDC is defined as the master sync generator, and the
others operate as its slaves. The VSYNC pins of all HGDCs
are connected together.
A few considerations should be observed when synchronizing two or more HGDCs to generate overlayed video via
the V/EXT SYNC pin. As mentioned above, the Horizontal
Front Porch (HFP) must be 4 or more display cycles wide.
This is equivalent to eight or more clock cycles. This gives
the slave HGDCs time to initialize their internal video sync
generators to the proper point in the video field to match the
incoming vertical sync pulse (VSYNC). This resetting of the
generator occurs just after the end of the incoming VSYNC
pulse, during the HFP interval. Enough time during HFP is
required to allow the slave HGDC to complete the operation
before the start of the HSYNC interval.
Once the HGDCs are initialized and set up as Master and
Slaves, they must be given time to synchronize. It is a good
idea to watch the VSYNC status bit of the Master HGDC
and wait until after one or more VSYNC pulses have been
generated before the display process is started. The START
command will begin the active display of data and will end
the video synchronization process, so be sure there has
been at least one VSYNC pulse generated forthe Slaves to
synchronize to.

308

PI

P2

P3

I-

I

EAD
.....---'---''--..........--'---''---'---'---'.

Execute WOrd Add....,
low byte

I.

Execute WOrd Address,
EAD
L-..........-'-~_-'---'----''--~---'r middle byte

dAD

1WG .1

° 1 E~D

I--

(Graphics M_ only)

'--~"""\---",-'~~~~~~~~~~~'"""""-~~_Word
-

Address, top bits

Dot Address within the word

In character mode, the third parameter byte is not needed.
The cursor is displayed for the word time in which the display scan address (DAD) equals the cursor address. In
graphics mode, the cursor word address specifies the word
containing the starting pixel of the drawing; the dot address
value specifies the pixel within that word.
When the WG bit is set to one, any data following the WDAT
command is written as is. When the WG bit is set to zero,
the 7220A performs as the 7220 does: The pattern written
is determined by the least Significant bit of each parameter
byte following the WDAT command. This bit is expanded
into 16 identical bits which form the pattern.

Parameter RAM Load

"-----_ _ _ Starting Address in
parameter RAM

I--

P,
I

'----I---'"_"'---'-____"_-'--_'_--.J

I

1 to 16 byt.. to be loaded

:.~~~: :~~:~~~:r.ss
specified by SA

I
p"

From the starting address, SA. any number of bytes may
be loaded into the parameter RAM at incrementing
addresses, up to location 15. The sequence of parameter
bytes is terminated by the next command byte entered into
the FIFO. The parameter RAM stores 16 bytes of information in predefined locations which differ for graphics and
character modes. See the parameter RAM discussion for
bit assignments.

Pitch Specification

during the RMW memory cycle.
In graphics bit-map situations, only the LSB of the WDAT
parameter bytes is used as the pattern in the RMW operations. Therefore it is possible to have only an all ones or
all zeros pattern. If the WG bit of the third parameter of the
CURS command is set to one, any byte following the WDAT
command is w~itten as is. In coded character applications
all the bits of the WDAT parameter\? are used to establish
the drawing pattern.
The WDAT command operates differently from the other
commands which initiate RMW cycle activity. It requires
parameters to set up the Pattern register while the other
commands use the stored values in the parameter RAM.
Like all of these commands, the WDAT command must be
preceded by a FIGS command and its parameters. Only the
first three parameters need to be given following the FIGS
opcode, to set up the type of drawing, the DIR direction, and
the DC value. The DC parameter + 1 will be the number of
RMW cycles done by the HGDC with the first set of WDAT
parameters. Additional sets of WDAT parameters will see a
DC value of 0 which will cause only one RMW cycle to be
executed per set of parameters.

Mask Register Load
P1:

1""--'_-'--'---'P'---'--'-_'--..J1

,

r---

Number of word addresses
In display memory In the
horizontal direction

This value is used during drawing by the drawing processor
to find the word directly above or below the current word,
and during display to find the start of the next line.
The Pitch parameter (width of display memory) is set by two
different commands. In addition to the PITCH command,
the RESET (or SYNC) command also sets the pitch value.
The "active words per line" parameter, which specifies the
width of the raster-scan display, also sets the Pitch of the
display memory. Note that the AW value is two less than the
display window width. The PITCH command must be used
to set the proper memory width larger than the window width.

DRAWING CONTROL COMMANDS
Write Data into Display Memory

"-----RMW Memory cycle
Logical Operation:

o ______ REPLACE with Pattern
1 ______ COMPLEMENT

o ______ RESET to zero
1~SETto1

'--------DataTranslerTypa:

:,":======Word,

Low then High byte
Low Byte of the Word
1 _ ' " < - - - - - - - H l g h Byte 01 the Word

o
o •

--,_-,---,---,M~,--,-_",___,_--,

Low significance byte

I. . ____"_-'---'---'M~"--'-_"'___'_--'

High significance byte

P1 1....

P2

This command sets the value of the 16-bit Mask register of
the figure drawing processor. The Mask register controls
which bits can be modified in the display memory during a
read-modify-write cycle.
The Mask register is loaded by the MASK command and
the third parameter byte of the CURS command. The MASK
command accepts two parameter bytes to load a 16-bit value
into the Mask register. All 16 bits can be individually one or
zero, under program control. The CURS command on the
other hand, puts a "1 to 16" pattern into the Mask register
based on the value of the Dbt Address value, dAD. If normal
single-pixel-at-a-time graphics figure drawing is desired,
there is no need to do a MASK command at all since the
CURS command will set up the proper pattern to address
the proper pixels as drawing progresses. For coded character DMA, and screen setting and clearing operations using
the WDAT command, the MASK command should be used
after the CURS command if its third parameter byte has
'been output. The Mask register should be set to all "ONES"
for any "word-at-a-time" operation.

1 _... . - - - - - - - I n v a l l d

Valid Figure Type Select Combinations
P1

P2
etc.

L- Word Low Data Byte or

WORD L OR BYTE
'----'---'-_"'----'---'"_"'---'---.J1 ~

IL..--'_-'--'---'_-'--'-_~-'!L
WORD H

-

Single Byte Data value

Word transfer only:
High Data Byte

Upon receiving a set of parameters (two bytes for a word
transfer, one for a byte transfer), one RMW cycle into Video
Memory is done at the address pointed to by the cursor EAD.
The EAD pointer is advanced to the next word, according
to the previously specified direction. More parameters can
then be accepted.
For byte writes, the unspecified byte is treated as all zeros

SL

R

A

GC

L

o

0

0

0

0

o
o

0

0

0

0

0

o

0

o
o

0

Operation
Character Display Mode Drawing, Individual Dot Drawing,
DMA, WDAT, and RDAT
Straight Line Drawing
Graphles Charleter Drawing and Area filling with graphles
character pattern

0

0

0

0

Arc and Circle Drawing
Reet.ngle

Draw:::ln~g_ _ _ _ _ _ _ __

Slanted Graphics Charaeter Drawing and Slanted
Area Filling

Only these bit combinations assure correct drawing
operation.

309

Figure Draw Start
FlGO:

I°

Graphics Character Draw and Area Filting Start

1
GCHRD:

On execution of this instruction, the HGDC loads the
parameters from the parameter RAM into the drawing
processor and starts the drawing process at the pixel pointed
to by the cursor, EAD, and the dot address, dAD.

I°

1

Based on parameters loaded with the FIGS command, this
command initiates the drawing of the graphics character or
area filling pattern stored in Parameter RAM. Drawing
begins at the address in display memory pOinted to by the
EADand dAD values.

DATA READ COMMANDS
Figure Drawing Parameters Specify

FIGS:

Read Data from Display Memory

L.I_O.....L....--l._-'--'---'_-'--'-_O...1

RDAT:

ll. . . . --'---..I.I_~-tP_E...J1'-o_II...-

MO
O.......
.....

....

.-t

o

1 - _ O - - - - - - - H l g h byta oItha WOrd only

Figure 1\Ipe Select BHs:
' - - - - - - - Line (Vecto,)
' - ' - - , - - - - - - - Graphics Character
'-'---------ArcJCircle

1--o-------lnvalld

'-----------Rectangle
' - - - - - - - - - - - - Slanted Graphics Chafacter

:1
:1
:1
:1

~oo_._

,

i

DC,

,

GO!

\

Graphlcs Drawing flag for uaeln
Mixed Graphl.. and Cha'acter Mod,

USing the DIR and DC parameters of the FIGS command
to establish direction and transfer count, multiple RMW
cycles can be executed without specification of the cursor
address after the initial load (DG = number of words or
bytes).
As this instruction begins to execute, the FIFO buffer direction is reversed so that the data read from display memory
can pass to the microprocessor. Any commands or parameters in the FIFO at this time will be lost. A command byte
sent to the HGDC will immediately reverse the buffer direction back to write mode, and all RDAT information not yet
read from the FIFO will be lost. MOD should be set to 00 if
no modification to video buffer is desired.

Cursor Address Read

~.--

0,

Low byte of the Word only

o ..

Drawing Direction Base

DC,

Dabl'll'an.Io'1\Ipa:

0 - _ o - - - - - - - W O r d , low then high byte

0,

,

The following bytes are returned by the HGDC through the
FIFO:

~~--

02,

PI

A7

Execute Address (EAD~

02,

low byte

,

01,

0

0

01,
I

r---

~2

AIS

o

Exec:tJte Address (EAO).
middle byte

0

0

0

0

Execute Add,... (EAO),
hlghblts

0

I-

i2--

r--

lbe parameters take on
different Intarp_tlonalor
different Ilgure types.

310

Dot Addre•• (dAD), low byte

Dot Add,... (dAD), high byte

The Execute Address, EAD, points to the display memory
word containing the pixel to be addressed.
The Dot Address, dAD, within the word is represented as a
1-of-16 code for graphics drawing operations.

DMA CONTROL COMMANDS

Light Pen Address Read

DMA Read Request

The following bytes are returned by the HGDC through the
FIFO:

...

E,_~

~: ILt~,--~~IL-T_YPrE~IL-'..JIL-M~O~D~
I_.~

_____

Data Transfer Type:

o __o - - - - - - - W o r d , Low then High Byte

o -.0_----- Low Byte of the Word

_~......, _A--,OI---LI9ht Pen Addre••, low byte

1 -........- - - - - High Byte of the Word

_LA-,-D'......

1 _ ..
o_-----Invalid

I

A15 .

L ,_

., . ._ ' - -. . . . . ._

LAD",

AS

I--

_,,--~_,--...J.

.' . .

Ugh! Pen Address,
middle byte

LI_O~_,--~_,--~_O.JI_LA~D_"..JI- Light

DMA Write Request
DMAW:

Pen Address, high byte

_RMW Memory Logical Operation:

The light pen address, LAD, corresponds to the display word
address, DAD, at which the light pen input signal is detected
and deglitched,
The light pen may be used in graphics, character, or mixed
modes but only indicates the word address of light pen
position.

o ~REPLACE with Pattern
1

-4---

COMPLEMENT

O~RESeTtoZero
1~SETtoOne

I _ - - - - - - D a t a Transfer Type:

o ..
Word, Low then High Byte
o -.__- - - - - Low Byte of the Word
1 -.O--------High Byte of the Word
1 - ........- - - - - I n v a l i d

311

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground
Power Dissipation

O°C to 70°C
- 65°C to 150°C
- 0.5V to + 7V
1.5 W

'COMMENT: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC CHARACTERISTICS T. = O°C to 70°C; Vee = 5V ± 10%; GND = OV
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Leak Current
(except VSYNC, !JACK)
Input Low Leak Current
(VSYNC, 0ACKj

Symbol
VIL
V,H
VOL
VOH
IlL

~~put High Leak Current

except LPEN/DH)
In~ut High Leak Current
(L ENI H)
Output Low Leak Current
Output High Leak Current
Clock Input Low Voltage
Clock Input High Voltage
Vee Supply Current

Limits
Typ

Min
-0.5
2.2

Max
0.8
Vee + 0.5
0.45
-10

Unit
V
V
V
V
fLA

IlL

-500

fLA

I'H

+10

fLA

I'H

+500

fLA

-10
-10
0.6
Vee - 1.0
270

fLA
fLA
V
V
mA

2.4

lo,
10H
Vel
VeH
Icc

-0.5
3.5

Test
Conditions
(j)

®@
lo, = 2.2mA
10H = - 400 fLA
V, = OV

V, = Vee
Vo = OV
Vo = Vee

CAPACITANCE T. = 25°C; Vee = GND = OV
Parameter
Input Capacitance
1/0 Capacitance
Output Capacitance
Clock Input Capacitance

Symbol
C'N

Min

Limits
l}tp

C'IO

Unit
pF
pF
pF
pF

Max
10
20
20
20

Test
Conditions
fc = 1 MHz

V,
(unmeasured) = OV

Notes:
(j) For 2XWCLK, VIL = - 0.5V to +O.6V.

® For 2XWCLK, V,H = + 3.9V to Vee + 1.0V.

@ForVVR,V,H =2.5VtoVee +0.5V.

AC Characteristics, T. = O°C to 70°C; Vee = 5.0V ± 10%; GND = OV
Read Cycle
Parameter
Address Setup to FID !
Address Hold from FID t
IfCj Pulse Width
Data Delay from RD!
Data Floating from AD t
FID Pulse Cycle

Write Cycle
Parameter
Address Setup to WI=! !
Address Hold from WR t
WR Pulse Width
Data Setup to Wl'!t
Data Hold from WI'!
WI=! Pulse Cycle

(HGDC.....CPU)
Symbol
tAR
tRA
tRR1

tR01

to,
tROV

7220AD Limits
Min
Max
0
0
tRcy•V2IcLK
tRO' +20
75
0
75
4 teLK

7220AD-1 Limits
Min
Max
0
0
tROY· V.lclK
tRO' + 20
65
0
65
4telK

7220AD-2 Limits
Min
Max
0
0
tRo, + 20
tReY· V2lclK
55
0
55
4 teLK

Unit
ns
ns
ns
ns
ns
ns

7220AD-1 Limits
Min
Max
0
10
70
twCY - teLl<
55
10
4telK

7220AD-2 Limits
Max
Min
0
10
60
t wCY - tCLK
45
10
4tCLK

Unit
ns
ns
ns
ns
ns
ns

Test
Conditions

Cl = 50pF

(HGDC.....CPU)
Symbol
t""
tWA
tww
tow
two
twev

7220AD Limits
Min
Max
0
10
80
twev - tClK
65
10
4 teLK

312

Test
Conditions

DMA Read Cycle

(HGDC<-->CPU)

Parameter
Symbol
DACK Setup to RD 1
tKR
DACK Hold from RD i
tRK
RD Pulse Width
tRR2
Data Delay from RD 1
tRD2
DREQ Delay from
tREQ
2XWCLK i
DREQ Setup to DACK I
tOK
DACK High Level Width
tDK
DACK Pulse Cycle
tE
DREQ I Delay from
tKQ(R)
DACKI
DACK Low-level Width
tlK
for high byte and low byte transfers: tE

.

DMA Write C¥cle
Parameter
DACK Setup to WR 1
DACK Hold from WR i

R/M/WCycle
Parameter
Address/Data Delay
from 2XWCLK i
Address/Data Floating
from 2XWCLK i
Input Data Setup to
2XWCLKI
Input Data Hold from
2XWCLKI
DBIN Delay from
2XWCLKl
ALE i Delay from
2XWCLKi
ALE I Delay from
2XWCLKI
ALE Width
ALE Low Width
Address Setup to ALE 1

Display Cycle
ParametC:tr
Video Signal Delay
from 2XWCLK i

Input Cycle
Parameter
Input Si~nal Setup to
2XWCL i
Input Signal Width

Clock
Parameter
Clock Rise Time
Clock Fall Time
Clock High Pulse Width
Clock Low Pulse Width
Clock Cycle

7220AO Limits
Min
Max

7220AO-1 Limits
Min
Max

1.5telK + 80

1.5tclK + 70

1.5tclK + 60

Unit
ns
ns
ns
ns

100

85

75

ns

a
a
tRD2

a
a

+ 20

a
a

+ 20

tRD2

a

tRD2

a

+ 20

a

tcLK

tCLK

tCLK

4t CLK '

4 tCLK '

4 t CLK'

telK + 100
~

7220AO-2 Limits
Min
Max

Cl

~

50 pF

Cl

~

50 pF

Cl

~

50 pF

ns
ns
ns

telK + 90

IccK + 80

ns
ns

2tCLK

2tCLK

2tcLK
5 telK

Test
Conditions

(GDC<-->CPU)
Symbol
tKW
tWK

7220AO Limits
Min
Max

a
a

I
I
I

7220AD-1 Limits
Max
Min

a
a

I
I
I

7220AO-2 Limits
Min
Max

I
I
I

Unit
ns
ns

7220AO-2 Limits
Min
Max

Unit

a
a

Test
Conditions

(GDC+->Display Memory)
Symbol
tAD
tOFF

7220AO Limits
Min
Max
20

105

20

105

7220AO-1 Limits
Min
Max
20

90

20

90

15

80

15

80

ns

Cl

~

50pF

ns

Cl

~

50pF

a

a

a

ns

tDIH

tDE

tDE

tDE

ns

tDE

20

80

tRR

20

tRF

20

tOIS

tRw
tRl
tAA

Test
Conditions

60

ns

Cl

~

50pF

15

60

ns

Cl

~

50pF

15

50

ns

Cl

~

50 pF

ns
ns
ns

C l - 50 pF

20

70

15

80

20

70

65

20

55

1/3 tCLK

VstCLK

1/3 tCLK

1.5telK - 30
30

1.5telK - 30
30

1.5telK - 30
30

(GDC+->Display Memory)
Symbol

72200 Limits
Min
Max

I
I

tVD

72200-1 Limits
Min
I Max

90

I

72200-2 Limits
Min
I Max

80

I

70

Unit
ns

Test
Conditions
Cl

~

50 pF

(GDC+->Display Memory)
Symbol

7220AO Limits
Min
Max

7220AO-1 Limits
Min
Max

7220AO-2 Limits
Min
Max

Unit

tps

10

10

10

ns

tpw

tCLK

tCLK

tcLK

ns

7220AO Limits
Min
Max
15
15
70
70
165
10,000

7220AO-1 Limits
Min
Max
15
15
61
61
145
10,000

7220AO-2 Limits
Min
Max
15
15
52
52
125
10,000

Test
Conditions

(2XWCLK)
Symbol
teR
teF

tcH

Icc
tCLK

313

Unit
ns
ns
ns
ns
ns

Test
Conditions

Display Memory Display Cycle Timing

Microprocessor Interface Write Timing

AO:~'.f3:validt.,
WR:

tww

t

tnvalld

~t-alld

-

hhh

::~
~t,,~

•

:1~

DBO-7:--""lnv--'a::-lid-:-li--~'--I:-nv-a"'lId""""-1f---

1----1." -----1

A16.A17:~[
ALE:

Microprocessor Interface Read Timing

AO:E!!Dj'f-_-!.va=li:::d_~j(
____
RD:

~~'~I

Invalid

x::=

I

I

C

-l t"W" r -k, ~

t.,
-It.,
~

HSYNC-REF:

BLANK

,-~t,~~_ _ _ _ _~

VSYNC
LCD 3
CSR
CSR-IMAGE

~

ATT-BLINK-CLC

High
080-7: Impedance

High Impedance

i - - - - - tRCy

Display Memory RMW Timing
Microprocessor Interface DMA Write Timing
2xWCLK:

ADO-15:

2xWCLK:

DREQ:

+.JH_______t---__

A16. A17:.__

DACK:

~L__

ALE:

WR:

·\-o----tR'----~

t_ (WR i to HSYNC i ) ~ !elK
~H (DACK

t to HSYNC i ) :;;. teLK

Microprocessor Interface DMA Read Timing

2xWCLK:

DREQ:

DACK:

RD::-------J:~=-.:~+=~

TIMING WAVEFORMS

314

Display and RMW Cycles (1x Zoom)

1-"'+~--"-r·~1-~-r.+" ~'rw
--~~.---

-

2xWCLK:

ALE:

ODIN:

~

(J1

AOO-15:

A16,17:

HSVNC:

BLANK:

__-'x----- . ----.. y,

uX,-_ _

V!EXTSYNC:

TIMING WAVEFORMS

•

,,-

Display and RMW Cycles (2x Zoom)

-1--"
"~welKe

I

ALE-b

OBIN,

~

(l)

ADO-1S:

I
I
I

At6. t7

=:ex

BLANK,

=--c\

\

I

\

I

+:'-':j
I
,I~

\

I

I~-----+-------

\

I

Output Add,.ss

I

Output Add,.ss

X

I

Output Add,.ss

X

I

I

TIMING WAVEFORMS

Input 0".

~I/~
Output 0","

I

Output Add,ess

X'-_ __

\~

___

Zoomed Display Operation with RMW Cycle (3x Zoom)

2xWCLK

\

DB IN

f

~

-..j

Couiput Address~

ADO-15: -+-----<

Output Data)

I

I

i

( Output Address}-

X'--_ __

!\~

Clock Timing (2XWCLK)

Light Pen and External Sync Input Timing
2xWCLK:

r-\ r-\ h r\.
-Ie==-;:~I-:-

- -

LPEN,---EX. SVNC:____

.
t~

Video Sync Signals Timing

I

I

IH

2 X W C L K : J " \ . f \ . . / ' \ . . / \ ____

./\../V\.../V\. __ ~ ___ ~ __ J\..
----~--~

HBLANK:J

I

HSVNC:

ADO-I5::X::=:X:=:::X::

~~

,'--____________

===::x=:::::x=::x:= ==x:::::::x: ~ == :x:=====:t:
I

LCO-4:=:J(

: \

r--1H~--------------------------------------------~
AOD-IS:-V-VV- -

..JJ'-"-"-~-

:xxx:x: -- .J\JI..J\J\...__________________________-:x:x:xx: --- :xx:
I

__ ""V"V"V'""V"- - - - - - - - - - - - - - - - - - - - - - - - -

LCO-4:-\r- --- -v--------y--- -- ---- -- -- ---------------

-:'i'--- -- - - - A - ___ - A . . - ____ -

~---:x:
- - - - - - - - - -- - - - - - - - -- - - - " - - - -

~:=*~-------~-------------------------------------------~(:
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ______ 1

ROW:=*==*==x:: ====:x:=:J<
:

' - - __

n

=~~:x::

--- -

I

vaLANK:

--II

_ _

-I1

vsVNC:...,.'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

'---

t-------------- 1V (FramOI ------------------.!.!
Interlaced Video Timing
HBLANK:JL __

--.JLJL __ JLJL __ ~ __ --1L __ JL __ JLJL __ JLJL_

I

I

I
VSVNC: I
(Interlace) I

I

I

VBLANK:1-- __ ~---,-----

I

I.

I
I I
I I
--L
__ S----,-,
------,-,---

I

I

I

I
I

I

I
I

I

I

I

I

L--

I

I-

Odd Field

Even Field - - - - - " ' - - - -

I

I

I

I

I

VSVNC:
(No Interlace)r:-.----------'

TIMING WAVEFORMS

318

L-

--------,

r-------Clock

CRT 72201
HGDC

0lI0-7

Data
Graphics

Input

MI

DevIces

Blanking
HSYNC
(,)

<0

YSYNC

LPEN

Host
Computer

--------------------------~

BLOCK DIAGRAM OF A GRAPHICS TERMINAL

Video Horizontal Sync Generator Parameters

1~'----------

_________

IH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~'1
I

~

HBLANK:----.J

______________________________

I
I
~r--

I

I
I
HSVNC:

rI~

I
I

______ ____________________________
~

I

I

I

I
I

I

I

I

~

----1 H:t~HBP-.+------I.- - - - C I A - - - - - - i

Video Vertical Sync Generator Parameters

-------IV----------1·1

lfo-'

VBLANK:
I

II

I

I

I

I

I

I

L,

VSVNC:~~_ _ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~----~r-1L----------'---

I
I

I
I

I--

I
VBP

I
I

I
I

iVFPr-1

I

---r'I-'- - - - - - L I F - - - - - - - - - j - l

I
I

i

---jVS

Cursor-Image Bit Flag

--I I--'c,.
2 x CCLK

"'""
HSVNC

CAS-Image

-.n..nnn

--tr1I-r>-----<'

n~~

~ ''"L-

10'C'.~

Invalid

,L

>G~
Image

TIMING WAVEFORMS

320

tBP--j

VIDEO FIELD TIMING
--II

fL----

HSYNC Output
BLANK Output

---.J! !

I""iI----

I '
: 1
H---+----;Ve=rt;::lc::calC;;S;;;Y"'N:;:;:C-;-l;:ln=o.,-----k:~-t-----·

Vertical aack Porch Blanked Lin..
Horizontal
SYNC~

Pulse
Horizontal
Front Porch--<
Blanking

Active

Dlaplay
Lines
Horizontal

Back Porch

__

Blanking
""
~

Vertical Front Porch Blanked Lines

~~-------------~~----

DRAWING INTERVALS

~

Drawing Interval

~ Additional Drawing Interval When
~ In Flash Mode

~ Dynamic RAM Refresh If Enabled, Otherwise
~ Additional Drawing Interval

DMA REQUEST INTERVALS

DMA Aequelt Interval
Add~l.nll DMA Requollintorvall
When In Flash Mode

321

Circuit diagrams utilizing SMC products are included as a means of illustrating typical applications; consequently
complete information sufficient for construction purposes is not necessarily given. The information has been carefully
checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore,
such information does not convey to the purchaser of the products described any license under the patent rights of
SMC or others. SMC reserves the right to make changes at any time in order to improve design and supply the l1est
pFOduct possible.

322

CRT 8002
jLPCFAMILY

CRT Video Display Attributes Controller
Video Generator
VDACTM
FEATURES

PIN CONFIGURATION

o On chip character generator (mask programmable)
o

o

o
o

o

o
o
o

VIDEO
LD/SH

1

28 RETBL

128 Characters (alphanumeric and graphic)
2
27 CURSOR
7 x 11 Dot matrix block
VDC 3
26 Msi1l
On chip video shift register
A0 4
25 MS1
Maximum shift register frequency
A1 5
24 BLINK
CRT 8002A
20M Hz
A2 6
23 V SYNC
CRT 8002B
15MHz
A3 7
CRT 8002C
10MHz
22 CHABL
Access time
400ns
A4 8
21 REVID
On chip horizontal and vertical retrace video blanking
A5 9
20 UNDLN
No descender circuitry required
A6 10
19 STKRU
Four modes of operation (intermixable)
A7 11
18 ATTBE
I nternal character generator (ROM)
17 GND
Vee 12
Wide graphics
R2 13
16 R0
Thin graphics
R3 14
15 R1
External inputs (fonts/ dot graphics)
On chip attribute logic-character, field
Subscriptable
Reverse video
Expandable character set
Character blank
External fonts
Character blink
Alphanumeric and graphic
Underline
RAM, ROM, and PROM
Strike-thru
On chip address buffer
Four on chip cursor modes
On chip attribute buffer
Underline
+ 5 volt operation
Blinking underline
o TTL compatible
Reverse video
Blinking reverse video
MOS N-channel silicon-gate COPLAMOS® process
Programmable character blink rate
CLASP® technology-ROM and options
Programmable cursor blink rate
o Gompatible with CRT 5027 VTAC®

o
o

o
o
o
o
o

General Description
The CRT 8002 attributes include: reverse video, charThe SMC CRT 8002 Video Display Attributes Controller
acter blank, blink, underline, and strike-thru. The
(VDAC) is an N-channel COPLAMOS® MaS/LSI device
which utilizes CLASP® technology. It contains a
character blink rate is mask programmable from 7.5 Hz
7X11X128 character generator ROM, a wide graphics
to 0.5 Hz and has a duty cycle of 75/25. The underline
mode, a thin graphics mode, an external input mode,
and strike-thru are similar but independently concharacter address/data latch, field and/or character
trolled functions and can be mask programmed to any
attribute logic, attribute latch, four cursor modes, two
number of raster lines at any position in the character
programmable blink rates, and a high speed video
block. These attributes are available in all modes.
shift register. The CRT 8002 VDAC'· is a companion
In the wide graphic mode the CRT 8002 produces a
chip to SMC's CRT 5027 VTAC. Together these two
graphic entity the size of the character block. The
chips comprise the circuitry required for the display
graphic entity contains 8 parts, each of which is assoportion of a CRT video terminal.
ciated with one bit of a graphic byte, thereby providThe CRT 8002 video output may be connected directly
ing for 256 unique graphic symbols. Thus, the CRT
to a CRT monitor video input. The CRT 5027 blanking
8002 can produce either an alphanumeric symbol or
output can be connected directly to the CRT 8002
a graphic entity depending on the mode selected.
retrace blank input to provide both horizontal and
The mode can be changed on a per character basis.
vertical retrace blanking of the video output.
The thin graphic mode enables the user to create sinFour cursor modes are available on the CRT 8002.
gle line drawings and forms.
They are: underline, blinking underline, reverse video
block, and blinking reverse video block. Anyone of
The external mode enables the user to extend the onthese can be mask programmed as the cursor funcchip ROM character set and/ or the on-chip graphics
tion. There is a separate cursor blink rate which can
capabilities by inserting external symbols. These exbe mask programmed to provide a 15Hz to 1 Hz blink
ternal symbols can come from either RAM, ROM or
323 PROM.
rate.

iii;!!!!;

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.

r~:J~~~~

,

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
applications: COI)S8quenlly comf:)!ete information sufficient for construction purposes is not necesssrily gill8n.
The information has been carefully checked and is believed to be entirely reliable. However, no re.sponsibllily is
assumed for Inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reseMs'the
right to make changes at any time in order to improll8 design ana supply the best product possible.

324

CRT8002H
CRT Video Display Attributes Controller
Video Generator
VDACTM
FEATURES

PIN CONFIGURATION

o On chip character generator (mask programmable)
o
o
o
o
o

o

o
o
o
o
o

128 Characters (alphanumeric and graphic)
7 x 11 Dot matrix block
On chip video shift register
Maximum shift register frequency 25 MHz
ROM Access time 310 ns
On chip horizontal and vertical retrace video blanking
No descender circuitry required
Four modes of operation (intermixable)
Internal character generator (ROM)
Wide graphics
Thin graphics
External inputs (fonts/dot graphics)
On chip attribute logic-character, field
Reverse video
Character blank
Character blink
Underline
Stri ke-th ru
On chip cursor
Programmable character blink rate
Programmable cursor blink rate
Subscriptable
Expandable character set
External fonts
Alphanumeric and graphic
RAM, ROM, and PROM

VIDEO
LD/SH

2

VDC
All
Al
A2

3
4
5
6

A3 7
A4 8
A5 9
AS 10
A7 11
Vee 12
R213
R314

28 RETBL
21 CURSOR
26 MSII
25 MSl
24 BLINK
23 V SYNC
22
21
20
19
18
17
16
15

CHABL
REVID
UNDLN
STKRU
ATTBE
GND
R~

Rl

o On chip address buffer
o On chip attribute buffer
o +5 volt operation
o TTL compatible
ON-channel COPLAMOS® Titanium
Disilicide Process
Compatible with CRT 5027/37 VTAC®

o

General Description
The SMC CRT 8002H Video Display Attributes Controller
(VDAC) is an n-channel COPLAMOS$ MaS/LSI device. It contains a 7X11X128 character generator ROM,
a wide graphics mode, a thin graphics mode, an external
input mode, character address/data latch, field and/or
character attribute logic, attribute latch, four cursor
modes, two programmable blink rates, and a high speed
video shift register. The CRT 8002H VDAC is a companion chip to SMC's CRT 5027/37 VTAC@. Together
these two chips comprise the circuitry required for the
display portion of a CRT video terminal.
The CRT-8002H video output may be connected directly.
to a CRT monitor video input. The CRT 5027137 blanking
output can be connected directly to the CRT 8002H
retrace blank input to provide both horizontal and
vertical retrace blanking of the video output.
The CRT 8002H attributes include: reverse video, character blank, blink, underline, and strike-thru. The
character blink rate is mask programmable from 7.5 Hz
to 1.0 Hz and has a duty cycle of 75/25. The underline
325

and strike-thru are similar but independently controlled
functions and can be mask programmed to any number
of raster lines at any position in the character block.
These attributes are available in all modes.
In the wide Qraphic mode the CRT 8002H produces a
graphic entity the size of the character block. The
graphic entity contains 8 parts, each of which is associated with one bit of a graphic byte, thereby providing
for 256 unique graphic symbols. Thus, the CRT 8002H
can produce either an alphanumeric symbol or a graphic
entity depending on the mode selected. The mode can
be changed on a per character basis.
The thin Qraphic mode enables the user to create single
line draWings and forms.
The external mode enables the user to extend the onchip ROM character set and/or the on-Chip graphics
capabilities by inserting external symbols. These external symbols can come from either RAM, ROM or
PROM.

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.

~~Q:I~~~ ~H;~~~== Circuit
diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
applications: consequently complete information sufficient for construction purposes is not necessarily given.

,.

The information has been carefUlly checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of Ihe
...",.... semiconductor devices described any license under the patent rights of SMC or others. SMC reserves "the
right to make changes at any time in order to improve design ana supply the best product possible.

~"!e..",!'''''M

,.

326

CRT 8021
CRT 8021-003
CRT Video Attributes Controller
Video Generator
VAC
FEATURES
D ON CHIP VIDEO SHIFT REGISTER

PIN CONFIGURATION

Maximum shift register frequency-20MHz
Maximum character clock rate-2.SMHz

VIDEO

D ON CHIP HORIZONTAL AND VERTICAL RETRACE
VIDEO BLANKING

D ON CHIP GRAPHICS GENERATION
D ON CHIP ATTRIBUTE LOGIC-CHARACTER, FIELD
Reverse video
Character blank
Character blink
Underline
Strike-thru

D ON CHIP BLINKING CURSOR
D ON CHIP DATA BUFFER
D ON CHIP ATTRIBUTE BUFFER
D +S VOLT OPERATION
D TTL COMPATIBLE
D MOS N-CHANNEL SILICON-GATE COPLAMOS®

LD/SH
VDO
A0
A1
A2
A3

1
2
3
4

5
6
7
A4 8
A5 9
A610
A711
Vee 12
R213
R314

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RETBL
CURSOR
Msa
MSI
BLINK
VSYN
CHABL
REVID
UNDLN
STKRU
ATTBE
GND
RO
R1

D COMPATIBLE WITH CRT S027/37 VTAC® AND

PROCESS

CRT 9007 VPAC

GENERAL DESCRIPTION
The SMC CRT 8021 Video Attributes Controller (VAG)
isan n-channel COPLAMOS® MOS/LSI device. It contains wide and thin graphics logic, attributes logic, a
data latch, field and character attribute latch, a blinking
cursor, and a high speed video shift register. The CRT
8021 VAC is a companion to SMC's CRT S027/37 VTAC®
or CRT 9007 VPAC. The CRT 8021 and a character ROM
combined with either a CRT S027/37 or a CRT 9007 comprises the major circuitry required for the display portion
of a CRT video terminal.

strike-thru are similar but independently controlled
functions. These attributes are available in all modes.
The thin graphic mode enables the user to create single
line drawings and forms.
In the wide graphic mode the CRT 8021 produces a
graphic entity the size of the character block. The graphic
entity contains 8 parts, each of which is associated with
one bit of a graphic byte, thereby providing 2S6 unique
graphic symbols. Thus, the CRT 8021 can produce either
alphanumeric symbols or various graphic entities
depending on the mode selected. The mode can be
changed on a per character basis.

The CRT 8021 video output may be connected directly
to a CRT monitor video input. The CRT S027/37 or
CRT 9007 blanking output can be connected directly to
the CRT 8021 retrace blank input to provide both horizontal and vertical retrace blanking of the video output.
A blinking cursor is available on the CRT 8021. There is a
separate cursor blink rate which is twice the character
blink rate and has a duty cycle of SO/SO.

The CRT 8021 is available in two versions. The CRT 8021
provides an eight-part graphic entity which fills the
character block. The CRT 8021 is designed for seven dot
wide, nine or eleven dot high characters in nine by twelve
or ten by twelve character blocks.

The CRT 8021 attributes include: reverse video,character
blank, blink, underline, and strike-thru. The character
blink rate has a duty cycle of 7S/2S. The underline and

The CRT 8021-003 provides a six part graphic entity for
five by seven or five by nine characters in character blocks
of up to seven by ten dots.
327

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.
DARD MICROSVSTEMS
~
POR A~I
_
u lUI"

.

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
!lPplications: consequently comp'lete information sufficient for construction purposes Is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
".......
.""'" assumed for inaccuracies. Furlhermore, such information does not convey to the urchaser of .the
'''.2'''31oo.~.m..... semiconductor devices described any license under the patent rights of SMC or others. ~MC reserves the
right to make changes at any time in order to Improve design ana supply the best product possible.

328

CRT 9006-135
CRT 9006-83
Single Row Buffer
SRB
PIN CONFIGURATION

EATURES:
] Low Cost Solution to CRT Memory Contention Problem
] Provides Enhanced Processor Throughput for CRT
Display Systems
] Provides 8 Bit Wide Variable Length Serial Memory
] Permits Active Video on All Scan Lines of Data Row
] Dynamically Variable Number of Characters per Data Row... 64,80, 132, ... up to a Maximum of 135
] Cascadable for Data Rows Greater than 135 Characters
] Stackable for Invisible Attributes or Character
Widths of Greater than 8 Bits
] Three-State Outputs
]3.3MHz Typical Read/Write Data Rate
] Static Operation
] Compatible with SMC CRT 5037, CRT 9007, and other
CRT Controllers
]24 Pin Dual In Line Package
1+5 Volt Only Power Supply
1TTL Compatible Inputs and Outputs
1Available in 135 Byte Maximum Length (CRT 9006-135)
or 83 Byte Maximum Length (CRT 9006-83)

DOUT3

GND

DOUT2

DOUT4

DOUT1

DOUT5

DOUH

DOUT6

CLK

DOUT7

WREN

6E

CLRCNT

OF

CKEN

DIN7

DIN~

DIN6

DIN1

DIN5

DIN2

DIN4

DIN3

+5V
Package: 24-pin D.I.P.

APPLICATIONS:

o CRT Data Row Buffer
o Block-Oriented Buffer
o Printer Buffer
o Synchronous Communications Buffer
o Floppy Disk Sector Buffer

GENERAL DESCRIPTION
rhe SMC Single Row Buffer (SRB) provides a low cost solu:ion to memory contention between the system processor and
:RT controller in video display systems.
rhe SRB is a RAM-based buffer which is loaded with character
jata from system memory during the first scan line of each
jata row. While data is being written into the RAM it is also
)eing output through the multiplexer onto the Data Ouput

(DOUT) Lines. During subsequent scan lines in the data row,
the system will disable Write Enable (WREN) and cause data
to be read out from the internal RAM for CRT screen refresh,
thereby releasing the system memory for processor access
for the remaining N-1 scan lines where N is the number of
scan lines per data row. The SRB enhances processor throughput and permits a flicker-free display of data.

0'

CCK

CKEN

OCTAL

2T01

MUX

o

,

L

NA
U
C

1----1

T H

DIN7-0

P T

329

B
U

P C

F
E
R

~

~§:=~==~

3-STATE
L

U A
T T
H

F

OOUT7-0

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

NAME

SYMBOL

1-4

DATA OUTPUTS

DOUT3-DOUT0

5

CLOCK

6

WRITE ENABLE

7

CLEAR COUNTER

8

CLOCK ENABLE

9-12
13
14-17

DATA INPUTS
POWER SUPPLY
DATA INPUTS

FUNCTION

ClK

Data Outputs from the internal output latch.
Character clock. The negative-going edge of ClK clocks the
latches. When CKEN (pin 8) is high, ClK will increment the
address counter.

WREN

When WREN is low, data from the input latch is transferred directly
to the output latch and simultaneously written into sequential
locations in the RAM.

ClRCNT

A negative transition on ClRCNT clears the RAM address counter.
ClRCNT is normally asserted low near the beginning of each
scan line.

CKEN

When CKEN is high, ClK will clock the address counter. The
combination of CKEN high and WREN low will allow the writing
of data into the RAM.

DIN0-DIN3

Data Inputs from system memory.

+5 Volt supply.

Vee

Data Inputs from system memory.

DIN4-DIN7

18

OVERFLOW FLAG

OF

This output goes high when the RAM address counter reaches its
maximum count. If cascaded operation of multiple CRT9006's is
desired for more than 135 bytes, OF may be used to drive the
CKEN input of the second row buffer chip.

19

OUTPUT ENABLE

OE

When DE is low, the data outputs DOUT0-DOUT7 are enabled.
When DE is high, DOUT0-DOUT7 present a high impedance
state.

20-23
24

DATA OUTPUTS
GROUND

DOUT7-DOUT4
GND

Data Outputs from the internal output latch.
Ground.

OPERATION
For CRT operation, the Write Enable (WREN) Signal is
made active for the duration of the top scan line of each
data row. Clear Counter (CLRCNT) typically occurs at
the beginning of each scan line (HSYNC may be used as
input to CLRCNT). Data is continually clocked into the
input latch by CLK. When Clock Enable (CKEN) occurs,
the data in the input latch (Write Data) is written into the
first location of RAM. At the negative-going edge of the
next clock, the address counter is incremented, the next
input data is latched into the input latch, and the new data
is then written into the RAM. Loading the RAM continues
until one clock after CKEN goes inactive or until the

RAM has been fully loaded (135 bytes). While data is
being written into the RAM, it is also being outputthrough
the multiplexer onto the Data Output (DOUT) lines. Each
byte is loaded into the output latch one clock time later
than it is written into the RAM. Output of the data during
the first scan line permits the Video Display Controller
(such as the CRT 8002) to display video on the first scan
line. During subsequent scan lines inthedata row, thesystem will disable Write Enable (WREN) and cause data to be
read out from the internal RAM, thereby freeing the system memory for processor access for the remaining N-1
scan lineswhereN isthe number of scan lines per data row.
330

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range .................................................................... 0° C to + 70° C
Storage Temperature Range ...............................•....•..•............................. -55° C to + 150° C
lead Temperature (soldering, 10 sec.) .................................................................... +325° C
Positive Voltage on any Pin, with respect to ground ......................................................... +8.0V
Negative Voltage on any Pin, with respect to ground .......................................................... -0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operational
sections of this specification is not implied.

ELECTRICAL CHARACTERISTICS (TA = 0° C to 70° C, Vcc = +5 ±5%, unless otherwise noted)
PARAMETER
DC CHARACTERISTICS
Input Voltage Levels
Low Level VIL
High Level VIH
Output Voltage Levels
Low Level VOL
High Level VOH
Input Current
Leakage, IlL
Output '1' Leakage
Output '0' Leakage
(Off State)
Input Capacitance
ClK
All other inputs
Power Supply Current
Icc (SRB-135)
Icc (SRB-83)
AC CHARACTERISTICS
tey
(SRB135)
(SRB83)
tCKL
(SRB135)
(SRB83)
tCKH
(SRB135)
(SRB83)
CKR
(SRB135)
(SRB83)
CKF
(SRB135)
(SRB83)
DSET
DHOLD
ENCKP
ENCKN
(SRB135)
(SRB83)
ENHOLD
WRCKN
(SRB135)
(SRB83)
t WENHLD
t DOUT
tTSON
tTSOFF
toFON
tCLRS
(SRB135)
(SRB83)
CLRH

MIN

TYP

MAX UNITS

0.8

V
V

0.4
10

V
V
jJA

10
10

JlA
JlA

45
15

pF
pF

115
100

mA
mA

2.0
2.4

30
10

300
400

250
330

240
320

190
250

COMMENTS

IOL=2mA
IOH = -1ooJlA
O$VIN$VCC

ns
ns
DC
DC

ns
ns

5000
5000

ns
ns

10
10

ns
ns

tCKH= 28ns
tcKH=34ns

10
10

tCKL=240ns
tCLK = 320ns

65
5
0

ns
ns
ns
ns
ns

100
125
0

ns
ns
ns

100
125
0

ns
ns
ns
ns
ns
ns
ns

28
34

175
175
175
175
100
125
0

ns
ns
ns
331

CL=50pF
CL=30pF

FIGURE 1: AC CHARACTERISTICS

ClK

CKEN

trSOFF

5E

----------~----------~

OF ____.-~----~~-----'
ClRCNT

___J--Ic",-----_
_______________
~

FIGURE 2: SINGLE ROW BUFFER READ TIMING

~TCZZlTTY--O-N-E----------------------------4! J~--,',~-_-_-_-___-_-_-_-_-_-__-_-_-__

CKEN
ClReNT

:--(~T~i-Y

l1

1"'"1'
: ; ;~7I1ZZZ

ADDRESS COUNTER

(INTERNAL)

Notes. N =0 134 FOR CRT9006~135
N = 82 FOR CRT9006-83
"'"" , eLK PERIOD (m,ni

DOUT7-0

n _ n __

~~

ADDR0

READDATA---v
(INTERNAL) - - - A

'- ______

ADDRl

ADDR2

ADDR N ADDR N+
(LAST ADDR)

~~

~ ~

RDr;J

IZZ7Z7ZZ71ZZ7Z7~

D

DATA N-'X

DATA~~

(LASTDAT~

OF ----------------------------41~

FIGURE 3: SINGLE ROW BUFFER WRITE TIMING

DIN7~(J

===>C==X]D11iAllTAij.DOD21AITTArr,X]D21AITJAIT2X]D21A>,IJAM3Yi

t::::::=>c==>c=

~ ~~'~O~N~E~--.----------------------------~I ~!---(L(---------------------------­
CKEN

l- (~~~ (r------------------------------;l1

~~~~R~fC

WD0

W01

WD2

lA~~::: ~Llll:::::::;::::J

__

~l--~<.-_-_-_-_--_-_-_-_--_-_--_-

~

hfl - :

COUNTER
(INTERNAL)

DOUT7-'

7l7TT77/.. .~

ADDR0.

mnmmnlllD- ~~:T'ii

(

ADDRl

DATAO

ADDR2

X

DATA'

>Q P

== 134 FOR CRT9006.. 135
== 82 FOR CRT9006..83
hI! == 1 elK PERIOD (min.)

Notes: N
N

OF--------------------------------------------<
332

mZWZl/IIZZIIZZIZ,
~
(LAST ADDA)

DATA N-'

X DATA N ) ~~=~:

(LAST DATA)

PROCESSOR
pP/pC

HLDAI---

INT

T
CRT CONTROLLER
(CRT 5037, CRT 9007, .. )

A S }

f----.-+I----

~

SL3 SL2 SL1 SL0 CURS

~

B
U

cn~
~~

S

LU

~

0

MEMORY

N
I
T

o
R

~

~~

r-~ot~~------------------------+--4--~--+--+------~-+~~-------J

9:

:J-I
<10"-

u..

>00

Ci

WRE

L eN

CKEN eLK

CRT 9006
DOUTl-0
SINGLE
ROW BUFFER
~

---,.;

DIN7-0

R3

R2

AI CURSOR

CRT8002
VDAC@

C5E
OF

VIDEOI

FIGURE 2: TYPICAL CRT CONTROLLER CONFIGURATION WITH SINGLE ROW BUFFER

•

MO~g.OR

FIGURE 4:
TYPICAL READ TIMING FOR SRB CASCADED CONFIGURATION
CLK~

CKENA
CLRCNTA,B
DOUT7-0A
OFA= CKENB
DOUT7-00

~

'\

''-----------11 t-J

r--------""--

L./'--

, "

'

~tXJDQi"';;;.!)(lD~N;!-.XQD;;N-:;:'X::]ii:=4..!t:!'B§~~L""':~\------------

-------------i}-----Jf.::~~~------~~~-----_tT---------------------1 ~---------~Q~XQD;;..!:.X!~!Y-!!~=::~c:...-_i t-------

Notes: N = t34 FOR CRT9006-135
N = 82 FOR CRT900So93
EXAMPLE IS FOR N+3 CHARACTERS TOTAL
A, B REFER TO DEVICES A&B IN FIGURE 5

FIGURE 5:
TYPICAL CASCADE OF SINGLE ROW BUFFERS-270 BYTES TOTAL

DATA OUT TO CHARACTER GENERAT~?

ClRCNT
WREN
ClK
CKEN

f--DOUT7-0

L-

t---

'-'----

ROW BUFFER
A

OF
OE

DATA INPUT FROM MEMORY> DIN7-0

p-ov

CRT 9006-135

?

ClRCNT
WREN
ClK
CKEN

oo",,~J
ROW BUFFER
B

DIN7-0

OF
OE

r-

p-ov

CRT 9006-135

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applica~
tions; consequently complete information sufficient for construction purposes is not necessarily given, The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does notconveytothe purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

334

CRT9007A2*
CRT9007A1*
CRT9007A
CRT Video Processor CRT9007B
CRT9007C
and Controller
*PRELIMINARY
VPACTM
FEATURES

PIN CONFIGURATION

o Fully Programmable Display Format

o

o

o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o

Characters per Data Row (8-240)
Data Rows per Frame (2-256)
Raster Scans per Data Row (1-32)
Programmable Monitor Sync Format
Raster Scans/Frame (4-2048)
Front Porch-Horizontal (Negative or Positive)
-Vertical
Sync Width - Horizontal (1-128 Character Times)
- Vertical (2-256 Scan Lines)
Back Porch - Horizontal
-Vertical
Direct Outputs to CRT Monitor
Horizontal Sync
Vertical Sync
Composite Sync
Composite Blanking
Cursor Coincidence
Binary Addressing of Video Memory
Row-Table Driven or Sequential Video Addressing Modes
Programmable Status Row Position and Address Registers
Bidirectional Partial or Full Page Smooth Scroll
Attribute Assemble Mode
Double HeightPata Row Mode
Double Width Data Row Mode
Programmable DMA Burst Mode
Configurable with a Variety of Memory'Contention
Arrangements
Light Pen Register
Cursor Horizontal and Vertical Position Registers
Maskable Processor Interrupt Line
Internal Status Register
Three-state Video Memory Address Bus
Partial or Full Page Blank Capability
Two Interlace Modes: Enhanced Video and Alternate
Scan Line

VA21
VA102
VA33
VA114
VA125
VA46
VA137
VA58
VA69
VA710
VLT 11
VS 12
RS13
CCI:R14
J:lRB 15
VD716
VD617
VD518
VD419
VD320

40GND
39VA9
38VA1
37VAB
36VAO
35 CBLANK
34 CURS
33ACKIl'SC
32 CS'i'Ii/C/LPSTB
31 SLD/SLO
30 "Sm/Sl1
29 WBEN/SL2ICS'i'Ii/C
28 DMARISL3NBLANK
271NT
26 R"ST
25CS
24VDO
23VD1
22VD2
21 +5V

o Ability to Delay Cursor and Blanking with respect to
Active Video

o Programmable for Horizontal Split Screen Applications

o Graphics Compatible
o Ability to Externally Sync each Raster Line, each Field
o Single +5 Volt Power Supply
o TTL Compatible on All Inputs and Outputs
o VT-100 Compatible
o RS-170 Interlaced Composite Sync Available

GENERAL DESCRIPTION

The CRT 9007 VPAC'· is a next generation video processor/
controller-an MOS LSI integrated circuit which supports either
sequential or. row-table driven memory addressing modes. As
indicated by the features above, the VPAC'· provides the user
with a wide range of programmable features permitting low cost
implementation of high performance CRT systems. Its 14 address
lines can directly address up to 16K of video memory. This is
equivalent to eight pages of an 80 character by 24 line CRT display. Smooth or jump scroll operations may be performed anywhere within the addressable memory. In addition, status rows
can be defined anywhere on the screen.
In the sequential video addressing mode, a Table Start Register
pOints to the address of the first character of the first data row on
the screen. It·can be easily changed to produce a scrolling effect
on the screen. By using this register in conjunction with two auxiliary address registers and two sequential break registers, a screen
roll can be produced with a stable status row held at either the first
or last data row position.

335

In the row-table driven video addressing mode, each row in the
video display is designated by its own address. This provides the
user with greater flexibility than sequential addressing since the
rows of characters are linked by pOinters instead of residing in
sequential memory locations. Operations such as data row
insertion, deletion, and replication are easily accomplished by
manipulating pOinters instead of entire lines. The row table itself
can be stored in memory in a linked list or in a contiguous format.
The VPAC ,. works with a variety of memory contention schemes
including operation with a Single Row Buffer such as the CRT 9006,
a Double Row Buffer such as the CRT 9212, or no buffer at all, in
which case character addresses are output during each displayable scan line.
User accessable internal registers provide such features as light
pen, interrupt enabling, cursor addressing, and VPAC'· status.
Ten of these registers are used for screen formatting with the ability to define over 200 characters per data row and up to 256 data
rows per frame. These 10 registers contain the "vital screen
parameters".

CURSOR, BLANK SKEW
CHARIDATAROW

DATA ROWS/FRAME
SCAN LINES/DATA ROW

HORIZ SYNC WIDTH

SCAN LINES/FRAME

CURS

CSYNCI
LPSTB
VA13-0

14 BIT ADDRESS BUS

TIMING
AND
CONTROL

05---------'

CBLANK
INT
SL3IDMAANBLANK
SL2IWBEN/CSYNC
SL11sm
SL1I/SLD

RST
VLT
CCLK--~__________________r~~--------~~

DESCRIPTION OF PIN FUNCTIONS
PROCESSOR INTERFACE:
PIN NO.
NAME
7,5,4,2,39, Video Address
37,10,9,8,6, 13-0
3,1,38,36

SYMBOL
VA13-VAO

16,17,18,19, Video Data 7-0
20, 22, 23, 24

VD7-VDO

FUNCTION
These 14 signals are the binary address presented to the video memo~ by the CRT 9007.
The function depends on the particular CRT 9007 mode of operation. A13-6 are outputs
only. VA5-0 are bidirectional.
-Double Row Buffer Configuration:
VA13-0 are active outputs for the DMA operations and are in their high impedance state at
all other times.
-Single Row Buffer Configuration:
VA13-0 are active outputs during the first scan line of each data row and are in their high
impedance state at all other times.
-Repetitive Memory AddressinR Configuration:
VA 13-0 are active outputs at a I times except during horizontal and vertical retrace at which
time they are in their high impedance state.
If row table addressing is used for either single row buffer or repetitive memory addressing
modes, VA 13-0 are active outputs during the horizontal retrace at each data row boundary to
allow the CRT 9007 to retrieve the row table address. For processor read/write operations
VA5-0 are inputs that select the appropriate internal register.
Bidirectional video data bus: during processor Read/writE! operations data is transferred via
VD7-1lQ9 when chip strobe (CS+iS active. These lines are in their hillh impedance state
when CS is inactive. During CR 9007 DMA operations, data from Video memor is infeut via
VD7-VDO when a new row table address is belnBretrieved or when~he attribute atch s being
updated in the attribute assemble mode. VD7-V 0 are outputs when the external row buffer
is updated with a new attribute in the attribute assemble mode.
Input; this si~nal when active low, allows the frocessor to read or write internal CRT 9007
registers. W en reading from an internal CR 9007 register, the chip strobe (es~ enables the
output drivers. When writin~ to an internal CRT 9007 register, the trailing edge 0 this signal
latches the incoming data. igure 2 shows all processor read/write timing.
Input; this active low sigllmPuts the CRT 9007 into a known, inactive state and insures
that the horizontal sXnc (HS) output is inactive. Activating this Input has the same effect as a
RESET command. fter inillalizatlon, a START command causes normal CRT 9007 operation. See processor addressable registers section, Register 16 for the reset state definition.
Output; an Interrupt to the processor from the CRT 9007 occurs when this signal is active
high. The interrupt returns to its inactive low state when the status register is read.

t

25

Chip strobe

es

26

Reset

RS'i'

27

Int,errupt

INT

336

DESCRIPTION OF PIN FUNCTIONS CONT'D
CRT INTERFACE:
PIN NO.
11

NAME
Visible Line Time

SYMBOL
VLT

12

Vertical Sync

VS

13

Horizontal Sync

HS

14

Character Clock

CCLK

15

Data Row
Boundary

DRB

34

Cursor

CURS

35

Composite Blank

CBLANK

FUNCTION
Output; this signal is active high during all visible scan lines and during the horizontal trace
times at vertical retrace. This signal can be used to gate the character clock (CCLK) when
supplying data to a character generator from a single or double row buffer.
Open drain output; this signal determines the vertical position of displayed text by initiating a
vertical retrace. Its position and pulse width are user programmable. The open drain allows
the vertical frame rate to be synchronized to the line frequency when using monitors with DC
coupled vertical amplifiers. If the VS output is pulled active low externally before the CRT
9007 itself initiates a vertical syng,lhe CRT 9007 will start its own vertical sync at the next
leading edge of horizontal sync (HS).
Open drain output; this signal determines the horizontal position of disPlabed text by initiating
a horizontal retrace. Its position and pulse width are user programmable. uring hardware
and software reset, this signal is inactive high. The open drain allows the horizontal scan rate
to be synchronized to an external source. If the HS output is pulled low externally before the
CRT 9007 itself initiates a horizontal sync, the CRT 9007 will start its own horizontal sync on
the next character clock (CCLK).
Infiut; this signal defines the character rate of the screen and is used ~ the CRT 9007 for
al internal timing. A minimum high voltage of 4.3V must be maintaine for proper
chip operation.
Output: this signal is active low for one full scan line (from VLTtrailing edge to VLT trailinQ
edge) at the top scan line of each new data row. This signal can be used to swap buffers In
the double row buffer mode. It indicates the particular horizontal retrace time that the CRT
9007 outputs addresses (VA13-VAO) for single row buffer operation. There will always
be one extra DRB signal which will become active during the first scan line of the vertical
retrace interval.
Output; this signal marks the cursor position on the screen as specified by the horizontal and
vertical cursor registers. The signal is active for one character time at the particular character
position for all sc!!n lines within the data row. For double height or width characters, this signal is active for 21-- 3 SCAN LINES AFTER VS --oj

HS

CSYNC

VS----------------------~------------~------------~-----

INT~~~CED

I

CSY::
VS ______________________

~------------L_

__________________

FIGURE 3: TYPICAL SYNC WAVEFORMS FOR INTERLACED AND NON-INTERLACED MODES

~

I

I.

I
I
5 CLOCKS
.,1
I",

:

~I-----------------------I~-

~I-----------~I----

I

I

V~~

VLTl

I

1

5 CLOCKS .. ,

1
I
I
I ..

SLD

I.
5 CLOCKS

I

6CL~C~S

."

-:

SLD
FIGURE 5: SERIAL SCAN LINE TIMING: INTERLACE
OR DOUBLE HEIGHT DATA ROWS

FIGURE 4: SERIAL SCAN LINE TIMING: NON INTERLACE
OR SINGLE WIDTH CHARACTERS

351

CRT9007AlCRT9007B/CRT9007C
MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range •• • • • • • • • • • • • • • • • • . • • • • • • • • • • • • • • • • • • • • • . • • • • • • • • • • . • • • • • • • • • • • • • • •• 0° to 70°C
Storage Temperature Range ••••.••••••..•.•••••••••••••••••••.•..•••••.••••••••.••••••.••.••• _55° to + 150°C
Lead Temperature (soldering, 10 sec.) ••••••.•••••.••••••..••••••••••..••••••••••••••••••••••••••••••• + 325°C
Positive Voltage on any Pin, with respect to ground •..••.•••••.••••••••.••••••...••.•••••••••••••••••••••••• + 8V
Negative Voltage on any Pin, with respect to ground ••.•••••.••..••••••••••••••••••••••.•••••••••••••••••••• -0.3V

'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be
exceeded or device fanure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power is
switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists it is
suggested that a clamp circuit be used.
DC ELECTRICAL CHARACTERISTICS TA = O°C to + 70°C, Vcc = 5.0V ± 5%

V,L
V1H1
V1H2
VOL
VOH

PARAMETER
Input voltage
Low
High
High
Output voltage
Low
High
Input leakage current

MIN

TYP

MAX

UNITS

0.8

V
V
V

all inputs except CCLK
CCLK input; see note 4

0.4

V
V

10L = 1.6 mA
10H = 100pA

10
50
-300

pA
pA
pA

o:5 V,N :53.5V; excluding CCLK

10
25

pF
pF

all inputs except CCLK
CCLKinput

100

mA

170

2.0
4.3

2.4

ILl
IL2

COMMENTS

V,N = 5V; for CCLK
V,N = OV; for CCLK

Input capacitance
C 1N1

C'N2
Power supply current

Icc

AC ELECTRICAL CHARACTERISTICS 3 ; T. = O°C to + 70°C, Vcc = 5.0V ± 5%

lev

tCKL.

Ie'H
Ie'R
tCKF

tOl

PARAMETER
Clock:
Clock period

Clock low
Clock high
Clock rise time
Clock fall time
Output Delay ' :

MIN

TYP

290
330
400
270
300
400
90
150

to.
25
25
25

tOSL
to.
tOB
tosv

tVCH

1200
1200
1200
1200
1200
1200

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

CRT9007A
CRT9007B
CRT9007C
CRT9007A
CRT9007B
CRT9007C

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

CRT9007A/B
CRT9007C
CRT9007A/B
CRT9007C
CRT9007A/B
CRT9007C
CRT9007A/B
CRT9007C
CRT9007A measured to the 2.3V
CRT9007B or 0.5V level on
CRT9007C VAI3-VAO

150
240
150
240
150
200
150
200
100
115
125
500
185
200
185
200
185
240

t03

tvos

UNITS

15
10

t02

tVA

MAX

50
55
60
10
185
185
240
185
240

tvoo

tSLO
tSlO

352

COMMENTS
double row buffer
or attribute assemble
all other operation
modes

measured from 0.8V to 3.5V level
measured from 90% to 10% points

CRT9007A/B
CRT9007C
CRT9007A/B
CRT9007C
CRT9007A/B
CRT90Q7C
CRT9007A valid for loading auxiliary
CRT9007B address register 2 or
CRT9007C attribute latch
CL-SOpF
CRT9007A/B
CRT9007C
CRT9007A/B
CRT9007C

AC ELECTRICAL CHARACTERISTICS3 ; TA =oDe to + 70 0 e, Vee =5.0V ± 5%
PARAMETER

MIN

TYP

t07
teo

MAX
240
185
240
300
310

UNITS
ns
ns
ns
ns
ns

COMMENTS
cursor skew of zero
CRT9007A/B cursor skew of one
CRT9007C through five
CRT9007A/B
CRT9007C
CRT9007A
CRT9007B/C

140
189
85
400
410

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

115

ns

measured from the O.4V level of
ACK or TSC falling edge
measured from the O.4V level falling
edge to O.4V level rising edge
see figure 24
see figure 24

Processor Read/Write2 :
100
110
0
165
650
100
0

tAS
tAH
tpw
tCSH

tPDS
tPDH
tPDA

10

tPDO
tlRR

CRT9007A/B
CRT9007C
CRT9007AIB
CRT9007C

Miscellaneous Timing:
tATS

25

tRW

4tcy

ns

ns
50
lAKW
50
ns
lAKS
NOTE:
1. Timing measured from the 1.5V level of the rising edge of CCLK to the 2.4V (high) or 0.4V (low)
voltage level of the output unless otherwise noted.
2. Reference points are 2.4V high and O.4V low.
3. Loading on all outputs is 30 pF except where noted.
4. This level must be reached before the next falling edge of CCLK

CRT9007A1/CRT9007A2
MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ......................................................................... O°C to + 70°C
Storage Temperature Ran~e ....................................................................... -55°C to + 150°C
Lead Temperature (Soldering, 10 sec) ........................................................................ + 325°C
Positive voltage on any pin (WRT ground) •. . • . . • . • . . . • . . . • . • . . • • . . . . . • . . • . . . . . • . • . .. • • . . • • • . . .. . . . • • . . . • • . . . . • .• + 8V
Negative voltage on any pin (WRT ground) .................................................. ,.................. -0.3V

'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condnion above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be
exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power is
switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists it is
suggested that a clamp circuit be used.
DC ELECTRICAL CHARACTERISTICS TA = O°C to + 70°C, Vee = 5.0V ± 5%
SYMBOL

PARAMETER
Input voltage:
Low
High
High
Output vo~age:
Low
High
Input leakage current:

MIN

TYP

MAX

UNITS

0.8

V
V
V

0.5

V
V

1L1

10

IIA

Ie>

50
-200

IIA
IIA

VOL
VOH

' L•

2
4.3

2.4

0= < V,N = < 3.5V; excluding
CCLK
V,N = 5V; for CCLK
V,N = OV; for CCLK

Input capacitance:

C'N2

10

15

pF

25

50

pF

100

TBD

rnA

Power supply current:

Icc

10L = 1.6 rnA
10H =IOOIlA

353

All inputs except CCLK
atl MHz
CCLK input at 1 MHz

354

====:::t======----,.

VLT, WBEN

1-----,,,-----l'----i!I--1;:====1:=====..!

VA13-0

){

SL3-0
CSYNC, DMAR
CBLANK

==~~,~~==~----~~
;t
J

\
f<-----'oo---J-I - - - - -

I

------~====~,,,====~

tvDO-----~>i

t------toSy - - - - - - - l I
'l'

VD7"0

ATTRIBUTE OR

){

-41

_ _ _ _ _~-----------I~~R~O~W~T~AB~LE~D~~~A~IN~Jl~1

1-0 '''=T-,,,:::[

SLG

rC':AT=TR"'IB"'U=TE=----

_~.-~D~~~A~OU~T----

I

){

==========~::::::::~,~,,~,::::~~t======~

SLD

------i;====r",~w~=~~-----

9+ 5V

CURS

"; 3900

<;.

INT
EONlYj

---+---------/1

FIGURE 22: CRT 9007 TIMING PARAMETERS: OUTPUT SIGNALS

VA5-.

)0-----..
.. ~ To CCLK
Input

74804 or equivalent

FIGURE 25: RECOMMENDED CCLK
DRIVER CIRCUIT

--r__..,-_____-=---_
-.J

t::=t"

Jr----'-------,.

ACK, TSC
VD7-0 (WRITE)
VA13-0

VD7-0 (READ)

INT (falling edge only)

,,,'_----ll'-----• tATS IS controlled directly from ACK orTsC or from the particular CciJ<. that ends a DMA

burst cycle.

FIGURE 2: CRT 9007 PROCESSOR READ AND WRITE
. TIMING PARAMETERS

FIGURE 23: CRT 9007 MISCELLANEOUS
TIMING PARAMETERS

355

ADDRESS DECODE
Register Type

VAS

VA4

VA3

VA2

REGISTER

BIT DEFINITION

VA1

VA.

D7

D6

D4

D5

NUMBER

D.

IHEX)

LSB

AO

LSB

A1

LSB

A2

LSB

A3

LSB

A4

LSB

A5

BLANK SKEW
MSB
LSB

A6

D3

D2

D1

WAITE

0

0

0

0

0

0

MSB

CHARACTERS PER HORIZ?NTAL PERIOD

WRITE

0

0

0

0

0

1

MSB

CHARACTERS PER DATA ROW

WRITE

0

0

0

0

1

0

MSB

HORIZONTAL DELAY

WRITE

0

0

0

0

1

1

MSB

WRITE

0

0

0

1

0

0

MSB

WRITE

0

0

0

1

0

1

MSB

WRITE

0

0

0

1

1

0

PIN CONFIG-I
URAT10N

1

1

WRITE

0

0

0

1

WRITE

0

0

1

0

0

0

WAITE

0

0

1

0

0

1

HORIZONTAL SYNC WIDTH
VERTICAL SYNC WIDTH
VERTfcAL DELAY

I

CURSOR SKEW
MSB
LSB

VISIBLE DATA ROWS PER FRAME

MSB

~~~~ INES/FRA~~8)

I MSB

LSB

SCAN L NES PER DATA ROW LSB

SCAN LINES PER FRAME

IB7)

LSBIBOI

A7
A8
A9

Table 3a: CRT 9007 Screen Format Registers

ADDRESS DECODE
Register Type
WRITE

VA5

0

WRITE

0

VA4

0

VA3

1

0

1

REGISTER

BIT DEFINITION

VA1

0

1

0

VA2.

1

VA.

D7

D6

0

DMA
DISABLE

MSBA

X

PBlSSI

1

WRITE

0

.0

1

1

0

0

WRITE

0

0

1

1

0

1

D4

D5

D2

DMA BURST DELAY
Lsa

INTERLACE
MODES
TABLE START

MSB

NUMBER

IHEX)

D3

D1

D0

DMA BURST COUNT
Msa

OPERATION MODES 1

~f1XC

REGIST~A (LS BYTE)

LSB

ADDRESS 1
TABLE STAT REGISTER (MS BYTE)
MODE
MSB

Lsa

AUXILIARY ADDRESS REGISTER 1 (LS BYTE)

WAITE

0

0

1

1

1

0

Msa

WRITE

0

0

1

1

1

1

ROW )[
ATTRIBUTES

AA
Lsa
AB

AC
AD

LSB

AE

AUXILIARY ADDRESS REGISTER 1 (MS BYTE)
LSB
Msa

AF

SEQUENTIAL BREAK REGISTER 1

LSB

AlO

DATA ROW START REGISTER

LSB

A11

DATA ROW END/SEQUENTIAL BREAK REGISTER 2

Lsa

A12

AUXILIARY ADDRESS REGISTER 2 (LS BYTE)

Lsa

A13

AUXILIARY ADDRESS REGISTER 2 (MS BYTE)
MSB
LSB

A14

WRITE

0

1

0

0

0

0

MSB

WRITE

0

1

0

0

0

1

Msa

WRITE

0

1

0

0

1

0

MSB

WRITE

0

1

0

0

1

1

Msa

WRITE

0

1

0

1

0

0

ATT~'ZTES 1

Table 3b: Control and Memory Address Registers

Register Type
READ OR
WRITE
READ OR
WRITE

D4

D3

D2

D1

VA4

VA3

VA2.

VA1

VA0

1

0

1

0

1

START COMMAND

A15

0

1

0

1

1

0

RESET COMMAND

A16

0

1

0

1

1

1

0
1
0
1

1
1
1
1

1
1
1
1

0
0
0
0

0
0
0
0

0
0
1
1

0

1

0

1

1

MSa
MSa

1

1

0

1

1

0

OFFSET VALUE
LSB

VERTICAL CURSOR REGISTER (ROW COORD.)

1

1

1

0

1

1

MSa

READ

1

1

1

1

0

0

MSB

I

INTEAAUPT ENAaLE AEGISTEA
RELIGHT
TRACE PEN
X
X
X
X

.I,~~~~I

I

•

A17

LSB

R18 or R3S

LSB

A190rA39

FAAME
TIMER

A1A

I

.1

• INT
PENDRELIGHT
ING TRACE PEN

READ

I

HORIZONTAL CURSOR REGISTER (COL. COORD.)

i,~~~~1

0

D0

I

OFFSETI
OVERFLOW Msa

x

READ

D6

D5

0

WRITE

WAITE

D7

VAS

WRITE
READ
WRITE

READ

REGISTER
NUMBER
IHEXI

BIT DEFINITION

ADDRESS DECODE

STATUS AEGISTEA
-' ODD~l
EVEN

X

VERTICAL LIGHT PEN REGISTER (ROW COORD.)

FRAME
TIMER

A3A

LS.

A3a

HORIZONTAL. L.IGHT PEN REGISTER (COL. COOR?) LSB

A3C

Table 3c: Cursor, Light Pen, Offset, and Status Registers

•, ••1.1.

Circuit diagrams utilizing SMC products are Included as a means of Illustrating typical semiconductor applications, consequently complete Information sufficient for construction purposes is not necessarily given. The
Information has been carefully checked and Is believed to be entirely reliable. However, no responsibility Is
assumed for Inaccuracies. Furthermore, such Information does notconvevothe purchaserofthesemlconductor

~r~~;~i~":1~1~~:..nful:~~:~v~n1e~~~efn"Jesnj;~~~trh~f ~:fp~6~~~~r~;'~SI~~~serves the right to make changes

356

CRT 9021 A
CRT9021B

CRT Video Attributes Controller
VAC
FEATURES

PIN CONFIGURATION

o On chip video shift register
o

Maximum shift register frequency
CRT9021A 30 MHz
CRT 9021 B 28.5 MHz
On chip attributes logic
Reverse video
Character blank
Character blink
Underline
Full/half intensity

00 1
MS0 2
MS1 3
REVIO 4
CHABL 5
BLINK 6
INTIN 7
+5V 8
ATTEN 9
INTOUT 10
CURSOR 11

o Four modes of operation
Wide graphics
Thin graphics
Character mode without underline
Character mode with underline

RETBL 12
LD/SH 13

o On Chip logic for double height/double
width characters
o Accepts scan line information in paraUel

VIOEO 14

2801
2702
2603
2504
2405
23 06
22 07
21 VSYNC
20 GNO
19 SL0/SLO
18 SL1/SLG
17 SL2/BLC
16 SL3/BKC
15 VOC

PACKAGE 28-pin·0.J.P.

or serial format

o Programmable cursor blink rate
o On chip data and attribute latches
o + 5 volt operation
o TTL compatible
o MOS n-Channel silicon gate COPLAMOS® process
o Compatible with CRT 5037 VTAC®; CRT 9007 VPAC"

o Four cursor modes dynamically selectable via 2
input pins
Underline
Blinking underline
. Reverse video
Blinking reverse video

o Programmable character blink rate

GENERAL DESCRIPTION
The SMC CRT 9021 Video Attributes Controller
(VAC) is an n-chl:mnel COPLAMOS MOS/LSI device
containing Graphics logic, attributes logic, data and
attributes latches, cursor control, and a high speed
video shift register. The CRT 9021, a character generator ROM and a CRT controller such as the CRT
9007 provide all of the major circuitry for the display
portion of a CRT video terminal.
The CRT 9021 serial video output may be connected directly to a CRT monitor's video input. The
maximum video shift register frequency of 28.5 MHz
or 30 MHz allows for CRT displays of up to 132 characters per data row.
The CRT 9021 attributes include: reverse video,
underline, character blank, character blink, and full/
half intensity selection. In addition, when used in conjunction with theCRT9007VPAC;" the CRT 9021 will
provide double height or double width characters.
Four programmable cursor modes are provided on
the CRT 9021. They are: underline, blinking under357

line, reverse video character block, and blinking
reverse video character block. When used in the serial
scan line input mode, the cursor mode may be selected
via two input pins_ When used in the parallel scan line
input mode, the cursor mode is a mask program option
and is fixed at the time of manufacture.
Two graphics modes are provided. In the wide
graphics mode, the CRT 9021 produces a graphic
entity the size of the character block. The graphic entity
contains eight parts, each of which is associated with
one bit of the input byte, thereby providing 256 unique
graphic symbols. The thin graphics mode enables the
user to create thin line drawings and forms.
In both graphics modes, continuous horizontal and
vertical lines may be drawn. Additional flexibility is
provided by allowing the mask programming of the
placement and dimensions of the blocks or lines within
a character block. In the thin graphics mode, mask
programming allows serrated horizontal or vertical
lines.

07-00

017-010

L
A
T

CURSOR

RO/SLO
R1/SLG

C
H

RETBL

R2/BLC
R3/ElKC

ATTRIBUTE
AND
GRAPHIC
LOGIC

WISH

ADEN
MSO
MSI
REVIO
CHABL
BLINK
INTIN

L
A
T
C
H

1---------..

VIOEO

~--------- VOC

L
A

T
C

~--------"INTOUT

H

FIGURE 1: CRT 9021 BLOCK DIAGRAM

DESCRIPTION OF PIN FUNCTIONS
PINNa.
NAME
1, 28, 27, 26, Data
25,24,23,
22

SYMBOL
07-00

2
3

Mode Select 0
Mode Select 1

MSO
MS1

4

Reverse Video

REVID

5

Character blank

CHABL

6

Blink

BLINK

7

Intensity In

INTIN

FUNCTION
In the character mode, the data on these inputs is passed through the Attributes
logic into the 8 bit high speed video shift register. The binary information on 07
will be the first bit output after the LD/SH input goes low.
In the thin or wide graphics mode these 8 inputs will individually control the on/off
condition of the particular portion of the character block or line drawing. Figures 2
and 3 illustrate the wide and thin graphics modes respectively and their
relationships to D7-DO
These 2 inputs define the four modes of operation of the CRT 9021 as follows:
MS1, MSO = 00; Wide graphics mode
= 10; Thin graphics mode
= 01; Character mode without underline
= 11; Character mode with underline
See section entitled Display Modes for details.
When this input and Retrace Blank (RETBL) are both low, data from the
Attributes and Graphics logic is presented directly to the video shift register.
When this input is high and RETBL is low, the Attribute and Graphics logic will
invert the data before presenting it to the video shift register.
When this input is high, the parallel inputs to the video shift register are all set low
(or high depending on the state of REVID) thus providing a constant video level
for the entire length of the character block.
When this input is high and both the RETBL and CHABL inputs are low, the character will blink at the programmed character blink rate. Blinking is accomplished
by causing the video to go to the background level during the "off" portion of the
Character Blink cycle. This video level may be either the white or black level
depending on slate of REVID. The duty cycle for the character blink is 75/25 (on/
off). This input is ignored if it coincides with the CURSOR input and the cursor is
formatted to blink.
The INTIN input along with the INTOUT output provides a user controlled general
purpose attribute. Data input to INTIN will appear at INTOUT with the same delay
as that from any other attribute input to the serial video output (VID.EO). By using
an external mixing circuit, it is possible to raise or lower the voltage level of the
video output to produce such attributes as "half intensity" or "intensity".

358

DESCRIPTION OF PIN FUNCTIONS CONT'D
PINNa.
8
9

NAME
Supply Voltage
Attribute
Enable

SYMBOL
+5V
ATTEN

10

Intensity Out

11

Cursor

12

Retrace Blank

RETBL

13

Load/Shift

LD/SH

14

Video

VIDEO

15

Video Dot
Clock
Scan line
3/Block Cursor

16

INTOUT

CURSOR

VDC
SL3/BKC

17

Scan line
2/Blink Cursor

SL2/BLC

18

Scan Line
1/Scan Line
Gate

SL1/SLG

19

Scan line
O/Scan Line
data

SLO/SLD

20
21

Ground
Vertical Sync

GND
VSYNC

FUNCTION
+ 5 volt power supply
When this if"!.QYt is high, the internal attribute latch is updated at the positive going
edge of the LD/SH input with data appearing on the REVID, CHABL, MS1, MSQ),
BLINK and INTIN inputs. By selectively bringing this input high, the user will
update the attribute only at specific character times; all subsequent characters
will carry with them the attributes last updated thus allowing "field" or "embedded" attributes. When using a wide video memory where attribute bits are
attached to every character, the internal attribute latch may be updated at each
character by tieing this input high (thus allowing for "invisible" attributes) ..
This output is used in conjunction with the INTIN input to provide a three character pipeline delay to allow for general purpose attributes (such as intensity) to be
implemented. See INTIN (pin 7).
When this input is high and RETBL is low, the programmed cursor format will be
displayed. When this input is high, and RETBL is high, the CRT 9021 enters the
double width mode. See section entitled cursor formats for details.
When this input is high, the parallel inputs to the video shift register are unconditionally cleared to all zeros and loaded on the next LD/SH pulse. This forces the
VIDEO output to a low voltage level, independent of all attributes, for blanking the
CRT during horizontal and vertical retrace time.
The 8 bit video shift register parallel-in load or serial-out shift operation is established by the state of this input. When high, this input enables the shift register for
serial shifting with each video dot clock pulse (VDC input). When low, the video
shift register is parallel loaded on the next video dot clock pulse and all data and
attributes are moved to the next position in the internal pipeline. In addition, input
data and attributes are latched on the positive transition of LD/SH.
The Video output provides the serial dot stream to the CRT. Video is shifted out
on the rising edge of the video dot clock VDC. The timing of the LD/SH input will
determine the number of backfill dots. See figure 5.
This input clock controls the rate at which video is shifted out on the
VIDEO output.
This input has two separate functions depending on the way scan line inform ation is presented to the CRT 9021.
Parallel scan line mode-This input is the most significant bit of the binary scan
line row address.
Serial scan line mode-This input controls the cursor's physical dimensions. If
high the cursor will appear as a reverse video block (the entire character cell will
be displayed in reverse video). If low, the cursor will appear as an underline on
the scan line(s) programmed.
This input has two separate functions depending on the way scan line information is presented to the CRT 9021.
Parallel scan line mode-This input is the second most significant bit of the
binary scan line row address.
Serial scan line mode-This input if low, will cause the cursor to alternate
between normal and reverse video at the programmed cursor blink rate. The duty
cycle for the cursor blink is 50/50 (on/off). If this iriput is high, the cursor will be
non-blinking.
This input has two separate functions depending on the way scan line inform ation is presented to the CRT 9021.
Parallel scan line mode-This input is the next to the least significant bit of the
binary scan line row address.
Serial scan line mode-This input will be low for 5 or 6 LD/SH pulses to allow the
scan line information to be ser@!!y shifted into the serial scan line shift register. If
this signal is low for 7 or more LD/SH pulses, the CRT 9021 will assume the parallel input scan line row address mode.
This input has two separate functions depending on the way scan line inform ation is presented to the CRT 9021. Refer to figure 6.
Parallel scan line mode-This input is the least significant bit of the binary scan
line row address.
Serial scan line mode-This input will present the scan line information in serial
form (least significant bit first) to the CRT 9021 and permits the QfQper scan line
information to enter the serial scan line shift register during the LD/SH pulses
framed by SLG (pin 18).
Ground
This input is typically connected to the vertical sync output of the CRT controller
and is used as the clock input for the two on-Chip mask programmable blink rate
dividers. The cursor blink rate (50/50 duty cycle) will always be twice the character blank rate (75/25 duty cycle). In addition, the internal attributes are reset when
this input is low. The VSYNC input is also used to determine the scan line mode
(parallel or serial) used. See the section "Scan Line Input Modes".

359

ATTRIBUTES FUNCTION
Retrace Blank

-The RETBL input causes the VIDEO
to go to the zero (black) level regardless of the state of all other inputs.
-The REVID input causes inverted data
to be loaded into the video shift
register.
-The CHABL input forces the video to
go to the current background level as
defined by Reverse Video.
-MS1, MS0 = 1,1 forces the video to
go to the inverse of the background
level for the scan line(s) programmed for underline.
-The BLINK input will cause characters to blink by forcing the video to the
background level 25% of the time and
allowing the normal video for 75% of
the time. When the cursor is pro-

Reverse Video
Character Blank
Underline

Blink

grammed to blink (not controlled by
the BLINK input), the video alternates from normal to reverse video at
50% duty cycle. The cursor blink rate
always overrides the character blink
rate when they both appear at the
same character position.
Intensity
-The INTIN input and the INTOUT
(Half Intensity)
output allow an intensity (or half
intensity) attribute to be carried
through the pipeline of the CRT 9021.
An external mixer can be used to
combine VIDEO and INTOUTto create the desired video level. See figure8.
Table 1 illustrates the effect of the REVID, CHABL, UNDLN
attributes as a function of the cursor format and the CURSOR and RETBL inputs.

TABLE 1: CRT 9021 ATTRIBUTE COMBINATIONS
CURSOR
FORMAT

X

UNDERLINE'

BLINKING'
UNDERLINE'

REVIDBLOCK

BLINKING'
REVIDBLOCK

RETBL
1
0
0

CRT 9021 INPUTS
CURSOR
REVID
CHABL
X
X
X
0
0
0
0
0
0

UNDLN
X
0
1

0
0
0

0
0
0

0
1
1

1
0
0

X
0

0
0

0
1

1
0

1
0

X

x'

1

0

1

0

1

X'

0

1

1

0

X,

0

1

1

1

X,

0

1

0

0

X,

0

1

0

1

X'

0

1

1

0

X,

0

1

1

1

X,

0
0

1
1

0
0

0
0

0
1

0
0
0

1
1
1

0
1
1

1
0
0

X
0

0
0

1
1

1
0

1
0

X
0

0

1

0

0

1

0
0
0

1
1
1

0
1
1

1
0
0

X
0

1

X

0

-~,

-. 1

~: ~tt~~t~r~~~d:~as;~~~(~)~~r f~~J~;lf~~ and underline cOincide, the

1

1

VIDEO SHIFT REGISTER
LOADED WITH:
all zero's
data
One's for selected scan line(s); Data for all
other scan lines.
All zero's
data
Zero's for selected scan line(s); data for all
other scan lines.
One's for all scan lines.
One's for selected scan line(s) for cursor;
data for all other scan lines.
One's for selected scan line(s) for cursor;
zero's for all other scan lines.
Zero's for selected scan line(s) for cursor;
Data for all other scan lines.
Zero's for selected scan line(s) for cursor;
one's for all other scan lines.
__
One's for selected scan line(s) blinKing;
Data for all other scan lines.
One's for selected scan line(s) blinKing;
zero's for all other scan lines.
Zero's for selected scan line(s) blinking;
Data for all other scan lines.
Zero's for selected scan line(s) blinking;
one's for all other scan lines.
Data for all scan lines.
Zero's for selected scan line(s) for
underline; data for all other scan lines.
One's for all scan lines.
Data for all scan lines
One's for selected scan line(s) for
underline; data for all other scan lines.
Zero's for all scan lines.
Off
Qn..
Data for all scan lines.
Data for all scan lines.
One's for selected
Zero's for selected
scan line(s) for
sCanline(S~
underline; Data for
underline; ata for
all other scan lines.
all other scan lines.
One's for all scan lines. Zero's for all scan lines.
Data for all scan lines.
Data for all scan lines.
Zero's lor selected
One's lor selected
scan line(s); Data
scan line(s); Data
for all other scan lines.
for all other scan lines.
Zero's for all scan lines. One's for all scan line.s.

cursor takes precedence, otherwise both are displayed.

3· at cursor blink rate
Note-cursor blink rate overrides character blink rate.

360

DISPLAY MODES
Inputs MS1 and MSQ) select one of four display modes. All
attributes except underline operate independent of the
display mode used. Figures 8a and 8b illustrate a typical
CRT 9021 configuration which operates in all display modes
for both the parallel and serial scan line modes respectively.
MS1. MSO = 00 -Wide Graphics Mode.
MS1,MSO = 01
In this display mode, inputs 07-00
define a graphics entity as illustrated
in figure 2. Note that individual bits in
07-00 will illuminate particular
portions of the character block. Table
2 shows all programming ranges
possible when defining the wide
graphic boundaries. No underline is
possible in this display mode.
MS1, MSO = 10 -Thin Graphics Mode.
In this display mode, inputs 07-00 MS1,MSO = 11
define a graphic entity as illustrated
in figure 3. Note that individual bits in
07-00 will illuminate particular horizontal or vertical line segments within
SL3-SLO ROW #
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

C7 C6 CS C4 C3 C2 C1 CO BF BF

0

0

the character block. Table 3 shows
all programming ranges possible
when defining the thin graphics
boundaries. No underline is possible in this display mode.
-Character Mode Without Underline ..
In this display mode, inputs 07-00 go
directly from the input latch to the
video shift register via the Attributes
and Graphics logic. This mode
requires either a bit mapped system
RAM (1 bit in RAM equals 1 pixalon
the CRT) or an external character
generator as shown in figures 8a and
8b.
-Character Mode With Underline.
Sarne operation as MS1, MSQ) = 01
with the underline attribute appearing on the scan line(s) mask programmed.

0

i

RO
R1
R2
R3
R4
RS
R6
R7
RS
R9
R10
R11
R12
R13
R14
R1S

07

I
I H3
I I

03

-- .JI
06

I

I

02

H2

-- 1: II
OS

I

01

H1

I

II

-"1

I
04

00

I

I
I
I

HO

I

I

I
W1

I

-.J

WO

I

I

10710610sI041031021011001 OATA INPUT ON 07-00
H3, H2, H1, HO, W1, WO are mask programmable

FIGURE 2: WIDE GRAPHICS MODE FOR STANDARD CRT 9021
SL3-SLO ROW #
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

RO
R1
R2
R3
R4
RS
R6
R7
RS
R9
R10
R11
R12
R13
R14
R1S

C7 C6 CS C4 C3 C2 C1 CO BF BF

-,

04
07

0

___ J

00
02

06
03

I
I
I
I
I

0

VERTICAL HEIGHT

0

00
01
06
07

I

I
I

-I
---~

I

-

-

PROGRAMMABLE
PROGRAMMABLE
PROGRAMMABLE
PROGRAMMABLE

J

I

OS

RO-RS
R6-R1S
RO-R1S*
RO-R1S*

--l

I
I

01

HORIZONTAL POSITION

I
I
__ J

HORIZONTAL LENGTH
02
03
04
OS

VERTICAL POSITION
PROGRAMMABLE
PROGRAMMABLE
PROGRAMMABLE
PROGRAMMABLE

C7-C3
C3-BF
C7-BF*
C7-BF*

10710610sI04103102101100 1

OATA INPUT ON 07-00

* These values are fixed

FIGURE 3: THIN GRAPHICS MODE FOR STANDARD CRT 9021
361

BACKFILL
Backfill is a mechanism that allows a character width of
greater than 8 dots and provides dot information (usually
blanks) for all dot positions beyond 8. The character width
is defined by the period of the LD/SH input. For the character
modes, backfill is added to the tail end of the character by
two methods which are mask programmable.
Method A
- The backfill (BF) dots will be the same
as the dot displayed in position C7.

Method B

-

The backfill (BF) dots will be the same
as the dot displayed in position CO.

For the wide graphics mode, the backfill dots will always be
the same as the dot displayed in position CO (method B)
with no programmable option.

CURSOR FORMATS
Four cursor formats are possible with the CRT 9021. If the
parallel scan line input mode is used, one of four cursor formats may be selected as a mask programmed option. If the
serial scan line input mode is used, the cursor format is
selected via input pins 16 and 17 (SL3/BKC, SL2/BLC). See
Table S. The four cursor modes are as follows:
Underline

Blinking Underline

Reverse Video
Block

-

-

-

The cursor will appear as an
underline. The position and width
of the cursor underline is mask
programmed.
The cursor will appear as an
underline. The underline will alternate between normal and reverse
video at the mask programmed
cursor blink rate.
The cursor will appear as a reverse
video block (The entire character

Blinking Reverse
Video Block

Scan Line
Input Mode
Serial
Parallel

-

cell will be displayed in reverse
video).
The cursor will appear as a reverse
video block and the entire block
(character plus background) will
alternate between normal and
reverse video at the masked programmed cursor blink rate.

Pin 17
1
1
0
0

Pin 16
0
1
0
1

X

X

Cursor Function
Underline
Reverse Video Block
Blinking Underline
Blinking Reverse
Video Block
Mask programmable
Only

TABLE 5: CURSOR FORMATS

DOUBLE WIDTH MODE
In order to display double width characters, video must be
shifted out at half frequency and the video shift register must
receive new information (parallel load) every other LD/SH
input pulse. In order to divide the video dot clock (VDC) and
the LD/SH pulse internally at the proper time, the cursor input
should be pulsed during RETBL prior to the scan line to be
displayed as double width. The CURSOR input must remain
low for a minimum of 1 LD/SH period from the leading edge
of RETBL. The CURSOR input can stay high for the entire
RETBL time but should not extend into active video. If it does,
a cursor will be displayed. It is assumed that the CRT con-

troller knows when a particular scan line should be double
width and it should activate the CURSOR in the manner just
described. Double height/double width characters can also
be displayed if the scan line count is incremented by the
CRT controller every other scan line. With respect to the
CRT 9021, no distinction between double width and double
height display is necessary. Figure 4 illustrated timing for
both single and double width modes. The CRT 9007, which
supports double height double width characters, will produce the CURSOR signal as required by the CRT 9021 with
no additional hardware.

SCAN LINE INPUT MODES
Scan line information can be introduced into the CRT 9021
in parallel format or serial format. Table 6 illustrates the pin
definition as a function of the scan line input mode. The CRT
9021 will automatically recognjze the proper scan line mode
by observing the activity on· pin 18. In parallel mode, this
input will be stable for at least 1 scan line and in serial mode
this input will remain low for about S'or 6 LD/SH periods. If
pin 18 goes active low for less than seven but more than
two continuous LD/SH periods during the last scan line that
has an active low on the VSYNC input, the serial mode will
be locked in for the next field. The parallel scan line input

mode will be selected for the next field if the following two
conditions occur during VSYNC low time. First, at least one
positive transition must occur o.!!..Q.in 18 and second, pin 18
must be low for seven or more LD/SH periods. Refer to figure 7 for timing details.
Scan Line
Input Mode
Serial
Parallel

1-9
SLD
SLO

CRT 9021 Pin Number
18
17
16
BLC
BKC
SLG
SL1
SL2
SL3

TABLE 6: PIN DEFINITION FOR PARALLEL AND SERIAL SCAN LINE MODES

PROGRAM OPTIONS
The CRT 9021 has a variety of mask programmed options. trates the range of the miscellaneous mask programmed
Tables 2 and 3 illustrate the range of these options for the options. In addition, Tables 2, 3 and 4 show the mask prowide and thin graphics modes respectively. Table 4 illus- grammed options for the standard CRT 9021.
362

LD/SH
1

RETBL

~

07-00
(NORMAL)
WIDTH
07-00
(DOUBLE)
WIDTH
017-010
(NORMAL)
WIDTH
017-010
(DOUBLE)
WIDTH

~I

1

VIDEO
(NORMAL)
WIDTH

~~+--+--~~--~~--~

1
1

X

CHAR N

1
I

1

X

CHARN/2X

X

I

I

:

X

CHAR (N-1)

X

1
I

1
1

I '
I
I

1
1

I
I

1

I

X

CHAR 3

I

I

r--~
""'-----I

I

i ,i i i

:

X

X

- - - CHAR
--l"
- - -.....
N/2

,

X

CHAR 0

I

1
I

VIDEO (N-2)(~

1
,

~

X

1

---~

CHAR 1

.

~
.

1

BLANKING
I

r'

ATTRIBUTE IN'
( DOUBLE)
WIDTH
ATTRIBUTE OUT'
( DOUBLE)
WIDTH

X

_ _ _-;1

VIDEO
( DOUBLE) VIDEO (N/2-1)
WIDTH
ATTRIBUTE IN'
( NORMAL)
WIDTH
ATTRIBUTE OUT'
( NORMAL)
WIDTH

X

,
I

VIDEO N/2

,

BLANKING

". _ _...,--_ _..J
i-

X

X

X

INT(N-2)

X

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-",

X
I
,

,

,

I

,

I
,

~

-----------------

X

X

,

X

X

1 - Attributes include MSO, MSI, BLINK, CHABL, INTENSITY, REVID

FIGURE 4: CRT 9021 FUNCTIONAL 1/0 TIMING

I

ATT (\

1

Xr--ATT.'. -1--,[

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ........................................................................ O°C to + 70°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to + 150°C
Lead Temperature (soldering, 10sec.) ............... , ................................................... , ... +325°C
Positive Voltage on any Pin, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .15V
Negative Voltage on any Pin, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists it is
suggested that a clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA = QOG to 7QoG, Vee
PARAMETER
DC CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low Level V'L
Low Level V'L
High Level V,HI
High Level V,H,
OUTPUT VOLTAGE LEVELS
Low Level VOL
High Level VOH
INPUT LEAKAGE CURRENT
Leakage ILl
Leakage IL'
INPUT CAPACITANCE
C'N1
C 'N2
CIN3
POWER SUPPLY CURRENT
Icc

MIN

TYP

= 5V

± 5%, unless otherwise noted)

MAX

UNIT

0.8
0.65

V
V
V
V

All inputs except VDC, LD/SH
For VDC, LD/SH inputs_
All inputs except VDC, LD/SH
For VDC, LD/SH input

0.4

V
V

10L=0.4mA
10H= 1OOfloA

10
50

floA
floA

O""V,N

~

)

ALLINPUT~

(EXCEPT VDC, LD/S H)

\

tCY2

VDC

VIDEO OR
INTOUT

RETBL

CURSOR
(FOR DOUBLE WIDTH)

FIGURE 5: CRT 9021 INPUT/OUTPUT TIMING

WISH

X

SLD _ _ _ _..I'-_J'-_I'---"'--J'---I'~....t,NOT USED BY CRT 9021

FIGURE 6: SERIAL SCAN LINE MODE TIMING

WISH

LnnrlJlJlJ1nnnJ1f
,
'

,
I

I

:

~:I-I_ _ _--Hit~~\!
I

SL1/SLG

l~

I

n

L' __ '-_T"-~
,

!

,

,

I

!

/

•

1

!

I

I

I~
•

STABLE,. 7 WISH

I

SET SERIAL
SCAN LINE MODE

FIGURE 7: SERIAL/PARALLEL SCAN LINE MODE SELECTION TIMING

365

.r-

~'
I

,

SET PARALLEL
SCAN LINE MODE

TABLE 2

WIDE GRAPHICS MASK PROGRAMMING OPTIONS
OPTION

CHOICES

Height of graphic block'
07 and 03
06 and 02
05 and 01
04 and 00
Width of 07,06,05,04"
Width of 03,02,01,00"

any scan
any scan
any scan
any scan

line(s)
line(s)
line(s)
line(s)

any number of dots 0 to 8
any number of dots 0 to 8

STANOARO CRT 9021
RO, R1, R2
R3, R4, R5
R6, R7, R8
R9,R10,R11,R12,R13,R14,R15
C7, C6, C5, C4
C3, C2, C1, CO, BF

, Any graphic block pair can be removed by programming for zero scan lines.
"Total number of dots for both must be equal to the total dots per character with no overlap.

TABLE 3
THIN GRAPHICS MASK PROGRAMMING OPTIONS
OPTION
Backfill
Horizontal position for
02 and 03
04
05

CHOICES

STANOARO CRT 9021

C1 or CO

CO

any scan line(s) RO-R15
any scan line(s) RO-R15
any scan line(s) RO-R15

R5
RO
R11

Horizontal length for
C7-C3
C3-BF

any continuous dots C7-CO, BF
02'
all dots not covered by 02
03'
Blanked dots for serrated horizontal lines
02
03
04 and 05

any dot(s) C7-CO, BF
any dot(s) C7-CO, BF
any dot(s) C7-CO, BF

none
none
none

any dot(s) C7-CO, BF
any dot(s) C6-CO, BF
any dot(s) C7-CO

C3
BF
C7

Vertical position for
00 and 01
06'
07'
Vertical length for
00
01
06
07

RO
R6
RO
RO

any scan line(s)
all scan lines not used by 00
no choice; always RO-R15
no choice; always RO-R15
1-07 must always come before 06 with no overlap; otherwise 06 is lost.
2-02 and 03 must always overlap by one and only one dot.

to
to
to
to

R5
R15
R15
R15

TABLE 4

MISCELLANEOUS MASK PROGRAMMING OPTIONS
CHOICES
C70rCO

STANOARD CRT 9021

Backfill in character mode

OPTION
Character blink rate
(division of VSYNC frequency)

8 to 60; divisible by 4
(7.5 Hz to 1 Hz)'

32
(1.875 Hz)'
16
(3.75 Hz)'
R11

Cursor blink rate'
character underline pOSition
cursor underline'
cursor format'
1234-

Twice the character
blink rate
any scan line(s) RO-R15
any scan line(s) RO-R15
underline
Blinking underline
Reverse video block
Blinking reverse video block

Assumes VSYNC input frequency of 60 Hz.
Valid only if the cursor is formatted to blink.
Valid only if the cursor is formatted for underline.
Valid for the parallel scan line mode only.

366

C7

not applicable
Blinking reverse video block

-"
11

THREE
STATE
DRIVER
OE P-

r-

r

---"

L t-A
T
C t--

/j

"

OR

w
~

SINGLE ROW
BUFFER
OR

FROM
CRT
CONTROLLER

CHARACTER
ROM

I-

~ ........
,/

SL3-SLO

L

~-

VSYNC
RETBL
CURSOR

07-00

CRT 9021
VAC

---1\..

SYSTEM RAM

I

OE

~

SL3-SLO

VSYNC
RETBL
CURSOR
MSO
.... MSI

DOUBLE ROW
BUFFER

BLINK
.... CHABL
INTIN
REVID
ATTEN

I

J
~GENERATOR
CLOCK

1

LD/SH
VDC

FIGURE 8a: CRT 9021 SYSTEM CONFIGURATION IN PARALLEL
SCAN LINE MODE

,-VIDEO
INTOUT

r-

M
[

X
E

-

R
~

VIDEO
TO MONITOR

,--

~

~

...---

....

~
v

OE

P+

OE

f-

CHARACTER
ROM

'CK
7

4
3
7
8
r"D

SYSTEM RAM
OR
(..)

m

CD

SINGLE ROW
BUFFER
OR
DOUBLE ROW
BUFFER

TO
w

::;; ::l

~5~

IL

VSYNC
RETBL

()

CURSOR

v

-"

07-00

"

'\/

CRT 9021
VAC

"

t

SLG
SLO
VSYNC
RETBL
CURSOR

SLD

is

r-

-

L
A
T
C r--H

Vi

THREE
STATE
DRIVER

I

I

I

CLOCK
GENERATOR

I

VIDEO
INTOUT

MSO
MSI
BLINK
CHABL
INTIN
REVIO
ATTEN
LO/SH
VOC
BKC

i ---.J
FORMAT

1

FIGURE 8b: CRT 9021 SYSTEM CONFIGURATION IN
SERIAL SCAN LINE MODE

BLC

J

VIOEO
TO MONITOR

CRT 9028
CRT 9128

VTLC
Video Terminal Logic Controller
PIN CONFIGURATION

FEATURES

D Built-in High Frequency (4-14 MHz) Oscillator
D Built-in Video Shift Register
D Built-in Character Generator
D Bi-Directional Smooth Scroll Capability
D Visual Attributes Include Reverse Video, Intensity

DA8,
DA9:
DA10
GND
XTAL2
XTAL1
VIDEO
INTOUT
DWR
000
001
002.
003
DD4
005
006
007
HSYNC
VSYNC
CSYN

Control, Underline and Character Blank

D Separate HSYNC, VSYNC and VIDEO Outputs
D Composite Sync (RS170 Compatible) Output
D Absolute (RAM address) Cursor Addressing
D MASK Programmable Video Parameters:
Dots Per Character Block (6-8)
Raster Scans Per Data Row (8-12)
Characters Per Data Row (32, 48, 64, 80)
Data Rows Per Page (8,10,12,16,20,24 or 25)
Horizontal Blanking (8-64Characters)
Horizontal Sync Front Porch (0-7 Characters)
Horizontal Sync Duration (1-64 Characters)
Horizontal Sync Polarity
Two Values of Vertical Blanking
Two Values of Vertical Sync Front Porch (0-63 Scan
Lines)
Two Values of Vertical Sync Duration (1-16 Scan
Lines)
Vertical Sync Polarity
Internal 128 Character 5x8 Dot Font
Character/Cursor Underline Position
Scan Rowand Column for Thin Graphics Entity
Segments
Scan Rows and Columns for Wide Graphics Entity
Elements
D Software Enabled Non-Scrolling 25th Data Row Available with 25 Data Row/Page Display
D Non-Interlace Display Format
D Separate Display Memory Bus Eliminates Contention

1
2
3
4
5
6
7

'-'

8
10
90
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

P DA7
P DA6
P DA5
P DA4
P DA3
PDA2
DA1
DAO
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
AID

....

VCC

CRT 9028

CRT 9128

Pin 23 RD
Pln22 WR

Pin 23 OS
Pln22 R/W

Problems

D Fill (Erase) Screen Capability
D Standard 8-bit Data Bus Microprocessor Interface
D Wide Graphics with Six Independently Addressable
Segments Per Character Space

D Thin Graphics with Four Independently Addressable
Segments Per Character Space

D Single + 5V Supply
D COPLAMOS® n-Channel Silicon ~ate Technology
D TTL Compatible

GENERAL DESCRIPTION
similar microprocessors or microcomputers. The CRT 9128
regulates the data flow with a data strobe (DS) and read/
write (R/W) enable signals for use with the 6500, Z8'", 68000
and similar microprocessors or microcomputers.

The CRT 9028 VTLC and CRT 9128 VTLC are mask programmable 40 pin COPLAMOS® n-channel MOS/LSI Video
Display Controller Chips that combine video timing, video
attributes, alphanumeric and graphics generation, smooth
scroll and screen buffer interface functions.

The VTLC provides two independent data buses; one bus
that interfaces to the processor and one that interfaces to
the display memory. Data is transferred to the display memory from the processor through the VTLC eliminating contention problems and the need for a separate row buffer.

The VTLC incorporates many of the features (previously
requiring a number of external components) required in
building a low cost yet versatile display interface. An internal mask programmable 128 character font provides for a
full ASCII character set. Wide graphics allow plotting and
graphing capabilities while thin graphics and visual attributes can make the display of forms straight-forward.

The VTLC has an internal crystal oscillator requiring only
an external crystal to operate. Masked constants for critical
video timing simplify programming, operation and improve
reliability. A separate non-scrolling status line (enabled or
disabled by the processor) is available for displaying system status.

Two pinout configurations enhance the versatility of the
VTLC. The CRT 9028 controls data flow over the processor
system data bus through separate read (RD) and write (WR)
strobes for use with the 8085, 8051, Z80®, 8086, and
'Z80 is a regislered Irademark of Zilog Corporation.
Z8 is a trademark of Zilog Corporation.

369

XTALl

XTAL2
CHARACTER
CLOCK

om

CLOCK

TO
D\SPLAY
MEMORY

-+5V
-

GND

FIGURE 1. VTLC FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

I/O

3-1,40-33

DA10-0

0

4

GND

5,6

XTAL2,1

I

7

VIDEO

8

NAME

DESCRIPTION

Display
Address

11 bit address bus to display memory

Ground

Ground Connection

Crystal 2,1

External Crystal
An external TTL level clock may be used to drive XTAL 1 (in
which case XTAL2 is left floating).

0

Video Output

This output is a digital TTL waveform used to develop the
VIDEO and composite VIDEO signals to the monitor. The
polarity of this signal is: HIGH = BLACK
LOW = WHITE

INTOUT

0

Intensity
Output

This pin is the intenSity level modification attribute bit (synchronized with the video data output).

9

DWR

0

Display
Write

Write strobe to display memory

17-10

DD7-0

I/O

Display
Data

8-bit bidirectional data bus to display memory

18

HSYNC

0

Horizontal
Sync

Horizontal sync signal to monitor

19

VSYNC

0

Vertical
Sync

Vertical sync signal to monitor

20

CSYNC

0

Composite
Sync

This output is used to generate an RS170 compatible composite VIDEO signal for output to a composite VIDEO monitor.

21

Voo

5.0 V power connection

Power

CRT 9028
22

WR

I

Write Strobe

Causes data on the microprocessor data bus to be strobed into
theVTLC

23

RD

I

Read Strobe

Causes data from the VTLC to be strobed onto the miCroprocessor data bus

22

R/W

I

Read/Write
Select

Determines whether the processor is reading data from or writing data into the VTLC (high for read, low for write)

23

DS

I

Data Strobe

Causes data to be strobed into or out of the VTLC from the
microprocessor data bus depending on the state of the R/W
signal

24

A/D

I

Register
Select

The state of this input pin will determine whether the data is
being read from, or written to, the address or status register, or
a data register.

32-25

DB7-0

I/O

Processor
Data Bus

a-bit bi-directional processor data bus

CRT 9128

370

DESCRIPTION OF OPERATION
THE VTLC INTERNAL REGISTERS

CHARACTER register. This bit is used to synchronize data
transfers between the processor and the VTLC. The VTLC
will set the DONE bit to a logic one after completing a byte
transfer command or a FILL operation. The DONE bit is set
to a logic zero by reading from, or writing to, the CHARACTER register. The processor must wait until the DONE
bit is 1 before attempting to change the CURSOR
ADDRESS, in order to write a character to, or read a character from, the CHARACTER register.

CRT 9028
Addressing of the internal VTLC data registers of th~
CRT 9028 is accomplished Jt!!'ough~ use of the AID
select input qualified by the RD and WR strobes.
AID RD WR

o
o

1

0

o
1

o
o

REGISTER OPERATION
WRITE TO DATA REGISTER
READ DATA REGISTER
WRITE TO ADDRESS REGISTER
READ STATUS REGISTER

STATUS REGISTER
DB7

0
0

0
0
0
0

0
1
0

DB6 DB5 DB4 DB3 DB2 DB1 DBO

x

DONE

CRT 9128
Addressing of the internal VTLC data re~ters of!b.e CRT
9128 is accomplished through use of the AID and RIW select
inputs qualified by the DS strobe.

AID DS R/Vii

*

X

X

REGISTER OPERATION

To access one of the seven eight-bit registers, the processor must first load the Address Register with the threebit address of the selected data register. The next read or
write to a data register will then cause the data register.
pointed to by the Address Register to be accessed. The Line
AID controls whether writing is occurring to the Address
Register orlo a data register. When a read operation is performed, AID controls access to either the Status Register
or to the data register selected by the Address Register.

REGISTER DESCRIPTION
ADDRESS REGISTER

Writing a byte to the ADDRESS register will select the
specified register the next time the processor writes to or
reads the VTLC data registers. The data register addresses
are as follows:

FILADD REGISTER
X

ADDRESS

DA10 DA9 DA8 DA7 DA6 DA5 DA4

TYPE

REGISTER

Write
Write
Write
Write
Write
Write
RDIWR
Write

CHIP RESET
TOSADD
CURLO
CURHI
FILADD
ATTDAT
CHARACTER
MODE REGISTER

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO

X
X
X
X
X
X
X
X

0
1
1
1
1
1
1
1

1
0
0
0
0
1
1
1

1
0
0
1
1
0
0
1

0
0
1
0
1
0
1
0

(X = don't care)
'NOTE: Chip Reset is required before starting operation.

X

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO

STATUS REGISTER
When reading the STATUS register, the DONE bit (DB7
of STATUS Register) will represent the current status of the

X
X
X
X
X
X
X
X

X.

DATA REGISTERS
FILADD (Fill Address) This register contains the RAM
address of the character following the last
addr~ss to be filled. Writing to this register will
enable the VTLC "fill" circuitry. The FILL operation will then be triggered by the next processor
write to the CHARACTER register. The FILL
operation will write the character in the CHARACTER register to every location in display
memory starting with the address specified in
the CURLO and CURHI registers through the
location preceeding the address specified in the
FILADD register. The cursor position is not
changed after a FILL operation. Note that the
address bits DA3-DAO are internally forced to 0
forcing the FILADD address to be 00, 16, 32, etc.
to 1920. The CURLO and CURHI registers will
not be changed .by this operation. Writing to the
CHARACTER register will cause the VTLC to
reset DB7 of the STATUS register to "0". Bit 7
will be set to 1 after the VTLC has filled the last
memory location specified.

The contents of the seven processor programmable registers located in the upper left hand side of the Functional
Block Diagram of figure 1 indicate the memory locations
from which screen data is to be fetched and displayed as
well as the selected modes of display operation. These registers are addressed indirectly via the Address Register.

X
X
X
X
X
X
X
X

X

DONE = 1 signifies that external processor is allowed to
access cursor ADDRESS andlor
CHARACTER registers.
DONE = 0 signifies that external processor must wait
until VTLC completes transfer of data
between display memory and CHARACTER
register.

WRITE TO DATA REGISTER
READ DATA REGISTER
WRITE TO ADDRESS REGISTER
READ STATUS REGISTER

X
X
X
X
X
X
X
X

X

371

Changing the Attribute register will change the
attribute of every "tagged" character on the
screen. The functions of the remaining bits in the
ATTDAT register are not affected by the display
character's TAG bit.

TOSADD (Top of Screen Address) This register contains
the RAM address of the first character displayed
at the top of the video monitor screen. In addition, this register controls selection of either of
two mask programmable vertical scan rates.
TOSADD REGISTER
DB? DBS DB5 DB4 DB3 DB2 DB1 DBO
TIM DA10 DA9 DA8 DA? DAS DA5 DA4
Note that address bits DA3-DAO are internally
forced to 0 forcing the first address at the beginning of each row to be 00, 1S, 32, etc. to 1920.
The most significant bit of this register (TIM)
is used to select between the two mask programmed sets of vertical retrace parameters
(scan A and scan B). This allows software
selection of, for example, 50/S0 HZ.
TIM
TIM
CURLO

=
=

0 enable raster scan A (SO Hz)
1 enable raster scan B (50 Hz)

(Cursor Low) This register contains the eight
lower order address bits of the RAM cursor
address. All FILL screen and character transfer
operations begin at the memory location pointed
to by this address.

There are two display modes, "alphanumerics" and
"graphics". In the alphanumeric mode, visual attributes may
be selected by the TAG bit. In the graphics mode, a tagged
character will be a normal alphanumeric character. This
allows a screen to display a mix of graphic and alphanumeric characters or visually attributed alphanumeric characters. The display variations of the alphanumerics and
graphics modes are summarized by the following:
ATTDAT REGISTER
DB? DBS DB5 DB4 DB3 DB2 DB1 DBO
DB?

MODE
SELECT

DB? = 1
DB? = 0

DBS

CURSOR
SUPPRESS

DBS

=

1

CURLO REGISTER
DB? DBS DB5 DB4 DB3 DB2 DB1 DBO
DA? DAS DA5 DA4 DA3 DA2 DA 1 DAO
CURHI

(Cursor High) This register contains the three
higher address bits of the RAM cursor address
(DA 10, DA9, DA8). All FILL screen and character transfer operations begin at the memory
location pointed to by this address. In addition,
this register contains the Smooth Scroll Offset
Values SS3-SS0 which determine the number
of scan lines that the data is shifted on the
screen. The MSB of this register (SLE-status line
enable) is the enableforthe non-scrolling status
line (this feature is available only on a part programmed for 25 data rows).

DBS = 0

DB5

CURSOR
DISPLAY

DB5 = 1
DB5

=

0

DB4

=

1

CURHI REGISTER
DB? DBS DB5 DB4 DB3 DB2 DB 1 DBO
SLE SS3 SS2 SS1 SSO DA10 DA9 DA8
SLE

1 enables non-scrolling 25th
status line
SLE = 0 disables and blanks nonscrolling status line
=

SS3-SS0 Smooth Scroll Offset Value
ATTDAT

(Attribute Data) This register specifies the visual attributes of the video data and the cursor
presentation. The visual attributes specified in
the ATTDAT register (DB3-DBO) are enabled or
disabled by a TAG bit that is appended to the
ASCII character written to the CHARACTER
register. Every character on the screen with its
TAG bit set is displayed with the same attribute.
372

DB4

SCREEN

DB4 = 0

enables graphics
mode display (No
attributes allowed)
enables alpha
mode display
inhibits VIDEO display at cursor time
by forcing the
VIDEO output to
background level
during cursor displaytime
enables VIDEO
display at cursor
time
Note: a blinking
cursor display can
be achieved by
toggling this bit
under processor
control.
enables underline
cursor display
enables block cursordisplay
Note: An underline
cursor in an underline character
attribute field will
be dashed.
for white screen
and black
characters
for black screen
and white
characters
Note: this is a
screen attribute
(versus character
attribute) bit and
sets the default
Video background
level.

DB3

CHARACTER DB3
SUPPRESS
DB3

=1
=0

t-

iD
C!)

~

iIi
0

DB2

INTENSITY

DB2 = 1

W

....J

III

«en

0

DB2

=0

UNDERLINE DB1

=1

a:
0
0

register. The VTLC takes that characte~
and stores it in the display memory in the
location specified by the CURLO and
CURHI registers. In Byte Transfer Read
Mode, the processor reads this register
causing the VTLC to fetch the character
whose address is specified in the CURLO
and CURHI registers from the display
memory and place it in the CHARACTER
register. The processor then reads the
character and initiates another fetch from
memory cycle. In FILL mode, writing a byte
to this register will initiate a FILL operation.
All VTLC/memory data transfers take place
during horizontal and vertical video retrace
blank time.

to enable Video
suppress
to inhibit Video
suppress
This bit allows
character blinking
and blanking under
processor control
allows the INTOUT
output pin to go
high for the charactertime
inhibits the
INTOUT output pin
from going high

W

....J

III

«

DB1

Z

w
DB1 = 0

DBO

REVERSE
VIDEO

DBO = 1

DBO = 0

MODE

will cause the characterto be
underlined
will inhibit the
underline
will cause the
standard foreground and background Video
levels (selected
with DB4) to be
reversed for the
character time
will inhibit reverse
video

This mode allows an intermix of alpha-numeric and
graphics characters. No attributes are permitted in this
mode. If TAG BIT = 1, the character will be an alphanumeric. If TAG BIT = 0, the character will be a graphics character.
CHARACTER REGISTER
ALPHANUMERIC: TAG BIT = 1
DB?

DB6 DB5 DB4 DB3 DB2 DB1 DBO

x

X

X

X

X

X

DB6

TAG = 1

X

DB5

DB4

DB3

DB2

DB1

DBO

I- ALPHA-NUMERIC CHARACTER...-!

DB6-DBO Specify character
CHARACTER REGISTER

DB? AUTO
DB?
1 to enable
INCREMENT automatic character
address
The RAM address is
incremented after the
VTLC completes a display memory access
initiated by a processor
to RAM or RAM to
processor
character
transfer.

GRAPHICS: TAG BIT = 0
DB?

DB6 DB5

DB4

DB3

DB2

DB1

DBO

TAG=O WIT SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
DB6

WIT = 1 specifies a wide graphics
character
WIT = 0 specifies a thin graphics
character

WIDE GRAPHICS ONLY:
DB5-4 SEG6-5 = 1 to turn on graphics
entity segment
SEG6-5 = 0 to turn off graphics
entity segment

DB? = 0 to disable
automatic increment
CHARACTER

CHARACTER SET

A. (MODE SEL = 1) GRAPHICS MODE

MODE REGISTER
DB?

TAG BIT +? BIT ASCII CHARACTER

Using the DB?-DBO data bus 1/0 pins and the MOD SEL
bit in the ATTDAT register, the user can address 128 characters, a six segment "wide graphics" and a four segment
"thin graphics" entity. Included in the 128 mask programmable characters can be the 96 standard ASCII characters
and 32 special characters.

The AUTO INCREMENT bit in this register
specifies whether or not the display memory
character address is automatically incremented by the VTLC after every readlwrite of
the CHARACTER register. Note: The visible
cursor position is not affected.

AUTO
INC

CHARACTER REGISTER
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO

This register allows access to the display
memory for both byte transfers and FILL
operations. In BYTE Transfer Write Mode,
the processor first writes a character to this

Note that DB5 and DB4 have no meaning in the
thin graphics entity.

373

the DD?-DDO data bus as shown in the Display Memory
Timing of figure 2. Because the system data bus is isolated
from the display data bus, the VTLC maintains complete
control over access to display memory. All data flow between
display RAM and the processor or the VTLC takes place
through the VTLC. Refer to the VTLC Display Memory
Access Timing of figure?

WIDE AND THIN GRAPHICS:
DB3-0 SEG4-1 if any bit = 1, corresponding
graphics entity segment ON
It any bit = 0, corresponding
graphics entity segment OFF

DISPLAY MEMORY ACCESS
B. (MOD SEL = 0) ALPHA-NUMERICS MODE
This mode allows display of alpha-numeric characters
with attributes. If DB? is set to a logical one, the attribute(s) specified in the ATTDAT register will be enabled for that character. If TAG BIT is cleared, attributes
will not be enabled for that character.
CHARACTER REGISTER
DB?
TAG

DB6

DB5

DB4

DB3

DB2

DB1

DBO

'-ALPHA-NUMERIC CHARACTER--l
DB? = 1 to enable attribute(s) for character.
DB? = 0 to disable attribute(s) for character.

DB6-DBO Specify character

SEGMENT
6

SEGMENT
3

SEGMENT
5

SEGMENT
2

SEGMENT
4

SEGMENT
1

Processor/display memory access is accomplished
through the CHARACTER register of the VTLC. All processor transfers to or from the CHARACTER register take place
only when the DONE bit is high. The DONE bit is used to
synchronize data transfers between the VTLC and the processor as shown in the Typical Processor To Display Memory Transfer of figure 6. When the processor needs to store
a byte of data in the display memory, it will write the byte to
the CHARACTER register of the VTLC. The VTLC will
immediately reset the DONE bit indicating that the transfer
hardware is busy. At the next blanked Video time, the VTLC
will store the byte in the dis:)lay memory, increment the
character address, (if auto increment is enabled) and set
the DONE bit. When the processor needs to read a byte of
data from the display memory, it will read the CHARACTER
register. The VTLC will fetch the desired byte from the display memory during the next blanked VIDEO time, increment the character address (if enabled), and set the DONE
bit. When the processor detects that the DONE bit is set, it
will read the CHARACTER register to getthe data byte from
the VTLC. This read will reset the DONE bit and cause the
VTLC to fetch the next byte of data from the memory.

If auto increment is not enabled, the processor must set
the cursor address in the CURLOand CURHI registerlothe
address of the memory location being read from, or written
into, before every access to the CHARACTER register.
It should be noted that Auto Increment does not affect the
visible cursor location. If auto-increment is enabled, the
current character location will equal the cursor position only
for the first character transfered following an update of the
CURLO and CURHI registers. Note that the DONE bit must
be high before attempting to update the cursor registers
because the loading of the cursor registers will reset the
character position counters to the cursor position.

WIDE GRAPHICS ENTITY
NOTE: scan line and column of segment
locations are mask programmable.

SEGMENT 3

SMOOTH SCROLL
SEGMENT 4

The VTLC may be programmed to do either "jump" or
"smooth" scrolling. Jump scrolling moves the data up or
down the monitor screen one data row at a time. Smooth
scrolling moves the data up the monitor screen one scan
line at a time. The number of scan lines and the rate they
move up the screen is under processor control.

SEGMENT 2
SEGMENT 1

THIN GRAPHICS ENTITY

Smooth scroll is controlled through manipulation of the
SS3-SS0 bits of the CURHI register. These bits represent
the binary address of the first scan line of the first data row
displayed on the monitor screen (the data row whose
beginning address is in the TOSADD register). When the
value represented by these bits is incremented, the video
data on the monitor screen moves up by the same number
of scan lines. After the address of the last scan line of the
data row is loaded into the CURHI register and the VIDEO
data has moved up the last scan line of the data row, the
processor resets the SS3-SS0 address to point to scan line

NOTE: scan line and column of segment
locations are mask programmable.

DESCRIPTION OF SYSTEM OPERATION
The VTLC circuitry provides two control functions. One
function interprets and controls data from the system processor interface through the data bus DB?-DBO as shown
in the Processor Timing of figure 3. The other function generates and refreshes the video image on the screen through
3?4

o and does a jump scroll. Jump scroll is accomplished by

will remain stationary at the bottom of the screen and will
not move up the screen when the remainder of the display
data is scrolled, Otherwise, VIDEO data on the status line
may be manipulated as though it were normal display data,
The smooth scroll offset will not function properly when the
status line is enabled, The memory address of the characters on the status line are always characters 1920-1999,
NOTE: If the part is programmed for 25 data rows an additional mask option must be specified which makes the 25th
data row either fixed (always displayed) or a status row
(enabled/disabled by the SLE bit),

incrementing the RAM address in the TOSADD register by
a data row length (so that it points to the address of the first
character of the new top data row on the monitor),
When programmed for a data row of 80 characters/data
row display (1920 data words), for example, the display RAM
contains 25 actual rows of data (2000 RAM locations), If the
smooth scroll offset equals zero, the VTLC will display the
1919 RAM locations following the top of screen address
when displaying data, The first data row is partially scrolled
off the screen and the 25th data row is scrolled onto the
screen when the smooth scroll offset is incremented, The
VTLC will now display the 1999 RAM locations following the
top of screen address (wrapping to 0 after address 1999),
After the VTLC does a jump scroll, the processor will program it to erase the line just scrolled off the screen (preparing it to be scrolled onto the screen), This line now becomes
the non-displayed 25th data row.

CHIP RESET
The CRT 9028 and CRT 9128 Chip Reset requires two
steps, The system processor first writes the reset address
to the address register of the VTLC, The system processor
then writes a dummy character to the VTLC Data register,
Writing to the Data register resets the chip, The only state
affected by the reset function is the setting of the DONE bit
in the STATUS register,

NON-SCROLLING STATUS LINE
The non-scrolling status line is only functional on a VTLC
that has been programmed for 25 data rows, This data row

ROM CHARACTER BLOCK FORMAT
COLUMN DOT

->

C7

C6

C5

C4

C3

C2

C1

co

SCAN LINE 0

->

0

o

o

o

o

o

o

SCAN LINE 1

->

0

o
o

SCAN LlNE2

->

0

SCAN LINE 3

->

0

SCAN LlNE4

->

0

SCAN LINE 5

->

0

o
o
o

MASK PROGRAMMABLE
CHARACTER BLOCK
(FONT)
5X8

SCAN LINE 6

->

0

SCAN LINE 7

->

0

SCAN LINE 8

->

0

SCAN LINE 9

->

0

->

0

o
o

o

SCAN LINE 10

o

o
o

SCAN LINE 11

->

0

o

o

o

o

o
o

o
o
o
o
o
o
o
o

o

o
o

0

o
o
0
0

0
0

o
o
o

Mask programmable options-The ROM character block format above shows the 5X8 mask programmable character font
within the character cell as defined by dots C7 through CO and scan lines 0 through 11
Dots/Character: 6 dots/character cell
7 dots/character cell
8 dots/character cell

~
~
~

> C7 - C2 displayed

> C7 - C1 displayed
> C7 - CO displayed

Column dots CO and C1 will be the same as column dot C7 when more than 6 dots/character cell are specified
when generating alpha-numerics,
NOTE: The maximum dot clock crystal frequency IS dependent on the dots.'character programmed:
DOTS/CHARACTER

MAX XTAL FREQ

6 dots
7 dots
8 dots

10.5 MHz max'
12.25 MHz max'
14.0 MHz max'

*These values are preliminary

Scan Lines per Character:

8 scan
9 scan
10 scan
11 scan
12 scan

lines/character ~ > SLO - SL7 displayed
lines/character ~ > SLO - SL8 displayed
lines. character ~ > SLO SL9 displayed
lines 'character ~ > SLO - SL 10 displayed
lines character ~ > SLO - SL 11 displayed

Thin and Wide GraphiCS: Dots mask programmed for vertical column C2 will be the same as backfill Columns 0 and 1
when generating wide and thin graphics.

375

I

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range .......................................................................O°C to + 70°C
Storage Temperature Range ......................................................................... - 55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ............................................................... + 325°C
Positive Voltage on any Pin, with respect to ground ................................................. + B.OV
Negative Voltage on any Pin, with respect to ground ................................................ - 0.3V
·Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches"
on their outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may
appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
ELECTRICAL CHARACTERISTICS (TA =O°C to 70°C, Vee =
PARAMETER

+ 5V ± 5%, unless otherwise noted.)
MIN

TYP

MAX

UNIT

O.B

V
V

0.4

V

0.4

V

COMMENTS

DC CHARACTERISTICS

INPUT VOLTAGE LEVELS
Low-level, Vii
High-Level, Vih
OUTPUT VOLTAGE LEVELS
Low-level, Vol

2.2

Low-level, Vol
High-level, Voh

2.4

V

High-level, Voh

2.4

V

INPUT LEAKAGE CURRENT
High-level, IIh
Low-level, III

All outputs except
VIDEO, CSYNC,
INTOUT, HSYNC,
VSYNC; 101 = 1.6 rnA
VIDEO, CSYNC,
INTOUT, HSYNC,
VSYNC; 101 = 0.4 rnA
All outputs except
VIDEO, CSYNC,
INTOUT, HSYNC,
VSYNC;loh =
- 40 p.A
VIDEO, CSYNC,
INTOUT, HSYNC,
VSYNC;loh =
. -20 !LA

10

!LA

All inputs; Yin

-10

!LA

All inputs
except~R,

Low-level, III
INPUT CAPACITANCE
All inputs, Cin
OUTPUT LOAD
CL
CL
POWER SUPPLY CURRENT
Icc

-200

!LA

15

pF

15
100

pF
pF

125

rnA

AC CHARACTERISTICS

CLOCK FREQUENCY, fin
DISPLAY MEMORY TIMING
Address Set-up Time
tAS
Write Strobe Set-up Time
tWST
Data Set-up Time
tST
Data Hold Time
tOH

1.0

MHz

20

ns

BO

ns

BO

ns

10
376

14.0

25

ns

= Vcc

RD,
OS, RIW; Yin = .04V
WR,RD,
OS, R!W; Yin = 0.4V

Except DB7-0
DB7-0

PARAMETER
Address Hold Time

MIN

tAHT

TYP

MAX

UNIT

25

ns

15

ns

COMMENTS

Output Hold From Address Change
tOH

Address Access Time
250

tM

ns

PROCESSOR TIMING
Address Read/Write Set-up
t ARWS

160

ns

160

ns

15

ns

Write Pulse Width
t wpw

Write Hold Time
tWHT

Read Set-up Time
200

tRST

ns

Read Data Valid

0

ns

250

ns

120

ns

160

ns

TRov '
Read Pulse Width
t RPw

Data Write Falling Set-up
t OWFS

Data Write Rising Set-up
t OWRS

Crystal specification (Applies for 4-14 MHz):
Series Resonant
50 ohms max series resistance
1.5 pf typ parallel capacitance
Operation below 4 MHz requires external crystal oscillator

OAt 0-0

ADDRESS

ADDRESS

DWR

READ DATA
FRDMRAM

DD7-DDO

READ DATA
FROM RAM

VTLC INPUT
FROM RAM
NOTE: DISPLAY ADDRESS BUS DAtO-DAO MUST NOT CHANGE WHILE DWR IS LOW

FIGURE 2. DISPLAY MEMORY TIMING

:=r

~,---'------==-X'----_-_><=

r-~-t_-,--;-;-----:-----J

ir--------.I
00, RD, WR

DB7-0
PROCESSOR WRITES
TOVTLC

(1) If set-up time is not met, screen may glitch when cursor or attribute
registers are changed during active video time.
(2) Minimum set-up time to ensure valid data into VTLC internal registers.

FIGURE 3. PROCESSOR TIMING
377

VERTICAL

VERTICAL TIMING

SYNC
I DURATION I

I

I.

01

I

I
I

I

I+-

VSYNC_
DELAY
I
VSYNC _ _ _ _

I

I

-;I_...Jr--\'-_---+I___-tI/-I_ _ _--...J1

I
1/
I
'II
-----~I+- NUMBER OF BLANKED -.I~----t7r - I
I
SCAN LINES
I*-- ~Y;~~~'?t ~
I
I

V BLANKING

I

r---

/

DATA ROWS

HORIZONTAL

HORIZONTAL TIMING

SYNC

DURATION

~

HSYNC _
DELAY

HSYNC

I

~

I

I

I

I

I

I
I
I

-------'I--'r--\}------7I----II~/----.J1
I
I
I

//

H BLANKING _ _ _ _ _..J/,--------......,

I+-----

NUMBER OF

cJ}~~f'?RS

r---

II

/r - I

---.!
I+-

~Y;~~~,?t - t
CHARACTERS

NOTE: Video parameters above are mask programmable

FIGURE 4. VERTICAL AND HORIZONTAL SYNC TIMING

n

HSYNC~

n

I
I

I
--I-

VSYNC

I
I
I
I

I

I

H---j

I---H/2--1

I

n'---__IL

n

n

I
I

I
I

I

I
I
I

I

I

I
I
I

I
I

CSYNC

~HCJ~~~~::~r: ~~~~ft~:iv~1ges and pulse width values may vary due to mask programmable features.

HSYNC

HSYNC

______~Il~_____
______~~d~r---------

CSYNC
CSYNC

U

d = HSYN Delay -CSYN Delay
WITHIN VERTICAL SYNC
PULSE TIME

OUTSIDE OF VERTICAL
SYNC PULSE TIME

FIGURE 5. VIDEO SIGNAL TIMING

r-00 7-O XXXXXXXXX

ASCII CHARACTER

PROCESSOR
BUS

~-----------------......

xxxxxxxxxxxxxxxx

PROCESSOR WRITES CHARACTER

VTLC CHARACTER REGISTER
(CAUSES DONE BIT RESET)
·DONE
(DB7 OF STATUS
REGISTER)

r-D

DI~~~AY

DISPLAY
D7-O
CHARACTER
_ _ _.J \. _ _
_ _ _ _J

DISPLAY
ASCII CHARACTER
CHARACTER
\. _ _ _ _ _...J ' -_
_ _ _ _- ' \._ _ _ _ _ _ _---'

~WR-----------------------------~
DONE = 1 SIGNIFIES THAT PROCESSOR MAY ACCESS CHARACTER REGISTER
DONE = 0 SIGNIFIES THAT PROCESSOR MAY NOT ACCESS CHARACTER REGISTER

VTLCWRITES
CHARACTER REGISTER
TO DISPLAY MEMORY

FIGURE 6. TYPICAL PROCESSOR TO DISPLAY MEMORY TRANSFER

378

~----

TYPICAL DISPLAY TIMING
TIME:
OA10-0

OWR

..Ill

DISPLAY MEMORY READ

READ AND WRITE DISPLAY MEMORY TIMING
TIME:
OA10-0

'"

OWR

PROCESSOR WRITES/READS TO /FROM
CHARACTER REGISTER

-.J

c---\

(OB7 OF STATUS
REGISTER)

., I,.

,---,,-,,--=.'=-"...,-1 J.:.

co

~ ___ ___ j

I

---,- -

HIGH FOR READ
LOW FOR WRITE

VTLC WRITES/READS
TO/FROM DISPLAY MEMORY

DONE
W

H

~I

!iI

,

B:ANKING

PROCESSOR WRITES/READS TO/FROM
CHARACTER REGISTER

-I ~ I,.

LL

77

1/
CHARACTER

DI~P~AY

--I h

-.I

007-0

FILL DISPLAY MEMORY COMMAND
TIME:
OA10-0

.---H

OWR
PROCESSOR WRITES TO FILADD REGISTER
FOLLOWED BY WRITE TO CHARACTER REGISTER

(
DONE
(OB7 OF STATUS
REGISTER)

~

~

007-0

NOTE:

ON CHARACTERS/DATA ROW

FIGURE 7. VTLC DISPLAY MEMORY ACCESS TIMING

(LAST LOCATION

.H
FILLED)
~TO
LAST LOCATION

11!
~11--~

APPENDIX-STANDARD PARTS-CRT 9028-000/CRT 9128-000
I. ROM CHARACTER BLOCK FORMAT:
->

C7

C6

C5

C4

C3

C2

C1

a

->

a

a

a

a

a

SCAN LINE 1

->

SCAN LINE 2

->

SCAN LINE 3

->

SCAN LINE 4

->

SCAN LINE 5

->

SCAN LINE 6

->

SCAN LINE 7

->

SCAN LINE 8

->

SCAN LINE 9

->

a
a
a
a
a
a
a
a
a
a

a
a
a
a
a
a
a
a
a
a

COLUMN DOT
SCAN LINE

II.

CHARACTER BLOCK
5 X8 CELL

a

a

DOTS PER CHARACTER:
DOT CLOCK XTAL FREQUENCY (MHz):
HORIZONTAL TIMING (IN CHARACTER TIMES):
CHARACTERS PER DATA ROW:
HORIZONTAL BLANKING:
HORIZONTAL SYNC DELAY:
HORIZONTAL SYNC PULSE WIDTH:
HORIZONTAL SYNC POLARITY:

a

a

a
7
10.92

80
20
4
8
NEGATIVE ACTIVE

10.--- HORIZ BLANKING-----.l
I
.I

VIDEO

ACTIVE VIDEO
---------1

ACTIVE VIDEO

1
...._ _ _ _ _ _ _-_

HSYNC
HORIZ SYNC DELAY

III.

IV.

-I.. .1..

HORIZ SYNC--.!
PULSE WIDTH

VERTICAL TIMING:
CHARACTER ROWS:
SCAN LINES PER CHARACTER:
TOTAL VISIBLE SCAN LINES:
VERTICAL SYNC POLARITY:

24
x10
240
NEGATIVE ACTIVE

VERTICAL SYNC TIMING (IN SCAN LINES):
60 Hz VERTICAL BLANKING:
60 Hz VERTICAL SYNC DELAY:
60 Hz VERTICAL SYNC PULSE WIDTH:
ALTERNATE (50 Hz) VERTICAL BLANKING:
ALTERNATE (50 Hz) VERTICAL SYNC DELAY:
ALTERNATE (50 Hz) VERTICAL SYNC PULSE WIDTH:
ACTIVE VIDEO

r--

20
4
8
72
30
10

VERTICAL BLANKING-1

ACTIVE VIDEO
1
...._ _
- _ _ _-_ _ _-_

VIDEO

--------1

VSYNC

--~V~S~Y~N~C~D1EE~LAAYy:::~I·;:~·~14..-VERTSYNC~
PULSE WIDTH

380

V.

COMPOSITE SYNC OUTPUT (IN CHARACTER TIMES):

2

COMPOSITE SYNC DELAY:
COMPOSITE SYNC PULSE WIDTH:

8

ACTIVE VIDEO

VIDEO

ACTIVE VIDEO

--------1

1--------

CSYN

CSYN DELAY -

f4'---;....rliool...'---~~

...

VI.

UNDERLINE ATTRIBUTE AND CURSOR LINE:

VII.

WIDE GRAPHICS FIGURE DEFINITION:
COLUMN

->

C6

C7

C5

CSYN PULSE WIDTH

SCAN LINE 9

C4

C3

C2

C1

SCAN LINE 0 ->
SCAN LINE 1 ->

SEGMENT 6

SEGMENT 3

SEGMENT 5

SEGMENT 2

SEGMENT 4

SEGMENT 1

SCAN LINE 2 ->
SCAN LINE 3 ->
SCAN LINE 4 ->
SCAN LINE 5 ->
SCAN LINE 6 ->
SCAN LINE 7 ->
SCAN LINE 8 ->
SCAN LINE 9 ->

VIII. THIN GRAPHICS FIGURE DEFINITION:
COLUMN DOT ->

C7

C6

C5

SCAN LlNEO ->

C4

-

SCAN LlNE3 ->

S
E
G
M
E
N
T

SCAN LlNE4 ->

3

SCAN LINE 1 ->
SCAN LINE 2 ->

SCAN LINE 5 ->
SCAN LINE 6 ->
SCAN LlNE7 ->
SCAN LINE 8 ->
SCAN LINE 9 ->

l

SEGMENT 4

C3

C2

C1

SEGMENT 2
S
E
G
M
E
N
T
1

-

SEGMENT 4 = SCAN LINE 5; C7, C6, C5, C4
SEGMENT 3 = C4; SCAN LINES 0, 1,2, 3, 4, 5
SEGMENT 2 = SCAN LINE 5; C4, C3, C2, C1
SEGMENT 1 = C4; SCAN LINES 5, 6, 7, 8, 9

381

1

KEYBOARD
CONN

;~fD~

OPTIONAL
SERIAL
EEROM

XTAL 1 XTAL2

P2 .3

INTO

CS
SK

P2.2

P2.1
P2.0

~INT1

LS249'
VSYNC PH•..-.-----I

01

HSYNCb----+---I

I P2.5

I~

INTOUTI

)I DB7-DOO

8051
OR
EQUIVALENT

~
I\)

TO MONITOR

I~

VIDEO 10

K.

~ }

HORIZONTAL SYNC

DO

COMM
CONN

PO.7 -PO.O

,VERTICAL SYNC

DWRbP~------1

CRT 9028

WE
DISPLAY MEMORY·

ADDRESS BUS

PRINTER 1488
I I
CONN
~

I

'0--l-----oI P1.5

:t

~ A1.E1'-A9

2K X 8
STATIC RAM

£~
CRT 9028
TYPICAL APPLICATION

K.

DATA BUS

~ 07-09'

KEYBOARD
CONN

n

II

0

OPTIONAL
SERIAL
EEROM

I I

-

II I

COMM
CONN

n~~"
(,)

-

tcv2

VDC
VIDEOOR
HINTO
BOLDa
GP10
GP20

RETBL

CURSOR
(FOR DOUBLE WIDTH)

FIGURE 2: CRT 9041 INPUT/OUTPUT TIMING

FIGURE 3: SERIAL SCAN LINE MODE TIMING

LD SH

lnflrlr1rlJ1nnnJ1f
~,t-l-----+--_--J!~(~~--l.\ i
! \;I

VSYNC

I

I

I

SLISLG

!h
\

;/- - T
!«

- T - ~I

n

t.

t1--\
\

I

STABLE LOW;;. 7 WISH

n-----Y,

SET SERIAL
SCAN LINE MODE

FIGURE 4: SERIAl/PARALLEL SCAN LINE MODE SELECTION TIMING
395

;; - - -

t

SET PARALLEL
SCAN LINE MODE

LDISH

~

011-00
(NORMAL)
WIDTH
011-00
(DOUBLE)
WIDTH
0111-010
(NORMAL)
WIDTH
0111-010
(DOUBLE)
WIDTH

~
,,

CHARN X

X

X

_ _ _---\'

X

X

,

I

I

I

I

I

I
r-----'\

X

X

II

I

,

I

,

I

,

,

I

I

t

I

:

I

I

I

X

,

I

CHAR3

I

i i I

:

X

X

- - -CHAR
- - - 'N/2
---i
•

,

~

X

I

CHAR 0

I

I

I
I

X

CHAR 1

.

~

.

,

BLANKING

VIDEO
( DOUBLE) VIDEO (N/2-1)
WIDTH
"
ATTRIBUTE IN'
( NORMAL)
WIDTH

L _ _: - - _ - J

('

X

X

X

INT(N-2)

X

_____________________________

ATTRIBUTE IN'
( DOUBLE)
WIDTH
ATTRIBUTE OUT'
( DOUBLE)
WIDTH

,

,

CHARNI2X

- - - - - I .:

,

~~~~

X

VIDEO
(NORMAL)
WIDTH

ATTRIBUTE OUT'
( NORMAL)
WIDTH

:,
,

_ _ _ _....'"

~

~I

I
I

'

RETBL

,

r-----7-----~~----~------~'

X
,

,
I

,

,

,

,
,

-----------------------~~
-----------------------------------------------~l,
X
X
X
A

1-Attributes include MSO, MSI, BLINK, CHABL, HINT, BOLO, REVIO and XCURS

FIGURE 5: CRT 9041 FUNCTIONAL 1/0 TIMING

ATH)

:Xr-----~:------~
ATT 1
'(

PROGRAM OPTIONS
The CRT 9041 has a variety of mask programmed options. Tables 8 and 9 illustrate the range of these options for the wide
and thin graphics modes respectively. Table 10 illustrates the range of the miscellaneous other mask programmed options.
In addition, Tables 8, 9 and 10 show the mask programmed options for the CRT 9041-004.

TABLE 8: WIDE GRAPHICS
MASK PROGRAMMING OPTIONS

OPTION

CRT 9041-004

CHOICES

Height of Graphic
block*
011 AND 07
010 AND 06
09 AND 05
08 AND 04

any
any
any
any

line(s)
line(s)
line(s)
line(s)

RO,R1,R2
R3,R4
R5,R6
R7 thru R15

Width of graphic
block**
011,010,09,08

any consecutive
dots
C11 thru CO

C11 thru C7

all remaining dots
not specified above

C6 thru CO
plus SF

07,06,05,04

scan
scan
scan
scan

•Any graphic block pair can be removed by programming for zero scan
lines.
"Total number of dots for both must be equal to the total dots per character with no overlap. 011.010.09 and 08 must always be to the left
of 07-04.

WIDE GRAPHICS
SL3-SLO ROW# C11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

RO
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

CO

SF

SF ...

T
011

07

010

06

09

05

08

04

I-~--w1-------o·o{+~----WO--------I·1
HO. H1. H2. H3. WOo W1. are mask programmable.
The values shown are for the CRT 9041-004.

397

H3

+H2

+

t

I

TABLE 9: THIN GRAPHICS
MASK PROGRAMMING OPTIONS

OPTION

STANDARD CRT 9041-004

CHOICES

Backfill

Horizontal position for
D6andD7
D8
D9
Horizontal length for
D6(1)
D7(1)

any dot(s) within the programmed D7 range to the right
of the programmed column(s)
forDll.

CO

any scan line(s) RO-R15
any scan line(s) RO-R15
any scan line(s) RO-R15

R5
RO
R9

any consecutive dots
all dots not covered by D6 with
one dot overlapping.
Blanked dots for serrated horizontal lines
D6
any dot(s), BF programmed
D7
any dot(s), BF programmed
D8,D9
any dot(s), BF programmed

Vertical position for:
D4andD5
Dl0(2)
Dl1 (2)

any dot(s) Cll-CO,BF
any dot(s) Cl O-CO,BF
any dot(s) Cll-CO

Vertical length for:
D4
D5
Dl0
Dll

any scan line(s)
any scan lines not in D4
no choice; always RO thru R15
no choice; always RO thru R15

Cll thruC7
C7thru BF
none
none
none
C7
C3
Cll
ROthru R5
R6thru R15
ROthru R15
ROthru R15

(1) 06 and 07 must always overlap by 1 dot. This overlap may be blanked by specifying the proper column(s) in the serration
program line. 07 must always be to the right of 06.
(2) 011 must always come before 010 with no overlap: otherwise 010 is lost.

THIN GRAPHICS

SL3-SLO ROW# Cl1

Cl0

C9 C8

C7

C6

C5

C4

C3

C2

Cl

co

BF

BF.
VERTICAL HEIGHT

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

RO
Rl
R2
R3
R4
R5
R6
R7
R8
R9
RIO
Rll
R12
R13
R14
R15

08
011

04

010

06

I

--.J
---1

07

I

05

___ I
_..J

09

-

==~I

~

04
05
010
Dll

RO-R5
R6-R15
RO-RI5
RO-RIS'
HORIZONTAL LENGTH

06
07
08
09

C11-C7
C7-BF
Cll-BF'
C11-BF'

-

The height of 04 and 05. the length of 06 AND 07. and the position of
04-011 are mask programmable. The values shown are for the CRT 9041-004.
"These values are fixed

398

HORIZONTAL POSITION
PROGRAMMABLE
PROGRAMMABLE
PROGRAMMABLE
PROGRAMMABLE
VERTICAL POSITION
PROGRAMMABLE
PROGRAMMABLE
PROGRAMMABLE
PROGRAMMABLE

TABLE 10: MISCELLANEOUS MASK PROGRAMMING OPTIONS
OPTION

"STANDARD" CRT 9041-004

CHOICES

Backfill in character mode

C11 or CO

C11

Character blink rate
(division of VSYNC frequency)

7.5 Hz to 0.5 Hz (1) (1)

1.25Hz (1)

Cursor blink rate (2)

same as, half, or twice the character blink rate

2.50 Hz (1)

Character blink duty cycle

50/50 or 75/25

50/50

Cursor blink duty cycle

50/50 or 75/25

50/50

Character underline 1 position

any scan line(s) RO thru R15

RS

Character underline 2 position

any scan line(s) RO thru R15

R10

Cursor underline position

any scan line(s) RO thru R15

R9

Extra cursor underline position

any scan line(s) RO thru R15

R11

Cursor format (3)

underline
blinking underline
reverse video block
blinking reverse video block

blinking reverse
video block

Extra cursor format (3)

underline
blinking underline
reverse video block
blinking reverse video block

blinking
underline

Blink table

Table 1
Table 2
Table 3

Table 3

CURSOR or XCURSOR effect on
BOLDa and HINTO

no effect or force to zero at cursor
position

force to zero at cursor position.

(1) Assumes VSYNC input frequency of 60 HZ.
(2) Valid only if the cursor is formatted to blink.
(3) Valid for the parallel scan line mode only.

1~~f~~

Y~l
r--

I:'

L '-A
T

cH

OEf.,J

-'\

SYSTEM RAM
OR
SINGLE ROW
BUFFER

F~-r

Sl3-SLO

VSYNC
AETBL

VSYNC
RETBL
CURSOR

CURSOR

OR

CRT 9041

VIC

1$

CONTROLLER

7D11-DO.DST

CHARACTER
ROM

VIDEO
HINTO
BOLDO

MSO
MSI

DOUBLE ROW
BUFFER

~
IX

ER

BLINK
CHABL
HINTI

BOLDI
RS
XCURSIGPll
UL21GP21
REVID

ADEN
[DISH
VDC

I
CLOCK RJ
GENERATOR

FIGURE 6a: CRT 9041 SYSTEM CONFIGURATION IN
PARALLEL SCAN LINE MODE
399

r+GP10
r + GP2O

VIDEO
TO MONITOR

-"
y

.-l
A

.

T

C
H

y

1

--.J2fP+

-

-

L..J...,

7
4
7

7

..

01'-00.0ST

~

-"
CRT 9041

y

VAC

r"D

OR
SINGLE ROW
BUFFER

OOUBLEROW
BUFFER

fo~

CHARACTER
ROM

CK
3

OR

DE

y

8

SYSTEM RAM

r--

THREE
STATE I - DRIVER

u..

r

t

w

::l
~§@
~

~

U

-

SlG
SlD
VSYNC
RETBl
CURSOR

SLD

VSYNC

RETBL
CURSOR

I

VIDEO
HINTO
BOLDO

MSO
MSI
BLINK
CHABl
HINTI
BOLDI
RS
XCURS/GPll
UL2/GP21
REVIO
ATTEN
WISH
VOC

I
CLOCK
GENERATOR

I

BKC

P~g~~~~~6~
FORMAT

~

VIDEO
TO MONITOR

r-- GPIO
r-- GP2O
BlC

Il..--l

I

FIGURE 6b: CRT 9041 SYSTEM CONFIGURATION IN
SERIAL SCAN LINE MODE

STANDARD MICROSVSTEMS

CORPORATION

35 Marws9l'ld ,Hauppauge, t.iY 11788

(5161273·3100 TWX·51Q·227·8898

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The

information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

400

CRT 9053
CRT 9153

EVTLC
Enhanced Video Terminal Logic Controller
FEATURES

PIN CONFIGURATION

D Built-in High Frequency (4-18.7 MHz) Oscillator
D Built-in Video Shift Register
D Built-in Character Generator (128 Characters,

DA8
DA9
DA1D
GND
XTAL2
XTALl
VIDEO
INTOUT
DWR
DDD
DDl
DD2
DD3
DD4
DD5
DD6
DD7
HSYNC
VSYNC
CSYN

7x11 Dot Font)

D Bi-Directional Smooth Scroll Capability
D Visual Attributes Include Reverse Video, Intensity
Control, Underline, and Character Blank and Blink
D Separate HSYNC, VSYNC and VIDEO Outputs
D Composite Sync (RS170 Compatible) Output
D Absolute (RAM address) Cursor Addressing
D MASK Programmable Video Parameters:
Dots Per Character Block (8-9)
Raster Scans Per Data Row (11-13)
Characters Per Data Row (32,48,64,80)
Data Rows Per Page (8,10,12,16,20,24 or 25)
Horizontal Blanking (8-64 Characters)
Horizontal Sync Front Porch (0-7 Characters)
Horizontal Sync Duration (1-64 Characters)
Horizontal Sync Polarity
Two Values of Vertical Blanking
Two Values of Vertical Sync Front Porch (0-63 Scan
Lines)
Two Values of Vertical Sync Duration (1-16 Scan
Lines)
Vertical Sync Polarity
Internal 128 Character 7x11 Dot Font
Character/Cursor Underline Position
Character/Cursor Blink Rate
Scan Rowand Column for Thin Graphics Entity
Segments
Scan Rows and Columns for Wide Graphics Entity
Elements
D Software Enabled Non-Scrolling 25th Data Row Available with 25 Data Row/Page Display
D Non-Interlace Display Format

1
2
3
4

'-'

7
8

[
[
[
(

10
90
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

P

DA7
DA6
DA5
DA4
DA3
DA2
DAl
DAD
DB7
DB6
DB5
DB4
DB3
DB2
DBl
DBD
AID

....

VCC

CRT 9053

CRT9153

Pin23
Pin22

Pin 23
Pin 22

RO
WR

os
RIW

D Embedded Attribute or Tag Bit Attribute Capability
D Separate Display Memory Bus Eliminates Contention
Problems

D Fill (Erase) Screen Capability
D Standard 8-bit Data Bus Microprocessor Interface
D Wide Graphics with Six Independently Addressable
Segments Per Character Space

D Thin Graphics with Four Independently Addressable
Segments Per Character Space

D Single + 5V Supply
D COPLAMOS® n-Channel Silicon Gate Technology
D TTL Compatible

GENERAL DESCRIPTION
(WR) strobes for use with the 8085,8051, Z80®, 8086, and
similar microprocessors or microoomputers. The CRT 9153
regulate.§.,the data flow with a data strobe (DS) and read/
write (R/W) enable signals for use with the 6500, Z8'", 68000
and similar microprocessors or microcomputers.
The EVTLC provides two independent data buses; one
bus that interfaces to the processor and one that interfaces
to the display memory. Data is transferred to the display
memory from the processor through the EVTLC eliminating
contention problems and the need for a separate row buffer.

The CRT 9053 EVTLC and CRT 9153 EVTLC are mask
programmable 4o-pin COPLAMOS® n-channel MOS/LSI
Video Display Controller Chips that combine video timing,
video attributes, alphanumeric and graphics generation,
smooth scroll and screen buffer interface functions.
The EVTLC incorporates many of the features (previously requiring a number of external components) required
in building il- low cost yet versatile display interface. An
internal mask programmable 128 character font provides
for a full ASCII character set. Wide graphics allow plotting
and graphing capabilities while thin graphics and visual
, attributes can make the display of forms straight-forward.

The EVTLC has an internal crystal oscillator requiring only
an external crystal to operate. Masked constants for critical
video timing simplify programming, operation and improve
reliability. A separate non-scrolling status line (enabled or
disabled by the processor) is available for displaying system status.

Two pinout configurations enhance the versatility of the
EVTLC. The CRT 9053 controls data flow over the processor system data bus through separate read (RD) and write
'ZSO is a registered trademark of Zilog Corporation.
is is a trademark of Zilog Corporation.

401

XTAL1

XTAL2

CHARACTER
CLOCK

DOT
CLOCK

TO
DISPLAY
MEMORY

CfH9053

CRT9153

All

-.5V
- GND

FIGURE 1. EVTLC FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

1/0

3-1,40-33

DA10-0

0

NAME

DESCRIPTION

Display
Address

11 bit address bus to display memory

Ground

Ground Connection

Crystal 2,1

External Crystal
An external TTL level clock may be used to drive XTAL 1 (in
which case XTAL2 is left floating).

4

GND

5,6

XTAL2,1

I

7

VIDEO

0

Video Output

This output is a digital TTL waveform used to develop the
VIDEO and composite VIDEO signals to the monitor. The
polarity of this signal is: HIGH = BLACK
LOW = WHITE

8

INTOUT

0

Intensity
Output

This pin is the intensity level modification attribute bit (synchronized with the video data output).

9

DWR

0

Display
Write

Write strobe to display memory

17-10

DD7-0

1/0

Display
Data

a-bit bidirectional data bus to display memory

18

HSYNC

0

Horizontal
Sync

Horizontal sync signal to monitor

19

VSYNC

0

Vertical
Sync

Vertical sync signal to monitor

20

CSYNC

0

Composite
Sync

This output is used to generate an RS170 compatible composite VIDEO signal for output to a composite VIDEO monitor.

21

V~

Power

5.0 V power connection
CRT 9053

22

WR

I

Write Strobe

Causes data on the microprocessor data bus to b~ strobed into
the EVTLC

23

RD

I

Read Strobe

Causes data from the EVTLC to be strobed onto the microprocessor data bus

22

R/W

I

Read/Write
Select

Determines whether the processor is reading data from or writing data into the EVTLC (high for read, low for write)

23

DS

I

Data Strobe

Causes data to be strobed into or out of the EVTLC from the
microprocessor data bus depending on the state of the R/W
signal

24

AID

I

Register
Select

The state of this input pin will determine whether the data is
being read from, or written to, the address or status register, or
a data register.

32-25

DB7-0

1/0

Processor
Data Bus

8-bit bi-directional processor data bus

CRT9153

402

DESCRIPTION OF OPERATION
THE EVTLC INTERNAL REGISTERS

bit is set to a logic zero by reading from, or writing to, the
CHARACTER register. The processor must wait until the
DONE bit is 1 before attempting to change the CURSOR
ADDRESS, in order to write a. character to, or read a character from, the CHARACTER register.

CRT 9053
Addressing of the internal EVTLC data registers of the
CRT 9053 is accomplished thr~h the use of the AID select
input qualified by the RD and WR strobes.

AID RD WR
o 1 o

o

STATUS REGISTER

REGISTER OPERATION
WRITE TO DATA REGISTER
READ DATA REGISTER
WRITE TO ADDRESS REGISTER
READ STATUS REGISTER

o
o
o

o

o

0
0

o

o
o

o

The contents of the eight processor programmable registers located in the upper left hand side of the Functional
Block Diagram of figure 1 indicate the memory locations
from which screen data is to be fetched and displayed as
well as the selected modes of display operation. These registers are addressed indirectly via the Address Register.
To access one of the eight eight-bit registers, the processor must first load the Address Register with the threebit address of the selected data register. The next read or
write to a data register will then cause the data register
po.!!lted to by the Address Register to be accessed. The Line
AID controls whether writing is occurring to the Address
Register orlo a data register. When a read operation is performed, AID controls access to either the Status Register
or to the data register selected by the Address Register.

REGISTER DESCRIPTION

TYPE

X

X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X

X

(X - don t care)

X
X
X
X
X
X
X
X
X

0
1
1
1
1
1
1
1
1

1
0
0
0
0
1
1
1
1

1
0
0
1
1
0
0
1
1

0
0
1
0
1
0
1
0
1

Write
Write
Write
Write
Write
Write
RD/WR
Write
Wrile

X

X

X

X

DA10 DA9 DA8 DA7 DA6 DA5 DA4

TOSADD (Top of Screen Address) This register contains
the RAM address of the first character displayed
at the top of the video monitor screen. In addi- .
tion, this register controls selection of either of
two mask programmable vertical scan rates.

REGISTER

DB? DB6 DB5 DB4 DB3 DB2 DBl DBO

X
X
X
X
X
X
X
X
X

X

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO

ADDRESS REGISTER
Writing a byte to the ADDRESS register will select the
specified register for the next time the processor writes to
or reads the EVTLC data registers. The data register
addresses are as follows:
ADDRESS

X

DATA REGISTERS
FILADD (Fill Address) This register contains the RAM
address of the character following the last
address to be filled. Writing to this register will
enable the EVTLC "fill" circuitry. The FILL operation will then be triggered by the next processor
write to the CHARACTER register. The FILL
operation will write the character in the CHARACTER register to every location in display
memory st.arting with the address specified in the
CURLO and CURHI registers through the location preceding the address specified in the
FILADD register. The cursor position is not
changed after a FILL operation. Note that the
address bits DA3-DAO are internally forced to 0
forcing the FILADD address to be 00, 16,. 32, etc.
to 1920. The CURLO and CURHI registers will
not be changed by this operation. Writing to the
CHARACTER register will cause the EVTLC to
reset DB7 of the STATUS register to "0". Bit 7
will be set to 1 after the EVTLC has filled the last
memory location specified.
FILADD REGISTER

REGISTER OPERATION
WRITE TO DATA REGISTER
READ DATA REGISTER
WRITE TO ADDRESS REGISTER
READ STATUS REGISTER

1

x

DONE

DONE = 1 signifies that external processor is allowed to
access CURSOR ADDRESS andlor
CHARACTER registers.
DONE = '" signifies that external processor must wait
until EVTLC completes transfer of data
between display memory and CHARACTER
register.

CRT9153
Addressing of the internal EVTLC data registers of the
Q.RT 9153 is accomplished thro!:!.9!l use of the AID and RI
W select inputs qualified by the DS strobe.

AID DS R/VIi

DB6 DB5 DB4 DB3 DB2 DB1 DBO

DB7

CHIP RESET
TOSADD
CURLO
CURHI
FILADD
ATTDAT
CHARACTER
MODEl REGISTER
MODE2 REGISTER

TOSADD REGISTER
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
TIM DA10 DA9 DA8 DA7 DA6 DA5 DA4
Note that address bits DA3-DAO are internally
forced to 0 forCing the first address at the beginning of each row to be 00, 16, 32, etc. to 1920.
The most significant bit of this register (TIM)
is used to select between the two mask programmed sets of vertical retrace parameters
(scan A and scan B). This allows software
selection of, for example, 50/60 HZ.
TIM = 0 enable raster scan A (60 Hz)
TIM = 1 enable raster scan B (50 Hz)

NOTE: Chip Reset IS required before starlmg operallon.

STATUS REGISTER
When reading the STATUS register, the DONE bit (DB7
of STATUS Register) will represent the current status of the
CHARACTER register. This bit is used to synchronize data
transfers between the processor and the EVTLC. The
EVTLC will set the DONE bit to a logic one after completing
a byte transfer command or a FILL operation. The DONE
403

CURLO

(Cursor Low) This register contains the eight
lower order address bits of the RAM cursor
address. All FILL screen and character transfer
operations begin at the memory location pointed
to by this address.

affected by the display character's TAG bit.
NOTE: All 8 bits are valid for the 9x28 mode. In
the 9x53 mode the only bits that are recognized
are DB6, 5 and 4.

CURLO REGISTER
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DAO
CURHI

(Cursor High) This register contains the three
higher address bits of the RAM cursor address
(DA10, DA9, DA8). All FILL screen and character transfer operations begin at the memory
location pOinted to by this address. In addition,
this register contains the Smooth Scroll Offset
Values SS3-SS0 which determine the number
of scan lines that the data is shifted on the
screen. The MSB of this register (SLE-status line
enable) is the enable for the non-scrolling status
line.

ATTDAT REGISTER
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
DB? (1). MODE
SELECT

DB?

DB?

CURHI REGISTER
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
SLE SS3 SS2 SS1 SSO DA10 DA9 DA8

DB6

SLE = 1 enables non-scrolling 25th
status line
SLE = g disables and blanks nonscrolling status line

CURSOR
SUPPRESS

SS3-SS0 Smooth Scroll Offset Value
ATTDAT

(Screen Attribute Data) Two attribute modes are
provided. In the "tag bit" attribute mode, the MSB
of each character is used to "tag" those characters which are to be enhanced with the attribute specified by the ATTDAT register. This allows
individual characters to be attributed, but with the
limitation that only one attribute style may be
enabled for a specific screen. This is compatible
with the CRT9028/9128, and is specified as the
9x28 operation mode. In the "embedded attribute" mode, multiple attributes may be displayed
on one screen. This is specified as the 9x53
operation mode.. See "MODE 2" register for
selection of 9x28 and 9x53 modes.

DB6

DB6

DB5

The ATTDAT register specifies the visual attributes of the video data, in 9x28 operation mode,
and the cursor presentation. The visual attriDB4
. butes specified in the ATTDAT register (DB3DBO) are enabled or disabled by a TAG bit that
is appended to the ASCII character written to the
CHARACTER register. Every character on the
screen with its TAG bit set is displayed with the
same attribute. Changing the Attribute register
will change the attribute of every "tagged" character on the screen. Character attributes in the
9x53 mode are determined by specific attribute
characters embedded in the character data
stream as explained below in the section titled
CHARACTER SETS. The functions of the
remaining bits in the ATTDAT register are not
404

CURSOR
DISPLAY

DB5
DB5

SCREEN

DB4

DB4

= 1 enables graphics
mode display (No
attributes allowed)
=0 enables alpha
mode displa>j
Note: See CHARACTER SETS for
definition of characters available in
each mode.
= 1 inhibits VIDEO display at cursor time
by forcing the
VIDEO output to
background level
during cursor displaytime
=0 enables VIDEO
display at cursor
time
Note: A blinking
cursor display can
be achieved by
toggling this bit
under processor
control.
= 1 enables underline
cursor display
=0 enables block cursordisplay
Note: An underline
cursor in an underline character
attribute field will
be dashed.
= 1 for white screen
and black
characters
=0 for black screen
and white
characters
Note: This is a
screen attribute
'(versus character
attribute) bit and
sets the default
video background
level.

§'

DB3(1)

o

w

o

o

:2

~

CHARACTER DB3 = 1 to enable Video
SUPPRESS
suppress
DB3 = 0 to inhibit Video
suppress
Note: This bit allows
character blinking
and blanking under
processor control

I-

m DB2(1)

INTENSITY

DB2= 1 allows the INTOUT
output pin to go
high for the charactertime
DB2= 0 inhibits the
INTOUT output pin
from going high

(!)

~

ib
o

W
..J

~

15
a:
o
o

DB1(1)

W

..J

~

W

DBO(1)

MODE 2 REGISTER
X

DBO= 1 will cause the
standard foreground and background Video
levels (selected
with BIT 4) to be
reversed for the
character time
DBO= 0 will inhibit reverse
video

The AUTO INCREMENT bit in this register
specifies whether or not the display memory
character address is automatically incremented by the EVTLC after every readlwrite
of the CHARACTER register. Note: The visible cursor position is not affected.
MODE 1 REGISTER
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
AUTO X
INC

X

X

X

X

X

X

DB? AUTO
DB? = 1 to enable
INCREMENT automatic character
address
The RAM address is
incremented after the
EVTLC completes a
display memory access
initiated by a processor
to RAM or RAM to
processor
character
transfer.

X

X

X

X

X

DBO

CUR 9x53
BLINK ENBL

DB1 CURSOR
BLINK

DB1 = 1 will enable
blinking cursor.
DB1 = 0 will disable
blinking cursor and state
of cursor is controlled by
DB6 in ATTDAT register.

DBO 9x53
ENABLE

DBO = 1 will enable
operation as a 90531
9153.
DB = 0 will enable operation as 9028/9128.

CHARACTER

(1) These bits not recognized in 9x53 mode and represent
don't care states.

MODE 1

This register contains two bits which control
operational modes of the device. DBO controls whether the device operates as a 9x53
or emulates the 9x28. In the 9x28 mode the
device is fully compatible with the CRT 90281
9128 with the exception of the higher density
character set. DB1 enables the cursor blink
function where the blink rate is a mask programmable feature (see CRT 9053/9153
coding sheet.) This function is automatically
disabled when in 9x28 mode.

DB? DB6 DB5 DB4 DB3 DB2 DB1

UNDERLINE DB1 = 1 will cause the characterto be
underlined
DB1 = 0 will inhibit the
underline
REVERSE
VIDEO

MODE 2

This register allows access to the display
memory for both byte transfers and FILL
operations. In BYTE Transfer Write Mode,
the processor first writes a character to this
register. The EVTLC takes that character
and stores it in the display memory in the
location specified by the CURLO and
CURHI registers. In Byte Transfer Read
Mode, the processor reads this register
causing the EVTLC to fetch the character
whose address is specified in the CURLO
and CURHI registers from the display
memory and place it in the CHARACTER
register. The processor then reads the
character and initiates another fetch from
memory cycle. In FILL mode, writing a byte
to this register will initiate a FILL operation.
All EVTLClmemory data transfers take
place during horizontal and vertical video
retrace blank time.
CHARACTER REGISTER
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
8 BIT CHARACTER(2)

(2)See next section, CHARACTER SETS, for definition of 8
bit characters.

DB? = 0 to disable
automatic increment.
405

GRAPHICS CHARACTERS(3)

CHARACTER SETS
The character set consists of 128 characters, a six segment "wide graphics" and a four segment "thin graphics"
entity. Included in the 128 mask programmable characters
can be the 96 standard ASCII characters and 32 special
characters.

SEGMENT

6
SEGMENT

SEGMENT
3

5

SEGMENT
2

SEGMENT
4

SEGMENT
1

9x28 OPERATION MODE (MODE 2: DBO = 0)

A. GRAPHICS MODE -.(ATTDAT: DB7 = 1)
This mode allows an intermix of afphanumeric and
graphics characters. No attributes are permitted in this
mode. If DB7 = 1, the character will be alphanumeric. If
DB7 = 0, the character will be a graphics character. DB7
is "tag bit".
ENTITY

DB7

DBB

DB5

I·

CHARACTER

THIN(l)
GRAPHICS

DB4

DB3

DB2

DBl

DBD

WIDE GRAPHICS ENTITY

SEGMENT 3

--I

CHARACTER DATA

X

X

SEG4

SEG3

SEG2

SEGl

SEGB

SEG5

SEG4

SEG3

SEG2

SEGl

SEGMENT4

SEGMENT 2

WIDE(l)
GRAPHICS

SEGMENT 1

B. ALPHANUMERICS MODE-(ATTDAT: DB7 = 0)

THIN GRAPHICS ENTITY

This mode allows display of alphanumeric characters with
attributes. If DB7 is set to a logical one, the attribute(s)
specified in the ATTDAT register will be enabled for that
character. If DB7 is cleared, attributes will not be enabled
for that character. DB7 is "tag bit".
ENTITY

DB7

DBB

DB5

1•

CHARACTER
(Attr enabled)

DB4
DB3
DB2
CHARACTER DATA

I-..
_---(CHARACTER DATA

CHARACTER

(No attribute)

9x53 OPERATION MODE (MODE 2: DBO

DBl

(3)Scan line and column of segment
locations are mask programmable.

DESCRIPTION OF SYSTEM OPERATION

DBD
_ 1

The EVTLC circuitry provides two control functions. One
function interprets and controls data from the system processor interface through the data bus DB7-DBO as shown
in the Processor Timing of figure 3. The other function generates and refreshes the video image on the screen through
the DD7-DDO data bus as shown in the Display Memory
Timing of figure 2. Because the system data bus is isolated
from the display data bus, the EVTLC maintains complete
control over access to display memory. All data flow between
display RAM and the processor or the EVTLC takes place
through the EVTLC. Refer to the EVTLC Display Memory
Access Timing of figure 7.

-----~I

= 1)

This mode allows the use of embedded field attributes
where the desired attribute for any given string of one or
more consecutive characters is defined by an attribute
character which is part of the character data stream and
is located immediately in front of the characters to be
attributed. A second attribute character should be located
immediately following the string of attributed characters
to restore the normal display mode. Since the specific
attribute characters occupy character positions, they are
actually displayed as spaces.
ENTITY
CHARACTER

ATTRIBUTE(2)

DB7

DBB

D

I·

DB5

DB4

DB3

DB2

DBl

BLANK BLINK

DBD

-I

CHARACTER DATA

CHARACTER
THIN(l}
GRAPH!CS

DISPLAY MEMORY ACCESS

INT

UNDLN

RV

X

SEG4

SEG3

SEG2

SEGl

SEG5

SEG4

SEG3

SEG2

SEGl

WIDE(l)
GRAPHICS

SEG6

Graphics segments are turned on when bit is set to a "1 ".
(2)A specific field attribute is enabled by setting the appropriate bit and disabled by resetting the bit. Attributes can
be mixed. The following defines the available attributes
indicated in the ATTRIBUTE CHARACTER.
DB4 (BLANK)-Suppresses character video output.
DB3 (BLlNK)-Causes character to blink at mask programmed rate.
DB2 (INTENSITY)-Controls INTOUT output pin.
DB1 (UNDERLlNE)-causes character to be
underlined.
DBO (REVERSE VIDEO)-Reverses foreground/background video levels.
(1)

406

Processor/display memory access is accomplished
through the CHARACTER register of the EVTLC. All processor transfers to or from the CHARACTER register take
place only when the DONE bit is high. The DONE bit is used
to synchronize data transfers between the EVTLC and the
processor as shown in the Typical Processor To Display
Memory Transfer of figure 6. When the processor needs
to store a byte of data in the display memory, it will write the
byte to the CHARACTER register of the EVTLC. The EVTLC
will immediately reset the DONE bit indicating that the
transfer hardware is busy. At the next blanked Video time,
the EVTLC will store the byte in the display memory, increment the character address, (if auto increment is enabled)
and set the DONE bit. When the processor needs to read a
byte of data from the display memory, it will read the CHARACTER register. The EVTLC will fetch the desired byte from
the display memory during the next blanked VIDEO time,
increment the character address (if enabled), and set the
DONE bit. When the processor detects that the DONE bit
is set, it will read the CHARACTER register to get the data
byte from the EVTLC. This read will reset the DONE bit and

cause the EVTLC to fetch the next byte of data from the
memory.
If auto increment is not enabled, the processor must set
the cursor address in the CURLO and CURHI register to the
address of the memory location being read from, or written
into, before every access to the CHARACTER register.
It should be noted that Auto Increment does not affectthe
visible cursor location. If auto-increment is enabled, the
current character location will equal the cursor position only
for the first character transfered following an update of the
CURLOandCURHI registers. Note that the DONE bit must
be high before attempting to update the cursor registers
because the loading of the cursor registers will reset the
character position counters to the cursor position.

When programmed for a data row of 80 characters/data
row display (1920 data words), for example, the display RAM
contains 25 actual rows of data (2000 RAM locations). If the
smooth scroll offset equals zero, the EVTLC will display the
1919 RAM locations following the top of screen address
when displaying data. The first data row is partially scrolled
off the screen and the 25th data row is scrolled onto the
screen when the smooth scroll offset is incremented. The
EVTLC will now display the 1999 RAM locations following
the top of screen address (wrapping to 0 after address 1999).
Afterthe EVTLC does ajump scroll, the processor will program it to erase the line just scrolled off the screen (preparing it to be scrolled onto the screen). This line now becomes
the non-displayed 25th data row.
NON-SCROLLING STATUS LINE

SMOOTH SCROLL
The EVTLC may be programmed to do either "jump" or
"smooth" scrolling. Jump scrolling moves the data up or
down the monitor screen one data row at a time. Smooth
scrolling moves the data up the monitor screen one scan
line at a time. The number of scan lines and the rate they
move up the screen is under processor control.
Smooth scroll is controlled through manipulation of the
SS3-SS0 bits of the CURHI register. These bits represent
the binary address of the first scan line of the first data row
displayed on the monitor screen (the data row whose
beginning address is in the TOSADD register). When the
value represented by these bits is incremented, the video
data on the monitor screen moves up by the same number
of scan lines. After the address of the last scan line of the
data row is loaded into the CURHI register and the VIDEO
data has moved up the last scan line of the data row, the
processor resets the SS3-SS0 address to point to scan line
o and does a jump scroll. Jump scroll is accomplished by
incrementing the RAM address in the TOSADD register by
a data row length (so that it points to the address of the first
character of the new top data row on the monitor).

The non-scrolling status line is only functional on a EVTLC
that has been programmed for 25 data rows. This data row
will remain stationary at the bottom of the screen and will
not move up the screen when the remainder of the display
data is scrolled. Otherwise, VIDEO data on the status line
may be manipulated as though it were normal display data.
The smooth scroll offset will not function properly when the
status line is enabled. The memory address of the characters on the status line are always characters 1920-1999.
NOTE: If the part is programmed for 25 data rows an additional mask option must be specified which makes the 25th
data row either fixed (always displayed) or a status row
(enabled/disabled by the SLE bit).
CHIP RESET
The CRT 9053 and CRT 9153 Chip Reset requires two
steps. The system processor first writes the reset address
to the address register of the EVTLC. The system processor then writes a dummy character to the EVTLC Data register. Writing to the Data register resets the chip. See the
DONE timing in figure 6. This reset process causes the
MODE 2 register to be set to the "00" state which disables
the blinking cursor and enables the 9x28 operation mode.

ROM CHARACTER BLOCK FORMAT
COLUMN DOT

->

SCAN LINE 0

->

SCAN LINE 1

->

SCAN LINE 2

->

SCAN LlNE3

->

SCAN LINE 4

->

SCAN LINE5

->

SCAN LINE 6

->

SCAN LINE 7

->

SCAN LINE 8

->

SCAN LINE 9

->

SCAN LINE 10

->

SCAN LINE 11

->

SCAN LINE 12

->

o

Dots/Charac1er: 8 dots/charac1er cell
9 dOls/charac1er cell

~
~

> C8 - Cl displayed
> C8 • CO displayed

Column dot CO will be the same as column dot C8 when more
than 8 dots/character cell are specified when generating alpha-numerics.

o
o

o
MASK PROGRAMMABLE
CHARACTER BLOCK
(FONT)
7Xll

o
o
o

NOTE: The maximum dot clock crystal frequency is dependent on'the
dots/character programmed:

*These values are preliminary

Scan Lines per Character:
11 scan Iines/charac1er = > SLO·SL 10 displayed
12 scan Iines/charac1er = > SLO-SL 11 displayed
13 scan lines/charac1er = > SLO-SL 12 displayed
Thin and Wide Graphics: Dots mask programmed for vertical column C1

will be the same as backfill Columns 0 when
generating wide and thin graphics.

Mask programmable oplions-The ROM charac1er block format above shows the 7Xll mask
programmable charac1er font within the charac1er cell as defined by dots C8 through CO and
scan lines 0 through 12.

407

MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range .......................................................................O°C to + 70°C
Storage Temperature Range ......................................................................... - 55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ............................................................... + 325°C
Positive Voltage on any Pin, with respect to ground ................................................. + 8.0V
Negative Voltage on any Pin, with respect to ground ................................................ - 0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches"
on their outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may
appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA =0 °C to 70°C, Vee =
PARAMETER

+ 5V

± 5%, unless otherwise noted.)

MIN

DC CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, Vii
High-Level, Vih
OUTPUT VOLTAGE LEVELS
Low-level, Vol

TYP

MAX

UNIT

0.8

V
V

0.4

V

0.4

V

2.2

Low-level, Vol

High-level, Voh

2.4

V

High-level, Voh

2.4

V

INPUT LEAKAGE CURRENT
High-level, IIh

COMMENTS

All outputs except
VIDEO, CSYNC,
INTOUT, HSYNC,
VSYNC; 101 = 1.6 mA
VIDEO, CSYNC,
INTOUT, HSYNC,
VSYNC; 101 = 0.4 mA
All outputs except
VIDEO, CSYNC,
INTOUT, HSYNC,
VSYNC;loh =
-40!-La
VIDEO, CSYNC,
INTOUT, HSYNC,
VSYNC;loh =
- 2O!-LA

10

!-LA

All inputs; Vin = Vcc

Low-level, III

-10

fLA

All inputs
except.YYR, RD,
DS, R/W; Vin = O.4V

Low-level, III

-200

!-LA

WR,RD,
DS, R/IN; Vin = O.4V

15

pF

15
100

pF
pF

INPUT CAPACITANCE
All inputs, Cin
OUTPUT LOAD
CL
CL
POWER SUPPLY CURRENT
Icc
AC CHARACTERISTICS
CLOCK FREQUENCY, fin
DISPLAY MEMORY TIMING
Address Set-up Time
t AS
Write Strobe Set-up Time
t WST
Data Set-up Time
tST
Data Hold Time
tOH

125
18.7

1.0

MHz

20

ns

100

ns

80

ns

10
408

mA

I

50

ns

Except DB7-0
DB7-0

PARAMETER

MIN

Address Hold Time
tAHT
Output Hold From Address Change
tOH
Address Access Time
tAA
PROCESSOR TIMING
Address Read/Write Set-up
tARWS
Write Pulse Width
twpw
Write Hold Time
tWHT
Read Set-up Time
tRST
Read Data Valid
T Rov
Read Pulse Width
tRPW
Data Write Falling Set-up
tOWFS
Data Write Rising Set-up
tOWRS

TYP

MAX

50

ns

15

ns
250

ns

160

ns

15

ns

ns

250

ns

120

ns

160

ns

ADDRESS

DWR

READ DATA
FROM RAM
EVTLC OUTPUT
TO RAM

EVTLC INPut
FROM RAM

NOTE: DISPLAY ADDRESS BUS DAtO·DAO MUST NOT CHANGE WHILE DWR IS LOW

FIGURE 2. DISPLAY MEMORY TIMING

(1) If set·up time is not met, screen may glitch when cursor or attribute
registers are changed during active video time.
(2) Minimum set·up time to ensure valid data into EVTLC internal registers.

FIGURE 3. PROCESSOR TIMING
409

ns

0

Crystal specification (Applies for 4-18.7 MHz):
Series Resonant
50 ohms max series resistance
1.5 pf typ parallel capacitance
Operation below 4 MHz requires external crystal oscillator

DD7·DDO

ns

160

200

OAt 0·0

UNIT

COMMENTS

VERTICAL

VERTICAL TIMING

SYNC

I DURATION 1

1

I-

I

>1

VSYNC~
I+1
1
DELAY
I
I
1
1
V SYNC _ _ _ _---'I_-'r---\'-_---,I'-_ _-III-I _ _ _
1
1
1
II

----'1

1

1

VBLANKING _ _~ _ _..JI

~

\ ____--jl I

t-- NUMBER OF BLANKED --.r

1

SCAN LINES

1;---1

~Y~p~~O~t------;

-

DATA ROWS
HORIZONTAL TIMING

HORIZONTAL

SYNC
DURATION

!+-------.I

1
HSYNC
DELAY

r.--

-..I
1

1

1
1

I
I
1

1

I

1
1
1

HSYNC _ _ _ _---'I'-~r----\~---7I---_ilrl----~;--

HBLANKING _ _ _ _ _-'1

71

1
1
1

\

14------

NUMBER OF

cJk~~~f~RS

~

II

~

...-

7r - - I
~y~p~~~~J' ---+f
CHARACTERS

NOTE. Video parameters above are mask programmable

FIGURE 4. VERTICAL AND HORIZONTAL SYNC TIMING

,n
I
I

HSYNC~
VSYNC

n

I
1
I
1
1

I

~.

H----j

I--H/2--1

CSYNC

1

n

n

I
I
1
I
1
1
1
1

n'---_-----IlL

I
I

I
I

1
I
I

NOTE: Delays be~ween pulse edges and pulse width values may vary due to mask programmable features.
'H represents hOrizontal interval

HSYNC _ _ _ _ _

---,~r--l~----­

_______
~~d~r_--------

U

CSVNC
d == HSYN Delay -CSYN Delay

WITHIN VERTICAL SYNC
PULSE TIME

OUTSIDE OF VERTICAL
SYNC PULSE TIME

FIGURE 5. VIDEO SIGNAL TIMING

1Ds?-O XXXXXXXXX

xxxxxxxxxxxxxxxx

ASCII CHARACTER

PROCESSOR

BUS

L!" -------------,.

PROCESSOR WRITES CHARACTER



SCAN LINE 0

->

0

SCAN LINE 1

->

0

0

SCAN LINE 2

->

0

0

SCAN LINE 3

->

0

0

SCAN LINE 4

->

0

0

SCAN LINE 5

->

0

C8 C7 C6 C5 C4 C3 C2 C1 CO
0

0

0

0

0

0

0

0
CHARACTER BLOCK
7X11 CELL

SCAN LINE 6

->

0

SCAN LINE 7

->

0

0

SCAN LINE 8

->

0

0

SCAN LINE 9

->

0

0

SCAN LINE 10

->

0

0

SCAN LINE 11

->

0

0

DOTS PER CHARACTER:
DOT CLOCK XTAL FREQUENCY (MHz):
HORIZONTAL TIMING (IN CHARACTER TIMES):
CHARACTERS PER DATA ROW:
HORIZONTAL BLANKING:
HORIZONTAL SYNC DELAY:
HORIZONTAL SYNC PULSE WIDTH:
HORIZONTAL SYNC POLARITY:

0

9
17.1072
80
19
4
8
NEGATIVE ACTIVE

J.-- HORIZ BLANKING~
I
.I

ACTIVE VIDEO

VIDEO

0

ACTIVE VIDEO

---------11

L._ - _ -_ _ _
- _ _- _ - _

HSYNC
HORIZ SYNC DELAY

III.

IV.

-I-

~..

HORIZ SYNC--I
PULSE WIDTH

VERTICAL TIMING:
CHARACTER ROWS:
SCAN LINES PER CHARACTER:
TOTAL VISIBLE SCAN LINES:
VERTICAL SYNC POLARITY:

25
x12
300
NEGATIVE ACTIVE

VERTICAL SYNC TIMING (IN SCAN LINES):
60 Hz VERTICAL BLANKING:
60 Hz VERTICAL SYNC DELAY:
60 Hz VERTICAL SYNC PULSE WIDTH:
ALTERNATE (50 Hz) VERTICAL BLANKING:
ALTERNATE (50 Hz) VERTICAL SYNC DELAY:
ALTERNATE (50 Hz) VERTICAL SYNC PULSE WIDTH:
ACTIVE VIDEO

20
4

8
84
17
34

L-- VERTICAL BLANKING----I
I

I-

--------11

ACTIVE VIDEO

L._ _ _ _ _
- _ _- _ - _

VSYNC

---'V~S;YNNCCCD~ELLA~Y~=+14;:~·~I~..-VERTSYNC~
PULSE WIDTH
412

V.

COMPOSITE SYNC OUTPUT (IN CHARACTER TIMES)
2
8

COMPOSITE SYNC DELAY:
COMPOSITE SYNC PULSE WIDTH:

ACTIVE VIDEO

ACTIVE VIDEO

VIDEO

--------1

1--------

CSYN

..

..

CSYN DELAY -1oe1llll..--....;.~IIoI..---~1

VI.

CSYN PULSE WIDTH

BLINK RATES (@ 60 Hz VSYNC):
CHARACTERBLINK RATE:
DUTY CYCLE:

1.25 Hz

CURSORBLINK RATE:
DUTY CYCLE:

2.5 Hz

75/25

50/50

VII. UNDERLINE ATTRIBUTE:
CHARACTER UNDERLINE:
CURSOR UNDERLINE:

SCAN LINE 11
SCAN LINE 11

VIII. WIDE GRAPHICS FIGURE DEFINITION:
COLUMN

->

ca C7

C6

C5 C4

C3 C2

C1

CO

SCAN LINE 0 ->
SCAN LINE 1 ->

SEGMENT 6

SCAN LINE 2 ->

T

rT

SEGMENT 3

SCAN LINE 3 ->
SCAN LINE 4 ->
SCAN LINE 5 ->
SCAN LINE 6 ->

~

SEGMENT 2

SEGMENTS

SCAN LINE 7 ->
SCAN LINE a ->
SCAN LINE 9 ->
SEGMENT 4

SCAN LINE 10->

IX.

W1

H1 = SCAN LINES 4, 5, 6, 7
HO = SCAN LINES a, 9,10, 11
W1 = ca, C7, C6, C5, C4
WO = C3, C2, C1, CO

HO

SEGMENT 1

1

SCAN LINE 11 ->
I.

H2 = SCAN LINES 0,1,2,3

WO~

.. 1-0.

THIN GRAPHICS FIGURE DEFINITION:
COLUMN DOT ->
SCAN LlNEO

->

SCAN LINE 1

->

SCAN LlNE2

->

SCAN LlNE3

->

SCAN LINE 4

->

SCAN LINES

->

SCAN LlNE6

->

SCAN LlNE7

->

SCAN LINEa

->

SCAN LINE 9

->

ca C7

C6 C5 C4 C3

C2

C1

CO

S
E
G
M
E
N
T
3

I

SEGMENT2

SEGMENT4

SCAN LINE 10 ->
SCAN LINE 11

.---

->

SEGMENT 4 = SCAN LINE 6; ca, C7, C6, C5, C4
SEGMENT 3 = C4; SCAN LINES 0, 1,2,3,4, 5, 6

I

S
E
G
M
E
N
T

e-L
SEGMENT 2 = SCAN LINE 6; C4, C3, C2, C1, CO
SEGMENT 1 = C4; SCAN LINES 6,7, a, 9, 10, 11

413

KEYBOARD
CONN

iOfl!

OPTIONAL
SERIAL
EEROM

XTAL 1

XTAL 1 XTAL2

"

INTO

~INT1

P2.3
P2.2
P2 .,

SK

P2.0

DO

XTAL2

CS
DI

VSYNC

LS~.....VE_R_T_IC_A_LS_Y_N_C ,.

b~

HORIZONTAL SYNC

10----,-10
VIDEO

HSYNC

1P25
COMM
CONN

PO.7 -PO.O

I\.

6SO VIDEO

I

I~
3900

DWRP-------,

OR
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~

)

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S051

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CRT 9053
DISPLAY MEMORY

ADDRESS BUS

~ A 1.0'-A9

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PRINTER
CONN

P'.5

:~

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}

DATA BUS

) D7-DQ'

TO MONITOR

KEYBOARD
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OPTIONAL
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XTAL 1

I

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XTAL2

CS

INT1
INTQ'

PROG

01

INT2

PORT

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PORT
BIT IN

COMM
CONN

LS24.G'
VERTICAL SYNC) }

I

VSYNC

I .:;:.0 HORIZONTAL SYNC;:
)

HSYNC

b •

68n VIDEO

VIDEO
INTOUT

PORT

1----11 BIT OUT

PORT
A07-AO.G' I\.,

.II OB7-0B.B'
I

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PORT
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1489

DISPLAY MEMORY

RXO
ADDRESS BUS

OA1.G'-0A.G'

PRINTER 1488
CONN
~

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~

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CRT92C07
PRELIMINARY

Advanced Terminal Logic Controller
ATLC
FEATURES:

PIN CONFIGURATION

o Internal 12 Bit 42 MHz Video Shift Register.
o Internal Oscillator (10 MHz to 42 MHz) or External
TTL Clock.
o Internal Clock Divider to Generate 80/132 columns.
o Separate 16 Bit Wide Private Display Memory Bus
Resolves Memory Contention.
o Row Table Indirect Video Memory Addressing.
o X-V Cursor Addressing.
o Multiple Bi-Directional Partial Page Smooth Scroll
Regions.
o Line Lock Capability.

z~

PD4
PD5
POs
PO?
INTER

o Programmable Interrupt Generation.

o

o

r-"'11.D
1O.D,CC,L.I:,LJ:,J.J:5J.J:.U,li,:J..OJ,,::U4B""'s~~-~;;- 7675
12
74
13
73
14
15
16

XTAl1

17

XTAL2
CGDO

18
19

CGDl
CGD2

20
21

CGD?

26

eGOS
eG09
CGD10
CGD11
eWE
COE

27
28
29
30
31
32

OA3
DA4
DA5
DAB
OA7

DAB

64
63
62
61
60
59

CGD3
CGD4
eGOS
CGDS

o Programmable Display Format:

Dots per character (9-12)
Characters per Data Row (64-132)
Data Rows per Frame (24-64)
Raster Scans per Data Row (10-16)
Programmable Sync Format:
Horizontal Blanking Time (8-128 Characters)
Horizontal Sync Delay (0-64 Characters)
Horizontal Sync Pulse (1-64 Characters)
Vertical Blanking Time (8-255 Scan Lines)
Vertical Sync Delay (0-63 Scan Lines)
Vertical Sync Pulse (1-63 Scan Lines)
Programmable Attribute Features:
Character Underline Position
Cursor Underline Position
Character Blink Rate and Duty Cycle
Cursor Blink Rate and Duty Cycle
Blink Mode
Four Level Intensity Control

550 ~

~~~~~i~!i~~~e~~~~;g~~

~~~$R.~.~.aM

• • U.~~~~.

DA13
OA14
OA1S
NC
NC
NC

58

000

57

DOl
D02

56
55
54

DD3
004

PACKAGE: 84-pin PLCC

o Mask Programmable Features:
o
o
o
o

Vertical Sync Polarity
Horizontal Sync Polarity
Video Output Polarity
Parallel and Tag Character Video Attributes.
External CharacterGenerator-Loadablethru the ATLC.
CMOS Technology for Low Power Consumption.
All Inputs and Outputs TTL Compatible.

GENERAL DESCRIPTION
The CRT92C07 Advanced Terminal Logic Controller (ATLC)
is a CMOS VLSI implementation of all the logic functions
required for generation of the timing and video outputs for
a terminal design.
The ATLC incorporates all of the functions associated with
a CRT controller and an attributes controller. These
functions include register programmability of all timing
parameters, pOSitioning of cursor, addressing of display
memory, control of screen partitions, generation of video
and timing signals and application of attributes.
The ATLC provides three independent bus interfaces-the
system processor, display memory, and character generator
memory. Data is transferred from the processor to the
display memory and character generator memory through
the ATLC. The double speed architecture of the ATLC

provides access to display memory at the character rate for
both display refresh and data update functions. The external
character generator can be implemented with either
EPROM or static RAM (for soft font implementations).
A row table addressing method is used to access character
data from display memory. This method provides the
capability to create multiple split screens and to smooth
scroll each screen region simultaneously and independently.
The use of a link within the row table allows flexible
manipulation of the sequence of character rows on screen.
The built in attributes controller, equivalent to the CRT9041
Video Attributes Controller, can support parallel, embedded,
or tag attributes. All commonly used video terminal attributes
are supported; in particular those required for DEC VT1001
220 emulation.
417

DESCRIPTION OF PIN FUNCTIONS
DISPLAY MEMORY INTERFACE
PIN NO.
62-76
43-58

35

34

36

NAME
Display Memory
Address
Display Memory
Data
Display Memory
Character Write
Enable
Display Memory
Attribute Write
Enable
Display Memory
Output Enaule

SYMBOL
DA15-1
0015-0

DCWE

':iR""""'11i"'1

;::~~:.. """,,Momo~ ""'~ ~

bit
_
the LSB.
Input/Output. Sixteen bit bi-directional Display Memory Data bus. Character data
is transferred on 007-0 and attribute data on 0015-8. 0015 is the MSB and 000
is the LSB.
Output. Active low write strobe to Display Memory. This signal is active when
character data is being written to the display memory.

DAWE

Output. Active low write strobe to Display Memory. This signal is active when
attribute data is being written to the display memory.

DOE

Output. Active low output enable strobe to Display Memory. This signal is active
whenever character and/or attribute data is read from memory.

CHARACTER GENERATOR MEMORY INTERFACE
77

Character Clock

CCLK

33

Alternate Font
Select

ALTFS

38-41

Scan Line Data

SL3-0

30-19

Character
Generator Data
Character
Generator Write
Enable

CGD11-0

Character
Generator
Output Enable

COE

31

32

CWE

Output. This output defines the rate at which characters are output to the screen.
This signal is also used to externally latch the 8 address bits output from DA7-0
for the external character generator. This clock output does not stop as a result of
the RESET or Stop commands.
Output. This signal reflects the state of the Underline 21Alternate Font Select
attribute bit (000) or the Font Select bit in the Mode 4 register. When it reflects
the state of the attribute bit, it is internally pipelined such that it is output at the
same time that the associated character data is presented to the address inputs
of the character generator. This output is typically connected to the MSB of the
address bus to the character generator.
Output. These signals represent scan line data that are used to provide the four
LSB's of the character generator address. SL3 is the MSB and SLO is the LSB.
Input/Output. Twelve bit bi-directional data bus to the Character Generator
memory.
Output. Active low write strobe to the external character generator memory. This
signal is active when the processor is writing pattern data to the Character
Generator memory.
Output. Active low output enable strobe to Character Generator Memory. This
output is active whenever character pattern data is read from memory.

PROCESSOR INTERFACE
3-2

Processor Address

PA1-0

Input. These signals represent a 2-bit address bus from the processor which is
used to access either the Status, Pointer, Character Data, RAM Address registers
or the internal registers pOinted to by the Pointer Register.

15-8

Processor Data

PD7-0

6

Read Strobe

RD

5

Read/Write Select

R/W

4

Data Strobe

DS

Input/Output. Eight bit bi-directional Processor Data bus. PD7 is the MSB and
PD~ is the LSB.
Input. This si~1 is useQ.!o gate data from the ATLC onto the processor bug
design usi!:!ll...OS and R/W should tie RD to ground. A deSign using RD and WR
should tie OS to ground.
Input. This si~1 deter!TI!Des if the processor is reading or writing to the ATLC. A
design usi!:!ll...DS and R/W should tie RD to ground. A design using RD and WR
should tie OS to ground.
Input. This signal causes data to be strobed into or ot!!.of the ATLC from the
Proces~r Data bus depending on the state of the R/W si~ A design using OS
and R/W should tie RD to ground. A design using RD and WR should tie OS to
ground.

7

Chip Select

CS

16

Interrupt

INTER

Input. This signal is active low and enables all read and write operations between
the processor and the ATLC.
Output. This signal is active high and occurs when the ATLC encounters an
enabled interrupt causing condition. This Signal is reset by reading the Interrupt
Status register or a Reset command.

418

VIDEO INTERFACE
PIN NO.
NAME
82
Horizontall
Composite Sync

83

Vertical Sync

78

Video

79-78

Intensity Out

SYMBOL
H/CSYN

FUNCTION
InpuVOutput. This signal provides either a horizontal or composite
synchronization output. It can also be driven as an input to allow synchronization
of horizontal sync to an external source. The function of this signal is register
programmable. After reset, this signal defaults to the input mode. The polarity of
the signal is mask programmable.
InpuVOutput. This signal provides either a vertical synchronization output. It can
VSYN
also be driven as an input to allow synchronization of vertical sync to an external
source. After reset, this signal defaults to the input mode. The polarity of the
signal is mask programmable.
VIDEO
Output. This signal provides the serial dot stream for the video interface. The
polarity of this signal is mask progammable.
INTOUT2-1 Output. These signals provide the two bits of the intensity attribute for use with an
external mixing circuit to create variable intensity on screen. This signal is
modified at the character rate and is synchronized with the VIDEO output.

MISCELLANEOUS
17-18
Crystal Input

XTAL1-2

81,84
1,42

VCC
GND

Power
Ground

,

Input. These inputs are used for direct connection to a crystal. An external TTL
level clock may be used to drive XTAL 1, in which case XTAL2 should be
left floating.
5.0 volt power connection.
Ground connection.

SYSTEM DESCRIPTION
The system diagram shown in Figure 1 illustrates the
minimum hardware required to implement the display
interface for a terminal design using the ATLC. There are
three bus interfaces, the video interface and the clock inputs.
The only external logic required is a decoder for generating
the chip select on the processor bus and an 8 bit latch
between the Character Generator RAM and the Display
Character RAM.
Processor Bus
The processor bus consists of a 2 bit address bus (PAt-D),
8 bit data bus (PD7-0) and three control signals. The MSB's
of the processor address bus are decoded to generate the
Chip Select (CS) signal for the ATLC. Three control signals
are available as inputs to the ATLC for data transfers over
the bus-Read ~obe (RS), Data Strobe (DS) and Readl
Write Select (R/W). Only two of these three signals will
typically be used depending on the lyRe of system.Q.rocessor
belng used. One option would be RD and R/W, where
R/W would serve as a write strobe inpJ!.!..(DS mY§t be
grounded), and the other option would be DS and R/W (RD
must be grounded).
There are five directly accessible registers in the ATLC which
are selected by two address inputs (PA1-0). All other
registers in the ATLC are indirectly accessible via one of the
direct registers, the Register Pointer. There is also an
Interrupt (INTER) output provided identifying key internal
events.
Display Memory Bus
The display memory bus consists of a 15 bit address bus
(DA15-1), a 16 bit data bus (DD15-0) and three control
signals. The 15 bit Display Memory Address bus provides
access to a maximum of 32K, 16 bit words which are divided
into 8 bits for character data and 8 bits for attribute data.
The last 256 memory locations (highest memory addresses)
are used to store the row table. The 8 MSB's of the Display
Memory Data bus are the attribute data and are used by the
ATLC to generate unique attributes for each character output
to the screen. The 8 LSB's of the Display Memory Data bus
are the character data and this data is latched externally, as
shown in Figure 1, to provide 8 of the 13 bits of the address
.for the character generator memory. There are three .control
signals-separate write enables for the character and

attribute RAM's and an output enable when reading from
the RAM's.
The processor can access the display memory through the
ATLC. The processor writes an address to the RAM Address
Register which serves as a pointer to the display memory
location to be accessed. Next the processor either reads
data from or writes data to the display memory through the
Character Data register. The ATLC actually performs the
transfer with the display memory using a Busy status bit as
a flag to indicate when the transfer has been completed.
The ATLC is capable of performing two display memory
accesses during each character period. One access is for
refresh of the screen (during visible scan time) and the other
is for data transfers from the processor (at any time). This
architecture eliminates the memory contention problem and
provides maximum throughput from the processor to display
memory.
Character Generator Memory Bus
The character generator memory bus consists of a 13 bit
address bus, a 12 bit data bus (CGD11-0) and two control
signals. Five of the 13 address bits are output by the ATLC
(ALTFS, SL3-0) while the other eight come from the external
latch that stores the ASCII character data coming from the
Display Character RAM. The 12 bits of pixel data are
transferred to the ATLC, processed by the attribute logic and
converted to serial form for output on the Video signal. The
character generator memory can be implemented with
either EPROM or RAM. If RAM is used then the processor
can make use of character data and address registers in the
ATLC to download the character font. The control signals
provided are a write enable and an output enable.
Video Interface
The ATLC outputs all the Signals required by the video
interface. These include the serial video data signal, two
intensity signals and the vertical sync and horizontall
composite sync signals. The dot clock can be generated by
a crystal oscillator internal to the ATLC. The crystal placed
on the XTAL1/XTAL2 inputs should be that required for the
dot clock used for a 132 column display. When switching
between 80 and 132 column displays, the ATLC will
automatically perform a divide by 2/3 of the dot clock
internally. There is also the option of driving the XTAL1 input
with ,a TTL clock.
419

9t::9

t-f--;",~---+1b~ of--*+H++------'

'"

°IW
Ei~

00

I"-

o

Uu
C\I...J
0'11-:

I-
,-----~
~
ADORa

ADOR1

ADOR2

AOOR3

ADOR13

DDR13~
-

-..,.,..,.,.,..,.,.,..,..,.,..,..,.,..,~

HIGH IMPEOANCE

DOUT15-0

FIGURE 2: CRT 94C12 QUAD ROW BUFFER READ TIMING
429

I

I

I

,''---~i-+'----------------------~l~l-------------------.. l~l

CLRCNT

--~----~-~~~::-.,~---~:----------------------~t~l--------------------,_,
I

INTERNAL
RAMADDR
(WRITE)
WEN
INTERNAL
WEN
DINI5-0

I

I

I

I

I

I

'l!1!1!//I!//Jj/!I!I!II!II!!!I!/I!Jt..~---A---DDR---O-~,"--ADD_R-'C~I!I!I!I!I!I!!I!I!I!
2

_____~I
________________________~I

'L-J
'L-J

u

7f!!I!//!!I!I!I!I!-II!!I!!/II~i:tllllll!11E~if~jJ2/~I!!I!//II!I!!!I!m/l$/////Ih

·in general WCLK and RCLK can be different

FIGURE 3: CRT 94C12 QUAD ROW BUFFER WRITE TIMING

io------------bw.IcvR----------..I
1+-----tCKH'---------~

DIN7-0

REN,WEN

HIGH
IMPEDANCE

DOUT7-0

t~s
CLRCNT OR TOG

WEN

________

:Fc=-_:=-_:=-_::-_-_~_-_-_-_-_-_-~_-~*~---------------FIGURE 4: CRT 94C12 I/O TIMING

430

MAXIMUM GUARANTEED RATINGS

Operating Temperature Range .................................................................................0° to 70°C
Storage Temperature Range ......................................................................... - 55°C to + 150°C
Lead Temperature (soldering, 10 sec) ........................................................................... + 325°C
Maximum Vcc ...................................................................................................... +7.0 V
Positive Voltage on any Pin, with respect to Ground ........................................................ Vcc + 0.3 V
Negative Voltage on any Pin, with respect to Ground ............................................................ - 0.5 V
·Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.

ELECTRICAL CHARACTERISTICS (TA
PARAMETER

MIN

= DOC to 7DoC, Vcc =
TYP

+5V ±5%)

'".4""

""aLIAt
eo....~hllJot

_/hIIIi&~
COMMENTS
~~

MAX

UNITS

0.8

V
V
V

excluding RCLK; WCLK
RCLK,WCLK

0.4

V
V

IOL = 2mA
IOH = 100/-LA

10
10
400
400

/-LA
/-LA
/-LA
/-LA

excluding OE
excluding WEN1
WEN1
OE

pF
pF

excluding RCLK, WCLK
RCLK,WCLK

DC CHARACTERISTICS

INPUT VOLTAGE LEVELS
Low Level V,L
High Level V,H1
High Level V,H2
OUTPUT VOLTAGE LEVELS
Low Level VOL
High Level VOH
INPUT LEAKAGE CURRENT
High Leakage ILH1
Low Leakage tu
High Leakage ILH2
Low Leakage tL2
INPUT CAPACITANCE
C'N1
C'N2
POWER SUPPLY CURRENT
Icc

PARAMETER

2.0
4.2

2.4

10
15

MIN

TYP

40

mA

MAX

UNITS

COMMENTS

AC CHARACTERISTICS'

tevw
tCVR
tCKH
tCKL
tCKR
tCKF
tos
tOH
tEN12
tEN22
tENH2
tov
tcs
tCH
tWT3

250
250
100
100

DC
10
10

50
0
0
100
0
175
100
0

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Write clock period
Read clock period
measured from 10% to 90% points
measured from 90% to 10% points
referenced to WCLK
referenced to WCLK

CL = 50pF; referenced from RCLK

1tevw

1 - Reference points for all AC parameters are 2.4V high and 0.4V low. _ _
2 - For REN, referenced from RCLK; for WEN1 or WEN2 referenced to WCLK.
3 - At least 1 WCLK riSing edge must occur between CLRCNT or TOG (whichever occurs last) and WEN
(= WEN1-WEN2).

431

INTR

PROCESSOR

.oK
OMARQ
ADDR

DATA

•

DMAR

OS"

INT

GND

T

AOM
AAM

CRT 9007
VPAC'"

A

VIDEO RAM

+5V

VA13-0

ADDRESS BUS

MEMORY

I I I

RST

ACK

}~

AS
CBLANK

V07-0

r--

'is

16-BIT
DATA BUS

WBEN ORB

SLD

VLT

D
A
T
A

SLC

lr J

CURS

QA

s

"'"'

W£~

Tml

wcm

IIE~

m!CR

L....-1\

~D~
II

LD/§i

CRT 902119041
ATTRIBUTES CONTROLLER

CRT 94C12
OW>lI6·t

"I

ATTRIBUTES

OOUT/·8

'-------Y

OBoe

.llL~.L~

! !

j

74164

I

~

,~

OATA

B
U

0
A

CCLK

J ~r
CLOCK

I

VDC

+

OAB

EPROMIRAM-BASED
CHARACTER GENERATOR

00,"

A7·0

15·8

TO

VIDEO

MONITOR

Figure 5. VPAC Configuration With Quad Row Buffer

'NT'
PAOCESSOR

.oK
OMARa

ADD'

W,RD

DATA

I
OMAR

AOOABUS

MEMORY
ROM
RAM
VIDEO RAM
8·BIT

DATA BUS

ACK

t

j

1

CRT 9007
VPAC"

VA13-1

,~--~
-

HS
VLT

SLD

,

eLK

DATA

U

!

~

Va

}M

TO

ONITOR

~1: ac ao

I

-6

I

I

1 !

I~ ~ I§ I~

RENRro<"

O!N7-1

DC""~

A3 A2 Rl

~

---v

ATTl'lIBUTES

Alii

i

'§ ~

~

rlOh
DOT CLOCK,
GENERATOR

VDe

CRT 902119041
ATTRIBUTES CONTROLLER

CRT94C12
CRB

OIN15·8

CURS CCLK CBlANK

SLe

4+'

~

.

'NT

ov

RST +5\1

+

VIOEO

EPROMfRAM-BASED
CHARACTER GENERATOR
DOUTl5-8

------'\

---v

I

J
TO

MONITOA

A'"

Figure 6. VPAC Configuration With Quad Row Buffer For Attribute Assembly

STANDARD MICROS'iSTEMS
CORPORATION

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications: consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the right to
make changes at any time in order to improve design and supply the best product possible.

432

CRT97C11
PRELIMINARY

Video Engine For Windows
VIEW
PIN CONFIGURATION

FEATURES:

D 127 Independent Windows Max per Screen.
D Windows Specified Relative to Screen:
Window Number

x-v Start/End Screen Coordinate
x-v Display Memory Start Address
D Attributes can be Specified on a per Window Basis:

D
D
D

D

D
D
D

D
D
D

Window Priority
Up to B Parallel Attributes/Window Output by VIEW
Background windows
Three Internal Break Address Buffers.
32 Max Visible Horizontal Breaks per Scan Line.
Capable of Generating Screen Resolutions as High as
4K x 4K Pixels (assuming a 16 bit wide display
memory).
Private Display and System Buses:
20 Bit
Display Memory Address Bus + 4 Bit
Extended Bus
16 Bit Address/Data Bus to System Memory
Separate Clocks for Display and System Buses.
DMA Master Capability for Interfacing to System
Memory.
Automatic and Transparent Dynamic RAM Refresh for
Display Memory.
Programmable Cursor Output.
Fully Programmable Display Format.
Normal or Interlaced Video Output.

x-v

GND
AD1S
AD14
AD13
AD12
ADll
AD10
ADS
ADB
AD7
AD6
ADS
AD4
AD3
AD2
ADl
AD0

VDAll
VDA12/ATTR4
VDA13/ATTRS
HDAS/ATTR7
HDABIATTR6
HDA7
HDA6
HDAS
HDA4
HDA3
HDA2
HDAl
HDA0
BRKCHG

HS
\is
VDD

PACKAGE: 68·pin PLCC

D Horizontal and Vertical Drive Signals may be Externally
Synchronized.

D Compatible with 6BOXO and BOXB6 Processors.
D Low Power CMOS Technology.

GENERAL DESCRIPTION
The CRT97C11 Video Engine for Windows (VIEW) is a 3rd The VIEW generates display memory addresses by
generation CRT controller following the CRT50x7 family (1st correlating the X and V screen coordinates at which the
generation) and the CRT9007 (2nd generation). The VIEW windows start and end with the X and V display memory
is designed to support both bit-mapped graphics and addresses. The VIEW stores this information in its three
alphanumeric types of CRT displays. This devioe allows real internal break buffers. As the VIEW generates the display
time manipulation of independent, overlapping windows on memory addresses for the windows, it automatically
the screen with a minimum of processor intervention.
resolves priority conflicts that arise when two or more
The VIEW architecture provides the system designer with windows overlap.
a very high performance and extremely flexible method for Control of window position on screen, its size and priority
supporting the generation of windows on screen. The relative to other windows and the visible contents of the
performance advantage over designs which manipulate window are all accomplished via the simple manipulation
windows via software is significant. Windows On screen are of data in the window list in system memory. The VIEW
defined via a window list maintained in system memory by buffers and outputs general purpose attribute bits for each
the system microprocessor and acoessed by the VIEW chip. window as it generates that window's display memory
The VIEW chip is also able to access display memory data addresses. The VIEW automatically generates dynamic
via a separate memory bus which can be as wide as 24 bits RAM refresh addresses during the horizontal and vertical
retrace intervals.
providing a 16M word address range.
433

SCLK

RESET

INT

DCLK

ACK
RESET AND
INTERRUPT
LOGIC

DMAR

1-----1

Aj5,~

R1W-

SYSTEM
BUS
IfF

REGISTER
FILE AND
RASTER
GENERATOR

AEN--.

cs-

CBLANK
VLT
CURS

AD1S-0
BRKCHG
REFRESH
BREAK
PROCESSOR

r---t---------ATTR7-0
BREAK
BUFFERS f+----'--~I
VDA11-0
HDA7-0

VIEW FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION OF PIN FUNCTIONS
DISPLAY MEMORY BUS SIGNALS
PIN NO.
55-48

NAME
Horizontal Display
Memory Address

SYMBOL
HDA7-0

FUNCTION
Output. Eight bits of the Display Memory Address corresponding to the X portion
of the window's data address in display memory. HDA7 is the MSB and HDAO is
the LSB.
Output. Twelve bits of the Display Memory Address corresponding to the Y
portion of the window's data address in display memory. VDA11 is the MSB and
VDAO is the LSB.
Input. This signal is used to generate all Display Memory Bus cycles. A minimum
high voltage of 4.0V must be reached for proper operation.

60
62-68
1-4

Vertical Display
Memory Address

VDA11-0

42

Display Clock

DCLK

40

Visible Line Time

VLT

Output. This signal is active high for the visible (non-blanked) portion of every
horizontal period including the vertical retrace period.

8-5
58-59
57-56

Attributes

ATTR3-0
ATTR5-4/
VDA13-12
ATTR7-6/

Outputs. Four of these outputs (ATT3-0) are used as general purpose attributes
which are unique to each window being displayed. The other four outputs (ATT74) are used as either four additional attribute outputs or as address extension bits
for the Horizontal Display Memory Address (ATT7-6/HDA9-8) or the Vertical
Display Memory Address (ATT5-4NDA13-12). The functions served by ATT7-4
are determined by the contents of the Interrupt Enable/Mode Register (R17[1,0]).
Output. This signal is active high when the VIEW is generating dynamic RAM
refresh addresses for the display memory. The refresh address is output on the
Vertical Display Memory Address bus during the portion of the horizontal period
in which the video is blanked (when VLT is low).
Output. The active high state of this signal indicates that the next Display Clock
generates a new visible horizontal break.

HDA9~8

41

Refresh

RFRSH

47

Break Change

BRKCHG

VIDEO DRIVE SIGNALS
PIN NO.
46

NAME
Horizontal Sync

SYMBOL

45

Vertical Sync

VS

HS

FUNCTION
Input/Output. This signal initiates a horizontal retrace. Its position and pulse width
are programmable. After a hardware or software reset this Signal will behave as
an input. Programming this signal as an input allows the horizontal scan rate to be
synchronized to an external source. An external pullup resistor Will be required to
guarantee that this signal is inactive high after power-up.
Input/Output. This signal initiates a vertical retrace. Its position and pulse width
are programmable. After a hardware and software reset this Signal will behave as
an input. Programming this signal as an input allows the vertical scan rate to be
synchronized to an external source. An external pullup resistor will be required to
guarantee that this Signal is inactive high after power-up.

434

VIDEO DRIVE SIGNALS
PIN NO.
39

NAME
Composite Blank

SYMBOL
CBLANK

38

Composite Sync

CSYN

36

Cursor

CURS

FUNCTION
Output. This signal goes active high when a vertical or horizontal retrace is going
to be initiated. The signal stays active for the entire retrace. CBLANK is used to
blank the video to the CRT. The CBLANK signal can be skewed 0 to 3 DCLK's
with respect to the Display Memory Address and Attribute bus timings.
Output. This signal provides a true RS-170 composite sync waveform with
equalization pulses and vertical serrations in both interlace and non-interlace
formats. Figure 14 under Functional Description illustrates the CSYN output in
both modes.
Output. This signal is active high for the programmed number of DCLK periods on
each of the programmed scan lines (see descriptions of R11 thru R15). The
CURS output can be skewed 0 to 3 DCLK's from the Display Memory Address
and Attribute bus timing.

SYSTEM BUS SIGNALS
11-26

System
Address/Data Bus

AD15-0

Input/Output. These 16 signals are used by the system processor to access the
internal registers of the VIEW chip when it is in the peripheral mode. When in the
master mode then the VIEW chip controls the bus in order to access the window
list in system memory. Following a hardware or software reset the VIEW chip will
be in the peripheral mode.

28

Chip Select

CS

31

Address Enable

AEN

30

Read/Write

R/W

33

DMARequest

DMAR

35

DMA Acknowledge ACK

37

Interrupt

INT

34

System Clock

SCLK

Input. If VIEW is not performing a DMA cycle, the active low state of this input will
allow the system to clock data into or read data out of the internal VIEW registers
while the inactive high state of this signal will force AD15-0 into an input (high
impedance) state. A minimum high voltage of 4.0V must be output for proper
operation.
Input. When the VIEW is operating as bus master and performing a DMA cycle,
the active high state of this signal will enable the VIEW to output the System
Memory Address on AD15-0. The VIEW is not affected by the state of this input
unless it has received ACK and is performing a DMA cycle.
Input. This signal is used to qualify the CS input and determines whether the
system is writing data into (lOW state) or reading data from (high state) the VIEW
registers.
Output. This signal is driven active high by VIEW to request use of the System
Address/Data bus. It will only become active if the DMA Acknowledge (ACK)
input is inactive. It remains active high throughout the entire DMA operation.
Input. This active high signal acknowledges a DMA request. It is used to enable
the VIEW's DMA mechanism. The system should drive ACK inactive low after
DMAR is negated. The state of this signal will not affect VIEW operation unless
DMAR is being driven active high.
Output. This signal is driven active high when VIEW encounters an enabled
interrupt causing condition. This output is reset by reading the Interrupt Status
register or a hardware reset. NOTE: This signal should be connected to a level
sensitive interrupt input as no edge can be guaranteed between successive
interrupts. This output will be reset one full DCLK period after CS goes high after
an Interrupt Status 1 register read.
Input. This signal is used to generate all system DMA bus cycles. The rising edge
of this signal is used by the VIEW to clock in data from the system memory during
a DMA cycle. This signal may be "stretched" by the system to generate long read
cycles. A minimum high voltage of 4.0V must be output for proper operation.

29

Address/Data

AID

32

Reset

RESET

Input. When the VIEW is in the peripheral mode, this signal selects whether a
system bus access is to the Register Pointer Latch or to the register file.
Input. This active low signal puts the VIEW in a known, inactive state and resets
all raster counters. Activating this input has the same effect as executing the
software Reset command. The following VIEW signals will be left in the indicated
states:
-Input
VS
HS
-Input
VLT
-Inactive Low
CSYN -Inactive High
CURS -Inactive Low
RFRSH -Inactive Low
AD15-0 -Inputs
DMAR -Inactive Low
INT
-Inactive Low
CBLANK-Active High

435

Address
PROCESSOR

Data

Address
SYSTEM
MEMORY
(WINDOW LIST)

VIEW

TIMING

Data

ATTRIBUTES

Address

DISPLAY
MEMORY
(DISPLAY DATA)

Data

!
VIDEO
LOGIC

VIDEO

SCREEN

FIGURE 1-SYSTEM ELEMENTS
FUNCTIONAL DESCRIPTION
SYSTEM FUNCTIONS
A display system based on the VIEW must have a minimum
set of elements as described in the following sections. The
block diagram in Figure 1 provides a simple conceptual
illustration of the interconnection of these elements. The
sections below will define the purpose of these major
elements and also describe how they interact with each
other. The VIEW does not restrict the architecture chosen
in any particular way and choices made will be determined
by the overall system performance goals and cost
guidelines.
System Elements
The six blocks shown in Figure 1 are described below in
more detail. The interconnection of the blocks are
depicted in terms of the address/data buses or other
primary inputs or outputs. The details of the
interconnection will be determined by the memory
arbitration methods implemented and are not being
shown here.
a) Processor-The processor can be a system
microprocessor (such as the 8088, 80X86, 680XO,
etc.) that is responsible for all system functions or
a microprocessor dedicated to handling all display
and drawing related functions. The processor is
responsible for maintaining the window list in
system memory and the display data in display
memory. For bit mapped graphics applications,
overall performance could be improved if a special
purpose coprocessor is added to handle the
drawing related functions.
b) Window List~ The window list is maintained in

436

system memory by the processor. For a definit!on
of the window list and its contents see the section
on Screen Management below. The VIEW
accesses the window list in order to determine the
display memory address sequencing required to
generate the windowing effect on screen.
c) VIEW-The VIEW accesses data from the window
list processes it and stores it in internal buffers. The
VIEW chip performs all display memory addressing
in accordance with the data accessed from the
window list. The VIEW can perform both window
list and display memory access l?imultaneously. In
addition the VIEW generates video synchronization
signals which define the overall video format.
d) Display Data-The VIEW outputs addresses to
display memory in a sequence defined by.the
window list which automatically takes Into
consideration the overlapping of windows. Display
data is stored in memory by the processor in
individually allocated areas for each image. Display
data can consist of either bit-mapped images or
ASCII-based character data. Bit-mapped images
may be either Single-plane monochrome or multiplane color. Contention between the VIEW and the
processor for access to display memory must be
supported at the system design level.
e) Video Logic-This block performs all operations
necessary on the data output from display memory
before being output as a video signal to the screen.
If the data represents bit-mapped images then
some typical operations might be serial-to-parallel
conversion, color look-up and conversion to RGB
output, and other shift operations that may be

required to move images within a window. If the data
represents ASCII characters in an alphanumeric
only system then some typical functions would
include a character generator and attributes
controller. In addition the VIEW can output up to 8
attribute signals which are unique to each window
and may be used to control specific visual effects.
f) Screen-The output display device can be a CRT
or flat panel screen. The VIEW provides all the
timing signals required to·synchronize the display.
See Video Output section below for a more detailed
description of these outputs.
System Interaction and Timing
In order to address the problem of memory contention
between the processor, VIEW, system memory and
display memory, an understanding of the interaction
between these elements and their relative timing is
important. Whereas the processor can access only one
memory (system or display) at a time (unless two
processors are used in the system design), the VIEW is
capable of performing both memory accesses
simultaneously. Refer to Figure 1 while reading this
section.
Processor and system memory-Updates of the
window list will require activity on the bus between the
processor and system memory. This can occur at any
time due to operator input or commands received over
communications networks which are asynchronous to
the screen refresh process. Resolving contention
between the processor and the VIEW for access to
system memory can make use of the DMA handshake
signals provided by the VIEW (see the section on
System Interfaces below) or through the use of dual
port RAM's.
VIEW and system memory-VIEW accesses the
window list whenever it needs to fill its break buffers.
This is a periodic process only with reference to the
refre3h rate. During a given frame refresh the actual
timing of these events is determined primarily by a
Break Processing Delay parameter and the spacing
and number of vertical breaks on the screen. These
events always occur before data is needed for screen
refresh. See the section on Break Processing below.
Processor and display memory-As in the case with
activity between the processor and system memory,
update of display data is also driven by commands
received via operator input or over communications
networks. These events are asynchronous to the
screen refresh process. Support for resolving memory
contention must be implemented in external logic.
VIEW and display memory-VIEW accesses display
memory for the purpose of refreshing the screen
image. Therefore this activity is completely
synchronous with the video timing and is normally
considered the highest priority process within the
system.
DISPLAY OUTPUT AND STORAGE
The window list in system memory is used to define and
manage windows on screen and specify the data displayed
within the windows. The following sections describe the
parameters used and how screens and display memory are
organized.
Screen Management
The positioning and sizing of windows on a display screen
is defined through the use of X and Y coordinates (0, 0
is defined as the upper left corner of the screen). The
437

maximum values of these coordinates is determined by
the screen resolution which is defined by the contents of
the timing registers (see Operational Description). The
absolute maximum values, as determined by the sizes
of the coordinate fields in the window list, are 256 for the
X coordinate and 4096 for the Y coordinate. Figure 2
shows a screen with a single window in place. The actual
location of a window on the screen is determined by a
set of 4 coordinates. The left and right edges of the
window are defined by XSTART and XEND coordinates
and the top and bottom edges of the window are defined
by YSTART and YEND coordinates. The width and height
of the window is automatically determined from these
coordinates. The XSTART and XEND coordinates are
called horizontal breaks and the YSTART and YEND
coordinates are called vertical breaks (see Break/Link
Concept below). These coordinates are stored in the
window list data for. each window. Horizontally, the
spacing of each coordinate is determined by the display
data bus width, and vertically, the spacing of each
coordinate is one pixel (see the next two sections on
Display Memory Management and the Window List).
Display Memory Management
The images viewed through windows on the display
screen are determined by a two segment address. This
address points to a display memory location which
represents the upper left hand corner of the image that
appears in the window. The two segment address
consists of an X MEMORY ADDRESS and a Y MEMORY
ADDRESS. The amount of display memory required is
dependent on the application and is a function of the
number of independent images to be maintained in
memory at the same time and the image sizes to be
stored. The VIEW limits the X and Y addressing ranges
to 8 bits and 12 bits respectively. Each address segment
can be extended by 2 bits. Figure 3a shows a rectangular
view of display memory with the unextended limits of
addreSSing indicated. An image area is defined that
occupies memory from addresses (0,0) through (X1, Y1).
In order to determine what portion of this image will be
shown in a window on the screen, an address pointer
(X2,Y2) is defined that identifies the upper left corner of
the image data to be displayed. This pointer is the X
MEMORY ADDRESS and Y MEMORY ADDRESS data
stored in the window list. As shown in Figure 3b, each
memory location stores N bits of data which is determined
by the display memory data bus width.
Window List
The window list (described in detail below under Window
Management) contains 6 fields of information that define
the relationship between the window on screen and the
portion of the display memory image that is shown in the
window. As described above, four of the fields are
XSTART, XEND, YSTART and YEND which define the
position and size of the window on screen. A display
memory location (X MEMORY ADDRESS and Y
MEMORY ADDRESS) is defined for the upper left corner
of the window and all other memory locations are mapped
in direct correlation to the width and height of the window.
Figure 4 illustrates this relationship. The example shows
that the location of the window on screen and the location
of the image in memory are independent of each other.
The VIEW uses the X MEMORY ADDRESS and the Y
MEMORY ADDRESS plus the width and height (~X, ~ Y)
to determine the range of display memory addresses to
be generated. Figure 4 assumes N = 8 for the display data
bus width which results in a screen size of 1K x 1K pixels
and a window size of 256 x 256 pixels.

WINDOW MANAGEMENT
The window list is a contiguous set of 16 word blocks of
memory which define all parameters associated with each
window. A maximum of 127 windows can be defined in a
given window list. Up to 32 independent window lists can
X START
be maintained in memory at the same time (see R16[7,3] in
I
Operational Description section).
Window List Contents
Each window requires the definition of the following
parameters (see Figure 5 for the format):
WO: D15-D12-General Purpose Attribute Bits
The four attribute bits, D15 thru D12, are output on the
-VEND
ATTR3 thru ATTRO pins. These signals are general
purpose and are active during the time the VIEW is
XEND
generating display memory addresses forthe window
to which these attributes are assigned.
X START)
Y START
WO: D10-Background Window Tag Bit
X END
HORIZONTAL BREAKS
Y END
VERTICAL BREAKS
If this bit is set to a one, the associated window is
displayed as a background window. The VIEW will
FIGURE 2-WINDOW COORDINATES
generate the same display memory address for every
memory access in the window. The address generated
is that specified for the X and Y MEMORY ADDRESS
described below. If this bit is set to a zero, then all
X ADDRESS
addresses for this window are generated in the normal
x,
o
255
incrementing manner.
o
WO: D9-D8-General Purpose Attribute/X Address
.-----1
:
x, I
Extension Bits
Y
Depending on the programming of R17[0] these bits
! Y2
I
ADDRESS
I
I
are either General Purpose Attribute bits or X Address
---'
Extension bits. When they are programmed to be X
Address Extension bits, they function as the X Memory
,
Address MSB's (D9 is the MSB and D8 is the LSB).
\ . IMAGE AREA
When they are General Purpose Attributes, D9 is
DISPLAYED IN
output on ATTR7 and D8 is output on ATTR6.
A WINDOW ON SCREEN
FIGURE3b
WO: D7-DO-X Memory Address
These 8 bits correspond to the X portion of the
window's beginning address in display memory. D7 is
the MSB and DO is the LSB. The actual value that is
stored in this field depends on the type of window being
displayed (normal or background). For a normal
window a value equal to [X Memory Address-X Start
Break] should b'e stored (see Figure 4) and for
background windows the value stored should be equal
to [X Memory Address). Note that if the X Address
Extension is used, then the calculation should be
performed using the 10-bit value for X Memory
Address and both this field and the X Address
Extension field should be programmed with the result.
4095
Negative results should be represented in 2's
X,-X MEMORY ADDRESS
complement form.
Y,-Y MEMORY ADDRESS
W1: D13-D12-General Purpose AttributelY Address
Extension Bits
FIGURE 3a-DISPLAY MEMORY
Depending on the programming of R17[1] these bits
are either General Purpose Attribute bits or Y Address
Extension bits. When they are programmed to be Y
X,
X,+1
X,+2
Address Extension bits, they function as the Y Memory
Address MSB's (D13 is the MSB and D12 is the LSB).
When they are General Purpose Attributes, D13 is
output on ATTR5 and D12 is output on ATTR4.
Y'I--I
W1: D11-DO-Y Memory Address
These 12 bits correspond to the Y portion of the
Y+11--········x········X···4I
,
~.
window's beginning address in display memory. D11
N bits
I N = Display memory
Y,+ 2 I _ _ _
bus width
is the MSB and DO is the LSB. The actual value that
I
I
is stored in this field depends on the type of window
Y,+3 1 - - :
being displayed (normal or background). For a normal
L ____ L... _ _ _ _ _ _ _ _ .J
window a value equal to [Y Memory Address-Y Start
Break] should be stored (see Figure 4) and for
FIGURE 3b-DISPLAY MEMORY DATA
background windows the value stored should be equal
438

I

X COORDINATE

O--------------,~255

YSTART-O

I

;--

.

sL

i----1---1--1-1

I

SYSTEM MEMORY
WINDOW LIST
~

XSTART
XEND

}
}

= 40

= 72
= 400
= 656

YSTART
YEND

{

DISPLAY
MEMORY

X MEMORY ADDRESS

= 12

Y MEMORY ADDRESS

= 100

o ,0-,_57 2---,r-"-""T"""""T"n 255

~~
\

500

~

.-"L,,",

400

0

IZJ
_1
-r

71 SCREEN
DISPLAY
127

:+-IlX __ :

IlY

655
1023 ' - - - - - - - - - - - '

755

,....,

NOTE: 1. Assume N = 8 bits, then screen size is 1024 (128
and window size is 256 (32 8) x 256 pixels.
2. IlX and Il Yare not programmed values.

,-ow

4095

*

L -_ _ _ _ _ _ _- - '

*8) x 1024 pixels

FIGURE 4-MAPPING MEMORY TO SCREEN

D15
WO
WI
W2
W3
W4
W5
W6
W7
W8
W9
Wl0
Wl1
W12
W13
W14
W15

D14

D13

D12

Dll

Dl0

AT3 AT2 ATI
ATO
0
BK IX
0
IY EXT/AT5,41
0
0
0
0
0
0
INT
0
0
0 I
WINDOW #
0 I
X
X
X
X
X
X
WINDOW #
0 I
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INT
0
0
0 I
0 I
WINDOW #
X
X
X
X
X
X
0 I
WINDOW #
X
X
X
X
X
X

D9

D8

D7

D6

D5

D4

D3

D2

Dl

X MEMORY ADDRESS
Y MEMORY ADDRESS
0
0
0
0
0
0
I 0
Y START BREAK
PRIORITY
0
I
I 0
Y LINK
I
X START BREAK
I
X LINK
I
0
0
0
0
0
0
I 0
0
0
0
0
0
0
I 0
0
0
0
0
0
0
I 0
Y END BREAK
PRIORITY
0
0 I
I 0
Y LINK
I
X END BREAK
I
X LINK
I

DO

EXT/AT7,61

o

0

0

X

X

X
0
0
0

X
0
0
0

X

X

X

X

0

o

ISlE
I S/E
0

0
0

ISlE
ISlE

FIGURE 5-FORMAT FOR WINDOW LIST
interrupt after the end of a window on screen.
W3: 011-00, W11: 011-00-V Start/End Break
Coordinate
This 12-bit value defines a vertical coordinate which
corresponds to the scan line on which a window starts
or ends on screen. W3: 011-00 points to the start of
a window (VSTART = 400 in Figure 4), while W11:
011-00 points to the scan line after the end of a window
(VEND = 656 in Figure 4). 011 is the MSB and DO is
the LSB. The first break at the top of the screen is OOH
and the last is FFFH (assuming the full 12 bit
coordinate range is used). With a maximum value of
FFFH, the last displayable scan line for a window on
screen would be FFEH.

to [V Memory Address]. Note that if the V Address
Extension is used, then the calculation should be
performed using the 14-bit value for V Memory
Address and both this field and the V Address
Extension field should be programmed with the result.
Negative results should be represented in 2's
complement form.
W3: 014, W11: 014-Window Display Interrupt Tag Bit
If this bit is a one, the VIEW will generate an interrupt
(if enabled) during the blanking interval preceding the
scan line defined as the VSTART break or the VEND
break. W3 :014 provides an interrupt prior to the start
of a window on screen and W11 :014 provides an
439

I

W4: 014-08, W6: 014-08, W12: 014-08, W14: 014-08Window Number
This 7-bit value corresponds to the break's window
number and represents an offset into the full window
list at which all data relating to this window can be
found. 014 is the MSB and 08 is the LSB. The contents
of these four fields should be the same. Window
number DOH is reserved. See the section entitled
Window .List Addressing for mOJe details.
W4: 04-00, W12: 04-00-Priority
This 5-bit value represents this window's priority
relative to the other windows. This value is used by
VIEW to resolve which of two or more overlapping
windows will be displayed on a coordinate by
coordinate basis. The contents of these two fields
should be the same. 04 is the MSB and DO is the LSB.
NOTE: Two windows with the same priority cannot
exist on. the same scan line. This presents the
restriction that no more than 32 windows can overlap.
W5: 015-08, W7: 015-08, W13: 015-08, W15: 015-08Backward Link
This 8-bit value (marked by X's in Figure 5) is not used
by the VIEW and therefore could be used by the system
software for the purpose of defining a Backward Link.
The format of this parameter could be similar to that
of the XlY Link and StarVEnd Tag parameters defined
below (8 bits are reserved) or any other format dictated
by the system software. These bits are reserved for
this purpose and future versions of the VIEW will not
make use of them.
W5: 07-01, W7: 07-01, W13: 07-01, W15: 07-01-X/
YLink
This 7-bit value is a pOinter to the next break in
ascending coordinate sequence. The XIV link is
actually a window number which represents the next
window encountered when sequencing through the
windows along the coordinate axis. This value when
combined with the associated Start/End Tag bit
uniquely identifies the next break. 07 is the MSB and
01 is the LSB. See section on Break/Link Concept for
more detail.
W5: ~O, W7: ~O, W13: ~O, W15: ~O-Start/End Tag Bit
This one bit value indicates whether the window break
defined in the associated XlY Link is the start or the
end of the window. A value of "1" indicates the end of
a window and a value of "0" indicates the start of the
window.
W6: 07-00, W14: 07-DO-X Start/End Break Coordinate
This 8-bit value defines a horizontal coordinate which
corresponds to the column at which a window starts
or ends on screen. W6: 07-00 points to the start of a
window (XSTART = 40 in Figure 4) while W14: 07DO points to the memory word after the end of a
window (XENO = 72 in Figure 4).07 is the MSB and
DO is the LSB. The first break at the left of the screen

is DOH and the last is FFH. With a maximum value of
FFH, the last displayable memory word for a window
on screen would be FEH.
NOTE: The contents of words W2, W8, W9 and W10 are
not used by the VIEW and may be utilized by the system
processor to store other window related information.
Break/Link Concept
The VIEW accesses the window list in order to determine
the exact sequence of display ~emory addresses to be
generated to create the desired windowing effect on
screen. The VIEW makes use of both break and link
information contained in the window list in order to
traverse the list in the correct sequence. As the VIEW
traverses the list, it checks the priority and location of each
window to determine whether it is active for a given region
of the screen. A region is defined as that portion of a
screen between two vertical breaks. For each active
window the VIEW accesses the address information
found in the window list, performs calculations on it and
stores it in one of three internal break buffers. The
contents of the break buffers are then accessed
sequentially to generate the display memory addresses
required during the screen refresh period.
Breaks-Breaks are the screen coordinates, both
vertical and horizontal, at which windows start or end.
Figure 6 provides an illustration. Four windows are
shown with the X START and END COORDINATES
(horizontal breaks) identified at the top-O, 5, 9, 23,
35, 42, 60 and 100. The Y START and END
COORDINATES (vertical breaks) are identified at the
left-O, 70, 130, 290, 360, 440, 500.
Links-When processing the window list, the VIEW
makes use of a series of pointers that link the breaks
together in sequential order. The window list contains
two linked lists-one for vertical breaks and one for
horizontal breaks. The link parameter contains two
data items-a window number and a tag bit. Thf;!
HORIZONTAL BREAKS
0

23

0

I

70

--~

I

I

I

I

I
I
I

-----------.i-'--~~

350
440
500~

_ _ _ _ _ _ _ _ _ _ _WINDOW
_ _#4

FIGURE 6-WINDOW BREAKS

XSTART
XEND
VSTART
VEND
COORD LINK COORD LINK COORD LINK COORD LINK
WINDOW #1
43
3E
70
361
3E
9
2E
2S
WINDOW #2
1S
24
3S
130
441
4E
3S
5
WINDOW #3
4E
290
441
2E
35
1E
61
1E
WINDOW #4
101
00
1S
501
00
0
2S
0
FIGURE 7-WINDOW LINKS
440

100

WINDOW #1

WINDOW #2
290

60

---T---r----;

I
VERTICAL
BREAKS

42

_ _ _ _i-'

I
130

35

~

window number identifies which window is
encountered next when sequencing through the
breaks. The tag bit identifies whether it is the start ("5")
or end ("E") of the window. (See the section under
Window List Contents for a definition of these data
items.) Figure 7 lists all the breaks and links for the
example shown in Figure 6. End breaks in Figure 6
represent actual coordinates of last scan line or last
display memory word for each window while in Figure
7 each end break value stored in the window list is one
more than defined in Figure 6. The VIEW starts
processing breaks at the upper left corner of the screen
(see Break Processing below), which in this example
is window 4. The following list describes the breaks
and links along the horizontal axis for this example.
• Break "O"-Coordinate for start of window 4.
• Link "2S"-Pointer to the start of window 2.
• Break "5"-Coordinate for start of window 2.
• Link "15" -Pointer to the start of window 1_
• Break "9" -Coordinate for start of window 1.

• Link "2E" -Pointer to the end of window 2.
• Break "2:4"-Coordinate for end of window 2.
• Link "35" -Pointer to the start of window 3.
• Break "35"-Coordinate for start of window 3.
• Link "1 E"-Pointer to the end of window 1.
• Break "43"-Coordinate for end of window 1.
• Link "3E"-Pointer to the end of window 3.
• Break "61 "-Coordinate for end of window 3.
• Link "4E"-Pointer to the end of window 4.
• Break "101 "-Coordinate for end of window 4.
• Link "00"-Terminator for end of horizontal breaks.
As shown, a special link, or terminator, equal to "00"
is used to indicate the last break in the sequence. A
similar sequence exists for the vertical breaks. The
VIEW uses the two independently linked lists to
perform the break processing described in the next
section. It is the responsibility of the window
management software to create and maintain these
links in the window list in system memory when
manipulating windows on screen.

HORIZONTAL BREAKS

o

o

23

42

35

60

100

Y

----

70
WINDOW #1

130

I

290

H

360
44 0

3

-- ../

4

/'

5

~

6

I-~~~

WINDOW #3

WINDOW #4
500

1

""

---------

WINDOW #2

VERTICAL
BREAKS

' " REGION

2

COORD

ACTIVE
WINDOWS

069
70129
130289
290360
361440
441·
500

BREAK
BUFFER

4

1

1.4

2

1.2.4

3

1.2.3.4

1

2.3.4

2

4

3

1/

FIGURE 8-BREAK PROCESSING EXAMPLE

FRAME
REFRESH

BUFFER
USED ,,..

I

FRAME
REFRESH

BREAK
PROCESSING

BUFFER
USED

ACCESS
TIME

REGION 6

3

39 SCLK's

® lAST BREAK PROCESSED

10 SCLK's

BREAK DELAY (R10)

® REGION 1}

REGION2 @
REGION 3

VERTICAL
RETRACE

1
2
3

44 SCLK's
39 SCLK's
39 SCLK's

@..Q

FRAME
REFRESH

REGION 1

1

70

REGION 2

2

130

REGION 3

3

REGION 4
REGION 5

1
2

290
360
440

REGION 6

3

500

39 SCLK's

REGION4 @

I

(f)

-

REGION5 @

2

42 SCLK's

REGION6 @

3

39 SCLK's

LAST BREAK PROCESSED @

10 SCLK's

BREAK DELAY (R10)
REGION 1

,.1.

FIGURE 9-BREAK PROCESSING TIMING
441

39 SCLK's

Break Processing
For each screen refresh, the VIEW accesses the window
list by reading all vertical breaks for each region of the
screen (more than one vertical break in a region is
possible if multiple windows either end or start on the
same scan line) and then reading all horizontal breaks.
When reading the horizontal breaks, the VIEW processes
the address and attribute data for each active window
and stores this data in the next available break buffer.
Figure 8 and 9 will be used to illustrate this process. Figure
8 repeats the same scre~n layout as shown in Figure 6
and adds four columns which identify the region, the
range of Y coordinates for that region, active windows in
that region, and the break buffer used to store data for
that region. Figure 9 illustrates the timing of the window
list accesses and the break buffer activity for a single
frame refresh period.
During a given frame refresh, the Last Break Processed
interrupt will occur when the vertical break for the end of
the screen is processed (!). At this time the VIEW will not
attempt to start break processing for the next frame
refresh until after the Start Delay (see R10[5,0]) timeout
has terminated ®. This timeout may occur before or after
the start of vertical retrace and is strictly a function of the
Start Delay parameter and when the Last break
Processed interrupt occurs. This delay allows time for
the processor to manipulate the window list. At this time
the VIEW will request access to the system bus by
activating the DMAR signal. When the ACK signal is
activated, the VIEW will process the first four vertical
breaks which provides all the data needed to refresh
these regions on screen ®. When frame refresh starts,
the VIEW will make use of the data in break buffer 1 to
refresh the first region on screen @. At the completion of
this period, the contents of break buffer 1 are no longer
needed and the VI EW processes the next vertical break
(between vertical coordinates 29 and 36-region 4). The
data for refreshing region 4 is now placed in break buffer
1 ®. Similarly, at the completion of the refresh of regions
2,3 and 4, break buffers 2, 3 and 1 become available and
the VI EW processes the breaks for regions 5 and 6 and
stores this data in break buffers 2 and 3 and then
processes the last break, represented by the Y break at
coordinate 500 (no break buffer is required in this case) @.
Once again the VIEW will generate the Last Break
Processed interrupt and the entire cycle will start
again ®.
Figure 9 also shows the amount of time that the VIEW
takes to perform the break processing. This time is
measured in SCLK's. The formula to calculate this timing
is as follows8W + 3Y + 4
where W = Number of total windows (for the
example in Figure 6, W would equal
4 for all regions).
Y = Number of vertical breaks with the
same break coordinate (start or end)
for a given region. For the example in
Figure 6, Yequals 1 for regions 1, 2,
3, 4, 6 and Y equals 2 for region 5.
Y = 2 for region 5 because windows
2 and 3 end on the same scan line
(same Y break coordinate).
Three special conditions exist with respect to the above
calcuation.

then the formula is modified as follows3Y + 7
2) If the break being processed is the first break (break
which represents the first scan line on the screenRegion 1 in the example), then the formula is
modified as follows8W + 3Y + 9
3) If the break being processed is the first break after
the VIEW has been given a Start command, then
an additional 2 SCLK's should be added to the
result.
Window List Addressing
As indicated above, each window is defined by the
parameters stored in a 16 word block of system memory.
In addition to the 127 blocks of system memory required
to define all possible windows (numbered 1 through 127),
there is also a block reserved for window # 0 that serves
a special purpose. When the VIEW processes breaks for
the next frame refresh, it starts with the block that defines
the first window to be encountered at the upper left corner
of the screen. The pointer to that block is found in the first
two words of the block for window # O. Figure 10 shows
the contents of this special block of data. The LSB of the
first word identifies the X START LINK and S/E tag bit
and the LSB of the second word identifies the Y START
LINK and S/E tag bit. All other bits in this block of memory
should be reset. These two link parameters define the
entry points to the linked lists for vertical and horizontal
breaks.
The address generated by the VIEW for accessing the
window list consists of three segments (see Figure 11).
The 5 MSB's (AD15-11) are defined by the contents of
the Window List Start Address found in register (R16[7,3]).
This base address allows the VIEW to access up to 32
independent window lists. The next 7 bits (AD10-4) are
defined by the specific window number which is included
in the data accessed from the window list. The 4 LSB's
(AD3-0) are the offset within each window list which
points to a specific data item.

SYSTEM INTERFACES

System Memory
The VIEW operates in two modes-peripheral and
master. Following a hardware RESET or a software Reset
command, the VIEW will be in peripheral mode. In this
mode, the processor can access the..YIEW's internal
registers by means of the CS and R/W inputs. After a
Start command, the VIEW will begin to generate DMA
requests. When it receives a DMA acknowledge from the
processor, the VIEW will operate in bus master mode (see
Figure 12). In this mode, the VIEW will use its DMA
circuitry to request the use of the system bus from the
permanent master (typically the system processor) when
it needs to fill its break buffers. When the VIEW disables
its DMA request, it will again revert to peripheral mode
(see Figure 13). Table 1 defines the activity on the System
Address/Data Bus for the control signal states shown.
After processing the last break for a given frame refresh,
the VIEW will wait the period of time specified in the Start
Delay register before it starts to access system memory
again. After this time, the VIEW will start to load the break
buffers for the first break of the next frame refresh. This
feature prevents system memory access conflicts as it
provides the processor with a window of programmable
length in which it can address the VIEW as a peripheral,
1) If the break being processed is the final break (break
disable the VIEW's DMA mechanism, access the internal
which represents the last scan line on the screen),
registers and access the window list in system memory.
442

ADDRESS

WINDOW  DATA
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
1
2
3
4
5

6
7
8
9
10
11
12
13
14
15

14 13 12
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0

11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

~I 7

6

0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0

5 4 3
X START LINK
y START LINK
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0

2

1

0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0

0
0

0
ISIEI'
ISIEI'
0
0
0
0
0
0
0
0
0
0
0
0
0
0

FIGURE 10-WINDOW  CONTENTS
NOTE: 1 Both SIE tag bits should be set equal to zero because the first window boundaries
encountered will always be the start of a window.

AD15 •
• AD11
WINDOW LIST START
ADDRESS

I AD10 •WINDOW NUMBER • AD41

AD3--AD0
LIST DATA
POINTER

FIGURE 11-WINDOW LIST ADDRESSING

PERIPHERAL MODE:

READ VIEW REGISTER

WRITE TO VIEW REGISTER

R/W _ _ _ _ _ _ _ _ _ _

~D

XXXXX

XXxxxxx
\,------,1

cs
AD7.0

~

==x'-___

XX
\I......----JI
X~_R_E_AD_D_Al:_A_ _

WR_IT_E_D_Al:_A_ _.....
X...........
X ........
X ........
X ......
X ......
X ......

MASTER MODE:

SCLK

~

AEN~
AD15·0

~
I•

I

\

I

\
ADDRESS OUT

X
ONE DMA CYCLE

DATA IN

X

•I

FIGURE 12-VIEW PERIPHERAUMASTER MODE

443

ADORESS

It' displ~y memory is impl~mented using DRAM's, then
the VIEW supports the refresh of memory through the
use of an internal twelve bit binary counter. The outputs
of this counter are used to drive the Vertical Display
Memory Address bus (VDA11-0) during the portion of the
horizontal period in which the video is blanked (when VLT
is low). The counter is incremented by the DCLK signal
the number of times specified by the Memory Refresh
Count register during each horizontal blanking interval
(for the entire vertical period). The counter is set to zero
(counting is inhibited) by a software Reset command or
a hardware RESET. The counter can also be disabled at
any time by setting the Memory Refresh Count register
to zero. The counter will not initiate the counting sequence
until the VIEW receives a Start command. The VIEW
drives the RFRSH output active high when it is driving
the VDA 11-0 bus with the counter output. To take
advantage of the VIEW's refresh function, the VDA11-0
bits should be used for the DRAM row address.

The VIEW will tri-state its System Address/Data bus
(AD15-0) when it is not performing a DMA cycle and when
it is not selected (CS in its inactive state) for register
access. The processor can also disable the DMA
mechanism by issuing a STOP command. In ,this case
the VIEW will not access system memory again until a
START command is issued. However, the VIEW will
continue to refresh the display memory if transparent
refresh is enabled.
Display Memory
The VIEW addresses display memory as a rectangular
memory space with a two segment address-8 bits for
the horizontal range (HDA7-0) and 12 bits forthe vertical
range (VDA11-0). Each segment can be independently
extended by two bits (see description of General Purpose
Attribute Bits below). The logic required to support the
RAS/CAS address generation (required when using
DRAM's) and to arbitrate display memory accesses must
be implemented externally.
VALID

VALID

VALID

READ
DATA

READ
DATA

READ
DATA

SCLK

DMAA

-t--.....J

AEN

ACK_+-_ _....J

AD15-0 8....!L:.::..._ _JY:.MJ!..:.:::.::...!l..::=-.J.L.::'::...L>...:::.::....._ _ _...1i-=....l!.:.=IYJI.IQll,CJI::l.IMo~_:.'N:P..:UT:......_ _
PERIPHERAL
MODE

FIGURE 13-VIEW DMA CYCLE

MODE

R/W'

CS'

ADR

DMAR

ACK

AEN

AD15 - AD8

PERIPHERAL
PERIPHERAL
PERIPHERAL
PERIPHERAL
PERIPHERAL
PERIPHERAL
PERIPHERAL
PERIPHERAL
PERIPHERAL
PERIPHERAL
MASTER
MASTER

1
1

0
0
0
0
0
0
0
0

0

0

1

0

0

X
X
X
X

X
X
X
X
X
X
X
X
X
X
0

X
X
X
X
X
X
X
X

1
1
1
1

0
0
X
X
X
X
0
X

X
X
X
X
0
0
0
0
X

0
0
1
1

0
0
X
X
X
X

1

0
1

0
1

1
1

0
1
1

1

SYSTEM ADDRESS/DATA BUS
TABLE 1

444

AD? - ADO

READ REG FILE
READ REG POIN TER
WI=!ITE REG FILE
WRITE REG POIN TER
READ REG FILE
READ REG POIN TER
WRITE REG FILE
WRITE REG POIN TER
HIGH IMPEDANCE (INPUT) STATE
HIGH IMPEDANCE (INPUT) STATE
HIGH IMPEDANCE (INPUT) STATE
DMA ADDRESS (OUTPUT)

Video Output
Cursor Control
The VIEW provides a cursor output (CURS-pin 36)
with separate programmable X and Y start and
duration values. The cursor output will become active
when the value programmed in the Horizontal Cursor
Position register is equal to the X component of the
raster counter and the value programmed in the
Vertical Cursor Position register is equal to the Y
component of the raster counter. It will remain active
for the number of DCLK periods specified in the
Horizontal Cursor Duration register before returning
to its inactive state. The cursor output's action will be
repeated on the scan lines following the one specified
in the Vertical Cursor Position register for the number
of scan lines specified in the Vertical Cursor Duration
register.
As the Horizontal and Vertical Cursor Position registers
are changed, the information read from the Interrupt
Status register will indicate in which window the cursor
resides. This is determined by the location of the upper
left corner of the cursor block as specified in the
Horizontal and Vertical Cursor Position registers. If
the cursor position registers place the cursor
simultaneously in two or more overlapping windows,
the status will report it as being in the window with the
highest priority.
Window Attributes
Unique attributes can be specified for each window.
Two types of attributes are used internally by the
VIEW-the window interrupt tag bits and a
background window tag bit. There are also eight
general purpose attribute bits. All of these bits are
accessed by the VIEW during break processing and
stored internally in break buffers.
Window Interrupt Tag Bits
Two interrupt tag bits are assigned to each window.
When either of these bits are set and the Y Break
Interrupt Enable bit (R17[4]) is set, an appropriate
interrupt will be generated by the VIEW during the
horizontal retrace period. The tag bit associated
with the Y Start break will cause an interrupt to be
generated during the horizontal retrace period prior
to the first scan line of the window. The tag bit
associated with the Y End Break will cause an
interrupt to be generated during the horizontal

retrace period following the last scan line of the
window. The timing of these interrupts is
independent of whether the first or last scan lines
of the window are obscured by a higher priority
window. See discussion of R17[4] in Register
Descriptions section and W3: 014 and W11 : 014 in
the Window List section.
Background Window Tag Bit
See description of this bit (WO: 010) in the section
on the Window List.
General Purpose Attribute Bits
The eight general purpose attribute bits do not
affect the internal operations ofthe VIEW, however
they are read and output on the ATTR7-0 pins
during the time the VIEW is generating display
memory addresses associated with that window.
The functionality of four of the eight attribute bits
can be programmed by the Attribute Select bits in
R17[1,0] (see Register Descriptions section).
Independently, two of the bits can be programmed
to extend the Horizontal Display Memory Address
and the other two can be programmed to extend
the Vertical Display Memory Address.
Horizontal and Vertical Sync
The horizontal and vertical synchronization outputs are
programmable with respect to their pulse width and
position relative to the horizontal and vertical visible
display times. See Figure 14 for typical waveforms in
interlaced and non-interlaced modes. They can also
be configured so as to allow external signals to initiate
horizontal and vertical retrace cycles. If the external
horizontal sync is enabled and an external signal drives
the AS input low, the VIEW will initiate a horizontal
retrace cycle on the leading edge of the second DCLK
pulse following AS going low. This will lock the VIEW's
horizontal frequency to that of the external signal. If
the external vertical sync is enabled and an external
signal drives the 'i7S input low, the VIEW will initiate a
vertical retrace cycle on the leading edge of the next
AS pulse. This will lock the VIEW's vertical frequency
to that of the external signal. When external sync is
enabled, the vertical and horizontal periods must be
programmed to be the same as the master sync
generator. Note that it is possible for the first frame to
be out of sync in interlace mode.

PROG

~~~~~11-

F6~Lf

{cv:
INTERLACED
_

vs-------:3~IS~CA~N~L~INE~S~B~EF~O~RE~V~S~\~PRcRO~G~V~SvrnNccw~lrrDT~H~~il3~SC~A~N~LlN~E~S~AF~TE~RGV~i-----

~~I§

{cv:
INTERLACED
_
v s - - - - - - - - - - - - - - - - - ,__________

r--------------

HS
NON.
INTERLACED

{CYSN
_
v s - - - - - - - - - - - - - - - - - c________~r--------------

FIGURE 14-TYPICAL SYNC WAVEFORMS FOR INTERLACED AND NON-INTERLACED MODES
445

OPERATIONAL DESCRIPTION
REGISTER ACCESSIBILITY
Figures 16 and 17 illustrate the bit layout of all addressable
registers within the VIEW. Access to these registers takes
place over the System Address/Data Bus (AD15-0). Specific
registers are selected for reading and writing by means of
a Register Pointer Latch. Data transfers to and from the
registers takes place over the 8 LSB's of the address/data
bus (AD7-ADO, see Table 1). Control over the access to both
the register§. and the Regj§!!lr Pointer Latch is accomplished
via the A/D, R/W and CS inputs (see Table 2). These
registers should not be accessed during a DMA cycle
(DMAR and ACK both active).
AID

0
0
1
1

RlW
0
1
0
1

FUNCTION
Write to register in register file
Read register in register file
Write to Register Pointer Latch
Read from Register Pointer Latch

TABLE 2-ACCESS TO VIEW REGISTERS
The Register Pointer Latch is 8 bits wide (Fig. 15). The five
LSB's are used to select the desired register. The three
MSB's are used to initiate Start, Stop and Reset commands
via software. The allowable combinations of bit settings for
the Register Pointer Latch are shown in Fig 15
D7
D6
D5
D4 D3 D2 D1 DO
RESET STOP START REGISTER NUMBER FUNCTION
1
0
0
X X X X X RESET
1
0
0
X X X X X STOP
0
1
X X X X X START
0
0
0
0
- N - - ACCESS
REGISTER
N
X-Don't care
N-Register address

FIGURE 15-REGISTER POINTER LATCH

NOTE: A minimum delay of 4 full SCLK
periods is required between a Stop, Start, or
Reset command or a hardware Reset and
writing to the VIEW registers. The clock
periods are counted starting with the first
rising edge of SCLK following the rising edge
ofCS.
RO

D7

1 D6 1 D51D41D31 D2 1 D1 1 DO
HORIZONTAL CYCLE MSB'S

R1

HORCYI
LSB

R2

INTER I
MODE

R3

HORIZONTAL SYNC WIDTH
HORIZONTAL DELAY
HORIZONTAL VISIBLE

ISCAN I EXT SYNC
MODE ENABLE
R5
VERTICAL CYCLE MSB'S
R6
VERTICAL SYNC WIDTH
R7
VERTICAL DELAY
R8
VERTICAL VISIBLE LSB'S
R9 VERTICAL VISIBLE MSB'S IMEMORY REFRESH COUNT
R10 BLANKSKEWI
START DELAY
R4

R11
R12
R13
R14
R15
R16
R17

VERTICAL CYCLE LSB'S

CURl HORIZ CURSOR DURATION
CURS SKEW IVDUR
MSB
VERTICAL CURSOR DURATION LSB'S
HORIZONTAL CURSOR POSITION
VERT CURSOR POS MSB'S 1
VERTICAL CURSOR POSITION LSB'S
WINDOW LIST START ADDRESS 1 0 1 0 1 0
INTERRUPT ENABLE
1ATIRSEL

FIGURE 16"':"VIEW REGISTERS (WRITE)

D7 1 D6 1 D51D41D31 D2 1 D1 1 DO
Executing one of the three commands requires the exclusive
setting of one of the three MSB's. When accessing a register RR17
INTERRUPT STATUS 1
all three MSB's must be reset. Execution of the commands RR18
INTERRUPT STATUS 2
causes the following actions to take place:
HORIZONTAL CURSOR POSITION
RR13
RESET: Writing this command will cause the VIEW to RR14 VERT CURSOR POS MSB'S 1
respond exactly as though the Reset pin was
VERTICAL CURSOR POSITION LSB'S
strobed. All raster counters will be reset and the RR15
signals listed below will be left in the states
FIGURE 17-VIEW REGISTERS (READ)
indicated:
REGISTER DESCRIPTIONS
VS
-Input
TIMINGHORIZONTAL
HS
-Input
VLT
-Inactive Low
HORIZONTAL CYCLE (9 Bits-RO[7,O), R1 [7])-Write
CSYN
-Inactive High
only.
CURS -Inactive Low
Defines the horizontal period length (visible and
RFRSH -Inactive Low
blanking time). This field should be programmed with
AD15-0 -Inputs
the total number of DCLK periods in the entire
DMAR -Inactive Low
horizontal period minus four times the number of
INT
-Inactive Low
DCLK periods specified for the Horizontal Sync Width
CBLANK-Active High
(see Figure 18).
HORIZONTAL SYNC WIDTH (7 Bits-R1 [6,O])-Write
STOP: Writing this command will cause the VIEW to
,:lisable its DMA circuitry and drive its CBLANK
only.
signal active high. The VIEW will not initiate a
Defines the duration of the Horizontal Sync signal
(HS). This field should be programmed with the
DMA request again or drive the System Address/
number of DCLK periods that compose the horizontal
Data bus until it receives a new Start command.
Horizontal and vertical sync generation will not
synchronization pulse (see Figure 18). The minimum
value is3.
be affected.
HORIZONTAL DELAY (7 Bits-R2[6,O])-Write only.
START: Writing this command will cause the VIEW to
Defines the delay between the start of the Horizontal
initiate its" internal operations by starting its raster
Sync signal and the start of the next visible scan line.
counters and filling its break buffers. The VIEW
This field should be programmed with N - 3 where N
always generates even field raster addresses
following a Reset command.
is the number of DCLK periods between the beginning
446

of the HS signal and the leading edge of the VLT signal.
If this register is programmed with a value that is
greater then the horizontal blank interval, the
horizontal sync pulse will begin before the horizontal
blank interval yielding a negative "front porch" (see
Figure 18). The minimum value is 1.
HORIZONTAL VISIBLE (8 Bits-R3[7,OJ)-Write only.
Defines the length of the visible portion of the total
horizontal period. This field should be programmed
with N - 1 where N is the number of DCLK periods that
the display is not blanked during the horizontal period
(see Figure 18).
NOTE: VIEW requires that the display must be
blanked a minimum of 11 DCLK periods
(interlaced display) or 7 DCLK periods
(non interlaced display) in a Horizontal
Cycle.
VERTICAL TIMINGVERTICAL CYCLE (13 Bits-R5[7,O], R4[7,3J)-Write
only.
Defines the vertical period length (visible and blanking

time). This field should be programmed with 6 less than
the total number of scan lines in the total vertical period
(see Figure 19).
VERTICAL SYNC WIDTH (8 Bits-R6[7,OJ)-Write only.
Defines the duration of the Vertical Sync signal (VS).
This field should be programmed with the number of
horizontal periods (scan lines) that compose the
vertical synchronization pulse (see Figure 19).
VERTICAL DELAY (8 Bits-R7[7,OJ)-Write only.
Defines the delay between the beginning of the Vertical
Sync signal and the end of the vertical blanking
interval. This field should be programmed with N - 2
where N is the number of horizontal periods (scan
lines) between the beginning of VS and the falling edge
of vertical blanking (see Figure 19).
VERTICAL VISIBLE (12 Bits-R9[7,4], R8[7,OJ)-Write
only.
Defines the length of the visible portion of the total
vertical period. This field should be programmed with
N - 1 where N is the number of horizontal periods
(scan lines) that the display is not blanked during the
vertical period (see Figure 19).

~

1 SCAN LINE

1..' ' ' ( . - - - - - - HORIZONTAL CYCLE ------~
1....1 - - - - HORIZONTAL VISIBLE

..

ACTIVE DISPLAY TIME
VLT - - - - - - - '

I..

I

I

~

HORIZONTAL
DELAY

HORIZONTAL
BLANKING'

I

~

I
I·

I
·1

HORIZONTAL SYNC WIDTH
NOTE: 1. This value is not programmed, however it can be calculated from the other programmed parameters.

FIGURE 18-VIEW HORIZONTAL TIMING

1:_------

1 COMPLETE FRAME

~I

VERTICAL CYCLE - - - - - - -..

""'(.---- VERTICAL VISIBLE

VERT BLANK'------,

.."'---.. ~:---I
.

----!~~I

I

I

~I

VERTICAL
DELAY
VS

~"""-t--~-_~

I

lL___---'

VERTICAL
BLANKING 2

I

,....---

L..-_ _ _.....

I..

~I

VERTICAL SYNC WIDTH
NOTE: 1. This signal not available externally.
2. This value is not programmed, however it can be calculated from the other programmed parameters.

FIGURE 19-VIEW VERTICAL TIMING
447

VLT

I

HORIZ BLANK'

I

I

I

I
I
I

I

I

I
I

I
I
I
I

BLANK

I
I

I

I

FIGURE 20.8-HORIZONTAL TIMING: SKEW

VLT

I

~TSKEW

HORIZ BLANK'

I

I

VISIBLE

BLANK

=0

I

I

I

PROGRAMMED

BLANK

I

VISIBLE

I

BLANK

L

NOTE: 1. This signal not available externally.

FIGURE 20b-HORIZONTAL TIMING: SKEWoF- 0
CURSOR CONTROLHORIZONTAL CURSOR DURATION (5 BitsR11[4,0])-Write only.
Defines the active time per scan line of the Cursor
(CURS) output pulse. This field should be
programmed with the number of DCLK periods that
the output is active high. The specific scan lines on
which the CURS signal will be activated is determined
by the contents of the Vertical Cursor Duration and
Position fields. This parameter defines the width of the
cursor rectangle on the screen.
VERTICAL CURSOR DURATION (9 Bits-R11[5],
R12[7,0])-Write only.
Defines the active time per vertical period of the Cursor
(CURS) output pulse. This field should be
programmed with the number of scan lines that the
output is active high. This parameter determines the
height of the cursor rectangle on the screen.
HORIZONTAL CURSOR POSITION (8 Bits-R13[7,0),
RR13[7,0])-ReadIWrite.
Defines the absolute horizontal coordinate relative to
the visible portion of the screen when the Cursor
(CURS) output will go active high. This field should be
programmed with the X coordinate of the upper left
corner of tbe cursor rectangle.
VERTICAL CURSOR POSITION (12 Bits-R14[7,4],
R15[7,0), RR14[7,4), RR15[7,0])-Read/Write.
Defines the absolute vertical coordinate relative to the
visible portion of the screen when the Cursor (CURS)
output will go active high. This field should be
programmed with the Y coordinate of the upper left
corner of the cursor rectangle.
CURSOR SKEW (2 Bits-R11 [7,S])-Write Only.
These bits define the number of DCLK periods that
the CURS output Signal is delayed (skewed) from the
Display Memory Address corresponding to the cursor
position. If zero skew is specified, the CURS output
will be active when the VIEW generates the addresses
in direct relation to the cursor position. The maximum
cursor skew is three.
448

MISCELLANEOUS CONTROLBLANKING SKEW (2 Bits-R10[7,S])-Write only.
These bits define the number of DCLK periods that
the horizontal blank component of the CBLANK signal
is delayed (skewed) from the VLT signal as shown in
Figure 20b. If, as shown in Figure 20a, zero skew is
specified, the edges of the horizontal component of
CBLANK will coincide with the edges of VLT. The
maximum blanking skew is three.
WINDOW LIST START ADDRESS (5 Bits-R1S[7,3])Write only.
Defines the 5 MSB's of the memory address generated
by the VIEW to access the Window List in system
memory. This base address allows the VIEW to
maintain up to 32 Window Lists in memory at the same
time.
SCAN MODE (1 Bit-R4[2])-Write only.
Defines which scan mode will be used by the VIEW
for generation of timing signals and Display Memory
Addresses. If this bit is reset then non-interlaced mode
(even and odd scan lines displayed sequentially in one
field) will be used and if set then the interlaced mode
(see Interlace Mode register) will be used.
INTERLACE MODE (1 Bit-R2(7)-Write only.
Defines which interlace mode will be used when the
Scan Mode bit is set (R4[2) = 1). If this bit is reset
(R2[7) = 0) then the normal interlaced mode is enabled
which will cause the odd scan lines to be displayed in
odd fields and even scan lines to be displayed in even
fields. If this bit is set (R2[7) = 1) then the enhanced
interlace mode is enabled which will cause the even
and odd SCan lines to be repeated on successive scan
lines for both even and odd fields.
EXTERNAL SYNC ENABLE (2 Bits-R4[1,0])-Write
only.
Defines whether sync outputs are generated internally
or triggered by external signals. R4(1) defines the
source of the Vertical Sync signal (R4[1) = 0 - internal,
R4(1) = 1 - external). R4[O)defines the source of the
Horizontal Sync signal (R4[O) = 0 - internal, R4[O) = 1
- external).

MEMORY REFRESH COUNT (4 Bits-R9[3,0])-Write
only.
Defines how many sequential Display Memory
addresses will be generated by VIEW for transparent
refresh of dynamic RAM's during the horizontal retrace
interval (when the VLT output is inactive low). Bit 3 is
the MSB and bit 0 is the LSB. Setting these bits to zero
will disable the refresh counter. These bits are reset
by a hardware Reset or software Reset command.
START DELAY (6 Bits-Rl0[5,0])-Write only.
Defines the number of scan lines the VIEW will wait
after accessing the Window List in system memory for
the last break. The VIEW will not access the Window
List again until this count expires at which time the
VIEW will begin processing data again for the first
break of the next frame refresh. Bit 5 is the MSB and
bit 0 is the LSB. See section on Break Processing
under Functional Description.
ATTRIBUTE SELECT (2 Bits-R17[1 ,O])-Write only.
Defines the functionality of the VIEW's ATTR7-4
general purpose Attribute output pins. The
programming of these bits will determine whether
these outputs function as attribute information or as
extension bits to the Display Memory Address bus.
See Table 3 for programming of these bits and the
Functional Description section for an explanation of
functions associated with these outputs.
VIEW
OUTPUT
ATTR7
ATTR6
ATTR5
ATTR4

ATTRIBUTE SELECT
R17[O] = 1
X ADDR EXT MSB
X ADDR EXT LSB
R17[1] = 1
Y ADDR EXT MSB
Y ADDR EXT LSB

ATTRIBUTE SELECT
R17[O] = 0
GP ATTRIBUTE
GP ATTRIBUTE
~17[1] = 0
GP ATTRIBUTE
GP ATTRIBUTE

ATTRIBUTE SELECT PROGRAMMING
TABLE 3
INTERRUPT ENABLE (7 Bits-R17[7,5,4,3,2])-Write
only.
These bits, when set, enable the VIEW to generate
an interrupt when the appropriate conditions exist.
These bits are reset to zero by a hardware Reset or a
software Reset command. The following defines the
specific conditions associated with each of the bits in
this register.
Bit 7 (Interrupt Enable)
This bit, when set, will allow the VIEW to drive its
INT pin high whenever the Interrupt Pending bit in
the Interrupt Status 2 register goes high. When
reset, the VIEW cannot drive the INT pin high. This
bit is a global interrupt enable and has higher priority
than the other enable bits in this register.
Bit 5 (Cursor Window Interrupt Enable)
This bit, when set, will allow the VIEW to set the
Interrupt Pending bit after the last break has been
processed whenever the cursor position (upper left
corner of the cursor area) is moved into another
window. When reset, this condition will be ignored.
Bit 4 (Y Break Interrupt Enable)
This bit, when set, will allow the VIEW to set the
Interrupt Pending bit whenever a Y break with the
Interrupt Tag bit set is encountered when
generating Display Memory Addresses. The same
interrupt will be generated for both even and odd
fields. When reset, this condition will be ignored.
449

Bit 3 (Last Break Processed Interrupt Enable)
This bit, when set, will allow the VIEW to set the
Interrupt Pending bit whenever the VIEW retrieves
a Y break with a terminator window number followed
by an X break with a terminator window number.
When reset, th:s condition will be ignored.
Bit 2 (Vertical Retrace Interrupt Enable)
This bit, when set, will allow the VIEW to set the
Interrupt Pending bit at the start of vertical blanking
time. When reset, this condition will be ignored.
INTERRUPT STATUS 1 (5 Bits-RR17[6, 5, 4, 3, 2))Read only.
These bits act as flags to indicate which condition/s
are causing an interrupt. With the exception of bit 6
(Odd/Even status), these bits are reset by reading the
Interrupt Status 1 register, a hardware Reset, ~- ~
software Reset command. They can only be driven
active when they are enabled in the Interrupt Enable
register. This register should not be read unless the
Interrupt Pending bit in the Interrupt Status 2 register
is high or the VIEW has driven its INT output active.
Bit 6 (Odd/Even)
This bit is set when the next field to be displayed is
the odd field and is reset when the next field to be
displayed is the even field. This status bit becomes
valid shortly before the Vertical Retrace Interrupt
occurs and remains valid for the vertical period.
Bit 5 (Cursor Window Interrupt)
This bit is set whenever the cursor position (upper
left corner of the cursor area) is moved into a new
window.
Bit 4 (Y Break Interrupt)
This bit is set during the retrace period preceeding
the display of a window that has its Interrupt Tag bit
set.
Bit 3 (Last Break Processed Interrupt)
This bit is set whenever the VIEW retrieves a Y
break with a terminator window number followed
by an X break with a terminator window number.
The purpose of this condition is to indicate that the
VIEW will not access system memory again until
the Start Delay count has expired. This can be used
to give the system processor an opportunity 10
access the window list in memory. See section on
Break Processing under Functional Description.
Bit 2 (Vertical Retrace Interrupt)
This bit is set when the vertical retrace interval
begins.
INTERRUPT STATUS 2 (8 Bits-RR18[7,O))-Read only.
Bit 7 (Interrupt Pending)
This bit is set when any of the enabled interrupt
causing conditions has occurred. This bit is reset
by reading the Interrupt Status 1 register, a
hardware Reset, or a software Reset command.
Bit 6-0 (Cursor Window Number)
These bits represent the window number that the
VIEW cursor is currently resident in. This is
determined with respect to the location of the upper
left corner of the cursor block as specified in the
Horizontal and Vertical Cursor Position registers.
Bit 6 is the MSB and bit 0 is the LSB. If the cursor
is resident in more than one window, the window
number with the highest priority is reported here.
The data in this register is valid from the time the
Last Break Processed Interrupt occurs until the
Start Delay count expires.

I

T1
T2

T3

T16

T17
T13_ _ _

SCLK

.T4
AEN
T10
T7
AD15-0

DATA IN
BUS DIR:

T12

DMAR-----J

fl-"~---T14----~.1

ACKXX~
FIGURE 21-SYSTEM BUS MASTER TIMING
MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range ..................•.....•..........•.•...........•........... O°C to + 70°C
Storage Temperature Range ........•.....................................•...•......... -55°C to + 150°C
Lead Temperature (Soldering, 10 sec) ...................................•...•............•.•..... + 300°C
Positive voltage on any pin (WRT ground) . . . . . . . . . . . . . . . . . . . . . . . . . . • . • . . . . . . . . . . . . . . . • . . . . . . . . .. Vcc + 0.3V
Negative voltage on any pin (WRT ground) ........•................•.•...........•...•.............. -0.3V
Maximum Vcc ...•.•............•...................•.........•....•..................•.•....... + 7.0V
'Stresses above those listed may cause permanent damage to the device_ This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their
outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may appear on
the DC output. If this possibility exists it is suggested that a clamp circuit be used_
DC ELECTRICAL CHARACTERISTICS TA = O°C to + 70°C, Vee = 5.0V +- 5%
SYMBOL
COMMENTS
PARAMETER
MIN
TYP
MAX
UNITS
Input voltage:
0_8
All inputs except OClK, SClK, and CS
low
V
V'L
V,H
High
2.0
V
low
1.0
V
OClK, SClK, CS with Vcc = 5.0V
V'L
V,H
High
4.0
V
See NOTE 1.
Output voltage:
Low
0.4
V
VOL
10L = 1.6mA
VOH
High
2.4
V
10H = -40 fLA
Input leakage current:
10
p.A
I'L
10
fLA
I'H
Input/Output capacitance:
All inputs
25
pF
C'N
All outputs
50
pF
COUT
Power supply current:
30
rnA
Icc
NOTES: 1. The V,H MIN and V'L MAX ofSClK, CS, and OClKare 80% and 20% of Vee respectively.
450

ooe to + 70 e, Vee = 50V +- 5%

AC ELECTRICAL CHARACTERISTICS TA =
SYMBOL
PARAMETER
MIN
T1
T2
T3
T16
T17
T4
T5
T6
T7
T8
T9
T10
T12
T13
T14
T19
T18
T60
T61
T62
T63

System Bus:
SCLKperiod
SCLKhigh
SCLKlow
SCLK rise time
SCLK fall time
SCLK to AEN delay
AEN pulse width
AEN active to address
valid delay
AEN high to AD bus
drive delay
AEN low to AD bus float delay
Data valid to SCLK
setup time
Data hold time from
SCLKhigh
SCLKtoDMAR
delay
SCLK rising edge
to address valid
delay
ACK to SCLK setup
Address hold from
AENlow
RESET pulse width
CS read pulse width
CS write pulse width
CS active to data valid delay
CS active to AD bus drive

0

TYP

200
70
70

MAX

UNITS

10,000
5,000
5,000
10
10

ns
ns
ns

0
50
50

(lS

ns
ns
ns
ns
ns

0
50
35

ns
ns

0

ns
65

ns

50

ns

35
0

ns
ns

200
125
75

ns
ns
ns
ns
ns

75
0

~elay

T64
T65
T66
T67

CS inactive to AD bus float
delay
Write data setup time
to CS inactive
Write data hold time from
CS inactive
R/W and AID to CS active

75

ns

40

ns

0

ns

30

ns

0

ns

~tuptim~

T6d
T69
T70
T71
T72

T30
T31
T32
T43
T44
T33
T34
T45
T46

R/W and AID to CS active
hold time
CSrisetime
CS fall time
CS inactive between
processor access
Data hold time from
CSinactive
Display Bus:
DCLKperiod
DCLKhigh
DCLKlow
DCLK rise time
DCLK fall time
DCLK high to signal'
valid delay
Signal' hold time to DCLK
ri~edge

Ext V lAS active to DCLK
rising edge setu.2..!ime
DCLK high to Ext VS/HS
inactive hold time

10
10
200

ns
ns
ns

0

ns

100
40
40

5,000
2,500
2,500
10
10
75

ns
ns
ns
ns
ns
ns

0

ns

35

ns

0

ns

NOTE: I. Signal refers to following-ATTR7·0, CURS, HDA7·0, VDAII·O, CBLANK, CYSN, RFRSH,
BRKCHG, VLT, INT, VS and HS (VS and RS only when programmed as outputs).

451

COMMENTS

AD7-0 - - - - - t - - {

ND

~~~------------------~~~~--------------~~~~~

R/Vil

RESET

---~t=T18_r
FIGURE 22-SYSTEM BUS PERIPHERAL TIMING

T30

~

-

-T31-

T43DCLK

V

~

-T32-T44

\

I

- ..

T33

T33

~
SIGNAL'

I

\

f'oI'Ts!

1- r. T34
VS,HS
(Input mode)

\

T45

~

i\

-T45

fT46

T46

NOTE: 1 SIGNALabovereferstoATTR7-,Q."cURS, HDA7-0, VDA11-0,CBLANK, CSYN, RFRSH, BRKCHG,
VLT, INT, iffi and AS (iffi and H~ only when programmed as outputs).

FIGURE 23-DISPLAY BUS TIMING

~

~;i!i~;;!!; Circuit
diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
applications: consequentiy complete Information sufficient for construction purposes is not necessarily' given.
The Information has been carefUlly checked and is believed to be entirely reliable. However, no responsibility is
,

assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design and supply the best product possible.

452

~FIOPPY Disk

453

454

FDC765A/765A-2
FDC 7265/7265-2
Single/Double Density Floppy Disk Controller
FEATURES

o
o

o
tJ

o
o

o
o
o
o
o

IBM Compatible in both Single
and Double Density Recording
Formats (FDC765A)
Sony (EMCA) Compatible
Recording Format (FDC7265)
Programmable Data Record
Lengths: 128, 256, 512, or 1024
Bytes/Sector
Multi-Sector and Multi.:rrack
Transfer Capability
Drive up to 4 Floppy Disks
Data Scan Capability-will scan a
Single Sector or an entire cylinder's
worth of data fields, comparing on a
Byte by Byte Basis, data in the
Processor's Memory with data read
from the Diskette
Data Transfers in DMA or NonDMA Mode
Parallel Seek Operations on up to
four drives
Compatible with Most
Microprocessors
Single Phase 8 MHz Clock
Single +5 Volt Power Supply

PIN CONFIGURATION
RST 1
RD 2
WR 3

CS 4

393837 36 35 34333231 3029
HDl
FRISTP
lCTlDlR
i'lW/SEEK'
Vee
Vee
RESET

40
41
42
43
44

28
27

'mJ
WI'!
CS

A.

19
18
7 8 9 1011 121314151617

Ac 5
SYNC DB 6
ROD
c
ROW DB, 7
DB, 8

~~~ DB, 9
GND DB. 10
GND DB,11
NC
DB,12
ClK DB,13
INT ORO 14
lOX !JACK 15
TC 16
lOX 17
INT 18
ClK 19
GND 20

40
39
38:
37
36
35
34
33:
32
31
30
29
28
27
26
25
24
23
22
21

Vee
i'lW/SEEK
lCTlDlR
FRISTP
HDl
ROY
WP/TS'
FlTITRc
PSc
PS,
WDA
USc
US,
HD
MFM
WE
VCO
RDD

ROW
WCK

PI\CKAGE: 44 pin PlCC
PACKAGE: 40-pin DIP

o

COMPLAMOS® n-Channel
Silicon Gate Technology

o

Available in 40-Pin Dual-in-Line
Package

GENERAL DESCRIPTION
The FDC765A is an LSI floppy disk controller (FDC) chip,
which contains the circuitry and control functions for interfacing a processor to 4 floppy disk drives. It is capable of
either IBM 3740 single density format (FM). or IBM System
34 double density format (MFM) includitq double-sided
recording. The FDC765A provides control signals which
simplify the design of an external phase-locked loop and
write precompensation circuitry. The FDC simplifies and
handles most of the burdens associated with implementing
a floppy disk interface.

every time a data byte to be transferred. In the DMA mode,
the processor need only load the command into the FDC
and all data transfers occur under control of the FDC and
DMA controllers.

The FDC7265 is an addition to the FDC family that has been
designed specifically for the Sony Micro Floppydisk® drive.
The FDC7265 is pin-compatible and electrically equivalent
to the 765A but utilizes the Sony recording format. The
FDC7265 can read a diskette that has been formatted by
the FDC765A.

Read Data
Read 10
Specify
Read Track
Scan Equal
Scan High or Equal
Scan Low or Equal

There are 15 commands which the FDC765A1FDC7265 will
execute. Each of these commands requires multiple 8-bit
bytes to fully specify the operation which the processor
wishes the FDC to perform. The following commands are
available:

Each of these devices is also available in a -2 version. The
-2 versions represent a reduction from 4-micron to 3-micron
design rule. Functionally is the same. Minor differences
between the two versions are detailed in the AC Characteristics table. The -2 versions are only available in the plastic
package at this time.

Read Deleted Data
Write Data
Format Track
Write Deleted Data
Seek
Recalibrate
Sense Interrupt Status
Sense Drive Status

Address mark detection circuitry is internal to the FDC
which simplifies the phase-locked loop and read electronics. The track stepping rate, head load time, and head
unload time are user-programmable. The FDC765AI
FDC7265 offers additional features such as multi-track and
multi-side read and write commands and single and double
density capabilities.

Hand-shaking signals are provided in the FDC765AI
FDC7265 which make DMA operation easy to incorporate
with the aid of an external DMA controller chip. The FDC
will operate in either the DMA or non-DMA mode. In the nonDMA mode the FDC generates interrupts to the processor
455

ORa

DACK
INT

AD

WR

READV

Ao

WAITE PROTECT/TWO SIDE

RESET

INDEX
FAULT/TRACK 0

os
UNIT SELECT 0
UNIT SELECT 1
MFMMODE

eLK

RWISEEK

Vee

HEAD L.OAD

GNO

LOW CURRENT{OIRECTION
FAULT RESET/STEP

HEAD SELECT

BLOCK DIAGRAM

~

MEMORIES

1

1
I

8080 SYSTEM BUS

080-7

AO

MeMA

080-7

iOR

Rri
iiJR
Cs

i'ii'a1W

iOW

CS

INT

HRO

,

RESET

HLDA

DMA
CONTROLLER

•

~

DAT~
PLL

AD DATA

ORO

DACK

READ

WINDOW

WR DATA
FDC765
FDC7265

INPUT CONTROL

TC
TERMINAL
COUNT

OUTPUT CONTROL

SYSTEM CONFIGURATION

456

)
~

DRIVE .
INTERFACE (

DESCRIPTION OF PIN FUNCTIONS
PIN
SYMBOL
RST

2

Reset

INPUT/
OUTPUT
Input

CONNECTION
TO
Processor

RD

Read

InputCD

Processor

3

WR

Write

InputCD

Processor

4

CS

Chip Select

Input

Processor

5

Ao

Data/Status Reg
Select

InputCD

Processor

DBo-DB,

Data Bus

Processor

14

DRQ

15

DACK

DataDMA
Request
DMA
Acknowledge

InputCD
Output
Output
Input

DMA

16

TC

Terminal Count

Input

DMA

17

IDX

Index

Input

FDD

18

INT

Interrupt

Output

Processor

19

ClK

Clock

Input

20
21

GND
WCK

Ground
Write Clock

Input

22

ROW

Input

Phase lock loop

23

ROD

Read Data
Window
Read Data

Input

FDD

24

VCO

VCO Sync

Output

Phase lock loop

25
26

WE
MFM

Write Enable
MFM Mode

Output
Output

FDD
Phase Lock Loop

27

HD

Head Select

Output

FDD

28,29
30
31,32

US" USo
WDA

Unit Select
Write Data
Precompensation
(pre-shift)

Output
Output
Output

FDD
FDD
FDD

33

FLTfTRo

FaultfTrack 0

Input

FDD

34

WPfTS

Write Protect!
Two-Side

Input

FDD

NO.
1

6-13

PS" PSo

NAME

DMA

457

FUNCTION
Places FDC in idle state.'Resets
output lines to FDD to "0" (low).
Does not effect SRT, HUT or HLT
in Specify command. If ROY pin is
held high during Reset, FDC will
generate interrupt 1.024 ms later.
To clear this interrupt use Sense
Interrupt Status command.
Control signal for transfer of data
from FDC to Data Bus, when
"0" (low).
Control signal for transfer of data to
FDC via Data Bus, when "0" (low).
IC selected when...::lL' (low),
allowing RD and WR to be
enabled.
Selects Data Reg (Ao = 1) or
Status Reg (Ao = 0) contents of
the FDC to be sent to Data Bus.
Bi-Directional 8-Bit Data Bus.
DMA Request is being made by
FOC when DRW = "1 '.
DMA cycle is active when "0" (low)
and Controller is performing DMA
transfer.
Indicates the termination of a DMA
transfer when "1" (high). It
terminates data transfer during
Read/Write/Scan command in
DMA or interrupt mode.
Indicates the beginning of a disk
track.
Interrupt Request Generated by
FDC.
Single Phase 8 MHz Squarewave
Clock.
D.C. Power Return.
Write data rate to FDD. FM = 500
kHz, MFM = 1 MHz, with a pulse
width of 250 ns for both FM and
MFM.
Generated by Pll, and used to
sample data from FDD.
Read data from FDD, containing
clock and data bits.
Inhibits VCO in PLL when "0"
(low), enables VCO when "1:'
Enables write data into FDD.
MFM mode when "1:' FM mode
when "0."
Head 1 selected when "1" (high).
Head 2 selected when "0" (low).
FDD Unit Selected.
Serial clock and data bits to FDD.
Write precompensation status
during MFM mode, Determines
early, late, and normal times.
Senses FDD fault condition, in
Read/Write mode; and Track 0
condition in Seek mode.
Senses Write Protect status in
ReadlWrite mode; and Two Side
Media in Seek mode.

DESCRIPTION OF PIN FUNCTIONS

35

PIN
SYMBOL
ROY

NAME
Ready

INPUTI
OUTPUT
Input.

CONNECTION
TO
FOO

36

HOL

Head Load

Output

FOO

37

FRISTP

Fit Reset/Step

Output

FDO

38

LCT/DIR

Low Current/
Direction

Output

FDD

39

RW/SEEK

Read Write/SEEK

Output

FDD

NO.

40
+5V
Vee
Note:  R), and the scan operation is continued. The scan operation continues until one
of the following conditions occur; the conditions for scan are
met (equal, low, or high), the last sector on the track is
reached (EaT), or the terminal count signal is received.

463

If the conditions for scan are met then the FDC sets the SH
(Scan Hit) flag Status Register 2 to a 1 (high), and terminates the Scan Command. If the conditions for scan are not
met between the starting sector (as specified by R) and the
last sector on the cylinder (EaT), then the FDC sets the SN
(Scan Not Satisfied) flag of Status Register 2 to a 1 (high),
and terminates the Scan Command. The receipt of a TERMINAL COUNT signal from the Processor or DMA Controller during the scan operation will cause the FDC to
complete the comparison of the particular byte which is in
process, and then to terminate the command. Table 4 ~hows
the status of bits SH and SN under various conditions of
SCAN.
STATUS REGISTER 2
COMMAND
COMMENTS
BIT2 = SN BIT3 = SH
0
1
DFDD = DpROCESSOA
Scan Equal
1
0
DFDO '4= DpROCESSOR
1
0
OFDD = DpROCESSOR
Scan Low or
0
0
OFDD < DpROCESSOR
Equal
1
0
DFOO > DpROCESSOR
1
0
DFDD = DpROCESSOR
Scan High or
0
0
OFDD> DpRocEssoR
Equal
1
0
OFDD < DpRocEssoR
Table 4
Ifthe FDC encounters a Deleted Data Address Mark on one
of the sectors (and SK = 0), then it regards the sector as
the last sector on the cylinder, sets CM (Control Mark) flag
of Status Register 2 to a 1 (high) and terminates the command. If SK = 1, the FDC skips the sector with the Deleted
Address Mark, and reads the next sector. In the second case
(SK = 1), the FDC sets the CM (Control Mark) flag of Status Register 2 to a 1 (high) in order to show that a Deleted
Sector had been encountered.
When either the STP (contiguous sectors = 01, or alternate sectors = 02 sectors are read) or the MT (Multi-Track)
are programmed, it is necessary to remember that the last
sector on the track must be read. For example, if STP = 02,
MT = 0, the sectors are numbered sequentially 1 through
26, and we start the Scan Command at sector 21 ; the following will happen. Sectors 21,23 and 25 will be read, then
the next sector (26) will be skipped and the index Hole will
be encountered before the EaT value of 26 can be read.
This will result in an abnormal termination of the command.
If the EaT has been set at 25 or the scanning started at
sector 20, then the Scan Command would be completed in
a normal manner.
During the Scan Command data is supplied by either the
processor or DMA Controller for comparison against the
data read from the diskette. In order to avoid having the OR
(Over Run) flag set in Status Register 1, it is necessary to
have the data available in less than 27 ILs (FM Mode) or 13
ILS (MFM Mode). If an Overrun occurs the FDC ends the
command with bits 7 and 6 of Status Register 0 set to 0 and
1, respectively.

Seek
The read/write head within the FDD is moved from cylinder
to cylinder under control of the Seek Command. FDC has
four independent Present Cylinder Registers for each drive.
They are clear only after Recalibrate command. The FDC
compares the PCN (Present Cylinder Number) which is the
current head position with the NCN (New Cylinder Number), and if there is a difference performs the following
operation:
PCN < NCN: Direction signal to FDD set to a 1 (high),
and Step Pulses are issued. (Step In.)
PCN > NCN: Direction signal to FDDsettoaO(low), and
Step Pulses are issued. (Step Out.)

The rate at which Step Pulses are issued is controlled by
SRT (Stepping Rate Time) in the SPECIFY Command. After
each Step Pulse is issued NCN is compared against PCN,
and when NCN = PCN, then the SE (Seek End) flag is set
in Status Register 0 to a 1 (high), and the command is terminated. At this point FDC interrupt goes high. Bits DB DDB3 in Main Status Register are set during seek operation
and are cleared by Sense Interrupt Status command.
During the Command Phase of the Seek operation the FDC
is in the FDC BUSY state, but during the Execution Phase
it is in the NON BUSY state. While the FDC is in the NON
BUSY state, another Seek Command may be issued, and
in this manner parallel seek operations may be done on
up to 4 Drives at once. No other command could be issued
for as long as FDC is in process of sending Step Pulses to
any drive.
If an FDD is in a NOT READY state at the beginning of the
command execution phase or during the seek operation,
then the NR (NOT READY) flag is set in Status Register 0
to a 1 (high), and the command is terminated after bits 7
and 6 of Status Register 0 are set to 0 and 1 respectively.
If the time to write 3 bytes of seek command exceeds 150
ILS, the timing between first two Step Pulses may be shorter
than set in the Specify command by as much as 1 ms.

Recalibrate
The function of this command is to retract the read/write
head within the FDD to the Track 0 position. The FDC clears
the contents of the PCN counter, and checks the status of
the Track 0 signal from the FDD. As long as the Track 0 signal is low, the Direction signal remains 0 (low) and Step
Pulses are issued. When the Track 0 signal goes high, the
SE (SEEK END) flag in Status Register 0 is set to a 1 (high)
and the command is terminated. If the Track 0 signal is still
low after 77 Step Pulses have been issued, the FDC sets
the SE (SEEK END) and EC (EQUIPMENT CHECK) flags
of Status Register 0 to both 1s (highs), and terminates the
command after bits 7 and 6 of Status Register 0 is set to 0
and 1 respectively.
The ability to do overlap RECALIBRATE Commands to
multiple FDDs and the loss of the READY signal, as
described in the Seek Command, also applies to the
RECALIBRATE Command.

Sense Interrupt Status
An Interrupt signal is generated by the FDC for one of the
following reasons:
1. Upon entering the Result Phase of:
a. Read Data Command
b. Read a Track Command
c. Read 10 Command
d. Read Deleted Data Command
e. Write Data Command
f. Format a Cylinder Command
g. Write Deleted Data Command
h. Scan Commands
2. Ready Line of FDD changes state
3. End of Seek or Recalibrate Command
4. During Execution Phase in the NON-DMA Mode
Interrupts caused by reasons 1 and 4 above occur during
normal command operations and are easily discernible by
the processor. During an execution phase in NON-DMA
Mode, DB5 in Main Status Register is high. Upon entering
Result Phase this bit gets clear. Reason 1 and 4 does not
require Sense Interrupt Status command. The interrupt is
cleared by reading/writing data to FDC. Interrupts caused
by reasons 2 and 3 above may be uniquely identified with
the aid of the Sense Interrupt Status Command. This com-

464

mand when issued resets the interrupt signal and via bits
5, 6, and 7 of Status Register a identifies the cause of the
interrupt.
SEEK
END

BITS 5

INTERRUPT
CODE
BIT6
BIT7

a

1

1

1

a

1

1

a
a

CAUSE

Ready Line changed state, either
polarity_
Normal Termination of Seek or
Recalibrate Command
Abnormal Termination of Seek or
Recalibrate Command
Table 5

Neither the Seek or Recalibrate Command have a Result
Phase. Therefore, it is mandatory to use the Sense Interrupt Status Command after these commands to effectively
terminate them and to provide verification of where the head
is positioned (PCN).
Issuing Sense Interrupt Status Command without interrupt
pending is treated as an invalid command.

Specify
The Specify Command sets the initial values for each of the
three internal timers. The HUT (Head Unload Time) defines
the time from the end of the Execution Phase of one of the
ReadlWrite Commands to the head unload state. This timer
is programmable from 16 to 240 ms in increments of 16 ms
(01 = 16 ms, a? = 32 mS ... OF = 240 ms).The SRT (Step
Rate Time) defines the time interval between adjacent step
pulses. This timer is programmable from 1 to 16 ms in increments of 1 ms (F = 1 ms, E = 2 ms, 0 = 3 ms, etc.). The
HlT (Head load Time) defines the time between when the
Head load signal goes high and when the Read/Write
operation starts. This timer is programmable from 2 to 254

ms in increments of 2 ms (01 = 2 ms, 02 = 4 ms, 03 = 6
ms ... 7F = 254ms).
The time intervals mentioned above are a direct function of
the clock (ClK on pin 19). Times indicated above are for an
8 MHz clock, if the clock was reduced to 4 MHz (mini-floppy
application) then all time intervals are increased by a factor
of2.
The choice of OMA or NON-OMA operation is made by the
NO (NON-DMA) bit. When this bit is high (NO = 1) the NONOMA mode is selected, and when ND = a the DMA mode
is selected.

Sense Drive Status
This command may be used by the processor whenever it
wishes to obtain the status of the FODs. Status Register 3
contains the Drive Status information stored internally in
FOC registers.
Invalid
If an invalid command is sent to the FOC (a command not
defined above), then the FOC will terminate the command
after bits 7 and 6 of Status Register a are set to 1 and a
respectively. No interrupt is generated by the FOC765A
during this condition. Bit 6 and bit 7 (010 and ROM) in the
Main Status Register are both high ("1") indicating to the
processor that the FOC is in the Result Phase and the contents of Status Register a (STO) must be read. When the
processor reads Status Register 0 it will find an 80 hex indicating an invalid command was received.
A Sense Interrupt Status Command must be sent after a
Seek or Recalibrate Interrupt, otherwise the FOC will consider the next command to be an Invalid Command.
In some applications the user may wish to use this command as a No-Op command, to place the FOC in a standby
or no operation state.

STATUS REGISTER IDENTIFICATION
BIT
NAME

SYMBOL

DESCRIPTION

Interrupt Code

IC

D,

Seek End

SE

D.

Equipment Check

EC

D3

Not Ready

NR

D,
D,
Do

Head Address
Unit Select 1
Unit Select a

D, = aand D. = a
Normal Termination of Command, (NT). Command was completed
and properly executed.
D, = aand D. = 1
Abnormal Termination of Command, (AT).
Execution of Command was started, but was not successfully
completed.
D, = 1 and D, = a
Invalid Command issue, (IC). Command which was issued was
never started.
D, = 1 and D. = 1
Abnormal Termination because during command execution the
ready signal from FDD changed state.
When the FDC completes the SEEK Command, this flag is set to
1 (high).
If a fault Signal is received from the FDD, or if the Track aSignal
fails to occur after 77 Step Pulses (Recalibrate Command) then this
flag is set.
When the FDD is in the not-ready state and a read or write
command is issued, this flag is set. If a read or write command is
issued to Side 1 of a single sided drive, then this flag is set.
This flag is used to indicate the state of the head at Interrupt.

NO.

D,
D,

HD
US1

usa

These flags are used to indicate a Drive Unit. Number at Interrupt.
465

BIT
NAME

NO.

07

End of Cylinder

D.
D.

Data Errror

D.

OverRun

0,
O2

No Data

0,

Not Writable

Do

Missing Address Mark

07
D.

Control Mark

D.
D.

Data Error in Data Field
Wrong Cylinder

0,

Scan Equal Hit

O2

Scan Not Satisfied

0,

Bad Cylinder

Do

Missing Address Mark
in Data Field

07

Fault

D.

Write Protected

D.

Ready

D.

Track 0

0,

Two Side

O2

Head Address

0,

Unit Select 1

Do

Unit Select a

DESCRIPTION
SYMBOL
STATUS REGISTER 1 (CONT.)
When the FDC tries to access a Sector beyond the final Sector of a
EN
Cylinder, this flag is set.
Not used. This bit is always 0 (low).
DE
When the FDC detects a CRC error in either the 10 field or the data
field, this flag is set.
OR
If the FDC is not serviced by the main-systems during data
transfers, within a certain time interval, this flag is set.
Not used. This bit always 0 (low).
NO
Duri~ execution of READ DATA, WRITE DELETED DATA or
SCA Command, if the FOC cannot find the Sector specified in the
lOR Register, this flag is set.
During executing the READ 10 Command, if the FDC cannot read
the 10 field without an error, then this fl~is set.
During the execution of the READ A Cylinder Command, if the
starting sector cannot be found, then this flag is set.
During execution of WRITE DATA, WRITE DELETED DATA or
NW
Format A Cylinder Command, if the FDC detects a write protect
signal from the FDD, then this flag is set.
MA
If the FDC cannot detect the 10 Address Mark after encountering
the index hole twice, then this flag is set.
If the FDC cannot detect the Data Address Mark or Deleted Data
Address Mark, this flag is set. Also at the same time, the MD
(Missing_Address Mark in Data Field) of Status Register 2 is set.
STATUS REGISTER 2
Not used. This bit is always 0 (low).
During executing the READ DATA or SCAN Command, if the FDC
CM
encounters a sector which contains a Deleted Data Address Mark,
this flag is set.
DO
If the FDC detects a CRC error in the data field then this flag is set.
This bit is related with the NO bit, and when the contents of C on the
WC
medium is different from that stored in the lOR, this flag is set.·
During execution, the SCAN Command, if the condition of "equal"
SH
is satisfied, this flag is set.
SN
During executin~ the SCAN Command, if the FDC cannot find a
Sector on the cy inder which meets the condition, then this flag
is set.
This bit is related with the NO bit, and when the content of C on the
BC
medium is different from that stored in the lOR and the content of C
is FF, then this flag is set.
When data is read from the medium, if the FDC cannot find a Data
MD
Address Mark or Deleted Data Address Mark, then this flag is set.
STATUS REGISTER 3
This bit is used to indicate the status of the Fault signal from
FT
the FDD.
This bit is used to indicate the status of the Write Protected signal
WP
from the FDD.
This bit is used to indicate the status of the Ready signal from
RY
theFDD.
This bit is used to indicate the status of the Track a signal from
TO
the FDD.
This bit is used to indicate the status of the Two Side signal from
TS
theFDD.
This bit is used to indicate the status of Side Select signal
HD
totheFDD.
This bit is used to indicate the status of the Unit Select 1 signal
US1
to the FDD.
This bit is used to indicate the status of the Unit Select a signal
usa
totheFDD.

466

PROCESSOR INTERFACE
During Command or Result Phases the Main Status Register (described earlier) must be read by the processor
before each byte of information is written into or read from
the Data Register. After each byte of data read or written to
Data Register, CPU should wait for 12 f,l-s before reading
MSR. Bits D6 and D7 in the Main Status Register must be
in aO and 1 state, respectively, before each byte of the command word may be written in the FDC. Many of the commands require multiple bytes, and as a result the Main Status
Register must be read prior to each byte transfer to the FDC.
On the other hand, during the Result Phase, D6 and D7 in
the Main Status Register must both be 1's (D6 = 1 and D7
= 1) before reading each byte from the Data Register. Note,
this reading of the Main Status Register before each byte
transfer to the FDC is required in only the Command and
Result Phases, and NOT during the Execution Phase.
During the Execution Phase, the Main Status Register need
not be read. If the FDC is in the NON-DMA Mode, then the
receipt of each data byte (if FDC is reading data from FDD)
is indicated by an Interrupt sigIllil on pin 18 (INT = 1). The
generation of a Read signal (RD = 0) or Write signal (WR
= 0) will reset the Interrupt as well as output the Data onto
the Data bus. If the processor cannot handle Interrupts fast
enough (every 13 f,l-s) for MFM and 27 f,l-s for FM mode, then
it may poll the Main Status Register and then bit D7 (ROM)
functions just like the Interrupt signal. If a Write Command
is in process then the WR signal performs the reset to the
Interrupt signal.
If the FDC is in the DMA Mode, no Interrupts are generated
during the Execution Phase. The FDC generates DRO's
(DMA Requests) when each byte of data is available. The
DMA Controller responds to this remest with both a DACK
= a (DMA Acknowledge) and a RD = a (Read signal).
When the DMA Acknowledge signal goes low (DACK = 0)
then the DMA Request is reset (DRO_==--O). If a Write Command has been programmed then a WR signal will appear
instead of RD. After the Execution Phase has been completed (Terminal Count has occurred) or EaT sector was
read/written, then an Interrupt will occur (INT = 1). This signifies the beginning of the Result Phase. When the first byte
of data is read during the Result Phase, the Interrupt is
automatically reset (INT = 0).

It is important to note that during the Result Phase all bytes
shown in the Command Table must be read. The Read Data
Command, for example has seven bytes of data in the Result
Phase. All seven bytes must be read in order to successfully complete the Read Data Command. The FDC will not
accept a new command until all seven bytes have been read.
Other commands may require fewer bytes to be read during
the Result Phase.
The FDC contains five Status Registers. The Main Status
Register mentioned above may be read by the processor at
any time. The other four Status Registers (STO, ST1, ST2,
and ST3) are only available during the Result Phase, and
may be read only after completing a command. The particular command which has been executed determines how
many of the Status Registers will be read.
The bytes of data which are sent to the FDC to form the
Command Phase, and are read out of the FDC in the Result
Phase, must occur in the order shown in the Command
Table. That is, the Command Code must be sent first and
the other bytes sent in the prescribed sequence. No foreshortening of the Command or Result Phases are allowed.
After the last byte of data in the Command Phase is sent to
the FDC, the Execution Phase automatically starts. In a
similar fashion, when the last byte of data is read out in the
Result Phase, the command is automatically ended and the
FDC is ready for a new command.

POLLING FEATURE OF THE

AC TEST CONDITION
INPUT/OUTPUT

CLOCK

2.4V

3.0V-----,

0,45V

O.3V---J

ACTESTING
Inputs are driven at 2.4V for a logic "1" and OASV for a logic "0," Timing measure~
ments are made at 2.0V for a logic "1" and a.8V for a logic "0."
Clocks are driven at 3.0V for a I09ic "1" and O.3V for a logic "0," Timing measurements are made at 2.4V for a logic "1" and O.65V for a logic "0."

467

FDC765A/7265

After the Specify command has been sent to the FDC, the
Unit Select line usa and US1 will automatically go into a
polling mode. In between commands (and between step
pulses in the SEEK command) the FDC polls all four FDD's
looking for a change in the Ready line from any of the drives.
If the Ready line changes state (usually due to a door opening or closing) then the FDC will generate an interrupt. When
Status Register a (STO) is read (after Sense Interrupt Status is issued), Not Ready (NR) will be indicated. The polling
of the Ready line by the FDC occurs continuously between
commands, thus notifying the processor which drives are
on or off line. Each drive is polled every 1.024 ms except
during the Read/Write commands.

I
-

TIMING DIAGRAMS

FDD WRITE OPERATION

PROCESSOR REAO OPERATION
AO,

Cs McK

=x

~'-

T AR~

I~

___

WAITE CLOCK

RD~TRR---t
,---I
I
J.: ---.:
TAD

I

t---TOF

WRITE ENABLE

I
I
I--'-Tev-j

PAESHIFT 0 OA

JX'-_______V-A....-

_I

I
WAITE DATA

I
I "0 I

I
<1>0 I

L

I

-;---v---....
~I:
~
1f'
!:lI:_.:....__

1'=-

CLOCK

:

I II
----t I-- T CP

~TAI--.I

'--i I

~

I

INT ------------""""~

I

I

"--1 ~TF

TA~:r--~_ _~I__~I____________~

:~------

DATA-------1-

elK

I

-----.J 1-4- TRA

I.Co-TCD

I

--l

I

I_"cv--'

¢A~~'j--','
I ...-J ~fF

I
PRESHIFT 0
NORMAL

WRITE CLOCK

LATE
EARLY

elK

INVALID

PRESHIFT 1

0
0

0

1

0

1

1

1

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
Operating Temperature, , .. , .. , , . , .. , , .. , , , .. , ... , ....... , , , ...... , , ..... , , .. , , ....... , , .. , , .... , ............ ,. -10°C to + 70°C
Storage Temperature .. , .. , .. , , .. , .. , ... , .... , ... , ..... , . , , ....... , ...... , ... , ... , .... , , .. , .... , .... , , ... , , .... - 55°c to + 150°C
All Output Voltages ... , .. , ... , ... , , ... , ..... , , .. , ..... , .......................... , ............ , ... , ...... , ..... - 0.5 to + 7 Volts
All Input Voltages .,",." ..... , .. , .. , ..... , .. , ............ , ....... , .. , ............ , ....... , ...... , ........ ,... - 0.5 to + 7 Volts
Supply Voltage Vee. , , , ..... , ..... , .. , , .... , .. , , ...... , ..... , .. , .... , , , ........ , ................. , , .... , .. .. ... - 0.5 to + 7 Volts
Power Dissipation , .. , , .. , .. , , .... , .. , , .... , .. , , ... , , . , ...... , , , , .... , , .... , ... , ... , , ....... , .............. , .. , .. , ........ 1 Watt
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device, This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not'
implied, Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC CHARACTERISTICS T.

=

DOC to

PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Voltage
(ClK + WR Clock)
Input High Voltage
(ClK + WR Clock)
Vee Supply Current
Input load Current
(All Input Pins)

+ 7DoC; Vee = + 5V ± 5% unless otherwise specified.
SYMBOL
VIL
V,H
VOL
VOH
VIL($I

MIN
-0.5
2.0

LIMITS
TYPey
«>0

Clock Rise Time

<1>,

Clock Fall Time
p." CS, i5AQ( Set Up Time to RD !
p." CS, DACK Hold Time from RD 1
RDWidth
Data Access Time from RD !
DB to Float Delay Time from RD 1
p." CS, i5AQ( Set Up Time to WR !
Ao, CS, DACK Hold Time to WR 1
WRWidth
Data Set Up Time to WR 1
Data Hold Time from WR 1
INT Delay Time from RD ;
INT Delay Time from WR ;
DRO Cycle Time
DRO Delay Time from DACK !
DRO ; to DACK ! Delay
DACKwidth
TCWidth
Reset Width

«>,
TAR
TRA
TRR
TRo
TOF
TAW
TWA
Tww
Tow
Two
TRI
TWI
TMcy
TAM
TMA
TAA
TTc

WCK CYCLE TIME

WCK Active Time (High)
ClK ; to WCK ; Delay
ClK ; to WCK ! Delay
WCK Rise Time
WCKFaliTime
Pre-Shift Delay Time from WCK ;
WDA Delay Time from WCK ;
RDD Active Time (High)

lAST

MIN
120
40

TCWH

TCWL

T,
T,
Tep
Teo
TROD

MAX
500

MIN
120
40

765A-2,7265-2
TYPCD
MAX
125
500

20
20
0
0
250

20
20
0
0
200

200
100

20
0
0
250
150
5

140
85

10
0
0
200
100
0

500
500
13

400
400
13

200
2
2
1
14

TWCKCY

To

765A,7265
TYPCD
125

80
0
0

140
2
2
1
14

16
8
8
4
8
4
16
8
250

350
40
40
20
20
100
100

20
20
40

80
0
0

CL
CL

~
~

100pF
100pF

"s
ns
ns
ns
ns
fl.s
ns

16
8
8
4
8
4
16
8
250

«>ev

350
40
40
20
20
100
100

2.0
1.0

MFM ~ 0 5V4"
MFM ~ 1 51/4"
MFM ~ 0 8"
MFM ~ 1 8"
MFM - 0 3W'@
MFM ~ 1 3W'@
MFM ~ 0 3W'@
MFM ~ 1 3W'@

ns
ns
ns
ns
ns
ns
ns
ns

Window Cycle Time

Twcy

Window Hold Time toifrom RDD

TRow
TWRO
Tus
Tso

15

15

ns

12
7

12
7

fl.S
fl.S

ToST

1.0

1.0

fl.S

TSTu

5.0

5.0

fl.S

TSTP
Tsc

6.0
33
8.0
To·50

USo, Hold Time to !lW/SEEK ;
SEEKlRW Hold Time to LOW
CURRENT/DIRECTION;
lOW CURRENTIDIRECTION Hold
Time to FAULT
RESET/STEP;
USo, Hold Time from FAULT RESET/
STEP;
STEP Active Time (Hiah)
STEP Cycle Time
FAULT RESET Active Time (High)
Write Data Width
USo , Hold Time After SEEK
Seek Hold Time from DIR
DIR Hold Time after STEP
Index Pulse Width
RD ! Delay from DRO
WR ! Delay from DRO
~ or I'![j Response TIme from DRO ;

TEST
CONDITIONS

«>Cy
«>Cy
«>Cy
«>Cy

20
20
40

2.0
1.0

UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

fl.s

MFM
MFM

~
~

0
1

8 MHz Clock Period

T'R
Twoo

Tsu
Tos
Ts10
T1DX
TMR
TMw
TMAW

7.0

8.0

@

@

10

15
30
24
10
800
250

6.0
33
8.0
To·50

7.0

8.0

@

®
10.0

15
30
24
4
800
250
12

NOTES: CD fI. Typical values forT, ~ 25°C and nominal supply voltage.
@ The former value of 2 and 1 are applied to Standard Floppy, and the
latter value of 4 and 2 are applied to Mini-floppy.
@ Under Software Control. The range is from 1 ms to 16 ms at 8 MHz
Clock Period, and 2 to 32 ms at 4 MHz Clock Period.

12

fl.S
fl.S
fl.S
ns
fl.S
fl.S
fl.S
«>Cy
ns
ns
fl.S

@ For mini-floppy applications, «>Cy must be 4 mHz.
@Sonymicrofloppy3W'drive(8"compatible).
® Sony microfloppy 3W' drive (5W' compatible).

469

8 MHz Clock Period

8 MHz Clock Period

TIMING DIAGRAMS
DMA OPERATION

PROCESSOR WRITE OPERATION
DRQ

WRorRD --+-------~

tNT

\...
I

SEEK OPERATION

==:x:

USO,1

j(,,__________

STABLE

-fU?1---

--i 'su
k

RW/SEEK - - " "

}lr.....,:~----

:1 DSr- I

--j'SDt--

-----X

DIRECTION

I-

X,....;..--i:-----

t - -~TU--l

'QST--I

~S-TD----~l~

STEP

________
'STP

----l f---

I

- - - - ' S C - - -....~I

" ".
I .

FLT RESET
I

I

II

I

~
I
II
I

~

FAULTRESET=
FILE UNSAFE RESET

~

TERMINAL COUNT

INDEX

T,DX

TFA 104--

TC

-.l1---l

I--TTC

TIDX

H~

FDD READ OPERATION
READ DATA

--1"\.------------.(\. '. . .-----X
t
---t
I

READ DATA WINDOW

I-TROD

I-TWRO-JI

I

I

I

J

Note: Either polarity d.-,-.-w-;n-d-O-W-;'-V-'-'id---

STANDARD MICROSVSTEMS
rlON

~

35M1rcusBMI.~.NY11788
(516)273-3'100TWJ(-510-227-88§'8

[--TROW,.!I

RESET

I

I.
..........-----TwCV---......-.:

RESET

H-

--::j ~

Circuit diagrams utilizing SMC products are included as a means of illustratingof:ypical semiconductor applications; consequently complete mformation sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is

:~i::~~~~~~~;J~~~\r~e~~!t~~~~~r~e ~a~~~i~?~ht:tb~s~~So~~\~~~~~J'Ct~s~~;~~~~rr~~rfos~~~;~nh~~~~~

at any time in order to improve design and supply the best product possible.

470

Floppy Oisk
Controller/Formatter
FOC
FEATURES

FOC 1791-02
FOC 1792-02
FOC 1793-02
FOC 1794-02
FOC 1795-02
FOC 1797-02
IlPC FAMILY

PIN CONFIGURATION

D SOFT SECTOR FORMAT COMPATIBILITY
D AUTOMATIC TRACK SEEK WITH VERIFICATION
D ACCOMMODATES SINGLE AND DOUBLE
DENSITY FORMATS
IBM 3740 Single Density (FM)
IBM System 34 Double Density (MFM)
DREAD MODE
Single/Multiple Sector Read with Automatic Search
or Entire Track Read
Selectable 128 Byte or Variable Length Record
DWRITE MODE
Single/Multiple Sector Write with Automatic Sector
Search
Entire Track Write for Diskette Initialization
D PROGRAMMABLE CONTROLS
Selectable Track to Track Stepping Time
Side Select Compare
D SYSTEM COMPATIBILITY
Double Buffering of Data 8 Bit Bi-Directional Bus for
Data, Control and Status
DMA or Programmed Data Transfers
All Inputs and Outputs are TTL Compatible
On-chip Track and Sector Registers/Comprehensive
Status Information
D WRITE PRECOMPENSATION (MFM AND FM)
D SIDE SELECT LOGIC (FDC 1795, FDC 1797)
D WINDOW EXTENSION (IN MFM)

.....,
NC
WE

cs
FiE

Ao
. A,
DALO"
DAL 1"
DAL2"
DAL3"
DAL4"
DAL5"
DAL6"
DAL 7"
STEP
DIRC
EARLY
LATE
MR
GND

3
4
5

10
9
0
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

+12V
INTRQ
ORO
DDEN"
WPRT

iP
TROO
WF
READY
WD
WG
TG43
HLD
RAW READ
RCLK
RGISSO
CLK
HLT
TEST
+5V

"INVERTED BUS FOR FDC 1791, FDC 1792, FOC 1795
""MUST BE LEFT OPEN FOR FOC 1792 and FDC 1794
PACKAGE: 40 pin D.I.P.

D INCORPORATES ENCODING/DECODING
AND ADDRESS MARK CIRCUITRY
D COMPATIBLE WITH FD179X-02
D COPLAMOS® n-CHANNEL MOS TECHNOLOGY
D COMPATIBLE WITH THE FDC 9216 FLOPPY DISK
DATA SEPARATOR
GENERAL DESCRIPTION

The FDC 179X is an MOS/LSI device which performs the
functions of a Floppy Disk Controller/Formatter in a
single chip implementation. The basic FDC 179X chip
design has evolved into six specific parts: FDC 1791,
FDC 1792, FDC 1793, FDC 1794, FDC 1795, and the
FDC1797.

density diskette. These include address mark detection,
FM and MFM encode and decode logic, window extension, and write precompensation.
The FDC 1793 is identical to the FDC 1791 except the
DAL lines are TRUE for systems that utilize true
data busses.
The FDC 1792 operates in the single density mode only,
Pin 37 (DDEN) of the FDC 1792 must be left open for
proper operation. The FDC 1794 is identical to the
FDC 1792 except the DAL lines are TRUE for systems
that utilize true data busses. The FDC 1795 adds side
select logic to the FDC 1791. The FDC 1797 adds the
side select logic to the FDC 1793.
The processor interface consists of an 8 bit bidirectional
bus for data, status, and control word transfers. This
family of controllers is configured to operate on a
multiplexed bus with other bus-oriented devices.

This FDC family performs all the functions necessary
to read or write data to any type of floppy disk drive.
Both 8" and 5'1'" (mini-floppy) drives with single or
double density storage capabilities are supported.
These n-channel MOS/LSI devices will replace a large
amount of discrete logic required for interfacing a host
processor to a floppy disk,
The FDC 1791 is IBM 3740 compatible in single density
mode (FM) and System 34 compatible in double density
mode (MFM). The FDC 1791 contains enhanced features necessary to read/write and format a double
471

\

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.
.. ""Don<:""":-r1,... ... ~

~

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor

!!!!~!!! applications: consequently complete information sufficient for construction purposes is not necessarily given.

The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to tne purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the best product possible.

472

FDC72C65/66
PRELIMINARY

Single/Double Density
Floppy Disk Controller
FEATURES

PIN CONFIGURATION

o IBM-compatible format (single,
double and quad density)
(FDC72C65)
o Sony (EMCA)-compatible recording
format (FDC72C66)
Multi-sector and multi-track transfer
capability
Drive Up to 4 floppy or micro
floppydisk drives
Data scan capability-will scan a
single sector or an entire cylinder
comparing byte-for-byte host
memory and disk data
Data transfers in DMA or
non-DMA mode
Programmable stepping rate, head
load and head unload times
Parallel seek operations on up to
four drives
Compatible with ""PD8080185,
""PD8086/88, ""PD80186/286/386
and Z80~ microprocessors
o Single-phase clock 8 MHz (standard
floppy) or 4 MHz (minifloppy)
CMOS technology
Single + 5V ± 10% power supply.

o
o
o
o
o
o
o

tu

CI)

'"~6g:

 ND

0

0

1

0

0

0

0

STO
PCN

~
~

Command codes
Status information about the FDC at the end of
seek operation

S~ecifl

Command

Sense Drive Status
Command
Result
Seek
Command

Execution
Invalid
Command
Result

.

W

0

0

0

0

0

W

X

X

X

X

X

R

.

W
W
W

1
HD

0
US,

ST3
0

0

0

0

X

X

X

X

Command codes

0
US.
~

1

X

1
HD

1
US,

Command codes

1
US.

NCN

Status information about FDD

~

Head is positioned over proper cylinder on diskette
W

Invalid Codes

~

STO

~

R

Invalid Command codes (No op-FDC goes into
standby state)
STO
BOH

Set Standby
Command
Execution
Reset Standby
Command
Execution
Software Reset
Command
Execution
Read a Track
Command

W

0

0

0

0

W

0

0

0

0

W

0

0

0

0

MF

SK

0

0

X

X

X

X

X

W
W
W
W
W
W
W
W
W

.
.

..

0
HD

C
H
R
N
EOT
GPL
DTL

1
US,

Command codes
Enter standbl mode
0

Command codes
Disable standbl mode

0

Command codes
Same as hardware reset

0
US.

Command Codes
~

~
~

~
~
~

Execution
Result

R
R
R
R
R
R
R

.
.
..

Sector ID information prior to command execution.

~

~

STO
ST1
ST2
C
H
R
N

Data transfer between the FDD and main system.
FDC reads ali data fields from index hole to EOT.
Status information after command execution

~
~

~
~

~
~

NOTES:

482

Sector ID information after command execution

Instruction Code
Phase
ReadlD
Command

RIW

D7

D,

D,

D,

D,

D,

D,

Do

W
W

0
X

MF
X

0
X

0
X

1
X

0
HD

1
US,

0
USo

Remarks
Command codes

Execution
Result

Format a Track
Command

Execution
Result

R
R
R
R
R
R
R

W
W
W
W
W
W

R
R
R
R
R
R
R

Scan Equal
Command

Execution
Result

W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R

..
..
.

STO
ST1
ST2
C
H
R
N

.

..
.

0
X

MF
X

0
X

0
X

.

MT
X

.
.
.

~
~

~

MF
X

SK
X

1
X

0
X
C
H
R
N
EOT
GPL
STP

Sector ID information read during execution phase
from floppy disk.

~

1
HD

0
US,

1
USo

Command codes

~

Bytes/sector
Sectors/track
Gap3
Filler byte
FDC formats an entire track.
Status information after command execution

~

In this case, the ID information has no meaning

~

~
~

~

STO
ST1
ST2
C
H
R
N

.
.

.

1
X
N
SC
GPL
D

~

The first correct ID information on the cylinder is
stored in data register.
Status information after command execution

0
HD

0
US,

1

Command codes

USo
~

•

STO
ST1
ST2
C
H
R
N

~

~

Note:

(1) In the Instruction Code, X = don't care (usually set to 0).
(2) A. should be 0 for SET STANDBY, RESET STANDBY, and SOFTWARE
RESET commands and 1 for all other commands.

NOTES:

483

Data compared between the FDD and main system
Status information after command execution
Sector ID information after command execution

System Configuration
Figure 2 shows an example of a system using a FDC72C65/
FDC72C66.

DBo-DB7
MEMR

imI

P.IEMW
lOW

cs

Ao
DBo-DB7

iiii
\Vii

cs
INT

HRQ
RESET
HLDA

Note that in the non-DMA mode it is necessary to examine
the main status register to determine the cause of the interrupt, since it co.u.ld be a data interrupt of a command termination interrupt, either normal or abnormal.
If the FDC72C65/FDC72C66 is in the DMA mode, no interrupts are generated during the execution phase. The
FDC72C65/FDC72C66 generates DROs (DMA requests)
when each byte of data is available. The DMA controller
responds to this request with both a DACK = 0 (DMA
acknowledge) and an RD = 0 (read signal). When the DMA
acknowledge signal goes low (DACK=O), then the DMA
request is clearmDRO = 0). If a write command has been
issued, then a WR signal will appear instead of RD. After
the execution phase has been completed (terminal count
has occurred) or the EOT sector read/written, then an interrupt will occur (INT = 1). This signifies the beginning of the
result phase. When the first byte of data is read during the
result phase, the interrupt is automatically cleared (I NT = 0).
The RD or WR signals should be asserted while DACK is
true. The CS signal is used in conjunction with RD and WR
as a gating function during programmed I/O operations. CS
has no effect during DMA operations. If the non-DMA mode
is chosen, the DACK signal should be pulled up to V cc'
It is important to note that during the result phase all bytes
shown in the instruction set (table 4) must be read. The read
data command, for example, has seven bytes of data in the
result phase. All seven bytes must be read in order to successfully complete the Read Data command. The
FDC72C65/FDC72C66 will not accept a new command until
all seven bytes have been read. Other commands may
require fewer bytes to be read during the result phase.

_P1l8257

DMA
ControU.r

Figure 2. System Configuration

Processor Interface
During command or result phases the main status register
(described earlier) must be read by the processor before
each byte of information is written into or read from the data
register. After each byte of data is read or written to the data
register, th~ CPU_ snou!Cl. wait for 12/Ls before reading
the main status register. Bits D6 and D7 in the main status
register must be in a 0 and 1 state, respectively, before each
byte of the command word may be written into the
FDC72C65/FDC72C66. Many of the commands require
multiple bytes and, as a result, the main status register must
be read prior to each byte transfer to the FDC72C65/
FDC72C66. On the other hand, during the result phase, D6
and D7 in the main status register must both be 1's (D6 = 1
and D7 = 1) before reading each byte from the data register.
Note that this reading of the main status register before
each byte transfer to the FDC72C65/FDC72C66 is required
only in the command and result phases, and not during the
execution phase.

The FDC72C65/FDC72C66 contains five status registers.
The main status register mentioned above may be read by
the processor at any time. The other four status registers
(STO, ST1, ST2, and ST3) are available only during the result
phase and may be read only after completing a command.
The particular command that has been executed determines how many of the status registers will be read.
The bytes of data which are sent to the FDC72C65/
FDC72C66 to form the command phase and are read out
of the FDC72C65/FDC72C66 in the result phase must occur
in the order shown in table 4. That is, the command code
must be sent first and the other bytes sent in the prescribed
sequence. No foreshortening of the command or result
phases is allowed. After the last byte of data in the command phase is sent to the FDC72C65/FDC72C66, the execution phase automatically starts. In a similar fashion, when
the last byte of data is read out in the result phase, the command is automatically ended and the FDC72C65/
FDC72C66 is ready for a new command.

During the execution phase, the main status register need
not be read. If the FDC72C65/FDC72C66 is in the non-DMA
uSo
mode, then the receipt of each data byte (if FDC72C65/
FDC72C66 is reading data from FDD) is indicated by an
interrup.!.§ignal on pin 18 (INT = 1.lJhe generation of a read
us,
signal (RD = 0) or write signal (WR = 0) will clear the interrupt as well as output the data onto the data bus. If the pro.cessor cannot handle interrupts fast enough (every 13/Ls
for the MFM mode and 27/Ls for the FM mode), then it may
poll the main status register and bit D7 (ROM) functions as
the inter.r.YID signal. If a write command is in the process
then the WR signal negates the reset to the interrupt signal.
484

Figure 3. Polling Feature

Polling
After reset has been sent to the FDC72C65/FDC72C66, the
unit select lines USa and US, will automatically go into a
polling mode. In between commands (and between step
pulses in the Seek command) the FDC72C65/FDC72C66
polls all four FDDs looking for a change in the ready line
from any of the drives. If the ready line changes state (usually due to a door opening or closing), then the FDC72C651
FDC72C66 will generate an interrupt. When status register
O(STO) is read (after Sense Interrupt Status is issued), not
ready (NR) will be indicated. The polling of the ready line by
the FDC72C65/FDC72C66 occurs continuously between
commands, thus notifying the processor which drives are
on or off line. Each drive is polled every 1.024 ms except
during the ReadlWrite commands. When used with a 4 MHz
clock for interfacing to minifloppies, the polling rate is 2.048
ms. See figure 3.

Read Data
A set of nine (9) byte words are required to place the FDC
into the read data mode. After the Read Data command has
been issued the FDC loads the head (if it is in the unloaded
state), waits the specified head settling time (defined in the
Specify command), and begins reading ID address marks
and ID fields. When the current sector number (R) stored
in the ID register (IDR) compares with the sector number
read off the diskette, then the FDC outputs data (from the
data field) byte-to-byte to the main system via the data bus.
After completion of the read operation from the current sector, the sector number is incremented by one, and the data
from the next sector is read and output on the data bus. This
continuous read function is called a multi-sector read operation. The Read Data command may be terminated by the
receipt of a terminal count signal. TC should be issued at
the same time that the DACK for the last byte of data is sent.
Upon receipt of this signal, the FDC stops outputting data
to the processor, but will continue to read data from the current sector, check CRC (cyclic redundancy count) bytes, and
then at the end of the sector terminate the Read Data command. The amount of data which can be handled with a single command to the FDC depends upon MT (multi-track),
MF (MFM/FM), and N (number of bytes/sector). Table 5
shows the transfer capacity.
The "multi-track" function (MT) allows the FDC to read data
from both sides of the diskette. For a particular cylinder, data
will be transferred starting at sector 1, side 0 and completing at sector L, side 1 (sector L = last sector on the side).
Note, this function pertains to only one cylinder (the same
track) on each side of the diskette.
When N = 0, then DTI defines the data length which the FDC
must treat as a sector. If DTL is smaller than the actual data
length in a sector, the data beyond DTL in the sector is not
sent to the data bus. The FDC reads (internally) the complete sector performing the CRC check and, depending
upon the manner of command termination, may perform a
multi-sector read operation. When N is non-zero, then DTL
has no meaning and should be set to FFH.

If the FDC detects the index hole twice without finding the
right sector, (indicated in "R"), then the FDC sets the ND
(No data) flag in status register 1 to a 1 (high), and terminates the Read Data command. (Status register 0 also has
bits 7 and 6 set to 0 and 1, respectively.)
After reading the ID and data fields in each sector, the FDC
checks the CRC bytes. If a read error is detected (incorrect
CRC in ID field), the FDC sets the DE (data error) flag in
status register 1 to a 1 (high), and if a CRC error occurs in
the data field, the FDC also sets the DD (data error in data
field) flag in status register 2 to a 1 (high), and terminates
the Read Data command. (Status register 0 also has bits 7
and 6 set to 0 and 1, respectively.)
If the FDC reads a deleted data address mark off the diskette, and the SK bit (bit D5 in the first command word) is
not set (SK = 0), then the FDC sets the CM (control mark)
flag in status register 2 to a 1 (high), and terminates the
Read Data command, after reading all the data in the sector. If SK = 1, the FDC skips the sector with the deleted data
address mark and reads the next sector. The CRC bits in
the deleted data field are not checked when SK = 1.
During disk data transfers between the FDC and the processor, via the data bus, the FDC must be serviced by the
processor every 27f.Ls in the FM mode, and every 13f.Ls in
the MFM mode, or the FDC sets the OR (Overrun) flag in
status register 1 to a 1 (high), and terminates the Read Data
command.
If the processor terminates a read (or write) operation in the
FDC, then the ID information in the result phase is dependent upon the state of the MT bit and EOT byte. Table 6
shows the values for C, H, R, and N, when the processor
terminates the command.

Functional Description of Commands
Write Data
A set of nine (9) bytes is required to set the FDC into the
write data mode. After the Write Data command has been
issued the FDC loads the head (if it is in the unloaded
state), waits the specified head setting time (defined in the
Specify command), and begins reading ID fields. When all
four bytes loaded during the command (C,H,R,N) match the
four bytes of the ID field from the diskette, the FDC takes
data from the processor byte-by-byte via the data bus and
outputs it to the FDD. See table 6.
After writing data into the current sector, the sector number
stored in R is incremented by one, and the next data field is
written into. The FDC continues this multisector write operation until the issuance of a terminal count signal. If a terminal count signal is sent to the FDC it continues writing
into the current sector to complete the data field. If the terminal count signal is received while a data field is being written then the remainder of the data field is filled with zeros.

At the completion of the Read Data command, the head is
not unloaded until after head unload time interval (specified The FDC reads the ID field of each sector and checks the
in the Specify command) has elapsed. If the processor CRC bytes. If the FDC detects a read error (CRC error) in
issues another command before the head unloads, then the one of the ID fields, it sets the DE (Data Error) flag of status
head setting time may be saved between subsequent register 1 to a 1 (high) and terminates the Write Data comreads. This time out is particularly valuable when a diskette mand. (Status register 0 also has bits 7 and 6 set to 0 and
1, respectively.)
is copied from one drive to another.
485

Table 5.

Transfer Capacity

MultiTrack
MT
0
0
1
1
0
0

MFM/
FM
MF
0
1
0
1
0
1
0
1
0
1
0
1

0
0

Table 6.
MT
0
0
0
0

Bytes/
Sector
N
00
01
00
01
01
02
01
02
02
03
02
03

Maximum Transfer Capacity
(Bytes/Sector)
(Number of Sectors)
(128) (26) = 3,328
(256) (26) = 6,656
(128) (52) = 6,656
(256) (52) = 13,312
(256) (15) = 3,840
(512) (15) = 7,680
(256) (30) = 7,680
(512) (30) = 15,360
(512) (8) ,;, 4,096
(1024) (8) = 8,192
(512) (16) = 8,192
(1024) (16) = 16,384

Final Sector
Read from
Diskettes
26atsideO
or 26 at side 1
26 at side 1
15 at side 0
or 15 at side 1
15atside 1
8atsideO
or 8 at side 1
8atside 1

Command Description
HD
0
0
1
0
0

Final Sector Transferred
to Processor
Less than EOT
EqualtoEOT
Less than EOT
EqualtoEOT
Less than EOT
Equal to EOT
Less than EOT
EqualtoEOT

C
NC
C+1
NC
C+1
NC
NC
NC
C+1

10 Information at Result Phase
H
R
N
NC
NC
R+1
NC
R=01
NC
NC
NC
R+1
NC
R=01
NC
NC
R+1
NC
LSB
R=01
NC
NC
NC
R+1
NC
LSB
R=1

NOle: (1) NC (No Change): The same value as the one at the beginning of
command execution.
(2) LSB (Least Significant Bit): The least significant bit of H is
complemented.

The Write command operates in much the same manner as
the Read command. The following items are the same, and
one should refer to the Read Data command for details:
• Transfer capacity
• EN (end of cylinder) flag
• ND (no data) flag
• Head unload time interval
• ID Information when the processor terminates command
• Definition of DTl when N = 0 and when N ,p. 0
In the write data mode, data transfers between the processor and FDe, via the data bus, must occur every 27f1s in
the FM mode and every 13f1s in the MFM mode. If the time
interval between data transfers is longer than this, the FDe
sets the OR (overrun) flag in status register 1 to a 1 (high)
and terminates the Write Data command. (Status register
also has bits 7 and 6 set to 0 and 1, respectively.)

o

Write Deleted Data
This command is the same as the Write Data command
except a deleted data address mark is written at the beginning of the data field instead of the normal data address
mark.
.

the beginning of a data field (and SK = 0 (low)), it will read
all the data in the sector and set the eM flag in status register 2 to a 1 (high), and then terminate the command. If
SK = 1, then the FDe skips the sector with the data address
mark and reads the next sector.
Read a Track
This command is similar to the Read Data command except
that this is a continuous read operation where the entire
data field from each of the sectors is read. Immediately after
sensing the index hole, the FDe starts reading all data fields
on the track as continuous blocks of data. If the FDe finds
an error in the ID or data eRe check bytes, it continues to
read data from the track. The FDe compares the ID information read from each sector with the value stored in the
IDR and sets the ND flag of status register 1 to a 1 (high) if
there is no comparison. Multi-track or skip operations are
not allowed with this command.
This command terminates when the number of sectors read
is equal to EOT. If the FDe does notfind an ID address mark
on the diskette after it senses the index hole for the second
time, it sets the MA (missing address mark) flag in status
register 1 to a 1 (high) and terminates the command. (Status register 0 has bits 7 and 6 set to 0 and 1, respectively).

Read Deleted Data

ReadlD

This command is the same as the Read Data command
except that when the FDe detects a data address mark at

The Read ID command is used to give the present position
of the recording head. The FDe stores the values from the

486

first ID field it is able to read. If no proper ID address mark
is found in the diskette before the index hole is encountered
for the second time, then the MA (missing address mark)
flag in status register 1 is set to a 1 (high), and if no data is
found then the ND (No data) flag is also set in status register 1 to a 1 (high). The command is then terminated with
bits 7 and 6 in status register 0 set to 0 and 1, respectively.
During this command there is no data transfer between
FDC and the CPU except during the result phase.

format which will be written is controlled by the values programmed into N (number of bytes/sector), SC (sectors/cylinder), GPL (gap length), and D (data pattern) which are
supplied by the processor during the command phase. The
data field is filled with the byte of data stored in D. The ID
field for each sector is supplied by the processor; that is,
four data requests per sector are made by the FDC for C
(cylinder number), H (head number), R (sector number), and
N (number of bytes/sector). This allows the diskette to be
formatted with nonsequential sector numbers, if desired.

Format a Track
The Format a Track command allows an entire track to be
formatted. After the index hole is detected, data is written
on the diskette; gaps, address marks, ID fields, and data
fields, all per the IBM System 34 (double density) or System
3740 (single density) format, are recorded. The particular

Table 7.

The processor must send new values for C,H,R, and N to
the FDC72C65/FDC72C66 for each sector on the track. If
FDC is set for the DMA mode, it will issue four DMA requests
per sector. If it is set for the interrupt mode, it will issue four
interrupts per sector and the processor must supply C, H,
R, and N loads for each sector. The contents of the R reg-

Sector Size
Format

Sector Size

N

SC

GPL(1)

GPL(2,3)

8" Standard Floppy
FMMode

128 Bytes/Sector

00

1A

07

1B

256

01

OF

OE

2A

512

02

08

1B

3A

1024

03
04

04

47

8A

02
01

C8

FF
FF
54

2048
256

05
01

1A

C8
OE

512

02

OF

1B

1024

003

08

35

74

2048
4096

04
05

04
02

99
C8

FF
FF

8192

06

01

C8

FF

128 Bytes/Sector
128

00

12
10

07
10

09

00

256
512

01
02

08
04

18
46

30
87

1024
2048

03
04

02

C8

FF

01

C8

FF

256

01

12

OA

OC

256
512

01
02

10

20
2A

1024
2048

03
04

4096
128 Bytes/Sector

4096
MFM Mode (Note 4)

36

51/." Minifloppy
FMMode

MFM Mode (Note 4)

19

32

80

50
FO

02

C8

FF

05

01

C8

FF

0
1

OF
09

07
OE

1B
2A

2
1

05
OF

1B

3A

256

OE

36

512

2

09

1B

54

1024

3

05

35

74

08
04

31/z" Sony Micro Floppydisk
FMMode

256
512
MFM Mode (Note 4)

Note:
(1) SU\lgested values of GPL in Read or Write commands to avoid
splice point between data field and ID field of contiguous
sections.
(2) Suggested values of GPL in format command.
(3) All values except sector size are hexidecimal.
(4) In MFM mode FDG cannot perform a ReadlWrite/Format operation with 128 bytes/sector. (N = 00).

487

ister are incremented by 1 after each sector is formatted;
thus, the R register contains a value of R when it is read
during the result phase. This incrementing and formatting
continues for the whole track until the FDC detects the index
hole for the second time, whereupon it terminates the
command.
If a fault signal is received from the FDD at the end of a write
operation, then the FDC sets the EC flag of status register
o to a 1 (high) and terminates the command after setting
bits 7 and 6 of status register 0 to 0 and 1, respectively. Also,
the loss of a ready signal at the beginning of a command
execution phase causes bits 7 and 6 of status register 0 to
be set to 0 and 1, respectively.
Scan Commands

The Scan commands allow data which is being read
from the diskette to be compared against data which is
being supplied from the main system. The FDC compares
the data on a byte-by-byte basis and looks for a sector of
data which meets the conditions of DFOO = DProcessor,
DFOO".;DProcessor, or DFOO'" DProcessor. The hexidecimal
byte of FF either from memory or from FDD can be used as
a mask byte because it always meets the condition of the
comparison. One's complement arithmetic is used for comparison (FF = largest number, 00 = smallest number). After
a whole sector of data is compared, if the conditions are not
mel, the sector number is incremented (R + STP-+R), and
the scan operation is continued. The scan operation continues until one of the following conditions occur: the conditions for scan are met (equal, low or high), the last sector
on the track is reached (EOT), or the terminal count signal
is received.
If the conditions for scan are met, then the FDC sets the SH
(scan hit) flag of status register 2 to a 1 (high) and terminates the Scan command. If the conditions for scan are not
met between the starting sector (as specified by R) and the
last sector on the cylinder (EOT), then the FDC sets the SN
(scan not satisfied) flag of status register 2 to a 1 (high) and
terminates the Scan command. The receipt of a terminal
count signal from the processor or DMA controller during
the scan operation will cause the FDC to complete the comparison of the particular byte which is in process and then
to terminate the command. Table 8 shows the status of bits
SH and SN under various conditions of Scan.

(SK = 1), the FDC sets the CM (control mark) flag of status
register 2 to a 1 (high) in order to show that a deleted sector
has been encountered.
When either the STP (contiguous sectors = 01, or alternate
sectors = 02) sectors are read or the MT (multitrack) is programmed, it is necessary to remember that the last sector
on the track must be read. For example, if STP = 02, MT = 0,
the sectors are numbered sequentially 1 through 26 and
the Scan command is started at sector 21, the following
will happen: sectors 21,23, and 25 will be read, then the
next sector (26) will be skipped and the index hole will be
encountered before the EOT value of 26 can be read. This
will result in an abnormal termination of the command. Ifthe
EOT had been set at 25 or the scanning started at sector
20, then the Scan command would be completed in a normal manner.
During the Scan cQmmand, data is supplied by either the
processor or DMA controller for comparison against the
data read from the diskette. In order to avoid having the OR
(overrun) flag set in status register 1, it is necessary to have
the data available in less than 27 fJ-s (FM mode) or 13 fJ-s
(MFM mode). If an overrun occurs, the FDC ends the command with bits 7 and 6 of status register 0 set to 0 and 1,
respectively.
Seek

The read/write head within the FDD is moved from cylinder
to cylinder under control of the Seek command. FDC has
four independent present cylinder registers for each drive.
They are cleared only after the Recalibrate command. The
FDC compares the PCN (present cylinder number) which
is the current head position with the NCN (new cylinder
number), and if there is a difference, performs the following
operations:
PCNNCN: Direction signal to FDD set to a 0 (low), and
step pulses are issued. (Step out)

The rate at which step pulses are issued is controlled by
SRT (stepping rate time) in the Specify command. After
each step pulse is issued NCN is compared against PCN,
and when NCN = PCN, the SE (seek end) flag is set in status register 0 to a 1 (high), and the command is terminated.
TableS. Scan Conditions
At this point FDC interrupt goes high. Bits DoB - D3B in the
main status register are set during the seek operation and
Status Register 2
are cleared by the Sense Interrupt Status command.
Bit2=SN Bit3 =SH
Comments
Command
During the command phase of the seek operation the FDC
Scan Equal
o
1
is in the FDC busy state, but during the execution phase it
o
is in the [lon-busy state. While the FDC is in the non-busy
Scan Low or
0
DFDD = Dp"",,,o,
Egual
--.::.O----O:...---.........:D::.!:F""DD'-<..:D::.!:p""""~,,~.,,'-- state, another Seek command may be issued, and in this
manner parallel seek operations may be done on up to four
drives at once. No other command can be issued for as long
o
Scan High or __.: .O_ _ _ _:...-_ _.........:D::.!:F""DD'-=..:D::.!:p""",,~,,~.,,'__ as the FDC is in the process of sending step pulses to any
drive.
Equal
o
o
If an FDD is in a not ready state at the beginning of the como
mand execution phase or during the seek operation, then
the NR (not ready) flag is set in status register 0 to a 1 (high),
If the FDC encounters a deleted data address mark on one and the command is terminated after bits 7 and 6 of status
of the sectors (and SK = 0), then it regards the sector as the register 0 are set to 0 and 1, respectively.
last sector on the cylinder, sets the CM (control mark) flag If the time to write three bytes of Seek command exceeds
of status register 2 to a 1 (high) and terminates the com- 150 fLS, the timing between the first two step pulses may be
mand. If SK = 1, the FDC skips the sector with the deleted shorter than set in the Specify command by as much as 1
address mark and reads the next sector. In the second case ms.
488

Recalibrate
The function of this command is to retract the read/write
head within the FDD to the track 0 position. The FDC clears
the contents of the PCN counter and checks the status of
the track 0 signal from the FDD. As long as the track 0 Signal
is I~w, the direction signal remains 0 (low) and step pulses
are Issue~. When the ~rack O. signal goes high, the SE (seek
end) flag In status register 0 IS set to a 1 (high) and the command is terminated. If the track 0 Signal is still low after 256
step pulses have been issued, the FDC sets the SE (seek
end) and EC (equipment check) flags of status register 0 to
both 1s (highs) and terminates the command after bits 7
and 6 of status register 0 are set to 0 and 1, respectively.
The ability to do overlapping Recalibrate commands to
mu.ltiple. FDDs and the loss of the ready signal, as desCribed In the Seek command, also applies to the Recalibrate command.
Sense Interrupt Status
An interrupt signal is generated by the FDC for one of the
following reasons:
(1) Upon entering the result phase of:
(a) Read Data command
(b) Read a Track command
(c) Read ID command
(d) Read Deleted Data command
(e) Write Data command
(f) Format a Cylinder command
(g) Write Deleted Data command
(h) Scan commands
(2) Ready line of FDD changes state
(3) End of Seek or Recalibrate command
(4) During execution phase in the non-DMA mode
Interrupts caused by reasons 1 and 4 above occur during
normal command operations and are easily discernible by

1:_

1 - - - - - - Seek (or Racallbrate) Command
:-command Phase
INT

I

I

I

I
I

RD1

Ul
U

Seek End _---=',':'-n:c:-te""rr:..::u:!:p""tC=-o=:d=e=--_ _
BitS
Bit6
Bit7
Cause
o
1
1
Ready line changed
state, either polarity
Normal termination
o
0
of Seek or Recalibrate command
o
Abnormal termination of Seek or
Recalibrate
command
~he S.ense Interrupt Status ~ommand is used in conjunction with the Seek and Recahbrate commands which have
no result phase. When the disk drive has reached the
desired head position the FDC72C65/FDC72C66 will set
the interrupt line true. The host CPU must then issue a
Sense Interrupt Status command to determine the actual
~ause of the interrupt, which could be seek end or a change
In ready status from one of the drives. A graphic example is
shown in figure 4.

Phase-I

U

~

un

li

Z

~i!~~_

~ii

~i:~

0_

~.~

I
I
I
I
I

I
I
I
I
I

I

I

I

I

llJn urn
In

lflJ

U

][

][

n

n

n

U

I
I
I

~

U

t

.li.

I

Sen•• Interrupt StatuI Command

I-Command P h a s e _ : _ Result Pha..- :

Ul
fLJl

DIOU

ROM

Interrupt Status

_I

Execution

-un unu m
I

WR

Table 9.

I
I
I
I
I

cs

Ao

the processor. During an execution phase in non-DMA
mode, DBs in the main status register is high. Upon entering
the result phase this bit gets cleared. Reasons 1 and 4 do
not require Sense Interrupt Status commands. The interrupt is cleared by reading/writing data to the FDC. Interrupts caused by reasons 2 and 3 above may be uniquely
identified with the aid of the Sense Interrupt Status comIT!and. This ?olT!mand, when issued, resets the Interrupt
Signal and, via bits 5, 6, and 7 of status register 0, identifies
the cause of the interrupt. See table 9.

I~
z ...

~§ i '"

8i
j@
Q.;;ls

uS
z.5

0.5:

.5

Figure 4. Seek, Recalibrate, and Sense Interrupt Status

489

C>

Iii "

.a~!~

us• a::Ina:: a.~

~

U
riB

0: ..

Specify
The Specify command sets the initial values for each of the
three internal timers. The HUT (head unload time) defines
the time from the end of the execution phase of one of the
Read/Write commands to the head unload state. This timer
is programmable from 16 to 240 ms in increments of 16 ms
(01 = 16 ms, 02=32 ms ... OFH =240 ms). The SRT (step
rate time) defines the time interval between adjacent step
pulses. This timer is programmable from 1 to 16 ms in increments of 1 ms (F = 1ms, E = 2ms, 0 = 3ms, etc.). The HlT
(head load time) defines the time between when the head
load signal goes high and the Read/Write operation starts.
This timer is programmable from 2 to 254 ms in increments
of 2 ms (01 =2 ms, 02=4 ms, 03=6 ms ... 7F=254 ms).

The set standby command reduces power consumption
(Po) from 10mWto 1O,..,W. Pin 19(ClK) must be active when
setting or resetting standby mode. All other clocks (i.e. WCK,
etc.) can be inactive. The supply voltage must be maintained at 5 V during standby. The clock to pin 19 may be
disabled during standby provided the following set-up and
hold conditions are met:

Standby Mode

Standby Mode
(Issuing command)

- -

32+CY_
CLKenabled
(0 = disabled)

The time intervals mentioned above are a direct function of
the clock (ClK on pin 19). Times indicated above are for an
8 MHz clock; if the clock was reduced to 4 MHz (minifloppy
application), then all time intervals are increased by a factor
of2.

_

24+CY

Note:
Standby mode will maintain internal status registers and 1/0 lines.

The choice of a OMA or non-OMA operation is made by the Differences Between the
NO (non-OMA) bit. When this bit is high (NO = 1) the non- FDC72C65/72C66 and FDC765A/7265
OMA mode is selected, and when NO = 0 the OMA mode is
selected.
Parameter
FDC72C65 FDC72C66 FDC765A FDC7265

Sense Drive Status

Track format

This command may be used by the processor whenever it
wishes to obtain the status of the FOOs. Status register 3
contains the drive status information stored internally in
FOC registers.

Tracks to be
recalibrated

Invalid
If an Invalid command is sent to the FOC (a command not
defined above), then the FOC will terminate the command
after bits 7 and 6 of status register 0 are set to 1 and 0,
respectively. No interrupt is generated by the FOC72C65/
FOC72C66 during this condition. Bits 6 and 7 (010 and
ROM) in the main status register are both 1 (high), indicating to the processor that the FOC72C65/FOC72C66 is in
the result phase and the contents of status register 0 (STO)
must be read. When the processor reads status register 0
it will find an 80H, indicating an invalid command was
received.
A Sense Interrupt Status command must be sent after a
seek or recalibrate interrupt, otherwise the FOC will consider the next command to be an Invalid command. In some
applications the user may wish to use this command as a
No-Op command to place the FOC in a standby or no operation state.

Commands that are available in the FOC72C65/FOC72C66
which are enhancements over the FOC765A1FOC7265
are the CMOS reset commands. They are initiated as
follows:

Reset standby
Software reset

1
1

0
0

0
0

IBM

EMCA/ISO

77

255

0.2ms (at 4 MHz)

about
about
1.2ms
0.2ms
(at 4 MHz) (at 4 MHz)

DRO i RD 1
TE response
time

125 ns at 4MHz
250 ns at BMHz

O.B fls

FDD response
latency after
unit select
signal output

2.5flS at 4MHz
5.0flS at BMHz

Multitrack
write by tunnel
erase head

Yes

No

Standby
function
(standby
command)

Yes

No

Software reset
command

Yes

No

Skipping time
after detection
of index pulses

1.6 fls

Figure 5 shows the data transfer format for the FOC72C65
and FOC72C66 in various modes.

AO RO WR 07 06 05 04 03 02 01 DO
0 1 0 0 0
0
0
0
0

ECMA/ISO
255

Data Format

CMOS Reset Commands

Set standby

IBM

0
0

0
0

0

0
0

The software reset command is identical to the hardware
reset described previously.
490

FDC72C65 (FM Mode)

IlId8~

i-------------RepeatN Tlmes-------------i

FDC72C66 (FM Mode)

IndeJt------------RepeatNTImeS-------------i

FDC72C65 (MFM Mode)

Inde~

f-------------RepeatNTlmes----------------i

FDC72C66 (MFM Mode)

Inde~

f------------RepeatNTlmes-------------1

FDC72C65
'nde.

Forma'

J\-------------t(~
L,..G_A_P_4a_.l..._'A_M_L...G_A_P_'_.L...'_D...L_G_A_P_2_.L..._DA_t_A_.l..._G_A_P_3...J_ _ _
'D_ _.,: :

GAP 4b

VCOSYNC

WE

FDC72C66
'nde.

Forma'

I

WE

\

J\-----------_t~
L..._G_AP_'__L-'_D...L_G_A_P_2_L..._D_A_TA_...L_G_A_P_3...J1_'D-LI_G_A_P_2...J_ _ _'_D_ _: :

VCOSYNC _ _ _ _ _ _ _ _\ ......_

Note:
_ _ _ Read
_ _ _ Write

r------,

1 ____ ~______ ~

....

r--------'I

r------""\
I

\

Figure 5. Data Format
491

I

GAP 4

ABSOLUTE MAXIMUM RATINGSTA = 25°e
Power supply voltage, Vcc ..................................................................................... - 0.3V to + 7V
Input voltage, V, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3V to Vee + 0.3V
Output voltage, Vo ....................................................................................... - 0.3V to Vcc + 0.3V
Operating temperature, TOPT ••• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• O°C to + 70°C
Storage temperature, TSTG •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• - 55°C to + 125°C
Power dissipation, Po ................................................................................................... 50mW
Comment: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the limits described in the operational sections of the specification. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CAPACITANCE TA

=

25°e, fc

=

1MHz, Vee

=

OV

PARAMETER
SYMBOL
Input clock capacitance
C,N("')
Input capacitance
C'N
Output capacitance
COUT
Note:
(1) All pins except pin under test tied to AC ground

LIMITS
TYP

MIN

MAX
20
10
20

UNIT
pF
pF
pF

DC CHARACTERISTICS
TA = - 1ooe to + 70oe, Vcc. = + 5V ± 10% unless otherwise specified
PARAMETER
Input voltage low
Input voltage high
Output voltage low
Output voltage high
Supply current (Vcel

SYMBOL
V,L
V,H
VOL
Vo"
100

MIN
-0.5
2.2

LIMITS
TYP

2.4
3
0.7

1001

Input load current high
Input load current low
Output leakage current high
Output leakage current low

IUH

ILiL

ILOH
ILOL

MAX
+0.8
Vcc+ 0.5
0.45
Vee
10
2
10
-10
10
-10

UNIT
V
V
V
V
mA
mA
I1A
I1A
I1A
I1A

(Note 1)
(Note 1)
(Note 1)

~

PARAMETER
Clock period

Clock active (high, low)
Clock rise time
Clock fall time
A", CS, DACK setup time to RDJ
A", CS, DACK hold time from ROt
RDwidth
Data access time from RDJ
DB to float delay time from ROt
A", CS, DACK setup time to WR!
A", CS, DACK hold time to WRt
WRwidth
Data setup time to WAt
Data hold time from WRt
INT delay time from ROt

SYMBOL

. WCK Timing
RWfSeek

Direction
ClK
Slap

-------.,;fI

Clock
Seek Operation

DRO

Fault ReIe1Fli. Un••" R....

--t}-~

!-----IIURW'----_I
WIIorllJj

FLTReset

DMA Operation

494

Timing Waveforms

-

n-1=

Reod-=f1
wIE-----I-RDO-t=;_
Data

Clock

Enable

Note: Either polarity dati window Is valid.

Pmhlft

FDD Read Operation

00r1

WrI..
Da..

PlHhlftO
Nannal

_1ft 1

Terminal Count

o

La..
Eady

Invalid

I

R...

1""1

~I~

FDD Write Operation

Reset

495

Cirouit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is

~!~~::~~~~~~~~U;~~~f6e~~~t~~~~~{~e ~ua~~~~~~~~t:tbfs~OC~~~\~~~s~~Stt~:s~~~;~i~:rr~~~ios~~~~~~~~~!

at any time in order to improve design and supply the best product possible.

496

FDC91C361
FDC92C36
PRELIMINARY

CMOS Floppy Disk Data Separator
FEATURES

PIN CONFIGURATION

o High Performance Digital Data Separator
o Pin Replacement for FDC9216 (FDC92C36)
o Performs complete data separation function for floppy
disk drives
o Eliminates all adjustments normally associated with
high performance data separators
o Single + 5 Volt Supply
o Fully TTL compatible
o Fabricated in power saving CMOS
o Compatible with 3.5",5.25" and 8" drives and data
rates up to 500 Kb/s
o 16-Bit half Cell Divide Algorithm greatly improves

FDC92C36/B

FDC91C36/B

~~:~~~ iL. ~____-,ll !E"
PACKAGE: B-pin DIP

performance over conventional digital designs

FUNCTIONAL
The FDC92C36 is a direct high performance CMOS pin for
pin replacement for the FDC9216 in systems using data
transfer rates of 250Kb/s or 125Kb/s.
The FDC92C36B can be used in systems having a 500Kb/s
data transfer rate by applying a 16MHz input clock to pin 3
and applying a low level to pin 6 and a high level to pin 5.
The FDC91 C36/B is designed for use with the FDC765A,
8272A or FDC72C65 floppy disk controller. The
FDC91C36/B provides an active high SEPD output, eliminating the inverter required when using the FDC9216/B.
The FDC91C36/FDC92C36 incorporates a high performance, synthetic phase locked loop digital data separator

DESCRIPTION
in a 300 mil wide 8 pin package.
The use of a high performance synthetic phase locked loop
allows the system designer to replace a costly and board
consuming analog data separator (and the tuning normally
required with an analog design) with a cost effective, single
chip digital circuit.
The FDC92C36 and the FDC91 C36 are available in two
versions: the parts without a "B" suffix (FDC92C36,
FDC91C36) are intended for 5.25" drives using data rates
of 250 Kb/s, and the parts with a "B" suffix (FDC92C36B,
FDC91C36B) are intended for 3.5",5.25" and 8" drives using
data rates of 500 Kb/s.
+5V
-GND

REFCLK _____
CDO_

CLOCK
DIVIDER

~

CD1_
~

DSKD_

EDGE
DETECTION
LOGIC

J

DATNCLOCK
SEPARATION
LOGIC

_SEPCLK
PULSE
REGENERATION
_SEPD
LOGIC

FLOPPY DISK DATA SEPARATOR BLOCK DIAGRAM

497

DESCRIPTION OF- PIN FUNCTIONS
PIN NO.

NAME

SYMBOL

1

OiskOata

OSKO

2
3
4
5,6

Separated Clock
Reference Clock
Ground
Clock Oivisor

7

Separated Oata
Separated Oata

SEPCLK
REFCLK
GNO
COO,
COl
SEPO
SEPO

8

Power Supply

Voo

FUNCTION

Oata input signal direct from disk drive. Contains combined clock and data
waveform.
Clock signal output from the FOOS derived from floppy disk drive serial bit stream.
Reference clock input
Ground
COO and COl control the internal clock divider circuit. Refer to Table 1.
(FOC91C36)
(FOC92C36)
This output is the regenerated data pulse derived from the raw data input. This
output is positive for the FOC91 C36 and negative for the FOC92C36.
+ 5 volt power supply

OPERATION
A reference clock (REFCLK) of 8 or 16 MHz is divided by
the FDDS to provide an internal clock. The division ratio is
selected by inputs COO and CD1. The reference clock and
division ratio should be chosen per table 1.
The FDDS detects the leading edges of the disk data pulses
and adjusts the phase of the internal clock to provide the
SEPARATED CLOCK output.
Separate short and long term timing correctors assure

accurate clock separation.
The SEPCLK frequency is nominally 1/32 the internal clock
frequency. Depending on the internal timing correction, the
duration of any SEPCLK half-cycle may vary from a nominal of 16 to a minimum of 12 and a maximum of 21 internal
clock cycles.
The reference clock (REFCLK) is .divided to provide the
internal clock according to pins COO and CD1.

TABLE 1
CDl

CDO

0

0

0

0

8MHzREFCLK

9.6 MHz

l6MHz REFCLK

not used

not used

51/4"SO
31/2" SOcoi
FLOPPY
DISK

I--=O:::'S::;Kc::D:..:;AT:;,;A_ _ DSKD

f - - - - -.....~ RDO
FOC179X
FLOPPYOISK
CONTROLLER

FOe 92C36

DRIVE

SEPClK f - - - - -......j RDW
C[Jf!

C01

~
LOGIC 1

LOGteO

~

TYPICAL SYSTEM CONFIGURATION FOR THE FDC92C36/B
(FDC179X Floppy Disk Controller, 5W Drive, Double Density)

16 MHz CRYSTAL
OSCILLATOR

REFClK
SEPD t-----~ ROD

FLOPPY
DISK

I-..:D::::IS::.:K.::DA::T::.A_-1 DSKO

FOe 91C368

DRIVE

SEPCLK
C[Jf!

t

LOGIC 1

FOC 765A or FOC 7265
FLOPPY DISK
CONTROLLER

1------1 RDW

CD1

LOOteO

TYPICAL SYSTEM CONFIGURATION FOR THE FDC91C36/B
(FDC765A Floppy Disk Controller, 1.2 MB 51/4" Drive)
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The information has been
carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under
the patent rights of SMC or others. SMC reserves the right to make changes at any time in order to improve design and
supply the best product possible.

500

FOC 9216
FOC 92168
pPC FAMILY

Floppy Disk Data Separator
FOOS
FEATURES

PIN CONFIGURATION

D PERFORMS COMPLETE DATA SEPARATION
FUNCTION FOR FLOPPY DISK DRIVES

D SEPARATES FM OR MFM ENCODED DATA
FROM ANY MAGNETIC MEDIA

D ELIMINATES SEVERAL SSI AND
MSI DEVICES NORMALLY USED FOR
DATA SEPARATION
D NO CRITICAL ADJUSTMENTS REQUIRED
D COMPATIBLE WITH STANDARD
MICROSYSTEMS' FDC 1791, FDC 1793 AND
OTHER FLOPPY DISK CONTROLLERS
D SMALL 8-PIN DUAL-IN-LiNE PACKAGE
D +5 VOLT ONLY POWER SUPPLY
D TTL COMPATIBLE INPUTS AND OUTPUTS

DSKD

1

SEPCLK

2
3
4

REFCLK
GND

8
7
6

CD1

5

COO

Voo

SEPD

GENERAL DESCRIPTION
package to save board real estate, the FDDS operates
on +5 volts only and is TTL compatible on all inputs
and outputs.
The FDC 9216 is available in two versions; the FDC 9216,
which is intended for 5'1.' disks and the FDC 92168 for
51f4' and 8" disks.

The Floppy Disk Data Separator provides a low cost
solution to the problem of converting a single stream of
pulses from a floppy disk drive into separate Clock and
Data inputs for a Floppy Disk Controller.
The FDDS consists primarily of a clock divider, a longterm timing corrector, a short-term timing corrector, and
reclocking circuitry. Supplied in an a-pin Dual-In-Line

-+5V
-GND

REFCLK

CDO
CDl

CLOCK
DIVIDER

DATNCLOCK
SEPARATION
LOGIC

DSKD

SEPCLK
PULSE
_
REGENERATION
LOGIC
_SEPD

EDGE
DETECTION
LOGIC

FLOPPY DISK DATA SEPARATOR BLOCK DIAGRAM

501

DESCRIPTION OF PIN FUNCTIONS

PIN NO.
1

NAME
Disk Data

SYMBOL
DSKD

2

Separated Clock

SEPCLK

3
4

Reference Clock·
Ground
Clock Divisor

REFCLK
GND
CDO,
CD1

5,6

FUNCTION
Data input signal direct from disk drive. Contains combined
clock and data waveform.
Clock signal output from the FDDS derived from floppy
disk drive serial bit stream.
Reference clock input
Ground
CDO and CD1 control the internal clock divider circuit. The
internal clock is a submultiple of the REFCLK according to
the following table:
CD1

CDO

0
0

0

1
1

0

Divisor
1

1

7

Separated Data

SEPD

1
SEPD is the data output of the FDDS

8

Power Supply

Voo

+5 volt power supply

2
4
8

FIGURE 1
TYPICAL SYSTEM CONFIGURATION
(5'/4' Drive, Double Density)

I

4 MHz CRYSTAL
OSCILLATOR

I
I

REFCLK

FLOPPY
DISK
DRIVE

SEPD
DISK DATA

~

74

I

REGENERATED DATA

COO CD1

••

GNDGND

502

•

CLK
RAW1'!E)i[i

FDG 1791 or Equiv.

FDC 9216
SEPCLK

1MHz

I

FLOPPY DISK CONTROLLER
DERIVED CLOCK

RCLK

OPERATION

A reference clock (REFCLK) of between 2 and 8 MHz
is divided by the FDDS to provide an internal clock.
The division ratio is selected by inputs CDO and CD1.
The reference clock and division ratio should be
chosen per table 1.
The FDDS detects the leading edges of the disk data
pulses and adjusts the phase of the internal clock
to provide the SEPARATED CLOCK output.

Separate short and long term timing correctors
assure accurate clock separation.
The internal clock frequency is nominally 16 times
the SEPCLK frequency. Depending on the internal
timing correction, the internal clock may be a
minimum of 12 times to a maximum of 22 times the
SEPCLK frequency.
The reference clock (REFCLK) is divided to provide
the internal clock according to pins CDO and CD1.

TABLE 1:
CLOCK DIVIDER SELECTION TABLE
DRIVE
(8" or 5'1/')

8
8
8

5'1.
5'1.
5'1.
5V.
5'1.

DENSITY
(DD or SD)
DD

REFCLK
MHz

CD1

CDO

8
8
4
8
4
8
4
2

0
0
0
0
0
1
0
0

0
1
0
1
0
0
1
0

SD
SD
DD
DD
SD
SD
SD

REMARKS

}select either one
}select either one
}select anyone

FIGURE 2

INTCLK
SEPCLK~r----------L-

____________~------------------L-__________

SEPD--------~~r-------------'~r-------------------,~r---------------

W

always two internal clm;k cycles

503

MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range .......................................................... O°C to +70°C
Storage Temperature Range ........................................................ -55°C to +150°C
Lead Temperature (soldering, 10 sec.) ......................................................... +325°C
Positive Voltage on any Pin, with respect to ground ............................................... +8.0V
Negative Voltage on any Pin, with respect to ground .............................................. -0.3V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in the
operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off.
In addition, voltage transients on the AC power line may appear on the DC output. If this possibility
exists it is suggested that a clamp circuit be used.

ELECTRICAL CHARACTERISTICS (TA =O°C to 70°C, VDD =+5V±5%, unless otherwise noted)
Parameter
D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low Level V,L
High Level V,H
OUTPUT VOLTAGE LEVELS
Low Level VOL
High Level VOH
INPUT CURRENT
Leakage I,L
INPUT CAPACITANCE
All Inputs
POWER SUPPLY CURRENT

Min.

TyP.

Units

0.8

V
V

0.4

V
V

10

pA

10

pF

60

mA

4.3
8.3
2500
2500
250
250

MHz
MHz
ns
ns
ns
ns
ns

100
100

ps
ps

2.0

2.4

100

A.C. CHARACTERISTICS
Symbol
REFCLK Frequency
fcy
REFCLK Frequency
fcy
REFCLK High Time
tCKH
REFCLK Low Time
tCKL
REFCLK to SEPD "ON" Delay
tSOON
REFCLK to SEPD "OFF" Delay
tSOOFF
REFCLK to SEPCLK Delay
tSPCK
DSKD Active Low Time
tOLL
DSKD Active High Time
tOLH

Max.

0.2
0.2
50
50
25
25
35
0.1
0.2

100
100

Comments

IOL=1.6mA
IOH=-100 pA
0-5V ,N -5V OO

FDC 9216
FDC 92168

FIGURE 3: AC CHARACTERISTICS

REFCLK

_ _ _~~"'l
SEPClK-------------------------'C

DSKD-----:[ ~ '59,--_
504

FDC9229T
FDC9229BT
FLOPPY DISK INTERFACE CIRCUIT
FEATURES

PIN CONFIGURATION

o Digital Data Separator

o
o
o
o
o
o
o
o

Performs complete data separation
function for floppy disk drives
Separates FM and MFM encoded data
No critical adjustments necessary
5%" and 8" compatible
Variable Write Precompensation
Internal Crystal Oscillator Circuit
Track-Selectable Write Precompensation
Retriggerable Head-Load Timer
Compatible with the FDC 179X, 765, and
other standard Floppy Disk Controllers
COPLAMOS® n-channel MOS Technology
Single + 5 Volt Supply
TTL Compatible

DSKD .1

I~ 0 ~ u
_ owu.J:5

a..o..I-ZJ:
........ n

18
17
16
15
14
13
12

19 P2

MINI 3

18 P1

J WDIN
DENS 4
J XTALlCLKIN SEPClK 5

17 PO

J EARLY
J NC
J GND
J CLKOUT

J NC

5 6 7 8 9 10 11
WLJLJLJLJLJLJ
t.)cn~()OI-~

zZ..Jza..::::l...J

~fu

C/)

20 Vee

.... n n n

25242322212019
NC C 26
P, ( 27
vee C 28
NC ( 1
DSKD C 2
FDCSEL C 3
MINI[ 4

"--./

FDCSEl 2

Z

~86
;:I

PACKAGE: 28-pin PLCC

SEPD 6

16 TEST
15 HlD

WDOUT 7

14 lATE

HlT/ClK 8

13 EARLY

ClKOUT 9

12 WDIN

GND10

11 ClKIN

PACKAGE: 20-pin DIP

FUNCTIONAL DESCRIPTION
may be used when writing to the inner and outer tracks of
the floppy disk drive. The FDC 9229 operates from a + 5V
supply and simply requires that a TTL-level clock be connected to the CLKIN pin. All inputs and outputs are TTL
compatible.
The FDC 9229 is available in two versions: The FDC
9229/T are intended for 5%"drives and the FDC 92298/T
for 5'14" and 8" drives.
--

The FDC 9229 is an MOS integrated circuit designed to
complement either the 179X or 765 (8272) type of floppy
disk controller chip. It incorporates a digital data separator,
write precompensation logic, and a head-load timer in one
0.3-inch wide 20-pin package. A single pin will configure the
chip to work with either the 179X or 765 type of controller.
The FDC 9229 provides a number of different dynamically
selected precompensation values so that different values

FDC9229
BLOCK DIAGRAM

505

DESCRIPTION OF PIN FUNCTIONS
PIN NO.
1

SYMBOL
DSKD

1/0
I

2

FDCSEL

I

3

MINI

I

4

DENS

I

5
6

SEPCLK
SEPD

0
0

7
8

WDOUT
HLT/CLK

0
0

9

CLKOUT

0

10
11

GND
CLKIN

I

12
13

WDIN
EARLY

I
I

14

LATE

I

15

HLD

I

16

TEST

I

17
18
19
20

PO
P1
P2
Vee

I
I
I

DESCRIPTION
This input is the raw read data received from the drive. (This input is
active low.)
This input signal, when low, programs the FDC 9229 for a 179X type of
LSI controller. When FDCSEL is high, the FDC 9229 is programmed for a
765 (8272) type of controller. (See fig. 4.)
The state of this input determines whether the FDC 9229 is configured
to support 8" or 5%" floppy disk drive interfaces. It is used in conjunction
with the DENS input to prescale the clock for the data separator. The
state of this input also alters the CLKOUT frequency, the
precompensation value, the head load delay time (when in 179X mode)
and the HLT/CLK frequency (when in 765 mode). (See figs. 2, 3, and 4.)
The state of this input determines whether the FDC 9229 is configured
to support single density (FM) or double density (MFM) floppy disk drive
interfaces. It is used in conjunction with the MINI input to prescale the
clock for the data separator. The state of this input also alters the
CLKOUT frequency when in the 765 mode. (See figs. 2, 3, and 4.)
A square-wave window clock signal output derived from the DSKD input.
This output is the regenerated data pulse derived from the raw data input
(DSKD). This signal may be either active low or active high as
determined by FDCSEL (pin 2).
The precompensated WRITE DATA stream to the drive.
When in the 765 mode (FDCSEL high), this output is the master clock to
the floppy disk controller. When in the 179X mode, this signal goes high
after the head load delay has occurred following the HLD input going
high. This output is retriggerable. (See fig. 3.)
This signal is the write clock to the floppy disk controller. Its frequency is
determined by the state of the MINI, DENS, and FDCSEL input pins.
(See fig. 3.)
Ground
This input is for direct connection to a 16 MHz or 8 MHz single-phase
TTL-level clock.
The write data stream from the floppy disk controller.
When this input is high, the current WRITE DATA pulse will be written
early to the disk.
When this input is high, the current WRITE DATA pulse will be written late
to the disk.
When both EARLY and LATE are low, the current WRITE DATA pulse will
be written at the nominal position.
This input is only used in 179X mode. A high level at this input causes a
high level on the HLT/CLK output after the specified head-load time delay
has elapsed. The delay is selected by the state of the MINI output. (See
fig. 3.) In 765 mode, this pin should be left floating or grounded.
This input (when low) decreases the head-load time delay and initializes
the data separator. This pin is for test purposes only. This input has an
internal pull-up resistor and should be tied high or disconnected for
normal operation.
P2-PO select the amount of precompensation applied to the write data.
(See fig. 2.)
+5 VOLT SUPPLY

506

OPERATION
Data Separator
The CLKIN input clock is internally divided by the FDC 9229
to provide an internal clock. The division ratio is selected
by the FDCSEL, MINI and DENS inputs depending on the
type of drive used. (See fig. 1.)

FDCSEL
0
0
0
0
1
1
1
1

The FDC 9229 detects the leading (negative) edges of
the disk data pulses and adjusts the phase of the internal
clock to provide the SEPCLK output.
Separate short- and long-term timing correctors assure
accurate clock separation.
The SEPCLK frequency is nominally 1116 the internal clock
frequency. Depending on the internal timing correction, the
duration of any SEPCLK half-cycle may vary from a nominal of 8 to a minimum of 6 and a maximum of 11 internal
clock cycles.

INPUTS
DENS
0
0
1
1
0
0
1
1

DIVISOR
f(CLKIN)/f(INTCLK)
2

MINI
0
1
0
1
0
1
0
1

4
4
8

4
8
2

4

FIG. 1

INTCLK
SEPCLK~r----------~__________~r------------------'L-

I

_______

LJr---~I--------~LJr------------------'~~-------------

SEPD*

I

I

lJ

'polarity of SEPD shown for FDCSEL = low.

always two internal clock cycles

Precompensation
The desired precompensation delay is determined by the
state of the PO, P1 and P2 inputs of the FDC 9229 as per
fig. 2. Logic levels present on these pins may be changed
dynamically as long as the inputs are stable during the time
the floppy disk controller is writing to the drive and the inputs
meet the minimum setup time with respect to the write data
from the floppy disk controller.

MINI
0
0
0
0
0
0
0
0

P2
0
0
0
0
1
1
1
1

P1
0
0
1
1
0
0
1
1

PO
0
1
0
1
0
1
0
1

MINI

PRECOMP VALUE
ns
62.5 ns
125 ns
187.5 ns
250 ns
250 ns
312.5 ns
312.5 ns

P2

P1

PO

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

PRECOMP VALUE

o ns
125
250
375
500
500
625
625

ns
ns
ns
ns
ns
ns
ns

o

NOTE: All values shown are obtained with a 16 MHz reference clock. Multiply pre-comp values by two for
8 MHz operation.

FIG. 2 WRITE PRECOMPENSATION
VALUE SELECTION

507

OPERATION. (CONT'O)

Head Load Timer
The head load time delay is either 40 ms or 80 ms, depending on the state of MINI. (See fig. 3.) The purpose of this
delay is to ensure that the head has enough time to engage
properly. The head load timer is only used in the 179X mode;
it is non-functional in the 765 mode.

FDCSEL
0
0
0
0

INPUTS
DENS
0
0
1
1
0
0
1
1

The FDC 179X initiates the loading of the floppy disk drive
head by setting HLD high. The controller then waits the programmed amount of time until the HLT signal from the FDC
9229 goes high before starting a read or write operation.

0
1
0
1

OUTPUTS
CLKOUT
HLT/CLK
2MHz
40ms'
80ms'
1 MHz
2MHz
40ms'
80ms'
1 MHz

0
1
0
1

500 KHz
250 KHz
1 MHz
500 KHz

MINI

8MHz
4MHz
8MHz
4MHz

NOTE: All values shown are obtained with a 16 MHz reference clock. Divide all frequencies and multiply all
periods by two for 8 MHz operation.
'May be mask programmed at factory to any value from 1
to 512 ms in 15.625 f-Ls increments (MINI low) or 1 to 1024
ms in 31.25 f-Ls increments (MINI high).

FIG. 3 CLOCK AND HEAD LOAD
TIME DELAY SELECTION

FDCSEL
0
0
0
0

INPUTS
DENS
0
0
1
1

MINI
0
1
0
1

FLOPPY DISK
DRIVE TYPE
8"DRIVE
5%"DRIVE
8"DRIVE
5W'DRIVE

FLOPPY DISK
DRIVE DENSITY
DOUBLE
DOUBLE
SINGLE
SINGLE

FLOPPY DISK
CONTROLLER TYPE
179X
179X
179X
179X

0
0
1
1

0
1
0
1

8"DRIVE
5W'DRIVE
8"DRIVE
5W'DRIVE

SINGLE
SINGLE
DOUBLE
DOUBLE

765 (8272)
765 (8272)
765 (8272)
765 (8272)

FIG. 4 FLOPPY DISK DRIVE AND CONTROLLER SELECTION

508

MAXIMUM GUARANTEED RATINGS'
Operating Temperature Range ........................................................................ O°C to + 70°C
Storage Temperature Range ........................................................................ - 55° to + 150°C
lead Temperature (soldering, 10 sec.) ....................................................................... + 300°C
Positive Voltage on any 1/0 Pin, with respect to ground ......................................................... + 8.0V
Negative Voltage on any I/O Pin, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3V
Power Dissipation .......................................................................................... 0.75W
·Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output.

ELECTRICAL CHARACTERISTICS (TA = 0°Ct070°C, Vee = 5V ±5%)

PARAMETER
DC CHARACTERISTICS
INPUT VOLTAGE
lowlevelVIL
High level V,H
ClKIN INPUT VOLTAGE
low level
High level

MIN

TYP

MAX

UNIT

-0.3
2.0

0.8
(Vee)

V
V

-0.3
2.4

0.8
(Vee)

V
V

0.4

V

OUTPUT VOLTAGE
low level VOL
High level V OH

2.4

V

CONDITIONS

Except ClKIN

10L
10L
10H
10H

= 1.6 mAexcept HlT/ClK
= 0.4 mA, HlTIClK only
= -1QOf1AexceptHlT/ClK
= -400 f1A, HlT/ClKonly

= OtoVee

POWER SUPPLY CURRENT
I"
INPUT lEAKAGE CURRENT
I'L
INPUT CAPACITANCE
C'N

ELECTRICAL CHARACTERISTICS (TA
PARAMETER
AC ELECTRICAL
CHARACTERISTICS
ClKIN frequency
ClKIN DUTY CYCLE
talkoh

t...o
I"
I"NEe
tWdE
t.dN
t.dL
t,

=

O°C to 70°C, Vee

MIN

=

100

mA

10

f1A

V,N

10
25

pF
pF

Except ClKIN
ClKINonly

MAX

UNIT

5V ± 5%

TYP

All times assume ClKIN
3.95
3.95
25
465
215
90
280
50
0
500

16
8

16.2
8.1

75
515
265
140
350
400
400
562.5
625
precomp value
2x precojP value
500
250
125
312.5

1.0

= 16 MHz unless otherwise specified)
MHz
MHz

%
ns
ns
ns
ns
ns
ns
ns

f1S

509

CONDITIONS

FDC9229B
FDC9229
FDCSEl = low; MINI = high.
FDCSEl = low; MINI = low.
FDCSEl = high.
Time Doubles with MINI = 1

9 clock times ± 1 clock time
See fig. 2
See fig. 2

AC TIMING CHARACTERISTICS
HLT/CLK (765 MODE)

~.

WDOUT PULSE WIDTH

~

I
4or8 MHz

}=tWO,==f

CLKOUT VS. WDIN TIMING
179X MODE

~"1

CLKOUT

WDIN

I

I

\
\

1,2, or 4 ,",sec.
765 (8272) MODE

r-\

~

CLKOUT
t dNEC

---t,--

I

WDIN

SET-UP TIME PI, P1 AND P2 TO WDIN
P0, P1, P2

c~o"'
WDIN

t.

-i..

(765)

WDIN

tClkOh

~

/

CLKOUT " " '
(179X)

CLKOUT

CLKOUT

\.

-..J

IIIIIIIIIIIIII
'WDOUT (EARLY) - - . . J

_t..",
PRECOMPENSATION

1

WDOUT (NOMINAL)

~t"dL

WDOUT (LATE)

Ref. to Fig. 2 for
~

i

(precompensation)
value

510

'-

TYPICAL SYSTEM IMPLEMENTATION-765 (8272) FOC

r--1>

DRIVE

A

~l

765(8272)

r=

G1

1

~

FRISTP

~

LCT/DIR

~

-iq-

WP/TS
FLTITR0

G2

2SIDED
WPRT
TRK00
FAULT

RW/SEEK
0007

(:)

DB0DB7

FAULT
RST
STEP
LOW CUR
DIR

I"'""'[)
NT-4- INT

US1

CS--- CS
RD ___
RD
WR _ WR
A 0 _ A0

US0

TC

~

D
E

HDL

l

FDC9229

I--

TC

r

WDA
PS0
PS1
RDW

EARLY
LATE
SEPCLK DSKD

RDD

SEPD

MFM
WCK
CLK

~

HLD

TEST
FDCSEL
WDOUT
WDIN

+5V

RES ET ..... RST

.,.,

--

I~

~r-

P2

MINI
DENS
CLKOUT
HLT/CLK

P1
P0

CLKIN

<$-

----'\
---I

WDATA

RAW
READ

~~tr;~~

~~
-~

•

16MHz
TTL INPUT

LATCH

D0-D7

DRSEL3
DRSEL2
DRSEL1

0

RDY ~RDY
IDX
IDX
WE ~WE
HD ~SIOESEL

DRO-4- DRO
CK ___
OA
DACK

DRSEL4

E
C

RDY

RDY

IDY
WE

IDX
WE

SIDESEL

SIDE

MOTOR
ON

A

--.J
"The FDC9229/B, as all other NMOS integrated circuits, presents a high
impedance on all inputs.
To avoid soft errors caused by transmission line effects and noise where
there is long cabling between the floppy disk drive and the controller board, the
use of a (non-inverting) k"bL schmidt-trigger input gate or bus transceiver is
recommended at the DS
input to the FDC9229/B.

511

TYPICAL SYSTEM IMPLEMENTATION-179X FOC
DRIVE
179X

TRK00
WPRT
INDEX
READY
DIR
STEP

TR00
WPRT

I.p.
READY
DIR
STEP

WRITE
GATE

WG

D0-D7

W

INT

D

RO _ _ _
RO _ _ _

HLD

DAL0DAL7

INTREO

DRO
R E - " RE
W E - . . WE
CS _ _
CS
AI _ _
AI
A0 - - . A0
ET _ _
RES
MR

RAWRD
HLT
RCLK
DDEN
WD
EARLY
LATE
TG43

L

-

HLD
FDC-9229
HLD
SEPD
DSKD
HLT/CLK
SEPCLK FDCSEL
DENS
MINI
WDIN
EARLY
LATE

WDOUT
TEST'
P2
PI

CLKOUT
CLKIN

CLK

!

P0

h

<8!...

~V"

RAW READ

WDATA

~~

::~

..c

0-

~~
.".

16MHz
TTL INPUT
LATCH
LCUR

,.,' =:>

MOTOR ON
SIDE
SEL3
SEL2
SELl

A.

--.J
'The FDC9229/B, as all other NMOS integrated circuits, presents a high
impedance on all inputs.
To avoid soft errors caused by transmission line effects and noise where
there is long cabling between the floppy disk drive and the controller board, the
use of a (nOn-invertin~sTlL schmidt-trigger input gate or bus transceiver is
recommended at the
D input to the FDC9229/B.

STANDARD MICROSVSTEMS
CORPORATION
35MifcusBlvd.~~V1118a

(5161273·3100 TWl(·510·221·11898

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

512

FDC 92C38/92C38B
FDC 92C38T/92C38BT
PRELIMINARY

CMOS Floppy Disk Data Separator
and Clock Generator
PIN CONFIGURATION

FEATURES

o High Performance Digital Data Separator with

o
o
o
o
o
o
o
o

Synthetic Oscillator and Phase Lock Loop for
industry standard FDC 765A and FDC 7265
Performs complete data separation function for floppy
disk drives
Eliminates all adjustments normally associated with
high performance data separators
Compatible with 3.5", 5.25" and 8" drives and data
rates up to 500 KBs
Internal Crystal Oscillator Circuit provides all clocks
required by FDC 765A and FDC 7265
Fabricated in power saving CMOS
16-Bit half Cell Divide Algorithm greatly improves
performance over conventional digital designs
Single + 5 Volt supply
Fully TTL compatible

v" [

CDo
CD,
SEPClK
SEPD
ClK
WClK

[
[
[
[
[
[

1

2
3
4

5
6
7

~ DSKD
J V"
J NC
~ XTAl,
~ GND,
9 ~ XTAl,lClKIN
8 JGND,

14
13
12
11
10

14 Pin DIP

FUNCTIONAL DESCRIPTION
The FDC 92C38 is a CMOS integrated circuit designed to
complement the FDC 765A (8272A) or the FDC 7265 floppy
disk controller. It incorporates a high performance, synthetic phase locked loop digital data separator and clock
generator in one 0.3 inch wide 14 pin package.
The use of a high performance synthetic phase locked loop
data separator allows the system designer to replace (without sacrificing performance) a costly and board consuming

analog data separator (and the tuning normally required
with an analog design) with a cost effective, single chip
digital circuit.
The FDC 92C38 is available in four versions: the FDC
92C38/T which is intended for disk transfer rates up to 250
kilobits per second and the FDC 92C38B/T is intended for
disk transfer rates up to 500 kilobits per second.

513

DATA SEPARATOR
CLOCK
PRESCALER

~---i----------------------------------------+-------------~wc~
C~

FDC 92C38 BLOCK DIAGRAM

DRIVE SIZE AND
DATA RATE SELECT

'---

FLOPPY
DISK
DRIVE

RAW
DATA

I'>.:

"t;Y

CDo
CD,

SEPD

RDD

ClK

ClK

DSKD

8/16 MHz or XTAl,
TTL INPUT- XTAl2
WCLK
(XTAl 1 ONLy)

I

.

~
...J

u
a.
w
(/)

ROW

FDC92C38

The FDC92C38JB/T, as all other CMOS Integrated circUits,
presents a high impedance on all inputs
To avoid soft errors caused by transmission line effects and
noise where there is long cabling between the floppy disk drive
and the controller board, the use of a (non-inverting) TTL
schmidt-trigger input gate or bus transceiver is recommended at
the DSKD input to the FDC92C38JBfT.

TYPICAL SYSTEM IMPLEMENTATION
514

WClK

DESCRIPTION OF PIN FUNCTIONS
PIN NO.

1/0
I

SYMBOL

1
2,3

V"
COo,CO,

4

SEPClK

0

5

SEPO

0

6

ClK

0

7

WClK

0

8
9

GNO,
XTAl,lClKIN

I

10
11

GN02
XTAl2

I
I

12
13
14

NC
Voc
OSKO

I
I

DESCRIPTION

This pin MUST be tied to Voc.
These inputs select the appropriate internal clock divisor
for the data rate of the disk data, the ClK output to the
FOC and the WClK output to the FOC. Refer to Table 1.
A Square wave window clock signal output derived from
the OSKO input.
This output is the regenerated data pulse derived from the
raw data input (OSKO). To insure complete compatibility
with the FOC 765A and FOC 7265, this output is positive
going.
This output provides the clock signal for the FOC 765A or
FOC 7265.
This output provides the write clock signal for the FOC
765A or FOC 7265.
Ground
This input is for direct connection to an 8 or 16 MHz singlephase TTL level clock, or one lead from an 8 or 16 MHz
crystal.
This pin must be tied to ground.
In the FOC 92C38 and FOC 92C38B, the second lead from
an 8 or 16 MHz crystal is connected to this pin. In the FOC
92C38T and FOC 92C38BT, this pin should be left floating.
No -connection should be made to this pin.
+5 Volts
This input is the raw read data received from the drive.
(This input is active lOw.)

I

OPERATION
The high performance digital data separator incorporated
in the FDC 92C38 will accept data from the floppy disk drive
at 125 KHz, 250 KHz, or 500 KHz data rates and output the
appropriate regenerated clock and data signals.
The heart of the digital floppy disk data separator section is
a synthetic oscillator phase locked loop. One half-bit cell of
the incoming data stream corresponds to one cycle of the
synthetic oscillator. Each oscillator cycle consists nominallyof 16 phase slices. The circuit, therefore, needs a phase
slice clock with a frequency of 16 times the half-bit cell time.
Detection of an input pulse away from the center of its halfbit "slot" causes a phase correction to be applied to the synthetic oscillator, bringing the center of the half-bit slot closer
to the pulse.
INTCLK

The end-of-cycle signal from the synthetic oscillator defines
the derived clock waveform and the duration of each halfbit slot. If there is a flux transition during the half-bit slot, it
is remembered and used to regenerate the data waveform
pulses immediately following the end-of-cycle.
A short history of input pulse detections (which induce
phase corrections by the FDC 92C38) is kept. This history is
used to allow subsequent phase corrections to request
upward or downward changes in center frequency, and
helps compensate for drive speed variations. This, along
with separate short term and long term correction
algorithms, assures accurate floppy disk data separation.

S~-ULJ

!!

t
SEPCLK ~
1

I

I

I

II

I

SEPD _ _---===---!r-l

a:=~ ~l

:,c: i
I

J-+-

I

I

I

I

i

i
I

I

I
I

~L

_____________

I
:

I~ always 4 internal clock cycles

iii

515

I
I

I
1

~r-oL-

_ _ _ _ __

MAXIMUM GUARANTEED RATINGS
Operating Temperature Range .................................................................................................................................................................... O°C to + 70°C
Storage Temperature Range ................................................................................................................................................................. -55°C to + 150°C
Lead Temperature (soldering, 10 sec.) .......,......................................................................................................................................................... + 300°C
Positive Voltage on any I/O Pin, with respect to ground ........................................................................................................................... Vee + 0.3V
Negative Voltage on any I/O Pin, with respect to ground .................................................................................................................................... -{).3V
Maximum Vee ....................................................................................................................................................................................................................... + 7V
Power Dissipation ............................................................................................................................................................................................................. 0.25W
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not
be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power
is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output.

INPUT VOLTAGE
Low (V,,)
High (V'H)
XTAUClKIN INPUT
Low (V,J
High (V'H)
E
Low (Vo,)
High (VOH )
POWER SUPPLY CURRENT
I..
INPUT lEAKAGE CURRENT
I"

-0.3
2.0

O.B
V..

V

-0.3
3.2

1.5
V..

V
V

0.4

V

2.4

Except XTAUClKIN

La, =1.6 ma, except
~ = 0.4 ma, ClK only
LaH = -100""a, except ClK
LaH = - 400""a, ClK only

TBD
TBD
TBD

CHARACTERISTICS

(All times assume XTAUClKIN = 16 MHz unless
otherwise specified)

ClKIN Frequency

3.95
3.95

ClKIN Duty Cycle

40

TCU

DRIVE

7265 or
765 (8272)

J

r=

WP/TS

(::)

FRISTP
LCTIDIR

N T _ INT

USI

C S - CS
R D _ RD
W R _ WR
A0~ A0
oR O _ DRO
OACK ........ DACK

US0

2 SIDED
WPRT
TRK00
FAULT

FAULT
RST
STEP
lOW CUR
DIR

roE

DRSEL4

C
0
D
E
R
~

HDL
FDC92C39

RDY ~RDY
IDX
IDX
WE
WE
HD
SIDE SEL
+5V

r---

r--r---

TC ........ TC
ET __
RST
RES

EARLY
LATE
-SEPCLK OSKD

ROD

SEPO

CLK

II

~ MINI
DENS
CLKOUT
HLT/CLK

P2
PI

XTAL 1

P0
XTAL2

!

!

16 MHzXTAL
OR
TTL INPUT
(XTAL 1 ONLY)

LATCH

-'\

HLD

.,...

~
~

WDATA

RAW
READ

o-r-

~~r~~r_0-

~

RDY
IDY
WE
SIOESEL

-.I

DRSEL3
DRSEL2
DRS ELI

1

FDCSEL
WDOUT
WDIN

WDA
PS0
PSI
RDW

MFM
WCK

00-D7

G2

-1t1- -B?L

RW/SEEK
DB0DB7

1t

r

FLTlTR0

D0D7

Gl

ROY
lOX
WE
SIDE

MOTOR
ON
A

~
*The FOC 92C39/B, as all other NMOS integrated circuits, presents a high
impedance on all inputs.
To avoid soft errors caused by transmission line effects and noise where
there is long cabling between the floppy disk drive and the controller board, the
use of a (non-inverting) TIL schmidt·-lrigger input gate or bus transceiver is
recommended at the DSKD input to 'the FDC 92C39/B.

523

TYPICAL SYSTEM IMPLEMENTATION-179X FOC OR 979X FOC
DRIVE
179X

READY
DIR
STEP

TRK00
WPRT
INDEX
READY
DIR
STEP

WG

WRITE
GATE

TR00
WPRT

I.p.

D0-D7

W

HLD

HLD

DAL0DAL7

FDC92C39

RAWRD
HLT
RO _ _ _
INT
INTREO
RCLK
RO _ _ _
D
DRO
RE ____
DDEN
RE
WE ____
WE
CS ____
CS
WD
A1 ____
A1
EARLY
A0 _ _
A0
LATE
ET ___
TG43
RES
MR

~ HLD
SEPD
HLT/CLK
DSKD
SEPCLK FDCSEL

----

DENS
MINI
WDIN
EARLY
LATE

WDOUT

P2
P1

CLK

CLKOUT
XTAL 1

PO
XTAL2

~16MHJ

h

<8!.-

RAW READ

~ WDATA

~~....

tgE

....
.".

OR
TTL INPUT
(XTAL 1 ONLY)

LATCH

LCUR
MOTOR ON
SIDE
SEL3
SEL2
SEL1

~D'~
A

-----1
'The FDC 92C39/B, as all other CMOS integrated circuits, presents a high
impedance on all inputs.
To avoid soft errors caused by transmission line effects and noise where
there is long cabling between the floppy disk drive and the controller board, the
use of a (non-inverting) TTL schmidt-trigger input gate or bus transceiver is
recommended at the DSKD input to the FDC 92C39/B.

Circuit diagrams utilizing SMC products are included as a means o~ illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

524

FDC9266

Single/Double Density Enhanced Floppy Disk
Controller
PIN CONFIGURATION
FEATURES

o Combination Floppy Disk Controller and Floppy Disk Interface
o Software compatible with industry standard FDC 765A
o On chip digital data separator
o
o

o
o
o
o

o
o
o

eliminates critical analog
adjustments
On-chip drive control logic
reduces component count.
IBM compatible in both single
and double density recording
formats
Programmable data record
lengths: 128, 256, 512, or 1024
bytes/sector
Multi-sector and multi-track
transfer capability
Controls up to 4 floppy disk drives
Data Scan Capability-will scan a
single sector or entire track's
worth of data fields, comparing
on a byte by byte basis, data in
the processor's memory with the
data read from the diskette
Data transfers in DMA or nonDMAmode
Single 8 MHz TTL clock input
Single + 5 Volt power supply

HDl
FRlSTP
lCT/DtR
RW/SEEK
Vee
NC
RST
RD
WR

CS

40

3938373635343332313029
28

1

2

3
4
5

A,

rErErErffriI

U

rifrifmOI"

ooooozooogs.~

RESET 1
RD 2
WI'i 3
C'S 4
A, 5
WE
DB, 6
P0
DB, 7
DSKD
DB, 8
ClK
DB, 9
MINI
DB,10
NC
DB,ll
GND
DB,12
TEST
DB,13
tNT
ORO 14
lOX
DA<::K 15
TC
TC 16
lOX 17
INT 18
TEST 19
GND 20

PACKAGE: 44-pin PlCC

o Parallel Seek operations on up to
four drives
o Compatible with most
microprocessors

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Vee
RW/SEEK
lCT/DIR
FRISTP
HDl
ROY
WP/TS
FlT/TR,
P2
PI
WDOUT
US,
Us,
HD
MFM
WE
P0
DSKD
ClK
MINI

PACKAGE: 4O-pin D.I.P.

o COPLAMOS® n-channel silicon
gate technology
o Available in 40-pin Dual-in-Line
package and 44-pin PLCC

GENERAL DESCRIPTION
The FDC 9266 is a monolithic combination of the industry
standard FDC 765A Floppy Disk Controller and the FDC
9229 Floppy Disk Interface Circuit. It preserves all of the
processor hardware and software interfaces to the FDC
765A, and contains on-chip circuitry to simplify drive
interfacing.
These on-chip enhancements include a digital data
separator, compatible with 5.25" and 8" drives. The data
separator separates both FM (Single Density) and MFM
(Double Density) encoded data, and requires no external
adjustments.
The FDC 9266 also allows variable write precompensation,
which is track selectable.
These enhancements greatly reduce the number of components required to interface floppy disks to a microprocessor system.
There are 15 separate commands which the FDC 9266 will
execute. Each of these commands requires multiple 8-bit

bytes to fully specify the operation which the processor
wishes the FDC to perform. The following commands are
available:
Read Data
ReadlD
Read Deleted Data
Read a Track
Scan Equal
Scan High or Equal
Scan Low or Equal
Specify

Write Data
Format a Track
Write Deleted Data
Seek
Recalibrate (Restore to Track 0)
Sense Interrupt Status
Sense Drive Status

Address mark detection circuitry is internal to the FDC
which simplifies the read electronics. The track stepping
rate, head load time, and head unload time may be programmed by the user. The FDC 9266 offers many additional features such as multiple sector transfers in both read
and write with a single command, and full IBM compatibility
in both single and double density modes.

525

I

DBa.,

REGISTERS

DATA
SEPARATOR

SERIAL
INTERFACE
CONTROLLER

OAQ

AND
PRECOMP
LOGIC

om

DSK DATA
WDOUT
PO

PI
P2

INT

ii1i
W-

READV
WRITE PROTECT/TWO SlOE
INDEX
FAULT/TRACK 0
MINI

'0
RESET

Co
elK
Vee
GNO

--

UNIT SELECT 0
UNIT SELECT 1
MFMMODE
RwISEEK
HEAD LOAD

-

HEAD SELECT

LOW CURRENT/DIRECTION
FAULT RESET/STEP

BLOCK DIAGRAM

DRIVE
2 SIDED

S:==========~WPRT

TRK 00
FAULT

FOC 9266

r:==================~~FITRST
~

RW/SEEK

DB0-DB7

P0
P1
P2

OB0OB7

ROY
lOX
WE
HO
HOL
INT

INT

CS
AD

CS
AD
WR

WR
A0
ORO

A0

STEP

t - - - - - - - - - -......-t 0IR
t---1~------......-tLOWCUR

WP/TS
FLTfTR0
FRISTEP
LCTIDIR

PRECOMPENSATION
SELECT
ROY
lOX
WE
SIDE SEL
__________________________________________

=

~

~HLO

~~~~~~~~~~~~DRSEL4

US1

ORSEL3
DRSEL2
DRSEL1

US0

OSKO

RAW READ

ORO

OACK
TC
RESET

TC
RST

MINI
MFM

ROY
lOX
WE
SIDE SEL

LATCH

r-_________
OB0-0B7

TYPICAL APPLICATION
526

~~MOTORON

DESCRIPTION OF PIN FUNCTIONS

1

PIN
SYMBOL
RST

2

Reset

INPUT/
OUTPUT
Input

CONNECTION
TO
Processor

RD

Read

Input~

Processor

3

WR

Write

Input®

Processor

4

CS

Chip Select

Input

Processor

5

Ao

Data/Status Reg
Select

Input~

Processor

DBo-DB,

Data Bus

Processor

14

DRO

DMA

15

DACK

DataDMA
Request
DMA
Acknowledge

Input®
Output
Output
Input

DMA

16

TC

Terminal Count

Input

DMA

17

IDX

Index

Input

FDD

18

INT

Interrupt

Output

Processor

19

TEST

Test

Input

20
21

GND
MINI

Ground
Mini

Input

22

ClK

8MHz
TTL Clock
Raw Data
Precompensation
Select

Input
Input
Input

FDD
Processor

NO·CD

6-13

23
24,31,32

DSKD
PO, P1, P2

NAME

Processor

25
26

WE
MFM

Write Enable
MFM Mode

Output
Output

FDD

27

HD

Head Select

Output

FDD

US" USo
WDOUT
FlTITRo

Unit Select
Write Data Out
FaultlTrack 0

Output
Output
Input

FDD
FDD
FDD

WP/TS

Write Protect/
Two-Side

Input

FDD

28,29
30
33

34

NOTES:

CD

®

For DIP package.
Disabled when CS=1.

527

FUNCTION
Places FDC in idle state. Resets
output lines to FDD to "0" (low).
Does not effect SRT, HUT or HlT
in Specify command. If RDY pin is
held high during Reset, FDC will
generate interrupt 1.024 ms later.
To clear this interrupt use Sense
Interrupt Status command.
Control signal for transfer of data
from FDC to Data Bus, when
"0" (low).
Control signal for transfer of data to
FDC via Data Bus, when "0" (low).
IC selected when...::.Q:' (low),
allowing RD and WR to be
enabled.
Selects Data Reg (Ao = 1) or
Status Reg (Ao = 0) contents of
the FDC to be sent to Data Bus.
Bi-DirectionaI8-Bit Data Bus.
DMA Request is being made by
FDC when DRW = "1'.
DMA cycle is active when "0" (low)
and Controller is performing DMA
transfer.
Indicates the termination of a DMA
transfer when "1" (high). It
terminates data transfer during
Read/Write/Scan command in
DMA or interrupt mode.
Indicates the beginning of a disk
track.
Interrupt Request Generated by
FDC.
This pin is for test purposes only.
Should be left tied high in normal
operation.
D.C. Power Return.
This input, when set to "1" (high),
configures the FDC for operation
with 5.25" floppies. If reset to "0"
(low), then the FDC is configured
for 8" drive operation.
Device clock.
Raw data from drive.
These pins select the amount of
precompensation applied to the
write data.
Enables write data into FDD.
MFM mode when "1;' FM mode
when "0."
Head 1 selected when "1" (high).
Head 2 selected when "0" (low).
FDD Unit Selected.
Serial clock and data bits to FDD.
Senses FDD fault condition, in
Read/Write mode; and Track 0
condition in Seek mode.
Senses Write Protect status in
Read/Write mode; and Two Side
Media in Seek mode.

DESCRIPTION OF PIN FUNCTIONS
PIN
SYMBOL

NO.(j)

INPUT/

CONNECTION
TO

OUTPUT

NAME

35

RDY

Ready

Input

FDD

36

HDL

Head Load

Output

FDD

37

FR/STP

Fit Reset/Stop

Output

FDD

38

LCT/DIR

Low Current/
Direction

Output

FDD

39

RW/SEEK

Read Write/SEEK

Output

FDD

40

Vee

+5V

®

NOTES: (j) For DIP package.

FUNCTION

Indicates FDD is ready to send or
receive data.
Command which causes read/
write head in FDD to contact
diskette.
Resets fault F.F. in FDD in Read/
Write mode, contains stop pulses
to move head to another cylinder in
Seek mode.
Lowers Write current on tracks;;:::42
in Read/Write mode, determines
direction head will stop in Seek
mode. A fault reset pulse is
issued at the beginning of each
Read or Write command prior to
the occurrence of the Head Load
signal.
When "I" (high) Seek mode
selected and when "0" (low) Read/
Write mode selected.
DC Power.

-

Disabled when GS=I.

DESCRIPTION OF INTERNAL REGISTERS
The FDG 9266 contains two registers which may be accessed by the main system processor; a Status Register
and. a Data Register. The 8-bit Main Status Register contains the status information of the FDC, and may be
accessed at any time. The 8-bit Data Register (actually
consists of several registers in a stack with only one register
presented to the data bus at a time), which stores data,
commands, parameters, and FDD status information. Data
bytes are read out of, or written into, the Data Register in
order to program or obtain the results after a particular command. The Status Register may only be read and used to

facilitate the transfer of data between the processor and
FDC9266.
The relation~ between the Status/Data registers and the
signals RD, WR, and Ao is shown below.

A.

RD

WR

0
0
0

0
1
0
0
0
1

1
0
0
0
1
0

1

1
1

FUNCTION

Read Main Status Register
Illegal
Illegal
Illegal
Read from Data Register
Write into Data Register

The bits in the Main Status Register are defined as follows:
BIT NUMBER
DBo

NAME

FDDO Busy

SYMBOL

DESCRIPTION

FDD number 0 is in the Seek mode. If any of the bits is set
FDG will not accept read or write command.
DB,
FDD 1 Busy
FDD number 1 is in the Seek mode. If any of the bits is set
D,B
FOG will not accept read or write command.
DB,
FDD 2 Busy
D,B
FDD number 2 is in the Seek mode. If any of the bits is set
FDC will not accept read or write command.
DB,
FDD 3 Busy
FDD number 3 is in the Seek mode. If any of the bits is set
D,B
FOG will not accept read or write command.
DB,
FDG Busy
A read or write command is in process. FDC will not accept
GB
any other command.
.
Execution Mode
This bit is set only during execution phase in non-DMA mode.
DB.
EXM
When DB, goes low, execution phase has ended, and result
phase was started. It operates only during NON-DMA mode
of operation.
Data Input/Output
Indicates direction of data transfer between FDC and Data
DB.
010
Register. If DIO = "I" then transfer is from Data Register to
the Processor. If 010 = "0", then transfer is from the
Processor to Data Register.
DB,
Request for Master
Indicates Data Register is readYt to send or receive data to or
ROM
from the Processor. Both bits D 0 and ROM should be used
to perform the hand-shaking functions of "ready" and
"direction" to the processor.
The DIO and ROM bits in the Status ~ister indicate when Data is ready and in which direction data will be transferred on the Data
Bus. The max time between the last RD or WR during command or result phase and 010 and ROM getting set or reset is 12 fLs. For
this reason every time Main Status Register is read the CPU should wait 12 fLs. The max time from the trailing edge of the last RD in
the result phase to when DB, (FOG Busy) goes low is 12 fLs.
DoB

528

COMMAND SEQUENCE
The FOC 9266 is capable of performing 15 different commands. Each command is initiated by a multi-byte transfer
from the processor, and the result after execution of the
command may also be a mUlti-byte transfer back to the processor. Because of this multi-byte interchange of information between the FOC 9266 and the processor, it is
convenient to consider each command as consisting of three
phases:

Out FoC and Into Processor
Data InfOut
(010)

Command Phase:
Notes:

0

-Data register ready to be written into by processor

Execution Phase:

[[] -Data register not ready to be written into by processor
@]-DataregisterreadYfOrnextdatabytetobereadbY the processor
[[] -Data reg1ster not ready for next data byte to be read by processor

Result Phase:

COMMAND SYMBOL DESCRIPTION
SYMBOL

The FOC receives all information
required to perform a particular
operation from the processor.
The FOC performs the operation
it was instructed to do.
After completion of the operation,
status and other housekeeping
information are made available to
the processor.

A"

NAME
Address Line 0

DESCRIPTION
Ao controls selection of Main Status Register (Ao = 0) or Data Register

C

Cylinder Number

0
D7-DO

Data
Data Bus

DTL

Data Length

EOT

End ofTrack

GPL

Gap Length

H
HD

Head Address
Head

HLT

Head Load Time

HUT

Head Unload Time

MF
MT

FM or MFM Mode
Multi-Track

N
NCN

Number
New Cylinder Number

ND
PCN
R
RIW
SC
SK
SRT

Non-DMA Mode
Present Cylinder
Number
Record
Read/Write
Sector
Skip
Step Rate Time

STO
ST1
ST2
ST3

Status 0
Status 1
Status 2
Status 3

C stands for the current/selected Cylinder (track) number 0 through 76 of
the medium.
o stands for the data pattern which is going to be written into a Sector.
8-bit Data Bus, where D7 stands for a most significant bit, and Do stands for a
least significant bit.
When N is defined as 00, OTL stands for the data length which users are
going to read out or write into the Sector.
EOT stands for the final Sector number on a Cylinder. During Read or Write
operation FDC will stop date transfer after a sector # equal to EOT.
GPL stands for the length of Gap 3. During ReadlWrite commands this value
determines the number of bytes that VCOs will stay low after two CRC bytes.
During Format command it determines the size of Gap 3.
H stands for head nu_mber 0 or 1, as specified in ID field.
HD stands for a selected head number 0 or 1 and controls the polarity of pin
27. (H = HD in all command words.)
HLT stands for the head load time in the FDD (2 to 254 ms in 2 ms
increments).
HUT stands for the head unload time after a read or write operation has
occurred (16 to 240 ms in 16 ms increments).
If MF is low, FM mode is selected, and if it is high, MFM mode is selected.
If MT is high, a multi-track operation is to be Berformed. If MT = 1 after
finishing ReadlWrite operation on side 0 FD will automatically start
searching for sector 1 on side 1.
N stands for the number of data bytes written in a Sector.
NCN stands for a new Cylinder number, which is~Oing to be reached as a
result of the Seek operation. Desired position of ead.
ND stands for operation in the Non-DMA Mode.
PCN stands for the Cylinder number at the completion of SENSE
INTERRUPT STATUS Command. Position of Head at present time.
R stands for the Sector number, which will be read or written.
R/W stands for either Read (R) or Write (W) signal.
SC indicates the number of Sectors per Cylinder.
SK stands for Skip Deleted Data Address Mark.
SRT stands for the SteWing Rate for the FDD. (1 to 16 ms in 1 ms
increments~) Steppir:!9 ate applies to all drives, (F = 1 ms, E = 2 ms, etc.).
ST 0-3 stand for one of four registers which store the status information after
a command has been executed. This information is available durin~the
result phase after command execution. These registers should not e
confused with the main status register (selected by A" = 0). ST 0-3 may be
read only after a command has been executed and contain information
relevant to that particular command.
During a Scan operation, if STP = 1, the data in continguous sectors is
compared byte by byte with data sent from the processor (or DMA); and if
STP = 2, then alternate sectors are read and compared.
US stands for a selected drive number 0 or 1.

STP
USO, US1

Unit Select

(A"

= 1).

529

INSTRUCTION SET CD @
PHASE

RIW

I
I

I

DATA BUS

07

06 05 04

03 02

01

DO

I
REMARKS

Command

W

MT

MF SK

R/W

07

Command

W

o

W

X

06

Os D

0

W

XXXXHOUS1USO

====:R'====
---------N---------

w
w

-------EOT:=====
-=====GPL
-

Command Codes

Sector 10 information prior

W

to Command execution. The

W

4 bytes are commanded against

W

header on Floppy Oisk.

W
W
W

Data-transfer between the
FDD and main-system

---------5TO::::::::::
--------ST
1

R C,==
R

H

R
R

W

w
w
w

R
R
R
R
R
R

Command execution

R
N

w
w
w
w
w

Execution
Relult
R

R

MT

MF SK
X

X

0
X

HD US1

usa

====:~,====

-------N--------

===:EOT·--====
=
---------DTL------------------STO----------

=::::::~~ ~:=::::::=
===~======

to Command execution. The
4 bytes are commanded against
header on Floppy Disk.

W

MT

Result

Data-transfer between the
F DO and main-system

Sector ID information after
Commend execution

XXXXXHOUS1USO

===H======
--------R--------EOT
------N{~~~~~
--------GPL
--------DTL

w
Execution

R
R
R
R

Status information after
Command execution

Command Codes

HO US1

USO

Data-transfer between t he
FOO and main-svstem_ FOC
reads all data fialds
from index hole to Ear •
Status information after
Command execution
Sector 10 information after
Command execution

N

o

MF

0

a

X

x

x

X

Commands

X

HO US1

usa

---------STO------===-STST2'====
=
-------C--------H

The first correct 10 information
on the Cylinder is stored in
Data Register
Status information after
Command execution
Sector 10 information read
during Execution Phase from
Floppy Disk

N

FORMAT A TRACK
Command

a

W
W

Sector 10 information prior
to Command execution. The
4 bytes are commanded against
header on Floppy Disk.

Sector 10 information prior
to Command execution

R

R

MF
X

a a
X

Command Codes

X

X

HO USt

USO
Bvtes/Sector
Sectors/Track
Gap 3
Filler Byte

w

Command Codes

w
w
w
w
w

a a
X

w

0

W

w

0

X

Execution

N

0

X

H

w
w

GPL-

MF

REMARKS

READ 10
Command

Sector 10 information prior

WRITE DATA
Command

X

Command Codes

X

R
R

R

MF SK

------ST 0---------------ST
,-------------S~2~=====

Result
Sector 10 information after

READ DELETED DATA
Command

DD

Execution

Slatus information after
Command execution

ST 2

R

D

~~'====
-EOT~
DTL
=====GPL

W

DTL

Execution

Result

0:1 02

READ A TRACK

0

w
w
w
w
w

J

DATA BUS

PHASE

READ DATA

w
w
Execution

FOC formats an entire track

====STO====
=
ST'
--------ST2----------

Result
R

R
R

====C====

W
W

MT MF SK
X
X
X

R
R
R

Data-transfer between the
main-system and FOO

Status information after
Command execution
In this case, the 10 information
has no meaning

R
N

SCAN EQUAL

R
R

Result

ST 0
ST 1

ST2------

R

R

C

R

H

R
R

R
N

Status information after
Command execution

Command

w

Sector 10 information after
Command execution

MF

X

X

W

==
DTL
==::-:GPL====
=

W
W
Execution
Result

~:

a

MT

W
W
W
W

R
R
R
R
R
R
R

0
X

a

W
W

1

X

X HO US1

1

Command

Codes

11

~E~:;=T

ST'ST2 ====:
§ STO'
~====

0

0

HO US1

1

C

H
R ----------

W
W

EOT
GPL.---------

N-:=====

Data-compered between the
FOD and maln-system

Result

R

R
R

Data-transfer between the
FOO and main-svstem
Status information aft8'l'
Command execution
Sec~or 10 information after
Commend execution

=====::-:~======

G)

Symbols used in thil table ere dncrit.d at the end of thlsl8Ction.

<%I

AO should equel blNry 1 for ell operations.

~ X ,. Don't ca.... Ulually made to equal binary O.

530

Sector 10 information prior
to Command execution

STP ----------

Execution
Sector 10 information prior
to Command execution. The
4 bytes are commanded against
header on Floppy Disk.

Command Codes

usa

W

W

usa

C

0
X

W

W

WRITE DELETED DATA
Command

1
X

=====E!=====

~:====
--------N---------

Status information after
Command execution
Sector 10 information after
Command execution

INSTRUCTION SET (CONT.)
I
PHASE

R/W

Os

06 0

03

I

I

DATA BUS
0,

02

D

DO

REMARKS
RECAL.IBRATE

SCAN LOW OR eQUAL

Command

W
W

MT

M'

SK

1

X

X

X

1

HD

US1

Command

Command Codes

usa
Sector 10 information prior
Command execution

W
W
W
W
W
W
W

J

DATA BUS

REMARKS

W

a a

0

,

w

X

X

0

X

Command Codes
US,

uso
Head retracted to Track 0

Execution

SENSE INTERRUPT STATUS

Command

o

W

0

Command Codes

0

'OT

Status information at the end
of seek-oparation about the FOC

STO

Result

GPL

PCN

5TP

SPECIFY

Execution

o
SAT
HlT

Result

0

0

Command Codes

0
HUT

....

.. ND
SENSE DR IV E STATUS

X

o

0

0

X

X

X

Command Codes

1

HD lJS1

usa

5T 3

Status information about FOD

SEEI;<
Command

W
W
W
W
W
W
W
W
W

o

0

X

X

1
X

HO

USl

----NCN----Head is positioned over
proper Cylinder on
Diskette

====N===
===~'OT======
GPl
----5TP-----

Execution

Data-compared

between the I-c:-o-m-m-'".,dr--:-W....,.:.:.:.:.:.:..-I,..OV-.I,..id,.,~,;.~:.,.;:.,.;L=ID======"T":-,"-"':-'id"'c"'o-m-m,-o":'d"'CO""d-,,---I

F DO and main-system
Result

Command Codes

usa

----5TO-------5T1----

Status information after
Command execution

=====:C=====:

Sector ID information after
Command execution

(NoOp _ FDe goes into
Standby State)
Result

-------~2--------

---------5TO---------

ST 0 = 80
{161

FUNCTIONAL DESCRIPTION OF COMMANDS
Read Data
A set of nine (9) byte words are required to place the FDC
into the Read Data Mode. After the Read Data command
has been issued the FDC loads the head (if it is in the
unloaded state), waits the specified head settling time
(defined in the Specify Command), and begins reading ID
Address Marks and ID fields. When the current sector number ("R") stored in the ID Register (IDR) compares with the
sector number read off the diskette, then the FDC outputs
data (from the data field) byte-to-byte to the main system
via the data bus.
After completion of the read operation from the current sector, the Sector Number is incre'mented by one, and the data
Multi-Track
MT

MFM/FM
MF

Bytes/Sector
N

0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1

00
01
00
01
01
02
01
02
02
03
02
03

from the next sector is read and output 01'\ the data bus. This
continuous read function is called a "Multi-Sector Read
Operation:' The Read Data Command may be terminated
by the receipt of a Terminal COl!!J~nal. TC should be
issued at the same time that the DACK for the last byte of
data is sent. Upon receipt of this signal, the FDC stops outputting data to the processor, but will continue to read data
from the current sector, check CRC (Cyclic Redundancy
Count) bytes, and then at the end of the sector terminate
the Read Data Command.
The amount of data which can be handled with a single
command to the FDC depends upon MT (multi-track), MF
(MFM/FM), and N (Number of Bytes/Sector). Table 1 below
shows the Transfer Capacity.
Maximum Transfer Capacity
(Bytes/Sector) (Number of
Sectors)
(128) (26) = 3,328
(256) (26) = 6,656
(128) (52) = 6,656
(256) (52) = 13,312
(256) (15) = 3,840
(512)(15) = 7,680
(256) (30) = 7,680
(512) (30) = 15,360
(512) (8) = 4,096
(1024) (8) = 8,192
(512) (16) = 8,192
(1024) (16) = 16,384

Table 1. Transfer Capacity
531

Final Sector
Read
from Diskette
26 at Side 0
or 26 at Side 1
26 at Side 1
15 at Side 0
or 15 at Side 1
15 at Side 1
8atSideO
or8 at Side 1
8 at Side 1

The "multi-track" function (MT) allows the FDC to read data
from both sides of the diskette. For a particular cylinder, data
will be transferred starting at Sector 1, Side 0 and completing at Sector L, Side 1 (Sector L = last sector on the side).
Note, this function pertains to only one cylinder (the same
track) on each side of the diskette.
When N = 0, the DTL defines the data length which the
FDC must treat as a sector. If DTL is smaller than the actual
data length in a Sector, the data beyond DTL in the Sector,
is not ~ent to the Data Bus. The FDC reads (internally) the
complete Sector performing the CRC check, and depending upon the manner of command termination, may perform a Multi-Sector Read Operation. When N is non-zero,
then DTL has no meaning and should be set to FF
Hexidecimal.
At the completion of the Read Data command, the head is
not unloaded until after Head Unload Time Interval (specified in the Specify Command) has elapsed. If the processor
issues another command before the head unloads then the
head settling time may be saved between subsequent
reads. This time out is particularly valuable when a diskette
is copied from one drive to another.
If the FOC detects the Index Hole twice without finding the
right sector, (indicated in "R"), then the FDC sets the ND
(No Data) flag in Status Register 1 to a 1 (high), and terminates the Read Data Command. (Status Register 0 also has
bits 7 and 6 set to 0 and 1 respectively.)
After reading the ID and Data Fields in each sector, the FDC
checks the CRC bytes. If a read error is detected (incorrect
CRC in ID field), the FDC sets the DE (Data Error) flag in
Status Register 1 to a 1 (high), and if a CRC error occurs in
the Data Field the FDC also sets the DD (Data Error in Data
Field) flag in Status Register 2 to a 1 (high), and terminates
the Read Data Command. (Status Register 0 also has bits
7 and 6 set to 0 and 1 respectively.)

Write Data
A set of nine (9) bytes are required to set the FDC into the
Write Data mode. After the Write Data command has been
issued the FDC loads the head (if it is in the unloaded state),
waits the spec'/fied Head Settling Time (defined in the
Specify Command), and begins reading ID Fields. When all
four bytes loaded during the command (C, H, R, N) match
the four bytes of the ID field from the diskette, the FDC takes
data from the processor byte-by-byte via the data bus, and
outputs it to the FDD.
After writing data into the current sector, the Sector Number
stored in "R" is incremented by one, and the next data field
is written into. The FDC continues this "Multi-Sector Write
Operation" until the issuance of a Terminal Count Signal. If
a Terminal Count signal is sent to the FDC it continues writing into the current sector to complete the data field. If the
Terminal Count signal is received while a data field is being
written then the remainder of the data field is filled with 00
(zeros).
The FDC reads the ID field of each sector and checks the
CRC bytes. If the FDC detects a read error (incorrect CRC)
in one of the ID Fields, it sets the DE (Data Error) flag of
Status Register 1 to a 1 (high), and terminates the Write Data
Command. (Status Register 0 also has bits 7 and 6 set to 0
and 1 respectively.)
The Write Command operates in much the same manner
as the Read Command. The following items are the same,
and one should refer to the Read Data Command for details:
• Transfer Capacity
• EN (End of Cylinder) Flag

If the FDC reads a Deleted Data Address Mark off the diskette, and the SK bit (bit D5 in the first Command Word) is
not set (SK = 0), then the FDC sets the CM (Control Mark)
flag in Status Register 2 to a 1 (high), and terminates the
Read Data Command, after reading all the data in the Sector. If SK = 1, the FDC skips the sector with the Deleted
Data Address Mark and reads the next sector. The CRC bits
in the deleted data field are not checked when SK = 1.
During disk data transfers between the FDC and the processor, via the data bus, the FDC must be serviced by the
processor every 27 fJ,s in the FM Mode, and every 13 fJ,S in
the MFM Mode, or the FDC sets the OR (Over Run) flag in
Status Register 1 to a 1 (high), and terminates the Read
Data Command.
lithe processor terminates a read (or write) operation in the
FDC, then the ID Information in the Result Phase is
dependent upon the state of the MT bit and EOT byte. Table
2 shows the value for C, H, R, and N, when the processor
terminates the Command.
10 Information at Result
Final Sector
Phase
Transferred to
MT HO
Processor
C
H
R
N
0
Less than EOT
NC
NC R + 1 NC
EqualtoEOT
NC R = 01 NC
0
C+1
0
1
Less than EOT
NC
NC R + 1 NC
1
NC R = 01 NC
Equal to EOT
C+1
Less than EOT
NC
NC R + 1 NC
0
EqualtoEOT
NC
LSB R = 01 NC
0
0
1
Less than EOT
NC
NC R + 1 NC
1
EqualtoEOT
C+1 LSB R = 01 NC
Notes: 1. NC (No Change): The same value as the one at the
beginning of command execution.
2. LSB (Least Significant Bit): The least significant bit of
H is complemented.

• ND (No Data) Flag
• Head Unload Time Interval
• ID Information when the processor terminates command
(see Table 2)
• Definition of DTL when N = 0 and when N -4= 0
In the Write Data mode, data transfers between the processor and FDC, via the Data Bus, must occur every 27 fJ,S in
the FM mode, and every 13 fJ,S in the MFM mode. If the time
interval between data transfers is longer than this then the
FDC sets the OR (Over Run) flag in Status Register 1 to a
1 (high), and terminates the Write Data Command. (Status
Register 0 also has bit 7 and 6 set to 0 and 1 respectively.)

Write Deleted Data
This command is the same as the Write Data Command
except a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address
Mark.

Read Deleted Data
This command is the same as the Read Data Command
except that when the FDC detects a Data Address Mark at
the beginning of a Data Field and SK = 0 (low), it will read
all the data in the sector and set the CM flag in Status Register 2 to a 1 (high), and then terminate the command. If SK
= 1, then the FDC skips the sector with the Data Address
Mark and reads the next sector.

Read A Track
This command is similar to READ DATA Command except
that this is a continuous READ operation where the eritire

532

Sector Size
N SC GPL R), and the scan operation is continued. The scan operation continues until one
of the following conditions occur; the conditions for scan are
met (equal, low, or high), the last sector on the track is
reached (EaT), or the terminal count signal is received.

The rate at which Step Pulses are issued is controlled by
SRT (Stepping Rate Time) in the SPECIFY Command. After
each Step Pulse is issued NCN is compared against PCN,
and when NCN = PCN, then the SE (Seek End) flag is set
in Status Register 0 to a 1 (high), and the command is terminated. At this pOint FDC interrupt goes high. Bits DBo·
DBa in Main Status Register are set during seek operation
and are cleared by Sense Interrupt Status command.
During the Command Phase of the Seek operation the FDC
is in tne FDC BUSY state, but during the Execution Phase
it is in the NON BUSY state. While the FDC is in the NON
BUSY state, another Seek Command may be issued, and
in this manner parallel seek operations may be done on
up to 4 Drives at once. No other command could be issued
for as long as FDC is in process of sending Step Pulses to
any drive.
If an FDD is in a NOT READY state at the beginning of the
command execution phase or during the seek operation,
then the NR (NOT READY) flag is set in Status Register 0
to a 1 (high), and the command is terminated after bits 7
and 6 of Status Register 0 are set to 0 and 1 respectively.
If the time to write 3 bytes of seek command exceeds 150
IJ-S, the timing between first two Step Pulses may be shorter
than set in the Specify command by as much as 1 ms.

If the conditions for scan are met then the FDC sets the SH
(Scan Hit) flag Status Register 2 to a 1 (high), and terminates the Scan Command. If the conditions for scan are not
met between the starting sector (as specified by R) and the
last sector on the cylinder (EOT), then the FDC sets the SN
(Scan Not Satisfied) flag of Status Register 2 to a 1 (high),
and terminates the Scan Command. The receipt of a TERMINAL COUNT signal from the Processor or DMA Controller during the scan operation will cause the FDC to
complete the comparison of the particular byte which is in
process, and then to terminate the command. Table 4 shows
the status of bits SH and SN under various conditions of
SCAN.
COMMAND
Scan Equal
Scan Low or
Equal
Scan High or
Equal

STATUS REGISTER 2
COMMENTS
81T2
SN 81T3 = SH
0
1
DFOD = DpROCESSOR
1
0
DFOD 4= DpROCESSOR
1
0
DFOD = DpROCESSOR

=

0

0
0
1
0
0

1

0
0
1

DF~D

DFDD

< DpROCESSOR
> DpROCESSOR

DFDD

=

DpROCESSOR

> DpROCESSOA
DFDD < DpROCESSOA
DFDD

Table 4
If the FDC encounters a Deleted Data Address Mark on one
of the sectors (and SK = 0), then it regards the sector as
the last sector on the cylinder, sets CM (Control Mark) flag
of Status Register 2 to a 1 (high) and terminates the command. If SK = 1, the FDC skips the sector with the Deleted
Address Mark, and reads the next sector. In the second case
(SK = 1), the FDC sets the CM (Control Mark) flag of Status Register 2 to a 1 (high) in order to show that a Deleted
Sector had been encountered.
When either the STP (contiguous sectors = 01. or alternate sectors = 02 sectors are read) or the MT (Multi-Track)
are programmed, it is necessary to remember that the last
sector on the track must be read. For example, if STP = 02,
MT = 0, the sectors are numbered sequentially 1 through
26, and we start the Scan Command at sector 21 ; the following will happen. Sectors 21,23 and 25 will be read, then
the next sector (26) will be skipped and the Index Hole will
be encountered before the EOT value of 26 can be read.
This will result in an abnormal termination of the command.
If the EOT has been set at 25 or the scanning started at
sector 20, then the Scan Command would be completed in
a normal manner.
During the Scan Command data is supplied by either the
processor or DMA Controller for comparison against the
data read from the diskette. In order to avoid having the OR
(Over Run) flag set in Status Register 1, it is necessary to
have the data available in less than 27IJ-s (FM Mode) or 13
IJ-S (MFM Mode). If an Overrun occurs the FDC ends the
command with bits 7 and 6 of Status Register 0 set to 0 and
1, respectively.

Recalibrate
The function of this command is to retract the read/write
head within the FDD to the Track 0 position. The FDC clears
the contents of the PCN counter, and checks the status of
the Track 0 signal from the FDD. As long as the Track 0 signal is low, the Direction signal remains 0 (low) and Step
Pulses are issued. When the Track 0 signal goes high, the
SE (SEEK END) flag in Status Register 0 is set to a 1 (high)
and the command is terminated. If the Track 0 signal is still
low after 77 Step Pulses have been issued, the FDC sets
the SE (SEEK END) and EC (EQUIPMENT CHECK) flags
of Status Register 0 to both 1s (highs), and terminates the
command after bits 7 and 6 of Status Register 0 is set to 0
and 1 respectively.
The ability to do overlap RECALIBRATE Commands to
multiple FDDs and the loss of the READY signal, as
described in the Seek Command, also applies to the
RECALIBRATE Command.

Sense Interrupt Status

Seek
The read/write head within the FDD is moved from cylinder
to cylinder under control of the Seek Command. FDC has
four independent Present Cylinder Registers for each drive.
They are clear only after Recalibrate command. The FDC
compares the PCN (Present Cylinder Number) which is the
current head position with the NCN (New Cylinder Number), .and if there is a difference performs the following
operation:
PCN < NCN: Direction Signal to FDD set to a 1,(high),
and Step Pulses are issued. (Step In.)
PCN > NCN: Direction signal to FDDsettoaO(low), and
Step Pulses are issued. (Step Out.)

An Interrupt signal is generated by the FDC for one of the
following reasons:
1 . Upon entering the Result Phase of:
a. Read Data Command
b. Read a Track Command
c. Read ID Command
d. Read Deleted Data Command
e. Write Data Command·
f. Format a Cylinder Command
g. Write Deleted Data Command
h. Scan Commands
2. Ready Line of FDD changes state
3. End of Seek or Recalibrate Command
4. During Execution Phase in the NON-DMA Mode
Interrupts caused by reasons 1 and 4 above occur during
normal command operations and are easily discernible by
the processor. During an execution phase in NON-DMA
Mode, DB5 in Main Status Register is high. Upon entering
Result Phase this bit gets clear. Reason 1 and 4 does not
require Sense Interrupt Status command. The interrupt is
cleared by reading/writing data to FDC. Interrupts caused
by reasons 2 and 3 above may be uniquely identified with
the aid of the Sense Interrupt Status Command. This cOm-

534

mand when issued resets the interrupt signal and via bits

5, 6, and 7 of Status Register 0 identifies the cause of the
interrupt.
SEEK
END
BITS 5

a

a

a

1

1

a

= 2 ms, 02 = 4 ms, 03 = 6

The time intervals mentioned above are a direct function of
the clock (ClK on pin 19). Times indicated above are for an
8 MHz clock, if the clock was reduced to 4 MHz (mini-floppy
application) then all time intervals are increased by a factor

INTERRUPT
CODE
BIT6
BIT7
1
1

1

ms in increments of 2 ms (01
mS .. .7F = 254 ms).

CAUSE
Ready Line changed state, either
polarity
Normal Termination of Seek or
Recalibrate Command
Abnormal Termination of Seek or
Recalibrate Command

of2.
The choice of OMA or NON-OMA operation is made by the
NO (NON-OMA) bit. When this bit is high (NO = 1) the NONOMA mode is selected, and when NO = 0 the OMA mode
is selected.

Sense Drive Status

TableS
Neither the Seek or Recalibrate Command have a Result
Phase. Therefore, it is mandatory to use the Sense Interrupt Status Command after these commands to effectively
terminate them and to provide verification of where the head
is positioned (PCN).
Issuing Sense Interrupt Status Command without interrupt
pending is treated as an invalid command.

Specify
The Specify Command sets the initial values for each of the
three internal timers. The HUT (Head Unload Time) defines
the time from the end of the Execution Phase of one of the
Read/Write Commands to the head unload state. This timer
is programmable from 16 to 240 ms in increments of 16 ms
(01 = 16 ms, 02 = 32 ms ... OF = 240 ms}.The SRT (Step
Rate Time) defines the time interval between adjacent step
pulses. This timer is programmable from 1 to 16 ms in increments of 1 ms (F = 1 ms, E = 2 ms, 0 = 3 mS, etc.). The
HlT (Head load Time) defines the time between when the
Head load signal goes high and when the Read/Write
operation starts. This timer is programmable from 2 to 254

This command may be used by the processor whenever it
wishes to obtain the status of the FOOs. Status Register 3
contains the Orive Status information stored internally in
FOC registers.

Invalid
If an invalid command is sent to the FOC (a command not
defined above), then the FOC will terminate the command
after bits 7 and 6 of Status Register 0 are set to 1 and 0
respectively. No interrupt is generated by the FOC 9266
during this condition. Bit 6 and bit 7 (010 and ROM) in the
Main Status Register are both high ("1") indicating to the
processor that the FOC 9266 is in the Result Phase and the
contents of Status Register 0 (STO) must be read. When
the processor reads Status Register 0 it will find an 80 hex
indicating an invalid command was received.
A Sense Interrupt Status Command must be sent after a
Seek or Recalibrate Interrupt, otherwise the FOC will consider the next command to be an Invalid Command.
In some applications the user may wish to use this command as a No-Op command, to place the FOC in a standby
or no operation state.

STATUS REGISTER IDENTIFICATION
NO.
D,

BIT
NAME
Interrupt Code

SYMBOL
IC

D,

D5

Seek End

SE

D4

Equipment Check

EC

D,

Not Ready

NR

D2
D,
Do

Head Address
Unit Select 1
Unit Select a

HD
US1

usa

DESCRIPTION
D, = a and D, = a
Normal Termination of Command, (NT). Command was completed
and properly executed.
D, = a and D, = 1
Abnormal Termination of Command, (AT).
Execution of Command was started, but was not successfully
completed.
D, = 1 and D, = a
Invalid Command issue, (IC). Command which was issued was
never started.
D, = 1 and D, = 1
Abnormal Termination because during command execution the
ready signal from FDD changed state.
When the FDC completes the SEEK Command, this flag is set to
1 (high).
If a fault Signal is received from the FDD, or if the Track 0 Signal
fails to occur after 77 Step Pulses (Recalibrate Command) then this
flag is set.
When the FDD is in the not-ready state and a read or write
command is issued, this flag is set. If a read or write command is
issued to Side 1 of a single sided drive, then this flag is set.
This flag is used to indicate the state of the head at Interrupt.
These flags are used to indicate a Drive Unit. Number at Interrupt.

535

BIT
NAME

NO.

0,

End of Cylinder

0,
0,

Data Errror

0,

Over Run

0,
0,

No Data

0,

Not Writable

Do

Missing Address Mark

0,
0,

Control Mark

0,

Data Error in Data Field
Wrong Cylinder

0,

Scan Equal Hit

0,

Scan Not Satisfied

0,

Bad Cylinder

Do

Missing Address Mark
in Data Field

0,

Fault

0,

Write Protected

Os

Ready

0,

Track 0

0,

Two Side

0,

Head Address

D,

Unit Select 1

Do

Unit Select 0

Os

DESCRIPTION
SYMBOL
STATUS REGISTER 1(CONT.)
EN
When the FDC tries to access a Sector beyond the final Sector of a
Cylinder, this flag is set.
Not used. This bit is always 0 (low).
When the FDC detects a CRC error in either the 10 field or the data
DE
field, this flag is set.
If the FDC is not serviced by the main-systems during data
OR
transfers, within a certain time interval, this flag is set.
Not used. This bit always 0 (low).
During execution of READ DATA, WRITE DELETED DATA or
NO
SCAN Command, if the FDC cannot find the Sector specified in the
lOR Register, this flag is set.
During executing the READ 10 Command, if the FDC cannot read
the 10 field without an error, then this flag is set.
During the execution of the READ A Cylinder Command, if the
starting sector cannot be found, then this flag is set.
During execution of WRITE DATA, WRITE DELETED DATA or
NW
Format A Cylinder Command, if the FDC detects a write protect
signal from the FDD, then this flag is set.
If the FDC cannot detect the 10 Address Mark after encountering
MA
the index hole twice, then this flag is set.
If the FDC cannot detect the Data Address Mark or Deleted Data
Address Mark, this flag is set. Also at the same time, the MD
(Missing Address Mark in Data Field) of Status Register 2 is set.
STATUS REGISTER 2
Not used. This bit is always 0 (low).
During executing the READ DATA or SCAN Command, if the FDC
CM
encounters a sector which contains a Deleted Data Address Mark,
this flag is set.
If the FDC detects a CRC error in the data field then this flag is set.
DO
This bit is related with the NO bit, and when the contents of C on the
WC
medium is different from that stored in the lOR, this flag is set.
During execution, the SCAN Command, if the condition of "equal"
SH
is satisfied, this flag is set.
During executinw the SCAN Command, if the FDC cannot find a
SN
Sector on the cy inder which meets the condition, then this flag
is set.
This bit is related with the NO bit, and when the content of C on the
BC
medium is different from that stored in the lOR and the content of C
is FF, then this flag is set.
When data is read from the medium, if the FDC cannot find a Data
MD
Address Mark or Deleted Data Address Mark, then this flag is set.
STATUS REGISTER 3
This bit is used to indicate the status of the Fault Signal from
FT
theFDD.
This bit is used to indicate the status of the Write Protected signal
WP
from the FDD.
This bit is used to indicate the status of the Ready signal from
RY
the FDD.
This bit is used to indicate the status of the Track 0 signal from
TO
theFDD.
This bit is used to indicate the status of the Two Side signal from
TS
the FDD.
This bit is used to indicate the status of Side Select signal
HD
to the FDD.
This bit is used to indicate the status of the Unit Select 1 signal
US1
to the FDD.
This bit is used to indicate the status of the Unit Select 0 Signal
usa
to the FDD..

536

PROCESSOR INTERFACE
Ouring Command or Result Phases the Main Status Register (described earlier) must be read by the processor
before each byte of information is written into or read from
the Oata Register. After each byte of data read or written to
Oata Register, CPU should wait for 12 fLs before reading
MSR. Bits 06 and 07 in the Main Status Register must be
in aO and 1 state, respectively, before each byte of the command word may be written in the FOC 9266. Many of the
commands require multiple bytes, and as a result the Main
Status Register must be read prior to each byte transfer to
the FOC 9266. On the other hand, during the Result Phase,
06 and 07 in the Main Status Register must both be 1's (06
= 1 and 07 = 1) before reading each byte from the Oata
Register. Note, this reading of the Main Status Register
before each byte transfer to the FOC 9266 is required in
only the Command and Result Phases, and NOT during the
Execution Phase.
Ouring the Execution Phase, the Main Status Register need
not be read. If the FOC 9266 is in the NON-OMA Mode, then
the receipt of each data byte (if FOC 9266 is reading data
from FOO) is indicated by an Interrupt signg! on pin 18 (INT
= 1). The generation of a Read signal (RO = 0) or Write
signal (WR = 0) will reset the Interrupt as well as output the
Oata onto the Oata bus. If the processor cannot handle
Interrupts fast enough (every 13 fLS) for MFM and 27 fLs for
FM mode, then it may poll the Main Status Register and then
bit 07 (ROM) functions just like the Interrupt signal. If a Write
Command is in process then the WR signal performs the
reset to the Interrupt signal.
If the FOC 9266 is in the OMA Mode, no Interrupts are generated during the Execution Phase. The FOC 9266 generates ORa's (OMA Requests) when each byte of data is
available. The OMA Controller responds to thisJequest with
both a OACK = 0 (OMA Acknowledge) and a RO = 0 (Read
slgngl). When the OMA Acknowledge signal goes low
(OACK = 0) then the OMA Request is reset (ORO = 0). If
a Write Command has been programmed then a WR signal
will appear instead of RO. After the Execution Phase has
been completed (Terminal Count has occurred) or EaT
sector was read/written, then an Interrupt will occur (INT =
1). This signifies the beginning of the Result Phase. When
the first byte of data is read during the Result Phase, the
Interrupt is automatically reset (INT = 0).

It is important to note that during the Result Phase all bytes
shown in the Command Table must be read. The Read Oata
Command, for example has seven bytes of data in the Result
Phase. All seven bytes must be read in order to successfully complete the Read Oata Command. The FOC 9266
will not accept a new command until all seven bytes have
been read. Other commands may require fewer bytes to be
read during the Result Phase.
The FOC 9266 contains five Status Registers. The Main
Status Register mentioned above may be read by the processor at any time. The other four Status Registers (STO,
ST1, ST2, and ST3) are only available during the Result
Phase, and may be read only after completing a command.
The particular command which has been executed determines how many of the Status Registers will be read.
The bytes of data which are sent to the FOC 9266 to form
the Command Phase, and are read out of the FOC 9266 in
the Result Phase, must occur in the order shown in the
Command Table. That is, the Command Code must be sent
first and the other bytes sent in the prescribed sequence.
No foreshortening of the Command or Result Phases are
allowed. After the last byte of data in the Command Phase
is sent to the FOC 9266, the Execution Phase automatically
starts. In a similar fashion, when the last byte of data is read
out in the Result Phase, the command is automatically
ended and the FOC 9266 is ready for a new command.

POLLING FEATURE OF THE FDC 9266
After the Specify command has been sent to the FOC 9266,
the Unit Select line USO and US1 will automatically go into
a polling mode. In between commands (and between step
pulses in the SEEK command) the FOC 9266 polls all four
FOO's looking for a change in the Ready line from any of
the drives. If the Ready line changes state (usually due to
a door opening or closing) then the FOC 9266 will generate
an interrupt. When Status Register 0 (STO) is read (after
Sense Interrupt Status is issued), Not Ready (NR) will be
indicated. The polling of the Ready line by the FOC 9266
occurs continuously between commands, thus notifying the
processor which drives are on or off line. Each drive is polled
every 1.024 ms except during the ReadlWrite commands.

AC TEST CONDITION
INPUT IOUTPUT

CLOCK
3.0V _ _--,.

2.4V

O.3V _ _---J

O.45V

ACTESTING
Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0:' Timing measurements are made at 2.0V for a logic "1" and O.SV for a logic "0."
Clocks are driven at 3.0V for a logic "1" and 0.3V for a logic "0." Timing measurements are made at 2.4V for a logic "1" and 0.65V for a logic "0."

537

P1
PO
PRECOMP VALUE
0
0
ONS
0
1
125NS
1
0
250NS
1
1
375 NS'
1
0
0
500NS'
WRITE PRECOMPENSATION VALUE SELECTION
'NOTE: Precompvalues of 375. ns and 500 ns are valid only with 51/4" drives.

PRECOMPENSATION
The desired precompensation delay is determined by the
state of the PO, P1 and P2 inputs. Logic levels present on
these pins may be changed dynamically as long as the
inputs are stable during the time the floppy disk controller
is writing to the drive.

P2

o
o
o
o

DATA SEPARATOR
The FDC 9266 detects the leading (negative) edges of the The SEPClK frequency is nominally V'6 the ClK frequency.
disk data pulses and adjusts the phase of the internal clock Depending on the internal timing correction, the duration of
any SEPCLK half-cycle may vary from a nominal of 8 to a
to provide the internal SEPCLK signal.
Separate short- and long-term timing correctors assure minimum of 6 and a maximum ·of 11 internal clock cycles.
accurate clock separation.

CLK
SEPCLK'--J;--------~~-----------l------------------~--------

SEPD' _ _ _ _--,

W

.-_ _ _ _ _ _ _ _ _-,

.-_ _ _ _ _ __

LJ

LJ

I

~ always two internal clock cycles

'internal signals to FDC 9266

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O°C to + 70°C
Storage Temperature ......................................................................................... -55°C to + 150°C
All Output Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5 to + 7 Volts
All Input Voltages ............................................................................................. - 0.5 to + 7 Volts
Supply Voltage Vee ............................................................................................ - 0.5 to + 7 Volts
Power Dissipation ........................................................................................................ 1 Watt
T. = 25°C
'COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the' operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC CHARACTERISTICS T. = O°C to
PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Voltage
(CLK + WR Clock)
Input High Voltage
(CLK + WR Clock)
Vee Supply Current
Input Load Current
(All Input Pins)

+ 70°C; Vee
SYMBOL

=

+ 5V

± 5% unless otherwise specified.

MIN
-0.5
2.0

LIMITS
TYPCD

V'L
V,H
VOL
VOH
V'L(CY
<1>a
<1>,
<1>f
TAR
TRA
TRR
TRo
TOF
TAw
TWA
Tww
Tow
Two
TRI
TWI

=

+ 5V

± 5% unless otherwise specified.

MIN
120
40

LIMITS
TYPCD
125

MAX
130
20
20

0
0
250
200
100

20
0
0
250
150
5

500
500

UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fLs
ns

TMCY

13

TAM
TTc
TRST
Tus
Tso

1
14
12
7

<1>CY
<1>CY
fLs
fLs

lOST

1.0

fLs

TSTU

5.0

fLs

TSTP
Tsc
TFR
Tsu
Tos
TSTD

T1DX
TMR
TMw
TMRW

200

6.0
33
8.0
15
30
24
10
800
250

7.0
®

®
10

12

fLs
fLs
fLS
fLs
fLs
fLS
<1>CY
ns
ns
fLs

TEST
CONDITIONS

CL
CL

=
=

100pF
100pF

8 Mhz Clock Period
Mini=O
16 MHz Clock Period
Mini=1

8 MHz Clock Period
Mini=O
16 MHz Clock Period
Mini=1
8 MHz Clock Period
Mini=O
16 MHz Clock Period
Mini=1

NOTES: CD Typical values for T, = 25 DC and nominal supply voltage.
® Under Software Control. The range is from 1 ms to 16 ms for 8" floppies, and 2 to 32 ms for 51/4' floppies.

539

TIMING DIAGRAMS

PROCESSOR WRITE OPERATION

PROCESSOR READ OPERATION

CLOCK
I

elK

I 00 I
OR

SEEK OPERATION
USO, ,

~

~ I

I

----'

I
¢O!

--i '-- I r-"I
f--r

~

STABLE

---""-------.
. . .1''-----Jtusl-----i r-

I

I

:--¢CY~

F

DMA OPERATION

·SU

RW/SEEK

-X
---1
-----X

'SOt--

DIRECTION

'OST

ORO

~ I
ItOSI -+-----

-.

r--

-X'-':"'-"";-:-----

WR

----l t--~TU--l

OR RD

~-TO----~I~

STEP

________
'STP

------l f---I
f-ol.o---- tsc--_.~I

FLT RESET
FAULTRESET-

I

I

:

I

~

FILE UNSAFE RESET
-

TFR - - -

TERMINAL COUNT

INDEX

~
I
II
I
TIOX

H

TIDX

TC

Jt-----l

~TTC

r----::---l

RESET

H
For more information, please consult:
Technical Note 6-1 (Digital Data Separation)

RESET--l!

~

-----J

I-- T RST

Cirouit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

540

FDC 9268

Quad Density Integrated Floppy Disk Controller
FEATURES
D Combination Floppy Disk Controller,
Data Separator and Precompensation
Generator
D Software compatible with industry
standard FDC 765A
D On chip high resolution digital data
separator eliminates critical analog
adjustments
D 500, 300, 250,125 Kb/s Data Rates
D IBM compatible in both single, double
and quad density recording formats
D Programmable data record lengths:
128,256,512, or 1024 bytes/sector
D Multi':'sector and multi-track transfer
capability.
D Controls up to 4 floppy disk drives
D Data Scan Capability-will scan a
single sector or entire track's worth of
data fields, comparing on a byte
by byte basis, data in the
processor's memory with
the data read from the diskette
D Data transfers in DMA or non-DMA
mode
D Single 16 MHz TTL clock input
D Parallel Seek operations on up to four
drives

PIN CONFIGURATION
f-::J

(f)rI
>-t:t:

RESET
RD
WR

00.-::2

~~~~(L~~~~~~
HDl
FRISTP
lCTlDlR
RWISEEK

Vee
NC
RESET

39 38 37 36 35 34 333231 3029
28
40
27
41
26
42
25
43
24
44
23
1
22

R5
WR
CS
Ao

6

18
7891011121314151617

0"'0'0·"'°1'"

~~gs~~z~~~gs~
0

CS

Ao
WE
DBo
PO
DB,
DSKD
DB2
ClK
DB3 9
MINI
DB4 10
NC
DBs 11
GND
DBs 12
TEST
DB,13
INT
ORO 14
IDX
DACK 15
TC
TC 16
IDX 17
INT 18
TEST 19
GND 20

PACKAGE: 44-pin PLCC

D Compatible with most microprocessors
D COPLAMOS® n-channel silicon gate
technology

40 Vee

3
4

39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

RW!SEEK
lCT'DIR
FR!STP
HDl
RDY
WPTS
FlT'TRo
P2
P1
WDOUT
USa
US,
HD
MFM
WE
P0
DSKD
ClK
MINI

PACKAGE. 4Q-pm D.I.P.

D Single +5 Volt power supply
D Available in 40-pin Dual-In-Line and
44-pin PLCC packages.

GENERAL DESCRIPTION
The FDC 9268 is a monolithic combination of the industry
standard FDC 765A Floppy Disk Controller and the FDC
9239, a high performance Data Separator and Precompensation Generator. It preserves all of the processor
hardware and software interfaces to the FDC 765A, and
contains on-chip circuitry to simplify drive interfacing. The
FDC 9268 contains the circuitry and control functions for
interfacing a processor to four 3.5", 5.25", and 8" floppy-disk
drives. It is capable of supporting either IBM 3740 single
density format (FM), IBM System 34 Double Density format
(MFM) or IBM quad density format, including double-sided
recording. The FDC simplifies and handles most of the
burdens associated with implementing a Floppy Disk
Interface.

The FDC uses a high performance 16-bit cell divide
algorithm which produces significant improvements in soft
error rates over existing designs. The FDC 9268's high
performance is achieved without any external adjustments.
The FDC 9268 also allows variable write precompensation,
which is track selectable.
There are fifteen separate commands which the FDC 9268
will execute. Each of these commands requires multiple
8-bit bytes to fully specify the operation which the
processor wishes the FDC to perform. The following
commands are available:
Read Data
Read ID
Read Deleted Data
Read a Track
Scan Equal
Scan High or Equal
Scan Low or Equal
Specify

Hand-shaking signals are provided in the FDC 9268 which
make DMA operation easy to incorporate with the aid of an
external DMA or Non-DMA mode. In the Non-DMA mode,
the FDC generates interrupts to the processor every time a
data byte is available. In the DMA mode, the processor
need only load the command into the FDC and all data
transfers occur under control of the FDC 9268.
The FDC 9268 enhancements greatly reduce the number
of components required to interface floppy disks to a
microprocessor system. These on-chip enhancements
include a digital data separator, compatible with 3.5", 5.25",
and 8" floppy disk drives. The FDC 9268 separates both FM
(Single Density) and MFM (Double Density) encoded data.

541

Write Data
Format a Track
Write Deleted Data
Seek
Recalibrate (Restore to Track 0)
Sense Interrupt Status
Sense Drive Status

Address mark detection circuitry is internal to the FDC
which simplifies the read electronics. The track stepping
rate, head load time, and head unload time may be
programmed by the user. The FDC 9268 offers many
additional features such as multiple sector transfers in both
read and write with a single command, and full IBM
compatibility in both single and double density modes.

REGISTERS

080.7

DATA
SEPARATOR
AND
PRECOMP
LOGIC

SERIAL
INTERFACE
CONTROLLER

DSK DATA
WDOUT

_PO

-P,
_P,

Rii

WA
WRITE PROTECT/TWO SIDE

AO

FAULT/TRACK 0

RESET

MINI

UNITSELECTO
UNIT SELECT 1
MFMMODE

eLK
Vee

RW'SEEK
HEAD LOAD
HEADSELECT

GNo

LOW CURRENT/DIRECTION
FAULT RESET/STEP

FIGURE 1: BLOCK DIAGRAM

DRIVE
2 SIDED
WPRT
TRK00
FAULT

FDe 9268

~~~~~~~~~~~§

RwISEEK
WP(rS
FLTITR0
FRISTEP
LCT/OIR
DB0-DB7

STEP
FLT
DIR RST
LOW CUR

P0
P1
PRECOMPENSATION
P2
SELECT
ROY
ROY
lOX
lOX
WE
WE
HD ~___________________________________
~HLO
SIDE SEL
HDL

INT

INT

CS

CS

US1

RD

US0

~~~~~~~~~~~~DRSEL4

ORSEL3
DRSEl2
DRSEL1

WR
A0
ORO
DACK
TC
RESET

A0

i5§i(!j

RAW READ

ORO
DACK WDOUT
TC

MINI
MFM

ROY
lOX
WE
SIDE SEL

--"":=__.....J
RST

LATCH

t-__________o-tMOTOR ON
DB0-0B7

FIGURE 2: TYPICAL APPLICATION

542

DESCRIPTION OF PIN FUNCTIONS
PIN
SYMBOL
RST

2

Reset

INPUT/
OUTPUT
Input

CONNECTION
TO
Processor

RD

Read

InputCD

Processor

3

WR

Write

InputCD

Processor

4

CS

Chip Select

Input

Processor

5

Ao

Data/Status Reg
Select

InputCD

Processor

DBo·DB,

Data Bus

Processor

14

DRO

15

DACK

DataDMA
Request
DMA
Acknowledge

InputCD
Output
Output
Input

DMA

16

TC

Terminal Count

Input

DMA

17

IDX

Index

Input

FDD

18

INT

Interrupt

Output

Processor

19

TEST

Test

Input

20
21

GND
MINI

Ground
Mini

Input

22

ClK

16MHz
TTL Clock
Raw Data
Precompensation
Select

Input
Input
Input

FDD
Processor

NO.
1

6·13

23
24,31,32

DSKD
PO,P1,P2

NAME

DMA

Processor

25
26

WE
MFM

Write Enable
MFMMode

Output
Output

FDD

27

HD

Head Select

Output

FDD

US"USa
WDOUT
FlTITRo

Unit Select
Write Data Out
FaultlTrack 0

Output
Output
Input

FDD
FDD
FDD

WP/TS

Write Protect!
Two·Side

Input

FDD

28,29
30
33

34

543

FUNCTION
Places FDC in idle state. Resets
output lines to FDD to "0" (low).
Does not effect SRT, HUT or HLT
in Specify command. If RDY pin is
held high during Reset, FDC will
generate interrupt 1.024 ms later.
To clear this interrupt use Sense
Interrupt Status command.
Control signal for transfer of data
from FDC to Data Bus, when
"O"(low).
Control signal for transfer of data to
FDC via Data Bus, when "0" (low).
IC selected when...JL' (low),
allowing RD and WR to be
enabled.
Selects Data Reg (Ao = 1) or
Status Reg (Ao = 0) contents of
the FDC to be sent to Data Bus.
Bi·DirectionaI8·Bit Data Bus.
DMA Request is being made by
FDC when DRW = "1".
DMA cycle is active when "0" (low)
and Controller is performing DMA
transfer.
Indicates the termination of a DMA
transfer when "1" (high). It
terminates data transfer during
Read/Write/Scan command in
DMA or interrupt mode.
Indicates the beginning of a disk
track.
Interrupt Request Generated by
FDC.
This pin is for test purposes only.
Should be left tied high in normal
operation.
D.C. Power Return.
This input, when set to "1" (hi9h),
configures the FOC for operation
with 250 Kb/s. If reset to "0"
(low), then the FDC is configured
for 500 Kb/s operation (MFM mode).
Device clock.
Raw data from drive.
These pins select the amount of
precompensation applied to the
write data.
Enables write data into FDD.
MFM mode when "1," FM mode
when "0."
Head 1 selected when "1" (high).
Head 2 selected when "0" (low).
FDD Unit Selected.
Serial clock and data bits to FDD.
Senses FDD fault condition, in
Read/Write mode; and Track 0
condition in Seek mode.
Senses Write Protect status in
ReadlWrite mode; and Two Side
Media in Seek mode.

· DESCRIPTION OF PIN FUNCTIONS
PIN
SYMBOL

NO.

CONNECTION
TO

INPUT/

NAME

OUTPUT

35

RDY

Ready

Input

FDD

36

HDL

Head Load

Output

FDD

37

FR/STP

Fit Reset!Stop

Output

FDD

38

LCTiDIR

LowCurrentJ
Direction

Output

FDD

39

RWSEEK

Read Write/SEEK

Output

FDD

40

Vee

+5V

FUNCTION
Indicates FDD is ready to send or
receive data.
Command which causes read/
write head in FDD to contact
diskette.
Resets fault F F in FDD in Read!
Write mode, contains stop pulses
to move head to another cylinder in
Seek mode.
Lowers Write current on inner
tracks ~ 42 in Read/Write mode,
determines direction head will stop
in Seek mode. A fault reset pulse is
issued at the beginning of each
Read or Write command prior to
the occurrence of the Head Load
signal.
When "1" (high) Seek mode
selected and when "0" (low) Read!
Write mode selected.
DC Power.

..

Note: (j) Disabled when CS = 1.

DESCRIPTION OF INTERNAL REGISTERS
The FOG 9268 contains two registers which may be accessed by the main system processor; a Status Register
and a Data Register. The 8-bit Main Status Register contains the status information of the FOG, and may be
accessed at any time. The 8-bit Data Register (actually
consists of several registers in a stack with only one register
presented to the data bus at a time), which stores data,
commands, parameters, and FOO status information. Data
bytes are read out of, or written into, the Data Register in
order to program or obtain the results after a particular command. The Status Register may only be read and used to

facilitate the transfer of data between the processor and
FOG 9268.
The relation~ between the StatuslData registers and the
signals RO, WR, and Ao is shown below.

A,
0
0
0
1
1
1

RD
0

WR

1

0
0
0

0
0
0
1

1

1

0

FUNCTION
Read Main Status Register
Illegal
IIleQal
Illegal
Read from Data Register
Write into Data Register

The bits in the Main Status Register are defined as follows:

--

c--.

NAME

BIT NUMBER
DBa

FDDO Busy

DB,

FDD 1 Busy

SYMBOL

DESCRIPTION

D,B

FDD number 0 is in the Seek mode. If any of the bits is set
FDC will not accept read or write command.
FDD number 1 is in the Seek mode. If any of the bits is set
FDC will not accept read or write command.
FDD number 2 is in the Seek mode. If any of the bits is set
FDC will not accept read or write command.
FDD number 3 is in the Seek mode. If any of the bits is set
FDC will not accept read or write command.
A read or write command is in process. FDC will not accept
any other command.
This bit is set only during execution phase in non-DMA mode.
When DB, goes low, execution phase has ended, and result
phase was started. It operates only during NON-DMA mode
of operation.
Indicates direction of data transfer between FDC and Data
Register. If DIO = "1" then transfer is from Data Register to
the Processor. If DIO = "0", then trahsfer is from the
Processor to Data Register.
Indicates Data Register is ready to send or receive data to or
from the Processor. Both bits DIO and ROM should be used
to perform the hand-shaking functions of "ready" and
"direction" to the processor.

D,B
1--.--.

DB,

FDD2 Busy

D,B

DB,

FDD 3 Busy

D,B

DB4

FDC Busy

CB

DB,

Execution Mode

EXM

DB,

Data Input!Output

DIO

DB,

Request for Master

ROM

The DIO and ROM bits in the Status .Brulistillndicate when Data is ready and in which direction data will be transferred on the Data
Bus. The max time between the last RD or WR during command or result phase and DIO and ROM getting set or reset is 12 fJ.UOr
this reason every time Main Status Register is read the CPU should wait 12 fJ.s. The max time from the trailing edge of the last RD in
the result phase to when DB4 (FDC Busy) goes low is 12 fJ.S.

544

COMMAND SEQUENCE
Out FDC and Into Processor
Data In/Out
(010)

The FOC 9268 is capable of performing 15 different commands. Each command is initiated by a mUlti-byte transfer
from the processor, and the result after execution of the
command may also be a mUlti-byte transfer back to the processor. Because of this multi-byte interchange of information between the FOC 9268 and the processor, it is
convenient to consider each command as consisting of three
phases:
Command Phase:

Execution Phase:
Result Phase:

COMMAND SYMBOL DESCRIPTION
SYMBOL
Ao

NAME
Address Line 0

C

Cylinder Number

D
D,-D o

Data
Data Bus

DTL

Data Length

EaT

End of Track

GPL

Gap Length

H
HD

Head Address
Head

HLT

Head Load Time

HUT

Head Unload Time

MF
MT

FM or MFM Mode
Multi-Track

N
NCN

Number
New Cylinder Number

ND
PCN
R
R/W
SC
SK
SRT

Non-DMA Mode
Present Cylinder
Number
Record
Read/Write
Sector
Skip
Step Rate Time

STO
ST1
ST2
ST3

Status 0
Status 1
Status 2
Status 3

STP

USO, US1

Unit Select

The FOG receives all information
required to perform a particular
operation from the processor.
The FOG performs the operation
it was instructed to do.
After completion of the opera t;,,:,
status and other housekeeping
informatic!1 are made available to
the processor.

DESCRIPTION
Ao controls selection of Main Status Register (Ao = 0) or Data Register
(Ao = 1).
C stands for the current/selected Cylinder (track) number 0 through 76 of
the medium.
D stands for the data pattern which is going to be written into a Sector.
8-bit Data Bus, where D, stands for a most significant bit, and Do stands for a
least significant bit.
When N is defined as 00, DTL stands for the data length which users are
. goinglo read out or write into the Sector.
EaT stands for the final Sector number on a Cylinder. During Read or Write
operation FDC will stop date transfer after a sector # equal to EaT.
GPL stands for the length of Gap 3. During Read/Write commands this value
determines the number of bytes that vcas will sta~low after two CRC bytes.
During Format command it determines the size of ap 3.
H stands for head number 0 or 1, as specified in ID field.
HD stands for a selected head number 0 or 1 and controls the polarity of pin
27. (H = HD in all command words.)
HLT stands for the head load time in the FDD (2 to 254 ms in 2 ms
increments).
HUT stands for the head unload time after a read or write operation has
occurred (16 to 240 ms in 16 ms increments).
If MF is low, FM mode is selected, and if it is high, MFM mode is selected.
If MT is high, a multi-track operation is to be performed. If MT = 1 after
finishing Read/Write operation on side 0 FDC will automatically start
searching for sector 1 on side 1.
Number of data bytes written in a Sector = 128* 2'.
NCN stands for a new Cylinder number, which is going to be reached as a
result of the Seek operation. Desired position of Head.
ND stands for operation in the Non-DMA Mode.
PCN stands for the Ctinder number at the completion of SENSE
INTERRUPT STATU Command. Position of Head at present time.
R stands for the Sector number, which will be read or written.
R/W stands for either Read (R) or Write (W) signal.
SC indicates the number of Sectors per Cylinder.
SK stands for Skip Deleted Data Address Mark.
SRT stands for the Stepping Rate for the FDD. (1 to 16 ms in 1 ms
increments.) Stepping Rate applies to all drives, (F = 1 ms, E = 2 ms, etc.).
ST 0-3 stand for one of four registers which store the status information after
a command has been executed. This information is available during the
result phase after command execution. These registers should not be
confused with the main status register (selected by Ao = 0). ST 0-3 may be
read only after a command has been executed and contain information
relevant to that particular command.
During a Scan operation, if STP = 1, the data in continguous sectors is
compared byte by byte with data sent from the processor (or DMA) ; and if
STP = 2, then alternate sectors are read and compared.
US stands for a selected drive number 0 or 1.
545

INSTRUCTION SET CD ®
I

DATA BUS
PHASE

DATA BUS

I
REMARKS

PHASE

R/W

07

06

05 0

READ DATA
Command

W

w
w
w
w
w
w

w
w

MT

MF SK

X

X

0

Command Codes

X

X

HD US1

Sector 10 information pnor
to Command execution, The

~EOT~~~

header on Floppy Disk.

GPl

-----OTl-----

-----STO----~~ST1====
H=====
------R------

W

w
w
w
w
w
w
w
w

4 bytes are commanded against

Data-transfer between the

I
01

Qjl

o

MF

SK

0

0

0

X

X

X

X

HD

REMARKS

Command Cocles

USl

usa
Sector 10 information prior
to Command execution

~3E~T:==---=
OTl-GPL-

Execution

FDD and main-system
Status information after
Command execution

sn

R

Command

usa

Execution

Result

03 02

READ A TRACK

-----STO---------ST1----~S;2~

Result
Seclor to information after
Command execution

Oata·transferbetweenthe
FOD and maln·system FDC
reads all data fields
from Index hole to Ear .
Status information after
Command execution
Sector 10 ,nformat,on after
Command execution

READ DELETED DATA
Command

W

MT

MF

w

w
w
w
w
w
w
w
Execution

SK

0

x

X

Command Codes
X

HD

US1

=====~====

====EOTr--=====

Command
Sector 10 information prior
to Commend execution. The
4 bytes are commanded agamst
header on FloPPV Disk.

GPL- - - - - OTL-----

==-ST;-==

---------STO----------

Result

READ 10

usa
W

W

W

w
w
w
w
w
w
w

MT

MF

0

0

X

X

HO US1

::::=::::::~EOT---------

SeCtor 10 information prior
to Command execution. The
4 bytes afe commanded against
header on Floppy Disk.

1

C=====

MT

w
w
w
w
w
w
w
w

x.

MF

0

0

X

X

Command Codes
X

X

HO US1

usa

==== ~.=====

Status information after
Command execution
In this case, the 10 information
hes no meaning

_____ R - - - - - - -

SCAN EaUAL

Status In'ormatlon after
Command execution

Command

W

W

Sector 10 mformatlon after
Command execution

W
W
W
W
W
W
W

Sector 10 information prior
to Command execution. The
4 bytes are commanded against
header on Floppy Disk.

Result

Sector 10 information after
Command elilecution

======-~======
Symb04s used in this table are described at the end of thiSl8Ction.

®

AO should equal binary 1 for all operations.

@

X" Don't care, usually made to equal binary O.

MF

1

SK
X

HO US1

546

Command Codes

USO
Sector 10 information prior
to Command ellleCU!lon

EOT~
~GP~-

STP-----

-==STO===
==
-----ST2
-c====
====R=-- - - - - N-------

Status informatiOn after
Command execution



DpRocEssoR
DpRocEssoR
DpROCESSOR
DpROCESSOR
DpROCESSOR

DFOo = DpRocEssoR

DFDO >
DFDO <

DpROCESSOR
DpRocEssOR

Table 4
If the FDC encounters a Deleted Data Address Mark on one
of the sectors (and SK = 0), then it regards the sector as
the last sector on the cylinder, sets CM (Control Mark) flag
of Status Register 2 to a 1 (high) and terminates the command. If SK = 1, the FDC skips the sector with the Deleted
Address Mark, and reads the next sector. In the second case
(SK = 1), the FDC sets the CM (Control Mark) flag of Status Register 2 to a 1 (high) in order to show that a Deleted
Sector had been encountered.
When either the STP (contiguous sectors = 01, or alternate sectors = 02 sectors are read) or the MT (Multi-Track)
are programmed, it is necessary to remember that the last
sector on the track must be read. For example, if STP = 02,
MT = 0, the sectors are numbered sequentially 1 through
26, and we start the Scan Command at sector 21 ; the following will happen. Sectors 21,23 and 25 will be read, then
the next sector (26) will be skipped and the Index Hole will
be encountered before the EOT value of 26 can be read.
This will result in an abnormal termination of the command.
If the EOT has been set at 25 or the scanning started at
sector 20, then the Scan Command would be completed in
a normal manner.
During the Scan Command data is supplied by either the
processor or DMA Controller for comparison against the
data read from the diskette. In order to avoid having the OR
(Over Run) flag set in Status Register 1, it is necessary to
have the data available in less than 27 f.Ls (FM Mode) or 13
f.Ls (MFM Mode). If an Overrun occurs the FDC ends the
command with bits 7 and 6 of Status Register 0 set to 0 and
1, respectively.

Seek
The read/write head within the FDD is moved from cylinder
to cylinder under control of the Seek Command. FDC has
four independent Present Cylinder Registers for each drive.
They are clear only after Recalibrate command. The FDC
compares the PCN (Present Cylinder Number) which is the
current head position with the NCN (New Cylinder Number), and if there is a difference performs the following
operation:
PCN < NCN: Direction signal to FDD set to a 1 (high),
and Step Pulses are issued. (Step In.)
PCN> NCN: Direction signal to FDDsettoaO (low), and
Step Pulses are issued. (Step Out.)

Recalibrate
The function of this command is to retract the read/write
head within the FDD to the Track 0 position. The FDC clears
the contents of the PCN counter, and checks the status of
the Track 0 signal from the FDD. As long as the Track 0 signal is low, the Direction signal remains 0 (low) and Step
Pulses are issued. When the Track 0 signal goes high, the
SE (SEEK END) flag in Status Register 0 is set to a 1 (high)
and the command is terminated. If the Track 0 signal is still
low after 77 Step Pulses have been issued, the FDC sets
the SE (SEEK END) and EC (EQUIPMENT CHECK) flags
of Status Register 0 to both 1s (highs), and terminates the
command after bits 7 and 6 of Status Register 0 is set to 0
and 1 respectively.
The ability to do overlap RECALIBRATE Commands to
multiple FDDs and the loss of the READY signal, as
described in the Seek Command, also applies to the
RECALIBRATE Command.

Sense Interrupt Status
An Interrupt signal is generated by the FDC for one of the
following reasons:
1. Upon entering the Result Phase of:
a. Read Data Command
b. Read a Track Command
c. Read ID Command
d. Read Deleted Data Command
e. Write Data Command
f. Format a Cylinder Command
g. Write Deleted Data Command
h. Scan Commands
2. Ready Line of FDD changes state
3. End of Seek or Recalibrate Command
4. During Execution Phase in the NON-DMA Mode
Interrupts caused by reasons 1 and 4 above occur during
normal command operations and are easily discernible by
the processor. During an execution phase in NON-DMA
Mode, DB5 in Main Status Register is high. Upon entering
Result Phase this bit gets clear. Reason 1 and 4 does not
require Sense Interrupt Status command. The interrupt is
cleared by reading/writing data to FDC. Interrupts caused
by reasons 2 and 3 above may be uniquely identified with
the aid of the Sense Interrupt Status Command. This com-

550

ms in increments of 2 ms (01 = 2 ms, 02 = 4 ms, 03 = 6
ms .. 7F = 254 ms).
The time intervals mentioned above are a direct function of
the clock (ClK on pin 22). Times indicated above are for an
16 MHz clock, ilthe clock was reduced to 8 MHz (mini -floppy
application) then all time intervals are increased by a factor
of 2.

mand when issued resets the interrupt signal and via bits
5, 6, and 7 of Status Register 0 identifies the cause of the
interrupt.
INTERRUPT
SEEK
CODE
END
BITS 5 I-SITs BiT7
1
1
a

1

a

a

1

1

a

CAUSE
Ready Line changed state, either
polarity
Normal Termination of Seek or
Recallbrate Command
Abnormal Termination of Seek or
Recalibrate Command

The choice of DMA or NON-DMA operation is made by the
ND (NON-DMA) bit. When this bit is high (ND ~ 1) the NONDMA mode is selected, and when ND = 0 the DMA mode
IS selected.

Sense Drive Status

Table 5
Neither the Seek or Recalibrate Command have a Result
Phase. Therefore, it is mandatory to use the Sense Interrupt Status Command after these commands to effectively
terminate them and to provide verification of where the head
is positioned (PCN).
Issuing Sense Interrupt Status Command without interrupt
pending is treated as an invalid command.

Specify
The Specify Command sets the initial values for each of the
three internal timers. The HUT (Head Unload Time) defines
the time from the end of the Execution Phase of one of the
Read/Write Commands to the head unload state. This timer
is programmable from 16 to 240 ms in increments of 16 ms
(01 = 16 ms, 02 = 32 ms ... OF = 240 ms).The SRT (Step
Rate Time) defines the time interval between adjacent step
pulses. This timer is programmable from 1 to 16 ms in increments of 1 ms (F = 1 ms, E = 2 ms, D = 3 ms, etc.). The
HlT (Head load Time) defines the time between when the
Head load signal goes high and when the Read/Write
operation starts. This timer is programmable from 2 to 254

This command may be used by the processor whenever it
wishes to obtain the status of the FDDs. Status Register 3
contains the Drive Status information stored internally in
FDC registers.

Invalid
If an invalid command is sent to the FDC (a command not
defined above), then the FDC will terminate the command
after bits 7 and 6 of Status Register 0 are set to 1 and 0
respectively. No interrupt is generated by the FDC 9268
during this condition. Bit 6 and bit 7 (DIO and ROM) in the
Main Status Register are both high ("1") indicating to the
processor that the FDC 9268 is in the Result Phase and the
contents of Status Register 0 (STO) must be read. When
the processor reads Status Register 0 it will find an 80 hex
indicating an invalid command was received.
A Sense Interrupt Status Command must be sent after a
Seek or Recalibrate Interrupt, otherwise the FOC will consider the next command to be an Invalid Command.
In some applications the user may wish to use this command as a No-Op command, to place the FOC in a standby
or no operation state.

STATUS REGISTER IDENTIFICATION
NO.

0,

BIT
NAME
Interrupt Code

SYMBOL
IC

06

Os

Seek End

SE

0,

Equipment Check

EC

03

Not Ready

NR

0,
0,
0,

Head Address
Unit Select 1
Unit Select a

HD
US1

usa

DESCRIPTION

0, = a and De = a
Normal Termination of Command, (NT). Command was completed
and properly executed.
0, = a and 0 6 = 1
Abnormal Termination of Command, (AT).
Execution of Command was started, but was not successfully
completed.
0, = 1 and 0 6 = a
Invalid Command issue, (IC). Command which was issued was
never started.
0, = 1 and De = 1
Abnormal Termination because during command execution the
ready signal from FDD changed state.
When the FDC completes the SEEK Command, this flag is set to
1 (high).
If a fault Signal is received from the FDD, or if the Track a Signal
fails to occur after 77 Step Pulses (Recalibrate Command) then this
flag is set.
When the FDD is in the not-ready state and a read or write
command is issued, this flag is set. If a read or write command is
issued to Side 1 of a single sided drive, then this flag is set.
This flag is used to indicate the state of the head at Interrupt.
These flags are used to indicate a Drive Unit. Number at Interrupt.

551

BIT
NAME

NO.

SYMBOL
STATUS REGISTER 1(CONT.)

D,

End of Cylinder

EN

D,
D,

Data Errror

DE

D,

Over Run

OR

D,
D,

No Data

ND

D,

Not Writable

NW

Do

Missing Address Mark

MA

DESCRIPTION

When the FDC tries to access a Sector beyond the final Sector of a
Cylinder, this flag is set.
Not used. This bit is always 0 (low).
When the FDC detects a CRC error in either the ID field or the data
field, this flag is set.
If the FDC is not serviced by the main-systems during data
transfers, within a certain time interval, this flag is set.
Not used. This bit always 0 (low).
Duri~ execution of READ DATA, WRITE DELETED DATA or
SCA Command, if the FDC cannot find the Sector specified in the
IDR Register, this flag is set.
During executing the READ ID Command, if the FDC cannot read
the ID field without an error, then this flag is set.
During the execution of the READ A Cylinder Command, if the
starting sector cannot be found, then this flag is set.
During execution of WRITE DATA, WRITE DELETED DATA or
Format A Cylinder Command, if the FDC detects a write protect
signal from the FDD, then this flag is set.
If the FDC cannot detect the ID Address Mark after encountering
the index hole twice, then this flag is set.
If the FDC cannot detect the Data Address Mark or Deleted Data
Address Mark, this flag is set. Also at the same time, the MD
(Missing Address Mark in Data Field) of Status Register 2 is set.

STATUS REGISTER 2
D,
D,

Control Mark

CM

D,
D,

Data Error in Data Field
Wrong Cylinder

DD
WC

D,

Scan Equal Hit

SH

D,

Scan Not Satisfied

SN

D,

Bad Cylinder

BC

Do

Missing Address Mark
in Data Field

MD

D,

Fault

FT

D,

Write Protected

WP

D,

Ready

RY

D,

Track 0

TO

D,

Two Side

TS

D,

Head Address

HD

D,

Unit Select 1

US1

Do

Unit Select 0

usa

Not used. This bit is always 0 (low).
During executing the READ DATA or SCAN Command, if the FDC
encounters a sector which contains a Deleted Data Address Mark,
this flag is set.
If the FDC detects a CRC error in the data field then this flag is set.
This bit is related with the ND bit, and when the contents of C on the
medium is different from that stored in the IDR, this flag is set.
During execution, the SCAN Command, if the condition of "equal"
is satisfied, this flag is set.
During executing the SCAN Command, if the FDC cannot find a
Sector on the cylinder which meets the condition, then this flag
is set.
This bit is related with the ND bit, and when the content of C on the
medium is different from that stored in the IDR and the content of C
is FF, then this flag is set.
When data is read from the medium, if the FDC cannot find a Data
Address Mark or Deleted Data Address Mark, then this flag is set.

STATUS REGISTER 3
This bit is used to indicate the status of the Fault signal from
the FDD.
This bit is used to indicate the status of the Write Protected signal
from the FDD.
This bit is used to indicate the status of the Ready signal from
the FDD.
This bit is used to indicate the status of the Track 0 signal from
the FDD.
This bit is used to indicate the status of the Two Side signal from
the FDD.
This bit is used to indicate the status of Side Select signal
to the FDD.
This bit is used to indicate the status of the Unit Select 1 signal
to the FDD.
This bit is used to indicate the status of the Unit Select a signal
to the FDD.

552

PROCESSOR INTERFACE
Ouring Command or Result Phases the Main Status Register (described earlier) must be read by the processor
before each byte of information is written into or read from
the Oata Register. After each byte of data read or written to
Oata Register, CPU should wait for 12 f.Ls before reading
MSR. Bits 06 and 07 in the Main Status Register must be
in aO and 1 state, respectively, before each byte of the command word may be written in the FOC 9268. Many of the
commands require multiple bytes, and as a result the Main
Status Register must be read prior to each byte transfer to
the FOC 9268. On the other hand, during the Result Phase,
06 and 07 in the Main Status Register must both be 1's (06
= 1 and 07 = 1) before reading each byte from the Oata
Register. Note, this reading of the Main Status Register
before each byte transfer to the FOC 9268 is required in
only the Command and Result Phases, and NOT during the
Execution Phase.
Ouring the Execution Phase, the Main Status Register need
not be read. If the FOC 9268 is in the NON-OMA Mode, then
the receipt of each data byte (if FOC 9268 is reading data
from FOO) is indicated by an Interrupt sig.om on pin 18 (INT
= 1). The generation of a Read signal (RO = 0) or Write
signal (WR = 0) will reset the Interrupt as well as output the
Oata onto the Oata bus. If the processor cannot handle
Interrupts fast enough (every 13 f.Ls) for MFM and 27 f.Ls for
FM mode, then it may poll the Main Status Register and then
bit 07 (ROM) functions just like the Interrupt signal. If a Write
Command is in process then the WR signal performs the
reset to the Interrupt signal.
If the FOC 9268 is in the OMA Mode, no Interrupts are generated during the Execution Phase. The FOC 9268 generates ORO's (OMA Requests) when each byte of data is
available. The OMA Controller responds to this request with
both a OACK = 0 (OMA Acknowledge) and a RO = 0 (Read
sl9.o.£!). When the OMA Acknowledge signal goes low
(OACK = 0) then the OMA Request is reset (ORO = 0). If
a Write Command has been programmed then a WR signal
will appear instead of RO. After the Execution Phase has
been completed (Terminal Count has occurred) or EaT
sector was read/written, then an Interrupt will occur (INT =
1). This signifies the beginning of the Result Phase. When
the first byte of data is read during the Result Phase, the
Interrupt is automatically reset (INT = 0).

It is important to note that during the Result Phase all bytes
shown in the Command Table must be read. The Read Oata
Command, for example has seven bytes of data in the Result
Phase. All seven bytes must be read in order to successfully complete the Read Oata Command. The FOC 9268
will not accept a new command until all seven bytes have
been read. Other commands may require fewer bytes to be
read during the Result Phase.
The FOC 9268 contains five Status Registers. The Main
Status Register mentioned above may be read by the processor at any time. The other four Status Registers (STD,
ST1, ST2, and ST3) are only available during the Result
Phase, and may be read only after completing a command.
The particular command which has been executed determines how many of the Status Registers will be read.
The bytes of data which are sent to the FOC 9268 to form
the Command Phase, and are read out of the FOC 9268 in
the Result Phase, must occur in the order shown in the
Command Table. That is, the Command Code must be sent
first and the other bytes sent in the prescribed sequence.
No foreshortening of the Command or Result Phases are
allowed. After the last byte of data in the Command Phase
is sent to the FOC 9268, the Execution Phase automatically
starts. In a similar fashion, when the last byte of data is read
out in the Result Phase, the command is automatically
ended and the FOC 9268 is ready for a new command.

POLLING FEATURE OF THE FDC 9268
After the Specify command has been sent to the FOC 9268,
the Unit Select line USO and US1 will automatically go into
a polling mode. In between commands (and between step
pulses in the SEEK command) the FOC 9268 polls all four
FOO's looking for a change in the Ready line from any of
the drives. If the Ready line changes state (usually due to
a door opening or closing) then the FOC 9268 will generate
an interrupt. When Status Register 0 (STO) is read (after
Sense Interrupt Status is issued), Not Ready (NR) will be
indicated. The polling of the Ready line by the FOC 9268
occurs continuously between commands, thus notifying the
processor which drives are on or off line. Each drive is polled
every 1.024 ms except during the Read/Write commands.

AC TEST CONDITION
INPUTIOUTPUT

CLOCK

24V

30V---,

o 45V

03V _ _ _J

ACTESTING
Inputs are dnven al 2 4V for a logiC "1" and OA5V for a logic "0," Timing
ments are made at 2 OV for a logiC "1" and O.BV for a logiC "0'

measure~

Clocks are driven at 3.0V for a logiC "1" and Q,3V for a logic "0," Timing measurements are made at 2.4V for a logic "1" and O.65V for a logiC "0:'

553

FOC 9268 COMPATIBILITY
The FDC9268 is software and hardware compatible with
the FDC9266 with the following qualifications pertaining to
Precomp and clock input.
-A 16 MHz clock is used on the FDC9268.
- The precomp specifications for the FDC9267 and
FDC9266 can be used for the FDC9268 with the following
qualification. Whenever the precomp select line P2 is
active, the FDC9268 uses the maximum precomp available in that mode (Le. 375 nsec in the 250 Kb/s mode and
187.5 nsec in the 500 Kb/s mode).

MINI

P2

P,

Po

PRECOMP VALUE (nsec)

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
125.0
250.0
375.0
375.0
375.0
375.0
375.0
0
62.5
125.0
187.5
187.5
187.5
187.5
187.5

Write Precompensation Value Selection

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. .'. .
OOG to + 700G
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... - 55°C to + 150°C
All Output Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5 to + 7 Volts
All Input Voltages ............................................................................................. - 0.5 to + 7 Volts
Supply Voltage Vee ............................................................................................ - 0.5 to + 7 Volts
Power Dissipation ....................................................................................................... , 1 Watt
T. = 25°C
'COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

DC CHARACTERISTICS T. = O°C to
PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Voltage
(ClK + WR Clock)
Input High Voltage
(ClK + WR Clock)
Vee Supply Current

+ 70°C; Vee
SYMBOL
VIL
V,H
VOl
VOH

VIL'~'

=

+ 5V

± 5% unless otherwise specified.

MIN
-0.5
2.0

LIMITS
TYPcy

eI>o
eI>,

5% unless otherwise specified.

MIN
60
20

LIMITS
TYPeD
62.5

~'.

MAX
250

500
500

UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

200

f1s
ns

10
10

,b,
TAA
TRA
TRA
THO
Toe
TAW
TWA
Tww
Tow
Two
TA,
Tw,

0
0
250

TMCY

13

200
100

20
0
0
250
150
5

TAM
Tre
Tus
TSD

20
280
12
7

-+j~

F R I S T P t - - - - - - - - - - - - -....

lCT/DIR 1 - - - - - - - - - - - - - - - -.....---1

VCO~::::::::::::::::::::::::::::~::::===--::l:::::~
uso

NT_ INT
C S - CS
R D - RD
WR-WR
A0_ A0
DRO_ DRO
DACK _
DACK
TC _TC
RESET --+ RST

US1

l

HDlr--~~------~:::;::~::~----r_~
RDY _RDY
IQx _IDX

~~ h~~ESEl

II :
1

WDIN

Illx~lillN6~lvl!

PS0

::g~

DVCC ...g4+ 5V

'--+----+1

EARLY VCO SYNC 1 :: rQ
P0
XTAl2
WDOUT 1-=2"-1_ _ _ _ _---'

~~O-'-=------'

r----"-..I lATE

II "M~~"" ~

WDA

L-l.

CLK~

XTAL1

6 WCK

RDD

~~~ r-ClK I+-

MFM
ClK

RDD
RDW

~

RDIN

"F-o-cn--C'-6-s-o---'r
F0C765A

7
8

10

MINI

MFM ~ MFM

I~
I.....

147K
5%

~~:~~:nh~~: ~~e~~yi~I~~~r~::hng

RDIN

lFOI

PDOUT

lFIN
VIR

DONO

DGND

.~~I

AVCC!f.-+5Vrr.;lJ:!:LC

l [ 1 1 RBT

'To avoid soft errors caused by
transmission line effects and

eLK

1+.:.19,,-_ _ _ _---,

~ T~~~f 1~
15 24.9K 1%MLC
14

AGND::"

FDC92C81

J

.~,",:,,,

75K

AGND

5%

J~ '~bt

and the controller board, the use of a
(non-Inverting) TTL
schmldt-tngger input gate or bus
transceiver is recommended at
the DSKO Input to the FDC92C81.

MLC

AVSS

TYPICAL SYSTEM IMPLEMENTATION

'I

XTAL1/Xl:Al2

OSCilLATOR

I

16MHz

.1 COUNTER
SHUFFLE
r-lO§CllLATOR)
500
KHz

1MHz
B/4MHz

I
250
KHz
~

MINI

I

MFM

I

CLOCK
GENERATOR ~8MHZ

~~~~~T
+

I

II

DETECtO~1 ~

EDGE
SYNCHRONIZER

RDIN

ClK
WCK

I

I

PHASE
COMPARATOR

PDOUT

-.t

VCO
SYNC

[:J
l J

lFIN
lFOI
VREF

CLOCK DIVIDERI
SELECTOR

PO

EARlY/lATE

WDIN

-

~
lATCH

PRECOMPENSATION
lOGICIWRITE DATA
TIMING

r1

I

I

1
558

LI

READ DATA/READl
DATA WINDOW
GENERATOR

J

RDW
RDD
WDOUT

BLOCK DIAGRAM
FDC92C81

TABLE 1-FDC92C81 DESCRIPTION OF PIN FUNCTIONS
PIN NO.

SYMBOL

1

NAME
Write Data In

WDIN

I/O
I

2

Early

EARLY

I

3

late

lATE

I

DESCRIPTION
This input contains the serial clock and data bits which may
be precompensated and output to the drive.
Used for precompensation. When high, the write data bit will
be written early. Refer to table below.
Used for precompensation. When high, the write data bit will
be written late.
EARLY
lATE
PULSE POSITION
0
0
nominal
1
0
early
0
1
late
1
1
not used
A 16.000 MHz parallel resonant crystal may be connected
between XTAl1 and XTAL2. If a TTL signal is used in place
of a crystal, the signal should be connected to XTAl1 while
XTAl2 is left unconnected.

4
5

Crystal
Crystal

XTAL2
XTAl1

0

6

Write Clock

WCK

0

This output contains the clock which cQntrols the rate at
which data is written to the drive. See table for MINI pin.

7

Read Data

RDD

0

This output contains the reclocked encoded bit stream from
the drive.

8

Read Data Window

RDW

0

9

Read Data In

RDIN

I

10

Phase Detect Out

PDOUT

0

11

Bias Reference

RBT

I

Digital Ground

DGND
AGND

This output is a function of the internal VCO frequency
which tracks and properly frames the encoded drive bit
stream for reliable clocking into the floppy disk controller.
This input is the read data from the floppy disk drive. The
input is active low. The leading edge (high to low transition)
is used for all frequency tracking operations.
The output of the phase detect circuit. A 75K 5% resistor is
connected between this output and lFIN.
An external 147K 5% resistor connected between this pin
and AVCC establishes a bias reference current for the VCO.
This input should not be forced low.
Digital Ground
Analog Ground

12
13

I

14

Analog Ground
Voltage to Current
Reference

VIR

I

15

low-pass Filter In

lFIN

I

16

low-pass Filter

lFOI

1/0

17
18

AnalogVcc
MFMMode

AVCC
MFM

I

19

MINI

MINI

I

20
21

Clock
Write Data Out

ClK
WDOUT

0
0

559

A 24.9K 1% metal film resistor connected between this pin
and AVSS establishes a current reference for the on-chip
voltage to current converter which is part of the VCO.
This is the input to the low pass filter amplifier. A resistor is
connected between this input and PDOUT and a low pass
filter is connected between this input and lFOI.
This pin is the output of the low pass filter amplifier and the
input to the VCO.
+ 5V analog power supply
When this input is high, the chip is in MFM mode. When low,
the chip is in the FM mode.
This input, along with the input P0 specifies the amount of
precompensation to be used. See table for the P0 pin. This
input along with MFM controls the ClK and WCK outputs.
MFM
MINI
WCK
ClK
0
0
500KHz
8MHz
0
1
250KHz
4MHz
1
1MHz
8M Hz
0
1
1
500KHz
4MHz
This output is a 4MHz or 8M Hz clock. See table above.
This output is the precompensated serial write data to the
floppy disk drive.

TABLE 1-FDC92C81 DESCRIPTION OF PIN FUNCTIONS CONTINUED
PIN NO.
22

23
24

SYMBOL

NAME
Precompensation

P0

VCOSync
DigitalVcc

VCOSYNC
DVCC

DESCRIPTION
This input along with the MINI input specifies the amount of
precompensation to be used.
MINI
PO
PRECOMP
O.Ons
a
a
1
62.5ns
0
O.Ons
1
0
1
1
125.0ns

I/O
I

I

VCO locks to clock when low and to data when high.
+ 5V digital power supply.

MODE GAIN IMPLEMENTATION
The phase locked loop gain of the FDC92C81 is controlled
by switching between two modes of operation, shuffle
oscillator and arm on data. The mode change is via VCO
SYNC. The shuffle oscillator mode is considered the high
gain mode and the arm on data mode is considered the low
gain mode.

Arm On Data Mode
The purpose of the arm on data mode is to reduce the gain
so that the chip can handle higher amounts of bit jitter. In
this mode, each code bit received from the drive resets the
phase compare circuits and a counter (shuffle oscillator).
The phase compare circuits are only armed for one compare
cycle after each code bit. The counter is set such that V4 bit
cell after the phase compare reset has gone away, it creates
an edge. (Only one compare is performed until the next code
bit is received.) This edge is compared against the edges
of the VCO by the phase compare circuits. The relationship
between these edges is used to generate one pump-up or

pump-down signal. Therefore, in this mode, each code bit
causes only one update to the loop.

Shuffle Oscillator Mode
The shuffle oscillator mode allows for a fast lock to data time
when attempting to acquire data synchronization. In this
mode, each code bit received from the drive resets the phase
compare circuits and a counter (shuffle oscillator). The
phase compare circuits are always armed. The counter is
set such that % bit cell after the phase compare reset has
gone away, it creates an edge. Each % bit cell thereafter
creates an edge until reset by another code bit. This edge
is compared against the edges of the VCO by the phase
compare circuits. The relationship between these edges is
used to generate pump-up/pump-down signals. In MFM
codes, the minimum spacing between code bits is one bit
cell, the maximum spacing is two bit cells. Therefore, in this
mode, each code bit can cause up to four updates to the
loop. This is how the gain of the loop is increased.

TYPICAL PERFORMANCE SPECIFICATIONS
PARAMETER
Bit Jilter
Nominal Speed
+5% Speed
-5% Speed
Window Margin
Early
Late

500KHz

300KHz

250KHz

UNITS

380
360
380

620
600
660

760
740
840

nsec
nsec
nsec

480
400

800
720

860
820

nsec
nsec

I Lock to Encoded Data

less than 3 bytes

560

ELECTRICAL CHARACTERISTICS
MAXIMUM GUARANTEED RATINGS
Operating Temperature Range .................................................................................... O°C to + 70°C
Storage Temperature Range ................................................................................. - 55°C to + 150°C
lead Temperature (soldering, 10 sec.) .................................................................................. + 300°C
Positive Voltage on any Pin, with respect to Ground ................................................................... Vcc + 0.3V
Negative Voltage on any Pin, with respeCt to Ground ...................................................................... - 0.3V
Power Dissipation ........................................................................................................ 0.25W
Positive Voltage on Vee Pin, with respect to Ground .......................................................................... 7.0V
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or at any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the "Maximum Guaranteed Ratings"
not be exceeded, or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when AC power
is switched off. In addition, voltage transients on the AC power supply line may appear on the DC output. If this possibility exists it is
suggested that a clamp circuit be used.

DC ELECTRICAL CHARACTERISTICS TA = O°C to 70°C, Vee = 5.0V ± 5% unless
PARAMETERS

MIN

TYP

MAX

UNITS

INPUT VOLTAGE

otherw;".-"'~""II-·
..· I

COMMI:I~~~

WDIN, EARLY,
lATE, RDIN, P0, SYNC

V

High Level V'L
High level V,H

-0.3
2.0

0.8
(VCC)

V

INPUT VOLTAGE
Low level V'L
High level V,H

-0.3
3.2

0.8
(VCC)

V
V

XTAL 1, XTAl2

OUTPUT VOLTAGE

V

0.4

Low level VOL

V

2.4

High Level VOH

ClK, WCK, RDD, RDW, MFM, MINI,
WDOUT
10L = 1.6mA except ClK
10L = 0.4mA, ClK only
10H = -100uA except ClK
10H = - 400uA, ClK only

POWER SUPPLY CURRENT

Icc
INPUT lEAKAGE CURRENT
I'L
INPUT CAPACITANCE

TBD

mA

TBD

uA

V,N = OtoVee
WDIN, EARLY, lATE, RDIN, P0,
SYNC,XTAl1

pF

TBD

AC ELECTRICALCHARACTERISTICSTA = OOCt070°C, Vee = 5.0V
TYP

MAX

±5%unlessothe~f!f!!,~L."
UNIT
LOArL. ~~'!l!!""tr

PARAMETERS

5MBL

MIN

Read data width

T,

40

ns

20Pf~'

Window setup time

T2

15

ns

20pf

Window hold time

T3

15

ns

20pf

Window cycle time

T.

us
us
us
us

20pf

ns

20pf

us
us
us

20pf
20pf
20pf

2
1
4
2

WCKhigh

T.

WCK cycle time

T.

ClKhigh

T7

40

ns

20pf

ClKlow

T.

40

ns

20pf

80

250

350

4
2
1

ClKperiod

T.

120

WDOUTwidth

T••

250

ClK t to WCK t delay

T,.

0

315

561

500

ns

20pf

350

us

20pf

40

ns

MFM = 0
MFM = 1
MFM = 0
MFM = 1

MINI = 0
MINI = 0
MINI = 1
MINI = 1

125KHz data rate
250KHz data rate
500KHz data rate

x2ifmini = 1

AC ELECTRICAL CHARACTERISTICS CONTINUED
PARAMETERS
ClK i to WCK

5MBL

1delay

WDOiJT early rising edge to
WDOUT nom. rising edge

MIN

TYP

0

T"
T12

MAX

UNIT

40

ns

Desired Precomp Value

WDOUT nom. rising edge to
WDOUT late rising edge

T,.

Pre-shift delay time from
WCK positive edge

T'4

20

100

ns

WDIN delay time
rising edge of WCK to
rising edge of WDIN,
falling edge of WCK to
falling edge of WDIN

T15

20

100

ns

WDINwidth

TlO

30

300

ns

Read data width

T17

100

Read data cycle time

TlO

~
,' .

see table for pin 22

see table for pin 22

Desired Precomp Value

200

.".

~~Tht&.

LOAD~'"

ns
2
2
4
4

SOO Kb/s MFM,
2S0 Kb/s FM
2S0 Kb/s MFM,
12SKb/s FM

us
us
us
us

The following Inputs are DC levels: MFM, MINI, Po.
50,-------------------------------~

'.0

TYPICAL VCO VOLTAGE IN
VS. FREQUENCY

30

2.0

FDC92C81

tyPICAL

1.0

0.0

+----,-------,-------.----...,-----r---_+_
0.5

'.5

2.5
FREQUENCY (MHZ)

INPUT TIMING

WCK

EARLY
LATE

WDA

RDIN"

562

3.5

OUTPUT TIMING

RD0~T'~\

/

RDW

X

I

I:-T,-

WCK~

~

t:= s-4
T

T,

T,

/

.,

r~
T'41

\-.-

WDOUT
(early)

.-A

WDOUT
(nominal)

W~

\
I-T9a--i

WDOUT
(LATE)

NOTE: For an updated data sheet please fill out the reply card in
the back of this catalog or call SMC at (516) 273-3100.
563

\

2.45"

RESISTOR VALUES
R1
R2
R3
R4

XTAL

10K5%
75K5%
24.9K 1% metal Iilm
147K5%

CAPACITOR VALUES
C1
C2
C3
C4
C5
C6
C7

TOP
GROUND
PLANE

REDUCE TO
2.500 ± .005"

••

.l1li

REDUCE TO
2.500 ± .005"

.003 ul 10% MLC
220 pi 10% MLC
.47ul 10% MLC
.22uI10%
.22 ul 10%
60 pi 10%
60 pi 10%

••

,
•

L

SOLDER SIDE

COMPONENT SIDE

.J

NOTE: The printed circuit board artwork shown above is included for illustration only. Camera ready artwork is available through
your SMC representative or regional sales office.
Blank PC boards (based on the illustrations above) are also available to facilitate evaluation and design. Contact your SMC
representative or regional sales office for more information.
Circu~ diagrams utilizing SMC products are included as a means 01 illustrating typical semiconductor applications; consequently ocmplete information sufficient for construction purposes is not necessarily given. The information has been
carefully checked and is believed to be entirely reliable. However, no responsibility IS assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under
the patent rights of SMC or others. SMC reserves the right to make changes at any time In order to i.mprove design and
supply the best product possible.

564

Floppy Disk
Controller/Formatter
FDC

FOC 9791
FOC9793
FOC9795
FOC 9797
I-lPC FAMILY

PIN CONFIGURATION

FEATURES

0+5 VOLT ONLY VERSION OF FDC179X-02
SOFT SECTOR FORMAT COMPATIBILITY
o AUTOMATIC TRACK SEEK WITH VERIFICATION
o ACCOMMODATES SINGLE AND DOUBLE
DENSITY FORMATS
1
40
NC
NC
3.
INTRa
WE
IBM 3740 Single Density (FM)
3.
DRO
cs
37
DDEN
fiE 4
IBM System 34 Double Density (MFM)
3.
WPRT
Ao
Wi5"Rf 40
READ MODE
35
iP
A,
D5'E'N 41
7
34
TROO
DALO'
Single/Multiple Sector Read with Automatic Search
33
DAll'
WFNFOE
•
ROY
DAL2'
or Entire Track Read
10
31
WD
32
DAL3'
NC
Selectable 128 Byte or Variable Length Record
11
30
WG
DAL4'
NC
12
29
TG43
DALS'
WRITE MODE
WE
3
13
2.
HLD
DALB'
cs
14
27
RAW READ
DAL7"
Single/Multiple Sector Write with Automatic Sector
15
2.
RCLK
EARLY
STEP
25
Search
RG/SSO
Ao •
DIRe
DIRe
24
17
ClK
EARLY
Entire Track Write for Diskette Initialization
23
HlT
LATE
22
TEST
MR
PROGRAMMABLE CONTROLS
21
20
Vee
GND
Selectable Track to Track Stepping Time
PACKAGE: 44 pin PLCC
'INVERTED BUS FOR FOG 9791, FOG 9795
Side Select Compare
PACKAGE: 40 pin 0.1 P.
'Inverted Bus for FDC9791, FDC9795
SYSTEM COMPATIBILITY
Double Buffering of Data 8 Bit Bi-Directional Bus for
Data, Control and Status
DMA or Programmed Data Transfers
INCORPORATES ENCODING/DECODING
All Inputs and Outputs are TTL Compatible
On-Chip Track and Sector Registers/Comprehensive
AND ADDRESS MARK CIRCUITRY
Status Information
COMPATIBLE WITH FDC 179X-02
COPLAMOS® n-CHANNEL MOS TECHNOLOGY
WRITE PRECOMPENSATION (MFM AND FM)
COMPATIBLE WITH THE FDC 9216 FLOPPY DISK
SIDE SELECT LOGIC (FDC 9795, FOC 9797)
DATA SEPARATOR
WINDOW EXTENSION (IN MFM)

o

~

o

·0

o

,.

,.,.

o

o

o
o
o
o

o
o
o

GENERAL DESCRIPTION
The FDC 979X is an MOS/LSI device which performs the
functions of a Floppy Disk Controller/Formatter in a single chip implementation. The basic FDC 979X chip design
has evolved into four specific parts: FDC 9791, FDC 9793,
FDC 9795, and the FDC 9797.

mode (MFM). The FDC 9791 contains enhanced features necessary to read/write and format a double
density diskette. These include address mark detection,
FM and MFM encode and decode logic, window extension, and write precompensation.

This FDC family performs all the functions necessary
to read or write data to any type of floppy disk drive.
Both 8" and 5114" (mini-floppy) drives with single or double
density storage capabilities are supported. These nchannel MOS/LSI devices will replace a large amount of
discrete logic required for interfacing a host processor to
a floppy disk.

The FDC 9793 is identical to the FDC 9791 except the
DAL lines are TRUE for systems that utilize true data
busses.
The FDC 9795 adds side select logic to the FDC 9791.
The FDC 9797 adds the side select logic to the FDC 9793.
The processor interface consists of an 8 bit bidirectional
bus for data, status, and control word transfers. This family of controllers is configured to operate on a multiplexed
bus with other bus-oriented devices.

The FDC 9791 is IBM 3740 compatible in single density
mode (FM) and System 34 compatible in double density
565

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
applications: consequentiy oomplete information sufficient for construction purposes is not necessarily given.
5~~§~~~~~~~~=; The
information has been carefully checked and is believed to be entirely reliable. However. no responsibility is
,,.,,~,,.

"'_•• " "". assumed for inaccuracies. Furlhermore. such information does not convey to the purchaser of the

'"'' ",.,,00 . "',.".",..... semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design and supply the best product possible.

566

~HardDisk
1laz.J)isk

:ran

J)isk I'ImD.at

Kv.:m.ber
MSD95000
MSD96C02
MSD7262
B009234
B0092C28

SCSI

Da~.

nda 'Ita1Iater

RLL 2 7114FM1NltZ/GOR
RLL2,7IW'MJNRZ1GOR

:aate

IBM\1I> POI.ATI1I>, ST·5OO

MFM,FM

20Mb/sec
24Mb/sec
18Mb/sec
5Mb/sec

ST-506

MFM,FM

5Mb/sec

UserD&fl.ned

ESDI

NBZ

Bar4Jiialt

DlRa
Elltter:nal
extern.a.l

lIower

extern.a.l

+SV
+SV
+SV
+SV

AnaJ.og,

+5V

extern.a.l

ex:terna.l VCO

B009223
B009224

ST-506
DllICVAX\1I>, MIcoov:AX\1I>;
ST·606

MFM.FM
MFl4,FM

6Mb/sec
5Mb/sec

VCOonlv
6.ltt$rnal

+5V
+SV

HD092C27

ST-606

MFl4,FM

5Mb/sec

AnaJ.O~
external CO

+6V

HDC92C25

8'1'·606
DCST·606

HDC7280

NECST-B06

MFl4 :PM
MFM,FM
MFl4 FM

5Mb/sec
12Mb/sec
6Mb/sec
5Mbisec

extern.a.l

BOO 7281

+SV
+SV
+SV
+SV

BOO 1100-01, SA1000, ST·5OO
·12 .()3 .Q5

NBZ,MFM,FM

567

exiiernaJ
ex:terna.l

external

l'acJtage

:rage

68PLOO
68PLCC
40 DIP
40 DIP,
44PLOO
24 DIP,
28PLOO
14 DIP
40 DIP,
44PLOO
28 DIP,
28PLCC
48 DIP
40 DIP
40 DIP
20 DIP

681-692
693·736
677-660
637-675
627-634
685-588
689-624

635-636
626-626
583-584
579-562
569-678

568

HDC 1100-01
PRELIMINARY

Hard Disk Serial to Parallel Converter
PIN CONFIGURATION

FEATURES

o Single + 5 Volt Power Supply
o Double Buffered
o Byte Strobe Outputs
o 5 MBit Shift Rate
o Seriallnput/Paraliel Out
020 Pin DIP
On-Channel COPLAMOS®Silicon Gate Technology

ClK 1

20 Vee

NC 2

19 EN

BClR 3

18 NRZ

TEST 4

17 ST

000 5

16 OOUT

001

15 BOONE

6

002 7

14 SHFClK

003 8

13 007

004 9

12 006

Vss 10

11 DOS

GENERAL DESCRIPTION
The HOC 1100-01 converts NRZ data from a Winchester
disk drive into eight bit parallel form. Additional inputs are
provided to initiate the conversion process, as well as output strobes to indicate the completion.

ST----,

+5Vr--~_-'

The HOC 1100-01 contains two sets of 8 bit registers. This
allows one register to be read (in parallel) while serial data
is being shifted into the other.

+5V

8 Q~'-~
Bit
Counter
cp

TEST

BOONE
EN
~----+---

NRZ--+~rct---~8~B~it---C~~
ClK

_-+~

Shift Register

~--'-T""'T'T""T-.-r-r----I

000 001 002 003 004 DOS 006 007

569

BClR

>--+--~ OOUT

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.
~~~I~~~!;~!;! Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor

~

applications: consequently comJllete information sufficient for construction purposes is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design and supply the best product possible.

570

HDC 1100-12
PRELIMINARY

Hard Disk Improved MFM Generator
FEATURES

PIN CONFIGURATION

o Single + 5 Volt Power Supply
o Write Precompensation
o Address Mark Generation
o 5 Mbit Data Rate
o Converts NRZ to MFM
020 Pin DIP
On-Channel COPLAMOS® Silicon Gate Technology

NRZ

1

SKPEN

2

19 AO

WCLK

3

18 A1

WCLK

4

17 MR

RWC

5

16 MFM
15 INTRO

20 Vee

CS

6

DROCLK

7

14 ORO

INTCLK

8

13 EARLY

2XDR

9

12 LATE

Vss 10

11 NOM

GENERAL DESCRIPTION
The HOC 1100-12 "improved" MFM Generator converts
serial NRZ data into an MFM (Modified Frequency Modulated) data stream. The MFM signal may be used to record
information on a Winchester Disk.
In addition, the HOC 1100-12 generates Write Precompen-

RWC

sation signals required to compensate for bit shift effects
on the recording medium.
The HOC 1100-12 has the ability to delete clock pulses in
the outgoing data stream in order to record Address Marks.

DROCLK
ORO

NRZ
WCLK

WCLK

4BIT
SHIFT
REG.

WRITE
PRECOMP
GEN.
MFMGEN

EARLY
NOM
LATE
INTCLK
INTRO
MFM

AO
A1

DECODE
LOGIC

CS
SKPEN

MR

MFM GENERATOR

INTERRUPT CONTROLLER

571

For additional information, consult your 1986 catalog or contact our product marketing department at (516) 273·3100.

~

!~!!!;! Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
applications: consequently complete information sufficient for construction purposes is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the best product possible.

572

HDC 1100-03
PRELIMINARY

Hard Disk Address Mark Detector
PIN CONFIGURATION

FEATURES
D Single + 5 Volt Power Supply
D Decodes A 1-0A
D Synchronous Clock/Data Outputs
D 5 MBit Data Rate
D Address Mark Detection
D20PinDIP
D n-Channel COPlAMOS ® Silicon Gate Technology

RClK 1
DIN 2

20

vee

19 RST

RClK 3

18 CP

ClKIN 4

17 NC

DOUT 5

16 AMDET

NC 6

15 AMDET

NC 7

14 QOUT

TEST1

8

ENDET 9
Vss 10

13 NC
12 DClK
11 TEST2

GENERAL DESCRIPTION
for a DATA = A 1, ClK = OA pattern and produces and AM
DET signal when the pattern has been found. NRZ data is
output from the device for driving a serial/parallel converter.
An uncommitted latch is also provided for use by the data
separator circuitry if required.

The HDC 1100-03 Address Mark Detector Provides an efficient means of detecting Address Mark Fields in an MFM
(NRZ) data stream. MFM clocks and data are fed to the
device along with a window clock generated by an external
data separator. The HDC 1100-03 searches the data stream

CP
RST

HV~

:

DIN
RClK

r-------------~.~ QOUT

Q 1-------1- DOUT

D
C
R

8BIT
SHIFT REG

r----- TEST 1
r--'--'---'-'--'--'-..L---Lt-_____ DClK
ENDET

1----- AMDET
li-L,-r-r--r-r-r-r..---,,J>---AMDET
L...-_ _ _ _ _ TEST 2
R

ClK IN

----+---1 D

8BIT
SHIFT REG

RClK --~-aC

573

Q

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.

~

~,~~~~:~ Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
';',ce","," "'''''',., ,,,,,
,",' '" "00 ' 'W, ''0

m""""

applications: consequently complete information sufficient for construction purposes is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the best product possible.

574

HDC1100-Q4
PRELIMINARY

Hard Disk CRC Checker/Generator
FEATURES

PIN CONFIGURATION

o Single + 5 Volt Power Supply
o Generates/Checks CRC
o Latched Error Outputs
o CCITT-16 CRC
o Automatic Preset

DIN

1 [

DOCK 2 [
SHFCLK 3 [

D20Pin DIP
On-Channel COPLAMOS®Silicon Gate Technology

NC 4 [
NC 5 [
CWE 6 [

P 20

Vee

P 19 NC
P 18 NC
P 17 NC
P 16 CRCOK
P 15 TIMCLK

DaCE 7 [

] 14 WCLK

CRCIZ B [

] 13 CRCOK

NC 9 [

] 12 SKPCLK

Vss 10 [

] 11 DOUT

GENERAL DESCRIPTION
The HDC 1100-04 CRC Checker/Generator generates a
Cyclic Redundancy Checkword from a serial data stream,
and checks for the proper CRC in a received serial data

stream. In addition to the transmitted CRC output, complimentary latched "CRCOK" outputs are provided to indicate
CRC errors in the check mode.

CRCIZ---...,

1-_-----0- SKPCLK
--*~D
SHFCLK
DOCE

POLYNOMIALGEN

x'. + x12 + x' +

1

a

~-t==~c~============~==~U
-----I

1 - - - - 4 - - - 4 + - - CWE

DOCK----d
. - - -__ CRCOK

":>01--- CRCOK
WCLK ..
---~

+ 16

1-------- TIMCLK
575

For additional information, consult your 1986 catalog or contact our product marketing department at (516) 273-3100.
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
" • • • • • applications: consequently complete information sufficient for construction purposes is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the best product possible.

Ii

576

HDC1100-05

STANDARD MICROSYSTEMS
CORPORATION

PRELIMINARY

Hard Disk Parallel to Serial Converter
FEATURES

PIN CONFIGURATION

o Single + 5 Volt Power Supply
o Double Buffered
o Byte Strobe Outputs
o 5 Mbit Data Rate
o Parallel In/Serial Out

iJ

00 1 [

D20PinDIP
On-Channel COPLAMOS ® Silicon Gate Technology

20 Vee

2 [

P19 EN

02 3 [

] 18 NC

03 4 [

] 17 TEST

01

04 5 [

] 16 BOONE

05

6 [

] 15 OOUT

06

7 [

] 14 SHFCLK

07 8 [

] 13 LO

SHFCLK 9 [

] 12 WCLK

vss 10 [

] 11 OCLK

GENERAL DESCRIPTION
The HDC 1100-05 converts bytes of parallel data to a serial
data stream for writing to disk memories or other serial
devices. Parallel data is entered via the DO-D7Iines. A synchronous byte counter is used to signify that 8 bits of data

B

00-07
OCLK

;

/

0
C

BBIT
LATCH

0

I

9

rL-J

WCLK

have been shifted out and that the 8 bit latch is ready to be
reloaded. The double buffering of the data permits another
byte to be loaded while the previous byte is in the process
of being shifted.

B
I

T~Vo

BYTE
C COUNTER Q

--

C

,l,
0

LO

EN

V

1

>-- BOONE
LO

577

SHFCLK

>- SHFCLK

R

C

OOUT

BBITSHIFT
REG

I

+t- o

01--'--0..-

0

I

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.

STANoo.RD MICROSYSTEMS
ATION

~

35Ma"t'11SaYCt,IiIUIIINIJge,NYl178(1

(5181213·3100.1\IIX·510·227·8898

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
applications: consequently complete information sufficient for construction purposes is not necessarily given.
The information has been carefully check!ld and is believed to be entirely reliable. However. no responsitillity is
assumed for inaccuracies. Furthermore. such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design and supply the best product possible.

578

HDC7260
PRELIMINARY

Universal Disk Controller
FEATURES
o Hard and floppy disk interface
o Controls four drives (any combination)
simultaneously
o Programmable track format
o Transfer rate 6 MHz maximum
o High Level Commands, Including:
Check
Sense Intr. Status
Detect Error
Sense Status
Read Data
Specify1
Read Diagnostic
Specify2
Read ID
Verify Data
Recalibrate
Verify ID
Scan
Write Data
Seek
Write Format
o Parallel seek capability
o Multi-sector, -track, -cylinder read/write capability
o Implied seek function
o CRC error detection
o ECC error detection and correction
o DMA data transfer
o Single +5 volt supply
o 40-Pin Dual-in-line Package
o COPLAMOS® n-Channel Silicon Gate Technology

PIN CONFIGURATION

SYNC
RfW DATA
RCLK
RST
INT
DMARQ

V"
RGATE
WGATE
CLK
INDEX
PCL
PCE
IDSD](2 Side)
ISKC](WPRT)
FLTITRKO
ROY
OS.
DS,
HSo
[HS1[
IHS2](FLTR)
IHS,](HDLD)
RW/SEEK
MFM/STEP
RWC/DIR

TC
WCLK

RB
WR

Ao
Do

0,
02
0,
04

05
06
07
GND

Package: 40·pin DIP

GENERAL DESCRIPTION
The HDC7260 is a single-chip disk controller that is
capable of interfacing to a maximum of four floppy or hard
disks in any combination. The chip utilizes the ST-506
defacto standard for the Winchester disks and is
compatible with a-inch, 51f4-inch and 31f2-inch floppy disks.
The HDC7260 is based on the HDC7261A architecture, but
with changes to enhance performance and flexibility. The

HDC7260 can generate both IBM- and ECMA-compatible
floppy disks and hard disks with the standard format. ECC
and CRC capabilities along with many high-level
commands provide excellent system throughput, and the
single-chip design provides for efficient board space
utilization.

579

RClK
WClK

ClK

RIW DATA

Processing
Unit

RST

Format
Control

SYNC
RGATE
WGATE
INDEX

PCl

Data FIFO

[BxB]

Do-D7

<==>

PE:E
[DSD](2 side)
[SCK](WPRT)

MPX

FlTITRKO
RDY
Disk
Interface
Control

Commandl
Status
Register

OSO
OS,
HSo
[HS1]
[HS2](FlTR)
[HS3](HOlO)

Ao

RW/SEEK

RD
WR
INT
DMARQ

ReadlWrite
liNT
IDMA
Control

MFM/STEP
RWC/DIR

TC

): Floppy disk interface
]: Hard disk interface

HDC7260 BLOCK DIAGRAM

DESCRIPTION OF PIN FUNCTIONS
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12-19
20
21

NAME
PLL SYNC
Read/Write Data
Read Clock
Reset

SYMBOL
SYNC
R/W DATA
RCLK

DESCRIPTION
PLL synchronization output
Read data input or write data output
Read clock input

Interrupt
DMA Request
Terminal Count

RST
INT
DMARQ

System reset input from host computer
Interrupt request output
DMA request output

TC

Terminal count input from DMA

Write Clock

WCLK

Write clock input

Read
RD
Write
WR
Data/Status Reg Select Ao
Data Bus
Do-D7
Ground
GND
Read Write
RWC/DIR
Current/Direction

Host computer read control input
Host computer write control input
Status/command register or FJFO select pin
System data bus connections
System ground
If RW/SEEK = 1, outputs read/write current decrease signal. If
RW/SEEK = 0, outputs the direction RW head is to move.

580

DESCRIPTION OF PIN FUNCTIONS
PIN NO.
22

NAME
MFM Step

SYMBOL
MFM/STEP

DESCRIPTION
If RW/SEEK =1, outputs MFM signal to VCO circuit. If RW/SEEK
=0, outputs STEP signal to move RW head.

23
24

Read Write/SEEK
Head Select 3
(Hold)

RW/SEEK
HS3
(HOLD)

Output signal that specifies function of some multiplexed signals
For hard disk, head select 3 output. For floppy disk, head
load output.

25

Head Select 2
(Fault Reset)

26
27

Head Select 1
Head Select 0
Drive Select
Ready

HS 2
(FlTR)
HS,
HSo
DS,-DSo

For hard disk, head select 2 output. For floppy disk, output to clear
drive fault state.
Head select output to disk drive.
Head select output to disk drive.
Drive select outputs.

ROY

28-29
30
31
32
33
34-35

Fault/Track Zero

FlT/TRK~

Ready input from disk drive.
If RW/SEEK =1, inputs a fault flag from the disk drive. If RW/SEEK
=0, inputs a signal indicating R/W head is over cylinder zero.

Seek Complete
(Write Protect)
Drive Select
(double-sided)
Precompensation
Entry, late

SKC
(WPRT)

Seek complete input from hard disk drive, or write protected input
from floppy disk drive.

DSD
(2 Side)

Drive selected input from hard disk drive, or double-sided disk
input from floppy disk drive.

PCE, PCl

Precompensation early/late output to disk drive.

INDEX
ClK
WGATE

Index hole detect input from disk drive
System clock input from host computer

36
37

Index
Clock

38

Write Gate

39
40

Read Gate
Power Supply

RGATE
Vee

Write gate output to disk drive
Read gate output to disk drive
+5 V (typical)

581

STANIlt\RO MICROSVSTEMS

CORPORATION

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications: consequently complete information sufficientfor construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the right to
make changes at any lime in orderto improve design and supply the best product possible.

582

HDC7261A
PRELIMINARY

Hard Disk Controller
FEATURES

PIN CONFIGURATION

D Flexible interface to various types of Hard Disk Drives
D Programmable Track Format
D Controls up to 8 Drives
D
D
D
D

D
D
D
D

D
D
D
D

Parallel Seek Operation Capability
Multi-sector and Multi-track Transfer Capability
Data Scan and Data Verify Capability
High Level Commands, Including:
READ DATA
SEEK (Normal or Buffered)
READ ID
RECALIBRATE (Normal or Buffered)
WRITE DATA READ DIAGNOSTIC (SMD Only)
WRITE ID
SPECIFY
SCAN DATA
SENSE INTERRUPT STATUS
VERIFY DATA SENSE DRIVE STATUS
DETECT ERROR
VERIFY ID
CHECK
NRZ, FM, or MFM Data Format
Maximum Data Transfer Rate: 12MHz
Error Detection and Correction Capability
Simple I/O Structure: Compatible with Most
Microprocessors
All Inputs and Outputs except Clock Pins are TTLCompatible (Clock Pins Require Pull-up)
Single + 5V Power Supply
40-Pin Dual-in-line Package
COPLAMOS® n-Channel Silicon Gate Technology

SYNC
RWOATA
RWClK
RESET
INT
OREQ

1
2
3
4
5

fC

7
8
9
10
11
12
13
14
15
16
17
18
19
20

~

RO

WR
AO
DO
01
02
03
04
05
06
07
GNO

6

40
'39
38
37
36
35
34
33
32
31
30.
29
28
27
26
.25
24
23
22
21

Vee
BTl
BTO
ClK
INDEX
SCT

usm
SSTG
BOIR
TG3
TG2
TGI
BT2
BT3
BT4
BT5
BT6
BT?
BT8
BT9

(RGATE)
(WGATE)

(PCl)
(PCE)
(OSO)
(SKC)
(TAKO)
(READY)
(WFlT)
(050)
(051)
(HSO)
(HS1)
(HS2)
(RWC)
(Si'EP)
(OIR)

PACKAGE: 4o-pin D.I.P.

Note: Signals shown in parentheses are used when the HOC7261
is in the floppy-like mode.

GENERAL DESCRIPTION
The HDC7261 Hard D,isk Controller is an intelligent microprocessor peripheral designed to control a number of different types of disk drives. It is capable of supporting either
hard-sector or soft-sector disks and provides all control signals that interface the controller with either SMD disk interfaces or Seagate floppy-like drives. Its sophisticated
instruction set minimizes the software overhead for the host
microprocessor. By using the DMA controller, the microprocessor needs only to load a few command bytes into the
HDC7261 and all the data transfers associated with read,

write, or format operations are done by the HDC7261 and
the DMA controller. Extensive error reporting, verify commands, ECC, and CRC data error checking assure reliable
controller operation. The HDC7261 provides internal
address mark detection, ID verification, and CRC or ECC
checking and verification. An eight-byte FIFO is used for
loading command parameters and obtaining command
results. This makes the structuring of software drivers a
simple task. The FIFO is also used for buffering data during
DMA read/write operations.

583

~

~,~~~:=~ Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
IWplications: consequently complete information sufficient for construction purposes is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsiDllity is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design and supply the best product possible.

584

HDC9223
PRELIMINARY

High Performance
Analog Data Separator Support Circuit
(ADSSC)
For Hard Disk

FEATURES

PIN CONFIGURATION

o Significantly reduces component count in hard
disk systems

o Completely compatible with the HDC 9226 Hard

Disk Data Separator and the HDC 9224 Universal
Disk Controller
RDGATE
PMPUP
PMPDWN
GND
4xVCO
CX1
CX2

o Simplifies design and improves performance of ST506
Hard Disk Controller sUb-system

o Eliminates costly critical "tune up" adjustments
o Space saving 14 pin package
o Monolithic analog solution reduces critical pc
o
o

11

12V
F2
F1
AGND
C1

C2
7

R1

board layout
Single + 12V power supply
Printed Circuit Board Artwork available to facilitate
prototyping and evaluation

GENERAL DESCRIPTION
The HDC 9223 Analog Data Separator Support Circuit
(ADSSC) is a 14 pin device, which when used with the HDC
9224 Universal Disk Controller and the HDC 9226 Hard Disk
Data Separator significantly simplifies the design of a high
performance hard disk data separator.
The HDC 9223, combined with the HDC 9226 and a few

resistors and capacitors, forms a phase locked loop which
performs phase and frequency locking onto either the MFM
or FM data stream output by ST506 or ST412 type drives.
By reducing the number of critical discrete components to
a minimum and eliminating all critical adjustments, the HDC
9223 and HDC 9226 simplify the task of the designer.

585

r-------

+12V

-------------,
1

I

l.

I

10

I
I
9

1.221'J

IIAGNOT

4

I

ft
.22
MLC

AGNO

PMPUP
PMPOWN

n

I

5
~~--i

I

_

4xVCO

I

__.-_~

I

_.-1

4990 5600 pi 5%
1%
MLC

AUNO

METAL FILM

FIGURE 1: HOC 9223 BLOCK DIAGRAM
DESCRIPTION OF PIN FUNCTIONS
PINNa.
1

NAME

SYMBOL

Read Gate

RDGATE

This active high input controls the gain of the loop. A high level
decreases the gain and a low level increases the gain.

DESCRIPTION

This active low input causes the VCO to increase its frequency.

2

Pump Up

PMPUP

3

Pump Down

PMPDWN

4

Digital Ground

GND

5

Four Times VCO

4xVCO

6

Extemal Capacitor
Connection 1

CX1

7

Extemal Capacitor
Connection 2

CX2

8

External
Resistor Connect

R1

A3.01K 1% resistor is connected from this pin to Analog Ground.

9

Extemal Filter
Cap Connection 1

C1

A .22fLf MLC capacitor is connected from this pin to Analog Ground.

10

Extemal Filter
Cap Connection 2

C2

A .22fLf MLC capacitor is connected from this pin to Analog Ground.

11

Analog Ground

AGND

12

External Filter
Connection 1

F1

A filter network should be connected to this pin as shown in Figure 4.

13 •

External Filter
Connection 2

F2

A filter network should be connected to this pin as shown in Figure 4.

12V

Connect the power supply to this pin. A .22fLf bypass capacitor should
also be connected from this pin to Analog Ground.

14

+12 Volts

This active low input causes the VCO to decrease its frequency.
This is the ground connection for the digital circuitry within the
HDC9223.
This is the VCO output. It will vary from 18 to 22 MHz as a function of
the PMPUP and PMPDWN input Signals.

An 8.2 pf extemal NPO capacitor is connected across pins 6 and 7.

This is the ground connection for the analog circuitry within the
HDC9223.

586

DESCRIPTION OF OPERATION
The functional block diagram of the HOC 9223 is shown in the disk is 100ns, the HOC 9226 divides the frequency of
Figure 1. The major functional blocks within the HOC 9223 the 4xVCO signal in half, and compares the phase and freare a voltage controlled oscillator (VCO) , an active loop fil- quency of the resulting 10 MHz signal to that of the incomter, and a pulse amplifier. The gain of the pulse amplifier is ing data. The HOC 9226 then varies the pulse width on the
PMPUP and PMPOWN lines to adjustthe outputfrequency
controlled by the ROGATE logic input.
The voltage controlled ocsillator generates the 4xVCO out- of the VCO on the HOC 9223, closing the loop.
put (nominally 20 MHz). The frequency of this output is A voltage regulator and bandgap voltage reference ensure
determined by the signals on the PMPUP and PMPOWN power supply rejection and stable VCO operation.
inputs to the HOC 9223. Since the half bit time for data from

MAXIMUM GUARANTEED RATINGS
Operating Temperature Range .................................................................................. 0 to 70 C
Storage Temperature Range ............................................................................ - 55 to + 150 C
Lead Temperature (soldering, 10 sec) . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . .. . . . . .. .. . . . . .. + 300 C
Positive Voltage on any Pin, with respect to Ground ......................................................... Vcc + 0.5V
Negative Voltage on any Pin, with respect to Ground ............................................................. - 0.5V
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or
any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the "Maximum Guaranteed Ratings" not be exceeded,
or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when AC power is switched off. In addition, voltage
transients on the AC power line may appear on the DC output. If this possibly exists it is suggested that a clamp circuit be used.

DC ELECTRICAL SPECIFICATIONS
(TA = DC to 7DC, Vee = 12.DV ± 5%)
SUPPLY CURRENT
Icc
SUPPLY VOLTAGE
V
INPUT VOLTAGE
V'L
V,H
OUTPUT VOLTAGE

60
11.4

mA

12.6

V

12V±5%

2.4
3.6
1.2
4.1

CURRENT
-10
40

AC ELECTRICAL CHARACTERISTICS
(TA = DCto7DC, Vee = 12.0V ± 5%)
PM PUP, PMPOWN pulse width
PMPUP, PMPOWN rise time
PMPUP PMPOWN fall time

15

125
10
10
22

ns
ns
ns
MHz

4xVCO rise time

15

ns

4xVCO fall time

15

ns

18

4xVCO pulse width high
4xVCO Ise width low

ns
ns

16
16
587

Measured at 50% amplitude
Measured between 0.6 and 1
Measured between 0.6 and 1

Measured between 1.5 and 3.0V;
Cload = 10pf (Fig. 3)
Measured between 1.5 and 3.0V;
Cload = 10pf (Fig. 3)
Fig. 3 Measured at 2.5V
3 Measured at 2.5V

=-=c-

FIGURE 2:

FIGURE 3: 4xVCO TIMING

PMPUP/PMPDWN TIMING

+12V

HDDS9226
RCLKI __~------~ RCLK
RDATA I - f - - - - - - - ! RDATA
EARLY
LATE
WDATA

1----------1
1----------1
1-------1

EARLY
LATE
WDATA

2XCLK I - f - - - - - - ! 10MHZOUT
10MHZlXTAL1
HDC
.9224
DMACLK I - f - - - - - - ! 5MHZOUT

1---------_1

HDC9223

DLY30
DLY40
NC

(NC)

NC

(NC)

XDL
DLY50

PMPDWN
4XVCO

WRGATE

RDIN

-I "RDGATE

WDOUT

RDGATEI-~f---__

_4.7V

+5V

PMPUP
XTAL2

WGATE

Vee

5%
B.2pf
NPO

12V
CX1

F1

CX2

-=-

GND

F2

RDGATE

R1

PMPUP

C2

PMPDWN
4XVCO

C1
AGND

GND

CONTROUSTATUS

FIGURE 4: TYPICAL CIRCUIT CONFIGURATION

Circu~ diagrams utilizing SMC products are included as a means of Illustrating typical semiconductor applications:
consequently complete information sufficient for construction purposes is not necessarily' given. The information
has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described
any license under the patent rights of SMC or others. SMC reserves the right to make changes at any time in order
to Improve design and supply the best product possible.

588

HDC9224

Universal Disk Controller
FEATURES

PIN CONFIGURATION

Programmable Disk Drive Interface
and Formats
Seagate (ST506) or user definable
Hard Disk Formats
I:'ct~~
IBM Compatible Single or Double
1llure adequate
tape mark is 257 bytes. The desired
spacing between tape blocks, a delay is frequently
rength is programmed into the secrequired before stopping tape motion. The UDC has a
tor count register.
programmable Ramp Up and Ramp ~own timer t~ allow
Multiple data block transfers are accomplished by profor easier implementation. The de~lred delaY.ls P,rogramming the 1's complement of the desired number of data
grammed into the DATA/DELAY register before Issuing
blocks to be transferred into the .sector count register.
the DRIVE SELECT "3" command.
The three lSB's of the MODE register function as part of
the BACK-UP command word. The WRITE ENABLE bit
DENSITY BIT
determines whether loading the BACK-UP command into
CLOCK
MODE
the UDC will initiate execution of a BACK-UP READ or
DIVISOR
REGISTER
TIME IN SECONDS PER
BACK-UP WRITE sequence. The TAPE MARK ENABLE
DELAY 'REGISTER COUNT
BIT4
BIT
bit determines whether the UDC will write a short or lorg
1 ClK Cycle * 80000
1
1 (Single)
block of data on the tape and the DELAY ENABLE bit detero (Double)
1 ClK Cycle * 40000
1
mines whether or not the RDGATE signal is stretched when
1 (Single)
1 ClK Cycle * 40000
0
it coincides with a sync mark when reading the tape. The
1 ClK Cycle * 20000
o (Double)
0
remaining bits in the,command word are as follows:
605

1

+5V

~

LOADD

STB
AB7

30an

ABS
ClK

ABS

XTAL 1

AB4
AB3

ADDR

---',
DECODE

RAMEN

AB2
AB1
ABO

HDCCS

~

I--

,

r
32Kx8

WE

WE

DE

DE

STATIC RAM

ADDR

D97-0

~tr

,p
ADDR
BUS

r-

~

B>

EN rj.

[9
LS245

"

"

~
DIR

V'-:- L.J.-..
-.

t--

DIP

AD14-0

SEN

Cs"---

BUS OrR

I

~clD

OB7-0

HDC

9225

~

LS244

A

-cs

lSOB

C/[j---

EN DIR

G>
~

/'-

['r

LS245

I--

[

R/VV
SYSR!W
WAIT
WAIT

DMAClK

RESET
liS
IlPCLK

SECTOR INTERRUPT ACK

-"

,

SYSDS

,

fJ.CLKrN

ECCTM

, iNTACK

SECTOR INTERRUPT

INT
SYS RESET

(

HOC INTERRUPT

606

HDCDS
HDCR!W

r--

AB7
AB6
ABS

lS

DRIVE STATUS

-

INDEX
SEEK COMPLETE

244

IDX

TRACK 000

AB4
AB3

~

AB2
AB1
AB0

f--

TRKOO

WRITE PROTECT

WRPROT

READY

DIR
STEP

WRITE FAULT

....

IT
,--

AB7

AB2

AB1
AB0

0
0
0

Q

0

Q

-

_

-

5RS'Eti

ORSElO

RDATA

-

r

LS04

ORSEl1

Q
LS374
0
Q

AB3

~

OUTPUT 1

0
0
0

ABS
ABS
AB4

WG

WDATA
MO
GNO
FLOPPY DISK
~

MOTOR ON

SINGLE DENSITY
lOX
SEEKCOMP

TRKODa
WRFLT

-=-

HOC 9224

,--

AS?
ABS
ABS
AB3
AB2
AB1

V"

8Th
GNO

U- -

E{

EC
EB
EA

C
S1
B
S0- A

WGATE
WDATA I "

rv

"

02
01
00

~

HEAD BIT 1
HEAD BIT 0

;-,.,

STEP
HEAD 2'
HEAD 2'
HEAD2

r-,..
.Y

...,.,

"

HEAD 2°

i.-"" r-,..

~rr

07P
Osp
OSp

lS13S04 P
03

~

HEAD BIT3

HEAD BIT 2

Q

lOW CUR
OIR

L.-'"
J't V

OIR
STEP

Q
Q

0
0
0

ABO

+SV

DASELl
RED WR CUR

Q
Q
LS374
Q
0
Q
0

AS4

READY

OUTPUT 2

0
0
0

V

r

740S

=

WG
GND
H=SK

STB3

8T82
STB1
STBO

'--

[....
+MFM

-f2

WRITE DATA
MFM

I-lA9638

A
LATE

1

EARLY
RDGATE
ClK

\Ii

I'

l100U
I-lA9637

HOC 9226

r-2Cl -

2C2

Ri5ATi\

2Y

RCLK

1Y

A

1C3
1C1
1CO
B

-

r-

Jf

XTAll

RDATA
XTAL2

INT

J

~

~'0MHZ
XTAL

RClK

r---

JROATA

RCLK
.".

DRSEl1

~

HO DATA
SEPARATOR
~

IFDC9216

~

I

I
8MHzCLK

607

+MFM

r':"

WDOUT

~r--

t

RAW
RO

CO~
CD1

=

READ DATA
MFM

GND
HA=SK

The UDC will issue a normal interrupt (with the command termination code set to a-a) when the RAMP UP
or RAMP DOWN timer has expired.
4. BACK-UP WRITE. The user will first request the UDC
to perform a disk READ TRACK command, with the
TRANSFER ENABLE bit in the command word reset.
This will cause the UDC to transfer only the 10 field
information to memory.
The TAPE BACKUP command will then be issued
causing the UDC to write this 10 information to the tape
as a tape mark (typically 96 bytes for a drive formatted
with a 3 byte/sector 10 field or 128 bytes for a drive formatted with a four byte/sector 10 field. The data fields
should then be transferred to the tape in a similar
manner.
The UDC may be used with either "Streaming" or "Start/
Stop:' type tape drives. This is illustrated by the following examples:
A. START/STOP TAPE DRIVE:
typically transfers 1f2 or 1 disk track at a time as illustrated by the following flow chart:

TAPESPEEO:
STOPPEO

/

DRIVE SEL

SL

1. tape motion on

2. write enable on

(write)o,off
(read)

WRITE BLOCK FROM MEMORY TO TAPE
STOP TAPE DRIVE
Control of a streaming tape drive is similar to that of a
start/stop drive. The tape is started at the beginning
of the data transfer and stopped after the last block is
written to the tape. The tape is not stopped in between
blocks. The UDC will however turn the Write Gate signal on when it is writing data and off when it is not so
that gaps will be written (with external hardware) on
the tape between the data blocks.

When controlling a start/stop tape drive, the UDC will
write the data "block by block". The system will issue
a Drive Select command to the UDC with the Tape
Motion, Motor On and Write Enable bits set to start
and write data to the tape.
The UDC will interrupt the system after the completion of the Ramp Up Delay indicating that the tape drive
is up to speed. This interrupt is distinguished by the
Command Termination Code of a-a (normal completion of command).
The System then outputs the Write command (for a
long or short block) and waits for the command termination interrupt. The UDC will write the Sync mark
and tape mark or data block on the tape.
When the System receives the interrupt indicating
completion ofthe Write command, itwill issue another
drive select command with the Motor On and Write
Enable bits set to stop the drive. The UDC will interrupt the system after completion of the Ramp Down
Delay indicating that the tape has stopped moving.
The UDC will turn the Write Gate signal on when it is
writing data and off when it is not, without regard to
the tape motion. The Write Gate signal is used to g~n­
erate "gaps" on the tape between the data blocks. This
is done by externally forcing the two Data outputs with
the Write Gate signal such that the Data + signal is
high and the Data - signal is low when the UDC is
not writing data to the tape (Write Gate is off):

5. BACK-UP READ. The data is read from the tape (in
either start/stop or streamer mode) and buffered in
memory. The disk track is then reconstructed from
the data.
The start/stop drive typically has a track (or half a track)
"Of disk data stored as a block. It is therefore expedient
to read in the data "block by block". When reading data
from a streamer drive use can be made of the SECTOR
COUNT register and a track's worth of data blocks may
be read from the tape before generating the track on
the disk.
Tape motion control is similar to that described above
except that the· Write Enable Bit is off to inhibit writing to
the tape. The UDC reads the tape until it detects a sync
mark. After detecting a sync mark the UDC will transfer
the data found on the tape to memory.
6. The search count is used when reading the tape. It
specifies a maximum number of blocks of 128 bytes
between adjacent data blocks. If the search count
expires before sync is detected, the command is
terminated.
For example, if a search count of two is specified by
loading the Desired Sector reQister with FD (hex), the
UDC will search for 256 byte times before terminating
the command. This will prevent the UDC from accidentally skipping a block. The search count is typically about
the size of one block length. In the following figure, TM1
and TM2 are two tape marks and DB1, DB2, DB3 etc.
are their associated Data Blocks:

(DRIVE STOPPED

1

GAP

1'--__

TMl

WRITE GATE:

LJ

2. write enable off
(write or read)

READ DATA FROM DISK TO MEMORY

STOP TAPE DRIVE

TAPE MARK ANDIOR DATA BLOCK

L

DRIVESEL
1. tape motion off

1. read or write

START TAPE DRIVE

WRITE BLOCK FROM MEMORY TO TAPE

1

BACKUP

STOPPED
RAMP DOWN DELAY

B. STREAMING TAPE DRIVE:
typically transfers 1 sector at a time as illustrated
by the following flow chart:

START TAPE DRIVE

[DRIVE STOPPED

\
-

2. long or short block

READ DATA FROM DISK TO MEMORY

GAP

TAPE AT SPEED
RAMP U'P DELAY

f----4

DBl
~

082

I----l

DB3

I----l
search count

608

DB4
~

TM2

I---l

DBl

I----l

ing of bytes of 00 as per figure 2 of the UDC spec (this
is required to synchronize the data separator when
reading the tape). The Tape Mark and Data Block
(including CRC or ECC bytes) are followed by a "postamble" consisting of one byte of 00.
Note that the postamble is not included in the Floppy
Disk formats. The GAP sizes are dependent on the type
of drive (start/stop or streamer) and the specific
mechanical tape drive specifications.

7. 16 BYTE DELAY. Provision is made to shift the RDGATE
pulse in the event that it coincides with the data block
sync mark. If a tape cannot be read (sync is never
detected) the tape can be re-read with the 16 byte delay
enabled.
DATA

GAP

Isync

DATA

GAP

RDGATE without delay:

RDGATE with delay:

8. The DRIVE STATUS bits may be used by the tape drive
if they are enabled (on the drive) by DRIVE SELECT 3.
The ready change interrupt is especially handy for
detecting start of tape (SOT) and end of tape (EOT) as
a UDC command can be terminated by a change in state
of the READY input.
9. The DATA FORMAT is as follows:

I

PRE- TMSYNC TAPE MARK POST GAP PRE DBSYNC DATA BLOCK POST GAP

The Tape Mark sync mark (TMSYNC) is composed of
three bytes of A 1 (Hex) followed by one byte of FE (Hex).
The Data Block sync mark (DBSYNC) is composed of
three bytes of A 1 (Hex) followed by one byte of FB (Hex).
A1 (Hex) is encoded with the standard missing clock
pattern.
The sync mark is preceeded by a "preamble" consist-

I

10. Use can be made of the Sector Count register when
doing a "file" (versus a "mirror image") backup on a
start/stop tape drive. Instead of transferring the entire
disk track to the tape in one long block, the data is moved
file by file.
If, for example, it is desired to back up a file COnSisting
of five 256 byte long Hard Disk sectors, a 2048 byte long
Data Block would have to be used for an image backup
(the Data Block size is specified as 2n * 128 restricting
blocks to 128, 256, 512 etc.). This would result in a lot
of wasted space on the tape.
If file backup is used and the Sector Count is set to five,
256' byte long Data Blocks can be used. Gaps will be
generated on the tape corresponding to the time
required to get the data from the disk drive (corresponding to DMA delays and the disk interleave factor).
The tape will not be stopped until the entire file is transferred. When using sector count, the UDC internal programming will create inter-block gaps of about 30 to 32
bytes on the tape in both single (FM) and double (MFM)
density modes.

SYSTEM CONFIGURATION NOTES
A simplified UDC schematic is shown in Schematic 1. The
following notes may be helpful in implementation ofthe UDC.

interface circuits (including floppy disk data inputs and
outputs) may be 74LS series devices.

1. In systems using a private memory area, it is important
to know when the buffer needs servicing from the host
processor. A second interrupt signal (INT2) signals the
processor that servicing is needed. INT2 is generated by
externall~ANDING the ECCTM signal with STB1 signal.
(The ST 1 signal is active when the UDC.J§..gutputing
the DMA address data, and occurs when STB is active
(low), SO is active (high) and S1 is inactive (low)).
This "interrupt" occurs only when the UDC needs the
system processor to either read from or write to the buffer
memory. When reading from the disk, the system processor should empty the memory buffer each time this
signal becomes active. (If an ECC error is detected, and
error correction is enabled, this signal will not become
active until the UDC has attempted to correct the error.)
When writing data to the disk, the system processor must
fill the buffer each time this signal becomes active.
2. The DIP (DMA in Progress) signal is used to isolate the
buffer memory from the main system memory. If 74LS244
and 74LS245 address buffers are used in the memory
addressing circuits, then this signal should be used to
enable or disable the address buffers, as required. This
eliminates the possibility of memory contention problems.
3. Write precompensation (for floppy disks) is handled
internally by the UDC. For hard disks, the LATE and
EARLY signals are connected to a multiplexer which, in
turn is connected to a 24 ns delay line. The EARLY and
LATE signals will toggle in response to the data pattern
being written. This will allow the data being written to the
shifted ± 12 ns from the nominal 12 ns delay specified
by hard disk manufacturers.
4. The interface to the hard disk drive data inputs and outputs requires RS-422 data tranceivers. Other disk drive

5. Since the UDC uses its Aux Bus for multiple functions,
the system designer must be able to determine which
function is occuring on the Aux Bus at any given time.
The SO and S1 Signals, when combined with STB Signal
are decoded (using a 74LS138 or equivalent) to provide
STBO-3 signals.
These generated signals and their respective functions
are:
STBO
STB1
STB2
STB3

Drive Status Input Time Slot
External DMA Address Counters Time Slot
Output 1 Time Slot
Output 2 Time Slot

6. The clocks required by the UDC are not TTL-level compatible. Pullup resistors (typically 390 ohms) should be
used with Schottky drivers to insure that the clock signals
reach the proper Input (high) level, with acceptable rise
and fall times.
7. The UDC features a built-in DMA controller that requires
connection to external counters. These counters are
configured so that they are incremented after each byte
is transferred. (The UDC's internal DMA circuits transfer
the starting memory address for each read or write operation.) 74LS161 Counters are typically used in this area.
8. The DMACLK input should be tied to the master system
clock, through a bus buffer. It is important to remember
that three DMACLK periods are required for each DMA
transfer.
9. The system design may be simplified, and costs reduced,
by using the FDC 9216B Floppy Disk Data Separator, to
separate raw data from the floppy disk drive into RDATA
and RCLK.
609

being checked. The longest data block that can be corrected (using the internal ECC algorithm) is 4K bytes.
2. The data input to the CRC/ECC registers is then disabled and the DMA counters are re-initialized to the
starting address for this data block. The contents of the
CRC/ECC registers are then "ring-shifted" until 21 consecutive zeros are detected. The remaining bits in the
CRC/ECC registers compose the error syndrome. As the
CRC/ECC registers are shifted, the UDC generates OS
signals, causing the external DMA counters to be incremented. When the 21 consecutive zeros are detected,
the DMA counters are pointing to the corrupt data.
If the error syndrome is not found within the data block
the error is judged to be uncorrectable and the correction
algorithm is terminated. (The data block is the length of
the data field in the sector and the 4 ECC bytes. A format
with a sector size of 256 bytes would have a data block
size of 260 bytes.)
3. When the error syndrome is detected, the UDC will enable its ECCTM output, read the next byte from memory,
exclusive-or it with the first byte of the three byte error
syndrome, disable the ECCTM output and write the corrected byte back to memory. The correction process is
then repeated for the next two bytes in memory.
When using internal ECC (with correction enabled), the
ECCTM output is used by the external DMA counters to
inhibit the counters from incrementing their addresses
when correctin~the erroneous bytes. When using external ECC, the E CTM output goes active (low) when the
UDC is requesting the ECC Check Bytes from the external ECC chip prior to writing them to the disk.
After a correction is completed, the UDC will then attempt
to read the next sector on the disk (if the SECTOR
COUNT register is still greater than zero). Anytime ECC
correction has been attempted, (even if unsuccessful),
the CORRECTION ATTEMPTED bit in the CHIP STATUS register will be set.
The maximum time required for one ECC Correction Cycle
(using the internal algorithm) is:
1) (Natural Message Length [BitsJ)+ 4 = ECC Cycle Time
8
(in Byte times)

ERROR CHECKING AND CORRECTION CIRCUIT (ECC)
OPERATING PRINCIPLES
The UDC will automatically detect and correct errors in the
data read from the disk. Error checking may be done using
industry standard CRC or ECC encoding. Error correction
may be done using either internal or external ECC encoding. This section will explain ECC operation, as implemented on the UDC.
The UDC contains two 16-bit registers used by the CRC/
ECC circuits. CRC logic uses only one of these registers,
while the logic for ECC uses both registers, implementing
a full 32-bit algorithm.
These registers may be preset to either one or zero, using
the CRC PRESET bit In the INTERRUPT/COMMAND
TERMINATION register. (This allows compatibility with
existing disk controllers and external ECC chips.) Both ECC
and CRC are calculated beginninfij with the sync mark of
the address (CRC) or data (ECC) field.
CRC/ECC GENERATION
The UDC uses the following industry standard polynomials
in computing the CRC and ECC check bytes:
CRC: X'6 +X'2 +X5 + 1
ECC: X32 +X23 +x 2' +x" +X2 + 1
As the UDC writes data to the disk drive, it first passes this
data thru the CRC (and, if enabled, ECC) registers. After all
data has been written, the remaining two (CRC) or four
(ECC) bytes remaining in these registers are written to the
appropriate address or data field.
CRC/ECC CHECKING
When CRC or ECC checking is initiated, the internal CRC/
ECC registers are set to either zero or one, as required by
the CRC PRESET bit in the INTERRUPT/COMMAND
TERMINATION REGISTER. Data read from the disk is
simultaneously shifted thru the CRC/ECC registers, and
transferred to external memory.
After the CRC or ECC check bytes have been shifted thru
the CRC/ECC registers, the remainder in these registers
should be zero, else an error has occurred in the address
or data block.
If CRC or ECC (without correction) is enabled, automatic
retry (if enabled) or command termination will occur. If internal ECC with automatic correction is enabled, the correction algorithm will be executed. If the internal ECC algorithm
is unable to correct the error (in one attempt), then automatic retry (if enabled) or command termination will occur.
ECC CORRECTION
Error Correction consists of three distinct parts:
1. The CRC/ECC registers are normalized by shifting zeros
thru the register. This sets up a data block which is 42,987
bits long, which corresponds to the "natural message
length" ofthe generation polynomial. The actual number
of zeros shifted through the registers depends on the difference between the natural message length of the generator polynomial and the actual length of the data block

2) Maximum ECC Time = ECC Cycle Time + 30 byte times
Since the internal algorithm has a natural message length
of 42,987 bits the ECC Cycle time is 5,377 byte times. Since
a period of about 30 byte times must be allowed for the readmodify-write operations, the Maximum ECC Time equals
5,407 byte times.
One byte time equals the amount of time required to read
one byte for the type of drive selected. For Hard Disks, this
is about 1 microsecond. This equates to approximately 1
revolution (maximum) for either 8" floppy disk (running in
double density) or 5.25" hard disk.
During the entire operation, the RDGATE signal is kept
active.

610

MAXIMUM GUARANTEED RATINGS'

Operating Temperature Range ............................................................................. 0 to + 70 C
Storage Temperature Range ....................................................................... - 55 C to + 150 C
Lead Temperature (soldering, 10 sec.) ........................................................................ +325 C
Positive Voltage on any Pin, with respect to ground .............................................................. + 8 V
Negative Voltage on any Pin, with respect to ground ........................................................... - 0.3 V
'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches"
on their outputs when the AC power is switched oft. In addition, voltage transients on the AC power line may appear
on the DC output. If this possibility exists it is suggested that a clamp circuit be used.

DC ELECTRICAL CHARACTERISTICS Ta = 0 C to + 70 C, Vcc = 5.0V ± 5%

VOL1
VO:H1

PARAMETER
Input Voltage
Low
High
High
Output Voltage
Low
High

VOL2
VOH2

Low
High

V,L
V,H1
V,H2

VOL3
VOH3
IL
ILc

MIN

Low
High
Input Leakage Current

TYP

UNIT

0.8

V
V
V

all inputs except CLK and DMACLK
CLK and DMACLK input

0.4

V
V

all outputs except WDATA,
Early and Late. (Drive 1
TTL load into 50 pf)

10L1 = 1.6 mA

WDATA, EARLY and LATE
outputs. (Will drive 1
Schottky load into 15 pt.)
DMARand INT
DMARand INT
0.4Vt03.5V

10L2 = 2mA

2.0
4.2
2.4
0.5

V
V

0.4

V
V

±10
-600

uA
JLA

25

pf

200

ma

2.7
2.4

(Clock)
Input Capacitance

C'N

COMMENTS

MAX

IOH1 = 40JLA

IOH2 = 50JLA
IOL3 = 0.4 mA
IOH3 = 20JLA

OV

Power Supply Current
Icc

AC ELECTRICAL CHARACTERISTICS Ta = 0 C to + 70 C , Vcc = 5 OV -+ 5%

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

COMMENTS

PROCESSOR WRITE CYCLE
C/Q, R/~, CS Setup time to DSl
CID, R/W, CS Hold time to DSi
DS Pulse Width
DS Pulse High Time
_
Data Bus In Setup time to DSi
Data Bus In Hold time to DSi

Toss
Toss
TosL
TosH
Tois
TOIA

110
0
150
850
100
0

ns
ns
ns
ns
ns
ns

FIGURE3

PROCESSOR READ CYCLE
Data Access time from DSl
Data Hold time from DSi

Toos
TooA

75
10

ns
ns

FIGURE3

UDC TO MEMORY TIMING
(BUS MASTER)
(based on 10 Mhz DMACLK Input)
Write Setup time to DS~
Write Data Strobe Widt
Write Hold time from DSi
Data Strobe Falling Edge
Data Strobe Rising EdglL
Write Data Valid before DS&
Write Data Hold time after Si
Memory Access Time

Tws
Twos
TWA
TosF
TosR
Twos
TwoA
Tw

110
180
110

ns
ns
ns
ns
ns
ns
ns
ns

FIGURE4

15
20
90
10
200
611

PARAMETER

SYMBOL

Read Setup time to D~
Read Hold time after D
Read Data Strobe Pulse idth
Read Data Setup time to D~
Read Data Hold time from D i
DMACLKf to DS
DMACLK to DSj

tv

1

TAB
TAA
TAos
T AoB
T AoA

MIN

TYP

MAX

UNIT

FIGURE4

100
100

ns
ns
ns
ns
ns
ns
ns

FIGURE7

100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

FIGURE2

FIGURE9

110
110
180
50
0

TO~~

TooA

COMMENTS

SO, S1, AND STB TIMING
STBWidth
SO, S1 Hold time after STBi
Data In Setup time to Sm
Data In Hold time after ST i
SO, S1 Setup time to
Aux Bus Setup time to S~
Aux Bus Hold time after ST i

Tsw
Tso
T o1s
TOIH
Tssn
TssT2
T ssT3

INPUT CLOCK TIMING (10 MHz Input)
Clock Rise Time
Clock Fall Time
Clock Cycle High Time
Clock Cycle Low Time
Clock Cycle Time

TAT
TAF
TCH
TCL
Tcyc

40
40
95

TpB

0

ns

TpB

50

ns

FLOPPY INPUT DATA TIMING
Window Setup time to RDCLK
Window Hold time from RDDATA i

TFAB
TFRA

50
50

ns
ns

FIGURE 10

HARD DISK INPUT DATA TIMING
Data Setup time to RCLKl
Data Hold time after RCLKl
Clock Setup time to RCLKj
Clock Hold time from RCLKi

THAB
THAA
T HcB
T HcA

60
10
60
10

ns
ns
ns
ns

FIGURE 10

ECCTIM TIMING
ECCTM Setup to D~
ECCTM Hold after D i

TEos
T EoH

50
100

ns

1

fLs

sm

PRECOMPENSATION TIMING
Early, Late Setup time
(Before WDATAj)
Early, Late Hold Time
(after WDATA1)

800
100
700
0
100
100

10
10

RESET TIMING
RST Pulse Width

612

100

105

FIGURE 10

AB0-7 C=~:1
DISK DRIVE
STATUS

'REQUIRED
FOR STANDARD
UDC/HARD DISK
INTERFACE

TAPE DRIVE
STATUS

OUTPUT 2
D

} TAPE MOTION CTL

LS3741-_~-1I-_f-:"=':'::"''::'''''_--1
4

WRITE ENABLE
TRACK #

STB2 ---411---I-----"""'--"""'--.cI
STB3
STB0

WGATE------------~

DATA +
WD --------~
DATA -

SCHEMATIC 2: UDC/TAPE DRIVE INTERFACE CIRCUIT

613

~

+5V

390n

_ _ _ _ _"'--......_ _.....J.._ _ _ _ TO ClK INPUT

\./"

or DMAClK
INPUT

74504

ClK

or
equivalent

T"

RECOMMENDED ClK DRIVER CIRCUIT

FIGURE 2: INPUT CLOCK TIMING (10MHz)

FIGURE 1: RECOMMENDED CLK/DMACLK INPUT

\'-----/
RIW

CID

T'":~T-'''_T""--T,o,~H
DB7-0

PROCESSOR WRITE CYCLE

PROCESSOR READ CYCLE

FIGURE 3: SYSTEM PROCESSOR TO UDC TIMING

--Tw---I'I

11+-.

RIW

T"=i

r--

~-I--+r-~_T~"-

-

~~T-w,- - - - - T - - 1 w J

--------;

~----------

DB7-0

(WRITES)

DB7-0

(READS)

FIGURE 4: UDC TO MEMORY TIMING (BUS MASTER)

614

DMACLK

,

DMAR

I

I

<

ACK

"

I

\

...... , ,

~--------------~--~~----4\~------------~--~~lr;------~)~

----1

I

I
\

I

I

/

\

"--

\

I

\

I
I

DIP

I
I

/
I

I
BYTE
READY

I

I
\
II.

BYTE

I

I ,

R/W

TRISTATE I

"

I
\
\

I

\

Os

TRISTATE

~..:.TR:.::I:.::ST.:.:A.:.::r=E_ __

I

\

\

TRISTATE

I

DB 7·0

------------~(~

r--

_ _ _D_AT_A_O_U_T_ _

MAX BYTE RATE 1.61'-8

---I

~~
UDC DMA MEMORY TIMING FOR HARD DISK
(BURST MODE)

FIGURE 5: UDC DMA MEMORY TIMING FOR HARD DISK (BURST MODE)

DMACLK
I

)

BYTE READY
DMAR
ACK
R/W

-------~I,~\
TRISTATE

I~
I

"

\

TRISTATE

DIP
DB7·0
(OUT)

~

I
\

I

,
I

~

,
I
I

' ...... \

...

I

I
\

\

\

J
I

101

I

,I

:\....--..,l~

)

y

it

~~
TRISTATE
TRISTATE

\

\

I

-----_----1).~

\

\

Q

----------------~(~------~--~
DATAOUT I
I

~

I

DB7·0
(IN)

\)

(

t

DATA IN

>-tJDC DMA TIMING FOR
FLOPPY DISK (1 BYTE AT A TIME)

FIGURE 6: UDC DMA TIMING FOR FLOPPY DISK (1 BYTE AT A TIME)

615

51,50

AB 7-0

FIGURE 7: 50, 51, 5TB TIMING

BIT

I

7

I I I
6

5

I I I IoI I I I I I I IoI
3

4

2

1

7

6

5

4

2

3

1

CLK

WDATA

Tn
0

I-

0
I

o

0

ADDRESS MARK

MISSING CLOCK
0
1

1

-I-

0
DATA "FE"

FIGURE 8: UDC DATA WRITE TIMING

TWA

-

WDATA

1\
I+- TpB

f--TPA-

><

>~

EARLY,
LATE

T
DRIVE TYPE

T(typ)
200NS

TWA (typ)
100NS

8" MFM FLOPPY
8"FMFLOPPY

21'-8

300NS

5W' MFM FLOPPY

41'-8

HARD DISK

5W' FM FLOPPY

-

300NS
300NS
300NS

FIGURE 9: PRECOMPEN5ATION TIMING

616

~I

DATA
BIT

1

a 1

I-

a 1 a 1 a 1 a 1

1

1

1

.. I

ADDRESS MARK

1

I I

1

1

1 1 1

a

I

a 1

1

I

MFM
READ DATA

READ CLOCK

RDATA

DS
INTERNAL
COMPARE

a
AI, 0A COMPARE

ECCTM

Te""

I LSYNCBYTE

RCLK

HARD DISK INPUT DATA TIMING
(HARD DISK BIT=1)

FLOPPY INPUT DATA TIMING
(HARD DISK BIT = 0)
FIGURE 10

INDEX

---------REPEATED N TIMES - - - - - - - - -..·.;1
rL
J1~______~r·..____
~------__----~~------~------~~----------~

12t:e~ I ~~ H~t"ell ~~ I~TKI ~ I ~ I~ I~ IgI~f':e~ I~~~gl ~; I
~INDEXAM
L
lOAM

1

128 da1a byla, ICAC1 CAC2

~~.~f I~tr.;F NOMINAL

I

DATA AM

-

FLOPPY DISK FORMAT; SINGLE DENSITY

ECCTM
2 bytes

INDE~~__________~I_··_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-:_R_E_P_E_AT_E_D_N__TI_M_E_S======================:'~I______~nL
80x4E 12xOO 3XC2 IIGAPllSYNCI
Fe 50x4E 12xOO
I GAPOISYNCI

LINDEXAM

3xAI

III
FE

II

I

I

TK SIDE SEC SIZE CRGI CRC2

22x4E2 I SYNC
12xOQ I 3xAl IF81
~~
I GAP

LIDAM

258 data bytes

ICRc'ICRc21~~gl

~~~4~ I

~ECCTM

LOATAAM

---1 t-

FLOPPY DISK FORMAT; DOUBLE DENSITY

2 bytes

r..·------------

"" n1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
REPEATED N TIMES _ _ _ _ _ _ _ _ _ _ _ _-!.1
_ _ _ _ _ _ _ _ _ _ _ _ _.......JrL

IND~

GAP 1
16X4E

GAP 4

512 data bytes

340x4E

~ECCTM
HARD DISK FORMAT

FIGURE 11: DISK FORMATS

617

---1

r-

2 bytes

I

11

INDEX

I

10

I IG31

(2) SYNC

DATA

:

I

SYNC

110

5 BYTES

I 1 I
02

SYNC

DATA

j+..I

100) SYNC I10) G21 SYNC I DATA I 03 ISYNC) 101 G8fSYNCJOATAf 001 G41
I 256 bytes I
j--~-----,

DG

RDGATE

3
AM AM FOUND

LOOKING FOR'

I

..... 16 Bytes

I

I

I

t
+
t
+ +
+_ F B - - + F E - - - - + + - - - - - - - - + - F B - - - - + - F E - - I - FB-+-FE _ __
AM FOUND

AM NOT FOUND

AM FOUND

AM NOT FOUND

AM FOUND

AM FOUND

(SINGLE DENSITYI _ _ _ FE _ _
(DOUBLEDENSITY) _ _ A1FE
(HARD DISK)

A1FB--I--A1FE _ _ _ _ _ _ _ _ _ _ _--II-A'FB _ _ _+A1FE-+A1FB-I-A1FE _ _

A1FE-------------t_

- - A1FE--t--A1FS--t-

+- A1FE--+ A1F8+ A1FE _ _

A1F8 _ _ _

.:~Jr~rf~~~~9:!!':~ity

FIGURE 12A: RDGATE DURING DISK READ

INDEX

~~

IGO

________________________________________

1SYNCII"..P~xIG,lsYNcl'DIG21 SYNC I DATAIG3ISYNCllofG~SYNCIDATAIG3ISYNCI'D 1021 SYNC I

-------..I1fl:.....t
:

ADGATE

RDG3

1

______
W_AG_2;..1....

DATA IG31 SYNC I 10 I G21 SYNC I DATAl G31

i r:u::-,-·y-,..-----.II
1.-""":"'16 Bytes

.....}4-

AM FOUND

WRGATE

~

WDG,]

~

AM NOT FOUND

t

II

AM FOUND

~

I
r-----,L-

AM FOUND

I

FIGURE 12B: RDGATE AND WRITE GATE TIMING

STANDARD FORMAT PARAMETERS
HARD DISK***

SINGLE DEN. FLOPPY

DOUBLE DEN. FLOPPY

GAP0*

16

40

80

GAP 1 *

16

26

50

GAP2*

3

11

22

GAP3*

18**

27

54

SYNCSIZE*

13

6

12

SECTOR COUNT *

user selectable

user selectable

user selectable

SECT. SIZE MULT *

user selectable

user selectable

user selectable

RDG 1

16

73

NA

RDG2

6

13

24

RDG3

25

27

24

WDG2

5

11

23

3

11

3

PARAMETER

WDG3
*
**
***

= PARAMETER USED BY FORMAT COMMAND
= GAP 3 VARIES WITH SECTOR SIZE
= ALL VALUES APPLY TO 512 BYTES/SECTOR

TABLE 1: STANDARD FORMAT PARAMETERS

618

G4

~rL

I

REGISTER BIT DEFINITIONS
7

6

4

5

2

3

0

DMA 7-0
(REGISTER 0)

(MSB)

LOW ORDER BYTE OF DMA BUFFER
MEMORY STARTING ADDRESS

(LSB)

DMA 15-8
(REGISTER 1)

(MSB)

MIDDLE ORDER BYTE OF DMA BUFFER
MEMORY STARTING ADDRESS

(LSB)

DMA23-16
(REGISTER 2)

(MSB)

HIGH ORDER BYTE OF DMA BUFFER
MEMORY STARTING ADDRESS

(LSB)

DESIRED SECTOR
(REGISTER 3)

(MSB)

DESIRED SECTOR NUMBER

(LSB)

DESIRED HEAD
(REGISTER 4)

HIGH ORDER BITS OF
DESIRED CYLINDER

DESIRED HEAD NUMBER

(MSB)

(LSB)

(MSB)

DESIRED CYLINDER
(REGISTER 5)

(MSB)

LOW ORDER BITS OF DESIRED CYLINDER

(LSB)

SECTOR COUNT
(REGISTER 6)

(MSB)

NUMBER OF SECTORS TO BE OPERATED ON BY COMMAND

(LSB)

RETRY COUNT
(REGISTER 7)

RETRY COUNT (1'S COMPLEMENT)

MODE
(REGISTER 8)

INTERRUPTI
COMMAND TERM,
(REGISTER 9)

CRC PRESET
1 ~Setto 1

DATAIDELAY
(REGISTER A)

(MSB)

CURRENT HEAD
(READ REGISTER 4)

0~Setto0

CRCIECC

ENABLE

ALWAYS
0

INTERRUPT
ON
DONE

I

PROGRAMMABLE OUTPUTS

FLAG
DELETED
DATA
MARK

I

USER
DEFINED
FLAG

I

STEP

RATE

SELECT

FLAG
WRITE
PROTECT

FLAG
READY
CHANGE

FLAG
WRITE
FAULT

I

HEAD LOAD DELAY MULTIPLE IS LOADED INTO THIS REGISTER
DATA IS LOADED TO OR READ FROM THIS REGISTER

I

(LSB)

CURRENT HEAD NUMBER

HIGH ORDER BITS OF
CURRENT CYLINDER
(MSB)

(LSB)

CURRENT CYLINDER
LOW ORDER BITS OF CURRENT CYLINDER NUMBER
(LSB)
(READREGISTER5)L-__________________________________________________________________________~

CHIP STATUS
(READ REGISTER 8)

DRIVE STATUS
(READ REGISTER 9)

INTERRUPT
STATUS
(COMMAND READ)

COMMAND TERMINATION
CODE

TABLE 2: REGISTER BIT MAPS

619

UDC WRITE REGISTERS (APPLIES DURING TAPE BACKUP ONLy)
REGISTER

DB7

DMA7-D
(REGISTER 0)

(MSB)

DMA BEGINNING ADDRESS BUTE (LOW ORDER BITS)

(LSB)

DMA 15-8
(REGISTER 1)

(MSB)

DMA BEGINNING ADDRESS BYTE (MIDDLE ORDER BITS)

(LSB)

DMA23-16
(REGISTER 2)

(MSB)

DMA BEGINNING ADDRESS BYTE (HIGH ORDER BITS)

(LSB)

DESIRED
SECTOR
(REGISTER 3)

(MSB)

MAXIMUM SEARCH COUNT (IN I'S COMPLEMENT) (1)

(LSB)

DB6

DB5

DB4

DB3

DB2

DBI

DBO

DESIRED
HEAD
(REGISTER 4)
DESIRED
CYLINDER
(REGISTER 5)

SECTOR COUNT
(REGISTER 6)

ALWAYS
1

ECCTYPE

TAPE MARK BLOCK SIZE
(IN 2'S COMPLEMENT + 1)
(MODULO 256) (2)

OR

RETRY COUNT
(REGISTER 7)

DATA BLOCK SIZE

DATA BLOCK COUNT
(IN I'S COMPLEMENT)
(3)

USER DEFINED OUTPUTS

MODE
(REGISTER 8)

INTERRUPTI
COMMAND
TERMINATOR
(REGISTER 9)

FLAG
WRITE
FAULT
NOTES: (1) The maximum search count is composed of:
130 byte inner loop (RDGATE high 128, 2 byte times)
times the number programmed (maximum of 33,150 byte times
(2) Tape mark operation
(3) Data block operation

TABLE 3: TAPE BACKUP REGISTER BIT MAPS

620

UDC READ REGISTERS (APPLIES TAPE BACKUP ONLy)
REGISTER

DB?

DMA?-D
(REGISTER 0)

(MSB)

DMA BEGINNING ADDRESS BYTE (LOW ORDER BITS)

(LSB)

DMA 15-8
(REGISTER 1)

(MSB)

DMA BEGINNING ADDRESS BYTE (MIDDLE ORDER BITS)

(LSB)

DMA23-16
(REGISTER 2)

(MSB)

DMA BEGINNING ADDRESS BYTE (HIGH ORDER BITS)

(LSB)

DESIRED
SECTOR
(REGISTER 3)

(MSB)

MAXIMUM SEARCH COUNT (IN 1'S COMPLEMENT)

CURRENT
HEAD
(REGISTER 4)

X

X

X

X

X

X

X

X

CURRENT
CYLINDER
(REGISTER 5)

X

X

X

X

X

X

X

X

DB6

DB5

DB4

DB3

DB2

DBI

DBO

(LSB)

CHIP
STATUS
(REGISTER 8)

PRESENT
DRIVE
SELECTED

DRIVE
STATUS
(REGISTER 9)
DATA
(REGISTER A)

READ DATA

INTERRUPT
STATUS
(COMMAND READ)

COMMAND
TERMINATION
CODE (1)

NOTES: (1) Command termination bits set to:
11 for data transfer error
10 for syne error
00 for successful termination
X Don'teare

TABLE 4: TAPE BACKUP REGISTER BIT MAPS

621

COMMAND BIT DEFINITIONS

7

6

5

4

3

2

RESET

o

o

o

o

o

o

o

DESELECT
DRIVES

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

SELECT
DRIVE

0

0

1

1 = Head Load
Delay Enabled
0= Delay
Disabled

SET REGISTER
POINTER

o

o

o

READ SECTORS
PHYSICAL

o

o

o

READ
TRACK

o

o

o

RESTORE
DRIVE

STEP IN
1 CYLINDER

STEP OUT
1 CYLINDER

o
o

1

=

Buffered
Seek

I

o = Seek
Norma~

1 = Buffered
Seek
0= Normal
Seek

o

1 = Buffered
Seek
0= Normal
Seek

I
I

POLL
DRIVES

I
TYPE OF DRIVE

1

DRIVE UNIT SELECTED

NUMBER

REGISTER

SEEK/READ ID

READ SECTORS
LOGICAL
0

1

0

1

1

FORMAT
TRACK

1

Enable
Transfer

o

11o == Transfer
Alii
Transfer ID
1 = Bad Sector
Bypass
0= Bad
Sector
Terminate

PRECOMPENSATION
VALUE

WRITE SECTORS
PHYSICAL

PRECOMPENSATION
VALUE

WRITE SECTORS
LOGICAL
1

1 = Bad
Sector
Bypass
0= Bad
Sector
Terminate

1

Write
Deleted
Data

Write With
Reduced
Current

TAPE
BACKUP

TABLE 5: COMMAND WORD BIT MAPS

622

PRECOMPENSATION
VALUE

Enable
Transfer

SECTOR SIZE FIELD BITS
DB2 DB1 DBO
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

IBM FD FORMAT

0 128 bytes/sector
1 256 bytes/sector
0 512 bytes/sector
1 1024 bytes/sector
0 not used
1 not used
0 not used
1 not used

HD FORMAT
128 bytes/sector
256 bytes/sector
512 bytes/sector
1024 bytes/sector
2048 bytes/sector
4096 bytes/sector
8192 bytes/sector
16,384 bytes/sector

FORMAT ECC TYPE FIELD
DB? DB6 DB5 DB4

o
1
1
1
note

0
1
1
1
1: WITH

HD FORMAT

0
0 4 ECC bytes generated/checked
1
1 5 ECC bytes generated/checked (1)
1
0 6 ECC bytes generated/checked (1)
0
1? ECC bytes generated/checked (1)
EXTERNAL ECC

IBM FLOPPY DISK FORMAT:
ID,FIELD
CYLINDER
HEAD
SECTOR
SECTOR SIZE

DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
track number
side number
sector number
sector size
(2 bits)

HARD DISK FORMAT: ST506 PC FORMAT (512 BYTES)
ID FIELD

DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO

CYLINDER
HEAD

~d~#~#~#~#~#~#~#

SECTOR

cylinder number (8 LSB's)
sector bit 10 bit 9 bit 8 bit 3 bit 2 bit 1 bit 0
flag
sector number

HARD DISK FORMAT: (USER SELECTABLE SECTOR SIZE)
ID FIELD
CYLINDER
HEAD
SECTOR
SECTOR SIZE

DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
cylinder number (8 LSB's)
bad cyl #cyl #cyl #hd #hd #hd #hd #
sectorbit10bit9 bit 8 bit 3 bit2 bit 1 bitO
flag
sector number
ECC type
X
sector size
(3 bits)

DISK FORMATS
TABLE 6

623

For additional information, please consult the
following:
Technical Note 6-2 (9224 Overview)
Technical Note 6-5 (Programmer's Reference
Manual)
HDC 9225 Data Sheet
HDC 9226 Data Sheet
HDC 9224 Programmer's Quick Reference Card

STANDARD MI~MS

rPORIliTlONI

35 MlrQJSiIYd ,t\auppIIuge:.NY 11788

\516j27H100 l'NX·51O·22H8911

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has be~n carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore. such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

624

HDC9225

DISK BUFFER MANAGEMENT UNIT
"DBMU"
PIN CONFIGURATION

FEATURES

o Significantly reduces chip count in hard disc systems
o Completely compatible with the HOC 9224 Universal

o
o
o
o
o

XTAL1
~,
XTAL2
CLOCKOUT
ECCTM
INT
ABO
INTACK
AB1
RESET
AB2
LDADD
AB3
SEN
ADO
WAIT
AD1
J!:QLKIN
AD2
OE
AD3
WE
ADS
SYSR/W
ADS
DIP
AD10
HDCDS
AD11
HDCCS
AD4
HDCR/W
ADS
BUSDIR
ADS
RAMEN
AD7
SYSDS
AB4
STB
ABS
DMACLK
ABS
AD12
AB7
AD13
GND '--"-_ _-'--r- AD14
48 Pin DIP Package

Disk Controller
Creates a dual-port disk buffer (up to 32K in size) using
low cost static ram
Programmable sector interrupt counter allows host processor rapid access to data
On board 10 MHz oscillator simplifies clock generation
Allows disk interleave factor of 1, improving system
performance
Fabricated in low power CMOS; fully TTL compatible
LDADLl---.....-------,

!!CCTM---+-..---===-----,

r-----

RESET

1----iWCK

I----'NT

r----v

AD14·0

AB7-0-----,-..,-v'

=---++-+1r--+-.,-::::-l----SEN
t----eusDIR
DIP ----1r+-+-+-1I---+-l

GENERAL DESCRIPTION
The HOC 9225 Disk Buffer Management Unit (DBMU) is a
48 pin CMOS/LSI device which, when used with the HOC
9224 Universal Disk Controller, significantly reduces the total
number of chips required to build a hard and floppy disk
controller.

RllClm _--1_..-+1

HDCR W----1t-+~<

I-----+-f+---+--

The DBMU allows low cost static rams to be used in a dualported configuration. This allows both the system processor and the HOC 9224 Universal Disk Controller to share a
common disk buffer local memory area, while eliminating
system memory contention problems. This feature greatly
improves overall system performance, while simplifying
design.

.----+--IJ..PClKN

WAIT

DMACLK

'CLOCK OUT

----OXZDa..a..

DLY40
DLY30
Vee
NC
RCLK
RDATA
EARLY

25242322212019
18
26
27
16
15
14
2
13
3
12
4
5 6 7 8 9 1011

4XVCO
RDIN
WDOUT
NC
GND
RDGATE
WRGATE

w

oo

;:

HOC 92C26
BLOCK DIAGRAM

HODS 92C26
RCLK

RCLK
RDATA

RDATA
EARLY

EARLY

LATE

LATE

WDATA

WDATA

10MHZOUT

CLK

HOC
9224

¢V~ ~f..l..
~

¢v~

'"

10MHZ/XTAL 1

'"
0

:J


...

-')
...
~

TYPICAL CIRCUIT CONFIGURATION

628

DESCRIPTION OF PIN FUNCTIONS
PIN. NO.
1
2
3
4
5

6
7,8

9
10

11

12
13
14

15

16
17
18

19

20,21
22
23
24

DESCRIPTION
Read clock output with nominal frequency of 5 MHz which defines the
half bit boundaries of the RDATA output.
This output is the regenerated raw read data from the drive. This signal
Read Data
RDATA
conforms to all timing requirements of the UDC.
EARLY
This input is connected to the HDC 9224, and causes the HDDS to send
Early
out the write data early.
LATE
This input is connected to the HDC 9224, and causes the HDDS to send
Late
out the write data late.
Write Data
WDATA
This input is connected to the HDC 9224, and is the MFM encoded write
data signal. This signal is passed through the HDDS and is delayed
according to the write precompensation inputs EARLY and LATE.
10 Mhz Out 10MHZOUT This output is normally connected to the CLK input on the HDC 9224.
Crystal 1 ,2
XTAL 1,2
A 10 Mhz crystal may be connected between these two inputs. If a TTL
signal is used in place of a crystal, the TTL signal (with pullup) should be
connected to the XTAL 1 and the XTAL 2 input should be left open.
5MHZOUT This output is normally tied to the HDC 9224 DMACLK pin in systems that
5 Mhz Out
do not use the HDC 9225 Disk Buffer Management Unit.
Write Gate
WRGATE This input is connected to the WRGATE output of the HDC 9224. When low
the RDIN input is selected and is outputto the delay line via the XDL pin.
When in write mode (WRGATE active), the WDATA input is selected and
output to the delay line via the XDL pin for precompensation.
Read Gate
RDGATE
This input signal, when active, allows the external VCO to begin locking
on the incoming data from the drive. When this Signal is inactive, the VCO
will lock on to the 5 MHz output signal.
Ground
GND
This is the ground pin for the device
Write Data
WDOUT
This output is the precompensated version of the WDATA input. This outOut
put is normally connected to the write data signal of the hard disk drive.
RDIN
Read Data
This input is normally connected to the Disk Data output of the drive. The
In
leading edge of this input arms the internal phase comparator, and then
also asserts the PMPUP output 50 ns later.
4TimesVCO
4XVCO
This input is connected to the external VCO and runs at a frequency of 4
times the data rate with RDGATE asserted. This signal is inte~
divided by 2 and feeds the phase comparator to generate the PMPDN
signal. 4XVCO is also divided by four and output as the RCLK signal.
Pump Down
PMPDN
When active (low) this output will decrease the frequency of the VCO.
Pump Up
PMPUP
When active (low) this output will increase the frequency of the VCO.
Delay 50 ns
DLY50
This is the 50 ns delay of the XDL signal. The 50 ns tap is used to arm the
phase detector and create a reclocked version of the raw read data from
the drive.
Excite
XDL
During write operations, when WRGATE is active, this output is identical
Delay
to WDATA, and is output to the delay line, creating precise delays which
Line
are used to perform write precompensation.
When WRGATE is inactive, this output is the image of the raw read data
the RDIN input. XDL is output to the delay line and is used to provide
proper arming,for the phase comparator and clocking for the data
recovery circuitry.
No Connect
NC
No connection should be made to these pins.
Delay 40
DLY40
These inputs are delays of 30 and 40 ns of the XDL signal, and come
from the external delay line. These signals are used for the nominal, late
Delay 30
DLY30
and early positioning of the databits in the WDOUT data stream.
+ 5V supply connected to this pin.
Vee
Vee
NAME
Read Clock

SYMBOL
RCLK

629

DESCRIPTION OF OPERATION
DATA SEPARATION
The HOC 92C26, in conjunction with a.n external VCO,
tapped delay line and filter, allows the system designer to
implement a high performance phase locked loop circuit to
perform phase and frequency locking onto either an MFM
or FM encoded data stream (from an ST-506 style disk
drive.)
In most applications, the data on the hard disk is recorded
in double density (MFM). In MFM mode, an input pulse on
ROIN indicates not a 1 or 0 but rather a flux transition on the
media and (by definition) these flux transitions may be
spaced at T, 1.5T or 2T time intervals, where T equals the
inverse of the bit data rate. For the standard ST-506 drive,
these time intervals are 200 ns, 300 ns, and 400 ns.
Due to the nature of magnetic storage phenomena, the bit
spacing found on the hard disk is not constant, but instead
will modulate due to magnetic effects and drive rotational
speed variations. The HOC 92C26 compensates for these
shifts in the ROIN signal coming from the drive and
regenerates ROATA and RCLK.
The RCLK signal is derived from the VCO which changes
its period as a function of the variations in the raw disk data
and permits the data from the drive to be correctly clocked
into the HOC 9224 Universal Disk Controller, independent
of the bit spacing variations found in the raw data coming
from the drive.
The VCO normally runs at 20 Mhz. Since the half bit time
(for data from the disk) is 100 ns, the HOC 92C26 divides

the 4XVCO signal in half and compares the phase and
frequency of the VCO with the incoming data. The read data
Signal is regenerated by the HOC 9266 and is placed
correctly within the RCLK window so as to satisfy the input
timing requirements of the HOC 9224 Universal Disk
Controller.

630

WRITE PRECOMPENSATION GENERATOR
The HOC 92C26 also performs write precompensation
which is needed because of tendency of written data to "realign" itself on the magnetic media.

Certain bit patterns, when written, and later read back, will
cause a phenomena known as "peak" or "bit" shift. Since
this shifting is predictable, it is common when writing to
magnetic media to intentionally pre-shift when these bits
are to be written. This intentional "pre-shifting" minimizes
the amount of shifting which occurs when the data is read
back, and facilitates proper data recovery.
The HOC 9224 recognizes those patterns which require
"pre-shifting" or precompensation, and outputs EARLY and
LATE signals to alert the HOC 92C26 to the need for
precompensation.
Typical ST-506 applications may require "pre-shifting" the
data bits by approximately 10 ns (either early or late). Three
taps of the delay line (OLY30, OLY40, OLY50) are normally
used to implement precompensation. The HOC 92C26 then
outputs the precompensated data via the WOOUT pin.

MAXIMUM GUARANTEED RATINGS

Operating Temperature Range .................................................................................. 0 to 70 C
Storage Temperature Range .......................................................................... - 55 C to + 150 C
Lead Temperature (soldering, 10 sec) ........................................................................... + 325 C
Maximum Vee ...................................................................................................... + 7.0 V
Positive Voltage on any Pin, with respect to Ground ........................................................ Vee + 0.3 V
Negative Voltage on any Pin, with respect to Ground ............................................................ - 0.3 V
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the "Maximum Guaranteed Ratings" not be exceeded, or device failure can result. Some power supplies exhibit voltage spikes or "glitches"
on their outputs when AC power is switched off. In addition, voltage transients on the AC power line may appear on
the DC output. If this possibility exists it is suggested that a clamp circuit be used.
DC ELECTRICALSPECIFICATIONS(TA=OCt070C, Vee = 5.0V, + 5%)

Parameter
Min.
Max.
Units
SUPPLY CURRENT
30
mA
Icc
OUTPUT VOLTAGE
VOH (1)
2.4
V
VoH (2)
4.3
V
0.4
V
VOL
INPUT VOLTAGE
2.0
V
V'H (3)
0.8
V
V'L (3)
3.5
V
V'H (4)
1.5
V
V'L (4)
INPUT CURRENT
10
uA
I'H
2.0
mA
I'L
Notes:
(1) For all outputs except 10MHzOUTand 5MHzOUT
(2) For 10MHzOUT and 5MHzOUT
(3) For all inputs except XTAL 1 and 4XVCO
(4) For XTAL 1 and 4XVCO
AC ELECTRICAL CHARACTERISTICS (TA = 0 C to

Symbol
T,
T2
T3
T.
T5
T6
T7
T8
T.
T,o
T11
T'2
T'3
T,.
T'5

Min.

11

Max.
70
80

60
10
60
10

45
6
50

50
50
50

65
65
65
65
55

IOH=400 uA
IOH=400 uA
IOL=2.0mA

V'H = 2.0V
V'L = O.4V

+ 70 C, Vee = 5.0V,
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

631

± 5%)

figure 1
figure 1
figure 2
figure 2
figure 2
figure 2
figure 3
figure 3
figure 3
figure 3
figure 4
figure 5
figure 6
figure 7
figure 7

~~,!!/I#<4"

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FIGURE 1

FIGURE 4

FIGURE 2

FIGURES

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RCLK

WRGATE~

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RDIN

XDL

FIGURE 3

FIGURE 6

632

EARLY
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Analog Gnd

0.

Digital Ground

SCHEMATIC 1

RECOMMENDED CHARGE PUMP
LOOP FILTER AND VCO

633

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NOTE: The printed circuit board artwork shown above is included for illustration only. Camera ready artwork is available at no charge.
Contact your SMC representative or regional sales office, and ask for Technical Note TN 6-4.
Blank PC boards (based on the illustrations above) are also available to facilitate evaluation and design: Contact your SMC representative or regional sales office for more information.
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications; consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor
devices described any license under the patent rights of SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

634

HDC9227
PRELIMINARY

High Performance
Dual (Hard/Floppy Disk) Data Separator
DDS

FEATURES

PIN CONFIGURATION

D Single chip combines high performance analog hard
disk data separator and high resolution digital floppy
disk data separator

coo
CD,
RCLK
RDATA
EARLY
LATE

D Significantly reduces component count in hard disk and
floppy systems

D Completely compatible with the HDC 9224 Universal

WD~A

Disk Controller

10MHZOUT
20MHz/XTAL,
XTAL,
5MHZOUT
11
WRGATE
RDGATE
GND """"'-'-'---_=.r-

D Eliminates all tuning and tweaking normally required by
analog data separators

D Built-in hard disk write precompensation logic
D Fabricated in CMOS technology

D Single + 5V supply
D TTL Compatible

2XRDCLK
RESET
Vee
DLY30
DLY40
VCOOUT
D~D~

XDL
DLY50
PMPUP
PMPDWN
4XVCO
RDIN
WDOUT

PACKAGE: 28-pin DIP

GENERAL DESCRIPTION
The HDC 9227 Universal Disk Data Separator (UDDS) is a
28 pin CMOS/LSI device, which when used with the HDC
9224 Universal Disk Controller significantly simplifies the
design of the hard disk/floppy disk sub-system.
Internally, a precision floppy disk digital data separator is

combined with the digital portion of a high performance, self
tuning analog hard disk data separator.
By reducing the number of critical discrete components to
a minimum and eliminating all critical adjustments, the HDC
9227 simplifies the task of the system designer.

635

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.

~

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor

!!!! applications: consequently complete information sufficient for construction purposes is not necessarily given.

The information has been carefully checked and is believed to be entirely reliable. However, no responsibilitv is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of Ihe
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the best product possible.

636

HDC9234
PRELIMINARY

Universal Disk Controller
PIN CONFIGURATION

FEATURES
Programmable Disk Drive Interface and Formats

D IBM® PC-AT® ST506/412 or user definable hard disk
formats

D IBM® PC-AT® compatible ECC algorithm
D IBM Compatible Single or Double Density Floppy Disk

'"

RDATA

EARLY

3938373635343332313029
ClK

28

40

ABO
AB1

EARLY
RDATA
NC

V"

D Read/Write commands with automatic seek
D Multiple sector read/write transfers

INT

RCLK

D Sector interleave capability

CID
ACK

D Internal address mark generation and detection

19
18

B

DB,
DB,

cs

7891011121314151617

D Programmable track step rates
D Supports both buffered and unbuffered seeks
D Polling command allows overlapping seeks

I~I~~~~~~~~~~

AB7

cs

DBO
DB1

RDGATE
DB7
DBB
DB5

V,,

DB4

D Powerful, high level command set
D Controls up to 4 drives with

D
D
D

w

,,~ >- ,,-I~~~g
~1ti5 ~ ool~ ~ B hl ~ ~!f

Formats

D Controls 8",5.25", and 3.5" drives
D Controls tape drives for tape backup of disks
D Full CRC generation and checking
D Internal or External Error detection
D Programmable user-transparent Error correction
D Programmable automatic retry option
D Programmable internal write precompensation logic

PACKAGE: 44·pin PLCC

up to 16 heads per drive
up to 2048 cylinders per drive
up to 256 sectors per track

Flexible System Interface

D Programmable Interrupt Mask
D TTL compatible
D Standard 40 pin DIP package
D Single + 5 volt supply

D Built-in DMA controller capable of addressing up to
16MBytes
D Supports either private or virtual buffer memory
addressing schemes
D User readable Interrupt, Chip Status, and Drive Status
registers

GENERAL DESCRIPTION
The HDC 9234 Universal Disk Controller (UDC) is a 40
pin, n-channel MOS/LSI device capable of interfacing up
to 4 Winchester-type hard disks and/or industry standard
floppy disks to a processor. The chip is programmable to
support IBM® PC-AT® ST506/412 and user defined hard
disk formats, as well as IBM compatible 8", 5.25" and 3.5"
single and double density formats.

viding up to 24 bit addresses over an 8 bit data bus. This
enables the HDC 9234 to address up to 16 megabytes of
memory, and allows the hardware deSigner tremendous
flexibility in system design.

A powerful and sophisticated command set reduces the
software overhead required to implement a combined hard
disk/floppy disk controller. These commands include:
Drive Select
Seek to cylinder and read ID
Step out 1 cylinder
Step in 1 cylinder
Restore Drive
Read Logical Sectors
Read Physical Sectors
Read Entire Track
Write Physical Sectors
Write Logical Sectors
Chip Reset
Deselect Drive
Poll Drives for Ready
Set Register Pointer
Tape Back-up
Format current track
The HDC 9234 can use both private memory or shared
memory buffers with the chip's internal DMA controller pro637

Several techniques of error detection and correction are
implemented on the HDC 9234. One user selected method
allows the chip to detect and transparently correct a read
error in the data-stream, without external logic. Another
technique allows the designer complete control over the
ECC algorithm, by using external logic or system software
to detect and correct the error. As a further aid in error handling, the HDC 9234 allows the user to specify the number
of read retries to be attempted before an error is reported
to the host processor by the HDC 9234.
The HDC 9234 features a versatile track format command which allows formatting with interleaved sectors. The
chip needs only 4 or 5 bytes of external memory space per
sector (depending on format selected). This feature allows
the designer to optimize sector interleaving for optimum
throughput.

2XCLK

WGATE
RGATE

~--------------------~STB

S0
S1

RDATA
RCLK

ALUIREGISTER FILE

WRITE ENCODER
AND
PRECOMP LOGIC

WDATA
EARLY
LATE

BLOCK DIAGRAM OF DATA PATH IN HDC 9234
DESCRIPTION OF PIN FUNCTIONS
PIN NO.

NAME

SYMBOL

DESCRIPTION

1

Power

Vee

+ 5 volt power supply pin

22

Ground

Vss

System ground

16

Chip Select

CS

This signal (when active) selects the HOC 9234 for communications with the host
ftrocessor. This signal is normally derived by decoding the high order address bits.
t is active low.

17,18
19,20
21,23
24,25

Data Bus 7-0

DB7-0

All system processor reads and writes, (including status reads, initialization, disk
parameters, and commands) are 8 bit transfers which utilize these lines.
When the UDC is accessing memory, data is inptll or output on these lines.
Data on these lines is valid only when DATA STROBE (OS) is active low.

8-15

AuxBus7-0

AB7-0

These 8 pins are used to output drive control signals and DMA Address
information.
Additionally, these pins are used to input drive status information.

4

Command/lJata

C/l)

During processor to UDC communications, this input is used to indicate whether a
command or data transfer will follow.
If this pin is low, data may be written to, or read from, the internal data registers.
If this pin is high, the processor may write commands or read command results
from the UDC.

7

Read/Write

R/W

When the processor is communicati~ to the UDC, a high on this in~ut line indicates a (processor) request for a UD read operation, and a low in icates a (processor) request for a write operation.
R/W
0
0
1
1

C/O'
0
1
0
1

Operation
Write to register file
Write to command reg.
Read from register file
Read Interrupt Status Register

During UDC initiated 0rcerations, this pin becomes an output, and is used to indicate a read operation ( ogic 1) or write operation (logic 0) to external memories.

638

PIN NO.

NAME

SYMBOL

DESCRIPTION

6

Data Strobe

i)'S

This active low pin functions as both an input and output. When the processor is
writing to the UDC, the trailing edge of an active (low) signal applied to this pin indicates that the data on DB7-0 is valid, and the.data is latched into the appropriate
UDC register on the rising edge.
When the processor is reading from the UDC, the trailing ed8e of an active (low)
signal applied to this pin is used to clock out the desired UD register on to DB7-0.
During UDC initiated DMA operations, the UDC drives this pin low to either read or
write data from memory. On DMA read cycles, data is clocked in on the trailing
edge. On DMA write operations, the data on DB7-0 is valid anytime this pin is
active (low).
When this pin is high (logic 1), DB7-0 return to a high impedance state.

2

Interrupt

INT

This active high output is used by the UDC whenever it wants to interrupt the processor. The interrupt pin is reset to its inactive (low) state when the UDC interrupt
status register is read.

30

DMA In Progress

DIP

This active high output becomes active whenever the UDC is actually performing a
DMA operation.

28

DMA Request

DMAR

5

Acknowledge

ACK

This active high signal from the processor tells the UDC that the processor has
released the system bus and the UDC may access system memory.

37

Write Data

WDATA

This pin is used to output serial data from the UDC to the drive, in either FM or
MFM format. In both cases, data is output with the most significant bit first.

38

Late

LATE

This output (when active high) indicates that the current flux transition appearing
on WDATA is to be written late.

39

Early

EARLY

This output (when active high) indicates that the current flux transition appearing
on WDATA is to be written early.

27

Write Gate

WGATE

This output (when active high) indicates the drive should allow a write operation.

40

Read Data

RDATA

This input pin contains the serial bit stream read from the drive, in either FM or
MFM format. Media flux reversals are indicated by a negative transition.

3

Read Clock

RCLK

This input is generated by the external data separator. Its frequency should selfadjust to the variations in bit width in the data stream from the drive. This clock
supplies a window to indicate half-bit-cell boundaries.

26

Read Gate

RDGATE

This output pin is used to enable the external data separator, compensate for write
to read recovery time of the drive, and filter out the write splice in gaps 2 and 3.
The timing of this signal is dependent upon the type of drive (hard or floppy) being
used.
RDGATE is inactive at all times except when the UDC is actually performing a read
operation or an internal ECC operation.

29

ECCTime

ECCTM

When the UDC is used in external ECC mode, this output pin becomes active
(low) during the time the UDC is reading the ECC bytes from memory or external
ECC chip, when executing a WRITE command.
It is also active during internal ECC correction operations, and for either one
(write) or two (read) byte times after DIP (pin 30) becomes inactive following a sector transfer. This shows the system processor when it should service the UDC
buffer.

32,35

Select 1,0

S1,SO

This active high output becomes active whenever the UDC requires the system
bus to perform a memory cycle, and ACK is inactive. During hard disk operations,
it remains active until the sector transfer is complete.
During floppy disk operations, it is active for 1 byte transfer time.
The UDC shows that it has released the system bus by resetting this signal to its
inactive (low) state.

These active high outputs are used by external logic to select either the source or
destination for data transfers occuring via AB7-0. The following table defines the
transfer being called for by the UDC. (Note that S1-0 are valid only when
STB is active low.)

~ific

STB
1
0
0
0
0

S1

SO

X

X

0
0
1
1

0
1
0
1

639

AB7-0 Activity
S1 ,SO Invalid
UDC inputs Drive Status Signals
UDC outputs DMA address bytes
UDC outputs OUTPUT 1 signals
UDC outputs OUTPUT 2 Signals

PIN NO.

SYMBOL

DESCRIPTION

34

Strobe

NAME

'STS

This active low output indicates when the host processor should read or write to
AB7-0, as indicated by S1-0.
When AB7-0 are used as outputs from the UDC, data is valid anytime this signal is
active (low).
When AB7-0 are used as inputs to the UDC, data is clocked in on the rising edge
of this signal.

3S

DEVICE CLOCK

ClK

This input is the double frequency clock used by the UDC for all internal timing
operations.
Eight inch hard disk drives (with a nominal bit time of 230 ns) require an input of
8.696 MHz (115 ns period).
5.25" hard disks (with a nominal bit time of 200 ns) require a 10 MHz input (100 ns
period).
Eight inch, 5.25" and 3.5" floppy drives all require a 10 MHz clock, which is internally prescaled by the UDC to the correct frequency, as determined from the Drive
Seled command and MODE register.
This input requires an external pull-up resistor, as it is not TTL-level compatible.
See figure 2.

31

Reset

RST

This active low input will force the UDC into the following known state:
INT-Inactive low
WDATA-Inactive low
E'CCiM-lnactive high
DMAR-Inactive low
EARLY-Inactive low
C/D-Input
AB7-0-lnput
lATE-Inactive low
R/W-Inrrut
DB7-0- nput
WGATE-Inactive low
DIP-Inactive low
RDGATE-Inactive low
LiS-Input
An active low on this pin has the same effect as a RESET Command.

33

DMAClock

DMAClK

All UDC DMA operations will be synchronized to this clock input. Three DMAClK
periods are required for each DMA byte transfer.

Three internal registers (OUTPUT 1, OUTPUT 2, and
INPUT DRIVE STATUS) which are not directly addressable by the processor are accessed by the UDC. The information contained in these registers is used in disk interfacing and is input or output on UDC Pins AB7-0. The following
table describes these registers and the signals they output
or input on AB7-0.

OVERVIEW OF UDC REGISTERS
The HOC 9234 has three types of internal, processor
addressable reQisters; Read/Write, Read Only, and Write
Only. These registers are addressed by an internal register
pointer that is set by the SET REGISTER POINTER
command.
All register data is passed to and from the UDC via the
data bus (DB7-0).
The internal register pointer is automatically incrementedwith each register access until it pOints to the DATA
Register. This insures that all subsequent register accesses
will address the DATA register.

UDC ADDRESSABLE REGISTERS

=

DRIVE STATUS REGISTER (input) Select Pins S1 0, SO
ABS-Index Pulse
AB4-Track 00
AB5-Seek Complete
AB3-User Defined
AB1-Drive Ready
AB7-ECC'Error
ABO-Write Fault
AB2-Write Protect

=0

PROCESSOR ACESSIBLE REGISTERS
REGISTER AD DR
0
1
2
3
4
5
6
7
8
9
A
COMMAND

WRITE
DMA7-0
DMA15-8
DMA23-16
Desired Sector
Desired Head
Desired Cylinder
Sector Count
Retry Count
Mode
Interrupt/Command
Terminator
Data/Delay
Current Command

READ
DMA7-0
DMA15-8
DMA23-16
Desired Sector
Current Head
Current Cylinder
Temporary Storage
Temporary Storage
Chip Status
Drive Status
Data
Interrupt Status

640

OUTPUT 1 (Output)
AB7-Drive Select 3
AB5-Drive Select 1
AB3-Programmable
Outputs (see text)
AB1-Programmable
Outputs

Select Pins S1-1, SO-O
ABS-Drive Select 2
AB4-Drive Select 0
AB2-Programmable Outputs
ABO-Programmable Outputs

OUTPUT 2 (Output)
AB7 Drive Select 3
AB5-Step Direction
AB3-Desired Head (Bit 3)
AB1-Desired Head (Bit 1)

Select Pins S1 1, SO 0
ABS-Reduce Write Current
AB4-Step Pulse
AB2-Desired Head (Bit 2)
ABO-Desired Head (Bit 0)

=

=

Additionally, several registers (DMA7-0, DMA 15-8, DMA23-16, DESIRED SECTOR, DESIRED CYLINDER, SECTOR
COUNT, and RETRY COUNT) serve an alternate purpose. These registers are used by the FORMAT TRACK command
to hold parameters. This alternate register utilization is described in detail under the FORMAT TRACK command.

DESCRIPTION OF UDC REGISTERS
DMA 7-0
(R/W Register; Address 0)
This 8-bit read/write register is loaded with the low order
byte (MSB in bit 7) of the DMA buffer memory starting
address.
DMA 15-18
(R/W Register; Address 1)
This 8-bit read/write register is loaded with the middle
order byte (MSB in bit 7) of the DMA buffer memory starting
address.
DMA 23-16
(R/W Register; Address 2)
This 8 bit read/write register is loaded with the high order
byte (MSB in bit 7) of the DMA buffer memory starting
address.
Prior to the data transfer portion of a read or write command, the UDC writes the contents of the DMA registers to
an external counter. This transfer (from the registers to the
external counter) is accomplished by the UDC with 3 separate outputs on AB7-0, with the contents of DMA 24-16
beinll transfered first. In memory areas that require less than
24 bit addressing, the higher order bits are overwritten. The
external counter must be incremented with the UDC's DS
signal after each byte transfer.
If, during read operations, an error is detected during the
data transfer, a retry will occur (if so programmed), and the
three DMA registers will re-initialize the external counter to
the original starting address.
During multiple sector read/write operations, the DMA
address contained in the DMA registers will be incremented by the size of the sector selected at each sector
boundary. This ensures that during read operations the
address contained in the DMA registers always corresponds to the proper memory starting address of the sector
currently being read.

DESIRED HEAD REGISTER

(Write Register;
Address 4)
The contents of this reQister are compared to the disk
sector's ID Field when verifying a seek operation.
For the PC/AT format, this register is loaded with a 2-bit
sector size, and 4-bit head number.
BIT 7
Bad Block Mark (always 0)
BITS 6,5 Sector Size
6

5

SECTOR SIZE

o
o

o
1
o

256
512
1024
128

1

1

1

BIT 4
Always 0
BIT 3-0
Desired Head Number
For the SMC format, this 8-bit write only register is loaded
with the 4-bit head number and the upper 3-bits of thE;!
desired cylinder number.

BIT 7
Bad Block Mark (always 0).
BITS 6-4 MSBs of the Desired Cylinder number.
BITS 3-0 Desired Head Number.
The desired head number is output on AB3-0 during
OUTPUT 2 times.
(Write Register;
DESIRED CYLINDER REGISTER
Address 5)
This 8-bit write only register is loaded with the 8 low order
bits of the desired cylinder (MSB in Bit 7). Combined with
the 3 high order bits loaded into the DESIRED HEAD REGISTER, these 11 bits form the desired. cylinder number,
which is checked by read and write operations during the
Check ID portion of the command.
(Write Register;
SECTOR COUNT REGISTER
Address 6)
This 8-bit write only register is loaded with the number of
sectors to be operated on by the read or write command.
This allows multiple sectors on the same cylinder to be either
written or read.
c
c
c
0
0
(Write Register;
0
RETRY COUNT REGISTER
u
u
U
Address 7)
N
N
ADD 16-23
AB7-0
N
This 8-bit write only register is loaded with the number
T
T
T
E
E
E
of times the UDC should retry to read a data field before
HDC9224
R
R
R
reporting an error. Additionally, this register is loaded with
the user programmable output si~nals that the UDC out'----~8~ ADD 8-15
puts on ABO-3 during OUTPUT 1 times.
The retry count is loaded (in 1's complement format) into
1.-----~8. . ADD 0-7
the 4 most significant bits of this register.
The user programmable output signals are loaded into
the
4 least significant bits of the register.
DMA COUNTER OPERATION
BITS 7-4 Desired Retry Count (in 1's complement
format)
BITS 3-0 User Programmable Output Signals
REGISTER
(Write Register; Address 8)
DESIRED SECTOR REGISTER
(R/W Register; MODE
8-bit write only register defines the operating mode
Address 3) of This
UDC as follows:
This 8-bit read/write register is loaded with the starting BITthe
7 (DRIVE DATA TYPE)
sector number of a multiple sector read/write operation. This
bit determines how the UDC decodes data from the
Except for the last sector of the operation, this register is
drive.
incremented after each sector is written or read without error.
BIT 7 = (1): UDC configured for hard disk use. (Level
If the UDC terminates a command because of an error,
transitions)
BIT 7 = (0): UDC configured for floppy use. (Pulse
this register will normally contain the bad sector number,
and may be read by the processor.
inputs)
641

STEP RATES FOR DOUBLE DENSITY (MFM) OPERATION
DRIVE TYPE

(Mode Bit 4

5.25" HARD DISK

B"FLOPPY

5.25" FLOPPY

DB2
1
1
1
1
0
0
0

DB1
1
1
0
0
1
1
0

DBO
1
0
1
0
1
0
1

STEP RATE
3.2ms
1.6ms
O.Bms
O.4ms
0.2ms
0.1 ms
0.05ms

STEP RATE
32ms
16ms
Bms
4ms
2ms
1 ms
0.5ms

STEP RATE
64ms
32ms
16ms
Bms
4ms
2ms
1 ms

0

0
Pulse Width:

0

21.B us
11.2 us

21B us
112 us

436 us
224 us

=0)

(DOUBLE ALL OF THE ABOVE TIMES FOR SINGLE DENSITY (FM) OPERATIONS.)

BITS 6,5 (CRC/ECC Enable Code)
These bits determine the error detection/correction code
generated and checked by the UDC. In addition, they
enable the Write long command.
DB6

DB5

o
o

o
1
o

1
1

1

CODE GENERATED/CHECKED
CRC
Enable Write Long
Internal 32 bit ECC without correction
Internal 32 bit ECC with correction

With internal ECC selected the UDC will transfer 4 extra
bytes during reads and writes. Normal CRC checking is
still done on aliiD fields.
If ECC is not selected, then the UDC will perform CRC
checks on both data and ID fields.
BIT 4 (Single or Double Density)
This bit determines whether the UDC will perform its
operations in either single or double density.
BIT 4 = (1) Single Density (FM) Format
BIT 4 = (0) Double Density (MFM) Format
BIT 3 (ALWAYS 0)
BITS 2,1,0 (Step Rate Select)
These bits are programmed to select the desired drive step
rate. Note that all step rates are determined by the type
of drive and density selected, and are scaled from the ClK
input.
The UDC can output extremely rapid step rate pulses if
these bits are set to 000. This IS useful when the UDC is
controlling drives which support buffered seeks. For other
speeds, please refer to the table above.
INTERRUPT/COMAND TERMINATION REGISTER

(Write Register; Address 9)
This B-bit write only register allows the programmer to
mask. out a number of conditions that would cause termination of a command. (Such termination occurs when the
DONE bit in the INTERRUPT STATUS register is set.)
One bit in this register also controls the generation of interrupts when either the DONE bit or the READY CHANGE
bit in the INTERRUPT STATUS register go active.

In the IBM® PC-AT mode, this bit should always be set to
"1 ". Failure to do so may result in unreliable operation.
ID field CRC and data field CRC or ECC are generated
and tested from the first A1 HEX byte in the ID field.
BIT 6 (ALWAYS "0")
This bit should always be set to "0" by the user. Failure to
do this may result in unreliable operation.
BIT 5 (INT ON DONE)
If this bit is set (to "1 "), an interrupt will occur when the
DONE bit in the INTERRUPT STATUS register is set. If
this bit is reset (to "0"), no interrupt will be generated for
this condition.
BIT 4 (DELETED DATA MARK)
If this bit is set (to "1 "), the DONE bit in the INTERRUPT
STATUS register will be set when the DELETED DATA
MARK bit in the CHIP STATUS register goes active, and
the command will terminate when the current sector operation is completed.
BIT 3 (USER DEFINED)
If this bit is set (to "1 "), the DONE bit in the INTERRUPT
STATUS register will be set when the USER DEFINED
status bit in the DRIVE STATUS register goes active, and
the command will terminate when the current sector operation is completed.
BIT 2 (WRITE PROTECT)
If this bit is set (to "1 "), the write or write format command
in progress will terminate and the DONE bit in the INTERRUPT STATUS register will be set when the WRITE PROTECT bit in the DRIVE STATUS register goes active.
BIT 1 (READY CHANGE)
If this bit is set (to "1 "), an interrupt will occur when the
READY CHANGE bit in the INTERRUPT STATUS register
is set. If this bit is reset (to "0"), no interrupt will be generated for this condition.
The user should note that as a drive is selected or deselected, it is possible for the ready line from the drive to
change state, and care should be taken in the design of
the interrupt handler.

BIT 0 (WRITE FAULT)
If this bit is set (to "1 "), the write or write format command
BIT 7 (ALWAYS "1 ")
in progress will terminate and the DONE bit in the INTERRUPT STATUS register will be set when the WRITE FAULT
Setting this bit to "1" will cause the CRC register to preset
to 1 for CRC generation and checking.
status bit in the DRIVE STATUS register is set. The com642

mand in progress will terminate when the current sector
operation is completed.

DATA/DELAY REGISTER

(R/W Register; Address
OAH)

This 8-bit read/write register serves three purposes.
During UDC writes, data is placed in this register for
recording to the disk. During UDC reads, recovered data
is fetched from this register for storage into memory. All
transfers occur via DB7-0, under DMA control.
Additionally, this register is loaded with the HEAD LOAD
TIMER COUNT when the Drive Select command is issued.
(Note that the actual amount of head load time is this value,
times a value predetermined by the UDC, based on the
type of drive selected. For more information, please see
the Drive Select command description.)
Finally, in the IBM® PC-AT mode, this register is used
for a third purpose. If Implied Seek is enabled, this register
is used by Seek/Read 10 and Read/Write commands to
control the UDC seek operation. The data in the Data/
Delay Register and the Current Cylinder Register are used
to calculate the direction and step count for a seek.

BITS 6-4 Three most significant bits of the current cylinder.
(Most significant bit in BIT 6).
BITS 3-0 Current Head Number (MSB in bit 3).

CURRENT CYLINDER REGISTER

This 8-bit read only register is updated from the disk when
a valid 10 field sync mark is found while executing a read 10
field command sequence. This register will contain the 8
least significant bits of the cylinder 10 number, as specified
during formatting. (The 3 most significant bits of the 11 bit
cylinder 10 number are contained as part of the CURRENT
HEAD REGISTER.)

CURRENT IDENT BYTE REGISTER

5

4

Sector Size

o
o

o
1
o

128
256
512
1024

1

1

1

IDENT BYTE

FE
FF

o
o
1
o

1
1

1

FD

(Read Register)

This 8-bit read only register contains status information
associated with interrupt conditions and errors that occl!"
during disk QQeration. This register is read by setting C/O
high, and R/W high.
When the Interrupt Status register is read, the INT output
signal from the UDC will be reset (to an inactive low level).

Cylinder Number
0256 512 768 -

FC

CYLINDER NUMBERS
0-255
256- 511
512-767
768 -1023

INTERRUPT STATUS REGISTER

BITS 3,2 Always 0
BITS 1,0 MSB's of Cylinder Number

o
o

(Read Register;
Address 6)

This 8-bit read only register reads the Ident Byte from the
disk during the Read 10 command sequence. The Current
Ident Byte is written to the disk during the format, changing
as specified below.

Please note, the MSB's of the Desired Cylinder Number
does not correspond to those written in the Disk 10 field.
BITS 7,6 Always 0
BITS 5,4 Actual Sector Size

(Read Register;
Address 5)

255
511
767
1023

COMMAND REGISTER

(Write Register)

BIT 7 (INTERRUPT PENDING)
A "1" indicates that either DONE bit or READY CHANGE
bit has gone active. The user may disable these interrupts
by setting the appropriate bits in the INTERRUPT/COMMAND TERMINATION, REGISTER. This bit is reset (to "0")
by reading the Interrupt Status register.
BIT 6 (DMA REQUEST)
A "1" indicates that the UDC requires a data transfer either
to or from its data register. This bit is reset (to "0") by the
data transfer.

This 8-bit write only register is used to pass commands
to the UD,£:. Valid comf!!9,nds are given to the UDC...Qy
setting C/O high and R/W active high, while strobing OS
active (low).

BIT5(DONE)
A "1" indicates that the current command is completed. This
bit is reset (to "0") when a new command is issued.

CURRENT HEAD REGISTER

BIT 4,3 (COMMAND TERMINATION CODE(Valid only when DONE is set)
These two bits indicate the command termination
conditions:

(Read Register)

This 8-bit read only register is updated from the disk when
valid 10 field sync mark is found while executing a SEEK!
READ 10 command.
IBM® PC-AT MODE
BIT 7

1 Last Sector read had BAD SECTOR bit set.
0 Last Sector read had BAD SECTOR bit reset.
BIT 6,5 Sector Size
=

=

6

5

SECTOR SIZE

o
o

0
1
0
1

256
512
1024
128

1
1

81T 4 Always 0
~31T 3-0 Current Head Number (MSB in BIT 3)

!)MC AND FLOPPY MODES
BIT 7

=
=

1 Last sector read had BAD SECTOR bit set.
0 Last sector read had BAD SECTOR bit reset.

BIT4

BIT3

CONDITIONS

0
0

0
1

1
1

0
1

Successful command termination
Execution error in READ 10
Sequence
Execution error in SEEK Sequence
Execution error in DATA field

More detailed command termination error information is
obtained by reading the Chip Status register.
BIT 2 (READY CHANGE)
A "1" indicates that the "ready" signal from the drive has
experienced a low-to-high or high-to-Iow transition. (This
shows that the drive has either become ready or become
not ready.) This bit is reset (to "0") by reading the Interrupt
Status register.
BIT 1 (OVERRUN/UNDERRUN)
A "1" indicates that a overrun or underrun condition has
643

occured during a read or write command. These-conditions
occur when the UDC does not receive an acknowledge (to
a DMA request) by the time a byte is ready for transfer to or
from the processor. .
This bit can only be reset (to "0") with a RESET command
or a high on the RESET pin.
BIT 0 (BAD SECTOR)
A "1" indicates that a bad sector (as indicated from the MSB
of the head ID byte in the ID field) has been encountered.
This bit is reset when a new command is issued, or a good
sector is read.
CHIP STATUS REGISTER (Read Register; Address 8)
This 8-bit read only register supplies additional chip status information. The Information in this register is only valid
between the time that the DONE bit is set in the INTERRUPT STATUS register and the time when the next command is issued to the UDC.
BIT 7 (RETRY REQUIRED)
If a retry was attempted by the UDC during the execution of
any read or write command, this bit is set (to "1 ").
BIT 6 (ECC CORRECTION ATTEMPTED)
If the internal ECC circuitry, has attempted to correct a bad
sector, this bit is set (to "1' ).
BIT 5 (CRC/ECC ERROR)
If the UDC detects a CRC error or an ECC error this bit is
set (to "1 ").
BIT 4 (DELETED DATA MARK)
If the UDC reads a deleted data mark in the ID field, this bit
is set (to "1 "), otherwise it is reset (to "0").
BIT 3 (SYNC ERROR)
If the UDC does not find a sync mark when it is attempting
to read either an ID or data field, then this bit is set (to "1 ").
The command being executed will terminate when this bit
is set.
BIT 2 (COMPARE ERROR)
If the Information contained in the DESIRED HEAD and
DESIRED CYLINDER registers does not match that contained in an ID field on the disk, this bit is set (to "1 "). The
command being executed will terminate when this bit is set.
BIT 1,0 (PRESENT DRIVE SELECTED)
These two binary encoded bits represent the drive currently
selected and correspond to the Drive Select bits set in the
Output 1 and Output 2 latches.
BIT1

BITO

DRIVE SELECTED

0
0

0

0

1

1

1
1

0

2
3

1

BIT 6 (INDEX)
This bit is set (to "1 ") when the INDEX signal from the
selected drive is active. Typically, index pulses from the
drives are active for 1Ous-1 OOus for each disk revolution.
This signal is input to the UDC on AB6.
BIT 5 (SEEK COMPLETE)
This bit is set (to "1") when the SEEK COMPLETE signal
from the selected drive is active. This bit will go active when
the heads of the selected drive have settled over the desired
track (at the completion of a seek).
When a drive supplies this signal, reading and writing should
not be attempted until SEEK COMPLETE is set (to "1 ").
This signal is input on AB5.
For floppy disk operation, where the drives normally do not
provide this signal, a retriggerable one shot could be used
to generate a SEEK COMPLETE signal (if desired).
BIT 4 (TRACK 00)
This bit is set (to "1 ") when the TRACK 00 signal from the
selected drive is active. This indicates that the heads on the
selected drive are positioned over track O. This signal is input
onAB4.
BIT 3 (USER DEFINED)
This bit is set (to "1 ") when the USER DEFINED signal is
active. This Signal is input on AB3.
BIT 2 (WRITE PROTECT)
This bit is set (to "1 ") when the WRITE PROTECT signal
from the selected drive is active. When set, this bit indicates
that the disk in the selected drive is write protected. This
signal is input on AB2.
BIT 1 (READY)
This bit is set (to "1 ") when the READY signal from the
selected drive is active. When set, this bit indicates that the
drive is ready to execute commands. This signal is input on
AB1.
BIT 0 (WRITE FAULT)
This bit is set (to "1") when the WRITE FAULT signal from
the selected drive is active. This signal, when active, indicates that a condition exists at the drive that would cause
improper writing on the disk. This signal is input to the UDC
on ABO.
TEMPORARY STORAGE REGISTERS
The UDC contains two temporary storage registers, used
by the UDC for internal operations. The host processor
should not attempt to read or modify these registers, as
unpredictable results may occur.
UDC COMMAND OVERVIEW

DRIVE STATUS REGISTER

(Read Register;
Address 9)
This 8-bit read only register contains status information
generated by the drives, external ECC Chip (if any), and a
user definable input to the UDC from the drive.
To save pins on the UDC, the 8 status lines are input on
AB7-0 and are latched in this internal reQister. The UDC will
update this register whenever it is not uSing AB7 -0 to output
DMA counter values, OUTPUT 1, or OUTPUT 2 data. When
configured as described below, the UDC will input drive status Signals and interpret them as follows. In all cases, a logic
"1" is considered the active input.
BIT 7 (ECC ERROR)
This bit is set (to "1") when the ECC ERROR siQnal is generated by an external ECC Chip. This signal is Input to the
UDConAB7.

644

The HDC 9234 has 16 high-level commands that provide
the user with a high degree of flexibility and control. All of
the commands for the UDC can be thought of as falling into
one of two basic groups.
The first group handles the "housekeeping" required by the
drives and the UDC itself. These commands are:
RESET
STEP OUT 1 CYLINDER
STEP IN 1 CYLINDER SET REGISTER POINTER
DRIVE SELECT
RESTORE DRIVE
DESELECT DRIVES
POLL DRIVES
The second group comprises the "READ/WRITE" functions required in a magnetic disk subsystem. These commandsare:
SEEK/READ ID
TAPE BACKUP (READ/
FORMAT TRACK
WRITE)
READ TRACK
READ SECTORS LOGICAL
READ SECTORS PHYSICAL
WRITE SECTORS LOGICAL

An internal status byte, which contains the BAD SECTOR,
DELETED DATA and OVER/UNDER RUN bits, along with
the current state ofthe READY, WRITE PROTECT, WRITE
FAULT, and USER DEFINED lines, is checked at various
times during command execution.
This internal status byte is examined before the execution
of all READ/WRITE commands, and is also checked just
prior to the completion of all commands (exceptfor RESET,
where its values would be meaningless.)
This byte is also checked by the UDC between sectoroperations during the execution of READ LOGICAL, READ
PHYSICAL, WRITE LOGICAL and WRITE PHYSICAL
commands.

READ ANY ID
FIELD FROM
CURRENT CYLINDER

The UDC makes decisions regarding command termination and interrupt generation based on the contents of this
status byte, and the state of the bits in the INTERRUPT/
COMMAND TERMINATION register. (Note that "write protect" and "write fault" status may cause command termination only during write and format operations.)
All commands (except RESET) terminate with the DONE
bit in the INTERRUPT STATUS register being set. This bit
may also be considered to be an inverted "busy"· line, as
the UDC resets it upon receipt of a valid command.
During all READ/WRITE group commands (except FORMAT TRACK and BACKUP), the UDC utilizes some common command execution sequences. Prior to entering each
sequence the UDC sets the COMMAND TERMINATION
bits (in the INTERRUPT STATUS register) to a known state.
If a command fails to execute properly, these bits may then
be used to determine where the command aborted.
The sequences common to the READ/WRITE group commands are as follows:
1. READ 10 FIELD (Command Termination Code = 0-1)
First, the UDC attempts to find an 10 Field Sync mark.
If no sync mark is found within 33,792 byte times (byte
time = time to read one byte from the type of drive
selected), the SYNC ERROR bit (in the CHIP STATUS register) is set (to "1 "), and the command is
terminated.
During this phase, the UDC will raise and drop
RDGATE up to 256 times (as it attempts to read each
sector on the cylinder).
After the 10 Field is found, the UDC reads it and
updates it CURRENT HEAD and CURRENT CYLINDER registers. This information was written to the
disk during formatting.
Next, the UDC checks the CRC of the 10 field which
was read. If it is incorrect, the UDC sets (to "1") the
CRC ERROR status bit (in the CHIP STATUS register) and terminates the command.
If the CRC is correct, the UDC then calculates the
direction and number of step pulses required to move
the head from the current cylinder to the cylinder
specified in the DESIRED HEAD REGISTER. These
pulses, and the direction bit are output during the
OUTPUT 2 times.
If a command should terminate while in the sequence,
the COMMAND TERMINATION bits will be set to
0-1.
2. VERIFY
(Command Termination Code = 1-0)
After the UDC has read the 10 Field, it attempts to verify that it has found the correct cylinder. To do this, the
UDC tries to find an 10 Field sync mark on the selected

645

READ AND VERIFY
ID FIELD FROM
CURRENT CYLINDER

SEEK/READ ID OPERATION

disk. If the UDC is unable to find an ID Field sync mark
within 33,792 byte times, the SYNC ERROR bit (in the
CHIP STATUS register) is set to "1", and the command is terminated.
The UDC, after finding the ID Field sync mark, then
reads the ID field and compares the information on
the disk to the information contained in the DESIRED
CYLINDER, DESIRED HEAD and DESIRED SECTOR registers.
The UDC will hunt for sync marks and read ID fields
until the desired sector is found. If the desired sector
is not located within 33,792 byte times, then the
COMPARE ERROR bit (in the CHIP STATUS register) is set to "1", and the command is terminated.
After the correct sector is found, the UDC checks the
CRC for the sector ID Field. If this is found to be incorrect, the UDC sets to "1" the CRC/ECC ERROR bit
in the INTERRUPT STATUS register, and the command is terminated.
(When the UDC is executing a READ PHYSICAL or
WRITE PHYSICAL command, ID Fields are checked
only until the first sector to be transfered is found. No
ID Field checking is performed on subsequent sectors, although CRC checking is done.)
If a command should terminate while in this sequence,
the COMMAND TERMINATION bits will be set to
1-0.
3. DATA TRANSFER
(Command Termination
Code = 1-1)
If a READ PHYSICAL or READ LOGICAL command is being executed, the UDC will try to find a data
sync mark (FBhex or F8hex) on the disk. If the sync
mark found is F8h, then the UDC will set the DELETED
DATA MARK bit in the CHIP STATUS register.
After a data sync mark is found, the UDC then updates
its CURRENT HEAD and CURRENT CYLINDER
registers from the information found on the disk and
initiates a DMA request. If the host processor does not
respond to the request within 1 byte time, then the UDC
will set to "1" the OVER/UNDERRUN status bit in the
INTERRUPT STATUS register, and the command will
terminate.
USing DMA, the UDC transfers a sector's worth of data,
and then reads the ECC and/or CRC bytes. If a CRC
error or uncorrectable ECC error is detected, the UDC
will decrement the RETRY REGISTER, set the
RETRY REQUIRED status bit (in the CHIP STATUS
register), and return to the VERIFY sequence.
Ifthe UDC cannot read the sector, and the count in the
ENTRY COUNT register has expired, then the CRC/
ECC Error bit (in the CHIP STATUS register) is set,
and the command terminates.
During a multi-sector transfer, the UDC updates the
DMA registers after all sector operations, including the
last one, and the SECTOR COUNT register is decremented. If the SECTOR COUNT register equals 0,
then the command is terminated. If the SECTOR
COUNT register is not equal to 0, then the UDC will
increment the DESIRED SECTOR register, re-initialize the RETRY COUNT register (to its original value)
and return to the VERIFY sequence.
If a command should terminate while in this sequence,
the command termination bits will be set to 1-1.

COMMAND DESCRIPTION
RESET
(Hex Value 00)
This command causes the UDC to return to a known state.
This command allows the system software to reset the chip,
and has the same effect as RST input becoming active.

=

646

MULTIPLE SECTOR READ OPERATIONS

=

DESELECT DRIVE
(Hex Value 01)
This command causes all of the drive select bits (Drive
Select 0-3) in the OUTPUT 1 and OUTPUT 2 registers to
become inactive.
RESTORE DRIVE
(Hex Values = 02, 03)
This command will cause the HDC 9234 to output step
pulses to the selected drive, so as to move the head back
to Track 00. Before each step pulse, the UDC first checks
the TRKOO and READY bits in the DRIVE STATUS register.
If TRKOO is active (high) or READY is inactive (low), then
the UDC will terminate the command.
The UDC will output up to 4096 step pulses. If the drive does
not respond with an active (high) TRKOO signal within this
period, the UDC will terminate the command with the DONE
bit set (to "1") and the COMMAND TERMINATION CODE

bits sei to 1-0. (These bits are contained in the INTERRUPT STATUS register.)
This command takes two forms:
COMMAND BYTE
RESULT
02
The command will terminate, and an interrupt generated after the UDC has issued the
step pulses.
The command will terminate, and an inter03
rupt~enerated after the drive has provided
a S EK COMPLETE signal to the UDC.
(This is useful in systems with "buffered
seek" drives.)
This command uses the step rate value loaded into the
MODE register.
STEP IN 1 CYLINDER
(Hex Values = 04, 05)
This command will cause the HOC 9234 to issue one step
pulse towards the inner most track. This command is generally used during track formatting, and takes two forms:
COMMAND BYTE
RESULT
04
The command will terminate, and an interrupt generated after the UDC issues the
step pulse.
05
The command will not terminate until the
UDC recognizes the SEEK COMPLETE
signal from the selected drive. Upon recognition of SEEK COMPLETE the UDC will
generate an interrupt.
This command uses the step rate value programmed into
the MODE register.
STEP OUT 1 CYLINDER
(Hex Values = 06, 07)
This command will cause the HOC 9234 to issue one step
pulse towards the outer most track (Track 00). This command is generally used during track formatting, and takes
two forms:
COMMAND BYTE
RESULT
06
This command will terminate, and an interrupt generated after the UDC issues the
step pulse.
07
This command will not terminate until the
UDC recognizes the SEEK COMPLETE
signal from the selected drive. Upon rec~nition olthe SEEK COMPLETE, the UDC
will generate an interrupt.
This command uses the step rate value programmed into
the MODE Register.

the DRIVE STATUS register to determine which drive
caused the command termination.
The POLL DRIVES command must be preceeded by SEEK
or DESELECT. In normal use, a SEEK command would
precede the POLL DRIVES command. In those cases
where another command (other than SEEK) has been
issued to a drive in the polling sequence, it will be necessary to DESELECT that drive prior to issuing the POLL
DRIVES command. This applies even if the selected drive
was not included in the polling sequence.

=

DRIVE SELECT
(Hex Values 20 thru 3F)
This command will cause one of (up to) four drives to be
selected for operation. Any previously selected drive is
deselected by this command. Bits 0 and 1 in the command
word indicate (in binary form) which of the (up to) four drives
has been selected.
COMMAND WORD
DB1
DBO
0
0
0
1
1
0
1
1

DRIVE
SELECTED
Drive 0
Drive 1
Drive 2
Drive 3

Decoded drive select Signals are then placed on the data
bus (via AB7-AB4) during OUTPUT 1 times and should be
latched externally.
Since the HOC 9234 can interface both hard disks and floppy
disks to a processor, the Drive Select command needs to
also specify the type of drive being selected. Bits 2 and 3 in
the command word are used to pass this information to the
chip, and take the following form:
COMMAND WORD
DB3
DB2
0
0

0

1

1

0

TYPE
OF DRIVE
Hard disk with IBM® PC-AT compatible format-512 Byte data field and
4 byte ID field per sector. No internal
clock prescaling performed.
Hard disk with user defineable format. This format allows a data field
length of 128, 256, 512, 1024, 2048,
4096,8192, or 16384 bytes with 5
byte ID field ~er sector. No internal
clock pre-sca ing is performed.
8 inch floppy disk, with standard 4
byte (FM) or 5 byte (MFM) ID field.
An internal divider creates a 1 MHz
clock to be compatible with standard
disk data rates.
5.25 inch floppy disk, with standard 4
byte (FM) or 5 byte (MFM) ID field.
An internal divider creates a 500 KHz
clock to be compatible with standard
disk data rates.

1
1
POLL DRIVES
(Hex Values = 10 thru 1F)
This command polls the drives for a SEEK COMPLETE
signal allowing the user to perform simultaneous seeks on
up to four drives. Polling is enabled by setting (to 1) the
appropriate bit in the command word: bit 0 for drive 0 thru
NOTE: Microfloppy system designers should determine
to bit 3 for drive 3.
whether the drive they have chosen to use in the system is
compatible with 8" floppy drives or 5.25" floppy drives, and
This command executes as follows:
use the appropriate values from the table above.
The UDC will output a drive select for the first drive in
the polling sequence and look for a SEEK COM- Note that eight inch Winchester-type drives require an 8.696
PLETE status input from the polled drive. If the polled MHz system clock. All other drives require a 1a MHz system
drive has not completed a seek, then this line remains clock. It is not possible for the UDC to derive internally the
low (logic 0), and the UDC selects the next drive in the clocks required for floppy disk operation from the 8.696 MHz
polling sequence. This continues until the UDC detects clock required by 8 inch Winchester drives.
a SEEK COMPLETE signal from a drive, which causes To insure compatibility with various drives, the HOC 9234
the DONE bit in the Interrupt Status register to be set, features a programmable head load timer. Head load delay
and the command terminates.
may be inhibited by resetting the Delay Bit (Bit 4) in the Drive
The UDCwili continue to selectthe drive that produced Select command word to O. If Bit 4 is set (to 1), then the
the SEEK COMPLETE signal, allowing the user to read head load delay timer is configured with the value in the
647

DATA/DELAY register (Register A), multiplied by value
shown below:
DRIVE AND
HEAD LOAD TIMER INCREMENT
FORMAT SELECTED (BIT 4 = 1 = Delay Enabled)
5.25" HARD DISK
200 usec
(Double Density)
5.25" HARD DISK
400usec
(Single Density)
HEAD LOAD
8"FLOPPY
2msec ~The
IMER is set to a value
IPouble Density)
equal
to
increment·
8" LOPPY
4msec times thethis
number in the.
(Single Density)
DATA/DELAY register.)
5.25" FLOPPY
4msec
(Double Density)
5.25" FLOPPY
8msec
(Single Density

The Drive Select command also optimizes certain characteristics of the HOC 9234 for the type of drive selected.
IF HARD DISK SELECTED:
-DMA mechanism works in burst mode and the bus is
held for the entire sector transfer.
-The RDGATE and WRGATE output signals follow the
timing relationships shown in Figures 12A and 12B.
-The GAP lengths are as shown in Table 1.
IF FLOPPY DISK SELECTED:
-DMA mechanism transfers an 8-bit byte, and releases
the bus.
-The RDGATE and WRGATE output signals follow the
timing relationships shown in Figures 12A and 12B.
-The GAP lengths are as shown in Table 1.
-The CLK input clock is prescaled (internally) to create
an internal clock compatible with the floppy disk data
rates.

reduces the number of times the user must set the register
pointer during read and write operation.
Care should be taken to ensure that only valid register values are loaded into the command word. (Valid register
numbers are 0 thru OAH.)
SEEK/READ 10
(Hex Values = 50 to 57)
This command will cause the UDC to read the first sector
10 field found from the currently selected drive, head, and
cylinder. The MODE re~ister should contain the correct value
for step rate and density options.
After reading the 10 field the UDC will examine the command word and execute the specified options. Bits 2 thru 0
in the command word are used to specify the following
options:
BIT 2 = 1 STEP ENABLE. The UDC will execute the step
sequence, and position the head on the track
specified by the DESIRED CYLINDER register.
BIT 2 = 0 STEP DISABLE. No step pulses will be issued
by the UDC.
BIT 1

1 WAIT FOR COMPLETE. The UDC will proceed
to the verify sequence only after the drive has
issued a SEEK COMPLETE signal.
BIT 1 = 0 DO NOT WAIT FOR COMPLETE. The UDC will
proceed to the verify sequence after the last step
pulse has been issued.
=

1 VERIFY 10. The UDC will execute the VERIFY
sequence after operations selected by the previous options have finished.
BIT 0 = 0 DISABLE VERIFY 10. The UDC will not enter
the VERIFY sequence. Instead, the command
will terminate.
The order in which these options execute is: STEP, COMPLETE, VERIFY 10. Any combination of these option bits
SET REGISTER POINTER
(Hex Values 40 to 4A)
may be specified in the command word.
This command causes the register pointer to point to a regREAD SECTORS PHYSICAL (Hex Values = 58 and 59)
ister. The desired register number is loaded into the 4 least
This command will cause the UDC to read up to a full track
significant bits of the command word. (MSB in BIT 3).
from the disk. The user specifies the MODE, DESIRED
The register pOinter is incremented by the UDC on each
CYLINDER, DESIRED HEAD, and DESIRED SECTOR
register access, until it points to the DATA ~egister. This
along with the SECTOR COUNT. When using the IBM® PCAT format, register A must also be initialized. The UDC will
find the requested cylinder and sector and set up to begin
the data transfer.
DMA ADDR (LOW BYTE
(If using drives which support buffered seeks, BITS 2-0 in
the MODE SELECT register should be set to 0-0-0. This
DMA ADDR (MIDDLE BYTE)
will cause the UDC to wait for a SEEK COMPLETE signal
DMA ADDR (HIGH BYTE
from the drive prior to entering the verify sequence.)
If a BAD SECTOR bit is read (from the sector 10 field) the
SECTOR NUMBER
UDC will set the COMMAND TERMINATION bits (in the
INTERRUPT STATUS register) to 1-0, and set the DONE
HEAD NUMBER
bit (in the INTERRUPT STATUS register) to 1, and terminate the command.
REGISTER POINTER
CYLINDER NUMBER
After each sector is successfully read, the SECTOR COUNT
register is decremented. If the SECTOR COUNT register
SECTOR COUNT
is not yet equal to 0 the process is repeated for the next
RETRY COUNT
physical sector on the track. This command also willterminate if the Index pulse is received from the drive.
MODE/CHIP STATUS
(Note that after the first sector is found, no further comparison is made against sector numbers found on the disk as
INTERRUPTIDRIVE STATUS
the DESIRED SECTOR register value may not correspond
to the next physical sector on the disk because of sector
DATA
interleaving.)
This command takes two forms allowing the user to specify'
the desired transfer option. The options are specified by Bit
oin the command word, and are:
SET REGISTER POINTER COMMAND
BITO = 1 TRANSFER ENABLE. The UDC will transfer the
data fields to (external) memory, using DMA.
648

=

BIT 0

=

BITO = 0 TRANSFER DISABLE. The UDC will NOT
transfer any data to (external) memory, but all
error detection circuitry will be enabled and
errors reported. This is useful in detecting bad
sectors and tracks on the disk.
Before executing this command, the user must set the
RETRY COUNT to O. This is done by loading tlie high order
nybble in the RETRY COUNT register to "1111" (zero in 1's
complement format). Failure to do this will result in unpredictable performance because the DESIRED SECTOR
register value may not correspond to the next physical sector on the disk.

READ TRACK
(Hex Values = 5A and 58)
When this command is issued, the UDC will read the data
from the entire track on which the selected drive is currently
sitting. The UDC will begin reading when it detects the leading edge of an index mark signal from the drive, and terminate reading when it detects the next leading edge of an
index mark signal. Sync detect is performed for the 10 field,
but no error checking is done on the data field.
This command allows the user to specify a data transfer
option, using Bit 0 in the command word. These options are:
BITO = 1 TRANSFER ALL DATA. The UDC will transfer
the 10 field and data fields to (external) memory.
BIT 0 = 0 TRANSFER ONLY IDs. The UDC will transfer
only 10 fields to the (external) memory. This is
useful during tape backup operations.

NO

=

READ SECTORS LOGICAL (Hex Values 5C to 5F)
When this command is issued, the UDC will read up to a full
track from the selected drive. Prior to reading the data from
the disk, the UDC will (if enabled in command) use the information in the MODE, DESIRED CYLINDER, DESIRED
SECTOR and DESIRED HEAD (and Register A for IBM®
PC-AT mode) registers to locate the correct track, sector
and drive surface (using the previously described VERIFY
sequence).
(If using drives which support buffered seeks, BITS 2-0 in
the MODE SELECT register should be set to 0-0-0. This
will cause the UDC to wait for a SEEK COMPLETE Signal
from the drive prior to entering the verify sequence.)
Before the command is issued, the system processor must
also load the desired values into the MODE, SECTOR
COUNT, RETRY COUNT and the three DMA registers.
After the desired track and sector is found and verified, the
DATA TRANSFER sequence begins. After each successful sector transfer, the UDC increments the DESIRED
SECTOR register (except after the last sector is transferred), decrements the SECTOR COUNT register, and reenters the VERIFY sequence. This process continues until
the SECTOR COUNT register is equal to 0 (or an error
occurs).
This command has four options, which are specified by Bit
1 and Bit 0 of the command word. The four options are:
BIT 1 = 1 IMPLIED SEEK DISABLED. The UDC will not
update the CURRENT CYLINDER, CURRENT
HEAD OR CURRENT SECTOR register and will
not issue step pulses.
BIT 1 = 0 IMPLIED SEEK ENABLED. The UDC will
update the CURRENT CYLINDER, CURRENT
HEAD and CURRENT SECTOR register and will
issue step pulses if requird.
BITO = 1 TRANSFER ENABLED. The UDC will transfer
data from the disk to the system. The DMA
REQUEST status bit (in the INTERRUPT STATUS register) will be set when the UDC requires
servicing.

649

READ SECTORS OPERATION
BITO = 0 TRANSFER DISABLED. The UDC will not
transfer data read from the disk, but all error
checking circuitry will be enabled.

FORMAT TRACK
. (Hex Values 60 to 7F)
This command causes the UDC to format the current cylinderfrom the leading edge of one index mark tothe leading
edge of the next index mark. The format chosen is dependent on the Drive Select command.
During execution of the FORMAT TRACK command, the
UDC will fetch all required 10 field data from external memory, and write it to the disk, along with format constants supplied automatically by the UDC. This reduces the number
of bytes required to format a sector to 3 or 4, depending on
the format chosen.
Before the FORMAT TRACK command can be given, the
system processor must:

1. Generate an ID Field Table for the track in UDC memory
area. This ID Field Table consists of:
IDENT BYTE (not required for floppy disk FM format)
CYLINDER BYTE
HEAD BYTE
SECTOR NUMBER BYTE
SECTOR SIZE/ECC SIZE BYTE (not required for
IBM® PC-AT FORMAT) repeated for each sector on
the track.

o

14
:6
I

29

PARAMETER
GAPOSize
GAP 1 Size
GAP 2 Size
GAP 3 Size
Sync Size
Sector Count

8

o
4
INTERLEAVED SECTORS

Sector Size Mult.

25
2
10

FORMAT
two's complement
format
two's complement
format
two's complement
format
two's complement
format
one's complement
format
one's complement
format
one's complement
format

REGISTER
DMA7-0
DMA15-8
DMA23-16
Desired Sector
Desired Cylinder
Sector Count
Retry Count

FORMAT PARAMETERS TABLE
When using the hard disk format, the values for GAP 0
and GAP 1 must both be set to the same number, and
loaded into the appropriate DMA register.
The Sector Size Multiple programs the UDC to format with
a sector size that is a multiple of 128 data field bytes. For
example, to format a track with a sector data field size of
256 bytes, then the Sector Size Multiple would be set to
FD hex, which is "2" in one's complement notation.
In IBM® PC/AT mode, the sector sizes allowed are 128,
256,512, or 1024 bytes. In IBM® floppy disk format, the
sector sizes allowed are 128, 256, 512, or 1024 bytes. With
user defineable hard disk formats, allowed sector sizes
are 128, 256, 512, 1024, 2048, 4096, 8192, or 16384 bytes.
6. Load the MODE register to specify the step rate, single
or double density option, and CRC/ECC options.
7. Step to the desired track. For the first track, this is normally done by issuing a RESTORE DRIVE command, to
return the heads to Cylinder 000, then use the STEP IN
1 or STEP OUT 1 commands to move the head to subsequent cylinders on the disk.
8. Issue the FORMAT TRACK command. All data fields on
the disk will be filled with E5 hex. In double density
recording (MFM) all gaps will be filled with 4E hex, while
in single density (FM) all gaps will be filled with FF hex.
This format is compatible for IBM specifications for floppy
disks.
9. To Format additional tracks, it is only necessary to update
the ID Field table (step 1) and repeat steps 7 and 8. Do
NOT modify the DESIRED HEAD register when formatting additional tracks with the same head. If it is necessary to change the DESIRED HEAD register, the system
processor must repeat all steps described above.
The FORMAT TRACK command allows the user to
specify several options. These options are specified by
setting the appropriate low order bits in the command
word. The bit mapping for these options are:
BIT 4 = 0 Write Deleted Data Mark. During the format
process, the UDC will write the deleted data
mark (F8 hex) for the data address field.
BIT 4 = 1 Write Normal Data Mark. During the format
process, the UDC will write the normal data
field address mark (FB hex).

The UDC can format a track with interleaved sectors by
staggering the sector numbers. For example, to format a
32 sector track, with a sector interleave factor of 4, the
system processor would set up the ID Field table sector
numbers as follows:
0,8,16,24,1,9,17,25,2,10,18,26,3,11,19,
27 ... 7,15,23,31.
(Note that when formatting in IBM® PC-AT and floppy FM
modes, only four bytes are required for each sector, while
five bytes are needed for floppy MFM and user defineable formats. Also note that sector numbers start with zero
(0) on IBM® PC-AT compatible format, and start with one
(1) on IBM formatted floppy diskettes.)
2. Load the UDC DMA registers with the starting address
of the external memory buffer containing the ID Field data
just created.
3. Issue the DRIVE SELECT command, which moves the
DMA registers to the CURRENT HEAD, CURRENT
CYLINDER, and a TEMPORARY REGISTER. (This is
necessary because the UDC will now re-use the DMA
registers to hold format parameters).
BIT 3 = 1 Write with Reduced Current. When this bit is set,
When formatting multiple cylinders, the system procesthe Reduced Write Current Output will go high
sor does not need to re-issue DRIVE SELECT between
cylinders as the STEP IN and STEP OUT commands
(active) during the Output 2 time slot.
preserve the DMA addresses and format parameters. It
BIT 3 = 0 Write with Normal Current. When this bit is reset,
is necessary, however, to update the ID Field table,
the Reduced Write Current Output wil remain low
described in #1, above.
(inactive) during the Output 2 time slot.
4. Load the DESIRED HEAD register with the proper value.
Bits 2, 1, and 0 are used to select the Write Precompensa5. ·Load the following values (in the format shown) into the
tion value to be used during the format of disks. The followregisters indicated below:
ing table specifies these values:
650

SECTOR SIZE FIELD BITS (IBM® FLOPPY AND USER
SELECTABLE HARD DISK FORMATS)
DB2
0
0
0
0
1
1
1
1

DB1
0
0
1
1
0
0
1
1

DBO
0
1
0
1
0
1
0
1

IBM FD FORMAT
128 bytes/sector
256 by1es/sector
512 bytes/sector
1024 bytes/sector
not used
not used
not used
not used

WRITE SECTORS LOGICAL (Hex Values AO thru BF,
EO thru FF)
This command will cause the UDC to write logically consecutive sectors on the disk. Before issuing this command,
the system processor must load the following UDC
registers:
DESIRED SECTOR
DESIRED CYLINDER
DESIRED HEAD
SECTOR COUNT
DMA 15-8
DMA 7-0
DMA 23-16
MODE
RETRY COUNT
REGISTER A (for IBM®
PC-AT Mode)
Since retries during a write command are not valid, the
high order nybble of the RETRY register should be set to
0, in 1's complement format (1111).

HD FORMAT
128 bytes/sector
256 bytes/sector
512 bytes/sector
1024 bytes/sector
2048 bytes/sector
4096 bytes/sector
8192 by1es/sector
16,384 bytes/sector

FORMAT ECC TYPE FIELD (IBM® FLOPPY AND
USER SELECTABLE HARD DISK FORMATS)
DB7 DB6 DB5 DB4
HD FORMAT
o 0 0 0 4 ECC bytes generated/checked
1
1
1
1 5 ECC bytes generated/checked (1)
1
1
1
0 6 ECC bytes generated/checked (1)
1
1
0
1 7 ECC by1es generated/checked (1)
note 1: WITH EXTERNAL ECC

(

WRITE

t
SEEK TO
DESIRED CYLINDER

IBM® MFM FLOPPY DISK FORMAT:

t

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
IDFIELD
IdentByte.
IDENT"
track number
CYLINDER
HEAD
side number
SECTOR
sector number
sector size
(3 bits)
SECTOR SIZE

WRITE DATA MARK
OR DELETED
DATA MARK

t

IBM® FM FLOPPY DISK FORMAT:

WRITE DATA
TO DISK

ID FIELD
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
track number
CYLINDER
HEAD
side number
SECTOR
sector number
SECTOR SIZE X
X
X
X
X
sector size

~
CALCULATE CRC OR
ECC BYTES AND
WRITE TO DISK

HARD DISK FORMAT: IBM PC-AT FORMAT
(512 BYTES)
ID FIELD
IDENT
CYLINDER
HEAD

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
Ident Byte
cylinder number (8 LSB's)
o sctr sctr 0 hd# hd# hd# hd#
bit 3 bit 2 bit 1 bit 0
bit 1 bit 0

SECTOR

sector number

HARD DISK FORMAT: (USER SELECTABLE
SECTOR SIZE)
ID FIELD
IDENT"
CYLINDER
HEAD

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
Ident By1e
cylinder number (8 LSB's)
bad cyl# cyl# cyl# hd# hd# hd# hd#
~tr~m~9~8~3~2~1~0

flag
SECTOR
SECTOR SIZE

sector number
ECC type
X
sector size
(3 bits)

C

~

RETURN

)

WRITE DATA OPERATION
Before writing data to the selected disk drive, the UDC will
read the current ID field, step to the desired cylinder (if
enabled in command) and verify that has located the correct cylinder and sector. (These steps were described previously under "UDC Command Overview").
After the "Verify" sequence is done, the "data transfer"
sequence begins. The UDC will first write either a Data
Mark (FB hex) or Deleted Data Mark (F8 hex) on the disk,
as selected by the user (see below). Then the UDC will
transfer a sector's worth of data (using DMA) from the
memory area specified by the DMA registers. After writing
out the sector, CRC or ECC bytes will be written as spec. ilied by the MODE register.
Next, the SECTOR COUNT register is decremented, and
if not yet equal to 0, the operation continues for the next
logical sector.

'for double density
ID FIELD
IDENTBYTE
FE
FF
FC
FD

)

CYLINDERS
0- 255
256 - 511
512 - 767
768 - 1023

This command allows the user to specify several options.
These options are specified by bits in the command word
and are as follows:
BIT 6 = 1 IMPLIED SEEK DISABLED. The UDC will
not update the CURRENT CYLINDER,
651

CURRENT HEAD OR CURR-ENT
SECTOR register and will not issue step
pulses.
BIT 6 = 0 IMPLIED SEEK ENABLED. The UDS will
update the CURRENT CYLINDER,
CURRENT HEAD and CURRENT
SECTOR reQister and will issue step
pulses if required.
BIT 5 =

ALWAYS 1.

BIT 4 = 1 DELETED DATA MARK. Data will be
written with a Deleted Data Mark (F8 hex)
in the ID field.
BIT 4 = 0 NORMAL DATA MARK. Data will be written with a Normal Data Mark (FB hex) in
the ID field.
BIT 3 = 1 REDUCED WRITE CURRENT. Setting
this bit will cause the UDC's Reduced
Write Current output to go high.
BIT 3 = 0 NORMAL WRITE CURRENT. Resetting
this bit will cause the UDC's Reduced
Write Current output to go low.
Bits 2, 1, and 0 are used to select the Write Precompensation value to be used during writes to floppy
disks. The table below specifies these values.
BIT2

BIT 1

BITO

0

1

0

1
0
1
1
1
0
0

0
1
1
1
0
0
0

1
1
1
0
0
1
0

Precompensation
(For Floppy Disks)
None, enable EARLY and
LATE Outputs
600 nsec, Minifloppy only
500 nsec, Minifloppy only
400 nsec, Minifloppy only
300 nsec
200 nsec
100 nsec
None, suppress EARLY and
LATE Outputs

NOTE: For hard disks, precompensation is handled
with an external delay line, which is Connected to
the EARLY and LATE Outputs of the UDC. These
lines toggle in response to the data pattern being
written to the disk.

WRITE LONG

(R8) bits 6 and 5 to 01. In this mode there is no retry. The
retry counter register (R7) will be used as the ECC check
byte length counter. The 1's complement value of the desired
check byte length plus two should be programmed into
these 4 bits, mapped as follows:
REGISTER?
1111
1110
1101
1100
1011

··
·

ECCLENGTH
2
3
4
5
?

··
·

The system processor then issues the Read Sector Logic
command. Signal ECCTM will not be activated in the WRITE
LONG operation.
Before writing data to the selected disk drive, the UDC will
read the current ID field, step to the desired cylinder (if enabled in command) and verify that it has located the correct
cylinder and sector. (These steps were described previously under "UDC Command Overview").
After the "Verify" sequence is done, the "data transfer"
sequence begins. The UDC will first write either a Data Mark
(FB hex) or Deleted Data Mark (F8 hex) on the disk, as
selected by the user (see below). Then the UDC will transfer a sector's worth of data including the programmed number of ECC bytes using (DMA) for the memory area specified
by the DMA register.
This command allows the user to specify several options.
These options are specified by the bits in the command
word, as follows:
BIT 6 = 1 IMPLIED SEEK DISABLED. The UDCwili
not update the CURRENT CYLINDER,
CURRENT HEAD or CURRENT
SECTOR register and will not issue step
pulses.
BIT 6 = 0 IMPLIED SEEK ENABLE. The UDC will
update the CURRENT CYLINDER,
CURRENT HEAD and CURRENT
SECTOR register and will issue step pulses
if required.
BIT 5 =

ALWAYS 1.

BIT 4 = 1 DELETED DATA MARK. Data will be written with a Deleted Data Mark (F8 hex) in
the ID field.

This command will cause the HDC9234 to transfer one
sector of data and four ECC bytes from the buffer to the
BIT 4 = 0 NORMAL DATA MARK. Data will be writdisk. The system processor must load the following UDC
ten with a Normal Data Mark (FB hex) in
registers:
the ID field.
DESIRED CYLINDER
DESIRED SECTOR
DESIRED HEAD
SECTOR COUNT
BIT 3 = 1 REDUCE WRITE CURRENT. Setting this
DMA 15-8
DMA 7-0
bit will cause the UDC's Reduced Write
DMA 23-16
MODE
Current output to go high.
RETRY COUNT
REGISTER A
(for IBM® PC-AT mode)
BIT 3 = 0 NORMAL WRITE CURRENT. Resetting
WRITE LONP can operate on only one sector per comthis bit will cause the UDC's Reduced Write
mand. The sector slew register should be programmed to
Current output to go low.
1. The value in the retry counter is decremented by the
HDC9234. It should, therefore, be programmed for each
Bits 2, 1, and 0 are used to select the Write PrecompenWrite Long command.
sated value to be used during writes to disks. The table
This mode is enabled by programming the mode register
below specifies these values.
652

BIT2 BIT1 BITO
0

1

0

1
0
1
1
1
0
0

0
1
1
1
0
0
0

1
1
1
0
0
1
0

BIT 3 = 1 REDUCED WRITE CURRENT. Setting
this bit will cause the UDC's Reduced
Write Current output to go high.

Precompensation
(For Floppy Disks)
None, enable EARLY and LATE
Outputs
600 nsec, Minifloppy only
500 nsec, Minifloppy only
400 nsec, Minifloppy only
300 nsec
200 nsec
100 nsec
None, suppress EARLY and LATE
Outputs

BIT 3 =

this bit will cause the UDC's Reduced
Write Current output to go low.

a

Bits 2, 1, and are used to select the Write Precompensation value to be used during writes to floppy
disks. The table below specifies these values.

NOTE: for hard disks, precompensation is handled with an
external delay line, which is connected to the EARLY and
LATE Outputs of the UDC. These lines toggle in response
to the data pattern being written to the disk.

(Hex Values 80 thru 9F,
COthru OF)
This command will cause the UDC to write physically consecutive sectors on the disk. Before issuing this command,
the system processor must load the following UDC registers:
DESIRED SECTOR
DESIRED CYLINDER
DESIRED HEAD
SECTOR COUNT
DMA 7-0
DMA 15-8
MODE
DMA 23-16
RETRY COUNT
REGISTER A (for IBM®
PC-AT Mode)
Since retries during a write command are not valid, the high
order nybble of the RETRY register should be set to 0, in
1's complement format (1111).
Before writing data to the selected disk drive, the UDC will
read the current ID field, step to the desired cylinder (if enabled in command) and verify that it has located the correct
cylinder and sector. (These steps were described previously under "UDC Command Overview").
After the "Verify" sequence is done, the "data transfer"
sequence begins. The UDC will first write either a Data Mark
(FB hex) or Deleted Data Mark (F8 hex) on the disk, as
selected by the user (see below). Then the UDC will transfer a sector's worth of data (using DMA) from the memory
area specified by the DMA registers. After writing out the
sector, CRC or ECC bytes will be written as specified by the
MODE register. Next, the SECTOR COUNT register is decremented, and if not yet equal to 0, the operation continues
for the next physical sector.
This command allows the user to specify several options.
These options are specified by bits in the command word
and are as follows:
BIT 6 = 1 IMPLIED SEEK DISABLED. The UDC will
not update the CURRENT CYLINDER,
CURRENT HEAD or CURRENT
SECTOR register and will not issue step
pulses.

BIT2 BIT1 BITO

WRITE SECTORS PHYSICAL

BIT 1 =

0

0
1
1
1
0
0
0

1
1
1
0
0
1
0

TAPE BACKUP REGISTER DESCRIPTION
The following bits in the UDC's register file assume the
functions listed below when executing the BACK-UP command and should be programmed accordingly.
The following tables describe the differences in register
usage when the UDC is executing the TAPE BACKUP
command. (Complete TAPE BACKUP register bit maps are
located in rear of the data sheet.)

a IMPLIED SEEK ENABLED. TheUDCwili

ALWAYS O.

a NORMAL DATA MARK. Data will be writ-

1

1
0
1
1
1
0
0

TAPE BACK-UP
(Hex Values = 08 to OF)
The TAPE BACK-UP command set provides the system with
the capability of transferring data to and from a tape drive
in continuous blocks. TAPE BACK-UP utilizes the UDC's
DMA, data conversion, error detection/correction and sector count circuitry.
Because of the mechanical and electronic differences
between tape drives and disk drives, some of the register
bits described earlier in this data sheet change functions
when the UDC is executing the TAPE BACKUP COMMAND. In many cases, the CLK input to the UDC will also
need to be changed to compensate for the slower data rate
from tape drives.

BIT 4 = 1 DELETED DATA MARK. Data will be
written with a Deleted Data Mark (F8 hex)
in the ID field.
BIT 4 =

0

Precompensation
(For Floppy Disks)
None, enable EARLY and LATE
Outputs
600 nsec, Minifloppy only
500 nsec, Minifloppy only
400 nsec, Minifloppy only
300 nsec
200 nsec
100 nsec
None, suppress EARLY and LATE
Outputs

NOTE: for hard disks, precompensation is handled with an
external delay line, which is connected to the EARLY and
LATE Outputs of the UDC. These lines toggle in response
to the data pattern being written to the disk.

update the CURRENT CYLINDER,
CURRENT HEAD and CURRENT
SECTOR re!;lister and will issue step
pulses if required.

BIT 5 =

a NORMAL WRITE CURRENT. Resetting

ten with a Normal Data Mark (FB hex) in
the ID field.
653

MODE REGISTER
Bit 2 = 1 16 byte sync detect delay enable
= 0 16 byte sync detect delay disabled
Bit 1 = 1 TAPE BACKUP Write Enable (writing)
= 0 TAPE BACKUP Write Disable (reading)
Bit 0 = 1 Tape mark enable (short block)
= 0 Tape mark disable (long block)
RETRY COUNT REGISTER
Bits 7-4 Retry' should be disabled, by setting these bits to
"1 n. (Retry Disabled)
Bits 3-0 program outputs (user controlled) Bit 3 is typically
used for write enable to the tape drive.
Bits 0 and 1 are typically used for tape driven
motion control as per drive manufacturer's
specification.

DESIRED CYLINDER
Bits 7-4ECC Type Field:
DB7 DB6 DB5 DB4
ECCTYPE

o

o

o

o

4 ECC bytes generatedl
checked
5 ECC bytes generatedl
checked
o
6 ECC bytes generatedl
checked
7 ECC bytes generatedl
o
checked
note: 5, 6, 7 byte ECCs are generated and checked by
hardware external to the UDC.
DESIRED CYLINDER
Bit3
Always 1
Bits 2-0
Data Block Size:
DB2 DB1 DBO DATA BLOCK SIZE
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

128 bytes
256 bytes
512 b&tes
1024 ytes
2048 bytes
4096 bytes
8192 bytes
16,384 bytes

0
1
0
1
0
1
0
1

Remember that the UDC internal ECC code can correct up
to a 4K byte long Data Block, but that the larger the Data
Block the greater the probability of a miscorrection.
Also, when executing the TAPE BACKUP command, the
DRIVE SELECT command is altered slightly, as illustrated
below:
DRIVE SELECT COMMAND
Bit#
7 6 5
4
Drive
Select
DB2

o
1

0

0

Ramp Up/Down
delay enable

3

2
ClK
divisor

o
a

CLOCK DIVISOR FOR TAPE
ClK is divided by 10 (similar to 8" flop,py divisor).
elK is divided by 20 (Similar to 5.25' floppy divisor).

These bits, in conjunction with Bits 4 and 7 of the MODE
register, will allow selection of both FM and MFM recording
on tape, with a tape format that resembles IBM compatible
floppy disk formats.
Setting the Drive Type bits to 1,0 or 1 ,1 will also cause the
UDC to take on the following cnaracteristics:
-DMA mechanism transfers a byte (8 bits) and relinquishes the bus.
-The RDGATE and WRGATE output signals have timing
characteristics as shown in Figures 12A and 12B of the
UDCspec.
-The gap lengths are as illustrated in Table 1 or the UDC
spec.
-Tape format parameters will be as per Table 1 of the UDC
spec.

Read and Write functions of TAPE BACKUP share a common command byte. The three lSB's of the MODE register
are also used by the TAPE BACKUP command to specify
user options, and to select between tape read or tape write
mode.
Two kinds of blocks may be specified when reading or writing dependent on the state of the TAPE MARK ENABLE bit
in the MODE register:
1. DATA BLOCK. The length of the data block (also
called a long block) is equal to:
2 n* 128 bytes where n is an integer
between 0 and 7 inclusive. The
desired length of the data block (2n)
is programmed into the desired cylinder register.
2. TAPE MARK. The minimum length of the tape
mark (also called a short block) is 3
bytes. The maximum length of the
tape mark is 257 bytes. The desired
length is pro!;lrammed into the sector count register.
Multiple data block transfers are accomplished by programming the 1's complement of the desired number of data
blocks to be transferred into the sector count register.
The three lSB's of the MODE register function as part of
the BACK-UP command word. The WRITE ENABLE bit
determines whether loading the BACK-UP command into
the UDC will initiate execution of a BACK-UP READ or
BACK-UP WRITE sequence. The TAPE MARK ENABLE
bit determines whether the UDC will write a short or long
block of data on the tape and the DELAY ENABLE bit determines whether or not the RDGATE signal is stretched when
it coincides with a sync mark when reading the tape. The
remaining bits in the command word are as follows:
COMMAND DB7 DB6 DB5 DB4 DB3 DB2 DB1
DBa
BACK-UP
a
0
a
0
0
a
xfer
(READING)
enable
o
a
a
o
BACK-UP
precomp value
(WRITING)
BACK-UP READ
When reading a short block, only CRC is checked. When
reading a long block, CRC or ECC will be checked, depending on the CRC/ECC bits in the Mode register.
Bit 0 = 1 Data transfer enabled, error checking enabled
= 0 Data transfer disabled, error checking enabled
BACK-UP WRITE
When writing, the precompensation value is derived from
the ClK frequency as follows:
Bit 2

Bit 1
Bit 0 Precompensation
1
0
None, enable EARLY and lATE
0
1
6 ClK cycle periods
1
1
5 ClK cycle periods
1
1
1
4 ClK cycle periods
a
3 ClK cycle periods
1
1
0
a
2 ClK cycle periods
1
a
a
1
1 ClK cycle period
a
a
a
None, suppress EARLY and lATE
PRECOMPENSATION SELECT FOR BACK-UP COMMAND

o
1
o

COMMAND EXECUTION OVERVIEW
The tape backup command allows the user a convenient
method of backin~ up either floppy or hard disks to tape.
TAPE BACKUP SYSTEM CONFIGURATION NOTES
The UDC may be Interfaced to either cartridge or cassette
(A schematic showing a typical system implementation
type tape drives, working in either streaming or start/stop
using the TAPE BACKUP feature is contained in Schemode.
matic Diagram 2.)
654

When controlling a start/stop tape drive, the UDC will
write the data "block by block". The system will issue
a Drive Select command to the UDC with the Tape
Motion, Motor On and Write Enable bits set to start
and write data to the tape.
Th'e UDC will interrupt the system after the completion of the Ramp Up Delay indicating that the tape drive
is up to speed. This interrupt is distinguished by the
Command Termination Code of 0-0 (normal completion of command).
The System then outputs the Write command (for a
long or short block) and waits for the command termination interrupt. The UDC will write the Sync mark
and tape mark or data block on the tape.
When the System receives the interrupt indicating
completion of the Write command, it will issue another
drive select command with the Motor On and Write
Enable bits set to stop the drive. The UDC will interrupt the system after completion of the Ramp Down
Delay indicating that the tape has stopped moving.
The'UDC will turn the Write Gate signal on when it is
writing data and off when it is not, without regard to
the tape motion. The Write Gate signal is used to generate "gaps" on the tape between the data blocks. This
is done by externally forcing the two Data outputs with
the Write Gate signal such that the Data + signal is
high and the Data - signal is low when the UDC is
not writing data to the tape (Write Gate is off):

1. Proper operation of the TAPE BACKUP command
requires that the tape drive be addressed as DRIVE #3
by the UDC.
2. During the UDC's OUTPUT 2 period external circuitry
must enable a separate latch to receive the user defined
10 bits and tape track number bits. This latch should
use the DRIVE SELECT 3 signal (output during the
OUTPUT 2 period) so that the contents of the latch may
only be changed when the tape drive is selected.
Four additional drive control signals may be loaded into
the four lSB's of the RETRY COUNT register. These
additional outputs are latched externally during OUTPUT 1 times for use by the tape drive. These outputs
would normally be used to control tape drive Write Enable logic (bit 3) and tape motion (bits 0 and 1), and tape
motor on and off (bit 2).
3. It is important to consider the time required for a tape
drive to come up to operating speed when using the
TAPE BACKUP command. Also, to insure adequate
spacing between tape blocks, a delay is frequently
required before stopping tape motion. The UDC has a
programmable Ramp Up and Ramp Down timer to allow
for easier implementation. The desired delay is programmed into the DATA/DELAY register before issuing
the DRIVE SELECT "3" command.

CLOCK
DIVISOR
BIT
1
1
0
0

DENSITY BIT
MODE
REGISTER
TIME IN SECONDS PER
BIT4
DELAY REGISTER COUNT
1 ClK Cycle * 80000
1 ~Single)
o Double)
1 ClK Cycle * 40000
1 (Single)
1 ClK Cycle * 40000
o(Double)
1 ClK Cycle * 20000

[DRIVE STOPPED

[DRIVE STOPPED

I

GAP

TAPE MARK ANDIOR DATA BLOCK

I

GAP

IL.___

WRITE GATE:

LJ

The UDC will issue a normal interrupt (with the command termination code set to 0-0) when the RAMP UP
or RAMP DOWN timer has expired.
TAPE SPEED:

4. BACK-UP WRITE. The user will first request the UDC
to perform a disk READ TRACK command, with the
TRANSFER ENABLE bit in the command word reset.
This will cause the UDC to transfer only the ID field
information to memory.
The TAPE BACKUP command will then be issued
causing the UDC to write this ID information to the tape
as a tape mark (typically 96 bytes for a drive formatted
with a 3 byte/sector ID field or 128 bytes for a drive formatted with a four byte/sector ID field. The data fields
should then be transferred to the tape in a similar
manner.
The UDC may be used with either "Streaming" or "Start/
Stop" type tape drives. This is illustrated by the following examples:

STOPPED

/

TAPE AT SPEED
RAMP UP DELAY

SL

DRIVE SEL
1. tape motion on
2. write enable on
(write) or off

BACKUP
1. read or write
2. long or short block

\
-

STOPPED
RAMP DOWN DELAY

L

DRIVESEL
1. tape motion off
2. write enable off
(write or read)

(read)

B. STREAMING TAPE DRIVE:
typically transfers 1 sector at a time as illustrated
by the following flow chart:
START TAPE DRIVE

A. START/STOP TAPE DRIVE:
typically transfers % or 1 disk track at a time as illustrated by the following flow chart:

READ DATA FROM DISK TO MEMORY
WRITE BLOCK FROM MEMORY TO TAPE

READ DATA FROM DISK TO MEMORY

STOP TAPE DRIVE

START TAPE DRIVE

Control of a streaming tape drive is similar to that of a
start/stop drive. The tape is started at the beginning
of tile data transfer and stopped after the last block is
written to the tape. The tape is not stopped in between
blocks. The UDC will however turn the Write Gate sig-

WRITE BLOCK FROM MEMORY TO TAPE
STOP TAPE DRIVE

655

;
Ii

DIP
101M

ADDle

AOD9
ADDS

ADD7
AOD6

ADDS
ADD4
AOD3

MEMORY SELECT

LS32

~

ADD15
;:::::::
ADD14
ADD13 [ ::>----""""1 LS244
ADD12
ADD1l

L_s

EN

:::---........

1-----1 A 6~.....:-:
1-----1 ~ _ : L~-"---b-~-:"'"
A til 6 ~I_--,,+
• ·--~O-.,......

==
=
0_-----1 V""
~ .....
t:::::-::A
___ til 6"":;- -tv

-

:::::

1---""1 A

T

E E

AOo.

ADD1
ADD0

E

,10MH.

~~1-

"'

~~~-~-----""1
MADS
MAD7

MADS
MA05
LS244 ~_ _--'~~
MAD4
MAC3
MAD2
MA01
MAD0

=

+6V

v

Ft=::~

:

MA07
~

.~

A t(l 6

:=

'1~t:=:t:=====l
MADS
L
MA04
MA03

a

0

<

LS74

+5V

1

~~------1g~ D~::t::t::~

LS244

oc C~
1-+------106
611--+-+-.....,
~4-----~aA

A,I-+-~~

LS161<1--t--

Lp-

MAD2
MADf
MADIJ

tf

E

DIP

c"o-

'--- aD DI-+---+---1
'---- ac cl-+--+-~

'---_00
L---""""1aA

DIP

6'~~-+--1

A'I-+-~~y.

L~161 -

~ 'i/ LS245

I

L

LS04

DIP

DAT7 C::>---....I

DAT6~~===~J
DAT5
[

~ ~ = ~ = Lfrr1-LS_27--oL---

L...:=

A'

:~~;:::

~

LSr;:,

7406

SYSCLK
RESET

656

:=====================~l

r - DRIVE STATUS
""'~:"~:---l
t-- INDEX
LS240'

,..AB2

~ ~r-_+-W!Y.tl!RI~TE!.!P~R~or~EC"T_ _ _ _ _-+++______1 WR PROT

"'A~B~3t:=~ ..-<:1

-

-

--

-

AB7
AB6
AB5
AB4
AB3
AB2
ABl
AOO

lOX
TRK00

~~=,Bs!:---I
ABl

~:~~ 0~PLETE

~------l olR

READY

AB0

WRITE FAULT

,

~
LS32

-

AS7
AS6
AB
AB4
AB3
AB2
Aa,
AS0

OUTPUT 1

0
0
0

a
LS374
0
a
a
a

_ _ _ _-; STEP

,----;WG
r---"'""IWoATA
r - - RoATA

.r~~~o

LS04-

oASELl

_

5RSW

~

oASELl

MOTQRON
SINGLE DENSITY

lOX
SEEKCOMP
TRK000
WRFLT

HDC9234

READY
ORSEL1

OUTPUT 2

""A""B7++-Ir;;-

-

""
~AB6
t*~:~:~:t:~~LS37~'I--_"'::;~""""""_---1
a

REo.WR.CUR
LOW CUR
olR
VOlA
STEP
Q l Vi i l lSTEP

0

DIP

"",A~B34-+--l 0
I"'A",B2'+-+--lO

~~:'~1+-t-1D

--ccs
c/D

v"~~~

:Lr
~:'38E~b
L..k
81

-

OB7
OB6
OBS
oB4
OB3
OB2
oBl

-

000

-

oMAR

r--=--

C

B

07

HEAD BIT 1
HEAOBIT0

al--~~="'----I

1

~S'T~B3~+

~

"

HEAD 23

V

HEAD 2'
HEAD 2-

HEADZZ

"

T

l.r- ~
WG

GNo

T7408

__
_ _ _-++_. . .
021>---i~~~o;~2"1-1f----t-'
01 t:=::jS~T~B0t:~_ _ _J

WGA::~t---~
WDATA

a

-J-=~t-1D

+5V

i.-"":

HEAOBIT3

HEAD BIT 2
QII---";;'~~~---1

Lr

Lr-C1 8153

DELAY

2 4 n s L - C2

~~

~~

.-----<..

=--.J

~~~-~-+-r--I+MFM
[1004
R'::~MoATA

.A9637 .......

-

ACK

-

oMACLK

I 10MHzCLKJ

~2C2-

--c RST

RDATA i > - - - - - - - - - - - - - " " " ' 1 2 V 2Cl -

~-----------~lV lC3-

-

lCl
lC0

R/iN

HODATA

-

RDATA

~J.:.:R:;::CL:.:.K---~
RAW

r-- I -

J~DATA
IRCLK

FDC9216

-

INT

ORSELl

I r~G_N_D.....,=...
Ii- ~

SEPARATOR

r---

RCLK..

_55

WRITE DATA

~,..4/::""---++--I-MFM

~r~

LATE
EARLY

+MFM

,----------------1"'-

~C0 Yr

1

":"

BMHzCLK

657

J

RDf:==========::::::J

CO~0~
COt

q

nal on when it is writing data and off when it is not so
that gaps will be written (with external hardware) on
the tape between the data blocks.
5. BACK-UP READ. The data is read from the tape (in
either start/stop or streamer mode) and buffered in
memory. The disk track is then reconstructed from
the data.
The start/stop drive typically has a track (or half a track)
of disk data stored as a block. It is therefore expedient
to read in the data "block by block". When reading data
from a streamer drive use can be made of the SECTOR
COUNT register and a track's worth of data blocksmay
be read from the tape before generating the track on
the disk.
Tape motion control is similar to that described above
except that the Write Enable Bit is off to inhibit writing to
the tape. The UDC reads the tape until it detects a sync
mark. After detecting a sync mark the UDC will transfer
the data found on the tape to memory.
6. The search count is used when reading the tape. It
specifies a maximum number of blocks of 128 bytes
between adjacent data blocks. If the search count
expires before sync is detected, the command is
terminated.
For example, if a search count of two is specified by
loading the Desired Sector ref.lister with FD (hex), the
UDC will search for 256 byte times before terminating
the command. This will prevent the UDC from accidentally skipping a block. The search count is typically about
the size of one block length. In the following figure, TM1
and TM2 are two tape marks and DB1, DB2, DB3 etc.
are their associated Data Blocks:
TM1

f-----I

DBt

f-----I.

DB2

I---l

DB3

-

I---l

DB4

f-----I

TM2

t-----l

8. The DRIVE STATUS bits may be used b the tape drive
if they are enabled (on the drive) by DRI E SELECT 3.
The ready change interrupt is especially handy for
detecting start of tape (SOT) and end of tape (EOT) as
a UDC command can be terminated by a change in state
of the READY input.
9. The DATA FORMAT is as follows:
~SYNC

The sync mark is preceeded by a "preamble" consisting of bytes of 00 as per figure 2 of the UDC spec (this
is required to synchronize the data separator when
reading the tape). The Tape Mark and Data Block
(including CRC or ECC bytes) are followed by a "postamble" consisting of one byte of 00.
Note that the postamble is not included in the Floppy
Disk formats. The GAP sizes are dependent on the type
of drive (start/stop or streamer) and the specific
mechanical tape drive specifications.
10. Use can be made of the Sector Count register when
doing a "file" (versus a "mirror image") backup on a
start/stop tape drive. Instead of transferring the entire
disk track to the tape in one long block, the data is moved
file byfile.
If, for example, it is desired to back up a file consisting
of five 256 byte long Hard Disk sectors, a 2048 byte long
Data Block would have to be used for an image backup
(the Data Block size is specified as 2n * 128 restricting
blocks to 128, 256, 512 etc.). This would result in a lot
of wasted space on the tape.

DBt

I---l

7. 16 BYTE DELAY. Provision is made to shift the RDGATE
pulse in the event that it coincides with the data block
sync mark. If a tape cannot be read (sync is never
detected) the tape can be re-read with the 16 byte delay
enabled.
GAP

Isync

DATA

I

The Tape Mark sy'nc mark (TMSYNC) is composed of
three bytes of A1 (Hex) followed by one byte of FE (Hex).
The Data Block sync mark (DBSYNC) is composed of
three bytes of A1 (Hex) followed by one byte of FB (Hex).
A1 (Hex) is encoded with the standard missing clock
pattern.

search count

DATA

TAPE MARK POST GAP PRE DBSYNC DATA BLOCK POST GAP

If file backup is used and the Sector Count is set to five,
256 byte long Data Blocks can be used. Gaps will be
generated on the tape corresponding to the time
required to get the data from the disk drive (corresponding to DMA delays and the disk interleave factor).

GAP

ROGATE without delay:

The tape will not be stopped until the entire file is transferred. When using sector count, the UDC internal programming will create inter-block gaps of about 30 to 32
bytes on the tape in both single (FM) and double (MFM)
density modes.

RDGATE with delay:

658

SYSTEM CONFIGURATION NOTES
A simplified UDC schematic is shown in Schematic 1. The
following notes may be helpful in implementation ofthe UDC.
1. In systems using a private memory area, it is important
to know when the buffer needs servicing from the host
processor. A second interrupt signal (INT2) signals the
processor that servicing is needed. INT2 is generated by
externally ANDING the ECCTM signal with STB1 signal.
(The STB1 signal is active when the UDC~utputing
the DMA address data, and occurs when STB is active
(low), SO is active (high) and S1 is inactive (low)).
This "interrupt" occurs only when the UDC needs the
system processor to either read from or write to the buffer
memory. When reading from the disk, the system processor should empty the memory buffer each time this
signal becomes active. (If an ECC error is detected, and
error correction is enabled, this signal will not become
active until the UDC has attempted to correct the error.)
When writing data to the disk, the system processor must
fill the buffer each time this signal becomes active.
2. The DIP (DMA in Progress) signal is used to isolate the
buffer memory from the main system memory. If 74LS244
and 74LS245 address buffers are used in the memory
addressing circuits, then this signal should be used to
enable or disable the address buffers, as required. This
eliminates the possibility of memory contention problems.,
3. Write precompensation (for floppy disks) is handled
internally by the UDC, For hard disks, the LATE and
EARLY signals are connected to a multiplexer which, in
turn is connected to a 24 ns delay line. The EARLY and
LATE signals will toggle in response to the data pattern
being written. This will allow the data being written to the
shifted ± 12 ns from the nominal 12 ns delay specified
by hard disk manufacturers.
4. The interface to the hard disk drive data inputs and outputs requires RS-422 data tranceivers, Other disk drive
interface circuits (including floppy disk data inputs and
outputs) may be 74LS series devices.
5. Since the UDC uses its Aux Bus for multiple functions,
the system designer must be able to determine which
function is occuring on the Aux Bus at any given time.
The SO and S 1 signals, when combined with STB signal
are decoded (using a 74LS138 or equivalent) to provide
STBO-3 signals.
These generated signals and their respective functions
are:
STBO
STB1
STB2
STB3

Drive Status Input Time Slot
External DMA Address Counters Time Slot
Output 1 Time Slot
Output 2 Time Slot

6. The clocks required by the UDC are not TTL-level compatible. Pullup resistors (typically 390 ohms) should be
used with Schottky drivers to insure that the clock signals
reach the proper rnput (high) level, with acceptable rise
and fall times.
7. The UDC features a built-in DMA controller that requires
connection to external counters. These counters are
configured so that they are incremented after each byte
is transferred. (The UDC's internal DMA circuits transfer
659

the starting memory address for each read or write operation.) 74LS161 Counters are typically used in this area.
8. The DMACLK input should be tied to the master system
clock, through a bus buffer. It is important to remember
that three DMACLK periods are required for each DMA
transfer.
9. The system deSign may be simplified, and costs reduced,
by using the FDC 9216B Floppy Disk Data Separator, to
separate raw data from the floppy disk drive into RDATA
and RCLK.

ERROR CHECKING AND CORRECTION CIRCUIT (ECC)
OPERATING PRINCIPLES
The UDC will automatically detect and correct errors in the
data read from the disk. Error checking may be done using
industry standard CRC or ECC encoding. Error correction
may be done using either internal or external ECC encoding. This section will explain ECC operation, as implemented on the UDC.
The UDC contains two 16-bit registers used by the CRC/
ECC circuits. CRC logic uses only one of these registers,
while the logic for ECC uses both registers, implementing
a full 32-bit algorithm.
These registers may be preset to either one or zero, using
the CRC PRESET bit in the INTERRUPT/COMMAND
TERMINATION register. (This allows compatibility with
existing disk controllers and external ECC chips.) Both ECC
and CRC are calculated beginning with the sync mark of
the address (CRC) or data (ECC) field.

CRC/ECC GENERATION
The UDC uses the following industry standard polynornials
in computing the CRC and ECC check bytes:
CRC: X'6 +X'2 +xs + 1
ECC: X32 +X2B +X 26 +X'9 +x17 +x'O +X6 +X2 +'
As the UDC writes data to the disk drive, it first passes this
data thru the CRC (and, if enabled, ECC) registers. After all
data has been written, the remaining two (CRC) or four
(ECC) bytes remaining in these registers are written to the
appropriate address or data field.

CRC/ECC CHECKING
When CRC or ECC checking is initiated, the internal CRC/
ECC registers are set to either zero or one, as required by
the CRC PRESET bit in the INTERRUPT/COMMAND
TERMINATION REGISTER. Data read from the disk is
simultaneously shifted thru the CRC/ECC registers, and
transferred to external memory.
After the CRC or ECC check bytes have been shifted thru
the CRC/ECC registers, the remainder in these registers
should be zero, else an error has occurred in the address
or data block.
If CRC or ECC (without correction) is enabled, automatic
retry (if enabled) or command termination will occur. If internal ECC with automatic correction is enabled, the correction algorithm will be executed. If the internal ECC algorithm
is unable to correct the error (in one attempt), then autornatic retry (if enabled) or command termination will occur.

ECC CORRECTION

Error Correction consists of three distinct parts:
1. The CRC/ECC registers are normalized by shifting zeros
thru the register. This sets up a data block which is 42,987
bits long, which corresponds to the "natural message
length" of the generation polynomial. The actual number
of zeros shifted through the registers depends on the difference between the natural message length of the generator polynomial and the actual length of the data block
being checked. The longest data block that can be corrected (using the internal ECC algorithm) is 4K bytes.
2. The data input to the CRC/ECC registers is then disabled and the DMA counters are re-initialized to the
starting address for this data block. The contents of the
CRC/ECC registers are then "ring-shifted" until 21 consecutive zeros are detected. The remaining bits in the
CRC/ECC registers compose the error syndrome. As the
CRC/ECC rellisters are shifted, the UDC generates DS
signals, causing the external DMA counters to be incremented. When the 21 consecutive zeros are detected,
the DMA counters are pointing to the corrupt data.
If the error syndrome is not found within the data block
the error is judged to be uncorrectable and the correction
algorithm is terminated. (The data block is the length of
the data field in the sector and the 4 ECC bytes. A format
with a sector size of 256 bytes would have a data block
size of 260 bytes.)
3. When the error syndrome is detected, the UDC will enable its ECCTM output, read the next byte from memory,
exclusive-or it with the first b~te of the three byte error
syndrome, disable the ECCT output and write the cor-

rected byte back to memory. The correction process is
then repeated for the next two bytes in memory.
When using internal ECC (with correction enabled), the
ECCTM output is used by the external DMA counters to
inhibit the counters from incrementing their addresses
when correCtin~the erroneous bytes. When using external ECC, the E CTM output goes active (low) when the
UDC is requesting the ECC Check Bytes from the external ECC chip prior to writing them to the disk.
After a correction is completed, the UDC will then attempt
to read the next sector on the disk (if the SECTOR
COUNT register is still greater than zero). Anytime ECC
correction has been attempted, (even if unsuccessful),
the CORRECTION ATTEMPTED bit in the CHIP STATUS register will be set.
The maximum time required for one ECC Correction Cycle
(using the internal algorithm) is about equal to the time it
takes to read 1 sector.

IMPLEMENTATION

Implementing ECC Correction consists of three steps:
1. Read with Auto-Correction disabled and Retry enabled.
2. When a sector with a hard ECC error is found, enable
Read for one sector (sector count = 1) with AutoCorrection enabled and correct the error.
3. After the correction is completed, issue a new Read
command with auto-correction disabled and retry disabled to transfer the balance of the data.

660

MAXIMUM GUARANTEED RATINGS·

Operating Temperature Range ............................................................................. 0 to + 70 C
Shortage Temperature Range ....................................................................... - 55 C to + 150 C
Lead Temperature (soldering, 10 sec.) ........................................................................ + 325 C
Positive Voltage on any Pin, with respect to ground .............................................................. + 8 V
Negative Voltage on any Pin, with respect to ground ........................................................... - 0.3 V
·Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this
specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches"
on their outputs when the AC power is switched off. In addition, voltage transients on the AC power line may appear
on the DC output. If this possibility exists it is suggested that a clamp circuit be used.

DC ELECTRICAL CHARACTERISTICS Ta = 0 C to

Vi1
Vih1
Vih2
V011
Voh1

PARAMETER
Input Voltage
Low
High
High
Output Voltage
Low
High

V012
Voh2

Low
High

MIN

TYP

UNIT

0.8

V
V
V

0.4

V
V

0.4

V
V

2.4
2.4

I

1ltIomS/rfc u:::.'~

MAX

2.0
4.2

~
SomeIVoJice, 11>1.,.

+ 70 C, Vcc = 5.0V ± 5%

COMMENTS

all inputs except CLK
CLKinput
all outputs except WDATA,
Early and Late. (Drive 1
TTL load into 50 pf)
WDATA, EARLY and LATE
outputs. (Will drive 1
Schottky load into 15 pf.)

Input Leakage Current
11

10

uA

25
200

pf

Input Capacitance
Cin
Power Supply Current
Icc

ma

AC ELECTRICAL CHARACTERISTICS Ta = 0 C to

PARAMETER

+ 70 C, Vcc = 5.0V ± 5%

SYMBOL

MIN

TYP

MAX

UNIT

COMMENTS

PROCESSOR WRITE CYCLE
C/Q, R/iiil, CS Setup time to DS1
C/D, R/W, CS Hold time to DSj
DS Pulse Width
DS Pulse Hi~h Time
Data Bus In etup time to DSj
Data Bus In Hold time to DSj

TosB
TosB
TosL
TosH
TOIB
TOIA

110
0
150
850
100
0

ns
ns
ns
ns
ns
ns

FIGURE3

PROCESSOR READ CYCLE
Data Access time from DS1
Data Hold time from DSj

TooB
ToOA

75
10

ns
ns

FIGURE3

UDC TO MEMORY TIMING
(BUS MASTER)
(based on 10 Mhz DMACLK Input)
Write Setup time to DS~
Write Data Strobe Widt
Write Hold time from DSj
Data Strobe Falling Edge
Data Strobe Rising Ed9L
Write Data Valid before DS~
Write Data Hold time after Sj
Memory Access Time

TWB
Twos
TWA
TosF
TosR
TwoB
TwoA
Tw

110
180
110

ns
ns
ns
ns
ns
ns
ns
ns

FIGURE4

15
20
90

10
200
661

"

~

PARAMETER

SYMBOL

Read Setup time to D~
Read Hold time after 0
Read Data Strobe Pulse idth
Read Data Setup time to D~
Read Data Hold time from 0 i
DMACLKf to OS
DMACLK to DSr

tv

t

TRB
TRA
TRos
TRoB
TRDA

TO~~

MIN

TYP

MAX

UNIT

FIGURE4

100
100

ns
ns
ns
ns
ns
ns
ns

FIGURE7

100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

FIGURE2

FIGURE 9

110
110
180
50
0

TODA

COMMENTS

SO, S1, AND STB TIMING
STBWidth
SO, S1 Hold time after STBi
Data In Setup time to STB~
Data In Hold time after ST i
SO, S1 Setup time to
Aux Bus Setup time to S~
Aux Bus Hold time after ST i

Tsw
Tso
To1s
TOIH
TSST1
TssT2
TssT3

INPUT CLOCK TIMING (10 MHz Input)
Clock Rise Time
Clock Fall Time
Clock Cycle High Time
Clock Cycle Low Time
Clock Cycle Time

TRT
TRF
TCH
TCl
Tevc

40
40
95

TpB

0

ns

TpB

50

ns

FLOPPY INPUT DATA TIMING
Window Setup time to RDCLK
Window Hold time from RDDATA i

TFRB
TFRA

50
50

ns
ns

FIGURE 10

HARD DISK INPUT DATA TIMING
Data Setup time to RDCLK!
Data Hold time after RDCLK!
Clock Setup time to RDCLKf
Clock Hold time from RCLK

THRB
THRA
THcB
THCA

60
10
60
10

ns
ns
ns
ns

FIGURE 10

ECCTIM TIMING
ECCTM Setup to D~
ECCTM Hold after 0 i

TEos
TEoH

50
100

ns

1

ILS

sm

PRECOMPENSATION TIMING
Early, Late Setup time
(Before WDATA j)
Early, Late Hold Time
(after WDATA1)

RESET TIMING
RST Pulse Width

800
100
700
0
100
100

10
10

662

100

105

FIGURE 10

AB0-7
DISK DRIVE
STATUS

OUTPUT 1
'REQUIRED
FOR STANDARD
UDC/HARD DISK
INTERFACE

D
•

••
•

Q t---::";";';:;':;::~""'-1- DRSEL3
TAPE DRIVE
STATUS

LS374

OUTPUT 2

D

Q

} TAPE MOTION CTL

DRSEL3

LS374~__~~+-

__4-~~~__~

4

WRITE ENABLE
TRACK #

1\
STB2 -~+--------'--'I----t--q
STB3
STB0

WGATE----------------________~

DATA +
WD----------~

DATA LS74

SCHEMATIC 2: HDC9234 TAPE DRIVE INTERFACE CIRCUIT

663

t+
~

5V

I+----T,~---~

3900

------1f'......>c>------L----

V'"

74504

TO CLK INPUT
or DMACK
INPUT

or
equivalent

FIGURE #1

RECOMMENDED CLK DRIVER CIRCUIT

FIGURE 1: RECOMMENDED CLK/DMACLK INPUT

cs·

FIGURE 2: INPUT CLOCK TIMING (10MHz)

l

I

\

I

R/W

\

~

c/o

X

58
Too,

TOSH

TOIA

TOIB

,~H
VALID
OUT

DB7-0

FIGURE 3

FIGURE 3: SYSTEM PROCESSOR TO UDC TIMING

--Tw---I'I

1+-1.

RNi

T""1

r--

~-+----I~Ir-~T"_ _

r-~T.. - - - - - - - - : - - T..
---1J

DB7-0
(WRITES)

DB7-0
(READS)

FIGURE 4: UDC TO MEMORY TIMING (BUS MASTER)

664

DMACLK

~

DMAR

I

"

I
ACK

,,

~

,I
I

\
\

I
I

1

1
\

\

I

('I

~

I

DIP

L

,

I
I

I
I

I
BYTE
READY

,,

I

U //Iii/

\
\

I\.

I,
TRISTATE I

R/W

" ~..:.T;.:;RI::;ST;.:.A;.:.JE=-_ _

\
\

I

\
\

1
\

\

TRISTATE

55

TRISTATE
\

I

DB 7·0

-------«~~~
~

r--

.•

DATA OUT

MAX BYTE RATE 1.6,,"0

-1

,

---8UDC DMA MEMORY TIMING FOR HARD DISK
(BURST MODE)

Figure 5

FIGURE 5: UDC DMA MEMORY TIMING FOR HARD DISK (BURST MODE)

DMACLK
I

I
I

BYTE READY

-LL.f.j~

DMAR
I

~

ACK
R/W

TRISTATE

,
\

TRISTATE

DIP
DB7·0
(OUT)
DB7·0
(IN)

U

\

\)
,

I
1

~

I

" ........ \,

I
I

______-JJ.

I

j

1
\
I

I

Y

t

,

i

,

DATA OUT I

(

t

DATA IN

)-

1

..'

\._\

000

tr\
TRISTATE
TRISTATE

\
\

Q

>-UDC DMA TIMING FOR
FLOPPY DISK (1 BYTE AT A TIME)

FIGURE 6: UDC DMA TIMING FOR FLOPPY DISK (1 BYTE AT A TIME)

665

81,80

AS 7-0

FIGURE 7: 50, 51, 5TB TIMING

BIT

17161S141312111017161S14131211101

ClK
WDATA

o

r-

o

MISSING CLOCK

.

o '0
0
1
1
1
....------" ADDRESS MARK----~-·_1I...· - - - - - - -

o

-;I

DATA " F E " - - - - - -......

FIGURE 8: UDC DATA WRITE TIMING

TWR

-

WDATA

1\
~TWB

I+-TWA -

>

EARLY,
LATE

ti"'"

'>(
T

DRIVE TYPE
HARD DISK
8" MFM FLOPPY
8"FMFlOPPY
Sv.' MFM FLOPPY
Sv.' FM FLOPPY

T(typ)
200NS
21'-5

41'-5

-

TWR(typ)
lOONS
300NS
300NS
300NS
300NS

FIGURE 9: PRECOMPEN5ATION TIMING

666

I

DATA
BIT

I

0

0

I

0

I

1

I

r-I..
- - - - - - ADDRESS MARK

_I

~----- A1, 0A COMPARE - - -_ _---j

L

o

I I
0

MFM
READ DATA

READ CLOCK

RDATA

INTERNAL
COMPARE

ECCTM

SYN-C-B-Y-TE---r~

RDCLK

RDDATA

~FLUX

REVERSAL

FLOPPY INPUT DATA TIMING
(HARD DISK BIT = 0)

HARD DISK INPUT DATA TIMING
(HARD DISK BIT = 1)
FIGURE 10

r. .

n I~_ _ _ _ _~·_____________
---------REPEATED
N T I M E S - - - - - - - - - - I ________~
~~__________~~
·1

IN DEX~

I

!2t:c~! ~~H~t"Cl! ~~!FEH ~! ~! ~! g ~ 1?~:F$!~~~g! ~!I
~
~
L
INDEX AM

10 AM

12Bdatabyte,

ICRCtl CRC2

GAP 3

27-FF

rL

I

I

GAP 4

247xFF NOMINAL

DATA AM

-

FLOPPY DISK FORMAT; SINGLE DENSITY

ECCTM
2

bytes

INDE~~______________~I_..._·======================_R_E_P_EA_T_E_D_N_T_I_M_ES_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_~_.jl~______~nL

I

01 SYNC
12)(00 !3XC2!FC!

GAP
80x4E

L

GAP
50x4E1

INDEX AM

I

SYNC
12)(00

13XA1 !FE !TKISIDElsECISIZEICRC1! CRC21

L

21 SYNC
12xOO 1 3XA1 ! ~~
Fa I

GAP
22x4E

L

10 AM

256 data bytes

F~

r..·..-------------

n

!

GIIP 4

54x4E

598x4E

~ECCTM

DATA AM

---1 r---

FLOPPY DISK FORMAT; DOUBLE DENSITY

IND.:2..J

ICRC11CRC21GAP 31

2

bytes

rL

··-II

REPEATED N TIMES--_ _ _ _ _ _ _ _ _ _ _

1'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-----'
GAP 1
16X4E

GAP4

256 data bytes

HARD DISK FORMAT

FIGURE 11: DISK FORMATS

667

340x4E

--r----r1--j

r--

ECCTM

2

bytes

I

n.

INDEX

I

I

10 I G2ISYNC) DATAl G31 SYNC 110 G21 SYNC DATA IOOISYNCIIDIG2ISYNCI DATA IOOISYNCI'OIGBiSYNCIDATAIG'IG41
:
I 5BYTES~
1 256 _1
i-------,
__ I

,

RDGATE

AM:!~::::+
AMFCUNOJ
-++________;-FB

AM AM FOUND
AMFCUNO'
LOOKING FOR·
(SINGLE OENSITYI _ _ _ FE _ _+_FB-j--FE _ _ _

(DOUBLE OENSITY) _ _ A1'Fi;:
'(HARD

DISK)

AM NOT

FCUNO!

AMFDUNO!
!AMFOUNO
FE--+-FB-+-FE _ __

A1FS-l-A1FE _ _ _ _ _ _ _ _ _ _ _--ir-A1FB _ _ _+A.1FE

+

--A1FE--+--A1F8-t- A1FE-_ _ _ _ _ _ _ _ _ __f_ A1F8 _ _ _

--+

A1FB

-4- A1FE _ _

A1FE--t A1F8+ A1FE-·:~2~I;:rI~n~~~~~

FIGURE 12A: RDGATE DURING DISK READ

INDEX

ROGATE

FIGURE 12B: RDGATE AND WRITE GATE TIMING

TYPICAL FORMAT PARAMETERS
PARAMETER

HARD DISK'"

SINGLE DEN. FLOPPY

DOUBLE DEN. FLOPPY

GAP0'

16

40

80

GAP1'

16

26

50

GAP2'

3

11

22

GAP3'

18"

27*'

54"

SYNCSIZE'

13

6

12

SECTOR COUNT'

user selectable

user selectable

user selectable

SECT. SIZE MULT'

user selectable

user selectable

user selectable

RDG 1

16

73

NA

RDG2

6

13

24

RDG3

25

27

24

WDG2

5

11

23

WDG3

3

11

3

, = PARAMETER USED BY FORMAT COMMAND
" = CHANGES FOR DIFFERENT SECTOR SIZES
'" = 512 BYTES/SECTOR
TABLE 1 : STANDARD FORMAT PARAMETERS

668

IBM® PC-AT HARD DISK FORMAT
REGISTER BIT DEFINITIONS
7

5

(MSB)

4
3
LOW ORDER BYTE OF DMA BUFFER
MEMORY STARTING ADDRESS

DMA 15-8
(REGISTER 1)

(MSB)

MIDDLE ORDER BYTE OF DMA BUFFER
MEMORY STARTING ADDRESS

(LSB)

DMA 23-16
(REGISTER 2)

(MSB)

HIGH ORDER BYTE OF DMA BUFFER
MEMORY STARTING ADDRESS

(LSB)

DESIRED SECTOR
(REGISTER 3)

(MSB)

DESIRED SECTOR NUMBER

(LSB)

DESIRED HEAD
(WRITE REGISTER 4)

6

o

DMA 7-0
(REGISTER 0)

SECTOR SIZE

(LSB)

DESIRED HEAD NUMBER

ALWAYS

o

2

(LSB)

(MSB)

DESIRED CYLINDER
(REGISTER 5)

(MSB)

LOW ORDER BITS OF DESIRED CYLINDER

(LSB)

SECTOR COUNT
(WRITE REGISTER 6)

(MSB)

NUMBER OF SECTORS TO BE OPERATED ON BY COMMAND

(LSB)

RETRY COUNT
(REGISTER 7)

RETRY COUNT (1'S COMPLEMENT)

PROGRAMMABLE OUTPUTS

MODE
(REGISTER 8)

STEP

RATE

SELECT

INTERRUPTI
COMMAND TERM.
(REGISTER 9)

DATAIDELAY
(REGISTER A)

HEAD LOAD DELAY MULTIPLE IS LOADED
INTO THIS REGISTER BEFORE SELECT COMMANDS

(LSB)

DATA IS LOADED TO OR READ FROM THIS REGISTER FOR
READIWRITE/FORMAT COMMANDS DURING DATA TRANSFERS

(LSB)

HIGH ORDER BITS OF
DESIRED CYL NUMBER

ACTUAL SECTOR SIZE

CURRENT HEAD
(READ REGISTER 4)

CURRENT HEAD NUMBER

CURRENT SECTOR
SIZE

(MSB)

(LSB)

CURRENT CYLINDER
(READ REGISTER 5) L -_____________________L_OW
__O
__
RD_E_R__
B_IT_S_O_F_C_U_R_R_E_NT
__
C_Y_lI_N_DE_R__
N_U_M_B_ER
_________________(_LS_B_)__~
CURRENT IDENT
(READ REGISTER 6) '--_ _ _ _ _ _ _ _ _
ID_E_NT_BY_T_E_F_R_O_M_D_IS_K_F_O_R_S_E_E_Kl_R_E_A_D_ID_C_O_M_M_A_N_D_S_O_N_LY
_ _ _ _ _ _ _ _-----'
CHIP STATUS
(READ REGISTER 8)

DRIVE STATUS
(READ REGISTER 9)

INTERRUPT
STATUS
(COMMAND READ)

COMMAND TERMINATION
CODE

TABLE 2: REGISTER BIT MAPS

669

FLOPPY AND SMC HARD DISK FORMATS
REGISTER BIT DEFINITIONS
7

6

5

o

DMA 7-0
(REGISTER 0)

(MSB)

4
3
LOW ORDER BYTE OF DMA BUFFER
MEMORY STARTING ADDRESS

DMA15-8
(REGISTER 1)

(MSB)

MIDDLE ORDER BYTE OF DMA BUFFER
MEMORY STARTING ADDRESS

(LSB)

DMA 23-16
(REGISTER 2)

(MSB)

HIGH ORDER BYTE OF DMA BUFFER
MEMORY STARTING ADDRESS

(LSB)

2

(LSB)

I

DESIRED SECTOR
(MSB)
DESIRED
SECTOR
(WRITE REGISTER 3) '-_ _
_____________
___
_ _NUMBER
_ _ _ _ _ _ _ _ _ _ _ _ _ _(_LS_B_)----l
DESIRED HEAD
(REGISTER 4)

HIGH ORDER BITS OF
DESIRED CYLINDER

DESIRED HEAD NUMBER
(MSB)

DESIRED CYLINDER
(REGISTER 5)

(MSB)

(LSB)

LOW ORDER BITS OF DESIRED CYLINDER

(LSB)

SECTOR COUNT
(WRITE REGISTER 6) '----_(M_S_B_)_ _ _ _ _ _ _
N_UM_BE_R_O_F_SE_C_T_O_R_S_TO_B_E_O_P_ER_A_T_E_D_O_N_B_Y_C_O_M_M_A_N_D_ _ _ _ _ _ _(_LS_B_)----'
RETRY COUNT
(REGISTER 7)

RETRY COUNT (1'S COMPLEMENT)

PROGRAMMABLE OUTPUTS

MODE
(REGISTER 8)

STEP

RATE

INTERRUPTI
COMMAND TERM.
(REGISTER 9)

DATNDELAY
(REGISTER A)

HEAD LOAD DELAY MULTIPLE IS LOADED INTO THIS REGISTER
DATA IS LOADED TO OR READ FROM THIS REGISTER

CURRENT HEAD
(READ REGISTER 4)

HIGH ORDER BITS OF
CURRENT CYLINDER

(LSB)

CURRENT HEAD NUMBER
(MSB)

(LSB)

CURRENT CYLINDER
(READ REGISTER 5) ,___(M_S_B_)_ _ _ _ _ _ _ _
LOW
__
O_R_D_ER_B_IT_S_O_F_C_U_R_RE_N_T_C_Y_L_IN_D_E_R_N_U_M_BE_R_ _ _ _ _ _ _ _(_LS_B_)----l

I

CURRENT IDENT
ALWAYS FE
(READ REGISTER 6) '-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----'

FOR SEEK/READ ID COMMAND ONLY

CHIP STATUS
(READ REGISTER 8)

DRIVE STATUS
(READ REGISTER 9)

IN~~fT~USPT

COMMAND TERMINATION

(COMMAND READ) '--_ _ _~_ _ _ _~_ _ _ _'___ _ _C_O_D_E_ _ __ L_ _ _ _~_ _ _-~---~

TABLE 2: REGISTER BIT MAPS

670

HDC9234 WRITE REGISTERS (APPLIES DURING TAPE BACKUP ONLy)
DB6

DB5

DB1

REGISTER

DB7

DMA 7-0
(REGISTER 0)

(MSB)

DMA BEGINNING ADDRESS BUTE (Law ORDER BITS)

(LSB)

DMA 15-8
(REGISTER 1)

(MSB)

DMA BEGINNING ADDRESS BYTE (MIDDLE ORDER BITS)

(LSB)

DMA 23-16
(REGISTER 2)

(MSB)

DMA BEGINNING ADDRESS BYTE (HIGH ORDER BITS)

(LSB)

DESIRED
SECTOR
(REGISTER 3)

(MSB)

MAXIMUM SEARCH COUNT (IN 1'S COMPLEMENT) (1)

(LSB)

DB4

DB3

DB2

DESIRED
HEAD
(REGISTER 4)
DESIRED
CYLINDER
(REGISTER 5)

SECTOR COUNT
(REGISTER 6)

ALWAYS

ECCTYPE

DATA BLOCK SIZE

1

TAPE MARK BLOCK SIZE
(IN 2'S COMPLEMENT + 1)
(MODULO 256) (2)

OR

RETRY COUNT
(REGISTER 7)

DATA BLOCK COUNT
'(IN 1'S COMPLEMENT)
(3)

USER DEFINED OUTPUTS

MODE
(REGISTER 8)

INTERRUPTI
COMMAND
TERMINATOR
(REGISTER 9)
NOTES: (1) The maximum search count is composed of:
130 byte inner loop (RDGATE high 128, 2 byte times)
times the number programmed (maximum of 33,150 byte times
(32) Tape mark operation
() Data block operation

TABLE 3-TAPE BACKUP REGISTER BIT MAPS

671

DBO

UDC READ REGISTERS (APPLIES TAPE BACKUP ONLY)

DB4

OBI

DBO

REGISTER

DB7

DMA 7-0
(REGISTER 0)

(MSB)

DMA BEGINNING ADDRESS BYTE (Law ORDER BITS)

(LSB)

DMA1S-8
(REGISTER 1)

(MSB)

DMA BEGINNING ADDRESS BYTE (MIDDLE ORDER BITS)

(LSB)

DMA 23-16
(REGISTER 2)

(MSB)

DMA BEGINNING ADDRESS BYTE (HIGH ORDER BITS)

(LSB)

DESIRED
SECTOR
(REGISTER 3)

(MSB)

MAXIMUM SEARCH COUNT (IN I'S COMPLEMENT)

CURRENT
HEAD
(REGISTER 4)

X

X

X

X

X

X

X

X

CURRENT
CYLINDER
(REGISTER S)

X

X

X

X

x

x

X

X

DB6

DBS

DB3

DB2

(LSB)

CHIP
STATUS
(REGISTER 6)

PRESENT
DRIVE
SELECTED

DRIVE
STATUS
(REGISTER 7)
DATA
(REGISTER 8)

READ DATA

INTERRUPT
STATUS
(REGISTER 9)

COMMAND
TERMINATION
CODE (3)
NOTES:

!i!

Active level ean generate interrupt.
Active Level will not cause interrupt.
Command termination bits set to:
11 for data transfer error
10 for sync error
00 for successful termination
X Don'teare

TABLE 4: TAPE BACK UP REGISTER BIT MAPS

672

COMMAND BIT DEFINITIONS

7

6

5

4

3

2

RESET

o

o

o

o

o

o

o

DESELECT
DRIVES

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

o

RESTORE
DRIVE

STEP IN
1 CYLINDER

STEP OUT
1 CYLINDER

o

o

o
o

1 - Buffered
Seek
~ Normal
Seek

I

o

o

1

~

o

~

Buffered
Seek
Normal
Seek

1 - Buffered
Seek
~ Normal
Seek

o

I

I

o

POLL
DRIVES

SELECT
DRIVE

SET REGISTER
POINTER

DRIVE TYPE

DRIVE UNIT SELECTED

REGISTER

NUMBER

o

o

READ SECTORS
PHYSICAL

o

o

o

READ
TRACK

o

o

o

o

SEEK/READ 10

READ SECTORS
LOGICAL
0

1

0

1

1

FORMAT
TRACK

1

Enable
Transfer

o
11
o

~ Transfer Alii
~

1 - Implied
Seek
Disabled
o ~ Implied
Seek
Enabled

PRECOMPENSATION
VALUE

WRITE SECTORS
PHYSICAL
1

1 ~Implied
Seek
Disabled

0~lmplied

0

Wri1e
Deleted
Data

Wri1eWith
Reduced
Current

PRECOMPENSATION
VALUE

1

Write
Deleted
Data

Write With
Reduced
Current

PRECOMPENSATION
VALUE

Seek
Enabled
WRITE SECTORS
LOGICAL
1

1-lmplied
Seek
Disabled

0~lmplied

Seek
Enabled
TAPE
BACKUP

TABLE 5: COMMAND WORD BIT MAPS

673

Transfer 10

Enable
Transfer

IBM® FM FLOPPY DISK FORMAT:
10 FIELD
DB? DBS DB5 DB4 DB3 DB2 DB1 DBD
CYLINDER
track number
HEAD
side number
SECTOR
sector number
SECTOR SIZE
X
X
X
X
X sector size (3 bits)

HARD DISK FORMAT:
IBM PC-AT FORMAT (512 BYTES)
10 FIELD
IDENT
CYLINDER
HEAD
SECTOR

DB? DBS DB5 DB4 DB3 DB2 DB1 DBD

D

Ident Byte
cylinder number (8 LSB's)
scti' sctr trk# hd# hd# hd# hd#
bit 1 bit D bit 8 bit 3 bit 2 bit 1 bit D
sector number

HARD DISK FORMAT:
(USER SELECTABLE SECTOR SIZE)
10 FIELD
IDENT
CYLINDER
HEAD

DB? DBS DB5 DB4 DB3 DB2 DB1 DBD
Ident Byte
cylinder number (8 LSB's)
bad cyl# cyl# cyl# hd# hd# hd# hd#
sector bit 10 bit 9 bit 8 bit 3 bit 2 bit 1 bit D
flag
SECTOR
sector number
SECTOR SIZE
ECC type
X
sector size
(3 bits)

DISK FORMATS
TABLE 6
(continued)

674

SECTOR SIZE FIELD BITS
DB2
0
0
0
0
1
1
1
1

DB1
0
0
1
1
0
0
1
1

DBO
0
1
0
1
0
1
0
1

IBM FD FORMAT
128 bytes/sector
256 bytes/sector
512 bytes/sector
1024 bytes/sector
not used
not used
not used
not used

HD FORMAT
128 bytes/sector
256 bytes/sector
512 bytes/sector
1024 bytes/sector
2048 bytes/sector
4096 bytes/sector
8192 bytes/sector
16,384 bytes/sector

FORMAT ECC TYPE FIELD
DB? DB6 DB5 DB4
HD FORMAT
o 0 0 0 4 ECC bytes generated/checked
1
1
1
1 5 ECC bytes generated/checked (1)
1
1
1
0 6 ECC bytes generated/checked (1)
1
1
0
1 ? ECC bytes generated/checked (1)
note 1: WITH EXTERNAL ECC

IBM® MFM FLOPPY DISK FORMAT:
IDFIELD
DB? DB6 DB5 DB4 DB3 DB2 DB1 DBO
IDENT
Ident Byte
track number
CYLINDER
side number
HEAD
sector number
SECTOR
SECTOR SIZE
X
X
X
X
X sector size (3 bits)

DISK FORMATS
TABLE 6

675

DARD MICROSVSTEMS
~
PORATION
_

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
@Ilplications: consequently comp'lete Information sufficient for construction purposes Is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However. no responsibility is
..........
.""'" assumed for inaccuracies. Furthermore. such information does not convey to the urchaser of the
15'. ,~ .•" .'n.m..... semiconductor devices described any license under the patent rights of SMC or others. ~MC reserves the
right to make changes at any time In order to improve design ana supply the best product possible.

676

MSD7262
PRELIMINARY

Enhanced Small Device
Interface Controller

PIN CONFIGURATION

FEATURES
o Controls ESDI serial mode disks
o Controls up to seven disk drives
o Programmable soft and hard sector formats
o 18-MHz data transfer rate
o Multi-sector, -track, and -cylinder transfer
capability
o Implied seek and parallel seek capability
o High Level Commands, Including:
Read Diagnostic
Check
Chip Reset
Read ID
Clear Command End Bit Recalibrate
Clear Data FIFO
Scan
Detect Error
Send
Format Sector
Send Extended
Format Track
Sense Seek Status
Get Internal Information Sense Unit Status
Group Assign
Specify1
Logical Seek
Specify2
Mask SRQ Interrupt
Verify Data
Physical Seek
Verify ID
Read Data
Write Data
o CRC error detection
o ECC error detection and correction
o Single +5 volt supply
o 40-Pin Dual-in-Iine Package
o COPLAMOS® n-Channel Silicon Gate Technology

WDATA
RDATA
RClK

RGATE
WGATE
ClK
INDEX
SECP/BClKlAMF
AME
NC
DSD
ROY

RSf
INT
DMARO

TC
WClK

AD
WR
All

ATT

Do

CMDC
HSo/XACK
HS,/R,D
HS2/T,D
HS3/XREO
OS,
DS2
DS3
RW/COM

0,
02
03
D.
D.

0,
07
GND

Package: 40-pin DIP

GENERAL DESCRIPTION
The MSD7262 is a highly-integrated, single-chip controller
for ESDI Winchester Disks. While conforming to the
complete revision E of the ESDI specification, this device
executes 22 high-level commands that provide flexibility
and ease of usage. The MSD7262 is based on the proven

HDC7261/HDC7260 architecture but adapted to the special
requirements of this disk interface. It eliminates numerous
ICs and gives complete access to all of the features
implemented by the ESDI disk drive manufacturers.

677

OSO
ROY

ATT
CMOC

Disk
Interface
Control
Logic

HSo
HS,
HS,
HS,
OS,
OS,
OS,

RWfi5"OM

XREQ

Serial

Communication
Logic

TxO
XACK
RxO

RGATE
WGATE
INDEX

Format
Control
Logic

1m
WR

All

'fC

Host

SECPfBCLKfAMF
AME
WOATA
WCLK

System
Interface
Logic

ROATA
RCLK

OMARQ
INT

CLK-

RST_
GNO_

MSD7262 BLOCK DIAGRAM

DESCRIPTION OF PIN FUNCTIONS
PIN NO.
1
2

3
4
5
6
7
8
9
10
11
12-19
20
21

NAME
Write Data
Read Data
Read Clock
Reset
Interrupt
DMA Request

SYMBOL
WDATA
RDATA
RCLK
RST
INT

DESCRIPTION
NRZ write data output to ESDI drive
NRZ read data input from ESDI drive
Read/reference clock input from ESDI drive
System reset input
Interrupt request output

Terminal Count
Write Clock

DMARQ
TC
WCLK

DMA request output
Terminal count input from DMAC
Write dock output to ESDI drive

Read
Write

RD
WR

Read control input signal from host computer
Write control input signal from host computer

Line Address 0

Ao
Do-D7
GND
RW/COM

Address select input from host computer

Data Bus
Ground
Read Write/Command

Data bus from host computer
System ground
This output specifies the status of pins 25-28

678

DESCRIPTION OF PIN FUNCTIONS
NAME

PIN NO.

SYMBOL

22-24

Drive Select

DS3-DS,

25
26
27
28

Head Select

HS3/XREQ
HS 2 /TxD
HS , /RxD
HSo/XACK

DESCRIPTION
Drive select outputs to ESDI drive
If RW ICOM

=1: head select (HS) outputs to ESDI drive.

If RW ICOM =0 for serial data transfer to ESDI drive: transfer
request (XREQ) output, transmit data (TxD) output, receive data
(RxD) input, and transfer acknowledge (XACK) input.

29

Command Complete

CMDC

Command complete input from ESDI drive

30

Attention

ATT

Attention input from ESDI drive
Ready input from ESDI drive

31

Ready

RDY

32

Drive Select

DSD

Drive selected input from ESDI drive

33

No Connect

NC

Not connected; leave open

34

Address Mark Enable

AME

Address mark enable output from ESDI drive

35

Selector Pulsel
Byte Clock/
Address Mark

SECP/BCLKI
AMF

drive (mutually exclusive)
Index detected input from ESDI drive

Sector pulse or byte clock or address mark found; input from ESDI

36

Index

INDEX

37

Clock

CLK

System clock input to MSD7262

38

Write Gate

WGATE

Write gate output to ESDI drive

39

Read Gate

RGATE

Read gate output to ESDI drive

40

Power Supply

Vee

+5 V (Typical) input

I

679

STANDARD MICROSVSTEMS

CORPORATION

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor applications: consequently complete information sufficient tor construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the right to
make changes at any time in order to improve design and supply the best product possible.

680

MSD95COO
PRELIMINARY

Small Computer System Interface (SCSI)
Controller-SCSIC
FEATURES:

o Initiator and Target Operation.
o 5 MByte/Sec Synchronous and 3 MByte/Sec
Asynchronous Data Transfers.
o Automatic Arbitration and (Re) Selection.
o Supports both Arbitration and Non-arbitration
Applications.
o Separate Busses for Data and Microprocessor.
o Separate DMA for Processor and Data Channels.
o Burst Mode DMA Transfers on Data Bus.
o Programmed 1/0 or DMA Transfers on Processor
Data Bus.
o Internal Twelve Byte Buffer.
o Internal 24-bit Byte Transfer Counter.
o Built-in 48ma High-Current SCSI Bus Drivers.
o Thru-Parity.
o User Selectable Selection Timeout.
o Eight Bit Bi-Directional General Purpose 1/0 Port.
o Bus Architecture allows caching.
o Compatible with MSD 95C02 Storage Controller.
o Low Power CMOS.
o TTL compatible inputs and outputs.

PIN CONFIGURATION

ADS
AD6
AD7

XD2
XD1
XD0
Vee

DB6

61
62
63
64
65
66
67
68

DBS

1

CID

DB4

2
3
4
5

SEL
GND
MSG
SRST
GND

DREa

DACK

DBP
DB7

DB3
DB2
DB1

DB0
DMACLK

GND
Vee

41

34
33
32
31
6
30
29
28
9
27
1011121314151617181920212223242526

GND
1/0
REa

GND

ACK
BSY

.GND

GENERAL DESCRIPTION
The MSD95COO SCSI Controller is capable of negotiating
for and supporting data transfer on an ANSI SCSI (Small
Computer System Interface) compatible computer bus. The
internal twelve byte buffer makes this device suitable for both
peripheral and host adapter applications in systems that
support both Asynchronous and Synchronous data transfer
modes.
The MSD95COO includes circuitry that automatically
arbitrates for the SCSI bus and selects or reselects another
device. This feature combined with the size of the internal
buffer allows a selected Target device to transfer an entire
command from an Initiator with a minimum of host processor
intervention on either side.
The MSD95COO has three independent busses: one that
connects to the local microprocessor (the System bus), one

that connects to the data ring buffer (the Data bus) and the
SCSI bus. Information transfers can be made between the
SCSI bus and either of the other two busses. The Data bus
supports burst mode DMA transfers and the System bus
supports both programmed 1/0 and DMA transfers.
AcCesses to the ring buffer are controlled via a DMA request!
acknowledge handshake. Local processor transfers, as well
as transfers to logical nodes (e.g., media transfers), are
completely asynchronous with respect to transfers across
the SCSI bus.
The MSD95COO can be combined with the flexible
MSD95C02 Storage Controller, a standard microprocessor,
and off-the-shelf static RAM to support embedded SCSI
peripheral applications with minimum component count and
synchronous SCSI speeds of up to 5 megabytes per second.
681

NUn"",!

j"

I
RING BUFFER

I

DB7-DBO

qf(~8ff~,ftf$#$iJ
X1

[J

DB7-DBO

A15-AO DE

DMA
OUTPUTS/
CYCLE STATUS

WE

K~===:>I

X2
DBP-NC

l'
GND
to...

<'f"===::
--v
A

RD (DS)I-__._-++-IRD (DS)
CE
MSD95C02

- r--

DMACLKr.---+--+

ALE (AS)
RST
WR (R/W)

1

ALE (AS)
RST
AD7-0

'----~--,~.----'-r~---'-'

I

PDREO

WR
(R/W)

A15-A8

I

---iSEPARATORI~

EARLY (CTL1)
LATE (CTL2)~---~_ _ _ _ 1

INTH-+--++-iINT

AD7-0

;::::::::::::::TEST INPUTS
.....
READ
DATA
DATA

~

OR
f==~~~~:;-;AiRii=t
DISK
I . I PRECOMP I ~mE
CONTROLLER WDATAr---1 LOGIC r-DMACLK
t t

~ WR (RiW)

PDREO

RCLK
RDATA

R,£gm

DREO ~-+--++-IDMAR
DACK
DMAA

CE - t - - - I C E
TO DISK
CONTROLLER

ADDR
DECODER

CTL5-813i:==~

POR

TST4-1

XD7-XDO

-

~D~B~~~DB-0~A~15~-A~0~DE;E~W~E--'

MSD95COO
SCSIC

lJ5S

f

I ~

INT ALE RST RD
(AS)

AD7-0

GPOUT

o

Ci5
A

o

JJ

<:
m

~~~!f-;j:======:::J~
V

SENS4-1

1v-

./

DRIVE STATUS

A

GPIN:~~

;:::=========J
DRIVE CONTROL

Z80, 80188, 8051 OR OTHER PROCESSORS

GPI/O

L...J TYPICAL SYSTEM CONFIGURATION (EMBEDDED SCSI DISK DRIVE)

12~TE3

8 WIDE
3:1 MUX

Cf)

:::l

co
~
~

SCSI
BUS
INTERFACE
DB(7)
DB(O)
DB(P)
BSY
SEL
REO
ACK
MSG
I/O
C/D
ATN
RST

<

.

FIFO

II

INTERFACE

DEMUX

~

---

DMACLK
DREO
DACK

DB7-DBO
DBP

RING
BUFFER

INTERFACE

STATE
MACHINE

I

SD7-

DISK
CONTROLLER

) SDO

SDP
BSY
SEL
• REO
ACK
MSG
I/O
C/D
ATN
SRST

b

PARITY
CHECKER/
GENERATOR ~

J
-

1

24-BIT
BYTE
COUNTER

1

CONTROL LOGIC
AND STATUS
REGISTERS

~

OSCILLATOR
CLOCK
X2 - - - ; GENERATOR

~

MSD95COO BLOCK DIAGRAM
682

XD7-XDO

r
AD7-ADO

I"

X1

GENERAL
PURPOSE
I/O PORT

r
PROCESSOR
INTERFACE

I--I---

'"

~

r------

RD(DS)
WR (RiW)
ALE (AS)
CE
RST
INT
PDREO

DESCRIPTION OF PIN FUNCTIONS
PIN NO

NAME

SYMBOL

I/O

1-6
67,68

RING BUFFER
DATA BUS

DBO-DB7

I/O

These pins are the eight bi-directional data signals
to/from the RING Buffer.

DESCRIPTION

7

DMACLOCK

DMACLK

0

This output is used by the DMA controller to time
data transfers.

8, 12, 15, 18,21

GROUND

GND

P

Ground connection.

9,40

POWER

Vee

P

+ 5V Power connection.

11

CRYSTAL INPUT

X1

I

A 20 MHz. (max) crystal is connected to this output.
Alternately a TTL clock may be the input to this pin.

10

CRYSTAL OUTPUT

X2

0

A 20 MHz. (max) crystal is connected to this output.
Alternately, if a TTL is connected to X1, this input is
left floating.

13,14,16,
17,19,20,
22,23

SCSI DATA BUS

SDO-SD7

I/O

These pins are the eight bi-directional SCSI data
signals to/from the SCSI bus. Their direction
depends on the state of the I/O signal, except
during arbitration.

25

SCSI PARITY

SDP

I/O

This pin is the bi-directional PARITY signal to/from
the SCSI bus. Its direction depends on the state of
the I/O signal.

26

ATTENTION

ATN

I/O

This pin is the bi-directional ATTENTION signal to/
from the SCSI bus. It is an output when the
controller is programmed as an initiator and an input
when programmed as a target.

28

BUSY

BSY

I/O

This pin is the bi-directional BUSY signal to/from the
SCSI bus.

29

ACKNOWLEDGE

ACK

I/O

This pin is the bi-directional ACKNOWLEDGE
signal to/from the SCSI bus. It is an output whon tho
controller is programmed as an initiator and an input
when programmed as a target.

31

SCSI BUS RESET

SRST

I/O

A low on this bi-directional SCSI bus indicates an
SCSI bus Reset.

32

MESSAGE

MSG

I/O

This pin is the bi-directional MESSAGE signal tol
from the SCSI bus. It is an output when the
controller is programmed as a target and an input
when programmed as an initiator.

34

SELECT

SEL

I/O

This pin is the bi-directional SELECT signal to/from
the SCSI bus.

35

COMMAND/DATA

C/D

I/O

This pin is the bi-directional COMMANDIDATA
signal to/from the SCSI bus. It is an output when the
controller is programmed as a target and an input
when programmed as an initiator.

37

REQUEST

REQ

I/O

This pin is the bi-directional REQUEST signal to/
from the SCSI bus. It is an input when the controller
is programmed as an initiator and an output when
programmed as a target.

38

INPUT/OUTPUT

I/O

I/O

This pin is the bi-directionaIINPUT/OUTPUT signal
to/from the SCSI bus. It is an output when the
controller is programmed as a target and an input
when programmed as an initiator.

41-48

BIDIRECTIONAL
EXTERNAL DATA BUS

XDO-XD7

I/O

These pins are open drain general purpose I/O bus
with internal 1K pull ups.

49

RESET

RST

I

This active low input causes the MSD95COO to reset
to an initial state:
All SCSI signals are deasserted.
DREQ is inactive high.
PDREQ is inactive low.
INT is inactive high.
AD7-0 are inputs.
DB7-0 are inputs.
Refer to individual register descriptions for the reset
state of each register.

24,2~30,33,36,39

683

DESCRIPTION OF PIN FUNCTIONS
PIN NO

NAME
PROCESSOR
DMA REQUEST
INTERRUPT

SYMBOL
PDREQ

I/O

INT

0

52

WRITE STROBE
(READIWRITE)

WR
(RiW)

I

53

READ STROBE
(DATA STROBE)

RD(DS)

I

54

CHIP ENABLE

CE

I

55

ADDRESS LATCH
ENABLE
(ADDRESS STROBE)
LOCAL PROCESSOR
ADDRESS/DATA BUS

ALE (AS)

I

ADO-AD7

I/O

50
51

56-63

0

64

DMAREQUEST

DREQ

0

65

DMA
ACKNOWLEDGE

DACK

I

66

SYSTEM DATA
BUS PARITY

DBP

I/O

SYSTEM OPERATION
SCSI initiators and targets communicate using a protocol
based on eight distinct phases. These phases are used to
describe changes to the various conditions of the control
lines and the data bus lines. In one possible order of
execution, the phases of SCSI include:
BUS FREE phase: No signal lines are being driven by
any target or initiator.
ARBITRATION phase: Arbitration is an optional phase
where the initiator, or target if reselection is supported,
tries to gain access to the bus by issuing its SCSI ID on
the data bus. The initiator with the highest SCSI ID
(closest to bit 7) wins the bus.
SELECTION phase or RES ELECTION phase:
SELECTION phase: The selection phase allows the
initiator .to select a target for a given function (e.g.,
READ or WRITE command). NOTE: Once the target
has been selected, it controls the bus until the end of
MESSAGE phase.
RESELECTION phase: An optional phase that is the
same as the selection phase, except that a target
becomes an arbitrator during the arbitration phase. This
phase is used when a target prematurely disconnects
from an initiator, leaving a previous command
unfinished.
MESSAGE phases: There are two MESSAGE phases
(MESSAGE IN and MESSAGE OUT) used to provide for
other communication between the initiator and the target.
This phase allows for single byte messages such as
COMMAND COMPLETE or multiple byte messages such

DESCRIPTION
Output active high when data byte transfer to/from
Processor RAM is required.
This output is the interrupt signal to the local
processor. This output is active low open drain and
has an internal pullup.
When the SCSIC is configured for ALE, this active
low strobe is used to latch write data from the AD7-0
bus into the S,Q,SIC. When the SCSIC is co!}!igured
for AS, the R/W input is used to qualify the OS for a
read or write cycle.
When the SCSIC is configured for ALE, this active
low strobe is used to enable read data from the
SCSIC onto the AD7-0 bus. When the SCSIC is
configured for AS, this active low signal is used to
strobe data into or out of the SCSIC.
This input, when low, enables the SCSIC's registers
for reading and writing.
This signal is active when address data is valid on
the AD7-0 bus. The local processor must read L
SCSIC register to configure the chip for ALE or AS.
These eight signals are the multiplexed address/
data bus to/from the local processor.
This active low output is used to request a DMA
transfer between the SCSIC and its logical node
across the RING Buffer data bus.
This active low input is used to strobe data from the
RING Buffer data bus during transfers between the
SCSIC and its logical node.
This pin is the parity bit for the RING Buffer Data
Bus.

as establishing data path management.
COMMAND phase: Allows the target to request a
command from the initiator. The command might be to
read data, write data, format the disk, etc. A command
consists of several bytes called the COMMAND
DESCRIPTOR BLOCK.
DATA phase: There are two data phases, the DATA IN
phase and the DATA OUT phase. For the DATA IN phase,
the Target requests that data be sent from the Target to
initiator. The DATA OUT phase transfers data from the
initiator to Target.
STATUS phase: The STATUS phase allows the target to
send a byte of status to the initiator. Additional status can
be requested with another command.

Automatic Selection And Reselection
This section describes how an Initiator selects a Target, a
Target reselectsan Initiator and a Target or Initiator becomes
selected or reselected.
SELECTION AND RESELECTION
The Arbitration, Selection and Reselection phases are
controlled by a state machine. When the MSD95COO detects
the SCSI Bus Free phase, it will perform the Arbitration,
Selection or Reselection sequence required.
Issuing the Select command to the MSD95COO will cause
the internal Attempt Selection (ATMTSEL) latch to be set.
The Destination 10 must be loaded prior to issuing the Select
command. Command execution will then be dependent on
the settings of the Initiator/Target and Arbitration Enable/
Disable bits in the Mode register:
684

INITITARG

ARBITRATION
ENABLE

0
0

0
1

1

0

1

1

Effect of
Select Command
Illegal Condition
Initiate Arbitration for
SCSI bus and Reselect
Initiator when
Arbitration won
Select Target without
Arbitration
Initiate Arbitration for
SCSI bus and Select
Target when Arbitration
won

In either case, the SCSIC will not begin the Arbitration or
Selection phases until detection of Bus Free. The SCSIC
will then either enter the Arbitration phase or go directly to
the Selection or Reselection phase.
If it enters the Arbitration phase, the SCSIC will attempt to
gain control of the SCSI bus. Following Arbitration, if it won
the bus, the SCSIC will start the Selection or Reselection
phase or if it lost the bus, begin looking for Bus Free phase.
BEING SELECTED OR RESELECTED
If enabled, the SCSIC may be Selected or Reselected by
another SCSI device (depending on whether it is
programmed as a Target or Initiator)
ENA
RESEL ENASEL Selection/Reselection
Device may not be selected or
0
0
reselected
Device may be selected but not
0
1
reselected
Device may be reselected but
1
0
not selected
Device may be selected or
1
1
reselected
The SCSIC will reset the ATMTSEL latch if 1) it detects that
it is being selected, the selection is good and Selection is
enabled or 2) it is being Reselected, the reselection is good
and Reselection is enabled. For example, in the case in
which the SCSIC attempted Arbitration (when ATMTSEL
was set), lost Arbitration and was itself selected, the
ATMTSEL latch will be reset. The ATMTSEL bit is also reset
when the SCSIC wins Arbitration and completes Selection
or Reselection either successfully or unsuccessfully. A
Selection or Reselection is good if there are no more than
two ID bits asserted (one of which corresponds to the one
in the SCSI ID register) and the parity, if enabled, is good.
If a Selection or Reselection is not good, the SCSIC will not
respond. If the Selection or Reselecion is good but not
enabled, the Invalid (Re)Selection Status bit will be set. If
the Selection or Reselec!ion is good and enabled, either the
Valid Selection or Valid Reselection status bit will be set.
When being selected or reselected the SCSIC will mask off
its own ID bit when it latches the bus ID into the SCSI BUS
ID register. The Processor can read the register after the
Selection or Reselection is complete to determine the
selecting or reselecting device.
Interrupt Mechanism
The processor should respond to an interrupt by reading
the Interrupt Status register.
If the SCSI status bit is active high, the Processor reads the
Status 1 register to determine the source of the interrupt. If
the Selection Attempted or (Re)Selection Complete status

bits are active high, the Processor should read the Status 2
register. The SCSIC resets Selection Attempted and
(Re)Selection Complete status bits during the Status 2
register read.
If the Transfer Requested, Transfer Complete, Parity Error,
SCSI Reset Change or SCSI ATN Change status bits are
active high, the Processor should read the Status 3 register.
In response, the SCSIC resets Transfer Requested, Transfer
Complete, Parity Error, SCSI Reset Change and SCSI ATN
Change status bits.
If the Condition Change status bit is active high, the
Processor should read the Status 4 register, and the SCSIC
resets the Condition Change status bit.
Byte Transfer Modes
INTERRUPT DRIVEN 110:
The processor responds to an interrupt by reading the
Interrupt Status register. If the SCSI status bit is active high,
the Processor reads the Status 1 register to determine the
source of the interrupt.
If the Transfer Requested status bit is active high, the
Processor should read the Status 3 register. In response
the SCSIC resets the Transfer Requested status bits.
If the Byte Available status bit is set, the Processor reads
the SCSI Data Out register. Next, if no more data is found
in buffer, the SCSIC clears the Byte Available status bit. If
the Byte Available status bit is still set, the SCSIC then clears
PDREQ and generates a new transfer Request interrupt.
If the Byte Requested status bit is set, the Processor writes
a byte of data to the SCSI Data Out register. The SCSIC
clears the Byte Requested status bit if no more SCSI REQs
are pending or there is no more room in the buffer. Next,
SCSI clears PDREQ and generates another Transfer
Request interrupt if the Byte Requested status bit is still set.
DMA DRIVEN 1/0:
DMA controller transfers Message bytes to Processor RAM
in response to PDREQ active high. The SCSI Byte Available
status bit is cleared if no more data is in the buffer. Next SCSI
clears PDREQ (byte mode) and PDREQ (burst mode) if the
Byte Available status bit is not active high. Another PDREQ
is generated if the Byte Available status bit is still set.
DMA controller transfers Message bytes from the Processor
RAM to the SCSI Data Out register in response to PDREQ
active high. The SCSIC then 1) clears the Byte Requested
status bit if no more SCSI REQs are pending or there is no
more room in the Buffer, 2a) PDREQ is cleared (byte mode),
2b) PDREQ is cleared (burst mode) if the Byte Requested
status bit is not active high and 3) another PDREQ is
generated if the Byte Requested status bit is still set.
POLLED 1/0:
The processor reads the Status 3 register to see if either
the Byte Available or Byte Requested status bits are active
high.
If Byte Available is active, the Processor transfers the byte
from the SCSI Data In register to the Processor or the
Processor RAM. If there is no more data in the buffer, the
SCSIC clears the Byte Available status bit.
If the Byte Requested is active, the Processor transfers the
byte from the Processor or the Processor RAM to the SCSI
Data Out register. If no SCSI REQs are pending or the Buffer
is full, the Byte Requested status bit is cleared.
SCSI Parity Error Handling
Initiator (Status, Message In, Data In Phases):
If the Halt On Parity Error bit in the Control Register is set
to one the SCSIC will halt and set the Halted and PE status

685

I

bits if data has even parity. If these bits are set, the SCSIC
will generate a PE interrupt. If enabled, a Condition Change
interrupt will also be generated. In response to the interrupt,
the processor reads the Status registers and resets Parity
Error and Condition Change Interrupts.
The processor asserts ATN to request Message Out phase
in order to signal its desire to send either Message Reject
or Message Parity Error. Then the processor issues a
(Re)Start Command.
Target (Command, Message Out, Data Out Phases):
The SCSIC will set the PE status bit if data has even parity.
If the PE bit is set, the SCSIC will generate a PE interrupt.
In response to the interrupt, the processor reads the Status
registers. Finally, the SCSIC resets the Parity Error
Interrupts.
Note: The Halt On Parity Error bit in the Control Register
does not affect Target operation.

COMMANDS
The SCSIC acts as an interface between the SCSI bus and
the initiator/target unit. When acting as an initiator (or target
supporting reselection), it controls the selection and
arbitration process. As a target, it manages the receipt of
the command packet from the initiator. All other operations
TABLE 1-MSD95COO COMMANDS
COMM
CODE
(HEX)
COMMAND
00
Test Unit Ready
03
Request Sense
04
Format Unit
08
Read
OA
Write
01
Rezero Unit
05
Check Track Format
OB
Seek
12
Inquiry
1A
Mode Sense
25
Read Capacity
06
Format Track
OE
Assign Alt Track
15
Mode Select
16
Reserve Unit
17
Release Unit
Receive Diag Result
1C
10
Send Diagnostics
2E
Write and Verify
REGISTER DESCRIPTION
RESET REGISTER
8-Bits Read Only (ADDRESS OOH)
Readinf1.!!1e Reset register address configures the chip to
ALE or AS type timing. Reading the Reset register address
a second time puts the MSD95COO into the same state as
driving the RST input low and simultaneously reads the
general purpose input port:A write to any other. MSD95COO
register will terminate the reset state as well as write to the
desired register. Both the hardware and software resets will
perform the same function as the Clear command in addition
to resetting certain register bits as detailed below.

are managed by an outside processor. The typical flow of
control progresses as follows:
1) The initiator's processor builds the command block.
2) The processor then instructs the initiating SCSIC to
begin Selection. Arbitration, if enabled, is handled by the
chip.
3) Once the target unit is selected, the target's processor
instructs the target SCSIC to set up a command phase
(other phases possible at this point include message,
status or data phases).
4) The first byte is transmitted to the target.
5) The target SCSIC notifies its processor (through
polling/interrupt) that it is holding the byte. The processor
reads the byte in order to determine the command length.
6) The target processor instructs its SCSIC to transfer the
remaining bytes.
7) The command packet now resides in the target
SCSIC's FIFO buffer.
8) The target SCSIC notifies its processor (through
polling/interrupt) that the command packet is available.
9) The processor transfers the command packet into its
own memory. The processor is now responsible for
digesting and executing the command.
10) While the target's processor executes each command,
the initiator and target SCSICs handle handshaking
associated with the command.

SCSI
optional
mandatory
mandatory
mandatory
mandatory
optional
vender unique
optional
extended
optional
extended
Vender Unique
Vender Unique
optional
optional
optional
optional
optional
optional

CCS
mandatory
mandatory
mandatory
mandatory
mandatory
optional
optional
mandatory
optional
mandatory
optional
mandatory
optional
optional
mandatory
optional

The 4 LSB's are used to program the SCSI REQ/ACK offset.
The 4 LSB'sare reset to zero by a hard or soft System Reset.
Bits 3-0
REQ/ACK Offset.
= 0 SCSI Asynchronous data transfer mode.
= 1-12 SCSI Synchronous data transfer mode.
These bits are used to program the MSD95COO with the
REQ/ACK offset. The maximum number of offsets the
MSC95COO can support is 12. These bits should be
programmed with the REQ/ACK Offset regardless of
whether the chip is operating in Initiator or Target mode.
Bits 7-4 Transfer Period

These bits are used to program the MSD95COO with the
NEGOTIATION REGISTER
Transfer Period for the SCSI Synchronous Data transfer
. 8-Bit Write Only (ADDRESS OOH)
operations. The transfer period will be (2 + N) T where T is
The 4 MS8's of this eight bit write only register are used to twice the clock period. For a 20 Mhz crystal 1 is (2 + 0)
program the Transfer Period for Synchronous Data transfer. 100ns = 200ns = 5mhz.
686

MSD95COO
REGISTER BIT MAPS
NEGOTIATION REGISTER

RESET REGISTER

(WRITE REGISTER-ADDRESS OOH)

TRANSFER PERIOD

(READ REGISTER-ADDRESS OOH)

REQ/ACK OFFSET

XD7-XDO (IN)

(WAITE AEGJSTER-ADDRESS01H)

BYTE COUNTER HIGH REGISTER

MOST SIGNIFICANT BYTE OF BYTE
COUNT REGISTER (1's compliment)

IIMSBI

MIDDLE BYTE OF BYTE COUNT REGISTER
(1 's compliment)

IIMSBI

MOST SIGNIFICANT BYTE

BYTE COUNTER MIDDLE REGISTER

110 REGISTER

IIMSBI

ILSBII

(READ REGISTER-ADDRESS 03H)

MIDDLE SIGNIFICANT BYTE

BYTE COUNTER lOW REGISTER

LEAST SIGNIFICANT BYTE OF BYTE
COUNT REGISTER (1's compliment)

(READ REGISTER-ADDRESS 02H)

ILSBII

(READ REGISTER-ADDRESS 04H)

LEAST SIGNIFICANT BYTE

ILSBII

(WRITE REGISTER-ADDRESS 05H)

I

LATCHED DATA TO XD7 TO XDO PINS

LATCHED DATA FROM XD7-XDO PINS (IN)

(READ REGISTER-ADDRESS 09H)

RESERVED

ISCSI IRESERVED I
INTERRUPT

(WRITE REGISTER-ADDRESS aBH)

ILSBI I

RESERVED

(WRITE REGISTER-ADDRESS OCH)

RESERVED

ILSBI I

RESERVED
DESTINATION 10 REGISTER

(WRITE REGISTER-ADDRESS DOH)

DESTINATION 10
seS110 REGISTER

SCSI 10 (NODE 10)
DATA OUT REGISTER

IMSBI

ILSBII

(WRITE REGISTER-ADDRESS OEH)

ILSBI I

SCSI BUS 10 (NODE SOURCE 10)

(WRITE REGISTER-ADDRESS OFH)

DATA TO BE OUTPUT TO THE SCSI BUS

DATA IN REGISTER

ILSBI

(READ REGISTER-ADDRESS OFH)

DATA FROM BUFFER

MODE REGISTER
8-Bits Read/Write (ADDRESS 01 H)
This 8 bit Read/Write register defines the operating mode
of the SCSIC. Refer to the System Operation section for a
description of the operating modes. The bits in this register
are reset to zero by a hard or soft System Reset.
Bit 0 Initiator/Target
The state of this bit will not prevent the chip from being

ILSBII

selected or reselected by another device. The state of this
bit determines whether the select command will start either
the select function or the reselect function.
Bit 1 Arbitration Enable/Disable
When this bit is set to 1, the MSD95COO will begin arbitration
for SCSI bus after detecting bus free for selected
commands. When set to 0, the arbitration phase will be
bypassed and the chip will go directly to selection after
detecting bus free.

687

Bit 2 Parity Check Enable
When this bit is "1 '; the MSD95COO checks the parity of the
SCSI bus during all phase except Bus Free and Arbitration.
When this bit is "0", Parity will not be checked.
Bit 3 DREQ Multiple/Single Pulse Mode
When this bit is "1 '; the SCSIC can generate up to twelve
DREQ pulses before receiving the first DACK. When this
bit is "0'; the SCSIC will expect one DACK for every DREQ
pulse generated.
Bit 4 PDREQ Level/Pulsed
When this bit is "1 '; PDREQ will be high as long as there is
received data in the buffer or there is room for more data in
the buffer when sending data. When this bit is "0'; the
MSD95COO will drive the PDREQ output inactive low after
the Data In register is read or the Data Out register is written
to regardless of the state of the buffer.
Bit 5, 6 Selection Timeout
These two bits are used to select the desired SCSI Selection
Timeout:
Bit6
Bit 5
Timeout Selected'
839ms
0
0
0
1
210ms
1
0
52ms
1
1.6ms
1
'based on 20 MHz crystal operation
Bit 7 Reserved
BYTE COUNTER HIGH REGISTER
8-Bit ReadlWrite (ADDRESS 02H)
This 8-bit ReadlWrite register holds the most significant byte
that is to be loaded into the Byte Counter. The data is
transferred from the Byte Counter High Register into the
Byte Counter when the Byte Counter Low register is loaded.
Bit 7 is the MSB and bit 0 is the LSB. The Byte Counter
registers are loaded with the 1's complement of the desired
byte count.
BYTE COUNTER MIDDLE REGISTER
8-Bit ReadlWrite (ADDRESS 03H)
This 8-bit ReadlWrite register holds the middle byte of data
that is to be loaded into the Byte Counter. The data is
transferred from the Byte Counter Middle Register into the
Byte Counter when the Byte Counter Low register is loaded.
Bit 7 is the MSB and bit 0 is the LSB. .
The Byte Count~r registers are loaded with the 1's
complement of the desired byte count.
BYTE COUNTER LOW REGISTER
8-Bit ReadlWrite (ADDRESS 04H)
This a-bit ReadlWrite register holds the least significant byte
of data that is to be loaded into the Byte Counter. The data
is transferred into the Byte Counter when the Byte Counter
Low register is loaded. Bit 7 is the MSB and bit 0 is the LSB.
The Byte Counter registers are loaded with the 1's
complement of the desired byte count.

This eight bit ReadlWrite register enables or disables certain
interrupt causing conditions to the microcomputer. Reading
this register reflects the states of the bits in it. The bits in this
register are cleared to zero by a hard or soft System Reset.
Bit 0 Selection Attempted Interrupt
When this bit is set to "1 ", the MSD95COO drives the SCSI
Master Interrupt bit active high when the Selection
Attempted bit in the Status 1 register is set to one. When
this bit is "0'; the Master Interrupt will not be driven active
high for this condition.
Bit 1 (Re)Selection Complete Interrupt Enable
When this bit is set to "1 ", the MSD95COO drives the SCSI
Master Interrupt bit active high when the (Re)Selection
Complete bit in the Status 1 register is set to one. If this bit
is "0'; the Master Interrupt will not be driven active high for
this condition.
Bit 2 Transfer Request Interrupt
When the bit is set to "1 ", the MSD95COO drives the SCSI
Master Interrupt bit active high when the Transfer Request
bit in the Status 1 register is set to one. If this bit is "0'; the
Master Interrupt will not be driven high for this condition.
Bit 3 Transfer Complete Interrupt Enable
When this bit is set to "1 '; the MSD95COO drives the SCSI
Master Interrupt bit active high when the Transfer Complete
Interrupt bit in the Status 1 register is set to one. The Master
Interrupt will not be driven high for this condition.
Bit 4 Parity Error Interrupt Enable
When this bit is set to "1 '; the MSD95COO drives the SCSI
Master Interrupt bit active high when the Parity Error
Interrupt bit in the Status 1 register is set to one. When this
bit is "0'; the Master Interrupt will not be driven active high
for this condition.
Bit 5 System Parity Error Interrupt Enable
When this bit is "1 '; the SCSIC will drive the SCSI Master
Interrupt bit active high when the System Parity Error
Interrupt bit in the Status 1 register is set to one. When this
bit is reset, the Master Interrupt will not be driven active high
for this condition.
Bit 6 SCSI ATN or RESET Change Interrupt Enable
When this bit is set to "1 '; the MSD95COOwili drive the SCSI
Master Interrupt bit active high when the SCSI ATN or
RESET Change bit in the Status 1 register is set to 1. When
this bit is set to "0", the Master Interrupt will not be driven
active high for this condition.
Bit 7 Condition Change Interrupt Enable
When this bit is set to "1 ", the MSD95COO will drive the SCSI
Master Interrupt bit active high when the Condition Change
bit in the Status 1 register is set to one. When this bit is set
to "0'; the Master Interrupt will not be driven active high for
"this condition.

INTERRUPT ENABLE 2 REGISTER
a-Bit ReadlWrite (ADDRESS 07H)
This eight bit ReadlWrite register enables or disables certain
microcomputer interrupt causing conditions. Reading this
register reflects the states of the bits in it. The bits in this
I/O REGISTER
register are cleared to zero by a hard or soft System Reset.
8-Bit ReadlWrite (ADDRESS 05H)
.Bit 0 Valid Selection Interrupt Enable
This a-bit ReadlWrite register is an eight bit bi-directional When this bit is set to "1 '; the SCSIC will set the Selection
I/O port available to the Processor. Data written to this Attempted bit in the Status 1 register to one when the Valid
register will be latched and available on the XD7-XDO pins. Selection bit in the Status 2 register is active high. When
Information present on the XD7-XDO pins will be available this bit is "0", the Selection Attempted bit cannot be set by
to the Processor when this register is read. The XD7~XDO this condition.
I/O pins are open drain with internal pullup devices.
Bit 1 Valid Reselection Interrupt Enable
INTERRUPT ENABLE 1 REGISTER
When this bit is set to "1 ", the SCSIC will set the Selection
Attempted bit in the Status 1 register to one when the Valid
a-Bit ReadlWrite (ADDRESS 06H)
688

Reselection bit in the Status 2 register is active high. When
this bit is set to "0'; the Selection Attempted bit cannot be
set by this condition.
Bit 2 Invalid (Re)Selection Interrupt Enable
Setting this bit to a one will cause the SCSIC to set the
Selection Attempted bit in the Status 1 register to one when
the Invalid (Re)Selection bit in the Status 2 register is active
high. If this bit is "0'; the Selection Attempted bit cannot be
set by this condition.
Bit 3 SCSI Transfer Complete Interrupt Enable
Setting this bit to "1" will cause the SCSIC to set the Transfer
Complete Interrupt bit in the Status 1 register to one when
the SCSI Transfer Complete bit in the Status 3 register is
active high. If this bit is "0", the Transfer Complete Interrupt
bit cannot be set by this condition.
Bit 4 Transfer Done Interrupt Enable
Setting this bit to "1" will.cause the MSD95COO to set the
Transfer complete Interrupt bit in the Status 1 register to one
when the Transfer Done bit in the Status 3 register is active
high. If this bit is "0'; the Transfer Complete Interrupt bit
cannot be set by this condition.
Bit 5 Halted Interrupt Enable
Setting this bit to "1" will cause the MSD95COO to set the
Condition Change bit in the Status 1 register to one when
the Halted bit in the Status 4 register goes active high. If this
bit is "0", the Condition Change bit cannot be set by this
condition.
Bit 6 Bus Free Phase Detect Interrupt Enable
Setting this bit to "1" will cause the MSD95COO to set the
Condition Change bit in the Status 1 register to one when
the Bus Free Phase Detect bit in the Status 4 register is
active high. If this bit is "0'; the Phase Change bit cannot be
set by this condition.
Bit 7 SCSI Master Interrupt Enable
Setting this bit to "1" will cause the MSD95COO to drive its
INT output active low when an enabled condition causes
one of the bits i.n the Status 1 register to go active high. If
this bit is "0'; the INT pin cannot be driven active.

Bit 5 Halt On Parity Error
When this bit is set to "1" and the MSD95COO is operating
in Initiator mode, the MSD95COO will not assert SACK for
bytes with bad parity during Status, Message In or Data In
phase transfers. This bit does not affect operation in Target
mode. When this bit is set to "0'; the MSD95COO will negate
SACK regardless of parity.
Bit 6 Enable PDREQ
When this bit is set to "1'; the SCSIC will be able to drive
the PDREQ output active high. When this bit is set to "0';
the PDREQ output will be forced low.
Bit 7 Enable DREQ
When this bit is set to "1 '; the MSD95COO will be able to
drive the DREQ output active low. When this bit is set to "0';
the DREQ output will be forced high.
INTERRUPT STATUS
8-Bit Read Only (ADDRESS 09H)
This Read Only register contains information about the
internal MSD95COO operation.
Bits 0-1 Always 0
Bit 2 SCSI Interrupt
This bit is set to "1" when one of the enabled interrupt
causing conditions causes a bit in the Status 1 register to
go active high. It is reset to "0" when the interrupt causing
condition(s) are cleared.
Bits 3-7 Always 0

COMMAND 1 REGISTER
8-Bit Write Only (ADDRESS 09H)
This Write Only register is used to initiate one of the Select
or Reselect operations and to assert or negate the SCSI
bus signals that are manipulated by the Processor software.
Except for the Clear bit, the states of these bits are used to
generate a strobe and are not latched in the MSD95COO. A
hard or soft System Reset will cause the signals controlled
by this register to be negated and the Clear bit to be reset
to "0':
Bit 0 Assert SCSI Reset Signal
Setting this bit to "1" will cause the MSD95COO to assert
CONTROL REGISTER
8-Bit Read/Write (ADDRESS 08H)
the SCSI bus reset signal (SRST).
This 8 bit Read/Write register is used to control chip Bit 1 Negate SCSI Reset Signal
operation. The bits are reset to zero by a hard or soft System Setting this bit to "1" will cause the MSD95COO to negate
the SCSI bus reset signal (SRST).
Reset.
Bit 2 Assert ATN Signal
Bit 0 Auto ATN Assert
When this bit is set to "1 ", the MSD95COO will automatically Setting this bit to "1" will cause the MSD95COO to assert
assert the SCSI bus ATN signal before beginning the select the SCSI bus ATN signal (ATN).
part of one of the Select commands. When this bit is set to Bit 3 Negate ATN Signal
"0'; ATN will not be asserted.
Setting this bit to "1 "will cause the SCSI chip to negate the
SCSI bus ATN signal (ATN).
Bit 1 Enable Selection
When this bit is set to "1'; the MSD95COO will allow itselt to Bit4Clear
be selected by another SCSI device. When this bit is set to Setting this bit to "1" will cause the chip to go into the Clear
"0", the MSD95COO will generate an interrupt when another state and reset all of the internal counters, reset the latched
SCSI device tries to select it. The state of this bit will not status bits, reset the SCSI Master Interrupt Enable, reset
prevent the chip from attempting to select or reselect another the bits in the Command 2 Register, disconnect from the
SCSI bus and negate the SCSI control signals. Setting this
SCSI device.
bit to "0" will terminate the Clear state. After setting this bit
Bit 2 Enable Reselection
to "1 ", the Processor must wait a minimum of 1 fLsecbelore
When this bit is set to "1'; the MSD95COO will allow itself to clearing it.
be reselected by another SCSI device. When this bit is set
to "0", the MSD95COO will generate an interrupt when Bit 5 (Re)Start
another SCSI device tries to reselect it. The state of this bit When the MSD95COO is operating in the Initiator mode,
will not prevent the chip from attempting to select or reselect writing a "1" to this bit will cause chip operation, that was
interrupted by detection of a parity error on the SCSI data
another SCSI device.
bus, to continue (this condition can only occur when the Halt
Bit 3 Always 0
On Parity Error bit in the Control register is set to "1 "). Also,
writing a "1" to this bit after the MSD95COO was halted by
Bit 4 Always 0
689

SREQ going active when the byte counter was equal to "0"
will cauSI;) the MSD95COO to respond with SACK. This will
allow the Initiator to perform single byte transfers without
loading the Byte Counter (data may be written to the buffer
before or after writing to the Command register). This bit
does not affect Target mode chip operation.
Bit6 Select
Setting this bit to "1" will cause the MSD95COO to initiate a
Select operation, a Select with ATN asserted operation, an
Arbitrate and Select operation, an Arbitrate and Select with
ATN asserted operation or an Arbitrate and Reselect
opration. The operation initiated depends on the state of the
Target/Initiator and Arbitration EnablelDisable bits in the
Mode register and the Auto-ATN Assert bit in the Control
register.
Bit 7 Disconnect
Setting this bit to "1" will cause the MSD95COO to stop
driving all of the SCSI Data Bus and Control signals.
STATUS 1 REGISTER
8-Bit Read Only (ADDRESS OAH)
This 8-bit Read Only register contains information about the
internal MSD95COO operation.
Bit 0 Selection Attempted
This bit is setto "1 " by the active and enabled state of either
the Valid Select, Valid Reselect or Invalid (Re)Select status
bits in the Status 2 register. It is reset by reading the Status
2 register.
Bit 1 (Re)Selection Complete
This bit is set to "1" by the active state of either the
Successful (Re)Selection Complete or Unsuccessful
(Re)Selection Complete status bits in the Status 2 register.
It is reset by reading the Status 2 register.
Bit 2 Transfer Request
This bit is set to "1" by the active state of either the Byte
Available or Byte Requested status bits in the Status 3
register. It is reset by reading the Status 3 register. It will be
set again after the Data Register is read if Byte Available or
Byte Requested are still high.
Bit 3 Transfer Complete Interrupt
This bit is set to "1" when either the Transfer Done or SCSI
Transfer Complete bits in the Status 3 register go active high.
It is reset by reading the Status 3 register.
Bit 4 Parity Error Interrupt
This bit is set to "1" when the Parity Error bit in the Status 3
register goes active high. It is reset by reading the Status 3
register.
Bit 5 System Parity Error
This bit is set to "1" when the System Parity Error bit in the
Status 3 register goes active high. It is reset by reading the
Status 3 register.
Bit 6 SCSI ATN or RESET Change
This bit is set to "1" when either the SCSI ATN or RESET
signal changes from the high to low or low to high state. It
is reset by reading the Status 3 register.
Bit 7 Condition Change
This bit is set to "1" when either the (enabled) Bus Free
Detected or Halted bits in the Status 4 register go active
high. It is reset by reading the Status 4 register.

changing direction from out (the.lnitiator driving) to in (the
Target driving) it will release the SCSI Data bus within a Data
Release Time (400ns) of 1/0 being asserted. This condition
can occur when the Target begins a Message In, Status or
Data In phase.
When the Target switches the SCSI Data Bus direction from
in (the Target driving) to out (the Initiator driving) it will release
the SCSI Data bus within a Deskew delay (45ns) of negating
1/0. This condition can occur when the Target begins a
Message Out, Command or Data Out phase.
Note that the Processor must delay at least 800ns after
issuing a Set Phase type command before writing to the
byte counter. The phase will be generated upon writing to
the LSB of the Byte Count register. Phases must not be
changed unless the FIFO is empty.
Bit 1 Set Data In Phase
Setting this bit to "1" will cause the MSD95COO to assert
the 1/0 signal and negate the MSG and CID signals.
Bit 2 Set Command Phase
Setting this bit to "1" will cause the MSD95COO to assert
the CID signal and negate the I/O and MSG signals.
Bit 3 Set Status Phase
Setting this bit to "1" will cause the MSD95COO to assert
the CID and 1/0 signals and negate the MSG signal.
Bits 4 and 5 Reserved
Must be set to "0" at all times.
Bit 6 Set Message Out Phase
Setting this bit to "1" will cause the MSD95COO to assert
the CID and MSG signals and negate the 1/0 signal.
Bit 7 Set Message In Phase
Setting this bit to "1" will cause the MSD95COO to assert
the CID, 1/0 and MSG signals.
Set Data Out Phase Setting bits 0-7 to "0" will cause the
SCSIC to negate the MSG, 1/0 and CID Signals.

STATUS 2 REGISTER
8-Bit Read Only (ADDRESS OBH)
This 8 bit Read Only register contains information about the
internal MSD95COO operation.
Bit 0 Valid Selection
This bit is set to "1" when the MSD95COO has been selected
by another SCSI device. In order to be selected, the Enable
Selection bit in the Control Register must be in the correct
state. This bit is reset by reading the Status 2 register.
Bit 1 Valid Reselection
This bit is set to "1" when the MSD95COO has been
reselected by another SCSI device. In order to be
reselected, the Enable Reselection bit in the Control
Register must be in the correct state. This bit is reset by
reading the Status 2 register.
Bit 2 Invalid (Re)Selection
This bit is set to "1" when another SCSI device attempts to
select or reselect the SCSIC and the corresponding enable
bit in the Mode register is not in the correct state. This bit is
reset by reading the Status 2 register.
Bit 3 Successful (Re)Selection Complete
This bit is set to "1" when the MSD95COO has successfully
selected or reselected another SCSI device and that device
has responded by asserting BSY. Also, this bit is set to "1 "
COMMAND 2 REGISTER
at the trailing edge of SEL when a device has selected or
8-Bit Write Only (ADDRESS OAH)
reselected this device. This bit is reset by reading the Status
This Write Only register is used to initiate a new phase when 2 register.
.
the SCSIC is in Target mode. A hard or soft System Reset Bit 4 Unsuccessful (Re)Selection Complete
or a Disconnect command will clear all the bits in this register This bit is set to "1 " when the MSD95COO has attempted to
to "0': When the Initiator detects that the SCSI Data Bus is select or reselect another SCSI device and that device has
690

not responded by asserting BSY within the programmed
Selection Timeout Delay. This bit is reset by reading the
Status 2 register.
Bits Sand 6 Reserved
Bit 7 SCSI ATN
This bit reflects the state of the ATN bit on the SCSI bus. It
is active high when the ATN signal is asserted and active
low when the ATN signal is deasserted.
STATUS 3 REGISTER
a-Bit Read Only (ADDRESS OCH)
This a bit Read Only register contains information about the
internal MSD9SCOO operation.
Bit 0 Byte Requested
This signal is active high whenever there is room for more
requested data in the internal buffer when transferring to
the SCSI Data bus.
Bit 1 Byte Available
This signal is active high whenever there is data from the
SCSI Data bus in the internal buffer for transfer to the
Processor or Ring Buffer RAM.
Bit 2 Parity Error (PE)
This bit is set to "1" if parity checking is enabled and the
SCSI chip detects even (bad) parity on received data
transfers over the SCSI data bus during any Information
phase. It is reset by reading the Status 3 register.
Bit 3 SCSI Transfer Complete (STC)
This status signal is active high when the Byte Counter End
Count condition is active high and the last byte has been
transferred from the SCSI bus into the internal buffer when
the chip is operating in Target mode during Message Out,
Command or Data Out phases. In all other cases, this status
signal will function the same as Transfer Done.
Bit 4 Transfer Done (TO)
This status signal is active high when the Byte Counter End
Count condition is active high and the last byte has been
transferred out of the internal buffer to the SCSI Data bus,
the Processor port or the ring buffer DMA port.
Bit S System Parity Error (SYPE)
This bit is set to "1" when the MSD9SCOO detects even (bad)
parity on the System Data Bus. It is reset by reading the
Status 3 register.
Bit 6 SCSI RESET
This bit reflects the state of the RST bit on the SCSI bus. It
is active high when the RST signal is asserted and active
low when the RST signal is deasserted.
Bit 7 SCSI ATN
This bit reflects the state of the ATN bit on the SCSI bus<. It
is active high when the ATN signal is asserted and active
low when the ATN signal is deasserted.
STATUS 4 REGISTER
a-Bit Read Only (ADDRESS ODH)
This a bit Read Only register contains information about the
internal SCSIC operation.
Bit 0-2 Encoded Phase
These bits are reflections of the SCSI MSG, I/O, and C/O
signals. They identify the SCSI Information Transfer Phase.

Bit2
MSG

Bit1
C/O

BitO
I/O

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
1
1

INFORMATION PHASE
Data Out Phase
Data In Phase
Command Phase
Status Phase
Reserved
Reserved
Message Out Phase
Message In Phase

Bit 3 Busfrpx
This bit goes high fourto five internal clock cycles after BSY
and SEL are both continuously false. The bit remains high
as long as the SCSI bus is free.
Bit 4 Busfree (window)
This bit goes high five to six internal clock cycles after BSY
and SEL are both continuously false. The bit remains high
three to four clock cycles after the bus is no longer free.
BitS Halted
This status bit can only be set when the chip is operating in
Initiator mode. It is set by SREQ going active when the Byte
Counter is "0': It can also be set when a parity error is
detected on the SCSI data bus. This bit is reset by reading
the Status 4 register.
Bit 6 Bus Free Phase Detect
This status signal is the output of the Bus Free detection
circuit. It is latched active high when the Bus Free phase as
specified in the SCSI specification is detected on the SCSI
Bus. This bit is reset by reading the STATUS 4 register.
DESTINATION 10 REGISTER
a-Bit Write Only (ADDRESS ODH)
This a-bit register Write Only is used to hold the value of the
SCSI 10 of the device that is to be Selected or Reselected.
SCSI BUS 10 REGISTER
a-Bit Read Only (ADDRESS OEH)
This a-bit Read Only register holds the 10 that had been
latched from the SCSI bus when an attempt was made to
Select or Reselect this chip. This chip's SCSI 10 is masked
off.
SCSI 10 REGISTER
a-Bit Write Only (ADDRESS OEH)
This a-bit Write Only register is used to hold the value of the
MSD9SCOO's SCSI 10.
DATA IN REGISTER
a-Bit Read Only (ADDRESS OFH)
This a-bit Read Only register is used by the Processor during
programmed I/O or Processor port DMA transfers. It allows
you to read data received from the SCSI bus which is
presently in the internal buffer.
DATA OUT REGISTER
a-Bit Write Only (ADDRESS OFH)
This a bit Write Only register is used by the Processor during
programmed I/O or Processor port DMA transfers. The data
loaded into this register is output to the SCSI bus via the
internal buffer.

691

NOTE: For an updated data sheet please fill out the reply card in
the back of this catalog or call SMC.at (516) 273-3100.
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor appli·
cations: consequently complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the right to
make changes at any time in order to improve design and supply the best product possible.

692

MSD95C02
PRELIMINARY

Storage /1- Controller for Direct Access (Disk) or
Serial Access (Tape) Devices - S/1nDAe™
PIN CONFIGURATION

APPLICATIONS SUPPORTED:

o Embedded SCSI drives when used with companion
MSD95COO SCSI Controller
o Compatible with ESDI and SMD disk interfaces
o Interfaces to 8051, Z8 and 80188 microprocessors
o Supports 3-Sector Prefetch for Unix® applications
o Supports QIC-24 Tape:
o
o
o

~

A15
A14
A13

5 Mb/sec GCR data transfers
Read-alter-write
Controls Optical Disks with commonly available Error
Correction IC's
Supports Floppy Disk
Modular design for easy adaption to special purpose
applications

A12
64
All
65
Al0 L 66

FEATURES:
024 Mb/sec NRZ OR 12 Mb/sec RLL, MFM, FM Disk
Data Transfers
o Zero Latency read capability
Choice ofECC:
Reed-Solomon ECC able to detect and correct a
41 bit burst error or two randomly spaced 17 bit burst
errors without miscorrection; CRC extension to
detect miscorrection of errors beyond that range, OR
32-bit IBM® compatible ECC
Register programmable data format via on-chip
writeable microsequencer
3-Channel internal double-speed 64K (externally
expandable) Ring Buffer DMA controller
Cache buffer management allows disk data transfers
without processor intervention

A9
AS
A7
A6
AS
A4
A3
A2
A1

67
68
1

2
[ 3

r

4

[ 5
[ 6
;:: 7

AQ[,

AD7 [ 9

o

o
o
o

• • ~.M~.gM~gUU.g"

61
62
63

43 J DREQ
42 J RCLK
41 J RGATE
40 J CTL3 (WRFCLK)
39 ~ WGATE
J CTL4 (AMEN)
37
TST4 (INDEX)
36
TST3 (ECCERR)
35 ., TST2 (IBG)
34 J TST1 (AMFND)
33:1 WDATA
32 I CTL2 (LATE)
31 J CTl1 (EARLY)
30 J RDATA
29 I iNf
28JLPS
27 J ALE (AS)

3'

MSD95C02

:i

2

1011121314151617181920212223242526

o Supports transparent "on-the-fly" error correction
o Low power CMOS with Standby Mode
o Available in 68 pin PLCC
o TTL compatible inputs and outputs

GENERAL DESCRIPTION
The MSD95C02 is a high speed micro-programmable of up to 5 megabytes per second.
data path controller. It incorporates a triple channel DMA The DMA CONTROLLER section of the MSD95C02
CONTROLLER, a RAM based MICROSEQUENCER, a controls and arbitrates up to 64K of external Ring Buffer
sophisticated ECC generator/checker circuit, an RLL2, 7/ memory built with standard off-the-shelf static RAM. The
MFM/FM/GCR Encoder/Decoder and a Parallel/Serial shilt Ring Buffer size can be easily expanded beyond 64K with
register in one 68 pin plastic package. The MSD95C02 can the addition of a few additional gates. Disk data transfers to
be combined in a circuit with standard local processor and and from this cache buffer are managed by the MSD95C02's
static RAM chips to build a very high performance multi- internal DMA CONTROLLER and are performed without the
media controller incorporating SCSI, ESDI, SMD, ST-506, need for processor intervention.
QIC 24, and FLOPPY disk interfaces. The RAM based External Device (e.g., SCSI bus) accesses to the Ring Buffer
MICROSEQUENCER permits the user to build a mass are controlled via a DMA request/acknowledge handshake
storage controller that conforms with any currently available and are completely asynchronous with respect to disk and
data format.
local processor transfers. This method of local buffer access
The addition of an SMC MSD95COO SCSI CONTROLLER combined with a powerful Reed Solomon error correcting
will provide a tightly coupled 2-chip set for high speed, high code and CRC extension designed to virtually eliminate
performance SCSI and "embedded SCSI" applications with miscorrection, provides the user with on-the-fly error
minimum component count and synchronous SCSI speeds correction with no loss of disk revolutions.
Unix" is a registered trademark of AT&T Bell Labs.

693

DIRECT DRIVE SCSI BUS

RING BUFFER
(64 K X 8 STATIC RAM)

~
1

D7-0

WE

1

DMA GENERAL
PURPOSE OUTPUTS

/'

~

DB7-0

I

DRIVE

~I O~::'·

DMAA •

CNTLB-5
TST4-1

",. " W,

RCLK

DMAA

MSD 95COO CLKO
SCSI
CONTROLLER
OR
EXTERNAL
DEVICE
ALE, RD, WR, RST

OE

~

IA

o~,

A15-0

RGATE
WGATE

MSD 95C02
DISK CONTROLLER

I\r--

WDATA

,------,/I ALE, RD, WR, RST

-I'>

f----

1--------'

I

WRITE GATE

H

PRECOMPENSATION
LOGIC

EARLY
(CTL1)

O'l
<0

INT

READ DATA

RDATA

DMACLK

t t

WRITE DATA

READIWRITE
HEAD
ELECTRONICS
MOTOR
CONTROL

I

LATE
(CTL2)

1-_--lIINT

I
I

•I

(CTL3)
(CTL4)

AD7-0

CE

CE

t

T

iDECODEi
7 ....

t===
UPPER
ORDER
ADDR.
BUS

ALE
RD
WR
RST

INT

AD7-0
~

GENERAL PURPOSE OUTPUTS

~

I'

1

DRIVE STATUS

-v

7
GENERAL PURPOSE
INPUTS

AD7-0

LOCAL PROCESSOR

FIGURE 1: MSD95C02 EMBEDDED SCSI SYSTEM.

GENERAL PURPOSE
OUTPUTS

--1

1..'_ _ _ _ _ _

ESDI DRIVE
WGATE

WRITE GATE

WDATA

NRZWDATA +
NRZWDATA -

RCLK

RDATA

£

--c

NRZ WRITE CLOCK +
NRZ WRITE CLOCK NRZ READ/REF CLK +
NRZ READ/REF CLK NRZ READ DATA +
NRZ READ DATA -

J

MSD 95C02 RGATE

READ GATE

TST4

INDEX

TST1

ADDR. MARK FOUND

SNS2

ATTENTION

SNS3

COMMAND COMPLETE

SNS4

READY

CTL4

ADDR. MARK ENABLE

~

GENERAL
PURPOSE
OUTPUTS

-V

DRIVE/HEAD SELECT

LOCAL
PROCESSOR
GENERAL
PURPOSE
INPUTS

~

SERIAL COMMAND/STATUS

FIGURE 2: MSD95C02 TO ESDI INTERFACE

The MSD95C02 is built from a set of high level, function
specific SuperCelis ,. that can be connected together in
such a way as to adapt themselves to a special purpose
customer requirement. The first set of SuperCelis ,. has
been chosen to optimize the device for "EMBEDDED SCSI"
and ESDI controller applications. Figure 1 illustrates the
MSD95C02 used with its companion MSD95COO SCSI chip
to form an "EMBEDDED SCSI" system. Figure 2 illustrates
the MSD95C02 used as an ESDI controller.

the ring buffer during local processor updates to
the MSD95COO and MSD95C02 devices. Ring buffer
arbitration is controlled by the on-chip triple channel
DMA CONTROLLER which arbitrates ring buffer accesses
to and from the media, SCSI channel and local processor.
Local processor accesses to the ring buffer are possible
through directly addressable registers in the MSD95C02's
DMAblock.
The MSD95C02 contains several general purpose input!
As can be seen from the system block diagrams, the output pins which can be used to control and monitor
interface to the external static RAM ring buffer requires no external events. In addition, there are four general purpose
external circuitry. In an "EMBEDDED SCSI" environment, test inputs and four latched sense inputs that may be used
there are two external data buses used; one to permit data directly by the MICROSEQUENCER to perform conditional
flow between the MSD95COO SCSI controller and the ring jumps.
buffer and another data bus to permit local processor to The sense inputs, test inputs and control outputs of the
MSD95COO SCSIC and MSD95C02 exchanges. The two MSD95C02 are used to efficiently handle ESDI drives with
data buses allow for uninterrupted data flow in and out of serial data rates up to 24 MHz.
SuperCell'· is a trademark of Standard Microsystems Corporation.
695

CTL7
CTL6,5
OMACLK
A15-0

OB7-0

WE

Ii-'l4~---RAM

TO MSO 95C02

---.'11. 00----

FIGURE 3: TYPICAL BUFFER TIMING (DISK WRITE)

CTL7
CTL6,5
OMACLK
A15-0
WE

OB7-0

OE
OACK

I.

_ - - M S O 95C02 TO RAM

----*0----

FIGURE 4: TYPICAL BUFFER TIMING (DISK READ)

696

PINOUT DESCRIPTION
RING BUFFER INTERFACE (Refer to Figures 3 and 4 for ring buffer timing)·

PIN NO.
53-60

SIGNAL NAME
DB7-0

61-68,1-8 A15-0

DESCRIPTION
Data Bus. Bi-directional data bus to the external ring buffer RAM. This bus is
automatically put into a high impedance state during valid External Device
DMAcycles.
Address Bus. These outputs are used to address the external ring
buffer RAM.
Output Enable. This active low output strobes the ring buffer RAM's data
bus output drivers.
Write Enable. Strobe. This active low output strobes write data from the data
bus into the ring buffer RAM.
DMA Clock. This 20 MHz (maximum) input is used by the MSD95C02 to
generate DMA cycles.
DMA Request. This input is driven active low by an External Device to
request a DMA cycle.
DMA Acknowledge. This output is driven active low by the MSD95C02 in
response to DREQ. During data transfer from the ring buffer to the External
Device, the rising edge of this signal is used to strobe data into the External
Device. During data transfer from the external device to the ring buffer, a low
will enable data transfer from the External Device.
Control 5.
Control 6. Depending on the programming of the MODE 1 Register, these
bits can either reflect the data written to bits 4 and 5 of the Local Processor
Output Register or they can be outputs that indicate the type MSD95C02
DMA controller cycle in progress:
ST1 STO CYCLE
0
0 EXTERNAL DEVICE
1 LOCAL PROCESSOR
0
1
0 MICROSEQUENCER (DISK)
1
1 RESERVED
Control 7. Depending on the programming of the MODE 1 Register, this bit
can either reflect the data written to bit 6 of the Local Processor Output
Register or this bit can be an output signal indicating to the ring buffer that a
WRITE or READ cycle is about to start. This output is low during a write
cycle and high during a read cycle. CTL 7, 6, and 5, when programmed as
WRITE, STO, ST1, can be used for interfacing to an external ECC chip.
Control 8. Depending on the programming of the MODE 1 Register, this bit
can reflect the data written to bit7 of the Local Processor Output Register. It
may also be used as an output of the MICROSEQUENCER to be used as a
"data valid" signal to indicate when data is being transferred on the DB7-0
bus for interface with an external ECC chip.

110
I/O

0

50

OE

0

51

WE

0

49

DMACLK

I

43

DREQ

I

44

DACK

0

45
46

CTL5(ST1)
CTL6(STO)

0
0

47

CTL7 (WRITE)

0

48

CTL8 (DGATE)

0

DRIVE INTERFACE·

PIN NO.
30

SIGNAL NAME
RDATA

I/O
I

41

RGATE

0

42

RCLK

I

33

WDATA

0

39

WGATE

0

DESCRIPTION
Read Data. This signal is the/serial data from the disk or tape drive. It
may be encoded as RLL2, 7, MFM, FM, GCR, or NRZ as selected in
MODE Register bits 2-0.
Read Gate. This output is typically used to enable the data separator to
begin locking to data. Normally, it becomes active during the PLO sync
field. This signal is controllable via microcode to allow specific read data
search algorithms and conformance to unique drive formats.
Read Clock (Read/Reference Clock). This input clock is used to frame
the encoded RDATA bit stream from the drive. For NRZ input data, the
Read/Reference Clock signal provides the timing necessary to
synchronize the serial data transfer between the drive and the
MSD95C02. RCLK is divided internal to the MSD95C02 and is used to
run the MICROSEQUENCER. It is therefore necessary to continually
provide a glitch-free clock into this input at all times.
Write Data. This output is the serial NRZ, FM, MFM, GCR or RLL data
being written to the drive.
Write Gate. This output is controlled by the microsequencer and is
active when the MSD95C02 is writing data to the drive.
697

PIN NO.
31

PINOUT DESCRIPTION CONTINUED
DESCRIPTION
I/O
Control 1. Depending on the programmi(1g of the MODE Register, this bit
0
either reflects the data written to bit 0 of the Local Processor Output
Register or indicates that the current disk Write Data bit should be
externally precompensated early.
Control 2. Depending on the programming of the MODE 3 Register, this
0
bit either reflects the data written to bit 1 of the Local Processor Output
Register or indicates that the current disk Write Data bit should be
externally precompensated late.
I/O
Control 3. Depending on the programming of the MODE 3 Register, this
bit either reflects the data written to bit 2 of the Local Processor Output
Register or acts as a tape write reference clock input. In tape
applications that require read after write capability, this pin must be
programmed as an input (WRFCLK).
Control 4. Depending on the programming of the MODE 2 Register, this
0
bit either reflects the data written to bit 3 of the Local Processor Output
Register or acts as a MICROSEQUENCER output which may be used
to write an Address Mark (WGATE active) or search for an address mark
(WGATE, RGATE inactive) in ESDI drive applications.
I
Sense Input 4. The MSD95C02 can be programmed to generate any
level change interrupt from this pin. This input may be used to sense
READY status from the drive.
I
Sense Input 3. The MSD95C02 can be programmed to generate a
high-to-Iow level change interrupt from this pin. This input may be used
to indicate a Command Complete status when using ESDI drives.
I
Sense Input 2. The MSD95C02 can be programmed to generate a
high-to-Iow level change interrupt from this pin. This input may be used
to sense ATTENTION status from an ESDI drive or a WRITE FAULT
status from an ST-506 drive.
I
Sense Input 1. The MSD95C02 can be programmed to generate a
high-to-Iow level change interrupt from this pin. This input may be used
to sense load pOint status for tape applications.
I
Test Input 4. This input is used by the MICROSEQUENCER for
conditional branching. Typically, the INDEX pulse from the drive is
connected to this pin.
I
Test Input 3. This input is used by the MICROSEQUENCER for
conditional branching. When used with an external ECC chip, this input
may be used to indicate an ECC error.
I
Test Input 2. This input is used by the MICROSEQUENCER for
conditional branching. An external signal indicating interblock gap for
tape applications may be connected to this pin.
I
Test Input 1. This input is used by the MICROSEQUENCER for
conditional branching. Typically, an ESDI address mark found signal is
connected this pin.

SIGNAL NAME
CTL 1 (EARLY)

32

CTL2(LATE)

40

CTL3 (WRFCLK)

38

CTL4(AMEN)

19

SNS4 (READY)

20

SNS3 (CMDDN)

21

SNS2 (ATTNIWFLT)

22

SNS1 (LDPT)

37

TST4 (INDEX)

36

TST3 (ECCERR)

35

TST2(IBG)

34

TST1 (AMFND)

PROCESSOR INTERFACE"
PIN NO.
9-12,
14-17
27

SIGNAL NAME
AD7-0

I/O
I/O

ALE (AS)

I

29

INT

0

26

RD(DS)

I

25

WR(R/W)

I

DESCRIPTION
Address/Data Bus. Multiplexed bi-directional address/data bus to local
processor.
Address Latch Enable (Address Strobe). This signal is active when an
address is valid on the AD7-0 bus. The local processor reads the
MSD95C02 RESET Register address either following a hard or prior to a
soft reset to automatically configure the MSD95C02 to expect ALE or AS at
this input.
Interrupt. This open collector output is driven low when the MSD95C02
detects an enabled interrupt. This pin has an internal MOSFET which
functions as a pull-up.
Read Strobe (Data Strobe). When the MSD95C02 is configured for ALE,
this active low strobe is used to enable read data from the MSD95C02 onto
the AD7-0 bus. When the MSD95C02 is configured for AS, this active low
signal is used to strobe data into or out of the MSD95C02.
Write Strobe (ReadIWrite). When the MSD95C02 is configured for ALE, this
active low strobe is used to latch write data from the AD7-0 buslDto the
MSD95C02. When the MSD95C02 is configured for AS, the RIW input is
used to qualify DS for a read or write cycle.
698

PIN NO.
24

PINOUT DESCRIPTION CONTINUED
1/0
DESCRIPTION

SIGNAL NAME
CE

I

28

LPS

I

23

RST

I

18
13
52

VCC
GND1
GND2

P
P
P

Chip Enable. This input signal is used to qualify the RD and WR strobes for
all accesses on the AD7-0 bus. This signal must be valid throughout the
memory cycle.
Low Power Standby. A low level applied to this input signifies that the system
is requesting the low power standby mode.
Reset. A low level at this input will cause the MSD95C02 to be reset (hard
reset) to a known state. Reset will cause the following 1/0 pins to be forced
to the states indicated:
DB7-0
Input
OE
Inactive High
WE
Inactive High
DACK
Inactive High
RGATE
Inactive Low
Inactive Low
WGATE
AD7-0
Input
INT
Inactive High
CTL1 (EARLY)
Inactive Low
CTL2(LATE)
Inactive Low
CTL3 (WRFCLK)
Input
CTL4(AMEN)
Inactive Low
Power connection
Ground connection
Ground connection

OVERVIEW OF MSD95C02 REGISTERS
Figure 5 shows the MSD95C02 address map. The 256
locations are internally decoded from the lower 8 bits of the
address bus. Valid decode space exists from address 40H
to FFH as shown. Address OOH to 2FH is not decoded by
the MSD95C02 and can be used as register space for the
External Device. The MSD95COO SCSIC uses address OOH
to OFH for its internal register space, allowing the
MSD95COO and the MSD95C02 to share the same chip
select decoded from the upper address bits of the local
processor's address bus.
The MSD95C02 address space accessible to the local
processor can be broken into four sections as follows:
ADDRESS 40H-5FH
This address space contains the MSD95C02 working
registers which include mode registers, setup registers,
interrupt enable registers, status registers, and DMA
parameter registers.
ADDRESS 60H-6FH
This address space contains an on-chip 16 byte registerfile
referred to as the DESIRED REGISTER FILE. It is shared
by the local processor and the MICROSEQUENCER and
is typically loaded by the local processor and internally
compared with data from the disk. Local processor access
to this address space should only occur when the
MICROSEQUENCER is not running.
ADDRESS 70H-1FH
This address space contains an on chip, 16 byte, register
file referred to as the CURRENT REGISTER FILE. It is
shared by the local processor and the MICROSEQUENCER
and is typically loaded with data from the disk for
examination later by the local processor. Local processor
access to this address space is only allowed during certain
MICROSEQUENCER initiated interrupts to the local
processor.

microcode used by the MICROSEQUENCER. Internally,
these bytes are arranged as 32 locations by 32 bits wide.
Local processor address 80H corresponds to the least
significant byte (07-0) of word zero of the microcode RAM.
This address space should not be accessed by the local
processor while a microprogram is running.
OOOH-

I

32 EXTERNAL (SCSI) DEVICE
LOCATIONS

I

FREE ADDRESS SPACE

I

MSD95C02 REGISTERS (reserved
for future expansion)

I

MSD95C02 REGISTERS

I

(16) MSD95C02 DESIRED
REGISTER FILE

I

(16) MSD95C02 CURRENT
REGISTER-FILE

01FH020H02FH030H03FH040H05FH060H06FH070H07FH080H-

I
I
I

MSD95C02 MICROCODE

OFFH-

FIGURE 5: MSD95C02 ADDRESS MAP

Figure 6 shows the internal block diagram of the
MSD95C02. The data flow through the chip occurs on the
INBUS and the OUTBUS. The OUTBUS connects all data
coming from the ring buffer to the drive and the INBUS
connects ~II data from the drive to the ring buffer. There are
six blocks that make up the MSD95C02 disk controller as
ADDRESS 80H-FFH
shown in the block diagram. Each block will be described
in detail in the following sections.
This address space contains the 128 bytes of loadable
699

WE

A15-0

5E

~~ ~~

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~"
H<

u~

0~

DB7-0

DMACLK

ECCBLOCK

DMAR
DMAA

M
A
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is
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REED SOLOMON
ECCCHECKER

L

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o
X

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m

I

~

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DMABLOCK

i:

(J)

ENCODER
DECODER
BLOCK

c

~

n

RDATA

N

RCLK

0

81

z

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m

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::a
z

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r0

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f---+"WGATE

I

WDATA

I

TST4-1

I

CTL3
(WRFCLK)

I

MICROSEQUENCER PROGRAMMED BIT
CTL4

~

LOCAL PROCESSOR PROGRAMMED BIT

_________________ J

i:
SNS4-1

CPS
RST

...J
r--------------------T
I
I
MICROCOMPUTER INTERFACE BLOCK

I
I

V

II

I

I
I

INTERNAL
INTERRUPT
CONDITIONS

I
I
I

TO ALL
.) BLOCKS

I
TNT

CTl2
(LATE)
CTL1
(EARLY)

m

lAS)

AD7-0

WFiRDEE
(RW)(DS)

ECCBLOCK

MSD95C02 REGISTERS
WRITE REGISTERS

07

06

I

05

04

03

02

READ REGISTERS

01

00

(RESERVED)

I

(RESERVED)

MODE 1

MODE 2

(RESERVED)

MODE3

07

MODE4

40H

I

06

05

04

03

02

41H

(RESERVED)

42H

(RESERVED)

43H

(RESERVED)

44H

(RESERVED)

MODE5

(RESERVED)

45H

(RESERVED)

SYNC 1

SYNC DATA

46H

(RESERVED)

SYNC 2

SYNC DATA

47H

(RESERVED)

SYNC 3

SYNC DATA

48H

(RESERVED)

SYNC 4

SYNC DATA

49H

(RESERVED)

4AH

(RESERVED)

4BH

(RESERVED)

4CH

(RESERVED)

TAPE BYTE
COUNTER

TAPE HIGHI
BYTE

UNUSED

TAPE LOW I
BYTE

TAPE BYTE COUNTER

I-LC
OUTPUT

eTL

8

CTL
7

,

CTL

eTL

eTL

5

4

ENA~IE 1 I MAS I OMA I~~RVEOI DONE I
INT
ENABLE 2

,

CTL

CTL
2

eTL
1

(RESERVED)

01

00

(RESERVED)

4DH I MAS I OMA I~~RVEOI DONE I

(RESERVED)

I

RESET

I ENABLE
INT
1

4EH

4FH
701

INT
ENABLE 3

WRITE REGISTERS

READ REGISTERS

07 06 05 04 03 02 01 00
07 06 05 04 03 02 01 00
FU~~tlONI FCTN I SOURCE I DEST 150H I
(RESERVED)
I
M~II'cr~X I DMA ADDR RAM DATA (MSB'S) 151 HI DMA ADDR RAM DATA (MSB'S) I M~II'cr~X
M~btlJ°X I DMA ADDR RAM DATA (LSB'S) I 52H I DMA ADDR RAM DATA (LSB'S) I M1~tlJ°X

OATA ~__R_I_NG_-_B_U_FF_E_R_D_A_JA__~153HLI___R_I_NG_-_B_U_FF_E_R_D_A_JA__~I O~A
START
CMD
(RESERVED)
L-_---=--(R_E_sE_R_v_ED--'-)_ ___'56H
'--____("-R_E_SE_R_V_E_D"-)______'I

I~~ I~~N~G I:~ I

57H I

BUSY

(RESERVED)

I STATUS
(PROG)2

I RESERVED) I PROGRAM COUNTER 1(~~U8~R)

(RESERVED)
'--__~(_RE_S_E_R_VE_D~)______'159H~1____~(_RE_S_E_RV_E_D~)______'

~____(_R_E_SE_R_V_E_D_)____~15AH~1_____(_R_E_SE_R_V_E_D_)____~
'--__~(_RE_S_E_RV_E_D~)______'15BH~1_____(_RE_S_E_RV_E_D_)____--'
'---_ _(R_E_S_ER_VE_D_)_----'15CH

I

Tr

I rr I rr I T~T I s~s I s~ I s~s I s~s I ItJP~T

(RESERVED)

150H I

(RESERVED)

(RESERVED)

15EH I

(RESERVED)

(RESERVED)

15FH I
702

(RESERVED)

DMACLK-_
DMAR

INTERNAL
REQUESTS

WE

A15-0

DE

CTL5
(ST1)

CTL6 CTL7
CTL8
(ST0) (WRITE) (DGATE)

oB7-0

DMAA

RING BUFFER
TIMING AND
CONTROL
LOGIC

LOCAL PROCESSOR
PROGRAMMED BITS

M
A
I

L
B
0
X
16

INBUS

OUTBUS

ZERO

OFFSET
REGISTER
AUXOFFSET
REGISTER

AUX ZERO

ZOFF
TO MICROSEQUENCER

FIGURE 7: DMA BLOCK DIAGRAM

COUNTER since there is a relationship between the value
in the OFFSET COUNTER and the amount of available free
DMA CONTROLLER
space there is in the buffer and available error free data there
The three channel DMA controller is composed of a 6 X 16 is to transfer out on the External channel. The local
bit register file, two OFFSET COUNTERS for monitoring processor channel might be required to perform read modify
ring buffer full/empty status, a DMA FUNCTION Register write routines during error correction operations.
to indirectly address the register file, a ring buffer DATA Local Processor channel operation:
Register, andALU to perform incrementing (by 1, 2, 3 or 4)
and in addition, a 16 bit mailbox register, state controller and The local Processor can specify the address operation to
be performed during its channel access via the DMA
DMA request priority resolver.
Channel access to the ring buffer comes from three sources. FUNCTION Register which is a write only local processor
addressed register (assigned address 50HEX). This
The MICROSEQUENCER requests are initiated by the
function register permits the loading of all registers in the
DISK INTERFACE block for every byte transferred to/from
register file which are not directly addressable from the
the MICROSEQUENCER and is given top priority. Local
processor accesses to the ring buffer are initiated by direct external local processor.

DESCRIPTION OF INDIVIDUAL BLOCKS

operation of the local processor on the addressable registers The Local Processor can directly access four registers in
within the DMA controller. The local processor is given the DMA controller. They are:
second priority. External Device access (like SCSI) is DMA FUNCTION Register (write only) address 50H
initiated via a DMA request-acknowledge handshake and MAILBOX HIGH Register (read/write) address 51 H
is given third priority.
MAILBOX LOW Register (read/write) address 52H
ALU and Register function:
DATA Register (read/write) address 53H
For each DMA channel, specific register manipulations are The local processor can indirectly access 6 additional 16 bit
possible depending upon the operation required. Each registers that make up the DMA register file. These registers
channel will have different requirements on the way the are accessed by using the DMA FUNCTION Register. An
address to the ring buffer is updated. For instance, during example of their use is illustrated as follows:
disk read operations, the channel must ensure that the
starting address for a sector transfer is not updated until the CONSTANT 1-Normally used to hold the sector size and
data transferred into the ring buffer is known to be error free. in calculating address updates and ring buffer status flags.
The External Device, during a read operation from the ring CONSTANT 2-Normally used to hold a number that is a
buffer, must cause the address to be incremented for each function of the Ring Buffer size for generating Ring Buffer
byte transferred. It must also update the OFFSET empty/full status.
703

LOCAL PROCESSOR ADDRESS Register-Holds the
current address of a local processor to ring buffer data
transfer.
EXTERNAL DEVICE ADDRESS Register-Holds the
current address of an External Device to ring buffer data
transfer.
DISK Register-Maintains the address of the first location
of a MICROSEQUENCER initiated disk transfer until data
integrity is established.
DISK ADDRESS Register-Holds the current address of
a MICROSEQUENCER initiated disk ring buffer data
transfer.
Refer to Appendix 2 for a description of how these registers
are set up for particular DMA operations.
DMA FUNCTION Register:
BITS 07-D6. These bits specify the operation to be
performed on the contents of a register in the internal register
file:
D7 D6
0 0

FUNCTION
SOURCE + OFFSET COUNTER ~
DESTINATION (Note 1)
0 1
SOURCE + N ~ DESTINATION;
DECREMENT OFFSET COUNTER
1 0
SOURCE ~ DESTINATION
1 1
SOURCE + N ~ DESTINATION
TABLE 1: DMA FUNCTION REGISTER OPERATION
N = 1 for disk and local processor data transfers
N specified by MODE 1 Register for External channel (SCSI)
data transfers
Notes:
1. For this case, the only destinations that can be updated
are the OFFSET COUNTER and the MAILBOX. All other
destinations will cause the OVERFLOW flag to be updated
as a function of the result out of the ALU, but will not update
the destination.
2. When the controller changes the contents of the
OFFSET and AUXILIARY OFFSET COUNTERS, it must
set or clear the zero bit via the START COMMAND Register
bits 4 and 3.
3. The OFFSET COUNTER cannot be used as a source. If
it is used as a source, it will take on the value of zero. During
error correction, it becomes necessary to use the OFFSET
COUNTER as a source. See appendix 3 for a description
of ERROR CORRECTION ON THE FLY for more detail.

Disk Channel Access Operation:
Disk requests for data transfer are initiated by the
MSD95C02's internal MICROSEQUENCER. For normal
data transfer between the disk and the ring buffer, the
MICROSEQUENCER causes the DISK ADDRESS in the
DMA block to be incremented by one between ring buffer
access cycles.
In addition, the MICROSEQUENCER may perform some
housekeeping functions at each sector boundary if required.
These housekeeping functions may include updating the
OFFSET COUNTER, determining buffer full/empty status,
etc.
In order to specify one of many housekeeping calculations,
the MSD95C02's internal MICROSEQUENCER has the
ability to specify the operation by loading a DISK DMA
FUNCTION Register (different from the local processor
addressable DMA FUNCTION Register). The bit definitions
of this register are identical to the DMA FUNCTION Register
as defined in Tables 1 and 2. The MICROSEQUENCER can
load the DISK DMA FUNCTION Register by transferring a
value previously stored in the DESIRED REGISTER FILE
to the DMA block.
EXTERNAL DEVICE CHANNEL ACCESS OPERATION:
Upon an external DMA request, this channel wUI perform
one hardwired function consisting of proper adjustment of
the current ring buffer address as well as decrementing the
OFFSET COUNTERs for current handling of ring buffer full/
empty situations. The MSD95C02 can buffer a maximum
of 12 DMA requests before issuing an acknowledgment
without causing an overrun/underrun condition. The
MSD95C02 uses the leading edge of DMA Request to post
the EXTERNAL channel access. This permits ·the
MSD95C02 to work with several REQ-ACK timing situations.
For External Device DMA operations, the DMA hardwired
function performed is:
EXTERNAL DEVICE ADDRESS + N ~ EXTERNAL
DEVICE ADDRESS.
N is used to permit various data bus widths between the
ring buffer and the External Device as shown in table 3.
N
DATA BUS WIDTH
1
SBITS
2
16BITS
24 BITS
3
4
32 BITS
TABLE 3: EXTERNAL DEVICE BUS WIDTHS AS A
FUNCTION OF N

The value N is programmed by the Local Processor in MODE
1 Register, bits 5 and 4.
OFFSET COUNTER:
These bits select the register file address location(s) The OFFSET COUNTER is part of the automatic
accessed by the operation specified by bits D7 and D6.
housekeeping function of the DMA block and is used to keep
track of buffer empty/full conditions.
D5 D4 D3
During External Device to Ring Buffer to Disk operations
D2 D1 DO REGISTER SELECTED
(WRITE the diSk), the OFFSET COUNTER keeps track of
0 0 0 MAILBOX HIGH, LOW
the number of free bytes left in the buffer. Whenever the Ring
0 0 1 OFFSET COUNTER
buffer size minus the OFFSET COUNTER is less than the
0 1 0 CONSTANT 1
sector size (indicating that there is less than a sector's worth
0 1 1 CONSTANT 2
of data in the ring buffer), the disk WRITE is temporarily held
1 0 0 LOCAL PROCESSOR ADDRESS
off. The throttling of the Disk DMA channel as a function of
1 0 1 EXTERNAL DEVICE ADDRESS
buffer space status is done automatically by the DMA
1 1 0 DISK REGISTER
controller without local processor intervention.
1 1 1 DISK ADDRESS
During Disk to Ring Buffer to External Device (READ the
TABLE 2: DMA FUNCTION REGISTER SOURCEIDEST disk) operations, the OFFSET COUNTER keeps track of
704
BITS D5-D3. Source register file Address
BITS D2-DO. Destination register file Address

the total data bytes left in the buffer. Whenever the Ring
Buffer size minus the OFFSET COUNTER is less than the
sector size (indicating that there is not enough room in the
buffer to accept another sector), the disk READ is
temporarily held off. The throttling of the Disk DMA channel
as a function of buffer space status is done automatically
by the DMA controller without local processor intervention.
Decisions by the MICROSEQUENCER regarding buffer
empty/full status are made by interrogating the ZOFF flag
whenever an ALU operation loads a zero into the OFFSET
COUNTER.
AUXILIARY OFFSET COUNTER operation:
The AUXILIARY OFFSET COUNTER is loaded and
modified along with the OFFSET COUNTER. It is required
because data transferred from the disk into the Ring Buffer
might contain errors. Because of this, the AUXILIARY
OFFSET COUNTER might be different from the OFFSET
COUNTER and is used to control the flow of data between
the External Device and the Ring Buffer. During External
Device to Ring Buffer transfers, the AUXILIARY OFFSET
COUNTER keeps track of the number of free bytes left in
the buffer. During Ring Buffer to External Device transfers,
the AUXILIARY OFFSET COUNTER keeps track of the
number of error free data bytes left in the buffer.
The OFFSET and AUXILIARY OFFSET COUNTERS are
linked together until an error is detected on data read from
the disk. When this occurs, only the OFFSET COUNTER
is incremented as new data is transferred from the disk to
the Ring Buffer. The AUXILIARY OFFSET COUNTER is
not incremented until the error is corrected. Both counters
are decremented when data is transferred from the Ring
Buffer to the External Device. If the error is corrected before
the AUXILIARY OFFSET COUNTER is decremented to
zero, then the two counters are linked back together by
transferring the contents of the OFFSET COUNTER into
the AUXILIARY OFFSET COUNTER in response to a DMA
FUNCTION Register command. If the AUXILIARY OFFSET
COUNTER is decremented to zero before the error is
corrected, the MSD95C02 will not respond to DMA requests
from the external device until the AUXILIARY OFFSET
COUNTER and OFFSET COUNTER are linked back
together. See Appendix 4 for a further description of the
OFFSET and AUXILIARY OFFSET COUNTERs during
error correction on the fly.
Status Flags:
The DMA block will generate three status flags which can
be used by the MICROSEQUENCER to test and make
decisions on the microprogram flow. These three status
flags, defined as follows, are also readable by the Local
Processor in STATUS 1 Register (ADDR 55H):
OVERFLOW: This flag indicates the result of the current
operation performed by the ALU; if the arithmetic yields an
overflow, this bit will be set. This bit is available to the Local
Processor in STATUS 1 Register, bit 05.
ZERO: This flag is set to a one when the OFFSET
COUNTER is decremented to zero. This bit is available to
the Local Processor in STATUS 1 Register, bit 06.
AUX ZERO: This flag is set to a one when the AUXILIARY
OFFSET COUNTER is decremented to zero. This bit is
available to the Local Processor in STATUS 1 Register, bit

ECC ON THE FLY:
The three channel DMA arrangement provides the user with
the ability to perform error correction on the fly without loss
of a disk revolution. In general, upon disk read operations,
one sector may be transferred from the Ring Buffer over the
EXTERNAL channel, one sector may be operated on by the
Local processor for error correction, and the third sector may
be read from the disk and written into the Ring Buffer. Refer
to Appendix 4 for further description of ECC on the fly.

MICROSEQUENCER
As shown in Figure 8, the MICROSEQUENCER consists
of a 32 X 32 microcode RAM, a 7 bit loop counter, a one
address STACK, a sophisticated next address generator
and two 16 byte register files. During next address
generation, the Program Counter can be loaded from the
STACK, from the ADDRESS FIELD output by the microcode
RAM (ADDR 4-0), or from the current or incremented value
in the Program Counter.
The Local Processor can initiate Command execution (eg.
a Read Command) by writing to the COMMAND START
Register (ADDR 54 HEX). The MSD95C02 will then begin
execution at address zero in the microcode RAM. From this
time until the command terminates, program flow is
dependent on which of the several sources are specified
when the Program Counter is loaded. Selection of the next
address is dependent on the Sequence control field (SEQ
2-0), and internal and external test points which are input
to the Next Address Control PLA. Test points are chosen
via the Test field (TEST 3-0) for interrogation and program
flow of the MICROSEQUENCER.
Contained within the MICROSEQUENCER block are two,
16 byte register files named DESIRED and CURRENT
REGISTER FILEs. In general, the MICROSEQUENCER
reads the DESIRED REGISTER FILE and writes the
CURRENT REGISTER FILE. The Local Processor can read
or write either register file. Local Processor access to these
register files are restricted and controlled by interrupts
generated by the MICROSEQUENCER to the Local
Processor. This limited access is required to resolve the
access contentions to these register files by both the Local
Processor and the MICROSEQUENCER.
In addition to the DESIRED and CURRENT REGISTER
FILEs, there is a comparator structure set up to compare
contents in the two register files as shown in Figure 8. Any
information loaded by the local processor in the DESIRED
REGISTER FILE may be compared with the data that is
depOSited in the CURRENT REGISTER FILE as it is filled
with data read from the disk. The sequence and number
of compares made are all initiated under
MICROSEQUENCER control. Typically, the compares can
be performed to determine whether a particular 10 field had
been encountered.
The contents of any DESIRED REGISTER FILE location
can be incremented under MICROSEQUENCER control.
Typically, this can be used to increment the sector number
in the DESIRED REGISTER FILE location when performing
consecutive logical sector operations.
In addition, the CURRENT REGISTER FILE can, under
MICROSEQUENCER control, be loaded with the error
syndrome bytes for examination by the Local Processor
07.
during an error correction operation.
The ZERO and AUX ZERO flags are not set if the OFFSET In typical applications, the CURRENT REGISTER FILE
and AUXILIARY OFFSET COUNTERS are loaded with a holds data such as the current header information (head #,
zero.
sector #, track #) and the writing to these registers is
The MICROSEQUENCER can interrogate the logical OR controlled by the MICROSEQUENCER as data is converted
of the ZERO and AUX ZERO flags via the test input ZOFF. from serial to parallel in the DISK INTERFACE block. The
705

FROM
DMABLOCK

!!

G')

k:

C

:D

m

II

FROM DISK
INTERFACE BLOCK

CCI

s:::

(;
:D

0

tn

p

0

C r--~-I)I ADDR

m

.oen. I cZm

MICROCODE
RAM
(32 X 32)

n
m

:D

m

6n

~TODISK

..------. ~ INTERFACE BLOCK

INBUS

OUTBUS

'c"

~:D

»
s:::
CTL4

~
:
U
X

MICROSEQUENCER PROGRAMMED BIT
LOCAL PROCESSOR PROGRAMMED BIT

DESIRED REGISTER FILE holds information such as the
desired sector to be operated on in a READ or WRITE DISK
operation. The desired header information, in this case is
written into the DESIRED REGISTER FILE by the Local
Processor prior to the execution of the READ OR WRITE
command in an order that is consistent with the order in
which the MICROSEQUENCER loads and compares the
CURRENT REGISTER FILE.
The 32 bit microprogram word definition contains a total of
8 separate fields as shown in Figure 9.
DESCRIPTION OF INDIVIDUAL FIELDS:

D31

SEQUENCE CONTROL
(3 BITS)

D29
D28

-

ADDRESS
(5 BITS)

D24
023

TEST CONDITIONS
(4 BITS)

D20
D19

AD7-0 --i

-

SEQUENCE CONTROL FIELD (D31-29):

REGISTER POINTER
(4 BITS)

D16

POINTER DECREMENT
ENABLE

015

The SEQUENCE CONTROL FIELD determines the next
address loaded into the PROGRAM COUNTER which
feeds the MICROSEQUENCER RAM. Depending upon
which SEQUENCE CONTROL FIELD is specified, the next
address might remain at the current address, increment, use
the value stored in the STACK, or use the value specified in
the ADDRESS FIELD. In addition, it can cause the current
value in the PROGRAM COUNTER to be pushed on the
STACK. The STACK is one address deep. The END COUNT
and TEST POINT can affect the next address generation
and STACK operations in a number of ways. See section
on the TEST FIELD and COUNT FIELD for a descrilltion of
the various conditions that will produce a valid TEST POINT
or END COUNT.

D14

-

COUNT
(7 BITS)

D8
07

OUT
(4 BITS)

D4
D3

-

EXT
(4 BITS)

DO

FIGURE9: 32 BIT MICROSEQUENCER PROGRAM
WORD DESCRIPTION

SEQUENCE CONTROL FIELD DEFINITION:
1
TEST POINT
D31-29
END COUNT
1
OPERATION
MNEMONIC
SHLP
000
PC+1
PC =
D28-24
(SHORT LOOP)
STACK =
LGLP
001
PC+1
PC =
D28-24
(LONG LOOP)
STACK =
STACK
RC
010
PC =
(RETURN OR CALL)
STACK =
D28-24
CI
01 1
PC =
(CALL OR INCREMENn
STACK =
PC+1
TSJ
100
PC+1
PC =
(TEST JUMP)
1 01
TSC
PC =
PC+1
(TEST CALL)
STACK =
TSJL
110
PC =
PC+1
(TEST JUMP LONG)
111
PC+1
TSCL
PC =
(TEST CALL)
STACK =
..
1. DS28-24 IS the address as speCified In the ADDR field of the microcode word .
2. - = no change.

ADDRESS FIELD (D28-24):
The Address Fjeld bits in the microcode instruction may be
directly loaded into the Program counter when executing
"jump" and "cali" instructions. When executing a cali
instruction, the current(or next} Program Counter value may
be saved on a one address STACK. "Return" instructions
can be implemented by loading the contents of the STACK
back into the Program Counter. It should be noted that
subroutines can only be nested one deep.

1
0
PC

0
1
PC+1

-

-

PC

PC+1

0
0
PC

-

PC

-

-

-

PC

-

-

D28-24
PC+1
PC+1

-

-

PC+1

D28-24

PC

PC+1

D28-24
PC+1 ,
D28-24

-

D28-24
PC+1

-

-

PC

-

PC+1
PC+1

-

PC
PC

PC
PC
PC

TEST CONDITIONS FIELD (D23-20):
The test condition field permits the MICROSEQUENCER
to test one of 16 conditions for the purpose of conditional
jumps and calls as specified in the SEQUENCE
CONTROL FI ELD. These 16 inputs originate in the
MICROSEQUENCER block and other blocks and four of
the test points are general purpose inputs from outside the
MSD95C02 appearing .on pins TST1-4.

707

TEST FIELD DEFINITION:
023
0
0

022
0
0

021
0
0

020
0
1

TEST POINT SELECTED
FORCE ZERO
DC GAP

0

0

1

0

SYNC

0

0

1

1

NDERR

0
0
0
0
1

1
1
1
1
0

0
0
1
1
0

0
1
0
1
0

TSTl
TST2
TST3
TST4
EQ8

1

0

0

1

LNEQ

1

0

1

0

XEND

1

0

1

1

NTP2

1

1

0

0

CMD

1

1

0

1

NOVERFLOW

1

1

1

0

ZOFF

1

1

1

1

ONE

REGISTER POINTER FIELD (019-16):
The REGISTER POINTER FIELD is associated with the
DESIRED and CURRENT REGISTER FILES and specifies
the address of the particular register file location to be
operated on. The DESIRED and CURRENT REGISTER
FILEs have a common address such that the same
corresponding location in each file may be operated on at
the same time.
POINTER DECREMENT FIELD (015):
This one bit field permits one to access sequentially
decrementing locations in the DESIRED and CURRENT
REGISTER FILEs for multiple operations within these
registers.

DEFINITION
Forces the TEST input to a logic zero.
From the ENCODER/DECODER block
indicating that no transitions have occurred on
the RDATA input pin for 15 WRFCLKs.
From the DISK INTERFACE block indicating a
16 bit high speed compare between disk data
and the MICROSEQUENCER selected SYNC
Register(s) .
From the DISK INTERFACE block indicating
that a CRC-16, ECC-32 or Reed Solomon ECC
data error has occurred. A zero indicates a
data error.
Input pin TST1.
Input pin TST2.
Input pin TST3.
Input pin TST4.
This input reflects the status of an 8 bit
compare between the INBUS and the
DESIRED REGISTER FILE.
Indicates that one of the previous 8 bit
compares or the current 8 bit compare is
not equal.
Indicates that the contents of a DESIRED
REGISTER FILE location has been
incremented to all zeros.
This is an auxiliary test input which is the
logical OR of three independent conditions. It
is equal to either a HALT (local processor
initiated via Register 54, bitO), an ABNORMAL
DATA MARK (Register 58H, bit 6) or a WRITE
FAULT (Register 58H, bit 5). A zero indicates
that one of the conditions is true.
Originates in the DMA block and indicates if
the command loaded by the local processor is
a READ or WRITE Command with respect to
the Disk. This operation tests bit 6 inverted in
the START COMMAND Register. A one is a
disk write and a zero is a disk read.
Originates from the DMA block. This test input
is a logic one if the result of an ALU operation
has not yielded an overflow and NTP2 is a logic
one.
Originates from the DMA block and indicates
when either the OFFSET or AUXILIARY
OFFSET COUNTER is loaded with a zero as a
result of an ALU operation.
Forces the TEST input to a logic ONE.
-

If the Pointer Decrement enable bit is zero, the Register
Address will be the value specified in the Register Pointer'
field. If the Pointer Decrement enable bit is one, the Register
Address will be the value specified in the Register Pointer
field added to the current contents of the Loop Counter.
When accessing sequential register file locations, the Count
field should be initialized to the number of sequential access
required and the REGISTER POINTER FIELD should be
initialized to the last sequential register file location to be
accessed. At each MICROSEQUENCER clock, the loop
counter in the instruction is decremented, thus permitting
sequential access at the MICROSEQUENCER clock
frequency.
708

COUNT FIELD (014-8):
This field serves two functions. First, it is loaded into the
loop counter for counting microinstruction loops. In this
instance, the generation of an END COUNT status bit, will
cause branching conditions as defined by the SEQUENCE
CONTROL FIELD (031-29). The END COUNT status bit
will be set to a logic one when the loop counter is
decremented to zero. The second function of this field is for
accessing sequential locations of the DESIRED and
CURRENT REGISTER FILEs as described in the POINTER

DECREMENT ENABLE FIELD.
It should be noted that the count value is loaded into the
loop counter as the microinstruction containing it is exited.
The loop counter is decremented every microinstruction
clock or every 128th microinstruction clock for a short loop
(SHLP) or a long loop (LGLP) respectively. To perform a
count of N, the value N-1 should be specified in the previous
instruction in the microcode since the loop counter gets
loaded as an instruction is exited.

OUT FIELD (07-4):
The out field is one of two control fields used to control
internal and external operations during microprogram

execution. This four bitfield yields one of 16 control outputs
as follows:

OUT FIELD DEFINITION:
MNEMONIC
NOP
CNTRL4

0000
0001

07-04

RDG

0010

WPRE

0011
0100

WMISS

0101

FREG
SNDRM

o1 1 1

PREQ1

1000

WCRC

1001

PINTO

1010
1 01 1
1 100

PINT1

110 1

PINT2

1110

DNINT

1111

0110

OPERATION
No operation.
To DISK INTERFACE block causing the output CTL 4 to change. This output is
multiplexed with a programmable output controlled by the local processor. This signal
may be used for an external address mark enable when interfacing with ESDI drives.
To the DMA block. This signal is a DMA request from the MICROSEQUENCER and
enables disk data to get transferred to the DATA Register in the DMA block over the
INBUS. It also can cause the output DG (Data Gate) to go active. The DG output is
multiplexed with a programmable output controlled by the local processor.
RESERVED FOR FUTURE USE.
This signal allows the PLO SYNC (preamble) data stored in the DESIRED REGISTER
FILE to be loaded into the ENCODER/DECODER/DISK INTERFACE block over the
OUTBUS. In addition, it is used to preset all CRC and ECC generation logic.
This signal allows the missing clock data pattern stored in the DESIRED REGISTER
FILE to be loaded into the ENCODER/DECODER/DISK INTERFACE block over the
OUTBUS and generate the missing clock pattern when shifting the data out to the disk.
In addition, it is used to start all CRC and ECC generation logic.
This signal gates the data stored in the DESIRED REGISTER FILE on to the OUTBUS.
This signal gates the error syndrome (from the selected error checker) to the DESIRED
REGISTER FILE.
This signal causes the contents of the DESIRED REGISTER FILE pointed to by the
register pointer field to be loaded into the DISK DMA FUNCTION Register.
This signal gates the check bytes (CRC-16, ECC-32 Reed Solomon ECC) out to the
disk.
RESERVED FOR FUTURE USE.
RESERVED FOR FUTURE USE.
This signal sets bit 5 of STATUS 2 Register (ADDR 56 H) and will, if enabled, generate an
interrupt to the Local Processor. In addition, this interrupt will permit the Local Processor
to access the CURRENT REGISTER FILE. It also separates the OFFSET and the
AUXILIARY OFFSET COUNTERS. Typically, this interrupt is used for error correction
operations. See description of STATUS 2 Register.
This signal sets bit 6 of STATUS 2 Register (ADDR 56H) and will, if enabled, generate an
interrupt to the Local Processor. In addition, this interrupt will permit the Local Processor
to access the CURRENT REGISTER FILE. Typically, this interrupt may be used to
permit the Local Processor to read the current 10 information that is stored in the
CURRENT REGISTER FILE.
This signal will, if enabled, generate an interrupt to the Local Processor. This interrupt is
general purpose and can be generated upon recognition of any MICROSEQUENCER
detectable condition. The generation of this interrupt will affect no additional hardware.
This signal sets bit 4 of the interrupt STATUS 2 Register (ADDR 56 H) and will, if
enabled, generate an interrupt to the Local Processor. Typically, this signal is invoked
to inform the Local Processor that the current command executed by the
MICROSEQUENCER has been completed. Generation of this signal will stop the
MICROSEQUENCER, reset BUSY (STATUS 3 Register, Bit 07), and set done
(INTERRUPT STATUS Register, Bit 04). In addition, this interrupt will permit the Local
Processor to access the CURRENT REGISTER FILE.
709

EXT FIELD (D3-0):
The EXT field is one of two control fields used to control
internal and external operations during microprogram
EXT FIELD DEFINITION:
MNEMONIC
NOOP
SWDG

D3-DO
0000
0001

MNEMONIC
TREG

D3-DO
1000

execution. This four bit field yields one of 16 control outputs
as follows:

OPERATION
No operation.
This signal posts a DMA request for the MICROSEQUENCER to the DMA block and is
used during disk write operations. The signal allows data to be transferred from the DATA
Register in the DMA block to the DISK INTERFACE and ENCODER/DECODER blocks.
It also generates the DG (Data Gate) signal.
This signal is used to inform the CRC-16 or ECC-32 CHECKER that the respective code
SRCRC
0010
is being transferred from the disk.
SRECC
0011
This signal is used to inform the Reed Solomon ECC CHECKER that the ECC bytes are
being transferred in from the disk.
This signal enables the gap detect logic.
SGAP
0100
SPRE
0101
This signal enables the compare between incoming data and the value programmed in
the appropriate SYNC register(s). Norma"y, this comparison is used to detect a PLO
SYNC (preamble) data pattern. The RGATE signal is also set.
SMC
0110
This signal enables the compare between incoming data and the value programmed in
the appropriate SYNC register(s). Norma"y, this comparison is used to detect a missing
clock data pattern. The RGATE signal is also set.
SDM
01 1 1
This signal enables the compare between incoming data and the value programmed in
the appropriate SYNC register(s). Norma"y, this comparison is used to detect a data
mark data pattern. The RGATE signal is also set.
SGOFF(1)
1100
This signal resets both RGATE and WGATE.
NOTE: The signals above describe operations to be
performed as the instruction containing them is exited (The
PC is changed). The following signals will be invoked when
the instruction containing them is entered.
OPERATION
This signal gates the contents of the INBUS into the CURRENT REGISTER FILE as
pOinted to by the REGISTER POINTER FIELD.
1001
RESERVED FOR FUTURE USE.
CRC16
1010
This signal presets the CRC-16 generation and detection logic.
ECC32
1 011
This signal presets the ECC-32 or the Reed Solomon generation and detection logic.
ZRCLR
11 01
This signal clears the ZERO and AUX ZERO flags in the DMA block.
INCE
111 0
This signal causes the contents of the DESIRED REGISTER FILE pOinted to by the
register pointer field to be incremented and placed back into the same DESIRED
REGISTER location.
WGON
1111
This signal sets WGATE on.
(1) The signal SGOFF is shown out of numerical sequence to permit it to be grouped accordingly.
DISK INTERFACE & ENCODER/DECODER BLOCK
The encoder/decoder section is local processor
This block interfaces to the rest of the chip via the INBUS programmable to handle FM, MFM, RLL 2, 7 and GCR
and the OUTBUS which connects the serial to para"el! codes. Included in this block is the CRC-16 and IBM AT
para"el to serial converters to the DESIRED and CURRENT compatible 32 bit ECC generator and checker.
REGISTER FILES and the appropriate data registers within REED SOLOMON ERROR CORRECTION BLOCK
the DMA block.
The REED SOLOMON ECC block has been optimized to
In addition to serialization and deserialization of data, this permit single and double burst error correction while
block will perform complex high speed compare logic that simultaneously reducing the probability of miscorrection and
can sequentially compare a bit pattern read from the disk expanding the error detection capability dramatically.
of up to 32 bits in length. Any and a" compares can detect
a predefined missing clock pattern. The sequence of FUNDAMENTALS OF REED-SOLOMON ERROR
comparisons made prior to declaring a valid synchronization CORRECTING CODES
with the rotating media, is fully programmable under The error correction and detection capability of any Reed
MICROSEQUENCER control. During write disk operations, Solomon code always relates the number of symbols (bytes)
this block can generate fully programmable formats and that are allowed to be in error to permit valid correction and
complex missing clock data patterns completely under detection. In the simplest case, data is run through hardware
MICROSEQUENCER control.
one byte at a time and, depending on the complexity of the
710

hardware and the number of redundancy bytes (bytes
appended to the data field) used, one can allow a certain
number of these bytes to be in error and still recover the
data via correction and or detection.
To minimize hardware and maximize the error detection and
correction capability of the Reed Solomon code, several
identical hardware constructions are employed in parallel;
each with their individual limit on the number of symbols
(bytes) that can be in error. This method is called
interleaving. The interleaving method is set up such that
the first byte goes into the first interleave, the second byte
into the second interleave, etc. for the entire length of the
data plus redundancy fields. The MSD95C02 can employ
either two or three interleaves, each interleave containing
a maximum of 255 bytes. Further, each interleave can be
programmed to handle either 1 or 2 symbols in ermr. The
combination of interleaves and allowable symbols in error
per interleave, accounts for a variety of local processor
programmable error detection and correction capabilities.
A few examples will illustrate.
CASE 1:
Interleave of 2 and the ability to correct 1 byte per interleave
--->11 BYTEI-

I 11 I 12 I 11 I 12 I 11 I 12 I 11 I 12 I
--->19 BITS I - A
--->110BITSI- B
--->1 10 BITS I - c

A: Any and all 9 bit bursts will never span more than one
symbol per interleave. This arrangement permits correction
of any single 9 bit burst error.
B: This 10 bit burst includes two symbols from interleave 1
and hence, cannot guarantee proper correction.
C: This 10 bit burst, because of its position, does not include
more than one symbol per interleave and can be corrected
properly.
CASE 2:
Interleave of 2 and the ability to correct 2 byte per interleave.
--->11 BYTEI-

I 11 I 12 I 11 I 12 I 11 I 12 I 11 I 12 I
--->19 BITS I -

--->1 9 BITS 1<-

1<--25BITS~1

A: Any two randomly placed 9 bit bursts will never include
more than two symbols per interleave. This arrangements
permits correction of any two, 9 bit burst errors.
B: Any single burst error, 25 bits long or smaller, will never
include more than two symbols per interleave. This
arrangement permits correction of any single 25 bit burst
error.
CASE 3:
Interleave of 3 and the ability to correct 1 symbol per
interleave.
--->11 BYTEI<-

I 11 I 12 I 13 I 11 I 12 I 13 I 11 I 12 I

CASE 4:
Interleave of 3 and the ability to correct 2 symbols per
interleave.
--->11 BYTEI-

I 11 I 12 I 13 I 11 I 12 I 13 I 11 I 12 I
A:
B:

--->1

I,

17 BITS

I41 BITS

--->1

17 BITS
J

I

I-

A: Any two randomly placed 17 bit bursts will never include
more than two symbols per interleave. This arrangement
permits correction of any two, 17 bit burst errors.
B: Any single burst error, 41 bits long or smaller, will never
include more than two symbols per interleave. This
arrangement permits correction of any single 41 bit burst
error.
The MSD 95C02 has the ability to handle 2 or 3 interleaves
and can be programmed to correct either single or double
burst errors of varying length. Single or double burst error
correction capability corresponds to 1 or 2 symbol errors
per interleave.
The MSD 95C02 provides the user with an additional option
used to control the range of the error detection capability.
This is performed by including either an ECC eJQension field
or a CRC addition field.
ECC EXTENSION FIELD:
An extension field can be added to the data block being
processed to guarantee detection of an extra symbol per
interleave. The extension field consists of either 2 (for an
interleave of 2) or 3 (for an interleave of 3) additional bytes
preceding the original ECC bytes as follows:
I DATA FIELD I EXT11EXT21EXT31 ECC1,2 ... N I

~

I SOLOMONTOTAL
REED
I1

17 BITS

1<-

CRC ADDITION'
INTERLEAVES
2

TOTAL
REDUNDANCY
BYTES
6(= 4R1SECC

CORR
TYPE
SEC,MED

MAXIMUM
DATA
BLOCK
LENGTH
504 BYTES

+ 2CRC)
2
3
3

9(= 7R1SECC
+ 2CRC)
9(= 6 RISECC
+ 3CRC)
15 (= 12 RIS ECC
+ 3CRC)

DEC,MED 501 BYTES
SEC,MED

756 BYTES

DEC,MED

750 BYTES

SEC = single error correction
DEC = double error correction
MED = multiple error detection as defined by the CRC
extension used
ECC EXTENSION'

INTERLEAVES
2
2
3
3

TOTAL
REDUNDANCY
BYTES
6(= 4R1SECC
+ 2 ECC EXT.)
9(= 7R1SECC
+ 2 ECC,EXT.)
9(= 6 RlS ECC
+ 3 ECC EXT.)
15 (= 12 RlS ECC
+ 3 ECC EXT.)

CORR
TYPE
SEC,DED

MAXIMUM
DATA
BLOCK
LENGTH
504 BYTES

DEC, TED

501 BYTES

SEC,DED

756 BYTES

DEC, TED

750 BYTES

SEC = single error correction
DEC = double error correction
TED = triple error detection
It is also possible to program the redundancy bytes to
exclude both an ECC extension and a CRC addition. In this
case the total redundancy bytes, etc. take on the following
form:
MAXIMUM
DATA
BLOCK
LENGTH
506 BYTES
503 BYTES
759 BYTES
753 BYTES

RESET (READ)-40H
Reading this register address will reset the MSD95C02. This
is referred to as a "soft" reset. Soft and hard resets are
indistinguishable. Reset will be terminated by a write to any
MSD95C02 register.
MODE 1 Register (WRITE)-41H
This register space is not presently implemented.
MODE 1 Register (write)-41 H
The bits in this register are cleared to "0" by a hard or soft
reset. This Mode Register is used to control the DMA
section.
BIT D7: DMA TRANSFER REQUEST COUNTER RESET
Writing a "1" to this bit causes the DMA transfer request
counter to be reset. This bit does not have to be cleared
between writing successive "1 's."
BIT D6: RESERVED
BIT D5-4: EXTERNAL DEVICE DMA ADDRESS
INCREMENT VALUE
These bits determine the value that the External Device's
DMA address will be incremented for every External Device
DMAcycle:
INCREMENT VALUE
D5
D4
1
0
0
1
2
0
1
0
3
1
1
4
BIT D3: CONTROL OUTPUTS MODE SELECT
These bits determine the function of the output pins CTLS-5:
D3 = 0: CTL8 is DGATE
CTL7 is WRITE
CTL6is STO
CTL5is ST1
D3 = 1: CTL8-5 are local processor programmed outputs.

MODE 2 Register (WRITE)-42H
This Mode Register is used to control the Disk Interface and
Encoder/Decoder section.
4
BIT D7: COMPOSITE/INDIVIDUAL SYNDROME
7
D7 = 0: The ECC uses individual syndrome.
6
D7 = 1: The ECC uses composite syndrome.
12
BIT D6: TAPE/DISK MODE
SEC = Single error correction
D6 = 0: Select disk mode.
DEC = double error correction
D6 = 1: Select tape mode, perform Read after Write using
CRC.
LOCAL PROCESSOR INTERFACE BLOCK
This block has been optimized to interface with Local BIT D5: REFERENCE CLOCK SOURCE
Processors that have a multiplexed 8 bit Address/Data bus. This bit is used to select the clock source for the bit rate
The internal local processor data bus and address bus are Read/Write circuitry used when the Read Gate is inactive.
distributed to all blocks within the MSD95C02. Each block (This bit must be a "1" when using Read after Write for tape
has its own address decoder as described in the mode.)
OVERVIEW OF THE MSD95C02 REGISTERS section.
D5 = 0: RCLK (COMBINED READ/REFERENCE CLOCK)
In addition, this block employs a complex interrupt structure D5 = 1: WRITE REF CLOCK
used to generate appropriate interrupt based on multiple BIT D4: CONTROL OUTPUTS MODE SELECT
internal and external conditions. The interrupts can occur These bits determine the function of the CTL4 pin:
from three sources, namely the MICROSEQUENCER, the
DMA block and via the four external sense inputs D2 = 0: CTL4 is MICROSEQUENCER output (typically
used for ESDI AM enable)
(SNS4-1) to the MSD95C02. Figure 10 illustrates the
interrupt structure of the MSD92C02 with all the D2 = 1: CTL4 is Local Processor output pin
BIT D3: 16/8 BIT COMPARISON
corresponding status and interrupt enable registers.
This bit will choose the 16 or 8 bit compare mechanism in
REGISTER DESCRIPTIONS
the ENCODER/DECODER block. The 8 bit compare is used
All reserved bits are read as zero and all unused bits should when accepting data in NRZ format. The 16 bit compare is
be written as zero for compatibility with future options.
used when accepting data in an encoded mode typically to
712
INTERLEAVES
2
2
3
3

TOTAL
REDUNDANCY
BYTES

CORR
TYPE
SEC
DEC
SEC
DEC

establish bit synchronization. Refer to the SYNC Register
description for a table of how the compares interact witr
this bit.
D3 = 0: Choose 8 bit compare.
D3 = 1: Choose 16 bit compare.
BITS D2-DO: FORMAT
These bits are used to control the Encoder and Decoder.
D2
0
0
0
0
1
1
1
1

D1
0
0
1
1
0
0
1
1

DO
0
1
0
1
0
1
0
1

TYPE OF ENCODING
FM
MFM
M2FM
MANCHESTER
Rll 2, 7 TYPE 1
Rll 2, 7 TYPE 2
GCR
NRZ

TABLE 4: ENCODER/DECODER SELECTION
Tables 5 and 6 show the correspondence mapping for Rll
and GCR encoding respectively
INPUT BIT STREAM Rll 2, 7 TYPE 1 Rll 2, 7 TYPE 2
0100
10
0100
100100
010
000100
001100100
00100100
0010
1000
11
1000
011
001000
001000
00001000
00001000
0011
100100
000100
000

TABLE 5: RLL ENCODING MAPPING
INPUT BIT STREAM
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

MODE 4 Register (WRITE)-44H
This Mode Register is used to control the ECC Interface
section.
BIT D7: INTERNAUEXTERNAl ECC
D7 = 1: Will disable all internal ECC/CRC circuitry.
D7 = 0: Will enable all selected ECC/CRC circuitry.
BIT D6: INTERLEAVE 2/3
D6 = 1: Indicates Interleave 2
D6 = 0: Indicates Interleave 3
BIT D5: SINGlEIDOUBlE ERROR CORRECTION
SELECTION
D5 = 1: Correct single error
D5 = 0: Correct double error
BITS D4, D3: REED-SOLOMON CODE OPTIONS
These bits determine the optional ECC configurations and
code capabilities
D4 D3 OPTION
0 0 REED-SOLOMON DISABLED (USE ECC-32
OR CRC-16)
0 1 REED-SOLOMON only
1 0 REED-SOLOMON WITH ECC EXTENSION
1 1 REED-SOLOMON WITH CRC ADDITION (1)

TABLE 7: REED-SOLOMON CODE OPTIONS

GCR ENCODING
11001
11011
10010
10011
11101
10101
10110
10111
11010
01001
01010
01011
11110
01101
01110
01111

(1) This is either a 16 bit CRC (for single error correction) or
a 24 bit CRC (for double error correction) different than the
standard CRC-16 code which can be used as defined by bit D2.
BIT D2: ALTERNATE ECC/CRC USAGE
D2 = 1: Attaches the IBM® PC/XT'"/AT® compatible 32 bit
ECC code to the end of the data field.
(X32 +.X28 + X26 + X19 + X17 + X10 + X6 +
X2 + 1)
D2 = 0: Attaches the standard floppy disk 16 bit CRC code
to the end of the data field.
(X16 + X12 + X5 + 1)
BIT D1 : CRC/PRESET
D1 = 1: Preset alternate ECC/CRC Register to "1" before
computing.
D1 = 0: Preset alternate ECC/CRC Register to "0" before
computing.
BIT DO: (RESERVED)

TABLE 6: GCR ENCODING MAPPING
MODE 3 Register (WRITE)-43H
This Mode Register is used to control the DISK INTERFACE
and ENCODER/DECODER blocks.
BIT D7: INVERT DATA
Setting this bit to "1" will cause the disk data to be inverted
before encoding and after decoding. If this bit is "0", the data
will not be inverted.
BIT D6: lEVEUPUlSE
Setting this bit to "1" will cause the disk data to be decoded
as hard disk data (level transitions). If this bit is "0", the data
will be decoded as floppy disk (pulse) data.
BITS D5-D2: RESERVED
BITS D1-DO: CONTROL OUTPUTS MODE SELECT
These bits determine the function of the CTl3-1 pins:
D1 = 0: CTl3 is WRFClK input
IBM® and AT® are registered trademarks of the International Business
Machines Corporation.

D1 = 1: CTl3 is local Processor output pin
(Note: this bit is set to a "0" upon a hard or soft reset)
DO = 0: CTl2 is lATE output
CTl1 is EARLY output
DO = 1: CTl2 and 1 are local Processor programmable
outputs.

713

RESERVED REGISTER SPACE-45H
This register space is reserved for future expansion.

SYNC REGISTER 1·4 (WRITE)-ADDR 46H·49H.
The following four SYNC Registers are used to perform
either 8 or 16 bit high speed compares on the incoming
encoded data from the disk. The compares are executed
via three signals in the microcode EXT field. The three
signals, SPRE, SMC and SDM are typically used to look for
PlO SYNC (preamble) data, missing clock pattern data, and
data mark data respectively. The MICROSEQUENCER can
check for a valid high speed compare via the signal SYNC
in the test field of the microcode word. Tables 8 and 9
illustrate how the compares are used in conjunction with the
four SYNC Registers as a function of the encoding scheme
used and bit D3 (8/16 bit compare) of MODE 2 Register.

pc/xr" is a trademark of International Business Machines Corporation.

SYNC 1 Register (WRITE)-46H

This register holds SYNC pattern 1.

SYNC 2 Register (WRITE)-47H

This register holds SYNC pattern 2.

SYNC 3 Register (WRITE)-48H

This register holds SYNC pattern 3.

SYNC 4 Register (WRITE)-49H

This register holds SYNC pattern 4.

ENCODING SCHEME
FM
MFM
RLL(1)
RLL (2)
NRZ&GCR(3)

SYNC 1 (47H)
ADDRESS MARK
DATA
MISSING CLOCK
DATA
MISSING CLOCK
PATIERN 1
MISSING CLOCK
DATA
PATIERN 1

SYNC 2 (48H)
DATA MARK
DATA
PLOSYNC
DATA
PLOSYNC
DATA
PLOSYNC
DATA
PATIERN2

SYNC 3 (48H)
PLOSYNC
DATA
PLOSYNC
CLOCK
PLOSYNC
CLOCK

SYNC 4 (49H)
DATA MARK
CLOCK
MISSING CLOCK
CLOCK
MISSING CLOCK
PATIERN2

-

-

TABLE 8: SYNC REGISTER DEFINITION AS A FUNCTION OF ENCODING SCHEME
(1) RLL SYNC Register setup for 16 bit compare (bit D3 of MODE 2 Register = 1)
(2) RLL SYNC Register setup for 8 bit compare (bit D3 of MODE 2 Register = 0)
(3) NRZ and GCR encoding should always use 8 bit compares (bit D3 of MODE 2 Register = 0)

MICROCODE SIGNAL
SPRE
SPRE

8/16 COMPARE
8
16

SMC
SMC

8
16

SDM
SDM

8
16

COMPARE BETWEEN DISK DATA AND SYNC REGISTER
SYNC 2 (47H)
SYNC 2 (47H) FOR DATA TRACK AND
SYNC 3 (48H) FOR CLOCK TRACK
SYNC 1 (46H)
SYNC 1 (46H) FOR DATA TRACK AND
SYNC 4 (49H) FOR CLOCK TRACK
SYNC 2 (47H)
SYNC 2 (47H) FOR DATA TRACK AND
SYNC 4 (49H) FOR CLOCK TRACK

TABLE 9: SYNC REGISTER COMPARE MATRIX AS A FUNCTION OF MICROCODE SIGNALS

The following two registers represent a 12 bit TAPE BYTE TAPE BYTE COUNTER LOW (WRITE)-4BH
counter. This counter is needed during tape Read/Write This register holds the lower eight bits ofthe twelve bit Tape
operating to inform the readback circuitry that the data block Byte Counter. This counter is used to count the number of
plus the two byte CRC field has been read. Only the CRC- bytes used for CRC 2 during the Read after Write.
16 can be used with the tape feature. It is loaded with the
value equal to the number of bytes in the data block plus 2 LOCAL PROCESSOR OUTPUT Register (WRITE)-4CH
(for the CRC-16 fielp).
This register holds the data that is directly output on the
TAPE BYTE COUNTER HIGH (WRITE)-4AH
CTL8-1 pins when they are configured as Local Processor
This register holds the upper four bits of the twelve bit Tape outputs by bits in MODE 1, MODE 2 and MODE 3 Registers.
Byte Counter. This counter is used to count the number of Bit 7 is output on CTL8 and bit 0 is output on CTL1. These
bytes used for CRC 2 during the Read after Write.
bits are cleared to zero by a hard or soft reset.
714

Read After Write Fault bit in the STATUS 4 Register
goes active high.
BIT D3: SENSE 4 CHANGE INTERRUPT ENABLE
Setting this bit to "1" will cause the MSD95C02 to
set the Interrupt Pending and Sense Change bits
in the INTERRUPT STATUS Register when the
Sense 4 Change bit in the STATUS 4 Register goes
active high.
BIT D2: SENSE 3 CHANGE INTERRUPT ENABLE
Setting this bit to "1 " will cause the MSD95C02 to
set the Interrupt Pending and Sense Change bits
in the INTERRUPT STATUS Register when the
SENSE 3 Change bit in the STATUS 4 Register
goes active high.
BIT D1 : SENSE 2 CHANGE INTERRUPT ENABLE
Setting this bit to "1 " will cause the MSD95C02 to
set the Interrupt Pending and Sense Change bits
in the INTERRUPT STATUS Register when the
SENSE 2 Change bit in the STATUS 4 Register
goes active high.
BIT DO: SENSE 1 CHANGE INTERRUPT ENABLE
Setting this bit to "1" will cause the MSD95C02 to
set the Interrupt Pending and Sense Change bits
in the INTERRUPT STATUS Register when the
SENSE 1 Change bit in the STATUS 4 Register
goes active high.

INTERRUPT ENABLE 1 Register (READIWRITE)-4DH

The bits in this register are cleared to zero by a hard or soft
reset.
BIT 07: MASTER INTERRUPT ENABLE
Setting this bit to "1" will cause the MSD95C02 to
drive its INT output pin active when an enabled
condition causes the Interrupt Pending status bit to
go active high.
BIT D6: DMA INTERRUPT ENABLE
Setting this bit to "1" will cause the MSD95C02 to
set the Interrupt Pending status bit when the DMA
bit in the INTERRUPT STATUS Register goes
active high.
BIT D5: (RESERVED)
BIT 04: DONE INTERRUPT ENABLE
Setting this bit to "'!-" will cause the MSD95C02 to
set the Interrupt Pending status bit when the DONE
bit in the INTERRUPT STATUS Register goes
active high.
BIT 03: (RESERVED)
BIT D2-DO: (reserved for future expansion)
INTERRUPT ENABLE 2 Register (READIWRITE)-4EH

The bits in this register are cleared to zero by a hard or soft
reset.
BIT D7: PROGRAM 2 INTERRUPT ENABLE
Setting this bit to "1" will cause the MSD95C02 to
set the Interrupt Pending and Program status bits
in the INTERRUPT STATUS Register when the
PROG 2 bit in the STATUS 2 Register goes active
high.
BIT 06: PROGRAM 1 INTERRUPT ENABLE
Setting this bit to "1" will cause the MSD95C02 to
set the Interrupt Pending and Program status bits
in the INTERRUPT STATUS Register when the
PROG 1 bit in the STATUS 2 Register goes active
high.
BIT 05: PROGRAM 0 INTERRUPT ENABLE
Setting this bit to "1" will cause the MSD95C02 to
set the Interrupt Pending and Program status bits
in the INTERRUPT STATUS Register when the
PROG 0 bit in the STATUS 2 Register goes active
high.
BITS D4-DO: (RESERVED)

DMA FUNCTION Register (READ)-50H

BITS D7-D6. These bits specify the operation to be
performed on the internal register file by the Local
Processor:

INTERRUPT ENABLE 3 Register (READIWRITE)-4FH

The bits in this register are cleared to zero by a hard or soft
reset.
BITS D7-D6: MUST BE SET TO ZERO (RESERVED)
BIT 05: WRITE FAULT ENABLE
Setting this bit to "1" will cause the MSD95C02 to
set the Write Fault bit in the STATUS 4 Register and
cause the test point "NTP2" to go active when the
Sense 2 Change bit in the STATUS 4 Register goes
active high. In tape mode, setting this bit will also
cause test point "NTP2" to go active if Rea:d After
Write Enable is active and a CRC error occurs
during a Read after Write.
BIT 04: READ AFTER WRITE INTERRUPT ENABLE
Setting this bit to "1" will cause the MSD95C02 to
set the Interrupt Pending and STATUS 4 Interrupt
bits in the INTERRUPT STATUS Register when the
715

D7D6 FUNCTION
0 0 SOURCE + OFFSET COUNTER-+
DESTINATION (Note 1)
0 1 SOURCE + N -+ DESTINATION;
DECREMENT OFFSET COUNTER
1 0 SOURCE -+ DESTINATION
1 1 SOURCE + N -+ DESTINATION
N = 1 for disk and local processor data transfers
N specified for MODE 1 Register for External channel
(SCSI) data transfers

TABLE 10: DMA FUNCTION REGISTER
OPERATION
Notes:
1. For this case, the only destinations that can be updated
are the OFFSET COUNTER and the MAILBOX. All other
destinations will cause the OVERFLOW flag to be updated
as a function of the result out of the ALU, but will not update
the destination.
2. When the controller changes the contents of the OFFSET
and AUXILIARY OFFSET COUNTERS, it must set orclear
the zero bit via the START COMMAND Register bits 4 and
3.
3. The OFFSET COUNTER cannot be used as a source. If
it is used as a source, it will take on the value of zero. During
error correction, it becomes necessary to use the OFFSET
COUNTER as a source. See appendix 3 for a description
of ERROR CORRECTION ON THE FLY for more detail.
BITS D5-D3. Source register file address.
BITS D2-00. Destination register file address.
These bits select the register file address location(s)
accessed by the operation specified by bits D7 and D6.

DS
D2
0
0
0
0
1
1
1
1

D4
D1
0
0
1
1
0
0
1
1

D3
DO
0
1
0
1
0
1
0
1

REGISTER SELECTED
MAILBOX HIGH, LOW
OFFSET COUNTER
CONSTANT 1
CONSTANT 2
LOCAL PROCESSOR ADDRESS
EXTERNAL DEVICE ADDRESS
DISK REGISTER
DISK ADDRESS

TABLE 11: DMA FUNCTION REGISTER SOURCE!
DESTINATION

caused by PROGO or PROG1 to allow
MICROSEQUENCER access to the CURRENT
REGISTER FILE. Writing a logic zero will have no
effect.
BIT D1 : (RESERVED)
BIT DO: HALT
Writing a logic "1" to this register will cause "NTP2"
to go active. The MICROSEQUENCER can test
"NTP2" at certain times to determine if it should
terminate execution of the present command. This
bit is a way for the local processor to halt the
microprogram at an appropriate time (for example;
at the end of a sector read) by having the
microprogram interrogate NTP2 at that time.

MAILBOX HIGH Register (READIWRITE)-51H
BITS D7-DO: HIGH ORDER DMA ADDRESS BITS; A1S-8 .
INTERRUPT STATUS Register (READ)-54H
This register functions as a mailbox for transfer of the high
This
register is the master interrupt status register. It should
order address bits to and from the DMA register file.
be ~ead after an interrupt is generated to determine which
logical block generated the interrupt condition.
MAILBOX LOW Register (READ/WRITE)-52H
BIT D7: INTERRUPT PENDING
BITS D7-DO: LOW ORDER DMA ADDRESS BITS; A7-0
This bit is set to "1" when one of the enabled
This register functions as a mailbox for transfer of the low
interrupt conditions occur. It is cleared to "0"
order address bits to and from the DMA register file.
when the interrupt causing condition(s) are
cleared.
DATA Register (READIWRITE)-53H
D6:
DMA INTERRUPT
BIT
This register functions as a mailbox for data transfers
This bit is set to "1" when the ZERO or
between the Local Processor and the Ring Buffer. Local
AUXILIARY ZERO bits in the STATUS 1 (DMA)
Processor read and writes to the Ring Buffer are funnelled
Regi~ter go active high. It is cleared to "0" by
through this register which resides in the DMA block. The
reading the STATUS 1 (DMA) Register, a hard or
Local Processor should poll STATUS 1 Register, bit 1
a soft reset.
(REQUEST 1), to determine the status of local processor
BIT DS: PROGRAM INTERRUPT
initiated DMA cycles.
This bit is set to "1" when one of the enabled
START COMMAND Register (WRITE)-54H
PROG2-0 bits in the STATUS 2 Register goes
active high. It is cleared to "0" by reading the
Writing to this register initiates microprogram execution.
STATUS 2 Register, a hard or a soft reset.
BIT D7: START ENABLE
BIT D4: DONE INTERRUPT
Setting this bitto a logic "1" will set the BUSYbit in STATUS
This bit is set to "1" when the MSD9SC02
3 Register and enable the start of microprogram execution.
completes a command. This interrupt is
BIT D6: DISK DMA DIRECTION
generated by the microcode and indicates that
This bit selects the direction of DMA data transfer
the internal MICROSEQUENCER has stopped.
for the disk data channel:
This bit is reset to "0" by reading STATUS 3
Register, or by a hard or soft reset.
D6 = 1 Disk to Ring Buffer (Disk READ)
D6 = 0 Ring Buffer to Disk (Disk WRITE)
BIT D3: SENSE CHANGE INTERRUPT
This bit is set to "1" when one of the enabled
BIT DS: EXTERNAL DEVICE DMA DIRECTION
Sense 4-1 Change bits in the STATUS 4 Register
This bit selects the direction of DMA data transfer
goes active high. This bit is reset to "0" by reading
for the EXTERNAL data channel:
the STATUS 4 Register, a hard or a soft reset.
DS = 1 External Device to Ring Buffer.
BIT D2: STATUS 4 Register INTERRUPT
DS = 0 Ring Buffer to External Device.
This bit is set to "1" when the Read After Write
BIT D4, D3: DMA ZERO BIT CONTROL
interrupt in STATUS 4 Register goes active high.
These bits can set or reset the zero output of
This bit is reset to "0" by reading the STATUS 4
the DMA OFFSET and AUXILIARY OFFSET
Register, a hard or a soft reset.
COUNTERs:
BITS D1-DO: (RESERVED)
D3
D4
RESULT
No change to zero indicator
0
0
STATUS 1 Register (READ)-55H
Reset zero indicator
1
0
This register contains status about the DMA block. Bits
1
Set zero indicator
0
D3-DO are cleared to zero following a hard or soft reset. Bits
1
1
Undefined
D7-D4 are unaffected by a hard or soft reset.
TABLE 12: DMA ZERO BIT CONTROL
BIT D7: AUXILIARY ZERO
This bit re~lects the state of the zero flag of the
BIT D2: CRR (Current Register Read)
AUXILIARY OFFSET COUNTER. This bit is set
Writing a logic "1" to this register indicates that the
by a hard or soft reset.
microprocessor has finished reading the
BIT D6: ZERO
information in the CURRENT REGISTER FILE.
This bit reflects the state of the zero flag of the
This must be done after an interrupt has been
716

OFFSET COUNTER. This bit is set by a hard or
soft reset.
BIT D5: OVERFLOW
This bit reflects the state of the overflow flag
generated from the ALU in the DMA block.
BIT D4: (RESERVED)
BIT D3: REQUEST 3
This bit reflects the state of the
MICROSEQUENCER housekeeping DMA cycle
request latch. A logic "1" indicates that the DMA
cycle request has either not been acknowledged
or is in progress and a logic "0" indicates thatthe
DMA cycle has been completed.
BIT D2: REQUEST 2
This bit reflects the state of the
MICROSEQUENCER data transfer DMA cycle
request latch. A logic "1" indicates that the DMA
cycle request has either not been acknowledged
or is in progress and a logic "0" indicates thatthe
DMA cycle has been completed.
BIT D1 : REQUEST 1
This bit reflects the state of the Local Processor
channel DMA cycle request latch. A logic "1"
indicates that the DMA cycle request has either
not been acknowledged or is in progress and a
logic "0" indicates that the DMA cycle has been
completed.
BIT DO: REQUEST 0
This bit reflects the state of the External Device
channel DMA cycle request latch. A logic "1"
indicates that the DMA cycle request has either
not been acknowledged or is in progress and a
logic "0" indicates that the DMA cycle has been
completed.

BIT D5: PROGRAMMABLE INTERRUPT 0
This is a programmable interrupt that is set
under MICROSEQUENCER control. This
interrupt will allow the local processor to
access the CURRENT REGISTER FILE.
The MICROSEQUENCER will not be able to
update the CURRENT REGISTER FILE until the
local processor has indicated that it has finished
reading the CURRENT REGISTER FILE by
writing a "1" to bit D2 (CRR) of the START
COMMAND Register. The generation of this
interrupt will delink the OFFSET and AUXILIARY
OFFSET COUNTERS in the DMA block. This
interrupt is used to indicate an ECC error. Service
would be required by having the Local Processor
read the error syndrome residing in the
CURRENT REGISTER FILE, correct the error
and properly relink the AUXILIARY OFFSET and
OFFSET COUNTERs in the DMA block back
together. See Appendix 4 (ECC ON THE FLY)
for further details.
BITS D4-DO: (RESERVED)

STATUS 3 Register (READ)-57H
This register contains status aboutthe MICROSEQUENCER
block. The values in bits D4-0 are valid when the Done
Interrupt bit is active high.
BITD7: BUSY
This bit indicates the state of the
MICROSEQUENCER.
o = MICROSEQUENCER is finished or reset.
1 = MICROSEQUENCER is executing a
program.
BITS D6-D5: (RESERVED)
BITS D4-DO: PROGRAM COUNTER DATA
These bits will hold the address ofthe instruction
executed prior to executing the instruction that
generated the Done Interrupt via the signal DNINT
in the OUT field of the MICROSEQUENCER
RAM. They are valid after the Done status bit is
set indicating that the MICROSEQUENCER has
stopped running.

STATUS 2 Register (READ)-56H
This register contains status about the M ICROSEQUENCER
block. The Program Interrupt bits are set under
MICROSEQUENCER control. The PROG2-0 bits are
cleared to zero by reading the STATUS 2 Register, a hard
or a soft reset.
BITS D7-D5: PROGRAMMABLE INTERRUPTS 2-0.
STATUS 4 Register (READ)-58H
These bits are set to "1" under This register contains status information.
MICROSEQUENCER control. These bits are
BIT D7: RESERVED
reset to "0" by reading the Status 2 Register, a
BIT D6: ABNORMAL DATA MARK
hard or a soft reset.
This bit is set to "1" when the
BIT D7: PROGRAMMABLE INTERRUPT 2
MICROSEQUENCER tests the data mark and it
This is a programmable interrupt that is set
does not match the data mark in the DESIRED
under a MICROSEQUENCER control. This is a
REGISTER. This bit being set will cause "NTP2"
general purpose interrupt that can be generated
to become active. This bit is reset by the start of
upon recognition of any MICROSEQUENCER
execution of a command.
detectable condition. The generation of this
BIT D5: WRITE FAULT
interrupt will affect no additional hardware.
This bit is set to "1" when the SNS2 input
BIT D6: PROGRAMMABLE INTERRUPT 1
undergoes a high-to-Iow level transition if the
This is a programmable interrupt that is set
WRITE FAULT enable bit of the INTERRUPT
underMICROSEQUENCER control. This
ENABLE 3 Register is an active "1 ". This bit being
interrupt will allow the local processor to
set will cause "NTP2" to become active. This bit
access the CURRENT REGISTER FILE. The
is resetto "0" by reading the STATUS 4 Register,
MICROSEQUENCER will not be able to update
a hard or a soft reset.
the register file until the local processor has
BIT D4: READ AFTER WRITE ERROR
indicated that it has finished readmg the register
This bit is set to "1" when a CRC error occurs
file by writing a "1" to bit D2 (CRR) of the START
during a Read After Write while in the tape mode.
COMMAND Register. This interrupt may be used
This bit is reset to "0" by reading the STATUS 4
for ID field interrupt to permit the local processor
Register, a hard or a soft reset.
to read the current ID information that is stored
717

BIT 03: SENSE 4 CHANGE
This bit is set to "1" when the SNS4 input
undergoes a high-to-Iow or low-to-high level
transition. This bit is reset to "0" by reading the
STATUS 4 Register, a hard or a soft reset.
BIT 02: SENSE 3 CHANGE
This bit is set to "1" when the SNS3 input
undergoes a high-to-Iow level transition. This bit
is reset to "0" by reading the STATUS 4 Register,
a hard or a soft reset.
BIT 01: SENSE 2 CHANGE
This bit is set to "1" when the SNS2 input
undergoes a high-to-Iow level transition. This bit
is reset to "0" by reading the STATUS 4 Register,
a hard or a soft reset.
BIT 00: SENSE 1 CHANGE
This bit is set to "1" when the SNS1 input
undergoes a high-to-Iow level transition. This bit
is reset to "0" by reading the STATUS 4 Register,
a hard or a soft reset. When the Local Processor
reads this register, this bit must not be reset
before it is read.
REGISTERS (READ)-59H, 5AH, 5BH
These registers are reserved. for future expansion.
DEVICE INPUTS Register (READ)-5CH
This register reflects the status of the external TEST and
SENSE inputs. The MS095C02 can be programmed to
generate an interrupt from some of these input pins as
follows:

BIT 07: TEST 4
This bit reflects the state of the TST4 input.
BIT 06: TEST 3
This bit reflects the state of the TST3 input.
BIT 05: TEST 2
This bit reflects the state of the TST2 input.
BIT 04: TEST 1
This bit reflects the state of the TST1 input.
BIT 03: SENSE 4
This bit reflects the state of the SNS4 input. The
MS095C02 can be programmed to generate an
interrupt whenever this input transitions (level
change interrupt).
BIT 02: SENSE 3
This bit reflects the state of the SNS3 input. The
MS095C02 can be programmed to generate an
interrupt whenever this input transitions from high
to low (negative edge triggered interrupt).
BIT 01 : SENSE 2
This bit reflects the state of the SNS2 input. The
MS095C02 can be programmed to generate an
interrupt whenever this input transitions from high
to low (negative edge triggered interrupt).
BIT 00: SENSE 1
This bit reflects the state of the SNS1 input. The
MS095C02 can be programmed to generate an
interrupt whenever this input transitions from high
to low (negative edge triggered interrupt).

MAXIMUM GUARANTEED RATINGS
Operating Temperature Range ..... , ...........................................................................0· to 70·C
Storage Temperature Range .......................................................................... - 55·C to + 150·C
Lead Temperature (soldering, 10 sec) ........................................................................... + 300·C
Positive Voltage on any Pin, with respect to Ground ......................................................... Vcc +0.3V
Negative Voltage on any Pin, with respect to Ground ............................................................. - 0.3V
Maximum Voltage on Vee pin ........................................................................................ 7.0V
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the "Maximum Guaranteed Ratings"
not be exceeded, or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when AC power
is switched off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists it is suggested
that a clamp circuit be used.

DC ELECTRICAL SPECIFICATIONS TA

= O·C to 70·C, Vcc = 5.0V,

± 5%)

Icc
OUTPUT VOLTAGE
High, VOH
Low,
INPUT VOLTAGE
High, VIH1
High, VIH2
Low, VIH1
Low,
INPUT LEAKAGE
High,I'H
Low, IlL

2.4
0.4

V
V

0.8
1.5

V
V
V
V

Except OMACLK, RCLK, CTL3
OMACLK, RCLK, CTL3
Except OMACLK, RCLK, CTL3
OMACLK, RCLK, CTL3

10
10

IJ.A
jJ.A

VIH = 2.0V, Except OMACLK, RCLK, CTL3
VIH = 3.5V, OMACLK, RCLK, CTL3
VIL = 0.8V, Except OMACLK, RCLK, CTL3
VIL = 1.5V, OMACLK, RCLK, CTL3

2.0
3.5

718

AC ELECTRICAL CHARACTERISTICS
All minimum and maximum times are given assuming a 20MHz clock. If the time is clock dependent, then the equation
is given under the comments column. This is to allow calculation of the time delays using slower clock rates.

AC ELECTRICAL SPECIFICATIONS TA
DATA
SYMBOL

PATH
MIN

T,

=

O°C to 70°C, Vee = 5.0V, ± 5%)

TIMING
MAX

UNITS

100

ns

COMMENTS
ADDR TO DATA VALID
(3xDMACLK) - 50 nsec

T.

0

ns

READ DATA HOLD FROM ADDR CHNG

T3

140

ns

OE PULSE WIDTH
(3xDMACLK) -10 nsec

T.

75

ns

OE TO READ DATA VALID
(3xDMACLK) - 75 nsec

T5

35

ns

OE TO DATA HIGH IMPEDANCE
(DMACLK) -15 nsec
OE TO TRAILING EDGE OF DACK
(2.5xDMACLK) - 25 nsec
TRAILING EDGE OF DACK TO TRAILING EDGE OF OE
(0.5xDMACLK) -10 nsec

T.

100

ns

T9

15

ns

TlO

0

ns

ADDR SETUP TIME TO WE

Tll

25

ns

WRITE RECOVERY TIME
(ADDR HOLD AFTER WE INACTIVE)
(DMACLK - 25 nsec)

T,.

75

ns

WE PULSE WIDTH
(2xDMACLK) - 25 nsec

T'3

40

ns

WRITE DATA SETUP TIME
(DMACLK -10 nsec)

T,.

25

ns

WRITE DATA HOLD TIME
(DMACLK -10 nsec)

T'5

85

ns

DACK TO TRAILING EDGE OF WE
(2xDMACLK) -15 nsec

T'6

10

ns

TRAILING EDGE OF WE TO TRAILING EDGE OF DACK
(0.5xDMACLK) -10 nsec

T,i

50

ns

DACK PULSE WIDTH HIGH
(1.5xDMACLK) -25 nsec

T, •

100

ns

DACK PULSE WIDTH LOW
(2.5xDMACLK) - 25 nsec

T,.

85

ns

SO, S1 HOLD AFTER OE ACTIVE
(2xDMACLK) -15 nsec

T'b

85

ns

SO, S1 HOLD AFTER WE ACTIVE
(2xDMACLK) -15 nsec

T,c

85

ns

SO, S1 VALID TO ADDRESS VALID
(2xDMACLK) -15 nsec (MIN)
(2xDMACLK) + 15 nsec (MAX)

T'd

185

ns

SO, S1 WIDTH
(4xDMACLK) -15 nsec

T2a

135

ns

WRITE HOLD AFTER OE ACTIVE
(3xDMACLK) -15 nsec

T2b

135

ns

WRITE HOLD AFTER WE ACTIVE
(3xDMACLK) -15 nsec

TOo

35

ns

WRITE VALID TO ADDRESS VALID
(1xDMACLK) -15 nsec (MIN)
(1 xDMACLK) + 15 nsec (MAX)

T2d

185

ns

WRITE WIDTH
(4xDMACLK) -15 nsec

115

65

71.9

='=T_'d--=---=--=~jr__
--+l

~f+---_;

_

T,,_

!.....-T2a

,I

T'd
S0,S1

T2b

I

X

j

I - T" -+ - - -

~T1b~

Tlo

r

A15-0

r----- T,

I-Tll-j

I:-T
T,.

lO -

T3
!-T4 -

I"t- T6+-\,

D87-0

,

~T17-1

v:;

0- read data from RAM

T.
T"

~-----RAM to MSD 95C02

,"""I

or RAM to External Device

-T~

.Ih-r
V

write data to RAM

f+-T13 -

I+T14.j

- T"

r

T15

~,y

-+l- External Device to RAM----~.~I
or MSD 95C02 to RAM

FIGURE 11: DATA PATH TIMING
DMA CLOCK and DMA REQUEST TIMING
SYMBOL

MIN
COMMENTS
MAX
UNITS
1000
nsec
DMACLK CYCLE TIME
50
T20
20
nsec
DMACLK HIGH TIME
T21
DMACLK LOW TIME
20
nsec
T22
nsec
DMACLK RISE TIME
5
T23
DMACLK FALL TIME
5
nsec
T24
DMAREQ' CYCLE TIME (Note 1)
T25
1.1xT20
nsec
nsec
DMAREQ LOW TIME
20
T26
DMAREQ HIGH TIME
20
nsec
T27
T28
nsec
DMAREQ RISE TIME
5
nsec
DMAREQ FALL TIME
5
T29
NOTE 1: Can be 1XT21 a if DMAREQ is synchronized to DMACLK.

FIGURE 12: DMA CLOCK and DMA REQUEST TIMING
720

INTERRUPT TIMING
SYMBOL

MIN

T30

MAX
100

UNITS
nsec

COMMENTS
INTERRUPT RESET
FROM RDorWR

n-

INTm

\

RD(DS)

'-

WR(DS)

FIGURE 13: INTERRUPT TIMING
DISK (Write Data) TIMING
SYMBOL
T,
T2
T3
T4
Ts
T6
T7
T.
Te
Tea
T,o
Tl1

MIN
48
0.40 T1
0.40 T1

MAX

5
5
(TBD)
(TBD)
0.75 T1

1.25 T1
10
10

0.5 T1
2xT1-20

UNITS
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec

COMMENTS
CYCLE TIME
HIGH TIME
LOW TIME
RISE TIME
FALL TIME
DATA SETUP TIME
DATA HOLD TIME
CYCLE TIME
WDATA VALID TO EARLY, LATE
EARLY, LATE VALID TO WDATA VALID
Hold from trailing edge of WDATA
Active time

2XRCLK

WRFCLK

WDATA
(NRZ)

WDATA
(Pulse Mode)

I

T.I

T9a~~r- -1;0/-

~~fJ-Y --.J/jJJ

r- T" -1

\'---__~/

FIGURE 14: DISK (Write Data) TIMING
721

l

Microprocessor Interface Timing

SYMBOL
T,
T2
T3
T.
T5
T6
T7
T.
T9
T,o
T11
T'2
T'3
T"
T'5

RlW
OS

RD
WR

45
30
15
120
70
10
110
135
25
20
20
0
0
0
0

45
30
15
120
115
10
110
135
25
20
20
0
0
0
0

I-

COMMENTS
ALE (AS) ACTIVE PULSE WIDTH
ADDRESS VALID TO ALE INACTIVE
ALE INACTIVE TO ADDRESS INVALID
READ STROBE LOW PULSE WIDTH
RD (OS) ACTIVE TO READ DATA VALID
READ DATA HOLD FROM RD (OS) HIGH
WRITE STROBE LOW PULSE WIDTH
WRITE DATA VALID TO WRJQ.S)~ACTIVE
WRITgj)ATA HOLD FROM WR (OS) INACTIVE
ALE (AS) INACTIVE TO READ STROBE ACTIVE
ALE ffi..S) INACTIVE TO WRITE STROBE ACTIVE
RD (I2§) INACTIVE TO ALE ACTIVE
WR (OS) INACTIVE TO ALE ACTIVE
C~VALID TO RD, WR OR OS
R/W VALID TO ALE (AS) INACTIVE

UNITS
nsec min
nsec min
nsec min
nsec min
nsec MAX
nsec min
nsec min
nsec min
nsec min
nsec min
nsec min
nsec min
nsec min
nsec MAX
nsec min

T,.

•

I_T,--

/
I-T,-

"'

ALE

-+-T2~

AD0AD?

~

./

.T._

- T3 - - - ADDRESS

~

DATA

~/

-Ts-

-T,o

AlW

t
_ _....J!

T,s+ - T , o

"~

• •

"',

•

-

/

T.

•

-T'2-

/V
T.

•

-T'2-

FIGURE 15: MICROPROCESSOR INTERFACE TIMING (READ)

722

V--

T"

•

-

I _ T, -

/

I -+- T, ----+-

r--

ALE

AD0·
AD7

=>--

+T2 .....

.......-.- T3-----+'"

_ _ _ T,

ADDRESS

- + - - T,,----..

I. . .T15~

-+----T'l~

•
DATA

•

T,

"-

•

T,

_T,~

1

•

- + - T'3----+-

•

. . . . - - TT3-----+-

RMI - - - - - \

c

FIGURE 16: MICROPROCESSOR INTERFACE TIMING (WRITE)
DISK INTERFACE TIMING
COMMENTS
Write gate setup to AMENA
Write gate active time
Write gate hold after AMENA
AMENA active time
Index active time
AMENA TO AMFNO
AMENA inactive to AMFNO inactive
AMFNO active time
AMFNO active to RGATE active
ROATA active time
ROATA setup to 2xRCLK
ROATA hold from 2xRCLK
SNS1 active time
TST3 active time
SNS2 active time
SNS3 active time
SNS4 active time
TST2 active time
RST active time
LPS active time (Note 1)
RGATE active time
NOTE 1
If the chip is at idle, then the time from LPS becoming active until the chip actually enters the low power mode is the
longest of the following times:
1. (2 x (2XRCLK)) + 200nsec
2. (2 x (WRFCLK)) + 200nsec
3. (0.5 x (OMACLK)) + 200nsec
723

SYMBOL
T40
T4O•
T41
T42
T43
T44
T45
T46
T47
T49
T50
T51
T52
T53
T54
T55
T56
T57
T58
T59
T608

MIN
(TBO)
8xWCLK
(TBO)
8xWCLK
50
(TBO)
(TBO)
50
(TBO)
25
12
12
25
25
25
25
25
25
1
0
8xWCLK

MAX

UNITS
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
f!.sec
nsec
nsec

I

WGATE

AMENA

T40a

'I

-.J

~;

~

.~

T42

Write Address Mark Timing

2XRCLK

\

NRZ READ DATA TIMING

}

INDEX

T43

·1

\

Index Timing

AMENA

-.l

LDPT~

--I---T,,-I-

\

~'\
~;
~!
T46

AMFND

RGATE

ATEN/WF~

f.- Too---1

j

CMDDN

\

~T"---1'----

Read Address Mark Timing

FIGURE 18: DISK INTERFACE TIMING 2

FIGURE 17: DISK INTERFACE TIMING 1

READY _ _

~I

\

--'I

\

~T56~'----

ECCERR _ _ _

RST

LPS

RGATE

~T57-1\....----

~~T58~1

1'---

'\

----,t-T.-}r---I

\

-~~Too~'----

FIGURE 19: DISK INTERFACE TIMING 3

724

APPENDIX 1-SAMPLE MICROPROGRAMS:
1-FORMAT COMMAND
The following description and microprogram will format a
Hard disk with the following format:

IL

INDEXJl

IGAP 11 SYNC IMCIAMICYL IHDlsEClcRC IGAP21SYNC IMC 10M I DATA IECC IGAP31GAP41
E
REPEATED N TIMES
,
All of the following variables can contain any data and be
microprogrammed for any length (in bytes).
GAP1-Post index gap.
SYNC-The PLO SYNC (preamble) field.
MC-Missing clock pattern.
AM-Address mark.
CYL-Cylinder number.
HD-Head number.
SEC-Sector number.
CRC-One of sever~1 selectable check bytes.
GAP2-Header to data gap.
OM-Data mark.
DATA-The data field.
ECC-One of 2 selectable ECC codes.
GAP3-Post data field gap.
GAP4-Pre index gap.
N-The number of sectors per track.
Prior to executing the format command with the defined
microprogram written in the Microprogram RAM, the local
processor should load the DESIRED REGISTER FILE with
the data to be used in each of the defined fields in the format.
The microprogram will point to these preloaded values, via
the register pointer field, to permit the data to be transferred
to the ENCODER/DECODER block and finally out to the
disk. The Local Processor should also load the Ring Buffer
with the TRACK, HEAD and SECTOR of all the sectors to
be formatted in consecutive locations as follows:
RING BUFFER
LOCATION
DATA
0000
TRACK #
HEAD #
0001
SECTOR # FOR FIRST
0002
SECTOR AFTER INDEX
TRACK #
0003
HEAD #
0004
SECTOR # FOR SECOND
0005
SECTOR AFTER INDEX

o

o
o
o

TRACK #
HEAD #
SECTOR # FOR LAST
o
SECTOR ON THE TRACK
This format tabJe can start at any Ring Buffer memory
address.
o

The Local Processor should also set the DISK ADDRESS
Register in the DMA block to the first address in this 10 format
sequence. In this case it would be address 0000. The track
number, head number and sector number may be merged
into two bytes as a function of the disk format used.

725

For the microprogram shown below, the DESIRED
REGISTER FILE is loaded as follows:
DESIRED
REGISTER
LABEL
ADDRESS
M(GAP1) OC HEX
M(SYNC) OA HEX

CONTENTS

M(MC)

OB HEX

Al HEX

M(GAP2) OC HEX
M(AM)
OE HEX

4E HEX
FE HEX

SLEW

OF HEX

EO HEX

M(DM)
M(FDAT)
M(GAP3)
M(GAP4)

09
08
OC
OC

FB
E5
4E
4E

HEX
HEX
HEX
HEX

4E HEX
00 HEX

HEX
HEX
HEX
HEX

COMMENTS
DATA IN GAP 1
DATA IN SYNC
FIELD
MISSING CLOCK
PATTERN
DATA IN GAP 2
ADDRESS MARK
DATA
2'S COMPo OF #
OF SECTORS
(16) TO BE
WRITTEN
DATA MARK DATA
FORMAT DATA
DATA IN GAP3
DATA IN GAP4

In addition, the following variables, which control the length
of each field in the format command, are aSSigned the
specified values for this microprogram:
VARIABLE
GAP 1
GAP2
GAP3
PLO

ASSIGNED
VALUE
10 HEX
03 HEX
12 HEX
ODHEX

DTFLD

04 HEX

CRC

02 HEX

ECC

04 HEX

COMMENTS
LENGTH OF GAP 1
LENGTH OF GAP 2
LENGTH OF GAP 3
LENGTH OF PLO SYNC
FIELD
LENGTH OF DATA FIELD
(128 X 4 = 512)
LENGTH OF CRC FIELD
(USES CRC-16)
LENGTH OF ECC FIELD
(USES ECC-32)

This example assumes thatthe INDEX pulse from the drive
is input on TST1.
The microcode is loaded by the local processor in byte
address space 80H to FFH according to table 13.
LOCAL PROCESSOR
ADDRESS (A7-AO)
lXXXXXOO
lXXXXXOl
lXXXXX10
1 XXXXXll

DATA
(D7-DO)
OUT 3-0, EXT 3-0
REGISTER DECREMENT (PEN),
COUNTS-O
TEST 3-0, REGISTER POINTER
3-0 (POINT)
SEa 2-0, ADDR 4-0.

TABLE 13: LOCAL PROCESSOR TO MICROCODE
ADDRESS MAPPING

MICROPROGRAM:
INST#
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13

LABEL
START
WAIT
BEGIN

OUT
LAST

SEQ
TSJ
TSJ
SHLP
SHLP
SHLP
SHLP
SHLP
SHLP
SHLP
SHLP
SHLP
SHLP
SHLP
LGLP
SHLP
CI
TSJ
TSJ
SHLP
CI

ADDR
START
WAIT
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT
BEGIN
OUT
0
LAST

TEST
ONE
TST1
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
XEND
ZERO
TST1
ZERO
ONE

POINT
0
0
M(GAP1)
M(SYNC)
M(MC)
M(AM)
0
SLEW
0
M(GAP2)
M(SYNC)
M(MC)
M(DM)
M(FDAT)
0
SLEW
M(SYNC)
M(GAP4)
M(GAP4)
0

PEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

COUNT
4-1
GAP1-1
PLO-1
1-1
1-1
3-1
CRC-2
1-1
GAP2-1
PLO-1
1-1
1-1
DTFLD-1
ECC-1

1-1
1-1
GAP3-1
1-1
1-1
1-1

OUT
0
0
FREG
WPRE
WMISS
FREG
0
WCRC
WCRC
FREG
WPRE
WMISS
FREG
FREG
WCRC
FREG
FREG
FREG
FREG
DNINT

EXT
SGOFF
0
WGON
CRC16
0
SWDG
0
INCE
0
ECC32
0
0
0
0
0
0
0
0
SGOFF
SGOFF

COMMENTS:
031-00 is the actual assembled microcode loaded into the microprogram RAM.
INST#
00
01
02
03
04

031-00
OC03 FO 80
00 OF 7081
6F OCOCOO
4AOO OAOO
5000 OB 00

05

61 02 OE 00

06

00000000

07

9E 00 OF 00

08
09
OA
OB

90020000
6B OCOO 00
4000 OA 00
5000 OB 00

OC
00
OE
OF

60030900
60030820
90000000
6000 AF71

10
11
12

6011 OA 82
60004C91
6COO OCOO

13

FCOO FO 73

COMMENTS
ENSURE THAT READ AND WRITE GATE ARE OFF.
WAIT FOR INDEX AND THEN GO TO NEXT INSTRUCTION.
RAISE WRITE GATE; WRITE GAP 1 DATA FOR GAP 1 TIME.
WRITE PLO SYNC (PREAMBLE) DATA FOR PLO TIME.
WRITE MISSING CLOCK PATTERN USING MISSING CLOCK DATA
FOR 1 BYTE TIME.
WRITE ADDRESS MARK DATA FOR 1 BYTE TIME. PREPARE TRANSFER OF DATA
FROM RING BUFFER TO DISK AT NEXT INSTRUCTION VIA SWDG.
TRANSFER TWO CONSECUTIVE BYTES FROM RING BUFFER AS SPECIFIED BY
THE DISK ADDRESS REGISTER TO THE DISK; THESE TWO BYTES CONTAIN THE
HEAD #, TRACK # AND SECTOR #.
WRITE THE FIRST BYTE OF THE CRC; INCREMENT CONTENTS OF THE
DESIRED REGISTER LOCATION LABELED SLEW TO LATER CHECK FOR THE
END OF THE FORMAT COMMAND.
WRITE SECOND BYTE OF THE CRC.
WRITE GAP 2 DATA FOR GAP 2 TIME; PRESET ECC GENERATOR.
WRITE PLO SYNC (PREAMBLE) DATA FOR PLO SYNC TIME.
WRITE MISSING CLOCK PATTERN USING MISSING CLOCK DATA
FOR 1 BYTE TIME.
WRITE DATA MARK DATA FOR 1 BYTE TIME.
WRITE FORMAT DATA IN DATA FIELD FOR 512 BYTE TIMES.
WRITE A FOUR BYTE ECC.
CHECK FOR END OF COMMAND VIA XEND; IF END, GO TO OUT; ELSE GO
TO NEXT INSTRUCTION.
WRITE 1 BYTE OF SYNC DATA AFTER ECC; GO TO BEGIN.
WRITE A 4E UNTIL INDEX.
WRITE ONE MORE BYTE OF 4E; RESET WRITE GATE AS INSTRUCTION
IS EXITED.
SET THE DONE INTERRUPT TO THE LOCAL PROCESSOR; THE
MICROSEQUENCER WILL STOP HERE.
726

2-READ AND WRITE COMMANDS FOR ST-506
FORMATTED DISKS
Prior to executing a READ or WRITE command, using the
defined microprogram written in the Microprogram RAM, the
Local Processor should load the DESIRED REGISTER
FILE with the parameters used during the execution of the
microprogram. The microprogram will point to these
preloaded values, via the register pointer field, to permit the

LABEL
XFER

DESIRED REGISTER ADDRESS
00 HEX

data to be transferred to the ENCODER/DECODER block
and finally out to the disk. The Local Processor should also
set up the appropriate DMA address and function registers
and specify disk direction, External Device direction, and
initialize the zero status bit in the START COMMAND
Register prior to execution of microprogram.
For the microprogram shown, the DESIRED REGISTER
FILE is loaded as follows:

CONTENTS
BE HEX

ADDC1

01 HEX

11 HEX

ADDC2

02 HEX

1B HEX

M(DM)
M(AM)
M(SYNC)
M(MC)
SIZE

03
04
05
06
07

HEX
HEX
HEX
HEX
HEX

FB
FE
00
A1

-

RETRY

08 HEX

-

SLEW

09 HEX

-

SSECT

OAHEX

-

HEAD

OB HEX

-

TRACK

OC HEX

-

HEX
HEX
HEX
HEX

COMMENTS

! USED AS DISK DMA FUNCTION REGISTER

I DATA TO MOVE DISK ADDRESS REGISTER TO

DISK ADDRESS IN DMA BLOCK.
USED AS DISK DMA FUNCTION REGISTER
DATA TO ADD CONSTANT 1 TO OFFSET
COUNTER IN THE DMA BLOCK.
USED AS DISK DMA FUNCTION REGISTER
DATA TO CHECK FOR OVERFLOW OF THE
SUM OFFSET COUNTER PLUS CONSTANT 2
IN THE DMA BLOCK.
DATA MARK DATA.
ADDRESS MARK DATA.
DATA IN SYNC FIELD.
MISSING CLOCK PATTERN.
NOT IMPLEMENTED BUT CAN INDICATE THE
SIZE OF THE SECTOR (0,1,2,3, FOR
SECTOR SIZES OF 128, 256, 512 AND 1024
RESPECTIVELY).
NOT IMPLEMENTED BUT CAN BE USED AS A
RETRY COUNT WHEN ENCOUNTERING SOFT
ERRORS DURING A READ COMMAND.
LOADED WITH THE 2'S COMPLEMENT.
VARIABLE LOADED BY THE LOCAL
PROCESSOR INDICATING THE NUMBER OF
SECTORS TO BE READ OR WRITTEN DURING
THE COMMAND EXECUTION. LOADED WITH
THE 2'S COMPLEMENT.
INITIALIZED WITH THE STARTING SECTOR
NUMBER IN THE TRANSFER.
INITIALIZED WITH THE HEAD NUMBER TO BE
OPERATED ON.
INITIALIZED WITH THE TRACK NUMBER TO
BE OPERATED ON.

In addition, the following variables, which are loaded into
the loop counter to control the length of each instruction,
are aSSigned the specified values for this microprogram·
VARIABLE
ASSIGNED VALUE
COMMENTS
PLO
OD.HEX
LENGTH OF PLO SYNC FIELD
DTFLD
04 HEX
LENGTH OF DATA FIELD (128 X 4 = 512)
CRC
02 HEX
LENGTH OF CRC FIELD (USES CRC-16)
LENGTH OF ECC FIELD (USES ECC-32)
ECC
04 HEX
LENGTH OF DATA PAD AT END OF DATA FIELD
DTPAD
04 HEX

INST#
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F

LABEL
01
NEXT
10

WT

RA

XERR
HSKP
CKFULL
STP

COMMENTS·
INST# 031-00
OA 00 FO 81
00
01
DC 05 FO 82
057FF010
02
03
04
05
06

07
08

SEQ
TSJ
TSJ
SHLP
TSJ
TSJ
TSJ
CI
TSJ
SHLP
RC
SHLP
SHLP
SHLP
LGLP
SHLP
TSJ
TSJ
TSC
TSC
TSC
LGLP
SHLP
CI
SHLP
TSJ
TSJ
TSJ
SHLP
CI
TSJ
RC
TSJ

ADDR
NEXT
10
RA
NEXT
NEXT
10
STP
10
WT
STP
0
0
0
0
0
HSKP
0
STP
STP
STP
0
0
HSKP
0
0
0
0
10
STP
STP
CKFULL
0

TEST
ONE
ONE
ONE
SYNC
SYNC
EQ8
LNEQ
EQ8
CMD
NDERR
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ONE
SYNC
SYNC
EQ8
ZERO
ZERO
NDERR
ZERO
ONE
ONE
ONE
ONE
XEND
NTP2
NOVFLW
ZERO

POINT
0
0
0
0
0
M(AM)
HEAD
SSECT
0
0
M(SYNC)
M(MC)
M(DM)
0
0
M(SYNC)
0
0
0
M(DM)
0
0
3
0
XFER
0
SLEW
ADDC1
SSECT
ADDC2
0
0

PEN
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0

COUNT
1-1
6-1
128-1
PLO-1
1-1
2-1
1-1
CRC-1
1-1
PLO-1
1-1
1-1
4-1
ECC-1
DTPAD-1
1-1
2*PLO-1
2*PLO-1
1-1
DTFLD-1
ECC-1
1-1
ECC-2
1-1
1-1
1-1
1-1
1-1
1-1
1-1
6-1
0

OUT
0
0
0
0
0
0
0
0
0
0
WPRE
WMISS
FREG
0
WCRC
FREG
0
0
0
0
RDG
0
SNDRM
SNDRM
PREQ1
PINTO
0
PREQ1
0
PREQ1
0
DNINT

EXT
CRC16
SGOFF
SPRE
SMC
0
0
TREG
SRCRC
SGOFF
ECC32
WGON
0
SWDG
0
0
SGOFF
SPRE
SMC
0
0
SRCRC
SGOFF
0
0
0
0
INCE
ZRCLR
INCE
0
0
SGOFF

COMMENTS
PRESET THE CRC CHECKER.
SHUT READ GATE AND WRITE GATE OFF.
WAIT HERE FOR 6 BYTE TIMES; PUT RA (INST #10) ON STACK. SET READ GATE
AND START LOOKING FOR PLO SYNC (PREAMBLE) AS INSTRUCTION IS EXITED
(VIA SPRE).
06 DC 20 80 LOOK FOR ALL D'S; WAIT 128 BYTE TIMES; IF FOUND, GO TO NEXT
INSTRUCTION; ELSE, GO TO NEXT (INST #1).
00002080 LOOK FOR THE MISSING CLOCK PATTERN FOR THE PLO TIME; IF FOUND, GO
TO NEXT INSTRUCTION; ELSE, GO TO NEXT (INST #1).
00018482 LOOK FOR AN "FE" ADDRESS MARK VIA 8 BIT COMPARE (EQ8). IF FOUND, GO
TO NEXT INSTRUCTION; ELSE, GO TO 10 (INST #2).
0880 9B 7F LOOK FOR TRACK AND HEAD COMPARE; IF COMPARE, GO TO NEXT
INSTRUCTION; ELSE, GO TO STP (INST #1 F). THIS BRANCH MEANS THAT THE
DISK IS ON THE WRONG TRACK. AT INSTRUCTION STP, THE LOCAL
PROCESSOR WILL BE INTERRUPTED; READING THE PC REGISTER WILL TELL
THE PROCESSOR THAT THE INTERRUPT WAS GENERATED BY THIS
INSTRUCTION; A STEP ROUTINE WILL USUALLY BE EXECUTED BY THE LOCAL
PROCESSOR. ALSO, THE TRACK AND HEAD NUMBER FROM THE DISK IS SAVED
IN THE CURRENT REGISTER FILE.
0201 8A 82 LOOK FOR SECTOR NUMBER COMPARE; IF COMPARE WITH DESIRED SECTOR
(IN DESIRED REGISTER FILE), GO TO NEXT INSTRUCTION; ELSE, GO TO 10
(INST #2).
DC 00 CO OA TEST FOR READ OR WRITE COMMAND. IF WRITE COMMAND, PUT WT (INST
#OA) ON STACK (lNST #02 PUT RA ON STACK PREVIOUSLY). AS INSTRUCTION
IS EXITED, TURN OFF READ GATE. THE CRC IS CHECKED HERE.
728

COMMENTS'
INST#
031-00
COMMENTS
09
OB OC 30 5F CHECK FOR GOOD CRC. IF GOOD, LOAD THE STACK TO THE PC (GO TO EITHER
RA OR WT). ELSE, GO TO STP (INST #F) TO END THE COMMAND. A RETRY CAN
BE IMPLEMENTED IF DESIRED TO ATTEMPT TO READ THE ID A NUMBER OF
TIMES.
OA
4F 00 05 00 THIS IS THE START OF THE WRITE ROUTINE; TURN WRITE GATE ON AND
WRITE THE PLO SYNC (PREAMBLE) FIELD, PLO TIMES.
OB
50000600 WRITE THE MISSING CLOCK PATTERN.
61030300 WRITE THE DATA MARK PATTERN. PREPARE DMA TRANSFER OF DATA FIELD
OC
FROM RING BUFFER AT NEXT INSTRUCTION.
OD
00030020 TRANSFER RING BUFFER DATA TO DISK FOR 4X128 TIMES.
OE
90030000 WRITE THE FOUR BYTE ECC FIELD.
OF
6C 00 05 9A WRITE A FOUR BYTE DATA PAD AFTER THE ECC BYTES. GO TO HSKP (INST
#1A; HOUSEKEEPING) FOR DMA UPDATES. TURN OFF WRITE GATE.
10
0519F080 THIS IS THE START OF THE READ COMMAND. PREPARE TO LOOK FOR ALL PLO
SYNC FIELD. RAISE READ GATE AS INSTRUCTION IS EXITED.
11
061920BF LOOK FOR PLO SYNC (PREAMBLE) FOR 2 X PLO TIME. IF FOUND, GO TO NEXT
INSTRUCTION; ELSE, GO TO STP (INST #1F) WHICH WILL END THE COMMAND
VIA A LOCAL PROCESSOR INTERRUPT. THE VALUE IN THE PC WILL INDICATE
TO THE LOCAL PROCESSOR THAT A PLO SYNC (PREAMBLE) OF ALL O'S WAS
NOT FOUND IN THE ALLOTTED TIME AFTER A VALID 10 WAS FOUND.
12
000120 BF LOOK FOR MISSING CLOCK PATTERN FOR 2 X PLO TIME. IF FOUND, GO TO
NEXT INSTRUCTION; ELSE, GO TO STP (INST #1F) WHICH WILL END THE
COMMAND VIA A LOCAL PROCESSOR INTERRUPT. THE VALUE IN THE PC WILL
INDICATE TO THE LOCAL PROCESSOR THAT A MISSING CLOCK PATTERN WAS
NOT FOUND IN THE ALLOTTED TIME AFTER A PLO SYNC (PREAMBLE) WAS
FOUND.
13
000383 BF LOOK FOR "FB" DATA MARK. IF FOUND, GO TO NEXT INSTRUCTION; ELSE, GO
TO STP (INST #1 F) WHICH WILL END THE COMMAND VIA A LOCAL PROCESSOR
INTERRUPT. THE VALUE IN THE PC WILL INDICATE TO THE LOCAL PROCESSOR
THAT A DATA MARK WAS NOT FOUND AFTER A MISSING CLOCK PATTERN.
22030020 START THE TRANSFER OF DATA FROM THE DISK TO THE RING BUFFER VIA THE
14
SIGNAL RDG WHICH REQUEST CHANNEL ACCESS TO THE RING BUFFER. THE
DMA ADDRESS WILL AUTOMATICALLY BE INCREMENTED. START THE
CHECKING OF THE ECC AS THIS INSTRUCTION IS EXITED.
15
OC 80 00 00 TRANSFER THE ECC BYTES TO THE CURRENT REGISTER FILE ADDRESSES 3,
2, 1 AND O. TURN OFF READ GATE AS INSTRUCTION IS EXITED.
16
7002337A CHECK FOR ECC ERROR. IF ERROR, GO TO NEXT INSTRUCTION; ELSE, GO TO
HSKP (INST #1A; HOUSEKEEPING). TRANSFER FIRST ECC SYNDROME INTO
CURRENT REGISTER FILE LOCATION 3.
17
70800000 THIS INSTRUCTION IS ENTERED IF AN ECC ERROR IS FOUND. TRANSFER THE
REMAINING 3 BYTES OF ECC SYNDROME INTO CURRENT REGISTER
LOCATIONS 2, 1, AND O.
18
8000 FO 80 SINCE DATA WAS BAD, REINITIALIZE THE DMA DISK ADDRESS REGISTER BACK
TO THE BEGINNING OF THE SECTOR BY LOADING THE CONTENTS OF XFER (IN
THE DESIRED REGISTER FILE), TO THE DMA DISK FUNCTION REGISTER
CAUSING THE TRANSFER OF THE DISK REGISTER TO THE DISK ADDRESS.
19
CO 00 FO 80 GENERATE AN INTERRUPT TO THE LOCAL PROCESSOR VIA PINTO WHICH IS
USED FOR ECC ERROR INTERRUPTS. THIS INTERRUPT DELINKS THE OFFSET
AND AUXILIARY OFFSET COUNTERS IN THE DMA BLOCK.
1A
OE 00 F9 80 THIS IS THE START OF THE DMA HOUSEKEEPING FUNCTION. THE LOCATION IN
THE DESIRED REGISTER FILE LABELED SLEW IS INCREMENTED. LATER A TEST
IS DONE TO DETERMINE IF ALL THE SECTORS IN THE COMMAND HAVE BEEN
READ OR WRITTEN.
1B
8D 00 F1 02 ADD CONSTANT 1 REGISTER TO THE OFFSET COUNTER. PUT ADDRESS ID
(INST #2) ON STACK; CLEAR ZERO FLAGS IN DMA BLOCK.
OE 00 AA 7F CHECK FOR END OF COMMAND VIA SLEW BEING INCREMENTED TO ZERO. IF
1C
END, GO TO STP (INST #1F); ELSE, GO TO NEXT INSTRUCTION. INCREMENT
THE DESIRED REGISTER LOCATION CONTAINING THE SECTOR NUMBER TO BE
OPERATED ON NEXT.
729

COMMENTS'
INST# D31-DO
COMMENTS
10
8000 B29F ADD CONSTANT 2 TO OFFSET COUNTER BUT DO NOT UPDATE THE OFFSET
COUNTER. JUST UPDATE THE OVERFLOW BIT. IF TP2 IS A LOCIC ONE (NTP2 A
ZERO), GO TO STP (INST #1F) BECAUSE A HALT, ABNORMAL DATA MARK OR
DELETED DATA MARK HAS BEEN ENCOUNTERED. ELSE, GO TO NEXT
INSTRUCTION.
1E
0005 DO 5D CHECK FOR OVERFLOW. IF OVERFLOW DURING WRITE, NO DATA IS
CURRENTLY AVAILABLE TO WRITE; FOR READ, NO BUFFER SPACE IS
AVAILABLE. IF OVERFLOW (NOVFLW = 0), GO TO CKFULL TO RECALCULATE THE
OVERFLOW STATUS; IF NO OVERFLOW (NOVFLW = 1), PUT THE STACK (WHICH
CONTAINS LOCATION ID; INST #02)INTO THE PC AND LOOK FOR THE NEXT ID.
1F
FC 00 00 80 THIS IS THE STOP LOCATION. A DONE INTERRUPT IS GENERATED TO THE
LOCAL PROCESSOR AND THE READ AND WRITE GATES ARE TURNED OFF. THE
MICROSEQUENCER IS STOPPED HERE BUT THE LOCAL PROCESSOR CAN
READ THE PREVIOUS VALUE OF THE PC (THE LOCATION OF THE INSTRUCTION
THAT BRANCHED TO HERE) VIA STATUS REGISTER 3 BITS D4-DO TO
DETERMINE HOW AND WHY THE COMMAND ENDED.

APPENDIX 2-DMA OPERATION EXAMPLES
It should be noted that a ">" indicates operations performed
automatically by the MSD95C02.
EXAMPLE 1-LOCAL PROCESSOR LOADS DMA
ADDRESS INTO DMA REGISTER FILE:
1. Write DMA FUNCTION Register to configure for
MAILBOX ~ LOCAL PROCESSOR ADDR.
2a. Write DMA address MSB data to MAILBOX HIGH
Register.
2b. Write DMA address LSB data to MAILBOX LOW
Register.
This operation triggers the next event by setting the cycle
request latch.
> transfer address data from Mailbox to DMA address
register.
EXAMPLE 2-LOCAL PROCESSOR READS DMA
ADDRESS:
1. Write DMA FUNCTION Register to configure for LOCAL
PROCESSOR ADDR ~ MAILBOX.
The transfer will take place automatically after this step as
follows:
> transfer address data from DMA address register to
Mailbox.
Local processor may r~ad DMA address data MSB's from
the MAILBOX HIGH Register and DMA address data LSB's
from the MAILBOX LOW Register. Bit 1 (REQUEST 1) of
STATUS 1 Register can be used to determine when the
operation is complete.
3-LOCAL PROCESSOR READS
SEQUENTIAL RING BUFFER DATA:
The local processor will initialize the Address location in the
DMA address register with the starting ring buffer address.
The MSD95C02 will automatically fetch the data in that
location and deposit it in the DATA Register. The Local
Processor may program the MSD95C02 to increment the
DMA address after every transfer via the DMA FUNCTION
Register. This permits the Local Processor to read
sequentially located data in the Ring Buffer without any
address manipulation by the Local Processor.
1. Write DMA FUNCTION Register to configure for
MAILBOX-,> LOCAL PROCESSOR ADDR.
2a. Write DMA address data to MAILBOX HIGH Register.
EXAMPLE

2b. Write DMA address data to MAILBOX LOW Register.
This operation triggers the following events by setting the
cycle request latch.
> Transfer address data from the mailbox to the DMA
ADDRESS Register.
> Output address data from LOCAL PROCESSOR
ADDRESS Register to Ring Buffer.
> Fetch data from Ring Buffer, leave in DATA Register and
reset the cycle request latch.
3. Write DMA FUNCTION Register to configure for LOCAL
PROCESSOR ADDR. + 1~LOCAL PROCESSOR
ADDR.
4. Read DATA Register (set Cycle Request and Read
latches) for data transfer.
> MSD95C02 will output address data from LOCAL
PROCESSOR ADDRESS Register to Ring
Buffer.
> MSD95C02 will increment address data in
LOCAL PROCESSOR ADDRESS Register.
> MSD95C02 will input data from Ring Buffer, store
it in the DATA Register and reset the cycle request
latch.
Data can be read sequentially by the local processor by
continually reading the DATA Register. Each read of the
DATA Register will automatically trigger a new ring buffer
access cycle at the next sequentially located memory
location.
EXAMPLE4-LOCAL PROCESSOR WRITES SEQUENTIAL
DATA TO RING BUFFER:
The Local Processor will initialize the address location in
the DMA address register with the ring buffer address. The
MSD95C02 will automatically fetch the data in that location
and leave it in the DATA Register. The Local Processor may
program the MSD95C02 to increment the DMA address
after every transfer via the DMA FUNCTION Register. This
permits the Local Processor to sequentially write data into
the Ring Buffer without any address manipulation by the
Local Processor.
1. Write DMA FUNCTION Register to configure for
MAILBOX~ LOCAL PROCESSOR ADDRESS.
2a. Write DMA address data to MAILBOX HIGH Register.
730

> Initialize OFFSET and AUXILIARY OFFSET

2. Write DMA address data to MAILBOX LOW Register.
This operation triggers the next event by setting the cycle
request latch.
> Transfer address data from Mailbox to DMA address
register.
> Output address data from DMA address register to Ring
Buffer.
> Fetch data from Ring Buffer and leave in DATA Register;
Reset cycle request latch.

COUNTERs with OOH and reset cycle request.
2. The Local Processor will set the DMA FUNCTION
Register for a Mailbox to CONSTANT 1 location
transfer and write a value of 512 (the sector size) into
the MAILBOX HIGH and LOW Registers, generating
a dummy request.
> Transfer value 512 from Mailbox to CONSTANT 1
location and reset cycle request.
3. The Local Processor will set the DMA FUNCTION
Register for a Mailbox to CONSTANT 2 location
transfer and write the value 64K - 2K + 512 -1 into
the MAILBOX HIGH and LOW Registers. The
General form for CONSTANT 2 is [64K - (BUFFER
SIZE) + (SECTOR SIZE) -1], generating a dummy
request.
> Transfer value 64K -2K + 512 -1 from Mailbox
to CONSTANT 2 location and reset cycle request.
4. The Local Processor will set the DMA FUNCTION
Register for a Mailbox to External Device Address
location transfer and write the buffer starting address
into the MAILBOX HIGH and LOW Registers,
generating a dummy request.
> Transfer start address from Mailbox to External
Device Address location and reset cycle request.
5. The Local Processor will set the DMA FUNCTION
Register for a Mailbox to DISK Address location
transfer and write the buffer starting address into the
MAILBOX HIGH and LOW Registers, generafing a
dummy request.
> Transfer start address from Mailbox to disk
address location and reset cycle request.
6. The Local Processor will set the DMA FUNCTION
Register for a Mailbox to DISK Register location
transfer and write the buffer starting address into the
MAILBOX HIGH and LOW Registers, generating a
dummy request.
> Transfer start address from Mailbox to DISK
Register location and reset cycle request.
7. Write the sector ID information and the number of
sectors to be read (SLEW) into the appropriate
locations in the DESIRED REGISTER FILE registers
and issue a Start Command with the Disk Direction
bit set to one and the External Device Direction bit
set to zero. External device DMA requests can start
at any time since they will not be acknowledged until
one error free sector is deposited into the Ring Buffer.
The MICROSEQUENCER routine will ensure that
the OFFSET COUNTER is incremented by the
sector size (512) when the MSD95C02 finishes
transferring an error free sector into the Ring Buffer.
B. When the OFFSET COUNTER is greater than zero,
the external channel's DMA requests will be
acknowledged. The OFFSET COUNTER will be
decremented by 1, 2, 3 or 4 (depending on the
programming of MODE 1 Register) every time the
external channel reads data from the Ring Buffer.
9. The MICROSEQUENCER will add the OFFSET
COUNTER value and CONSTANT 2 together before
beginning the next sector transfer into the Ring
Buffer. This calculation is done to determine buffer
full/empty status. This is done without altering the
contents of the OFFSET COUNTER.
> If ALU Overflow status is active, then the buffer
is full.

3. Write DMA FUNCTION Register to configure for LOCAL
PROCESSOR ADDRESS + 1 ~ LOCAL PROCESSOR
ADDRESS.

4. Write to DATA Register (set Cycle Request and Write
latches) for data transfer.
> output address data from DMA address register
to Ring Buffer.
> increment address data in DMA address register.
> output data from DATA Register to Ring Buffer
and reset the cycle request latch.
Data can be written sequentially by the local processor by
continually writing the DATA Register. Each write to DATA
Register will automatically trigger a new ring buffer access
cycle at the next sequentially located memory location.
EXAMPLE 5-DATA IS READ FROM THE DISK AND
WRITTEN INTO THE RING BUFFER AND
SIMULTANEOUSLY, DATA IS READ
FROM THE RING BUFFER OUT OVER
THE EXTERNAL CHANNEL (SCSI):
This function of filling the Ring Buffer from the disk data and
emptying the Ring Buffer over the external channel involves
two independent and simultaneous operations. The
description of this example will explain the local processor's
involvement in this example. It is the role of the local
processor to set up the DMA controller block such that the
two operations can take place. Once the external channel's
DMA registers are set up, the operation involves a simple
DMA request-acknowledge handshake to empty the buffer.
Automatic throttling on the DMA acknowledge to the external
channel will occur as described in the section on the DMA
block operation.
In addition, there is a MICROSEQUENCER routine that is
executed when the Local Processor causes a command to
be started. The details olthe MICROSEQUENCER routine
is described in appendix 1.
It is the role of the Local Processor to initialize the OFFSET
and AUXILIARY OFFSET COUNTERs, CONSTANT 1 and
CONSTANT 2 Registers, as well as the starting ring buffer
addresses for the disk and external channel data. The
MICROSEQUENCER will assume that these registers are
initialized and use then accordingly to calculate buffer full/
empty status which is used to automatically throttle the DMA
request coming from the disk, which are initiated and
controlled by the MICROSEQUENCER, and the External
Device DMA requests.
For this example, it is assumed that the sector size is 512,
and the ring buffer size is 2K.
1. The Local Processor will set the DMA FUNCTION
Register for a Mailbox to OFFSET COUNTER
transfer and write OOH into the MAILBOX HIGH and
LOW Registers (generating a dummy request).

731

> If the OFFSET COUNTER equals zero, then the

location transfer and write the buffer starting
address into the MAILBOX HIGH and LOW
Registers, generating a dummy request.
> Transfer start address from Mailbox to External
Device Address location and reset cycle request.
5. The Local Processor will set the DMA FUNCTION
Register for a Mailbox to DISK Address location
transfer and write the buffer starting address into
the MAILBOX HIGH and LOW Registers,
generating a dummy request.
> Transfer start address from Mailbox to disk
address location and reset cycle request.
6. The Local Processor will set the DMA FUNCTION
Register for a Mailbox to DISK Register location
transfer and write the buffer starting address into
the MAILBOX HIGH and LOW Registers,
generating a dummy request.
> Transfer start address from Mailbox to DISK
Register location and reset cycle request.
7. Start the transfer of sector data from the External
Device to the Ring Buffer. Since the OFFSET
COUNTER is decremented as information is
deposited into the Ring Buffer from the external
channel, and the OFFSET COUNTER is initialized
to 512, it will hit zero after one sector is written into
the Ring Buffer. Loading the OFFSET Register with
512 initially, ensures that there is at least 1 sector
of data in the Ring Buffer before disk writing is
started.
8. The Local Processor will set the DMA FUNCTION
Register for a Mailbox to OFFSET COUNTER
transfer and write 64K - 512 + 1 into the MAILBOX
HIGH and LOW Registers, generating a dummy
request.
> Initialize OFFSET COUNTER with 64K - 512
+ 1 and reset cycle request.
The External Device is free to continue data transfer
into the Ring Buffer.
9. Write the sector ID information and the number of
sectors to be written (SLEW) into the appropriate
locations in the DESIRED REGISTER FILE
registers and issue a Start Command with the
Disk Direction bit set to 0 and the External
Device Direction bit set to 1. This starts a
MICROSEQUENCER routine to transfer data from
the Ring Buffer to the disk. The OFFSET
COUNTER is incremented by 512 when the
MSD95C02 finishes transferring a sector from the
Ring Buffer to the disk.
10. Before transferring a sector to the disk, the
MICROSEQUENCER will add the OFFSET
COUNTER value and CONSTANT 2 (64K -512
+ 1). This calculation allows the
MICROSEQUENCER to determine if at least
1 more sector resides in the Ring Buffer by
checking the overflow flag in the DMA's ALU. This
is done without altering the contents of the
OFFSET COUNTER. If it is determined that the
buffer is empty (overflow = 1), all DMA requests
for data to the Ring Buffer, which are initiated by
the MICROSEQUENCER, will be held off.

buffer is empty.
If the buffer is full, the MSD95C02 will wait before
transferring the next sector into it. If the buffer is
empty, the External Channel's DMA requests will not
be serviced.
EXAMPLE 6-DATA IS WRITTEN TO THE DISK BY
SIMULTANEOUSLY WRITING TO THE
RING BUFFER FROM THE EXTERNAL
CHANNEL AND READING FROM THE
RING BUFFER FOR DATA TRANSFER
ON TO THE DISK.
This function of filling the Ring Buffer from the EXTERNAL
CHANNEL and emptying the Ring Buffer for data transfer
to the disk involves two independent and simultaneous
operations. The description of this example will explain the
Local Processor's involvement in this example. It is the role
of the Local Processor to set up the DMA controller block
such that the two operations can take place. Once the
External Channel's DMA registers are set up, the operation
involves a simple DMA request-acknowledge handshake to
start filling the buffer. Automatic throttling on the DMA
acknowledge to the External Channel will occur if the buffer
becomes full.
In addition, there is a MICROSEQUENCER routine that is
executed when the Local Processor causes a command to
be started. The details of the MICROSEQUENCER routine
is described in appendix 1.
It is the role of the Local Processor to initialize the OFFSET
and AUXILIARY OFFSET COUNTERs, CONSTANT 1 and
CONSTANT 2 Registers, as well as the starting ring buffer
addresses for the disk and external channel data. The
MICROSEQUENCER will assume that these registers are
initialized and use then accordingly to calculate buffer full/
empty status which is used to automatically throttle the DMA
request coming from the disk, which are initiated and
controlled by the MICROSEQUENCER, and the external
channel's DMA requests.
For this example, it is assumed that the sector size is 512,
and the Ring Buffer size is 2K.
1. The Local Processor will set the DMA FUNCTION
Register for a Mailbox to Offset Counter transfer and
write 512 into the MAILBOX HIGH and LOW
Registers, generating a dummy request.
Initialize OFFSET and AUXILIARY OFFSET
COUNTERs with 512 and reset cycle request.
2. The Local Processor will set the DMA FUNCTION
Register for a Mailbox to Constant 1 location transfer
and write a value of 512 (the sector size) into the
MAILBOX HIGH and LOW Registers, generating a
dummy request.
> Transfer value 512 from Mailbox to Constant 1
location and reset cycle request.
3. The Local Processor will set the DMA FUNCTION
Register for a Mailbox to Constant 2 location
transfer and write the value 64K - 2K + 512 -1
into the MAILBOX HIGH and LOW Registers. The
General form for CONSTANT 2 is [64K (BUFFER SIZE) + (SECTOR SIZE) -1],
generating a dummy request.
> Transfervalue64K - 2K + 512 -1 from Mailbox
to Constant 2 location and reset cycle request.
4. The Local Processor will set the DMA FUNCTION
Register for Mailbox to External Device address

11. If the buffer is full (OFFSET COUNTER = zero),
DMA requests from the External Device will not be
serviced.

732

APPENDIX 3. ERROR CORRECTION ON THE FLY:
In order to perform error correction on the fly, a Reed
Solomon ECC with CRC extension is recommended.
When a disk read operation detects an error, the
MICROSEQUENCER program will set Program Interrupt 0
(PROG 0) which automatically delinks the OFFSET the
AUXILIARY OFFSET COUNTERs. Further, the micro·
program will cause the error syndrome bytes to be
transferred into designated sequential locations in the
DESIRED REGISTER FILE. The generation of this interrupt
will also permit the Local Processor access to the
CURRENT REGISTER FILE. Transfer of data into the Ring
Buffer from the disk and out of the Ring Buffer to the external
channel will continue simultaneous to the error correction
operation.
When the Local Processor gets an interrupt, it will read the
error syndrome bytes out to the CURRENT REGISTER
FILE and then immediately write a logic one to bit D2 (CRR)
of the START COMMAND REGISTER (ADDR 54H). This
permits the disk to regain access to the CURRENT
REGISTER FILE to allow proper processing of the next
sector. Next, the Local Processor should use the error
syndrome bytes to calculate the error pattern and location.
Once this is performed, a read modify write operation to the
calculated Ring Buffer locations wili correct the error.

While this is going on, data will continue to be read from the
disk and transferred out over the external channel. As new
error free sectors are read, only the OFFSET COUNTER is
increased by the sector size. As the external channel reads
data out of the Ring Buffer, both the OFFSET and
AUXILIARY OFFSET COUNTERs are decremented
together. If the AUXILIARY OFFSET COUNTER reaches
zero, the external channel's DMA requests are temporarily
held off. Buffer full status is determined as usual by the
MICROSEQUENCER using the value in the OFFSET
COUNTER and CONSTANT 2.
Once the error has been corrected, the OFFSET and
AUXILIARY OFFSET COUNTERS must be linked back
together again. This is accomplished by loading the DMA
FUNCTION Register (ADDR 50 H) with a value 09 H. This
special function will load the value of the OFFSET
COUNTER into the AUXILIARY OFFSET COUNTER and
permit these counters to both increment and decrement
together. This function will be performed when the Local
Processor writes any value rnto the MAILBOX LOW Register
(ADDR52H).
It should be noted that when errors occur on multiple sectors,
this special function must not be initiated until all bad sectors
are corrected.

74LS245

DATA IN
7-0

GENERIC
ECCCHIP

DATA OUT
7-0

DATAIECC

CHIP
SELECT

GENERIC
ECCCHIP
MSD95C02
READ ENABLE

WRITE ENABLE
WGATE
RGATE

PRESET
ERROR

TST4

FIGURE 20: MSD 95C02 USED WITH OPTIONAL EXTERNAL ECC CHIP

733

TO RING
BUFFE;R

APPENDIX 4-USE WITH AN EXTERNAL ECC
CHIP
The MSD95C02 has been designed to allow operation with
an external ECC chip. To allow this operation, it is necessary
for the external ECC chip to be able to determine three
situations.
1-The time when the MSD95C02 is performing a disk
access cycle.
2-The disk access cycle is a read or write cycle.
3-The access cycle is for data transfer or ECC transfer.
Figure 20 shows connection to a generic ECC chip. The
required information for proper operation is presented to the
outside world via the signals DGATE, ST1, STO and WRITE
It should be noted that the DATA ERROR Signal from the
external ECC chip must be valid when it is checked by the
MICROSEQUENCER.

Registers 1 & 4 and the incoming decoded bit stream. For
a valid compare, SYNC Registers 1 & 4 should be
programmed with the following values:
SYNC 1 Register = 7A
SYNC 4 Register = 00
The two cases above assume that bit 03 of MODE 2
Register (8/16 COMPARE) is set to select the 16 bit compare
mode.

APPENax&-OUTIUNE OF REED SOUlMON ERROR

APPENDIX 5-USE OF SYNC REGISTERS WITH
RLL ENCODING:
For RLL encoding, two missing clock patterns are
recommended.
1-For RLL 2,7 type 1, a missing clock pattern of FO is
recommended along with a PLO SYNC pattern of 00. During
the RLL encoding process, the PLO SYNC field of all zeros
will encode on the disk as a repeating 100 pattern. If the
PLO SYNC field is of such a length that an RLL encoding
grouping ends at the 00 to FO boundary, then reliable bit
synchronization via missing clock pattern detection can
occur. The length of the PLO SYNC field during disk writing
can be controlled via microcode.
Loading 00 and FO in DESIRED REGISTER FILE locations
and outputting them to the disk via the microcode signal
WPRE and WMISS, will produce a unique pattern on the
disk. In order to read this unique pattern back and obtain bit
synchronization via the high speed compare, the signal SMC
is activated which will cause a compare between SYNC
Registers 1 & 4 and the incoming decoded bit stream. For
a valid compare, SYNC Registers 1 & 4 should be
programmed with the following values:
SYNC 1 Register = FO
SYNC 4 Register = OB
2-For RLL 2, 7 type 2, a missing clock pattern of 7A is
recommended along with a PLO SYNC pattern of FF. During
the RLL encoding process, the PLO SYNC field of all ones
will encode on the disk as a repeating 1000 pattern. In this
case, the length of the PLO SYNC field is not a critical
parameter in obtaining reliable bit synchronization.
Loading FF and 7A in DESIRED REGISTER FILE locations
and outputting them to the disk via the microcode signal
WPRE and WMISS, will produce a unique pattern on the
disk. In order to read this unique pattern back and obtain bit
synchronization via the high speed compare, the signal SMC
is activated which will cause a compare between SYNC

CORRECTION AND VERIFICATION
ROUTINES
The Reed Solomon ECC has been designed to permit the
user correction of a maximum of two error bursts. The ability
to correct two burst errors is generally associated with Reed
Solomon codes. Using Reed Solomon alone, there is a finite
probability of miscorrection ifthe error appearing in the data
falls outside the capability of the Reed Solomon code used.
The MSD95C02 allows the user to attach an optional CRC
field to the Reed Solomon ECC field to permit detection of
virtually all miscorrected data.
The following steps should be performed to successfully
correct a data error via Reed Solomon ECC and verify that
the correction was performed properly:
1. If an error is detected, the MICROSEQUENCER will
interrupt the Local Processor with the syndrome bytes
(information used to correct the error) and the CRC field
residing in the CURRENT REGISTER FILE.
2. The Local Processor will read the syndrome and CRC
bytes and use the syndrome bytes to calcuate the error
pattern (exclusive OR mask) and error location (in the Ring
Buffer memory). This calculation is performed via table
lookup in software. For the Reed Solomon code
implemented in the MSD95C02, three tables of 256 bytes
each are required. These three tables are a Log, antilog and
root table. The generation of the error pattern will require a
maximum of 6 recursive table lookups and the generation
of the error location will require a maximum of 3 recursive
table lookups. It is this routine that will indicate if the error
in the data is correctable or uncorrectable.
3. Once the error location and error pattern are determined,
the Local Processor will set up the DMA block to perform
the required read-modify-write operation to correct the error.
4. Once the error is corrected, the Local Processor should
verify if the error was corrected properly. This is done by
taking the error pattern generated in step 2 and performing
another table lookup (uses the same antilog table as step
2) and taking this result and exclusive ORing it with one of
the CRC bytes read in from the CURRENT REGISTER FILE
in step 1. This is performed for each interleave. The result
of these operations should yield zero if the error was
corrected properly and yield a non zero if the error was not
corrected properly.
Details of the three tables and actual software routines will
be available in associated application notes.

734

735

Circurt diagrams utilizing SMC products 8'e included as a means of illustrating typical semiconductor applications: consequenfly complete information sufficient for construction purposes is not necessarify given. The information has been carefully
checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such
information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of
SMC or others. SMC reserves the right to make change~ at af!y tima in Oide. iu improve dasign and supply the best product
possible.
736

JIQt

.0. of

Z;:'" Keyboard Encoder
~

Ke;ya

IIod••

XB.9600 XXeet

90

.Pa.oJrag.
40DIPI
44SMT

Binary SequentiaJ.

ABon

738

KR9600
KR9601
KR9602
Keyboard Encoder Read Only Memory
KEM
PIN CONFIGURATION*

FEATURES
D On-chip "caps" lock (KR9601, KR9602)
D On-chip auto repeat (KR9601, KR9602)
D Contact bounce protection
D N Key Rollover or Lockout operation
D Hysteresis on keyboard matrix inputs
D Tri-state TTL compatible data outputs
D Serial output (on KR9602 only)
D Quad Mode (Normal, shift, control,
shift-control)

D High frequency clock input
D Pin-compatible with KR3600 (KR9600)
D Static charge protection on all inputs
and outputs

D + 5 volt supply

EXTERNALLY SELECTABLE
OPTIONS ON KR9600 AND KR9601
D Pulse or level data ready output signal
D External clock input
D On chip master/slave oscillator
D All 10 output bits available
D Lockout/Rollover external selection
D Chip enable external selection
D Data complement control
D Any Key Down output
D Selectable Auto-Repeat rate
D Programmable Auto-Repeat rate

KR9600/KR9601

FUNCTION

OPTION {

_

".0

40 xO
39 xl
38 x2
37 x3
36 x4
35 x5
34 x6
33 x7
32 x8
31 delay node
30 Vee
29 shift input
28 control input
27 caps lock (NC on KR9600)
26 y9
25 y8
24 y7
23 y6
22 y5
21 y4

OPTION
assignment
OPTION
chart"
OPTION
OPTION
OPTION
(B9 on KR9600)
data output B8
data output B7
data output B6
d,!ta output 85
data output B4
data output B3
data output B2
data output Bl
Gnd
data ready
yO
yl
y2
y3

FUNCTION
X3
X2
XI
XO
Scan clock
Serial clock
Gnd
Serial output
yO
yl
y2
y3
y4
y5

1
2
3
4
5

6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

X4
X5
X6
X7
X8
Delay node
Vee
Shift
Control
Caps Lock
y9
y8
y7
y6

'PLCC (J LEAD QUAD PACK) also available ..

GENERAL DESCRIPTION
The KR9600/1/2 is a keyboard encoder that contains all the
logic necessary to debounce and encode SPST keyswitches into a fully decoded data output of up to 10 bits.
The KR9600/1/2 contains a 3600 bit ROM, 9 stage and 10
stage ring counters, a 10 bit comparator, timing circuitry, a
90 bit memory to store the location of encoded keys for N
key rollover operation, an externally controllable delay net-

739

work for eliminating the effect of contact bounce, an output
data buffer and TTL compatible output drivers.
The KR9600 and the KR9601 provide a parallel data output
in a 40 pin configuration with pin selectable options, while
the KR9602 provides a serial asynchronous output in a 28
pin configuration with mask programmable options. (Ref.
KR9600/1/2 custom coding information sheet).

,----15 1

GND

Vcr;

Yo y, y,- y,- y. y, y, y, y,- y,,.

c::1~1~"'N (\I('I')...,.1OW
C\lC\lC\lC\l
-----------------~

-+

MASTER/SLAVE!
OSCILLATOR I

SCALER

+SV

;<'+
I

1

..

GND

r--i

10 BIT COMPARATOR

I

Itt

I
I

"'.,,

1

'v'

~

TIMING
CKT

R:

0

) T
1

28

..

TI

Ir'I

1
271

1

I
I

I:

MODE
DECODEi----'

~

{~
"1

I
GND

COMPLEM NT!
CONTH lL
(OPTIO ~)

~::D

1

L____

3600 BIT ROM

33
32

o

e
y,

v

90 SPST
KEYBOARD
SWITCHES

J
1

I

11987654321

Y, Y'l YSY4 Ys Ys Y7 YB Y9

,

1
1

OUTPUT DATA
BUFFER

'11

o::D

'en~"

1

HUtttt"

ANY KEY
DOWN (OPTION)

--

TTL
COMPATIBLE
OUTPUT DRIVERS

--------11
BlO~B8B7B6B5B483B2Bl

.. Not Available on KR9600

~

3
X4
5
X6
X7
X8

34

(10 x 90 x 4)
BITS KEYS MODES

i:

X1 '"

39
38
37
36
35

9
STAGE
RING
COUNTER

»

xo

140

GND

CAPS
LOCK

'c"

-=-

~

~

I

III

5n

IDELAY

1

I J..,
291

N

. C··

IGND

1 I

SHIFT
CONTROL

0

I'

II
GNDI

~
o

~T"

t---+-=c.>

I

CONT

ARD
ARO
RR1
16 DATA
READY
131
STROBE

.J -

11

I

3

I

t;~~

CLOCK
CONTROL

ENCODED
KEY
MEMORY

10 STAGE RING
COUNTER

l2'" r 1 FREQ

GND

1

EXT
CLOCK
1C,' (OPTION)

.

Nc

R, (100K) C, (45 pF) provide approx. 50 KHz Clock Freq .
"C, (300 ns Delay/C ,) R, supplied internally
'''Diodes necessary for complete n Key Rollover operation

,

'::D~"

...o

Yo y, Y" y, Y. y, Y. Y, Y.
L

O~

r-------

"'~~

GND
Vee

1
.7 +

GND

~2+

+5V

V

~

"

v

Y,

~~ :!~~ ~~
~-------------------,

SCALER

1

10 BIT COMPARATOR

--1

I

'f 'f 'f

I

10 STAGE RING
COUNTER

CLOCK
CONTROL

ENCODED
KEY
MEMORY

,! ,! rH

IGND

1)7

~
SHIFT
CONTROL

211
20

11

~

I

1<-";·

CAPS
LOC

==

---'
6?

1

~

U

f:.

I,T
;R'I
c.

9fSn6n4 321

PARALLEL/SERIAL
CONVERTER

____A~~~

"

I'

II

C

~

7

JJ

»

I

"TI

...
X1

START/STOP
PARITY
BIT GEN.

,

I

OJ.

m

"
JJ

CO

en
Yo

!

~ ______
I _______ J

o
I\)

YI Yz Y1 Y4 Ys Yb Y7 VB Y9

,

,
V

90 SPST
KEYBOARD
SWITCHES

I
I

Is

-I

:J:

1

I

oJJ

"*

X2
X3
X4
X5
X6
X7
X8

I

TRANSMITTER

___

s:

xo

I

I

OUTPUT DATA
BUFFER
10

C')

c"

2
1
28
27
26
25
24

HHUH"

Ul

5

IDELAY

GNDI

(10 x 90 x 4)
BITS KEYS MODES

"-

III

STROBE

123

13

9
STAGE
RING
COUNTER

3600 BIT ROM

I

L_~

TIMING
CKT

16X
BRCLK

1

--

IGNDI

J

14

MODE
DECODE _ _

MAIN
CLOCK

rB~"1
t

I

1I

15

i

t

I

I
I

1

SERIAL
OUT

Note: "C, (300 ns Delay/C ,) R, supplied internally
'''Diodes necessary (or complete n Key Rollover operation

DESCRIPTION OF PIN FUNCTIONS
KR9600
PIN#

KR9601
PIN#

KR9602
PIN#

XO-X8

40-32

40-32

4-1
28-24

YO-Y9

17-26

17-26

9-18

1

5

NAME
X OUTPUTS
Y INPUTS
~XTERNAL

CLOCK

SYMBOL

...

1

SERIAL CLOCK

...

DATA OUTPUTS

B8-B1

DATA READY

DR

16

16

N/A

DELAY NODE
INPUT

DELAY

31

31

23

SHIFT INPUT

SHIFT

29

29

21

CONTROL INPUT

CNTRL

28

28

20

CAPS LOCK

CAPS

see
note

27

19

POWER SUPPLY
GROUND

Vee
Gnd

30
30
15
15
see
OPTION PINS
1-6
note
Note: Caps Lock and Auto-Repeat are not available on KR9600.
See option 8.election table for pin assignment.

22
7

see note)

...

...

7-14

7-14

8

DESCRIPTION OF OPERATION
The main clocks for the KR9600 and KR9601 are derived
from either an external clock source or the fnternal oscillator. The KR9q02 requires an external clock. The external clock is routed to a divider with a mask programmable
division rate from 1 to 63 to generate the internal clock.
The keys are scanned in a nine output by ten input matrix,
each key having a unique input-output combination connected to it. The inputs all QO selectively to a level detector which has logically variable (1 's and O's) levels and
hysteresis. The outputs are enabled one at a time from
output XO towards X8, at a rate of 10-1 OOKHz, through a
9 stage ring counter. The 10 inputs are searched one at
a time from YO to Y9, through a 10 stage ring counter,
each time one of the outputs is enabled. The output and
input pins all have pullups to Vee and are precharged each
clock even if the scan is stopped at one key. When a level
on the selected path to the comparator matches a level
on the corresponding comparator input from the 10 stage
ring counter and the key has not been encoded, the switch
bounce delay network is enabled. The key down stroke
is examined, without advance to the next key location,
until the key has been stable for the length of the DELAY
CAP pin to discharge. The code for the depressed key is
transferred to the output data buffer and the data ready
signal appears.

6

N/A

FUNCTION
External outputs from the 9-sta~ ring
counter to the keyboard to form -Y
matrix with the keyboard switches as
the crosspoints.
External inputs from the keyboard X-V
matrix.
External clock input.
Serial input Baud rate clock, for
KR9602.
Data outputs B1-B8. Parallel outputs
for the KR9600/9601 , serial output for
theKR9602.
This output, which can be a level or a
~ulse, signals that a key closure has
een detected and that data is
available at the output port.
Externally controllable delay network
for eliminating the effect of switch
contact bounce.
This input is used to select the shift
mode data.
This input is used to select the control
mode data. Simultaneous assertion of
shift and control inputs will place the
encoder into the shift-control mode.
This input "ANDed" with bit B9 of the
ROM will cause a mode shift. See
"programming options".
+ 5V power supply.
Ground.
See option selection table for pin
asslgnment.

The scan has two modes as determined by the LOckout/
Rollover option. Once a key is determined to be down the
scan will not advance if in the LOckout mode. Consequently a new key closure is not detected until the previously depressed key is released. The scan sequence,
will resume upon key release and tI~e output data buffer
stores the code of the last key encoded: ,In the Rollover
mode a "1" is stored in the encoded key memory and the
scan sequence is resumed and the code for the last
encoded key remains in the data output buffer. Each
depressed key is encoded regardless of the state of the
previously depressed keys. The internal keyboard ROM
is 10 bits wide. Bits 1-8 are output via data outputs B1B8. Bits 9 and 10 may be output as data and/or utilized
respectively for Caps-lock and Auto-repeat select. This
allows mask programmable selection of which keys will
have caps-lock and auto-repeat. When selected, the auto
repeat will commence with a "long" delay after key
depression followed by "short" delays. The duration of
the delays varying with the clock frequency and the state
of the ARD, ARO, and AR1 signals.
A Chip Enable input is available to enable the parallel
output buffer. Data Ready can be put in the high-impedance state with Chip Enable (CE) or can be open drain
as a mask programmable option to facilitate wire-oring
as an interrupt.
742

In the serial output version of KR9602, when a key is
debounced and then called valid, the serial shift register
is loaded with the data (8 bits B1-B8) from the ROM, the
data from the parity generator, and the data from the start
and stop bits generator. Bits B9 and B10 are internally
used respectively'for Caps-lock and Auto-repeat select.
The data register is then allowed to shift data out at the
rate of one bit per 16 clocks of the baud rateclock.pin, on
the negative edge of that clock. If the baud rate clock is
too slow with respect to the internal clock, and the keyboard were allowed to continue scanning when the data
register is loaded, then new data could be loaded on top
of shifting-out data.
To avoid this, if a new key is depressed before the previous data is fully shifted out of the device, including the
stop bits, the delay cap will be allowed to decay but the
internal logic will delay its effect until the shift out of the
previous data is completed. If the new key is released
before the end of the extended delay time it will not be
encoded.

PIN
1
1
2
2
3
3
4
4
5

5
6

FUNCTION in ut unless noted
Ext clock (opt. internal divisor of 1-63)**
Pin 1 of Internal oscillator.
Pin 2 of Internal oscillator.
LolRo CC CE ARD** ARO** AR1**
Pin 3 of Internal oscillator.
LolRo CC CE ARD** ARO** AR1**
AKa output
LolRo CC CE ARD** ARO** AR1**
AKa or B10 output
LolRo CC CE ARD** ARO** AR1**
B9 or AKO** output

Options Available for the KR9602:
The following options can be obtained on the KR9602
only with a mask program, and are not pin selectable:
LoIRo, CC, AUTO-REPEAT, LONG
DELAY, SHORT DELAY,
CLOCK DIVISOR 1,2,4,8,16,32,63; PARITY,
1 OR 2 STOP BITS.

Legend
OPTION SELECTION TABLE
Since the selected coding of each key and all the options
are defined during the manufacture of the chip, the coding and options can be changed to fit any particular
application of the keyboard. Up to 360 codes of up to ten
bits can be programmed into the KR9600/KR9601 ROM
covering most popular codes such as ASCII, EBCDIC,
SELECTRIC etc. as well as many specialized codes:

Pin Assignment for KR9600/KR9601
The chip pins from pin #1 thru pin #6 are optionally connected to differing logic functions. Many of the functions
are available on more than one pin.

PROGRAMMING OPTIONS
The various options on the KR9600 and KR9601 are user
selectable via externally programmable pins, but they are
fixed, internally mask programmed, for fhe KR9602.

Oscillator:
The main clocks are derived from either an external clock
source or from the Internal oscillator. The resultant signal is then routed to a divider with a mask programmable
division rate from 2 to 63. If no division is required then
the divider is bypassed. The external clock requires one
pin (pin #1), while the Internal oscillator needs three pins
(pins #1, 2, 3) for frequency selection via an external
resistor and capacitor.

Lockout/Roliover: LO/RO
This option selects the operation of the key scan when a
new key is detected. In Lockout the scan stops as long
as the key is down. In Rollover the scan stops till the new
key is debounced by the DELAY CAP and the key code
is output. Then the key position is marked as down and
the scan continues until another new key is seen. The
option is selected either by an external pin or internally
mask programmed, fixed in either state. The external
LOckout selection is optionally hi or low active. A pulldown resistor to ground is optional.

Complement Control: CC

CC = COMPLEMENT
AKO = ANY KEY DOWN
CONTROL
CE = CHIP ENABLE
Lo/Ro = LOCKOUTI
B10 = B10 (DATA)
ROLLOVER
OUTPUT
B9 = B9 (DATA) OUTPUT
INTERNAL CLOCK = SELF CONTAINED OSCILLATOR
(Not available in KR9602)
EXTERNAL CLOCK = EXTERNAL FREQUENCY
SOURCE
ARD = INITIAL AUTO-REPEAT DELAY
ARO, AR1 = SECONDARY AUTO-REPEAT DELAY, OR
NO AUTO-REPEAT WHEN BOTH ARE FALSE.

*Contact local sales office for custom coding sheet.
**Not available on the KR9600.
PUTS and can optionally additionally invert the logic true
state of the DATA READY pin. The option can be internally fixed as true or false where true will output a high
logic level. When externally selected the option can be
either input high or low active true. The pulldown to
,ground is optional.

Data Ready:
The data ready pin is optionally either a pulse or level
upon an output state ready to transfer. This transfer
occurs when a new key is encoded or when the current
key is repeating via the repeat logic. This output is individually capable of being disabled via CE or inverted via
CC. To invert DATA READY is to have the pulse go logic
low or the level fall to logic low active when the output is
allowed to drive out of the chip.

Any Key Down: AKO output
The AKa output is an indicator to tell that there is at least
one key determined to be depressed. The output is
optionally logic high or low true. The CE can be separately used to set the output in the high impedance mode.
AKa will reset one full keyboard scan time after the last
key is released. AKa cannot be inv~rted by CC (complement control).

,

Chip Enable: CE

This option inverts the logic true state of the DATA OUT-

The chip enable option can be internally fixed to true or

743

can be externally selected. When an external pin is used
the true level is only low true. The true state means that
the outputs connected to CE will go to the driven state
from the high-impedance condition. Output pins 81-810
are always affected by Chip Enable (CE), optional for
Data Ready and Any Key Down. A pulldown to ground is
optional.

consist of a programmable num.ber of scan frequency
time clocks varying from 2 to 131071 clock times.
This option is masked programmable and dependent on
the programming ofthe data bit 10 ofthe ten data outputs
to be true for the resultant key code (after lock logic) and
upon whether any repeat action should occur at all.
There are three optional pins associated with the auto
repeat logic: ARO, AR1, and ARD. Each of these can
individually optionally have a pulldown resistor to ground.
ARD controls the selection of the initial repeat delay count
code, while the combination of ARO and AR1 controls
the selection of the short delays as shown below. If no
external pins are desired then those functions can be
mask programmed.

Shift Control Lock: S C L
These three pins determine what will be output in
response to a new key being detected. The Caps Lock
pin is optional on the KR9601 and KR9602 but it is not
available on the KR9600. All three pins have optional
p'ulldown resistors to ground. The Lock option is allowed
If data bit nine of the ten data bits is programmed as true.
In other words the Rom is read with no lock logic allowed,
but with the full influence of the Shift and Control pins.
This determines the 89 output which is used to see if this
key can be shifted (be it a control code or not) by modifying the effect of the Shift upon a second read of the
rom. The operation ofthe allowed Lock follows this table:
L
F
F
F
F

69
F
F
F
F

S
F
F
T
T

C Result
F
N
T
C
F
S
T
SC

F
F
F
F

T
T
T
T

F
F
T
T

F
T
F
T

N
C
S
SC

T
T
T
T

F
F
F
F

F
F
T
T

F
T
F
T

N
C
S
SC

T

T

F

F

T
T

T
T

F
T

T
F

T

T

T

T

S

TYPICAL INITIAL REPEAT DELAY COUNTS
ARD = hi 80000 clock times
ARD = low 40000 clock times
The repeat delays are selected by a two bit code where
one decode is used to disable the repeat operation
completely.

L = CAPS LOCK
69 = DATA OUTPUT 69
N = NORMAL
S = SHIFT
C = CONTROL
SC = SHIFT and CONTROL

TYPICAL SECONDARY REPEAT COUNTS
ARO AR1 Count
o
0 All Auto-Repeat Disabled
o
1 6250
1
0 3125
1
1 1250
Typical Example:
One typical approach would be to mask program ARD
for only one long delay value and mask ARO to ground.
This way one can save two option pins for ARD and ARO
and still be able to select or disable auto-repeat via AR1
and have the option of having one fixed short delay value.

ForceN->S

allow shift
(iem->M)
ForceC->SC
shift of Control
Opt Force S->N allow reverse
(ieM->m)
'SC/C Opt Force
remove shift in
SC->C
Shift-Control
SC
'SIN

ROM Data:
The actual programming data is in 10 bit wide characters
with four function codes for each key position. There are
90 key positions organized as 9 "X" outputs with 10 "Y"
inputs. The four functions as previously defined are Control, Shift, Normal, and Shift-Control.
The use of the optional Lock requires the programming
of the 89 data bit. The use of the optional Auto-Repeat
requires the programming of the 810 data bit. If the 89
or 810 outputs are used then these will show the result
of the contents of the "corrected" key function data bits.
The "corrected" function is the possibly changed Normal to Shift etc. etc. so that the output is that of the 'Shifted
key code' NOT that of the initial key code.

'The mask programmable option for the removal of the shift is
coded as either ON for all keys or OFF. Note that the 69 DATA
output (and all the others) is the code olthe second decode. Note
that shift only occurs when both the lock is true and the unmodified code gives a 69 ROM output as true.

Repeat: ARD ARO AR1
When the Auto-repeat option is selected and a key is
pressed, either of two delays can be selected. Typically
a long initial delay after the key is pressed, and short
delays afterwards ifthe key is still pressed. These delays

Minimum Switch CI.osure:
T = Switch bounce

I

maximum
expected

+ (90 x 1/f) + Strobe delay + Strobe width

I

determined
by frequency
of operation

I

determined
by external
capacitance

I

minimum time
required by
external circuitry

744

CONDITIONS:
The clock divider is 1 so that elkl is "same as clock IN",
A key is pressed down at XOYO but the delay cap has not timed out.
Data Ready is high true and we have already had another key,
DataRP = Data Ready as a Pulse
DataRL = Data Ready as a Level
Clkl

xq
X1

X2

I

------------~i~~--~~~'~~--------------------I

I

I

I
I

I

Delay Cap

L-J

I
I

I

DataRP

I

I

--------~~~ll~---------------I

DataRL

81-810

_____________ }c-------------------------

Condition: Test mode autorepeat at divide by 4 and keep key down
Clkl

Xo
I

X1

I

:

I

----------+:4-~~~~
I

X2

I

:

------------~I~--+-~--~I~

I

I

II

I
I

I

I

I
I

DelayCap

DataRP

DataRL

81-810

745

ELECTRICAL CHARACTERISTICS: KR9600, KR9601, KR9602
MAXIMUM GUARANTEED RATINGS
Operating Temperature Range~' ....................................................................... O°C to + 70°C
Storage Temperature Range ................ , ..................................................... - 55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ....................................................................... +325°C
Positive Voltage on any Pin, with respect to ground ........................................................... + 8.0V
Negative Voltage on any Pin, with respect to ground .......................................................... - 0.3V

ELECTRICAL CHARACTERISTICS (TA = O°C to 70°C, Vcc = + 5V ± 5%, unless otherwise noted)
PARAMETER
D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low Level
High Level
YINPUTS
High Level
Low Level
INPUT CURRENT
Leakage
Input with Pull-down resistor
selected as option
Yinputs
OUTPUT VOLTAGE LEVELS
Low Level
High Level
X output voltage
TRI-STATE LEAKAGE
INPUT CAPACITANCE
All inputs
POWER SUPPLY CURRENT

A.C. CHARACTERISTICS
CLOCK FREQUENCY'
16X CLOCK FREQUENCY
Chip enable access time
SWITCH CHARACTERISTICS
Min switch closure
Contact closure resistance

SYMBOL
VIL
VIH
VYIH
VYIL

MIN

TYP

UNIT

COMMENTS

0.8

V
V
V

All inputs
Except Y + 16X CLK
16X CLK only

0.8

V
V

Yinput
Yinput

10.0

IIA

All inputs except Y
VIN = 5V

220
-500

floA
floA

VIN = 5V
VYIL = 1 volt
Y inputs only

0.4

V
V

2.0
2.2
2.8

IL

IY'L

75
-100

VOL
VOH

2.4

VOL
VOH

3.4

CIN
Icc
Icc
FIN

MAX

-400

TCE

floA

10
40
35

pF
rnA
rnA

Except Y inputs
KR9600/01
KR9602

4
0.1
640
250

MHz
MHz
KHz
ns

KR9601/02
KR9600
KR9602

0.4
4.0

20
15
0.01
0.01
DC

10

IOL = 1.6 rnA
IOH = 100 floA
Except X outputs
6OOfloA
clock high
IOH =10floA
81-810

V
V

see timing
diagram
Zcc
Zoc

300

ohms

1 x 107

NOTE: The KR9600 is a direct replacement for the KR3600. Please note that due to the logic level of the KR9600, when
replacing the KR3600 in a N-Key rollover system where diodes are utilized, the polarity of the diodes must be
reversed .
• Divisor on KR9601/02 must be selected such that the resulting internal scan frequency is 10 KHz min to 100 KHz max .
•• Parts optionally available in extended temperature ranges in hermetic packages. Inquire at factory.

746

Bits 2 and 3 indicate the mode as follows:

KR9600-PRO DESCRIPTION
The KR9600 PRO is a MaS/LSI device intended to simplify the interface of a microprocessor to a keyboard
matrix. Like the other KR9600 parts, the KR9600 PRO
contains all of the logic to de-bounce and encode keyswitch closures, while providing either a 2-key or N-key
rollover.
The output of the KR9600 PRO is a simple binary code
which may be converted to a standard information code
by a PROM or directly by a microprocessor. This permits
a user maximum flexibility of key layout with simple field
programming.
The code in the KR9600 is shown in Table I. The format
is simple: output bits, 9, 8, 7, 6, 5,4 and 1 are a binary
sequence. The count starts at XO, YO and increments
through XOY1, XOY2 ... X8Y9. Bit 9 is the LSB; bit 1 is the
MSB.

Bit2

o
o

30

Rollover

+5......../___ 4
Lockout X0

0

Normal
Shift
Control
1
0
1
1
Shift Control
For maximum ease of use and flexibility, an internal
scanning oscillator is used, with pin selection of N-key
lockout (also known as 2-key rollover) and N-key rollover.
An "any-key-down" output is provided for such uses as
repeat oscillator keying.
Figure 1 shows a PROM-encoded 64 key, 4 mode application, using a 256 x 8 PROM, and Figure 2 a full 90 key,
4 mode application utilizing a 512 x 8 PROM.
If N-key rollover operation is desired, it is recommended
that a diode be inserted in series with each switch as
shown. This prevents "phantom" key closures from
resulting if three or more keys are depressed
simultaneously.

FIGURE 1
KR9600 PRO TYPICAL APPLICATION
64 KEY, 4 MODE

+5

Bit3
1

FIGURE 2
KR9600 PRO TYPICAL APPLICATION
90 KEY, 4 MODE

NC

'5

",

Any Key Down

"

:~

40

X139
)1.2 38
X3 37

X5 35

"38

~

X3 37
X436

;---E 320,4 .!!...-NC

g:

12 83
11

Y3 20

10 B5

!

~

f\.

g86

""

Iyp'(l.llwll<:h
(2-keyroIlOYflr)

, , ,

17f

8~

~

VI

11~
12~
13~

shift

;

Y2

,9

Y3

ao

!

Y42'~

14f!!L..

13 B2
12 83

$"

VS 22
VB 23

Y7 24

B4

10 B5

.,"...,.,
,
a

c.

IN·~eyroliover)

1

,

,,

f\.

~~~rE
tYPical SWitch
~2·keyrDllo ...r)

, , ,

1-

control

747

,"
.," , " Sa...
7.2!....,..

.

"3

alL.

" 1 92L.
"', , I,.!!!....,..
""

"'6 16

•~ 12.2!......
13~

",7 17

14.Q.!.....,.

AB 16

ISle

VB 25

typical SWitch

I

3 2 0 , 4 81

" ,BC

,i2i-

g

1518

~~re

~

7r-+-

,

AS"
"'1'9

6

Y8 2S

,
.," ,

"'. ,
"',

a

Y7 24

,,

~ ~
02

~33

1~2'o6~

"3 M

, ""
"

VB 23

,

B2

Y219~

V5 al

IYPIC:.IBW!lch
(N·keyrallover)

13

VItae

Y4 21

"

X5 35

DalaAeady

X8 34

~33
17

Any key Down

';~
""

X139

~

"',.
"

",

Loclloul )1,040

02

"

x. "

30

Rollover

+5......../____ 4

OataRa&Oy

NC

L

C.

TABLE 1
KR9600-PRO CODING SHEET AND OPTIONS
XV
00
01
0'
03
04
05
06
07
06
09
10
11

,."
,.
13
14
16
17
18

20
21

"

23
24
25

'6
27

"

2'
30
31
32
33
34
35
35
37
38
39
40
41
42
43
44

45
46
47
48
49
50
51

"

53
54
55
56
57

58
5.
60
51
62
63
64
65
86
67

66
8.
70
71

72
73
74
75

76
77

78
7.
80
81
82
83
64
85
86
87
88
89

Normal
8·12345676910
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001000
000001001
000001010
000001011
000001100
000001101
000001110
000001111
000010000
000010001
000010010
000010011
000010100
000010101
000010110
000010111
000011000
000011001
000011010
000011011
000011100
000011101
000011110
000011111
000100000
000100001
000100010
000100011
000100100
000100101
000100110
000100111
000101000
000101001
000101010
000101011
000101100
000101101
000101110
000101111
000110000
000110001
000110010
000110011
000110100
000110101
000110110
000110111
000111000
000111001
000111010
000111011
000111100
000111101
000111110
000111111
100000000
100000001
100000010
100000011
100000100
100000101
100000110
100000111
100001000
100001001
100001010
100001011
100001100
100001101
100001110
100001111
100010000
100010001
100010010
100010011
100010100
100010101
100010110
100010111
100011000
100011001

OPTIONS:
Internal Oscillator (Pins 1, 2, 3)
Lockout/Rollover (Pin 4)
Internal Resistor to GND
Lockout is LogiC 1

Shift

Control

Shirt/Control

001000000
001000001
001000010
00100001'
001000100
001000101

8·12345678910
010000000
010000001
010000010
010000011
010000100
010000101

OO~OOO110

010000',0

001000111
001001000
001001001
001001010
001001011
001001100
001001101
001001110
001001111
001010000
001010001
001010010
001010011
001010100
001010101
001010110
001010111
001011000
001011001
001011010
001011011
001011100
001011101
001011110
001011111
001100000
001100001
001100010
001100011
001100100
001100101
001100110
001100111
001101000
001101001
001101010
001101011
001101100
001101101
001101110
001101111
001110000
001110001
001110010
001110011
001110100
001110101
001110110
00111011'
001111000
001111001
001111010
001111011
001111100
001111101
001111110
001111111
101000000
101000001
101000010
101000011
101000100
101000101
101000110
101000111
101001000
101001001
101001010
101001011
101001100
101001101
101001110
101001111
101010000
101010001
101010010
101010011
101010100
101010'101
101010110
101010111
101011000
101011001

010000111
010001000
010001001
010001010
010001011
010001100
010001101
010001110
010001111
010010000
010010001
010010010
010010011
010010100
010010101
010010110
010010111
010011000
010011001
010011010
010011011
010011100
010011101
010011110
010011111
010100000
010100001
010100010
010100011
010100100
010100101
010100110
010100111
010101000
010101001
010101010
010101011
010101100
010101101
010101110
010101111
010110000
010110001
010110010
010110011
010110100
010110101
010110110
010110111
010111000
010111001
010111010
010111011
010111100
010111101
010111110
010111111
110000000
110000001
110000010
110000011
110000100
110000101
110000110
110000111
110001000
110001001
110001010
110001011
110001100
110001101
110001110
110001111
110010000
110010001
110010010
110010011
110010100
110010101
110010110
110010111
110011000
110011001

11-12345678910
011000000
011000001
011000010
011000011
011000100
011000101
011000110
011000111
011001000
011001001
011001010
011001011
011001100
011001101

11-12345678910

011001110

011001111
011010000
011010001
011010010
011010011
011010100
011010101
011010110
011010111
011011000
011011001
011011010
011011011
011011100
011011101
011011110
011011111
011100000
011100001
011100010
011100011
011100100
011100101
011100110
011100111
011101000
011101001
011101010
011101011
011101100
011101101
011101110
011101111
01H1QOOO
011110001
011110010
011110011
011110100
011110101
011110110
011110111
011111000
011111001
011111010
011111011
011111100
011111101
011111110
011111111
111000000
111000001
111000010
111000011
111000100
111000101
111000110
111000111
111001000
111001001
111001010
111001011
111001100
111001101
111001110
111001111
111010000
111010001
111010010
111010011
111010100
111010101
111010110
111010111
111011000
111011001

Pulse Data Ready
Any Key Down (Pin 5) Positive Output
Internal Resistor to GND on Shift
and Control Pins

748

CODING FOR KR9600-STD
XV
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16

17
18
19
20
21
22
23
24
25
26
27
28
2.
30
31
32
33
34
35
36
37

38
3.

40
41
42
43

44
45
46
47
48
49

50
51
52
53
54
55
56
57
58
59
60
61
62
63

64
65
66
67

.8
69
70
71
72
73
74
75
76

77
78
79
80

81
82
83

64
85
86
87
88
8S

Normal
8-12345678910
1

1000111001

q 1000110101

a
z

1000010101
0101110101

HT 1001000001
H 0001000101
+ 1101011001
SO 0111001001
P 0000110101
1 1000111001
2 0100111001
w 1110110101
s 1100110101
x 0001110101
RS 0111100001
% 1010011001
m 1011010101
SI 1111000001
n 0111010101
2 0100111001
3 1100111001
1010010101
d 0010010101
c 1100010101
- 1111100100
$ 0010011001
L 0011000101
US 1111100001
6 0110111001
k 1101010101
4 0010111001
0100110101
1 0110010101
SP 0000011000
CAN 0001101000
CR 1011000001
1101111101
1101000000
7 1110111001
0100011001
5 1010111001
1 0010110101
1110010101
0110110101
ETX 1100000001
1011111101
1111111001
- 1011011001
1001011001
0000011001
6 0110111001
1001110101
0001010101
b 0100010101
0101111001
> 0111111001
1101111001
NU~ 0000000001
0101011001
! 1000011001
7 1110111001
1010110101
0101010101
0111010101
1011111000
< 0011111001
P 0000110101
0 0000111001
& 0110011001
# 1100011001
8 0001111001
; 1001010101
k 1101010101
m 1011010101
I 1111011001
1110011001
LF 0101000000
1011111001
FF 0011001001
( 0001011001
1001111001
0 1111010101
I 0011010101
0011011001
0111011001
1101111001
1011100101
1011011001
0 0000111001
9 1001111001

.
,

vt

e

1

S~

~

"~

~

~

•
i

OPTIONS:
Internal Oscillator (Pins 1, 2, 3)
Any Key Down (Pin 4) Positive Output
.N-Key Rollover only
Pulse Data Ready signal

Shift

Control

8-12345678910

8-12345678910

<
Q

0011111001
1000100101

A

1000000101

Z 0101100101
HT 1001000001
H 0001000101
+ 1101011001
> 0111111001
@, 0000000101
1000011001
@ 0000000101
W 1110100101
S 1100100101
X 0001100101
RS 0111100001
% 1010011001
1011100101
1111000001
0111100101
0100011001
# 1100011001
E 1010000101
D 0010000101
C 1100000101
1111100100
$ 0010011001
L 0011000101
US 1111100001
& 0110011001
[ 1101100101
$ 0010011001
R 0100100101
F 0110000101
SP 0000011000
( 0001011000
CR 1011000001
1101111101
1101000000
1110011001
0100011001
% 1010011001
T 0010100101
1110000101
0110100101
ETX 1100000001
I 1011111101
? 1111111001
- 1011111001
) 1001011001
SP 0000011001
> 0111111001
V 1001100101
H 0001000101
~ 0100000101
0101011001
> 0111111001
+ 1101011001
NU~ 0000000001
0101011001
1000011001
& 0110011001
U 1010100101
J 0101000101
N 0111000101
1011111000
< 0011111001
P 0000100101
) 1001011001
& 0110011001
1100011001
~ 0101011001
I 1001000101
K 1101000101
M 1011000101
? 1111111001
0100011001
LF 0101000000
+ 1101011001
< 0011111001
( 0001011001
0001011001
1111000101
L 0011000101
0011011001
0111011001
0101111001
1101100101
1111100101
0 0000111001
) 1001011001

sl

-

vt
~

,

~

d

-i

1

1000111011
q 1000111111
a 1000011111
z 0101111111
HT 1001000001
H 0001000101
+ 1101011001
SO 0111000001
NUL 0000000001
SOH 1000000001
2 0100111011
w 1110111111
s 1100111111
x 0001111111
RS 0111100001
% 1010011001
CR 1011000001
SI 1111000001
SO 0111000001
STX 0100000001
3 1100111011
1010011111
d 0010011111
c 1100011111
- 1111100100
$ 0010011001
L 0011000101
US 1111100001
ACK 0110000001
DEL 1111111101
4 0010111011
0100111111
f 0110011111
SP 0000011000
CAN 0001100000
CR 1011000001
1101111111
1101000000
BE~ 1110000001
0100011001
5 1010111011
I 0010111111
G 1110011111
0110111111
ED< 1100000001
1011111111
1111111011
- 1011011001
1001011001
0000011001
6 0110111011
1001111111
0001011111
b 0100011111
0101111011
> 0111111011
1101111011
NU~ 0000000001
0101011001
! 1000011001
7 1110111011
1010111111
0101011111
0111011111
1011111010
< 0011111011
P 0000111111
0 0000111011
& 0110011001
# 1100011001
8 0001111011
; 1001011111
k 1101011111
m 1011011111
1111011001
1110011001
LF 0101000000
1011111001
FF 0011000001
( 0001011001
9 1001111011
0 1111011111
I 0011011111
0011011001
0111011001
1101111001
1011100101
1011011001
0000111001
0
HT 1001000001

.
,

vt

,

1

S~

~

"~

~

:

~

i

Shift Control
8-12345678910
SUB
DLE
@
P
I
H

01.D1100001

0000100001
0000000101
0000100101
1001000101

0001000111
+ 1101011011
SO 0111000011
NUL 0000000001
SOH 1000000001
ETB 1110100001
0011100101
A 1000000101
Q 1000100101
FS 0011100001
% 1010011011
CR 1011000001
SI 1111000011
SO 0111000001
STX 0100000001
NAK 1010100001
DC3 1100100001
B 0100000101
R 0100100101
0111100100
$ 0010011011
L 0011000111
US 1111100011
ACK 0110000001
DEL 1111111101
DC4 0010100001
ENQ 1010000001
C 1100000101
SP 0000011000
BS 0001000000
M 1011000101
K 1101000101
VT 1101000010
BE~ 1110000001
0100011011
STX 0100000001
EaT 0010000001
D 0010000101
S 1100100101
ETX 1100000001
N 0111000101
[ 1101100101
- 1011011011
1001011011
0000011011
SOH 1000000001
DC1 1000100001
E 1010000101
T 0010100101
SYN 0110100001
Z 0101100101
Y 1001100101
NUL 0000000001
0101011011
! 1000011011
ETX 1100000001
BEL 1110000001
F 0110000101
U 1010100101
0111111100
W 1110100101
J 0101000101
DC2 0100100001
& 0110011011
# 1100011011
ESC 1101100001
ACK 0110000001
G 1110000101
~ 0110100101
1110011001
0100011001
GS 1011100000
+ 1101011001
FF 0011000011
( 0001011011
EM 1001100001
1011100101
0001100101
0011011011
0111011011
0101111001
1101100101
- 1111100101
0000111001
0
HT 1001000001

S~

~

~

i

Internal Resistor to GND on Shift and
Control Pins
KR9600-STD outputs provides ASCII
bits 1-6 on 81-86, and bit 7 on 88

749

CODING FOR KR9601 AND KR9602 STD

XV
00
01
02
03
04
05
06
07
0.
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
5.
59
60
61
62
63
64
65
66
67
6.
69
70
71

72
73
74
75
76
77
78
79
.0
81
82
83
84
85
86
87
88
89

Normal
8·12345678910
0000000100

0000001001
0000001101
0000010001

0000010101
0000011001
0000011101

0000100001
0000100001
0000100101
0000101001
0000101101
00001 lOa 01
0000110001
0000110101
0000111001
000U1111 01
0001000001
0001000101
0001001001
0001001111
0001010011
0001010111
0001011011
0001011111
0001100011
0001100111
0001101011
0001101111
0001110011
0001110101
0001111001
0001111101
0001111101
001000QOOl
0010000101
0010001001
0010001101
0010010001
0010010101
0010011011
0010011111
0010100011
0010100111
0010101011
0010101111
0010110011
0010110111
0010111011
0010111011
0010111101
0011000001
0011000101
0011000101
0011001001
0011001101
0011010001
0011010100
0011011001
0011011101
0011100011
0011100111
0011101011
0011101111
0011110011
0011110111
0011111011
0011111111
0011111111
0011111111
0100000001
0100000101
0100001001
0100001101
0100010001
0100010101
01000110 01
0100011101
0100100001
0100100101
0100101001
0100101101
0100110001
0100110101
0100111001
0100111101
0101000001
0101000101
0101001001
0101001101

Shift
8-12345678.910
0101010100
0101011001
0101011101
0101100001
0101100; 01
0101101001
0101101101
0101110001
0101110001
0101110101
0101111001
0101'11101
0110000001
0110000001
0110000101
0110001001
0110001101
0110010001
0110010101
0110011001
0110011111
0110100011
0110100111
0110101011
0110101111
0110110011
0110110111
0110111011
0110111111
0111000011
0111000101
0111001001
0111001101
0111001101
0111010001
0111010101
0111011001
0111011101
0111100001
0111100101
0111101011
0111101111
0111110011
0111110111
0111111011
0111111111
1000000011
1000000111
1000001011
1000001011
1000001101
1000010001
1000010101
1000010101
1000011001
1000011101
1000100001
1000100100
1000101001
1000101101
1000110011
10001101 11
1000111011
1000111111
1001000011
1001000111
1001001011
1001001111
1001001111
1001001111
1001010001
1001010101
1001011001
1001011101
1001100001
1001100101
1001101001
1001101101
1001110001
1001110101
1001111001
1001111101
1010000001
1010000101
1010001001
1010001101
1010010001
1010010101
1010011001
1010011101

OPTIONS FOR THE KR9601·STD:
PINS 1,2, 3
INTERNAL OSCILLATOR [Input clock divisor = 1]
PIN 4
CE [Active Low]
PIN 5
AR 1 [ARO fixed at Lo = 0]
[FIXED LONG DELAY OF 40000 CLOCK TIMES]
[FIXED SHORT DELAY OF 6250 CLOCK TIMES]
AKO [positive true]
PIN 6
Pulsed DATA READY signal
N-KEY ROLLOVER
Pull-down resistor to ground at the following pins:
_SHIFT
_CONTROL
_CAPS-LOCK
_ARO

750

Control
8-12345678910

Shift/Control

8·12345678910

1010100100

10101001 DO

1010101001
1010101101
10101'0001
1010110101
10101'1001
1010111101
1011000001
1011000001
1011000101
1011001001
1011001101
1011010001
1011010001
1011010101
1011011001
1011011101
1011100001
1011100101
1011101001
1011101111
1011110011
1011110111
1011111011
1011111111
1100000011
1100000111
1100001011
1100001111
1100010011
1100010101
1100011001
1100011101
1100011101
1100100001
1100100101
1100101001
1100101101
1100110001
1100110101
1100111011
1100111111
1101000011
1101000111
1101001011
1101001111
1101010011
1101010111
1101011011
1,01011011
1101011101
1101100001
1101100101
1101100101
1101101001
1101101101
1101110001
1101110100
1101111001
1101111101
1110000011
1110000111
1110001011
1110001111
1110010011
1110010111
1110011011
1110011111
1110011111
11100111 11
1110100001
1110100101
1110101001
1110101101
1110110001
1110110101
1110111001
1110111101
1111000001
1111000101
1111001001
1111001101
1111010001
1111010101
1111011001
1111011101
1111000001
1111000101
1111101001
1111101101

1010101001
1010101101
1010110001
1010110101
10101 i 10 01
1010111101
1011000001
1011000001

1011000101
10110010 01
1011001101
1011010001
1011010001
10110101 01
1011011001
1011011101
1011100001
1011100101
1011101001
1011101111
1011110011
1011110111
1011111011
1011111111
1100000011
1100000111
1100001011
1100001111
1100010011
1100010101
1100011001
1100011101
11000111 01
1100100001
1100100101
1100101001
1100101101
1100110001
1100110101
1100111011
1100111111
1101000011
1101000111
1101001011
1101001111
1101010011
1101010111
1101011011
1101011011
1101011101
1101100001
11011001 01
1101100101
1101101001
1101101101
1101110001
1101110100
1101111001
1101111101
1110000011
1110000111
1110001011
1110001111
1110010011
1110010111
1110011011
1110011111
1110011111
1110011111
1110100001
1110100101
1110101001
1110101101
1110110001
1110110101
1110111001
1110111101
1111000001
1111000101
1111001001
1111001101
1111010001
1111010101
1111011001
1111011101
1111100001
1111100101
1111101001
1111101101

OPTIONS FOR THE KR9602-STD:
N-KEY ROLLOVER
AUTO-REPEAT
(FIXED LONG DELAY OF 40000 CLOCK TIMES)
(FIXED SHORT DELAY OF 6250 CLOCK TIMES)
1 STOP bit.
No PARITY bit.
Input clock divisor of 63
Pull-down resistor to ground at the following pins:
-SHIFT
-CONTROL
-CAPS-LOCK

CODING FOR KR9602-012 (ASCII)

XV

00
01
02
03
04
05
06
07
06
09
10
11

12
13
14
15

16
17

18
19
20
21
22
23
24
25
26
27
26
29
30
31
32
33
34
35
36
37
36
39
40
41
42
43
44
45
46
47
46
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71

72
73
74
75

78
77
76
79
80
81
82
83
84
65
86
87
66
69

Normal
8-12345678910
0000110001
1001110001
0001110001
1110110001
0110110001
1010110001
0010110001
1100110001
0100110001
1000110001
0001000001
1010110001
1011010001
1010101001
1101101001
1111011011
1111011011
1001011011
1010111011
1001111011
0010111011
0100111011
1010011011
1110111011
1000111011
1101100000
1001000001
1011000001
0000011001
1110010001
1101110001
0011011011
1101011011
0101011011
0001011011
1110011011
0110011011
0010011011
1100111011
1000011011
1111010001
0111010001
0011010001
1011011011
0111011011
0100011011
0110111011
1100011011
0001100011
0101111011
0011101001
0000010001
1010000001
0110000001
1110000001
1001000001
0101000001
1101000001
0111000001
1111000001
0000100001
1000100001
0100100001
1100100001
0010000001
1010100001
0110100001
1110100001
0001100001
1001100001
0101100001
0011100001
1011100001
0111100001
1111100001
0000000001
1000000001
0100000001
1100000001
0010000001
0000110111
1001110111
1000100011
1110110111
1100100011
1010110111
0100100011
1100110111
0010100011
1000110011

Shift
8-12345678910
1001010001
0001010001
0101010001
0110010001
0111101001
1010010001
0010010001
1100010001
0000001001
1000010001
0001000001
1101010001
1111101001

1010111001
1101111001
0000101011
1111001011
1001001011
1010101011
1001101011
0010101011
0100101011
1010001011
0101001011
1000101011
1101100000
1001000101
1011000001
0111111001
0100010001
0101110001
0011001011
1101001011
0101001011
0001001011
1110001011
0110001011
0010001011
1100101011
1000001011
1111110001
0111110001
0011110001
1011001011
0111001011
0100001011
0110101011
1100001011
0001100011
0101101011
0011111001
0000010001
1010000001
0110000001
1110000001
1001000001
0101000001
1101000001
0111000001
1111000001

~ggg~gggg~

0100100001
1100100001
0010000001
1010100001
0110100001
1110100001
0001100001
1001100001
0101100001
0011100001
1011100001
0111100001
1111100001
0000000001
1000000001
0100000001
1100000001
0010000001
0000110011
1001110011
0001110011
1110110011
0110110011
1010110011
0010110011
1100110011
0100110011
1000110011

OPTIONS FOR THE KR9602-012 ASCII:
Lockout
Auto Repeat
(Fixed Long Delay of 60,000 Clock Times)
(Fixed Short Delay of 2000 Clock Times)
One Stop Bit
Input Clock Divisor of 32

Control
8-12345678910
0000110001
1001110001
0001110001
1110110001
0110110001
1010110001
0010110001
1100110001
0100110001
1000110001
0001000001
1011110001
1111100001
1011100001
1101100000
0000100011
1111000011
1001000011
1010100011
1001100011
0010100011
0100100011
1010000011
1110100011
1000100011
1101100000
1001000001
1011000001
0000011001
1110010001
1101110001
0011000011
1101000011
0101000011
0001000011
1110000011
0110000011
0010000011
1100100011
1000000011
1111010001
0111010001
0011010001
1011000011
0111000011
0100000011
0110100101
1110100101
0001100101
0101100011
0011100001
0000010001
1010000101
0110000101
1110000101
1001000101
0101000101
1101000101
0111000101
1111000101
0000100101
1000100101
0100100101
1100100101
0010000101
1010100101
0110100101
1110100101
0001100101
1001100101
0101100101
0011100101
1011100101
0111100101
1111100101
0000000101
1000000101
0100000101
1100000101
00tOOO0101
0000110111
1001110111
1000100011
1110110111
1100100011
1010110111
0100100011
1100110111
0010100011
1000110111

Shift Control
8·12345678910
1001010001
0001010001
0101010001
0110010001
0111101001
1010010001
0010010001
1100010001
0000001001
1000010001
0001000001
1101010001
1111100101
1010100101
1101100100
0000100111
1111000111
1001000111
1010100111
1001100111
0010100111
0100100111
1010000111
1110100111
1000100111
1101100000
1001000101
1011000001
0111111001
0100010001
0101110001
0011000111
1101000111
0101000111
0001000111
1110000111
0110000111
0010000111
1100100111
1000000111
1111110001
0111110001
0011110001
1011100111
0111000111
0100000111
0110100111
1100000111
0001100111
0101100111
0011100101
0000010001
1010000101
0110000101
1110000101
1001000101
0101000101
1101000101
0111000101
1111000101
0000100101
1000100101
0100100101
1100100101
0010000101
1010100101
0110100101
1110100101
0001100101
0001100101
0101100101
0011100101
1011100101
0111100101
1111100101
0000000101
1000000101
0100000101
1100000101
0010000101
0000110011
1001110011
0001110011
1110110011
0110110011
1010110011
0010110011
1100110011
0100110011
1000110011

No Parity
Eight Data Bits
Pull down Resistor to Ground is at the following pins:
-SHIFT
-CONTROL
-CAPS LOCK

751

OSCILLATOR FREQUENCY vs
C1 FOR KR9600/~R9601

STROBE DELAYvs C2 FOR KR9600/1/2

200 r--.-\--.----,--~-_-___,
R = lOOKO

1BO ~-\--'
\I---+~o:"~;f sumY VOLTAGE

1~r-~\H---~~---+--~
140

~

~ l00f---rI~
\--lr--+---+----l

= 25° C

TA

f---+---j--+--f--l

'20 f---1\1\:----l--+---+----l

~ BOI--+-~~\-r---+--+---+

f-I_-+__t-_-tNOMINAL VOLT AGE
DELAY =13000SECrCPF-

15

60

1---+--lI.1,,:--+--+---1

--

401---+----r~~----t---~

10

12
20

DELAY (mS)

I---+---+----+,,---'~=_~

°0~-~20~-~40~-~60~-B~0,.-~100
FREQUENCY (KH,)

KEYBOARD LAYOUT FOR KR9601/9602-S'TD

[ill [millJ~~~~@]J@TIffiJ[illffiJffi)lliJ ill] [rn @TI
[ill [ill [ru ~lli][lli@1]rm[ill@IJ@TI[llilru~[m Lm ill] @IJ[ill
[ill
[ill [ill @]J ~@!]illJillJ[§JlliJ[lliffi][illillJ@I]~
n
~ ffiJ [lli

'~i
YO i
Y2

YO

Y1

YO

Y1

. Y2

YO

YO

Y3

Y1

Y4

Y5

Y2, Y3

Y6

Y4

Y7

Y7

Y5

Y6

yg

YB

Y7

Y4

yg

YB

Y5

yg

Y6

YB

.

Y2

Y1

~

YO

~

Y6

Y4

Y7

Y5

Y4

~

Y5

Y2

Y1

Y7

~

~

~

~

~

fl

~

~

~

Lrn [ill ~mJ @1]ffi][lli[gJ ill] [ill[lliffilillJ mJ ill] ill] ill] ffi] [ill [ill
@U [ill
[; [lli ffiJ
[illi
Y2

Y1

Y3

Y2

'i0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

XB
Y6

Y7

Y7

YB

yg

Y6

yg

Y5

Y4

YB

Y3

Y5

Y4

Y7

Circuit diagrams utilizing SMC products are included as a means 01 illustrating typical semiconductor applica·

l~~g~;,,;f;g~~:n~~e~o:a~f~fl~n~~~:,:~~~~~~c~~le~':.'d ~~n~~~~~~~I:~~ft~~: ~o":.!~c~~s;O:~~0~~7ilt~~:

assumed for inaccuracies. Furthermore, such information does not convey to the purchaserofthesemiconductor

devices described any license under the petent rights 01 SMC or others. SMC reserves the right to make changes
at any time in order to improve design and supply the best product possible.

752

Microprocessor Products

Part
5'IuIl'ber

MPU800
·MPU80Q.l

:MPu8OO-4.
MPU810A.
MPi:l'810A-l.

MPU810A-4
MPU830...
:M.1?Cr630~1

'.

:O••crQ1d.cm
Mioro'Dl'OC8SSOr
WcroP1'O(ll)SSQr
WQl'OP1'(lOesSOl'
It.AM-lIOJl'1:rn$r
It.AM~I/O~

It.AM-IIO-T1lneli

:amBiO

MPU830-4

MM·:t!Ci
ROM-I/O

MPUS31

Iio

MPU831
MPU831-4

liD

I/O

'.'

...

8 Bit
8131t

.S131t
e131t
81311'..
8l3it
8l3it
8B1t

8B1t
8 Bit
8 rut
8131t

1'1:00...

S:Pe.ct·

CMOS.
CMOS
CMOS

2.5MB:Z
.1.0 MB:Z.

CMOS'

.cMos

4;OMRa
a.aMRa

'. lIo'iImI"

tU.iiiij8i .

at

c··.

BV"

CMOS
CMOS

:uum;1iI

.CMoS

".!'$V
5V.

4.0lDk

OMOS
CMOS
C)'{OS

2.5 lrU'Iz

753

1.0lrU'Iz
4.0 MHz

40Dtp

8V

aT

1,.OlrU'Iz

40 DIP

ev.

1.Oli4Bz
4.01Orz

CMOS

.~.

.

8V

av
6V

e:v'

'm

.'

:

4O:t>IP
40PIP ..•..
40DlP •...
40 DIP
40IlIP
. 40 DIP

40DlP
.40DIl"
40 DIP
40DlP

--

755·756'
.756-.'1'56
755·'1'56
.757"'75$
757·7fl8
757·'1'68
759-,760
759-750
7e9-'1'60
759-7eO
'1'.59-'1'60
'1'59-760'

754

MPU 800
MPU 800-1
MPU 800-4
PRELIMINARY

High-Performance
Low-Power Microprocessor
FEATURES

PIN CONFIGURATION

o Variable Power Supply: 2.4V - 6.0V

o Fully Compatible Wth Z80® Instruction Set
o Pin-Compatible With NSC800

AS
A9
A10
A11
A12
A13
A14
A15
ClK
XOUT
XIN
ADO
AD1
AD2
AD3
AD4
AD5
ADS
AD7
GND

o Powerful Set of 158 Instructions
010 Addressing Modes
o 22 Internal Registers
o Low Power: 50 mW at 5 V Vcc
o Multiplexed Bus Structure

o
o

On Chip Bus Controller and Clock Generator
DOn-Chip 8 bit Dynamic RAM Refresh Circuitry
Three Speed Versions:
MPU800-4 4 MHz
MPU800
2.5 MHz
MPU800-1
1 MHz
Capable of addressing 64 k bytes of memory, and
256 1/0 devices
Five interrupt request lines on-chip
Schmitt trigger input on reset
Power-Save Feature

o
o
o
o

v"

PS
WAIT
RESET OUT

l!REQ
BACK

101M
~
Rl)

WR
ALE
SO

RFSH
S1

TNiA

iNfR
~
RSTB

RSTA
NMi

GENERAL DESCRIPTION
The MPU800 is an 8 bit microprocessor that functions as
the central processing unit (CPU) in Standard Microsystems MPU800 microcomputer family. The device is fabricated in double-poly CMOS to combine high performance
with the low-power of CMOS.

including: vectored priority interrupts, refresh control,
power save, and interrupt acknowledge.
Dedicated peripherals (MPU81 0 Ram 1/0 Timer, MPU830
ROM 1/0 Timer, and (MPU831 1/0 Timer) have on-chip
logic for direct interface to the MPU800.

Many system functions are incorporated on the device

zao is a registered trademark of Zilog Corporation.

755

For additional information, consult your 1986 catalog or contact our product marketing department at (516) 273·3100.
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
applications: consequently complete information sufficient for construction purposes is not necessarily gill9n.
~~i§~~~~~:~~;: The
information has been carefully checked and is beliell9d to be entirely reliable. However, no responsibility is

11"'"',,,',,", ":"11:>'1,"",;,:0;'

assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right 10 make changes at any time in order to improve design ana supply the best product possible,

756

MPU810A
MPU 810A-1
MPU 810A-4
PRELIMINARY

RAM-I/O-Timer
FEATURES
D Variable Power Supply: 2.4V-6.0V
D Pin-Compatible With NSCS10
D Three Programmable 1/0 Ports

PIN CONFIGURATION
v~

PC3/TG

PC4fT1IN
TOIN
RESET
PCSfT10UT
TOOUT
10T/M
CE

D Two 16 Bit Programmable Counter Timers
D Very Low Power Consumption
D Fully Static Operation
D Single Instruction 1/0 Bit Operations
D Timer Operation: DC to 5 MHz
D Bus Compatible with MPUSOO Family
D Three Speed Versions For Full

PC2/S'fB

PC1/BF
PCO/INTR
PB7
PB6
PBS
PB4
PB3
PB2

AD

WR

Compatibility with the MPUSOO:
MPUS10-4-4 MHz
MPUS10 -2.5 MHz
MPUS10-1-1 MHz

ALE
ADO
AD1
AD2
AD3

PB1
PA7
PA6
PAS

AD4

PA4

PBO

ADS
PA3
AD6
PA2
AD7
PA1
GND --c.::"'---_ _....:..:..r- PAO

BLOCK DIAGRAM

GENERAL DESCRIPTION
The MPUS10A functions as a memory, inputloutput
peripheral interface, and a timing device. The memory is
comprised of 1024 bits of static RAM organized 12S by S.
The 1/0 portion consists of 22 programmable inputloutput bits arranged as three separate ports, with each bit individually definable as an input or output. The port bits can
be set or cleared individually and can be written or read in
bytes. Several types of strobed mode operations are available through port A.
The timer portion of the device consists of two programmable 16 bit binary down-counters each capable of
operation in anyone of 6 modes. Timer counts are extendable by one of the available pre-scale values. The MPUS10A
comes in three speed versions to match the MPUSOO.

FIGURE 1

757

For additional inform&tion, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.

~

~.~~~:i Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor

lIPPlications: consequently complete information sufficient for construction purposes is not necessarily given.
The information has been carefullv checked and is believed to be entirely reliable. However. no responsibility is
.,,""'" "'"~"." "'. assumed for inaccuracies. Furthermore. such information does not convey to the purchaser of the
.,," m """ . 'w, """'... semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the besl product possible.

758

MPU830
MPU831
PRELIMINARY

MPU 830 ROM I/O Device
MPU 831 I/O Device
FEATURES

o Variable Power Supply: 2.4V-6.0V
o Pin-Compatible With NSC830/NSC831
o Three Programmable I/O Ports
o 2K x 8 Read Only Memory (MPU830)
o Very Low Power Consumption
o Fully Static Operation
o Single Instruction I/O Bit Operations
o Bus Compatible With MPU800 Family
o Strobed Mode Available on Port A

PIN CONFIGURATION
PAO
A8
A9
A10
RESET
CEo/CEo
10/M
10R/CE,/CE,'
RD
WR
ALE
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7

PAO

Vee
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PCO/INTR
PC1/BF
PC2/STB
PC3
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

vss

*Pin 6 is mask programmable as CEo or CEo
Pin 8 is mask programmable as lOR, CEll or CE l

GENERAL DESCRIPTION
The MPU830 is a combination ROM and I/O
peripheral device contained in a standard 40 pin
package.
The ROM is comprised of 16,384 bits of Read
Only Memory organized as 2048 by 8.
The I/O portion consists of 20 programmable
input/output bits arranged as three separate ports,
with each bit individually definable as an input or
output. The port bits can be set or cleared individually and can be written or read in bytes. Several
types of strobed mode operations are available
through port A.
The MPU831 is similar to the MPU830 except
that is contains no ROM. The MPU831 is useful for
prototyping work prior to ordering the MPU830, and
when on chip ROM is not required.

Vee
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PCO/INTR
PC1/BF
PC2/STB
PC3
PBO
PB1
PB2
PB3
PB4
PB5
PB6

RESET
CEo

Vee
CE,
RD
WR
ALE
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7

Vss '-="-_ _.=.c..J' PB7
*Tie pins 2, 3 and 4 to either Vee or Vss.

Figure 1
CEo/CEo

IOR/CE11~

,..----,

--tst-+
(10)

:

1iD~

IO/M~
ALE~
RESET ~

CONTROL
LOGIC

L-_--'

ROM
16,38481TS
(2048l<8)

(1.-4\

(12-19)

PAO-PA7

(21-28)

ADDRESS
8UFFERS

ADDRESSI

OA,'

BUFFERS
AND
LATCHES

Note' ApphcablepLlIOutlrn4Q-p,ndual.,n.hnepackagew,\'Hn parentheses

759

(1.33·391
PORTA

(29-32)

PORTe
PeG-pel
HANDSHAKE

BLOCK DIAGRAM

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.
diagrams
utilizing complete
SMC products
are included
means of illustrating
semiconductor
applications:
consequently
information
sufficientas
foraconstruction
purposes istypical
not necessarily
given.
~~~~~~~~~,;~;~~~~~~r~ Circuit
The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design and supply the best product possible.

760

.,f

Shift Register

SB 5018-80, 81, 133

ums

+6

16 DIP

763-764

SB5018

1:MRz

+5

16DIP

766-766

761

762

SR5015-XXX
SR 5015-80
SR 5015-81
SR 5015-133

Quad Static Shift Register
FEATURES
D COPLAMOS® N Channel Silicon Gate
Technology
D Variable Length-Single Mask
Programmable-1 to 134 bits
D Directly TTL-compatible on all inputs,
outputs, and clock
D Clear function
D Operation guaranteed from DC to 1.0 MHz
D Recirculate logic on-chip
D Single +5.0V power supply
D Low clock input capacitance
D 16 pin ceramic DIP Package
D Pin for Pin replacement for AMI S2182, 83, 85

PIN CONFIGURATION
INPUTA
RECABC

1 "--../16 ~
15 ~
2

OUTPUT A
RID

3

14

OUTPUT 0

4

13

INPUTD

5

12'

RECD

6

11

NC

Vee I ·7

10

INPUTC

8

9

CLOCK

CLEAR
INPUTB
OUTPUTB,.
GNDI

OUTPUTCI

APPLICATIONS
D Memory Buffering
D Unique Buffering Lengths
D Terminals
BLOCK DIAGRAM
OUTPUT A

OUTPUTC

REC CONTROL ABC">-........It--I.~

,-j---< INPUTC

INPUT A >-+_---1

~--<... RECIRC.INPUT D

'-.1-.----:::: REC. CONTROL D
INPUT B

INPUT 0

CLOCK

763

CLEAR

For additional information, consult your 1986 catalog or contact our product marketing department at (516) 273-3100.
Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
applications: consequently complete information sufficient for construction purposes is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furlhermore, such information does not convey to the purchaser of Ihe
semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design ana supply the best product possible.

764

SR 5017
SR 5018

Quad Static Shift Right/Shift Left Shift Register
Last In First Out Buffer
LIFO
FEATURES
D COMPLAMOS® N-Channel Silicon
Gate Technology.
D Quad 81 bit or Quad 133 bit
D Directly Compatible with PL, MOS
D Operation Guaranteed from DC to
1.0MHz
D Recirculate logic on-chip
D Single +5.0V power supply
D Low clock input capacitance
D Single phase clock at PL levels
D Clear function
D 16-pin Ceramic DIP Package
APPLICATIONS
D Bi-Directional Printer
D Computers-Push Down
Stack-LIFO
D Buffer data storage-memory buffer
D Delay lines-delay line processing
D Digital filtering

PIN CONFIGURATION
INPUTD

RECD

RID

GND

OUTPUTD

OUTPUTC

CLEAR

INPUTC

OUTPUT A

INPUTS

L/RCON

OUTPUTS

INPUT A

RECASC

Vcc

CLOCK

D Telemetry Systems
D Terminals
D Peripheral Equipment

BLOCK DIAGRAM
OUTPUT A

OUTPUTC

REC CONTROL ABC ' ) -..........L-.J

'--J---oc. INPUT 9'

INPUT A >-+---l~

J---C, RECIRC.INPUT D

'--.J-.---C REC. CONTROL D

INPUTB

>-----1

'--J---'. INPUT D

L J R C O N T R O L > - - - - - - - -.......'"t~~~~~

CLOCK

765

CLEAR

For additional information, consult your 1986 SMC catalog or contact our product marketing department at (516) 273-3100.

STANDARD MICROSVSTEMS
I\~I
CORPOR/"\IIVI1I

Circuit diagrams utilizing SMC products are included as a means of illustrating typical semiconductor
applications: consequently complete information sufficient for construction purposes is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However. no responsibility is
" .." .... " _ " '''"' assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the
,,,,,m 3>OO·;W, "0 m",% semiconductor devices described any license under the patent rights of SMC or others. SMC reserves the
right to make changes at any time in order to improve design and supply the best product possible.

766

Plastic Package Outlines

c --------]
-------

DIM
A
B
C
D
E
F

G
H

J
K

L
M

8 LEAD
.380-.400
.240-.250
.125-.135
.016-.021
.290-.330
.055-.065
.090-.110
.040-.050
.010-.014
.120-.140
.315-.370
.210-.250

14 LEAD
.750-.770
.240-.250
.125-.135
.016-.021
.290-.330
.060-.070
.090-.110
.075-.085
.010-.014
.120-.140
.315-.365
.210-.250

16 LEAD
.750-.770
.240-.250
.130-.140
.016-.021
.290-.330
.060-.070*
.090-.110
.025-.035
.010-.014
.120-.140
.315-.365
.210-.250

18 LEAD
20 LEAD
24 LEAD
28 LEAD
40 LEAD
48 LEAD
.900-.920 1.025-1.050 1 .245-1 .265 1 .450-1 .470 2.050-2.070 2.430-2.460
.240-.250 .240-.260 .530-.545 .535-.550 .535-.550
.53q~
.125-.140
.125-.140
.145-.155 .145-.155 .145-.155
.140-.200
.016-.021
.016-.021
.016-.021
.016-.021
.016-.021
.015-.021
.290-.330 .290-.330 .590-.630 .590-.630 .590-.630
.580-.630
.060-.070 .060-.070 .060-.070 .060-.070 .050-.060
.040-.065
.090-.110 .090-.110 .090-.110, .090-.110 .090-.110
.090-.110
.040-.060 .065-.075 .065-.085 .070-.090 .070-.090
.065-.090
.010-.014 .010-.014 .010-.014 .010-.014 .010-.014
.007-.014
.120-.140 .120-.140 .120-.140 .120-.140 .120-.140
.120-.160
.315-.365 .315-.365 .610-.670 .610-.670 , .610-.670
.610-.675
.210-.250 .210-.250 .210-.250 .210-.250 .210-.250
.210-.250

',045 TYP FOR END LEADS

767

Plastic Surface Mount Package Outlines
20, 28, 44, 68, 84 J-Lead Carrier
PIN 1

NOTE:

1. All dimensions are in inches.
2. Circle indicating pin 1 can appear
on a top surface as shown on the
drawing or right above it on a
beveled edge.

~---------D1------------~

~---------D-------------t

DIM
A
A1
D
D1
D2
D3
F

G
J
E
R
8
81
C

20l
.165-.180
.090-.12b
.385-.395
.350-.356
.290-.330
.200
.050TYP
.045TYP
.000-.020
.047-.053
.025-.045
.013-.021
.026-.032
.020-.045

28l
.160-.188
.090-.120
.482-.495
.450-.456
.390-.430
.300
.042-.056
.042-.048
.000-.020
.047-.053
.025-.045
.013-.021
.026-.032
.020-.045

44l
.160-.188
.090-.120
.682-.695
.650-.656
.590-.630
.500
.042-.060
.042-.048
.000-.028
.047-.053
.025-.045
.013-.021
.026-.032
.020-.045
768

68l
.160-.190
.090-.130
.982-.995
.950-.956
.890-.930
.800
.042-.062
.042-.048
.00-.028
.047-.053
.025-.045
.013-.021
.026-.032
.020-.045

84l
.165-.179
.095-.109
1.185-1.195
1.150-1.156
1.090-1.130
1.000
.050TYP
.045TYP
.010
.047-.053
.025-.045
.013-.021
.027
.020-.045

Small Outline Package
(SOle), 16 Lead Plastic

I~

D

t

-I

"g~~J
I-

sPlane
...

i'++l ~

A1

A

DIM

MIN

A

.053

.069

A1

.004

.010
.019

MAX

B

.014

e

.0075

.010

D

.386

.394

E
e

.150

.158

H

.228

.244

h

.010

.020

L

.016

.050

0(

0°

8°

.050 BSe

769

Cerdip Hermetic Package Outlines
14, 16, 18, 20 PIN CERDIP

8 PIN CERDIP HERMETIC PACKAGES

HERMETIC PACKAGES ~

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24, 28, 40 PIN CERDIP HERMETIC PACKAGES

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DIM

8 LEAD

14 LEAD

16 LEAD

18 LEAD

20 LEAD

A

.400 MAX

.785 MAX

.810 MAX

.915 MAX

.970 MAX

24 LEAD

28 LEAD

40 LEAD

8
C

.245-.295

.244-.295

.244-.295

.265-.295

.265-.295

.510-.595

.510-.595

.510-.595

.160 MAX

.160 MAX

.180 MAX

.180 MAX

.180 MAX

.180 MAX

.180 MAX

.180 MAX

1.280 MAX 1.460 MAX 2.070 MAX

D

.016-.020

.016-.020

.016-.020

.016-.020

.016-.020

.016-.020

.016-.020

.016-.020

E

.290-.320

.290-.320

.290-.320

.310-.330

.310-.330

.590-.620

.590-.620

.590-.620

F

.050-.070

.050-.070

.050-.070

.050-.070

.050-.070

.050-.070

.050- .070

.050-.070

.100±.010 .100±.010 .100±.010 .100±.010 .100± .010 .100±.010 .100±.010

.100-.010

G
H
J

-

.065 TYP

.020TYP

.040TYP

.020TYP

.045 TYP

.045 TYP

.045TYP

.008-.012

.008-.012

.008-.012

.008-.012

.008-.012

.008-.012

.008-.012

.008-.012

L

.400 MAX

.400 MAX

.400 MAX

.400 MAX

.400 MAX

.700 MAX

.700 MAX

.700 MAX

M

.240-.300

.240-.300

.240-.300

.240-.300

.240-.300

.240-.300

.240-.300

.240-.300

K

.125 MIN

.125MIN

.125 MIN

.125 MIN

.125MIN

.125MIN

.125MIN

.125 MIN

770

Ceramic Package Outlines
14, 16, 18, 20 PIN HERMETIC PACKAGE

14 LEAD

~

~~ft
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0

-I IG

I

I

\/

SEATING PLANE !-L--=::::I M

20 LEAD

A

.670 .760 .790 .810 .885 .915 .965 .995

C

.175

.175

.175

.175

D

.015 .021

.015 .021

.015 .021

.015 .021

F

.048 .060 .048 .060 .048 .060 .048 .060

G

.090 .110 .090 .110 .090 .110 .090 .110

J

.008 .012 .008 .012 .008 .012 .008 .012

K

.130 .170 .130 .170 .130 .170 .130 .170

r---'=--

.295 .325 .295 .325 .295 .325 .295 .325

N

.025 .060 .025 .060 .025 .060 .025 .060

10°

M

24 LEAD
DIM
A

771

18 LEAD

MIN MAX MIN MAX MIN MAX MIN MAX

24, 28, 40, 48 PIN HERMETIC DIP

AlL UNITS INCHES UNLESS OTHERWISE SPE91FIED

16 LEAD

DIM

MIN

MAX

10°

28 LEAD
MIN

MAX

10°

10°

40 LEAD
MIN

MAX

48 LEAD
MIN

MAX

1.180 1.220 1.380 1.430 1.980 2.030 2.376 2.424

B

.575

.610

.580

.610

.580

.610

.567

.600

C

.595

.625

.595

.625

.595

.625

.590

.620

D

.065

.120

.065

.120

.065

.120

.077

.093

E

.020

.070

.020

.070

.020

.070

.025

.060

F

.125

.175

.125

.175

.125

.175

.130

.170

G

0.100 TP

0.100 TP

0.100TP

0.100 TP

H

0.05 TP

0.05 TP

0.05 TP

0.500TP

J

0.018TP

0.Q18 TP

0.Q18 TP

0.018 TP

K

0.040TP

0.040TP

0.040 TP

0.040TP

L

0.010 NOM

0.010 NOM

0.010 NOM

0.010 NOM

M

0.600TP

0.600TP

0.600TP

0.600TP

Ceramic Leadless
Chip Carrier Outlines
Edge

[Ei!3J
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PIN
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DIM
A
A1
B
0
01
02
03

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G
J
L
L1

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44 LEAD
.062-,078
.071-.089
.025TYP
.640-.660
.500
.355-.598
.350-.590
,050BSC
.020 x 45°
.040 x 45°
,045-.055
,075-.095

68 LEAD
.072-.088
.081-.099
.025TYP
.940-.965
.800
.455-.820
.450-.820
.050BSC
.020 x 45°
.040x45°
.045-.055
,075-.095

772

84 LEAD
.072-.088
.081-.099
.025TYP
1.135-1.165
1.000
.530-1.020
.500-,990
.050BSC
.020x45°
.040 x 45°
,042x.048
.075-.095

Cerquad Package Outline
68 LEADED CEROUAD GULLWING (GA)

II

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.900

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1.125
±.005

'DEFINES MINIMUM CLEAR LEADFRAME ZONE -zone consists of package body.
including ceramic and glass.

~".L
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.120

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68 LEADED CEROUAD FLAT LEAD (FA)

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.050

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.900

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1.250
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including ceramic and glass .

.155

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• 'PC Board Socket available from Cannon ITT

- pin CAlll484
10550 Talbert Ave., Fountain Valley, CA 92728-8048

773

c

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F'12} max

SALES REPRESENTATIVES
fiii~Oiig;gR~~7"7"n CALIFORNIA/South

y~+i~~~all~gtus Drive

EI Segundo, California 90245
PHONE: 213-634-2116
Varigan, Inc.
23441 S. Pointe Dr.
Suite 90

Laguna Hills, CA 92653
PHONE: 714-855-0233
TELEX: 910-997-0225
FAX: 714-458-0854
Cerco
5230 Carron Canyon Road
Suite 214
San Diego, California 92121
PHONE: 619-450-1755
TELEX: 910-335-1220
FAX: 619-450-3681
COLORADO
Elcom, Inc.
2015 South Dayton Street
Denver, Colorado 80231
PHONE: 303-337-2300
TELEX: 62927893 (Easylink)
FAX: 303-745-0462

ILLINOIS/South
S.w. Wollard Co.
Rural Route 1
Post Office Box 66A
Parker, Kansas 66072
PHONE: 913-898-6552
FAX: 913-898-6081

MISSISSIPPI
Jordan Center
HuntSVille, Alabama 35805-0306
PHONE: 205-536-3044
FAX: 205-533-5097

INDIANA
Wilson Technical Sales, Inc.
P.o Box 688510
Indianapolis, Indiana 46268
PHONE: 317-872-2513
TELEX: 910~997~8120
FAX: 317-872-0664

MISSOURI
S.w. Wollard
Rural Route 1
Post Office Box 6SA
Parker, Kansas 66072
PHONE: '913~898-6S52
FAX: 913-898-6081

IOWA
S.W. Wollard Co.
Rural Route 1
Post Office Box 66A
Parker, Kansas 66072
PHONE: 913-898-6552
FAX: 913-898-6081

MONTANA
Quest Marketing, Inc.
15921 N.E. 8th St., Ste. 207
Bellevue, Washington 98008
PHONE: 206-747-9424
FAX: 206-643-3488

~~b~r,j~:~a~a~~~~~~t:~~oc.

NEBRASKA
S.w. Wollard Co.
Rural Route 1
Post Office Box 66A
Parker, Kansas 66072
PHONE: 913-898-6552
FAX: 913-898-6081

KANSAS
s.w. Wollard Co.
Rural Route 1
Post Office Box 6SA
Parker, Kansas 66072
PHONE: 913-898-6552
FAX: 913-898-6081

CONNECTICUT
Orion Group
KENTUCKY
27 Meriden Avenue
Southington, Connecticut 06489 Wilson Technical Sales, Inc.
P.O. Box 688510
PHONE: 203-621-8371
Indianapolis, Indiana 46268
TWX: 510-601-1381
PHONE: 317-872-2513
FAX: 203-628-0494
TELEX: 910-997-8120
FAX: 317-872-0664
DELAWARE
Tritek Sales, Inc.
LOUISIANA
21 E. Euclid Avenue
Haddonfield, New Jersey 08033 Southern States Marketing
1143 Rockingham, Suite 106
PHONE: 609-429-1551
Richardson, Texas 75080
TELEX: 710-896-0881
PHONE: 214-238-7500
FAX: 609-429-4915
TWX: 910-867-4754
FAX: 214-231-7662

NEVADA/North
Costar, Inc.
19220 Stevens Creek Blvd.
Cupertino, California 95014
PHONE: 408-448-9339
TELEX: 910-338-0206
FAX: 408-446-4885
NEVADA/South
Southwest Technical Sales
4314 E. Tonto St.
Phoenix, Arizona 85044
PHONE: 602-893-1209
TELEX: 910-950-0195
FAX: 602-893-1312

""'--'''-''''-""'''=='-''"''"'''"''''''1 ~LE~RIDA

600 W. Hillsboro Blvd., Ste. 300 MAINE
The Orion Group
Deerfield Beach, FL 33441
~~~~trJ~;~a~a~~~~~~t~~~OC.
607 North Ave.
PHONE: 305-426-8944
Jordan Center
Wakefield, Massachusetts 0188
TELEX: 510-100-4470
PHONE: 617-245-5220
Huntsville, Alabama 35805·0306 FAX: 305-427-9911
TWX: 510-601-0667
PHONE: 205-536-3044
FAX: 205-533-5097
MEC
MARYLAND
989 Woodgate Drive
Robert Electronic Sales
ALASKA
Palm Harbor, FL 33563
Quest Marketing, Inc.
5525 Twin Knolls Rd., Ste. 325
PHONE: 813-784-8561
Columbia, Maryland 21045
15921 N.E. 8th Street, Ste. 207 FAX: 305-427-9911
BeHevue, Washington 98008
PHONE: 301-995-1900
FAX: 301-964-3364
PHONE: 206-747-9424
MEC
FAX: 206-643-3488
375 S. North Lake Blvd.
MASSACHUSETTS
Altamonte Springs, FL 32701
ARIZONA
The Orion Group
PHONE: 305-332-7158
Southwest Technical Sales
607 North Ave.
4314 E. Tonto St.
Wakefield, Massachusetts 01880
GEORGIA
Phoenix, Arizona 85044
Electronic Marketing Associates PHONE: 617-245-5220
PHONE: 602-893-1209
6695 Peachtree Industrial Blvd. TWX: 510-601-0667
TELEX: 910-950-0195
Suite 109
Digital Equipment Corp. Only
FAX: 602-893-1312
Atlanta, Georgia 30360
Mill-Bern Associates, Inc.
PHONE: 404-448-1215
2 Mack Road
ARKANSAS
FAX: 404-446-9363
Woburn, Massachusetts 01801
Southern States Marketing
PHONE: 617-932-3311
1143 Rockingham, Suite 106
IDAHO
FAX: 617-932-0511
Richardson, Texas 75080
Quest Marketing, Inc.
PHONE: 214-238-7500
15921 N.E. 8th St., Sle.207
MICHIGAN
TWX: 910-867-4754
Bellevue, Washington 98008
A.P. Associates
FAX: 214-231-7662
PHONE: 206-747-9424
P.O. Box 777
FAX: 206-643-3488
Brighton, Michigan 48116
CALIFORNIA/North
PHONE: 313-229-6550
ILLINOIS/North
Costar, Inc.
TELEX: 287310
19220 Stevens Creek Blvd.
Sumer, Inc.
FAX: 313-229-9356
Cupertino, California 95014
1675 Hicks Road
PHONE: 408-446-9339
~H~~E~:f~_991:~~~8iS 60008 MINNESOTA
TELEX: 910-338-0206
Comstrand, Inc.
FAX: 408-446-4885
62958372 (Easylink)
2852 Anthony Lane South
FAX: 312-991-0474
Minneapolis, Minnesota 55418
PHONE: 612-788-9234
TELEX: 910-576-0924
FAX: 612-788-7218
ALABAMA

NEW HAMPSHIRE
The Orion Group
607 North Ave.
Wakefield, Massachusetts 01880
PHONE: 617-245-5220
TWX: 510-601-0667
NEW JERSEY/Northern
Technical Marketing Group
705 Cedar Lane
Teaneck, N.J. 07666
PHONE: 201-692-0200
TWX: 710-990-5086
FAX: 201-692-8367
NEW JERSEY/Southern
Tritek Sales, Inc.
21 E. Euclid Avenue
Haddonfield, New Jersey 08033
PHONE: 609-429-1551
TELEX: 710-896-0881
FAX: 609-429-4915
NEW MEXICO
Southwest Technical Sales
4314 E. Tonto SI.
Phoenix, Arizona 85044
PHONE: 602-893-1209
TELEX: 910-950-0195
FAX: 602-893-1312
NEW YORK
Technical Marketing Group
20 Broad Hollow Road
Melville, N.V. 11747
PHONE: 516-351-8833
TWX: 910-997-3030
FAX: 516-351-8667
T-Squa~ed

Elec. Co., Inc.
7353 VIctor Pittsford Rd.
Victor, New York 14564
PHONE: 716-924-9101
FAX: 716-924-4946

T-Squared Elec. Co., Inc.
6443 Ridings Road
Syracuse, New York 13206
PHONE: 315-463-8592

TENNESSEE

~~b~rJ~:da~a~~~~~~t~~oc.

Jordan Center
Huntsville, Alabama 35805·0306
NORTH CAROLINA
PHONE: 205-536-3044
Electronic Marketing Associates FAX: 205-533-5097
9225 Honeycutt Creek Road
~~~i~~; ~f~~~4~~~~Oa 27609 TEXAS
Southern States Marketing
TELEX: 510-928-0594
1143 Rockingham, Suite 106
FAX: 919-848-1787
Richardson, Texas 75080
PHONE: 214-238-7500
NORTH DAKOTA
TWX: 910-867-4754
Comstrand, Inc.
FAX: 214-231-7862
2852 Anthony Lane South
Minneapolis, Minnesota 55418
Southern States Marketing
PHONE: 612-788-9234
400 E. Anderson Lane, Suite 111
TELEX: 910-576-0924
Austin, Texas 78752
FAX: 612-788-7218
PHONE: 512-452-9459
TWX: 910-874-2006
OHIO
Thompson & Associates
UTAH
23215 Commerce Dr., Suite 202 Ercom, Inc.
Beachwood, Ohio 44122
2520 South State Street
PHONE: 216-831-6277
Suite 116
TELEX: 333804
Salt Lake City, Utah 84115
FAX: 216-831-2553
PHONE: 801-486-4233
TELEX: 62893625 (Ea.ylink)
Thompson & Associates
309 Regency Ridge
VERMONT
Dayton, Ohio 45459
The Orion Group
PHONE: 513-435-7733
607 North Ave.
TELEX: 810-459-1767
Wakefield, Massachusetts 01880
FAX: 513-435-1898
PHONE: 617-245-5220
TWX: 510-601-0667
OKLAHOMA
Southern States Marketing
VIRGINIA
1143 Rockingham, Suite 106
Robert Electronic Sales
Richardson, Texas 75080
1901 West Huguenot Road,
PHONE: 214-238-7500
Suite 201
TELEX: 910-867-4754
Richmond, Virginia 23235
FAX: 214-231-7662
PHONE: 804-276-3979
FAX: 804-794-6090
OREGON
Quest Marketing, Inc.
WASHINGTON
6700 S.W. 105th. Ste. 3110
Beaverton, Oregon 97005
207
PHONE: 503-641-7377
Bellevue, Washington 98008
FAX: 503-646-9536
PHONE: 206-747-9424
FAX: 206-643-3488
PENNSYLVANIA/Eastern
Tritek Sales, Inc.
WASHINGTON D.C.
21 E. Euclid Avenue
Robert Electronic Sales
Haddonfield, New Jersey 08033 5525 Twin Knolls Rd. Suite 331
PHONE: 609-429-1551
Columbia, Maryland 21045
TELEX: 710-896-0881
PHONE: 301-995-1900
FAX: 609-429-4915
WEST VIRGINIA
PENNSYLVANIA/Western
Thompson Associates
Thompson & Associates
23715 Merchantile Road
309 Regency Ridge
Beachwood, Ohio 44122
Dayton, Ohio 45459
PHONE: 216-831-6277
PHONE: 513-435-7733
TELEX: 810-427-9453
TELEX: 810-459-1767
WISCONSIN/West
RHODE ISLAND
Comstrand, Inc.
The Orion Group
2852 Anthony Lane South
607 North Ave.
Minneapolis, Minnesota 55418
Wakefield, Massachusetts 01880 PHONE: 612-788-9234
PHONE: 617-245-5220
TELEX: 910-576-0924
TWX: 510-601-0667
FAX: 612-788-7218

?5~~~t ~.W.k~\i~~t~~~te.

SOUTH CAROLINA
Electronic Marketing AsSOCiates
210 West Stone Avenue
Greenville, South
Carolina 29609-5499
PHONE: 803-233-4637/4638
TELEX: 810-281-2225
FAX: 803-242-3089
SOUTH DAKOTA
Comstrand, Inc.
2852 Anthony Lane South
Minneapolis, Minnesota 55418
PHONE: 612-788-9234
TELEX: 910-576-0924
FAX: 612-788-7218

WISCONSIN/Ea.t
Sumer, Inc.
350 Bishops Way
Brookfield, Wisconsin 53005
PHONE: 414-784-6641
FAX: 414-785-9628
WYOMING
Elcom, Inc.
2015 South Dayton Street
Denver, Colorado 80231
PHONE: 303-337-2300
TELEX: 62927893 (Easyllnk)
FAX: 303-745-0462

DISTRIBUTORS
ALABAMA
Hall-Mark Electronics Corp.
4900 Bradford Drive
Huntsville, Alabama 35807

PHONE: 205-837-8700
ARIZONA
Cetee Electronics
3617 N. 35th Avenue

P·hoenix, Arizona 85017
PHONE: 602-272-7951

Hall-Mark Electronics Corp.
4040 ~ast Raymond
PhoenIx, Arizona 85040
PHONE: 602-437-1200

Cetec Electronics
3940 Ruffin Road
San Diego, California 92123
PHONE: 619-278-5020

CALIFORNIA
Cetec Electronics
1692 Browning
Irvine, California 92714
PHONE: 714-250-4141

Cetec Electronics
2300 Owen Street
Santa Clara, California 95051
PHONE: 408-434-1114
FAX: 408-433-0822

Diplomat Electronics, Inc.
6921 San Fernando Road
Glendale, California 91201
PHONE: 818-845-8700
FAX: 818-848-6420

Halt-Mark Electronics Corp.
8130 Remmet Avenue
Canoga Park, California 93104
PHONE: 818-716-7300
FAX: 818-704-4860

Hall-Mark Electronics Corp.
1110 Ringwood Court
San Jose, California 95131
PHONE: 408-432-0900
FAX: 403-433-0745

Hall-Mark Electronics Corp.
6341 Auburn Blvd.
Suite D
Citrus Heights, California 95610
PHONE: 916-722-8600

Hall-Mark Electronics Corp.
3878 Ruffin Road, Ste. 108
San Diego, California 92123
PHONE: 619-268-1201

Hall-Mark Electronics Corp.
19220 S. Normandie Avenue
Torrance, California 90502
PHONE: 213-217-8450

774

DISTRIBUTORS (con't)

Inc.

~1~~~E~yro~~:: ~~ite 102

~{aa,;~~~~S'':'~way

~JW~a~!~:~;iCS,

Tustin, California 92680
PHONE: 714-869-4700

Atlanta, Georgia 30338
PHONE: 404·393·9666
800·241·5523

Columbia, Maryland 21046
PHONE: 301·621-6169
800-638·6656

Western Microtechnology. Inc.
10040 Bubb Road
Cupertino, California 95014
PHONE: 408·725-1660
FAX: 408·255·6491

Executive Campus
Marlton, New Jersey 08053
PHONE: 609-963-5010
800-257·780817111

IDAHO
Radar Electric Co., Inc.
5821 Franklin Road

MASSACHUSETTS
Nu Horizons
151 Andover St.

BOise, Idaho 83709

Danvers, MA 01930

PHONE: 208·336·2227
FAX: 208-336-2322

PHONE: 617·7n-8800

IOWA

Hall-Mark electronics Corp.
6 Cook Street
Pinehurst Park

Hall-Mark Electronics Corp.

14831 Franklin Avenue

COLORAOO
Hall-Mark Electronics Corp.

6950 Tucson Way So.
Suite 206

~~Ib~Ii3<:~'i..~~rI12

Advent Electronics
682 58th Avenue S.W.

Nu Horizons
258 Route 46
Falrlleld, N.J. aroo&
PHONE: 201-882·8300

~~'ba~:~~J~_~::~

OKLAHOMA

Current Components

g~~i~. ~~~:~I~!C.

UTAH
Hall-Mark Electronics Corp.
2265 So. 1300 West

l:'~~~e~;i7~~7'!J~ro

215 Marcus Boulevard

Tulsa, Oklahoma 74146

~~tftf:~i;6~.~~ 11788

PHONE: 916·664-11812

l:'~8N~ii8b,~~.~8'c18 84119

OREGON
Western Micro
1800 N.W. 189th Place #3300

~a~~~~d~~:n~~::O:~

PHONE: 312-860-3800

Jaco
222 Andover Street

FAX: 516-273-2801

Milgray Electronics, Inc.
378 Boston Post Road

Mar-Con
4836 Main Street
Skokie, Illinois 60078
PHONE: 312-875-6450

~~~~~~~17:f3:setts 01887

Hall-Mark Electronics Corp,
101 Comac Street
Ronkonkoma, New York 11779
PHONE: 516·737·0600

Hall-Mark Electronics Corp.
3161 S.w. 15th St.

~'8~~03~~_~~~~da 33069
Milgray ElectroniCS, Inc.
1850 Lee Road, Suite 104
Winter Park, Florida 32789
PHONE: 305-647-5747
800-327·5262

PHONE: 617·935-9n7

~"!~V:I~~~~S'

Inc.

FAX: 617·273·1942
MICHIGAN
Advent Electronics
24713 Crestview Court

~~I~~~~~~~!CS,

Inc.

~wg~nt:~1~~_:~igan 48018 ~Wgtra:d:~~2e:~~~

Hall-Mark Electronics Corp.
4275 W. 96th Street
Indianapolis, Indiana 46268
PHONE: 317-872-8875
KANSAS
Hall-Mark Electronics Corp.
10815 Lakeview Drive
Lenexe, Kansas 66215
PHONE: 913·888·4747

~J~r~eE~e~~~ig~;~c.
Overland Park, Kansas 66202
PHONE: 913·236·6800

GEORGIA
Hall-Mark Electronics Corp,
6410 Atlantic Blvd.
Suite 115

MARYLAND
Hall-Mark Electronics Corp.
10240 Old Columbia Road

~~~~~'4~~~~~

~~~~~~a3~~91~_9i:J046

MINNESOTA
Hall-Mark Electronics Corp.
10300 Valley View Rd.
Suite 101
Eden Prairie, Minnesota 55344
PHONE: 612·941·2600

11735

~~It~~r:~:~i~:,

Inc.

Pittsford, New York 14534
PHONE: 716·385·9330
Nu Horizons
6000 New Horizons Blvd.

MISSOURI
Hall-Mark Electronics Corp.
13750 Shoreline Drive
Earth City, Missouri 63045
PHONE: 314·291·5350

~~m;~~e51"&.i!i~0
NORTH CAROLINA
Hall-Mark Electronics Corp,
5237 North Blvd. Suite 0

NEW JERSEY
Hall-Mark Electronics Corp,
107 Fairfield Road
Suite 18
Fairfield, New Jersey 07006
PHONE: 201·575-4415

~~~~~: ~f~~~~a 27604

OHIO
Applied Data Management
435 Dayton Street
Cincinnati, Ohio 45214
PHONE: 513·579·8108

Hall-Mark Electronics Corp.
11000 Midlantic Drive

~~~~~i~~3t~90d 08054

FAX: 713·240-6968

FAX: 801·972-3446

~~~V:~~~O~~i~~2=06
Radar Electric Co., Inc.
704 SE. Washington
Portland, Oregon 97214
PHONE: 503-232·3404
FAX: 503-235·0428

FAX: 516·752·9670
INDIANA
Advent Electronics
8446 Moller Road
Indianapolis, Indiana 46268
PHONE: 317-872·4910

Austin, Texas 78758

~~~~~~1U:.~_~o1rrk 13057

Billerica, Massachusetts 01801

Wood Dale, Illinois 60191

Hall-Mark Electronics Corp.
7648 Southland Blvd.
Suite 100
Orlando, Florida 32809
PHONE: 305·855-4020

PHONE: 512·835-0220

PHONE: 214-733·4300

Quality Components. Inc.
1005 Industrial Blvd.

ILLINOIS
Hall-Mark Electronics Corp.
210 Mittel Drive

Milgray Electronics, Inc.
765 Route 83, Ste. 123
Bensenville, Illinois 80106
PHONE: 312-350-0490

Quality Components. Inc.
2120-M Breaker lane

~i~~ra~o~I:~~~:dlnc.

CONNECTICUT
Hall-Mark Electronics Corp.
Barnes Industrial Park W.

FLORIDA
Hall-Mark Electronics Corp.
15301 Roosevelt Blvd.
Suite 303
Clearwater, Florida 33520
PHONE: 813-530-4543
FAX: 813-535-3665

Hall-Mark Electronics Corp.
5821 Harper Road
Solon, Ohio 44139
PHONE: 216-349·4632

PD. Box 819

Addison, Texas 75001

Cleveland, Ohio 44131
PHONE: 216-477·1520
800-321-0006

~~~"N:arj~~2i~404

~~~2~: ~~~~i~~~77

~~5~~ker~~:~~~7:' Inc.

NEW YORK
ADD Electronics
7 Adler Drive

FAX: 303·790-4991

PHONE: 203·269-0100

Hall-Mark Electronics Corp.
400 E. Wilson Bridge Road
Suite S
Worthington, Ohio 43085
PHONE: 614-888·3313

PENNSYLVANIA
QED Electronics, Inc.
805 N. Bethlehem Pike
Box 847

~~~~E~~~:~S::'::~7
TEXAS
Hall-Mark Electronics Corp.
12211 Technology Blvd.
Austin, Texas 187'Zl
PHONE: 512·258-8848
Hall·Mark Electronics Corp.
10375 Brockwood Road
Dallas, Texas 75238
PHONE: 214·553·4300
Hall-Mark Electronics Corp.
8000 Westglen
Houston, Texas 77063
PHONE: 713·781·6100
FAX: 713·953-8420

FAX: 609-235-3381

~~~~ ~I~~r~~~c~r,
Suite 102
Salt Lake City, Utah 84124
PHONE: 801·272·4999
WASHINGTON
Western Microtechnology, Inc.
14636 N.E. 95th Stree1
Redmond, Washington 98052
PHONE: 206-881·6737
FAX: 206·882·2996
Radar Electric Co" Inc,
East 303 Pacific

~Wo~~~, 5":~~~-~~~399202
FAX: 509·456·8069
Radar Electric Co., Inc,
292 Torbett Street
Richland, Washington 99352
PHONE: 509·943·8336
FAX: 509·943·6790
Radar Electric Co., Inc.
168 Western Ave. West
Seattle, Washington 98119
PHONE: 206·282·2511
FAX: 206-282·1596
WISCONSIN
Hall-Mark Electronics Corp.
16255 W. Lincoln Avenue
New Berlin, Wisconsin 52153
PHONE: 414·797·7844

INTERNATIONAL SALES REPRESENTATIVES AND DISTRIBUTORS
BELGIUM
Auriema Belgium S.A.lN.V,
Rue Brognezstraat 172-A
6-1070 Brussels
PHONE: 32·2-523-6295
TELEX: 84621646
BRAZIL
Fllcres
Rua Aurora, 165
CEP .01209. Calxa Pos1aI 18787
San Paulo
PHONE: 011·223·7388
TELEX: 1131298
CANADA
Carsten Electronics ltd,
3791 Victoria Park Avenue #1
Scarborough, Ontario M1W 3K6
PHONE: 416-495-9999
TELEX: 065·26264
Carsten Electronics Ltd.
215 Stafford Road, Unit 106
Nepean, Ontario K2H 9Ct
PHONE: 613·726-9250
ARGENTINA
Electroquimica Delta Ind, Comp.
Timoteo Gordillo 72
COD Postal 1408
Buenos Aires-R
PHONE: 641-3193
TELEX: 21212 AR EDELTA
AUSTRIA
Othmar Lackner
Elektron Bauelement und Gerate
Landstr Haupstr ~
A-l031 Vienna
PHONE: 43-222·75-26-18
AUSTRALIA
Total Electronics
9 Harker Street
Burwood, Victoria 3125
PHONE: 03·288-4044
TELEX: AA31261

Carsten Electronics ltd.
9480 Trans Canada Highway
SI. laurent, Quebec H4S lA7
PHONE: 514-334-8321
Future Electronics, Inc,
5809 Macleod Trail S
Unit 109

~~8~~: ~:\':.~~~o~
Future Electronics, Inc.
82 St. Regis Crescent No.
Downsview, Ontario M3J 123
PHONE: 416·638·4771
TELEX: 610·491·1470
Future Electronics, Inc.
237 Hymus Blvd.

~~~~:a?I~~~bec

Future Electronics, Inc,
Baxter Center
1050 Baxter Road
Ottawa, Ontario K2C 3P2
PHONE: 613·820-8313

HONG KONG
Protech Components Ltd.
Flat 3. 101F Wing Shing Ind Bldg.

~:"N~~~gS~oon

PHONE: 3·255106
TELEX: 38396 PTLD HX

Future ElectroniCS, Inc.
1695 Boundry Road
Vancouver, B.c. V5R 4X7
PHONE: 604-294·1166

DENMARK
DK2750 Ballerup
PHONE: 45·2·658111
TELEX: 85535293
FINLAND
Instrumentarium Elek.
PD, Box 64
SF..Q2631 Espoo 63
PHONE: 35805284320
TELEX: 57124426
FAX: 35805021073
FRANCE
Tekelec Airtronic
Cite Des Bruyeres
Rue Carle Vernet
BP2 92310 Sevres
PHONE: 33·14-5347535
TELEX: 204552F

~~8;rEr~:::a.,n4387

TELEX: AS 39142
FAX: 65·7488694

INDIA

~~":::;n~f~~~:::t!~ Ltd.

Haltronics, Ltd.
1085 North SelVice Rd, E.
Oakville, Ontario l6H lA6
PHONE: 416-844~2121
TELEX: 610-495·2664
FAX: 416·844-0129
Eastern & Western Canada
1-800-367·7949
Central Canada
1-800-367·7955

:"~I:r~~s~~S222

SINGAPORE
Logic Devices Ltd.
No.3, Lorong Bakar Batu
08-04, Brightway Bldg.

near Dipali Cinema Ashram Road
Ahmedabad
PHONE: 40916(0) 443488(R)
TELEX: 121539 TRCE-IN
ISRAEL
ROT Electronics Engr. ltd.
IIrIDIM Advanoed Technologies Pk.
Neve Sharat
Tel Aviv
PHONE: 972-3492187, 188, 191
TELEX: 371452 or 92233551

SOUTH AFRICA
Eagle Electric
31-41 Hout Street
Capetown 8000
Republic of South Africa
PHONE: 451421
TELEX: 5·21713
SOUTH KOREA
Kortronics Enterprises
Room 307, 8-9
#604-01, Gura-Dong, Gura-gu
Seoul
PHONE: 634-5497
TELEX: MICROS K28484

TAIWAN
Sertek International
3 FL No, 135
Chien Kuo N, Road, Sec. 2
Taipei
PHONE: 02·501·0055
TELEX: 23758 SERTEK
UNITED KINGDOM
Golden Gate
Winchester House
Gardner Road
Maidenhead
Berks SL6 7RL
PHONE: 44-628-783631
TELEX: 846263 Golden G
FAX: 44-628·71120
Manhattan Skyline
Manhattan House

~~13:n~~:3,

Berkshire Sl6 808
PHONE: 44-628-75851
TELEX: 851·847896

ITALY
Dott. Ing. Giuseppe De Mico SPA
Viale Vittorio Veneto 8
20060 Cassina De Pe9chi
Milano
PHONE: 02·95·20-551
TELEX: 330869

WEST GERMANY
SPAIN
Atlantik Elektronik Gmbh
Amitron S.A,
Fraunhoferstr, 11A
Avenida de Valladolid, 47A
D~8033 Martinsried
28008 Madrid
PHONE: 247·93·131248·58·63 PHONE: 49·89·8570000
TELEX: 5215111 ALEC D
TELEX: 45550 AMIT·E

NEDERLAND
Auriema Nederland BV
Doornakkersweg 26
5642MP Eindhoven
PHONE: 31-40-816565
TELEX: 84451992

SWEDEN
NAXAB
Box 4115
17104 Solna
PHONE: 08-98-51-40
TELEX: 17912

NORWAY
Henaco AJS
Box 126, Kaldbakken
Trondheimsveien 436
Oslo 9
PHONE: 47·2·16210
TELEX: 76716 Hanac N

SWITZERLAND
Datacomp AG
Silbernstrasse 10
CH-8593 Dietikon
Zurich, Switzerland
PHONE: 41·1-7405140
TELEX: 827750 DACO
FAX: 1·7413423

H9R 5C7
PHONE: 514-694-7710

775

Beka Electronics Gmbh
Industriestrasse 39-43
0.2000 Wedel
PHONE: 49-410384061
TELEX: 2789582
Tekelec Aitronic Gmbh
Kapauzinerstrasse 9
8000 Munich 2
PHONE: 49-89·51640
TELEX: 522241

STANDARD MICROSVSTEMS
CORPORATION

APPLICATION AND
TECHNICAL NOTE DIRECTORY

DATA COMMUNICATIONS
NUMBER: TITLE:

FLOPPY DISK/HARD DISK
USE WITH
PART
NUMBERS:

NUMBER: TITLE:

USE WITH
PART
NUMBERS:

TN6-1

Principles of Digital FI~PY
Disk Data Separation sing
FDC9216, FDC9229 or
FDC9266

FDC9216
FDC9229
FDC9266

TN6-2

Improved Functionally
Simplifies Disk Controller
Design

HDC9224

COM1553A
COM1553B

TN6-3

FDC765A Circuit
Recommendation

FDC765A
FDC9229

VLSI Circuit Provides
Complete Controller for
Token-Pass Systems

COM9026
COM9032

TN6-5

Programming the HDC9224
Universal Disk Controller

HDC9224

TN5-6

Low Cost Hi~h Performance
Token Pass AN

COM9026
COM9032

TN6-6

Pr08ramming the FDC765A,
FD 9266 and FDC9267 .

FDC765A
FDC9266
FDC9267

TN5-7

COM7210 GPIB-488 Talker/
Listener Controller

COM7210

TN6-7

HDC9224 Programmers
Reference Card

HDC9224
HDC9225
HDC9226

TN5-1

Using the COM8004 for High COM8004
Data Integrity in Bit Oriented COM5025
Protocols

TN5-2

Using the COM9026 Local
Area Controller and the
COM9032 Local Area
Network Transceiver

COM9026
COM9032

TN5-3

MIL-STD-1533A and MILSTD-1553B Overview

TN5-5

MAGAZINE REPRINTS

DISPLAY PRODUCTS
AN1-7

Horizontal Scrolling with the
CRT5037 VTAC®

AN4-1

CRT9006 Single Row Buffer CRT9006
Enhances Processor
Through-put

AN4-3

Programming and Interfacing CRT9006
to the CRT9007
CRT9007
CRT9021
CRT9212
Next Generation CRT
CRT9006
CRT9007
Systems
CRT9021
CRT9212

AN4-4

AN4-5
TN4-2

Using the CRT97C11 in an
Alphanumeric Terminal
CRT9007 VPAC
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