1988_Supertex_Databook 1988 Supertex Databook

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01

·

'-.

1225 Bordeaux Drive • Sunnyvale, California 94088-360 7

Supertex Inc. Life Support Policy
As a general policy, Supertex Inc.. does not recommend the use of any of its products in life support applications where
the failure or malfunction of the Supertexproduct can be reasonably expected to cause failure of the life support device
or to significantly affect its safety or effectiveness. Supertex will not knowingly sell its products for use in such applications
unless it receives an adequate "products liability indemnification insurance agreement", satisfactory to Supertex, stating
that the risks of injury or damage have been minimized, that the customer assumes all such risks, and that the liability of
Supertex is adequately covered in the customer's insurance policy.
Examples of devices considered to be life support devices are neonatal oxygen analyzers, nerve stimulators (for any use),
autotransfusion devices, blood pumps, defibrillators, arrhythmia detectors and alarms, pacemakers, hemodialysis
systems, peritoneal dialysis systems, ventilators of all types, infusion pumps, and any other devices designated as "critical"
by the FDA. The above are representative examples only and are not intended to be conclusive on any other life support
device.

ro-'neral
'een carefully checked and is believed to be reliable; however, no responsibility is assumed for possible
'acies. Specifications are subject to change without notice.
"e responsibility for use of circuitry described; no circuit patent licenses are implied; and Supertex
'1ge said circuity at any time without notice. Liability of Supertex to circuits it manufactures is
• such circuits ifthey are determined to be defective due to workmanship and not due to misuse

'1988 by Supertex, Inc. All rights reserved. Printed in the U.S.A.

Alphanumeric Index and Ordering Information

•
)

Company Profile

~

Application Notes

~

Static Handling Procedures and Quality Assurance

..

Process Flow

~

DMOS Product Family

~

N- and P- Channel Low Threshold MOSFETs

..

DMOS Discretes N-Channel

..

DMOS Discretes P-Channel

..

DMOS Arrays and Special Functions

~

HVCMOS High Voltage ICs

~

CMOS Consumer/Industrial Products

~

Lead Bend Options and Surface Mount Packages

~

Package Outlines

,e.

Representatives''''

Table of Contents
Chapter 1
Alphanumeric Index ........................................................................................................................................... 1-1
Product Nomenclature/Ordering Information ..................................................................................................... 1-5

Chapter 2
Company Profile ................................................................................................................................................2-1
Custom Wafer Foundry ......................................................................................................................................2-2

Chapter 3
Application Notes
Power MOS Transistor Electrical Performance ................................................................................................. 3-1
Low-Threshold MOSFETs: Structure, Performance and Applications ............................................................... 3-5
Basics of EL Panel Drive Techniques ................................................................................................................ 3-9
Cascading Encoder-Decoder ...........................................................................................................................3-12
DC-7, ED-5, ED-9, ED-ll Applications ............................................................................................................ 3-15
Encoder-Decoder for Power Line Carrier Remote Control .............................................................................. 3-21

Chapter 4
Static Handling and Testing Techniques for MOS Devices ............................................................................... 4-1
Quality Assurance and Handling Procedures .................................................................................................... 4-2

Chapter 5
Process Flow
HVCMOS Standard Product Flow ......................................................................................................................5-1
DMOS Standard Product Flow ...........................................................................................................................5-2
HVCMOS IC Process Option Flow Chart ...........................................................................................................5-3
DMOS Process Option Flow Chart .................................................................................................................... 5-4

Chapter 6
DMOS Product Family
Understanding MOSFET Data ...........................................................................................................................6-1
DMOS Products .................................................................................................................................................6-6
DMOS Power FETs ...........................................................................................................................................6-8

Chapter 7
N- and P-Channel Low Threshold MOSFETs
TN01A
TNOl L
TN02L
TN05C
TN06A
TNOSC
TNOSL
TP01L
TP02L
TPOSA
TP06C
TP06L

SO, 100V, 3 ohms ................................................................................................................................7-1
20,40V, 1.8 ohms ............................................................................................................................... 7-5
20, 40V, 1.0 ohms ............................................................................................................................... 7-9
200,240V, 10 ohms ..........................................................................................................................7-10
60,100V,1.50hms ...........................................................................................................................7-14
200,240,6 ohms ..............................................................................................................................7-18
20, 40V, 0.75 ohms ...........................................................................................................................7-22
-20, -40V, 4.0 ohms ...........................................................................................................................7-2S
-20, -40V, 2.0 ohms ........................................................................................................................... 7-30
-SO, -100V, 3.5 ohms ......................................................................................................................... 7-31
-160,-200V, 12 ohms ........................................................................................................................ 7-35
-20, -40V, 2.0 ohms ........................................................................................................................... 7-39

Chapter 8
DMOS Discretes - N-Channel
2NSS59 35V, 1.8 ohms ...................................................................................................................................8-1
2NSSSO/2NS6S1 60V, 3.0 ohms; 90V, 40 ohms ............................................................................................. 8-3
2N7000 SOY, 5 ohms ................................................................................................•.....................................8-5
2N7007 240V, 45 ohms ..................................................................................................................................8-7
2N7008 SOY, 7.5 ohms ...................................................................................................................................8-9
iRF510/iRF511/1RF512/1RF513 100, SOY; 0.6, 0.8 ohms ............................................................................ 8-11

v

IRF520llRF52111RF522/1RF523/R520/R521 100, 60V; 0.3, 0.4 ohms ......................................................... 8-13
IRF531/R531 60V, 0.18 ohms ......................................................................................................................8-15
VN01A 40,60, 90V; 3 ohms ......................................................................................................................... 8-17
VN01C 160, 200V; 10 ohms .........................................................................................................................8-21
VN02A 40, 60, 1OOV; 2 ohms ....................................................................................................................... 8-25
VN02C 160, 200V; 6 ohms ...........................................................................................................................8-29
VN03D 350, 400V; 2.5 ohms ...............................................................:........................................................ 8-33
VN03E 450, 500V; 4 ohms ...........................................................................................................................8-37
VN03F 550, 600V; 6 ohms ..........................................................................................................................8-41
VN0300 30V, 1.2 ohms ................................................................................................................................8-45
VN05D 350, 400V; 35 ohms .........................................................................................................................8-47
VN05E 450, 500V; 60 ohms ......................................................................................................................... 8-51
VN06D 350, 400V; 10 ohms .........................................................................................................................8-53
VN06E 450, 500V; 16 ohms ......................................................................................................................... 8-57
VN06F 550, 600V; 20 ohms .........................................................................................................................8-61
VN0606NN0610 60V; 3, 5 ohms ................................................................................................................. 8-65
VN0808 80V, 4 ohms ...................................................................................................................................8-67
VN10K 60V, 5 ohms .....................................................................................................................................8-69
VN11A 60, 100V; 0.7 ohms ..........................................................................................................................8-73
VNllC 160,200V;30hms ...........................................................................................................................8-77
VN12A 40,60, 100V; 0.3 ohms ....................................................................................................................8-81
VN12C 160, 200V; 1 ohm ............................................................................................................................8-85
VN1206NN1210 120V; 6,10 ohms .............................................................................................................8-89
VN13A 40,60, 100V; 8 ohms .......................................................................................................................8-91
VN13C 160, 200V; 40 ohms ............................................................................................................;............ 8-95
VN1706NN1710 170V; 6,10 ohms ..............................................................................................................8-99
VN2010L 200V, 100hms ...........................................................................................................................8-101
VN22A 60, 1OOV; 0.3 ohms ........................................................................................................................8-103
VN2222 60V, 7.5 ohms ..........................................................................................................,.................... 8-105
VN2406NN2410 240V; 6,10 ohms ...........................................................................................................8-107
VN3515UVN4012L 350, 400V; 15 ohms ................................................................................................... 8-109
VN6035L 600V, 35 ohms ........................................................................................................................... 8-111

Chapter 9
DMOS Dlscretes - P-Channel
IRF9521/R9521 -60V; 0.6 ohms ......................................................................................................................9-1
IRF9522!IRF9523/R9522!R9523 -100, -60V; 0.8 ohms ................................................................................. 9-3
VP01A -40, -60, -90V; 8 ohms .......................................................................................................................9-5
VP01C -160, -200V; 25 ohms ........................................................................................................................9-9
VP02A -40, -60, -100V; 4 ohms ................................................................................................................... 9-13
VP02C -160, -200V; 16 ohms ......................................................................................................................9-17
VP03D -350, -400V; 6 ohms ........................................................................................................................ 9-21
VP03E -450, -500V; 7.5 ohms ...................................................................................................................... 9-25
VP0300 -30V, 2.5 ohms ................................................................................................................................9-29
VP05D -350, -400V; 75 ohms ...................................................................................................................... 9-31
VP05E -450, -500V; 125 ohms .....................................................................................................................9-35
VP06D -350, -400V; 25 ohms ...................................................................................................................... 9-39
VP06E -450, -500V; 20 ohms ..........................................................................................................,............ 9-43
VP0808NP1008 -80, -100V; 50 ohms .........................................................................................................9-47
VPllA -60, -100V; 2 ohms ...........................................................................................................................9-49
VPllC -160, -200V; 5 ohms ........................................................................................................................9-53
VP12A -40, -60, -100; 0.8 ohms ...................................................................................................................9-57
VP12C -160, -200V; 2.5 ohms ..................................................................................................................... 9-61
VP13A -40, -60, -100V; 25 ohms ................................................................................................................. 9-65
VP13C -160, -200V; 100 ohms .................................................................................................................... 9-69

Chapter 10
DMOS Arrays and Special Functions
MOSFET Array Selector Guide ........................................................................................................................ 10-1
AN01, 8 N-Channel Monolithic Array; 160, 200, 300, 320, 400V; 350 ohms ............................................... 10-3
AP01, 8 P-Channel Monolithic Array; -160, -200, -300, -320, -400V; 700 ohms .......................................... 10-8
HT01, 8-Channel Logic to High Voltage Level Translator .............................................................................. 10-13

vi

TC0604WG 40V, 2.75 ohms ...................................................................................................................... 10-17
TN0604WG 40V, 0.75 ohms ...................................................................................................................... 10-18
TN0606N6fTN0606N7 60V, 1.5 ohms ....................................................................................................... 10-19
TP0604WG -40V, 2.0 ohms ....................................................................................................................... 10-20
TP0606N6/TP0606N7 -60V, 3.5 ohms ....................................................................................................... 10-21
T03001N03001N07254
N- and P-Channel Ouad Power MOSFET Array; 40, 20V; 3 ohms ............... 10-22
VC0106N6NC0106N7 60V, 11 ohms ........................................................................................................ 10-25
VC0206N6NC0206N7 60V, 6 ohms .......................................................................................................... 10-2S
VN0104NSNN09104N7NN010SN6NN010SN7 40, 60V; 3 ohms ............................................................. 10-27
VN010SNENN0109NE SO, 90V; 3 ohms ................................................................................................... 10-28
VN0204N6NN0204N7NN0206N6NN020SN7 40,SOV; 2 ohms ................................................................ 10-29
VN2l06NFNN2ll0NF 60, 100V;30hms .................................................................................................. 10-30
VP0104NSNP0104N7NP010SNSNP010SN7 -40, -SOY; 8 ohms ............................................................. 10-32
VP0204N6NP0204N7NP0206N6NP0206N7 -40, -60V; 4 ohms ............................................................. 10-33
VOl 000 SOY; 5.5 ohms .............................................................................................................................. 10-34
V0100l 30V, 1.0 ohms .............................................................................................................................. 10-39
VOl 004 60V, 3.5 ohms ............................................,' ................................................................................. 10-41

Chapter 11
HVCMOS High Voltage ICs
HVCMOS Selector Guide ................................................................................................................................ 11-1
HVOl lS-Channel Matrix TFEl Panel Display Column Driver ...................................................................... 11-3
HV02 lS-Channel Matrix TFEl Panel Display Row Driver ........................................................................... 11-9
HV03/HV05 64-Channel Serial to Parallel Converter with Open Drain Outputs ......................................... 11-14
HV04/HV06 64-Channel Serial to Parallel Converter with High Voltage CMOS Outputs ........................... 11-21
HV04H/HV06H S4-Channel Serial to Parallel Converter with Ruggedized High Voltage Outputs .............. 11-28
HV08 24-Channel Matrix TFEl Panel Display Column Driver .................................................................... 11-35
HV10 4-Channel High Voltage Switch ......................................................................................................... 11-39
HV12 8-Channel High Voltage Switch ......................................................................................................... 11-44
HV13 Dual 4-Channel High Voltage Switch with Decoder .......................................................................... 11-50
HV14 8-Channel High Voltage Switch with Decoded Switch Selection ...................................................... 11-55
HV15 1 of 8 Decoder 8-Channel High Voltage Switch ................................................................................ II-SO
HV1S 8-Channel High Voltage Switch ......................................................................................................... 11-S5
HV17 4-Channel High Voltage Switch ......................................................................................................... 11-72
HV18 8-Channel High Voltage Switch ......................................................................................................... 11-77
HV30 High Voltage 7-Segment latch/Decoder/El-Display Driver .............................................................. 11-84
HV341/HV343/HV345/HV348 High Voltage Analog Switches .................................................................... 11-88
HV41/HV42 32-Channel Serial to Parallel Converter with P-Channel Open Drain Outputs ....................... 11-95
HV45/HV46 32-Channel Serial to Parallel Converter with P-Channel Open Drain Outputs ..................... 11-100
HV500 32-Channel AC Plasma Display Driver ......................................................................................... 11-105
HV510 32-Channel AC Plasma Display Driver ......................................................................................... 11-110
HV51/HV52 32-Channel Serial to Parallel Converter with Open Drain Outputs ....................................... 11-115
HV53/HV54 32-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs ..................... 11-120
HV55/HV56 32-Channel Serial to Parallel Converter with P-Channel Open Drain Outputs ..................... 11-125
HV57/HV58 32-Channel Serial to Parallel Converter with Push-Pull Outputs .......................................... 11-130
HVSO 32-Channel ± 40V liquid Crystal Display Driver ............................................................................. 11-135
HV6810 10-Channel Serial-Input latched Display Driver ......................................................................... 11-140

Chapter 12
CMOS Consumer/Industrial Products
DC-7, Programmable Data Doder .................................................................................................................... 12-1
ED-5/ED-9/ED-l1 /ED-15, Programmable Encoder/Decoder ......................................................................... 12-10
ET13, Programmable Encoder ...................................................................................................................... 12-19
MPS90/S92/MPS91/693, Processor Supervisory Circuits .............................................................................. 12-24
SD2, CMOS Photo-electric Smoke Detector/Integrated Circuit ..................................................................... 12-39
SD3A, Ionization Chamber Type Smoke Detector Circuit ............................................................................. 12-4S

Chapter 13
Lend Bend Options and Surface Mount Packages
Surface Mount Packages ................................................................................................................................. 13-1
lead Bend Options .......................................................................................................................................... 13-3
TO-92 Taping Specifications and Winding Styles ............................................................................................ 13-S

vii

Chapter 14
Package Outlines
TO-3, TO-39, TO-92 .................................................................................:............................... ,.................•.... 14-1
TO-52, TO-220 ................................................................................................................................................. 14-2
14-Lead Ceramic Side-Brazed, 16-Lead Ceramic Side-Brazed ...........................................•.......................... 14-3
18-Lead Ceramic Side-Brazed, 20-Lead Ceramic Side-Brazed ...................................................................... 14-4
24-Lead Ceramic Side-Brazed, 28-l,.ead Ceramic Side-Brazed ...................................................................... 14-5
40-Lead Ceramic Side-Brazed ......................................................................................................................... 14-6
14-Lead CERDIP, 16-Lead CERDIP ............................................................................................................... 14-7
18-Lead CERDIP, 20-Lead CERDIP ............................................................................................................... 14-8
24-Lead CERDIP, 28-Lead CERDIP ............................................................................................................... 14-9
40-Lead CERDIP, 14-Lead Plastic Dual-In-Line ........................................ ,................................................... 14-10
16-Lead Plastic Dual-In-Line, 18-Lead Plastic Dual-In-Line .......................................................................... 14-11
20-Lead Plastic Dual-In-Une, 24-Lead Plastic Dual-In-Line .......................................................................... 14-12
28-Lead Plastic Dual-In-Une, 40-Lead Plastic DIP .................................... :................................................... 14-13
28-Lead Plastic Quad "J" Bend, 20-Lead SOW ............................................................................................. 14-14
16-Terminal C/C, Type "C" Leadless 20-Terminal Chip Carrier ..................................................................... 14-15
36-Leaded C/C Bend Option "CR", 36-Leaded C/C Bend Option "CF" ......................................................... 14-16
36-Leaded C/C Bend Option "CS", 36-Leaded C/C Bend Options ................................................................ 14-17
84-Terminal Ceramic C/C Type "B", 84-Lead Quad Plastic Chip Carrier ...................................................... 14-18
44-Lead Quad CERPAC "DJ", 80-Lead Quad CERPAC "DG" ...................................................................... 14-19
44-Lead Plastic "J" - Bend, 80-Lead Quad Plastic "PG" ................................................................................ 14-20

Chapter 15
Representatives/Distributors .............................................................................................................................15-1

viii

"

!iupertex inc.

-

Alphanumeric Index
Device
2N6659
2N6660
2N6661
2N7000
2N7007

Page #
8-1
8-3
8-3
8-5
8-7

Device

Page #

DC7X
ED5P
ED9P
ED9WG
ED11P

12-1
12-10
12-10
12-10
12-10

HV0406T
HV0406X
HV0408DG
HV0408LC
HV0408PG

11-21
11-21
11-21
11-21
11-21

HV06H06LC
HV06H06PG
HV06H06PJ
HV06H06T
HV06H06X

11-28
11-28
11-28
11-28
11-28

Device

Page #

Device

Page #

2N7008
AN0116NA
AN0116NB
AN0116ND
AN0116WG

8-9
10-3
10-3
10-3
10-3

ED11WG
ED15J
ED15P
ED15WG
ET13P

12-10
12-10
12-10
12-10
12-19

HV0408PJ
HV0408T
HV0408X
HV04H06DG
HV04Y06LC

11-21
11-21
11-21
11-28
11-28

HV06H08DG
HV06H08LC
HV06H08PG
HV06H08PJ
HV06H08T

11-28
11-28
11-28
11-28
11-28

AN0120NA
AN0120NB
AN0120ND
AN0130NA
AN0130NB

10-3
10-3
10-3
10-3
10-3

ET13WG
HT0130D
HT0130LC
HT0130P
HT0130WG

12-19
10-13
10-13
10-13
10-13

HV04H06PG
HV04H06PJ
HV04H06T
HV04H06X
HV04H08DG

11-28
11-28
11-28
11-28
11-28

HV06H08X
HV08DJ
HV08X
HV1014C
HV1014P

11-28
11-35
11-35
11-39
11-39

AN0130ND
AN0132NA
AN0132NB
AN0132ND
AN0132WG

10-3
10-3
10-3
10-3
10-3

HT0130X
HV01C
HV01CF
HV01CS
HV01CR

10-13
11-3
11-3
11-3
11-3

HV04H08LC
HV04H08PG
HV04H08PJ
HV04H08T
HV04H08X

11-28
11-28
11-28
11-28
11-28

HV1014X
HV1016C
HV1016P
HV1016X
HV1214C

11-39
11-39
11-39
11-39
11-44

AN0140NA
AN0140NB
AN0140ND
AN0140WG
AP0116NA

10-3
10-3
10-3
10-3
10-8

HV01LC
HV01X
HV02C
HV02CF

11-3
11-3
11-9
11-9

HV0522DG
HV0522LC
HV0522PG
HV0522PJ
HV0522T

11-14
11-14
11-14
11-14
11-14

HV1214P
HV1214X
HV1216C
HV1216P
HV1216X

11-44
11-44
11-44
11-44
11-44

AP0116NB
AP0116ND
AP0116WG
AP0120NA
AP0120NB

10-8
10-8
10-8
10-8
10-8

HV02CS
HV02CR
HV02LC
HV02X
HV0322DG
HV0322LC

11-9
11-9
11-9
11-9
11-14
11-14

HV0522X
HV0530DG
HV0530LC
HV0530PG
HV0530PJ

11-14
11-14
11-14
11-14
11-14

HV1314C
HV1314P
HV1314X
HV1316C
HV1316P

11-50
11-50
11-50
11-50
11-50

AP0120ND
AP0130NA
AP0130NB
AP0130ND
AP0132NA

10-8
10-8
10-8
10-8
10-8

HV0322PG
HV0322PJ
HV0322T
HV0322X
HV0322LC

11-14
11-14
11-14
11-14
11-14

HV0530T
HV0530X
HV0606DG
HV0606LC
HV0606PG

11-14
11-14
11-21
11-21
11-21

HV1316X
HV1414C
HV1414P
HV1414X
HV1416C

11-50
11-55
11-55
11-55
11-55

AP0132NB
AP0132ND
AP0132WG
AP0140NA
AP0140NB

10-8
10-8
10-8
10-8
10-8

HV0330DG
HV0330LC
HV0330PG
HV0330PJ
HV0330T

11-14
11-14
11-14
11-14
11-14

HV0606PJ
HV0606T
HV0606X
HV0608DG
HV0608LC

11-21
11-21
11-21
11-21
11-21

HV1416P
HV1416X
HV1514C
HV1514P
HV1514X

11-55
11-55
11-60
11-60
11-60

AP0140ND
AP0140WG
DC7P
DC7PJ
DC7WG

10-8
10-8
12-1
12-1
12-1

HV0330X
HV0406DG
HV0406LC
HV0406PG
HV0406PJ

11-14
11-21
11-21
11-21
11-21

HV0608PG
HV0608PJ
HV0608T
HV0608X
HV06H06DG

11-21
11-21
11-21
11-21
11-28

HV1516C
HV1516P
HV1516X
HV1614C
HV1614CS

11-60
11-60
11-60
11-65
11-65

Device

Page #

Device

Page #

Device

Page #

Device

Page #

HV1614P
HV1614PJ
HV1614X
HV1616C
HV1616CS

11-65
11-65
11-65
11-65
11-65

HV4222DJ
HV4222PJ
HV4222X
HV4522DJ
HV4522PJ

11-95
11-95
11-95
11-100
11-100

HV5708DJ
HV5708PJ
HV5708X
HV5808DJ
HV5808PJ

11-130
11-130
11-130
11-130
11-130

RBMP693D
RCMP690D
RCMP691D
RCMP692D
RCMP693D

12-24
12-24
12-24
12-24
12-24

HV1616P
HV1616PJ
HV1616X
HV1714C
HV1714P

11-65
11-65
11-65
11-72
11-72

HV4522X
HV4530DJ
HV4530PJ
HV4530X
HV4622DJ

11-100
11-100
11-100
11-100
11-100

HV5808X
HV6008D
HV6008P
HV6008PG
HV6008X

11-130
11-135
11-135
11-135
11-135

SD2P
SD3AP
TC0604WG
TN0102N2
TN0102N3

12-39
12-46
10-17
7-5
7-5

HV1714X
HV1716C
HV1716P
HV1716X
HV1814C

11-72
11-72
11-72
11-72
11-77

HV4622PJ
HV4622X
HV4630DJ
HV4630PJ
HV4630X

11-100
11-100
11-100
11-100
11-100

HV6810P
HV6810WGS
IRF510
IRF511
IRF512

11-140
11-140
8-11
8-11
8-11

TN0102ND
TN0104N2
TN0104N3
TN0104ND
TN0106N2

7-5
7-5
7-5
7-5
7-1

HV1814CS
HV1814P
HV1814PJ
HV1814X
HV1816C

11-77
11-77
11-77
11-77
11-77

HV500D
HV500DJ
HV500P
HV500PJ
HV500X

11-105
11-105
11-105
11-105
11-105

IRF513
IRF520
IRF521
IRF522
IRF523

8-11
8-13
8-13
8-13
8-13

TN0106N3
TN0106ND
TN0110N2
TN0110N3
TN0110ND

7-1
7-1
7-1
7-1
7-1

HV1816CS
HV1816P
HV1816PJ
HV1816X
HV30C

11-77
11-77
11-77
11-77
11-84

HV501D
HV501DJ
HV501P
HV501PJ
HV501X

11-110
11-110
11-110
11-110
11-110

IRF531
IRF9521
IRF9522
IRF9523
MP690MD

8-15
9-1
9-3
9-3
12-24

TN0202N2
TN0202N3
TN0204N2
TN0204N3
TN0520N2

7-9
7-9
7-9
7-9
7-10

HV30D
HV30P
HV30X
HV341D
HV341MD

11-84
11-84
11-84
11-88
11-88

HV5122DJ
HV5122PJ
HV5122X
HV5222DJ
HV5222PJ

11-115
11-115
11-115
11-115
11-115

MP690MP
MP690P
MP691MD
MP691MP
MP691MWG

12-24
12-24
12-24
12-24
12-24

TN0520N3
TN0520ND
TN0524N2
TN0524N3
TN0524ND

7-10
7-10
7-10
7-10
7-10

HV341MWG
HV341P
HV341WG
HV341X
HV343D

11-88
11-88
11-88
11-88
11-88

HV5222X
HV5306DJ
HV5306PJ
HV5306X
HV5308DJ

11-115
11-120
11-120
11-120
11-120

MP691P
MP691WG
MP691X
MP692MD
MP692MP

12-24
12-24
12-24
12-24
12-24

TN0602N2
TN0602N3
TN0602ND
TN0604N2
TN0604N3

7-22
7-22
7-22
7-22
7-22

HV343MD
HV343MWG
HV343P
HV343WG
HV343X

11-88
11-88
11-88
11-88
11-88

HV5308PJ
HV5308X
HV5406D
HV5406PJ
HV5406X

11-120
11-120
11-120
11-120
11-120

MP692P
MP693MD
MP693MP
MP693MWG
MP693P

12-24
12-24
12-24
12-24
12-24

TN0604ND
TN0604WG
TN0606N2
TN0606N3
TN0606N5

7-22
10-18
7-14
7-14
7-14

HV345D
HV345MD
HV345MWG
HV345P
HV345WG

11-88
11-88
11-88
11-88
11-88

HV5408DJ
HV5408PJ
HV5408X
HV5522DJ
HV5522PJ

11-120
11-120
11-120
11-125
11-125

MP693WG
MP693X
R520
R521
R531

12-24
12-24
8-13
8-13
8-15

TN0606N6
TN0606N7
TN0606ND
TN0610N2
TN0610N3

10-19
10-19
7-14
7-14
7-14

HV345X
HV348D
HV348MD
HV348MWG
HV348P

11-88
11-88
11-88
11-88
11-88

HV5522X
HV5530DJ
HV5530PJ
HV5530X
HV5622DJ

11-125
11-125
11-125
11-125
11-125

R9521
R9522
R9523
RBHV341D
RBHV343D

9-1
9-3
9-3
11-88
11-88

TN0610N5
TN0610ND
TN0620N2
TN0620N3
TN0620N5

7-14
7-14
7-18
7-18
7-18

HV348WG
HV348X
HV4122DJ
HV4122PJ
HV4122X

11-88
11-88
11-95
11-95
11-95

HV5622PJ
HV5622X
HV5630DJ
HV5630PJ
HV5630X

11-125
11-125
11-125
11-125
11-125

RBHV345D
RBHV348D
RBMP690D
RBMP691D
RBMP692D

11-88
11-88
12-24
12-24
12-24

TN0620ND
TN0624N2
TN0624N3
TN0624N5
TN0624ND

7-18
7-18
7-18
7-18
7-18

1-2

Device

Page #

Device

Device

Page #

Page #

Device

Page #

TP0102N2
TP0102N3
TP0102ND
TP0104N2
TP0104N3

7-26
7-26
7-26
7-26
7-26

VN0106ND
VN0106NE
VN0109N2
VN0109N3
VN0109N5

8-17
10-28
8-17
8-17
8-17

VN0355ND
VN0360N1
VN0360N5
VN0360ND
VN0535N2

8-41
8-41
8-41
8-41
8-47

VN1116N5
VN1116ND
VN1120N1
VN1120N2
VN1120N5

8-77
8-77
8-77
8-77
8-77

TP0104ND
TP0202N2
TP0202N3
TP0204N2
TP0204N3

7-26
7-26
7-30
7-30
7-30

VN0109N9
VN0109ND
VN0109NE
VN0116N2
VN0116N3

8-17
8-17
10-28
8-21
8-21

VN0535N3
VN0535ND
VN0540N2
VN0540N3
VN0540ND

8-47
8-47
8-47
8-47
8-47

VN1120ND
VN1204N1
VN1204N2
VN1204N5
VN1204ND

8-77
8-81
8-81
8-81
8-81

TP0602N2
TP0602N3
TP0602ND
TP0604N2
TP0604N3

7-39
7-39
7-39
7-39
7-39

VN0116N5
VN0116ND
VN0120N2
VN0120N3
VN0120N5

8-21
8-21
8-21
8-21
8-21

VN0545N2
VN0545N3
VN0545ND
VN0550N2
VN0550N3

8-51
8-51
8-51
8-51
8-51

VN1206B
VN1206D
VN1206L
VN1206N1
VN1206N2

8-89
8-89
8-89
8-81
8-81

TP0604ND
TP0604WG
TP0606N2
TP0606N3
TP0606N5

7-39
10-20
7-31
7-31
7-31

VN0120ND
VN0204N2
VN0204N5
VN0204N6
VN0204N7

8-21
8-25
8-25
10-29
10-29

VN0550ND
VN0606L
VN0610LL
VN0635N2
VN0635N3

8-51
8-65
8-65
8-53
8-53

VN1206N5
VN1206ND
VN1210B
VN1210D
VN1210L

8-81
8-81
8-89
8-89
8-89

TP0606N6
TP0606N7
TP0606ND
TP0610N2
TP0610N3

10-21
10-21
7-31
7-31
7-31

VN0206N2
VN0206N3
VN0206N5
VN0206N6
VN0206N7

8-25
8-25
8-25
10-29
10-29

VN0635N5
VN0635ND
VN0640N2
VN0640N3
VN0640N5

8-53
8-53
8-53
8-53
8-53

VN1210N1
VN1210N2
VN1210N5
VN1210ND
VN1216N1

8-81
8-81
8-81
8-81
8-85

TP0610N5
TP0610ND
TP0616N2
TP0616N3
TP0616N5

7-31
7-31
7-35
7-35
7-35

VN0210N2
VN0210N3
VN0210N5
VN0216N2
VN0216N3

8-25
8-25
8-25
8-29
8-29

VN0640ND
VN0645N2
VN0645N3
VN0645N5
VN0645ND

8-53
8-57
8-57
8-57
8-57

VN1216N2
VN1216N5
VN1216ND
VN1220N1
VN1220N2

8-85
8-85
8-85
8-85
8-85

TP0616ND
TP0620N2
TP0620N3
TP0620N5
TP0620ND

7-35
7-35
7-35
7-35
7-35

VN0216N5
VN0220N2
VN0220N3
VN0220N5
VN0300B

8-29
8-29
8-29
8-29
8-45

VN0650N2
VN0650N3
VN0650N5
VN0650ND
VN0655N2

8-57
8-57
8-57
8-57
8-61

VN1220N5
VN1220ND
VN1304N2
VN1304N3
VN1306N2

8-85
8-85
8-91
8-91
8-91

TQ3001N6
TQ3001N7
TQ3001NF
VC0106N6
VC0106N7

10-22
10-22
10-22
10-25
10-25

VN0300D
VN0300L
VN0335N1
VN0335N2
VN0335N5

8-45
8-45
8-33
8-33
8-33

VN0655N3
VN0655N5
VN0655ND
VN0660N2
VN0660N3

8-61
8-61
8-61
8-61
8-61

VN1306N3
VN1310N2
VN1310N3
VN1316N2
VN1316N3

8-91
8-91
8-91
8-95
8-95

VC0206N6
VC0206N7
VN0104N2
VN0104N3
VN0104N5

10-26
10-26
8-17
8-17
8-17

VN0335ND
VN0340N1
VN0340N2
VN0340N5
VN0340ND

8-33
8-33
8-33
8-33
8-33

VN0660N5
VN0660ND
VN0808L
VN10KN3
VN10KN9

8-61
8-61
8-67
8-69
8-69

VN1320N2
VN1320N3
VN1706B
VN1706D
VN1706L

8-95
8-95
8-99
8-99
8-99

VN0104N6
VN0104N7
VN0104N9
VN0104ND
VN0106N2

10-27
10-27
8-17
8-17
8-17

VN0345N1
VN0345N2
VN0345N5
VN0345ND
VN0350N1

8-37
8-37
8-37
8-37
8-37

VN1106N1
VN1106N2
VN1106N5
VN1106ND
VN1110N1

8-73
8-73
8-73
8-73
8-73

VN1710B
VN1710D
VN1710L
VN2010L
VN2106ND

8-99
8-99
8-99
8-101
10-30

VN0106N3
VN0106N5
VN0106N6
VN0106N7
VN0106N9

8-17
8-17
10-27
10-27
8-17

VN0350N2
VN0350N5
VN0350ND
VN0355N1
VN0355N5

8-37
8-37
8-37
8-41
8-41

VN1110N2
VN1110N5
VN1110ND
VN1116N1
VN1116N2

8-73
8-73
8-73
8-73
8-77

VN2106NF
VN2110ND
VN2110NF
VN2206ND
VN2206NW

10-30
10-30
10-30
8-103
8-103

1-3

Device

Page #

Device

Device

Page #

Page #

VN2210ND
VN02210NW
VN2222LL
VN2406B
VN2406D

8-103
8-103
8-10S
8-107
8-107

VP0220N3
VP0220NS
VP0300B
VP0300L
VP033SN1

9-17
9-17
9-29
9-29
9-21

VP1106ND
VP1110N1
VP1110N2
VP1110NS
VP1110ND

9-49
9-49
9-49
9-49
9-49

VN2406L
VN2410B
VN2410D
VN2410L
VN3S1SL

8-107
8-107
8-107
8-107
8-109

VP033SN2
VP033SNS
VP033SND
VP0340N1
VP0340N2

9-21
9-21
9-21
9-21
9-21

VP1116N1
VP1116N2
VP1116NS
VP1116ND
VP1120N1

9-S3
9-S3
9-S3
9-53
9-S3

VN4012L
VN603SL
VP0104N2
VP0104N3
VP0104NS

8-109
8-109
9-S
9-S
9-S

VP0340NS
VP0340ND
VP034SN1
VP034SN2
VP034SNS

9-21
9-21
9-2S
9-2S
9-2S

VP1120N2
VP1120NS
VP1120ND
VP1204N1
VP1204N2

9-S3
9-S3
9-S3
9-S7
9-57

VP0104N6
VP0104N7
VP0104N9
VP0104ND
VP0106N2

10-32
10-32
9-S
9-S
9-S

VP034SND
VP03S0N1
VP03S0N2
VP03S0NS
VP03S0ND

9-2S
9-2S
9-2S
9-2S
9-2S

VP1204NS
VP1204ND
VP1206N1
VP1206N2
VP1206NS

9-S7
9-S7
9-S7
9-S7
9-S7

VP0106N3
VP0106N5
VP0106N6
VP0106N7
VP0106N9

9-5
9-S
10-32
10-32
9-S

VPOS3SN2
VPOS3SN3
VP053SND
VPOS40N2
VP0540N3

9-31
9-31
9-31
9-31
9-31

VP1206ND
VP1210N1
VP1210N2
VP1210NS
VP1210ND

9-S7
9-S7
9-S7
9-S7
9-S7

VP0106ND
VP0109N2
VP0109N3
VP0109N5
VP0109N9

9-S
9-S
9-S
9-S
9-S

VP0540ND
VPOS4SN2
VPOS45N3
VPOS4SND
VPOSSON2

9-31
9-3S
9-3S
9-3S
9-3S

VP1216N1
VP1216N2
VP1216NS
VP1216ND
VP1220N1

9-61
9-61
9-61
9-61
9-61

VP0109ND
VP0116N2
VP0116N3
VP0116NS
VP0116ND

9-S
9-9
9-9
9-9
9-9

VPOSSON3
VPOSSOND
VP063SN2
VP063SN3
VP063SNS

9-3S
9-3S
9-39
9-39
9-39

VP1220N2
VP1220NS
VP1220ND
VP1304N2
VP1304N3

9-61
9-61
9-61
9-6S
9-6S

VP0120N2
VP0120N3
VP0120NS
VP0120ND
VP0204N2

9-9
9-9
9-9
9-9
9-13

VP063SND
VP0640N2
VP0640N3
VP0640N5
VP0640ND

9-39
9-39
9-39
9-39
9-39

VP1306N2
VP1306N3
VP1310N2
VP1310N3
VP1316N2

9-65
9-6S
9-6S
9-65
9-69

VP0204NS
VP0204N6
VP0204N7
VP0206N2
VP0206N3

9-13
10-33
10-33
9-13
9-13

VP064SN2
VP0645N3
VP064SNS
VP064SND
VP06S0N2

9-43
9-43
9-43
9-43
9-43

VP1316N3
VP1320N2
VP1320N3
\/01000N6
V01000N7

9-69
9-69
9-69
10-34
10-34

VP0206NS
VP0206N6
VP0206N7
VP0210N2
VP0210N3

9-13
10-33
10-33
9-13
9-13

VP06S0N3
VP06S0NS
VP06S0ND
VP0808B
VP0808L

9-43
9-43
9-43
9-47
9-47

V01001P
V01004J
V01004P
V03001N6
V03001N7

10-39
10-41
10-41
10-22
10-22

VP0210NS
VP0216N2
VP0216N3
VP0216NS
VP0220N2

9-13
9-17
9-17
9-17
9-17

VP1008B
VP1008L
VP1106N1
VP1106N2
VP1106NS

9-47
9-47
9-49
9-49
9-49

V03001NF
V072S4N6
V072S4N7

10-22
10-22
10-22

1-4

"

!iupertex inc.
Product Nomenclature/Ordering
Information

DMOS Proprietary Products

TS

VN0109N3

J

...------------T
FAMILY TYPE

POLARITY

A= Lateral DMOS
Arrays

N = N-Channel

T= Low Threshold
DMOS Discretes

P = P-Channel

V= Vertical DMOS
Discretes & Quads

C = Complementary
(2N &2P)

FAMILY
NUMBER
01
02
03
05
06
11
12
13
21
22

Q = Arrays

PACKAGE TYPE

BVDSS
DIVIDED BY 10
02
04
06
09
10
16
20
24
30
35
40
45
50
55
60
(e.g., 09 = 90V)

Nl
N2
N3
N5
N6
N7
N9
NA
NB
NE
NF
WG
ND
NW

= TO-3
= TO-39
= TO-92
= TO-220
= 14-Pin Plastic DIP
= 14-Pin Ceramic DIP
=TO-52
= 18-Pin Plastic DIP
= 18-Pin Ceramic DIP
= 16-Terminal Ceramic LCC
= 20-Terminal Ceramic LCC
= 20 Lead SOW
= Die in Waffle Pack
= Die in Wafer Form

CMOS Products
Encoder I Decoder
ED - 5 P

(1

T
FAMILY TYPE

NUMBER OF
ADDRESS BITS

PACKAGE TYPE

ED = Programmable
Encoder/Decoder

ED-5
DC-7
ED-9
ED-l1
ET-13
ED-15

PJ

DC = Data Coder
ET = EncoderlTransmitter

= 5
= 7
= 9
= 11
= 13
= 15

1-5

Molded Plastic Surface Mount
J-Lead Chip Carrier
P
Molded Plastic DIP
X
Dice
WG= Small Outline Surface Mount

Smoke Detectors

TF

S D 2 P

FAMILY TYPE

SD = Smoke Detectors

1·

PRODUCT
DESIGNATOR

PACKAGE TYPE

2

P = Molded Plastic DIP
X = Dice

3A

HVIC Products
RBHV0106C

~TT~~
HI-REL

FAMILY TYPE

RB = Hi-Rei 883
type processing

HV = High VoltagelC

RC '" Mil-Temp Testing
only

PRODUCT
DESIGNATOR
01
02
03
04
05
06
10
12
13
14
15
16
17
18
30
41
42
45

46
51
52
53
54
55
56
57
58
60
341
343
345
348
500
501
6810

1-6

ABSOLUTE MAX
VOLTAGE DIVIDED
BY 10
04 14
06 16
08 18
10 20
12 22
(e.g., 22

25
27
30

= 220V)

PACKAGE TYPE

P
C
D
X
LC
CF =
CS =
CR =
DG =
PG =
WG=
DJ
PJ =

Plastic DIP
Ceramic Side Brazed
CERDIP
Dice
LCC Ceramic
Ceramic Leaded Chip
Carriers with Flat Leads
Ceramic Chip CarrierSTD Bent Leads
Ceramic Chip CarrierReverse Bent Leads
CERDIP Gullwing
Plastic Gullwing
SOW Gullwing
Quad CERDIP J Lead
Quad Plastic J Lead

Alphanumeric Index and Ordering Information
Company Profile

Application Notes
Static Handling Procedures and Quality Assurance
Process Flow
DMOS Product Family
N- and p. Channel low Threshold MOSFETs

.1
•
........
....
\1M

DMOS Discretes N-Channel
DMOS Discretes P-Channel
DMOS Arrays and Special Functions
HVCMOS High Voltage ICs
CMOS Consumer/Industrial Products
lead Bend Options and Surface Mount Packages

~
.'1
~

i

Package Outlines
Representatives/Distributors

(1) §upertex inc.
Company Profile
Success Through Innovation
Founded in 1976, Supertex designs and manufactures complex
proprietary and industry-standard integrated circuits (ICs) and
discrete components for a select range of diverse markets,
including the medical, data processing, military, telecommunications, instrumentation, and consumer product industries.
Throughout the years the company has developed advanced
technologies utilizing high-performance Complementary Metal
Oxide Semiconductors (CMOS) and Double-Diffused MOS
(DMOS) processes.

power transistors. These advanced HVCMOS ICs, as well as
Supertex's families of CMOS and DMOS products, provide performance and cost benefits to give customers a competitive edge
in developing new products.
Supertex now focuses on two process technologies, DMOS and
HVCMOS, which allow for a varied product mix of integrated
circuits and MOS powerfield effect transistors (FETs) and arrays.
The company's products are targeted for application-specific
markets, such as ultrasound imaging for medical electronics, flatpanel display terminals, and high reliability products for military
systems. Supertex has demonstrated technological leadership in
specific product areas that has earned the company international
as well as domestic recognition.

In 1980, Supertex pioneered SMART POWER high voltage integrated circuitry with its proprietary HVCMOS® technology, a
merging of the CMOS and DMOS process technologies onto one
chip. SMART POWER chips have the "brains" and low power
consumption of CMOS ICs and the high-voltage output of DMOS

Product Development Milestones
Supertex has continued the commitment to new product and
technology development that enhances and complements existing product lines. Supertex is recognized as a world leader in
SMART POWER and POWER MOSFET innovations. While
responding to market demands for current products, the company
is also maintaining a leadership position as an industry innovator
in our product niches as evidenced by the product development
milestones listed below:

1980

1981

First to develop fully TTL compatible High Speed
CMOS HCT Octal Interface Logic Family of 22 ICs.

Introduced

1982

First fully integrated Electroluminescent (EL) Flat Panel
Display Drive chip set (HV01/HV02).

1976

Industry leader in CMOS Wafer Foundry technology
and production.

1977

Forerunner in VMOS Silicon-gate technology
development.

Highest density 64K and 12BK CMOS ROMs
introduced.

CMOS Encoder/Decoder with byte-wide Data Capacity
(DC-7) introduced.
1983

Patent filed for High Power VMOS process.
1984

First U.L. approved Smoke Detector IC.

State-of-the-art High Voltage (500V) Power Fet
introduced.

1979

Widest product offering CMOS Encoder/Decoder ICs,
using Manchester coding.

First to introduce 64-line density EL Display Drivers
(HV03/HV04).
First major printer HVIC design win.
First Hi-Rei HCT in leadless chip carriers.

First in the industry to introduce P-Channel VMOS
Power FETs.
1978

Industry Leader in Photo Electric Smoke Detection IC.
Introduction of High Voltage DMOS Lateral Arrays.

MVIC (40-Volt) and HVIC technologies developed for
wafer foundry production.
1985

First Hi- Rei HVCMOS display drivers in industry
(RB HV01/HV02).
Registered HVCMOS trademark.

1986

Development of combined Bipolar and DMOS
technologies (SuperfejTM).
World's first 32K CMOS ROM commercially available.

First to introduce 32-Channel high voltage Matrixaddressed LCD Driver (HV60) with three state outputs.
Introduction of 32-Channel HV51 through HV54 low
power flat panel display drivers, suitable for portable
applications.

High Voltage DMOS/CMOS IC technology developed
for Ultra Sonic Imaging.

2-1

1986

Introduction. ~f industry's first low~threshold P-Channel
power MOSF~T family.

1987

First toirWOCluce 8-Channel nigh voltage level
translator chip (HT01).
Introduction of 84-lead, surface-mount gullwing
packaged for EL flat panel display drivers.

Introduction of 32-Channel P-Channnel EL row driver,
HV41 and 42."to be used for high voltage, high current
. push-pull applicatio!1s in conjunctionwilh HV51 and 52.
Expanding the 32-channel display driver product line to
a total of 12 products.
Introduction of low power 32-Channel AC plasma flat
panel display drivers (HV500 and HV501).

Custom Wafer Foundry
Supertex specializes in CMOS and DMOS Wafer Foundry production providing state-of-the-art wafer fabrication for CustomerOwned-Tooling (C.O.T.) production. Standard as well as modified processes can be produced per specific customer requirements thus providing the highest possible yields and quality.
Engineering runs and preproduction volumes can be run with very

short .. throughput time (I.e., 3 weeks typically). In addition
Supertex can also support back-end packaging and testing
needs.
The following table lists the process types that can be accommodated by Supertex in Custom Wafer Foundry production:

Preferred
Data Format

MInImum
Feature SIze

Metal-Gate CMOS

Masks

411m

Metal-Gate PMOS

Masks

411m

High Voltage Silicon-Gate HVCMOS

Masks

411m

Process Type

2-2

Application Notes

"':l

4
"'-" !!iupertex .nc.

Application Notes

Power MOS Transistor Electrical Performance
This leakage current results from current flow through the insulating layer of silicon dioxide surrounding the gate. Typical DCleakage currents are in the picoampere range between the
temperatures of -55°C and +200° C. This value is well below the
level of concern in most power conversion circuits. When an onchip diode is incorporated between the gate and the source, the
leakage current, which is that of a reverse-biased diode, doubles
approximately every 10°C.

The electrical behavior of power MOS transistors has been
explained by numerous authors. A different, and non-traditional
way of viewing their behavior arises when the device structure is
closely examined. The source and body regions comprise one
side of a diode, with the drain region being the other side. A
voltage on the gate allows carriers to flow from source to drain
through an induced surface channel. Figure 1A shows the forward
and reverse current vs. voltage characteristics of a diode, while
Figure 1B shows the current vs. voltage characteristics of a power
MOS transistor.

C. IDss - The zero gate voltage drain current or offstate leakage
current. It is determined by applying specified voltage from
drain to source (with gate shorted to source) and measuring
the resulting current. (See Figure 5 for the measurement
circuit.)

A power MOS transistor is characterized by a set of parameters
different in many ways from a bipolar transistor. The parameters
specified in a power MOS transistor data sheet are defined and
briefly explained below:
A. VGS(TH) - The gate threshold voltage. It is defined as the voltage
from gate to source required to produce a specified drain
current. For ease of measuring, the drain is commonly shorted
to the gate. (The measurement circuit is shown in Figure 2.)

+

Threshold current is usually measured at a current in the range of
1 to 10mA. (Threshold voltage measurement can be normalized
to the amount of source perimeter when comparing different size
transistors. Full current is usually obtained at VGS = VGS(TH) + 8
volts (N-channel). The threshold voltage is a function of temperature as shown in Figure 3 for a 500 volt Supertex VN03 transistor.
The decrease in the measured value of VGS(TH) is primarily caused
by thermally generated carriers or leakage current that add to the
induced surface current flow, thus decreaSing the amount of
applied voltage needed to obtain a specified current.

G

~

10

Figure 2. N-Channel VGS(th) Measurement

B. IGSS - The gate to body leakage current. It is measured with
drain and source at ground, and gate biased to specified
voltage. NOTE: Due to input capacitance, large die size MOS
transistors may prove difficult to measure with automatic test
equipment, unless a preconditioning test is performed to
charge the gate capacitance prior to test. (See Figure 4 for the
measurement circuit.)

1.2

1.0

.8

.6

.4

.6V

.2

o

-50

-25
Temperature (OC)

A. Diode characteristics

B. Gated diode characteristics

Figure 3. Normalized VGS(th) vs. Temperature for the VN03
Transistor

Figure 1.
3-1

current from drain to source and measuring the resulting
voltage. Properly designed DMOS transistors should not have
a latchback breakdown and a low current measurement is
sufficiently accurate. (See Figure 6 for the measurement
circuit.)

VGS

This parameter is most likely to degrade if exceeded for an
extended period of time in high voltage applications, because of
the large current (and, hence, high power dissipation that may
occur). A lower clamping breakdown voltage diode from sourceto-drain will prevent degradation of the parameter.

(CGSSI-TI

E. gf. or gm - The small signal forward transconductance. It is the
ratio of Lllo/LlVGS measured for a 10% change in drain current
at a specified quiescent drain bias pOint.

Figure 4. N-Channel IGSS Measurement

This parameter depends on device structure as shown in the
equation below (see Figure 7 for measurement circuit):

li°ft L.E ox

Ltox

Vos

where Z

G

L
VOff

(V

GS -

V

GSITH)

)

Source perimeter
Channel length
Effective carrier mobility

E ox = Gate Dielectric constant
tox = Gate oxide thickness

Figure 5. N-Channel loss Measurement

G

These parameters are shown in Figure 8. The forward transconductance is proportional to source perimeter, hence proportional
to chip area. For a given device area, maximizing the.source
perimeter results in a maximum value of gm. This parameter is
also increased by decreasing the gate dielectric thickness, but
this approach limits the total voltage swing on the gate because
of the dielectric strength of silicon dioxide (60V/1000A of Si02 ).
Typical gate oxide thicknesses are in the 1000A range. In power
MOS structures, the transconductance vs. VGS varies as shown in
Figure 9 for a 500 Volt VN03 power MOSFET.

1
10

F . .ROSION) - The static drain-source on-state resistance. It is
measured as the drain-source voltage divided by the drain
current at specified values of drain current and gate source
voltage. (See Figure 10 for the measurement circuit.)

Figure 6. N-Channel BV oss Measurement

The on-state resistance of a high voltage MOS transistor is
dominated by the resistance of the drain region. For a given
breakdown voltage and device area, there is a minimum value of
ROSION), The variations in source geometrics and body-to-drain
breakdown structures discussed earlier are all aimed at realizing
this minimum ROSION) value. In device operation, ROSION) may
appear to be considerably higher than at room temperature. This
behavior occurs because the heating of the device decreases the
carrier mobility, thus reducing the current for a given voltage. This

SOURCE

GATE

Figure 7. N-Channel Gis Measurement

This leakage current is that of a reverse-biased diode. As with a
reverse-biased diode, this current is a measure of the integrity of
the structure and may degrade under extremes of voltage and
temperature.
D. BVoss - The breakdown voltage of drain to source with gate
shorted to source. It is determined by forcing a specified

Figure 8. Parameters Affecting MOSFET Transconductance

3-2

behavior for a 500 volt VN03 transistor is shown in Figure 11 . This
negative feedback characteristic is the key to power MOSFETs
thermal stability.
Vos:;; 10V

G.

300psec pulse
2% duty cycle

v

10(ON) - The on-state drain current. It is measured at specified
values of drain-source and gate-source voltage. NOTE: To reduce heating of the device, this should be performed in a pulse
mode, orwith an adequate heat sink. (See Figure 12for measurement circuit.)

The on-state drain current is proportional to the amount of source
perimeter and the total chip area. Since current flow causes
device heating, the pulsed value of 10(ON) is considerably greater
than the steady state value because of the increasing value of
ROS(ON) with temperature. This specific behavior is shown by the
dotted line for the VN03 in Figure 13.

L

I

I

10
(O(ON> -

2.21

DRAIN CURAENT (ON STATE (Amps)

Figure 9A.

w

Sf
"'-=

1.8

Z~

1

OW 1.6

WZ
-"

VDS:;; 10V
30011secpulse
2% duty cycle

,,<
"',..

5m

1.'

z'"
C~

1.2

1<

1.0

~

.80

/7
/

",w

(

~~

I

~

II

'"

/

/
/

.60

V

I

)

I

.20

-50

-25

25

50

75

100

125

175

200

T - TEMPERATURE (OC)
10

Figure 11.

VGS - GATE·SOURCE VOLTAGE (Volls)

ROS(ON)

as a Function of Temperature for the VN03

Figure 98.

Figure 9.

Transconductance vs. Drain Current or GateSource Voltage for the VN03

VDS
VGS

VGS

Figure 12. N-Channel

Figure 10. N-Channel

ROS(ON)

Measurement

3-3

IO(ON)

Measurement

TRANSFER CHARACTERISTICS

•

Conclusion

/

•

pulse
2% duty cycle

saves

t

•

/

IY

t

:..-

The power MOS transistor is a device with its own set of electrical
parameters. These parameters depend on the device structure.
The success with which power MOS transistors are used will
depend on a designer's understanding of these electrical parameters and their limits. This article has attempted to link the performance of power MOS transistors to their optimum design and
processing and to establish some physical limits for optimum
performance.

3OO~sec

20VDS

-

10VDS

If
2

/

SOurca

,.

Cia

VGS - GATE·SOURCEVOLTAGEIVolts)

=Cga + cdg (unguardad)

em Z Cd. (guardad)
COli"'" Cds + Cdg (unguarded)

Figure 13. ID(ON) as a Function of Gate-Source Voltage for the
VN03
H. Capacitances - Power MOSFETs are characterized by three
capacitances:

Figure 14. VMOS Transistor Capacitance

1. CISS : Input capacitance
2. Coss : Common source capacitance
3. CRSS : Reverse transfer capacitance

Gate

These measured capacitances are related to device structure as
shown in Figure 14. We see from this figure that the value of CISS
for a dual layer access structure will be correspondingly greater
per unit area than an interdigitated structure. With these capacitances, a simple small signal equivalent circuit may be derived as
shown in Figure 15. This equivalent circuit is also useful in more
elaborate transient analysis. These three capacitances have
been measured over temperature, with no appreciable temperature dependence found.

Drain

Cd.

rd.

Figure 15. FET Equivalent Clrcult-Small Signal

3·4

"§upertex inc.
Low-Threshold MOSFETs:
Structure, Performance and Applications
translates to a higher threshold voltage. One method of reducing
threshold voltage is to reduce the body dopant concentration until
the required VGS(th) is met. This technique by itself is dangerous
because it degrades other device parameters. The first and most
important of these is drain-source breakdown (B VDSS ), which is a
result of certain conditions, most commonly punch-through.
Punch-through is defined as the drain voltage needed to create an
electric field connecting the drain and source, as shown in Figure
2, at voltages less than the actual BVDSS rating.

Since an increasing amount of attention is being focused on
system interface from low-level logic, the need for higher current
and/or low on-resistance at drive levels of only 3-5 volts has
become a major concern. Supertex has always known of the
importance of the gate drive consideration and has been offering
N-channel low-threshold devices with threshold voltages of 2.4
and 1.6 volts for many years. Additionally, standard and lowthreshold versions of P-channel DMOS devices are available. To
understand the reasons that low-threshold processing requires
very specialized techniques, one needs to understand the DMOS
structure.

The susceptibility to punch-through increases dramatically as the
body dopant concentration is lowered. There is an optimum body
dopant level that is needed in orderto stay away from the punchthrough mechanism, but this concentration is too high for low
thresholds. This is one of the reasons why P-channel devices
typically have higher thresholds, because the optimum body
dosage is higher than N-channel FETs.

DMOS Structure
Most double-diffused MOS (DMOS) structures have very similar
cross-section characteristics, as shown in Figure 1. For conduction to occur, a channel of electrons is needed between the gate
and the source. This potential produces an inversion layer called
the channel. The depth of this layer is the limiting factor in allowing
current flow between the drain and source terminal. The greater
the voltage applied, the deeper the induced channel; resulting in
more current flow. The voltage needed to invert the channel
region is called the threshold voltage VGS(th)" However, when
examining most manufacturers data books, one finds V GS(th) defined as the voltage needed to produce a specified drain current
(I D). This differs from the theoretical definition of knowing when a
channel is produced, which is of little interest to power MOSFET
users. Comparing V GS(th) at the same ID simplifies the analysis of
databook parameteric guarantees, allowing the designer to
compare the product to actual needs.

Another technique, used by some manufacturers, is to lower
threshold by reducing the gate oxide thickness. Again, there are
tradeoffs using this method: (1) The input capacitance increases
which will effect the switching speed efficiency and (2) the
maximum gate voltage rating is decreased, making it more
susceptible to input voltage spikes.
Supertex has developed a proprietary technique to successfully
lower threshold voltage without these major tradeoffs. This
method mainly depends on modifying the diffusion profile and
altering the charge distribution to produce low-threshold N- and Pchannel devices. This process, which makes use of Supertex's
interdigitated design structure, allows typical thresholds of 1.1

The control of the threshold voltage is dependent on many factors,
such as dopant concentration, gate-to-silicon work function and
surface change. The greater the body dopant concentration, the
larger the applied voltage needed to produce a channel, which
n+

~PO~IY

Gate,-_ _L -_ _-,

Gate

%ZZZZ~ZZ~t-

Electric Field

drain

Figure 1. Double Diffused MOS (DMOS)

Figure 2. Electric Field Connecting Drain and Source

3-5

Part Number

IRF 520

Parameter
VGSlth)
Gate Threshold Voltage

VN1210N5

Mjll

Max

Conditions

Min

Max

2.0

4.0

Vos = VGS ' 10 = 25Ol1A

0.8

2.4

8.0

Vos > 1010N) x
ROSION) max
VGS = 10V

IDION) On-State
Drain Current

0.3
ROSION) State Drain~
to-Source On Resistance

VGS = 10V
10 = 4.0A

Conditions

Unit

Vos = "GS' 10 = 10mA

V

20.0

Vos = 25V
VGS = 10V

A

5.0

Vos = 25V
VGS = 5V

A

VGS = IOV
10 = 10.0A
VGS =SV
10 = 2.0A

0

0.3
0.45

0

Table 1. Comparison between power MOSFET and standard threshold Supertex device
threshold voltage of 1.6 volts for N-channel and 2.4 volts maximum for P-channel clearly supports this claim.

volts for N-channel and 1.8 volts for P-channel, DMOS devices.
An added benefit of Supertex's design is the lower input capaci.tance achieved by the interdigitated geometry, rather than the
more conventional closed cell approach. "The Ideal Interface," an
article published in Supertex's DMOS applications booklet, discusses these geometric considerations. As stated in the article,
less charge is needed to control the device input. Therefore, it can
be concluded that a lower threshold device will start conducting
earlier for a given gate drive and allow control of larger drain
current than a higher threshold device.

Supertex measures threshold voltages at 10 = lmA, 2.SmA, and
10mA for small, medium and large-sized devices, respectively.
Although some manufacturers use test conditions as low as 10 =
2S01lA for large devices, Supertex devices, in comparison, still
have lower values of threshold voltages at higher values of 10, See
Table 1 for a comparison between a popular power MOSFET and
a standard-threshold Supertex device.
A true comparison can be made by normalizing the value of the
10 test condition. The threshold voltage for VNI210NS will be
lower than 2.4 volts, maximum, when it is tested at 10 = 2S011A.
Supertex's test conditions therefore portray a realistic picture of
the device's capabilities at low VGS conditions.

The availability of such low-threshold DMOS devices insures the
performance needed to be driven by low level logic systems, in
which the maximum voltage available is only 3-5 volts.

The threshold VOltage is an important indicator of performance at
low VGS conditions because a device that starts conducting at a
very low bias will exhibit good characteristics under such conditions. In fact, ROSION)' maximum, and 1010N)' minimum, at low VGS
conditions are much more important than just the threshold
voltage value because quiescent gate voltage conditions are
usually at least a few volts above the VGSlth) value. Figure 3 shows
the transfer characteristics of a standard-threshold and a lowthreshold device. For example, if the drain current requirement is
100mA, TN0520N3 will typically need VGS = 1.8 volts and
VN0220N3 will require 2.8 volts to achieve this value. In case a 2.8
volts drive is not available, as in many applications, a VN0220N3
will be incapable of functioning in the circuit. In spite of the TNOS
die being half the size of a VN02, the TNOS20N3 performance is
far superior at low gate to source Voltages.

Performance Advantages
With the first device shipped in 1982, Supertex was the pioneer in
low-threshold DMOSFET technology and still maintains a performance edge over other manufacturers. Supertex currently
supplies the lowest threshold power MOSFETS in the industry. A

r----,----;---_--r--,

300

1.P

200 j------j----i----,f--t---J-----I

When confronted by low gate drive voltage, a designer basically
has two choices:
100 I-----+----#------J--'.'-'-===-j

o

~

__

~

__

~~

__

~

__

Approach 1: Use a large industry-standard-threshold device to
obtain the required low ROSION)' maximum, and
1010N)' minimum, values. 1010N) can be obtained from
the transfer characteristics and ROSION) values will
be read off the typical saturation or output characteristics.

~

Approach 2: Compared to the device used in Approach I, use a
relatively small (die size), low-threshold device to
achieve the desired 1010N) and ROSION) at the given
minimum gate-to-source Voltage.

Figure 3. Typical Transfer Characteristics
3-6

vGS =

0J
Utilty

Power Supplyl
Battery Charger
with float

9.3V Max
6.0V Min

JL
Control Circuit

and equalize mode

Figure 4. Motor of a Fluid Injection Pump

Comparison of Approach 1 and 2

a FET can cause two problems: A) loss of control signal or
data; or B) loss of power due to resistive losses. Supertex TNI
TP series devices are being used for a variety of data acquisition and remote-control applications.

1. Large die always have larger parasitic capacitance and consequently slower switching speeds. This could pose a restriction
in many applications, where limited gate drive charging current
is available.

• Medical equipment with battery back up is another popular
application. Figure 4 shows the motor of a fluid injection pump
powered by the utility supply and backed by a NiCad battery.
The VGS = 6 volts condition demands carefully attention, because the RDS(ON) has to be low in order to ensure a low drain
to source voltage drop. A large voltage drop can A) affect motor
performance, and B) cause high 12R losses, reducing system
efficiency and battery back-up time.

2. Large die must be accommodated in large packages, and this
may result in unnecessary waste of board space. For example,
the total volume occupied by a TO-220 package including
stand off could be 8 to 10 times more than a TO-92 package.
3. A judicious choice using smaller die in a smaller package can
result in considerable cost savings. With more silicon and
several times the raw material content for packaging, a lowthreshold TO-92 will definitely be a much more cost-effective
alternative.
Supertex publishes ROS(ON), maximum, and ID(ON) minimum,
specifications at VGS = 5 volts (see Table 1). This data is very
useful to a designer because it is always desirable to rely on
guaranteed values instead of typical curves. Typical curves are
based on a high statistical probability of the majority of devices
closely meeting values on the curves. They do not 100% guarantee performance of all devices. Manufacturing tolerances and
some variations from one fabrication lot to another are likely to
cause lower than expected values of these parameters. Depending entirely on curves tends to be risky for production runs even
if prototypes built earlier perform satisfactorily.

Photovoltaic
Diode Stack

Control
Signal

The combined effect of low-threshold voltage and low-input
capacitance is ease of drive, which is a key consideration in most
circuits employing power MOSFETs. What better trait can a
designer expect than a small amount of charge controlling high
voltages and large currents? These low-threshold FETs from
Supertex are ideally suited to interface low-voltage logic to the
outside world.

n

]

f
/V
/V

1
1
1

IJ

+

Figure 5. Photovoltaic Drive Scheme

Low-threshold power MOSFETs playa key role in circuit design
whenever there is a low gate-to-source voltage situation. Conventional devices are often very inefficient and sometimes unusable
in some applications as follows:

• Solid-state relays utilize optically-isolated drive schemes for
isolation purposes. Figure 5 shows a commonly-used photovoltaic drive scheme. Usually a low voltage is available to turn
on the FET to meet the relay's assured ROS(ON) specifications.
Precautions are taken to avoid excessive drive since the charge
applied during turn-on must be quickly discharged during turnoff. Turn-off circuitry is not shown in this simplified schematic .

• Handheld, battery-operated equipment requiring satisfactory
operation at low/end-of-discharge voltages. This is necessary
for complete utilization of battery energy. Inadequate turn-on of

• Figure 6 shows a simple charge pump converting 5vdc to
12vdc. The key parameter for efficient functioning of this circuit
is ROS(ON) at V GS = 5 volts.

Applications

3-7

5Vdc

5Vdc

IN

IN

Figure 6. Charge Pump Converting Svdc to 12vdc
Supertex low-threshold TN05 devices used for the pulser and
mute switch operate satisfactorily, even at voltages as low as 3
volts. A TN0524N3's guaranteed IO(ON) minimum = 1OOmA at VGS
= 3 volts is more than adequate for this purpose.

• Telephone. handsets encounter wide variations of voltage
during normal operation (Figure 7). While the DC voltage
appearing across the unit may vary from approximately 3 to 25
volts when the phone is off the hook, high voltage AC ringer
signals and associated transients have to be handled safely.
Moreover, atmospheric disturbances (e.g., lightening and RF
radiations) are picked up by the lines, inducing high voltages
which are suppressed by MOVs, gas discharge tubes, etc. (not
shown in the figure).

Advances in low-threshold power MOSFET technology offers
several useful choices to a designer. Circuit design for many
applications are simplified and use of components minimized.
Consequently, system complexity is reduced and reliability enhanced. All these benefits combined with the cost-effectiveness
of the devices makes the low-threshold FETs an excellent choice.

(240V

--0 <>-----,
Hook-switch

Constant-current
Device)

Line
--0 <>--t----'

Figure 7. MOSFETs In a Telephone Handset

3-8

4

-

"--'-' §upertex .nc.

Application Notes

Basics of EL Panel Drive Techniques
Thin film electroluminescent (EL) panels operate on a principle of
successive pulses of opposite polarity. These pulses must exceed a threshold of approximately 200V for the panel to emit light.

to the row scan pulse. This combination of row and column voltage
across the phosphor will exceed the threshold and cause the
phosphor in areas between the energized row electrodes and the
energized column electrodes to glow. This sequence, applied to
successive rows, causes certain portions of the display to be
illuminated.
.

A flat panel display is a sandwich of phosphor material with
dielectric coating on either side; transparent ITO (indium Tin
Oxide) row electrodes on one side and column electrodes on the
opposite side. These layers are built up on a sheet of glass to form
a very thin, lightweight display panel.

Because the phosphor requires successive pulses of opPOSite
polarity to operate, an opposite polarity refresh pulse is applied to
all row electrodes simultaneously while the column drivers are
kept at ground. The sequence then begins again at row #1 with the
next frame of data. Figure 2 is a representative timing diagram of
the signals applied to a TFEL panel showing the first four rows and
the first column.

Since the drive electrodes are dielectrically isolated from the
phosphor material, and each other, the display panel exhibits a
capacitive load to the drive electronics. On larger panels this
capacitance can be quite high. Surge currents can be large,
therefore coupling from the row to the column electrodes should
be considered.

Due to the fact that the phosphor illumination threshold has a
slope of illumination versus applied voltage within a short range,
the column drive electronics can be made to vary the applied
voltage within this range, dictated by the intensity of light desired
for a particular element on the display. By this means, a grey
shade image can be created using the EL display.

The drive electronics used to operate the panel are organized in
a manner to surround the display panel with contacts as shown in
Figure 1Generally, the row electrode electronics supply the major portion
of the threshold voltage, called the scan pulse, and the opposite
polarity "refresh" pulse, which is necessary for the panel to emit
light. The refresh pulse is usually applied to all rows at one time
while the scan pulse is applied to one row at a time (starting with
row #1), similar to a television raster scan.

Row Drivers (HV02, HV03, HV05)
To allow the open drain outputs to provide the opposite polarity
pulses to the panel, the sources of the output MOSFETs must be
switched between the different voltages required for the panel.

Depending on the data to be displayed in each column, the
column electrode electronics supply a voltage of opposite polarity

Inpllt§§~~~~~~~==~==~~=j~===4JU

Column Clock

Bottom
Data Enable
Column
Column Latch

Figure 1. Block diagram of the driver system for a TFEL (Thin Film Electroluminescent) panel. Note that the column drivers have
two data lines with interleaved pixel data.

3-9

_":
I

1

Row 1

Row 2

(

~

Scan
Pulse

U

ROW3~

II

((

U

ROW4~

u
n

n

Column 1

)\

((

Pixel On
VScan
+

Vpp

))

t(

r~

n
n
n

U
U

Lr
rL

)l

((

Pixel Off

Pixel Off

_L

Vpp

V Pixel
(Row 1, Col. 1)

Figure 2. Simplified diagram illustrating row and column timing to operate an EL Panel. YREF only lights pixels that were turned
on by Y SCAN and Ypp pulses in the previous frame of information.

Monolevel Column Driver (HV04, HV06)

Since these MOSFET source connections are connected to chip
ground, the entire device needs to be isolated or "floated" from the
system ground. The control signals to the row driver chips
therefore must be opto-isolated from the system ground. Figure
3 shows a simplified way to accomplish this.

The column drivers are used to apply the data to be displayed onto
the panel. The data for each row of picture elements (pixels) is
loaded into all the column drivers serially and latched into the
'output latches. The outputs are thus turned to their desired state,
and then the high voltage (Vpp) is applied. Columns selected for
data display are connected to Vpp through the CMOS output and
are pulled up to Vpp' The combination of the column Vpp and the
selected row voltage will cause selected pixels to light in that
particular row.

The two high voltage supplies are switched to the row substrate
(driver chip ground) using MOSFET switches. Application of the
voltages to the panel is as follows: the refresh pulse is applied to
the entire panel at the same time by pulsing on "C," forward
biasing the body-drain diodes on all row outputs. The panel is
returned to ground by pulsing "D" while having all the row driver
outputs on. The scan pulse is applied, one row ala time, by pulsing
on "A" while the selected row output is on. The selected row is
returned to ground by turning on "B." The next row to be scanned
is then selected, and the scan is repeated; first "A," then "B." When
the entire panel has been scanned, the refresh sequence is
executed; first "C," then "D." The scan cycle then begins again.
In this way the proper voltages and sequences are applied to the
panel for operation.

During the time that the data for one row is being displayed, the
data for the next row is being loaded into the shift registers,
awaiting the display olthe next row. When a row is completed, the
column driver Vpp is brought low and the data waiting in the shift
register is loaded into the output latches. The cycle then begins
again for each successive row.
The column drivers are designed with a serial shift register output
for use in cascading the column drivers together. This allows the
data for one row to be loaded serially, using one serial input at the
first column driver device.

3-10

Grey Scale Column Driver (HV01)

put, such as required by panels to be operated in direct sunlight,
requires another method of increasing output. This is done by
increasing the pan~lJrame rate, or .refresh rate. Normal CRT
based systems work on a 60Hz frame rate.Most applications of
EL panels replacing eRTs, then, also operate at this rate: This:is
fine for office and home use but does not provide enough
brightness to accommodate most military applications. By increasing the refresh rate up to tenfold, a dramatic increase in
brightness can be achieved.

This device is designed to take four data inputs in parallel into four
shift registers. The data is then taken from equivalent stages of
each shift register and converted to an analog level, 10f 16
between ground and Vpp' this is done by a digital counter using
four bits of input data. The counter is preset with data counting
down to turn off a transistor. This transistor isolates a ramp input
(VR) from an internal storage capacitor, which controls a CMOS
output stage. The output voltage therefore represents the value of
the ramp voltage (VR) at the time the counter for each output
counted down. This voltage, applied to the column of the panel,
combines with the row scan voltage to vary the light output from
each pixel in the selected row.

This increase in refresh rate requires some changes in the column
driver configuration. Instead of cascading all the column drivers
together, each column driver shift register input is driven in parallel
by the controlling system at the same time. This increases the
number of data lines required but allows the data to be loaded
much faster, enabling the faster frame rates desired. The row
drivers are used at a much slower rate, so no changes are
required to achieve faster operation.

Panel Brightness
The varying brightness of an EL panel by voltage variation can
only achieve a limited range. Dramatically increased panel out-

01
+190V
Refresh
Power
Supply

Scan
Power
Supply

Row
Electrode
Row
Logic
Supply

B~

Logic
Op10
Isolator

01,04
02,03

D~

= VN0345N5
= VN0335N5

450V
350V

-190V
Q4

-190V Scan

Figure 3. Row driver panel switching block diagram.

3-11

a
'f1J !iupertex inc.

Application Notes

Cascading Encoder-Decoder
Mode of Operation

The Supertex family of Encoder-Oecoderdevices allows address
matching of up to 32,768 different codes. Four bits of data can be
sent to up to 2048 different receive devices. This has been
adequate for the vast majority of applications. Some applications,
however, require even more addressing capability than the largest part can offer.

Figure 1 shows a simple means of cascading two ED devices to
allow more than 1.07 x 109 addresses. The basic requirement for
using this design is that the transmission into the receiver consists
of two ED-style data packets (preamble and data) separated by
a short interval. The first data packet will go to the primary ED
device (ED #1) and the second data packet will go to the
secondary ED device (ED #2). These groups of two data packets
must be separated by a much longer delay. Figure 2 is a timing
diagram of the operation of this cascaded receiver.

A cable TV control system, with which a cable company would
want to control operation of all the decoders in their area, is one
application in which the possible remote addresses could number
more than 32,768. Another possible use is remote meter reading
of domestic and industrial power meters by the local utility
company. This offers tremendous savings in labor costs over
manual meter reading. Both of these applications require a low
cost, simple means of implementing single unit identity coding of
a large number of remote devices. The Supertex ED devices offer
this capability.

On initial condition, in which the receiver is waiting for an address
group to arrive, one-shot Ie #1 enables the incoming signal into
the Start/Data Input (SOl) of ED #1 while disabling the path to ED
#2. When the group arrives, the first data packet is input into ED
#1. When this data packet, both preamble and data, have been

Vee

SIGNAL
INPUT

Figure 1.

3-12

ADDRESS
/~

GROUP

_________________________

/l~

_________________________

~

PRIMARY ADDRESS

SECONDARY ADDRESS

DATA PACKET#,
PREAMBLE #1

I

-------------'

#1

~

PREAMBLE# 2

LJ

DATA#2

L ____

~~---------~

EO#, OV

IC# 1

LJ

qATA'.PACKET#2 .

DATA

IT

•

------,
ED

# ,

I

DIDO

I

ADDRESS MATCH

-- -

- - - - - - - - - -- -

- - -

--

- - - --;

-

ED# 2 0/00

.~----------~

ADDRESS MATCH

LJ

EO# 2 501

Figure 2.

Address and Data

received by ED #1, the Data Valid (DV) signal will go high,
triggering the one-shot. This will disable the SDI input to ED #1.
If the data in data packet 1 matched the address data on the ED
#1 data pins, then ED #1 Decode/Data Output (DDO) pin will also
go high. This and the triggered one-shot enables the path from the
signal input to the SDI pin of ED #2. The second data packet Will
then be received by ED #2 and compared to the data input pins.
If the address matches, the ED #2 DDO will go high.

Often it is necessary not only to address a particular device within
a large number of devices in a system, but also to send some
amount of data only to that device. The ED-11 and DC-7 devices
easily implement this capability in the cascaded design. Figure 3
illustrates a data transmission variation of the cascade circuit.
The input controls for ED #1 and #2 operate the same as for the
address matching case. In this case, however, the Serial Data
Output (SDO) and Data Clock (DC) of ED #2 are connected to a
4094 serial to parallel shift register. The SDO is connected to the
Data In pin, while the DC is connected to the Clock pin to clock the
data into the shift register. The rising edge of the ED #2 DDO
Signal is converted to a pulse and used to transfer the data from
the shift register to the parallel output latches of the 4094 if the
address match is detected. The DDO pulse is also available from
the receiver system as an interrupt to the external circuitry
signalling the arrival of data from the transmitter.

The one-shot timing must be set to allow data packet 2 to be
completely received before the one-shot times out and returns to
the off condition. This time period will vary depending on the
transmission speed of the communication link and the ED speed
used. After both data packets have been received and the oneshot has timed out on all the receivers in the system, the
transmitter can then send out a new address group.

Address Decode
The circuit shown in Figure 1 and described in the previous section implements the address decode function. The DDO pin on ED
#2 should be connected to a device that operates on a positive
going edge to signal the correct addressing of both ED #1 and ED
#2.

ED#1

ED #2

Data Bits

ED-15

ED-l1

4

67,108,864

ED-15

DC-7

8

4,194,304

ED-15

ED-5

15

Different combinations of ED devices can give a different number
of possible addresses. The following table illustrates these possibilities:

ED-5

ED-l1

4

65,536

ED-5

DC-7

8

4,098

ED-5

ED-5

15

# of possible addresses

ED#1

ED #2

ED-15

ED-15

ED-15

ED-9

16,777,220

ED-15

ED-5

1,048,576

Address Combinations

32,768 'special case

32 'special case

* The special cases noted above represent a situation in which 15 dat~ bits must. be

1,073,741 ,824

received. This is implemented by using ED#1 only for address matching and uSing
ED #2 only for data reception. To receive 15 bits, two 4094s must be serially
connected to form a 16 bit shift register. The Data Valid (DV) output of ED #2 would
be connected in place of the 000 output to strobe the data into the latches of the
40948.

The ED-9 cannot be used in the ED #1 position because it does
not have a DV output available.

3-13

V D

RTD

SIGNAL
INPUT

TRI-STATE
ENABle

Figure 3.

Transmitter

Conclusion

The transmitter used to address this receiver design would
normally be microprocessor controlled, with a peripheral adapter
port connected to the data pins of an ED-15 device. The data pins
could be changed to implement the data packet #1 and #2 by the
much faster microprocessor. Alternatively, two ED-15s could be
OR-gated to a transmission media and controlled by normal logic.

This application should help implement a simple low cost means
to address a large number of remote devices in an addressing
system. If there are any questions or suggestions for improve·
ment, please contact the applications engineering department at
Supertex.

3-14

a"'-1J §upertex ,nc.
-

Application Notes

DC-7, ED-5, ED-9, ED-11 Applications
The Supertex EDs

The Supertex "ED Family" of remote control encoder/decoder
chips has almost unlimited uses. To make the user aware of some
of the salient features of these unique ICs, we have put together'
this application note. When used in conjunction with the data
sheet for these parts, most of the questions that may arise from
attempts to design systems around them may be answered.

In addition to the "Iock-and-key" feature of ED codability, the ED11 has the feature of being able to transmit and receive 4
additional bits of binary data which are available at the decoder's
output. The DC-7 has 8 bits of data. These can be used to perform
tasks such as channel recognition (with digital readouts), microprocessor interface and event sequencing. This feature makes
the ED family of encoders/decoders extremely versatile.

Remote Control Systems
As electronic systems become increasingly more sophisticated,
the need to perform certain functions at a distance becomes
increasingly important. In many cases, the need arises for central
automatic control of remote operations. Here, too, remote control
devices are necessary. Until recently, remote control of various
functions required a plethora of discrete circuits, raising the cost,
in many cases, to prohibitive levels. Recently the MOS lSI
industry has responded with integrated circuits of varying usefulness and complexity. Most of these ICs are geared to perform a
single task such as opening garage doors, controlling TV functions, and the like. Until now, all remote control ICs were sold in
a set; i.e., a separate encoder and decoder. The Supertex EDs on
the other hand are a single chip. The encode/ decode function is
determined by a programming pin, which is tied to V DD for the
encode function and V55 forthe decode function. Having only one
chip reduces the complexity of purchasing remote control. Spares
are easier to stock, and reliability is enhanced.

Simple, Two-Wire Interface Utilizing ED-15s
The basic application for the ED-IS is the simple two wire
interface. This configuration is useful for optimizing ED parameters such as encoder/decoder frequency stability, and lockup
time. It is also a useful way of observing waveforms and can be
invaluable for troubleshooting a more complicated system using
other transmission media.
In Figure 1, the output is not latched and will stay high only so long
as the trigger circuit keeps cycling the encoder. The CMOS
oscillator is necessary to produce the start pulse. By utilizing an
oscillator, it is possible to get a continuous data stream. This is
useful for observing all waveforms involved. The start pulse
oscillator can even be used to trigger the scope, making the
waveforms easy to sync. The wire used can be just a jumperwhen

VDD

.025uF
.025 uF

DATAVAl/D
DATA CLOCK

DECODE

our

L-._ _ _ DATA OUT

4049 OR 4089 TRIGGER CIRCUIT
~

1 KHz

Figure 1_ Basic Two-Wire ED System

3-15

chart is given below tlie schematic to show the relationship of the
"key-coda' bits to the last 4 data bits.

both encoder and: decoder are on the samebreadboard,but
twisted pair or shielded cable should be used for long runs.

In Figure 3, a DC-7 Can be used for the transmitters,as well as for
the receiver. An ED-15 is shown to illustrate the cOillPatibility of
the ED family o/encoder/decoders. The 4094 in the circuit is a
serial to parallel converter and an 8-bit latch. This circuit demonstrates the use of the DC-7 in which both the data and address can
be transmitted from one location to another and both the data and
address of the transmitter recovered. In an application in which
only the data is to be recovered and a special address assigned
to the receiver, the 0/00 signal should be connected to the 4094
and only the TOP 4094 used. In a system in which all incoming
data and addresses are to be decoded the DV signal would be
connected to both 4094s as shown. The bit sequence chart is
given below the schematic to show the relationship of the "keycode" bits to the last 8 data bits.

ED-11, DC-7 System Utilizing Hardwire
Transmission and Output Latches for
Additional Data
As stated earlier, one of the great features of the ED family of
encoder/decoders is the ability of the ED-II and ED-5 to transmit
4 bits of binary code along with the "Iock-and-key" recognition bits,
the DC-7 to transmit 8 bits of binary code along with the "Iock-andkey" recognition bits, and these 4 or 8 bits to appear at the data
clock output of the receiver. This feature allows the transmission
of useful data instead of just the "code valid" output common to
other so-called remote control encoder/decoders. The following is
an adaptation of the hard-wired system seen above. The difference is that even though an ED-15 is used forthe encoder, an ED11 is used for the receiver, and this data is decoded for use as a
parallel latched data bus. Of course, since the last 4 bits in the ED11 are used as actual transmitted non-dedicated data, it has only
2048 different possible code combinations instead of the 32,768
combinations possible with the ED-15 system. The trigger circuit
is .the same as above and will be represented from here on only
'as a block diagram.

Infrared Transmission
Often it is necessary to transmit data over some distance without
wires. In such an instance it is necessary to couple the data (in this
case from ED-series encoder/decoders) by way of some transmission media. Here is a simple but effective way to use IR as a
medium for signalling between two EDs.
The circuit in Figure 4 is designed so that the ED-15 is operating
at 25KHz. The output of the chip (Pin 7) is applied to an NPN
transistor gated with a 3.3KQ base resistor to act as a switch. The
data stream turns the 2N4401 hard on or off depending upon the
coded state. This in turn switches on and off the Monsanto
MV5000 series infrared LEOs. Three of the LEOs are used to
make aiming at the receiver easier.

In Figure 2, an ED-11 can be used for the transmitter as well as
for the receiver. An ED-15 is shown to illustrate the compatibility
of the ED family of encoder/decoders. The 4015 in the circuit is a
serial to parallel converter and the 4042 is a quad 4-bit latch. The
data valid pin is used to clock the parallel data into the latch and
Q as well as Q outputs are available on this IC. The bit sequence

DATA

.025 uF
10K

19

22

1

28

2

27

3 ~
4

VDD

VeD
28
2
.025 uF

6w

10K

3
4

::
I

0

w

6
6

27
23 SDO
25 DC
7 000
24 DRS

18

18

ADDRESS

ADDRESS

It>

7

...0

5

01

9 :.<1 4

02

3

03

6

10

04

5

2

01

10

02

11

03

TO LATCHES

SPST
TRIGGER
CIRCUIT
FIXED
BIT

, 1'-

KEY CODE

.,... .,

Veo

DATA

TO 4015
OUTPUTS

I IXIXIXIXIXIXIXI

6

I

02
03

Q,

7
13

04

14

4

Figure 2. ED System with Latched Parallel Data Out
3-16

~

FOR CONTROL
OR DISPLAY

04

VOO

VOO

VOO

2.
GNO

27

6'"w
501

START SIGNAL

r-

DIDO

STROBE

CLOCK

22
DATA

6

•

07
06
DO

16
TIA

DATA

"
"

ADDRESS

1

~

7
I.
13
12

04
03
02
01
DO

ADDRESS

A6
AS
A4

~:~ED

"..

I

A3
KEY CODE

DATA

~I"

A2

~,

AI
AO

.,

IXIXf>'VV-----..

The impedance of the line is likewise ill-defined. It may be
resistive, inductive or capacitive. Line attenuation is difficult to
estimate because it is extremely load dependent. A high-power
load can significantly reduce the impedance of the line at the point
of connection and thus dominate attentuation for all points of
communication that occur beyond the offending load unless that
load is isolated with chokes. Capacitive loads can be equally
troublesome and are not necessarily associated with high-power
loads. Another large component of the net attenuation can be the
signal loss incurred in coupling across the multiple windings of a
power distribution transformer. This alone can amount to 20 to 40
db, depending on carrier frequency and transformer construction.
The system described in this application will have problems
communicating to the receiver units if the line attenuation is large
enough to load the transmitted signal to a level below the receive
sensitivity of the power line modem.

Power

Line
Modem
Receiver

AC PowerUne

Figure 4. Receive Circuit

Power Line Interface
The Power Line Modem was calibrated to transmit a 125KHz
burst at a signal level of 7.5 volts pop into a 50 ohm load.
Impedances of residential wiring may be over 50 ohms while
industrial impedances may be less than 1 ohm, with the receiver
sensitivity set at 15 millivolts.
3-22

Designing for the Power line Environment

There are numerous methods for overcoming the problems
associated with power line impedance. If the problem is due to the
transmitted signal level, then line drivers can be added to boost
the transmitted signal level. If the problem is due to cross phase
attenuation caused by transformers, then a capacitor can be used
to couple the communication signal across the windings.

The application described in this paper is a relatively simple use
of existing technology to achieve a low cost means of control
communication overtheAC power line. The system is veryflexible
with regards to the ability to add microprocessor intelligence to the
transmit and receive ends of the communication link. This added
intelligence may be used to overcome some of the problems
associated with power line noise.

The primary problem that everybody is faced with when interfacing to the power line is that the communication media (power line)
is different at each installation. The key is to offer a system that is
flexible enough to adapt to the demands of the environment.

The microprocessor could be used to allow both receive and
transmit at the same location. The microprocessor would enable
the use of a closed-loop communication link with the unit that is to
be controlled. This ability could be used to obtain status reports
from the control unit, to make sure the unit properly responded to
control information. In the case of a unit not properly responding
to control messages, the controller would simply resend the
control message until the unit properly responds. The microprocessor software could also include algorithms that detect power
line noise or other power line communication. When noise or
communication is detected, the microprocessor would simply wait
until the power line was quiet enough for it to transmit its control
message.

Summary
Flexibility of the Supertex Encoder-Decoder devices can be
utilized to make practical a simple power line interface design that
has the capability to transmit data bidirectionally as well as the
simple address match OnlOff function. This design is only a
representation of the many possible new product designs that can
result from the use of the Supertex Encoder-Decoder in power line
systems.

3-23

.

,'

Alphanumeric Index and Ordering Information
Company Profile
Application Notes
Static Handling Procedures and Quality Assurance

..-.
.-..
""~

i

I

I

Process Flow

'

DMOS Product Family

~

N- and P- Channel Low Threshold MOSFETs

~

DMOS Discretes N-Channel
DMOS Discretes P-Channel

•

DMOS Arrays and Special Functions
HVCMOS High Voltage ICs
CMOS Consumer/Industrial Products
Lead Bend Options and Surface Mount Packages
Package Outlines
Representatives/Distributors

-

I

"!iupertex inc.
Static Handling and Testing Techniques For MOS Devices
CAUTION MUST BE USED WHEN HANDLING AND TESTING MOS DEVICES. STANDARD PROCEDURES SHOULD INCLUDE THE
FOLLOWING TECHNIQUES IN ORDER TO AVOID POSSIBLE STATIC DAMAGE:
1. Store MOS devices in conductive carbon or nickel shipping
bags, conductive foam, or conductive tote bins.

6. All parts should be handled by their packages and not by the
leads.

2. The person handling the device should be grounded by the use
of a 0.5 to 1.5Mn wrist-strap.

7. Relative room humidity should be kept between 45 to 60%
since static generation increases exponentially as humidity
decreases.

3. Workstations should have grounded conductive mats over
non-conducting surfaces.

8. Work, testing and storage areas should be mopped monthly
with staticide solution or equivalent.

4. All conductive surfaces and equipment must be connected to
earth ground.

9. For further details refer to DOD Handbook 263 and DOD
Standard 1686.

5. Rubber gloves and clothing that do not generate static are
recommended to be worn by any person handling parts.

FOR YOUR CONVENIENCE, THE FOLLOWING IS A PARTIAL LIST OF COMPANIES THAT SUPPLY ANTISTATIC PRODUCTS:
1. 3M Nuclear Products
3M Center
St. Paul, MN 55101

Conductive Bags, Grounding
Mats, Tote Bins and Other
Material

2. Wescorp/DAL Industries, Inc.
1155 Terra Bella Ave.
Mountain View, CA 94043

Wrist Straps

3. Biggam Enterprises, Inc.
2124 Bering Dr.
San Jose, CA 95131

Wrist Straps, Staticide and
Other Antistatic/Conductive
Material

4. Free-Flow Packaging Corp.
2500 Middlefield Rd.
Redwood City, CA 94063

Anti-Static Packaging
Material

4-1

"!!iupertex inc.
Quality Assurance
The Management of Supertex Incorporated is committed to the
continued enhancement of product excellence and service
through the dynamics of its Reliability and Quality Assurance
System, through the integrity of its people, and through the many
professional disciplines engaged in new product development
and process innovation.

•
•

Document Control - The primary responsibilities of the Document Control department are to translate and format internal
operating procedures and customer requirements into a system
of regulatory written instructions. Document Control functions to
ensure documentation integrity by establishing and maintaining
procedures for:

It is the chartered responsibility of the Reliability and Quality
Assurance Manager to oversee and ensure enforcement of
Supertex's Quality System. A formal yearly review is undertaken
to ensure continued development of a Quality System that maintains a competitive stance with the marketplace and meets
customer requirements.

•

The Manager of Quality Assurance/Quality Control reports
directly to executive staff level of Management.
Reliability Assurance maintains a dual level of reporting - to the
QAlQC Manager for R & QA program coordination, Reliability
Assurance monitor and control, failure analysis, and to the Product Vice President for Reliability Assurance and qualification of
product/process. This type of structure provides for the autonomy
and direction that is needed to successfully manage the Reliability
functions and maintain technological awareness in specific product support areas.

In-Process QC - The primary responsibilities of the Quality
Control department are to establish and maintain effective controls for monitoring manufacturing processes and equipment; to
provide information concerning the state-of-control; and to initiate
statistically valid techniques to further improve Quality and Reliability levels. This concept is used extensively in, but not limited to,
the following major Quality Control functions:

It is the responsibility of the R & QA Manager to administer the
planning, organization, execution, surveillance, appraisal, corrective action and documentation of Quality Programs within the
chartered responsibility. The character, responsibility and authority vested with the R & QA Manager will establish the means to
attain the necessary Quality and Reliability objectives in all
aspects of manufacturing.

Incoming Raw Materials Qualification
Wafer Fabrication Monitors/Audits
Assembly Monitors/Audits
Test Monitors/Audits

Quality Assurance (Standard and Hi-Reliability) - The primary
responsibilities of the Quality Assurance department are to ensure that the delivered product meets appropriate workmanship
standards and any special customer requirements. This is accomplished through a program of process controls and gates designed so that all devices are properly tested and sampled prior
to shipment. Control/inspection data keeps all relevant personnel
fully informed on the quality level of product going through final
test operations. Major Quality Assurance functions include:
•
•
•
•

Quality programs administered by the R & QA Department
support the following functions:

Operator Training - Supertex maintains a System of Operator
Training and Qualification specific to the nature and complexity of
each manufacturing operation, inspection, or test requirement.
The basic training approach used by Supertex is supervised onthe-job training assisted by experienced/qualified personnel to
provide a "buddy system" of training.

Incoming Contract Subassemblies Inspection
Wafer Electrical Test
Product Assurance Electrical Test
OutgOing Plant Clearance

Training is typically performed with the same eqUipment and tools
used in the normal manufacturing environment. The use of
training aids, such as films, photographs and demonstrations of
equipment and tools, is typical.

Reliability - The primary responsibility of the Reliability function
is to assure that a high and consistent level of product reliability
is maintained. Reliability establishes, defines and maintains
evaluation programs to determine process/product reliability.
Major Reliability activities include:
•
•
•

Initiating, revising, approving, distributing, recalling, and
archiving documents.

Organization

Primary Job Charter of the
R & QA Departments:

•
•
•
•

New Product Design Evaluations
Reliability Assurance Monitors

Each department manager is responsible for the training and
evaluation of the workmanship performance to manufacturing
norms.
The R & QA department maintains a System of Audits/Monitors
for evaluating Operator's adherence to specification and quality of
workmanship.

Failure Analysis
Hi-Reliability Programs
Process/Product Qualifications

4-2

Raw Material Procurement and Qualificetion - Supertex maintains a system that ensures economical control and conformance
to detailed technical and quality requirements of purchased
materials (direct and critical indirect). Material procurement is
performed through regulated specifications and drawings. R &
QA functions within this system by providing the following
services:

Major elements found in Supertex's Quality Control Program are
summarized by, but not limited to, the following:
•

Environmental monitors (Airborne Particle counts, % RH
and temperature).
• Routine Scanning Electron Micrography (SEM) of semiconductor devices.
•
•
•

Specification compliance audits.
Random monitor of wafers in-process.
Electrostatic discharge prevention/monitor.

•

Product lot sample qualification at critical manufacturing
points.

•
•

Wafer/die electrical sort monitor.
Quality performariceltrend data reporting.

•
•

Formal review for disposition of nonconforming materials.

Return material analysis reporting.
Monitoring of storage, handling, packaging, and identification of raw materials, of work-in-process, and of finished
product.

Equipment Calibration - Supertex maintains a Calibration System that ensures measurement accuracy of equipment used to
determine product workmanship and acceptability.

Product Assurance Inspection - Supertex maintains a system
of Product Qualification through inspection and test of finished
product prior to customer shipment.

The Calibration System conforms to MIL-STD-45662. Major
provisions of the R & QA program are described as follows:

The Quality Assurance department provides inspection based on
statistical sampling to ensure that outgoing product quality meets
internal workmanship standards and customer procurement
requirements.

•

Documented instructions for material evaluation, procedures, flow, workmanship standards, test methods and statistical sampling.

•
•

Incoming inspection of raw materials.
Identification and segregation of qualified and nonconforming material.

•

Vendor qualification and ongoing vendor performance
appraisal.
Feedback of inspection results and informing suppliers of
new design changes on raw materials.

•
•

•
•

Qualification of external calibration services.
Traceability of references to National Bureau of Standards.
Identifications of measurement and test equipment (electrical, mechanical, and optical) for type and frequency of
calibration.

•

Document file certifying equipment calibration and recall
history.

•
•

Management report on recall status.
R & QA audits of equipment calibration (date stickers and
recall designation).

The following process controls, inspections, tests, and documentation requirements are assured prior to submission of product to
Customer Source Inspection and prior to final Outgoing Plant
Clearance:
•
•
•

•

Manufacturing Flow, Inspection, and Test Points - Supertex
maintains Flow Charts that describe the sequential steps of
semiconductor processing and associated documentation for
Wafer Fabrication, Assembly, and Post Assembly Finishing
through Final OutgOing Plant Clearance. Flow charts are prepared for each product family and associated manufacturing
technology.

Test equipment correlation and qualification.
Monitor manufacturing test operations.
Ensure conformance of product lots to detailed customer
test requirements (Electrical, External Visual, and Mechanical).
Assure proper and complete documentation for each product lot, both in-process and at-plant clearance.

Reliability Assurance - At Supertex the Reliability Concept is
introduced at the design phase of all new products. The factors
that may affect product reliability are: compatibility of fabrication
process, circuit layout and characteristics, assembly process,
package materials, and application. Hence, Reliability Engineering is involved in evaluating all critical factors of reliability, starting
with the design and first prototype functional circuit. From analysis, modification of design, wafer fabrication, and assembly,
process changes can be implemented to enhance the reliability of
the product. Approval is given for the release of new product to
manufacturing only after the reliability of the product is established as acceptable within standard norms.

Flow charts that delineate Fabrication processing are regarded as
proprietary and are not available for external dissemination without prior approvals from the R & QA Manager and respective
ProducVOperations Vice President. Applicable Assembly Packaging Flow Charts are Available upon request.
Flow charts for Customer Hi-Reliability Products are documented
by a detailed lot traveler which defines all sequential operations,
manufacturing inspection points, Customer Source Inspection
points, and Quality Assurance product sample acceptance
points.

The Reliability department provides the Product group with a
number of programs to define product reliability levels. Among
these programs are: 1) Qualification, 2) Reliability, 3) Failure
A~alysis, and 4) Data Collection and Presentation.

In-Process Quality Control -

Quality Control is a system of
measurement and surveillance. The System is comprised of
visual, dimensional, structural, and electrical characterization of
material from incoming receipt of raw goods to outgoing finished
product. Information obtained provides management with an
overview on the state-of-the-process by specifically quantifying
position of product yield, quality, and reliability.

Qualification Program of New Products and Processes:
•

4-3

Procedures for qualification of new product designs require
Reliability participation and approval in design reviews,
documentation, characterization, and reliability stress
studies.
.

Failure Analysis Support Activities Include:

• New package qualification is approved and released for
production by Reliability after prescribed environmental
tests have been successfully completed.
• Qualification of a new product is granted only after Quality
and Reliability have completed evaluation of process control studies. Significant modifications to existing processes
are treated as new processes for the purpose of qualification.
• Proper documentation of all changes to process steps and
procedure, and of any new or improved designs or material,
is assured by Reliability's approval.

• Qualification 01 existing products for new applications.
• Customer Qualifications. Reliability is responsible for review and acceptance of all customer requirements. When
qualification programs or special testing is required, Reliability designs and implements appropriate test plans and
coordinates with customer.
• Failure analysis, in support of In-Process Quality Control
monitors, is handled by Reliability through Failure Report
Requests. This support includes such services as visual
inspection, metallography, thickness measurements,
selective etching, and die probing.
• Customer's requests for failure analysis are filled by Reliabiltiy, which coordinates all replies to customers and
approves all correspondence outside the Company.
• Where Reliability has determined that corrective action is
necessary prior to the release of product for shipment, or
to proceed further in production processing, a Corrective
Action Request is generated by Reliability. No shipment
may occur if the integrity of product reliability would be
jeopardized.

Reliability Monitor Programs:
• Device and Package Reliability Monitor Programs are
effected for all packages using a variety of device types to
maximize data usefulness and to evaluate cost effectiveness of eqUipment.
• Packages are evaluated using all applicable methods of MI
STD-883; Level B, or MIL-STD-750, as appropriate. Data
are reported, as specified, in detailed procedures for each
package-chip combination. Package Monitor programs
include, but are not limited to, the following general tests,
using the appropriate conditions specified in MIL-STD-883,
Level B, Method 5005:
Condition

Reporting and Publication of Data:
Qualification test reports are prepared and distributed by
Reliability for all certified products and processes which have
been formally qualified and released for manufacturing.

Method

Operating Life (HTRB)

1005

Steam Pressure (Molded packages)

.N/A

Temperature Cycling

1010

Package Hermeticity

1014

Intermittent Opens (Molded package)

N/A

Salt Atmosphere (Initial Qual, only)

1009

Constant Acceleration

2001

Mechanical Shock (Initial Qual, only)

2002

Solderability

2003

Lead Integrity

2004

Vibration (Initial Qual, only)

2007

Biased Temperature Humidity
(Molded packages)

N/A

Reliability is responsible for aSSisting the Marketing department in the preparation of publications for distribution to field
sales locations and to customers.
Presently, the in-house Reliability Assurance testing is supplemented by testing done at outside Test Laboratories that have
been approved by D.E.S.C. for performing MIL-STD testing.
In addition, Reliability Assurance maintains a routine monitor
of commercial grade finished product to evaluate reliability
attributes against internally published norms. Products and
packages are deliberately selected to represent typical characteristics and conditions of manufacturing - with the following
considerations given:
• Design complexity and fabrication processing technology.
• Package type/assembly construction and materials.
• Assembly plant location.
Supertex reliability data for standard product is published for
internal use. Specific reliability information is made available to
customers upon request.

• Accelerated Stress Monitor Programs are conducted to
obtain til']1ely feedback for process evaluations, as well as
for ultimate device capability studies.

Plant Clearance Inspection - Supertex maintains a Final OutgOing Inspection on Finished asssembleditested product to
ensure that all conditions of processing have been satisfied·and
that support documentation, as specified by contract, is maintained for each shipped lot.

Failure Analysis:
It is the policy of Supertex to perform analysis of defective
product and utilize the resulting findings to improve product
yield and integrity.
• Reliability Engineeering also performs failure analysis in
mode and the mechanism of all failures (both from routine
reliability tests and customer returns).
•

Provisions for the control of shipped product during the Outgoing
Piant Clearance Final Acceptance Program are structured to
ensure product workmanship guarantees are met.

4-4

Summary
Supertex maintains R & QA Programs at critical operations to
assure that products are manufactured under a documented and
controlled system for consistency in workmanship standards (fit,
form, function, and reliability).
The following Standards and Specifications have been integrated
into Supertex's manufacturing operations and process control
programs:
• FED-STD-209

• MIL-M-38510
• MIL-Q-9858
• MIL-I-45208
• MIL-S-19500
• MIL-STD-105
• MIL-STD-750
• MIL-STD-883
• MIL-STD-202

Clean Room and Work Station
Requirements, Controlled
Environments.
Microcircuits, General
Specification For.
Quality Program Requirements.
Inspection Systems.
Semiconductor Devices, General
Specification For.
Sampling Procedures and Tables for
Inspection by Attributes.
Test Methods for Semiconductor
Devices.
Test Method and Procedures for
Microelectronics.
Test Methods for Electronic and Electrical Component Parts.

..

• MIL-STD-45662
Calibration System Requirements.
• Special Customer Specifications

4-5

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Alphanumeric Index and Ordering Information

~ll

Company Profile

..

Application Notes

•
i

Static Handling Procedures and Quality Assurance

~

Process Flow

..

DMOS Product Family

~

N· and p. Channel Low Threshold MOSFETs

_
i
I

DMOS Discretes N-Channel

~
I

DMOS Discretes P-Channel

•

DMOS Arrays and Special Functions

•

HVCMOS High Voltage ICs

~

CMOS Consumer/Industrial Products

~

Lead Bend Options and Surface Mount Packages

.-

Package Outlines

..

Representatives/Distributors

~

"

!!iupertex inc.
HVCMOS Standard Product Flow

INCOMINGOC
PHOTOMASK INSPECTION

OC FINISHED
WAFER INSPECTION

WAFER
FABRICATION

DIE ORDERS TO
PLANT CLEARANCE

POSTSORTOA
VISUAL INSPECTION

CUSTOM WAFERS TO
PLANT CLEARANCE

1----1 WAFER ELECTRICAL
TEST (WAFER SORT)

OPTIONAL)
STABILIZATION
BAKE

GROSS LEAK
100% AND/OR 1% AOL

OPTIONAL
STABILIZATION
BAKE

MARK
SOME DEVICES MARKED
AT THIS POINT

TEMPERATURE.
CYCLE

CONSTANT
ACCELERATION

FINE LEAK
100% AND/OR 1% AOL

(OPTIONAL)
TEMPERATURE
CYCLE

MARK
SOME DEVICES MARKED
AT THIS POINT

INCOMINGOA
INSPECTION MECH./VIS
AND ELECT.

BURN-IN
IN-HOUSE SAMPLE
AND/OR 100%

POST BURN-IN
ELECTRICAL TEST
100%

FINAL OA
INSPECTION
MECHANICAL/VISUAL
AND ELECT. (0.65% AOL)
ISD DEVICES 1.5% AOL)

FINAL ELECTRICAL
TEST

QA INSPECTION:
PLANT CLEARANCE

Note: Quality Assurance shall exercise the option to incorporate this screen to assure quality workmanship and conformance guarantees.

5-1

"§upertex inc.
DMOSStandard Product Flow
INCOMING QC
PHOTOMASK INSPECTION

SAW
AND
VISUAL

WAFER ORDERS TO
PLANT CLEARANCE

DICE ORDERS TO
PLANT CLEARANCE

QC
FINISHED WAFER
INSPECTION

WAFER
FABRICATION

STABILIZATION
BAKE: 100%
24 HOURS AT 150'C

HERMETIC

FINE LEAK
1.0% AQL

POST MOLD
CURE

WAFER ELECTRICAL
TEST (WAFER SORT)
100%

POST SORT QA
INSPECTION
VISUAL /ELECTRICAL

ASSEMBLY

TEMPERATURE CYCLE'
5 CYCLES -55'C TO +150'C

INCOMING QA
INSPECTION: MECHIVIS
AND ELECT.

STABILIZATION BAKE'
100% 24 HOURS AT 150'C

FINAL QA INSPECTION
MECHIVIS AND ELECT.
0.65% AQL

WAFER
BACKSIDE
PROCESS

FINAL
ELECTRICAL
TEST

IN·PROCESS QA
ELECTRICAL TEST

BOX STOCK
INVENTORY

QA INSPECTION:
PLANT CLEARANCE

*Note: Quality Assurance shall exercise the option to incorporate this screen to assure quality workmanship and conformance guarantees.

5-2

"§upertex inc.
HVCMOS IC Process Option Flow Chart
RB PRODUCT FLOW
(SIMILAR TO MIL-STD-883 CLASS B)

COMMERICAL PRODUCT FLOW

Preseal Visual

Preseal Visual

Method 20t 0, Condition B

Supertex Standard

Stabilization Bake

Stabilization Bake

Method 1008, Condition C,
24 Hrs. @ 150°C

Method t 008, Condition C,
24 Hrs. @ t 50°C

-

Temperature Cycle

(2)
Method 1010, Condition C,
10 Cycles, -65°C to + 150°C
10 min. Minimum@

Temperature Extremes
Constant Acceleration

(2)
Method 2001 , Condition E,

~b~~g g~~r 24-40 LD PKGS
30,000 G for 8-20 LD PKGS

Fine Leak
(2)
Method 1014, Condition A,

~rxBio-8 atm cc/sec
Gross Leak

(2)
Method 1014, Condition C
(4)

Trim and Mark

External Visual
(4)

Electrical Test
100% Go/No-Go,

[OptionaiEiectrtc.;!re;t
100% Go/No-Go,

I Tests@
Static and Functional
Max. Rated

Tests @ Max Rated

:....

Temperature
Electrical Test

(4)

100% Go/No-Go

Static Dynamic and

""'" ;,- -,I

Functional Tests @ 25°C

DynamiC/HTRB Burn-in

Dynamic Burn-in

Method 1015, Condition C,
48 Hrs. @ 125°C
Electrical Test
100% Go/No-Go

I Method
1015, Condition A
arC,
li8~.~125°C_ _

---I

Static Dynamic and
Functional Tests @ 25°C

I
I

~
I

I

__ J___ -,

l>100 Grade Option
HTRB Burn-in Method 1015,
Condition A, 160 Hrs @ 125°C

I

I

.J

I
I

Electrical Test
100% Go/No-Go
Static and Functional
Tests @ Max. Rated
Temperature

I

"--I---.J

Static and Functional

Group A
25°C Tests
Max. Rated Temp
Min. Rated Temp

I

Group B Sample
Per MIL-STD-883

~---

(3)

I

I
Electrical Test
100% Go/No-Go
Static and Functional
Tests @ Max. Rated
Temperature

~

Group A
25°C Tests

LTPD2
LTPD3
LTPD5

Note 1:

Processing consists of 100% screening and Group A.
Generic data available on request.

Note 2:

Hermetic packages only.

5-3

0.65%AQL

Note 3: Group C & D pertodic lot sampling per MIL-STD-883.
Note 4: As required.
All test methods are per MIL-STD-883 unless specified otherwise.

"

!iupertex inc.
DMOS Process Option Flow Chart

DMOS ARRAY
RB FLOW

SXFLOW

COMMERCIAL BURN-IN
SCFLOW

(SIMILAR TO JAN TX)

(SIMilAR TO Mll-STD-83
CLASS B) (1)

SXVFLOW

STANDARD PRODUCTS

SJ FLOW
(SIMilAR TO JAN)

(SIMILAR TO JAN TXV) (1)
Preseal Visual
Method 2072
Stabilization Bake
Method 1032,
24 Hrs. @ IS0'C

Stabilization Bake
Method 1032,
24 Hrs. @ 150'C

Stabilization Bake
Method 1032,
24 Hrs. @ IS0'C

Fine leak
(2)
Method 1071, Condition G
orH,
Maximum leak Rate
TO-3 - S x 10-7 atm cc/sec
Others - S x 10-8 atm cc/sec

Fine leak 1% AOl
(2)
Method 1071, Condition G
orH,
Maximum leak Rate
TO-3 - S x 10-7 atm cc/sec
Others - 5 x 10-8 atm cclsec

Fine leak 1% AOl
(2)
Method 1071, Condition G
orH,
Maximum leak Rate
TO-3 - 5 x 10-7 atm cc/sec
Others - S x 10-8 atm cc/sec

Fine leak 1% AOl
(2)
Method 1071, Condition G
orH,
Maximum leak Rate
TO-3 - S x 10-7 atm cc/sec
Others - S x 10-8 atm cc/sec

Gross leak
(2)
Method 1071, Condition C

Gross leak
Method 1071,

(2)
Gross leak
Method 1071, Condition C

(2)
Gross leak
Method 1071, Condition C

Electrical Test
100% Go/No-Go,
2S'C D.C. Parameters

Electrical Test
100% Go/No-Go,
25'C D.C. Parameters

Electrical Test
100% Go/No-Go,
25'C D.C. Parameters

Electrical Test
100% Go/No-Go,
2S'C D.C. Parameters

Group A
Subgroup A 0.65% AOl
Subgroup 1 VIS/MEC,
Subgroup 2 D.C. @ 25'C

Group A
Subgroup 1 Vls/MEC,
lTPDS
Subgroup 2 D.C. @ 2S'C,
lTPDS
Subgroup 3 D.C. Mln.lMax.,
lTPDS
Subgroup 4 A.C. l TPD S

Stabilization Bake
Method 1032,
24 Hrs. @ lS0'C
Temperature Cycle
Method 10S1
20 Cycles, -6S'C to + IS0'C
Constant Acceleration
V, Axis,
TO-3 -10,000 G,
Others - 20,000 G

fEledrica"'iTest 100% Go/No-Go,
I 25'C D.C. Parameters

(5)J
I

~--I----1
~TRGBBurn-in - (5)J

IL..::
~:~::.;:;
_ _ ;o~gndition
, _ _A,

--1I

Electrical Test
100% Go/No-Go
2S'C D.C. Parameters

(4)

(2)

(4)

(2)
Cond~ion

C

HTRGB Burn-in
(3)
Method 1039, Condition A,
48 Hrs. @ 150'C
Electrical Test
(4)
100% Read and Record,
25'C D.C. Parameters

HTRB Burn-in
Method 101S, Condition A,
160 Hrs. @ 12S'C

HTRB Burn-in
Method 1039, Condition A,
168 Hrs. @ IS0'C

HTRB Burn-in
Method 1039, Condition A,
96 Hrs. @ 150'C

Electrical Test
100% Go/No-Go
2S'C D.C. Parameters

Electrical Test
(4)
100% Read and Record,
2S'C D.C. Parameters

Electrical Test
100% Go/No-Go
25'C D.C. Parameters

(4)

Electrical Test
100% Go/No-Go,
Group A, Subgroup 2
Group A
Subgroup 1 VIS/MEC,
lTPD 5,
Subgroup 2 D.C. @ 25'C
lTPD S,
Subgroup 3 D.C. Min.lMax.,
lTPD 5,
Subgroup 4 A.C. l TPD S

Group A
Subgroup 1 VIS/MEC,
lTPD 5,
Subgroup 2 D.C. @ 25'C
lTPD5,
Subgroup 3 D.C. Mln.lMax.,
lTPD 5,
Subgroup 4 A.C. l TPD 5

Group A
Subgroup 1 VISIMEC,
lTPD 5,
Subgroup 2 D.C. @ 2S'C
lTPD 5,
Subgroup 3 D.C. Min.lMax.,
lTPD5,
Subgroup 4 A.C. l TPD 5

Note 1: Processing consists of 100% screening and Group A only. Preseal Visual applies to ·SXV· version only.
Note 2: Hermetic packages only.
Note 3: HTRGB-High temperature reverse gate bias.
Note 4: Read and Record with delta and percent .values Is optional.
Note 5: Optional.
All test methods are per Mll-STD-750 unless specified otherwise.

5-4

Alphanumeric Index and Ordering Information
Company Profile
Application Notes
Static Handling Procedures and Quality Assurance
Process Flow
DMOS Product Family

N- and P- Channel Low Threshold
DMOS Discretes N-Channel
DMOS Discretes P·Channel

DMOS Arrays and Special Functions
HVCMOS High Voltage ICs
CMOS Consumer/Industrial Products
Lead Bend Options and Surface Mount Packages
Package Outlines
Representatives/Distributors

«

"§upertex inc.
Understanding MOSFET Data
The following outline explains how to read and use Supertex
MOSFET data sheets. The approach is simple and care has been
taken to avoid getting lost in a maze of technical jargon.

The VNOI A data sheet was chosen as an example because this
is one of the most popular devices and has the largest choice of
packages. The product nomenclature shown applies only to'
Supertex proprietary products.

It:.
'flI!iupertex 'DC.

VN01A

~ JJ
Type of Channel
Device Structure
V:

T:

A:

Vertical DMOS
(discretes & quads)
Low threshold
vertical DMOS
discretes

Voltage Range

N Channel, or

Suffix

P Channel

L:

A:
C:
D:
E:
F:
•

Design
Supertex Family
number

Lateral DMOS
arrays

•

Min BVosslvoltsl

20, 40
40, 60, 90, 100
160, 200, 240
350, 400
450, 500
550, 600
Some A range devices not
available in 40, 90 & 100V
Some C range devices not
available in 240V

Advanced DMOS Technology
These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,

these devices are free from thermal runaway and thermallyinduced secondary breakdown.
Supertex vertical DMOS power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speed are desired.

12'\

This section outlines main
features of the product

\;:!31

N-Channel Enhancement-Mode
Vertical DMOS Power FET s

"---Product Summary
BY... ' R"stOM) ID(ON)
BVOQ8 (max) (min)
40V

6f1V
90V

I

30
30
30

2.OA
2.0A
2.0A

T0-39

TO-82

T0.52

VN0104N2 VN0104N3 VN0104N9
VN0106N2 VN0106N3 VN0106N9
VN0109N2 VN0108N3 VN0109N9

Order ....- I Package
Quad POP Quad COP Quad CI..CC
TO-22O
VN0104N5
VN0106N5
VN0109N5

I

Drain to source breakdown
voltage & drain to gate
breakdown voltage

VN0104N6
VN0106N6

VN0104N7
VN0106N7

DICE

-

VN0104NO
VN0106NE VN0106NO
VN0109NE VN0109NO

I
Maximum resistance from
drain to source when device
is fully turned on

Minimum drain current when
device is fully turned on

Package Options

~
ifj'

TO·220

.

Hermetic metal can
• Moderate power
dissipation
• Industrial/Military
applications

BV""" RDS(IlN)
BV""" (max)

1_
(min)

TO·92

Plastic
,. Low power

Plastic
• High power
• Commercial/
Industrial
applications

Hermetic metal can
Low power
Industrial/Military
applications

• Mainly commercial
applications
• Cost effective

Order Number I Packa e
T()'39

T()'92

T()'52

TO-22Q

QuadP-DIP

Quade-DIP Quade-Lee

40V

30

2.0A

VN0104N2 VN0104N3 VN0104N9 VN0104N5 VN0104N6

VN0104N7

60V

3Q

2.0A

VN0106N2 VN0106N3 VN0106N9 VN0106N5 VN0106N6

VN0106N7

90V

30

2.0A

VN0109N2 VN0109N3 VN0109N9 VN0109N5

• 4 dice in one package

Dice

VN0104ND
VN0106NE

VN0106ND
VN0109ND

TO-3

16·TERMINAL Lee

Ceramic Leadle" Chip Carrier

;.c

":J

TO-52

TO-39

Dual in line plastic
• 4 dice in one package
• Commercial/Industrial
applications

NO: Die in waffle pack
Die can be visually
inspected to
commercial (standard)
or military visual
criteria (specify
while ordering) .

'4.LEAD DIP

Hermetic metal can
• Very high power
• Commercial/lndustrial/
Military requirements

Dual in line ceramic
.4 dice in one package
Industrial/Military
requirements

NW:

Die in wafer form

• 4" diameter wafers
• Reject die are inked

Extreme conditions a device can be
subjected to electrically and thermally.
Stress in excess of these ratings will
usually cause permanent damage.

Ratings given in product summary

I

I

.. Absolute Maximum Ratings
i"'"'- Drai n-to-Source Voltage

VGS
• All Supertex FETs are rated for ±20V
• ± voltage handling capability allows quick
turn off by reversing bias.
• External protection should be used when
there is a possibility of exceeding this
rating. Stress exceeding ±20V will result
in gate insulation degradation and eventual
failure.

___ Drai n-to-Gate
Gate-to-Source Voltage
- O p e rating and Storage Temperature

r

• All Supertex devices can be stored and operated satisfactorily
within these junction temperature (TJ) limits
• Appropriate derating factors from curves and change in
parameters due to reduced/elevated temperatures have to be
considered when temperature in not 25° C
• Operation at TJ below maximum limit can enhance operating life

6-1

Sol

BVDGS

±20V

-55°C to +150°C

dering Temperature

Maximum allowable temperature at leads
while soldering, 1.6mm away from case for 10
seconds.

..

/lja
Thermal resistance from
junction to air.
Depends mainly on
package and die size.

•
Thermal Characteristics

/lje

Device characteristics affecting
limits of heat produced and removed
from device. Die size, ROS{ON), and
packaging type are the main factors
determining these thermal
limitations.

Pac:kqll

IDlcontinuousl

IDlpulMdl

Power Dissipation

(Note 3)

TO-39

O.SA

TO-92

T()'52

a.SA
a.SA

TO·22O

1.M

2.SA

~.

,~

.TC"~C

.c!w

'C/W

3.SW

125

36

170
17.

I.OW
I.OW

2.0A
2.0A
2.5A

Plastic DIP

Thermal resistance from junction to
case.
Depends mainly on
package and die size
To determine TJ use equation
TJ = Po x lIie + TA

7.

lS.OW

12'
12'8

•
•

lOR

IORM

.08A
C,SA
C.SA
I.SA

2.SA

2.0A
2.0A

2,SA

See OMOS Arrays and Special Functions section.

Ceramic DIP

J
10RM
300 ,..5, 2% duty cycle pulsed
Current handling capability of drain
to source diode.
Factors affecting this
parameter same as 10 (pulsed)

10 (continuous)

•

Maximum Continuous current carrying
capability of device.
Depends mainly on:
A. ROS{ON) - on state resistance
B. PO - maximum power
dissipation for package
C. Die size
D. Maximum junction temperature

•

lOR
Continuous current handling
capability of drain to source diode.
Factors affecting value same as
10 (continuous)

•

10 (pulsed)
Maximum non-continuous pulse current
carrying capabilty for a 300,..5 2% duty
cycle pulse.
Depends mainly on:
A. ROS{ON)
B. Po max.
C. Diameter of bonding wire
D. Die size
E. Maximum junction temperature

•

Power Dissipation

-

•
•

Maximum power package
can dissipate when case
temperature is 25°C.
When case temperature is
higher than 25° C, use
PO vs. Tc curve to
determine dissipation
permissible.

6-2

The following DC parameters are 100% tested with 300 "S. 2% duty cycle pulse at 25'C; avoss.
'VGSITH), loss, IOION) & ROSION) .
.lVGSITH) and .lRoSION) are guaranteed by design ie., when device is functional for other DC
parameters, these two parameters will not deviate from published values.

Since a representative sample is adequate to assure consistency of specs, A.C. parameters
are sample tested on a lotlbatch basis.
High temperature testing on sample basis when requested with hi-rei processing.
Refer \0 section 3 "power MDS stnJcIures" for test circuits used for measurement

Electrical Characteristics (@ 25° C unless otherwise specified)

avOSS
0

Please see product summary (part 1)

0

Positive temperature coefficient.

i--

See curve aVOSS VS. TJ.
VGSITH)
Voltage required from gate to source to

0

turn on device to certain ID current value
given in "condition" column
ID measurement condition is low for

BVOSS

r---

r--

-

10(ONI

ON·St.te OrainCurrenl

ROSION)

StaticOr.in·to·Source
ON·State Resistance
Change in ROS(ONI With Temperature
Forward Transcondyctance
Input Capacitance
Cornmon Source Output Capaeitance
Raverse Transfer Cap'CltanCB
Turn·ON Delay Time
Rise Time
Turn·OFF Delay Time
Fall Time
Oiodlr Forw.rd Voltage Drop
R'\IIIrSe RlCover..,. Tima

0.'
2
3
2.3

t:.ROSIONI
CISS
cOSS

CI'ISS
tdlON)
I,

tdIOFF)

0

"

VSD

I"

0

0

0

Since the gate is insulated from the rest of
the device by a silicon dioxide insulating
layer, this pa~ameter depends on
thickness/integrity of layer and size of
device.
Measured at maximum permissible
voltage from gate to source:.±20V.
values of this parameter are often
tens/hundreds of times less than
published maximum value.

0

U."
V

-3.8
0.1

2.4

V

-5.6

mVI"C

100

.A

100

"A

",·c

mU

IIOS" 25V, 10

A

•

a

0.70

3
1

400
45
20
2

,. .,

2

300

VGS = VOS. 10 = lmA
10" lmA, VGS" VOS
VGS = ±20V, VOS = 0
VGS" 0, VOS = Max Rating
VGS .. 0, VOS" 0.8 Mal( Rating
TA" 12S"C
VGS" 5V, VOS" 25V
VGS'" 10V, VOS" 26V
VGS= 5V, 10" 250mA
VGS" 10V, 10" lA
la-lA, VGS-IOV

1.0
2.50
4.50

Conditions

ID=lmA,VGS"O

= a.5A

80

•,

• ,
5

8

5
1.2

8
1.8

VGS = 0, VOS = 2611
f .. lMHz

"'

1100" 25V, 10 = lA,

V

ISO" ,

"'

so=

RS-RL'"SOSl

.

as-

• Positive
temperature
coeffiCient.
• Enhances

0

0

devices may be used.

during parallel
0

operation.

This is the leakage current from drain to
source when device is fully turned off.
Measured byapplying maximum permissible

Typical value of ROSION) can be calculated

at various VGS conditions by using output
characteristics or saturation characteristics family of curves (VGS Vs 10).
0

ROS(ON)

increases with higher drain

currents.
ROSION) Vs. IOION) curve has a slight slope

for values low values of
rapidly for high values.

I

losS

0

DeSigners should use maximum values
for worst case condition.
When better turn on characteristics (ie.,
low ROSION)) is required for logic level
inputs, Supertex's low threshold TN & TP

stability due to

current sharing

Electrical screening is done at 100nA

0

Drain to source resistance measured
when device is partially turned on at VGS
= 5V, and fully turned on at VGS = 10V.

since test equipment functions slowly at
lower values, which is not practical for
mass production.
Consult factory for screening lower
values.

IOION)
0

0

voltage between drain and source (BVoss)
0

M"

ROSION)
aROS(ON)

IGSS

TV.

90
60
40

IDSS

a"

voltage reduces when
temperature increases and vice versa.
value at temperature other than 25' C
can be determined by VGSITH)
(normalized) VS. TJ curve.

VN0106

0.8

lass

Threshold

VN0109

Breakdown Voltage

VN0104

lWGS(th)

aVGSITH)

MI.

Drain·ta-Source

Gate Threshold Voltage
Change in VGS(thl with Temperature
Gate Body Leakage
Zero Gate Voltage Drain Current

VGS(th)

small die and higher for larger die

0

P'r,mtt"

Symbol

0

and gate shorted to source (VGS=O)
Special electrical screening possible at lower

Defined as the minimum drain current
when device is turned on.
Supertex measures 10rON) min. at two test
conditions:
VGS

= 5V

and VGS

= 10V.

to give the

designer a look at both logic level turn on

values since max. published values are higher

and full turn on.
Although Supertex specifies a typical
value of 1010N), the designer should use

to achieve practical testing speeds.

minimum value as the worst case,

6-3

10,

but rises

SWITCHING CHARACTERISTICS

•
•

GFS

Extremely fast switching compared to
bipolar transistors, due to absence of
minority carrier storage time during turn
off.
Switching times depend almost totally
on i nterelectrode capacitance, Rs
(source impedance) and RL (load
impedance) as shown on test circuit.

•
•

Represents gainof the device and can be
compared to HFE of a bipolar transistor.
Value is the ratio of change in 10 for a
change in VGS

•

C ISS ' C RSS' COSS

•

Please see section 3 in data book "power
MOSFET Electrical Performance" for
interelectrode capacitances and equivalent circuit.

•

Supertex interdigitated structures have
lowest CISS in the industry for comparable die sizes and exhibit excellent
switching characteristics.

•

Values of these capacitances are high at
low voltages across them. Please see
capacitance vs. Vos curves for details.

•
•

Negligible effect of temperature on capacitances.

TO(ON)
During this period, the drive circuit
changes CISS to up to VGS(TH). Since
no drain current flows prior to turn on,
Vos and consequently elss remain
constant. Region I on the VGS vs. aG
curve shows linear change in voltage
with increasing aGo

•

The following equation may be used for
calculating effective value of C s with
"Miller Effect":
I s
CISS = C GS + (1 + GFS

RLl CGO

~"

Gate Drive Dynamic Characteristics
10

Cgd

A~

-

GFS = .llo
IlVGS
Rises rapidly with increasing 10, and
then becomes constant in the saturation
region. See VGS vs. 10 curve.

VDS=10V

-r

1

17VDS =40V

8

Cds

~
..J
0

Cgs

c
'"
>
Cl

SOURCE

I

I

6

m

II

/

4

2

~

Crss = Cgd
0

)

II

)

V

VV

Ciss = Cgd + Cgs
Coss = Cgd + Cds

II

1/ V

II
0

0·2

0'4

0'6

0,8

QG (NANOCOULOMBS)

6-4

1·0

Electrical Characteristics (@ 25° C unless otherwise specified)
Symbol
BVDSS

VGSllh)
lIVGSllh)
IGSS
lOSS

-

~

-

VN0109

Breakdown Voltage

VN0106
VN0104

Gate Threshold Voltage

Typ

Min

O.B

Zero Gate Voltage Drain Current

ROSION)

Static Drain-to-Source

ON· State Resistance
Change in RDS(ON) with Temperature
Forward Transcondyctance
Input Capacitance

0.5
2
3
2.3

1.0
2.50
4.50
2
0.70
400
45
20
2

300

Common Source Output Capacitance

CRSS

Reverse Transfer Capacitance

IdION)
Ir
IdIOFF)

Turn-ON Delay Time

If

Fall Time
Diode Forward Voltage Drop

Irr

Reverse Recovery Time

TR

---

5
3
1

1.8

Sl

%tc
pF

VGS - VOS, 10 = 1mA
10 = 1mA, VGS = VOS
VGS - ±20V, VOS - 0
VGS - 0, VOS - O.B Max Raling
TA = 125"C
VGS = 5V, VOS = 25V
VGS = 10V, VOS = 25V
VGS - 5V, 10= 250mA
VGS = lOV, 10 - 1A
10 1A, VGS - 10V
VOS - 25V, 10 - 0.5A

VGS

0, VOS= 25V

f= 1MHz

ns

VOO - 25V, ID - 1A,
RS = RL = 50n

V

ISO - 2.5A, VGS - 0
ISO - 1A, VGS = U

ns

TRR

•

When CISS is driven to a voltage
exceeding VGSITH), conduction from
drain to source begins. GFS increases
causing increase in C,SS due to "Miller
Effect". Charge requirements for Region
II increase considerably. Gain stabilizes
in Region III and Miller Effect is nullified,
resulting in a linear change in VGS for
increase in QG.

•

TD(OFF)

VSD

•

•

The sequence of events now begins to
reverse. CISS discharges through Rs
and the 50 n resistor. The rise of Vos is
initally slowed by increase of output
capacitance.

-

TF

•

ID = 1mA, VGS = 0

VGS == 0, VOS = Max Rating

uA

mts
60
25
5
5
B
9
B

5
6
5
1.2
400

Turn-OFF Delay Time

V

mVtC
nA

A

3

Rise Time

VSD

-

2.4
-5.5
100
1
100

-3.B
0.1

Conditions

Unit

V

Gate Body Leakage

ON·State Drain Current

•

Max

90
60
40

Change in VGS(thl with Temperature

101ON)

1IR0SION)
GFS
C,SS
Coss

r--

Parameter
Drain-ta-Source

Vos rises rapidly as the output capacitance falls.

6-5

•

The reverse recovery time is the time
needed for the carrier gradient, formed
during forward biasing, to be depleted
when the biasing is reversed.
An external fast recovery diode may be
connected from drain to source to improve recovery time.

This is the forward voltage drop of the
parasitiC diode between drain and
source.
Diode my be used as a commutator in H
bridge configurations or in a synchronous rectifier mode. Excessive fly back
voltages may be clamped by this diode
in a totem pole configuration.

•

"§upertex inc.
DMOS Products
switching speeds, and low threshold voltages. Available in a wide
variety 01 packages types, they give the designer flexibility using
state-ol-the-art power semiconductor technology.

The Supertex DMOS Power MOSFET lamily utilizes both vertical
and lateral, double-diffused MOS processes. These DMOS Power
MOSFETs are ideally suited lor a wide range 01 switching, driving,
and amplifying applications. They feature high input impedance, fast

N-Channel Low Threshold MOSFETs
Device
Family

BV DSS
Min (V)

TNOl
TNOl
TN02
TN05
TNOS
TNOS
TNOS

20,40
SO, 100
20 40
200,240
20 40
SO, 100
200,240

RDS(ON)
Max (ohms)
1.8
3.0
0.75
10.0
0.75
1.50
S.O

IO(ON)
Min (A)

CISS
Typ (pf)

VpS(lh)
Max (V)

2.0
2.0
4.0
0.3
4.0
3.0
1.0

45
50
85
45
85
85
85

1.S
1.S
1.S
1.5
1.S
1.S
1.S

Note 1: Refer to Arrays and Special Functions section for package. available.

TO·39

•
•
•
•
•
•
•

Package Options
T0-92 TO·220 Quad 1

•
•

•
•

•
•
•

•
•

•

Ole

•
•
•
•
•
•
•

P-Channel Low Threshold MOSFETs
Device
Family

BVDSS
Min (V)

TPOl
TP02
TPOS
TPOS
TPOS

20,40
20 40
20,40
SO, 100
lS0,200

RDS(ON)
Max (ohms)
4.0
2.0
2.0
3.5
12.0

IO(ON)
Min (A)

CISS
Typ (pf)

VpS(lh)
Max (V)

45
85
85
85
85

2.4
2.4
2.4
2.4
2.4

0.85
2.0
2.0
1.5
0.75

Note 1: Refer to Arrays and Special Functions section for packages available.

S-S

T0-39

•
•
•

•
•

Psckage Options
TO·92 TO-220 Quad 1

•
•
•
•
•

•
•

•

Die

•
•
•
•
•

N-Channel DMOS Power FETs
Device
Family

Min (V)

VN01
VN01
VN02
VN02
VN03
VN03
VN03
VN05
VN05
VN06
VN06
VN06
VN11
VN11
VN12
VN12
VN13
VN13
VN21
VN22
R5202
R521 2
R531 2

40,6090
160,200
40,60,100
160,200
350,400
450,500
550,600
350,400
450,500
350,400
450,500
550,600
60, 100
160,200
40,60,100
160,200
4060100
160,200
60, 100
60, 100
100
60
60

BVoss

RDS(ON)
Max (ohms)
3.0
10.0
2.0
6.0
2.5
4.0
6.0
35.0
60.0
10.0
16.0
20.0
0.7
3.0
0.3
1.0
8.0
40.0
3.0
0.3
0.3
0.3
0.18

ID(ON) .
Min (A)

CISS
Typ (pf)

2.0
0.4
3.0
1.0
3.0
2.0
1.5
0.25
0.15
0.75
0.50
0.25
8.0
2.0
20.0
6.0
0.50
0.25
0.5
8.0
8.0
8.0
12.0

45
45
85
75
550
550
550
45
45
85
85
85
300
300
600
600
25
25
45
400
500
500
600

T0-3

•
•
•

•
•
•
•

TO-39

•
•
•
•
•
•
•
•
•
•
•

Package Options
TO-52 TO"92 TO-220 Quad!

•

•
•
•

•
•
•
•
•
•

•
•
•
•
•
•

•

•
•
•
•
•
•

•
•

•

•
•
•
•
•
•
•

•

•
•

•

Ole

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•

Note 1: Refer to Arrays and Special Functions section for packages available.
Note 2: TO·220 compatible lead bend available.

P-Channel DMOS Power FETs
Device
Family

Min (V)

RDS(ON)
Max (ohms)

VP01
VP01
VP02
VP02
VP03
VP03
VP05
VP05
VP06
VP06
VP11
VP11
VP12
VP12
VP13
VP13
R9521 2
R95222
R9523 2

40,60,90
160,200
40,60,100
160,200
350,400
450,500
350,400
450,500
350,400
450,500
60, 100
160,200
40,60,100
160,200
40,60,100
160,200
60
100
60

8.0
25.0
4.0
16.0
6.0
7.5
75.0
125.0
25.0
25.0
2.0
5.0
0.8
2.5
25.0
100.0
0.6
0.8
0.8

BVoss

ID(ON)
Min (A)

CISS
Typ (pf)

0.50
0.35
2.0
0.75
1.5
1.0
0.25
0.10
0.40
0.20
5.0
1.5
6.0
4.0
0.25
0.10
6.0
5.0
5.0

40
40
75
75
600
500
45
45
75
75
325
325
600
600
25
25
400
400
400

Note 1: Refer to Arrays and Special Functions section for packages available.
Note 2: TO-220 compatible lead bend available.

6-7

TO-3

•
•

•
•
•
•

T0-39

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Package Options
TO-52 TO-92 TO-220 Quad!

•

•
•
•
•
•
•
•
•

•
•
•

•
•

•
•
•
•
•
•

•
•
•
•
•
•

•
•

•

Die

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

"§upertex inc.
I

DMOS Power FETS
The following table represents an industry cross-reference for power MOSFETs. The Supertex devices are a "form, fit, and function"
replacement for the industry standard part types, but subtle differences in charateriestics and/or specifications may exist.

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

2N6659
2N6660
2N6661
2N6755
2N6756

2N6659
2N6660
2N6661
VN1206N1
VN1210N1

2SK176
2SK176H
2SK196H
2SK213
2SK214

VN1220N1
VN1220N1
VN0116N2
VN0216N5
VN0216N5

AN0110NA
AN0120NA
AN0130NA
AN0140NA
BS107P

AN0120NA
AN0120NA
AN0130NA
AN0140NA
VN1320N3

BUZ60B
BUZ63B
BUZ72
BUZ72A
BUZ73A

VN0340N5
VN0340N1
VN1210N5
VN1210N5
VN1220N5

2N6757
2N6757
2N6759
2N6761
2N6761

VN1216N1
VN1216N5
VN0335N1
VN0345N5
VN0345N1

2SK215
2SK216
2SK216K
2SK220
2SK221

VN0220N5
VN0220N5
VN0220N5
VN1216N1
VN1220N1

BS107PT
BS170
BS170P
BS250
BS250P

VN1320N3
VN0106N3
VN0106N3
VP0106N3
VP0106N3

BUZ74
BUZ74A
BUZ76
BUZ76A
D80AK2

VN0350N5
VN0350N5
VN0340N5
VN0340N5
VN0206N3

2N7000
2N7000
2N7007
2N7008
2N7009

2N7000
VN0106N3
2N7007
2N7008
VN0550N3

2SK259
2SK260
2SK294
2SK295
2SK296

VN0335N1.
VN0340N1
VN1210N5
VN1210N5
VN0335N5

BSR78
BSS100
BSS101
BSS110
BSS88

TP0604N3
VN0210N3
VN0120N3
VP0106N3
TN0524N3

D80AL2
D80AM2
D80AN2
D84BK2
D84BL2

VN0210N3
VN0216N3
VN0220N3
VN1206N5
VN1210N5

2N7014
2SJ101
2SJ102
2SJ117
2SJ121

VN1110N5
VP1204N5
VP1206N5
VP0340N5
VP1204N5

2SK298
2SK31 0
2SK311
2SK319
2SK345

VN0340N1
VN0340N5
VN0345N5
VN0340N5
VN1204N5

BSS89
BSS98
BST70A
BST72
BST72A

VN0220N3
VN0106N3
VN0109N3
VN1310N3
VN1310N2

D84BM2
D84BN2
D84B01
D84B02
D84CK2

VN1216N5
VN1220N5
VN0335N5
VN0340N5
VN1206N5

2SJ48
2SJ49
2SJ50
2SJ55
2SJ56

VP1216N1
VP1216N1
VP1216N1
VP1220N1
VP1220N1

2SK346
2SK382
2SK383
2SK398
2SK399

VN1206N5
VN0350N5
VN1210N5
VN1210N1
VN1210N1

BST74
BST74A
BST76
BST76A
BUZ171

VN0220N3
VN0220N3
VN0220N3
VN0220N3
VP1206N5

D84CL2
D84CM2
D84CN2
D84C01
D84C02

VN1210N5
VN1216N5
VN1220N5
VN0335N5
VN0340N5

2SJ56H
2SJ76
2SJ77
2SJ78
2SJ79

VP1220N1
VP0116N5
TP0616N5
VP1220N5
VP0120N5

2SK400
2SK402
2SK408
2SK409
2SK411

VN1220N1
VN0340N1
VN0220N5
VN0220N5
VN0360N1

BUZ172
BUZ173
BUZ20
BUZ23
BUZ30

VP1210N5
VP1220N5
VN1210N5
VN1210N1
VN1220N5

D84CR1
D84CR2
D84DK2
D84DL2
D86DK2

VN0345N5
VN0350N5
VN1206N5
VN1210N5
VN1206N1

2SJ79K
2SK133
2SK134
2SK135
2SK175

VP0120N5
VN1216N1
VN1216N1
VN1216N1
VN1220N1

2SK413
2SK414
2SK428
2SK440
2SK441

VN1216N1
VN1216N1
VN1206N5
VN1220N5
VN0650N2

BUZ33
BUZ40
BUZ42
BUZ43
BUZ46

VN1220N1
VN0350N5
VN0350N5
VN0350N1
VN0350N1

D86DL2
IRF120
IRF121
IRF122
IRF123

VN1210N1
VN1210N1
VN1206N1
VN1210N1
VN1206N1

6-8

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

IRF130
IRF131
IRF132
IRF133
IRF220

VN1210N1
VN1206N1
VN1210N1
VN1206N1
VN1220N1

IRF722
IRF723
IRF732
IRF733
IRF820

VN0340N5
VN0335N5
VN0340N5
VN0335N5
VN0350N5

IRFF220
IRFF221
IRFF222
IRFF223
IRFF232

VN1220N2
VN1216N2
VN1220N2
VN1216N2
VN1220N2

IVN5200TNE
IVN5200TNH
IVN5201CND
IVN5201CNE
IVN5210CNF

VN1206N2
VN1210N2
VN1204N5
VN1206N5
VN1210N5

IRF221
IRF222
IRF223
IRF232
IRF233

VN1216N1
VN1220N1
VN1216N1
VN1220N1
VN1216N1

IRF821
IRF822
IRF823
IRF832
IRF833

VN0345N5
VN0350N5
VN0345N5
VN0350N5
VN0345N5

IRFF233
IRFF310
IRFF311
IRFF312
IRFF313

VN1216N2
VN0340N2
VN0335N2
VN0340N2
VN0335N2

IVN5210CNH
IVN5210KND
IVN5210KNE
IVN5210KNF
IVN5210KNH

VN1210N5
VN1204N1
VN1206N1
VN1210N1
VN1210N1

IRF320
IRF321
IRF322
IRF323
IRF332

VN0340N1
VN0335N1
VN0340N1
VN0335N1
VN0340N1

IRF9132
IRF9133
IRF9232
IRF9233
IRF9510

VP1210N1
VP1206N1
VP1220N1
VP1216N1
VP1210N5

IRFF320
IRFF321
IRFF322
IRFF323
IRFF332

VN0340N2
VN0335N2
VN0340N2
VN0335N2
VN0340N2

IVN5210TND
IVN5210TNE
IVN5210TNF
IVN5210TNH
IVN6000CNE

VN1204N2
VN1206N2
VN1210N2
VN1210N2
VN1206N5

IRF333
IRF420
IRF421
IRF422
IRF423

VN0335N1
VN0350N1
VN0345N1
VN0350N1
VN0345N1

IRF9511
IRF9512
IRF9513
IRF9520
IRF9521

VP1206N5
VP1210N5
VP1206N5
IRF9520
IRF9521

IRFF333
IRFF420
IRFF421
IRFF422
IRFF423

VN0335N2
VN0350N2
VN0345N2
VN0350N2
VN0345N2

IVN6000CNF
IVN6000CNH
IVN6000CNR
IVN6000CNS
IVN6000CNT

VN1210N5
TN0610N5
VN0340N5
VN0340N5
VN0345N5

IRF432
IRF433
IRF510
IRF511
IRF512

VN0350N1
VN0345N1
IRF510
IRF511
IRF512

IRF9522
IRF9523
IRF9532
IRF9533
IRF9610

IRF9522
IRF9523
VP1210N5
VP1206N5
VP1220N5

IRFG9113
IVN5000AND
IVN5000AND
IVN5000ANE
IVN5000ANF

TP0606N7
TN0104N3
TN0104N3
VN0206N3
VN0210N3

IVN6000CNU
IVN6000KNE
IVN6000KNF
IVN6000KNH
IVN6000KNR

VN0350N5
VN1206N1
VN1210N1
VN1210N1
VN0340N1

IRF513
IRF520
IRF521
IRF522
IRF523

IRF513
IRF520
IRF521
IRF522
IRF523

IRF9611
IRF9612
IRF9613
IRF9620
IRF9621

VP1216N5
VP1120N5
VP1116N5
VP1220N5
VP1216N5

IVN5000ANF
IVN5000ANH
IVN5000ANH
IVN5000SND
IVN5000SND

VN0210N3
VN0210N3
VN0210N3
VN0104N9
VN0109N9

IVN6000KNS
IVN6000KNT
IVN6000KNU
IVN6000TNE
IVN6000TNF

VN0340N1
VN0345N1
VN0350N1
TN0606N2
VN0610N2

IRF530
IRF531
IRF532
IRF533
IRF610

VN1210N5
IRF531
VN1210N5
VN1206N5
VN1220N5

IRF9622
IRF9623
IRF9632
IRF9633
IRFF110

VP1220N5
VP1216N5
VP1220N5
VP1216N5
VN1210N2

IVN5000SNE
IVN5000SNF
IVN5000SNF
IVN5000SNH
IVN5000TND

VN0106N9
VN0109N9
VN0109N9
VN0109N9
TN0104N2

IVN6000TNH
IVN6000TNR
IVN6000TNS
IVN6000TNT
IVN6000TNU

TN0610N2
VN0340N2
VN0340N2
VN0345N2
VN0350N2

IRF611
IRF612
IRF613
IRF620
IRF621

VN1216N5
VN1120N5
VN1216N5
VN1220N5
VN1216N5

IRFF111
IRFF112
IRFF113
IRFF120
IRFF121

VN1206N2
VN1110N2
VN1106N2
VN1210N2
VN1206N2

IVN5000TND
IVN5000TNE
IVN5000TNF
IVN5000TNF
IVN5000TNH

TN0104N2
VN0206N2
VN0210N2
VN0210N2
VN0210N2

IVN6001CNE
IVN6001CNF
IVN6001CNH
IVN6001KNE
IVN6001KNF

VN1206N5
VN1210N5
TN0610N5
VN1206N1
VN1210N1

IRF622
IRF623
IRF632
IRF633
IRF710

VN1220N5
VN1216N5
VN1220N5
VN1216N5
VN0340N5

IRFF122
IRFF123
IRFF130
IRFF131
IRFF132

VN1210N2
VN1206N2
VN1210N2
VN1206N2
VN1210N2

IVN5000TNH
IVN5200HND
IVN5200HNE
IVN5200HNF
IVN5200HNH

VN0210N2
VN1204N5
VN1206N5
VN1210N5
VN1210N5

IVN6001KNH
IVN6001TNE
IVN6001TNF
IVN6001TNH
IVN6002CND

VN1210N1
VN1206N2
VN1210N2
VN1210N2
VN1204N5

IRF711
IRF712
IRF713
IRF720
IRF721

VN0335N5
VN0340N5
VN0335N5
VN0340N5
VN0335N5

IRFF133
IRFF210
IRFF211
IRFF212
IRFF213

VN1210N2
VN1220N2
VN1216N2
VN1120N2
VN1216N2

IVN5200KND
IVN5200KNE
IVN5200KNF
IVN5200KNH
IVN5200TND

VN1204N5
VN1206N5
VN1210N5
VN1210N5
VN1204N2

IVN6002KND
IVN6002TND
IVN6100TNS
IVN6100TNT
IVN6100TNU

VN1204N1
TN0104N2
VN0640N2
VN0645N2
VN0650N2

...

I

6-9

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

IVN6200ANE
IVN6200ANF
IVN6200ANH
IVN6200ANM
IVN6200ANS

VN1206N5
VN1210N5
VN1210N5
VN1220N5
VN0340N5

MTM5N18
MTM5N20
MTM7N12
MTM7N15
MTM7N18

VN1220N1
VN1220N1
VN1216N1
VN1216N1
VN1220N1

MTP8N08
MTP8N10
MTP8N12
MTP8N15
MTP8P08

VN1210N5
VN1210N5
VN1216N5
VN1216N5
VP1210N5

RFL1N10
RFL1N12
RFL1N15
RFL1N18
RFL1N20

VN1110N2
VN1216N2
VN1216N2
VN1120N2
VN1120N2

IVN6200CND
IVN6200CNE
IVN6200CNF
IVN6200CNH
IVN6200CNM

VN1204N5
VN1206N5
VN1210N5
VN1210N5
VN1220N5

MTM7N20
MTM8N08
MTM8N10
MTM8N12
MTM8N15

VN1220N1
VN1210N1
VN1210N1
VN1216N1
VN1216N1

MTP8P10
PM1001L
PM1002L
PM1003P
PM1004P

VP1210N5
VN0210N3
VN0210N3
VN1110N5
VN1110N5

RFL1P08
RFL1P10
RFL2N05
RFL2N06
RFM12N08

TP0610N2
TP0610N2
VN1106N2
VN1106N2
VN1210N1

IVN6200CNR
IVN6200CNS
IVN6200CNU
IVN6200KNE
IVN6200KNH

VN0340N5
VN0340N5
VN0350N5
VN1206N1
VN1210N1

MTM8P08
MTM8P10
MTP10N05
MTP10N06
MTP10N08

VP1210N1
VP1210N1
VN1206N5
VN1206N5
VN1210N5

PM1006M
PM1006P
PM1010M
PM1010P
PM1201L

VN1210N1
VN1210N5
VN1210N1
VN1210N5
VN0216N3

RFM12N10
RFM15N05
RFM15N06
RFM3N45
RFM3N50

VN1210N1
VN1206N1
VN1206N1
VN0345N1
VN0350N1

IVN6200KNM
IVN6200KNR
IVN6200KNS
IVN6200KNU
IVN6300ANE

VN1220N1
VN0340N1
VN0340N1
VN0350N1
VN1306N3

MTP10N10
MTP12N05
MTP12N06
MTP12N08
MTP12N10

VN1210N5
VN1206N5
VN1206N5
VN1210N5
VN1210N5

PM1203P
PM1206P
PM1503P
PM1504P
PM1506M

VN1216N5
VN1216N5
VN1216N5
VN1216N5
VN1216N1

RFM4N35
RFM4N40
RFM6P08
RFM6P10
RFM8N18

VN0335N1
VN0340N1
VP1210N1
VP1210N1
VN1220N1

IVN6300ANF
IVN6300ANH
IVN6300ANM
IVN6300ANP
IVN6300ANS

VN1310N3
VN0210N3
VN1320N3
VN0635N3
VN0540N3

MTP15N05
MTP15N06
MTP1N45
MTP1N50
MTP1N55

VN1206N5
VN1206N5
VN0645N5
VN0350N5
VN0355N5

PM1506P
PM503L
PM506L
PM509P
PM510P

VN1216N5
TN0606N3
TN0606N3
VN1206N5
VN1206N5

RFM8N20
RFM8P08
RFM8P10
RFP12N08
RFP12N10

VN1220N1
VP1210N1
VP1210N1
VN1210N5
VN1210N5

IVN6300ANT
IVN6300ANU
IVN6300SNE
IVN6300SNF
IVN6300SNH

VN0545N3
VN0545N3
VN0106N9
VN0109N9
VN0109N9

MTP1N60
MTP20N08
MTP20N10
MTP2N18
MTP2N20

VN0360N5
VN1210N5
VN1210N5
VN1220N5
VN1220N5

PM512M
PM512P
PM601L
PM602L
PM603L

VN1206N1
VN1206N5
VN0106N3
TN0606N3
VN0206N3

RFP15N05
RFP15N06
RFP1N35
RFP1N40
RFP2N08

VN1206N5
VN1206N5
VN0635N5
VN0640N5
TN0610N5

IVN6660
IVN6661
MTM10N05
MTM10N06
MTM10N08

VN0106N2
VN0109N2
VN1206N1
VN1206N1
VN1210N1

MTP2N35
MTP2N40
MTP2N45
MTP2N50
MTP2P45

VN0335N5
VN0340N5
VN0345N5
VN0350N5
VN0345N5

PM604P
PM605P
PM606L
PM608M
PM608P

VN1106N5
VN1206N5
TN0606N3
VN1206N1
VN1206N5

RFP2N10
RFP2N12
RFP2N15
RFP2N18
RFP2N20

VN1110N5
VN1216N5
VN1216N5
VN1120N5
VN1120N5

MTM10N10
MTM12N05
MTM12N06
MTM12N08
MTM12N10

VN1210N1
VN1206N1
VN1206N1
VN1210N1
VN1210N1

MTP2P50
MTP3N12
MTP3N15
MTP3N35
MTP3N40

VN0350N5
VN1216N5
VN1216N5
VN0335N1
VN0340N5

PM609P
PM609R
PM610P
PM612M
PM612P

VN1206N5
VN1206N5
VN1206N5
VN1206N1
VN1206N5

RFP2P08
RFP2P10
RFP3N45
RFP3N50
RFP4N05

TP0610N5
TP0610N5
VN0345N5
VN0350N5
VN1i06N5

MTMi5N05
MTMi5N06
MTM20N08
MTM20N10
MTM2N45

VN1206N1
VN1206N1
VNi2i0N1
VNi210N1
VN0345Ni

MTP4N08
MTP4Ni0
MTP5N05
MTP5N06
MTP5Ni8

VNii10N5
VNi1i0N5
VNi106N5
VN1206N5
VN1220N5

PM614M
PM6i4P
PM80iL
PM802L
PM805P

VNi206N1
VNi206N5
VNOi09N3
TN06i0N3
VNi2i0N5

RFP4N06
RFP4N35
RFP4N40
RFP6P08
RFP6P10

VNii06N5
VN0335N5
VN0340N5
VPi2i0N5
VPi2i0N5

MTM2N50
MTM2P45
MTM2P50
MTM3N35
MTM3N40

VN0350N1
VP0345Ni
VP0350N1
VN0335N1
VN0340Ni

MTP5N20
MTP7Ni2
MTP7Ni5
MTP7N18
MTP7N20

VN1220N1
VNi2i6N5
VN12i6N5
VNi220N5
VNi220N5

PM808M
PM808P
PM814M
PM814P
RFL iN08

VN12i0N1
VN12i0N5
VN12i0Ni
VNi210N5
TN06i0N2

RFP8N18
RFP8N20
RFP8P08
RFP8P10
SD1i00HD

VN1220N5
VN1220N5
VPi210N5
VP1210N5
VN0545N2

6-10

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

S0110180
S01101HO
S01102BO
S01102BO
S01102HO

VN0640N3
VN0640N2
VN0635N3
VN0635N3
VN0635N2

SGSP311
SGSP312
SGSP317
SGSP318
SGSP319

VN1210N5
VN1210N5
VN1220N5
VN0355N5
VN0350N5

UFN423
UFN432
UFN433
UFN441
UFN510

VN0345N1
VN0350N1
VN0345N1
VN1106N1
VN1210N5

UFNF122
UFNF123
UFNF130
UFNF131
UFNF132

VN1210N2
VN1206N2
VN1210N2
VN1206N2
VN1210N2

S01104BO
S0110400
S01104HO
S01105BO
S0110500

VN0210N3
VN0109N9
VN0210N2
VN0210N3
VN0109N9

SGSP330
SGSP331
SGSP351
SGSP352
SGSP354

VN0345N5
VN0340N5
VN1210N5
VN1210N5
VN0345N5

UFN511
UFN512
UFN513
UFN520
UFN521

VN1206N5
VN1110N5
VN1106N5
VN1210N5
VN1206N5

UFNF133
UFNF210
UFNF211
UFNF212
UFNF213

VN1206N2
VN1220N2
VN1216N2
VN1110N2
VN1216N2

S01105HO
S01106AO
S01106AO
S0110600
S01107BO

VN0210N2
VN0106N3
VN0106N3
VN0106N9
VN0210N3

SGSP355
SGSP367
SGSP511
SGSP512
SGSP517

VN0340N5
VN1220N5
VN1210N1
VN1210N1
VN1220N1

UFN522
UFN523
UFN530
UFN531
UFN532

VN1210N5
VN1206N5
VN1210N5
VN1206N5
VN1210N5

UFNF220
UFNF221
UFNF222
UFNF223
UFNF232

VN1220N2
VN1216N2
VN1220N2
VN1216N2
VN1220N2

S01107BO
S0110700
S01107HO
S01107N
S01112BO

VN0210N3
VN0109N9
VN0210N2
VN0210N6
VN0220N3

SGSP519
SGSP530
SGSP531
SGSP579
SN0120NB

VN0350N1
VN0345N1
VN0340N1
VN1106N1
AN0120NB

UFN533
UFN610
UFN611
UFN612
UFN613

VN1206N5
VN1220N5
VN1216N5
VN1110N5
VN1216N5

UFNF233
UFNF310
UFNF311
UFN0312
UFNF313

VN1216N2
VN0340N2
VN0335N2
VN0340N2
VN0335N2

S01112BO
S01112HO
S01113BO
S01113BO
S01113HO

VN0220N3
VN0220N2
VN0120N3
VN0120N3
VN0120N2

SN0130NB
SN0140NB
TN0106N3
TN0110N3
TZ402BO

AN0130NB
AN0140NB
VN0106N3
VN0210N3
VN1304N3

UFN620
UFN621
UFN622
UFN623
UFN632

VN1220N5
VN1216N5
VN1220N5
VN1216N5
VN1220N5

UFNF320
UFNF321
UFNF322
UFNF323
UFNF332

VN0340N2
VN0335N2
VN0340N2
VN0335N2
VN0340N2

S01114BO
S0111400
S01114HO
S01115BO
S0111500

VN0109N3
VN0109N9
VN0109N2
VN0109N3
VN0109N9

TZ403BO
TZ404BO
UFN120
UFN121
UFN122

VN1304N3
VN1304N3
VN1210N1
VN1206N1
VN1210N1

UFN633
UFN710
UFN711
UFN712
UFN713

VN1216N5
VN0340N5
VN0335N5
VN0340N5
VN0335N5

UFNF333
UFNF420
UFNF421
UFNF422
UFNF423

VN0335N2
VN0350N2
VN0345N2
VN0350N2
VN0345N2

S01115HO
S01117BO
S0111700
S01117HO
S01117N

VN0109N2
VN0206N3
VN0106N9
VN0206N2
VN0206N6

UFN123
UFN130
UFN131
UFN132
UFN133

VN1206N1
VN1210N1
VN1206N1
VN1210N1
VN1206N1

UFN720
UFN721
UFN722
UFN723
UFN732

VN0340N5
VN0335N5
VN0340N5
VN0335N5
VN0340N5

UFNF432
UFNF433
VN01000A
VN010000
VN0104N3

VN0350N2
VN0345N2
VN1210N1
VN1210N5
VN0104N3

S01122BO
S01122BO
S01124BO
S01124BO
S0112780

VN0120N3
VN1320N3
VN0106N3
VN0106N3
VN0106N3

UFN220
UFN221
UFN222
UFN223
UFN232

VN1220N1
VN1216N1
VN1220N1
VN1216N1
VN1220N1

UFN733
UFN820
UFN821
UFN822
UFN823

VN0335N5
VN0350N5
VN0345N5
VN0350N5
VN0345N5

VN0106N3
VN0109N3
VN0300B
VN03000
VN0300L

VN0106N3
VN0109N3
VN0300B
VN03000
VN0300L

S01137BO
S01202BO
S01202BO
S01,iiOOBO
S01501BO

VN0206N3
VN1320N3
VN1320N3
VN0660N3
VN0655N3

UFN233
UFN320
UFN321
UFN322
UFN323

VN1216N1
VN0340N1
VN0335N1
VN0340N1
VN0335N1

UFN832
UFN833
UFNA11
UFNA12
UFNF110

VN0350N5
VN0345N5
TN0606N3
TN0610N3
VN1210N2

VN0300M
VN0400A
VN0401A
VN04010
VN0601A

VN0300L
VN1204N1
VN1204N1
VN1204N5
VN1206N1

S05101N
SGSP111
SGSP112
SGSP151
SGSP152

VN1304N6
VN1210N2
VN1210N2
VN1210N2
VN1210N2

UFN332
UFN333
UFN420
UFN421
UFN422

VN0340N1
VN0335N1
VN0350N1
VN0345N1
VN0350N1

UFNF111
UFNF112
UFNF113
UFNF120
UFNF121

VN1206N2
VN1110N2
VN1106N2
VN1210N2
VN1206N2

VN06010
VN060M
VN0610LL
VN0800A
VN08000

VN1206N5
VN0606L
VN0610LL
VN1210N1
VN1210N5

6-11

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

VN0801A
VN0801D
VN0808M
VN1001A
VN10KE

VN1210N1
VN1210N5
VN0808L
VN1210N1
VN0106N9

VN10KM
VN10KMA
VN10KN3
VN10LE
VN10LM

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

VN46AD
VN5002A
VN5002D
VN6035L
VN64GA

VN0104N5
VN0350N1
VN0350N5
VN6035L
VN1206N1

ZVN0104B
ZVN0104L
ZVN0106A
ZVN0106B
ZVN0106L

VN0104N2
VN0104N5
VN0106N3
VN0106N2
VN0106N5

ZVN021OM
ZVN0214B
ZVN0214L
ZVN0214M
ZVN0216B

VN1110N1
VN0216N2
VN1216N5
VN1116N1
VN0216N2

VN10KN3
VN10KN3
VN10KN3
VN0106N9
VN10KN3

VN66AD
VN66AK
VN67AA
VN67AB
VN67ABA

VN0106N5
VN0106N2
VN0106N5
VN0106N2
VN0106N2

ZVN0108A
ZVN0108B
ZVN0108L
ZVN0109A
ZVN0109A

VN0109N3
VN0109N2
VN0109N5
VN0109N3
VN0109N3

ZVN0216L
ZVN0216M
ZVN0220B
ZVN0220L
ZVN02A2B

VN0216N5
VN0216N1
VN0220N2
VN0220N5
TN0602N2

VN10LM
VN10LP
VN1206B
VN1206D
VN1206L

VN10KN3
VN1306N3
VN1206B
VN1206D
VN1206L

VN67AD
VN67AK
VN88AD
VN89ABA
VN89AD

VN0106N5
VN0106N2
VN0109N5
VN0109N2
VN0109N5

ZVN0109B
ZVN0109L
ZVN0110A
ZVN0110B
ZVN0110L

VN0109N2
VN0109N5
VN1310N3
VN1310N2
VN0210N5

ZVN02A2L
ZVN02A2M
ZVN02A3B
ZVN02A3L
ZVN02A3M

VN0300D
VN1106N1
TN0604N2
VN0300D
VN1106N1

VN1206M
VN1210L
VN1210M
VN1216B

VN1206L
VN1210L
VN1210L
VN1216N2

VN90AA
VN90AB
VN90ABA
VN98AK
VN99AB

VN1110N1
VN0109N2
VN0109N2
VN0109N2
VN0109N2

ZVN0114A
ZVN0114B
ZVN0114L
ZVN0116A
ZVN0116B

VN0216N3
VN0216N2
VN0216N5
VN0116N3
VN0116N2

ZVN0330B
ZVN0330L
ZVN0330M
ZVN0335B
ZVN0335L

VN0335N2
VN0335N5
VN0335N1
VN0335N2
VN0335N5

VN1706B
VN1706D
VN1706L
VN1706M
VN1710L
VN1710M

VN1706B
VN1706D
VN1706L
VN1706L
VN1710L
VN1710L

VN99AK
VP0104N3
VP0106N3
VP0109N3
VP0300B

VN0109N2
VP0104N3
VP0106N3
VP0109N3
VP0300B

ZVN0116L
ZVN0117TA
ZVN0120A
ZVN0120A
ZVN0120B

VN0115N5
VN0120N3
VN0120N3
VN0120N3
VN0120N2

ZVN0335M
ZVN0340B
ZVN0340L
ZVN0340M
ZVN0345B

VN0335N1
VN0340N2
VN0340N5
VN0340N1
VN0345N2

VN2010L
VN2222KM
VN2222L
VN2222LL
VN2222LM

VN2010L
VN1306N3
VN2222LL
VN2222LL
VN1306N3

VP0300L
VP0300M
VP0540L
VP0808B
VP0808L

VP0300L
VP0300L
VP0640N5
VP080B
VP0808L

ZVN0120B
ZVN0120L
ZVN0120L
ZVN0124A
ZVN0124B

VN0120N2
VN0120N5
VN0120N5
TN0524N3
TN0524N2

ZVN0345L
ZVN0345M
ZVN0350L
ZVN0350M
ZVN0355B

VN0345N5
VN0345N1
VN0350N5
VN0350N1
VN0355N2

VN2222LM
VN2406B
VN2406D
VN2406L
VN2406M

VN1306N3
VN2406B
VN2406D
VN2406L
VN2406L

VP0808M
VP1008B
VP1008M
VQ1000J
VQ1000P

VP0808L
TP0610N2
TP0610N3
VQ1000N6
VQ1000N7

ZVN0124L
ZVN01A2A
ZVN01A2B
ZVN01A2L
ZVN01A3B

TN0624N5
TN0102N3
TN0602N2
VN0300D
TN0604N2

ZVN0355L
ZVN0355M
ZVN0360B
ZVN0360L
ZVN0360M

VN0355N5
VN0355N1
VN0360N2
VN0360N5
VN0360N1

VN2410L
VN2410M
VN30ABA
VN3501A
VN3501D

VN2410L
VN2410L
VN0104N2
VN0335N1
VN0335N5

VQ1001J
VQ1001P
VQ1004J
VQ1004P
VQ2001J

TN0606N6
VQ1001P
VQ1004J
VQ1004P
TP0604N6

ZVN01A3L
ZVN0204B
ZVN0204L
ZVN0204M
ZVN0206B

VN0204N5
TN0104N2
VN0204N5
VN120N1
VN0206N2

ZVN0450M
ZVN0530A
ZVN0530B
ZVN0535A
ZVN0535A

VN0350N1
VN0535N3
VN0535N2
VN0535N3
VN0635N3

VN3515L
VN35AA
VN35AB
VN35AK
VN4001A

VN3515L
VN1106N1
VN0204N2
VN0204N2
VN0340N1

VQ2001P
VQ2004J
VQ2004P
VQ2006J
VQ2006P

TP0604N6
TP0606N6
TP0606N7
TP0606N6
TP0606N7

ZVN0206L
ZVN0206M
ZVN0208B
ZVN0208L
ZVN0208M

VN0206N5
VN1106N1
VN0210N2
VN0210N5
VN1110N1

ZVN0535B
ZVN0535L
ZVN0540A
ZVN0540B
ZVN0540L

VN0635N2
VN0635N5
VN0540N3
VN0540N2
VN0640N5

VN4001D
VN4012L
VN40AD
VN4502A
VN4502D

VN0340N5
VN4012L
VN0104N5
VN0345N1
VN0345N5

VQ3001J
VQ3001P
VQ7254J
VQ7254P
ZVN0104A

VQ3001N6
VQ3001N7
VQ7254N6
V07254N7
VN0104N3

ZVN0209B
ZVN0209L
ZVN0209M
ZVN0210B
ZVN0210L

TN0610N2
TN0610N5
VN1110N1
VN0210N2
VN0210N5

ZVN0545A
ZVN0545B
ZVN0545L
ZVN1104B
ZVN1104L

VN0545N3
VN0545N2
VN0645N5
TN0604N2
VN1106N5

6-12

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

Industry
Part
Number

Supertex
Part
Number

ZVN1104M
ZVN1106B
ZVN1106L
ZVN1106M
ZVN1108B

VN1106N1
VN1106N2
VN1106N5
VN1106N1
VN1110N2

ZVN1206M
ZVN1208B
ZVN1208L
ZVN1208M
ZVN1209B

VN1206N1
VN1210N2
VN1210N5
VN1210N1
VN1210N2

ZVN1408B
ZVN1409A
ZVN1409A
ZVN1409B
ZVN1410A

VN1310N2
VN1310N3
VN1310N3
VN1310N2
VN1310N3

ZVP0120L
ZVP0535A
ZVP0535B
ZVP0535L
ZVP0540A

VP0120N5
VP0535N3
VP0535N2
VP0635N5
VP0540N3

ZVN1108L
ZVNll08M
ZVNll09B
ZVN1109L
ZVN1109M

VN1110N5
VNlll0Nl
VNlll0N2
VNlll0N5
VN1110Nl

ZVN1209L
ZVN1209M
ZVN1210B
ZVN1210L
ZVN1210M

VN1210N5
VN1210Nl
VNlll0N2
VNll10N5
VN1110N1

ZVN1410B
ZVN1414A
ZVN1414B
ZVN1416A
ZVN1416B

VN1310N2
VN1316N3
VN1316N2
VN1316N3
VN1316N2

ZVP0540B
ZVP0545A
ZVP0545B
ZVP0545L
ZVP1320A

VP0540N2
VP0545N3
VP0545N2
VP0645N5
VP1320N3

ZVN1110B
ZVN1110L
ZVNlll0M
ZVNl114B
ZVN1114L

VN0210N2
VN0210N5
VN1110Nl
VN1216N2
VN1216N5

ZVN1214B
ZVN1214B
ZVN1214L
ZVN1214M
ZVN1216L

VN1216N5
VN1216N2
VN1216N5
VN1216N1
VN1216N5

ZVN1420A
ZVN1420B
ZVN2106A
ZVN2106B
ZVN2106L

VN0120N3
VN0120N2
VN0206N3
VN0206N2
VN0206N5

ZVP1320B
ZVP2106A
ZVP2106B
ZVP2106L
ZVP2110A

VP1320N2
TP0606N3
TP0606N2
TP0606N5
VP0109N3

ZVNll14M
ZVNl116B
ZVN1116L
ZVN1116M
ZVN1120B

VN1216N1
VNll16N2
VN0216N5
VN1116N1
VNl120N2

ZVN1216M
ZVN1220B
ZVN1220L
ZVN1220M
ZVN12A2B

VN1216N1
VN1220N2
VN1220N5
VN1220N1
VN1204N2

ZVN2110A
ZVN2110B
ZVN2110L
ZVN2120A
ZVN2120B

VN0210N3
VN0210N2
VN0210N5
VN0120N3
VN0120N2

ZVP2110B
ZVP2110L
ZVP2120A
ZVP2120B
ZVP2120L

VP0109N2
TP0610N5
VP0120N3
VP0120N2
VP0120N5

ZVN1120L
ZVN1120M
ZVN1130B
ZVNl130L
ZVN1130M

VN1120N5
VNl120Nl
VN0335N2
VN0335N5
VN0335Nl

ZVN12A2M
ZVN12A3B
ZVN12A3L
ZVN12A3M
ZVN1304A

VN1204N1
VN1204N2
VN1204N5
VN1204Nl
VN1304N3

ZVN2120L
ZVN2206B
ZVN22061.
ZVN2210B
ZVN2210L

VN0120N5
VN1206N2
VN1206N5
VNll10N2
VN1110N5

ZVP2206B
ZVP2206L
ZVP2210B
ZVP2210L
ZVP2220B

VP1206N2
VP1206N5
VP1110N2
VP1110N5
TP0620N2

ZVN1135B
ZVNl135L
ZVN1135M
ZVN1140B
ZVNl140L

VN0335N2
VN0335N5
VN0335Nl
VN0340N2
VN0340N5

ZVN1304B
ZVN1306A
ZVN1306B
ZVN1308A
ZVN1308B

VN1304N2
VN1306N3
VN1306N2
VN1310N3
VN1310N2

ZVN2220B
ZVN2220L
ZVN2224B
ZVN2224L
ZVN2535A

VNl120N2
VNl120N5
TN0624N2
TN0624N5
VN0535N3

ZVP2220L
ZVP3306A
ZVP3306B
ZVP3310A
ZVP3310B

TP0620N5
VP0106N3
VP0106N2
VP1310N3
VP1310N2

ZVNl140M
ZVN1145B
ZVN1145L
ZVNl145M
ZVN11A2B

VN0340N1
VN0345N2
VN0345N5
VN0345N1
VN1204N2

ZVN1309A
ZVN1309B
ZVN1310A
ZVN1310B
ZVN1314A

VN1310N3
VN1310N2
VN1310N3
VN1310N2
VN0116N2

ZVN2535B
ZVN2535L
ZVN3210L
ZVN3220L
ZVN3306A

VN0535N2
VN0535N5
VN1210N5
VN1220N5
VN0106N3

ZVN11A2L
ZVN11A2M
ZVN11A3B
ZVN11A3L
ZVNllA3M

VN1204N5
VN1204N1
VN1204N2
VN1204N5
VN1204N1

ZVN1314B
ZVN1316A
ZVN1316B
ZVN1320A
ZVN1320B

VNOl16N2
VN1316N3
VN1316N2
VN1320N3
VN1320N2

ZVN3306B
ZVN3310A
ZVN3310B
ZVN3320A
ZVN3320B

VN0106N2
VN1310N3
VN1310N2
VN1320N3
VN1320N3

ZVN1204B
ZVN1204L
ZVN1204M
ZVN1206B
ZVN1206L

VN1204N2
VN1204N5
VN1204N1
VN1206N2
VN1206N5

ZVN1404A
ZVN1404B
ZVN1406A
ZVN1406B
ZVN1408A

VN1304N3
VN1304N2
VN1306N3
VN1306N2
VN1310N3

ZVN4206A
ZVNL120A
ZVNL535A
ZVP0120A
ZVP0120B

TN0606N3
VN0120N3
VN0535N3
VP0120N3
VP0120N2

6-13

Alphanumeric Index and Ordering Information
Company Profile
Application Notes
Static Handling Procedures and Quality Assurance
Process Flow
DMOS Product Family

N- and P- Channel Low Threshold MOSFETs
DMOS Discretes N-Channel
DMOS Discretes P-Channel

.t
-_:
.'•
.-•
..

CMOS Consumer/Industrial Products

•
•

Lead Bend Options and Surface Mount Packages

WI

DMOS Arrays and Special Functions
HVCMOS High Voltage ICs

•

.I

Package Outlines
Representatives/Distributors

~:

TN01A

(1) !iupertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVDSS 1

RDS(ON)

IDlON)

VGS(lh)

BV DClS

(max)

(min)

(max)

TQ-39

Order Number I Package
TQ-92

DICE

SOV

30

2A

l.SV

TN010SN2

TN010SN3

TN010SND

100V

30

2A

1.SV

TN0110N2

TN0110N3

TN0110ND

Advanced DMOS Technology

Features
0

Low threshold

0

High input impedance

0

Low input capacitance

0

Fast switching speeds

0

Low on resistance

0

Freedom from secondary breakdown

0

Low input and output leakage

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.
Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications
0

Solid state relays

0

Battery operated systems

0

Photo voltaic drive

0

Analog switch

0

General purpose line driver

Package Options

Absolute Maximum Ratings

T0-39

(Notes 1 and 2)

i

TO-92

Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature

Note 1: See Package Outline section for discrete pinouts.
Note 2: See Array section for quad pinouts.

Soldering Temperature"
"Distance of 1.6 mm from case for 10 seconds.

7-1

•

TN01A

Thermal Characteristics
Package

ID (continuous)'

TO-92

.

TO-39

ID (pulsed)"

, Power;Dissipation

°je

°jO

@Tc::',25°C

°CIY!:

°CIW,

lOR

IDR...•

'.

0.5A

·2.0A

1.0W

170

126

' 1.0A

4.GA

0.8A

2.5A

3.5W

125

35

2.5A

5.0A

10 (continuous) IS limited by max rated Tr

Electrical Characteristics

(@ 25°C unl~ss otherwise specified)

Parameter

Symbol
BVoss

Min

I TN0110
I TN0106

Drain-to-Source
Breakdown Voltage

VGSlth

Gate Threshold Voltage

AV GSlth)

Change in VGSlth) with Temperature

IGSS

Gate Body Leakage

loss

Zero Gate Voltage Drain Current

Typ

Max

60
0.6
-3.2

.

Unit

100

(Notes 1 and 2)
Conditions

V

10 = 1mA, VGS = 0

1.6

V

-5.0

mV/oC

100

nA

VGS = Vos ' 10 = 0.5mA
VGS = Vos ' 10 = 1.0mA
VGS = ±20V, Vos = 0

I1A

VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Rating

10

---soc

TA = 125°C
ON-State Drain Current

101ON)

0.75

1.5

2.0

3.5

Static Drain-to-Source
ON-State Resistance

2.5

4.5

2.0

3.0

AROSION)
GFS

Change in ROSION) with Temperature

0.6

1.1

C,SS

Input Capacitance

50

60

Coss
CRSS

Common Source Output Capacitance

25

35

Reverse Transfer CapaCitance

4

8

tdlPNI
tr
tdOFF

Turn-ON Delay Time

2

5

Rise Time

3

5

Turn-OFF Delay Time

6

7

\

Fall Time

3

5

Vso

Diode Forward Voltage Drop

1

1.5

tIT

Reyerse Recovery Time

ROSION)

Forward Transconductance

°IO/°C

VGS = 10V, 10= 500mA
10 = 0.5A, VGS = 10V

mU

VDS = 25V, ID = 500mA

pF

VGS = 0, Vos = 25V
f = 1 MHz

ns

Voo =25V
ID = 1.0A
Rs= 50Q

400

225

400

Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated, (Pulse test:
Note 2:

Q

VGS = 5V, Vos = 25V
VGS = 10V, Vos= 25V
VGS = 5V, 10= 250mA

A

300~s

V

Iso = 0.5A, VGS = 0
Iso = 0.5A, VGS = 0

ns

pulse, 2% duty cycle.)

All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

Input

1----puLSE---l

i

10%
t(ON)

t(OFF)

I

GENERATOR

1
V-~~~-r;-~

1
1

1

Output _ _ _ _----I

1

10%

1

i

7
1
'- __________1

7-2

I-<~__<:)SCOPE

D.U.T.

TN01A

Typical Performance Curves

Saturation Characteristics

Output Characteristics
5

5

4

4
VGS = 10V

iii

w

a:

~

3

II'.
r/

w

a.

::;

~

9

~
...~~

~v

.tI'.

2

6V.
1
5V
I
4V

&

r
If

o

3

7V

V

2

VGS = 10V

9V
I

20

30

o

50

40

6V

~ i"""

3V
2V.
10

-=18V

~~

1

o

r-

./!

4V

~

o

1

~V
4

2

6

8

10

Vos (VOLTS)

vos (VOLTS)

Transconductance Vs. Drain Current

Power Dissipation Vs. Case Temperature

0.5

10

I

TA = -55°C'
1

25°C

0.4
iii

z

w
::;
w

§
In

8

J.150·C
J

0.3

6

0.2

4

0.1

2

LL

1:W;;iil

(!1

o

0
.6

1.2

1.8

2.4

3.0

o

25

50

Maximum Rated Safe Operating Area

cw

.g

:J

~IQ:~D~

a:

w
::;
a.

~

9

«

:;

~

.1

(1)
(2)

300~S
10~S

pulse @ 2% D.C.
pulse@2% D.C.

II

I

III

I

.6

~

~

'"

in

.4

150

'/

oJ

«

.2

~

a:

"

w

t
1000

o

./
.001

VOS (VOLTS)

7-3

J

J

/
J

~

a:

:;

,

/

w

100

125

I..;'

()

Z

10

100

TO--39
TC= 2S"C
PD=3.5W

o

~
w

I'.01

.8

a:

,

TO 39 DC

1.0

N

fWT~ leifr~ (2)
iii
w

r-....

Thermal Response Characteristics

10

IIlii

75

r--....

TC (oC)

10 (AMPERES)

E+::0--39 PULSED

.........

trO-9:

YDS,=f V
0

...........

1."...000

I'
",

TO-92
TA=25°C

l~p=l'fl.

.01
.1
1
tp (MILLISECONDS)

10

TN01A

Typical Performance Curves

ON - Resistance Vs. Drain Current

BVoss Variation with Temperature

1.3
1.2
w

N

1.1

--

a:
0

~

en

~~s ]5V

4

C
:J
«
:;;

,,

5

1.0

~

V

~

>
III

...- v

-

J
V S 10V

r

1

I)

3
~

2

V

V

.......

.9

o

.8

o

-60

50

o

150

100

2

IVO~ -

TA- _5~oy

iii
w

a:

17

1.2
w
N
:J

«
::;;

1/ VIA

0

~

)~ V

.6
0

o

...

~
.!::

"--

"- /
V r":

!'....

""- "-

",

.6

6

8

10

50
TJ (oC)

Gate Drive Dynamic Characteristics

Capacitance Vs. Orain-to-Source Voltage

80

10

60

8

/
1VOS=10V I
1--1--1--+---1- 5 5pF

I

6

o

J

20

2

o

o

o
10

20

30

40

v.5

VDS (VOLTS)

J

/

1/ /
J40V

VI/

4

U

/

/

j

40

~
U

150

100

J

v

50pF
.65

.8

.95

1.1

OG (NANOCOULOMBS)

7-4

1.25

<
:E
a:

0

z
Z
9en
0

0.4

o

-50

w

0.6 a:

,

VGS (VOLTS)

~
«
a:
«
LL

0.8

.4

4

0

N

::::;

1.0

\!)

>

1.2

./ /10=0.5A

en

1/
1/

2

~

.8

1.4

/

I".V(th)

1.0

a:

J V V,50° C

1.2

5

/

C

V2~~C/

1.8

w
0..
:;;

5
9

1.4

J

25V

2.4

4

V(th) and ROS Variation with Temperature

Transfer Characteristics

3.0

3

ID (AMPERES)

TJ tC)

TN01L

"§upertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
(max)

(min)

TO·39

Order Number I Package
TO·92

DICE

20V

1.8g

2.0A

TN0102N2

TN0102N3

TN0102ND

40V

1.8g

2.0A

TN0104N2

TN0104N3

TN0104ND

BVoss I
BVOGS

ROS(ON)

IO(ON)

Features

Advanced DMOS Technology

0

Low threshold

0

High input impedance

0

Low input capacitance

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

0

Fast switching speeds

0

Low on resistance

0

Freedom from secondary breakdown

0

Low input and output leakage

0

Complementary N- and P-channel devices

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications
0

Logic level interface

0

Solid state relays

0

Battery operated systems

0

Photo voltaic drive

0

Analog switch

0

General purpose line driver

Package Options

(Note 1)

i i

Absolute Maximum Ratings

TO-39

TO-92

Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Note 1: See Package Outline section for discrete pinouts.

Soldering Temperature'
*Oistance of 1.6 mm from case for 10 seconds.

7-5

..

:.

TN01L

Thermal Characteristics
Package

ID

iD(pul~)·

(continuous)·

';".'

TO-39

,·l.25A

TO-92

O.aOA

•: j

'<.<
Power Dissipation
.
@T=25°C
. . c.

9jC

911.

°CIW

·C/W

IDR

IDRM

•

2.9OA

3,5W

,125

35

1.25A

2.90A

2.40A

1.0W

170

125

O.aOA

2.40A

• 10 (continuous) is limited by max rated Tj"

Electrical Characteristics
Symbol
BVoss

(@ 25°C unless otherwise specified)

Parameter

Min

I TN0104
I TN0102

Drain-to-Source
Breakdown Voltage

VGSCth )

Gate Threshold Voltage

IN GS(th)
IGSS

Change in VGS(th) with Temperature
Gate Body Leakage

loss

Zero Gate Voltage Drain Current

Typ

Max

Unit

40

V

20
0.6

(Notes 1 and 2)

Conditions
VGS = 0, 10 = 1.0mA

-3.8

1.6
-5.0

V
mV/oC

0.1

100

nA

VGS = Vos' 10 = 1.0mA
VGS = ±20V, Vos = 0

1

~A

Vas = 0, Vos = Max Rating

100

~A

VGS = Vos' 10 = 500~A

Vas

=0, Vos = 0.8 Max Rating

TA = 125°C
10(ON)

ROS(ON)

aROS(ON)
GFS

ON-State Drain Current

0.5
0.5

0.8

2.0

2.8

VGS = 3V, Vos = 25V
A

VGS =10V, Vos = 25V

5.0

Static Drain-to-Source
ON-State Resistance

Change in ROS(ON) with Temperature
Forward Transconductance

0.34

VGS = 3V, 10 = 50mA

2.3

2.5

1.5

1.8

0.7

1.0

Q

Input Capacitance

45

60

Common Source Output Capacitance

20

25

CRSS

Reverse Transfer Capacitance

2

5

td(ON)
tr

Turn-ON Delay Time

3

5

Rise Time

7

a

td(OFF)

Turn-OFF Delay Time

6

9

~

Fall Time

5

8

Vso

Diode Forward Voltage Drop

1.2

1.8

trr

Reverse Recovery Time

300
300~s

VGS = 5V, 10 = 250mA
Vas = 10V, 10 = 1A

%IOC

0.45

CISS
Coss

Note 1: All D.C. parameter. 100% tested at 25'C unle •• otherwise stated. (Pulse test:
Note 2: All A.C. parameters sample tested.

Vas = 5V, Vos = 25V

10 = 1A, VGS = 10V

U

Vos = 25V, 10 = 0.5A

pF

VGs= 0, Vos= 25V
f= 1 MHz

ns

Voo = 25V, 10 = 1A
Rs = 50Q

V

Iso= 2.5A, Vas = 0

ns

Iso=1A,Vas=0

pulse, 2% duty cycle.)

Switching Waveforms and Test Circuit

r-----..,.,

90%

I----PULSE---i
:
td(ON)

tr

Output - - - - - - , J
10%

GENERATOR
I
~-+~T-~-r~

I
I
I
I
I
I
I.,.

10%

L__________II

7-6

1--4"0--<) SCOPE
O.U.T.

TN01L

Typical Performance Curves
Saturation Characteristics

Output Characteristics

~

3.75

3.75

3.0

3.0

E

~

r

7V

J

sv

~

SV

..£l

1.5

l'

20

'0

30

40

en
c:
Il)

o

SO

I

4

S

'0

I
TA = -55°C
4

TO-39
TA

=25°C

TA

=125°C

~

3

.....

,

0.3
TO-92

0.15

2

0

3

4

-

""

" "-.....',,-

-..... ...

2S

SO

~

75

100

'2S

'SO

Tc(OC)

10 (amperes)
Maximum Rated Safe Operating Area

Thermal Response Characteristics

'0

1.0
f- TO.92

(~C)

r-r·I...,
1.0 I-

!!!
~
E

~

..£l

SV
4V
3V
2V

2

(!)

en

-

Power Dissipation vs. Case Temperature

r

!

-"'"

7V
SV

Transconductance vs. Drain Current

r

0.45

~

~

BV

Vos (volts)

I

E
~

0.75

~

~ :;.. ~

,ov

.......
"'"
".,.-

VOS (volts)

-Vos =25V
0.6

~

1.5

3V
2V

o

0.75

E

4V

r

2.25

!!!
~

BV

IT

0.75

en

9V

"-

~

E

'O~

~

2.25

(06,'

T6-92 1

~-

-"

,,

1
iii

E
0

'-

O.B

-S
UJ

()

z

ro-..

o.s

/

~

1ii
UJ

0.4

0:
..J

<
:;

I'

0:

I'

0.2

'0

100

V

/

~

0.01

o

./'

UJ

::c

I-

0.00'

7-7

TO-92
Po =1WTA = 25°C-

·1

0.01

0.'

tp (milliseconds)

Vos (volts)

J

V

C/)

0.1

/

I

10

TN01L

BVoss Variation with Temperature

On-Resistance vs. Drain Current

1.3

10

8

./

'0
Q)

/'

N

~

E
0
.s
CI)
CI)

0

I
J

Vas = SV

1.2

1.1

./
1.0

>
CD

V

0.9

","

/'

II

(j)

E

~

'"

6

J

S

z

~

0

J

/

4

a:

Vas = 10V

j

r-

2

~

~,

-

~

0.8
-50

50

100

150'

10 (amperes)

Transfer Characteristics
2.5

vos = 2SV

/f

(j)
~

.J

f-c,

f--

Q)

rt>

II v../,,'!-+
1.0

/

~

~

.,

V(th)

......

'0
Q)
.~

(ij

1.0

,.,.

E
0

.s

-f--

ECI)

~V

V

I"-....

i'..... . /

. /~

V

v

1.2
N

1.0

..........
........

0.8

~

0.8

I"-.....

r'-....

0.6

100

150

Vas (volts)
Capacitance vs. Drain-to-Source Voltage

Gate Drive Dynamic Characteristics

80 rr-----r----~--~--~-----,

10

f=1MHz

VOS = 2SV

60
(j)

~

.l!!
0

55pF

C 1SS

6

/

40

'I

u

B

4

<.)

COSS

20

)
C RSS

o
10

20

30

40

1/

0.5

L I(-'-

I

i
'I(
1/

J /
J
I(

/

IL /
0.65

0.8

0.95

Qa (nanocoulombs)

VOS (volts)

7-8

1.1

~
.s
z

~

a:

0.4

o

-50

~

0

0.4
10

6

'0
Q)

I"

0.6

4

2

1.4

1O=O.2SA

~

J~ V

0.5

.....

1.2

) / .v::'l,."v-

1.5

a.

.9

1/

~7~~Yl/

E

.!!

V(th) and Ros Variation with Temperature
1.4

'I- :¥~1/


'"

t

1.2

~

1.0

./

"
o

-50

10

8

..........

10

f = 1MHz

~

25

\

(J

=

"-

o
o

~

/

6

..........

.8

i'-....

..........

100

.4
150

/V
10VJ '/
VI VOS 40V

1/

-'

CISS

o

~

'"

~

"""" ~
20

30

/

125 pF

IV

2

COSS

,. ~

1/

1{50 pF

GRSS
10

!J

4

o
o

40

.4

.8

1.2

1.6

QG (NANOCOULOMBS)

VOS (VOLTS)

7-13

a:

z

=

50

0

Vo~

8

75

::::;
c(
:;
0

Gate Drive Dynamic Characteristics

Capacitance Vs. Drain-to-Source Voltage

(J

1.6

TJ tC)

100

E;

/

1.2

50

VGS (VOLTS)

~
«
a::
«
u.

r-......

~"
C

UJ
N

1/

~ .......... /
'/

.8
6

2.0

V

(!)

4

2

1.0

1/

d'

V DS = 25V

.8

.6

.4

lOS (AMPERES)

Transfer Characteristics
1.5

tii
UJ

= 5V

....... ."..

r-

TJ ('C)

1.2

, / V'VGS

V

8

a::

V

.90
-50

V

12

0

V

/

.96

I

tii
::;;

/V

0

~

I

16

Ci

I

2

Z

Q.
CIl
c
a:

TN06A

(t) §upertex inc.
I

N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
Order Number' Package

BVoss '
BVOGS

ROS(ON)

IO(ON)

(max)

(min)

VGS(th)
(max)

T0-39

TO·92

TO·220

Quad P·DIP

Quad C·DIP

DICE

SOV

1.S0

3.0A

1.SV

TNOSOSN2

TNOSOSN3

TNOSOSNS

TNOSOSNS

TNOSOSN7

TNOSOSND

100V

1.S0

3.0A

1.SV

TNOS10N2

TNOS10N3

TNOS10NS

-

-

TNOS10ND

Features

Advanced DMOS Technology

D Low threshold

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

D High input impedance
D Low input capacitance
D Fast switching speeds
D Low on resistance
D Freedom from secondary breakdown
D Low input and output leakage

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications

Package Options

(Notes 1 and 2)

D Logic level interface
D Solid state relays
D Battery operated systems
D Photo voltaic drive
D Analog switch
D General purpose line driver

TQ·220

;~~

Absolute Maximum Ratings
Drain-to-Source Voltage

~-

Drain-to-Gate Voltage
Gate-to-Source Voltage

14·Lead DIP

±20V

Operating and Storage Temperature

Note 1: See Package Outline section for discrete pinouts.
Note 2: See Array section for quad pinouts.

Soldering Temperature'
*Oistance of 1.6 mm from case for 10 seconds.

7-14

TN06A

Thermal Characteristics
Package

10 (continuous)"

TO-92
TO-39
TO-220
PLASTIC DIP
CERAMIC DIP

10 (pulsed)"

0.8A
1.5A
3.0A

Power Dissipation

°Je

OJ"

@Tc=25°C

°CIW

°CIW

125
20
2.7

170
125
70

4A
4A
4A

1W

28W

lOR

10RM"

0.8A
1.5A
3.0A

4.0A
4.0A
4.0A

Refer to Arrays & Special Functions Section.

• 10 (continuous) is limited by max rated Tj"

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

Min

I TN0610

Drain-to-Source
Breakdown Voltage

BVoss

I TN0606

Typ

Max

Unit

100

Conditions

V

60
0.6

1.6

(Notes 1 and 2)

Vas = 0,1 0 = lmA

VGSlthl
aVaS(th)

Gate Threshold Voltage

-4.5

V
mY/DC

Vas = Vos' 10 = lmA

Change in VaS(th) with Temperature

IGSS

Gate Body Leakage

100

nA

Vas = ±20V, Vos = 0

loss

Zero Gate Voltage Drain Current

10

!LA

1

mA

VGS = 0, Vos = Max Rating
Vas = 0, Vos = 0.8 Max Rating

Vas = Vos' 10 = 1mA

TA = 125°C (note 2)
ON-State Drain Current

10(ON)

1.2

2.0

3.0

6.0

Static Drain-to-Source
ON-State Resistance

ROS(ON)
aROS(ON)

Change in ROS(ON) with Temperature

GFS
CISS

Forward Transconductance

Vas = 10V, Vos= 25V

1.5

2.0

1.0

1.5
0.75

0.4

Vas = 5V, Vos = 25V

A

Vas =5V,l o =0.75A
VGS = 10V, 10 = 0.75A

n
%/oC
U

0.6

Input Capacitance

85

150

Coss
CRSS

Common Source Output Capacitance

50

85

Reverse Transfer Capacitance

10

35

t-O~

~

D-

I II

I

TO-220

(pulsed)

I

¥

I

'ffi

E
0

I"

I.C

"

E

~

$I
0.1

O.B

TO-220

.s

,"".9

I\\.

Q)

w

"'~"'

""

4

2

6

10

0.4

VGS (volts)
Capacitance vs. Drain-to-Source Voltage
200

"""-

"0

~

V

~

100

:§,
(.)

50

'" '"',100

-50

8

10

,

1!l

C1SS

"-"

(5
~

>'"
Cl

VI
/ /

4

Coss _

CRSS
20

30

150

, ,I

~
40

1/ /
/

/

-

~

0.5

" Vos = 40V
172 pF

,/.

95 pF
1.0

1.5

QG (nanocoulombs)

Vos (volts)

7-17

2.0

'fil

0.8

.s
zQ.

E
0

rf'"

I

Vos = 10V

~

"

1.2

0.4

Gate Drive Dynamic Characteristics

f= lMHz

~

N

",

10

~

'0
(I)

".

.".,
./

150
Ii)

"".,..

./

1.0

0.8

1.6

/

10 =2A

V(th)

0.6

l..-' ~
o

"

1.2

2.5

."

TN06C

"§upertex inc.
N·Channel Enhancement·Mode
Vertical DMOS Power FETs
Ordering Information
Order Number I Package

BVDSS I
BVDGS

RDS(ON)

ID(ON)

(max)

(min)

VGS(th)
(max)

TO·39

T0-92

200V

SO

1.0A

1.SV

TNOS20N2

TNOS20N3

TNOS20N5

TNOS20ND

240V

SO

1.0A

1.SV

TNOS24N2

TNOS24N3

TNOS24N5

TNOS24ND

Advanced DMOS Technology

Features
0

Low threshold

0

High input impedance

0

Low input capacitance

0

Fast switching speeds

0

Low on resistance

0

Freedom from secondary breakdown

0

Low input and output leakage

0

Complementary N- and P-channel devices

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.
Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications
0

Logic level interface

0

Solid state relays

0

Battery operated systems

0

Photo voltaic drive

0

Analog switch

0

General purpose line driver

DICE

T0-22O

Package Options

if
TO-39

Absolute Maximum Ratings
Drain-to-Source Voltage

~

(Notes 1 and 2)

i

TO-92

TO-220

Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Soldering Temperature*

Note t: See Package Outline section for discrete pinouts.
Note 2: See Array section for quad pinouts.

300°C

*Distance of 1.6 mm from case for 10 seconds.

7-18

TN06C

Thermal Characteristics
Package

10 (continuous)'

10 (pulsed)'

Power Dissipation

8jC

8ja

@Tc=25°C

,

lOR

10RM

°C/W

°C/W

TO-39

O.7A

2.5A

6W

20

125

0.7A

2.5A

TO-92

O.4A

2.0A

1W

125

170

O.4A

2.0A

TO-220

1.5A

2.5A

28W

4.5

70

1.5A

2.5A

* ID (continuous) is limited by max rated Tf

Electrical Characteristics

(@ 25°C unless otherwise specified)

Parameter

Symbol

Drain-to-Source
Breakdown Voltage

BVoss

Min

I
I

TN0624

240

TN0620

200

Typ

Max

Unit
V

VGSlthl

Gate Threshold Voltage

tN GSlth)

Change in VGSlth) with Temperature

0.6

-5.0

1.6

V
mV/oC

IGSS

Gate Body Leakage

100

nA

loss

Zero Gate Voltage Drain Current

10

j.lA

1

mA

(Notes 1 and 2)

Conditions
VGS = 0, 10 = 2.0mA
VGS = Vos ' 10 = 1.0mA
VGS = Vos' 10 = 1.0mA
VGS = ±20V, Vos = 0
VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Rating
TA = 125°C

101ON)

ON-State Drain Current

ROSION)

Static Drain-to-Source
ON-State Resistance

0.5

A

~

VGS = 5V, Vos = 25V
VGS = 10\1, Vos = 25V

6

8

4

6
1.4

llROSION)

Change in ROSION) with Temperature

GFS

Forward Transconductance

CISS

Input Capacitance

85

150

Coss

Common Source Output Capacitance

50

85

CASS
tdON

Reverse Transfer Capacitance

10

35

Turn-ON Delay Time

10

tr

Rise Time

10

tdIOFF)

Turn-OFF Delay Time

20

\

Fall Time

20

Vso

Diode Forward Voltage Drop

tn

Reverse Recovery Time

n

VGS = 5V, 10 = 0.25A
VGS = 10V, 10 = 0.5A

%/OC

VGS = 10V, 10 = 0.5A

mU

Vos = 25V, 10 = 0.5A

pF

VGS = 0, Vos = 25V
f= 1 MHz

300

1.8
300

Note 1:

All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300J.ls pulse, 2% duty cycle.)

Note 2:

All A.C. parameters sample tested.

Voo = 25V
ns

10 = 1.0A
Rs = 50n

V

VGS = 0, Iso = 1.0A

ns

VGS = 0, Iso = 1.0A

Switching Waveforms and Test Circuit

Inpul

10%

I---<~-OSCOPE

I(ON)

t(OFF)
D.U.T.

Id(ON)
Output

-----..,J
10%

7-19

TN06C

Typical Performance Curves
Output Characteristics

Saturation Characteristics

4.0

5

3.2

u;~

,

2.4

~

BV

~

G)

a.
E

.9

4
10V

6V

I

1.6

II':.
,...

O.B

3

~

2

a.
E

l...IIIIII

3V

v.

....

2V

o

10

20

30

VOS

40

<:
G)

0.3

~

,

0.2

(!l

0.1

0

I

I

TA = 150°C

a..'"

30

r- TO·220

I--

i'...

...... ~

"'

20

.....

""'"

TO·39
TO·92

o
1.6

O.B

2.4

3.2

o

4.0

50

25

75

"

100

~

125

150

Tc(°C)
Thermal Response Characteristics
1.0

~tJ~ul;t)

I
~

r--~O.i9 (~d~"
0.1

,""

'iJ
G)

I

TO·220

.~

(pulsed)

OJ

E
0

I\..

O.B

.s

'"
"' ,

f= TO·220 (OC)
I I NI

~

(volts)

10

II

.9

2V
10

B

40

Maximum Rated Safe Operating Area

a.
E

3V

TA = 25°C

10

1.0

4V

TA = -55°C

10 (amperes)

u;!!?
G)

~

Vos = 25V

I
o

-

Power Dissipation vs. Case Temperature

J

I

~~

10V
BV
6V

50

!J ~
/I

E
.91
!!1..

~

6

VOS

1/

u;-

4

(volts)

,

0.4

~

2

Transconductance vs. Drain Current
0.5

..... ~ ~
~ P'

50

iii

-

.9

4V

L~

u;!!?
G)

UJ

u
Z

0.6

~

"

iii
UJ

0.4

a:

...J

«

::!:

a:

I\..
0.01
10

100
VOS

"

0.2

Po =4W
Tc=25°C

UJ

::I:
I1000

0.001

0.01

0.1

tp (milliseconds)

(volts)

7-20

10

TN06C

On-Resistance vs. Drain Current

BVoss Variation with Temperature
1.1

1S

~

/
/

!

E
1.0

~

>

III

V

V

l/

-

(j)

./

'iij
~

12

./
E
.c

/

.9Z

-

0

i1i
Cl

6

rc

--

o

0.9

a

-so

100

IfI VGS = 1OV-

-VGS =5V

9

1S0

.,V /'

.......

o

".

/

V

0.8

1.6

2.4

3.2

4.0

...

10 (amperes)

Transfer Characteristics
4.0

I

I

II

Vos = 25V

I

3.2

(j)
~

TA =-55°C
2.4

a.
E

.!!

)
0.8

a

-

If)"
~

./

V

~ ~I'

""

~25J7
'C
())

1.2

.!::!

iii

E
0

/

.s

~

1.0

E

en

~

TA = 150°C

0.8

~V

"

i'..

4

r

.",

./

~

Capacitance vs. Drain-to-Source Voltage

~

\'--~
\~

~

J!!

.~

100

.e,

C)

SO

"
10

j

en

...

Coss -

30

4

/

2

f """'"I

V

V

IL,'j

..",

r-.100 pF

CRSS
20

"

/. V Vos =40V
V 1/178PF
/ /

~

~
~

0.4

1S0

/ /

~

CISS

....

a

i'..

1 II
Vos = 10V

8
(j)

"

Gate Drive Dynamic Characteristics

f= 1MHz

40

O.S

I
1.0

1.S

QG (nanocoulombs)

Vos (volts)

7-21

0.8

.s
z0

E
0
i1i

100

10

1.2

iii

r£

V GS (volts)

200

1S0

.!::!

-so

10

8

6

'C
())

~V

""
"
./

1.6

V-

10 =500mA

V (th)

0.6

", FI"'"

a

~

1.4

V

j ~~
1.6

2.0

V

I

())

.9

/

I

J TA

V(th) and Ros Variation with Temperature

2.0

2.S

TN06L

"§upertex inc.
I

N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
Order Number I Package

BVoss I
BVOGS

RDS(ON)

ID(ON)

VGS(th)

(max)

(min)

(max)

T0-39

TO-92

20V

0.750

4.0A

1.SV

TNOS02N2

TNOS02N3

-

TNOS02ND

40V

0.750

4.0A

1.SV

TNOS04N2

TNOS04N3

TNOS04WG

TNOS04ND

SOW-20'

DICE

"Same as SO·20 with 300 mil wide body.

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Notes 1 and 2)

Motor control
Convertors
Amplifiers
Switches

i

Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps
Memories, Displays, Bipolar Transistors, etc.)
TO·39

TO·92

~

Absolute Maximum Ratings
Drain-to-Source Voltage

SOW·20

Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature

Note 1:
Note 2:

Soldering Temperature"
*Oistance of 1.6 mm from case for 10 seconds.

7-22

See Package Outline section for discrete pinouts.
See Array section for quad pinouts.

TN06L

Thermal Characteristics
Package

10 (continuous)'

10 (pulsed)'

Power Dissipation

BJe

Bj •

@Tc=25°C

°CIW

°CIW

,

IDA

lOAM

TO-39

2.5A

4.6A

4W

35

125

2.5A

4.6A

TO-92

1.0A

4.6A

1W

125

170

1.0A

4.6A

SOW-20

Refer to Arrays & Special Functions Section.

* 10 (continuous) is limited by max rated Tj'

Electrical Characteristics
Symbol

Parameter
Drain-to-Source
Breakdown Voltage

BVoss

(@ 25°C unless otherwise specified)
Min

I TN0604
I TN0602

VGS(th)

Gate Threshold Voltage

tNGS(th)

Change in VGS(th) with Temperature

IGSS

Gate Body Leakage

loss

Zero Gate Voltage Crain Current

ON-State Drain Current

1010N)
ROSION)

Typ

Max

Unit

40
20
0.6
-3.8

1.5

2.1

4.0

7.0

Static Drain-to-Source
ON-State Resistance

Conditions

V

VGS= 0, 10 = 2.0mA
VGS = Vos ' 10 = 1.0mA
VGS = Vos ' 10 = 2.5mA

1.6

V

-4.5

mV;oC

100

nA

VGS = ±20V, Vos = 0

10

!lA

VGS = 0, Vos = Max Rating

1

mA

VGS = 0, Vos = 0.8 Max Rating
TA = 125°C
VGS = 5V, Vos = 25V

A

VGs= 10V, Vos=25V

0.8

1.5

0.60

0.75

0.5

0.75

LlROSION)

Change in ROSION) with Temperature

GFS

Forward Transconductance

CISS
Coss

Input Capacitance

85

150

Common Source Output Capacitance

50

85

CRSS
tdON

Reverse Transfer Capacitance

12

35

Turn-ON Delay Time

t,

Rise Time

10

td(OFF)

Turn-OFF Delay Time

25

\

Fall Time

13

Vso

Diode Forward Voltage Drop

-1.2

trr

Reverse Recovery Time

300

0.5

(Notes 1 and 2)

n

VGS = 5V, 10 = 0.75A
VGS = 10V, 10 = 1.5A

%;oC

VGs= 10V, 10=2.0A

U

Vos = 25V, 10 = 2.0A

pF

VGS = 0, Vos = 25V
f= 1 MHz

1.0

10

-1.8

Note t:

All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pu)se lest: 300~s pulse, 2% duty cycle.)

Note 2:

All A.C. parameters sample tested.

Voo = 25V
10 = 0.5A

ns

Rs = 50n
V

VGS = 0, Iso = 1.5A

ns

VGS = 0, Iso = 1A

Switching Waveforms and Test Circuit

I----PU~E---I
:

Id(ON)
OUlput

-------1
10%

:

I

GENERATOR

V-~~--~~

I
I
I
I
I
I
-"

L __________

7-23

I
I

f--~-O SCOPE

D.U.T.

TN06L

Typical Performance Curves
Output Characteristics

Saturation Characteristics

10

10

8

..-

/

9V

I ,r~

..-

,..
,..
~
~

---

10V

~

til

8V

2i

7V

~

SV

.£l

E

4

/. ~ ~ ~

5V

~

,..
./ """ ,,..
,/ /. c;...

S

~

~~~

4V

~

:::-r--- ~

10

20

30

40

4

50

Vos (volts)

8V

7V
SV
5V
4V
3V

3V

o

10V
9V

10

8

VOS (volts)

Transconductance VS. Drain Current

Power Dissipation vs. Case Temperature

2.0

5

Vos = 25V
4

til

:§.

T6.39~

'1'1..

TA --55'C_

c:
CD
E

1/

1.0

~
Cl

I

TA -25'C_

I.'r

T~ = 1k5,6-

'-

c

0..

V-

I

I-- TO-r

1/

4

2

S

8

10

0

-

25

50

Maximum Rated Safe Operating Area

"

~

-- """"-~
100

125

150

Thermal Response Characteristics
1.0

TOI.92
1

TO-39

l(pUIIS~~)

"

1
(~C)

~

1.0

'0
CD

I II
I
I
TO-39 (pulsed)

",

~

,

N

'fa

E
0
.s
LU

(,)

,I'

CD

Co

E

.£l

75

'-

Tc(°C)

10

~

I\..

t--

10 (amperes)

til

"

TO-92

(~C)

O.S

Z

<

~

t;;

iii
LU
a:

"'-

0.1

0.8

0.4

...J

<
~

a:

0.2

Tc = 25'C
Po =1W

LU

J:

I1

10

100

0.001

0.01

0.1

tp(milliseconds)

VOS (volts)

7-24

10

TN06L

BVoss Variation with Temperature

On-Resistance vs. Drain Current
2.0

1.1

.,V

'0
Q)
N

'ffi

1./i'"

E

(;

.sCIl

1.0

.JII' V

CIl
Cl

VGS = 5V

./

V

I

VGS = 10V

-

>

i-'
.I

III

0.9

o

-50

100

o

150

5.0

10.0

10 (amperes)

Transfer Characteristics

V(1h) and Ros Variation with Temperature
1.4

10

Vos = 25V

1.4
10 =2.0A

(j)
~

"'~

Q)

E

.!!!.
..fl

/

4

'0
Q)

~
?

a.

,u ~
+re

E
(;

'\b

.s
~

/ ~

1.0
~

.L. V

0.8

r' ........"

10

-50

0.8

.s
z

~

0.6

v lL

170 pF

(j)

100

:e,

C ISS

()

50

COSS

2
C RSS

~
30

150

Gate Drive Dynamic Characteristics

o

40

7-25

.J

If

/ /
,-'- I -'~/
~V
1.0

E
0
Q.

a:

100

Vos = 10V

20
Vos (volts)

'ffi

1'-..

150

10

1.0

CIl
Cl

10

0

'0
Q)
N

.......

Capacitance vs. Drain-to-Source Voltage

'0
0

L

1.2

0.4

4
6
VGs (volts)

200

~til

~ VI"""

V

V

0.6

1& ~
2

V(1h)

1'-..

E
CIl

/.. ~

0

~ t-

'ffi

~V1"'1-~u/ V
".-c-"\~

2

1.2

N

~:

V

1/ yI

V
Vos = 40V

2.0
3.0
4.0
QG (nanocoulombs)

5.0

o

TP01L

§upertex inc.
P-Channel Enhancement-Mode
Vertical DMOS Power FETs

Ordering Information
Order Number I Package

BVoss I
BV OGS

ROS(ON)

(max)

(min)

TO-39

TO-92

DICE

-20V

4.00

-0.85A

TP0102N2

TP0102N3

TP0102ND

-40V

4.00

-0.85A

TP0104N2

TP0104N3

TP0104ND

IO(ON)

Features

Advanced DMOS Technology

D Low threshold

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

D High input impedance
D Low input capacitance
D Fast switching speeds

D Low on resistance
D Freedom from secondary breakdown
D Complementary N- and P-channel devices

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications

Package Options

D Low input and output leakage

(Note 1)

D Logic level interface
D Solid state relays
D Battery operated systems
D Photo voltaic drive
D Analog switch
D General purpose line driver

i

TO·92

Absolute Maximum Ratings

TO·39

Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Note 1:

Soldering Temperature'
*Oistance of 1.6 mm from case for 10 seconds.

7-26

See Package Outline section for discrete pinouts.

TP01L

Thermal Characteristics
Package

'0 (continuous)-

TO-39

'0 (pulsed)-

Power Dissipation

lije

lila

@Tc=25°C

°CIW

°C/W

lOR

'ORM-

-0.9A

-2.6A

3.5W

35

125

-0.9A

-2.6A

TO-92
-0.5A
10 (contmuous) IS limited by max rated Tj'

-2.4A

1.0W

125

170

-0.5A

-2.4A

Electrical Characteristics
Symbol
BVoss

(@ 25°C unless otherwise specified)

Parameter
Drain-to-Source
Breakdown Voltage

Min

I TP0104
I TP0102

Typ

Max

Unit

-40
-20
-1.0

VGS = 0,1 0 = -1.0mA
VGS = Vos ' 10 = -1.0mA
VGs=Vos,lo=-1.0mA

VGSCth)

Gate Threshold Voltage

-2.4

V

Change in VGS(th) with Temperature

-5.8

-6.5

mV/oC

'GSS

Gate Body Leakage

-1.0

-100

nA

loss

Zero Gate Voltage Drain Current

-10

J.lA

-1

mA

ROS(ON)

ON-State Drain Current

0.08
-0.25

-0.40

-0.85

-1.70

A

5.5

7.5

2.5

4.0

0.55

1.0

&ROS(ON)
GFS

Change in ROS(ON) with Temperature

Crss

Input Capacitance

45

60

Coss
CRSS

Common Source Output Capacitance

22

30

Reverse Transfer Capacitance

3

8

td(ON)
t,

Turn-ON Delay Time

4

6

Rise Time

7

10

td(OFF)
t,

Turn-OFF Delay Time

3

5

Fall Time

4

6

Vso

Diode Forward Voltage Drop

-1.2

-2.0

trr

Reverse Recovery Time

300

Forward Transconductance

225

Note t:

All D.C. parameters tOO% tested at 25°C unless otherwise stated. (Pulse test:

Note 2:

All A.C. parameters sample tested.

VGS = 0, Vos = 0.8 Max Rating
TA = 125°C
VGS = -3V, Vos = -25V
VGS = -5V, Vos = -25V

%fOC

VGS = -5V, '0 = -0.1A
VGS = -10V, '0 = -0.5A
'0 = -0.5A, VGS = -10V

mV

Vos = -25V, '0 = -0.5A

pF

VGS = 0, Vos = -25V
f= 1 MHz

ns

Voo = -25V, '0 = -1A

n

300

300~s

VGs =±20V, Vos=O
VGS = 0, Vos = Max Rating

VGs =-10V, Vos --25V
VGS = -3V, 10 = -25mA

15

Static Drain-to-Source
ON-State Resistance

Conditions

V

IN GS(th)

'O(ON)

(Notes 1 and 2)

Rs = 50n
V

Iso = -0.25A, VGS = 0

ns

Iso = -1.0A, VGS = 0

pulse. 2% duty cycle.)

Switching Waveforms and Test Circuit
, . . - - - - - " ' " 90%

I-''''''''-.;C) SCOPE
D.U.T.
Output _ _ _ _---I

10%

7-27

..

TP01L

Typical Performance Curves

Saturation Characteristics

Output Characteristics
2.5

2.26
2
10V

iii
w
a:
w

Ir

1.5

V

c..

BV

0

6V

k
l¥'

1.25

.J~

5
9

7V

~ "'""

.5

c..

:;

il'

:2

5
9

,..
; ' ,..

1.75

iii
w
a:
w

9V

~~ ~

.75

Ie! .....~

5V

10"'"

It:I'-"'"

.26

4V

~

~ .-~

I'10

20

30

40

o

60

"-.-.

",,9V

.",. ~

.....- ~

-

--

-4

2

~
~

10V

.",.

BV

... 7V
6V
5V
4V

8

6

10

VOS (VOLTS)

VOS (VOLTS)

Transconductance Vs. Drain Current

Power Dissipation Vs. Case Temperature

1.0
VOS=25V

.8

4
T0-39

iii

z

w
:2
w

TA = -55·C

.6

§
III

u..

"-

3

TA =+25 C

~

"-

TA· +125'C

.4

2

(!)

TC>-92

.2

-

"-

r---

o

0.5

1.6

1.0

2.0

o

2.5

o

25

10 (AMPERES)

-.......

75

50

"

100

TC tC)

~

125

150

Thermal Response Characteristics

Maximum Rated Safe Operating Area
10

Q
w

N

I

::J
«
:;

),

)-~-I~ r.,,-t::

iii
w

a:

),

,~.,

w

~
9

1--_-+-_ T 0-39
TC=25"c

~

19~~_

w

U
Z

~

~

% ~

.1

//

a:

o

0.5

I'

iii
w

a:

@

o

/~

0.001

0.01

I
0.1

tp (SECONDS)

Vos (VOLTS)
10mS Pulse

V

::I:

I-

2V DC

7-28

j

/TC>-921----t-~./"'----IVI---:;;;c- TA = 25"c
P10 =IW_

:2
a:
w

100

If

./

«

"

L

/
/

= 3.5

III

...J

10

I----+--Po

/
/

10

TPOtL

Typical Performance Curves
BVDSS Variation with Temperature

j
1.06

w

N

:J
«
:;;

0

V)

1.02

/

~

>
Dl

1.0.

j

I

::;;

::t:

/

.e

z0

6
~

I

2

w

a:

2

lOS (amperes)'

I

V(th) and RDS Variation with Temperature
2.0

~A=:55Z

VOS=25V

1.4

~
0"

1.6

I~

C

IV~

:::;

w

N

1.0

a:

0
~

lj C/

~

en
l:l

/L /'

~

o

"
4

2

\.

1.2

'1\.

\Q

8

o

"

50
TJ

100

te)

200

10

VJ

8

150

~

0

-'
0
~

()

V)

~

>

l:l

()

/

6

II'

4

/

o

10

20

30

2

COSS
CRSS

0

I

~

tiPFI

o

40

V-

,.J. ;.....-~

50
CISS

V /

.2

.4

.6

.8

QG (NANOeOULOMBS)

VOS (VOLTS)

7-29

-40V

/

75pF /

100

;/

/

VOS=10V

f = lMHz

--1---+-_-1

0
150

Gate Drive Dynamic Characteristics

Capacitance Vs. Drain·to·Source Voltage

~----~--~----~----~

0.4

'\.
-50

10

0.8

'-I-,
,,~./

0.6
6

1.2

V "\.
/"

VGS (VOLTS)

~
«
a:
«
u..

"'~~

"\ / "

1.0

0.8

1,6

V
~p./

>

~~

0

I\.

«
::;;

// /
// /

""

:;;

0.6

'"

VGS=10V-

150

te)

w

:!
9

..,.

J

o
100

2.0

tii

-

..,... ~

4

Transfer Characteristics

-

II

J

c
a:

50
TJ

2.6

I

iii

V

o

-50

VGs=5V

1i)

II

.98

I

I
8

I

1.04

a:

~

I

j

C

,

ON-Resistance Vs. Gate-to-Source Voltage
10

1.0

..

TP02L

"

!iupertex inc.

I

P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss I
BVOGS

ROS(ON)

Order Number I Package
TO-39
TO-92

IO(ON)

(max)

(min)

-20V

2.0n

-2.0A

TP0202N2

TP0202N3

-40V

2.0n

-2.0A

TP0204N2

TP0204N3

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Low threshold
High input impedance
Low input capacitance
Fast switching speeds
Low on resistance
Freedom from secondary breakdown

Supertex VerticalDMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Low input and output leakage
Complementary N- and P-channel devices

Applications
0

Logic level interface

0

Solid state relays

0

Battery operated systems

0

Photo voltaic drive

0

Analog switch

0

General purpose line driver

Package Options

Ratings and Characteristics
TP02L not recommended for new designs. Refer to TP06L data
sheet for all ratings and characteristics.

TO-39

Note 1:

7-30

(Note 1)

i

TO-92

See Package Outline section for discrete pinouts.

o

TP06A

§upertex inc.
P-Channel Enhancement-Mode
Vertical CMOS Power FETs

Ordering Information
BVoss I ROS(ON)
BVOGS (max)

Order Number I Package

IO(ON)
(min)

VGS(th)
(max)

TO·39

TO·92

TO·220

Quad P·DIP

Quad C·DIP

DICE

-60V

3.50

-1.SA

-2.4V

TP0606N2

TP0606N3

TP0606NS

TP0606N6

TP0606N7

TP0606ND

-100V

3.S0

-1.SA

-2.4V

TP0610N2

TP0610N3

TP0610NS

-

-

TP0610ND

Features

Advanced CMOS Technology

o
o
o
o

Fast switching speeds

o
o

These enhancement-mode (normally-off) power transistors util·
ize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown

o

Low input and output leakage

Low threshold
High input impedance
Low input capacitance

Low on resistance

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications
0

Logic level interlace

0

Solid state relays

0

Battery operated systems

0

Photo voltaic drive

0

Analog switch

0

General purpose line driver

Package Options

(Notes 1 and 2)

TO-220

ID~

Absolute Maximum Ratings

~_

Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

14-Lead DIP

±20V

Operating and Storage Temperature

·Note1:
Note 2:

Soldering Temperature>
-Distance of 1.6 mm from case for 10 seconds.

7-31

See Package Outline section for discrete pinouts.
See Array section for quad pinouts.

...

I

TPOSA

Thermal Characteristics
Package

ID

(continuous)"

ID

(pulsed)"

Power Dissipation

61e
°CIW

@Tc=25°C
TO-39
TO-92
TO-220
Plastic Dip
Ceramic Dip

-1.0A
-0.5A
-2.0A

.

-4.0A
-3.5A
-4.5A

125
170
70

20
125
2.7

Symbol

-O.SA
-O.4A
-2.0A

-4.0A
-3.5A
-4.5A

(@ 25°C unless otherwise specified)

Parameter
Drain-to-Source
Breakdown Voltage

Min

I TPOS10

I TPOSOS

Typ

Max

Unit

-100

VGS(th)

Gate Threshold Voltage
Change in VGS(th) with Temperature

-5.0

V
mV/oC

IGSS

Gate Body Leakage

-100

nA

loss

Zero Gate Voltage Drain Current

-10

~A

-1

mA

ON-State D.rain Current

-2.4

-0.4

-O.S

-1.5

-2.5

Static Drain-to-Source
ON-State Resistance

5

7

3

3.5
1.7

I!..ROS(ON)

Change in ROS(ON) with Temperature

GFS
CISS

Forward Transconductance
Input Capacitance

85

150

Coss

Common Source Output Capacitance

50

85

10

35

CRSS

Reverse Transfer Capacitance
Turn-ON Delay Time

10

tr

Rise Time

15

t

/'f"-\'1':

4

V (Ih)

0.8

-

,.

1.6

SCI)
N

/

1.2

V ......... r--....

......... r--

0.8

100

150

VGS (volts)
Capacitance vs. Drain-to-Source Voltage
200

Gate Drive Dynamic Characteristics

...----r----,.----,----,

-10

I

f=1MHz

Vos = -10V
-8

)

150

/

Ii)
"0

~

e!

~0

1/

-6

0

Z-

100

:e:

/

C/l
(!)

>

0

-4

J

/

50
-2

/

/
J

/
200 pF

)

I

Vos =-40V

1.5

2.0

1/

~

r;;;F
-10

-20

-30

0.5

-40

1.0

QG (nanocoulombs)

Vos (volts)

7-34

E
0
.s
z
Q.
C/l

0.4

-50

'a

£

0.6

10

6

r--.... ~ . /

1.0

I

2.5

TP06C

"§upertex inc.
P-Channel Enhancement-Mode
Vertical CMOS Power FETs
Ordering Information
BVoss

I

Order Number I Package

ROS(ON)

IO(ON)

VGS(th)

BVOGS

(max)

(min)

(max)

TO·39

TO·92

-160V

120

-O.7SA

-2.4A

TP0616N2

TP0616N3

TP0616NS

TP0616ND

-200V

120

-O.7SA

-2.4A

TP0620N2

TP0620N3

TP0620NS

TP0620ND

TQ.220

DICE

Features

Advanced CMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Low threshold
High input impedance
Low input capacitance
Fast switching speeds
Low on resistance
Freedom from secondary breakdown

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Low input and output leakage
Complementary N- and P-channel devices

Applications
0

Logic level interface

0

Solid state relays

0

Battery operated systems

0

Photo voltaic drive

0

Analog switch

0

General purpose line driver

Package Options

lii
TO·39

Absolute Maximum Ratings
Drain-to-Source Voltage

i

TO·92

TO·220

Drain-to-Gate Voltage
Gate-to-Source Voltage

~

(Note 1)

±20V

Operating and Storage Temperature
Note 1: See Package Outline section for discrete pinouts.

Soldering Temperature'
*Oistance of 1.6 mm from case for 10 seconds.

7-3S

TP06C

Thermal Characteristics
Package

'D

10 (pulsed)'

(continuous)'

Power Dissipation
@Tc=2SoC

81c
°C/W

811
°C/W

.

IDR

IDRM

.TO-39

-1.0A

-1.5A

6W

21

125

-1.0A

-1.5A

TO-92

-O.4A

-0.8A

1W

125

170

-0.4A

-0.8A

TO-220

-1.0A

-2.5A

28W

2.7

70

-1.0A

-2.5A

• 10 (continuous) is limited by max rated Tr

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)
Min

Parameter

I TP0620
I TP0616

Drain-to-Source
Breakdown Voltage

BVoss

Typ

Max

Unit

-200

V

-160
-1.0

-2.4

VGS(thl
tNGS(th)

Gate Threshold Voltage
Change in VGS(th) with Temperature

-4.5

V
mV/oC

IGSS

Gate Body Leakage

-100

nA

loss

Zero Gate Voltage Drain Currenl

-10

f.lA

-1
-0.25

ON-Slate Drain Current

10(ON)

mA
A

--:0:75
ROS(ON)

Stalic Drain-to-Source
ON-State Resistance

12

15

9

12
1.7

aROS(ON)
GFS

Change in ROS(ON) withTemperature

CISS
Coss

Input Capacitance

85

150

Common Source Output Capacitance

50

85

CRSS
IdON

Reverse Transfer Capacilance

10

35

Turn-ON Delay Time

10

Ir

Rise Time

15
20

Forward Transconductance

Id(OFF)

Turn-OFF Delay Time

If

Fall Time

Vso

Diode Forward Voltage Drop

trr

Reverse Recovery Time

Note 2:

VGS = 0,1 0 = -2.0mA
VGS = Vos ' 10 = -1.0mA
VGs=Vos,lo=-1.0mA
VGS = ±20V, Vos = 0
VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Raling
TA = 125°C
VGS = -5V, Vos = -25V

Q
%IOC

VGs =-10V,l o =-0.2A

mU

Vos = -25V, 10 = -0.2A

pF

VGS = 0, Vos = -25V
f= 1 MHz

ns

Voo = -25V
10 = -1.0A
Rs =50Q

V

VGS = 0, Iso = 0.5A

ns

VGS = 0, Iso = 0.5A

VGS = -10V, 10 = -0.2A

15
-1.8
300
300~s

Conditions

VGs =-10V, Vos =-25V
VGS = -5V, 10 = -0.1mA

100

Note 1: All D.C. parameters 100% tesled at 25"C unless olherwlse staled. (Pulse test:

(Notes 1 and 2)

pulse. 2% duly cycle.)

All A.G. parameters sample tested.

Switching Waveforms and Test Circuit
, - - - - - " " " 90%

Input

10%
I(ON)

1---1-"<--0 SCOPE

t(OFF)

D.U.T.
Id(ON)
Oulpul

------.,J
10%

7-36

TP06C

Typical Performance Curves
Output Characteristics

Saturation Characteristics

-2.0

-9V -BV

-1.0

-1.6

-10y~

~~

-O.B

~

en

-BV

CD

E

~

-O.B

-0.6
-5V

~

Q.

E

~

-6V

,

-0.4

.9-

. ~......

-5V
-0.2

fI_

-4V

/
o

-10

-20

-30

-40

-2

-50

Transconductance vs. Drain Current
250

I

I

-4

I

'{

~

l

u.

100

50

l-

55 lc

I I I
TA = 150°C

I

40

I

-

o

a.

,

30

-

TO-220

......

.......

20

Ij

'"

TO-39
TO-92
2.0

1.0

0

25

50

Maximum Rated Safe Operating Area

150

'0
CD
.~

"iii

E
0

r-TQ':;9 '(;6)

CD

Q.

E

w

()

"' "' I\-"' "
"

TO-92 (DC)

......

"'
-10

«fen

(volts)

iii

,

W

0.4

II:
...J

«

~

II:

PD =6W

0.2

Tc = 25°C

w

"

-100
VDS

0.6

Z

I\..

I'

O.B

.s.
TO-220 (DC)

-0.1

125

Thermal Response Characteristics

(pulsed)

~

.9-

100

1.0

I I III

~

75

"' "' -'

Tc(°C)

-10

-1.0

.......

10

TO-39

..

;'

-

ID (amperes)

en

-10

Power Dissipation vs. Case Temperature

r


CO

"

/

V

0.95

0.9

""v

I

I

I

t--VGS = -10V

-

(j)

E
.s:::

12

../

.3-

""V

V

I

VGS = -5V

r-- -

Z

-

-",.,.

~

Y

f-"""

Cl

a:

4

"""
-50

100

-0.2

150

-0.4

-0.6

-0.8

-1.0

10 (amperes)

Transfer Characteristics
-2.0

~
"''''

,

V(th) and Ros Variation with Temperature
1.2

I

1.1

_!::l

I. ~?)r
,v
~ /:",r:;,
/' r-/ ....'"

Cij

1.0

E
0

.s

:2
"'en

0.9

./

~ l/

V

V

,,- V I'
./

"

'0
OJ
N

~

.......

-6

-8

Gate Drive Dynamic Characteristics

~

f= 1MHz

I I I hit'

8

¥

J!!
0

100

S

0
50

~
~

Vos = 10V ~
I

I

170pF

C1SS _

~

~

------

"

10

20

~

Coss

~

V-

CRss
30

I

Jf/

'/

~I

Vos =40V- I----

.... ,P

65 pF
.I
O~

40

1~

1~

QG (nanocoulombs)

Vos (volts)
7-38

a:
0.33

o
150

100

10

2~

E
0
en

t'...
-50

-10

Capacitance vs_ Drain-to-Source Voltage

.!.I

0.66

.s
zQ.

0.7

-4

200

(j)

'ai

Cl

VGS (volts)

150

1.0

~

0.8

~~
~~

1.33

10 = O_2A

-J

/ '/

-2

~

'0
OJ

v
~

~ r- V(th)

1.66

v

2.5

TP06L

"§upertex inc.
P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
Order Number I Package

BVossl

ROS(ON)

IO(ON)

VGS(th)

BVoos

(max)

(min)

(max)

TO-39

TO-92

-20V

2.00

-2.0A

-2.4V

TP0602N2

TP0602N3

-40V

2.00

-2.0A

-2.4V

TP0604N2

TP0604N3

DICE

SOW-20'

-

TP0602ND

TP0604WG

TP0604ND

'Same as SO·20 with 300 mil wide body.

Features

Advanced DMOS Technology

0

Low threshold

0

High input impedance

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

0

Low input capacitance

0

Fast switching speeds

0

Low on resistance

0

Freedom from secondary breakdown

0

Low input and output leakage

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications
0

Logic level interface

0

Solid state relays

0

Battery operated systems

0

Photo voltaic drive

0

Analog switch

0

General purpose line driver

Package Options

TO·39

(Notes 1 and 2)

TO·92

~

Absolute Maximum Ratings

SOW·20

Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Soldering Temperature'
*Oistance of 1.6 mm from case for 10 seconds.

7-39

Note 1:

See Package Outline section for discrete pinouts.

Note 2:

See Array section for quad pinouts.

TP06L

Thermal Characteristics
P~ckage

10 (continuous)"

10 (pulsed)"

.Power Dissipation

81c

@Tc=25°C

°cm

8;_
°C/W

10RM"

lOR

TO-39

-2.0A

-4.8A

6W

20

125

-2.0A

-4.8A

TO-92

-0.75A

-4.2A

lW

125

170

-0.75A

-4.2A

SOW-20

Refer to Arrays & Special Functions Section

* ID (contmuous)

IS

limited by max rated Tj ,

Electrical Characteristics
Symbol

Parameter

Min

I TP0604
I TP0602

Drain-to-Source
Breakdown Voltage

BVoss

(@ 25°C unless otherwise specified)
Typ

Max

Gate Threshold Voltage

iN GSlth)

Change in VGSlth) wilh Temperature

IGSS

Gate Body Leakage

loss

Zero Gate Vollage Drain Currenl

Conditions

V

V GS = 0, 10 = -2.0mA

-2.4

V

V GS = V os ' 10 = -1.0mA

-4.5

mV/oC

V GS = V os ' 10 = -1.0mA

-100

nA

V GS = ±20V, Vos = 0

-10

Il A

V GS = 0, Vos = Max Rating

-1

mA

-20
-1.0

VGSlth)

Unit

-40

(Notes 1 and 2)

-3.0

V GS = 0, Vos = 0.8 Max Rating
TA = 125°C

ON-Slale Drain Currenl

101ON)

-0.4

-0.7

-2.0

-3.3

Slatic Drain-to-Source
ON-Slate Resistance

ROSION)

"'ROSION)

Change in ROSION) wilh Temperature

V GS = -10V, Vos= -25V

2.0

3.5

1.5

2.0

0.75

1.2

G FS

Forward Transconductance

C 1SS

Input Capacilance

85

150

C oss

Common Source Output Capacilance

55

85

C RSS

Reverse Transfer Capacitance

15

35

tQlOr-l]

Turn-ON Delay Time

5

10

t,

Rise Time

7

10

Id OFF

Turn-OFF Delay Time

It

Fall Time

0.4

10

15

6

10
-2.0

Vso

Diode Forward Vollage Drop

-1.3

Reverse Recovery Time

300

V GS = -5V, 10 = -250mA

0

V Gs =-10V,l o =-1.0A
%;oC

VGs =-10V,l o =-1.0A

U

Vos = -25V, 10 = -1.0A

pF

V GS = 0, Vos = -25V
f= 1 MHz

0.65

In

V GS = -5V, Vos = -25V

A

Voo = -25V
ns

10 = -1.0A
Rs = 500

Note 1:

All D.C. parameters 100% tested at 25"C unless otherwise stated. (Pulse test: 300~s pulse. 2% duty cycle.)

Note 2:

All A.G. parameters sample tested.

V

V GS = 0, Iso = -1.5A

ns

V GS = 0, Iso = -1.5A

Switching Waveforms and Test Circuit

1- - :

t(OFF)

-pu~E"

- --"1

GENERATOR

1
\r-~~--~~4

I

I
I
Output

1

----""'"'\I

1
1

10%

:

~

L. _ _ _ _ _ _ _ _ _ _

7-40

I
I

I--"-T--O SCOPE
D.U.T.

TP06L

Typical Performance Curves
Output Characteristics

Saturation Characteristics

4

-10V

J

V

-

~~

IY.

CD

-8V

.!!

-7V

..9

2

~ :::::; ~
......
::;...
~

-SV
-5V

I~

-4V

-10

-20

-30

-40

lI-

./ ~ ~

Co

E

--

V """"

~

-9V

f

f

(i)

-7V
-SV
-5V
-4V

-4

VOS (volts)

-S

-8

-10

VOS (volts)

Transconductance vs. Drain Current

Power Dissipation VS. Case Temperature

1.0

10

Vos = -25V
TA=-55'C
0.8

8

(
TA = 25'C

(i)

c:

CD

TO-39

O.S

E

I

~
~

TA = 150'C

CD

I

I

-

Irf

r--

0.4

(!)

"

4

~

"

........

2

0.2

TO-92

o
4

S

o

10

25

50

10 (amperes)
Maximum Rated Safe Operating Area

100

"

-="'.

125

150

Thermal Response Characteristics
1.0

=- ~

TO-39

1.0
(i)

~

"

TO-92 (OC)

CD

Co

N

(pulsed)

~

0.1

~
E

"
~

f'

E

.!!

I

'C
CD

~u..J..J...

TO-39 (OC)

..9

75

~

Tc('C)

10

U
Z

II

~
en
u;

'II

I'

l'i"I

0.8

0

.s
LJ.J

LJ.J

/

O.S

0.4

/

...J

<

:::iE

c::

I
0.01

o

1

10

0.2

,,/

LJ.J

J:
I-

I
100

./

0.Q1

0.1

tp (milliseconds)

7-41

TO-39

Po =6W
Tc = 25'C-

~
0.001

VOS (volts)

/

/

/
/

c::

t

-9V
-8V

~~
......
-2

-50

-10V

10

TP06L

BVoss Variation with Temperature

On-Resistance vs. Drain Current

1.1

7.5

;'

VGS = -10V

""
./

~

./

~

§

.s

VGS = -5V
6.0

./

1.0

(j)

E

..c:

.,g.

Z

./

I

~

0

/

V

5.0

3.0

a:
~

1.5

0.9

-50

100

o

150

2

4

3

5

10 (amperes)
Transfer Characteristics

V(th) and Ros Variation with Temperature
2.0

Vos = -25V
1.4
4

~
~

~"

'0'
Ql
§
0

1.0

>

0.8

.s
~
Cl

.-

4~

'/ /'

------ -

......... ........ .,- ~

1.6

/'

V

V(th)

~

,,~

'0'
Ql
N

1.2

......... .........

0.8

-50

10

6

100

iil

150

VGS (volts)
Gate Drive Dynamic Characteristics

Capacitance vs. Drain-to-Source Voltage
-10

200

v

I

150
(j)
'0

~

~

100

S"
()

50

f= lMHz

\

-8

Vos =-10V )

~

{
~

Z.

>'"
Cl

~

Coss -

10

20

30

j

-4

~to-"~

If
o

40

75 pF
0.5

"

-

I

-2

C RSS

1-0.

-8

0

CISS -

"
"-

\

/

V

/

7-42

J

V
180 pF

V Vos =-40V

/

i""'"

1.0

1.5

QG (nanocoulombs)

Vos (volts)

(

2.0

.s
z0

rE'

0.6

i-"

~
E

0

.........

0.4

./ ~ /~
4

1.2

N

11"/ ~:L

~~

'0 = -1.0A /

2.5

Alphanumeric Index and Ordering Information
Company Profile
Application Notes
Static Handling Procedures and Quality Assurance
Process Flow
DMOS Product Family
N- and p. Channel Low Threshold MOSFETs

~

~

.-...

..
.-..
....
...-~

i

DMOS Discretes N-Channel
DMOS Discretes P-Channel
DMOS Arrays and Special Functions
HVCMOS High Voltage ICs
CMOS Consumer/Industrial Products

~

I

Lead Bend Options and Surface Mount Packages
Package Outlines

i

Representatives/Distributors

I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

I

~

2N6659

't1I !!!iupertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FET
Ordering Information
BVoss /
BV OGS

Order Number / Package

ROS(ON)

IO(ON)

(max)

(min)

TO-39

1.8n

1.5A

2N6659

35V

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C ISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

Motor control
Converters
Amplifiers
Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO·39

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±40V

Operating and Storage Temperature
Note 1:

Soldering Temperature*Distance of 1.6 mm from case for 10 seconds.

8-1

See Package Outline section for discrete pinouts.

(Note 1)

,

ThermalCha.racteristics
Package
TO-39

10 (continuous)"

10 (pulsed)

I.4A

Power Dissipation
@Tc=25°C

3A

6.25

91a

910

°CIW

.oCIW.

170

2N6es~

20

*10 (continuous) is limited by max rated Tf

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

BVOSS

Orain-to-Source
Breakdown Voltage

VGS(th)

Gate Threshold Voltage

IGSS

Gate Body Leakage

lOSS

Zero Gate Voltage Drain Current

Min

Typ

Max

35
O.B

ON-State Drain Current

ROS(ON)

Static Orain-to-Source
ON-State Resistance

Unit

Conditions

V

10 = 10.,.A, VGS = a

2.0

V

VGS = VOS, 10 = ImA

lOa

nA

VGS = ±15V, VOS = a
VGS = 0, VOS = Max Rating

10
500

10(ON)

(Notes I and 2)

1.5
5.0

f--I.B

Gf'S

Forward Transconductance

CISS

Input Capacitance

170
50

COSS

Common Source Output Capacitance

65

CRSS

Reverse Transfer Capacitance

10

t(ON)

Turn-ON Time

10

t(OFF)

Turn-OFF Time

10

VSO

Diode Forward Voltage Drop

.,.A

VGS = 0, VOS = O.B Max Rating
TA = 125°C

A

VGS = -IOV, VOS ;;. 2 VOS(ON)
VGS = 5V, 10 = 0.3A

n

VGS = 10V, ID = IA
mU

VOS = 24V, 10 = O.SA

pF

VGS = 0, VOS = 2SV
f = IMHz

VOO = 25V, 10 = IA
ns

0.9

RS =
V

son

ISO =-I.4A, VGS = a

Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300l's pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

INPUT

r-;;L~--l

I

:
OUTPUT

I
I
I

GENERATOR

I

V-I~~~~

I

I
I
L _____ J

8-2

I-Uo,,.---G SCOPE

~

D.U.T.

~

2N6660
2N6661

'tlI §upertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
Order Number' Package

BVoss '
BVOGS

ROS(ON)

IO(ON)

(max)

(min)

TO-39

60V

3.00

1.5A

2N6660

90V

4.00

1.5A

2N6661

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Package Options

Applications
o
o
o
o
o
o

Motor control
Converters
Amplifiers
Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO-39

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±30V

Operating and Storage Temperature
Note 1:

Soldering Temperature"
-Distance of 1.6 mm from case for 10 seconds.

8-3

See Package Outline section for discrete pinouts.

(Note 1)

~

..

2N6660/2N6661

Thermal Characteristics
Package

10 (continuous)"

10 (pulsed)"

Power Dissipation

.

(lIe
°CIW

~.

lOR

10RM

@Tc=25°C

°CIW

2N6660

1.lA

3A

6.25W

125

20

2.5A

5.0A

2N6661

O.SA

3A

6.25W

125

20

2.5A

5.0A

.

10 (continuous) is limited by max rated Tj"

Electrical Characteristics
Symbol
BVOSS

VGS(th)
LWGS(th)
IGSS

(@ 25°C unless otherwise specified)

Parameter
Drain-to-Source
Breakdown Voltage

2N6660
2N6661

Gate Threshold Voltage
Change in VGS(th) with Temperature
Gate Body Leakage

Min

Typ

Max

60
SO

2.0

0.8
-3.8

-5.5
100

~
lOSS

Zero Gate Voltage Drain Current

500
10(ON)

ON·State Drain Current

RDS(ON)

Static Drain-Io-Source
ON-State Resislance

GFS
CtSS
Coss
CRSS
td(ON)
tr

1.5
ALL

2N6660
2N6661
Forward Transconductance

5.0
3.0
4.0
170

tf
VSO

Fall Time
Diode Forward Voltage Drop

trr

Reverse Recovery Time

VGS

= 0.10 = 10~A

V

VOS

= VGS.

mVtC
nA

Il A

10 = lmA

VGS = VDS. 10 - lmA
VGS - 15V. VDS - 0
VGS = 15V. VDS" O. TA = 125'C
VGS - O. VDS - Max Rating
VGS - O. VDS - O.B Max Rating
TA = 125°C

A

VDS

n

VGS
VGS
VGS

m15
40
10
10

Reverse Transfer Capacitance

td(OFF)

V

= 25V.

VGS

= 10V

= 5V. ID = 0.3A
= 10V. ID = lA
= 10V. ID = lA
VDS - 25V.10 = 0.5A

50

I nput Capacitance
Common Source Output Capacitance
Turn·ON Delay Time
Rise Time
Turn·OFF Delay Time

Conditions

Unit

10

r---

(Notes 1 and 2)

pF

VOS = 25V. VGS = 0
f = lMHz

ns

VDD = 25V. RL = 23n'
RS = 25n

10
1.2
350

V
ns

Note 1: All D.C. parameters 100"10 tested at 25'C unless otherwise stated. (Pulse test: 300ms pulse, 2"10 duty cycle.)
Note 2: All A.C. parameters sample tested.

8·4

VGS - O. ISO

lA

VGS-0.ISD-1A

2N7000

"§upertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FET
Ordering Information
BVoss '
BVoos

ROS(ON)

IO(ON)

Order Number' Package

(max)

(min)

TO-92

SOV

50

75mA

2N7000

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C fSS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

Motor control
Converters
Amplifiers
Switches
Power supply circuits

i

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO-92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±40V

Operating and Storage Temperature
Note 1:

Soldering Temperature'
"Distance of 1.6 mm from case for 10 seconds.

8-5

See Package Outline section for discrete pinouts.

(Note 1)

•

2N7000

Thermal Characteristics
Package

10 (continuous)"

10 (pulsed)"

Power' D'ssipation

TO-92

200mA

500mA

400mW

11'8
°CIW

lI,e

°C/W

' 312,5

40

*ID (continuous) is limited by max rated Tj'

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Paramater

BVDSS

Drain-to-Source
Breakdown Voltage

VGS(th)

Gate Threshold Voltage

IGSS

Gate Body Leakage

IDSS

Zero Gate Voltage Drain Current

Min

Typ

Max

60
0,8

(Notes 1 and 2)
Conditions

Unit
V

ID = lOIJ.A, VGS = 0

3,0

V

VGS = VDS, ID = 1mA

10

nA

VGS = ±15V, VDS = 0

1

IJ.A

VGS = 0, VDS = 48V
VGS = 0, VDS = 48V

1

mA
TA = 125'C

ID(ON)

ON-State Drain Current

RDS(ON)

Static Drain-to-Source
ON-State Resistance

GFS

Forward Transconductance

75
5
100

CISS

Input Capacitance

60

COSS

Common Source Output Capacitance

25

CRSS

Reverse Transfer Capacitance

t(ON)

Turn-ON Time

10

t(OFF)

Turri-OFF Time

10

VSD

Diode Forward Voltage Drop

mA

VGS = 4.5, VDS = 10V

n

VGS = 10V, ID = 0.5A

mU

VDS = 10V, ID = 0.2A

pF

f = lMHz

VGS = 0, VDS = 25V

5
VDD = 15V, ID = 0.5A
ns
-0.85

RS =
V

son

ISD = -0.2A, VGS = 0

Note 1: All D.C. parameters 100% tested at 2S'C unless otherwise stated. (Pulse test: 300IJ.S pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

r - ;;:;L-;; --,

INPUT

I
I
I
I

OUTPUT

GENERATOR

I

\r-I~+-~~

I

I

IL _____ JI

8-6

1-~-_oSCOPE

D.U.T.

2N7007

"§upertex inc.
I

N-Channel Enhancement-Mode
Vertical DMOS Power FET
Ordering Information
BVoss I
BVOGS

ROS(ON)

'O(ON)

(max)

(min)

Order Number I Package
T()'92

45Q

150mA

2N7007

240V

Features

Advanced DMOS Technology
These enhancement·mode (normally·off) power transistors util·
ize a vertical DMOS structure and Supertex's well·proven silicon·
gate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermally·
induced secondary breakdown.

D

Freedom from secondary breakdown

D

Low power drive requirement

D

Ease of paralleling

D

Low C1SS and fast switching speeds

D

Excellent thermal stability

D

Integral Source· Drain diode

D

High input impedance and high gain

D

Complementary N· and P·Channel devices

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high break·
down voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications
D

Motor control

D

Converters

D

Amplifiers

D

Switches

D

Power supply circuits

D

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

Package Options

i

TO-92

Absolute Maximum Ratings
Drain·to·Source Voltage
Drain·to·Gate Voltage
Gate·to·Source Voltage

±40V

Operating and Storage Temperature
Note 1: See Pacl

Note 1: See Package Outline section for discrete pinouts.

"Distance of 1.6 mm from case for 10 seconds.

8-9

(Note 1)

•

.!.-

2N7008

Thermal Characteristics
Package

TO-92

10 (continuo.us)"

10 (pulsed)

Power Dissipation

BJa

BI•

°CIW

°CIW

lA

400mW

312.5

150mA

40

'1 0 (continuous) is limited by max rated \

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

BVOSS

Orain-to-Source
Breakdown Voltage

VGS(th)

Gale Threshold Voltage

IGSS

Gate Body Leakage

lOSS

Zero Gate Voltage Orain Current

Min

Typ

Max

Unit

Conditions

=

10

2.5

V

VGS

= VOS,

100

nA

VGS

= ±30V, VOS = a
= OV, VOS = 50V

VGS

= OV, VOS = 50V

mA

VGS

= 10V, VOS '"

VGS

= 5V,

10

=

VGS

= 10V,

10

= 500mA

TA

ROS(ON)

Static Orain-to-Source

500

-

ON-State Resistance

7.5

n

7.5

GFS

Forward Transconductance

CISS

Input Capacitance

50

COSS

Common Source Output Capacitance

25

80

=

VGS
Reverse Transfer Capacitance
Turn-ON Time

20

t(OFF)

Turn-OFF Time

20

VSO

Oiode Forward Voltage Orop

Note 1:
Note 2:

pF
f

CRSS

125°C
2 VOS(ON)

SOmA

VOS '" 2 VOS(ON), 10

mu

t(ON)

10 '" 250.,A

VGS

500
ON-State Orain Current

-10.,A, VGS

fJ.A

1

f--

10(ON)

=a

V

60
1

(Notes 1 and 2)

=

=

0, VOS

= ·200mA

= 25V

lMHz

5
VOO

= 30V,

ns
-1.5

V

10

=

200mA

RS

=

son

ISO

=

-150mA, VGS

=a

All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300". pulse, 2% duty cycle.)
All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

INPUT

OUTPUT

r I
I
I

II

;7;L;'; - - ,

GENERATOR

I
I

I
I
L _____ J

8-10

I -.....--QSCOPE

\r-I~+-~~

-=

D.U.T.

IRF510

:~~m

"§upertex inc.

IRF513
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVDSS I
BVDGS

RDS(ON)

ID(ON)

Order Number I Package

(max)

(min)

T()"220

0.6n
0.6n

4.0A
4.0A

IRF510
IRF511

0.8n
0.8n

3.5A
3.5A

IRF512
IRF513

100V
60V
100V
60V

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C1SS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Package Options

Applications
o
o
o
o
o
o

Motor control
Converters
Amplifiers
Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

GDS
TO·220

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Soldering Temperature·

Note 1:

*Oistance of 1.6 mm from case for 10 seconds.

8-11

See Package Outline section fro discrete pinouts.

(Note 1)

IRF5101lRF51111RF5121IRF513

Thermal Characteristics
Package

'10 (continuous)·

IRF510
IRF511
IRF512
IRF513

.

10 (pulsed)·

4.0A
4.0A
3.5A
3.5A

10 (continuous)

,

IS

Power Dissipation
@Tc=25°C,

16.0A
16.0A
14.0A
14.0A

,IIJe

IIJa

'jCIW

°CIW

20W
20W
20W
20W

6.4
6.4
6.4
6.4

80
80
80
80

lOR

'ORM·

4.oA
4.0A
3.5A
3.5A

16.0A
16.0A
14.0A
14.0A

,

limited by max rated Tr

Electrical Characteristics
Symbol

Parameter

BVoss

Drain-to-Source
Breakdown Voltage

VGS(th)

Gate Threshold Voltage

IGSS

Gate Body Leakage

(@ 25°C unless otherwise specified)
Min

IRF510,IRF512

100

IRF511, IRF513

60

Typ

Max

2.0

Conditions

Unit
V

VGS = 0, 10 = 2501lA

4.0

V

VGS = Vos' 10 = 250ltA

500

nA

VGS = ±20V, Vos=O
VGS = 0, Vos = Max Rating

250

1000

Zero Gate Voltage Drain Current

loss

(Notes 1 and 2)

itA

VGS = 0, Vos = 0.8 Max Rating
Tc = 125°C

ON-State Drain Current

10(ON)
ROS(ON)

Static Drain-to-Source
ON-State Resistance

IRF510, IRF511

4.0

IRF512,IRF513

3.5

IRF510, IRF511

0.6

IRF512,IRF513

0.8

GFS

Forward Transconductance

C,SS
Coss

Input Capacitance

150

Common Source Output Capacitance

100

1.0

1.5

CRSS

Reverse Transfer Capacitance

25

td(ON)
t,

Turn-ON Delay Time

20

Rise Time

25
25

td(OFF)

Turn-OFF Delay Time

4

Fall Time

Vso

Diode Forward

IRF510,IRF511

Voltage Drop

IRF512,IRF513

Vos > 10(ON) X ROS(ON) Max Rating

n

VGS = 10V, 10 = 2.0A

U

Vos > 10(ON) x ROS(ON) Max Rating
10= 2.0A

pF

VGS = 0, Vos = 25V
f= 1 MHz

VDO = 0.5BV 055
10 = 2.0A
Rs= 50n

ns

20
2.5

~

Reverse Recovery Time

trr

VGS -10V

A

230

Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test:
Note 2: All A.C. parameters sample tested.

300~s

VGS = 0, Iso = 4.0A
VGS = 0, Iso = 3.5A

V
ns

TJ = 150°C, Iso = 4.0A,
dl F/dt = 100A/ItS

pulse, 2% duty cycle.)

Switching Waveforms and Test Circuit

Input

I----PULSE---i

i

10%
t(ON)

'(OFF)

1
1
1
1
1
1

'd(ON)
Output _ _ _ _-----.]
10%

GENERATOR

i'"

1

V-~~--~~

'- _ _ _ _ _ _ _ _ _ _1

8-12

I-~---- 10(ON) X ROS(ON) Max Rating
10 = 4.0A

pF

VGS = 0, Vos = 2SV
f= 1 MHz

ns

Voo = O.SBVoss
10 = 4.0A
Vos = O.S Max Rating

V

VGS = OV, Iso = lA

ns

VGS = OV, Iso = SA
Tj = lS0°C, IF = S.OA,
dlF/dl = 100AlllS

70
IRFS20, IRFS21
RS20 RS21
IRFS22, IRFS23

2.S
2.3

Reverse Recovery Time

trr

Q

0.4

CISS

Diode Forward
Voltage Drop

VGS = 10V
Vos > 10(ON) X ROS(ON) Max Rating

2S0

Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300"s pulse. 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit
~----"90%

Input

I----pULSE---i

i

10%
t(OFF)
td(ON)

Output _ _ _--:~

10%

GENERATOR

1
1
1
1
1
1

10%

i""

1
\~~+-~~-+~

L.. _ _ _ _ _ _ _ _ _ _

S-14

I1

I-~-OSCOPE

D.U.T.

IRF531
R531

(JJ §upertex inc.

Preliminary

N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss I
BVOGS

ROS(ON)
(max)

IO(ON)
(min)

SOV

O.18!l

12.0A

Order Number I Package
TO-39

I

TO-92

IRF531

I

R531

Features

Advanced DMOS Technology

o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain

Package Options

Applications
o
o
o
o
o
o

Motor control
Converters
Amplifiers
Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

GOS
TO-92
With TO-220
pinout

i

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature>

±20V
-55°C to + 150°C
300°C

*Distance of 1.6 mm from case for 10 seconds.

8-15

(lead bend
option: Pt t)

GOS

GOS

TO-92

TO-220

IRF53f/R531

Thermal Characteristics
Package

10 (continuous)·

IRF531
R531

10 (pulsed)·

Power, Dissipation
@TC=25°C

91e

91a

°C/W ,',

lOR

10RU·

°C/W

14.OA

56.0A

75W

SO

3,12

14.0A

56.0A

1.5A

15.0A

1W

170

125

1.5A

15.0A

.' 0 (continuous) is lim~ed by max rated Tr

Electrical Characteristics (@ 25°C unless otherwise specified)
Min

Typ

Max

'Symbol

Parameter

BVoss

Drain-to-Source Breakdown Voltage

60

VGS(th)

Gate Threshold Voltage

2.0

IGSS

Gate Body Leakage

loss

Zero Gate Voltage Drain Current

250

Unit

(Notes 1 and 2)
Conditions

V

VGS = 0, 10 = 250j!A

4.0

V

VGS = Vos' 10 = 250j!A

500

nA

VGS = ±20V, Vos = 0
VGS = 0, Vos = Max Rating
VGS = 0, Vos = O.S Max Rating

~

/!A

TA = 125°C
10(ON)

ON-State Drain Current

ROS(ON)

Static Drain-to-Source
ON-State Resistance

GFS

Forward Transconductance

C,SS
Coss

Input Capacitance

SOO

Common Source Output capacitance

500

CRSS

Reverse Transfer Capacitance

150

td(ON)

Turn-ON Delay Time

30

tr

Rise Time

75

td(OFF)

Turn-OFF Delay Time

40

~
Vso

Fall Time

45

12.0
0.1S
4.0

Diode Forward Voltage Drop

Vos > 10(ON) x ROS(ON) Max Rating

Q

VGS = 10V, 10 = S.OA

U

Vos > 10(ON) x ROS(ON) Max Rating
10 = S.OA

pF

VGS = OV, Vos = 25V
f= 1 MHz

ns

VDO = 0.5BV oss
10 = 4.0A
Vos = O.S Max Rating

V

VGS = OV, Iso = 1A
VGS = OV, Iso = SA

2.5

2:3"
Reverse Recovery Time

t"

VGS = 10V

A

360

ns

TJ = 150°C, IF = S.OA,
dlFldt = 1OOAl/!S

Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 30011" pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

Input

1----puLSE---l

i

10%
t(ON)

t(OFF)

GENERATOR

I
I
I
I
I
I

td(ON)
Output _ _ _ _-"'\I

10%

I
V-~~--~~

i ' "______II
~----

S-16

I---'>T~JSCOPE

D.U.t.

,

VN01A

"§upertex inc.
I

N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVDSS '
BVDGS

RDS(ON)

Order Number' Package

ID(ON)

(max) (min)

To-39

TO-92

TO-52

To-220

Quad P-DIP Quad C-DIP Quad C-LCC

-

DICE

40V

30

2.0A

VN0104N2

VN0104N3

VN0104N9

VN0104N5

VN0104N6

VN0104N7

60V

30

2.0A

VN0106N2

VN0106N3

VN0106N9

VN0106N5

VN0106N6

VN0106N7

VN0106NE

VN0106ND

90V

30

2.0A

VN0109N2

VN0109N3

VN0109N9

VN0109N5

-

VN0109NE

VN0109ND

-

VN0104ND

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C ISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

Motor control
Converters
Amplifiers
Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

Absolute Maximum Ratings

TO·220

Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

16·Terminal LCC

±20V

Operating and Storage Temperature
Soldering Temperature>

14·Lead DIP

300°C

·Dlstance of 1.6 mm from case for 10 seconds.

8-17

•

i

VN01A

Thermal Characteristics
ID (continuous)"

Package

..

ID (pulsed)"

"

TO-39
TO-92
TO-52
TO-220
Plastic DIP
Ceramic DIP
Ceramic LCC

0.8A
0.5A
0.5A
1.5A

2.5A
2.0A
2.0A
2.5A

Power Dissipation
@Tc=25°C
3.5W
1.0W
1.0W
15.0W

811
°CIW
125
170
170
70

81c

. IDR

IDAM"

0,08A
0.5A
0.5A
1.5A

2.5A
2.0A
2.0A
2.5A

~CIW
..

35
125
125
8

See DMOS Arrays & Special Functions section

..

• '0 (continuous) IS limited by max rated Ti"

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter
Drain-to-Source
Breakdown Voltage

BVoss

VGSllh)
I!.VGSllh)

Gate Threshold Voltage

IGSS

Gate Body Leakage

loss

Zero Gate Voltage Drain Current

Min
VN0109

90

VN0106
VN0104

60
40
0.8

Change in VGSllh) with Temperature

Typ

Max

Unit
V

2.4

VGS = 0, 10 = 1mA

-3.8

-5.5

V
mV/oC

0.1

100

nA

-

VGS = Vos' 10 = lmA
VGS = Vos' 10 = lmA
VGS = ± 20V, Vos = 0
VGS = 0, Vos = Max Rating

1
100

(Notes 1 and 2)
Conditions

VGS = 0, Vos = 0.8 Max Rating

IlA

TA = 125°C
ON-State Drain Current

101ON)

0.5

1.0

2.0

2.50

Static Drain-to-Source
ON-State Resistance

4.50

5

2

3

I!.RoSION)
GFS

Change in ROSION) with Temperature

0.70

1

CISS

Input Capacitance

45

60

Coss
CRSS

Common Source Output Capacitance

20

25

Reverse Transfer Capacitance

2

5

tdON

Turn-ON Delay Time

3

5

t,

Rise Time

5

8

tdIOFF)
tf

Turn-OFF Delay Time

6

9

Fall Time

5

8

Vso

Diode Forward Voltage Drop

1.2

1.8

trr

Reverse Recovery Time

ROSION)

Forward Transconductance

300

VGS = 5V, VOS = 25V
VGs =10V,Vos =25V
VGS = 5V, 10 = 250mA

A
n
%/oC

VGS = 10V, 10 = lA
VGS = 10V, 10 = lA

mU

Vos = 25V, 10 = 0.5A

400

400

pF

VGS = 0, Vos = 25V
f=l MHz

ns

Voo= 25V
10= lA
Rs=RL=50n

V

VGS = 0, Iso = 2.5A

ns

VGs=O,lso=lA

Note 1: All D.C. parameters 100% tested al 25°C unless otherwise stated. (Pulse test: 300~s pulse, 2% duly cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

Input

I----pULSE---i

i

10%
t(ON)

t(OFF)

I

GENERATOR

1
v-~+-r-~-+~

1
1

1

OUlput _ _ _ _--.I

10%

1

10%

1

i'- __________
'"
1
8-18

I-~-OSCOPE

D.U.T.

VN01A

Typical Performance Curves
BVDSS Variation with Temperature

ON - Resistance Vs. Drain Current
5

1.1

,/'

w

N

:J

/'

«
::;;
II:
0

~
en

~

>
CD

J:

,/

V

V

3

Q

I
..,;1'

Z

V

/

J

en:;;

V

/"

1.0

I

JGS~ 16v

4

,/

i3

~GS =5V

0

en

2

0
II:

0.9

o

-50

50

100

o

150

o

0.5

1

TJ ('C)

I I
TA = -55'C

enw

II:
Q.

1/'

J

~
o

~

A

1.4
10= 1.0A~

i3

w

N

:J
«
::;;

125'C

1.2

r

t!l

>

,

~

0.8

t:/

0.6

4

2

8

6

10

"""

Capacitance Vs. Drain-to-Source Voltage

t"--

~
«
II:
«
u.

50

0

()

~
()

25

o

......

0.7

i"-..

100

150

Gate Drive Dynamic Characteristics
10
VOS = 10

fllMHz

/ /

~

~

6

/

-'

""--

o

/

/ 4t r--

S

0

~

CISS

en
t!l

SOpF

VV

/ /

2

....... !5""""
/40PF

I-CRSS

10

V

V t'

4

>

r-COSS.....

/

0
20

30

40

o

0.2

0.4

0.6

O.S

QG (NANOCOULOMBS)

VOS (VOLTS)

8-19

«
::;;
II:

Z
0

13
II:

TJ ('C)

100

w

0
~

1.0

50

VGS (VOLTS)

75

1.3

0.4

o

-50

i3
:J

~

~ .......... .......

1.6

N

~P" 10=0.lA

1.0

~
en

V

J

~(th)

II:

0
~

U

0.5

1.9

'1/

//

1.0

E

0

1.6

!- 25'C

'b
I. ~ -

1.5

::;;

5

1- ./

I;"

w

2.5

V!th) and RDS Variation with Temperature

Transfer Characteristics
2.5

2.0

2

1.5

lOS tAMPS)

1.0

•

VN01A

Saturation Characteristics

Output Characteristics
2.5

2.5
VGS = 10V

~~

2.0

Ci)

w

a:
w

IV: v:
V
P. /

1.5

::.
!!
9

w

0.5

o

a:
w

6V

::.
!!
9

k

0

o

e

1.0

10

~

0.5

'4\

V

1.5

0..

f'

1.0

....."!! ~

Ci)

~

0..

20

30

40

50

::.
w
iii
Vl

25

O.S

20

TA =-55°C

0.6

u.

/

0

!c

125°C

/

(!)

I. 0-

0.2

~
I-

25°C

/

4\1

I~

I?

o

4

2

"

......

0..

TO-39

5

TO-9d
0

O.S

0.4
0.6
I D (AMPERES)

o

1.0

-

I--

25

50

.......

-

"t---

..........

75
100
TC (C)

1.0

TO-39,~O-~20(PULSED)
1----1--

0W

,

N

:::;

«
a:
0
S

~"I}~

a:

w

"\

0..

::.

);

~OJ
)'Q~
Y
'%lr.;

o~ ~"

!!

.,~

0.1

w
u

~
Vl

iii

'1

10

0.4

/

/

L

~

150

/

./

0.2

:I:

100

VDS (VOLTS)

8-20

0
0.001

I

L TO·92

.../

a:
w

I-

/

~

..J

::.

~

Y

a:

«

)~

1

~

125

V
./

w

LIMITED
BY BVDSS
I II
I
0.1

0.6

z

I

I II "'\...
0.01

O.S

TO-220
TC = 25°C
PD = 15W

::.

'rQ~_

1.0
Ci)
w

10

Thermal Response Characteristics

Maximum Rated Safe Operating Area
10.0

9

S

"'- ~

10

VDS = 25V
0.2

6

TO-220

15

,/

l~

o

-

Power Dissipation Vs. Case Temperature

1.0

0.4

SV

r::::: :.- BV

Vos (VOLTS)

Transconductance Vs. Drain Current

zw

~ ~~
;:/

~?

~ .........

VDS (VDLTS)

Ci)

--

VGS =!.Z-V

2.0

-----

0.01

0.1
tp (SECONDS)

TA = 25°C
rD= lW

10

~

VN01C

'flI !iupertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
Order Number I Package

BVoss I
BVOClS

ROS{ON)

IOION)

(max)

(min)

TO-39

TO-92

TQ-220

Dice

160V

100

0.4A

VN0116N2

VN0116N3

VN0116N5

VN0116ND

200V

100

O.4A

VN0120N2

VN0120N3

VN0120N5

VN0120ND

Features

Advanced DMOS Technology
These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

D

Freedom from secondary breakdown

D

Low power drive requirement

D

Ease of paralleling

D

Low CISS and fast switching speeds

D

Excellent thermal stability

D

Integral Source-Drain diode

D

High input impedance and high gain

D

Complementary N- and P-Channel devices

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications
D

Motor control

D

Converters

Package Options

~

D Amplifiers
D

Switches

D

Power supply circuits

D

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

i

Absolute Maximum Ratings

TO·220

TO-92

(Note 1)

i

Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Note 1:

Soldering Temperature"
"Distance of 1.6 mm from case for 10 seconds.

8-21

See Package Outline section for discrete pinouts.

TO-39

•

VN01C

Thermal Characteristics

.

..

ID (continuous)'

Package

ID (pUlsed)'

Power Dissipation

9)a

91c

@Tc=2SoC

°CIW

°CIW

IDR

IDRM

TO-39

350m A

1.0A

3.5W

125

35

350mA

LOA

TO-92

250mA

0.9A

1.0W

170

125

250m A

0.9A

700mA

UA

15.0W

70

8.3

700mA

1.2A

TO-220
• 10 (continuous)

IS

limited by max rated Tj'

Electrical Characteristics
Symbol
BVDSS

VGS(th)
t>VGS(th)
IGSS
IDSS

(@ 25°C unless otherwise specified)

Parameter
Drain-la-Source
Breakdown Vollage

Min

VN0120
VNOl16

Gate Threshold Voltage
Change in VGS(th) with Temperature
Gate Body Leakage

Typ

Max

Unit

200
160
1
-5.1
0.1

Zero Gate Voltage Drain Current

3
-6_0
100
10

ID(ON)

ON-State Drain Current

RDS(ON)

Static Drain-lo-Source
ON-State Resistance

t>RDS(ON)
GFS
CISS
Coss
CRSS
td(ON)
tr
td(OFF)
tf

VSD
trr

0.3
0.4

0.5
0.8
10

B

Change in RDS(ON) with Temperature
Forward Transconductance
Input Capacitance
Common Source Output Capacitance
Reverse Transfer Capacitance
Turn-ON Delay Time
Rise Time
Turn-OFF Delay Time
Fall Time
Diode Forward Voltage Drop
Reverse Recovery Time

1.0
100

Conditions

V

ID = lmA, VGS = 0

V

VGS = VDS, ID = lmA

mVtC
nA
jJ.A

1

mA

15

150
40

55

20
5
3
5

30
8
5
8

6
5

9
8

1.2
400

1.8

VGS-VDS,ID=lmA
VGS - ±20V, VDS - 0
VGS - 0, VDS - Max Rating
VGS - 0, VDS = 0.8 Max Rating
TA'" 125°C
VGS - 5V, VDS - 25V
VGS = 10V, VDS - 25V
VGS - 5V, ID = 100mA,
VGS = 10V, ID - 100mA,

A

10
1.2

(Notes 1 and 2)

n

%tc

ID = 500mA, VGS = 10V
VDS = 25V, ID ~ 250mA

mU
pF

VGS = 0, VDS = 25V,
f = lMHz

ns

VDD = 25V, 10 = 250mA,
RS= 50n

V
ns

ISD = 2.5A, VGS = 0
ISD= lA, VGS = 0

Note 1: All D.C. parameters 100% tested at 25"C unless otherwise stated. (Pulse test: 300l1s pulse, 2% duty cycle.)
Note 2: All A.C. perameters sample tested.

Switching Waveforms and Test Circuit

INPUT
liON)

OUTPUT

IIOFFI

r - ;:L-;; --,
I
I
I

lI

GENERATOR

I

~I~r-~~

I

I
I

L _____ J -::-

8-22

I-'~-OSCOPE

D.U.T.

VN01C

Typical Performance Curves
Saturation Characteristics

Output Characteristics

iii
w

2.0

1.0

1.6

0.8

iii

1.2

VGS= 10V;;
BV

_1--"'

II:
W

Do

:;

:!
E

0.8

p

0.4

)
I.

~

~

p0-

~

::::;;o-t-

w
w

It
Do

:;

6V

:!

E

---

~V-

~~

0.4

10

30

40

4v

V

1

20

1

/

~ V"

0

o

.-:::::::.---t::I~

",-"

~ F""""
0.2

IY

0

VGS= 10V

0.6

o

50

2

4

8

6

10

VDS (VOLTS)

VDS (VOLTS)

Power Dissipation Vs. Case Temperatu re

Transconductance Vs. Drain Current
0.20

25

..

VDS = 25V
TAI= .sJoc_

V

0.16

1

25°C_

I'

r

iii
z
w
:;
w

§

en
u.

20

125°C-

0.12

TO·220

15

I..........

0.08

"-

10

c.!l

0.04

5

--

TO-39
TO·92

o

o

o
0.2

0.4

0.6

0.8

o

1.0

25

50

--~ 10-

1\
0.1

iii
w

It

w

~ 1

~r,ov

'"

)'o~~1l'
. ~o
.l'O~Q".I':;

\9,,'0

Do

0w
:J
0(
:;

0

75

100

w

0.6

z0(
t-

/

004

:;
w

LIMITED
BY BVDSS

It

I

t-

~

125

150

..-----7
/

/

O

i-""'"

0.001

./

/'
/V

/

/'
0.01

TC = 25°C
PD = 3'jW
0.1
tp (SECONDS)

Vos (VOLTS)

8-23

/

/TO-39

0.2

:r

1000

/

If

It
..J
0(

i-""'"

/'

u

en
iii
w

100

TO-220
TC = 25° C
PD= 15W./

II:

'/ \.::

10

0.8

0

6

-'

0.001

I----

N

t}
0.01

-

.........

t---

1.0

"-~~ O"'.;l
" I
Y.ov
0r,o
I".I'Q
~
,<9 ~~~o -'Il'",-

:;

:!
E

r---.

Thermal Response Characteristics

Maximum Rated Safe Operating Area
TO·220(DC)

.......

TC (oe)

I D (AMPERES)

1.0

r---.

1.0

10

VN01C

BVDSS Variation with Temperature

ON· Resistance Vs .Drain Current
25

1.1

I

,/
20

0:
N

0

0:;
::ii

/

::i
~
:;

a:

I

/""

w

1.0

1/

~
Vl
Vl

Cl

>

V

'"

V

:I:

Q

/

/

15

~

L

./

Z
0

I

VGS=5V

~ f.;'"

10

a:

I--

r-

-

/

!-'VGS=10V -

r--

./

5

0.9

o

o

-50

50

100

150

o

0.2

0.4

V/th) and RDS Variation with Temperature

Transfer Characteristics
1.0

~
(Iv

VDS = 25V
TA = ·55°C

0.8

0:;
UJ

a:

w
:;

""

5
9

0.4

0.2

0

'{

ID =500mA
1.2

~, /25'C

0.6

'fA

/h
'1/

0:
w

N

~

::i

/h \

:;

VI

2

,,

~Vhh)
1.1

~

a:
0

125'C

1.0

~

:c
.::
Vl

0.9

t:I

>

/

V

-?

l/

#'

4

8

6

~

"'-

"-

a:

8

~

50

~

0

U

~
u

25

0

o

V.

/. V

6

'"

10

CISS-

--- 20

0.2

150

VDS= 10V
100pF

u.

"-

100

50

f= lMHz

~

o
40

VDS (VOLTS)

/~

If
o

v.: /

~OPFI
0.2

0.4

0.6

0.8

QG (NANOCOULOMBS)

8·24

V,JPF

/. /

2
CRSS

~v'

/. /

r-COSS-

30

~

/ /

4

0
~
0

~

a:

10

75

a:

Z

0.6

Gate Drive Dynamic Characteristics

Capacitance Vs. Drain·to,Sol!rce Voltage

N

:;

TJ ('C)

100

0:
w
::i

"

VGS (VOLTS)

~

1.4

rfIII' 1"'-

o

1.8

1.0

ID=500mA

-50

10

l#

l#
~=100mA

0.8

~IY

o

0.8

0.6

IDS (AMPERES)

TJ tC)

1.0

VN02A

"§upertex inc.
N.;Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
Order Number' Package

BVoss '

RDS(DN)

ID(DN)

BVoos

(max)

(min)

TO-39

TO-92

TO-220

Quad P-DIP

40V

20

3.0A

VN0204N2

-

VN0204N5

VN0240N6

VN0204N7

60V

20

3.0A

VN0206N2

VN0206N3

VN0206N5

VN0206N6

VN0206N7

100V

20

3.0A

VN0210N2

VN0210N3

VN0210N5

-

Quade-DIP

-

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C 1SS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally SUited to a wide
range of switching and amplifying applications where high breakdown voltage. high input impedance, low input capacitance,and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Notes 1 and 2)

Motor control
Converters

i

Amplifiers
Switches
Power supply circuits

TO-92

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)
TO·39

Absolute Maximum Ratings

TO·220

Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature'

14·Lead DIP

±20V
-55°C to + 150°C

Note 1: See Package Outline section for discrete pinouts.
Note 2: See Array section for quad pinouts.

300°C

*Oistance of 1.6 mm from case for 10 seconds.

8-25

-

VN02A

Thermal Characteristics
Package
TO-39
TO-92
TO-220
Plastic Dip
Ceramic Dip

10

(continuous)"

10

(pulsed)"

1.5A
0.8A
3.0A

.

.c-

Power Dissipation
@Tc=2SoC

4A
4A
4A

4W
lW
28W

"

~c
°CiW

~.
. o¢1W

lOR

10RM

25
125
4.8

125
170
70

2A
0.8A
3A

4A
4A
4A

Refer to Arrays and Special Functions section:

*'D (continuous) is limited by max rated Ti"

Electrical Characteristics
Symbol

BVoss

(@ 25°C unless otherwise specified)

Parameter
Drain-to-Source
Breakdown Voltage

Min
VN0204

60

VN021 0

100

VGS(th)

Gate Threshold Voltage
Change in VGS(th) with Temperature

IGSS

Gate Body leakage

0.8
-3.8

..

loss

Zero Gate Voltage Drain Current

10(ON)

ON-State Drain Current

Max

1.2

1.6

3.0

4.0

100

nA

25

itA
mA

VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Rating
TA = 125°C
VGS = 5V, Vos = 25V
VGS = 10V, Vos = 25V

A
2.5

1.5

2

!!.ROS(ON)

Change in ROS(ON) with Temperature

0.5

0.75

GFS
CISS

Input Capacitance

85

150

Coss
CRSS

Common Source Output Capacitance

50

85

Reverse Transfer Capacitance

12

35

td(ON)

Turn-ON Delay Time

10

tr

Rise Time

10

td(OFF)
tf

Turn-OFF Delay Time

Vso

Diode Forward Voltage Drop

trr

Reverse Recovery Time

VGs=5V,lo=IA
0
%/OC

VGS = 10V, 10 = 2A
VGS= 10V, 10=2A

U

Vos = 25V, 10 = 2A

pF

VGS = 0, Vos = 25V
f= I MHz

ns

Voo = 25V
10 = 0.5A
Rs = 500

V

VGS = 0, Iso = 1.5A

ns

VGs=O,lso=IA

0.65

25

Fall Time

VGS = Vos ' 10 = 2.5mA
VGS = Vos ' 10 = 2.5mA
VGs =±20V, Vos=O

V
mV;oC

1.6

0.4

VGS = 0, 10 = 2.5mA

2.4

1

Forward Transconductance

(Notes 1 and 2)
Conditions

V

-4.5

Static Drain-to-Source
ON-State Resistance

ROS(ON)

Unit

40

VN0206

!!.VGS(th)

Typ

13
1.2

1.8

330

Note 1: All D.C. parameters 100% tesled at 25'C unless olherwise slaled. (Pulse lest: 300~s pulse, 2% duly cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

I----PULSE---i
:

Output _ _ _ _--,j

10%

GENERATOR

I
I
I
I
I
I
:.,.

10%

~----

8-26

I

v-~~--~~

I
______ I

f-.,....~OSCOPE

D.U.T.

VN02A

Typical Performance Curves
Saturation Characteristics

Output Characteristics
5

5

4

"iii

w

a:
w

I I I
Jj,v

-

4

VGS

,

~~

3

0..

6V_

.-,,::; /:-::==

-

3

:<

5
9

F~ ~:;;;.. r-\r=10~
~ .... 6V"
.......

~

2

2

I

•
I

4V -

V

,

o

-

-

~
.....

,....
J

I

o 'r

o

10

20

30

40

o

50

r--

4V

4

2

VOS (VOLTS)

8

6

10

VOS (VOLTS)

Transconductance Vs. Drain Current

Power Dissipation Vs. Case Temperature

1.0

50
. TA --55°C

II

0.8

"iii

zw
:<
w
§
Vl

40

,

0.6

I

0.4 I

u.

(!)

I
0.2 ,

25°C
30

r---,
TO-220

.........

125°C

20

V
1

VOj = i5V t---

"-

"'-.
"'-.

10

-

"-

TO-39

o
o

o
2

5

4

3

o

25

50

75

125

150

Thermal Response Characteristics

Maximum Rated Safe Operating Area
10

1.0
-

TO·220 (PULSED)

>-.

~"0

- -....,
"iii
w
a:
w

~

0..

:<

5

9

'"""

100

TC (oC)

10 (AMPERES)

0.1

i5

,

w

N

:J
«
:<

0.8

a:

,

0

'/

~

w

0.6

z

«
f-

"

Vl

iii
w

,/

a:

,/

«

:<

0.2

. / i-""

a:
w

J:
f-

10

V

0.4

.J

0.01
1

1/

C)

100

1000

o

~

0.001

Pulse Condition: 300 ".'. 2% Outycycle.

~

:11
0.01

0.1
tp (SECON OS)

VOS (VOLTS)

8-27

TO-39
TC = 25°C
Po =5W

I
10

VN02A

ON - Resistance Vs. Drain Current

BVDSS Variation with Temperature
1.1

5

V
./

4

/V

"0
w
N

/

::i

«
:;;
II:
0

1.0

6

'"'"0

/'

>

/'

/

j

)

2

50

°

150

100

TJ i"C)

..... 1.---'

-..,..,.....

I
2

°

3

2.0

1.25

I

I

IO~
'l .

I

4

t

TA = -55o

V

/ V

1/

~

"",~

1.00

~~

/V

~

'~

/.'//

...,,

V (th)

,

(oc -

// VI

'2

I......

I

25"C

j

3

"

~

°

~

2

6

8

o

-50

10

0

.......

0.8

r-....

r-....

50

8
150
(j)

~

~
S

100

Co)

50

~

~

C1SS

)'

V /270pF

6

..J

0

~

1\\"-

>'"
(!)

7

4

.I

Coss

~

2
CRSS
20

150

/0,-

Vos = 10V

10

~

//

I

f=IMHz

30

~

lCr

°°

40

Vos (volts)

8-28

0.6

V /
I

1/

~V

1.2

1.8

2.4

OG (NANOCOULOMBS)

0

~

100

10

Z

II:

Gate Drive Dynamic Characteristics

Capacitance vs. Drain-to-Source Voltage
200

w

N

II:

TJ (oC)

VGS (VOLTS)

"0

6

0.75
4

1.6

::i
«
1.2 :;;

~1'b=0.12A

ip
o

5

4

losJAMPERES)

V(th) and RDS Variation with Temperature

Transfer Characteristics

vbs =125VI

./

-:/

I---'"'

o

-50

15 11
V s= 10'1

I-"'

0.9

5

f-- I- JGs

3

V

"'

rr

3.0

0.4

°

VN02C

"

!iupertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs

Ordering Information
Order Number I Package

BVoss '
BVDGS

RDS{ON)

ID(ON)

(max)

(min)

TO·39

TO·92

TO·220

160V

60

1A

VN0216N2

VN0216N3

VN0216N5

200V

60

1A

VN0220N2

VN0220N3

VN0220N5

Features

Advanced DMOS Technology

D

Freedom from secondary breakdown

D

Low power drive requirement

D

Ease of paralleling

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

D

Low C 1SS and fast switching speeds

D

Excellent thermal stability

D

Integral Source-Drain diode

D

High input impedance and high gain

D

Complementary N- and P-Channel devices

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications
D

Motor control

D

Converters

D

Amplifiers

D

Switches

D

Power supply circuits

D

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

Package Options

i

Absolute Maximum Ratings

TO·92

~
TO·220

(Notes 1 and 2)

if
TO-39

Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature

Note 1: See Package Outline section for discrete pinouts.
Note 2: See Array section for quad pinouts.

Soldering Temperature'
"Distance of 1.6 mm from case for 10 seconds.

8-29

VN02C

Thermal Characteristics
Package

ID (continuous)"

ID (pulsed)",

Power Dissipation

91a

@Tc=25°C

°C/W,

~c

IDR

\'DAM"
2.5A

°C/W

TO-39

0.7A

2.5A

4W

125

32

0.7A

TO-92

0.4A

2.5A

lW

170

125

0.5A

2.5A

TO-220
1.5A
• 10 (continuous) IS limited by max rated Tr

2.5A

28W

70

4.6

1.7A

2.5A

Electrical Characteristics

(@ 25°C unless otherwise specified)

Symbol

Parameter
Drain-to-Source
Br~akdown Voltage

BVoss

Min
t

VN0216

160

t

VN0220

200
0,75

GateThreshold Voltage

VGS(lh)
tN GS(lh)

Typ

Gate Body Leakage

loss

Zero Gate Voltage Drain Current

Unit

Conditions

V

-4.6

Change in VGS(lh) with Temperature

IGSS

Max

3
-5.5

VGS = 0, 10 = 2.0mA

V
mV/OC

100

nA

25

!lA

2.5

mA

(Notes 1 and 2)

VGS = Vos ' 10 = 2.0mA
VGS = Vos ' 10 = 1.0mA
VGS = ± 20V, Vos = 0
VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Rating
TA = 125°C

ON-State Drain Current

10(ON)

1.3

1.0

2.2

Static Drain-to-Source
ON-State Resistance

ROS(ON)
IIROS(ON)
GFS
C1SS
Coss

0.5

Change in ROS(ON) with Temperature
Forward Transconductance

0.3

VGS = 5V, Vos = 25V

A

VGs= 10V, Vos=25V

5.0

8

4.0

6

0.8

1.4

%/oC

0.7

Input CapaCitance

75

150

Common Source Output Capacitance

34

85

15

35

CRSS

Reverse Transfer Capacitance

td(ON)
t,

Turn-ON Delay Time

10

Rise ~ime

10

td(OFF)

Turn-OFF Delay Time

20

~
Vso

Fall Time

t"

Reverse Recovery Time

VGS = 5V, 10 = 0.5A
VGS = 10V, 10 = 0.5A

Q

VGS = 10V, 10 = 500mA

U

Vos = 25V, 10 =lA

pF

VGS = 0, Vos = 25V
f= 1 MHz

ns

Voo = 25V
10 = 0.5A
Rs = 50Q

V

VGs=O,lso=lA

ns

VGs=O,lso=lA

20

Diode Forward Voltage Drop

1.2

1.8

430

Note t: All D,C, parameters 100% tested at 25°C unless otherwise stated, (Pulse test:
Note 2: All A,C, parameters sample tested.

300~s

pulse. 2% duty CYCle,)

Switching Waveforms and Test Circuit

I----PULSE---i
t(ON)

i

t(OFF)

GENERATOR

1
1

1

v-+4~--~~

1
Output

1
1
1

-----"'\I
10%

i'"

L. _ _ _ _ _ _ _ _ _ _1

8-30

I

f-~-OSCOPE

D.tH

VN02C

Typical Performance Curves
Saturation Characteristics

Output Characteristics

--

2.5

-

I

2.0

~ ....
f-~ ~ - 6V
I
~V
I
~V
VGS -10V

d6'

2.0

JGS1t¥k
b:::::= ~

1.6

1

(i;
w
II:

1.5

w
a..

:;

:!

E

1.0

I

0.5

o

I

~

......

(i;

w
w
a..

II:

5r

:!

I

E

~

1.2

:;

~ /'

0.8

~r

0.4

~~

I
3V

o

10

0

20
30
VDS (VOLTS)

3Y-

I?
o

50

40

4V-

l.t y

4V

V

~ ~ ~-

~ ~ "./

4
6
Vas (VOLTS)

2

8

10

Power Dissipation Vs. Case Temperatu re

Transconductance Vs. Drain Current
50

1.5
V9S = 125V
1.2
TA

40

~ ·55°C

(i;

z

w

0.9

w

§

...
f/)

~

25°C

:;

If
Ir

0.6

(!l

!o

lJ5°C

a..

IJ

0.3

30

20

o
0.4

0.8
1.2
10 (AMPERES)

1.6

2.0

'"

'"

o

25

50

75

100

"

~

125

150

TC (oC)

Maximum Rated Safe Operating Area

Thermal Response Characteristics
1.0

10

-

Td. ~io I(PU~SEti)
-+ 11=1- - -r-.

_ TO - 220 (DC)

'0

w

N

:::;

«

~,

:;

'"'"

O.B

II:

0
~

I,

TO-39 (OC)

0.01

"r-...

TO·39

0

0.1

I

10

'I
0

".II

TO-220

r - .........

w
u

I

0.6

I
I

z

....«

""

f/)

Cij

II

/

0.4

w

II:

VI'

.J

«
:;

'"

0.2
.,/

II:

w

J:
....

10
100
1000
VDS (VOLTS)
Pulsed Condition: 300lLs, 2% dutycycle

8-31

TO-220
II
I
I
TC = 25°C

IrD-r~

~

0
0.001

0.01

0.1
tp (SECONDS)

10

VN02C

ON - Resistance Vs. Drain Current

BVDSS Variation with Temperature
50
JI'

1.1

....V

C

/'

w
N

0
~

VGS =5V

Cii
::;;

/

::J

«
::;;
a:

40

V

1.0

V

(J)
(J)

J:

2
Z

/

0

en

c
a:

,/

C

>
CO

V

30

20
VGS = 10V L

-

10

0.9

o

o

-50

50
TJ (oC)

100

150

VOS = 25V
lA--SSoC.

2.0

Cii

w
w
0::;;

1.5

5
9

1.0

a:

0.5

o

~
o

I

/I

~(th)

C
N

1 5°C

::J
«
::;;

a:

0

1.00

V

~

V

~

"../

en

'" '"

"

>

6

8

0.75 I
-50

10

~
u

l~

rl

CISS

~ i'....

o

10

K

>

" '"
100

0.5 ~

a:

"

150

1/iJOV 115 pF
1/1/

/ ./

4

-

2

30

zo

I

vos=~ov/

6

./ '/

~V

/75pF

o 1/

40

o

Vos (VOLTS)

0.5

1.0

1.5

2.0

OG (NANOCOULOMBS)

8-32

15

~

/

COSS-

~

1.0

77

o

~
~

20

1

50

-J

CRSS

o

"

8

40

«
::;;

./

Gate Drive Dynamic Characteristics

120

U

C

1.5 ~
::J

10

f = lMHz

0

V

V

TJ ("C)

Capacitance Vs. Drain-to-Source Voltage

80

/

o

VGS (VOLTS)

~
«
a:
«
LL

2.5

2.0

1

160

2.11

10 = 500mA7

w

4

2

1.0
1.5
lOS AMpERES

1.25

,'~5od f
I
f
I I

I.

1/
lUI

0.5

/'

V(th) and RDS Variation with Temperature

Transfer Characteristics
2.5

o

l..I 1..----- . /

2,5

o

VN03D

"!iupertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVossl
BV OGS

Order Number I Package

ROSION)

'DiaN)

(max)

(min)

3S0V

2.S0

3A

VN033SN1

400V

2.S0

3A

VN0340N1

TO-3

TO-39

TO-220

Dice

VN033SN2

VN033SNS

VN033SND

VN0340N2

VN0340NS

VN0340ND

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Package Options

Applications
o
o
o
o
o
o

(Note 1)

Motor control
Converters
Amplifiers
Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)
TO·39

TO·220

Absolute Maximum Ratings
Drain-to-Source Voltage

BVDSS

Drain-to-Gate Voltage

BV DGS

Gate-to-Source Voltage

± 20V

TO'3

Operating and Storage Temperature
Note 1: See Package Outline section for discrete pinouts.

Soldering Temperature>
"Distance of 1.6 mm from case for 10 seconds.

8-33

..
I

VN03D

Thermal Characteristics
Package

10 (continuous)"

10 (pulsed)'

Power Dissipation

6,e

6'8

°CIW

@Tc=25°C

,

lOR

lOAM

°CIW

TO-3

3.5A

8A

100W

30

1.25

3.5

.8A

TO-39

1.0A

7A

6W

125

20.8

1.0

7A

50W

40

2.5

2.1

8A

TO-220

2.1A

8A

*'0 (continuous) is limited by max rated Tj'

Electrical Characteristics
Parameter

Symbol
BVoss

(@ 25°C unless otherwise specified)
Min

I VN0340

Drain-to-Source
Breakdown Voltage

I

VN0335

VGS(th)

Gate Threshold Voltage

!,vGS(th)

Change in VGS(lh) with Temperature

IGSS

Gate Body Leakage

loss

Zero Gate Voltage Drain Current

Typ

Max

Unit

400

Conditions

V

350
2

4
-4.8

(Notes 1 and 2)

VGS = 0, 10 = 10mA

V
mV/oC

VGS = Vos ' 10 = 10mA
VGS = Vos ' 10 = 10mA

100

nA

VGS = ± 20V, Vos = 0

100

!1A
mA

VGS = 0, Vos = 0.8 Max Rating

-6

2

VGS = 0, Vos = Max Rating
TA = 125°C

10(ON)

ON-State Drain Current

4.5

ROS(ON)

Static Drain-te-Source
ON-State Resistance

2.2

lI.ROS(ON)

Change in ROS(ON) with Temperature

GFS
C1SS

Input Capacitance

Coss
CASS
tdON
tr

Forward Transconductance

1

1.8

2.5

1

2
650

Common Source Output Capacitance

75

125

Reverse Transfer Capacitance

25

50

Turn-ON Delay Time

12

20

Rise Time

12

20

t.
::;:

5
9

4

~
~~

5V

~

5
9
4V

10

20

30

40

..;'

~;;..;

::;:

~

2.0

~~

1.0

3V

o

VGS-l0V
3.0

<>.

V

,

2

0

~

~~

u;
w
a:
w

6V

........ ../~

6

3V.

o

4

2

2

w
w

TO-3

~

'\

80

/

§

/

en

~

2JC

60

I-

~
0

u.

<>.

'\

""'" ~ ~ '\.'\

40

125°C
20

I

I'\.

TO-22O

(,!)

0.5

0

2

0

3

5

4

o

25

50

10 (AMPERES)

- -

-- '~~~
~~~
~~~~ ~ t=

cw

~"JXo.

Q

w
<>.

U'r;

:::;

150

1.0

0.8

a:

~~,

0
~

w

0.6

u

2

«

::;:

I-

5

9

~

125

N

«
::;:

r-

u;
w
a:

75
100
TC (oC)

l"\.

Therma( Response Characteristics

Maximum Rated Safe Operating Area
10

""

TO-39

0

-

.'\.

'\

TA = -55°C

::;:

10

8

Power Dissipation Vs. Case Temperature
100

VOS =25V

1.5

6

VOS (VOLTS)

Transconductance Vs. Drain Current

en2

-4V

~".

VOS (VOLTS)

2.5

~~

~

o

50

-

:;;-'

5Y-

.1

LIMITE
8Y BVOSf

.01
10

en

"

100

u;

0.4

w

a:

...J

«

::;:
a:
w

0.2

J:

I-

0.01

1000

0.1
tp (SECONOS)

VOS (VOLTS)
Pulse Condition: 300l's. 2% dutycycle.

8-35

10

.

VN03D

ON . Resistance Vs. Drain Current

BVDSS Variation with Temperature
20
./

1.1
./

13

VGS=5V
(j)

::;:

/

:::;

OJ

/'

J:

/"

12

Q

Z
0

El

/'

8

4

0.9
50

6

S
9

4

100

o

150

Vos =25V

;I

TA = -55°C

2

I I

J

,25°C

/

w

N

1.2

:::;

~(th)

-...... :---...



V

...-

1.0

~

--

/

V

............ I--....

0.8

6

8

10

o

-50

150

Gate Drive Dynamic Characteristics

Vos =

"J"V

/ jcfV

//

V) 160( pF

,\

Ciss

6V

1/17
JV

500

0

U

4V

~

\

~

2V

10

20

30

-~

Vj
~

loPF

COSS
CRSS-"';;

0
0

r---...

100

50

8V

250

r---..... r-.....

10V

750

u

1.0

TJ (oC)

f = lMHz

o

40

o

4

8

12

QG (NANOCOULOMBS)

VOS (VOLTS)

8-36

1.9

;/

0.6

4

2

17

13

Capacitance Vs. Drain-to-Source Voltage

0::

10

110 =1

/

II 1/
'I /

1000


"'

V

8

V

.".

en::!!
J:

V

.....

2
Z
0

~

~/

)

--

4

I - ........

2

i,.....-- V

o

50

o

150

100

2

4

,

VpS = 25V

/

8

TA =·55'C,

:;;
4

I

E

V '/

2

o

,
,

aw
N

::!!
cr
0
~

r/

£

4

0.8

(jj
C1

>

/~

2

6

8

r-.....

::i

J,U
o

1.1

J.

1'0 = .51A V

~

V(th)

........

r-.... 1,/
V ............. t-...

«

V I? Jl
/ 1/ 125'C

W

Q.

5

1.2

12s1c-J I--

6

~

~

0.4
-50

10

~
«
cr
«
LL

r--....

......

z
Z

r--......

0

0.5

100

150

'/

A ~I"'"

250
2

1\

COSS
CRSS
30

40V

VI
/ V 600Pf
1//
1.1.1/

~

20

0

/

500

10

cr

50

8

0

o

::!!

VOS-l0V'Y

CISS

o

::i

«

Gate Drive Dynamic Characteristics

U

u

N

o

o

10

f = lMHz

~

C

w

ID-IA

TJ ('C)

Capacitance Vs. Drain-to-Source Voltage
1000

1.5

~

0.6

VGS (VOLTS)

750

10

8

V(th) and RDS Variation with Temperature

Transfer Characteristics
10

6

los (AMPERES)

TJ ('C)

cr

'/

o

0.8
-50

enw

tGSI~ 10~.-

6

cr

0.9

II

II

V~S~5V

o
40

~5fOpfl
o

2

4

6

8

OG (NANOCOULOMBS)

Vos (VOLTS)

8-40

10

'§
a:

VN03F

(J) §upertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVDSS I

RDS(ON)

ID(ON)

BVDGS

(max)

(min)

To-3

TO-220

Dice

550V

60

1.5A

VN0335N1

VN0335N5

VN0335ND

600V

60

1.5A

VN0360N1

VN0360N5

VN0360ND

Order Number I Package

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C ISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Note 1)

Motor control
Converters
Amplifiers
Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO·3
TQ-220

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature'

±20V
-55·C to +150·C
Note 1:

300·C

'Distance of 1.6 mm from case for 10 seconds.

8-41

See Package Outline section for discrete pinouts.

..

VN03F

Thermal Characteristics
..
.

'

.

,','"

Package

,

10 (llontlnuous)*

10 (pulsed)~

8 je

'8,a ,

@T=25°C
c"

.oCfW

ocm.

Power Ois.sipation

"

-~.

lOR

IDRM

TO-3

2.5A

6A

100W

1.25

30

2.5A

6A

TO-220

1.5A

6A

50W

40

40

1.5A

6A

*ID (continuous) is limited by max rated Tj'

Electrical Characteristics
Symbol
BVDSS

(@ 25°C unless otherwise specified)

Parameter
Drain·to·Source
Breakdown Voltage

Typ

Min
VN0360
VN0355

VGS(th)

Gate Threshold Voltage

LWGS(th)

Change in VGS(th) with Temperature

IGSS

Gate Body Leakage

lOSS

Zero Gate Voltage Drain Current

Max

2
-4.8

V

VGS= 0,10 = lOrnA

4

V

VGS = VDS, 10 = lOrnA

-6.0

mVtC
nA

100
100

ON·State Drain Current

1.3

Static Drain·to·Source
ON·State Resistance

b.ROS(ON)

Change in RDS(ON) with Temperature

GFS

Forward Transconductance

CISS

Input Capacitance

COSS

Common Source Output Capacitance

CRSS
td(ON)

Reverse Transfer Capacitance

/J-A
rnA
A

3.0

1.5
RDS(ON)

Conditions

600
550

2
ID(ON)

Unit

(Notes 1 and 2)

0.5

VGS = 0, VDS = 0.8 Max Rating
TA = 125°C
VGS = 5V, VOS = 25V
VGS = 10V, VOS = 25V
VGS = 5V, 10 = 0.25A

5.5
4.5

6.0

n

1

2

%tc

VGS = 10V, 10 = O.SA

U

VOS = 2SV, 10 = O.SA

pF

VGS = 0, VOS = 25V
f = lMHz

ns

VOO = 25V
10 = O.SA
RS = 50n

1
550

125

Turn·ON Delay Time

8

15

tr

Rise Time

8

15

td(OFF)
tf

Turn·OFF Delay Time

65

100

Fall Time

VSD
trr

Diode Forward Voltage Drop

12
1.1

1.5

Reverse Recovery Time

450
300~s

VGS = 10V, 10 = 0.5A

650

75
25

Note 1: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pul.e test:
Note 2: All A.C. parameters sample tested.

VGS = VDS, 10 = lOrnA
VGS - ±20V, VDS = a
VGS - 0, VDS - Max Rating

50

25
V
ns

VGS = 0, ISO - 5A
VGS - 0, ISD = SA

pul.e, 2% duty cycle.)

Switching Waveforms and Test Circuit

INPUT

I---'u..--OSCOPE
D.U.T.
OUTPUT

8-42

VN03F

Typical Performance Curves
Output Characteristics

Saturation Characteristics
1.0

~

IL

f'

a.
E

5V

~

0.4

.9
0.2
4V

10

20

30

40

/

'/

1\.

TO-3

0.8

'\..

80

\.
'\..

TA - -55°C

ff

0.4

i.!

TA = 25°C

.Ill
,!!l.

c

C!l

II.

TA _150°C
0.2

60

40

-TO-2~

20

a

2

3

a

5

4

50

25

'\..

75

Tc(OC)

Maximum Rated Safe Operating Area

'\..
'\

""

100

'\..

~

125

150

Thermal Response Characteristics

10

1.0

r-- TO-3

(~C)

1.0 f-- TO-220

(~C)

~

"

E
0

w

~

"

~

iii

U
Z

~
CiS

~

I"

0.1

/
V

W

,r

0.4

~

:::E

a:
w

J:
I0.01
100

0.6

a:

<

10

0.8

.s

!

8.

I

i.1::1

~

t-- TO-220 (pulsed)

.9

~

""""

10 (amperes)

.,

4

Power Dissipation vs. Case Temperature
100

'. ' =25V
.L
f--VOS

0.6

3

VOS (volts)

Transconductance VS. Drain Current

c:
II)
E

3V

2

50

VOS (volts)

1.0

.,

,"
i""'"

"

"

a

,~

0.6

!II)

J~

I

.,

6V

~ P"'"

~

0.8

7Vlo 10V

~ II""""

10V

1000

0.2

/
0.001

/
./
TO-3
Po = 100W
Tc = 25°C -

/

I

0.Q1

0.1

tp (milliseconds)

VOS (volts)

8-43

/

10

VN03F

BVoss Variation with Temperature

On-Resistance vs. Drain Current

1.1

10

/

II

I VGS =10V

VGS =SV

8

!/

E

.c

/

6

~

Cl

./ l/

---

.2Z

V

V

V

/

'ii)

/

V

J

/

..,

V

4

i-"""

II:

/

"

0.9

o

-50

100

2

1S0

3

4

S

10 (amperes)
Transfer Characteristics'
5

/f1l0~
l!r
•~'l

Vos =2SV
4

V(th) and Ros Variation with Temperature
1.2

1.1

~~~(
C
"1

/--:«

3

i/ J
'1/ V

2

1

.!::!

ca

V(th) .....
1.0

........

§

0

.s
~

1//

0.9

/

,
~

>'"

Cl

LVI

O.B

2.0

'0
Q)

/10 =O.SA

N

1.5

~' /

V

0

.........

......

.....

1.0

,

6

8

O.S

o
-so

10

100

1S0

VGS (volts)
Capacitance vs. Drain-to-Source Voltage

Gate Drive Dynamic Characteristics

BOO

10

f= 1MHz
600
'ii)

~

i

400

()

200

B

\

"

\

C1ss

6

A'"

A

"'20

~

740 pF

r

toss

/SOO pF

I

CRSS
10

~

~

~Vos =40V

4

"o

vos = 10V

30

o

40

246

QG (nanocoulombs)

Vos (volts)

8-44

~

&

0.7

4

'ffi
§

.s

..........

'.'

.J'
2

,/

....... ......

'0
Q)

2.S

/

10

a"-'-' §upertex inc.

VN0300

N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BV DSS I
BVoos
30V

Order Number I Package

ROS(ON)

IO(ON)

(max)

(min)

TO-39

I

TO-92

I

TO-220

1.20

2.0A

VN0300B

I

VN0300L

I

VN0300D

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C 1SS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Note 1)

Motor control
Converters
Amplifiers

i

Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO-39

TO-92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±40V

TO-220

Operating and Storage Temperature
Soldering Temperature"

Note 1: See Package Outline section for discrete pinouts.

"'Distance of 1.6 mm from case for 10 seconds.

8-45

VN0300

Thermal Characteristics
Packaga

.

10 (continuous)"

10 (pulsed)

8j.

Power Dissipation

TO-39

1.2A

3A

6.25W

TO-92

.4A

3A

.4W

TO-220

2.11A

6A

20W

8)"

°crw

°crw

170

20

312.5

43.5
6.25

80

'0 (continuous) IS limited by max rated Tj'

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

BVOSS

Orain-to-Source
Breakdown Voltage

VGS(th)

Gate Threshold Voltage

IGSS

Gate Body Leakage

lOSS

Zero Gate Voltage Orain Current

Min

Max

Typ

30
.8

Unit

Conditions
10

2.S

V

VGS

100

nA

VGS

10
fLA

TA

ROS(ON)

Static Orain-to-Source
ON-State Resistance

2

VGS

0

1.2
Forward Transoonductance

CISS

Input Capacitance

200

COSS

Common Source Output Capacitance

95

CRSS

Reverse Transfer Capacitance

2S

t(ON)

Turn-ON Time

30

t(OFF)

Turn-OFF Time

30

VSO

Oiode Forward Voltage Orop

= 12S'C

VGS

3.3

GFS

=0

= .10V, VOS '" 2 VOS (ON)
= SV, 10 = .3A
VGS = 10V, 10 = lA
VOS '" 2 VOS(ON), 10 = O.SA

A
~

VGS

= VOS, 10 = lmA
= ±30V, VOS = 0
VGS = OV, VOS = Max Rating
VGS = OV, VOS = Max Rating

SOO
ON-State Orain Current

= lOfLA,

V

r--

10(ON)

(Notes 1 and 2)

mU
100

= 0, VOS = ISV
= lMHz
VOO = 2SV, 10 = 1.0
RS = son
ISO = 0.63A VGS = 0

pF

VGS
f

ns

-0.9

Note 1: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse tes\:
Note 2: All A.C. parameters sample tested.

300~s

V

pulse. 2% duty cycle.)

Switching Waveforms and Test Circuit

r-;;L-;--'

INPUT

I
I
I
I

OUTPUT

GENERATOR

,

~,~~~~

I

I

IL _____ JI

8-46

1-~-_oSCOPE

D.U.T.

~

VN05D

'tlI §upertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss I
BVDGS

Order Number I Package

ROS(ON)

IO(ON)

(max)

(min)

TO-39

T0092

Diea

350V

35Q

250mA

VN0535N2

VN0535N3

VN0535ND

400V

35Q

250mA

VN0540N2

VN0540N3

VN0540ND

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C1SS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Note 1)

Motor control
Converters
Amplifiers
Switches
Power supply circuits

i

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO-92

i

TO·39

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Note 1:

Soldering Temperature'
*Oistance of 1.6 mm from case for 10 seconds.

8-47

See Package Outline section for discrete pinouts.

..

VN05D

Thermal' Characteristics
Package

ID (continuous)"

10 (pulsed)"

, Power Dissipation
, @Tc

"Oj8 "

"em'

=25"C

°je,

,IORIII

IDR

,',oefW'

"

,

TO-39

250m A

500mA

6.0W

125

20.8

250mA

500mA

TO-92

100mA

400mA

1.0W

1'70

125

100mA

400mA

• ID (continuous) is limited by max rated Tj'

Electrical Characteristics
Symbol
BVDSS

VGS(th)
LWGS(th)
IGSS
IDSS

ID(ON)

(@ 25°C unless otherwise specified)

Parameter
Drain-to-Source
Breakdown Voltage

Min
VN0540
VN0535

Gate Threshold Voltage
Change in VGS(th) with Temperature
Gate Body Leakage
Zero Gate Voltage Drain Current

2.0
-3.5

t.RDS(ON)
GFS
CISS
Coss
CRSS
td(ON)
tr
td(OFF)
tf
VSD
trr
Note 1:
Note 2:

V

ID; lmA, VGS; 0

V

VGS; VDS, ID; lmA

4.0
-4.5
100
10

mVtC
nA

500

p.A

200
300

rnA

30
25
0.9
100

Conditions

Unit

I---

ON-State Drain Current
Static Drain-to-Source
ON·State Resistance
Change in RDS(ON) with Temperature
Forward Transconductance
Input Capacitance
Common Source Output Capacitance
Reverse Transfer Capacitance
Turn-ON Delay Time
Rise Time
Turn-OFF Delay Time
Fall Time
Diode Forward Voltage Drop
Reverse Recovery Time

Max

400
350

250
RDS(ON)

Typ

35
1.5

200
45
8
2
3
3

n
%tc

ID - O.lA

= 25V,

VGS = 0, VDS
f = lMHz

ns

VDD = 25V, ID
RS

= SOmA,

= son

ISD - 0.5A, VGS

V
ns

400

= 25V,

pF

5
5
5
5
5

VGS - ±20V, VDS - 0
VGS - 0, VDS - Max Rating
VGS ; 0, VDS ; 0.8 Max Rating
TA = 125°C
VGS; 5V, VDS; 25V
VGS; 10V, VDS = 25V
VGS - 5V, ID - 20m A
,VGS; 10V, ID = O.lA
ID = OilA, VGS = 10V
VDS

mU
55
10

3
3
0.8

(Notes 1 and 2)

0

ISO - 0.5A, VGS - 0

All D,C, parameters 100% tested at 25°C unless otherwise stated, (Pulse test: 300jlS pulse, 2% duty cycle,)
All A,C, parameters sample tested,

Switching Waveforms and Test Circuit

INPUT

OUTPUT

r -

I
I
I

I

;;:;L~

--,

GENERATOR

I

~1~r-~r4

I

I

IL _____ J,
8-48

~~-OSCOPE

D.U.T.

VN05D

Typical Performance Curves
Saturation Characteristics

Output Characteristics
0.25

0.5

VGS

0.4

t:::

V
Cii
w
II:
w
Il.

,

0.2

A

0.1

o

I

Cii
w
a:

J=

~V

fi. /

~~

0.15

w

Il.

::;

:!

~

9

~

0.10

V

0.05

I
31-

0

o

VGS = 10V

0.20

5Y-

l/ "/

0.3

::;

:!
9

=JJ'!-

10

20

30

40

50

L

/"

o

4

10

0.32

8
TA =·55°C

::;

'"u.

~ ......

(!l

0.08

0

4

I
125°C

!;' . / ~

~

r-.....

TO·92

0.08

0.12

0.16

0.20

.......

.::--...

o
0.04

0

25

50

75
100
TC (oC)

125

150

Thermal Response Characteristics

Maximum Rated Safe Operating Area
1.00

1.0

0:
w

TO·39 (PULSED)

I

I I

N

I"

TO·39 (DC)

:;

"',

"

0.10

«
::;

1",

~

w

LIMITED
BY BVDSS

0.01

0.6

()

z

~

Il.

0.8

II:
0

I

f",.

::;

:!
9

......

.........

10 (AMPERES)

Cii
w
II:
w

.........

2

/V
If'
o

'"

I

°
25 C

V .--

0.16

10

8

TO·39

6

fo"'""
......- ~

w

§

6

Power Dissipation Vs. Case Temperature

0.40

0.24

3V

VDS (VOLTS)

Transconductance Vs. Drain Current

zw

~~

'"

2

VDS (VOLTS)

Cii

~ "'54VV

:;..--

«
t-

'"(jjw

-

004

II:
..J

«
::;

0.2

II:
W

J:

t-

.001
10

100

1000

O
.001

.01

.1
tp (SECONDS)

VDS (VOLTS)
Pulse Condition: 300J.Ls, 2% dutycvcle.

8·49

10

VN05D

ON-Resistance Vs. Drain Current

BVDSS Variation with Temperature
100

V

C
w

N

«
:E

a:

80

en

,/

~

I

:!E

:I:

V

/

1.0

~

/

Vi

./"

:J
0

./
Q

60

V

Z

/'

/ 1/

0

in
0
a:

>

'"

40

..

VGS =5vll

1.1

-

20 -

,::;...

/

vGS = 10V

/

J

if

I

V

/

-.

r--.

0.9

0

o

-50

50

+fA

1.4

I
25°C

w
N

0.5

0.1

~

cc

0
~

P
I
'I

~
in

1.0

.,..,.,

".. V

0.8

CI

>

cw
1.4

./

- --

./

CC

r-

~

~

6

8

10

o

-50

50
TJ (oC)

100

150

10
vos~;O

105pF /

8

75

~
«
a:
«
u.

50

25

2

-

\OSS
0

CRSS

o

10

o
20

30

40

VDS (VOLTS)

112pF

/ V

1//

4

\

~
u

V/

~CISS

0

U

-

I

~I;:

i/V

/
o

0.2

0.4

0.6

0.8

QG (NANOCOULOMBS)

8-50

40

/ /

6

~

CC

Gate Drive Dynamic Characteristics

Capacitance Vs. Drain-to-Source Voltage
100

z0

0.6

0.2

VGS (VOLTS)

N

:J
«
:E

1.0 0

0.6

4

2

r-. r-

:E

125°C

if

0.2

V(th)

«

~

102

V

/

1.2

:J

,,!.. r--

w
:E
Il.

ID = 250m~

C

J

0.3

R~S(O~)

If

/,/. ~

o

0.4

V(th) and RDS Variation with Temperature

I:

0

0.3

Transfer Characteristics

TA =-55°C

5
9

0.2

0.1

lOS (AMPERES)

0.4

a:

o

150

TJ (oC)

0.5

Vi
w

100

1.0

VN05E

"§upertex inc.
I

N-Channel Enhancement-Mode
Vertical CMOS Power FETs
Ordering Information
Order Number I Package

BVoss I
BVOGS

ROS(ON)
(max)

IO(ON)
(min)

TO-39

TO-92

Dice

450V

600

150mA

VN0545N2

VN0545N3

VN0545ND

500V

600

150mA

VN0550N2

VN0550N3

VN0550ND

Features

Advanced CMOS Technology

o
o
o
o

Freedom from secondary breakdown

o

Excellent thermal stability

o
o
o

Integral Source-Drain diode

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o

Package Options

(Notes 1 and 2)

Motor control
Converters

o
o

Amplifiers

o
o

Power supply circuits

Switches
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO·39

Absolute Maximum Ratings

TO·92

Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature

Note 1:
Note 2:

Soldering Temperature"
*Distance of 1.6 mm from case for 10 seconds.

8-51

See Package Outline section for discrete pinouts.
See Array section for quad pinouts.

..

VNG5E

Thermal Characteristics
"

Package

10 (cOntinuous)~

,

,"

It;> (p!:,lsed)'

Power Dissipation
@Tc =25°C '

9jc

°CIW

9 11
°C/W

'DR

.

'DR\I

TO·39

100mA

300mA

6W

20

125

100mA

300m A

TO·92

50mA

250mA

lW

125

170

50mA

250mA

*ID (continuous) is limited by max rated Tj'

Electrical Characteristics
Symbol
BVDSS

VGS(th)
6VGS(th)
IGSS
lOSS

(@ 25°C unless otherwise specified)
Min

Parameter
Orain-to-Source
Breakdown Voltage

VN0550
VN0545

Gate Threshold Voltage
Change in VGS(th) with Temperature
Gate Body Leakage
Zero Gate Voltage Orain Current

Typ

Max

Unit

500
450

2
-3.8

4
-5
100
10

r--

ON-State Orain Current
150

ROS(ON)
6 ROS(ON)
GFS
CISS
COSS
CRSS
td(ON)
tr
td(OFF)
tf

VSO
trr
Note 1:
Note 2:

Static Orain-to-Source
ON-State Resistance
Change in ROS(ON) with Temperature
Forward Transconductance
Input Capacitance
Common Source Output Capacitance
Reverse Transfer Capacitance
Turn-ON Oelay Time
Rise Time
Turn-OFF Oelay Time
Fall Time
Oiode Forward Voltage Orop
Reverse Recovery Time

50

100
200

V

VGS = 0,10 = lmA

V

VGS = VDS, 10 = lmA

/LA

60

n

1

1.7

%tc

2
3
3
3
3
0.8
300

5
5
5

=
=
=

5V. VOS = 25V
10V. VOS = 25V
5V, 10 - 50mA
10V, 10 =50mA

VGS = 10V, 10 = 50mA
VOS = 25V, 10 = SOmA

mU
55
10

VGS = VOS, 10 = lmA
VGS - ±20V, VOS - 0
VGS - O. VOS - Max Rating
VGS = 0, VOS = 0.8 Max Rating
TA = 125'C
VGS
VGS
VGS
VGS

mA

50
45
75
45
8

Conditions

mVtC
nA

1000
10(ON)

(Notes 1 and 2)

VGS = 0, VOS = 25V

pF

f = 1 MHz
VOO = 25V
ns

10 = 50mA

5

RS = 50n

5
V
ns

VGS - O. ISO - 0.5A
VGS - 0, ISO - 0.5A

All D,C, parameters 100% tested at 25'C unless otherwise stated, (Pulse test: 300~s pulse, 2% duty cycle.)
All A,C, parameters sample tested,

Switching Waveforms and Test Circuit

r -;;:;:s; --,

INPUT
tION)

I

tdlON) tr
OUTPUT

tdIOFF) tf

I

I

10%

GENERATOR

I

\~I~+---~

I

:
I
I
I
L _____ J -=
8·52

1-~-_oSCOPE

D.U.T,

VN06D

"§upertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
Order Number' Package

BVDSS '

RDS(ON)

IOlON)

BV DGS

(max)

(min)

T0-39

350V

10n

0.75A

VN0635N2

VN0635N3

VN0635N5

VN0635ND

400V

10n

0.75A

VN0640N2

VN0640N3

VN0640N5

VN0640ND

T0-92

T0-220

Dice

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capaCitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Package Options

Applications
o
o
o
o
o
o

(Note 1)

Motor control
Converters

i

Amplifiers
Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO-39

TO-92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

TO-220

±20V

Operating and Storage Temperature
Note 1: See Package Outline section for discrete pinouts.

Soldering Temperature"
"Distance of 1.6 mm from case for 10 seconds.

8-53

•

Thermal. C~,aracteristi~s

VN060

'.'i"

,',

Package

I~Jc;ontlnuous)'

',:,"

ID(pUlsed)'c"

III

/

Ii)

V

~ --'

./

"

o
-50

100

150

0.2

0.6

1.0

1.4

1.8

10 (amperes)
Transfer Characteristics

V(th) and Ros Variation with Temperature
1.4

2.5

2.5

/

Vos =25V

10 =500mA./
1.2

2.0

Ii)

2!

CIl

E

~

.~

~

-S

'>

0-

E

fJ,/ ~
00

1.5

1.0

ca

k!::: ~ i"""'"
o

/'

Z

<::-

~

0.8

L.........

/

'0
CIl
N

.........

........

",.

r--.....

rn

.........

0.6

0.5

-50

10

0
150

100

Capacitance vs. Drain-to-Source Voltage

Gate Drive Dynamic Characteristics
10

200 , - - - - - - , - - - , - - - - - , - - - - - - ,

VOS =lOV

f=lMHz

Ii)

~

C 1SS

6

.1

0

~

100

I If

rn

S"

(!)

>

0

4

I

2

30

o

40

l80pF

0.5

1.0

1.5

QG (nanocoulombs)

8-56

-

I--

I

1/
20

I

lOOpF

J

COSS

VOS (volts)

I

.J.../

50

10

,

/ I
I / VOS =40V

150

0

1.0

-S
Z

~

r:P

VGS (volts)

~

'fii

~

'I

6

1.5

E
0

0.4

4

2

.......... ........

E

~ ~~,,~

A ~ i..,..oo"

1.0

0

/"-h ",\)O~

0.5

2.0

.........

'0
CIl

V(th)

2.0

2.5

VN06E

"!iupertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss I
BVOGS

Order Number I Package

ROS(ON)

10(ON)

(max)

(min)

T0-39

T0-92

T0-220

Dice

450V

160

O.5A

VN0645N2

VN0645N3

VN0645N5

VN0645ND

500V

160

O.5A

VN0650N2

VN0650N3

VN0650N5

VN0650ND

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C ,SS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Note 1)

Motor control
Converters
Amplifiers
Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO-39

TO-92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature"

TO-220

±20V
-55°C to + 150°C
Note t:

300°C

""Distance of 1.6 mm from case for 10 seconds.

8-57

See Package Outline section for discrete pinouts.

VNOse

Thermal CharacterisUos
Package

10

(continuous)·

: "10

(pulsed)·
'.

~

Power Dissipation
@Tc=2S?C""

~c

9)8

"C/W

°CIW

.

lOR

10RM

TO-92

:'" "O.2A

1.M

lW /",,:,~~, 125

170

0.2A

1.0A

TO-39

O.4A

1.5A

6W

21

125

0.4A

1.5A

TO-220

1.0A

1.5A

28W"

2.7

70

1.0A

1.5A

*10 (continuous) is limited by max rated Tj'

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

Min

I VN0645

Typ

Max

Unit

450

V

(Notes 1 and 2)
Conditions
VGS = 0, 10 = 2mA

BVoss

Drain-to-Source
Breakdown Voltage

VGS(lh)

Gate Threshold Voltage

tNGS(lh)

Change in VGS(th) with Temperature

-4.5

IGSS

Gate Body Leakage

100

nA

VGS= ±20V, Vos=O

loss

Zero Gate Voltage Drain Current

10

j.lA

VGS = 0, Vos = Max Rating

1

mA

VGS = 0, Vos = 0.8 Max Rating
TA = 125°C

I VN0650

500
2

ON-State Drain Current

10(ON)

V
mV/oC

0.7
0.5

Static Drain-to-Source
ON-State Resistance

ROS(ON)

4

A

VGS = 5V, Vos = 25V
VGs= 10V, Vos=25V

n

VGS = 5V, 10 = 100mA
VGS = 'lOV, 10 = 400mA

%IOC

VGS = 10V, 10 = 400mA

mU

Vos = 25V, 10 = 400mA

pF

VGS = 0, Vos = 25V
f= 1 MHz

ns

Voo= 25V
10 = O.4A
Rs = 50n

1.1
15
13

16
0.75

AROS(ON)
GFS

Change in ROS(ON) with Temperature

C1SS

Input Capacitance

85

130

Coss
CRSS

Common Source Output Capacitance

50

75

Reverse Transfer Capacitance

10

20

td(OIll)
t,

Turn-ON Delay Time

10

Rise Time

10

td(OFF)

Turn-OFF Delay Time

20

~
Vso

Fall Time

10

Diode Forward Voltage Drop

1.8

t"

Reverse Recovery Time

Forward Transconductance

100

VGS = Vos' 10 = 2mA
VGS = Vos' 10 = 2mA

300

V
ns

VGS = 0, Iso = 0.4A
VGS = 0, Iso = 0.4A

Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300118 pulse. 2% duty cycle.)
Note 2: All A.C, parameters sample tested,

Switching Waveforms and Test Circuit

I-~-OSCOPE

t(OFF)

D.U,T.
td(ON)
Output

------.I
to%

8-58

VN06E

Typical Performance Curves
Output Characteristics

Saturation Characteristics

2.0

1.0

..,..

6V to 10V

i""'"

(jj'
~

1.0

Q)

~

Co

,..../'"

,..

20
VOS

30

Transconductance

VS.

(jj'

0.18

/V
'1/
!J V
1'1

~
~ 0.12

(!)

0.06

4

2

10

6

Power Dissipation vs. Case Temperature
50

-

40

- , ......

--,

TO-220

I I 1_
TA = 150°C

10

......

........ ....

"

TO-39
TO-92

1.0

2.0

25

50

75

100

"

~

125

150

Tc (0C)

10 (amperes)

Thermal Response Characteristics

Maximum Rated Safe Operating Area
10

t.O

'0
Q)

I(jj'
~

1.0

~

E
.!!!.

'"

TO·39 (OC)
0.1

E
0

-_,<=>o

..

UJ

(,)

~

Z

0.01
10

iii
UJ

"'... ~

:\..

100

0.4

II:

~-

'" '"

0.6

~
en

II
i9~,,>1'\1

'>-0\l ."

'" :\..

0.8

oS

~-

,~i

I I I

Co

.J::!
1ii

'>-O~-r;-

TO-220 (OC)

Q)

.9

-- -~

4V

Vos (volts)

JX

"

--

~~

3V

50

t =1-55O~t =125O~-

L
I(

~

Ir

Drain Current

Vos =25V
0.24

40

,

6V to 10V
5V

l/

/

(volts)

0.3

Q)

~~

3V
10

E
Q)

.!!!.
.9

4V

I

c:

0.5

E

5V

10""

o

IL

~

...J



!Xl

V"

V

./

24

Ul
E
..c:
.f!.

I""'"

18

Z

V

~
c

VGS = 10V

VGS = 5V

.-- -'"

12

~

ex:

-

.-- ~

0.9

o

-50

50

o

150

100

0.3

0.6

Transfer Characteristics

/

Vos = 25V
oU

1.6

~

/t

/t

V-W~~

E
0
.s

J/
/, )'

V(th)

1.0

1:

,
V.

<::.

en

~

~ 'I'

./

1.2

.t:!
iii

~,

0.8

"" roo..... ........ i"'"
/
.,~

~

'"

'0
Ql

/

1.2

r-....

........

r-....

0.8

--

4

6

100

150

VGs (volts)
Capacitance vs. Drain-to-Source Voltage

Gate Drive Dynamic Characteristics

200

10

II

Vos = 10V
8

150

Ul

CISS

i'

l

100

:e,

en

~

U

4

'r'
2

Coss

I
10

20

30

40

-

I

L
IJ ~79P~
)

~

50

0

/. V

J r/
VI
V _~os =40V-

f=lMHz

~
~0

0.4

o

o

-50

10

,.,

110 pF

0.5

1.0

1.5

QG (nanocoulombs)

Vos (volts)

8-60

2.0

2.5

.t:!
iii

E
0
.s

~

r£

0.6

t!!t. ~
2

2.0

10 =500mA /

_

~

"

0

1.5

V

1.4

..o~
~"Ir-~~ ~o~
f/;

I

1.2

V(th) and Ros Variation with Temperature

2.0

1.0

0.9

10 (amperes)

Tj(OC)

VN06F

"§upertex inc.
N-Channel Enhancement-Mode
Vertical CMOS Power FETs
Ordering Information
BVoss '
BVDGS

Order Number' Package

RDs(ON)

'OlON)

(max)

(min)

TO-39

550V

200

0.25A

VN0655N2

VN0655N3

VN065SNS

VN06SSND

600V

200

0.2SA

VN0660N2

VN0660N3

VN0660NS

VN0660ND

T0-92

T0-220

Dice

Features

Advanced DMOS Technology
These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

D

Freedom from secondary breakdown

D

Low power drive requirement

D

Ease of paralleling

D

Low C ISS and fast switching speeds

D

Excellent thermal stability

D

Integral Source-Drain diode

D

High input impedance and high gain

D

Complementary N- and P-Channel devices

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications
D

Motor control

D

Converters

D

Amplifiers

D

Switches

D

Power supply circuits

D

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

Package Options

i

nr
TO-39

TO-92

~

Absolute Maximum Ratings
Drain-to-Source Voltage

TO·220

Drain-to-Gate Voltage
Gate-to-Source Voltage

(Note 1)

±20V

Operating and Storage Temperature
Note 1:

Soldering Temperature'
*Oistance of 1.6 mm from case for 10 seconds.

8-61

See Package Outline section for discrete pinouts.

..

VN06F

Thermal·· Characteristics
Package

ID (cQntinuous)"

ID(pulsed)·

...

Power Dissipation
@Tb =25°C

(ljc

~a

°CfW

°CfW

IDR

'DRY·

TO-92

0.15A

0.5A

1W

125

170

0.15A

0.5A

TO-39

0.35A

1.0A

6W

21

125

0.25A

1.0A

TO-220

0.75A

1.0A

25W

3.1

70

0.6A

1.0A

*10 (continuous) is limited by max rated Tr

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

Min

I VN0655
I VN0660

Typ

Max

Unit

550

V

(Notes 1 and 2)

Conditions
VGS = 0,1 0 = 2mA

BVoss

Drain-to-Source
Breakdown Voltage

VGS(th)
dV GS(th)

Gate Threshold Voltage

4
-4.5

V
mV/oC

VGS = Vos ' 10 = 2mA

Change in VGS(th) with Temperature

IGSS

Gate Body Leakage

100

nA

VGS = ± 20V, Vos = 0

loss

Zero Gate Voltage Drain Current

10

itA
mA

VGS = 0, Vos = Max Rating

600
2

1

VGS = Vos ' 10 = 2mA

VGS = 0, Vos = 0.8 Max Rating
TA = 125°C

ON-State Drain Current

10(ON)

700
250

Static Drain-to-Source
ON-State Resistance

ROS(ON)

mA

900
19
15

0.75

dROS(ON)
GFS

Change in ROS(ON) with Temperature

CISS
Coss

Input Capacitance

85

130

Common Source Output Capacitance

50

75

CRSS

Reverse Transfer Capacitance

10

20

td(ON)
tr

Turn-ON Delay Time

10

Rise Time

10

td(OFF)
tf

Turn-OFF Delay Time

20

Fall Time

10

Vso

Diode Forward Voltage Drop

1.8

tIT

Reverse Recovery Time

Forward Transconductance

n

20

50

VGS = 5V, Vos = 25V
VGS = 10V, Vas = 25V
VGS = 5V, 10 = 100mA
VGS = 10V, 10 = 100mA

%/oC

VGS = 10V, 10 = 100mA

mU

Vos = 25V, 10 = 100mA

pF

VGS = 0, Vas = 25V
f= 1 MHz

ns

Voo= 25V
10=0.1A
Rs= 50n

V

VGS = 0, Iso = 100mA

ns

VGS = 0, Iso = 100mA

300

Note 1: All D.C. parameters 100% tested at 2S'C unless otherwise stated. (Pulse test: 300,," pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

Input

10%

I-~-OSCOPE

t(OFF)

D.U.T.
td(ON)
Output

------..I
10%

10%

8-62

VN06F

Typical Performance Curves
Output Characteristics

Saturation Characteristics
1.0

1.8

-

VGS= 6V to 10V
1.4

"'
~

CD
0-

E

I-- I--

VGS= 6V to 10V

~

.!2.
.9

CD
0-

5V

~~

0.5

E

~

~ i"""

0.6

V

E

I

3V
10

20

30

40

3V

"..

50

8

4

Transconductance VS. Drain Current
0.1

I

0.08

-55°C
I

40

I
TA

25°C

E

§.

TA _150°C

0.06

CD

...

20

Power Dissipation vs. Case Temperature

L I
I

(f)

16

50

I
TA

CD

12

Vos (volts)

VOS (volts)

c:

4V

~ I-""'"

V

j
o

"'

"'

i

0.04

Cl

Il..

:!l

30

't_:M

TO-220

~

20

i"....

"'

10 fTO -39

0.02

Vos =25V

TO-92
1.0

0.5

25

50

10 (amperes)

75

~

100

["....

125

Maximum Rated Safe Operating Area

Thermal Response Characteristics
1.0

SCD
N

'iij

§

"'0

~

TO-220 (DC)

CD
0-

","

E

.!2.
.9

TO-39

(~C)

0.1

.s

~

LU

U
Z

d\&~

">-0

"'09

~~,....~

en
LU

-'
«
::l;

a:

LU
I
I-

~
100

0.6

1000

0.2

V

./

,.../
0.01

0.1

tp (milliseconds)

8-63

-

Po =4W
Tc=25°C-

/

0.001

Vos (volts)

/

J
/

/'
LTO-39

0.4

a:

"- ~ I\10

V

«
Ien

,;;

",,-

0.Q1

0.8

0

'""'0 _

1.0

150

Tc(°C)

10

"'

5V

~

4V

".
0.2

"'
~

1.0

.& ~ """'"

10

VN06F

BVoss Variation with Temperature

/

1.1

/

i

'a

1.0

V

/

oo
c

VGS =5V . /
U)

E
.c

./

Q.

l!l

20

...... ~

II:

/

0.9

~

30

.2Z

/

>
aJ

10

~

o

-50

V J
If
/

)

40

V

V

N

E
0
.soo

On-Resistance vs. Drain Current
50

100

-

1/~

/

.2

150

I'"

V

/

VGs=10V

.6

.4

1.0

.8

10 (amperes)

Transfer Characteristics
1.0

V(lh) and Ros Variation with Temperature

lil!

Vos = 25V
0.8

1.4

I

(/SV

I

~

E

.!!!.
.9

/

0.4

J

~

1'il

~
.s

, '#'2
/""

~

..........

1.0

0.8

>

0.6

~

~

'"

~

. . .V

r-...... b£

V

'0
Q)

./

1.5

r-...... ......

3

4

E
0

0.5

o
100

150

V GS (volts)

Capacitance vs. Drain-to-Source Voltage

Gate Drive Dynamic Characteristics

200

10

f= lMHz

Vos = 10V
8

ISO
U)

~

~
S

100

U
SO

~

~\

'-

CISS

~

>
Coss

6

~

2

CRSS
10

20

30

f
o

40

I

Vos =40V

217pF

If '
I /

4

-

V/

/'

oo
t'l

I

J/

Z-

-

~
80 pF

I
0.5

1.0

1.5

QG (nanocoulombs)

Vos (volts)

8-64

1.0

........

z

~

If

-SO

5

.!::!

1'il

.s

0.4

2

2.0

10 = 100mA/

V GS(th)

t'l

h ~~

~

~

oo

/, I'" V

0.2

./

1.2

~.
)
/fi
"~
I "" oC;2

0.6

2.5

-

2.0

2.5

0J §upertex inc.

VN0606
VN0610

N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss I
BV DGS

Order Number I Package

ROS(ON)

'O(ON)

(max)

(min)

TO-92

60V

30

1.5A

VN0606L

60V

50

O.75A

VN0610LL

Features

Advanced DMOS Technology

D

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown

D Low power drive requirement
D Ease of paralleling
D Low CISS and fast switching speeds
D Excellent thermal stability
D Integral Source-Drain diode

D Complementary N- and P-Channel devices

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications

Package Options

D High input impedance and high gain

D Motor control
D Converters
D Amplifiers

D Switches
D Power supply circuits

i

D Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

Absolute Maximum Ratings

TO·92

Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature"

±40V
-55·C to +150·C
300·C
Note 1: See Package Outline section for discrete pinouts.

"Distance of 1.6 mm from case for 10 seconds.

8-65

(Note 1)

VNOQ06IVN0610

Thermal Characteristics
..~ .
Package

10 (continuous)'

10 (pulsed)

TO-92

0.3A

2.0A

PoWer Dissipation

610

61e

@Tc=25°C

°CIW

°CIW

AW

312.5

51

*ID (continuous) is limited by max rated Tr

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

Min

Typ

Max

Unit

BVDSS

Drain-to-Source
Breakdown Voltage

VN0610

VGS(th)

Gate Threshold Voltage

VN0610

0.8

2.5

VN0606

0.8

2.0

V

100

nA

VN0606

IGSS

Gate Body Leakage

IDSS

Zero Gate Voltage Drain Current

60

-

=

1001LA, VGS

V

ID

=

101LA, VGS

=0

V

VGS

=

VDS, ID

=

1mA

VGS

=

VDS, ID

=

1mA

VGS

=

±15V, VDS

VGS

= OV,

VDS

= Max Rating

VGS

= OV,

VDS

= Max

10
ILA
500

ON-State Drain Current

ID(ON)

VN0610

0.75

VN0606

1.5

RDS(ON)

VN0610

7.5

VN0610

5

VN0606

3

n

GFS

Forward Transconductance

CISS

Input Capacitance

50

COSS

Common Source Output Capacitance

25

170

ml1

CRSS

Reverse Transfer Capacitance

t(ON)

Turn-ON Time

10

t(OFF)

Turn-OFF Time

10

VSD

Diode Forward Voltage Drop

Note 1:
Note 2:

TA
A

Static Drain-to-Source
ON-State Resistance

Conditions
ID

V

60

(Notes 1 and 2)

pF

=

=0

=0
Rating

125'C

VGS

=

VGS

=

VGS

=

5V, ID

VGS

=

10V, ID

=

0.5A

VGS

=

10V, ID

=

1A

10V, VDS '" 2 VDS(ON)
10V, VDS '" 2 VDS(ON)

=

0.2A

VDS .. 2 VDS(ON), ID

VGS = 0, VDS
= 1MHz

=

25V

=

1A

= 0.5A

f

5
VDD

=

ns
VN0610

-1.2

VN0606

-.85

All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test:
All A.C. parameters sample tested.

300~s

V

25V, ID

son

RS

=

ISD

=

-OA7A, VGS

ISD

=

-0.2A, VGS

=

=

0

0

pulse, 2% duty cycle.)

Switching Waveforms and Test Circuit

INPUT
I-~:---O SCOPE

D.U.T.
OUTPUT

8-66

VN0808

"§upertex inc.
N-Channel Enhancement-Mode
Vertical CMOS Power FETs
Ordering Information
BVoss I
BVOGS

ROS(ON)
(max)

ID(ON)
(min)

Order Number I Package

80V

40

1.SA

VN0808L

TO-92

Features

Advanced DMOS Technology

D Freedom from secondary breakdown

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

D Low power drive requirement
D Ease of paralleling
D Low CISS and fast switching speeds

D Excellent thermal stability
D Integral Source-Drain diode
D Complementary N- and P-Channel devices

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications

Package Options

D High input impedance and high gain

D Motor control
D Converters

tJ Amplifiers
D Switches

D Power supply circuits

i

D Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO·92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±40V

Operating and Storage Temperature
Note 1: See Package OutUne section for discrete pinouts.

Soldering Temperature"
"Distance of 1.6 mm from case for 10 seconds.

8-67

(Note 1)

..

VN0808

Thermal Characteristics
Package
TO-92

10 (continuous)*

10 (pulsed)

.26A

±2A

Power Dissipation

~c

°je

@Tc=25°C

°CIW

1W

°C/W

125

26.4

* 10 (continuous) IS limited by max rated Tr

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

BVOSS

Orain-to-Source
Breakdown Voltage

VGS(th)

Gate Threshold Voltage

IGSS

Gate Body Leakage

lOSS

Zero Gate Voltage Orain Current

Min

Typ

Max

-

ON-State Orain Current

ROS(ON)

Static Orain-to-Source
ON-State Resistance

~

~

2.0

V

VGS ~ VOS, 10 ~ 1mA

100

nA

10

1.5
4.0

GFS

Forward Transconductance

CISS

Input Capacitance

50

COSS

Common Source Output Capacitance

40

CRSS

Reverse Transfer Capacitance

10

t(ON)

Turn-ON Time

10

t(OFF)

Turn-OFF Time

VSO

Oiode Forward Voltage Orop

Note 1:
Note 2:

Conditions
10

500
10(ON)

Unit
V

80
0.8

(Notes 1 and 2)

170

iJ.A

10iJ.A, VGS

0

VGS

~

±15V, VOS

VGS

~

OV, VOS

~

Max Rating

~

VGS

~

OV, VOS

~

Max Rating

0

TA ~ 125°C
A

VGS ~ 10V, VOS '" 2 VOS(ON)

II

VGS

~

10V, 10

~

1A

mU

VOS '" 2 VOS(ON), 10 ~ 0.5A

pF

VGS ~ 0, VOS ~ 25V
f ~ 1MHz

VOO

~

15V, 10

~

0.6A

ns
10
-1.2

RS

~

VGS

V

50n
~

0, ISO

~

-0.35A

All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test 300),1.5 pulse, 2% duty cycle.)
All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

INPUT

r-~L-;;--l

I
OUTPUT

I
I

GENERATOR

I

'r-~I~~r+~

I

:
I
I
L _____ JI

8-68

I-.u..,.--Q SCOPE
D.U.T.

o

VN10K

§upertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs

Ordering Information
BVoss I
BVOGS

Order Number I Package

RDS(ON)

ID(ON)

(max)

(min)

TO·39

I

SO

O.SA

VN10KN9

I

60V

TO·92

VN10KN3

Features

Advanced DMOS Technology

o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
TTUCMOS compatibility
Low input capacitance
Fast switching speeds
Reliable TO-92 package compatible with auto-insertion
Complements VP01A P-Channel devices

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Package Options

Applications
0

Inductive load driver

0

Display driver

0

Line driver

0

Analog switch

0

Alternative to VN01 06N3

i

TO-52

(Note 1)

i

TO-92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature·

±20V
-SSOC to +1S0°C
Note 1: See Package Outline section for discrete pinouts.

300°C

·Dislance of 1.6 mm from case for 10 seconds.

8-69

..

!

VN10K

Thermal Characteristics
~:,

~

Package

10 (continuous)

10 (pulsed)

Power Dissipation

°l~
°C(W

°je
°C(W

IDR

@Tc=25°C

170

125

1.5A

(Notes 1 and 2)

TO·92

0.3A

1.0A

1.0W

IDRM

3.0A

Note t: 10 (continuous) IS limited by max rated Tj'
Note 2: VN0106N3 can be used if an 10 (continuous) of O.SA is needed.

Electrical Characteristics
Symbol
BVOSS

(@ 25°C unless otherwise specified)

Parameter
Drain-to-Source
Breakdown Voltage

Min

VN10K

VGS(th)

Gate Threshold Voltage

LWGS(th)

Change in VGS(th) with Temperature

IGSS

Gate Body Leakage

lOSS

Zero Gate Voltage Drain Current

ID(ON)

ON·State Orain Current

Typ

Max

60

2.5

0.8
-3.8

100
10

0.25

Unit

Conditions

V

VGS

= 0.10 = 100uA

V

VOS

= VGS. 10 = lmA

mV/'C
nA

VGS = 10V. VOS = 0

p.A

VGS - O. VDS - 40V

VOS = 25V. VGS = 5V

A

----0:75
5

(Notes 1 and 2)

VOS - 25V. VGS - 10V

n

VGS = 10V. 10 - 0.5A

RDS(ON)

Static Drain-to-Source
ON·State Resistance

6RDS(ON)

Change in ROS(ON) with Temperature

GFS

Forward Transconductance

CISS

I nput Capacitance

48

60

Coss

Common Source Output Capacitance
Reverse Transfer Capacitance

16
2

25

eRSS
td(ON)

Turn·ON Oelay Time

5

tr

Rise Time

5

td(OFF)

Turn·OFF Delay Time

5

tt

Fall Time

5

VSD

Diode Forward Voltage Drop

0.8

V

ISO -.5A. VGS - 0

trr

Reverse Recovery Time

160

ns

ISO -.5A. VGS - 0

0.7
.100

%/'C

10 = 500mA. VGS = 10V

mU

VDS - 15V. 10 - 0.5A

pF

VDS = 25V. f = lMHz

ns

VOO = 25V. 10 = 0.5A.

5

RS= 50.11

Note 1: All D.C. parameters 100% tested at 2SoC unless otherwise stated. (Pulse test: 300llS pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

INPUT

Id(ON) Ir
OUTPUT

r-~L-;;--l

liON)

10%

IdIOFF) If

I
I
I

GENERATOR

I

~I~~~~

I

I
L _____ JI

I

I
8-70

i---'~-O SCOPE

D.U.T.

VN10K

Typical Performance Curves

-- -

"

,

j:~

O.B

,
I

enw
a:

9

I

O.B

1

6v

enw

'5V

::;;

0.6

a:
w

a.

f

V
If

0.2

o

r

I

r,V

0.4

1.0

I
I
VGS = 7V

I.,

w
::;;
a.

~

- -

.

•

..",

0.6

Saturation Characteristics

Output Characteristics

.,

1.0

~

0.4

9

14V •

I

0.2

:3V~
2V

o

10

20

40

30

o
50

o

2

4

6

B

10

VOS (VOLTS)

Vos (VOLTS)

Power Dissipation Vs. Case Temperature

Transconductance Vs. Drain Current
2

250

~

/

200

.-

--

/

II

::J

E
(fl

100

TO-92

~

I
I
I

u..

"

''=

I

150

50

""" i"-. """-

Vos= 10V
BOIJ.s.1%
OUTYCYCLE
PULSE TEST

o

0

o

200

400

600

BOO

1000

o

50

25

10 (rnA)

Maximum Rated Safe Operating Area
w

10

150

o>0
~

l

/

...Jrn

5

~~

1.0

5o

I - t- TO-92(OC)

w
a.

"""-

125

,

V'

C1


co

o.lv

\

V
./

«
:;;

a:

v

-

,/
0.9

o

-50

50

100

150

VGS (VOLTS)

Transfer Characteristics
1.0

VDS = 25V

iii
w
w

a:

Vos

25V

BOj./S,1%
DUTY CYCLE
PULSE TEST

I
I

lL

j

0.4

II

L
1/

j

0.2

V

V

V

0

o

/

0.D1

2

4

6

B

0.01

10

0.1

VGS (VOLTS)

Capacitance Vs. Drain-to-Source Voltage

Transconductance vs Gate-Source Voltage
250

CISS

40

200

\.

20

o

\

\

o

Vos= 10V
BOj./S,1%
DUTY CYCLE
PULSE TEST j

r-

\

30

10

1.0

ID (AMPS)

50

o
u
~
u

REDUCTI ON
DUE TO
HEATING

I

0-

~
«
a:
«
u.

I"':

.'

0.6

:;;

S
9

Output Conductance vs Drain Current
1.0

j

BOj./S,l%
DUTY CYCLE
PULSE TEST

0.8

100

10

TJ ('C)

......

J

150

~

-

10

........

i"-

20

30

I
J

100

I
L

~S r ~

clss
40

lL

50

1

ro
50

VDS (VOLTS)

V
o

2

4
VGS(VOLTS)

8-72

6

B

10

VN11A

"§upertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVDSS I
BVDGS

Order Number I Package

RDS(ON)

ID(ON)

(max)

(min)

TO-3

TO-39

TO-220

Dice

60V

0.70

8.0A

VNll06Nl

VNll06N2

VNll06N5

VNll06ND

100V

0.70

8.0A

VNlll0Nl

VNlll0N2

VNlll0N5

VNlll0ND

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low Crss and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Note 1)

Motor control
Converters
Amplifiers
Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)
TO-220

TO-39

Absolute Maximum Ratings
Drain-to-Source Voltage
TO-3

Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature'

±20V
-55°C to +150°C
Note 1: See Package Oulline section for discrete pinouts.

300°C

"Distance of 1.6 mm from case for 10 seconds.

8-73

~

I

VN11A

Thermal Characteristics
.
.

Package

10 (continuous)'

10 (pulsed),

Power Dissipation

TO-3

9.0A

TO- 39

2.5A

TO - 220

7.0A

20A
6A
lSA

(I,.

(1]&,

@TC=2SoC

.

lOR

10RM'

°C/W

°C/W

75W

41

1.6

9A

20A

6W
45W

125
70

20.S

2.5A

2.7

7A

6A
lSA

'1 0 (continuous) Is limited by max rated Tr

Electrical Characteristics
Symbol
SVDSS

VGS(th)

lWGS(thl
IGSS
IDSS

ID(ON)

(@ 25°C unless otherwise specified)

Parameter
Drain-to-Source
Breakdown Voltage

Min
VNlll0
VNll06

Gate Threshold Voltage
Change in VGS(th) with Temperature
Gate Body Leakage

O.S
-4

3

Static Drain-to-Source
ON-State Resistance
Change in RDS(ON) with Temperature

GFS

Forward Transconductance
Input Capacitance

CISS
Coss
CRSS
td(ON)
tr
td(OFF)
tf
VSD
trr

Common Source Output Capacitance
Reverse Transfer Capacitance
Turn-ON Delay Time
Rise Time
Turn-OFF Delay Time
Fall Time
Diode Forward Voltage Drop
Reverse Recovery Time

1

Conditions

VGS=O,ID=5mA

V

VGS=VOS,ID = 5mA

2.4
-6
100
50

mVtC
nA

1

mA

5
15
0.7
0.4

t.RDS(ON)

Unit

V

Zero Gate Voltage Drain Current

ON-State Drain Current

Max

100
60

S
RDS(ON)

Typ

1.0
0.7

0.3
2

O.S

240
150
16
10

350
200
25
45

5
35
20
1.2

10
45
35
1.6

300

( Notes 1 and 2 )

p.A

VGS = VDS, ID = 5mA
VGS = ±20V, VDS = 0
VGS = 0, VDS = Max Rating
VGS = 0, VDS = O.S Max Rating
TA = 125'C

A

VGS = 5V, VDS = 25V
VGS = 10V, VDS = 25V

n

VGS=5V,ID=3A
VGS = 10V, ID = 5A

%tc

VGS = 10V, ID = 5A

13

VDS = 25V, ID - 3A

pF

VGS = 0, VDS = 25V
f = 1 MHz

VDD = 25V
ID =3A
RS = 50n

ns

V
ns

VGS = 0, ISD = 5A
VGS=O,ISD = lA

Note 1: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse test: 300ms pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

INPUT

,(ON)

,(OFF)

r - ;;L-;; --,

I
,dION)
OUTPUT

10%

tr

'dIOFF) 'f

I
I

II

GENERATOR

I

~I~~~~

I

I
I
L _____ J -=-

S-74

I--~-OSCOPE

O.U.T.

VN11A

Typical Performance Curves
Saturation Characteristics

Output Characteristics
20

JGS ~ 10~-

If "

16

iii
w
II:

12

V

8

"

w
:;
0-

5
E

20

I

BJi

4

iii

w
II:
w
:;

6V -

5

I

E

J=
i

II

r
o
20

10

30

12

..,
~

8

0

4y=

~~I

r

4

2

Transconductance Vs. Drai n Current

2.0

VD~ = ~5V

T

z

w
:;
w

§

'"
t!l

Power Dissipation Vs. Case Temperature

25°C

I

TO·3

15Jc

1--'......

1.5
50

"''" " "'"

TO·220

I--'

1.0

......

.......

LL.

........

......

0.5

o

10

B

100

1=.55~C

I
I

i

iii

6

VDS (VOLTS)

VDS (VOLTS)

2.5

6V_

~~

a

50

40

i

~ ::,....~"

4

I

o

~ ........ r;r~
~~

0-

1

J

VGSiJOY-

16

TO·39

I
o

a
B

4

12

16

20

a

,"'

"'"

-..........: ~

~

125

25

150

I D (AMPERES)

Maximum Rated Safe Operating Area

Thermal Response Characteristics
1.0

100

II11

0

I

10

I III

I

~r'r1trs~

=

w

::;

«
:;

1-....

~

10

r--

w
u

'"w

iii

0.4

oJ

"'

0.2

V

/

J:
f-

a -I-

100

0.001

VDS (VOLTS)
Pulse Condition :300 !,S .2% duty cycle.

/

I
/
",

w

......

"

/

«
II:

V
;"

~

0.6

II:

:;

I

TC = 25°C
PD =45W

z
~

"-

"
1

~

~

r......

0.8

II:
0

,

TO· 220 (DC)
TO ·39 (DC)

0.1
0.1

Tb~d~o

N

~

0.01

TO·39
TC = 25°C
PD=ti

0.1
tp (SECONDS)

8-75

I

1.0

I
10

VN11A

ON • Resistance Vs. Drain Current

BVDSS Variation with Temperature
2.5

1.25

1.15

V

0

w

/

1.05

a:

0

~
U)

~
>
III

0.95

V
0.85

V

VGS = 10V

:;;
J:

Q

1.5

Z
0

~

1.0

a:

--

0.5

0.75
-50

VG~ =JJ

~

/

V

I

2.0 I---

V

N

::J
..:
:;;

v

a

a

50

a

150

100

8

4

1.45

~oS ~ 25~

17

16
TA =-SsoC

w
a:
w
Il.
:;;

~

2.2

1.8

1.30

0

/

IO=5A/

w
N

J
/

8

V.... r/

9

o

::J

IA50ci

12

4

,

Ih

A~

~

a

~5Yc./

..:
:;;
a:

0
~

~

1.15

1.0

0;

V

4

2

20

V(thl and RDS Variation with Temperature

Transfer Characteristics

~

16

12

loS (AMPERES)

TJ (oC)

20

_.......V

/

~

~(th)

........... ,...."

8

6

0.85

./

0

~~

0.6

0.2

a

50

150

100

TJ (oC)

VGS (VOLTS)

Gate Drive Dynamic Characteristics

Capacitance Vs. Drain-to-Source Voltage
10

/

f = lMHz

360

8

I-l----+---+----f----l

jg

L~
vt
1/

6

..:
a:
..:
u.
o()

"p

()

/

COSS
2

-' I -

o

10

20

30

~

~V

l/ .......... V
-

V2 OpF

a L______~:::::J::::==d=~C~RS~S;d

a
o

40

2

3

OG (NAN'OCOULOMBS)

Vos (VOLTS)

8-76

,-

/

4

~

a:
z
Z

0

1.0

r---.....

0.70
-50

10

V

10-l-- t--- r--.... "-

(!l

>

-

l/

C
w

N

1.4 ::J
..:
:;;

4

6

~
a:

4

VN11C

"'-11 !iupertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss I
BVOGS

Order Number I Package

RDS(ON)

IO(ON)

(max)

(min)

T0-3

TO·39

TO·220

Dice

160V

3Q

2.0A

VN1116N1

VN1116N2

VN1116N5

VN1116ND

200V

3Q

2.0A

VN1120N1

VN1120N2

VN1120N5

VN1120ND

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
0

Package Options

(Note 1)

Motor control

0

Converters

0

Amplifiers

0

Switches

o
o

Power supply circuits

i

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO·220

TO·39

Absolute Maximum Ratings

~,

Drain-to-Source Voltage
Drain-to-Gate Voltage

TO·3

Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature"

±20V
-55°C to +150°C
Note 1: See Package Outline section for discrete pinouts.

300°C

*Oistance of 1.6 mm from case for 10 seconds.

8-77

VNUC

Thermal
Characteristics
,
Package

ID

(continuous)'

ID

(Plllsed)'

Power Dissipation
@Tc=25°C

9ja
°CfW

9jC
°CfW

.

IDR

IORM

TO-3

3A

4.5A

100W

9.1

1.25

3A

4.5A

TO-39

1A

2.5A

4W

33

31

1A

2.5A

TO-220

2A

3.5A

45W

11.4

2.7

2A

3.5A

*10 (continuous) is limited by max rated Tj"

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

Min

L VN1116

BVoss

Drain-to-Source
Breakdown Voltage

VGS(th)

Gate Threshold Voltage

aVGS(th)

Change in VGS(th) wilh Temperalure

IGSS

Gate Body Leakage

I VN1120

loss

Zero Gale Voltage Drain Currenl

10(ON)

ON-Slale Drain Current

ROS(ON)

Change in ROS(ON) with Temperature

Coss
CRSS

Common Source Output Capacilance

IdON
I,
td(OFF)
If

Turn-OFF Delay Time

Vso
trr

Forward Transconductance

Unit

Conditions

V

VGS = 0, 10 = 5mA

200
1

3
-3.5

-6

1

1.5

2

2.5

Stalic Drain-to-Source
ON-Slate Resistance

aROS(ON)
GFS
CISS

Max

Typ

160

(Notes 1 and 2)

0.2

Input Capacitance

V
mV/oC

100

nA

50

itA

5

mA

4

2.5

3

VGS = 0, Vas = 0.8 Max Raling
TA = 125°C
VGS = 5V, Vas = 25V
VGs= 10V, Vos=25V

0.6

1

%rC

VGS = 5V, 10 = 0.5A
VGS = 10V, 10 = 1A
VGS = 10V, 10 = 1A

U

Vos = 25V, 10 = 0.5A

pF

VGS = 0, Vas = 25V
f= 1. MHz

ns

Voo = 25V
10=2A
Rs = 500

0

0.4
300

350

75

150

Reverse Transfer Capacitance

20

30

Turn-ON Delay Time

20

30

3

10

32

40

Fall Time

VGs =±20V, Vos=O
VGS = 0, Vas = Max Raling

A

3.5

Rise Time

VGS = Vas' 10 = 5mA
VGS = Vas' 10= 5mA

8

15

Diode Forward Voltage Drop'

0.7

1.0

Reverse Recovery Time

400

V

VGS = 0, Iso = 100mA
VGS = 0, Iso = O.IA

ns

Note t: All D.C. parameters t 00% tested at 25°C unless otherwise stated. (Pulse test: 300~s pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

1----PULsE---i

i
I
I
I
I
I

GENERATOR

I
\~~~~~-+~

I

I":"
L
__________II

8-78

I--~-O SCOPE

D.U.T.

VNllC

Typical Performance Curves
Saturation Characteristics

Output Characteristics
5.0

2.0

VGS=W~

VGS; 10V
~

iii
w
a:
w

0-

~

2.5

:2

5
9

-

~

o

f/

A

4V

1/

4V

J

3V
10

20

30

40

5"

). ~

1.0

~

L

o

i"

I~ ~

5V

~,.

,

V"

';/ V
."
~ '/"

o

50

"-

II

3V

o

4

2

6

8

10

VDS (VOLTS)

VDS (VOLTS)

Transconductance Vs. Drain Current

Power Dissipation Vs. Case Temperature

1.0

100
VDS = 25V

0.8

iii

zw

TO·220
0.6

:2

w

§
09.

U

Z

fE

~

0.1

0.5


co

~

........

...-

J:

~

Q

3

Z
0

~
a:

-

V

2

0.9

0.8

o

-50

o

150

100

50

0

2

1.2
TA =.55°C,'

.,...' ,
I,i' .I

25°C

h

iii
w

a:

w
::;

5
9

o

I

~

o

~

2

,

"-

1.1

Q
w

1~5°C

N

::J
«
::;

a:
0
6

III

,II'

;S

1.0

1/

ent.?

>

Cl

"-I" / '
Vi
I

0.8

8

II

300

\

«
a:
«
LL

200

U

~
u
100

o

o

0.8

I

50

100

f = 1 MHz

VOS =

0.6

K

150

1O,~7

J.40V

'I

CISS

500PF: IJ 500pF
(/

5

\."

10

I.

~

VI

COSS
CRSS

o
20

30

40

VrPi
o

5
OG (NANOCOULOMBS)

VOS (VOLTS)

8-80

Z
Q

:g

a:

Gate Drive Dynamic Characteristics
10

\

0

!

TJ tC)

\

§

i

0.4

Capacitance Vs. Drain·to-Source Voltage

~

Z

I

VGS (VOLTS)

400

«
::;

1.0

i

\

o

-50

10

:i

l'...1 i
I i Ki

i

0.7
6

./

1.2 ~

./

I......... ,

i

4

I

j/,""

0.9

1.4

10=0.SV ~

I

/

VII

1.0

5

V(th) and RDS Variation with Temperature

Transfer Characteristics
2.0
VDS =2t

4

3

10 (AMPS)

TJ tC)

0..

VGS = 10V

10

4
't1I !!iupertex inc.

VN12A

N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVDSS '
BVoos

RDS(ON)

ID(ON)

(max)

(min)

Order Number' Package
TO-3

T0-39

TO-220

Dice

40V

0.30

20A

VN1204N1

VN1204N2

VN1204N5

VN1204ND

60V

0.30

20A

VN1206N1

VN1206N2

VN1206N5

VN1206ND

100V

0.30

20A

VN1210N1

VN1210N2

VN1210N5

VN1210ND

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Note 1)

Motor control
Converters
Amplifiers
Switches
Power supply circuits

TO·3

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

Absolute Maximum Ratings
Drain-to-Source Voltage
TO·39

Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Soldering Temperature'

Note 1: See Package Outline section for discrete pinouts.

'Distance of 1.6 mm from case for 10 seconds.

8-81

TO·220

VN12A

Thermal Characteristics
Package.

10 (con~lnuous)"

10 (pulsed)"

. ::'
'"

'TO-3
TO-39

910
°CfW

lOR

10RM•
3liA ;:

30

1.25

12A

15A

6,5W

125

20

3.5A

15A

9A

35A

45W

70

2.75

9A

35A

TO-220

.~

,100W'

91e
'.:,' °C/W

3.5A

12A

35A

POy'!.er ·Dissipation
. . @"Tc =25°C i

*10 (continuous) is limited by max rated Tj'

Electrical Characteristics
Symbol

Parameter
Drain-to-Source
Breakdown Voltage

BVoss

(@ 25°C unless otherwise specified)
Min
VN1210

100

VN1206

60

VN1204

40

Typ

Gate Threshold Voltage
Change in VGS(lh) with Temperature

IGSS

Gate Body Leakage

loss

Zero Gate Voltage Drain Current

Unit

Conditions

V

0,8

VGS(lh)
aV GS(lh)

Max

2.4

(Notes 1 and 2)

VGS = 0, 10 = 10mA

V
mV/oC

-4.3

-5.5

1

100

nA

VGS = Vos ' 10 = 10mA
VGS = VDS' 10 = 10mA
VGS = ± 20V, VOS = 0

100

itA
mA

VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Rating

10

TA = 125°C
ON-State Drain Current

10(ON)

5

10

20

35

Static Drain-to-Source
ON-State Resistance

0.22

0.45

0.2

0.3

aROS(ON)

Change in ROS(ON) with Temperature

0.85

1.2

GFS
CISS

Input Capacitance

600

650

Coss
CRSS

Common Source Output Capacitance

300

350

50

75

td(ON)

Turn-ON Delay Time

8

20

tr

Rise Time

8

20

td(OFF)

Turn-OFF Delay Time

70

90

~
Vso
trr

Fall Time

40

60

Diode Forward Voltage Drop

1.2

1.4

ROS(ON)

Forward Transconductance

4.0

Reverse Transfer Capacitance

Reverse Recovery Time

VGS = 5V, Vos = 25V
VGS = 10V, Vos = 25V
VGs=5V,lo=2A

A
0
%/oC

VGS = 10V, 10 = lOA
VGS = 10V, 10 = lOA

U

Vos = 25V, 10 = 2A

pF

VGS = 0, Vos = 25V
f= 1 MHz

ns

Voo = 25V
10=5A
Rs =500

4.5

500

V

VGS = 0, Iso = lOA
VGs=O, 150= lA

ns

Note 1: All D,C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300IJ-S pulse. 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

'----puLSE---l

I

GENERATOR

1
1

Output

------,J
10%

1

v-~~r-~-+~

I
I
I
I

10%

I"

I

' - - - - - ______1

8-82

I-----~-OSCOPE

D.U.T.

VN12A

Typical Performance Curves
Saturation Characteristics

Output Characteristics
40

C;;

w
w

a:

0

1

V

9

I

Y
IV

9

4~20

30

I--"
4V ....

Y

l'

o

50

4

2

8

10

Power Dissipation Vs. Case Temperature
100

Vos = 25V

'\.. TO-3

8

(I)

6

VDS (VOLTS)

Transconductance Vs. Drain Current

:<
w
§

_I.

_ 6V.:::

f-"'"

I

10

zw

-r

I.V

VDS (VOLTS)

C;;

~ ;::::...

~

/

10

0

40

~ ~

5

I
10

~~

15

I

iY

o

w
0..
:;;
~

6V-

J./

16

c;;
w
a:

L

~

0..

VGS=10V~ ~v-

20

8~-

hV

24

8

I

~V

:<

~

tGS ~ 10~=

~
./

32

25

'\

80
TA =·55'C-

6

c;;

60

!6

40

t:

25°C_

4

LL

'\

I - - I'-.. TO-220

.........

0..

125°C:::

(!)

2

20

0

0

TO-39
0

5

10

15

20

25

•
,

'\.

0

25

50

ID (AMPERES)

'" ,
'\

""'- ~'\I,

~

75
100
TC (oC)

125

150

Thermal Response Characteristics

Maximum Rated Safe Operating Area
100

1.0

is
w

N

- ro.22"Ot8ts"ED) "'I ~~
c;;
w
a:

:J
<
:<

I'~

o\?~_=

10

0

~

~~~-

w

~{

w
:<
0..

0"

~

Z

;!...,

0.1

10
1.0
Pulse Condition: 300!'s, 2% dutycycle.
VDS (VOLTS)

<
u;

0.4

a:
oJ
<
:<
a:
w

0.2

f-

(I)

w

LIMITED
BY BVOSS
I I I

0.1

0.6

()

<>0

9

0.8

a:

J:
f-

100

0
.001

.01

.1
tp (SECONDS)

8-83

10

VN12A

ON - Resistance V,. Drain Current

BVDSS Variation with Temperature
2.0
1.1

.... V

15
w

N

::;

«
::.tI:

0

/"
1.0

V

~
CI)
CI)

0

>

V

'"

V

._-

v

VGS =5V

VGS=10V- f - -

1.6

en::.

V

J:

V

2
Z

1.2

~
tI:

0.8

0

, - - ~.

'--

0.4

-~

./

0.9

o

-50

50

100

150

o

10

20
30
IDS (AMPERES)

//

enw
5
9

,

10

15
w
N

::;

«

1//1/

tI:
0

r/J

~

o

...-

~

~v;

1260pF

40V

..J

0

~

0

u
~
u

150

8

500
COSS

>'"
Cl

4

CRSS
0
20

30

40

1300pF

6

8

/ [/

2

10

V V
./ V......

250

V
o

V
590pF
2

4

OG (NANOCOULOMBS)

VOS (VOLTS)

8-84

0.4

o
100

50

6

tI:

Z
0

0
tI:

.......

f = lMHz

~

«
:;:

;n

Gate Drive Dynamic Characteristics

CISS

N

0.8

10

750

15
w
::;

..........

TJ ("C)

Capacitance Vs. Drain-to-Source Voltage
1000

1.6

0
~

.......

o

-50

10

8

2.0

1.2

r-........

VGS (VOLTS)

~
«
tI:
«
LL

/'

0.7

0.5

6

4

50

r--.... . / io-""
V f'-...

Cl

>

~

2

0.9

£;n

A

~

1.1

~~)

::;;

fj.V

5

0

1.3

/ V/

15

w

40

IO~1O{f
V

125'C

II 25°C I

tI:

::.""

1.5

J

J J

TA = -55°C

V

V(th) and RDS Variation with Temperature

Transfer Characteristics
25

20

i:7'

o

TJ (DC)

Vos = 25V

H-.IIII I

10

VN12C

"§upertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
Order Number I Package

BVossl

ROS(ON)

JO(ON)

BVDGS

(max)

(min)

160V

In

6.0A

VN1216Nl

200V

1n

6.0A

VN1220N1

TO-3

TQ-39

TO-220

Dice

VN1216N2

VN1216N5

VN1216ND

VN1220N2

VN1220N5

VN1220ND

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C rss and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Note 1)

Motor control
Converters
Amplifiers
Switches
Power supply circuits
TO-3

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

Absolute Maximum Ratings
Drain-to-Source Voltage

TO-39

TO-220

Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Note 1:

Soldering Temperature"
·Distance of 1.6 mm from case for 10 seconds.

8-85

See Pacllage Outline section for discrete pinouts.

•

VN12C

Thermal Characteristics
Package

10 (continuous)'

10 (pulsed)'

Power Dissipation
@Tc=25°C

lI,a

lIie

°CIW

°CIW

,

lOR

10RM

TO-3

6.0A

14.0A

100W

30

1.25

6A

TO-39

3.0A

11.0A

6.5W

125

20

3A

11A

TO-220

4.5A

13.0A

45W

70

2.75

4.5A

13A

14A

*10 (continuous) is limited by max rated Tr

Electrical Characteristics
Symbol

Min

Parameter
Drain-to-Source
Breakdown Voltage

BVoss

(@ 25°C unless otherwise specified)

VGSlth )
I!N GSlth)

Gate Threshold Voltage

IGSS

Gate Body Leakage

I VN1220
J VN1216

Zero Gate Voltage Drain Current

101ON)

ON-State Drain Current

Max

Unit

Conditions

200
V

160
1

Change in VGSlth) with Temperature

loss

Typ

(Notes 1 and 2)

3

VGS = 0, 10 = 10mA

V
mV/oC

-3.7

-4.5

1

100

nA

100

j.tA

10

mA

VGS = Vos ' 10 = 10mA
VGS = Vos ' 10 = 10mA
VGS = ±20V, Vos = 0
VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Rating
TA = 125°C

4

8

8

12

Static Drain-to-Source
ON-State Resistance

0.7

1.5

0.6

1

.1.RoSION)
GFS

Change in ROSION) with Temperature

1.0

1.4

CISS

Input Capacitance

550

650

Coss

Common Source Output Capacitance

180

250

12

20

8

20

10

20

ROSION)

Forward Transconductance

2.0

CASS

Reverse Transfer Capacitance
Turn-ON Delay Time

td(OFF)
tf

Turn-OFF Delay Time

30

Fall Time

30

60

Vso

Diode Forward Voltage Drop

1.3

2.5

trr

Reverse Recovery Time

VGs=5V,lo=2A

n
%/oC

VGS = 10V, 10 = 2A
VGS -10V, 10 - 5A

V

Vos = 25V, 10 = 5A

pF

VGs=O, VOS= 25V
f=1 MHz

ns

Voo= 25V
10=2A
Rs= 50n

V

VGS = 0, Iso = 2A

ns

VGs=0,lso=1A

3.2

tdlON )
t,

Rise Time

VGS - 5V, Vos = 25V
VGS = 10V, Vos = 25V

A

90

500

Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300~s pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

I----PULSE---i
:

Output

GENERATOR

I
I
I
I
I
I
I.,.

-----..I
10%

I
~~~~-r;-~

L__________II

8-86

f--~-OSCOPE

D.U.T.

VN12C

Typical Performance Curves
Saturation Characteristics

Output Characteristics
20

10

16

8

I

enw
a:
w

12

~~

:2

5
9

--

.....-:: :::::::: ~

Q.

8

-VGS=10
86

enw

5V

:2

6

5

~~

4

1£:Y"

4V

~V

2

/
IJ'
10

20

30

40

4

2

100

4

en

"-'\

• TA =·55°C·

;; '"

L1.

(!)

o

25'C

'/
/

~
I-

60

Cl

40

~

125'C

-

TO·220

......

..............

Q.

,I

-

'\

80

I I

2

20

."

"-

'\.
I'...... '\
...............

TO·39

2

8

4
6
I D (AMPERES)

10

0

'\.

~

0

o

10

f\.

TO·3

VDS = 25V

§

8

Power Dissipation Vs. Case Temperature

Transconductance Vs. Drain Current

w
:2
w

6

VOS (VOLTS)

5

3

4

ir
o

50

VOS (VOLTS)

enz

.-

Jr

0

o

WJ

-

~~

w

9

~

4

~~

F"""'~ ~

Q.

~V

IY

0

a:

I.

VGS = 10V

25

50

75
TC ('C)

100

125

150

Thermal Response Characteristics

Maximum Rated Safe Operating Area
1.0

100

8

LU

N

1

en
w

10

-;:

0.,

'lI...;;>0~

a:

w

:2

rq

U>

1.0

°

r-- t - LIMITED
~y

0.8

:2

a:

~v

Cl

~

(~:_ _

'~0--

LU

0.6

u

z

..:

d'~

I-

en
iii
w

'0(>
0..1
t;
:I
0 _, ~.

""'0

0.1

..:

~
~'

--

Q.

5
9

::::;

004

a:

..J

t"-"

..:

:2

0.2

a:
LU

J:

IBY?SS

I-

10
100
1000
Pulse Condition: 300"s, 2% dutycycle.

0
.001

.01

.1
tp (SECONDS)

VOS (VOLTS)

8-87

10

I

VN12C

ON-Resistance Vs. Drain Current

BVDSS Variation with Temperature
4

1.1

0w
N

:J

.."

«
:;;;
a:

0
~

1.0

til
til

I--"""

.."...

V

~GS~V
-j

3.2

.....

en:;;;
J:

V
...... V

Q

en0

1.6

0

'"

0.8

o

100

50

o

150

4

8
12
lOS (AMPERES)

TJ (oC)

,
,
I ,V~

0

}5Jr

N

/

VOS = 25V

1.2

lo1:JA ~ -

TA =·55'C I
16

enw
a:

I

12

w
c..
:;;;

S
9

8

,

-

w

/

~

1.1

a:

0
~

11/

:2
.:;

>'"

1.0

0.9

(!l

4

6

8

"'" """
!/
o

a:

0

l.p 2
0

"""

"'-

""-

100

50

"'"

150

10
f = lMHz

1350pF VOS=19YA 1420pF

~
8

750

~
500

\

0

U

~
u

0.6

Gate Drive Dynamic Characteristics

Capacitance Vs. Drain·to-Source Voltage

~
«
a:
«
u..

~

TJ (oC)

1000

250

CISS-

r----

2

r-COSS_

20

30

40

~

J.

It'l
LV
I

oV
o

CRSS
10

40V

X/

4

0

o

/j

6

1000pF

4

8

12

16

QG (NANOCOULOMBS)

VOS (VOLTS)

8-88

:J
«
:;;;
~

/

VGS (VOLTS)

0w
N

V

-50

10

1.8

./'

0
2

/

1.4

0.8

~,

o

20

V(th)

"-

:J
«
:;;;

i/, mOc

II V

4

16

Vlth) and RDS Variation with Temperature

Transfer Characteristics
20

f7

~V

i==== F'""'"

0.9
-50

f--

V 1/

a:

>

10V

V

IJ

2
0

itrs =

I
VI

20

0.2

a:

VN1206
VN121 0

(,fJ !iupertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss '
BVOGS

Order Number' Package

ROS(ON)

ID(ON)

(max)

(min)

TO·39

TO·92

TO·220

120V

60

1.0A

VN1206B

VN1206L

VN1206D

120V

100

1.0A

VN1210B

VN1210L

VN1210D

Features

Advanced DMOS Technology

D Freedom from secondary breakdown

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

D Low power drive requirement
D Ease of paralleling
D Low C1SS and fast switching speeds
D Excellent thermal stability

D Integral Source-Drain diode

D Complementary N- and P-Channel devices

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications

Package Options

D High input impedance and high gain

(Note 1)

D Motor control

D Converters

D Amplifiers
D Power supply circuits
D Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

~

Drain-to-Source Voltage

TO-220

Drain-to-Gate Voltage
Operating and Storage Temperature

TO-92

TO·39

Absolute Maximum Ratings

Gate-to-Source Voltage

i

if

D Switches

±40V
-55°C to +150°C
Note 1:

Soldering Temperature"
*Oistance of 1.6 mm from case for 10 seconds.

8-89

See Package Outline section for discrete pinouts.

•

VN1206IVN1210

Thermal Characteristics
~c

°la

10 (continuous)'

10 (pulsed)

Power Dissipation

T()"39

0.7A

3.0A

6.25W

170

TO-92

O.IA

0.6A

.4W

312.5

21.3

TO-220

1.5A

3.0A

45W

80

6.25

Package

°C/W

°CIW

21

'I D (continuous) is limited by max rated Tj'

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

BVOSS

Orain-to-Source
Breakdown Voltage

VGS(th)

Gate Threshold Voltage

IGSS

Gate Body Leakage

lOSS

Zero Gate Voltage Orain Current

Typ

Min

Max

0.8

Unit

Conditions

=

VGS

=

VOS, 10

=

lmA

VGS

=

±15V, VOS

=0

VGS

= 0,

VOS

= 120V

VGS

= 0,

VOS

= 120V

10

2.0

V

100

nA

10

=

r--.,.A
500

=

TA
10(ON)

ON-State Orain Current

ROS(ON)

Static Orain-to-Source
ON-State Resistance

GFS

1.0

A

ALL

10

VN1206

6

VN1210

10

Forward Transconductance

300

n

CISS

Input Capacitance

COSS

Common Source Output Capacitance

50

CRSS

Reverse Transfer Capacitance

20

t(ON)

Turn-ON Time

16

t(OFF)

Turn-OFF Time

57

VSO

Oiode Forward Voltage Orop

125'C

VGS

=

10V, VOS ;" 2 VOS(ON)

VGS

=

2.5V, 10

=

VGS

=

10V, 10

= 0.5A

10
mU

°

100.,.A, VGS

V

120

(Notes 1 and 2)

=

0.5A, VGS

O.1A

=

10V

VOS ;" 2 VOS(ON), 10

= 0.5A

125
pF

VGS
f

=

VOO
ns

=

0, VOS

=

25V

lMHz

=

60V, 10

RS

= son

= O.IA

VN1210

-1.2

V

ISO

=

-.12A, VGS

=0

VN1206

-1.2

V

ISO

=

-.25A, VGS

=

°

Note 1: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse test: 300~s pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

INPUT
I-~,---o SCOPE

D.U.T.
OUTPUT

8-90

o

VN13A

§upertex inc.
N-Channel Enhancement-Mode
Vertical CMOS Power FETs

Ordering Information
BV DSS I
BVOGS

Order Number I Package

RDS(ON)

IO(ON)

(max)

(min)

TO-39

an
an
an

O.5A

VN1304N2

VN1304N3

O.5A

VN1306N2

VN1306N3

O.5A

VN1310N2

VN1310N3

40V
60V
100V

TO-92

Features

Advanced DMOS Technology

o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling

o
o
o
o

High input impedance and high gain

o

Complementary N- and P-Channel devices

Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown VOltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications
o
o
o
o
o
o

Package Options

(Note 1)

Motor control
Converters
Amplifiers
Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)
TO-39

TO-92

Absolute Maximum Ratings
Draln-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Soldering Temperature"

Note 1:

*Oistance of 1.6 mm from case for 10 seconds.

a-91

See Package Outline section for discrete pinouts.

.I

VN13A

Thermal,Characteristic.s
Package

10

(continuous)"

I~ (pulse(l)"

@Tc=25°C
TO-39
TO-92

1.4A
1.3A

O.4A
0.25A

8,.

8,e

°CfW

°CfW

125
170

41.5
125

Power Dissipation

3.0W
1.0W

"

lOR

10RM

O.4A
0.2SA

l.4A
1.3A

*ID (continuous) Is limited by max rated \

Electrical Characteristics
Parameter

Symbo'
BVDSS

VGS(th)
6VGS(th)
IGSS
IDSS

(@ 25°C unless otherwise specified)

Drain-to-Source
Breakdown Voltage

Min
VN1310
VN1306
VN1304

Gate Threshold Voltage
Change in VGS(th) with Temperature
Gate Body Leakage
Zero Gate Voltage Drain Current

Typ

Max

Unit

100
60
40
0.8
-3.9
0.1

Conditions

V

ID=lmA,VGS=O

V

VGS = VDS, ID = lmA
ID = lmA, VDS = VGS
VGS = ±20V, VDS - 0
VGS - 0, VDS - Max Rating
VGS = 0, VDS = 0.8 Max Rating
TA = 125°C

2.4
-5
100

mVtC
nA

~

uA

100
ID(ON)

ON-State Drain Current

0.25
0.50

RDS(ON)

Static Drain-to-Source

6RDS(ON)
GFS

ON-State Resistance
Change in RDS(ON) with Temperature
Forward Transconductarice

CISS
Coss

Input Capacitance
Common Source Output Capacitance

CRSS
td(ON)
tr
td(OFF)
tf

Reverse Transfer Capacitance
Turn-ON Delay Time
Rise Time
Turn-OFF Delay Time
Fall Time

VSD
trr

Diode Forward Voltage Drop
!;leverse Recovery Time

Note 1:
Note 2:

0.6
1.4
15

5
5
200

8
2

0.8
250
27
13
3
2
2
2

35
15
5
5
5
5

2
1.0

5
1.3

(Notes 1 and 2)

A

VGS - 5V, VDS - 25V
VGS - 10V, VDS - 25V

n

VGS = 5V, ID = 50mA
VGS - 10V, ID - 500mA

%tc

ID = 500mA, VGS

mU

VDS - 25V, ID - 500mA

= 25V,

pF

VGS = OV, VDS
f = 1 MHz

ns

VDD =25V, I D = 500mA,
RS = 50n

V

ISD = LOA, VGS - 0
ISD-l.0A, VGS=O

ns

350

= 10V

All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300l'S pulse, 2% duty cycle.)
All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

INPUT
t(ON)

r -

t(OFF)

I
I
I

OUTPUT

lI

;;L;'; - - ,

GENERATOR

I

V-I~r-~~

I

I
I
L _____ J

8-92

I-'~-OSCOPE

-=-

D.U.T.

VN13A

Typical Performance Curves
Saturation Characteristics

Output Characteristics

Cil
w
0:
w

2.0

2.0

1.6

1.6

h V-

0.

::<

~

9

VGS = l~V;;;
BV=
I
7V,=I
6V",

V

1.2

O.B

/J

~

0

~

I
I
4V:;
i

'/

9

10

20
30
VOS (VOLTS)

40

~

~

r

o
50

~

;::::::::

..-

....

7V

6V
SV

".-

4V

~~

3V

IF

o

4

2

6

B

10

VOS (VOLTS)

Power Dissipation Vs. Case Temperature

Transconductance Vs. Drain Current
O.S

~

0.8

0.4

fV

o

~S,:l~ 8v"

1.2

0.

::<

sv-

rt

0.4

Cil
w
a:
w

5

VOS = 2SV

0"",

4

TO·39

Cil
zw
::<
w

§

'"

f'...

TA =·55°C

0.3

(

0.2

I

LL
(!)

0,1

0

~

25!C

'=

r

"'-

I'-.
'"
- r---"

12S D C

I

TO·92

,

r--

M

o

o
.2

.4
.6
10 (AMPERES)

.B

o

1.0

25

50

75
100
TC tC)

aw
:::;

«

::<

f-- TO·92(OC)

TO·3!/(PC;:)

0.

9

/

a:

TO-39(PULSEO)

~

O.B

::<

o

,

.~

0.1

~

w

Z

~

en
iii
w

~

/

0.4

a:

«

::<
a:
w

0.2

r-

o

:t

.01
0.1

1

10

V

AO-39
Po =2.6W
TC = 2S"C

./

0.001

100

./

j;'

oJ

~

I
0.01

0.1
tp (SECON O~J

VOS (VOLTS)

8-93

L

/

0.6

U

~,

~

lS0

J

N

~~-~2J..P~~I~L

~

12S

Thermal Response Characteristics

Maximum Rated Safe Operating Area
10

Cil
w
a:
w

......

10

VN13A

ON - Resistance Vs. Drain Curtent

BVDSS Variation with Temperature
15

1.1

cw
N

:J

./

«
:.OC

o

V

~

~

. /V

>
III

V

V

1 1lOlJ

/'"

1
12 I-- f-1VGS = 5! - f - +---VGS=
(jJ

::E
:r

Q

./

I

9
)

Z

-

0

en0

6

oc

'"

3

f.- ...---

V

~

-

l -V

0.9

o
o

-50

o

150

100

50

0.3

0.6

,

VDS -25V

1~=5r~

1.25

TA =·55'C '
1.2

J

IJ

(jJ

w
w

0.9

:.

5
9

]5° IC

C

1..., , -

:::i

«

o

~
o

/

0

~

;....-

:2

.!:'

rn
I.?

If/

~~

/

1.2

f'.-.

0.8

...........
.........

>

r-.....

o

-50

10

8

6

0.4

............

.75

4

2

,

'-V

oc

#V

0.3

1.6

:.

1(/
0.6

......

N

/'

100

o

150

VGS (VOLTS)

Gate Drive Dynamic Characteristics

Capacitance Vs. Drain-to-Source Voltage
50

10
VDb = lbv l

f = lMHz

1/41

,\

~
«
oc
«
u.

25

o

u

~
u

o

8

~'-..
I~
o

~ r---.-

CRSS

o
10

20

30

40

VDS (VOLTS)

pF

/V

Coss-

2

V

VJ

4

-

/

I.

J [la
VJ

6

CISS

If
112

o

ILV
pF
0.2

0.4

0.6

0.8

OG (NANOCOULOMBS)

8-94

2

1.A=JomA

....... V(th)

w

I. /1~C- I--

0..

1.5

V(th) and RDS Variation with Temperature

Transfer Characteristics
1.5

oc

1.2

0.9

IDS (AMPERES)

TJ tC)

1.0

a
"-1J §upertex inc.

VN13C

N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss I
BVOGS

Order Number I Package

ROS(ON)

IOlON)

(max)

(min)

TO-39

160V

400

250mA

VNI316N2

VNI316N3

200V

400

250mA

VNI320N2

VNI320N3

TO-92

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C 1SS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Package Options

Applications
o
o
o
o
o
o

(Note I)

Motor control
Converters
Amplifiers
Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO-39

TO-92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Note t:

Soldering Temperature"
*Oistance of 1.6 mm from case for 10 seconds.

8-95

See Package Outline section for discrete pinouts.

-

I

VN13C

Thermal Characteristics
.,
Package

10 (continuous)'

10 (pulsed)'

Power Dissipation

/:Ii.

/:I/e

@Tc=25°C

°CIW

°CIW
41.5

TO-39

150mA

450mA

3.0W

125

TO-92

100mA

400mA

o.aw

155

lOR

10RM'

150mA

450mA

100mA

400mA

*10 (continuous) is limited by max rated Tr

Electrical Characteristics
Symbol
BVDSS

VGS(th)
LlVGS(th)
IGSS
IDSS

(@ 25°C unless otherwise specified)

Parameter
VN1320
Drain-to-Source
Breakdown Voltage VNI~IR

200

Gate Threshold Voltage
Change in VGS(th) with Temperature
Gate Body Leakage
Zero Gate Voltage Drain Current

1.5

ID(ON)

ON·State Drain Current

RDS(ON)

Static Drain-to-Source
ON·State Resistance

6RDS(ON)

Change in RDS(ON) with Temperature
Forward Transconductance

GFS
CISS
COSS
CRSS
td(ON)
tr
td(OFF)
tf
VSD
trr
Note I:
Note 2:

Min

Typ

IRn

3.5

V

-4.0
100

mVtC
nA

10
r-500
160
300
30
25

o.a
50

Turn-ON Delay Time
Rise Time
Turn-OFF Delay Time

70
25
10
3
1.5
2
1.5

Fall Time
Diode Forward Voltage Drop
Reverse Recovery Time

2
1.2
300

jJ.A
mA
mA

40
40
2.0

n
%tc
mU

35
15
5
5
5
5
5
2.0

Conditions

Unit

V

- 2.0

50
250

I nput Capacitance
Common Source Output Capacitance
Reverse Transfer Capacitance

Max

(Notes 1 and 2)

10 = lmA, VGS = 0

VGS = VDS, 10 = lmA
VGS = VDS, ID = lmA
VGS - ±20V, VDS = 0
VGS - 0, VDS - Max Rating
VGS = 0, VDS =
Max Rating
TA = 125°C

o.a

VGS - 5V, VDS - 25V
VGS - 10V, VDS - 25V
VGS
VGS
10 VDS

= 5V, 10 = 50mA
= 10V, I D = 100mA
100mA, VGS - 10V
- 25V, 10 - lUOmA

pF

VGS = 0, VDS = 25V
f = 1 MHz

ns

VDD = 25V
10 = O.2A, RS = 50n

V
ns

ISD-1A,VGS-0
ISD

= 1A, VGS -

0

All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300"s pulse, 2% duty cycle.)
All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

INPUT

tION)
tdlON) tr
OUTPUT

1-.u..--0SCOPE
IdIOFF) If

D.U.T.

10%

8-96

VN13C

Typical Performance Curves
Saturation Characteristics

Output Characteristics
0.5

0.2

VGS = 10V _

k~~

k:::::: ~ ::::: ~

0.4

A~ ~

0;

w
w
"::;
II:

~

9

0.3

~ 1/

0.2

0.1

0

A ~ ~ t::: 5'v-

1
I

V

"
f"

l& ~ ~

0;
w
a:
w
0..

::;

I
~V I-

~V

IVI

~~

L-

II.V

0.1

~

~~
~

4V;;;;;

7

I
50

~
..4~

-

9

4V-

o

'I

o

o

100

10

5
VDS (VOLTS)

VDS (VOLTS)

Power Dissipation Vs. Case Temperature

Transconductance Vs. Drain Current
.100

10~

VGS =

5

VDS = 25V

TA =·55°C

.080

4

25° C
0;
Z
w
::;

TO-39

.060

3

150'C

""-

w

§

en

u.

.040

2

TO-92

.020

o

o

o
0.1

0.2

0.3

0.4

0.5

"

"""'" r-...

(!l

o

25

--50

0;

0.1

9

«

::;

0.01

/

0.8

~
w

0.6

u
Z

«
Ien
enw

/

0.4

«
::;

"

II:
w
J:
I-

0.001
10

100

0.2

/

/

TO-39
TC = 25° C
PD = 3W

17'

I

0
10

1000

/

~

...J

LIMITED
BY BVDSS

100
tp (SECONDS)

VDS (VOLTS)

8-97

/

/'

0

a:

1

150

~7

a:

"'~ "'\
~

~

::::::s::

125

N

::;

"' "

w
II:
w
"::;

100

"""-

0W

,
"

1'0·92 (DC)

-"-

Thermal Response Characteristics

Maximum Rated Safe Operating Area

10~9 (IJ)

75

TC (C)

ID (AMPERES)

_T£~.!j~~SE~

'"....

1000

10,000

BV

VN13C

ON - Resistance Vs .Drain Current

BVDSS Variation with Temperature
250

1.15

5

/

1.1

N

::;
«
::;
0::
0
~

'"~

1.05

J:

Q

0.95

J

/
LI

150

Z

V

0

~

/

/

100

50
~

50

100

V

/

0

o

....

o

150

./

./

w
w
0..
::;

0.3

5

0.2

0::

E

0

5

::;

«

:;

£
~

>

I

"

1.2

~/

1.0

0.8

2.05
w

N

::;

10

«

/

1 .5 ~

o

~

- --

1.0

0.5

o
100

50
TJ ('C)

150

Gate Drive Dynamic Characteristics

Capacitance Vs. Drain·to·Source Voltage
10

f = 1 MHz

,/
VOS = ~y/

8

30

~
«
0::
«
u..

\.
20

0

~
u

10

o

6

\

U

'"

I~
o

/ ~

CISS

50~/

I'-..

10

COSS-

/

2

CRSS

o
20

30

40

1/V

V

1/ KOPF

4

11
o

1/V
I--""

V

25Pi
0.1

0.2

0.3

0.4

QG (NANOCOULOMBS)

VOS (VOLTS)

8-98

~
~

0::

"-...

o

-50

VGS (VOLTS)

40

7

....... r--..... , /
V ....... "-...

0.6

8

6

/'

r--.....V(th)

a:

0
~

~ j

4

10"= 100my

N

I,
V/
/J I

2

1.4

~

w

1/[5(}C_

o

2.5

I

Jf~5'C/

0.1

0.5

1.6

~'

Vr S = 25V

TA =.S:'C I

tii

0.4

V(th) and RDS Variation with Temperature

Transfer Characteristics

0.4

"""
0.2
0.3
lOS (AMPERES)

0.1

TJ ('C)

0.5

/

)

0::

/

0.90
-50

GS

:;:

/

1.0

J 1101_

vbs =15l

I-- t-

tii

/

/

>

'"

200

/

w

I

0.5

4

VN1706
VN1710

"-11 !iupertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss I
BVoas

Order Number I Package

ROS(ON)

IO(ON)

(max)

(min)

TO-39

TO-92

TO-220

170V

Srl

1.0A

VN170SB

VN170SL

VN170SD

170V

100

1.0A

VN1710B

VN1710L

VN1710D

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Note 1)

Motor control
Converters
Amplifiers

i

Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO·39

TO·92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

TO·220

±40V

Operating and Storage Temperature
Note 1: See Package Outline section for discrete pinouts.

Soldering Temperature·
*Oistance of 1.6 mm from case for 10 seconds.

8-99

..
!

VN1706/vN1710

Thermal Characteristics
Elil

El le

°CIW

°CIW

Package

10 (continuous)'

10 (pulsed)

Power Dissipation

TO-39

0.S3A

3.0A

S.2SW

170

20

TO-92

0.IS8A

O.SA

OAW

312.5

21.3

TO-220

0.7A

3A

20W

80

S.2S

*ID (contInuous) is limited by max rated Tj'

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

BVDSS

Drain-to-Source
Breakdown Voltage

VGS(th)

Gate Threshold Voltage

IGSS

Gate Body Leakage

IDSS

Zero Gate Voltage Drain Current

Min

Typ

Max

Unit

170
.8

-

(Notes 1 and 2)

Conditions

V

ID = 100.,.A, VGS = 0

2

V

VGS = VDS, ID = lmA

100

nA

VGS = ISV, VDS = 0
VGS = OV, VDS = 120V

10

VGS = OV, VDS = 120V

.,.A
500

TA = 125°C
tD(ON)

ON-State Drain Current

RDS(ON)

Static Drain-to-Source
ON-State Resistance

GFS

Forward Transconductance

CISS

Input Capacitance

1.0

A

ALL

10

VN1710

10

VN170S

S
300

VGS = -10V, VDS '" 2 VDS (ON)
VGS = 2.SV, ID = O.IA

0.

VGS = 10V, ID = O.SA
ID = O.SA VGS = 10V

mU

VDS '" 2 VDS(ON), ID = O.SA

125

COSS

Common Source Output Capacitance

50

CRSS

Reverse Transler Capacitance

20

t(ON)

Turn-ON Time

pF

VGS = 0, VDS = 2SV
1= lMHz
VDD = SOV, ID = O.IA

8
ns

t(OFF)

Turn-OFF Time

VSD

Diode Forward Voltage Drop

17
VN1710

-1.2

VN170S

-1.2

RS =

son

ISD = -0.19, VGS = 0

V

ISD = -1.4A, VGS = 0

Nole 1: All D.C. parameters 100% lested a125°C unless otherwise stated. (Pulse lest: 300ms pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample lesled.

Switching Waveforms and Test Circuit

INPUT

r-~L-;--l

I
I
OUTPUT

I

lI

GENERATOR

I

\~I~+-~~

I

I
I

L _____ J

8-100

I-~:---o SCOPE

D.U.T.

VN2010L

"!!iupertex inc.
Preliminary

N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss /
BV OGS

ROS(ON)
(max)

VGS(th)
(max)

Order Number / Package
T()"92

200V

10n

1.5V

VN2010L

Features
o
o
o
o
o

Freedom from secondary breakdown

o
o
o

Integral Source-Drain diode

Advanced DMOS Technology
These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Low power drive requirement
Ease of paralleling
Low Crss and fast switching speeds
Excellent thermal stability
High input impedance and high gain

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o
o

Package Options

Motor control
Converters
Amplifiers
Switches
Power supply circuits

i

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)
Telecom Switching

T0-92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±40V

Operating and Storage Temperature
Note 1:

Soldering Temperature"
*Oistance of 1.6 mm from case for 10 seconds.

8-101

See Package Outline section for discrete pinouts.

(Note 1)

,:

VN2010L

Thermal Characteristics
Package
TO-92

10 (continuous)"

10 (pulsed)"

250mA

Power Dissipation
@Tc=25°C

1.0A

81a
°C/W

125

1W

lOR

10RM"

250mA

1.0A

81c
°C/W

170

*10 (continuous) ...
IS limited by max rated Tr

Electrical Characteristics

(@ 25°C unless otherwise specified)

Symbol

Parameter

Min

BVoss

Drain-to-Source Breakdown Voltage

200

VGS(th)

Gate Threshold Voltage

0.6

IGSS
loss

Typ

Max

Unit

(Notes 1 and 2)

Conditions

V

VGS = 0, 10 = 100llA

1.5

V

Gate Body Leakage

10

nA

VGS = Vos' 10 = 1mA
VGs =±20V,V os =0

Zero Gate Voltage Drain Current

10
IlA

VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Rating

100

TA = 125°C
Static Drain-Source ON-State Voltage

VOS(ON)
ROS(ON)

Static Drain-to-Source
ON-State Resistance

0.5

V

1

V

10

n

10

n

mV

GFS

Forward Transconductance

C,SS
Coss

Input Capacitance

125
60

Common Source Output Capacitance

30
15

pF

VGS = 4.5V, 10= 50mA
VGS = 10V, 10 = 100mA
VGS = 4.5V, 10= 50mA
VGS = 10V, 10= 100mA
Vos = 25V, 10 = 100mA
VGS = 0, Vos = 25V
f= 1 MHz

CRSS

Reverse Transfer Capacitance

td(ON)

Turn-ON Delay Time

10

ns

Voo = 25V, 10 = 100mA, Rs = 50n

td(OFF)

Turn-OFF Delay Time

30

ns

Voo = 25V, 10 = 100mA, Rs = 50n

Vso

Diode Forward Voltage Drop

1.2

V

VGS = 0, Iso = 250mA

Note 1:
Note 2:

All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test:
All A.C. parameters sample tested.

300~s

pulse, 2% duty cycle.)

Switching Waveforms and Test Circuit

Input

10%

I-P<----.DSCOPE

t(ON)

D.U.T.
td(ON)
Output

-------J
10%

8-102

o §upertex inc.

VN22A

Preliminary

N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss /
BV OGS

Order Number / Package

ROSION)

IOION)

(max)

(min)

DIE

WAFER

60V

0.30

lOA

VN2206ND

VN2206NW

100V

0.30

lOA

VN2210ND

VN2210NW

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C,ss and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications

Specifications

o
o
o
o
o
o

o
o
o

Die Size:

o
o

Recommended Bonding Wire Size:

Motor control
Converters
Amplifiers

70 X 105 Mil

Die Thickness:

11 ± 1.5 Mil

Bonding Pad Size:

Switches
Power supply circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

Backside Metal:

Gate = 20 X 27 Mil
Source = 20 X 27 Mil

Au (CrAg optional)

Die Geometry
S----

Absolute Maximum Ratings
G = Gate
S = Source
Drain Backside

Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Soldering Temperature'
"'Distance of 1.6 mm from case for 10 seconds.

8-103

8 Mil

•

I

VN22A

ThermaICharacteristics,(@ SjC =1.25°CIW)
..

.

'

10 (continuous>:

ID ,(pulsed)·

IDR

8A

15A

8A

IDRM

15A

..

*10 (continuous) IS limited by max rated Tr

Electrical Characteristics
Symbol

Min

Parameter

I VN2206
I VN2210

Drain-to-Source
Breakdown Voltage

BVoss

(@ 25°C unless otherwise specified)

VGS(th)

Gate Threshold Voltage

AV GS(th)

Change in VGS(th) with Temperature

Typ

Gate Body Leakage

loss

Zero Gate Voltage Drain Current

Unit

Conditions

V

100
0.8

IGSS

Max

60
2.4

VGS = 0, 10 = 10mA

V
mV/oC

-4.3

-5.5

1

100

nA

50

~
mA

10

(Notes 1 and 2)

VGS = Vos ' 10 = 10mA
VGS = Vos ' 10 = 10mA
VGS = ±20V, Vos=O
VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Rating
TA = 125°C

ON-State Drain Current

10(ON)

3

5

ROS(ON)
AROS(ON)
GFS

Static Drain-to-Source
ON-State Resistance

0.22

0.45

0.2

0.3

Change in ROS(ON) with Temperature

0.85

1.2

Forward Transconductance

2.0

VGS = 5V, Vos = 25V
VGs= 10V, Vos=25V

A

8

C,ss

Input Capacitance

500

Common Source Output Capacitance

300

CRSS

Reverse Transfer Capacitance

td(ON)

Turn-ON Delay Time

tr
IdOFF

Rise Time
Turn-OFF Delay Time

If

Fall Time

40

60

Vso

Diode Forward Vollage Drop

1.2

1.4

trr

Reverse Recovery Time

VGs= 10V,10=4A

%/oC

3.0

Coss

VGs=5V,10=lA

n

VGS = 10V, 10 = lOA

U

Vos = 25V, 10 = 2A

pF

VGS = 0, Vos = 25V
f= 1 MHz

125

8
8

15

70

90

15

500

Note 1: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse test:
Note 2: All A.C. parameters sample tested.

300~s

Voo= 25V
ns

10=5A
Rs = 50n

V

VGS = 0, Iso = 4A

ns

VGs=O,lso=lA

pulse, 2% duty cycle.)

Switching Waveforms and Test Circuit

I----pULSE---i

i

t(OFF)

GENERATOR

1

1
~~~--~~

I
Output

1
1

------..I
10%

I

10%

1

i'"

I

L. _ _ _ _ _ _ _ _ _ _1

8-104

f-~-OSCOPE

D.U.T.

VN2222

"

§upertexinc.
N-Channel Enhancement-Mode
Vertical DMOS Power FET

Ordering Information
BV DSS I
BVDGS

RDS(ON)

ID(ON)

(max)

(min)

Order Number I Package
T0-92

7.50

0.7SA

VN2222LL

60V

Features

Advanced DMOS Technology

o

Freedom from secondary breakdown

o

Low power drive requirement

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

o
o
o
o
o
o

Ease of paralleling
Low C1SS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

Motor control
Converters
Amplifiers
Switches
Power supply circuits

i

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO·92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±40V

Operating and Storage Temperature
Note' : See Package Outline section for discrete pinouts.

Soldering Temperature'
·Distance of 1.6 mm from case for 10 seconds.

8-105

(Note 1)

_

.VN2222

Thermal· Characteristics
10 (continuous)Package

TC

TO-92
10 (contmuous)

= 100"C

10. (pulsed)

±.099A
IS

Power Dissipation

@Tc=25°C

818
°C/W

AW

312.5

±IA

81e
°C/W
51

limited by max rated Tr

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

BVOSS

Orain-to-Source
Breakdown Voltage

VGS(th)

Gate Threshold Voltage

Min

Typ

Max

Unit

60
0.6

IGSS

Gate Body Leakage

lOSS

Zero Gate Voltgge Drain Current

Conditions

V

10 = 100fLA, VGS = 0

2.5

V

VGS = VOS, 10 = lmA

100

nA

VGS = 15V, VOS = 0

10

VGS = 0, VOS = 50V

t---

fLA

VGS = 0, VOS = 50V
TA = 125°C

A

VGS = -10V, VOS '" 2 VOS(ON)

500
10(ON)

ON-State Drain Current

ROS(ON)

Static Orain-to-Source
ON-State Resistance

(Notes 1 and 2)

.75
7.5

VGS = 5V, 10 = .2A

t---

n

7.5
GFS

Forward Transconductance

CISS

Input Capacitance

60

COSS

Common Source Output Capacitance

25

CRSS

Reverse Transfer Capacitance

100

VGS = 10V, 10 = .5A
mU

VOS '" 2 VOS(ON), 10 = O.5A

pF

VGS = 0, VOS = 15V
1= lMHz

5

t(ON)

Turn-ON Time

10

t(OFF)

Turn-OFF Time

10

VSO

Diode Forward Voltage Drop

VOO = 15V, 10 = 0.6A
ns

Note 1:
Note 2:

RS = 50n

-.85

V

ISO = -.2A, VGS = 0

All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300118 pulse, 2% duty cycle.)
All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

INPUT

I

td{ONI

tr

~---lI+-~

OUTPUT

r -

t{OFFI

t{ONI

I
I
I
I

td{OFFI tf

10%

~L-;;

--,

GENERATOR

I

~I~r-~~

I

I

:
I
L _____ J

8-106

f-~r--<::

SCOPE

D.U.T.

VN2406
VN2410

" §upertex inc.
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
Order Number' Package

BVoss '

ROS(ON)

IO(ON)

BVOGS

(max)

(min)

T()"39

TO-92

TO-220

240V

6n

1.0A

VN2406B

VN2406L

VN2406D

240V

10n

1.0A

VN2410B

VN2410L

VN2410D

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Note 1)

Motor control
Converters
Amplifiers

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO·39

TO·92

~

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

i

W

Switches
Power supply circuits

TO·220

±40V

Operating and Storage Temperature
Note 1:

Soldering Temperature'
"Distance of 1.6 mm from case for 10 seconds.

8-107

See Package Outline section for discrete pinouts.

VN240SNN2410

Thermal Characteristics
lila

IIle

°CfW

°CfW

ID (continuous)"

10 (pulsed)

Power Dissipation

TO-39

0.7A

3.0A

S.25W

170

TO-92

0.158A

O.SA

OAW

312.5

21.3

TO-220

1.5A

3.0A

45W

80

S.25

Package

*10 (continuous) is limited by max rated

21

Tr

Electrical Characteristics

(@ 25°C unless otherwise specified)

Parameter

Symbol

Min

BVOSS

Drain-la-Source
Breakdown Vollage

240

VGS(th)

Gate Threshold Voltage

0.8

IGSS

Gale Body Leakage

lOSS

Zero Gale Voltage Drain Currenl

Typ

Max

Unit

V

Conditions

10

=

2.0

V

VGS

= VOS,

nA

VGS

=

VGS

= OV,

VOS

= 120V

VGS

= OV,

VOS

= 120V

10

IJ.A

500
TA
ON-State Orain Current

ROS(ON)

Static Orain-to-Source
ON-State Resistance

GFS

1.0

A
10

ALL

=0

1001J.A, VGS

100
~

10(ON)

(Noles 1 and 2)

=

=

lmA

=0

125'C

VGS

=

VGS

= 2.5V,

n

10

15V, VOS

-10V, VOS ;;, 2VOS(ON)
10

= O.lA

VN241 0

10

VGS

=

10V, 10

= 0.5A

VN240S

S

VGS

=

10V, 10

= 0.5A

Forward Transconductance

300

mU

CISS

Input Capacitance

COSS

Common Source Output Capacitance

50

CRSS

Reverse Transfer Capacitance

20

!d(ON)

Turn-ON Delay Time

Ir

Rise Time

!d(OFF)

Turn-OFF Delay Time

If

Fall Time

VSO

Oiode Forward Voltage Orop

VOS ;;, 2 VOS(ON), 10

= 0.5A

125
pF

VGS
f

=

= 0,

VOS

= 25V

lMHz

8
8

VOO
ns

18

RS

=

SOY, 10

= O.lA

= 50n

12
VN241 0

-1.2

V

ISO

= 0.19A,

VN240S

-1.2

V

ISO

= 0.8A,

VGS

VGS

=0

=0

Note t: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse test: 300~s pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

INPUT

J-,u",.---o SCOPE
D.U.T.
OUTPUT

"

VN3515L
VN4012L

§Upertex inc.

Preliminary

N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss /
BV OGS

ROS(ON)
(max)

VGS('h)
(max)

Order Number / Package

350V

150

1.5V

VN3515L

400V

120

1.5V

VN4012L

TO-92

Features
o
o
o
o
o
o
o
o

Advanced DMOS Technology

Freedom from secondary breakdown

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Low power drive requirement
Ease of paralleling
Low C ISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode
High input impedance and high gain

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

Motor control
Converters
Amplifiers
Telecom Switching
Power supply circuits

i

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO·92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature*

±40V
-55'C to +150'C
Note 1:

300'C

*Distance of 1.6 mm from case for 10 seconds.

8-109

See Package Outline section for discrete pinouts.

(Note 1)

VN3515L1VN4012L

Thermal Characteristics
Package

10 (continuous)"

10 (pulsed)"

Power Dissipation
@TC=25°C

~C

818
°CIW

lOR

10RM"

°CIW

VN3515L

180mA

720mA

1W

125

170

180mA

720mA

VN4012L

200mA

800mA

1W

125

170

200mA

800mA

"1 0 (continuous) is limited by max rated Ti"

Electrical Characteristics
Symbol

Parameter

BVoss

Drain-to-Source
Breakdown Voltage

(@ 25°C unless otherWise specified)
Min
VN3515

350

VN4012

400

Typ

Max

Unit

(Notes 1 and 2)

Conditions

V

Vos = 0,1 0 = 100J,lA

VGS(th)

Gate Threshold Voltage

1.5

V

Vos = Vos' 10 = 1mA

loss

Gate Body Leakage

10

nA

Vos = ± 20V, Vos = 0

loss

Zero Gate Voltage Drain Current

10

0.6

r---wo

Vos = 0, Vos = Max Rating
J,lA

Vos = 0, Vos = 0.8 Max Rating
TA = 125°C

VOS(ON)

ROS(ON)

VN3515
VN4012
VN3515
VN4012
VN3515
VN4012
VN3515
VN4012

Static Drain-Source
ON-State Voltage

Static Drain-to-Source
ON-State Resistance

1.5
1.2
1.5
1.2
15
12
15
12
125

V

Vos = 4.5V, 10 = 100mA

V

Vos = 10V, 10= 100mA

n

Vos = 4.5V, 10= 100mA

n

Vos = 10V, 10= 100mA

mU

Vos = 25V, 10 = 100mA

pF

VGS = 0, Vos = 25V

GFS

Forward Transconductance

C,ss

Input Capacitance

90

Coss
CRSS

Common Source Output Capacitance

20

td(ON)

Turn-ON Delay Time

20

ns

Voo = 25V, 10 = 100mA, Rs = 50n

td(OFF)
VSD

Turn-OFF Delay Time

65

ns

Diode Forward Voltage Drop

1.2

V

VDD = 25V,I o = 100mA, Rs = 50n
VGS = 0, Iso = 180mA

Reverse Transfer CapaCitance

5

Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300j1S pulse, 2% duty cycle.)
Note 2: ·AII A.C. parameters sample tested.

Switching Waveforms and Test Circuit

1--~---1:JSCOPE

t(OFF)

D.U.T.

Output

--------,J
10%

8-110

VN6035L

"

!iupertex inc.
Objective

N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss I
BV OGS

ROS(ON)

VGS(th)

(max)

(max)

Order Number I Package
TO-92

600V

350

2.8V

VN6035L

Features
D

Freedom from secondary breakdown

D

Low power drive requirement

D

Ease of paralleling

D

Low C ISS and fast switching speeds

D

Excellent thermal stability

D

Integral Source-Drain diode

D

High input impedance and high gain

D

Complementary N- and P-Channel devices

Advanced DMOS Technology
These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.
Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications
D

Package Options

Motor control

D

Converters

D

Amplifiers

D

Telecom Switching

D

Power supply circuits

D

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories. Displays, Bipolar Transistors, etc.)

T0-92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±40V

Operating and Storage Temperature
Soldering Temperature"

Note 1:

*Oistance of 1.6 mm from case for 10 seconds.

8-111

See Package Outline section for discrete pinouts.

(Note 1)

VN603SL

Thermal Characteristics
\,t

Pacl(age

TO-92

10 (continuoils)"

10 (pulsed)"

110mA

Power Dissipation
@Tc=2SoC

SOOmA

1W

,lila

lIjC

°CIW

°CIW

12S

170

lOR

10RM"

110mA

SOOrhA

"1 0 (continuous) is limited by max rated Tr

Electrical Characteristics

(@ 25°C unless otherwise specified)

Symbol

Parameter

Min

BVDss

Drain-to-Source Breakdown Voltage

600

VGSlth)

Gate Threshold Voltage

0.8

Typ

Max

(Notes 1 and 2)

Unit

Conditions

V

VGS = 0, 10 =

2.8

V
nA

VGS = VDS' 10 = 1mA
VGs =±20V,VDS =0

~

IlA

VGS = 0, VDS = Max Rating
VGS = 0, VDS = 0.8 Max Rating

1.7S

V

VGs= 10V, ID = SOmA

3S

n

VGS = 10V, 10 = SOmA

U

VDS = 2SV, 10 = SOmA

pF

VGS = 0, VDS = 2SV
f= 1 MHz

IGSS

Gate Body Leakage

10

IDSS

Zero Gate Voltage Drain Current

SO

100~

TA = 12SoC
VDSION)

Static Drain-Source ON-State Voltage

ROSION)

Static Drain-to-Source
ON-State Resistance

GFS

Forward Transconductance

CISS

Input Capacitance

80

Coss
CRSS

Common Source Output Capacitance

20

Reverse Transfer Capacitance

10

tdlON)

Turn-ON Delay Time

20

ns

Voo = 2SV, 10 = SOmA, Rs = son

tdIOFF)

Turn-OFF Delay Time

100

ns

Vso

Diode Forward Voltage Drop

1.2

V

VOD = 2SV, ID = SOmA, Rs = son
VGS = 0, Is = 11 OmA, TA = 2Soc

Note 1:
Note 2:

0.100

All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 3001lS pulse. 2% duty cycle.)
All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

Input

I----PU~E---I

I

10%
t(OFF)

I
I
I
I
I
I

td(ON)
Output

-----"'\I
10%

10%

GENERATOR

I'"

I
y-~~--~~

II

L. _ _ _ _ _ _ _ _ _ _

8-112

I--~---;O

SCOPE

D.U.T.

Alphanumeric Index and Ordering Information
Company Profile

,-,

Application Notes

-Ii

Static Handling Procedures and Quality Assurance

w;

Process Flow
DMOS Product Family
N- and p. Channel low Threshold MOSFETs
DMOS Discretes N-Channel
DMOS Discretes P-Channel

DMOS Arrays and Special Functions
HVCMOS High Voltage ICs
CMOS Consumer/Industrial Products

•
•.-

.-i!
•
•~

I

lead Bend Options and Surface Mount Packages

~\
,
,

Package Outlines

~
W,
I

Representatives/Distributors

"

IRF9521
R9521

§upertex inc.

Preliminary

P-Channel Enhancement-Mode
Vertical DMOS PowerFETs
Ordering Information
BVoss I
BVDGS

ROS(ON)
(max)

IO(ON)
(min)

Order Number I Package

-60V

0.60

-6.0A

IRF9521

TO-220

1

J

TO-92
R9521

Features

Advanced DMOS Technology

D

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown

D Low power drive requirement

D Ease of paralleling
D Low C ISS and fast switching speeds
D Excellent thermal stability
D Integral Source-Drain diode
D High input impedance and high gain

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications

Package Options

D Motor control
D Converters
D Amplifiers
D

Switches

D Power supply circuits
D Drivers (Relays, Hammers, Solenoids, Lamps,

GOS

Memories, Displays, Bipolar Transistors, etc.)

i

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Soldering Temperature"
*Oistance of 1.6 mm from case for 10 seconds.

9-1

TO-92
With TO-220
pinout
(lead bend
option: Pll)

GOS

GOS

TO-92

TO-220

_I

-.-J.

IRF9521/R9521

Thermal- Characteristics
Package

ID (continuous)"

ID (pulsed)"

Power Dlsslpetion

~c

818
°C/W

°C/W

@Tc=25°C

IDR

IDRM"

IRF9521

-S.OA

-24.0A

40W

SO

3.12

-S.OA

-24.0A

R9521

-O.SA

-7.5A

1W

125

170

-O.SA

-7.5A

'10 (continuous) is limited by max rated TI'

Electrical Characteristics (@ 25°C unless otherwise specified)
Symbol

Parameter

Min

BVoss

Drain-to-Source Breakdown Voltage

-so

VGS(th)

Gate Threshold Voltage

-2.0

IGSS
loss

Typ

Max

Unit

(Notes 1 and 2)

Conditions

V

VGS =0,1 0 = -2501lA

-4.0

V

Vos = VGS ' 10 = -2501lA

Gate Body Leakage

-500

nA

VGS = ± 20V, Vos = Max Rating

Zero Gate Voltage Drain Current

-250

~

VGS = 0, Vos = Max Rating
VGS = 0, Vos = O.S Max Rating

IlA

TA = 125°C
10(ON)

ON-State Drain Current

ROS(ON)

Static Drain-to-Source
ON-State Resistance

GFS

Forward Transconductance

-S.O
O.S
0.9

CISS

Input Capacitance

450

Coss
CRSS

Common Source Output Capacitance

350

Reverse Transfer Capacitance

100

td(ON)
t,

Turn-ON Delay Time
Rise Time

100

td(OFF)

Turn-OFF Delay Time

100

~
Vso
trr

Fal/Time

100

Note t.

VGs =-10V

A

Vos> 10(ON) X ROS(ON) Max Rating

0

VGS = -10V, 10 = -3.5A

U

Vos > 10(ON) X ROS(ON) Max
10= -3.5A

pF

VGS = OV, Vos = -25V
f= 1 MHz

ns

V00 = 0.5BV oss
10= -3.5A
Rs= 500

50

Diode Forward Voltage Drop

S.3

Reverse Recovery Time

230

V

VGS = OV, Is = -S.OA, Tc = 25°C

ns

Tj = 150°C, IF = -S.CA,
dl F/dt = 100AlllS

All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse test: 300J1S pulse. 2% duty cycle.)

Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

'----puLSE---l
:
1
1
1

td(ON)

GENERATOR

1
v-~~~~~~

I

Output _ _ _--:-:~

1

10%

1

:
~
1
'- __________1

9-2

f--~-----1:)SCOPE

D.U.T.

o

IRF9522

IR~~m

§upertex inc.

R9523
Objective

P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss I
BVOGS
-100V
-60V

Order Number I Package
10-220
10-92

ROS(ON)

'O(ON)

(max)

(min)

o.sn
o.sn

-5A

IRF9522

R9522

-5A

IRF9523

R9523

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

Motor control
Converters
Amplifiers
Switches
Power supply circuits

GOS

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO·92
With TO·220
pinout
(lead bend

option: P11)

Absolute Maximum Ratings
GOS

Drain-to-Source Voltage

TO·92

Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature'

±20V
-55°C to +150°C
300°C

*Oistance of 1.6 mm from case for 10 seconds.

9-3

GOS
TO·220

IRF9522/IRF9523/R9522/R9523

Thermal Characteristics
Package

ID

(continuous)"

..

ID

(pulsed)"

Power Dissipation
@Tc=25°C,

IRF9522
IRF9523
R9522
R9523

~

~a

°C/W

°C/W

IDR

IDRM

"

-5.0A

-20.0A

40W

80

3.1Z

-5.0A

-20.0A

-0.55A

-7.0A

1W

125

170

-0.55A

-7.0A

• 10 (continuous) IS limited by max rated Tj"

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

BVoss

Drain-to-Source
Breakdown Voltage

Min
IRF9522
R9522
IRF9523
R9523

Typ

Max

Unit

(Notes 1 and 2)
Conditions

-100
V

VGS = OV, ID = -250J.1A

-so

VGS(lh)

Gate Threshold Voltage

-4.0

V

Vos = VGS' 10 = -250J.1A

IGSS

Gate Body Leakage

-2.0

-500

nA

loss

Zero Gate Voltage Drain Current

-250

VGs =±20V,Vos =0
VGS = 0, Vos = Max Rating

J.lA

VGS = 0, Vos = 0.8 Max Rating
Tc = 125°C

-

-1000
10(ON)

ON-State Drain Current

-5.0

ROS(ON)

Static Drain-to-Source
ON-State Resistance

GFS

Forward Transconductance

CISS

Input Capacitance

450

Coss
CRSS

Common Source Output Capacitance

350

Reverse Transfer Capacitance

100

td(ON)

Turn-ON Delay Time

tr

Rise Time

100

td(OFF)

Turn-OFF Delay Time

100

~
Vso
trr

Fall Time

100

Diode Forward Voltage Drop

-S.O

0.8
0.9

A

Vos > 10(ON) x ROS(ON) Max Rating
VGs =-10V

0

VGS = -10V, 10 = -3.5A

U

Vos > 10(ON) x ROS(ON) Max
10= -3.5A
VGS = 0, Vos = -25V
f = 1.0 MHz

ns

Voo = 0.5BV oss
10 = -3.5A
Rs =500

50

Reverse Recovery Time

.

pF

230

V

Tc = 25°C, Is = -5.0A, VGS = OV
Tj = 150°C, IF = -S.OA,

ns

dlF/dt = 100NJ.lS

Note 1, All D.C, parameters 100 V. tested at 25 C unless otherwise stated. (Pulse test.
Note 2: All A.C. parameters sample tested.

300~s

pulse. 2% duty cycle.)

Switching Waveforms and Test Circuit

Input

I----PULSE---i

i

10%

I
I
I
I
I
I

td(ON)
Output _______--.I
10%

GENERATOR

i'"

I
V-~~---r~~

L. _ _ _ _ _ _ _ _ _ _

9-4

II

I--~---
III

0

~

20

a:

'"

0.94

30

Z

V

V

i!l

10

0.90

o

-50

50

100

o

150

./
",

o

0.3

'1.6

TJ ("C)

TA = ·55°C

2.2
1.4

w

J

9

:J

..:
::;;
a:

"

0
~

~
o

~

1.0

......

> <. ...............
10~~¥

0.8

~I

r----.....

10 =-50mA

-6

-8

-10

o

-50

50

-10

f= lMHz

II os =-IJif

..:
u.

50

~

~
25

o

-6

II

0

~

CISS

'"
~

t--.,...

COSS

1/ j,40V
A
If 70pF

1/ 1/

-4

>

~

-2

L

l.,./

/45PF

~

o

70pF /

-'

~

0
CJ
CJ

~

I

yy

-8

75

..:
a:

150

Gate Drive Dynamic Characteristics

Capacitance Vs. Drain·to-Source Voltage

~

100

TJ ("C)

VGS (VOLTS)

100

~=-50mA

r--......

CRSS

o
-10

-20

-30

I
o

-40

0.2

0.4

0.6

0.8

QG (NANOCOULOMBS)

VOS (VOLTS)

9-7

w
N
:J
..:
::;;

a:

~

0.6

-4

-2

I"-...

~

>

1.8

V(th)

1.2

~
iii

I(

-0.2

10=-500mA~

N

fI

-0.4

is

is

" "I125°C

-0.6

o

1//11
N'

/I II ~5°C

w
Q.
::;;
~

1.5

1.6

"

-0.8

a:

1.2

0.9

V(th) and RDS Variation with Temperature

Transfer Characteristics
VOS=-25V

V

lOS (AMPERES)

-1.0

Cii
w

ld~

VGSI =

40

1.0

0

1.4

~

1.0

~

z0

a:

i

~;

VP01A

Saturation Characteristics

Output Characteristics

U;

w

cr:

-2.0

-1.0

-1.6

-O.B

Vr.~ =

-1.2

/,,'

W

Q.

-O.B

9

0

-0.6

Q.

~

- v,

II V

-0.4

9

- v-

p;V
/2:.

-0.2

-20
-30
VDS (VOLTS)

-40

U;
2:
w
::;;
w

§

'"u.

I

150

I I.
II V

100

0

V
V
V-

I °
25 C

...-

T4V

-2

U;

15.0

TO-220

~

1=

~
0

10.0

5.0

1/

"

TO-39

0
-0.4

-O.B

-0.6

-1.0

a

25

50

I D (AMPERES)

1.0

i5

I

TO-220 (DC)

:::;

W

TO-92(DC)

Q.

::;;
-0.1

1\

%~
0
"\...

LIMITED "'\
BY BVDSS-0.01
-0.1

1 LI L I
-1.0
-10
VDS (VOLTS)

-- "
..........

125

w
u

'"

0.6

2:

«

I-

'"

iii
w

"'"

0.4

cr:

..J

«

::;;

I

/

/

150

/

0

/

./

/TO-39 °
TC=25C
PD = 3.5W

/'
0.001

0.01

0.1
tp (SECONDS)

9-8

/

/

/

:I:

-100

V

0.2

w

I-

/

/

cr:

~

..,.....,... f--

V

cr:

~
V-

"\

0.8

0

~

'\

~

9

«
::;;

-,

cr:

........

75 100
TC tC)

TO·220
TC=25°C
PD=15W/

_

w

N

~~22,(P-¥~S=Dl. -1-

.........

Thermal Response Characteristics

Maximum Rated Safe Operating Area
-10

-1.0

~

TO-92

U;
w

-10

20.0

Q.

-0.2

-B

-4
-6
VDS (VOLTS)

-~5°C .

I(
o

f"""

TA = 125°C

l(J

50

V",

co

Power Dissipation Vs. Case Temperature

~//

c.:l

~

/

25.0

VDS =-25V

200

,...J.~
o

-50

Transconductance Vs. Drain Current
250

"..."
./

L

0
-10

"

/'
..,...
~~

..,..

V

_-BV"

~ / ' .- ~

-0.4

41i-

o

V

/'

/ V
'l / V

::;;

~V
~ V-

::;;

~

U;
w
cr:
w

OIl-

~GS l-lbv

10

VP01C

"

!iupertex inc.
P-Channel Enhancement-Mode
Vertical DMOS Power FETs

Ordering Information
BVoss '
BVOGS

ROS(ON)

IO(ON)

(max)

(min)

Order Number' Package
TO·39

TO·92

TO·220

DICE

-160V

250

-250mA

VP0116N2

VP0116N3

VP0116N5

VP0116ND

-200V

250

-250mA

VP0120N2

VP0120N3

VP0120N5

VP0120ND

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage,high input impedance, low input capaCitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Package Options

Applications
o
o
o
o
o
o

(Note 1)

Motor control
Convertors

i

Amplifiers
Switches
Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO-92

W

Absolute Maximum Ratings
Drain-to-Source Voltage

TO-39

Drain-to-Gate Voltage
Gate-to-Source Voltage

~
TO-220

±20V

Operating and Storage Temperature
Note 1:

Soldering Temperature"
*Oistance of 1.6 mm from case for 10 seconds.

9-9

See Package Outline section for discrete pinouts.

VP01C

Thermal Characteristics
Package

ID

(continuous)·

ID

(pulsed)·

Power Dissipation

9,"

9,c

@Tc =25°C

°C/W

°e/W

IDR

IDRM•

TO-39

-0.2A

-0.65A

3.5W

125

35

-0.2A

-0.65A

TO-92

-O.lA

-0.35A

1.0W

170

125

-O.lA

-0.35A

-0.425A

-1.0A

15.0W

70

8.3

-0.425A

-1.0A

TO-220

• 10 (continuous) Is limited by max rated Tr

Electrical Characteristics
Symbol

Parameter

Min

I VP0120
I VPOl16

Drain-to-Source
Breakdown Voltage

BVoss

(@ 25°C unless otherwise specified)

VGS(th)

Gate Threshold Voltage

aVaSCthl

Change in VGS(thl with Temperature

lass

Gate Body Leakage

loss

Zero Gate Voltage Drain Current

ON-State Drain Current

10(ON)
ROS(ON)
aROS(ON)
GFS

Typ

Max

Unit

-200

Conditions

V

-160
-1.5

-3.5
-6.0

-100

-400

-350

-700

(Notes 1 and 2)

10 = -1.0mA, Vas = 0

V
mV/oC

Vas = Vos' 10 = -1.0mA
10 = -1.0mA, VGS = Vos

-100

nA

VGS = ±20V, Vos = 0

-10

I!A

Vas = 0, Vos = Max Rating

-1

mA

VGS = 0, Vos = 0.8 Max Rating
TA = 125°C
Vas = -5V, Vos = -25V

mA

VGS = -10V, Vos =-25V

Static Drain-to-Source
ON-State Resistance

25

40

15

25

Change in ROS(ON) with Temperature

0.6

'Y%C

10 = -100mA, VGS = -10V

70

mU

Vos = -25V, 10 = -100mA

pF

VGS = 0, Vos = -25V
1=1 MHz

ns

Voo= -25V
10= -100mA
Rs = 50n

Forward Transconductance

50

VGS = -5V, 10 = -50mA

n

VGS = -10V, 10 = -100mA

CISS

Input Capacitance

50

60

Coss
CRSS

Common Source Output Capacitance

20

30

Reverse Transfer Capacitance

5

10

td(ONI
t,

Turn-ON Delay Time

4

10

Rise Time

4

10

t(j(OFF)

Turn-OFF Delay Time

4

10

\

Fall Time

4

10

Vso

Diode Forward Voltage Drop

1.0

V

Iso = -0.5A, VGS = 0

tIT

Reverse Recovery Time

500

ns

Iso = -0.5A, VGS = 0

Note 1: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse test: 300~s pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

I----PULSE---i

t(ON)

i

t(OFF)

GENERATOR

I
I
Output

1
v-~~~~-+~

1
1

-------\I

I

10%

1

i'"

L. _ _ _ _ _ _ _ _ _ _ 1

9-10

I

J---<~-OSCOPE

D.U.T.

VP01C

Typical Performance Curves
Saturation Characteristics

Output Characteristics
-1.0

VGS=~~

-o.S

~

U;
w
a:
w
Q.
::;
~

9

~~

-0.6

~ ~ -s(,,..
~

V

~ ~V

-0.4

Ji
V

-0.2

0

-0.5

---

~

U;
w
a:
w
Q.
::;
~

-6(,-

~

/~

9

t~

t
o

VGS=-2,.OV
-0.4

-3V_
-10

-40

-20
-30
VOS (VOLTS)

-50

§
en

u.

~ e;.~ ~ .....

-4V

V

/

tV

o

-5

-10

Power Dissipation Vs. Case Temperature
25

VOS = -25V

20

120

U;
zw
::;
w

,.

TA = ·55°C

100

TO·220

15

""

I

I

so

10

25°C

(!)

I

12io c

60

5

t'.....

"',-

" .....

-

TO'39
TO·92

o

40

o

-0.2

-0.4
-0.6
10 (AMPERES)

-O.S

-1.0

o

25

50

"'" .........

75
100
TC (oC)

cw

1.0

./1

«
::;
TO-220(PULSEO)

r-TO·220(OC)
..... -...... ITO·92(PULSED)

~

9

TO-39(OC)

~

1"1

z

;::en

,'.-,

-10

0.5

enw

/

...J

«
::;

'\.

-100

V

7

/

I

7

/

a:

w

:I:

I-

o
0.001

-1000

7

V

a:

LIMITED
BY BVOSS

o

I--

TO·220
TC = 25°C
./
PO=15W/

()

1"1

-0.01

-

w

,

hIo..l\.

r'\.

-0.1

a:

o
S

-

150

77

N

:::;

-1.0

125

Thermal Response Characteristics

Maximum Rated Safe Operating Area
-10.0

U;
w
a:
w
Q.
::;

j..-"

VOS (VOLTS)

Transconductance Vs. Drain Current
140

~ ~ :..,......

-0.2

o

-SV

~ ~~~

-0.3

-0.1

41'""

~~

/

TO·92
TA = 25°C
Po = 1.0W . /

t...-0.01

./
0.1

tp (SECONDS)

VOS (VOLTS)
Pulsed Condition: 10ms, 2% duty cycle.

9-11

II

10

-6V

VP01C

ON - Resistance Vs .Drain Current

BVDSS Variation with Temperature
100

1.10

/
/

1.06
w

N

::;

«
::;;

1.02

V

a:

0

~

en
en

0.98

/

C

>

'"

/

U;
::;;

/

J:

60

0

V

a:

~

~

./

V

V

o

o

-50

50
TJ ('C)

100

o

150

Transfer Characteristics
-1.0

Vas

-0.4

o
W
::;

«
::;;
a:

o

j

o
o

-2

-4

[7/ 7Ia~-lmA

....... ~

.#

.//

V

.JAr
-6

-8

0.75
-50

-10

1.0

" " "'

o

"'

.......

......

100

50

o
150

TJ ('C)

VGS (VOLTS)

Gate Drive Dynamic Characteristics

Capacitance Vs. Drain-to-Source Voltage
80

/

"'-lP'

1.0

~

W

7

//

~ ~)

N

II V

-0.2

1.5

2.0

//

II '/
1111

0..

1.2

la~-10mA/

JI
V2;OC V
1/125'C
J

::;;

0.6
0.9
I as (AMPERES)

1.25

V VJ

TA =·55'C

-0.6

0.3

Vlth) and RDS Variation with Temperature

I

~-25V

-0.8

S
E

7

J

40

20

II

)

Z

enc

0.90

U;
w
a:
w

I

Q

/

0.94

IVGS~10V J

VGS~5V

80

/

0

rr-----,-----,r---..,----,
f~

-10

lMHz

Vas ~-~O,V ./
60

I7V

/ -40V _

CISS

13«
a:

«
LL

~
.J

40

0

~
en

0

U

-5

/ /

>

/

20

/
COSS
CRSS

0
0

-10

-20

-30

0

100pF

/

~

V~OPFI
o

-40

Vas (VOLTS)

/ j

/ '/

t:l

~
U

l00pF

-0.5
OG (NANOCOULOMBS)

9-12

-1

VP02A

"

!iupertex inc.
P-Channel Enhancement-Mode
Vertical DMOS Power FETs

Ordering Information
Order Number I Package

BVossl

ROSION)

'OION)

BVOGS

(max)

(min)

-40V

40

1.5A

-60V

40

1.5A

VP0206N2

-100V

40

1.5A

VP0210N2

TO-39

TO-92

Quad P-DIP

Quad C-DIP

VP0204N5

VP0204N6

VP0204N7

VP0206N3

VP0206N5

VP0206N6

VP0206N7

VP0210N3

VP0210N5

-

VP0204N2

TO-220

-

-

Features

Advanced DMOS Technology

o
o
o
o

Freedom from secondary breakdown

o
o

Excellent thermal stability

These enhancement-mode (normally-off) power tranSistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolartransistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

o
o

High input impedance and high gain

Low power drive requirement
Ease of paralleling
Low C 1SS and fast switching speeds

Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Complementary N- and P-Channel devices

Package Options

Applications
o
o
o
o
o
o

(Notes 1 and 2)

Motor control
Convertors
Amplifiers
Switches
Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar TranSistors, etc.)

TO-39

TO-220

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
14-Lead DIP

Gate-to-Source Voltage

±20V

Operating and Storage Temperature

Note 1:
Note 2:

Soldering Temperature"
""Distance of 1.6 mm from case for 10 seconds.

9-13

See Package Outline section for discrete pinouts.
See Array section for quad pinouts.

I

~

VP02A

Thermal Characteristics
Package

10 (continuous)'

10 (pulsed)'

-0.8A
-0.4A
-2.0A

'4.0A
-3.5A
-4.5A

Power Dissipation

,@Te
TO-39
TO-92
TO-220
Plastic Dip
Ceramic Dip

.

ID (continuous)

IS

=25°C

6W
lW
27W

eje

ej •

°CfW

°CfW

125
170
70

20
125
4.7

10RM

-0.8A
-O.4A
-2.0A

-4.0A
-3.5A
-4.5A

Reier to Arrays & Special Functions Section.
limited by max rated

Tr

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

BV Dss

Drain-to-Source
Breakdown Voltage

Min
VP021 0

-100

VP0206

-60

VP0204

-40
-1.0

Typ

Max

Unit

-3.5

Gate Threshold Voltage

!'NGS(lh)

Change in VGS(lh) with Temperature

-3.0

-3.5

IGSS
IDss

Gate Body Leakage

-1.0

-100

nA

-25

ILA

-1.0

mA

Zero Gate Voltage Drain Current
-0.6
ON-State Drain Current

ID(ON)

-1.5
RDS(ON)

3.5

8.0

3

4.0

0.75

1.2

GFS
C,SS

Forward Transconductance
Input Capacitance

VGS ; -5V, Vos; -25V
VGS ;-10V, VDs ;-25V

90

150

Coss
CRSS

Common Source Output Capacitance

65

85

Reverse Transfer Capacitance

15

20

td(ON)
t,

Turn-ON Delay Time

5

10

Rise Time

7

10

td(OFF)

Turn-OFF Delay Time

~
VSD

Fall Time

tIl

VDS ; -25V,

U

10

15

6

10

Diode Forward Voltage Drop

-1.3

-2.0

Reverse Recovery Time

430

10 ;

-0.25A

VGS ;-10V,l o ;500mA
10 ; -1.0A, VGS ; -10V

%/oC

0.5

300~s

VGS ; 0, Vos; 0.8 Max Rating
TA ; 125°C

VGS ; -5V,

Change in RDS(ON) with Temperature

Nole 1: All D.C. paramelers 100% lesled a125°C unless olherwise slaled. (Pulse lest:

VGS ; ±20V, Vos; 0
VGS ; 0, Vos; Max Rating

n

AROS(ON)

0.3

VGS ; VDS' ID ; -2.5mA
10 ; -2.5mA, VGS ; Vos

A

-2.5

Static Drain-to-Source
ON-State Resistance

ID; -2.5mA, VGS ; 0

V
mV/oC

-0.4

(Notes 1 and 2)

Conditions

V

VGS(lh)

NOle 2:

,

lOR

10 ;

-1.0A

pF

VGS ; 0, Vos; -25V
I; 1 MHz

ns

Voo; -25V
10 ; -IA
Rs; 50n

V

Iso; -lA, VGS ; 0
Iso; -lA, VGS ; 0

ns

pulse, 2% duly cycle.)

All A.C. paramelers sample lesled.

Switching Waveforms and Test Circuit
Input

1- - -

10%

:

I
I
I
I
I
I
:.,.

Id(ON)
Oulpul

-PULSE - --I

GENERATOR

--------I
10%

~----

9-14

I
V-~~--~~

I
______ I

f--~-O SCOPE

D.U.T.

VP02A

Typical Performance Curves
Output Characteristics

u;-

e

Saturation Characteristics

-5

-5

-4

-4

-3

u;-

Ol

a.

E

~

.E

~ I"""""

-2

//~

-

e

-9V

E

a.

~

-2

.E

~

-7V
-1

-6V
-5V
-4V

&

,...
o

-3

Ol

-BV

~~

-1

-10V

-10

-20

-30

-40

-50

~

~

:;;,..00

TA

I:
Ol

0.4

~

en
u.

Cl

0.2

J-ss!c-

I

TA = 1S0°C

c..'"

"

JIf

,

30

-~
TO-220

.......

"-

20

""

10

U

o

-10

TA = 2S0C

II

0.3

-B

-6

Power Dissipation vs. Case Temperature

I

Ol

TO-39
O.B

1.6

2.4

3.2

4.0

0

25

50

10 (amperes)

""

75

Maximum Rated Safe Operating Area

'"'"

100

Tc(°C)

~

125

150

Thermal Response Characteristics

10

1.0

SOl

- TO-220 (pulsed)

.t:!

u;-

T[39.Iei'lse'll

,~

TO-220 (OC)

""

1.0

e
Ol

a.
E

(ij

...

E
0

O.B

.s
UJ

(.)

0.6

Z

""

~
en

~

.E

Cii
UJ
a:

0.1

0.4

...J

<
:;
a:

0.2

UJ

J:
f0.01

o

-BV
-7V
-6V

40

I

E

-9V

50

_ Vos =-2SV

u;-

-10V

VOS (volts)

II

0.5

~

-4

-2

Transconductance vs. Drain Current
I

i-""""

--

-5V
-4V

VOS (volts)

0.6

::::.

~~

i--'" ......

10

100

1000

0.001

VOS (volts)

0.Q1

0.1

tp (milliseconds)

9-15

10

VP02A

On-Resistance vs. Drain Current

BVoss Variation with Temperature
1.1

15

I

J'

12

V"'"

VGs=-10V

J'V

,

J'/

I

f-- VGS = -5V

(j)

E

..r:;

V

9

II

~

z

J

~
Cl

c::

./

./

-~

,..",
3

0.9

-50

o

100

o

150

-2

-1

-3

-5

-4

10 (amperes)

Transfer Characteristics

V(th) and Ros Variation with Temperature
10=-1A

1.4

~V

4

'0
CD

,v

/ /
/ [/

.L. ~ [ /
4

E
0

~P
!%

"--.'t-""

/

V

.s

_:-

~"--."

'"
~

~,v~

I~~
"~fr

6

8

--.~
1.0

-""'II

~

~v

0.8

1.0

~V

1.2

.!:!
1'ii

1.2

h

~~

~ ~10 --100mA-

,--""-r~

r--

---

0.6

10

o

-50

100

150

VGS (volts)
Capacitance vs. Drain-to-Source Voltage
200

Gate Drive Dynamic Characterist.ics

.-r----,----.,------,---.,

-10

Vos = -10V

f= 1MHz

/ /
V /

-8

150
(j)

i'
0

~

Jl!

.~

-6

/

Z.

100

'"
~

.s
(.)

/

-4

Coss

-10

-20

-30

II
o

-40

-

./

, "'"- '

50
-2

9-16

V

/ / VOS = -40V~

'

1

290pF

V

63 pF

-1

-2

QG (nanocoulombs)

Vos (volts)

/

-3

~
N

0.8

'iii

0.6

.s
z

E
0
~
0

c::
0.4

VP02C

"

!iupertex inc.

I

P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVcss I
BV OGS

ROS(ON)

Order Number I Package

IO(ON)

(max)

(min)

TO-39

TO-92

TO-220

-160V

160

O.7SA

VP0216N2

VP0216N3

VP0216NS

-200V

160

O.7SA

VP0220N2

VP0220N3

VP0220NS

Features

Advanced DMOS Technology

D Freedom from secondary breakdown

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

o

Low power drive requirement

D Ease of paralleling

o

Low CISS and fast switching speeds

D Excellent thermal stability

o

Integral Source-Drain diode

D Complementary N- and P-Channel devices

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications

Package Options

D High input impedance and high gain

o
o
o
o
o

(Note 1)

Motor control
Convertors
Amplifiers

i

Switches
Power supply circuits

D Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO-92

it

Absolute Maximum Ratings
Drain-to-Source Voltage

TO-39

Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature"

~
TO-220

±20V
-SSOC to +1S0°C
Note t:

300°C

*Oistance of 1.6 mm from case for 10 seconds.

9-17

See Package Outline section for discrete pinouts.

VP02C

Thermal Characteristics
Package

ID

(continuous)'

ID

(pulsed)'

Power Dissipation

B,.

B,a

@Tc=25°C

,

IDR

IDRM

°CIW

°CIW

TO-39

-0.35A

-1.0A

4W

32

125

-0.35A

TO-92

-0.2A

-1.0A

1W

125

170

-0.2A

-1.0A

TO-220

-0.8A

-2.5A

27W

4.7

70

-0.8A

-2.5A

-1.0A

, Ie (continuous) is limiled by max rated Tj

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

Min

I VP0220

Drain-to-Source
Breakdown Voltage

BVess

I VP0216

Vas(th)

Gate Threshold Voltage

dVaS(th)

Change in Vas(th) with Temperature

lass

Gate Body Leakage

less

Zero Gate Voltage Drain Current

ON-State Drain Current

le(oN)

Typ

-3.5
-4.5

-0.25

-0.4

-0.75

-0.85

-6.0

Vas = Yes' Ie = -2.5mA
Vas = VDS ' Ie = -2.5mA

nA

Vas = ±20V, Ves = 0

J.lA

Vas = 0, Ves = Max Rating

-2

mA
A

9

16

7

16

0.5

1.2

CISS

Inpul Capacitance

85

150

Coss
CRSS

Common Source Oulput Capacitance

60

85

Reverse Transfer Capacitance

10

35

tdON

Turn-ON Delay Time

8

10

tr

Rise Time

10

15

tclJOFF)

Turn-OFF Delay Time

15

20

~

Fall Time

10

15

Vse

Diode Forward Vollage Drop
Reverse Recovery Time

-1.2
400

-1.8

I"

Vas = 0, Ie = -2.5mA

-25

Change in RDS(ON) with Temperature
0.1

V
mV/oC

Conditions

-100

dRes(ON)
GFS

Forward Transconductance

Unit
V

-160
-1.0

Static Drain-Io-Source
ON-State Resistance

Res(ON)

Max

-200

(Notes 1 and 2)

g

Vas = 0, Ves = 0.8 Max Rating
TA = 125°C
Vas = -5V, Ves = -25V
Vas =-10V, Ves =-25V
Vas = -5V, Ie = -0.1A
Vas = -10V, Ie = -0.25A

%/oC

Vas = -10V, ID = -0.25A

U

Ves = -25V, Ie = -0.25A

pF

Vas = 0, Ves =- 25V
f= 1 MHz

ns

Vee =-25V
le=-1.0A
Rs= 50g

V
ns

Vas = 0, Ise = -0.5A
Vas = 0, Ise = -0.5A

0.2

Note 1: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse test: 300~s pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

Input

10%

r~---<:)SCOPE

t(OFF)

D.U.T.

Output

------I
10%

9-18

VP02C

Typical Performance Curves
Saturation Characteristics

Output Characteristics
-1.0

-2.0

VGS=-10V

~~

enw

,'r'

II:

w

0..

~

A

-1.0

~

9

J

~~

:? po

6V

~

-0.5

o~

4V f -

1

-10

-20

·-30

-40

~

o

-50

--

~

r-

~

V"

=::

~3!V

~~

If

~

VGS =-10V
p~6V

-6

-4

-2

~

C

·1 4V
-8

-10

VDS (VOLTS)

VDS (VOLTS)

Transconductance Vs. Drain Current

Power Dissipation Vs. Case Temperature

so

.40
VDSi-45V
TA = ·55°C

.32

enz

w
:;
w

25°C

125°C

§
(/)

~

.24

TO-220
25

-~

'"""-

o

.16

"'"

0..

LL

t!l

.08

-.75

-1.5

"- .:--....

TO·39

o
0

..........

0

25

50

75

100

Maximum Rated Safe Operating Area

Thermal Response Characteristics

-10

C

1.0

w
N

:::;

«
:;

enw

-1

5
9

II:
0

TO-220(DC)
TO-39(PULSED

II:

w
0..
:;

TO-39(DC)
-0.1

...

~
w
U
Z

... \.

"'r\. "

«
t-

... ...

LIMITED
BY BVDSS
-10

O.S

(/)

iii
w

II:
.J

«

.....

0,01
- -0,01

125

TC (C)

I D (AMPERES)

:;

r\.

-100

II:

w

:r
t-

-1000

O
tp (SECONDS)

VDS (VOLTS)

9-19

150

VP02C

ON-Resistance Vs. Drain Current

BVDSS Variation with Te",perature
100

1.3

~-5V

VGS

C

1.2
~

w

N

:J
«
:<

cr:
0
6

rn

1.1

~/

1.0

~

./

>
II>

1/

V
50

1/

V

~

vGS

./

0.9

-"

/

J

~

o

-2.0

VOS

50

o

150

100

-1.0

-2.0

lOS (AMPERES)

Transfer Characteristics

V(th) and RDS Variation with Temperature

~-25V

,,

/25°C'

l/

-1.0

I /

I.

./

W

N

:::;
:<
cr:

"

-4

-2

1.2

o
6

i'

V

r-..... r--.
0.9

~

.- ~

V

-6

-8

0.5
-50

-10

~
........... .........

f

~

o

100

0

U

~
40

"""

0

1/17

CISS.
f-- I--

7

............

Casso

I'--.
0

-10

CRSS
-20

150

X-40~

I

215pF

-30

o

-40

VOS (VOLTS)

lf1~o

~

~5PFI~
I

j--

~ ~I- -f---~-----i-

1- -

f--

- -

1- -

QG (NANOCOULOMBS)

9-20

i

R-I

-1

-2

z
Z
0

//q=
V

120

cr:

0

1icr:

vJs~~1Tv;r

I-- i---

u

...... .........

50

-10

1MHz

:J
«
:<
1.0

Gate Drive Dynamic Characteristics

Capacitance Vs. Drain-to-Source Voltage

w

N

;7

TJ (oC)

160

80

0

0.7

VGS (VOLTS)

~
«
cr:
«
u..

A./J

)O~-125mA

~

V(th)

«

.J. ~

..,",

'O~-~5~m~7

c

,.

2.0

/

1.4

/ /j25ol[~ -

o

0

.....

~-10V

i.,...-- i--""

TJ tC)

TA =-55°C/

o

~~

17'

VP03D

"§upertex inc.
P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss /
BV OGS

Order Number / Package

RDS(ON)

10(ON)

(max)

(min)

TO-3

T()"39

-350V

6Q

-1.5A

VP0335N1

VP0335N2

VP0335N5

VP0335ND

-400V

6Q

-1.SA

VP0340N1

VP0340N2

VP0340NS

VP0340ND

TO·220

DICE

Features

Advanced DMOS Technology

o
o
o
o

Freedom from secondary breakdown

o

Excellent thermal stability

o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

High input impedance and high gain

Low power drive requirement
Ease of paralleling
Low C1SS and fast switching speeds

Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Notes 1 and 2)

Motor control
Convertors
Amplifiers
Switches
Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO-3

Absolute Maximum Ratings
Drain-to-Source Voltage

TO-39

TO-220

Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature>

±20V
-55°C to + 150°C

Note 1: See Package Outline section for discrete pinouts.
Note 2: See Array section for quad pinouts.

300°C

*Oistance of 1.6 mm from case for 10 seconds.

9-21

i,;,
. .,.

VP03D

Thermal Characteri$tics
Package

ID·(continu.ous)·

10 .(pulsed)·

Power Dissipation
@Tc :o;25°C

".

911
°CIW

91"
°CIW

lOR

IDRM•

TO-3

~2.7A

-5.0A

100W

1.25

30

-2.7A

-5.0A

TO-39

-0.7A

-5.0A

6W

20.8

125

-0.7A

-5.0A

TO-220

-1.6A

-5.0A

50W

2.5

40

-1.6A

-5.0A

• 10 (continuous) is limited by max rated Tj'

Electrical Characteristics
Symbol

Parameter

VGSIIhI
tNGSlth)

Min

I VP0340
I VP0335

Drain-to-Source
Breakdown Voltage

BVoss

(@ 25°C unless otherwise specified)

Gate Threshold Voltage

Typ

Max

Unit

-400

-4.8

Change in VGSlth) with Temperature

-4.5
-6.0

V
mV/oC

IGSS

Gate Body Leakage

-100

nA

loss

Zero Gate Voltage Drain Current

-200

ItA

-2

mA

ON-State Drain Current

10(ON)

-1.5
-1.5

t.RO~ONL
GFS
CISS

Change in ROS(ON) with Temperature

Coss
CRSS
td(ON)
t,

Forward Transconductance

6

0.7

1.2

0.5

700

Common Source'Output Capacitance

90

120

Reverse Transfer CapaCitance

20

50

Turn-ON Delay Time

25

40

Rise Time

25

40

td(OFF)

Turn-OFF Delay Time

65

110

~

Fall Time

20

40

Vso

Diode Forward Voltage Drop
Reverse Recovery Time

-1
500

-1.3

VGS = ±20V, Vos = 0
VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Rating
TA = 125°C

Q

VGS = -5V, 10 = -0.25A
VGS = -10V, 10 = -0.5A

%IOC

VGS = -10V, 10 = -0.5A

U

Vos = -25V, 10 = -0.5A

pF

VGS = 0, Vos = -25V
f= 1 MHz

ns

Voo= -25V
10=-1A
Rs= 50Q

V
ns

VGS = 0, Iso = -0.5A
VGS = 0, Iso = -0.5A

1
550

t"

Input CapaCitance

VGS = Vos ' 10 = -10mA
VGS = Vos ' 10 = -10mA

VGS = -5V, Vos = -25V
VGs =-10V, Vos =-25V

5
4

VGS = 0, 10 = -10mA

A

-3.5

Static Drain-to~Source
ON-State Resis\!i'nce

ROS(ON)

Conditions

V

-350
-2.5

(Notes 1 and 2)

Note 1: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse test: 3001'8 pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

I----PULSE~--I

t(ON)

i

t(OFF)

I
V-~~r-~-+~

1
1
1
1

td(ON)
Output

GENERATOR

I

-----.I
10%

1

I

-:

1

L.. _ _ _ _ _ _ _ _ _ _

9-22

I

f-~---.

:;

5

9

I'"

,

150

~

'0
w

ff/

N

125°C

::i

",
......
" :.....

.

5
9

~

~ ~ ""I

:;

,.I,

.4~~

-1.0

-1.6

I

..- f-

~ :.

VGS

-BV ....

~ :,.....-

~ V....
Ih ~

I>.

5
9

-2.0

0.01

/

/

TO-39
TC = 25°C
PO-6W

0.1
tp (SECONDS)

10

-SV
7V

VPO,3D

BVDSS Variation with Temperature

ON - Resistance Vs. Drain Current
20

1.1

/'

C
w

./

N

::J

«
:;

a:
0
g

1.0

!:3'"

>
Ol

V

V

V

V

16

.;'

I

,.--

I

~G~ =5~

VG~! lbv-- I--

iii
:;

./

1:

Q

12

Z

. . .V

0

~

S

........ V

a:

4

~~

0.9

o

-60

50

100

o

160

o

TJ (oC)

3
4.5
lOS (AMPERES)

Transfer Characteristics

V(th) and RDS Variation with Temperature

-5.0

I

VOS =-25V

I

TA = .5S·C-"

1.5

~-

\.4

I

V

-4.0
/25°C ~I

iii
w
a:
w

1/

-3.0

J' ...r

'"
:;

5
9

If
-2.0

J

w

N

/

a:

125°C

g

I~

~
~

o

-4

-2

-6

V

........

th)

,........,,~

IO=~~

1.0

O.S

600

CJ

-S

-10

o

-50

~
CJ

250

"--

.........
0

o

VDS=-10~'1

I. ~40~

~

...J

I.

0

>'"
Cl

-4

~
-2

COSS_
CRSS-20

-30

,

-40

VOS (VOLTS)

1300pF

'I

-6

~

-10

150

Gate Drive Dynamic Characteristics

CISS_

--

r- r--

TJ (·C)

I

1/1
j V
p

(
/1150pF

o0

-4

-S

-12

-16

OG (NANOCOULOMSS)

9-24

~
a:

oz

100

50

-S

"

1.2

0.8

-20

g
~

a:
0.4

-10

0

::J

-r-..

'"i?-.506mA

Capacitance Vs. Drain-to-Source Voltage

~
«
a:
«
IL

w

0.6

1000

\

c

N

.;'

./

VGS (VOLTS)

750

2.0

1.6

>

~.,.

0

1.2

::J
«
:;
0

J

LV

C

rv
/j

-1.0

7.5

6

o

VP03E

,,§Upertex inc.
P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss /
BV OGS

Order Number / Package

ROS(ON)

IO(ON)

(max)

(min)

TO-3

TO-39

TO-220

CICE

-450V

7.50

-1A

VP0345Nl

VP0345N2

VP0345N5

VP0345ND

-500V

7.50

-1A

VP0350Nl

VP0350N2

VP0350N5

VP0350ND

Features

Advanced DMOS Technology

o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

o
o
o

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C 1SS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Notes 1 and 2)

Motor control
Convertors
Amplifiers
Switches
Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

Absolute Maximum Ratings
TO·39

Drain-to-Source Voltage

TO·220

Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature

Note 1:

Note 2:

Soldering Temperature'
*Distance of 1.6 mm from case for 10 seconds.

9-25

See Package Outline section for discrete pinouts,
See Array section for quad pinouts.

~

VP03E

Thermal Characteristics
Package

10 (continuous)'

10 (pulsed)'

Power Dissipation

9)e

9)8

@Tc=25°C

°C/W

°CIW

lOR

10RM'

TO-3

-1.5A

-3.0A

100W

1.25

30

-1.5A

-3.0A

TO-39

-0.4A

-3.0A

6W

20.8

125

-0.4A

:3.0A

TO-220

-1.0A

-S.OA

50W

2.5

40

-I.OA

-3.0A

• Ie (continuous) Is limited by max rated Tj'

Electrical Characteristics
Symbol

Parameter
Drain-to-Source
Breakdown Voltage

BVess

(@ 25°C unless otherwise specified)
Min

I VP0350
I VP0345

VGS(lh)

Gate Threshold Voltage

!'..V GS(lh)

Change in VGS(lh) with Temperature

IGSS
less

-4.5
-6.0

V
mV/oC

Gate Body Leakage

-100

nA

Zero Gate Voltage Drain Current

-200

itA

-2

mA

-0.75

Change in Res(ON) with Temperature
Forward Transconductance

0.25

Conditions

5.5

7.5

0.7

1.2

Input CapaCitance

550

700

Coss
CRSS

Common Source Output Capacitance

90

120

Reverse Transfer Capacitance

20

50

tdON

Turn-ON Delay Time

II

30

tr

Rise Time

II

30

td OFF

Turn-OFF Delay Time

70

100

~
Vse

Fall Time

22

30

Diode Forward Voltage Drop

-1.0

-1.3

trr

Reverse Recovery Time

550

VGS = Yes' Ie = -IOmA
VGS = Yes' Ie = -IOmA
VGS = ±20V, Ves = 0
VGS = 0, Ves = Max Rating
VGS = 0, Ves = 0.8 Max Rating
TA = 125°C
VGS = -5V, Ves = -25V
VGs=-IOV, Ves =-25V

0

VGS = -5V, Ie = -0.25A
VGS = -IOV, Ie = -0.25A
VGS = -IOV, le= -0.25A

%/"C

0.75

CISS

VGS= 0, Ie =-IOmA

A

-2.5
6.0

Static Drain-to-Source
ON-State Resistance

!'..ReS(ONL
GFS

Unit
V

-4.8

-1.0
ReS(ON)

Max

-450
-2.5

ON-State Drain Current

le(ON)

Typ

-500

(Notes I and 2)

U

Ves = -25V, Ie = -0.5A

pF

VGS = 0, Ves = -25V
f= I MHz

ns

Vee = -25V
Ie = -0.5A
Rs =500

V

VGS = 0, Ise = -0.25A

ns

VGS = 0, Ise = -0.25A

Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300)!s pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

1- - :

I
I

td(ON)
Output

-pulsE - --I

GENERATOR

I
V-~~--~~

I
I

------.I

I

10%

I

I
-:
I
L
__________
I

9-26

j-,..~__IJSCOPE

D.U.T.

VP03E

Typical Performance Curves
Output Characteristics

Saturation Characteristics
-2.0

4

I

3

CD

c.

E

~

.E

~

r

,

,

~

-

~

-1.6

10V
7V
Ii)
~

6V

"

c.

E

~

-0.8

.E

5V

~

-0.4

J

~

4V

o

,

-1.2

CD

-10

·20

-30

-40

-4

TA--55'C_ -

Ii)

TA = 25'C
TA - 150'C

60

TO-220

~

-

0

a..

0.2

"-

~

'Iii

(!)

40

""" 1"""'."-

20
TO-39

o

2

3

0

5

4

25

50

10 (amperes)
Maximum Rated Safe Operating Area

TO-39

(pulsed)

"1" 1-1

-

I-

-1

-I

E

_

~

"

,

"TO-3

-TO-220

CD

.E

100

~

125

150

Thermal Response Characteristics
1.0

_

c.

75

'\.

Tc(°C)

-10

Ii)
~

-10

,
"
1"""'"r\.

80

0.4

-8

l\.

TO-3

VDS = 25V

~
~

-6

Power Dissipation vs. Case Temperature

0.8

0.8

-4V

VOS (volts)

100

CD

",

~~

-2

Transconductance VS. Drain Current

CD

II

....

TO-39

"-

~

-0.1

'0
CD
.!::!

1U

E
0

0.8

.s

~

w

t)

I

Z

0.6

~

"\

Cii
W
a:

0.4

--I

......


III

0.95

/

/

/

/

./

L

./

./

VGS =-5V

16

VGS =-10V

(i)

E

.s::
~

12

Z

0

iii

c

8

-"'"

/

a:

4

0.9

o

-50

100

o

150

Transfer Characteristics

,CJoLL

,~
"Y('

-3.0

/

2i
E

.!!
...f'

1.1

~

",.

.!::!
0;

,4~

~

-1.0

~

:2
<::.

0.9

en

~

~

V

C><

"".". i"""

0.8

V

/

2.0

V

i

0;

~

"

1.0

.......

-6

-10

-8

o

-50

".....

100

150

VGS (volts)
Capacitance vs. Drain-to-Source Voltage

Gate Drive Dynamic Characteristics

800

-10

f=lMHz

/.

-8

Vos = 10V

600
(i)

~

.l!!

.~

400

.s
u

200

~-

\

'-

c,ss

I

-6

C!l

-4

l/¥

en

>

~~

-2

Coss

-

CRSS
10

800 pF. /

20

30

o

~'

~

Vos = 40V

I ' 800pF

500 pF
246

QG (nanocoulombs)

Vos (volts)

9-28

~V

I

if
40

"'

1

8

~

j

.........

o

-4

-2

~

1.0

oS

I. ~ V
l/. ~
lb ~

10 = 250mA

V(th)

"-

0

~v,,'t-/

-2.0

-5.0

v

13'
CD

'1i

It

(i)
~

-4.0

1.2

A

Vos = 25V

-2.0
-3.0
10 (amperes)

V(th) and Ros Variation with Temperature

-5.0

-4.0

-1.0

10

IIll

VP0300

"-II §upertex inc.
P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVDSS 1
BVDGS

R OSION)
(max)

(min)

TO-39

I

T0-92

-30V

2.50

-1.SA

VP0300B

I

VP0300L

IDION)

Order Number I Package

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C1SS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
0

Motor control

0

Converters

0

Amplifiers

0

Switches

o
o

Power supply circuits

Package Options

Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)
TO·39

(Note 1)

i

TO·92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±40V

Operating and Storage Temperature
Note 1: See Package Outline section for discrete pinouts.

Soldering Temperature'
*Oistance of 1.6 mm from case for 10 seconds.

9-29

VP0300

Thermal Characteristics

'0 (continuous)'

10 (pulse!!)

Power Oissipaiion

TO-39

1.25A

3.0A

6.25W

170

20

TO-92

0.32A

0.B7A

OAW

41

312.5

Package

°Ja

°Je

°CIW

°CIW

• ID (continuous) is limited by max rated Ti'

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

BVOSS

Orain-to-Source
Breakdown Voltage

VGS(th)

Gate Threshold Voltage

Min

Typ

Max

-30

-304

-2

Unit

Conditions

=

10

-4.5

V

VGS

=

VOS, 10

nA

VGS

=

±30V, VOS

VGS

= OV,

VOS

=

-25V

VGS

= OV,

VOS

=

-25V

Gate Body Leakage

100

lOSS

Zero Gate Voltage Orain Current

-10
.,.A
-500

TA
10(ON)

ON-State Orain Current

ROS(ON)

Static Orain-to-Source
ON-State Resistance

-1.5

-1.7
2.5

GFS

Forward Transconductance

CISS

Input Capacitance

150

COSS

Common Source Output Capacitance

100

CRSS

Reverse Transfer Capacitance

60

t(ON)

Turn-ON Time

30

t(OFF)

Turn-OFF Time

30

VSO

Oiode Forward Voltage Orop

200

10.,.A, VGS

=

=

lmA

=0

12SoC

A

VGS

=

-12V, VOS '" 2 VOS(ON)

n

VGS

=

-12V, 10

mU

pF

VGS
f

=

=

1.2

V
pulse, 2% duty cycle.)

0, VOS

=

= O.SA

-15V

lMHz

VOO

300~s

= -IA

VOS '" 2 VOS(ON), 10

=

ns

Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test:
Note 2: All A.C. parameters sample tested.

=0

V

IGSS

-

(Notes 1 and 2)

RS

=

ISO

=

-25V, 10

=

-IA

son
-1.SA, VGS

=

a

Switching Waveforms and Test Circuit

INPUT

OUTPUT

r-~L-;--l

I
I
I

GENERATOR

I
I

:
I
I
I
L _____ J

9-30

~..".-_{)SCOPE

\r-I~+-4-~

-=

D.U.T.

o

VP05D

!iupertex inc.
P-Channel Enhancement-Mode
Vertical DMOS Power FETs

Ordering Information
BV oss '

ROS(ON)

Order Number' Package

IO(ON)

BVOGS

(max)

(min)

TO·39

TO·92

DICE

-350V

750

-200m A

VP0535N2

VP0535N3

VP0535ND

-400V

750

-200mA

VP0540N2

VP0540N3

VP0540ND

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C ISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
0

Motor control

0

Convertors

0

Amplifiers

0

Switches

o
o

Package Options

(Notes 1 and 2)

Power supply circuits

i

Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO-92

TO·39

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature"

±20V
-55°C to +150°C

Note 1:

Note 2:

300°C

*Oistance of 1.6 mm from case for 10 seconds.

9-31

See Package Outline section for discrete pinouts.
See Array section for quad pinouts.

VPOSD

Thermal Characteristics
10 (continuous)"

Package

10 (pulsed)"

Power Dissipation
@Tc=25°C

~c

°CIW

811
°CIW

.

lOR

10RM

TO· 39

-0.2A

-O.SA

3.5W

35

125

-0.2A

-0.5A

TO· 92

-O.lA

-0.5A

1.0W

125

170

-O.lA

-0.5A

,. 10 (continuous)

IS

limited by max rated Tj.

Electrical Characteristics
Symbol
BVDSS

VGS(th)
LWGS(th)
IGSS
IDSS

(@ 25°C unless otherwise specified)

Parameter
Drain·to·Source
Breakdown Voltage

Min
VP0540
VP0535

Gate Threshold Voltage
Change in VGS(th) with Temperature
Gate Body Leakage
Zero Gate Voltage Drain Current

Typ

Max

Unit

-400
-350

-3.5

-4.5
-6.0
-100
-10

t---

ON·State Drain Current
200

RDS(ON)
lIRDS(ON)
GFS
CISS
COSS
CRSS
td(ON)
tr
td(OFF)
tf
VSD
trr

Static Drain·to·Source
ON·State Resistance
Change in RDS(ON) with Temperature
Forward Transconductance
Input Capacitance
Common Source Output Capacitance
Reverse Transfer Capacitance
Turn·ON Delay Time
Rise Time
Turn·OFF Delay Time
Fall Time
Diode Forward Voltage Drop
Reverse Recovery Time

/LA

-80
-250

50

75
1.5

70
40
11

60
20

-0,8
200

\'l
%/'C
mU

5
10
15
15
10
-1.5

VGS= VDS,ID=-lmA
VGS = VDS, ID = -lmA
VGS - ±20V, VDS - 0
VGS - 0, VDS - Max Rating
VGS = 0, VDS = 0.8 Max Rating
TA = 125'C
VGS =-5V, VDS =-25V
VGS=-10V, VDS=-25V
VGS =-5V, ID =-10mA
VGS =-10V, ID =-50mA
VGS=-10V,ID=-50mA
VDS = -25V, ID =-50mA

mA

60
45
0.8

3

VGS = 0,10 =-lmA

V
mV/'C
nA

-500
ID(ON)

Conditions

V

-2.5

(Notes 1 and 2)

VGS = 0, VDS =-25V
f= 1 MHz

pF

VDD =-25V
ns

ID=-50mA

V
ns

VGS=O,ISD=-O.lA

RS= 50.11
VGS = 0, ISD =-0.1 A

Note 1: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse test: 300~s pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

INPUT

r-;;:;L-;--'
I
I
I

OUTPUT

GENERATOR

I

\~I~+---~

I

:
I
IL _____ JI
9·32

I--'~-OSCOPE

D.U.T.

VP05D

Typical Performance Curves
Saturation Characteristics

Output Characteristics
-0,5

~GSI=Jov

w

a::
w

~

-0.3

Cl.

::0
~

£:

#

-0.2

-0.1

0

I-!

-

K

-0.4

til

-0.2 r---,--r---,-----r--,---;--r---,----r-.,

l.-': i--""n
.....

av

......
~

-

til
w

a::

w

J. V

,

~

I- ~-8V

-

l6V

fj

l£:

-0.1

J,

~V

o

-10

-20
-30
VDS (VOLTS)

-

-40

o

-50

o

-10

-5
VOS (VOLTS)

Transconductance Vs. Drain Current

Power Dissipation Vs. Case Temperature

-100

5
TA = -55°C

I('
4

25 JC

til

TO-39

r

zw

w

:J

.".

3

::0

en

-50

15JC

"-........

r-

..J

2

~
CI)

fl

LL

"
o

o

o

0.16
ID (AMPERES)

'-,

o 25

0.3

Maximum Rated Safe Operating Area
1.0

~ TCf.; 3tJf~LIS~)rT6

til
w
a::
w

aw

"---'"

0.01

:J



-8

---

0.9
-50

-10

/I

./

"'-,,,,-

Q

w

N

=-50mA

:::i

..:

:;:

a:
1.0 0z

/

1.0

~

/

-6

f - - ~(th)

w

~

o

-0.5

V(th} and RDS Variation with Temperature

Transfer Characteristics
-0.4

~

I-- I--

20

.90
-50

w

--

II

V

Z
0

"-

o

"-

50

'a:8

'"

100

TJ ('C)

VGS (VOLTS)

'"

0.0

150

Gate Drive Dynamic Characteristics

Capacitance Vs. Drain-to-Source Voltage
-10

80

1/
/
/ -fov
/ ./

Vos =-l~V
60

~
..:
a:

..:
u.

40

-8

~

r-

~

CISS

-6

VV

-'

0

L ./

2!

0

II)

U

(.?

~

105 pF

-4

>

()

20 1--

o

~

C SS

I'-o

10

132PF

-2

I---

I

CRSS
20

30

I

o
o

40

\

0.2

0.4

0.6

0.8

QG (NANOCOULOMBS)

VOS (VOLTS)

9-34

1.0

VP05E

"§upertex inc.
P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
Order Number' Package

BVoss '
BV OGS

ROS(ON)

(max)

(min)

T()'39

T()'92

DICE

-450V

1250

100mA

VP0545N2

VP0545N3

VP0545ND

-500V

1250

100mA

VP0550N2

VP0550N3

VP0550ND

IO(ON)

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C,ss and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Notes 1 and 2)

Motor control
Convertors
Amplifiers
Switches
Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO-39

i

TO-92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature'

±20V
-55°C to +150°C
300°C

*Oistance of 1.6 mm from case for 10 seconds.

9-35

Note 1:

See Package Outline section for discrete pinouts.

Note 2:

See Array section for quad pinouts.

-.

~,

VP05E

Thermal Characteristics
Package

10 (continuous)'

10 (pulsed)'

Power Dissipation
@Tc=2SoC

9jC

9'8

°CIW

°CIW

IDR

10RI"

TO-39

-125mA

-0.25A

3.5W

35

125

-125mA

-0.25A

TO-92

-70mA

-0.25A

1W

125

170

-70mA

-0.25A

, 10 (continuous) IS limited by max rated Tj'

Electrical Characteristics

(@ 25°C unless otherwise specified)

Parameter

Symbol

Min

I VP0550

Drain-to-Source
Breakdown Voltage

BVoss

I VP0545

VGSJlhl

Gate Threshold Voltage

aV GS(lIli
IGSS

Change in VGS(Ih) with Temperature
Gate Body Leakage

loss

Zero Gate Voltage Drain Current

Typ

Max

Unit

-500
-4.5
-3.5

-6
-100

rnA

VGS = -5V, Vos = -25V
VGs =-10V, Vos =-25V

n

VGS = -5V, 10 = -5mA
VGS = -10V, 10 = -10mA

0.85

"/%C

VGs =-10V,1 0 =-10mA

40

mU

Ves = -25V. 10 = -10mA

pF

VGS = 0, Vos = -25V
f = 1 MHz

-150
75

125

aROS(ON)
GFS

Change in ROS(ON) with Temperature

C,SS

Input Capacitance

35

60

Coss

Common Source Output Capacitance

10

20

Forward Transconductance

25

Reverse Transfer Capacitance

3

10

Turn-ON Delay Time

5

10

Rise Time

8

15

Turn-OFF Delay Time

8

15

~

Fall Time

5

10

Vso
trr

Diode Forward Voltage Drop
Reverse Recovery Time

-0.8
200

-1.5

CRSS
tdJON )
t,
tdOFF

VGS = 0, Vos = 0.8 Max Rating
TA = 125°C

85

Static Drain-to-Source
ON-State Resistance

ROS(ON)

VGS = ±20V, Vos = 0
VGS = 0, Vos = Max Rating

ilA

-50
-100

VGS = Vos' 10 = -1mA
VGS = Vos , 10 = -1mA

nA

-10
l-

ON-State Drain Current

VGs =0,l o =-1mA

V
mY/DC

-1000
10(ON)

Conditions

V

-450
-2.5

(Notes 1 and 2)

Voo= -25V
10 = -10mA
. Rs=50n

ns

V
ns

VGS = 0, Iso = -0.1A
VG.=0,l so =-O.1A

Note 1: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse te.t: 300)1S pulse. 2% duty eyele.)
Note 2:

All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

Input

I----pULSE---i

t(ON)

Output

i

10%
t(OFF)

GENERATOR

1
1
1
1

-----..I

1
~~~--~~

1
1

10%

i'"

I

L.. _ _ _ _ _ _ _ _ _ _ 1

9-36

I-~-OSCOPE

D.U.T.

VP05E

Typical Performance Curves
Output Characteristics

Saturation Characteristics

-0.5

-1.0

-0.4

Iii

l!!
CD

-0.3

..o!!:

a.

,

E

~

..9

-0.8

,

-0.2

-0.1

~

~

/ ~~

Iii

io"""

loIII!IS ~

-0.6

l!!
CD

-7V

a.

E

~

-0.4

..9

-6V

-0.2

-5V

'r

/

-10V
-8V

...0lIl

~

o

-10

-20

-30

o

-50

-40

",.

~
-4

-2

Vos (volts)

.... ~
~,
~~
~

-6

-4V

-8

-10

Vos (volts)
Power Dissipation vs. Case Temperature

Transconductance vs. Drain Current
5

50

Vos = -25V
40

TA = -55°C

Iii
c::

CD

30

I(

E

TO-39

:e
rJl

"-

,

20

II

C!}

10

f"..

I'"

TA=25°C

CD

'""'

[L

TA = 150°C

TO-92

-

r-..

-0.15

-0.3

25

50

Maximum Rated Safe Operating Area

TO-39 (pulsed)
,...1-1' I·~
TO-39 (DC)

125

150

•

- '""

<0
CD

.!::!

0;

§

I..

" '- " ~

-TO-92 (DC)

a.
E

'-

~
0.1

0.8

0

.s

1.0

CD

..9

100

1.0

-

l!!

75

'1'0...

r-.. ~

Thermal Response Characteristics

10

Iii

""- ~

TdOC)

10 (amperes)

UJ

"
\..

()

Z

0.6

~
CI)

"

""~ I

~

iii

UJ
II:

0.4

....J

<

::E

II:
UJ

""

0.2

:c

I-

0.01

10

100

1000

0.001

0.01

0.1

tp(milliseconds)

Vos (volts)

9-37

-10V
-8V
-6V
-5V

10

VP05E

On-Resistance vs. Drain Current

BVoss Variation with Temperature
1.15

/
/

1.1

V

N

E
0

1.05

.s

CI)
CI)

.0

VGS = -5V

VGS = -10V

...,'

-.--'"

160

~

'0
III

7a

200

1.0

>

III

,/

0.95

0.9

/

/

U;
E
.::

V

120

.2Z

~

0

80

a:
40

V
-50

-.1

-.05

150

100

-.15

-.25

-.2

10 (amperes)
Transfer Characteristics
1.1

If

Vos = -25V

t?J~ ~

1.05

oC;

~
N
7a

J
<:~;p
qr!f

IfJ

"'I.

f'...

f'...

1.0

E
0

oC>

:2
<::.

.95

V

CI)

Cl

>

/t

.9

I~ /'

~~

"

10 =-10mA

V (Ih)

.s

If' /.""r:s
IiV
",~"'-f-

-2

,

V(lh) and Ros Variation with Temperature

-0.4

r".. V
D<
V r"..

V

f'...

2.0

V

1.6

OJ

0.8

.s
z

"-r"..

.85

·4

-6

-so

-10

-8

o

100

150

VGS (volts)
Capacitance vs. Drain-to-Source Voltage

Gate Drive Dynamic Characteristics
10

80

~

f=lMHz
60

U;

~

'"

'0
0

40

:e,
t)

20

Vos = -10V

~

"-r---...
\

P

~~os =-40V_

~~

[,- ~

"-

Coss

.............

CR$S
10

~'

20

~ ~ 83pF

CISS

"-

30

2

-

/

J

30 pF

I{
o

40

0.2

0.4

0.6

QG (nanocoulombs)

VOS (volts)

9-38

0.8

~
.~

1.2

1.0

E
0
~
0

a:
0.4

VP06D

"§upertex inc.
P-Channel Enhancement-Mode
Vertical DMOSPower FETs
Ordering Information
BVoss /
BVOGS

Orur Number / Package

ROS(ON)

IO(ON)

(max)

(min)

-350V

250

-O.4A

VP0635N2

VP0635N3

VP0635N5

VP0635ND

-400V

250

-O.4A

VP0640N2

VP0640N3

VP0640N5

VP0640ND

T0.92

TO·3f

DICE

TO·220

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate mar11.lfacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inhereflt in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C ISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertax Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Notes 1 and 2)

Motor control
Convertors
Amplifiers

if

Switches
Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO·39

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature"

~

i

TO-92

TO-220

±20V
-55°C to + 150°C
Note 1; See Package Outline section tor discrete pinouts.

300°C

*Oistance of 1.6 mm from case for 10 seconds.

9-39

VPOSD

Thermal Characteristics
Package

10 (continuous)"

10 (pulsed)"

Power Dissipation

61e
°C/W

'@>Tc =25°C
..

618
O(;/W

lOR

10RM"

-0~30A

-O.SA

lW

125

170

-0.30A

:O.SA

TO-39

-0.40A

-0.75A

SW

21

125

-0.40A

-0.75A

TO-220

-0.40A

-0.75A

28W

2.7

70

-0.40A

-0.75A

TO-92

• 10 (continuous) is limited by max rated Tr

Electrical Characteristics (@ 25°C unless otherwise specified)
Symbol
BVoss

Parameter

Min

I VPOS40

Drain-to-Source
Breakdown Voltage

I VPOS35

Typ

Max

Unit

-400
-4

VGs(th)
tNGs(th)

Gate Threshold Voltage
Change in VGs(th) with Temperature

-4.8

IGss

Gate Body Leakage

-100

nA

loss

Zero Gate Voltage Drain Current

-10

itA

-1

mA

10(ON)

-400
ROS(ON)

19

VGs = ±20V, Vos = 0
VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Rating
TA = 125°C
VGS = -5V, Vos = -25V
VGS = -10V, Vos = -25V
VGS = -5V, 10 = -100mA

0

25
0.75

.1.R OS (ON)
GFS

Change in ROS ON) with Temperature
Forward Transconductance

C1ss
Coss

Input Capacitance

75

130

Common Source Output Capacitance

50

75

Reverse Transfer Capacitance

10

20

CRSs
tdON
. tr

VGS = Vos ' 10 = -2mA
VGs = VDS ' 10 = -2mA

mA

-550
20

Static Drain-to-Source
ON-State Resistance

VGS = 0, 10 = -2mA

V
mV/oC

-300

ON-State Drain Current

Conditions

V

-350
-2

o/oI°C

VGS = -10V, 10 = -100mA
VGS = -10V, 10= -100mA

mU

VDS = -25V, 10 = -100mA

pF

VGS = 0, Vos = -25V
f= 1 MHz

ns

Voo= -25V
10 = -100mA
Rs = 500

V
ns

VGS = 0, Iso = -100mA
VGS = 0, Iso = -100mA

100

Turn-ON Delay Time

10

Rise Time

10

td(OFF)

Turn-OFF Delay Time

20

~

Fall Time

10

Vso
trr

Diode Forward Voltage Drop
Reverse Recovery Time

1.8

(Notes 1 and 2)

300

Note 1: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse test: 300l1s pulse. 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

1----puLSE---1
t(ON)

i

t(OFF)

GENERATOR

I
I
I
I

Output .,.-_ _ _~
10%

I

rv-+~+-~-+~

I
I

i

7
~----

9-40

I
______I

I---~-O SCOPE

D.U.T.

VP06D

Typical Performance Curves
Output Characteristics

Vl
~

-1.0

-1.6

-0.8

tP ~

CI>

E

.9

-0.8

-0.4

~

~

/
y

~

-7V

-0.4

.9

-10

-20

-30

VOS

Vos

~

-0.6

~

CI>

a.
E

~

-40

~"

-0.2

VS.

~

~ ~ ",....

-5V

-4

-2

-6

Power Dissipation

VS.

Case Temperature

50

=-2SV
Tl=Jsocl-

40

120

Tl =Jsoc l-

30

Vl
E
CI>

:§.

T~ =

80

1

1S0

(!)

I

b-

o

a..'"

40

TO-220

~

.........
.....

20

b-...

.......

i"o..

"

10
TO-39

0.8

1.2

1.6

2.0

25

50

0.1

I"",

1'\
TO-39 (DC)

~

rTt;2~U=)'

'0
CI>

~~>~
o~
'&>.,'

~
E

<'0 ~

.s>

~00

,

CI>

a.

E

~

.9

125

150

1.0

~~

Vl

100

Thermal Response Characteristics

Maximum Rated Safe Operating Area

"'" ....

75

Tc (0G)

10 (amperes)

1.0

..........
~

TO-92
0.4

-10

-8

Vos (volts)

Drain Current

t;¢'- ('0

~<:-i-..-0

I'~

0.8

0

oS
UJ

()

Z

0.6

~
(/)

1\"'

enUJ

" "'

I'

0.01

N

=

0.4

a:

-'
«

'"

:2

a:
UJ
:r:

0.2

I0.001
10

100

0.01

1000

0.1

tp (milliseconds)

Vos (volts)

9-41

-6V

""""

1/"'"
o

-50

160

o

-10V

~~

(volts)

Transconductance

s:

Vl

-8V

-6V

200

CI>

-10V
-9V

-5V

"

c:

--

-......--:

-1.2

a.
~

Saturation Characteristics

-2.0

10

VP06D

On-Resistance vs. Drain Current

BVoss Variation with Temperature
1.15

40

V

1.1

~

~

E
.s
0

.<::

V

0

(/J
(/J

Ui
E

,/

1.05

1.0

/

>
III

/

/

0.9

-

0

Cii
0

16

a:
8

/

VGS = -10V

24

.2Z

~

0.95

VGS = -5V

32

/

'0

I

/

-

,.,. ./

V

o
100

-50

o

150

.4

.2

1.0

.8

.6

10 (amperes)
Transfer Characteristics
-2.0

Vos = -25V

~

.9

IV"

-0.8

1.1

i~

~
o

-4

-2

"

........

'0
OJ
.!::!
tii

1.0

V(lh)

........... ......

E
(;

.s

ou_

§.

I/r/'~~_

-0.4

o

~

1*

E

~

10 =-loomy

1fll

-1.2

OJ

c.

L

J

pi/!fJ

-1.6

Ui

V(lh) and Ros Variation with Temperature
1.2

/'

0.9

.,

(/J

./

Cl

>

"''

/

"?< ......

~

/

r--.... .....

.........

0.8

0.7

-6

-8

-10

o

-50

100

150

VGS (volts)
Capacitance vs. Drain-to-Source Voltage
200

Gate Drive Dynamic Characteristics

.-----,-----r---..,.-----,

-10

f=IMHz
Vos =-10V/
-8

/V

150

Ui

I

~
(/J

S

Cl

>

0

/~os=40V_
~ V150P~

-6

~

100

-4

50
-2

/ ./
./

f

~~

~~

.90 pF

I

o
o

10

20

30

40

Vos (volts)

9-42

I

o

0.5

1.0
1.5
2.0
QG (nanocoulombs)

2.5

VP06E

"§upertex inc.
P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
Order Number I Package

BVoss I
BV OGS

ROS(ON)
(max)

IO(ON)
(min)

TO-39

TO-92

-450V

200

-0.2A

VP0645N2

VP0645N3

VP0645N5

VP0645ND

-500V

200

-0.2A

VP0650N2

VP0650N3

VP0650N5

VP0650ND

TO-22O

DICE

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Package Options

(Note 1)

Motor control
Convertors
Amplifiers

if

Switches
Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO-39

Absolute Maximum Ratings
Drain-to-Source Voltage

~

i

TO-92

TO-220

Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Note 1:

Soldering Temperature"
"'Distance of 1.6 mm from case for 10 seconds.

9-43

See Package Outline section for discrete pinouts.

.-

'"

"

VP06E

Thermal Characteristics
Package

10

(continuous)"

10

(pul$8d)~

Power Dissipation
@Tc=25°C

8)0

8)0

°C/W

°C/W

10RM"

lOR

TO-92

-0.1A

-0.3A

1W

125

170

-0.1A

-0.3A

TO-39

-0.25A

-0.5A

6W

21

125

-0.25A

-0.5A

TO-220

-0.25A

-0.5A

45W

2.7

70

-0.25A

-0.5A

• 10 (continuous) is limited by max rated \

Electrical Characteristics
Symbol

Parameter

Min

I VP0650
I VP0645

Drain-to-Source
Breakdown Voltage

BVoss

(@ 25°C unless otherwise specified)
Typ

Max

Unit

-500

Conditions

V

-450
-2

-4

VGS(th)
I'NGS(th)

Gate Threshold Voltage
Change in VGS(th) with Temperature

-4.8

IGSS

Gate Body Leakage

-100

nA

loss

Zero Gate Voltage Drain Current

-10

itA

-1

mA

(Notes 1 and 2)

VGS = 0, 10 = -2mA

V
mV/oC

VGS = Vos ' 10 = -2mA
VGS = VDS ' 10 = -2mA
VGS = ±20V, Vos = 0
VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Rating
TA = 125°C

ON-State Drain Current

10(ON)

-100
-200

30

Static Drain-to-Source
ON-State Resistance

ROS(ON)

22

0.75

Change in ROS(ON) with Temperature

CISS

Input Capacitance

75

130

Coss

Common Source Output Capacitance

50

75

CRSS
tdON

Reverse Transfer Capacitance

10

20

Turn-ON Delay Time

10

tr

Rise Time

10

td(OFF)

Turn-OFF Delay Time

20

~

Fall Time

15

Vso

Diode Forward Voltage Drop
Reverse Recovery Time

1.8

trr

%/OC

VGS = -5V, 10 = -100mA
VGS = -10V, 10 = -100mA
VGs =-10A,1 0 =-100mA

mO

VO" = -25V, 10 = -100mA

pF

VGS = 0, Vos = 25V
f= 1 MHz

ns

Voo = -25V
10 = -100mA
Rs=50n

V
ns

VGS = 0, Iso = -50mA
VGS = 0, Iso = -50mA

n
30

t.ROS(ON)
GFS

Forward Transconductance

VGS = -5V, Vos = -25V
VGS = -10V, Vos = -25V

mA

-300

50

300

Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300!1S pulse. 2% duty cycle.)
Not. 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

I----PULSE---i

i

t(OFF)

GENERATOR

1
1
1

Output

1

v-~~--~~

1

--------J

1

10%

1

i'"

L.. _ _ _ _ _ _ _ _ _ _ 1

9-44

I

I-~-OSCOPE

D.U.T.

VP06E

Typical Performance Curves
Output Characteristics

Saturation Characteristics

-1.0

-0.5

-0.4
-10V

\/ i"""

-0.1
(i)

~

~~

"-

i~
~~
j~

E

~

..9

-0.01

-0.001

'"

-10

f!1CI)
E

-7V

,

-0.3

~

-0.2

~

..9

-6V

-4V

-20

-30

-40

~

V

l/

-10V

-6V

-5V

",.

~~

-0.1

-5V

V
o

(i)

-BV

"-

-

#~

-9V

/

l/

-4V

/

-50

-4

-2

VOS (volts)

-6

-10

-8

Vos (volts)

Transconductance VS. Drain Current

Power Dissipation VS. Case Temperature

1.0

50
TO-220

r\.

Vos = -25V

,

O.B
(i)

c:
CI)

0.6

~
(/J

TA = 25°C

~

TA = 125°C

a.

/

0.4

.!.

I 11/

(!)

c

r~

0.2

"I"'"

TA = -55°C

II ~

E
CI)
"-

40

;I"

30

20

~

10

I

TO-39

-0.2

-0.4

-0.6

-O.B

25

-1.0

50

10 (amperes)
Maximum Rated Safe Operating Area

125

"

150

Thermal Response Characteristics

'0
CI)

TO-92 (pulsed)
1 ..... 1 ....

-TO-39

I

-0.1

I

(~C)

I II

TO-220

-

-

E
0

~

O.B

.s
UJ

~
~

-0.01

.!::!

1\

~

E

~

(~C)

'iii

,~

-TO-92 (~C)

"-

..9

100

r'\.

1.0

= .....
f!1CI)

75

Tc(°C)

-1.0

(i)

" "-

0
Z

0.6

Ui

0.4

~
en

~

UJ

a:

..J

«

"-

:::!E

a:

I'

0.2

UJ

::I::
f-

-0.001
-1

-10

-100

0.001

-1000

0.01

0.1

tp (milliseconds)

VOS (volts)

9-45

10

VP06E

BVoss Variation with Temperature

On-Resistance vs. Drain Current
50

1.1

./

'0
(I)
'iii

.s

./

1.0

C/)
C/)

CI

>
aJ

~

~

VGS =-5V

40

,,/

.!::!

E
0

,
(jj'

E

.r:.

".

VGS = -10V
30

,g.

~

Z

./

~

CI

.",

20

a:

10
0.9

o

·50

50

100

-0.2

150

-0.4

Ti(OC)
Transfer Characteristics
-1.0

~

.£I

~

'iii

E
0
.s

If~ "'~

-0.4

""

C/)

.J

I. V ~
~~

2

"...-

/
" V (th)

i

./

'iii

E

~l /

" . V-I 'i'o...

.....

0.9

1.0

,
......... "......

o

4

10

6

o

-50

100

150

VGS (volts)
Gate Drive Dynamic Characteristics

Capacitance vs. Drain-to-Source Voltage

vV

-10

200

f=lMHz

/ 1/
LL

Vos = -10V
-8

150
(jj'

I

100

~

i

CISS

j

-6

~
C/)

.J

c..>

50

\

-4

Coss

90 pF
-2

"

o

Vos = -40V

j

V /250 pF
/ V
LL ./

10

20

30

/

If

CRss
40

0.5

1.0

1.5

QG (nanocoulombs)

Vos (volts)

9-46

2.0

2.5

~

j

0.8

~V
o

1.0

:2

.hII' V

-0.2

1.1

.!::!

)/f~

-0.6

(I)

2.0

'0 =100mA/

7"~

E

-1.0

lL'

1.2

q

A.,"f"

a.

-0.8

V(th) and Ros Variation with Temperature

I~

VOS = -25V
-0.8

(jj'
~

-0.6

10 (amperes)

IIl1
"-11 §upertex inc.

VP0808
VP1008

P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss I
BVOGS

ROSION)
(max)

JOlON)
(min)

Order Number I Package
TO-39

TO-92

-80V

5f.!

-UA

VP0808B

VP0808L

-100V

5f.!

-1.1A

VP1008B

VP1008L

Features

Advanced DMOS Technology

D Freedom from secondary breakdown

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

D Low power drive requirement
D Ease of paralleling
D Low CISS and fast switching speeds
D Excellent thermal stability
D Integral Source-Drain diode

D Complementary N- and P-Channel devices

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications

Package Options

D High input impedance and high gain

(Note 1)

D Motor control
D Converters

D Amplifiers
D Switches
D Power supply circuits

i

D Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

TO·39

TO·92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±40V

Operating and Storage Temperature
Note 1:

Soldering Temperature'
'Dlstance of 1.6 mm from case for 10 seconds.

9-47

See Package Outline section for discrete pinouts.

..
I
I

,

VP0808/vP1008

Thermal Characteristics
Package

'0 (continuous)' .

10 (pulsed)

OJ.

Power Olssipation

°Je
°CIW

°C/W

TO-39

-O.BBA

-3A

6.2SW

170

20

TO-92

-0.21A

-3A

OAW

312.S

41

*10 (conlinuous) is limiled by max raled TI'

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

BVDSS

Drain-to-Source
Breakdown Voltage

VGS(th)

Gate Threshold Voltage

Min
VP100B

VPOBOB

TYP

Max

-100

(Notes 1 and 2)

Unit

Conditions

V

ID = -1O",A, VGS = 0

-4.S

V

VGS = VDS, ID = -1mA

nA

~BO

-2

IGSS

Gate Body Leakage

100

IDSS

Zero Gate Voltage Drain Current

-10

VGS = 30V, VDS = 0
VGS = OV, VDS = Max Rating

I--VGS = OV, VDS = Max Rating
-SOO

",A
TA = 12S'C

ID(ON)

ON-State Drain Current

RDS(ON)

Static Drail1-to-Source

-1.1

A

n

ON-State Resistance
GFS

Forward Transconductance

CISS

Input Capacitance

COSS

Common Source Output Capacitance

VGS = -10V, VDS .. 2 VDS(ON)

S
200

VGS = -10V, ID = -1A
mU

VDS .. 2 VDS(ON), ID = -O.SA

1S0
60

CRSS

Reverse Transler Capacitance

2S

td(ON)

Turn-ON Delay Time

10

Ir

Rise Time

10

td(OFF)

Turn-OFF Delay Time

10

pF

VGS = 0, VDS = 2SV
1= 1MHz

VDD = -2SV, ID = -O.SA
ns

tf

Fall Time

VSD

Diode Forward Voltage Drop

RS =

son

10
VP1008

1.2

VPOBOB

1.2

V

ISD = 0.21A, VGS = 0
ISD = 0.9A, VGS = 0

Note I: All D.C. parameters 100% tesled at 25'C unless otherwise stated. (Pulse test: 300~s pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

r - ;;L-;; --,

INPUT

I
I
I

OUTPUT

GENERATOR

I

\~I~+-~~

I

:
I
IL _____ JI
9-48

1-....,.,,---0 SCOPE
O.U.T.

VP11A

"§upertex inc.
P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss I
BV DGS

Order Number I Package

ROSION)

IOION)

(max)

(min)

TO-3

TO-39

TO-220

DICE

-60V

20

-5A

VP1106N1

VP1106N2

VP1106N5

VP1106ND

-100V

20

-5A

VP1110N1

VP1110N2

VP1110N5

VP1110ND

Features

Advanced DMOS Technology

D Freedom from secondary breakdown

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures.
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

D Low power drive requirement
D Ease of paralleling

D Low Crss and fast switching speeds
D Excellent thermal stability
D Integral Source-Drain diode

D Complementary N- and P-Channel devices

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

Applications

Package Options

D High input impedance and high gain

(Notes 1 and 2)

D Motor control
D Convertors
D Amplifiers
D Switches
D Power supply circuits
D Driver (Relays. Hammers. Solenoids. Lamps.
Memories, Displays, Bipolar Transistors. etc.)

TO·39

Absolute Maximum Ratings
TO·220

Drain-to-Source Voltage

TO·3

Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature

Note t : See Package Outline section for discrete pinouts.
Note 2: See Array section for quad pinouts.

Soldering Temperature"
"Distance of t.6 mm from case for 10 seconds.

9-49

_

VP11A

Thermal Characteristics
Package

ID

(continuous)"

ID

, Power bi~sipatlon

{pullied)*"

~tc~~5°C

°ja

Ole

°CIW

°CIW

IDR

IDRM

"

TO-3

-6.0A

-15A

75W

50

1.66

-6A

-15A

TO-39

-1.5A

-7A

6W

125

20.8

-1.5A

-7A

TO-220

-4.0A

-12A

45W

70

2.78

-4A

-12A

:

• Ie (continuous) is limited by max rated Tr

Electrical Characteristics
Symbol
BVess

Min

I VP111.0

I VP1106

Gate Threshold Voltage

IGSS

Gate Body Leakage

less

Zero Gate Voltage Drain Current

ON-Slale Drain Currenl

ReS(ON)

Slatic Drain-Io-Source
ON-Slale Resislance

Tye

Max

Unit

-1 00.

V

-SO
,1.5.

Change in VGS(th) with Temperature

le(ON)

(Notes 1 and 2)

...

Parameter
Drain-to-Source
Breakdown Voltage

VGS(th)
!!.VGS(th)

!!.Res(ON)
GFS

(@ 25°C un.... otherwise specified)

-3.5
~4.0

..

V
mV/OC

-100

nA

-50

~

-5

rnA

-1.0

~

Change in ReS(ON) with -,:em~erature

ri.~

Forward Transconductance

2

5

1.5

2

0.7

1.0

Input Capacitance

300

350

Coss
CRSS

Common Source Output Capacitance

100

150

Reverse Transfer Capacitance

20

35

tdON

Turn-ON Delay Time

35

40

Ir

Rise Time

20

30

td(OFF)

Turn-OFF Delay Time

40

50

~
Vse
trr

Fall Time

..

10

20

Diode Forward Vollage Drop

-1.4

-2.5

Reverse Recovery Time

400

Ie = -5mA, VGS = 0
VGS = Ves ' Ie = -5mA
Ie = -5mA, VGS = Ves
VGS = ±20V, Ves = 0
VGS = 0, Ves = Max Rating
VGS = 0, Ves = 0.8 Max Rating
TA = 125°C

A

VGS = -5V, Ves = -25V
VGs =-10V, Ves =-25V

n

VGS = -5V, Ie = -0.5A
VGS = -1 OV, Ie = -2.0A

%/oC

Ie = -1.0A, VGs= -10V

U

Ves = -25V, Ie = -2.0A

pF

VGS = 0, Ves = -20V
f= 1 MHz

ns

Vee = -18V
Ie = -2.0A
Rs= 50n

1.3

CISS

Conditions

V
ns

Ise = -1.0A, VGS = 0
Ise = -1.0A, VGS = 0

Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300~s "ulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

I--'~~JSCOPE

D.U.T.
td(ON)
Output _ _ _ _

~

10%

VP11A

Typical Performance Curves
Saturation Characteristics

Output Characteristics
-10

:-5

I

-8


'"

til
:;;
:r:

.,/

3

vGS=

Z
0

~

V

2

10J
.1.

II

.L

..-

/

a:

~

0.9

o

-50

50
TJ

100

o

150

~OSI= 25~

-4

I

/
II II /
I

/ VV

9
-1

o

~
o

j

0:

J{"C

N

/

1.4

0

6

0.9

§
>'"

10'=-1~""", V-

,........... I"'...

:J


4

V

2

o

-

~VOS=40V

BOOpF

~ :,/

i270PF

"--..
o

VV

eRSS
10

20

30

o

40

VOS (VOLTS)

V
o

2

3

QG (NANOeOULOM8S)

9-52

4

5

4
"-1J §upertex inc.

VP11C

P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BV DSS I
BVDGS

Order Number I Package

RDS(ON)

ID(ON)

(max)

(min)

T()"3

TO-39

-160V

SO

-1.SA

VP1116N1

VP1116N2

VP1116NS

VP1116ND

-200V

SO

-1.SA

VP1120N1

VP1120N2

VP1120NS

VP1120ND

TO-220

DICE

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C ISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications

Package Options

o
o

Motor control

o
o
o

Amplifiers

o

Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

(Notes 1 and 2)

Convertors

Switches
Power supply circuits
TO·39

Absolute Maximum Ratings
Drain-to-Source Voltage

TO-220

BV DSS

TO-3

Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature"

±20V
-SSOC to +1S0°C

Note 1:
Note 2:

300°C

*Oistance of 1.6 mm from case for 10 seconds.

9-S3

See Package Outline section for discrete pinouts.
See Array section for quad pinouts.

VPllC

Thermal Characteristics
Package

ID (continuOus)"

ID (pulsed)"

Power Dissipation

(lIB

(lIe

@Tc=2SoC

°CIW

°CIW

IDR

IDitU"

TO-3

-2.5A

-7.5A

75W

50

I.S

-2.5A

-7.5A

TO-39

-0.8A

-3A

SW

125

20.8

-0.8A

-3A

TO-220

-1.8A

-7A

45W

70

2.7

-1.8A

-7A

• 10 (continuous) is limited by max rated Tr

Electrical Characteristics
Symbol

Parameter

VGS(th)
tNaS(lh)

Gate Threshold Voltage

lass

Gate Body Leakage

Min

I VP1120

Drain-to-Source
Breakdown Voltage

BVoss

(@ 25°C unless otherwise specified)

I VPlllS

Typ

-3.5
-3.5

Change in VaS(lh) with Temperature

Zero Gate Voltage Drain Current
ON-State Drain Current

ROS(ON)

Unit

0.5

1.5

1.5

4

-S

V
mV/oC

Vas = Vos' 10 = -5mA
10 = -5mA, Vas = Vos

nA

Vas = ±20V, Vos = 0

-50

IlA

Vas = 0, Vos = Max Rating

-10

mA

Vas = 0, Vos = 0.8 Max Rating
TA = 125°C
Vas = -5V, Vos = -25V

A

3.3

7

3

5

Change in ROS(ON) with Temperature

0.8

1.2

aROS(ON)
GFS

Forward Transconductance

CISS
Coss

300

350

Common Source Output Capacitance

SO

80

CRSS

Reverse Transfer Capacitance

10

25

to(ON)
t,

Turn-ON Delay Time

8

25

Rise Time

4

20

td OFF

Turn-OFF Delay Time

~
VSD

Fall Time

trr

Input Capacitance

10= -5mA, VGS = 0

-100

Static Drain-to-Source
ON-State Resistance

0.5

Conditions

V

-ISO
-1.5

loss

10(ON)

Max

-200

(Notes 1 and 2)

40

8

20

Diode Forward Voltage Drop

-1.2

-2.0

Reverse Recovery Time

350

Vas = -5V, 10 = -0.5A

0

Vas = -10V, 10 = -1.0A
%/oC

10 = -1.0A, Vas = -10V

U

Vos = -25V, 10 = -1.0A

pF

Vas = 0, Vos = -25V
f=1 MHz

ns

Voo= -25V
10 = -1.0A
Rs =500

V

Iso = -1.0A, Vas = 0

ns

Iso = -1.0A, Vas = 0

0.75

24

Vas = -10V, Vos = -25V

Note 1: All D.C. parameters 100% tested at 25"C unless otherwise stated. (Pulse test: 300~s pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

,----PULsE---i
:

t(OFF)

I
1
1

td(ON)
Output

GENERATOR

,

v-~~--~~

1

------.J

,

1

10%

:.,.
1
__________1
~

9-54

f--~--
co

/"

0.95

0.90

16

/'

Ci

V

Gs

VGS

:;;

:c

Q

12

0

~

./

8

ex:

4

o

50

0

150

100

J

,.et.
o

./

1.5

3.0

TI- -shoeJIf

~f

/
J

3

Cl.

II
il.
II. /

:;;

2

9

o

./
2

,.

4

,

/

UJ
N

:J
<0:
:;;
ex:

~

~

~
Ul

8

--- ----

0.6

10

o

-50

50

300

U

~
u

150

V~S = ~lOt /

8

~

o

Cl

/

/

500Pi/v.l

~
...J

CISS_

1\"-

1'o

117V

VV-

6

0

~
Ul

l?

~

20

30

-l..tV

/250 pF

o II

eRSS

10

V

2

COSS

40V - f---

VV

4

>

40

o

2

3

QG (NANOeOULOMBS)

VOS (VOLTS)

9-56

4

Z

Q

Ul

0.6

0.2
150

100

I

450

ex:

--

10
f =MHz

.<0:
u.
0

1.0

Gate Drive Dynamic Characteristics

Capacitance Vs_ Drain-to-Source Voltage
600

<0:

0

TJ ('C)

VGS (VOLTS)

0

UJ

:J
<0:
:;;
ex:

;;::

.,./

~

Cl
N

1.4

./

1.0

0.8

1.8

/

K(th)

l?

>

,L

/

1.2

0

/

6

1lOJ1A

1.4

Ci

)5;e' -

I /

UJ

~2

,

A-

4

;;;

7.5

6.0

1~

VOS = 25V

o

4.5

V(th) and RDS Variation with Temperature

Transfer Characteristics

~

V

lOS (AMPERES)

5

ex:

/'

~

TJ ('e)

~

= 10V

/

Z

V
-50

J ll5)

;;;

/'

/'

i./

f--

5

a:

VP12A

(J) §upertex inc.
P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVDSS I
BV DGS

Order Number I Package

RDS(ON)

ID(ON)

(max)

(min)

T0-3

TO-39
VP1204N2

TO-220
VP1204N5

DICE

-40V

0.8n

-SA

VP1204Nl

VP1204ND

-SOY

0.8n

-SA

VP120SNl

VP120SN2

VP120SN5

VP120SND

-100V

0.8n

-SA

VP12l0Nl

VP12l0N2

VP12l0N5

VP12l0ND

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway' and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C ISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o

Convertors

o
o

Switches

o
o

Package Options

(Notes 1 and 2)

Motor control

Amplifiers

nr

Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

~,~ ~

Absolute Maximum Ratings
Drain-to-Source Voltage

TO·3

Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature*

±20V
-55°C to + 150°C

Note t : Sae Package Outline section for discrete pinouts.
Nota 2: Sea Array section for quad pinouts.

300°C

*Distance of t.6 mm from case for to seconds.

9-57

VP12A

Thermal Characteristics
.:Package

ID

(continuous)"

ID

(pulsed)"

Power Dissipation
@Tc=2SoC

6)1

6)C

°C/W

°CfW

IDRy"

IDR

TO-3

-7.0A

-14A

100W

30

1.25

-7A

-14A

TO-39

·2.5A

-11A

6.5W

125

20

-2.5A

-11A

TO-220

-5.OA

-14A

45W

70

2.75

-5A

-14A

• 10 (continuous) is limited by max rated Tr

Electrical Characteristics
Symbol
BVoss

(@ 25°C unless otherwise specified)
Min

Parameter
Drain-to-Source
Breakdown Voltage

VP1210

-100

VP1206

-60

VP1204

-40
-1.5

Typ

Max

Unit

Conditions

V
-3.5

10 = -10mA, VGS = 0

V
mV/oC

VGSth

Gate Threshold Voltage

8VGSIthi

Change in VGS(thl with Temperature

-4.7

-5.5

IGSS

Gate Body Leakage

-1.0

-100

nA

loss

Zero Gate Voltage Drain Current

-100

j.lA

-10

mA

(Notes 1 and 2)

VGS = Vos ' 10 = -10mA
10 = -10mA, VGS = Vos
VGS = ±20V, Vos = 0
VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Rating
TA = 125°C

10(ON)

ON-State Drain Current

-1.5

-2.0

-6.0

-12.0

Static Drain-to-Source
ON-State Resistance

1.0

1.4

0.5

0.8

8R OS(ON)
GFS

Change in ROS(ON) with Temperature

1.0

1.5

CISS
Coss

Input Capacitance

550

650

Common Source Output Capacitance

250

275
40

ROS(ON)

Forward Transconductance

1

VGS = -5V, Vos = -25V
VGS = -10V, Vos= -25V
VGS = -5V, 10 = -1A

A
0

tJ

Vos = -25V, 10 = -3A

pF

VGS = 0; Vos = -25V
f= 1 MHz

ns

Voo = -25V
10=-4A
Rs =500

V

Iso = -SA, Vas = 0

ns

Iso = -1A, VGS = 0

2

CRSS

Reverse Transfer Capacitance

25

td(ON)
tr

Turn-ON Delay Time

10

30

Rise Time

17

40

td(OFF)

Turn-OFF Delay Time

70

105

~
Vso

Fall Time

35

60

Diode Forward Voltage Drop

-1.2

-1.6

t"

Reverse Recovery Time

500

VGS = -10V, 10 -.3A
10 = -10A, VGS = -10V

%IOC

Note 1: All D.C. parameters 100% tested at 25'C unless othelWlse stated. (Pulse test: 300llS pulse. 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit
'----puLSE---l
:

t(ON)
td(ON)
OUlput _ _ _ _

I
I
I
I
I

tr

~

10%

10%

GENERATOR

I
\~~~~~~~

I
I
-:L
_________
-'I

9-58

1---+'"<--0 SCOPE
D.U.T.

VP12A

Typical Performance Curves
Saturation Characteristics

Output Characteristics

iii
w
a:

-20

-10

-16

-8

/

w
0::;

5
9

I/~

-L;;;

If~ V-

-8

r

0
-10

-20

-30

-6

//.

~V
A~ "...

-4

'ItV

-2

-40

0

-50

o

Transconductance Vs. Drain Current

4V

-4

-2

TO-3

VDS =-25V

w

/'
~V

w

iii

'"

1.6

LL

C)

0.8

o

I

-8

TA = ·55°C

,,-

~

25°C

!

125·C

Cl

~

'\

I'\.

'\

60

-

'\.

TO-220

40

.......

0-

...J,

'\

~

20

I

...............

-4

-6

-8

-10

0

'\
~

25

50

ID (AMPERES)

Maximum Rated Safe Operating Area

I

r--...... '\.

TO-39

-2

~~I

'\.

0

o

-10

[\.

80

3.2

::;

-6

Power Dissipation Vs. Case Temperature
100

2.4

6V

VDS (VOLTS)

4.0

2

'--

10-

Y

VDS (VOLTS)

iii

-

-

~

-

"'

V

1'",. / '

,.4 ~

=0

4v_

V

o

5
9

civ~
I

h I'

w
Q.
::;

I

!. V
/J

-4

iii
w
a:

I

V

/. VI
V -8V'"

h

VGS=-10V

I/~

-12

VGS = -},ov;.

75
100
TC ("C)

125

150

Thermal Response Characteristics
1.0

-100

0

w

N

::;

TO-220(PULSED)

iii
w
a:

-10

F~=+R
~:
TD-3(DC)

w
0::;

TDtO(IDT

5
9

TO-39(DC)

==
"-

-1.0

TD-3(PULSED)

LIMITED

''''~t(;f

w

.~

-10

0.6

(J

~~d'~

18~ ~~DSSI
-1.0

0

~

""'I",,~/

'"

0.8

a:

~~::$J

I"
-0.1
-0.1

«
::;

2

~

'"

iii
w

0.4

a:

-'
«
::;

0.2

a:

w

~

J:
f-

0
0.001

-100

0.01

0.1
tp (SECON OS)

VDS (VOLTS)
Pulse Condition: 300"., 2% dutycycle.

9-59

1.0

10

VP12A

ON- Resistance Vs. Drain Current

BVDSS Variation with Temperature

5
~

1.1

~V

W

N

«
a:

0

1.0

~
rn
rn
0

>


r-o
o

~
..J

-40

VOS (VOLTS)

/

/

-40V

"
1000pF

/

480pF

II
o

-2

-4

-6

-8

OG (NANOCOULOMBS)

9-60

«
a:

100

50

VGS (VOLTS)

N

:::i
:;:

r........

0.8

-8

1;8

/""

,/

>

~

-4

-2

h
~ 'l

1.1

«
:;:

V2~oC

9

-15

-10

VP12C

"§upertex inc.
P-Channel Enhancement-Mode
Vertical CMOS Power FETs
Ordering Information
BV DSS I
BV OGS

Order Number I Package

RDS(ON)

ID(ON)

(max)

(min)

TO-3

TO-39

TO-220

DICE

-160V

2.50

-4.0A

VP1216N1

VP1216N2

VP1216N5

VP1216ND

-200V

2.50

-4.0A

VP1220N1

VP1220N2

VP1220N5

VP1220ND

Features

Advanced CMOS Technology

o
o
o
o

Freedom from secondary breakdown

o
o
o
o

Excellent thermal stability

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Package Options

Applications
o
o
o
o
o
o

(Notes 1 and 2)

Motor control
Convertors
Amplifiers
Switches
Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps.
Memories, Displays, Bipolar Transistors, etc.)

TO·3S

Absolute Maximum Ratings
Drain-to-Source Voltage

BV DSS

Drain-to-Gate Voltage

BV DGS

TO·220

Gate-to-Source Voltage
Operating and Storage Temperature

TO·3

± 20V
-55°C to +150°C

Note 1:

Soldering Temperature>

Note 2:

*Oistance of 1.6 mm from case for 10 seconds.

9-61

See Package Outline section for discrete pinouts.
See Array section for quad pinouts.

._
..

'

VP12C

Thermal Characteristics
package

ID (continuous)·

I~ (pulsetl)·

lI _

i

Power Dissipation
@Tc=25°C

lila

°CIW

°CIW

IDR

IDAM•

TO-3

-4.5A

-8.0A

100W

30

1.25

-4.5A

-8.0A

TO-39

-2.0A

-4.5A

6.5W

125

20

-2.0A

-4.5A

TO-220

-3.5A

-6.0A

45W

70

2.75

-3.5A

-6.0A

• 10 (continuous) is limited by max rated Tj.

Electrical Characteristics (@ 25°C unless otherwise specified)
Symbol
BVoss
VGSlth)
/'NGS(th)

Parameter

Min

I VP1220
I VP1216

Drain-to-Source
Breakdown Voltage
Gate Threshold Voltage

Typ

-3.5

IGSS
loss

Zero Gate Voltage Drain Current

-1.0

ROS(ON)
aROS(ON)

ON-State Drain Current

Unit

-.0.5

-1.0

-4.0

-7.0

V
mV/oC

-100

nA

VGS = ±20V, Vos = 0

-100

j.lA

VGS = 0, Vos = Max Rating

-10

mA

2.0

4.0

1.6

2.5

Change in RosJoNJwith Temperature

0.5

1.0

0.8

GFS

Forward Transconductance

CISS
Coss

Input Capacitance

600

650

Common Source Output Capacitance

200

250

CRSS
tdON

Reverse Transfer CapaCitance

20

30

Turn-ON Delay Time

30

40

tr

Rise Time

26

35

td(OFF)

Turn-OFF Delay Time

45

90

4

Fall Time

20

40

Vso

Diode Forward Voltage Drop

-1.4

-2.0

trr

Reverse Recovery Time

500

All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse test:

Note 2:

All A.C. parameters sample tested.

VGS = Vos ' 10 = -10mA
VGS = Vos ' 10 = -10mA

VGS = 0, Vos = 0.8 Max Rating
TA = 125°C

A

VGS = -5V, Vos = -25V
VGs =-10V, Vos =-25V

0

VGS = -5V, 10 = -0.5A

%IOC

VGs =-10V,l o =-1.0A
10 = -1A, VGS = -10V

U

Vos = -25V, 10 = -3.0A

pF

VGS = 0, Vos = -25V
f=1 MHz

ns

Voo =-15V
10 = -2.0A
Rs =500

V

Iso = -0.5A, VGS = 0

ns

Iso = -0.5A, VGS = 0

1.2

300~s

10 = -10mA, VGS = 0

-3.5
-4.5

Static Drain-to-Source
ON-State Resistance

Note 1:

Conditions

V

-160
-1.5

Change in VGS(lh) with Temperature
Gate Body Leakage

10(ON)

Max

-200

(Notes 1 and 2)

pulse, 2% duty cycle.)

Switching Waveforms and Test Circuit

puLSE ---,

1---t(ON)

i

t(OFF)

GENERATOR

I
I
I
I
I
I

td(ON)
Output _ _ _ _ _-.I
10%

I

v-~~--~~

i ' " ______II
~----

9-62

~"'<--o SCOPE

D.U.T.

VP12C

Typical Performance Curves
Saturation Characteristics

Output Characteristics
-10

-5.0

JGS~-11v ..
/.

/~

-5

j--VGS = -1IOV

J.....--' ~

j

I

....
~

-2.5

1.

1-

4v_

II'
o

-25
VOS (VOLTS)

~ t:/

o

-50

I~

~ ..-

-4V_

o

Power Dissipation Vs. Case Temperature
100

VOS = -25V

'\.

TO-3

"I'\.

1.5

"

Z

w

w

§

'\.

TA = -55°C

1.3

1.1

/
'/

0.9

/

(I)

u.

(!1

-10

-5

1.7

:;;:

1250

50 ITO-220,

b

"\

'\.
'- '\

...........

1125°b

I

........... '\.

TO-39

~

o
0

-9

-3
-6
10 (AMPERES)

o
w

,

~

~

"

:;;:
~

-0.1

)j

71

'I\.

II
II

a:
o

,

~,-~~

0..

~

'1"'~

,

~

w
z

U

1"\
,
"

~

(I)

ffi
a:
«

:;;:
a:
w
:r

"

LIMITED
BY BVOSS

-1

-10

-100

I-

-1000

./

o
0.001

.-""

------

V

.......

0.01

45W-J /
/ II

9-63

/

/TO-39
TC=25°CPo -5W

0.1

tp. (SECONDS)

VOS (VOLTS)
Pulse Condition: 300,..5.2% dutycycle.

II I

TO-220
Tc = 25°C
Po =

0.5

...J

o

150

1.0

:J
«
:;;:

-~)<~

-1

125

N

'~I)Q ,Q,y,9.7,0~"'Ot:

w
a:
w

75
100
TC ("C)

Thermal Response Characteristics

-10

l°.:2':0J!'!;!~~01. -I..

50

25

Maximum Rated Safe Operating Area

u;

-6V

Vas (VOLTS)

Transconductance Vs. Drain Current

u;

~

~~ V l- I-./. ~ ~
~

~
~

-r~

Y
o

w
~

Jv-

~

l.d ~

u;
w
a:

10

VP12C

ON-Resistance Vs. Drain Current

BVDSS Variation with Temperature
7.5

aw

1.2

t/

N

::i

«
:;

1.1

a:

0

~

'"~

1.0

>
til

/

/

0.9

V

V

JGS l_5~

/
Iii
:;

1/

J:

2
Z

J

4.5

V

0

~

a:

3.0

1.5

o
o

-50

-

)
~

/

0.8

50

100

150

o

-1.5

TJ tC)

TA = -S;,'CI

/

a:

w
0..
:;

J.

-3

'I

)

aw

IV

::i

«
:;

-2

-4

1.1

......

~

:2

,,
illih)

......

0

1.0

>'"

~


co

V

:;
:J:

2
Z

60

f§

40

0

a:

---

20

o

o

-50

V
~

50

150

100

o

0.2

0.4

V(thl and RDS Variation with Temperature

Transfer Characteristics
-1.0

2.0

Vos =-25V

IO=-250mA0
1.2

~ .lss,tJ
/I,

-0.8

C

A

-O.S

//

w
:;

5
9

w

N

.11.1 25°C

0..

.., ,

-0.2

0

o

-2

1.1

:J
<
:;

d~

a:

// ./
~ '/

-0.4

1.0

0.8

0.6

IDS (AMPERES)

TJ ("C)

a:

r7

V

)--

0.9

Ui
w

!

lGs 1 lJV- f - -

Ui

./

V

~

V

U
'VGS =5V
.1

80

V

1

I

1.1

~V
~

~7

"""'v........

(th)

0
~

1.0

~
iii
(.!l

0.9 ~

"""

",

>

l/

~

~2mA-

:;

a:

0.8

"'" .........

0

0.4

o
-S

-4

-8

o

-50

-10

50

150

100

TJ ("C)

Gate Drive Dynamic Characteristics
-10

7

Vos = -10VY

V
- 8

~

rl

<
a:

1/ 7

- 6

2:

en

(.!l

V

-4

>

1/"'"

- 2

0
-20

-30

40pF

J

~ i-"

II

0.1

0.2

0.3

0.4

QG (NANOCOULOMBS)

VOS (VOLTS)

9-68

-

J 25pF

o

-40

J

J

0

~
u

j

~40V

7

..J

<
u.
o
u

z
Z

f§

..........

0.8

Capacitance Vs. Drain-to-Source Voltage

-10

a

w

N

1.2 :J
<
0

...........

........

VGS (VOLTS)

o

1.6

0.5

a:

VP13C

"

!iupertex inc.
P-Channel Enhancement-Mode
Vertical DMOS Power FETs

Ordering Information
Order Number / Package

BVoss /
BVoos

ROS(ON)

(max)

(min)

TO-39

TO-92

-160V

lOOn

-100mA

VP1316N2

VP1316N3

-200V

loon

-100mA

VP1320N2

VP1320N3

jOlON)

Features

Advanced DMOS Technology

o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

o
o
o
o

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o

Motor control

o
o
o
o

Amplifiers

Package Options

(Note I)

Convertors

Switches
Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)
TO-39

i

TO·92

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Note 1:

Soldering Temperature'
*Distance of 1.6 mm from case for 10 seconds.

9-69

See Package Outline section for discrete pinouts.

~:;

VP13C

Thermal Characteristics
Package

10 (continuous)·

10 (pulskl)·

Power Dissipation

6,c
°C/W

6'8
°C/W

@Tc=2SoC

.

IDA

lOAM

TO-39

-0.10A

-0.40A

3.0W

125

41

-O.IA

-0.4A

TO-92

-O.OSA

-0.30A

0.8W

170

155

-O.OSA

-0.3A

* 10 (continuous) is limited by max rated Tr

Electrical Characteristics (@ 25°C unless otherwise specified)
Parameter

Symbol
BVoss

Min

l VP1320

Drain-to-Source
Breakdown Voltage

I VP131S

Gate Threshold Voltage

VGS(lh)
INGS(lh)

Gate Body Leakage

loss

Zero Gate Voltage Drain Current

Max

-4.0

-5.0

-3.5

V
mV/oC

0.1

100

nA

-

10(ON)

10 = -1 mA, VGS = 0
VGS = VOS ' 10 = -lmA
VGS = VOS ' 10 = -lmA
VGS = ±20V, Vos = 0
VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Rating

-10
~

-500
ON-State Drain Current

Conditions

Unit
V

-ISO
-1.5

Change in VGS(lh) with Temperature

IGSS

Typ

-200

(Notes 1 and 2)

TA = 12SoC

-50

-100

mA

-100

-400

mA

VGS = -SV, Vos = -25V
VGs =-10V, Vos =-25V

Static Drain-to-Source
ON-State Resistance

65

100

n

VGS = -SV, 10 = -40mA

60

100

n

aROS(ON)

Change in ROS(ON) with Temperature

0.6

1.0

%/oC

VGS = -10V, 10 = -150mA
10 = -SOmA, VGs= -10V

GFS
CISS

Input Capacitance

35

40

Coss
CRSS

Common Source Output Capacitance

10

15

2

5

td(ON}

Turn-ON Delay Time

1.5

5

tT

Rise Time

2.5

5

tdOFF

Turn-OFF Delay Time

I.S

S

tf

Fall Time

2.S

S

1.6

2.0

ROS(ON)

Forward Transconductance

20

Reverse Transfer Capacitance

Vso

Diode Forward Voltage Drop

tTT

Reverse Recovery Time

mU

Vos = -25V, 10 = -150A

pF

VGS = 0, Vos = -25V
f= 1 MHz

ns

Voo = -2SV
10= -200mA
Rs= 50n

30

V

Iso = -lA, VGS = 0
ISD = -lA, VGS = 0

ns

3S0

Note 1: All D.C. parameters 100% tesled at 25°C unless otherwise stated. (Pulse test: 3DOI's pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

Input

1----puLSE---l

i

10%
I(ON)

I(OFF)

GENERATOR

I
I

Output

I
V-~~--~~

I
I

-----.I

I
I

10%

I.".

L:... _________II

9-70

f-~----

V

0.94

I-""
50

V

/'
~

50

100

VDS

I--

150

0

0.1

1.2

w

V·

N

-0.2

V
VV V

I. . '
,, l25°C

w

11.

::.

-1.0

/

.L.
-2

U

0
~

~
>

1.0

0.9

.....

-8

-10

"

§

«
c::
«
u..

\

f = 1 MHz

"-

u
12.5

o

o

'"

~

-6

>'"
(!1

-4

150

1/

-2
CRSS

0
40

Vas (VOLTS)

=

~10J'l

~~

J

COSS-

30

"-.......

l/: v-'OpF

~

20

.......

XA

oJ

10

.......

/ i/-40V
70P F:""-:[7

0

"'~

0

U

§;

vo1

-8

~15Pi
o

.1

.2

.3

.4

QG (NANOCOULOMBS)

9-72

g
~

100

CISS

~

c::

-10

1\

26

'" "'

Gate Drive Dynamic Characteristics

Capacitance Vs. Drain·to·Source Voltage

37.6

c::

1

50
TJ (oC)

VGS (VOLTS)

50

:J

«
::.

o

o

-50

Cl

w

N

/'

. /~

V

/

/"

0.8

/

-6

t'-...

:c

/ '/ V
h/

-4

1.1

:J

«
::.
c::

10 = 50m~ , /

~(th)

C

-~

, 26°(;
-0.3

o

0.5

'2

TA =.SsoC,

o

0.4

V(th) and RDS Variation with Temperature

,

9

0.3

0.2

lOS (AMPERES)

= -25V

-0.4

~

i"

0

o

Transfer Characteristics

c::

I--

V

TJ tC)

rnw

111
~

I

100

c::

0.90
-50

-0.5

VGS =

U

)

Cl

enCl

I I II

150

Z

/~
0.98

vJs

rn:<

V

::J

«

200

V

II

II
=~t

.5

I

Alphanumeric Index and Ordering Information

.,

Company Profile

. .:

Application Notes
Static Handling Procedures and Quality Assurance
Process Flow
DMOS Product Family

"I
•

•.

..
,.

N· and p. Channel Low Threshold MOSFETs

..

DMOS Discretes N-Channel

..

DMOS Discretes P-Channel

..

DMOS Arrays and Special Functions

'nM~

HVCMOS High Voltage ICs

,.

CMOS Consumer/Industrial Products

~.

Lead Bend Options and Surface Mount Packages

_j

Package Outlines

~

Representatives/Distributors

,.:.

"§upertex inc.
MOSFET Array Selector Guide
Low Voltage N-Channel
Device
No.1

ChannelslType

BVoss
Min (V)

Max(n)

VN0104

4N

40

3

VN010S

4N

SO

3

Number of

ROS(ON)

Plastic Dip

Ceramic Dip

•
•

•

•

•
•
•
•

•

•

•
•

•
•
•

Max(n)

Plastic Dip

Ceramic Dip

•
•
•
•

•
•

•

•

Plastic Dip

Ceramic Dip

•

•
•

VN0204

4N

40

2

VN020S

4N

SO

2

TNOS04

4N

40

0.75

TNOSOS

4N

SO

1.5

VN210S

4N

SO

3

VN2110

4N

100

3

VQ1000

4N

SO

5.5

VQ1001

4N

SO

1

VQ1004

4N

SO

3.5

Note 1:

Package Options
SOW-20
C"ramicLCC

•

Die

•
•
•
•

•

•
•
•

•

•
•

•
•
•

Excluding package suffix.

Low Voltage P-Channel
Device
NO.1

Number of
BVoss
Channels/Type Min (V)

VP0104

4P

40

8

VP010S

4P

SO

8

VP0204

4P

40

4

VP020S

4P

SO

4

TPOS04

4P

40

2

TPOSOS

4P

SO

3.5

Note 1:

Package Options

RDS(ON)

SOW-20

Ceramic LCC

•

•
•

•

•

Die

•

•

•
•

Excluding package suffix.

Low Voltage Complementary
Device
NO.1

Number of
BVoss
ChannelslType Min (V)

ROS(ON)

TCOS04

2N +2P

40

Max(n)
2.752

VC010S

2N+2P

SO

11.02

VC020S

2N +2P

SO

S.02

TQ3001

2N +2P

40

3.02

VQ3001

2N+2P

40

3.02

VQ7254

2N +2P

20

3.02

Note 1:
Note 2:

•
•
•
•

•

•
•

Excluding package suffix.
One N·channel plus one P·channel.

10·1

Package Options
SOW-20
Ceramic LCC

Die

•
•

•
•

•

•
•
•
•

"§upertex inc.
MOSFET Array Selector Guide
High Voltage 2
Device
No.'

Number of
ChannelslType

BV DSS
Min (V)

Max(Q)

Plastic Dip

Ceramic Dip

AN0120
AN0130
AN0140
AP0120
AP0130
AP0140

8N
8N
8N
8P
8P
8P

200
300
400
200
300
400

300
300
350
600
600
700

•

•

Note' :
Note 2:

RDS(ON)

Excluding package suffix.
Monolithic 8 Channel Array.

Package Options
SOW-20
Ceramic LCC

•

•
•
•
•
•

•

Ole

•
•
•
•
•
•

•

•
•
•

•

High Voltage Low Leakage 2,3
Device
No.'

AN0116
AN0132
AP0116
AP0132
Note 1:
Note 2:
Note 3:

BVDSS
Number of
ChannelsIType Min (V)

8N
8N
8P
8P

Package Options

ROS(ON)

Max(Q)

Plastic Dip

Ceramic Dip

SOW-20

350
350
700
700

•
•

•

•

160
320
160
320

Excluding package suffix.
Monolithic 8 Channel Array.
Low loss Leakage (refer to data sheet for details).

Ole

•
•
•
•

•
•
•

•
•
•

•
•

Ceramic LCC

High Voltage Level Translators
Device
No.'

Number of
Channels

Vpp
Max (V)

ISOURCE

ISINK

Min (mAj

Min (mA)

Plastic Dip

HT0130
HT02402

8
1

300
400

0.2
300

0.1
300

•
•

Note' : Excluding package suffix.
Note 2: Available September 1988.

10-2

Package Options
Ceramic Dip
SOW-20 CeramicLCC

•
•

•

•

Die

•
•

AN01

"

!iupertex inc.
8 Channel Power MOSFET Array
Monolithic N-channel Enchancement Mode

Ordering Information
BVOS~
BV DGS
(min)
160V
200V
300V
320V
400V

ROS(ON)
(max)
350(1
300(1
300(1
350(1
350(1

10(ON)
(min)

loss··@Vos=
100V Max

25mA
25mA
25mA
25mA
25mA

1nA

10ss··@Vos=
250V Max

18-Lead
Ceramic DIP

-

-

1nA

AN0116NB
AN0120NB
AN0130NB
AN0132NB

-

AN0140NB

-

-

Order Number / Package
Plastic
18-Lead
Plastic DIP
SOW-20·
AN0116NA
AN0116WG

Die

AN0120NA
AN0130NA
AN0132NA

AN0132WG

AN0116ND
AN0120ND
AN0130ND
AN0132ND

AN0140NA

AN0140WG

AN0140ND

-

·Same as 50-20 with 300 mil wide body.

**Average current per channel, measured with all eight channels connected in parallel.

Features

General Description

D

Low drain to source leakage for AN0116 and AN0132

D

200-volt to 400-volt capability

The Supertex AN01 series of high voltage arrays is designed to
provide the interface between MOS logic and loads requiring high
voltages and intermediate currents. Each circuit consists of eight
channels in a common-source configuration with open drains.
This design minimizes the number of package leads needed.

D

Interfaces directly to CMOS logic

D

8 independent channels

D

Low crosstalk between channels

D

Low power dissipation

D

Pin compatible with industry standard driver array

D

Freedom from secondary breakdown

The AN0116 and AN0132 are ideally suited for low leakage/high
impedance measurement, providing excellent accuracy and
resolution for Automatic Test Equipment.

Applications
D

High impedance/low leakage measurements for Bare Board
Testers

D

High voltage piezoelectric transducer drivers

D

High voltage electroluminescent panel drivers

D

High voltage electrostatic array drivers

D

General multi-channel driver array

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

Operating and Storage Temperature
Soldering Temperature"
Channel-to-Channel Crosstalk

10mVN

·Oistance of 1.6 mm from case for 10 seconds.

10-3

"n.,

ANOl

Thermal Characteristics
Package

10 (continuous)'

10 (pulsed)'

Power Dissipation

1:1/0

I:I/e

@Tc=25°C

°C/W

°CIW

,

lOR

10RM

18 lead plastic

30mA

75mA

1.5W

135

83

30mA

75mA

18 lead ceramic

40mA

75mA

2.0W

85

62

40mA

75mA

ID (continuous)

IS

limited by max rated Tj'

Electrical Characteristics
Symbol
BVOSS

(@ 25°C unless otherwise specified)

Parameter
Orain-to-Source
Breakdown Voltage

Min
ANOl16
AN0120
AN0130
AN0132
AN0140

VGS(th)

Gate Threshold Voltage

LNGS(th)

Change in VGS(th) with Temperature

IGSS

Gate Body Leakage

Zero Gate Voltage
Orain Current

lOSS

Typ

Max

160
200
300
320
400
2

5
-3.5

Unit

10

ON-State Orain Current
SIalic Drain-Io-Source
ON-Slale Resislance

100!,A, VGS

~

OV

V

VGS

~

VOS, 10

~

lmA

VGS

~

VOS, 10

~

lmA

~

AN0120
AN0130
AN0140

10

nA

VGS

±20V, VOS

~

0

ANOl16
AN0132

1

nA

VGS ~ ±20V, VOS
(Nole3)

~

0

1

!,A

VGS

1

mA

VGS ~ 0, VOS = 0.8 Max Rating
TA = 125°C

1

nA

VGS = 0, VOS = 100V
(NOle3)

1

mA

VGS = 0, VOS = 0.8 Max Rating
TA = 125°C

1

nA

VGS = 0, VOS = 250V
(Nole3)

1

mA

VGS = 0, VOS = 0.8 Max Rating
TA = 125°C

mA

VGS = 1OV, VOS = 25V

AN0120
AN0130
AN0140

25

~

0, VOS

~

Max Rating

AN0120
AN0130

300

n

ANOl16
AN0132
AN0140

350

n

VGS = 10V, 10 = 10mA

0.8

%/oC

VGS = 1OV, 10 = 10mA

8.0

ma

10 = 10mA, 6VGS = 1V

pF

VOS = 25V, VGS = 0
f = 1 MHz

ns

VOS = 25V
10 = 10mA
50n drive, VGS(ON) =10V

V

VGS = 0, ISO = 50mA

6ROS(ON)

Change in ROS(ON) with Temperature

GFS

Forward Transconductance

CISS

Input Capacitance

5.0

7.5

COSS

Common Source Output Capacitance

3.0

5.0

CRSS

Reverse Transfer Capacitance

0.8

1.5

td(ON)

Turn-ON Oelay Time

3

tr

Rise Time

3

td(OFF)

Turn-OFF Oelay Time

5

tf

Fall Time

3

VSO

Oiode Forward Voltage Orop

Note 1:
Note 2:
Note 3:

~

mV/oC

AN0132

ROS(ON)

Conditions

V

AN0116

10(ON)

(NOles 1, 2 and 3)

4.0

1.3

All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300ms pulse, 2% duty cycle.)
All A.C. parameters sample tested.
?
Average current per channel, measured with all 8 channels connected in parallel.

10-4

VGS = 10V, 10 = 10mA

ANOl

Switching Waveforms and Test Circuit

INPUT
t(ON)

r - ;;;L-;; --,

t(OFF)

I

td(ON)
OUTPUT

tr

I

td(OFF) tf

GENERATOR

I
I

10%

I

I-Do.--OSCOPE

V-~I~~-+~

D.U_T.

I

I

I
I
L _____ J

-=

Typical Performance Curves
Saturation Characteristics

Output Characteristics
75

. / i--"""

w

a:
w

:;;

45

...J

30

I
0

:;;

6V

:J

15V

~

~~

15

w
a:
w

Q.

30

«

11'/

~

ii)

7V

;; ~

:J

~

I

40

Isv

~ :;...---

«

VGS = 10V

IgV

/ V .....
/. 0 ~

ii)
Q.

VGS -10V

80 fl"ec Pulse Test

60

50

...J

4V

#

20

~

4V
10

3V
0

o

10

20
30
VDS (VOLTS)

40

0

50

2

s

4
6
VDS (VOLTS)

10

Power Dissipation Vs. Case Temperature

Transconductance Vs. Drain Current

(For one channel)

20

250

16

200

ii)

-55'C

zw

:;;

w

iii
:J

12

r

en

~

'\

'"'" "

"\. CERAMIC

'\

150

:J

...J

~

~

I

~

...J

25°C

S

~

100

II.

Q.

~

125°C
50

4

o

o

20

40

60

so

0
100

ID (MILLIAMPERES)

10-5

~~

PLASTlC"- ~

C

t!)

1'-.

o

25

50

75
100
TC ('C)

~

125

"

150

AN01

Maximum Rated Safe Operating Area
~

iii
w
a:

Thermal Response Characteristics

(One channel DC)

100

1001'.

r-- C~FlAMiC'(PULSED)

N

"'4.!.. ~ '--

~

10

cw
:::;

«
:;:

w

~

:.so"? :"\.

~C'

«

w

.;/,
T

...J

~

AN0120

i""-t'

AN0130

r--

z

i:!:
(J)

iii
w

10

Po =250mW

0.4

1/

V

...J

«
:;:

0.2

,., .,;

a:

w
J:

f-

100

1000

o
.001

.01

0.1

10

tp (SECONDS)

ON-Resistance Vs. Gate-to-Source Voltage

BVoss Variation with Temperature
1000

,I

\\

1.2

C

./

w

N

./'

:::;

«
:;:

0

V

CERAMIC

VDS (VOLTS)

a:

I

TA =25°C

a:

fN0114~

o

-

0.6

U

~

:::;

0

-

o

:;:

e

0.8

a:

,,~

Q.

1.0

\\.

'"

"'~ r---I- r-r-1-0.

./

1.0

100

AN0140
AN01301
AN0120

I

.,./'

~

. / '"

(J)
(J)

Cl

>
III

VDSjO.li
0.8
10

o

-50

100

50

1.0

150

100

10
VGS (VOLTS)

TJ tC)

V(thl and ROS Variation with Temperature

Transfer Characteristics
100
1.2

-55°C.1

iii
w
a:

80

«

60

w
Q.
:;:

/1" . . .
/25

...J

e

N

JC

;'

h V '"

a:

'"

0
~

~

125°C

Cij

~Y

20

t.:l

o

2

6

8

o

w
N

:::;

«
:!l

a:

1

./' ........... 1-0.
~

Vth
.........
VGS =VDS

IDilm~

-50

10

o

10-6

Z

o

~
a:

r-.....
o

50
TJ (oC)

VGS (VOLTS)

o

C

................

0.8

VDS =25V

4

/

.......... V

1.0

>

~~

....'f'

['..1-0.

0.9

2

~/
/;'

1.1

:::;

«
:!l

V.

40

o

w

II"

:::;

:iii

C

JDs(dn)
ID= lOrnA

/

100

150

AN01

Gate Drive Dynamic Characteristics

Capacitance Vs. Drain-to·Source Voltage
10.0

10

f = lMHz
vGS =0

8

7.5

en
c
~

a:
~

5.0

VOS=20~

\.

0

~
u

2.5

~
CI)

/ /

6

j;

4

~~

COSS

2

"-

o
o

..J

o

'----

Ii..

U

~

CISS

~~

/

~

~

,;'

/

1 5pF

CRSS

o
10

20

30

40

VOS (VOLTS)

o

0.1

.05

0.15

0.2

QG (NANOCOULOMBS)

Pin Configuration and Schematic

top view

SOW-20

top view

18-pin DIP

10-7

0.25

AP01

"§upertex inc.
I

8 Channel Power MOSFET Array
Monolithic P-channel Enchancement Mode
Ordering Information
BVf)SS/
BVOGS
(min)
-160V
-200V
-300V
-320V
-400V

ROS(ON)
(max)
700n
600n
600n
700n
700n

10(ON)
(min)
-1SmA
-1SmA
-1SmA
-1SmA
-1SmA

1f)SS·· @ Vos = 10ss··@Vos=
·250V Max
·100VMax
-1.SnA
-

-

-

-1.SnA

-

18-Lead
Ceramic DIP
AP0116NB
AP0120NB
AP0130NB
AP0132NB
AP0140NB

Order Number / Package
Plastic
18-Lead
Plastic DIP
SOW·20·
AP0116NA
AP0116WG
AP0120NA
AP0130NA
AP0132NA
AP0132WG
AP0140NA
AP0140WG

-

Ole
AP0116NI:)
AP0120ND
AP0130ND
AP0132ND
AP0140ND

• Same as SO-20 with 300 mil wide body.
** Average current per channel. measured with all eight channels connected in parallel.

Features

General Description

o
o
o
o
o
o
o
o

The Supertex AP01 series of high voltage arrays is designed to
provide the interface between MOS logic and loads requiring high
voltages and intermediate currents. Each circuit consists of eight
channels in a common-source configuration with open drains.
This design minimizes the number of package leads needed.

Low drain to source leakage for AP0116 and AP0132
200-volt to 400-volt capability
Interfaces directly to CMOS logic
8 independent channels

The AP0116 and AP0132 are ideally suited for low leakage/high
impedance measurement, providing excellent accuracy and
resolution for Automatic Test Equipment.

Low crosstalk between channels
Low power dissipation
Pin compatible with industry standard driver array
Freedom from secondary breakdown

Applications
o
o
o

High voltage electroluminescent panel drivers
High voltage electrostatic array drivers
General multi-channel driver array

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

±20V

·Operating and Storage Temperature
Soldering Temperature"
Channel-to-Channel Crosstalk

10mVN

"Distance of t.6 mm from case for to seconds.

10-8

AP01

Thermal Characteristics
Package

10 (continuous)*

10 (pulsed)*

18 lead plastic

-15mA

-40mA

18 lead Ceramic

-15mA

-40mA

* 10 (continuous) IS limited by max rated

BVDSS

Bic
°C/W

1.5W

135

83

-15mA

-40mA

62

-15mA

-40mA

2.0W

85

(@ 25°C unless otherwise specified)

Parameter
Drain-to-Source
Breakdown Voltage

Min
APOl16
AP0120
AP0130
AP0132
AP0140

VGS(th)

Gate Threshold Voltage

6VGS(th)

Change in VGS(th) with Temperature

IGSS

Gate Body Leakage

Zero Gate Voltage
Orain Current

lOSS

10RM*

Bi•
°C/W

lOR

@Tc=25°C

Tr

Electrical Characteristics
Symbol

Power Dissipation

Typ

Max

-160
-200
-300
-320
-400

Unit

V

-2

-5
-3.5

(Notes 1, 2 and 3)
Conditions

10 = -100J.lA, VGS = OV

V

VGS = VOS, 10 = -lmA

mV/oC

VGS = VOS, 10 = -lmA

AP0120
AP0130
AP0140

-10

nA

VGS = ±20V, VOS = 0

AP0116
AP0132

-1

nA

VGS = ±20V, VOS = 0
(Note 3)

AP0120
AP0130
AP0140

-1

p.A

VGS = 0, VOS = Max Rating

-1

mA

VGS = 0, VOS = 0.8 Max Rating
TA = 125°C

-1.5

nA

VGS = 0, VOS = -100V
(Note 3)

-1

mA

VGS = 0, VOS = 0.8 Max Rating
TA = 125°C

-1.5

nA

VGS = 0, VOS = -250V
(Note 3)

-1

mA

VGS = 0, VOS = 0.8 Max Rating
TA = 125°C

AP0116

AP0132

10(ON)

ON-State Orain Current

mA

VGS = -10V, VOS = -25V

ROS(ON)

Static Orain-to-Source

AP0120
AP0130

-15
600

n

VGS = -10V, 10 = -10mA

ON-State Resistance

AP0116
AP0132
AP0140

700

n

VGS = -IOV, 10 = -lOmA

0.8

%/oC

VGS = -10V, 10 = -10mA

5.0

m1J

VOS = -25V, 10 = -5mA

pF

VOS = -25V, VGS = 0
f = 1 MHz

ns

VOS = -25V
10 = -10mA
RS = 50n, VGS(ON)=-10V

V

VGS = 0, ISO = -25mA

6ROS(ON)

Change in ROS(ON) with Temperature

GFS

Forward Transconductance

CISS

Input Capacitance

5.0

7.5

COSS

Common Source Output Capacitance

3.0

5.0

CRSS

Reverse Transfer Capacitance

1.0

2.0

td(ON)

Turn-ON Oelay Time

3

t,

Rise Time

3

td(OFF)

Turn-OFF Delay Time

5

tf

Fall Time

3

VSO

Oiode Forward Voltage Orop

Note 1:
Note 2:
Note 3:

3.0

1.5

All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300ms pulse, 2% duty cycle.)
All A.C. parameters sample tested.
Average current per channel, measured with all 8 channels connected in parallel.

10-9

"It ,

APOl

Switching Waveforms and Test Circuit

r - ;;:;L;; --,

INPUT

I

GENERATOR

I
I

OUTPUT

I

"""''"''r--OSCOPE

\r-I~+-~+4

D.U.T.

I

I
I
L _____ J -=

I

I
Typical Performance Curves

Saturation Characteristics

Output Characteristics
-50

-20

-40

-16

en

(j)

a:
UJ
a.
:;

a:
UJ
a.

UJ

-30

V GS =-10V.

:::i

§
E

1/' -9
~ /' -8

UJ


co

./

0.9

V

8

:2

lL

V

0

3

:t:

8

'81000

f"

,..

~

enCl

. . . r----- VDS=-O.lV

a:

./
0.8

10

ON-Resistance Vs_ Gate-to-Source Voltage

1.2

§

0.1

t p [SECONDS]

VDS (VOLTS)

V

AP01201
AP0130

0.7

o

-50

100

100
-1.0

150

!

-10

-100

VGS (VOLTS)

Transfer Characteristics

V(th) an!! RDS Variation with Temperature

-30

2.0

1

VDS = 25V

V

TA = ·55'C

-24

'"'
m
w
a:
w
a. -18

)

:2

..:

~
.P

-12

~

-6

1/

N

-2

-

::::;

1.1

0

1.0

3
'"'
:5

150°C

en

li L
-6

/'
RDS

<
:2
a:

. / V-

./

I--

0.9

L

V"

V

V(th)

V

1.6

>

1.2

-

-10

vGS (VOLTS)

o

50
T J (OC)

10-11

100

a:

3
0.8

Z
0

0.4

-50

-'
..:
:2
0

-

0.8

-8

8w
~

(!)

...l.L

1£
-4

ID =10mA

8w

L 25°C
.If ./
I ,. A'"

::::;
-'

1.2

o

150

enCl

a:

APOl

Capacitan~e Vs. Drain-to·Source Voltage

Gate Drive Dynamic Characteristics

8

(i)

6

0

«
a:
«
LL
0

4

-10

-"-..

--

~

/

-8

CISS

(i)
I-

-'
0

COSS-

0

-6

'I

2:
en

&



0

2

-2
CRSS

-30

-20

-10

I
/

0

-40

V V
J /
V

~

5pF

.03

.01

.05

.07

QG (NANOCOULOMBS)

Pin Configuration and Schematic
G1

°1

°1
NC

°2

°2

G2

VOS =40V

If

VOS (VOLTS)

G1

/

V DS =10V,

°3

°3

G3

°4

°4

G4

°5

°5

G5

Os

Gs

°7

°6
°7
NC

G7

Gs

top view

SOW-20

top view

18-pin DIP

10-12

.09

HT01

,,§Upertex inc.
a-Channel Logic To High-Voltage
Level Translator
Ordering Information
Part Number/Package

.

20 Lead CERDIP

I

20 Lead Plastic DIP

HT0130D

I

HT0130P

I
. I

20 Terminal Ceramic LCC

I

Plastic SOW-20·

HT0130LC

I

HT0130WG

'

I Die in waffle pack

I

HT0130X

Same as 50-20 0,300 mil wide body,

Features

General Description

D Operating voltage up to 300V

The Supertex HT01 a-channel Level Translator is designed to
implement the necessary level translation between logic level
signals and voltage swings required to drive high-voltage PChannel MOSFET transistors_ This device is intended to provide
gate drive signals to devices such as the Supertex AP01 pChannel MOSFET Array in applications requiring active pull-up to
a high-voltage (V pp) line of up to 300 volts. Logic input can be from
5 volts to 15 volts and is referenced to the logic supply (VDD)'

D 5V to 15V logic input capability
D

Output swings be,low GND if required

D Drives high-voltage P-Channel MOS from logic level signal
D Surface mount packaging available
D No "floating logic" required

When an input is switched to 4.2 volts below the VDD supply, the
corresponding output will typically switch from Vpp to V pp -14 volts.
If the Vpp supply remains above 12 volts, the negative supply
(VNN ) would be connected to system ground (GND). If variations
of the V pp supply level require the P-Channel MOSFET gate drive
to swing below GND in order to turn on, connect the VNN pin to a
negative supply of up to -15 volts. The logic inputs can remain
between Voo and system ground (GND) and still provide correct
operation.

D a independent channels

Applications
D ATE systems

D Printers/plotters
D

P-Channel MOSFET control

In an OFF condition, the HT01 is a low power device. In an ON
condition, each channel will dissipate power determined by the
Vpp and VNNvoltage. Internal power disSipation must be considered when the application requires that more than one channel be
active at one time, especially at h!gher Vpp voltage values.

Absolute Maximum Ratings 1,2
Supply voltage, V DD

VNN - 0.3V to +161(

Supply Voltage, Vpp

VNN - 0.3V to + 300V
-16Vto 0.3V

Supply Voltage, VNN
Logic inputs levels

Y'N

VNN - 0.3V to VDO + 0.3V

~~--------~--~~-7~~-

VOUTPUT

lOUT -

DC per Channel

Continuous total power dissipation2
Operating temperature range
Storage temperature range

Vpp + 0.3V max

30mA
700mW
O°C to 70°C
-65°C to + 150°C

Note 1:

All voltages are referenced to chip ground,

Note 2:

For operation above 25°C ambient derate lineraly to 85°C at 8mW/oC,

10-13

"

'"

"'''',L,

:""

HT01

",,' -:'

ElectricatCharacteristics(over
recQmi!jendedoperating cond~iohsunress
'.
.
..... ,."
.. noted)
'.

, " ,

DC Characteristics
,
Symbol

'"

100

'Par.meter
VDO Supply Current

Ipp

Vpp Supply Current

INN

VNN Supply Current

ISOURCE

Output current

ISINK
VON

,

,",

.......

-

"

'"

'"''

Min" :,:'+,:

..

','

lyp

",

0.6
0.4

VOFF
Vz

Max
0.001
3.50
0.001
1.0
0.001
4.50

'Units
mA
mA
mA
mA
mA
mA
I1A

" Conditions
All OFF
1 ch ON, no load
All OFF
1 ch ON, no load
All OFF
1 ch ON, no load
'Capacitive load
Capacitive load

135

1.0
200

Output current

66

100

Output voltage

Ypp -17

Vpp -10

I1A
V

Vpp -17

Vpp -12.5

V
V

Output voltage

Vpp - 0.5

Zener voltage

11

14

17

V

Min

Typ

Max

Units

Voo =4.75V
Voo = 15V

,.

Output to Vpp

AC Characteristics
Symbol

Parameter

tON

Turn on time, any channel

5

Ll.tON

Variation in tON'
any 2 channels

5

tOFF

Turn off time, any channel

3

Ll.tOFF

Variation in tOFF '
any 2 channels

5

Conditions

I1S
%

Voo = 10V, VNN = GND

I1S
%

Voo = 10V, VNN = GND

Voo = 10V, VNN = GND

Voo = 10V, VNN = GND

Recommended Operating Conditions
Symbol
voo

Min
4.75

Parameter
Logic supply voltage

vpp

Positive high voltage supply

VNN
VIH

Negative supply

VNN + 12
-15

High-level input voltage

VIL

TA

Typ

Max
15

Units
V

275

V

0

V

Voo -1.2

Voo

V

Low-level input voltage

0

Voo - 4.2

V

Operating free-air temperature

0

+70

°C

Function Table
Input Condition

Output Stage

High level

Vpp

Low level

Vpp - Vz

10-14

HT01

Functional Block Diagram
Vpp

1

VDD

SOURCE
CONTROL

LOGIC LEVEL
INPUT

OUTPUT

INPUT
LOGIC

SINK
CONTROL

(

(One of eight channels within the HT01)

Switching Waveforms and Test Circuit
VPPZOOV

.~'~
o VOLTS

10FF

t-'ON

INPUT

----I

OUTPUT
Vpp-Vz - - - - GNDJL

(One of eight channels within the HT01)

10-15

TEST POINT

HT01

Pin Configuration

02

03

04
bottom view

top view

20-pin LCC

20-pin DIP/SOW-20

10-16

05

Os

"

TC0604WG
Surface Mount

§upertex inc.

Preliminary

Complementary Enhancement-Mode
Vertical DMOS Power FETs Quad Array
Ordering Information

.

Max

Order Number' Package

BVDSS '
BVDGS

Q, + Q 2 or Q 3 + Q 4

SOW-20'

40V

2.75Q

TC0604WG

RDS(DN)

Same as 50-20 with 300 mil wide body.

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

4 independent channels
4 electrically isolated die
Commercial and Military versions available
Freedom from secondary breakdown
Low power drive requirement
Low C,SS and fast switching speeds

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high Input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Electrical Characteristics

Motor control

Refer to TNOSL and TPOSL Data Sheets for detailed characteristics of N- and P-channel devices.

Convertors
Amplifiers

Pin Configuration

Switches
Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

Thermal Characteristics
Package

Plastic
SOW-20

10 continuous
& IDA (single die)

N-Channel

1.0A

P-Channel

O.SA

10 pulsed'
& 10AM+

N-Channel

4.0A

P-Channel

Power Dissipatio;' @ Tc = 25°C*

2.0A
1.5W

Sj' ("CIW)

85

SjC (OCIW)

top view

Pulse test 300 ~s pulse, 2% duty cycle.
t Total for package.

+

SOW-20

10-17

0) !iupertex inc.

TN0604WG
Surface Mount
Preliminary

N-Channel Enhancement-Mode
Vertical DMOS Power FETs Quad Array
Ordering Information
BVDSS 1
BVDGS

Order Num.ber I Package
RDS(ON)

40V

Max

SOW·20·

0.75Q

TN0604WG

'Same as SO·20 with 300 mil wide body.

Features

Advanced DMOS Technology

o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

4 independent channels
4 electrically isolated die
Commercial and Military versions available
Freedom from secondary breakdown
Low power drive requirement
Low C,ss and fast switching speeds

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain

Applications
o
o
o
o
o
o

Motor control

Electrical Characteristics

Convertors

Refer to TN06L Data Sheet for detailed characteristics.

Amplifiers

Pin Configuration

Switches
Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

Thermal Characteristics
Package

Plastic
SOW·20

10 continuous & lOR (single die)

1.0A

10 pulsed> & 10RM>

4.0A

Power Dissipation @ Tc = 25°C*
9ja (OC/W)

1.5W

9je (OC/W)

85

-

top view

SOW-20

+ Pulse test 300 ~S pulse, 2% duty cycle.

*Total for package.

10-18

"

TN0606N6
TN0606N7

§upertex inc.

I

N-Channel Enhancement-Mode
Vertical DMOS Power FETs Quad Array
Ordering Information
Order Number' Package

BVoss '
BV DGS

ROS(ON)

(max)

14-Pin P-Dip

60V

1.50

TN0606N6

I

I

14-Pin C-Dip·
TN0606N7

*14-pin Side Brazed Ceramic Dip.

Features

Advanced DMOS Technology

D 4 independent channels

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

D 4 electrically isolated die
D Commercial and Military versions available
D Freedom from secondary breakdown
D Low power drive requirement
D Low C,ss and fast switching speeds

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

D High input impedance and high gain

Applications
D Motor control

Electrical Characteristics

D Convertors

Refer to TN06A Data Sheet for detailed characteristics.

D Amplifiers
D Switches

Pin Configuration

D Power supply circuits
D Driver (Relays, Hammers, Solenoids, Lamps,
Memories. Displays, Bipolar Transistors. etc.)

Thermal Characteristics
Plastic
DIP

Ceramic
DIP

10 continuous & IDA (single die)

1.4A

1.60A

10 pulsed- & lOAM'

6.0A

6.0A

Package

Power Dissipation @ Tc = 25°C*
0ja
0je

(OCIW)
(OCIW)

3W

4W

83.3

62.5

top view

41.6

14-pin DIP

31.2

Pulse test 300 I1S pulse. 2% duty cycle.
t Total for package.

+

10-19

o

§upertex inc.

TP0604WG
Surface Mount
Preliminary

P-Channel Enhancement-Mode
Vertical DMOS Power FETs Quad Array
Ordering Information
BVoss I
BVoos

ROS(ON)

-40V

Max

2.0n

Order Number I Package
SOW·20·
TP0604WG

·Same as 50·20 with 300 mil wide body.

Features

Advanced DMOS Technology

o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures.
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

4 independent channels
4 electrically isolated die
Commercial and Military versions available
Freedom from secondary breakdown
Low power drive requirement
Low Crss and fast switching speeds

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage. high input impedance. low input capacitance. and
fast switching speeds are desired.

High input impedance and high gain

Applications
o
o
o
o
o
o

Motor control

Electrical Characteristics

Convertors

Refer to TP06L Data Sheet for detailed characteristics.

Amplifiers
Switches

Pin Configuration

Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors. etc.)

Thermal Characteristics
Package

Plastic
SOW·20

10 continuous & lOR (single die)

2.0A

10 pulsed' & 10RM+

0.6A

Power Dissipation @ Tc = 25°C*

1.5W

9ja (OC/W)

85

91e (OC/W)

-

top view

• Pulse test 300 ~S pulse, 2% duty cycle.
t Total for package.

SOW-20

10-20

"

TP0606N6
TP0606N7

!iupertex inc.

P-Channel Enhancement-Mode
Vertical DMOS Power FETs Quad Array
Ordering Information
BVossl
BVDGS

Order Number I Package

ROS(ON)

-60V

(max)

14-Pin P-Dlp

3.50

TP0606N6

I
I

14-Pln CoD/po
TP0606N7

"14-pin Side Brazed Ceramic Dip.

Features

Advanced DMOS Technology

D 4 independent channels

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

D 4 electrically isolated die
D

Commercial and Military versions available

D Freedom from secondary breakdown

D Low power drive requirement
D Low CISS and fast switching speeds

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

D High input impedance and high gain

Applications
D Motor control

Electrical Characteristics

D Convertors

Refer to TP06A Data Sheet for detailed characteristics.

D Amplifiers
D Switches

Pin Configuration

D Power supply circuits
D Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

Thermal Characteristics
Package
10 continuous & lOR (single die)
10 pulsed' & lOAM'

Plastic
DIP

Ceramic
DIP

O.65A

O.75A

3.5A

3.5A

3W

4W

0ja

(OCIW)

83.3

62.5

0je

(OCIW)

41.6

31.2

Power Dissipation @ Tc = 25°C*

top view

14-pin DIP

• Pulse leol300 IlS pulse, 2% duly cycle.
I Total lor pacl.VGSlth)

Change in VGSlth) with Temperature

IGSS

Gate Body Leakage

loss

Zero Gate Voltage Drain Current

-

Typ

Max

-3.0

-

Unit

ON-State Drain Current

VGS ; 0,1 0

VGS;V OS ' 10 ; 1.0mA
VGS ; V os ' 10 ; 1.0mA

2.5

V
mV/oC

100

nA

10
IlA

!>.RoSION)

100llA

VGS ; ±20V, VOS;

A

VGS ; 0, Vos; 0.8 Max Rating
VGS ; 5V, Vos; 25V
V GS ; 10V, Vos; 25V

7.5

Static Drain-to-Source
ON-State Resistance

s:s
0.6

1.1

G FS

Forward Transconductance

C ISS

Input Capacitance

60

Coss
C ASS

Common Source Output Capacitance

25

Reverse Transfer Capacitance

5

tdON

Turn-ON Delay Time

5

t,

Rise Time

5

tdIOFF)

Turn-OFF Delay Time

5

tt

Fall Time

Vso

Diode Forward Voltage Drop

trr

Reverse Recovery Time

n

VGS ; 5V, 10

0.2A

;

VGS ; 10V, 10

;

0.3A

%/oC

V GS ; 10V, 10 ; 0.3A

mU

Vos; 15V, 10 ; O.5A

pF

f; 1 MHz

100

VGS ; 0, Vos; 25\1

Voo; 15V
ns

10 ; 0.6A
Rs; 50n

5
-0.85

V

VGS ; 0, Iso; 0.5A

165

ns

VGS ; 0, Iso; 0.3A

Note 1:

All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300llS pulse, 2% duty cycle.)

Note 2:

All A.C. parameters sample tested.

10-35

a

T A ; 125°C

0.2

Change in ROSION) with Temperature

;

VGS ; 0, Vos; Max Rating

0.5
ROSION)

Conditions

V

-5.0

500
101ON)

(Notes 1 and 2)

VQ1000

Thermal Coupling and Effective Thermal Resistance
In multiple chip devices, coupling of heat between die occurs. The

Assuming equal thermal resistance for each die, equation (1)
simplifies to:

junction temperature can be calculated as follows:

(3)

<1.TJ1 = R01 P01 + R02 K02 P02 + R03 K93 P03 + R94 K94 P04 (1)
where <1.TJ1 is the change injunction temperature of die 1.
R01 thru 4 is the thermal resistance of die 1 through 4.
PD1 thru 4 is the power dissipated in die 1 through 4.
K02 thru 4 is the thermal coupling between die 1 and die 2

For conditions where P01 = P02 = P03 = P04' POT = 4P 0' equation
(3) can be further simplifed and, by substituting into equation (2),
results in:
RO(EFF) = R01 (1 + K02 + K03 + K04)/4
(4)
Values for the coupling factors when the ambient is used as a
reference are given in the previous table. If significant power is to
be dissipated in two die, die at the opposite ends of the package
should be used so that lowest position junction temperatures will
result.

through 4.
An effective package thermal resistance can be defined as
follows:
RO(EFF) = <1.TJ/P OT
where POT is the total package power dissipation.

(2)

Drain-Source Diode (trr - Reverse Recovery Time)
Reverse recovery time is measured using the circuit below.
Forward and reverse current IF and IR are equal and are tested at
the continuous and peak current ratings of the DMOS FET.

The internal drain-source diodes of DMOS Power FETs may be
used as catch diodes or free-wheeling diodes. Current ratings for
these diodes are the same as thecontnuous and peak drain
current ratings for the DMOS FET.

Switching Waveforms and Test Circuits
+30 V

D

D.U.T.
CURRENT PROBE ....[ ]

s
-30 V

TRR Test Waveforms

TRR Test Circuit

+15V

"n
v,

PULSE GENERATOR
HP:zt5AOR EQUIV.

r------,
I

I
I

TO
SAMPLING

~-r-2iiii;--. ._-+1:,::,,::,,::~:SCOPE

PULSE WIDTH

50niNPUT

va

I

VGS(on) =+ 10V

---Ih------_

INPUT
VGS(off)

Switching Time Test Circuit

VOSlofll----~.

OUTPUT

......::::.:.r

O%:::....._ _
VOSlonl _ _ _ _ _ _....::I..:9::.

Switching Time Test Waveform

10-36

VQ1000

Typical Performance Curves
Output Characteristics
1.0

...in:;;

',',

",/

0.8

,
I

«

i=
zw
cr:
cr:

..,
"

0.6

'11

::J
0
Z

«
cr:
9

v6s =17V

.

•

I

in

16V •

«

...:;;

9V
BV .....

O.B

zw
cr:

t;~

::J

f/

u

I

«
a:

0.4

I

0.2

Z

4V •

1

9

2V

a

50
10
20
30
40
VDS - DRAIN-SOURCE VOL TAGE(VOL TS)

...:;;in

O.B

cr:
cr:

2V_

a

2

z

I

0.2

9

«

t0

150

u
en

100

Z

«
cr:

/

tI

/

50

w

c;

V

a

a

2
4
B
10
6
VGS - GATE·TO·SOURCE VOL TAGE(VOLTS)

:;;

o

VDS = 10V
80/lS.1%

DUTY CYCLE
PULSE TEST
600
800
400
10 - DRAIN CURRENTlmA)

200

250
VDS - 25V
BO/lS,I%
DUTY CYCLE
PULSE TEST

0

:::i
-'
~

iii

1/

0

::J

a

VDS = 10V

-

/IS.

1%

DUTY CYCLE
PULSE TEST

iii
u

REDUCTION
DUETO
HEATING

z

«
t0

150

I

::J
0

0.1

I

i/

I

Z

z

0

0

«
cr:

0

en

100

I
II

Z

t-

...::Jt-

1/

::J

V

t-

/

I

50

i

en

a

00.01

l:'

80

:0
E 200

0

0
I

1000

Transconductance vs
Gate-Source Voltage

1.0

::c

z
~
0

-

I
I
I

Output Conductance vs
Drain Current

in

10

II

Z

0

II

0

8

J

::J
0

J

a

6

/

u

z

I
0.4

4

L ~

iii

0.6

«
cr:

3V "

1

I

I'

:0
E 200

I

0

I

~~

250

I

::J

t

Transconductance vs Drain
Current

I

«

i=
zw

~Vii

I'

//

VDS - DRAIN-SOURCE VOL TAGE(VOLTS)

,

VDS = 25V
BO /IS, 1%
DUTY CYCLE
PULSE TEST

6V -

1

I '/

Static
Transfer Characteristics
1.0

-

, '"

,~ ';'

0

I

.,

I,

tt~"
0.6

a:

15V •

-.. ,;'~~ 7V
~. ,:,

"

i=

:3V~

a

VGS=10~ .....

-

I

I

r;

0.2

o

-

r,lI"
V

0.4

a

I

-- - -

Saturation Characteristics
1.0

0.01

0.1
10 - DRAIN CURRENT(AMPS)

1.0

V
o

2

4

6

8

10

VGS - GATE·TO-SOURCE VOLTAGE(VOLTS)

10·37

VQ1000

Drain-to-Source ON Resistance
vs Gate-to-Source Voltage

Capacitance vs Drain-to-Source
Voltage
50
CISS

VOS=O.1V

40

\

u
Z

;:

~

30

\

U

«a..
«
u

20

I
U

10

o
100

10

VGS - GATE-TO-SOURCE VOLTAGE(VOLTS)

II'

I'l

/

1\

,

I

\

II
10

20

30

40

~

.......

f'..

\

\

o

-

"'" """
10

20

30

~OSS

r----

=

C~SS r----40

50

VOS - ORAIN-SOURCE VOLTAGE(VOLTS)

~

o

1

LLCo
iii

\

-

60

t - TlME(n.)

10-38

o §upertex inc.

VQ1001

N-Channel Enhancement-Mode
Vertical DMOS Power FETs Quad Array
Ordering Information
BVoss J
BVOGS

ROS(ON)
(max)

IOION)
(min)

30V

1.00

2.0A

Order Number J Package
Quad Ceramic DIP'
VQ1001P

'14-pin side-brazed ceramic DIP.

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thernial stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Pin Configuration

Motor control
Convertors
Amplifiers
Switches
Power supply circuits
Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)

Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage

top view

±40V

14-pin DIP

Operating and Storage Temperature
Soldering Temperature'
*Oistance of 1.6 mm from case for 10 seconds.

10-39

-

VQ100l

Thermal Characteristics

(TA :::25°C)

Test

Each Transistor

All Four Transistors

VQ1001P

VQ1001P

Unit

Total Power Oissipation

Watts

1.3

2.0

Linear Oerating Factor

mWI"C

10.4

9.6

'CfW

2S0

104

Thermal Resistance
Continuous Orain Current

A

.BS

Pulsed Orain Current

A

3.0

Electrical Characteristics
Symbol

(@ 25°C unless otherwise specified)

Parameter

BVOSS

Orain-to-Source
Breakdown Voltage

VGS(th)

Gate Threshold Voltage

IGSS

Gate Body Leakage

lOSS

Zero Gate Voltage Orain Current

1}tp

Min

Max

-

Conditions

Unit
V

VGS

=

0, 10

2.S

V

VGS

=

VOS 10

100

nA

VGS

=

±1SV, VOS

VGS

= 0,

VOS

=

Max Rating

VGS

= 0',

VOS

=

O.B Max Rating

30
O.B

10
f!.A
SOO

TA
ON-State Orain Current

10(ON)
ROS(ON)

2

A
1.7S

Static Drain-to-Source
ON-State Resistance

i--

Forward Transconductance

200

CISS

Input Capacitance

110

COSS

Common Source Output Capacitance

110

CRSS

Reverse Transfer Capacitance

3S

t(ON)

Turn-ON Time

30

VGS

mU

pF

Turn-OFF Time
Oiode Forward Voltage Orop

=

1mA

= 0'

12S'C

=

12V, VOS" 2VOS(ON)

=

SV, 10

= 0.2A

=

12V, 10

=

1.0A

VOS .. 2VOS(ON), 10

VGS

=

RS

=

0, VOS

= O.SA

=

1SV

=

.6A

1MHz

VOO

V

10 f!.A

VGS

f

30
-O.BS

=

VGS

ns
VSO

=

0

1

GFS

t(OFF)

(Notes 1 and 2)

=

=

VGS

1SV, 10

SOO

= 0,

ISO

=

1A

Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300",8 pulse, 2% duty cycle.)
Note 2:

All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

INPUT

f-43to,,.--o SCOPE
O.U.T:
OUTPUT

10-40

VQ1004

"§upertex inc.

N-Channel Enhancement-Mode
Vertical CMOS Power FETs Quad Array
Ordering Information
Order Number I Package

BVoss I
BVOGS

ROS(ON)
(max)

IO(ON)
(min)

Quad Ceramic DIP'

I

Quad Plastic DIP

60V

3.50

1.5A

VQ1004P

I

VQ1004J

*14-pin side-brazed ceramic DIP.

Features

Advanced DMOS Technology

o
o
o
o
o
o
o
o

These enhancement-mode (normally-off) power transistors utilize a vertical DMOS structure and Supertex's well-proven silicongate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermallyinduced secondary breakdown.

Freedom from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C 1SS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode

Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and
fast switching speeds are desired. .

High input impedance and high gain
Complementary N- and P-Channel devices

Applications
o
o
o
o
o
o

Pin Configuration

Motor control
Convertors
°1

°4

Switches

51

54

Power supply circuits

Gl

G4

Amplifiers

Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar TranSistors, etc.)
G2

5

G3

Absolute Maximum Ratings

52

6

53

Drain-to-Source Voltage

°2

7

°3

Drain-to-Gate Voltage
Gate-to-Source Voltage

top view

±40V

14-pin DIP

Operating and Storage Temperature
Soldering Temperature"
Distance of 1.6 mm from case for 10 seconds.

10-41

•

VQ1004

Thermal Characteristics

(TA = 25°C)
All Four Transistors

Each Tranaistor
Test

Unit
VQ1004P

VQ1004J

VQ1004P

VQ1004J

1.3

1.3

2.0

2.0

Total Power Dissipation

Walls

Linear Oerating Factor

mWrC

10.4

10.4

16

16

'CIW

96.2

96.2

62.5

62.5

Continuous Orain Current

A

.46

.46

Pulsed Orain Current

A

2.0

2.0

Thermal Resistance

Electrical Characteristics

(@ 25°C unless otherwise specified)

Parameter

Symbol

Typ

Min

BVOSS

Orain-to.-Source
Breakdown Voltage

VGS(\h)

Gate Threshold Voltage

IGSS

Gate Body Leakage

lOSS

Zero Gate Voltage Orain Current

Max

-

Conditiona

Unit
V

VGS = 0, 10 = 10 ...,A

2.5

V

VGS = Ves, 10 = 1mA

100

nA

VGS = ±15V, VOS = 0

60
O.B

1

VGS = 0, VOS = Max Rating
VGS

fLA
500

TA
10(ON)

ON-State Orain Current

ROS(ON)

Static Drain-Io-Source
ON-State Resistance

1.5

A

-

(Notes 1 and 2)

5

n

GFS
CISS

Input Capacitance

60

COSS

Common Source Output Capacitance

50

CRSS

Reverse Transler Capacitance

10

t(ON)

Turn-ON Time

10

t(OFF)

Turn-OFF Time

VSO

Diode Forward Voltage Orop

170

mU

= 0,

VOS

= O.B

= 10V, VOS '" 2
= 5V, 10 = 0.3A

VGS

=

10V, 10

=

VOS(ON)

1A

VOS '" 2VOS(ON), 10

pF

Max Rating

125'C

VGS

VGS

3.5

Forward Transconductance

=

= .5A

VGS = 0, VOS = 25V

~

1= 1MHz
VOO = 25V
10 = 1A

ns

10
0.9

RS =
V

son

VGS = O,ISO = 1A

Note 1: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse test: 300fLS pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

,

~

r-;;L-;--'

INPUT
,(ON)

,(OFF)

I
OUTPUT

10%

GENERATOR

I
I

I
I

I
I
I

I
I

I

L _____ J

10-42

SCOPE
D.U.T.

':'

':'

-=

Alphanumeric Index and Ordering Information
Company Profile
Application Notes

_f

..
~

~_'I

and Quality

DMOS
Threshold

DMOS
DMOS
DMOS

and ..... 'u"".... ,,'"
HVCMOS High Voltage ICs

Products
Packages

\1'.'

o

§upertex inc.
HVCMOS Selector Guide

High-Voltage Source/Sink Outputs (Push-Pull)
Device OutNumber puts

Logic Configuration

Output
Operating
Voltage

Output
Current

Similar
Devices

Per Channel

Applications

HV6810

10

Serial to parallel
converter wllatches

80V

+25mA
-4mA

TITL4810
Sprague UCN5810

Vacuum Fluorescent
display drivers

HV01

16

Grey shade driver with
16 analog levels

60V

±40mA

None

Video and grey shade
displays EL and LCD

HV08

24

Grey shade driver with
16 analog levels

70V

±40mA

None

Video and grey shade
displays EL and LCD

HV531
HV54

32

Serial to parallel converter
wllatches, output enable

80V

±20mA

*Siliconix SI 9553/9554
*TI SN75555/75556
*Sprague UCN5853/5854

EL column drivers and
non-impact printers
LCD Drivers

HV571
HV58

32

Serial to parallel converter
wllatches, polarity and
blanking

80V

±20mA

Siliconix SI9553/9554
TI SN75555/75556
Sprague UCN5853/5854

Non-impact printers
and plotters, EL
displays, LCD drivers

HV60

32

LCD driver w/active
return to ground

±40V

±15mA

None with return to
GND capability

High voltage LCD
displays

HV500

32

AC plasma driver with
multiplexed 8-bit shift
register

100V

±15mA

*TI SN75500/55500

AC plasma display
drivers, printer

HV501

32

Serial to parallel AC plasma
driver with shift register

100V

±15mA

*TI SN75501/55501

AC plasma display
drivers, printer

HV041
HV06

64

Serial to parallel converter
wllatches, polarity and
blanking

80V

±20mA

None

EL column drivers, nonimpact printers, LCD
displays

HV04HI
HV06H

64

Serial to parallel converter
wllatches, polarity and
blanking w/hotswitch
capability

80V

+20mA
-12mA

None

EL column drivers, nonimpact printers, LCD
displays

*Pin compatible direct replacement.

11-1

High-Voltag~

Sink Only Outputs (Open Drain N-Channel)

HV02

16

Serial to parallel converter

250V

HV51
HV52

32

Serial to parallel converter
w/output enable and strobe

220V

Current
Per
Channel
-250mA
-100mA

HV55
HV56

32

Serial to parallel converter
wllatches, polarity and
blanking

300V

-100mA

TI 75551175552
Siliconix Si9551/9552
Sprague UCN5851/5852

Non-impact printers/
plotters, EL row drivers

HV03
HV05

64

Serial to parallel converter
wllatches, Supertex logic

300V

-100mA

None

EL row drivers, nonimpact printers/plotters

HV30

8

7 segment decoder/driver

200V

-5mA

None

EL 7 segment displays

Device Out~ ..
Number puts

Output
Logic
Configuration

Output
Operating
Voltage

...

Direct
Competitive
Devices
None
·TI75551/75552
·Siliconix Si9551/9552
·Sprague UCN5851/5852

Applications
EL row driver
EL row driver, nonimpact printers/
plotters

·Pln compatible direct replacement

High-Voltage Source Only Outputs (Open Drain P-Channel)
Device OutNumber puts

Output
Operating
Voltage
-220V

Logic
Configuration

HV41
HV42

32

Serial to parallel converter
w/output enable and strobe

HV45
HV46

32

Serial to parallel converter
wllatches, polarity and
blanking

Output
Current Per
Channel

-300V

Similar
Devices

Applications

+80mA

Sharp

EL row drivers, nonimpact printers

+60mA

Sharp

Non-impact printers and
plotters, EL display row
drivers

High-Voltage Analog Switches

Dual SPST

Switch
Operating
Configuration
100V pop

Maximum
Switch
Resistance
100 ohms

MAX 341

High voltage switching, mil
electronics & insturmentation

HV343

Dual SPOT

100V Pop

100 ohms

MAX 343

High voltage switching, mil
electronics & instrumentation

HV345

Dual DPST

100V pop

100 ohms

MAX 345

High voltage switching, mil
electronics & instrumentation

HV348

Dual SPST

100V pop

55 ohms

MAX 348

High voltage switching, mil
electronics & instrumentation

Device
Number

Switches

HV341

Similar
Devices

'Appllcatlons

High-Voltage Bilateral Switches

HV10
HV17

4

Individual inputs
with/without latches

Maximum
Switch
Voltage
160V P-Supp
130V pop Sig

HV12-16
HV18

8

Shift register or decoders,
latches & chip selects

160V P-Supp
130V pop Sig

Device SwitNumber ches

LogiC
Configuration

Peak
Switch
Current
±3.0A

Siliconix OG568/569
Intersil H9108

Medical ultrasound HV
multiplexers, Ink jet
printers

±1.5A

Siliconix OG568/569
Intersil H9108

Medical ultrasound HV
multiplexers, Ink jet
printers

11-2

Similar
Devices

Applications

4

HV01

"'-11 §upertex inc.
16-Channel Matrix TFEL Panel Display Column Driver

Ordering Information
Package Options
Device

40-Pin Ceramic
DIP

36-Pin
Leadless Chip
Carrier

36-Pin Leaded
Chip Carrier
Flat Leads

36-Pin Leaded
Chip Carrier
Std. Bent Leads

36-Pin Leaded
Chip Carrier
Reverse Bent Leads

Die

HV01

HV01C

HV01LC

HV01CF

HV01CS

HV01CR

HV01X

Features

General Description

o
o
o
o
o
o

The HV01 is a 16 channel column driver IC designed for general
purpose electroluminescent display use. The chip contains a D to
A converter and a push-pull output driver for each channel. Input
data is clocked in on the Hi to Lowtransition olthe Clock input and
stored in shift registers. This data feeds into the respective 4-bit
polynomial counter, which serves as a time measuring device.
The output of this counter controls a charging device allowing a
ramp signal to set the analog driver to the desired voltage level
corresponding to one of the 16 possible gray shades.

Up to 60V modulation supply voltage
Drives up to 1000 lines
Capability of 16 levels of gray shading
1511S per conversion and output cycle
Integrated high voltage DMOS and CMOS technology
Available in 40-pin DIP, 36 LCC pkg., or in die form

Absolute Maximum Ratings
Low Voltage Supply V DD
High Voltage Supply V pp
Ramp Voltage V R
Logic Input Voltage

-0.5Vto 14V
-0.5V to 65V

•

-0.5 to Vpp +0.3V
-0.5V to V DD +0.5V

Storage Temperature
Power Dissipation 1
Note 1:

1.6 Watt

For operation above 25°C ambient derate linearly to 85°C at 15mW/oC.

11-3

HV01

Electrical Characteristics

(over recommended operating conditions unless noted)

DC Characteristics
Symbol
VIH
VIL

Input High Voltage Logic Inputs

100

V00 Supply Current

Min

Parameter

Typ

Max
1

V

4

13

mA

Voo = 13.2V, fsc = 3mHz

8

mA

Voo= 13.2V

mA

Vpp = 60V, tCR = 50llS

5.5

mA

Vpp = 60V

±50

J.LA

VIN = OVor Voo

-50

IlA

VOH = Voo - 1.0V
VOL = 1.0V

Voo - 1

Input Low Voltage Logic Inputs

Units
V

loos
Ipp

STDBY Voo Supply Current

Ipps

STDBY Vpp Supply Current

IIL,IIH

Input Leakage Current

IOH

Logic Output Source Current

IOL
IAOH

Logic Output Sink Current

50

HV Analog Output Source Current

-8

-40

IlA
mA

IAOL

HV Analog Output Sink Current

8

40

mA

Min

Typ

Vpp (Driver) Supply Current

AC Characteristics

12
±1

Conditions

Vpp = 60V, VR= 60V
VAOH = 50V
Vpp = 60V, VR= 60V
VAOL= 10V

(Voo = 12V, TA = 25°C)

Symbol

Parameter

Max

Units

tSL

Set up time before load (Shift Clock)

200

ns

tHL

Hold time after load (Shift Clock)

100

ns

tL

Load/Count Pulse Width

100

ns

tLS
tLC

Load set up before Count Clock

20

ns

Load hold after Count Clock

20

ns

tOA

Count to Ramp Delay

tCA

Cycle Time of Ramp Signal

8

tAA

Rise Time of Ramp Signal

3

fsc

Operating Frequency (Shift Clock)

tos

Data set up to shift clock J,

35

tOH
CH

Data hold from shift clock J,

20

Internal holding capacitance per part

tAF

Ramp voltage fali time

100

6

ns
Ils
Ils
MHz

Voo = 10.8V

ns
ns
50

5

Conditions

pF

!IS

Recommended Operating Conditions·
Parameter

Value

Low Voltage Supply V00

12V± 10%

High Voltage Supply Vpp

40Vto 60V

Logic Input Voltage

oto Voo

Operating Temperature (TA)

-40°C to 85°C

• Recommended Power Up Sequence: Voo' Vpp' Logic, VA

11-4

HV01

Switching Waveforms
DATA·IN

;xII-I
tDS¥l-tDH

I

l-tSL-1

I

I
I

SHIFT CLDCK

I
I

ILDAD

LDAD/COUNT

=1-..J

_EN_AB_LE_ _ _ _ _- '_ _

I

I=-

tL

I

COUNTING

I

•

'LS

ff--

I I
·i··~l.C
I

COUNT CLOCK

RAMP SIGNAL VA
_----tCR-----_

:_tAF

I

Timing Diagram
SHIFT REGISTER CLOCK

LOAD/COUNT

~L-

_ _ _ _ _ _~nL

______

~nL

______

~nL__

COUNTER CLOCK

RAMP SUPPLY
VR

~

CHARGING PULSE
(INTERNAL NODE)

________

SHADE 10

~~L

__________________

SHADE 1

~

_________

SHADEOt

0~-~. .-----.

ANALOG OUTPUT
VOLTAGE VAO

11-5

HV01

Functional Block Diagram
D TO A AND
ANALOG DRIVER

4 BIT DECREMENT COUNTER

~

~

Ol
o:l

Ol
o:l

Ol
o:l

(f)

(f)

I

I

(f)

(f)

I

I

:D

:D

:D

:D

Gl

Gl

Gl

Gl

~

::::=

:D

:D

I

=1

~

m

~
m

:D

=1

~
m

~
m

:D

Ol
o:l

=1

=1

=n
--1

~

m

m

~
m

m

16 TOTAL

16 TOTAL

I
I

Vpp
ANALOG
DRIVER

Function Table
Control Inputs
Function

Outputs

Shift
Clock

Counter
Clock

Load!
Count

VR

L

X

L

X

NoL

L

H

Counting

X

L

Voltage Conversion

X

Pulsing

Load Shift Register
Load Counter

Shift
Registers

Counters

Serial

Parallel

Normal
Shift Op.

X

Delayed
Data-In

X

X

No Change

Load Data From
SIR to Counter

No Change

Low

L

Initiates
Ramp

X

Translates Data
To Time

X

DIA Conversion

L

Volt.
Ramping Up

X

Counting

X

Follows Ramp

L = Low level, H = High level, X = Irrelevant, L = Hi to Low Transition

11-6

HV01

Operation of the Column Driver

Programming the Column Driver

Operation of the Column Driver can be understood by looking at
the logic and timing diagrams. The shift registers store four bits of
data for each column to be driven. The four bits are used to
program a counter for sixteen possible values (0-15) which
generate the sixteen gray shades. Since the shift registers have
serial outputs, the chips can be connected in sequence. To load
the shift registers we need n times sixteen pulses (where n = the
# of chips connected serially). After the last shift clock, we need
a short set up time (tSL ) before we can load the data of the register
into the counter. The loading is performed by the Hi level of a Load/
Count Enable Pulse (tL). At the end of this pulse the load count
enable goes low and the transfer gates which connect the shift
registers to the counters turn off and the counter inputs are
enabled. The counting will start at the negative going edge of the
first count clock pulse (tLC ). Concurrently, a positive going ramp
signal is initiated whose rise time is equal to the length of 16 count
clocks. The output of the counter is, in effect, a pulse width with
a termination time controlled by the shift register digital value. The
analog storage stage follows the value on the voltage ramp input
for the duration of that pulse, and then holds that voltage value. As
the timing diagram indicates, each pulse width will specify a
different voltage level. In effect a digital to analog converter stage
was implemented. If at any time the difference in voltage stored
in the analog storage stage and the output voltage differs by more
than one transistor threshold (typically 2 to 3 volts), one of the two
output transistors will turn on to set the correct voltage on the
column.

The Supertex HV01 Column Driver was built to generate 16
different shades on a thin film electroluminescent panel. These 16
shades are achieved by having 1 of 16 possible voltage levels on
the analog outputs.
Depending on the 4 digital inputs fed into the 4 shift registers, data
is loaded into each of the 16 counters. These counters will
interpret the data and produce a pulse whose width is determined
by the data. The output of each drive line is basically a D/A
conversion of the timing signal generated by the polynomial
counter.
The shade voltages are specified by the digital input according to
the table shown. In the table we designate the various shade
voltages by numbers. Shade No. 16 is the brightest, while Shade

Gray Shade Decoding Scheme
Brightest
Shade No.

INA

INB

INC

INO

16

1

0

0

1

15

1

1

0

1

14

1

1

1

1

13

1

1

1

0

12

0

1

1

1

11

1

0

1

0

10

0

1

0

1

9

1

0

1

1

8

1

1

0

0

7

0

1

1

0

6

0

0

1

1

5

1

0

0

0

4

0

1

0

0

3

0

0

1

0

2

0

0

0

1

1

0

0

0

0

11-7

Brightest

Dimmest

HV01

Pin Configurations
4o-Pin DIP
Pin Function

Pin

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

HVout8
HVout7
HVout€
HVout5
HVout4
HVout3
HVout2
HVout 1
HGND

lGND
load Count

N/C
0'A
Os
°c
00
VR
Vpp

N/C
N/C
HGND
HVout 16
HVout 15
HVout 14
HVout 13
HVoul12
HVout 11
HVout 10
HVoul9

N/C
N/C
Vpp
VR
INo
INc
INs
INA
Shift ClK
CounlClK

36-Pin LCC
Pin Function

Pin

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

HVout8
HVout 7
HVout6
HVout5
HVout4
HVout3
HVout2
HVout 1
HGND
Vpp
VR
INo
INc
INs
INA
ShiftClK
Count ClK

lGND
load Count

N/C
°A
Os
°c
00
VR
Vpp
HGND
HVout 16
HVout 15
HVout 14
HVout 13
HVout 12
HVoul11
HVoul10
HVoul9

Voo

Package Outlines
40

20 - ' - -_ _ _...r-- 21

lop view

IOpviaw

40-pin DIP

36-pin lCC

11-8

Voo

HV02

"§upertex inc.
16-Channel Matrix TFEL Panel Display Row Driver

Ordering Information
Package Options
Device

40·Pin Ceramic
DIP

36·Pln
Leadless Chip
Carrier

36·Pin Leaded
Chip Carrier
Flat Leads

36-Pin Leaded
Chip Carrier
Std. Bent Leads

36·Pin Leaded
Chip Carrier
Reverse Bent Leads

Die

HV02

HV02C

HV02LC

HV02CF

HV02CS

HV02CR

HV02X

Features

General Description

o
o
o
o
o
o
o
o

The HV02 is a 16 Channel Row Drive IC designed for general
purpose electroluminescent display use. The chip provides the
scanning voltage to each row output in sequence and, in unison,
generates the refresh pulse and two sinking pulses (scan and refresh sink) which are required for the operation of the TFEL panel.
The intrinsic source-drain diodes on the outputs can handle surge
currents up to 250mA for charging of the capacitive loads.

HVCMOS® Technology
Up to 200V output voltage
Can drive up to 1000 lines
250mA surge current sink capability
TYP RON of 25 ohms
High performance - up to 200 KHz scan rate

Serial Data is entered into a 16-bit shift register on the Hi to Low
transition of the clock input. Data is outputted if enable is Hi and
the "ALL ON" input is Low. If the "ALL ON" input goes Hi, all parallel
outputs turn on in unison to refresh the Row lines on the panel.
Expansion is possible by using the serial output (data out). This
output is not controlled by the enable and "ALL ON" inputs. To
make the system design versatile, the HV02 has an initialization
feature which allows setting or resetting the first bit and resetting
the other bits of the shift register.

Integrated high voltage DMOS and CMOS technology
Available in 40-pin DIP, 36 Pin Ceramic Chip Carrier and
Leaded Chip Carrier packages

Absolute Maximum Ratings
-0.5Vto 14V

Low Voltage Supply Voo
BVos Driver output transistor voltage
Total Drive Current (Unison Mode)
Logic Input Voltage
Storage Temperature
Power Dissipation 1
Note 1:

10LU

-0.5V to 250V
1.6AMP
-0.5V to VDO +0.5V
-65°C to 150°C
1.6 Watt

For operation above 25°C ambient derate linearly to 85°C at 15mW/"C.

11-9

Electrical Characteristics

HV02

(over recommended operating conditions unless rioted)

DC Characteristics
~'i

.'

Symbo,l
VIH
VIL

Parameter
Input High Voltage

IDD

VDO Supply Current

10LH

High Voltage Output Sink Current
(Single Driver)

Mirt

Typ

Max
1

Units
V
V

1

6.5

mA

VDD - 1

Input Low Voltage
250

300

Conditions

mA

Voo = 13V, Ise = 100KHz
VDO = 10.8V
Vo= 15V

IlL' IIH

Input Leakage Current

±1

±50

IlA

VIN = OVor Voo

RON

Output driver transistor On-resistance

25

60

n

BVos

Output driver transistor Drain-Source
Breakdown voltage

200

Voo = 10.8V
High Voltage Outputs Off
10 = 2001lA

10L

Shift Register Data Out
Source Current

50

J.lA

Voo = 10.8V
VOL = 1.0V

10H

Shift Register Data Out
Source Current

-50

J.lA

Veo = 10.8
VoH =Voo -1.0V

AC Characteristics

250

V

(Voo = 12V, TA = 25°C)

Symbol

Parameter

Ie

Max shilt Clopk Frequency

SR

Driver Ground Slew Rate

Min

Typ

6

10

Max

Units
MHz

50

Conditions
Voo= 10V

V/J.lsec

Recommended Operating Conditions
Parameter

Value

Low Voltage Supply VDO

10.8V to 13.2V

Driver ouput transistor voltage

up to 200V

Logie Input Voltage

OVto Voo
-40°C to 85°C

Operating Temperature (TA)

11-10

HV02

Operation of the Row Driver
The operation of the row driver can be understood by looking at
the Logic Diagram and Output Waveform states. In normal
operation, a row driver selects out a single line on the electroluminescent panel by pulling it down to a negative voltage (-Vd). This
selection is called scan. Since the EL panel has a large capacitance that was charged, eventually it has to be discharged. This
operation is called refresh, and is performed by connecting these
to a positive voltage (+Vd).

Serial data is entered into the registers on the Hi to Lo transition
of the clock input. Normal operation calls for a single logic "high"
to be clocked through the shift register via the serial output. To
create a scan function, the enable must be pulsed at each time.
For the refresh sync mode, the ALL ON input must be high, since
this function has to be done in unison for all row lines.
The Row Driver was designed with an added feature of a mode
control input. The flip-flops of the shift registers are made with a
reset control. By pulling the "RESET" input high, they will be reset
to zero with the exception of the first. This stage can be high or low
during the reset depending on the control input called "First." "this
input is high, the "RESET" command will be interpreted as a "SET"
command for the first flip-flop. This feature is important in the
normal scanning function when a group of these row drivers are
interconnected to form a long string of shift registers. By utilizing
this function, asingle "ONe" can be placed into any of the selected
chips, and the row drivers in the system can be initialized in a very
flexible way.

The driver ground (DR GND) is not tied to the system ground, but
rather is a floating node. It is connected to the substrate driver,
whose output varies as shown on the Waveform Diagram. The
combination of the Row Drivers and the Substrate Drivers gives
the required four functions which are called scan, scan sync,
refresh and refresh sync. The first mode of the scan must be
applied individually since it is by definition a single line selection.
The refresh sync on the other hand, must be applied in unison.
The other two modes, scan sync and refresh, can be applied
either way according to the designer's discretion.

Switching Waveforms
ROW 1

-Vd
ROW2

ROW3

CLOCK
ENABLE

ALLON

ILI=

SCAN

SCAN SYNC

-- ------_..

.----------

U

REFRESH

REFRESH

-n-

REFRESH SYNC

________~~---------~rl~----_______ n____..n.._____

----------------------- -- --------

DRIVER
GROUND
SUBSTRATE DRIVER OUTPUT

11-11

..
I

HV02

Logic Diagram

18 TOTAL

~
[OUT
DATA

SHIFT REGISTER

SHIFT REGISTER
AND CONTROL lOGIC

Function Table
Control Inputs

Function

Internal Shift Registers

1

2-16

Set to "1"

RESET to "0"

"0"

Determined by
Enable and
ALL ON

Reset to "0"

"0"

Determined by
ALLaN

X

LOAD & SHIFT

R 16

Determined by
ENABLE and
ALL ON

H

L

X

R16

Determined by
Rl through R16

X

L

L

As determined above

R 16

All Parallel
Outputs "OFF"

X

X

H

As determined above

R 16

All Parallel
Outputs are "ON"

Enable All On

First

Reset

Clock

First

H

H

X

X

X

Reset

L

H

X

X

X

Load Data/Shift

X

L

J.

X

Output Enable

X

L

X

Output Disable

X

X

Allan

X

X

L = Low level, H = High level, X = irrelevant, J,

Outputs
Serial
Output

=Hi to Low Transition, R 16 = State of register 16, Rt = State of Register 1.

11-12

1-16 Parallel

HV02

Pin Configurations
40·Pin DIP
Pin Function
1
N/C
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Allan
Enable
N/C
Data Out
LGND
DRGND
HVout 16
HVout 15
N/C
N/C
HVout 14
HVout 13
N/C
N/C
N/C
HVout 12
HVout 11
HVout 10
HVout9

Pin

Function

36-Pln Lee
Pin Function

Pin

Function

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

HVout8
HVout7
HVout6
HVout5
N/C
N/C
N/C
HVout4
HVout3
N/C
N/C
HVout2
HVout 1
DRGNO
LGND
Data In
Clock
Reset

1
2
3
4
5
6'
7
8
9
10
11
12
13
14
15
16
17
18

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

HVout8
HVout7
HVout6
HVout5
N/C
N/C
N/C
N/C
HVout4
HVout3
HVout2
HVout 1
ORGND
LGND
Data In
Clock
Reset

First
Allan
Enable
Data Out
LGND
DRGND
HVout 16
HVout 15
HVout 14
HVout 13
N/C
N/C
N/C
N/C
HVout 12
HVout 11
HVout 10
HVout9

Voo
First

Package Outlines
40

20

21
top view

lop view

40-pin DIP

36-pin LCC

11-13

Voo

~

HV03
HV05

"'-" §upertex inc.
64-Channel Serial To Parallel Converter
With Open Drain Outputs
Ordering Information
Package Options
Device

Recommended
Operating
Vpp Max

S4-Pad Ceramic
Leadless Chip
Carrier

S4-J Lead
Plastic Chip
Carrier

SD-Lead
Quad Cerpak
Gullwing

SO-Lead
Quad Plastic
Gullwing

SO-Lead
35mmTAB
Tape

Ole

HV03
HV05

220V

HV0322LC

HV0322PJ

HV0322DG

HV0322PG

HV0322T

HV0322X

300V

HV0330LC

HV0330PJ

HV0330DG

HV0330PG

HV0330T

HV0330X

220V

HV0522LC

HV0522PJ

HV0522DG

HV0522PG

HV0522T

HV0522X

300V

HV0530LC

HV0530PJ

HV0530DG

HV0530PG

HV0530T

HV0530X

Features

General Description

o
o
o
o
o
o
o
o

The HV03 and HV05 are low voltage serial to high voltage parallel
converters with open drain outputs. These devices have been
designed for use as drivers for AC-electroluminescent displays.
They can also be used in any application requiring multiple output
high voltage current sinking capabilities such as driving inkjet and
electrostatic printheads. plasma panels. vacuum fluorescent. or
large matrix LCD displays.

HVCMOS® Technology
Output voltages up to 300V using a ramped supply
Sink current minimum 100 mA
Shift register speed 8 MHz
Latched outputs
Output polarity and blanking

These devices consist of a 64-bit shift register. 64 latches. and
control logic to perform the polarity select and blanking of the outputs. Data is shifted through the shift register on the high to low
transition of the clock. The HV03 shifts in the counterclockwise
direction when viewed from the top of the package and the HV05
shifts in the clockwise direction. A data output buffer is provided
for cascading devices. This output reflects the current status of
the last bit of the shift register. Operation of the shift register is not
affected by the LE (latch enable). BL (blanking). or the POL
(polarity) inputs. Transfer of data from the shift register to the latch
occurs when the LE ~tch enable) input is high. The data in the
latch is stored when LE is low.

CMOS compatible inputs
Forward and reverse shifting options

Absolute Maximum Ratings 1
Supply voltage. VDO

-0.5Vto+15V

Supply voltage. Vpp2

-o.SV to +225V

Logic input levels
Ground current3
Continuous total power dissipation 4

-0.5V to VDO +0.5V
6.0A

The HV03 and HV05 have been designed to be used in systems
which either switch off the high voltage supply before changing
the state of the high voltage outputs or limit the current through
each output.

1900mW

Operating temperature range
Storage temperature range
Notes: 1. All voltages are referenced to Vss'
2. These devices have been designed to be used in applications which
either switch the Vpp supply to ground before changing the state of the
high voltage outputs or limit the current through each output.
3. Connection to all power and ground pads is required. Duty cycle is limited
by the total power dissipated in the package.
4. For operation above 25'C ambient derate linearly to 85'C at 15mW/,C.

11-14

HV03/HV05

Electrical Characteristics

(over recommended operating conditions unless noted)

DC Characteristics
Symbol

Parameter

Min

Typ

Voo Supply Current

100

Max

Units

25

mA

fCLK = 8MHz, fOATA = 4MHz
LE= LOW

Conditions

looa

Quiescent V00 Supply Current

0.25

mA

All VIN =OV

IO(OFF)

Off State Output Current

100

IlA

All outputs high, All SWS parallel

IIH

High-Level Logic Input Current

10

IlA

IlL
VOH

Low-Level Logic Input Current

-10

IlA

VIH = Voo
VI=OV

High-Level Output Data Out

VOL

Low-Level Output

Voc

HVOUT Clamp Voltage

Voo -IV

I
I

V

HVOUT
Data Out

15

V

IDoUT = -1 001lA
IHVoUT = +100mA

1

V

IDoUT = +1 OOIlA

-1.5

V

IOL

= -100mA

AC Characteristics
Symbol

Parameter

Min

Typ

Max

Units

8

MHz

fCLK

Clock Frequency

tw

Clock Width High or Low

62

tsu

Data Setup Time Before Clock Falls

25

ns

tH

Data Hold Time After Clock Falls

10

ns

tWLE

Width of Latch Enable Pulse

62

ns

tOLE

LE Delay Time Falling Edge of Clock

25

ns

tSLE

LE Setup Time Before Falling Edge of Clock

30

ns

Delay Time from Vpp Low Until

100

ns

to

Conditions

ns

Change in LE, POL, BL Is Allowed
tSL

Setup Time from Falling Edge LE to Vpp Rise

200

ns

tSB

Setup Time from BL Selected to Vpp Rise

150

ns

tsp

Setup Time from POL Selected to Vpp Rise

100

tOHL

Delay Time Clock to Data High to Low

100

ns

tOLK

Delay Time Clock to Data Low to High

100

ns

ns

Recommended Operating Conditions
Symbol
Voo

Parameter
Logic supply voltage

Vpp

High voltage supply

VIH
VIL

High-level input voltage

dV/dt

Vpp ramp rate

TA

Operating free-air temperature

I
I

Min

Typ

Max

Units

10.8

12

13.2

V

HV0320/HV0520

-0.3

200

V

HV0330/HV0530

-0.3

300

V

Voo - 2V

Voo
2.0

V

80

V/IlS

+85

°C

Low-level input voltage

0
-40

11-15

V

HV03/HV05

Input and Output Equivalent Circuit
Voo

-------K, .

Data Valid

V1H

50_%_,_ _ _ _ _ _ _ _ _ _ _ __

,

t su ------..J..--tH
,

V1L

------+-1

I

,

V1H

~, V1L
, '------""

' K50%

%50%

'--------

,

1,

:••------tWL-------..<: ••~---------twH----------~.~:

,

,

1
1

i

Data OUT

/ ,50%

,

VOH
VOL

-----------------~i---------·
'!~.o__----- t DLH --------<.~,

~50%
_ - - - - - t DHL

Latch Enable

________________

~,----J

-------.. 1,

'-----------------~----

'I

1

50%/

: . - - tDLE

50%

------.1I••------- t WLE -------+-~
tSLE ~:
I
,

I

I

1

HV OUT
w SIR LOW

i

~-'_10-%-,---------- ~::

I

--..1

,

'

1---1

I-+---- t OFF ~
1

:

HV OUT
w SIR HIGH

:
1

'

90%~------------ VOH
10%¥ :

,
I

~,

,

,

'

1
1..-.
1

.--tON_

11-30

VOL

HV04H/HV06H

Functional Block Diagram
~rltYo-

_________________--,
Vpp

]tanking

0--------------..,

~eo----------_,
Data Input

HVout 1

Clock

HVout 2

I

I
64-blt

64

static
shift
register

Latches

HVout63

HVout64

L....------------e

x

L

HOLDS PREVIOUS STATE

X

X

X

X

H

X

L

HOLDS PREVIOUS STATE

X

X

X

X

X

X

H

ALL OUTPUTS OFF

OFF
ON

11-58

HV14

Typical Performance Curves
TYPICAL
RSW

VI.

TYPICAL

VPP VNN

RSW VI. VPP VNN
40

70

ISW l200mA

1

ISW· 5mA _

60

30

;;;
~li

",%
II:

-

70'C

I-70'C

50

25'C

o'c

£

40

-

20

25'c
o'c
10

30
t50

tao

±oo

too

±50

VPP VNN (volts)

Vpp VNN (volts)

TYPICAL
Ipp INN vs. Vpp VNN (ONE SWITCH ON)

1.5

±oo

±70

'off

r-------,r-------.-----,

TYPICAL
VS. Vpp VNN

8

1z
z

o

.5

o
t50

±70

t60

tao

t50

Vpp VNN (vol'.)

tao

±70

t60
Vpp VNN (volts)

TYPICAL

TYPICAL
SWITCH CURRENT vs VOLTAGE

'on (uS)

VL Vpp VNN
3 . 5 , - -_ _-,-_ _ _ _, -_ _ _--,

250

.L

/'Y ~

200

ISO

~ ty

Vpp .. +8Ov
Vnn=-8{)v

100

3

.:!

"

c

~

0

~_

-5 0

;;;

.§
:r

0

2.5

50

1& ~

/~

-10 0
--15 0

-2001/

2L-_ _ _- L______
t50

~

too

______

~

~~

?'

~~
V; V

~

-25 0

tao

-7

-6 -5 -4 -3 -2

o

1

2

V SWITCH (Volts)

Vpp VNN (volts)

11-59

3

4

5

6

7

'.

~

HV15

"-11 !iupertex inc.
1 of a Decode a-Channel High Voltage Switch

Ordering Information
Package Options
20-pln Plastic
DIP

V NN

VS1G

20-pln ceramic
side-brazed DIP

+70V

-70V

110V pop

HV1514C

HV1514P

HV1514X

+80V

-80V

130V P-P

HV1516C

HV1516P

HV1516X

Vpp

Die in waffle pack

Features

General Description

D

This device is an 8-channel high-voltage integrated circuit (HVIC),
configured as a 1 of 8 decode functions, intended for use in applications requiring high voltage switching controlled by low voltage signals; e.g., ultrasound imaging and printers. ON-chip
latches are provided for the decoded data. Using HVCMOS technology, this HVIC combines high voltage bi-Iateral DMOS
switches and low power CMOS logic to provide efficient control of
high voltage analog signals.

HVCMOS® Technology

D Up to 130V peak to peak switching capability
D Output On-resistance typically 40 ohms
D Low parasitic capacitances
D DC to 1OMHz analog signal frequency

D 45 dB typical output off isolation at 5 MHz
D CMOS logic circuitry for low power

Pin Configuration

and excellent noise immunity

D On-chip decode, latch and chip select logic circuitry
Y4

Y6

Absolute Maximum Ratings*

YC

Voo Logic power supply voltage

vpp Positive high voltage supply

-0.5V to +90V

V NN Negative high voltage supply

+0.5V to -90V

Logic input voltages
Peak analog signal current/channel
Storage temperature

Y1

-0.5Vto+18V

YO
Y3

A

-O.5V to Voo +0.3V

B

1.5A

C

-65°C to + 150°C
800mW

CL

.. Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability.

LE

Power dissipation

top view

20-pin DIP

11-60

HV15

Electrical Characteristics

(over recommended operating conditions unless noted)

DC Characteristics
Characteristics

Sym

DOC
min

max

min

+25°C
typ

max

+7DoC
min
max

Units

Test Conditions

Switch (ON) Resistance

Rsw

50

40

50

60

ohms

Switch (ON) Resistance

Rsw

35

25

35

45

ohms

Isw =200mA

Switch (ON) Resistance

Rsw

55

45

55

65

ohms

Vpp = +50V

Isw =5mA

V NN = -50V
Isw= 5mA
Switch (ON) Resistance

40

Rsw

25

40

50

ohms

Vpp = +50V
VNN = -50V
Isw = 200mA

Switch (ON) Resistance

30

Rsw

10

30

30

%

Matching x and y (0-3)
Switch Off Leakage

Isw= 5mA
Vpp = +50V, V NN = -50V

50

ISWL

0.5

50

150

~

Your = Vpp -10V thru 10K
with 8 SWS in parallel

DC Ollset Switch Oil

500

100

500

500

mV

RL= 100K

DC Ollset Switch On

500

100

500

500

mV

RL= 100K

10

4.5

10

10

pF

DC Bias = 40V
1= 1MHz

Pole to Pole
Switch Capacitance

Csw

Logic Input Capacitance

CIN

Pos. HV Supply Current

Ippo

200

50

200

200

~

Neg. HV Supply Current

INNO

-200

-50

-200

-200

~A

Pos. HV Supply Current

Ipp

0.8

1.6

mA

Neg. HV Supply Current

INN

-0.8

-1.6

mA

Isw= 5mA

Pos. HV Supply Current

Ipp

0.6

1.2

mA

Vpp = +50V

Neg. HV Supply Current

INN

-0.6

-1.2

mA

V NN = -50V

3.5

pF
ALLSWSOFF
1 SWON

1 SW ON, Isw = 5mA
Switch Output
Peak Current
Logic Supply Current

1.5

A

0.001

100

mA

5

AC Characteristics
Characteristics
Data Hold Time After LE Rises

Sym

DOC
min

max

min

+25°C
typ

max

min

+7DoC
max

Units

tHO

5

ns

Set Up Time Before LE Rises

tso

260

ns

Time Width 01 LE

IwLE

300

ns

Time Width 01 CL

IwCL

100

Turn On Time

iaN

5

tOFF
KO

10

Turn

011 Time

Ofl Isolation

35

11-61

Test Conditions

ns
2.5

5

5

5.0

10

10

45

~s
~s

dB

f =5MHz

HV15

Recommended Operating Conditions
Symbol

Parameter
Logic power supply voltage

Device
HV1514
HV1516
X
X

Voo
Vpp

Positive high voltage supply

X

VNN

Negative high voltage supply

X

+10.0V to +15.5V
+50.0V to +70.0V

X

+50.0V to +80.0V
-50.0V to -70.0V

X

-50.0V to -80.0V
Voo -2V to Voo
Oto 2.0V

High level input voltage

X

X

V,L

Low-level input voltage

X

X

VS1G

Analog signal voltage peak to peak

X

X

VNN +15Vto Vpp -15V

TA

Operating free air-temperature

X

X

0° to 70 0 e

V,H

Note:

Value

For non·ground referenced systems the following must be used:
Power up sequence:
GND VNN VDD VPP
Power down sequence: VPP VDD VNN GND

T ONITOFF Measurement Circuit
Vpp=+BOV

JOV

AINPUT
(TYPICAL)

o-l~-.L...-O VOUT

Logic Timing Waveforms
LOGIC
INPUT
(TYPICAL) L....J'-"-"'--"-"'y

LE ------1----..1

Your
(TYPICAJ.)
ON

---"1--'

11-62

HV15

Logic Diagram
Vc

v..
LE

Truth Table
C

B

A

L

L

L

L

LE

CL

YO

L

L

L

ON

CS1 CS2

Y1

Y2

Y3

Y4

Y6

L

L

H

L

L

L

L

L

H

L

L

L

L

L

L

H

H

L

L

L

L

H

L

L

L

L

L

L

H

L

H

L

L

L

L

H

H

L

L

L

L

L

H

H

H

L

L

L

L

X

X

X

H

X

L

L

ALL OUTPUTS OFF

X

X

X

X

H

L

L

ALL OUTPUTS OFF

X

X

X

X

X

X

H

ALL OUTPUTS OFF

X

X

X

X

X

H

L

HOLDS PREVIOUS STATE

ya

ON
ON
ON
ON
ON
ON
ON

Notes:
1 . Address data at A, B, C cause one of the eight switches to be selected for connection to the
common bus C.
2. The clear input CL overrides all other inputs.
3. Since the latch follows the decoder, only the CL Input matters when LE is H.
4. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low,
the decoded selection address information flows through the latch.

11-63

Y7

HV15

Typical Performance Curves

TYPICAL
Ipp INN vo. Vpp VNN (ONE SWITCH ONI

TYPICAL

SWITCH CURRENT Vi VOLTAGE
250

1.5 , . . - - - - - , - - - - , - - - - - - ,

oL )Y'

i

200

)~

\50

~~

Vpp = +8Ov
Vnn=-BOv

100
50

-50

10 ?fT

/~

0

w:: ~

1

~V

2
2

..
.5

~ '/
oV //

15 ()
--20

25 0

- ()

--5

-4

--3

o

--2

±50

7

iao

teo

V SWITCH (Volts)

Vpp VNN (yoltsl
TYPICAL
TYPICAL

RSW vs. Vpp VNN

toff vs. VPP VNN
70

,. 1._

60

~

in

~:E

.,:1:
II: ~

-

70°C

50

~

O'C

25'C

40

O'C

30
±50

iao

±70

±60

±50

VPP VNN (yoltsl

±eo

±70

±ao

Vpp VNN (voltsl

TYPICAL
RSW

YS.

TYPICAL

VPP V NN

ton (uSI
40

YS.

Vpp VNN

3.5,------,.------r-----...,

I

Isw = 200m A

30

-

70'C

25'C

c

o

O'C
20

2.5

)-----+--=--..::,-::.;...=--=..,....-l

10
±50

i60

±70

±so

±50

iao
Vpp VNN (voltsl

Vpp VNN (voltsl

11-64

Iao

~

HV16

'UJ !!iupertex inc.
a-Channel High Voltage Switch

Ordering Information
Vpp

V NN

V S1G

24-pin ceramic
side-brazed DIP

waffle pack

Package Options
3S-pin leaded
ceramic chip carrier

Die in

24-pin
plastic DIP

28-lead plastic
chip carrier

+lOV

-lOY

110V pop

HV1614C

HV1614X

HV1614CS

HV1614P

HV1614PJ

+BOV

-BOV

130V pop

HV1616C

HV1616X

HV1616CS

HV1616P

HV1616PJ

Features

General Description

D

This device is an 8-channel high-voltage integrated circuit (HVIC)
intended for use in applications requiring high voltage switching
controlled by low voltage signals; e.g., ultrasound imaging and
printers. Input data is shifted into an 8-bit shift register which can
then be retained in an 8-bit latch. Using HVCMOS technology, this
HVIC combines high voltage bi-Iateral DMOS switches and low
power CMOS logic to provide efficient control of high voltage
analog signals.

HVCMOS® Technology

D Up to 130V peak to peak switching capability
D Output On-resistance typically 40 ohms
D Low parasitic capacitances
D DC to 1OMHz analog signal frequency

D 45 dB typical output off isolation at 5 MHz
D CMOS logic circuitry for low power
and excellent noise immunity

D On-chip shift register, latch and chip select logic circuitry
D

Surface mount package available

Absolute Maximum Ratings*
V 00 Logic power supply voltage

-0.5V to + 1BV

Vpp Positive high voltage supply

-0.5V to +90V

V NN Negative high voltage supply

+0.5V to -90V

LogiC input voltages
Peak analog signal current/channel
Storage temperature
Power dissipation

-0.5V to Voo +0.3V
1.5A
-65°C to + 150°C
BOOmW

* Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability.

11-65

HV1.6

Electrical Characteristics

(over recommended oJerating conditions unless noted)

DC Characteristics
Characteristics

DoC

Sym

min

max

min

+25°C
typ

max

+70°C
min
max

Units

Test Conditions

Switch (ON) Resistance

Rsw

50

40

50

60

ohms

Switch (ON) Resistance

Rsw

35

25

35

45

ohms

Isw =200mA

Switch (ON) Resistance

Rsw

55

45

55

65

ohms

Vpp = +50V
VNN = -50V

Switch (ON) Resistance

Rsw

40

40

50

ohms

Vpp = +50V
VNN = -50V

Switch (ON) Resistance
Matching

Rsw

15

15

15

%

Switch Off Leakage

Iswl

50

0.5

50

150

~

-

Isw= SmA

Isw= SmA

25

Isw= 200mA
Isw= SmA
Vpp = +50V, VNN = -50V
VOUT = Vpp -10V thru 10K
with 8 SWS in parallel

DC Offset Switch 011

500

100

500

500

mV

RL = 100K

DC Offset Switch On

500

100

500

500

mV

RL= 100K

10

4.5

10

10

pF

DC Bias =40V
1= 1MHz

50
-50

200
-200

200
-200

itA

0.8
-0.8

1.6
-1.6

mA
mA

1 SWON

0.6
-0.6

1.2
-1.2

mA
mA

Vpp = +50V
VNN =-50V
1 SW ON, Isw = SmA

Pole to Pole
Switch Capacitance

Csw

Logic Input Capacitance

CIN

Pos. HV Supply Current
Neg. HV Supply Current

Ippo

Pos. HV Supply Current
Neg. HV Supply Current
Pos. HV Supply Curient
Neg. HV Supply Current

3.5
200
-200

INNO
Ipp
INN
Ipp
INN

Switch Output
Peak Current

pF

1.5

ALLSWSOFF

~

Isw= SmA

A
IClK =3MHz

Logic Supply Current

100

4

6

mA

Logic Supply Current

100

0.001

5

rnA

Data Out Source Current

ISOR

0.7

0.8

0.9

0.7

mA

VOUT = Voo - 0.7V

Data Out Sink Current

ISINK

1.5

1.6

1.8

1.5

mA

VOUT= 0.7V

AC Characteristics
Characteristics

Sym

O°C

min

max

min

+25°C
typ

max

min

+70°C
max

Units

Set Up Time Belore LE Rises

tso

260

Tim,e Width 01 LE

IwlE

300

Clock Delay Time to Data Out

too

Turn On Time

tON

5

2.5

5

5

its

tOFF
KO

10

5.0

10

10

its
dB

Turn Off Time
Ofl Isolation

ns
ns
250

35

ns

330

45

Max Clock Freq

tClK

Set Up Time Data to Clock

tsu

0

ns

Hold Time Data from Clock

th

35

ns

3

11-66

Test Conditions

MHz

f = 5MHz
fOATA = IClK/2

HV16

Recommended Operating Conditions
Symbol
Vee
Vpp

Parameter

Device
HV1614

HV1616

X
X

X

Logic power supply voltage
Positive high voltage supply

+10.0V to +15.5V
+50.0V to +70.0V

X
VNN

Note:

V1H

High level input voltage

V1L

Low-level input voltage

VS1G

Analog signal voltage peak to peak

TA

Operating free air-temperature

+50.0V to +80.0V

X

Negative high voltage supply

-50.0V to -70.0V

X
X
X
X

X
X

-50.0V to -80.0V

X

o to 2.0V

X
X

0° to 70 0 e

Vee -2V to Vee
VNN +15V to Vpp -15V

For non·ground referenced systems the following must be used:
Power up secuence:
GND VNN VDD VPP
Power down sequence: VPP VDD VNN GND

T ONITOFF Measurement Circuit
Vpp"'+SOV

70V

o-If--....L-O

Logic Timing Waveforms
DATA
IN

u-----+--..

CLOCK

DATA

OUT

11-67

Value

VOUT

Logic Diagram
LATCHES

LEVEL
SHIFTERS

OUTPUT
SWITCHES

eLK

8W2

'WI

OW.
SW.
sws

Dour

OW7

LE

Truth Table
DO

01 02 03 D4 05 De 07 LE SWO SW1 SW2 SW3 SW4 SW5

L
H

X

L

OFF

L

ON

L

L

OFF

H

L

ON

X

L

L

OFF

H

L

ON

X

L

L

OFF

H

L

ON

X

L

L

OFF

H

L

ON

X

L

L

OFF

H

L

ON

X

swe

L

L

OFF

H

L

ON

X

L

L

H

L

X

H

OFF
ON
HOLD PREVIOUS STATE

Notes:
1. The eight switches operata Independently
2. Serial data is clocked In on the L.....,H transition of CK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low,

the shift register data flows through the latch.
4. DOUT is high when switch 7 is on.

5. Shift register clocking has no effect on the switch states if LE is H.

11-68

SW7

HV16

Typical Performance Curves
TYPICAL

TYPICAL

RSW n. VPP VNN

RSW vs. Vpp VNN

70

40

l

iSW- SmA _

ao

I

ISW = 200mA
~

-

70'C

30

iii
3::;

en"£

50

-

-

70'C

a:

25'C
O'C
20

:lS'C

40

O'C

10

30
:t50

:t70

±eo

:tao

teo

t50

VPP V NN (volts)

tao

±70

Vpp VNN (volts)

TYPICAL
VL Vpp VNN

TYPICAL
Ipp INN v.. Vpp VNN (ONE SWITCH ON)

t on (uS)

3.5 r - - - - - , - - - - - , - - - - - - - ,

1.5

r-----,-----,------,

1z
~

......

c

o
2.5

1-----+-...::::.......:-"'''+--;;:-.....::''''''':-1

:t50

:tao

±70

.5

tao

:tao

:teo

±50

Vpp VNN (volts)

Vpp VNN (volts)

TYPICAL
Idd VI. Frequency

TYPICAL
Vpp VNN

tuff vs.

J..

e-

Vdd = 15V
LE = High
TA = OOto 10fl.C



"5>

SEGMENT OUTPUTS

is

a

o

X
X

1

X
X

2
3

X

II

X

5

X

6

X

7

X

8

X

9

X
X

X
X
X
X

1

2
OFF
OFF
OfF
OFF
OFF

OFF
OFF
OFF
OFF
OFF

OFF
OFF
OFF
OFF
OFF

OFF
OFF
OFF
OFF
OFF

ON

ON

ON

ON

8.

6ft

,.

a ::::JIuper
~
....Lex .nc.
"-11

HV341
HV343
HV345
HV348
Preliminary

High Voltage Analog Switches
Ordering Information
Function

DualSPST

DualSPDT

Dual DPST

DualSPST

Analog Signal Range

V NN to Vpp

VNN to Vpp

V NN to Vpp

V NN to Vpp

RDS(ON)

100 ohms

100 ohms

100 ohms

55 ohms

Package Type

Order
No.
and
Part
Type

Temp Range

16-lead CERDIP, Hi-Rei

-SsoC to + 12SoC

RBHV341D

RBHV343D

RBHV34SD

RBHV348D

16-lead CERDlP, Mil-Temp

-SsoC to + 12SoC

HV341D

HV343D

HV34SD

HV348D

16-lead CERDIP

-20°C to + 8SoC

HV341MD

HV343MD

HV34SMD

HV348MD

16-lead small outline'

-20°C to + 8SoC

HV341MWG

HV343MWG

HV34SMWG

HV348MWG

16-lead small outline'

O°Cto + 70°C

HV341WG

HV343WG

HV34SWG

HV348WG

16-lead plastic DIP

O°Cto + 70°C

HV341P

HV343P

HV34SP

HV348P

Die in waffle pack

O°Cto + 70°C

HV341 X

HV343X

HV34SX

HV348X

,300 mil wide SO package

Features

General Description

D

These CMOS/DMOS high voltage analog switches are designed
to handle high voltage analog signals. They may be used when
analog voltages are low and high voltage immunity is desired. The
signal handling capability extends1rom positive to negative supply voltage; i.e., 100V peak to peak with ±SOV power supplies.

±20V to ±SOV single and dual supply operation

D

RON less than SSg (HV348)

D

Signal switching from positive to negative rail

D

-SOdb OFF isolation at SMHz

D

Withstand +80V to -100 spikes

D

Withstand V51G with power supply off

Inputs are compatible with CMOS logic, with a zero level turning
the switches ON.
Operating supply voltage ranges from ±20V to ±SOV with dual
output power supplies, with the positive supply current below
300llA and negative supply not exceeding IOOIlA.

Applications
D

When a single output power supply is used, operating voltage
ranges from +20V to +SOV, with less than 20llA operating current
when logic input signal equals the supply voltage.

Test Equipment and Instruments

D

Diagnostic Systems

D

48 Volt Telecom Systems

D

Military Electronics

With the addition of series diodes on the power supply and ground
inputs, the HV341 series drivers will withstand +80V to -100V
excursion on the inputs or switch pins without damage, or will withstand signal input with the power supplies OFF.

Absolute Maximum Ratings 1
Supply voltage, V DD

-0.3V to +6SV

Supply voltage, V NN

+0.3V to -6SV

Data input voltage
Input current
Continuous total
power dissipation 2

Switches

±200mA

Logic inputs

±30mA

Plastic Packages

SOOmW

Ceramic Packages

7S0mW

Storage temperature range

-6SoC to + IS0°C

Notes: 1. All voltages are referenced to V5S'
2.

For operation above 25°C ambient, derate linearly to 85"C at BmW/cC.

11-88

HV341/HV343/HV345/HV348

Electrical Characteristics

(over recommended operating conditions unless noted)

DC Characteristics
Symbol

VSIG

Parameter

Min

Analog signal range
HV341 1343/345

RON

Typ

VNN
25°C

Units

Vpp

V

40

Over temp
HV348

Max

75

Q

100

Q

VSIG = ±50V

50

Q

ISIG = 10mA

75

Q

25

25°C
Over temp

RON
VIL
VIH

ON-Resistance matching

ISOL

Switch OFF leakage

7

%

Input low threshold

3.5

Input high threshold

V

12

V

25°C
Over temp

10

60

nA

1

5

~A

Ipp

Vpp quiescent current

200

600

~A

INN

VNN quiescent current

15

100

~A

liN

Logic input current

0.1

10

~A

ISON

Switch ON leakage

10

60

nA

1

5

~A

Typ

Max

Units

0.5

1.0

~s

1.5

Ils

0.4

0.75

115

1.0

25°C
Over temp

AC Characteristics (@ voo
Symbol

= 12V,

Turn-ON time

tOFF

Turn-OFF time

VSIG =±50V

VIN = Oto 15V
VSIG =±50V

vpp = 60V, Tc = 25°C)

Parameter

tON

Conditions

Min

25°C
Over temp
25°C
Over temp

Conditions

Figure 7

Ko
KCR

OFF isolation

-70

115
dB

Switch crosstalk

-75

dB

25°C,1MHz

CSW(OFF)

OFF capacitance across switch

1

pF

TA = 25°C, Vs = OV

CSG(OFF)

OFF capacitance SW to GND

17

pF

CSG(ON)

ON capacitance SW to GND

38

pF

100

pC

240

pC

VSIG = +50V
VSIG = OV

480

pC

VSIG = -50V

Charge injection

Q

25°C,1MHz

Recommended Operating Conditions
Symbol

Parameter

Min

Typ

Max

Units

VNN

Negative high voltage supply

-50

0

V

Vpp

High voltage supply

+20

+50

V

VIH
VIL

High-level input voltage

+12

+50

V

Low-level input voltage

-50

+3.5

V

0

+70

°C

-55

+125

°C

Operating temperature range

I

I

Commercial
Military Hi-Rei (RB)

11-89

HV341/HV343/HV345/HV348

Functional Block Diagrams and Pin Configurations
HV341
HV348

HV343

SW 1B

SW 1A
NC

At

NC

VNN

NC

GND

NC

NC

NC

Vpp

SW tA

SWtA
At

At

NC

SW 38

VNN

SW 38

VNN

GND

SW 3A

GND

SW48

NC

SW 4B

NC

Vpp

SW 4A

Vpp

A2

A2

NC
SW 2B

SW2A

SW28

HV345

A2

NC

SW2A

SW 2A

SW28

DualSPDT

Dual SPST

Dual DPST

Test Circuits

N.C.

---4---._.,.----+...:.:..-

N.C.
+1SV

:':SOV

N.C.

-SOY
13

13

4

N.C.

:':SOV

HV343
11

11

+SOV

10

+SOV

10

OFF Leakage Test Circuit

ON Leakage Test Circuit

1£1

~+1SV

s~Cl ~

V

15

---1_+--+--........ ..----+.:..::.;

VOUT1 ...

.n.:

SOV

VOUT 2 _-,_+-_3=+_-¥

-50V

ov

VOUT 1

--JI
I
-,
48V'

I
~tON

'--- t OFF

I
'+4BV
VOUT2~: . .•.

1KCl

50% " - t
~ . - tOFF
:
10%
:
OV

'90%
~
--.:

4

50%

--.:

,__ t ON
"
90%r-

10%~·

5W

HV343
11

+SOV

10

Switching Time Test Circuit

11-90

HV341/HV343/HV345/HV348

loon

,

100n

VOUT

Y,N

7sn

7sn

r---o
I

VOUT
7sn

14

N.C.

I

22V RMS
All MHz

-SOY

N.C.--"--l--"'-~A

13

4

HV343

11

N.C.--"-t------l

HV343
+SOV

10

Ko= 20 Log

lS
14

OV
-SOY

13

11

+SOV

10

VOUT
Y,N

OFF Isolation Test Circuit

Channel-Channel Crosstalk Test Circuit

N.C .
........, +lSV

VOUT - - - , - - - - ,

....J
-SOY
13

11
HV343
10

Q = 1000pF

x 11 VOUT

Charge Injection Test Circuit

11-91

+SOV

L-ov

22V RM S
All MHz

HV341/HV343/HV345/HV348

Typical Operating Characteristics
On-Resistance

On-Resistance VS. Switch lriput Voltage
140

140
Vpp = +20V
V NN = -20V

TA =1+2S0C
120

Vi
.!:!-

~

J

./

'iii
(l)

II:
I

40

c:

0

I

J:

.!:!-

I

~

-40

-20

0

V

V

'iii
(l)

II:
I

./
20

so

40

c:

0

40

20

-50

60

----

-25

0

Switching Time vs. Temperature

z

o

75

I
I

VNN = -SOY _-I-_+------,......~

Vi

9

50

1D

100

125

i"o

Y
c:

I:;r"""-+----i---I--+--__,r::::.

TA=25"C
RL = 7S0

Crosstalk

"

so

VNN = -SOY

vpp
= +SOV
'1'

~

400 f--t--t-c~"F-+

'0
.!!!.

0;

i"o

OFF Isolation

40

~

.!::!

1:::1"-

0

300

V S1G = -50V

OFF Isolation And Crosstalk VS. Frequency

80

500

25

100

600 f--t--+--:~"I""--+

LI..
LI..

-

~ I--

Temperature (OC)

800 , - - - , - - - , - - - , - - - - - , - - - - - , - - - - , - - . ,
Vpp = +SOV
700

VS1G= +50V

".,

Switch Input Voltage, VS1G(V)

.s

.....

./

80

(l)

u
c:

20

-60

100

E

J

60

V~

V NN = -50V

Vi

80

I

Vpp = +50V

100

(l)

u
c:

Temperature

120

Vpp= +SOV
V NN = -SOY

E

J:

VS.

I:;r"""-t------:==--'F'--+

'"

E
o

.s

~

j

1"'0,

20
200

f--t---::±--"I""=-+

100 L-_.l-_-I-_-I-_-L-_-L-_..I..._.J
-50

-25

0

+25

+50

+75

+100

106

+12S

Temperature (OC)
OFF Leakage vs. Switch Voltage
+30

«
«
.s

V

'E

"
(l)
C)

J2ca

-10

(l)

---'

-20

-

-40

-20

TA= +125"C (I'A)

"

-...........

()
(l)

l

TA= 2soiC (nA)

I

+10

~

J.......-- io""'"
I

+20

'E

./

- TA= +125"C (I' A)

()

«
«
.s

~

+10

~

ON Leakage vs. Switch Voliage
+30

Vpp =+SOV
VNN = -SOV

+20

107

Frequence (Hz)

-10

r---.....

(l)

---'

-30

i""'--

-20

(iA) """----TAZl2S0C

-30
-60

0

+20

+40

+SO

-so

-40

-20

0

+20

VS 1G Voltage (V)

VSIG Voltage (V)

11-92

+40

+so

HV341/HV343/HV34S/HV348

Applications Information
Analog Signal Range

Control Inputs

The HV341 family's analog signal range is equal to the power
supply value, up to ±SOV with split power supplies and +60V with
a single power supply (VNN connected to GND). An ON switch is
also capable of passing up to O.SA on a peak current basis.
Maximum continuous current is limited only by the package power
dissipation (see Absolute Maximum Ratings).

lSV logic level inputs are required to turn switches on or oft, but
the control inputs can also accept levels up to Vpp and V NN' An
input greater than 12V constitutes a "1" state (switch OFF), and an
input less than 3.SV will constitute a "0" state (switch ON).
Standard TTL logic can be used with HV341 series switches if a
level shifter such as the MC14S04 is used to drive the control
inputs as shown in Figure 1. Open collector drivers, with external
pull-up resistors, can be used in a similar fashion as well.

ON Resistance
The ON resistance of the MAX341 series switches is typically
400. RON does, however, increase as the switch voltage (VSIG)
approaches Vpp. For example, with ±SOV supplies and a +SOV
analog signal, RON will be typically less than 1000 (SOO for the
HV348), and 4S0 (2S0 for the HV348 for -SOV signals. With ±SOV
power supplies, and ±40V switch voltages, RON is about 400 for
the +40V case and 300 for the -40V case. ON resistance can be
reduced and current handling capacity can be increased by
connecting switches in parallel. This is especially useful in power
switching applications. Table 1 and the graph in the Typical
Characteristics section further describe the relation between RON
and Vpp.

Table 1 : ON Resistance
VPPIVNN

Note:

RON

at VS1G

=Vpp

RON

at VS1G

+20V/-20V

12m

+30V/-30V

10S0

360

+40V/-40V

920

320

=V

NN

390

+SOV/-SOV

840

300

+40V/GND

12m

390

+60V/GND

10S0

360

Typical RON for the HV348 is approximately one half of the above values.

Power Supply Current
The maximum supply current for Vpp and V NN at 2SoC is 3001!A
and 100~A, respectively. However, the positive supply current
(1+) is partly dependent on the input logic level and can be
reduced if control signals of a larger amplitude than OV and lSV
are used. If the control inputs swing to within 4V of Vpp and V NN
then 1+ drops to a typical value of 200~A.

+50V

tOOkn
15V

+5V

Vpp

TTL

2

15

4

10

I
I
I
I

--,

HV341
TTL

I
I
I
I

(2 of 6)
Vss
8

GND

MC14504B

Figure 1. Using TTL Control Levels

11-93

16

..

HV341/HV343/HV345/HV348
HV343
16
Differen1ial Signal ±10V
Common Mode Range ±50V (VSig )

15

CN
0.471lF

14

-50V

13

.----

11

i
i
1--i
i

+50V

+~V

10

OV
Sample/Hold

Figure 2. Flying Capacitor Differential to Single-Ended Converter With ±50V Common-Mode Range.

Flying Capacitor Input

Parallel Switches

A "flying capacitor" differential to single-ended converter takes
advantage of the HV343's wide input voltage range, which allows
large common mode inputs to be rejected. As shown in figure 2,
a capacitor is alternately charged by the differential input signal
and then is connected to an op-amp or A-to-D input. An instrumentation amplifier is not required since the output signal can be
referenced to ground. Sample-hold operation is also built into the
design and the HV343's break-before-make operation ensures
thatthe output sees only the differential portion olthe input signal.
A similar approach can also be used for single-ended to differential signal conversion as well.

In designs where power switching ability is needed, any of the HV
341 series switches can be connected in parallel to increase
current handling capability and reduce ON resistance. Applications such as ultrasonics, RF power, and DC motor drive are areas
where this is often important. An HV348 is shown in a parallel
configuration in Figure 3. The resulting SPST switch has a typical
RON of 120 (50 for signals more than 10V below Vpp ) and can
handle pulsed loads of up to 0.5 Amps. With ±50V power supplies,
the peak-to-peak signal range is still 100V, and 1OM Hz Signals
can be switched while maintaining typically -50dB of isolation.

HV348
16
15
14

-50V

13

I

,--0

·1

..,.v,

F·~'

+15V (OFF)
OV (ON)

I

Figure 3. Minimum RON (5 to 10n typ.) High Voltage Switch.

11-94

4

HV41
HV42

"-'-' §upertex inc.

Preliminary

32-Channel Serial To Parallel Converter
With P-Channel Open Drain Outputs
Ordering Information
Package Options
Device

44 J·Lead Quad
Ceramic Chip Carrier

44 J·Lead Quad
Plastic Chip Carrier

Ole In waffle pack

HV41

HV4122DJ

HV4122PJ

HV4122X

HV42

HV4222DJ

HV4222PJ

HV4222X

Features

General Description
The HV41 and HV42 are low voltage serial to high voltage parallel
converters wtih P-Channel open drain outputs. These devices
have been designed for use as drivers for AC electroluminescent
displays. They can also be used in any application requiring
multiple output high voltage current source capabilities such as
driving inkjet and electrostatic print heads, plasma panels, or
vacuum fluorescent displays.

D

Processed with HVCMOS'" technology

D

Output voltages to -225V

D

Source current minimum BOmA

D

Shift register speed BMHz

D

Strobe and enable inputs

D

CMOS compatible inputs

D

Forward and reverse shifting options

D

44-lead plastic and ceramic surface mount packages

D

Hi-Rei processing available

D

Can be used with the HV51 and HV52 to provide
200V push-pull operation

These devices consist of a 32-bit shift register and control logic to
perform the Output Enable and AII·ON functions. Data is shifted
through the shift register on the logic high to low transition of the
clock. The HV41 shifts in the counterclockwise direction when
viewed from the top of the package and the HV42 shifts in the
clockwise direction. A data output buffer is provided for cascading
devices. This output reflects the current status cif the last bit of the
shift register. Operation of the shift register is not affected by the
OE (Output Enable) or the STR (Strobe) inputs.

Absolute Maximum Ratings
Supply voltage,

V DO 1

Off state output voltage 1
Logic input levels1
Ground current2
Continuous total power dissipation 3

For applications requiring active pull down as well as pull up, the
HV41 and HV42 can be paired with the HV52 and HV51 devices,
respectively. The footprint of the HV41 output pins matches the
HV52 output pin footprint when the parts are mounted on opposite
sides of a PC Board. Similarly the HV42 output footprint matches
the HV51. The logic control and power pin locations do not match.

+O.5V to -15.5V
+O.5V to -250V
+O.5V to VDD - O.5V
1.5A
1200mW

Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
Notes: 1. All vo~ages are referenced to V55'
2. Duty cycle is limited by the total power dissipated in the package.

3. For operation above 25°C ambient, derate linearly to 85°C at 15mW/oC.

11-95

Electrical Characteristics

HV41/HV42

(over recommended operating conditions unless noted)

DC Characteristics (voltages referenced to Vss)
Max

Units

Conditions

'DD

Symbol

VDD supply current

-15

mA

fCLK = 4 MHz

IDOO

Quiescent VDD supply current

-50

ALL Y'N = OV
All SWS parallel
V,H = -12V
V,L = OV

Parameter

Min

FDATA = 2 MHz
'O(OFF)

Off state output current

-50

~
IlA

I'H

High-level logic input current

-1

IlA

I'L
VOH

Low-level logic input current

+1

High-level output data out

IlA
V

VOL

Low-level output voltage

Voc

VDD + 1.0V

I HVou,

-30.0

V

-1.0

V

I Dataout

HVout clamp voltage

+1.5

V

' Dout = -100~
' Hvout = -SOmA
IDou, = -100~
IOL = +SOmA

AC Characteristics (@ VDD = -12V, vss = OV)
Symbol

Parameter

Min

Max

Units

S

MHz

Conditions

fCLK

Clock frequency

fwHItWL

Clock width high or low

tsu

Data set-up time before- clock rises

50

ns

tH

Data hold time after clock rises

20 •

ns

tON

Turn ON time, HVout from enable

400

ns

tDHL

Delay time clock to data high to low

100

ns

tDLH

Delay time clock to data low to high

100

ns

Min

Nom

Max

Units

-10.S

-12

-13.2

V

+0.3

-225

V

VDD +2V
0

VDD
-2.0

V

125

ns

RL = 10K to -225V

Recommended Operating Conditions
Symbol

Parameter

VDD

Logic supply voltage

Voo
V,H

Output off voltage

V,L

Low-level input voltage (LOGIC "0")

fCLK

Clock frequency

TA

Operating free-air temperature

High-level input voltage (LOGIC "I")

4

I Commercial

I Military Hi-Rei (RB)

Note 1: All voltages are referenced to Vss'

11-96

V
MHz

-40

+70

°C

-55

+125

°C

HV41/HV42

Input and Output Equivalent Circuits
Vss o---_---~-

Vss - - - - - + - - -

Input <.J--------~Logic Inputs

High Voltage Output

Logic Data Output

Switching Waveforms
Data Input

',
<>

Data Valid

•

,

t su - - - - - . . 1, 4 - - - - - t H

VSS-12V

I

~~--------------~,

~

Vss

: ' ' ' - - - - - VSS-12V

----_.!

,,I
,
,,

~,"'-_ _ _ _ _ _ _ Vss
.,,

:

, - - - - - - - - Vss

-

I.

Data Out

Vss

~I

:••- - - t W H - - - - - - -••:t 4 . - - - - - t W L

Data Out

, _

:

-------------------~!---------'~
,

,
,

!-o---

VSS-12V

tDHL - - - - . :

VSS

~,,

Enable

VSS-12V

,

...- - - - - - - - - - - - - - VSS-12V

,,

HV OUT

tON

________________________

----.:
I
I , _ _ _ _ _ _ _ _ VSS

~;t

Voo

11-97

•

,

HV41/HV42

Functional Block Diagram
Vss
Strobe
Output Enable

Data Input

Clock
32-8it
Static Shift
Register

Data Out

Function Table
Inputs
Function
All on
~/H

elK

OE

STR

X

X

X

l

]I.

X

L

H

H orL

,I.

L

H

X

Horl

H

H

AllOT!
LoaO

DI

Output enable

Shift Reg

. .....
1

2 ...32

...
...
...

. ..

HorL

Notes:
X =Not relevant to the output state.
ft

= Dependent on previous stage's state before the last elK: High to low transition.

A logic high bit in the shift register will turn on the corresponding output when the strobe and output enable inputs are both high.

J. = High to low transition. ~12V to Vss
H = High level = ·12V
L

=Low level =OV

11-98

Outputs
HVOutputs
1

2 ...32

All On
AliuTT
unorUTT

...

On or Off •...•

Data Out

·

·
·

HV41/HV42

Pin Configurations
HV41
44 Pin J·Lead Package

HV42
44 Pin J·Lead Package

Pin

Function

Pin

Function

Pin

Function

Pin

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

HVout 17
HVout 18
HVout 19
HVout20
HVout21
HVout22
HVoul23
HVout24
HVoul25
HVout26
HVoul27
HVoul28
HVout29
HVoul30
HVout31
HVout32
N/C
DalaOul
N/C
N/C
N/C
N/C

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Output Enable
Clock

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

HVout 16
HVout 15
HVout 14
HVout 13
HVout 12
HVout 11
HVoull0
HVout9
HVoul8
HVout7
HVout 6
HVout5
HVoul4
HVout3
HVout 2
HVoull
N/C
Data Out
N/C
N/C
N/C
N/C

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Output Enable
Clock

Vss
Vee
Strobe
Data In
HVout 1
HVoul2
HVout 3
HVoul4
HVoul5
HVoul6
HVout 7
HVout8
HVout 9
HVout 10
HVout 11
HVoul12
HVout 13
HVoul14
HVout 15
HVout 16

Vss
Vee
Strobe
Data In
HVoul32
HVout31
HVout30
HVout29
HVout 28
HVout27
HVoul26
HVoul25
HVoul24
HVoul23
HVoul22
HVoul21
HVoul20
HVout 19
HVout 18
HVout 17

Package Outline
28

6

top view

44-pin J-Iead Package

11-99

..

4
'fU !!iupertex inc.

HV45
HV46

I

Preliminary

32-Channel Serial To Parallel Converter
with P-Channel Open Drain Outputs
Ordering Information
Device

Package Options

Recommended
Operating
Voo Max

44 J·Lead Quad
Ceramic Chip Carrier

44 J·Lead Quad
Plastic Chip Carrier

Die in Waffle Pack

-300

HV4530DJ

HV4530PJ

HV4530X

-220

HV4522DJ

HV4522PJ

HV4522X

-300

HV4630DJ

HV4630PJ

HV4630X

-220

HV4622DJ

HV4622PJ

HV4622X

HV45

HV46

Features

General Description

o
o
o
o
o
o
o
o
o
o

The HV45 and HV46 are low-voltage serial to high-voltage parallel converters with P-Channel open drain outputs. These devices
have been designed for use as drivers for AC-electroluminescent
displays. They can also be used in any application requiring
multiple output high-voltage current source capabilities such as
driving inkjet and electrostatic print heads, plasma panels, or
vacuum fluorescent displays.

Processed with HVCMOS Technology
Output voltages to -300V
Source current minimum 60 mA
Shift register speed 8 MHz
Polarity and blanking inputs
CMOS compatible inputs

These devices consist of a 32-bit shift register, 32 data latches,
and control logic to periorm polarity and blanking functions. Data
is shifted through the shift register on the logic high-to-Iow transition of the clock. The HV45 shifts inthe counterclockwise direction
when viewed from the top of the package and the HV46 shifts in
the clockwise direction. A data output buffer is provided for cascading devices. This output reflects the current status of the last
bit of the shift register. The data in the shift register is latched when
the latch enable pin is brought to logic high and then returned to
ground. If the latch enable pin is held high, the latch becomes
transparent and the shift register data is directly reflected in the
outputs.

Forward and reverse shifting options
44-lead plastic and ceramic suriace mount packages
Hi-Rei processing available
Can be used with the HV55 and HV56 to provide 300V
push pull operation

Absoiute Maximum Ratings
+0.5V to -16V

Supply voltage, VDO 1
Off state output voltage

HV4530/HV4630

+0.5V to -315V

HV45221 HV4622

+0.5V to -220V

Logic input levels 1
Ground currrent2
Continuous total power dissipation 3
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds

For applications requiring active pull down as well as pull up, the
HV45 and HV46 can be paired with the HV55 and HV56 devices,
respectively. The footprint of the HV45 output pins matches the
HV55 output pin footprint when the parts are mounted on opposite
sides of a PC Board.

+0.5V to VDO - 0.3V
1.5A
1200mW
-65°C to +150°C
260°C

Notes: 1. All voltages are referenced to VSS'
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25'C ambient, derate linearly to 70'C at 12mWI'C.

11-100

Electrical Characteristics

HV45/HV46

(over recommended operating conditions unless noted)

DC Characteristics
Symbol

Parameter

100

Voo supply current

Min

Max

Units

-15

mA

Conditions
fClK

= 4 MHz

FOATA = 2 MHz
IODO

Quiescent Voo supply current

-50

IlA

10(OFF)

Off state output current

-50

IlA

IIH

High-level logic input current

-1

III
VOH

Low-level logic input current

+1

IlA
IlA

High-level output data out

Val

Low-level output voltage

Voe

I HVOU!

HVout clamp voltage

AC Characteristics

VIH

V
-30.0

V

IHVOU! = -60mA

-1.0

V

IOOU! = -1001lA

+1.5

V

10l = +60mA

(V DD = 12V. T c = 25°C)

Symbol

Parameter

fClK

Clock frequency

tWH/tWl

Clock width high or low

125

ns

tsu

Data set-up time before clock rises

50

ns

tH

Data hold time 'after clock rises

20

ns

tON

Turn ON time. HVOU! from enable

400

ns

Rl

tOHl

Delay time clock to data high to low

100

ns

Cl

tOlH

Delay time clock to data low to high

100

ns

Cl

tOLE

Delay time clock to LE low to high

50

ns

'wlE

Width of LE pulse

50

ns

tSlE

LE set-up time before clock falls

50

ns

Min

Max

Units

8

MHz

Conditions

= 10K to Voo MAX
= 15pF
= 15pF

Recommended Operating Conditions
Symbol
Voo

Note 1:

Parameter

I
1

Output off voltage

VIH
Vil

High-level input voltage (LOGIC "1 ")

fClK

Clock frequency

Min

Max

Units

-13.2

V

HV4530 and HV4630

+0.3

-300

V

HV4522 and HV4622

+0.3

-200

V

Voo + 2V
0

Voo
-2.0

V

Commercial

-40

+70

°C

Military Hi-Rei (RB)

-55

+125

°C

Low-level input voltage (LOGIC "0")

Operating free-air temperature

(Note 1)

-10.8

Logic supply voltage

Voo

TA

= Voo

Vil = Vss
IOOU! = -1 OOIlA

Voo+1.0V

I Data out

VIN = Vss or Voo
All SWS parallel

4

I

I

All voltages are referenced to VS8.

11-101

V
MHz

HV45/HV46

Input and Output Equivalent Circuits
Vss O-t-------~-

Vss - - - - - - - 1 1 " " - -

Input O-o-'\I\A-T~

VOO

Data Out

0-----+-------'

VDO

Logic Inputs

Logic Data Output

High-Voltage Outputs

Switching Waveforms
Data Input

_______50,.,"->!<:

~ t su ------.-14--0--

I

Clock

>1<.

V 1L

50_%_"_____________

Data Valid

V 1H

t H -----..:

:

I

50O/\'....._------,/00%

\,,50%
;(:/0
....._----

,

,.

tWH

1
1
1
1
1

- - - - -.........:

/50%

I
Data Out

,

tWL

.. I-

,

,

I.

tOLH

1
I

..I

~50%

,,1
,,.
,,

tDHL

1
'1

1
Latch Enable

HV OUT
W SIR HIGH

:....--tON

11-102

V 1L

,
,
,
,

V 1H

1

VOL
V OH

HV4S/HV46

Functional Block Diagram
VSS
Polarity
Blanking
latch Enable
Data Input

Clock

32-Bit
Shift
Register

Data Out

Function Table
Inputs
Function

Data

eLK

LE

BL

POL

Allan

X

X

X

L

L

Alloff

X

X

X

L

H

Invert mode

X

X

L

H

L

H orL

.j,

L

H

H

Load
latches

X

H orL

H

H

X

H orL

t
t

H

L

Transparent
latch mode

L

.j,

H

H

H

H

.j,

H

H

H

Load SIR

Notes:
H. high level, l = low level, X • Irrelevant, .I- =law·ta-high transition, -12V to VSS'
• =dependent on previous stage's state before the last ClK .I- or last lE high.

11-103

Shift Reg
1

2 ... 32

Outputs
HV Outputs
1

2 ... 32

H

H ... H

L

L ... L

· ·......·
·· ··...··
... ·
·
·
...
·...· · ·......·
·· ·...·· · ·.. .·
·... · ··...·
·...·
·
...

H orL

L

H

··

L

H

··

Data Out

·
·

·
··
··
·
·

-

HV45/HV46

Pin Configurations
HV45
44 Pin J-Lead Package

HV46
44 Pin J-Lead Package

Pin

Function

Pin

Function

Pin

Function

Pin

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

HVout 17
HVout 18
HVout 19
HVout20
HVout 21
HVout22
HVout23
HVout24
HVout25
HVout26
HVout27
HVout28
HVout29
HVout30
HVout31
HVout32
N/C
Data Out
N/C
N/C
N/C
Polarity

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Clock

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

HVout 16
HVout 15
HVout 14
HVout 13
HVout 12
HVout 11
HVout 10
HVout9
HVout8
HVout7
HVout6
HVout5
HVout4
HVout3
HVout2
HVout 1
N/C
Data Out
N/C
N/C
N/C
Polarity

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

Vss
Voo
Latch Enable
Data In
Blanking
HVout 1
HVout2
HVout3
HVout 4
HVout5
HVout6
HVout7
HVout8
HVout 9
HVout 10
HVout 11
HVout 12
HVout 13
HVout 14
HVout 15
HVout 16

Package Outline

top view

44-pin J-Iead Package

11-104

44

Function
Clock
Vss
Voo
Latch Enable
Data In
Blanking
HVout 32
HVout 31
HVout 30
HVout29
HVout 28
HVout27
HVout 26
HVout25
HVout 24
HVout23
HVout 22
HVout21
HVout 20
HVout 19
HVout 18
HVout 17

~

HV500

"-" §upertex inc.

Preliminary

32-Channel AC Plasma Display Driver

Ordering Information
Device

40-Pin Ceramic
DIP

HV500

HV500D

40-Pin Plastic
DIP

Package Options
44-Pin J-Lead
Ceramic Chip Carrier

44-Pln J-Lead
Plastic Chip Carrier

Die

HV500P

HV500DJ

HV500PJ

HV500X

Features

General Description

o
o
o
o
o
o
o
o
o

The HV500 is a monolithic low-voltage logic to high-voltage output
32-channel driver for AC plasma flat panel displays. It is manufactured using the HVCMOS process, providing the high output voltages and currents possible with DMOS structures and the low
power dissipation of CMOS logic.

Processed with HVCMOS® Technology
Output voltage of up to 100V
CMOS push-pull output buffers
Low-power level shifting

The HV500 is comprised of an 8-stage DMOS shift register, four
groups of eight high-voltage output buffers, and logiC to select
which group of outputs will reflect the status of the data in the shift
register and strobe functions. When the strobe input is high, all
outputs are held low independent of any other logic input. When
strobe is brought low, the group of outputs selected by the state
of the select inputs reflects the data in the shift register, and all
non-selected outputs are held low.

Source/sink current minimum of 15mA
Shift register speed 8MHz
CMOS compatible inputs
Output clamp diodes to Vpp and GND
Direct replacement for the SN75500 and SN55500
series devices

o

44-lead plastic and ceramic surface mount
packages available

o

Hi-Rei processing available

The high-voltage output buffers have level shifters which dissipate no DC power. These level shifters also control the rise and
fall times of the outputs which have been optimized to lower
system noise without compromising the current source and sink
capability of the output buffers. Additionally, each output has low
Vfwd clamp diodes to Vpp and GND.

Absolute Maximum Ratings
Supply voltage, VDO '

-0.3V to +15V

Supply voltage, Vpp ,

-0.3V to +100V

Logic input levels'
Ground currrent2
Continuous total power dissipation 3

-0.3V to VDD + 0.3V
1.2A
1850mW

Operating temperature range

-55°C to +125°C

Storage temperature range

-65°C to +150°C

Notes: 1. All voltages are referenced to V55'
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C case temperature, derate linearly to 70"C at
15mWI"C.

11-105

_
_

Electrical Characteristics

HV500

(over recommended operating conditions unless noted)

DC Characteristics
Parameter

Symbol

Min

Max

Units

1

mA

Conditions

100
Ipp

V00 quiescent supply current
Vpp quiescent supply current

1

mA

HVOU! H or L

IIH

High-level input current

1

IJA

VIN = Voo

IlL

Low-level input current

-1
94

IJA
V

VIN = Vss
IOH=-1mA!

HVoutputs

90

V

IOH = -15mA'

Serial out

9

V

IOH = -1 00IJA2

2

V

IOL = 1mA

5

V

IOL = 15mA

1

V

10L = 100IJA2

High voltage output

2.5

V

10K = 20mN

Clamp voltage

-2.5

V

10K = -20mA3

VOH

VOL

High-level output voltage

HVoutputs

Low-level output voltage

Serial out
VOK
Notes: 1. vpp .100V
2. voo .10.8V
3. Vpp.ov

AC Characteristics (VDD = 12V, vpp
Symbol

= 100V, Tc = 25°C)

Parameter

Min

Max

Units

8

MHz

fMAX

Maximum clock frequency

tw

Clock pulse width high or low

62

ns

tOHL

Delay time strobe to HVOU! high to low

250

ns

tOLH

Delay time strobe to HVout low to high

250

ns

Set-uptime

Data in to clock l'

20

ns

tsu

Select before strobe .I-

50

ns

Data after clock l'

50

ns

Strobe high after clock l'

50

ns

Select after strobe l'

50

Hold time

tH

Conditions

CL = 30pF

ns

tR

Rise time low to high HVOU!

300

ns

tF

Fall time high to low HVOU!

200

ns

CL = 30pF
CL = 30pF

Recommended Operating Conditions
Min

-Max

Units

Voo
Vpp
VIH

Logic supply voltage

10.8

13.2

V

High voltage supply

0

100

V

High-level input voltage

0.75 Voo

V

VIL

Low-level input voltage

GND

Voo
0.25 Voo

Symbol

TA

Parameter

Operating free-air temperature

V

I

Commercial

-40

+80

°C

I

Military Hi-Rei (RB)

-55

+125

°C

11-106

HV500

Input and Output Equivalent Circuits
Voo

0-.--------.--

Vppo----~~--

Input O-O--'\I\A,.--,..-;

GND

HV out

0----4-----'--

GND

0--------+---High Voltage Outputs

Logic Inputs

Switching Waveforms
Data Input

;.,)!<:
,
I-+---

,

~50%

Clock

Data Valid

_ _ _ _ _ _ _5_00

t su

,

~..

V ,H

,

V'L

50_0;'_O_ _ _ _ _ _ _ _ _ _ _ __

~......--- t H _____..1

,,
,,
,

I

50%~'---------------------------------

,,

V'H
V'L

:...- - - tw - - - - . . : . - - tH ~:

Strobe

------------------------------------~~50%
,

V'H

50%)(

,, ------------ ,,
,,
,
,
,

,

~tsu~:

,,
Select

50-'O~

___________________________

..__________

~--------------_+---i
,,

tOLH :.

I
• I

I

10%:

I

I

I I tR
I

tOHL: • •
I

~'~------~

fi90%

-------------------------------------------------~"

11-107

V'L

>€

,
HV OUT

,
,,
,

t.....- t H -.. 1

11.:tF
I
I
I

90%~

V'H
V'L

I

,

i

~

VOH
VOL

..

HV500

Functional Block Diagram
0 - - - - - - - - - - - - - - - - 1 :>0----,

Strobe

101

Select 0

0------;
lOB

2-Lina to 4-Line
Decoder

201

Select 1

208
301

Rl

Data In

Clock

0------1

30B
8-Bit
Shift
Register

0------;

401

40B

RB

Function Table
Inputs
Select

Function

Load

Strobe

Internal Levels
Shift Register

101 ...108

HVOutputs
201 .. .208
301 .. .308

401 ...408

Data elk

S1

SO Strb R1

R2

i
i
X

X
X
X

X
X
X

H

L

R1n R2n .. .R7n

L.. .L

L. ..L

L...L

H

H

R1n R2n .. .R7n

L...L

L. ..L

L. ..L

L. ..L

H

R1n R2n R3n ...RSn

L ...L

L. ..L

L...L

L. ..L

H

L

L

L

R1n R2n R3n .. .RSn

RL.RS

L. ..L

L...L

L. ..L

H

L

H

L

R1n R2n R3n .. .RSn

L. ..L

R1 .. .RS

L ...L

L. ..L

H

H

L

L

R1n R2n R3n .. .RSn

L. ..L

L...L

R1 .. .RS

L. ..L

H

H

H

L

R1n R2n R3n ...RSn

L. ..L

L ...L

L. ..L

R1 ...RS

H
L

X
X
X
X
X

R3 ...R8

Notes:
H =high level, L =low level, X =irrelevant, t =low·to·high transition.
Rl ... RB = levels currently at internal outputs of shift registers one through eight, respectively.
A1n ... RBn -levels at shifi-rsyister outpuiS Ai through RS, respectively, before the most recent i transition of the clock.

11-10S

L...L

HV500

Pin Configurations
4O-Pin Dual-In-Llne
Pin Function
Pin

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Select 0
Data In
Clock

101
102
103
104
105
106
107
108
201
202
203
204
205
206
207
208
GND

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Function

Vpp
308
307
306
305
304
303
302
301
408
407
406
405
404
403
402
401
Strobe
Select 1

Voo

44 Pin J-Lead
Pin Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Pin

Function
N/C

101
102
103
104
105
106
107
108
201
202
203
204
205
206
207
208

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

GND

44

N/C
Select 0
Data In
Clock

N/C

Vpp
308
307
306
305
304
303
302
301
408
407
406
405
404
403
402
401
N/C
Strobe
Select 1

Voo

Package Outlines
40

20

21

top view

top view

40-pin DIP

44-pin J-Iead Package

11-109

4
"'-11 §upertex inc.

HV501

Preliminary

32-Channel AC Plasma Display Driver

Ordering Information
Device

40·Pin. Ceramic
DIP

HVS01

HVS01D

40·Pin Plastic
DIP

Package Options
44·Pin J·Lead
Ceramic Chip Carrier

44·Pin J·Lead
Plastic Chip Carrier

Die

HVS01P

HVS01DJ

HVS01PJ

HVS01X

Features

General Description

o
o
o
o
o
o
o
o
o

The HVS01 is a 32-channel low-voltage serial to high-voltage
parallel converter designed for use in matrix-addressable display
applications. It is manufactured with the HVCMOS technology for
enhanced ruggedness and performance. This device is a direct
replacement for the SN7SS01 family of devices.

Processed with HVCMOS® Technology
Output voltage of up to 100V
DMOS push-pull output buffers
Low-power level shifting

These devices are comprised of a 32-bit shift register with a serial
data out, strobe and sustain control logic, and level shifters with
high-voltage DMOS output buffers. When the strobe and sustain
outputs are held high the outputs are held high. Data can then be
clocked into the shift register without changing the state of the
outputs. When the strobe input is brought low with the sustain
input remaining high, the outputs will change state to reflect the
status of the data in each output's corresponding shift register bit.
A logic "1" in the shift register will cause the corresponding output
to pull up to VPP' and a logic "0" will cause the output to pull to GND.
The sustain input is used to bring all the outputs low. When the
sustain input is low, all outputs are low, independent of any other
control input.

Source/sink current minimum of 1SmA
Shift register speed 8MHz
CMOS compatible inputs
Output clamp diodes to Vpp and GND
Direct replacement for the SN7SS01 and SNSSS01
series devices

o

44-lead plastic and ceramic surface mount
packages available

o

Hi-Rei processing available

The high-voltage output buffers have low power level shifters
which dissipate no DC power. These level shifters also control the
rise and fall times of the outputs which have been optimized to
lower system noise without compromising the current source and
sink capability of the output buffers. Additionally, each output has
low Vfwd clamp diodes to Vpp and GND.

Absolute Maximum Ratings
Supply voltage, Vee l
Supply voltage, Vpp 1
Logic input levels1
Ground currrent2
Continuous total power dissipation 3

·0.3Vto+15V
-0.3V to +1 OOV
-0.3V to Vee + 0.3V
1.SA
18S0mW

Operating temperature range
Storage temperature range
Notes: 1. All voltages are referenced to V55'
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25'C case temperature. derate linearly to 70'C at
15mWI"C.

11-110

HV501

Electrical Characteristics

(over recommended operating conditions unless noted)

DC Characteristics
Symbol

Parameter

100

V00 quiescent supply current

1

rnA

Ipp

Vpp quiescent supply current

1

rnA

HVout H or l

IIH

High-level input current

1

~A

VIN = Voo

ill

low-level input current

-1

~A

VIN = Vss
10H = -1mA1

VOH

Min

HVoutputs

High-level output voltage

V
V

IOH = -15mA1

9

V

IOH= -100~A2

2

V

IOL = 1mA

5

V

IOL = 15mA

1

V

IOL = 100~A2

2.5

V

10K = 20mA3

-2.5

V

10K = -20mA3

Data out
VOK

Conditions

90

HVoutputs

low-level output voltage

Units

94

Data out
VOL

Max

High voltage output
Clamp voltage

Notes: 1. Vpp =100V
2. voo = 10.8V
3. vpp=OV

AC Characteristics (Voo = 12V, vpp = BOV)
Symbol

Parameter

Min

Max

Units

8

MHz

fMAX

Maximum clock frequency

tw

Clock pulse width high or low

62

ns

tsu

Data input set-up time before ClK

20

ns

tH

Data input hold time after ClK

50

tOHL

Delay time
High to low
level outputs

Conditions

ns

Strobe to HVout

250

ns

Sustain to HV out

250

ns

CL = 30pF
CL = 30pF

Serial out

147

ns

Cl = 30pF

Strobe to HVout

450

ns

Sustain to HV out

450

ns

CL = 30pF
Cl = 30pF

tOLH

Delay time
low to high
level outputs

147

ns

Cl = 30pF

tR

Rise time low to high HVout

300

ns

tF

Fal.l time high to low HVout

200

ns

CL = 30pF
CL = 30pF

Serial out

Recommended Operating Conditions
Symbol
Voo
Vpp
VIH
VIL

T'A

Min

Max

Units

logic supply voltage

Parameter

10.8

13.2

V

High voltage supply

0

100

V

Voo
0.25 Voo

V

°c
°c

High-level input voltage

0.75 Voo

low-level input voltage

GND

Operating free-air temperature

I
I

Commercial

-40

+80

Military Hi-Rei (RB)

-55

+125

11-111

V

HV501

Input and Output Equivalent Circuits
Voo

0-..--------..--

VOO--------~~--

Data Out

Input o-........VV'v-<.-....

GND

Vppo-_ _ _ _..-__

GND 0--------+----

o----~--------L--

GNDO-------~~--

Logic Data Output

Logic Inputs

High Voltage Outputs

Switching Waveforms
Data Input

Yk,

500

)1(,50%

Data Valid

------" ,

'
~ t su - - . : . . - - - t H

Clock

,

50'/~
,

,

/ 5, 0 %

....._ _ _ _ _ _ _, J

,, ••- - - - tw

,

,.

,,

-----o.~,..11 - - - - - t DLH - - -........~,

,

i

Data Out

"------------

----.:

,

/50%

----------------~I--------'
:'~.o_--- t DHL - - -........~,
,

\,,50%

,,

Sustain

,50%

50%;if

,,

,,,
Strobe

,

!....~--...,.~:

,
,
,
,,,
,

,
,,
\k,50%
,,

tOLH

!··-----·1, tDHL

HV OUT

w SIR LOW

HV OUT

w SIR HIGH

90%

10%
,
,
,
\----', , t F

90%

~ 10%

!......

10%

,,

90%

,
---,, :...... tR
,

10%

7

90%

11-112

50%/

,,

,
,
,

90%

,
,,

!.... -tDLH~,

tDHL -""1

10%

10%

HV501

Functional Block Diagram
Sustain
Strobe

Clock

Data Input
32-8it
Static Shift
Register

Data Out

Function Table
Inputs

Function

Load

Strobe
Sustain

Shift Register

Data

Clock

Strobe Sustain

H

H

L

i
i

X

HVOutputs

R1

R2

R3 ...R32

1

2

3 ...32

H

H

Rln

R2n ... R31 n

H

H

H ... H

H

H

L

Rln

R2n ... R31n

H

H

H ... H

X

H

H

Rln

R2n

R3n ...R32n

H

H

H ... H

X

H

L

H

Rln

R2n

R3n ... R32n

Rl

R2

R3 ... R32

X

X

X

L

R1n

R2n

R3n ...R32n

L

L

L ... L

Notes:
H =high level. L =low level. X =irrelevant. r =low-to-high transition.
R1 ... R32 = levels currently at internal outputs of shift registers one through 32, respectively.
R1n ...R32n = levels at shift-register outputs R1 through R32, respectively, before the most recent ftransition of the clock input.

11-113

HV501

Pin Configurations
40-Pln Dual-In-Line
Pin
Pin Function

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Vpp
HVoul17
HVout 18
HVout 19
HVout20
HVout21
HVout 22
HVout23
HVout24
HVout 25
HVout 26
HVout27
HVout28
HVout29
HVout30
HVout31
HVout32
Data Out
Data In
VDD

Clock
Sustain
Strobe
HVout 1
HVout2
HVout3
HVout4
HVout5
HVout 6
HVout7
HVout8
HVout9
HVout 10
HVout 11
HVout 12
HVout 13
HVout 14
HVout 15
HVout 16
GND

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

44 Pin J-Lead Package
Pin Function
Pin
1
N/C
23

Function
N/C

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Vpp
HVout 17
HVout 18
HVout 19
HVout20
HVout21
HVout22
HVout 23
HVout24
HVout 25
HVout26
HVout 27
HVout 28
HVout 29
HVout30
HVout 31
HVout32
N/C
Data Out
Data In
VDD

Clock
Sustain
Strobe
N/C
HVout 1
HVout2
HVoul3
HVout4
HVout5
HVout6
HVout7
HVout8
HVout9
HVout 10
HVout 11
HVout 12
HVout 13
HVout 14
HVout 15
HVout 16
GND

24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Package Outlines
40

20

-'-----~-

21

lop view

top view

40-pin DIP

44-pin J-Iead Package

11-114

4
'tlI §upertex inc.

HV51
HV52

32-Channel Serial To Parallel Converter
With Open Drain Outputs
Ordering Information
Device
HV51

44 J·Lead Quad
Ceramic Chip Carrier
HV5122DJ

HV52

HV5222DJ

Package Options
44 J·Lead Quad
Plastic Chip Carrier

Die in waffle pack

HV5122PJ

HV5122X

HV5222PJ

HV5222X

Features

General Description

D Processed with HVCMOS® technology

The HV51 and HV52 are low voltage serial to high voltage parallel
converters wtih open drain outputs. These devices have been
designed for use as drivers for AC electroluminescent displays.
They can also be used in any application requiring multiple output
high voltage current sinking capabilities such as driving inkjet and
electrostatic print heads, plasma panels, vacuum fluorescent, or
large matrix LCD displays.

D Output voltages to 225V using a ramped supply voltage
D Sink current minimum 100mA
D Shift register speed 8MHz
D Strobe and enable inputs

D CMOS compatible inputs

These devices consist of a 32-bit shift register and control logic to
perform the Output Enable and All-ON functions. Data is shifted
through the shift register on the high to low transition of the clock.
The HV51 shifts in the counterclockwise direction when viewed
from the top of the package and the HV52 shifts in the clockwise
direction. A data output buffer is provided for cascading devices.
This output reflects the current status of the last bit of the shift
register. Operation of the shift register is not affected by the OE
(Output Enable) or the STR (Strobe) inputs.

D Forward and reverse shifting options
D Replacements for SN75551 (HV5122) and SN75552
(HV5222) Row Drivers
D 44-lead ceramic surface mount package
D Hi-Rei processing available

Absolute Maximum Ratings
Supply voltage, V00 1
. Output voltage, Vpp2

-O.5V to +250V

Logic input levels

-O.5V to Voo + O.5V

Ground currrent3

1.5A

Continuous total power dissipation 4
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds

The HV51 and HV52 have been designed to be used in systems
which either switch off the high voltage supply before changing
the state of the high voltage outputs or which limit the current
through each output.

-O.5V to +18V

These devices are pin for pin replacements for the SN75551 and
SN75552 devices. In addition, Supertex HVCMOS technology
provides significantly higher speed and higher sink current capability in the HV51 and HV52 devices.

1500mW
-65°C to +150°C
260°C

Notes: 1. All voltages are referenced to V 5S'

2. These devices have been designed to be used in applications which
eilher swilch Ihe V pp supply 10 ground before changing the slale of Ihe
high voltage oulpuls or limil the current Ihrough each oulput.

3. " Duty cycle is limited by the total power dissipated in the package.
4. For operation above 25°C ambient, derate linearly to 700 e at 12mWfOC.

11-115

~

Electrical Characteristics

HV51/HV52

(over recommended operating conditions unless noted)

DC Characteristics
Symbol
100

Parameter

Min

Typ

Max.

Units

15

mA

V00 supply current

Conditions

= 8MHz
= 4MHz
All Y'N = OV

fCLK

FOATA

1000

Quiescent V00 supply current

0.5

mA

IOIOFF)

Off state output current

10

!LA

All outputs high
All SWS parallel

I'H
I'L
VOH

High-level logic input current
Low-level logic input current

1
-1

!LA

V,H = 12V
V,L = OV

V

loout

15.0

V

IHvout = +1OOmA
loout = +1 OO!LA
IOL = -100mA

High-level output data out

VOL

Low-level output voltage

Voc

HVOUT Clamp Voltage

AC Characteristics

!LA

Voo -1.0V

I HVoUT

J Data out

1.0

V

-1.5

V

Max

Units

8

MHz

= -1 OO!LA

(Voo = 12V, Tc = 25°C)

Symbol

Parameter

Min

Typ

fCLK

Clock frequency

tw

Clock width high or low

62

tsu

Data set-up time before clock falls

25

ns

tH

Data hold time after clock falls

10

ns

tON

Turn ON time, HVoUT from enable

500

ns

tOHL

Delay time clock to data high to low

100

ns

tOLH

Delay time clock to data low to high

100

ns

Conditions

ns

RL = 2Kn to 200V

Recommended Operating Conditions
Symbol

Parameter

Voo
Vpp

Logic supply voltage
High voltage supply

V'H

High-level input voltage

V'L
fCLK

Low-Ievei input voltage
Clock frequency

TA

Operating free-air temperature

Min

Typ

Max

Units

10.8

12

15
225

V
V

Voo
2.0

V

-0.3
Voo - 2V
0

8

I
I

Commercial
Military Hi-Rei (RB)

11-116

V
MHz

0

+70

°C

-55

+125

°C

HV51/HV52

Input and Output Equivalent Circuits
Voo ~-------t--

Voo - - - - - - - f - -

Input O-+-'V'v"v--.----f

GND

Data Out

--~---4---

GND

0-----"-High-Voltage Outputs

Logic Data Output

Logic Inputs

Switching Waveforms

, . . - - - - - - - - 12V
50%
- -- - - - ---OV

CLOCK
DATA __________________4-________

~

OUT

50%

DATA
OUT------------------~--------J

-y- 50%
ENABLE - - - - - - - - - - - - - - - - - - - - ' ,

~tON---..

HVOUT

--------------------+-----------,.

Jr-- 15V

11-117

HV51/HV52

Functional Block Diagram
Strobe
Output Enable

0-------------1
0-------------..,

Data Input

Clock

32·bl.

28 Additional

static shift
register

Outputs

I
I

rHVOU.31
-o

L - -_ _ _ _ _ _

r-"

DataOut

Function Table
Inputs
Function
All on
All off
Load SIR
Output enable

Shift Reg

Outputs
HV Outputs

01

eLK

OE

STR

X
X

X
X

X

L

L

H

H orL

.j.

L

H

H orL

X

H orL

H

H

H orL

Lor H

Notes:
X =Don't care
• =Dependent on previous stage's state before the last elK: High to low transition.
J, =High to low transition
H • High level
l . low level

11-118

. ·...·
. ·...·
·......·
··
1

2 ...32

1

2 ...32

L

L ... L

H

H ... H

H

H ... H

.....

OataOut

··
·
·

HV51/HV52

Pin Configurations
HV51
44 Pin J·Lead Package

HV52
44 Pin J·Lead Package

Pin

Function

Pin

Function

Pin

Function

Pin

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

HVout 16
HVout 17
HVout 18
HVout 19
HVout20
HVout21
HVout22
HVout23
HVout24
HVout25
HVout26
HVout 27
HVout 28
HVout29
HVoul30
HVoul31
HVoul32
DalaOul

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

Output Enable
Clock
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

HVout 17
HVout 16
HVout 15
HVout 14
HVout 13
HVout 12
HVout 11
HVout 10
HVout 9
HVout8
HVout7
HVout6
HVout5
HVoul4
HVoul3
HVoul2
HVoul1
DalaOul

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Output Enable
Clock
GND

N/C
N/C
N/C
N/C

Voo
Strobe
Data In

N/C
HVout 1
HVout2
HVout3
HVout4
HVout5
HVout6
HVoul7
HVoul8
HVoul9
HVoul10
HVoul11
HVoul12
HVoul13
HVoul14
HVout 15

44

N/C
N/C
N/C
N/C

Voo
Strobe
Data In

N/C
HVout32
HVout31
HVout30
HVoul29
HVoul28
HVoul27
HVoul26
HVoul25
HVoul24
HVoul23
HVoul22
HVoul21
HVoul20
HVoul19
HVoul18

Package Outline
28

40

7

8

9 10 11 12 13 14 15 16 17

top view

44-pin J-Iead Package

11·119

..

a

-

HV53
HV54

"-11 !!iupertex .nc.
32-Channel Serial To Parallel Converter
With High Voltage Push-Pull Outputs
Ordering Information
Device

Recommended
Operating Vpp max

44 J-Lead Quad
Ceramic Chip Carrier

Package Options
44 J-Lead Quad
Plastic Chip Carrier

Die in waffle pack

SOV

HV530SDJ

HV530SPJ

HV530SX

80V

HV5308DJ

HV5308PJ

HV5308X

SOV

HV540SDJ

HV540SPJ

HV540SX

80V

HV5408DJ

HV5408PJ

HV5408X

HV53
HV54

Features

General Description

o
o
o
o
o
o
o
o
o
o

The HV53 and HV54 are low voltage serial to high voltage parallel
converters wtih push-pull outputs. These devices have been
designed for use as drivers for AC-electroluminescent displays.
They can also be used in any application requiring multiple output
high voltage current sourcing and sinking capabilities such as
driving plasma panels, vacuum fluorescent, or large matrix LCD
displays.

o
o

Processed with HVCMOS® technology
Output voltages up to 80V using a ramped supply voltage
Low power level shifting
Source/sink current minimum 20mA
Shift register speed 8MHz
Latched data outputs

These devices consist of a 32-bit shift register, 32 latches, and
control logic to enable outputs. HVoutl is connected to the first
stage of the shift register through the Output Enable logic. Data is
shifted through the shift register on the high to low transition olthe
clock. The HV54 shifts in the counterclockwise direction when
viewed from the top of the package and the HV53 shifts in the
clockwise direction. A data output buffer is provided for cascading
devices. This output reflects the current status of the last bit of the
shift register (32). Operation of the shift register is not affected by
the LE (latch enable) or the OE (output enable) inputs. Transfer
of data from the shift register to the latch occurs when the LE input
is high. The data in the latch is retained when LE is low.

CMOS compatible inputs
Forward and reverse shifting options
Diode to VPP allows efficient power recovery
Replacements for SN75553 (HV530S), SN75554
(HV540S), SN75555 (HV5308) AND SN7555S
(HV5408) Column Drivers
44-1ead ceramic surface mount package

Hi-Rei processing available

These devices are pin for pin replacements for the SN75553 and
SN75554, SN75555 and SN7555S. In addition, Supertex
HVCMOS technology provides significantly iroved power consumption, speed, and source/sink current capability in the HV53
and HV54 devices.

Absolute Maximum Ratings
Supply voltage, VDD t

-0.5V to +18V

Supply voltage, Vpp

-0.5V to +250V

Logic input levels t
Ground currrent2
Continuous total power dissipation3

-0.5 to VDD + 0.5V
1.5A
1500mW

Storage temperature range
Lead temperature I.Smm (IllS inch)
from case for 10 seconds
Notes: 1. All voltages are referenced to Vss'
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C ambient, derate linearly to 70°C at t2mWrC.

11-120

HV53/HV54

Electrical Characteristics

(over recommended operating conditions unless noted)

DC Characteristics
Symbol

Units

Conditions

15

mA

fCLK = 8MHz

0.5

mA

Outputs High

0.5

mA

Outputs Low

0.5

mA

All VIN = OV

52

V

10= -20mA

52

V

10 = -15mA

10.5

V

10 = -100jlA

8

V

10 = 20mA

8

V

10 = 15mA

1

V

10 =100jlA

IIH

High-level logic input current

1

j.tA

V IH = Voo

IlL

Low-level logic input current

-1

jlA

V I = OV

Max

Units

110

ns

100

Parameter

Min

Typ

Max

VDO supply current

Voo = Voo max
Ipp

High voltage supply current

looa

Quiescent V DO supply current

VOL

Low-level output

I Commercial

oUll Military

HV

Data out

I Commercial

HV
VOH

High-level output

oUll Military

Data out

AC Characteristics (@
Symbol

V DD = 12V, vpp = 60V, Tc = 25°C)

Parameter

Min

Typ

Conditions

tOHL

Delay time, high to low data out from clock

tOLH

Delay time, low to high data out from clock

ns

C L = 10pF

tsu

Data set-up time before clock rises

25

ns

C L = 10pF

tH

Data hold time after clock rises

10

ns

C L = 10pF

110

CL = 10pF

Recommended Operating Conditions
Symbol
Voo
Vpp

Parameter
Logic supply voltage
High voltage supply

Min

Typ

Max

Units

10.8

12

13.2

V

I

HV5306 and HV5406

-0.3

60

V

I

HV5308 and HV5408

-0.3

80

V

Voo - 2V

VIH

High-level input voltage
Low-level input voltage

0

Voo
2.0

V

V IL
fCLK

Clock frequency

0

8.0

MHz

TA

Operating free-air temperature

I

I

Commercial
Military Hi-Rei (RB)

11-121

V

0

+70

°C

-55

+125

°C

HV53/HV54

Input and Output Equivalent Circuits
V DD

0 - - . - - - - -__-

V DD

-------t--

vpp

I
Input O4--'V\,,.,,.....---+

Data Out

HV out

i
GND 0 - - - - - - - - 0 - -

GND - - - - - - O - - - - - + - - -

GND

Logic Data Output

Logic Inputs

High Voltage Outputs

Switching Waveforms
~tw

CLOCK --""""'\

\

t

50%

I

50%

-----.J
--=-=
I
\ , 50%

1+=1w~

~tsu~tH~
I ~1If"""l1lf"""l1l""""l~l""'7VDD

~1'""'II~1""'1II1""'1II_1

DATAIN~

VALID

f"5-D-%~--""'\
CLOCK

---.....I.

~DV

----------

I

DV

--1tDLHI"~_ _ _ _ _ _ _ _ _ ___

/50

_____1_..1
DATA OUT

-.l

VOD

%

tDHLj.-

\50%

11-122

HV53/HV54

Functional Block Diagram
Vpp

0-----------------,
Latch Enable 0-------------,

Output Enable

Data Input

HVout'

Clock

HVout 2

32·bit
static

32
Latches

shift
register

HVout 31

HVout 32

GND

Function Table
Inputs
Function

All of!
Load SIR
Load latches
. Latch mode

01

elK

X

X

H orL

Outputs

-

lE

OE

l

l'

X
X

X

X

HorL

l'

X

X

X

L

H

Shift Reg

1

·
·
·

HorL

x =Don't care.

* = Dependent on previous stage's state before the last elK: or last LE high and status of DE.
t = low·to·high transition.
H = High level .
. L = Low level.
1 = When output enable is high.
2 = Data oul takes the same state as the 32nd shift register stage.

11-123

latch

HVOutputs

·......· .. .......... . .....
·...·
. .....
·...·
··

2 ...32

1

2 ...32

1

2 ...32

l

L ... L

New Data

Stored Data

Stored Data'

Data Out

2
2
2
2

•

HV53/HV54

Pin Configurations
HV53
44 Pin J-Lead Package

HV54
44 Pin J-Lead Package

Pin

Function

Pin

Function

Pin

Function

Pin

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

HVout 17
HVout 16
HVout 15
HVout 14
HVout 13
HVout 12
HVout 11
HVout 10
HVout9
HVout8
HVout 7
HVout6
HVout5
HVout4
HVout3
HVout 2
HVout 1
Data Out
N/C
N/C
N/C
Clock

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

GND
Vpp
Voo
Latch Enable
Data In
Output Enable
N/C
HVout32
HVout31
HVout30
HVout29
HVout28
HVout27
HVout26
HVout25
HVout24
HVout23
HVout22
HVout21
HVout20
HVout 19
HVout 18

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

HVout 16
HVout 17
HVout 18
HVout 19
HVout20
HVout21
HVout 22
HVout 23
HVout24
HVout25
HVout26
HVout 27
HVout28
HVout29
HVout30
HVout31
HVout32
Data Out
N/C
N/C
N/C
Clock

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

GND
Vpp
Voo
Latch Enable
Data In
Output Enable
N/C
HVout 1
HVout2
HVout3
HVout4
HVout5
HVout6
HVout7
HVout8
HVout9
HVout 10
HVout 11
HVout 12
HVout 13
HVout 14
HVout 15

Package Outline
40

top view

44-pin J-Iead Package

11-124

~

HV55
HV56

"-11 !!iupertex inc.

Preliminary

32-Channel Serial To Parallel Converter
With Open Drain Outputs
Ordering Information
Package Options
Device

Recommended
Operating Vpp max

44 J-Lead Quad
Ceramic Chip Carrier

44 J-Lead Quad
Plastic Chip Carrier

Die in waffle pack

300V

HV5530DJ

HV5530PJ

HV5530X

HV55
HV56

220V

HV5522DJ

HV5522PJ

HV5522X

300V

HV5630DJ

HV5630PJ

HV5630X

220V

HV5622DJ

HV5622PJ

HV5622X

Features

General Description

o
o
o
o
o
o
o
o
o
o

The HV55 and HV56 are low-voltage serial to high-voltage
parallel converters wtih open drain outputs. These devices have
been designed for use as drivers for AC-electroluminescent
displays. They can also be used in any application requiring
multiple output high voltage current sinking capabilities such as
driving inkiet and electrostatic print heads, plasma panels,
vacuum fluorescent, or large matrix LCD displays.

Processed with HVCMOS® technology
Output voltages up to 300V using a ramped supply voltage
Sink current minimum 100mA
Shift register speed 8MHz
Polarity and Blanking inputs
CMOS compatible inputs

These devices consist of a 32-bit shift register, 32 latches, and
control logic to perform the polarity select and blanking of the outputs. Data is shifted through the shift register on the high to low
transition of the clock. The HV55 shifts in the counterclockwise
direction when viewed from the top olthe package, and the HV56
shifts in the clockwise direction. A data output buffer is provided
for cascading devices. This output reflects the current status of
the last bit of the shift register. Operation of the shift register is not
affected by the LE (latch enable), BL (blanking), or the POL
(polarity) inputs. Transfer of data from the shift registerto the latch
occurs when the LE (latch enable) input is high. The data in the
latch is stored when LE is low.

Forward and reverse shifting options
Diode to VPP allows efficient power recovery
44-lead ceramic surface mount package
Hi-Rei processing available

Absolute Maximum Ratings
-O.5V to + 18V

Supply voltage, V DD'
Output voltage, V pp ,

HV5530/HV5630

-O.5V to +315V

HV5522/HV5622

-O.5V to +220V

Logic input levels'
Ground currrent2
Continuous total power dissipation 3

-O.5V to V DD + O.5V
1.5A
1500mW

Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from c~se for 10 seconds
Notes: 1. All voltages are referenced to Vss.
2 Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25'C ambient. derate linearly to 70'C at 12mW/,C.

11-125

Electrical Characteristics

HV55/HV56

(over recommendedoperaling condilionS unlessnoled)

DC Characteristics
Symbol

Parameter

100

V00 supply current

1000

Quiescent V00 supply current

IO(OFF)

Off state output current

Min

Max

Units

Conditions

15

mA

feLK = 8MHz

0.05

mA

10

J.lA

Y'N = OV
All outputs high

FOATA

= 4MHz

All SWS parallel
I'H

High-level logic input current

1

J.lA

I'L
VOH

Low-level logic input current

-1

J.lA

High-level output data out

VOL

Low-level output voltage

Voe

HVOUT clamp voltage

I HVOUT

Voo -l.0V
15.0

V,H = Voo
V,L = OV
loou, = -1 OOJ.lA

V
V

IHvou, = +1OOmA

1.0

V

-1.5

V

loou' = +1OOJ.lA
10L = -100mA

I Dataout

AC Characteristics (Voo = 12V, Tc = 25°C)
Symbol

Min

Parameter

Max

Units

8

MHz

feLK

Clock frequency

tw

Clock width high or low

62

ns

tsu

Data set-up time before ciock falls

25

ns

tH

Data hold time after clock falls

10

tON
tOHL

Turn on time, HVOUT from enable
Delay time clock to data high to low

tOLH

Delay time clock to data low to high

tOLE

Delay time clock to LE low to high

50

ns

tWLE

Width of LE pulse

50

ns

tSLE

LE set-up time before clock falls

50

ns

Conditions

ns

=2Kn to Vpp MAX

500

ns

RL

100

ns

CL = 15pF

100

ns

CL =15pF

Recommended Operating Conditions
Symbol

Parameter

Voo

Logic supply voltage

Vpp

High voltage supply

V,H
V,L

High-level input voltage

feLK

Clock frequency

TA

Operating free-air temperature

I
I

Min
10.8

Max
15

Units
V

HV5530 and HV5630

-0.3

+300

V

HV5522 and HV5622

-0.3

+200

V

Voo - 2V

Voo
2.0

V

Low-level input voltage

0

8

I

I

Commercial
Military Hi-Rei (RB)

11-126

V
MHz

0

+70

°C

-55

+125

°C

HV55/HV56

Input and Output Equivalent Circuits
VOO

0-K:50~o/.~O~~~~~~~~~~~~~~~~~~~~~~~~~~

Data Valid

----":-4-t H ________
,
'

I

I

1

:

,

,
I

:

V OH

;(50%

~I--------------J

~----

tOLH -------<.~,

tOHL

~50%
,

VOH
VOL

-I

V'H
/50%

Latch Enable
f - - - tDLE

,
HV OUT
w SIR LOW

HV OUT

w SIR HIGH

11-132

).,50%
,,
,
,
---...:~
t
".'
,,
,
,,
,,,
~o
,,I , 10%
,,,
,,
:-toFF
-,, ':'
,,
,,
,
tO% Jtfeo%
,,
,,
,,
,'_tON~,
,
,
tWLE

,
,

VOL

SLE-----:

VOH
VOL

VOH
VOL

HV57/HV58

Functional Block Diagram
Vpp

Polarity
Blanking
Latch Enable
HV OUT1

Data Input

Clock

HVOUT2

32-Bit
Shift
Register

HVOUT32

Data Out

Function Table
Inputs
Function

Outputs

Data

eLK

IT

BL

POL

All on

X

X

X

L

L

Allof!

X

X

X

L

H

Invert mode

X

X

L

H

L

H orL

i

L

H

H

X

H orL

H

H orL

i
i

H

X

H

L

L

i

H

H

H

H

i

H

H

H

Load SIR
Load
latches
Transparent
latch mode

Notes:
H = high level, L = low level, X ::: irrelevant, i ::: low-ta-high transition .
• = depsndent on previous stage's state before the last CLK or last IE high,

11-133

Shift Reg
1

2 ... 32

· ·......·
· ··
· ··......··
· ·......·
· ·...·
··...··

H orL

L

H

HVOutputs
1

2 ... 32

H

H... H

L

L... L

·...
·· ·......··
· ··
· ·......·
··...··
L

H

Data Out

·
·
·
·
·
··
··

•

HV57/HV58

Pin Configurations
HV53

HV58

44 Pin J-Leacl Package

44 Pin J-Lead Package

Pin

Function

Pin

Function

Pin

Function

Pin

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

HVoul17
HVoul16
HVoul15
HVoul14
HVoul13
HVout 12
HVoul11
HVoul10
HVoul9
HVout8
HVoul7
HVout6
HVoul5
HVoul4
HVoul3
HVoul2
HVout 1
Data Out

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

GND
Vpp
Voo
Lalch Enable
Dala In
Blanking

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

HVoul16
HVoul17
HVoul18
HVoul19
HVout20
HVout21
HVoul22
HVoul23
HVoul24
HVoul25
HVout26
HVoul27
HVout28
HVoul29
HVout30
HVoul31
HVoul32
DalaOut

23
24
25
26
27.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

GND
Vpp
Voo
Lalch Enable
Data In
Blanking

N/C
N/C
Polarity
Clock

44

N/C
HVoul32
HVoul31
HVout30
HVoul29
HVout28
HVoul27
HVout26
HVoul25
HVoul24
HVoul23
HVoul22
HVoul21
HVout 20
HVout 19
HVout 18

Package Outline

top view

44-pin J-Iead Package

11.-134

N/C
N/C
Polarity
Clock

44

N/C
HVoul1
HVoul2
HVoul3
HVoul4
HVoul5
HVoul6
HVoul7
HVout8
HVout9
HVout 10
HVout 11
HVoul12
HVoul13
HVoul14
HVout 15

~

HV60

"--'-' §upertex inc.

Preliminary

32-Channel ±40V Liquid Crystal Display Driver

Ordering Information
Package Options
Device

Plastic

80-Lead Plastic
Quad Gullwing

Die

48-Pin DIP

Ceramic
48-Pin DIP

HV6008P

HV6008D

HV6008PG

HV6008X

HV6008

Features

General Description
The HV60 is a 32-channei liquid crystal display driver with 3-state
DMOS outputs. Each output can be set to +40V, -40V, or ground.
A symmetric waveform can be applied to a capacitive load using
the phase shift feature of the HV60.

0

Symmetrical ±40V output swing

0

Active return to GND

0

15mA peak source/sink/GND current per channel

0

±5V control logic

0

Special shift register with clear

0

Phase shift control

0

Output enable

0

Data out enable

0

1MHz shift register

0

Surface mount package available

The HV60 consists of a 32-bit shift register with Clear, Enable, and
Phase Shift logic, and 32 high voltage output buffers. With the
Enable pin held low, all outputs are placed in the return to zero
(GND) state. When Enable is high, each output reflects the data
in its shift register bit. All outputs with a logic "0" in their shift
register will be in the return to zero state. Outputs with a logic "1"
in their shift register will reflect the state of the phase shift pin.
These outputs will be switched to V pp when phase shift is high and
V NN when phase shift is logic "0".
Additional functions provided are shift register clear and data out.
All bits of the shift register are changed to logic "0" when clear is
pulled low. With clear at a logic "1 ", normal shift register operation
proceeds. The data output reflects the status of the 32nd shift
register stage.

Absolute Maximum Ratings
Supply voltage, V001 1

-6

Supply voltage, V002 1

+6

Supply voltage, Vpp l.2

+42V

Supply voltage, VNN 1.2

-42V

Logic input levels

V DO + 0.3V to V 002 + 0.3V

Ground currrent2

700mA

Continuous total power dissipation3

1W

Operating temperature range
Storage temperature range

-65°C to + 150°C

Notes: 1. All voltages are referenoed to Vss'
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25'C ambient, derate linearly to 85'C at 15mWI"C.

11-135

..

Electrical-Characteristics

HV60

(over rec6mmended operating conditionsl.lhless noted),

DC Characteristics
" Symbol

,
Parameter

'

Min

Typ

Max

I V001

1001 ,2

VDO supply current

VIH
Vil

Logic input high

+2

Logic input low

VOOI

VOH

Logic output high

VOL

Logic output low

I V002

,",'

Units'

SOO

!iA

V002
-2

V
V

.":

Conditions
VI = 4V, V001 = -6V
VI = 4V, VOD2 = +6V
VOOI = -4.SV
V002 = +4.SV

V

VOOI =-4.SV
V002 = +4.SV

-2

V

10H = -1S!iA
10l = 2S0llA

+2

IIH

High-level logic input current

+3

!iA

VI = Voo ' VOOI ,2 = max

III
Ipp

Low-level logic input current

-SO

High voltage supply current

+1

!iA
mA

VI = OV, VOOI ,2 = max
Static, no load

INN
VOH

+1

mA

StatiC, no load

Output voltage high

+39

Vel

Output voltage clamp

-20

VOL

Output voltage low

High voltage supply current

V

ZOH

Output switch impedence high

ZCl

Output switch impedance clamp

SOO

ZOl

Output switch impedance low

700

10

DC output current

+20

mV

-39

V

Vpp, VNN = ±40
loutput = 0.0

1000

n

I Output H or L
I Data out H or L

S

mA

1S0

!iA

Vpp' VNN = ±40
10 = ±1SmA
1 output only

AC Characteristics
Symbol

Parameter

Min

Typ

tWH

Width of high clock phase

TBD

tWl

Width of low clock phase

TeO

tsu

Data set-up time before clock rises

tH

Data hold time after clock rises

Max

Units

Conditions

TBD
0

Phase shift duty cycle

ns
SO

%

Recommended Operating Conditions
Symbol

Min

Parameter

Typ

Max

Units

VOOI
VOO2

Logic supply voltage

-4

-6

V

Logic supply voltage

+4

+6

V

Vpp
VNN

High voltage supply

+40
-40

V

High voltage supply

+10
-10

VIH
Vil

High-level input voltage

+2V

V

Low-level input voltage

-2V

VOO2
VOOI

10pk.

Peak output current (any state)

±80

mA

TA

Operating free-air temperature

fOIN
fps

Input data rate

1

MHz

Phase shift rate

1

MHz

-10

11-136

+70

V
V
°C

HV60

Switching Waveforms
+5V

Clock
-5V

+5V
Phase
Shift

-5V

+5V
SR#1
-5V

J

+5V
SR#2
-5V

+5V
SR#3
-5V

V NN ------------

Vpp

OUT #2

OV

V pp

OUT#3

OV

11-137

HV60

Functional Block Diagram
Phase
Shifter

0----------------,

Enable

0----------,

Data IN

0----,

Vpp

32
Bit
Shift
Register

L - - - - - - - - - o Data OUT

Function Table
Inputs
Function

Data
In

ClK

ClR

Outputs
Enable

Phase
Shift

Shift Reg
1

2 ... 3::>
ALLL

. .....

CLR Reg

X

X

L

X

X

All output GND

X

X

X

X

H orL

l'

H

L
L

X

L

L. .. L

X

HorL

H

H

H

H

H... H

L

L

L. .. L

Load SIR
Output State

Notes:
X.Don1care
• =Dependent on previous stage's state before the last elK
j = low to high transition
H • High level
l. low level

11-138

X

HVOutputs

1

2 ... 32
ALLGND
ALLGND

H or L .....

ALLGND
GND GND ... GND
Vpp
VNN

Vpp ... Vpp
VNN""VNN

Data Out
L

·
·
·
·
·

HV60

Pin Ccmfigurations
28·Pln J-Lead
Pin Function

Pin

Function

Pin

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54

Phase Shift
N/C
Clock
N/C
N/C
Clear
N/C
-5V
Enable
N/C
+5V
N/C
GND
N/C
Data Out
N/C
N/C
HVout32
HVout31
HVoul30
HVout29
HVout28
HVout27
HVout26
HVoul25
HVoul24
N/C

55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71

GND
N/C
N/C
N/C
N/C
N/C
-40V
N/C
+40V
N/C
N/C
HVout9
HVout8
HVout7
HVout6
HVout5
HVout4
HVoul3
HVout2
HVout 1
N/C
N/C
Data In
N/C
GND
N/C
N/C

72
73
74
75
76

77
78
79
80

Function
N/C
+40V
N/C
-40V
N/C
N/C
N/C
N/C
N/C
GND
N/C
HVout23
HVout22
HVoul21
HVout 20
HVout 19
HVoul18
HVoul17
HVoul16
HVout 15
HVout 14
HVoul13
HVoul12
HVout 11
HVoul10
N/C

48·Pln DIP
Pin Function

Pin

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

V001 (-5V)
Enable
V002 (+5V)
GND
Data Out
HVoul32
HVout31
HVout30
HVout29
HVout28
HVout27
HVout26
HVoul25
HVout24
Vpp
VNN
GND
HVout23
HVout22
HVout21
HVout20
HVout 19
HVout 18
HVoul17

HVout 16
HVout 15
HVout 14
HVout 13
HVout 12
HVout 11
HVout 10
GND
VNN
Vpp
HVout9
HVout8
HVout 7
HVout6
HVout5
HVoul4
HVoul3
HVout2
HVout 1
Data In
GND
Phase Shift
Clock
Clear

Package Outlines

40

25

top view

lop view

80-pin Gullwing Package

48-pin DIP

11-139

a"-11 §upertex inc.

HV6810

Preliminary

10-Channel Serial-Input
Latched Display Driver
Ordering Information
Device

Package Options
18·Pln Plastic
20·PinSmall
Outline Package

HV681 0

HV6810P

HV6810WG

Features

General Description

D High output voltage 80V

The HV681 0 is a monolithic integrated circuit designed to drive a
dot matrix or segmented vacuum fluorescent display (VFD).
These devices feature a serial data output to cascade additional
devices for large display arrays.

D High speed SMHz @ SVDO

D Low power IBB $ 0.1 mA (All high)

A 1O-bit data word is serially loaded into the shift register on the
positive-going transitions of the clock. Parallel data is transferred
to the output buffers through a 1O-bit D-type latch while the latch
enable input is high and is latched when the latch enable is low.
When the blanking input is high, all outputs are low.

D Active pull down 2.SmA min
D Output source current 60mA
D Each device drives 10 lines
D High-speed serially-shifted data input

Outputs are structures formed by double-diffused MOS (DMOS)
transistors with output voltage ratings of 80 volts and 60 milliamperes source-current Capability. All inputs are compatible with
CMOS levels.

D SV CMOS-compatible inputs
D Latches on all driver outputs
D Pin-compatible improved replacement for UCNS81 OA
and TL4810A, TL4810B

The HV681 0 is characterized for operation from O°C to 70°C.

Absolute Maximum Ratings 1
Logic supply voltage, VDC2

7.SV

Driver supply voltage, VBB
Output voltage

90V

Input voltage

90V
-0.3V to VCD + 0.3V

Continuous total power dissipation
at 2SoC free-air temperature 3
P-Package

87SmW

Notes: 1. Over operating free-air temperature.
2. All voltages are referenced to V55'
3. For operation above 25Q C free-air temperature the derating factor is
7.0mWI"C.

11-140

HV6810

Electrical Characteristics
DC Characteristics (Voo
Symbol

VOH

= 5V ±10%, V BB = 60V, vss = 0, unless otherwise noted)

Parameter

High-level output voltage

a outputs

Min

Typ

57.5

58

V

IOH = 25mA

4

4.5

V

VDD = 4.5V, IOH = -100~
IOH = 1mA, Blanking input at VDD

Serial output
Val

Low-level output voltage

a outputs

0.15

1

Serial output

0.05

0.1

a output current (pull-down current)

IOl

Low-level

IOIOFF)

Off-state output current

Max

2.5

3.7
-1

Units

Conditions

V
V

VDD = 4.5V, IOl = 100llA
TA = Max

rnA
-15

Va = 0, Blanking input

IlA

TA=Max atV DD
IH

High-level input current

IDD

Supply current from VDD (standby)
Supply current from VBB

IBB

1

IlA

VI = VDD

10

50

IlA

All inputs at OV, one

10

50

IlA

All inputs at OV, all outputs low

0.5

0.1
0.1

IlA
rnA

All outputs low, all

0.05

a output high

a outputs open
a outputs open

All outputs high, all

AC Characteristics (Timing requirements over recommended operating conditions)
Symbol

Parameter

Min

Typ

Max

Units

tWICKH)

Pulse duration, clock high

100

nS

tWllEH)

Pulse duration, latch enable high

100

nS

tsulD )

Setup time, data before clock

50

nS

t HID )

Setup time, data after clock

50

nS

tCKH.lEH
t •

Delay time, clock to latch enable high

50

pd

Propagation delay time, latch enable to output

·Switching characteristics. VBB

Conditions

ns
0.3

IlS

=60V, TA =25°C.

Recommended Operating Conditions
Symbol

(Note 1)
Min

Parameter

Nom

Max

Units

VDD

Supply voltage

4.5

5.5

V

Vee

Supply voltage

20

80

V

Vss
VIH
Vil

Supply voltage

IOH

Continuous high-level output current

TA

Operating free-air temperature

0

High-level input voltage (for VDD = 5V)
Low-level input voltage

11-141

V
5.3

V

-0.3

-0.8

V

0

-25

rnA

70

°C

3.5

0

•

HV681 0

Input and Output Equivalent Circuits
Input Equivalent Circuit
Voo

Input

Output Equivalent Circuit
----------1~,..--,-_O Vaa

D----"--f"---------1r-

D---,...-v\."v-""""""f--+

Output

Vss D--......----1r----------'---

Vss

Switching Waveforms
I

~--------------------- V 1H

Clock

Clock
Input

I

Pulse

V1L.

: _ t CKH-LEH - - ' ; _ 1 - - t w(LEH)
tsu(D)

:•

• :

I

\/\/\/'\U

~

Valid

Data 1 \ A A l ' \ 5 0 %

",,r---.\ -50% -- -- - - ~::

Latch _ _ _ _ _ _ _
50,;.'1<_,

t h(D)

I

50%7\AI\A

V 1H

Enable

:-- t pd'-'

V

Output _ _ _ _ _ _ _ _ _ _9_0....
%~

I

1L

Output Switching Times

Input Timing

Timing Diagram
Clock

Data In

SR Contents

Irrelevant

Valid

Invaild

Valid

n

Latch
Enable _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'

' -_ _ _ _ _ _ _ __

Latch
y _St_or_e_d_Da_t_a_ _ _ _...L_ _ _N_e_w_D_a_ta_V_a_ild_ _ _ __
Contents _ _ _ _ _P_r_ev_io_u_SI_

Blanking

Q Outputs

Vaild

--------------~--~---

11-142

HV681 0

Functional Block Diagram
Logic Diagram (positive logic)
Blanking
Latch
Enable
Shift

Register

Latches

Data Input
Clock

Function Table
Serial
Data
Input
H

L

X

Clock
Input

Shift Register Contents
11

S
S
L

12 13

••• I N_1

IN

H

R1 R2 ••• R N_2

R N_1

L

R1 R2 ••• R N.2

R N_1

R1 R2 R3 ••. R N_1

RN

X X X ... X

X

P 1 P2 P3

•..

PN-1 PN

Serial
Data
Output
R N. 1
R N. 1

Latch Contents

Strobe
Input
11

12 13

••• I N_1

IN

11

12 13

••• I N_1

IN

RN

X

L

R1 R2 R3 ••. R N. 1

PN

H

P 1 P2 P3

•••

L = Low logic level

= High logic level

X = Irrelevant
P = Present state
R = Previous state

11-143

RN

PN-1 P N

X X X ... X
H

Output Contents

Blanking
Input

X

PN-1 P N

L

P 1 P2 P3

H

L L L ... L

••.

L

HV681 0

Pin Configurations
18-Pin DIP
Pin Function

Pin

Function

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18

03
02
01
Blanking
Data in

08
07
06
Clock
Vss
Voo
LE (strobe)
05
04

Vee
Serial data out
010
09

20-PlnSOW
Pin Function

Pin

Function

1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20

03
02
01
Blanking
Data in

08
07
06
Clock
Vss
N/C
Voo
LE (strobe)
05
04

Package Outlines

top view

top view

18-pin DIP

SOW 20

11-144

Vee
Serial data out
N/C
010
09

Alphanumeric Index and Ordering Information
Company Profile
Application Notes
Static Handling Procedures and Quality Assurance
Process Flow
DMOS Product Family
N- and p. Channel low Threshold MOSFETs
DMOS Discretes N-Channel
DMOS Discretes P-Channel

...;
-':~
• •'l:'

....iii

..
.--..
,.
•..
~
-..
I

DMOS Arrays and Special Functions
HVCMOS High Voltage ICs
CMOS Consumer/Industrial Products
lead Bend Options and Surface Mount Packages
Package Outlines

!

Representatives/Distributors

4

DC-7

"--" §upertex inc.
Programmable Data Coder
Ordering Information
Device

28·Pin Plastic
DIP

28·Pin Plastic
Quad J Lead

28·Pin 50
Gullwing

Die

DC-7P

DC-7PJ

DC-7WG

DC-7X

DC-7

Features

General Description

D

8 Data Bits (Byte Wide Data)

D

7 Address Bits (128 Addresses)

The DC-7 is a single monolithic chip using metal gate CMOS
technology for low cost, low power, high yield and high reliability.
This dual purpose circuit is capable of working either as an encoder or decoder on its own transmission in applications where
exclusive recognition of address codes is required in addition to
transmission or reception of 8 Data Bits. It will decode 1 of 128
address codes. In the transmit mode this circuit is capable of
generating the possible codes by connecting the Address and
Data Inputs to Voo or GND for a "1" or a "0". In the receive mode
this circuit is capable of decoding the transmitted signals and simultaneously making cqmparisons to the local address code for
identification.

D

Manchester Phase Encoding

D

TransmitterlReceiver in one circuit

D

Schmitt Trigger Input for excellent noise rejection

D

Built-in Oscillator using non-critical RC Components

D

Zener Diode to regulate the power supply

D

Low Power, High Noise Immunity CMOS technology

D

Ability to Decode Original Signals

D

Automatic Preamble Generation

Absolute Maximum Ratings
Supply Voltage with respect to Vss

Applications
D

Multi-port Computer 1/0

D

Smoke & Fire Alarm Control Systems

D

Pocket Pagers

D

Digital Locks

D

Theft Alarm Systems

D

Security Systems

D

Digital Paging Systems

D

Special Identification Code Systems

D

Remote Sensor Data Acquisition Systems

D

Single Channel Digital Transmission of Information

6.4V

Operating Temperature
Storage Temperature
Zener Current
NOTE:

12-1

100mA

All inputs except 01 centain protection circuitry to prevent damage due to
static charges. Care should be exercised to prevent application of voltages
outside of the specification range. The 01 has a special Input protection clr·
cuit and special care should be taken with this Input.

Electrical

DC Characteristics
Symbol

DC-7

Characteri~tics
(Voo =5,O.± 5%; GRD = OV; TA = 25°C)

Parameter

. Min

.

Max

Unit

Voo + 0,3
0,3

V
V

"0" INPUT

0,1

2.0

I1A

VIN = 5.0V for pins TIR, SOl

6.0

20.0

I1A
V

VIN = 5.0V for pins RS, AO - A6, DO - 07
Voo = 4.75V, ILOAO = -10011A

V

Voo = 4.75V,I LOAO = 1001lA

Typ
(Note 1)

Conditions

VIH
VIL

Input High Voltage

Voo - 0,3

Input tow Voltage

-0,3

ILKC
ILC

Input Leakage Current
Input Load Current

2.0

VOH

Output High Voltage

Voo - 0.3

VOL

Output Low Voltage

IOH

Output High Current (Sourcing)

-1.0

-1.5

rnA

IOL
Vz

Output Low Current (Sinking)

1.0

3.0

rnA

Zener Voltage

5.5

6.4

7.0

V

Iz = 101lA

6.0

6.7

7.5

V

Iz = lOrnA (Note 2)

0.3

"1" INPUT

VOH = Voo -1:0V
VOL = 1.0V

CIN

Input Capacitance

10

pF

(Note 2)

CONT

Output Capacitance

10

pF

(Note 2)

'00

Drain Current

10

IlA

(Note 2)

Voo = 5.0V, all inputs = GRD
all outputs floating

Note 1:
Note 2:

Typical values are those values measured in a production sample at Vee = 5.0V.
This parameter is periodcally sampled and is not 100% tested.

AC Characteristics (Voo = 5.0 ± 5%; TA = 25°C)
Symbol
fc

Parameter
Clock Frequency

Min

Typ
(Note 1)

Max
25

0

Unit
kHz

Conditions
R = 150k, C = 100pF;
Clock Period (tc) = 1lie

tsOi

Start Pulse Width

tO~~

000 Delay from SOl

toc
tWORO

Data Clock Pulse Width

RR

Receiver Oscillator
Resistor Tolerance
from Transmitter
Oscillator Resistor

CR

Receiver Oscillator
Capacitor Tolerance
from Transmitter
Oscillator Capacitor

Full Cycle Word Length

ns

500
5
5tc
130tc
t10

t10

I1s
sec
sec

%

%

Note 1: Typical values are those values measured on a production sample at Vee = S.OV.

12-2

DC-7

Pin Definition
Label

Pin Name

GND

Ground

Supply Potential negative side.

Function

01

Oscillator
Input

This input is to drive the oscillator and is the tie point of the timing resistor (RT), and the timing
capacitor (C T). It also is connected through a diode to an open drain P-channel device that turns
on to V00 when the oscillator is being reset. This input can exceed the power supplies and does
during normal oscillator operation.

OR

Oscillator

Provides phase feedback to the RC timing circuit through the connected timing resistor. Note:
This Resistor pin is driven high during oscillator reset.

OC

Oscillator
Capacitor

Capacitor connection of RC timing circuit provides phased feedback from the oscillator. This pin
is driven low during oscillator reset.

RS

Reset

This input pin may be used to override the data transmission cycle or inhibiting a SOl input. It
clears the DIDO to a low state and resets the internal oscillator and data comparison circuits. This
pin may be left open (No Connection) when not used, or driven as an input, or an external
capacitor (1 OOpF) to V00 may be added for power-up reset. The Reset function is activated when
this input is connected to V00'

SIDI

Start/Data
Input

Start/Data input is a dual function pin. It is used to start the oscillator which enables the
transmission of the encoded word in the transmit mode. And, in the receive mode, this input
receives the serial coded information for processing and comparison.

DIDO

Data/Decode
Output

Another dual purpose pin, this pin is the encoded sequence data output in the transmit mode and
becomes the decode true output in the receive mode. It indicates that the incoming code has
matched the local bit data input address.

AO-AS

Address Inputs

These Inputs provide the parallel Address to be sequentially transmitted. In the receive mode,
these inputs become the'parallellocal Address code for comparison with the incoming data.

00-07

Data Bit Inputs

These Inputs provide parallel data to be sequentially transmitted. In the receive mode, these
Inputs are not used.

SDO

Serial Data
Output

This output signal is a buffered SIDI signal after going through the input Schmitt Trigger - a delay
circuit, and is the same polarity as the input and can be used to chain a number of receivers
together. This output can be connected to the input of a B-bit shift register (clocked by the DC pin)
in a receiver system where data is to be recovered. This output can be connected to the input
of a 1S-bit shift register (clocked by the DC pin) in a receiver system where Address and data are
to be recovered.

DRS

Data Reset
Output

Data Reset can be used in the receive mode to reset an external data shift register since this
signal pulse indicates that a new word has just begun processing.

DC

Data Clock
Outputs

The Data Clock output may be used in a receive system since it is the recovered data sync pulses.
Also, this output can be used to clock an external shift register where data is to be recovered.

DV

Data Valid
Output

This output is triggered low at the start of any input and will remain low until a complete word has
been processed. Note that this output simply signals that a valid word has been received and not
that the code received has matched the local address code.

TIR

Transmit!
Receive

This is a control input to determine the operating mode. A logic high applied to this input puts it
in the transmit mode, a logic low puts it in the receive mode.

Voo

Voo

Positive Supply Potential- This circuit contains an on-chip zener of approximately S.7 volts
across the supply terminals.

12-3

DC-?

Block Diagrams
RECEIVER

TRANSMITTER

O$CINPUT

OIeFl£s

0""'"
DATA/DECODE

OUTPUT

STAAT/DATA

STAAT/DATA
INPUT

DATA/DECODE
OUTPUT

INPUT

AO
All 00
ADDRESS arTS

Operation
General

encoder will transmit the serial data each time the StarVData input
is activated.

The DC-? mode of operation is controlled by the TransmiVReceive
control input (T/R). When switched for Voo to GND, the circuit will
automatically change the oscillator, StarVData Input, and Data
Decoder Output from Transmit to Receive mode.

This encoded Data word is transmitted in 2 parts. The first part is the
preamble information which is a series of 12"1 "s and then a space
indicating that the encoded Data is to follow. This preamble
information is intended to be used to synchronize a phase locked
loop at the receiver or used as a setting time for receivers that have
automatic gain control. The second part contains the ? bits of
address and 8 bits of data.

The DC-? contains an on-chip zener diode to clamp the power
supply to around 6.? volts. The circuit will operate from 4.0 volts to
the zener voltage, but operation is recommended at 5 volts ± 5%,
or a regulated power supply in order to stabilize the time constants
of the oscillator circuit. In order to use the on-chip zener diode, a
current limiting resistor of 1K ohm or greater is required. If pull up
resistors are used for the 0 1 - D15 drivers, the resistors should be
tied to a voltage no higher than that on Pin 28 or 6 volts, whichever
is lower.

Receive Function
The receive mode is selected by connecting the TransmiVReceive
control input to ground. In this mode the circuit will work as a
decoder receiving the serial data in Manchester Coded format and
recovering the clock. The incoming data is converted to a 15-bit
serial word. It is compared with the local address word by sampling
the Address Inputs (?-bits). These bits are usually programmed to
the expected Address that will be decoded. If the two Address
words match, the decoded output will become logic "1" state, but if
the two do not match the decoded output will stay low. Also, if the
words do not match but the bit stream was valid (i.e., 15-bits of
proper timing) then only the output valid signal will go high. If at any
time the bit sequence has the wrong timing, the local oscillator and
internal comparison circuits will be reset and any new input pulses
will be recognized as a new bit stream. Therefore, as with the
receiver processing of the preamble information, the 12-bits will be
recognized. But, during the 13th interval where no bit transition
occurs, the circuit times-out and awaits the start bit of the address
and data sequence.

Output drivers are capable of sinking or sourcing 1.0mA minimum
at 1.0 volts Vos' All inputs are gate protected to both power supplies
by internal diodes. The Address Data inputs oUhe DC-? each have
pull down resistors to ground so that only a "1" will have to be programmed. This allows the inputs to be programmed by using SPST
switches or jumpers to VDO only. The TransmiVReceive input does
not have a pull up or pull down resistor. The StarVData Input also
does not have a pull up or pull down resistor, but is applied to a
Schmitt Trigger Input circuit to improve noise rejection.

Transmit Function
This function is selected by connecting the TransmiVReceive
control input to VDO. This enables the Transmit mode and the circuit
to function as an encoder - sampling the? Address and 8 Data
Input pins digital information and encoding this parallel data in NRZ
format, combining it with the clock in Manchester Code (Phase
Encoded) and presenting it to the DIDO pin for transmission.
(Usually to another DC device used as the decoder circuit). The

The DC-? will only compare the first? bits and ignore the state of
the last 8 bits - that is, 128 distinct address codes with 8 bits that
may be used for data transmission.

12-4

DC-7

Transmit and Receive Address and Data Patterns
VDD

VDD

28

28
GND

":'

3

CT

Co)

7

DIDD

SDI

2

22
DATA

6
8

SDI

15

~

TIR
GND
DV

4

25

DC

6

7

0

DIDO

14

ADDRESS

ADDRESS

Transmitted Bit Sequence

Received Addre•• Code

111xlxlxlxlxlxlxlxlxlxlxlxlxlxlxl
AO

27
26

3

CT

0
4

START SIGNAL

GND

27

2

111xlxlxlxlxlxlxlolololololololol

D7

A6 DO

NOTE:

AO

A6 DO

D7

Bit Sequence Code Format.
X = Programmable

o = Hardwired I nternally Zero
1 = Hardwired I nternally One
D = Don't Care in Receive Mode (Data)

Note: When unused. the DV. DC, DRS and SDO pins should be left floating and must not be tied to either a power supply or to ground.

".L'

12-5

Typical Application

VOO

VOD
28
GND'

CT :;::

01

12

'-------"4

01

27
0

3

o

()

.:..,

7

GNO

-I

4
START SIGNAL

SDI16
8

ADDRESS

OR
CT
OC
SOl

()

2

.:..,

27

3

70r 26

4

25

6

VOO

23

4

07

5

06

6

05

14

03
02

16

28
GND

DIDO or DV
DC
SOO

"'"

STROBE
CLOCK
DATA

04

(:)
<.C

"'"

3

13

2

12

01

11

DO

j:m"~"'

Enable
or VOD

GNO

J\)

m

VOD

DATA

16
2

4

A6

5

A5

STROBE

The circuit shown above demonstrates the use of the DC-7
where both the Data and Address bits can be transm itted from
one location to another and both the Data and Address bits of
the transmitter recovered. In an application where only the
Data is to be recovered and a special address assigned to the
receiver. the 0/00 signal should be connected to the 4094 and
only the top 4094 used. In a system where all incoming Data
and Addresses are to be decoded, the DV signal would be
connected to both 4094's as shown.

CLOC

3

"'"
~

6

A4

7

A3

14

A2

0

8

13

A1

12

AO

15

IT""
GND

Output
Enable
or VDD

o

()

.:..,

Timing Diagram - Transmit Mode
so.

r- TMIN- 500ns

-j

TfUOGER IN r-Th"T--"

....... _.L_ '

-

... ---I-l-_-:l~~.1~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

t--~ 4T" ~

DATAOUT

4TC

PREAMBLE 81JRST

,·''j''l-rirr;r-:-..'''!-;5'r-:&r-rj1-r.-:- r g!-i 1o"!" -~1\:--:;2~-1'j!-~1.-r '!i5o~~_ _ _ __

I

~- ;-;~D'R~~SCS;;:,s·=-:I~~·8D;TA BITS'~

Total Time Required for Transmission of One Sequence = (DRS - 4Tc) = 130Tc
Tc=-~~~~~~

CLOCK FREQUENCY

~

Timing Diagram - Receive Mode
DATA VALID

Dv----"(
..,.

D01,"

~
10"'"

~

,~

~

--r-'
'j

~

1/

ImA

I

I-""'"

~ 2.0
1.0

-

lOmA

~

4.0

=
~

100 vsVoo

I,
100 TRANSMIT

lOOuA

.B

'00 RECEIVE
I

'OuA

I

--

'STaY TRANSMIT

~

~ r~·

o

luA
3.5

I

4.0

4.5

5.0

5.5

6.0

6.5

#

1.0"

o

3

'STIY RECEIVE

•

VOO(VOLTS)

VOO (VOLTS)

12-8

9

DC-7

Pin Configuration
GNO

DC DRS SOO

01
OR
OC
RS
SOl

A.
A5
A6
-'------~-

RS
top view

28-pin DIP

DIDO Ao
A1
top view

A2

28-pin J-Iead Package

12-9

A3

ED-5
ED 9
ED:11
ED-15

a.::=
'f1I
:::JJupertex ,nc.
Progammable Encoder/Decoder
Ordering Information
Device

Order No.

Package

ED-15

28-Pin Plastic DIP
28-Pin Plastic Chip Carrier
28-Pin SOW Package

ED-15P
ED-15J
ED-15WG

ED-11

28-Pin Plastic DIP
28-Pin SOW Package

ED-11P
ED-11-WG

ED-9

18-Pin Plastic DIP
20-Pin SOW Package

ED-9P
ED-9WG

ED-5

18-Pin Plastic DIP

ED-5P

Features

General Description

o
o
o
o
o
o
o
o

The ED series is a single monolithic chip using metal-gate CMOS
technology for low cost, low power, high yield and high reliability.
It is a dual purpose circuit, capable of working either as an encoder
or as decoder on its own transmissions in applications where
exclusive recognition of a special code is required. It will decode
1 of 32,768 codes. In the transmit mode each circuit is capable of
generating the possible codes by connecting the Data Inputs to
VDO or GRD for a "1" or a "0". In the receive mode each circuit is
capable of decoding the transmitted Signal and simultaneously
making a comparison to the local ~ddress code for identification.

Manchester Phase Encoding
Encoder/Decoder in one circuit
Schmitt Trigger Input for excellent noise rejection
Built-in Oscillator using non-critical RC Components
Zener Diode to regulate the power supply
Low Power. High Noise Immunity CMOS technology
Ability to Decode Original Signals

Absolute Maximum Ratings

Automatic Preamble Generation

Supply Voltage with respect to VS8

Applications
o
o
o
o
o
o
o
o
o

6.4V

Operating Temperature

Smoke & Fire Alarm Control Systems

Storage Temperature

Security Systems

Zener Current

Theft Alarm Systems

Note: All inputs except 01 contain protection Circuitry to prevent damage due to
static charges. Care should be exercised to prevent application of voltages
outside of the specWication range. The 01 has a special input protection
circuit and special care should be taken with this input.

Digital Locks
Digital Paging Systems
Garage Door Openers
Systems that require a Special Identification Code
Pocket Pagers
Recognition or Transmission

12-10

100mA

EO-5,9,ll,15

Electrical Characteristics
DC Characteristics (VDD
Symbol

= 5.0

± 5%;

Parameter

GRD = OV; TA = 25°C)
Min

Typ
Note 1

Max

Unit

VDD + 0.3
0.3

V

"1" INPUT

V

"O"INPUT

0.1

2.0

I1A

VIN = 5.0V for pins TIR, SOl

6.0

20.0

ItA

VIN = 5.0V for pins RS, 01-015

VIH
VIL

Input High Voltage

VDD - 0.3
-0.3

ILKC
ILC

Input Leakage Current
Input Load Current

2.0

VOH

Output High Voltage

VDD - 0.3

VOL

Output Low Voltage

10H

Output High Current (Sourcing)

-1.0

-1.5

10L
Vz

Output Low Current (Sinking)

1.0

3.0

Zener Voltage

5.5

6.4

7.0

6.0

6.7

Input Low Voltage

V

Conditions

mA

VDD = 4.75V, ILOAD = -1001tA
VDD = 4. 75V, ILOAD = 1001tA
VoH =VDD -l.0V

mA

VOL = 1.0V

V

Iz = lOI1A

7.5

V

Iz = 10mA (Note 2)
(Note 2)

0.3

V

(Note 2)

CIN
CONT

Input Capacitance

10

pF

Output Capacitance

10

pF

(Note 2)

IDD

Drain Current

10

I1A

VDD = 5.0V, all inputs = GRO
all outputs floating

Max

Unit

Note 1: Typical values are those values measured in a production sample at Vcc
Note 2: This parameter is periodcally sampled and is not 100% tested.

=S.OV.

AC Characteristics (V DD = 5.0 ± 5%; T A= 25°C)
Symbol

Parameter

Min

Clock Frequency

fc

Typ
Notel

0

25

kHz

Conditions
R= 150k, C= 100pF;
Clock Period (tc)= 11fc

tSDI
t DDO
tDC

Start Pulse Width

IwORD
RR

Full Cycle Word Length

CR

500

000 Delay from SOl
Data Clock Pulse Width
Receiver Oscillator
Resistor Tolerance
from Transmitter
Oscillator Resistor
Receiver Oscillator
Capacitor Tolerance
from Transmitter
Oscillator CapaCitor

ns
5
5tc
1301c
±10

±10

I1s
sec
sec
%

%

Note 1: Typical values are those values measured on a production sample at VCC = S.OV.

Pin Definition
Label

Pin Name

Function

GNO

Ground

Supply Potential negative side.

01

Oscillator
Input

This input is to drive the oscillator and is the tie point of the timing resistor (RT), and the timing capacitor (CT). It also is connected through a diode to an open drain P-channel device that turns on
to VDD when the oscillator is being reset. This input can exceed the power supplies and does during normal oscillator operation.

OR

Oscillator
Resistor

Provides phase feedback to the RC timing circuit through the connected timing resistor.
Note: This pin is driven high during oscillator reset.

OC

Oscillator
Capacitor

Capacitor connection of RC timing circuit provides phased feedback from the oscillator. This pin
is driven low during oscillator reset.
12-11

~I

ED-5,9,11,15
RS

Reset Input

This input pin may be used to override the data transmission cycle or inhibiting an SDI input. It
clears the DIDO to a low state and resets the internal oscillator and data comparison circuits. This
pin may be left open (No Connection) when not used, or driven as an input, or an external
capacitor (1 OOpf) to VDO may be added for power-up reset. The Reset function is activated when
this input is connected to V~o'

SIDI

Start/Data
Input

Start/Data input is a dual function pin. It is used to start the oscillator which enables the transmission of the encoded word in the transmit mode. And in the receive mode, this input receives
the serial coded information for processing and comparison.

DIDO

Data/Decode
Output

Another dual purpose pin, this pin is the encoded sequence data output in the transmit mode and
becomes the decode true output in the receive mode. It indicates that the incoming code has
matched the local bit data input address.

D1-D15

Data Bit Inputs

These Inputs provide parallel input data to be sequentially transmitted. The 18-pin package
options have some pins omitted and hence these data positions will have logical zeros
transmitted. In the receive mode, these imputs become the parallel local addres code for
comparison with the incoming data. Note that with the ED-11 and ED-5 options, the data bits 1115 are not used in the comparison when in the receive mode.

SDO

Serial Data
Output

This output signal is a buffered SIDI signal after going through the input Schmitt Trigger - a delay
circuit, and is the same polarity as the input and can be used to chain a number of receivers
together. This output can be connected to the input of a 16-bit shift register (clocked by the DC
pin) in a receiver system where data is to be recovered regardless of its comparison to a preset
address word.

DRS

Data Reset
Output

Data Reset can be used in the receive mode to reset an external data shift register since this
Output signal pulse indicates that a new word has just begun processing.

DC

Data Clock
Output

The Data Clock output may be used in a receive system since it is the recovered data sync pulses.
Also, this output can be used to clock an external shift register where data is to be recovered.

DV

Data Valid
Output

This output is triggered low at the start of any input and will remain low until a complete word has
been processed. Note thatthis output simply signals that a valid word has been received and not
that the code received has matched the local address code.

TIR

Transmit!
Receive

This is a control input to determine the operating mode. A logic high applied to this input puts it
in the transmit mode; a logic low puts it in the receive mode.

Voo

Voo

Positive Supply Potential- This circuit contains an on-chip zener of approximately 6.7 volts
across the supply terminals.

Block Diagrams
TRANSMITTER

RECEIVER

12-12

ED-5,9,11,15

Operation
ED-15 General Description

Decoder Function

The ED-15 series mode of operation is controlled by the Transmit!
Receive control input (T/R). When switched for Voo to GND, the
circuit will automatically change the oscillator, StarVData input,
and Data/Decoder Output from Transmit to Receive mode.

The receive mode is selected by connecting the Transmit/Receive control input to ground. In this mode the circuit will work as
a decoder, receiving the serial data in Manchester Coded format
and recover the clock. The incoming data is converted to a 15-bit
serial word. Compare it with the local data word by sampling the
Data Inputs (15-bits). These bits are usually programmed to the
expected Data that will be decoded. If the two data words match,
the decoded output will become logic "1 "state, but ilthe two words
do not match the decoded output will stay low. Also, if the words
do not match but the bit stream was valid (i.e., 15-bits of proper
timing) then only the output valid signal will go high. If at any time
the bit sequence has the wrong timing, the local oscillator and
internal comparison circuits will be reset and any new input pulses
will be recognized as a new bit stream. Therefore, as with the
receiver processing of the preamble information, the 12 bits will be
recognized. But during the 13th interval where no bit transition
occurs, the circuit times-out and awaits the start bit of the data
sequence.

The circuit contains an on-chip zener diode to clamp the power
supply to around 6.7 volts. The circuit will operate from 4.0 volts
to the zener voltage, but operation is recommended at 5 volts ±
5% in order to stabilize the time constants of the oscillator circuit.
In order to use the on-chip zener diode, a current limiting resistor
of 1K ohm or greater is required. If pull up resistors are used for
the D1 - D15 drives, the resistors should be tied to voltage no higher
than that on Pin 28 or 6 volts, whichever is lower.
Output drivers are capable of sinking or sourcing 1.0 mA minimum
at 1.0 volts Vos' All inputs are gate protected to both power
supplies by internal diodes. The Data Inputs each have pull down
resistors to ground so that only a "1" will have to be programmed.
This allows the inputs to be programmed by using SPST switches
or jumpers to V00 only. The Transmit/Receive input does not have
a pull up or pull down resistor. The StarVData Input also does not
have a pull up or pull down resistor, but is applied to a Schmitt
Trigger Input circuit to improve noise rejection.

ED-9 Option
The ED-9 is an 18-pin packaging of the ED-15 die. The operation
and function of this circuit is the same as the ED-15; the only
difference being the available pins. In the transmit mode the circuit
is only capable of encoding 9 bits of data, the other 6 bits are not
programmable and remain zeros. The pin configuration also
drops DV, DC, DRS, and SDO such that the circuit can now only
respond to a data match condition on the only output DIDO. In the
receive mode the circuit can decode the same 9 bits of data,
enabling up to 512 possible addresses.

Encoder Function
This function is selected by connecting the Transmit/Receive
control input to Voo' This enables the Transmit mode and the
circuit to function as an encoder - sampling the 15 Data Input
pins digital information and encoding this parallel data in NRZ
format, combining it with the clock in Manchester Code (Phase
Encoded), and presenting it to the DIDO pin for transmission
(usually to another ED devise used as the decoder circuit). The
encoder will transmit the serial data each time the StarVData input
is activated.

ED-11 Option
The ED-11 differs from the ED-15 in that in the receive mode the
ED-11 will only compare the first 11 bits and ignore the state olthe
last 4 bits - that is 2048 distinct address codes with 4 bits may
be used for control data transmission.

This encoded Data word is transmitted in 2 parts. The first part is
the preamble information which is a series of 12 "1 "'s, then a
space indicating that the encoded Data is to follow. This preamble
information is intended to be used to synchronize a phase locked
loop at the receiver or used as a settling time for receivers that
have automatic gain control. The second part contains the 15 bits
of addresses andlor controls.

ED-5 Option
The 18-pin packaging option olthe ED-11 die is called ED-5.ln the
transmit mode it is only capable of 5 bits of programmable code.
All the other bits are held at zero. But in the receive mode, the
circuit has the five (32) unlock code bits piUS the last four
transparent bits of the ED-11. The ED-5 also supplies the necessary output signals to process the 4 bits of control data.

12-13

ED-5, 9, l'

Transmit and Receive Data Patterns of ED-Series Devices

NOTE:

Bit Sequence Code Format
X = Programmable

0= Hardwired Internally Zero

1 = Hardwired Internally One
D = Don't Care in Receive Mode

ED-15 to ED-15

VDD

2B.----i
GND

,--,..-""-! 2

It)
po

271--'"'''''----'

3 Q
' - - -.......-14 W

7~~~------------~~

- -......-16

Transmitted Bit Sequence

Received Address Code

111xlxlxlxlxlxlxlxlxlxlxlxlxlxlxl
D1

ED-11

D15

to ED-11
VDD

VDD
2B
GND

2

3

START SIGNAL

po

6
w

GND

27

2

po
po

3

Q

4
7

DIDO

6

2

W
7

D/DO

Received Address Code

Transmitted Bit SeQuence

111xlxlxlxlxlxlxlxlxlxlxlolololol
D1

D1

D15

D15

Note: When unused, the DV, DC, DRS and SDO pins should be left floating and must not be tied to either a power supply or to ground.

12-14

ED-5, 9, 11, 15
ED-9to ED-9
VDD

r------117

16

17

.---:r-"~ 18 en 15 TIR

GND

16
W

C

1

C

'-----="'--i 2
SDI

START SIGNAL

16

18 en 15

GND

TIR

6W

GND

2
5

4

SDI

DIDO

Transmitted Bit Sequence

DIDO

4

Received Address Code

11101010lxl xl xl xlolxlolol xl xl xl xI
D1

D15

ED-9to ED-5
VDD

16 t----1

r------117

CT

1

~--"""-i2
START SIGNAL

SOl

17

18

~~~18en 15~~~

GND

GND

It)

6

2

w

3

6W

16
GND

14
6

4

Transmitted Bit Sequence

DC

DIDO

Received Address Code

11"1010 lolxl xl xl xlo Ixlo lolxlxlxlxl
D1

VDD

D15

11101010lxl xlxl xlolxlo 10101010101
D1

D15

~

I

12-15

Timing Diagram - Transmit Mode

r- TMIN- 500ns

-j

so,

TR'OO"'.

r- T -- i --'
~- • . I - - •

_~-l~l~~'

-

______________________

... ~ r
~

000

OATAOUT

aTe

~

4OT,

-,-

~

1IT,

_________________________________

-,..

PREAMBLE BURST

117T,

-11r----f-4T

'

DATA

~-.1~}:!!I~r~rJ!]=I~_"I'I_-r!1~r~r!rl~o::~~~=!1~:~1~!=1!·I=~-S.f-~______

I

I·

INPUT BITS 0, - 0 ' 5 - - -

---I

Total Time Required for Transmission of One Sequence = (DRS - 4Tcl = 130Tc

TC= ______l~_____
CLOCK FREQUENCY

~

Ol

Timing Diagram - Receive Mode
Goes hi if received

DATA VAllO

r Address compares

ov ----"l
. .CODE

I-

44T,

DlOO~
,
SOl

I

-,-

I
'Y"""_'Z'TlO,,"UOST

1IT,

-I-

.....- _ _ _-.1_1\ t-- 7-

I

' I

to local data pattern

CT,

'
DATA

-r;1-T21--rl"rl-.1-T5i-"1-.ii-7~-TiTi-,~-Ti01-il1-:;lirl1ii1,,,'-lftl

___ ,-_
Stays low if Address

does not compare

I
"-"_J_J_J_j_~_J_""_~_.J_""_.J_..J_~.J_..J_""_""_""_""_..J_..J_..J_..J_..J_.J,_""_~-,-=:,_-,,=:..:c==

I-

INPUT BITS 0, - 0'5

.. I

oc -OA-T.,-.-"CL-,OC.,-,.:-!',,..--.,r-,...-,,..--,,-,,...-,,,'-',...-'r"-',...--------h,r l r I r I r l r l r l r l r l r l r l r l r l r l r l r l r
I
nI

_~

m
Tc =

1
CLOCK FREQUENCY

o

~
!"
~

'"

Typical Performance Curves

IOH

•
6

!

4

VS

~
~

-6.OV

..!-)>!

/

:::;

5.0V

....

~ 4

§

~ io""

A ~ i--"

.........

Voo'

6

:IE

V' I-"" "oo,.:!~
~~

.......

-6.0V

o.lQQ4<

~

4.5V

3

4.0V

2

3

4

5

6

7

8

9

VOH IVOLTSI

OPERATING FREQUENCY

vs
VOO
70

eoO

80

\\ I"-

\ ~"f'.

\

~''-~

.........'00-,;;;
--.

30

1\~~'"" -- ~

20

I'

20

§

,.

10
o

o'l«; ",

~

\. I"-

40

I~ V

~~

50

So""
......

J'..
", ..... ,<'sO""

~

10

20

30

40

50

80

r--: 'l'c
~..(

o

70

~

~'-

~

,~o

~'

~

., ~~«;

"., ,/ i

10

4.c-

'0

~i

~\

10

lK
800 In

100
80
80

~~

\.'\ I\. \

RESISTANCE
vs
OSCILLATOR FREQUENCY

200

I"'
~,

~

VOL IVOLTSI

400

."

,...... ,,\

r;i'
1

"'\

3.5

4.0

4.5

FREQUENCY IKHzl

5.0

5.5

6.0

6.5

Voo IVOLTS)

.'

SOl INPUT
VILIV IH vs VOO
5.0

~
....
3.0

l:

J....--'"
>!,,,

",..".
io"'"

,

~f

~ 2.0

~

lmA

-

f
~

..-

i

1.0

-

-~
'I)'"

V

II
100 TRANSMIT
l00uA

0

9

100 RECEIVE
I

10uA

I.A
4.0

4.5

5.0

5.5

6.0

6.5

I

-.

...

I

ISTHY TRANSMIT

io"'"
3.5

I

10mA

~

4.0

~

100 vs VOO

I
o

I

l"""" L

10-"

ISTBY RECEIVE

8
VooIVOlTSI

Voo IVOLTS)

12-23

11

a'f1I !iupertex inc.

MP690/692
MP691/693
Preliminary

Microprocessor Supervisory Circuits
Ordering Information
Device

Temperature Range

Package

MP690

O°Cto + 70°C
-40°C to + 85°C
-40°C to + 85°C
-55°C to + 125°C
-55°C to + 125°C

8 Lead Plastic Dip
8 Lead Plastic Dip
8 Lead CERDIP
8 Lead CERDIP
8 Lead CERDIP'HI-REL

Order No.
MP690P
MP690 MP
MP690MD
RCMP690D
RBMP690D

MP691

O°Cto + 70°C
O°C to + 70°C
O°C to + 70°C
-40°C to + 85°C
-40°C to + 85°C
-40°C to + 85°C
-55°C to + 125°C
-55°C to + 125°C

Dice
16 Lead Plastic DIP
16 Lead Small Outline
16 Lead Plastic DIP
16 Lead CERDIP
16 Lead Small Outline
16 Lead CERDIP
16 Lead CERDIP HI-REL

MP691X
MP691P
MP691WG
MP691MP
MP691MD
MP691MWG
RCMP6910
RBMP691D

MP692

O°C to
-40°C to
-40°C to
-55°C to
-55°C to

8 Lead Plastic DIP
8 Lead Plastic DIP
8 Lead CERDIP
8 Lead CERDIP
8 Lead CERDIP HI-REL

MP692P
MP692MP
MP692MD
RCMP692D
RBMP692D

MP693

O°C to + 70°C
O°C to + 70°C
O°C to + 70°C
-40°C to + 85°C
-40°C to + 85°C
-40°C to + 85°C
-55°C to + 125°C
-55°C to + 125°C

Dice
16 Lead Plastic DIP
16 Lead Small Outline
16 Lead Plastic DIP
16 Lead CERDIP
16 Lead Small Outline
16 Lead CERDIP
16 Lead CERDIP HI-REL

MP693X
MP693P
MP693WG
MP693MP
MP693MD
MP693MWG
RCMP693D
RBMP693D

+ 70°C
+ 85°C
+ 85°C
+ 125°C
+ 125°C

Features

General Description

o

Precision Voltage Monitor:
4.65V in MP690 and MP691
4.40V in MP692 and MP693

The MP690 Family of supervisory circuits reduces the complexity
and number of components required for power supply monitoring
and battery control functions in microprocessor systems.

Power OK/Reset Time Delay

The MP690 and MP692 are supplied in 8-pin packages and provide
four functions:
1) A Reset output during power-up, power down, and brownout
conditions.
2) Battery backup switching for CMOS RAM, CMOS microprocessor other low power logic.
3) A Reset pulse if the optional watchdog timer has not been
toggled within a specified time.
4) A 1.25V threshold detector for power fail warning, low battery
detection, or to monitor a power supply other than +5V.

o
o
o
o
o
o
o

Watchdog Timer -lOOms, 1,6 sec, or adjustable
Minimum Component Count
lIlA Standby Current
Battery Backup Power Switching
Onboard Gating of Chip Enable Signals
Voltage Monitor for Power Failor Low Battery Warning

The MP691 and MP693 are supplied in 16-pin packages and
perform all MP690/692 functions, plus:
1) Write protection of CMOS RAM or EEPROM.
2) Adjustable reset and watchdog timeout periods.
3) Separate outputs for indicating a watchdog timeout, battery
switchover, and low Vee'
12-24

MP690/692 MP691/693

Absolute Maximum Ratings
Terminal Voltage (with respect to GND)
Vee
VSATT
All other Inputs (Note 1)

Power Dissipation
S Pin Plastic DIP
(Derate 5mW/oC above +70°C)
SPin CERDIP
(Derate SmW/oC above +S5°C)
16 Pin Plastic DIP
(Derate 7mW/oC above +70°C)
16 Pin Small Outline
(Derate 7mW;oC above +70°C)
16 Pin CERDIP
(Derate 1OmW/oC above +S5°C)

-0.3V to 6.0V
-0.3V to 6.0V
-0.3V to (Vout +0.5V)

Input Current
Vee
VSATT
GND

200mA
50mA
20mA

Output Current
VOUT
All other Outputs

short circuit protected
20mA

500mW
600mW
600mW
600mW

Storage Temperature Range

100V/I1S

Rate-ol-Rise, VSATT' Vee

400mW

-65°C to +160°C

Lead Temperature (Soldering, 10 seconds)

300°C

Electrical Characteristics
(Notes 1 and 2)

(Vee = full operating range; V BATT = 2.BV; TA = 25°C, unless otherwise noted.)
Parameter

Min

Typ

Max

Unit

Conditions

BATTERY BACKUP SWITCHING
Operating Voltage Range
MP690, 691 Vee
MP690, 691 VSATT
MP692, 693 Vee
MP692, 693 VSATT
VOUT Output Voltage
VOUT in Battery Backup Mode
Supply Current (excludes lOUT)

4.75
2.0
4.5
2.0

VBATT - 0.1

5.5
4.25
5.5
4.0
Vee - 0.1

V

lOUT = 1mA

Vee - 0.25
VSATT - 0.02

V

lOUT = 50mA

V
mA

4
10

Supply Current in Battery Backup Mode

V

0.6

Battery Standby Charging Current

lOUT = 100IlA, Vee< VSATT - 0.2V
lOUT = 1mA

mA

lOUT = 100mA

1

IlA

1

IlA

Vee = OV, VSATT = 2.SV
5.5V> Vee> VBATT + 0.2V

5

IlA

5.5V> Vee> VSATT + 0.2V
lOUT = 100mA

lOUT = 1mA

Battery Switchover Threshold
Vee - VSATT

70

mV

Power Up

50

mA

Power Down

Battery Switch over Hysteresis

20

mV

BATT ON Output Voltage
BATTON Output Short
Circuit Current

0.4
7

V
mA

ISINK = 3.2mA
BATT ON = VOUT
BATTON=OV

0.5

1

25

IlA

4.5

4.65

4.75

V

MP690, 691

4.25

4.4

4.5

V

MP690, 691

RESET AND WATCHDOG TIMER
Reset Voltage Threshold
Reset Threshold Hysteresis

40

mV

Reset Timeout Delay

35

50

70

ms

Figure 6. OSC SEL High

Watchdog Timeout Period,
Internal Oscillator

1.0
70

1.6
100

2.25
140

sec
ms

Long Period
Short Period

Watchdog Timeout Period,
External Clock

4032
960

4097
1025

Clock
Cycles

Long Period
Short Period

Minimum WDllnput Pulse Width

ns

200

12-25

VIL = 0.4, VIH = 3.5V

MP690/692 MP691/693

Electrical Characteristics (continued)
(Vcc

= full operating range;

VBAn

= 2.SV; TA = 25°C, unless otherwise noted.)

Parameter

Typ

Min

Max

(Notes 1 and 2)

Unit

0.4
RESET and LOW LINE Output Voltage

0.4

RESET and WDO Output Voltage

3.5
1

Output Short Circuit Current

I
I

WDI Input Threshold

V

3.5

WDI Mid-Level Logic Voltage

25
0.8

3.0
1.3

WDI Input current

ISOURCE = 1l1A, Vcc = 5V
ISINK = 800llA
ISOURCE = lilA, Vcc = 5V

3

Logic Low
Logic High

V

Conditions
ISINK = 1.6mA

1.9

2.5

lIA

RESET, RESET, WDO, LOWLINE

V
V

Vcc = 5V (Note 2)
Vcc = 5V (Note 2)

20

lIA

WDI = VOUT

-15

IlA

WDI =OV

POWER FAIL DETECTOR
PFI Input Threshold

1.15

PFI Input Current

1.25

1.35

V

±0.01

±10

nA

PFO Output Voltage

PFO Short Circuit Source Current

1

3

0.4

V

3.5

V

ISOURCE = 11lA

IlA

PFI = OV, PFO = OV

V

VIL
VIH

25

ISINK = 3.2mA

CHIP ENABLE GATING
CE IN Thresholds

0.8
3.0

CE IN Pullup Current

lIA

3

CE OUT Output Voltage

0.4
Vcc -1.5

CE Propagation Delay

V

50

V

ISINK = 3.2mA

V

ISOURCE = 3.0mA

ns

OSCILLATOR
OSC IN Input Current

±2

OSC SEL Input Pullup Current
OSC IN Frequency Range
OSC IN Frequency with External Capacitor
lim~s

IlA

lIA

5
0

250
2

kHz

OSC SEL= OV

kHz

OSC SEL = OV, Cosc = 47pF

Note 1:

The input voltage

on PFI and WDI may be exceeded provided the input current is limited to less than 10mA.

Noto 2:

WOI is guaranteed to be in the mid-level (inactive) state ifWDI is floating and Vee is in the operating voltage range. WDI is internally bia:sed to 38% of Vcc with an impedance
of approximately 125 kilohms.
Caution - Battery Backup Function
Initial insertion of the back-up battery may cause excessive battery drain (111- 20mA) on early production parts. This condition will not damage the IC, but
could prematuraly discharge the battery.
CONDITIONS: Two conditions must be present simultaneously for the problem to ooeur: a voltage rate·of·rise greater that 0.25V/~s at the VBATT terminal (such as can
occur when battery is first inserted into the system). and Vee connected to ground with a resistance of less than 10 kilohms.
PREVENTION: Either limitthe rate·of·rise of VBATT by inserting a 100 ohm series resistor between the battery and the VBATT terminal and connect a 0.22~F or greater
capaCitor between VBATT and ground. or insert the battery while VCC is applied to the IC.
CORRECTION: In some instances, it may not be possible to take either of the preventative measures described above. Normal operation can be restored simply by
raising Vcc above VBATT (i.e., by applying power). The high current mode will not recur, even if Vcc subsequently returns to ground.

12-26

MP690/692 MP691/693

Pin Description
Name

Pin
MP690/692
MP 691/693

Function
The +5V input.

Vee
VBATT

2

3

8

1

Baekup battery input. Connect to Ground if a backup battery is not used.

VOUT

1

2

GNO

3

4

The higher of Vee or VBAH is internally switehed to VOUT' Connect VOUT to Vee if
VOUT and VBAH are not used.
OV ground reference for all signals.

RESET

7

15

RESET goes low whenever Vee falls below either the reset voltage threshold or
the VBAH input voltage. The reset threshold is typically 4.65V for the MP 690 and
MP691, and 4.4V for the MP692 and MP693. RESET remains low for 50ms after
Vee returns to 5V. RESET also goes low for 50ms if the Watchdog Timer is
enabled but not serviced within its timeout period. The RESET pulse width can
be adjusted as shown in Table 1.

WOI

6

11

The watchdog input, WOI, is a three level input. If WOI remains either high or low
for longer than the watchdog timeout period, RESET pulses low and WOO goes
low. The Watchdog Timer is disabled when WOI is left floating or is driven to midsupply. The timer resets with each transition at the Watchdog Timer Input.

PFI

4

9

PFI is the non-inverting input to the Power Fail Comparator. When PFI is less than
1.25V, PFO goes low. Connect PFI to GNO or VOUT when not used. See Figure
1.

PFO

5

10

PFO is the output olthe Power Fail Comparator. It goes low when PFI is less than
1.25V. The comparator is turned off and PFO goes low when Vee Is below VBATT'

CE IN

13

The input to the CE gating circuit. Connect to GNO or VOUT if not used.

CEOUT

12

CE OUT goes low only when CE IN is low and Vee is above the reset threshold
(4.65V for MP691, 4.4V for MP693). See Figure 6.

BATTON

5

BATT ON goes low when VOUT is internally switched to the VBATT input. It goes low
when VOUT is internally switched to Vee' The output typically sinks 7mA and can
directly drive the base of an external PNP transistor to increase the output current
above the 100mA rating of VOUT'

LOW LINE

6

LOW LINE goes low when Vee falls below the reset threshold. It returns high as
soon as Vee rises above the reset threshold. See Figure 6, Reset Timing.

RESET

16

RESET is an active high output. It is the inverse of RESET.

OSC SEL

8

When OSC SEL is unconnected or driven high, the internal oscillator sets the
reset time delay and watchdog timeout period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled. OSC SEL has a 311A internal pullup.
See Table 1.

OSCIN

7

OSC IN sets the Reset delay timing and Watchdog timeout period when OSC SEL
floats or is driven high. The timing can also be adjusted by connecting an external
capacitor to this pin. See Figure 8. When OSC SEL is low, OSC IN selects
between fast and slow Watchdog timeout periods.

14

The Watchdog Output, WOO, goes low if WOI remains either high or low for
longer than the Watchdog timeout period. WOO is set high by the next transition
at WOI. If WOI is unconnected or at mid-supply, WOO remains high. WOO also
goes high when LOW LINE goes low.

WOO

12-27

~I

MP690/692 MP691/693

Typical Applications
MP691 and MP693

this oscillator start-up time. The manual reset switch and the 0.1 ~F
capacitor connected to the reset bus can be omitted if manual reset
is not needed. An inverted, active high, RESET output is also
supplied.

A typical connection for the MP 691/693 is shown in Figure 1.
CMOS RAM is powered from Vour VOUTis internally connected to
Vee when 5V power is present, or to VBAn when Vee is less than the
battery voltage., VOUT can supply 100mA from Vec ' But if more
current is required, an external PNP transistor can be added. When
Vcc is higher than VBAn, the BATT ON output goes low, providing
7mA of base drive for the external transistor. When Vcc is lower
than VBAn, an internal500n MOSFET connects the backup battery
to Vour The quiescent current in the battery backup mode is 1J.LA
maximum when Vee is between OV and VBAn - 700mV.

Power Fail Detector
The MP691/93 issues a non-maskable interrupt (NMI) to the
microprocessor when a power failure occurs. The +5V power line
is monitored via two external resistors connected to the Power Fail
Input (PFI). When the voltage at PFI falls below 1.25V, the Power
Fail Output (PFO) drives the processor's NMI input low. If a Power
Fail threshold of 4.8V is chosen, the microprocessor will have the
time when Vce falls from 4.8V to 4.65V to save data into RAM. An
earlier power fail warning can be generated if the unregulated DC
input of the 5V regulator is available for monitoring.

Reset Output
A voltage detector monitors Vce and generates a RESET output to
hold the microprocessor's Reset line low when Vcc is below 4.65V
(4.4V for MP693). An internal monostable holds RESET low for
50ms after Vee rises above 4.65V (4.4V for MP693). This prevents
repeated toggling of RESET even if the 5V power drops out and
recovers with each power line cycle.

RAM Write Protection
The MP691/93 CE OUT line drives the Chip Select inputs of the
CMOS RAM, CE OUT follows CE IN as long as Vce is above the
4.65V (4.4V for MP693) reset threshold. If Vee falls below the reset
threshold, CE OUT goes high, independent of the logic level at CE
IN. This prevents the microprocessor from writing erroneous data
into RAM during power-up, power-down, brownouts, and momentary power interruptions. The LOW LINE output goes low when Vcc
falls below 4.65V (4.4V for MP693).

The crystal oscillator normally used to generate the clock for
microprocessors takes several milliseconds to start. Since most
microprocessors need several clock cycles to reset, RESET must
be held low until the microprocessor clock oscillator has started.
The MP690 Family power-up RESET pulse lasts 50ms to allow for

+5V
~Cp~t~-------1'---------'-- -- -..
O.I~F

.'-- - - - ---- - ---

i

i

~

I
I

15

3V

vee
1 VBAn
+ ____-'-j

Batte~f-+_ _

BATTOn

VOUT

2

CE Out

f-l;.:2'---_-'

CE In

f-l:.::3'---_-l

PFI
MP691
MP693

4

7

No Connection

8

GNO

WOI

PFO
OSCln
OSC SEL

Low Line

Reset

11

1/0

10

NMI

15

Reset

Reset
WOO

~

rO'I~F

Other System
Reset Sources
System Status Indicators

Figure 1. MFP691/693 Typical Application

12-28

Microprocessor

MP690/692 MP691/693

Watchdog Timer

MP691 and MP693. Figure 2 shows the MP690/692 in a typical
application. Operation is much the same as with the MP691/693
(Figure 1) but in this case the Power Fail Input (PFI) monitors the
unregulated inputlo the 780S regulator. The MP690 RESET output
goes low when Vcc falls below 4.6SV. The RESET output of the
MP692 goes low when Vcc drops below 4.4V.

The microprocessor drives the WATCHDOG INPUT (WDI) with an
110 line. When OSC SEL are connected, the microprocessor must
toggle the WDI pin once every 1.6 seconds to verify proper software
execution. If a hardware or software failure occurs such that WDI
is not toggled, the MP691 193 will issue a SOms RESET pulse after
1.6 seconds. This typically restarts the microprocessor's power-up
routine. A new RESET pulse is issued every 1.6 seconds until WDI
is again strobed.

The current consumption of the battery-backed-up power bus must
be less than 100mA. The MP690/692 does not have a BATT ON
output to drive an external transistor. The MP690/92 also does not
include chip enable gating circuitry that is available on the MP6911
93. In many systems though, CE gating is not needed since a low
input to the microprocessor RESET line prevents the processor
from writing to RAM during power-up and power-down transients.

The WATCHDOG OUTPUT (WDO) goes low if the watchdog timer
is not serviced within its timeout periOd. Once WDO goes low it
remains low until a transition occurs at WDI. The watchdog timer
feature can be disabled by leaving WDI unconnected. OSC IN and
OSC SEL also allow other watchdog timing options, as shown in
Table 1 and Figure 8.

The MP690/92 watchdog timer has a fixed 1.6 second timeout
period.lfWDI remainseitherloworhighformorethan 1.6seconds.,
a RESET pulse is sent to the microprocessor. The watchdog timer
is disable, if WDI is left floating.

MP690 and MP692
The 8-pin MP690 and MP 692 have most of the features of the

+

8V

+5V

Q--r--

7805

Vcc

3-Terminal

Regula10r

~

1

2
Vour

±

0.1~F

I

0.1~F

Microprocessor
power

=

=

VBATT

MP690
MP692

~11r:L
7
5

PFO

PFI

~-----

WDI

GND

Microprocessor

=

Reset

4

--'--

Power to

CMOS
RAM

Rese1
NMI
1/0 Line

j;
Figure 2. MP690/692 Typical Application

Detailed Description
Battery-Switchover and VOUT

average current drawn by the CMOS RAM if there is adequate
filtering. Many RAM data sheets specify a 7SmA maximum supply
current, but this peak current spike lasts only lOOns. A O.IIolF
bypass capacitor at Vour supplies the high instantaneous current,
while Your need only supply the average load current, which is
much less. A capacitance of O.IIolF or greater must be connected to
the Your terminal to ensure stability.

The battery switch over circuit compares Vcc to the VBATT input, and
connects Vour to whichever is higher. Switchover occurs when Vcc
is SOmV greater than VBATT as Vcc falls, and when Vcc is 70mV
more than VBATT as Vcc rises (see Figure 4). The switchover
comparator has 20mV of hystersis to prevent repeated, rapid
switching if V cc falls very slowly or remains nearly equal to the
battery voltage.
When Vcc is higher than VBATT' V CC is internally switched to Vour via
a low saturation PNP transistor. Your has 100mA output current
capability and thermal shutdown short circuit protection. Use an
external PNP pass transistor in parallel with the internal transistor
if the output current requirement at Vour exceeds 100mA or if a
lower Vcc-V our voltage differential is desired. The BATT ON output
(MP691/693 only) can directly drive the base of the external
transistor.
It should be noted that the MP690/91/92/93 need only supply the

A SOO ohm MOSFET connects the V BATT input to Your during
battery backup. This MOSFET has very low input-to-output differential (dropout voltage) at the low current levels required for battery
backup of CMOS RAM or other low power CMOS circuitry. When
Vcc equals V BATT the supply current is typically 121olA. When Vcc is
between OV and (VBATT -700mV) the typical supply current is only
600nA typical, 11!A maximum.
The MP690/691 operates with battery voltages from 2.0V to 4.2SV
while the MP692/693 operates with battery voltages from 2.0V to
4.0V. High value capacitors, either standard electrolytic or the
farad-size double layer capacitors, can also be used for short-term

12-29

•

MP690/692 MP691/693
The response time of the reset voltage comparator is about 1001LS.
Vee should be bypassed to ensure that glitches do not activate the

memory backup. The charging resistor for both capacitors and
rechargeable batteries should be connected to VOUT since this
eliminates the discharge path that exists if the resistor is connected
to Vee'
A small charging current of typically 1OnA (51L max) flows out of the
VBATT terminal. This current varies with the amount of current that
is drawn from VOUT but its polarity is such that the backup battery is
always slightly charged, and is never discharged while Vee is in its
operating voltage range. This extends the shelf life of the backup
battery by compensating for its self-discharging current. Also note
that this current poses no problem when lithium batteries are used
for backup since the maximum charging current (5ILA) is safe for
even the smallest lithium cells.
.

RESET output.
RESET also goes low if the Watchdog Timer is enabled and WDI
remains either high or low longer than the watchdog timeout period.
RESET has an internal 31!A pullup, and can either connect to an
open collector Reset bus or directly drive a CMOS gate without an
external pullup resistor.

CE Gating and RAM Write Protection
The MP691 and MP693 use two pins to control the ';:;C~:;-h;-i"E""n-a"bl;-e or
Write inputs of CMOS RAMs. When Vee is +5V, CE OUT is a
buffered replica of CE IN, with a 50ns propagation delay. If Vcc in~t
falls below 4.65V (4.5V min, 4.75V max) an internal gate forees CE
OUT high, independent of CE IN. The MP693 CE OUT goes high
whenever Vee is below 4.4V (4.25V min, 4.5V max). The CE output
of both devices is also forced high when Vee is less than VBATT' (See
Figure 5.)

If the battery-switchover section is not used, connect VSATT to GND
and connect VOUT to Vce' Table 2 shows the state of the inputs and
output in the low power battery backup mode.

Reset Output
RESET is an active low output which goes low whenever Vee falls
below 4.5V (MP690/691) or 4.25V (MP692/693). It will remain low
until Vee rises above 4.75V (MP 690/691) or 4.5V (MP692/693) for
50 milliseconds. (See Figures 5 and 6.)

CE OUTtypicallydrives the CE, CS, or Write input of battery backed
up CMOS RAM. This ensures the integrity olthe data in memory by
preventing write operations when Vee is at an invalid level. Similar
protection of EEPROMs can be achieved by using the CE OUT to
drive the Store or Write inputs of an EEPROM, EAROM, or
NOVRAM.

The guaranteed minimum and maximum thresholds olthe MP 6901
691 are 4.5V and 4.75V, while the guaranteed thresholds of the
MP692/693 are 4.25V and 4.5V. The MP690/691 is compatible
with 5V supplies with a +10%, -5% tolerance while the MP6921693
is compatible with 5V ±1 0% supplies. The resetthreshold comparator has approximately 50mVof hysteresis, with a nominal threshold
of 4.65V in the MP690/691, and 4.4V in the MP692/693.

lithe 50ns typical propagation delay of CE OUT is too long, connect
CE IN to GND and use the resulting second alternative is to AND
the LOW LINE output with the CE or WR signal. An external logic
gate and the RESET output of the MAX690/692 can also be used
for CMOS RAM write protection.

r-_ _--,VSATT
5

I=

BATIOn

+

VOUT

vee ~",3-t---..,--{;,...

+ ___________...,___

Chip-enable Input .1"'3-t-_ _

12
6

·4.4V( MP693 )

15
16

Chip Enable Output
Low Line
Reset
Reset

OSC In ~?..7+_---1TI;;;;.;t;;~:;-R.~-l
OSCSEL ~,,-8+-----t
Watchdog Input .1 1

:=::::;:;:w;:;at;::;ch:::;dog~T;:ra:::n:::;si;;;:tio:::::n=~-1

1-_-+,;...14. Watchdog Output

Detector
Power Fail ~.:..9-t-_=-_-i
Input

>-____________+-1....
0

4 Ground

=
Figure 3. MP691/693 Block Diagram

12-30

Power Fail Output

Y ee
+5Y ----------~--------------------------------------------,

MP690/692 MP691 1693

1

1-(/
i

Your

Yee

"'I

To CMOS RAM
and Realtime
Clock Yeeln

~--------------~>--------+-------;------+---

P Channel
MOSFET

Thermal
Shutdown
and

Base Drive

BattOn
(MP691/693 only)

Low IQ Mode

Internal
Shutdown
Signal When
Y BATT > Y ee +0.7Y

Select

Figure 4. Battery Switchover Block Diagram

CE IN - - - - - - - - - - - - - - - - - - \
) - - - - - - - - - - - - - - - CE Out
+-------------:"''--------------<~

Low Une

Vcc~

Power-on
Reset

Reset

Metal
Link

Trimmed
Resistors

14------

Reset

10 kHz Clock

'-----------------.... from Timebase
Section

Figure 5. Reset Block Diagram

12-31

MP690/692 MP691/693

',----------'>L4.6V
'

vee /

: 4.7V

,
I

~u~~~:

___

50ms

~t=1
__

----l

?fr4-.7V------~~

T

~

,

,,
,

I

I

LO~u~~u~

J

50ms

'------------

I

II-'- - - - -...t=1I-----'1-'_ _ _ _ _ _ __
,
,

,

--

,

',-----~

---.;....J(

11-'_______

11-'_ _ _ _ _ _ __

CE In

CEOut

Figure 6. MP691 Reset Timing

1.2SV Comparator and Power Fail Warning
The Power Fail Input (PFI) is c~ared to an internal 1.2SV
reference. The Power Fail Output (PFO) goes low when the voltage
at PFI is less than 1.2SV. Typically PFI is driven by an external
voltage divider which senses either the unregulated DC input to the
system's SV regulator or the regulated SV output. The voltage
divider ratio can be chosen such that the voltage at PFI falls below
1.2SV several milliseconds before the +SV supply falls below
4. 7SV. PFO is normally used to interruptthe microprocessor so that
data can be stored in RAM before Vce falls below 4.7SV and the
RESET output goes low (4.SV for MP692/93).
The Power Fail Detector can also monitor the backup battery to
warn of a low battery condition. To conserve battery power, the
Power Fail Detector comparator is turned off and PFO is forced low
when Vee is lower than the YeAn input voltage.

Watchdog Timer and Oscillator
The watchdog circuit monitors the activity of the microprocessor. If
the microprocessor does not toggle the Watchd0!l...!!!e!!!jWDI)
within the selected timeout period, a SO millisecond RESET pulse
is generated. Since many systems cannot service the watchdog
timer immediately after a reset, the MP691/693 has a longer
timeout period after a reset is issued. The normal timeout period

becomes effective following the first transition of WDI after RESET
has gone high. The watchdog timer is restarted at the end of Reset,
whether the Reset was caused by lack of activity on WDI or by Vee
falling below the reset threshold. If WDI remains either high or low,
reset pulses will be issued every 1.6 seconds. The watchdog monitor can be deactivated by floating the Watchdog Input (WDI).
The Watchdog Output (WOO, MP691/693 only) goes low if the
watchdog timer '1imes out", and it remains low until set high by the
next transition on the watchdog input. WOO is also set high when
Vee goes below the reset threshold.
The watchdog timeout period is fixed at 1.6 seconds and the rest
pulse width is fixed at SOms on the B-pin MP690 and MP692. The
MP691 and MP693 allow these times to be adjusted per Table 1.
Figure B show various oscillator configurations.
The internal oscillator is enabled when OSC SEL is high or floating.
In this mode, OSC IN selects between the 1.6 second and 100ms
watchdog timeout periods. In either case, immediately after a reset
the timeout period is 1.6 seconds. This gives the microprocessor
time to reinitialize the system. If OSC IN is low, then the 100ms
watchdog period becomes effective after the first transition of WDI.
The software should be written such that the I/O port driving WDI
is left in its power-up reset state until the initialization routines are
completed and the microprocessor is able to toggle WDI at the
minimum watchdog timeout period to 70ms.

12-32

MP690/692 MP691/693

,

Watchdog Input

10.24 kHz From Internal Oscillator
or Externally Sel Frequency From
OSC In Pin
Watchdog Timeout Selecl

Prescaler

Resel
Counter

Watchdog
Counter
all

Watchdog
Timeout
Selector
Logic

013
015

Goes High at the
End of Watchdog
Timeout Period

S
Watchdog
Faull FF

Q

Watchdog Oulput

Figure 7. Watchdog Timer Block Diagram

External Clock

ExternalOscilialor
OSCSEL

OSC SEL

MP691
MP693

MP691
MP693

oto 250kHz

OSCIN

OSCIN
Cose

1"
Internal Oscillator
lOOms Watchdog

Internal Oscillator
1.6 Second Watchdog
NC

-

8

8
NC -

OSCSEL

OSCSEL

MP691
MP693

MP691
MP693

NC

-

7

r

OSCIN

.".

Figure 8. Oscillator Circuits

12·33

7

OSCIN
1.....-.._ _--1

..

MP690/692 MP691/693

Table 1. MP691 and MP693 Reset Pulse Width and Watchdog Timeout Selections
OSCSEL

Watchdog Timeout Period
Normal
Immediately
After Reset

OSCIN

Low

External Clock Input

Low

External Capacitor

1024 clks

Reset
Timeout Period

4096 clks

512 clks

1.6 sec x C
47pF

400ms x C
47pF

200ms xC
47pF

High/Floating

Low

100ms

1.6 sec

50ms

High/Floating

High / Floating

1.6 sec

1.6 sec

50ms

Note 1.
Note 2.

The MP690 watchdog timeout period is fixed at 1.6 seconds nominal; the MP690 Reset pulse width is fixed at 50ms nominal.
When the MP691 OSC SEL pin is low. OSC IN can be driven by an external clock signal. or an external capacitor can be connected between OSC IN and GND. The
nominal internal oscillator frequency is 10.24kHz.
F = 1.75 X 107
The nominal oscillator frequency w~h external capacitor is
Cose
(Farads)

Note 3.

See Electrical Specifications Table for minimum and maximum timing values.

lHz)

Application Hints
Other uses of the Power Fail Detector
In Figure 9 the Power Fail Detector is used to initiate a system reset
when Vee falls to 4.85V. Since the threshold of the Power Fail
Detector is not as accurate as the onboard Reset voltage detector,
a trim put must be used to adjust the voltage detection threshold.
Both the PFO and RESET outputs have high sink current capability
and only 1O~ of source current drive. This allows the two outputs
to be connected directly to each other in a "wired or" fashion.
The overvoltage detector circuit in Figure 10 resets the microprocessor whenever the nominal5V Vee is above 5.5V. The battery
monitor circuit (Figure :!.!l shows the status of the memory backup
battery. If desired, the CE OUT can be used to apply a test load to
the battery. Since CE OUT is forced high during the battery backup
mode, the test load will not be applied to the battery while it is in use,
even if the microprocessor is not powered.

Adding Hysteresis
to the Power Fail Comparator

can be added by connecting a resistor between the PFO output and
the PFI input as shown in Figure 12. When PFO is low, resistor R3
sinks current from the summing junction at the PFI pin. When PFO
is high, the series combination of R3 and R4 source current into the
PFI summing junction.

Alternate Watchdog Input Drive Circuits
The Watchdog feature can be enabled and disabled under program
control by driving WDI with a 3-state buffer (Figure 13). The
drawback to this circuit is that a software fault may erroneously 3state the buffer, thereby preventing the MP690 from detecting that
the microprocessor is no longer working. In most cases a better
method is to extend the watchdog period rather than disabling the
watchdog. See Figure 14. When the control input is high, the OSC
SEL pin is low and the watchdog timeout is set by the external
capacitor. A 0.0111F capacitor sets a watchdog timeout delay of 100
seconds. When the control input is low, the OSC SEL pin is driven
high, selecting the internal oscillator. The 100ms or the 1.6 see
period is chosen, depending on which diode in Figure 14 is used.

Since the power fail comparator circuit is non-inverting, hysteresis
+5V

+5V

vee

vee

29.4k!l

2k!l

PFI

10k!l

MP690
MP691
MP692
MP693

GND

=

=

~

35.7kO

~

Reset

Reset

Reset
Input

PFO

PFI

2k!l

Reset
Input

MP690
MP691
MP692
MP693

N·Channel

PFO

I

lOkO

GND

=

=

=

=

Figure 10. Reset on Overvoltage or Undervoltage

Figure 9. Externally Adjustable Vee Reset Threshold

12-34

MP690/692 MP691/693
7V -1SV
vee
R4
10kQ

+SV

PFO

R1
7SkQ
VSATI

vee

Low Battery
PFO ------+- Signal to
~P 1/0 Pin

MP690
MP691
MP692
MP693

PFI

10MQ

GND
PFI

10MQ

MP690
MP691
MP692
MP693

R2
13kQ

R3
300kQ
To~P

CE Out
RL

GND

CE In

Low

From~P

V H = 8.7SV
V L = 7.6V
Hysteresis = 1.1SV

Applies 1/0 Pin
Load
to Battery

( 1

V H = t.2V

( t

+

B..!

Hysteresis ", 5V

x

B..!

Assuming R4

Figure 11. Backup Battery Monitor with Optional Test Load

B..!

V H =1.2V

R2

R2

B..!)
R3
ISV - 1.25V) R1 )
1.2SV (SR3 + R4)

R3

« R3

Figure 12. Adding Hysteresis to the Power Fail Voltage
Comparator

+SV

+SV
Low = Internal Watchdog
Timeout
Vee

Watchdog
Strobe

WDI

OSC SEL Vee

Hi = External
Watchdog ,
Timeout -7,·

MP690
MP69t
MP692
MP693

jf

Watchdog
Disable

MP691
MP693

Connect for
I
1.6 sec Timeout
when Internal
Timeout is Selected

GND

Figure 13. Disabling the Watchdog under Program Control

Figure 14. Selecting Internal or External Watchdog Timeout

12·35

MP690/692 MP691/693

Table 2. Input and Output Status In Battery Backup Mode
VBATI • VOUT

V BATI is connected to VOUT via internal MOSFET.

RESET

Logic low.

RESET

Logic high. The open circuit output voltage is equal to VOUT"

LOW LINE

Logic low.

BATION

Logic high.

WOI

WOI is internally disconnected from its internal pullup and does not source or sink current as long as its input
voltage is between GNO and VOUT" The input voltage does not affect supply current.

WDO

Logic high.

PFI

The Power Fail Comparator is turned off and the Power Fail Input voltage has no effect on the Power Fail
Output.

PFO

Logic low.

CE IN

CE IN has a 21JA input pullup current source. Float or drive high to minimize supply current.

CEOUT

Logic high.

OSCIN

OSC IN is ignored.

OSCSEL

OSC SEL is ignored.

Vee

Approximately 121JA is drawn from the V BATI input when Vee is between VSATI + 100mV and VBATI - 700mV.
The supply current is 11lA maximum when Vee is less than V BATI -700mV.

Package Information

ff.
0.400

(10.160) MAX

I

0.291
(7.391) MAX

--ooj

I--

Lead #1

0.025 RAD
(0.635)

0.060 ±0.005
(1.524±0.127)
0.290 - 0.320

0.020 - 0.070
(0.508-1.778)

0.200 MAX
(5.080)

1

(7.366-8.128)

~~--+(~::~~)

0.060 MAX
(1.524)

j---.I

MIN

J] I'L-t
-I

0.10010.010

0.018±0.002

j..-

(2.540 ±0.254)

8 LEAD CEROIP (D)

= 125·CIW
=55·elW

12-36

0.160
(4.064) MAX

.-,~\
,.~-,.,,,
WI-

(O.457±O.051)

0ja
0je

r

(0.203- 0.305)

0.3B5±0.025
(9.779±0.635)

MP690/692 MP691/693
Lead #1

0.291 - 0.299 0.344 - 0.364
0.394-0.419
(7.390-7.959) (8.738-9.246) (10.00r 10.643)

1.!;=rr;=rrn=;=;=n=;;=;=;!J

-

L

j

II

0.014 _ 0.019

-

~

~

0.050 BSC.
(1.270)

(0.356 - 0.482)
0.092 - 0.1 04

t
J I-

-1 r(~:~!~)

~ MAx~(2.337_2.642)

--

45~1

(10.465)

0.030 MAX
(0.762)

0.003 - 0.011
(0.076 - 0.279)

3"-ff'

~JJ

J L 11

];,
0.088 _ 0.096

0.053 MIN
(1.346)

(2.250 - 2.450)

0.009-0.012
(0.229 - 0.305)

16 Lead Small Outline, Wide (WG)
Sja= 105° CIW
Sjc = 60°CIW

0.780 MAX
(19.812)

0.250+0.005
(6.350±0.127)
0.025 +0.015
(0.635±0.381)

_~
L

0.030-0.110 RAD
(0.762-2.794)

--I \.-

~
0.130±0.005 ~ •
3.302±0.127

T--=r=

0.020 MIN
(0508)
.

Lead #1

0.040 TYP

0.020

(1.016)~(0.508)
--:---T

~ T

~ ~~~ ~--r

L 0 .125 MIN
(3.175)

0.018 + 0.003
(0.457 ±0.076)

0.300 - 0.320
(7.620 - 8.128)

~

00-1~

0.009-0.015

WI(O.229-0.381)
0.325 + 0.025
-0.015

0.100±0.010
2.540±0.254

)
( 8.255 _+0.635
0.381

16 Lead Plastic DIP (P)
Sja = 100°CIW
Sjc = 6rI'CIW

12-37

0.395 MAX

0.250±0.005
(S.3SO±0.127)

I~L;~~;;~:~~
~

0.025 ± 0.015 --I I--

I

RAD

0 300 _ 0 320

,:;;;~dQ~;;'., "~=,
~ WW:
L' ~L~'
0.020
- MIN
(0.508)
j~
0.018 ± 0.003
(0.457 ± 0.07S)

5

MP690/692 MP691/693

0.785 MAX
19.939)

--.

00_10°1=---11-0.009-0.015
(0.229 - 0.381)

0.100 ±0.010
(2.540 ±0.254)

0.325 + 0.025

0.291
(7.391)MAX
0.050
(1.270) MAX

L••d#1
0.025 RAD
V(0.S35)

II
--Ii-

•
~MAX~
(4.064)
t-=;=

J

H

0.125 MIN

~(3.175)

0.020-0.070
(0.508 1.778)
0.100±0.010
(2.540 ± 0.254)

BL

0.290 - 0.320
(7.366 -8.128)

0.060± 0.005
(1.524±0.127)

~

II II T
-II-- -11-

00_1()'
0.018±0.002
(0.457 ±0.051)

I_~

0.385 ± 0.025
(9.779 ± 0.635)

~

0.635 )
( 8255+
-0.381
.

8 LEAD PLASTIC DIP (P)

16 LEAD CERDIP (D)
Sja = 100° elW

Sj.=120"CIW
Sje = 70"CIW

0je = 50°CIW

Pin Configuration
MP690 & MP692

MP691 & MP693
V BATT

VBATT

RESET

V OUT

WOI
PFO

RESET
RESET

VCC

WOO

GNO

CEIN

BATTON
top view

8-pin DIP

CEOUT

LOW LINE

WOI

OSCIN

PFO

OSCSEL

PFI

lop view
16-pin DIP

12-38

(0.203-0.305)

4

SD2

"--'-' §upertex inc.
CMOS Photo-Electric Smoke
Detector Integrated Circuit
Ordering Information
Package

Order No.

16-Pin Plastic

SD2P

Features

General Description

o
o
o
o
o
o
o
o
o
o
o

This low power CMOS circuit is intended for use in a pulsed LED/
silicon cell smoke detector system. It is designed for use in low
power, battery operated, consumer applications with a minimum
of external components. This device meets UL217 requirements
and is available in a 16-pin plastic DIP.

6~A -

Average Standby Current

Minimum Cost of External Components
1mV Sensitivity
8 to 1 Increase of Sample Rate when smoke detected
Improved Noise Rejection by multiple sampling

Pin Configuration

Automatic LED Supervisor Alarm
Multi-Station InpuVOutput Capability

PHOTODIODE

1

VDD

LED PRE-DRIVER

Horn Modulation Mode Control
Piezoelectric Horn Driver
Smoke Sensitivity Adjustable by single resistor
Self-contained Oscillator requires only a resistor

Absolute Maximum Ratings
Supply Voltage

-0.5 to VDD +0.5V

Input Current, Any Input

±10mA

LED SUP'R

LOW BATT ADJ

4

110

SENSADJ

5

HORN MODUL

6

RTIMING

7

OPMONlTOR
11

FEEDBACK
HORN 1

top view

16-pin DIP

Storage Temperature Range
300mW
25mA

Lead Temperature (Soldering, 10 sec)
Relative Humidity

3

HORN 2

Operating Free Air Temperature Range
Power Dissipation (Package)

2

-0.5V to +15.0V

Input Voltage, All inputs

Continuous Output Drive Current

CMEMORY
LATCH/RESET

90%

12-39

SD2

Electrical Characteristics
(w/R-(7)

= 22 Meg n then fosc =485 Hz; TA = 25° C;Voo = 9V, unless otherwise specified)
.. '

!!Iymbol

Parameter

"

liN

Photodiode Input Leakage Cu~rent '

vpo

Photodiode Input Signal Sensitivity

Low Battery Threshold Voltage

VBTH

tTBL

Min

Typ

Max

Units

0.Q1

±1.0

nA

0.5

0.8

1.1

mV

7.3

7.7

8.2

V

Horn Modulation Frequency

8

Hz

Horn Modulation Duty Cycle

62.5

%

Low Battery/LED
Supervisor Trouble
Alarm Pulse Width

Conditions
Cmem = .051!F
CinPU\ =5pF
t LEO = 1001! sec
R(4) =cc
PIN 6to Voo
R(7) =22 meg n
Smoke Detected

=485 Hz
=22 Meg n

@ losc

17

mSec

R(7)

35

sec

@ lose =485 Hz

mA

Vo

TTBL

Low Battery/LED
Supervisor Alarm Period

lOUT

Horn Output Current

VIN

Feedback Input Voltage Range

10M

Operation Monitor
Output Current, Source

-2.5

-4.5

mA

VOM

1 1/0

I/O Output Source Current

-4.0

-10.0

mA

V I/O

Remote Alarm Trigger Voltage

0.6 Voo

VI/O =Voo -1.0
Sink Current 20mA
typical at Voo =4.5V

VIH _ON

LED Supervisor, upper
Threshold Range

Voo - 0.8

Voo - 0.2

VI-OFF
VIL _ON

LED Supervisor, Sale Region

Voo - 2.5

Voo - 0.8

LED Supervisor, lower
Threshold Range

Voo - 4.0

Voo - 2.5

=22 Meg n
=IV Sink
Vo =8V Source
R(7)

±25
Vss -15

-10

Voo + 15

V

V

Typical Min and Max.
Not 100% tested

=2.0V

V

=5V

ILEO

LED Output Source Current

-20

mA

VLEO

TLEO

Photodiode Sample Pulse
Period (Smoke Detected)

1.0

sec

losc =485 Hz

TLEO

Photodiode Sample Pulse
Period (Smoke Detected)

8.0

sec

lose =485 Hz
R(7) =22 meg

Voo

Supply Voltage

100

Average Standby Supply Current

7.0

12-40

9.0

10.0

V

6.0

10.0

I!A

n

R(7) =22 Meg n
V00 =9.0, Non-Alarm Mode

SD2

Pin Definition
Pin

Function

Name

1 Photodiode Input

Connect the cathode of a VTS-4085S, or equivalent, to pin 1. Connect the anode to V00' The
typical allowed signal range is from Voo to Voo -1.0V.

2 Memory Capacitor Input

The capacitor may range from 0.Q1 ~F to 0.05~F and should have low leakage. The detector
sensitivity increases with increasing capacitance.

3 Latch/Reset Input

When connected to V00' the detector will latch on at the first detection of smoke alarm. When
connected to V55' the alarm will not latch on detection of smoke and the low battery condition
will not override the smoke alarm condition. Reset after latching is accomplished by
momentarily connecting this pin to VSS until the horn silences. The Latch/Reset Input only
affects the local smoke alarm response.

4 Low Battery Threshold

The nominal threshold of the battery alarm is 7.7 volts. The alarm can be raised by connecting
Adjustment a resistor to ground, and lowered by connecting a resistor to Voo'

5 Smoke Sensitivity Adjustment

A resistor or potentiometer to ground is used to adjust the duration of the LED pulse and
thereby the Smoke Sensitivity. Pulse duration is proportional to the resistor value and varies
approximately 100~sec per megohm.

6 Horn Modulation Control Input

When connected to V00' the Horn will pulse ON and OFF at approximately 8 Hz, with the ON
time exceeding the OFF time. When connected to V55' the "Smoke" alarm will sound the Horn
continuously. This control only affects the "Smoke" alarm condition.

7 Timing Resistor

A nominal resistor value of 22 megohms to V55 sets the oscillator frequency to 485 Hz. Thus:
a) The IR LED pulses every 8 seconds in standby.
b) The OPERATION MONITOR LED pulses very 35 seconds in standby.
c) The Horn modulation (ON-OFF) frequency is approximately 8Hz.
d) The Low Battery or LED SUPERVISOR trouble pulse to the Horn will occur every 35
seconds, with 17ms duration.
e) The IR LED will pulse every 1 second when smoke is detected.
f) The Horn will be silenced just before each IR LED pulse for 4.2 ms, to reduce electromagnetic interference.

8 Vss
9 Horn Output 2

Connect this pin to circuit common, the lowest potential.
This terminal is connected to the brass electrode of the piezoelectric horn.

10 Horn Output 1

This pin is connected to the large silver electrode of the piezoelectric horn.

11

This pin is connected to the small silver electrode of the piezoelectric horn.

Horn Feedback

12 Operation Monitor

This output is a current source of 4mA for driving a visible LED. The LED will flash for 17ms
every 35 seconds under normal conditions. The LED will be ON continuously when smoke is
first detected. This occurs before the alarm sounds and indicates that the detector is in speedup mode (1.0 second LED pulse period). This output indicates which unit is alarming in multiple station applications. When this output is used for both local LED indication and remote
logic, a resistor must be placed in series with the LED.

13

Multiple Station InpuVOutput

14

LED Supervisor

This InpuVOutput may be connected via twisted pairs to at least 20 other units. The output
goes high after at least two consecutive smoke detections have been made. The output
structure allows units of different operating voltages to be connected together with no
impairment of performance or excessive loading ofthe higher voltage units. There is an active
pull-down on the output. Because of the high currents sourcing capability of the output, this
pin should never be connected to V55 via a low impedance path. An Input level of greater than
0.6V oo volts is required to ensure a local alarm.
This pin must be connected to the LED circuit as shown. Failures detected are open or shorted
conditions in the LED and Driver circuit. A failure is indicated by a local pulsed trouble alarm.
To defeat this feature, pin 14 must be tied to a voltage about 1.5-volts below V00' or to pin 2
in most applications.

15 LED Pre-Driver Output

This terminal can source about 13mA. The output voltage is zener clamped at approximately
6.7Vand the current becomes limited. The LED current set resistor may be put in the collector
circuit, below the LED, butthe LED current and therefore the Sensitivity of the smoke detector
will vary with supply voltage.

12-41

-

Pin Definition
Name

Pin
16

9,10

SD2

(cont.)
Function

Voo

This pin is connected to the positive battery terminal. Pin 16 should be solidly connected to
the V DO side of both the photodiode and the memory capacitor. A V DO guard-ring type foil path
around pins 1 and 2 will enhance noise immunity of the detection circuit. This circuit will
operate from 7 to 10 volts, although average standby current will increase with supply voltage.
Protect the integrated circuit from polarity reversal.

Alternate Driver for ElectroMechanical Horns

When the smoke detector circuit is used to drive either a transistorized mechanical or electromechanical horn, the feedback (pin 11) must be connected to Voo. When an alarm condition
is not present, pin 10 will be at V DO and pin 9 will be at Vss. When an alarm condition is present,
pin 10 will switch from VDO to Vss and pin 9 will switch from Vss to V DO. Both horn outputs are
capable of sinking or sourcing more than 1OOmA at a 9-volt supply voltage. Limit the steady
state on current to 25mA.

Transistorized Mech. Horn

The control tab of the horn is connected to pin 9 and pin lOis left open.

Electro-Mechanical Horn

Pin 9 is connected through a resistor to the base of an NPN horn driver transistor. Pin lOis
left open.

Timing Waveform
I

Single Smoke

I

Detection

I

I

I

I

I

Latch Mode

f.oj"<---f--j---+-.----355----+----~_j
SMOKE
CONDITION

LED
PRE·DRIVER
(PIN 15)

n:

i :n

n LJ=-:
nI_S_n_'o_ke_____~.n~.____~________

~ I~::~~~.~.::~;:::~I~
t+-- 85
_j"
85
_I"

III
---.j k17ms
~I+--I

0.55

11111
-..! k-

No

85

I

-j"

1111 III

85

I

_I"
85 -j ..
11111I111 III

85---+1

1

105

I-

OP/MON
(PIN 12J

~

I/O
(PIN 13)
HORN 1
(PIN 10)

__~r--l~________~
LJ :=:=;u 2--,-1-----'
Trouble Alarm
Pulse

_ _ _ _-JnL-_...J1l

HORN 2
(PIN 9)

Remote

Input

r

'----'

Low Battery
Override

~

i==.:
Reset

MODE

Low Battery Condition

LOW BATTERY
CONDITION

12-42

L

SD2

Truth Table
Input Conditions
Alarm Status
Standby
Remote
Smoke

Low
Batt.

LED
Sup'r

Pin 3
Latch

Pin4
Batt

Pin 6
Mod'i

Pin 11
Fdbk

Pin 13

Ping

1/0

H2

F
F
F

F
X
X
X
X
F

X
X
X

H4

N

L

H4

H

H

H4

H

L
H5
H5.6

L

H4

H

H4

L
H

H4
H4

T

T

F
X

X
X
X
X
X

H
H4

X

N
N
N
N
N
N
N
N
N
N

X

F
T
T

F
X
X
X
X
X
X
X
X

Local

T(A)

Smoke

T(A)

Local
Smoke

T(B)
T(B)

Latched

T(B)

Low Batt

F
F
F
X

LED Sup'r
Batt Disable
Horn Disable
Key:

TFHLPNX-

Output Conditions

Smoke

X

Logical TRUE, Analog Condition
Logical FALSE, Analog Condition
Logical HIGH, Digital Level or Driver Sourcing
Logical LOW, Digital Level or Driver Sinking
Output PULSE HIGH, Normally LOW
No Signal Applied / Open
Unspecified

L
L
H
H
H

X
X
X
X
Notes:

H

N

H4
H4
L

N
N
N
N
N
N
N
N
N

Pin 10 Pin 12 Pin 13 Pin 15
H1 OPIMO
110
LED
pI
p2
L
H
pI
p2
L5
N
L5.6

pI

N

H5

L5

H

H

p3

H'·D
H5

L'·D
L5

H

H

H'·D

L'·D

H
H

H
H

p'
p3

L
Ll

H
HI

H
pI

H

po

L

p2

Ll

HI

pI

L

p2

L

H

pI

L

p2

L

H

X

X

X

1. Pulsed to opposite state ONCE every fourth PULSE on pin t 5.
2. Normal Sample Rate, Typical 8 seconds.
3. 8 Times Normal Sample Rate, Typical t .0 second.
4. When used with a piezo horn, this signal is oscillating,but considered HIGH.
5. When used with a pieza horn, this signal is oscillating.
6. Signal will be in non-alarm state 37.5% of time.

A - After two consecutive smoke detections

8 - After one smoke detection

Block Diagram
o!~::::::::::::::::::::::::::~------------V-D-D-~l16 VOD

H--r::~ SoPEED·lJP

H-----I:>-.....------7"=o3 110

BA~~~RV ~~----.=ll~>-------ii

FEEOBACK
HORN 1

ADJUST

HORN2

LED

,4

SUPERVISOR

SENSITIVITY o2.5L-----Ir;;;;;;;;;---;~1J1-----------+_tI>_r------~~ LED
ADJUST

PRE·DRIVER

R:~~~OGR

0.:.'=-____--1
vss~tl~vs~s__~::::~__~::::::~==~::~

12-43

__________~

p2

p3

SD2

Operation
This device utilizes low power CMOS technology to provide all of
the necessary functions of a battery operated. photoelectric smoke .
detector using a minimum of external components.
.
The LED PRE-DRIVER output pulses an external transistor which
in turn. switches on the infrared light emitting diode at a very low
duty cycle. The desired IR LED pulse period is determined by the
value of the external timing resistor. The Smoke Sensitivity is
adjustable through a trimmer resistor which varies the IR LED pulse
width.

tion. the unit will sound a continuous alarm when smoke is detected
even during low battery conditions .. When the alarm mode control
is set for latching operation. the low battery trouble alarm will
override the smoke alarm. in accordance with UL217specifications.
The LED SUPERVISOR tests for open or shorted conditions in the
LED and Driver circuit. For either condition of the IR LED when
pulsed. failure of the forward voltage to fall between two limits
produces a trouble alarm pulse on the Horn after every fourth LED
pulse.

The light sensing element is a silicon photovoltaic cell which is held
at near zero bias to minimize leakage currents. The circuit can
detect signals as low as 1mV and generate an alarm. The IR LED
pulse repetition rate increases when smoke is detected.

The Input/Output terminal (1/0) is used to interconnect SD2 units for
multiple station applications.
The OPERATION MONITOR pulses a visible LED after every
fourth IR LED pulse to indicate device operation. For a local Smoke
detection the LED is driven continuously.

For use with a 9-volt battery. an internal zener is incorporated into
the IC. When the minimum battery voltage is reached (tested during
the IR LED on pulse). the output produces a short trouble alarm
pulse or "blip". The horn is pulsed after every fourth IR LED pulse.
When the alarm mode control is set for non-latching opera-

The Horn Driver circuit self-oscillates with a piezoelectric element
or enables an electro-mechanical horn when pin 11 is connected to
VDD •

Typical System --- Non-Latching Single Station
SMOKE CHAMBER

r--,
I

100~F

*

lK

NOTE 1

I

I IR I
I LED I

:NOT~

I

2

I

16

L_..J

15
14
LOW
BATTERY
DISABLE
ALARM

13

4

SD2

= 2M!l

12
11
10

22MSl
30K

-=

t::::=J

PIEZOELECTRIC HORN
CATT -101FB

Notes: 1. IR Diode RCA Type SG 1010A or Spectronics Type SE 5455-4
Cleirex Type CLED-l
2. I R Photo detectors Vactec VTS4085

12-44

SD2

Typical Performance Curves (TA = 25°C unless otherwise noted)
TLEDvS VDD.

TPDVSVDD

100

1000

~

Q
a:

-

w
w_

Cl.

5g

::>2

R '(pin~)

= ~Mn

I

-

I--

z

0

o

2~n

§~ 100

l~n

Z

-

R (pin 7)

10

= 40 Mn

~

20MJ

Cl.

o-

0

w

w
~

10Mn

...J

500Kn

::>

!!:

Cl.

o

w

...J

a:
1

6

10

8

12

10
6

14

8

VDD (VOLTS)

10

12

VDD (VOLTS)

IR LED VS TLED vs Oscillator
OSCILLATOR (PIN 7)
(Hz)

4100
10.0

Detector Sensitivity vs CMEM

410

41

10.0
~

~

I'

z

~

/

>-

!::;;

~.s

1

1.0

f'\

(jj

z
w

I'

C/l

0.1
10.0

100.0

0.02

(uF)

= [OOH(15)) + ILED] ~~~D

1

0

I'.

}ljll1i'°~i
II!~

.D-I+tf

7.8

~~isl.I1il~o Voo

II 1111
II 1111

6
100K

0.2

MEMORY CAPACITOR

I R LED - PU LSE PER 100
(PIN 15) (sec)
IAVG (LED)

0.1

1M

RESISTOR (PIN 4)
(OHMS)

12-45

14

a
"--'-' §upertex inc.

SD3A

Ionization Chamber Type
Smoke Detector Circuit
Ordering Information
Package

Order No.

14 Pin Plastic

SD3AP

General Description

Features
0

Capable of Directly Driving Piezoelectric Horn

0

Multiple 1/0 Station Capability

0

Low Battery Level Beep Alarm

0

Continuous or Intermittent Alarm

0

LowPower Consumption - 10j.1A Maximum

0

High Noise Immunity CMOS Technology

0

Meets UL217 Requirements

0

Uses Economical Zinc Carbon 9V Battery

0

No Voltage Detection Adjustment Necessary

0

Optional Battery Impedance Check

The SD3A is a CMOS integrated circuit designed for an ionization
chamber type smoke detector that directly drives a piezoelectric
horn. It satisfies UL217 requirements and is available in a 14-lead
plastic DIP.
Designed and built for an efficient, low component count, smoke
detector system, the SD3A has numerous features that allow
increased alarm effectiveness and reduced false triggering. With
an improved offset voltage and built-in hysteresis, this device
requires less ion source and has increased sensitivity.
The horn output of this circuit can be a continuous or intermittent
alarm. An optional LED indicafor can be used to monitor the
battery level. The SD3A operates on a single 9-volt alkaline or zinc
carbon battery. It also may be used in multiple station connection
applications.

Absolute Maximum Ratings

Pin Configuration

Storage Temperature Range
Operating Temperature
Supply Voltage
Voltage on All Other Pins
Power Dissipation

N/C

+1S.0V

IclN

BAIT

-O.3V to Voo + O.3V
1/0

300mW

ICR

Relative Humidity Range

Voo

10
9

H2
GND

H1
top view

14-pin DIP

12-46

H3

SD3A

DC Electrical Characteristics
Parameter

Symbol

Operating Voltage

Voo

Supply Current

100

Ionization Chamber Input
Reference Voltage

Min

Typ

S.O
7.0
1/2Voo - 0.15

VIR
II

Ionization Chamber Input
Offset Voltage

Vos

Input/Output Alarm
Trigger Voltage

VI/O

3.0

Units

10.0

V

10.0

~A

Voo

V

VIR

V

VIR tied to external
resistor

1.0

pA

Input Voltage

150

mV

1/2V oo 1/2Voo + 0.15

0.5

Ionization Chamber Input
leakage Current

Max

Voo - 3

50

Conditions

=9.0V; lED not con't
=floating
=9.0V

V

Input/Output Drive Current

1110

-3.0

-5.0

Operating Voltage
low Voltage Detection

Voo

7.5

7.7

Horn Current
H2,H3

I HORN

lED Current

ILEO

mA
7.9

V

Voo =7.0V; VIO =S.OV
No Adjustment
Necessary

2

4

Ie

20

40

SO

sec

10

20

30

msec

lED Flash Period

tON
tLEO

30

sec

=7.0V; VHORN = 1.0V
=7.0V; VHORN =5.0V
Voo =B.OV
CL = 1~F; Voo =B.OV
CL = 1~F; Voo =B.OV
CL = 1~F; Voo =B.OV

Horn Pulse ON/OFF Time

tose

sec

Intermittent Mode Only

Clock Period
Clock ON Time

-25

mA

10
0.5

25

mA
mA

Voo
Voo

Pin Definition
Label

SD3APIn

ClK

11

Clock oscillates with a nominal period of 40 sec when an external 1~F capacitor is connected to
the clock lead.

Function

ICR

12

The Ionization Chamber Reference Input is connected to the other side of the Ionization Chamber
comparator. It is set at 1/2 Voo generated by an internal resistor network.

IC IN

14

The Ionization Chamber Input has high input impedence and is connected to one side of the
Ionization Chamber comparator.

I/O

3

Input/Output terminal can drive up to 20 units using a simple two wire bus.

lED

4

An optional light Emitting Diode can be attached to this lead to monitor operation of the SD3A.

Voo

5

Power Supply.

H1
GND

7

The Horn Driver Feedback Input is used for a piezoelectric horn feedback connection.

B

Ground.

H2

9

This horn driver output connects to the brass disc of the piezoelectric horn.

Hs
lV R

10

This horn driver output connects to the top electrode of the piezoelectric horn.

2

For low Voltage Detection Point Adjustment.

OPT

S

This pin controls the type of horn drive. When tied to VDO' the horn output is continuous. When this
pin is left open, the horn output is intermittent.

BATT

13

This lead is for battery Test.

12-47

SD3A

Block Diagram
VDD

DPTo>------I

Operation
The SD3A is specifically designed to directly drive a piezoelectric
horn. In this circuit the ionization chamber input (lCIN) is connected
to the first input of a voltage comparator which responds to a voltage
drop by activating the horn. The other input of the voltage comparator is connected to an internal reference voltage preset at VDr/2.
This reference voltage can also be adjusted externally by a resistor
or potentiometer tied to the ionization chamber reference input
(lCR)' Adjustment of the bias voltage sets the sensitivity of the
chamber to the smoke.

chanical horn through an external resistor. The piezoelectric horn
drive provides a feedback lead for resonance oscillation to boost
the sound output level at a modulated tone to increase the horn
effectiveness.
Low voltage is detected by the internal zener reference and voltage
detection circuitry. This design allows either utilization of the preset
low voltage detection level or external adjustment using a resistor
tied to the low voltage reference (LV R) lead of SD3A. The preset low
battery voltage detection level is at 7.7 volts ± 2.0V. Several
connection options are illustrated in Figures 1, 2 and 3.

The horn output of this device can be connected to an electrome-

, ", 1T

LED

LV,

VDD

IC,

LED

150K

",

SD3A

ALKALI NE
OR ZINC
CARBON

I. 5M

"3

BATTERY

DUAL IONIZATION CHAMBER

PIEZOELECTRIC HORN

Figure 1.

Ie! ~
9V

"2

SD3A with a Daullonization Chamber and Piezoelectric Horn together with an LED as battery connection indicator.

12-48

SD3A

eF

!"

lEO

r-

)OOuF

LV,

ElECTROMEeHAN I CAL I

HORN

I

",

lEO
H,

lOOK

I

VOO

SD3A

I C IN

OUTER

__ J

ELECTRODE

~______~I~eO~l~lE~e~TO~'~'___ ~_'~T~E~ST~~4
ELECTRODE

ELECTRODE

H2

AMER5HAM

HJ

ONO

9V

'/0 elK

OSCA3DR

SOURCE
ELECTRODE

~QuIVALENT

BATTERY

TEST

PUSH
SUTTON

=
Figure 2.

~

SD3A with an Amersham DSC A3 Concentric Chamber and an electromechanical Horn. Special features are optional
R1/R2 resistor network for adjusting comparator trip voltage and built-in test electrode for in-circuit alarm test.

30K

LEO

lV,

O.2uF

",

lEO
BATT

2N3906

H,

'SDK

lOuF

voo OPT

I C IN

SD3A

9V
H2

ALKALI NE
OR ZINC
CARBON

I. 5"
H)

BATTERY

DUAL ION I ZAT I ON CHAMBER

Figure 3. SD3A with a Dual Ion Chamber, Piezoelectric Horn, LED, Battery Impedance Check, and Intermittent Horn.

Multiple Station Connection
The SD3A can drive up to 20 units simultaneously. When any unit
detects smoke, all the units are triggered. However, when only
one unit gives a beep indicating low battery level, only that unit

STAT'ON 1

beeps. Multiple station connection of SD3A devices requires only
a simple two-wire bus.

STATION 2

12-49

STATION 20

..

Alphanumeric Index and Ordering Information
Company Profile
Application Notes
Static Handling Procedures and Quality Assurance
Process Flow
DMOS Product Family
N- and p. Channel Low Threshold MOSFETs
DMOS Discretes N-Channel
DMOS Discretes P-Channel
DMOS Arrays and Special Functions
HVCMOS High Voltage ICs
CMOS Consumer/Industrial Products
Lead Bend Options and Surface Mount Packages

Package Outlines
Representatives/Distributors

.~

..
....
....
•
".
\'a.

;

~

~

,,-

~

-

!

"§upertex inc.
Surface Mount Packages
Various surface mount packages are available for HVCMOS, DMOS, and CMOS devices. Refer to the respective product data sheet for
availability and package outline for detailed dimensional drawings. This section also includes lead bend and taping options.

Type "C" Leadless
20 Terminal
Ceramic Chip Carrier

16 Terminal
Ceramic Chip Carrier

16-Lead *
Small Outline

20-Lead *
Small Outline

28-Lead *
Small Outline

36-Leaded Ceramic Chip Carrier
Available with "CR", "CF", and "CS"
Lead Bend Options

28-Lead Plastic Quad
"J" Bend

*300 mil wide body.

13-1

44-Lead Plastic and Ceramic Quads
"J" Bend

80-Lead Plastic and Ceramic Quads

84-Terminal Ceramic Chip Carrier
Type "B"

84-Lead Plastic Quad
"J" Bend

o
o
o
Die on tape
(for Tape Automated Bonding)

13-2

"§upertex inc.
Lead Bend Options
Lead bend options are available in order to retrofit existing boards with small, cost effective, pin-compatible TO-92 packages, or for the
purpose of surface mounting.

~g

I
I

~ ~~~. ~

:

~

.050 + .010
.050 + .010

t

~\---I
~.010
----.JF
' - - - - 1 ---r

L--.

Figure 1
TO·92 leads bent for TO·18 or TO·52 pin circle (Ordering information: Option P015)'

.050 ± .01 0

--1
I

J--L

.050 ± .010

Figure 2
TO·92 leads bent for reversed TO·18 or TO·52 pin circle (Ordering information: Option P01S)'

*Lead lengths are those of original components as shown in the Package Outline Section (i.e., uncropped, unless otherwise specified).

13-3

~-===::=:-=-3

-----.
.100 ± .010

l

.100 ± .010

~::::=:=3 -----.i

~ i1c;oo '1--

__ .100
±.010

I
L '

Figure 3
TO-92 leads bent for TO-5 or TO-39 pin circle (Ordering information: Option P017)*

-;=-===:::::-=-3 -----.
.100±.010

;

.100±.010

~==3 -----.i

I

--m~
~!~~OO

-__ .100
±.010

L '

Figure 4
TO-92 leads bent for reversed TO-5 or TO-39 pin circle (Ordering information: Option P018)*

------------=±!

1-

Figure 5
TO-92 leads bent for TO-220 (Ordering information: Option P011)*

*Lead lengths are those of original components as shown in t~9 Package Outline Section (Le., uncropped, unless otherwise specified).

13-4

1_ _1
0 .175
0.185

-r
0.175
0.185

0.226 Max.

L

L -- - ---------'--

I---

0.190 _ _
0.160

1 - - - - - 0.375 Max. ------1

0.135
0.145

LLI
[

tj'l-

0.002
0.025

Nominal~

Figure 6
TO·92 for surface mounting. Leads formed for pad spacing of 0.100" center to center
(Ordering information: Option P010)

~r-------~~~
0.175
0.185

Lr-------~
I--

I

..

0.175---1
0.185

I

-t
0.135
0.145

0.002
0.025

~L=+=======,---_~~
J :
=-t
j............_ _ _ 0.295
0.315

-----1

0.010
0.015

Figure 7
TO·92 for surface mounting. Leads formed for pad spacing of 0.050" center to center
(Ordering information: Option P012)
13-5

"§upertex inc.
TO-92 Taping Specifications and Winding Styles
(per EIA Standard RS468)
Extraction force
Min 300gf

fr

P
Po
P,
P2
P3
W
Wo
W,
W2
W3
H

Ho
F
F,-F2
Do

12.7±0.5
12.7±0.2
3.S5±0.5
6.35±0.5
6.35

16±0.5
5±0,s
-0,2
±0.3
4±0.2
0.7±0.2

t

1S:6:~
6±1

Ah
d

R

9±0.5
Max. 0.5

0±1
O. 50 :g:g~dia.
O.S
45°-60°
Max. 11

Ct

Min.4.5
19.5±0.5

L

0±0.5

Ac

All dimensions in millimeters.
STYLE A

STYLE E

STYLE A IS PREFERRED

STYLE EIS A PREFERRED STYLE

STYLE P
ADHESIVETAPf:
FLAT SIDE

CARRIER STRIP

_ _ _ _ _ _--"

FEEO-~

ROUNDED SIDE OF TRANSISTOR AND ADHESIVE TAPE VISIBLE

STYLE B

FLAT SIDE OF TRANSISTOR AND ADHESIVE TAPE VISIBLE

STYLE F

ROUNDED

1'--_L1-t_-.llLl1',SlOE

ROUNDED SIDE OF TRANSISTOR AND ADHESIVE TAPE VISIBLE

8r~~~61~SGE8~~~~l~16~.~CX~~~ ~p:N~b ~Z6 w~I~~im OF

FLAT SIDE OF TRANSISTOR AND CARRIER STRIP VISIBLE
(ADHESIVE TAPE ON REVERSE SIDE)

STYLE C

ROUNDED SIDE Of TRANSISTOR AND CARRIER STRIP VISIBLE
(ADHESIVE TAPE ON REVERSE SIDE)

THE BOX THE DEVICES ARE FEO FROM.

STYLE G

STYLEM
FlAT SlOE
FEEO

FEED

ROUNDED
SIDE

ROUNDED SIDE OF TRANSISTOR AND ADHESIVE TAPE VISIBLE

FLAT SIDE

/

~~~~~~~~~~AOHESIVETAPE

....:.:.:::::

~

CARRIER STRIP

FLAT SIDE OF TRANSISTOR AND ADHESIVE TAPE VISIBLE

FLAT SIDE OrTRANSISTOR AND ADHESIVE TAPE V1SIB!.~

FLAT SIDE Of TRANSISTOR AND CARRIER STRIP VISIBLE
(ADHESIVE TAPE ON REVERSE SIDE)

ROUNDED SIDE OF TRANSISTOR AND CARRIER STRIP VISIBLE
(ADHESIVE TAPE ON REVERSE SIDE)

13-6

STYLE M AMMO PACK IS EQUIVALENT TO STYLES E, F, G, HOF REEL PACK
DEPENDING ON WHICH BOX·FLAP IS OPENED AND WHICH END OF
THE BOX THE DEVICES ARE FED FROM.

Alphanumeric Index and Ordering Information
Company Profile
Application Notes
Static Handling Procedures and Quality Assurance
Process Flow
DMOS Product Family
N- and p. Channel Low Threshold MOSFETs
DMOS Discretes N-Channel
DMOS Discretes P-Channel
DMOS Arrays and Special Functions
HVCMOS High Voltage ICs
CMOS Consumer/Industrial Products
Lead Bend Options and Surface Mount Packages
Package Outlines
Representatives/Distributors

.....
--;
....
....
..
~"

'

'III

....
-•
...
t.L

"

!iupertex inc.
Package Outlines

,

®"'~.==='=:::;:;=====~
@.450+,030

r

2 MOUNTING HOLES

O.lS6±.0059

@

TO·3 Metal Can Packages
2·Lead (Sleel)

-t-----"ifiT'ii"~
1·Source
2·Gate
3·Drain

L·~~J' ~'l''.::'"0"'0
LEAP PIA

(f)

f~~ @

.J ~ I

1

.100!.OCIS(!)

1-Source
2·Gate
3-Drain

Note: Excludes parts with 'R' prefix.

To-39 Melal Can Package
3·Lead
Note:

Circle (i.e.,

TO·92 Plastic Package
3·Lead

®) indicates JEDEC Reference.
14·1

.OI5!.005

BEF~:E

@ .oso ;!:..

LEAD FINISli

..

@
.215 ± .005

8
t'B5:.~

---r

I

t

1-5
2-G
3-D

TO·52 Metal Can Package
3·Lead

®
@

I

,151±..002

F

.180±.005

@

.05Q:t.003

®

.----1--

®

fl======l
8

1,150±.010

=Ff"i':'iF'T,:;=d

SEATING

PLANE
I

.340t.010

i
225t 025

@

~

C9

.540±.OlS

L

'-G
'-5

"2-D

.015

C9

050:1:003

100t010

®

®

200± 010

TO·220 Power Package
3·Lead
Note:

Circle (i.e.,

®) indicates JEDEC Reference.
14·2

~~'o~-t

~

I
L

8

14

P

®.290±.008

7

1
~

~

~

~

~

~

~

f-----@

f
® .135±.Oro

~

t

f

@.035±.010

©.150±.015

t
G).100

J

L®.018±.002

L

® .300±.010

J

14·Lead Ceramic Side Brazed Package

I

®.295±.008

L

9

16

D
8

1

JL

JL

® .050±.003

®.050±.003

@.800±.008

t

~

@.130±.010

f

f

@.035±.010

©.150±.015

!

JL

G).lOO

®.018±.002

l6·Lead Ceramic Side·Brazed Package
Note:

Circle (i.e.,@) indicate. JEDEC Reterence.

14·3

TI
©.01O:'::.~~~ - - I.-

L J
@ .300±.010

-

I

r

10

18

D

®.295±.008

L

9

1

JL®

J

.050±.003

t--------@.900±.010

L®.050±.003

---------1

-.--1

t

@.035±.010

6).100

jL

®.018±.002

18-Lead Ceramic Side-Brazed Package

·r

®.290•. 00B

L

20

11

1

10

)

JL

® .050±.003

~-------- @1.000±.010

L®.050±.003

---------+1

©.010~.~~~
@.035±.010

j~
2O-Lead Ceramic Side-Brazed Package
Note: Circle (I.e., @) Indicates JEDEC Reference.

14-4

®.018±.002

~~

'I

L..J

~,''''''''i

t

@.ID.01.

!

24-Lead Ceramic Side-Brazad Package

II

JL

O_·IID

1----------

..

@,._.o,.
L...J

©.O'O~·.1m

L
211-Lead Caramlc Side-Brazed Package
Note: Circle (i.e .. ®) indicates JEDEC Reference.

14-5

-

I--

c .""'.0'0 - - - - I

..

"

,

..

~

I

'I

@,--

'~

r

@.145"!:..010

I I

(0.15O±.015

~

"

~

40-Lead Ceramic Side-Brazed Package

Note:

Circle (i.e.,

®) indicates JEDEC Reference.
14-6

---.l

~.010

I

0

1
©O":~T

L---@_o,.~

I

®

14

.248:t .003

L

'-.---.---.---,~~

JL

L®.080:t· .005

@).060±.005

@.760±.007

~

t

@mo

~~

. ©.010±.002

®.o18±.002

14-Lead CERDIP Package

®

1

'6

.288

L~1~-.---.--.--,---~

j L

JL

@) .060±.005
@.760±.007

®mo :':. .005

--------1

-=-r

@.020

(9.150±.015

*
~.100

~~

tt=O'~I

Note:

Circle (i.e.,

®) indicates SEMI-STANDARD Gl.l STD. 1.
14-7

(9.010±.002

V

®.018±.002

16·Lead CERDIP Package

..

Ij

~

"'", El

.310:':. .010

~

J

I
L,

10

'S

® .268:t. .003

~c=r=~=r==c=r==c=r~

~ L®.04S:':.

L

(§ .060±.005

.005

1+-----@.S90±.00S--------I°1

--L

--r

@.020

(S).100

j

L

®.01S±.002

18·Lead CERDIP Package

@uE[ ~ ~ ~~~ ~ ~ ~:I
JL

® .060±.00SJ

1----- @

.950

® .025 !. .005

± .010 - - - - - - I

j

L

20·Lead CERDIP Package
Note:

l-

Circle (i.e .• @) indicates SEMI-STANDARD Gl.l STD.l.

14-8

@018±.002

0

@.010±.002

f

U

1------

@1.2000.010-----I

24-Lead CERDIP Package

r'

@-!-

15

)

L~=-=-=--=--=-=-<~"
~ ~ ~_a
-J l-®'~5'1------@1.4"".OIO-----I'1

~

JL ~
@.Ot ...

2B-Lead ,CERDIP Package
Note:

Circle (i.e.,

®) indicates SEMI·STANDARD G!.! STD.!.
14-9

@L

~
II =1"
./[1 @.Ot~_
'-OI~ @"IIUII~

+

-----r
.

nn'nnnnnn

e.050:.012

mDDODDD

•

21~

01

-H- - - - - - + - - -

.52.0! .006

~~~~20~

[o,,~oo,
@

+-~~~~~~-~·"f;."'i~~"~.100
TYP.

40·Lead CERDIP Package

t

®

.16S±.OOS

©

.l"30±.01S

,
+

JL®

.. = 0.lS0

.0l8±.002

14-Lead Plastic Dual·ln·Llne Packaga
Note:

Circle (I.e .• @ ) indicates JEDEC Reference.

14-10

~

~®l310±'010J

®,[[: : : : : : : :
L®l

j
I

1-----

--J

.060! .005

@

I

L

® .025 !. .005

.750±.010

16·Lead Plastic Dual-ln·Line Package

®'L(-l:L-:::: ::--ll:I
®l.oso

® .035 !. .005

-=--==",

.----=~~_®._870

----1
t

@.020

JL

®.018±.003

18·Leed Plastic Dual·ln·Llna Package
Note:

Circle (Le.,

@) indicates JEDEC Reterenca.

14·11

@.010±.001--tf--

"'0'~@j)'310±'OlO j

®EJ::::::::::I
J lJ L
®

.0116

® .065 ±. .005

± .006

.
r
r-.rr--:---------,

---@I.030±.OfO------i

@

~

.170:!: .006

t

@

(0. 150±.015

+

~~

t

©

.020:!: .006
"=0·15'

®.OI8±.003

~

.010

~~

~.:

.310±,010J

20-Lead Plastic Dual-In-Llne Package

I------@

@

'.210 t .D'O

-.,------1

"_,t_

~ "T t 1 - - - \9 .61Ot.Ol0

24-Lead Plastic Dual-In-Llne Package
Note: Circle (i.e., ® ) indicates JEDEC Reference.

14-12

--J

\

1---------

@1.47. - - - - - - - - -

@.I&.U'..

t

211-Lead Plastic Dual-In-Llne Package

®

1---------- 2.050!,020-------~1

J

.062 R.

.~&8

t

.010

~=r=FFFFFFF"FT~~~
j [o~cpoo.

~
TYP,

40-Lead Plastic DIP
Note:

Circle (i.e.,@) Indicates JEDEC Reference.

14-13

-

28-Lead Plastic Quad
"J" Bend

20-Lead SOW Package

Note:

Circle (i.e.,

®) indicates JEDEC Reference.
14-14

r
'~1r
±.ooe
.010

GOLD PLATING

BASE
BLACK CE RAMie

EPOXY
SEAL

16 Terminal C/C Package

350':'

008

300':' ,DOS

. aff.,.,•
f

sa
so.

. 070

@

~

.007

0

.016 min
4· PLC'S

20

4

5

6

.,

.028 TVP,'

8
,040

II

46° CHAMFER

3· PLC'S REF ..

o

"c" Leadless
Type I Chip Carrier
2O·Termlna

Note:

Circle (I.e.,
.

® )indicates JEDEC Reference.
14·15

... 1 TERMINAL

.105

r ~.::

.400 sq.

36-Leaded CtC
Bend Option "CR"

1I1--

.010

t

.003

TYP.

36·Leaded CtC
Bend Option "CF"

Note:

Circle (i.e .• @) indicates JEDEC Reference.

14-16

.11,.

1

1--.010

I

t

j! 'O'0r-

.003
.010

TYP.

In

1 ° 3 2 ±.O03

r~
.375 sq.

L
36-Leaded CtC
Bend Option "CS"

iiiiiiii
"CF"

"CS"

"CR"

..
1

36-Leaded CtC Bend Options
(For detail dimensions refer to package outlines)

Note: Circle (i.e .• @) indicates JEDEC Reference.

14-17

CE=

+'017=sJ

1.150 sq. _ .012
•710 _

C·
I

072

mill.

:! ....

.DIG :'001

PIn 1

+

------+---'*--1.(110 Jq. .:t .010

" ....

~ ~ ~.
.050

! .006

84-Terminal Ceramic CtC

Typs"B"

f - - - - - - - - - - - 1 . 1 9 0 · .005 _ _ _ _ _ _ _ _ _ _---1

1

{""'' "'"

r-

.008 :t .0003

,050:': .001 Be

+-------

----&

1.120 LOOS
Be OF BEND RADII

1.190±.005

.450-----\

-J 1-028 ••002

.021

! - - - - - - - - - - - 1 . 1 5 0 ~:~----------...;.I

.104

t

84·LeacI Quad Plaatle Chip Carrier
Note: Circle (i .•.• ®) indicates JEDEC Reference.

14-18

.010

ll

"':O::, h
'.00'

CONTACT SURFACES TO BE
CO-PLANAR YlITHIH!.ooa

I~'I

~

'-I

LEAO'" I

.640 ~-~
=OO!l

.!lSO!' .006

"

J
.Ol3t.006

44-Lead Quad CERPAC "OJ" Package

""'OO'-j
....

41

I
- - : - - - 1- - - - r

~~~~~Ull~~~~~~uw~

~~~------------+----------~~~

JL-...
1 0 - - - - - -_ _ _

CONTACT SURFACES TO 8E
CO-PLANAR WlmN

I.OI4±mo

-------~

SCALe:- lOX

SO-Lead Quad CERPAC "OG" Package
Note:

Circle (i.e., ®) indicates SEMI-STANDARD Gt. t STD.!.

14-19

!

.002

I
PIN No. I IDENT.I

+

I

44·Lead Plastic "J" • Bend

eO-lead Quad Plastic "PG" Package
Note: Circle (i ..
e , @ ) Indicates
.
JEDEC Reference.

14-20

Alphanumeric Index and Ordering Information

~\

Company Profile

. .'

Application Notes

"i

Static Handling Procedures and Quality Assurance

. .'

Process Flow

..

DMOS Product Family

..

N- and p. Channel Low Threshold MOSFETs

..

DMOS Discretes N-Channel

..

DMOS Discretes P-Channel

..

DMOS Arrays and Special Functions

..

HVCMOS High Voltage ICs

'III

CMOS Consumer/Industrial Products

~"

Lead Bend Options and Surface Mount Packages

_

Package Outlines

_
,
I

Representatives/Distributors

~

DISTRIBUTORS

INDIANA

ARIZONA

RM ELECTRONICS CO., INC.
(317) 291-7110

MILGRAY ELECTRONICS Rochester
(716) 235-0830

KANSAS

OHIO

MILGRAY ELECTRONICS
(913) 236-8800

SCHUSTER ELECTRONICS
(513) 489-1400
(216) 425-8134

MARYLAND

MILGRAY ELECTRONICS
(216) 447-1520
(800) 321-0006
(800) 362-2808

ARIZONA COMPONENT CO.
(602) 269-5655

CALIFORNIA (NORTH)
ALL AMERICAN TRANSISTOR
(408) 287-0190
IEC
(916) 424-5297
IEC
(408) 435-1000

CALIFORNIA (SOUTH)
ALL AMERICAN TRANSISTOR
(213) 320-0240
ELMO
(818) 768-7400
ZEUS WEST
(714) 632-6880
DISTRIBUTED MICROTECHNOLOGY
(714) 921-1830
IEC
(714) 837-9960
NEUMANN ELECTRONICS
(619) 695-3005

MILGRAY ELECTRONICSBaltimore
(301) 995-6169
MILGRAY ELECTRONICS Columbia
(301) 621-8169
(800) 638-6656

SHELLEY-RAGON
(503) 641-1691

MASSACHUSETTS

IEC
(503) 641-1690

J.V. ELECTRONICS OF
BOSTON
(617) 657-6523

TEXAS

OREGON

ZEUS CONPONENTS
(617) 863-8800

RM ELECTRONICS CO., INC.
(214) 263-8361
(214) 869-2080

NU HORIZONS
(617) 777-8800

ZEUS COMPONENTS
(214) 783-7010

SALEM SCIENTIFIC
(617) 927-5820

MILGRAY ELECTRONICS
(214) 248-1603
(800) 441-9078

MILGRAY ELECTRONICS
(617) 657-5900

UTAH

CANADA

IEC
(801) 298-1869

MILGRAY ELECTRONICSToronto
(416) 756-4481

MICHIGAN

COLORADO

MINNESOTA

IEC
(303) 292-6121

ALL AMERICAN TRANSISTOR
(612) 884-2220

WASHINGTON
IEC
(206) 455-2727

RM ELECTRONICS
(616) 531-9300

CONNECTICUT

NEW JERSEY

MILGRAY ELECTRONICS
(203) 878-5538

NU HORIZONS
(201) 882-8300

FLORIDA

MILGRAY ELECTRONICS
(609) 983-5010
(800) 257-7111

ALL AMERICAN TRANSISTOR
(305) 621-8282
ZEUS COMPONENTS
(305) 365-3000
MILGRAY ELECTRONICS
(305) 647-5747
(800) 432-0645

MILGRAY ELECTRONICS
(801) 272-4999

NEW MEXICO
ELECTRONIC DEVICES CO.,
INC.
(505) 884-2950

RM ELECTRONICS CO., INC.
(312) 364-6622

NU HORIZONS
(516) 226-6000

IEC
(312) 843-2040

ZEUS ELECTRONICS
(914) 937-7400

MILGRAY ELECTRONICS
(312) 350-0490

MILGRAY ELECTRONICS Farmingdale
(516) 391-3000
(800) MILGRAY

CALIFORNIA (NORTH)
CUSTOM TECHNOLOGY
SALES
514 Valley Way
Milpitas, CA 95035
(408) 263-3660 - 3664

CALIFORNIA (SOUTH)
ORION-ECLIPSE SALES, INC.
828 E. Colorado Blvd., Suite F
Glendale, CA 91205
(818) 240-3151
FAX: (818) 240-3181
ORION-ECLIPSE SALES, INC.
6905 Oslo Circle, Suite B1
Buena Park, CA 90621
(714) 522-6310
FAX: (714) 522-6312

CALIFORNIA
(SAN DIEGO)
EARLE ASSOCIATES
7585 Ronson Road, Suite 200
San Diego, CA 92111
(619) 278-5441
TLX: 314285 EARLE SDG
FAX: (619) 278-5443

R.N. LONGMAN SALES Mississauga
1715 Meyerside Drive, Unit 1
Mississauga, Ontario
Canada L5T 1C5
(416) 670-8100
FAX: (416) 670-1384
TWX: 610-422-3028

NEW YORK

ILLINOIS

ARIZONA
SMS & ASSOCIATES
7807 E. Greenway Road, Suite 8
Scottsdale, AZ 85260
(602) 998-0831

R.N. LONGMAN SALES Kirkland
168 Hymus Blvd.
Kirkland, Quebec
Canada H9H 3L4
(514) 694-3911
TWX: 610-422-3028

GCI CORP.
(509) 768-6767

ADD ELECTRONICS
(716) 924-4760
(800) 962-2200
(315) 437-0300

MACRO MARKETING
11513 S. Memorial Pkwy
Huntsville, AL 35803
(205) 883-9630
TWX: 810-726-2230

CANADA

GEORGIA
MILGRAY ELECTRONICS
(404) 446-9777
(800) 241-5523

SHELLEY-RAGON
(206) 883-2220

REPRESENTA TlVES
ALABAMA

R.N. LONGMAN SALES Coquitiam
310-218 Blue Mountain Street
Coquitlam, B.C.
Canada V3K 4H2
FAX: (604) 273-5477

15-1

_i_I

COLORADO

MARYLAND

OHIO

VIRGINIA

FRONT RANGE MARKETING
3100 Arapahoe, Road
Suite 404
Boulder, CO 80303
(303) 443-4780
FAX: (303) 497-0371

ROBERT ELECTRONIC SALES
5525 Twin Knolls Road
Suite 325
Columbia, MD 21045
(301) 995-1900

OMEGA SALES INC.
240 W. Elmwood Dr.,
Suite 20165
Centerville, OH 45459
(513) 434-5507
FAX: (513) 434-5772

DELTA III ASSOCIATES
12616 E. Hampton Drive
Midlothian, VA 23113
(804) 379-1816

WASHINGTON

MILL-BERN ASSOCIATES
2 Mack Road
Woburn, MA 01801
(617) 932-2311
FAX: (617) 932-9594

OMEGA SALES, INC.
20475 Farnsleigh Rd., Suite 106
Shaker Heights, OH 44122
(216) 751-9600
FAX: (216) 751-7430

ELECTRONIC COMPONENT
SALES
9311 S.E. 36TH
Mercer Island, WA 98040
(206) 232-9301
FAX: (206) 232-1095

MICHIGAN

OREGON

WISCONSIN

ARETE SALES
2260 Lake Avenue
Ft. Wayne, IN 46805
(219) 423-1478

ELECTRONIC COMPONENT
SALES
15255 SW 72ND Avenue,
Suite C
Tigard, OR 97224
(503) 245-2342
FAX: (503) 684-6436

JANUS, INC.
W239 N 1690 Busse Road
Suite 203
Waukesha, WI 53188
(414) 542-7575
FAX: (414) 542-7634

MASSACHUSETTS
CONNECTICUT
ED GLASS ASSOCIATES
120 Sylvan Drive, Suite 2
Englewood Cliffs, NJ 07632
(201) 592-0200
FAX: (201) 592-0488

FLORIDA
DYNE-A-MARK CORP.
1001 NW 62nd Street, Suite 180
FI. Lauderdale, FL 33309
(305) 771-6501
TWX: 510-956-9872
DYNE-A-MARK CORP.
573 S. Duncan Avenue
Clearwater, FL 33515
(813) 441-4702
TWX: 810-866-0438
DYNE-A-MARK CORP.
500 E. Semoran Blvd., Suite 15A
Casselberry, FL 32707
(305) 831-2822
FAX: (305) 834-4524

GEORGIA
MACRO MARKETING
3040 Holcomb Bridge Road
Suite J-2
Norcross, GA 30071
(404) 662-5580

ILLINOIS
JANUS CORP.
650 E. Devon Avenue
Itasca, IL 60143
(312) 250-9650
FAX: (312) 250-8761

INDIANA

MINNESOTA
SMILEY-SCOn ASSOCIATES
9001 E. Bloomington Frwy,
Suite 118
Bloomington, MN 55420
(612) 888-5551
FAX: (612) 888-9754

MISSOURI
BC ELECTRONICS
500 Airport Road
SI. Louis, MO 63135
(314) 521-6683
TWX: 910-762-0600

NEW YORK
GEN-TECH ELECTRONIC
SALES
4855 Executive Drive
Liverpool, NY 13088
(315) 451-3480
GEN-TECH ELECTRONIC
SALES
(SOUTHERN TIER)
5 Arbutus MR 97
Binghampton, NY 13901
(607) 648-8833

ARETE SALES
918 Fry Road, Suite B
GreenWOOd, IN 46142
(317) 882-4407
FAX: (317) 888-8416

ED GLASS ASSOCIATES
120 Syian Drive, Suite 2
Englewood Cliffs, NJ 07632
(201) 592-0200

ARETE SALES
2260 Lake Avenue
FI. Wayne, IN 46805
(219) 423-1478
FAX: (219) 240-1440

NEW JERSEY (NORTH)
ED GLASS ASSOCIATES
120 Sylvan Drive, Suite 2
Englewood Cliffs, NJ 07632
(201) 592-0200

KANSAS

NEW JERSEY (SOUTH)

BC ELECTRONICS
1140 Adams
Kansas City, KS 66103
(913) 342-1211
TWX: 910-749-6414
BC ELECTRONICS
2421 Yellowstone
Witch ita, KS 67215
(316) 722-0104
TWX: 910-741-6804

PENNSYLVANIA
(WESTERN)
OMEGA SALES, INC.
2431 Milton Road
University Heights, OH 44118
(216) 318-1404

PENNSYLVANIA
(EASTERN)
DELTA TECHNICAL SALES,
INC.
Willow Wood Office Center
3901 Commerce Avenue,
Suite 180
Willow Grove, PA 19090
(215) 657-7250
TWX: 510-601-1858

TEXAS
T.L. MARKETING
12200 Stem mons Frwy
Suite 317
Dallas, TX 75234
(214) 484-6800
TWX: 910-861-4149
FAX: (214) 241~9315
T.L. MARKETING
7745 Chevy Chase Drive
Suite 360
Austin, TX 78752
(512) 453-4586
T.L. MARKETING
810 Hwy 6 #120
Houston, TX 77079
(713) 589-2763

DELTA TECHNICAL SALES,
INC.
Willow Wood Office Center
3901 Commerce Avenue,
Suite 180
Willow Grove, PA 19090
(215) 657-7250
TWX: 510-601-1858

UTAH
FRONT RANGE MARKETING
7050 Union Park Center
Suite 440
Midvale, UT
(801) 566-2500
FAX: (801) 566-2951

15-2

INTERNA TlONAL
AUSTRALIA/
NEW ZEALAND
SOANAR ELECTRONICS
TEL: 038950222
TLX: 790-34303
FAX: (038) 907198

AUSTRIA
ING. E. STEINER
TEL: (0222) 82-74-74-0
TLX: 135026.EAS

BELGIUM
RODELCO NV ELECTRONICS
TEL: 02 7205013
TLX: 61415 RODL B
FAX: 02 7202048

DENMARK
C-88 AS
TEL: (1) 244888
TLX: 41198
FAX: (1) 244889

FINLAND
TURION OY
TEL: 90 372 144
TLX: 124388 TURIO SF

FRANCE
A2M
TEL: (1) 39549113
TLX: 698376
INTERNATIONAL SEMICONDUCTOR
TEL: 33 1 45 06 42 75
TLX: 614596 Attn: I.C.S.
FAX: 1 45064699
ASAP
TEL: 3 043 8233
TLX: 842698887
FAX: (1) 30570719

HONG KONG

SPAIN

A & N ENTERPRISES
TEL: 5 461179
TLX: 65218 MCLWW HX
LEADERTRONICS CO.
TEL: 3 890384/3 890385
TLX: 32581 LADTC HX
FAX: 3 7978429

AMITRON, SA
TEL: 1 241 5402
TLX: 45 550 AMIT E
FAX: 1 248 79 58

INDIA
SARAS ELECTRONIC
TEL: 044 3249
TLX: 041-6937 PCOA IN

ISRAEL
E.I.M. INTERNATIONAL
ELECTRONIC
TEL: 03 9233257
TLX: 922 381144 ElM IL
FAX: 03 9244857

ITALY
SILVERSTAR
TEL: 024996
TLX: 332189 SIL
FAX: 2435594

JAPAN
MICROTEK, INC.
TEL: 03363231
TLX: 781 27466
FAX: 03 3695623
SYSTEMS MARKETING
TEL: 03-254-2751
TLX: 781-222 5276
FAX: 03 254 3288

KOREA
YEONIL CO., LTD
TEL: 02 244 7492 1
0224707067
TLX: K241123 YEONIL
LEADERTRONICS KOREA CO.
TEL: 02 548 094
TEL: 02 548 0943
TLX: K32502 HOJIN
FAX: 02 540-0608

NETHERLANDS
RODELCO B.V.
ELECTRONICS
TEL: 076 784911
TLX: 54195 RODL NL
FAX: 076 710029

SWEDEN
INTEGRERAD ELEKTRONIK
KOMPONENTAR AB
TEL: 08 80 4685
TLX: 812 5126 INTEL

SWITZERLAND
EGLI FISCHER
TEL: 01 20981 11
TLX:53762
FAX: 201 22 75

TAIWAN
COMMAX TECHNOLOGIES,
INC.
TEL: 02 772 7205
TLX: 888816 CT ENT
FAX: 02 752 2088
SPIROX TAIWAN LTD.
TEL: 02 565 2878
FAX: 02 511 8255

UNITED KINGDON
KUDOS ELECTRONICS LTD
TEL: 0734 351010
TLX:847575
FAX: 0734 351030

WEST GERMANY
INFRATECH
TEL: 04 08 17 578
TLX: 841213513
SCANTEC
TEL: 89134093
TLX: 841 5213219
TOPAS ELECTRONIC GMBM
TEL: 0511 345691
TLX: 9218176
SCANTEC GMBH
TEL: 07021 54027
TLX: 7267486
FAX: 7021 82568
MILGRAY ELECTRONICS
GMBH
TEL:07161 73054 8
TLX: 727269 MILO
FAX: 07161 76855

NORWAY
E.B. NORTELCO
TEL: 47 2 64 90 50
TLX: 76743 TELCO N
FAX: 47 2 64 74 00

SINGAPORE
SEAMAX ENGINEERING
PRIVATE LTD
TEL: 7476155
TLX: RS 51147 SEAMA
FAX: 65 7447653

15-3

SALES OFFICES
Eastern U.S. - Supertex, Inc.
120 Sylvan Avenue, Suite 3
Englewood Cliffs, NJ 07632
(201) 947-3844 FAX : (201) 947-2802

Central U.S. - Supertex, Inc.
7608 Fox River Court
Fort Worth, TX 76112
(817) 457-5677 FAX: (817) 457-9269

Western U.S. - Supertex , Inc.
22726 Islamare
EI Taro, CA 92630
(714) 533-0481 FAX: (714) 837-1564

§upertex inc.
Leadership in CMOSI OMOS Technologies
1225 Bordeaux Drive • Sunnyvale, California 94088-3607
TEL: (408) 744-0100· TLX: 6839143 SUPTX· FAX: (408) 734-5247
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