1988_TI_Programmable_Logic_Data_Book 1988 TI Programmable Logic Data Book

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TEXAS
.
INSTRUMENTS

Progralnlnable Logic

1988

1988

General Information

Data Sheets

Application Reports

Mechanical Data

The Programmable Logic
Data Book

,.,
TEXAS
INSTRUMENTS

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to
discontinue any semiconductor product or service identified in this
publication without notice. TI advises its customers to obtain the latest
version of the relevant information to verify, before placing orders,
that the information being relied upon is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Unless mandated by government
requirements, specific testing of all parameters of each device is not
ne,cessarily performed.
TI assumes no liability for TI applications assistance, customer product
design, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or
relating to any combination, machine, or process in which such
semiconductor products or services might be or are used.

Copyright © 1988, Texas Instruments Incorpor~ted

INTRODUCTION
In this volume, Texas Instruments prflsents technical information on TI's broad line of programmable logic
devices (PlDs), including 10-ns, 20-pin PAl® circuits.
TI's programmable logic products include high-speed leadership circuits, as well as standard 20- and 24-pin
PAL devices in a variety of speed/po/wer versions. This data book includes specifications on existing and
future products, including:
•

High-performance, low-power IMPACT'" and IMPACT-X'" 20- and 24-pin standard PAL
circuits
• High-complexity latched- :and Registered-input PAL ICs and Exclusive-OR arrays
• Flexible, '22V1 O-architectulre macrocell PAL ICs, including TI's enhanced, 20-ns version, the
TIBPAl22VP10-20
• High-speed 6- and 3-ns, 1 OKH and 100K ECl IMPACT'" and ExCl'" PAL circuits
• Ultra-low-power UV-erasalble and one-time programmable CMOS PAL ICs, including 20-pin,
'22V10, and generic architectures
• Fast, 50-MHz programmable state machines, including enhanced versions of '8251 05B/167B
sequencers and the TIBP'SG507 Programmable Sequence Generator
Texas Instruments high-speed programmable. bipolar devices utilize TI's advanced IMPACT'" and new
IMPACT-X'" technologies. IMPACT-X'" uses trench isolation and polysilicon emitters to increase performance
and reduce power dissipation compared to traditional processes. IMPACT-X'" provides 1.5-/Lm feature sizes
and 7-/Lm pitch.
Based on IMPACT-X"', TI's new ECl process, ExCl'" , offers even greater speed and density for highperformance ECl circuits.
This volume contains design and specification data for 78 device types. Package dimensions are given
in the Mechanical Data section in metric measurement (and parenthetically in inches).
Four programmable logic applic,ation reports have been incorporated into this data book as a reference
tool. They are: Designing with To'3xas Instruments Field Programmable Logic; Hard Array Logic; A Designer's
Guide to the PSG507; and Systems Solutions for Static Column Decode.
Complete technical data for any Texas Instruments semiconductor product is available from your nearest
TI field sales office, local auth.mized TI distributor, or by calling Texas Instruments at 1-800-232-3200.

PAL is a registered trademark of Monolithic, Memories Inc.
IMPACT and IMPACT-X are trademarks of Texas Instruments Incorporated.
ExCL is a trademark of Texas Instruments [Incorporated.

v

General Information

1-1

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Contents
Page

Alphanumeric Index .................... ,. . . . . . . . . . . . . . . . . . . . ..
Glossary ..... ~ ................ ; . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Explanation of Function Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Parameter Measurement Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Hardware/Software Manufacturers ...............................
TIIMPACT'" Design and Service Centers ....... ,....................

1-3
1-5
1-9
1-11
1-12
1-13
1-14

ALPHANUMERIC INDEX

Page

Page

PAL16LSAC
PAL 16L8A-2C

PALI6LSAM ............
PAL 16L8A-2M ..........

2-3
2-3

TIBPAL20L 10-30C .......................... 2-127
TIBPAL20SPS-30M ....... 2-139
TIBPAL20SPS-20C

PAL16R4AC

PAL16R4AM . . . . . . . . . . .
PAL 16R4A-2M ..........

2-3

TIBPAL20X4-20C

PAL16R4A-2C
PAL16R6AC
PAL16R6A-2C

PAL16R6AM ...........
PAL16R6A-2M ..........

2-3
2-3

TIBPAL20X4-30C ........................... 2-127
TIBPAL20XS-20C
TIBPAL20XS-25M ........ 2-115

2-3

TIBPAL20X8-30C ........................... 2-127

PAL16RSAC
PAL 16RSA-2C

PAL16R8AM ...........
PAL 16R8A-2M ..........

2-3
2-3

TIBPAL20Xl0-20C
TIBPAL20Xl0-25M ....... 2-115
TIBPAL20Xl0-30C .......................... 2-127

PAL20LSAC

PAL20LSAM ............ 2-15

PAL20R4AC
PAL20R6AC
PAL20RSAC

TIBPAL20X4-25M ........ 2-115

TIBPAL22Vl0C

TIBPAL22Vl0M ......... 2-145

PAL20R4AM . . . . . . . . . . . 2-15

TIBPAL22Vl0AC

PAL20R6AM ........... 2-15
PAL20R8AM ........... 2-15

TIBPAL22VP10-20C

TIBPAL22Vl0AM ........ 2-145
TIBPAL22VP10-25M ...... 2-157
2-169

TIBPALR19L8C

TIBPALR19L8M

TISPADI6NS-7C ............................ 2-27

TIBPALR19R4C

TIBPAD ISNS-6C ............................ 2-35
TIBPAL 16LS-l0C
TIBPALI6L8-12M ........ 2-41

TIBPALR19R6C
T!BPALRI9R8C

TIBPALR19R4M ......... 2-169
2-1S9
TIBPALR 19R5M
TI8PALR19RSM ......... 2-1S9

TIBPAL 16LS-12C

TIBPAL16LS-15M ........ 2-57

TIBPALT19L8C

TIBPAL16LS-15C

TIBPAL 16L8-20M ........ 2-S7

TIBPAL 16L8-25C

TIBPAL 16LS-30M ........ 2-77

TIBPALT19R4C
TIBPALT19RSC

TIBPALT19LBM
TI8PALT19R4M . .....
TIBPALT19R6M

2-1S1
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2-181

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2-1S1

TIBPAL ISR4-1 OC

TIBPAL 16R4-12M ........ 2-41

TIBPALT19R8C

TIBPAL1SR4-12C
TIBPAL 16R4-15C

TIBPAL 16R4-1 5M ........ 2-57
TIBPAL 16R4-20M ........ 2-67

TIBPLS50SC
TIBPSG507C

TIBPALT19RSM . ...... , ' 2-1S1
TIBPLS50SM . .......... 2-193
TIBPSG507M ........... 2-201

TIBPAL 16R4-25C

TIBPAL 16R4-30M ........ 2-77

TIBB2S105BC

TIBB2S105BM . . . . . . . . . . 2-209

TIBPAL ISRS-l OC

TIBPALISRS-12M ........ 2-41

TIBPAL1SRS-12C

TIBPAL ISRS-l 5M ........ 2-57

TIBS2S1S7BM . ......... 2-219
TIBS2S1S7BC
TIC HAL ISLS-35C ........................... 2-229

TIBPAL ISRS-15C

TIBPAL ISRS-20M ........ 2-S7

TIBPAL ISRS-25C

TlBPAL ISRS-30M ........ 2-77

TIBPAL ISRS-l0C
TIBPAL1SR8-12C

TIBPAL ISR8-12M ......
2-41
TIBPAL ISRS-l 5M ........ 2-57

TIBPAL ISRS-15C
TIBPAL ISRS-25C

TIBPAL ISR8-20M ........ 2-S7
TIBPAL1SRS-30M ........ 2-77

TIBPAL20LS-15C

TlBPAL20LS-20M ........ 2-S7

TIBPAL20LS-25C

TlBPAL20LS-30M ........ 2-101

TICPAL ISV8-25C

TIBPAL20R4-15C
TIBPAL20R4-25C

TIBPAL20R4-20M ........ 2-S7
TIBPAL20R4-30M ........ 2-101

TIBPAL20RS-15C

TISPAL20RS-20M ........ 2-S7

TICPAL22Vl0M ......... 2-271
TICPAL22Vl0C
TIEPAL10HI6PS-3C ......................... 2-2S5
TIEPAL 10H1SPS-SC ......................... 2-291

TIBPAL20RS-25C

TIBPAL20RS-30M ........ 2-101

TIEPAL10016P8-3C .... , .................... 2-297

TIBPAL20RS-15C

TIBPAL20RB-20M ........ 2-S7

TlEPAL 10016PS-SC ......................... 2-303

TIBPAL20R8-25C

TIBPAL20R8-30M ........ 2-101

TIFPLA839C

TISPAL20L 10-20C

TIBPAL20L 10-25M ....... 2-115

TIFPLAS40C

TICHAL ISR4-35C ........................... 2-229
TICHAL ISRS-35C ........................... 2-229
TICHAL ISRB-35C ........................... 2-229
TICPAL ISLS-55C ........................... 2-243
TICPAL ISR4-55C ........................... 2-243
TICPAL1SR6-55C ......... '...............•.. 2-243
TICPAL ISRS-55C ........................... 2-243
TICPAL 1BV8-30M . . . . . . 2-257

TEXAS ."

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.

TIFPLAS39M . . . . . . . . . . . 2-309
TIFPLAS40M . .......... 2-309

1-3

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1-4

GLOSSARY

INTRODUCTION
These symbols, terms, and definitions are in accordance with those currently agreed upon by the JEDEC Council
of the Electronic Industries Association (EIA) for use in the USA and by the International Electrotechnical
Commission (lEC) for international use.
PART 1 - GENERAL CONCEPTS AND CLASSIFICATIONS OF CIRCUIT COMPLEXITY
Chip-Enable Input
A control input that when active permits operation of the integrated circuit for input, internal transfer,
manipulation, refreshing, and/or output of data and when inactive causes the integrated circuit to be in
reduced-power standby mode.
NOTE: See "chip-select input."

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Chip-Select Input

Q)

A gating input that when inactive prevents input or output of data to or from an integrated circuit.
NOTE: See "chip-enable input."

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Field-Programmable Logic Array (FPLA)
A user-programmable integrated circuit whose basic logic structure consists of a programmable AND array
and whose outputs feed a programmable OR array.
Gate Equivalent Circuit
A basic unit-of-measure of relative digital-circuit complexity. The number of gate equivalent circuits is that
number of individual logic gates that would have to be interconnected to perform the same function.
Large-Scale Integration (LSI)
A concept whereby a complete major subsystem or system function is fabricated as a single microcircuit.
In this context a major subsystem or system, whether digital or linear, is considered to be one that contains
100 or more equivalent gates or circuitry of similar complexity.
Mask-Programmed Read-Only Memory
A read-only memory in which the data content of each cell is determined during manufacture by the use
of a mask, the data content thereafter being unalterable.
Medium-Scale Integration (MSI)
A concept whereby a complete subsystem or system function is fabricated as a single microcircuit. The
subsystem or system is smaller than for LSI, but whether digital or linear, is considered to be one that
contains 12 or more equivalent gates or circuitry of similar complexity.
Memory Cell
The smallest subdivision of a memory into which a unit of data has been or can be entered, in which it
is or can be stored, and from which it can be retrieved.
Memory Integrated Circuit,
An integrated circuit consisting of memory cells and usually including associated circuits such as those
for address selection, amplifiers, etc.

~

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1-5

GLOSSARY

Output-Enable Input
A gating input that when active permits the integrated circuit to output data and when inactive causes
the integrated circuit output(s) to be at a high impedance (off).

G) Programmable Array Logic (PAL"')
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A user-programmable integrated circuit which utilizes proven fuse link technology to implement logic
functions. Implements sum of products logic by using a programmble AND array whose outputs feed a
fixed OR array.

.

Programmable Read-Only Memory (PROM)
A read-only memory that after being manufactured can have the data content of each memory cell altered

3 once only.
a Random-Access Memory (RAM)
0'
;::,

A memory that permits access to any of its address locations in any desired sequence with similar access
time for each location.
NOTE: The term RAM, as commonly used, denotes a read/write memory.
Read/Write Memory
A memory in which each cell may be selected by applying appropriate electronic input signals and the
stored data may be either (a) sensed at appropriate output terminals, or (b) changed in response to other
similar electronic input signals;
Small-Scale Integration (551)
Integrated circuits of less complexity than medium-scale integration (MSI).
Typical (TYP)
A calculated value representative of the specified parameter at nominal operating conditions (VCC = 5 V,
T A = 25°C), based on the measured value of devices processed, to emulate the process distribution.
Very-Large-Scale Integration (VLSI)
A concept whereby a complete system function is fabricated as a single microcircuit. In this context, a
system, whether digital or linear, is considered to be one that contains 3000 or more gates or circuitry
of similar complexity.
Volatile Memory
A memory the data content of which is lost when power is removed.

PAL is a registered trademark of Monolithic Memories Inc.

1-6

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,

GLOSSARY

PART 2 -

OPERATING CONDITIONS AND CHARACTERISTICS (IN SEQUENCE BY lETTER SYMBOLS)

f max

Maximum clock frequency
The highest rate at which the clock input of a bistable circuit can be driven through its required
sequence while maintaining stable transitions of logic level at the output with input conditions
established that should cause changes of output logic level in accordance with the specification.

ICC

Supply current
The current into* the

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Vee

supply terminal of an integrated circuit.

Supply current, outputs high
The current into* the Vee supply terminal of an integrated circuit when all (or a specified number)
of the outputs are at the high level.

ICCl

Supply current,outputs low
The current into* the Vee supply terminal of an integrated circuit when all (or a specified number)
of the outputs are at the low level.

IIH

High-level input current
The current into * an input when a high-level voltage is applied to that input.

III

low-level input current
The current into * an input when a low-level voltage is applied to that input.

10H

High-level output current
The current into * an output with input conditions applied that, according to the product
specification, will establish a high level at the output.

10l

low-level output current
The current into * an output with input conditions applied that, according to the product
specification, will establish a low level at the output.

lOS (10)

Short-circuit output current
The current into * an output when that output is short-circuited to ground (or other specified
potential) with input conditions applied to establish the output logic level farthest from ground
potential (or other specified potential).

10ZH

Off-state (high-impedance-state) output current (of a three-state output) with high-level voltage
applied
The current flowing into * an output having three-state capability with input conditions established
that, according to the production specification, will establish the high-impedance state at the output
and with a high-level voltage applied to the output.
NOTE: This parameter is measured with other input conditions established that would cause the
output to be at a low level if it were enabled.

IOZl

Off-state (high-impedance-state) output current (of a three-state output) with low-level voltage
applied
The current flowing into* an output having three-state capability with input conditions established
that, according to the product specification, will establish the high-impedance state at the output
and with a low-level voltage applied to the output.
NOTE: This parameter is measured with other input conditions established that would cause the
output to be at a high level if it were enabled.

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*Current out of a terminal is given as a negative value.

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1-7

GLOSSARY

High-level input voltage
An input voltage within the more positive (less negative) of the two ranges of values used to
represent the binary variables.
NOTE: A minimum is specified that is the least-positive value of high-level input voltage for which
operation of the logic element within specification limits is guaranteed.
Input clamp voltage
An input voltage in a region of relatively low differential resistance that serves to limit the input voltage
swing.
Low-level input voltage
An input voltage level within the less positive (more negative) of the two ranges of values used to
represent the binary variables.
NOTE: A minimum is specified that is the most-positive value of low-level input voltage for which
operation of the logic element within specification limits is guaranteed.
High-level output voltage
The voltage at an output terminal with input conditions applied that, according to the product
specification, will establish a high level at the output.
VOL

Low-level output voltage
The voltage at an output terminal with input conditions applied that, according to the product
specification, will establish a low level at the output.

ta

Access time
The time interval between the application of a specific input pulse and the availability of valid signals
at an output.

tdis

Disable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms,
with the three-state output changing from either of the defined active levels (high or low) to a highimpedance (off) state. (tdis = tpHZ or tPLZ).

ten

Enable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms,
with the three-state output changing from a high-impedance (off) state to either of the defined active
levels (high or low). (ten = tpZH or tPzLl.

th

Hold time
The time interval during which a signal is retained at a specified input terminal after an active transition
occurs at another specified input terminal.
NOTES: 1 . The hold time is the actual time interval between two signal events and is determined by
the system in which the digital circuit operates. A minimum value is specified that is the
shortest interval for which correct operation of the digital circuit is guaranteed.
2 . The hold time may have a negative value in which case the minimum limit defines the longest
interval (between the release of the signal and the active transition) for which correct
operation of the digital circuit is guaranteed.

tpd

1-8

Propagation delay time
The time between the specified reference points on the input and output voltage waveforms with
the output changing from one defined level (high or low) to the other defined level. (tpd = tpHL or
tpLH)·

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GLOSSARY

Propagation delay time. high-to-Iow level output
The time between the specified reference points on the input and output voltage waveforms with
the output changing from the defined high level to the defined low level.
Disable time (of a three-state output) from high level
The time interval between the specified reference points on the input and the output voltage waveforms
with the three-state output changing from the defined high level to a high-impedance (off) state.
Propagation delay time. low-to-high-Ievel output
The time between the specified reference points on the input and output voltage waveforms with
the output changing from the defined low level to the defined high level.
Disable time (of a three-state output) from low level
The time interval between the specified reference points on the input and output voltage waveforms
with the three-state output changing from the defined low level to a high-impedance (off) state.
tPZH

Enable time (of a three-state output) to high level
The time interval between the specified reference points on the input and output voltage waveforms
with the three-state output changing from a high-impedance (off) state to the defined high level.

tpZL

Enable time (of a three-state output) to low level
The time interval between the specified reference points on the input and output voltage waveforms
with the three-state output changing from a high-impedance (off) state to the defined low level.

tsr

Sense recovery time
The time interval needed to switch a memory from a write mode to a read mode and to obtain valid
data Signals at the output.

tsu

Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent
active transition at another specified input terminal.
NOTES: 1 . The setup time is the actual time interval between two signal events and is determined
by the system in which the digital circuit operates. A minimum value is specified that is
the shortest interval for which correct operation of the digital circuit is guaranteed.

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2. The setup time may have a negative value in which case the minimum limit defines the
longest interval (between the active transition and the application of the other signal) for
which correct operation of the digital circuit is guaranteed.
tw

Pulse duration (width)
The time interval between specified reference points on the leading and trailing edges of the pulse
waveform.

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1-9

EXPLANATION OF FUNCTION TABLES

The following symbols are used in function tables on TI data sheets.

H

G)
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high level (steady state)

L

low level (steady state)

t

transition from low to high level

~

transition from high to low level
value/level or resulting value/level is routed, to indicated destination

~

CD

fl
x

z

value/level is reentered
irrelevant (any input, including transitions)
off (high impedance) state of a 3-state output

0

a ... h

...o·3

Qo

the level of Q before the indicated steady-state input conditions were established

00

complement of QO or level of
established

ell
~

Qn

the level of steady-state inputs A through H respectively
before the indicated steady-state input conditions were

level of Q before the most recent active transition indicated by

JL

one high-level pulse

1.....f

one low-level pulse

TOGGLE

0

~

or t

each output changes to the complement of its previous level on each transition indicated by
~ or t.

If, in the input columns, a row contains only the symbols H, L, and/or X, this means the indicated output is
valid whenever the input configuration is achieved and regardless of the sequence in which it is achieved. The
output persists so long as the input configuration is maintained.
If, in the input columns, a row contains H, L, and/or X together with i and/or t this means the output is valid
whenever the input configuration is achieved but the transition(s) must occur following the achievement of
the steady-state levels. If the output is shown as a level (H, L, QO, or 00), it persists so long as the steady-state
input levels and the levels that terminate indicated transitions are maintained. Unless otherwise indicated, input
transitions in the opposite direction to those shown have no effect at the output. (If the output is shown as
r-L or l..S ,the pulse follows the indicated input transition and persists for an interval
a pulse,
dependent on the circuit.)

1-10

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SERIES TIBPAL', PAL', TlFPLA DEVICES

PARAMETER MEASUREMENT INFORMATION

7V

FROM OUTPUT
UNDER TEST

q

CL

~

VCC
TEST
POINT

FROM OUTPUT
UNDER TEST

RL

L

~

c

R1
FROM OUTPUT -0
3

PI
...

1 20 19

4

18

5

17

6

16

8

14

15

I/O
I/O
I/O
I/O
I/O

...
CO
CO

C

9 1011 12 13

-0

z

-og

(!)

The Half-Power versions offer a choice of
operating frequency, switching speeds, and
power dissipation. In many cases, these HalfPower devices can result in significant power
reduction from an overall system level.
The PAL16' M series is characterized for
operation over the full military temperature range
of - 55 °e to 125 oe. The PAL 16' e series is
characterized for operation from Doe to 70 ae.

t Integrated Schottky-Barrier diode-clamped transistor is patented
by Texas Instruments. U.S. Patent Number 3.463.975.

PAL is a registered trademark of Monolithic Memories Inc.

PRODUCTION DATA documonts contain inlormation
currant IS Df publication data. Prallueta conform to

spacificlltions par the terms of Taxas Instruments

:'=:=i~·i~~~7i ~:~:~:; :.r::::£::~1 not

Copyright @ 1984, Texas Instruments Incorporated

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2·3

PAL 16R4A. PAL 16R4A·2. PAL 16R6A. PAL 16R6A·2. PAL 16RBA. PAL 16RBA·2
STANDARD HIGH·SPEED PAL@ CIRCUITS

PAL1SR4'
M SUFFIX •.. J PACKAGE
C SUFFIX ... J OR N PACKAGE

PAL1SR4'
M SUFFix. , • FH OR FK PACKAGE
C SUFFIX .•• FN PACKAGE

, (TOPVIEWI

(TOP VIEWI

eLK

><: u

Vee

uo
__ -.l
u>::;,

liD
liD

3

2

1 2019

Q
Q
Q

I

18

1/0

5

17

6

16

Q
Q

15

Q

14

Q

Q

I/O
liD

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C

I»
1'+
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(J)

:::T
CD
CD

GND

9 1011 1213

BE
'-l..._---'r'

-

M SUFFIX ..• J PACKAGE
C SUFFIX ... J OR N PACKAGE

PAL16R6'

PAL1SRS'
M SUFFIX .•. FH OR FK PACKAGE
C SUFFIX, .• FN PACKAGE

(TOP VIEWI

(TOPVIEWI

eLK

Vee

~o
__ ~
u>::;,

liD
Q

1'+

en

3

Q

Q
Q

Q
Q

GND

'-l..._ _r'

2

1 2019

4

18

5

17

6

16

Q

7

15

Q
Q

14

8

liD

9 1011 1213

DE

PAL16R6'
M SUFFIX ..• J PACKAGE
C SUFFIX ... J OR N PACKAGE

PAL1SR8'
M SUFFIX ..• FH OR FK PACKAGE
C SUFFIX FN PACKAGE

(TOP VIEWI

lTOPVIEWI

~ ~
__ u>d

Vee

eLK

Q

Q

GND

3

'-l..._---'r'

2

1 20 19

Q

4

18

Q

5

17

Q

6

Q

7

16
'15

Q

8

Q

I

2·4

~I~ ~ ~
(!l

14
9 10111213

OE

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265

PAL 16LBA, PAL 16LBA·2, PAL 16R4A, PAL 16R4A·2
STANDARD HIGH·SPEED PAL® CIRCUITS
functional block diagrams (positive logic)
'PAL16L8A
'PAL 16L8A-2

EN >1

&

32X64

'<:110-----0
10-----0

t>

10

10-,-""''''-1/0
16

0--.+........-1/0

IO-e+........-I/O

6

II
...

10-",-+,--1/0

II)

10-.-+........-1/0

CI)
CI)

.c:
en
ca
ca

10-.-+.........-1/0

...

6

C

'PAL16R4A
'PAL 16R4A-2
OE

EN2

ClK

C1
&

32X 64

-+-

>1

~

-+8

~

,:

-+-

~

-

r-+- ""'--

Q

~

-f-f-

-l-

Q

~
Q

~

EN

>1

'<:1

.

~

-i""7""

---..

--+r--"7

~

,

4

o

2'<:1
10

""

I/O
I/O

I/O
I/O

...

- denotes fused inputs

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-5

PAL 16R6A, PAL 16R6A·2, PAL 16R8A, PAL 16R8A·2.
STANDARD HIGH·SPEED PAl@ CIRCUITS

functional block diagrams (positive logic)
'PAl16R6A
·PAl16R6A·2

6E

_(N2
C1

ClK

~

&
32 X 64

;;'1

~

10

~
- : - --=-C>

....;.'!.-

;...

-

0.:-

Q

Q

~

.....-...

~

~

Q

~

~

-

Q

~

~

-..?,.....

r---.....
I---"

~

-

Q

2

Q

h
EN ;;'1

-+

-2

liD

\7

liD

...

6
'PAl18R8A
·PAl18R8A·2

6E
ClK
&

8

;;'1

32X 64

Q

10
Q
Q

8

16

Q
Q
Q

Q
Q

8
- denQtes fused inputs

2-6

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

PAL16LBA, PAL16L8A·2
STANDARD HIGH·SPEED PAL® CIRCUITS
logic diagram
I

(1 )

INPUT LINES

PRODUCT ,
LINES
0
0

I

4

8

12

16

20

24

28

··
···
"'8
··
··

31

1

f--

(19)

v

.-

0

.-

(2),,~

r>-l

(18) 1/0

v

(3) 15
I
16

I

··•
·
··
·•
··
·
···•
··
·
··•
·

f-...
f--

f-'

1

(17) liD

(4) 23
)l

'"

24

~p-

J

(16) 1/0

r--

(5) 31
I

)l

32

f--'"

1

(15) liD

v

(6) 39
I

)l

'"

40

>---'

(14) liD

V

7 47
I( )X

~

48

1

f--

v

~

(13) liD

>--

55
I (8) X

1

56

f-'

1
...

0

(12)

\--

r-

(9) 63
I

1

f--

(11 )
I

.)l

TEXAS .."

INSTRUMENlS
POST OFF1CE BOX 655012 • DAl.LAS, TeXAS 75285

2·7

PAL16R4A, PAL16R4A-2
STANDARD HIGH-SPEED PAL® CIRCUITS
logic diagram
ClKl.!lt>

.

INPUT LINES
PRODUCT ,
LINES
0
0

4

B

12

16

20

24

28

··
··
Ii
··
·
···
·
··
·
··
·
··•
·
·••
··•
·••
•

'-.../

1

1

-

v

(3) 15
I

(19)1/0

(18)1/0

1

16

c

...
A)

A)

:::T

v

).----,

7

en

1

}--

1.(2~

IE

31

>---.> :bJ;~Q
Cl

I (4) ....23
v

...en

CD
CD

~

24

-

:bJ;

'":J,...

rt

~15)0

D-

>---'

Cl

(5) 31
I

(16)0

32

I

e-D>---'

(6) 39
)l

40

'""J

~C>t1 v

f--

47
1(7)

(14) 0

Cl

)l

48

--'

f--

55
I (8)

Cl

1
v

(13)1/0

1

)l

56

f-<

)....)~
f-<

•

1

(12) 1/0

,. . 1

(9) 63
I~

2-8

~)OE

TEXAS ."

INSTRUMENlS
POST OFFICE BOX 656012 • DALLAS. TEXAS 76266

PAL 16R6A, PAL 16R6A·2
STANDARD HIGH·SPEED PAL® CIRCUITS
logic diagram
CLK

11lt>------------- -- ------------------------ ---------------,

P RODUCT,

LINES

INPUT LINES

0

0
00
0-

(2)

··
,?-

4
--

8

12

16

20

24

28

31

----

~

f----c

).

r---'

'8

··

liD

r---'

>---<

~D-

0
0

·
·
··
··
·
··
··
·
··
·

~-

~:CW'"

Q

Cl

}--->

f---'

16

r-r--P-

0

0

X

f---'

24

r=pf-----

0
0

~

'"";:1

~

Rv

I...

CI)

(17)

v

Q

CD
CD

.c

Cl

r--

(4) 23

0

...caca

(16)

Q

C

Cl

31

(5)

J]

(19)

A

I----'

32

~>~
I

~
Q
v

Cl

(6) 39

X

40

\----;

0

~Dr---'

~
Cl

(7) 47
v

~)
Q
v

48
0

C-=~tJ;

0
0
0

JII)

'"";:1

(13)

v

Q

Cl

55
56
0-

-

0
0
0
0

·

)--

V

J

(12)

\

(9) 63

~--

TEXAS ."

INSTRUMENTS
post OFFICE BOX 655012 • DALLAS. TEXAS 75265

liD

~
2-9

PAL 16R8A, PAL 16R8A-2
STANDARD HIGH-SPEED PAL® CIRCUITS
logic diagram
ClK

l!lt>-

PRODUCT i
LINES
0
0

,.

I

INPUT LINES
4

8

16

12

20

24

28

··
•
1(2~
'8
··
·
····
·
··•
·•
··
·
··
·
·•
··•
··•
··

31

:>f--J

Cl

D-

16

f---1
...--

...--D...--

(4) 23

~

:tw

~

'"Jv

(16)0

t1

I.:l

(15)0

...-->
)--

a

v

17 )0

Cl

(5) 31
X
32

i------1

Dr----'

rvr

Cl

(6) 39

I

40

"'--p-

~

'"-yo;::1 (14)0

~

'";::1

Cl

47
48

I (8)

(18)

~

Cl

I

24

tl

R

Cl

f---1

(3) 15

1(7)

""Q

f---1

I

I

~~

f---

:>-

55

f--f---

56

)--

(13)0

v

Cl

=>t1;~'''Q
Cl

(9) 63

I~-

2-10

~)OE

I

TEXAS ~

INSTRJJMENTs
POST OFFice BOX 655012 • DALLAS, TEXAS 75265

PAL 16L8A, PAL 16L8A·2, PAL 16R4A, PAL 16R4A·2
PAL 16R6A, PAL 16R6A·2, PAL 16R8A, PAL 16R8A·2
STANDARD HIGH·SPEED PAL@ CIRCUITS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: M suffix. . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
C suffix .............................. OOC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions
M SUFFIX

PARAMETER
Vee

Supply voltage

VIH

High-level input voltage

VIL

Low-level input voltage

IOH

High-level output current

IOL
TA

Low-level output current
Operating free-air temperature

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

5.5
5.5
0.8
-2
12
125

2
2

I OE input
I

C SUFFIX

MIN

2.4
2

All others

-55

0

5.5
5.5
0.8
-3.2
24
70

UNIT
V
V
V
mA
mA
·e

programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.

PI
...
U)

CD
CD

.c

(IJ

...caca

C

Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5762.

TEXAS . .

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-11

PAL16L8A, PAL16R4A, PAL16R6A, PAL16R8A
STANDARD HIGH-SPEED PAL® CIRCUITS
recommended operating conditions
M SUFFIX
MIN
fclock

Clock frequency'

tw

Pulse duration, see Note 2

tsu
th

Hold time, input or feedback after elK t

TYP

0
15

I <;:Iock high
I Clock low

Setup time, input or feedback before elK t

C SUFFIX

MAX
25

MIN

TYP

MAX

0

35

12

20

16

25
0

20
0

UNIT
MHz
ns
ns
ns

NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock' The minimum pulse durations specified
are only for clock high or clock low, but not for both simultaneously.

electrical chara,cteristics over recommended operating free-air temperature range

E

VIK

Vee = MIN,

11=-18mA

c

VOH

Vee = MIN,

IOH = MAX

D)

VOL

Vee = MIN,

10l = MAX

D)

102H

...

Vee = MAX,

Vo = 2.7 V

Vee; = MAX,

Vo = 0.4 V

II

Vee = MAX,

VI = 5.5 V

IIH

Vee = MAX,

VI = 2.7 V

III

Vee = MAX,

VI = 0.4 V

lo!

Vee = MAX,

Vo = 2.25 V
Outputs Open

CJ)

:::r

10Zl

CD

!en

Outputs
I/O ports
Outputs
I/O ports

Vee - MAX,

ICC

C SUFFIX

M SUFFIX

TEST.CONDITIONSt

PARAMETER

MIN

TYP*

2.4

3.2
0.25

I OE INPUT
I All others

MAX
-1.5

140

Vi' = OV

TYP*

2.4

3.3

0.4

MAX
-1.5
0.5
20

100
-20

100
20

-250

-250

0.2
25

0.1

-0.25

-0.4

20
-0.2
-30

185

UNIT
V
V

0.35

20

-0.2
-125

-30

MIN

V
~A

~

mA
~

mA

-125

mA

180

mA

140

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, TA = 25°C.
§The output conditions have been chosen to produce a current that closely aproximates one half of the true short-circuit output current, lOS.

switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER

FROM

TO

TEST CONDITIONS

f max

25

tpd

1,1/0,

TYP*
45
15

MAX

UNIT

MIN

TYP*

MAX

35
30

45
15

25

MHz
ns

tpd

elKt

0,1/0
Q

Rl = 500 II,

10

20

10

15

ns

ten

OE~

Q

el = 50 pF,

15

25

15

22

ns

tdis

OEt
1,1/0

Q

See Note 3

10

10

15

ns

0,1/0

14

25
30

14

25

ns

1,1/0

0,1/0

13

30

13

25

ns

ten
tdis

*AII typical values are at Vee = 5 V, TA = 25°C.
NOTE 3: Load circuits and voltage waveforms are s~own in Section 1.

2-12

C SUFFIX

M SUFFIX
MIN

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS,

T~XAS

75265

PAL 16LBA-2, PAL 16R4A-2, PAL 16R6A-2, PAL 16RBA-2
STANDARD HIGH-SPEED PAL® CIRCUITS
recommended operating conditions
M SUFFIX
MIN
fclock

Clock frequency

tw

Pulse duration, see Note 2

tsu

Setup time, input or feedback before elKt

th

Hold time, input or feedback after elK t

TYP

0

I Clock high
I Clock low

C SUFFIX

MAX

MIN

16

0

TYP

MAX
18

25

28
28
35

MHz
ns

25

ns

28
0

0

UNIT

ns

NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified
are only for clock high or clock low, but not for both simultaneously.

electrical characteristics over recommended operating free-air temperature range
PARAMETER
VIK

Vee = MIN,

11=-18mA

VOH

Vee = MIN,

IOH = MAX

Vee = MIN,

10l = MAX

VOL
10ZH

Outputs

Vec = MAX,

Vo = 0.4 V

II

Vec = MAX,

IIH

Vee = MAX,

III

Vee = MAX,

VI = 0.4 V

lo!

Vee = MAX,

Vo = 2.25 V

Vee = MAX,

Outputs Open

1/0 ports

ICC

TYP*

C SUFFIX
MAX

MIN

MAX

TYP*

-1.5
3.2

-1.5
2.4

0.25

Vo = 2.7 V

10Zl

MIN
2.4

Vec = MAX,

1/0 ports
Outputs

M SUFFIX

TEST CONDITIONSt

0.4

3.3

V
V

0.35

0.5

20

20

100
-20

-250

"A

VI = 5.5 V

0.2

0.1

mA

VI = 2.7 V

25

20

-0.2

' -0.2

-0.1
-30

-125
75

VI = OV

-0.1
-30

95

.c

CIl

...nsns

"A

C

mA

-125

mA

90

mA

70

Q)
Q)

"A

-250

I All others

U)

V

100
-20

10E INPUT

PI
...

UNIT

tFor conditions shown as MIN or MAX, use the appropriate value specified 'under recommended operating conditions.
*AII typical values are at Vee = 5 V, TA = 25°C.
§The output conditions have been chosen to produce a current that closely aproximates one half of the true short-circuit output current, lOS.

switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER

FROM

TO

TEST CONDITIONS

M SUFFIX
MIN

TYP*

16

25

f max

tpd

1,1/0,

0,1/0

tpd

elKt

Q

ten

OB

tdis

C SUFFIX
MAX

MIN

TYP*

18

25

MAX

UNIT
MHz

25

40

25

35

ns

Rl = 500 Il,

11

35

11

25

ns

Q

Cl = 50 pF,

'20

35

20

25

ns

OEt

Q

See Note 3

11

30

11

20

ns

ten

1,1/0

0,1/0

25

40

25

35

ns

tdis

1,1/0

0,1/0

25

35

25

30

ns

'All typical values are at Vce = 5V,TA = 25°C.
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-13

II

2-14

PAL20LBA, PAL20R4A, PAL20R6A. PAL20RBA
STANDARD HIGH-SPEED PAL® CIRCUITS
02706. DECEMBER 1982-REVISED DECEMBER 1987

•

PAL20LS'
M SUFFIX ... JW PACKAGE
C SUFFIX ... JW OR NT PACKAGE
(TOP VIEW)

Standard High Speed 125 nsl PAL Family

•

Choice of Input/Output Configuration

•

Preload Capability on Output Registers

•

DIP Options Include Both 300-mil Plastic
and 600-mil Ceramic
3-STATE

DEVICE

I INPUTS

o OUTPUTS

'PAL20LSA
'PAL20R4A
'PAL20R6A
'PAL20RSA

14
12
12
12

2
0
0
0

Vcc
)

o
)/0
)/0

REGISTERED
I/O
QOUTPUTS
PORTS
0
6
4 (3-state buffers)
4
6 (3-state buffers)
2
S 13-sta!e buffers
0

I/O
I/O
I/O
I/O

o
I
GND

description
These programmable array logic devices feature
high speed and a choice of either standard or
half-power speeds. They combine Advanced
Low-Power Schottky t technology with proven
titanium-tungsten fuses. These devices will
provide reliable, high performance substitutes
over conventional TTL logic. Their easy
programmability allows for quick design of
"custom" functions and typically result in a
more compact circuit board. In addition, chip
carriers are also available for further reduction
in board space.

TEXAS

CI)
CI)

.c
tn

...

U

CO
CO

U U

z>_o

NC
I

5

4 3 2 1 282726
25

I/O

6
7

24
23

I/O
I/O

8

22

NC

9
10

21

I/O

20
19

I/O

11

o

I/O

12131415161718

--ou--o
zz

The PAL20' series is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The commercial range is
characterized from ooe to 70°C.

::':!:~ri;·{:I~" ~=~~:r :.~,:::::~::.s not

...en

PAL20LS'
M SUFFIX ..• FH OR FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)

In addition, extra circuitry has been provided to
allow loading of each register asynchronously to
either a high or low state. This feature simplifies
testing because the registers can be set to an
initial state prior to executing the test sequence.

PROOUCTIOI OATA documants .ontain information
CURlnt IS of publication datI. Products conform to
specifications par the tarms of Taxi. Instruments

........_ _OJ-'

(!)

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

Copyright © 1982, Texas Instruments Incorporated

2-15

PAL20R4A. PAL20R6A. PAL20R8A
STANDARD HIGH·SPEED PAL® CIRCUITS
PAL20R4'
M SUFFIX . .. JW PACKAGE
C SUFFIX . .. JW OR NT PACKAGE

PAL20R4'
M SUFFIX . .. FH OR FK PACKAGE
C SUFFIX . .. FN PACKAGE

(TOP VIEW}

(TOP VIEW}

OUTCLK

:J

VCC

u
....
u
=> U U 0
__ 02>_'"

I

I/O
110

4

Q

3

5

Q

Q
Q

110
110

2 1 282726
25

110

24

I

6
7

NC

8

22

NC

21
20

Q
Q

19

110

23

10
11

E

Q
Q

12131415161718

- -

~ ~I~

- g

(!)

PAL20R6'
M SUFFIX . .. JW PACKAGE
C SUFFIX . .. JW OR NT PACKAGE
(TOP VIEW}
OUTCLK

PAL20R6'
M SUFFIX . .. FH OR FK PACKAGE
C SUFFIX . .. FN PACKAGE
(TOP VIEW)

...""
~

VCC
I
Q

432

Q
Q

I
I
I

Q
Q

Q

110
I

GNDL..C;~"':"::'i-J

u

=> U U
0
__ oz>_:::::

110

1 282726

5

25

6
7

24

8

22

NC

9
10

21

Q
Q
Q

23

20

11

DE

19

Q
Q
Q

12131415161718

--~~Io-g
(!)

PAL20R8'
M SUFFIX . .. JW PACKAGE
C SUFFIX . .. JW OR NT PACKAGE

PAL20R8'
M SUFFIX . .. FH OR FK PACKAGE
C SUFFIX . .. FN PACKAGE

(TOP VIEW}

(TOP VIEW}

OUTCLK

I

...""

VCC

U

....
U
=> 2
U >
U _0
__ 0

I
Q

Q
Q
Q
Q

4

3 2

1 282726

Q
Q
Q

Q

NC

Q
Q

21

Q

10

Q

11

GND '-C!........::~OE

12131415161718

--~~I~-O
(!)

2·16

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

Q

PAL2DL8A, PAL2DR4A
STANDARD HIGH·SPEED PAL® CIRCUITS
functional block diagrams (positive logic)
PAL20L8A
PAL20L8A-2
EN ;'1

&

'ill:>---- 0

40X64

0
1/0
1/0

II
...

1/0
1/0

U)

1/0

G)
G)

1/0

.c

0

...

6

CO
CO

C

PAL20R4A
P~L20R4A-2

J EN2

"liE

-l

OUTCLK

~
40X64

a

C1

;'1

-+-

1-0
( 10

-+-

~
1}
4

-+'---

*

Q

r---,
Q

r---

-+-+- - -+-

Q

r---,
Q

r---,

--;- EN

~

2'il

;'1

-+-

'il

""""T

>+
~

'"

+
~

..

1/0
1/0
1/0
1/0

-~
,4

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2·17

PAL20R6A, PAL20R8A
STANDARD HIGH·SPEED PAL® CIRCUITS

functional block diagrams (positive logic)
PAL20R6A
PAL20R6A-2

OE
OUTCLK

-tN2
' C1

r--;-

B
40X64 ....;.....

-..:L

•

,..-fI> -:..

-

~

~

b-i1!~

-

;;>1

1=0 2
10

Q

r-----

.J!..J!..-

---...
---...
---...

~

~

---...

J!..-

---...

r?-t-;___ r+-

Q

Q

Q

Q

Q

EN ;;>1

'V

2

6

)

L

I/O
I/O

. PAL20R8A
PAL20R8A-2

OE
OUTCLK
0
0
0
Q

Q

Q

Q

Q

8

2-18

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265

PAL20L8A
STANDARD HIGH·SPEED PAL® CIRCUITS
(1)

INPUT LINES

10

4

8

12

1\

16

20

24

28

32

36

\

(2) ..

~

-t..

P RODUCT
LI NES

0

•
•

(3) ..
~

(4)",

-t..

(22)

V

•
7
8

•
•
•
15

~

16

~

...

•
23•

(8) ...

;..

"""'t.

10)...

Q)

1/0

~

•

""

1

40

•
•
•
47

..
CO
CO

C
(18)

~

•
39

i

.c
en
(19)

rJ

1/0

(17)

1/0

~
...

48

•
•

(9)

1/0

24

•
•

...

U)

(20)

-~

31
"""t32

(7)"

II

.....

•
•

(6)",

I/O

...r--:---

•

(5) ..

(21)

o

(16)

I/O

v

•
55
56

•
•
•
63

(15)

v

o

(14)

"""1-

~

11)

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

2·19

PAL20R4A
STANDARD HIGH·SPEED PAL® CIRCUITS
OUTClK

(1)J ....
-V

INP!JT"lINES
10

~

4

8

12

16

20

24

28

32

36

\

123)

PR OOUCT

0

LIN ES

13)

...

4)_

••
•
15

f.A

.....

•
•
•
23

)--

v

•
•
31•

")-

'32

"

....

•

L>"

40

•

~

(9)_

•
•
47

1)

:J

1/0

MI.l ""
10

~

-V

o

~

119) 0

•
•
•
55

....

r----'

~

:J....

118)0

'1v

(17)

C1

:©i

48

b--J 1

116)

•
•
•
63

1
.....

v

I

(15)

"
(14)

.....-1

...

~3

2·20

o

I/O

~

56

£!.t-

121)

.:..r r - -

•
39•

7)

-J

1/0

C

24

16)

122)

. ~r

7
8

16

5)_

1

TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

I/O

PAL20R6A
STANDARD HIGH·SPEED PAL® CIRCUITS

OUTClK

(1)II.....

v

,

0

..

INPUTklNES
4

B

12

16

20

24

28

32

36

,
(23)

(2) ..

1/0

PR ODUCT
LI NES

0

r-.,......., 1
v

•

•
•
7

(3)
--t

8

•
•

4) ....

."

15•
16

...

(6)

-;.

(7)

(8) ...

...

(9)

)a

II...

...

.......

r-

~
....

•
23

c,

' ] (20

v

)a

U)

CD
CD

.s::.

f---'

24

•
•
•
31

)--

en
"]

M
M

(1 9)a

;.;>0-

c,

....

32

•
•
•
39

)-

40

"

...

•
•
•
47

)-

...
"

48

•
•
•
55

"]

...

CO
CO

o

r---

(1

v

c,

~

IJv

(1

c,

L>-~

~I

c,

"I------'

-)

56

10)

1/0

I

'0
>- ~
-:l... '"
c

•
•

(5)

(22)

J

•
•
•
63

...

v

(15)

1

1/0

(14)

11)

-;.

....

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

I

~) OE

2-21

PAL20R8A
STANDARD HIGH·SPEED PAL® CIRCUITS

OUTC LK

,...

(1)

v

INPUT",LlNES
"'0

4

8

12

16

20

24

28

32

(2)

36

"

(23)

-;..

PRODUCT
LINES

0

•
•
•
7

(3) ...

:r- ~ r.J.""
ID

E

•

>-

15•
"

A

'"

•
•
•
23

.•

A

'"

>-

•

'"

•

>-

A

•

_39

~

•

-

>-

•
47

~

48

(9) "

•
•
•
55

>-

...

i:l...

(20

~

Q

~
~

~19
V

Q

11(18

"V""

Q

1.
-yo-

Q

1.v

(1 6)

Q

I.J.

(15

r----'

~

(17

r----'

M

.-J"" r----'

"56

10)

Q

Cl

-4.

(8) ...

(21)

Cl

31
(6)
...
32
(7)

~

:r-

"'2~
,

I.J.v

Cl

16

(51 ...

Q

.-J"" - - '

~
4)

~

Cl

•
•
•
63

~

Q

V

Cl

(14)

....

!.!t

~

I

3)_
OE

~

2-22

TEXAS .."
INSTRUMENlS
POST OFfiCE BOX 655012 • DALLAS, TEXAS 75265

PAL20LBA, PAL20R4A, PAL20R6A, PAL20RBA
STANDARD HIGH-SPEED PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: M SUFFIX . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
C SUFFIX ............................. DoC to 70°C
Storage temperature range ......................................... - 65°C to 1 50°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions
M SUFFIX

PARAMETER
VCC

Supply voltage

VIH

High-level input voltage

Vil

Low-level input voltage

IOH

High-level output current

IOl

Low-level output current

fclock

Clock frequency

tw

Pulse duration, clock

tsu

Setup time, input or feedback before OUTClKt

th

Hold time, input or feedback after OUTClKt

TA

Operating free.,.air temperature

I

High

I

low

C SUFFIX

MIN

NOM

MAX

MIN

NOM

MAX

4.5
2

5

5.5
5.5
0.8
-2
12
20

4.75
2

5

5.25
5.5
O.B
-3.2
24
30

0
20
20
30
0
-55

125

0
15
15
25
0
0

UNIT
V
V
V
mA

EI

mA
MHz
ns
ns
ns
ns

70

·C

programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5762 .

. TEXAS.

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-23

PAL20LBA. PAL20R4A. PAL20R6A. PAL20RBA
STANDARD HIGH-SPEED PAL® CIRCUITS
electrical characteristics over recommended free-air operating temperature range
PARAMETER

TEST CONDITIONSt

VIK

Vee = MIN,

11=-18rnA

VOH
VOL

Vee = MIN,
Vee - MIN,

10H = MAX
10L = MAX

Vee = MAX,

VIH = 2.7 V

Vee = MAX,

VIH = 0.4 V

0, Q outputs
10ZH
10ZL

I/O ports
OE Input

II

•

I/O ports
0, Q outputs

All others
OE Input

IIH

All others
OE Input

IlL

All others

lo§

c

....

lee

D)

Vee = MAX,

VI = 5.5 V

Vee = MAX,

VI = 2.7 V

Vee = MAX,

VI = 0.4 V

Vee = MAX,

Vo = 2.25 V

Vee = MAX,

VI = 0 V,

Outputs open,

DE at VIH

M SUFFIX

C SUFFIX
MAX

MIN TYP*

MAX

MIN TYP*

-1.5
2.4

3.2

2.4

0.25

0.4

V

0.5

V
V

20
100
-20

100
-20

-250

-250

0.2

0.2

0.1
40

0.1
40

20
-0.4

20
-0.4

20

-0.2
-30

-1.5
3.3
0.35

-125
150

-0.2
-30

210

UNIT

~A
~A

rnA
~A

rnA

-125

rnA

210

rnA

150

D)

tFor conditions shown as MIN or MAX, use the appropriate value specified' under recommended operating conditions.

en
:::r

§The output conditions have been chosen to produce a current that closely approximates one half the true short-circuit current, lOS.

....en

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

CD
CD

tAli typical values are Vee = 5 V, TA = 25°e.

PARAMETER

FROM

TO

TEST CONDITIONS

f max

MIN TYP*

MAX

30

UNIT

MHz

15

30 .

15

25

RL = 5000,

10

20

10

15

ns

Q

eL=50pF

10

25

10

20

ns

Q

See Note 2

11
14

25
30

11
14

20
25

ns

0, I/O
0,1/0

12

30

12

25

ns

1,1/0

0,1/0

tpd

OUTeLKt

Q

ten

OE

tdis
ten

OEt
1,1/0
1,1/0

tAli typical values are at Vee = 5 V, TA = 25°e.
NOTE 2: Load. circuits and v,?ltage waveforms are shown in Section 1.

2-24

C SUFFIX
MAX

20

tod

tdis

M SUFFIX
MIN TYP*

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

ns

ns

PAL20LBA, PAL20R4A, PAL20R6A, PAL20RBA
STANDARD HIGH·SPEED PAL® CIRCUITS
PRELOAD PROCEDURES
5V

Vcc

/

ov--f
VIH

,._--.:O:::U::..:T:,:.P,::U..:.;TS::.D::;I:.:S:::,AB:::;L:,:E:.::D:.....-_

....Jt

___.

\1...__________

VIL _ _ _

~

j+-ton

I
I

I4~O~,~I:
I

i
I
I

I

I
I

I

o

: VERIFY NEW
I STATEO'n

VDH~~~~~)L
_ _~~[j~~~~LY-1_~I~~~~~c========
VOL":=
z
:
~ tpd

PIN1
IOUTCLK)

VERIFYO'n+1

h

VIH
VIL-----------------------J

FIGURE 1, PRELOAD WAVEFORMS

I+-

II
...
II)

CI)
CI)

.c

U)
L _ _ _ __

...caca

C

preload procedure for registered outputs
Step
Step
Step
Step
Step
Step
Step

1
2
3
4
5
6
7

Pin 13 to VIH, Pin 1 to VIL, and VCC to 5 volts,
Pin 14 to VIHH for 10 to 50 microseconds,
Apply VIL for a low and VIH for a high at the Q outputs.
Pin 14 to VIL.
Remove the voltages applied to the outputs.
Pin 13 to VIL.
Check the output states to verify preload.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-25

E

c
....
Q)

Q)

en
J
CD
CD

r+
UI

2-26

TIBPAD16N8·7C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER
03085. JANUARY 1988

•

Very-High-Speed Address Decoder (Ideal for
Use .with High Speed Processors)

•

I/O Propagation Delay: 7 ns Max

•

Field Programmable on Standard PLD
Programmers

ITOP VIEW)

Vee
o
1/0
1/0

I/O

•

Fully TTL Compatible

•

Security Fuse Prevents Unauthorized
Duplication

•

Dependable Texas Instruments Quality and
Reliability

•

J OR N PACKAGE

1/0
1/0
1/0

o
GND

Potential Applications
Address Decoders
Code Detectors
Peripheral Selectors
Fault Monitors
Machine State Decoders

~

_ _...r-

II...

FN PACKAGE
ITOPVIEW)

u

u
___ >0
3

description

2

U)

CD
CD

1 20 19

4

18

5

17

.c

o

...caca

16

The TIBPAD 16N8 is a very-high-speed
Programmable Address Decoder featuring 7 ns
maximum propagation delay, the highest speed
in the TTL programmable logic family. The
TIBPAD16N8 utilizes the IMPACT-X'" process
and proven titanium-tungsten fuse technology
to provide reliable, high performance substitutes
for. conventional TTL logic.

7

15

8

14

C

9 1011 1213

The TIBPAD16N8 contains 1a dedicated inputs and 8 outputs. Each output has two product terms, one
of which is used to enable the inverting buffer associated with the respective output. Six of the outputs
are I/O ports, the remaining two are dedicated outputs. Each of the six I/O ports can be individually
programmed as an input or an output; this allows the device to be used for functions requiring up to 16
inputs and and 2 outputs or 1 inputs and 8 outputs.

a

The TIBPAD 16N8 is supplied with all six I/O ports in the input configuration (output buffers in the highimpedance state). If an I/O port is selected to be an output, it must be programmed accordingly. It is
recommended that all unused outputs on this device remain in the three-state condition for better noise
immunity.
The TIBPAD16N8-7C is characterized for operation from

IMPACT~X

aoc to

75°C.

Is a trademark of Texas Instruments Incorporated.

PROOUCTIOI DATA documents contain information
Durrant II of publication data. Pfoducts caoform to
specifications par the tarms at TailS Inltruments

::.~=;af:~':!1i ~::I~~I~. :.:":!;:::~~.

not

Copyright @ 1988, Texas Instruments Incorporated

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-27

TIBPAD 16N8·7C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER
functional block diagram (positive logic)
&

EN '" 1

32x16

'VP----O
P----O

I>

10

16
~"""'~I/O

~..r"'-I/O

6

•

~tt-"'-I/O

D-i..r...._1/0

c

....'"

'"

D-i..r...._1/0
6

tJ)

:::r
CD

....CD
(II

2-28

TEXAS . "

INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265

TlBPAD16N8-7C
HIGH-PERFORMANCE PROGRAMMABLE ADDRESS DECODER
logic diagram (positive logic)
1111
0

4

8

12

16

20

24

31

J..!!!!.
~
N

(2)

(3)

28

k1~

":x

~
-"..

0

I/O

I/O

fI
J

= 4.75 V.

/

7.7

/V

7.6

.!!

Q

c

.'."
.....'"
£

7.5

0

7.4

/

7.3

7.0

/

/

/

7.2
7.1

/

V

2

/
4

6

Number of Outputs Switching

FIGURE 2

2-32

/

TEXAS . "

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265

8

TIBPAD16N8·7C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE

SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
150r--'--~--~--~-'---.--~--'

6.5

UNPROGRAMMED DEVICE

'"f

I\.tPH~
6.0

\

CD

E

j::

~

2l

\

5.5

c

tPLH

.'"
CI.

E! 5.0

11.

TA-Free-Air Temperature- DC

PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
24

n,
390 n,
III

c

..
I

E

j::

>
.!!
CD

4.4
4.2
4.0
4.5

V

U)

G)
G)

-

20

...
CO
CO

18

Q

14

.,..

12

0

tpHL-

..'"

~J

CI.

i.

tP~H-:::
I

/

~-

V/ ./

10
8

4
5.5

/

/./ V

6

I

V
V t PHL

16

c

4.75
5.25
VCC-Supply Voltage-V

.c
en
C

VCC = 5 V,
R1 - 200 n,
R2 - 390 n,
TA - 25 DC,
1 OUTPUT SWITCHING

22

-R2 -CL - 50 pF,
-TA = 25 DC

r--;:

fI
-- ...

-

PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE

-R11. 200

...... ~

/

t7

FIGURE 4

FIGURE 3

~

/

./
./

r---

4.5
-75 -50 -25 0
25 50
75 100 125
TA-Free-Air Temperature- DC

9~7=5~-~5=0---=25~~0--=2=5--~-==-~~~125

f

'\

r-...
J
-....... --........ "- V

o

.~

7.0
6.8
,".6.6
6.4
~ 6.2
j:: 6.0
~ 5.8
~ 5.6
§ 5.4
;; 5.2
~. 5.0
E! 4.8
11. 4.6

VCC - 5 V,
R1 - 200 n
R2 - 390 n
CL - 50 pF,
1 OUTPUT SWITCHING

;;

~

o

FIGURE 5

V
hV

600
200
400
CL -Load Capacitance-pF

800

FIGURE 6

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-33

2-34

TIBPAD 1BNB·6C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER/NAND ARRAY
03086. DECEMBER 1987

•

J OR N PACKAGE

Very High Speed Address Decoder (Ideal for
Use with High Speed Processors)

(TOP VIEW)

Vee

•

1/0 Propagation Delay: 6 ns Max

•

Suitable for High Speed NAND·NAND Logic
Implementation

•

Field Programmable on Standard PLD
Programmers

•

Fully TTL Compatible

•

Security Fuse Prevents Unauthorized
Duplication

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
GND '-1.._ _..r"

•

Dependable Texas Instruments Quality and
Reliability

•

Potential Applications
Address Decoders
Random Logic (NAND·NAND)
Code Detectors
Peripheral Selectors
Fault Monitors
Machine State Decoders

II
...

FN PACKAGE
(TOP VIEW)
U

UO

en

--->;:,
3

2

II)
II)

1 20 19

4

18

5

17

6

16

15
8

14

.c
en

1/0
1/0
1/0
1/0
1/0

...
~
~

C

910111213

description
The TIBPAD lSNS-6C is a very-high-speed Programmable Address Decoder featuring 6-ns maximum
propagation delay, the highest speed in the TTL programmable logic family. The TIBPAD lSNS uses the
IMPACT-X'" process and proven titanium-tungsten fuse technology to provide reliable, high-performance
substitutes for conventional TTL logic.
The TIBPAD1SNS-6C contains 10 dedicated inputs and 8 product terms, each followed by an inverting
buffer leading to an 110 port. Each of the eight 110 ports can be individually programmed as an input or
an output, depending on the state of the fuse controlling the output buffer, as indicated by Table 1. This
allows the device to be used for functions ranging from 17 inputs and a single output to 10 inputs and
S outputs.

sw

A high-speed feedback path, which does not go through the output buffer, is provided to offer higher
performance operation in designs where feedback is required. The architectural fuse on the 110 multiplexer
is used for the selection of this path (see Table 2). This makes the TIBPAD1SNS-6C ideal for the
implementation of a very fast NAND-NAND logic.

:>w
a:

The TIBPAD lSNS is supplied with all eight 110 ports in the input configuration (output buffers in the highimpedance state). If an 110 port is selected to be an output, it must be programmed accordingly. It is
recommended that all unused outputs on this device remain in the high-impedance state for better noise
immunity.

a..

I-

o

::::>

The TIBPAD1SNS-6C is characterized for operation from 0 DC to 75 DC.

c

oa:

a..

IMPACT-X is a trademark of Texas Instruments Incorporated.

PRODUCT PREVIEW d......1IIJ ••ntain informati.n
• n prod••ts in the formative .r delign pha.. of
development. Charactaristia data anil other

=::~::Iri~~ dt-:i:C8:::1~T:'::'=~ur:=
pradoets without notice.

Copyright @ 1987, Texas Instruments Incorporated

TEXAS •

INsrRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-35

TIBPAD1BNB·6C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER/NAND ARRAY

functional block diagram (positive logic)
8xl>

&
10

I>

~

8

8

~

~

8

9

36x8

~

1/0

EN

L

8

18XMUX
1

E

I--

G1

C

m
m

":'

r+

en
::r

Table 1. Output Buffer Programming

CD
CD

ARCHITECTURAL

rn

FUSE

r+

OPERATION

Table 2. I/O Multiplexer programming
ARCHITECTURAL
FUSE

Input

Intact

Intact

(Output Buffer

Blown

in Hi-Z Statel
Output

Blown

"'0

:D

o
C

c:
(")
-I
"'0

:D

m

S

m

~
2-36

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

OPERATION
I/O Feedback
High-Speed
Feedback

TIBPAD1BNB-6C
HIGH-PERFORMANCE PROGRAMMABLE ADDRESS DECODER/NAND ARRAY

logic diagram (positive logic)
III

I~

DI191

I

~

131

-

DIISI
I/O

v

141

I/O

MUX ,

1
~

DI171
v

151

I/O

MUX ,

II)

.c

BI~

IV

en

I/O

MUX ,

161

....

Q)
Q)

1
~

II
....COCO

C

1
~

&

I/O

v

171

MUX ,

1
~

~

lSI

1141

I/O

MUX,

1

~

~

W

DI131

~

191

-

I111

HIGH PERFORMANCE PROGRAMMABLE ADDRESS DECODER/NAND ARRAY

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265

I/O

a:

c..

tO

DI121

~

:>W

I/O

::::>
C

0
a:
c..
2-37

TlBPAD18N8·6C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER/NAND ARRAY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150 °C
NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions

E
C

I»
r+
I»
(J)

:r
CD
CD

Vee

Supply voltage

VIH

High-level input voltage (see Note 2)

Vil
10H

low-level input voltage (see Note 2)
High-level output current

10l
TA

Operating free-air temperature

MIN

NOM

MAX

4.75

5

5.25

2

UNIT
V
V

Low-level output current

0

0.8
-3.2

V
rnA

24

rnA

75

°e

NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or
tester noise. Testing these parameters should not be attempted without suitable equipment.

electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted I

r+

TEST CONDITIONS

PARAMETER

(II

MIN

Typt

2.4

3

MAX
-1.2

UNIT
V

Vee = 4.75 V,

11= -18 rnA

VOL

Vee = 4.75V.
Vee - 4.75 V.

10ZH

vee = 5.25 V.

10H = MAX
10l - MAX
Vo = 2.7 V

IOZl
II

Vee = 5.25 V.

Vo = 0.4 V

20
-20

Vee = 5.25 V,

VI = 5.5 V

0.2

pA

IIH

Vee = 5.25 V,
Vee - 5.25 V,

VI=2.7V

20

VI - 0.4 V

-0.25

pA
rnA

Vee = 5.25 V.
Vee = 5.25 V.

Vo = 0 V
VI = 4.5 V

VIK
VOH

III
lOS
lee

0.37

V
0.5

V
pA
pA

rnA
140

180

rnA

switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER

"'C

FROM

::XJ

CONDITIONS

I/O (no feedback)

o

I/O (with 1 feedback path

C

C

tpd

(")

-I
"'C
::XJ

TEST

TO

I

1/0
1/0
-

1/0 MUX fuse blown)
(with 2 feedback paths
I/O MUX fuse blown)
(with 3 feedback paths
1/0 MUX fuse blown)

Rl = 200
R2 = 390

el = 50 pF

tAli typical values are at Vee = 5 V. TA = 25°e.

m

-
w
W

a:

a..
t-

(.)
:;:)

Q

oa:

a..

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-39

•

C

I»
r+
I»

en
::r
~
~

r+

til

2-40

TIBPAL 16L8·12M, TIBPAL 16R4·12M, TIBPAL 16R6·12M, TIBPAL 16R8·12M
TIBPAL 16L8·1 DC, TIBPAL 16R4·1 DC, TIBPAL 16R6·' DC, TIBPAL 16R8·1 DC
HIGH·PERFORMANCE IMPACT™PAL® CIRCUITS
03023. MAY 1987-JANUAAY 1988

•

•

High·Performance Operation:
f max (w/o feedback)
TIBPAl16R'·10C Series ... 62.5 MHz
TIBPAl 16R'·12M Series •.. 56 MHz
f max (with feedback)
TIBPAl16R'·10C Series ... 55.5 MHz
TlBPAl16R'·12M Series ... 48 MHz
Propagation Delay
TlBPAl16l·10C ... 10 ns Max
TlBPAl16l·12M ... 12 ns Max

Vee
0
I/O
I/O
I/O
I/O
I/O

Functionally Equivalent, but Faster than
Existing 20·Pin PAls

I

I/O

I

0

GND

•

Preload Capability on Output Registers
Simplifies Testing

•

Power·Up Clear on Registered Devices (All
Register Outputs are Set low, but Voltage
levels at the Output Pins Remain High)

•

TIBPAL l6LB'
M SUFFIX ..• J PACKAGE
C SUFFIX ... J OR N PACKAGE
(TOP VIEWI

.c

_>0
3

2

C/)

4

•

Dependable Texas Instruments Quality and
Reliability

8

14

PAL16LB
PAL16R4
PAL16R6
PAL16R8

3·STATE

10
8
8
8

2
0
0
0

REGISTERED
Q OUTPUTS

0
4 (3·statel
6 13-statel
8 (3-statel

I/O

...coco

1 20 19

Security Fuse Prevents Duplication

o OUTPUTS

~
~

U

u

•

INPUTS

U)

C SUFFIX ... FN PACKAGE
(TOPVIEWI

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

DEVICE

PI
...

TIBPAL l6LB'
M SUFFIX ... FK PACKAGE

18

I/O

5

17

I/O

6

16

I/O

15

I/O
I/O

C

9 1011 12 13

PORTS
6
4

2
0

Pin assignments in operating mode

description
These programmable array logic devices feature high speed and functional equivalency when compared
with currently available devices. These IMPACT" circuits combine the latest Advanced low-Power
Schottky t technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes
for conventional TTL logic. Their easy programmability allows for quick design of custom· functions and
typically results in a more compact circuit board. In addition, chip carriers are available for further reduction
in board space.
All of the register outputs are set to a low level during power-up. Extra circuitry has been provided to allow
loading of each register asynchronously to either a high or low state. This feature simplifies testing because
the registers can be set to an initial state prior to executing the test sequence.
The TIBPAl16' M series is characterized for operation over the full military temperature range of - 55°C
to ·125°C. The TIBPAL16' C series is characterized for operation from aoc to 75°C.

IMPACr" is a trademark of Texas Instr~ments Incorporated.
PAL® is a registered trademark of Monolithic Memories Inc.
t'ntegrated Schottky-Barrier diode-clamped transistor is patented by Texas Instruments. U.S. Patent Number 3.463.975.
PRODUCTION DATA d••uments ••ntain inf.rmati.n
currant as of publication data. Products conform to
spacificatians par the tarms of TaXI. Instruments
:=~:~~i;ar::,~1i ~:~~:i:r :,~O::~::~:~~ not

TEXAS ~

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

Copyright @ 1987, Texas Instruments Incorporated

2·41

TlBPAL 16R4·12M, TIBPAL 16R6·12M, TIBPAL 16R8·12M
TlBPAL 16R4·1 DC, TIBPAL16R6·1 DC, TlBPAL 16R8·1 DC
HIGH·PERFORMANCE IMPACT™PAL® CIRCUITS
TIBPAl 16R4'
M SUFFIX ... J PACKAGE
C SUFFIX ... J OR N PACKAGE

TIBPAl16R4'
M SUFFIX ... FK PACKAGE
C SUFFIX .•• FN PACKAGE

(TOPVIEWI

(TOP VIEW)

eLK

Vee

'" U
....
UO
_ _ U>;:,

I/O
I/O

E
c
D)

....
D)

en

::::r

3

2

1 2019

0

4

18

Q

5

17

Q

6

16

0

15

I/O
I/O

14

I/O
Q
Q

0
0

9 1011 1213

5E

-

~1t:5

gg

(!l

TIBPAl16R6'
M SUFFIX ••• J PACKAGE
C SUFFIX •.. J OR N PACKAGE
(TOP VIEW)

eLK

nBPAl16R6'
M SUFFIX .•. FK PACKAGE
C SUFFIX .•• FN PACKAGE
(TOP VIEW)

Vee
1/0

CD
CD

Q

....rn

3

Q

2

1 2019
18

4

Q

17

Q

16

6

Q
Q

15
14

1/0

Q
Q
Q
Q
Q

9 1011 12 13

GN D '-t...-=--"";"J-' OE

-

~1t:5

ga

(!l

TIBPAl16R8'
M SUFFIX .•• J PACKAGE
C SUFFIX .•• J OR N PACKAGE
(TOP VIEW)

eLK

TIBPAl16R8'
M SUFFIX •.. FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)

~ tl
__ u>o

Vee
Q
Q

3

18

Q

Q

5

17

0

6

16

Q
Q
Q

Q

7

Q

8

14

Q

9 1011 1213

ill

- 0lw
a
zO
(!l

Pin assignments in operating mode

2·42

1 2019

4

o

GND '-t...-=--~t-'

2

Q

TEXAS •

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

a

TIBPAL 16L8·12M, TIBPAL 16L8·1 OC, TIBPAL 16R4·12M, TlBPAL 16R4·1 OM
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS

functional block diagrams (positive logic)
'PAL16L8

&

7

EN >1

b-----o

32 X 64

0----0

0-.........-1/0
D-e+........-I/O

.......-I/O

o-~

IO-~.........-I/O

...

n-a+-....__ 1/0

CI)

Q)
Q)

.c

U)

...

6

C'CS
C'CS

C

'PAL 16R4

EN2
C1

O!
CLK

r---s;32X64

,.......,..
16xt>

8

~

~ "v

--,

p-f- "v

rlL--

>1

8

~

1-0

~
~
~

2'9

Q

~

10

Q

:>

1----1

:>

~

:>

~

Q

Q

I - - EN >1

r+-

'9

'"'-

.....

~
'---7
I-+-

"'\

~I--+4

"'\

.....

~
4

7

1/0
1/0
1/0
1/0

....

rv denotes fused inputs

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265

2-43

TIBPAL 16R6·12M, TIBPAL 16R6·1 DC, TIBPAL 16R8·12M, TlBPAL 16R8-1 DC
HIGH·PERFORMANCE IMPACT ™PAL® CIRCUITS
functional block diagrams (positive logic)
'PAL16R6

De----------------------~~~--,

CLK .....--------------------------~

r~-r1=ii2tl--o
r-----t------1-~-o

t---t-----t.......:1--o
t---t-----t.......:1--o
r------t------1-..l--

E

0

c

C»
r+
C»

........

l--~:p_1IiI
_tb--eri........~-~-

f/)

:r
CD
CD

1/0
1/0

r+
(I)

'PAL16R8

De
eLK
;;'1

0
0
0

16

0

a
0
0
0

rv denotes

2-44

fused inputs

TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TlBPAL 16LB·12M, TlBPAL 16LB·1 DC
HIGH·PERFORMANCE IMPACTTMPAl® CIRCUITS

INPUT LINES

P ROOUCT,
LINES
0

0

4

8

12

16

20

24

28

31

0
0
0
0
0

t----.

}---

r-- f..--'
r--

o-

~
8

r-

0
0
0
0
0
0

V--

~

t:>--

(3) 15
')f

p-

(19)

I.-

J

(18)

o

1/0

J<:

16
}-c

0
0
0
0
0
0

1

./

1

(17)

--V

1/0

r--

")[

J:

en

J<

24
0
0
0
0
0
0

I (5)

r-

f--....
r-- fJ

31

"

~

0
0
0
0
0
0

(6

)

p-

r-<~

~

J

r)----

0
0
0
0
0

)----

.

)---)----

47
I (7)")1.

f--....

V

1

--V

I<'

+-

48
0
0
0
0
0
0

-

55
I (8) ")I
56

h

f-<

0
0
0
0
0
0

....r~f-/

1

'>--

63

J-

J

(14)

1

i-_J
)----

(15)

1

~

J..!Ilt>t:.

(16)

I.-

l-

39
40

I

J

1/0

...
CO
CO

C

....

32

I

en

II)
II)

~

(4) 23

II
...

(13)

(12)

I.-

110

1/0

110

o

(11 )

I!

-IJ1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2·45

TlBPAL 16R4·12M, TIBPAL 16R4·1 DC
HIGH·PERFORMANCE IMPACT™PAL® CIRCUITS

CLK1!lt>
p RODUCT,
LINES
0
0

INPUT LINES
4

8

12

16

20

24

28

··
··
~
''8
···
··•
·
··•
·
··•
•

E

31

J

~

v

j

l)-

(18)

Vi

)--

(3) 15
16

I

(19)

1/0

1/0

>->->--

P-Q[tJ..!!.~1 a
C1

(4) 23

24

>--1=>J<

32

C
C1

>--

(5) 31

~16) a

l-

~'-

..>-

I--).-.l-

')[

>--

··•
·
··
·
···•

P-~

48

'-..>--

55

2·46

(9

)

J

bv

(14)

a

r-

----J<.J

l-

p- I--"
f--r---,

63

J(

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

(13)

1/0

i

}--

56

I

a

C1

47
(7) ':>I,

(!!)

(15)

v

C1

(6) 39

40

kJ

t;:}

j

VI

(12)

~)

1/0

TIBPAL16R6·12M, TIBPAL 16R6·1 DC
HIGH·PERFORMANCE IMPACT'MPAL® CIRCUITS

CLKDlt>

.-~----

-

------------

INPUT LINES

P RODUCT •
LINES
0

0

4

8

16

12

20

24

28

31

1

:0

0
0

v

}--

-

~
8

I

(191

I/O

-« .....

0
0
0
0
0
0

}--

>-D-

(31 15

}--

16

}--

o -

fbl~""
Cl

\---

0
0
0
0
0

Q

->

t1;

~I
Q
v

Cl

(41 23

-'-

24

\-----'

\---,

0
0
0
0
0
0

t>
-'

t1;

'"J

(161

t1;

>-;:I

(151

V

Q

...caca

Q

Cl

(51 31
\---

32
0
0
0
0
0
0

-

->
-

V

Q

Cl

39
(61 ')[
}--

40
0
0
0
0
0
0

~

48

~

;b-t1;

0
0
0
0
0
0

-

55
(81 ")(

v

(141

Q

Cl

)--

47
(71 ")(

~

KY~I Q

Cl

56

··
·
-~
0
0

l-<

h

1-

!-/

"---'

~-

.

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

J

v

(121

I

I/O

~I

2-47

TIBPAL 16R8·12M, TIBPAL 16R8·1 DC
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS

...

CLK ( 1 ) v

.

INPUT LINES

P RODUCT ,

LINES
0

(2)

0

4

8

12

16

20

24

28

··
·•
··•
·•
··•
•

31

-

tr ""

D-

C1

>--

~

Vb-

8

}---

~P}---

16

o

....

.--

>-D-

'>r
24

>--

··
•
•

CD
CD

....
til

>--

·
•
••
•

....

Q

}---

>--

')[

f6l
fbl

I.:J.
(14)
-va- Q

C1

'"

40

·•••
··
··
·

~

I.:J.
(15)
--vo-- Q

P-

(6) 39

~
-

(7) 47
48

)--

C1

:>-

~) Q

C1

(8)~55

,...

56

••

~~~t?''''

··•

2·48

R(16)

C1

>--

'>r
32

(9) 63
·X

~

-:>}---

(5) 31

I

!.:1
(17)
-va- Q

C1

(4) 23

en
::T

fkl
t1

~Q

C1

(3) 15

I»
I»

Q

.

C1

'-

~)

t

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

Q

TlBPAl16l8·12M, TIBPAl16R4·12M, TIBPAl16R6·12M, TIBPAl16R8·12M
TIBPAl 16LB·1 DC, TIBPAl 16R4·1 DC, TlBPAl 16R6·1 DC, TlBPAl 16R8·1 DC
HIGH·PERFORMANCE IMPACTTMPAL@ CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: M suffix. . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°e
e suffix .............................. ooe to 75°e
Storage temperature range ......................................... - 65 °e to 150 0 e

I
I

I

NOTE 1: These ratings apply except for programming pins during a programming cycle.

I

recommended operating conditions
PARAMETER
VCC
VIH
Vil
10H
10l

MIN
4.5
2

Supply voltage
High-level input voltage (see Note 2)
low-level input voltage (see Note 2)

-12M
NOM
5

High-level output current
Low-level output current

fclock Clock frequency

12
56

0

l High
J low

tw

Pulse duration, clock (see Note2)

tsu
th
TA

Setup time, input or feedback before ClKi
Hold time, input or feedback after ClKt
Operating free-air temperature

-IDe
MAX
5.5
5.5
0.8
-2

9
9
11

0
-55

25

125

MIN
4.75
2

NOM
5

0
8
8
10
0
0

25

MAX
5.25
5.5
0.8
-3.2
24
62.5

75

~

UNIT
V
V
V
mA
mA
MHz

il
G)

ns
ns
ns

...

en
ca
ca
Q

°c

NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system andlor

tester noise. Testing these parameters should not be attempted without suitable equipment.

.

electrical characteristics. over recommended operating free-air temperature range

VIK
VOH
VOL

VCC
VCC
VCC

10ZH§

VCC

10Zl §
II

VCC
VCC

= MIN,
= MIN,
= MIN,
= MAX,
= MAX,
= MAX,
= MAX,
= MAX,
= 5 V,

IIH§

VCC

Ill§

Vce

lOS'

Vce
Vce - MAX,
V, = OV,
f = 1 MHz.
f = 1 MHz.
f = 1 MHz.

ICC
ein
Cout
CelK

-12M

TEST CONDITlONSt

PARAMETER

=

II

MIN
-18 mA

= MAX
= MAX
Vo = 2.4 V
Vo = 0.4 V
VI = 5.5 V
V, = 2.4 V
V, = 0.4 V
Vo = 0
IOH
10l

2.4

-30

Outputs Open

TYP*
-0.8
3.2
0.3

MAX
-1.5

MIN

-10C
TVPt
-0.8

MAX
-1.5

UNIT

0.5

V
V
V

100

100

~

-100
0.2

-100

~

0.2

mA

2.4
0.5

3.2
0.3

25

25

~A

-0.08 -0,25

-0.08 -0.25

mA

-70

-130

140

180

=2V
Vo = 2 V
VelK = 2 V
V,

5
6
6

-30

-70

-130

mA

140

180

mA

5

6.
6

pF
pF
pF

t For conditions shown as MIN or MAX use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vce = 5 V. TA = 25°e.
§ I/O leakage Is the worst case of 10Zl and I,l or 10ZH and ',H. respectively.
, Not inore than one output should be shorted at a time and duration of the short·circuit should not exceed one second.

TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

.

.c:

2-49

TIBPAL 16L8·12M, TIBPAL 16R4·12M, TIBPAL 16R6·12M, TIBPAL 16R8·12M
TIBPAL 16L8·1 DC, TIBPAL 16R4·1 DC, TIBPAL 16R6·1 DC, TIBPAL 16R8·1 DC
HIGH·PERFORMANCE IMPACT™PAL® CIRCUITS
switching characteristics over recommended supply voltage and oplnating free·air temperature ranges
(unless otherwise noted)
PARAMETER
fmax*

FROM

TEST CONDITIONS

TO

With Feedback

tpd

0.110

tod
ten

Q

tdis

ClKt
OE<
OEt

ten
tdis

1.110
1.110

0.110
0.110

R1 = 200 O.
R2 = 390 O.
See Figure 1

Q
Q

-12M
TYpT

48
56
3
2

Without Feedback

1.110

MIN

MAX

MIN

-10C
TypT

MAX

12
10
10
10
12
12

55.5
62.5
3
2
1
1
3
3

80
85
7
5
4
4
8
8

10
8
10
10
10
10

80
85
7
5
4
4
8
8

1

1
3
3

UNIT

MHz
ns
ns
ns
ns
ns
ns

t All typical values are at VCC = 5 V. TA = 25°C.
*fmax (with feedbackl =
•
tsu

1

+ tpd (ClK to

Q)

• f max (without feedbackl =

tw high

1

+ tw low

.

programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5762.

2-50

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TlBPAl16lB·12M, TIBPAl16R4·12M, TIBPAl16R6·12M, TIBPAl16RB·12M
TIBPAl 16lB·1 DC, TIBPAl 16R4·1 DC, TIBPAl 16R6·' DC, TIBPAl 16RB·1 DC
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS
preload procedure for registered outputs (see Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state
to be tested without having to step through the entire state-machine sequence. Each register is preloaded
individually by following the steps given below.
Step
Step
Step
Step

1.
2.
3.
4.

With Vee at 5 volts and Pin 1 at VIL. raise Pin 11 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse Pin 1. clocking in preload data.
Remove output voltage. then lower Pin 11 to VIL. Preload can be verified by observing
the voltage level at the output pin.

preload waveforms (see Note 3)

PIN 11

---I

~----v'...
VIL

~td-1

jf-tsu--l

M-tw~

j+-Id ---.I

'ii

PIN 1

I

I
I

1'-..-_-_-...;1_-_-.;..1_-_-_-_-_-_-_

VIH

-

VIL

:
I

I
I

I

I
I

------.~
REGiSTERED 110

I

~

I
I
I

~,.-O-U-TP-U-T-- VOH
INPUT

~

_ _ _ _ _ _ _J

VIL

- - - - - VOL

NOTE 3: td = tsu = tw = 100 ns to 1000 ns.
VIHH = 10.25 V to 10.75 V.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-51

TIBPAl16lB·12M, TIBPAl16R4·12M, TIBPAl16R6·12M, TIBPAl16RB·12M
TIBPAl 16lB·1 DC, TIBPAl 16R4·1 DC, TlBPAl 16R6·1 DC, TlBPAl 16RB·1 DC
HIGH·PERFORMANCE IMPACTTMPAL@ CIRCUITS
PARAMETER MEASUREMENT INFORMATION
5V
Sl

~
Rl

FROM OUTPUT _ ...........~~~_ TEST
UNDER TEST
POINT
CL
(See Note A)

IE

R2

LOAD CIRCUIT FOR
THREE·STATE OUTPUTS

C

./.
3.5 V
TIMING
T,1.5V
INPUT _ _ _ _U - - - - - - 0.3 V
\4-th-+t
I4- t su-+\
1
DATA
~-;;;;3.5V
INPUT
1.5V
~
0.3V

...
&»
&»

rn
::T

J

CD
CD

...

(II

---3.5V

HIGH-LEVEL
PULSE

1 5 V
15 V
~
.
.

Lt ---'!1

I·

15 V
1 5 V
~
.
.
I

LOW·LEVEL
PULSE·

.Ji,1.5 V

\1-:;; -; -

----"
tpd

I

14
l . 5V

1

tpd
OUT-OF·PHASE
OUTPUT
(See Note D)

14

- - 3.5 V
0.3 V

.1

tpd

1,-_..;1_---.:+ - -

:f

IN-PHASE
OUTPUT

VOLTAGE WAVEFORMS
PULSE DURATIONS

1.

14.1

~

I

E

14

.1

1.1

'\.1.5 V
.

VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES

OUTPUT
CONTROL
!low-level
enabling)

~3.5V
1.5 V
ten -+I

VOL

tpd

.

14-

I!

-1- - - - -- 0.3
~ 14-- tdis

II

V

=3.3 V

WAVEFORM1~1.5V
,
.c--VOL-f,0.5V

I

Sl CLOSED

(See Note B)

--VOL

1.5 V
I

1

VOH

p.vVOH
.

3.5V

- - --0.3V

VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES

INPUT

0.3 V

w

ten.-.t

I

j+-

-+I

-

__ ..Jt_
-"X -

14- tdis T.

VOL

~

WAVEFORM 2
S10PEN.
(See Note B)

I

I _ _ _ t.-VOH
-

1.5 V

-

LVOH-0.5 V
=0 V

VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten. 5 pF for tdis'
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR s 1 MHz. tr = tf = 2 ns. duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs. switch S 1 is closed.

FIGURE 1

2-52

TEXAS

~

INSTRUMENlS
,POST OFFICE BOX 656012 • DALLAS, TEXAS 75265

TIBPAL 16R4·1 DC, TlBPAL 16R6·1 DC, TIBPAL 16R8·1 DC
HIGH·PERFORMANCE IMPACfYMPAL® CIRCUITS
metastable characteristics for TIBPAL 16R4·10C, TIBPAL 16R6·10C, and TIBPAL 16R8·10C
At some point in every system designer's career, he or she is faced with the problem of synchronizing
two digital signals operating at two different frequencies. This problem is typically overcome by
synchronizing one of the signals to the local clock through use of a flip-flop. However, this solution presents
an awkward dilemna since the setup and hold time specifications associated with the flip-flop are sure
to be violated. The metastable characteristics of the flip-flop can influence overall system reliability.
Whenever the setup and hold times of a flip-flop are violated, its output response becomes uncertain and
is said to be in the metastable state if the output hangs up in the region between V,l and V,H. This metastable
condition lasts until the flip-flop falls into one of its two stable states, which takes longer than the specified
maximum propagation delay time (ClK to Q max).
From a system engineering standpoint, a designer cannot use the specified data sheet maximum for
propagation delay time when using the flip-flop as a data synchronizer - how long to wait after the specified
data sheet maximum must be known before using the data in order to guarantee reliable system operation.
The circuit shown in Figure 2 can be used to evaluate MTBF (Mean Time Between Failure) and ~t for a
selected flip-flop. Whenever the Q output of the DUT is between 0.8 V and 2 V, the comparators are in
opposite states. When the Q output of the DUT is higher than 2 V or lower than 0.8 V, the comparators
are at the same logic level. The outputs of the two comparators are sampled a selected time (~t) after
SClK. The exclusive OR gate detects the occurrence of a failure and increments the failure counter.
NOISE
GENERATOR

... -

:

DATA
IN

OUT
----,

10

VIH

I

H .........-t

1-----f1D

I

I

/--i>+

II)

CD
CD

.r:.
en

...

CO
CO

C

C1

I

I

Vil
COMPARATOR

I

SClK-------iH>C1

MTBF
COUNTER

COMPARATOR

...

:
I

I _____ JI
L
SClK

+

4 1 - - - - - - - - - - - - - - - -______- - - - - - 1

FIGURE 2. METASTABLE EVALUATION TEST CIRCUIT
In order to maximize the possibility of forcing the DUT into a metastable state, the input data signal is
applied so that it always violates the setup and hold time. This condition is illustrated in the timing diagram
in Figure 3. Any other relationship of SClK to data will provide less chance for the device to enter into
the metastable state.

-

DATA
SClK
SClK + 41

-

•I
•I
-----1-'__~.:-------..,----~'--j.r--I

I

I

~M~

MTBF _

I

~M~

TIME (SEC)
# FAILURES

I ree

- 4t - ClK TO Q (MAXI

FIGURE 3. TIMING DIAGRAM

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-53

TIBPAL16R4-1 DC, TIBPAL 16R6-1 DC, TlBPAL16R8-1 DC
HIGH-PERFORMANCE IMPACP'PAl@ CIRCUITS

By using the described test circuit, MTBF can be determined for several different values of ll.t (see Figure 2).
Plotting this information on semilog paper demonstrates the metastable characteristics of the selected
flip-flop. Figure 4 shows the results for the TIBPAL16'-10 operating at 1 MHz.
109
-lOy.
108
-ly.
107
- - 1 rna
106 --lwk
~
5
"III 10
- 1 day
I-

::E 104

"...
0

•

- - 1 hr
103
10 2 - l m i "
10 1

C

....

I»
I»

At (nsl

FIGURE 4. METASTABLE CHARACTERISTICS

rn

:r

From the data taken in the above experiment, an equation can be derived for the metastable characteristics
at other clock frequencies.

CD
CD

....en

The metastable equation:

MiBF = fSClK x fdata x C1 e (-C2 x at)

The constants C1 and C2 describe the metastable characteristics of the device. From the experimental
data, these constants can be solved for: C1 = 9.15 x 10~7 and C2 = 0.959
Therefore
M;BF

= fSClK

x fdata x 9.159 x 10- 7 e (-0.959 x at)

definition of variables
OUT (Device Under Test): The OUT is a 10-ns registered PAL programmed with the'equation Q : = D.
MTBF (Mean Time Between Failures): The average time (s) between metastable occurrences that cause
a violation of the device specifications.
fSClK (system clock frequency): Actual clock frequency for the OUT.
fdata (data frequencyi: Actual data frequency for a specified input to the OUT.
C1: Calculated constant that defines the magnitude of the curve.
C2: Calculated constant that defines the slope of the curve.
trec (metastability recovery time): Minimum time required to guarantee recovery from metastability, at
a given MTBF failure rate. trec = ll.t - tpd (ClK to Q, max)
ll.t: The time difference (ns) from when the synchronizing flip-flop is clocked to when its output is sampled.
The test described above has shown the metastable characteristics of the TIBPAl 16R4/R6/R8-1 0 series.
For additional information on metastable characteristics of Texas Instruments logic circuits, please refer
to TI Applications publication HSDAA004, "Metastable Characteristics, Design Considerations for AlS,
AS, and lS Circuits."

2-54

TEXAS

~

INSTRUMENTS
POST OfFICE BOX 655012 • OAl,.lAS, TEXAS 75265

TIBPAL 16L8·1 DC, TlBPAL 16R4·1 DC, TlBPAL 16R6·1 DC, TlBPAL 16R8·1 DC
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
FREE·AIR TEMPERATURE
9

..

8

.,
I

E

.

9

VCC _ 5 V
1 OUTPUT SWITCHING

c

i=

PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE

7

.

kl/o

R1 - 200 0 -'tPHl
to 0,1/0)
R2 - 391 0
Cl - 50 pF
See Figure 1 -t-----I;"....,=+-,,.....'F----1f----1

c

.,
I

E

.

>
'ii

6r-~--+--r-+--f___+--r~

c

o

.'."
....'"
0

.~

5

11........::::::j:=::l=:::::::p~t"""'=--t--t---j

!2

5

!2

II..

II..

4

4
3L-~

tpHl II,I/? to 0,1/0)

!'.....

r--

tPlH~
I

6

Q

c

[

7

i=

>

~

8

R1 - 200 0, See Figure 1
R2 - 3900, TA - 25°C
Cl-50pF

__-L__~~__- L__~~L-~

3

r--

--

4.5

-75 -50 -25
0
25
50
75 100 125
TA-Free-Air Temperature- °C

tpHl (ClK to Q~

tPlH

4.75

5

(cJ

5.25

VCC-Supply Voltage-V

FIGURE 5

FIGURE 6

en

+or
to Q ) -

Q)
Q)

.c
en
5.5

ca
ca

+or

C

PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
11

..
c

.,I

9

i=

8

>
'ii

7

E

.

Q

VCC = 5 V
R1 - 2000
R2-3900
CL - 50 pF
See Figure 1

10

----

TA - 25°C_

c

o!

6

!2

5

....'"

f.--::

II..

:::--r ~ \t'~\..

\\,\1

0\0

-

'

0 \10'

\t'\..~

\\~

IlCL~tO~1

-::TI .

4

tPlH (ClK to QI

I

3

1

2

3

4

5

6

7

8

Number of Outputs Switching

FIGURE 7

TEXAS

~

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-55

TIBPAL16L8·1 DC, TIBPAL16R4·1 DC, TIBPAL16R6·1 DC, TIBPAL16R8·1 DC
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
FREQUENCY
8-BIT COUNTER MODE

PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE

900
VCC - 5 V. TA - 25·C
16 R1 - 200 0. 1 Output Switching -=1;...-----1
R2 - 3 9 0 0 b
0'\
c
O~~-b.,e:::...-+---I
I 14 See Figure 1

.

I

...0

II

~~70~"c--;;,Fc
~"

E

j::

E
C

...
C»
C»

en

::r
(1)

...en
(1)

>-

12

.!!
~ 10

!'"

£

!

8

I-'
.......... 1-'

..........
:.-- ~
~

TA - O·C

:.--

I

rr

:. 700 -TA - 25·C
I

6

I I I

f

4

2

5V

800

;

0

D

~I

is

c

"j

VCC

TA
600
0

100
200
300
400
500
CL -Load Capacitance-pF

600

I-

F-Frequency-MHz
FIGURE 9

,

SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE

180r--.--.-.--.~-r-~-.r--'

UNPROGRAMMED DEVICE

170r-~-~-+---Ir--+-+---Ir-~

~160r--+-~~~~-~-+---I-~
I

i150r-~~d-~~~~-r-+---I-~
::I

(.) 140

I--+-="'t-o=-P"d~rr""-:-+---I-~

~130r--+-~~~~~~~~~~~
I

~120r--+-~-+---I~~~~~~d

100~~_~_~~_~_~~~~

-~-~-~

0
~
~
~ 1001~
TA-Free-Air Temperature-·C
FIGURE 10

2·56

~

1Q

1

FIGURE 8

i

---

.... 1-'

TEXAS ,.,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265

40

100

TIBPAL 16L8·15M, TIBPAL 16R4·15M, TIBPAL 16R6·15M, TIBPAL 16R8·15M
TlBPAL 16L8·12C, TIBPAL 16R4·12C, TIBPAL 16R6·12C, TIBPAL 16R8·12C
HIGH· PERFORMANCE IMPACT'MPAL® CIRCUITS
JANUARY 1986-REVISED DECEMBER 1987

•

•

TIBPAL 16LB'
M SUFFIX ••• J PACKAGE
C SUFFIX ••. J OR N PACKAGE

High-Performance Operation
Propagation Delay
M Suffix ... 12 ns Max
C Suffix ... 15 ns Max

(TOPVIEWI

Vee

Functionally Equivalent, but Faster than
PAL16L8B, PAL16R4B, PAL16R6B, and
PAL16R8B

0

•

Power-Up Clear on Registered Devices
IAII Registered Outputs are Set Low)

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DiPs

•

1/0
1/0
1/0
1/0
1/0

I/O
0

I
GND

II
...

Dependable Texas Instruments Quality and
Reliability
TlBPAL 16LB'

DEVICE

INPUTS

PAL16LB

10

3·STATE

REGISTERED

a OUTPUTS

QOUTPUTS

2

0

MSUFFIX •.• FK PACKAGE

en

C SUFFIX ..• FN PACKAGE

1/0 PORTS

CD
CD

(TOPVIEWI
6

PAL16R4

8

0

4 (3-sto'e)

PAL16R6

8

a

6 (3-state)

2

PAL16R8

8

0

8 (3-sto'o)

0

..c
en
as
as

U
U
_ _ _ >0

4

3

2

description
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices.
These IMPACT'" circuits combine the latest
Advanced Low-Power Schottky t technology
with proven titanium-tungsten fuses to provide
reliable, high-performance substitutes for
conventional TTL logic. Their easy
programmability allows for quick design of
"custom" functions and typically results in a
more compact circuit board. In addition, chip
carriers are available for further reduction in
board space.

...

1 2019

4

18

I/O

5

17

110

6

16

I/O
I/O
I/O

"IS
14

8

C

9 1011 1213

-0-00
Z

C,!)

'"

Pin assignments in operating mode

The TIBPAL 16' M series is characterized for
operation over the full military temperature range
of - 55°C to 125°C. The TIBPAL 16' C series
is characterized for operation from 0 °C to 75°C.

IMPACT'" is a trademark of Texas Instruments Incorporated.
PAL'" is a registered trademark of Monolithic Memories Inc.
t'ntegrated Schottky-Barrier diode-clemped transistor is patented
by Texas Instruments, U.S. Patent Number 3,463,975.

PRODUCTION DATA da...m.......tain informad...
.urrent .. 01 publi.atioo data. P..d......00.rll ta
lpacificatlHa par do. term••f T.... Instrum....
standard warranty. Praolut:tian p......ing da....t
.......ri/y i..- - . 01 .11 poromatarl.

Copyright @ 1986, Texas Instruments Incorporated

TEXAS .."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-57

TIBPAL 16R4·15M, TIBPAL 16R6·15M, TIBPAL 16R8·15M
TIBPAL 16R4·12C, T1BPAL 16R6·12C, T1BPAL 16R8·12C .
HIGH·PERFORMANCE IMPACfTMPAL® CIRCUITS
TISPAL16R4'
M SUFFIX •.. J PACKAGE
C SUFFIX •.. J OR N PACKAGE

nBPAl16R4'
M SUFFIX ... FK PACKAGE
C SUFFIX ..• FN PACKAGE

(TOP VIEW)

(TOP VIEW)

elK

>£

Vee

u

--' uo
_ _ U>::;,

I/O

GND

'-l..._---Ir"

I/O
Q
Q

4

5

18
17

I/O
Q

Q

6

16

Q

Q

7

15

Q

I/O
I/O

8

14

Q

3

2

I 2019

9 1011 12 13

OE

-

~I~

gg

<.:)

TIBPAL l6RO'
M SUFFIX ..• FK PACKAGE
C SUFFIX ..• FN PACKAGE
(TOP VIEW)

TIBPAl16R6'
M SUFFIX ... J PACKAGE
C SUFFIX ..• J OR N PACKAGE
(TOP VIEW)

C

...
I»
I»

fJ)

elK

::r

>£

Vee

CD
CD

...en

u

--' UO
_ _ U>::;,

I/O
Q

3

Q

4
5

Q

6

Q

2

1 2019

Q

Q

I
GND

8

I/O
........_ - - - - ' r "

18

Q

17
16

Q

15

Q

14

Q

Q

9 1011 1213

BE

-

~I~

ga

<.:)

TIBPAL 10RS'
M SUFFIX .•. J PACKAGE
C SUFFIX •.. J OR N PACKAGE

TIBPAL 16RS'
M SUFFIX •.. FK PACKAGE
C SUFFIX.•. FN PACKAGE

(TOP VIEW)

(TOP VIEW)

elK

~ tl
__ u>o

Vee
Q

3

Q

2

1 2019

Q

4

18

Q

5

17

Q

6

16
15
14

Q
Q

I
GND

........_ _ _r"

8

Q

9 1011 1213

BE

- Qlw
zo a
<.:)

Pin assignments in operating mode

2·58

TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

a

TIBPAL 16LB·15M, TIBPAL 16LB·12C, TlBPAL 16R4·15M, TlBPAL 16R4·12C
HIGH·PERFORMANCE IMPACTTMPAL@ CIRCUITS
functional block diagrams (positive logic)
'PAL1SL8

&

EN .. 1

7

'Vk>-----o

32X64

k>-----o

0-.-.......-1/0

.......-I/O

P-~

k>-...........- I/O

II
...

k>-.-t"'+--I/O
k>-e+"''''-I/O

U)

4)
4)

..c
en

...

6

CU
CU

o

'PAL16R4

J EN2
-L C1

DE
ClK
&

32X 64

~

'V

,i

rt-

f>+-

'V

-

10

r+r+-

+

8

1=0

..1

r-+

r+~

~

a
~

~

>

~

a

r+-

t--

a

2'V

a
~

EN

..1

'V

r-+-

~

r+-

f-J'
~~

"'\
"'\

....

"" ---"'\

I/O
I/O
I/O
I/O

,

4

rv denotes

fused inputs

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265

2-59

TIBPAL 16R6·15M, TIBPAL 16R6·12C, TIBPAL 16RB·15M, TIBPAL 16RB·12C
HIGH·PERFORMANCE IMPACP'PAL® CIRCUITS
functional block diagrams (positive logic)
'PAl16R6

OE----~------------------~~--_,

CLK .....--------------------------~
&

32X64

a

16

E

r--;-----1~l_Q

C

C»
1'+
C»

.........,-- I/O

J----2:r-~

t/)

::r

P--ed--4....--t--

CD
CD

I/O

1'+

en

'PAL 16Ra

OE
ClK

a

;'1

Q
Q
Q

8

16

Q
Q
Q

Q
Q

rv denotes

2·60

fused inputs

TEXAS •
INSTRUMENTS
POST OFFICE BOX 6550.12 • DALLAS. TEXAS 75266

TlOPAL 16LB·15M, TlOPAL 16RB·12C
HIGH·PERFORMANCE IMPACT™PAL® CIRCUITS

INPUT LINES
P RODUCT,

LINES

0

4

8

12

16

20

24

28

31
~

····
·
~
··
·
··•
·
··••
·
··••
0

II- >---

1
....

'- >---

(19)

o

I)-

8

I--

h

f.--/

1

I

(18)

--V

I

1/0

(3) 15
')f

16

1

}--

....

(17)

1/0

24

...
Q)
Q)

-

(4) 23

-

J....

(16)

1

(15)

1'"

(14)

J

(13)

1

(12)

I/O

.c
en
ca
ca

...

Q

-

(5) 31

32

f.--/

•

V

1/0

(6) 39
-'-"

"

40

I (7)

··•
·
··
·
··
·

-

r-)-}--

47
')f

48

I (8)

~

h
~

....

1/0

~

55
')f

,.....

56

I

1/0

b1 - - f.--/

r:=d(l
I-

(!!. 63
....

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

v

o

(11)

2·61

'
I

TIBPAL 16R4·15M, TIBPAL 16R4·12C
HIGH·PERFORMANCE IMPACT TMPAL® CIRCUITS

INPUT LINES

4

LIN

8

12

16

20

24

28

··••
•
·
~
0

31
>--

J

'-'

~

I----

8

E

••
••
••

i--

16

l--

••
••

·

1----:>I----

10

1

1

(18) I

~1

f.--"

(3) 15

(19) I

tbJ;
10

I"
r:J
""

10

Q

C1

(4) 23
24

••
•
••

·

D-

32

>->-->

•

·••••

40

Q

v

(15)

I--.

•
•
•
47

·
·
·•••

b
~>tt; .

(14)

1--..

C1

I---

1

(13)

J

(12)

48

~

h.

!--./

••
55

Vl

Q

1/0

;:;;

·•••

56

I-<

••

I-

9) 63
I (

2-62

~

r.:J.

C1

39
1(6),>[

1(8)

Q

C1

(5) 31

1(7)

tbJ;

:CW 16 )

.. 'I

1/0

L---

>-

f-f--

="24

.

-

0
0
0
0
0

>-

\---

,

0
0
0
0
0
0

"

\---t>)--

\--'-

(6) 39

CI)
CI)

.c

'CI)

CU

~

~

(16)

~

(15)

Q

CU

C

C

-vo-

a

Cl

I-------'

40

c

~

Cl

(5) 31
32

~
Cl

>---

(4)~23

1.:1
(17)
Q
v

}--

0
0
0
0
0
0

~
::::>t6];
~

~) Q

}--

Cl

}--

(7) 47
48
0
00
0
0
0

r.:J....

(13)

Q

Cl

55
(8) '>f
56

I-~

0
0
0
0
0
0

II-"

J

(12)

....

1/0

~

~

L.

1

~)

TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TeXAS 75265

2·63

,
,

TIBPAL 16R8·15M, TIBPAL 16R8·12C
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS

ClKillt>

.

INPUT LINES

PR

l?~E~CT '0

4

8

12

16

20

24

28

.

I

31

0

•••
••
•

~

>-

Elrl'8
••
••
••

-

'0+

m

tn

··••
·

::J

'"";:1

{181

Rv

{171

~

>-;:t

{161

Y;

'"";:1

{151

Rv

{141

~

v

Q

C1

r---I
I----

~::>)-----i

Y;

Q

C1

{41 23

-'-

Q

C1

-p-

{31 15
X
16

o
m

n? "

24

•••
•
••

CD
CD

0+
(I)

~

-

.>-

t----'

C1

{51 31
32

I----"

••
•
•

·

~ Q

_D-

v

Q

C1

{61 39

~

40

••
•
•
47

I----

·

I---I----<

{71 X

~

•

··••
·•••

;:-

{81 55
X
56

~

·•

'

I---'

{91 63
X

>-;:t

...

{131

POST OFFICE BOX 665012 • DALlAS. TEXAS 76266

Q

C1

C/Y;S ""
C1

~I

TEXAS •
INSTRUMENTS

Q

C1

:=/n

48

'2-64

>-

Q

TlBPAL 16L8·15M. TIBPAL 16R4·15M. TIBPAL 16R6·15M. TIBPAL 16R8·15M
TIBPAL 16L8·12C. TIBPAL 16R4·12C. TIBPAL 16R6·12C. TIBPAL 16R8·12C
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: M suffix. . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°e
e suffix ................. _ ............ ooe to 75°e
Storage temperature range ......................................... - 65°C to 150 0 e
NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions (see Note 2)
-15M

PARAMETER
Vec
VIH
Vil
10H

MIN
4.5
2

Supply voltage
High-level input voltage
low-level input voltage
High-level output current

Low-level output current
10l
fclock Clock frequency

NOM
5

I

Pulse duration, clock (see Note2)

tsu
th
TA

Hold time, input or feedback after ClK1
Operating free-air temperature

I

MIN
4.5
2

12
50

10
15
0
-55

0
0

9

High
low

Setup time, input or feedback before ClK1

NOM
5

MAX
5.25
5.5
0.8
-3.2
24

0
7
8
10

0

tw

-12C
MAX
5.5
5.5
0.8
-2

125

62

UNIT

~
:

V
V
V
mA
mA
MHz

...

.s:.

ns

en

...

ns

«J
«J

ns
75

o

°c

NOTE 2: The total clock period of elK high and ClK low must not exceed clock frequency, fclock. Minimum pulse durations specified
are only for ClK high or ClK low, but not for both simultaneously.
.

electrical characteristics, over recommended operating free-air

VCC = MIN,
VCC - MIN,

VIK
VOH
VOL
10ZH
10Zl

Outputs
110 ports
Outputs
110 ports

=

II

10H - MAX

= MIN,

10l

= MAX

VCC

= MAX,

Vo

= 2.7V

VCC

= MAX,

Vo

= 0.4 V
= 5.5 V

II

VCC

= MAX,

VI

IIH

Vec
VCC

10§

= MAX,
= MAX,
= MAX,
= MAX,

VI

III

Vce
VCC
VI = OV,

ICC

MIN

TYP*

2.4

3.3

-18mA

VCC

= 2.7 V
= 0.4 V
Vo = 2.25 V

range

-15M

TEST CONDlTlONSt

PARAMETER

temp~rature

0.35

Pin 1, 11
All others
Pin 1, 11
All others

VI

170

MIN

TYP*

2.4

3.3

0.5

0.35

MAX
-1.5

20
100
-20
-250

0.2
0.1
50
20
-0.2

0.1
0.1
20
20
-0.2

220

-30
170

UNIT
V
V

0.5

20
100
-20
-250

-125

-30

Outputs Open

-12C
MAX
-1.5

V
~A
~A

mA
~

mA

-125

mA

200

mA

tFor conditions shown as MIN or MAX use the appropriate value specified under recommended operating conditions.
*AII typical values are at Vec = 5 V, TA = 25°e.
§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265

2-65

I

.

TIBPAL 16L8·15M, TlBPAL 16R4·1.5M, TIBPAL 16R6·15M, TIBPAL 16R8·15M
TIBPAL 16L8·12C, TIBPAL 16R4·12C, TIBPAL16R6·12C, TIBPAL 16R8·12C
HIGH·PERFORMANCE IMPACT'MPAL® CIRCUITS
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER

FROM

TO

1,1/0
ClKi
DE.
DEi
1,1/0
1,1/0

0,1/0

TEST CONDITIONS

f max ;
tpd t
tpd
ten
~is

ten
tdis

t All

-15M
MIN

-12C

TVpt

MAX

8
7
B
7
8
8

15

50
Q

Rl = 5000,
Cl = 50 pF

Q
Q

See !'Iote 3

0,1/0
0,1/0

=

MIN

TVPt

MAX

8
7
B
7
8
8

12

62
12
12
12
15
15

UNIT
MHz
ns

10

ns

10

ns

10

ns

12

ns

12

ns

=

typical values are at VCC
5 V, TA
25 ·C.
Maximum operating frequency and propagation delay are specified for the basic building block. When using feedback, limits must be
calculated accordingly.
NOTE 3: Load circuits and voltage waveform,s are shown in Section 1.

'2 ;
C

programming information

OJ
r+
OJ

en
:T
CD
CD

r+

en

2-66

'

Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers,
Complete programming specifications. algorithms. and the latest information on hardware. software. and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available. upon request. from the nearest TI field sales office. local
authorized TI distributor. or by calling Texas Instruments at (214) 997-5762.

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265

TIBPAL 16L8·20M, TIBPAL 16R4·20M, TIBPAL 16R6·20M, TIBPAL 16R8·20M
TIBPAL 16L8·15C, TIBPAL 16R4·15C, TIBPAL 16R6·15C, TIBPAL 16R8·15C
HIGH·PERFORMANCE IMPACTTM PAL@ CIRCUITS
FEBRUARY 1

•

High·Performance Operation
Propagation Delay
M Suffix ... 20 ns Max
C Suffix ... 15 ns Max

•

Functionally Equivalent, but Faster than
PAL16L8A,PAL16R4A, PAL16R6A, and
PAL16R8A

•
•

TIBPAl16la'
M SUFFIX .•. J PACKAGE
C SUFFIX •.. J OR N PACKAGE
{TOP VIEW)

Vee
o
110

110

Po.wer·Up Clear on Registered Devices
IAII Registered Outputs are Set Low)

1/0

110
110

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DiPs

110

o
GND -"'_--Jr

DEVICE
PAL16lB
PAL16R4
PAL16R6
PAL16RB

3-STATE

INPUTS

o OUTPUTS

10
B
B
B

2
0
0
0

REGISTERED
1/0 PORTS
Q OUTPUTS
0
6
4 (3-state)
4
6 (3-state)
2
a (3-state)
0

TlBPAl16la'
M SUFFIX •.. FH OR FK PACKAGE
C SUFFIX .•. FN PACKAGE
(TOP VIEW)

...
U)

CP
CP

U

.c

u
___ >0

description

3

These programmable array logic devices feature
high speed and a choice of either standard or
half-power devices. They combine Advanced
Low-Power Schottky t technology with proven
titanium-tungsten fuses, These devices will
provide reliable, high-performance substitutes
for conventional TTL ipgic. Their easy
programmability allows for quick deSign of
"custom" functions and typically result in a
more compact circuit board. In addition, chip
carriers are available for further reduction in
board space.

2

o
as
as

...

1 20 19
18

5

17

6
7

16
15
14

8

Q

9 1011 12 13

The PAL 16' M series is characterized for
operation over the full military temperature range
of -55°C to 125°C. The PAL16' e series is
characterized for operation from ooe to 70°C.

tlntegrated Schottky-Barrier diode-clamped transistor is patented by Texas Instruments, U.S. Patent Number 3,463,975.
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories Inc.

PRODUCTION DATA do••_
.ontll. information
••rront "' 01 publication date. P......... canform to
.paciljcatio•• per the tarOll 01 T.... Iistruments

=i~·i:'':.7.;

=-::; 1Ir=~:..~

not

Copyright © 1984, Texas Instruments Incorporated

TEXAS ",

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75285

2-67

TlBPAL 16R4·20M. TIBPAL 16R6·20M. TIBPAL 16RB·20M
TIBPAL 16R4·15C. TIBPAL 16R6·15C. TIBPAL 16RB·15C
HIGH·PERFORMANCE IMPACTTM PAl® CIRCUITS
TIBPAL 16R4'
M SUFFIX ... J PACKAGE
C SUFFIX ..• J OR N PACKAGE

TIBPAL 16R4'
M SUFFIX .•• FH OR FK PACKAGE
C SUFFIX ... FN PACKAGE

(TOP VIEW)

(TOP VIEW)

~
_ _ U>:::,

tlo

Vee

eLK

I/O

3

1/0

2

1 20 19

Q
Q

17

Q

16

18

Q

E
..
..
c

S»
S»

en
-:r
CD
CD

15

1/0
1/0
GND ""1...._---.Jr- OE

14

TIBPAL 16R6'
M SUFFIX .•. J PACKAGE
C SUFFIX ... J OR N PACKAGE

TIBPAL 16R4'
M SUFFIX ... FH OR FK PACKAGE
C SUFFIX ..• FN PACKAGE

(TOP VIEW)

(TOP VIEW)

Vee

eLK
I

1/0
3

Q
Q
Q
Q
Q
Q

en

1 20 19

TIBPAL 16RS'
M SUFFIX ... FH OR FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOPV'IEW)

TIBPAL 16RS'
M SUFFIX ... J PACKAGE
C SUFFIX ... J OR N PACKAGE
(TOP VIEW)

etK

2

Vee
Q

3

Q

1 20 19
18

Q

17

Q

16

Q

15

Q

14

Q

9 1011 1213

GND ........_---l-OE

2-68

2

Q

TEXAS ."

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TIBPAL 16L8·20M, TIBPAL 16L8·15C, TIBPAL 16R4·20M, TIBPAL 16R4·15C
HIGH·PERFORMANCE IMPACpM PAL@ CIRCUITS
functional block diagrams (positive logic)
'PAL 16L8

EN ;"1

&

32X 64

\/b-----o
b-----o
b-......-4.....-1/0

10

16

t')....a.I..........- I/O

b-.-+..........-I/O

6

h-~...._ -

II

I/O

b-.-+........-I/O

en

~

b-~-4...-1/0

CI)

.c
en

6

...
CO
CO

C

'PAL 16R4

OE-----------------~
CLK------------------~
0

0

I>

8

0

16
0

4
4

I/O
I/O
I/O
I/O

4
-

denotes fused inputs

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

2·69

TlBPAL 16R6·20M, TIBPAL 16R6·15C, TIBPAL 16R8·20M, TIBPAL 16R8·15C
HIGH·PERFORMANCE IMPACT™ PAL@! CIRCUITS
functional block diagrams (positive logic)
'PAl16R6

DE

]~N2

r, Cl

ClK
&
32X64

:>1

~

1=0 2

P-

---...
---...
---...
---...
---...

R-

---...

10

Rr--:--:-

II

[>

r-i!- - R-

P-

~
~

2.,..
io..--

-

I - - EN :>1

P-

\l

....
-

p

I--

rz,....

p

a
a

a
a
a
a

I/O
I/O

2

-

.....

6

'PAl16R8

~-----------------------d~---'

ClK--------------------------~

&
32 X 64

8

r~:>;;1-r-i=O~'_--- a
r----t----1-~-a

t---r---1--':l--a
t---r---1--':l--a
r----r---1--.:l--a
8
-

2-70

denotes fused inputs

TEXAS ."

INSTRUMENTS
POST OFFICE BOx 855012 • DALLAS. TEXAS 75285

TIBPAl16lB·20M, TIBPAl16lB·15C
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS

I (1)

PRODUCT
LINES '0
0

INPUT LINES

4

8

12

16

20

24

28

···
~
's
··
·
·
···•
··
·
··
·
···
·•••
·
·••
·•

3"

~v-J

119)

o

~

1

~
~

118)

v

110

~

(3) 15

-

16

1

f-

(17)

v

~

110

-

(4) 23

-

24

:::>

J

116)

1

(15)

1

114)

1

(13)

1

(12)

110

r--

(5) 31

r

32

t-<

v

110

.....

(6) 39

X

40

f---' ~

.--

110

.--

(7) 41

X
48

.--

.-- ~

(8) 55

v

110

A

)l

56

(9)

v

r--

>-

v

o

.-

~

r--

TEXAS ~

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

(11)

2-71

TIBPAl16R4·20M, TIBPAL16R4·15C
HIGH·PERFORMANCE IMPACTTM PAL@ CIRCUITS
CLK~
PRODUCT
LINES '0
0

,

INPUT LINES

,

4

8

12

16

20

24

28

3"

·•
·•
"t--

1

f-'

v

(191

J

I/O

(21 .....

'8
••
••

(31

1

-,

·
··•
·
·•••

v

>--

15

(181

I

I/O

-

16

Q
>---- >- ~,:!Im
C1

>-----<

(41 23

24

~

r.Jv

~

>-;::L (151 Q

/~

>-;::L (141 Q

>---->-

•

>---'

C1

(51 31

..:.:

32

••
••
•

·

f-pf-

....

-

f-

40

•

(7l

··••
·•••
·•

ff--

ff-

47

v

C1

X

48

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l>-

-

56

1
v

r-

55
1(81 X

~

••
••

·

>----....

63
1(91 X

2-72

v

C1

(61 39

I

(161 Q

TEXAS

..If

INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TEXAS 75265

(131

I
(121

1

I/O

I/O

~ OE

TIBPAL 16R6·20M, TlBPAL 16R6·15C
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS

ClK

!1!-t>---PRODUCT,
LINES
0

._----------------------,
INPUT LINES

,

4

8

12

16

20

24

28

0

31

>-------c

0
0
0
0
0
0

'--...
-/

v

7

(2~

~

f----'

0
0
0
0
0
0

(31

1

-

>-,/-

I

tr

3 n.

C1

15

1191

I/O

Q

16
0
0
0
0
0
0

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f-----"

41 23

(X

24

->~

(51 31
32

~

0
0
0
0
0
0

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v

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~
~

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(141

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v

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40

:t>~

0
0
0
0
0
0

-

f0-

(71 47

X

48

....

Q

C1

1---1

0
0

••

·
0

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66
66
0

-

•
•
0

>----

63

>--

0

....

U)

;

CD

C1

~ (151 Q

fo-p-

(61 39

(91

~

':!

I

C'CI

0
0
0
0
0
0

1(81

~

I.:J.
(171
-va- Q

·

v

Q

C1

1
v

(121

1'4""

I/O

OE

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265

2-73

TIBPAL 16R8·20M, TlBPAL 16R8·15C
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS

ClK

.!!!.t>
PRODUCT
LINES '0
0

D)

;tn

:::r

CD
CD

r+

fn

8

12

16

20

24

28

··
·•
~
··
·
·••••
(21

Ic

I

INPUT LINES
4

~

::>-

Q

f-------,

~D-

tJ;
0-->tJ;

I.:l (181 Q
r-vo-

C1

v

16

i-----'

•

>--;-'

23

IQ
~
v

C1

24

··•.·
·•••
·
·
··•
··•
·
··
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~-

f-------,

p-

)l

32

16 )

~

I.J

(15)

~

";:1

(14)

~

";::L

(13)Q

~

o--Pr--

39

v

Q

C1

40

(71

~

I.:l
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f-p-

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47

-

48

----1

-

>-

f---'

)l

56

t--

~

>:bh"e- '"
C1

A

TEXAS ",

INSIRUMENlS
POST OFFICE BOX 65501 i

..

DALLAS. TEXAS 76265

v

C1

f----<

(81 55

2-74

tJ;'3 ' '
C1

7

(31 15

(41

3"

~

TIBPAL 16L8·20M, TIBPAL 16R4·20M, TIBPAL 16R6·20M, TIBPAL 16R8·20M
TIBPAL 16L8·15C, TlBPAL 16R4·15C, TIBPAL 16R6·15C, TIBPAL 16R8·15C
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: M suffix. . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°e
e suffix .............................. ooe to 75°e
Storage temperature range .......................................... - 65 °e to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions

VCC
VIH

Supply voltage
High-level input voltage

Vil

low-level input voltage

IOH

High-level output current

15C

20M

PARAMETER

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5
5.5

4.5
2

5

5.25
5.5

V
V

0.8
-3.2

mA

2

0.8
-2

low-level output current
IOl
fclock Clock frequency

12
0

I High

tw

Pulse duration, clock (see Note 2)

tsu
th
TA

Satup time, input or feedback before ClKt

I low

Hold time, input or feedback after ClKt

40

0

V

24

mA

50

MHz

10
11

8
9

ns

20

15

ns

0
-55

Operating free-air temperature

UNIT

MIN

0
125

0

ns
70

°c

NOTE: 2. The total clock period of ClK high and ClK low must not exceed clock frequency, fclock. Minimum pulse durations specified
are only for ClK high or ClK low, but not for both simultaneously.

•
....
tI)

Q)
Q)

.c

en

....asas

C

programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 995-5762.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265

2-75

TIBPAL 16L8·20M, TIBPAL 16R4·20M, TIBPAL 16R6·20M, TIBPAL 16R8·20M
TIBPAL 16L8·15C, TlBPAL 16R4·15C, TIBPAL 16R6·15C, TIBPAL 16R8·15C
HIGH·PERFORMANCE IMPACpM PAL® CIRCUITS
electrical characteristics over recommended operating free·air temperature range
TEST CONDITIONSt

PARAMETER
VIK

Vcc
Vcc

VOH
Outputs
10ZH
10Zl

1/0 ports
Outputs
1/0 ports

Cit
(/'J

::T

CD
CD

....
U)

= MAX,

Vo

= 2.7

VCC

= MAX,

Vo

= 0.4 V

= MAX,
= MAX,

VCC

IlL

VCC - MAX,

10§

VCC
VCC
VI

= MAX,
= MAX,

=0

VI
VI

20M
TYpt

2.4

3.2

-18mA

IOH = MAX
10L - MAX

IIH

ICC

=

VCC

VCC

II

cD)

II

Vcc - MIN,

VOL

E

= MIN"
= MIN,

MIN

= 5.5
= 2.7

0.25

V

MIN

TYP*

2.4

3.3
0.35

0.4

MAX
-1.5
0.5

UNIT
V
V
V

20
100
-20

20
100
-20

-;150
0.2

-250

Pin 1, 11
All others

0.1

0.1

Pin 1, 11

50
20
-0.2

20
20
-0.2

rnA

-125

rnA

180

rnA

V

V

16C
MAX
-1.5

All others

VI "- 0.4 V
Vo = 2.25 V
Outputs Open

-30

-125
140

V

0.1

-30

190

140

p.A
p.A
rnA

p.A

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

*All typical values are at VCC = 5 V, TA = 25 ·C.

§The output conditions have been chosen to produce 8 current that closely approximates one half of the true short-circuit output current, lOS.

switching characteristics over recommended supply voltage and operating free·air temperature ranges
(unless otherwise noted)
PARAMETER

FROM

TO

1,1/0

0,1/0
Q

20M
TYpo

MAX

10
RL = 50011,
CL '" 50 pF,
See Note 3

TEST CONDITIONS

f max

tod
tpd
ten
tdis
ten
tdis

CLKt
OE!
OEt

Q

1,1/0

0,1/0
0,1/0

1,1/0

Q

MIN
40

UNIT

TYP*

MAX

20

10

ns

8

15

8

15
12

8
7

15

8

12

ns

15
20

10
15

ns

10

7
10

10

20

10

15

ns

*

All typical values are at VCC = 5 V, TA 25 ·C.
Note 3: Load circuits and voltage waveforms are shown in Section 1.

2·76

15C

TEXAS'.

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265

MIN
50

MHz
ns

ns

TIBPAL 16LB·30M, TIBPAL 16R4·30M, TIBPAL 16R6·30M, TIBPAL 16RB·30M
TIBPAL 16LB·25C, TIBPAL 16R4·25C, TIBPAL 16R6·25C, TIBPAL16RB·25C
LOW·POWER HIGH·PERFORMANCE IMPACT™PAl® CIRCUITS
FEBRUARY 1984-REVISED

•

High-Performance Operation
Propagation Delay
M Suffix ... 20 ns Max
C Suffix ... 15 ns Max

•

Functionally Equivalent, but Faster than
PAL16L8A. PAL16R4A, PAL16R6A.and
PAL16R8A

o

•

Power-Up Clear on Registered Devices
CAli Registered Outputs are Set Lowl

1/0
1/0

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

I/O
I/O

1987

TIBPAl16lS'
M SUFFIX .•• J PACKAGE
C SUFFIX ••• J OR N PACKAGE
(TOP VIEW)

Vee

I/O
I/O

o
GND-,.._ _~

OEVICE
PAL16LS
PAL16R4
PAL16R6
PAL16R8

3-STATE

INPUTS

o OUTPUTS

10
8

2
0
0
0

8
8

REGISTERED
I/O PORTS
Q OUTPUTS
0
6
4 (3-state)
4
6 (3-state)
2
8 (3-state)
0

II
...

TIBPAL 16L8'
M SUFFIX ••. FH OR FK PACKAGE
C SUFFIX •.. FN PACKAGE
(TOP VIEW)

en
CD
CD

.c

U

___ >0
u
description

3

These programmable array logic devices feature
high speed and a choice of either standard or
half-power devices. They combine Advanced
Low-Power Schottky t technology with proven
titanium-tungsten fuses. These devices will
provide reliable, high-performance substitutes
for conventional TTL logic. Their easy
programmability allows for quick design of
"custom" functions and typically result in a
more compact circuit board. In addition. chip
carriers are available for further reduction in
board space.

2

en

...coco

1 20 19

18

I

5

17

6

16
15

8

o

14

9 1011 1213

The PAL 16' M series is characterized for
operation over the full military temperature range
of -55°e to 125°e. The PAL16' e series is
characterized for operation from ooe to 70 oe.

tlntegrated Schottky-Barrier diode-clamped transistor is patented by Texas Instruments, U.S. Patent Number 3.463,975.
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories Inc.

PRODuCnoli DATA .......0011 cont.i. ,."....lIia.
••rnllll .s a' p••liclli•• Uta. Pr....cts coala.... 10
spscilicotitoa. par 1110 tor... of T.... lnotro..onto

=H~8{'::I~ =~ :.r:::~ nat

Copyright @ 1984. Texas Instruments Incorporated

TEXAS . "

INSIRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-77

TIBPAL16R4·30M, TIBPAL 16R6·30M, TIBPAL 16R8·30M
TlBPAL 16R4·25C, TIBPAL 16R6·25C, TIBPAL 16R8·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS
TIBPAL16R4'

TIBPAL 16R4'
M SUFFIX ••• J PACKAGE
C SUFFIX .•. J OR N PACKAGE

M SUFFIX, •• FH OR FK PACKAGE

ITOPVIEWI

ITOPVIEWI

elK

C SUFFIX ••• FN PACKAGE

~

Vee

U

..J U·o
__ u>;::,

1/0
1/0

3

2

1 20 19

Q

•
c

D)

r+

::r

5

17

Q

6

16

Q

7

15

1/0

8

I/O
GND "-l.._....;.;J.... OE

M SUFFIX .•• J PACKAGE
C SUFFIX ••• J OR N PACKAGE

TIBPAL 16R4'
M SUFFIX ... FH OR FK PACKAGE
C SUFFIX ... FN PACKAGE

ITOPVIEWI

ITOPVIEWI

TIBPAL 16R6'

D)

en

18

Q

elK

Vee

CD
CD

I/O

en

Q

3

Q

r+

2

1 20 19

18
17
16
15

Q
Q

Q
Q

14

I/O

9 1011 12 13

GND"-l.._....;.;J....

M SUFFIX ... J PACKAGE
C SUFFIX .•. J OR N PACKAGE

TIBPAL 16RS'
M SUFFIX •.• FH OR FK PACKAGE
C SUFFIX ••• FN PACKAGE

ITOPVIEWI

ITOPVIEWI

TIBPAL 16RB'

elK

Vee
Q

3

Q

2

1 20 19

Q

18

Q

17

Q

16
15

Q
Q

14

Q

9 1011 1213

OE

2·78

TEXAS ."

INSTRUMENlS
POST OFFICE BOX 855012 • DALLAS. TeXAS 75265

TIBPAL l6LO·30M, TIBPAL l6R4·30M
TIBPAL l6LO·25C, TIBPAL 16R4·25C
LOW·POWER HIGH·PERFORMANCE IMPACpMPAL@ CIRCUITS
functional block diagrams (positive logic)
'PAL 16LB

EN ;>1

&

k>-----o

32X 64

r:>----O
k>-"'~""-I/O

10

16

P-~""'''''-I/O

k>-ti.........-I/O

6

k>-e+........-I/O

II
II)

b-1

8
32X644-

~

--J-

~

c>

....;L

-

~
2!"""

C

....
en
:::r
I»
I»

CD
CD

....
en

-

~

-

r-------

r----.
r----.
r----.

~
~

+

--...

~

2,.7
...:.,.-

a

1-0 2
lD

EN

a

a
a
a

a

~

:>1
V

110
110

2
6

'PAL 16RS

DE----------------------~~~--,
CLK----------------------------~

r;:>;;l--r~o,~--- a
j----t----1-~-a

t---r--1---':l-a
j---t----1--+-- a
j----t----1--+--a
~---t----1-~-a

t---r--1---':l-a
t---r--1---':l-a
-- denotes fused inputs

2·80

TEXAS ~

IN STRUM ENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TIBPAL 16L8·30M, T1BPAL 16L8·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTNPAL® CIRCUITS
I 111
PRODUCT
LINES '0

INPUT LINES

,

4

8

12

16

20

24

28

0

···
~
···
·
'r:x
··•

31

,-

0-

>----"

~

J

1191

1

1181

o

t----c

8

v

I/O

r-

131 15
16

[--...

·•

1

1171

v

I/O

II...
U)

Q)
Q)

t----c

.c

141 ...23

0

v

24

··•
·
··
·
··•
·
·••
·
·••
·•

t----c

f--

p-

J

1161

1

1151

1

1141

I/O

...a:sa:s

C

151,,31

32

v

I/O

t----c

161 39

40

r-...

v

I/O

171 47
48

)-)--

k

- f--"

1

1131

v

I/O

)--

181 55
v

56

f--

63

191

p-

J

1121

o

1111

v

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-81

TIBPAL 16R4·30M, TIBPAL 16R4·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS
CLK~----------__________________________

PRODUCT ;o;;-_--;:_ _-:=-_~::_I-NP-U_T':'U:::_N-ES-_::::_-__:::_:__-_:=__::':'
UNES '0
4
8
12
16
20
24
28
31'
0

··•
·
~

f--

I--'

1
v

119)

I

110

va-

1

••
••
•

E

·

en
:::r

I/O

1

13) 15

··••

16

f----1

-

C

...mm

v

118)

-l->

·
··••
•

>---'

14) 23
X
24

...

CD
CD

(II

15)

tJ; -;) ' '

Q

C1

f---'

e-D-

tJ;

'";:1116)

--yo-

Q

~

'";:1

Q

C1

~

32

••
••

f----1

·

e-P-

C1

16) 39

40

•

··•••
·••
·••

~D-tJ;

'";:1114) Q

v

C1

17) 47

48

1

e-

55
18) X

v

f----c

··••
·

56

'--'

113)

110

1

1
v

63
1 19) X

2-82

115)

v

(12)

110

1
~ DE

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 866012 • DALLAS, TEXAS 75265

TIBPAL 16R6-30M. TIBPAL 16R6-25C
LOW-POWER HIGH-PERFORMANCE IMPACTTMPAL® CIRCUITS
CLK~~--------------------------------------------__~
PRODUCT,
LINES
0
0

INPUT LINES
4

8

12

16

20

24

28

31
I--

0
0
0
0
0
0

>------'~

'--"

7
(2'-f:::,t---<
"~
0
0
0
0
0
0

(3)

WI

(19)

110

> :bl~ n. a

-

Cl

15
16

~

0
0
0
0
0
0

}-P>---'

23

e---'

0
0
0
0
0
0

:bl

a

&I
...
U)

CD
CD

.c
tn

...
CO

,-,C>r--

~16) a

Q

CO

C

Cl

c-----<

(5) 31

(17)

Cl

(4) >L

24

'";J
....

32
f---<

0
0
0
0
0
0

:bl
8
->8
C>-

>---'

(6) 39
40
0
0
0
0
0
0

'";J
v

(14)

a

";::l

(13)

a

Cl

48
0
0
0
0
0
0

-

55
56
0
0
0
0
0
0

......r~
~

63

(9)

Cl

>----,C>-

(7) 47

(8)

¢'a

>L

V

Cl

1
v

I

(12)

110

l.(p!!!) DE

TEXAS ."

INSlRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265

2-83

TlBPAL t6RB·30M. TlBPAL t6RB·25C
LOW·POWER HIGH·PERFORMANCE IMPACT'MPAl® CIRCUITS

PRODUCT
LINES '0
0

INPUT LINES
4

8
I

12

16

20

24

28

I

3'-

0
0
0
0
0
0

>- ~'~ ""

Q

C1

~

'b--

8
0
0
0
0
0
0

E

>---

16
0
0
0
0
0
0

CI)
CI)

(4)

....
tn

0
0
0
0
0

(5)

}---

.

24

CD
CD

>--->

23

::r

}--p.

0
0

t±>-

0
0
0

39
(6) )(

tl

~

Q

C1

I--

40

l---1

"

}--t>

0
0
0
0
0
0

}--

I--

47
48

}--t>

0
0
0
0
0
0

(bl

t:r:l(14) Q
I.-

C1

w
b
V

(13)

Q

C1

55
56
}-----,

0
0
0
0
0
0

'-t:>-lbl

I-.

63

2-84

Q

C1

31

I(~

~

~

l---1

o

i8)

~

~) Q

Q

C1

32

Q)

~

~

C1

(3) 15

c
....

t/)

~

~(12) 1/0

C1

L.,

~) OE

I

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TIBPAL 16LB-30M, T1BPAL 16R4-30M
TIBPAL 16LB-25C, TIBPAL 16R4-25C
LOW-POWER HIGH-PERFORMANCE IMPACpMPAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) ............................. :. . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) ......................... : . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: M suffix. . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
C suffix .............................. DoC to 75°C
Storage temperature range ......................................... - 65°C to 150°C
NOT~

1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions
25C

30M

PARAMETER

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.5

5

5.25

V

5.5

2

5.5

V

VCC

Supply voltage

VIH

High-level input voltage

Vil

Low-level input voltage

0.8

0.8

IOH

High-level output current

-2

-3.2

mA

IOl

Low-level output current

12

24

mA

fclock

Clock frequency

50

MHz

2

,

0

I High
I low

tw

Pulse duration, clock (see Note 2)

tsu

Setup time, input or feedback before ClKt

th

Hold time, input or feedback after ClKt

TA

Operating free-air temperature

40

10

0
8

11

9

20

15

0
-55

0

U)

Q)
Q)

J:

ns

o

...caca

ns
ns

0
125

II
...

V

70

·C

NOTE: 2. The total clock period of ClK high and ClK low must not exceed clock frequency. fclock. Minimum pulse durations specified
are only for ClK high or ClK low, but not for both simultaneously.

o

programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 995-5762.

TEXAS . "

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-85

TlBPAL 16L8·301lli, TIBPAL 16R4·30M, TIBPAL 16R6·30M, TlBPAL 16R8·30M
TIBPAL 16L8·25C, TlBPAL 16R4·25C, TIBPAL 16R6·25C, TIBPAL 16R8·25C
LOW·POWER HIGH·PERFORMANCE IMPACT™PAL® CIRCUITS
.
electrical characteristics over recommended operating free-air temperature range

•

PARAMETER
VIK

Vee - MIN,

VOH

Vee

VOL
Outputs
IOZH

1/0 ports

Outputs
10ZL

•

1/0 ports

II

=

IOH

Vee

= MIN,
= MIN,

IOL

= MAX
= MAX

Vee

= MAX,

Vo

= 2.7

Vee

= MAX,

Vo

= 0.4 V

= MAX,

VI

= 5.5

V

IIH

Vee

= MAX,

VI

= 2.7

V

IlL

Vee

= MAX,
= MAX,
= MAX,

VI

Vee
Vee
VI

TYP*

2.4

3.2
0.25

V

Vee

10§

MIN

-18 mA

II

lee

-30M

TEST CONDITIONS t

MAX
-1.5

-26C
MIN· TYP*
2.4

3.3
0.35

0.4

MAX
-1.5
0.6

20

20

100
-20
-250

100
-20

Pin I, 11

0.2

All others

0.1

-250
0."
0.1

UNIT
V
V
V
~A

~

mA

Pin 1, 11

50

20

All others

20
-0.2

20
-0.2

mA

-125

mA

100

mA

= 0.4 V
Vo = 2.25 V

-30

Outputs Open

-125
75

= OV

-30
75

105

~

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, TA = 25·e.
§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.

switching characteristics over recommended supply voltage and operating free-air temperature renges
(unless otherwise noted)
PARAMETER

fROM

TO

TEST CONDITIONS

0,1/0

tdis

1,1/0
eLK!
OEJOEt

ten
tdis

1,1/0
1,1/0

0,1/0
0,1/0

t1td
ten

TYP*

MIN

UNIT

TYP*

MAX
26

MHz
ns

30
15

30

15

Q

RL = 600 Il,

10

20

10

15

ns

Q

eL = 50 pF,
See NDte 3

15

15
10

20
20

ns

10

25
25

14

30

14

25

ns

13

30

13

25

ns

Q

t All typical values are at Vee = 5 V, T A 25 ·C.
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.

2-86

-26C
MAX

25

f max

tDd

-30M
MIN

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

ns

TIBPAL20L8·20M, TIBPAL20R4·20M, T1BPAL20R6·20M, TIBPAL20R8·20M
TIBPAL20L8·15C, T1BPAL20R4·15C, TIBPAL20R6·15C, TIBPAL20R8·15C
HIGH PERFORMANCE IMPACT'MPAl® CIRCUITS
02920, JUNE 1986- REVISED DECEMBER 1987

TIBPAL20LB'
M SUFFIX, , . JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE

•

High Performance: f max (wlo feedbackl
TIBPAL20R' C series . , . 45 MHz
TIBPAL20R' M series ... 41.5 MHz

•

High Performance, .. 45 MHz Min

Vee

•

Functionally Equivalent to, but Faster than,
PAL20L8, PAL20R4, PAL20R6, PAL20R8

I

ITOP VIEW)

•

Preload Capability on Output Registers
Simplifies Testing

•

Package Options Include Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

o
1/0
1/0
1/0
1/0
1/0
1/0

o

Reduced ICC of 180 mA Max
DEVICE
'PAL20L8
'PAL20R4
'PAL20R6
'PAL20R8

3·STATE

I INPUTS

o OUTPUTS

14
12
12
12

2
0
0
0

0
4

(3~state

II
...

1/0

REGISTERED
Q OUTPUTS
buffers)

6 /3-state buffers)

8 (3-state buffers)

PORTS
6
4
2
0

TlBPAL20LB'
M SUFFIX .. , FK PACKAGE
C SUFFIX ... FN PACKAGE
ITOPVIEW)

CD
CD

.s:::
en

u
u
___ uz>_o

description

4

These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices.
These IMPACT'" circuits combine the latest
Advanced Low-Power Schottky t technology
with proven titanium-tungsten fuses to provide
reliable, high performance substitutes for
conventional
TTL logic,
Their easy
programmability allows for quick design of
custom functions and typically results in a more
compact circuit board. In addition, chip carriers
are also available for further reduction in board
space.

I/)

3

2

...
CO
CO

1 28 27 26

25

24
23

1/0
1/0
I/O

C

22 Ne
21

20

10

"

19

1/0
1/0
1/0

121314 15 16 17 18

NC- No internal connection

Pin assignments in operating mode

Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low
state. This feature simplifies testing because the registers can be set to an initial state prior to executing
the test sequence.
The TIBPAL20'M series is characterized for operation over the full military temperature range of - 55 DC
to 125 DC, The TIBPAL20'C is characterized from 0 DC to 75 DC.

IMPACT is a trademark of Texas Instruments Incorporated
PAL is a registered trademark of Monolithic Memories Inc.
t Integrated Schottky-Barrier diode-clamped transistor is patented
by Texas Instruments, U.S. Patent Number 3,463,975.

PRODUCTION DATA do.umants .ontain inlormation
currnt 88 of publication data. Products cantDrm to
spacifications per the terms of Texas Instruments

::~:~~i~air::1~7i ~!:~~:i:r :.~O:::~~~~ not

Copyright

TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

© 1986, Texas Instruments Incorporated

2-87

TIBPAL20R4·20M, TIBPAL20R6·20M, TIBPAL20R8·20M
TIBPAL20R4·15C, TIBPAL20R6·15C, TIBPAL20R8·15C
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS
TIBPAL20R4'
M SUFFIX . .. JT PACKAGE
C SUFFIX . .. JT OR NT PACKAGE

TISPAL20R4'
M SUFFIX . .. FK PACKAGE
C SUFFIX . .. FN PACKAGE

(TOP VIEW)

(TOP VIEW)

ClK

e

VCC

~ u
a
--uz>_""

I
liD
liD

4

3 2

1 2827 26
25

Q

liD

Q
22

liD
liD

Q

Q

19

liD

I
12131415 1617 18

GND --.;'---=.... DE

11

NC

21

20

TlBPAL20RS'
M SUFFIX . .. JT PACKAGE
C SUFFIX . .. JT OR NT PACKAGE

TIBPAL20RS'
M SUFFIX . .. FK PACKAGE
C SUFFIX . .. FN PACKAGE

(TOPVIEWI

(TOP VIEWI

ClK

u ~ 0
__ :J
uz>_""

VCC
I

liD

4321282726

Q

Q
Q

I

5

25

I

6

24

I
NC
I

liD

9

I

10

I

11

121314151617 18

TIBPAL20RS'
M SUFFIX . .. JT PACKAGE
C SUFFIX . .. JT OR NT PACKAGE

TIBPAL20RS'
M SUFFIX . .. FK PACKAGE
C SUFFIX . .. FN PACKAGE

(TOPVIEWI

(TOP VIEW)

ClK
I

VCC
I
Q

4

Q
Q

I
I

Q

2

1 2827 26

I

Q

NC
I

Q

Q
I

GND Y;;=--..:.:::J>-'

3

5
6

22
9

I

10

I

11
12131415 161718

BE

--~~Ib-d
(!)

NC-No internal connection

Pin assignments in operating mode

2·88

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265

TIBPAL20LB·20M, TIBPAL20R4·20M
TlBPAL20LB·15C, TIBPAL20R4·15C
HIGH·PERFORMANCE IMPACpMPAL® CIRCUITS
functional block diagrams (positive logic)
TIBPAL20LS'

EN >1

&

40

x 64

'<:7t>----0
b----o

14

20

IO-~""_I/O

II

b-e+-+....-I/O
b--<-+-....~ I/O

(I)

+or
Q)
Q)

b--<-+-+t~ I/O

.c

6

CJ)

(Q

+or

TIBPAL20R4'

(Q

o

OE

EN

ClK

C1

~
40 X 64

,..-20X [>
12

4

r+
I..--

~

'V

~

'V

>1

8

I--f-

o

'<:7
~

10

~
~

:>

f-+-

~

:>

~

I--

f-..,l.-

Q

~
Q

EN

o

>1

'<:7

f---J
~
f--.y-

f-+--

'"

'"

I---y-

L.-~

I/O
I/O
I/O
I/O

4

I"\.J denotes fused inputs

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-89

TIBPAL20R6·20M, TIBPAL20RB·20M
TIBPAL20R6·15C, TlBPAL20RB·15C
HIGH·PERFORMANCE IMPACTTM PAl® CIRCUITS
functional block diagrams (positive logic)
TIBPAL20RS'

OE

"lEN
C1

r.,

ClK

-a;40X 64

8

;;>1

p.;.

Q

---..

10

~
~-m-;+ 'V
~

Eo

---..

~

"---

~

'V

~

Q

r----,

AI

en

Q

h

EN ;;>1

\7

,---f-!."-

:::T
CD
CD

a

r----,

~

2,.7

AI

r+

Q

r----,

~

r,.

Q

.

1/0

r

1/0

2

6

r+

en

TIBPAL20RS'

OE
ClK
Q

Q

Q

12

20X C>

20
Q

Q

Q

Q

Q

8

"-' denotes fused inputs

2·90

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

TIBPAL20LB·20M
TlBPAL20LB·15C
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
logic diagram (positive logic)
(1)

INPUT LINES
/0

4

8

12

16

1\

20

24

28

32

I~

0

•
•
•

I~

141 .....

7
8

161~

...

~

..

181~

-

. ...r---'

•
•
23

.--

~4

•
•
•
31

~~

tI)

(201

(191

I/O

1/0

G)
G)

.c
en
....asas
C

32
(181

•
•
39

:J

40

•
•
•
47

(171

...

I/O

1/0

--

.......

...J

••
•
55

(161
1/0

-

~

56

~

•
•

1~

....

v

48

l!!t

o

1211

....

•

I~

1221

:--

•
•
•
15
•

...

1231
,.---

r--J

16
151

\

..;.r--

""
PR ODUCT
II NES

36

•
63

~

.

1151

o

(14)

(13)

111~

.;,r-------

Pin numbers shown are for JT and NT packages.

. TEXAS.

INSTRUMENTS
POST OFFICE BOX 655012 .. DALLAS, TEXAS 75265

2·91

TIBPAL20R4·20M
TIBPAL20R4·15C
HIGH·PERFORMANCE IMPACTTM PALl$) CIRCUITS
logic diagram (positive logic)
ClK

,

11) ....
INPU~LlNES

10
12)

4

8

16

12

20

24

28

32

36

\

....

'"

PR ODUCT

0

LIN ES

.1

@!.-

7
8

....

•

••

14)-

'"
I~-

'\..

15
16

....

•
••
23

......

.

40

""

~
c,

~

1.119)

V""

1.l118)

v

Q

Q

IJ... 117)

Q

......

•
•
•
55

J

116)

1

116)

~

•
•
•
63

~

'"

114)

111)

""
Pin numbers shown are for JT and NT packages.

2-92

Q

1- ~

56

11!l.4

/0

----'

-Pl

~

48
II~

Vl

c,

•
•
39
•
•
•
47

118)

(21) I

)-

•

v

J

:J

I10

'D

"32

171-

122)

Iv
>-- ~~]
c

•
•
31•

16)

1

......

24

I

123)

""

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • OAUAS. TEXAS 75265

I

~

I/O

I/O

TlBPAL20R6·20M
TIBPAL20R6·15C
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
logic diagram (positive logic)
ClK

(1)~

...

,

0

. INPUTA;:INES
4

8

12

16

20

24

28

32

(2)

36

,
(23)

~

I/O

PR ODUCT
LI NES

0

•

•
•
7

(!l

'-

•
•

...

1 .....

"\.

"
r--

16

(7)~

(!)~

(1

v

31•
32

••
•
39

)-

40

"

~

•
•
•
47

-~

)-

.....

•
•
55

iJ...

(1

I.l...

(1

B
c,

~

L>-~

•

c,

t;w1

I .....

: t------'

56

1

•

(10) ..

(20

I'"

~

48
(~

c,

"

•
•

...

iJ

~
r- I.l
tl]
.-..

•
•
23
24

(6)~

1/0

... 1

r- ~I.l'"
'0
c,

•
15

•

(5)~

(22)

~

8
(4) ....

J

•
63•

(15)

1/0

- .. 1
(14)

(11)

4.-

~-I

+

Pin numbers shown are for JT and NT packages.

TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

)

OE

2-93

TIBPAL20RB·20M
TIBPAL20RB·15C
HIGH·PERFORMANCE IMPACTTM PAL@ CIRCUITS
logic diagram (positive logic)
(1)

.

c LK '"

INPUT,./-INES
"'0

4

B

16

12

20

24

2B

32

(2)

36

...

....

(23)

P RODUCT
LINES

0

.

(3)"

•
•
7•

r ~
~"2J
c,
........

~

•
15•

4)

)-

C

.....
~

•

en

:::r

(5)"

•
•
23

...

-2~

CD
CD

P+

tit

(6)

...

(7)

(B) ...

)-

...,
~

>...,
~

32

•
•
•
39

r
~

••

r

•
47

•
•
•
55

)-

~
~

Pl
c,

...,

-56

•
•

10)

~

c,

1....

48
(9) ...

~
c,

1-

c,
)-~

•
63

~(21)
v

Q

r---'

c,

•
•
•
31

-4

~
c,

16

I»
P+
I»

Q

i:l....

(20)
Q

1.1 (19

v

Q

1.1(18

rv-

Q

1.
-v--

(17

1...

(16

i:l....

(16

Q

Q

Q

~

(14)

1)

- ...

"::l- 1-1
3)_
OE

~
Pin numbers shown are for JT and NT packages.

2-94

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265

TIBPAL20LB-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20RB-20M
TlBPAL20LB-15C, TIBPAL20R4-15C, TlBPAl20R6-15C, TIBPAL20RB-15C
HIGH-PERFORMANCE IMPACTTM PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: M suffix. . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°e
e suffix : ............................. ooe to 75°e
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions
-20M

PARAMETER
vCC

Supply voltage

VIH

High-level input voltage

VIL

Low-level input voltage

IOH

High-level output current

IOL

Low-level output current

fclock

Clock frequency

MIN
4.5

NOM
5

2

-lSC

MAX

MIN

NOM

5.5

4.75

5

5.5

2

5.5

O.B
-2

O.B
-3.2

12

I High
I Low

tw

Pulse duration, clock

tsu
th

Setup time,. input or feedback before CLKt
Hold time, input or feedback after CLKt

TA

Operating free-air temperature

41.5

0
12
10

15

0
-55

0

0

\i

V
V
mA

24

mA
MHz
ns

10

0
125

UNIT

45

10
12

12
20

MAX
5.25

75

EI...
til

Q)
Q)

.c

ns

Ul

ns

CIS
CIS

ns
DC

...

C

fClock. two tsu. and th do not apply for TIBPAL20LB'.

TEXAS •

INSlRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-95

TIBPAL20L8·15C, TIBPAL20R4·15C, TIBPAL20R6·15C, TIBPAL20R8·15C
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
electrical characteristics over recommended free·air operating temperature range
PARAMETER

TEST CONDITIONS
Vee = 4.75 V,
Vee - 4.75 V,
Vee = 4.75 V,

VIK
VOH
VOL
10ZH
10Zl

•
C

DI

S'

0,0 outputs
1/0 ports
0, 0 outputs
1/0 ports

II = -18mA
10H - -3.2 mA
10l

=

=

5.25 V,

Vo

= 2.7

Vee

=

5.25 V,

Vo

= 0.4 V

=
=
=
=
=

5.25 V,

VI

5.25 V,

VI

II

Vee
Vee

III *

Vee

10S§

Vee
5.25 V,
Vee
5.25 V,
Outputs open,

5.25 V,

-lSC
TYpt
-0.8

MAX
-1.5

2.4
0.3

24 mA

Vee

IIH*

lee

MIN

V

= 5.5 V
= 2.7 V
VI = 0.4 V
Vo = 0
VI = 0,

-30

OE at VIH

0.5
20
100
-20
-0.25
1

UNIT
V
V
V

p.A
p.A
mA
mA

25

p.A

-0.25

mA

-70

-130

mA

120

180

mA

tAli typical values are Vee = 5 V, TA = 25°e.
* For 1/0 ports, the parameters IIH and III include the off-state output current.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

en switching characteristics over recommended operating free-air temperature range (unless otherwise
;- noted)
CD
r+

(II

PARAMETER

FROM

f max '
tpd

with feedback
without feedback
1,110

0,1/0

tpd

elKt

0

Rl

ten

?5E

0

eL

tdis

?5Et

ten
tdis

TO

TEST CONDITIONS

MAX

40

UNIT
MHz

15

ns

8

12

no

10

15

ns

0

8

12

ns

1.1/0

0,1/0

12

18

ns

1,1/0

0,1/0

12

15

no

=
=

=

2000,

R2

3900,

50 pF,

See Figure l'

tsu

1

+ tpd (elK to 0)

, f max (without feedback)

=

tw high

1

+ tw low

f max does not apply for TIBPAL20l8'

2-96

-lSC
TYpt
50
12

tAli typical values are at Vee = 5 V, TA = 25°e.
1fmax (with feedback) =

MIN
37
45

TEXAS

~

INSIRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TIBPAL20LB-20M. TIBPAL20R4-20M. TIBPAL20R6-20M. TIBPAL20RB-20M
HIGH-PERFORMANCE IMPACpM PAl® CIRCUITS
electrical characteristics over recommended free-air operating temperature range
PARAMETER

TEST CONDITIONS

VIK

Vee = 4.5 V,

VOH

Vee = 4.5 V,
Vee = 4.5 V,

VOL
0, 0 outputs
10ZH
10ZL

110 ports
0, 0 outputs
110 ports

MIN

II = -18 rnA
10H = -2 rnA

2.4

10L = 12 rnA

Vee = 5.5 V,

Vo = 2.7 V

Vee = 5.5 V,

Vo = 0.4 V

-20M
Typt

MAX

-0.8

-1.5

3.2
0.25

0.5

V

20
100

~A

UNIT

V
V

-20

~A

-0.25

rnA
rnA

II

Vee = 5.5 V,

VI = 5.5 V

1

IIH"

Vee = 5.5 V,

VI = 2.7 V

25

~A

IlL'

Vee = 5.5 V,

VI = 0.4 V

-0.25

rnA

10S§

Vee = 5.5 V,

Va = 0

-70

-130

rnA

Vee = 5.5 V,

VI.= 0,
OE at VIH

120

180

rnA

lee

Outputs open,

-30

II

t All typical values are Vee = 5 V, TA = 25°e.
:t: For 110 ports, the parameters IIH and IlL include the off-state output current.
§

Not more than one output shquld be shorted at a time, and duration of the short-circuit should not exceed one second.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
FROM

PARAMETER

TO

TEST CONDITIONS

with leedback
I max '

without feedback

MIN

-20M
Typt
MAX

28.5

40

41.5

50

UNIT

MHz

12

20

ns

R2 = 750 II,

8

15

ns

See Figure 1

10

20

ns

0

8

20

ns

1,1/0

0,1/0

12

25

ns

1.1/0

0,1/0

12

20

ns

tpd

1,110

0,1/0

tpd

eLKt

0

Rl = 390 II,

ten

OE

0

CL = 50 pF,

tdis

O'Er

ten
tdis

t All typical values are at VCC = 5 V, T A = 25°e.

'I

max (with leedback) =

1
, 1m ax (without leedback) = ..,--;-:--;-c.....,.......,..,tsu + tpd (CLK to 0)
tw high + tw low

'max does not apply lor TIBPAL20L8'

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-97

TIBPAL20L8·20M, TIBPAL20R4·20M, TIBPAL20R6·20M, TIBPAL20R8·20M
TIBPAL20L8·15C, TlBPAL20R4·15C, TIBPAL20R6·15C, TlBPAL20R8·15C
HIGH·PERFORMANCE IMPACpM PAL ® CIRCUITS
preload procedure for registered outputs (see Note 2)
The output registers of the TIBPAL20R' can be preloaded to any desired state during device testing. This
permits any state to be tested without having to step through the entire state-machine sequence. Each
register is preloaded individually by following the steps given below.
Step
Step
Step
Step

1.
2.
3.
4.

With Vee at 5 V and pin 1 at VIL, raise pin 13 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse pin 1, Clocking in preload data.
Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage
level at the output pin.

preload waveforms (see Notes 2 and 3)

PIN 13 _ _ _

f\---- ::~"
n---:-T-----

~/ ~""~
~td...l

PIN 1

~+~

: l

I+-tw-+l

I

.

I

I

VIH

I

I

I

I

I

-JR ,. ~ 8 o~.~

REGISTERED I/O _ _ _

NOTES:

:::

2. Pin numbers shown are for JT and NT packages only. If chip carrier socket adapter is not used, pin numbers must be changed

accordingly.
3. td ~ tsu ~ tw ~ 100 ris to 1000 ns.
VIHH ~ 10.25 V to 10.75 V.

2-98

VIL

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TIBPAL20LB·20M, TIBPAL20R4·20M, TIBPAL20R6·20M, TIBPAL20RB·20M
TIBPAL20LB·15C, TIBPAL20R4·15C, TlBPAL20R6·15C, TlBPAL20RB·15C
HIGH·PERFORMANCE IMPACTTM PAL ® CIRCUITS
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5762.

PARAMETER MEASUREMENT INFORMATION
5V

Sl

b

Rl
FROM OUTPUT_....._ . ._ ...._
UNDER TEST

...

TEST
POINT

II)

CD
CD

R2

.c

(/)

...asas

LOAD CIRCUIT FOR
THREE-STATE OUTPUTS
TIMING
INPUT

:

-'w-

HIGH.LEVEL ~- --3.5 V
" ,1.5V
1.5V,
PULSE
,
,0.3 V

/.
3.5 V
/,1.5V
:--------0.3V

_ _ _oJ

... t.u

DATA
INPUT

o

""'h~

1.5 V
1.5 V
~
0.3 V

~

LOW-LEVEL
PULSE

'1.5V

\1.5
I·

----35V
V
.

~1.5V
- - "1
tPLH~

IN.pHASE
OUTPUT

1

I

"

-I

I

~~
-;:~ VOH

I

'PHL ~
OUT '()F.pHASE
OUTPUT

11.5V:

I

1.5V
•

VOL

F'

1.5V VOH
__ VOL

(See Note D)

VOL TAGE WAVEFORMS
PROPAGATION DELAY TIMES

3.5V
0.3V

~
1.5 V

(low-Iavel
enabling)

PHL

I4--*-tpLH

\1

OUTPUT
CONTROL

0.3 V

_____ t

1.5V
--- -

VOLTAGE WAVEFORMS
PULSE DURATIONS

VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES

INPUT

tw~

..

-:----3.5V

I

.PZL .....
I

ItI

Sl CLOSED
(See No.e B)
WAVEFORM 2
Sl OPEN
(See No.e B)

i

'PZH

-i-- -- ----

0.3 V

__ It--tpLZ
I I

I I

WAVEFORM1~

3.5V

1.5 V

=3.3 V

1.5V

iI::~5V

~-=-------:.;==

--l..t

...:

~
1.5 V

VOL

!'-tPHZ

-----t--v
-----.-0.5 V

OH

"'0 V

VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS

NOTES: A_ CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C_ All input pulses have the following characteristics: PRR '" 1 MHz. tr = If = 2 ns, duty cycle = 50%.
O. When measuring propagation delay times of 3-state outputs, switch S1 is closed.

FIGURE 1

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TeXAS 75266

2-99

•

...c
A)
A)

en
:::r
CD
CD

...en

2-100

TIBPAL20L8·30M, TlBPAL20R4·30M, TIBPAL20R6·30M, TIBPAL20R8·30M
TIBPAL20LB·25C, TlBPAL20R4·25C, TIBPAL20R6·25C, TIBPAL20R8·25C
LOW·POWER HIGH PERFORMANCE IMPACTTM PAL® CIRCUITS
D2920. MAY 1987-REVISED DECEM8ER 1987

•

Low-Power, High Performance
Reduced ICC of 105 mA Max
f max (TIBPAL20R'-25C Series):
Without Feedback ... 33 MHz Min
With Feedback ... 25 MHz Min
tpd (TIBPAL20'-25C Series) ... 25 ns Max

•

Direct Replacement for PAL20L8A, PAL20R4A,
PAL20R6A, and PAL20R8A with at Least 50%
Reduction in Power

•

Preload Capability on Output Registers Simplifies
Testing

•

Power-Up Clear on Registered Devices

•

Package Options Include Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic
DIPs

•

Dependable Texas Instruments Quality and
Reliability

DEVICE
'PAl20l8
'PAl20R4
'PAl20R6
'PAl20R8

I INPUTS
14
12
12
12

1/0

REGISTERED
OUTPUTS

PORTS

2
0
0

0
4 (3-state buffers)
6 (3-state buffers)
8 13-state buffers)

6
4
2
0

0

ITOP VIEW)
VCC
I

o
110
110
110
110
110
110

o

3·STATE
o OUTPUTS

a

TIBPAL20LS'
M SUFFIX •.. JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE

GND ""--''---=~

TlBPAL20LB'
M SUFFIX •.. FK PACKAGE
C SUFFIX .•• FN PACKAGE
(TOP VIEW)
u
u
___ u
z>_o
4

3

2 I 28 27 26
25
24

9

" 12 13 14 15 16 17 18
description

23
22
21
20
19

...en

CD
CD

.s:.

en

...caca

110
110
110
NC
110
110
110

o

--ou--o
zz

l!J
These programmable array logic devices feature
high speed and functional equivalency when
NC - No internal connection
compared with currently available devices.
Pin assignments in operating mode
These IMPACT'" circuits combine the latest
Advanced Low-Power Schottkyt technology
with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL
logic. Their easy programmability allows for quick design of custom functions and typically results in a
more compact circuit board. In addition, chip carriers are also available for further reduction in board space.

In many cases, these low-power devices are fast enough to be used where the high-speed or "A" devices
are used. From an overall system level, this can amount to a significant reduction in power consumption,
with no sacrifice in speed.
All of the output registers are set to a low level during power-up, but the voltage levels at the output pins
stay high. Extra circuitry has been provided to allow loading of each register asynchronously to either a
high or low state. This feature simplifies testing because the registers can be set to an initial state prior
to executing the test sequence.
The TIBPAL20'M series is characterized for operation over the full military temperature range of - 55°C
to 125°C. The TIBPAL20'C is characterized from OOC to 75°C.
IMPACT is a trademark of Texas Instruments Incorporated
PAL is a registered trademark of Monolithic Memories Inc.
tlntegrated Schottky·Barrier diode·clamped transistor is patented by Texas Instruments. U.S. Patent Number 3.463,975.

This docu_1It cantains informatiDn aD pradum in
mara thIn ana ph••a af dovalopmant na statUI al
81ch device is indic_ an tba paga(s)spaclfying ilB
electrlc.1 characteristics.

Copyright @"1987, Texas Instruments Incorporated

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265

2-101

TIBPAL20R4·30M. TlBPAL20R6·30M. TIBPAL20R8·30M
TIBPAL20R4·25C. TlBPAL20R6·25C. TlBPAL20R8·25C
LOW·POWER HIGH·PERFORMANCE IMPACpM PAL® CIRCUITS
TIBPAL20R4'
M SUFFIX .•. JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE

TIBPAL20R4'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE

(TOP VIEW)

(TOP VIEW)

ClK

VCC

I

~

~

u
0
--UZ>_,,=

I

I/O
4

liD

3

2

1 28 27 26

Q

I

5

25

liD

Q

I

6

24

Q

Q

23

Q

Q

22
21
20

Q

19

liD

liD
liD
I

I

I

GND """''--...;.;;J....

NC
Q

12 131415 1617 18

ill

TIBPAL20RS'
M SUFFIX ... JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE

TIBPAL20RS'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE

(TOP VIEW)

(TOP VIEW)

ClK

VCC
I
liD

4

Q

I
I

Q
Q

3

2 1 28 27 26

5
6

25

Q

24

Q

23

Q

Q

22
21
20
19

Q
Q

10

liD

11

NC
Q
Q

Q

121314151617 18

TIBPAL20RS'
M SUFFIX ... JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE

TIBPAL20RS'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE

(TOP VIEW)

(TOP VIEW)

CLK

VCC
I
Q

4321282726

Q

25

Q

24

Q

23

Q

22

Q

21
20
19

I

GND

I

12131415 1617 18

'-I.:.:;.....-::~ ill

- -

~ ~Io

-

0

(:J

NC - No internal connection

Pin assignments in operating mode

2·102

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TIBPAL20L8·30M, TIBPAL20R4·30M
TIBPAL20L8·25C, TIBPAL20R4·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
functional block diagrams (positive logic)
TIBPAL20L8'

EN ~1

&

40X64

"10----0
0----0

14

20

II

b--e+.......-I/O

6

TIBPAL20R4'

OE----------------------------~

CLK------------------------------~
&

1-------0

j--t--l-l--j--t---l-l---

20X I>

12

0
0

20
4

b--....-OIIIf+-+--- I/O

4

-+--- I/O

b-..-l~....

b-....I--o. .- I - -

I/O

b-....I--o...-I~-

I/O

4

"-' denotes fused inputs

TEXAS ..,
INsrRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-103

TIBPAL20R6·30M. TIBPAL20R8·30M
TIBPAL20R6·25C. TIBPAL20RB·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTM PAl® CIRCUITS
functional block diagrams (positive logic)
TIBPAL20RS'

OE-------~----....

40

•
•
•
47

.....

I/O

I/O

~

~~I
10

V

~

~
~
e,

~) a
'1
-v-- )a
(18

~

'1
-yo- ) a
(17

l

(16

~

•
55

56

./ -J .

•
•
63

(15

.. 1

....

(14)

""""1.-

I

.;,r-I

~

Pin numbers shown are for JT and NT packages.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

a

e

....

48

11)

2·106

-AI

c,

•

10) ...

(21)

h~

•
•

(9)

I

24

•
•
39

(7)

(22)

~

16

...C

l

TIBPAL20R6·30M
TIBPAL20R6·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTM PAL@ CIRCUITS
logic diagram (positive logic)
CLK

(1)

....l{)

,

0

INPUT~INES

4

8

12

16

20

24

28

32

I (2)

-"t,.
PR ODUCT
LIN ES

~

•
•
•
7

v

(7) ...

-"t,.

(!!.t

10) ...

~8'"

r

15
16

)0

c,

.A
~

•
•
23

>-)-

~

24

•
31•

)-

~

~

Q
v

II

(20 )0

"l

(1

"l

(1

"l

(1

1.1

(1

v

c,

~

~

32

••
•
39

r

~
c,

v

~

40

•
•
•
47

)-

~

v

c,

.....

•
•
•
55

....

1/0

I

~

48

(9)

v

(22)

~

8

•

(6)...

1

r--..
1--"

•

-v

(23)

0

•

(5) ...

,
~

•
•

4)"

36

~

>-=Yl
c,

v

.....

56

1

•
•
63•

(15)

~
. . +)

....

1/0

(14)

1~

ct---I

Pin numbers shown are for JT and NT packages.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-107

TIBPAL20RB·30M
TIBPAL20RB·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
logic diagram (positive logic)
'C LK

(1)

'''''

INPU~INES

~

"'0

4

8

12

16

20

24

28

32

(2)

"'""1.-

36

,
(23)

....

P ROOUCT
LINES

0

-

1 (3)"

4) ...
r

•
•

)-

~.

"'"

•
7

r

~

....

•
15•

)-

.....
'"

16,

>-

-t

9)

-t

"Z4

~

•
•
•
31

>-

Q

-

~
-

J(20
v

~

1 . (19

Q

-v--

Q

r--'

3Z

)-

~-

1 . (18
Q

Cl

'"

•
•
47

)-

1'"

48

•
•
•
55

)-

s

1 . (17

J

Pl

Q

....

....

(1 6)

Q

Cl

....

-56

~

•
•
63

•

0) ..

~-

1.(21

Cl

4.

(8)

Cl

•
•
•
39

(7)

Q

Cl

•
•
•
23

(6)

FI1 ?,,'

>-~
Cl

•

~

Q

~

r

'"

(14)

1)

.t- -I

~

3)_
OE

P~n

2-108

4:

numbers shown are for JT and NT packages.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

TlBPAL2DLB-3DM, TIBPAL2DR4-3DM, TIBPAL2DR6-3DM, TIBPAL2DRB-3DM
TIBPAL2DLB-25C, TIBPAL2DR4-25C, TIBPAL2DR6-25C, TIBPAL2DRB-25C
LOW-POWER HIGH-PERFORMANCE IMPACTTM PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: M suffix. . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
e suffix .............................. DoC to 75°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions
-25C

-30M

PARAMETER

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V

5.5

2

5.5

V

VCC

Supply voltage

VIH

High-level input voltage

VIL

Low-level input voltage

O.S

O.S

IOH

High-level output current

-2

-3.2

mA

IOL

Low-level output current
Clock frequency

12

24

mA

33

MHz

fclock

2

0

25

I High

tw

Pulse duration. clock

tsu

Setup time, input or feedback before CLKt

th

Hold time. input or feedback after CLKt

TA

Operating free-air temperature

I Low
-55

125

0

V

15

ns

fI
...
U)

CD
CD

.c

en

15

ns

25

ns

0

ns

...

°c

C

0

75

CO
CO

fclock. two tsu. and th do not apply for TIBPAL20LS·.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-109

TIBPAL20LB·30M. TIBPAL20R4·30M. TIBPAL20R6·30M. TIBPAL20RB·30M
LOW·POWER HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS
electrical characteristics over recommended free-air operating temperature range
PARAMETER

Vee = 4.5 V,
Vee - 4.5 V,
Vee = 4.5 V,

VIK
VOH
VOL
10ZH
10Zl

II
C

!

S»
(/)

:::r

CD

!(II

-30M

TEST CONOITIONS

0, 0 outputs
1/0 ports
0,0 outputs
1/0 ports

II = -lBmA
IOH = -2 mAo
IOl = 12mA

MIN

TVpT

2.4

-O.B
3.3
0.25

= 2.7 V

Vee

= 5.5 V,

Vo

Vee

= 5.5 V,

Vo = 0.4 V

MAX
-1.5
0.5
20
100
-20
-0.25
0.1

UNIT
V
V
V
I'A
I'A
mA
mA

II

Vee = 5.5 V,

VI = 5.5 V

IIH~

Vee = 5.5 V,

VI = 2.7 V

20

j4A

III ~

Vee = 5.5 V,

VI = 0.4 V

-0.2

mA

10S§

Vee = 5.5 V,
Vee = 5.5 V,
Outputs open,

Vo = 0
VI - 0,
DE at VIH

-130

mA

lee

-30

-70
75

mA

tAli typical values are at Vee = 5 V, TA = 25°e.
~ For 1/0 ports, the parameters·IIH and III include the off-state output current.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not excaed 1 second.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
f max '

!I!d
tDd

FROM

TO

with feedback
without feedback
1,1/0
elKt

MIN

0,1/0
0

ten

DE

0

DEt
1,1/0
1,1/0

0
0,1/025
0,1/0

tsu +tpd

n,

el = 50 pF,

R2 = 750

n,

Sea Figure 1

~e l K to 0)' fmax

(without feedback) =

h' h 1
I
tw Ig +tw ow

f max doe. not apply for TIBPAl20lB'

::D

o
C

c:
(')

-I
"'0

::D

m

m

~

=

PRODUCT PREVIEW inforlllotli••lnlOr••
In iii. far.lIi .. or l1li111 p.... of .....
......rIIIi. data .1III1IIIior ~... aro doIIl.

2-11 0

::"Jt:::.=;"":'"wit'\".~=:""

UNIT
MHz
ns.
ns
ns
no
ns
ns

"'0

<
-

MAX

30
Rl= 390

tAli typicai values a're at Vee = 5 V, TA = 25°e.
'fmax (with feedback) =

TVpT

25

tdls
ten
tdis

-30M

TEST CONDITIONS

TEXAS ",

INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 7528&

TlBPAL20LB·25C, TIBPAL20R4·25C, TlBPAL20R6·25C, TIBPAL20RB·25C
LOW·POWER HIGH·PERFORMANCE IMPACpMPAL® CIRCUITS
electrical characteristics over recommended free·air operating temperature range
PARAMETER

TEST CONDITIONS

VIK

Vce

VOH

Vee

VOL

Vee
0, Q outputs

10ZH

I/O ports
0, Q outputs

10Zl

I/O ports

= 4.75
= 4.75
= 4.75

II

V,

10H

V,

10l

-18mA

= -3.2 mA
= 24 mA

Vee

=

5.25 V,

Vo

= 2.7

Vee

=

5.25 V,

Vo

= 0.4 V

=
=
=
=

5.25 V,

VI

5.25 V,

VI

II

Vee

IIH*

Vee

III *

Vee

10S§

Vee
5.25 V,
Vee - 5.25 V,
Outputs open,

ICC

=

V,

MIN

5.25 V,

2.4

-25C
Typt

MAX

-0.8

-1.5

3.3
0.5
20
100
-20
-0.25

= 5.5 V
= 2.7 V
VI = 0.4 V
Vo = 0

0.1

-30

VI - 0,
OE at VIH

V
V

0.3

V

UNIT

V
~A

~

mA
mA

20

~A

-0.2

mA

-70

-130

mA

75

105

mA

...
fI)

t All typical values are at Vee = 5 V, TA = 25°C.
* For I/O ports, the parameters IIH and III include the off-state output current.
§ Not more than one output should be shorted at a time. and duration of the short-circuit should not exceed 1 second.

CD
CD
J:

switching characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER

FROM

f max '

with feedback
without feedback

tpd

I, I/O

tpd

TEST CONDITIONS

TO

MIN

·25C
TYpt

MAX

UNIT

25
33

40

3

25

ns

2

14
10

15

ns

2

8

15

ns

elKf

Rl

ten

OE

Q

el

tdis

trEf

Q

2

8

15

ns

ten
tdis

I, I/O

0,1/0

15

I, I/O

0, I/O

3
3

25
25

ns

tAli typical values are at Vee
'fmax (with feedback) =

tsu

=
+

5 V, TA

= 390 Il,

200 Il,

R2

50 pF,

See Figure 1

15

...
CQ
CQ

C

MHz

50

0, I/O
Q

=
=

en

ns

= 25°C.

1
, f max (without feedback)
tpd (elK to QI

=

tw high

1

+

tw low

f max does not apply for TIBPAl20lB'

PRODUCTION DATA do.umanls ••ntoi. infarmation
currant 8. of publication data. Products conform to
specificatiDns par t•• tarms of Taxas Instruments

:'~~~:~~.ir::I-::li =::i~n :'=ID~S not

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-111

TIBPAL20LB·30M, TIBPAL20R4·30M, TIBPAL20R6·30M, TIBPAL20RB·30M
T1BPAL20LB·25C, TIBPAL20R4·25C, TIBPAL20R6·25C, TIBPAL20RB·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
preload procedure for registered outputs (see Note 21
The output registers of the TIBPAL20R' can be preloaded to any desired state during device testing. This
permits any state to be tested without having to step through the entire state-machine sequence. Each
register is preloaded individually by following the steps given below.
Step
Step
Step
Step

1.
2.

3.
4.

With Vee at 5 V and pin 1 at VIL, raise pin 13 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse pin 1, clocking in preload data.
Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage
level at the output pin.

preload waveforms (see Notes 2 and 31

-1! ~''"~

Ec

~+~ i\-_n:~

PIN13 _ _ _

k-td-.l

....C»C»

: !

PIN 1

I+-tw~

n---:-T----1

---+---TI---'

en

::r

1

1

I

I

1

I

1

I

-1M

(1)
(1)

....UI

REGISTERED 1/0 _ _ _

I

VIH
VIL

8'-0-UT-P-U-T-::~

INPUT

NOTES: 2. Pin numbers shown are for JT and NT packages only. If chip carrier socket adapter is not used, pin nunibers must be changed
. accordingly.
3. td = tsu = tw = 100 ns to ;000 ns.
VIHH = 10.25 V to 10.75 V.

2-112

TEXAS

,If

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS '75265

TlBPAL20LB·30M. TIBPAL20R4·30M. TIBPAL20R6·30M. TIBPAL20R8·30M
TlBPAL20L8·25C. TlBPAL20R4·25C. TIBPAL20R6·25C. TlBPAL20R8·25C
LOW·POWER HIGH·PERFORMANCE IMPACpM PAL@ CIRCUITS
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers. .
.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5762.

PARAMETER MEASUREMENT INFORMATION
sv
Sl

b

Rl
FROM OUTPUT_....._ ...~t-_ TEST
UNDER TEST
POINT

...
fI)

R2

Q)
Q)

.c

en

...caca

LOAD CIRCUIT FOR
THREE-STATE OUTPUTS
TIMING
INPUT

./.
3.S V
/,l.SV
_ _ _..J. : - - - - - - - - O . 3 V

PULSE

~ 0.3 v
INPUT
DATA

LOW·LEVEL
PULSE

r---""",

..
I 1.5 V

-"

~

tPLH 1IN·PHASE,
OUTPUT
I

~tPHL

l:t--

-j

/1 S v I
.
"

I

I

tPHL ~
OUT -OF.pHASE
OUTPUT

\

);..,.~ \

C"

1.5 v
•

VOH

VOL

__ VOL

VOLTAGE. WAVEFORMS
PROPAGATION DELAY TIMES

OUTPUT
CONTROL

v

VOH
TI,C'".I
1.5 v

(See Note 01

NOTES:

v

I4----+t-tpLH

'

tw~

3.5V

1.5

_ _ _ _ 0.3 V

VOLTAGE WAVEFORMS
PULSE DURATIONS

---3.5
\1.5V
I ...
· - - - - 0.3

.L,1.5V

tw ~

~
v

VOL TAGE WAVEFORMS
SETUP AND HOLD TIMES

INPUT

1.5V~0.3 v

---../: 1.5V
.....--

14- 'su ..,.- 'h ~
'
-'----3SV
' 1 .SV
1 1.SV
·

C

~---3.5V

HIGH.LEVEL

~
1.5 V

(Iow-Iavel

3.5V

1.5 V
_:_ - - - - - - -

0.3 V

tpZL ~..-..... ..-- 'PLZ
I I
I'
I I
, :
~3.3 V
WAVEFORM 1 ~ 1.5 V
:~5 V
. Sl CLOSED
; ~-=-------=-;='~ VOL
(See Note BI
'PZH ~
....: jf-'PHZ
enabling 1

i

WAVEFORM 2
Sl OPEN
ISee Note BI

1

1.5 V

\:::-=-{.:::=
0.5 V

VOH
"0 V

VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE·STATE OUTPUTS

A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR .:s; 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.

FIGURE 1

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-113

E

2-114

TIBPAL20L 10-25M, TlBPAL20X4-25M, TIBPAL20X8-25M, TIBPAL20X10-25M
TIBPAL20L 10-20C, TIBPAL20X4-20C, TIBPAL20X8-20C, TIBPAL20X10-20C
HIGH-PERFORMANCE EXCLUSIVE-OR IMPACT 1M PAP CIRCUITS
02920, OCTOBER 19aS-REVISED DECEMBER 19a7

•

High Performance ... 35 MHz Min

•

Preload Capability on Output Registers
Simplifies Testing

TIBPAL20L 10'
M SUFFIX, . , JT PACKAGE
C SUFFIX, . , JT OR NT PACKAGE
(TOP VIEW)

•

Power-Up Cleer on Registered Devices

•

Package Options Include Both Plastic and
Ceremic Chip Carriers in Addition to Plastic
and Ceramic DIPs
DEVICE

I INPUTS

3·STATE

REGISTERED

I/O

o OUTPUTS

Q OUTPUTS

PORTS

'PAL20L10

12

2

0

8

'PAL20X4

10

0

4 (3-5tate buffers)

6

'PAL20X8

10

0

8 13-5tate buffers)

2

'PAL20X1O

10

0

10 (3-state buffers)

0

Vcc
o
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

o

These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices,
These IMPACT'" circuits combine the latest
Advanced Low-Power Schottky t technology
with proven titanium-tungsten fuses to provide
reliable. high-performance substitutes for
conventional
TTL
logic.
Their
easy
programmability allows for quick design of
custom functions and typically results in a more
compact circuit board, In addition, chip carriers
are available for further reduction in board space.
All of the registered outputs are set to a low level
during power-up, In addition, extra circuitry has
been provided to allow loading of each register
asynchronously to either a high or low state. This
feature simplifies testing because the registers
can be set to an initial state prior to executing
the test sequence.

fI

TIBPAL20L 10'
M SUFFIX ... FK PACKAGE
C SUFFIX .. , FN PACKAGE
(TOP VIEW)

description

u

°

u
___ uz>o::o
4

I
I
I
NC
I
I
I

3 2

1 28 2726

~5
~6

25
24

]7

23

]8

22

]9

21

~10

20
19

]11

1/0
1/0
1/0
NC
1/0
1/0
1/0

12131415161718

ou
zz

(!)

NC-No internal connection

Pin assignments in operating mode

The PAL20' M series is characterized for operation over the full military temperature range of - 55 DC to
125 DC, The PAL20' C series is characterized for operation from 0 DC to 75 DC.

IMPACT is a trademark of Texas Instruments Incorporated,
PAL is a registered trademark of Monolithic Memories Inc.
tlntegrated Schottky-Barrier diode-clamped transistor is patented by Texas Instruments, U.S. Patent Number 3,463,975.

PRODUCTION DATA documents contain information
currant as of publication date. Products conform to
specifications per the terms of Texas Instruments

:~~:~:~~i~ai~:r~1i ~~:~:~ti:f :'Io::;:::t:~~s not

Copyright © 1984, Texas Instruments Incorporated

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-115

TlBPAL20X4·25M, TlBPAL20X8·25M, TIBPAL20X10·25M
TIBPAL20X4·20C, TlBPAL20X8·20C, TlBPAL20X10·20C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACTTMPAL® CIRCUITS
TIBPAL20X4'
M SUFFIX . .. FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)

TIBPAL20X4'
M SUFFIX . .. JT PACKAGE
C SUFFIX . .. JT OR NT PACKAGE
(TOP VIEW)
OUTCLK

':5
U

VCC
I/O
110
110

U

f-

::JU uoo
__ oZ>::o::o

4

Q

I

Q

3

2

1 28 2726

5

25
24

Q

I

Q

23

n

NC

110
110

21
20
19

110

GN D <-<.:-=-....;;::.>-'

DE

12131415161718

--

~ ~Io

gg

C)

TIBPAL20XS'
M SUFFIX . .. FK PACKAGE
C SUFFIX . .. FN PACKAGE
(TOP VIEW)

TIBPAL20XB'
M SUFFIX . .. JT PACKAGE
C SUFFIX . .. JT OR NT PACKAGE
(TOP VIEW)
OUTCLK

'"U
...J

VCC
110

f::l U

U

Q

UO
__ oz>::oO

Q

4

3

2

1 28 2726

Q

25

Q

I

GND '-1..:.:'---"",",

Q

Q

23

Q

Q

n

NC

Q

21

Q

Q

20

Q

110

19

Q

DE

12131415161718

TIBPAL20X10'
M SUFFIX . .. JT PACKAGE

TIBPAL20X 1 0'
M SUFFIX . .. FK PACKAGE
C SUFFIX ... FN PACKAGE
ITOPVIEW)

C SUFFIX . .. JT OR NT PACKAGE
(TOP VIEW)
OUTCLK

'"

VCC

...J

U
f-

Q

::J U

Q

U

U

oz>OO

Q

4

Q

I
I
I

Q
Q
Q

3

2

1 28 2726
25
24

Q

6
7

23

Q

5

Q
Q
Q

GND

........'---'"'"'-'

DE

12131415161718

--

NC-No internal connection

~ ~Io 0 0
C)

Pin assignments in operating mode

2-116

Q

24

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

Q

22

NC

21

Q

20
19

Q
Q

TIBPAL20L 1O·25M, TIBPAL20X4·25M
TIBPAL20L 1O·20C, TIBPAL20X4·20C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACTTMPAL® CIRCUITS
functional block diagrams (positive logic)
'PAL20Ll0
EN:>1

"VP---- 0
0

20XC>
12

110

20
1/0
110

I/O

8

fII
....

1/0
110

II)

G)
G)

110

.c

en

110

....asas

8

C
'PAL20X4

.J EN

DE

1.

OUTCLK

[,

~

Cl
1=0

=1

4OX40P-

2o'Xi>

~ rv

~

P-

4

+

~

~ rv

-

Q

------------.....

~
10

"V

10
Q

Q

Q

----....

EN :>1

"V

110

~
--+-

~
~
...;.-

-a-

-+-t---aL..----+-

110

"

110
110
1/0
110

6
4

"V denotes fused inputs

TEXAS .."

INSTRUMENTS
POST OFFICE BOX,655012 • DALLAS, TEXAS 75266

2·117

TIBPAL20XB-25M, TIBPAL20X10-25M
TIBPAL20X8-20C, TlBPAL20X10-20C
HIGH~PERFORMANCE EXCLUSIVE-OR IMPACTTMPAL® CIRCUITS
functional block diagrams (positive logic)
'PAL20X8

~---------------------
&
4OX40

r--t---t.-+-Q
r---r--;-'-::~Q

10

20XI>

20

rv

r---~----t_~-Q

r---t---;-'-::I--Q
r---r---;'~I--Q
10

20

r---~----t_~-Q

t--t--"i--+-Q
r---r--;~I--Q

t--t--"i--+- Q
"'-.J denotes fused inputs

2-118

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265

TIBPAL20L 1O·25M
TIBPAL20L 1O·20C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACTTMPAL® CIRCUITS
logic diagram (positive logic)
I~

(1)

PRODUCT
LINES

INPUT LINES
__________________
________________
~A~

0 .. • 4'"

8···12'"

16"· 20'·' 24 •• ' 28."

~\

32··.36··39

?

. r")-.L

j

v

(23)

o

....

~

...

8

>-t1

11
(3) ..

(22)

I/O

...
A

v
16

",-;J.
v

19

(21)

1/0

'"

24

~ r......

27

.L

Q)
Q)

(20)

v

1/0

(5)
32

~19)

35
(6) ..

'"

~

.c

en
....a:sa:s
C

1/0

A

4!1

~18)

'"

43

171

PI
....
II)

(4) ..

.

1/0

48

...... .y
.1..

51
(8)

.

(17)

1/0

A

-

56

~L(16)

'"

59
(9)
64

-.... .1

67
(10) ..

(15)

1/0

1/0

....."'1

""

72

...... .1
-v

75
111 )

...

....

0'"

A

(14)

o

(13)

4 · · ' 8·"12···16···20··· 24·"28· "32"'36·'39

Pin numbers shown are for JT and NT packages.

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2·119

TlBPAL20X4-25M
TlBPAL20X4-20C
HIGH-PERFORMANCE EXCLUSIVE-OR IMPACTTMPAL@ CIRCUITS
logic diagram (positive logic)
~__________~_________
____________________~
INPUTA~
LINES
/

0-··

4-· -

8- - - 12· - - 16-'-·20 •• ,24-··28- •• 32· _. 36· ·39 \

OUTCLK ( 1-'{:l
)

~

PRODU CT
LINES

~l

3

~

. . . .1.....

;;.
11
~,

...

....

16

. . . ......1

;:::;:
19
(4) ...

c
Q)

....

r+

Q)

::r

CD
CD

~

...

r+

en

1

,

(21)

=SD
--- ~I~

27
(5)

(22)

I/O

I/O

....

24

en

I/O

.....

8

E

(23)

(20)

Q

A

32

~~
.-

tr:
.........

35
(6)

1.:1

(19)

I .....

Q

Cl

A

40

tKJD ~ ~

.........

43
(7) ...

48

H~
~ ~ IV

1.::1

51
(8) ...

Q

Cl

'....

(17)

Q

Cl

...

56

:,....... ..1

59
(9)

~

--""-t..
64

:t
67
(10)

.

J

~r

(15)

I/O

I/O

"

72

...:
75

. . . . .1

.:J

(11) ...

.......

...

0'"

4 ...

8··· 12".16· •• 20' •• 24 ••• 28 . . . 32 ••• 36' .39

Pin numbers shown are, for JT and NT packages.

2-120

(16)

TEXAS . "
INSTRUMENlS
I POST OFFICE BOX 655012· DALLAS, TEXAS 75265

(14)

~

I/O

TlBPAL20X8·25M
TIBPAL20X8·20C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACT'MPAL® CIRCUITS
logic diagram (positive logic)
~____________________
~A~
____________________~
INPUT
LINES

/ 0 •••

4".8'"

12 .. ·16 . . ·20'''24 . . ·28 . . • 32"'36"39'

OUTCLK ( 1 )

?

PRODU CT
LINES

f~ J

:i

E4>t

(23)

I/O

...

8

~¢ el
~~
....
...

(22)

-

11
(3) ...
16

£D
... ~

19

....

(4) ...

...

24
27

(21)

~

a

CI)
CI)

';1

'~
~

';l

(19)

>-;:1

(18)

(20)

.....

el

a

.- ... tl]

35
(6) ...

...

40

iF
~

171 ...

...

48
51
(8) ...

el

el

...

:

...

C
a

a

(17)

a

(16)

a

el

...

56

£D~

59

....

(9)
r

64
67
(10)

...

'- tJ]
rr::t.
,........
:~
tJ]

43

oJ:

en

CO
CO

....

32

PI
...
II)

.==9D
tJ]
.....

(5)

el

>-;:1

a

.

...
72

~~
...
"",..L

;J

75
(11) ...

...

o •••

4'"
8'" 12' •• 16' •• 20' ., 24' •• 28.' • 32'"
Pin numbers shown are for JT and NT packages.

el

itt
.....

~(15) a
.....

(14)

I/O

~

36' '39

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2·121

TIBPAL20X 1O·25M
TIBPAL20X10·20C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACT™PAL® CIRCUITS
logic diagram (positive logic)
INPUT LINES

~

I

________________

0 •••

4...

~A~

________________

~

8 ••• 12••• 16 ••• 20 ••• 24••• 28 ••• 32··· 36··39 \

-'----f)

OUTCLK (1)

~ ~-a
.- '"
'";l

0

PRODU CT
LINES

3

'-'-

E4>t
8

~~
-.-

11
(3) ....

IE

~

.

....

....

R;D

27

..

~

-~
......,

32

.

36

.

(6)

....

.~
'......, ....

40
43
(7)...:

....

51

....
'"

....
56

;::;:
-~
:=:::

-

69

..

(9)

.

~2!l. Q

~

'";J

~

'";J

~

'";:1

67
(10) ...

(20)

V

Q

v

(19)

Q

Cl

(18)
Q

V

Cl

i.J

(17)

V

Q

Cl

~
Cl

~
- ~

64

~
";J

(15)

V

Q

Q

Cl

..

'"

~~~

72

.

,1.....

75

.!:!1l

........

0-··· 4'"

8'"

12"

• 16 ••• 20 ••• 24' •• 28"

• 32'"

36·' 39

Pin numbers shown are for JT and NT packages.

2-122

Q

Cl

,~
,~

48

(8)

(22)

~

Cl

24

(S)

~

fb,.

19
(4) ...

Q

Cl

Eo
~

16

(23)'

Cl

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

Cl

~

Q

TlBPAL20L 10·25M, TlBPAL20X4·25M, TIBPAL20X8·25M, TIBPAL20X10·25M
TIBPAL20L 10·20C, TIBPAL20X4·20C, TIBPAL20X8·20C, TIBPAL20X10·20C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACTtMPAL@ CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: M suffix. . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°e
e suffix .............................. ooe to 75°e
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions
PARAMETER

MIN
4.5
2

Vee
VIH
VIL
10H
10L

Supply voltage
High-level input voltage
Low-level input voltage
High-level output current
Low~level output current

fclock

elock frequency

tw

Pulse duration, clock, see Note 2

th
TA

MIN
4.75
2

0.8
-2
12
25

0
15
20
25

I High

I

Low
Setup time, input or feedback bafore OUTeLKt
Hold time, input or feedback after OUTeLKt
Operating free-air temperature

t su

-25M
NOM MAX
5.5
5
5.5

0
-55

125

-20C
NOM MAX
5.25
5
5.5
0.8
-3.2
24

0
10
14
20

35

0
0

75

UNIT
V
V
V
mA
mA
MHz
ns
ns
ns
ns
°e

NOTE 2: The high and low clock pulse durations cannot both be at the minimum values specified. Their sum must be equal to or greater
than the minimum clock period. which is the reciprocal of the maximum recommended clock frequency.

electrical characteristics over recommended free-air operating temperature range
PARAMETER

Vee = MIN,
Vee - MIN,
Vee - MIN,

VIK
VOH
VOL
10ZH
10ZL

Outputs
1/0 ports

Outputs
1/0 ports

Vee

= MAX,

Vee

= MAX,
= MAX,
= MAX,
= MAX,
= 5 V,
= MAX,

Vee
Vee
Vee

II
IIH
IlL
10S§
Ice

TEST CONDITIONSt

Vee
'20X4, '20X8, '20Xl0
'20Ll0

Vee

II

-25M
MIN

TYP*

2.4

3.2
0.25

= -18 mA

10H - MAX
10L - MAX
Vo

= 2.7 V

= 0.4 V
= 5.5 V
VI = 2.7 V
VI = 0.4 V
Vo = 0
VI = 0
Vo

VI

-20C
MAX
-1.2

MIN

TYP*

2.4

3.3
0.35

0.4
20
100
-20
-250
0.1
20
-0.25
-130

-30
120
120

180
165

-30
120
120

MAX
-1.2

UNIT
V
V
V

0.5
20
100
-20
-250
0.1

mA

20
-0.25

~
mA

-130

mA

180
165

mA

~A

~

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*AII typical values are Vee = 5 V, TA = 25°e.
\
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

TEXAS ."

INSTRUMENlS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265

2-123

TlBPAL20L 10·25M, TIBPAL20X4·25M, TIBPAL20XB·25M, TIBPAL20X10·25M
TIBPAL20L 10·20C, TIBPAL20X4·20C, TlBPAL20XB·20C, TIBPAL20X10·20C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACTTMPAL® CIRCUITS
switching characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER

FROM

TO

TEST CONDITIONS

f max
ted
ted
ten
tdio
ten
tdis

1,1/0

0,1/0

MIN
25

-25M
TYpt MAX

MIN

-20C
TYpt

MAX

35

UNIT

25
20

12
10

20
15

MHz
no
no

OUTCLKt

Q

Rl = 200 0,

12
10

O'E
'1iET

Q

R2 = 3900,

7

20

7

15

no

Q

CL=50pF

7

7

1,1/0
1,1/0

0,1/0
0,1/0

20
25
25

15
20
20

ns
ns
ns

15
15

15
15

tAli typical values ar. at VCC = 5 V, TA = 25·C .

. . programming information
_

C
m
r+

m

en
:::T

Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 995-5762.

CD
CD

r+

en

2-124

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265

TIBPAL20L 1O·25M, TIBPAL20X4·25M, TIBPAL20XB·25M, TIBPAL20X10·25M
TIBPAL20L 1D·2DC, TIBPAL2DX4·20C, TIBPAL2DXB·20C, TIBPAL2DX1D·20C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACT™PAL® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
5V

SI

b

Rl
FROM OUTPUT_+_. ._ . - _ TEST
UNDER TEST
POINT
CL
(Saa Nota A)

R2

'---4

LOAD CIRCUIT FOR
THREE-STATE OUTPUTS
TIMING
INPUT

DATA
INPUT

/.

3.5V

A

l .5V
_ _ _..J. : - - - - - - - - 0 . 3 V
... tsu~th'"
:
+---3.5V
1.5V
1.5V
0.3 V

~

HIGH.LEVEL
~ - --3.5 V
PULSE
----./rl.5V
1.5V~
:.....- tw - . . :
0.3 V

LOW·LEVEL
PULSE

:.
tw~
~
I.5V

.L
, l •5 V

\:;:;;;--3.5 V

--':
tPLH~
IN.pHASE
OUTPUT

1
I

I·
0.3
~tPHL

,'"

1.5V

,

I

tpHL ~
OUT-DF.pHASE
OUTPUT

i1

\

V

i-;:~
VOH
~
VOL

I4----*-tPLH

1

1.5 V

FI

1.5 V VOH

~. ______-J.

VOL

(Sea Nota D)

VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES

CD
CD

3.5V

.r:.
en

0.3V

...caca

VOLTAGE WAVEFORMS
PULSE DURAT)ONS

VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES

INPUT

1.5V
--- -

...en

OUTPUT
CONTROL
(low·la.al

1.5 V
,
tpZL ~:e-

anabling)
WAVEFORM 1
SICLOSED
(SaaNoteB)

o

~

3.5V
1.5 V
~ ________ 0.3V

11'""tPLZ

I: .. 0.3=3.3V
~
I
1.5 vi'
V
VOL

WAVEFORM 2
S10PEN
(Sae Nota B)

':

::--~.==

I

tPZH~

1

1.5V

...:

~tPHZ T

~-:..{.::=
0.3V

VOH

"0 V

VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR s 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch 51 is closed.

TEXAS . .

INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS. TEXAS 75265

2-125

TIBPAL20L 10·25M, TIBPAL20X4·25M, TIBPAL20X8·25M, TIBPAL20X10·25M
TIBPAL20L 10·20C, TIBPAL20X4·20C, TIBPAL20X8·20C, TIBPAL20X10·20C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACTTMPAL® CIRCUITS
preload procedures
preload procedure for registered outputs

With Vee at 5 volts, raise Pin 13 (OE) to VIHH to disable the outputs and clear the
registers (output goes low). Since the outputs are low, only high levels need be preloaded.
Raise the selected output to be preloaded high to VIHH.
Lower Pin 13 to VIH.
Remove the voltages applied to the outputs. (At least a 1OO-ns wait is required between step 3
and step 4)
Lower Pin 13 to VIL to verify preload.

Step 1
Step 2
Step 3
Step 4
Step 5

i------i----- --------- VIHH
I

(PRELOAD PIN 13)

11

OE

...c

I

1
1100 ns

~N

i

SELECTED
OUTPUT
TO PRELOAD

D)

(I)

::r
CD
CD

...en

Q

1 100 ns

~ ~

V
1

D)

I

100 nS I

I

1

:1

Il

;..----I.~-!~T

~

XXXXXXXXX\ _

----::
VIL

VOL
VERIFY

PRELOAD WAVEFORMS

security fuse programming

PIN 10

I

.---Jill

" ' ___ u",.
tw3----+~

•

0 V

SECURITY FUSE PROGRAMMING WAVEFORMS
NOTE: Pin numbers shown apply only for the DIP package. If a chip carrier socket adaptor is not used, pin numbers must be changed
accordingly.

2-126

, TEXAS"

INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265

TlBPAL20L 1O·30C, TIBPAL20X4·30C, TIBPAL20X8·30C, TIBPAL20X10·30C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACT""PAL® CIRCUITS
02920. DECEMBER 19B7

•

Functionally Equivalent to MMI PAL® Series
24XA

•

Preload Capability on Output Registers
Simplifies Testing

Vcc

•

Power· Up Clear on Registered Devices
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
I

3-STATE

INPUTS

o OUTPUTS

REGISTERED
Q

OUTPUTS

1/0
1/0
1/0

110
1/0
1/0

110

110

PORTS

1/0

'PAL20L10

12

2

'PAL20X4

10

0

'PAL20X8

10

0

8 (3-state buffers)

2

'PAL20Xl0

10

0

10 f3-state buffers)

0

0

(TOP VIEWI

o

•

DEVICE

TIBPAL20L 10'
C SUFFIX ..• JT OR NT PACKAGE

o

8

4 (3-state buffers)

II

GN

6

TIBPAL20L 10'
C SUFFIX ... FN PACKAGE
(TOP VIEWI

description

U

These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices.
These IMPACrM circuits combine the latest
Advanced Low-Power Schottkyt technology
with proven titanium-tungsten fuses to provide
reliable, high-performance substitutes for
conventional
TTL
logic.
Their
easy
programmability allows for quick design of
custom functions and typically results in a more
compact circuit board. In addition, chip carriers
are available for further reduction in board space.

U
U

0

_Z>O:::o
4 3

NC

2

1 282726

5

25

6

24

7

23

8

22

9

21

10

20

11

19

1/0
1/0
1/0
NC
1/0
1/0
1/0

12131415161718

All of the registered outputs are set to a low level
during power-up. In addition, extra circuitry has
been provided to allow loading of each register
asynchronously to either a high or low state. This
feature simplifies testing because the registers
can be set to an initial state prior to executing
the test sequence.

NC-No internal connection

Pin assignments in operating mode

The TIBPAL20' C suffix devices are characterized for operation from ooC to 75°C.

IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories Inc.
tlntegrated Schottky-Barrier diode-clamped transistor is patented by Texas Instruments, U.S. Patent Number 3,463,975.

PRODUCTION DATA d••umonts contain informati.n
.umnt al 01 publication dOlo. Products ••nform to
spacificati.ls per the terms of Telal Instruments

:.=.~~ar::I~i ~=::i:; :.r::::::~. not

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

Copyright

© 1987, Texas Instruments Incorporated

2-127

TIBPAL20X4·30C, TIBPAL20X8·30C, TIBPAL20X10·30C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACT"'PAL@ CIRCUITS
TIBPAL20X4'
C SUFFIX ... JT OR NT PACKAGE

TIBPAL20X4'
C SUFFIX •. : FN PACKAGE

ITOPVIEW)

ITOPVIEW)

OUTCLK

:J

VCC

1=

110
110
110

u

U UO 0
__ ::>
02>::::::::::
4 3 2 1 282726
25

Q

Q
Q

I
NC

Q

110
110
110
GND '-<.;;:.-...:.::J...

II

7
8

23
22
21

20
19

DE

cm

TIBPAL20XS'
C SUFFIX .•. JT OR NT PACKAGE

TIBPAL20XS'
C SUFFIX ... FN PACKAGE

Cit

ITOP VIEW)

ITOPVIEW)

(I)

OUTCLK

::r

110

12131415161718

VCC
110

CD
CD

Q

U)

Q

Q

P+

5

Q

I

Q

6
7

I.
NC

Q
Q
Q

8
9

I

110

20

10
11

I

DE

4 3 2 1 282726
25
24
23
22
21
19
12131415161718

TIBPAL20X10'
C SUFFIX •.. JT OR NT PACKAGE

TIBPAL20X10'
C SUFFIX •.. FN PACKAGE

ITOP VIEW)

ITOPVIEW)

OUTCLK

:J

VCC

1=
::>U

Q

U

U

~~oz>OO

Q

Q
Q
Q
Q
Q
Q

4 3 2 1 282726
25
24
23
22
21

Q

20

Q
GND

--..;;=--....:.::....

19

DE

12131415161718

NC-No' internal connection

Pin aSSignments in operating mode

2·128

Q
Q

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265

TIBPAL20L 10·30C, TIBPAL20X4·30C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACT"'PAL® CIRCUITS
functional block diagrams (positive logic)
TIBPAL20L'O'
&

EN;>1

'ilP---- 0

0----0
20XI>
12

I/O
20
P-<~4-+-1/0

1:>-<>d-4-+- 1/0

P-<~"'-I/O

I:>-<>d-"'-

I/O ,

...
U)

CD
CD

.c

D-,

~

~

o

'il

h

1D

I/O

'il

I-;-

I/O

~

~

'\

~
....:;.-

"'\

~
~

I----+-

I/O
I/O
I/O

""-

I/O

6

4
'"\..t denotes fused inputs

,

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

2·129

TlBPAL20XB·3DC. TIBPAL2DX1D·3DC
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACT"'PAL® CIRCUITS
functional block diagrams (positive logic)
TIBPAL20XB'

OE------------~--------~;---,
OUTCLK.----------..,-....---i>

Q

Q

Q

•..

t---t----L-.JL- a
Q

C

I»
I»
(I)

Q

..

:::r

\--~fH,--I-

CD
CD

I/O

l : > - t i - - - - + - 1/0

(I)

TIBPAL20X10'

OE-----------------------da.~_,
OUTCLK--------------i>

t--t--1---+-

Q

t---r--1--...:t...-Q
t---t---1---=l--Q
t---t---"1---=l-- Q

t---r--1--+--Q
t---r--;---=l-- Q

t--t--"1--=+-':"'Q
Q

Q

"'" denotes fused inputs

2·130

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TlBPAL20L 10-30C
HIGH-PERFORMANCE EXCLUSIVE-OR IMPACT'MPAl® CIRCUITS
logic diagram (positive logic)
I~

I (11

PRODU CT
LINES

INPUT
__________________

0 ---

LINES
________________

~A~

4 -- -

8··- 12·_· 16 _ •• 20'"

24'"

28'·' 32'"

~\

36 .. 39

~

,>..L...

3

o

..,

E4>t

~

8

~(221

11
(31 ...

v

...

16

I

~

19
(41 ...
24

. . . . ....L

27
(51

(231

...

A

32

(201

...

-

40

(191

I

....... ,.L

...

~

43
(71 ..
~

48

(181

.. J

~I ....

EI
...
en

Q)
Q)

110

J:

en
ca
ca

...

110

C

110

I

~171

51

110

J

....... ,1.

35
(61 ...

110

110

~

56

..J.

..,VJ

59
(91

(161

110

~

64

....... r.I.

...

67
(10) ...

.....

...

(151

I

110

72

r
75
(111 ...

(141

.....

...

o •••

4··· 8'"

12··· 16·· ·20· •• 24·· • 28· •• 32'"

36' '39

-

o

(13)

Pin numbers shown are for JT and NT packages.

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265

2-131

TIBPAL20X4·30C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACT'MPAl@CIRCUITS
logic diagram (positive logic)
~____________________
~A~
____________________~
INPUT
LINES

I
OUTCLK (1)
PROOU CT
LINES

0 ...

4 ...

8 ' " 12 ••• 16 •••

.....

2~"

• 24 . . . 28 •• , 32 ••• 36 . . 39 \

v

?
3

J!4>t

')-rl.
v
....

(23)

........ to!..

(22)

I/O

8

~
....

11
(3) ,.;.

11

-;..

16

;;;">-r!

19
(4) ...

c
C\)

:~
- ....

24

en

:r-

27
(5) ..

r+

32

CD
CD

...

til

fJ][fL(20)
10
v

Q

Cl

~

~
- .... ~

Rv

(19)

iF
~
-

R

(18)

~

35
(6)

I/O

.....

v

r+

C\)

(21)

I/O

...
40
43

(7) ...

...

10

10

;=::
51
(8) ...

v

Q

Cl

fJ]

~fJ]

48

Q

Cl

10

ttl,.,. (17)
v

Q

Cl

v
56

~~

59
(9)

-

64

~~I

67
(10) ..

...

(15)

I/O

I/O

~
~

72

""'to!..
v

75

.!!1!t...

....
0','

4.·.

8·.,12 . . . 16 .. ·20 . . ·24 . . ·28 .. • 32 . . . 36' ·39

Pin numbers shown are for JT and NT packages.

2·132

(16)

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS ?5265

~

(14)

~

I/O

TIBPAL20XB·30C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACT"'PAL® CIRCUITS
logic diagram (positive logic)
~

I

INPUT LINES
________________
________________

0 ...

~A~

4...

8 .. ' 12 . . . 16· . . 20· . . 24'"

28 . . • 32'"

~

36"39 \

OUTCLK I1 I ...

v

PRODU CT
LINES

?
:i

>-r!

~

1231

[

~
- ~~

8

':,

11

1221

liD

Q

I ......

....

131
r

'"

.Eo
... ~

16

10

19
141 ...

I;l

(211

v

Q

C1

-r

'"

II
..
U)

Q)
Q)

~
..
.-~ 1.:1
::t...
~
Ir:l
~~
.- ... ~ .......
~
'- ~
;~
-- ... ~
=
5D~
...

24

.=S;D

27
(51 ...

-;...

10

1.:1
I ....

1201

Q

C1

10

35

0

as
as

,

32

.c

(191

v

C

Q

C1

161
40

1181

10

43

Q

C1

171 ...

...

'"

48

10

51
181 ...

';J.

1171

";:l

1161

>;::t

1151

v

Q

C1

...

56

10

59
191 ...

v

Q

C1

r

64

10

67
1101 ...

'_

...

72

....

_S~

75
1111 ..

....

.

0'"

4'"

8'"

12·.·16'"

20'"

24'"

28."

32'"

36"39

-

;V

Q

C1

1141

1/0

~

Pin numbers shown are for JT and NT packages.

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2·133

TIBPAL20X10·30C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPACT'" PAL® CIRCUITS
logic diagram (positive logic)

~____________________~A_____________________~
INPUT LINES

_......

10

... 4 ...

8.·. 12- . . 16·· • 20· . . 24.. • 28 .. - 32.. • 36-·39 \

OUTCLK (11

0

~~'~'
19t>
- ...

-

PAODU CT
LINES

10

3

.ill.t:>t

.-

(221

'";J.

(211

~

";l

(201

t1!
~ flJ
.ED flJ

~
,V

(191

I.:J.

(181

!t:l
v

(171

Ii:L

(161

~
L. .....

, 11
(31 ...

...

f:l;
1O

1O

19

C1

...

:~

24

-

27
(51

....

~
-

32

-

35
(61 ...

,'"

40

43

...

48

1O

1O

Q

~

1O

Q

IV

Q

e1

Q

e1

...

56

;~

-- ~

59

....

(91

...

~

1O

V

-

,

1O

67
(101

Q

e1

~
~
'- .... ~

64

Q

e1

....

"RD tJ; 1.1 ""

72

_

10

_

75
(111 ..

....

0-- - 4' - - 8 - - - 12- - - 16- - - 20- - - 24- - - 28- - - 32- - - 36- - 39
Pin numbers shown are for JT and NT packages.

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TeXAS 75265

v

e1

...~

r

2·134

v

Q

e1

1O

51
(81 ...

v-----

e1

~

....

(71 ...

"V""- Q

C1

£D t1!

16

(41

Q

~

'tl.

8

E

V

C1

~

Q

TIBPAL20L 10-30C, TIBPAL20X4-30C, TIBPAL20X8-30C, TIBPAL20X10-30C
HIGH-PERFORMANCE EXCLUSIVE-OR IMPACT""PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ...................................' . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: e suffix ............................. " ooe to 75°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: These ratings apply except ·for programming pins during a programming cycle.

recommended operating conditions
-30C

PARAMETER

MIN

NOM

4.75

5

MAX
5.25

UNIT

Vee

Supply voltage

VIH

!:'iigh-Ievel input voltage

VIL

Low-level input voltage

IOH

High-level output current

-3.2

mA

IOL

Low-level output current

24

mA

fclock

elock frequency

22.2

MHz

tw

Pulse duration, clock, see Note 2

tsu
th
TA

Hold time, input or feedback after OUTeLKi

0

Operating free-air temperature

0

2

5.5
0.8

0

I High

15

I Low

25

Setup time, input or feedback before OUTeLKi

V

II
..
..

V
V

II)

G)
G)

ns

30

.c
en
ca
ca

ns
ns
75

°e

NOTE 2: The high and low clock pulse durations cannot both be at the minimum values specified. Their sum must be equal to or greater

C

than the minimum clock period, which is the reciprocal of the maximum recommended clock frequency.

electrical characteristics over recommended free-air operating temperature range
PARAMETER

TEST CONDITIONSt

VIK

Vee = MIN,

II = -18 mA

VOH
VOL

Vee = MIN.
Vee - MIN.

10H = MAX
IOL - MAX

Vee = MAX.

Vo = 2.7 V

Outputs
IOZH

1/0 ports
.Outputs

-30C
MIN

TYP*

MAX
-1.2

2.4

3.3

UNIT
V
V

0.35

0.5
20
100
-20

V
pA
pA

Vee = MAX,

Vo = 0.4 V

II

Vee = MAX.

VI = 5.5 V

0.1

mA

IIH
IlL

Vee = MAX.
Vee = MAX,

VI = 2.7V
VI ='0.4 V

20
-0.25

pA
mA

-130

mA

10ZL

1/0 ports

10S§
lee

t For

I '20X4, '20X8, '20X10
I '20L10

Vee = 5 V,

Vo = 0

Vee = MAX.

VI = 0

-250

-30
120

180

120

165

mA

conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

*All typical values are Vee = 5 V. TA = 25 e . ·
o

§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

TEXAS ",

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-135

TIBPAL20L 10-30C, TIBPAL20X4-30C, TIBPAl20XB-30C, TIBPAL20X10-30C
HIGH-PERFORMANCE EXCLUSIVE-OR IMPACrPAL® CIRCUITS
-switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER

FROM

TO

fmax*

With Feedback

TEST CONDITIONS

MIN

-30C
Typt

MAX

23
10

30
15

ns
ns

UNIT

22.2

MHz

1,1/0

0,1/0

OUTCLKt

Q

R1

= 200 Il,

DE
OEt

Q

R2

= 390 Il,

11

20

ns

tdis

Q

CL

= 50 pF

ten

1,1/0

~is

I, I/O

0,1/0
0,1/0

10
19
15

20
30
30

ns
ns
ns

tDd
tDd

ten

t All typical values are at VCC = 5 V, T A = 25°C.
_

..

C

:t: f max (with feedback)

=

1

tsu + tpdlCLK to Q)

• f max without feedback can be calculated as f max (without feedback)

=

.

1

twhogh + twlow

programming information

!
I»
C/)

=
ur
:::r'

2-136

Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers,
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request, Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5762.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

TlBPAL20L 10-30C, TlBPAL20X4-30C, TIBPAL20XB-30C, TIBPAL20X10-30C
HIGH-PERFORMANCE EXCLUSIVE-OR IMPAC~PAL® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
5V
51

b

Rl
FROM OUTPUT_. ._ ....~t-_ TEST
UNOER TEST
POINT
CL
(Sao Nota A)

R2

1--_--.

LOAD CIRCUIT FOR
THREE-STATE OUTPUTS
./.
3.5 V
l .5V
- - -.....-:- - - - - - --0.3 V
,.. tsu ..,.- th ....
'
:----3.5V
DATA
1.5V
1.5V
INPUT
0.3 V

TIMING
INPUT

A

~

_t

~

LOW-LEVEL
PULSE

~1.5V

\1.5~--3.5V

I

I

tPLH~
IN-PHASE
OUTPUT
tpHL

1
I

1.5V

~

OUT.QF-PHASE
OUTPUT
(Soe Nota D)

\

0.3 V

~tPHL

"

i

~-;:~ VOH

I
~
I.
VOL
I4---*-tPLH

1

'C'"..I VOH

T l .5V

1•5V
\'._ _ _...J.

VOL

VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES

tw - :
-·1.5V

i.r-

fI)

l)
CD
.c

3.5V

~---0.3V

(I)

ca
ca

VOLTAGE WAVEFORMS
PULSE DURATIONS

VOL TAGE WAVEFORMS
SETUP AND HOLD TIMES

INPUT - 1 1 . 5 V

II
..

HIGH-LEVEL ~---3.5 V
1 1.5V
1.5V
I
_
PULSE
I
w
I
O.3V

OUTPUT
CONTROL

~
1.5 V

(low-Ievol
enabling)

I.

tPZL'-""
I

I

51 CLOSED
(Sao Nota B)

WAVEFORM 2
51 OPEN
(5.. Nota B)

-i--------

O.3V

..... II-tPLZ
II

I :

WAVEFORM1~

C

3.5V

. 1.5 V

i1 I1~5V

=3.3 V

1.5V

I \..!:!!..--IJ..:--=-----=-;,;,:,

tpZH ~

...:

~tPHZ

~------::.i-==
1.5 V

.

VOL

VOH

0.5 V

.. 0 V

VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR :;; 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS. TEXAS 15265

2-137

TIBPAL20L 1O·30C, TIBPAL20X4·30C, TIBPAL20X8·30C, TIBPAL20Xl0,30C
HIGH·PERFORMANCE EXCLUSIVE·OR IMPAC"f'MPAL® CIRCUITS
preload procedures
preload procedure for registered outputs
Step 1
Step 2
Step 3
Step 4
Step 5

With Vee at 5 volts. raise Pin 13 (OE) to VIHH to disable the outputs and clear the
registers (output goes low). Since the outputs are low. only high levels need be preloaded.
Raise the selected output to be preloaded high to VIHH.
Lower Pin 13 to VIH.
Remove the voltages applied to the outputs. (At least a 1OO-ns wait is required between step 3
and step 4)
Lower Pin 13 to VIL to verify preload.
i------~.-

I

(PRELOAD PIN 13)

I

I

1100 ns
MIN

I--+j

I

- - - - - -- - - - - - -

lOa nS I

1 100 ns

H

~
I

MIN

MIN

VIHH

I

II

Vr----4\T-r;----::

I
SELECTED
OUTPUT
TO PRELOAD

i

Q

XXXXXXXXX\ .

I

VIL

I~

~

VOL

VERIFY

PRELOAD WAVEFORMS

security fuse programming

PIN 10

I

~4

\-----""
t w 3 - - - -... ·

OV

SECURITY FUSE PROGRAMMING WAVEFORMS
NOTE: Pin numbers shown apply only for the DIP package. If a chip carrier socket adaptor is not used, pin numbers must be changed
,
accordingly.

2-138

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TIBPAL20SPB·30M, TIBPAL20SPB·20C
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS WITH PRODUCT·TERM SHARING
03088. DECEMBER 1987

•

True Product·Term Sharing Option

•

High·Performance Operation:
TlBPAL20Sps·20C tpd ... 20 ns
TIBPAL20Sps·30M tpd ... 30 ns

TIBPAL20SP8
M SUFFIX ... JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE
ITOPVIEW)

Vee

•

Choice of Output Polarity

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Depandable Texas Instruments Quality and
Raliability

I

o
I/O
I/O
I/O
I/O
1/0
1/0

o

II
II)

TIBPAL20SPS
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE

description
These programmable array logic devices feature
high-speed product-term sharing. They combine
the Advanced Low-Power Schottky technology
with proven titanium-tungsten fuses. These
devices will provide reliable, high-performance
substitutes for conventional TTL logic. Their
easy programmability allows for quick design of
custom functions and typically result in a more
compact circuit board. In addition, chip carriers
are available for further reduction in board space.
Product-term sharing allows a choice of one Or
two outputs for any product term. The 56
product terms are grouped in multiples of 14 per
output pair, not counting the 8 enable terms (1
per output). Any number of product terms (from
o to 16) can be associated with one output. In
addition, a product term may be common to two
outputs. In addition to the product term sharing,
these devices feature a polarity option for each
output.

~

Q)

.c

(TOPVIEWI

CI)

U

....CISCIS

u
___ u
z>_o
5

4 3 2 1 282726
25

6
7

24
23

8

22

9
10

20

C

21

11

19
12131415161718

--cu--o
zz
(!)

NC - No internal connection
Pin assignments in operating mode

;:
w

The TIBPAL20SP8-30M is characterized for
operation over the full military temperature range
of - 55°C to 125°C. The TIBPAL20SP8-20C is
characterized for operation from O°C to 75°C.

:>w
a::

Q.

t-

(.)
::;)

C

oa::

IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a ragistered trademark of Monolithic Memories Inc.

PRODUCT PREVIEW dac.m.....ontoln Infannatlon
an prod.... I. tile IIrmall.. or dlllgR ~hl" of
do..la, ....t. Cha,o.toristic dltl a.~ atha,

:::::::0ri;t~::I:::II.;,T=~==
pradaell wlthalt ooti...

Q.

Copyright @ 1987, Texas Instruments Incorporated

TEXAS ",

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-139

TIBPAL20SPB·30M, TIBPAL20SPB·20C
HIGH·PERfORMANCE IMPACf'MPAL® CIRCUITS WITH PRODUCT·TERM SHARING
logic diagram (positive logic)
,'1)
INPUT LINES
A
I

,

0

12)

\

4

8

12

16

20

24

28

32

38

PRODUC;
LINES

(3)

~

0

1

···

14)

.~

en
::r

...
CD
CD

·
··

~l
""
. I

18

L(20)

15

··
·

CD
15)

v

··
·

(6)

1

;.f

1

o
c
c:
o-t

19)

~

m
S
m

1

··
·

I/O

-

47

~J

···

55

.

63

1

(16),
10

115)

v

114)
113)

Ill)

-

~

2-140

(171

v

··
·

110)

I/O

39

56

"tI

118)

v

48

"tI

I/O

I

40

~

I/O

31

··
·

(81

(19)

v

32

17)

'fO

23

24

U)

o

7

8

Ec

122)

v

·TEXAS ."

INSTRUMENTS
POST OFfiCE BOX 655012 • DALLAS. TEXAS 75285'

o

TlBPAL20SPB·30M, TIBPAL20SPB·20C
HIGH·PERFORMANCE IMPACT™PAL® CIRCUITS WITH PRODUCT·TERM SHARING
functional block diagram (positive logic)

&

EN

40 • 64

'V

'Q

0

2Q

0

;",

'V
EN

II)

'V

[>
'4

20

'V

'V
EN

en

3Q

'V

110

...
CCI
CCI

C

;",
4Q

110

5Q

110

6Q

110

7Q

110

8Q

110

;",

EN

'V

CD
CD

.c

;",
EN

II
...

;",

'V
EN

;",
EN

'V

;",

'V
EN

~

W

:>W
a:
Q.

I-

0

::J

C

0
a:
Q.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 •

DALL~S.

TEXAS 75265

2-141

TIBPAL20SP8·30M, TIBPAl20SP8·20C
HIGH·PERFORMA,.CE IMPACr"PAL@ CIRCUITS WITH PRODUCT·TERM SHARING
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: -30M suffix ....................... -55°e to 125°e
-20e suffix .......................... , ooe to 75°e
Storage temperature range ......................................... - 65 °e to 1 50 0 e
NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating condtions

•
C

....

I»
I»

en

MIN
4.5
2

Supply voltage
High-level input voltage
low-level input voltage
High-level output current
Low~level output current
Operating free-air temperature

Vee
VIH
Vil
IOH
IOl
TA

-30M
NOM MAX
5
5.5
0.8
-2
12
125

-55

MIN
4.75
2

-20C
NOM MAX
5
5.25
0.8
-3.2
24
75

0

UNIT
V
V
V
mA
mA
·e

electrical characteristics over recommended operating free·air temperature range

::::r

-30M
TYPJ MAX
-0.8 -1.5
3.2
0.3
0.5

-20C
TYP* MAX
-0.8 -1.5
3.2
0.3
0.5

CD
CD

PARAMETER

(I)

VIK
VOH
VOL

Vee = MIN,
Vee = MIN,
Vee = MIN,

IOH - MAX
IOl = MAX

IOZH§

Vee = MAX,

Vo = 2.7V

100

100

p.A

IOZl§

Vee = MAX,

Vo = 0.4 V

-100

-100

~A

mA

....

"'0

oo

MIN

II = -18 mA
2.4

MIN
2.4

V
V
V

II

Vee = MAX,

VI = 5.5 V

0.2

0.2

Vee = MAX,

VI = 2.7 V

25

25

p.A

III §

Vee = MAX,

VI = 0.4 V

-0.08 -0.25

-0.08 -0.25

mA

lOS'

Vee = MAX,

Vo = 0
Outputs open,

ei

Vee =MAX,
VI = 0
f = 1 MHz,

eo

f = 1 MHz,

-30

-70

-130

140

180

-30

-70

-130

mA

140

180

.mA

VI = 2 V

5

5

pF

Vo = 2 V

6

6

pF

tFor conditions shown as MIN or MAX use the appropriate value specified under recommended operating conditions.
~AII typical values are at Vee = 5 V. TA = 25·e.
§I/o leakage is the worst case of IOZl and III or 10ZH and IIH. respectively.
'Not more than one output should be shorted at at time and duration of the short-circuit should not exceed one second.

c:

n-I

"'0

:u
m

<
-

~

2-142

UNIT

IIH§

lee

:u

TEST CONDInONst

TEXAS'"
INSTRUMENlS
POST OFFICE

aox 655012 • DALLAS. TEXAS ~6285

TIBPAL20SPB·30M, TIBPAL20SPB·20C
HIGH·PERFORMANCE IMPACTTMPAl® CIRCUITS WITH PRODUCT·TERM SHARING
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
lpd
len
ldis

FROM

TO

I,

0,

I/O

I/O

I,

0,

I/O

I/O

I,

0,

I/O

I/O

TEST
CONDITIONS

-20C

-30M
MIN

MAX

30

15

20

no

16

30

16

20

ns

,,,

30

16

20

ns

MAX

15

Rl = 200 [l,
R2 = 390 [l,
See Figure 1

MIN

UNIT

TVP

TYP

programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications. algorithms. and the latest information on hardware. software. and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available. upon request. from the nearest TI field sales office. local
authorized TI distributor. or by calling Texas Instruments at (214) 997-5762.

PI
~

Q)
Q)

.t:

U)

...co
CO

C

~

w

:>w
a::

a..
tO
:>
C

oa::

a..

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-143

TIBPAL20SPB·30M, TIBPAL20SPB·20C
,HIGH·PERFORMANCE IMPACf'MPAL@ CIRCUITS WITH PRODUCT·TERM SHARING
PARAMETER MEASUREMENT INFORMATION
SV
Sl

L
Rl

FROM OUTPUT _ . ._ ...._ ..._
UNDER TEST
R2

CL
(See Note A)

•

LOAD CIRCUIT FOR
THREE-STATE OUTPUTS

cC»

\.1~ -;

INPUT J , l . S V

r+

C»

en
:::T
CD
CD

TEST
POINT

tpd
IN-PHASE
OUTPUT

r+

I'"

,
:

tpd ,..

en

~I,
!l.SV

I·
I..

- - - 3.S V
0.3 V

~I tpd

OUTPUT
CONTROL
(low-level
enabling)

~3.SV
1.SV
ten~

:,+--VOH

I~
I
VOL

I

I"

OUT-OF-PHASE
OUTPUT
(See Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES

~I

tpd

I:r.::

VOH

/ll.SV
--VOL

,

14-

, I'

WAVEFORM 1
Sl CLOSED
(See Note B)
WAVEFORM 2
S10PEN
(See Note B)

1.SV

_1 ______ 03 V
,

--r\:

1.S V

~

.

14-- tdis

I',
II ~VOL

I ~-==~-=

ten-+l!+-

-+I

l4- tdis

l.

I _____

=3.3 V
+O.S V
VOL

-t.-= VOH

~
LVOH-~'S
I

1.S V

.

V

=OV

VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance and is SO pF for tpd and ten, S pF for 'dis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. AII.input pulses have the following characteristics: PRR s 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
0, When measuring propagation delay times of 3-state outputs, switch 51 is closed.

FIGURE 1

"'0

::1:1

o
C

c:

n-I

"'0

::1:1

m

:S

m'

~

2-144

TEXAS "",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TIBPAL22V10M TIBPAL22V1 DAM
TIBPAL22V1 DC, TIBPAL22V10AC
HIGH-PERFORMANCE IMPACT""PROGRAMMABLE ARRAY LOGIC
02943, OCTOBER 1

•

Second Generation PAL Architecture

•

Choice of Operating Speeds
TIBPAL22V10AC ... 25 ns Max
TIBPAL22V10AM ... 30 ns Max
TIBPAL22V10C ... 35 ns Max
TIBPAL22V10M ... 40 ns Max

DECEMBER 1987

M SUFFIX ... JT PACKAGE
C SUFFIX ... NT PACKAGE
(TOP VIEW)

ClK/I

•

Increased Logic Power - Up to 22 Inputs
and 10 Outputs

•

Increased Product Terms - Average of 12
per Output

•

Variable Product Term Distribution Allows
More Complex Functions to be Implemented

•

Each Output is User Programmable for
Registered or Combinatorial Operation,
Polarity, and Output Eneble Control

VCC
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0

II
....

M SUFFIX ... FK PACKAGE
C SUFFIX .•. FN PACKAGE

•

TTL-Level Preload for Improved Testability

•

Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability

•

Fast Programming, High Programming Yield,
and Unsurpassed Reliability Ensured Using
Ti-W Fuses

en

(TOP VIEWI

CD
CD

.c

en

4321282726
5

25

6

24

23

•

AC end DC Testing Done at the Factory
Utilizing Special Designed-In Test Features

8
9

22

•

Dependable Texas Instruments Quality and
Reliability

10

20

21

11

19

....COCO

1/0/0
1/0/0
1/010
NC
110/0
1/0/0
1/0/0

C

1213 14 15 16 17 18

•

•

Package Options Include Plastic and
Ceramic Dual-In-Line Packages and Chip
Carriers

--ou-oo
zz

Cl

-gg

NC - No internal connection
Pin assignments in Qperating mode

Functionally Equivalent to AMD
AMPAL22V10 and AMPAL22V10A

description
The TIBPAL22V10 and TIPPAL22V10A are programmable array logic devices featuring high speed and
functional equivalency when compared to presently available devices. They are implemented with the
familiar sum-of-products (AND-OR) logic structure featuring the new concept "Programmable Output Logic
Macrocell". These IMPACr" circuits combine the latest Advanced Low-Power Schottky technology with
proven titanium-tungsten fuses to provide reliable high-performance substitutes for conventional TTL logic.
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining
and programming the architecture of each output on an individual basis. Outputs may be registered or
nonregistered and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential
outputs are enabled through the use of individual product terms.

IMPACT is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA do.umen,. .ontain informelion
CURIRt as of publication data. Products conform to
spacifications per th. terms of TUls Instruments
standard warranty. Production pro ....lng dolS nOI'
necessarily include tasting of all parameters.

Copyright @ 1986, Texas Instruments Incorporated

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-145

TIBPAL22V10M TlBPAL22V1 DAM
TIBPAL22V1 ~C, TIBPAL22V10AC
HIGH·PERFORMANCE IMPACTTII PROGRAMMABLE ARRAY LOGIC
Further advantages can be seen in the introduction of variable product term distribution. This technique
allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output.
This variable allocation of terms allows far more complex functions to be implemented than in previously
available devices.
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term.
These functions are common to all registers. When the synchronous set product term is a logic 1, the
output registers are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous
reset product term is a logic 1, the output registers are loaded with a logic O. The output logic level after
set or reset depends on the polarity selected during programming. Output registers can be preloaded to
any desired state during testing. Preloading permits full logical verification during product testing.

•

With features such as programmable output logic macrocells and variable product term distribution, the
TIBPAL22V10 and TIBPAL22V10A offer quick design and development of custom LSI functions with
complexities of 500 to 800 equivalent gates. Since each of the ten output pins may be individually configured
as inputs on either a temporary or permanent basis, functions requiring up to 21 inputs and a single output
or down to 1 2 inputs and 10 outputs are possible.
A power-up clear function is supplied that forces all registered outputs to a predetermined state after power
is applied to the device. Registered outputs selected as active-low power-up with their outputs high.
Registered outputs selected as active-high power-up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns.
Once blown, the verification circuitry is disabled and all other fuses will appear to be open.
The M suffix devices are characterized for operation over the full military temperature range of. - 55°C
to 125°C. The C suffix devices are characterized for operation from OOC to 75°C.

2-146

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

TlBPAL22V10M TIBPAL22V1 DAM
TlBPAL22V1 ~C. TIBPAL22V10AC
HIGH·PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
logic diagram (positive logic)
(11

INPUT LINES

0

4

8

12

16

20

24

28

32

36

40
ASYNCHRONOUS RESET
(TO ALL REGISTERS)

AR
O.

i

r1r

+CELL

7

-t>t::=
O.

··
0

(21

9

~J

:H=

CELL

:s:

0

·

(3)

Wl=l

0

i=l
3>13

P

··
(51

·

p-

15
(61

a

a

·

11

~

¥

::I

:S=l..

:l=!"l
-d-'

a

9

o.

··
a
7

(10)

SP

CO
CO

+I
(19)

C

CELL

(18)

CELL

(17)

CELL

(16)

L.......-

o.

·

.s:::

C/)

'---

:s:

(81

(91

CI)
+I
G)
G)

c.,-.--,-.

O.

13

1201

fI

'---

o.
a

O.

CelL

CELL

15

(71

(21)

'-----

0'
0

·

CELL

'---

o.

(41

=J
=J
=_1
=J
=J
=J
=J

1221

'---

o.

11

(23)

W>

=!l=T
-<>-

CELL

M>GJ

:§:f

il1)

(15)

(14)

CELL

SYNCHRONOUS SET
(TQ ALL REGISTERS)

03)

TEXAS -IJ}

INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265

2·147

TlBPAL22V1 DM TIBPAL22V1 DAM
TIBPAL22V1 DC, TIBPAL22V10AC
HIGH·PERFORMANCE IMPACT™PROGRAMMABLE ARRAY LOGIC
functional block diagram (positive logic)

r-£>

r

C1
J1S

SET
RESET

&

44x132
8

~

;,,1

OUTPUT
~ > lOGIC
~ MACROCEll

h

[>
~

.- EN

~ I/O/Q

~

I- EN

~

~

I- EN

,........,.

~

EN

h

~

EN

h

~

EN

h

~

EN

~

h

~

EN

~

~

I- EN

~

~

I- EN

f--; f--- I/O/Q

10

--,:;ClK/1

II...

h

~ rv

~>--

h

h

~

->
~

12
~

->
~

14

1-1-->

V-

16

1-1-->

c
Q)

V-

~

16

~ rv

~

Q)

1~

fA

:r-

...en

V-

14
'---

CD
CD

I-t--I>
~

---..
---..

~I--I>
~

12

~~

10

~-

---..

~

8

'-_

,........,.

r

I>
I>
I>-

~

~

~

-4\

10
10
'"'-' denotes fused inputs

2-148

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

r-r-r--

10

I/O/Q

I/O/Q

-------

r--

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

TIBPAl22V10M TlBPAL22V1 DAM
TIBPAl22V1 ~C, TlBPAL22V10AC
HIGH·PERFORMANCE IMPACT"" PROGRAMMABLE ARRAY LOGIC
output logic macrocell diagram

r-------- -,
OUTPUT LOGIC MACROCELL

I ~--------~--~3

I

AR

R

MUX

2

1-0

>--+_---t1D
r--!..---~C1

88

I
I

b---4~---I0

1} G-0

18
L..-_
_' "

O

3

II
...

FROM CLOCK BUFFER

MUX

en

81

I

AR _ asynchronous reset

~-~hr=s~

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TEXAS 15265

I
I
I
I
J

CD
CD

.c:

en

...caca

C

2·149

TIBPAl22V10M TlBPAL22V1 DAM
TlBPAl22V1 ~C. TIBPAL22V10AC
HIGH·PERFORMANCE IMPACT7M.PROGRAMMABLE

A~RAY

LOGIC

51 - 0

51 - 0

SO - 0

So - 1

REGISTER FEEDBACK, REGISTERED. ACTIVE-LOW OUTPUT

REGISTER FEEDBACK. REGISTERED. ACTIVE-HIGH OUTPUT

E
51 -.1
SO - 1

51 - 1
SO - 0

1/0 FEEDBACK. COMBINATIONAL. ACTIVE-LOW OUTPUT

I/O FEEDBACK. COMBINATIONAL. ACTIVE-HIGH OUTPUT

MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE
FUSE SELECT

51
0
0
1
1

SO

0
1
0
1

FEEDBACK AND OUTPUT CONFIGURATION
Regis.ter feedback Registered

Active low

Register feedback Registered

Ac1ive high

110 feedback
110 feedback

Combinational Active low
Combinational Active high

o = unblown fuse,

1 = blown fuse
51 and SO are select-func1ion fuses as shown in the output logic
macrocell diagram.

FIGURE 1. RESULTANT MACROCELL FEEDBACK AND OUTPUT LOGIC AFTER PROGRAMMING

absolute maximum ratings over operatinlJ free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ..................... , . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) _ . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: M suffix. . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°e
e suffix .............................. ooe to 75°e
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a pre-load cycle.

2-150

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75266

TIBPAL22V10M, TIBPAL22V1 DC
HIGH-PERFORMANCE IMPACT"" PROGRAMMABLE ARRAY LOGIC
recommended operating conditions
TIBPAL22Vl0M
VCC

Supply voltage

VIH

High-level input voltage

Vil

Low-level inpl;It voltage

TIBPAL22Vl0C

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

5.5

2

2

UNIT
V

5.5

V

0.8

0.8

V

IOH

High-level output current

-2

-3.2

IOl

Low-level output current

12

16

mA

fclock

Clock frequency t

16.5

18

MHz

tw

Pulse duration

Clock high or low

30

25

Asynchronous Reset high or low

40

35

Input

35

30

Feedback

35

30

Synchronous Set

35

30

Asynchronous Reset low (inactive)

40

35

tsu

Setup time before clockt

th

Hold time, input, set, or feedback after clockt

TA

Operating free-air temperature

0

mA

ns

ns

0

-55

125

II
...

ns

0

75

°c

U)

electrical characteristics over recommended operating free-air temperature range
PARAMETER
VCC - MIN.

11-

VCC - MIN.

10H - MAX

Val

VCC - MIN,

10ZH

VCC = MAX,

IOl - MAX
Va = 2.7 V

Vce = MAX,

Va = 0.4 V

I
I

Any output
Any 1/0

MIN

TIBPAL22V10C
TYP§
MAX

MIN

-1.2

18 mA

VIK
VOH

10Zl

TlBPAL22Vl0M
TYP§
MAX

TEST CONDITIONS*

Q)
Q)

2.4

3.5
0.25

-1.2
2.4

0.5

V
0.5

V

0.1

0.35

0.1

mA

-100

-100

-250

-250

VCC - MAX,

VI - 5.5 V
VI - 2.7 V

1

1

mA

VCC - MAX,

25

25

III

VCC - MAX,

VI - 0.4 V

-0.25

-0.25

MA
mA

lOS'

VCC = MAX,

Va = 0.5 V

-90

mA

ICC

VCC - MAX,

VI - GND,

180

mA

-90
120

-30

180

120

Q

MA

II

-30

...

V

3.5

IIH

Outputs open

.r::.
en
ca
ca

UNIT

switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER

FROM

fmax t

With feedback

TEST CONDITIONS

TO

Cl = 50 pF

TIBPAl22V10M
TYP§
MAX

MIN

16.5

TIBPAL22V10C
TYP§ MAX

UNIT

18

MHz

MIN

tpd

1,1/0

1/0

Rl = 300 0 for C suffix,

15

40

15

35

ns

tpd

1,1/0 (reset)

Rl = 390 0 for M suffix,

15

45

15

40

ns

tpd

Clock

a
a

R2 = 390 0 for C suffix,

10

25

10

25

ns

ten

1,1/0

1/0,

R2 = 750 0 for M suffix,

15

40

15

35

ns

tdis

1,1/0

1/0,

See Figure 2

15

40

15

35

ns

t f max and fclock (with feedback)
fclock (without feedback) =

a
a

tsu
.

+ tp~

(ClK to a)' fmax and fclock without feedback can be calculated as f max and

1

tw high + tw low
:t: For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ All typical values are at Vce = 5 V, T A = 25°C.
, Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set
0.5 V to avoid test problems caused by test equipment ground degradation.

TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

Vo

at

2-151

TIBPAL22V1 DAM, TlBPAL22V10AC
HIGH·PERFORMANCE IMPACT"' PROGRAMMABLE ARRAY LOGIC
recommended operating conditions
TIBPAL22Vl0AM

Ea
c

Vee

Supply voltage

VIH

High-level input voltage

VIL

Low~level

10H

Hj'gh-Ievel output current

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V

5.5

2

5.5

V

input voltage

0.8

0.8

-2

-3.2

V
rnA

10L

Low-level output current

12

16

rnA

fclock

elock frequency t

22

28.5

MHz

tw

Pulse duration

tsu

Setup time before clock1

elock high or low

20

15

Asynchronous Reset high or low

30

25

Input

25

20

Feedback
Synchronous Set

25

20

25

20

Asynchronous Reset low (inactive)

30

25

th

Hold time, input, set, or feedback after clockt

TA

Operating free-air temperature

0

ns

ns

ns

0

-55

125

0

75

·e

electrical characteristics over recommended operating free-air temperature range

en

...en

UNIT

NOM

2

Q)

::T
CD
CD

TIBPAL22Vl0AC

MIN

PARAMETER
VIK

Vee - MIN,

II -

VOH

Vee - MIN,

10H - MAX

VOL

Vee - MIN,

10L - MAX

Vee - MAX,

Vo - 2.7 V

10ZH
10ZL

TIBPAL22Vl0AM
TYP§
MAX

TEST CONDITIONS*

I Any output
I Any 1/0

Vee

~

MAX,

Vo

MIN

-1.2

-18 mA

~

TIBPAL22Vl0AC
TYP§
MAX

MIN

2.4

2.4

3.5
0.25

0.4 V

0.5

UNIT

-1.2

V

0.5

V
rnA

3.5
0.35

V

0.1

0.1

-100

-100

-250

-250

1

1

~A

Vee - MAX,

VI - 5.5 V
VI - 2.7 V

25

25

~A

Vee - MAX,

VI - 0.4 V

-0.25

-0.25

rnA

10S§

Vee ~ MAX,

Vo

-90

rnA

lee

Vee - MAX,

VI - GND,

180

rnA

II

Vee - MAX,

IIH
IlL

~

0.5 V

-90

-30
120

Outputs open

-30

180

120

rnA

switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER

FROM

f max t

With feedback

TEST CONDITIONS

TO

TIBPAL22Vl0AM
TYP§
MAX

MIN

TIBPAL22Vl0AC
TYP§
MAX

MIN

UNIT

eL

~

50 pF

tpd

1,1/0

I/O

R1

~

300 [l for e suffix,

15

30

15

25

ns

tpd

Q

R1

~

390 [l for M suffix,

15

35

15

30

ns

tpd

I, 1/0 Iresetl
elock

Q

R2

~390 [l

for e suffix,

10

20

10

15

ns

ten

1,1/0

Q

R2

~

750 [l for M suffix,

15

30

15

25

ns

tdis

1,1/0

Q

See Figure 2

15

30

15

25

ns

t f max and fclock (with feedback)
fclock Iwithout feedback I

~

= tsu + tp~

22

28.5

MHz

(elK to aI' f max and fclock without feedback can be calculated as f max and

.
1
tw high + tw low

:t: For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ All typical values are at Vec ~ 5 V, TA ~ 25 ·e.
~ Not more than one output should be shorted at a time and the duration of the short circuit should not exceed. one second. Set
0.5 V to avoid test problems caused by test equipment ground degradation.

2-152

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265

Vo

at

TIBPAL22V10M TIBPAL22V1 DAM
TIBPAL22V1 DC, 'TIBPAL22V1 OAC
HIGH·PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
preload procedure for registered outputs (see Note 2)
The output registers can be preloaded to any desired state during device testing. This permits any state
to be tested without having to step through the entire state-machine sequence. Each register is preloaded
individually by following the steps given below.
Step
Step
Step
Step

1.
2.
3.
4.

With Vee at 5 volts and pin 1 at VIL. raise pin 13 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse pin 1. clocking in preload data.
Remove output voltage. then lower pin 13 to VIL. Preload can be verified by observing the voltage
level at the output pin.

preload waveforms (see Notes 2 and 3)
PIN 13

~-

/

~
PIN 1

1

1

!

:

1
1

REGISTERED 1/0

I4- t d-+j

j4- t su-+j

i+-td--+i

==>------\

*-tw-+l
I

:

1
1

~ -VIH

INPUT

I

-VIL
NOTES:

- VIHH
VIL

...

1___ 1_____ vlH

I 1- --:

1

-

I'
I

1

1

-

U)

CD
CD

VIL

.c

tn
ca
ca
C

1
I

...

Vr----VOH

\

OUTPUT
VOL

2. Pin numbers shown are for JT and NT packages only. If chip carrier socket adapter is not used, pin numbers must be changed
accordingly.
3. td ~ tsu ~ tw ~ 100 ns to 1000 ns. VIHH ~ 10.25 V to 10.75 V.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, 'TEXAS 75265

2-153

TIBPAL22V10M TIBPAL22V1 DAM
TIBPALZ2"1 bc, TlBPAL22V10AC
HIGH·PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
power·up reset
Following power-up, all registers are reset to zero. The output level depends on the polarity selected during
programming. This feature provides extra flexibility to the system designer and is especially valuable in
simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the VCC's
rise be monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable
input and feedback setup times are met.

power-up reset waveforms

I1r

~-----------------------------------5V

4
VCC __________

J

tpd t
1600 ns typo 1000 ns MAX)

1.
4.'_ _ _ _

r--------~ I

ACTIVE-HIGH
REGISTERED OUTPUT

c

....
C»
C»

",

/

/

ACTIVE-LOW
REGISTERED OUTPUT

STATE UNKNOWN

Vo

.

f 5 -; -

-

-

-

--

I
JlI
STATE UN~NOWN

VO~
VOH

)11.5 V
: -

o

::r

-

-

*

-

-

-

-

VOL

)+- t su --+I

CD
CD

....

\'.5V

CLOCK

en

FVIH

. . . ----.l1-

-------------'--~-r:

--VIL

14---- tw-----+t
tThis is the power~up reset time and applies to registered outputs only. The values shown are from characterization data.
t. This is the setup time for input or feedback.

programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5762.

2-154

TEXAS

~

INSTRUMENTS
POST OFFle!=, BOX 655012 • DALLAS, TEXAS 75265

TIBPAL22V10M TlBPAL22V1 DAM
TIBPAL22V1 ~C, TIBPAL22V10AC
HIGH·PERFORMANCE IMPACT"' PROGRAMMABLE ARRAY LOGIC
PARAMETER MEASUREMENT INFORMATION
5V
S1

L
R1

FROM OUTPUT
UNDER TEST -

.....-

TEST
POINT

...........R2

CL
(See Note A)

II
...

LOAD CIRCUIT FOR
THREE-STATE OUTPUTS

TIMING
INPUT

L.

HIGH-LEVEL
PULSE

F,1.5V

- - _.......U - -

-

1 5 V
15 V
~
.
.
L
.!
0.3 V
---3.5V

3.5V

- - - 0.3 V

,

DATA
~-:;;:;;3.5 V
INPUT ~ 1.5V
.~
0.3V

LOW-LEVEL
PULSE

.

3.5

IN·PHASE
OUTPUT
tpd

.1
I

:

!1.5V

1
14

.1

14

0.3V

~I

tpd

OUTPUT
CONTROL
lIow-levei
enabling)

:+--VOH

,I~
I
VOL
14
.1 tpd

OUT·Of·PHASE
OUTPUT
(See Note D)
VOLTAGE WAVEfORMS
PROPAGATION DELAY TIMES

3 .5V

...

CO
CO

C

VOLTAGE WAVEfORMS
PULSE DURATIONS

I·
14

1

- - --0.3V

\1-:;; -; --- V

1

I

1 5 V
15 V
~
.
.

VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES

tpd

CD
CD

.c
en

~-tw---..

I+-th-"
)4-tsu-+j
I

INPUT J , 1 . 5 V

II)

lr.:"":'1

VOH

,,1.5 V
--VOL

WAVEFORM
S1 CLOSED
(See Note 8)

~3.5V
1.5V
,
ten -+I

I+-

1.5V
)
-,- - -

-.r

- -·0.3 V

I+-- tdis

I'

I
~3.3V
1~VOL+0.5V
I
A
VOL
ten-.l
--+I ~~s_Ti_ V

!

i

-= = -=

WAVEFORM2~--"S1 OPEN
(See Note B)

1.5 V

OH
L-VOH·-O.5 V
~0 V

VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.
B. Waveform· 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with Internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR :5 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is open.

FIGURE 2

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265

2-155

2-156

TEXAS ,.,
INSlRUMENlS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75285

TIBPAL22VP10-25M
TIBPAL22VP10-20C
HIGH-PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
02943, FEBRUARY 1987-REVISED DECEMBER 1987

•

M SUFFIX ... JT PACKAGE
C SUFFIX ... NT PACKAGE

Functionally Equivalent to the
TIBPAL22V10/10A. with Additional
Feedback Paths in the Output Logic
Macrocell

(TOP VIEWI

ClK/1

•

Choice of Operating Speeds:
TIBPAL22VP10-20C . , . 20 ns Max
TIBPAL22VP10-25M , .. 25 ns Max

•

Variable Product Term Distribution Allows
More Complex Functions to be Implemented

•

Polarity of Each Output is Programmable

•

TTL-bvel Preload for Improved Testability

•

Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability

•

•
•
•

VCC

1/0/0
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0

I

GND

Fast Programming. High Programming Yield.
and Unsurpassed Reliability Ensured Using
Ti-W Fuses

II
...

"""';'''--'':'J-O

M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE

fI)

(TOP VIEWI

-

AC and DC Testing Done at the Factory
Utilizing Special Designed-In Test Features

G)
G)

ua a

.c

~ U UQ (3
__ uz>;:,;:,
4

Dependable Texas Instruments Quality and
Reliability
Package Options Include Plastic and
Ceramic Dual-In-Line Packages and Chip
Carriers

3

CJ)

...asas

2 1 28 27 26

5

25

6

24

1/0/0
1/0/0

Q

23

NC

description

8

22

9

21

10

20
19

11

The TIBPAL22VP10 is equivalent to the
TIBPAL22V10A but offers additional flexibility
in the output structure. The improved output
macrocell uses the registered outputs as inputs
when in a high-impedance condition. This
provides two additional output configurations for
a total of six possible macrocell configurations
all of which are shown in Figure 1.

12 13 14 15 16 17 18

--cu-aa
22

(!)

-gg

NC-No internal connection
Pin assignments in operating mode

The device contains up to twenty-two inputs and ten outputs, It defines and programs the architecture
of each output on an individual basis. Outputs may be registered or nonregistered and inverting or
noninverting, In addition, the data may be fed back into the array from either the register or the I/O port,
The ten potential outputs are enabled through the use of individual product terms.
Further advantages can be seen in the introduction of variable product term distribution, This technique
allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output.
This variable allocation of terms allows far more complex functions to be implemented than in previously
available devices.

IMPACT is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA d••umo.ts •• ntain information
curr••t 81 of pllblication date. Products canfarm to
spooifioatio.s par tho Iorms of T.... Instrumonts

~==,r:-i~:,~li =:~ti~n :I~O:=~I:"~ nat

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

Copyright @ 1987, Texas Instruments Incorporated

2-157

TIBPAL22VP10-25M
TIBPAL22VP10-20C
HIGH-PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term.
These functions are common to all registers. When the synchronous set product term is a logic 1, the
output registers are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous
reset product term is a logic 1, the output registers are loaded with a logic O. The output logic level after
set or reset depends on the polarity selected during programming. Output registers can be preloaded to
any desired state during testing. Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product terms, the TIBPAL22VP1 0
offers quick design and development of custom LSI functions with complexities of 500 to 800 equivalent
gates. Since each of the ten output pins may be individually configured as inputs on either a temporary
or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and 10
outputs are possible.

E

A power-up clear function is supplied that forces all registered outputs to a predetermined state after power
is applied to the device. Registered outputs selected as active-low power-up with their outputs high.
Registered outputs selected as active-high power-up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns.
Once blown, the verification circuitry is disabled and all other fuses will appear to be open.
The TIBPAL22VP1 0-25M i.s characterized for operation over the full military temperature range of - 55°C
to 125°C. The TIBPAL22VP10-20C is characterized for operation from O°C to 75°C.

2-158

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

T1BPAL22VP10·25M
TIBPAL22VP10·20C
HIGH·PERFORMANCE IMPACT'M PROGRAMMABLE ARRAY LOGIC
functional block diagram (positive logic)

r--1>

r C1

SET
RESET

8<

32.44
B

11S

~

",1

C>

OUTPUT

>--- P- lOGIC

---.

r-

MACROCEll

h

r-

~ 1/0/0

EN

10

---.

~

ClK/1

.....

~ '"

~

---.
h
h

~

~
1~

-

'"

h
I-"""-

h
h

.........

~

-

>

~

-

>

~

>

---.

>- EN

>-r---- >

---.

>- EN

V-

---.

>- EN

>-c-- P-

V-

---.

>- EN

r-H r-H r--

-t;: P-

---.

>- EN

H f++- 1/0/.0

rr-

r

V-

>-r---- P-

h

~

>

~

B

......... 1/0/0

-

16

10

~

~

16

12

......... 1/010

P-

14

14

~

~

~

12

h
h
h
h

EN

""""
EN

""""
EN

""""

~

EN

""""

H
~

---r--

I/O/ofl
110/0
1/0/0

...en
Q)
Q)

.c
tn

1/010

...

110/0

C

CO
CO

1/0/0

10
10
'V

10

denotes fused inputs

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-159

TIBPAL22VP10·25M
TlBPAL22VP10·20C
HIGH·PERFORMANCE IMPACfTMPROGRAMMABLE ARRAY LOGIC
logic diagram (positive logic)

I.

111
0
AR

•

8

12

INPUT LINES

20

2.

28

32

3.

40
ASYNCHRONOUS RESET

(TO All REGISTERS)

0.

i

:Rc
:Rc

C}1

0'

··
0

121

~rr

ru:>

CELL

:g3

9

~J

0

13)

·
"

=h-

~

I»
I»

gp
14)

::T

13

0

...en

~J
CELL

(20)

~

0.

(I)
(I)

(21)

L--

0

...
en

CELL

~

0.

C

(22)

L--

0.

E

(23)

CELL

:B=i

7

-i>t:=

··

r,.

15

~IT
CELL

(19)

)5)
~

0.
0

·
16)

P-

15
0'

17)

13

w
l=l

0

18)

"

-<>

9

·
7

s.>
:B=l

:8=l
:R:

:B=i

SP
(111

2-160

~~

PEl)

FbtcP
CELL

(15)

--L-

0'
0

(10)

(17)

L--

0

·

CELL

CELL

:§::f

0'

19)

~h
'----

0. _

·

(18)

L--

,

0

··

~lI
CELL

(14)

CELL

SYNCHRONOUS SET
\TO ALL REGISTERS)
(13)

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TlBPAL22VP10·25M
TIBPAL22VP10·20C
HIGH·PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
output logic macrocell diagram

-,

OUTPUT LOGIC MACROCELL

r--:-:M~U~X-"

~--------~--~3
AR

R

1-0

I
I

2

)---1-....--110
.---':""'---1> C1
88

b-~~----i0

1} G-0

18

O

3

FROM CLOCK BUFFER
MUX

o

....Q)
II)

1 / 2 / 3 t - - - - / - - - -......._--+----'

1}G.!!..
o

3

51

II

AR --aSynChrOnous reset

55 - _
synchronous
L-.
_ set-...-

Q)

I
I
I

.c

en

....asas

C

I

J

t This fuse is unique to the Texas Instruments TIBPAL22VP1 O. It allows feedback from the 110 port using registered outputs as shown
in the macrocell fusing logic function table.

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75266

2·161

TIBPAL22VP10·25M
TlBPAL22VP10·20C
,
HIGH·PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC

S2 - 0
S1 - 0
so - 0
REGISTER FEEDBACK. REGISTERED. ACTIVE-LOW OUTPUT

S2 - 0
S1 - 0
SO - 1
REGISTER FEEDBACK. REGISTERED. ACTIVE-HIGH OUTPUT

c

....
D)
D)

fA

:::r

S2 - 1
S1 - 0

S2 - 1
S1 - 0
SO - 0

CD

!en

1/0 FEEDBACK. REGISTERED. ACTIVE-LOW OUTPUTt

SO -

1/0 FEEDBACK. REGISTERED. ACTIVE-HIGH OUTPUTt

S2 - X
S1 - 1
SO - 1

S2 - X
S1 - 1
SO - 0

1/0 FEEDBACK. COMBINATIONAL. ACTIVE-LOW OUTPUT

1

1/0 FEEDBACK. COMBINATIONAL. ACTIVE-HIGH OUTPUT

tThese configurations are unique to the TIBPAL22VP10 and provide added flexibility when comparing it to the TIBPAL22Vl0 or
TIBPAL22Vl0A.

FIGU~E 1. ~ESULTANT MACRO CELL FEEDBACK AND OUTPUT LOGIC AFTER PROGRAMMING

2·162

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TIBPAL22VP10·25M
TIBPAL22VP10·20C
HIGH·PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE
PROGRAM-FUSE SELECT
52

51

0

0

0

0

1
1

SO

FEEDBACK AND OUTPUT CONFIGURATION

0
1

Register feedback Registered

Active low

Register feedback Registered

Active high

0

0

1/0 feedback

1
0

1/0 feedback

X

0
1

I/O feedback

Active low
Registered
Active high
Combinational Active low

X

1

1

I/O feedback

Combinational Active high

Registered

o = unblown fuse,

1 = blown fuse, X = unblown or blown fuse
S2, S 1, and SO are select-function fuses as shown in the output logic macrocell
diagram.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: TlBPAL22VP10-25M ................. - 55 °e to 125 °e
TIBPAL22VP10-20e ..................... ooe to 75°e
Storage temperature range ......................................... -65°e to 150 0 e
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a pre-load cycle.

VIH

High·level input voltage

Vil

Low-level input voltage

10H

High-level output current

4.5

Low~level

Clock frequency t

tw

Pulse duration

tsu

th
TA

2

Setup time before clockt

=

tsu

+ tpd

NOM

MAX

4.75

5

5.25

V

5.5

2

5.5

V

0.8
-3.2

en

..

V
mA

12

16

mA

25

37

MHz

20

10

Reset high

30

20

Input

25

15

Feedback

25

15

Preset

25

15

30
0
-55

20

Operating free-air temperature

.c

UNIT

MIN

5.5

Clock high or low

Reset low (inactive)
Hold time, input, preset, or feedback after clockf

t fclock (with feedback)

5

TIBPAL22VP10-20C

0.8
-2

output current

10l
fclock

CD
CD

C
TIBPAL22VP10-25M
MIN NOM MAX

Supply voltage

en

CO
CO

recommended operating conditions

VCC

I..

125

0
0

ns

ns

75

ns
·C

1
, fclock without feedback can be calculated as
(ClK to Q)

fclock (without feedbackl = :-=.,.--1.,.....,_;-tw high + tw low

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

2-163

TIBPAL22VP10·25M
TIBPAL22VP10·20C
HIGH·PERFORMANCE IMPACpM PROGRAMMABLE ARRAY LOGIC
electrical characteristics over recommended operating free·air temperature range
PARAMETER
VIK

Vee - MIN,

11--lamA

VOH

Vee - MIN,

10H - MAX

Val

Vee

10ZH

Vee

= MIN,
= MAX,

Va

= MAX
= 2.7 V

Vee

=

Va

= 0.4 V

II

Vee

IIH

Vee

III

Vee

= MAX,
= MAX,
= MAX,
= MAX,
= MAX,

10Zl

...C
I»
I»

TIBPAL22VP10-25M

TEST CONDITIONSt

I Any output
I Any 1/0

10S§

Vee

ICC

Vee

MAX,

10l

= 5.5 V
VI = 2.7 V
VI = 0.4 V
Va = 0.5 V
VI = GND,

MIN

TYP*

MAX

TIBPAL22VP10-20C
MIN

TYP*

-1.2
2.4

3.5

2.4

0.25

0.5

3.5
0.35

0.1

UNIT
V
V

0.5

-100

0.1
-100

-250

-250

1

1

VI

V
mA
~A

mA

25

25

~A

-0.25

-0.25

mA

-90

mA

210

mA

-30
Outputs open

MAX
-1.2

-90
140

-30

220

140

switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise notedl ~
PARAMETER

en

f max '
tod

:r-

...

CD
CD

(I)

FROM

TEST CONDITIONS

TO
el

= 50 pF,
= 300 !l for
= 390 !l for
= 390 !l for
= 750 !l for

1,1/0

1/0

R1

t~

I, 1/0 Ireset)

Q

Rl

tpd

Clock

Q

R2

ten

1.1/0
1,1/0

Q

R2

Q

See Figure 2

tdis

TIBPAl22VP10-25M
MIN

TYP*

25

50

MAX

TIBPAl22VP10-20C
MIN

TYP*

37

50

MAX

UNIT
MHz

e suffix,

12

25

12

20

ns

M suffix,

12

25

12

20

ns

e suffix,

a

15

a

12

ns

M suffix,

12

25

12

20

ns

12

25

12

20

ns

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*AII typical values are at Vee = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set Va at
0.5 V to avoid test problems caused by test equipment ground degradation.

, f max Iwith feedback) = .
1
, f max without feedback can be calculated as
tsu + tpd lelK to Q)
f max Iwithout feedback)

2-164

= tw

1
high

+

tw low'

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TlBPAL22VP10-25M
TIBPAL22VP10-20C
HIGH-PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
preload procedure for registered outputs (see Note 2)
The output registers of the TIBPAL22VPl 0 can be preloaded to any desired state during device testing.
This permits any state to be tested without having to step through the entire state-machine sequence.
Each register is preloaded individually by following the steps given below.
Step
Step
Step
Step

1.
2.
3.
4.

With Vee at 5 volts and pin 1 at VIL, raise pin 13 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse pin 1, clocking in preload data.
Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage
level at the output pin.

preload waveforms (see Notes 2 and 3)

PIN 13

~

I4- t su-+f

I

*"-tw--+l

i !
I

I

-

I

~

II...

- - :::H

I

I

I

I

I

~-VIH

REGISTERED 1/0 ~

INPUT

I

-VIL
NOTES:

-

i i __!___ :nu_::

*-td--+l

PIN 1

~

I4- t d--+/

o

CD
CD

.c

en
ca
ca

...

Vr----VOH

\

o

OUTPUT
VOL

2. Pin numbers shown are for JT and NT packages only. If chip carrier socket adapter is not used, pin numbers must be changed

accordingly.
3. td = tsu = tw

=

100 ns to 1000 ns. VIHH

=

10.25 V to 10.75 V.

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-165

TIBPAL22VP10·25M
TIBPAL22VP10·20C
HIGH·PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
power·up reset
Following power-up, all registers of the TIBPAL22VP10 are reset to zero. The output level depends on
the polarity selected during programming. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it
is important that the VCC's rise be monotonic. Following power-up reset, a low-to-high clock transition
must not occur until all applicable input end feedback setup times are met.

power·up reset waveforms

~--------------------------------5V

.J;tf

4
VCC __....................

~----tpdt

141
..

(800 ns typ, 1000 ns MAXI

REGISTE:~~I~~~~~~

/

.

STATE UNKNOWN

~

I

~~5 -; -

-

-

- - - VOH

--.....--..........~...............--.....------..........-~~------.....--~.-VOL

I

CLOCK

tThls is the

power~up

reset time and appiies to registered outputs only. The values shown are from characterization data.

*This is the setup time for input or feedback.
programming information

Texas Instruments Programmable Logic Devices can be programmed using widely availeble software and
inexpensive device programmers.
When the additional fuses are not being used, the TIBPAL22VP10 can be programmed using the
TIBPAL22V10/10A programming algorithm. The fuse configuration data can either be from a JEDEC file
(format per JEDEC Standard No.3-A) or a TIBPAL22V10/10A master.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information' on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized Tldistributor, or by calling Texas Instruments at (214) 995-5762.

2-166

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 76266

TlBPAL22VP10·25M
TIBPAL22VP10·20C
HIGH·PERfORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
PARAMETER MEASUREMENT INFORMATION
5V
Sl

t.

Rl
FROM OUTPUT _ ..._ ..._ ...._
UNDER TEST
CL
(See Note A)

TEST
POINT

R2

II
...

LOAD CIRCUIT FOR
THREE-STATE OUTPUTS

TIMING
INPUT

--/.

T,1.5

V

- - _.....U - - -

- - -

0.3

V

1 5 V
15 V
~
.
.

---3.5V

3.5 V
HIGH-LEVEL
PULSE

I..--tw--J

I+-th-+t
I4- t su-+(
I

DATA
~~-;;::3.5V
INPUT..../' 1.5V
..~
0.3 V

I

LOW-LEVEL
PULSE

\.1~;- -

.LI1.5 V

--"

I·

tpd -Io414f---.~1

14

- - 3.5 V

tpd

II /1~-. . . I.:----.'t:;5~
L

IN·PHASE
OUTPUT
tpd
OUT-Of-PHASE
OUTPUT
(See Note D)

I

14.'

,I

14

1.5V
.

VOLTAGE WAVEfORMS
PROPAGATION DELAY TIMES

1

~I

I

til

3.5V

...
IV

- - --0.3V

OUTPUT
CONTROL
now-level
enabling)

IV

C

~3.5V
1.5 V

I

VOH
VOL

tpd

~VOH
1.5V
.
- - VOL

1.5 V
I

I
ten ~

1.5 V

--;'I--J

I

.c

VOLTAGE WAVEfORMS
PULSE DURATIONS

0.3 V

.1

Q)
Q)

0.3 V

1 5 V
15 V
~
.
.

VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES

INPUT

U)

I+-

!

-1- - - - _. 0.3
-+I 14-- tdis

II

.

V

~3.3V

WAVEFORM l - - - - - r \ l 1 . 5 V
II~vOL+0.5V
Sl CLOSED
1 ~-==~= V
(S •• Note 8)
ten-+! j+:+-tdis Tit
OL
WAVEfORM 2
S10PEN
(See Note B)

Y,

1.5 V

--.I

•

~-

.= VOH
·L-VOH-0.5 V
~

aV

VOLTAGE WAVEfORMS
ENABLE AND DISABLE TIMES. THREE-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR '" 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
.
D. When measuring propagation delay times of 3·state outputs, switch S1 is closed.

FIGURE 2

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 7526,5

2-167

c

....

S»
S»

o::sCI)
CI)

....
(I)

2-168

TlBPALR19LBM, TIBPALR19R4M, TIBPALR19R6M, TIBPALR19RBM
TIBPALR19LBC, TIBPALR19R4C, TIBPALR19R6C, TIBPALR19RBC
HIGH-PERFORMANCE LATCHED-INPUT PAL® CIRCUITS
02709, DECEMBER 1982-REVISED DECEMBER 1987

•

High-Performance Operation , , . 30 MHz

•

Preload Capability on Output Registers

•

DIP Options Include Both 300-mil Plastic
and 600-mil Ceramic

•

Dependable Texas Instruments Quality and
Reliability

DEVICE

110 INPUTS

I INPUTS

o OUTPUTS

3-STATE

REGISTERED
QOUTPUTS

'PAlR19l8
'PAlR19R4
'PAlR19R6
'PAlR19R8

11
11
11
11

2
0
0
0

2
0
0
0

0
4 13-state buffers)
6 13-state buffers)
8 13-state'buffers)

description
These programmable array logic devices feature
high speed and functionality similar to the
TIBPAl16la, 16R4, 16R6, 16Ra series, but
with the added advantage of D-type input
registers. If any input register is not desired, it
can be converted to an input buffer by simply
programming the architectural fuse.

110 PORTS
6
4

2
0

TlBPAlR19lS'
M SUFFIX ... JW PACKAGE
C SUFFIX ' .. JW OR NT PACKAGE
(TOP VIEW)

Combining Advanced low-Power Schottky t
technology, with proven titanium-tungsten
fuses, these devices will provide reliable high
performance substitutes over conventional TTL
logic. Their easy programmability allows for
quick design of custom functions and typically
result in a more compact circuit board. In
addition, chip' carriers are available for further
reduction in board space.

fI)

0
110
110
110
110
110
110
0
INClK

Q)
Q)

.s::.
o

..
as
as

C

TIBPALR19lS'
M SUFFIX ••• FK PACKAGE
C SUFFIX .•. FN PACKAGE

Extra circuitry has been provided to allow loading
of each register asynchronously to either a high
or low state. This feature simplifies testing
because the registers can be set to an initial state
prior to executing the test sequence.

(TOP VIEW)

4321282726

25

An M suffix designates full-temperature circuits
that are characterized for operation over the full
military temperature range of - 55°C to 125°C.
A C suffix designates commercial-temperature
circuits that are characterized for operation from
OOC to 70°C.

..

Vcc
110

110
110
110
110
110
110
110
110
liD
liD
GND

24

1/0
1/0

23
22
21

liD
liD

20

10

19

11
12131415161718

INPUT REGISTER FUNCTION TABLE
INPUT
INClK
0

OUTPUT OF
INPUT REGISTER

1
1

H

H

l

l

X

l
Qo

NC - No internal connection
Pin assignments in operating mode

t Integrated Schottky-Barrier diode-clamped transistor is patented
by Texas Instruments, U.S. Patent Number 3,463,975.
PAL is a registered trademark of Monolilthic Memories Inc.

PRODUCTION DATA documants .onlain info.matlon
......t as of publication data. Products .onform 10
.ccificltions par the tarml of Taul Instrumants

:'::'~:=i~·t::I-::.ra =~::i:r :.r::::~~~~ not

Copyright © 1985, Texas Instruments Incorporated

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-169

TIBPALR19R4M. TIBPALR19R6M. TIBPALR19R8'M
TIBPALR19R4C. TIBPALR19R6C. TIBPALR19R8C
HIGH·PERFORMANCE REGISTER~D·INPUT PAL@ CIRCUITS
TIBPALR19R4'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE

TIBPALR19R4'
M SUFFIX, •• JW PACKAGE'
C SUFFIX .•. JW OR NT PACKAGE
(TOPVIEWl
OUTCLK

(TOP VIEW)

VCC
liD

liD

110
110
110
110

Q
Q

110
110

Q

110
110
INCLK

OE

GND

c

D)

en

:::T

OUTCLK
110
110.
110
110

CD
CD

r+

en

NC
Q
Q

110

C SUFFIX •.. FN PACKAGE
(TOP VIEW)

VCC
110
110
Q

4 3 2 1 282726

Q

110 5
110 6
110 7
NC
110
110 10

Q
Q

110
INCLK

lID

OE

11
12131415161718

TIBPALR19RS'
M SUFFIX ... JW PACKAGE
C SUFFIX ..• JW OR NT PACKAGE

TIBPALR19RS'
M SUFFIX ... FK PACKAGE
C SUFFIX .•. FN PACKAGE

(TOP VIEW)

(TOPVIEWI

OUTCLK

110
110

:s

VCC
110
Q

~
u
gg5~~~o

Q

4321282726

Q

25
24

Q
Q

110
110
110
110
GND """''--....;.:;;.....

Q

22
21
20
19

Q
Q

10

INCLK

OE

12131415161718

gg~~I~dd
t!l
:!!:

Pin assignments in operating mode

NC-No internal connection

2-170

Q

TIBPALR19R6'

Q

GND

Q

M SUFFIX .•• FK PACKAGE

Q

110
110
110

110

12131415161718

TlBPALR19R6'
M SUFFIX ... JW PACKAGE
C SUFFIX ... JW OR NT PACKAGE
(TOP "(lEW)

D)

r+

25
24
23
22
21
20
19

110 5
110 6
110 7
NC 8
110 ~9
110 ~10
110 ~11

Q

TEXAS . . ,
INSTRUMENTs
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TIBPALR19L8M, TIBPALR19R4M
TIBPALR19L8C, TIBPALR19R4C
HIGH·PERFORMANCE REGISTERED·INPUT PAl@CIRCUITS
functional block diagrams (positive logic)
'PALR19L8
EN >1

&

"iJD----O

t>----o
b-4~"'-1/0

b-4.........-1/0
b-4.........-I/O
b-4.........-I/O

PI

....-I/O
~.r....-I/O
~.r

6

'PALR19R4

OE-----------------------------q

OUTCLK------------------II>
&

Q
Q

INCLK-_cP
Q
Q

11

I/O
1/0
1/0
1/0

4
4

TEXAS •

INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75265

2-171

TIBPALR19R6M. TlBPALR19R8M
TIBPALR19R6C, TIBPALR19R8C
HIGH·PERFORMANCE REGISTERED·INPUT PAL @ CIRCUITS
functional block diagrams (positive logic)
'PALR19R6

Q
Q

Q
Q

Q

E...
I

Q

C

I»
I»

1/0
1/0

tn

:T
CD
CD

...
U)

'PALR19R8

OE
OUTCLK
Q

INCLK

Q

Q
Q

11

Q
Q

Q

':'

Q

8

2-172

TEXAS

-II

INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265

TIBPALR19LBM, TIBPALR19L8C
HIGH·PERFORMANCE REGISTERED·INPUT PAL@CIRCUITS
logic diagram (positive logic)
1(11

.

INPUT LINES
i

I/O 1&

~.
..,

4

8

12

16

20

,
24

28

32

J

(231

'C2
20

'C2
20

I/O

MO

M

M'

2432

2433
~

36

~

PRODUCT
LINES

···
·
..,
~ ····
····
···
·
···
·
···
·
···
·
···
·
0

1

(221

l

(211

0

7

I/O

@L

'C2
20

8

M'

v

2434

11
tr
ttJ

I/O,1&

'02
20
MO
M'

15

!!!L

'C2
20

MO
M'

~

,C2
20
MO
M'

31

32

ill.

fJ
fJ
'02
20

MD

(181

~ vl

(171

v

I/O,!!l

40

2438

'C2
20
MO

48

2439

JJ
,C2
20

MD

56

f

2440

~

.c

en

...caca

I/O

C

I/O

I/O

1

(161

1

(151

I/O

55

M'

I/O,~

I/O

47

M'

I/O,~

CD
CD

39

M'

~

(191

l

2437

I/O

(201

v

~

~ 2436

I/O ~

l

23

24

II
...
U)

16

~ 2435

I/O

I/O

q

63

..,

'02
20

v

o

M'

I/O,\!!l

t1
'02
20

MD

M'

_ 2442

.A(1

~.

Pin numbers shown are for JW and NT packages.

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2·173

TIBPALR19R4M, T1BPALR19R4C
HIGH·PERFORMANCE REGISTERED·INPUT PAL@ CIRCUITS

logic diagram (positive logic)
OUTCLK (1)

.

INPUT LINES
)

110

!&

fttF"

4

12

8

16

,
24

20

28

32

0<2
,e2
20

C

~

PRODUCT
LINES
0

···
·
···

J

(22)

1/0

tr ·

~

f1fJ ····

P- ~~20)

Q

~

Q

,e2
20

ffi.

MO

M,

~ 2434

8

l
v

15

110 ~

....

110

CD
CD

110

2432

7

110

....
en
=r
I»
I»

(23)

M.
M,

2433

IE

J
'02
20

M'

~

36

J

(21)

1/0

,e2

20
M.
M'

16

~ 2435

e,

~ ···
23

~

'02
20

M'
M'

~ 2436

(II

24

/-

•

110 ~

1tJ ····
,e2
20
MO

32

M'

~
p-I:hlj ~

1lJ
Ir' ···
·
39

ill.

~)

p-

~ 2437

110

~
e,

31

40

M'

I ~ 2438

Q

Q

e,

rtJ ····
47

110

!!L

j--

,e2

M.20
M'
~ 2439

48

if ····
fU
IJ

l
>=1

55

110

!.!!L

,e2
20

M'
M'

56

'H
).

~ 2440

>=1

63

110

110

{~

(ill

,e2
20

I
(15)

I

1/0

1/0

M'
M'
2441
,e2
20

M'
M'

IIII

I

~ 2442

",,{14

LqE)

Pin numbers shown are for JW and NT packages.

2·174

J

(16)

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265

TIBPALR19R6M. TIBPALR19R6C
HIGH·PERFORMANCE REGISTERED·INPUT PAL@ CIRCUITS

logic diagram (positive logic)

OUTCLK~(1~)~====================================================~
I
INPUT LINES

110

rn

~'~2'0 ti:~4:j:j::t=18~:t=1~2:j:j:=1~6~=""2O~;f:2~4li1=2~8li1=3:\:2li1;::3:\:6~\=:;j~

-PRODUCT

2433
~

(23)1/0

~
~

M

2432
~

LINES

···
·
l ;
rtfJ ·
o

I/O@LtfJ
M'
2434

liD!!!.

~~~)Q

:

15

~:2

16

MO

M,

•

2435

:

P-Fl1~)Q

1/0lllr1tJ~
~f ::
M'

•

2436

:

~~~)Q

I/D!!!.~-i :

fNj!i: .
tfji2 .
M'

2437

t>- ~

•

~

:

39

IIOJ!!.

40

M'

2438

P- ~ ~)

•

:

M,

'e

2439

Q

Q

I

47

I/O!!!

II

48

•
:

I/DQ!!.ffJ2~2 ::

iJi2 ·
MO

M'

2440

I/D~

•

•
•

63

M'
2441

1/0\!!l~f'
_2442
Ml

LZ_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _+-<...!"'""'--::'O

4 3 2 I 282726

110
110
110
NC
110
I/O
110

5
6
7
8
9
10

25
24
23
22
21
20
19

II

12 1314151617 18

INPUT LATCH FUNCTION TABLE

0
L
H

LATCH OUTPUT

L
L
H

X

00

INLE

OOOU-I WO

~::::~z

L
H

~

NC - No internal connection
Pin assignments in operating mode

tlntegrated Schottky-Barrier diode-clamped transistor is patented
by Texas Instruments, U.S. Patent Number 3.463,975.
PAL is a trademark of Monolithic Memories Inc.

PRDDUCTIO. DATA dooumanta oontain infnrmation
ourrant II of publioation date. Praduota oonform to
spacificationl par the tarms of TaxIS Instrumants

:.:~:~~r,·I:I-:.ri =:~:r :'~D=::~:~ not

Copyright © 1985, Texas Instruments Incorporated

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

2-181

TIBPALT19R4M, TIBPALT19R6M, TIBPALT19RBM
TIBPALT19R4C, TlBPALT19R6C, TIBPALT19RBC
HIGH·PERFORMANCE LATCHED·INPUT PAL® CIRCUITS
TIBPALT19R4'
M SUFFIX •.• JW PACKAGE
C SUFFIX ••• JW OR NT PACKAGE

TIBPALT19R4'
M SUFFIX ..• FK PACKAGE
C SUFFIX ..• FN PACKAGE

(TOP VIEW)

(TOP VIEW)

OUTCLK
110

~

VCC
110
1/0
1/0
Q
Q
Q
Q
1/0
110

110
110
110
110
110
110

U
I-

4321282726

iiiiCE

•

5
6
7
8

25

10

20

24
23

22
21

11

DE

GNO

U

gg5!l1~gg

19
12 1314 15161718

TIBPALT19RS'

TIBPALT19RS:

M SUFFIX .•. JW PACKAGE

M SUFFIX ••. FK PACKAGE

C SUFFIX ••• JW OR NT PACKAGE
(TOP VIEW)

C SUFFIX ..• FN PACKAGE

OUTCLK

(TOP VIEW)

~

VCC
110
110

U

I-

Q

110
110
110

7

4

Q
Q
Q

110
110
110
NC

Q

liD

Q

110

110
INLE

GND ......:.:=--...;.:;.....

U

cc::)u UCO
::::::::0 z >::::::::
3 2

1 282726

7

25
24
23

8

22
21

110
110

OE

10

11
12 13 14 1516 17 18

TIBPALT19RB'
M SUFFIX ... JW PACKAGE
C SUFFIX ••• JW OR NT PACKAGE

TIBPALT19RS'
M SUFFIX .•• FK PACKAGE
C SUFFIX ••• FN PACKAGE

(TOP VIEW)

(TOPVIEWl

OUTCLK

liD

~

VCC
110

~

Q

110
110

4 '3 2 1282726

Q
Q

1/05
110 ]6
. 110 ]7
NC ]8
110 ~9
110 ~10
110 ]11

Q
Q

110
110
110
GND """:':=--....:.::JI-'

U

gg5!l1~go

o

Q
Q

DE

250
24 Q
23 Q
22 NC
21~ 0
20[ Q
19[ Q
12 131415161718

c

C C

UIWI W0

::::::::~ZO~

Pin assignments in operating mode

2-182

NC-No internal connection

TEXAS •
INSTRUMENTS
POST OFFICE BOX 6E15012 • DALLAS, ·TEXAS 76265

TIBPALT19L8M. TIBPALT19R4M
TIBPALT19L8C. TIBPALT19R4C
HIGH·PERFORMANCE LATCHED·INPUT PAL® CIRCUITS
functional block diagrams (positive logic)
'PALT19LB
EN .. I

&

'V~---o

t>----o
t>-_....._I/O
b-;-<

(

I
VIL

secruity fuse programming (see Note 4)
Vee

~
I

PIN1 _ _ _ _

II:'ll&

~tw3-e1

0V

..7h--------- -----:----- :6

~'--t_h_. .

:

vV

I
I+-tw3...1
I.-th~ J----\.

-"1/

PIN 13 _ _ _ _ _ _ _ _ _ _ _
1_ _

:
j.th.j- ----16V
I
0V

\i

NOTE 4: Pin numbers shown are for JW and NT packages only. If chip carrier socket adapter is not used, pin numbers must be changed
accordingly.

TEXAS . "

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-191

•
c

a
I»

en
::r
CD

CD
....
en

2-192

TIBPLS506M. TIBPLS506C
13 x 97 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
03090. DECEMBER 1987

•

50-MHz Clock Rate

•

Power-On Reset of All Registers

M SUFFIX ... JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE
(TOPVIEWI

•

16-Bit Internal State Registers

ClK

VCC

•

a-Bit Output Registers

•

Outputs Programmable for Registered or
Combinational Operation

•

Ideal for Waveform and State Machine
Applications

10
11
12
13
14
15
00
01
02
03
GND

16
17
18
19
110
111
112/0E
07
06
05
04

description
The TIBPLS506 is a TTL field-programmable
state machine of the Mealy type. This state
machine (logic sequencer) contains 97 product
terms (AND terms) and 24 pairs of sum terms
(OR terms). The product and sum terms are used
to control the 16-bit internal state registers and
the a-bit output registers.

~ u tl
::Qoz>!!!!:::

The outputs of the internal state registers
(PO-P15) are fed back and combined with the 13
inputs (10-112) to form the AND array. In
addition, two sum terms are complemented and
fed back to the AND array, which allows any
product terms to be summed, complemented,
and used as inputs to the AND array.
The eight output cells can be individually
programmed for registered or combinational
operation. Nonregistered operation is selected by
blowing the output multiplexer fuse. Each
combinational output must also have all fuses
blown from the reset term. Registered output
operation is selected by leaving the output
multiplexer fuse intact.

II

M SUFFIX ... FK PACKAGE
C SUFFIX ... FK OR FN PACKAGE
(TOP VIEWI

432 1 282726
5
6
7
8
9
10
11

25

24
23
22
21
20
19

18
19
110
NC

111
112/0E

12131415161718
NMCO'lt..,«l

aazzaaa

w

a:

~

l-

e)

::::l
C

oa:
~

PRODUCT PREVIEW docum..ts contoin Information
on products in the formetivo Dr dHign ~h.se of
development. Chareet.. istic deto .n~ other
srr:~t d:i:.... I::I~r
products without notic•.

:'.!':.4::

T.c:.:Jl:::7::

Copyright @ 1987. Texas Instruments Incorporated

TEXAS .."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265

2-193

TlBPLS506M, TIBPLS506C
13 x 97 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER

. logic diagram (positive logic)

0..

0

-'

IL

~
~

11

~

0..

::::;
IL

'"':I:"
C.)

«
w

W
:::l

:IE

~I ....

~
CJ

•

c

Iii

!I»
en

::T
CD

!en

I
I

"o

::D

C

c:

•...

(")

-t

"::Dm
S
m

:e

NOTES: A. All AND gate inputs with a blown link assume the logic-1 state
B. All OR gate inputs with a blown link assume the logic-O state.

2·194

TEXAS

~

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TlBPLS506M, TlBPLS506C
13 x 97 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
logic diagram (continued)

~

II

II

II

PI
U)

+or

CD
CD

~

tn
ca
+or
ca
Q

~
w

:>w
a:

a.

I(.)

::l
C

oa:
a.

TEXAS

..If

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2·195

TIBPLS506M. TIBPLS506C
13 x 97 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
S-R FUNCTION TABLE (sea Note 1)
ClK POLARITY FUSE

ClK

INTACT

t
t
t
t

INTACT
INTACT
INTACT

•
•••

BLOWN
BLOWN
BLOWN
BLOWN

S
l

R

STATE REGISTER

L

L

H

H

L

H

H

QO
L
H
INDETERMINATE

L

L

00

L
H

H
L

L
H

H

H

INDETERMINATE

NOTE 1: The S-R registers clear at power-up. 00 is the state of the
S-R registers before the active clock edge.

functional block diagram (positive logic)
CLK----------~~~

>-------------------~
16

2
",1
97x50

8xMUX

8

.,
G1

10-111

8

""C

112/0E

8

:a

o
c
o

c

I"\,.,

-I

denotes fused inputs

""C

:a
m

S
m

:e

2-196

T~.

INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265

'il

8

QO-07

TIBPLS506M, TlBPLS506C
13 x 97 x 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to disabled output (see Note 2) ................................... 5.5 V
Operating free-air temperature range: TIBPLS506M. . . . . . . . . . . . . . . . . . . . . . . .. 55°e to 125°e
TIBPLS506e . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 2: These ratings apply except when programming pins during a programming cycle.

recommended operating conditions
TIBPlS506M
VCC

Supply voltage

VIH

High-level input voltage

Vil

Low-level input voltage

IOH

High-level output current

10l

Low-level output current

tw
tsu

TIBPlS506C

MIN

NOM

MAX

MIN

NOM

MAX

4.5
2

5

5.5
5.5

4.75
2

5

5.25
5.5

0.8
-2

0.8
24

rnA

Setup time before elK t input or

Without C-a"ay
With e-a"ay
Input or feedback

TA

Operating free-air temperature

...
tI)

Q)
Q)

ns

feedback to S-R inputs
Hold time after ClK

V
rnA

Clock low

th

V
V

-3.2

Clock high

Pulse duration

UNIT

.c

en

ns

...caca

ns

at S-R inputs
-55

125

75

0

C

·e

tThe active edge of elK is determined by the programmed state of ClK polarity fuse.

electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VIK

VCC

VOH

Vee

Val
II

Vee

= MIN,
= MIN,
= MIN,
= MAX,

IH

Vce
Vee - MAX,

III

Vee

lOS
10ZH

Vee
Vce

10Zl

Vce
Vee

lec

TIBPlS506M
TYP§
MAX

TEST CONDITIONS*

= MAX,
= MAX,
= MAX,
= MAX,
= MAX,

II

=

MIN

2.4

3.2
0.25

2.4
0.4

3
0.37

25
20
-0.25

VI - 2.7 V

= 0.4 V
Va = 2.25 V
Va = 2.7 V
Va = 0.4 V
VI = 4.5 V,

-1.2

-1.2

-18mA

= MAX
10l = MAX
VI = 5.5 V
10H

TIBPlS508C
TYP§ MAX

MIN

VI

-15

Outputs open

-65
20

-15

=5

V, TA

=

25·C.

0.5

V

25

~A

20

~A

rnA

20

~A

-20

~

140

tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.

§AII typical values are at Vee

V
V

-0.25
-65

-20
140

UNIT

rnA

rnA

~

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a:

Q.

I(J

::>

Q

oa:
Q.

TEXAS . "

INSTRUMENlS
POST OFFICE BOX 65501·2 • DAllAS, TEXAS 75265

2-197

TIBPLS506M, TIBPLS506C
13 x 97 x 8 FIELD-PROGRAMMABLE LOGIC·SEQUENCER
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted). (see Note 3)
FROM
(lNPUTI

TO
(OUTPUTI
Without C-arrey
With C-Array

'PARAMETER
fmax*

ClK§
ClK
I
~.
~r

tpd
ten
!dis

Q (nonregisteredl
Q (registered
Q (nonregistered)

. TIBPLS606M
MIN TVP
MAX
60
40

TEST CONDITIONS

nBPLS606C
MIN TVPt MAX

20

Rl = 500 Il.
Cl=50pF

60
40

UNIT
MHz

20

9

9

ns

15

15
6
6

ns
ns

Q

6
6

Q

t All typical values are at VCC = 5 V. TA = 25 ·C.
*fmax is independent of the internal programmed configuration and the number of product terms used:
§The active edge of ClK is determined by the programmed state of the ClK polarity fuse.
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.

diagnostics

C

A diagnostic mode is provided with these devices that allows the user to inspect the contents of the state
registers. The step-by-step procedures required to use the diagnostics follow.

....C»C»
tn

1. Disable all outputs by taking pin 17 (DE) high (see Note 4).

CD
CD

2. Take pin 8 (00) double high to enable the diagnostics test sequence.

~

....

3. Apply appropriate levels of voltage to pins 11 (03). 13 (04). and 14 (05) to select the desired
state register (see Table 1).

(I)

The voitage'level monitored on pin 9 will indicate the state of the selected state register.
NOTE 4: If pin 17 is being used as an input to the array. then pin 7 (16) must be taken double high before pin 17 is taken high.

diagnostics waveforms
15 _ _ _ _ _. . J / , . - - - - - - - - - - - - - - - - - - - - - - VIHH
(PIN 7)

.

I

--J"i

OE
(PIN 171 _ _ _ _

;--------------...;...--------VIH
...... 100n.~ ,..-_ _ _,",\ _ _ _ _ _ _ _ _ _ ----VIHH

."
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C

c:

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(PIN0:'

I
.,.,i/;,r"T/....
v,..,.v,"Z.,.,'/;,r"TZ",WI/I
j
J//j/(p;/

m
S
m

.-_-_-_-_-_-_-_-_-_-_-_..
~:~

\e-100 ns-+t
03.04.05
(PINS 11. 13. 141

_Jt.r--------------

Vi/1///JlllillliIJJliJ//j/llj///N-- - - - - - - - - -- I

-t
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\

VOL

~100 n8--+1

.

~~ WIJ/ill/II//I//11//II//////J///////II//li//J/~m'l;,m'(;,m7hmr;;m'i;,mYhm'ihmYhmYh"T7Z ~OH

(PIN

,

Ol

~

2-198

VOHH

-VOH

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75286

TlBPLS506M, TlBPLS506C
13 x 97 x 8 FIELD·PROGRAMMABLE LOGIC SEOUENCER

TABLE 1. ADDRESSING STATE REGISTERS
DURING DIAGNOSTICS
REGISTER BINARY ADDRESS

BURIED REGISTER

PIN 11

PIN 13

PIN 14

L

L

L

Cl

L

L

L

L

H
HH

CO

L
L

H
H
H
HH
HH
HH

L
L
L
L

H
H
H
H
H
H
H
H
H

L
L
L

H
H
H
HH
HH
HH

SELECTED

L

P15
P14

H
HH

Pl

L

P2

H
HH

P3

L

P5

H
HH

P6

PO

~

P4

P7

L

PS

H
HH

P9
Pl0

L

Pll

H
HH

1"13

..

CD
CD

..c

..

P12

t/)

CO
CO

Q
PROGRAMMING INFORMATION
Texas Instruments programmable logic devices can be programmed using widely available software and
reasonably priced device programmers.
Complete programming specifications, algorithms, and the latest information on firmware, software, and
hardware updates are available upon request. Information on programmers that are capable of programming
Texas Instruments programmable logic is also available, upon request, from the nearest TI sales office,
local authorized Texas Instruments distributor, or by calling Texas Instruments at (214) 997·5762.

~
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TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2·199

I
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CD
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2-200

TlBPSG507M, TIBPSG507C
13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
MAY 1987-REVISED DECEMBER 1987

•

50 MHz Clock Rate

•

Ideal for Waveform and State Machine
Applications

•

6-Bit Internal Binary Counter

•

B-Bit Internal State Register

M SUFFIX .•.• JT PACKAGE
C SUFFIX ...• JT OR NT PACKAGE
(TOPVIEWI

ClK

•

Programmable Clock Polarity

•

Outputs Programmable for Registered or
Combinatorial Operation

•

6-Bit Counter Simplifies Logic Equation
Development in State Machine Designs

•

Dependable Texas Instruments Quality and
Reliability

VCC
16
17
18
19
110
111
112/0E
07
06
05
04

10
11
12
13
14
15
00
01
02
03

GND

description
The TIBPSG507 is a 13 x 80 x 8 Programmable
Sequenc~ Generator (PSG) that offers the
system designer unprecedented flexibility in a
high-performance field-programmable logic
device. Applications such as waveform
generators, state machines, dividers, timers, and
simple logic reduction are all possible with a PSG.
By utilizing the built-in binary counter, the PSG
is capable of generating complex timing
controllers. The binary counter also simplifies
logic equation development in state machine and
waveform generator applications.
The PSG507 contains 80 product (AND) terms,
a 6-bit binary counter with control logic, eight
SIR state holding registers, and eight outputs.
The eight outputs can be individually
programmed for either registered or
combinatorial operation. The clock input is fuse
programmable for either positive- or negativeedge operation.

-

M SUFFIX . . . . FK PACKAGE
C SUFFIX . . . • FK OR FN PACKAGE
(TOPVlEWI
:.l

. ..

CD
CD

U

::Qd~~';!.~
4

3

.c

en

...

2 1 282726

CIS
CIS

25

12
13

5
6

NC

8

22

9
10

21

24

Q

23

01

11
12 13 14 15 16 17 18
NMCUVIDIC

00 z z'O 0 0
C!l

NC - No internal connection

The 6-bit binary counter is controlled by a synchronous-clear and a count/hold function. Each control function
has a nonregistered and registered option. When either SCLRO or SClR1 is taken high, the counter resets
to zero on the next active clock edge. When either CNT/HLDO or CNT/HLD1 is taken high, the
counter is held at the present count and is not allowed to advance on the active clock edge. The SCLR
function overrides the CNT/HLD feature when both lines are simultaneously high.
Clock. polarity is programmable through the clock polarity fuse. Leaving this fuse intact selects positiveedge triggering. Negative-edge triggering is selected by blowing this fuse. Pin 17 functions as an input
and/or an output enable. When the output enable fuse is intact, all outputs are always enabled allowing
pin 17 to be used strictly as an input. Blowing the output enable fuse lets pin 17 function as an output
enable and an input. In this mode, the outputs are enabled when pin 17 is low and are in a high-impedance
state when pin 17 is high.

~

W

~

a:
Q.
t-

(.)

::l
C

oa:
Q.

PRODUCT PREVIEW do.uments .ontaln Information
on products in the formatlv. or design ~ba.. of
devllopmlnt. Cherl.taristi. data an~ other
::.-::::.at::=srr::t dt",l::a~::I~r T::,=::,:::
products without noll...

Copyright C) 1987, Texas Instruments Incorporated

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • CALLAS. TEXAS 75265

2-201

I

!

TlBPSG507M. TlBPSG507C
13 x 80 x 8 PROGRAMMABLE

SE~UENCE

GENERATOR

dellcription (continued)
The eight outputs can be individually programmed for combinational operation by blowing the output
multiplexer fuse. Each combinational output must also have all fuses blown from its associated reset term.
When the output mUltiplexer fuse is left intact, registered operation is selected.
The M suffix devices are characterized for operation over the full military temperature range of - 55
to 125
The C suffix devices are characterized for operation from 0
to 75

ac.

ac

6-BlT COUNTER CONTROL FUNC"RON TA!,LE
CNT/HLD1

CNT/HLDO

L
X
X
X
H

L
X
X
H
X

SCLR1
L

(888

SCLRO

X
H
L
L

ac.

Note 1)
OPERATION

L
H

counter active

X
L
L

synchronous clear

synchronous dear
hold counter
hold counter

NOTE 1: The 6-Bit counter and the SIR control registers are clear upon power-up.
Devices with the fuses intact will power~up in the counter~active mode.
When all fuses are blown on a product line (AND), its output will be high.
When all fuses are blown on a-sum line (OR), its outputs will be low. All
product and sum terms are low on devices with fuses intact.

c
C»

...

C»

t/)

SIR FUNCTION TABLE (sBe Nota 2)

::r

CD

CLK POLARITY FUSE

!fI)

\'

ClK
t

S

R

INTACT

L

L

00

INTACT

t

L

H
L
H
L
H
L
H

L

INTACT

t

H

INTACT

t

BLOWN

t

.H
L

BLOWN

t

BLOWN

t
t

BLOWN

L
'H

H

STATE REGISTER

H
INDETt
00
L
H
. tNDETt

t Output state is indeterminate
NOTE 2: SIR registers are clear upon power up. 00 is the state of the SIR regisier
before the active clock edge .

."

::D

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C

c:

(')

....

."

::D

m

S

m
~

2-202

TEXAS . "

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

ac

TIBPSG507M. TIBPSG507C
13 x 80 X 8 PROGRAMMABLE SE~UENCE GENERATOR
functional block diagram

,-

ClK

.,V
':'

8

6
STATE REGISTERS

~C1

'" 1
80x38

2

a.
~

axC> ~

~

*

'V
'V

..;....
~
8xC>

-.!,....

p!,--

~

10·111
112/(jE

12
1

--:--:13xC>

+
ol¥-

-

81NARY COUNTER
CTR a
1-0
G2

1S

2

54x80

'V
'V

2x
1-0

J

IR

1CT-0

C1/2.3+
G3
1CT-0

~C1
~ 'V

)
8

1S

8

IR

OUTPUT CEll
8

1

~NC1
EN
8x
1-0
8

1S

8

]

-

I"U

CO·C5

8x
1-0

8

'V
'V

~

IR

'-

MUX

"V~
8

,.

r

G1

Qo=

f

denotes fused inputs

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TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265

2·203

TIBPSG507M, TIBPSG507C
13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
logic diagram (positive logic)

'"r
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""05" , ,

""

'"

"" ""

'"

16

" ,

:~~
112/0E

f/
I)

If;G;l

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)Il
-"'~

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;;.

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CD

-'""'
;;.

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~

~DO

ro-~

:;;'::

...

~

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"'-

P2

,

I~ I-f.'

- ~"

I::::

-X>

...r:.. ~
.~

r.=

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~~
-'""-:F~

~~
,~

Hi'

~QO

"'-'

~~~"
"C

~uur=~02

o

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2-204

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~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 '. DALLAS, TEXAS 75265

TIBPSG507M. TIBPSG507C
13 )( 80 )( 8 PROGRAMMABLE SEQUENCE GENERATOR
absolute maximum ratings
Supply voltage, Vee (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage, VI (see Note 3) ................................................ 5.5 V
Voltage applied to a disabled output (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free:air temperature range: TIBPGS507M. . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
TIBPGS507e. . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 75°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 3: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions
M SUFFIX

PARAMETER
Supply voltage

VCC
V,H

High-level input voltage

V,L

Low-level input voltage

IOH

High-level output current

IOl

Low-level output current

tw

4.5
2.

before ClK
active transition

C SUFFIX

NOM

MAX

5

5.5

MIN
4.75

5.5

2

0.8
-2
12

th

after ClK

active transition

Clock low
Input or feedback
to SIR inputs

MAX
5.25

to SClRa
Input or feedback

~

V

5.5

V

0.8
-3.2
24

V
mA
mA

Q)
Q)

15

ns

25

ns

25

ns

.c

en

ca
ca

C

a

at SIR inputs
Input or feedback

ns

a

at SCLO
Input or feedback

Operating free-air temperature

UNIT

~

Input or feedback

a

atCN'l'/HlDa
TA

5

ns

to eN'!'IHOLDa
Input or feedback
Hold timet

NOM

Clock high

Pulse duration

Setup timet
tsu

MIN

-55

125

0

75

·C

t'nterna' setup and hold times, tsu feedback to SClR1, feedback to eN'!'/HlD1: th feedback at SClR1 and feedback at eN'!'/HlD1. are
guaranteed by f max specifications. The active transition of ClK is determined by the programmed state of the ClK polarity fuse.

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TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265

2-205

TIBPSG507M, TIBPSG507C
13 x80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted 1
PARAMETER
VIK
VOH
VOL

IL
IIH
III
lOS
!OZH
IOZl

TEST CONDITIONS
VCC
VCC
VCC
Vee
Vcc
VCC
VCC
Vee
Vee

=
=
=
=
=
=
=
=

MIN,
MIN,
MIN,
MAX,
MAX,
MAX,
MAX,
MAX,
MAX,

MIN

II = -18mA
10H = MAX
10l = MAX
VI = 6.5 V
VI = 2.7 V
VI - 0.4 V
Vo = 2.25 V
VO. = 2.7 V
Vo = 0.4 V
VI - 4.5 V,
OutoutsoDen

2.4

M SUFFIX
TYpT
3.2
0.25

MAX
-1.2

MIN
2.4

0.4
25
20
-0.25
-55
20
-20

-15

C SUFFIX
TypT
3
0.37

-15

MAX
-1.2
0.5
26
20
-0.25
-55
20
-20

UNIT
V
V
V
,.A
,.A
rnA
rnA
,.A
,.A

Eow. . . . . . . . . . . . . ..-.. . . . . . . . . . . . . _ . . ._ ,. . . . . .,....
ICC

o

VCC = MAX

(unless otherwise notedl (see Note 41

I»

;-

-rnA

140

140

PARAMETER

en

::r'
CD

fmax *

!

(I)

tpd
ten
tdis

FROM

TEST
CONDITIONS

TO

5-Blt counter
5-Bit counter with SClR1 or BlT/HlD1
5-Bit counter with SClRO or BlT/HlDO
SIR registers
CLK§
Q (non-registered) 1
ClK§
Q (registered)
Q non-reaisteredl
I
OE~

Q

OEt

Q

MIN

M SUFFIX
TYpt
MAX

Rl = 500 0,
CL=50pF

MIN

CSUFFIX
Typt
MAX

50
35
50

UNIT

MHz
20
12
18
12
12

ns
ns
ns
ns
ns

NOTE 4: load circuits and voltage waveforms are shown in Section 1 of the TTL Data Book, Volume 4.
tAli typical values are at VCC = 5 V, TA = 25°C.
*fmax is independent of the number of product terms used.
§The active edge of CLK is determined by the programmed stete of the ClK polarity fuse.
'tpd ClK to Q (nonregistered) is the same for data clocked from the counter or state registers.

PRINCIPLES OF OPERATION

;g

PSG DESIGN THEORY

c:
n

Most s.tate machine and waveform generator designs can be simplified with the PSG by referencing all or part
of each sequence to a binary count. The internal state registers can then be used to keep track of which binary
count sequence is in operation, to store input data and keep track of internally generated status bits, or as output
registers when connected to a nonregistered output cell. State registers can also be used to expand the binary
counter when a larger counter is needed.

oC

-I

"'0

::D

m
<
m

Through the use of the binary counter, the number of product lines and state registers required for a design
is usually reduced. In addition, the deSigner does not have to be concerned about generating wait states where
the outputs are unaffected because these can be timed from the binary counter. For detailed information and
examples using this design concept, see the "DESIGNER'S GUIDE TO THE PSG507" applications report (literature
number SPDA003).

:e

2-206

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 752.65

TIBPSG507M. TIBPSG507C
13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
PRINCIPLES OF OPERATION
PROGRAMMING INFORMATION
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on firmware, software, and
hardware updates are available upon request. Information on persons capable of programming Texas Instruments
Programmable Logic is also available upon request from the nearest TI sales office or local authorized TI distributor;
information may also be obtained by calling or writing Texas Instruments at (214) 997-5762, Texas Instruments,
Post Office Box 655803, Dallas, Texas 75265.

TYPICAL APPLICATION

RFC
DYNAMIC RAM
REFRESH
TIMER

DYNAMIC
MEMORY
CONTROLLER
SN74ALS6301

REFREQ

REFREQ

MEMORY
TIMING
CONTROLLER
TIBPSG507
OSC

CLOCK
GENERATOR

RFC

-

QO·QS

CLK
VCC
~ RESET

iN
WAIT

R/iN
A22
ALE

AS

RAS
CAS

L

-

MSEL
MCI

2

r
Fo~

-

MSEL

HSA ~

*
*

r--

SN74ALS6310 ~

-

-

RASI
CASI

MICROPROCESSOR

7

LE

-

ADDRESS

MCI
OE
CS

-

~

-----+

r

-~

-~

RASO
CASO

iN

~

-~
-~
-~

-~
~

-~

RASI

DATA

TEXAS . "

POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

...caca

J
AO·AS
RAS2

BANK2
1 MEG x 32 BITS
TMS4Cl027

CAS2

iN

I
AO·AS

~

w

BANK3
1 MEG x 32 BITS
TMS4Cl027

:>w
a::

a..

iN

I-

l'

::J

detailed information, please see the "SYSTEMS SOLUTION FOR STATIC COLUME DECODE" Application Report.

INSTRUMENTS

f/)

BANKI
lMEG x 32 BITS
TMS4Cl027

CAS3

~

CD
CD

.c

CASI

RAS3
SELO.l

~...
C

I
AO·AS

--~ iN

,

MEMORY BANK SIGNALS

AO·AB

BANKO
1 MEG x 32 BITS
TMS4Cl 027

o
C

oa::
a..

2-207

TIBPSG501M. TlBPSG501C
13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
diagnostics
A diagnostics mode is provided with these devices that allows the user to inspect-the contents of the state
registers. The following are the step-by-step procedures required for the diagnostics.
1. Disable all outputs by taking OE (pin 17) high. (Note: If pin 17 is being used as an input to the array, then
pin 15 or pin 7 must be taken to double high first before pin 17 is taken high.)
2. Take 00 (pin 8) double high to enable the piagnostics test sequence.
3. Apply appropriate levels of voltage to pins 11, 13 and 14 to selectthe desired state register, (see Table 1)
4. The voltage level monitored on pin 9 will indicate the state of the selected state register.

diagnostics waveforms
5 _________J/~--------------------------------------------VIHH

(PIN 71

.

DE _ _ _ _ _'l~--------------------------------------~------VIH
(PIN, 17)
I
14--100 ns---+t

_ _ _ _ _ _ _ _ _ _ VIHH

{~N~~JS~S~~S:IS~lWCI'J,~,:,~,:tsxfl'~----~\

-

-

-

-

-

-

-

-

-

- VIH
VIL

14-100 ns--.lI _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ VOHH
~M~
(PINS 11. 13. 14)

S S S s s s s .s s s s s s s , ,

v

~
S 5 ..
I

OH
VOL

I
1+--100 ns--+(
Q1

(PIN 9)

S S S S

I

S Ss s s s s s s s s s s s s s s s s s s • s s s s s s SS ,

TABLE 1. ADDRESSING STATE REGISTERS DURING DIAGNOSTICS
REGISTER BINARY ADDRESS
PIN 11
PIN 13
PIN 14

""0

:0

o
C

c:

o

-t
""0

:0

m
S
m
~

2-208

BURRIED REGISTER SELECTED

L

L

L

L

L
H

L

L

HH

CNT/HLDO

L

H
H

L
H
HH

CNT/HlD1

SCLRO
SCLR1

PO
P1

l
l

H

L

HH

l

P2

L

HH

P3

L

HH

H
HH

H

L

L

P4
P5

H
H

L
l

H
HH

P6
P7

H

H

L

CO

H
H

H
H

H
HH

C1

H

HH

L

H

HH

H

C3
C4

H

HH

HH

C5

C2

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

,

VOH
VOL

TlB82S 1OSBM, TIB82S 1OSBC
16 x 48 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
02897, SEPTEMBER 1985-REVISED DECEMBER 1987

•

50· MHz Clock Rate

•

Power-On Preset of All Flip-Flops

•

6-Bit Internal State Register with 8-Bit
Output Register

M SUFFIX, , . JD PACKAGE
C SUFFIX ... JD OR N PACKAGE
(TOP VIEW)

•

Power Dissipation ... 600 mW Typical

•

Programmable Asynchronous Preset or
Output Control

•

Functionally Equivalent to. but Faster than
82S105At

description
The TIB82S 1OSB is a TTL field-programmable
state machine of the Mealy type, This state
machine (logic sequencer) contains 48 product
terms (AND terms) and 14 pairs of sum terms
(OR terms), The product and sum terms are used
to control the 6-bit internal state register and the
8-bit output register.

elK

Vee

17
16
15
14
13
12
11
10
Q7
Q6
Q5
Q4
GND

18
19
110
111
112
113
114
115
PRE/OE
QO
Q1
Q2
Q3

PI
....
en

Q)
Q)

M SUFFIX ... FK PACKAGE
C SUFFIX ... FK OR FN PACKAGE
(TOP VIEW)

The outputs of the internal state register
(PO- PSI are fed back and combined with the 16
inputs (l0-11S) to form the AND array. In
addition a single sum term is complemented and
fed back to the AND array. which allows any of
the product terms to be summed.
complemented, and used as an input to the AND
array.
The state and output registers are positive-edgetriggered SIR flip-flops. These registers are
unconditionally preset high on power-up. Pin 19
can be used to preset both registers or. by
blowing the proper fuse, be converted to an
output control function.

>l

.c

(/)

....asas

U

~5ec::d~~~
4

3

2

Q

1 282726

5

25

6

24

7

23

8

22

9

21

10

20

11

110
111
112
113
114
115
PRE/OE

12 1314 15161718

The TIB82S1 OSBM is characterized for operation
over the full military temperature range of
-SsoC to 12SoC. The T1B82S10SBC is
characterized for operation from OOC to 7S DC.
t Power-up preset and asynchronous preset functions are not
identical to 8251 05A. See Recommended Operating Conditions.

PRODucnOI DATA ..... m.nts co.taln infarmdia.
.umot II of publication dets. Praducls .onfarm to
opeoillcatlo.. per.lb. tarms of T•••• Instrum.nts
:'=~~r:"f::I~li =~:i:r :.\o:::::~. not

Copyright @ 1985. Texas Instruments Incorporated

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DAL.LAS. TEXAS 75265

2-209

TIB82S105BM, TIB82S105BC
16 x 48 x 8 FIELD,PROGRAMMABLE LOGIC SEOUENCER
WITH 3·STATE OUTPUTS OR PRESET
functional block diagram (positive logic)
PRE/OE

-----4If--f-"'"

~--~----~----------,
EN

S

CLK-------------------------------------+-~~
.. 1
48 X 29

&

8

8

8

16xI>
10_115 __.."...1:.::6-:....,-I

E

48

cm

6xI>

tn

I>

'V

....~

6

6

1R

'V

~

CD
CD

....til

6

'V denotes fused inputs.

timing diagram

vee

PRE

OPTIONAL

M

10-11&

---J
I
I

I~-----T--------I4--tsu --.!

rh

i

--~I------------~------~I I ~----I
~I-+I~-------

-K _________
~.

I

elK

r-----1

--~I~----------~I

~

I

!ot=tsu
.

I

I
I

I

INTERNAL
STATE
REG
PO-P5

V

I

___-JA\~I~,~I--~--~~

I

=iII

~~

-_-_-_-_-_-_-_

-11r-v~--~!r-------:I:~tT-~::f_
I

I
I
. I
I
I
QO-Q7---V---~~-----~!~------~·
iJ-----\\..----J
~

2-210

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

QO-Q7

TIB82S 185BM, TIB82S 185BC
16 x 48 x 8 FIELD·PROGRAMMABLE LOGIC SEOUENCER
WITH 3·STATE OUTPUTS OR PRESET
logic diagram (positive logic)
10 191
181
11
12 171
161
" 151
14
141
15
131
17 121

,.

18

19
110
111

112

)J.
I

1271

(19)

12.,
,25,
(24)

•

(23)

PIIE/1Ir

E

(221
11.
114 1211
115 1201

.,

PO

''32
PO

'5

~I

~.o

rt,~~l
~

~

tt,~1

~P2

~~1t

~P3

~

N
~

~

~

H>~
'S;~e
H;~~

~

H;~1

=

,

'fr

1(171

H;~~L

H>~
<;S"

,.

H>~
~

~

~

a
~

~

47· • • • • • •

....... . ........ ....... . ........

• •••••• 0

H>~

H>~
~11~
~

r+.~~
.!!!..:.

'\l
H>.J!r.-

,181

00
01

I

,

'(161

1 115 ,

01

I
1 113)

04

1
1(121

05

I

'1'1'
1
1(101

111

o.
07
elK

INPUT LINES

NOTES:

1. All AND gate inputs with a blown link float to a logic 1.
2. All OR gate inputs with a blown link float to a logic O.

TEXAS

.Jf

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75266

2·211

TlB82S105BM, TlB82S105BC
16 x 48 x 8 FIELD~PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
absolute maximum ratings over operating free-air temperature range (unless otherwise hoted)
Supply voltage, Vee (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " 5.5 V
Voltage applied to a disabled output (see Note 3) . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: TIB82S 105BM . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°e
TIB82S105Be .......................... ooe to 75°e
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 3: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions
M SUFFIX

PARAMETER

...C
I»
I»

VCC

Supply voltage

VIH
Vil

High-level input voltage
low-level input voltage

IOH

High-level output current
Low-level output current

IOl

fclock

Clock frequency t

::::r

CD
CD

...

NOM

MAX

MIN

NOM

MAX

4.5
2

5

5.5
5.5
0.8
-2
12

4.75
2

5

5.25
5.5
0.8
-3.2
24

0

40

0

50

0

25

0

30

1 thru 48 product terms

C/)

without C-array*

Pulse duration

tsu

Setup time before ClKi.
1 thru 48 product terms

tsu
th

Setup time. Preset low (inactive) before ClKi§
Hold time, input after ClKi

TA

Operating free-air temperature

CI)

UNIT
V
V
V
mA
mA

MHz

1 thru 48 product terms
with C-array
Clock high or low

tw

C SUFFIX

MIN

12
18
20
35

10
15
15
30

10
0
-55

8
0
0

Preset
Without C-array
With C-array

125

ns
ns
ns
ns

75

°c

tThe maximum clock frequency is independent of the internal programmed configuration. If an output is fed back externally to an input,
the maximum clock frequency must be calculated.
* The C-array is the single sum term that is complemented and fed back to the AND array.
§ After Preset goes inactive. normal clocking resumes on the first low-ta-high clock transition.

2-212

TEXAS

..If

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TIB82S 105BM, TIB82S 105BC
16 x 48 x 8 FIELD-PROGRAMMABLE LOGIC SEOUENCER
WITH 3-STATE OUTPUTS OR PRESET
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER

M SUFFIX

TEST eONDITIONst

MIN

VIK
VOH

Vee - MIN,

II - -18 rnA

Vee = MIN,

Val
II

IOH = MAX
IOl = MAX

IIH

Vee = MIN,
Vee - MAX,
Vee - MAX,

III

Vee - MAX,

VI - 0.4 V

IO§
IOZH

Vee = MAX,
Vee - MAX,

Va = 2.25 V
Vo - 2.7 V

IOZl

Vee - MAX,

Vo = 0.4 V

lee

Vee = MAX,
PRE/OE input at GND,

VI = 4.5 V,
Outputs open

e SUFFIX
MAX

TYP*

MIN

TYP*

MAX

-1.2
2.4

3.2

2.4

0.25

0.4

VI - 5.5 V
VI - 2.7 V

25
20
-0.25
-112

-30

-1.2
3
0.37

0.5

V

25

pA
pA
rnA

-112

rnA

20
-20

pA

180

rnA

-30

180

V
V

20
-0.25

20
-20
120

UNIT

120

pA

switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER

1

f

rnax

FROM

TO

I Without e·array
I With e-array

elKt

Q

tpd

PREt

Q

tpd

Veet

Q

ten
tdis

OEl
OEt

Q

tpd

TEST CONDITIONS

M SUFFIX
MIN

TYP*

40
25

70
45
8

Rl = 500O,
el=50pF

Q

e SUFFIX
MAX

0

20
25
10

10
5

25
15

12

MIN

TYP*

50
30

70
45
8

MAX

~....
CD
CD

UNIT

.s::.

C/)

...

MHz
ns

12

15
20

0

10

10
5

20
10

ns
ns

CO
CO

C

ns

ns

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
* All typical values are at Vee = 5 V, T A = 25 De.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit current, lOS.
1f max is independent of the internal programmed configuration and the number of product terms used.

programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5762.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-213

TIB82S 105BM, TIB82S105BC
16 x 48 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
diagnostics
A diagnostics mode is provided with these devices that allows the user to inspect the contents of the
state register. When 10 (pin 9) is held at 10 V, the state register bits PO-P5 will appear at the 00-05
outputs and 06-07 will be high. The contents of the output register will remain unchanged.

diagnostics waveforms

-y,.....------------------...;....-----_-

VIH

11-115-11\

---------------------------Vli.

I

I

r------""\-- - - - *
/1
1\

I
I

11

~--------------~II

l, ,

l0-A,

1 :\~Ih-+l

I

!

eLK
INTERNAL

I
14-- tsu

_____

STATE REGISTER
PO-P5 -

PS
-

-

-

-

I
~.

,-X
~
:

-

I

~

00-05----0-n---+:-"-"*.

I

I

I
------r-------'--VIH

I I
I

'
I

r

VIL

I

tw--l+j

I

----+10V

~~V
,.~------------- VIH
I ,
I '--------VIL

-

-t- -

-:S- -

-

-

/4---tp d

-

-1- - - - - -

----+:

On+1

--t -

X

I

-

-

/4--tPd
NS

l

-

-

-

-VOH

-

VOL

EVOH
VOL

I+-tpd-+l

OPTIONAL
~

PS

=

Present stete. NS

----------------------------0 V

=

Next state

TEXAS ."

2·214

INSTRUMENTS
~ST OFFICE BOX

665012 • DALLAS. TEXAS 75265

TIB82S 105BM, TIB82S 105BC
16 x 48 x 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
test array
A test array that consists of product lines 48 and 49 has been added to these devices to allow testing
prior to programming. The test array is factory programmed as shown below. Testing is accomplished
by connecting 00-07 to 18-115, PRE/OE to GND, and applying the proper input signals as shown in the
timing diagram. Product lines 48 and 4~ MUST be deleted during user programming to avoid interference
with the programmed logic function.
TEST ARRAY PROGRAM
OPTION PRE/OE
AND
PRODUCT
LINE

C

48
49

C 1 1 1 1 1 1
54 32 1o

X -

- X

lH

OR

INPUT

PRESENT STATE

NEXT STATE

OUT

(In)

(PS)

(NS)

(an)

514J3J2J 11° 51413121110 7161514l312J11°

918L716L5J4J3J2~110
H H H H H H HIHIHIHIHIHIHIHIHIH HIHIHIHIHIH LILILILILIL LILILILILILILIL
L L L L L L LILILILILILIL ILILIL LILILILILIL HIHIHIHIHIH HIHIHIHIHIHIHIH

test array waveforms

~-------------------------------------------------5V

VCC~

___ _

I+-tw~
I
I

I
I

:

CLK

--------------oV

nL________________----iIL

---'----------!I:-

I4--tsu~th-..l

1

1

I

I

I4-tpd~

~ tpd

tpd~

~~II_--_--_-_-::~

1

1

STATE

VIL

1

I

00-Q7 ______--'/or:------------~\J
I

INTERNAL

VIH

I! .I-----------------+l----~'-"=
.
::~

:

10-17

I

1

\J

RE~S~:: _ _ _ _.I1

I

/r_-_-_-_~~:

TEST ARRAY DELETED
OPTION PRE/~
AND
PRODUCT
LINE

C

C 1 1 1 1 1 1
5

48
49
x=

- -

H

INPUT

PRESENT STATE

NEXT STATE

OUT

(In)

(PS)

(NS)

(an)

4 3 2 1 0 91817161514J3J2111° 51 4 1313(110 514131 2J 1 10 716151413121110
H H H H Ii HIHIHIHIHIHIHIHIHIH HIHIHIHIHIH -1-1-1-1-1- -1-1-1-1-1-1-1-

X L L L L L L LILILILILILILILILIL LILILILILIL

Fuse intact, -

IH

OR

I-I

01 JJ

-1-[

-[I

J J:1

= Fuse blown

TEXAS . "

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

2-215

TlB82S105BM. TlB82S105BC
16 x 48 x 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
TIB82S105B. 82S105A COMPARISON
The Texas Instruments T1682S 1056 is a 16 x 48 x 8 Field-Programmable Logic Sequencer that is functionally
equivalent to the Signetics 82S1 05A. However, the TI682S1 056 is designed for a maximum speed of 50 MHz
with the preset function being made conventional. As a result the TI682S1058 differs from the 82S105A in
speed and in the preset recovery function.
The TI882S 1058 is a high-speed version of the original 82S 105A. The TI882S 1058 features increased switching
speeds with no increase in power. The maximum operating ,frequency is increased from 20 MHz to 50 MHz
and does not decrease as more product terms are connected to each sum (OR) line. -For instance, if all 48 product
tems were connected to a sum line on the original 82S105A, the f max would be about 15 MHz. The f max
for the TIB82S1058 remains at 50 MHz regardless of the programmed configuration. In addition, the preset
recovery sequence was changed to a conventional recovery sequence, providing quicker clock recovery times.
This is explained in the following paragraph.

E

The TI882S1058 and the 82S105A are equipped with power-up preset and asynchronous preset functions.
The power-up preset causes the registers to go high during power-up. The asynchronous preset inhibits clocking
and causes the registers to go high whenever the preset pin is taken high. Afte,r a power-up preset occurs,
the minimum setup time from power-up to the first clock pulse must be metin order to assure that clocking
is not inhibited. In a similar manner after an asynchronous preset, the preset input must return low (inactive)
for a given time, tsu, before clocking.
The Signetics 82S 105A was designed in such a way that after both power-up preset and asynchronous preset
it requires that a high-to-Iow clock transition occur before a clocking transition (Iow-to-high) will be recognized.
This is shown in Figure 1. The Texas Instruments TIB82S 105B does not require a high-to-Iow clock transition
before clocking can be resumed, it only requires that the preset be inactive 8 ns (preset inactive-state setup
time) before the clock riSing edge. See Figure 2.
The TIB82S105B, with an f max of 50 MHz, is ideal for systems in which the state machine must run several
times faster than the system clock. It is recommended that the TIB82S 105B be used in new designs. However,
"the TIB82S1058 is used to replace the 82S 105A. then the customer must understand that clocking will begin
with the first clock rising edge after preset.
TABLE 3. SPEED DIFFERENCES
PARAMETER
'fmax

tpd, elK to a

2-216

82S105A
SIGNETICS

TIB82S105B
TIONlY

20 MHz

50 MHz

20 ns

15 ns

TEXAS ",

INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265

TIB82S105BM, TIB82S105BC
16 x 48 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
Vee

--"l
I

I4--t su -+I
PRE

I

I

I
I

elK
REGISTERS

. I

r I~--+----------I

I
I
--~--~I--------~i

____c

I

___XJJ
I

:J

I

FIGURE 1. 82S105A PRESET RECOVERY OPERATION

vee

-.I!

I
I
I
I

PRE

EJ...

~tsu
I

11

I
I
I

U)

I

CI)
CI)

I

I
I

elK
REGISTERS

J

I
I

I
I

I
I

\

X

XJ/

~

I

I

\

X

FIGURE 2. TIB82S1058 PRESET RECOVERY OPERATION

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAlt.AS, TeXAS 75265

x::

tn
ca
ca

....
C

2-217

c

Q)

r+
Q)

en

::r

CD
CD

r+

In

2-218

TlB82S167BM, TIB82S167BC
14 x 48 x 6 FIELD·PROGRAMMABLE LOGIC SEDUENCER
WITH 3·STATE OUTPUTS OR PRESET
02896, JANUARY 1985-REVISED DECEMBER 19B7

•

Programmable Asynchronous Preset or
Output Control

•

Power·On Preset of All Flip-Flops

•

8-Bit Internal State Register with 4-Bit
Output Register

•

Power Dissipation . . . 600 mW Typical

•

Functionally Equivalent to, t but Faster than
82S167A

M SUFFIX ... JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE
(TOP VIEW)

ClK

VCC

16
15
14
13
12
11
10
00
01
02

PO

GND

03

description
The TIB82S167B is a TTL fieldcprogrammable
state machine of the Mealy type. This state
machine (logic sequencer) contains 48 product
terms (AND terms) and 12 pairs of sum terms
(OR terms). The product and sum terms are used
to control the 8-bit internal state register and the
4-bit output register.
The outputs of the internal state register (PO-P7)
are fed back and combined with the 14 inputs
(10-113) to form the AND array. In addition the
first two bits of the internal state register (PO-P1)
are brought off-chip to allow the output register
to be extended to 6 bits if desired. A single sum
term is complemented and fed back to the AND
array, which allows any of the product terms to
be summed, complemented, and used as inputs
to the AND array.
The state and output registers are positive-edgetriggered SIR flip-flops. These registers are
unconditionally preset high on power-up. PRE/OE
can be used as PRE to preset both registers or,
by blowing the proper fuse, be converted to an
output control function, OE.

17
18
19
110
111
112
113

PRE/OE
Pl

M SUFFIX ... FK PACKAGE
C SUFFIX ... FK OR FN PACKAGE

...
II)

(TOP VIEW)
~

CD
CD

u

.c

!2!Qd~~!::!!1
4
13
12

NC

3 2

(I)

...

1 282726

ta
ta

25
24

7

23

8
9

22
21

10

20

C

19

11
12 131415161718

NC-No internal connection

The TIB82S167BM is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The TIB82S 167BC is
characterized for operation from O°C to 75°C.

t Power

up preset and asynchronous preset functions

are not identical to 82S167A.

PRODUCTIOI DATA d••umanll contain i.'.rmati••
currant a. of publioation data. Products .onform to
spa.ilioati••• per the term. Ta... Instrumanll

:'=~i~;':~':.7.;

0'

==:i:;:'l"=~~~.

nD!

Copyright @ '985, Texas Instruments Incorporated

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265

2-219

TIB82S167BM. TIB82S167BC
14x 48 x 6 FIELD·PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
functional block diagram (positive logic)
PRE/~

r-u

~

-

LEN

-:f"'
----../

...--- 8

CLK

"1 C1
~1

&
45X 48

14Xt>
10-113

14

Ec

2Xt>

~
~

+-

P-

!m

6Xt>

(I)

~

~

:::r'

...
CD
CD

r

(I)

f-!.-

t>

~

4

48X 25

4

'V
'V

2

2

'V
'V

~

QO-03

2X
18 1 - 1 ",
1R

PO,P1

'V
'V

6X
18 1 _ 1

6

6

1R

l
6

2

'V denotes

2-220

2

~'

'V

'V

r

4X
18 1=1", 4
1R

fused inputs

TEXAS •

INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75266

fo-

TlB82S167BM. TIB82S167BC
14 x 48 x 6 FIELD·PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
timing diagram

Vee

~

PRE

I
I

I

~

--~I------~
OPTIONAL

OE

10-113

rh

I

--~I~----------~------~I

I

I

I

--+-<
I

elK

~~-ts-u~~------

,~------­

Xl:

~--------~----J~~t~su-~~~-----­
I

I

I
I

I

~~!~~NR~~ --.J/~---T.---------L"'--------;II---';-..I.!------P2-P7

00-03, PO-P1

I

;

I
I
I
I
I
IJ~,\r---~!~--~yl-------II
'__---..J

•

. TEXAS
.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-221

TIB82S167BM, TIB82S167BC
14 x 48 x 6 FIELD·PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
LOGIC DIAGRAM
10 '81

171
12 '81

..,. '"
13

'41

(OP11ONI

131

IS

17 '231
1221

I.

""1

121

I

1161

II.
II' ,191
112

113

PRE/(j'E

1211
1201

•

1181

E

1171

.,.,
PO

.3
P4

.0
PO
.7

C
C
,S

~
.,..,

~

~

~

~

--'"'

..fht:
~

'\t
.~

~;~l:

~2~t:
'R S
m;;;;;

~

~

I

~

c:t"gj....
;r.::;

~I

r;T'"1

~
or.;
~
•

~
•
47

NOTES:

. 2-222

'"

40 3.

'M

32 31

...

24 23

...

18111

...

8

7

1. All AND gate inputs with a blown link float to the high level.
2. All OR gate inputs with a blown link float to the low level .

. TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

...

~;!1.-

•

(151 P

I
I 1141

I 1131

PO

Q3

I
11111

Q2

I
I ,101

I
I

191

111

Q,
GO
CLK

TlB82S167BM. TIB82S167BC
14 x 48 x 6 FIELD·PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 3) . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . .. 5.5 V
Operating free-air temperature range: TIB82S 167BM . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°e
TIB82S167Be .......................... ooe to 75°e
Storage temperature range ......................................... - 65 °e to 150 °e
NOTE 3: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions
M SUFFIX

PARAMETER
VCC
VIH

Supply voltage

Vil

low-level input voltage

IOH

High-level output current

IOl

Low-level output current

High-level input voltage

NOM

MAX

MIN

NOM

MAX

4.5
2

5

5.5
5.5
0.8
2
12

4.75
2

5

5.25
5.5
0.8
-3.2
24

0

40

0

50

0

25

0

30

1 thru 48 product terms
fclock

tw
tsu
tsu
th
TA

Clock frequency t

Pulse duration

without C-array*
1 thru 48 product terms
with C-array
Clock high or low

Setup time before ClK t,

Preset
Without C-array

1 thru 48 product terms

With C-array

Setup time. Preset low (inactive) before ClKt§
Hold time, input after ClKt
Operating free-air temperature

C SUFFIX

MIN

UNIT
V
V
V
mA
mA

MHz

12
18
20
35

10
15
15
30

10
0
-55

8
0
0

125

ns
ns
ns
ns

75

°c

t The maximum clock frequency is independent of the internal programmed configuration. If an output is fed back externally to an input,
the maximum clock frequency must be calculated.
* The C-array is the single sum term that is complemented and fed back to the AND array.
§ After Preset goes inactive. normal clocking resumes on the first low-to-high clock transition.

TEXAS . •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-223

TlB82S167BM, TlB82S167BC
14 x 48 x 6 FIELD·PROGRAMMABLE LOGIC SEOUENCER
WITH 3·STATE OUTPUTS OR PRESET
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VIK
VOH
VOL
II
IIH
III
IO§
IOZH
IOZl

C

m

MIN

TYP*

2.4

3.2
0.25

IOH - MAX
IOl - MAX
VI - 5.5 V
VI - 2.7 V
VI - 0.4 V

Vee - MAX,
Vee - MAX,
Vee - MAX,
Vee = MAX,
Vee - MAX,
Vee - MAX,
Vee - MAX,
PRE/OE input at GND,

Vo = 2.25 V
Vo - 2.7 V
Vo - 0.4 V
VI - 4.5 V,

PARAMETER

(I)

, I Without e-array

:r
CD
CD

~

o

'max .

FROM·

TO

90

dod....., ""_

TEST CONDITIONS.

2.4

3
0.37

MAX
-1.2
0.5
25
20
-0.25

-30

-112

90

160

UNIT
V
V
V
p.A
p.A
mA

20
20

mA
p.A
p.A

160

mA

and ope...... , ..... tempe............
M SUFFIX

MIN

40

I With e-array

TYP*

20
20

~

m

MIN

0.4
25
20
-0.25
-112

Outputs open

OW", . . . . . . . . . .

(unless otherwise noted)

-30

C SUFFIX
MAX
-1.2

II - -18 mA

Vee - MIN,
Vee -.MIN,
Vee - MIN,

E . . . _. . .""""""
lee

M SUFAX

TEST CONDITIONSt

25

e SUFFIX

TYP*
70
45

MAX

10
8
0

MIN
50
30

UNIT

TYP*
70
45

MAX

20
25
10

10
8
0

15
20
10

ns
ns
ns

MHz

tpd
tpd
tpd

elK,
PREt

Q

Veet

Q

ten

OE!

Q

10

25

10

20

ns

1dis

OEt

Q

5

15

5

10

ns

Q

Rl = 500 n,
el = 50 pF

t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, TA = 25°e.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit current, lOS.
,. f max is independent of the internal programmed configuration and the number of product terms used.

programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5762 ..

2·224

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 866012 • DALLAS. TEXAS 76265

TIB82S167BM. TIB82S167BC
14 x 48 x 6 FIELD·PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
diagnostics
A diagnostics mode is provided with these devices that allows the user to inspect the contents of the
state register. When 10 (pin 9) is held at 10 V, the state register bits P2-P7 will appear at the 00-03 and
PO-Pl outputs. The contents of the registers, 00-03, and PO-Pl remain unchanged.

diagnostics waveforms

-y..----------------------------vIH
11·113 - - ' "

1 ~--------------------------Vll

,I

=*
1

10

-

I

1
I

r------"'----------+10V

+
---------J11
v
..(. I

--------'1
1
~th~ 1

:,\-------

1

I

ClK ----i:i---~l
1
INTERNAL

I '

-

I1 '
1

PS
--

-I -

-+ - - - - -

I

:

tw----i+j

I

I

QO-Q3,PO.Pl----Q-n---+:-""""'*
I

I

PI
....
fI)

CI)
CI)

.c

'"....

Il

T- -:S- - -1 - - - - - -

.,"

VIH
Vil
:IH

r---------

"1- X

t4--tsu

____ _

STATE REGISTER

P2-P7- -

*~V
,
I c-, ' - - - - - - - I \

CO
CO

,

k--tpd-----+:

Qn+l

--I -

X

,

-

-

-

-

I4--tpd~
NS

-

E

-VOH

-

o

VOL

VOH
VOL

I4-tpd-.l

OPTIONAL
~

-----------------------------0 V

PS = P,esent State
NS = Next State

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265

2-225

TIB82S167BM, TIB82S167BC
14 x 48 x 6 FIELD·PROGRAMMABLE· LOGIC SEOUENCER
WITH :i·STATE OUTPUTS OR PRESET
test array
A test array that consists of product lines 48 and 49 has been added to these devices to allow testing
prior to programming. The test array is factory programmed as shown below. Testing is accomplished
by connecting 00-03 to 110-113, PRE/DE to GND, and applying the proper input signals as shown in the
timing diagram. Product lines 48 and 49 must be deleted during user programming to ~void interference
with the programmed logic function.

test array program

IH

OPTION PRE/OE
AND
PRODUCT

•

~

INPUT

PRESENT STATE

NEXT STATE

OUTPUT

Unl

(PSI

(NSI

(ani

C C 1 1 1 1 1 1

LINE

OR

5 4 3 2 1 0 9L81716L514J3J211Jo 51413121110 51413121110 716151413121110

x - H H H H H H H]HIHIHIHIHIHIHIHIH HIH IHJH IH IH Ll LI LI LILIL LILILILILILJLJL

48
49

-

L L L L L L LJLJLJLJLILILILILJL LJLILILILIL HIHIHIHIHIH HIHIHIHIHIHIHIH

X

test array waveforms

r .....--..............................................................................................................~5V

At

VCC~

(I)

::r
CD
CD

___ _

-

....

-

(I)

-

H,I.________
-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-0

v

ILVIH

ClK

_ .........:....................................."""1

I+- tsu
......

/';'1-

-----':

VIL

_-+:. . . . . . .r=-=:::
/1i--.....

..

tpd~

!

-VOH

l- -I
_...Ilr~. . _
. . ._-_-~~:

~

-VOL

I

\J. .

REG:!~:~ ....._ _-JI

.

1...................................

.....- - - -...,

I

INTERNAL

I

I

~tpd

I+tpd+j

00-03

-+r- th~

!

1

10-19 ..........0+1..............._

STATE

-

I _ _ _ _.........._ _.....

test array deleted

IH

OPTION PRE/OE
AND
PRODUCT
LINE

48
49
X

2-226

C C 1 1 1 1 1 1

OR

INPUT

PRESENT STATE

NEXT STATE

OUTPUT

lin)

(PS)

(NS)

(an)

5 4 3 2 1 0 91817 6 51413121110 5 41312 110 5 4 312 1 0 7 6 5 4 13 21110
-1- - - - - - - 1- -1-1-1- - - - - - - 1- -1-1-

- - H H H H H H HIHIH H HI_HIHIHIHIH H HIHIH HIH - - X L L L L L L LJLIL L LILILILJLIL L LILIL LJL - -

= Fuse intact,

-

= Fuse blown

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TIB82S167BM. TIB82S167BC
14 x 48 x 6 FIELD·PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
TIB82S167B. 82S167A COMPARISON
The Texas Instruments TIB82S167B is a 14 x 48 x 6 Field-Programmable Logic Sequencer that is functionally
equivalent to the Signetics 82S167A. However, the TIB82S167B is designed for a maximum speed of 50 MHz
with the preset function being made conventional. As a result the TIB82S167B differs from the 82S167A in
speed and in the preset recovery function.
The TIB82S 167B is a high-speed version of the original 82S 167A. The TIB82S 167B features increased switching
speeds with no increase in power. The maximum operating frequency is increased from 20 MHz to 50 MHz
and does not decrease as more product terms are connected to each sum (OR) line. For instance, if all 48 product
tems were connected to a sum line on the original 82S167A, the f max would be about 15 MHz. The f max
for the TIB82S167B remains at 50 MHz regardless of the programmed configuration. In addition, the preset
recovery sequence was changed to a conventional recovery sequence, providing quicker clock recovery times.
This is explained in the following paragraphs.
The TIB82S167B and the 82S167A are equipped with power-up preset and asynchronous preset functions.
The power-up preset causes the registers to go high during power-up. The asynchronous preset inhibits clocking
and causes the registers to go high whenever the preset pin is taken high. After a power-up preset occurs,
the minimum setup time from power-up to the first clock pulse must be met in order to assure that clocking
is not inhibited. In a similar manner after an asynchronous preset, the preset input must return low (inactive)
for a given time, tsu, before clocking.
The Signetics 82S 167A was designed in such a way that after both power-up preset and asynchronous preset
it requires that a high-to-Iow clock transition occur before a clocking transition (low-to-high) will be recognized.
This is shown in Figure 1. The Texas Instruments TIB82S 167B does not require a high-to-Iow clock transition
before clocking can be resumed, it only requires that the preset be inactive 8 ns (preset inactive-state setup
time) before the clock rising edge. See Figure 2.

CO
...
CO

C

The TlB82S167B, with an f max of 50 MHz, is ideal for systems in which the state machine must run several
times faster than the system clock. It is recommended that the TlB82S167B be used in new designs. However,
if the n88251678 is used to replace the 825167A, then the customer must understand that clockIng wHI begin
with the first clock rising edge after preset.
TABLE 3. SPEED DIFFERENCES
PARAMETER
f max

tpd, eLK to Q

SIGNETICS

82S167A

TlB82S167B
TIONLY

20 MHz

50 MHz

20 ns

15 ns

TEXAS ",

INSIRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-227

TIB82S167BM. TIB82S167BC
14 x 48x 6 FIELD·PROGRAMMABLE LOGIC SEGUENCER
WITH 3·STATE OUTPUTS OR PRESET
Vee
PRE

-I':
I

I+-tsu --+/

jt--tsu-+j
I
I

I

I

r-1
---+I------rl-------------i,
I

elK

I

REGISTERS

:J

I

I

I

:

_____u

I
I

FIGURE 1. 82S167A PRESET RECOVERY OPERATION

Vee

.-I!

I
I

I

PRE

om

elK

tn
:r

REGISTERS

CD
CD

r+

o

2-228

I

I

r-1
:
, ~~-----------------­
,

r+

m

.....r-tsu

J

,'------'x'-__XJI

\'-_....IX"_____C

FIGURE 2. TIB82S167B PRESET RECOVERY OPERATION

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75285

TlCHAL 16L8·35C. TlCHAL 16R4·35C. TICHAL 16R6·35C. TICHAL 16R8·35C
HIGH·SPEED HAL® CIRCUITS
02972. MARCH 1

•

Mask·Programmed Version of 20-Pin PAL®
Family

•

Virtually Zero Standby Power

•

35-ns Maximum Propagation. Delay

TICHAL l6L8
C SUFFIX ... DW OR N PACKAGE
ITOPVIEW)

Vee

•

HC. HCT. and TTL Compatible

•

Choice of 20-Pin DIP. 20-Pin SO (Small
Outline) or 20-Pin PLCC Packages

•

Low-Power Replacement for 20-Pin •A'
PAL® Devices

•

Dependable Texas Instruments Quality and
Reliability
DEVICE

l-STATE

INPUTS
Q

'HAL16L8
'HALI6R4
'HALI6R6
'HALI6R8

10
8
8
8

OUTPUTS

2
0
0
0

I

GND

REGISTERED

1/0

OUTPUTS

PORTS

0

6

4 (l-statel

4

6 (l-statel

2
0

8 (J-statel

0
liD
liD
liD
liD
liD
liD
0

TICHAL16L8
C SUFFIX ... FN PACKAGE
ITOP VIEW)
U

u

_>0
3

2

1 20 19

18

description
These high-speed CMOS Hard Array Logic
(HAL®) circuits are mask-programmed versions
of the 20-pin PAL® devices. They provide
reliable, high-speed, low-power substitutes for
conventional TTL and HCT logic. They are also
compatible with HC logic over VCC range of 4.5
volts to 5.5 volts.

5

17

6

16

7

15

8'

14
9 1011 12 13

This family of CMOS HAL® circuits provide the flexibility of using integrated circuits with virtually zero
standby power and lower operating power than those currently achieved by bipolar PALs. Prototyping can
be done using standard PAL® devices before converting to CMOS HAL® circuits for production.
The TICHAL 16' circuits have internal electrostatic discharge (ESD) protection circuits and have been
classified with a 2000-volt ESD rating tested under MIL-STD-883B, Method 3015.1. However, care should
be exercised in handling these devices as exposure to ESD may result in a degradation of the device
parametric performance.
The C suffix designates commercial-temperature circuits that are characterized for operation from OoC
to 75°C.

PAL and HAL are registered trademarks of Monolithic Memories Inc.

PRODUCTION DATA docl..lnll ••nlli. info,ma'io.
••,nnt IS of publicetlo. dill. Products confonn '0
_lIcali... pa, the tar... of T.... Inat'.....11

='=il;"r.::::ri =::r :YI":::':~:'~

not

Copyright @ 1987, Texas Instruments Incorporated

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-229

TICHAL 16R4-35C. TlCHAl16R6·35C. TICHAl16R8·35C
HIGH·SPEED CMOS HAL® CIRCUITS
TICHAL16R4
C SUFFIX, , , OW OR N PACKAGE

TICHAL16R4
C SUFFIX, , , FN PACKAGE

(TOPVIEWI

ITOP VIEWI

eLK

tl 0
__ :1
u>::;;

Vee
I/O

1/0

2 1 2019

3

Q

4

18

110

Q

5

17
16

Q

Q

7

15

Q

I/O

8

14

Q

Q

1/0

E
C

AI
.....
AI

9 10111213

OE

GND

Q

-

~I~

gg

CI
TlCHAL16R6
C SUFFIX, , , OW OR N PACKAGE

TICHAL16R6
C SUFFIX, , "FN PACKAGE

(TOPVIEWI

ITOPVIEW)

eLK

tl 0
__ :1
u>::;;

Vee
I/O

en
:T

3

Q

...en
CD
CD

Q

18
17

Q

16

Q

Q

6
7

15

Q

Q

8

14

Q

Q
Q

110

Q

9 1011 1213

OE

GND

2 1 2019

4
5

-

~I~

gd

CI
TICHAL16R8
C SUFFIX, , , OW OR N PACKAGE

TICHAL16R8
C SUFFIX, , , FN PACKAGE

(TOP VIEWI

(TOPVIEWI

eLK

tl
__ :1
u>d

Vee
Q

3 2 1 20 19

Q
Q

18

Q

17

Q

16
15

Q
Q

14

Q

GND

2-230

9 10111213

OE

'TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

TlCHAl16l8·35C, TIC HAL 16R4·35C
HIGH·SPEED CMOS HAL® CIRCUITS
functional block diagrams (positive logic)
TlCHAL16L8
EN ,,1

&

'\lb-----O

32 X 64

P-----O

P-.-.......-I/O
b-4H--+",-1/0
b-4H--+"'- 1/0

-

P-4H-.......-1/0
IO-~....+--I/O

U)

;

P-4H-....+--1/0

CD

.c

en

6

CIS
CIS

~

TlCHAL16R4

C

OE

AEN2

CLK

.,
,,1

&
32

C1

x 64 -!,..

I-Q

-!,..
8

..J..!I..-

4

~

~

-

r----.
r----.
r----.

-!,..

c>

~

-

-:z....
-:z....

Q

2'\1
10

EN

,,1

'\I

-

,

Q

Q

1/0
1/0

..2,..

1/0

..2,..

1/0

4
4

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-231

I

!
!

TICHAL 16R6·35C, TICHAL 16R8·35C
HIGH·SPEED CMOS HAL® CIRCUITS
functional block diagrams (positive logic)
TICHAl16R6

CiE

~(N2

ClK

'" C1
32

"x

64

>1

..!.,..

2'\7

10

...!!..,..
~

--::::-I> -1!,..

----.
----.

...!!..,..

E

':.,.

o

....

Q)

p.!!,...

fI)

Q

Q

(1)
(1)

r+

EN

r----.

,,1

'\7

~

::r

....

1

1

2
6

fI)

Q

---..,

...!!..,..

r4

Q)

Q

---..,

~

-

Q

Q

..!.,..

,!.-

-

I/O
1/0

TICHAl16R8

OE------------------------dEr~__,
ClK

----------------P

r;;-..,....-~I_-Q
.----r----1-~-Q

t--;--""""1--':f-Q
r----t----1-~-Q
r----t----1-~-Q
.----t----1-~-Q
.----t----1-~-Q

.----r----1-~-Q

2-232

TEXAS

..If

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

TIC HAL 16L8·35C
HIGH·SPEED CMOS HAL® CIRCUITS
logic diagram (positive logic)
I

(1)

.

INPUT LINES
PRODUCT ,
LINES
0
0

4

8

12

16

20

24

28

31
r'

··
·
·
I~
··
··
··•
·
··
··

r-V-J
r-

7

8

I

f--"'"

1
v

(19)

0

(18) 1/0

t--

(3) 15
1'>L

r-V-J

16

f---

o

...
CIS

24

f---

V

J

CIS

(16)1/0

C

f---

(5) 31
X
32

••
•

I

CD
CD

.c

1(4)~

I

...
II)

(17)1/0

·
·
···•
·•
··
··•
••

1

-

v

(6) 39
X
40

(15)1/0

~

>---'

1

(14)1/0

V

I--

47
1(7) .:>L

I--

48

I--

1
v

(13)1/0

55
I (8) X
56

I

f--

1

0

(12)

v

(11)

(9) 63
X

I

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

2-233

TICHAL 16R4·35C
HIGH·SPEED CMOS HAL® CIRCUITS
logic diagram (positive logic)
CLK.i!lt>

.

INPUT LINES
PRODUCT ,
LINES
0
0

4

8

12

16

20

24

28

31

·••••
·

V

~

"'8
•••
•

I

,

1

7

I (21"

(191 110

1

.--

·
··••
·
··••
·
·••
·

(181 1/0

v

J

(31 15

16

~

.--/A

f..-

>f..-

~

l.:J.
(151Q
-v""'

~~Q

R
(14)Q
1?'""

I---'D)--

I----'

C1

(6) 39

I---'

40

•••
•

I

··

_

••
•
•

1

-'

··
··•
·•

(13) 110

V

J

-

55

~

56

1

~

I---

v

9) 63
I (
::>L

2·234

C1

(7 47
I
"'48

IJ!)

Q

(161Q

f----I

32

I

'"..."J

C1

(51 31
I

Q~Q
C1

(41 23
I
'"
24

~"

TEXAS . "

INSTRUMENTS
POST OFFICE BOX

65501~

• DALLAS, TEXAS 75265

.....

(12) 1/0

J
~)OE

TlCHAL 16R6·35C
HIGH·SPEED CMOS HAL® CIRCUITS
logic diagram (positive logic)

CLK~-------------------------INPUT LINES
PRODUCT ,
LINES
0
0

4

8

12

16

20

24

28

··
·
'8
·••
··

31
~

~

1(2),,~

>----c

-

'

~>-

(19) 1/0

I
tJ;:CW'' .

I..

Cl

(3) 15
I~

J

16

•••
•
•

>---,>-

·

f----'

24

>---,

••
•
•

tJ;

i.:l

tJ;
tJ;

i.J

(17) Q

CD
CD

"

.c

..

Cl

(4) 23

I~

U)

as
as

>----.

·

:>-

C

(16) Q

"

Cl

(5) 31
I

32

••

··•
..·•
··
·••
·•

~P>---

(6) 39

I

U)

~

~15)Q

Cl

'-'

40

1(7)

p--

47

Cl

f-----1

48

I (8)

tJ;

~14)Q

~~hl -v
:J

(13) Q

Cl

55

,.....

56

•

·•••
·

~

L/

~

(12) 1/0

~L4'I-

(9) 63

I~-

OE

TEXAS ~

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-235

TICHAL16R8·35C
HIGH·SPEED CMOS HAL@ CIRCUITS
logic diagram (positive logic)
ClK (1)

.L!Lf>

P

.

I

INPUT LINES

Rl~~E~CT '0

4

8

12

16

20

24

28

··•
·
0

31
f----'
f---;

f-t>-

··
·
··••
·
··•••
·

f-p~

16

~

'"";:l

(18)

t1
tl

'"";:l

(17)

R

(16)

r---.

~D>---'

x

f---'

f----'p-

v

A

-

32

••
••

·

f----'
f----'

)-

v

Q

fbJ;

'"";:l

(15)

v

Q

C1

(6) 39
~

40

··..••

~

)~

48

••
••
••
55

f----'

-)-

~

'"";:l

(13)

v

56

')-~ ';)v ""

- ,.....

C1

(9 63

I

TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

Q

C1

-

.-••
·••

~

R(14}
Q
v

C1

).----,

(7)~

2-236

Q

C1

(5) 31

I~.

Q

C1

(4) 23

24

v

C1

f----'

(3) 15

I (8)

Q

C1

Elrl:'8

•

fbJ; ? ""

~)

Q

TlCHAL 16L8·35C. TIC HAL 16R4·35C. TICHAL 16R6·35C. TlCHAL 16R8·35C
HIGH·SPEED CMOS HAL@ CIRCUITS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage range, VCC ........................................... -0.5 V to 7 V
Input voltage range, VI ........................................ -0.5 V to VCC+0.5 V
Input clamp current, 11K (VI < 0 or VI > Vcc) ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ±20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±35 mA
Continuous current through VCC pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 mA
Continuous current through GND pin ................................... , . . .. - 200 mA
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .............. :'. . . . . .. 260 0 C
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 75 °C
Storage temperature range ......................................... - 65 °C to 150 0 C

recommended operating conditions
C-SUFFIX
MIN

4.5
2

VCC

Supply voltage

VIH

High·level input voltage

VIL

Low·level input voltage

tw

Pulse duration

tsu
th

Setup time, input or feedback before CLKt

TA

Operating free-air temperature range

NOM

MAX

5.5

Clock high
Clock low

Hold time, input or feedback after CLKt

20
20
30
0
0

V
V

0.8

I
I

UNIT

V
ns
ns
ns

75

·C

II
...
U)

CD
CD

.c

CI)

...

CG
CG

Q

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265

2-237

TICHAL 16L8·35C, TlCHAL 16R4-35C, TICHAL 16R6·35C, TICHAL 16R8·35C
HIGH·SPEED CMOS HAL® CIRCUITS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER

IIH
III

High-level output voltage
lOW-level output voltage
Off-state output current with
high-level voltage applied
Off-state output current with
low-level voltage applied
High-level input current
low-level input current

lee

Standby supply current

lec

Operating supply current

VOH
VOL
10ZH
10Zl

c
I

= 4.5 V,
= 4.5 V,

10H
10l

Vee = 6.5 V,
Vee

= 5.5 V.
= 6.5 V.
= 5.6 V.

Vo

= -6 mA
= 24 mA

C-SUFFIX
TYP . MAX

=0

VI = Vee
VI - 0
VI = o or Vee.

Vee = 5.5 V•
Other inputs at 0 'or Vee
TA = 26·e.
TA = 25·e.

MIN
3.76

Vo = Vee

Vee
Vee
Vee" 5.5 V.
10 = 0
Vee = 5.5 V.
f." 1 MHz.

Input capacitance
Output capacitance

ei
eo

~

..

Vee
Vee

..1lee* ehange In supply currant

!
:

TEST CONDITIONS

VI = o or Vee.
10 = 0
VI = 0.6 V or 2.4 V.

0.4

V
V·

10

p.A

-10

~A

1
-1

p.A
p.A

100

p.A

2
1.4

f = 1 MHz
f = 1 MHz

UNIT

mA/MHz
3

mA

10
10

pF
pF

-

switching characteristics over recommended renges of supply voltage and operating free-air temperature
(unless otherwise noted)

en

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)
with feedback
without feedback
o or I/O

fmax§
tpd
tpd

I. I/O. or feedback
elKt

0

DE.
DEt

0

tdis
ten
ldis

I or I/O
lor I/O

Oorl/O
o or I/O

ten

TEST CONDITIONS

R1 = 200
R2= 390

MIN
18
25

n.
n.

eL=50pF

0

C-SUFFIX
TYP
MAX

MHz
18
10

36
25

ns
ns

12

25

ns

12
14
16

25
36
36

ns
ns·
ns

t All typical values are Vee = 5 V. TA = 25 ·e.
*This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 or Vee.
§fmax (with feedback) =

2-238

tsu

1
elK

+ tpd (

to

0); fmax (without feedback) =

(h' h)
tw.g

1

()

+ tw low

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 855012 • OAUAS. TEXAS 75265

UNIT

TICHAL 16L8·35C. TICHAL 16R4·35C. TIC HAL 16R6·35C. TICHAL 16R8·35C
HIGH·SPEED .CMOS HAL® CIRCUITS

PARAMETER MEASUREMENT INFORMATION

Vcc
Sl

~

Rl
FROM OUTPUT _
UNDER TEST

...._~___- ........ TEST
POINT
R2

CL
(See Note Al

PI
...

NOTES: A. CL = includes probe and jig capacitance.
B. When measuring propagation times of 3-state outputs, 51 is closed.

U)

FIGURE 1. LOAD CIRCUIT FOR THREE-STATE OUTPUTS

CI)
CI)

INPUT~1.5V

\:~~-- - - - - - 3 v
tpd - tpLH or tpHL

I

IN-PHASE
OUTPUT

OUT ·OF-PHASE
OUTPUT

I'

OV

r+--tPLH--+I

I+--tPHL----"!

I

I

:

I
Y,.5V

\~;V--VOH

I

I

I+--tPHL---+t

k---tPLH----"!

-

I

I

' - _ _ _ _ _ _ _ _ _ _ _J

tJ)

...
(CI
(CI

I

l

.c::
Q

VOL

VOH
1.5 V
- - - - VOL

VOLTAGE WAVEFORMS
NOTES:

A. When measuring propagation times of 3-state outputs, S 1 is closed.
B. All input pulses are supplied by generators having the following characteristics: PRR

.s:

1 MHz, Zo :::: 50 fl, tr == 6 ns.

FIGURE 2. PROPAGATION DELAY TIMES. OUTPUT RISE AND FALL TIMES

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-239

TlCHAL 16LB·35C, TIC HAL 16R4·35C, TICHAL 16R6·35C, TlCHAL 16RB·35C
HIGH·SPEEDCMOS HAL® CIRCUITS
PARAMETER MEASUREMENT INFORMATION

\"----3V

f.5V

CLK

'-,---ov

~I.~-------th'------___·~I

.d:'"'~--------~~N'--J+--tsu --'!

DATA
INPUT

I

1.5 V
0.3 V

I

2.7 V

2.7 V

I
I
I

I
I

I

~~~

I

.

---3 V

1.5 V
0.3 V

ov

~q~
VOLTAGE WAVEFORMS

E

NOTE:

Phase relationship between waveforms was chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR s 1 MHz, Zo = tr = 6 ns, tf = 6 ns.

FIGURE 3, SETUP AND HOLD TIMES. AND INPUT RISE AND FALL TIMES

~:

DE },,1_.5_V_ _ _ _ _ _ _ _ _ _J (

14-- tPLZ--.!

!4---tPZL ~
OUTPUT
WAVEFORM 1
Sl CLOSED
(See Note B)

I

I

!

_ _ _ _ _ _ _ _ : :V

I

\1.5V

:,

I

Y-f~'~V

~VCC

_ _ VOL

I+---- tPZH---.I

f

OUTPUT
:
WAV.EFORM 2
S1 OPEN
1.5 V
(See Note B) _ _ _ _ _ _ _....J.

:

I.
I

...i - - - -

"t-"
!'-,·t:-O.5 V
I

VOH

"'----- =0 V

14-- tPHZ---+l
tan - tpZL

0'

tpZH
VOLTAGE WAVEFORMS

NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR s 1 MHz, Zo = 50 II, tr = 6 ns, tf = 6 ns.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditi~ns such that the output is high except when disabled by the output control.

FIGURE 4. ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS

2-240

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

TICHAL 16L8·35C, TlCHAL 16R4·35C, TICHAL 16R6·35C, TICHAL 16R8·35C
HIGH·SPEED CMOS HAL® CIRCUITS
PARAMETER MEASUREMENT INFORMATION

X5~ - ---::

HI~~-~:~EL ____.,!'.5 V

~14~----tw------~~~
1OI14~----tw------""'1

I

LOW-LEVEL
PULSE

I

\.5V

3 V

'-5~ ____ OV

VOLTAGE WAVEFORMS
NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR :::; 1 MHz, Zo = 50 0, tr = 6 ns.
B. For clock inputs, f max is measured with input duty cycle = 50%,

FIGURE 5. PULSE DURATIONS

...
U)

CD
CD

.c
tn

...caca

C

.

TEXAS'"

INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265

2-241

E

2-242

TlCPAl16l8·55C, TlCPAl16R4·55C
TlCPAl16R6·55C, TICPAl16R8·55C
STANDARD CMOS PAl@ CIRCUITS
03062, NOVEMBER, 1987

TICPAL l6LS'
C SUFFIX ••• JL OR N PACKAGE
ITOPVIEWI

•

Standard 20-Pin PAL Family

•

Virtually Zero Standby Power

•

Propagation Delay ... 55 ns Max

•

TTL- and HC-Compatlble Inputs and Outputs

•

Preload Capability to Aid Testing

•

Fully Tested ,for High Programming Yield
Before Packaging

•

Greater than 2000-V Input Protection for
Electrostatic Discharge

•

Devices In the' JL' Package Can Be Erased
and Reprogrammed More Than Once

Vee

o

110
1/0
110
110
110
110

o

I

GND ......_ _....
TlCPAl16R4'
C SUFFIX ... JL OR N PACKAGE
ITOPVIEWI

elK
DEVICE

INPUTS

PALt6L8

to

PAL16R4
PALt6R6

B
B

PAL16RB

B

3-STATE

REGISTERED
I/O
o OUTPUTS QOUTPUTS PORTS

2
00
0

0
413-state)
6 (3-statel
B 13-statel

I

Vee

I

1/0
110

U)

iCD
.c
en

Q

6
4

Q
Q

2
0

Q

110
110
......___ OE

as
as

~

description

Q

TICPAL16R6'
C SUFFIX •.. JL OR N PACKAGE

These PAL devices ptovide reliable, highperformance substitutes for conventional TTL
and HCT logic. They are also compatible with HC
logic over the Vec range of 4.75 V to 5.25 V.
Their easy programmability allows for quick
design of "custom" functions and typically
result in a more compact circuit board. Static
power dissipation for these devices is negligible.

ITOPVIEWI

elK

Vee
1/0
Q
Q
Q

Q
Q

The output registers of these devices are Ootype
flip-flops that store data on the low-to-high
transition of the clock input. The registered
outputs may be disabled by taking OE high,
whereas the nonregistered outputs may be
disabled through the use of individual product
terms. Unused inputs must always be connected
to an appropriate logic level, preferably either
VCC or ground.

Q

110

OE
TICPAL16RS'
C SUFFIX ... JL OR N PACKAGE
(TOPVIEWI

elK

Vec
Q
Q
Q
Q

Q
Q

Q
I
Q
GND ......_ _rOE

The dotted circles represent windows found only on the JL package.
PAL" is a registered trademark of Monolithic Memories Inc.

PRODucnOI OATA d..om.." .ontain inmmotian

cu"",t II of po..looti•• dote. Pradocts coof.,m to
_Iflooti... par the to,... of TUII lnotro..
m.d.rd w."alltY. P,oductl•• " ....1•• d... oot

on"

n.....rily

io~odl

tastln. of III plllmotan.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DAUAS, TeXAS 75265

Copyright @ 1987. Texas Instruments Incorporated

2-243

TICPAl16l8-55C, TICPAl16R4-55C
TICPAl16R6-55C, TlCPAl16R8-55C
STANDARD CMOS PAl®CIRCUITS
description (continued)
The programming cell consists of a floating-gate device like those used in EPROMs. All terms are initially
connected. The unwanted terms are programmed out to provide the desired function. The output of a
given AND gate is low if both the true and complement cells of a term are connected, and high if all related
cells are programmed. Programming can be done manually but is usually achieved through the use of
commercially available programming equipment.
This TICPAl 16' series has internal electrostatic discharge (ESD) protection circuits and has been classified
with a 2000-V ESD rating tested under Mll-STD-883B, Method 3015.1. However, care should be exercised
in handling these devices, as exposure to ESD may result in a degradation of the device parametric
performance.
The floating gate programmable cells allow these PAls to be fully programmed and tested before assembly
to assure high field programming yield and functionality. They are then erased by ultraviolet light before
packaging.
All devices in this series contain a security feature. Once the security cell is programmed, additional
programming and verification cannot be performed. This prevents easy duplication of a design.

...c
C»
C»

The TICPAL16'C series is characterized for operation from OOC to 75°C.

erasure

tn

::::r

...

CD
CD

(I)

2-244

The TICPAl16' (Jl package) series can be erased after programming by exposure to ultraviolet light that
has a wavelength of 253.7 nm (2537 A). The recommended minimum exposure dose (UV intensity x
exposure time) is fifteen w.s.cm - 2. The lamp should be located about 2.5 cm (1 inch) above the chip
during erasure. It should be noted that normal ambient light contains the correct wavelength for erasure .
Therefore, when using the nCPAl 16' series (Jl package). the window should be covered with an opaque
label.

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALlAS. TEXAS 76265

TICPAl16lB·55C, TlCPAl16R4·55C
STANDARD CMOS PAl@ CIRCUITS
functional block diagrams (positive logic)
TlCPAl16lS'
EN 201

8<
32 X 64

"illo----o

10----0

p...~~~1/0

b--.+.........-I/O
b-~~~I/O

...us

Io-H-~~I/O

CD
CD

.c
fn

6

...caca

TICPAl16R4'

Q
J EN2

OE

, C1

ClK
8<
32 x 64

201

-.!!,..

2"il
10

Q

-.!!,..
8

~

4

~

----

---..,
Q

~

"'"'1>

~

---..,

~

-

Q

-

Q

---..,
EN

201

--2.,..

"il

-

--2.,..

"

110
110

-

1/0

-

1/0

--2.,..
--2.,..
4
4

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265

2·245

·TICPAl 16R6·55C, TlCPAl16R8·55C
STANDARD CMOS PAl® CIRCUITS
functional block diagrams (positive logic)
TICPAl16R6

OE

-tN2

ClK

L,
&

32 X 64

C1

,,1

~

10

E
c
C»

....C»
·0

:sCD

!en

~

I>

~

,...!.,&

~

~
~

r----.
r----.
r----.
r----.
r----.

rJ!+
rJ!+
r-!+
~
~

~

Q

r-Q

~
~

2'V

EN

",
'V

G+
r+

Q
Q
Q
Q

110
110

2
6

T1CPAl16R8

OE----~------------------dEr~__,
ClK -------------~~

r;;-.,...-~I_-Q

r---r-""--"':f--Q
r----t----1-~-Q
r----t----1-~-Q

t--T---1-+--

Q

r----t----1-~-Q
r----t----1-~-Q
8

2·246

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 866012 • DALLAS. TEXAS 75285

II"rftL lULU· .... "

STANDARD CMOS PAL® CIRCUITS
logic diagram (positive logic)
1(1 )
INPUT LINES

P RODUCT •
LINES
0
0

·.···
'8
···
···
··
·
··•
·
··
:-

(2),,-~_

4

12

8

16

20

24

28

-

31

~:l
r-

(19)

v

o

-

k

r- f--"

1

(18)

v

110

-

(3) 15

.A

16

r-

-

~

~

-

:--'

1

I•
CI

(17)

110

G
G

~

~

(4) 23

U

24

•
c:

x

(5)

(1

r-

r- V
r-

~

32

r- -..,.

J

(16)

1

(15)

1

(14)

(1

v

110

110

)----,

(6) 39

X

40

i)..

110

-

(7) -;:

··
·
··
·
~48

~p-J

55
(8)"

--

56

~J
--

--

r - I--"

-

+-=:kI
r-

63

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

(13)

-1

(12)

v

110

o

(11 )

2-247

TICPAL 16R4·55C
STANDAilD CMOS PAL@> CIRCUITS
logic diagram (positive logic)

ClK~.

,

.

INPUT LINES
PRODUCT ,
LINES
0
0

··•
·

4

8

12

16

20

24

28

31

J

.

I~
'8

••
••
••

J

>--

V

;>l

16

••
••
•

r---<

·

I---c

>-

.~

·

>

-

>--

I

'"

32

·•••

~pt-;.-

Ir-

40

1(7)

.bJi

:>~

··
··•
·•

)----

47

(16) 0

I.:lv

(15)0

r.:J.v

(14)0

~

Cl

J<

48

J

>---'

~

55
I (8) ;>l

(13) 1/0

~J
1

~

56

••
•••

h

1-/

·

}--

63

I~.

2-248

fb1

r.:J

Cl

(6) 39

1

••
•
•

Q

Cl

. (5) 31

••

.bJi f3 ""
Cl

(4) 23
1'-'-"
24

•••
••

(18) 1/0

1

(3) 15
I

(19) 110

~ 1

v

(12) 1/0

1
~)OE

TEXAS ."

INSTRUMENTS
POST OFFICE

aox 65~12

, CALLAS. TEXAS 15285

TlCPAl16R6·SSC
STANDARD CMOS PAl@ CIRCUITS
logic diagram (positive logic)
CLK~~--------------------------- _______

----------,

INPUT LINES
PRODUCT,~--------------------~------------------~

LINES

0

4

8

0--+-+++-++++-

I

·•
··
··
·

12

---

16

20

24

28
-f-- -

31
I---

J
~

I
I

f--

(31 15

>f-fol-'3
~

~

(181 Q

i
til
...caca

.c

C

--s-- -1-t,;]

56

••

··

j

V

~==t<}----

(91 63

I~_-

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

(121 1/0

I /1-(111~OE

2-249

I
I

i

!
!

TICPAL16RS·55C
STANDARD CMOS pAL® CIRCUITS
logic diagram (positive logic)
ClK~~--------------~----~--~--____
INPUT LINES

PRODUCT ,
0
LINES
0

4

8

12

16

20

0
0
0
0
0
0

IEl .....

24

28

~
.-

Z--

C1

~

}---J ....

I-

0
0
0
0
0
0

1~
1FI-~

(3) 15

'-'

I
16

'--

0
0

~

~

~

I;:L

I--

•

--D-

o
0
0

I

tJ;? "".

~

'8

E

31

'--

(4) 23
.;>L

I--

24
0
0
0
0
0
0

C1

-- ~
....

·•
··
··•
·
···
·
··
·

~
1-

t>

1-

40

-~
F-

-

C1

>---

48--

'=>fbJ;

--

.

55

v

(13) 0

VI

...r-'
I- ~~ >~ ';! "".
~
~
C1

63

2-250

>-;:L

C1

I--

56

I~

~

~14)0

(15) 0

}-

1(7) 47

J!)

~

':lv

C1

(6) 39

I

:;::l..,I1.~)
0
....

C1

~

. 32

I

(17) 0

I?'"

C1

I--D-

31
I (5)x

(18)0

I ~

I

I

I

I

TEXAS ."

INSTRUMENlS
POST OFFI,CE BOX 655012 • DALLAS, TEXAS 75265

~)OE

TICPAL 16LB·55C, TICPAL 16R4·55C
TICPAL 16R6·55C, TICPAL 16RB·55C
StANDARD CMOS PAL® CIRCUITS
absolute maximum ratings over operating free·air temperature range (unless otherwise notedl
Supply voltage range, Vec ........................................... :....0.5 V to 7 V
Input voltage range, V, ........................................ -0.5 V to VCC +0.5 V
Input clamp current, 11K (V, -!:. 0 or V, > VCCl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (VO < 0 or Vo > VCCl ............................. ± 20 mA
Continuous output current, 10 (VO = 0 to Vecl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through Vec pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 mA
Continuous current through GND pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 200 mA
Operating free-air temperature range ...................................... OOC to 75°C
Storage temperature range ......................................... - 65 °e to 150°C
Lead temperature 1,6 mm (1/16 inchl from case for 60 seconds (JL packagel ........... 300 0 e
Lead temperature 1,6 mm (1/16 inchl from case for 10 seconds (N packagel ............ 260 0 e

recommended operating conditions
C-SUFFIX
MIN
4.75

VCC Supply voltage
VIH High-level input voltage
Vil low-level input voltage

NOM

MAX
5.25

V
V

0.8

V

2

I Clock high

tw

Pulse duration

tsu
th
TA

Setup time, input or feedback before ClK I

I

Clock low

Hold time, input or feedback after ClK I
Operating free-air temperature range

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 .. DALLAS. TEXAS 75265

20
20
40
0
0

UNIT

75

...
U)

Q)
Q)

ns

.c

ns
ns
·C

...caca

tJ)

C

TICPAl16l8·55C, TlCPAl16R4-55C
TlCPAl16R6·55C, TICPAl16R8·55C
STANDARD CMOS PAL@) CIRCUITS
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER

TEST CONDITIONS
10H = 3.2 rnA Ilor TTL)
10H = -4 mA 110' CMOS)
10l = 24 mA 110' TTL)
10l = 4 mA 110' CMOS)
Vo = 2.4 V
Vo = 0.4 V

10ZH
10Zl
IIH
III
leelstandbvl
leelope,ating)
I

Vee = 4.75 V,
Vee = 4.75 V,
Vee - 4.75 V,
vee = 4.75 V,
Vee = 5.25 V,
Vee = 6.26 V,
Vee = 5.25 V,
Vee - 5.25 V,
Vee = 5.25 V,
Vee = 5.25 V,
I = 1 MHz to 25 MHz

* 4l ee

VI - 0.5 Vo, 2.4 V,
Vee 5.25 V,
Othe, inputs at 0 V 0' Vee

VOH
VOL

= Vee
= 0
= 00' Vee,
= Oto Vee,

10 = 0
10 = 0,

Tvpt

MAX

UNIT
V
V

10
-10
10
-10
100

p.A
p.A
p.A
p.A
p.A
mA
MHz

3

mA

2
1.4

1- 1 MHz

TA = 25°C,

el

VI
VI
VI
VI

MIN
4
3.86
0.5
0.4

pi

6

C
r»

switching characteristics over recommended ranges of supply voltage and operating free-air temperature
;- (unless otherwise noted) R1 - 200 (}, R2 - 390 (},. CL - 50 pf

tn

PARAMETER

::T
CD

!

FROM
(INPUT)

elKt

TO
IOUTPUT)
. with leedback
wlo leedback
00,1/0
a

m.

a

15

25

ns

a
ao, I/O
ao, I/O

15
35
35

25
55
55

ns
ns
ns

Imax§
tad
tod
tan
ldis
tan
ldis

I, I/O;

0' leedback
~t

10,1/0
10,1/0

MIN

TYpt

MAX

35
15

55
22

ns
ns

16
25

MHz

tAli typical values are at Vee = 5 V, TA = 25°C.
*This Is the inc,ease in supply cu,rent 10' each input that is at one 01 the specilied TTL voltage levels ,athe, than 0 0' Vee.
§Imaxlwith leedback) =

2-252

2-

1
; Imaxlwithout leedback) =
tsu + tpd lelK to aJ
.
tsu

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 855012 • DALlAS. TEXAS 75286

UNIT

TICPAl16lB·55C, TlCPAl16R4·55C
TlCPAl16R6·55C, TICPAl16RB·55C
STANDARD CMOS PAl® CIRCUITS
preload procedure for registered outputs
The output registers can be preloaded to any desired state during device testing. This permits any state
to be tested without having to step through the entire state-machine sequence. All of the registers may
be preloaded simultaneously by following the steps below.
Step 1.

With Vee at 5 V and Pin 11 at VIH. raise Pin 1 to VIHH.

Step 2.

Apply either VIL or VIH to the output corresponding to the register to be preloaded.

Step 3.

Lower Pin 1 to VIL. then remove the output voltage. Preload can be verified by lowering Pin 11
to VIL and observing the voltage level at the output pins.

preload waveforms

\'-------v II
...

""~
---.I
PINS

2·9

td

w

I+-

,

, ,

~

'L

!

I

'I

"

-, :-'--------------I - - - ,,

~td~
,

I
-------tpreload _ 11'0 _ _ _ _...:

,

I

I

,

Q)
Q)

.s:.
fn

...asas

VIH

VIL

C

~tdr-l

,

l :. .

PIN 11

U)

\..-----VIL

I

I

I

~

,

,

- : - - VIH
I
VIL

---+j td j4-

IVIH-',.---------------}-C
'I
I , VOH

REGISTERED 1/0

----J~VIL-'-

~

VOL

preload parameters, TA - 25°C
PARAMETERt
VIHH
IIHH
Av/At
td

Preload voltage on pin 1
Preload input current at pin 1

Voltage ramping (VIHH)
Setup and hold times

MIN
12.5

NOM
13

MAX
13.5

UNIT
V

3.2

4

4.8

mA
VI,..

50

2

,..

tOther test parameters and conditions are shown in recommended operating conditions and electrical characteristics tables.

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75285

2-253

TlCPAlI6L8·55C, TlCPAlI6R4·SSC
TlCPAlI6R6·SSC, TlCPAl16R8·SSC
STANDARD CMOS PAl® CIRCUITS

•

PARAMETER MEASUREMENT INFORMATION

Vee
.~

S1

R1
fROM OUTPUT -~-~_---41>-- TEST
UNDER TEST
POINT

R2

NOTES: A. Cl =- includes probe and jig capacitance.

•

S. When measuring propagation times of 3~state outputs, S1 is closed.

FIGURE 1. LOAD CIRCUIT FOR THREE-STATE OUTPUTS

C
CD

at

INPUT

en
::T
CD

!en

L

--Ii,I

'.5V

\.,'; : : - - - - - - - 3 V
tpd - tpLH or tpHL

(+--tPLH-+/

I
IN-PHASE
OUTPUT

:

I

0 V

I+--tPHL~

,.-----~I-----d --- -

Y,.5V

I '

I,

VOH

\1.5V
VOL

I+--tPLH~

I+--tPHL--+f
OUT-Of-PHASE
OUTPUT

.1\
,

,

\1.5V
•

I'r---

VOH

1.5V

----VOL

VOLTAGE WAVEfORMS
NOTES:

A. When measuring propagation times of 3-state outputs, 51 is closed.
B. All input pulses are supplied by generators having the following characteristics: PRR :S 1 MHz, Zo = 50 0, tr = 6 ns.

FIGURE 2. PROPAGATION DELAY TIMES, OUTPUT RISE AND FALL TIMES

2-254

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75266

TlCPAl16L8·55C, TICPAl16R4·55C
TlCPAl16R6·55C, TlCPAl16R8·55C
STANDARD CMOS PAl® CIRCUITS
PARAMETER MEASUREMENT INFORMA nON

f.5V

ClK

!w
a:

0..
t-

O

:::»

Q

o

g:

EPIC is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories Inc.

PRODUCT PREVIEW do.umlats ...tai. inform.llon
on products In tho formlli•• or dosigl ,bul a'
d•••lopm.nt. Cblra.leriolic dltl .n~ olh.r

=~:~::srrg':t d:I::,:::I~rT:.::~~::~::
products without noti...

Copyright @ 1987. Texas Instruments Incorporated

TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-257

TlePAl18V8-30M, TICPAl18V8-25C
ADVANCED EPICTM CMOS GENERIC PAL®
description (continued)
architecture
The 'PAL 18V8 architecture is a generic version of the 20-pin family of PAls. This generic flexibility is
achieved by the implementation of each output function with an Output logic Macrocell (OlM). The OlM
contains architectural options configured through programming. These options include the user selection
of combinatorial or registered outputs with a choice of active-high or active-low logic.
The 'PAL 18V8 has 74 product terms in the AND array, 64 of which are OR-function product terms, 8
product terms that are used as bidirectional output controls, and 1 product term each as asynchronous
reset and synchronous set control, respectively. Each of the 8 outputs has 8 product terms per OR functiori
and a dedicated product term for the bidirectional control of that output. The bidirectional control allows
for individual outputs to be forced into the high-impedance state for bidirectional operations or for dedicated
input usage.

Cit

The circuit design is enhanced by the addition of synchronous set and asynchronous reset product terms.
These two functions are common to all the OlMs. When the synchronous set product term is a logic 1,
the output registers are loaded with a logic 1 on the next low-to-hi,gh clock transition. When the
asynchronous reset product term is a logic 1, the output registers are loaded with a logic 0 independently
of the clock. The output logic level after set or reset depends on the polarity selected during programming.
An asynchronous reset always overrides synchronous set .

CI)
CI)

. A clock function is routed to all the OlMs. It is used with the registered macrocell options. The clock function
shares a pin with an array input. The sharing provides an additional input pin when registered options are
not exercised.

o

Q)

en
:::r

....en

The registers in the' 18V8 have been designed to reset after power-up. During power-up, all registers will
reset to the O-state following a transition of any input or any I/O. The output voltage level for any output
will depend on the polarity selected for that output. This feature is especially valuable in Simplifying state
machine initialization.
All output registers can be preloaded to any desired state during testing. Preloading permits full logical
verification during device testing.
The TICPAl 18V8 has internal electrostatic discharge (ESD) protection circuits and has been classified with
a 2000-V ESD rating tested under Mll-STD-883B, Method 3015.1. However, care should be exercised
in handling these devices, as exposure to ESD may result in a degradation of the device parametric
performance.
The floating gate programmable cells allow these PAls to be fully programmed and tested before assembly
to assure high field programming yield and functionality. They are then erased by ultraviolet light before
packaging.

"'0
:D

The M-suffix devices are characterized for operation over the full military temperature range of - 55°C
to 125°C. The C-suffix devices are characterized for operation from OOC to 75°C.

o
C

c:

design security

(')

-4
."
:D

m

<

m

The 'PAL 18V8 contains a programmable design security bit. Programming this bit will disable the read
verify and programming circuitry, protecting the design from being copied. The security bit is usually
programmed after the design is finalized and released to production. A secured device will verify as if every
location in the device is programmed. Because programming is accomplished by storing an invisible charge
instead of opening a metal link, the '18V8 cannot be copied by visual inspection. Once a secured device
is fully erased, it can be reprogrammed to any desired configuration.

:e

2-258

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TlCPAl18V8·30M, TICPAl18V8·25C
ADVANCED EPICTM CMOS GENERIC PAL®

functional block diagram (positive logic)

~

C,

.

SET
'S
R

RESET

36x74

8

..,

,......,

-

n

~ ......

ClKII ...0 ....

r

8

I>

r
I>

."

OUTPUT
LOGIC
MACROCELL ~

r

EN

h

V-

EN

8

r
V-

h

V-

EN

8

V-

h

V-

EN

,......,

r

EN

h

1/0/0

1/0/0

1/0/0

II
U)

h

~

~

~ ......

-

8

h

V-

r

,......,

r

EN

8

r

,......,

r

EN

8

h

V-

EN

,......,
,......,

r

~

1/0/0

en

CI)
CI)

.r::

8

h

1/010

as
as

~

1/010

Q

1/0/0

1/0/0

8
8

8

__ denotes fused inputs

~
W

:;
w
a..

a:

le.,)
;:)

o
oa:

a..

TEXAS . "

INSIRUMENlS
POST OFFICE BOX 656012 • DALLAS. TeXAS 75286

2-259

TICPAl18V8·30M, TlCPAl18V8·25C
. ADVANCED EPICTM CMOS GENERIC PAL®

logic diagram (positive logic)
cu1'7

~ ~tT

....
en
::r

/4128

CD
CD

~ ~tT

U)

(51 311

~ ~tT

44

.

~

",53

""C

::a

54

o

~

C

c:

n
-I

(II"

.

""C

m
m

(11

Tr

~tT

1/0/0

Tr

~tT

~~tT

71

:r,-

=E

2-260

1/0/0

1/0/0

Tr

::a

<
-

1/0/0

Tr

311

181

1/0/0

Tr

27

....

1/0/0

1T

,.

C

I»
I»

'=tT

1/0/0

(111

TEXAS ."

INSlRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

1/0/0

TICPAl1 BVB-30M, TlCPAl1 BVB-25C
ADVANCED EPICTM CMOS GENERIC PAl@

output logic macrocell (OlM) description
A great amount of architectural flexibility is provided by the user-configurable macrocell output options.
The macrocell consists of a Ootype flip-flop and two select multiplexers. The Ootype flip-flop operates like
a standard TTL Ootype flip-flop. The input data is latched on the low-to-high transition of the clock input.
The Q and Q outputs are made available to the output select multiplexer. The asynchronous reset and
synchronous set controls are available in all flip-flops.
The select multiplexers are controlled by programmable bits. The combination of these programmable bits
will determine which macrocell functions are implemented. It is this user control of the architectural structure
that provides the generic flexibility of this device.

output logic macrocell diagram

r----------,
OUTPUT LOGIC MACROCELL

,

MUX

I

AR

R

1-0

>---+-~--~1D

Q~--------_i

r-...:.....----~I>Cl

55

:

Q

0

1S

1 \ G0

O

FROM CLOCK BUFFER
MUX

3

I

II
...
en
CD
CD

'I

..c

I
I
I
I

...caca

en
C

I
I

G1

,
I

I
I

AR _ asynchronous reset

E -::hrc:::se_t_

__-1

~
w

5>
w

a:

0.
I-

o

:::::>
Q

oa:

0.

TEXAS

~

INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2-261

TICPAL 18V8·30M, TICPAL 18V8·25C
ADVANCED EPIC"" CMOS GENERIC PAL®
output logic macrocell options
MACROCEU FEEDBACK AND OUTPUT FUNCTION TABLE
CELL SELECT
SI

SO

0
0
1
1

0
1
0
1

FEEDBACK AND OUTPUT CONFIGURATION
,Register feedback Registered

Active low

Register feedback Registered

Active high

I/O feedback
I/O feedback

Combinational Active low
Combinational Active 'high

o=

erased cell, 1 = programmed cell
51 and SO are select-function cells as shown in the output logic
macrocell diagram,

SI - 0
SO - 0

SI - 0
SO - 1

REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT

REGISTER FEE,DBACK, REGISTERED, ACTIVE·HIGH OUTPUT

SI - 1
SO - 0

."

:::a

SI - 1
SO - 1

I/O FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT

1/0 FEEDBACK. COMBINATIONAL. ACTIVE·HIGH OUTPUT

o
C

c:

(")

-I
."

:::a

S
~

2-262

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DAlLAS. TEXAS 75265

TICPAl18V8-30M, TlCPAl18V8-25C
ADVANCED EPIC™ CMOS GENERIC PAL®

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Input voltage, VI (see Note 1) ................................... -0.5 V to Vee+0.5 V
Input diode current, 11K (VI < 0 or VI > Vee). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output diode current, 10K (Vo < 0 or Vo > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±40 mA
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 300 0 e
Operating free-air temperature range: M suffix. . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°e
e suffix .............................. ooe to 75°e
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 1: These ratings apply except during programming and preload cy'cles.
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
-25C

-30M
Vee

Supply voltage

VIH

High-level input voltage

VIL

Low·level input voltage

IOH

High·level output current

IOL

Low-level output current

fclk

Clock frequency
Pulse dlJration

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V

VCC+O.5
0.8

2

VCC+O.5
0.8

V

2
Driving TTL

-2

-3.2

Driving CNiOS

-2

-4

Driving TTL

12

24

2

4

Driving CMOS

V
mA
mA
MHz

CLK high
tw

UNIT

MIN

10

8

eLK low

11

9

Asynchronous reset

30

25

Input or feedback

25

20

Reset inactive state

30

25

0

0

tsu

Setup time

th

Hold time

TA

Operating free-air temperature

Input or feedback

-55

125

0

ns
ns
ns

75

ns
De

:=w

5>
w
a:

Q.

....

. CJ
::::>

c
oa:

Q.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-263

TlCPAl18V8·30M, TICPAl18V8·25C
ADVANCED EPIC™ CMOS GENERIC PAL@

electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)

VOH
VOL

-30M

TEST CONDITIONSt

PARAMETER

MIN

VCC = MIN,

10H = MAX

TTL

VCC = MIN,

10H = MAX

VCC - MIN,
Vec = MIN,

10L - MAX

CMOS
TTL

TYP*

-25C
MAX

4

4

3.B6

3.86

TYP*

MAX

V
0.5
0.4

V
V

10
-10

~A

10ZH

Vce = MAX,

10ZL
,IIH

Vce = MAX,
Vee = MAX,

Vo = 0.5 V
VI = 5.25 V

IlL

Vce = MAX,

VI - 0.5 V

10§

Vce = MAX,

Vo = 0.5 V

Ice

Vce = MAX,
Outputs open 1

VI =

lee
f

Vec = MAX,
f;" 1 MHz

Vi = 0 to 3 V,

Vcc - MAX,
One input at 0.5 V or 2.4 V,

Pin 1

4

4

Alec#

Other inputs at 0 V or Vec
Pin 2
VI = 2 V,
Clock Pin
f = 1 MHz,
All I/O Pins
TA = 25°C
Other inputs

Others

2

2

o

I»
r+
I»

en

:r
(1)

ei

(1)

r+
fI)

-30

-130

o or Vee,

-30

~

-130

mA

100

~

2

15
12

15
12

15

15

10

10

~A

10
-10

100
2

UNIT
V

0.5
0.4

eMOS

10L = MAX
Vo = 2.7 V

MIN

~

mAlMHz
mAl
Input

pF

switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
fmaxl

"'0

o
o

c:

TO
(OUTPUT)

W /0 feedback
With feedback

tcd

1,1/0
eLKt

tcd

Reset

Q

ten

1,1/0

I,Q,I/O

tdis

1,1/0

I,Q,I/O

tod

:a

FROM
(IN pun

0,1/0
Q

TEST CONDITIONS

-30M
MIN

TYP*

e suffix:

50

Rl = 200 Il, R2 = 390 Il,

35
15

-25C
MAX

MIN

TYP*
50

MAX

MHz

35

12

15
12

Rl = 390 Il, R2 = 750 Il,

20

10

ns

eL=50pF
eL = 5 pF, See Figure 4

15

15

ns

15

15

ns

CL=50pF
M suffix:

30

UNIT

25

ns
ns

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vec = 5 V, TA = 25°C.

*

§ This

parameter approximates lOS' The condition

Vo "'"

0.6 V takes tester noise into account.

1Disabled

'.

outputs tied to GND or Vee.
#This is the increase in supply curr~nt for each input that is at one of the specified TTL voltage levels rather than at 0 V or Vee.
Itmax(with feedback) =

tsu

1
e

+ tpd( LK to Q)

; fmaxlwithout feedback) =

(. I
tw hIgh

1

(")

-I
"'0

:a

-m~

:e
2-264

TEXAs

(I

+ tw low

~

INSTRUMENTS
.PoST OFFICE BOX 655012 • DALLAS, TEXAS 15265

TlCPAl18V8·3DM, TICPAl18V8·25C .
ADVANCED EPICTM CMOS GENERIC PAL®
preload procedure for registered outputs
The output registers can be preloaded to any desired state during device testing. This permits any state
to be tested without having to step through the entire state-machine sequence. Each register is pre loaded
individually by following the steps given below. The output level depends on the polarity selected during
programming.
Step
Step
Step
Step

1.
2.
3.
4.

With Vee at 5 volts and Pin 1 at VIL, raise Pin 11 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the voltage
lellel at the output pin.

preload waveforms (see Note 2)

~----:::H

PINll~
f4- tsu -+t

*I

*-td --+I
1
1
PIN 1

i : I I : :
1
1

REGISTERED I/O

!4-td-+l
I
tw--+l
I
I
1 __ 1___ 1_____ VIH

==>-----\
1

I

INPUT

•

U)

CD
CD

.c

t.n
VIL

1
1

~I -vIH

V,.---- VOH

/

\
-VIL

II...
...
CO
CO

C

OUTPUT
VOL

NOTE 2: t,j = tsu = tw = 100 ns to 1000 ns.
VIHH = 10.25 V to 10.75 V.

~
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a::

a..

...

CJ
:::l

o
o

a::
a..

TEXAS . "

INSI:RUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76285

2-265

TICPAL 18V8·30M, TICPAL18V8·25C
ADVANCED EPle™ CMOS GENERIC PAL®
power·up reset
Following power-up, all registers are reset to zero. The output level depends on the polarity selected during
programming. This feature provides extra flexibility to the system designer and is especially valuable in
simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the VCC!s
rise be monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable
input and feedback setup times are met.

power-up reset waveforms

JII

~----------~----------------------5V

4
V CC ___________

J

141+-____ tpd t

.,

(600 ns typ, 1000 ns MAX)

I

ACTIVE·HIGH
REGISTERED OUTPUT

/

STATE UNKNOWN

1
I

1.5 V

/

r-

VOH

------------~-----------------------------~~------£------VOL

I
ACTIVE·LOW
REGISTERED OUTPUT

/

STATE UNKNOWN

11.5V

-----------~-----------------------~I

I+--"" tsu t ---+t

\1.5V

CLOCK

FVIH

--------------------~------_f+'''----------J1- - - VIL
I4-----tw~

tThis is the power·up reset time and applies to registered outputs only. The values shown are from characterization data.
tThis is the setup time for input or feedback.
-

programming information
Texas Instruments Programmable Logic Devices can be programmed using widelY available software and
inexpensive device programmers.
Complete programming specifications, -algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Insruments at (214) 997-5762.

2-266

TEXAS . "

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 15265

TICPAl10VO·30M, TlCPAl1 OVO·25C
ADVANCED EPICTM CMOS GENERIC PAL®
PARAMETER MEASUREMENT INFORMATION

Vcc

~

S1

ISee Note A)

R1
FROM OUTPUT
UNDER TEST -

TEST
...- -...- - - - POINT
R2

CL
ISee Note B)

fI

NOTES: A. When measuring propagation times of 3-state outputs, S1 is closed.
B. Cl ~ includes probe and jig capacitance.

FIGURE 1. LOAD CIRCUIT FOR THREE-STATE OUTPUTS

ISee Notes A

~~~U:'~1.5

V

tpd _ tpLH or tPHL

I

-

-

-

-

-

-

-

en
....CI:ICI:I

3 V
0 V

I ,-_ _ _ _ _--+I___""""'\.J - - - -

II

Y,.5V

I '
I+--tPHL~

OUT·OF·PHASE
OUTPUT

Q)

.c

I+--tpHL~

J+--tPLH--+t

:

~

II)

I

I
IN-PHASE
OUTPUT

\ :- :

....Q)

C

VOH

\15 V

.....- - V O L

I+-tPlH~

II,----

I
\15 V

,

~5~

VOH

__ VOL

VOLTAGE WAVEFORMS
NOTES: A. When measuring propagation times of 3-state outputs. S1 is closed.
B. All input pulses are supplied by generators having the following characteristics: PRR ,;; 1 MHz, Zo

= 50 11, tr =

FIGURE 2, PROPAGATION DELAY TIMES, OUTPUT RISE AND FALL TIMES

3 ns.

~
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a:
0.

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::J

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oa:

0.

TEXAS . "

INSTRUMENTS
POST OFFICE

sox 655012

• DALLAS, TEXAS 75265

2-267

TlCPAl18V8-30M, TICPAl18V8-25C
ADVANCED EPICTM CMOS GENERIC PAL®
PARAMETER MEASUREMENT INFORMATION

f·5V

ClK
(See Notes A and B)

\----3V

14-- tsu--.l

aa

0

a

'.5V
0.3 V

v.~1

2.7

I

I

-----------------------~

I

r-----

I

I

INPUT~I 2.7 V

DATA
(S NtA)

\"'.- - - 0 V

1~4~-------th--~----~~~1

_ _ _ _ _ _ _ _ _ _ _ _J

~~~

3

V

'.5V

~0.;.=.3:..V:...._ _ 0 V

~-~

VOLTAGE WAVEFORMS

FIGURE 3. SETUP AND HOLD TiMES. AND INPUT RISE AND FALL TIMES

--V

C

X
---------..J

DATA INPUT
(See Note A) - A , . 5 V

...
I»
I»

I ......

en

OUTPUT
WAVEFORM 1
SI CLOSED
(See Note C)

...
(1)

(II

---+1----'"'\
I
I
~

1-£1
.
I _.r-

I
I

".5 V

~

I
I
I+-- tPZH--+I

OUTPUT
WAVEFORM 2
S, OPEN _ _ _ _ _ _ _ _J
(See Note C)
.

OV

I+-- tpLZ--+I

I+--- tPZl--+!

:r
(1)

3V

+,.5V

L

t - - -- VOL

I

I

I

J..

lr------t-----~"I
':i '.5 V

2/3 VCC

0.5 V

1

I

I

---

VOH

~0.5 V

..-____

=0 V

I+-- tPHZ---+!
ten - tpZl or tpZH

tdis - tPlZ or tpHZ
VOLTAGE WAVEFORMS

FIGURE 4. ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS

HI~~-~~~El
."

=
o
LOW-LEVEL
PULSE

c:
o

~

~

tw------~~~

14

tw

-

-

-

: :

~I

I

\.5V

-

'-5~

3 V

_ _ _ _ OV

VOLTAGE WAVEFORMS

."

:sm
:e

\~5 ~

5V

----'"'\ I

c

=
m

..Jt.

____

FIGURE 5. PULSE DURATIONS
NOTES: A. All input pulses are supplied by generators having the followng characteristics: PRR :s " MHz. Zo = 50 II. tr = 3 ns.
B. For clock inputs. f max is measured with input duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

2-268

TEXAS . "

INSTRUMENlS.
POST OFFICE BOX 665012 • DAUAS, TEXAS 76266

TlCPAl18V8·30M, TlCPAl18V8·25C
ADVANCED EPIC" CMOS GENERIC PAL@
special design features
True CMOS Outputs: Each' 18V8 output is designed with a P-channel pull-up transistor and an N-channel
pull-down transistor, a true CMOS output with rail-to-rail output switching. This provides direct interface
to CMOS logic, memory, or ASIC devices without the need for a pull-up resistor. The CMOS output has
24-mA drive capability, which makes the '18V8 an ideal substitute for bipolar PAls. The electrical
characteristics of this device show the output under both CMOS and TTL conditions.
Simultaneous Switching: High-performance CMOS devices often have output glitches on nonswitched
outputs when a large number of outputs are switched simultaneously. This glitch is commonly referred
to as "ground bounce" and is most noticeable on outputs held at VOL (low-level output voltage). Ground
bounce is caused by the voltage drop across the inductance in the package lead when current is switched
(dv ex I x di/dt).
One solution is to restrict the number of outputs that can switch simultaneously. Another solution is to
change the device pinout such that the ground is located on a low-inductance package pin. TI opted for
a third option in order to maintain pinout compatibility and eliminate functional constraints. This option
controls the output transistor turn-on characteristics and puts a limit on the instantaneous current available
to the load, much like the lOS resistor in a TTL circuit.
Wake-Up Features: The' 18V8 employs input signal transition detection techniques to power-up the device
from the standby-power mode. The transition detector monitors all inputs, 1I0s, and feedback paths.
Whenever a transition is sensed, the detector activates the power-up mode. The device will remain in the
power-up mode until the detector senses that the inputs and outputs have been static for about 40 ns;
thereafter, the device returns to the standby mode.
Electronic Signature Word: The' 18V8 has a 72-bit word available for the user to store device information,
such as 10 codes, revision numbers, or inventory control. The signature cannot be programmed or altered
once the device is secured.

I...
U)

Q)
Q)

.c

fJ)

...caca

C

Power Dissipation: Power dissipation of the' 18V8 is defined by three contributing factors, and the total
power disSipation is the sum of all three.
Standby Power: The product of VCC and the standby ICC. The standby current is the reverse current
through the diodes that are reversed biased. This current is very small, and for circuits that remain
in static condition for a long time, this low amount of current can become a major performance
advantage.
Dynamic Power: The product of VCC and the dynamic current. This current flows through the device
only when the transistors are switching from one logic level to the other. The total dynamic current
for the '18V8 is dependent upon the users' configuration of the PAL and the operating frequency.
Output loading can be a source of additional power dissipation.
Interface Power: The product of ~ICC (operating) and VCC. The total interface power is dependent
on the number of inputs at the TTL VOH level. The interface power can be eliminated by the addition
of a pull-up resistor.
Even though power dissipation is a function of the user's device configuration and the operating
frequency, the' 18V8 is a lower-powered solution than either the quarter-powered or half-powered
bipolar devices. The virtually zero standby power feature makes the '1 8V8 the device of choice for
low duty cycle and battery-powered applications.

~
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0-

J-

(.,)
:,)

C

o
IX
0-

TEXAS ~

INSTRl}MENTS
POST OFFICE BOX 665012 • OAUAS, TeXAS 75265

2-269

TlCPAl18V8·30M, TlCPAl18V8·25C
ADVANCED EPIC™ CMOS GENERIC PAL®

special design features (continued)
Programming and Eraseability: Programming of the '1aVa is achieved through floating-gate avalanche
injection techniques. The charge trapped on the floating gate remains after power has been removed,
allowing for the nonvolatility of the programmed data. The charge can be removed by exposure to light
with wavelengths of less than 400 nm (4000 AI. The recommended erasure wavelength is 253.7 nm
(2537 A), with erasure time of 20 to 30 minutes, using a light source with a power rating of 12000 pW/cm
placed within 2.5 em (1 inch) from the device.

E

The '1aVa is designed for programming endurance of 1000 write/erase cycles with a data retention of
ten years. A few precautions will guarantee maximum data retention. Continuous exposure to high-intensity
UV light can cause permanent damage. The maximum exposure intensity is 7000 W.s/cm (The equivalent
of leaving the unit in a UV eraser for a· week). The window on the device should be covered by an opaque
label, as the fluorescent light in a room can erase a unit in three years or, in the case of a direct sunlight,
erasure can be complete in one week.

...mmC
(I)

::r
CD
CD

...

U)

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::l:J

o

o
o
-I
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."
::l:J

m

<

m
~

2-270

TEXAS .."

INSTRUMENTS
POST OFFICE BOX 866012 • DAlLAS. TEXAS·76265

TICPAL22V10M, TICPAL22V10C

EPIC'" CMOS PROGRAMMABLE ARRAY LOGIC
03089. DECEM8ER 1987

JL PACKAGE
(TOP VIEW)

•

24-Pin Advanced CMOS PAL

•

Virtually Zero Standby Power

•

Propagation Delay Time ... 20 ns Typ

•

Variable Product Term Distribution Allows
More Complex Functions to be Implemented

•

Each Output is User-Programmable for
Registered or Combinatorial Operation,
Polarity, and Output Enable Control

•

Extra Terms Provide logical Synchronous
Set and Asynchronous Reset Capability

•

Preload Capability on All Registered Outputs
Allow for Improved Device Testing

•

Power-Up Clear on Registered Outputs

•

UV Light Erasable Cell Technology Allows
for:
Reconfigurable logiC
Reprogrammable Cells
Full Factory Testing for
Guaranteed 100% Yields

eLK/)

Vee
1/0/0
1/0/0
1/0/0
1/0/0
1/010
1/0/0
110/0
1/0/0
1/0/0
1/0/0

GND

...
(I)

I

.c

en

•

Programmable Design Security Bit Prevents
Copying of logic Stored in Device

•

Package Options Include Plastic and
Ceramic Dual-In-Line Packages and Chip
Carriers

...asas

C

description
This PAL device features high-speed performance, increased and variable product terms, flexible outputs,
and virtually zero standby power. It combines Tl's EPIC" (Enhanced Processed Implanted CMOS) process
with ultraviolet-light-erasable EPROM technology. Each output has an OlM (Output logic Macrocell)
configuration allowing for user definition of the output type. This PAL provides reliable, low-power
substitutes for numerous high-performance TTL PAls with gate complexities between 300 and 800 gates.
The 'PAl22V10 has 12 dedicated inputs and ten user-definable outputs. Individual outputs can be
programmed as registered or combinational and inverting or noninverting as shown in the Output logic
Macrocell (OlM) diagram. These ten outputs are enabled through the use of individual product terms.
The variable product-term distribution on this device removes rigid limitation to a maximum of eight product
terms per output. This technique allocates from 8 to 16 logical product terms to each output for an average
of 12 product terms per output. The variable allocation of product terms allows for far more complex
functions to be implemented in this device than in previously available devices.
With features such as the programmable OlMs and the variable product-term distribution, the
TICPAl22V10-25 offers quick design and development of custom lSI functions. Since each of the ten
output pins may be individually configured as inputs on either a temporary or permanent basis, functions
requiring up to 21 inputs and a single output or down to 12 inputs and 10 outputs can be implemented
with this device.

p"ducts without notl...

t-

(.)

::l

o

oa:

Copyright @.1987. Texas Instruments Incorporated

PRODUCT PREVIEW documlnts contain information

:::c::tsria;:.ct;:i::.::I~rT;'::'=:ur:~::

~

a:
Q.

Q.

EPIC is a trademark of Texas Instruments Incorporated.
DR products in the formative or _asign ~h8se of
development. Characteristic data anll other

3:
w

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-271

TICPAL22V10M. TICPAL22V1 DC
EPICTMCMOS PROGRAMMABLE ARRAY LOGIC
description (continued)
Design complexity is enhanced by the addition of synchronous set and asynchronous reset product terms.
These functions are common to all registers. When the synchronous set product term is a logic 1. the
output registers are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous
reset product term is a logic 1. the output registers are loaded with a logic 0 independently of the clock.
The output logic level after set or reset will depend on the polarity selected during programming.
Output registers of this device can be preloaded to any desired state during testing. thus allowing for full
logical verification during product testing.
The TICPAL22V10 has internal electrostatic discharge (ESD) protection circuits and has been classified
with a 2000-V ESD rating tested under MIL-STD-883B. Method 3015.1. However. care should be exercised
in handling these devices. as exposure to ESD may result in a degradation of the device parametric
performance.

E

The floating gate programmable cells allow these PALs to be fully programmed and tested before assembly
to assure high field programming yield imd functionality. They are then erased by ultraviolet light before
packaging.

cC»

The TICPAL22V1 0-25 has a power-up clear function. which forces all registered outputs to a predetermined
state after power is applied to the device. Registered outputs selected as active low will power up with
their outputs high while registered outputs selected as active high power up with their outputs low.

r+

C»

en

The M-suffix devices are characterized for operation over the full military temperature range of - 55°C
to 125°C. The C-suffix devices are characterized for operation from OOC to 75°C.

:T
CD
CD

Cit

design security
The 'PAL22V10 contains a programmable design security bit. Programming this bit will disable the read
verify and programming circuitry protecting the design from being copied. The security bit is usually
programmed after the design is finalized and released to production. A secured device will verify as if every
location in the device is programmed. Because programming is accomplished by storing an invisible charge
instead of opening a metal link. the' 22V 10 cannot be copied by visual inspection. Once a secured device
is fully erased. it can be reprogrammed to any desired configuration .

."

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m

S

~
2-272

TEXAS ",

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265

TICPAL22Vl0M, TICPAL22Vl DC
EPIClMCMOS PROGRAMMABLE ARRAY LOGIC

functional block diagram (positive logic)

r--I>

C1
-'1S

SET
RESET

&

44x132
8

.,

IR

>:1

OUTPUT
> LOGIC
r- MACROCELL

h
10

Er-

-~

-----'V

r----.
h

V-

12

>- t--p.

V-

14
~

16
~

+

~

1~

------

>-r-->

~

CLK/I

C>

~

'---

'V

--------.
---..
r----.
h

16

- p.
r-

-

p.

r

>-r-- >

r

14

>-1-- P.

V-

12

~I--

r

10

~-

r

8

P.
>

'-- >

h

r

r-

~I1010

EN

,,- EN

~ f++-I1010

,,- EN

~ f++-I 1010

------

-..r--

-----h

V-

EN

V- EN
-----------

------

~ ......11010

!1

~ ...... 11010

.c

CD
CD

r- EN
r-

1/0/0

EN

~ _I1010

h

V-

EN

~ f++-I

h

V-

EN

~ f-++-I 1010

h

V- EN

1010

'"j!
CO

C

f--; f++- 1/0/0

10
10

10

'V denotes fused inputs

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TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

2-273

TICPAL22V10M, TICPAL22V1 DC
EPICTMCMOS PROGRAMMABLE ARRAY LOGIC

logic diagram (positive logic)
11\

INPUT LINES

0

4

8

'2

'6

20

24

28

32

36

40

AR

D.

i

~
0

12\

·

E

131

·
"

=B::h--

=H=

=t

14\

13

::1

O.0

:::r

CD
CD
til

is\

·

17\

d.0

"'0

·

::lJ

o

181

"

C
C

D.0

-I

9

·

n

d.0

·

::lJ

m

-<
m

f>-

7

CEll

~~.
CEll

(20)

119)

!lS)

J

f- ~J
CELL

(17)

'--

:8=
=H=

IY
~

~J
CELL

(161

'--

:8=

ft:f

:s:t

:sor

(lO)

SP

("1

~

2-274

~J

'--

191

"'0

(21)

~

·
,.
13

CEll

CEll

,.
D.0

~1

~J

o.0

16\

1221

~

·

r+

CELL

(231

~

}f

CJ)

~Cr

(TO All REGISTERS)

L---

=H=

o.0

c

C»
r+
C»

h

9

O.0

co

~CELL

7

ASYNCHRONOUS RESET

~rr
CELL

rn

TEXAS .",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

{151

(141

CEll

SYNCHRONOUS SET

no ALL REGISTERS)
1131

TlCPAL22V10M. TlCPAL22V10C
EPIC™CMOS PROGRAMMABLE ARRAY LOGIC

/

output logic macrocell (OlM) description
A great amount of architectural flexibility is provided by the user-configurable macrocell output options.
The macrocell consists of a D-type flip-flop and two select multiplexers. The D-type flip-flop operates like
a standard TTL D-type flip-flop. The input data is latched on the low-to-high transition of the clock input.
The Q and Q outputs are made available to the output select multiplexer. The asynchronous reset and
synchronous set controls are available in all flip-flops.
The select multiplexers are controlled by programmable bits. The combination of these programmable bits
will determine which macrocell functions are implemented. It is this user control of the architectural structure
that provides the generic flexibility of this device.

output logic macrocell diagram

OUTPUT lOGIC MACROCEll

...

MUX

U)

r--------------4.-----~3
2
R 1-0
AR

Q)
Q)

.c:

fn

10

...

C1

I
FROM CLOCK BUFFER

ss

I
I

MUX

C

.,

G1

II

CO
CO

1}
03
GO

15

AR _ .synchronous reset

S5 - synchronous set
L______

I
I
I
I
J

~
w

:>w
a:

c.
l-

t.)

:::>

c
oa:

c.

TEXAS ."

INSTRUMENTS
POST OFFice BOX 655012 • DALLAS. TeXAS 76265

2-275

TICPAL22V10M, TICPAL22V10C

EPIC"'CMOS PROGRAMMABLE ARRAY LOGIC
output logic macroc.1I optio"s
MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE
CELL
SELECT

51
0
0
1
1

FEEDBACK AND OUTPUT CONFIGURATION

SO

0
1
0
1

Register feedback

Registered

Register feedback

Registered

Active low
Active high

I/O feedback

Combinational

Active low

I/O feedback

Combinational

Active high

o = erased cell

1 = programmed cell
51 and SO are select-function cells as shown in the output logic macracell
diagram.

II
...c
CI)
CI)

en
::T

...
CD
CD

51 - 0
SO - 0

(I)

51 - 0
SO - 1

REGISTER FEEOBACK, REGISTERED, ACTIVE-LOW OUTPUT

REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT

51 - 1

51 - 1
SO - 1

SO - 0

""D

::lD

o

1/0 FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT

1/0 FEEDBACK, COMBINATIONAL, ACTIVE-HIGH OUTPUT

C

c:

n

-I
""D

::lD

m

S
m

~
2-276

TEXAS .."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

T1CPAL22V1DM, T1CPAL22V1 DC
EPIC™CMOS PROGRAMMABLE ARRAY LOGIC
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Supply voltage range, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 to Vee + 0.5 V
Input diode current, 11K (VI < 0 or VI > Vee). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output diode current, 10K (Va < 0 or Va > Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Continuous output current, 10 (Va = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±40 mA
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds: FN or N package ......... 260°C
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds: FH or J package .......... 300°C
Operating free-air temperature range: M suffix .......................... - 55°C to 125°C
e suffix .............................. OOC to 75°C
Storage temperature range ......................................... - 65°C to 150°C
Note 1: This rating applies except during programming and preload cycles.

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other conditions beyond those indicated under" recommended
operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
M SUFFIX
Supply voltage

VCC
VIH

High-level input voltage

Vil

low-level input voltage

IOH

High-level output current

IOl

Low-level output current

fclock

Clock frequency

NOM

MAX

4.5
2

5

5.5

Driving TIL

en

C SUFFIX

MIN

VCC+O.5
0.8
-2

MIN
4.75
2

NOM

MAX

5

5.25
VCC+O.5
0.8
-3.2

Driving CMOS

-2

-4

Driving TTL

12

16

2

4

Driving CMOS

UNIT
V
V
V
mA

0

0

MHz

8

ns

Pulse duration

ClK low

11

9

ns

25

n.

Setup time

30
26

tsu

20
25

n.

th

Hold time
Operating free-air temperature

Asynchronous reset
Input or feedback
Reset inactive state
Input or feedback

TA

0
-55

0
125

0

75

(I)

...
IV
IV

Q

10

30

CD
CD

.c

mA

ClK high
tw

EI...

ns
DC

3:
w
5>
w

a:

a..

I(.)
:::;)

C

oa:
a..

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

2-277

TlCPAL22V10M, TICPAL22V1 DC
EPICTMCMOS PROGRAMMABLE ARRAY LOGIC
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VOH

= MIN,
= MIN,

10H
10H

Vee

MAX,

Vo

10ZL

Vo

IIH

Vee = MAX,
Vee - MAX,

IlL

Vee

V"

10§

=
=
=

Vee
MAX,
Vee
MAX,
Outputs open'

MAX for TTL
MAX for eMOS

=0

alee#

Vee - MAX,
One input at 0.5 V or 2.4 V,

Vi

CD
CD

=

TA

4
3.86

TYP~

MAX

25 0 e

-30

I

I

UNIT
V
V

0.5

0.5

V

0.4

0.4
10
-10

V

-130

-30

~
~

-130

mA

100

~A

2

2

~A

10
-10

100

~

mA/MHz

Pin 1

4

4

Others

2

2

mA
12

12

I All inputs

10

10

1 All 1/0 pins

15

15

1 MHz,

=

4
3.86

to 3 V,

I

f

MIN

= 2.7 V
= 0.5 V

= 0.5 V
Vo = 0.5 V
VI = 0 or Vee,

MAX,

lee
f

ei

C SUFFIX
MAX

TYP*

VI - 5.25 V

Vee = MAX,
f = 1 MHz

t/)

MIN

10L - MAX for TTL
10L =; MAX for eMOS

10ZH

=

=
=

Other inputs at 0 V or Vee
elock pin
VI = 2 V,

::r

....en

Vee

-Vee - MIN,
Vee = MIN,

C

....m
m

Vee

VOL

lee

M SUFFIX

TEST CONDITIONSt

pF

switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
.
PARAMETER
fmaxll

FROM
(INPUT)

TO

TEST CONDITIONS

10UTPUT)

Without feedback

e suffix:

With feedback

tod

1,1/0

0,1/0

tod
tod

eLKt
RESET

0
0

len
tdis

1,1/0
1,1/0

1,0,1/0
1,0,1/0

M SUFFIX
MIN

Rl
!

= 20011,
= 50 pF

R2

= 39011,

eL
M suffix:
Rl
eL
CL

= 39011, R2 = 75011,
= 50 pF
= 5 pF, See Figure 4

TYP~

CSUFFIX
MAX

MIN

MAX

UNIT

45

TYP*
45

30

30

20

20

ns

15
25

15
25

ns

20

20

ns

20

20

ns

MHz

ns

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

= 5 V, TA = 25°e.
§This parameter approximates lOS- The condition Va

tAli typical values are at Vee

-a

:D

o
C

c:
n

= 0.5

V takes tester noise into account.

'Oisabled outputs are tied to GNO or Vee.
'This is the increase. in supply current for each input that is at one of the specified TTL voltage levels rather than at 0
hmaxlwith feedback) = _ _1
_ _ (eLK to 0); fmaxlwithout feedback) = _ _
. _1_ __
tw1htl + tw(iow)
tsu + tpd

-I

-a

:D

m

S
m

:e

2-278

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, texAS 75265

V or Vce.

TICPAL22V10M, TlCPAL22V1 DC

EPIC"'CMOS PROGRAMMABLE ARRAY LOGIC
preload procedure for registered outputs
The output registers can be preloaded to any desired state during device testing. This permits any state
to be tested without having to step through the entire state-machine sequence. Each register is preloaded
individually by following the steps given below. The output level depends on the polarity selected during
programming.
Step
Step
Step
Step

1.
2.
3.
4.

With Vee at 5 volts and pin 1 at VIL, raise pin 8 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse pin 1, clocking in preload data.
Remove output voltage, then lower pin 8 to VIL. Preload can be verified by observing the voltage
level at the output pin.

preload waveforms (see Note 2)
PIN 8

~-

/

---f

I4-tsu~

I+-td--+l

CLK/I

I

I
I

VIL

I

I
I

~

~ -VIH

REGISTERED I/O ~

INPUT

I

-VIL

= tsu = tw =

- VIHH

i l l i !- --IUU-:::
I
I

NOTE 2: td

-

I'

)4-td-+l

I+-tw---'

-

100 ns to 1000 ns. VIHH

=

I
I
V,.---VOH

\

EI...
en

Q)
Q)

.c

fI)

...

CO
CO

C

OUTPUT
VOL

10.25 V to 10.75 V.

W

==
:;
w

a:
Q.

....

o

:::>

o
oa:
Q.

TEXAS . "

INSTRUMENTS
POST OffiCE BOX 655012 • DALLAS, TEXAS 75265

2-279

TlCPAl22V10M, TlCPAL22V1 DC
EPIClMCMOS PROGRAMMABLE ARRAY LOGIC
power-up reset
.Following power-up, all registers are reset to zero. The output level depends on the polarity selected during
programming. This feature provides extra flexibility to the system designer and is especially valuable in
simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the VCC's
rise be monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable
input and feedback setup times are met.

power-up reset waveforms

4
VCC __________

J

;;r

~-----------------------------------5V

1414~---tpdt
(600 ns typo '000 ns MAX)
ACTIVE-HIGH
REGISTERED OUTPUT

...C
I»
I»

ACTIVE-lOW
REGISTERED OUTPUT

/

STATE UNKNOWN

I

STATE UNKNOWN

~

~

~

1~~: ---T::~

!

!f,.5 V

_ _ _~ ____""" ____________________-.J :

rJ)

-

-

-

-

-

\

_~

VOH

-

VOL

J+-t.u*~

:::r
CD

!(I)

ClK/1

_____________________________~'.5V

.

CVIH

1:,.5V
- --

~----------J~

Vil

I+---tw~

tThis is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
*This is the setup time for input or feedback.

programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available softwl!re and
inexpensive device programmers.
Complete programming specification, algorithms, and the lastest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5762.
-

"'D

:a

o
c

c:

(')

-I
"'D

:a

m

-:e
<

m

2-280

TEXAS .."

INSTRUMENTS
PO$T OFFICE BOX 655012 • DALLAS, T-EXAS 76265

TICPAL22V10M, TICPAL22V1 DC
EPIC™CMOS PROGRAMMABLE ARRAY LOGIC
PARAMETER MEASUREMENT INFORMATION

Vee
S,

~

ISee Nota A)

FROM OUTPUT _ _ _

R1
_ _>-- TEST

~~

UNDER TEST

POINT
R2

NOTES: A. When measuring propagation times of 3-state outputs, 51 is closed.
B. CL = includes probe and jig capacitance.

...en

FIGURE 1. LOAD CIRCUIT FOR THREE-STATE OUTPUTS

INPUT
ISea Notas A and B)

-..IiL'5V

\~5:-tpd - tPLH or tpHL

I

(4--tpLH~

IN-PHASE
OUTPUT

,
:,

'
Y,.5V

-----3V
OV

...

, •
I+--tpHL~

II

I

,~.:V--VOH

,

-

til

ctI
ctI

C

VOL

k--tPLH~

!+-tPHL---+r
OUT-Of-PHASE
OUTPUT

CI)
CI)

.c

\,.5 V

I'

'-----------~

VOH

'.5 V
-

-

- - VOL

VOLTAGE WAVEFORMS
NOTES: A. When measuring propagation times of 3-state outputs, S1 is closed.
B. All input pulses are supplied by generators having the following characteristics: PRR '" 1 MHz, Zo

= 50 I), tr = 3 ns.

FIGURE 2. PROPAGATION DELAY TIMES. OUTPUT RISE AND FALL TIMES

3=
w
5>
w
a::

a.

I-

(.)
::)

C

oa::
a.

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 6550~ 2 • DALLAS. TeXAS 75265

2-281

TICPAL22V10M. TICPAL22V10C
EPIClMCMOS PROGRAMMABLE ARRAY LOGIC
PARAMETER MEASUREMENT INFORMATION

f·

ClK
(See Not..s A and BI

____________- J

5V

~14~--------th--------~~~,

~tsu---+l

DATA~I
':5 V

INPUT
(See Note Al

0.3 V

I

2'7V~:

2.7V

---------------""i

I
~~~
I

,..---------3 V
'.5 V

I

,.,;;,0;,;;.3,.;V;.....___

°

V

~q~
VOLTAGE WAVEFORMS

,.------------

FIGURE 3. SETUP AND HOLD TIMES. AND INPUT RISE AND FALL TIMES

I~~~~
(See Note Al

==x

X,

1.5 V
I _ _ _ _ _ _ _ _ _ _ _ _ _ _.J.

I

I

I

I

I

\1.5V

I

I

I

OUTPUT

J_rO.

°V
~2/3 VCC

II/::

:

I.

I+-- tPZH---..I

•

~3 V

I+-- tpLZ----+I

I+-- tpZL ---+i
OUTPUT
WAVEFORM 1
S1 CLOSED
(Se•. Note CI

1.5 V

I

,..-------1"-----,
I

5V

'"" -

-

..t..
...J -

-

- - VOL

KLo.5 ~

WAV~10~:E~ _____________",·5 V

-

- VOH

I

(See Note C I '

~O V

~tpHZ--+I

ten - tpZl or tpZH

'dis

= 'PLZ

or tpHZ

VOLTAGE WAVEFORMS

FIGURE 4. ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS

.~

HI~~~:~EL

(")

-I

\-5 ~ ----::

5 V

1144------'w ----~~

o
o

c:

-Jt.

______

~14r_----tw------~~1

-----'\ I
LOW-LEVEL
PULSE

I

f..5~

\.5V

."

VOLTAGE WAVEFORMS

m

FIGURE 5. PULSE DURATIONS

:D

<
in

==

3 V

____

NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR
B. For clock inputs, f max is measured with input duty cycle = 50%

s

ov

1 MHz, Zo = 50 0, t, = 3 ns.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

TEXAS

+

INSTRUMENTS

POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TICPAL22V10M, TICPAL22V10C
EPICTMCMOS PROGRAMMABLE ARRAY LOGIC
special design features
True CMOS Outputs: Each '22V10 output is designed with a P-channel pull-up transistor and an N-channel
pull-down transistor, a true CMOS output with rail-to-rail output switching. This provides direct interface
to CMOS logic, memory, or ASIC devices without the need for a pull-up resistor. The CMOS output has
16-mA drive capability, which makes the '22V10 an ideal substitute for bipolar PALs. The electrical
characteristics of this device show the output under both CMOS and TTL conditions.
Simultaneous Switching: High-performance CMOS devices often have output glitches on nons witched
outputs when a large number of outputs are switched simultaneously. This glitch is commonly referred
to as "ground bounce" and is most noticeable on outputs held at VOL (low-level output voltage). Ground
bounce is caused by the voltage drop across the inductance in the package lead when current is switched
(dv ex I X di/dt).
One solution is to restri.ct the number of outputs that can switch simultaneously. Another solution is to
change the device pinout such that the ground is located on a low-inductance package pin. TI opted for
a third option in order to maintain pinout compatibility and eliminate functional constraints. This option
controls the output transistor turn-on characteristics and puts a limit on the instantaneous current available
to the load, much like the lOS resistor in a TTL circuit.
Wake-Up Features: The '22V1 0 employs input signal transition detection techniques to power-up the device
from the standby-power mode. The transition detector monitors all inputs, II0s, and feedback paths.
Whenever a transition is sensed, the detector activates the power-up mode. The device will remain in the
power-up mode until the detector senses that the inputs and outputs have been static for about 40 ns;
thereafter, the device returns to the standby mode.
Power Dissipation: Power dissipation of the '22V1 0 is defined by three contributing factors, and the total
power dissipation is the sum of all three.

...en=
.c

en

...caca

o

Standby Power: The product of VCC and the standby ICC. The standby current is the reverse current
through the diodes that are reversed biased. This current is very small, and for circuits that remain
in static condition for a long time, this low amount of current can become a major performance
advantage.
'
Dynamic Power: The product of VCC and the dynamic current. This dynamic current flows through
the device only when the transistors are switching from one logic level to the other. The total dynamic
current for the '22V10 is dependent upon the users' configuration of the PAL and the operating
frequency. Output loading can be a source of additional power dissipation.
Interface Power: The product of ICC (operating) and VCC. The. total interface power is dependent
on the number of inputs at the TTL VOH level. The interface power can be eliminated by the addition
of a pull-up resistor.
Even though power dissipation is a function of the user's device configuration, and the operating
frequency, the '22V1 0 is a lower powered solution than either the quarter-powered or half-powered
bipolar devices. The virtually zero standby power feature makes the '22V10 the device of choice
for low-duty-cycle and battery-powered applications.

~
w

:>w
a:

Programming and Eraseabllity
Programming of the '22V1 0 is achieved through floating-gate avalanche injection techniques. The charge
trapped on the floating gate remains after power has been removed, allowing for the nonvolatility of the
programmed data. The charge can be removed by exposure to light with wavelengths of less than 400 nm
(4000 A). The recommended erasure wavelengthJs 253.7 nm (2537 A), with erasure time of 20 to 30
minutes, using a light source with a power rating of 12000 p.W/cm placed within 2.5 cm (1 inch) of the
device.

a.

~

(J

::J
Q

oa:
a.

TEXAS . "

INSTRUMENTS
POST OFfiCE BOX 655012 " DALLAS, TEXAS 75265

2-283

TlCPAL22V10M, TICPAl22V1 DC
EPICTMCMOS PROGRAMMABLE ARRAY LOGIC
Programming and Eraseability {continued)
The '22V10 is designed for programming endurance of 1000 write/erase cycles with a data retention of
ten years. A few precautions will guarantee maximum data retention. Continuous exposure to high-intensity
UV light can cause permanent damage. The maximum exposure intensity is 7000 W.s/cm (The equivalent
. of leaving the unit in a UV eraser for a week). The window on the device should be covered by an opaque
label, as the flourescent light in a room can erase a unit in three years or, in the case of a direct sunlight,
erasure can be complete in one week .

•
""0
::J:J

o
C

c:
(')
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~

m

<
-m
~

2-284

TEXAS

+

INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 76285

TlEPAl1 OH 16PB·3C
HIGH·PERFORMANCE ExeL ™PAL® CIRCUIT
03084, DECEMBER 1987

JTPACKAGE
ITOPVIEWI

•

ECl 10KH PAL

•

High-Performance Operation
Propagation Delay , , . 3 ns Max

•

Replacement for Conventional ECl logic

•

24-Pin, 300-Mil Package

•

Reliable Titanium-Tungsten Fuses

Vee
I
I/O

I/O

o
Veeo
o

o

Veeo

o

description

I/O

I/O

This ECl PAL device combines the ExCl'"
(Double Polysilicon Self-Aligned) process with
the proven titanium-tungsten fuses to provide
reliable, high-performance substitutes for
conventional ECl logic, Its easy programmability
allows for quick design of "custom" functions
and typically results in a more compact board,
In addition, chip carriers are available for further
reduction in board space,
The TIEPAl1 OH 16P8-3 is provided with output
polarity fuses, Each output remains active-high
when the fuse is intact and is active-low when
the fuse is blown,
The TIEPAl 10H16P8-3 has 12 dedicated inputs,
four standard outputs, and four I/O ports, It
should be noted that with emitter-coupled
outputs, a high level overrides a low level,
Therefore, in order to use an I/O port as an input,
the related output must be forced to a low level
either through satisfying preprogrammed
equations or permanently by programming,

II....

FK PACKAGE
(TOPVIEWI

en

u

___ uz>u __
4

I/O

o
Veeo
Ne
o
I/O

3

CD
CD

.c

2 1 28 27 26

5

25

I/O

6

24

0

7

23

8

22

Veeo
Ne

9

21

0

10

20

I/O

11

en

....'"

'"

C

19
12 13 14 15 16 17 18

wu - - -

~z

NC - No internal connection

The TlEPAl1 OH 16P8-3 is equipped with a
security fuse, Once the security fuse is blown,
additional programming and verification cannot
be performed, This prevents easy duplication of
a design,
This device is characterized for operation from OOC to 75°C; this temperature range is designated by a
"C" suffix in the part number (TiEPAl10H16P8-3CJT),

~
w

:>w
a:

Q.

t-

O

::>
C

oa:

ExCL is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories Inc.

PROOUCT PREVIEW documlllll.Dntoi. i.lormodD.
o. pradaell I. tho for ••Ii.1 or dl.i.. ~ha.. of
dl.olop ....t. Chlr••tarl,tI. data .Ii other

::'l::'rr.':t
d:i::.:::"';rT=~,==
pnducll
witIoout .oti..,

a..

TEXAS ,.,
INSTRUMENTS
POST OFFICE BOX 1555012 • DALLAS, TEXAS 75265

Copyright © 1987, Texas Instruments Incorporated

2-285

TlEPAl10H16PB·3C
HIGH·PERFORMANCE ExCLTMPAL® CIRCUIT
functional block diagram (positive logic)
8

&
32 X 64

l!:

8

-1

-

"v

~

"v

~

"v

8
12
4.

16Xt>

16
16

8

"v

~

8

"v

~

8
~

11
...c
C»
C»

"v

8
~

"v

~

"v

8

4

en

::r
CD

!o

"'0

::I:J

o
C

c:

(")

-t
"'0

::I:J.

m
S
m

:e

2-286

'"
'"

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 866012 • DAUAS. TEXAS 75286

Vee

o
o

o

o
110

I/O
110

I/O

TIE PAL 1OH 16P8·3C
HIGH·PERFORMANCE ExCLTM PAL® CIRCUIT
logic diagram (positive logic)
[28](241

VCC

INPUT LINES
/\

10 ••• 4 ••• 8 ••• 12 ••• 16 ••• 20 ••• 24 ••• 28 •••'

[2](11

~

[27](231

,

v!>"-

[3](21

...

[26](221

~

PRODUCT
LINES

0

•
•
•
7

f>?ol

[25](211

I/O

I

[4](31

II

8

110

•
•
•
15

[5](41

r

I

....en
Q)
Q)

.......

.s:.
en
....caca

16

•
•
•
23
o

4

[6](51

?p

[24](201

~

0

0

24

•
•
•
31

~
~

I--'

32

t>p

•
••
39

[21](181

o

40

o

•
•
•
47

~

[9](71

48

•
•
•
55

gppr

[20](171

I

~

56

110

••
•
63

[10](81

r
I

[11](91
[12](101

....

[17](141
f------fA

"" ....

NOTE: Pin numbers in

r 1 are for the

0..

[18](151

[13](111

FK package; pin numbers in ( ) are for JT package.

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

~
:>w
a:

[19](161

::
::

I/O

[16](131

t-

(.)

::l

C

o
a:
a..
2·287

TIEPAl1 OH 16P8-3C
HIGH-PERFORMANCE ExCL™PAL® CIRCUIT,
absolute maximum ratings over operating frea-air temperature range (unless otherwise noted)
(see Note 1)
Supply voltage, VEE (see Note 2) ....................................... 0 V to -6.5 V
Input voltage, VI (see Note 3) .................................. . . . . . . . . .. 0 V to VEE
Output current .......................................... '. . . . . . . . . . . . . .. - 50 mA
Operating free-air temperature ran~e: C suffix .................... : ......... OOC to 75°C
Storage temperature range ......................................... - 65 OCto 150°C
NOTES:

1. These ratings apply except for programming pins during a programming cycle.

2. All voltage values are with respect to Vee and Veeo. i.e .• these pins are all assumed to be at 0 volts.
3. VI should never be' more negative than VEE.

recommended operating conditions (see Note 4)

•

VEE

Supply voltage
TA

= ooe
= 25°C
= 75°C
= ooe

c
....

VIH

High-level input voltage

TA
TA
TA

en
:::r

VIL

Low-level input voltage

TA - 25°C
TA = 75°C

TA

Operating free-air temperature

D)
D)

CD

!

(I)

MIN
-4.94
-1.17
-1.13
-1.07
-1.95
-1.95
-1.95

C-SUFFIX
NOM
MAX
-5.2 -5.46
-0.84
-0.81
-0.735
-1.48
-1.48
-1.45

0

75

UNIT
V
V

V
°e

NOTE 4: The algebraic convention. in which the more negative limit is designated as minimum and the less negative limit is designated
as maximum. Is used in this data sheet for logic voltage levels only. For other quantities. e.g .• supply voltages and currents.
the normal. magnitude convention is used.

electrical characteristics over recommended supply voltage range at specified free-air temperature
,
(see Notes 4 and 5)
PARAMETER

TEST CONDITIONS
ooe

VOH

VI

= VIHmin or VILmax

25°C
75°C
ooe

VOL

VI

= VIHmin or VILmax

25°C
75°C
ooe

"'tJ
.::JJ

IIH

VI

= VIHmax

25°C
75°C
ooe

c
c:
n

IlL

VI

= VILmin

25°C
75°C
ooe to 75°C

o

-I

"'tJ
::JJ

-~

lEE

All Inputs open

C-SUFFIX
TVP
MIN
MAX
-1.02
-0.84
-0.98 -0.895 -0.81
-0.92
-0.735
-1.95
-1.63
-1.95
-1.63
-1.95 -1.79 -1.60
220
220
220
0.5
0.5
0.3

UNIT

V

V

p.A

~A

-220

mA

NOTES: 4. The algebraic convention. in which the more negative limit is designated as minimum and the less negative limit is designated
as maximum, Is used in this data sheet for logic voltage levels only. For other quantities, e.g., supply voltages and currents.
the normal magnitude convention is used.
5. Each 10KH PAL has been designed to meet these specifications after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and transverse air flow greater than 150 meters (500 feetl per minute
Is maintained. Outputs are terminated through a 50-ohm resistor to - 2 V.
.

~
2-288

TEXAS •

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TlEPAl1 OH 16P8·3C
HIGH·PERFORMANCE ExeLTM PAL@ CIRCUIT
switching characteristics over recommended ranges of supply voltage and operating frae-air temperature
(see Note 5)
PARAMETER

FROM
(lNPUTI

TO
(OUTPUTI

tpd

I, 1/0, or feedback

0,1/0

C-SUFFIX

TEST CONDITIONS

MIN

See Figures 1 and 2

tr
tf

TYP

MAX

UNIT

1

3

ns

0.7

1.5

ns

0.7

1.5

ns

NOTE 5: Each 10KH PAL has been designed to meet these specifications after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and transverse air flow greater than 150 maters (500 leetl per minute
is maintained. Outputs are terminated through a 50~ohm resistor to - 2 V.

PROGRAMMING INFORMATION
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5762.

PI
...
U)

CD
CD

.c

o

...
CO
CO

PARAMETER MEASURI=MENT INFORMATION

Q
INPUT- - 1 ' " 5 - 0 - % - - - \ ; ; - - -

1

I

1

,'50% I
•

tPLH~
IN·PHASE
OUTPUT
tpHL

I

VIL

~tPHL

VOH
II i-;;;.;;
~
VOL

-J..-.--..c

OUT '()F.pHASE
OUTPUT

VIH

I4---*-tpLH

1
\ 50%
•

OUTPUT
WAVEFORM

F'
50% VOH
__ VOL

801f

I

20%
I

I

I 1

t,......c

VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES

I+-

"t"
"---VOH
(80%1

I

1
I

(20%1
I

V
OL

I 1
~

I4-tf

VOLTAGE WAVEFORMS
RISE TIME AND FALL TIME

FIGURE 1. VOLTAGE WAVEFORMS

;:
w
5>
w
a::

Q.

t;
::;)

C

oa::
a.

TEXAS . "

INSfRUMENlS
POST OFFICE BOX 855012 • DALLAS. TeXAS 16265

2-289

I

TIEPAL 1OH16P8·3C
HIGH·PERFORMANCEExCLTM PAL® CIRCUIT
PARAMETER MEASUREMENT INFORMATION
2.00 V ± 0.01 V

25 "F

r

0.1 "F

q

iNPUT

OUTPUT
UNDER ~-4---~~~~~
TEST

....... UNDER

t-t-~----t-+---

TEST

c

!C»

~
CD

....

CD

VIH max
or

+ 2V{

VIL min

+ 2V

}

ALL
OTHER
INPUTS

ALL
{
OTHER
OUTPUTS

~.

VEE

0.1 "F

q

-3.20 V ± 0.01 V
NOTES: A. The offset voltage generator has the following characteristics: Pulse amplitude = BOO mV poP. PRR :s; 1 MHz. tw = 500 ns.
t,=tf=lns.
B. RT is • 50-0 terminator internal to the oscilloscope.
C. CL :$ 3 pF. includes fixture and stray clipacitance.
D.Coax has 50-0 impedance and the coax to oscilloscope channel A and to channel B must be of equal lengths.
E. All unused outputs are loaded with 50-0 ± 1% resistors to ground.
F. All. unused inputs should be connected to either high or low levels consistent with the logic function required.
G. All fixture wire lengths or unterminated stubs should not exceed 6 mm (114 inch).

FIGURE 2. LOAD CIRCUIT

2-290

TEXAS ,.,
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265

TIE PAL 1OH 16PB·6C
HIGH·PERFORMANCE IMPACTTMECL PAL~ CIRCUIT
02111

•

ECl 10KH PAL

•

High-Performance Operation
Propagation Delay ... 6 ns Max

•

Replacement for Conventional ECl logic

•

24-Pin, 300-Mil Package

•

Reliable Titanium-Tungsten Fuses

MAY 1987-REVISEO OECEMBER 1987

TIEPAL10H16P8-6 .•• JT PACKAGE
(TOP VIEW)

Vee
I
I
I/O

I
I/O

0

0

Veea

Veeo

0

0

description

1/0

This IMPACT'" ECl PAL device uses proven
titanium-tungsten fuses to provide reliable, highperformance substitutes for conventional ECl
logic. Its easy programmability allows for quick
design of "custom" functions and typically
results in a more compact board. In addition, chip
carriers are available for further reduction in
board space.

I

TIEPAL10H16P8-6 ... FK PACKAGE
(TOP VIEW)

u
___ uz>u __

The TIEPAl1 OH 16P8-6 is provided with output
polarity fuses. Each output remains active-high
when the fuse is intact and is active-low when
the fuse is blown.

4

The TlEPAl 10H16P8-6has 12 dedicated inputs,
four standard outputs, and four 110 ports. It
should be noted that with emitter-coupled
outputs, a high level overrides a low level.
Therefore, in order to use an 1/0 port as an input,
the related output must be forced to a low level
either through satisfying preprogrammed
equations or permanently by programming.
The TIEPAL10H16P8-6 is equipped with a
security fuse. Once the security fuse is blown,
additional programming and verification cannot
be performed. This prevents easy duplication of
a design.

1/0

3

2

1 28 27 26

5

25

6

-24

7

23

8

22

9

21

10
11

20
19

121314 15 1617 18

wu---

~z

NC - No internal connection

This device is characterized for operation from OOC to 75°C; this temperature range is designated by a
"C" suffix in the part number (TIEPAL10H16P8-6CJT).

IMPACT is a trademark of Texas Instruments Incorporated
PAL is a registered trademark of Monolithic Memories Inc.

PRODUCTION DATA d...m.........1. information
currant .1 af publication doll. Products .0.lorm II

sp..if_o.. per thlllrml af Tun Instrum....

:.=~i~·i~1:.'li =::':1' lJl·::::~ nat

Copyright @ 1987, Taxaslnstruments Incorporated

TEXAS . "

INSTRl)MENlS
POST OFFICE BOX 655012 • DALI.AS, TEXAS 75265

2-291

TlEPAl1 OH 16PB·6C
HIGH·PERFORMANCE IMPACTTMECL PAL® CIRCUIT
functional block diagram (positive logic)
8

&

-1

~,

32 X 64
8

-

'V

~

'V

~

'V

8
12
4,

16X!>

16
16

'V

8

'V

8

..- h
~

h.

8
~

11
c

am

8

r+

rn

TEXAS

~

IN STRUM ENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

o
1/0
1/0

'V

1/0

vee

rn
:r

o

1/0

~

4

o

..- 'V

8

CD
CD

2·292

'V

o

TlEPAl1DH16PB·6C
HIGH·PERFORMANCE IMPACT'MECL PAL® CIRCUIT

logic diagram (positive logic)
[281124}

Vcc

INPUT LINES
/\

10 ... 4 ... 8 ... 12 ... 16 ... 20 ... 24'''28 .. ''
[2111}

....1 - -

v

[3112}
PRODUCT
LINES

0>-

0

A

[271123}

::

[261122}

=l

•
•
•
7

>PI

[251121}

1/0

T

[4][3}

I...

8
[5114}

I/O

•

r~
I

•
•
15

CI)

CI)
CI)

.s::

t/)

16

•

??D

•
•
23

[241120}

5::

...
CO
CO

0

0

24

o

•
•
•
31

~

[6115}

32

•
•
•
39

>P

40

o

[211118}

o

•
•
•
47

[9](7}

48

•
•
•
55

§P?Dr
,.

A

[201117}

1/0

I

56

I/O

[lOllS}

r
I

[11119}
[121110}
[131111}

•
•
•
63

....

A

[19](16}

..;

[171114}

:::

[181115}

...
...

I-------.~
f---J't

[161113}

NOTE: Pin numbers in [ 1 are for the FK package; pin numbers in ( ) are for JT package.

TEXAS

~

INSfRUMENlS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265

2-293

TlEPAl1 OH 16P8-6C
HIGH-PERFORMANCE IMPACT™ECL PAL@, CIRCUIT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
(see Note 1)
Supply voltage, VEE (see Note 2) ....................................... 0 V to -6.5 V
Input voltage, VI (see Notes 2 and 3) ..................................... ;. 0 V to VEE
Output current ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 50 mA
Operating free-air temperature range: e suffix .............................. ODe to 75 De
Storage temperature range ......................................... - 65 De to 150 De
NOTES: 1. These ratings apply except for programming pins during a programming cycle.
2. All voltage valuas are with respect to VCC and VCCO, i.e., these pins are all assumed to be at 0 volts.
3. VI should never be more negative than VEE.

recommended operating conditions (see Note 4)

IIo

VEE
VIH

Supply voltage
TA = OoC
TA = 25°C

High-level input voltage

I»
~
I»

TA '" 75°C
TA '" ooC
TA = 25°C
TA = 75°C

(I)

VIL

Low-level Input voltage

i

TA

Operating free-air temperature

!

(n

MIN
-4.94
-1.170
-1.130
-1.070
-1.960
-1.960
-1.950
0

C-SUFFIX
NOM
M~
-5.2 -5.4/3

UNIT
V

-0.8~0

-0.8to
-0.736
-1.4811
-1.48(>
-1.450\
76

v

V
°C

NOTE 4: The algebraic convention, in which the more negative limit is designated as minimum and the less negative limit is designated
as maximum, is used in this data sheet for logic voltage levels only. For other quantities, e.g., supply voltages and currents,
the normal magnitude convention Is used.

electrical characteristics over recommended supply voltage range at specified free-air temperature,
Vee - Veeo - 0 (see Notes 4 and 5)
PARAMETER

TeST CONDITIONS

TA

VOH

VI = VIHmln or VILmax

25°C
76°C
ooC

VOL

VI = VIHmin or VILmax

25°C
75°C
ooC

IIH

VI'" VIHmax

25°C
75°C
OOC

IlL

VI = VILmin

lEE

All inputs .opan

25°C
75°C
O'C to 76°C

OOC

MIN
-1.020
-0.980
-0.920
-1.950
-1.950
-1.950

C-SUFFIX
TVP

MAX
-0.840
-0.810
-0.735
-1.630
-1.630
-1.600
220
220
220

0.5
0.5
0.3

UNIT

V

V

pA.

pA.

-240

mA

NOTES: 4: The algabralC convantlon, In which the more negative limit i. designated a. minimum and the la•• negative limit is deSignated
as maximum, Is used in this data sheet for logiC voltage levels only. For other quantities, e.g" supply voltages and currents,
the normal magnitude convantion Is used.
5. Each 10KH PAL'" . has been designed to meet these specificetions after thermal equilibrium has been established. The circuit
Is In a te.t socket or mounted on a printed circuit board and transverse air flow greeter than 150 meters (500 feet) per minute
is maintained. Outputs are termlnatad through a 50-ohm resistor to - 2 V.

2-294

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 7526!i

TlEPAL 1OH16P8·6C
HIGH·PERFORMANCE IMPACT'MECL PAL® CIRCUIT
switching characteristics over recommended ranges of supply voltage and operating free..:air temperature
(see Notes 4 and 5)
PARAMETER

FROM
(INPUT!

TO
(OUTPUTI

tpd

I. I/O. or feedback

Q

TEST CONDITIONS

See Figures 1 and 2

tr
tf

MIN

C-SUFFIX
TYP 'MAX

4
1
1

2
0.7
0.7

UNIT

6

ns

2.2

ns
ns

2.2

NOTES: 4. The elgebraic convention. in which the more negative limit is designated as minimum and the less negative limit is designated
as maximum, is usec::t in this data sheet for logic voltage levels only. For other quantities. e.g., supply voltages and currents,
the normal magnitude convention is used.
5. Each 10KH PAL~ has been designed to meet these specifications after thermal equilibrium has been established. The circuit
is in a test sock.et or mounted on a printed circuit board and transverse air flow greater than 150 meters (500 feet) per minute
is maintained. Outputs are terminated through 8 50-ohm resistor to - 2 V.

programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive programmers.

PI

Complete programming specifications. algorithms. and ,the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5762.

PARAMETER MEASUREMENT INFORMATION
.L, 50%

INPUT

--ft

\..50;-- I

~tPHL

VIH
VIL

tPLHJ....I - - i , . - - + I - _ : t - - VOH
1
/50% I
)I. 50%
I
.
I
~
I
I
VOL
tpHL~
~tpLH
'.1':"::1 VOH
1
OUT -OF-PHASE
50%
\ 50%
OUTPUT
•
- VOL
IN-PHASE
OUTPUT

OUTPUT
WAVEFORM

801f
20%

i

T

I

I

I 1
t r ........

I+--

~---VOH
(80%1
I

1

I ,

120%1

V

OL

I 1

-.I

l+-tf

VOLTAGE WAVEFORMS
RISE TIME AND FALL TIME

VOLTAGE WAVEFORMS
PROPAGAT'ION DELAY TIMES

FIGURE 1. VOLTAGE WAVEFORMS

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-295

TlEPAL 10H16P8·6C
HIGH·PERFORMANCE IMPACTTMECL PAL® CIRCUIT
PARAMETER MEASUREMENT INFORMATION
2.00 V ± 0.01 V
251'F

r

0.1 "F

q

INPUT
UNDER
TEST

OUTPUT
UNDER
TEST

II
C

v~_ .. v{

I»
~
I»

or
VIL min + 2 V

tn

:r
CD
CD

~

A~

}

ALL
OTHER
INPUTS

en

OTHER {
OUTPUTS

VEE

r

':'

25 "F
0.1 "F

q

-3.20 V ± 0.01 V
NOTES: A. The offset voltage generator has the following characteristics: Pulse amplitude =; 800 mV poP, PRR s 1 MHz, tw = 500 ns,
tr : tf = , ns.
B. RT is a 50-0 terminator internal to the oscilloscope.
C. CL s 3 pF, include. fixture and .tray capacitance.
D. Coax has 50-0 impedance and the coax to oscilloscope channel A and to channel B must be of.equallengths.
E. All unused outputs are loaded with 50-0 ± 1% resistors to ground.
F. All unused inputs should be connected to either high or low levels consistent with the logic function required.
G. All fixture wire lengths or unterminated stubs should not exceed 6 mm (1/4 inchl.

FIGURE 2. LOAD CIRCUIT

2-296

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

TlEPAl10016PB·3C
HIGH·PERFORMANCE ExCL mpAL® CIRCUIT
03083, DECEMBER 1987

JTPACKAGE
(TOP VIEW)

•

ECl 100K PAL

•

High-Performance Operation
Propagation Delay ... 3 ns Max

•

lEE ... -220 mA Max

•

Replacement for 100K ECl logic

•

24-Pin, 300-Mil Package

•

Reliable Titanium-Tungsten Fuses

Vee
I
I
1/0

1/0

o

o
Veeo

Veeo

o

o

1/0

1/0

description
This ECl PAL device combines the ExCl'"
(Double Polysilicon Self-Aligned) process with
the proven titanium-tungsten fuses to provide
reliable, high-performance substitutes for
conventional ECl logic, Its easy programmability
allows for quick design of "custom" functions
with increased logic density. In addition, chip
carriers are available for further reduction in
board space,

tn
'CD
CD

u

___ uz>u __
4

The TIEPAl1 0016P8-3 is provided with output
polarity fuses. Each output remains active-high
when the fuse is intact and is active-low when
the fuse is blown.
The TIEPAl 10016P8-3 has 12 dedicated inputs,
four standard outputs, and four 110 ports. It
should be noted that with emitter-coupled
outputs, a high level overrides a low level.
Therefore, in order to use an 110 port as an input,
the related output must be forced to a low level
either through satisfying preprogrammed
equations or permanently by programming.

II...

FK PACKAGE
(TOPVIEWJ

3

.c

2 1 282726

5
6

25
24

7

23 Veeo

8

22

Ne

9

0

10

21
20

1/0

11

19

I

til

...

I/O

CIS
CIS

0

C

12 13 14 15 16 17 18

wu - - .!j!z
NC-No internal connection

The TIEPAl1 0016P8-3 is equipped with a security fuse. Once the security fuse is blown, additional
programming and verification cannot be performed. This prevents easy duplication of a design.
This device is characterized for operation from OOC to 85°C; this temperature range is designated by a
"C" suffix in the part number (TIEPAL10016P8-3CJT).

~

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w

a:

0-

tU
:::J
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oa:

ExCL is a trademark of Texas Instruments Incorporated.

0-

PAL is a registered trademark of Monolithic Memories Inc.

PRODUCT PREVIEW doc.........ntal. i.formatlo.
DR prad.... In the fonnalivl or dasig. ~~I" a'
dlvllopml.t. Charlotlrl,tl. dati In~ other

:=~cstl~:"Jg':t ~~::I=::I~rT:.~::~a:.,:;.:
products wit.out noti...

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

Copyright @ 1987. Texas Instruments Incorporated

2-297

TIEPAL10016P8·3C
HIGH·PERFORMANCE ExCLTMPAL® CIRCUIT
functional block diagram (positive logic)
8

&

32

i<

64

'"

-

-1

'V

8

I-- 'V
8

I-- 'V
12
4,

16X!>

16
16

8

'V

I-- 1"'8

'V

I-- II'\.,
8

•

o

....
I»
I»

I-- 'V
8

I-- 'V
8

I-- 'V
4

tn

:sCD

!

(II

2-298

TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

Vee

o

o
o

o
1/0

I/O
1/0
1/0

TlEPAl10016P8·3C
HIGH·PERFORMANCE ExeL'" PAL~ CIRCUIT
logic diagram (positive logicl
[28)(24)

Vcc

INPUT LINES
A

'0 ••• 4 ... 81 ••• 12' ••• 181 ...,20 ••• 24·••• 128,...'
[2)(1)

[27)(23}

~

......~

[3)(2}
PRODUCT
LINES

[28)(22}

0

~I

••
•
7

I/O

1/0

J

[4)(3)

[5)(4}

[25)(21}

PI

8

•

la,w
a:

Q.

t-

(..)
::::)

C

oa:
Q.

TEXAS ",

INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TeXAS 75265

2-301

TlEPAl10016P8·3C
HIGH·PERFORMANCE ExCL™ PAL® CIRCUIT
PARAMETER MEASUREMENT INFORMATION
2.00 V ± 0.01 V

r

25 "F
0.1 "F

q

-2.50 V ± 0.01 V
NOTES: A. The offset voltage generator has the following characteristics: Pulse amplitude = 800 mV P·P. PRR':s 1 MHz. tw = 600 ns.
t r =tf=lns.
8. RT is a 60·11 terminator internal to the oscilloscope.
C. CL :S 3 pF. includes fixture and stray capacitance.
D. Coax has 50·11 impedance and the coax to oscilloscope channel A and to channel 8 must be of equal lengths.
E. All unused outputs are loaded with 50·11 ± 1% resistors to ground.
F. All unused inputs should be connected to either high or low levels consistent with the logic function required.
G. All fixture wire lengths or unterminated stubs should not exceed 6 mm (1/4 inch).

"1:J

FIGURE 2. LOAD CIRCUIT

:IJ

o
C

c:

n

""'!!

"1:J

:IJ

m

<
iii
~

2·302

TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76285

TlEPAl10016P8·6C
HIGH·PERFORMANCE IMPACTTM ECl PAL® CIRCUIT
03082. DECEMBER 1987

JT PACKAGE

•

ECl 100K PAL

•

High·Performance Operation
Propagation Delay ... 6 ns Max

•

lEE ... -240 mA Max

•

Replacement for 100K ECl logic

•

24-Pin. 300-Mil Package

•

Reliable Titanium-Tungsten Fuses

(TOP VIEW)

Vee
I

110

110

o

o

Veeo

Veeo

o

o

110

1/0

description
This IMPACT'" ECl PAL device uses proven
titanium-tungsten fuses to provide reliable. highperformance substitutes for conventional ECl
logic. Its easy programmability allows for quick
design of "custom" functions and typically
results in a more compact board. Additionally.
chip carriers are available for further reduction
in board space.

(TOPVIEWI

U)

u

___ uz>u __
4

The TIEPAl1 0016P8-6 is provided with output
polarity fuses. Each output remains active-high
when the fuse is intact and is active-low when
the fuse is blown.
The TIEPAl1 0016P8-6 has 12 dedicated inputs.
four standard outputs. and four I/O ports. it
should be noted that with emitter-coupled
outputs. a high level overrides a low level.
Therefore. to use an I/O port as an input. the
related output must be forced to a low level
either by satisfying pre programmed equations or
by permanent programming.

fI
...

FK PACKAGE

3

2

CD
CD

.r:.

1 28 27 26

en

25
6

24

7

23

8

22

9

21

10

20

11

...caca

o

19
12 13 14 15 16 17 18

wu - - -

~z

NC-No internal connection

The TIEPAl1 0016P8-6 is equipped with a
security fuse. Once the security fuse is blown.
additional programming and verification cannot
be performed. This prevents easy duplication of
a design.

~
w

This device is characterized for operation from
OOC to 85°C.

:>w
a:
D..

I-

o

:J
C

oa:

IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories Inc.

PRODUCT PREVIEW da.umants .ontain inlarma!io.
a. praduell I. tha 'armati.. ar dllig. ~ha.. af
d8V~lopm.nt.

Characteristic data anil athar

~=~':::Ir~~t ~rar.:l~rT3i::'=::~:::
products without nltice.

D..
Copyright © 1987. Texas Instruments Incorporated

TEXAS .."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

2-303

TlEPAl10016P8·6C
HIGH·PERFORMANCE IMPACTTM ECl PAL® CIRCUIT
functional block diagra~ (positive logic)
8

&

32 X 64

'"

-1

r--

rv

~

'V

8
8

--

~

12
4.

16X!>

16
16

8

'V

.'\.

8

'V

--

I'\.

8

E

8
8

4

."
::ZJ

o
C

c:

o

""'"
."
::ZJ

m

<
-

~

2·304

'V

TEXAS ."

INSIRUMENlS
POST OFFICE BOX 655012 • DAlLAS, TEXAS 7&266

rv
rv

..- 'V

Vee

o
o

o

o
I/O
110
110
110

TlEPAl10016P8·6C
HIGH·PERFORMANCE IMPACTTM ECl PAL® CIRCUIT
logic diagram (positive logic)
[28)(24)
VCC
INPUT LINES
1\
10 ... 4 ... 8 ... 12 ... 16 ... 20 ... 24 ... 28 ...'

[2)(1)

[27)(23)

-t>t=
...

[3)(2)

PROOUCT
LINES

[26)(22)

"

0

•
•

125)(21)

•
7
14)(3)

A

1/0

J
I

II...

8

•

•
•
15

15)(4)
1/0

I
I

CI)

Q)
Q)

...

.c

16

CJ)

WP

•
•
•
23

124)(20)

0

C

24

o

•
•
•

C1tf

16)(51

...

«I
.«1

31
32

~

•
•
•
39

[21](18)

o

40

o

•
•
•
47

19](7)

48

•
•
55

•

120)(17)

-:j

I

110](8)
1/0

->w

"

•
•
•
63

las<
I

a:
c..

A

[12)(10)

119](16)
118](15)

111)(9)

113)(11 )

:::.

.A

...

I------I.A
~

NOTE: Pin numbers in ( ) are for the FK package; pin numbers in ( ) are for JT package.

TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

~

W

I

56

1/0

117)(14)
116)(13)

tO
::l
Q

o

a:
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2·305

TlEPAl1 00 16PB-6C
HIGH~PERFORMANCE

IMPACpM ECl PAL® CIRCUIT

absolute maximum ratings over operating free-air temperature range lunless otherwise noted)
Isee Note 1)
Supply voltage, VEE (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 0 V to - 6.5 V
Input voltage, VI (see Note 3) ............................................ 0 V to VEE
Output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 50 rnA
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 85°C
Storage temperature range ......................................... - 65°C to 1 50°C
NOTES: 1. Thes. ratings apply except for programming pins during a programming cycle.
2. All voltage values are with respect to VCC and VCCO, i.e., these pins are all assumed to be at 0 volts.
3. VI should never be more negative than VEE.

recommended operating conditions Isee Note 4)
VEE

MIN
-4.2

Supply voltage
VEE

VIH

High-level input voltage

VEE

C

VIL

en
::T

TA

Low-level input voltage

VEE
VEE

MAX

UNIT

-4·8.
-0.88

V

-0.88

V

=
=
=

-4.2 V
-4.6 V

-1.15
-1.165

-4.8 V
-4.2 V

-1.165

-0.88

-1.81

=
=

-4.5 V
-4,8 V

-1.81

-1.475
-1.475

-1.81

-1.49

0

85

VEE
VEE -

....t»t»

NOM
-4.5

Operating free-air temperature

V

°c

~ electrical characteristics over recommended supply voltage range at OOC to 85 °C Isee Notes 4 and 5)

....
U)

PARAMETER
VOH

TEST CONDITIONS

VEE
-4.2 V

VI .= VIHmin or VILmax

-4.6 V
-4.8 V

VI

VOL

=

VIHmin or VILmax
VI

IIH
IlL

=

MAX
-0.87

UNIT

-0.88
-0.88

V

-1.045

-4.2 V

-1.81

-1.595

-4.5 V

-1.81 ·-1.700

-1.61

-4.8 V

-1.81

-1.61

VIHmax

VI = VILmin
All inputs open

lEE

MIN
TYP
-1.03
-1.035 -0.955

V

220

~A

-240

pA
mA

0.5

switching characteristics over recommended ranges of supply voltage and operating free-air temperature
Isee Note 5)

""0

PARAMETER

FROM
(INPUT)

TO
IOUTPUT)

o

too

I, 1/0, or feedback

0, I/O

c:
o

tf

:D

tr

C

-f
""0

:D

m

TEST CONDITIONS

MIN

TYP

MAX

2

4

0.7

1

6
1.5

ns

See Figures 1 and 2

0.7

1

1.5

ns

UNIT

ns

NOTES: 4. The algebraic convention, in which the rnore negative limit is designated as minimum and the less negative limit is designated
as maximum, is used in this data sheet for logic voltage levels only. For other quantities, e.g., supply voltages and currents,
the normal magnitude convention is used.
5. Each 100KH PAL has been designed to meet these specifications after thermal equilibrium has been established. The circuit
is in a test socket or mounted on 8 printed circuit board and transverse air flow greater than 150 meters (500 feet) per minute
is maintained. Outputs are terminated t~rough a 50-ohm resistor to - 2 V.

S
m
~

2-306

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

TlEPAl1 00 16P8·6C
HIGH·PERFORMANCE IMPACTTM ECl PAL® CIRCUIT
PROGRAMMING INFORMATION
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
reasonably priced device programmers.
Complete programming specifications. algorithms and the latest information on firmware. software. and
hardware updates are available upon request. Information on programmers that are capable of programming
Texas Instruments programmable logic is also available. upon request. from the nearest TI sales office.
local authorized Texas Instruments distributor. or by calling Texas Instruments at (2141 997-5762.

PARAMETER MEASUREMENT INFORMATION

~,"5-0-%---,;-.; -

INPUT

~

~

tPLH 1_
IN-PHASE
I
OUTPUT
I
tpHL

VIH

~tPHL

VIL

I.t--VOH

-j

/50% I

I
I

•

+--...

OUT -OF-PHASE
OUTPUT

-

I

~ 50%

'\::.:.

VOL

I4--*-tpLH

\ 1 50%

F'
50%

_

OUTPUT
WAVEFORM

801:
I

20%

I

vOH
VOL

I

I I
t, ......

I+-

(80%)
I
II (20%) VOL

"1\:----VOH

I

I I

-+I

I+-tf

VOLTAGE WAVEFORMS
RISE TIME AND FALL TIME

VOLTAGE WAVEFORM$
PROPAGATION DELAY TIMES

FIGURE 1. VOLTAGE WAVEFORMS

II...
rn

Q)
Q)

.c

U)

...asas

C

3:
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~

a::

a.

tO

:::)

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oa::
a.

TEXAS ."

INSlRUMENTS
POST OFFICE BOX 86&012 • DALLAS, TEXAS 75265

2-307

TIEPAl10018P8·6C
HIGH·PERFORMANCE IMPACTTM ECl PAl® CIRCUIT
PARAMETER MEASUREMENT INFORMATION
2.00 V :I: 0.01 V

0.1 "F

q

INPUT
UNDER
TEST

II
C

v~_., "{

CD
CD

1+

en

or

::::r

VIL min

CD
CD

1+
U)

+2V

OUTPUT
UNDER
TEST

} ~{
ALL
OTHER
INPUTS

OTHER
OUTPUTS

VEE

r

-=

25 "F
0.1 "F

q

-2.50 V :I: 0.01 V
NOTES: A. The offset voltage generator has the following characteristics: Pulse amplitude = 800 mV poP, PRR :s 1 MHz, tw = 500 ns,
t r =tf=lns.
B. RT is a 50-0 teminator internal to the oscilloscopa.
C. CL :S 3 pF, includes fixture and stray capacitencea.
D. Coax has 50-0 impedance and the coax to oscilloscopa channel A and to channel B must be of equal lengths.
E. All unused outputs are loaded with 50-0 :I: 1 % resistors to ground.
F. All unused input should be connected to either high or low levels consistent with the logic function required.
G. All fixture wire lengths or unterminated stubs should not exceed 6 mm (1/4 inch).

"'0

::0

FIGURE 2. LOAD CIRCUIT

o
C

c:

n

-I
"'0

::0

m

-<
~

2-308

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 15286

TIFPLA839M, TIFPLA839C
TIFPLA840M, TIFPLA840C
14 x 32 x 6 FIELD·PROGRAMMABLE LOGIC ARRAYS
JUNE 1984- REVISED DECEMBER

•

Input-to-Output Propagation Delay ...
10 ns Typical

•

24-Pin, 300-mil Slim Line Packages

•

Power Dissipation ... 650 mW Typical

•

Programmable Output Polarity

LOGIC FUNCTION

I{I) = PO + Pl ... P31 lor polarity link intact
III) = PO' Pi' ...
lor polarity link open
where PO through P31 are product terms

·m

TIFPLA839M. TIFPLA840M .•. JT PACKAGE
TIFPLA839C. TIFPLA840C .•• JT OR NT PACKAGE
(TOPVIEWI

description

OEl

The 'FPLA839 (3-state outputs) and the 'FPLA840
(open-collector outputs) are TTL field-programmable
logic arrays containing 32 product terms (AND terms)
and six sum terms (OR terms). Each of the sum-ofproducts output functions can be programmed either
high true or low true. The true condition of each output
function is activated by the programmed logical
minterms of 14 input variables. The outputs are
controlled by two chip-enable pins to allow output
inhibit and expansion of terms.
These devices provide high-speed data-path logic
replacement where several conventional SSI functions
can be designed into a single package.
The 'FPLA839M and 'FPLA840M are characterized for
operation over the full military temperature range of
- 55·e to 125 ·e. The 'FPLA83ge and 'FPLA840e
are characterized for operation from o·e to 70 ·e.

Vee
I

I
I

I

0
0
0

0
0
0

II
:l
CD
CD

.c

0E2

GND

en
ca
i

TlFPLA839M. TIFPLA840M ... FH OR FK PACKAGE
TIFPLA839C, TIFPLA840C .•. FN PACKAGE

C

(TOPVIEWI
~

u

__ I~~~-4 3 2 1 282726
25
24
23
22
21
20
19
12131415161718

5
6
7
8
9
10
11

Pin assignments in operating mode (pin 1 is less positive than VIHHI

Copyright @ 1984, Texas Instruments Incorporated

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 866012 • DALLAS, TEXAS 76286

2-309

TlFPLA839M. TIFPLA839C
TlFPLA840M. TIFPLA840C
14 x 32 x 6 FIELD·PROGRAMMABLE LOGIC ARRAYS
.functional block diagram (positive logic)
0E1---

o

&
28X32

o

o

32

14

o

II

o
o

C

m
m

~

~

o

-denotes fused inputs.

::r

tFPLA839 has 31tate ('V) outputs; FPLA840 has open.... nector (0) outputs.

CD

aen

absolute maximum ratings

Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Off-state output voltage (see Note 1) ......................................... " 5.5 V
Operating free-air temperature range: 'FPLA839M, 'FPLA840M . . . . . . . . . . . . .. - 55 °e to 125°C
'FPLA839C, 'FPLA840e .................. ooe to 70 0 e
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 °e to 150 0 e
NOTE 1: These ratings apply except for programming pins during a programming cycle.

2·310

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 855012 .. DALLAS. TEXAS 75265

TIFPLA839M, TlFPLA839C
TIFPLA840M, TIFPLA840C
14 x 32 x 6 FIELD·PROGRAMMABLE LOGIC ARRAYS
LOGIC DIAGRAM

(81

"::lL

0
1

(71

...x

2
3

(61

4
5

(51 ')(.

6
7

(41 ')(.

8
9

(3)

10
11

(21 ....

...x

12
13

(23)')(.

14
15

(22) ....

16
17

L/I:
(21) A

18
19

(20) "

20
21

(19)

22
23

-----vI:
---L)l
(18)

II

24
25

;>t

(17)

26
27

lJlJl

Dp

D¥
~
D¥
o¥
D¥

~

o

~o
~ o

,J!!!. o
~

o

33

I'M(TIU')'I""""MO'I
~ U') 'I"""

00

U') ....

co-.:t

_~2mcncnQ)C:O

OEl
OE2

LnIl"""r...Mcnlt) ........

C;;~~;:::ro(g«iC;

MClLnIl"""I'MO)U')

1l\f51t~~r;;::l~

~ .... '" en LIl ~ .... '"
..... MOlDMOlDM

NNNII""''1''''"'-

1

1093

~o

)

~

(1 )
(13)

.
TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2-311

TIFPLA839M, TlFPlA839C
TlFPlA840M, TIFPlA840C
14 x 32 x 6FIElD·PROGRAMMABlE lOGIC ARRAYS
recommended operating conditions
M SUFFIX
Supply voltage, Vee

MIN

NOM

4.5

5

High-level input voltage, VIH

C SUFFIX
MAX
5.5

2

Low-level input voltage, VIL

I 'FPLA840
I 'FPLA839

High-level output voltage, VOH
High-level output current, IOH
Low-level output current, IOL

MIN

NOM

MAX

4.75
2

5

5.25
0.8

5.5

5.5
-3.2

-2
-55

125

.V
V

0.8

12

Operating free-air temperature, TA

UNIT

0

,

V
V

24

rnA
rnA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise' noted)

E
C

....m

m

CJ)

:r
(1)

M SUFFIX

TEST CONDITIONS t

PARAMETER

MIN

Vee = MIN,

II = -18 rnA

'FPLA840

Vee =,MIN,

VOH = 5.5 V

0.1

VOH 'FPLA839

Vee - MIN,

IOH - MAX

VOL
II

Vee - MIN,

IIH

Vee = MAX,
Vee - MAX,

IOL - MAX
VI - 5.5 V
VI = 2.7 V
VI - 0.4 V

VIK
IOH

Vee - MAX,

IlL

2.4

3.2
0.25

MIN

TVP*

MAX
-1.5
0.1

2.4
0.5

3
0.37

IO§

Vee = MAX,

Vo = 2.25 V

IOZH

Vee - MAX,

Vo - 2.7 V

(I)

IOZL

Vee - MAX,

Vo - 0.4 V

lee

Vee - MAX,
Oe inputs at VIH

VI = 0 V,

-30

V
rnA
V
V

0.1

0.1

rnA

20

20
0.5

rnA

-112

rnA

20
-20

~

180

rnA

-112

-30

20
-20
130

UNIT

0.5

0.5

(1)

....

C SUFFIX
MAX
-1.5

TVP*

190

130

~A

~A

"FPLA839 switching characteristics
PARAMETER
tpd
ten
tdis

FROM
Input

TO

TEST CONDITIONS

M SUFFIX
TVP; MAX

RL = 500 to GND,

Output

Output

Pin 13

MIN

C SUFFIX
TVP; MAX

10

25

10

20

RL 1 - 500 to 7 V,

10

25

10

20

RL = 500 to GND,
eL = 50 pF to GND

8

20

8

15

CL = 50 pF to GND

Pin 1
or

MIN

UNIT
ns

ns

'FPLA840 switching characteristics
PARAMETER
tpd

FROM
Input

TO

TEST CONDITIONS

Output
o

ten
tdis

Pin 1
or

Output

Pin 13

MIN

M SUFFIX
TVP;
MAX

MIN

C SUFFIX
TVP; MAX

RL - 500 to Vee..
eL = 50 pF to GND

10

30

10

25

RL1 - 500 to 7 V,

10

25

10

20

8

15

RL = 500 to GND,
eL = 50 pF to GND

Vee""

5 V, TA

20 '

= 25°C.

§The output conditions have been chosen to produce a current that closely approximates one half

2-312

ns

ns
8

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

iAII typical values are at

UNIT

?f the true

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

short-circuit current, lOS'

TIFPLA839M, TIFPLA839C
TIFPLA840M, TIFPLA840C
14 x 32 x 6 FIELD·PROGRAMMABLE LOGIC ARRAYS
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997·5762.

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TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

2·313

•

2-314

Application Reports

I

3-1

Contents
Designing with TI Field-Programmable Logic ........................
Hard Array Logic (HAL®) ......................................
A Designer's Guide to the TIBPSG507 ............................
System Solutions for Static Column Decode ........................

3-2

Page
3-3
3-25
3-31,
3-81

Designing with
Texas Instruments
Field-Programmable Logic
Robert K. Breuninger and Loren E. Schiele
Contributors
Bob Gruebel, Renee Tanaka, Jim Ptasinski

I

."

TEXAS

INSTRUMENTS
3-3

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes in the
devices or the device specifications identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
information being relied upon by the customer is current.
TI warrants performance of its semiconductor products, including SNJ
and SMJ devices, to current specifications in accordance with TI's
standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems such testing necessary to support this
warranty. Unless mandated by government requirements, specific
testing of all parameters of each device is not necessarily performed.
In the absence of written agreement to the contrary, TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third parties by or ariSing from
use of semiconductor devices described herein. Nor does TI warrant
or represent that any license, either express or implied, is granted
under any patent right, copyright, or other intellectual property right
of TI covering or relating to any combination, machine, or process in
which such semiconductor devices might be or are used.

Copyright © 1984, Texas Instruments Incorporated

3-4

Contents
Title

Page

INTRODUCTION ............................................................................ .

3-7

FIELD-PROGRAMMABLE LOGIC ADVANTAGES ............................................... .

3-7

PAL

'0

"2n'
....m
0'
~

::a
CD

..

'0
0

....
tI)

3-6

11
12
13
14
15
16
17
18
19
20
21

Title
Basic Symbology ........................................... : .... '. . . . . . . . . . . . . . . . . . . . . . .
Basic Symbology Example ............................... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PROM Architecture ....................................................................
PAL Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FPLA Architecture . .. . . . . . . .. . .. . .. . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . .. . . . . . . .. . . . .
TmPLA16L8 Logic Diagram........ ......................... ...........................
TmPALI6R8 Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polarity Selection . '. . . . .. . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . .. . .. . .. .. .
Input Register Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Latch Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAL Process Flow Diagram....... ......... ..... .......... ..............................
Counter Implementation with Standard Logic..................... ..........................
TmPALI6R4 Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .
Karnaugh Map for CLKOUT ................ :...........................................
Karnaugh Map for CLKOUT .............................................................
Karnaugh Maps ....................................................................... :
Programmed TmPALI6R4 .................................. '............................
Pin ID and Logic Equations................................................. ............
Fuse Map ................................................. '. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source File for ABEL .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABEL Output Documentation................................................ ............

Page
3-7
3-7
.3-8
3-8
3-9
3-10
3-11
3-12
3-12
3-13
3-13
3-14
3-15
3-16
3-16
3-17
3-18
3-19
3-20
3-22
3-23

List of Tables
Table

1
2
3
4

Title
Clock Selection ............................................................. " . . . .. . . . . . .
Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Truth Table ........................... ,..... ................ ........... .................
Truth Table. . . . . . . . . .. . . . . . . . . . .. .. . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . .. . .

Page
3-13
3-14
3-16
3-17

INTRODUCTION
The purpose of this application report is to provide the
first time user of field-programmable logic with a basic
understanding of this new and powerful technology. The
term «Field-Programmable Logic" refers to any device
supplied with an uncommitted logic array, which the user
programs to his own specific function. The most common,
and widely known field-programmable logic family is the
PROM, or Programmable Read-Only Memory. Relatively
new entries into this expanding family of devices are the
PAL® and FPLA. This report will primarily concentrate
on the PAL family of programmable logic.
FIELD-PROGRAMMABLE LOGIC ADVANTAGES
Field-programmable logic offers many advantages to
the system designer who presently is using several
standard catalog SSI and MSI functions. Listed below are
just a few of the benefits which are achievable when using
programmable logic.
1. Package Count Reduction: typically, 3 to 6
MSIISSI functions can be replaced with one
PAL or FPLA.
2. PC Board Area Reduced: Fewer devices
consume less PC board space. This results in
lower PC board cost.
3. Circuit Flexibility: Programmability allows for
minor circuit changes without changing PC
boards.
4. Improved Reliability: With fewer PC
interconnects, overall system reliability
increases.
5. Shorter Design Cycle: When. compared with
standard-cell or gate-array approaches,
custom functions can be implemented much
more quickly.
The PAL and FPLA, will fill the gap between
standard logic and large scale integration. The versati'lity
of these devices provide a very powerful tool for the·
system designer.

An X represents an intact fuse. This makes that input,
part of the product term. No X represents a blown fuse.
This means that input will not be part of the product term
(in Figure 1, input B is not part of the product term). A
dot at the intersection of any line represents a hard wire
connection.
INPUT TERMS
ABC

PRODUCT
LINE

~

TIT L...I

OUTPUT
F = A'C

Figure 1. Basic Symbology
In Figure 2, we will extend the symbology to develop
a simple 2-input programmable AND array feeding an OR
gate. Notice that buffers have been· added to the inputs,
which provide both true and complement outputs to the
product lines. The intersection of the input terms form a
4 x 3 programmable AND array. From the above
symbology, we can see that the output of the OR gate is
programmed to the following equation, AB+AB. Note
that the bottom AND gate has an X marked inside the
gate symbol. This means that all fuses are left intact, which
results in that product line not having any effect on the
sum term. In other words, the output of the AND gate will
be a logic O. When all the fuses are bluwn un a product line,
the output uf the AND gate will always be a lugic I. This has
the effect uf lucking up the uutput uf the OR gate to. a lugic
level I.

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Q.

-

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Cl

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tl

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(lBI Q
v

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tr:l
(171
Q
v

~

r.J

(161

"";:l

(151 Q

Cl

(3} 15
.;>\.

16

••

I-----.

II-/-

•
•

·

-

(4} 23

Cl

.A

24

·•••
•

/-

v

Q

Cl

(5} 31
32

••
•

D-

••
•

I-

Cl

(6} 39
40

•
••
•

··

tl

v

f-D-

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...0

~

"";:l

~

~ (131 Q

(141

v

Q

~

4B

••
••
••

..
0

v

Cl

(B} 55
56

·•••
·
..

Q)

"

---,

/-

Q.

a::
c

Cl

(71 47

I...

p-~8''''

ca

"~

C.
Q.
oCt

Q

Cl

(B1 63

.

4-!-1 OE

Figure 7. TIBPALl6R8 Logic Diagram

3-11

I

function. Listed below are some of the manufacturers of
this programming equipment.'
Citel
Storey Systems
DATA 1/0
Structured'Design
Digelec
Sunrise Electronics
Kontron
Valley Data Science
Wavetec
Varix
Stag Micro Systems

ENABLE

FIgure 8. Polarity Selection
Figure 10 shows an example of this type of input. If the
fuse is left intact, data enters while the control input is
high. When the control input is low, the data that was
. present when the control input went low will be saved. If
the fuse is blown, the latch becomes permanently
transparent, and is equivalent to a normal input buffer.

PROGRAMMING
Notice in Figure 7, that the product and inplit lines
are numbered. This allows any specific fuse to be located
anywhere in the fuse matrix. When the device is in the
programming mode (as defined in the device data sheet),
the individual product and input lines can be selected. The
fuse .at the intersection of these lines, can then be blown
(programmed) with the defined programming pulse.
Fortunately, the user seldom has to get involved with these
actual details of programming, because there exist several
commercially available programmers which handle this

At Texas Instruments, we have coordinated with
DATA 1/0 using their Model 19 for device
characterization. Currently, DATA 1/0, Sunrise, and
Structured Design have been certified by Texas
Instruments. Other programmers are now in the
certification process. For a current list of certified
programmers, please contact your local TI sales
representative.
It should now be obvious to the reader, that the
actual blowing of the fuses is not a problem. Instead, the
real question is what fuses need to be blown to generate a
particular function. Fortunately, this problem has also
been greatly simplified by recent advances in computer
software.
DATA I/O has developed a software package called
ABEL"'. Also available is CUPL", from Assisted
Technology. Both have been designed to be compatible
with several different types of programmers. Both of these
software packages greatly extend the capabilities of the
original PALASM'· program, and both can be run on
most professional computers.
Before proceeding to a design example, it would be
instructive to look at the simplified process flow of a PAL
(Figure 11). .This should help give the reader a better
understanding of the basic steps necessary to generate a
working device.
DESIGN EXAMPLE
The easiest way to demonstrate the unique
capabilities of the PAL is through a .design example. It is

REGISTER FUSE INTACT
D·TYPE REGISTER
FUNCTION TABLE

Q

CLOCK

D

0

t

H

H

L

t

L

L

H

L

X

00 li.,

00· THE STATE OF 0 BEFORE CLOCK t

Figure 9. Input Register Selection
ABEL ~ is a trademark of DATA 1/0.
CUPL ,. Is a trademark of Assisted Technology, Inc,
PALASM" is a trademark of Monolithic Memories Inc ..

3-12

LATCH FUSE INTACT
TRANSPARENT LATCH
FUNCTION TABLE

OC2
lC2

20
MO (INTACT)
Ml (BLOWN)

ENABLE

0

0

fi

H

L

L

H

H

H

H

L

L

X

00

QO

00 = THE

LEVEL OF Q BEFORE ENABLE.

Figure 10. Input Latch Selection
Table 1. Clock Selection
SELl

o
o

SELO

o
1

o
1

OUTPUT

CLKA
ClKB
CLKC
ClKD

As can be seen, three MSI functions are required. The
'LS162 is used to generate the 4-bit counter while the clock
selection is handled by the 'LS253. The 'LS688 is an 8-bit
comparator which is used for selecting either the binary or
decade count. In this example, only five of the eight
comparator inputs are used. Four are used for comparing
the counter outputs, while the other is used for the BD
input. The comparator is hard-wired to go low whenever
the BD input is low and the counter output is "9". The
P =Q output is then fed back to the synchronous clear
input on the 'LS162. This will reset the counter to zero
whenever this condition occurs.

It is desired to generate a 4-bit binary counter which
is fed by one of four clocks. There are two lines available
for selecting the clocks, SELl and SELO. Table 1 shows the
required input for the selection of the clocks. In addition,
it is desired that the counter be able to switch from binary
to decade count. This feature is controlled by an input
called BD. When BD is high, the counter should count in
binary. When low, the counter should count in decade.
Figure 12 shows how this example could be
implemented if standard data book functions were used.

o

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Figure 11. PAL Process Flow Diagram

EXAMPLE REQUIREMENTS

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PAL IMPLEMENTATION

hoped that through this el\ample the reader will gain the
basic understanding needed when applying the PAL in his
own application. In some cases, this goal may only be to
reduce existing logic, but the overall approach will be the
same.

I

As stated before, the problem in programming a
PAL is not in blowing the fuses, but rather what fuses need
to be blown to generate a particular function. Fortunately,
this problem has been grl)atly simplified by computer
software, but before we examine these techniques, it is
beneficial to explore the methods used in generating the
logic equations. This will help develop an understanding,
and appreciation for these advanced software packages.
From digital logic theory, we know that most any
type of logic can be implemented in either AND-ORINVERT or AND-NOR form. This is the basic concept
used in the PAL and FPLA. This allows classical
techniques, such as Karnaugh Mapsl to be used in
generating specific logic functions. As with the separate
component example above, it is easier to break it into
separate functions. The first one that we will look at is the
clock selector, but remember that the overall goal will be
to reduce this design example into one PAL.

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as

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Q.



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c:;'
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:XI
CD

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0

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en

3-14

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

SElO ClKA ClKB ClKC ClKO ClKOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0
0

0
0
0
1

0

0

0
0
0

0

SEll

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
1

0

0

0

1

0
1

1

1

0
0

0
0

0

0

0

0
0

0

0
0
1

0

0

0
0
0

0

0
0
0
0

SElO ClKA ClKB ClKC ClKO ClKOUT
0
0
0
0
0
0
0
0

0
0

1

1

0

0
0

1

0
0

0
1

1

0
0

0

0
0

1

0
0
0

0
0
0
0

1

0

0

0

0

0

0

0

0

0

0
1

0

1

0
0

0
0

0

0

0

0

0
0
0

0

1

0

1
1

0
0

0
0

0
0
0
0
0

1

0

0

0

0
0

0
0

0

0

1

0

0

0

0

1

1

0
·0

0
1

0
0
0
0

1

1

0

0

0

0

0

1

0
1

0

0

0

1

0

0
0

0
1

1

1

0

0

elK (1)

~

p

.

INPUT lINES

Rl~,!>~er. 0

4

8

12

16

20

24

28

31

0

·••••

>->--

•

J...

(19)

1/0

1

(2)~!~b-

8

••
••
••

~

J

(18)

1/0

~

(3) 15

1

16

·••••

~

>--P"

•

ihJ,; i? ""

a

e1

(4) 23

x.
>--

24

·
·
•
••
•

I--

~

r.:J.v

(16)

a

~

~

(15)

a

~~tbl

~

r-

I--

:>-

e1

(5) 31
':>[

32

I--

••
••

·
·•••

I--

::>-

...

e1

(6) 39

40

fI)

1::
0

)--

••

-

(7)~47

I

I

Q.

(14)

~

Q)

Q

a:
C
0

C1

',j:

48

•
••
•

·

j

·
·•••
·

(8) 55

66

r-

I-'

J

ca

(13)

I

1

,~

1/0

Q.
Q.

-

·

>-

01

A

ii,

32

••
••

rr
02

40

••
••
•

·
48

"::1-oo

·

~

Q2

(131

NC

1

(81 56

~

••

~

••
••

(91~

1
v

Figure 17. Programmed TlBPAL16R4

3-18

(14

v

....56

BO

rJv

1

••
•
••

ClR

(151

C1

m 47

CD

tJ;
>tJ;

rJ...

C1

39

:ZJ

~

16 1Q1
t:r1.J
v

)--

·
ClK D

In

C1

(51 31
ClKB

::s

tJ;S

DO

••
••
•

"'2.5"

NC

C1

(41 23
CLKA -'-'
24

l> ClKC (61

(181

v

ClKOUT

1

··••

....m
0"

1

(31 15
16

I

I

(191

(121

1'-4-"

BOOUT

It is now probably obvious to the reader, that
inserting the logic equations into the logic diagram is a
tedious operation. Fortunately, a computer program
called PALASM will perform this task automatically. All
that is required is telling the program which device has
been selected, and defining the input and output pins with

their appropriate logic equations (Figure 18). The program
will then generate a fuse map (Figure 19) for the device
selected. Notice that the fuse map looks very similar to the
block diagram (Figure 17) which we have just completed
by hand. In addition, this information can now be down
loaded into the selected device programmer.

DEVICE TYPE 16R4

PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN

LIST NAMES =
NUMBER
1
NUMBER
2
NU~IBER
3
NUMBER = 4
NUMBER
5
NUMBER
6
NUMBER
7
NIJr1SER = €<
NU~IBER

9
NUMBER = 10
NU~lBER

NUMBER
NUMBER
NUMBER
NU~lBER

11
12
13
14
IS
16

Nur1BER
NUMBER
NUI1BER

17
l.B

Nl.I~lBER

= 19

NUMBER

20

PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN

NAME
NAME
NAME
NAME
NAME
NAr1E
NAME
NAr1E

CLK

= SELO
SEll
= CLKA
CLKB
= CLKC

CLKD
'CLR
BD
GND
NAME
NAME
IOE
NAME
BDOUT
NAME = NC
Q3
NAME
Q2
NAME
Q1
NAME
QO
NAME
NAI1E
NC
NAME
CLKOUT
NAME
VCC
NA~IE

EXPRESSIONS AND DESCRIPTION =
EXPRESSIONC I] =
ICLKOUT=/SEL1*/SELO*/CLKA +/SELl*SEI.O*/CL.KIl +SELl*/SELO*/CLKC +SELl*SELO*/CLKD

EXPRESSIONC 2] =
IQO=/CLR +QO

I
II)

~

o

c.

EXPRESSIONC 3] =
IQI=/CLR +/Q1*/QO +Q1*QO

Q)

a:

c
o

~

EXPRESSIONI 4] =
IQ2=/CLR +/Q2*/QI +Q2*QI*QO +/Q2*/QO

CIS
.~

Q.
EXPRESSIONI 3] =
IQ3=/CI.R +/Q3*/Q2 +/Q3*/QI

+/(~3*/Q(I

+Q3*Q2*Q1*QO

c.

c:(

EXPRESSIONI 6J =
IBDOUT~/BD*Q3*/Q2*/QI*QO

Figure 18. Pin ID and Logic Equations

3-19

0000 0000 0011 1111 1111 2222 2222 2233
0123 4567 8901 2343 6789 0123 4:;6'7 8901
ICLKOUT

-x-- -x-- -X--

x--- -x--

-x--

-x--

x---

XXXX
XXXX
xxx X
XXXX
XXX X
XXXX
XXX X
XXXX

XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX

XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX

XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXX X
XXXX

XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX

xxx X
XXXX
XXX X
XXXX
XXXX
XXXX
XXXX
XXXX

XXXX
XXXX
XXXX
XXXX
XXXX
XXXX

--XXXXX
XXXX
XXXX
XXXX
XXX X
XXXX

XXXX
XXXX
XXX X
XXXX
XXXX
XXXX

XXXX
XXXX
XXXX
XXX X
XXXX
XXXX

XXXX
XXXX
XXXX
XXXX
XXXX
XXXX

-X--

X--- x---X-XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
XXXX xxx x xxx x XXXX XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXXX
XXXX

XXXX
XXXX
XXX X
XXX X
XXXX
XXXX
XXXX
XXX X

o -

I
2
3
4
5
6
7

'-

ISEL1*/SELO*/CLKA+
ISELI*SELO*/CLKB+
SEL1*/SELO*/CLKC+
SEL1*SELO*/CLKD

8 9 10 11 -

12
13
14
15

-

XXXX
XXXX
XXXX
XXXX
XXXX
XXXX

16
17
18
19
20
21
22
23

- ICLR+
- QO
-

XXXX
XXXX
XXXX
XXXX
XXXX

24
23
26
27
28
29
30
31

- ICLR+
- IQI*/QO+
- m*QO
-

XXXX
XXXX
XXXX
XXX X

32
33
34
33
36
37
38
39

-

IQO

-X-XXXX
XXXX
XXXX
XXXX
XXXX
XXXX

XXXX
XXXX,
XXXX
XXXX
XXXX
XXXX

IQI

---x

I
-,
..

l>

"0

'2.
n
&»

0'

::s

::a

CD

'"g

0

:::I.
0

XXXX
XXXX
XXXX
XXXX
XXXX
/Q2

XXXX
XXXX
XXXX
XXXX
XXXX

--XXXXX
XXX X
XXX X
XXXX
XXXX

XXXX
XXXX
XXXX
XXXX

--X---x
XXXX
XXXX
XXXX
XXXX

-X----x
--XXXXX
XXXX
XXXX
XXXX
XXXX

XXXX
XXXX
XXXX
XXXX
XXXX

'XXXX
XXXX
XXXX
XXX X
XXXX

XXXX
XXXX
XXXX
XXXX
XXXX
-X--

XXXX
XXXX
XXXX
XXXX

---X ---X
--X- --X-~-X

XXXX
XXXX
XXXX
XXXX

XXXX
XXXX
XXXX
XXX X

XXXX
XXXX
XXX X
XXXX

XXXX
XXXX
XXXX
XXXX

ICLR+
/Q2*/Q1+
Q2*Ql*QO+
/Q2*/QO

1&3

-X-40
---X ---X
41
42
---X
---X
---X
43
--X- --x- --X- --X44
XXXX xxxx XXXX XXXX XXXX XXXX XXXX XXXX 45
XXXX XXXX XXXX XXXX XXX X XXXX XXXX XXXX 46
XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 47

- ICLR+
- IQ3*/Q2+
/Q3*/&I+
- IQ3*IQO+
- Q3*Q2*QI*&0

XXXX XXXX XXXX
XXXX XXXX XXXX
xxxx xxxx XXXX
XXXX XXXX XXXX
XXXX XXXX XXXX
XXXX XXXX XXXX
XXXX XXXX XXXX
XXXX XXX X XXXX

-

--..:X

XXXX
XXXX
XXX X
XXXX
XXXX
XXXX
XXXX
XXXX

XXXX XXXX XXXX XXXX 48
XXXX XXXX XXXX XXX X 49
XXXX 50
XXXX XXXX XXXX XXXX 51
XXXX XXXX XXXX XXXX 52
XXXX XXX X XXXX Xxx X 53
XXXX XXXX XXXX XXXX 54
XXXX XXXX XXXX XXXX 55

xxxx xxxx xxxx

'0

-

-

-

IBDOLIT

XXXX
XXXX
XXXX
XXXX
XXXX
XXX X

XXXX
XXX X
XXXX
XXXX
XXXX
XXXX

--XXXX X
XXXX
XXXX
XXX X
XXXX
XXXX

---X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX

---X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX

--XXXXX
XXXX
XXXX
XXXX
XXXX
XXXX

XXXX
XXXX
XXXX
XXXX
XXXX
XXXX

-x-XXXX
XXXX
XXXX
XXXX
XXXX
XXXX

Figure 19. Fuse Map
3-20

56
57
58
59
60
61
62
63

- /BD*Q3*/Q2*/QI *QO
-

ADVANCED SOFTWARE
PALASM, while extremely useful in generating the
fuse map, does little to help formulate the logic equations.
This is what the new software packages such as ABEL and
CUPL address. They not only generate the fuse map, but
they also help in developing the logic equations. In most
cases, they can generate the logic equations from simply
providing the program with either a truth table or state
diagram. In addition, they can test the logic equations
against a set of test vectors. This helps ensure the designer
gets the desired function.
These are only a few of the features available on
these new advanced software packages. We recommend
that the reader contact tbe specific manufacturers
themselves to obtain the latest information available. For
your convenience, at the end of this application note we
have included the addresses and phone numbers for many
of these programming and software companies.
As an example, we will approach our previous
design utilizing DATA I/O's ABEL packlige. The purpose
here is not to teach the reader how to· use ABEL, but
rather to give them a basic overview of this powerful
software package. Figure 20 shows the source file required
by ABEL. Note that the 4-bit counter has been described
with a state diagram table. When the ABEL program is
complied, the logic equations will be generated from this.
The equations for CLK OUT and BD OUT have been

given in their final form to demonstrate how ABEL would
handle these. Also notice that test vectors are included for
,checking the logic equations. This is especially important
when only the logic equations has been given.
Figure 21 shows some of the output documentation
generated by the program. Notice that the equations
generated for the counter, match the the ones generated
by the Karnaugh maps. A pinout for the device has also
been generated and displayed. The fuse map for the
device has not been shown, but looks very similar to the
one in Figure 19. As with the PALASM program, this
information can be down loaded into the device
programmer.

PERFORMANCE
Up to this point, nothing has been said about the
performance of these devices. The Standard High Speed
PAL (indicated by an ';.\" after the device number) offered
by TI has a maximum propagation of 25 ns from input to
output, and 35 MHz fmax . Also available is a new, higher
speed family of devices called TIBPALs. These devices are
functionally equivalent with the current family and offer a
maximum pro\Jagation delay of 15 ns from input to output.
They are also rated at 50 MHz fmax . The higher speeds on
these devices make them compalible with most high-speed
logic families. This allows them to be designed into more
critical speed path applications.

3-21

mod~ile BO .. COUNT Tlan "-r2'
"4-bit

titl~

Iel
pin

bin~ry/d~cade

count~r

d\!'vi r:e "Pl bR4";

~ssi~nm@nts

a~d

cQnstant do .. larations

CLK_.rN>SEL(),SEL1~CLKA

1~·2.3.4=

CLKB.CU

0 THEN
0 THEN
0 THEN
0 THEN
0 THEN
0 THEN
0 THEN
0 THEN
0 THEN
0 THEN
0 THEN
0 THEN
0 THEN
0 THEN
0 THEN
0 THEN

SO
SO
SO
SO
SO
SO
SO
SO
50
SO
SO
SO
SO
SO
SO
SO

ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE
ELSE

Sl;
S2;
$3;
S4,
55;
S6;
S7,
58,
S9;
510:
511,
S12,
S13;
SI4,
SIS;
SO;

.... clock selector""
te-st_vectors
([CLKA, CLKB, CLKe, CLKD, SELl, SELO] -:> CLK_OUn
L
X
X
X
L,
r
L J -:>
L,
X
r H
X
X
L,
L ] ->
H;
X
X
X
r
L
L,
H ] ->
L;
[ X
H
X
L,
H J -:>
H.
L· ] ->
[ X
X
L
X
H,
L,
[ X
H
H,
X
X
H,
L J -:>
[
X
X
L
H,
H J -:>
L;
[
X
X
H
H,
H ] -:>
H;
te-st_vect"ors

, rCLK •. IN,
r CK,
[
CK,
(
CK,
[

CK~

[

CK,
CK,
CK,
CK,
CK,
CK,
CK,
CK,
CK,
CK,
CK,
CO<,
CK,

r
[

r
X,
.. nd BD_COUNT

"counter""
OE, CLR, BD_IN)
X J
L
L,
L
X J
H.
L
H,
X
L
H,
X
H,
L
L
H,
H,
L
H,
L
X
L
H,
L
H,
L
L
H,
X
H,
X
L
H,
X
L
L
H,
X
L
H,
X
L
H,
H
L
H,
X
H
X,
X

-> roUTPUT, BD_OUTl)

->
->
-~

-:>

->
-:>
-:>

->

-:>
-:>

->

-:>

->

-:>

->
->
->
->

SO,
SI,
S2,
53,
S'I,
55,
S6,
S7,
58,
S9,
SIO,
Sl1,
512,
S13.,
S14,
S15,
SO,
Z

H
H
H
H

]
]
]

H ]
H ]
H']
H ]
H ]
L ]
H ]
H ]
H ]
H ]
H J
H ]

H ]
H J

Figure 20. Source File for ABEL

3-22

]

Page

ABEL(tm) Version
1.00 - Document Generator
4-bit binary/dec~de counter
Equ~tions

Module SO_COUNT

~or

D(?vice Iel

Reduced Equations:

eLK_OUT = '«SELl & SELO & 'CLKD
41 (SELl & !SELO 8< 'eLKe
• C!SELI & SELO & !CLKB
41 !5ELl 8< 'SELO & 'CLKA)))),

~ Q2 & Ql & 00
41 ('038< '02

03 := !«Q3
•
.,

#

(!03 ~
C!Q3 &:

~Qt

'00.
'CI_RI»)),

02 := '«028< 01 8< QO # ('028< '01 # ('028< !OO 41 !CLR»»,
01 .- '«01 & 00 41 ('01
QO

t=

I(CQO •

8<

'00

#

!CLR))),

!CLR»;

Page 2

ABELCtm) Version
1.00 - Document Generator
4-bit binary/decade counter
Chip diagram for Module SO_COUNT

I

Devic(? let

U)

P16R4

CLK_IN
SElO
SEL1
CLKA
ClKB
CLKC
ClKD
ClR
BD IN
GND

end

o~

~

VCC
ClK OUT
00
01
02
03

BD_OUT
OE

o

0eD

a::
C

o

'';:;

ca

,~

Q.
0c(

module BD_COUNT

Figure 21. ABEL Output Documentation

3-23

ADDRESSES FOR PROGRAMMING AND SOFtWARE MANUFACTURERS.
HARDWARE MANUFACTURERS

E

Citel
3060 Raymond St.
Santa Clara, CA 95050
(408) 727-6562

Structured Design
1700 Wyatt Dr., Suite 7
Santa Clara, CA 95054
(408) 988-0725

DATA I/O
10525 Willows Rd.
Redmond, WA 98052
(206) 881-6444

Sunrise Electronics
524 S. Vermont Avenue
Glendora, CA 91740
(213) 914-1926

DIGITAL MEDIA
3178 Gibralter Ave.
Costa Mesa, CA 92626
(714) 751-1373

Valley Data Sciences
2426 Charleston Rd.
Mountain View, CA 94043
(415) 968-2900

Kontron Electronics
630 Price Avenue
Redwood City, CA 94063
(415) 361-1012

Varix
1210 Campbell Rd.
Richardson, TX 75081
(214) 437-0777

Stag Micro Systems
528-5 Weddell Drive
Sunnyvale, CA 94086
(408) 745-1991

WaveteclDigelec
586 Weddel Dr., Suite 1
Sunnyvale, CA 94089
(408) 745-0722

Storey Systems
3201 N~ Hwy 67, Suite H
Mesquite, Tx 75150
(214) 270-4135

SOFTWARE MANUFACTURERS
Assisted Technologies (CUPL)
2381 Zanker Road, Suite 150
Santa Clara, CA 95050
(408) 942-8787
DATA 110 (ABEL)
10525 Willows Rd.
Redmond, WA 98052
(206) 881-6444

*Texas Instruments does not endorse or warrant the suppliers
.
referenced.

Reference
1. H. "froy Nagle, Jr., B.D. Carroll, and David Irwin, An Introduction
to Computer Logic. New Jersey: Prentice-Hall, Inc., 1975.

3-24

Hard Array Logic (HAL®)

tn

1::

o

Co

r!
c
o

i
.2
-aCo
«

."

TEXAS

INSlRUMENTS
3-25

IMPORTANT NOTICE

Texas Instruments (Til .reserves the right to make changes in the
devices or the device specifications identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
information being relied upon by the customer is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
such testing necesSary to support this warranty. Unless mandated
by government requirements, specific testing of all parameters of each
device is not necessarily performed.
In the absence of written agreement to the contrary, TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third parties by or arising from
use of semiconductor devices described herein. Nor does TI warrant
or represent that any license, either express or implied, is granted
under any patent right, copyright, or other intellectual property right
of TI covering or relating to any combination; machine, or process in
which such semiconductor devices might be or are used.

I

,

3-26

Copyright @ 1985, 'texas Instrumenta Incorporated

INTRODUCTION
The purpose of this document is to provide the design and
component engineer with a better understanding of Hard
Array Logic (HALI!». [It details both the advantages and
disadvantages of HAL and Programmable Array Logic
(PALI!» designs as a means of aiding the design and
component engineer in deciding whether to go to a HAL
device or to remain with the (PAL) product.] More
importantly, this document also defines the procedures to
be used by the customer when ordering HALs from Texas
Instruments.

PRODUCT DESCRIPTION
Programmable Array Logic (PAL) technology
constitutes one of the fastest growing areas in the
semiconductor industry today. This growth exists because
PALs offer circuit flexibility and package count reduction,
an advantage which design and component engineers find
over stan

Pin 1:

Pin 15:

Pin'2:

Pin 16:

Pin 3:

Pin 17:

Pin 4:

Pin 18:

Pin 5:

Pin 19:

Pin 6:

Pin 20:

Pin 7:

Pin 21:

·Pin 8:

Pin 22:

Pin 9:

Pin 23:

Pin 10:

Pin 24:

Pin 11:

Pin 25:

Pin 12:

Pin 26:

Pin 13:

Pin 27:

Pin 14:

Pin 28:

Programming Equations:

"C

'2.

..

C;'
I»

0'
~

l:I
~

"C

o

~

rn

3-30

A Designer's Guide to the
TIBPSG507
Robert K. Breuninger and Loren E. Schiele
with Contributions by
Joshua K. Peprah

E

..

TEXAS

INSTRUMENTS
3-31

IMPORTANT NOTICE

Texas Instruments (Til reserves the right to make changes in the
devices or the device specifications identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
information being relied upon by the customer is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with Tl's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
such testing necessary to support this warranty. Unless mandated
by government requirements, specific testing of all parameters of each
deviCe is not necessarily performed.
In the absence of written agreement to the contrary, TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third parties by or arising from
use of semiconductor devices described herein. Nor does TI warrant
or represent that any license, either express or implied, is granted
under any patent right, copyright, or other intl!lIectual property right
of TI covering or relating to any combination, machine, or process in
which such semiconductor devices might be or are used.

Copyright © 1987, Texas Instruments Incorporated

3-32

Contents
Title
INTRODUCTION .............................................................................

Page
3-37

FUNCTIONAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-37

THEORY OF OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1: Waveform Generator.............. .................... ..... ... .... ................. .
Example 2: Refresh Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 3: Dynamic Memory Timing Controller......... ................ ....................... .

3-37
3-39
3-42
3-45

DESIGNER NOTES...........................................................................
Obtaining Maximum Counter Performance. ..... .. ..... ....... ... ......... ..... ............ ......
Expanding the 6-Bit Counter ..................................................................
Software Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-51
3-51
3-51
3-51

Appendixes
A
B
C

ABEL Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CUPL Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
'PSG507 Fuse Numbers.....................................................................

3-57
3-67
3-79

I

tn

t::
o

~
G)

a:

c
o

'';::

ca

,~

Q.
~



"
"
P3

..
P5

P.

J=~

~~ ~ao

;:: R>

~~~al

=~~a2
~~a3
~~-Q4
~~r141

~~~Q.
~r".,

;:::.'-'-1>
Figure 1. PSG507 Architecture

3-38

for nonregistered operation. This permits the outputs to be
directly fed from the counter, AND/OR array, or state
registers. Example I highlights this feature.
In short, the outputs of a PSG can be controlled by any
or all of the following conditions:

to the master clock (PSG CLK) of the PSG. As shown in
the timing diagram, at count II (10112) the sequence is
repeated. By using the SCLRO function, a logic equation can
be defined to reset the counter at count II. This concept is
demonstrated in Figure 3.
With the binary counter programmed to clear at 11,
it is a simple matter to decode the outputs from the binary
count. With the REF CLK equal to the inverse of binary
count zero (CO), REF CLK can be directly generated from
the binary counter. A product term is required to connect
CO to the output cell. The output register is bypassed by
blowing the output multiplexer fuse. Figure 4 shows how
CO can be connected.
SYS CLK and PCLK are decoded from the present state
of the binary counter through the SIR outputs. Since the SIR
register holds its present state until changed, product terms
have to be used only during output transitions. For example,
when the binary counter reaches one, a product term is used
to reset the SYS CLK on the next clock transition. Below is a
summary of the product terms required to control SYS CLK
and PCLK. Note that the output transitions are set up in the
previous clock cycle. Also note that only one product term
is used regardless of how many output terms switch. This
is demonstrated at count 5 and count 11. Figure 4 also shows
how SYS CLK and PCLK are connected.

• Present state of the inputs
• Present state of the binary counter
• Present state of the state holding registers
The key to understanding state machine design when
using a PSG is to realize that different states can be assigned
for each sequence. In other words, the assigned state
determines which sequence is in operation. The length of
each sequence is controlled by the SCLR function. Once the
count sequence has been programmed to the desired length,
each output can be easily decoded from the present state of
the binary counter. The user will soon discover that complex
state machines are easily developed when using this
technique. This technique is demonstrated in Example 3;

Example 1: Waveform Generator
The first example demonstrates a design for a simple
clock generator used for driving a microprocessor operating
at 5 MHz (required duty cycle of33.5% high, 66.5% low).
In addition to the 5 MHz system clock (SYS CLK), a
reference clock (REF CLK) operating at 15 MHz (50% duty
cycle) and a peripheral clock (PCLK) operating at 2.5 MHz
(50% duty cycle) are required for other timing controllers
and peripherals throughout the system. Both clocks must be
in close phase with the SYS CLK to guarantee synchronous
operation within the system.
The above example demonstrates one of the many uses
of the binary counter in the PSG. State registers are not used
in this particular application, only the binary counter and
three outputs. A 30 MHz clock, typically generated from
a crystal, is used for driving the binary counter of the PSG.
The three generated clock signals are decoded from the
binary count. The unused inputs and outputs are still available
for other sequential or combinational applications.
Figure 2 shows the timing diagram for the above
application. For reference, a decimal count has been assigned

o

2

4

3

5

CNT
CNT
CNT
CNT

1:
5:
7:
11:

Reset SYS CLK
Set SYS CLK, reset PCLK
Reset SYS CLK
Set SYS CLK, set PCLK

This simple application demonstrates the basic concept
of building a waveform generator using the PSG. This
concept will be expanded further in Example 3 when a
memory timing controller is developed. The basic rules for
building a waveform generator are summarized below.

13

• Program the counter to reset to zero after the
desired count length is reached.
• Generate the logic equations to control the
outputs from the present state of the binary
counter.
6

7

8

9

10

11

t!o

Q.

CD

a:
C
o

';
,S:!

Q.

o

~

PSG CLK

115 MHz)

REF CLK

. . ._________. . .r

SYS CLK

'-_______________

PCLK

15 MHz)

~G2.5

MHz)

2. Clock Generator Timing Requirements
(Example 1 - Waveform Generator)

Figur~

3-39

£:'"COUNT 11

{'

fi

'II~

j~~
l\JlJIoo

155\

III

III

I:O~

SCLRO

:=: f+.:

~CiiiT/HLDO

':::'

~

;:: f+.:
~

~

;:: f+.:

~

::::: f+.:

~

I

~

;::: H::

~

{Rfe~~
~~
~~~
..

~~
~~~

~~

~

Figure 3. SCLR at COUNT 11
(Example 1 - Waveform Generator)

3-40

,

~eOUNT6
COUNT

eOUNT'\

COUNT 1'~

\

\

r

,;;=r- ~OUNT
1

11

*l

Ci;l
/l1,

/ifli1iiiJ

1

'

~

1Fs
r.~.r

t/)

e lK

I:ii.

Q.

~
~r-pelK

_ovo elK

~r~~
~-

~~-

~
Figure 4. Waveform Generator
(Example 1)

t:
o

CI)

IX:
C

o

'';:
«:I

,~

C.
Q.


• CNTIHLDC

;::,

~
K

:':.='

.~

K
K

==

.::: ~~
~

;;:::

:::

;:::

~

,:;::;;:::~

~~
I;::'~~

~~
~~

.~~~

fI)

~

o

c.
Q)

a:

..
c

-o

CO

-~
Q.
c.

«

!~~~
I~~~

~Figure 6. Expanding to 7-Bit Binary Counter
(Example 2 - Refresh Timer)
3-43

RESET~FC\
PSG elK

/CO~TC7'

63

~

RESET

RFC

+":-\
I

rr;:E5
co
C1
C2
C3

co

I'-

~

" CNTfHLOC

I:::

~~
~

'-'

~

I

==

'-'

•

~

R;

:;;:::
R;

--".

:=

- =-=

,:::~

~~~RFR

~~
~~
I'-~~
~~~

--".~~

ut~~

Figure 7. Refresh Timer
(Example 2)
3-44

Example 3: Dynamic Memory Timing Controller

accessing and refreshing the dynamic memory. The memory
timing controller must also be capable of arbitrating between
refresh and access cycles. In other words, if a refresh request
(REFREQ) occurs while the timing controller is performing
an access cycle, the controller must finish the access cycle
before granting the refresh request. Likewise, if an access
cycle is requested during a refresh cycle, the controller must
hold the processor while completing the refresh cycle. After
the refresh cycle has been completed, the access cycle can
be performed.

The third and last example will demonstrate a state
machine design using the PSG507. Figure 8 shows the circuit
requirement for a memory timing controller used for
interfacing an Intel 8086 to an 'ALS2967 dynamic memory
controller. Note that the clock generator and refresh timer,
developed in Examples I and 2, can be used in this circuit.
The dynami~mory timing controller generates the
control signals (RAS, CAS, MSEL, etc.) needed for

DYNAMIC RAM
DYNAMIC
MEMORY
CONTROllER

REFRESH

~

2967

RFC
REFREO
RESET<

i-

I-MEMORY
TIMING
CONTROllER
PSG507

CLOCK

~R

"ii2ii4'"

{

OSC

RESET

l - i- ~
I--<

SYS
ClK

I---<

r--

L..t

00-08
RFC

'-

ii-

II-

REF
ClK

256K DYNAMIC RAMS
TMS4256 (161

liASo

~ CASO
W

'-~

'1'7'"
I-\--t
I-t--t

BANKl
AO·A8

256K DYNAMIC RAMS
TMS4256 (161

RASl
CASl

~ W

L..--

'---

..

AO-A8

r

IiEFRm

REF
ClK

~
~

BANKO

RESET

RESET
8086

<

liAS ~ RASi

CAS ~ CASI

~

ROY

ROY

M/iO

MIlO

iiDl-WR

I--+-

r

MSEl ~ MSEl
MCl

I------t

MCl

~

MCO

II-

,-w..,
r-.I

f--t
f--t

I
BANK2
AO-A8
RAS2

AO-A17

lE

-r"

ROW (AD-A81
COL (A9-A 171

AlB

SELD

A19

SEL1

~

o

~ W

,-w..,

II
o

CAS2

c.

CD

a:

I

ALE

ALE

256K DYNAMIC RAMS
TMS4256 (161

BANK3
AO-AB

256K DYNAMIC RAMS
TMS4256 (161

RAS3

c

o

'';:;
CO

,S:!

CAS3

Q.

~ W

c.

00-15

00-015



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r+

o·:::s

ox
:L
o
A

iiD

I

AO·A17

I

AO·A17

I

I

AO-A17

I

:AO-A17

I

WR

( DATA FROM MEMORY

~

I

AO-A17

I

WRITE DATA

I

~~~~~~~~~~~~*~~~~~~~~~~~

9

:zJ

AO·A17

.

~Lox
~

I

\

1
1

I

8

9

10

11

12

13

14

15

16

17

18

19

'0

0

ose

.g

MC1

0

~

1
____________..,_ - - - - T - - - - .., -1- _____ __,,.___________________________

ROY

tn

\

,

t

-

,

RFC

MSEl __________

~

______________________________

~

*IF ROY - H. RETURN STO

Figure 11. Refresh/Access Grant Cycle

3-48

RE F elK

.(

~

[

~

~

ALE

Mlill

PO

+i

F
I

::

,.c::::r

I

F
seLRon
'::-...:t;
• CNTIHLDO

~
'="='

!:: o--l>

~

PO

"

~ .2

I~

~

K

;::: .,
?=

..

~

'"*

P5

"',-

..
~~r

"'~

I!::~.r

-

!::~.r

11111111

1111111

!::~~~
•

~~MSEL

I

en

~

&.

II)

a:
c
o
'';:;
ca
,S:!

i5.
Q.

c:r:

'='FJi'

~~ro
~~~

':'~~
Figure 12. Counter Control Logic
(Example 3 - Dynamic Memory Timing Controller)
3-49

RfF elK

.~

~

!!!..£!!!1

RESE!T

r=-

-.!!!2L

ALE
M/Rl
REFREQ

IPO

*lj

-

,til

rp
co
C1
C2
C3
C.
C.

~QJ
CNrIHLDO

~

=

;::, t±

~

PO

Pl

r---t.:

=

~
~

~

;:::
~

~

~

~~~~

:----MCl

~-RFC

;::,tY.:

~

~-=

;::,.t:±

~

~~-MSEL
~~~=

~~~~
~~rFigure 13. Memory Timing Controller
(Example 3)
.

3-50

DESIGNER NOTES
Obtaining Maximum Counter Performance
As with any programmable logic device, there are
usually several different methods for implementing anyone
application. In some cases, device performance is affected.
On the PSG, maximum counter frequency is affected by how
the designer controls the 6-bit counter.
For example, in the waveform generator example
shown at the beginning of this application note, the counter
was reset to zero after reaching count II by using the
nonregistered SCLRO function. By using the registered
SCLRI function, a higher operating frequency is obtainable.
This method requires an additional "AND" term as
shown in Figure 14, but does' provide maximum
performance. Note that during the 10th clock cycle the set
input on the SCLRI register is high. On the next active clock
edge, the counter advances to II and the SCLRI register
is set high. This causes the counter to be reset on the next
active clock edge. At the same time, the SCLRI register is
reset low to allow the counter to advance past zero.
In effect, the setup time requirement for SCLR I is
performed in the previous clock cycle. When using the
SCLRO method, the setup time must be added to the fmax
equation. This results in a lower fmax . The same tradeoffs
apply with the CNT/HLD function. The PSG507 data sheet
specifies fmax for both methods.

Expanding the 6-Bit Counter
In Example 2, the six bit counter had to be expanded
to 7 bits. This was accomplished by adding one of the state
registers to the most significant bit of the counter. It should
be noted that the synchronous clear and count hold functions
must be controlled through the set and reset inputs of the
added bits. The designer must be aware of certain limitations
when trying to perform this function. Figure 15 shows three
additional bits being added to the 6-bit counter. Note that
every bit added requires two additional "AND" terms.
A problem can arise on certain counts when trying to
generate a synchronous clear before reaching the full binary
count (all outputs high). The designer must ensure that both
Sand R are not high simultaneously. For example, let's say
we want the 9-bit counter to return to zero at count 383
(1011111112). At count 383, the SIR register used for C7
is being told to set. Therefore, any reset command would
result in both Sand R being high simultaneously.
This problem, only seen on a few data words, can be
solved by using another state register to control the counter
reset. This method is similar to that used above to obtain
maximum operating frequency. Figure 16 shows the 9-bit
counter returning to zero after count 383. Notice that at
count 382 the extra SIR register is being told to reset on the

next active clock edge. At count 383 the six product lines
controlling C6, C7, and C8 are disabled by the feedback from
the extra register, in particular the S input on C7. At
count 383, the 9-bit counter will return to zero and the extra
register is set high.
An extra register may also be needed to achieve the
countlhold function when using an expanded counter. During
certain counts the added bits will change state, even though
the 6-bit counter is programmed to hold. For example, let's
say we want the 9-bit counter to hold at count 383. Even
though the 6-bit counter can be held at 111111, C6 and C7
will advance on the next active clock edge. In order to hold
C6 and C7 where they are, an extra register is used to disable
the product lines responsible for the transition from count
383 to 384. Since the counter is on hold, the extra hold
register can only be reset from an input pin or a state
register(s) transition (not on the next count). In this example,
an input pin is used to reset the extra register and the
CNT/HOLD register. When the CONTINUE input is taken
low, the counter will continue to advance. The system must
guarantee that the continue input will not be low during count
382 to avoid the indeterminant set = H, reset = H state.
Figure 17 shows this 9-bit counter.
It is also important to note that when using extra
registers a reset input may be necessary to set the extra
registers high after powerup, since all SIR registers powerup clear. This requirement would not be necessary if the
phase of the extra register was reversed. This is easily
accomplished by using the iriverted feedback from the extra
register. However, it is good state machine design practice
to include a reset input that forces all SIR registers to a known
state.

I
U)

Software Support
The PSG507 is supported by two software packages;
CUPL, which was created by and is supported by Assisted
Technologies, a division of Personal CAD Systems
Incorporated, and ABEL, which was created by and is
supported by FutureNet, a division of Data I/O Corporation.
Each of these software packages can be used to reduce
equations and to generate a fuse map necessary to program
the PSG507. Appendices A and B show the ABEL and CUPL
files for Examples 1, 2, and 3. In addition, a PSG507
template is shown for each software package. These
templates provide software information that will make it
easier for the designer to create the source files.
Test vectors are included with the ABEL and CUPL
source files so software simulation can be performed on the
computer. If the proper instruction is provided, the software
will attach the test vectors to the end of the fuse map. This
allows programming equipment to run a functional test on
each device immediately after programming.

1::
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II

~.
'-' H;'

f--P'
"'-J

:::: ~

•

"'-J

>=I>
'-' ~

~~~
o.:p:

I--

'-'~~
'-'~~

~I-~I-~~~

Figure 14. Registered SCLR Example
(Designer Notes)

3-52

r~~~~~~1

cg.?~i'~ ,255-

~------------------------

N-!27
63

___

rJ

::.,..

C6

II~

--

I

SCLRO

I

;::; i---i>
- CNT/HLDO

I

-~

~

;::;
I;::;

~

I

ljJ; ::
Ef.l

C8

==='

~

;::;

FtJ

~

j~~

I;::;~~
I

I

~~

fL:~~

~~~

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en
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o
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CtI

.~

C.
Q.

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f~~~
I

1

I

;::;~~-

Figure 15. Expanding to 9-Bit Counter

3-53

COUNT
COUN:::il·
COUNT 382- r 511'
COUNT 383-

Ir~~~~;' 127
255

rCOUNTo:;;;.T .3

f""~

C6

->"j

;:E5;l
CO
C1
C2
C3
C4

~

- CNrIHlDO

r:..~
:= C6

~

;::~

0'
C8

""!!!=

>-P.:

=[}
n

E

-P.:

~

'.~ ~--

~~
~--

~~~

ut=~

~

.~ut=-

~~~
Figure 16. Resetting after Count 383
(Expanding the 6-Bit Counter)
3-54

COUNT 255-

COUNT

CONT1N~~~T 382-

511l

-COUNT 255

rCOUNT 127
rCOUNT 127
rCOUNT 63

f

~

_C§

~

Ig!
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.~

t-+..
-~I~l_D9

.~
.~

~

Hi:
~

~

Hi:

~

~

::: Hi:

C7

~~

==

::::

~
;;;=
~

I

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en
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 [OUT~UTS, STATE ])

-> [
-> [
-> [

-];
];
];

'count xx
·count xx
·count xx

I

3-59

Module PSG EXI
title 'ABEL EXAMPLE '1 (WavefoDn Generator) for the
PSGS07 DESIGNERS GUIDE, Texas Instruments, August 26, 1987'
PSGI device 'F507';
• Input pin assignments
PSG_CLK pin 1;
• Output
REF CLK
SYS-CLK
PCLK

pin and node assignments
pin
8;
pin
9;
SYS CLK r node 48;
peLK r node 49;
pin 10;
• REF_CLK is combinational

• Internal counter bits & control - node declarations
CO
node 55;
Cl
node 56;
node 58,;
C2
node 57;
C3
SCLRO node 25;
• Intermediate declarations for simplification
COUNT
[C3,C2,Ci,CO];
H,L,clk a 1, 0, .C.;
equations
REF CLK
SYS-CLK
SYS-CLK r
PCLK PCLK r
SCLRO

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CD

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o
;::.
en

3-60

•
•
•
•
•

=

:=

••
••
:=

-

!CO;
(COUNT==5) # (COUNT==11);
(COUNT==1) • (COUNT==7);
(COUNT-ll);
(COUNT=5);
(COUNT==l1);

•
•
•
•
•

High on cnt 5 and 11
Low on cnt 1 and 7
High on cnt 11
Low on cnt 5
·COllnter cleared after cnt 11

The PSG507 has powerup clear of counter· and registers. Six clocks
are required after powerup for this design to initialize. This
design could be initialized after one clock by setting SYS CLK and
PCLK high at COUNTO. i.e. SYS CLK .= COUNTO • COUNTS. COuNT11; and
PCLK :-COUNTO I COUNT11;
-

test vectors
([PSG CLK

[ clk
[ clk
[ clk
[ elk
[ elk
[ clk
I elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
I elk
I elk
I elk
[ elk
[ elk
I elk
[ elk
[ elk
I elk

COUNT)

0
1

)
)

2
3

)

4
5
6
7
8
9
10

11
0
1

2

3
4

5
6
7
8
9
10
11
0

]

]
)
]
]
]
)
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]

->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->

[REF_CLK, SYS CLK, PCLK) )
);
[
L
L
L
[
);
H
L
L
];
L
L
L
I
];
H
L
L
I
];
L
L
L
I
];
H
H
L
I
[
L );
L
H
[
];
H
L
L
[
];
L
L
L
H
L
L ];
I
L ];
L
L
I
[
H
H
H ];
[
L
H
H ];
[
H
L
H );
L
L
H ];
I
[
H
L
H ];
[
L
L
H ];
];
H
H
L
I
[
H
L ];
L
];
L
H
L
I
[
);
L
L
L
];
[
H
L
L
];
L
L
L
I
H
H
H ];
I
L
H ];
H
I

end PSG_EX1

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3-61

Module PSG EX2
title 'ABEL EXAMPLE '2 (Refresh Timer) for the
PSG507 DESIGNERS GUIDE, Texas Instruments, August 26, 1987'
PSG2 device 'F507';
" Input
PSG CLK
RESET
RFC

pin assignments
pin 1;
pin 2;
pin 3;

• Output pin' and node assignments
REFREQ pin
8; REFREQ_r node 47;
" Internal counter bits & control - node declarations
CO node 55; Cl node 56; C2 node 57;
C3 node 58; C4 node 59; C5node 60;
SCLRO node 25;
" Buried register
C6 node 31; C6_r node 39; " 7th counter bit
" Intermediate declarations for simplffication
COUNT
= [C6,C5,C4,C3,C2,Cl,CO); ,
H,L,clk,X = 1, 0, .C., :X.;

13

equations
REFREQ
:= RFC • RESET;
REFREQ r .~ (COUNT--76) & !RESET;
C6
:= (COUNT==63) « !RESET;
C6 r
.= (COUNT==76) & IRESET t RESET;
SCLRO
- (COUNT-76) & !RESET t RESET;
clear

@REPEAT 76
@REPEAT 20

3-62

•
•
•
"
"

([PSG_CLK,RESET,RFC)
[ clk
X)
H
[ clk
L )
L
[ clk
L )
L
[ clk
L )
L
[ clk
H )
L
[ clk
L )
L
[ clk
X)
H

set input
reset input
set input
reset input
synchronous nonregistered

-> REFREQ )
H
->
->
H
->
L
L
->
H
->
H
->
H
->

"CNTO
'CNTl-76
'CNTO
'CNTl-20
"CNT21
"CNT22
'CNTO

Module PSG EX3
title 'ABEL EXAMPLE '3 (Dynamic Memory Timing Controller)
"for the PSG507 DESIGNERS GUIDE, Texas Instruments, August 26, 1987'
PSG3 device 'F507';
• Input pin assignments
OSC
pin 1;
RESET
pin
2;
3;
ALE
pin
MIO
pin
4;
REFREQ
pin
5;
• Output
ROY
MCl
RFC
RAS
MSEL
CAS

•
•
•
•
•

pin and node assignments
8; ROY r
pin
node 47;
pin
9; MC1-r
node 48;
pin 10; RFC-r
node 49;
pin 11; RAS-r
node 50;
pin 13; MSEL r
node 51;
pin 14; CAS):
node 52;

• Internal counter
node 55;
CO
C3
node 58;
SCLRO
node 25;
CNTHOLDl node 29;
PO
node 31;
Pl
node 32;
BROY
node 33;

OSCILLATOR
RESET - INITIALIZES WHEN HIGH
ADDRESS LATCH ENABLE
MEMORY I/O
REFRESH REQUEST

• READY

•
•
•
•
•

MODE CONTROL
REFRESH COMPLETE
ROW ADDRESS STROBE
MULTIPLEXER SELECT
COLUMN ADDRESS STROBE

bits & control, and state reg - node declarations
C1 node 56; C2 noae 57;
C4 node 59;

,

CNTHOLD1_r
PO r
Pl-r
BRDY r

node
node
node
node

·

30;
COUNT/HOLD CONTROL REGISTER
39; • BURIED STATE REGISTER
40; • BURIED STATE REGISTER
41; • BURIED READY SIGNAL

• Set notation is used to represent control, buried state, and output
" registers. This is done to simplify the equations. The following
• sets are in the form; register name = [set input, reset inputJ. Note
" that the ouput register pin name specifies the set input.
ROY
[ROY, ROY rJ;
MC1- [MC1, MC1-rJ;
RFC= [RFC, RFC- rJ ;
RAS= [RAS, RAS-rJ;
MSEL
[MSEL, MSEL rJ;
CAS = [CAS, CAS rT;
BROY
= [BROY, BRDY_rJ;
" Intermediate declarations for simplification.
" The sets 'high' and 'low' are used to set or reset the SiR
"registers. Example: Mel := high & RESET; will cause pin 9
" to go high on the next clock edge if input pin 2 is high.
high
= [1, OJ;
low
= [0,
lJ;
COUNT
[C4,C3,C2,Cl,COJ;
STATE
- [Pl,POJ;
• STATE REGISTER SET DEFINED
H,L,clk,X = 1, 0, .C., .X.;
@page

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as
,9
Q.
Q.

 [RDY,MCl,RFC,RAS,MSEL,CAS,STATE ])
0 -];
[clk, H
X
X
X
X
-> [ H , H , L , H , L , H
[clk, L
L
H
H
0
-> [H H L
H, L
H
0
];
H,HrL,H,L ,H, 1
];
[clk, L , H , H, H
0
->
H , H , L , L , L
11, 1
];
[clk, L , X , X, X
0
->
];
[clk, L , X , X, X
1
-> H , H , L, L , H , H, 1
[clk, L , X , X, X
2
-> 11 , H , L , L , H , L, 1 ];
@CONST cnt
3; @REPEAT 6
[clk, L , X , X, X
, cnt
-> H , H , L , L , l l , L , 1
];
@CONST cnt
cnt + 1;)
[clk, L , X , X, X
9
-> H , H , L , H , L ,11
0
];
[clk, L , L , L
H
0
->
H , H , L , H
L , H
0
];
test vectors ' REFRESH WITH ACCESS FOT,LOWING'
([OSC, RESET,ALE,MIO,REFREQ,COUNT] .. > [RDY,MCl,RFC,RAS,MSEI" CIIS, STATE])
[clk, H
X
X
X
X
-> [ H , H , L , H , J~ , ll, 0 -];
[clk, L , X , X
L
0
-> [ H , H , L , H , L , ! l I 2
];
[clk, L , L , L, X
0
->
H , L , L , H , L , H,
2
];
[clk, L , L , L, X
1
-> [ H , L , H , I, , L , H, 2
];
[clk, L , L , L, X
2
-> [ H , L , H , L , L , H, 2
1;
];
[clk, L , L , L, X
3
->
H, H , H , L , I, , H,
2
];
[elk, L
H
H
X
4
->
L I H
H
L
L , H
2
];
[clk, L , X , X, X
5
->
L, H , L , L ,J~ , H,
2
];
[clk, L , X , X, X
6
-> L, H , L , II L
H,
2
[clk, L
X
X
X
7
->
L
H
I,
H
L
H
2
1;
] ;
[elk, L , X , X, X
8
->
IJ 1 H ! L , H , 1 r H, 2
];
[clk, L , X , X, X
9
->
L, H
L, H ,L , ll, 2
];
[clk, L , X , X, X
10
-> L
H, L , L , I,
H
2
];
[clk, L 1 X , X, X
, 11
->
H, H , L , L , H
H f
2
];
[clk, L , X , X 1 X
12
->
H, H , L , L ,H , J~
2
@CONST cnt =13; @REPEAT 6 {
];
cnt
H
H
L
2
[clk, L , X ,X
X
->
L r H
@CONST cnt
cnt + 1;)
H, H, L H
, 19
L
[clk, L , X , X, X
->
I'
H. ,
o ];

r

test vectors ' REFRESH WITHOUT ACCESS FOLLOWING'
([OSC,RESET,ALE,MIO,REFREQ,COUNT] -> [RDY,MCl,RFC,RAS,MSEL,CAS,STATE_l)
[clk, H
X
X
X
X
-> [ H , H , L , H , L ,Ii, 0
];
[clk, L , X , X,
L
0
-> [ H , H , I, , II ,I"
H
2
];
[clk, L , L , L 1 X
0
-> [ H , L ,I, H, L , H, 2
];
[clk, L
L
L
X
1
-> [H I,
H, 1. ,L
II
2
1;
[clk, I,
L
L
X
2
-> [H L H, I, ,L , H , 2
1;
[clk, L
L
L
X
3
-> [H
H
H
J.
I,
l!,
2
J;
[clk, L , L , H, X
4
-> [ H , H , Ii , ], r L , Hr·?
l;
[clk, L , H , L, X
5
-> [ H , H , J~ r L ,L , H, 2 ];
[elk, L , H , L r X
6
-> [H
H
I"
H
L
H
2
J;
[clk, L , H , L r X
7
_.> [H
H, j, , H , L
H
2
J
[elk, L , H , L, X'
8
-> [H H, I,
H, T" " l:J.,
:2
[elk, L , H
L, X
9
-> [ H , H , I, , H , I. , H r 0

en

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a::

c::

o
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ca

,sa

Q.
Q.

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@page

3-65

test vectors ' RESET DURING REFRESH '
([OSC,RESET,ALE,MIO,REFREQ,COUNT] ->
X ] ->
[clk, H ,X,'X, X
[clk, L , X , X , L
0 ] ->
[clk, L , L , L , X
0 ] ->
[clk, L , L , L , X
1 ] ->
2 ] ->
[clk, L , L , L , X
3 ] ->
[clk, H , X , X , X
end PSG EX3

I

3-66

[RDY,MC1,RFC,RAS,MSEL,CAS,STATE_])
[ H, H, L , H, L , H
];
0
[ H , H , L , H , L , H ,
];
2
[ H , L , L , H , L , H ,
2
];
[ H , L , H , L , L , H ,
2
1;
[ H , L , H , L , L , H
];
2
[ H , H , L , H , L , H ,
];
0

Appendix B. CUPLTN Source and Simulation Files
1****************************************************************************1
1* CUPL (tm) TEMPLATE FOR THE TI PSG507
*1

1*
1*
1*
1*
1*
1*
1*

*1
*1
*1
*1
*1
*1
6-BIT COUNTER: The 6-bit counter is accessed through use of the PINNODE *1

This file provides the PSG507 designer quick access to the information
needed to write a CUPL source file. By copying this file and deleting
this box from the new file a fill-in-the-blanks template will be left
for use in creating a source file.

/*
/*
/*

/*
/*

1*
/*

/*

statement. The pinnode statement is used to assign
variables to the internal node numbers. i.e. pinnode
[33 •. 38) ~ [CO .. C5).CNT. These variables can then
be used in. the same manner as input pins.Using the
field statement, i.e. field COUNTER ~ [CO .• C5).CNT;
allows an equation like QO = COUNTER'd'3 f COUNTER'd'7;
This equation causes the nonregistered output QO to be
high only during counts 3 and 7.

1*
1* COUNTER CONTROLS:
1*
/*

1*
/*

/*
/*

/* STATE

/*
/*

REGISTERS:

Clear and hold functions SCLRO, SCLRl, CNTHOLDO,
and CNTHOLDl are specified using the PINNODE
statement. Any valid variable can be used as a node
n~e, i.e. pinnode [39 .. 42) = [CLRO,CLRl,HLDO,HLDl);
These variables can then be used in the same manner
as an output pin.
Buried registers are assigned using the NODE statement, i.e. node [PO •. P7);. The actual registers
used are chosen by software in the order specified.

1*
1* OUTPUT STRUCTURE: Each output can be defined as either registered or

/*
/*

1*

/*
/*

/*
/*

nonregistered. The structure assignment is automatic
and is determined by usage. QO.s = COUNTER'd'77;
causes the QO output to remain registered while
QO = 90UNTER'd'77; causes the QO output to be nonregistered. When using nonregistered outputs CUPL
will automatically program the associated reset fuse
for each product term used as required in the PSG507
data sheet.

*/
*/

*/
*/
*/
*/

*1
*1
*1

*/

*1

*/
*/
*/
*/

*1

*/

*1

*/

*1

*/

*1

13

*/
*/

*/
*/

*1
*1
*i

/*
/*
*/
1***************************************************** ***********************/

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P3

~

P,

~

::: ~

P<

;:::

~

P6

~

P7

I::::

en
1::

i-~~'l"

I;:::

II

~tl"
-L

,;::~!J!o>-02
~

2"6'

,-~~Q3
1"-

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o

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ca

,sa

Q.
Co

«

~rtl1"

I':-~

~

~t""
i'!.

~~~Q'
~

~~

.

,"

~rl161

--j>

~~

MOO
.M
000

~~

;g

;n~
;;N

~~

MOO

~;::

~

l"69

3-79

Il

3-80

System Solutions for
Static Column Decode
Robert K. Breuninger, Loren Schiele,
and Joshua K. Peprah

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TEXAS

INSTRUMENTS
3-81

IMPORTANT NOTICE
Texas Instruments (Til reserves the right to make changes in the
devices or the device specifications identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
information being relied upon by the customer is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with Tl's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
such testing necessary to support this warranty. Unless mandated
by government requirements, specific testing of all parameters of each
device is not necessarily performed.

I

In the absence of written agreement to the contrary, TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third parties by or arising from
use of semiconductor devices described herein. Nor does TI warrant
or represent that any license, either express or implied, is granted
under any patent right, copyright, or other intellectual property right
of TI covering or relating to any combination, machine, or process in
which such semiconductor devices might be or are used.

Copyright © 1987, Texas Instruments Incorporated

3-82

Contents
Title
INTRODUCTION .............................................................................
STATIC COLUMN DECODE...................................................................
TYPICAL MEMORY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING CONTROLLER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NORMAL ACCESS SEQUENCE .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HIGH-SPEED ACCESS SEQUENCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXTENDED ACCESS SEQUENCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NORMAL/EXTENDED REFRESH SEQUENCES ............................................ . . . . . .
SOFTWARE SUPPORT ............ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SUMMARY ..................................................................................

Page
3-85
3-85
3-87
3-87
3-89
3-89
3-90
3-90
3-94
3-94

Appendixes
A
B

ABEL'" Files .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CUPL'" Files....... .. ..... ... .. ..... ........... .. ............ ... ................ .... ......

3-95
3-101

ABEL is a trademark of DATA 110
CUPL is a trademark of Persooal CAD Systems, Inc.

fI)

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3-83

List of IDustrations
Figure

Title

Page

1
2
3
4
5
6
7
8
9

Static Column Decode Mode Read Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68020/6301 Static Column Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ALS6310 Static ColumnlPage Mode Access Detector ........................................
Timing Controller Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normal Access Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-Speed Access Cycle ...............................................................
Extended Access Cycle .................................................................
Normal Refresh!Access Grant Cycle ......................................................
Extended Refresh Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-85
3-86
3-87
3-88
3-89
3-90
3-91
3-92
3-93

3-84

INTRODUCTION
The new 32-bit microprocessors are capable of addressing
4G bytes of physical memory and typically feature clock
frequencies greater than 16 Mhz. However, clock speed
alone does not guarantee increased system performance; if
the processor must wait for data, then memory bandwidth
will be the limiting factor.
This situation exists between today' s microprocessors
and the access times of affordable DRAMs. One solution to
optimizing system performance is to mix and match memory,
using lower cost dynamic RAM in conjunction with fast,
more expensive static RAM caches. However, this approach
is only attractive to high end systems where cost and board
space is a less significant factor.
Another approach to improving system performance
is to utilize the new accessing modes available on certain
I meg DRAMs, such as static column decode. This method
does not improve system performance as much as caches,
but it does involve less hardware, resulting in lower system
cost. This approach can also be used in systems already using
caches, further improving system performance.
This application note describes the theory of using static
column decode and also describes how it might be
implemented in a typical system. In addition, it highlights
three new products from Texas Instruments. The

SN74ALS6300 "Selectable Refresh Timer", the
SN74ALS631O "Static Column Access Detector", and the
TIBPSG507 "Programmable Sequence Generator".

STATIC COLUMN DECODE
The TMS4C1027 is a 1,048,576-bit x 1 dynamic
RAM featuring static column decode. Static column decode
allows high-speed read and write operations by reducing the
number of required signal setup, hold, and transition timings.
This is achieved by first strobing the row and column
addresses in the normal manner by taking RAS and CAS low.
If RAS and CAS are kept low, new data can be accessed
by simply changing the column addresses, assuming the new
address is in the same row. If the new address is not in the
same row, then a normal access cycle must be performed.
Figure I is a timing diagram taken from the
TMS4CI027 datasheet showing static column decode mode
read cycle timing.
If the assumption is made that the majority of memory
references tend to be sequential, which is a similar
assumption made when using caches, then it is logical to
assume that a large percentage of memory accesses will be
within the same row. The trick is how to implement a timing
controller which will take full advantage of the static column
mode of operation.
~

I+-tw(RH)

1~4f-------------tw(RL)P------------".1 1 1

II I
},A.·
II '--

1
~i
RAS

!\
I "'.

I
1I
I I

--------------------------1

~ t+-tt

I

.1

14

:I ~

td(RLCL)rd

/I+!-';---

I
I

,
I

I I4--th(RLCA)~

~ t4- t h(RA)
tsu(RA)--.I
I

I
I

tJ., 1 I

1

~

VIL

I

~

oQ.

VIH

VIL
t+-thIRHCA)

I I I
l+--tc(rd)SC~
I+-tsuICAR)~ I I
I
i'_ _..........I,....._ _ _.l..S..1

AO·A9

VIH

CD

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~td(RLCA)

••
II

j4-tsu(RLrd)

I I

1

I I
II

!ldd"

~

•

C»

V'C.
REFRESH
TIMER

SO-S3

RefREO

CLK

1

~'

f----t
f----t
f----t

SYSCLK

osc

CLK

~

IOtllil

....

DSACK

Rt'li

Rt'li
AS

AS
STATIC CDLUMN
DETECT
SN74ALS6310
_P-CLK

·
r-I •

Al0-A1S

\

I-t HSA

ROW
Al0-A1S
COLUMN
AO-AS
A20
A2l

..

RASO

CASO

CASO

'Ii

I I I I
~

MCl

7

AS

MCO

RASl

-I--

RASl

a

CASl -~

CASl

~

lH':

BANK 1
1 MEG X 32 BITS
(321 TMS4Cl027

'Ii

I I I I
7

··

AO

-I--

RAS2

CAS2

I- >--

CAS2

~

BANK 2
1 MEG X 32 BITS
(321 TMS4Cl027

AS

RAS2

BO

I

·••

~

r-

\

BANKO
1MEG X 32 BITS
1321 TMS4Cl027

'Ii

~

Bl

1

---.:...

AO

AO

r

·

•
•
AS-

RASO -----,-

MSEL

AS

r---t

I

AO

- - - l iiASi

L.....--

SYS RSf

lotlll(A2Z

••
OSf--

\

.----

iiFC

~

DYNAMIC RAM

00

RST

r---t

SYS CLK
(OSCt2)

LE

TIMING
CONTROLLER
TIBPSG507

~

REFRESH
RATE
SELECT

DRAM
CONTROLLER
74ALS6301

'Ii

I I I T

...-

...:l.

AO

A.O

•

--, :9

A1S

SELO

RAS3

RAS3

SEll

CAS3

CAS3

BANK 3
1 MEG X 32 BITS
1321 TMS4Cl 027

W

00_. e031

Figure 2. 68020 Static Column Memory Controller

QO •• ea31

'J

TYPICAL MEMORY CONTROLLER
Figure 2 shows a block diagram of a memory system
utilizing static column decode. The ALS63 10 is a new circuit
offered by Texas Instruments which detects if the present
row being accessed is the same as last row accessed. This
is the fundamental requirement for implementing static
column decode. Note that the row addresses from the 68020
are used as the most significant bits (AIO-AI9) and the
column addresses are used as the least significant bits
(AO-A9). Figure 3 shows a block diagram of the ALS63 10.
In circuit operation, when address strobe (AS) from
the 68020 is taken low, the present row (AIO-AI9) and bank
address (BO, Bl) is clocked into the first register of the
ALS631O. The previous bank and row address, stored in the
first register, is clocked into the second register at the same
time. The two addresses are then compared to see if they
are equal. If they are equal, the high speed access output
(HSA) will be logically low. If not, HSA will be high.
The function of the PSG507 is to generate the required
memory timing control signals (RAS, CAS, etc.) for the
ALS6301 dynamic memory controller. The ALS6301 is
responsible for multiplexing row and column addresses into
DRAM. The ALS6391 is also capable of driving 4 banks
of 1M-byte memory.

Supporting the PSG507 is the ALS6300 refresh timer.
This device is responsible for generating a refresh request
signal (REFREQ) every 15.5 p.s. The input select lines are
hardwired to match the microprocessor clock frequency. The
refresh complete input (RFC), resets the REFREQ signal
after the timing controller completes the refresh cycle.

TIMING CONTROLLER DETAILS
Figure 4 shows a typical flow chart for implementing
static column decode. As stated before, the PSG507 is
responsible for implementing the flow chart shown in
Figure 4. A breakdown of this flow chart reveals 9 states
(STO-ST8), associated with 5 different sequences. States STO,
STl, ST3, and ST4 are holding and transition states, leading
into the various sequences. The five possible sequences are
listed below.
ST2 Normal Access Sequence
ST5 Extended Access Sequence
ST6 High-Speed Access Sequence
ST7 Normal Refresh Sequence
ST8 Extended Refresh Sequence
Notice that the HSA signal from the ALS63 10 decides
if the timing controller will execute ST5, the Extended Access
Sequence, or ST6, the High-Speed Access Sequence. A brief
description of each sequence follows.

CLKEN----~----------------------------_,
CLK--e-~---------------------------,

PRESENT ADDRESS
REGISTER
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10

AO-A9

4X

4X

(BANK]

(BANK]

BO-B3

P-Q

HSA

P-Q

HSA

..
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()

=a

Q.

ct

Figure 3. ALS6310 Static Column Page Mode Access Detector

3-87

NO

Figure 4. Timing Controller Flowchart

3-88

NORMAL ACCESS SEQUENCE

HIGH-SPEED ACCESS SEQUENCE

The normal access sequence is shown in Fi~ 5. This
sequence begins by executing a normal RAS/CAS cycle.
Notice that a wait state of one clock cycle is needed to
guarantee that data is valid for the 68020. This is the problem
mentioned in the introduction; if all access cycles had to be
performed in this manner, then the processor would face a
wait state every access cycle. As will be shown later, this
wait state can be eliminated if the next address is from the
same row.
Notice also, at the end of this sequence, the RAS and
CAS output signals are left active low. Here we are making
the assumption that the next access cycle will be a high-speed
access. We will not know if this assumption is true until the
next address is presented by the 68020. At that time, the
ALS6310 wilt' signal the timing controller if it can execute
a high-speed access.

For a high-speed access sequence to be executed, two
conditions must be met. The RAS and CAS inputs must
already be low, and secondly, the static column access
detector must be indicating the present row is the same as
the last row (HSA = L). The bank addresses must also be
unchanged as detected by the ALS631 O.
Figure 6 shows the timing diagram for the high-speed
access sequence. Notice that no wait states are required. If
the assumption is made that the majority of memory
references are sequential, then this sequence will be the one
typically used., In other words, this sequence is similar to
accessing data from a static RAM, or just like taking data
from cache.

ST2
CNT1
S2

r-~~~L-

ST2
CNT2
SW

ST2
CNT3

ST2
CNT4
S3

SW

ST2
CNT5
S4

____________________

ADX SSSSSSSSSSSx
R/W \SSSss\\s\SlC - - - - -

ST3
CNTO
S5

~

__

~-------'L

ISSSSS,S,'

VALID PROCESSOR ADDRESS

- - - VALID R/W SIGNAL

"')(sss SSS \SS

I
I

I

I

II)
~--------------------------1-----------------------------+'----------------------I
t::
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MSEL--------------------~----~----~----------t!-----------------­ Q.
CD

a:

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I

CASI

--------------------------~------------~--------------+:----------------------- C

o
+=
as

I

MADR S"SSSSSSS"""X

ROW ADDRESS

x
I
I

I

QO~Q31

I
COLUMN ADDRESS

I
I

.~

I

_ ____________________________________~'--~I.::====:.~I~TA~(C~I~::~W[~~ffiC:::::::::::
:

(

VALID READ DATA

_TA (CAI--.l

DSACK-----------------------------------------,____________________

Q.
Q.

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IN

cD

•

~

STO
CNTO

ST7
CNT1

ST7
CNTO

ST7
CNT2

ST7
CNT3

ST7
CNT4

ST7
CNT5

ST7
CNT6

ST7
CNT7

ST7
CNT8

ST7
CNT9

ST7
CNT10

ST7
CNT11

ST7
CNT12

ST7
CNT13

ST7
CNT14

ST3
CNTO

OSC
SO:
SYS ClK

S1

S2

SW

SW

SW

SW

i

r-

AS--1

REFREO ~:1-i-

________________________________-1-------1--------------------------------------------t---------

-

I

RFC

'I
I

AGREO---------,________________________________________~I~r_----------------------------------------!--------ADX \ \

55 \ \\X

x::s:s

VALID PROCESSOR ADDRESS

liSA \\\\ \\ \\\\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \\\\\\\\\\\\\\\\S\\\\\\\

DON'T CARE

\\\\\\\\\ \\\\\\\\\\\\\\\ \\\\\\\\ \\\\\\\

I

R/W \s\\\SSSJC - - - - - - - - - - - - - - - - - VALiD RiWDinA - - - - - - - -

- - - - - - - - - - - L - ~
I

MC1------------1-____________________________r-------------------------------~
RASI----------------~__________________~------------------L_

MADR

ROW REFRESH ADDRESS

________________

ROW ADDRESS

~-------

COL ADDRESS

I

MSEl

I
I

ht-----------f
I

CASI'

00-031

---------------------------------~-------------------------------------------------------It=~~~~)
I+-TA (C) .....

H~ADDAIA

r-C-----r-

DSACK

W

Figure 8. Normal Refresh!Access Grant Cycle

ST3
CNTO

STB
CNTO

STB
CNT1

STB
CNT2

STB
CNT3

ST1
CNTO

ST1
CNT1

ST1
CNT2

ST1
CNT3

ST1
CNT4

ST7
CNT5

ST7

CNT6

STO
CNTO

STO
CNTO

OSC

SYS CLK

---..J

]-

AS------~------------------------------------------------------~-------------

REFREQ
RFC------------------------------------------------------------iL__________~~--~--------------AGREQ------------------------------------------------------------------------------------------~------------------ADX

\SSSSSS\\SS \\S S\ S\SSSS\\S\\ S\SS\ SSS\

DON'T CARE

S\\\S\ S\SS\\\\\SSS\\SS'0\TI)\\\\\\\\\\

HSA

\\\SSSSSS\\S\\SSS\\SS\\SS \\S\\SSSSSS

DON'T CARE

SSS\\SS\\SSSSSS\\\\SS\\\SS\S\\\\SSS'\ '0

R/W

S\ S\\ \ \\ \\\ \\\\ S\\ \\ \ \ \ \\\ \ \\\ \ \ \\ \\

DON'T CARE

\

\\\S S \\S \S \ S\\ \\\ \\ \, 'TISTI,\\\\\ \\ \\ \

1

MC'

~--------------------~
MADR

\\\\\\\\\\\SS\SS\S\\\\S\\\S\\\S\\\\\\\\\\\X

ROW REFRESH ADDRESS

X\ 'US\\\\\\\

MSEL------------------------1-__________________________________________________________________________
CASI ________________________

~

QO-Q31 \\\ \\ \ \ \ \\ \ \ \ \\ \ \, \\'\ \, \ '\'}~----------------------------------------...
DSACK---------------------------------------------------------------------------------------------------------

W----------------------------------------------w
cO
w

Figure 9. Extended Refresh Cycle

Application Reports

1:1

SOFTWARE SUPPORT

SUMMARY

The PSG507 is supported by two software packages.
CUPL which was created by and is supported by Assisted
Technologies, a division of Personal CAD Systems Inc. and
ABEL which was created by and is supported by FutureNet
a division of Data 1/0 Corp. BOth of these software packages
have been used to reduce eqUations and to generate the
fusemap necessary to program the PSG507. Appendices A
and B show the ABEL1M and CUPLno source files for the
described static column memory timing controller are
attached to assist the designer in progra:mming the PSG507.
Since only 54 % (43 out of 80) of the PG507' s product
terms were used in this design, it will be easy to modify or
add to the sequences used to meet specific system
requirements. For detailed information ondesigning with the
PSG507 see "A Designer's Guide to the PSG507"
application report.

Static column decode offers the system designer a
method for improving system performance in applications
where the microprocessor can outperform conventional
DRAM access times. By utilizing the ALS6310 "Static
Column Access Detector" , the ALS6300 "Refresh Timer" ,
and the TIBPSG507 "Programmable Sequence Generator"
a high performance memory timing controller can be easily
developed to take full advantage of static column decode.

11

3-94

APPENDIX A
IlOdule S(DECODE
title ' ABEL EXAMPLE FOR TIlE S'lATIC COLUIti DECODER
JOSH PEPRAH, TEXAS mS'lRUM!'.IITS, OCT 29, 1987'
DECODE device ' r507' ;
• Input pin assi9Jlll8llts
pin 1;
RESET
pin 2;
122
pin 3;
RII
pin 4;
REI'REQ
pin 5;
AS
pin 6;
HBA
pin 7;
SYSCLK
pin 17 ;

ose

•
•
•
•
•
•
•
•

• Output pin and node assiCJIIIRents
RfC
pin 8; RfC r
WI
pin 9; WI r
MSEL
pin 10; MSEL-r
CASI
pin 11; CASfr
1«:1
pin 13; 1«:1
II
pin 14; II rDSACK
pin 15; DSACKJ

r

node
node
node
node
node

47;
48;
49;
50;
51;

node 53;

OSCILLATOR
SYSm! RESET - IIBEN LOll
IO/MtHlRY - MEMORY ACCESS
READ I IIRlTE EHABLE
REfRESH REQUEST
ADDR STROBE - ACCESS REO
HIGH SPEFD ACCESS
SYSm! CLOCK - (Ose/2)

• REfRESH COMPLETE
• ROW ADDRESS STROBE
• .m.TIPLEXER SELECT

• COLUIIH ADDRESS STROBE
• DE CONTROL
node 52; • IIRITE
• DATA STROBE ACIINOIILEDGE

• Internal counter bits , control, and state reg - node declarations
CO,C1,C2,C3,C4,C5 node 55,56,57,58,59,60;
SCLRO
node 25;
Ctl'.l'IIOLDO node 28;
OOHOLDI node 29; OOHOLDI_r node 30; 11 COUN'l/HOLD CONTROL REGIS'lER
• Buried state registers - node declarations
node
node
PI
node
P2
node
P3
AGREQ node
PO

•
"
•
•

31;
32;
33;
34;
35;

PO r

node
Pl-r
node
P(r
node
P3 r
node
AGREQ_r node 43;

39;

40;

41;
42;

" STATE REGIS'lER
• STATE REGISTER
• STATE REGISTER
• STm: REGISTER
• ACCESS GRAHT REQUEST STATIlS REGISTER

Set notation i8 used to represent control, buried state, and output
registers. This is done to simplify the equations. The following
sets are in the fOIII; register DaIl8 • [set input, reset input). Rote
that the ouput register pin l\8IIe specifies the set input.

RfC
WI
MSELCASI11:1 I DSACK
AGREQ:

'•
=
•
•
•
•
=

I
~

oQ.
Q)

a:

c
o
as

'';:;

,9

Q.
Q.

c:t

[RfC, RfC r);
[WI, WI r);
[MSEL, MSEL- r) ;
[CASI, CASI-r);
[11:1, 1«:1 rT;
[I, I r);[DSACK, DSACK r);

• [AGREQ, AGREQ:r);

3-95

•
•
•
•

Int8l1l8diate declarations fot simplification.
The sets 'high' and ' low' are used to set or reset the SiR
registers. Ewlple: WI := high' RESET; lIill cause pin 9
to go high on the next clock edge if input pin 6 is high.
..
•
..
=

high
1011

COM'

S'lAft

H,L,cll,X

[1, 0];
[0, I];
[C3,C2,Cl,CO];
[P3,P2,P1,PO];

n

STm: REGISmt SET DEFINED

- 1, 0, .C., .X.;

equations
enable RI'C .. 1; "outputs always enabled, pin 17 is only an input·
" Initialization when RESET is 1011
[WI, CASI, RI'C, W, AGREQ, DSACK,II:1, SCLRO] := IRESET;
[1ISEL_r,PO_r,PIJ,P2_r,P3J]
:= !RESET;
n

Counter controls defined
= I RESET
# (STATE -2)
f (STATE-==4)
f (STATE-""5)
t (STADC=6)
t (STATE-==7)
t (S'lATE-==7)
t (STATE:-8)

SCLRO

•

ctmIOLD1

.=

, (COIJNTI=5)
, (COUN'l==O) & A22
, (COIJNT-10)
, (COON'l-4)
, (COIJN'l-6) , (A22
, (COIlN'l=oo14)

t AGREQ)

, (COON'1=3);

!RESET

t
f
f
f
t
f

t

(STATE =2)
(STATE-"'4)
(STATE-=5)
(STATE- =6)
(STATE- -7)
(STATE- ==7)
(STAT(-8)

,
,
,
,
,

(COON'l'-5)

(COUHT-o) , A22
(COONT==10)
(COUHT==4)
(COON'1=6) , (A22 f AGREQ)
, (COIlHT-14)
, (COUHT-3);

CHTHOLDl r :- (STATE -0) , lREFREQ , RESET
1 (SUTt: =1) , !A22 , RESET
t (STATE- ••3) , !REFREQ , RESET
f (STAT(==3) & REFREQ & AS & SYSCLK & RESET;

• Execution of access and refresh sequences
state diagram SUft
State 0:
case
!RESET
REFREQ & (lAS t ISYSCLK)
REFREQ' AS' SYSCLK , RESET
!REFREQ' RESET
endcase;

3-96

"Hm
" STm:
: 0;
: 0;

: 1;
: 7;

" NORMAL ACCESS CYCLE
State 1:

" NEXT
" STATE
: 2;

case
(COUNT-O) & !A22
(COUNT-O) , A22
endcase;

: 0;

State 2:
RASI :- (COUNT-O) & low & RESET;
& high;
CASI- :- (COUNT-2) & low & RESET;
DSACK- :" (COUNT-2) & low & RESET;
11 - :" (COUNT-3) & low 'RESET;
If := (C0UNT-5) 'high;
DSACK := (C01JNT-5) 'high;
if (coiiNT-5) then 3 else 2;
MSEL- :- (COUNT-I)

"BOLDING STATE
State 3:

" NEXT

case
(!AS

" STATE

t

!SYSCLK) , REFREQ , RESET
REFREQ' AS' SYSCLK & RESET
!REFREQ , RESET
endcase;

State 4:

,,

CASI :" (COllN'r-O)
high &
RASI- :- (COONT-O)
high'
MSEL- := (COUNT-O)
low
RASI- :" (COUNT-I) & high'
DSAcK := (COUNT-1)
low &
MSEL :- (COONT-l)
low
high ,
CAS( :- (COtlNT-I)

,
,

: 3;

: 4;
: 8;

A22;
A22;
A22;
KSA;
!RSA;
KSA;
BSA;

I

U)

t:

o

" NEXT

case
(COUNT==O)
(COUNT-O)
(COUNT-I)
(COUNT-I)
endcase;

" STATE
& A22 & RESET
& 1A22 & RESET
& BSA & RESET

: 0;
: 4;
: 5;

, !BSA ,RESET

: 6;

Co
Q)

a:
c
o
as

'';:;

,~

Q.
Co
~

"EXTENDED ACCESS CYCLE
state 5:
RASI := (COUNT-5) ,low' RESET;
MSEL- := (COUNT-6) 'high' RESET;
CAS( := (COUNT-7) ,low' RESET;

DSACK :" (COUNT==7) 'low' RESET;
11:- (COUHT-8) 'low & RESET;
11- := (COUNT==10) , high;
DSACK :- (COUNT-IO) , high;
inCOUHT-IO) , RESET then 3 else 5;

3-97

"HIGH SPEED ACCESS
State 6:
II := (COUH'l==2) & lOll & RESET;
11- := (C00HT==4) & high;
DSACK := iCo0HT==4) & high;
inCOONT-4) then 3 elae 6;
"HOHL REl'RESH CYCLE
State 7:
AGREQ :- AS

'loll & RESE!;
:- (COmr.r-O) 'loll & RESE!;
:= (COUNT""1) & lOll 'RESET;
:= (COUN'J'-3) 'loll 'RESET;
:- (C01lHT=-5) 'high;
:" (COUN'J'==5) 'high;
Me( := (C01JHT=a6) 'high;
RASI :'" (COOHT==9) & lOll 'RESET;
MSEL- :- (C01JHT=alO) , high i RESET;
CASI- :- (COOHT==ll) 'loll & RESET;
DSACIC := (COIlN'l'-=ll) 'loll 'RESET;
11:= (C01lHT==12) & lOll 'RESET;
11- := (C01lHT==14) , high;
DSACK :- (COUH'l-=14) , high;
if (c01lHT==6) " (122 t AGREQ) then 0 elae 7;
if (COUN'J'....14) then 3 elae 7;
11:1RASIRrCRFCRASI-

"Em:HDED REFRESH CYCLE
State 8:
RASI :- (cotJm'---l) 'high;
MSEL- :- (C01lHT==1) 'loll;
CASI- := (COUN'J'-1) & high;
if (Cotnrz-3) then 7 else -8;

I

l>

"0

"2.

teat_VIlctora ' KOHL ACCESS CYCLE'

...0'~'

([OSC, RESET,122,RII,REFREQ,AS,HSA, SYSCLK,COUN'J')
(clk,
L , X ,X, X
, X,
(clk,
H , X ,X, H
, L,
(clk,
H , X , X, H
, H,
(clk,
H , L ,X, X
, X,
(elk,
H , X ,X, X
, X,
(clk,
H ,X, x, X
, X,
, X,
(clk,
H ,X, X, X
(clk,
H ,X, X, X
, X,
(clk,
H , X , X, X
, x,
, X,
(clk,
H , X , X, X

::::s

:::a
CD

"0

o

~

(I)

-) (RrC,RASI,MSEL,CASI,MC1,II,DBACK,STATE II
X, X, X ) -) ( H, H, L, 8 ,-H ,H,
X, X, 0 ) -) ( H, H, L, 8, H ,8,
X, H, 0 ) -) ( H, H, L, H, 8 ,H,
X, X, 0 ) -) ( H, H, L, H, H ,H,
X, X, 0 I -> ( H, L, L, 8, 8 ,H,
X, X, 1 I -> ( H, L, 8, 8, H , H,
X, X, 2 I -> ( 8, L, H, L, H ,8,
X, X, 3 I -> ( H, L, H, L, 8 ,L,
X, X, 4 I -> ( H ,L, H, L, 8 ,L,
X, X, 5 I -> ( 8, L, H, L, H ,H,

H
H
H
H
H
8
L
L
L
H

,
,
,
,
,
,
,
,
,
,

0
0
1
2

2'
2
2
2
2
3

teat VIlctora 'HOWING S'lATE 4 IIITH EX'l'EHDID ACCESS REQUES'l'
([OsC,RESET,122,RII,RErREQ,AS,HSA,SYSCLK,COUNTI -> (RrC,RASI,MSEL,CASI,MC1,II,DSACK,STATE ))
(clk,
8 ,H, X, 8
, H, X, H, 0 I -> ( 8, L, B, L ,-8 ,H, H , 4
(clk,
'8 , L ,X, X
, X, X, X, 0 I -> ( B, L, H, L, H ,8, H , 4
(clk,
R , X ,X, X
, X, R, X, 1 I -) ( H, H, L, H, R ,H, R , 5

3-98

I;
I;
I;
I;
I;
];
];
];

I;
I;

test vectors 'EXTENDED ACCESS'
( [OSC, RESET, A22, RII, REFREQ, AS, lSA, SYSCLK, COUNT]
, X,
[elk,
I , X, X, X
, X,
[elk,
I , X, X, X
, X,
[elk,
I , X, X, X
, X,
[elk,
H , X, X, X
, X,
[elk,
H , X, X, X
, X,
[elk,
H , X, X, X
, X,
[elk,
H , X, X, X
[ellt,
, X,
H , X, X, X
[elk,
, X,
H , X, X, X

-) [RFC, RASI, MSEL, CASI, Mel, II, DSACK, STATEJ )
X, X , 2 ] -) [ H , I, L , H , I ,H,
X, X , 3 I -) [ I , H, L , H , H ,H,
X, X , 4 I -) [ I , H, L, I , H ,H,
X, X , 5 ] -) [ I , L, L, I , H ,H,
X, X
6 ] -> [ I , L , I, I , B ,H,
X, X , 7 ] -) [ B , L, H , L , H ,H,
X, X , 8 ] -) [ B , L , B , L , 8 ,L,
X, X , 9 ] -) [ H , L, B , L , H ,L,
X, X , 10 I -) [ 8 , L , B, L , B ,H,

,

I
I
H
H
H
L
L
L
H

test vectors ' HOLDING STm 4 tilTH HIGH SPEED ACCESS REQUEST'
([OSC,RESET,A22,RII,REFREQ,AS, HSA, SYSCLK,COUNT] -) [RFC,RASI,MSEL,CASI,MC1, II,DSACK, STATEJ)
[elk,
, 8, X , H , 0 I -) [ H , L , H , L , I,H, H
8 , H , X, H
, X,'X , X
[elk,
0 I -) [ H , L , H , L , I ,H, H
H , L , X, X
, X, L, X , 1 I -) [ H , L, H , L , B ,H, L
[ellt,
H , L , X, X

,

test vectors ' HIGH SPEED ACCESS'
([OSC,RESET,A22,RII,REFREQ,AS, HSA, SYSCLK,COUNT]
[elk,
H , X, X, X
, X,
[elk,
H , X, X, X
, X,
, X,
[ellt,
8 , X, X, X

-) [RFC,RASI,MSEL,CASI,MC1, II, DSACK, STATEJ)
X, X
2 I -) [ H , L, H , L , H ,L, L
X, X
3 ] -) [ H , L, H , L , 8 ,L, L
X, X , 4 ] -) [ H , L, H , L , H ,H, B

,
,

test vectors ' NOH-MEMORY ACCESS FOLLOlIED BY REFRESH REQUEST'
([OSC,RESE7,A22, RII, REFREQ,AS,HSA,SYSCLK,COOHT] -) [RFC,RASI,MSEL,CASI,Mel, II,DSACK, STATEJ)
, H, X, H , 0 ] -) [ 8 , L, 8, L, H ,8,
[elk,
H , H , X, H
, X, X, X , 0 ] -) [ H , H , L, H , 8 ,H,
[ellt,
H , H , X, X
, L, X, X
[ellt,
0 ] -) [ H , H, L , H , H ,B,
H , X, X, H
, X, X, L
[ellt,
H , X, X, H
0 ] -) [ B , H, L , H , H ,B,
(ellt,
0 ] -) [ B , H, L , H , H ,H,
, X, X, X
B , X, X, L

,
,
,

test vectors ' NORMAL REFRESH CYCLE'
([OSC, RESET,A22, RII,REFREQ,AS,HSA, SYSCLK,COUNT]
(elk,
H , X, X, X
, L,
[elk,
, L,
H , X, X, X
[elk,
, L,
H , X, X, X
, L,
(elk,
H , X, X, X
[elk,
H , X, X, X
, L,
, L,
[elk,
H , X, X, H
[ellt,
, L,
H , X, X, X

-) [RFC,RASI,MSEL,CASI,MC1, II,DSACK, STATEJ)
X, X , 0 ] -) [ H , 8 , L, 8 , L ,H,
X, X , 1 ] -) [ B , L , L, H , L ,8,
X, X , 2 ] -) [ B , L , L, H , L ,H,
X, X
3 ] -) [ L , L , L , H , L ,H,
X, X , 4 ] -) [ L , L , L, H , L ,1,
X, X
5 I -) [ B , H, L, H , L ,H,
X, X , 6 ] -) [ B , H , L, B, B ,H,

,

H
H
H
H
H

8
8
8
H
H
H
H

,
,
,
,
,
,
,
,
,

5
5
5
5
5

]1

II
II
II

5
3

]1
]1
]1
]1
]1

,
,
,

4
4
6

II
II
II

,
,

6
6
3

II

,
,

4
0
0
0

]1
]1
]1
]1
]1

,

,
,
,

,
,
,
,
,
,

5
5

7

7
7
7
7
7
7
0

]1
]1

]1
]1
]1
]1
]1
]1
]1

I...
...0en

C.
CD

a:
C
0

'.;I
CIS

,~

C.
c.
 (RFC, RASI,MSEL, CASI,l«:l, II, DSACI(, S'lATE

(elk,
(elk,
(elk,

8 , X , X, 8
H , X , X, 8
H , X , X, L

, X, X,
, L, X,
, X, X,

((OsC,RESET, 122, RII, REFREQ,AS, BSA, SYSCLK, CO\IH'r] -) (RFC,RASI,MSEL,CASI,lI:l, II,DSACK, STATE

I

(elk,

(elk,
end SCDECODE

3-100

B
B
8
8

,
,
,
,

X,
X,
X,
X,

X,
X,
X,
X,

X
X
X
X

,
,
,
,

X,
X,
X,
X,

X,
X,
X,
X,

B
B
B
B
B
8
8
8
8
B
H
8
L
L
L
B

,
,
,
,
,
,
,
,
,

,
,
,
,
,
,
,

11

L, 0 ] -> ( 8, L, B, L ,-8 ,8, 8
X, 0 ] -> ( 8, L, 8, L, 8 ,8, H
X, 0 ] -) ( 8, L, 8, L, 8 ,8, 8

test vectors ' EXmNDID REFRESB CYCLE'
(elk,
(elk,

11

B ,B;
L ,B,
L ,8,
L ,B,
L ,B,
L ,8,
L ,8,
8 ,8,
8 ,B,
8 ,H,
B ,H,
B ,8,
B ,8,
8 ,L,
8 ,L,
B ,8,

X, 0
X, 1
X, 2
X, 3

]
]
]
]

->
->
->
->

( 8,
( 8,
( B,
( 8,

L,
8,
B,
8,

8,
L,
L,
L,

11

L ,-8 ,8,
8, B ,B,
8, 8 ,8,
8, R ,B,

8
R
8
8

7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
3

,
,
,

,

,
,
,

];
];
];
];

];
];
];
];
];
];
];
];
];
];
];
];

3
3
8

];
];
];

8

];
];
];
];

8
8
7

APPENDIXB
NAME
PARTNO
DATE
REV
DESIGNER
COMPANY
ASSmLY
LOCATION

,I
,I,I
,I,I

SCDECODE;
TIO004;
05,07,87 ;
01 ;
Breun i nger ,Peprah;
Texas I nstrullents;
None;
Dallas;

/ , . flf' ,.11 flf •• If . . If I " ' I I ' II Iff I. I •• Ilf ••• If If II ••••

I'
I'
"

"

'f' ••••••• , ••• , , .. 1 •• , . , . , ' . . ' . .

Static Colulln Decode

This Is an eXaliple of how the PSG507 can be used to generate the
required mellory tilling control signals (RAS. CAS. "SEL etc) for static
colulln decode IlIPlellentation using the ALS6301. ALS6310 and the AlS630
AlS6300. I n a system env Ironment.

/ , . Ilflf Iff.f ••• , . , •••••• If

f. Iff. Ilf III •••••• ,,"

"

Allowable Target Device Types:

'"

Inputs

I., Iliff. fll'

.f.

I,I,1,
I,I,i,
I,I,
"
I,
"

Iff. ".1 •• ,,1,,1.1 "11'/

TEXAS INTSRUMENTS PSG507

,1.".,.'. If ".' ••••••• ",,1 'flfl" f"f".I.flf. , ••••••••••••• 'fll •• ,'.' •••• I., •• II •••• ,/

pin
pin
pin
pin
pin
pin
pin
pin 18

'"

pin
pin
pin
pin
pin
pin
pin

Outputs
8

9
10
11
13
14
15

"'

"'

OSC
RESET
AZZ
RW
REFREQ
AS
HSA
SYSClK

" Oscillator
" Systell Reset - when lOll
" IO!!" - Me.ory access
Read, Write Enable
Refresh Request
Addr Strobe - access request
" High Speed Access
System Clock - (OSCJ2)

,I,I
,I
,I

I,I,
"
"I,
"
"

"

I

US

't
0
c.
CD

RFC
RASI
NSEl
CASI
NC1
W
DSACK

'" Node Declarations " '
pinnode [33 •• 38] = [CO .. 5]
pinnode 39
= SClRO
pinnode 41
= CNTHOlDO
pinnode 42
= CNTHOlDI
node
[P3 .. 0]
node
AGREQ

" Refresh COIIplete
" ROil Address Strobe
Multiplexer Select
Colulln Address Strobe
Node Control
" IIrlte
" Data Strobe Acknowledge

,I,I
,I
,I

Sui It-in 6-Bit counter

I' Counter Cc I ear- non regi stered
" Counter Hold
" Counter Hold
I' Buried State
Access Grant

,I

- non registered
- registered
Registers
Request

I,"
I,I,""
"
I,I,
I,
I,""

a:
C
0

'';;
CIS

.g

Q.
C.

c:(

3-101

, .. Declarations and lnterlaediate Variable Definition '"
field COUNT
= [C5 •• 0]
field STATE
= [P3 •• 0]
$deflne STO
'b'OOOO
$deflne STl
'b'OOOI
$define ST2
'b'OOIO
$define 513
'b'OOII
$define 514
'b'OIOO
$define ST5
'b'OIOI
$define ST6
'b'OliO
$define ST1
'b'OIII
Sdefine ST8
'b'IOOO
" BUILT-IN COUNTER CONTROL EQUATIONS '/
SCLRO

= !RESET
, ST2 & COUNT:'d'5
• ST4 & COUNT:'d'O
I ST5 & COUNT:'d'IO
, ST6 & COUNT: 'd' 4
I ST1 & COUNT: 'd'6 & (Al2 & AGREQ)
• ST1 & COUNT: 'd' 14
f ST8 & COUNT:'d'3;

CNTHOLDl.s

I

CNTHOLOl.r

= !RESET
• ST2 & COUNT:. 'd'S
,514 , COUNT:'d'O
t ST5 & COUNT: 'd' 10
, ST6 & COUNT: 'd' 4
I ST1 , COUNT:'d'6 , (A22 & AGREQI
• ST7 , COUNT: 'd'14
, ST8 & COUNT:'d'3;

= STO
• STl
I ST3
• ST3

& !REFREQ & RESET

"
"
"

""/' Set count hold while clearing

"

'/

" the counters accordingly.

"
"

"/'
"

"
"

""/'

"
"
Reset
Reset
Reset
Reset

count
count
count
count

hold
hold
hold
hold

on
on
on
on

Iff

3-102

"
"
"
"

""/'

"
"
/'
"

& !A22 & RESET
& !REFREQ & RESET
& REFREQ & AS
& SYSCLK & RESET;

"

" Clear counter when RESET is low
" and during transitions at the end
" the Indicated states and counts.

State Hach i ne Equat ions .. ,
sequence STATE (
present STO:
iflREFREQ & liAS ,!SYSCLK))
if(REFREQ & AS & SYSCLK & RESETI
i fI ! REFREQ & RESET)
default

next
next
next
next

present STl:
iffCOUNT:'d'O & !A22)
IfICOUNT:'d'O & A22)
default

next ST2;
next STO;
next STl;

present ST2:
" NORm ACCESS CYCLE "
if(COUNT:'d'OI & RESET
ifICOUNT:'d'I)
iffCOUNT:'d'21 & RESET
ifICOUNT:'d'31 & RESET
if(COUNT:'d'S)
default

next
next
next
next
next
next

STO;
STl;
ST1;
STO;

ST2 out
ST2 out
ST2 out
ST2 out
ST3 out
ST2;

!RASI;
HS[L;
[!CASI.IDSACK];
IW;
[W.DSACK)i

transition
transition
transition
transition

to
to
to
to

ST1
ST2
ST8
514

"
"

'/

"

present S13:
/" HOLDING STATE
"/
ifl!AS t ISYSCLK) & RHREQ & RESET
if(REFREQ & AS & SYSCLK & RESET)
if I !REFREQ & RESET)
default

next
next
next
next

S13;
SU;
ST8;
S13;

present 514:
if(COUNT:'d'O)
if(COUNT:'d'O)
if(COUNT: 'd'l)
If(COUNT:'d'l)
default

next
next
next
next
next

STO out [RASl,!NSEL,CASl];
514;
ST5 out [RASl,!NSEL,CASl];
ST6 out I DSACK;
S14;

& AZZ & RESET
& !AZZ & RESET
& HSA & RESET
& IHSA & RESET

present STS:
/" EXTENDED ACCESS CYCLE "/
if(COUNT:'d'S) & RESET
if(COUNT:'d'6) & RESET
if(COUNT:'d'71 & RESET
if(COUNT:'d'8) & RESET
if(COUNT:'d'IO) & RESET
default

next
. next
next
next
next
next

present ST6:
/" HIGH SPEED ACCESS
"/
If(COUNT: 'd'Z) & RESET
If(COUNT: 'd' 4)
default

APPEND
APPEND
APPEND
APPEND
APPEND

RAS!.s
V.S
MCI_.s
PO_.r
P3_.r

= !RESET;
= I RESET;
= !RESET;
= IRESET;

APPEND
APPEND
APPEND
APPEND

I RAS I;
NSEL;
[lCASI,!DSACK];
IV;
[V,DSACK];

next ST6 out !V;
next ST3 out [V,DSACK];
next ST6;

present 517:
/" NORm REFRESH CYCLE '/
if AS
if(COUNT:'d'O) & RESET
if(COUNT:'d'l) & RESET
if(COUNT: 'd'3) & RESET
if(COUNT:'d'S)
IfICOUNT: 'd'6) & (AZZ , AGREQ)
IfICOUNT:'d'6) & IAZZ & !AGREQ
if(COUNT: 'd'9) & RESET
if(COUNT: 'd'IO) & RESET
if(COUNT: 'd'll) & RESET
if(COUNT:'d'IZ) & RESET
if(COUNT: 'd'14)
default
present ST8:
/" EXTENDED REFRESH CYCLE
If(COUNT:'d'l)
If(COUNT:'d'3)
default

ST5 out
ST5 out
ST5 out
ST5 out
513 out
ST5;

next
next
. next
next
next
next
next
next
next
next
next
next
next

S17 out
517 out
517 out
S17 out
S17 out
STO out
517 out
517 out
517 out
ST7 out
517 out
S13 out
S17;

!AGREQ;
!NC U
!RAS!;
!RFC;
[RfC,RASl];
NC U
NC U
!RASI;
NSEL;
[lCASI,!DSACK];
!V;
[V ,DSACK];

I
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Q.
G)

a:
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;:;
CO

.sa
Q.
Q.



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CD

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en

3-108

Mechanical Data

4-1

Contents
Page

Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
Sockets . , . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . • . . . . . . . . . . . . . . 4-25

4·2

MECHANICAL DATA

OW plastic "small outline" packages
Each of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulated
within a plastic compound. The compound will withstand soldering temperature with no deformation, and
circuit performance characteristics will remain stable when operated in high-humidity conditions. Leads
require no additional cleaning or processing when used in soldered assembly.

OW PLASTIC PACKAGE
(20-pin package used for illustration)

2,65 (0.1041

~r

70NOM

9,0 (0.3541

4 PLACES

2'35~J~

~,I
0,10 (0.004)

0,185 10.031)

,

I"

II
-.j

0,510.021 X

45"LC-~---'

rl::r-

~1~70NOM

r
~

0.490(0.019'

tt-- 0,350 (0.014)

40:t40

-) I
jl

'PLACES

0,230 (0.0091

'

~jf-I

P
.

1,27 (0.0501
0,40 (0.016)

1t--ti-',27 10.0501 TP (See Note AI

~
DIM

A MIN
A MAX

16

20

24

2St

10.16

12,70

15,29

17,68

(0.400)

(0.500)

(0.602)

(0.69S)

10,36

12,90

15.49

17,88

(0.408)

(0.508)

(0.S10)

(0.704)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

tThe 28-pin
NOTES: A.
B.
C.
D.

package drawing is presently classified as Advance Information.
Leads are within 0,25 (0.010) radius of true position at maximum material dimension.
Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed 0,15 (0.006),
Lead tips to be planar within ±0,051 (0.002) exclusive of solder.

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

as
as

~

o

4-3

MECHAIIICAL DATA

DWplastic "small

outline~'

packages

Each of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulated
wit/1in a plastic compQund. The compound will withstand soldering temperature with no deformation, and
circuit performance characteris~ics will remain stable when operated in high-humidity conditions. \..eads
require no additional, cleaning or processing when used in soldered assembly.

24-PIN

ow

PACKAGE

15'5(O'6101~

15,310.6021

-----

13

0 •• (0.021

I:~:::~::I
=-:-1. . 1

LI:z---

k.lJ. . JJlib,

x ...

-r-

~
o· •••
0,78510.031)

0,585

IO.~231

NOM
\ . •7·PLACES

~

. 1.27 {O.05OI

0,230 (O.OO!II

Q.4D"iii.Oiii

All LINEAR DIMENSIONS ARE IN MllliMETER$ AND PARENTHETICAllY IN INCHES

IIs:

NOTES: A.
B.
C.
D.

Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed' b, 15· (0.006).
Leads are within 0,25 (0.010) radius of true positiofl at maximum material dimension.
lead tips to be planar within ±0.051 (0.002) exclusive of solder.

CD

n

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:J

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4-4

TEXAS ."

INSTRUMENTS
POST OFFICE SOX'665012 • DALLAS; TEXAS 76265

MECHANICAL DATA

FK ceramic chip carrier packages
Each of these hermetically sealed chip carrier packages has a three-layer ceramic base with a metal lid
and braze seal. The packages are intended for surface mounting on solder lands on 1,27 (O.050-inchl
centers. terminals require no additional cleaning or processing when used in soldered assembly.
FK package terminal assignments conform to JEDEC Standards 1 and 2.

FK CERAMIC CHIP CARRIER PACKAGES
(2B-terminal package shown)

-:3

Io--r

r'i :~'-_ _ ~
ili1J

CERAMIC CHIP CARRIERS
JEOEC
OUTLINE
DESIGNATION'

NO.OF
TERMINALS

MSOO4CB

20

MS004CC

28

A

B

MIN

MAX

MIN

MAX

8,69
(0.342)
11,23
(0.442)

9,09
(0.358)
11,63
(0.458)

7,80
(0.307)
10,31
(0.406)

9,09
(0.358)
11,63
(0.458)

*AII dimensions and notes for the specified JEDEC outline applv.

~ORNER

A

0.71 (0.028)
0,56 (0.022)

~~

I
"1

1,63 (0.064)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

TEXAS ~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 16266

4-5

MECHANICAL DATA
I

FN plastic chip carrier package
Each of these chip carrier packages consists of a circllit mounted on a lead frame and encapsulated within
an electrically non conductive plastic compound. The com'pound withstands soldering temperatures with
no deformation, and circuit performance characteristics remain stable when the devices are operated in
high-humidity conditions. The packages are intended for surface mounting on solder lands on 1,27 (0.050)
centers. Leads require no additional cleaning or processing when used in soldered assembly.

FN PLASTIC CHIP CARRIER
(28-termlnal peckage used for iII!'stratlonl

r

4.50 10.1771
4.24 (0. 1671

Ii' .

122 (00481
1.07 (0.0421 X45'

V
[ 5

•

1.35 (0.0531 X 45'
1.19(0.0471

0
3

2

1

28

27

26

1

I. r-+ ~:~~o~~if~LI
----rJ

Il

L...1/O.69 (0.0271 R

25

[ 6

2'

[ 7

23
22

ll::

21
20

-- - -

I'
12

1.

13

14

15

16

17

18

I

.r~1' 0.25
(0.0101
3 PLACES

.B

~"___________ A_(s_e_e_N_ot_e_A_I__~..
1

NO. OF
TERMINALS
20
28
44

II:s:

68

64

MAX

MIN

R MAX

MIN

MAX

1~,O3

B.B9

9.04

7,87

8,38

10.3961

(0.3561
11.58

10.3101

(0.4561

(0.4101

10.3301
10.92
(0.4301
16.00
10.6301

10.9851

10.4951
17.65
10.6951
25.27
10.9951

(0.3501
'1,43
(0.4601
16.51
10.6501
24.13
10.9501

30.10

30,35

29,21

(1.1851

11.1951

11.1501

!

C

MAX

9,78

25,02

(See Note BI

SEATING PLANE
(See Note CI

10.3851
12.32
10.4851
17.40
(0.6851

12,57

~:',::~~::U'"

'--~..;::::;~

8

A
MIN

.'

'd

16.66
10.6561
24.33
10.9661
29.41
11.1581

10,41

15.49

(0.6101
23.11
(0.9101

23,62

10.9301

27,69

28,70

11.0901

(1.1301

0,81 (0.032)~
0,66 (0.0261

~T
1.52 (0.0601 MIN

I-.i.
I ~ (0.0251 MIN
0,51 (0.020I-oj I ~
0,36 (0.0141
I
LEAD DETAIL

CD

(')

::T
I»
~

ri'

!!.

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTES: A. Centerline of center pin each side is within 0,10 (0.004) of package centerline as determined by dimension B.
B. Location of each pin is within 0,' 27 (0.005) of true position with respect to center pin on each side.
C. T~e lead contact points are planar within 0,10 (0.0041.

c
!I»

4-6

TEXAS ...,
INSlRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76266

MECHANICAL DATA

J ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is'intended for insertiQn in mounting-hole rows
on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("'bright-dipped") leads require no additional
cleaning or processing when used in soldered assembly.

14-PIN J CERAMIC
1.--19.9410.785) ~
I19.18 (0 755)

i:::::::
I@@@@@cv®

0.63(0.025)RNOM
7.87 (0 310)

I

11-_ _'it-.;;7",.11;;-:(",0.;;;;8",,~ (0.290)

-1 J:j
,ffi
L~

__

0 0 0 0 0@0

6.22 (0.245)
1.27

0.51 10.020) MINl

10.050) NOM

\-SEATINGPLANE

14PLACES~10.3610.014)
020 (0 0081

14 PLC:CES

lw ~

8-

5.0~~:00)

3.30 (0.130)
MIN

11

I-' 1.78 (0.070) MAX 14 PLACES

----

H

II

_u~u

J-.{ J-1

W s~~t!~JT

Hu 1( I'" j.0.6~41~~~~)E~IN
U...JL
--, r-

058 (0023)
0;38 (0:015) 14 PLACES

2.54 10.100)
1,78 (0.070)
4 PLACES

PIN SPACING 2.54 (0.100) T.P.
(See Note AI

Falls Within JEDEC TO-116 and EIA MO-OO 1AA Dimensions
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTE A: Each pin centerline is located within 0.25 (0.010) of its true longitudinal position.

..
as
as

C

cau

'2
as

.c
u
CD

:!

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

4-7

MECHANICAL DATA

J ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped") leads require no additional
cleaning or processing when used in soldered assembly.

l6·PIN J CERAMIC

ktbtfw-,~.

'!.

'!.

7,1fl10.310)
7,37 10.290)

7,1110.280) •
6,22 10.245)

l. JI \~n",~'
16 PLACES

I\-- 0.3610.014)

,....I.

0,20 10.008)
16 PLACES

-1 r

CD@@0®@0®
5,oato.200)

1.7810.070) MAX 16 PLACES

~ AA~ ADO

SE~i~":T

R,

j::.~~~ l~1 ~I U~~rt 1jli--O'~i~~~~k~'N

3,3OM\~ 130)

0,305 10.012) MIN
4 PLACES

~

PIN SPACING 2.5410.100) T.P.
lSee Note A)

g:~: 19:9~~!
-I ~ 16 PLACES

~:~ :~:~~: 4 PLACES

• For memories of 64 bits and up, a few MSIILSI products in Series 54174 and Series 54S/74S that are
derived from memory circuit bars, and complex HCMOS parts. this maximum is 7,62 (0.3001. All other
dimensions apply without modification.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN )NCHES

IIs:

NOTE A: Each pin centerline is located within 0,25 (0.0101 of its true longit,udinal position.

CD

()

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:::I

(;'

!.

...C
&»
&»

4-8

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265

MECHANICAL DATA

J ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped") leads require no additional
cleaning or processing when used in soldered assembly.

18·PIN J CERAMIC

7,87 (0.310)

7,37 (0.290)

7.62 10.300)
6,22 (0.245)

-1 t

000000000

l!tt
~~5: S:t;~~G 3'30A::~~OO-)

MAX 18 PLACES

-1,27 (0.060) NOM

GLASS
II'~;;;;;;~~~;;;;;;~---,SEALANT

--

18 PLACES

-,..-_ _ _ _ _ _ U

..IlL.. 0,356 (0.014)

~\

0.203(0.008)

f

18 PLACES

-H

I~t!--+tl--~:=~~.g~~)

MIN

0,58 (0.023)

0.38 10,015)
18 PLACES

PIN SPACING 2,54 (0.100)
(See Note AI

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY )N INCHES

NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.

a
!ca

C

TEXAS ",

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

4-9

MECHANICAL DATA

J ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped") leads require no additional
cleaninll or processing when used in soldered assembly.

20-PIN J CERAMIC

g

'l

'l

~:~~:~:~~~:

7,62 (0.300)
6,22 (0.245)

1

1.78 (0.070) MAX 20 PLACES

1,27 (0.050) NOM

r:;;t~~;;:;:;;:;;;;;:;;~~

~
105"

..

_s:t;~~G -~--.-----.,-

"Sir

MIN

20 PLACES

, . -_ _' - -_ _

\\
0,36 (0.014)
.-.I~0,20 (0.008)

GLASS
SEALANT

lioe-H---+t-+ft- ~:~~~g~~) MIN

•

0,58 (0.023)
0,38 (0.015)
20 PLACES

I

20 PLACES

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.

c

;

4-10

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. tEXAS 76285

~

"~~~V~

MECHANICAL DATA

JT ceramic dual-In-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7,62 (0.300) centers. Once the pins are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-diped") pins require no additional
cleaning or processing when used in soldered assembly.

24-PIN JT CERAMIC
! - - - - 3 2 . 5 1 (1.2801 MAX

-----.I

,6'~;~"'~~'C:::::::::::I
@@@@@®®®®®®®

7,'2'0,3001
',22'0245)

1

0000®®0®®®@@

0,38 (0015)

1.27 (0.050) NOM

MIN

1,78 (0.070)

~

~24PLAces

GLASS
SEALANT

5,08(0.200)
MAX

SEA TlNG---.:-I----,rl-1
PLANE

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.

I..
ca
ca

C

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u
'2
ca
..c
u

CD

:IE
TEXAS

~

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

4-11

MECHANICAL DATA

J ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 15,24 (0.600) centers. Once the pins are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-diped") pins require no additional
cleaning or processing when used in soldered assembly.

24-PIN JW CERAMIC

~---------~~~:~:~~:----------~

®@@@@@@@@@@@

0,63 (0.025) R
NOM

1.7Slt .•7.)
0,51 (O.020)

I I

I '

~::~ :~:~~: ~ 1-1~
I
24 PLACES

PIN SPACING 2,54 (0.100) T.P.
{5ee Note A)

Falls within JEDEC MD-015AA dimensions
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.

II
3:
CD

()

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4-12

TEXAS . "

INSIRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 752,?5

MECHANICAL DATA

JD ceramic side-brade dual-in-line packages
This is a hermetically sealed ceramic package with a metal cap and side-brazed tin-plated leads.

JD CERAMIC-SIDE-BRAZE

Io---b
_
. _
-_BMAX==~II
_

.

~~~~nD[Jt
bJl
OR NUMBERI

C0------------------~

It

It

---L

t
.
1-ffimvvmtW1llt
~
~A___oI

II

SEATING
PLANE

0.38100151

-0011<- 0.20 CO.0081

0.7610.0~01:!

0.51CO.020IMIN

_

~::

,

1.7B 10,0701

1_ _ I

~

1.9141~i.~~~sMAX

-01

1--1

--..j

1--2.5410.1001 NOM
PIN SPACING
(See Note AI

j

3.18

16

18

20

22

2.4

-0.25 (-0.010)

7.62
(0.300)

7.62
(0.300)

7.62
(0.300)

10.16
(0.400)

7.62
(0.3001

B (MAX)

20.57
(0.810)

23.11
(0.9101

25.65
(1.010)

27.94
(1.1001

30.86
(1.215)

C (NOM)

7.37
(0.290)

7.37
(0.290)

7.37
(0.290)

9.91
(0.390)

7.37
(0.290)

~N)

24

28

40

48

52

64

-0.25 (-0.010)

15.24
(0.600)

15.24
(0.600)

15.24
(0.600)

15.24
(0.600)

15.24
(0.600)

22.86
(0.900)

8IMAX)

31.8
(1.250)

36.8
(1.450)

52.1
(2.050)

62.2
(2.450)

67.3
(2.650)

82.6
(3.250)

C (NOM)

15.0
(0.590)

15.0
(0.5901

15.0
(0.590)

15.0
(0.590)

15.0
(0.5901

22.6

DIM
A + 0.51 (+ 0.020)

10.~251 MIN

0.5310.0211
0.3810.0151

~NI

DIM
A +0.51 1+0.020)

5.0810.2001
MAX
•

(0.8901

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTE A: Each pin centerline is located within 0,25 (0,0101 of its true longitudinal position.

II...
as
as

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u

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as

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TEXAS

~

INSTRUMENlS
POST OFFICE BOX 656012 • DALLAS, TeXAS 76285

4-13

MECHANICAL DATA

JK ceramic dual-In-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 10,16 (0.400) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped") leads require no additional
cleaning or processing when used in soldered assembly;
24-PlN JK CERAMIC

24 E::ES

\\

~~36

(0.014)

~~ 0.20 (0.008)

r-lJ L
T

24 PLACES

0,305 10.0121 MIN

Ir

------II~--'-'---1f+-_O.68 (0.0231

PIN SPACING
I

----II----

°2!8pt~g~:)

2,54 to.100) T.P.
tSee Note AI

4 PLACES

2.03 (0.080)
MAX
4 PLACES

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTE A:

Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.

IIs:
CD

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....

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4-14

TEXAS ."

INSfRUMENlS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265

MECHANICAL DATA

JL ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap with a window, and
a lead frame. Hermetic sealing is accomplished with glass. The package is intended for insertion in mountinghole rows on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension is
provided to secure the package in the board during soldering. Tin-plated ("bright-dipped") leads require
no additional cleaning or processing when used in soldered assembly.
20-PIN JL CERAMIC

I-

24,7610.975)
23.62 (0.930)

------11

-"~'-{~~~2:J

0000®0000@

0,58 (O,023)

0,38 (0.0151
20 PLACES

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTE A:

Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.

...co
CO

C

TEXAS . "

INSlRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

4-15

MECHANICAL DATA

N plastic dual-in-Iine package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.

14-PIN N PLASTIC

Ii. 7.62. 0.25
14----+lt-(0.30h 0.0101
6,35:!:. 0,25
(0.250.0.0101

(See Notes B and C)

Falls Within JEDECTO-116 and EIA MO-001AA Dimensions
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true )ongitudinal position.
R. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating
plane.

...C
I»
I»

4-'16

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TeXAS 75265

MECHANICAL DATA

N plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.

16-PIN N PLASTIC

7.62:!: 0.25
(0.3001; 0.010)
6,35 i 0,25
(0.250 ± 0.010)

2.0 (0.0801 NOM

0,84 iO.033) MIN

(See Notes 8 and Cl

Parts may be supplied In accordance
with the alternate side view at the
option of TI plants located in Europe.

In this case, the overall length of the
package is 22.1 (0.870) max.

ALTERNATE SIDE

view

--1
(O.~70J
f 0'51~~~201~1
-*-t-"",,78

MAX 16 PLACES

5.08 (0.2001 MAX

L
,....

L~
4 PLACES

0,84 (0.033) MIN
16 PLACES

---ll-- 0.533 (0.0211
0,381 (0.015)

16 PLACES
(See Notes Band C}
PIN SPACING 2.54 (0.1001 T.P.
(See Note Al

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTES:

A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.0201 above seating
plane.

TEXAS .."

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

...asas

C

4-17

MECHANICAL DATA

N plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
non conductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance chllracteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.

18-PlN N PLASTIC

7,62 t 0,25

(0.300 ; 0.0101

i----H--8,99 (0.275) MAX

_i

--I r-,,78

2,03 (0.080) NOM

L

0.25 (0.010) NOM

OOI
-SEATING PLANE 5.08 (O·'t MAX
_

~\

~

0,279 ± 0,076

(0011 ±0003)

18 PLACES
(See Notel B and C)

(0 070) MAX 18 PLACES

'O.51(00'OI~1
MIN

-*--J,

3,17 (0 125) MIN

-

L

~

~

.; PL.ACES

0.89(00351 MIN
18 PLACES

--l ~O.467tO,076
(0018 ± 0003)

1,91 (0 075)
023 (0 009)

r--

18 PLACES
(See Notes B and C)

PIN SPACING 2,64 (PlOD) T P
(See Note Al

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder· dipped leads.
C. When solder·dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0.51 10.0201 above seating
plane •

•
3iC
CD

n
::::r
m

=
5'

I!.
C
m

Dr

4-18

TEXAS ",

INSTRUMENTS
POST OFFICE SOX 866012 • DAUAS. TeXAS 75265

MECHANICAL DATA

N plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.

20-PIN N PLASTIC

Ii.

Ii.

8

'O';~::':~0I

7,1' (02BO)
6,61(0260)

--1

I
•

2,0 10 080) NOM

0,25 (0 010) NOM

-tlj

24.77 '0.9'5'
23,22(0.914)
jt-l,78 (0.070) MAX 20 PLACES

•

I

i~1
t

5,08 (0.200) MAX-*--SEATING PLANE

:.5~~N020)

~~~::l~:~~~:
20 PLACES

(SleNotes Band C)

3.9"0.1551
317 (0 125)
•
.
1,68 (0.066)
0,22 (0.009)

J.-

1.-.1..

I

0.8' '0.033) MIN
16 PLACES

--ojj.--0.53310.021'

j'
'I
PIN SPACING 2.54 (0.100) T.P.
{See Note Al

0,381 (0.015)
20 PLACES
(See Notes B and C)

4 PLACES

J~ ~
L
r-1,02 (0.040)
4 PLACES

VIEWA

Parts may be supplied in accordance
with the alternate stde view at the
option of TI. European-manufactured
parts may have pin 1 as shown in
view A. Alternate·side-view parts
manufactured outside of the USA
may have a maximum package length
of 26.7 (1.0501.

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTES:

A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating
plane.

II
....
ca
ca

o

"i

·cuca

.c
u
CD

:E
TEXAS .."

INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS. TEXAS 75285

4-19

MECHANICAL DATA

N plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation.
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended.for insertion in mounting-hole rows on 15.24 (0.600) centers. Once the leads are
compressed and inserted. sufficient tension is provided to secure the package in the board during soldering.
'
Leads require no additional cleaning or processing when used in soldered assembly.

28-PIN N PLASTIC
10------36.611.440) M A X - - - - - - - . f

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

II

NOTES: A. Each pin centerline is located within 0.25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solderwdipped leads.
C. When solder-dipped leads are specified. dipped area of the leaa extends from the lead tip to at least 0.51 10.020) above seating
plane.

3:
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4-20

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

MECHANICAL DATA

N plastic dual-in-line packages (continued)

24-PlN NT PLASTIC

1<-_ _ _ _ _ _ 31'8 (1.250) _ _ _ _ _ _--01
28,6 (1.125)

· · .'~::~" .~i~::.==i:VVVVVVVVVI
)<----->1-1--7,1 (0.280) MAX

0,38 (0.015)

00000000 \::..J
f9\ @@ ®

----I ~ 1--2,0 (0.080) NOM
F f M I N-01 10--- 1,78 (0.070) 24 PLACES
~ ~rr
1~1----1~,l-4~(0-.0-4~5)------------------~

~i

- :-To,25 (0.010) NOM 5,08(0.200)
MAX
/,

105°

U"'---- 90"
24PLACES

-SEATING PLANE·

~

1

]-

.11..--- 0 ,36(0.014)
If
0,25 (0.010)
24 PLACES
(See Note B)

.

T

_

I

4,06(0.160)
317 (0 125)
'
216 (0085)
0:71 (0:028)
4 PLACES

- ~

I

~

--I ~ 1,14 (0.045) MIN
24 PLACES
--11--- 0 ,533(0.021)

PIN SPACING 2,54 (0.100) T.P.
(See Note A)

0,381 (0.015)
24 PLACES
(See Note B)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTES:

A. Each pin cen'terline is located within 0,2510,010) of its true longitudinal position.
B. For solder-dipped leads, this' dimension applies from the lead tip to the standoff.

....CISCIS

Q

TEXAS . "

INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265

4-21

MECHANICAL DATA

NW plastic dual-in-Iine package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 15,24 (0.600) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additiomil cleaning or processing when used in soldered assembly.
NOTE: For all except 24~pin packages, the letter N is used by itself since only the 24-pin package is available in more than one row-spacing.

For the 24'pin package, the 7,62 (0.300) versio!' is designated NT; the 15,24 (0.600) version is designated NW. If no second
letter or row-spacing is specified, the package is assumed to have 15,24 (0.600) row-spacing.

24-PIN NW PLASTIC
1 - - - - - - 32,8

_.. .

~u~::~:::::::::]

\;.[:::~:;:~:~\;.

CD0@0®®0®®@@@

2,0 (0.0801 NOM

H

L...£.0.25 (0.010) NOM

-[I
~

~

---I

I02~1 ~~~~:3)

ISsa Notes Bend CI

1,,78 (0.0701 MAX 24 PLACES

L-~---,5,08 10200) MAX

-SEATINGPLANE-r0,5' 10.020) MIN

24 PLACES

90 0,28 t 0,08

11,290) M A X - - - - - - - I

@l@@@@@@@@@@)@

J

I I

JL

L J , '

0,467:t 0,076
(0.018:t. 0.003)

0,83 (0.033) MIN

-~~

J---1

317 (0 125) MIN

24 PLACES 2.42 (0 0951 MAX

. 24

P~ACES

4 PLACES

24 PLACES

PIN SPACING 2,54 (0.100) T. P.

(5 •• Notes B and cj

(See Note A)

All LINEAR DIMENSIONS ARE IN MIlliMETERS AND PARENTHETICAllY IN INCHES

IIs:

NOTES: A. Each pin centerline is located within 0,25 (0.0101 of its true longitudinal position.
B. This dimension does not apply for solder·dipped leads.
C. When solder·dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating
plane.

CD

n
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:::J

C:;"

!.

c

m
....
m

4-22

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265

MECHANICAL DATA

N plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation.
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 15.24 (0.600) centers. Once the leads are
compressed and inserted. sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.

40-PIN N PLASTIC

I'

53.1 [2.0901 MAX

'I

,,::~:~·~~t::::::::::::::::::[1o

-

@@@@@@@@

1.3/2.0
(0.05/0.081 T Y r 2
0.10/0,121
'

3.6/4.6
10.14/0.181

I

2.54
10.100) TVP NONCUMULATIVE

n n nw
~ ~

~~033

2.6713.61

~

10.02U DIA

10.106/0.1501

PRODUCTION DATA documents contain iolarmeti••
• urrelll II of publiml•• d.tto. Prod_ ••nf.rm to
spaciIiCltio•• por the tto"". of Te,," Instr....nts

=~i~·;':.~1.; ~'=::':r 111"::;:=:''' not

~

I

~~

18~

18

BODY MATERIAL
G - Glass Filled Epoxy
P - PBT Polyester
TI Socket

f""{!)~@-@-@':"o-@-@:-.-:-@-@~@-:@-@~o

B

Number of Pins
024 to 324

Grid

Body - PBT polyester UL 94 V-O
On request, G 10/FR4 or Mylar film
Outer sleeve - Machined Brass (QQ-B-626)
Inner contact - Beryllium copper (QQ-C-530) heat treated
Plating: (specified by part number)

I

Contact Loading Pattern

1.35

10.0&3) DIA

A

B

±0.010
(0.9501 24,13
(1.050) 26,67
(1.1501 29.21
(1.250) 31.75
(1.350) 34.29
(1.450) 36.83
(1.550) 39.37
(1.650) 41.91
(1.750) 44,45
(1.850) 46,99

±0.005 t
(0.800) 20.32
(0.900) 22,86
(1.0001 25,40
(1.100) 27.94
(1.200) 30,48
(1.300) 33.02
(1.400) 35,56
(1.500) 38.10
(1.600) 40,64
(1.700) 43.18

I

as

;
o

tNoncumulative
Dimensions in parentheses are inches
Consult factory for detailed information

TEXAS •

INSTRUMENTS
34 Forest Street. Attleboro, Massachusetts 02703

4-29

IC SOCKETS
SOJ BURN-IN/TEST
PERFORMANCE SPECIFICATIONS
Mechanical
Accommodates IC leads per specific IC device
Recommended PCB thickness range: 0.062 in to 0.092 in
Recommended PCB hole size range: 0.032 in to 0.042 in
Durability: 10,000 cycles; 20 mil max contact resistance
'
change
Insertion force: 1.3 oz per position max
Withdrawal force:· S.S grams per position min

Electrical
Contact rating: 1.0 A per contact
Contact resistance: 20 mil max initial
Insulation resistance: 1000 Mil per MIL-STD 202,
Method 302, Condition B
Dielectric withstanding voltage: 700 V ac rms per
MIL-STD 202, Method 301

Environmental
Thermal shock: 100 cycles, -25°C to +IS0oC, 1 hour
Temperature soak: IS00C for 1000 hours, SO mil max
change
Operating temperature: - 65°C to + ISO °C

PART NUMBER SYSTEM
CSJT

xxx

xx

xx

X

T
Body Material

MATERIALS
Body - PES glass, filled UL 94 V-O
Contact - copper alloy
Plating - overall gold plate min 4 /Lin over min 70 /Lin nickel
plating

Blank = G.F. PES
A = PPS R4-03
B = G.F. PEl
Body Variation

02 = Standard 1 forward!
backward insertion

03 = Special/orientation pin
04 = Special/high standoff
05 = Special/24-pin
06 '= Standard 2 forward
insertion. BECU
Contact Finish
37 = Overall gold plate 41'in
38 = Overall gold plate 30 I'in
57 = Selective gold plate 4 I'in
58 = Selective gold plate 30 I'in
Number of Contacts
3.00
10,1181

-....::::.. 2.53
4------20.310.8001-1- - - - _ " 10.0991

IIs:

02 VERSION SHOWN
~----,

TI SOJ series
SIZES: 20 pin
Z6 pin

20-PIN (02 VERSION) FOOTPRINT SHOWN

--r -@--------@--@--rtf
0,80

I

CD

::r
I»
::J

I

I

(0.1001

-t~'tl'
@-i----*@-1-@111"';:
I '

: , : !

C:i"

!.

I

I

I

! 5!

5!

I"!'
'1'1''':;

" I

...C
I»
I»

2,54

IM10.0321

ttt+t---- ---t+~t®l
~
I,

(')

5,08

I

-@---'
;'--tll---@-ll-Gl
,~.--~
I 54~ ,~
110.2001

1.27 '

Dimensions in parentheses are inches
Contact fa~torv for detailed information

4-30

PRODUCTIOI DATA doc....nts cont.in infor..dion
••rrant I. of pu.llcotion dot•. Protl.......iorll ta
.p..llinti••• par t .. tannl of T.... Instr...ents
otond.rd w.rrenty. Prod.ction pj'G....lng dot. oot
..._rily incl.do ltIIing of III porl..lttro.

10.0501

TEXAS

~

INSTRUMENTS
34 Forest Street. Attleboro, Massachusetts 02703

I

2
(01001
.

2.64
\ (0.1001
NO. 1 PIN

IC SOCKETS
DUAL·IN·LlNE
PERFORMANCE SPECIFICAnONS

C7X SERIES -

SCREW MACHINE

Mechanical
Accommodates IC leads 0.011 ± 0.003 in by
0.018 ± 0.003
Recommended PCB thickness range: 0.062 in to 0.092 in
Recommended PCB hole size range: 0.032 in to 0.042 in
Recommended hole grid 'pattern: 0.100 in ± 0.003 in each
direction
Vibration: 15 G, 10-2000 Hz per MIL-STD 1344A,
Method 2005.1 Test Condition III.
Shock: 100 G, sawtooth waveform, 2 shocks each direction
per MIL-STD 202, Method 213, Test Condition I
Durability: '5 cycles, 10 mil max contact resistance change
per MIL-STD 1344, Method 2016
Insertion force (C7X and C86): 16 oz (454 g) per pin max
Withdrawal force: (40 g) per pin min

Electrical

C7X SERIES - SCREW MACHINE
PART NUMBER SYSTEM

C7X

Contact rating: 1 A per contact
Contact resistance: 20 mil max initial
Insulation resistance: 1000 Mil at 500 V dc per
MIL-STD 1344, Method 3003
Dielectric withstanding voltage: 1000 V ac rms per
MIL-STD 1344, Method 3001.1
Capacitance: 1 pF max per MIL-STD 202, Method 305

(X)

1I
XX -

X

X

I

Environmental
Operating temperature: - 55·C to 125 ·C, gold; - 40·C
to 100 ·C, tin
Corrosive atmosphere: 10 mil max contact resistance
change when exposed to 22% ammonium sulfide for
4 hours
Gas tight: 10 mil max contact resistance change when
exposed to nitric acid vapor for 1 hour
Temperature soak: 10 mil max contact resistance change
when exposed to 105·C temperature for 48 hours

Materials (C7X and CB6)

PRECISION
MACHINED'
SLEEVE

PRECISION
FOUR-FINGERED
CONTACT

Body - PBT polyester UL 94 v-o
C7X Contacts - Outer sleeve: brass
Clip: BECU
Contact finish - clip 30 jLin gold over 50 jLin nickel or
50
jLin
tin/lead
over 50 jLin nickel
Specified by
Part Number - sleeve 1b "in gold over 50 jLin nickel
or 50 jLin tin/lead over 50 jLin nickel
C86 Contacts - Phosphor bronze base metal
C86 Contact-finish - Tin plate 200 jLin over copper flash

~;~e~;t"t:' ~.:10

Plating ISleeve/Clop)
Gold/Gold
5 - Tin/Gold

o-

Number of
Positions
S -

Variations
Solder Ta.l: 9
Pin length 0.125 Typ

Single-in-line package (where applicable I

Screw Machine Socket
1 - wire wrap
2 - solder tail

CB6 SERIES - STAMPED AND FORMED

II
...
ca
ca

C

CB6 SERIES
PART NUMBER SYSTEM

l
c

l86 lXX-

L

Variation

01 - Standard product
Number of positions
Tin Dual Beam Face Wipe

'ii
Co)
'2
ca

.c
Co)
CD

:E

TI Socket Series

PRODUCTIOI DATA documonts •••llil inf.rmotlon
curnnt II af publicltiDn date. Preducts canfarm to
speclficatians per the tarms of TIXI. Instruments
:':~::i;·{::I:ri ~=::i:; :.r::;:~~~~ nat

TEXAS

~

INSTRUMENTS
34 Forest Street. Attleboro, Massachusetts 02703

4·31

IC SOCKETS

DUAL·IN·LlNE
C7X SERIES

DUAL·IN·L1NE
C7X AND C86 SERIES

~~F=~~----~/9
1.35

0.53
...U
....
(0.021) DIA

(0.053)

3.61/4.57
,
(0.142)110.180)

...:.j1-{~~:5) DIA

C86 SERIES

,

4.25
(0.169)

.

DIPS

'"

0
0

0
0

g :Ii<=

J
6
8
14
16
18
20
22
24

t24

.Ii
Q

0

..
it

~

=

:Ii

"
~

0

'"

Q

E

is

..

on

.

0
0

a :Ii<=

~

i.

7.62
5.08 10.16 7.62 t24
10.300) 10.200) 10.400) 10.300)
10.16 7.62 10.16 7.62
28
10.400) 10.300) (0.400) 10.300}
17.78 15.24 10.16 7.62
32
10.700} 10.600} 10.400) (0.300)
20.32 17.78 10;16 7.62
34
10.800) 10.700) (0.400) 10.300)
22.86 20.32 10.16 7.62
40
(0.900) 10.800) (0.400) 10.300}
25.40 22.86 10.16 7.62
11.000) 10.900) 10.400) 10.300} 48
27.94 25.40 12.76 10.16
50
11.10Q) 11.000) 10.500) 10.400)
30.48 27.94 17.78 15.24
11.200) 11.100) (0.700) 10.600) 64

0

..
it

*

,

0.38 TVP

0

:i

"

C!

0
it
Q

E
E
is
is
~
30,48 27.94 12.76 10.16
11.200) 11.100) 10.500) 10.400}
35.56 33.02 17.78 15.24
11.400) 11.300) 10.700) (0.600)
40.64 38.10 17.78 15.24
11.600) 11.500) 10.700) 10.600}
45.72 '43.18 17.78 15.24
11.800) 11.7"00) 10.700) 10.600)
50.80 48.26 17.78 15.24
12.000) 11.900) 10.700) 10.600)
58.42 17.78 15.24
I~~~) 12.300) 10.700) 10.600)
63.50 60.96 25.40 7.62
12.500) (2.400) (1.000) (0.900)
78.74 25.40 22.86
1~~2~) 13.100) 11.000) 10.900}

.5
Q

30,48 27.94 10.16 7.62
11.200) 11.100} 10.400) 10.300)

t Nonstandard sizes
Not all sizes available in each series
Dimensions apply to all series

C

I»

&t

Dimensions in" parentheses are inches
Contact factory for detailed Information

4 ..32

PRODUCTION DATA d......nts ••nIIln inf.rmlti.n
.urrelt • •f p.bli..ti.n dlto. Producta ••nf.rm t.
lpacHic.ti... p.r th. tonal of T.... IlIIIrumonts
sta .... rd w.rranty. Pr.ducti.n ~rDCnsing do. nit
.......rIl' Inctudo tuI{ng of .11 per.met....

TEXAS

~

INsTRUMENTS
34 Forest Street. Attleboro, Massachusetts 02703

IC SOCKETS
BURN·IN/TEST DIP

1

PERFORMANCE SPECIFICATIONS

PART NUMBER SYSTEM

Mechanical

C

X

37

XX

-

Accommodates IC leads 0.011 in by 0.018 in
Recommended PCB thickness range: 0.062 in to 0.092 in
Recommended PCB hold size range: 0.032 in to 0.042 in
Durability: 10K cycles - CM Series, 5K cycles - CP/CQ

22

Number of positions'

Overall gold plate

Operating temperature: - 65°C to 170°C - CP/CM Series,
- 65°C to 150°C - CQ Series
Humidity: 10 mil max contact resistance
Temperature Soak: 10 rnO max contact resistance change

MATERIALS

A
±0.01
Length

Number of
Positions

BURN-IN/TEST DIP SOCKETS

I,

P - High density mounting
M - Shrink 0.070 centers

C037 SERIES

tFor additional plating options consult the factory

~

Series Features
Q- Auto unload able

TI Socket Series

Body - PPS (polyphenylen sulfide) UL 94 V-O
Contacts - Higher performance copper nickel alloy
Plating: t 4 "in of gold min over 100 "in of nickel min

2.54

A-0.l00 centers
8-0.070 centers

Copper nickel alloy
Soldertail

Environmental

IO.100)~

Pin to pin

PPS high temperature
body material

Electrical
Contact rating: 1 A per contact
Contact resistance: 20 mil max initial
Insulation resistance: 1000 M{J at 500 V dc
Dielectric withstanding voltage: 1000 V ac rms
Capacitance: 1 pF max per MIL-STD 202, Method 305

-.-'.c

L

LS

3.30}2
10.'
3011...
,?-"
2 54
~~1O:1001
SOLDER TAil

0

C

B

±0.02

±O.01
Width

±0.01

Contact

14
16
18
20

20,32
22,35
24,89
27,43

(0.8001
(0.8801 12,70
15,24
7,62
(0.9801 (0.5001 (0.6001 (0.300)
(1.080)

24
28
40
42

32,51
37,59
52,83
55,37

(1,280)
(1.480) 19,05 22,86
15,24
(2.080) (0.750) (0.900) (0.600)
(2.180)

~

C037 SERIES

CP37 SERIES

CP37 SERIES
Number of

Positions

1

CM37 SERIES

•. 50

TI,

(0.460)
(0.700)
(0.800)
(0.900)
(1.000)

7,62
(0.300)

12,70
(0.500)

24
28
40

30,48 (1.2001
35,56 (1.400)
50.80 (2.000)

15,24
(0.600)

20,32
(0.800)

A
±O.016
Length

B

C

±0.O2

±0.016
Width

28

27,18 (1.070)

10,67
(0.420)

17,20
(0.677)

40
42
54

37,85 (1.490)
39,62 (1.560)
50,29 (1.980)

16,51
(0.650)

23,11
(0.910)

10.4721

3.48

64

59,18 (2.3301

20,32
(0.800)

26,92
(1.060)

020 1

Number of

Positions

B

nll~"99

~~.l
O.53......!1.-

11,68
17,78
20,32
22.86
25,40

CM37 SERIES

--.l

(0.021,

C
max
Width

8
14
16
18
20

I ~O.5'

10.2561

B
±0.02

A
max
Length

1 78-J \..IO.i)701

(0.137)
0,50
10.0201

I

as
.....
as

o

Dimensions in parentheses are inches

Contact factory for detailed information

PRODUCTION DATA do•• monts .ontain information
current 8. of publicatiDn dat•• Products conform to
specifications par the terms of T8XI. Instruments

::~'!:~i~ai~:1~7i ~:\:~i:r lI~D::;:~~~~ not

TEXAS ~

INSfRUMENTS
34 Forest Street. Attleboro, Massachusetts 02703

4-33

IC SOCKETS
QUAD·IN·LlNE/SHRINK PACK
PERFORMANCE SPECIFICATIONS
Insertion force: 16 oz (454 g) per pin max
Withdrawal force: 1.5 oz (42 g) per pin min
Operating temperature: - 40 °C to 100 °C, tinllead
Accommodates IC leads 0.011 ± 0.0003 in by
0.018 ± 0.003 in
Contact rating: 1 A per contact

MATERIALS

Body - PBT polyester UL 94 v-o
C4S & CxW Contacts - Copper alloy
Contact finish - Reflow tin plating, 40 "in min

DUAL BEAM
EDGE GRIP
CONTACT

PART NUMBER SYSTEM FOR CxW SERIES

lli
C

X

W

XX -

11

QUAD-IN-L1NE (CxW SERIES)

l

Number of contacts (42, 52, 64)
Staggered leads

5 6 -

I"

A---~

64 contacts
42, 52 contacts

TI Socket Series

QUAD-IN-L1NE (CxW SERIES)
A
Max
Length
41,90
(1.651

Product
Number

C5W64-11

B

C

Row to Row

Max

Row to Row
22,90
(0.950)

19,05
(0.750)

C6W42-11

27,90
(1.10)

22,90
(0.900)

17,80
(0.700)

C6W52-11

34,30
(1.35)

22,90
(0.900)

17,80
(0.700)

Dimensions in parentheses are inches
Contact factory for detailed information

1,79
(0.050)

C4S SERIES

PART NUMBER SYSTEMt FOR C4S SERIES

1
II
c

4

1S

t~::ber

of contacts
28,40,42,52,54,64

Shrink Pack
(0.070 in pin-to-pin contact spacing)

s:

(')

B

Row to Row

C
Max
Width

28

25,02
(0.985)

10,16
(0.400)

13,00
(0.512)

40

35,69
(1.405)

15,24
(0.600)

17,98
(0.708)

64

57,07
(2.247)

19,05
(0.750)

21,62
(0.851)

Dimensions in parentheses are inches

SHRINK PACK DIP (C4S SERIES)

Reflow tin plating

CD

A

Max
Length

Positions

TI Socket Series

t Also available in screw machine contacts

::r

I»

C4S SERIES

j

C:;'

!.
C

....
I»
I»

4-34

PRODUCTION DATA documents contain information
current 8S of publication date. Products conform to
specifications par the terms of TexIs Instruments

:~~~~:~~i~ai~:1~1i ~!::i:~ti:r ~~o::;:~~:~~s not

,If

TEXAS
INSTRUMENTS
34 Forest Street. Attleboro, Massachusetts 02703

IC SOCKETS
BURN·IN/TEST
PERFORMANCE SPECIFICATIONS

QUAD FLAT PACK (CFPM SERIES)

Mechanical
Accommodates IC leads per specific IC device
Recommended PCB thickness range: 0.062 in to 0.092 in
Recommended PCB hole size range: 0.032 in to 0.042 in
Durability: 5000 cycles, 10 mil max contact resistance
change per MIL-STD 1344, Method 2016

Electrical
Contact rating: 1 A per contact
Contact resistance: 20 mil max initial
Insulation resistance: 1 Mil at 500 V dc per
MIL-STD 1344, Method 3003.1
Dielectric withstanding voltage: 700 V ac rms per
MIL-STD 1344, Method 3001.1
Capacitance: 1 pF max per MIL-STD 202, Method 305

Environmental

1'"L:~:'

PART NUMBER SYSTEM

Operating temperature: -65°C to 170°C
Humidity: 10 mil max contact resistance change when
tested per MIL-STD 202, Method 103B
Temperature soak: 10 mil max contact resistance change
when exposed to 105°C temperature for 48 hours

MATERIALS
Body - CFP Series - PES (polyether sulfone) glass filled
UL 94 V-O
Temperature: -65°C to 170°C
Contact - Beryllium copper
Plating: t Overall gold plate min 41'in over min 70 I'in nickel
plating

01X
Lvariation.
A - 1.0 mm ~
B - 0.8 mm ~
contact spacing

lXX

M - Quad pack

TI socket

Plating
37 - overall gold plate

Style PF - Flat pack

PIN GRID ARRAY (CZFW SERIES)

t For additional plating option consult the factory.
Dimensional drawings available from factory.

SMALL OUTLINE FLAT PACK (CFPH/K SERIES)

PART NUMBER SYSTEM

c

11

XX X

XXX

XX

01

Lplating
37 - overall gold plate

Number of positions

Configuration

PART NUMBER SYSTEM

c xx

L
x

LXXX Lplati::

.

.

....'"

W-llxllx2

o'"

Style ZF - Zero force

37 - overall gold plate

TI Series socket

Number of positions

AVAILABlE SIZES

Configuration

H - 14, 16, 18,20 Positions
K - 24, 28 Positions
Style FP - Flat pack
TI Series socket

CFPH Series 14, 16, 18, 20
CFPK Series 24, 28

Small Outline
Flat Pack

CFPM Series 64, 80

Quad Flat Pack

CZFW Series 11 x 11 x 2

Pin Grid Array

Contact factory for detailed information

PRODUCTION DATA do•• monts .ontsin inlarmalion
carnnt .1 of publication date. Praducts conform to
specifications per the terms of Taxas Instruments

::~=~~;I[::1~7i ~:\::i:r :.r::::::':~~1 not

TEXAS . "

INSTRUMENlS
34 Forest Street. Attleboro, Massachusetts 02703

4-35

For more Information contact your
local distributor or contact TI directly:
Texas Instruments Incorporated
CSD Marketing, MS 14·1
Attleboro, MA 02703

(617)

699·5242/~269

Field Sales Offices
UNITED STATES

INTERNATIONAL

California

Australia

Irvine 91714
17891 Cartwright Road
Phone: (714) 660·8111

Texas Instruments Australia, Ltd.
P.O. Box 63
Ellzabetl1, South Australia 5112
Phone: 61.·8·255·2066

San Diego 92123
4333 View Ridge Ave., Suite B
Phone (619) 278·9600/9603
Torrence 90502
9505 Hamilton St.
Bldg. A, Suite One
Phone: (213) 217·7000

Georgia
Norcross 30092
5515 Spaulding Drive
Phone: (404) 662·7861/7931

Massachusetts
Attleboro 02703
34 Forest Street, MS 10·6/MS 14·3
Phone: (617) 699·5206/127815213

North Carolina
Charlotte 28210
8 Woodlawn Gree~
Suite 100
Phone: (704) 527·0930

Texas.
Dallas 75265
7800 Banner Drive; MS 3936
Phone: (214) 995·7550/7547/7548

Texas Instruments provides customer
assistance in varied technical areas. Since
Ti does not possess full access to data

concerning all of the uses and applications
of customers' products, responsibility is
assumed by TI neither for customer
product design nor for any Infringement of

patents or rights of others, which may
result from TI aSSistance.

C
r»

...
I»,

4-36

England
Texas Instruments, Ltd.
Belfordia House
Prebend.Stsreet
Bedford MK41 7PA
Phone: (0234) 63211, Ext. 1

France
Texas Instruments, Ltd ..
Metallurgical Materials Division
8·10 Avenue Morane Saulnier
78140 Vellzy·Viliacoublay, Paris
Phone: 333. 946. 9712

Hong Kong
Texas Instruments Asia, Ltd.
Asia Pacific Division
8th Floor, World Shipping Centre
Harbor City 7, Canton ~oad
Kowloon, Hong Kong
Phone: 852·3-722·1223

Italy
Texas Instruments Italla SPA
Viale Europa, 40
1·20093 Cologno Monzese
Milano
Phone: 011·39·2·25.300.1

Japan
Texas Instruments Japan, Ltd.
305 Tanagasnira
Oyama·Cho
Suntoh·Gun, Shizuoka·Ken
Japan 410·13
Phone: (81) 550·81211

Mexico
Texas Instruments de Mexico, SA
Av. Reforma No. 450·10 Piso
Col. Juarez
Delegacion: Cuauhtemoc
Mexico City, D.F.
Mexico 06600
Phone: 52·5·514·3583

Singapore
Texas Instruments Asia
#02·08, 12 Lorong Bakar Batu
Kolam Ayer Industrial Estate
Singapore 1334
Republic of Singapore
Phone: 65·747·2255

Taiwan
Texas Instruments Supply Co.
Taiwan Branch
Bank Tower
Room 903., 205 Tun Hwa N. Road
Taipei, Taiwan
Phone: 866·2·713·9311

West Germany
Texas Instruments Deutschland GMBH
Metallurgical Materials Div.
Rosenkavallerplatz 15
0·8000 Muenchen 81
Phone: 011-49·89·915081

TI Sales Offices TI Distributors
ALABAMA: Huntsville (205) 837·7530.
ARIZONA: Phoenix (602) 995·1007;
Tucson (602) 624-3276.

TI AUTHORIZED DISTRIBUTORS
Arrow/Klerulff Electronics Group
Arrow,Canada (Canada)
Future Electronics (Canada)
GRS Electronics Co., Inc.
Hall-Mark Electronics
Marshall Industries
Newark Electronics
Schweber Electronics
Time Electronics
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Zeus Components
- OBSOLETE PRODUCT ONLYRochester Electronics, Inc.
Newburyport, Massachusetts
(617) 462-9332

CALIFORNIA: Irvine (714) 660-1200;
Sacramento (916) 929-0197;

~:~t~l~ra~II(~lgk?~:£~gb;
Torrance (213) 217·7000;
Woodland Hilla (81a) 704-7759.
COLORADO: Aurora (303) 368-8000.
CONNECTICUT: Wallingford (203) 269-0074.
FLORIDA: Altamonte Springs (305) 260-2116;
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~:;~J~~~ld:(~'rJ)~~7~4~~ (313) 553-1500;
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MISSOURI: St. Louis (314) 569·7600.
NEW JERSEY: Iselin (201) 750,1050.
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~~I~~~~~) ~~~ilJg~~rJs~!~~) (j~~i9;:~_~770;

Poughkeepsie (914) 473·2900.

NORTH CAROLINA: Charlo"e (704) 527-0930;
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OHIO: Beachwood (216) 464-6100;
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ARIZONA: Arrow/Kierulff (602) 437-0750;
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CALIFORNIA: Los Angeles/Orange County:
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Hall·Mark (818) 716-7300. (714) 669·4100,
13) 217·8400; Marshall (818) 407-0101, (818) 459-5500,
1141458-5395; Schweber (818) 999-4702;
14 663·0200, ~13l320.8090; Wyle ~213~ 322-9953,

~

~~:;a:~~g~oHall!~a~k6r9~~r~k~~:0ci;'4

921·9000;
Marshall (916) 635·9700; Schweber (916) 929·9732;
Wyle (916) 638-5282;
San Diego: Arrow/Kierulff (619) 565·4800;

~~~~~~r (~19J) ~~~_1~~~; ~;~h(JI, ~1~~~~116;OO;

OREGON: Beaverton (503) 643-6758.
PENNSYLVANIA: Blue Bell (215) 825·9500.
PUERTO RICO: Halo Rey (809) 753-8700.
TENNESSEE: Johnson City (615) 461·2192,
TEXAS: Austin ~512) 250-6769;

~:~~~ro~~315;2f::i~~~~~hardson

ALABAMA: Arrow/Kierultf (205) 837·6955;
Halt-Mark (205) 837-8700; Marshal! (205) 881-9235;
Schweber (205) 895·0480.

(214) 680-5082;

UTAH: Murray (801) 266-8972.
VIRGINIA: Fairfax (703) 849-1400,
WASHINGTON: Redmond (206) 881-30aO.
WISCONSIN: Brookfield (414) 782-2899.

~~~~~~ ~~r.~~ia~~t(l~~)(~1~.~fg1 ~ 970;
St. Laurent, Quebec (514) 336·1860,

TI Regional
Technology Centers
CALIFORNIA: Irvine (714) 660-8140;
Santa Cla,a (408) 748·2220;
Torrance (213) 217·7019.
COLORADO: AUrora (303) 368-8000.
GEORGIA: Norcross (404) 662·7945.
ILLINOIS Arlington Heights (313) 640·2909.
MASSACHUSETTS: WaHham (617) 895·9196.
TEXAS: Richardson (214) 680-5066.
CANADA: Nepean, Ontario (613) 726-1970,

San Francisco Bay Area: Arrow/Kierultf (408) 745-6600,
Hall-Mark (408) 432·0900; Marsha!! (408) 942-4600;
Schwaber (408) 432-7171; Wyle (408) 727-2500;
Zeus (408) 998-5121,
COLORADO: Arrow/Kierutff (303) 790-4444;
Hall-Mark (303) 790-1662; Marshall (303) 451·8383;
Schweber (303) 799-0258; Wyle (303) 457-9953.
CONNETICUT: Arrow/Kierulff (203) 265·7741;
Hall·Mark (203) 269-0100; Marshall (203) 265·3822;
Schweber (203) 748-7080.
FLORIDA: Ft. Lauderdale:

~~~~~:e[3uO~)(~~~:;:o~~~~~~~~(j~5l3~if_%~ i~280;

Orlando: Arrow/Kierulff (305) 725-1480, (305) 682·6923;
Hall·Mark (305) 855-4020; Marshall (305) 767-8595;
Schweber (305) 331.7555; Zeus (305) 365-3000;
Tampa: Hall-Mark (813) 530·4543;
Marshall (813) 576· 1399.

~;I~~;~~4t;)~~:~~ ~~:lh~iI9i:~:)2~23_5750;

Schweber (404) 449-9170,

ILLINOIS: Arrow/Kierulff (312) 250·0500;
Halt-Mark (312) 860-3800; Marshall (312) 490-0155;
Newark (312) 784·5100; Schweber (312) 364·3750.
INDIANA: Indianapolis: Arrow/Kierulff (317) 243-9353;
Hall-Mark (317) 872·8875; Marshall (317) 297-0483.
IOWA: Arrow/Kierulff (319) 395·7230;
Schweber (319) 373·1417.
KANSAS: Kansas City: Arrow/Kierulff (913) 541-9542;
Hall·Mark (913) 888·4747; Marshall (913) 492-3121;
Schweber (913) 492-2922,
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Hall·Mark (301) 988-9800; Marshall (301) 840·9450;
Schweber (301) 840-5900; Zeus (301) 997·1118.

•

TEXAS
INSTRUMENTS

MASSACHUSETTS Arrow/Kierulff (617) 935-5134;

~~~:!~~r (r~th ~615~5~~, ~:;~~~~*~ci~~~8.0810;

Time (617) 532-6200; Zeus (6t7) 863-8800.
MICHIGAN: Detroit: Arrow/Kierulff (313) 971-8220;
Marshall (313) 525-5850; Newark (313) 967-0600;
Schweber (313) 525·8100;
Grand Rapids: A(row/Kierulff (616) 243-0912,
MINNESOTA: Arrow/Kierulff (612) 830-1800;
Halt-Mark (612) 941·2600; Marshall (612) 559-2211;
Schweber (612) 941·5280.
MISSOURI: 51. Louis: Arrow/KierulH (314) 567·6888;
Hall-Mark (314) 291-5350; Marshal! (314) 291-4650;
Schweber (314) 739·0526.
NEW HAMPSHIRE: Arrow/Kierulff (603) 668·6968;
Schweber (603) 625-2250.
NEW JERSEY: Arrow/Kierulff (201) 538·0900,
(609) 596-8000; GRS ElectroniCS (609) 964-8560;
Han·Mark (201) 575-4415, (609) 235-1900;
Marshall (201) 882-0320, (609) 234-9100;
Schweber (201) 227-7880.
NEW MEXICO: Arrow/Kierulff (505) 243-4586.

~:;:iK?e~~~ ~~6r J~~a_~g~o; Hall-Mark (516) 737.0600;

Marshall (516) 273·2424; Schweber (516) 334-7555;
Zeus (914) 937·7400;
Rochester: Arrow/Kierulff (716) 427-0300;
Hall-Mark (716) 244·9290; Marshall (716) 235·7620;
Schweber (716) 424·2222;
Syracuse: Marshall (607) 798-16ft.
NORTH CAROLINA: Arrow/Kierulff (919) 876-3132,
(919) 725·8711; Hall·Mark (919) 872-0712;
Marshall (919) 878-9882; Schweber (919) 876-0000.
OHIO: Cleveland: Arrow/Kierulff (216) 248-3990;
Hall-Mark (216) 349-4632; Marshall (216) 248·1788;
Schweber (216) 464·2970;
Columbus: Arrow/Klerulff (614) 436-0928;
Hall-Mark (614) 888-3313;
Dayton: Arrow/Kierulff (513) 435-5563;
Marshall (513) 898-4480; Schweber (513) 439·1800.
OKLAHOMA: ArrowlKlerulff (918) 252·7537;
Schweber (918) 622-8003,

~:~~~~~O~)~~~~~ ~~!) (~;)s:g:6000.
PENNSYLVANIA: Arrow/Klerulff (412) 856·7000,

~2dh5~:;:;(:~~i ~~~~eg,t~~i~) ~~~J8~~~·7037;
TEXAS: Austin: Arrow/Kierulff (512~ 835-4180;
Hall-Mark (512) 258-8848; Marshall 512) 837·1991;
Schweber (512) 339-0088; Wy!e (51 ) 834-9957;
Dallas: Arrow/Kierulff (214~38Q.64t34;

~~~~~:r (~1,~) ~5631~~~°d; ~;~h(~J, %':11.~~iOO;
Zeus (214) 783-7010;
Houston: Arrow/Klerulff (713) 530·4700;
Han·Mark (713) 781-6100; Marshal! (713) 895-9200;
Schweber (713) 784-3600; Wyte (713) 879-9953.
UTAH: Arrow/Kierulff (801) 973-6913;
Hall-Mark (801) 912.1008; Marshall (801) 485-1551;
Wyle (801) 974-9953.
WASHINGTON: Arrow/Klerulfl (206) 575-4420;
Marshall (206) 747·9100; Wyle (206) 453-8300.
WISCONSIN: Arrow/Kierulff (414) 792·0150;
Hall-Mark (414) 797·7844; Marshall (414) 797-8400;
Schweber (414) 784-9020.
CANADA: Calgary: Future (403) 235-5325;
Edmonton: Future (403) 438·2858;
Montreal: Arrow Canada (514) 735·5511;
Future (514) 694-7710;
CHawa: Arrow Canada (613) 226·6903;
Future (613) 820·8313;
Quebec City: Arrow Canada (418) 687-4231;
Toronto: Arrow Canada (416) 672·7769;
Future (416) 638·4771;
Vancouver: Future (604) 294-1166;
Winnipeg: Future (204) 339-0554.

Customer
Response Center
TOLL FREE: (800) 232·3200
OUTStDE USA: (214) 995-6611
(6:00 a.m, - 5:00 p.m. CSl)

BU

TI Worldwide
Sales Offices
ALABAMA: Huntsville: 500 Wynn Drive, Suite 514,
Huntsville, AL 35805, (205) 837·7530.

~~rw!~~~g~~~~~~1'1~~~I(~'~'::4~:4~~W York Dr.,
g~~:g~:!:: ~~o 1~~~~~(4~~i'7~t~~ Office Park,
PUERTO RICO: Halo Rey: Mercantil Plaza Bldg.,
Suite 505, Hato Rey, PR 00919, (809) 753·8700.
TEXAS: Austin: P.O. Box 2909, Austin, TX 78769,
WI~~a~~~~kR~~:O~80n: 1001 E. Campbell Rd.,

~~i~~ 6:7~~~~g~~~~:7ngg, ~~fJr~::~:~y·,

GERMAN~JF~ut::~I:~C ~~:~~~~~~~~:~rrsasse "
1

Kurfuerstendamm
n

"

06196+8070; Hamburgerstrasse 11, 0·2000 Hamburg
76,040+220'1154, Klrchhorsterstrasse 2, 0·3000

~~;~v~~rf1id~~~ 2=~~~~alf1~~¥gg~; 11,
~~~~~~i~~:M9, °R=t~:~u,ra. ~5:&t~~~~~1;

ARIZONA: Phoenix: 8825 N. 23rd, Ave., Phoenix,

San Antonio: 1000 Central Parkway South,
San Antonia, TX 78232, (512) 496·1779.

261 +35044.

CALIFORNIA: Irvine: 17891 Cartwright Rd., Irvin.,

UTAH: Mumy: 5201 South Green SE, Suite 200,
Murray, UT 84107, (801) 266·8972.

Texas Instruments Asia Ltd., 8th Floor, World
Shipping Ctr., Harbour City, 7 Canton Rd., Kowloon,
Hong Kong, 3 + 722-1223.

AZ 85021,1602)995·1007.

CA 92714, (714) 660-8187; Sacramento: 1900 Point
West Way, Suite 171, Sacramento, CA 95815,

n
Torrance,

DbT~n~~I~\e;:2~~~t•. '
~Vo~~~.~~gg~~~xc~~~~ CA
(213) 217-7010;

Woodland Hills: 21220 Erwin St., Woodlan"d Hills,

CA 91367, 1618) 704-7759.
COLORADO: Aurora: 1400 S. Potomac Ave.,
Suite 101, Aurora. CO 80012, (303)368-8000.

~~~~~T~!~ ~n.J~~'r~:rct~:rk~~~~~~~~U~~ri8J

CT 06492, 1203) 269-0074.

FLORIDA: Ft. Lauderdale: 2765 N,W. 6200 St.,
Ft. Lauderdale, FL 33309, (305) 973-8502;
Maitland: 2601 Maitland Center Parkway,
Maitland, FL 32751, (305) 660-4600;

~:::g: ~1~:09~1~1n3rI7g.~2b~uite

VIRG'INIA: Fairfax: 2750 Prosperity, Fairfax, VA
22031, (703) 849-1400.
WASHINGTON: Redmond: 5010 148th NE, Bldg B,
Suite 107, Redmond, WA 98052, (206) 881·3080.

:J~~:O~I::o~~'~i,'~i ~~: ~~~)~8~.~~:b.
CANADA: Nepean: 301 Moodie Drive, Mallorn
Center, Nepean, Ontario, Canada, K2H9C4,

Wi~~~~~9J~i r~m~~~~~~:.sg~:~e St. E.,
1:.1:J ¥~~'~~n:;a~~~~ts~i~:u~!'n~~r~~~e~~ebec,
Canada H4S1R7, (514) 335·8392.

101,

GA 30092, 1404)662·7900

ARGENTINA: Texas Instruments Argentina
S.A.I.C.F,: Esmeralda 130, 15th Floor, 1035 Buenos
Aires, Argentina, 1 + 394·3008.

~r~"~g~~~: ~~~~tt:,~LH:A~~:(g~~) ~40~~~Rquln,

AUSTRALIA (II NEW ZEALAND): Texas Instruments
Australia Ltd.: 6-10 Talavera Rd., North R{de

GEORGIA: Norcross: 5515 Spalding Drive, Norcross,

I~D:8~:': (~~9)W:l~H~~ Inwood Or., Ft. Wayne,
Indianapolis: 2346 S. Lynhurst, ~ulte J·400,
Indianapolis, IN 46241, (311) 24&-8555.
IOWA: Cadar Rapid,: 373 Collins Rd. NE, Suite 200,
Cedar Rapids, IA 52402, (319) 395-9550.
MARYLAND: Baltimore: 1 Rutherford Pl.,
7133 Rutherford Rd., Baltimore, MO 21207,

1301) 944-8600.
MASSACHUSETTS: Waltham: 504 Totten Pond Rd.,
Waltham, MA 02154, (617) 895-9100.

~S~d;~l ~2~~ 5~u~~~,a~~~ :t~S~~~~ ~~~:

Melbourne, Victoria, Australia 3004, 3 + 267·4677;
~11 ~~~~~hWay, 'Elizabeth, South Australia 5112,
AUSTRIA: Texas Instruments Ges.m.b.H.:
Industrlestrabe BI16, A·2345 BrunnlGebirge,

2236·846210.

:~~J~Mde~~~:~ ~~:~~rr::~~o~R~:i8~u~ ~u~~,

HONG KONG I + PEOPLES REPUBLIC OF

CHINA~

IRELAND: Texas Instruments (Ireland) Limited:
~r:~~71~d., Stillorgan, County Dublin, Eire,
ITALY: Texas Instruments Semiconduttori ltaUa Spa:
Viale Delle Scienze, 1,02015 Clttaducale (Rletl),
Italy, 746 694.1; Via Salaria KM 24 (Palazzo Cosma),
Monterotondo Scalo (Rome), Italy, 6+9003241; Viale

~~rgf:54~~r~i~~~~~~~f3,ZO'~~~~~~flaIY,

11 774545; Via J. Barozzl 6, 40100 Bologna, Italy, 51

355861.
JAPAN: Texas Instruments Asia Ltd.: 4F Aoyama

~~~y~~d.pap:';1~b~I~~2sr:~; t~~~::;'a~~n~tgt,u,

Nissho Iwal Bldg., 30 Imabashi 3· Chome,
Higashl-ku, Osaka, Japan 541, 06-2Q4-1881; Nagoya
Branch, 7F oainl Toyota West Bldg., 10-27, Melekl
4-Chome, Nakamura·ku Nagoya, Japan
450, 52-583-8691.
KOREA: Texas Instruments Supply Co.: 3rd Floor,

~~mg~~\~~o~~~~a:~~.~bfangnam-kU,
MEXICO: Texas Instruments de Mexico S.A.: Mexico

g~?:: ~~f~~m5~~~0'a~ - 10th Floor, Mexico,

MIDDLE EAST: Texas Instruments: No. 13, 1st Floor

~:~~~aB~~~ra?~;~::l~~ ~~~: ~7~'+~~~:F'

NETHERLANDS: Texas Instruments Holland B.V.,

;U?d,g~~t~~:a~~u~~::m~~~rr. CB Amsterdam,

1130 Brussels, Belgium, 21720.80.00.

~~::::~~J.e~~~ol~~t~~,:~~ (~)o~O':'S:

PB106,

BRAZIL: Texas Instruments Electronicos do Brasil

~=~~~:~ ~~I~t:~~~I,I~~~l{~~sJg. Mile Rd.,

§:apa~~g, ~a;:ite~~5~~U. Andar Plnheiros, 05424

PHILIPPINES: Texas Instruments Asia Ltd.: 14th

MINNESOTA: Edan Pralrla: 11000 W. 78th St.,
Eden Prairie, MN 55344 (812) 828-9300.

DENMARK: Texas Instruments AIS, Mairelundvej
46E, oK·2730 Herlev, Denmark, 2 • 91 7400.

PORTUGAL: Texas Instruments E~uipamento

~i\~~R:.~::.~:,~IW3-s:80~ard Pkwy'., Kansas
St. Loull: 11816 ~orman Drive, SI. Louis,

FINLAND: Texas Instruments Finland OY:
Teoilisuuskatu 190 00511 Helsinki 51, Finland, (90)
701-3133.

NEW JER'SEY: 1••lln: 485E U.S. Route 1 South,
Parkway Towers, Iselin, NJ 08830 (201) 75().1050

FRANCE: Texas Instruments France: Headquarters
and Prod. Plant, BP OS, 06270 Villeneuve-Lou bet,
(93)20"()1..t)1: Paris Office, BP 67 8-10 Avenue
Morane-8aulnler, 78141 Vellzy-Villacoublay,
n Sales Office, L'Oree o'Ecully,

MO 63148, 1314)569·7600.

NEW MEXICO: Albuquerque: 2820-0 Broadbent Pkwy
NE, Albuquerque, NM 87107, (505) 345·2555.

~~~~il~~e~~:!~i~~~hi~~~rn:~~~ ~~~~~~,
m~i~~~~~~ (:~~~:15a~~ia~~:70n~:~~~~~~al,

2·Q4.8.1003.

SINGAPORE 1+ INDIA, INDONESIA, MALAYSIA,

THAILAND): Texas Instruments Asia Ltd.: 12 Lorang
Bakar Batu , Unit 01..()2, Kolam Ayer Industrial Estate,
Republic of Singapore, 747·2255.

r~~~: J:rd~~~s~~.~~~~~rSfe~'1~4:a:. ,c1.~~~e
SWEDEN: Texas Instruments International Trade

~ci:~~~~~ ~~:J~~~f~~:~J~:'x 39103,

5100
Le Peripole-2, Chemin du Plgeonn er de la ep ere,
31100 Toulouse, (61) 44·18-19; Marseille Sales Office,
~~:1~7~~38~s-146 Rue Paradis, 13006 Marseille,

10054

SWITZERLAND: Texas Instruments, Inc., Reldstrasse
6, CH·8953 oietikon (Zuerich) Switzerland,
1·7402220.
TAIWAN: Texas Instruments

SuPPI~

Co.: Room 903,

~rw~~~ ~::':'I~cd~/6~~:~2K~a~~1.::i. TaipeI,

UNITED KINGDOM: Texas Instruments Limited:
Manton Lane, Bedford, MK41 7PA, England,0234
OHIO: B.achwood: 23408 Commerce Park Rd.,
Beachwood, OH 44122, (216) 464-6100;
g~".i3~~(~f~)~:J.d3'lt: 124 Linden Ave., Dayton,
OREGON: B.averton: 6700 SW 105th St., Suite 110,
Beaverton, OR 97005, (503) 643-6758.

~

TEXAS
INSTRUMENTS

tI=~~~, J;.v.e~Rtt~,::s:gl~~~I~?~O~~.~~2~orth,
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TEXAS
INSTRUMENTS
Printed in U.S.A .

288 - 100

SDZD001C
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date                     : 2017:07:26 11:35:01-08:00
Modify Date                     : 2017:07:26 12:44:31-07:00
Metadata Date                   : 2017:07:26 12:44:31-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:f1af7c3e-ec35-8e41-9457-e46c347f3d82
Instance ID                     : uuid:5b46a5e4-16d4-7d46-ae48-5deafd96c2cf
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 482
EXIF Metadata provided by EXIF.tools

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