1988 TI SN74ACT8800 Family 32 Bit CMOS Processor Building Blocks Data Manual

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•
TEXAS
INSTRUMENTS

SN74ACTBBOO Family
32·Bit CIIIIOS Processor
Building Blocks

1988

Overview

SN74ACT8818

16-Bit Microsequencer

SN74ACT8832

32-Bit Registered AlU

SN74ACT8836

32- x 32-Bit Parallel Multiplier

SN74ACT8837

64-Bit Floating Point Processor

SN74ACT8841

Digital Crossbar Switch

SN74ACT8847

64-Bit Floating Point/Integer Processor

Support

Mechanical Data

SN74ACT8800 Family
32·Bit CMOS Processor
Building Blocks
Data Manual

TEXAS

INSTRUMENTS

IMPORTANT NOTICE
Texas Instruments (Til reserves the right to make changes to or
to discontinue any semiconductor product or service identified
in this publication without notice. TI advises its customers to
obtain the latest version of the relevant information to verify,
before placing orders, that the information being relied upon is
current.
TI warrants performance of its semiconductor products to current
specifications in accordance with Tl's standard warranty. Testing
and other quality control techniques are utilized to the extent TI
deems necessary to support this warranty. Unless mandated by
government requirements, specific testing of all parameters of
each device is not necessarily performed.
TI assumes no liability for TI applications assistance, customer
product design, software performance, or infringement of patents
or services described herein. Nor does TI warrant or represent that
any license. either express or implied, is granted under any patent
right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or
process in which such semiconductor products or services might
be or are used.

Copyright © 1988, Texas Instruments Incorporated
First edition: March 1988
First revision: June 1988

INTRODUCTION
In this manual, Texas Instruments presents technical information on the TI
SN74ACT8800 family of 32-bit processor "building block" circuits. The
SN74ACT8800 family is composed of single-chip VLSI processor functions, all of which
are designed for high-complexity processing applications.
This manual includes specifications and operational information on the following highperformance advanced-CMOS devices:
•
•
•
•
•
•

SN74ACT8818
SN74ACT8832
SN74ACT8836
SN74ACT8837
SN74ACT8841
SN74ACT8847

16-bit microsequencer
32-bit registered ALU
32- x 32-bit parallel multiplier
64-bit floating point processor
Digital crossbar switch
64-bit floating point/integer processor

These high-speed devices operate at or above 20 MHz, while providing the low power
consumption of Tl's advanced one-micron EPIC'· CMOS technology. The EPIC'· CMOS
process combines twin-well structures for increased density with one-micron gate
lengths for increased speed.
The SN74ACT8800 Family Data Manual contains design and specification data for
all five devices previously listed and includes additional programming and op~rational
information for the '8818, '8832, and '8837/'8847.
Introductory sections of the manual include an overview of the '8800 family and a
summary of the software tools and design support TI offers for the chip-set. The general
information section includes an explanation of the function tables, parameter
measurement information, and typical characteristics related to the products listed
in this volume.
Package dimensions are given in the Mechanical Data section of the book in metric
measurement (and parenthetically in inches).
Complete technical data for any Texas Instruments semicondutor product is available
from your nearest TI field sales office, local authorized TI distributor, or by calling Texas
Instruments at 1-800-232-3200.

EPIC

is a trademark of Texas Instruments Incorporated.

v

vi

Award Winners/1987
Electronic Products'

12th Annual
Product of the Year
Awards

E

very year, the editors of Electronic Products
select what we judge to be the best electronics products announced during the preceding
12 months. Our goal: to honor those products that
have contributed most to help our engineer-readers
do their jobs better.
We weigh several criteria as we sift through the
thousands of products brought to our attention.
Alone or in combination, each product must represent a significant advance in technology or its application, a decided innovation in deSign, or a substantial gain in price-performance ratio.

• 74ACT8836 Multiplier-Accumulator
• 74ACT8837 Floating Point Unit
• 74AS8840 .Crossbar Switch

vii

viii

Overview

1-1

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1-2

Overview

1-3

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1-4

Introduction
Texas Instruments SN74ACT8800 family of 32-bit processor building blocks has been
developed to allow the easy, custom design of functionally sophisticated, highperformance processor systems. The '8800 family is composed of single-chip, VLSI
devices, each of which represents an element of a CPU.
Geared for computationally intensive applications,SN74ACT8800 devices include highperformance ALUs, multipliers, microsequencers, and floating point processors.
The '8800 chip set provides the performance, functionality, and flexibility to fill the
most demanding processing needs and is structured to reduce system design cost
and effort. Most of these high-speed processor functions operate at 20 MHz and above,
and, at the same time, provide the power savings of TI's advanced, 1 /lm EPIC'· CMOS
technology.
The family's building block approach allows the easy, "pick-and-choose" creation of
customized processor systems, while the devices' high level of integration provides
cost-effectiveness.
Designed especially for high-complexity processing, the devices in the '8800 family
offer a range of functional options. Device features include three-port architecture,
double-precision accuracy, optional pipelined operation, and built-in fault tolerance.
Array, digital signal, image, and graphics processing can be optimized with '8800
devices. Other applications are found in supermini and fault-tolerant computers, and
I/O and network controllers.
In addition to the high-performance, CMOS processor functions featured in this data
manual, the family includes several high-speed, low-power bipolar support chips. To
reduce power dissipation and ensure reliabilty, these bipolar devices use TI's proprietary
Schottky Transistor Logic (STL) internal circuitry.

EPIC is a trademark of Texas Instruments Incorporated.

1-5

3:Q)

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At present, TI's .'8800 32-bit processor building block family comprises the following
functions:
•
•
•
•
•
•
•

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~

SN74ACT8818 16-bit microsequencer
SN74ACT8832 32-bit registeredALU
SN74ACT8836 32- X 32-bit parallel multiplier
SN74ACT8837 64-bit floating point processor
SN74ACT8841 digital crossbar switch
SN74ACT8847 64-bit floating point and integer processor
Bipolar Support Chips
• SN74AS8833 64-bit funnel shifter
• SN74AS8834 64 x 40 register file
• SN74AS8838 32-bit barrel shifter
• SN74AS8839 32-bit shuffle/exchange network
• SN74AS8840 16 x 4 crossbar switch

20 MIPS and Low CMOS Power Consumption
With instruction cycle times of 50 ns or less and the low power consumption of EPICTM
CMOS, the '8800 chip set offers an unrivaled speed/power combination. Unlike
traditional microprocessors, which require multiple cycles to perform an operation,
the 'ACT8800 processors typically can complete instructions in a single cycle.
The 'ACT8832 registered ALU and 'ACT8818 microsequencer together create a
powerful 20-MHz CPU. Because instructions can be performed in a single cycle, the
8832/8818 combination is capable of executing over 20 million instructions per second
(MIPS).
For math-intensive applications, the 'ACT8836 fixed-point multiplier/accumulator
(MAC),' ACT8837 64-bit floating point processor, and' ACT884 7 64-bit floating point
and integer processor offer unprecedented computational power.
The exceptional performance of the' ACT8800 family is made possible by Tl's EPICY.
CMOS technology. The EPICY. CMOS process combines twin-well structures for
increased density with one-micron gate lengths for increased speed.

Customized Solution
The '8800 family is designed with a variety of architectural and functional options
to provide maximum design flexibility. These device features allow the creation of
"customized" solutions with the '8800 chipset.
A building block approach to processing allows designers to match specialized hardware
to their specific design needs. The 8818/8832 combination forms the basis of the
system, a high-speed CPU. For applications requiring high-speed integer multiplication,
the' ACT8836 can be added. To provide the high precision and large dynamic range
of floating point numbers, the 'ACT8837 or 'ACT8847 can be employed.

1-6

To ensure speed and flexibility, each component of the '8800 family has three data
ports. Each data port accommodates 32 bits of data, plus four parity bits. This
architecture eliminates many of the I/O bottlenecks associated with traditional singleI/O microprocessors.
The three-port architecture and functional partitioning of the '8800 chip-set opens
the door to a variety of parallel processing applications. Placing the math and shifting
functions in parallel with the ALU permits concurrent processing of data. Additional
processors can be added when performance needs dictate.
The 'ACT8800 building block processors are microprogrammable, so that their
instruction sets can be tailored to a specific application. This high degree of
programmability offers greater speed and flexibility than a typical microprocessor and
ensures the most efficient use of hardware.
A separate control bus eliminates the need for multiplexing instructions and data, further
reducing processing bottlenecks. The microcode bus width is determined by the
designer and the application.
Another source of design flexibility is provided by the pipelined/flowthrough operation
option. Pipelining can dramatically reduce the time required to perform iterative, or
sequential, calculations. On the other hand, random or nonsequential algorithms requite
fast flowthrough operations. The '8800 chip set allows the designer to select the mode
(fully pipelined, partially pipelined, or nonpipelined) most suited to each design.

Scientific Accuracy
The '8800 family is designed to support applications which require double-precision
accuracy. Many scientific applications, such as those in the areas of high-end graphics,
digital signal processing, and array processing, require such accuracy to maintain data
integrity. In general-purpose computing applications, floating point processors must
often support double-precision data formats to maintain compatibility with existing
software.
To ensure data integrity, '8800 devices (excluding the barrel shifter and
microsequencer) support parity checking and generation, as well as master/slave error
detection. Byte parity checking is performed on the input ports, and a parity generator
and a master/slave comparator are provided at the output. Fault tolerance is built into
the processors, ensuring correct device operation without extra logic or costly software.

1-7

3:
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The SN74ACT8800 Building Block Processor System
Some of the high-performance '8800 devices are described in the following paragraphs.

SN74ACT8818 16-Bit Microsequencer

s>

In a high-performance microcoded system,· a fast microcode controller is required to
control the flow of instructions. The SN74ACT8818 is a high-spe~d, versatile 16-bit
< microsequencer capable of addressing 64K words of microcode memory. The
(j)"
~ 'ACT8818 can address the next instruction fast enough to support a 50-ns system
cycle time.
~

The' ACT8818 65-word-deep by 16-bit-wide stack is useful for storing subroutine
return addresses, top of loop addresses, and loop counts. Addresses can be sourced
from eight different sources: the three I/O ports, the two register counters, the
microprogram counter, the stack, and the 16-way branch.

SN74ACT8832 Registered ALU
The SN74ACT8832 is a 32-bit registered ALU that operates at approximately 20 Mhz.
Because instructions can be performed in a single cycle, the' ACT8832 is capable of
executing 20 million microinstructions per second. An on-board 64-word register file
is 36-bits-wide to permit the storage of parity bits. The 3-operand register file increases
performance by enabling the creation of an instruction and the storage of the previous
result in a single cycle. To facilitate data transfer, operands stored in the register file
can be accessed externally, while the ALU is executing. To support the parallel
processing of data, the' ACT8832 can be configured to operate as four 8-bit ALUs,
two 16-bit ALUs, or a single 32-bit ALU. The' ACT8832 incorporates 32-bit shifters
for double-precision shift operations.

SN74ACT8836 32- x 32-Bit Integer MAC
The SN74ACT8836 is a 32-bit integer multiplier/accumulator (MAC) that accepts two
32-bit inputs and computes a 64-bit product. The device can also operate as a 64-bit
by 64-bit multiplier. An onboard adder is provided to add or subtract the product or
the complement of the product from the accumulator.
When pipelined internally, the 1 /Lm CMOS parallel MAC performs a full 32- x 32-bit
multiply/accumulate in a single 36-ns clock cycle. In flowthrough mode (without any
pipelining), the' ACT8836 takes 60 ns to multiply two 32-bit numbers. The' ACT8836
performs a 64- x 64-bit multiply/accumulate, outputting a 64-bit reSUlt, in 225 ns.
The' ACT8836 can handle a wide variety of data types, including two's complement,
signed, and mixed. Division is supported via the Newton-Raphson algorithm.

SN74ACT8837 64-Bit Floating Point Unit
The SN74ACT8837 is a high-speed floating point processor. This single-chip device
performs 32- or 64-bit floating point operations.

1-8

More than just a coprocessor, the' ACT883 7 integrates on one chip a double-precision
floating point ALU and multiplier. Integrating these functions on a single chip reduces
data routing problems and processing overhead. In addition, three data ports and a
64-bit internal bus architecture allow for single-cycle operations.
The' ACT8837 can be pipelined for iterative calculations or can operate with input
registers disabled for low latency.

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SN74ACT8841 Digital Crossbar Switch

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The SN74ACT8841 is a single-chip digital crossbar switch. The high-performance
device, cost-effectively eliminates bottlenecks to speed data through complex bus
.
architecture.
The' ACT8841 is ideal for multiprocessor applications, where memory bottlenecks
tend to occur. The device has 64 bidirectional If 0 ports that can be configured as 16
4-bit ports, 8 8-bit ports, or 4 l6-bit ports. Each bidirectional port can be connected
in any conceivable combination. Any single input port can be broadcast to any
combination of output ports. The total time for data transfer is 20 ns.
The control sources for ten separate switching configurations are on-chip, including
eight banks of programmable control flip-flops and two hard-wired control circuits.
The EPIC'· CMOS SN74ACT8841 and its predecessor, SN74AS8840, are based on
the same architecture, differing in power consumption, number of control registers,
and pin-out. Microcode written for the' AS8840 can be run on the' ACT8841 .

SN74ACT8847 64-Bit Floating Point Unit
The SN74ACT8847 is a high-speed 64-bit floating point processor. The device is fully
. compatible with IEEE standard 754-1985 for addition, subtraction, multiplication,
division, square root, and comparison. Division and square root operations are
implemented via hardwired control.
The SN74ACT8847 FPU also performs integer arithmetic, logical operations, and logical
shifts. Registers are provided at the inputs, outputs, and inside the ALU and multiplier
to support multilevel pipelining. These registers can be bypassed for nonpipelined
operations.
When fully pipelined, the' ACT884 7 can perform a double-precision floating point or
32-bit integer operation in under 40 ns. When in flowthrough mode, the' ACT884 7
. takes less than 100 ns to perform an operation.

Bipolar Support Chips
The SN74AS8833 64-bit-to-32-bit funnel shifter can increase overall speed in systems
where multi-bit shift operations and field masking are frequently used. The device can
perform logical, cir~ular, and arithmetic shifts on 32-bit and 64-bit words, IEEE or IBM
normalization, and field pack or extract operations. The 'AS8833 provides
shift/maSk/merge capability for graphics and data compression applications.

1-9

o

The SN74AS8834 is a high-speed, three-operand, 64-word by 40-bit register file.
Designed to expand the' ACT8832 register file, the' AS8834 is an ideal temporary
storage device for high-speed applications. Four address ports, two write and two
read, operate independently to support MSH/LSH swap operations.

o

The SN74AS8838 high-speed, 32-bit barrel shifter can shift upto 32 bits in a single
instruction cycle of under 25 ns. Five basic shifts can be programmed: circular left,
;: circular right, logical left, logical right, and arithmetic right. The' AS8838 offloads the
CD" responsibility for shifting operations from the ALU, which increases shifter functionality
~ and system throughput.
~

The SN74AS8839 is a 32-bit shuffle/exchange network. The high-speed device can
perform data permutations on one 32-bit, two 16-bit, four 8-bit, or eight 4-bit data
words in a single instruction cycle of under 25 ns. The shuffle/exchange network is
designed primarily for use in digital signal processing applications.

1-10

SN74ACT8818

16-Bit Microsequencer

2-1

2-2

SN74ACT8818
16·8it Micfosequencef
•

Addresses Up to 64K Locations of Microprogram Memory

•

CLK-to-Y

•

Low-Power EPIC" CMOS

•

Addresses Selected from Eight Different Sources

•

Performs Multiway Branching, Conditional Subroutine Calls, and Nested
Loops

•

Large 64-Word by 16-bit Stack

•

Cascadable

=

30 ns (tpdl

Because they're microprogrammable, the ACT8800 building block processors provide
greater speed and flexibility than does a typical microprocessor. In such a highperformance microcoded system, a fast microsequencer is required to control the flow
of microinstructions.
The SN74ACT8818 is a high-speed, versatile 16-bit microsequencer capable of
addressing 64K words of microcode memory. The 'ACT8818 can address the next
instruction fast enough to support a 50-ns system cycle time.
The 'ACT8818 65-word-deep by 16-bit-wide stack is useful for storing subroutine
return addresses, top-of-Ioop addresses, and loop counts. For added flexibility,
addresses can be selected from eight different sources: the three I/O ports, the two
register/counters. the microprogram counter, the stack, and the 16-way branch input.

EPIC is a trademark of Texas Instruments Incorporated.

2-3

2-4

Contents
Page
Introduction ........................................ .

2-11

Understanding the 'ACT8818 Microsequencer .............
Microprogramming the 'ACT8818 ......................
Design Support ....................................
Design Expertise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
'ACT8818 Pin Grid Allocation .........................
'ACT8818 Specification Tables ........................

2-11
2-12
2-12
2-13
2-14
2-21

.
.
.
.
.
.

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2-8

List of Tables
Table
1
2
3
4
5

6
7
8
9
10
11
12
13
14

Page

Title
' ACT8818 Pin Grid Allocation ., ..................
' ACT8818 Pin Functional Description ...............
Response to Control Inputs ......................
Y Output Controls (MUX2-MUXO) .................
Stack Controls (S2-S0) .........................
Register Controls (RC2-RCO) .....................
Continue/Repeat Encodings . . . . . . . . . . . . . . . . . . . . . .
Branch Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conditional Branch Encodings ....................
Decrement and Branch on Nonzero Encodings .. . . . . . .
Call Encodings without Register Decrements .........
Call Encodings with Register Decrements ............
Return Encodings without Register Decrements .......
Return Encodings with Register Decrements ..........

.
.
.
.
.
.
.
.
.
.
.
.
.
.

2-15
2-18
2-26
2-32
2-33
2-33
2-34
2-35
2-37
2-40
2-41
2-42
2-42
2-43

2-9

00
~

00
00

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2-10

Introduction
The SN74ACT8818 microsequencer is a low-power, high-performance microsequencer
implemented in TI's EPIC'· Advanced CMOS technology. The l6-bit device addresses
up to 64K locations of microprogram memory and is compatible with the SN74AS890
microsequencer.
The 'ACT8818 performs a range of sequencing operations in support of TI's family 00
of building block devices and special-purpose processors such as the SN74ACT8847 ....
Floating Point Unit (FPU).
~

...

Understanding the .ACT8818 Microsequencer

()

«

The 'ACT881 8 microsequencer is designed to control execution of microcode in a CIt
microprogrammed system. Basic architecture of such a system usually incorporates Z
at least the microsequencer, one or more processing elements such as the' ACT884 7
FPU or the SN74ACT8832 Registered ALU, microprogram memory, microinstruction
register, and status logic to monitor system states and provide status inputs to the
microsequencer.

"
en

The' ACT8818 combines flexibility and high speed in a microsequencer that performs
multiway branching, conditional subroutine calls, nested loops, and a variety of other
microprogrammable operations. The' ACT8818 can also be cascaded for providing
additional register/counters or addressing capability for more complex microcoded
control functions.
In this microsequencer, several sources are available for microprogram address
selection. The primary source is the 16-bit microprogram counter (MPC), although
branch addresses may be input on the two l6-bit address buses, ORA and ORB. An
address input on the ORA bus can be pushed on the stack for later selection.
Register/counters RCA and RCB can store either branch addresses or loop counts as
needed, either for branch operations or for looping on the stack.
The selection of address source can be based on external status from the device being
controlled, so that three-way or multiway branching is supported. Once selected, the
address which is output on the Y bus passes to the microprogram memory, and the
microinstruction from the selected location is clocked into the pipeline register at the
beginning of the next cycle.
It is also possible to interrupt the ' ACT881 8 by placing the Y output bus in a highimpedance state and forcing an interrupt vector on the Y bus. External logic is required
to place the bus in high impedance and load the interrupt vector. The first

EPIC is a trademark of Texas Instruments Incorporated.
2-11

microinstruction of the interrupt handler subroutine can push the address from the
Interrupt Return register on the stack so that proper linkage is preserved for the return
from subroutine.

Microprogramming the ' ACT8818
Microinstructions for the' ACT8818 select the specific operations performed by the
Y output multiplexer, the register/counters RCA and RCB, the stack, and the
bidirectional ORA and ORB buses. Each set of inputs is represented as a separate field
in the microinstructions, which control not only the microsequencer but also the ALU
(J) or other devices in the system.

Z
....,

The 3-port architecture of the 'ACT8818 facilitates both branch addressing and
register/counter operations. Both register/counters can be used to hold either loop
~ counts or branch addresses loaded from the ORA and DRB buses. Register/counter
(')
-I operations are selected by control inputs RC2-RCO.
00
~ Similarly, the 65-word by l6-bit stack can save addresses from the ORA bus, the
00 microprogram counter (MPCl. or the Interrupt Return register, depending on the settings
of stack controls S2-S0 and related control inputs. Flexible instructions such as Branch
ORA else Branch to Stack else Continue can be coded to take advantage of the
conditional branching capability of the' ACT88l8.
~

Multiway branching (16- or 32-way) uses the B3-BO inputs to set up a 16-way branch
address on ORA or ORB by concatenating B3-BO with the upper 12 bits of the ORA
or ORB bus. The resulting branch addresses ORA' (ORA l5-0RA4::B3-BO) and ORB'
(ORB15-0RB4::B3-BO) are selected by the Y output multiplexer controls MUX2-MUXO.
A Branch ORB' else Branch DRA' instruction can select up to 32 branch addresses,
as determined by the settings of 83-80.

Design Support
Texas Instruments Regional Technology Centers, staffed with systems-oriented
engineers, offer a training course to assist users of Tl's LSI products and their
application to digital processor systems. Specific attention is given to the understanding
and generation of design techniques which implement efficient algorithms designed
to match high-performance hardware capabilities with desired performance levels.

2-12

Information on LSI devices and product support can be obtained from the following
Regional Technology Centers:
Atlanta
Texas Instruments Incorporated
3300 N.E. Expressway, Building 8
Atlanta, GA 30341
404/662-7945

Chicago
Texas Instruments Incorporated
515 Algonquin
Arlington Heights, IL 60005
312/640-2909

Boston
Texas Instruments Incorporated
950 Winter Street, Suite 2800
Waltham, MA 021 54
617/895-9100

Dallas
Texas Instruments Incorporated
10001 E. Campbell Road
Richardson, TX 75081
214/680-5066

Northern California
Texas Instruments Incorporated
5353 Betsy Ross Drive
Santa Clara, CA 95054
408/748-2220

Southern California
Texas Instruments Incorporated
17891 Cartwright Drive
Irvine, CA 92714
714/660-8140

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Design Expertise
Texas Instruments can provide in-depth technical design assistance through
consultations with contract design services. Contact the local Field Sales Engineer
for current information or contact VLSI Systems Engineering at 214/997-3970.

2-13

'ACT8818 Pin Grid Allocation
(TOP VIEW)
2

A

B

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D

en

:2

E

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F

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(X)
(X)

5

6

7

8

9

10 11

.
• • • • •
• • • • • • • • •
• • • • • • • • •

• (!) •

• •

• • •

• • •

• • •

• •

• • •

K

• (!) •

L

4

.~

J

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(X)

3

• •

• • •
• • •
• • •
• • •
• •
• • • •

• • • • • • (!)
• • • • • • • • •

•

Figure 1, 'ACT8818 . .... GC Package

2-14

Table 1. 'ACTSS1S Pin Grid Allocation

PIN
NO.
A2
A3
A4
A5
A6
A7
A8
A9
Al0
Bl
B2
83
B4
B5
B6
87
B8
89
810
Bll
C1

NAME
RC2
Y1
Y3
Y5
Y6
Y8
Y11
Y13
NC
ORB15
RCl
YO
Y2
Y4
YOE
Y9
Y12
Y14
Y15
ZEROIN
DRB14

PIN
NO.
C2
C3
C5
C6
C7
C9
Cl0
Cll
Dl
D2
09
010
Dll
El
E2
E3
E9
E10
Ell
Fl
F2

NAME
RCO
GND
GND
Y7
Yl0
GND
VCC
RE
ORB12
DRB13
GNO
COUT
INC
ORB9
DR810
DRBll
INT
83
B2
DRB7
ORB8

PIN
NO.
F3
F9
FlO
Fl1
Gl
G2
G3
G9
Gl0
Gl1
Hl
H2
Hl0
Hll
Jl
J2
J3
J5
J6
J8
J9

NAME
RBOE
BO
Bl
MUX2
DRB6
DRB5
GNO
CLK
MUXO
MUXl
DRB4
DRB3

CC
ZEROUT
DRB2
DRBl
VCC
GNO
RAO'E
DRAl
GNO

PIN
NO.
Jl0
Jl1
Kl
K2
K3
K4
K5
K6
K7
K8
K9
K.l0
Kll
L2
L3
L4
L5
L6
L7
L8
L9
L10

NAME
Sl
STKWRN/RER
DRBO
SELDR
DRA14
DRA12
DRA10
ORA7
DRA5
DRA3
ORAO
SO
S2
ORA15
DRA13
DRAll
DRA9
ORA8
DRA6
ORA4
ORA2
OSEL

2-15

(TOP VIEW)
~

o

O~N(')'

(")

-t

00
00
...a

00

50
51
52
CC
5TKWRN/RER
ZEROUT
CLK
MUXO
MUX1
MUX2
BO
B1
B2
B3
INT
INC
COUT
RE
GND
VCC
ZERO IN

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 4748 49 50 51 52 53
OLn'
16-BIT MICROSEQUENCER
'ACTSS1S

CLK
SO
S2

MASTER CLOCK

••

OSEL

RC2

••
r--..

BO

B3
MUXO
MUX2

DRAO

DRA15

••
••

••
•

DRBO

DRB15

STACK CONTROL

••
•

~

2

EN

I

REGISTER/COUNTERS
A AND B CONTROLS

STKWRN/RER
ZEROUT

ZERO DETECT

ORA/ORB INPUT
MUX SELECT
ORA OUTPUT
MUX SELECT

SELDR

RCO

iI

STACK
WARNING FLAG

,

CONDITION CODE

Y-BUS OUTPUT
ORA OUTPUT
ORB OUTPUT
INT RT REG

....,
A

YOE
RAOE
RBOE
RE

INCREMENTER
CARRY-OUT

COUT

INCREMENTER
CONTROL

INC

INT RT
MUX CONTROL

iI

....,
....,

.;1

00
~

00
00

....

C,)

«
~
,....

Z

INT

en

BRANCH ADDRESS

~

2

.,
0

••

•
15
0

••
•
15

I

Y-OUTPUT
MUX CONTROLS

r

<

DATA

)

~

~.

I

CURRENT
ADDRESS

.

••
•

YO

Y15

Figure 3. 'ACT8818 ... Logic Symbol

2-17

Table 2. 'ACT8818 Pin Functional Description
PIN

GC

FN

NAME

NO.

NO.

BO

F9

22

B1

F10

23

B2

E11

24

B3

E10

25

ClK

G9

18

I/O

I

"'l>"

Incrementer carry-out. Goes high when an attempt is
COUT

D10

28

0

~

15

CC

H10

-f

DRAO

K9

9

DRA1

J8

8

DRA2
DRA3

19
K8

6

DRA4

l8

5

DRA5

K7

4
3

~

00

made to increment microprogram counter beyond
addressable micromemory.

(')

00
00

Input bits for branch addressing (see Table 3)

System clock

C/)

Z

DESCRIPTION

I

Condition code

7

DRA6

l7

DRA7

K6

2

DRA8

l6

84

stack or register/counter A (RAOE = 0) or inputs

DRA9

l5

83

external data (RAOE = 1 ).

DRA10

K5

82

DRA11

l4

80

DRA12

K4

79

D.RA13

L3

78

DRA14

K3

77

DRA15

l2

76

DRBO

K1

73

DRB1

J2

72

DRB2

J1

71

DRB3

H2

70

DRB4

H1

69

DRB5

G2

67

DRB6

G1

66

DRB7

F1

65

DRB8

F2

63

DRB10

E2

61

2-18

I/O

Bidirectional ORA data port. Outputs data from

Bidirectional DRB data port. Outputs data from
I/O

register/counter B
(RBOE = 0) or inputs external data

Table 2. 'ACT8818 Pin Functional Description (Continued)
PIN

GC

FN

NAME

NO.

NO.

DRBll

E3

60

DRB12

Dl

59

DRB13

D2

58

DRB14

Cl

57

DRB15

Bl

56

DESCRIPTION

I/O

Bidirectional DRB data port. Outputs data from
I/O

register/counter B (RBOE = 0) or inputs external data
(RBOE=l).

GND

C3

10

00

GND

C5

30

00
00

GND

C9

33

GND

D9

46

GND

G3

52

GND

J5

68

..-

I-

Ground pins. All pins must be used.

()



00
00
~

00

Y9

B7

40

Y10

39

Y11

C7
A8

Y12

B8

37

Y13

A9

36

Y14

B9

I/O

I/O

DESCRIPTION

Bidirectional Y data port

38

Y15

B10

35
34

YOE

B6

42

I

ZEROIN

B11

32

I

Forces internal zero detect high

ZEROUT

H11

17

0

Outputs register/counter zero detect signal

2-20

Y output enable, active low

'ACT8818 Specification Tables
absolute maximum ratings over operating free air temperature range (unless
otherwise noted) t
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 6 V
Input clamp current, 11K (VIVCC) ................ ±20 mA
Output clamp current, 10K (VOVCC ............. ±50 mA
Continuous output current, 10 (VO= 0 to Vcc) . . . . . . . . . . . .. ± 50 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . .. ± 100 mA
ex)
Operating free-air temperature range. . . . . . . . . . . . . . . . . .. OoC to 70°C orStorage temperature range . . . . . . . . . . . . . . . . . . . . . . .. 65°C to 1 50 °C ~

....

tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond
those indicated under "recommended operating.conditions"is not implied. Exposure to absolute maximum
rated conditions for extended periods may affect device reliability.

(,)

recommended operating conditions

en

PARAMETER
Vee

Supply voltage

VIH

High-level input voltage

Vll

low-level input voltage

IOH

High-level output current

IOl

Low-level output current

VI

Input voltage

Vo
dt/dv

Output voltage
Input transition rise or fall rate

TA

Operating free-air temperature

.

MIN

NOM

MAX

4.5
2

5

5.5

0

0
0
0
0

UNIT
V
V

Vee

0.8
-8
8
Vee
Vee

..

V
mA
mA
V
V

15

nslV

70

°e

2-21

«
~
,....

z

electrical characteristics over recommended operating free-air temperature
range (unless otherwise noted)
PARAMETER

TEST CONDITIONS

VCC
4.5 V

•

IOH = -20 p.A
VOH
IOH = -8 rnA

en
Z

IOL = 20 p.A

"J>

VOL

~

IOL = 8 rnA

C')

-t

CO
CO
~

CO

TA - 25°C
MIN TYP MAX

MIN

TYP

MAX

UNIT

4.48

5.5 V

5.46

4.5 V

4.15

5.5 V

4.97

V

3.76
4.76

4.5 V

0.014

5.5 V

0.014

4.5 V

0.15

0.45

5.5 V

0.13

0.45
±1

p.A

98

200

p.A

II

VI = Vee or 0

5.5 V

lee

VI = Vee or 0

5.5 V

ei

VI = Vee or 0

5V

~Ieet

One input at 3.4 V, other
5.5 V
inputs at 0 or Vee

3

V

pF
1

rnA

t This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather
than 0 V or Vee.

2-22

maximum switching characteristics
PARAMETER

TO

FROM
/INPUT)

. (OUTPUT)

y

23
27
ClK
30 t
ORA15-0RAO 23
ORB15-0RBO 22
MUX2-MUXO 22
RC2-RCO
26
25
52-SO
19
63-BO
05El
25
ZERO IN
25
5ElOR
23
INC

ZEROUT

UNIT

ORA

ORB

STKWRN

24

16

25

COUT

CC

tpd

23 t

18
19
ns

20

20
16

Y

ten

tdis

YOE
RAOE
RBOE
YOE
RAOE
RBOE

16
18

ns

17
14
13

ns

14

t Decrementing register/counter A or B and sensing a zero.

2-23

setup and hold times
PARAMETER

FROM (INPUT)

TO (OUTPUT)

CC

Stack

15

Stack

9
6
9

DRA15-DRAO

RCA
INT RT

Een

DRB15-DRBO

2
....,

»

MPC
Stack

7

Stack

15

S2-S0

tsu

~

CO
OSEl
B3-BO
SElDR
ZEROIN

7

RCA, RCB

6

INT RT .

16

Stack

13

INT RT

13

Stack

12

INT RT

13

Stack

8

INT RT

14

Stack

10

INT RT

10

Stack

14

INT RT

13

y

MPC

6

RE

INT RT (ClK)

7

MUX2-MUXO

INT RT

12

Any

Any

Input

Destination

th

UNIT

7

INT
RC2-RCO

-I
CO
CO

MAX

11

INC

~

(")

RCB
INT RT

MIN

ns

ns

0

clock requirements
PARAMETER
tw1

Pulse duration, clock low

tw2

Pulse duration, clock high

tc

Clock cycle time

2-24

MIN
7
9
33

MAX

UNIT
ns
ns
ns

Architecture
The' ACT8818 microsequencer is designed with a 3-port architecture similar to the
bipolar SN74AS890 microsequencer. Figure 4 shows the architecture of the
'ACT8818. The device consists of the following principal functional groups:
1. A 16-bit microprogram counter (MPCl consisting of a register and
incrementer which generates the next sequential microprogram address
2. Two register/counters (RCA and RCBl for counting loops and iterations,
storing branch addresses, or driving external devices
3. A 65-word by 16-bit LIFO stack which allows subroutine calls and interrupts
at the microprogram level and is expandable and readable by external
hardware
4. An interrupt return register and Y output enable for interrupt processing at
the microinstruction level
5. A Y output multiplexer by which the next address can be selected from MPC,
RCA, RCB, external buses DRA and DRB, or the stack.
'ACT8818 control signals are summarized in Table 3. Those signals, which typically
originate from the instruction register, are Y output multiplexer controls, MUX2-MUXO.
These select the source of the next address; stack operation controls, S2-S0;
register/counter operation controls, RC2-RCO; OSEL, which allows the stack to be
read for diagnostics; input MUX select, SELDR; DRA and DRB output enables, RAOE
and RBOE; and INT, used during the first cycle of interrupt service routines to push
the address in the interrupt return register address onto the stack.
Control and data signals that commonly originate from the microinstruction and from
other hardware sources include INC, which determines whether to increment the MPC;
DRA and DRB, used to load or read loop counters and/or next addresses; and CC,
the condition code input. The address being loaded into the MPC is not incremented
if INC is low, allowing wait states and repeat until flag instructions to be implemented.
If INC originates from status, repeat until flag instructions are possible.
The condition code input CC typically originates from ALU status to permit test and
branch instructions. However, it must also be asserted under microprogram control
to implement other instructions such as continue or loop. Therefore, CC will generally
be controlled by the output of a status multiplexer. In this case, whether CC is to
be forced high, forced low or taken from ALU status will be determined bya status
MUX select field in the microinstruction.

2-25

CO


4. Register counters RCA and RCB, which can be used for additional address

-I

5. B3-BO, whose contents can replace the four least significant bits of the
DRA and DRB buses to support l6-way and 32~way branches

~

storage

C')

00
00

6. An external input onto the bidirectional Y port to support external
interrupts.

~

00

Use of controls MUX2-MUXO is explained further in the later section on
microprogramming the' ACT88l8.

Microprogram Counter
Based on system status and the current instruction, the microsequencer outputs the
next execution address in the microprogram. Usually the incrementer adds one to the
address on the Y bus to compute next address plus one. Next address plus one is
stored in the microprogram register at the beginning of the subsequent instruction cycle.
During the next instruction, this 'continue' address will be ready at the Y output MUX
for possible selection as the source of the subsequent instruction. The incrementer
thus looks two addresses ahead of the address in the instruction register to set up
a continue (increment by one) or repeat (no increment) address.
Selecting INC from status is a convenient means of implementing instructions that
must repeat until some condition is satisfied; for example, Shift ALU Until MSB = 1,
or Decrement ALU Until Zero. The MPC is also the standard path to the stack. The
next address is pushed onto the stack during a subroutine call, so that the subroutine
will return to the instruction following that from which it was called.

Register/Counters
Addresses or loop counts may be loaded directly into register/counters RCA and RCB
through the direct data ports DRA l5-DRAO and DRB l5-DRBO. The values stored in
these registers may either be held, decremented, or read. Independent control of both
the registers during a single cycle is supported with the exception of a simultaneous
decrement of both registers.

2-28

Stack
The positive edge clocked l6-bit address stack allows multiple levels of nested calls
or interrupts and can be used to support branching and looping. Seven stack operations
are possible:
1. Reset, which pulls all Y outputs low and clears the stack pointer and read
pointer
2. Clear, which sets the stack pointer and read pointer to zero
3. Pop, which causes the stack pointer to be decremented
4. Push, which puts the contents of the MPC, interrupt return register, or
ORA bus onto the stack and increments the stack pointer
5. Read, which makes the address indicated by the read pointer available
at the ORA port
6. Hold, which causes the address of the stack and read pointers to remain
unchanged
7. Load stack pointer, which inputs the seven least significant bits of ORA
to the stack pointer.

Stack Pointer
The stack pointer (SP) operates as an up/down counter; it increments whenever a push
occurs and decrements whenever a pop occurs. Although push and pop are two event
operations (store then increment SP, or decrement SP then read), the 'ACT8818
performs both events within a single cycle.

Read Pointer
The read pointer (RP) is provided as a tool for debugging microcoded systems. It permits
a nondestructive, sequential read of the stack contents from the ORA port. This
capability provides the user with a method of backtracking through the address
sequence to determine the cause of overflow without affecting program flow, the status
of the stack pointer, or the internal data of the stack.

Stack Warning/Read Error Pin
A high signal on the STKWRN/RER pin indicates a potential stack overflow or underflow
condition. STKWRN/RER becomes active under two conditions. If 62 of the 65 stack
locations (0-67) are full (the stack pointer is at 62) and a push occurs, the STKWRN/RER
pin outputs a high signal to warn that the !!tack is approaching its capacity and will
be full after two more pushes.
The STKWRN/RER signal will remain high if hold, push or pop instructions occur, until
the stack pointer is decremented to 63. If a push instruction is attempted when the
stack is full, the new address will be ignored and the old address in stack location
64 will be retained.

2-29

The second condition in which the STKWRN/RER signal goes high is to indicate that
the last location has been popped from the stack and the stack is empty. The user
may be protected from attempting to pop an empty stack by monitoring STKWRN/RER
before pop operations. A high level at this pin signifies that the last address has been
removed from the stack (SP = 0). This condition remains until an address is pushed
onto the stack and the stack pointer is incremented to one.

Interrupt Return Register
Unlike the MPC register, which normally gets next address plus one, the interrupt return
register simply gets next address. This permits interrupts to be serviced with zero
~ latency, since the interrupt vector replaces the pending address.

en

~ The interrupting hardware disables the Y output and forces the vector onto the

»
(")

microaddress bus. This event must be synchronized with the system clock. The first

-I address of the service routine must program INT low and perform a push to put the
CO contents of the interrupt return register on the stack.
CO
~

CO

2-30

Microprogramming the ' ACT8818
Microprogramming is unlike programming monolithic processors for several reasons.
First, the width of the microinstuction word is only partially constrained by the basic
signals required to control the sequencer. Since the main advantage of a
microprogrammed processor is speed, many operations are often supported by or
carried out in special purpose hardware. lookup tables, extra registers, address
generators, elastic memories, and data acquisition circuits may also be controlled by
the microinstruction.
The number of slices in a bit-slice ALU is user-defined, which makes the microinstruction
width even more application dependent. Types of instructions resulting from
manipulation of the sequencer controls are discussed below. Examples of some
commonly used instructions can be found in the later section of microinstructions and
flow diagrams. The following abbreviations are used in the tables in this section:
BR A
BR A'
BR B
BR B'
BR S
CAll A
CALL B
CALL A'
CAll B'
CAll S
ClR SP, RP
CONT/RPT
ORA
ORA'
ORB
ORB'
MPC
POP
PUSH
RCA
RCB
READ
RESET
RP
SP
STK

Y
Y
Y
Y
Y
Y
Y

00
....
00
00

t-

~
¢

-

ORA
ORA'
ORB
ORB'
STK
ORA; STK - MPC; SP - SP + 1
ORB; STK - MPC; SP - SP + 1
Y - ORA'; STK - MPC; SP - SP + 1
Y - ORB'; STK - MPC; SP - SP + 1
Y - STK; STK - MPC; SP - SP + 1
SP - 0; RP - 0
Y - MPC + 1 if INC = H; Y - MPC if INC = l
Bidirectional data port (can be loaded externally or from RCA)
ORA 15-0RA4::B3-80
Bidirectional data port (can be loaded externally or from RCB)
ORB15-0RB4::B3-BO
Microprogram counter
SP - SP - 1
STK - MPC; SP - SP + 1
Register/counter A
Register/counter B
Y - STK; RP - RP - 1
Y - 0; SP - 0; RP - 0
Read pointer
Stack pointer
Stack

.....
Z

(J)

2-31

Address Selection
Y -output multiplexer controls MUX2-MUXO select one of eight 3-source branches as
shown in Table4. The states of CC and ZERO determine which of the three sources
is selected as the next address. ZERO is set at the beginning of any cycle in which
a register/counter will decrement to zero.
Table 4. Output Controls (MUX2-MUXOI

MUX2RESET
MUXO

CJ)

Z

.....

~

»

n

XXX

Yes

III

No
No
No
No
No
No
No
No

llH
lHl
lHH
Hll
HlH
HHl
HHH

-I
00
00
-'

00

Y OUTPUT SOURCE
CC = L
CC - H
ZERO - l ZERO = H
All low
All low All low
STK
MPC
ORA
STK
MPC
ORB
STK
ORA
MPC
STK
ORB
MPC
ORA
ORB
MPC
ORA't
ORB'+
MPC
ORA
STK
MPC
STK
ORB
MPC

tORA 15-0RA4::B3-BO
tORB15-0RB4::B3-BO

By programming CC high or low without decrementing registers, only one outcome
is possible; thus, unconditional branches or continues can be implemented by forcing
the condition code. Alternatively, CC can be selected from status, in which case Branch
A on Condition Code Else Branch B instructions are possible, where A and B are the
address sources determined by MUX2-MUXO.
Decrement and Branch on Nonzero instructions, creating loops that repeat until a
terminal count is reached, can be implemented by programming CC low and
decrementing a register/counter. If CC is selected from status and registers are
decremented, more complex instructions such as Exit on Condition Code or End or
Loop are possible.
When MUX2-MUXO = HLH, the B3-BO inputs can replace the four least significant
bits of DRA or DRB to create 16-Way branches or, when CC is based on status, to
create 32-way branches.

Stack Controls
As in the case of the MUX controls, each stack-control coding is a three-way choice
based on CC and ZERO (see Table 5). This allows push, pop, or hold stack operations
to occur in parallel with the aforementioned branches. A subroutine call is accomplished
by combining a branch and push, while returns result from coding a branch to stack
with a pop.
2-32

Table 5. Stack Controls (S2-S0)
STACK OPERATION
S2-S0

OSEL

LLL

HLH

X
X
X
X
X
X

HHL

LLH
LHL
LHH

CC - L
ZERO = H
ZERO = L

CC = H

Reset/Clear

Reset/Clear

Reset/Clear

Clear SP/RP

Hold

Hold

Hold

Pop

Pop

Pop

Hold

Hold

Hold

Push

Push

Push

Hold

Hold

X

Push

Hold

Push

HHH

H

Read

Read

Read

HHH

L

Hold

Hold

Hold

HLL

00
~

ex>
ex>

IU

ct

.q
I'
Combining stack and MUX controls with status results and register decrements permits Z
even greater complexity. For example: Return on Condition Code or End of Loop; Call A
on Condition Code Else Branch to B; Decrement and Return on Nonzero; Call 16-Way.
Diagnostic stack dumps are possible using Read (S2-S0

= HHH) when OSEL is set high.

Register Controls
Unlike stack and MUX controls, register control is not dependent upon CC and ZERO.
Registers can be independently loaded, decremented, or held using register control
inputs RC2-RCO (see Table 6). All combinations are supported with the exception of
simultaneous register decrements. The register control inputs can be set to store branch
addresses and loop counts or to decrement loop counts, facilitating the complex
branching instructions described above.
Table 6. Register Controls (RC2-RCO)
RC2-RCO

REGISTER OPERATIONS
REG A

REG B

LLL

Hold

Hold

LLH

Decrement

Hold

LHL

Load

Hold

LHH

Decrement

Load

HLL

Load

Load

HLH

Hold

Decrement

HHL

Hold

Load

HHH

Load

Decrement

The contents of RCA are accessible to the DRA port when OSEL is low and the output
bus is enabled by RAOE being low. Data from RCB is available when DRB is enabled
by RBOE being low.
2-33

en

Continue/Repeat Instructions
The most commonly used instruction is a continue, implemented by selecting MPC
at the Y output MUX and setting INC high. If MPC is selected and INC is off, the current
instruction will simply be repeated.

C/)

Z
.....

A repeat instruction can be implemented in two ways. A programmed repeat (INC
forced low) may be useful in generating w,!it states, for example, wait for interrupt.
A conditional repeat (INC originates from status) may be useful in implementing Do
While operations. Several bit patterns in the MUX control field of the microinstruction
will place MPC on the microaddress bus. Continue/repeat instructions are summarized
in Table 7 below .

~

l>

Table 7. Continue/Repeat Encodings

n

-t

00
00
~

00

cc -

MUX2-MUXO

S2-S0

OSEl

lHL

LLH

X

CONT/RPT

lHL

LHL

X

CONT/RPT: POP

LHL

HLl

X

CONT/RPT: PUSH

LHL

HHH

CONT/RPT

LHL

HHH

LHH

LLH

LHH

LHL

LHH

HLL

LHH

HHH

LHH

HHH

HHL

LLH

HHL

LHL

0
1
X
X
X
0
1
X
X

HHL

LHH

X

CONT/RPT

HHL

HLL

X

CONT/RPT: PUSH

HHL

HHH

CONT/RPT

HHL

HHH

HHH

LLH

HHH

LHL

HHH

LHH

HHH

HLL

HHH

HHH

HHH

HHH

0
1
X
X
X
X
0
1

H

CONT/RPT: READ
CONT/RPT
CONT/RPT: POP
CONT/RPT: PUSH
CONT/RPT
CONT/RPT: READ
CONT/RPT
CONT/RPT: POP

CONT/RPT: READ
CONT/RPT
CONT/RPT: POP
CONT/RPT
CONT/RPT: PUSH
CONT/RPT
CONT/RPT: READ

Branch Instructions
A branch or jump to a given microaddress can also be coded several ways. RCA, ORA,
RCB, ORB, and STK are possible sources for branch. addresses (see Table 4). Branches
to register or stack are useful whenever the branch address could be stored to reduce
overhead.
2-34

The simplest branches are to DRA and DRB, since they require only one cycle and
the branch address is supplied in the microinstruction. Use of registers or stack requires
an initial load cycle (which may be combined with a preceding instruction), but may
be more practical when an entry point is referenced over and over throughout the
microprogram, for example, in error-handling routines. Branches to stack or register
also enhance sequencing techniques in which a branch address is dynamically
computed or multiple branches to a common entry point are used, but the entry point
varies according to the system state. In this case, the state change might require
reloading the stack or register.
In order to force a branch to DRA or DRB, CC must be programmed high or low. A ~
branch to stack is only possible when CC is forced low (see Table 4).
00
·00
When CC is low, the ZERO flag is tested, and if a register decrements to zero the tbranch will be transformed into a Decrement and Branch on Nonzero instruction. ~
Therefore, registers should not be decremented during branch instructions using o::t
CC = 0 unless it is certain the register will not reach terminal count. Branch instructions ~
are summarized in Table 8, below. Call (Branch and Push MPC) instructions and Return
(Branch to Stack and Pop) instructions are discussed in later sections.

en

Table 8. Branch Encodings
MUX2-MUXO 52-SO OSEL

CC - H

LLL

LHL

X
X

LLL

HHH

a

BA A

LLL

HHH

1

BA A: AEAD

LLH

LlH

X

BA B

LLH

LHL

X

BA B: POP

LLH

HHH

a

BA B

LLH

HHH

1

BA B: AEAD

HLL

LLH

X

BA B

HLL

LHL

BA B: POP

HLL

LHH

X
X

HLL

HHH

a

BR B

HLl

HHH

1

HLH

LLH

X

BR B: AEAD
BA B' (16-way)

HLH

LHL

X

BR B' (16-way) : POP

HLH

LHH

X

BR B' (16-way)

HLH

HHH

a

BR B' (16-way)

HLH

HHH

1

BR B' (16-way): READ

LLL

LLH

X

BR S: CLR SP/AP

LLL

LHL

X

BR S

LLL

LLH

BA A
BA A: POP

BR B

2-35

Table 8. Branch Encodings (Continued)
MUX2-MUXO 52-SO OSEL

CC - H

LLL

HLL

X

BR S

LLL

HHH

0

BR S

LLL

HHH

1

BR S: READ

LLH

LLH

X

BR S: CLR SP/RP

LLH

LHL

X

BR S

LLH

HLL

X

BR S

z
......

LLH

HHH

0

BR S

LLH

HHH

1

BR S: READ

.J:a.

»
(")

LHL

LLH

X

BR S: CLR SP/RP

LHL

LHL

X

BR S

-4

LHL

HLL

X

BR S

LHL

HHH

0

LHL

HHH

1

BR S
BR S: READ

LHH

LLH

X

BR S: CLR SP/RP

LHH

LHL

X

BR S

LHH

HLL

X

BR S

LHH

HHH

0

BR S

LHH

HHH

1

BR S: READ

HLL

LLH

X

BR A: CLR SP/RP

HLL

LHL

X

BR A

HLL

LHH

X

BR A: POP

HLL

HLL

X

BR A

HLL

HHH

0

BR A

HLL

HHH

1

BR A: READ

HLH

LLH

X

BR A' (16-way): CLR SP/RP

HLH

LHL

X

BR A' (16-way)

HLH

LHH

X

BR A' (16-way): POP

HLH

HLL

X

BR A' (16-way)

HLH

HHH

0

BR A' (16-way)

HLH

HHH

1

BR A' (16-way): READ

HHL

LLH

X

BR A: CLR SP/RP

HHL

LHL

X

BR A

HHL

LHH

X

BR A: POP

HHL

HLL

X

BR A

HHL

HHH

0

BR A

HHL

HHH

1

BR A: READ

en

00
00
~

00

2-3.6

Table 8. Branch Encodings (Concluded)

cc

MUX2-MUXO S2-S0 OSEL
HHH

= H

LLH

X

BR B: CLR SP/RP

HHH

LHL

X

BR B

HHH

LHH

X

BR B: POP

HHH

HLL

X

BR B

HHH

HHH

0

BR B

HHH

HHH

1

BR S: READ

00
t'""

Conditional Branch Instructions

00
00

Perhaps the most useful of all branches is the conditional branch. The' ACT8818
permits three modes of conditional branching: Branch on Condition Code; Branch
16-Way from DRA or DRB; and Branch on Condition Code 16-Way from DRA Else
Branch 16cWay from DRB. This increases the versatility of the system and the speed
of processing status tests because both single-bit and 4-bit status are allowed.

I-

Testing single bit status is preferred when the status can be set up and selected through
a status MUX prior to the conditional branch. Four-bit status allows the' ACT8818
to process instructions based on Boolean status expressions, such as Branch if Overflow
and Not Carry if Zero or if Negative. It also permits true n-way branches, such as If
Negative then Branch to X, Else if Overflow, and Not Carry then Branch to Y. The
tradeoff is speed versus program size. Since multiway branching occurs relatively
infrequently in mos.t programs, users will enjoy increased speed at a negligible cost.
Conditional branching codes are listed in Table 9. Call (Branch and Push MPC)
instructions and Return (Branch to Stack and Pop) instructions are discussed in later
sections.
Table 9. Conditional Branch Encodings
MUX2MUXO

S2-S0

OSEL

cc

CC = L

= H

LLL

LLH

X

BR S: CLR SP/RP

LLL

LHL

X

BR S

BR A: POP

LLL

HLL

X

SR S

CALL A

LLL

HHH

0

SR S

BR A

LLL

HHH

1

SR S: READ

BR A: READ

LLH

LLH

X

BR S: CLR SP/RP

BR B

LLH

HHH

0

BR S

BR B

LLH

LHL

X

BR S

BR S: POP

LLH

HLL

X

BR S

CALL B

LLH

HHH

1

SR S: READ

BR B: READ

LHL

LLH

X

BR S: CLR SP/RP

CONT/RPT

BR A

~

o::t
~
CJ)

Table 9. Conditional Branch Encodings (Concluded)
MUX2-

CC -

82-80

08EL

LHL

LHL

X

BR S

CONT/RPT: POP

LHL

HLL

X

BR S

CONT/RPT: PUSH

LHL

HHH

0

BR S

CONT/RPT

LHL

HHH

1

BR S: READ

CONT/RPT: READ

LHH

LLH

X

BR S: CLR SP/RP

CONT/RPT

LHH

X

BR S

CONT/RPT: POP

LHH

LHL
HLL

X

BR S

CONT/RPT: PUSH

LHH

HHH

0

BR S

CONT/RPT

(")

LHH

HHH

1

BR S: READ

CONT/RPT: READ

-t

HLL

LLH

X

BR A: CLR SP/RP

BR B
BR B: POP

MUXO

en

z-.oJ
~

l>

CC "" H

L

00
00

HLL

LHL

X

BR A

...10

HLL

LHH

X

BR A: POP

BR B

HLL

HLL

X

BR A

CALL B

00

HLL

HHH

0

BR A

BR B

HLL

HHH

1

BR A: READ

HLH

LLH

X

BR A' (16-way): CLR SP/RP

BR B: R.EAD
BR B' (16-way)

HLH

LHL

X

BR A' (16-way)

BR B' (16-way): POP

HLH

LHH

X

BR A' (16-way): POP

BR B' (16-way)

HLH

HLL

X

BR A' (16-way)

CALL B' (16-way)

HLH

HHH

BR B'( l6-way)

HHH

0
1

BR A' (16-way)

HLH

BR A' (16-way): READ

BR B' (16-way): READ

HHL

LLH

X

BR A: CLR SP/RP

CONT/RPT

HHL

LHL

X

BR A

CONT/RPT: POP

HHL

LHH

X

BR A: POP

CONT/RPT

HHL

HLL

X

BR A

CONT/RPT: PUSH

HHL

HHH

0

BR A

CONT/RPT

HHL

HHH

1

BR A: READ

CONT/RPT: READ

HHH

LLH

X

BRB: CLR SP/RP

CONT/RPT

HHH

LHL

X

BR B

CONT/RPT: POP

HHH

LHH

X

BR B: POP

CONT/RPT

HHH

HLL

X

BR B

CONT/RPT: PUSH

HHH

HHH

0

BR B

CONT/RPT

HHH

HHH

1

BR B: READ

CONT/RPT: READ

2-38

loop Instructions
Up to two levels of nested loops are possible when both counters are used
simultaneously. Loop count and levels of nesting can be increased by adding external
counte~s if desired. The simplest and most widely used of the loop instructions is
Decrement and Branch on Nonzero, in which CC is forced low while a register is
decremented. As before, many forms are possible, since the top-of-Ioop address can
originate from RCA, DRA, RCB, DRB, or the stack (see Table 4). Upon terminal count,
instruction flow can either drop out of the bottom of the loop or branch elsewhere.
When loops are used in conjunction with CC as status, B3-BO as status and/or stack
manipulation, many useful instructions are possible, including Decrement and Branch
on Nonzero else Return, Decrement and Call on Nonzero, and Decrement and Branch
16-Way on Nonzero. Possible variations are summarized in Table 10. Call (Branch and
Push MPC) instructions and Return (Branch to Stack and Pop) instructions are discussed
in later sections.

00
t'""
00
00

t;

rex>
ex>

I-

o

The various branch instructions described above can be merged with a push instruction 

Flow diagrams and suggested code for the sample microinstructions are also given

....

hexadecimal numbers. Fields in microinstructions are binary numbers except for inputs

(') below. Numbers inside the circles are microword address locations expressed as

00
00 on DRA or DRB, which are also in hexadecimal. For a discussion of sequencing

...a instructions, see the preceding section on microprogramming.

00

Continue
To Continue (Instruction 10), this example uses an instruction in Table 7 with
CONT/RPT in the instruction column and no stack operation. INC and CC must be
programmed high one cycle ahead of instruction 10 for pipelining.
Address
(Set-up)
10

Instruction
Continue

MUX2-MUXO 52-SO R2-RO OSEL
XXX
110

xxx
111

XXX
XXX

CC

INC

x

1
X

X

o

ORA

ORB

XXXX XXXX
XXXX XXXX

Continue and Pop
To Continue and decrement the stack pointer (Pop), this example uses an instruction
in Table 7 with CONT/RPT: POP in the instruction column. INC and CC are forced
high in the previous instruction.
Address

Instruction

(Set-up)
10
Continue/Pop

MUX2-MUXO 52-SO R2-RO OSEL

CC

INC

XXX
010

1

X

1
X

XXX
110

XXX
XXX

X
X

ORA

ORB

XXXX XXXX
XXXX xxxx

Continue and Push
To Continue and push the microprogram counter onto the stack (Push), this example
uses an instruction in Table 7 with CONT/RPT: PUSH in the instruction column. INC
and CC are forced high one cycle ahead of Instruction 10 for pipelining.
Address

Instruction

(Set-up)
10
Continue/Pust"!

2-44

MUX2-MUXO 52-SO R2-RO OSEL

CC

INC

XXX
100

1
X

1
X

XXX
110

XXX
XXX

X

o

ORA

ORB

XXXX XXXX
XXXX XXXX

>--=--

Figure 5. Continue

IMPOSSIBLE

Figure 6. Continue and Pop

Figure 7. Continue and Push

2·45

Branch (Example 1)
To Branch from address 10 to addr.ess 20, this example uses a BR A instruction from
the CC = H column of TableB. CC must be programmed high one cycle ahead of
Instruction 10 for pipelining.

(J)

Z

.....

~
(')
....
00
co

Address

Instruction

(Set-up)
10

BR A

MUX2-MUXO

S2-S0

xxx

xxx

000

111

R2-RO OSEL
XXX
XXX

X

o

CC

INC

ORA

ORB

1
X

X
X

XXXX
0020

XXXX
XXXX

Branch (Example 2)
To Branch from address 10 to address 20, this example uses a BR A instruction from
the CC = L column of Table B. CC is programmed low in the previous instruction;
as a result, a ZERO test follows the condition code test in Instruction 10. To ensure
that a ZERO = H condition will not occur, registers should not be decremented during
this instruction.

~

00

Address
(Set-up)
10

Instruction
BR A

MUX2-MUXO S2-S0
XXX
110

XXX
111

R2-RO

OSEL

XXX
000

X
0

CC

INC

ORA

ORB

0
X

X
X

XXXX
0020

XXXX
XXXX

Sixteen-Way Branch
To Branch 16-Way, this example uses a BR B' instruction in Table B. CC is
programmed high in the previous instruction. The branch address is derived from the
concatenation DRB15-DRB4::B3-BO.
Address

Instruction

(Set-up)
10

BR B'

2-46

MUX2-MUXO S2-S0
XXX
101

XXX
111

R2-RO

OSEL

CC

INC

XXX
XXX

X
0

X

X
X

ORA

ORB

XXXX XXXX
XXXX 0040

00
or-

00
00

I-

(J


(")
-t

00
00
~

To Branch 3-Way, this example uses an instruction from Table 10 with BR A in the
ZERO = L column, CONT/RPT in the ZERO = H column and BR B in the CC = H
column. To enable the ZERO = H path, register A must decrement to zero during this
instruction (see Table 6 for possible register operations). INC is programmed high in
Instruction 10 to set up the Continue.

00
Address
(Set-up)
10
11

Instruction

MUX2-MUXO 52-SO R2-RO OSEL CC INC

Continue and
Load Reg A
Decrement Reg A;
Branch 3-Way

XXX

XXX

XXX

X

110

111

010

0

t

100

111

001

0

X

ORA

ORB

XXX X XXXX
XXXX XXXX
X

0020

0030

t Selected from external status

Thirty-Two-Way Branch
To Branch 32-Way, this example uses an instruction from Table 9 with BR A' in the
CC = L column and BR B' in the CC = H column. The four least significant bits of
the DRA' and DRB' addresses must be input at the B3-BO port; these are concatenated
with the 12 most significant bits of DRA and DRB to provide new addresses DRA'
(DRA 15-DRA4::B3-BO) and DRB' (DRB15-DRB4::B3-BO).
Address
(Set-up)
10

2-48

Instruction
32-way Branch

MUX2-MUXO 52-SO R2-RO OSEL CC INC
XXX
101

XXX
XXX
111000

X'
0

X

X

ORA

ORB

XXXX XXXX
0040 0030

H IMPOSSIBLE"

• no register decrement

Figure 11. Conditional Branch

Figure 12. Three-Way Branch

• no register decrement

Figure 13. Thirty-Two-Way Branch

2-49

Repeat
To Repeat (Instruction 10), this example uses an instruction in Table 7 with CONT/RPT
in the instruction column. INC must be programmed low and CC high one cycle ahead
of Instruction 10 for pipelining.

(J)

z
.....

~

»
n

-t

co
co
....a
co

Address

Instruction

(Set-up)
10

Continue

MUX2-MUXO 52-SO R2-RO OSEL CC INC

xxx

XXX
110

111

XXX
XXX

X
0

o
X

ORA

ORB

XXXX XXXX
XXXX XXXX

Repeat on Stack
To Continue and push the microprogram counter onto the stack (Push), this example
uses an instruction in Table 7 with CONT/RPT: PUSH in the instruction column. INC
and CC must be forced high one cycle ahead for pipelining.
To Repeat (Instruction 12), an BR S instruction from the ZERO = L column of Table 8
is used. To avoid a ZERO = H condition, registers are not decremented during this
instruction (see Table 6 for possible register operations). CC and INC are
programmed high in Instruction 12 to set up the Continue in Instruction 11.
Address
(Set-up)
10
11
12

Instruction
Continue/Push
Continue
BR Stack

MUX2-MUXO 52-SO R2-RO OSEL CC INC
XXX
110
110
010

XXX
100
111
111

INC-O

XXX
XXX
XXX
000

X
X
0
0

0

CC-1

>...;;L:;....-_ IMPOSSIBLE
H

V-MPC

Figure 14. Repeat

2-50

X
X

ORA

ORB

XXXX
XXXX
XXXX
XXXX

XXXX
XXXX
XXXX
XXXX

ex)

.....

ex)
ex)

....
u

c:(

.q-

"""

:2

CJ)

• no register decrement

Figure 15. Repeat on Stack

2-51

Repeat Until CC

=

H

To Continue and push the microprogram counter onto the stack (Push). this example
uses an instruction in Table 7 with CONT/RPT: PUSH in the instruction column. INC
and CC must be forced high one cycle ahead for pipelining.
To Repeat Until CC = H (Instruction 12), an instruction from Table 9 with BR S
in the CC = L column and CONT/RPT: POP in the CC = H column is used. To avoid
a ZERO = H condition, registers are not decremented (See Table 6 for possible register
operations). CC and INC are programmed high in Instruction 12 to set up the
(J) Continue in Instruction 11 . A consequence of this is that the instruction following 13
Z cannot be conditional.
--J
~

»
(')
-I

00
00
~

00

Address
(Set-up)
10
11
12

Instruction
Continue/Push
Continue
BR Stack else
Continue

MUX2-MUXO 52-SO R2-RO OSEL CC INC
XXX
110
110

XXX
100
111

XXX
XXX
XXX

X
X
0

010

111

000

0

1
1

t

ORA

ORB

XXX X XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX

t Selected from external status

Loop Until Zero
To Continue and push the microprogram counter onto the stack (Push), this example
uses an instruction in Table 7 with CONT/RPT: PUSH in the instruction column. INC
and CC are forced high one cycle ahead for pipelining. Register A is loaded with
the loop counter using a Load A instruction from Table 6.
To decrement the loop count, a decrement register A and hold register B instruction
from Table 6 is used. To Repeat Else Continue and Pop (decrement the stack pointer).
an instruction from Table 9 with BR S in the ZERO = L column and CONT/RPT: POP
in the ZERO = H column is used. CC is programmed low in Instruction 11 to
force the ZERO test in Instruction 12; it is programmed high in Instruction 12 to set
up the Continue in Instruction 11.
Address
(Set-up)
10
11
12

2-52

Instruction
Continue/Push
Continue/Load
Reg A
Decrement Reg A;
BR 5 else
Continue: Pop

MUX2-MUXO 52-SO R2-RO OSEL CC INC
XXX
110

XXX
100

XXX
XXX

X
0

110

111

010

0

000

010

001

DRA

DRB

XXXX XXXX
XXXX XXXX
0

XXX X XXXX

XXXX XXXX

00
t-

OO
00
~

U


-t

00
00

H

N

J

W

K

L

M
N
P

R

S
T

• •
•••
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •

3

4

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

• • • •
• • • •
• • • •
• • • •

•
•
•
•
•
•
•
•
•
•
•
•
•

5

•
•
•
•

6

•
•
•
•

7

•
•
•
•

12 13 14 15 16 17

8

9

•
•
•
•

• • • •
• • • •
• • • •
• • • •

•
•
•
•

• • • • •

10 11

•
•
•
•

• • • • •

• • • • •
• • • • •

Figure 2. SN74ACT8832 . .. GB Package

3-16

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •

432-BIT
REGISTERED
ALU
WRITE EN

L.-1

CLK

CLK

INPUT
SELECT

I

CARRY IN

1:

RF
OPERAND
SELECT

EBO-EBl

....

sroo-S103
SSF

"CFO

I

ALU

AO

BPORTI O
READ'
ADDRESS •
SELECT 5

BO

·
··
I ·
·

CONFIGURATION
MODE
SELECT

DA
PORT

TEST PINS

TPO-TPl

1

ALU SHIFTER

10

I

PARITY
I/O

OUTPUT

DB
PORT

POR~I
INSTRUCTIONS

15
PARITY
STATUS

16
7

"-

DAO-DA31

OEB

"-

OBO-OB31

0EYi5-0E'l3

.....
.....

OA31

PAO

YO-Y31

EN

PA3

CO
CO

PBO

()

STATUS

,

·· ·· ~.
· ·
0

31

Z

en

PYl
PY2
PY3
PERI!A

Y BUS
MASTER/SLAVE
COMPARATOR

PERRY
MSERR

SIGN

N

CARRY-OUT

C

BYTE OVERFLOW

 Vee) . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 'OK(VO < 0 or Vo > Vee) .......... ± 50 mA
eontinuous output current, 10 (VO = 0 to Vee) ........... "
± 50 mA
eontinuous current through Vee or GND pins. . . . . . . . . . . . .. ± 100 mA
Operating free-air temperature range. . . . . . . . . . . . . . . . . .. ooe to 70 0 e
Storage temperature range ...................... - 65 °e to 150 °e
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond
those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximumrated conditions for extended periods may affect device reliability.

Table 3. Recommended Operating Conditions
PARAMETER

Vee Supply voltage
High-level input voltage

VIH
VIL

Low-level input voltage

IOH

High-level output current

IOL

Low-level output current

VI

Input voltage

Output voltage
Vo
dt/dv Input transition rise or fall rate
TA

Operating free-air temperature

MIN

NOM

MAX

4.5
2
0

5.0

5.5

V

Jt:i§c

V

,;;:":;'0.8
-8
~t"'~"
,{,;"
8
Q~;,5"?
Vee

,.;1q~·'

0
0

Vee

15
70

UNIT

V
mA
mA
V
V
ns/V
°e

3-25

N
M
00
00

I-

o


5.49

5,5 V
4.5 V

10l = 8 mA

5.5 V
5.5 V

VI = Vee or 0
VI = Vee or

4.49

5.5 V

O.

10

MIN

MAX

~"'~;:"

3.76

,,~~

~3h
",,"1~")
"..:;f;,)
d;I,;'~

UNIT

V

",,~~~;~'<
(;;(;"

4.76

O.~;I:"
i

,t~,.

'i'

0,45

""G·I'

,,"~f~f

V

0.45

,~i~,i:;:;'

±1

".;,

5.5 V

p.A
p.A
pF

5V

VI = Vee or 0

ei

MAX

,,,,:~,;~j'

5.5 V

10l = 20 p.A

ICC

TYP

4.5 V

4.5 V

Val

en

MIN

4.5 V

10H = -8 mA

II

TA = 25°C
VCC

One input at 3.4 V,

~Ieet

other inputs at

(1

5.5 V

1

mA

o or Vee

-f

00
00

Table 5. Register File Write Setup

Co\)

N

PARAMETER
C5-CO
DA/B32-DA/BO. PA/B3-PA/BO

1'7-14
OEY3-0EYO
tsu

MAX

7

i,,;~l~

13

~,",:~,;:""

7

.d~(';;i''''

Y31-YO

4

4

SElRF(DA,DB,PA,PB)

5c::S

SElRF(Y)

.,':I~i

SIO

";'10

IESI03-IESIOO
ALL

UNIT

4

WE3-WEO

SElMO
th

MIN

,,,,<~,

ns

9
10
0

tThis is the increase in supply current for each input that is at one of the specified TTL voltge levels rather
then 0 V to Vee.

3-26

Table 6. Maximum Switching Characteristics
TO (OUTPUT)
PARAMETER

FROM (INPUT)

A5-AO,B5-BO
DA31-DAO,PA3-PAO
DB31-DBO,PB3-PBO

PA/B

Y

C

Z

SID

36

30

37

28

36

25

37

25

PERRA/B

20

OVR

DA/B

PY

30

37

16

37

28

37

37
32

Cn

30

22

31

24

28

28

EA

37

28

37

25

31

37

37

EB1-EBO

37

28

37

25

31

37

37

17-10
CF2-CFO

37
37

30
30

37
37

28
28

'~;;/
32
~A,.l
32 ",,;~1'

OEB,OEA
tpd

UNIT

N

,.

OEY3-0EYO

20

SElMQ

15

,:;'\"

20

15

ClK

21

28

ClKMQ

37

37

RClK

37

IE5103-IESIOO

15

25

SSF

25

30

y

24

32

22

30

~

27

25

37

37

22

30

I-

."
(.)

«
Z

27

25

N

M

20

S103-5100

37

~.

37
37
ns

l,·~(~:i"-'

32

MSERR

15

1,;,11<;:',,,
25

,0>'' ' '\

PERRY

en

15

15

3-27

I

ACT8832 Registered ALU

The SN74ACT8832 is a 32-bit registered ALU that can be configured to operate as
four 8-bit ALUs, two 16~bit ALUs, or a single 32-bit ALU. The processor instruction
set is 100 percent upwardly compatible with the' AS888 and includes 13 arithmetic
and logical functions with 8 conditional shifts, multiplication, division, normalization,
add and subtract immediate, bit and byte operations, and data conversions such as
BCD, excess-3, and sign magnitude. New instructions permit internal flip-flops
controlling BCD and divide operations to be loaded or read.
Additional functions added to the' ACT8832 include byte parity and master/slave
operation. Parity is checked at the three data input ports and generated at the Y output
port. The 64-word register file is 36 bits wide to permit storage of the parity bits.
Master/slave comparator circuitry is provided at the Y port.
The DA and DB ports can simultaneously input data to the ALU and the 64-word by
36-bit register file. Data and parity from the register file can be output on the DA and
:2
" DB ports. Results of ALU and shift operations are output at the bidirectional Y port.
,J:a. The Y port can also be used in an input mode to furnish external data to the register
file or during master/slave operation as an input to the master/slave comparator.
-I Three 6-bit address ports allow a two-operand fetch and an operand write to be
00
00 performed at the register file simultaneously. An MQ shifter and MQ register can also
W be configured to function independently to implement double-precision 8-bit, l6-bit,
N
and 32-bit shift operations. An internal ALU bypass path increases the speeds of
multiply, divide and normalize instructions. The path is also used by , ACT8832
instructions that permit bits and bytes to be manipulated.
U)

f)

Architecture
Figure 4 is a functional block diagram of the' ACT8832. Control input signals are
summarized in Table 7. Data flow and details of the functional elements are presented
in the following paragraphs.

3-28

Table 7. 'ACT8832 Response to Control Inputs
SIGNAL

HIGH

LOW

CF2-CFO

See Table 11

See Table 11

EA

Selects external DA bus

Selects register file

EB1-EBO

See Table 9

See Table 9

IESI03-IESI00

Normal operation

Force corresponding SIO

17-10

See Table 15

MQSEl

Selects MQ register

Selects AlU

OEA

Inhibits DA and PA output

Enables DA and PA output
Enables DB and PB output

inputs to high impedance
See Table 15

OEB

Inhibits DB and PB output

OEY3-0EYO

Inhibits Y and PY outputs

Enables Y and PY outputs

RFSEl1-RFSElO

See Table 8

See Table 8

SSF
TP1-TPO

Selects shifted AlU output

Selects AlU (unshifted) output

See Table 14

See Table 14

WE3-WEO

Inhibits register file write

Byte enables for register file

N
M
00
00

....
u



CO
CO
W

3·40

Circular right double precision shift

Circular left shift MQ register
load MQ register
Pass AlU to Y

Table 15 .• ACT8832 Instruction Set (Continued)
GROUP 3 INSTRUCTIONS
INSTRUCTION BITS

17-10
(HEX)

MNEMONIC

08

SET1

18

SETO

Set bit 0

28

TB1

Test bit (one)
Test bit (zero)

FUNCTION
Set bit 1

38

TBO

48

ABS

58

SMTC

Sign magnitude/two's complement

68

ADDI

Add immediate

78

SUBI

Subtract immediate

88

BADD

Byte add R to S

98

BSUBS

Byte subtract S from R

A8
B8

BSUBR

Byte subtract R from S

BINCS

Byte increment S

C8

BINCNS

08

BXOR

E8

BAND

F8

BOR

Absolute value

Byte increment negative S
Byte XOR Rand S
Byte AND Rand S
Byte OR Rand S

3-41

Table 15. 'ACT8832 Instruction Set (Continued)
GROUP 4 INSTRUCTIONS
INSTRUCTION BITS

17-10

MNEMONIC

FUNCTION

(HEX)

00

CRC

Cyclic redundancy character accumulation

10

SEL

Select S or R

20

SNORM

30

DNORM

Single length normalize
Double length normalize

40
50
60

DIVRF
SDIVQF

Divide remainder fix
Signed divide quotient fix

SMUll

Signed multiply iterate

70

SMULT

2:

80
90

SDIVIN
SDIVIS

Signed multiply terminate
Signed divide initialize

~

l>

AO

SDIVI

Signed divide iterate

("')

80

UDIVIS

Unsigned divide start

-I

CO

UDIVI

Unsigned divide iterate

W
N

DO
EO

UMULI
SDIVIT

FO

UDIVIT

Unsigned multiply iterate
Signed divide terminate
Unsigned divide terminate

en
-....I

00
00

3-42

Signed divide start

Table 15. 'ACT8832 Instruction Set (Continued)
GROUP 5 INSTRUCTIONS
INSTRUCTION BITS

17-10
(HEX)

MNEMONIC

OF

LOADFF

1F

CLR

Clear

2F

CLR

Clear

3F

CLR

Clear

4F

CLR

Clear

5F

DUMPFF

6F

CLR

7F

BCDBIN

BCD to binary

SF

EX3BC

Excess-3 byte correction

M

CO
CO
I-

FUNCTION
Load divide/BCD flip-flops

Output divide/BCD flip-flops
Clear

9F

EX3C

Excess-3 word correction

AF

SDIVO

Signed divide overflow test

BF

CLR

Clear

CF

CLR

Clear

OF

BINEX3

EF

CLR

Clear

FF

NOP

No operation

N

(J

«
'¢
,....

. Binary to excess-3

z

en

Group 1, a set of ALU arithmetic and logic operations, can be combined with the userselected shift operations in Group 2 in one instruction cycle. The other groups contain
instructions for bit and byte operations, division and multiplication, data conversion,
and other functions such as sorting, normalization and polynomial code accumulation.

Arithmetic/Logic Instructions with Shifts
The seven Group 1 arithmetic instructions operate on data from the Rand/or S
multiplexers and the carry-in. Carry-out is evaluated after ALU operation; other status
pins are evaluated after the accompanying shift operation, when applicable. Group 1
logic instructions do not use carry-in; carry-out is forced to zero.
Possible shift instructions are listed in Group 2. Fourteen single and double precision
shifts can be specified, or the ALU result can be passed unShifted to the MQ register
or to the specified output destination by using the LOADMQ or PASS instructions.
Table 16 lists shift definitions.
When using the shift registers for double precision operations, the least significant
half should be placed in the MQ register ano the most significant half in the At.U for
passage to the ALU shifter. An example of a double-precision shift using the ALU and
MQ shifters is given in Figure 8.

3-43

SERIAL DATA
INPUT SIGNALS

SIOO

-1>---,'---1

Single Precision Logical Right .Single Shift, 32-Bit Configuration
SERIAL DATA
INPUT SIGNALS

SIOO-+-----,

en

z-..J
~

»

("')

-I
CO
CO
W
N

Double Precision Logical Right Single Shift, 32-Bit Configuration

Figure a.Shift Examples. 32-Bit Configuration
All Group 2 shifts can be made conditional using the conditional shift pin (SSF). If the
SSF pin is high or floating. the shifted ALU output will be sent to the output buffers.
MQ register. or both. If the SSF pin is pulled low. the ALU result will be passed directly
to the output buffers and any MQ shifts will be inhibited.
Table 16. Shift Definitions
SHIFT TYPE
Left

NOTES
Moves a bit one position towards the most significant bit

Right

Moves a bit one position towards the least significant bit

Arithmetic right

Retains the sign unless an overflow occurs, in which case, the
sign would be inverted

Arithmetic left

May lose the sign bit if an overflow occurs. Zero is filled into
the least significant bit unless the bit is set externally

Circular right

Fills the least significant bit in the most significant bit position

Circular left

Fills the most significant bit in the least significant bit position

Logical right

Fills a zero in the most significant bit position unless the bit

Logical left

Fills a zero in the least significant bit position unless the bit

is forced to one by placing a zero on an SIO pin
is forced to one by placing a zero on an SIO pin

The bidirectional SIO pins can be used to supply external end fill bits for certain Group 2
shift instructions. When SIO is high or floating, a zero is filled, otherwise a 1 is filled
Table 17 lists instructions that make use of the SIO inputs and identifies input and
output fUnctions.·
Table 17. Bidirectional SIO Pin Functions
INSTRUCTION
BITS 17-10

SIO
MNEMONIC

110

0*

SRA
SRAD

0
0

Shift out

1*
2*

SRL

I

Most significant bit

(HEX)

DATA

Shift out

3*

SRLD

I

Most significant bit

4*

SLA

I

Least significant bit

5*

SLAD

I

Least significant bit

6*

SLC

Shifted input to MO shifter

N
M
CO
CO

7*

SLCD

Shifted input to MO shifter

(.)

8*

SRC

9*

SRCD

A*

MOSRA

0
0
0
0
0

8*

MOSRL

I

Most significant bit

Shifted input to ALU shifter
Shift out

MOSLL

I

Least significant bit

0*

MOSLC

Shifted input to MO shifter

00

CRC

0
0

20

SNORM

I

Least significant bit

30

DNORM

I

Least significant bit

60

SMUll

ALUO

Internally generated end fill bit

90

SDIVIS

AO

SDIVI

80

UDIVIS

CO

UDIVI

DO

UMULI

EO

SDIVT

FO

UDIVIT

0
0
0
0
0
0
0
0
0
0

7F

BCD BIN

I

Least significant bit

OF

BINEX3

0

Shifted input to MO register

70

SMULT
SDIVIN

~
,....
zen

Shifted input to ALU shifter

C*

80

I-

ALUO
Internally generated end fill bit
Internally generated end fill bit
Internally generated end fill bit
Internally generated end fill bit
Internally generated end fill bit
Internal input
Internally generated end fill bit
Internally generated end fill bit

3A5

Other Arithmetic Instructions
The 'ACT8832 supports two immediate arithmetic operations. ADDI and SUBI
(Group 3) add or subtract a constant between the values of 0 and 15 from an operand
on the S bus. The constant value is specified in bits A3-AO.
Twelve Group 4 instructions support serial division and multiplication. Signed, unsigned
and mixed multiplication are implemented using three instructions: SMUll, which
performs a signed times unsigned iteration; SMULT, which provides negative weighting
of the sign bit of a negative multiplier in signed multiplication; and UMULI, which
performs an unsigned multiplication iteration. Algorithms using these instructions are
given in Tables 18, 19, and 20. These include: signed multiplication, which performs
a two's complement multiplication; unsigned multiplication, which produces an
unsigned times unsigned product; and mixed multiplication which multiplies a signed
multiplicand by an unsigned multiplier to produce a signed result.

en

z

Table 18. Signed Multiplication Algorithm

......
~

»

OP

(')

CODE

-t

E4

LOADMO
SMUll

N-1 t

Accumulator

Multiplicand

J\)

60
70

SMULT

1

Accumulator

Multiplicand

CO
CO
W

MNEMONIC

CLOCK

INPUT

INPUT

CYCLES

SPORT

R PORT

1

Multiplier

-

OUTPUT
Y PORT
Multiplier
Partial product
Product (MSH):I:

Table 19. Unsigned Multiplication Algorithm
OP
CODE

MNEMONIC

CLOCK

INPUT

INPUT

CYCLES

SPORT

R PORT

Multiplier

-

E4

LOADMO

DO

UMULI

1
N-1 t

Accumulator

Multiplicand

DO

UMULI

1

Accumulator

Multiplicand

OUTPUT
Y PORT
Multiplier
Partial product
Product (MSH):I:

Table 20. Mixed Multiplication Algorithm
OP
CODE

MNEMONIC

E4

LOADMO

60
60

CLOCK

INPUT

INPUT

CYCLES

SPORT

R PORT

Multiplier

-

OUTPUT
Y PORT

SMUll

1
N-1 t

Multiplier

Accumulator

Multiplicand

Partial product

SMUll

1

Accumulator

Multiplicand

Product (MSH):I:

tN =·8 for quad 8-bit mode, 16 for dual 16-bit mode, 32 for 32-bit mode.
tThe least significant half of the product is in the MQ register.

3-46

Instructions that support division include start. iterate and terminate instructions for
unsigned division routines (UDIVIS, UDIVI and UDIVIT); initialize, start, iterate and
terminate instructions for signed division routines (SDIVIN, SDIVIS, SDIVI and SDIVIT);
and correction instructions for these routines (DIVRF and SDIVQF). A Group 5
instruction, SDIVO, is available for optional overflow testing. Algorithms for signed
and unsigned division are given in Tables 21 and 22. These use a nonrestoring
technique to divide a 16 N-bit integer dividend by an 8 N-bit integer divisor to produce
an 8 N-bit integer quotient and remainder, where N == 1 for quad 8-bit mode, N = 2
for dual 16-bit mode, and N = 4 for 32-bit mode.
Table 21. Signed Division Algorithm
OP
CODE

MNEMONIC

CLOCK

INPUT

CYCLES

SPORT

E4

LOADMQ

1

Dividend (LSH)

80

SDIVIN

1

Dividend (MSH)

1

Remainder (N)

AF
90

SDIVO
SDIVIS

1

INPUT
R PORT

Divisor
Divisor

OUTPUT
Y PORT
Dividend (LSH)

N

Remainder (N)

(It)

00
00

Overflow Test
Result

I-

«
¢

Remainder (N)

Divisor

Remainder (N)

AO

SDIVI

N-2t

Remainder (N)

Divisor

Remainder (N)

EO

,SDIVIT

1

Divisor

Remainder§

40

DIVRF

1

Remainder (N)
Remainder t

Divisor

Remainder'

50

SDIVQF

1

MQ register

Divisor

Quotient #

U

"en2

tN = 8 for quad 8-bit mode. 16 for dual 16-bit mode, 32 for 32-bit mode.
lThe least significant half of the product is in the MO register.
§Unfixed
, Fixed (corrected)
# The quotient is stored in the MO register. Remainder can be output at the Y port or stored in
the register file accumulator.

Table 22. Unsigned Division Algorithm
OP
CODE
E4

MNEMONIC
LOADMQ

CLOCK

INPUT

CYCLES

SPORT

1

Dividend (LSH)

INPUT
R PORT
-

OUTPUT
Y PORT
Dividend (LSH)

Dividend (MSH)

Divisor

Remainder (N)

N-1 t

Remainder (N)

Divisor

Remainder (N)

UDIVIT

1

Remainder (N)

Divisor

Remainder t

DIVRF

1

Remainder§

Divisor

Remainder§

BO

UDIVIS

CO

UDIVI

FO
40

1

tN = 8 in quad 8-bit mode, 16 in dual 16-bit mode, 32 in 32-bit mode
lUnfixed
§Fixed (corrected)

3-47

Data Conversion Instructions
Conversion of binary data to one's and two's complement can be implemented using
the INCNR instruction (Group 1). SMTC (Group 3) permits conversion from two's
complement representation to sign magnitude representation, or vice versa. Two's
complement numbers can be converted to their positive value, using ABS (Group 3).
SNORM and DNORM (Group 4) provide for normalization of signed, single- and doubleprecision data. The operand is placed in the MQ register and shifted toward the most
significant bit until the two most significant bits are of opposite value. Zeroes are shifted
into the least significant bit, provided SIO is high or floating. (A low on SIO will shift
a one into the least significant bit.) SNORM allows the number of shifts to be counted
and stored in one of the register files to provide the exponent.
C/)

2

......

Data stored in binary-coded decimal form can be converted to binary using BCD BIN
(Group 5). A routine for this conversion, given in Table 23, allows the user to convert
an N-digit BCD number to a 4N-bit binary number in 4N + 8 clock cycles .

~

l>

Table 23. BCD to Binary Algorithm

n

-I

(X)
(X)

W
N

OP

MNEMONIC

COOE

CLOCK

INPUT

INPUT

OUTPUT

CYCLES

SPORT

R PORT

DESTINATION

-

MQ reg:

E4

LOADMQ

1

BCD operand

D2

SUBR/MQSLC

1

Accumulator

Accumulator

Accumulator/MQ reg.

D2

SUBR/MQSLC

1

Mask reg.

Mask reg.

Mask reg/MQ reg.

D1

MQSLC
ADDI (15)

2

Don't care
Accumulator

Don't care

MQ reg.

Decimal 15

Mask reg.

Interim reg/MQ reg.

68

1

REPEAT N-1 TIMES t
DA

AND/MQSLC

1

MQ reg.

Mask reg.

D1

ADD/MQSLC

1

Accumulator

Interim reg.

Interim reg/MQ reg.

7F

8CDBIN

1

Interim reg.

Interim res.

Accumulator/MQ reg.

7F

BCDBIN

1

Accumulator

Interim reg.

Accumulator/MQ reg.

END REPEAT
FA
D1

I

AND
ADD MQSLC

1

MQ reg.

Mask reg.

Interim reg.

1

Accumulator

Interim reg.

Accumulator

tN = Number of BCD digits

BINEX3, EX3BC, and EX3C assist binary to excess-3 conversion. Using BINEX3, an
N-bit binary number can be converted to an N/4- digit excess-3 number. For an
algorithm, see Table 24.

3-48

Table 24. BCD to Binary Algorithm
OP
CODE

MNEMONIC

CLOCK

INPUT

INPUT

OUTPUT

CYCLES

SPORT

R PORT

DESTINATION

E4

LOADMQ

1

Binary numbe

-

D2

SUBR

1

Accumulator

Accumulator

Accumulator

D2

SET1 (33)16

1

Accumulator

Mask (33)16

Accumulator

MQ reg.

REPEAT N TIMESt
DF

BINEX3

1

Accumulator

Accumulator

Accumulator/MQ reg

9F

EX3C

1

Accumulator

Internal data

Accumulator

END REPEAT
tN

=

Number of bits in binary number

N

~

Bit and Byte Instructions
Four Group 3 instructions allow the user to test or set selected bits within a byte.
SET1 and SETO force selected bits of a selected byte (or bytes) to one and zero,
respectively. TBl and TBO test selected bits of a selected byte (or bytes) for ones
and zeros. The bits to be set or tested are specified by an a-bit mask formed by the
concatentation of register· file address inputs C3-CO and A3-AO. The register file
addressed by B5-BO is used as the destination operand for the set bit instructions.
Register writes are inhibited for test bit instructions. Bytes to be operated on are
selected by forcing SIOn low, wheren represents the byte position and 0 represents
the least significant byte. A high on the zero output pin signifies that the test data
matches the mask; a low on the zero output indicates that the test has failed.
Individual bytes of data can also be manipulated using eight Group 3 byte
arithmetic/logic instructions. Bytes can be added, subtracted, incremented, ORed,
ANDed and exclusive ORed. Like the bit instructions, bytes are selected by forcing
SIOn low, but multiple bytes can be operated on only if they are adjacent to one another;
at least one byte must be nonselected.

Other Instructions
SEL (Group 4) selects one of the ALU's two operands, S or R, depending on the state
of the SSF pin. This instruction could be used in sort routines to select the larger or
smaller of two operands by performing a subtraction and sending the status result
to SSF. CRC (Group 4) is designed to verify serial binary data that has been transmitted
over a channel using a cyclic redundancy check code. An algorithm using this instruction
is given in Table 25.

3-49

00

.....

U
~
"

:2

en

Table 25. CRC Algorithm
OP
CODE
E4
F6
F2

MNEMONIC
LOADMQ
INCR
SUBR

CLOCK
CYCLES

1
1
1

INPUT

OUTPUT

SPORT
Vector c'(x)t

INPUT

R PORT

DESTINATION

-

Polynomial g(x)

MQ reg.
Poly reg.

Accumulator

Accumulator

Accumulator

Accumulator
Vector c'(x) t

Poly reg.

-

REPEAT n/8N TIMES t

00
E4

CRC
LOADMQ

1
1

-

Accumulator
MQ reg.

END REPEAT

en

tN = Number of bits in binary number
n = Length of the code vector

2

:t
'-01

CLR forces the ALUoutput to zero and clears the internal BCD flip-flops used in excess-3
BCD operations. NOP forces the ALU output to zero, but does not affect the flip-flops.

n

-t Configuration Options

(X)
(X)

W
N

The' ACT8832 can be configured to operate in 8-bit, l6-bit, or 32-bit modes, depending
on the setting of the configuration mode selects (CF2-CFO). Table 11 shows the control
inputs for the' four operating modes. Selecting an operating configuration other than
32-bit mode affects ALU operation and status generation in several ways, depending
on the mode selected.

Masked 32-Bit Operation
Masked 32-bit operation is selected to reset to zero the 20 most significant bits of
the R Mux input. The 12 least significant bits are unaffected by the mask. Only Group
1 and Group 2 instructions can be used in this operating configuration. Status
generation is similar to unmasked 32-bit operating mode.

Shift Instructions
Shift instructions operate similarly in 8-bit, 16-bit, and 32-bit modes. The serial I/O
(SI03'-SI00') pins are used to select end-fill bits or to shift bits in or out, depending
on the operation being performed. Table 12 shows the SIO signals associated with
each byte or word in the different modes, and Table 17 indicates the specific function
performed by the SIO pins during shift, multiply, and divide operations.
Figures 9 and 10 present examples of logical right shifts in 16-bit and 8-bit
configurations.

3-50

SERIAL DATA
INPUT SIGNALS

SIOO~--------------------~--------,

Single Precision Logical Right Single Shift, 16-Bit Configuration
SERIAL DATA
INPUT SIGNALS
SIOO~--------~-------------------,

Double Precision Logical Right Single Shift, 16-Bit Configuration

Figure 9. Shift Examples. 16-Bit Configuration

Bit and Byte Instructions
The' ACT8832 performs bit operations similarly in 8-bit, 16-bit, and 32-bit modes.
Masks are loaded into the R MUX on the A3-AO and C3-CO address inputs, and the
bytes to be masked are selected by pulling their 510' inputs low. Instructions which
set, reset, or test bits are explained later
Byte operations should be performed in 32-bit mode to get the necessary status
outputs. While byte overflow signals are provided for all four bytes (BYOF3-BYOFOI,
the other status signals (C, N, Z) are output only for the word selected with the
configuration control signals (CF2-CFO).

Status Selection
Status results (C, N, Z. and overflow) are internally generated for all words in all modes.
but only the overflow results (BYOF3-BYOFO) a"re available for all four bytes in 8-bit
mode or for both words in 16-bit mode. If a specific application requires that the four
status results are read for two or four words, it is possible to toggle the configuration

3-51

SERIAL DATA
INPUT SIGNALS
SIOO~.~----------------------------------------------~

Siij1~------------~------------------,
~~----------------.

,...---.rnr-----,

Single-Precision Logical Right Shift. 8-81t Configuration

SERIAL DATA
INPUT SIGNALS
SIOO~----------------------------------------------~

Siij1~.~~-----------------------------,
~~----------------~

Double-Precision Logical Right Shift. 8-8it Configuration

Figure 10. Shift Examples, 8-Bit Configuration
con~rol

signals (CF2-CFO) within the same clock cycle and read the additional status
results. This assumes that the necessary external hardware is provided to toggle
CF2-CFO and collect the status for the individual words before the next clock signal
is input.

Instruction Set
The' ACT8832 instruction set is presented in alphabetical order on the following pages.
The discussion of each instruction includes a functional description, list of possible
operands, data flow diagram, and notes on status and control bits affected by the
instruction. Microcoded examples are also shown.
Mnemonics and opcodes for instructions are given at the top of each page. Opcodes
for instructions in Groups 1 and 2 are four bits long and are combined into eight"bit
instructions which select combinations of arithmetic, logical, and shift operations.
Opcodes for the other instruction groups are all eight bits long.
.
An asterisk in the left side of the opcode box for a Group 1 instruction indicates that
a Group 2 opcode is needed to complete the instruction. An asterisk in the right side
of a box indicates that a Group 1 opcode is required to combine with the Group 2
opcode in the left side of the box.

ABS

Absolute Value

I4 I8 I

FUNCTION
Computes the absolute value of two's complement data on the S bus.

DESCRIPTION
Two's complement data on the S bus is converted to its absolute value. The carry
must be set to one by the user for proper conversion. ABS causes S' + Cn to be
computed; the state of the sign bit determines whether S or S' + Cn will be selected
as the result. SSF is used to transmit the sign of S.
Available R Bus Source Operands

C3-CO
A3-AO
RF
(A5-AO) Immed

DA-Port

..
A3-AO

Mask
No

No

No

No

Available S Bus Source Operands

RF
MQ
DB-Port
(B5-BO)
Register
Yes

Yes

Yes

Available Destination Operands

RF
RF
(C5-CO) (B5-BO)
Yes

No

Shift Operations

Y-Port

ALU

MQ

Yes

None

None

Control/Data Signals

Signal

User
Programmable

Use
Inactive

SSF

No

5100

No

Inactive

5101

No

Inactive
Inactive

5102

No

Si03

No

Cn

Yes

Inactive
. Should be programmed high for proper conversion.

3-53

1418

Absolute Value

ASS

Status Signals
if result = 0

ZERO

N
OVR

1 if MSB (input) = 1
1 if input of most significant byte is 80 (Hex) and inputs (if any) in all
other bytes are 00 (Hex).

C=1ifS=0

EXAMPLES (assumes a 32-bit configuration)
Convert the two's complement number in register 1 to its positive value and store
the result in register 4.
(f)

2

"
»
o
~

Instr
Code
17-10

Oprd
Addr
A5-AO

Oprd
Addr
B5-6O

01001000

XX XXXX

00 0001

Oprd Sel
EB1EA EBO
X

00

Dest
Addr
C5-CO

SELMO

000100

0

Destination Selects;

WE3-

SELRF1-

WED
0000

SELRFO
10

0Ev3
i5EA
X

OEB
X

~ Example 1: Assume register file 1 holds F6D81340 (Hex):

00

Source

11110110110110000001001101000000

I

S - RF(1)

Destination

00001001 00100111 11101100 11000000

I

RF(4) - S

~

Example 2: Assume register file 1 holds 09D527CO (Hex):
Source

00001001 1101 0101 00100111 11000000

I

S - RF( 1)

Destination

00001001 1101 0101 00100111 11000000

I

RF(4) - S

3-54

+

Cn

0eY0 DES
xxxx

0

Cn

CF2CFO

1

110

ADD

Add with Carry (R + S + Cn)

*

I

1

FUNCTION
Adds data on the Rand S buses to the carry-in.

DESCRIPTION
Data on the Rand S buses is added with carry. The sum appears at the ALU and MQ
shifters.
"The result of this instruction can be shifted in the same microcycle by specifying a shift instruction in the
upper nibble {I7·14} of the instruction field. The result may also be passed without shift. Possible instructions
are listed in Table 15.

Available R Bus Source Operands

N

C3-CO
RF

A3-AO

(A5-AO) Immed

DA-Port

('I')

00
.00

..

....
(.)

A3-AO
Mask

Ves

No

Ves



W
N

1 if result = 0
1 if MSB = 1
1 if signed arithmetic overflow
if carry-out = 1

t C is ALU carry out arid is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR (overflow) is evaluated after ALU operation and after shift operation.

EXAMPLES (assumes a 32-bit configuration)
Add data in register 1 to data on the DB bus with carry-in and pass the result to the
MQ register.
Op,d
Add,

Instr

Code
17·10
1110 eOOl

A5·AO
000001

Op,d
Add,

Op,d Sel
Oest
Destination Selects
E81·
Add,'
WE3· SELRF1·
SELMQ WEO SELRFO OEA 0eB OEYO
.85·80
EAEao
C5·CO
XX XXX X
0
1111
10
X
X
XXX X
0 10 XX XXXX

om·

0eS
0

CF2·
Cn CFO
0
110

.Assume register file 1 holds 0802C618 (Hex and DB bus holds. 1E007530 (Hex):
Source

00001000000000101100011000011000

I R-

RF(l)

Source

0001 1110000000000111 0101 0011 0000

I S-

DB bus

Destination

0010011000000011 0011 1011 0100 1000

I MQ register -

3-56

R + S + Cn

ADDI

I

ADD Immediate

6

I

8

I

FUNCTION
Adds four-bit immediate data on A3-AO with carry to S-bus data.

DESCRIPTION
Immediate data in the range 0 to 15, supplied by the user at A3-AO, is added with
carry to S.
Available R Bus Source Operands (Constant)
C3-CO
RF

A3-AO

..

DA-Port

(A5-AO) Immed

N
M

Mask
No

Yes

No

No

ex)
ex)

IU

Available S Bus Source Operands

«
~

RF
MQ
DB-Port
(85-80)
Register
Yes

Yes

Z

(IJ

Yes

Available Destination Operands
RF
RF
(C5-CO) (85-BO)
Yes

I'

No

Shift Operations

Y-Port

ALU

MQ

Yes

None

None

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

Inactive

SIOO

No

Inactive

SiOT

No

Inactive

SI02

No

Inactive

SI03

No

Inactive

Cn

Yes

Increments· sum if set to one.

3-57

I6 I8 I

ADD Immediate

ADDI

Status Signals
ZERO

N
OVR
C

1 if result = 0
1 if MSB = 1

1 if signed arithmetic overflow
1 if carry-out = 1

EXAMPLES (assumes a 32-bit configuration)
Add the valule 12 to data on the DB bus with carry-in and store the result in register
file 1.

en

2:
....,

Instr
Code
17-10
01101000

Oprd
Addr
A5-AO
00 1100

Oprd
Addr
B5-BO
XX XXXlC

Cest
Oprd Sel
EB1Addr
EA EBO C5-CO
X 10 00 0001

Destination Selects
SELRF1SELMa
SELRFO 0eA DeB 0EY0
0
0000
10
X
X
XXXX

om

W5WeO

~

l>
-t

n

Assume bits A5-AO hold OC (Hex) and DB bus holds 24000100 (Hex):
Source

000000000000 0000 0000 0000 0000 1100

I R-

A5-AO

Source

001001000000000000000001 00000000

I5-

DB bus

Destination

00100100000000000000,000100001100

I RF(1) -

00
00
tAo)

N

3-58

R +5 + Cn

0Es
0

CF2Cn CFO
110
0

AND

Logical AND (R AND S)

FUNCTION
Evaluates the logical expression RAND S.

DESCRIPTION
Data on the R bus is ANDed with data on the S bus. The result appears at the ALU
and MQ shifters.
'The result of this instruction can be shifted in the same microcycle by specifying a shift instruction in the
upper nibble (17-14) of the instruction field. The result may also be passed without shift. Possible instructions
are listed in Table 15.

Available R Bus Source Operands
C3-CO
A3-AO
RF
(A5-AO) Immed

DA-Port

..
A3-AO
Mask

Yes

No

Yes

No

Available S Bus Source Operands
RF
MQ
DB-Port
(B5-BO)
Register
Yes

Yes

Yes

Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Yes

No

Shift Operations

Y-Port

ALU

MQ

Yes

Yes

Yes

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

Affect shift instructions programmed in bits 17-14 of

SIOO

No

Inactive

SI01

No

Inactive

5102

No

Inactive

SI03

No

Inactive

Cn

No

Inactive

instruction field.

3-59

I * IA I

Logical AND (R AND S)

AND

Status Signals t
ZERO

N
OVR
C

1 if result = 0
1 if MSB = 1

o
o

t C is ALU carry out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR (overflow) is evaluated after ALU operation and after shift operation.

EXAMPLES (assumes a 32-bit configuration)
Logically AND the contents of register 3 and register 5 and store the result
in register 5.
Cf)

2

-.oJ
~

:t>

(")

Instr
Code
17-10
11111010

Oprd
Addr
AS-AO·
000011

Oprd
Addr
BS-8O
000101

Dest
Oprd Sel
EB1Addr
CS-CO
EAEBO
0 00
000101

Destination Selects
WE3- SELRF1SELMO WEO SELRFO 0eA
0
0000
10
X
X

ore

0eY3
0eY0 l5Es
XXX X

0

CF2Cn CFO
X 110

-4

~

Assume register file 3 holds F617D840 (Hex) and register file 5 holds 15F6D842 (Hex):

W
N

Source

1111 01100001 0111 1101 100001000000

I

Source

0001 0101 1111 01101101 1000 0100 0010

I S-

Destination

0001 01000001 01101101 100001000000

I

3-60

R - RF(3)

RF(5)

RF(5) - RAND S

Logic AND Negative R (R' AND S)

ANDNR

*

I

E

FUNCTION
Computes the logical expression S AND NOT R.

DESCRIPTION
The logical expression S AND NOT R is computed. The result appears at the ALU and
MQ shifters.
"The result of this instruction can be shifted in the same microcycle by specifying a shift instruction in the
upper nibblf;t (/7-14) of the instruction field. The result may also be passed without shift. Possible instructions
are listed in Table 15.

Available R Bus Source Operands
C3-CO
A3-AO
RF
(A5-AO) Immed

DA-Port

..
A3-AO
Mask

Yes

Yes

No

No

Available S Bus Source Operands
MQ
RF
DB-Port
(B5-BO)
Register
Yes

Yes

Yes

Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Yes

No

Shift Operations

Y-Port

ALU

MQ

Yes

Yes

Yes

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

Affect shift instructions programmed in bits 17-14 of

SIOO

No

Inactive

instruction field.
SI01

No

Inactive

SI02

No

Inactive

SI03

No

Inactive

Cn

No

Inactive

3-61

Logic AND Negative R (R' AND S)

ANDNR

Status Signals t
ZERO

= 1 if result =0

N = 0
I

OVR

0

C

0

t C is ALU carry out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR (overflow) is evaluated after ALU operation and after shift operation.

EXAMPLE (assumes a 32-bit configuration)
Invert the contents of register 3, logically AND the result with data in register 5
and store the result in register 10.
fJ)

2
....,
~

l>
(")
-t

Instr

Code
17-10
11111110

Oprd
Addr
A5-AO
000011

Oprd
Addr
B5-BO
000101

Oprd Sel
Dest
Destination Selects
EB1Addr
WE3- SELRF1C5-CO
EAEBO
SELMO WEb SELRFO 0eA 0eB
001010
10
X
0 00
0
0000
X

orn-

CWo DeS

XXX X

0

CF2Cn CFO
X 110

CO
CO Assume register file 3 holds 15F6D840 (Hex) and register file 5 hold F617D842 (Hex):
W
N
Source

0001 0101 1111 01101101 100001000000

I R-

RF(3)

Source

11110110000101111101100001000010

I S-

RF(5)

Destination

1110001000000001 00000000 0000 0010

I RF( 10) -

3-62

RAND S

BADD

Byte Add R to S with Carry

I8 I8 I

FUNCTION
Adds S with carry-in to a selected byte or selected adjacent bytes of R.

DESCRIPTION
S103-S100 are used to select bytes of R to be added to the corresponding bytes of
S. A byte of R with SIO programmed low is selected for the computation of
R + S + en. If the SIO signal for a byte of R is left high, the corresponding byte
of S is passed unaltered. Multiple bytes can be selected only if they are adjacent to
one another. At least one byte must be nonselected.
Available R Bus Source Operands

N
M
CO
CO

C3-CO
RF
A3-AO
(A5-AO) Immed

DA-Port

..
A3-AO

IU

Mask
Yes

No

Yes

oCt

No

'd'

"Z

Available S Bus Source Operands

en

RF
MQ
DB-Port
(B5-BO)
Register
Yes

Yes

Yes

Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Yes

No

Shift Operations

Y-Port

ALU

MQ

Yes

None

None

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

SIOO

Yes

Inactive
Byte select

5101

Yes

Byte select

5102

Yes

Byte select

5103

Yes

Byte select

Cn

Yes

Propagates through nonselected bytes; increments
selected byte(s) if programmed high.

3-63

I8 I8

BADD

Byte Add R to S with Carry

Status Signals
1 if result (selected bytes) = 0

ZERO

o

N

if signed arithmetic overflow (selected bytes)

OVR

C

if carry-out (most significant selected byte) = 1

EXAMPLE (assumes a 32-bit configuration)
Add bytes 1 and 2 of register 3 with carry to the contents of register 1 and store the
result in register 11.
Instr

Oprd

Oprd

Oprd Sel

Dest

en

Code

Addr

Addr

EB1-

Addr

17·10

AS-AD

B5-BO

......

01001000

000011

000001

z

~

»

EAEeo
0

00

Destination Selects

C5-CO

SELMQ

WE3.
WEO

001011

0

0000

SELRF1·
10

SELRFO

OEY3-

CF2-

OEA 0Eii 0EY0 0Es
X

X XXXX

0

Cn CFO
1

SiOO· IEsi03·
SiOo IESiOO

110 1001

0000

Assume register file 3 holds 2CO 18181 (Hex) and register file 1 holds 7 A8FBE3E (Hex):

(")

~

Source

0010110000000001 10000001 10000001

I Rn

+-

RF(3)n

00
CAl
N

Source

01111010100011111011111000111110

I Sn

+-

RF(1)n

ALU

101001101001 0001 01000000 11000000

I Fn

+-

Rn

Destination

01111010100100010100111100111110

I

tF

= ALU result
n = nth byte
Register file 11 gets F if byte selected, S if byte not selected.

3-64

RF(11)n

+ Sn + Cn
+-

Fn or Sn t

Byte AND RAND S (Byte Logical ANDR AND S)

BAND

I

E

I

8

I

FUNCTION
Evaluates the logical AND of selected bytes of R-bus and 5-bus data.

DESCRIPTION
Bytes with their corresponding 510 signals programmed low compute RAND 5. Bytes
with 510 Signals programmed high, pass 5 unaltered. Multiple bytes can be selected
only jf they are adjacent to one another. At least one byte must be nonselected.
Available R Bus Source Operands
C3-CO
RF
A3-AO
(A5-AO) Immed
Ves

DA-Port

No

Ves

..
A3-AO
Mask
No

Available S Bus Source Operands
RF
MQ
DB-Port
(B5-BO)
Register
Ves

Ves

Ves

Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Ves

No

Shift Operations

V-Port

ALU

MQ

Ves

None

None

Control/Data Signals
Signal
SSF
§iOO

SiOT
ID02
Si03
Cn

User
Programmable

Use

No

Forced low

Ves
Ves

Byte select
Byte select

Ves
Ves

Byte select

No

Inactive

Byte select

IE 18 I

Byte AND RAND S (Byte Logical AND RAND S)

BAND

Status Signals
ZERO
N
OVR

C

1 if result (selected bytes) = 0

o
o
o

EXAMPLE (assumes a 32-bit configuration)
Logically AND bytes 1 and 2 of register 3 with input on the DB bus; store the result
in register 3.

en

:2

"
»
~

~

Instr

Op,d

Op,d

Op,d .Sel

Dest

Code

Add,

Add,

EB1-

Add,

17-10

A5-AO

B5-BO

11101000 000011

XX XXXX

EA EBO
0

10

Destination Selects

WE3-

SELRF1-

C5-CO

SELMa

WEo

SELRFO

000011

0

0000

10

om-

CF2-

0eA 0Es 0EY0 5ES
X

X

XXXX

Cn CFO

0

X

Si(53: 1'Esi03-

SiOO IESiOO

110 1001

0000

Assume register file 3 holds 398FBEBE (Hex) and input on the DB port is 4290BFBF
(Hex):

(X)
(X)

Source

001110011000·11111011111010111110

I Rn

Source

01000010100100001011111110111111

Sn

Destination

010000101000 0000 1011 11101011 1111

RF(3)n

W
N.

t F = ALU result

n = nth byte
Register file 3 gets F if byte selected, S if byte not selected.

3-66

4-

RF(3)n

4-

DBn

4-

Fn or Sn t

BCDBIN

BCD to Binary

I7I

F

FUNCTION
Converts a BCD number to binary.

DESCRIPTION
This instruction allows the user to convert an N-digit BCD number to a 4N-bit binary
number in 4(N-1) plus 8 clocks. The instruction sums the Rand 5 buses with carry.
A one-bit arithmetic left shift is performed on the ALU output. A zero is filled into bit 0
of the least significant byte unless 5100 is set low, which would force bit 0 to one.
Bit 7 of the most significant byte is dropped.
Simultaneously, the contents of the MQ register are rotated one bit to the left, Bit
7 of the most significant byte is rotated to bit 0 of the least significant byte.
Recommended R Bus Source Operands
C3-CO
RF

A3-AO

(A5-AO) Immed

DA-Port

..
A3-AO
Mask

Yes

No

No

No

Recommended S Bus Source Operands
RF
MQ
DB-Port
(85-BO)
Register
Yes

Yes

No

Recommended Destination Operands
RF

RF

(C5-CO) (B5-BO)
Yes

No

Shift Operations

Y-Port

ALU

MQ

No

Left

Left

3-67

I7 IF

BCDBIN

BCD to Binary

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

Inactive

IDC50

Yes

If high or floating, fills a zero in LSB of ALU shifter;

SiOT

No

Inactive in 32-bit configuration. Used in other

5102

No

configurations to select endfill in LSBs.

if low, fills a one in LSB of ALU shifter.

en
2

SI03

No

Cn

Yes

Should be programmed low for proper conversion.

Status Signals

".J::o
»

ZERO

(')

OVR

-f

C

N

1 if result = 0
1 if MSB =1

1 if signed arithmetic overflow
1 if carry-out = 1

CO
CO
W ALGORITHM
N

The following code converts an N-digit BCD number to a 4N-bit binary number in 4(N-1 )
plus 8 clocks. It employs the standard conversion formula for a BCD number (shown
here for 32 bits):
ABCD

= [(A

X

10

+ B)

X

10

+ C)

X

10

+ D.

The conversion begins with the most significant BCD digit. Addition is performed in
radix 2.

3-68

LOADMO NUM

Load MO with BCD number.

SUB ACC, ACC, SLCMO

Clear accumulator;
Circular left shift MO.

SUB MSK, MSK, SLCMO

Clear mask register;
Circular left shift MO.

SLCMO

Circular left shift MO.

SLCMO

Circular left shift MO.

ADDIACC,MSK,15

Store 1 5 in mask register.

BCDBIN

BCD to Binary

I7IFI

Repeat N-1 times:
(N = number of BCD digits)
AND MO, MSK, R1, SLCMO

Extract one digit;
Circular left shift MO.

ADD, ACC, R1, R1, SLCMO

Add extracted digit to accumulator, and
store result in R1; Circular left shift MO.

BCDBIN R1, R1, ACC

Perform BCDBIN instruction, and store
result in accumulator
[4 x (ACC + 4 x digit)];
Circular left shift MO.

BCDBIN ACC, R1, ACC

Perform BCD BIN instruction, and store
result in accumulator
[10 x (ACC + 10 x digit)];
Circular left shift MO.

N
M
00
00

....U



..
A3·AO

No

No

No

No

()

-t

CO
CO

'W
N

Available S Bus Source Operands
RF
MQ
DB·Port
(B5·BO)
Register
Yes

Yes

Yes

Available Destination Operands
RF

RF

(C5·CO) (B5·BO)
Yes

No

Shift Operations

Y·Port

ALU

MQ

Yes

None

None

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

Inactive

SIOO

Yes

Byte select

SiOT

Yes

Byte select

SI02

Yes

Byte select

SI03

Yes

Byte select

Cn

Yes

Propagates through nonselected bytes; increments
selected byte(s) if programmed high.

3·70

BINCNS

IcI8 I

Byte Increment Negative S with Carry

Status Signals
ZERO
N

1 if result (selected bytes) = 0

o

OVR
C

if signed arithmetic overflow (selected bytes)
if carry-out (most significant selected byte)

EXAMPLE (assumes a 32-bit configuration)
Invert bytes 0 and 1 of register 3 and add them to the carry (bytes 2 and 3 are not
changed). Store the result in register 3.
Instr

Op,d

Op,d

Op,d Sel

Dest

Code

Add,

Add,

E61-

Add,

17-10

A5-AO

65-60

EAEBO

C5-CO

000001

X 00

000011

1100 1000 XX XXXX

Destination Selects

WEJ-

SELRF1-

SELMa

WEo

SELRFO

0

0000

10

om-

CF2-

OEA 0Es 5EYo 5Es
X

X

XXXX

0

Cn CFO
1

Sili3- iESi5'3SiOo IESIOO

110 1100

0000

Assume register file 3 holds A3018181 (Hex):
Source

10100011 00000001 10000001 10000001

Sn'" RF(3)n

ALU

01011100111111100111111001111111

Fn ... S'n

Destination

10100011 0000 0001 0111 11100111 1111

RF(3)n ... Fn or Sn t

+ Cn

tF = ALU result
n = nth byte
Register file 3 gets F if byte selected, S if byte not selected_

3-71

IBla

Byte Increment S with Carry

BINCS

FUNCTION
Increments selected bytes of S if the carry is set.'

DESCRIPTION
Bytes with SIO' inputs programmed low compute S + Cn. Bytes with SIO inputs
programmed high, pass S unaltered. Multiple bytes can be selected only if they are
adjacent to one another. At least one byte must be nonsselected.
Available R Bus Source Operands
C3-CO

o

2
.....

~

»
(")
-t

CO
CO
W
N

RF
A3-AO
(A5-AO) Immed
No

DA-Port

No

No

..
A3-AO
Mask
No

Available S Bus Source Operands
RF
MQ
DB-Port
(B5-BO)
Register
Ves
Ves
Ves
Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Ves

No

Shift Operations

V-Port

ALU

MQ

Ves

None

None

Control/Data Signals
Signal
SSF

SiOO
SiOf
5102
SI03
Cn

User
Programmable
No
Ves
Ves
Ves
Ves
Ves

Use
Inactive
Byte select
Byte select
Byte select
Byte select
Propagates through nonselected bytes; increments
selected byte!s) if programmed high.

IBI8 I

Byte Increment S with Carry

BINCS
Status Signals
ZERO

N

1 if result (selected bytes) = 0

o
if signed arithmetic overflow (selected bytes)

OVR

if carry-out (most significant selected byte)

C

EXAMPLE (assumes a 32-bit configuration)
Add bytes 1 and 2 of register 7 to the carry (bytes 0 and 3 are not changed). Store
the result in register 2.
Instr

Op,d

Oprd

Op,d Sal

Dest

Code

Add,

Add,

EB1-

Add,

17-10

A5-AO

B5-BO

1011 1000 XX XXXX

000111

EA EBO
X

00

Destination Selects

C5-CO

SELMQ

WE3WEo

000010

0

0000

SELRF1SELRFO

OEA

OEe

10

X

X

om-

CF2-

0EY0 0Es

XXXX

Cn CFO

0

Assume register file 7 holds 408FBEBE (Hex):
Source

01000000100011111011111010111110

I Sn -

RF(7)n

ALU

01000000100011111011111110111110

I Fn -

Sn

Destination

0100000010001111 1011 1111 1011 1110

I RF(2)n -

tF = ALU result
n = nth byte
Register file 11 gets F if byte selected, S if byte not selected.

+

Cn

Fn or Sn t

1

Sili3- iEsi'1i3SiOo iESiOo

110 1100

0000

lolF

Binary to Excess·3

BINEX3

FUNCTION
Converts a binary number to excess·3 representation.

DESCRIPTION
This instruction converts an N-digit binary number to a N/4 digit excess-3 number
representation in 2N + 3 clocks. The data on the Rand S buses are added to the carryin. which contains the most significant bit of the MQ register. The contents of the
MQ register are rotated one bit to the left. The most significant bit is shifted out and
passed to the least significant bit position. Depending on the configuration selected.
this shift may be within the same byte or from the most significant byte to the least
significant byte.
.
tJ)

2

Recommended R Bus Source Operands

.....

~
(')
-t

00
00
Co\)

C~-CO

RF
A~-AO
(A5-AO) Immed
Ves

DA-Port

No

No

..
A3-AO
Mask
No

N
Recommended S Bus Source Operands
MQ
RF
DB-Port
(B5-BO)
Register
Ves
Ves
No
Recommended Destination Operands
RF
RF
(C5-CO) (B5-BO)
Ves

No

Shift Operations

V-Port

ALU

MQ

Ves

None

Left

Control/Dilta Signals
Signal
SSF

SiOO
~

Si02

Si03
Cn

3-74

User
Programmable
No
No
No
No
No
No

Use
Inactive
Inactive
Inactive
Inactive
Inactive
Holds MSB of MQ register.

BINEX3

Binary to Excess·3

I0I

F

I

Status Signals
ZERO

1 if result = 0

N
OVR
C

1 if MSB = 1
1 if signed arithmetic overflow
1 if carry-out = 1

ALGORITHM
The following code converts an N-digit binary number to a N/4 digit excess-3 number
in 2N + 3 clocks. It employs the standard conversion formula for a binary number:
an 2 n

+ an-1 2n-1 + an_2 2n- 2 + . .. + ao =
([(2an

~

+ an-1) x 2 + an-1] x 2+ . , . + ao} x 2 + aO •

The conversion begins with the most significant bit. Acldition during the BINEX3
instruction is performed in radix 10 (excess-3).
LOADMO NUM

Load MO with binary number.

SUB ACC, ACC, ACC

Clear accumulator;

SET1 ACC, 33 (Hex)

Store 33 (H~~) in all bytes of
accumulator.

CO
CO

I-

~

'I:t

roZ

en

Repeat N times:
(N = number of bits in binary number)
BINEX3 ACC, ACC, ACC

Double accumula~or and add in most
significant bit of MO register. Circular left
shift MO.

EX3C ACe

Perform excess-3 correction.

(END REPEAT)

3-75

Byte OR Rand S
(Byte Inclusive OR Rand S)

IF I8

BOR

FUNCTION
Evaluates R OR S of selected bytes.

DESCRIPTION
Bytes with SIO inputs programmed low evaluate R OR S. Bytes with SIO inputs
programmed high, pass S unaltered. Multiple bytes can be selected only if they are
adjacent to one another. At least one byte must benonselected.
Available R Bus Source Operands
C3-CO
C/)

Z

.....
l>

~

RF
A3-AO
(A5-AO) Immed

DA-Port

..
A3-AO
Mask

Ves

No

Ves

No

(")

-4

00
00

Co\)

N

Available S Bus Source Operands
MQ
RF
DB-Port
(B5-BO)
Register
Ves

Ves

Ves

Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Ves

No

Shift Operations

V-Port

ALU

MQ

Ves

None

None

ContrOl/Data Signals
Signal

User

Use

Programmable

SSF

No

Inactive

SIOO

Ves

Byte select

SI01

Ves

Byte select

SI02

Ves

Byte select

~

Ves

Byte select

Cn

No

Inactive

3-76

Byte OR Rand S
(Byte Inclusive OR Rand S)

BOR

IFI8I

Status Signals
ZERO

N
OVR

C

1 if result (selected bytes) = 0

o
o
o

EXAMPLE (assumes a 32-bit configuration)
Logically OR bytes 1 and 2 of register 12 with bytes 1 and 2 on the DB bus. Concatenate
with DB bytes 0 and 3, storing the result in register 12.
Instr

Oprd

Oprd

Oprd Sel

Dest

Code

Addr

Addr

EB1-

Addr

17-10

A5-AO

85-BO

EA E80

1111 1000 001100

XX XXXX

0

10

Destination Selects

C5-CO

SELMO

We3WEo

001100

0

0000

SELRF l10

SELRFO

orn-

CF2-

0eA Oeii 0EY0 OES
X

X

XXXX

0

Cn CFO

X

110

SiOO- IEs'i03- N
SIoO IESiOO M
1001 0000
CO
CO

Assume register file 12 holds 578FBEBE (Hex) and the DB bus holds 1C90BEBE (Hex):
Source

I

01010111100011111011111010111110

I Rn

+-

Source

I

0001 1100 1001 0000 1011 11101011 1100

I Sn

+-

Destination

I

0001 11001001 1111 1011 11101011 1110

I RF(12)n

~

(.)

~

RF(12)n

I'

Z

en

DBn

+-

Fn or Sn t

t F = ALU result
n = nth package
Register file 12 gets F if byte selected, S if byte not selected_

3-77

IA I8

Byte Subtract R from S with Carry

BSUBR

FUNCTION
Subtracts R from S in selected bytes.

DESCRIPTION
Bytes with SIO inputs programmed low compute R' + S +Cn. Bytes with SIO inputs
programmed high, pass S unaltered. Multiple bytes can be selected only if they are
adjacent to one another. At .least one byte must be nonselected.
Available R Bus Source Operands
C3-CO
CJ)

RF
A3-AO
(A5-AO) Immed

DA-Port

Z

"""
~

»
(")

..
A3-AO
Mask

Yes

No

Yes

No

-I Available S Bus Source Operands

00
00

W
N

MQ
RF
DB-Port
(85-80)
Register
Yes

Yes

Yes

Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Yes

No

Shift Operations

Y-Port

ALU

MQ

Yes

None

None

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

Inactive

SIOO

Yes

Byte select

"SiOf

Yes

Byte select

Si02

Yes

Byte select

5103

Yes

Byte select

Cn

Yes

Propagates through nonselected bytes; should be
set high for two's complement subtraction.

3-78

BSUBR

IAI8 I

Byte. Subtract R from S with Carry

Status Signals
1 if result (selected bytes) = 0

ZERO

o

N

if signed arithmetic overflow (selected bytes)

OVR

C

if carry-out (most significant selected byte)

EXAMPLE (assumes a 32-bit configuration)
Subtract bytes 1 and 2 of register 1 with carry from bytes 1 and 2 of register 3.
Concatenate with bytes 0 and 3 of register 3, storing the result in register 11.
Instr

Op.d

Op.d

Op.d Sel

Dest

Code

Add.

Add.

EB1-

Add.

17-10

AS-AO

BS-BO

10101000

000001

000011

EA EBO
0

00

Destination Selects

WE3-

SELRF1-

CS-CO

SELMQ

WEo

SELRFO

001011

0

0000

10

om-

CF2-

OEA 0Eii 0EY0 0Es
X

X

XXXX

0

Cn CFO
1

'Si03- iESiOOSiOo' IESIOO

110 1001

N

(Y)

0000

CO
CO
Assume register file 1 holds 09185858 (Hex) and register file 3 holds 703A9898 (Hex): ISource

000010010001 10110101 10000101 1000

I Rn

U

+-

RF(1)n

Source

01110000001110101001100010011000

I Sn

ALU

01100111 0001 1111 0100000001000000

I Fn

Destination

0111 00000001 1111 01000000 1001 1000

I RF( 11)n

t F = ALU result
n = nth package
Register file 11 gets F if byte selected. S if byte not selected.

~

......
Z
+-

RF(3)n

+-

R'n

+ Sn + Cn

+-

Fn or Sn t

CJ)

I9 I8

Byte Subtract S from R with Carry

BSUBS

FUNCTION
Subtracts S from R in selected bytes.

DESCRIPTION
Bytes with SIO inputs programmed low compute R + S' + Cn. Bytes with SIO inputs
programmed high, pass S unaltered. Multiple bytes can be selected only if they are
adjacent to one another. At least one byte must be nonselected.
Available R Bus Source Operands
C3-CO
RF

A3-AO

DA-Port

(A5-AO) Immed

Mask

(J)

:2

..
A3-AO

Yes

No

Yes

No

'-01
~

l>

Available S Bus Source Operands

(")

-t

RF

ex)
ex)

(B5-BO)

W
N

Yes

DB-Port
I

MO
Register
Yes

Yes

Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Yes

No

Shift Operations

Y-Port

ALU

MO

Yes

None

None

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

Inactive

5100

Yes

Byte select

SiOf

Yes

Byte select

8102

Yes

Byte select

5103

Yes

Byte select

en

Yes

Propagates through nonselected bytes; should be
set high for two's complement subtraction.

I9I8I

Byte Subtract S from R with Carry

BSUBS
Status Signals
ZERO

N

1 if result (selected bytes) = 0

o
if signed arithmetic overflow (selected bytes)

OVR

if carry-out (most significant selected byte)

C

EXAMPLE (assumes a 32-bit configuration)
Subtract bytes 1 and 2 of register 3 with carry from bytes 1 and 2 of register 1.
Concatenate with bytes 0 and 3 of register 3, storing the result in register 11.
Instr

Oprd

Op.d

Op.d Sel

Dest

Code

Add.

Add.

EBI-

Add.

17-10

A5-AO

85-80

Eli" EBO

C5-CO

000011

0 00

00 1011

1001 1000 000001

Destination Selects

WE3-

SELRF1-

SELMa

WED

SELRFO

0

0000

10

om-

CF2-

OEA 0Eii 0eY0 DEs
X

X

XXXX

0

Cn CFO
1

Sr03- iEsi'03SiOo iESiOO

110 1001

0000

N

('I)

Assume register file 1 holds 52888888 (Hex) and register file 3 holds 143A9898 (Hex): CO
CO
Source

01010010100010001011100010111000

Source

0001 01000011 10101001 1000 1001 1000

I Rn
I Sn

+-

~

RF(1)n

U



(')

-t

CO
CO
W
N

Available S Bus Source Operands
MQ
RF
DB-Port
(B5-BO)
Register
Yes

Yes

Yes

Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Yes

No

Shift Operations

Y-Port

ALU

MQ

Yes

None

None

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

SIOO

Yes

Byte select

SiOT

Yes

Byte select

5102

Yes

Byte select

5103

Yes

Byte select

Cn

No

Inactive

3-82

Inactive

Byte XOR Rand S
(Byte Exclusive OR Rand S)

BXOR

I0 I8 I

Status Signals
ZEAO

N
OVA
C

1 if result (selected bytes) = 0

o
o
o

EXAMPLE (assumes a 32-bit configuration)
Exclusive OR bytes 1 and 2 of register 6 with bytes 1 and 2 on the DB bus; concatenate
the result with DB bytes 0 and 3, storing the result in register 10.
Instr

Oprd

Oprd

Oprd Sel

Dest

Code

Addr

Addr

EB1-

Addr

17-10

A5-AO

B5-BO

1101 1000 000110

XX

xxx x

EA EBO
0

10

Destination Selects

WE-

SELRF1-

C5-CO

SELMa

WEci

SELRFO

001010

0

0000

10

om-

CF2-

OEA 0eB 0eY0 0Es
X

X

XXXX

0

Cn CFO
1

Si03- iESi'03SiOO iESiOO

110 1001

0000

Assume register file 6 holds 938FBEBE (Hex) and the DB bus holds 4190BEBE (Hex):
Source

1001 0011 1000 1111 1011 1110 10111110

I An -

Source

01000001 1001 0000 1011 1110 1011 1110

I

Destination

01000001 0001 1111 00000000 1011 1110

I AF(' O)n

AF(6)n

Sn - DBn

+-

Fn or Sn t

tF = AlU result
n = nth package
Register file 10 gets F if byte selected, S if byte not selected.

3-83

I 1 I F It

CLEAR

FUNCTION
Forces ALU output to zero and clears the BCD flip-flops.

DESCRIPTION
ALU output is forced to zero and the BCD flip-flops are cleared.
tThis instructio~ may also be coded with the following opcodes:
[2) [F). [3) [F). [4) [F). [6) [F). [B) IF). [e) [F). [E) [F)

Available R Bus Source Operands
C3-CO
RF

A3-AO
(A5-AOI [mmed

DA-Port

f/)

2

......

No

No

No

..
A3-AO
Mask
No

~

~
-4

00
00

W
N

Available S Bus Source Operands
RF
(B5-BOI
No

DB-Port
No

MQ
Register
No

Available Destination Operands
RF
RF
(C5-COI (B5-BOI
No

Ves

Status Signals

IZE~

OVR
. Cn

··3-84

1

o
o
o

Shift Operations

V-Port

ALU

MQ

Ves

None

None

CLR

CRC

Cyclic Redundancy Character Accumulation

I0I0 I

FUNCTION
Evaluates R exclusive OR S for use with cyclic redundancy check codes.

DESCRIPTION
Data on the R bus is exclusive ORed with data on the S bus. If MOO XNORed with
SO is zero (MOO is the LSB of the MO register and SO is the LSB of S-bus data), the
result is sent to the ALU shifter. Otherwise, data on the S bus is sent to the ALU shifter.
A right shift is performed; the MSB is filled with RO (MOO XOR SO). where RO is the
LSB of R-bus data. A circular right shift is performed on MO data.
Recommended R Bus Source Operands

C3-CO
RF
A3-AO
(A5-AO) Immed

DA-Port

N
M
CO
CO

..
A3-AO

I-

Mask
Yes

No

No

(,)

~

No

o:::t

"Z

Recommended S Bus Source Operands

U')

RF
(B5-BO)
Yes

DB-Port

MO
Register

Yes

No

Recommended Destination Operands

RF
RF
(C5-CO) (B5-BO)
Yes

Shift Operations

Y-Port

ALU

MO

No

Right

Right

No

Control/Data Signals

Signal

User

Use

Programmable

SSF

No

5100

No

Inactive
Inactive

SiOT

No

Inactive

5102

No

Inactive

5103

No

Inactive

Cn

No

Inactive

3-85

1010

Cyclic Redundancy Character Accumulation

CRC

Status Signals
ZERO = 1 if result. = 0
N = 0
I

OVR = 0

en

= 0

CYCLIC REDUNDANCY CHARACTER CHECK
DESCRIPTION

en

:5
~

l>

n

-t

ex)

CO

eN
N

Serial binary data transmitted over a channel is susceptible to error bursts. These bursts
may be detected and corrected by standard encoding methods such as cyclic
redundancy check codes, fire codes, or computer generated codes. These codes all
divide the message vector by a generator polynomial to produce a remainder that
contains parity information about the message vector.
If a message vector of m bits, a(x), is divided by a generator polynomial, g(xl. of order
k-1, a k bit remainder,r(x), is formed. The code vector, c(xl. consisting of m(x) and
r(x) of length n = m + k is transmitted down the channel. The receiver divides the
received vector by g(x).
After m divide iterations, r(x) will be regenerated only if there is no error in the message
bits. After k more iterations, the result will be zero if and only if no error has occurred
in either the message or the remainder.

ALGORITHM
An algorithm for a cyclic redundancy character check, using the 'ACT8832 as a
receiver, is given below:
Load MQ with first 32 message bits of
LOADMQ VEC(X)
received vector c'(x).
LOAD POLY

Load register with polynomial g(x).

CLEAR SUM

Clear register acting as accumulator.

REPEAT (n/32) TIMES:
SUM

=

SUM CRC POLY

LOADMQ VEC(X)
(END REPEAT)

3-86

Perform CRC instruction where
R Bus = POLY
S Bus = SUM
Store result in SUM.
Load MQ with next 32 message bits of
received vector c'(x).

CRC

Cyclic Redundancy Character Accumulation

I0 I0 I

SUM now contains the remainder [r'(x)) of c'(x). A syndrome generation routine may
be called next, if required.
Note that the -most significant bit of
g(x) = (gk-1 IIxk-1)

+ (9k_2I1xk-2) + .. (gollx O )

is implied and that POLV(O) is. set to zero if the length of g(x) requires fewer bits than
are in the machine word width.

N
M

CO
CO

....
o



(")
~

00
00
W
N

C3-CO
RF
A3-AO
(A5-AO) Immed

DA-Port

..
A3-AO
Mask

No

No

No

No

Available S Bus Source Operands
MQ
RF
DB-Port
(B5-BO)
Register
Yes

No

No

Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Yes

Shift Operations

Y-Port

ALU

MQ

No

No

No

No

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

Inactive

SIOO

Yes

Byte select

SiOT

Yes

Byte select

SI02

Yes

Byte select

SI03

Yes
No

Inactive

Cn

3-94

Byte select

EX3BC

I 81

Excess-3 Byte Correction

F

I

Status Signals
ZERO

0

N
OVR

0
if arithmetic signed overflow

en

if carry-out = 1

EXAMPLE (assumes a 32-bit configuration)
Add two BCD numbers and store the sum in register 3. Assume data comes in on
DB bus.
1.
2.
3.
4.
5.
6.

Clear accumulator (SUB ACC, ACC)
Store 33 (Hex) in a" bytes of register (SET1 R2, H/33/l
Add 33 (Hex) to selected bytes of first BCD number (BADD DB, R2, R1)
Add 33 (Hex) to selected bytes of second BCD number (BADD DB, R2, R3)
Add selected bytes of registers 1 and 3 (BADD, R1, R3, R3)
Correct the result (EX3BC, R3, R3)

N

('I)

CO
CO
I-

U

c::(
~

Instr

Oprd

Op,d

Op,d S.I

r"

Destination Selects

Dest

Cod.

Add,

Add,

EB1-

Add,

WE3.

17-10

AS-AD

B5-BO

EA EBO

. C5-CO

SELMQ WED SELRFO

0eY3-

SELRF1-

CF2-

'1i'EA Oeii OEYO 0eS

Cn CFO

Si03- 'iESi03SiOo iESiOO

0000

10

X

X

XXXX

0

1

110 XXXX

XXXX

0000

10

X

X

XXXX

0

X

110 XXXX

XXXX

0000

10

X

X

XXXX

0

0

110 1100

0000

000011

o
o
o
o

0000

10

X

X

XXXX

0

0

110 1100

0000

00

00 0011

o

0000

10

X

X

XXXX

0

0

110 1100

0000

X 00

000011

o

0000

10

X

X

XXXX

0

0

110 1100

0000

1111 0010 000010

XX XXX X

0

XX

000010

0000 1000 000010

XX XXXX

0

XX

00 0010

1000 1000 000010

XX XXXX

0

10

00 0001

10001000 000010

XX XXXX

0

10

1000 1000 000001

000011

0

10001111 XXXXXX

000011

Assume DB bus holds 51336912 at third instruction and 34867162 at fourth
instruction.
0000 0000 0000 0000 0000 0000 0000 0000

I RF(2)

2

00000000000000000011 0011 0011 0011

RF(2)

3

0101 0001 0011 0011 1001 110001000101

RF(l) ... RF(2) + DB

4

0011 0100 10000110101001001001 0101

RF(3)

5

0011 01001000011001000000 1101 1010

I RF(3)n'" RF( l)n + RF(3)n

6

0011 0100 1000 0110 0100 0000 0111 0100

I RF(3)n .... Corrected RF(3)n result

+-

0

+-

00003333 (Hex)

+-

RF(2)

+

DB

3-95

2

CJ)

I9 IF

Excess·3 Word Correction

EX3C

FUNCTION
Corrects the result of excess-3 addition or subtraction.

DESCRIPTION
This instruction corrects excess-3 additions or subtractions in the word mode. For
correct excess-3 arithmetic. this instruction must follow each add or subtract. The
operand must be on the S bus.
Data on the S bus is added to a constant on the R bus determined by the state of
the BCD flip-flops and previous overflow condition reported on the SSF pin.
Available R Bus Source Operands
U)

C3-CO

2

-...J

~

l>

RF

A3-AO

DA-Port

(A5-AO) Immed

(")

-t

CO
CO
W
N

..
A3-AO
Mask

No

No

No

No

Available S Bus Source Operands
RF
(85-80)
Yes

D8-Port

MO
Register

No

No

Available Destination Operands
RF
RF
(C5-CO) (85-80)
Yes

No

Shift Operations

Y-Port

ALU

MO

Yes

No

No

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

Inactive

5100

No

Inactive

5101

No

Inactive

SiO'2

No

Inactive

5103

No

Inactive

Cn

No

Inactive

EX3C

I9I

Excess·3 Word Correction

F

Status Signals

o

ZERO

N

1 if MSB =
1 if arithmetic signed overflow

OVR

en

1 if carry-out = 1

EXAMPLE (assumes a 32-bit configuration)
Add two BCD numbers and store the sum in register 3. Assume data comes in on
DA bus.
1.
2.
3.
4.
5.
6.
7.

Clear accumulator (SUB ACC, ACC)
Store 33 (Hex) in all bytes of register (SET1 R2, H/33/)
Add 33 (Hex) to all bytes of first BCD number (ADD DB, R2, R1)
Add 33 (Hex) to all bytes of second BCD number (ADD DB, R2, R3)
Add the excess-3 data (ADD, R1, R3, R3)
Correct the excess-3 result (EX3C, R3, R3)
Subtract the excess-3 bias to go to BCD result.

Instr

Oprd

Oprd

Code
17-10

Addr
AS-AO

Addr

Oprd Sel
EB1-

B5-SO

EAEBO

11110010

000010
000010

XX XXXX

000010
000010

XX XXXX

00001000
1111 0001
1111 0001
1111 0001

000001
1001 1111 XX XXXX
11110010 000010

0
0

xx
xx

0
0

10
10

00 0010
000010
00 0001
000011

00 '0011

0

000011
000011

X

00
00

000011
000011

0

00

00 0011

XX XXXX
XX XXXX

Destination Selects

Dest

Addr
C5-.CO

SELMa
0
0
0
0
0
0
0

WE3WEO

SELRF1SELRFO
10
0000
0000
10
10
0000
10
0000
0000
0000
0000

10
10
10

l5EA OEB

om-

X

X

OEYO
XXXX

X

X

XXXX

X

X

xxx x

X

X

XXXX

X

X

XXXX

X

X

xxxx

X

X

XXXX

CF2-

i5ES
0
0
0
0
0
0
0

Cn CFO
1 110
110
X
110
0
i 10
0
0
0

110
110

0

110

I 9 IF

Excess·3 Word Correction

EX3C

Assume DB bus holds 51336912 at third instruction and 34867162 at fourth
instruction.
Results of Instruction Cycles:
1 0000

en
2
.....
.,::.
l>

o()oo 0000

0000 0000 0000 0000 0000 1 RF(2) -

0

2

1 0011 0011 0011 0011 0011 0011 0011 0011

RF(2) -

33333333 (Hex)

3

1 10000100011001101001 110001000101

RF(1) -

RF(2) + DB

4

1 01100111 1011 1001 101001001001 0101

RF(3) - RF(2) + DB

5

111011000010000001000000110110101

6

1011 1001 0101 0011 0111 0011 10100111 1 RF(3) -

7

100001100010000001000000011101001

RF(3)-RF(1)

+ RF(3)

(")

....
CO

Corrected RF(3) result

CO

eN

N

3-98

RF(3)

+-

RF(3)-RF(2)

Increment Negative R using Carry (R' + Cn)

INCNR
FUNCTION

Evaluates R' +Cn.

DESCRIPTION
Data on the R bus is inverted and added with carry. The result appears at the ALU
and MQ shifters.
"The result of this instruction can be shifted in the same microcycle by specifying a shift instruction in the
upper nibble (17-14) of the instruction field. The result may also be passed without shift. Possible instructions
are listed in Table 15.

Available R Bus Source Operands
C3-CO
RF
A3-AO
(A5-AO) Immed

DA-Port

..
A3-AO
Mask

Ves

No

Ves

No

Available S 8us Source Operands
RF
MQ
DB-Port
(B5-80)
Register

No

No

No

Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Ves

No

V-Port
Ves

ALU

MQ

Shifter

Shifter

Ves

Ves

Control/Data Signals
Signal
SSF
SIOO

~
5102

8m
Cn

User
Programmable

Use

No

Affect shift instructions programmed in bits 17-14 of

No
No

instruction field.

No
No
Ves

Increments if programmed high.
..

3-99

1* 17

Increment Negative Rusing Carry (R' + Cn)

INCNR

Status Signals t
ZERO

if result = 0

N

1 if MSB = 1

OVR

1 if signed arithmetic overflow
if carry-out = 1

C

t C is ALU carry out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR (overflow) is evaluated after ALU operation and after shift operation.

EXAMPLE (assumes a 32-bit configuration)
Convert the data on the DA bus to two's complement and store the result in register 4.
C/)

2

Instr

~

Code
17·10

Oprd
Addr
A5·AO

1111 0111

XX XXXX

-..J

»

n

~

Oprd
Addr
B5-8O
XX XXXX

Oprd Sel
EB1·
EA EBO
1

XX

Dest
Addr

WE3.

Destination Selects
SELRF1·

SELMQ WeO SELRFO
C5·CO
000100
0
0000
10

OEA
X

Assume register file 1 holds 3791 FEF6 (Hex):

CO
Source

00110111 100100011111111011110110

I R ..... DA

Destination

1100100001101110000000010000 1010

I RF(4) ..... R' + Cn

tAo)

N

3-100

0Ev3.

OEB "O'E'YO
X
XXXX

CF2·

0eS
0

Cn CFO
1 110

Increment Negative S using Carry (S' + Cn)

INCNS
FUNCTION
Evaluates S'

+ en.

DESCRIPTION
Data on the S bus is inverted and added to the carry. The result appears at the ALU
and MQ shifters.
"The result of this instruction can be shifted in the same microcycle by specifying Ii shift instruction in the
upper nibble (17-14) of the instruction field. The result may also be passed without shift. Possible instructions
are listed in Table 15.

Available R Bus Source Operands
C3-CO
RF
A3-AO
(A5-AO) Immed

DA-Port

..
A3-AO
Mask

No

No

No

No

Available S Bus Source Operands
RF
MO
DB-Port
(B5-BO)
Register
Yes

Yes

Yes

Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Yes

No

Y-Port

ALU
Shifter

MO
Shifter

Yes

Yes

Yes

Control/Data Signals
Signal

User
Programmable

SSF
5100

No
No

SiOf

No

SI02

No

SI03
Cn

No
Yes

Use
Affect shift instructions programmed in bits 17-14 of
instruction field.

Increments if programmed high.

Increment Negative S using Carry (S' + Cn)

INCNS

Status Signals t
ZERO
N

OVR
C

if result = 0
1 if MSB = 1
1 if signed arithmetic overflow
if carry-out = 1

tc is ALU carry-out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR (overflow) is evaluated after ALU operation and after shift operation.

EXAMPLE (assumes a 32-bit configuration)
Convert the data on the MQ register to one's complement and store the result in
register 4.

en
2

-..J
~

»
(")
""'t

00
00

Instr
Code
17-10
11110101

Oprd
Add,

Oprd
Add,

Oprd Sel

A5-AO

85-80

XX XXXX

XX XXXX

Dest
Add,

EA

EB1·
E80

C5-CO

X

11

000100

Destination Selects

WE3-

SELRF1-

SELMQ

WeO

SELRFO

.0

0000

10

X

X

Assume MO register file 1 holds 3791 FEF6 (Hex):

Co\)

N

Source

00110111100100011111111011110110

Destination

110010000110111000000001 00001001

3-102

I S-

om-

CF2-

OEA OEB 0W0 0Es

MQ register

RF(4)- S'

+

Cn

XXXX

0

Cn CFO
0

110

INCH

Increment H using Carry (H

+

Cn)

I

*

I

6

I

FUNCTION
Increments R if the carry is set.

DESCRIPTION
Data on the R bus is added to the carry. The sum appears at the ALU and MQ shifters.
"The result of this instruction can be shifted in the same microcycle by specifying a shift instruction in the
upper nibble (17-14) of the instruction field. The result may also be passed without shift. Possible instructions
are listed in Table 15.

Available R Bus Source Operands
C3-CO
RF

A3-AO

DA-Port

(A5-AO) Immed

..
A3-AO
Mask

Yes

No

No

Yes

Available S Bus Source
Operands (MSH)
RF
(B5-BO)
No

DB-Port

MQ

Register

No

No

Available Destination Operands
RF

RF

(C5-CO) (B5-BO)
Yes

No

Y-Port
Yes

ALU

MQ

Shifter

Shifter

Yes

Yes

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

Affect shift instructions programmed in bits 17-14 of

5100

No

instruction field.

5101

No

5102

No

5103

No

Cn

Yes

Increments R if programmed high.

3-103

I* I6 I

Increment R using Carry (R

+ Cn)

INCR

Status Signals t
if result = 0

ZERO

N
OVR

Cn

1 if MSB = 1
1 if signed arithmetic overflow
1 if carry-out = 1

t C is ALU carry-out and is evaluated before shift operation. ZERO and N (negative) are evaluated after shift
operation. OVR (overflow) is evaluated after ALU operation and after shift operation.

EXAMPLE (assumes a 32-bit configuration)
Increment the data on the DA bus and store the result in register 4.

en

2:

.....

~

~

Op,d
Instr
Add,
Code
A5-AO
17-10
1111 0110 XX XXXX

Op,d
Addr
B5-BO
XX XXXX

Op,d Sel
EB1EAEBO
1 XX

Destination Selects

Dest

Addr
'We3- SELRF1C5-CO
SELMQ
SELRFO
00 0100
0
0000
10

WEo

0eY3X

X

Assume register file 1 holds 3791 FEF6 (Hex).

-I

~

Source

00010111100100011111111011110110

Destination

0001 0111 1001 0001 1111 1110 1111 0111

W

I R-

DA

N

3-104

CF2-

0eA 0eB 0W0 DeS

RF(4) - R

+ Cn

XXXX

0

Cn
1

CFO
110

Increment 8 using Carry (8 + Cn)

INC8
FUNCTION

Increments S if the carry is set.

DESCRIPTION
Data on the S bus is added to the carry. The sum appears at the ALU and MQ shifters.
*The result of this instruction can be shifted in the same microcycle by specifying a shift instruction in the
upper nibble (17-14) of the instruction field. The result may also be passed without shift. Possible instructions
are listed in Table 15.

Available R Bus Source Operands
C3-CO
RF
A3-AO
(A5-AO) Immed

DA-Port

..

N
M

A3-AO

CX)
CX)

Mask
No

No

No

IU

No

«
~

Available S Bus Source Operands

"en2:

RF
MQ
DB-Port
(B5-BO)
Register
Yes

Yes

Yes

Available Destination Operands
RF

RF

(C5-CO) (B5-BO)
Yes

No

Y-Port
Yes

ALU

MQ

Shifter

Shifter

Yes

Yes

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

Affect shift instructions programmed in bits 17-14 of

SIOO

No

instruction field.

SI01

No

SI02

No

SI03

No

Cn

Yes

Increments S if programmed high.

3-105

Increment S using Carry (S

+ Cn)

INCS

Status Signals t
ZERO

1 if result = 0

N
OVR

1 if MSB = 1
if signed arithmetic overflow
if carry-out == 1

C

t C is ALU carry-out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR (overflow) is evaluated after ALU operation and after shift operation.

EXAMPLE (assumes a 32-bit configuration)
Increment the data in the MQ register and store the result in register 4.

en
2

'"»
~

~

Instr
Code
17-10

Oprd
Addr
A5-AO

Oprd
Addr

Oprd Sel
ES1-

B5-80

EA EBO

11110100 XX XXXX XX XXXX

X

11

Dest
Destination Selects
Addr
0Ev3WE3- SELRF1SELMQ WeO SELRFO OEA Oeii 0eY0
C5-CO
000100
10
X
X
XXX X
0
0000

Assume MQ register holds 54FFOOFF (Hex):

CO
CO
W
N

Source

0101 0100 1111 1111 0000 0000 1111 1111

Destination

0101 0100 1111 1111 0000 0001 00000000

3-106

5

+-

MQ register

I RF(4)

+-

5

+

Cn

CF2-

DeS
0

Cn CFO
1 110

LOADFF

Load Divide/BCD Flip-Flops

I0IFI

FUNCTION
Load divide/BCD flip-flops from external data input.

DESCRIPTION
Uses an internal bypass path to load data from the S MUX directly into the divide/BCD
flip-flops.
Available R Bus Source Operands
C3-CO
RF

A3-AO

DA-Port

(A5-AO) Immed

..
A3-AO
Mask

No

No

No

No

Available S Bus Source Operands
MQ
RF
D8-Port
(85-80)
Register
Yes

Yes

Yes

Available Destination Operands
RF
RF
(C5-CO) (85-801
No

MQ

Y-Port

ALU
Shifter

Shifter

No

No

No

No

ControllData Signals
Signal

User

Use

Programmable

SSF

No

SIOO

No

Inactive
Inactive

STOT

No

Inactive

SI02

No

Inactive,

SI03

No

Inactive

Cn

No

Inactive

3-107

I 0 IF

Load Divide/BCD Flip-Flops

LOADFF

Status Signals

IZERON

=. 0
=

= 0
C = 0

OVR

EXAMPLE (assumes a 32-bit configuration)
Load the divide/BCD flip-flops with data from the DB input bus.

en

z

Instr
Code
17-10
00001111

Oprd
Destination Selects
Oprd
Oprd Sel
Dest
Addr
Addr
EB1Addr
WE'3- SELRF1Ci'EY3SELMQ WEo SELRFO 0eA 0eB 0eY0
A5-AO
B5-BO
EAEBO
C5·CO
XXXX
X
X
XXXX
XX XXXX XX XXXX
X 10 XX XXXX
X
XX

DEs
X

~ Assume DB input holds 2A08C618 (Hex):

»
(")

Source

I

001010100000 1000 110001100001 1000

Is ... DB bus

Destination

I

0010 10100000 1000 110001100001 1000

I Divide/BCD flip-flops -

-f

CO

~
N

3-108

S

CF2Cn CFO
X 110

Pass (Y - F) and load MO with F

lOADMO
FUNCTION

Passes the result of the ALU instruction specified in the lower nibble of the instruction
field to Y and the MQ register.

DESCRIPTION
The result of the arithmetic or logical operation specified in the lower nibble of the
instruction field (13-10) is passed unshifted to Y and the MQ register .
• A list of ALU operations that can be used with this instruction is given in Table 15.

Shift Operations

N
M

00
00

Available Destination Operands
RF

I-

o

(C5-CO)

RF
(B5-BO)

V-Port

Ves

No

Ves



('")

-4

CO
CO

Instr
Code
17·10
1111 1100

Oprd
Addr
A5·AO
000011

Oprd
Addr
B5·BQ
000101

Oprd Sel
Dest
Addr
EB1·
EA EBO CS·CO
0 00 000101

Destination Selects
SELRF1·
SELMa
SELRFO 0eA 0eB
10
X
X
0
0000

WE3.
WeD

0eV3.
0eY0 DEs
XXXX

0

CF2·
Cn CFO
X 110

Assume register file 1 holds 60F6D840 (Hex) and register file 5 holds 13F6D377 (Hex).

~

I

Source

01100000111101101101100001000000

Source

00010011 111101101101001101110111

S - RF(5)

Destination

1111 1111 0000 1001 0010 1111 1011 1111

RF(5) - R NAND S

3·120

R-RF(3)

NOP

No Operation

IFIFI

FUNCTION
Forces AlU output to zero.

DESCRIPTION
This instruction forces the AlU output to zero. The BCD flip-flops retain their old value.
Note that the clear instruction IClR) forces the AlU output to zero and clears the BCD
flip-flops.
Available R Bus Source Operands
C3-CO
RF

A3-AO

(A5-AO) Immed

DA-Port

..
A3-AO
Mask

No

No

No

No

Available S Bus Source Operands
RF
MQ
DB-Port
(B5-BO)
Register
No

No

No

Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Yes

No

Shift Operations

Y-Port

ALU

MQ

Yes

None

None

Status Signals

IZER~

1

o
o

OVR

C

=

0

3-121

I FI F

NOP

No Operation

EXAMPLE (assumes a 32-bit configuration)
Clear register 12.
Instr
Code
17-10
11111111

Oprd
Addr
A5-AO
XX XXXX

Destination

3-122

I

Oprd
Oprd Sel
Dest
Destination Selects
EB1Addr
Addr
We3- SELRF1B5-BO
EAEBO
C5-CO SELMa WEO SELRFO 0eA
10
XXXX
00 1100
0
0000
X
X

xx

me

x xx

000000000000000000000000 0000 0000

I RF(12) -

0

0eV3-

0eY0 l5ES
XXXX

0

CF2'
Cn CFO
X 110

NOR

Logical NOR (R NOR S)

FUNCTION
Evaluates the logical expression R NOR S.

DESCRIPTION
Data on the R bus is NORed with data on the S bus. The result appears at the ALU
and MQ shifters.
'The result of this instruction can be shifted in the same microcycle by specifying a shift instruction in the
upper nibble (17-141 of the instruction field. The result may also be passed without shift. Possible instructions
are listed in Table 15.

Available R Bus Source Operands

RF
A3-AO
(AS-AO) Immed

DA-Port

C3-CO
.,
A3-AO
Mask

Yes

No

Yes

No

Available S Bus Source Operands
MQ
RF
DB-Port
(B5-BO)
Register
Yes

Yes

Yes

Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Yes

No

Y-Port
Yes

ALU

MQ

Shifter

Shifter

Yes

Yes

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

Affect shift instructions programmed in bits 17-14 of

SIOO

No

instruction field.

SI01

No

SI02

No

SI03

No

Cn

No

Inactive

3-123

NOR

Logical NDR(R NOR· S)
Status Signals t
ZERO
N
OVR
C

1 if result = 0

1 if MSB

=

1

o
o

tc is ALU carry out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR (overflow) is evaluated after ALU operation and after shift operation.

EXAMPLE (assumes a 32-bit configuration)
Logically NOR the contents of register 3 and register 5, and store the result
in register 5.
t/)

2

;"
o

-I

00
00

Inst,
Code
17-10
11111011

Oprd
Add,
A5-AO
000011

Op,d
Add, ,
B5-BO
000101

Op,d Sel

Cast
Add,
EB1·
C5-CO
EAEBO
0 00 000101

Oestinetion Selects
SELRF1·
SELMQ WeO SELRFO OEA 0eB 0EY0
10
X
X XXXX
0
0000

om·

WE3.

0eS
0

CF2·
Cn CFO
X 110

Assume register file 3 holds 60F6D840 (Hex) and register file 5 holds 13F6D371 (Hex).

~

Source

01100000 111101101101100001000000

I R- RF(3)

Source

00010011111101101101001101110111

I S-

Destination

1000 1100 0000 1001 00100100 1000 1000

I RF(5) -

3-124

RF(5)
R NOR S

OR

Logical OR (R OR S)

I

*

IB I

FUNCTION
Evaluates the logical expression R OR S.

DESCRIPTION
Data on the R bus is ORed with data on the S bus. The result appears at the ALU
and MQ shifters.
"The result of this instruction can be shifted in the same microcycle by specifying a shift instruction in the
upper nibble (17-14) of the instruction field. The result may also be passed without shift. Possible instructions
are listed in Table 15.

Available R Bus Source Operands
C3-CO
RF

A3-AO

DA-Port

(A5-AO) Immed

..

A3-AO
Mask

Yes

No

Yes

No

Available S Bus Source Operands
RF
MO
DB-Port
(B5-BO)
Register
Yes

Yes

Yes

Available Destination Operands
RF
RF
(C5-CO) (B5-BO)
Yes

No

Y-Port
Yes

ALU

MO

Shifter

Shifter

Yes

Yes

Control/Data Signals
Signal

User

Use

Programmable

55F

No

Affect shih instructions programmed in bits 17-14 of

5100

No

instruction field.

5101

No

5102

No

5103

No

Cn

No

Inactive

3-125

Logical OR (R OR S)

OR

Status Signals t
ZERO

1 if result = 0

N
OVR
C

1 if MSB = 1

o
o

t C is ALU carry out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR (overflow) is evaluated after ALU operation and after shift operation.

EXAMPLE (assumes a 32-bit configuration)
logically OR the contents of register 5 and register 3, and store the result in
register 3.

en
z
.....
~

:t>

(")

-t

00
00

InSlr
Code
17-10
1111 1011

Oprd
Addr
A5-AO
000101

Oprd
Addr
B5-BO
000011

Oprd Sel
Desl
EB1Addr
EAEBO
C5-CO
0 00
000011

Destination Selects

"We3WeO

SELRF1SELMO
SELRFO
0
0000
10

om-

l5EA Oeii 0eY0 OES
X

X

XXXX

0

CF2Cn CFO
X 110

Assume register file 5 holds 60F6D840 (Hex) and register file 3 holds 13F6D377 (Hex).

~

I

Source

01100000111101101101100001000000

Source

00010011111101101101001101110111

S

Destination

0111 0011 1111 0110 1101 1011 0111 0111

RF(3)

3-126

R +- RF(5)

+-

RF(3)

+-

R OR 5

PASS

F

Pass (Y - F)

FUNCTION
Passes the result of the ALU instruction specified in the upper nibble of the instruction
field to Y MUX.

DESCRIPTION
The result of the arithmetic or logical operation specified in the lower nibble of the
instruction field (13-101 is passed unshifted to Y MUX .
• A list of ALU operations that can be used with this instruction is given in Table 1 5.

Available Destination Operands
RF

RF

(C5-CO)

(B5-BO)

Yes

No

Y-Port
Yes

ALU

MO

Shifter

Shifter

None

None

Control/Data Signals

Signal

,

User

Use

Programmable

SSF

No

Inactive

SiOo

No

Inactive

SI01

No

Inactive

Si02

No

Inactive

SI03

No

Cn

,No

Inactive
Affects arithmetic operation specified in bits 13-10 of
instruction field.

Status Signals t
ZERO

N

1 if result = 0
1 if MSB of result = 1

o if MSB of result
OVR

C

= 0

1 if Signed arithmetic overflow
if carry-out condition

t C is ALU carry out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR (overflow) is evaluated after ALU operation and after shift operation.

IF 1*

PASS

Pass(Y - F)

EXAMPLE (assumes a 32-bit configuration)
Add data in register 1 to data on the DB bus with carry-in and store the unshifted
result in register 10.
Instr

Code
17-10
1111 0001

Op,d
Add,
AS-AO
000001

Op,d
Op,d Sel
Dest
Destination Selects
Add,
Add,
EB1WE3- SELRF1:
B5-BO
EA EBO C5-CO SELMQ WEO SELRFO 0eA 0e'i3
XX XXXX
0 10 001010
0
0000
10
X
X

0eY30eYci DeS
XXXX

0

CF2Cn CFO
1 110

Assume register file 3 holds 9308C618 (Hex) and DB bus holds 24007530 (Hex).
Source

100100110000 1000 1100011000011000

I R +- RF(1)

Source

00100100000000000111 0101 0011 0000

Is+- DB bus

Destination

1011 0111 00001001 0011 1011 01001001

3-128

RF(10)

+- R + S + en

SDIVI

Signed Divide Iterate

I A 10 I

FUNCTION
Performs one of N-2 iterations of nonrestoring signed division by a test subtraction
of theN-bit divisor from the 2N-bit dividend. An algorithm using this instruction is
given in the "Other Arithmetic Instructions" section.

DESCRIPTION
SDIVI performs a test subtraction of the divisor from the dividend to generate a quotient
bit. The test subtraction passes if the remainder is positive and fails if negative. If
it fails, the remainder will be corrected during the next instruction.
SDIVI checks the pass/fail result of the test subtraction from the previous instruction,
and evaluates
F
F

++-

R + S
R' + S + Cn

N
M
00

if the test fails
if the test passes

A double precision left shift is performed; bit 7 of the most significant byte of the MO
shifter is transferred to bit 0 of the least significant byte of the ALU shifter. Bit 7 of
the most significant byte of the ALU shifter is lost. The unfixed quotient bit is circulated
into the least significant bit of the MO shifter.
The R bus must be loaded with the divisor, the S bus with the most significant half
of the result of the previous instruction (SDIVI during iteration or SDIVIS at the beginning
of iteration). The least significant half of the previous result is in the MO register. Carryin should be programmed high. Overflow occurring during SDIVI is reported to OVR
at the end of the signed divide routine (after SDIVOF).
Available R Bus Source Operands
C3-CO
RF
A3-AO
(A5-AO) Immed
Yes

No

DA-Port

Yes

..
A3-AO
Mask
No

Recommended S Bus Source Operands
RF
MO
DB-Port
(B5-BO)
Register
No
Yes
Yes
Recommended Destination Operands
RF
RF
(C5-CO) (B5-BO)
Yes
No

Shift Operations

Y-Port

ALU

MO

Yes

Left

Left

3-129

~

(,)

«
~

~

IAlo

Signed Divid., Iterat.,

Control/Data Signals
Signal
SSF

SiOO
~

!i02
Si03
Cn

User
Programmable
No
No

Inactive
Pass internally generated end-fill bits.

No
No
No
Yes

Should be programmed high

Use

Status Signals

en
2
.....
~
~
-I
CO
CO

ZERO = 1 if .intermediate result
N = 0
OVR = 0
C = 1 if carry-out

Co\)

N

3-130

=0

SDIVI

. Signed Divide Initialize

SDIVIN

I8I0I

FUNCTION
Initializes' ACT8832 for nonrestoring signed division by shifting the dividend left and
internally preserving the sign bit. An algorithm using this instruction is given in the
"Other Arithmetic Instructions section.

DESCRIPTION
This instruction prepares for signed divide iteration operations by shifting the dividend
and storing the sign for future use.
The preceding instruction should load the MO reqister with the least significant half
of the dividend. During SDIVIN, the S bus should be loaded with the most significant
halfof the dividend, and the R bus with the divisor. V-output should be writteh back
to the register file for use in the next instruction.
N

A double precision logical left shift is performed; bit 7 of the most significant byte
of the MO shifter is transferred to bit 0 of the least significant byte of the ALl) shifter.
Bit 7 of the most significant byte of the ALU shifter is lost. The unfixed quotient sign
bit is shifted into the least significant bit of the MO shifter.

~
I~

Available R Bus Source Operands

,....

(W)

q-

Z

VJ

C3-CO

RF

A3-AO
(A5-AO) Immed
Yes

No

DA-Port

Yes

..
A3-AO
Mask
No

Recommended S Bus Source Operands

RF
(85-80)
Yes

D8-Port
Yes

MQ
Register
No

Recommended Destination Operands

RF

RF

(C5-CO) (85-80)
Yes
No

Shift Operations

Y-Port

ALU

MQ

Yes

Left

Left

3-131

I8 I0 I

Signed Divide Initialize

Control/Data Signals
Signal

User

SSF

No

Inactive

5100

No

Pass internally generated end-fill bits.

SiOT

No

Si02

No

5103

No

Cn

No

Status Signals

~ IZER~
~

OVR

l>

Cn

(")

Use

Programmable

-I

00
00
W
N

3-132

1 if divisor = 0

o
o
o

Inactive

SDiVIN

SOIVIS

Signed Divide Start

I9I0I

FUNCTION
Computes the first quotient bit of nonrestoring signed division. An algorithm using
this instruction is given in the "Other Arithmetic Instructions" section ..

DESCRIPTION
SDIVIS computes the first quotient bit during nonrestoring signed division by subtracting
the divisor from the dividend, which was left-shifted during the prior SDIVIN instruction.
The resulting remainder due to subtraction may be negative. If so, the subsequent
SDIVI instruction will restore the remainder during the next subtraction.
The R bus must be loaded with the divisor and the S bus with the most significant
half of the remainder. The result on the Y bus should be loaded back into the register
file for use in the next instruction. The least significant half of the remainder is in the
MQ register. Carry-in should be programmed high.

N
M
00
00

A double precision left shift is performed; bit 7 of the most significant byte of the
MQ shifter is transferred to bit 0 of the least significant byte of the ALU shifter. Bit 7
of the most significant byte of the ALU shifter is lost. The unfixed quotient bit.is
circulated into the least significant bit of the MQ shifter.

(.)

Overflow occurring during SDIVIS is reported to OVR at the end of the signed division
routine (after SDIVQF).

"
en

Available R Bus Source Operands
C3-CO
RF

A3-AO

(A5-AO) Immed

DA-Port

..
A3-AO
Mask

Yes

No

Yes

No

RecommendedS Bus Source Operands
MQ
RF
DB-Port
(B5-BO)
Register
Yes

Yes

No

Recommended· Destination Operands
RF
RF
(C5-CO) (B5-BO)
Yes

No

Shift Operations

Y-Port

ALU

MQ

Yes

Left

Left

3-.133

I-

«
o::t

:2

19 10

Signed Divide Start

SDIVIS

ControlfData Signals
Signal

User

Use

Programmable

SSF

No
No

5100
5101
5102
5103

Inactive
Pass internally generated end-fill bits.

No
No
No

Cn

Yes

Should be programmed high.

Status Signals
t/)

2

'-J

~

l>

(")

ZERO
N
OVR
C

1 if intermediate result = 0

o
o
1 if carry-out

~

CO
CO

W
N

I

.3-134

SDiVIT

Signed Divide Terminate

I EI 0 I

FUNCTION
Solves the final quotient bit during nonrestoring signed division. An
algorithm using this instruction is given in the "Other Arithmetic Instructions" section.

DESCRIPTION
SDIVIT performs the final subtraction of the divisor from the remainder during
nonrestoring signed division. SDIVIT is preceded by N-2 iterations of SDIVI, where
N is the number of bits in the dividend.
The R bus must be loaded with the divisor, and the S bus must be loaded with the
most significant half of the result of the last SDIVI instruction. The least significant
half lies in the MQ register. The Y bus result must be loaded back into the register
file for use in the subsequent DIVRF instruction. Carry-in should be programmed high.
SDIVIT checks the pass/fail result of the previous instruction's test subtraction and
evaluates;
Y+-R+S
Y +- R' + S

+

U

«
~

The contents of the MQ register are shifted one bit to the left; the unfixed quotient
bit is circulated into the least significant bit.
Overflow during this instruction is reported to OVR at the end of the signed division
routine (after SDIVQF).
Available R Bus Source Operands
C3 cCO
RF

A3-AO

(A5-AO) Immed

DA-Port

..
A3-AO

Mask
Ves

No

Ves

No

Recommended S Bus Source Operands
RF
MO
DB-Port
(B5-8O)
Register
Ves

Ves

No

Recommended Destination Operands
RF

RF

(C5-CO) (B5-80)
Ves

No

Shift Operations

V-Port

ALU

MO

Ves

Left

Left

('f)

CO
CO
~

if the test fails
if the test passes

Cn

N

3-135

"Z

fI)

IEI0 I

Signed Divide Terminate

Control/Data Signals
Signal
SSF
SIOO

User

Use

Programmable
No

Inactive

No

Pass internally generated end-fill bits.

mer

No

Si02

No

SiOO

No

Cn

Yes

Should be programmed high

Status Signals

(')
-t

Use

Programmable

C

ex)
ex)
Co\)

N

3-138

1 if divisor = 0
0
0
1 if carry-out

Inactive

SDIVO

SDIVQF

Signed Divide Quotient Fix

I5I0 I

FUNCTION
Tests the quotient result after nonrestoring signed division and corrects it if necessary.
An algorithm using this instruction is given in the "Other Arithmetic Instructions"
section.

DESCRIPTION
SDIVQF is the final instruction required to compute the quotient of a 2N-bit dividend
by an N-bit divisor. It corrects the quotient if the signs of the divisor and dividend are
different and the remainder is nonzero.
The fix is implemented by incrementing S:

v-S+
v-S+O

if a fix is required
if no fix is required

N
M

The R bus must be loaded with the divisor, and the S bus with the most significant· IX)
half of the result of the preceding DIVRF instruction. The least significant half is in ~
the MQ register.
(.)

«
~
r...

Available R Bus Source Operands

Z

U)

C3-CO

RF

A3-AO

(A5-AO) Immed

DA-Port

..
A3-AO
Mask

Yes

No

Yes

No

Recommended S Bus Source Operands

RF
(B5-BO)
Yes

DB-Port
Yes

MQ
Register
No

Recommended Destination Operands

RF

RF

(C5-CO) (B5-BO)
Yes

No

Shift Operations

Y-Port

ALU

MQ

Yes

None

None

3-139

1510

Signed Divide Quotient Fix

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

Inactive

SIOO

No

Inactive

SI01

No

Inactive

SI02

No

Inactive

SI03

No

Inactive

Cn

Yes

Should be programmed high

Status Signals
CJ)

2

ZERO

.....

N

»
n

OVR

~

-I
CO
CO

C

W
N

3-140

1 if quotient = 0
1 if sign of quotient

+

o if sign of quotient

+ 0

1 if divide overflow
1 if carry-out

SDIVQF

SEL

Select SIR

1

I0J

FUNCTION
Selects S if SSF is high; otherwise selects R.

DESCRIPTION
Data on the S bus is passed to Y if SSF is programmed high or floating; data on the
R bus is passed without carry to Y if SSF is programmed low.
Av,llabie R Bus Source Operands
C3-CO

RF

A3-AO

(A5-AO) Immed
Yes

DA-Port

No

Yes

..
A3-AO
Mask
No

Available S Bus Source
Operands (MSH)

RF
(B5-BO)
Yes

DB-Port

MQ
Register

Yes

Yes
Shift Operadons

Available Destination Operands

RF

RF

(C5-CO) (85-BO)
Yes

No

Y-Port

ALU

MQ

Yes

None

None

Control/Data Signals
Signal

User
Programmable

SSF

Yes

SelectsS if high, R if low.

~

Inactive

~

No
No

'S"m

No

Inactive
Inactive

.~

No

Inactive

Cn

No

Inactive

Use

I l' I 0 I

SEt

Select SIR

Status Signals
1 if result = 0
1 if MSB =

ZERO

N

o
o

OVR

C

EXAMPLE (assumes a 32-bit configuration)
Compare the two's complement numbers in registers 1 and 3 and store the larger in
register 5.
1. Subtract (SUBS) data in register 3 from data in register 1 and pass the result
to the Y bus.
2. Perform Select SIR instruction and pass result to register 5.
t/)

[This example assumes the SSF is set by the negative status (N) from the previous

:2
...... instruction] .
~

»
n
-I

CO
CO
Co\)

N

Instr

Code
17-10
11 I 1 0011
0001 0000

Oprd
Addr
A5-AO
000001
000001

Oprd
Addr
B5-80
000011
000011

Oprd Sel
EB1EAE80
0 00
0 00

Dest
Addr
C5-CO

xx xxx x
000101

SELMa
0
0

Destination Selects
WE3- SELRFI WEo SELRFO OEA l5Eii

0Ev3-

0eY0 0eS

xxxx

xx

x

x

0000

0000

10

X

X

xxxx

0
0

CF2Cn CFO
1 110
0 110

Assume register file 1 holds 00849700 (Hex) and register file 3 holds 01 C35250 (Hex).

Instruction Cycle 1
Source

00000000 1000 0100 1001 0111 1101 0000

I R +- RF( 11

Source

00000001 11000011 0101 00100101 0000

Is+- RF(31

Destination

11111110110000010100010110000000

I Y bus +- R + S' + Cn

Instruction Cycle 2
Source

00000000 1000 0100 1001 0111 1101 0000

I R"" RF(

GJ

1)

SSF"" 1

Source

0000 0001 11000011 0101 00100101 0000

Is .... RF(3)

Destination

0000 0001 11000011 0101 00100101 0000

I RF(51"" S

3-142

SETO

1

Reset Bit

8

FUNCTION
Resets bits in selected bytes of S-bus data using mask in C3-CO::A3-AO.

DESCRIPTION
The register addressed by 85-80 is both the source and destination for this instruction.
The source word is passed on the S bus to the ALU, where it is compared to an 8-bit
mask, consisting of a concatenation of the C3-CO and A3-AO address ports
(C3-CO::A3-AO). The mask is input via the R bus. All bits in the source word that are
in the same bit position as ones in the mask are reset. Bytes with their SIO inputs
programmed low perform the Reset 8it instruction. Bytes with their SIO inputs
programmed high or floating pass S unaltered.
AvaiiableR Bus Source Operands
C3-CO
RF

A3-AO

DA-Port

(A5-AO) Immed

..
A3-AO
Mask

No

No

No

Yes

Available S Bus Source
Operands (MSHI
RF
MQ
DB-Port
(B5-BO)
Register
Yes

Yes

Yes

Available Destination Operands
RF
RF
(C5-COI (B5-BOI
No

Yes

Shift Operations

Y-Port

ALU

MQ

Yes

None

None

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

SIOO

No

Inactive
Byte-select

SI01

No

Byte-select

SI02

No

Byte-select

SI03

No

Byte-select

Cn

No

Inactive··

3-143

I1 I8

SETO

Reset Bit

Status Signals

ZERO

1 if result (selected bytes) = 0

o
o
o

N
OVR

C

EXAMPLE (assumes a 32-bit confiQuration)
Set bits 3-0 of bytes ·1 and 2 of. register file 8 to zero and store the result back in
register 8.

en

z

"
»
(')
~

Instr

Mask

Oprd

Oprd Sel

Mask

Code

ILSH)

Addr

EB1-

IMSH)

17-10

A3-AO

B6-BO

EAEeo

C3-CO

0001 1000

1111

001000

X 00

0000

Destination Selects
SELRF1-

SELMO

WE:i.\iiiEO

0

0000

10

SELRFO

om-

CF2-

OEA 0Ee 0EY0 0Es'
X

X

XXXX

Cn CFO

0

X 110 1001

Assume register file 8 holds A083BEBE (Hex).
Rn ..... C3-CO::A3-AO

-4

Source

00001111000011110000111100001111

W
N

Source

10100000100000111011111010111110

I

Sn ..... RF(3)n

ALU

10100000100000001011 00001011 1110

I

Fn ..... Sn AND Rn

Destination

10100000100000001011000010111110

I

RF(8)n ..... Fn or Sn t

CO
CO

tF = ALU result
n = nth byte
Register file 8 gets F if byte selected, S if byte not selected.

3-144

S'iOO- i'ESi035100 iEsiOo
0000

I0I8I

Set Bit

SET1
FUNCTION

Sets bits in selected bytes of S-bus data using mask in C3-CO::A3-AO.

DESCRIPTION
The register addressed by B5-BO is both the source and destination for this instruction.
The source word is passed on the S bus to the ALU, where it is compared to an 8-bit
mask, consisting of a concatenation of the C3-CO and A3-AOaddress ports
(C3-CO::A3-AO). The mask is input via the R bus. All bits in the source word that are
in the same bit position as ones in the mask are forced to a logical one. Bytes with
their SIO inputs programmed low perform the Set Bit instruction. Bytes with their
SIO inputs programmed high or floating pass S unaltered.
Available R Bus Source Operands

N

('I)

CO
CO
I-

C3-CO
A3-AO
RF
(A5-AO) Immed
No

DA-Port

No

..
A3-AO

o

Mask

q-

Yes

"enz

No



()

-t

Q)
Q)

'Instr

Oprd

Oprd

Oprd Set

Dest

Code

Addr

Addr

ES1-

Addr

17-10

AS-AD

B5-BO

0101 0001

00 0001

XX XXXX

-EA ESO
a

10

-

Destination Selects

WE3- SELRFl -

C5-CO

SELMQ

00 0001

a

WED

$ELRFO

0000

10

-

-

OEY3-

CF2- SID3-

OEA

DEB

0EY0'

DES

X

X

XXXX

0

Cn CFO
0

iESi03-

SIOO

IESIOO

SSF

110 1110

0000

1

W

N Assume register file 1 holds 2408C618 (Hex), DB bus holds 26007530 (Hex), and
MQ register holds 50A99AOE (Hex).
MSH
Source

0010 0100 0000 1000 1100 0110 0001 1000 1

R ... RF(1)

Source

0010 0110 0000 0000 0111010100110000 1

S ... DB bus

Intermediate
Result

0100 1010 0000 1001 0011 1011 0100 1000·1

ALU Shifter'" R

Destination

1001 0100 0001 0010 0111 0110 1001 0000 1

RF(1)

0101 0000 1010 1001 1001 1010 0000 1110 1

MQ shifter

1010 0001 0101 0011 0011 0100 0001 1101

MQ register

+-

+ S + Cn

ALU shift register

LSH
Source

Destination

3-150

+-

MQ register

+-

MQ shift result

SLC

Circular Left Single Precision Shift

I6I

*

I

FUNCTION
Performs circular left shift on result of ALU operation specified in lower nibble of
instruction field.

DESCRIPTION
The result of the ALU operation specified in instruction bits 13-10 is rotated one bit
to the left. Bit 7 of the most significant byte in each word is passed to bit a of the
least significant byte in the word, which may be 1, 2, or 4 bytes long.
The shift may be made conditional on SSF. If SSF is high or floating, the shift result
will be sent to Y MUX. If SSF is low, F is passed unaltered .
• A list of ALU operations that can be used with this instruction is given in Table 1 5.

Shift Operations

ALU Shifter
Circular Left

MQ Shifter
None

Available Destination Operands (ALU Shifter)

RF
RF
(C5-CO) (B5-BO)
Ves

No

V-Port
Yes

Control/Data Signals

Signal
SSF
5100
5101
5102
5103
Cn

User
Programmable
Yes
No
No
No
No
No

Use
Passes shift result if high; passes ALU result if low.
Bit 7 of ALU result
Bit 1 5 of ALU result
Bit 23 of ALU result
Bit 31 of ALU result
Affects arithmetic operation specified in bits 13-10 of
instruction field.

3-151

I6 I*

Circular left Single Precision Shift

SLC

Status Signals t
ZERO

N

1 if result = 0
1 if MSB of result = 1

o if MSB of result
OVR

= 0

1 if signed arithmetic overflow
if carry-out condition

C

t C is ALU carry-out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR (overflow) is evaluated after ALU operation and after shift operation.

EXAMPLE (assumes a 32-bit configuration)
Perform a circular left shift of register 6 and store the result in register 1.
rJ)

Z

-...J
~

»
n

Code
17-10

Oprd
Addr
A5-AO

Oprd
Addr
B5-BO

01100110

000110

XX XXXX

Instr

Oprd Sel
EB1-

Eli: EBO
0

00

Oest
Addr
C5-CO
000001

Destination Selects

SELMQ

WEJWEo

SELRF1SELRFO

0

0000

10

OEY3-

OEA 0Ee 0eY0 DES
X

X

XXXX

0

CF2Cn CFO SSF
-0 110
1

-t

00 Assume register file 6 holds 3788C618 (Hex).
00

~

Source

0011 0111 1000 1000 110001100001 1000

I

R

Intermediate
Result

0011 0111 10001000110001100001 1000

I

ALU Shifter

Destination

0110 1111 0001 0001 1000 11000011 0000

I

RF( 1)

3-152

+-

RF(6)

+-

+-

R

+ Cn

ALU shifter result

SLCD

Circular Left Double Precision Shift

7

FUNCTION
Performs circular left shift on MO register (LSH) and result of ALU operation specified
in lower nibble of instruction field (MSH).

DESCRIPTION
The result of the ALU operation specified in instruction bits 13-10 is used as the upper
half of a double-precision word, the contents of the MO register as the lower half.
The contents of the MO and ALU registers are rotated one bit to the left. Bit 7 of the
most significant byte in the MO shifter is passed to bit 0 of the least significant byte
of the ALU shifter. Bit 7 of the most significant byte is passed to bit 0 of the least
significant byte in the MO shifter.
The shift may be made conditional on SS~. If SSF is high or floating, the shift result
will be sent to Y MUX. If SSF is low, F is passed unaltered and the MO register is
not changed.

N

*A list of ALU operations that can be used with this instruction is given in Table 15.

U

Shift Operations

"

.«
~
Z

ALU Shifter

MQ Shifter

Circular Left

Circular Left

CJ)

Available Destination Operands (ALU Shifter)
RF

RF

(C5-CO)

(B5-BO)

Yes

No

Y-Port
Yes

Control/Data Signals
Signal

~

CO

User

Use

Programmable

SSF

Yes

SIOO

No

Passes shift result if high; passes ALU result if low;
Bit 7 of ALU result

SI01

No

Bit 1 5 of ALU result

SI02

No

Bit 23 of ALU result

5103

No

Bit 31 of ALU result

Cn

No

Affects arithmetic operation specified in bits 13-10 of
instruction field.

Circular Left Double Precision Shift

SLCD

Status Signals t
ZERO

N

1 if result = 0
1 if MSB of result = 1

o if MSB of result
OVR

C

= 0

1 if signed arithmetic overflow
1 if carry-out condition

tc is AlU carry-out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR (overflow) is evaluated after AlU operation and after shift operation.

EXAMPLE (assumes a 32-bit configuration)
(J)

:2

Perform a circular left double precision shift of data in register 6 (MSH) and MO (LSH),
and store the result back in register 6 and the MO register.

~

~

»
(")

Instr

Oprd

Oprd

Code
17-10

Addr
A5-AO

Addr
B5-BO

Oprd Sel

Eft:

EB 1EBO

Dest
Addr
C5-CO

Destination Selects

SELMa

WE3WED

SELRF1SELRFO

0Eii 0eB

0eY36EYo OES

CF2Cn CFO SSF

-4 01110110 000110 XXXXXX 0 00 000110 o 0000 l O X X XXXX 0 0 110 1
CO
CO Assume register file 6 holds 3708C618 (Hex) and MO register holds 50A99AOE (Hex).
CN
N

MSH
Source

0011 0111 00001000110001100001 1000

IR

Intermediate
Result

0011 0111 00001000 110001100001 1000

I ALU Shifter

Destination

01101111 0001 0001 1000 11000011 0000

I RF(6}

Source

0101 00001010 1001 1001 101000001110

I MQ register ..... MQ register

Destination

10100001 0101 0011 0011 01000001 1100

I MQ register

+-

RF(6}

+-

+-

R + Cn

ALU shifter result

LSH

3-154

+-

MQ shift result

SMTC

Sign Magnitude/Two's Complement

I5I

8

I

FUNCTION
Converts data on the S bus from sign magnitude to two's complement or vice versa.

DESCRIPTION
The S bus provides the source word for this instruction. The number is converted by
inverting S and adding the result to the carry-in, which should be programmed high
for proper conversion; the sign bit of the result is then inverted. An error condition
will occur if the source word is a negative zero (negative sign and zero magnitude).
In this case, SMTC generates a positive zero, and the OVR pin is set high to reflect
an illegal conversion.
The sign bit of the selected operand in the most significant byte is tested; if it is high,
the converted number is passed to the destination. Otherwise the operand is passed
unaltered.
Available R Bus Source Operands
C3-CO
RF
A3-AO
(AS-AO) Immed

DA-Port

..
A3-AO
Mask

No

No

No

No

Available S Bus Source Operands
RF
MQ
DB-Port
(B5-BO)
Register
Yes

Yes

Yes

Available Destination Operands
RF
RF
(C5-CO) (85-80)
Yes

No

Shift Operations

V-Port

ALU

MQ

Yes

None

None

3-155

I5 I8

SMTC

Sigm Magnitude/Two'sComplement

Control/Data Signals
Signal

(J)

2

"l>
~

(")

User

Use

Programmable

SSF

No

Inactive

SIOO

No

Inactive

SI01

No

Inactive

SI02

No

Inactive

SI03

No

Inactive

Cn

Yes

Should be programmed high for proper conversion

Status Signals
ZERO

1 if result = 0

N

1 if MSB = 1

OVR

1 if input of most significant byte is 80 (Hex) and results in all other
bytes are 00 (Hex).

-I

CO
C = 1 if S = 0
CO
W
N EXAMPLES (assumes a 32-bit configuration)
Convert the two's complement number in register 1 to sign magnitude representation
and store the result in register 4.

Instr

Op,d

Op,d

Op,d Sel

Code
17·10

Add,

Add,

A5·AO

B5·BO
000001

EB1·
EA EBO

0101 1000 XX XXXX

X 00

Des!
Add,

Destination Selects

We3.

SELRF1·

SELMO WeO SELRFO
C5·CO
000100
0
0000
10

OEY3·

OEA

OEB

X

X

Example 1: Assume register file 1 holds C3F6D840 (Hex).
Source

11000011 1111 01101101 100001000000

Is+- RF(1)

Destination

1011 110000001001 00100111 11000000

I RF(4) +- S' + Cn

Example 2: Assume register file 1 holds 550927CO (Hex).
Source

0101 0101 00001001 00100111 11000000

Is+- RF(1)

Destination

0101 0101 0000 1001 00100111 11000000

I RF(4) ..... S

3-156

OEYO 0eS
XXXX

0

CF2·
Cn CFO
1

110

SMUll

Signed Multiply Iterate

I6I0I

FUNCTION
Computes one of N-1 signed or N mixed multiplication iterations for computing an
N-bit by N-bit product. Algorithms for signed and mixed multiplication using this
instruction are given in the "Other Arithmetic Instructions" section.

DESCRIPTION
SMUll checks to determine whether the multiplicand should be added with the present
partial product. The instruction evaluates:
F- R

+

S

+

Cn

F-S

if the addition is required
if no addition is required

A double precision right shift is performed. Bit 0 of the least significant byte of the
ALU shifter is passed to bit 7 of the most significant byte of the MQ shifter; carry-out
is passed to the most significant bit of the ALU shifter.

N
C")

CO
CO

....

The S bus should be loaded with the contents of an accumulator and the R bus with
the multiplicand. The Y bus result should be written back to the accumulator after
each iteration of UMULI. The accumulator should be cleared and the MQ register loaded
with the multiplier before the first iteration.

o
~

Available R Bus Source Operands

CI'J

C3-CO
RF

A3·AO

(A5-AO) Immed

DA-Port

..
A3-AO
Mask

Yes

No

Yes

No

Recommended S Bus Source Operands
RF
(B5-BO)
Yes

DB-Port
Yes

MQ
Register
No

Recommended Destination Operands Shift Operations
RF

RF

(C5-CO) (B5-BO)
Yes

No

Y-Port

ALU

MQ

No

Right

Right

3-157

"2

16 10

Signed Multiply Iterate

Control/Data Signals

Signal

User

SSF

No

Inactive

SIOO

No

Passes LSB from ALU shifter to MSB of MQ shifter.

SIOl

No

SI02

No

SI03

No

Cn

Yes

Status Signals

en
2

-...I

~

»

(")

Use

Programmable

ZERO

N
OVR

C

-I
CO
CO

W
N

3-158

1 if result = 0
1 if MSB = 1

o
1 if carry-out

Should be programmed low

SMUll

SMULT

Signed Multiply Terminate

I7I0 I

FUNCTION
Performs the final iteration for computing an N-bit by N-bit signed product. An algorithm
for signed multiplication using this instruction is given in the "other Arithmetic
Instructions" section.

DESCRIPTION
SMUll checks the present multiplier bit (the least significant bit of the MOregister)
to determine whether the multiplicand should be added with the present partial product.
The instruction evaluates:
F

+-

R'

+ S + en

if the addition is required
if no addition is required

F-S

with the correct sign in the product.
A double precision right shift is performed. Bit 0 of the least significant byte of the
ALU shifter is passed to bit 7 of the most significant byte of the MO shifter.
The S bus should be loaded with the contents of an register file holding the previous
iteration result; the R bus must be loaded with the multiplicand. After executing SMUL T,
the Y bus contains the most significant half of the product, and MO contains the least
significant half.
Available R Bus Source Operands
C3-CO
RF

A3-AO

(A5-AO) Immed

DA-Port

..
A3-AO
Mask

Yes

No

Yes

No

Recommended S Bus Source Operands
RF
(B5-BO)
Yes

DB-Port
Yes

MQ
Register
No

Available Oestination Operands
RF

RF

(C5-CO) (B5-BO)
Yes

No

Shift Operations

Y-Port

ALU

MQ

No

Right

Right

3-159

I7 I0

Signed Multiply Terminate

Control/Data Signals

User

Signal
SSF

No

Inactive

5100

No

Passes lSB from AlU shifter to MSB of MQ shifter.

SI01

No

SI02

No

SI03

No

Cn

Yes

Status Signals
fJ)

Z
.....,

ZERO

N

~

OVR

l>

C

(")

Use

Programmable

-f

CO

(X)

W
N

3-160

1 if result = 0
1 if MSB = 1

o
1 if carry-out

Should be programmed low

SMULT

SNORM

Single· Length Normalize

I2I

0

I

FUNCTION
Tests the two most significant bits of the MQ register. If they are the same, shifts
the number to the left.

DESCRIPTION
This instruction is used to normalize a two's complement number in the MQ register
by shifting the number one bit position to the left and filling a zero into the LSB (unless
the SID input for that word is low). Data on the S bus is added to the carry, permitting
the number of shifts performed to be counted and stored in one of the register files.
The shift and the S bus increment are inhibited whenever normalization is attempted
on a number already normalized. Normalization is complete when overflow occurs.

N

Available R Bus Source Operands

RF

A3-AO

(A5-AO) Immed

DA-Port

('I)

C3-CO

CO
CO

..

u

~

«
~

A3-AO
Mask

No

No

No

"Z

No

(/)

Available S Bus Source Operands (Count)
RF
MO
DB-Port
(95-80)
Register
Yes

No

No

Available Destination Operands

Shift Operations

(Count)

(Conditional)

RF
RF
(C5-CO) (85-80)
Yes

No

Y-Port

ALU

MO

Yes

No

Left

3-161

I2 I0 I

Single-Length Normalize

SNORM

Control/Data Signals
User
Signal

Programmable

Use

SSF

No

Inactive

SIOO

No

Passes internally generated end-fill bit.

SiOT

No

SI02

No

SI03

No

Cn

Yes

Increments S bus (shift count) if set to one.

Status Signals
C/)

ZERO

:2
....,

N
OVR
C

~

l>

~

1 if result = 0

1 if MSB of MO register =
1 if MSB of MO register XOR 2nd MSB =
1 if carry-out = 1

CO EXAMPLE (assumes a 32-bit configuration)
CO

W
N Normalize the number in the MQ register. storing the number of shifts in register 3.
Instr

Op,d

Add,
Code
17-10
A5·AO
00100000 XX XXXX

Op,d

Op,d Sel

Add,

Add,
EB1·
EA EBO C5-CO
X 00
000011

B5·BO
000011

Dest

Destination Selects

VTe3.
WEo

SELRF1·

SELMO
SELRFO
10
0
0000

C5"EY3.
0eA Oeii 5EvO 0Es
X

X

XXXX

0

CF2·
Cn CFO
1 110

Assume register file 3 holds 00000003 (Hex) and MQ register holds 3699D84E (Hex).
Operand
Source

00110110 100110011101100001001110

I MO shifter

Destination

0110 1101 0011 0011 1011 0000 1001 1100

I MO register

+-

MO register

+-

MO shifter

Count
Source

00000000 0000 0000 0000 0000 0000 0011

Destination

0000 0000 0000 0000 0000 0000 0000 0100

3-162

S

+-

RF(3}

I RF(3}

+-

S + Cn

Arithmetic Right Single Precision Shift

SRA
FUNCTION

Performs arithmetic right shift on result of ALU operation specified in lower nibble of
instruction field.

DESCRIPTION
The result of the ALU operation specified in instruction bits 13-10 is shifted one bit
to the right. The sign bit of the most significant byte is retained unless it is inverted
as a result of overflow. Bit 0 of the least significant byte is dropped.
The shift may be made conditional on SSF. If SSF is high or floating, the shift result
will be sent to the Y MUX. If SSF is low, the ALU result will be passed unshifted to
the Y MUX .
• A list of ALU operations that can be used with this instruction is given in Table 15.

N

('I)

00
00

Shift Operations

IALU Shifter

MQ Shifter

(..)

Arithmetic Right

None

q,....

ct
2

Available Destination Operands (ALU Shifterl
RF

RF

(C5-CO)

(B5-BO)

Yes

No

en

Y-Port
Yes

Control/Data Signals
Signal

User

Use

Programmable

SSF

Yes

SIOO

No

SI01

Passes shifted output if high; passes ALU result
if low.
LSB is shifted out from each word, which may be

No

1, 2, or 4 bytes long depending on selected

SI02

No

configuration

SI03

No

Cn

No

Affects arithmetic operation specified in bits 13-10 of
instruction field.

3-163

I0 I*

Arithmetic Right Single Precision Shift

SRA

Status Signals t
ZERO

1 if result = 0

N

1 if MSB of result = 1

o if MSB of result
o

OVR

C

= 0

1 if carry-out condition

t C is ALU carry-out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR (overflow) is evaluated after ALU operation and after shift operation.

EXAMPLE (assumes a 32-bit configuration)

en
2!
-..J
~

:l=-

n
-f
co
co
tAl
N

Perform the computation A = (A + B)/2, where A and B are single-precision numbers.
Let A reside in register 1 and B be input via the DB bus.
Instr

Oprd

Oprd

Oprd Sel

Dest

Code

Addr

Addr

EB 1·

Addr

17-10

A5-AO

B5-BO

00000001

000001

XX XXXX

EA EBO
0

10

Destiaation Selects

C5-CO

SELMO

WE3WEc5

000001

o

0000

SELRF1·
SELRFO OEA OEB
lOX

X

0EY30EY0 0eS
XXXX

0

CF2·
Cn CFO
0

110

SSF
1

Assume register file 1 holds 6A08C618 (Hex) and DB bus holds 51007530 (Hex).
Source

0110101000001000110001100001 1000

I R .... RF(1)

Source

0101 0001 000000000111 0101 0011 0000

IS .... DB bus

Intermediate
Result

*

Destination

1011 1011 00001001 0011 1011 01001000

01011101100001001001110110100100

I ALU Shifter .... R + S + Cn
I RF(1) .... ALU shift result

tAfter the intermediate operation (ADD), overflow has occurred and OVR status signal is set high. When the
arithmetic right shift is executed. the sign bit is corrected (see Table 16 for shift definition notes).

3-164

SRAD

Arithmetic Right Double Precision Shift

1

FUNCTION
Performs arithmetic right shift on MQ register (LSH) and result of ALU operation (MSH)
specified in lower nibble of instruction field.

DESCRIPTION
The result of the ALU operation specified in instruction bits 13-10 is used as the upper
half of a double precision word, the contents of the MQ register as the lower half.
The contents of the ALU are shifted one bit to the right. The sign bit of the most
significant byte is retained unless the sign bit is inverted as a result of overflow. Bit 0
of the least significant byte in the ALU shifter is passed to bit 7 of the most significant
byte of the MQ register. Bit 0 of the MQ register's least significant byte is dropped.
The shift may be made conditional on SSF. If SSF is high or floating, the shift result
will be sent to the Y MUX. If SSF is low, the Al::U result will be passed unshifted to
the Y MUX.

('t)

~

l-

• A list of ALU operations that can be used with this instr~ion is given in Table 15.

(.)

«
~

Shift Operations

.....

ALU Shifter

2

MQ Shifter

C/)

Arithmetic Right Arithmetic Right
Available Destination Operands (ALU Shifter)
RF

RF

(C5-CO)

(B5-BO)

Yes

No

Y-Port
Yes

Control/Data Signals
Signal

N

User

Use

Programmable

SSF

Yes

Passes shifted output if high; passes ALU result

SIOO

No

LSB of ALU shifter is passed to MSB of MQ shifter,

SI01

No

and LSB of MQ shifter is dropped.

SI02

No

SI03

No

Cn

No

if low.

Affects arithmetic operation specified in bits 13-10 of
instruction field.

3-165

Arithmetic Right Double Precision Shift

SRAD

Status Signals t

ZERO

1 if result = 0

N

1 if MSB of result

1
0

OVR

o if MSB of result
o

C

1 if carry-out condition

t C is ALU carry-out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR(overflow) is evaluated after ALU operation and after shift operation.

EXAMPLE (assumes a 32-bit configuration)

en
2

~

Perform the computation A = (A + B)/2, where A and B are two's complement numbers.
Let A be a double precision number residing in register 1 (MSH) and MO (LSH). Let
B be a single precision number which is input through the DB bus.

~

»

(")

-i

(X)
(X)

~

Destination Selects

Instr

Oprd

Dest

Add,

Oprd
Add,

Oprd Sel

Code

EB1-

Add,

WE3-

17-10

A5-AO

B5-BO

EA EBO

C5-CO

SELMO WEO SELRFO

00010001

000001

XX XXXX

0

10

000001

0

0000

SELRF110

OEY3-

OEA OEB
X

X

CF2-

Offij

5ES

XXXX

0

Cn CFO

SS

110

1

0

Assume register file 1 holds 4A08C618 (Hex), and DB bus holds 51007530 (Hex),
and MOregister holds 17299AOF (Hex).
MSH

I R -- RF( 1)

Source

010010100000 1000 110001100001 1000

Source

0101 0001 000000000111 0101 0011 0000

Intermediate~
Result

1001 1011 00001001 0011 1011 0100 1000

Destination

01001101100001001001110110100100

Source

0001011100101001 1001 101000001111

MQ shifter

Destination

0000 10111001 0100 1100 1101 00000111

MQ register

I S -- DB bus
I AlU Shifter -- R + S + Cn
I RF(1) -- AlU shift result

LSH
<-

MQ register

<-

MQ shift result

tAfter the intermediate operation (ADD). overflow has occurred and OVR status signal is set high. When the
arithmetic right shift is executed, the sign bit is corrected (see Table 16 for shift definition notes).

3-166

SRC

Circular Right Single Precision Shift

FUNCTION
Performs circular right shift on result of ALU operation specified in lower nibble of
instruction field.

DESCRIPTION
The result of the ALU operation specified in instruction bits 13-10 is shifted one bit
to the right. Bit 0 of the least significant byte is passed to bit 7 of the most significant
byte in the same word, which may be 1, 2, or 4 bytes long depending on the selected
configuration.
The shift may be made conditional on SSF. If SSF is high or floating, the shift result
will be sent to the Y MUX. If SSF is low, the ALU result will be passed unshifted to
the Y MUX.

N

• A list of ALU operations that can be used with this instruction is given in Table 15.

('\')

Shift Operations

....
(.)

ALU Shifter

MQ Shifter

Circular Right

None

CO
CO

«
oct

"z

en

Available Destination Operands (ALU Shifter)
RF
(C5-CO)

RF
(B5-BO)

Y-Port

Yes

No

Yes

Control/Data Signals
Signal

User

Use

Programmable

SSF

Yes

Passes shift result if high; passes ALU result

5100

No

Rotates LSB to MSB of the same word, which may

5101

No

be 1, 2, or 4 bytes long depending on configuration

5102

No

5103

No

Cn

No

if low.

Affects arithmetic operation specified in bits 13-10 of
instruction field.

3-167

I8 I*

Circular Right Single Precision Shift

SRC

Status Signals t
ZERO

N

1 if result = 0
1 if MSB of result = 1

o if MSB of result
OVR

C

= 0

1 if signed arithmetic overflow
if carry-out condition

t C is ALU carry-out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation'. OVR (overflow) is evaluated after ALU operation and after shift operation.

EXAMPLE (assumes a 32-bit configuration)
Perform a circular right shift of register 6 and store the result in register 1.
CJ)

Z
....,
~

l>

("')

Instr

Code
17-10

Oprd
Addr

A5·AO
10000110 000110

Oprd
Addr
B5-BO
XX XXXX

Oprd Sel
EB1·
EA EBO
0

XX

Dest

Destination Selects

Addr
C5-CO
000001

SELMO
0

WE3.
WeO

SELRF1·

SELRFO
10
0000

om·

O'EA DEB 0eY0 0eS
X

X

XXXX

0

CF2Cn CFO SSF
0

~

CO Assume register file 6 holds 3788C618 (Hex).
CO

~

Source

0011 0111 1000 1000 110001100001 1000

Intermediate
Result

0011 0111 10001000110001100001 1000

Destination

0001 1011 1100010001100011 00001100

I R .... RF(6)
I ALU Shifter .... R + Cn
I RF(1)"'" ALU shift result

110

1

SRCD

Circular Right Double Precision Shift

FUNCTION
Performs circular right shift on MO register (LSH) and result of ALU operation (MSH)
specified in lower nibble of instruction field.

DESCRIPTION
The result of the ALU operation specified in instruction bits 13-10 is used as the upper
half of a double precision word, thecontents of the MO register as the lower half.
The contents of the ALU and MO shifters are rotated one bit to the right. Bit Oof the
least significant byte in the ALU shifter is passed to bit 7 of the most significant byte
of the MO shifter. Bit a of the least significant byte is passed to bit 7 of the most
significant byte of the ALU shifter.
The shift may be made conditional on SSF. If SSF is high or floating, the shift result
will be sent to the Y MXU and MO register. If SSF is low, the Y MUX and MO register
will not be altered.
• A list of ALU operations that can be used with this instruction is given in Table 15.

N
M

~

....
(J
~

.;:r
Shift Operations

"

Z

fn

ALU Shifter

MQ Shifter

Circular Right

Circular Right

Available Destination Operands (ALU Shifter)
RF

RF

(C5-CO)

(B5-BO)

Yes

No

Y-Port
Yes

Control/Data Signals
Signal
SSF

User

Use

Programmable
Yes

Passes shift result if high; passes ALU result and
retains MQ register if low.

SIOO

No

Rotates LSB of ALU shifter to MSB of MQ shifter,

SI01

No

and LSB of MQ shifter to MSB of ALU shifter

SI02

No

SI03

No

Cn

No

Affects arithmetic operation specified in bits 13-10 of
instruction field.

3-169

I9 I*

SHCD

Circular Hight Double Precision Shift

Status Signals t
1 if result = 0
1 if MSB of result =

ZERO

N

o if MSB of result

= 0
1 if signed arithmetic overflow

OVR

1 if carry-out condition

C

tc is ALU carry-out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR (overflow) is evaluated after ALU !lperation and after shift operation.

EXAMPLE (assumes a 32-bit configuration)
CI)

2
......

~

l>

n

-4

Perform a circular right double precision shift of the data in register 6 (MSH) and MQ
(LSH), and store the result back in register 6 and the MQ register.
Inst,
Code
17-10
10010110

Op,d
Add,
A5-AO
000110

Op,d
Op,d Sel
Dest
Destination Selects
Add,
Add,
EB1WEa- SELAF1B5-8O
C5-CO SELMQ WEo SELAFO 0eA Oeii 0eY0
EAE80
10
X
X
XXXX
XX XXXX 0 XX 00 0110
0
0000

om-

i5Es
0

CF2Cn CFO
0 110

00
00 Assume register file 6 holds 3788C618 (Hex) and MQ register holds 50A99AOF (Hex).
W
N
MSH

I
Intermediate
Result I
Source

Destination

0011 0111 0000 1000 1100 0110 0001 1000

'

0011 0111 0000 1000 1100 0110 0001 1000

1001 1011 10000100 0110 0011 00001100

I R'" RF(6)
I

ALU shifter'" R + Cn

I RF(6)'" ALU shift result

lSH

I
Destination I
Source

3-170

0101 0000 ;010 1001 1001 10100000 1111

MQ shifter'" MQ register

001010000101 0100 1100 1101 0000 0111

MQ register ... MQ shift result

Logical Right Single Precision Shift

SRL
FUNCTION

Performs logical right shift on .result of ALU operation specified in lower nibble of
instruction field.

DESCRIPTION
The result of the ALU operation specified in instruction bits 13-10 is shifted one bit
to the right. A zero is placed in the bit 7 of the most significant byte of each word
unless the SIO input for the word is programmed low; this will force the sign bit to
one. The LSB is dropped from the word, which may be 1, 2, or 4 bytes long depending
on selected configuration.
The shift may be made conditional on SSF. If SSF is high or floating, the shift result
will be sent to the Y MUX. If SSF is low, the ALU result will be passed ul1shifted to
the Y MUX.

N

C")

00
00
l-

* A list of ALU operations that can be used with this instruction is given in Table 15.

e.)



0

10

Destination Selects

WE3-

SELRF1SELRFO OEA

C5-CO

SELMa

Wfij

XX XXXX

1

XXXX

XX

x

0Ev30eB 0eY0 DeS

x

XXXX

0

-t

CF2Cn CFO
1

110

CO Assume register file 1 holds 15008400 (Hex) and DB bus holds 4900C350 (Hex).
CO
Source

00010101000000001000010011010000

I R -- RF(l)

Source

01001001 00000000 11000011 0101 0000

Is+- DB bus

Destination

0011 0100000000000011 111010000000

I

~

3-178

MQ register

+- R'

+ S + en

Subtract S with Carry (R + S' + Cn)

SUBS

*

I3

FUNCTION
Subtracts data on the S bus from R with carry.

DESCRIPTION
Data on the S bus is subtracted with carry from data on the R bus. The result appears
at the ALU and MQ shifters.
'The result of this instruction can be shifted in the same microcycle by specifying a shift instruction in the
upper nibble (17-14) ofthe instruction field. The result may also be passed without shift. Possible instructions
are listed in Table 15.

Available R Bus Source Operands
C3-CO
RF
A3-AO
(A5-AO) Immed

DA-Port

..
A3-AO
Mask

Yes

Yes

No

No

Available S Bus Source Operands
RF
MQ
DB-Port
(B5-BO)
Register
Yes

Yes

Yes

Available Destination Operands
RF

RF

(C5-CO) (B5-BO)
Yes

No

Y-Port
Yes

ALU

MQ

Shifter

Shifter

Yes

Yes

Control/Data Signals
Signal

User

Use

Programmable

SSF

No

Affect shift instructions programmed in bits 17-14 of

SIOO

No

instruction field.

SIOl

No

SI02

No

Si03

No

Cn

Yes

Two's complement subtraction if programmed high.

3-179

I* I3
Status Signals t
ZERO

N

+ S' + Cn)

Subtract S with Carry (R

SUBS

,

if result = 0
1 if MSB = 1
if signed arithmetic overflow

OVR

if carry-out

C

tc is ALU carry-out and is evaluated before shift operation. ZERO and N (negative) are evaluated
after shift operation. OVR (overflow) is evaluated after ALU operation and after shift operation.

EXAMPLE (assumes a 32-bit configuration)
Subtract data on the DB bus from data in register 1, and store the result in the MQ
register.
CJ)

2
....,
~

»

n

-t

00
00

Instr

Oprd

Oprd

Oprd Sel

Dest

Code

Addr

Addr

EB1·

Addr

17-10

A5-AO

B5-BO

1110 0011

00 0001

XX

EA EBO

xxxx a

10

C5-CO

xx

XXXX

Destination Selects
SELMa

WEO

1

XXXX

SELRFO OEA

XX

CF2-

OEY3-

WE3· SELRF1·

x

OEB 5EYo 5ES

x

XXXX

0

Cn CFO
1

110

Assume register file 1 holds 150084DO (Hex) and DB bus holds 4900C350 (Hex).
Source

000101010000 0000 1000 0100 11010000

I R +- RF(1)

Source

0100 1001 0000 0000 1100 0011 0101 0000

Is+- DB bus

Destination

1100 1011 1111 1111 1100 0001 1000 0000

MQ register

W
N

3-180

+- R +

S' + Cn

TBO

Test Bit (Zero)

I 31 81

FUNCTION
Tests bits in selected bytes of 5-bus data for zeros using mask in C3~CO::A3-AO.

DESCRIPTION
The 5 bus is the source word for this instruction. The source word is passed to the
ALU. where it is compared to an 8-bit mask. consisting of a concatenation of the C3-CO
and A3-AO address ports (C3-CO::A3-AO). The mask is input via the R bus. The test
will pass if the selected byte has zeros at all bit locations specified by the ones of
the mask. Bytes are selected by programming th~ 510 inputs low. Test results are
indicated on the ZERO output. which goes to one if the test passes. Register write
is internally disabled during this instruction.
'
Available R Bus Source Operands
C3-CO
RF

A3-AO

(A5~AO)

Immed

No

No

DA-Port

..
A3-AO
Mask

No

Yes

Available S Bus Source Operands
RF
MG
DB-Port
(B5-80)
Register
Yes

Yes

Yes

Control/Data Signals
Signal

User
Programmable

Use

SSF

No

SIOO

Yes

Inactive
Byte Select

SiOT
Si'02

Yes

Byte Select

Yes

8yte SeleCt

SI03

Yes

Byte Select

Cn

No

Inactive

3-181

I3 I8

Test Bit (lero)

TBO

Status Signals
1 if result (selected bytes)

ZERO

Pass

o

N

OVR
0
C =,0

EXAMPLE (assumes a 32-bit configuration)
Test bits 7, 6 and 5 of bytes 0 and 2 of data in register 3 for zeroes.

CJ)

:2
"

~

Instr

Mask

Oprd

Oprd Sel

Mask

Code

ILSH)

Addr

EB1,

IMSHI

17-10

A3-AO

B5-BO

00111000

0000

00 0011

Destination Selects

WE3- SELRF1-

EA EBO

C3-CO

SELMa

WEe

00

1110

X

xxxx

X

om-

0EY0 0Es en
x xxxx a x

SELRFO OEA DEB

xx

x

CF2CFO

Si03- 'iEs'iOOSiOo iEsiOo

110 lOla

Assume register file 3 holds 881 CD003 (Hex).

~

Source

11100000 11100000 11100000 11100000

IR

Source

10001000000111001101000000000011

I

+-

Mask (C3-CO::A3-AO)

-i

(X)

~

SN

+-

RF(3)n t

N
Output
tn

3-182

nth byte

[2]

ZERO

+-

1

0000

Test Bit (One)

TB1

I 2 I 81

FUNCTION
. Tests bits in selected bytes of S~bus data for ones using mask in C3cCO::A3~AO.

DESCRIPTION
The S busis the source word for this instruction. The source word is passed to the
ALU, where it is compared to an a-bit mask, consisting of a concatenation of the C3-CO
and A3-AO address ports (C3-CO::A3-AOI. The mask is input via the R bus;.The test
will pass if the selected byte has ones at all bit locations specified by the ones· of the
mask. Bytes are selected by programming the 510 inputs low. Test results are indicated
On the ZERO output, which goes to. one if the test passes. Register write is internally
disabled for this instruction.
Available RBus Source Operands
C3-CO
RF

A3-AO ..

(A5~AO)

Imrned

No

No

.

DA-Port

No

..
A3-AO
Mask
Yes

Available SBu, Source Operands
RF
(B5-BOI
Yes

DB-Port

MQ
Register

Yes

Yes

Control/Dat.a Signals
Signal

User
Programmable

SSF
5100
5101
5102 .

Yes
Yes

~

en

No

, Use
Inactive
Byte Select

Yes

Byte Select
Byte Select

Yes
No

Inactive

Byte Select

12 18

Test Bit (One)

TB1

Status Signals

ZERO

1 if result (selected bytes)

Pa'ss

o
o
o

N
OVR
C

EXAMPLE (assumes a 32-bitconfiguration)
Test bits 7, 6 and 5 of bytes 1 and 2 of data in register 3 for ones.

en
2

-...I

~

Instr

Mask

Oprd

Oprd Sel

Mask

Code

ILSHI

Addr

EB1-

IMSHI

17-10

A3-AO

B5-BO

EA EBO

C3-CO

00101000

0000

000011

X 00

1110

Destination Selects
SELRF1-

OEY3-

SELMQ

WE3WeO

SELRFO

0eA DEs 0EY0

X

XXXX

XX

X

X XXXX

CF2- 5103OES Cn CFO
0

5100

X 110 1001

Assume register file 3 holds 881CF003 (Hex).

l>

(")

Mask

11100000 11100000 11100000 1110 0000

I Rn

<-

Mask (C3-CO::A3-AO)

Source

1000 1000 0001 1100 1101 0000 0000 0011

I Sn

<-

RF(3)n t

-f

(X)
(X)

W
N

Output
tn

3-184

nth byte

G

ZERO

<-

0

iES'iO:iiESiOo
0000

UDIVI

Unsigned Divide Iterate

IcI0 I

FUNCTION
Performs one of N-2 iterations of nonrestoring unsigned division by a test subtraction
of the N-bit divisor from the 2N-bit dividend. An algorithm using this instruction can
be found in the "Other Arithmetic Instructions" section.

DESCRIPTION
UDIVI performs a test subtraction of the divisor from the dividend to generate a quotient
bit. The test subtraction may pass or fail and is corrected in the subsequent instruction
if it fails. Similarly a failed test from the previous instruction is corrected during
evaluation of the current UDIVI instruction (see the "Other Arithmetic
Instructions" section for more details).
The R bus must be loaded with the divisor,the S bus with the most significant half
of the result of the previous instruction (UDIVI during iteration or UDIVIS at the
beginning of iteration). The least significant half of the previous result is in the MQ
register.
UDIVI checks the result of the previous pass/fail test and then evaluates:

F-R+S
F - R' + S +

en

N
M
CO
CO

IU


,J:I.

n
.....

(X)
(X)

W
N

Signal

Programmable

Use

SSF

No

Inactive

SIOO

No

Passes internally generated end-fill bit.

SiOT
'Si'52

No
No

5103

No

Cn

Yes

Status Signals
ZERO
N

OVR

C

3-186

1 if result = 0

o
o
1 if carry-out

Should be programmed high.

UDiVI

UDIVIS

Unsigned Divide Start

IBI0 I

FUNCTION
Computes the first quotient bit of nonrestoring unsigned division. An
algorithm using this instruction is given in the "Other Arithmetic Instructjions" section.

DESCRIPTION
UDIVIS computes the first quotient bit during nonrestoring unsigned division by
subtracting the divisor from the dividend. The resulting remainder due to subtraction
may be negative; the subsequent UDIVI instruction may have to restore the remainder
during the next operation.
The R bus must be loaded with the divisor and the S bus with the most significant
half of the remainder. The result on the Ybus should be loaded back into the register
file for use in the next instruction. The least significant half of the remainder is in the
MO register.

~

UDIVIS computes:

00
00

F

+-

R'

IU

+ S + Cn

«

A double precision left shift is performed; bit 7 of the most significant byte of the ~
MO shifter is transferred to bit 0 of the least significant byte of the ALU shifter. Bit 7 I '
Z
of the most significant byte of the ALU shifter is lost. The unfixed quotient bit is
circulated into the least significant bit of the MO shifter.

en

Available R Bus Source Operands
C3-CO
RF

A3-AO

(AS-AO) Immed

DA-Port

..
A3-AO
Mask

Yes

No

Yes

No

Recommended S Bus Source Operands
RF
(85-80)
Yes

DB-Port
Yes

MQ
Register
No

Recommended Destination Operands Shift Operations
RF
RF
(C5-CO) (85-60)
Yes

No

Y-Port

ALU

MQ

Yes

Left

Left

3-187

IBID

Unsigned Divide Start

Control/Data Signals
Signal

User

Use

Programmable

SSF
SIOO

No

Inactive

No

Passes internally generated end-fill bit.

SI01

No

SI02

No

SI03

No

en

Yes

Should be programmed high.

Status Signals
ZERO

N
OVR

C

3-188

1 if intermediate result = 0

o
if divide overflow
1 if carry-out

UDIVIS

UDiVIT

Unsigned Divide Terminate

F

I0 I

FUNCTION
Solves the final quotient bit during nonrestoring unsigned division. An algorithm using
this instruction is given in the "Other Arithmetic Instructions" section.

DESCRIPTION
UDIVIT performs the final subtraction of the divisor from the remainder during
nonrestoring signed division. UDIVIT is preceded by N-l iterations of UDIVI, where
N is the number of bits in the dividend.
The R bus must be loaded with the divisor, the S bus must be loaded with the most
significant half of the result of the last UDIVI instruction. The least significant half
lies in the MO register. The Y bus result must be loaded back into the register file for
use in the subsequent DIVRF instruction.

N

UDIVIT checks the results of the previous pass/fail test and evaluates:
Y+-R+S
Y +- R' + S +

en

M
CO
CO

if the test is failed
if the test is passed

.....

()

The contents of the MO register are shifted one bit to the left; the unfixed quotient
bit is circulated into the least significant bit.



(")

ZERO
N

OVR

C

-4

00
00
CtJ

N

3-190

1 if intermediate result = 0

o
o
1 if carry-out

UMULI

Unsigned Multiply Iterate

o o

FUNCTION
Performs one of N unsigned multiplication iterations for computing an N-bit by N-bit
product. An algorithm for unsigned multiplication using this instruction is given in the
"Other Arithmetic Instructions" section.

DESCRIPTION
UMULI checks to determine whether the multiplicand should be added with the present
partial product. The instruction evaluates:
F -

R + S + Cn

F-S

if the addition is required
if no addition is required

A double precision right shift is performed. Bit 0 of the least significant byte of the
ALU shifter is passed to bit 7 of the most significant byte of the MQ shifter; carry-out
is passed to the most significant bit of the ALU shifter.
The S bus should be loaded with the contents of an accumulator and the R bus with
the multiplicand. The Y bus result. should be written back to the accumulator after
each iteration of UMULI. The accumulator should be cleared and the MQ register loaded
with the multiplier before the first iteration.

N

('I)

CO
CO

IU



EPIC is a trademark, of Texas In$tr.um,ents,-Incorporated


::j
0
Z

TEXAS .."

4-6

(E141

MASTER/SLAVE

110

OBO

."

DB REG

V PORT

(G131

OAO

z
nm

OA REG

V PORT
PARITV

C

<

PAR
STAT

(F15)

l>
l>

(BSI
(aSI
(C15)

OA PORT

IN STR.UMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

0

•••

31

•••

VO

Y31

SN74ACT8836
32-BIT BY 32-BIT MULTIPLIER/ACCUMULATOR

functional block diagram (positive logic)

SGNEXT
SELO

PA3-PAO +---I-c.;4:......-+-_ _ _-f
PB3-PBO +-_-f'-4_ _-f-_ _ _-I
PERRA
PERRB

2

SFT1-SFTO

-+------+-----'

+----+------'--'
2
32

SELREG
WEMS
WElS

32

OA31-0AO +-_+3:;.:2=-._._-----.

32

CKEA~----~----_f---;--I

OB31-0BO
CKEB

II

CKEI+---t--I
EA+---t----+------~

1------++-+ EB

'---.---'

CD
M
00
00

OASGN
OBSGN
RND1-RNDO

' - - - - - - - - - - 1 MULTIPLIER/ADDER STAGE 1

ACC1-ACCO

I-

o

PIPEliNE REGISTER

COMPL


C

MSERR PY 3-PYO

TEXAS.~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265



o

<

l>
2:

(")

m

-

2:
"T1

o

:xJ

3:

l>

o

-I

PIN
NAME
V8
Yl0
Yll
Y13
Y14
Y16
Y18
Y19
Y21
Y23
Y25
Y27
Y28
Y30
PYl
Y2
Y6
SElY
Y7
Y9
Y12
Y17
Y20
Y26
Y29
Y31

NO.
812
B13
B14
815
Cl
C2
C3
C4
C5
C6
C7
C8
C9
Cl0
Cll
C12
C13
C14
C15
Dl
02
D3
D7
D8
D9
013

PIN
NAME
YETPl
YETPO
YETP2
PY3
YO
Y4
EB
Y5
VCC
GND
Y15
GND'
Y22
GND
VCC
CKEY

OEY
ACCD
PERRY
WEMS
TPl
TPD
GND
VCC
Y24
ACCl

NO.
014
015
El
E2
E3
E13
E14
E15
Fl
F2
F3
F13
F14
F15
Gl
G2
G3
G4
G12
G13
G14
G15
Hl
H2
H3
H4

PIN
NAME
PYD
ETPERR
SElREG
Y3
GNO
GND
PY2
RNDl
SFTO
Yl
GND
GND
MSERR
DASGN
SELD
SGNEXT
WElS
SFTl
RNDO
DBSGN
CKEI
FTl
ClK
CKEli
DBD
DBl

NO.
H12
H13
H14
H15
Jl
J2
J3
J4
J12
J13
J14
J15
Kl
K2
K3
K13
K14
K15
II

l2
l3
l13
l14
l15
Ml
M2

PIN
NAME
CDMPl
FTO
EA
CKEA
082
DB3
DB5
OB7
DA26
DA24
DA30
DA31
DB4
DB9
DBll
DA22
DA28
DA29
DB6
D815
DB13
DA18
DA20
DA27
DB8
DB17

2:

TEXAS.

4-8

INSTRUMENTS
POST OFFICE BOX' 655012· DALLAS, TEXAS 75265

PIN
NO.
M3
M7
M8
Ml0
M13
M14
M15
Nl
N2
N3
N4
N5
N6
N7
N8
N9
Nl0
Nll
N12
N13
N14
N15
Pl
P2
P3
P4

NAME
OB18
PBl
PAD
OA6
DA16
DA17
DA25
DB10
DB19
DB20
DB21
DB23
DB27
VCC
GND
DAD
DA4
DA10
DA13
DA15
DA19
DA23
DB12
D816
DB24
DB22

NO.
P5
P6
P7
P8
P9
Pl0
Pl1
P 12
P13
P14
P 15
Rl
R2
R3
R4
R5
R6
R7
R8
R9
Rl0
Rl1
R12
R13
R14
R15

PIN
NAME
OB25
DB29
OB31
PERRA
PA2
DA2
DA8
DA12
DA14
DAll
DA21
DB14
0826
0828
DB30
PBO
P82
P83
PERRB
PAl
PA3
DAl
DA3
DA5
DA7
DA9

SN74ACT8836
32·BIT BY 32·81T MULTIPLIER/ACCUMULATOR

PIN
NAME

NO.

ACCO
ACCl
CLK

C14
013
Hl
H15
H2

CKEA
CKEB

G14

110

DESCRIPTION

I

Accumulate mode opcode (see Table 2)

I
I
I

System clock

CKEI
CKEY

C12

I
I

COMPL

H12

I

DAO
DAl
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DAlC
DAll
DA12
DA13
DA14
DA15
DA16
DA17
DA18
DA19
DA20
DA21
DA22
DA23
DA24
DA25
DA26
DA27
DA28
DA29
DA30
DA31

N9
Rll
Pl0
R12
Nl0
R13
Ml0
R14
Pll
R15
Nll
P14
P12
N12
P13
N13
M13
M14
L13
N14
L14
P15
K13
N15
J13
M15
J12
L15
K14
K15
J14
J15

DASGN

F15

I

Clock enable for A register, active low
Clock enable for B register, active low
Clock enable for I register, active low
Clock enable for Y register, active low

Product complement control; high complements multiplier result, low passes multiplier unaltered
to accumulator,

DA port input data bits 0 through 31

2:

o

i=

C


C

~

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265

4-11

SN74ACT8836
32-BIT BY 32-BIT MULTIPLIER/ACCUMULATOR

PIN

III
CJ)

z

......
~

»
(")
-I

co
co
w

0)

l>

c
<

NAME
YO
Yl
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Yll
Y12
Y13
Y14
YI5
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
YETPO
YETPI
YETP2

NO.
Cl
F2
Bl
E2
C2
C4
B2
B4
Al
B5
A2
A3
B6
A4
A5
C7
A6
B7
A7
A8
88
A9
C9
Al0
D9
All
B9
A12
A13
Bl0
A14
811
B13
B12
B14

DESCRIPTION

110

110

1/0

Y port data bus. Outputs data from Y register (OEY :::; L); inputs data to master/slave comparator

(OEY = HI.

Data bus for extended precision product. Outputs three most significant bits of the 67-bit multiplier
core result; inputs external data to master/slave comparator.

TABLE L INSTRUCTION INPUTS

l>
2

Signal
DASGN

Identifies DA Input data as two's complement

--n2m

DBSGN

Identifies DB input data as two's complement

Identifies DB input data-as unsigned

RNDO

Rounds integer result

Leaves integer result unaltered

ANDI

Rounds fractional result

Leaves fractional result unaltered

COMPL

Complements the product from the multiplier

Passes the product from the multiplier to the

o

o
:lJ
3:
l>
:::!
o

ACCO
ACCI

High

Low
Identifies DA input data as unsigned

before passing it to the accumulator

accumulator unaltered

See Table 2

See Table 2

2

TEXAS . "
4-12

INSTRUMENTS
POST OFfiCE BOX 655012 ._ DALLAS, TEXAS 75265

SN74ACT8836
32-BIT BY 32-BIT MULTIPLIER/ACCUMULATOR
TABLE 2. MULTIPLIER/ADDER CONTROL INPUTS
Operation

ACC'

ACCO

EA

EB

0

0

X

X

±(R x 51 + 0
±(R x 51 + ACC

Ace

0

1

X

X

1

0

X

X

± (R x 51 - ACC

1

1

0

0

±1 x 1 + 0

1

1

0

1

± 1 x DB + 0

1

1

1

0

±DA x 1 + 0

1

1

1

1

±DA x DB + 0

is the data stored in the accumulator

TABLE 3. SHIFTER CONTROL INPUTS
SFT,

SFTO

L

L

Pass data without shift

Shifter Operation

L

H

H

L

Shift one bit left; fill with zero
Swap upper and lower halves of temporary register

H

H

Shift 32 bits right; fill with sign bit

TABLE 4. FLOWTHROUGH CONTROL INPUTS
Control Inputs

Registers Bypassed

FTO

Pipeline

L

L

Yes

L

H
L

Yes

No

No

No

H

Yes

Ves

No

No

No

H

H

No

No

No

No

No

FTl

V

I

A

B

Yes Yes Ves Yes
No

TABLE 5. TEST PIN CONTROL INPUTS
Operation

TP'
L

TPO
L

All outputs and II0s ,forced low
All outputs and liDs forced high

L

H

H

L

All outputs placed. in a high impedance state

H

H

Normal operation (default state)

z

o

data flow
Two 32-bit input data ports, DA and DB, are provided for input of the multiplicand and multiplier to registers
A and B and the multiplier/adder. Input data can be clocked to the A and B registers before being passed
to the multiplier/adder if desired. Two multiplexers, RandS; in conjunction with a flowthrough decoder
select the multiplier operands from DA and DB inputs, A and B registers, or the temporary register. Data
is supplied to the temporary register from a shifter that operates on external DA/DB data or a previous
multiplier/adder result. The 67-bit multiplier/adder result can be output through the Y port or passed through
the shifter to the accumulator.
External DA and DB data is also available to the accumulator via the shifter. This 64-bit data can be extended
with zeros or the sign bit. The 64 least significant bits from the shifter may also be latched in the 64-bit
temporary register and input to the multiplier through the Rand S multiplexers. Aswap option allows the
most significant and least significant 32-bit halves of temporary register data to be swapped before being
. made availahle to the Rand S multiplexers .. This aflows either 32-bit half of the temporary register to be
used as a multiplier.

le::(
~

a:
o
LL
Z
W

(,)

Z

~

C

e::(

~

TEXAS
INSTRUMENTS
POST OFFICE

~ox

655012· DALLAS, TEXAS

7526~

4-13

SN74ACT8836
32·BIT BY 32·BIT MULTIPLIER/ACCUMULATOR
architectual elements
Included in the functional block diagram of the 'ACT8836 are the following blocks.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
•

~

Two 32-bit registered input data ports DA and DB
A parity checker at tile DA and DB inputs
An instruction decoder (I register)
A flowthrough decoder that permits selected registers to be bypassed to support up to three
levels of pipelining
Rand S multiplexers to select operands for the multiplier/ adder from DA and DB inputs, registers
A and B, or temporary register
A 0 multiplexer th~t selects the operand for the shifter from the 67 -bit sign-extended DA and
DB inputs or the multiplier/adder output
A shifter block that operates on DA/DB input data or on multiplier/adder outputs for scaling or
Newton-Raphson division
A Y output multiplexer that selects the most significant half or the least significant half of the
multiplier/ adder result for output at the registered Y port
An extended precision error check that tests for overflow
A master/slave comparator and parity generator/comparator at the Y output port for master/slave
and parity checking
Registers at the external data and instruction input ports and the shifter and multiplier/adder
output port to support pipe-lining

input data parity checker
An even-parity check is performed on each byte of input data at the DA, DB and Y ports. If the parity
test fails for any byte, a high appears at the parity error output pin (PERRA for DA data, PERRB for DB
data, PERRY for Y data).

A and B registers
Register A can be loaded with data from the DA bus, which normally holds a 32-bit multiplicand. Register
B is loaded from the DB bus which holds a 32-bit multiplier. Separate clock enables, CKEA and CKEB, allow
the registers to be loaded separately. This is useful when performing double precision multiplication or
using the temporary register as an input to the multiplier/adder. The registers can be made transparent
using the FT inputs (see Table 4).

instruction register

:t>

C

<
:t>

:2

om
:2

-n

o

::n

s:

-o~

Instruction inputs to the device are shown in Table 1. These signals control signed, unsigned, and mixed
multiplication modes, fractional and integer rounding, accumulator operations and complementing of
products. They can be latched into instruction r,egister I when clock enable CKEI is low.
Sign control inputs DASGN and DBSGN identify DA and DB input data as signed (high) or unsigned (low).
Rounding inputs RNDO and RND1 control rounding operations in the multiplier/adder. A low on these inputs
passes the results unaltered. If a high appears on RND 1, the result will be rounded by adding a one to
bit 30. RND 1 should be set high if the multiplier/adder result is to be shifted in order to maintain precision
of the least significant bit following the shift operation. If a high appears on RNDO, the result will be rounded
by adding a one to bit 31. This code should be used when the adder result will not be shifted.
A complement control, COMPL, is used to complement the product from the muliplier before passing it
to the accumulator. The complement will occur if COMPL is high; the product will be passed unaltered
if COMPL is low.
ACC1-ACCO control the operation of the multiplier/adder. Possible operations are shown in Table 2.

:2

'111

4-14

TEXAS
INSTRUMENTS
POST, OFFICE BOX 655012 • DALLAS, TEXAS 75265

SN74ACT8836
32·BI1 BY 32·BIT MULTIPLIER/ACCUMULATOR

PA3·PAO
PB3·PBO
PERRA
PERRB

4
4
32

32

r---e~~3:.:;2"DB31.DBO

DA31·DAO

I-++-..... CKEB

CKEA

~---~--+EB

EA~-+---~------~

DASGN
DBSGN

~--~-----I

MULTIPLIER/ADDER STAGE 1

RND1·RNDO
COII(IPL
ACC1·ACCO

PIPELINE REGISTER

co

MULTIPLIER/ADDER STAGE 2

67

M
00
00

....
«
oq-

INPUT REGISTERS AND PARITY CHECK

(,)

I, S, and swap multiplexers
The Rand S multiplexers select the multiplier/adder operands from external data or from the temporary
register.
When EA is low, the R multiplexer selects data from the swap multiplexer. When EA is high, the R multiplexer
selects data from DA or the A register, depending on the state of the flowthrough control inputs (see
Table 4). When EB is low, the S multiplexer selects data from the swap multiplexer. When EB is high, the S
multiplexer switches data from DB or the B register, depending on the state of the flowthrough control inputs.
EA and EB are also used in conjunction with the multiplier/adder control inputs to force a numeric one
on the R or S inputs (see Table 2).
The swap multiplexers are controlled by the shifter control inputs. When SFT1 is high and SFTO is low,
the most significant half of the temporary register is available to the S multiplexer, and the least significant
half is available to the R multiplexer. When SFT1-SFTO are set to other values, the most significant half
of the temporary register is available to the R multiplexer, and the least significant half is available to the
S multiplexer.

"Z

(J)

2:

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a::
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2:

w

lultiplier/adder
The multiplier performs 32-bit multiplication and generates a 67-bit product. The product can be latched
in the pipeline to increase cycle speed. The product is complemented when COMPL is set high as shown
in Table 1. The adder computes the sum or the difference of the accumulator and the product and gives
a 67-bit sum. Bits 66-64 are used for overflow and sign extension.

(.)

2:

c:(

>

·0
c:(

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4-15

SN74ACT8836
32·BIT BY 32·BIT MULTIPLIER/ACCUMULATOR

o multiplexer
The D multiplexer selects input data fot the shifter. Two sources are available to the multiplexer: a 64-bit
word formed by concatenating DA and DS bus data, and the 61-bit sum from the multiplier/adder. IfSELD
is high, external DA/DS data is selected; if SELD is low, the sum is selected.
If the 64-bit word is selected for input to the shifter, three bits are added to the word based on the state
of the sign extend signal (SGNEXT). If SGNEXT is low, bits 66-64 are zero-filled; if SGNEXT is 'high, bits
66-64 are filled with the value on DA31.

temporary register and accumulator (Figure 11
Output from the shifter will be stored in the temporary register if SELREG is high and in the accumulator
register if SELREG is low. The 64-bit temporary register can be used to store temporary data, constants
and scaled binary fractions.
Separate clock controls, WELS and WEMS, allow the most significant and least significant halves of the
shifter output to be loaded separately. The 32 least significant bits of the selected register are loaded when
WELS is low; the most significant bits when WEMS is low. When WELS and WEMS are both low, the
entire word from the shifter is loaded into the selected register.

y

III

\

en
z
.....

I

»

1

1'67

~

I

-f

(X)
(X)

32

OA31-0AO
CKEA

l>

..f'67

I
I

REGtsTER

\

A MUX /

,2

II
,i

ACCUMULATOR

WAPI
MV!/

T

I

I

0831·080
S
REGISTER

I

\

'\ R MUX /

SMUX /

-2:

MULTIPLIERIAOOER STAGE 1
PIPELINE REGISTER

."

MULTIPUERIAOOER STAGE 2

0

67

XI

T

s:

FIGURE 1. TEMPORARY REGISTER AND ACCUMULATOR

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0
2:

TEXAS •
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II

r--

r=r

---,

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

SELREG
WEMS
WELS

32

T

m

SFT1-SFTO

32

\SMUXJ

-~

EA

I

l

32

I

C

n

~~
MUX

32

/2

(67

TEMPORARY

-!'32

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SHIFTER

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SELO

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SN74ACT8836
32·BIT BY 32·BIT MULTIPLIER/ACCUMULATOR
shifter
The shifter can be used to multiply by two for Newton-Raphson operations or perform a 32-bit shift for
double precision multiplication. The shifter is controlled by two SFT inputs, as shown in Table 3.

Y register
Final or intermediate multiplier/adder results will be clocked into Y register when CKEY is low.
Results can be passed directly to the Y output multiplexer using flowthrough decoder signals to bypass
the register (see Table 4).

Y multiplexer and Y output multiplexer
The Y multiplexer allows the 64-bit result or the contents of the Y register to be switched to the Y bus,
depending upon the state of the flowthrough control outputs. The upper 32 bits are selected for output
when the Y output multiplexer control SEL Y is high; the lower 32 bits are selected for output when SEL Y
is low. Note that the Y output multiplexer can be switched at twice the clock rate SO that the 64-bit result
can be output in One clock cycle.

flowthrough decoder
To enable the device to operate in pipelined or flowthrough modes, on-chip registers can be bypassed using
flowthrough control signals FT1 and FTO. Up to three levels of pipeline can be supported, as shown in . .
Table 4.
...

MULTIPLIER/ADDER STAGE 1

PIPELINE REGISTER
MULTIPLIER/ADDER STAGE 2

FT1·FTO

~----------~~~~t-------------------~CKEY

~------------------~SELY

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Y31·YO

FIGURE 2. Y OUTPUT

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4-17

SN74ACT8836
32-BIT BY 32-BI1 MULTIPLIER/ACCUMULATOR
Y

~-------------------4-CKEY

REGISTER

~------------------~SELY

PERRY

OEY~-------------------r~~1------t--+-------~

•
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z

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~

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ETPERR YETP2-YETPO

Y31-YO

MSERR PY3-PYO

FIGURE 3_ OUTPUT ERROR CONTROL

extended precision check
Three extended product outputs, YETP2-YETPO, are provided to recover three bits of precision during
overflow. An extended precision check error signal (ETPERR) goes high whenever overflow occurs. If sign
controls OASGN and OBSGN are both low, indicating an unsigned operation, the extended precision bits
66-64 are compared for equality. Under all other sign control conditions, bits 66-63 are compared for
equality.

~

00 master slave comparator
00

W

0)

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C

~
2

(")

m

:2
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3:

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::::t

A master/slave comparator is provided to compare data bytes from the Y output multiplexer with data
bytes on the external Y port when OEY is high. A comparison of the three extended precision bits of the
multiplier/adder result or Y register output with external data in the YETP1-YETPO port is performed
simultaneously. If the data is not equal, a high signal is generated on the master slave error output pin
(MSERR). A similar comparison is performed for parity using the PY3-PYO inputs. This feature is useful
in fault-tolerant design where several devices vote to ensure hardware integrity.

test pins
Two pins, TP1-TPO, support system testing. These may be used, for example, to place all outputs in a
high-impedance state, isolating the chip from the rest of the system (see Table 5),

data formats
The 'ACTBB36 performs single-precision and double-precision multiplication in two's complement, unsigned
magnitude, and mixed formats for both integer and fractional numbers.
Input formats for the multiplicand (R) and multiplier (S) are given below, followed by output formats for
the fully extended product. The fully extended product (PROT) is 67 bits wide. It includes the extended
product (XTP) bits YETP1-YETPO, the most significant product (MSP) bits Y63~Y32, and the least significant
product (LSP) bits Y31-YO.

o
2

~

4-18

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SN74ACT8836
32-BIT BY 32-BIT MULTIPLIER/ACCUMULATOR

This can be represented in notational form as follows:
PRDT

XTP : : MSP : : LSP

PRDT

YETP2 - YETPO : : Y63 - YO

or
Table 6 shows the output formats generated by two's complement, unsigned and mixed-mode
multiplications.

TABLE 6. GENERATED OUTPUT FORMATS
Two's Complement

Unsigned Magnitude

Two's Complement

Two's Complement

Two's Complement

Unsigned Magnitude

Two's Complement

Unsigned Magnitude

examples
Representative examples of single-precision multiplication, double-precision multiplication, and division using
Newton-Raphson binary division algorithm are given below.

single-precision multiplication
Microcode for the multiplication of two signed numbers is shown in Figure 1. In this example, the result
is rounded and the 32 most significant bits are output on the Y bus. A second instruction (SEL Y = 0)
would be required to output the least significant half if rounding were not used.
Unsigned and mixed mode single-precision multiplication are executed using the same code. (The sign
controls must be modified accordingly.) Following are the input and output formats for signed, unsigned,
and mixed mode operations.

II

Two's Complement Integer Inputs
Input Operand B

'nput Operand A
31

30

29

_231

2 30

2 29

............

2

0

22

20

2'

I 31
_2 31

'Sign 1

30

29

2 30

2 29

.................

2
22

0
2'

20

(Sign 1

Unsigned Integer Inputs
Input Operand A
31

30

29

............

2 31

2 30

2 29

........ , .

2:

Input Operand B
'

2
22

2'

0

31

30

29

20

2 31

2 30

2 29

.. . .. . ... .

2
22

0
2'

20

31

30

29

-2°

2-1

2- 2

,ig")

In put 0 perand B
2

I

0

..... 2- 29 2-30 2-3 •

I 31

30

29

-2°

2- 1

2-2

~a:

au..

Two's Complement Fractional Inputs
Input Operand A

o
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2

0

.. 2-29 2-30 2-31

2

w

(J

(Sign 1

2:

ct

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C



65

64J

_24
23
22
'-.,-'

Most Significant Product
(Y63-Y32)
63
21

62

61

'30

20

2- 1

2-28 2-29 2- 30

<
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2

m
2

:T1

o

31

32

31

30

29

2-31 2-32 2- 33

2

2-60 2-61

o 1
2-62

(Sign)

C

(")

Least Significant Product
(Y31-YO)

Unsigned Fractional Outputs
Extended
Product
(YETP2-YETPO)

Most Significant Product
(Y63-Y32)

L.-6_6___6....:5___6_4~1

L.1_6_3___
6_2___
6_1____________
30____
31___3_2~

22

21

20

2- 1

2-2

Least Significant Product
(Y31-YO)
31

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TEXAS.

4-20

30

29

2-33 2-34 2-35

2- 3

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

2

0

2-62 2-63 2 - 64

I

SN74ACT8836
32·BIT BY 32·81T MULTIPLIER/ACCUMULATOR

double'precision multiplication
To simplify discussion of double-precision multiplication, the following example implements an algorithm
using one' ACT8836 device. It should be noted that even higher speeds can be achieved through the use
of two 'ACT8836s to implement a parallel multiplier.
The example is based on the following algorithm where A and Bare 64-bit signed numbers.
Let
Am = as,a62, a61,· .. , a32
and
AI = a31. a30, a29, ... , ao (ao
LSBI
Therefore:
A = (Am x 2 32 1 + AI
Likewise:
B = (B m x 2 32 1 + B,
Thus:
A x B = [(Am x 2 32 1 + Ali x [(B m x 2 32 1 + B,]
= (Am x Bm) 2 64 + (Am x B, + Ail x Bm )2 32 + AI x B,
Therefore, four products and three summations with rank adjustments are required.
Basic implementation of this algorithm uses a single' ACT8836. The result is a two's complement 128-bit
product. Microcode signals to implement the algorithm are shown in Figure 4.
The first instruction cycle computes the first product, AI x B,. The least significant half of the result is
output through the Y port for storage in an external RAM or some other 32-bit register; this will be the
least significant 32-bit portion of the final result.

II

The instruction also uses the shifter to shift the AI x B,product 32 bits to the right in order to adjust
for ranking in the next multiplication-addition sequence. The least significant half of the shift result is stored
in the lower 32-bit portion of the accumulator; the upper 32 bits contain the zero and fill.
The second instruction produces the second product, AI x Bm , adds it to the contents of the accumulator,
and stores the result in the accumulator for use in the third instruCtion.
Instruction 3 computes Am x B" adds the result to the accumulator, and outputs the least significant
32 bits of the addition for use as bits 63-32 of the final product.
This instruction also shifts the result 32 bits to the right to provide the. necessary rank adjustment and
stores the shift result (the most significant half of the addition result) in the lower 32 bits of the accumulator.
Bits ACC63-ACC32 are filled with zeros; the sign is e.xtended into the three upper bits (ACC66-ACC64).
Instruction 4 computes the fourth product (Am x Bm), adds it to the accumulator, and outputs the least
significant half at the Y port for use as bits 95~64 of the final product.
This example assumes that the chip is operating in feed-through mode. A fifth instruction is therefore required
to perform the fourth iteration again so that bits 127-96 of the final product can be output.

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TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

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Example 1. Single Precision Multiply. 32-Bit Result

m .....
-.c=o
ooo4:z:,.

.p.

N

Instruction Inputs

m"
<0004
CO

Operand

N

Select
R bus
S bus

EAEB
1

Rounding

Product
Comple-

Control

ment

Sign

Multiplierl
Adder
Mode

O·MUX

OASGN OBSGN RN01 RNOO COMPL ACC1 ACCO

1

1

L ________

0

1

1

0

0

0

Register
Load

Shift-MUX
Control

Select

Sign
Extend

SELD

SGNEXT

8FT1

SFTO

SELREG

0

X

0

0

0

Select

Register
Write
Enable

Feed-

!wEll WEL FT1
0

A

B

Y

FTO CKE' CKEA CKEB CKEY

0

0

Y/PY
Y-MUX Output
Select Enable

Clock Enables

,

through
Control

0

0

0

0

SELY

0

W CO

NW

CaCD

OEY •

::::j

o ,

1

s:

c
,...

::!
-a
,...

Example 2. Double-Precision Multiply. 64-Bit Result

;:;;

Instruction Inputs
Operand

2\

Instruction
Number

~

~i:iZ

EAEB

i3(JJ

"-l

~~r;;l

.;~
~

C~
~
I"'l

~z

4r

~ ~ ~.
~

Select
R bus
S bus

Rounding

Product
Comptement

Multiplierl

Adder

O-MUX

Mode

Select

Sign
Extend

Shift-MUX
Control

SELD

SGNEXT

SFT1 SFTO
1

OASGN OBSGN RN01 RNOO COMPL ACC1 ACeO

0

0

0

0

1

0

0
0

0

1

0

1

1

1

0

0

1

1

1

0

0

111

1

1

0

121

1

1

131

1

1

141

1

151

1

-

Control

Sign

0

Register
Load

Select

Register
Write
Enable

Feed-

through
Control

,

Clock Enables

A

B

Y

SELREG

iwEH

1

0

0

0

0

0

1

1

1

1

WEL FT1 FTO CKE' CKEA CKEB CKEY

Y/PY
Y-MUX Output
Select Enable
SELY

OEY

0

0

0

0

0

0

0

1

0

0
0

0

0

0

0

0

0

0

1

1

1

1

X

X

0

0

1

0

0

1

1

0

0

0

0

0

1

1

1

1

0

0

0

0

1

X

0

0

0

X

X

X

0

0

1

1

1

1

0

0

0

0

1

X

0

0

0

X

X

X

0

0

1

1

1

1

1

0

O-MUX
Select

Sign
Extend

SELD

SGNEXT

0

0

1

1

1

1

0

1

0

0

0

0

0

0

0

1

1

0

1

1

0

0

0

0

Example. 3. Newton-Raphson Division

~
~

Instruction Inputs

N

Operand

0>
~

Instruction
Number

Select
R bus
5 bus

EAEB

Rounding
Control

Sign

Product
Complement

Multiplier!
Adder
Mode

OASGN OBSGN RND1 RNOO COMPL ACCl ACCO

Shift-MUX
Control

SFTl

SFTO

Register
Load
Select

SELREG

Register
Write
Enable

Feedthrough
Control

!wEll WEL FTl

Clock Enables

I

A

B

Y/PY
Y-MUX Output
Y

Select

Enable

SELY

OEY

0

1

0

0

1

0

0
0

1

0

1

0

FTO eKEI CKEA CKEB CKEY

Repeat N Times *

111

0

1

0

121

0

0

a

0
0

0

0

0

1

0

0
0

0

0
0

'End Repeat

131

0

1

0

0

0

0

0

0

0

0

0

1

1

1

1

0

1

0

0

0

0

141

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

1

0

0

0

0

"N '" ~ Where m "" number of bits in the seed (assuming 32-bits of precisionl
2m+ 1

FIGURE 4. MICROCODED EXAMPLES

=

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=

SN14ACT8836

32·BI1 BY 32·BIT MULTIPLIER/ACCUMULATOR
Newton-Raphson binary division algorithm
The following explanation illustrates how to implement the Newton-Raphson binary division algorithm using
the 'ACT8836 multiplier/accumulator. The Newton-Raphson algorithm is an iterative procedure that
generates the reciprocal of the divisor through a convergence method.
Consider the equation Q = A/B. This equation can be rewritten as Q = A x (1/8). Therefore, the quotient
Q can be computed by simply multiplying the dividend A by the reciprocal of the divisor (B). Finding the
divisor reciprocal l/B is the objective of the Newton-Raphson algorithm.
To calculate liB the Newton-Raphson equation, Xi + 1 = Xi(2-BXi) is calculated in an iterative process.
In the equation, 8 represents the divisor and X represents successively closer approximations to the
reCiprocal 1/8. The following sequence of computation illustrates the iterative nature of the Newton-Raphson
algorithm.
XO(2-BXO)
Xl (2-8Xl)
X2(2-BX2)

Step 1
Step 2
Step 3

Xl
X2
X3

Step n

Xn = Xn-l (2-BXn-l )

The successive approximation of Xi, for all i, approaches the reciprocal 118 as the number of iterations
increases; that is
lim Xi = 1/8
i -+ n
The iterative operation is executed until the desired tolerance or error is reached. The required accuracy
for 118 can be determined by subtracting each xi from its corresponding xi + 1. If the difference IXi + 1
_. Xi I is less than or equal to a predetermined round off error, then the process is terminated. The desired
tolerance can also be achieved by executing a fixed number of iterations based on the accuracy of the
initial guess of 1/8 stored in RAM of PROM.
The initial guess, XO, is called the seed approximation. The seed must be supplied to the Newton-Raphson
process externally and must fall within the range of 0 
c
«

11 1 dO . dl d2 ............ dn - 2 dn-l

TEXAS

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4-23

SN74ACT8836
32·BIT BY 32·BIT MULTIPLIER/ACCUMULATOR

The next step in Newton-Raphson is to complete the 2 - BXi equation. The fractional representation of 2 is:

001 0 . 00 ........... 00
Completion of the 2 - BXi equation is shown in Table 8.

TABLE 8. COMPLETION OF 2-BXj EQUATION

+

=

Extended Bits
66
65
64
1
1
1
1
0
0
0
0
0

63

62

61

., , ...

dO
0

dl
0

d2
0

dO

dl

d2

.
.....
......
"

1

0

dn -2 dn -l
0
0
dn -2

dn -l

Since this step only affects the extended bits (66-64) on the' ACT8836. this step can be skipped. The
following algorithm can therefore be used to perform Newton-Raphson binary division with the' ACT8836.
Assuming B is on the DB bus (or stored in the B register) and Xi is stored in the temporary register:
Step 1
Accumulator

II

Step 2
Temporary Register <- Left shift one bit of
(accumulator times temporary register)
Xi+1

(J)

= Xi (2-BXiI

2

-.oJ

(DB x temporary register)
= 2-BXi

<- -

.,::a.

Step 3

-I

Two cycles are required for each iteration. The left shift that is performed in Step 2 is required to realign
Xi after the signed fraction mUltiply. Microcode for this example is shown in Figure 4.

»
(")
00
00
eN

Repeat Steps 1 and 2 until

IXi + 1

- Xi I :5 a predetermined round-off error

en

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-2

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TEXAS . "

4-24

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

SN74ACT8836
32·BIT BY 32·BIT MULTIPLIER/ACCUMULATOR
absolute maximum ratings over operating free-air temperature range (unless otherwise notedl t
Supply voltage, Vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 6 V
Input clamp current, 11K (VI < 0 or VI> Vee) ................................... ± 20 mA
Output clamp current, 10K (VOVee) . . . . .. .. . . . . . ... . .. . . . .. . . . . .
±50 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
± 50 mA
eontinous current through Vee or GND pins. . . .
....................
± 100 mA
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 e
Storage temperature range ......................................... - 65 °e to 150 °e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and fUnctional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maxi mum-rated conditions for 'extended periods may affect device reliability.

recommended operating conditions
MIN

NOM

MAX

4.5

5

5.5

V

Vee
0.8

V

-8

rnA

8

rnA

Vee

Supply voltage

VIH

High~Jevel

input voltage

2

Vil

Low-level input voltage

0

10H

High-level output current

10l
V,

Input voltage

0

Vee

Vo
dt/dv

Output voltage

0

Input transition rise or fall rate

0

Vee
15

TA

Operating free-air temperature

0

70

Low-level output current

UNIT

V

V
V
nsN
Qe

II

electrical characteristics over recommended operating free-air temperature range (unless otherwise
notedl
PARAMETER

TEST CONDITIONS
IOH

~

-20 pA

10H

=

-8 rnA

10l

= 20 pA

10l

=8

VOH

VOL
rnA

Vee

4.4

5.5 V
4.5 V

5.4
3.8

3.7

5.5 V

4.8

4.7
0.1

0.1

4.5 V

0.32

0.4

5.5 V

0.32

0.4

0.1

VI

=

Vee or 0

~

Vee or 0.10

5.5 V

VI - Vee or 0
One input at 3.4 V,

5V

VI ~ Vee or 0

10Zl

VI

= Vee

or 0

Vee

V

0.1

VI

other ihputs at 0 or

V

5.5 V

II

UNIT

4.4
5.4

4.5 V

ICC
ei

IOZH

TA - oQe to 10'e
MIN
MAX

4.5 V

5.5 V

"Iee t

TA = 25°e
MIN
TYP MAX

0.1
V
V

± 1.0

pA

50

100

pA

10

10

pF

5.5 V

1

1

rnA

5V

0.5

5

pA

5V

5

-0.5

-5

t This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 or

pA

Vee.

z

o

i=

C

o
<
:t>

:2

(")

m

-

:2
'"T'I

o

::D

s:

»
:::!
o

:2
TEXAS
4-26

~

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

MAX

UNIT

ns

SN74ACT8836
32·BIT BY 32·BIT MULTIPLIER/ACCUMULATOR
switching characteristics over recommended ranges of supply voltage and free-air temperature (see
Figure 21 for load circuit and voltage waveforms 1
PARAMETER

FROM

TO

(INPUT)

(OUTPUT)

FT MOOE (FTl-FTO)

MIN

TYP

MAX

tpdl t

ClK

PIPE

11

36

tpd2 t

PIPE

Y REG

11

36

tpd3 t

PIPE

ACCUM

11

36

tpd4 t

Y REG

Y

All modes

18

tpd5

SElY

Y

All modes

18

tpd6 t

ClK

Y REG

01

54

tpd7 t

ClK

ACCUM

10 or 01

67

tpd8

ClK

Y

10

67

tpd9

DATA

Y

00

60

tpdl0 t

DATA

ACCUM

00

56

tpdll

ClK

YETP

11 or 10

18

tpd12

ClK

ETPERR

11 or 10

18

t pd13

elK

YETP

00

67

tpd14

ClK

ETPERR

01

67

tpd15

DATA

YETP

00

60

tpd16

DATA

ETPERR

00

60

tpd17

PA

PERRA

All modes

20

t pd18

DA

PERRA

All modes

20

t pd19

P8

PERRB

All modes

20

tpd20

D8

PERRB

All modes

20

tpd21

PY

PERRY

All modes

20

tpd22

Y

MSERR

All modes

22

t pd23

YETP

MSERR

All modes

22

ten2

OEY

YETP

All modes

20

tenl

OEY

Y

All modes

20

tdisl

OEY

YETP

All modes

15

tdis2

OEY

y

All modes

15

UNIT

ns

II

2

o

-

I-

«

clock requirements
SN74ACT8836

PARAMETER

MIN

twl

ClK high

5

tw2

ClK low

20

MAX

UNIT
ns

~

a:
o
u..

-2w

tThese parameters cannot be measured but can be inferred from device operation and other measurable parameters.

()

2

«
>
o
«

..tf

TEXAS
INSTRUMENTS
POST OFFICE BOX 655012. DALlAS,'TEXAS 75265

4-27

SN74ACT8836
32·BIT BY 32·BI1 MULTIPLIER/ACCUMULATOR
PARAMETER MEASUREMENT INFORMATION
eLK I/??????ZZ??????????????)?????????????????????????????ZZZZZZZZZZZZZZZ
___________________________________________________________________

CKEA,CKEB~n-

CKEI, CKEY

ZZf
I

INSTR~:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::X::::

,,
I

DATAZZX====================================================X===
I

,

1

SELY--+:------------------------------------------_______
I

I

I

I

OEY SSSSS\SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS '>
,

,

I

~ten2

I
~ tpd5

"
Ipd9
"I
Y31-YO SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSX

II
en
2

""-I
~

l>
("')
-t

00
00
eN

m

Z
"T1
o

MSP

I
x:s

CLK __________________________________________~~L------------------_
I

CKEA,CKEB~r_--------------------------------------~I------------------------_

CKEI, CKEY

INSTR

Z4'

I

I

I

I
I
2X:::::::::::::::::::::::::::::::::::::::::t'::::::::::::::::::::x::::
I
I
I

,

DATA~~==================================II==============:::X===
I
I
I

I

I

I

I

SELREG _ _

(')

X

LSP

tdiS2~

FIGURE 5, FULL FLOWTHROUGH MODE 1FT - 00)

0)

»
c
<
»
z

«ZZZZ

I

I

,

\~\\'>'\'>'>'>YYY\'''Y\'"\'\.:YYYYY\'\)':YYY\;''\\)''\''\,'>1>

I,

gIZZ??Z?ZZ?

tSU7-tsU9~:

iNm'S, WELS

~th7-th9-_

I

SUM-OF-:~::::::::::::::::::::::::::::::::::::::==*::::::::::JA~C~CU~M:::::::::::
PRODUCT
I
I,
tpd10
.,
SELY
OEY

I
I
I

I

I

I

sssssssssssssssssssssssssssssssssssssss ~
I

-r"..----~~~~

I

I

I

I,

I

tpd9

I

I

I
I

.,

I
I
I

s:

l!C

FIGURE 6_ FULL FLOWTHROUGH MODE, ACCUMULATOR MODE 1FT = 00)

»
:j
o
z

~

4-28

TEXAS
INSTRUMENTS
POST OfFICE BOX 655012 • DALLAS, TEXAS 75265

I

I

LSP

ten2~

:xJ

tdis2~

I

,I

Y31-YO s\Ss\SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSlSSSX

(7Z7Z

tpd5~

MSP

I
xs:

SN74ACT8836
32-81T BY 32-81T MULTIPLIER/ACCUMULATOR
PARAMETER MEASUREMENT INFORMATION
CLK __________

~r____I~

__________________

~r____I~

,

1

CKEA, eKES
CKEI, CKEY

I

~:

_t

______________________

1

422222ZZZZ22222227ZZZZ;
11+.--~.,~th3-thS

:

:+-tsu 3-tsuS-.!

INSTR::J!<:,.----th1---_.'>,t=================
*
"=================:::
1

DATA:::X
I

au 1---+!

1

...

i

1

i+-- t su2---+!

,

,

A,.

1

I

1

I+1.----th2-----+l.,

PRODUCT=====:ti============::f::======]YR~EG[:====:::
I
1
SELY

OEY

,....- - - - - - t p d S - - - - - - - o t . ,
I

,

:

SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS" :

1

:
:
Y31-YO

~,.----------...
~::-<:""~~

1

--------------------------------------~,----------,

~tpd4:
:
tpd5~

SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS](
1
ten2 I.

1
.1

LSP

4Z7U
tdis2-l+--+1
:

X::=JM~S[P==XS

II
co

(Y')

CO
CO

....

FIGURE 7. FLOWTHROUGH PIPE ONLY VOLTAGE WAVEFORMS (FT - 01)

(.)


Q
«
TEXAS.

INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

4-29

SN74ACT8836
32:81T 8Y 32·81T MULTIPLIER/ACCUMULATOR
PARAMETER MEASUREMENT INFORMATION

ClK

,

CKEA.CKEB

,

I

~~3k~'~~~~;;;;;;I;;;;;;;;;;;~;;;;;;;;;;;;~;t;;;;;;;;~~~~~~~~
lIe::±====::J

CKEI.CKEY --+i !+-tsu3- su6
INSTR S)K ,
t

-.:

:.-tsu 1

:

~th1-----.t

DATA:SX:

-.l

*:::::t===:::::::

A. B

:--tsu2

:

:
,

_th2~

,

1

SElREG
I
WEMS. WElS SSS(;SSSSSSS).
,

i

t su7-t su9

14

1
I
1
..cZZZZZzzzzzzzzzzzzZZZZZZZZZZZZZZZZZZZZZ
II II
I,
i

.',

I+-- t h7- t h9---.t

1

PRODUCT
SUM-OF- SSSSSSSSSSSSSSSSS'1iCI
I

II

I

~tpd7----+!
,
I

PRODUCT SSSSSSSSSSSSSSSS'X
I

1

YRE.

I'

~tpd6----+1

I

I

I::======:::jl=======±====
xq:~======::j:,=======::::====
i

ACCUM:t<

I

,

1

'

I

I

1

:

I

1

I

1

I

SElY-------------------T:-----------i:~;:-----------'(~SSf$sSSSSSSS~S~,~S~S~S~S~S~SSS~fSSSSSS~S~S~S~S~
SSSSSSSSSSSSSssss\ssSSSSSSSSSSSSSSSSSS*

lSP

X

1

XS

MSP

FIGURE 9. FLOWTHROUGH PIPE AND Y ONLY 1FT = 10)

ClK
I
I
CKEA. CKEB ">.'{,.I
:
}z
CKEI
~~~I--------------~-------------r--------------;---------------~I----~~
INSTR ~
l!<
x
x
)(C~:
~

~tsu3·tsu5

-..I

~tsu1
:
i+---th1_

DATA~
I

I
I

I

th3·th5~

I

I

*

A,S

I

X

I
I

~tsu2

xC~I===:

X

I
1

I
1
'---th2----.1

SElREG:
WEMS.WElS ~SSSSSSS»

II

I
I . I
I4--- t h7·t h9--..i

SUM.OF.
I
I
PRODUCT ZZZZZZZZZZZ722ZZZZX

ACCUM

I

1

:.
I

1

I

I

I

I.
I

.
tpd8

I
:
1

*I

:

I .1

1

I

:E
a:

oLL

-w

-flZZz)zzzzzzzzzzazhzzzm 2

I

I i i
tpd5~1
tdis2"*--!
I
II

lSP

2

o
;::

«

:

1

!

I

Y3HO ZZZZZZZZZZZZZZZZZZ2X

1

I
I

1

~ten2
I

I
I
I

~--~------------~I~------------~------(
I

~ SSS
o
«

SN74ACT8836
32·BIT BY 32·BIT MULTIPLIER/ACCUMULATOR
PARAMETER MEASUREMENT INFORMATION
ClK
_
CKEA. CKEB ~
CKEI. CKEY -

,

I

"'-t su3-tsu6
I
:

INSTR::::!< :

'

I

I
I

x:

--+i ~tsul
: I
-thl- I

DATA:::K:

-..:
INTR. PRODUCT

8PI1l

*:

!.--tpdl--":

I

x

X
I

:

:

:

X

ptPE

i

I

I

*c:=====~====::::====:±==

PIPE

I

I

I YREG

I

c=::~::::::::~I::::::::::t:::=
I

I

X

X

! YREG

I

I

I,

~~~
:

I

I

:

I

I

~~Ir-----~~__

I

I

I

I I

I

I

I

-+____~~(----rl----~\~"~S~'~SS~S~S~SS~s~S~S
:
122?vymm

:
I

II

I
:

CO!2l

PRODUCT s&~"'~""'-\'L~'\$'>S*

SElY

=====>q:===::)

xCI!

;"'tsu2
::
_th2-o1 I

~A'S\\§.\S\s,*

I

x

I I

~ S\\\f%SS\\\\\\\fSSSS\\\SS\S~ :
I

I

I

I

I J4-.tpd4.....
J. I
I

I I
' I
lSP1:

I

*

tpd5~ I
I I
MSP1

I '

_te"2_

*

LSP2

~tpd5

»

-

:2

."

o

:xJ

3:

»
::t

o

:2

~

4-32

TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

I

I

:

I

I

I

:

:

tpd5~ I
I I

FIGURE 11. ALL REGISTERS ENABLED 1FT - 11)

c
<
»
:2
n
m

:

I

I

::

Y31~YO'~""~'§»%»&~%,,$S\$S\SS$*
[

I

*

I
I

MSP2

_

I

:X1Vifi?V!
I
/+-ldis2

SN74ACT8836
32·BIT BY 32·BIT MULTIPLIER/ACCUMULATOR
PARAMETER MEASUREMENT INFORMATION
ClK
~

I

r4- 'h3"suS

CKEA. CKEB ~ I
CKE!. CKEY
I
INSTR

:JI< :

I
I

:

th3- t hS-':

I

I

:

I

I

*:
*

-.I ,..tsu 1
I
.......----th1--.i
DATA:::':; A.B"I
-.J !"-'su2
:
:+--th2_ I
INTR. PRODUCT ~'''''*'''\§'X
,
I

:

~'§S\~

C, D 121

SUM-OF-

PI"

I .I

Y31-YO

,

PIPE

I

I
ACCUM

.:

X

i

I

:

I

I

:

I

'

I

,

x:
:
xc:==t=:==::t:====::==

'
,I

ACCUM.

I

x

,

I,
tpd2~

I

!

I

,(

:

:

:

:

I

I

I ......... t p d4

I

I

"

I

I

,

I

OEY

*

*

I

. ' .

I
I

PRODUCT S\»SSS\S§SS\SSS$S§\*

SElY

I

I

I

tpd3"""""'-

I

I

I

I

~ 'h7- t h9-oi

I

I

I

I

:

I

I

:

I

I

\'S.\w~&'$%\\S%.&~

:

I

xd==~xq====XX~:==~X¢:===~

WEMS. WElS,
I
I
:tSU7-'SU9~
PRODUCT

I

I

xd==~xq====Xx~,==~x¢:===~

-'pd1~
I
I

SELREG

f4-

k2z'l

VREG :

•

I
I

YREG

I
I

I

:

:

I

I

I

:

:

:

: 4 ZZ2(2Wzdww

:

I

I

I

I

I

I:

:

: :

:

J

sssK~,*,\S\\\~\§\§\§$l>t:

SS$SSSS\$SSS~"-\\&~%,K

\.~__-tII-,/-------r'''''';;:<::~$::S$:S$\:S:$'::::>::S$SS\:S:$~9;S~SSS:$::::$;SS

'pd5~
lSPl

*

---.I-'.n2

MSP1

I

I

II

*=Jl!lSP2:2=:JXC=]MmSrlp2c'::jI,)X;;I~:SSS')'.S:SS:$S:SS:S':::S~S:SS\:S:S::::$::S::S'
I

.-.I

I+-.J-tpd5

~tdi.2

FIGURE 12. ALL REGISTERS ENABLED, ACCUMULATOR MODE 1FT - 11)
rVCC
S1
TEST
FROM OUTPUT _ _P....
O.IN_T_ _"Rl,.,.._-.
UNDER TEST

PARAMETER
'en
'dis

tPZH
tpZL
tpHZ

Rl

clt

1 kll

50 pF

1 kll

50 pF

-

50 pF

'PlZ

'cd

S2
CLOSED
OPEN
CLOSED
OPEN
OPEN

S1'
OPEN
CLOSED
OPEN
CLOSED
OPEN

cd:

t Cl includes probe and test fixture capacitance

~

lOAD CIRCUIT
~II input

pulses are supplied by generators having the following characteristics: PRR :s; 1 MHz, Zout

=

50 0, tr ::::: 50

z

o
i=

n,

tf = 6 ns.

FIGURE 13. LOAD CIRCUIT

a::
o
LI..
Z

W
(.)

:iii!
cd:

>
Q
cd:

~

TEXAS
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TeXAS 75265

4-33

4-34

SN74ACT8837

64-Bit Floating Point Processor

5-1

5-2

SN74ACT8837
64·8it Floating Point Unit
•

Multiplier and ALU in One Chip

•

60-ns Pipelined Performance

•

Low-Power EPIC'M CMOS

•

Meets IEEE Standard for 32- and 64-Bit Multiply,
Add, and Subtract

•

Three-Port Architecture, 64-Bit Internal Bus

•

Pipelined or Flowthrough Operation

•

Floating Point-to-Integer and Integer-to-Floating
Point Conversions

•

Supports Division Using Newton-Raphson
Algorithm

•

Parity Generation/Checking
The SN74ACT8837 single-chip floating point processor performs high-speed 32and 64-bit floating point operations. More than just a coprocessor, the' ACT8837
integrates on one chip, two double-precision floating point functions, an ALU
and multiplier.
The wide dynamic range and high precision of floating point format minimize
the need for scaling and overflow detection. Computationally-intense
applications, such as high-end graphics and digital signal processing, need doubleprecision floating point accuracy to maintain data integrity. Floating point
processors in general-purpose computing must often support double-precision
formats to match existing software.
By integrating its two functions on one chip, the' ACT8837 reduces data routing
problems and processing overhead. Its three data ports and 64-bit internal bus
structure let the user load two operands and take a result in a single clock cycle.

EPIC is a trademark of Texas Instruments Incorporated.

5-3

en

:2

.....

,f:I.

»
(")
-I

co
co
w
.....

5-4

Contents
Page

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .
Understanding the 'ACT8837 Floating Point Unit .........
Microprogramming the' ACT8837 ....................
Support Tools ...................................
Design Support . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . ..
Design Expertise ..... , ...........................
'ACT8837 Logic Symbol ...........................
'ACT8837 Pin Descriptions .........................
'ACT8837 Specification Tables ......................

5~13

.
.
.
.
.
.
.
.

5-13
5-13
5-14
5-14
5-15
5-16
5-17
5-24

SN74ACT8837 Floating Point Unit ..................... , .

5-27

Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "' ......
Input Data Parity Check ..........................
Temporary Input Register .........................
RA and RB Input Registers ........................
Multiplier/ALU Multiplexers ........................
Pipelined ALU .................................
Pipelined Multiplier ..............................
Product, Sum, and C Registers .....................
Parity Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Master/Slave Comparator .........................
Status and Exception Generator/Register ............
Flowthrough Mode ............................
Fast and IEEE Modes ..........................
Rounding Mode . . . . . . . . . . . . . . . . . . . . . . .. . . . ...
Test Pins ...................................
Summary of Control Inputs ..................... ,

.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.

5-27
5-27
5-29
5-29
5-30
5-31
5-31
5-31
5-31
5-34
5-34
5-37
5-37
5-38
5-38
5-38

5-5

r...

('I)

CO
CO
t-

U



(")

-t

00
00
W

......

5-8

List of Illustrations
Figure

1
2

3
4
5
6
7
8
9
10

Page

' ACT8837 Floating Point Unit .....................
Single-Precision Operation, All Registers Disabled
(PIPES = 111, CLKMODE = 0) · .................
Single-Precision Operation, Input Registers Enabled
(PIPES = 110, CLKMODE = 0) · .................
Single-Precision Operation, Input and Output Registers
Enabled (PIPES = 010, CLKMODE = 0) ............
Single-Precision Operation, All Registers Enabled
(PIPES = 000, CLKMODE = 0) · .................
Double-Precision ALUOperation, All Registers Disabled
(PIPES = 111, CLKMODE = 0) · .................
Double-Precision ALU Operation, Input Registers Enabled
(PIPES = 110, CLKMODE = 0) · .................
Double-Precision ALU Operation, Input and Output
Registers Enabled (PIPES = 010, CLKMODE = 0) .....
Double-Precision AlU Operation, All Registers Enabled
(PIPES = 000, CLKMODE = 0) · .................
Double-Precision ALU Operation, All Registers Disabled
(PIPES = 111, CLKMODE = 1)
Double-Precision ALU Operation, Input Registers Enabled
(PIPES = 110, CLKMODE = 1) · .................
Double-Precision ALU Operation, Input and Output
Registers Enabled (PIPES = 010, CLKMODE = 1) .....
Double-Precision ALU Operation, All Registers Enabled
(PIPES = 000, CLKMODE = 1) · ............... ..
Double-Precision Multiplier Operation, All Registers
Disabled (PIPES = 111, CLKMODE = 0) ...........
Double-Precision Multiplier Operation, Input Registers
Enabled (PIPES = 110, CLKMODE = 0) ............
Double-Precision Multiplier Operation, Input and Output
Registers Enabled (PIPES = 010, ClKMODE = 0) .....
Double-Precision Multiplier Operation, All Registers
Enabled (PIPES = 000, CLKMODE = 0) ............
Double-Precision Multiplier Operation, All Registers
Disabled (PIPES = 111, CLKMODE = 1) ...........
•

11
12
13

• • • • • • • • • • • • • • • •

'

14
15
16
17
18

8

5-28
5-53
5-54
5-55
5-57
5-59
5-61
5-63

,....
5-65

M
CO
CO

5-67

I-

5-68

o:::t
,....

5-70

(J)

(.)

<{

5-72
5-74
5-75
5-76
5-78
5-80
5·9

Z

List of Illustrations (Concluded)
Figure

19

20
21
22

23
24
25
26

en
:2
~
"""
l>

C')

-I
00
00
eN

"""

5-10

Page

Double-Precision Multiplier Operation, Input Registers
Enabled (PIPES = 110, CLKMODE = 1) .......... .
Double-Precision Multiplier Operation,lnput and Output
Registers Enabled (PIPES = 010, CLKMODE = 1) ....
Double-Precision Multiplier Operation, All Registers
Enabled (PIPES = 000, CLKMODE "" 1) .......... .
Mixed Operations and Operands
(PIPES2-PIPESO = 110, CLKMODE = 0) .......... .
Mixed Operations. and Operands
(PIPES2-PIPESO = 000, CLKMODE = 1) .......... .
Sequence of Matrix Operations . . . . . . . . . . . . . . . . . . .
Resultant Matrix Transformation ................. .
IEEE Double-Precision Seed ROM for Newton-Raphson
Division and Square Root ..................... .

5-81
5-83
5-85
5-91
5-92
5-96
5-103

5-125

List of Tables
Table

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Page

'ACT8837 Pin Grid Allocations ..................
'ACT8837 Pin Functional Description .... ; .........
Double-Precision Input Data Configuration Modes .....
Single-Precision Input Data Configuration Mode ......
Double-Precision Input Data Register Sources ........
Multiplier Input Selection .......................
ALU Input Selection ..........................
Independent ALU Operations, Single Operand
(19 = 0, 16 = 0) ...........................
Independent ALU Operations, Two Operands
(19 = 0, 15 ::: 0) ...........................
Independent Multiplier Operations
(19 = 0, 16 ::: 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Independent Multiplier Operations Selected by 14-12
(19 = 0, 16 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operations Selected by 18-17 (19 = 0, 16 = 1) .......
Chained Multiplier/ALU Operations (19 = 1) .........
Comparison Status Outputs .....................
Status Outputs ..............................
Status Output Selection (Chain Mode) .............
Pipeline Controls (PIPES2-PIPESO) ................
Rounding Modes .............................
Test Pin Control Inputs ........................
Control Inputs ...............................
IEEE Floating-Point Representations ...............
Handling Wrapped Multiplier Outputs ..............
Independent ALU Operations with One Operand ......
Independent ALU Operations with Two Operands ....
Independent Multiplier Operations ................
Chained Multiplier/ALU Operations ................
Single-Precision Sum of Products
(PIPES2-PIPESO = 010) ......................
Sample Microinstructions for Single-Precision
Sum of Products ...........................

.
.
.
.
.
.
.

5-17
5-18
5-29
5-30
5-30
5-30
5-30

.

5-32

.

5-33

.

5-33

.

.
.
.
.
.
.
.
.
.
.
.
.
.
.
.

5-34
5-34
5-35
5-36
5-36
5-37
5-37
5-38
5-38
5-39
5-44
5-46
5-49
5-50
5-50
5-51

.

5-86

.

5-87
5-11

"
M

00
00

....
()


'ACT8837
64-Bit Floating Point Unit

CLK

CLKMOOE

CLOCK EDGE

BYTEP

PARITY GENERATION

CONFIG1-0
FAST

~

SUDDEN
GRADUAL

/'I
/'I

INSTRUCTION, RA, & RB IFLOWTHROUGH
REGISTERS
EN

4-l

ALU AND MULTIPLIER I FLOWTHROUGH
PIPELINE REGISTERS
EN

4-l

STATUS, p, AND S I FLOWTHROUGH
REGISTERS
EN

~

IUNDERO
FLOW

ROUNDING MODE

~

MULTIPLIER
ALU

Ic

OPERAND SOURCE

SELST1-0

STATUS SOURCE

~

TP1-0

MSH
LSH

SELECT

REG

SELOP7-0

SELMS/LS

STALLS OPERATION

PIPESO

DATA SOURCE

RND1-0
SRCC

CLEARS STATES
& STATUS

MASTER CLOCK (EXCEPT C REGISTERI
C REGISTER CLOCK

CLKC

PARITY
I/O

I

Y BUS

STATUS
PARITY

TEST PINS

10

I
I

PIPES2

DA DATA

PA3-0

DB DATA

PB3-0
PY3-0

Y BUS
DA DATA
DB DATA

PERRA

MASTER/SLAVE
COMPARATOR

MSERR

0
COMPARISON
STATUS

11

PIPES1

PERRB

I

UNORD
AGTB
AEQB

12
13

IVAL

14

en

IN EX
OVER

16

Z

17

~

19

9

ENRA

,....

OES

"-

OEC

W

......

OEY

~

DAO

DA31
DBO

DB31

5-16

DENORM
DENIN
RNDCO

LOAD RA REGISTER

ENRB

0)
0)

UNDER

EXCEPTION
AND
OTHER
STATUS

18

,J::o

l>
(")
-t

INSTRUCTIONS

15

··•
··•

SRCEX

LOAD RB REGISTER
EXCEPTION & OTHER STATUS

CHEX
EN

STEX1STEXO

COMPARISON STATUS

...,

Y31-YO, PY3-PYO

r

0

··

C§0

··

~

0

31
0

31

~

···

31

··

YO

Y31

'ACT8837 Pin Descriptions
Pin descriptions and grid allocations for the' ACT8837 are given on the following pages.
208 PIN . .. GB PACKAGE

(TOP VIEW)
1 2 3 4

67891011121314151617

••••••••••••• -·-1

A
B

C
D

•••••••

••••••••• I
• • I,
:

·• .• i

F

I

• • II

G
H

J
:
'

M

....
..

N

•

P

•

R

•I

• ••• I
• I

i

• •I

._.:J

•••••

S
T

L• • • • • • •

Table 1 .• ACT8837 Pin Grid Allocations
PIN
NO.
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A 12
A13
A14
A15
A16
A17
Bl
82
B3
B4
B5
86
B7
BB
89
810
811
812
813
814
815
816
B17
Cl

NAME
NC
NC
Y5
Y8
Yll
Y14
Y17
Y20
Y21
Y24
Y27
Y29
PYO
PV3
IVAL
NC
NC
NC
Y2
Y4
Y7
Yl0
Y13
Y16
Y19
Y22
Y25
Y28
Y31
PY2
OVER
RNDCO
DENORM
NC
PERR8

PIN

PIN
NO.

NAME

NO.

C2
C3
C4
C5
C6
C7
C8
C9
Cl0
Cll
C12
C13
C14
C15
C16
C17
Dl
02
03
04
05
06
D7
D8
09
Dl0
011
D12
D13
D14
D15
D16
D17
El
E2

YO
Y3
Y6
Y9
Y12
Y15
Y1S
Y23
V26
Y30
PVl
UNDER
INEX
DENIN
5RCEX
CHEX
11
RNDl
Yl
GND
VCC
GND
GND
VCC
GND
GND
VCC
GND
GND
VCC
5TEXl
5TEXO
UNORD
12
10

E3
E4
E14
E15
E16
E17
Fl
F2
F3
F4
F14
F15
F16
F17
Gl
G2
G3
G4
G14
G15
G16
G17
Hl
H2
H3
H4
H14
H15
H16
H17
Jl
J2
J3
J4
J14

NAME
FA5T
GND
GND
AGT8
AEOB
M5ERR
15
13
RNDO
GND
GND
PERRA
OEY
OES
17
16
14
VCC
VCC
OEC
5ELM5rLS
TPl
19
NC
18
GND
GND
TPO
5EL5Tl
5EL5TO
SELOP2
5ELOPl
5ELOPO
VCC
VCC

J15
J16
J17
Kl
K2
K3
K4
K14
K15
K16
K17
L1
L2
L3
L4
L14
L15
L16
L17
Ml
M2
M3
M4
M14
M15
M16
M17
Nl
N2
N3
N4
N14
N15
N16
N17

NAME
NC

SRCC
BYTEP
5ELOP3
SELOP4
SELOP5
GND
GND
PAl
PA2
PA3
5ELOP6
5ELOP7
CLK
VCC
GND
DA30
DA31
PAO
ENRB
ENRA
CLKC
GND
VCC
DA27
DA28
DA29
CONFIGO
CONFIGl
CLKMODE
PIPES2
DA18
DA24
DA25
DA26

PIN

PIN

PIN
NO.

NO.
Pl
P2
P3
P4
P5
P6
P7
P8
P9
Pl0
Pl1
P12
P13
P14
P15
P16
P17
Rl
R2
R3
R4
R5
R6
R7
R8
R9
Rl0
Rll
R12
R13
R14
R15
R16
R17

NAME NO. NAME
NC
PIPESO
RE5ET
P81
DBl
DB5
DB9
DB16
DB21
DB28
DAO
DA4
DA8
DA12
DA19
DA22
DA23
PIPE51
HALT
PB2
DB2
DB6
D810
DB14
DB18
DBn
DB27
0831
DA3
DA7
DAll
DA16
DA20
DA21

51
52
53
54
55
56
57
58
59
510
511
512
513
514
515
516
517
T1
T2
T3
T4
T5
T6

T7
T8
T9
T10
Tll
Tl2
Tl3
T14
Tl5
Tl6
Tl7

NC
PBO
DBO
DB4
DB11
DB12
D815
DB19
DB23
D826
D830
DA2
DA6
DAlO
DA14
DA15
DA17
NC
P83
083
DB7
DB8
DB13
DB17
0820
D824
D825
0829
DAl
DA5
DA9
DA13
NC
NC

"
M

ex)
ex)

.....

o

«
'¢

"Z

tJ')

5-17

Table 2. 'ACT8837 Pin Functional Description
PIN
NAME

en

z-...J
~

l>

("")
~

00
00
W
-...J

NO.

1/0

AEQB

E16

I/O

AGTB

E15

I/O

BYTEP

J17

I

CHEX

C17

I/O

ClK
ClKC

l3
M3

I
I

ClKMODE

N3

I

CONFIGO
CONFIG1
DAO
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
DA14
DA15
DA16
DA17
DA18
DA19
DA20
DA21
DA22
DA23

N1
N2
P11
T12
S12
R12
P12
T13
S13
R13
P13
T14
S14
R14
P14
T15
S15
S16
R15
S17
N14
P15
R16
R17
P16
P17

I

I

DESCRIPTION

Comparison status 1 zero detect pin. When high.
indicates that A and B operands are equal during a
compare operation' in the AlU. If not a compare, a
high signal indicates a zero result.
Comparison status pin. When high, indicates that A
operand is greater than B operand.
When high, selects parity generation for each byte
of input (four parity bits for each bus).
When low, selects parity generation for whole
32-bit input (one parity bit for each bus).
Status pin indicating an exception during a chained
function. If 16 is low. indicates the multiplier
is the source of the exception. If 16 is high,
indicates the AlU is the source of the exception.
Master clock for all registers except C register
C register clock
Selects whether temporary register loads only on
rising clock edge (ClKMODE = l) or on falling
edge (ClKMODE = HI.
Select data sources for RA and RB registers from
DAbus. DB bus and temporary register.

DA 32-bit input data bus. Data can be latched in a
64-bit temporary register or loaded directly into an
input register.

Table 2. 'ACT8837 Pin Functional Description (Continued)
PIN
NAME

OA24
OA25
OA26
OA27
OA28
OA29
OA30
OA31
OBO
OB1
OB2
OB3
OB4
OB5
OB6
OB7
OB8
OB9
OB10
OB11
OB12
OB13
OB14
OB15
OB16
OB17
OB18
OB19
OB20
OB21
OB22
OB23
OB24
OB25
OB26
OB27
OB28
OB29
OB30
OB31
OENIN

NO.

N15
N16
N17
M15
M16
M17
L15
L16
53
P5
R4
T3
54
P6
R5
T4
T5
P7
R6
55
56
T6
R7
57
P8

I/O

DESCRIPTION

OA .32-bit input data bus. Data can be latched in a
64-bit temporary register or loaded directly into an
input register

I

T7

DB 32-bit input data bus. Data can be latched in a
64-bit temporary register or loaded directly into an
input register

....

(.)

R8
58
T8
P9
R9
59
T9
T10
510
R10
P10
T11
511
R11
C15

"'"

M
00
00

«~

"'z"

en

I/O

5tatus pin indicating a denormal input to the
multiplier. When OENIN goes high. the 5TEX pins
indicate which port had the denorrnal input.

Table 2. 'ACT8837 Pin Functional Description (Continued)
PIN
NAME

5-20

NO.

110

DENORM

B16

1/0

ENRA

M2

I

ENRB

M1

I

FAST

E3

I

GND
GNO
GND
GNO
GND
GND
GND
GNO
GNO
GND
GND
GND
GNO
GND
GND
GND
GND

04
06
07
09
D10
D12
013
E4
E14
F4
F14
H4
H14
K4
K14
L14
M4

HALT

R2

10
11
12
13
14
15
16
17
18
19
INEX

E2
01
E1
F2
G3
F1
G2
G1
H3
H1
C14

DESCRIPTION
Status pin indicating a denormal output from the
ALU or a wrapped output from the multiplier. In
FAST mode, causes the result to go to zero when
DENORM is high.
When high, enables loading of RA register on a
rising clock edge if the RA register is not disabled
(see PIPESO below).
When high, enables loading of RB register on a
rising clock edge if the RB register is not disabled
(see PIPESO below).
When low, selects gradual underflow (IEEE mode).
When high, selects sudden underflow, forcing all
denormalized inputs and outputs to zero.

Ground pins. NOTE: All ground pins should be
used and connected.

I

Stalls operation without altering contents of
instruction or data registers. Active low.

I

Instruction inputs

1/0

Status pin indicating an inexact output

Table 2 .• ACT8837 Pin Functional Description (Continued)
PIN
NAME

NO.

I/O

IVAL

A15

I/O

MSERR

a

OEC

E17
A1
A2
A16
A17
B1
B17
H2
J15
Pl
81
T1
T16
T17
G15

OES

F17

I

OEY

F16

I

OVER

B14

I/O

PAO
PAl
PA2
PA3
PBO
PBl
PB2
PB3

L17
K15
K16
K17
S2
P4
R3
T2

PERRA

NC

DESCRIPTION
Status pin indicating that an invalid operation or a
non number (NaN) has been input to the multiplier
or ALU.
Master/Slave error output pin

No internal connection. Pins should be left floating.

I

Comparison status output enable. Active low.
Exception status and other status output enable.
Active low.
Y bus output enable. Active low.
Status pin indicating that the result is greater the
largest a"owable value for specified format
(exponent overflow).

,...
M
CO
CO

I-

I

U

Parity inputs for DA data

«
'd'
,...
Z

I

Parity inputs for DB data

F15

a

PERRB

Cl

a

PIPESO

P2

I

PIPESl

Rl

I

DA data parity error output. When high, signals a
byte or word has failed an even parity check.
DB data parity error output. When high, signals a
byte or word has failed an even parity check.
When low. enables instruction register, RA and RS
input registers. When high, puts instruction
register. RA and RB registers in flowthrough mode.
When low, enables pipeline registers in ALU and
multiplier. When high, puts pipeline registers in
flowthrough mode.,

en

5-21

Table 2 .• ACT8837 Pin Functional Description (Continued)
PIN
NAME

en

z

~

.J:io

»

('")

-I

00
00

W

NO.

1/0

DESCRIPTION

I

When low, enables status register, product (P) and
sum (S) registers. When high, puts status register,
P and S registers in flowthrough mode.

PIPES2

N4

PYO
PYl
PY2
PY3

A13
C12
B13
A14

RESET

P3

I

RNOO
RNOl

F3
02

I

RNOCO

B15

I

SELMS/LS

G16

I

SELOPO
SELOPl
SELOP2
SELOP3
SELOP4
SELOP5
SELOP6
SELOP7
SELSTO
SELST1

J3
J2
Jl
Kl
K2
K3
Ll
L2
H17
H16

SRCC

J16

I

SRCEX

C16

I/O

STEXO
STEXl

016
015

I/O

TPO
TPl

H15
G17

I

UNDER

C13

I/O

UNORO

017

I/O

I/O

I

I

~

5-22

Y port parity data
Clears internal states and status with no effect to
data registers. Active low.
Rounding mode control pins. Select four IEEE
rounding modes (see Table 18).
When high, indicates the mantissa of a wrapped
number has been increased in magnitude by
rounding.
When low, selects LSH of 64-bit result to be
output on the Y bus. When high, selects MSH of
64-bit result.

Select operand sources for multiplier and ALU
(See Tables 6 and 7)

Select status source during chained operation
(see Table 16)
When low, selects ALU as data source for C
register. When high, selects multiplier as data
source for C register.
.
Status pin indicating source of status, either
ALU (SRCEX = L) or multiplier (SRCEX = H)
Status pins indicating that a nonnumber (NaN) or
denormal number has been input on A port
(STEX1) or B port (STEXO).
Test pins (see Table 19)
Status pin indicating that a result is inexact and
less than minimum allowable value for format
(exponent underflow).
Comparison status pin indicating that the two
inputs are unordered because at least one of them
is a nonnumber (NaN).

Table 2. 'ACT8837 Pin Functional Description (Concluded)
PIN
NAME

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31

NO.

05
08
011
014
G4
G14
J4
J14
l4
M14
C2
03
B2
C3
B3
A3
C4
B4
A4
C5
B5
A5
C6
B6
A6
C7
B7
A7
C8
B8
A8
A9
B9
C9
A10
B10
C10
A11
B11
A12
C11
B12

I/O

DESCRIPTION

5-V power supply

,.....
M

CO

I/O

CO
....

32-bit Y output data bus

o

«
~
,.....
:2

CJ)

5-23

, ACT8837 Specification Tables
absolute maximum ratings over operating free-air temperature range
(unless otherwise noted) t
Supply voltage, Vee ..... . . . . . . . . . . . . . . . . .. -0.5 V to 6 V
Input clamp current, 11K (VI < 0 or VI > Vee) ........ ± 20 mA
Output clamp current, 10K (VO <0 or Vo > Vee) ..... ± 50 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . .. ± 50 mA
eontinuous current through Vee or GND pins ...... "
± 100 mA
Operating free-air temperature range . . . . . . . . . . . .. ooe to 70 0 e
Storage temperature range. . . . . . . . . . . . . . . .. - 65 °e to 150 °e
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage
to the device. These are stress ratings only and functional operation of the device at these or
any other conditions beyond those indicated under "recommended operating ~onditions" is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.

recommended operating conditions
PARAMETER

SN74ACT8837
NOM

MAX

4.75

5.0

5.25

V

V,dt:

V

-8
8

mA

Vee

Supply voltage

VIH

High-level input voltage

2

VIL

Low-level input voltage

0

IOH

High-level output current

IOL

Low-level output current

VI

Input voltage

Vo
dt/dv

Output voltage
Input transition rise or fall rate

TA

Operating free-air temperature

5-24

UNIT

MIN

,,·t1:~;~'O'. 8
,:"",,~\

";~~ -~~,

.~;:;p'
(Q:j,V

..

V
mA

Vee

V

0

Vee
15

ns!V

0

70

'\0

V
°e

electrical characteristics over recommended operating free-air
temperature range (unless otherwise noted)
PARAMETER

TEST CONDITIONS

=

10H

-20 p,A

VOH

=

10H
10L

=

-8 rnA
20 p,A

VOL
10L

'I

V,

lee

V,

ei

Vi

=

=
=
=

8 rnA

VCC

TA - 25°C
MIN TYP MAX

SN74ACT8837
MIN

TYP MAX

UNIT

4.5 V
5.5 V
4.5 V

3.76

5.5 V

4.76

V
,,',\

,,",;,;\,j\>;:"" "

4.5 V
5.5 V

,el'\, '1/

4.5 V

.,w:,(jI::i"

0.45

5.5 V

"

0.45

V

Vee or 0

5.5 V

±1

p,A

Vee or 0, 10

5.5 V

200

p,A

Vee or 0

5V

pF

switching characteristics (see Note)
PARAMETER

SN74ACT8837-65
MIN

Propagation delay from DAIDB!! inputs
tpd1

to Y output
Propagation delay from input register to

tpd2

output buffer
output buffer
Propagation delay from output register to

tpd4
tpd5

output buffer
Propagation delay from SELMS/LS to Y output

,;:;,dd,,:'i:"'\
''.;

Propagation delay from input register to
td1

output register
Delay time, input register to pipeline register or

td2

pipeline register to output register

UNIT

125

ns

118

ns

'~'"

Propagation delay from pipeline register to
tpd3

MAX

65

,j,~;5;:"\:{'~'~

ns

30

ns

32

ns

95

ns
ns

Note: Switching data must be used with timing diagrams for different operating modes.

5·25

setup and hold times
SN74ACT8837-65

PARAMETER

MIN

MAX
dC." ~

tsu1

Setup time, Instruction before ClK!

18

tsu2

Setup time, data operand before ClK!

18

Setup time, data operand before second ClK!

~oQ\)C;'\

tsu3

for double-precision operation (input register

",,9.~'l'

UNIT
ns
ns
ns

not enabled)
th1

Hold time, Instruction input after ClK I

0

ns

clock requirements
PARAMETER
tw

Pulse duration
Clock period

en
2

'-I
~

»
C')
-t

00
00

W

.....

5-26

I ClK high
I ClK low

SN74ACT8837-65
tJ-INIT
MIN
M,M\~ .¥'
15

?tlILJV

"c1 V'Y"""

ns
ns

SN74ACT8837 FLOATING POINT UNIT
The SN74ACT8837 is a high-speed floating point unit implemented in TI's
advanced 1-llm CMOS technology. The device is fully compatible with IEEE
Standard 754-1985 for addition, subtraction and multiplication operations.
The' ACT8837 input buses can be configured to operate as two 32-bit data buses
or a single 64-bit bus, providing a number of system interface options. Registers are
provided at the inputs, outputs, and inside the ALU and multiplier to support multilevel
pipelining. These registers can be bypassed for nonpipelined operation.
A clock mode control allows the temporary register to be clocked on the rising edge
or the falling edge of the clock to support double precision operations (except
multiplication) at the same rate as single precision operations. A feedback register with
a separate clock is provided for temporary storage of a multiplier result, ALU result
or constant.
To ensure data integrity, parity checking is performed on input data, and parity is
generated for output data. A mastei"lslave comparator supports fault-tolerant system
design. Two test pin control inputs allow alii/Os and outputs to be forced high, low,
or placed in a high-impedance state to facilitate system testing.
Floating point division using a Newton-Raphson algorithm can be performed in a sumof-products operating mode, one of two modes in which the multiplier and ALU operate
in parallel. Absolute value conversions, floating point to integer and integer to floating
point conversions, and a compare instruction are also available.

'"

Data Flow

M

IX)

Data enters the' ACT8837 through two 32-bit input data buses, DA and DB. The buses IX)
can be configured to operate as a single 64-bit data bus for double precision operations ....
U
(see Table 7). Data can be latched in a 64-bit temporary register or loaded directly ~
into the RA and RB registers for input to the multiplier and ALU.
.....

'"

Four multiplexers select the multiplier and ALU operands from the input register, C 2
(J)
register or previous multiplier or ALU result. Results are output on the 32-bit Y bus;
a Y output multiplexer selects the most significant or least significant half of the result
for output. The 64-bit C register is provided for temporary storage of a result from
the ALU or multiplier.

Input Data Parity Check
When BYTEP is high, internal odd parity is generated for each byte of input data at
the DA and DB ports and compared to the PA and PB parity inputs. If an odd number
of bits is set high in a data byte, the parity bit for that byte is also set high. Parity
bits are input on PA for DA data and PB for DB data. PAO and PBO are the parity bits
for the least significant bytes of DA and DB, respectively. Ifthe parity comparison
fails for any byte, a high appears on the parity error output pin (PERRA for DA data
and PERRB for DB data).

5-27

PERRA

DA3l-DAO

PA

0831-080

~

PB

PERRB

______-.c-_____.....

gg~~:~~-

~---+-ENRB

ENRA

19-10
SElOP7 -SElOPO
PIPES2 -PIPES 1
FAST
RN01-RNOO

HA'lT
BYTEP
SRCC

eLK
PIPESO
ClKMODE

fiE'S'ET

CLKC

(J)

TP1-TPO

Z

...,J
~

»
(")
-4

vee
GND
SElST1·
SElSTO

SHMS/i3
FAOM
INSTRUCTION·
REGISTER

(X)
(X)

iSEC

W

on

...,J

PY3-PYO

V31-VO

m

MSERR

UNORD
A GT B

A eo B

IVAL
INEX

oveR
UNDER
DENORM

OENIN
RNOCO

SRCEX
CHEX
STEX1-STEXO

Figure 1. •ACT8837 Floating Point Unit

5-28

A parity check can also be performed on the entire input data word by setting BYTEP
low. In this mode, PAO is the parity input for DA data and PBO is the parity input for
DB data.

Temporary Input Register
A temporary input register is provided to enable double precision numbers on a single
32-bit input bus to be loaded in one clock cycle. The contents of the DA bus are loaded
into the upper 32 bits of the temporary register; the contents of DB are loaded into
the lower 32 bits. A clock mode signal (ClKMODE) determines the clock edge on which
the data will be stored in the temporary register. When ClKMODE is low, data is loaded
on the rising edge of the clock; when ClKMODE is high, data is loaded on the falling
edge.

RA and RB Input Registers
Two 64-bit registers, RA and RB, are provided to hold input data for the multiplier
and AlU. Data is taken from the DA bus, DB bus and the temporary input register,
according to configuration mode controls CONFIG1-CONFIGO (see Tables 3 and 5).
The registers are loaded on the rising edge of clock ClK. For single-precision operations,
CON FIG 1-CONFIGO should ordinarily be set to 0 1 (see Table 4).
Table 3. Double-Precision Input Data Configuration Modes
LOADING SEQUENCE
DATA LOADED INTO
TEMP REGISTER ON FIRST

DATA LOADED INTO

CLOCK AND RAJRB

RA/RB REGISTERS ON

REGISTERS ON SECOND

SECOND CLOCK

CONFIG1

CONFIGO

DA

DB

DA

DB

0

0

B operand
(MSH)

B operand
(LSH)

A operand
(MSH)

A operand
(LSH)

A operand
(LSH)

B operand
(LSH)

A operand
(MSH)

B operand
(MSH)

A operand
(MSH)

B operand
(MSH)

A operand
(LSH)

B operand
(LSH)

A operand
(MSH)

A operand
(LSH)

B operand
(MSH)

B operand
(LSH)

0

CO
CO

tU

CLOCKt

0

r--

M

t On the first active clock edge (see CLKMODE, Table 17), data in this column is loaded into the temporary
register. On the next rising edge, operands in the temporary register and the DAtDB buses are loaded into
the RA and RB registers.

5-29

«
'¢
r--

Z

UJ

Table 4. Single-Precision Input Data Configuration Mode
DATA LOADED INTO
RA/RB REGISTERS ON
FIRST CLOCK.
CON FIG 1

CONFIGO

DA

DB

0

1

A operand

B operand

NOTE
This mode is ordinarily
used for single-precision
operations.

Table 5. Double-Precision Input Data Register Sources
RA SOURCE

RB SOURCE

CONFIG1

CONFIGO

MSH

LSH

MSH

LSH

0

0

DA

DB

TEMP REG
(MSH)

TEMP REG
(LSH)

0

1

DA

TEMP REG
(MSH)

DB

TEMP REG
(LSH)

1

0

TEMP REG
(MSH)

DA

TEMP REG
(LSH)

DB

1

1

TEMP REG
(MSH)

TEMP REG
(LSH)

DA

DB

Multiplier/ALU Multiplexers
Four multiplexers select the multiplier and ALU operands from the RA and RB registers,
the previous multiplier or ALU result, or thee register. The multiplexers are controlled
by input signals SELOP7-SELOPO as shown in Tables 6 and 7.
Table 6. Multiplier Input Selection
A1 (MUX1) INPUT

B 1 (MUX2) INPUT

SELOP7

SELOP6

OPERAND SOURCE

SELOP5

SELOP4

0
0

0

Reserved

0

Reserved

1

C register

0
0

1

C register

1

0

ALU feedback

1

0

Multiplier feedback

1

1

RA input register

1

1

RB input register

OPERAND SOURCE

Table 7. ALU Input Selection
A2 (MUX3) INPUT

B2 (MUX4) INPUT

SELOP3

SELOP2

OPERAND SOURCE

SELOP1

SELOPO

0

Reserved

0

0

0
1

C register

0

1

0

Multiplier feedback

1

1

1

RA input register

1

0
1
0
1

5-30

OPERAND SOURCE
Reserved
C register
ALU feedback
RB input register

Pipe lined ALU
The pipelined ALU contains a circuit for addition and/or subtraction of aligned operands,
a pipeline register, an exponent adjuster and a normalizer/rounder. An exception circuit
is provided to detect denormal inputs; these can be flushed to zero if the fast input
is set high. A denorm exception flag (DENORM) goes high when the ALU output is
a denormal.
The ALU may be operated independently or in parallel with the multiplier. Possible ALU
functions during independent operation are given in Tables 8 and 9. Parallel
ALU/multiplier functions are listed in Table 11.

Pipelined Multiplier

*

The pipelinedmultiplier performs a basic multiply function, A
B. The operands can
be single-precision or double-precision numbers and can be converted to absolute values
before multiplication takes place. Multiplier operations are summarized in Table 10.
An exception circuit is provided to detect denormalized inputs; these are indicated
by a high on the DENIN signal.
The multiplier and ALU can be operated simultaneously by setting the 19 instruction
input high. Possible operations in this chained mode are listed in Table 13.

Product. Sum. and C Registers
The results of the ALU and multiplier operations may optionally be latched into two
output registers on the rising edge of the system clock (CLK). The P (product) register
holds the result of the multiplier operation; the S (sum) register holds the ALU result.
An additional 64-bit register is provided for temporary storage of the result of an ALU
or multiplier operation before feedback to the multiplier or ALU. The data source for
this C register is selected by SRCC; a high on this pin selects the multiplier result;
a low selects the ALU. A separate clock, CLKC, has been provided for this register.

Parity Generators

"
('I)

00
00

I-

(.)

~vLNS
(11

W
tv

Table 8. Independent ALU Operations, Single Operand (19
CHAINED
OPERATION
19

o=

Not
Chained

PRECISION
RA
18
o = A(SP)
1 = A(DP)

PRECISION
RB
17

OUTPUT
SOURCE
16

OPERAND
TYPE
15

ABSOLUTE
VALUE A
14

o=

o=

1 = Single
Operand

O=A
1 = IAI

B(SP)
1 = B(DP)

ALU
result

0, 16 .. 0)
ALU OPERATION
13·10
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

RESULT
Pass A operand
Negate A operand
Integer to floating point
conversion t
Floating point to integer
conversion
Undefined
Undefined
Floating point to floating
point conversion:!:
Undefined
. Wrap (denormal) .input
operand
Undefined
Undefined
Undefined
Unwrap exact number
Unwrap inexact number
Unwrap rounded input
Undefined

tThe precision of the integer to floating point conversion is set by lB.
tThis converts single precision floating point to double precision floating point and vice versa. If the IB pin is low to indicate a single-precision input, the result
of the conversion will be double precision. If the IB pin is high, indicating a double-precision input, the result of the conversion wiU be single precision.

Table 9. Independent ALU Operations, Two Operands (19 = 0, 15 = 0)
CHAINED
OPERATION

PRECISION
RA

19

o=

Not
chained

PRECISION
RB

18

o=

A(SP)
1 = A(OP)

OUTPUT
SOURCE

OPERAND
TYPE

ABSOLUTE
VALUE A

ABSOLUTE
VALUE B

ABSOLUTE
VALUE Y

17

16

15

14

13

12

11-10

RESULT

B(SP)
1 = B(OP)

0= ALU
result

0= Two
operands

O=A
1 = IAI

0= B
1 = IBI

0= V
1 = IVI

00
01
10
11

A + B
A - B
Compare A, B
B - A

o=

Table 10. Independent Multiplier Operations (19 = 0,16
CHAINED
OPERATION

PRECISION
RA

PRECISION
RB

OUTPUT
SOURCE

19

18

17

16

o=

Not
chained

o=

A(SP)
1 = A(OP)

ALU OPERATION

o=

B(SP)
1 = B(OP)

1 = Multiplier
result

=

1)

ABSOLUTE
VALUE A

ABSOLUTE
VALUE B

NEGATE
RESULT

WRAP A

15

14t

13 t

12t

11

0

O=A
1 = IAI

0= B
1 = ;BI

0= V
1 = IVI

tSee Table 15.

CJ1

W
w

SN74ACT8837

o=

Normal
format
1 = A is a
wrapped
number

WRAP B

10

o=

Normal
format
1 = B is a
wrapped
number

Table 11. Independent Multiplier Operations Selected by 14-12 (19
ABSOLUTE
VALUE A
14

ABSOLUTE
VALUE B
13

NEGATE
RESULT
12

0= A
1 = IAI

0= B
1 = I BI

O=Y
1 = -y

fJ)

Z

1)

OPERATION SELECTED

Table 12. Operations Selected by 18-17 (19
PRECISION
SELECT RA
18

0,16

14-12

RESULTS

000
001
010
011
100
101
110
111

A'B
-(A' B)
A * IBI
-(A' IBI)
IAI * B
-(IAI ' B)
IAI • IBI
-(IAI ' IBI)

= 0,

16

=

1)

PRECISION
RAINPUT

PRECISION
SELECT RB
17

PRECISION
RBINPUT

PRECISION'
OF RESULT

0

Single

0

Single

Single

0

Single
Converted
to Double

1

Double

Double

1

Double

0

Single
Converted
to Double

Double

1

Double

1

Double

Double

-...I
~

»
(")
-4
·00
00

eN

-...I

Master/Slave Comparator
A master/slave comparator is provided to compare data bytes from the Y output
multiplexer and the status outputs with data bytes on the external Y and status ports
when DEY, DES and DEC are high. If the data bytes are not equal, a high signal is
generated on the master/slave error output pin (MSERR).

Status and Exception Generator/Register
A status and exception generator produces several output signals to indicate invalid
operations as well as overflow, underflow, nonnumerical and inexact results, in
conformance with IEEE Standard 754-1985. If output registers are enabled
(PIPES2 = 0), status and exception results are latched in a status register on the rising
edge of the clock. Status results are valid at the same time that associated data results
are valid. Status outputs are enabled, by two signals,OEC for comparison status and
DES for other status and exception outputs. Status outputs are summarized in
Tables 14 and 15.
During a compare operation in the ALU, the. AEQ8 output goes high when the A and
B operands are equal. When any operation other than a compare is performed, either
by the ALU or the multiplier, the AEQB signal is used as a zero detect.
5-34

Table 13. Chained Multiplier/ALU Operations (19
CHAINED
PRECISION PRECISION
OPERATION
RA
RB

18

19
1 = Chained

o=

17

A(SP) o = B(SP)
1 = A(DP) 1 = B(DP)

OUTPUT
SOURCE

ADD ZERO

15

16
0= ALU
result
1 = Multiplier
result

MULTIPLY
BY ONE

o=

Normal
operation
1 = Forces
B2 input
of ALU
to zero

(J1

w

(J1

SN74ACT8837

Normal
operation
1 = Forces
B1 input
of multiplier to
one

1)

NEGATE
NEGA TE MUL TIPLiER RESULT
ALU RESULT

13

14

o=

=

o=

Normal
operation
1 = Negate
ALU
result

ALU
OPERATIONS

12

11-10

Normal
operation
1 = Negate
multiplier
result

00
01
10
11

o=

RESULT

A
A
2
B

+ B
- B
- A
- A

Table 14. Comparison Status Outputs
SIGNAL
AEQB

RESULT OF COMPARISON (ACTIVE HIGH)
The A and B operands are equal. (A high signal on the AEQB output indicates a
zero result from the selected source except during a compare operation in the
ALU.)

AGTB

The A operand is greater than the B .operand. (Only during a compare operation
in the ALU)

UNORD

The two inputs of a comparison operation are unordered, i.e., one or both of
the inputs is a NaN.

Table 15. Status Outputs
SIGNAL
CHEX

DENIN

DENORM

en

z-..J

-t

00
00
eN
-..J

Input to the multiplier is a denorm. When DENIN goes high, the STEX pins
indicate which port had a denormal input.
The multiplier output is a wrapped number or the ALU output is a denorm. In
the FAST mode, this condition causes the result to go to zero.

INEX

The result of an operation is not exact.

IVAL

A NaN has been input to the multiplier or the ALU, or an invalid operation
(0
00 or ± 00+ 00) has been requested. When IVAL goes high, the STEX
pins indicate which port had a NaN.

OVER

The result is greater than the largest allowable value for the specified format.

~

»
(")

STATUS RESULT
If 16 is low, indicates the multiplier is the source of an exception during a
chained function. If 16 is high, indicates the ALU is the source of an exception
during a chained function.

*

RNDCO

The mantissa of a wrapped number has been increased in magnitude by
rounding and the unwrap round instruction can be used to unwrap properly
the wrapped number (see Table 8).

SRCEX

The status was generated by the multiplier. (When SRCEX is low, the status
was generated by the ALU.)

STEXO

A NaN or a denorm has been input on the B port.

STEX1

A NaN or a denorm has been input on the A port.

UNDER

The result is inexact and less than the minimum allowable value for the
specified format. In the FAST mode, this condition causes the result to go to
zero.

5-36

In chained mode, status results to be output are selected based on the state of the
16 (source output) pin (if 16 is low, ALU status will be selected; if 16 is high, multiplier
status will be selected). If the nonselected output source generates an exception, CHEX
is set high. Status of the nonselected output source can be forced using the SELST
pins, as shown in Table 16.
Table 16. Status Output Selection (Chain Mode)
SELST1SELSTO
00
01
10
11

STATUS SELECTED
Invalid
Selects multiplier status
Selects ALU status
Normal operation (selection based on result source specified by 16 input)

Flowthrough Mode
To enable the device to operate in pipelined or flowthrough modes, registers can be
bypassed using pipeline control signals PIPES2-PIPESO (see Table 17).
Table 17. Pipeline Controls (PIPES2-PIPESO)
PIPES2PIPESO
X X 0

Enables input registers (RA, RB)

X X 1

Disables input registers (RA, RB)

X 0 X

Enables pipeline registers

REGISTER OPERATION SELECTED

X 1 X

Disables pipeline registers

0 X X

Enables output registers (P, S, Status)

1 X X

Disables output registers (P, S, Status)

I"

M
CO
CO
I-

U

«
o::t
I"

2

en

FAST and IEEE Modes
The device can be programmed to operate in FAST mode by asserting the FAST pin.
In the FAST mode, all denormalized inputs and outputs are forced to zero.
Placing a zero on the FAST pin causes the chip to operate in IEEE mode. In this mode,
the ALU can operate on denormalized inputs and return denormals. If a denorm is input
to the multiplier, the DENIN flag will be asserted, and the result will be invalid. If the
multiplier result underflows, a wrapped number will be output.

5-37

Rounding Mode
The' ACT8837 supports the four IEEE standard rounding modes: round to nearest,
round towards zero (truncate), round towards infinity (round up), and round towards
minus infinity (round down). The rounding function is selected by control pins RND1
and RNDO, as shown in Table 18.
Table 18. Rounding Modes
RND1-

ROUNDING MODE SELECTED

RNDO

o

0
0 1
1 0
1 1

Round towards nearest
Round towards zero (truncate)
Round towards infinity (round up)
Round towards negative infinity (round down)

Test Pins
Two pins, TP1-TPO, support system testing. These may be used, for example, to place
all outputs in a high·impedance state, isolating the chip from the rest of the system
(see Table 19).
Table 19. Test Pin Control Inputs
TP1-

:2

0 0
0 1
1 0
1 1

-...J
~

»
("')
~

CO
CO
W
-...J

OPERATION

TPO

(J)

All outputs and liDs are

forc~d

low

All outputs and liDs are forced high
All outputs are placed in a high impedance state '
Normal operation

Summary of Control Inputs
Control input signals for the' ACT8837 are summarized in Table 20.

5-38

Table 20. Control Inputs
SIGNAL
BYTEP

lOW

HIGH
Selects byte parity generation
and test

Selects single bit parity generation
and test

Clocks all registers except C

No effect

Clocks C register

No effect

CLKMODE

Enables temporary input register
load on falling clock edge

Enables temporary input register load
on rising clock edge

CONFIG1CONFIGO

See Table 3 (RA and RB register
data source selects)

See Table 3 (RA and RB register data
source selects)

ENRA

If register is not in flow through,
enables clocking RA register

If register is not in flow through, holds
contents of RA register

ENRB

If register is not in flow through,
enables clocking of RB register

If register is not in flow through, holds
contents of RB register

FAST

Places device in FAST mode

Places device in IEEE mode

HALT

No effect

Stalls device operation but does not
affect registers, internal states, or
status

OEC

Disables compare pins

Enables compare pins

OES

Disables status outputs

Enables status outputs

OEY

Disables Y bus

Enables Y bus

See Table 17 (pipeline mode
control)

See Table 17 (pipeline mode control)

No effect

Clears internal states and status but
does not affect data registers

ClK
CLKC

PIPES2PIPESO
RESET

RND1RNDO
SELOP7SELOPO
SElMS/LS

SELSTlSELSTO
SRCC
TP1-TPO

,....
M

00
00

....

See Table 18 (rounding mode
control)

See Table 18 (rounding mode control)

See Tables 6 and 7
(multiplierl ALU operand selection)

See Tables 6 and 7 (multiplier/ALU
operand selection)

Selects MSH of 64-bit result for
output on the Y bus

Selects lSH of 64-bit result for output
on the Y bus (no effect during single
precision operation)

See Table 15 (status output
selection)

See Table 15 (status output sel.ection)

Selects multiplier result for input
to C register

Selects ALU result for input to C
register

See Table 19 (test pin control
inputs)

See Table 19 (test pin control inputs)

U

0

Table 21. IEEE Floating-Point Representations
TYPE OF
OPERAND
Normalized
Number (max)
Normalized
Number (min)
Denormalized
Number (max)
Denormalized
Number (min)
Wrapped
Number (max)
Wrapped
Number (min)
Zero
Infinity
NAN (Not a
Number
ts

sign bit

EXPONENT (e)
SP (HEX)
DP (HEX)

FRACTION (f)
(BINARY)

HIDDEN
BIT

VALUE OF NUMBER REPRESENTED
SP (DECIMAl) t
DP (DECIMAL) t

FE

7FE

All 1'5

1

(-1)5 (2127) (2-2 -23)

( - 1)5 (2 1023) (2 - 2 - 52)

01

001

All 0'5

1

( - 1)5 (2- 126) (1)

(-1)5 (2- 1022 ) (1)

00

000

All 1 '5

0

(1-)5 (2- 126) (1-2~23)

( - 1)5 (2 - 1022) (1 - 2 - 52)

00

000

000 ... 001

0

( - 1)5 (2 - 126) (2 - 23)

(-1)5 (2-1022) (2-52)

00

000

All 1 '5

1

(- 1)5 (2 - 127) (2 - 2 - 23)

( - 1)5 (2 - 1023) (2 - 2 - 52)

EA

7eD

An 0'5

1

(-1)5 (2-22+127) (1)

( - 1)5 (2 - 51 + 1023) (1)

00

000

Zero

0

(-1)5 (0.0)

(-1)5 (0.0)

FF

7FF

Zero

1

( - 1) 5 (infinity)

( - 1)5 (infinity)

FF

7FF

Nonzero

N/A
----

- - - -

None
-

- - -----_ .. _-- - -

None
--

--- 1..---

___

~-

IEEE formats for floating-point operands, both single and double precision, consist of
three fields: sign, exponent, and fraction, in that order. The leftmost (most significant)
bit is the sign bit. The exponent field is eight bits long in single-precision operands
and 11 bits long in double-precision operands. The fraction field is 23 bits in single
precision and 52 bits in double precision. Further details of IEEE formats and exceptions
are provided in the IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE
Std 754-1985.
Several status exceptions are generated by illegal data or instruction inputs to the FPU.
Input exceptions may cause the following signals to be set high: IVAL, DENIN, and
STEX1-STEXO. If the IVAL flag is set, either an invalid operation has been requested
or a NaN (Not a Number) has been input. When DENIN is set, a denormalized number
has been input to the multiplier. STEX 1-STEXO indicate which port (RA, RB, or both)
is the source of the exception when either a denormal is input to the multiplier
(DEN IN = H) or a NaN (lVAL = H) is input to the multiplier or the ALU.
NaN inputs are all treated as IEEE signaling NaNs, causing the IVAL flag to be set.
When output from the FPU, the fraction field from a NaN is set high (all 1 's), regardless
of the original fraction field of the input NaN.
Output exception signals· are provided to indicate both the source and type of the
exception. DENORM, INEX, OVER, UNDER, and RNDCO indicate the exception type,
and CHEX and SRCEX indicate the source of an exception. SRCEX indicates the source
of a result as selected by instruction bit 16, and SRCEX is active whenever a result
is output, not only when an exception is being signaled. The chained-mode exception
signal CHEX indicates that an exception has be generated by the source not selected "
for output by 16. The exception type signaled by CHEX cannot be read unless status M
select controls SELST1 -SELSTO are be used to force status output from the deselected ~
source.

...

(.)

«

Output exceptions may be due either to a result in an illegal format or to a procedural
error. Results too large or too small to be represented in the selected precision are ~
signalled by OVER and UNDER. Any ALU output which has been increased in magnitude
by rounding causes INEX to be set high. DENORM is set when the multiplier output
is wrapped or the ALU output is denormalized. Wrapped outputs from the multiplier
may be inexact or increased in magnitude by rounding, which may cause the INEX
and RNDCO status signals to be set high. A denormal output from the ALU
(DENORM = H) may also cause INEX to be set, in which case UNDER is also signalled.

"
en
z

Handling of Denormalized Numbers (FAST)
The FAST input selects the mode for handling denormalized inputs and outputs. When
the FAST input is set low, the ALU accepts denormalized inputs but the multiplier
generates an exception when a denormal is input. When FAST is set high, the DENIN
status exception is disabled and all denormalized numbers, both inputs and results,
are forced to zero.

5A5

A denormalized input has the form of a floating-point number with a zero exponent,
a nonzero mantissa, and a zero in the leftmost bit of the mantissa (hidden or implicit
bit). A denormalized number results from decrementing the biased exponent field to
zero before normalization is complete. Since a denormalized number cannot be input
to the multiplier, it must first be converted to a wrapped number by the ALU. When
the mantissa of the denormal is normalized by shifting it left, the exponent field
decrements from all zeros (wraps past zero) to a negative two's complement number
(except in the case of .IXXX ... ,where the exponent is not decremented).
Exponent underflow is possible during multiplication of small operands even when the
operands are not wrapped numbers. Setting FAST = L selects gradual underflow so
that denormal inputs can be wrapped and wrapped results are not automatically
discarded. When FAST is set high, denormal inputs and wrapped results are forced
to zero immediately.
When the multiplier is in IEEE mode and produces a wrapped number as its result,
the result may be passed to the ALU .and unwrapped. If the wrapped number can be
unwrapped to an exact denormal, it can be output without causing the underflow status
flag (UNDER) to beset. UNDER goes high when a result is an inexact denormal, and
a zero is output from the FPU if the wrapped result is too small to represent as a
denormal (smaller than the minimum denorm). Table 22 describes the handling of
wrapped multiplier results and the status flags that are set when wrapped numbers
are output from the multiplier.

Table 22. Handling Wrapped Multiplier Outputs

(J)

2
.....,
~

»

C')

-f

00
00
W
.....,

TYPE
OF RESULT
Wrapped,
exact

DENORM

STATUS FLAGS SET
INEX
RNDCO

UNDER

NOTES

1

0

0

0

Unwrap with 'Wrapped
exact' ALU instru.ction

Wrapped,
inexact

1

1

0

1

Unwrap with 'Wrapped
inexact' ALU instruction

Wrapped,
increased in
magnitude by
rounding

1

1

1

1

Unwrap with 'Wrapped
rounded' ALU instruction

When operating in chained mode, the multiplier may output a wrapped result to the
ALU during the same clock cycle that the multiplier status is output. In such a case
the ALU cannot unwrap the operand prior to using it, for example, when accumulating
the results of previous multiplications. To avoid this situation, the FPU can be operated
in FAST mode to simplify exception handling during chained operations. Otherwise,
wrapped outputs from the multiplier may adversely affect the accuracy of the chained
operation, because a wrapped number may appear to be a large normalized number
instead of a very small denormalized number.

5-46

Because of the latency associated with interpreting the FPU status outputs and
determining how to process the wrapped output, it is necessary that a wrapped operand
be stored external to the FPU (for example, in an external register file) and reloaded
to the A port of the ALU for unwrapping and further processing.

Data Output Controls (SELMS/LS, OEY)
Selection and duration of results from the Y output multiplexer may be affected by
several factors, including the operation selected, precision of the operands, registers
enabled, and the next operation to be performed. The data output controls are not
registered with the data and instruction inp"uts. When the device is microprogrammed,
the effects of pipelining and sequencing of operations should be taken into account.
Two particular conditions need to be considered. Depending on which registers are
enabled, an offset of one or more cycles must be allowed before a valid result is available
at the Y output multiplexer. Also, certain sequences of operations may require both
halves of a double-precision result to be read out within a single clock cycle. This is
done by toggling the SELMS/LS signal in the middle of the clock period.
When a single-precision result is output, the SELMS/LS signal has no effect. The
SELMS/LS signal is set low only to read out the LSH of a double-precision result.
Whenever this signal is selecting a valid result for output on the Y bus, the OEY enable
must be pulled low at the beginning of that clock cycle.

Status Output Controls (SELST1-SELSTO, OESiOEC)
Ordinarily, SELSTl-SELSTO are set high so that status selection defaults to the output
source selected by instruction input 16. The ALU is selected as the output source when
16 is low, and the multiplier when 16 is high.
When the device operates in chained mode, it may be necessary to read the status
results not associated with the output source. As shown in Table 16, SELSTl-SELSTO
can be used to read the status of either the ALU or t!1e multiplier regardless of the
16 setting.
Status results are registered only when the output (P and S) registers are enabled
(PIPES2 = L). Otherwise, the status register is transparent. In either case, status
outputs can be read by pulling the output enables low (OES, OEC, or both).

Stalling the Device (HALT)
Operation of the' ACT8837 can be stalled nondestructively by means of the HALT
signal. Pulling the HALT input low causes the device to stall on the next low level
of the clock. Register contents are unaltered when the device is stalled, and nor'11al
operation resumes at the next low clock period after the HALT signal is set high. Using
HALT in microprograms can save pow.er, especially using high clock frequencies and
pipe lined stages.

5-47

,....

M

00
00

t-

U

«'¢

,...,.
:2
tI'J

For some operations, such as a double-precision multiply with CLKMODE = 1, setting
the HALT input low may interrupt loading of the RA. RB, and instruction registers,
as well as stalling operation. In clock mode 1, the temporary register loads on the falling
edge of the clock, but the HALT signal going low would prevent the RA, RB, and
instruction registers from loading on the next rising clock edge. It is therefore necessary
to have the instruction and data inputs on the pins when the HALT signal is set high
again and normal operation resumes.

Instruction Inputs (19-10)
Three modes of operation can be selected' with inputs /9-10, including independent
ALU operation, independent multiplier operation, or simultaneous (chained) operation
of ALU and multiplier. Each operating mode is treated separately in the following
sections.

Independent ALU Operations
The ALU executes single- and double-precision operations which can be divided
according to the number of operands involved, one or two. The ALU accepts integer,
normalized, and de normalized numbers as operands. Table 22 shows independent ALU
operations with one operand, along with the inputs 19-10 which select.each operation.
Conversions from one format to another are handled in this mode, with the exception
of adjustments to precision during two-operand ALU operations. Wrapping and
unwrapping of operands is also done in this mode.

VJ
Z
-...J

~

(")

-f

ex>
ex>

w

-...J

Table 24 presents independent ALU operations with two operands. When the operands
are different in precision, one single and the other double, the settings of the precisionselects 18-17 will identify the single-precision operand so that it can automatically be
reformatted to double precision before the selected operation is executed, and the
result of the operation will be double precision.

Independent Multiplier Operations
In this mode the multiplier operates on the RA and RB inputs which can be either single
precision, double precision, or mixed. Operands may be normalized or wrapped
numbers, as indicated by the settings for instruction inputs 11-10. As shown in Table 25,
the multiplier can be set to operate on the absolute value of either or both operands,
and the result of any operation can be negated when it is output from the multiplier.
Converting a single-precision denormal number to double precision does not normalize
or wrap the denormal, so it is still an invalid input to the multiplier.

5-48

Table 23. Independent ALU Operations with One Operand
ALU OPERATION
ON A OPERAND
Pass A operand

INSTRUCTION
INPUTS 19·10
Ox 001x 0000

Negate A operand
Convert from integer to
floating point t

Ox 001x 0001
Ox 0010 0010

Convert from floating
point to integer

Ox 001x 0011

Undefined

Ox 001 x 0100

Undefined

Ox 001 x 0101

Convert from floating
point to floating point
(adjusts precision of
input: SP-OP, OP-SP)

Ox 001x 0110

Undefined

OxOOlxOl11

Wrap denormal operand

Ox 001x 1000

Undefined

Ox 001x 1001

x = Don't care
18 selects precision of A operand:
a = A (SP)
1 = A (OP)
14 selects absolute value of A operand:
O=A

Undefined
Undefined

NOTES

I

1 = IAI
During integer to floating point conversion,
I A I is not· allowed as a result.

Ox 001x 1010
Ox 001x 1011

Unwrap exact number

OxOOlxll00

Unwrap inexact number

Ox 001 x 1101

Unwrap rounded input

Ox 001x 1110

Undefined

Ox 001 x 1111

t During this operation. 18 selects precision of the result.

5-49

Table 24. Independent ALU Operations with Two Operands
ALU OPERATIONS

INSTRUCTION

AND OPERANDS

INPUTS 19-10

NOTES

Add A + B

Ox xOOO OxOO

Add IAI + B

Ox x001 OxOO

Add A + IBI

OX xOOO 1xOO

Add IAI + IBI
Subtract A - B

Ox xOOO Ox01

18 selects precision of A operand:

Subtract I A I - B

Ox x001 Ox01

o=

Subtract A -

Ox xOOO lxOl

1 = A (DP)

OX x001 1xOO

IBI

x = Don't Care

A (SP)

Ox x001 1 x01

17 selects precision of B operand:

Compare A, B

Ox xOOO Ox10

o=

Compare I A I, B

Ox x001 Ox10

1 = B (DP)

Compare A, I B I

Ox xOOO 1x10

12 selects either V or its absolute value:

Compare IAI, IBI
Subtract B - A

OX x001 1 x1 a

0= V

Ox xOOO Ox11

1 = IVI

Subtract B-1 A I

Ox x001 Ox11

Subtract I A I -

IB

Subtract I B I - A

Ox xOOO 1 x11

Subtract I B I - I AI

Oxx0011x11

B (SP)

Table 25. Independent Multiplier Operations
MULTIPLIER OPRATION
AND OPERANDS

*B
* B)
Multiply A * I B I
Multiply -(A * IBI)
Multiply I A I * B
Multiply - ( I A I * B)
Multiply I A I * IBI
Multiply - ( I A I * IBI)

INSTRUCTION
INPUTS 19-10

NOTES

Multiply A

Ox x100 OOxx

x = Don't Care

Multiply - (A

Ox x100 01xx

18 selects A operand
precision (0 = SP, 1 = DP)

Ox x100 10xx
OX x100 11 xx
Oxx10100xx
Ox x101 01xx
OX x101 10xx
Oxx101 11xx

17 selects B operand
precision (0 = SP; 1 = DP)
11 selects A operand format
(0 = Normal, 1 = Wrapped)
10 selects B operand format
(0 = Normal, 1 = Wrapped)

Chained Multiplier/ALU Operations
In chained mode, the' ACT8837 performs simultaneous operations in the multiplier
and the ALU. Operations include addition, subtraction, and multiplication, except
multiplication of wrapped operands. Several optional operations also increase the
flexibility of the device.
The B operand to the ALU can be set to zero so that the ALU passes the A operand
unaltered. The B operand to the multiplier can be .forced to the value 1 so that the
A operand to the multiplier is passed unaltered (see Table 26).
Table 26. Chained Multiplier/ALU Operations
CHAINED OPERATIONS
MULTIPLIER
ALU

OUTPUT
SOURCE

INSTRUCTION
INPUTS 19·10

A+B

ALU

lx xOOO xxOO

A * B

A + B

Multiplier

lx xl00 xxOO

A * B

A-B

ALU

lx xOOO xxOl

A*B

A - B

Multiplier

1 x xl00 xxOl

A * B

2 - A

ALU

lx xOOO xxl0

x

A*B

2 - A

Multiplier

1 x xl00 xxl 0

A * B

NOTES

=

Don't Care

A*B

B-A

ALU

1 x xOOO xxll

18. selects precision of
RA inputs:

A*B

B-A

Multiplier

1 x xl 00 xx 11

o=

RA (SP)

A * B

A + 0

ALU

lx xOl0 xxOO

1

RA (DP

A*B

A +0

Multiplier

lx xll0 xxOO

=

ALU

lxx010xxll

17 selects precision of
RB inputs:

Multiplier

1 x x 11 0 xx 11

o=

RB (SP)

A + B

AlU

lx xOOl xxOO

1

RB (DP)

A + B

Multiplier

lx xl0l xxOO

13 negates ALU result:

A - B

ALU

1 x xOOl xxOl

o=

Normal

Multiplier

lx xl0l xxOl

1

Negated

12 negates multiplier
result:

A * B

o -'

A * B

0- A

A * 1
A * 1
A * 1

A

A * 1

A - B

=

=

A * 1

2 - A

ALU

1 x xOOl xxl0

A * 1

2 - A

Multiplier

1 x xl 01 xxl0

A * 1

B-A

AlU

lxxOOlxxll

o=

Normal

1

Negated

A * 1

B-A

Multiplier

1 x xl0l xx 11

A * 1

A+O

AlU

.1 x xOll xxOO

A * 1

A+O

Multiplier

lx xll1 xxOO

A * 1

0- A

AlU

lxxOl1xxll

A * 1

0- A

Multiplier

lXxl11 xxll

=

5·51

MICROPROGRAMMING THE ' ACT8837
Because the' ACTSS37 is microprogrammable, it can be configured to operate on either
single- or double-precision data operands, and the operations of the registers, ALU,
and multiplier can be programmed to support a variety of applications. The following
examples present not only control settings but the timings of the specific operations
required to execute the sample instructions.
Timing of the sample operations varies with the precision of the data operands and
the settings of CLKMODE and PIPES. Microinstructions and timing waveforms are given
for all combinations of data precision, clock mode, and register settings. Following
the presentation of ALU and multiplier operations is a brief sum-of-products operation
using instructions for chained operating mode.

Single-Precision Operations
Two single-precision operands can be loaded on the 32-bit input buses without use
of the temporary register so CLKMODE has no effect on single-precision operation.
Both the ALU and the multiplier execute all single-precision instructions in one clock
cycle, assuming that the device is not operating in flowthrough mode (all registers
disabled). Settings of the register controls PIPES2-PIPESO determine minimum cycle
time and the rate of data throughput, as evident from the examples below.

Single-Precision ALU Operations

~
......
~

l>

n

-I
CO
CO

Precision of each data operand is indicated by the setting of instruction input IS for
single-operand ALU instructions, or the settings of IS-17 for two-operand instructions.
When the ALU receives mixed-precision operands (one operand in single precision and
the other in double precision). the single-precision data input is converted to double
and the operation is executed in double precision.
If both operands are single precision, a single-precision result is output by the ALU.
Operations on mixed-precision data inputs produce double-precision results.

W
...... It is unnecessary to use the 'convert float-to-float' instruction to convert the single-

precision operand prior to performing the desired operation on the mixed-precision
operands. Setting IS and 17 properly achieves the same effect without wasting an
instruction cycle.

Single-Precision Multiplier Operations
Operand precision is selected by IS and 17, as for ALU operations. The multiplier can
multiply the A and B operands, either operand with the absolute value of the other,
or the absolute values of both operands. The result can also be negated when it is
output. If both operands are single precision, a single-precision result is output.
Operations on mixed-precision data inputs produce double-precision results.

5-52

Sample Single-Precision Microinstructions
The following four single-precision microinstruction coding examples show the four
register settings, ranging from flowthrough to fully pipelined. Timing diagrams
accompany the sample microinstructions.
In the first example PIPES2-PIPESO are all set high so the internal registers are all
disabled. This microinstruction sets up a wrapped result from the multiplier to be
unwrapped by the ALU as an exact denormalized number. In flowthrough mode the
'unwrap exact' operation is performed without a clock as Soon as the instruction is
input. Single-precision timing in flowthrough mode is shown in Figure 2.
CLKMODE

=

0

C
L
K
M
0
D
E

I I
9-0

=

PIPES

CC
00 PP
NN I I
FF PP
II E E
GG SS
1-02-0

00 0010 1100 0 01

Operation: Unwrap A operand exact

111

SS
EE
LL
00
PP
7-0

RR
NN
DD
1-0

111 xxxx 11 xx 00

FIRST INSTRUCTION

S
E
L
M
S S
S
BEE R
FEE S /
Y L L EH
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1-0 T T 1-0
0 1 1 0 1 0 0 0 x 11

1 1 11

.....

M
CO
CO

SECOND INSTRUCTION

I-"

(J

INSTRUCTION: FUNC{9,O), RND{1,O), FAST

===><~

____

FIR_S_T_O_PE_R_AN_D_S____

-J)(~____S_E_CO_N_D_O_PE_R_AN_D_S__--J)(~_______________

DATA{31,O) A AND B INPUTS
FIRST ~ SECOND ~
RESULT ~ RESULT ~

~tpd1----+1

~tpd1~

OUTPUT{31,O), STATUS{13,O)

Figure 2. Single-Precision Operation, All Registers Disabled
(PIPES - 111, CLKMODE == 0)

5-53

«
"d'

"enZ

The second example shows a microinstruction causing the ALU to compare absolute
values of A and B. Only the input registers are enabled (PIPE52-PIPE50 = 110) so
the result is output in one clock cycle.
CLKMODE = 0

PIPE5=110

C
L
K
M
0
D
E

I I
9-0
000001 1010

CC
00 P P
NN I I
FF PP
II EE
G G 55
1-02-0

o 01

Operation: Compare IA I' IB I

55
EE
LL
00
PP
7-0

5
E
L
M
5

RR
NN
DD
1-0

110 xxxx 1111 00

55
BEE R
FEE 5 I
Y L L EH
ANNR
000T55SATT
5RRCLEEEETTELPP
TAB C 5 Y C 5 P 1 -0 T T 1.,..0

o1

10 1 0 0 0 x 11

Load First Operands
Begin First Operation

Load Second Operands
Begin Second Operation

~

~

1 1 11

en elK 1
Z ,.-_-i-'_""
.....
.j::lo

l>

I
~tsu1-t1.-"'''+-1 th1

,,
,

(")

-i

00
00
W

I

..... ( OP~:!~DS ~ o~~~~~~s ~
I+-tsu2 ..... th1~
DATA(31,O) A AND B INPUTS

...
tpd1---"'~
OUT(31,O) STATUS(13.0)

~tsu2""'''~~I--~''I-th1

I + l f - - - tpd2---+l"1

Figure 3. Single-Precision Operation, Input Registers Enabled
(PIPES - 110, CLKMODE - 0)

5-54

Input and output registers are enabled in the third example, which shows the subtraction
B. - A. Two clock cycles are required to load the operands, execute the subtraction,
and output the result (see Figure 4).
CLKMOOE = 0

PIPES = 010

C
L
K
M
0
I I
9-0
0000000011

elK

CC
00 P P
NN I I
FF PP
II EE
oGG SS
E 1-02-0

o 01

Operation:

SS
EE
LL
00
PP
7-0

Subtract B - A
S
E
L
M
S S
S
BEE R
FEE S I
Y L L EH
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1 -0 T T 1-0

RR
NN
DO
1-0

010 xxx x 1111 00

00001 OOOx 11

load First Operands
Begin First Operation

load Second Operands
Begin Second Operation

~

~

1 1 11

I

It-------td1-------+l~1
I

I

"

M

00
00

....
«

u

~~

CJ)

l4-t su 2 ........t h1+l
DATA(31.0) A AND B INPUTS

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _>@

Load Rest
of First
Operands

I

ClK

Operation: Subtract IBI - IAI

11 110 xxxx 1111 00

Load half
of First
Operands

~

= 110

THIRD INSTRUCTION

SECOND INSTRUCTION

I

I+- th1 ~ 14---* tsu1

~NDI1.0). FAST
:

I
I4-tsu2~ I+--tsu2~ I+--tsu2~'"

th1
thl
OATAI3l.0) A AND B INPUTS

~

thl

\4- t su 2-t1+-th1-.t

~th1~ ~tsu2*-*thl

tsu2

SELMS/lS

OUTI3l.0) STATUSI13.0)

14---+1
tpd2

Figure 11. Double-Precision ALU Operation, Input Registers Enabled
(PIPES - 110, CLKMODE - 11
5-68

The third example shows a single denormalized operand being wrapped so that it can
be input to the multiplier. Both input and output registers are enabled
(PIPES2-PIPESO = 010). Timing is shown in Figure 12.
CLKMODE = 1

I I
9-0
01 1010 1000

PIPES = 010

C
L
K
M
0
D
E

CC
00 P P
NN I I
FF PP
II E E
GG SS
1-02-0

Operation: Wrap Denormal Input

SS
EE
LL
00
PP
7-0

RR
NN
DD
1-0

11 010 xxxx.l1xx 00

S
E
L
M
S S
BEE R
S
Y L L EH
FEE S /
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1 -0 TTl -0

o1

0 0 x 0 0 0 x xxl 1 11

5-69

L£881.~"vLNS
(11

~

load HaH
of First
Operands

Begin First
Operation

load Half
of Second
Operands

load Rest
of Second
Operands
Begin Second
Operation
load Output

~

~

~

~

o

load Rest
of First
Operands

1

~r------'I
I

I

r--I----,

•

I

ClK

I

'I"

I
I
FIRST INSTRUCTION

I

td3----~
.1

SECOND INSTRUCTION

I
th1~ ~tsu1-+f

W-- t su1-+1

THIRD INSTRUCTION

I.- th1 +I j4- t su1-+1

I

~th1-+1

INSTRUCTION: FUNC(9.01. RND(1.01. FAST
I
I

HALF
1ST OPS

t su2"

HALF
2ND OPS

~

th1

I
.. I.-tsu2----'"
th1

REST
2ND OPS

..--tsu2~1h1-+1 ~

tsu2

HALF
3RD OPS

th1 -+I 14
....
tsu2

REST
3RD OPS

th1 -+114+14- th1 - + I
tsu2

DATA(31.01 A AND B INPUTS

'-------'r

n

-

SElMS/lS

OUT(31.0) STATUS(13.01

~

14--+1

14--+1

~

tpd4

tpd5

tpd4

tpd5

Figure 12. Double-Precision ALU Operation, Input and Output Registers Enabled
(PIPES = 010, CLKMODE - 1)

L

The fourth example shows a conversion from integer to floating point format. All three
levels of data registers are enabled (PIPES2-PIPESO) so that the FPU is fully pipelined
in this mode (see Figure 13).
CLKMODE = 1

PIPES = 000

Operation: Convert Integer to Floating Point

S
C CC
L 00 P P

K NN I I
M FF PP

o

I I

9-0

II E E
D GG SS
E 1-02-0

SS
EE
LL
00
PP

7-0

RR
NN
DD
1 -0

01 10100010 0 11 000 xxxx 1100 00

E
L
M
SS
S
BEE R
FEES/
YLLEH
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1-0 T T 1-0

0 1 1 x x 0 0 0 x xx

1 1 11

5-71

L€881.:lVtrLNS
(J1

Load Rest
of Third
Operands

~

N

Load Half
of First
Operands

Load Rest
of First
Operands

Load Rest Load Half
Load Half of Second of Third
Operands
Begin First of Second Operands
Operation Operands
ad Pipeline

•
•
•
J
I I
I

14

CLK

td2

r 1
I
~

td2

Begin Third
Operation
Load Pipeline
Load Output

•I

r

~I

I
FIRST
INSTRUCTION

tsu1~

I
th1~

SECOND
INSTRUCTION

I4---+t- t su1

THIRD
INSTRUCTION

th1~ t4----* t su1

FOURTH
INSTRUCTION

th1-!+--+1 t4----* t su1

th1-l4---+t

INSTRUCTION: FUNC(9,O), RND(1,O), FAST
I
I

I

14 ~.. ~ 14 ~14 ~ 14 ~\4 ~ ,4 ~'4 ~'14 ~I" ~I ,4 ~14 ~I 14 ~,.. ~I '4 ~,..
~I
tsu2 th1 tsu2 th1
tsu2 th1
tsu2 th1 tsu2 th1 tsu2 th1
tsu2 th1 tsu2 th1
DATA(31,O) A AND B INPUTS

~I-l
SELMS/LS

OUT(31 ,0) STATUS(13,O)

tpd4~

tpdS-l4'-+I tpd4~ tpdS......-.t

Figure 13. Double-Precision ALU Operation, All Registers Enabled
(PIPES '" 000, CLKMODE = 1)

tpd4......-.t tpds~

L

Double-Precision Multiplier Operations
Independent multiplier operations may also be performed in either clock mode and with
various registers enabled. As before, examples for the two clock modes are treated
separately. A double-precision multiply operation requires two clock cycles to execute
(except in flowthrough mode) and from one to three other clock cycles to load the
temporary register and to output the results, depending on the setting of
PIPES2-PIPESO.
Even in flowthrough mode (PIPES2-PIPESO = 111) two clock edges are required, the
first to load half of the operands inthe temporary register and the second to load the
intermediate product in the multiplier pipeline register. Depending on the setting of
CLKMODE, loading the temporary register may be done on either a rising or a falling
edge.

Double-Precision Multiplication with CLKMODE

=

0

In this first example, the A operand is multiplied by the absolute value of 8 operand.
Timing for the operation is shown in Figure 14:
CLKMODE

=0

PIPES = 111

Operation: Multiply A

ecc
PP
I I
PP
EE
SS

SS
EE
LL
00
PP

RR
NN
DO

E 1-02-0

7-0

1-0

L
K
M
0
I I

9-0
01 11001000

o

o

00
NN
FF
II
GG

11 111 1111 xxx x 00

* 181

S
E
L
S5
M
8 EE R
S
Y L L EH
FEE S /
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
T A 8 C S Y C S P 1-0 T T 1-0

ox

x x x 0 0 0 x xx

1 1 11

,....
M
CO'
CO

IU



load Rest
of First
Operands

load Half
of Third
Operands

load Half
of Second
Operands

Begin Second
Operetion

load Pipeline

load Half
of First
Operands

Begin First
Operation

load Pipeline

load Pipeline

load Output

+

+

+

~

~

I

.'4

I+-td2
,

ClK

I

.'4

td2

td2 ~

I

I

th1~
I

I+-tsu1~

THIRD
INSTRUCTION

SECOND
INSTRUCTION

FIRST
INSTRUCTION

~tsu1

I+-th1~

., tsu1

t h 1 - ' - 14

,

INSTRUCTION: FUNC{9.0). RND'1.01. FAST
I

~tsu2~

th1

14

tsu2

tM

tsu2

th1

tsu2

th1

.14

tsu2

.'4 th1 ~

., 14

th 1

tsu2

DATA(31,OI A ANDB INPUTS

SElMS/LS

------------------------------------------------------------~
OUT(31.0) STATUS{13,OI
14-----1>1
14-----1>1
14-----1>1
~

tpd4

tpd5

tpd4

Figure 17. Double-Precision Multiplier Operation, All Registers Enabled
(PIPES - 000, CLKMODE - 0)

tpd5

Double-Precision Multiplication with CLKMODE

=

1

Setting the CLKMOOE control high causes the temporary register to load on the falling
edge of the clock. This permits loading both double-precision operands within the same
clock cycle. The time available to output the result is also affected by the settings
of ClKMOOE and PIPES2-PIPESO, as shown in the individual timing waveforms.
The first multiplication example with CLKMOOE set high shows a multiplication in
flowthrough mode (PIPES2-PIPESO = 111). Figure 18 shows the timing for this
operating mode:
CLKMODE

I I
9-0

=1

PIPES

C
L
K
M
0
D
E

= 111

CC
00 P P
NN I I
FF PP
EE
GG SS
1-02-0

"

Operation: Multiply A

SS
EE
LL
00
PP
7-0

RR
NN
DO
1-0

01 1100 1000 1 11 111 1111 xxxx 00

*

181

S
E
L
M
S S
8 EE R
S
FEE S I
Y L L EH
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
T A 8 C S Y C S P 1-0 T T 1-0
0 x x x x 0 0 0 x xx

1 1 11

5-79

Load Half
of Operands

Load Pipeline

+

+

L

I

eLK

:

(

I~STRUCTION

FIRST

'
I

I+- t su1-.l

I
I
I
I

INSTRUCTION: FUNC(9.0). RND(1.0). FAST

< l~:~~S )(~_l_:_i_~~~s________________~:______________________________
I+- tsu2~ '4

tsu3-----.t~:

th1
DATA(31.0) A AND B INPUTS

SELMS/LS

~

-----------------------------'~
OUT(31.0) STATUS(13.0)
Figure 18; Double-Precision Multiplier Operation, All Registers Disabled
(PIPES .. 111. CLKMODE = 1)

en

z

t

...,j

C')

-I
00
00

In the second example, the input registers are enabled and the instruction is otherwise
similar to the corresponding example for CLKMODE = O. Timing is shown in Figure 19.
CLKMODE = 1

PIPES

=

110

Operation: Multiply - ( IA I

* B)

eN
...,j

S
E
C
L
K
M

I I

9-0

CC
00 P P
NN I I
FF PP
o II E E
D GG SS
E 1-02-0

01 1101 0100 1 11

5-80

L

SS
EE
LL
00
PP

7-0

M

SS
S
BEE R
RR FEES!
YLLEH
NN ANNR
OOOTSSSATT
DD SRRCLEEEETTELPP
1-0 TAB C S Y C S P 1-0 T T 1-0

110 1111 xxxx 00

0 1 1 x x 0 0 0 x xx

1 1 11

Load Rest
of First
Operands

Load Pipeline

Load Half
of First
Begin First
Operands Operation

1

~

~

Load Rest
of Second
Operands

Load Half
of Second Begin Second
Operands Operation

~

~

~~~~II~--~

___

CLK

FIRST INSTRUCTION

SECOND INSTRUCTION

~th1

I

INSTRUCTION:

FUNC(~.OI.

RND(1.01. FAST

HALF

REST
1ST OPS

1ST OPS

14- tsu2

~ 14
th1

~i.
tsu2

th1-.t

HALF

REST
2ND OPS

2ND OPS

tsu2 I..

~I" ~II..

th1

~I"

th1--t>!

tsu2

DATA(31.01 A AND B INPUTS

SELMS/LS

~

---------------------~-------

OUT(31.01 STATUS(13.01

Figure 19. Double-Precision Multiplier Operation, Input Registers Enabled
(PIPES = 110, CLKMODE = 1)

5-81

With both input and output registers pipelined, the third example calculates the product
of I A I and I B I .. Enabling the output register introduces a one-cycle delay in outputting
the result (see Figure 20):
CLKMODE

I I

9-0

=

1

PIPES

= 010

C CC
L a a PP
K NN I I
M FF PP
a II EE
DGGSS
E 1-02-0

Operation: Multiply I A I

SS
EE
LL
PP

RR
NN
DD

7-0

1-0

00

01 1101 1000 1 11 010 1111 xxxx 00

5-82

*

IBI

S
E
L
M
S S
BEE R
S
FEE S I
Y L L EH
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1-0 T T 1-0

a

1 1 x x

aaa

x xx 1 1 11

Load Rest
of Second
Operands

Load Rest
of First
Operands
Load Half
of First
Operands

~

Begin First
Operation

Begin Second
Operation

I

Load Output

Load Pipeline

~

~

~

~

SECOND INSTRUCTION

FIRST INSTRUCTION

~tsu1-----..t

Load Half
of Second
Operands

I.----th1
I

I+- t su1-+1

INSTRUCTION: FUNC(9.01. RND (1.01. FAST
I

I
HALF
1ST OPS

~tsu2~ "" ~4

th1 tsu2 th1
DATA(31.01 A AND.B INPUTS

HALF
2ND OPS

tt

~ tsu2

.'4th1.. "".""
.,
tsu2

th1

SELMS/LS

~~

~(X)
""14--IO+-1 tpd4 """,,-__.+-I tpd5
~

.. O-U-T-(-3-1-.0-I-S-T-A-TU-S-(-1-3-.0-1-------------

Figure 20. Double-Precision Multiplier Operation. Input and Output Registers Enabled
(PIPES .. 010. CLKMODE = 1)

U

«~

I'

:2

CJ)

The fourth example shows the instruction and timing (Figure 21) to generate the
negated product of the .A and B operands. This operating mode with CLKMODE set
high and all registers enabled permits use of the shortest clock period and produces
the most data throughput, assuming that this is the primary operating mode in which
the device is to function.
Additional considerations affecting timing and throughput are discussed in the section
on mixed operations and operands.
CLKMODE

=

1

PIPES = 000

Operation: Multiply - (A

*

B)

S
E
C CC
L 00 P P
K NN I I

M FF PP

o

I I

9-0

II EE
D GG SS
E 1-02-0

L

SS
EE
LL
00
PP

7-0

M

RR
NN
DD
1-0

01 11 00 0100 1 11 000 1111 xxxx 00

5-84

SS
S
BEE R
FEES!
YLLEH
.ANNR
OOOTSSSATT
SRRCLEEEETT ELPP
TAB C S Y C S P 1-0 T T 1-0
0 1 1 x x 0 0 0 x xx

1 1 11

load Rest
of Second
Operands

load Rest
of First
Operands
load Half
of First
Operands

load Pipeline

Begin First
Operation

1

Begin Second
load Half Operation
of Second
Operands load Pipeline

.. .

•
•u-LJL
I

I+-

I
I
I

14--- tsu1---';

td2

V

FIRST INSTRUCTION

I

load Output

Begin Third
Operation

load Half
of Third
Operands

1 • •

load Pipeline

1

I

ClK

load Rest
of Third
Operands

load Pipeline

1

~

·14

td2

td2 --+t

.14

X

SECOND INSTRUCTION

1 4 - tsu1~

THIRD INSTRUCTION

I+----.; I+-- tsu1 ~

1 th1

I4---.t
th1

th1

I

INSTRUCTION: FUNC(9.0). RND(1.0). FAST
HALF
1ST OPS

HALF
2ND OPS

I+--tsu2~

I

114 .14

.1

I I tsu2 th1

--+'

I 4 - t su2

HALF
3RD OPS

.1 I+-- t su2

.1011 •• '4
th1

~I

th1

th1

I4---.t
th1

1 I

~ *-tus2

t.-th1

DATA(31.0) A AND B INPUTS

SElMS/lS

-------------------------~
tpd4
tpd5
tpd4
tpd5
OUT(31.0) STATUS(13.0)
~

C11

Co
C11

~

~

Figure 21. Double-Precision Multiplier Operation. All Registers Enabled
(PIPES .. 000. CLKMODE = 1)

SN74ACT8837

~

Chained Multiplierl ALU Operations
Simultaneous multiplier and ALU functions can be selected in chained mode to support
calculation of sums of products or products of sums. Operations selectable in chained
mode (see Table 25) overlap partially with those selectable in independent multiplier
or ALU operating mode. Format conversions, absolute values, and wrapping or
unwrapping of denormal numbers are not available in chained mode.
To calculate sums of products, the FPU can operate on external data inputs in the
multiplier while the ALU operates on feedback from the previous calculation. The
operand selects SELOPS7-SELOPSO can be set to select multiplier inputs from the
RA and RB registers and ALU inputs from the P and S registers.
This mode of chained multiplier and ALU operation is used repeatedly in the division
and square root calculations presented later. The sample microinstruction sequence
shown in Tables 27 and 28 performs the operations for multiplying sets of data
operands and accumulating the results, the basic operations involved in computing
a sum of products.
Table 27 represents the operations, clock cycles, and register contents for a singleprecision sum of four products. Registers used include the RA and RB input registers
and the product (P) and sum (S) registers.

Table 27. Single-Precision Sum of Products (PIPES2-PIPESO =·010)

en

CLOCK
CYCLE

2

5

MULTIPLIER/ALU
OPERATIONS
Load A. B
A * B
Pass P(AB) to S
Load C. D
C* D
S(AB) + P(CD)
Load E. F
E* F
S(AB + CD) + P(EF)
Load G. H
G* H
S(AB + CD) + EF) + P(GH)

6

New Instruction

1

'-I
~

l>

2

(")

-f

00
00

3

eN
'-I
4

PSEUDOCODE

A -+ RA. B -+ RB

C -+ RA. D -+ RB
A * B -+ P(AB)
P(AB) + 0 .... S(AB)
E -+ RA, F -+ RB
C * D -+ P(CD)
S(AB) + P(CD) -+ S(AB + CD)
G -+ RA. H -+ RB
E * F -+ P(EF)
S(AB + CD) + P(EF)
G * H -+ P(GH)

-+

S(AB + CD + EF)

S(AB + CD + EF) + P(GH)

-+

S(AB + CD + EF + GH)

A microcode sequence to generate this sum of product is shown in Table 28. Only
three instructions in chained mode are required, since the multiplier begins the
calculation independently and the ALU completes it independently.

5-86

Table 28. Sample Microinstructions for Single-Precision Sum of Products

I I

9-0
0001000000
1001100000
1000000000
1000000000
0000000000
xx xxxx xxxx

C CC
L 00 pp
K NN I I
M FF pp
0 II EE
D GG 55
E 1-0 2-0

0
0
0
0
0
x

01
01
01
01
01
xx

010
010
010
010
010
xxx

5
E
L
55
EE
LL
00

RR
NN

pp
7-0

1-0

M
5 5
5
BEE
FEE 5 /
Y L L
ANN R
000T55
5 R R C LEE E E TT
TABC5YC5 P 1-0

00
00
00
00
00
xx

x
x
x
x
ox x x
x x x x

1111
1111
1111
xxxx
xxxx
xxxx

xxxx
xxxx
1010
1010
1010
xxxx

DD

0
0
0
0

x
x
x
x
x
x

x x x
x x x
x x x
x x x
x x x
000

x
x
x
x
x
x

xx
xx
xx
xx
xx
xx

R
E H
5 A TT
E L PP
T T 1-0

11
11
11
11
11
11

Fully Pipelined Double-Precision Operations
Performing fully pipelined double-precision operations requires a detailed understanding
of timing constraints imposed by the multiplier. In particular, sum of products and
product of sums operations can be executed very quickly, mostly in chained mode,
assuming that timing relationships between the ALU and the multiplier are coded
properly.
Pseudocode tables for these sequences are provided, (Table 29 and Table 30) showing
how data and instructions are input in relation to the system clock. The overall patterns
of calculations for an extended sum of products and an extended product of sums
are presented. These examples assume FPU operation in CLKMODE 0, with the CONFIG
setting HL to load operands by MSH and LSH, all registers enabled
(PIPES2 - PIPESO = LLL), and the C register clock tied to the system clock.
In the sum of products timing table, the two initial products are generated in
independent multiplier mode. Several timing relationships should be noted in the table.
The first chained instruction loads and begins to execute following the sixth rising
edge of the clock, after the first product P1 has already been held in the P register
for one clock. For this reason, P1 is loaded into the C register so that P1 will be stable
for two clocks.
On the seventh clock, the ALU pipeline register loads with an unwanted sum, P1 + P1.
However, because the ALU timing is constrained by the multiplier, the S register will
not load until the rising edge of CLK9, when the ALU pipe contains the desired sum,
P1 + P2. The remaining sequence of chained operations then execute inthe desired
manner.

5-87

I""M
~

....

U
:;
I""-

2

en

L£88.L:J'

~

Matrix Operations

0)
0)

The' ACT8837 floating point unit can also be used to perform matrix manipulations
involved in graphics processing or digital signal processing. The FPU multiplies and
adds data elements, executing sequences of microprogrammed calculations to form
new matrices.

W
-..J

Representation of Variables
Instate representations of control systems, an n-th order linear differential equation
with constant coefficients can be represented as a sequence of n first-order linear
differential equations expressed in terms of state variables:
dx1
dt

5-92

'" x 2, ... ,

dx(n -1)
dt

'" xn

For example, in vector-matrix form the equations of an nth-order system can be
represented as follows:

d
dt

x1
x2

a11

a12

a1n

~

b11

b1n

x2

:

xn

an1

an2

ann

~
u2

+

xn

bn1

bnn

un

+ bu

or, X = ax

Expanding the matrix equation for one state variable, dx 1/dt, results in the following
expression:
X1

=

(a11

*

x1 + ... + a1n

*

xnl + (b11

* u1

+ ... + b1n

* unl

where X 1 = dx 1/dt.
Sequences of multiplications and additions are required when such state space
transformations are performed, and the 'ACT8837 has been designed to support such
sum-of-products operations. An n x n matrix A multiplied by an n x n matrix X yields
an n x n matrix C whose elements cij are given by this equation:

,....

n
cij =.E aik

('I)

*

xkj

for i=1, ... ,n

j=1, ... ,n

(11

~
l-

k=1

e.>

For the cij elements to be calculated by the' ACT8837, the corresponding elements
aik and xkj must be stored outside the' ACT8837 and fed to the' ACT8837 in the
proper order required to effect a matrix multiplication such as the state space system
representation just discussed.

Sample Matrix Transformation
The matrix manipulations commonly performed in graphics systems can be regarded
as geometrical transformations of graphic objects. A matrix operation on another matrix
representing a graphic object may result in scaling, rotating, transforming, distorting,
or generating a perspective view of the image. By performing. a matrix operation on
the position vectors which define the vertices of an image surface, the shape and
position of the surface can be manipulated.

5-93

«
~
,....

;2

en

The generalized 4 x 4 matrix for transforming a three-dimensional object with
homogeneous coordinates is shown below:

a
e
T

b
f

c
9
k

..... ...
m n

0

:

d
h
I

p

The matrix T can be partitioned into four component matrices, each of which produces
a specific effect on the resultant image:

3
x

3 x 3

1
1 x 1

1 x 3

The 3 x 3 matrix produces linear transformation in the form of scaling, shearing and
rotation. The 1 x 3 row matrix produces translation, while the 3 x 1 column matrix
produces perspective transformation with multiple vanishing points. The final single
en element 1 x 1 produces overall scaling. Overall operation of the transformation matrix
2 T on the position vectors of a graphic object produces a combination of shearing,
-...J rotation, reflection, translation, perspective, and overall scaling.

t

("')

The rotation of an object about an arbitrary axis in a three-dimensional space can be

-I carried out by first translating the object such that the desired axis of rotation passes

00 through the origin of the coordinate system, then rotating the object about the axis
00

W through the origin, and finally translating the rotated object such that the axis of rotation
-...J resumes its initial position. If the axis of rotation passes through the point P = [a b c 11.
then the transformation matrix is representable in this form:

[x y z hI

= [x y z 11

1

0

0
0

1

0
0

0

1

0
0
0

-a

-b

-c

1

R

~
translation
to origin

5-94

1

0

0
0
a

1

0
0

0

1

0
0
0

b

c

1

~
rotation
about
origin

translation
back to initial
position

(2)

where R may be expressed as:

R

n12 + (1-n)2 costj>

n1n2(1-costj»+n3sintj>

n1n3(1-costj»-n2sin

0

n1n2(1-costj»-n3sintj>

n22 + (1-n2)2costj>

n2n3( 1-costj» + n 1sintj>

0

n1n3(1-costj»+n2sintj>

n2n3(1-costj»-n1sintj>

n3 2 + (1-n3)2 cos

0

o
and

o

o

n1

=

n2

= q2/(q 12

+ q22 + q3 2 ) 1/2

=

n3

= q3/(q1 2

+ q22 + q3 2 ) 1 /2

= direction cosine

h

direction cosine for x-axis of
rotation

vector defining axis of rotation

= the

direction cosine for y-axis of rotation

= unit

= (n1 n2 n3)

0: =
tj>

q1/(q1 2 + q22 + q3 2 )1/2

rotation angle about

vector for

= [q1

for z-axis of rotation

0:

q2 q3)

0:
......

A general rotation using equation (2) is effected by determining the [x y z) coordinates
of a point A to be rotated on the object, the direction cosines of the axis of rotation
[n1, n2, n3]. and the angle tj> of rotation about the axis, a.II of which are needed to
define matrix [R). Suppose, for example, that a tetrahedron ABCD, represented by
the coordinate matrix below is to be rotated about an axis of rotation RX which passes
through a point P = [5 - 6 3 11 and whose direction cosines are given by unit vector
[n1 = 0.866, n2 = 0.5, n3 = 0.707). The angle of rotation 0 is 90 degrees (see
Figure 24). The rotation matrix [R) becomes
2
1
2
2

R =

-3
-2
-1
-2

0.750
-0.274
1.112

0

3
2
2
2

1.140
0.250
-0.513
0

A
B

C
D

0.112
1.220
0.500
0

0
0
0
1

5-95

M
CO
~

U
<{

o::t
......
Z

CJ)

y

Z'

+- - - - - - - - - - - - - - -,

r-I
(211

°T

BT
AT

55·

1(1\
I

Q

I
I
x,+-----------~7.7~~~~~--------~-----------------~)X
I
L _.-.
BR
I

c'

I

Z

IL

(3)
____

-+
B'

t-

0'

90·

P (5, -6,3)

(1) THIS ARROW DEPICTS THE FIRST TRANSLATION
(2) THIS ARROW DEPICTS THE 90· ROTATION
(3) THIS ARROW DEPICTS THE BACK TRANSLATION

en

Figure 24, Sequence of Matrix Operations

~

The point transformation equation (2) can be expanded to include all the vertices of
the tetrahedron as follows:

z
'J

»
(")
-4

CO
CO

W
.....

xa
xb
xc
xd

ya
yb
yc
yd

2 -3
1- 2
2 -1
2 -2

za
zb
zc
zd

3
2 1
2 1
2 1

h1
h2
h3
h4

1 0 00
0.750 1.140 0.112 0 1 000
01 00 -0.274 0.250 1.22 0 0 1 0 0
1.112 -0.5130.5000 0 010
00 1 0
-56-31
0
0
0
1 5-6 3 1

translation
to origin

5-96

rotation about origin

translation
back to
initial
position

(3)

The 'ACT8837 floating-point unit can perform matrix manipulation involving
multiplications and additions such as those represented by equation (1). The matrix
equation (3) can be solved by using the' ACT8837 to compute, as a first step, the
product matrix of the coordinate matrix and the first translation matrix of the righthand side of equation (3) in that order. The second step involves postmultiplying the
rotation matrix by the product matrix. The third step implements the back-translation
by premultiplying the matrix result from the second step by the second translation
matrix of equation (3). Details of the procedure to produce a three-dimensional rotation
about an arbitrary axis are explained in the following steps:
Step 1
Translate the tetrahedron so that the axis of rotation passes through the origin. This
process can be accomplished by multiplying the coordinate matrix by the translation
matrix as follows:

2
1
2
2

-3
-2
-1

-2

3
2
2
2

1

0

0

1
0
6

0

-5

0
0
1

-3

(2-5)
(1 - 5)
(2-5)
(2-5)

0
0
0
1

(-3+6)
(-2+6)
(-1 +6)
(-2+6)

(3-3)
(2-3)
(2-3)
(2-3)

~

l

translation
to origin

vertices of translated
tetrahedron

1
1
1
1

,....
('I')

OJ
OJ
-3
-4
-3
-3

+3
+4
+5
+4

0
-1
-1
-1

....
«
~

(.)

AT
BT
CT
DT

,....

2

(/)

The' ACT8837 could compute the translated coordinates AT, BT, CT, DT as indicated
above. However, an alternative method resulting in a more compact solution is
presented below.

5-97

Step 2
Rotate the tetrahedron about the axis of rotation which passes through the origin after
the translation of Step 1. To implement the rotation of the tetrahedron, postmultiply
the rotation matrix [R) by the translated coordinate matrix from Step 1 . The resultant
matrix represents the rotated coordinates of the tetrahedron about the origin as follows:

-3
-4
-3
-3

3
0 1
0.750
1.140 0.112 0
4 -1 1 -0.274
0.250 1.22 0
1.112 -0.513 0.500 0
5 -1 1
4 -1 1
0
0
1
0

-3.072
-5.208
-4.732
-4.458

-2.670
-3.047
-1.657
-1.907

3.324
3.932
5.264
4.044

1
1
1
1

~
rotation about origin

rotated coordinates

Step 3
Translate the rotated tetrahedron back to the original coordinate space. This is done
by premultiplying the resultant matrix of Step 2 by the translation matrix. The following
calculations produces the final coordinate matrix of the transformed object:

en
Z

....,J
~

~

(")

- 3.072
-5.208
-4.732
-4.458

- 2.670 3.324 1
-3.0473.9321
-1.657 5.264 1
-1.907 4.044 1

1 0
0
1
0 0
5 -6

0
0
1
3

0
0
0
1

1.928
-0.208
0.268
0.542

- 8.670
-9.047
-7.657
-7.907

6.324
6.932
8.264
7.044

-"4
CO
CO

~

~

....,J

translate back

final rotated coordinates

eN

A more compact solution to these transformation matrices is a product matrix that
combines the two translation matrices and the rotation matrix in the order shown in
equation (3). Equation (3) will then take the following form:

xa
xb
xc
xd

ya
yb
yc
yd

za
zb
zc
zd

hl
h2
h3
h4

2
1
2
2

-3
-2
-1
-2

3
2
2
2

0.750
-0.274
1.112
-3.730

1.140
0.250
-0.513
-8.661

0.112
1.220
0.500
8.260

0
0
0
1

~
transformation matrix
The newly transformed coordinates resulting from the postmultiplication of the
transformation matrix by the coordinate matrix of the tetrahedron can be computed
using equation (1) which was cited previously:

I'
('I)

CO
CO

n

cij

= 1:;

aik

* xkj

for i = 1, ... ,n

j = 1, ... ,n

(1)

t;


C'
D'

,J::o

(")

[-5.208 -3.0473.93211
[-4.732 -1.6575.2641)
[-4.458 -1.9074.044 11

-t

IX)
IX)

CN

"

Microinstructions for Sample Matrix Manipulation
The' ACT8837 FPU can compute the coordinates for graphic objects over a broad
dynamic range. Also, the hQmogeneous scalar factQrs h1, h2, h3 and h4 may be made
unity due tQ the availability.of large dynamic range. In the example presented below,
some .of the calculations pertaining to vertex A' are shown but the same apprQach
can be applied tQ any number .of points and any vector space.
The calculations belQw shQW the sequence of operations for generating tWQ
coordinates, xa and ya, .of the vertex A' after rQtation. The same sequence CQuid be
continued to generate the remaining two cOQrdinates for A' (za and h1). The other
vertices of the tetrahedron, 8', C', and D', can be calculated in a similar way.

5-100

A microcode sequence to generate this matrix multiplication is shown in Table 31.
Table 32 presents a pseudocode description of the operations, clock cycles, and register
contents for a single-precision matrix multiplication using the sum-of-products sequence
presented in an earlier section. Registers used include the RA and RB input registers
and the product (P) and sum (S) registers.
Table 31. Microinstructions for Sample Matrix Multiplication

S

E
C CC
L 00 P P
K NN I I

M FF PP

o II EE

00

G G SS
E 1-0 2-0

9-0

SS
EE
LL

o

I I

L

PP

7-0

SS
S
BEE R
R R FEES /
Y L L EH
NN ANNR
OOOTSSSATT
DDS R R C [ EE E E T TEL P P
1-0 TAB C S Y C S P 1-0 T T 1-0

0001000000 0010101111 xxxx 00
1001100000 0010101111 xxxx 00
1a 0000 0000 a a 1 a 1 a 1 1 1 1 1a 1a 00
1a 0000 0000 a a 1 a 1a 1 11 1 10 10 00
1a 0000 0000 a a 1 01 0 1 11 1 1a 1a 00
10
10
10
10
10

0110
0000
0000
0000
0110

0000
0000
0000
0000
0000

a
a
a
a
a

01
01
01
01
01

0101111
0101111
0101111
0101111
0101111

M

xxxx 00
1010 00
1010 00
1010 00

xxxx 00

01
01
a1
a1
a1

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

xx
xx
xx
xx
xx

11
11
11
11
11

a1
a1
a1
a1

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

xx
xx
xx
xx
xx

11
11
11
11

a

1

11

Six cycles are required to complete calculation of xa, the first coordinate, and after
four more cycles the second coordinate ya is output. Each subsequent coordinate can
be calculated in four cycles so the 4-tuple for vertex A' requires a total of 18 cycles
to complete.
Calculations for vertices B~, C', and 0', can be executed in 48 cycles, 16 cycles for
each vertex. Processing time improves when the transformation matrix is reduced,
i.e., when the last column has the form shown below:

5-161

'"
M

co
co
....
(.)

«
~

'"2:

fJ)

Table 32. Single-Precision Matrix Multiplication (PIPES2-PIPESO - 010)
CLOCK
CYCLE
1

Load a13, x31
SP Multiply
Add P to S

4

Load a14, x41
SP Multiply
Add P to S

5

Load a 11, x 1 2
SP Multiply
Add P to S

a11 ..... RA,x12 ..... RB
p5 = a11
x12, p4 ..... P(p4)
P(p3) + S(p1 + p2) ..... S(p1 + p2 + p3)

6

Load a12, x22
SP Multiply
Pass P to S
Output S

a12 ..... RA, x22 ..... RB
p6 = a12
x22, p5 ..... P(p5)
P(p4) + S(p1 + p2 + p3) .....
S(p1 + p2 + p3 + p4)

7

Load (113, x32
SP Multiply
Add P to S
Load a14, x42
SP Multiply
Add P to S

a 13 ..... RA, x32-+ RB
p7 = a13
x32. p6 -+ P(p6)
P(p5) + 0 ..... S(p5)
a14 ..... RA, x42 ..... RB
p8 = a14
x42. p7 - P(p7)
P(p6) + S(p5)- S(p5 + p6)

9

Next operands
Next instruction
Add P to S

A ..... RA, B ..... RB
pi = A
B, p8 ..... P(p8)
P(p7) + S(p5 + p6) - S(p5 + p6 + p7)

10

Next operands
Next instruction
Output

C - RA, D ..... RB
pj = C
D, pi':" P(pi)
P(p8) + S(p5 + p6 + p7) .....
S(p5 + p6 + p7 + p8)

-4

00
00
eN

.....

*
*

3

.....
~

a 11 - RA, x 11 -RB
p1 = a11
x11
a12 -RA, x21 -RB
p2 = 812
x21
p1 - P(p1)

Load a12, x21
SP Multiply
Pass P to S

2

»
(")

PSEUDOCODE

2

8

CJ)

MULTIPLIER/ALU
OPERATIONS
Load a 11, x 11
SP Multiply

S.

a13 - RA, x31 -RB
p3 = a13
x31, p2 -P(p2)
. P(p1) + 0-S(p1)
a14 ..... RA, x41 ..... RB
p4 = a14
x41, p3 ..... P(p3)
P(p2) + S(p1) ..... S(p1 + p2)

*

*
*

*

*

*

*

*

The h-scalars h1, h2. h3, and h4 are equal to 1. The number of clock cycles to generate
each 4-tuple can then be decreased from 16 to 13 cycles. Total number of clock cycles
to calculate all four vertices is reduced from 66 to 54 clocks. Figure 25 summarizes
the overall matrix transformation.

5-10.2

Y

Z'

x'--------------------~~~--------------~----~------------_7X

1°
I
I
I
I

B

C'

I

Z

.-0.

0'

B'

:A'

90°
P (5, -6,3)

I

I
I
I

Y'

Figure 25, Resultant Matrix Transformation

This microprogram can also be written to calculate sums of products with all pipeline
registers enabled so that the FPU can operate in its fastest mode; Because of timing
relationships, the C register is used in some steps to hold the intermediate sum of
products. Latency due to pipelining and chained data manipulation is 11 cycles for
calculation of the first coordinate, and four cycles each for the other three coordinates.
After calculation of the first vertex, 16 cycles are required to calculate the four
coordinates of each subsequent vertex. Table 33 presents the sequence of calculations
for the first two coordinates, xa and ya.

5-103

"
M
00
00
....

U

c:x:
..,.

"z

en

Table 33. Fully Pipe lined Sum of Products (PIPES2-PIPESO = 000)
(Bus or Register Contents Following Each Rising Clock Edge)

CLOCK
CYCLE

I
BUS

DA
BUS

DB
BUS

I
REG

RA
REG

RB
REG

MUL
PIPE

ALU
PIPE

P
REG

S
REG

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Mul
Mul
Chn
Mul
Chn
Chn
Chn
Chn
Chn
Chn
Chn
Chn
Chn
Chn
Chn
Chn

x11
x21
x31
x41
x12
x22
x32
x42
x13
x23
x33
x43
x14
x24
x34
x44

a11
a12
a13
a14
a 11
a12
a13
a14
a11
a12
a13
a14
a 11
a12
a13
a14

Mul
Mul
Chn
Mul
Chn
Chn
Chn
Chn
Chn
Chn
Chn
Chn
Chn
Chn
Chn

x11
x21
x31
x41
x12
x22
x32
x42
x13
x23
x33
x43
x14
x24
x34

a 11
a12
a13
a14
a 11
a12
a13
a14
a 11
a12
a13
a14
a 11
a12
a13

p1
p2
p3
p4
p5
p6
p7
p8
p9
p10
p11
p12
p13
p14

51
t
52
53
54
xa
55
56
57
ya
58
59

p1
p2
p3
p4
p5
p6
p7
p8
p9
p10
p11
p12
p13

51
t
52
53
54
xa
55
56
57
ya
58

C Y
REG BUS

p2
p2
p2
52
p6
p6
p6
55
p10
p10
p10

xa

ya

t Contents of this register are not valid during this cycle.

Products in Table 33 are numbered according to the clock cycle in which the operands
and instruction were loaded into the RA, RB, and I register, and execution of the
instruction began. Sums indicated in Table 33 are listed below:
s1
52
53
s4

5-104

p1
p1
p2
p5

+ 0
+ p3
+ p4

+0

55 = p5 + p7
56
p6 + p8
57
p9 + 0
58
p9 + p11

59
xa
ya

=
=

p10 + p12
p1 + p2 + p3 + p4
p4 + p5 + p6 + p7

SAMPLE MICROPROGRAMS FOR BINARY DIVISION AND
SQUARE ROOT
The SN74ACT8837 Floating Point Unit supports binary division and square root
calculations using the Newton-Raphson algorithm. The' ACT8837 performs these
calculations by executing sequences of floating-point operations according to the
control settings contained in specific microprogrammed routines. This implementation
of the Newton-Raphson algorithm requires that a seed ROM provide values for the
first approximations of the reciprocals of the divisors.
This application note presents several microprograms for floating-point division and
square root using the Newton-Raphson algorithm. Each sample program is analyzed
briefly to show details of the floating-point procedures being performed.

Binary Division Using the Newton-Raphson Algorithm
Binary division can be performed as an iterative procedure using the Newton-Raphson
algorithm. For a dividend A, divisor B, and quotient Q, this procedure calculates a value
for .1 /B which is then used to evaluate the expression Q = A * 1/B. The calculation
can be performed with either single- or double-precision operands, and examples of
each precision are shown.
The basic algorithm calculates the value of a quotient Q by approximating the reciprocal
of the divisor B to adequate precision and thel] multiplying the dividend A by the
approximation of the reciprocal: .
Q

= A/B = A *

Xn, where Xn = the value of X after the nth iteration
n = the number of iterations to achieve the
desired precision

IU

Intermediate values of X are calculated using the following expression:
Xi

+

1 = Xi

*

(2 - B

*

"

('I)
(Xl
(Xl

~

Xi), where XO = approximates 1/B for
the range 0 < XO < 2/B

o::t

"Z

To illustrate a program using the Newton-Raphson algorithm, the sequence oftn
calculations is presented in detail. For double-precision operations, three iterations are

5-105

needed to· achieve adequate precision in the value of 1/B. A value for the seed XO
(approximately equal to 1/B) is assumed to be given, and the following operations are
performed to evaluate Q from double-precision inputs:

* XO)
X2 == X1 (2 - B * X1) == XO(2 - B * XO) * (2 - B * XO(2 - B * XO))
X3 == X2(2 - B * X2)
X3 == XO(2-B * XO) * (2-B * XO(2-B * XO)) * (2-B * XO * (2-B
* XO) * (2-B * XO * (2-B * XO)))
Q == A * 1/B == A * X3
AlB = A * XO(2-B * XO) * (2-B * XO(2-B * XO)) * (2-B * XO
* (2-B * XO) * (2-B * XO * (2-B * XO)))
X1 == XO(2 - B

X1

X1

X1

X2

X1

X2
X3

~

Table 36 presents decimal and hexadecimal values for A, B, and XO, which are used
in the sample calculation. The computed value of the quotient Q is also included,
showing the representations of the results of this sample division.

~

Table 34. Sample Data Values and Representations

(J)

~

l>
CX)
CX)

W

...,J

TERM
A
B

XO
Q

VALUE

DECIMAL REPRESENTATION
MANTISSA • 2 EXPONENT

22
7
117
22/7

1.375
2 4
1.75
2 2
1.140625
2 (-3)
1.5714285714285713

*
*

*

*2

IEEE HEXADECIMAL
REPRESENTATION

1

40360000
401 COOOO
3FC24000
40092492

00000000
00000000
00000000
49249249

In Table 35, the sequence and timing of this procedure is shown exactly as performed
by the' ACT8837. This example shows the steps in a double-precision division requiring
three iterations to achieve the desired accuracy. In this table each operation is
sequenced according to the clock cycles during which the instruction inputs for that
operation are presented at the pins of the 'ACT8837. Operations are accompanied
by a pseudocode summary of the operations performed by the' ACT8837 and the clock
cycle when an operand is available or a result is valid.
Each line of pseudocode indicates the operands being used, the operations being
performed, the registers involved, and the clock cycles when the results appear. Each
5-106

register is represented by its usual abbreviation (RA, RB, P, S, or C) followed by the
number of the clock cycle when an operand will be valid or available at the register;
For example, "P.4" refers to the contents of the Product Register after the fourth
clock cycle.
Table 35. Binary Division Using the Newton-Raphson Algorithm
CLOCK
CYCLES
1, 2
3, 4

PSEUDOCODE

OPERATIONS
B * XO

5, 6

2 - B * XO
Xl = XO(2 - B * XO)

7, 8

B * Xl

B -+ RA.2. XO -+ RB.2
RA.2 * RB.2 -+ P.4
2 - P.4-+ 5.6
RB.2 * 5.6 -+ P.8
RA.2 * P.8 ..... P.l0
P.8 ..... C.9, 2 - P.l0 ..... 5.12

9. 10

2 - B * Xl

11. 12

X2=Xl(2-B*Xl)

C.9 * 5.12 P.14

13, 14
15. 16

B * X2
2 - B * X2
X3 = X2(2 - B * X2)

RA.2 * P.14 ..... P.16
P.14-+ C.15, 2 - P.16 ..... 5.18

17, 18
19,20
21, 22

A * X3
Output M5H

A ..... RA.18, C.15 * 5.18 ..... P.20
RA.18 * P.20 ..... P.22
P.22.M5H ..... Y

The sequence of operations can be microcoded for executio'n exactly as listed in the
table above. Sample microprograms (with data and parity fields provided) are given
below. To make the programs easier to follow, comment lines have been included to
indicate clock timing, calculation performed by the instructions being loaded, and
operations being represented, in the same pseudocode as in the preceding table. The
fields in the microinstruction sequences presented below are arranged in the following
order:

~
CX)

CO
....

t)

<{

N
S
L
T
I
C R
N C L U
ELK C
# K C T

S
E
L
CC
LC
M
KOP S
BSR
T
S
YEE'HE
MNI E
FEE S I
OFPLRANNR
OOOTLS.AS
DIE 0 N S R R C [ E E E ES E L T
EGSPDTABCSYCSPTTTP

~
.....

z

en
0
0
0
DB
A
B P P
A3
3
1-----01-----0 A B

d h h hhh h h h hh h h h h h h h h h h h h h h hhhhhhhh hhhhhhhh h h
All fields in the sample microcode sequences (except for line numbers) are represented
as hexadecimal numbers. Line numbers are the only decimal numbers in thesamples.

5-107

Single-Precision Newton-Raphson Binary Division
Use of the Newton-Raphson algorithm is similar for both single- and double-precision
operands. However, for implementations which handle both single- and doubleprecision division, it may be preferable to use a double-precision seed ROM, converting
the double-precision seeds to single precision when necessary.
The following sample program involves conversion of a double-precision seed XO for
use in single-precision division. Since 8 is given as a single-precision number, it must
be converted to double precision in order to address a double-precision seed ROM.
Then the seed XO, which is double precision, must be converted to single precision
for the actual calculation.
Two iterations are used in the single-precision example. Thus, the formula
Q = A
1/8 may be rewritten with n = 2:

*

Q == A

*

1/8 = A

*

where X2 = X1
A

*

118 = A

*

XO

X2

*
*

(2 - 8

(2 - 8

*
*

X1) and X1 = XO

XO)

*

[2 - 8

*

XO

*

(2 - 8

*

(2 - 8

*

XO)

*

XO)]

Table 36 presents a single-precision division using a double-precision seed ROM. This
example divides 2217.

5-' 08

Table 36. Single-Precision Newton-Raphson Binary Division

;Lines 1-2

01 0 0 026 1
02 1 0 026 1

;Lines 3-4

Calculation: B s.p. -+ d.p.
Operations: B - RA.1, (s.p. to d.p.)(RA.1)- S.2
3 FF 0 0 1 0 1 1 0 0 0 0 3 1
3 FF 0 0 1 0 1 1 0 0 0 0 3 1

3 40EOOOOO 00000000 0 0
3 40EOOOOO 00000000 0 0

Calculation: load XO
Operations: XO - RA.4

03 0 0 126 1 0 2 FF 0 0 1 0 1 1 0 0 0 0 3 1
04 1 0 126 1 0 2 FF 0 0 1 0 1 1 a a 0 0 3 1

3 3FC24000 00000000 0 0
3 3FC24000 00000000 0 0

;lines 5-6
Calculation: XO d.p. - s.p.
Operations: (d.p. to s.p.)(RA.4) - S.6
05 0 0 126 1 a 2 FF a 0 1 a 1 1 0
06 1 0 126 1 0 2 FF 0 a l' 0 1 1 0

;Lines 7-B

07 0 1 040 1
OB 1 a 040 1

;Lines 9-10

1
1

*

3 3FC24000 00000000 0 0
3 3FC24000 00000000 0 0

Calculation: load B, B
XO
Operations: S.6 -+ C. 7, B - RA.B RA.B

a2
a2

DF 0
DF 0

a 1aa1aaaa3
a 1aa1aa0 0 3

"

M

* C.7 -

00
00

P.l a

I-

1 1 3 40EOOOOO 00000000 0 0
1 1 3 40EOOOOO 00000000 0 a

*

a0
a0

aa3
aa0 a3

0 1
0 1

0 0

1
1

3 00000000 00000000 0 0
3 00000000 00000000 0 0

*

Calculation: Xl = XO(2-B
XO)
Operation:
C.7
S.12 - P.14

11 a a 040 0 0 2 9F
1 2 1 0 040 0 0 2 9F

*

aa0
aa0

0 1 1 0 a a
0 1 1 a0 0

a3
a3

~
~

"2

en

Calculation: 2 - (B
XO)
Operations: 2 - P.l0 -+ S.12

09 0 0 202 0 0 2 FB a
10 1 a 202 0 a 2 FB 0

;Lines 11-12

aaa3
aaa3

1
1

3 00000000 00000000 0
3 00000000 00000000 0

a
a

Table 36. Single-Precision Newton-Raphson Binary Division (Concluded)

;Lines 13-14

*

Calculation: B
X1
Operation:
RA.8
P.14

*

~

P.l6

13 0 0 040 0 0 2 EF 0 0 0 0 1 1 0 0 0 0 3 1 1 3 00000000 00000000 0 0
14 1 0 040 0 0 2 EF 0 000 1 1 0 0 0 0 3 1 1 3 00000000 00000000 0 0

;Lines 15-16

Calculation: 2 - (B * Xl)
Operations: P.14~C.15, 2 - P.16-S.18

1 5 0 0 202 0 0 2 FB 0 0 0 0 1 1 0 0 0 0 3. 1
16 1 0 202 0 0 2 FB 0 0 0 0 1 1 0 0 0 0 3 1

;Lines 17-18

* Xl)
* S.18 .... P.20

Calculation: X2 = Xl (2 - B
Operations: A .... RA.18, C.15

1 7 0 0 040 0 0 2 9F 0 0 1 0 1 1 0 0 0 0 3 1
18 1 0 040 0 0 2 9F 0 0 1 0 1 1 0 0 0 0 3 1

Ch

;Lines 19-20

Z
.....,

3 00000000 00000000 0 0
3 00000000 00000000 0 0

*

3 41 BOOOOO 00000000 0 0
3 41 BOOOOO 00000000 0 0

Calculation: A
X2
Operations: RA.18
P.20 .... P.22

*

~

»

(')
~

19 0 0 040 0 0 2 EF 0 0 0 0 1 1 0 0 0 0 3 1 1 3 00000000 00000000 0 0
20 1 0 040 0 0 2 EF 0·0 0 0 1 1 0 0 0 0 3 1 1 3 00000000 00000000 0 0

00
00
W
.....,

;Lines 21-22

Operation:

P.22'" Y

21 0 0 020 0 0 2 EF 0 0 0 0 1 1 0 0 0 0 3 1 1 3 00000000 00000000 0 0
22 1 0 020 0 0 2 EF 0 0 0 0 1 1 0 0 0 0 3 1 1 3 00000000 00000000 0 0

5-110

Double-Precision Newton-Raphson Binary Division
If the value of B is given as a double-precision number and XO is looked up in a doubleprecision seed ROM, no conversions are required prior to performing a double-precision
division using the Newton-Raphson algorithm. Three iterations are used in the doubleprecision example (n = 3). The following formula represents the sequence of
calculations to be performed:

* XO * (2 - B * XO) * [2 - B * XO * (2 - B * XO))
* (2 - B * XO .(2 - B * XO) * [2 - B * XO .(2 - B * XO)))

AlB = A

Table 37 shows a double-precision division using a double-precision seed ROM. The
example divides 2217.
Table 37. Double-Precision Newton-Raphson Binary Division

*

;lines 1-4

01
02
03
04

0
1
0
1

0
0
0
0

1CO
1CO
1 CO
1CO

Calculation: B
XO
Operations: B -+ RA.4, XO
0
0
0
0

0
0
0
0

2
2
2
2

FF
FF
FF
FF

0
0
0
0

0
0
0
0

0
0
1
1

0
0
1
1

1
1
1
1

1
1
1
1

0
0
0
0

0
0
0
0

0
0
0
0

-+

0
0
0
0

3
3
3
3

RB.4, RA.4
1
1
1
1

* RBA

1 3 3FC24000
1 3 3FC24000
1 3 401 COOOO
13 401COOOO

-+

P.8

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0
I'
M

05
06
07
08

0
1
0
1

0
0
0
0

382
382
382
382

Calculation: 2 - (B
Operation:
2 - P.8
0
0
0
0

0
0
0
0

0
1
0
1

0
0
0
0

1CO
1CO
1CO
1CO

2
2
2
2

FB
FB
FB
FB

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

1
1
1
1

1
1
1
1

0
0
0
0

XO)
-+ S.12
0
0
0
0

0
0
0
0

0
0
0
0

3
3
3
3

~

(,)

1
1
1
1

00000000
00000000
00000000
00000000

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

1
000031
3 00000000
1 1 0 0 0 0 3 1 1 3 00000000
1 1 0 0 003 1 1 3 00000000
1 1 0 0 003 1 1 3 00000000

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

3
3
3
3

Calculation: Xl = XO(2-B * XO)
Operation:
RB.4
S.12 -+ P.16

;Lines 9-12

09
10
11
12

CC
CC

*

;Lines 5-8

*

0
0
0
0

0
0
0
0

2
2
2
2

BF
BF
I3F
BF

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

5·111

«
;:!
Z
U)

Table 37. Double-Precision Newton-Raphson Binary Division (Continued)

*

;Lines 13-16

13
14
15
16

0.0
1 0
0 0
1 0

1CO
1CO
1 CO
1 CO

Calculation: B
Xl
Operations: RA.4
P.16
0 0
O. 0
0 0
0 0

0
1
0
1

0
1
0
0

382
382
382
382

Z
-...I

t

21
22
23
24

0
1
0
1

0
0
0
0

1CO
1 CO
1CO
1CO

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

1
1
1
1

P.20

1000031
3 00000000
1 0 0 0 0 3 1 1 3 00000000
1 0 0 0 0 3 1 1 3 00000000
1 0 0 0 0 31 1 3 00000000

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

00000000
00000000
00000000
00000000

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

3 00000000
1 000 0 3 1
1000031 1 3 00000000
1000031 1 3 00000000
1 00 0 0 3 1 1 3 00000000

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

Calculation: 2 - (B
Xl)
Operations: P.16 -+ C.18, 2 - P.20
0
0
0
0

0
0
0
0

2
2
2
2

FB
FB
FB
FB

0
0
0
0

0
0
0
0

0 0
0 0
0 0
00

1
1
1
1

1
1
1
1

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

3
3
3
3

1
1
1
1

3
3
3
3

-+

S.24

*

;Lines 21-24

(J)

EF
EF
EF
EF

-+

*

;Lines 17-20

17
18
19
20

2
2
2
2

*

Calculation: X2 = X 1 (2-B
Xl)
Operations: C.18 * S.24 -+ P.28
0
0
0
0

0
0
0
0

2
2
2
2

9F 0
9F 0
9F 0
9FO

0
0
0
0

0
0
0
0

0
0
0
0

1
1
1
1

(")

-4

(X)
(X)

*

;Lines 25-28

Calculation: B
X2
Operations: RA.4
P.28

W

-...I

25
26
27
28

0
1
0
1

0
0
0
0

lCO
lCO
1CO
1CO

0
0
0
0

0
0
0
0

0
1
0
1

5-112

0
1
0
0

382
382
382
382

EF
EF
EF
EF

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

1
1
1
1

1
1
1
1

0
0
0
0

0
0
0
0

0
0
0
0

-+

0
0
0
0

P.32
3
3
3
3

3 00000000
1
1 1 3 00000000
1 1 3 00000000
1 1 3 00000000

*

;Lines 29-32

29
30
31
32

2
2
2
2

*

Calculation: 2 - (B
X2)
Operations: P.28 -+ C.30, 2 - P.32
0
0
0
0

0
0
0
0

2
2
2
2

FB
FB
FB
FB

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

1
1
1
1

1
1
1
1

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

3
3
3
3

1
1
1
1

3
3
3
3

-+

S.36

00000000
00000000
00000000
00000000

Table 37. Double-Precision Newton-Raphson Binary Division (Concluded)

*

;Lines 33-36

33
34
35
36

0
1
0
1

0
0
0
0

1 CO
1 CO
1CO
1CO

Calculation: X3 = X2(2-B
X2)
S.36
Operations: A -+ RA.36, C.30
0
0
0
0

3
3
3
3

0
1
0
1

0
0
0
0

1CO
1CO
1 CO
1CO

0
1
0
1

0
0
0
0

120
120
120
120

0
0
0
0

0
0
0
0

1
1
1
1

1000031
1000031
1000031
1000031

Calculation: A
X3
Operations: RA.36
0
0
0
0

0
0
0
0

;Lines 41-44

41
42
43
44

9F
9F
9F
9F

*

;Lines 37-40

37
38
39
40

2
2
2
2

2
2
2
2

EFO
EF 0
EF 0
EF 0

0
0
0
0

0
0
0
0

Operation:

0
0
0
0

0
0
0
0

2
2
2
2

FF
FF
FF
FF

0
0
0
0

0
0
0
0

0
0
0
0

*

0
0
0
0

1
1
1
1

0
0
0
0

P.40
0
0
0
0

0
0
0
0

0
0
0
0

P.44.MSH

-+

Y

0
0
0
0

1
1
1
1

*

-+

3
3
3
3

-+

P.40

3
3
3
3

40360000
40360000
00000000
00000000

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

3
3
3
3

00000000
00000000
00000000
00000000

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

3
3
3
3

00000000
00000000
00000000
00000000

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

P.44
1
1
1
1

1 1 00 0 0 3 1
1
000031
1
00003 1
1
o 000 3 1

1
1
1
1

,......
M

00
00

I-

U

<1:
o::t
,......

;Line 45

Operation:

P.44.LSH

-+

2

Y

CJ)

45 0 0 120 0 0 2 FF 0 0 0 0 1 0 0 0 0 0 3 1 1 3 00000000 00000000 0 0

5-113

Binary Square Root Using the' Newton-Raphson Algorithm
Square roots may be calculated iteratively using the Newton-Raphson algorithm. The
procedure is similar to Newton-Raphson division and involves evaluating the following
expression:
A

=

B

*

Xn

where Xn
Xi

+

=

the value of X after the nth iteration given

1 = 0.5 * Xi * [3 - B * (Xi ZZ 2))

XO = a guess at 1/sqrt(B) where 0
and n

=

< XO < sqrt(3/B)

number of iterations to achieve the desired precision

Single-Precision Square Root Using a Double-Precision Seed ROM
When the value of B is given in single precision, it must be converted to a double~
precision number before it can be used to address a double-precision seed ROM. Since
the seed XO is stored as a double-precision number, it must first be converted to single
precision before it is used in the calculation.
Two iterations (n = 2) are used in a single-precision calculation so the following
expression for sqrt(B) is to be evaluated:

A = 'B

A

5-114

=

*

X2

where X2

=

0.5 * X1 * [3 - B * (X1 2))

and X1

=

0.5 * XO * [3 - B* (XO 2))

B * 0.5 * 0.5 * XO * [3 - B * (XO 2))
* [3 - B * (0.5 * XO * [3 - 8 * (XO 2))) 2)

Table 38. Single-Precision Binary Square Root

;Lines 1-2

01 0 0 026 1
02 1 0 026 1

;Lines 3-4

Calculation: B s.p. -+ d.p.
Operations: B -+ RA.l, (s.p. to d.p.)(RA.l)
3 FF 0 0 1 0 1 1 0 0 0 0 3 1
3 FF 0 0 1 0 1 1 0 0 0 0 3 1

Calculation: Load XO
Operation:
XO -+ RA.4

Calculation: XO d.p. -+ s.p.
Operations: (d.p. to s.p.)(RA.4)

3 3FE6AOOO 00000000 0 0
3 3FE6AOOO 00000000 0 0

-+

S.6

05 0 0 126 1 0 2 FF 0 0 1 0 1 1 0 0 0 0 3 1
06 1 0 126 1 0 2 FF 0 0 1 0 1 1 0 0 0 0 3 1

;Lines 7-8

S.2

3 40000000 00000000 0 0
3 40000000 00000000 0 0

03 0 0 126 1 0 2 FF 0 0 1 0 1 1 0 0 0 0 3 1
04 1 0 126 1 0 2 FF 0 0 1 0 1 1 0 0 0 0 3 1

;Lines 5-6

-+

3 3FE6AOOO 00000000 0 0
3 3FE6AOOO 00000000 0 0

*

Calculation: Load B, B
XO
Operations: S.6 -+ C. 7, B -+ RB.8, RB.8

07 0 1 040 1 0 2 7F 0 0 0 1 0 1 0 0 0 0 3 1
08 1 0 040 1 0 2 7F 0 0 0 1 0 1 0 0 0 0 3 1

,.....

*

C.7

-+

P.l 0

3 40000000 00000000 0 0
3 40000000 00000000 0 0

M
00
00
....
U



(")

*

Calculation: B
Xl 2
Operations: Po18 - Co19, P020
Co19 - P022,
3 -+ RA020 -+ S022

*

-I

ex>
ex> 19 0 1 260 0 0 2 6F 0 0 1 0 1 1 0 0 0 0 3 1 1 3 40400000 00000000 0 0

eN

20 1 0 260 0 0 2 6F 0 0 1 0 1 1 0 0 0 0 3 1 1 3 40400000 00000000 0 0

""'"
; Lines 21-22

*

Calculation: 3 - (B
Xl 2)
Operations: S022 - P022 -+ S024

21 0 0 003 0 0 2 FA 0 0 0 0 1 1 0 0 0 0 3 1 1 3 00000000 00000000 0 0
22 1 0 003 0 0 2 FA 0 0 0 0 1 1 0 0 0 0 3 1 1 3 00000000 00000000 0 0

;Lines 23-24

*

*

Calculation: Xl
(3 - (B
Xl 2))
Operations: Co19 * S024 -+ P026, 112 - RA024

23 0 0 260 0 0 2 9F 0 0 1 0 1 1 0 0 0 0 3 1
24 1 0 260 0 0 2 9F 0 0 1 0 1 1 0 0 0 0 3 1
5-116

-+

S026

3 3FOOOOOO 00000000 0 0
3 3FOOOOOO 00000000 0 0

Table 38. Single-Precision Binary Square Root (Concluded)

;Lines 25-26

*

25 0 0 240 0 0 2 AF 0 0 1 0 1
26 1 0 240 0 0 2 AF 0 0 1 0 1

;Lines 27-28

*

*

*

0 00 0 3 1
0 0 0 0 3 1

Calculation: B
X2 -+ A
P.28
Operations: S.28

27 0 0 040 0 0 2 AF 0 000 1
28 1 0 040 0 0 2 AF 0 0 0 0 1

;Lines 29-30

*

Calculation: 1/2
X1
(3 - (B
X1 2)) - X2
Operations: S.26
P.26- P.28, 0 - RA.26,
RA.26 + RB.8 S.28

*

-+

3 00000000 00000000 0 0
3 00000000 00000000 0 0

P.30

0000 3 1
0 0 0 0 3 1

3 00000000 00000000 0 0
3 00000000 00000000 0 0

Calculation: NOP
Operation:
Y - Output

29 0 1 OOA 00 2 FF 0 0 0 0 1 1 00 0 0 3 1 1 3 00000000 00000000 0 0
30 1 0 OOA 0 0 2 FF 0 0 0 0 1 1 0 0 0 0 3 11 3 00000000 00000000 0 0

,.....
M

Double-Precision Square Root

ex)
ex)

The value of B is given as a double-precision number so XO can be looked up from
a double-precision seed ROM without conversion fromone precision to the other. Three
iterations (n = 3) are required in the double-precision calculation, and the following
formula for sqrt(B) is to be evaluated:

.....
(.)

A

=

B

*
*
*

*

0.5
[3 - B
[3 - B
[3 - B

* 0.5 * 0.5 * XO * [3 - B * (XO
* (0.5 * XO * [3 - B * (XO 2)]) 21
* (0.5 * 0.5 * XO * [3 - B * (XO 2)J
* (0.5 * XO * [3 - B * (XO 2)]) 2]) 2J

~

...r

,.....

Z

CJ)

2)J

5-117

Table 39. Double-Precision Binary Square Root

*

;Lines 1-4

01
02
03
04

0
1
0
1

0
0
0
0

3EO
3EO
3EO
3EO

XO
Calculations: Load B, Load XO, B
Operations: B -+ RB.4, XO -+ RA.4, RA.4
RA.4 -+ S.8 -+ C.1 0
0
0
0
0

0
0
0
0

0
1
0
1

0
0
0
0

3EO
3EO
3EO
3EO

FF
FF
FF
FF

0
0
0
0

0
0
0
0

0
0
1
1

0
0
1
1

1
1
1
1

1
1
1
1

*

;Lines 5-8

05
06
07
08

2
2
2
2

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

3
3
3
3

0
0
0
0

2
2
2
2

AF
AF
AF
AF

0
0
0
0

0
0
0
0

0
0
1
1

0
0
0
0

1
1
1
1

*

1
1
1
1

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

3
3
3
3

RB.4

3 40000000
1
1 1 3 40000000
1 1 3 3FE6AOOO
1 1 3 3FE6AOOO

Calculations: B
XO 2
Operations: P.8
S.8 -+ P.12, 3
0
0
0
0

*

-+

RA.8

-+

-+

P.8

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

S.12

1
3 00000000
1 1 3 00000000
1 1 3 40080000
1 1 3 40080000

Calculations: 3 - (B * XO 2)
Operations: S.12 - P.12 -+ S.16

;Lines 9-12
(f)

2

~

l>
(")

09
10
11
12

0
1
0
1

0
1
0
0

183 0 0 2
183002
183 0 0 2
183 0 0 2

FA
FA
FA
FA

0 0 0 0 0 1
000001
0 0 0 0 1 1
0 0 0 0 1 1

0 0 0 0
0000
0 0 0 0
0 0 0 0

3
3
3
3

1
3 00000000
1 1 3 00000000
1 1 3 00000000
1 1 3 00000000

-f

(X)
(X)

W
-..J

*

;Lines 13-16

13
14
15
16

0
1
0
1

5-118

0
0
0
0

3EO
3EO
3EO
3EO

*

Calculations: XO
(3 - (B
XO 2))
S.16 -+ P.20, 1/2
Operations: C.l0
0
0
0
0

0
0
0
0

2
2
2
2

9F
9F
9F
9F

0
0
0
0

0
0
0
0

0
0
1
1

0
0
0
0

1
,
1
1

*

-+

RA.16

-+

S.20

1 0 0 0 0 3 1 1 3 00000000 00000000 0 0

1 0 0 0 0 3 1 1 3 00000000 00000000 0 0
1 0 0 0 0 3 1 1 3 3FEOOOOO 00000000 0 0
1 0 0 0 0 3 1 1 3 3FEOOOOO 000000000 0

Table 39. Double-Precision Binary Square Root (Continued)

;Lines 17-20

17
18
19
20

0
1
0
1

0
0
0
0

3CO
3CO
3CO
3CO

Calculations: 1/2* XO * (3-(B * XO 2))"'" Xl
Operations: S.20 * P.20 ..... P.24 ..... C.25, 0"'" RA.20,
RA.20 + RBA"'" S.24
0
0
0
0

0
0
0
0

; Lines 21-24

21
22
23
24

0
1
0
1

0
0
0
0

1CO
1CO
1CO
1CO

0
1
0
.1

1
0
0
0

3EO
3EO
3EO
3EO

0
0
0
0

0 2
02
0 2
0 2

0 0
1 0
00
1 0

0
0
0
0

0
0
0
0

0
0
1
.1

0 1
01
0 1
0 1

1
1
1
1

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

3
3
3
3

1
1
1
1

1
1
1
1

3
3
3
3

00000000
00000000
00000000
00000000

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

AF
AF
AF
AF

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

1
1
1
1

1
1
1
1

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

3
3
3
3

1
1
1
1

13
1 3
1 3
1 3

00000000
00000000
00000000
00000000

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

Calculations: B * Xl 2
Operations: P.28 * C.25 ..... P.32, 3 --- RA.28 --- S.32
0
0
0
0

0
0
0
0

;Lines 29-32

29
30
31
32

AF
AF
AF
AF

Calculations: B * Xl
Operations: S.24 * P.24 ..... P.28

;Lines 25-28

25
26
27
28

2
2
2
2

183 0 0
183 0 0
18300
183 0 0

2
2
2
2

6F 0
6FO
6F 0
6F 0

0 0
0 0
01
0 1

0
0
0
0

1
1
1
1

1 000 0 3 1
3
1000031 1 3
1000031 1 3
1 0 0 0 0 3 1 1 3

00000000
00000000
40080000
40080000

00000000
00000000
00000000
00000000

FA
FA
FA
FA

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
1
1

1
1
1
1

0 0 0 0 3
0 0 0 0 3
00003
0 0 0 0 3

1
1
1
1

1
1
1
1

«
q-

"z
en

Calculations: 3 - (B * Xl 2)
Operations: S.32 - P.32 ..... S.36
2
2
2
2

"

M
00
00
I(.)

3 00000000 00000000 0 0
3 00000000 00000000 0 0
3000000000000000000
3 00000000 00000000 0 0

5-119

Table 39. Double-Precision Binary Square Root (Continued)

*

;Lines 33-36

33
34
35
36

0
1
0
1

0
0
0
0

3EO
3EO
3EO
3EO

0
0
0
0

0
0
0
0

0
1
0
1

0
0
0
0

3CO
3CO
3CO
3CO

2
2
2
2

9F
9F
9F
9F

0
0
0
0

0
0
0
0

0
0
1
1

0
0
0
0

1
1
1
1

1
1
1
1

*

0
0
0
0

0
0
0
0

*
*

;Lines 37-40

37
38
39
40

*

Calculations: X1
(3 - (B
X1 2))
8.36 - P.40, 1/2 - RA.36 8.40
Operations: C.25
0
0
0
0

0
0
0
0

3
3
3
3

1
1
1
1

1
1
1
1

*

3
3
3
3

00000000
00000000
3FEOOOOO
3FEOOOOO

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

*

Calculations: 1/2
X1
(3 - (B
X 1 2)) - X2
P.40 - P.44 - C.45, 0 - RA.40,
Operations: 8.40
RA.40 + RB.4 8.44
0
0
0
0

0
0
0
0

2
2
2
2

AF
AF
AF
AF

0
0
0
0

0
0
0
0

0
0
1
1

0
0
0
0

1
1
1
1

1
1
1
1

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

3
3
3
3

1 1 3 00000000 00000000
1 1 3 00000000 00000000
1 1 3 00000000 00000000
1
3 00000000 00000000

Calculations: B * X2
Operations: 8.44
P.44- P.48

;Lines 41-44

*

(f)

Z
-..J 41 0 0 1CO 0 0 2 AF 0 0 0 0 1 1 0 0 0 0 3 1 1 3 00000000 00000000 0 0

:t

42 1 0 1CO 0 0 2 AF 0 0 0 0 1 1000031 1 3 00000000 00000000 0 0
(") 43 0 0 1CO 0 0 2 AF 0 0 0 0 1 1000031 1 3 00000000 00000000 0 0
.... 44 1 0 1CO 0 0 2 AF 0 0 0 0 1 1000031 1 3 00000000 00000000 0 0
CX)
CX)

eN
-..J

*

;Lines 45-48

45
46
47
48

0
1
0
1

5-120

1
0
0
0

3EO
3EO
3EO
3EO

Calculations: B
X2 2
Operations: P.48
C.45 - P.52, 3- RA.48 - 8.52
0
0
0
0

0
0
0
0

2
2
2
2

6F
6F
6F
6F

0
0
0
0

0
0
0
0

0
0
1
1

0 1
0 1
0 1
01

1
1
1
1

*
0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

3
3
3
3

1
1
1
1

1
1
1
1

3
3
3
3

00000000
00000000
40080000
40080000

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

Table 39. Double-Precision Binary Square Root (Continued)

*

;Lines 49-52

49
50
51
52

00
1 0
0 0
1 0

183
183
183
183

Calculations: 3 - (B
X2 2)
Operations: S.52 - P.52 ... S.56
0
0
0
0

0
0
0
0

0
1
0
1

0
0
0
0

3EO
3EO
3EO
3EO

0
1
0
1

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
1
1

1
1
1
1

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

3
3
3
3

1
1
1
1

1
1
1
1

3
3
3
3

00000000
00000000
00000000
00000000

2
2
2
2

9F
9F
9F
9F

0 0
0 0
0 0
00

0
0
1
1

0
0
0
0

1
1
1
1

1
1
1
1

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

*

0
0
0
0

*

*

3CO 0
3CO 0
3COO
3CO 0

1CO
1CO
1CO
.1 CO

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

3
3
3
3

1
1
1
1

1
1
1
1

*

3
3
3
3

-+

RA.56

00000000
00000000
3FEOOOOO
3FEOOOOO

-+

S.60

000000000 0
000000000 0
00000000 0 0
00000000 00

*

Calculations: 1/2
X2
(3 - (B
X2 II'" X3
Operations: S.60
P.60
P.64, 0 -+ RA.60,
RA.60 + RB.4 -+ S.64
0
0
0
0

2
2
2
2

AF
AF
AF
AF

0
0
0
0

0
0
0
0

0
0
1
1

0
0
0
0

1
1
1
1

0
0
0
0

2
2
2
2

AF
AF
AF
AF

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

1
1
1
1

1
1
1
1

3
3
3
3

00000000 00000000 0 0
00000000 00000000 0 0
000000000000000000
00000000 00000000 0 0

,....
M
~
....
U
c:(

o:::t
,....
2

Calculations: B
X3 -+ A
P.64
Operations: S.64
0
0
0
0

-0.

1000031
1000031
1000031
1 000 0 3 1

*

;Lines 61-64

61 0
621
63 0
64 1

0
0
0
0

Calculations: X2
(3 - (B
X2 211
Operations: C.45 * S.56 -+ P.60, 1/2

;Lines 57-60

57
58
59
60

FA
FA
FA
FA

*

;Lines 53-56

53
54
55
56

2
2
2
2

*

1
1
1
1

en
-+

0 0 0 0
0000
0 0 0 0
0 0 0 0

P.68

3
3
3
3

1
1
1
1

1
1
1
1

-+

3
3
3
3

Y.MSH
00000000 00000000 0 0
000000000000000000
00000000 00000000 0 0
00000000 00000000 0 0

Table 39. Double-Precision Binary Square Root (Concluded)

;Lines 65-68

65
66
67
68

0
1
0
1

1
0
0
0

;Line 69

18A
18A
18A
18A

Calculation:
Operation:
0
0
0
0

0
0
0
0

2
2
2
2

FF
FF
FF
FF

0
0
0
0

0
0
0
0

0
0
0
0

Calculation:
Operation:

NOP
Y.MSH
0
0
0
0

1
1
1
1

1
1
1
1

-+

0
0
0
0

NOP
Y.LSH

0
0
0
0

-+

Output
0
0
0
0

0
0
0
0

3
3
3
3

1
3
1
3
1 1 3
1 1 3

00000000
00000000
00000000
00000000

00000000
00000000
00000000
00000000

0
0
0
0

0
0
0
0

Output

69 0 0 18A 00 2 FF 0 0 0 0 1 00000 31 1 300000000 00000000 0 0

5-122

GLOSSARY
Biased exponent - The true exponent of a floating point number plus a constant called
the exponent field's excess. In IEEE data format, the excess or bias is 127 for singleprecision numbers and 1023 for double-precision numbers.
Denormalized number (denorm) - A number with an exponent equal to zero and a
nonzero fraction field, with the implicit leading (leftmost) bit of the fraction field being O.
NaN (not a number) - Data that has no mathematical value. The' ACT8837 I' ACT884 7
00 is executed. The output
produces a NaN whenever an invalid operation such as 0
format for an NaN is an exponent field of all ones, a fraction field of all ones, and a
zero sign bit. Any number with an exponent of all ones and a nonzero fraction is treated
as a NaN on input.

*

Normalized number - A number in which the exponent field is between 1 and 254
(single precision) or 1 and 2046 (double precision). The implicit leading bit is 1.
Wrapped number - A number created by normalizing a denormalized number's fraction
field and subtracting from the exponent the number of shift positions required to do
so. The exponent is encoded as a two's complement negative number.

I'
('I)

00
00

....

(,)



the example microprograms assume that a negative B simply means that the negative

(") of the square root of B is the desired answer instead of the positive root. This is

-I
CO accomplished by using the absolute value of B in all computations except for looking
CO up the seed. If the seed is negative, then the answer generated will be the negative root.
eN

......

PROM Contents
Because one address line of the PROMs selects divide or square root, the PROMs can
be considered to be divided functionally into two halves: the divide half and the square
root half. Each functional half is discussed separately in the sections below.

Divide PROMs
The exponent part of the seed is defined in the following manner. Assuming that
B = m
(2 e ) and XO = m'
(2 e \ e' is computed as e' = - e. Using the definition
of an IEEE number, the value of m can be represented as a number within the following
interval: 1 s m < 2.

*

5-124

*

DATA BUS
63-0

32 ..

,

C
L
K

ACT8837 FLOATING
POINT PROCESSOR

32

,

Y OUTPUT

63-32
63

,

..

SIGN 81T
LOGIC

D
V
I

5
o
R

I

32

0
U
T
P
U
T
E
N
A
B
L
E

OE

63
11

OE

A10-AO

62-52
4

4K X 4
REGISTERED PROM

03-00

A11

6i59

11 ,

OE I'

A10-AO

62-'52
4
03-00

4K X 4
REGISTERED PROM
Al1

58.55

11

62~52
4

"

('I')

OE

A10-AO

00
00
I-

4K X 4
REGISTERED PROM
03-00

U

A11

or::(

5:52

c::t

11

52~42

4K X 4
REGISTERED PROM

4,
. 51~48

11

I

52~42
4

47~44

"en2:

OE

A10-AO

03-00

A11

OE

A10-AO
4K X 4
REGISTERED PROM
03-AO

1..0

A11 f'"

Figure 26. IEEE Double-Precision Seed ROM for
Newton-Raphson Division and Square Root

5-125

This range of values of m can be subdivided into two cases:
m = 1, or 1 < m < 2
Since m' is computed as m' = 1 I m, the range of m' will be

m' = 1, or 1/2 < m' < 1
To be represented as a normalized IEEE number, m" would be

m"

= m'

*

(21)

=

21m

(1 )

This would make the range of m"
m" = 2, or 1 < m" < 2
This is still not quite in the range of a valid IEEE number; however, m" = 2 only when
m = 1. Therefore, m" can be forced to be just less than 2 in this case.

*

Since XO = m'
(2 e '), to use m" in the PROMs, we must have an e" in the exponent
(2 e"). This is true for e" = e' - 1. Since, XO = m"
(2 e''),
such that XO = m"
the following substitution can be made:

XO

= (m'
= m'
= m'
= m'
= m'

*
*
*
*
*

*

(2 1 ))
(21)
(2e')
(2 e ')
(2e')

*

* (2(e'-1))
* (2e') * (2(-1))
* (2(1-1))
* (2 0 )

~ Therefore, if e" is used in the exponent PROMs and m" is used in the mantissa PROMs,
'" a normalized IEEE seed can be generated. The only exception to the formula is that
~ for m = 1,

»

(")

m"

-t

=

2 I m - delta

~
Where delta = 2(-8)
W
'" So m"
= 2 I m, and e"

= (- e)

- 1.

Since IEEE exponents are represented in excess 1023 notation, a formula for X" must
be determined, given that X is the IEEE exponent. As an IEEE exponent,
X = e + 1023 - e = X - 1023 and X" = e" + 1023. So, forX" in terms of X,
X" = e" + 1023
= (-e) - 1 + 1023
= (- (X - 1023)) + 1022
= 1023 - X + 1022
= 2045 - X
So given the 11 bits of X as address of the seed exponent, the value stored at address
X is
X" = 2045 - X
5-126

(2)

Given that the mantissa seed ROM uses 10 bits of the mantissa to determine the seed,
delta).
each seed Xm will be used for some range of mantissas, Bm to (Bm + 2
The formula for Xm is from formula (1).

*

2/Bm
2/(Bm + 2
Where delta

*

-Xm
-Xm

delta)

=

2( -11)

This value is used since the actual Xm should be generated by the mantissa in the
center of the given range:
Xm = 2/(Bm + delta)
This would result in a more accurate seed on the average. Therefore, the formula used
to generate the mantissa part of the seed is
Xm = 2/(Bm + (2( - 11 I))

(3)

Square Root PROMs
The seed for the square root, XO, is actually the reciprocal of the square root of the
data, B:
XO = 1 I (B(1/2))

*

Given B = m
(2 e ) and XO = m'
by substitution and reduction:

*

*

(2 e '), the expression for XO can be evaluated

XO = 1 I ((m
(2 e ))(1!2))
= 1 I (m(1 12) (2(e/2)))
= m( - 1/2)
(2( - e/2))

*

*

Then m' and e' may be written as m' = m( - 1/2) and e' = - e/2.
Next, it is necessary to verify that the above m' and e' form a valid normalized IEEE
number. When e is an odd number, e' is not an integer and, therefore, it is not valid
IEEE exponent. If the above expression is separated into two cases, e' can be
represented in terms of a valid IEEE exponent, e":
e' = -e/2

e'

= e"

for e even
for e odd

+ 112

Rewriting e" in terms of e produces this expression:

e"

=

e' - 112

= (-e/2) -

1/2

for e odd

Then a valid IEEE exponent, e", can be written for all e as

e"
e"

= -e/2
= (-e/2) -

1/2

for e even
for e odd

5-127

This is equivalent to e"
XO
XO
XO

= m' *
= m' *
=

m'

Since. XO = m"

m"

=

m'

m"

=

m'

*

e/2) for all e. However, the 112 affects the mantissa:

(2e')
(2(e" + 112))
(21/2)
(2 e ")

*

*

= intI -

for odd e
for odd e

*

(2e") m" can be rewritten as
for even e
for odd e

(21/2)

In terms of m, m" = m -112
m" = (m- 1/2 )

*

(2112)

for even e
for odd e

Simplifying m" for odd e,
m"
m"

(1/m1/2)

= (21m 112)

* (21/2)

for odd e
for odd e

Just as the divide exponent needed to be converted to excess 1023 notation, so the
same must be done for the square root:
X" = e" + 1023
X = e + 1023
X" = intI - e/2) + 1023
X" = int((1023-X) I 2) + 1023

en

The IEEE bits for the exponent seed, X", can be expressed in terms of the IEEE bits

:2 for the exponent of B, X:

'"t

X" = intI (1023-X) 12) + 1023

~ Because the formula for m" depends on the least significant bit of e, that bit must
CO be used as an address line to the mantissa.
CO
W Since X = e + 1023, an odd value of e will result in an even value of X, and an even
'" value of e will result in an odd value of X. Therefore,
m" = m -1/2
m" = 2/m1/2

5-128

for odd X
for even X

SN74ACT8841

Digital Crossbar Switch

6-1

6-2

SN74ACT8841
.Digital Crossbar Switch
The SN74ACT8841 is a single-chip digital crossbar switch that cost-effectively
eliminates bottleneck~ to speed data through complex bus architectures.
The' ACT8841 has 16 four-bit bidirectional ports which can be connected in
any conceivable combination. Total time for data transfer is 14-ns flowthrough.
The' ACT8841 is ideal for multiprocessor application, where memory bottlenecks
tend to occur. For example, four 32-bit buses can be easily connected by two
'ACT8841 devices. System architectures based on the 16-port 'ACT8841 can
include up to 16 switching nodes (Le., processors, memories, or bus interfaces).
Larger processor arrays can be built with multistage interconnect schemes.

~

~

00
00

tU

«
~

"Z

CIl

6-3

6-4

SN74ACT8841
DIGITAL CROSSBAR SWITCH
JUNE 1988

•

High-Speed Programmable Switch for
Parallel Processing Applications

•

Dynamically Reconfigurable for FaultTolerant Routing

•

64 Bidirectional Data 1I0s in 16 Nibble
(Four-Bit) Groups

•

Data 110 Selection Programmable by Nibble

•

Eight Banks of Control Flip-Flops for Storing
Configuration Programs

•

Two Selectable Hard-Wired Switching
Configurations

•

Selectable Stored-Data or Real-Time Inputs

~
w

GB PACKAGE
(TOPVIEWI
2

A
B

o

3

4

5

6

7

8

9

10 11

12 13 14 15

•••••••••••••••

........• • • . . .• .• .•
•••••••••••••••

•••

• • •
• • •
• •••
• •••

:~~~:D · ·. .. ..
• • •

l

•

• ••
• • •

•

156-Pin Grid-Array Package

M

•••

•

CMOS 1 pm EPIC~ Process

N

•••••••••••••••

•

Single 5-V Power Supply

p

•••••••••••••••

A

•••••••••

• •

•

description
The SN74ACT8841 is a flexible. high-speed digital crossbar switch. It is easily microprogram mabie to
support user-definable interconnection patterns. This crossbar switch is especially suited to multiprocessor
interconnects that are dynamically reconfigurable or even reprogram mabie after each system clock. The
•ACT8841 is built in Texas Instruments advanced 1 JLm EPIC~ CMOS process to enhance performance
and reduce power consumption. The switch requires only a 5-V power supply.
Because the' ACT8841 is a 16-port device. system architectures based on the' ACT8841 can include
up to 16 switching nodes. which may be processors, data memories, or bus interfaces. Larger processor
arrays can be built with multistage interconnection schemes. Most applications will use the crossbar switch
as a broadband bus interface controller, for example, between closely coupled processors which must
exchange data with very low propagation delays.
The' ACT8841 has ten selectable control sources, including eight banks of programmable control flip-flops
and two hard-wired control circuits. The device can switch from 1 to 16 nibbles (4 to 64 bits) of data
in a single cycle.
The 64 110 pins of the' ACT8841 are arranged in 16 switch able nibbles (see Figure 1). A single input nibble
can be broadcast to any combination of 1 5 output nibbles, or even to 16 nibbles (including itself) if operating
off registered data. Multiple input nibbles can be switched to multiple outputs, depending on the programmed
configurations available in the control flip-flops.
The digital crossbar switch is intended primarily for multiprocessor interconnection and parallel processing
applications. The device can be used to select and transfer data from multiple sources to multiple
destinations. Since it can be dynamically reprogrammed, it is suitable for use in reconfigurable networks
for fault-tolerant routing.

EPIC is a trademark of Texas Instruments Incorporated
Copyright @ 1988, Texas Instruments Incorporated

PRODUCT PREVIEW documents contain information
on products in the formative or design phase of

development. Characteristic data and other

specifications are design goals. Texas Instruments
reserves the right to change or discontinue these
products without notics.

TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

6-5

:>w
a:

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(,)

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SN74ACTB841
DIGITAL CROSSBAR SWITCH
"tJ

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description (continued)

o

The' ACT8841 and the bipolar SN74AS8840 share the same architecture, Microcode for the' AS8840
can be run on the' ACT8841 if the additional control inputs to the' ACT8841 are properly terminated,
However, because the' ACT8841 is a CMOS device with six additional control inputs, the' AS8840 and
the' ACT8841 are not socket-compatible and cannot be used interchangably, A summary of the differences
between the SN74AS8840 and the SN74ACT8841 is provided in the 'AS8840 and 'ACT8841
FUNCTIONAL COMPARISON at the end of the data sheet,

C

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The SN74ACT8841 is characterized for opertion from O°C to 70°C,

::D

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~

Table 1. 'ACT8841 Pin Grid Allocation
PIN
NO,

PIN
NAME

NO.

PIN

PIN
NO.

NAME

Al

GNO

Cl0

031

A2

GNO

Cll

l5E56

A3

037

C12

A4

035

C13

VCC
GNO

NAME

NO,

NAME

N7

CNTR13

H13

VCC
LSCLK

N8

CREAOO

H14

SELOLS

N9

VCC

H15

CNTR3

Nl0

DO
03

H12

A5

033

C14

023

Jl

OEC

Nll

A6

WE

C15

021

J2

CRWRITEO

N12

06

A7

CRAORl

01

043

J3

CRWRITEl

N13

GNO

A8

CNTR7

02

042

J4

GNO

N14

08

A9

CNTR4

03

J12

GNO

N15

09

Al0

l5'EEi7

07

VCC
GNO

J13

CNTR2

Pl

GNO

All

029

08

CNTRl

P2

GNO

027

09

VCC
GNO

J14

A12

J15

CNTRO

P3

056

A13
A14

025
GNO

013
014

022
020

Kl

CRWRITE2

P4

K2

OE012

P5

058
060

A15

GNO

015

019

K3

048

P6

062

61

GNO

El

045

K13

015

P7

CNTR12
CNTR15

62

GNO

E2

044

K14

014

P8

63

039

E3

C5E'OfO

K15

0ED3

P9

TPO

64

E13

5ED5

L1

049

Pl0

0Ei50

65

036
034

E14

018

66

l5E56

E15

017

L2
L3

02
04

67

CRAORO

Fl

OEOll

68

CRSRCE

F2

046

69

CNTR5

F3

610

030

F13

611
612

028

F14

026

613

050

Pll
P12

L13

OED13
OE02

P13

07

L14

012

P14

GNO

047

L 15

013

P15

GNO

016

Ml

051

Rl

GNO

M2
M3

052

R2

GNO

F15

OE04
CRSEL3

054

R3

057

024

Gl

CNTR6

M7

GNO

R4

059

614

GNO

G2

CNTR9

M8

R5

061

615

GNO

G3

CNTR10

Ml0

VCC
GNO

R6

OE015

Cl

041

G4

GNO

M13

CNTR14

040

G12

GNO

M14

VCC
010

R7

C2

R8

CREAOl

C3
C4

GNO

G13

CRSEL2

M15

011

CREA02

038

G14

CRSEL1

Nl

053

R9
Rl0

C5

0Ei'i9

G15

CRSELO

N2

055

Rll

01

C6

032

Hl

CNTRll

N3

GNO

R12

OEOl

C7

H2

SELOMS

N4

VCC

C8

VCC
CRCLK

H3

MSCLK

N5

0B514

R13
R14

GNO

C9

CNTR6

H4

VCC

N6

063

R15

GND

~

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~

DALLAS TEXAS 75265

TPl

05

SN74ACT8841
DIGITAL CROSSBAR SWITCH

~

Table 2. 'ACT8841 Pin Functional Description
PIN
NAME

NO.

I/O

W

DESCRIPTION

>
w

CNTRO

J15

CNTRl

J14

CNTR2

J13

Q.

CNTR3

H15

IU

CNTR4

A9

CNTR5

89

CNTR6

C9

CNTR7

A8

CNTR8

Gl

CNTR9

G2

CNTR10

G3

CNTRll

Hl

CNTR12

P7

CNTR13

N7

CNTR14

R7

CNTR15

P8

CRADRO

87

CRADRl

A7

CRClK

C8

CAEADO·

N8

CREAD1

A8

CAEAD2

A9

CASElO

G15

CASEll

G14

CRSEl2

G13

CASEl3

F15

CASRCE

88

a:

::::>

I/O

Control 1/0. Inputs four control words to the control flip-flops on each CRCLK cycle. As outputs, the
same

add~esses

can be used to read the flip-flop settings.

o
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D..

I
I
I

Control register address. Selects 16·bits of control flip-flops as a source/destination for outputs/inputs

on CNTRO·CNTR15. (see Table 71
Control register clock. Clocks CNTRO-CNTR15 into the control flip-flops on low-ta-high transition.
Selects one of eight banks of control flip-flops to read out on CNTRO-CNTR 15 in 16-bit words

addressed by CAADA l-CAADAO.

I

Selects one of ten control configurations.

I

Load source select. When low selects CNTR inputs, when high selects DATA inputs.

TEXAS " ,
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6-7

SN74ACT8841
DIGITAL CROSSBAR SWITCH
"0

Table 2. 'ACT8841 Pin Functional Description (continued}

::::a

o

PIN

C
C

CRWRITEO

J2

(")

CRWRITEl

J3

-4

CRWRITE2

Kl

DO

Nl0

"0

::::a
m

S
m

:E

NAME

NO.

01

Rll

02

Pll

03

Nll

04

P12

05

R13

06
07

N12
P13

08

N14

09

N15

010

M14

011

M15

012
013

L14
L15

014

K14

015

K13

016

F13

017

E15

018

E14

019

015

020

014

021

C15

022

013

023

C14

024

813

025

A13

026
027

812

028

811

029

All

1/0

I

DESCRIPTION

Destination select. Selects one of eight control banks. (see Table 4)

1/0

1/0 data bits 0 through 31 (data bits 0 through 31 are the least signIficant half).

110

I/O data bits 32 through 35 (data bits 32 through 63 are the most significant half).

A12

030

810

031

Cl0

032

C6

033

A5

034

85

035

A4

TEXAS •
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6-8

SN74ACT8841
DIGITAL CROSSBAR SWITCH

~

Table 2. 'ACT8841 Pin Functional Description {continuedl
PIN
NAME

NO.

036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
051
052
053
054
055
056
057
058
059
060
061
062
063
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO

84
A3
C4
83
C2
Cl
02
01
E2
El
F2
F3
K3
L1
L2
Ml
M2
Nl
M3
N2
P3
R3

w

1/0

5>
w

DESCRIPTION

a::

a..

t::>
O

C

o

a::

a..
I/O

liD data bits 36 through 63 (data bits 32 through 63 are the most significant half)'

P4
R4

P5
A5
P6
N6
Al
A2
A14
A15
81
62
614
615
C3
C13
07
09
G4
G12

Ground (all pins mus~ b,e usedl.

TEXAS ."

INSTRUMENTS
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6-9

SN74ACTB841
DIGITAL CROSSBAR SWITCH
"'CJ

Table 2 ..• ACT8841 Pin Functional Description (continued I

::D

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PIN
NAME

GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GND
GNO
GNO
GND
GND
LSCLCK
MSCLK
OEC
OEOD
OEOl
OE02
OE03
OE04
0E05
OE06
0E07
OEDS
OE09
OE01D
OEDll
OE012
0ED13
OED14
OED15

NO.
J4
J12 .
M7
M1D
N3
N13
Pl
P2
P14
P15
Rl
R2
R14
R15
H13
H3
Jl
P1D
R12
L13
K15
F14
E13
ell
A1D
86
C5
E3
Fl
K2
L3
N5
RS

1/0

-

OESCRIPTION

Ground (all pins must be used).

I

Clocks the least significant half of data inputs into the input registers on a low-ta-high transition.

I

Clocks the most significant half of data inputs into the input registers on a low-ta-high transition.

I

Output enable for control flip-flops. active low

I

Output enables tor data nibbles, active low

TEXAS ."
INSTRUMENTS
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6-10

SN74ACT8841
DIGITAL CROSSBAR SWITCH

~

Table 2. 'ACT8841 Pin Functional Description (concluded)

PIN
NAME

NO.
H14

I

SELOMS

H2

I

TPO
TPl
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee

P9
R10
e7
e12
03
08
H4
H12
M8
M13
N4
N9
A6

wt

OESCRIPTION

1/0

SELOLS

I

W

When tow, selects the stored, least significant data input to the main internal bus. When high, real-

>
w
IX

time data is selected.
When low, selects the stored. most significant data input to the main internal bus. When high, real-

Q.

time data is selected.

I()

Test pins. High during normal operation. (see Table 9}

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Q.

5-V supply

I

Write enable for control flip-flops. active low

overview
The 64 I/O pins of the' ACT8841 are arranged in 16 nibble (four-bit) groups where each set of four pins
serves as bidirectional inputs to and outputs from a nibble multiplexer. During a switching operation, each
nibble passes four bits of either stored or real-time data to the main internal 64-bit data bus. Each output
multiplexer will independently select one of the 16 nibbles from this 64-bit data bus.
Data nibbles are organized into two groups: the least significant half (D31-DO) and the most significant
half (063-032). Stored versus real-time data inputs (:an be selected separately for the LSH and the MSH.
Two clock inputs, LSCLK and MSCLK, are available to latch LSH and MSH data inputs, respectively, into
the data register.
The pattern of output nibbles resulting from the switching operation is determined by a selectable control
source, either one of eight banks of programmable control flip-flops or one of two hard-wired switching
configurations. Inputs to the control flip-flops can be loaded either from the data bus or from controll/Os.
A separate clock (CRCLK) is provided for loading the banks of control flip-flops .

. TEXAS.
INSTRUMENTS
POST OFFICE 80)( 6~5012

e

DALLAS, TEXAS 75265

6.-"

SN74ACTB841
DIGITAL CROSSBAR SWITCH
."

::J:J

logic symbol

0

DIGITAL CROSSBAR SWITCH

C

*

c:

ACT8841

WRITE EN

WE
CREADO

(")

-t

CREAD1

REG 8ANK\

CREAD2

."
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SELECT

CRClK

DESTINATION

m

<
m
:E

CRWRITEO

I

CRWRITE1
_CRWRITE2

SOURCE

DEC

SELECT
READ

CNTR3-CNTRO

CONTROL

CNTR7-CNTR4

\l

I

CNTR1 1 -CNTR8

lOAD
TEST
ClK

i

MSHI

lSH

SElDlS

CRSRCE
CRSElO

CRSEl2
CRSEl3
CRADRO

ADDRESsi

CNTR1 5-CNTR1 2
LSCLK

I

CONTROL
REGISTER

---+--

I

-+-CRADR1
TPO
TP1

ClK
SELDMS

I
MUX

0

03 DO

D35-D32

MUX
oEi59

OED1

D39D36

07-04
MUX

MUX

OED2
10

D1108

D43-o40

MUX
OED11

OE03

11

047-044

015-012
lSH

MSH

MUX

rJ)

MUX
OE012

OE04

Z

019-016

'"»
~

12

4

MUX

DATA

051-048
MUX
OED13

13

(")

-t
ex>
ex>

055-052
MUX

~

14

027-024

~

MUX

MUX

OE07

15

o31-o2B

FIGURE 1

"'IJ

TEXAS
INSTRUMENTS
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6-12

OEo15
063-060

SN74ACT8841
DIGITAL CROSSBAR SWITCH
architecture
The' ACT8841 digital crossbar switch has its 64 data II0s arranged in 16 multiplexer logic blocks, as shown
in Figure 2. Each nibble multiplexer logic block handles four bits of real-time input and four bits of storeddata input, and either input can be passed to the common data bus.
Two input multiplexer controls are provided to select between stored and real-time inputs. SELOLS controls
input data selection for the LSH (031-00) of the 64-bit data input, ~nd SELOMS for the MSH (063-D32) .
The input register clocks, LSCLK and MSCLK, are grouped in the same way and are used to clock data
into the registers in the multiplexer logic blocks. The 1 6 data input nibbles make up the 64 data bits on
the internal main bus.
This common bus supplies 16 data nibbles to a 16-to-1 output multiplexer in each multiplexer logic block
(see Figure 3). As determined by one of ten selectable control sources, the 16-to-1 output multiplexer
selects a data nibble to send to the outputs via the three-state output driver.
Control of the input and output multiplexers determines the input-to-output pattern for the entire crossbar
switch. Many different switching combinations can be set up by programming the control flip-flop
configurations to determine the outputs from the 16-to-1 multiplexers.

~
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For example, the switch can be programmed to broadcast one data input nibble through the other 15 nibbles
(60 outputs). Conversely, a 15-to-1 nibble multiplexer can be configured by programming the switch to
select and output a single data nibble from the 64-bit bus. Several examples are described in more detail
in a later section.

~

'¢

00
00

I()

«
'¢
,....
2:

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TEXAS •
INSTRUMENTS
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6-13

S1\I74ACT8841
DIGITAL CROSSBAR SWITCH
"'0

::a

functional block diagram

0

SELDLS

SELDMS

LSCLK

M$CLK

-I

03·00

035-032

"'0

m.

C
C

(")

::a

m.

m

<
iii
=e

039-036

07-04

m,

m.
043·040

011·08

i5H'ii10

(jljj,

047·044

015-012

m,

OED 11

051·048

019-016

m.

OED12

055·052

023020

m.

OEl113

059·056

027024

0E014

DED6

063·060

031028

en
2
.....

0ED1S

OED7

~

»
(")
-I

em:

00
00
~
.....

FIGURE 2

INSTRUMENTS
TEXAS ' "
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265

6·14

, - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _

~

_ _ _ _ _ _ _ _ _ _ _ _ _....-SElOLS OR SELDMS

~

~~~

r---t--------------------~------+.-~

:~A~

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(jillli!

~(

~

...

~

.,
)

~~
~ ".r;yI

OXX-DXX

CABEL3·
CRSELO
CAEA02·

CREADO

CONTROL
NIBBLE

OUTPUT

~C
.. ~
~~
~('I'l

...

~.~

.

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•

•

ClIeLK

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LOGIC
CRSRCf

NiBBlE FROM
D-ATA 8US

CONTROL FlIP·FlOP
N.a8lE INPUT

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FIGURE 3. DATA NIBBLE MULTIPLEXER LOGIC

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SN74ACT8841

PRODUCT PREVIEW

SN74ACT8841
DIGITAL CROSSBAR SWITCH
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, multiplexer logic group
There are 16 multiplexer logic blocks, one for each nibble, External data flows from ·four data 1/0 pins
into a logic block, A block diagram of the multiplexer logic is shown in Figure 3, The data inputs are either
clocked into the data register or passed directly to the main internal bus. The 64 bits of data from the
main bus are presented to a 16-to-l multiplexer, which selects the data nibble output.
Each of the 16 nibble multiplexer logic blocks contains eight control flip-flop (CF) groups, one for each
of the control banks. A control bank stores one complete switching configuration. Each CF group consists
of four O-type edge-triggered flip-flops. In Figure 3, the CF groups are shown as CFXXO to CFXX7, where
XX indicates the number of the nibble multiplexer logic group (0 < = XX < '" 15). CFXXO represents the
16 CF groups (one from each logic block) which make up flip-flop control bankO, CFXXl the 16 CF groups
in bank 1, etc.
In addition to the eight banks of programmable flip-flops, two hard-wired switching configurations can
be selected. The MSH/LSH exchange directs the input nibbles from each half of the switch to the data
outputs directly opposite. This switching pattern is shown in Table 3 below. For example, data input on
011-08 is output on 043-040, and data input on 043-040 is output on 011-08.
Table 3. MSH/LSH Exchange
LSH

MSH

03-00

035-032

07-04

039-036

011-08

043-040

015-012

047-044

019-016

051-048

023-020

055-052

027-024

059-056

031-028

063-060

The second hard-wired configuration, a read-back function, causes all 64 bit to be output on the same
I/Os on which they were input. Neither of the hard-wired control configurations affects the contents of
the control banks,
The control source select, CRSEL3-CRSELO, determines which switching pattern is selected, as shown
in Table 4,
Table 4, 16-to-l Output Multiplexer Control Source Selects
CONTROL SOURCE SELECTEO

CRSEL3

CRSEL2

CRSELl

CRSELO

L

L

L

L

Control bank 0

(programmable)

L

L

L

H

Control bank 1

(programmable)

L

L

H

L

Control bank 2

(programmable)

L

L

H

H

Control bank 3

(programmable)

L

H

L

L

Control bank 4

(programmable)

L

H

L

H

Control bank 5

(programmable)

L

H

H

L

Control bank 6

(programmable)

L

H

H

H

Control bank 7

(programmable)

H

X

X

L

MSHfLSH exchange *

H

X

X

H

Read-back (output echoes inpuU *

*Hard-wired switching configuration
X = don't care

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SN74ACT8S41
DIGITAL CROSSBAR SWITCH
control words
A CF group can store a four-bit control word (CFN3-CFNO) to select the output of the 16-to-1 multiplexer
for that nibble port. One control word is loaded in each CF group. A total of 16 words, one per multiplexer
logic block, are loaded in a bank to configure one complete switching pattern. Table 5 lists the control
words and the input data each selects.
Each control word can be stored in a CF group and sent as an internal control signal to select the output
of a 16-to-1 multiplexer in a nibble logic block. For example, any CF group loaded with the word "LHHH"
will select the data input on 031-028 as the outputs of the associated nibble. If all 16 CF groups in a
bank were loaded with "LHHH," the same output (031-028) would be selected by the entire switch.

INTERNAL SIGNALS

INPUT DATA SelECTED AS

CFN2

CFNl

CFNO

l

l

l

l
H

l

l

l

l

l

H

l

l

l

H

H

l

H

L

L

L

H

L

H

L

H

H

L

L

H

H

H

H

L

I,

L

H

L

L

H

H

L

H

L

H

L

H

H

H

H

L

L

H

H

L

H

H

H

H

L

H

H

H

H

03-00
07-04
011-08
015·012
019D16
023-D20
027-024
D31·028
035-032
039-036
043-040
047-044
051-048
055-052
059-056
063-060

loading control configurations
CRWRITE2-CRWRITEO select which control bank is being loaded, as shown in Table 6.
Table 6. Control Flip-Flops Load Destination Select
CRWRITEl

CRWRITEO

DESTINATION

L

l

l

Control bank 0

l

l

H

l

H

l

Control bank 1
Control bank 2

l

H

H

Control bank 3

H

l

l

Control bank 4

H

L

H

Control bank 5

H

H

L

Control bank 6

H

H

H

Control bank 7

a:

c..

I-

o::;:)
c
c..

MULTIPLEXER OUTPUT

CRWRITE2

:>w

oa:

Table 5. 16-to-1 Output Multiplexer Control Words
CFN3

3:
w

~

TEXAS
INSTRUMENlS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265

6-17

SN74ACT8841
DIGITAL CROSSBAR SWITCH
"'tJ

The control words for a bank can be loaded either 16 bits at a time on the control 110 pins (CNTR 1 5-CNTRO)
or all 64 bits at once on the data inputs (063-00). If the control load source select, CRSRCE, is high, the
words are loaded from the data inputs. When CRSRCE = L, the CNTR inputs are used.

:D

o
C
C

("')

-t
"'tJ

:D

m

:5
m

:E

When a control bank is loaded from the data inputs, WE, CRSRCE, CRWRITE2-CRWRITEO, and the control
register clock CRCLK are used in combination to load all 16 control words (64 bits) in a single cycle. A
MSH/LSH exchange like that shown in Table 3 is used to load the flip flops on a rising CRCLK clock edge.
For example, data inputs 03-00 go to the data bus and then to the CF group that selects the data outputs
for 035-032. CRWRITE2-CRWRITEO select the control bank that is loaded (see Table 6).
The CNTRI5-CNTRO inputs can also be used to load the control banks. The bank is selected by
CRWRITE2-CRWRITEO (see Table 6), Four control words per CRCLK cycle can be input to the CF groups
(CFXX) that make up the bank. The CF groups loaded are selected by CRAORI-CRAORO, as shown in
Table 7. Four CRCLK cycles are needed to load an entire control bank.
Table 7. Loading Control Flip-Flops from CNTR liDs
CF GROUPS LOADED BY
CRAD1

CRADO

WE

CRCLK

L

L

L

L

H

L

H

L

L

H

H

L

S
S
S
J-

X

X

H

X

CONTROL (CNTR) 110 NUMBERS
15-12

11-8

7-4

3-0

CF12

CF8

CF4

CFO

CF13

CF9

CF5

CFl

CF14

CFlO

CF6

CF2

CFll

CF7

CF3

CF15

Inhibit write to flip-flops

To read out the control settings, the same address signals can be used, except that no CRCLK signal is
needed and OEC is pulled low. CREA02-CREAOO select the bank to be read; the format is the same as
for CRWRITE2-CRWRITEO, shown in Table 6.
Using the control II0s to read the control bank settings can be valuable during debugging or diagnostics.
Control settings are volatile and will be lost if the' ACT8841 is powered off. An external program controlling
switch operation may need to read the control bank settings so that it can save and restore the current
switching configurations.

test pins

C/)

2

.......

TP1-TPO test pins are provided for system testing. As Table 8 shows, these pins should be maintained
high during normal operation. To force all outputs and II0s low, low signals are placed on TP1-TPO and
all output enables (OEDI5-0EOO and OEC). To force all outputs and II0s high, TPI and all output enables
are pulled low, and TPO is driven high. When TPO is left low and a high signal is placed on TP1, all outputs
on the' ACT8841 are placed in a high-impedance state, isolating the chip from the rest of the system.

~

l>

Table 8. Test Pin Inputs

("')

-t

0)
0)
~
~

TP1

TPO

L

L

OED15OEDO
L

DEC

RESULT

L

All outputs and 1I0s forced low
All outputs and II0s forced high

L

H

L

L

H

L

X

X

All outputs placed in a high-impedance state

H

H

X

X

Normal operation (default state)

TEXAS

~

INSTRUMENTS
POST OFFICE BOX 655012. DALLAS TEXAS 75265

6-18

SN74ACT8841
DIGITAL CROSSBAR SWITCH

~

examples
Most' ACT8841 switch configurations are straightforward to program, involving few control signals and
procedures to set up the control words in the banks of flip-flops. Control signals and procedures forloading
and using control words are shown in the following examples.

broadcasting a nibble

w

:>
w
a:
0..

Any of the 16 data input nibbles can be broadcast to the other 15 data nibbles for output. For ease of
presentation, input nibble 063-060 is used in this example. Example 1 presents the microcode sequence
for loading flip-flop bank 0 and executing the nibble broadcast.
The low signal on CRSRCE selects CNTR15-CNTRO as the input source, and the low signals on
CRWRITE2-CRWRITEO select flip-flop bank 0 as the destination. Table 5 shows that to select data on
063-060 as the output nibble, the four bits in the control word CFN3-CFNO must be high: therefore the
CNTR15-CNTRO inputs are coded high. The four microcode instructions shown in Example 1 load the same
control word from CNTR15-CNTRO into all 16 CF groups of bank O.
Once the control flip-flops have been loaded, the switch can be used to broadcast nibble 063-060 as
programmed. The microcode instruction to execute the broadcast is shown as the last instruction in
Example 1. WE is held high and the data to be broadcast is input on 063-060. The high signal on SELDMS
selects a real-time data input for the broadcast. MSCLK and LSCLK (not shown) can be used to load the
input registers if the input nibble is to be retained. No register clock signals are needed if the input data
is not being stored.
The banks of control flip-flops not selected as a control source can be loaded with new control words
or read out on CNTR15-CNTRO while the switch is operating. For example, the MSH data inputs can be
used to load flip-flop bank 1 of the LSH while bank 0 of the LSH is controlling data I/O.

TEXAS ."

INSTRUMENTS
POST OFFICE 80X 655012 • DALLAS. TEXAS 75265

....
(.)
:::::>

c

oa:
0..

M31A3Hd J.onaOHd

Lv88J.O"vLNS

een

Ol

-2

~

1:) .....

Example 1. Programming a Nibble Broadcast

o

tNST.

CR$RCE CRWRlTE2 CRWRITEl

CRWRITEO CRADRl CAADAO

CNTA 110 NUMBERS

CRSEL2

CRSEl'

CRSELO

WE

sELOMS SElDlS

0ED15-0EOO

O£C

CRCU<

11-8

7-4

3-0

1

0

0

0

0

0

0

1111

1111

1111

1111

X

X

X

X

0

X

X

xxxx xxxx xxxx xxxx

1

0

0

0

0

0

1

1111

1111

1111

1111

X

X

X

X

0

X

X

xxxx xxxx xxxx

r

2

XXXX

1

3

0

0

0

0

1

0

1111

1111

1111

1111

X

X

X

X

0

X

X

xxxx xxxx xxxx

XXXX

1

4

0

0

0

0

1

1

1111

1111

1111

1111

5

X

X

X

X

X

X

xxxx xxxx xxxx xxxx

NO.

15-12

::::j~

CRSEL3

X

X

X

X

0

X

X

xxxx xxxx xxxx

XXXX

1

J
J
J

0

0

0

0

1

1

X

1000

0000

1

None

0000

0000

n

:c

loads CF14. eFtO, CF6, CF2 of bank 0

loads eFtS, eF", CF7, CF3 of bank 0
Selects bank 0 for switching control
Selects real-time data inputs

~~

Z

Ciloet

Example 2. Programming an MSH/LSH Exchange on CNTR Inputs
INST
NO.

CRSRCE CAWAlTE2

CAWRITEI

CRWRITEO CRADAI CRAORO

CNTR I/O NUMBERS

0

15-12 "-8
0100 0000

H
,,00

CASEl3

CRSEL2

CQSEL 1

CASEtO

WE

1000

x

x

x

x

0

x

x

3-0

SELDMS SELOlS

2

0

1

1

1

0

1

0101

0001

1101

1001

X

X

X

X

0

X

X

3

0

1

1

1

1

0

0111

0011

1111

1011

X

X

X

X

0

X

X

4

0

1

1

1

1

1

0111

0011

1111

1011

X

X

X

X

0

X

X

5

x

X

x

x

x

x

xxxx xxxx xxxx xxxx

0

1

1

1

1

0

0

0000

0

1

1

1

0

Commentl

INST. NO

COMMENT
loads CF12, eF8. CF4, CfO of bank'
Loads CF13, CF9. CFS, CF1 of bank 7
Loads CF14. CF10, Cf6, CF2 of bank 1
Loads,CF1S. CF11. CFl. Cf3 of bank 7
Selects bank 7 for SWltchrng contrOl
$elects regIstered data rnputs

liEC

OE015·0E50

xxxx
xxxx
xxxx
xxxx

1

l:1li

>

::II

=e

Loads eFt3, CF9, CF5, eFt of bank 0

~r;;1

e~
en_
en

::::j

COMMENT
loads CF12, CF8, CF4. CFO of bank 0

z

n"""'i
::11=

en

Common..
INST. NO.

»r-n

xxxx
xxxx
xxxx
xxxx

xxx x xxxx
xxxx XXXX
xxx x XXXX
xxxx xxxx

1

0000

0000

1

0000

CRClK

1
1
1

;
None

SN74ACT8841
DIGITAL CROSSBAR SWITCH
programming an MSH/LSH exchange
A second, more complicated example involves programming the switch to swap corresponding nibbles
between the MSH and the LSH (first nibble in the LSH for first nibble in the MSH, and so on). This swap
can be implemented using the hard-wired logic circuit selected when CRSEL3 is high and CRSELO is low.
Programming this swap without using the MSH/LSH exchange logic requires loading a different control
word into each mux logic block. This is described below for purposes of illustration.
Each nibble in one half, either LSH or MSH, selects as output the registered data from the corresponding
nibble in the other half. The registered data from 035-032 is to be output on 03-00, the registered data
from 03-00 is output on 035-032, and so on for the remaining nibbles. As shown in Table 4, the flip-flops
for 03-00 have to be set to 1000 and the 035-032 inputs must be low. The CF groups and control words
involved in this switching pattern are listed in Table 9.

CF

CNTR INPUTS

WORD

FLlP·FLOPS

LOADED
0111

031-028 -'- 063-060

CF14

CNTA15-

0110

CNTA12

0101

027-024 023-020 -

059-056

CF13

051-048

CF15

RESULTS

CF12

0100

CF11

0011

019-016 015-012 -

055-052
047·044

CF10

CNTA11-

0010

011-08

-

043-040

CF9

CNTA8

0001

07-04

-

039-036

03-00 063-060 059-056 -

035-032

CF8
CF7

0000
1111

CF6

CNTA7-

CF5

CNTA4

1110 cc
1101

CF4

1100

CF3

1011

CF2

CNTA3-

1010

CFl

CNTAO

1001

CFO

1000

031-028
027-024

055-052 051-048 -

023-020

047-044 043-040 -

015-012

039-036
035-032

--

Il.

IU

:::>
C

0

a:

CONTROL

TO LOAD

W

a:

Il.

Table 9. Control Words for an MSH/LSH Exchange

GROUP

3:
W
>

019-016
011-08
07-04
03-00

With this list of control words and the signals in Table 7, the 16-bit control inputs on CNTR15-CNTRO
can be arranged to load the control flip-flops in four cycles. Example 2 shows the microcode instructions
for loading the control words and executing the exchange.
In Example 2, bank 7 of flip-flops is being programmed. Bank 7 is selected by taking CRWRITE2-CRWRITEO
high and leaving CRSRCE low (see Table 4) when the control words are loaded on CNTR15-CNTRO. With
WE held low, the CRCLK is used to load the four sets of control words. Once the flip-flops are loaded,
data can be input on 063-00 and the programmed pattern of output selection can be executed. A
microinstruction to select registered data inputs and bank 7 as the control source is shown as the last
instruction in Example 2. The data must be clocked into the input registers, using LSCLK and MSCLK,
before the last instruction is executed.

TEXAS •

INSTRUMENTS
POST OFFICE BOX 655012. DAllAS. TEXAS 75265

6-21

SN74ACT8841
DIGITAL CROSSBAR SWITCH
."
:%I

o
C
c(')

The control flip-flops could also have been loaded from the data input nibbles in one CRCLK cycle. Input
nibbles from one half are mapped onto the control flip-flops of the other half. All control words to set up
a switching pattern should be loaded before the bank of flip-flops is selected as control source. The
microcode instructions to load bank 1 with the 16 control words in one cycle are presented in Example 3.
Example 3. Loading the MSH/LSH Exchange from Data Inputs

-f

CRWRlTE2

CRWRITEI

CRWRITEO

WI!

."

o

0

I

0

::a

m

:sm
~

SELOMS

SELDLS

m16·m60
I I " l U I " " 1111

These control nibbles may be loaded from the input as a 64-bit real-time input word or as two 32-bit words
stored previously. To use stored control worels, MSCLK and LSCLK are used to load the LSH and MSH
input registers with the correct sequence of control nibbles. Whenever the flip-flops are loaded from the
data inputs, "II 64 bits of control data must be present when the CRCLK is used so that all control nibbles
in a program are loaeled simultaneously. Example 4 presents the three microcode instructions to load the
MSH and LSH input registers and then to Pass the registered data to flip-flop bank 2.
Example 4. Loading Control Flip-Flops from Input Registers
INST.
CRSRCE CRWRITE2 CRWRITEI CRWRITEO
NO_
1

X

X

2

X

X

3

1

0

WI!

SELDMS SELOLS

X

X

1

X

X

X

X

1

X

X

1

0

0

0

0

l5Ei516CRCLK MSCLK LSCLK COMMENTS
m60
load inputs
1
None
None
S
063-032
load inputs
1
None
None
S
031-00
Load control
1
None
None
S
bank 2

The control words in a program can also be read back from the flip-flop.s using the CNTR outputs. Four
instruction.s are necessary to read the 64 bits in a bank of flip-flops out on CNTR15-CNTRO. WE is held
high and OEC is taken·low. No CRCLK signal is required. CREAD2-CREADO select bank 2.of flip-flop~,
and CRADR l-CRADRO select in sequence the four addresses of the l6-bit words to be read out on the
CNTR outputs. Example 5 shows the four microcode instructions. .
Example 5. Reading Control Settings on CNTR Outputs
INST.
NO.
1
2
3
4

0
1

CNTR 110 NUMBERS
15-12 11-8 7-4
3-0
1 0100 DODO 1100 1000
1 0101 0001 1101 1001

Read CF12. CF8. CF4. CFO
Read CF13. CF9. CF5. CFl

0
1

1
1

Read CF14. CF10. CF6. CF2
Read CF16. CFll. CF7. CF3

CREAO;! CREAOI CREAPO ~ CRAORI CRAORO
0
0
0
0

1
1

0

0

0

0

1
1

0

0
0

0

0

0
1
1

WI!

0110 0010 1110 1010
0111 0011 1111 lOll

TEXAS ."

INSTRUMENlS
POST OfFICE BOX 65S012 • OALI.AS, TEXAS 75265

6-22

COMMENT

SN74ACT8841
DIGITAL CROSSBAR SWITCH
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, VCC . . . . . . . . .
. . . . . . . . . . . . . . . . . . -0.5 V to 6 V
Input clamp current, 11K IVI < 0 or VI > Vce) . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ...
. . . . . . . . . .
±50 mA
Continuous output current, 10 (VO = 0 to VCC)
. . . . . . . . . . . ±50 mA
Continuous current through VCC or GND pins. .
. . . . . . . . . . . . . . . .. ± 100 mA
Operating free-air temperature range .
.. ooC to 70°C
Storage temperature range ..
. . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions
PARAMETER

MIN
4.5
2
0

Supply voltage

vee
VIH
Vil
10H
10l
VI
Vo

Output voltage

dt/dv

Input transition rise or fall rate

TA

Operating free-air temperature

High-level input voltage

low-level input voltage

NOM
5.0

High-level output current

low-level output current
Input voltage

0
0
0
0

MAX
5.5

UNIT
v

Vee
0.8
-8
8
Vee
Vee
15
70

v

~

W

:;
w

a:

~

l-

e,.)
::;)

C

oa:

~

V
mA
mA
V
V
ns/V

De

electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER

TEST CONDITIONS
~

-20,A

10H

~

-8 mA

IOl

~

20 pA

10l

~

8 mA

10H
VOH

VOL

10l

II
ICC
el

Vo ~ Vee or 0
VI - Vee or 0
VI ~ Vee or O. 10
VI ~ Vee or 0

VCC

TA - 25 DC
MIN
TYP MAX

4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5V
4.5 V
5.5 V
5V
5.5 V
5.5 V
5V

MIN

TYP

MAX

UNIT

4.4
5.4
3.7
4.7

3.8
4.8

0.32
0.32
±O.5
0.1

lThis is'the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0

V

0.1
0.1
0.4
0.4
±0.5
±1
100

V

,A
,A
,A·
pF

V or Vee-

TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265

6-23

•
.....

~

CO
CO

SN74ACT8841
DIGITAL CROSSBAR SWITCH

l!
o

switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted I

o

Typt

MAX

7

14

10

18

9
12

15
19

CRSEL3-CRSELO

12

19

CREAD2-CREADO

10

18

10

18

8

16

PARAMETER

FROM

TO

MIN

Data in

C

MSCLK, LSCLK

C')
~

Data out

SELDMS, SELDLS
CRCLK

"0
::0

tpd

m

CRCLK

:$

CNTRn

CRAD 1, CRADO

m

:E

'en

tdis

tAli typical values are at

vee

TP1, TPO

AU outputs

10

19

TP1, TPO

All outputs

10

15

OED

Data out

7

12

OEC
TP1, TPO

CNTRn

8
10

14

om

All outputs
Data out

GEC

CNTRn

UNIT

ns

ns

15

5

8

6

10

ns

= 5 V, TA = 25°C.

timing requirements over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted I
PARAMETER
tw

MIN

LSCLK, MSCLK, CRCLK high or low

Pulse duration

Data
CNTRn
SELDMS, SELDLS
tsu

Setup time before CRClK

8

CRSRCE, CRWRITE2-CRWRITEO

8

'h

en
z
.....

th

Hold time after CRCLK

8

Data

0

CNTRn

0

SELDMS, SELDLS

0

CRADR 1, CRADRO

0

CRSRCE, CRWRITE

0

WE

0

7

0

Hold time, data after LSCLK or MSCLK

~

»
C')
-I
CO
CO

....
~

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265

6-24

UNIT
ns

ns

10

WE
Setup time. data before LSCLK or MSClK

MAX

9

CRADR1,CRADRO
LSCLK, MSCLK

tsu

7
7
7

ns

ns

ns

SN74ACT8841
DIGITAL CROSSBAR SWITCH

~
w

'AS8840 AND 'ACT8841 FUNCTIONAL COMPARISON
differences between the SN74AS8840.and the SN74ACT8841
The SN74AS8840 and the SN74ACT8841 digital crossbar switches essentially perform the same function·.
The SN74AS8840 and the SN74ACT8841 are based on the same 16-port architecture, differing in the
number of control registers, power consumption, and pin-out.
One difference is in the number of programmable control flip-flop banks available to configure the switch.
The 'AS8840 has two programmable control banks, while the 'ACT8841 has eight. Both have two
selectable hard-wired switching configurations.
The increased number of control banks in the' ACT8841 require six additional pins not found on the
'AS8840. These are: CRWRITE2, CRWRITE1, CREAD2, CREAD1, CRSEl3, and CRSEl2. CREAD and
CRWRITE on the '8840 become CREADO and CRWRITEO on the '8841. On the '8840, CRSEl1 selects
the hardwired control functions when high. This function is performed by the CRSEl3 signal on the '8841.
Therefore, CRSEl2 and CRSEl1 are actually the added signals.
The 'ACT8841 is a low-power CMOS device requiring only 5-V power. Because of its STl internal logic
and TTL liDs, the' AS8840 requires both 2-Vand 5-V power.
Both the' AS8840 and the' ACT8841 are in 156 pin grid-array packages, however, the two devices are
not pin-for-pin compatible. Control signals were added to the' ACT8841 and the 2-V VCC pins (' AS8840
only) were assigned other functions in the' ACT8841 .

changing 'AS8840 microcode to 'ACT8841 microcode
Since only six signals have been added to the 'ACT8841, changing existing 'AS8840 microcode to
'ACT8841 microcode is straight forward. CRSEl3 on the' ACT8841 is functionally equivalent to CRSEl 1
on the 'AS8840. CREAD2, CREAD1, CRWRITE2, CRWRITE1, CRSEl2, and CRSEl1 bits must be added.
These can always be 0 if no additional control banks are needed. Additional control configurations can
be stored by programming these bits.
All other signals in the' AS8840 microcode remain the same when converting to 'ACT8841 microcode.

TEXAS " ,
INSTRUMENTS
POST OffiCE BOX 655012. DALLAS. TEXAS 75265

6-25

:>w
a::

Il..

t-

()

:::>

c
o
a::

Il..

en
2

-..J
~

l>

(")

-I

00
00
~

.

~

6-26

SN74ACT8847

64-Bit Floating Point/Integer Processor

7-1

SN74ACT8847
64·8it Floating Point Unit
•

Superset of Tl's SN74ACT8837

•

30-ns, 40-ns and 60-ns Pipelined Performance

•

Low-Power EPIC'· CMOS

•

Meets IEEE Standard for Single- and DoublePrecision Formats

•

Performs Floating Point and Integer Add,
Subtract, Multiply, Divide, Square Root, and
Compare

•

64-Bit IEEE Divide in 11 Cycles, 64-Bit Square
Root in 14 Cycles

•

Performs Logical Operations and Logical Shifts
The SN74ACT8847 is a high-speed, double-precision floating point and integer
processor. It performs high-accuracy, scientific computations as part of a
customized host processor or as a powerful stand-alone device. Its advanced
math processing capabilities allow the chip to accelerate the performance of both
CISC- and RISC- based systems.
High-end computer systems, such as graphics workstations, mini-computers and
32-bit personal computers, can utilize the single-chip' ACT884 7 for both floating
point and integer functions.

EPIC is a trademark of Texas Instruments Incorporated.

7-3

7-4

Contents
Page
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .

7-15

Understanding the' ACT8847 Floating Point Unit .........
Microprogramming the ' ACT884 7 ....................
Support Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Support ..................................
, ACT884 7 Logic Symbol ...........................
Design Expertise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
, ACT8847 Pin Descriptions .........................
, ACT884 7 Specifications ...........................

.
.
.
.
.
.
.
.

7-15
7-15
7-16
7-16
7-17
7-18
7-18
7-26

SN74ACT8847 Floating Point Unit . ..................... .

7-33

Data Flow ...................................... .
Input Data Parity Check ........•....................
Temporary Input Register ........................... .
RA and RB Input Registers .......................... .
Multiplier/ALU Multiplexers .......................... .
Pipe lined ALU ................................... .
Pipe lined Multiplier ................................ .
Product, Sum, and C Registers ....................... .
Parity Generators ................................. .
Master/Slave Comparator ........................... .
. Status and Exception Generation ..................... .
Flowthrough Mode ................................ .
Fast and IEEE Modes .............................. .
Rounding Mode .................................. .
Test Pins ....................................... .
Summary of Control Inputs ......................... .

7-33
7-35
7-35
7-35
7-37
7-37
7-41
7-42
7-42
7-42
7-42
7-45
7-46
7-46
7-46 ~
7-46 ClO

"

ClO

....

U

~

~

"2:

en

7-5

Contents (Continued)
Page

Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 -48

Loading External Data Operands. . . . . . . . . . . . . . . . . . . . . .
Configuration Controls (CONFIG1-CONFIGO) . . . . . . . . . . . . .
CLKMODE Settings .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. .
Internal Register Operations . . . . . . . . . . . . . . . . . . . . . . . . .
Data Register Controls (PIPES2-PIPESO) . . . . . . . . . . . . . . . .
C Register Controls (SRCC, CLKC, FLOWC, ENRC) . . . . . . . .
Operand Selection (SELOP7-SELOPO) . . . . . . . . . . . . . . . . . .
Rounding Controls (RND1-RNDO) . . . . . . . . . . . . . . . . . . . . .
Status Exceptions ........ . . . . . . . . . . . . . . . . . . . . . . . .
Handling of Denormalized Numbers (FAST) . . . . . .. . . . . .
Exception Disable Mask Register ...................
Data Output Controls (SELMS/LS, OEY) . . . . . . . . . . . . . . . .
Status Output Controls (SELST1-SELSTO, OES, OEC) . . . . . .
Stalling the Device (HALT) . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Inputs (110-10). . . . . . . . . . . . . . . . . . . . . . . . . . .
Independent ALU Operations ......................
Independent Multiplier Operations. . . . . . . . . . . . . . . . . . .
Chained Multiplier/ALU Operations. . . . . . . . . . . . . . . . . .

7 -48
7-48
7-48
7 -49
7-50
7-50
7-51
7-51
7 -51
7-54
7-55
7-56
7-56
7-56
7-57
7-57
7-60
7-61

Microprogramming the 'ACT884 7 ......................

7 -64

Single-Precision Operations ........................ .
Single-Precision ALU Operations ................... .
Single-Precision Multiplier Operations ............... .
Sample Single-Precision Microinstructions ............ .
Double-Precision Operations ........................ .
Double-Precision ALU Operations .................. .
Double-Precision ALU Operations with CLKMODE = 0 ..
Double-Precision ALU Operations with CLKMODE = 1 ..
Double-Precision Multiplier Operations ............... .
Double-Precision Multiplication with CLKMODE = 0
Double-Precision Multiplication with CLKMODE = 1 ....

7-64
7-64
7-64
7-65
7-70
7-70
7-70
7-78
7-85
7-85
7-91

7-6

Contents (Concluded)
Page

Division and Square Root Operations .................
Division Microinstructions ........................
Single-Precision Floating-Point Division ............
Double-Precision Floating-Point Division ...........
Integer Division .............................
Square Root Microinstructions ....................
Single-Precision Floating-Point Square Root .........
Double-Presion Floating-Point Square Root .........
Integer Square Root ..........................
Chained Multiplier/ALU Operations ... ; ...............
Fully Pipelined Double-Precision Operations .............
Mixed Operations and Operands .....................
Matrix Operations ...............................
Representation of Variables ......................
Sample Matrix Transformation ....................
Microinstructions for Sample Matrix Manipulation ......

.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.

7-98
7-98
7-98
7-102
7-107
7-110
7-111
7-115
7-119
7-123
7-124
7-127
7-129
7-129
7-130
7-137

Glossary . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . , . . . . . .

7-142

7-7

List of Illustrations
Figure

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

Page

' ACT884 7 Floating Point Unit .................... .
Single-Precision Operation, A" Registers Disabled
(PIPES = 111, CLKMODE =0) ................. .
Single-Precision Operation, Input Registers Enabled
(PIPES = 110, CLKMODE = 0) ................. .
Single-Precision Operation, Input and Output Registers
Enabled (PIPES = 010, CLKMODE = 0) ........... .
Single-Precision Operation, A" Registers Enabled
(PIPES = 000, CLKMODE = 0) ................. .
Double-Precision ALU Operation, A" Registers Disabled
(PIPES = 111, CLKMODE = 0) ................. .
Double-Precision ALU Operation, Input Registers Enabled
(PIPES = 110, CLKMODE = 0) ................. .
Double-Precision ALU Operation, Input and Output
Registers Enabled (PIPES = 010, CLKMODE = 0) .....
Double-Precision ALU Operation, A" Registers Enabled
(PIPES = 000, CLKMODE = 0) ................. .
Double-Precision ALU Operation, A" Registers Disabled
(PIPES = 111, CLKMODE = 1) ................. .
Double-Precision ALU Operation, Input Registers Enabled
(PIPES = 110, CLKMODE = 1) ................. .
Double-Precision ALU Operation, Input and Output
Registers Enabled (PIPES = 010, CLKMODE = 1) .....
Double-Precision ALU Operation, A" Registers Enabled
(PIPES = 000, CLKMODE = 1) ................. .
Double-Precision Multiplier Operation, A" Registers
Disabled (PIPES = 111, CLKMODE = 0) .......... .
Double-Precision Multiplier Operation, Input Registers
Enabled (PIPES = 110, CLKMODE = 0) ........... .
Double-Precision Multiplier Operation, Input and Output
Registers Enabled (PIPES = 010, CLKMODE = 0) .....
Double-Precision Multiplier Operation, A" Registers
Enabled (PIPES = 000, CLKMODE = 0) ........... .
Double-Precision Multiplier Operation, A" Registers
Disabled (PIPES = 111, CLKMODE = 1) .......... .

7-34
7-65
7-66
7-67
7-67
7-71
7-73
7-75
7-77
7-79
7-80
7-81
7-84

......
7-86
7-87

~

ex)
ex)

~

7-88

«
~

7-90

en

2

7-92

7-9

List of Illustrations (Continued)
Figure

Double-Precision Multiplier Operation, Input Registers
Enabled (PIPES = 110, CLKMODE = 1) .......... .
20 Double-Precision Multiplier Operation, Input and Output
Registers Enabled (PIPES = 010, CLKMODE = 1) ....
21
Double-Precision Multiplier Operation, All Registers
Enabled (PIPES = 000, CLKMODE = 1) .......... .
22 Single-Precision Floating Point Division
(PIPES2-PIPESO = 110) ...................... .
23 Single-Precision Floating Point Division
(PIPES2-PIPESO = 100) ...................... .
24 Single-Precision Floating Point Division
(PIPES2-PIPESO = 010) ...................... .
25 Single-Precision Floating Point Division
(PIPES2-PIPESO = 000) ...................... .
26 Double-Precision Floating Point Division
(PIPES2-PIPESO = 110) ...................... .
27 Double-Precision Floating Point Division
(PIPES2-PIPESO = 100) ...................... .
28 Double-Precision Floating Point Division
(PIPES2-PIPESO = 010) ...................... .
29 Double-Precision Floating Point Division
(PIPES2-PIPESO = 000) ...................... .
30 Integer Division (PIPES2-PIPESO = 110) ........... .
Integer Division (PIPES2-PIPESO = 100) ........... .
31
32 . Integer Division (PIPES2-PIPESO = 010) ........... .
33 Integer Division (PIPES2-PIPESO = 000) ........... .
34 Single-Precision Floating Point Square Root
(PIPES2-PIPESO = 110) ...................... .
35 Single-Precision Floating Point Square Root
(PIPES2-PIPESO = 100) ...................... .
36 Single-Precision Floating Point Square Root
(PIPES2-PIPESO = 010) ...................... .
37 Single-Precision Floating Point Square Root
(PIPES2-PIPESO = 000) ...................... .
38 Double-Precision Floating Point Square Root
(PIPES2-PIPESO = 110) ...................... .
39 Double-Precision Floating Point Square Root
(PIPES2-PIPESO = 100) ...................... .

Page

19

7-10

7-93
7-95
7-97
7-99
7-100
7-101
7-102
7-103
7-104
7-105
7-106
7-107
7-108
7-109
7-110
7-111
7-112
7-113
7-114
7-115
7-116

List of Illustrations (Concluded)
Figure

40
41
42

43
44
45

46
47

48
49

Page

Double-Precision Floating Point Square Root
(PIPES2-PIPESO = 010) .......................
Double-Precision Floating Point Square Root
(PIPES2-PIPESO = 000) .......................
Integer Square Root (PIPES2-PIPESO = 110) ........
Integer Square Root (PIPES2-PIPESO = 100) ........
Integer Square Root (PIPES2-PIPESO = 010) ........
Integer Square Root (PIPES2-PIPESO = 000) ........
Mixed Operations and Operands
(PIPES2-PIPESO = 110, CLKMODE = 0) ..........
Mixed Operations and Operands
(PIPES2-PIPESO = 000, CLKMODE = 1)
Sequence of Matrix Operations ...................
Resultant Matrix Transformation ..................

.

7-117

.
.
.
.
.

7-118
7-119
7-120
7-121
7-122

.

7-128

.
.

7-128
7-133

7-140

7,-11

7-12

List of Tables
Table

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

Page

' ACT884 7 Pin Grid Allocations ..................
' ACT884 7 Pin Functional Description ..............
Double-Precision Input Data Configuration Modes .....
Single-Precision Input Data Configuration Mode ......
Double-Precision Input Data Register Sources ........
Multiplier Input Selection .......................
ALU Input Selection ..........................
Independent ALU Operations, Single Floating Point
Operand .................................
Independent ALU Operations, Two Floating Point
Operands ................................
Independent ALU Operations, Single Integer Operand ..
Independent ALU Operations, Two Integer Operands ..
Independent Multiplier Operations ................
Independent Multiplier Operations Selected by 14-12 ...
Independent Divide/Square Root Operations
Selected by 14-12 ...........................
Formats Selected by 18-17 ......................
Chained Multiplier/ALU Operations ................
Comparison Status Outputs .....................
Status Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Output Selection (Chain Mode) .............
Pipeline Controls (PIPES2-PIPESO) ................
Rounding Modes .............................
Test Pin Control Inputs ........................
Control Inputs ...............................
IEEE Floating-Point Representations ...............
Handling Wrapped Multiplier Outputs ..............
Loading the Exception Disable Mask Register ........
Independent ALU Operations with One Floating Point
Operand .................................
Independent ALU Operations with Two Floating Point
Operands ................................
Independent ALU Operations with One
Integer Operand ...........................

.
.
.
.
.
.
.

7-19
7-20
7-36
7-36
7-36
7-37
7-37

.

7-38

.
.
.
.
.

7-39
7-39
7-40
7-40
7-41

.
.
.
.
.
.
.
.
.
.
.
.
.

7-41
7-42
7-43
7-44
7-44
7-45
7-45
7-46
7-46
7-47
7-53
7-54
7-55

.

7-58

f'

~

00
00

tO

«
~
f'

Z

.

7-59

.

7-59

7-13

CI)

List of Tables (Concluded)
Table
30
31
32
33
34
35
36
37
38

39

40
41
42

7-14

Page
Independent ALU Operations with Two
Integer Operands" " " " " " " " " " " " " " " " " " " " " " " " " " " "
Independent Floating Point Multiply Operations """""""
Independent Floating Point Divide/Square Root
Operations """"""""""""""""""""""""""""""""
Independent Integer Multiply/Divide/Square Root
Operations ""."""""""""""""""""""""""""""""
Chained Multiplier/ALU Floating Point Operations" " " " " "
Chained Multiplier/ALU Integer Operations" " " " " " " " " " "
Single-Precision Sum of Products
(PIPES2-PIPESO = 010) " " " " " "" " " " " " " " " " " " " " " " "
Sample Microinstructions for Single-Precision
Sum of Products " " " " " " " " " " " " " " " " " " " " " " " " " " " "
Fully Pipelined Double-Precision Sum of Products
(CLKM = 0, CONFIG = 10, PIPES = 000,
CLKC+-+SYSCLK) " ,; " " " " " " " " " " " " " " " " " " " " " " " "
Fully Pipelined Double-Precision Product of Sums
(CLKM = 0, CONFIG = 10, PIPES = 000,
CLKC+-+SYSCLK) " " " " " " " " " " " " " " " " " " " " " " " " " ""
Microinstructions for Sample Matrix Manipulation" " " " " "
Single-Precision Matrix Multiplication
(PIPES2-PIPESO = 010)" " " " " . " " " " " " " " " " " " " " " " "
Fully Pipelined Sum of Products
(PIPES2-PIPESO = 000) " " " " " " " " " " " " " " " " " " " " " " ;

7-60
7-60
7-61
7-61
7-62
7-63
7-123
7-124

7-125

7-126
7-138
7-139
7-141

Introduction
The SN74ACT8847 combines a multiplier and an arithmetic-logic unit in a single
microprogrammable VLSI device. The' ACT884 7 is implemented in Texas Instruments
one-micron CMOS technology to offer high speed and low power consumption with
exceptional flexibility and functional integration. The FPUs can be microprogrammed
to operate in multiple modes to support a variety of floating point applications.
The 'ACT884 7 is fully compatible with the IEEE standard for binary floating point
arithmetic, STD 754-1985. This FPU performs both single- and double-precision
operations, integer operations, logical operations, and division and square root
operations (as single microinstructions).

Understanding the ' ACT884 7 Floating Point Unit
To support floating point processing in IEEE format, the' ACT884 7 may be configured
for either single- or double-precision operation. Instruction inputs can be used to select
three modes of operation, including independent ALU operations, independent multiplier
operations, or simultaneous ALU and multiplier operations.
Three levels of internal. data registers are available. The device can be used in
flowthrough mode (all registers disabled), pipelined mode (all registers enabled), or
in other available register configurations. An instruction register, a 64-bit constant
register, and a status register are also provided.
Each FPU can handle three types of data input formats. The ALU accepts data operands
in integer format or IEEE floating point format. A third type of operand, denormalized
numbers, can also be processed after the ALU has converted them to "wrapped"
numbers, which are explained in detail in a later section. The' ACT884 7 multiplier
operates on normalized floating-point numbers, wrapped numbers, and integer
operands.

Microprogramming the ' ACT884 7
The' ACT884 7 is a fully microprogrammable device. Each FPU operation is specified
by a microinstruction or sequence of microinstructions which set up the control inputs
of the FPU so that the desired operation is performed.
The microprogram which controls operation of the FPU is stored in the microprogram
memory (or control store). Execution of the microprogram is controlled by a
microsequencer such as the TI SN74ACT8818 l6-bit microsequencer. A discussion
of microprogrammed architecture and the operation of the' ACT8818 is presented
in this Data Manual.

7-15

"'I:t

00
00

....
«
'I:t

(.)

"2

en

Support Tools
Texas Instruments has developed functional evaluation models of the 'ACT884 7 in
software which permit designers to simulate operation of the FPU. To evaluate the
functions of an FPU, a designer can create a microprogram with sample data inputs,
and the simulator will emulate FPU operation to produce sample data output files, as
well as several diagnostic displays to show specific aspects of device operation. Sample
microprogram sequences are included in this section.
Texas Instruments has also designed a family of low-cost real-time evaluation modules
(EVM) to aid with initial hardware and microcode design. Each EVM is a small selfcontained system which provides a convenient means to test and debug simple
microcode, allowing software and hardware evaluation of components and their
operation.
At present, the 74AS-EVM-8 Bit-Slice Evaluation Module .has been completed, and
a 16-bit EVM is in an advanced stage of development. EVMs and support tools for
devices in the VLSI family are planned for future development.

Design Support
Texas Instruments Regional Technology Centers, staffed with systems-oriented
engineers, offer a training course to assist users of TI LSI products and their application
to digital processor systems. Specific attention is given to the understanding and
generation of design techniques which implement efficient algorithms designed to
match high-performance hardware capabilities with desired performance levels.
Information on VLSI devices and product support can be obtained from the following
Regional Technology Centers:

CJ)

Z

"-oJ

~

l>

n

-t

CO
CO
~

"-oJ

Atlanta
Texas Instruments Incorporated
3300N.E. Expressway, Building 8
Atlanta, GA 30341
404/662-7945

Chicago
Texas Instruments Incorporated
51 5 Algonquin
Arlington Heights, IL 60005
312/640-2909

Boston
Texas Instruments Incorporated
950 Winter Street, Suite 2800
Waltham, MA 02154
617/895-9100

Dallas
Texas Instruments Incorporated
10001 E. Campbell Road
Richardson, TX 75081
214/680-5066

Northern California
Texas Instruments Incorporated
5353 Betsy Ross Drive
Santa Clara, CA 95054
408/748-2220

Southern California
Texas Instruments Incorporated
17891 Cartwright Drive
Irvine, CA 92714
714/660-8140

7-16

. ACT884 7 Logic Symbol
4>
ACT8847
64-Bit Floating Point Unit

C REGISTER CLOCK

CLKC
CLKMODE

CLOCK EDGE

BYTEP

PARITY GENERATION

CONFIG1~0

FAST

ENRC
FLOWC
SELOP7·0

Lr::,.

SUDDEN

~

ALU AND MULTIPLIER I FlOWTHROUGH
PIPELINE REGISTERS
EN

~

STATUS. P. AND S I FLOWTHROUGH
REGISTERS
EN

~

~

MUL TIPLIER

;R~TE

I

SELECT

C REG
PARITY
If 0

BYPASS
OPERAND SOURCE
STATUS SOURCE

LJ::::.

10

MSHI
LSH Y BUS

STATUS
PARITY

DA31
080

DB31

PB3~0
PY3~0

I

PERRA

DA DATA
DB DATA
MASTER/SLAVE
COMPARATOR

PERRB
MSERR

I

UNORD
AGTB
AEUB
ED
DIVBYO
IVAL
INEX
OVER
UNDER
DENORM
DEN IN
RNDCO
SRCEX
CHEX

EXCEPTION
AND
OTHER
STATUS

LOAD RA REGISTER
LOAD RB REGISTER

_l'--, EXCEPTION & OTHER STATUS

r-.,

'"

EN

STEX1~0

COMPARISON STATUS

NEG
INF

Y31~YO. PY3~PYO

-,

r

··•
··• ·•

···

···

0

0

31

~

P)PES2

PA3~0

INSTRUCTION

10

PIPES1

DB DATA

COMPARISON
STATUS

12
13
14
15
16
17
18
19
110

PIPE SO

DA DATA

0

11

DAO

I

Y BUS

TP1~0

ENRA
ENRB
OES
OEC
OEY

/1

INSTRUCTION. RA. & RB I FlOWTHROUGH
EN
REGISTERS

IUNDER'
FLOW

GRADUAL

ROUNDING MODE

SELST1~O

SELMS/LS

STAllS OPERATION

DATA SOURCE

RND1~0

SRCC

CLEARS STATES
& STATUS /1

MASTER CLOCK (EXCEPT C REGISTER)

CLK

~

31

..

YO

~

Y31

0

31

~

7-17

Design Expertise
Texas Instruments can provide in-depth technical design assistance through
consultations with contract design services. Contact your local Field Sales Engineer
for current information or contact VLSI Systems Engineering at 214/997-3970.

, ACT884 7 Pin Descriptions
Pin descriptions and grid allocation for the' ACT884 7 are given on the following pages.
208 PIN ... GA PACKAGE
(TOP VIEW)

A
B
C

D
E
F
G

H

J
K

L

M
N
CJ)

Z
.....

p

»

R

-t

S

~

(")
(Xl
(Xl
~

T

.....

7-18

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•

2

3

4

5

6

7

8

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•

•
•
•
•

•
•
•
•

•
•
•
•

• • • • • • • • •
• • • • • • • • •
• • • • • • • • •
• • • • • • • • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • • • • • • • •
• • • • • • • • •
• • • • • • • • •
• • • • • • • • •

•

•
•
•
•

•
•
•
•
•
•

•
•
•
•

•
•
•
•

•
•

•
•

9

10 11

12 13 14 15 16 17

•
•
•
•
•

•
•
•
•
•

•
•
•
•
•
•
•

Table 1. 'ACT8847 Pin Grid Allocation

PIN
NO. NAME
A1 NC
A2 INF
A3 Y5
A4 Y8
A5 Y11
A6 Y14
A7 Y17
A8 Y20
A9 Y21
A10 Y24
Al1 Y27
A12 Y29
A13 PYO
A14 PY3
A151VAL
A16 NEG
A17 NC
81 ED
82 Y2
83 Y4
84 Y7
85 Y10
86 Y13
B7 Y16
B8 Y19
89 Y22
B10 Y25
B11 Y28
B12 Y31
B13 PY2
B14 OVER
815 RNDCO
B16 DENORM
B17 DIV8YO
C1 PERRB

NO.
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
El
E2

PIN
NAME
YO
Y3
Y6
Y9
Y12
Y15
Y18
Y23
Y26
Y30
PY1
UNDER
INEX
DENIN
SRCEX
CHEX
11
RND1
Y1
GND
VCC
GND
GND
VCC
GND
GND
VCC
GND
GND
VCC
STEX1
STEXO
UNORD
12
10

NO.
E3
E4
E14
E15
E16
E17
F1
F2
F3
F4
F14
F15
F16
F17
G1
G2
G3
G4
G14
G15
G16
G17
H1
H2
H3
H4
H14
H15
H16
H17
J1
J2
J3
J4
J14

PIN
NAME
FAST
GND
GND
AGT8
AEQ8
MSERR
15
13
RNDO
GND
GND
PERRA
OEY

NO.
J15
J16
J17
K1
K2
K3
K4
K14
K15
K16
K17
L1
L2
OES
L3
17
L4
16
L14
14
L15
L16
VCC
L17
VCC
OEC
M1
SELMS/LS M2
TEST1
M3
110
M4
19
M14
18
M15
GND
M16
M17
GND
TESTO
N1
SELST1
N2
SELSTO
N3
SELOP2
N4
SELOP1
N14
SELOPO
N15
N16
VCC
N17
VCC

PIN
NAME
FLOWC
SRCC
8YTEP
SELOP3
SELOP4
SELOP5
GND
GND
PA1
PA2
PA3
SELOP6
SELOP7
CLK
VCC
GND
DA30
DA31
PAO
ENR8
ENRA
CLKC
GND
VCC
DA27
DA28
DA29
CONFIGO
CONFIG1
CLKMODE
PIPES2
DA18
DA24
DA25
DA26

NO.
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17

PIN
NAME
ENRC
PIPESO
RESET
P81
D81
D85
D89
D816
D821
D828
DAO
DA4
DA8
DA12
DA19
DA22
DA23
PIPES1
HALT
P82
D82
D86
D810
DB14
DB18
D822
DB27
D831
DA3
DA7
DA11
DA16
DA20
DA21

PIN
NAME
NC
PBO
DBO
DB4
DB11
DB12
DB15
DB19
DB23
DB26
DB30
DA2
DA6
DA10
DA14
DA15
DA17
NC
P83
DB3
DB7
DB8
DB13
T7 DB17
T8 DB20
T9 DB24
T10 DB25
T11 DB29
T12 DA1
T13 DA5
T14 DA9
T15 DA13
T16 NC
T17 NC
NO.
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
T1
T2
T3
T4
T5
T6

7-19

Table 2. 'ACT8847 Pin Functional Description
PIN
NAME

7-20

NO.

1/0

AEQB

E16

I/O

AGTB

E15

I/O

BYTEP

J17

I

CHEX

C17

I/O

ClK
ClKC

l3
M3

I
I

ClKMODE

N3

I

CONFIGO
CONFIGl
DAO
DAl
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DAll
DA12
DA13
DA14
DA15
DA16
DA17
DA18
DA19
DA20
DA21
DA22
DA23
DA24

Nl
N2
Pll
T12
S12
R12
P12
T13
S13
R13
P13
T14
S14
R14
P14
T15
S15
S16
R15
S17
N14
P15
R16
R17
P16
P17
N15

I

I

DESCRIPTION
Comparison status or zero detect pin. When high,
indicates that A and B operands are equal during a
compare operation in the AlU. If not a compare, a
high signal indicates a zero result on the Y bus.
Comparison status pin. When high, indicates that A
operand is greater than B operand.
When high, selects parity generation for each byte
of input (four parity bits for each bus). When low,
selects parity generation for whole 32-bit input
(one parity bit for each bus).
Status pin indicating an exception during a chained
function. If 16 is low, indicates the multiplier is the
source of an exception. If 16 is high, indicates the
AlU is the source of an exception.
Master clock for all registers except C register
C register clock
Selects whether temporary register loads only on
rising clock edge (ClKMODE = l) or on falling
edge (ClKMODE = H).
Select data sources for RA and RB registers from
DA bus, DB bus and temporary register

DA 32-bit input data bus. Data can be latched in a
64-bit temporary register or loaded directly into an
input register

Table 2. 'ACT8847 Pin Functional Description (Continued)
PIN
NAME

NO.

110

DESCRIPTION

I

OA 32-bit input data bus. Data can be latched in a
64-bit temporary register or loaded directly into an
input register.

OA25
OA26
OA27
OA28
OA29
OA30
DA31
OBO
DBl
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
OB10
OBll
DB12
OB13
DB14
DB15
D816
OB17
OB18
OB19
OB20
DB21
OB22
DB23
OB24
OB25
DB26
OB27
0828
D829
DB30
DB31

N16
N17
M15
M16
M17
L15
L16
S3·
P5
R4
T3
S4
1"6
R5
T4
T5
P7
R6
S5
S6
T6
R7
S7
P8
T7
R8
S8
T8
P9
R9
S9
T9
Tl0
S10
Rl0
Pl0
Tl1
S11
Rl1

DENIN

C15

I/O

DENORM

B16

110

I

DB 32-bit input data bus. Data can be latched in a
64-bit temporary register or loaded directly into an
input register.

Status pin indicating a denormal input to the
multiplier. When OENIN goes high, the STEX pins
indicate which port had the denormal input.
Status pin indicating a denormal output from the
AlU or a wrapped output from the muHiplier. In
FAST mode, causes the. result to go to zero when
DENORM is high.
7-21

Table 2 .• ACT8847 Pin Functional Description (Continued)
PIN
NAME

7-22

NO.

1/0

OIVBYO

B17

110

ED

B1

110

ENRA

M2

I

ENRB

M1

I

ENRC

P1

I

FAST

E3

I

FLOWC

J15

I

GND
GNO
GNO
GND
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO
GNO

04
06
07
09
010
012
013
E4
E14
F4
F14
H4
H14
K4
K14
L14
M4

HALT

R2

DESCRIPTION
Status pin indicating an attempted operation
involved dividing by zero
Exception detect status signal representing logical
OR of all enabled exceptions in the exception
disable register
When high. enables loading of RA register on a
rising clock edge if the RA register is not disabled
(see PIPESO below).
When high, enables loading of RB register on a
rising clock edge if the RB register is not disabled
(see PIPESO below).
When low, enables write to C register when CLKC
goes high.
When low, selects gradual underflow (IEEE modell.
When high, selects sudden underflow. forcing all
denormalized inputs and outputs to zero.
When high, causes product or sum to bypass
C register, so that product or sum appears on the
C register output bus. Timing is similar to P register
or S register feedback operands. C register remains
unchanged. Product or sum may also be
simultaneously fed back in usual manner (not
through C register).

Ground pins. NOTE: All ground pins should be
used and connected.

I

Stalls operation without altering contents of
instruction or data registers. Active low.

Table 2. 'ACT8847 Pin Functional Description (Continued)
PIN
NAME

NO.

DESCRIPTION

1/0

10
11
12
13
14
15
16
17
18
19
110
INEX
INF

E2
D1
E1
F2
G3
F1
G2
G1
H3
H2
H1
C14
A2

I/O
I/O

IVAL

A15

0

MSERR
NC
NC
NC
NC
NC
NC
NEG
OEC

E17
A1
A17
S1
T1
T16
T17
A15
G15

0

I/O
I

OES

F17

I

OEY

F16

I

OVER

B14

I/O

PAO
PAl
PA2
PA3
PBO
PB1
PB2
PB3

L17
K15
K16
K17
S2
P4
R3
T2

PERRA

F15

0

PERRB

C1

0

I

Instruction inputs

Status pin indicating an inexact output
When high, indicates output value is infinity.
Status pin indicating that an invalid operation or a
non number (NaNl has been input to the multiplier
or ALU.
Master/Slave error output pin

No internal connection. Pins should be left floating

When high, indicates result has negative sign.
Comparison status output enable. Active low.
Exception status and other status output enable;
Active low.
Y bus output enable. Active low.
Status pin indicating that the result is greater the
largest allowable value for specified format
(exponent overflowl.

I

Parity inputs for DA data

I

Parity inputs for DB data

DA data parity error output. When high, signals a
byte or word has failed an even parity check.
DB data parity error output. When high, signals a
byte or word has failed an even parity check.

7-23

Table 2 .• ACT884 7 Pin Functional Description (Continued)
PIN
NAME

•
7-24

NO.

DESCRIPTION

I/O

PIPESO

P2

I

PIPES1

R1

I

PIPES2

N4

I

PYO
PY1
PY2
PY3

A13
C12
B13
A14

I/O

RESET

P3

I

RNDO
RND1

F3
D2

I

RNDCO

B15

I/O

SELOPO
SELOP1
SELOP2
SELOP3
SELOP4
SELOP5
SELOP6
SELOP7
SELSTO
SELST1

J3
J2
J1
K1
K2
K3

When low, enables instruction register and,
depending on setting of ENRA and ENRB, the RA
and RB input registers. When high, puts instruction,
RA and RB registers in flowthrough mode.
When low. enables pipeline registers in ALU and
multiplier. When high, puts pipeline registers in
flowthrough mode.
When low. enables status register, product (P) and
sum (S) registers. When high, puts status register,
P and S registers in flowthrough mode.

Y port parity data
Clears internal states, status, and exception disable
register. Contents of internal pipeline registers are
lost. Does not affect other data registers. Active
low.
Rounding mode control pins. Select four IEEE
rounding modes.
When high, indicates the mantissa of a wrapped
number has been increased in magnitude by
rounding.

I

Select operand sources for multiplier and ALU

I

Select status source during chained operation

L1
L2
H17
H16

SELMS/LS

G16

I

SRCC

J16

I

SRCEX

C16

I/O

STEXO
STEX1

D16
D15

I/O

When low, selects LSH of 64-bit result to be
output on the Y bus. When high, selects MSH of
64-bit result. (No effect on single-precision
operations. )
When low, selects ALU as data source for C
register. When high, selects multiplier as data
source for C register.
Status pin indicating source of exception, either
ALU (SRCEX = L) or multiplier (SRCEX = H).
Status pins indicating that a nonnumber (NaN) or
denormal number has been input on A
port (STEX 1) or B port (STEXO).

Table 2. 'ACT8847 Pin Functional Description (Continued)
PIN
NAME

NO.

DESCRIPTION

I/O

TESTO
TESTl

H15
G17

I

UNOER

C13

I/O

Status pin indicating that a result is inexact and
less than minimum allowable value for format
(exponent underflow).

UNORO

017

I/O

Comparison status pin indicating that the two
inputs are unordered because at least one of them
is a nonnumber (NaN).

VCC
VCC
VCC
Vce
VCC
VCC
VCC
VCC
VCC
VCC
YO
Yl
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Yl1
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26

05
08
011
014
G4
G14
J4
J14
L4
M14
C2
03
B2
C3
B3
A3
C4
B4
A4
C5
B5
A5
C6
86
A6
C7
B7
A7
C8
88
A8
A9
89
C9
Al0
810
Cl0

Test pins

5-V power supply

lID

32-bit Y output data bus

7-25

Table 2. 'ACT8847 Pin Functional Description (Concluded)
PIN
NAME
Y27
Y28
Y29
Y30
Y31

NO.
A 11
B11
A12
e11
B12

I/O

1/0

DESCRIPTION

32-bit Y output data bus

, ACT884 7 Specifications
absolute maximum ratings over operating free-air temperature range
(unless otherwise noted) t
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . .. ~0.5 V to 6 V
Input clamp current, 11K (VI < 0 or VI > Vcc) ........ ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > VCC). . . .. ± 50 mA
Continuous output current, 10 (VO = VCC ........... ± 50 mA
Continuous current through VCC or GND pins , . . . . . .. ± 100 mA
Operating free-air temperature range . . . .. . . . . . . .. ooC to 70 0 C
Storage temperature range. . . . . .. . . . . . . . . .. - 65 DC to 150 DC
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage
to the device. These are stress. ratings only and functional operation of the device at these or
any other conditions beyond those indicated under "recommended operating conditions" is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.

recommended operating conditions
PARAMETER

SN74ACT8847
NOM

MAX

4.75

5.0

5.25

V

VCIi:

V

Vee

Supply voltage

VIH

High-level· input voltage

2

VIL

Low-level input voltage

0

10H

High-level output current

IOL

Low-level output current

VI

Input voltage

Vo
dtldv

Output voltage
Input transition rise or fall rate

TA

Operating free-air temperature

7-26

UNIT

MIN

... \<~.'8

. . {<';,

9;c:;5>"

V

,d;;:'!"· -8

mA

8

mA

Vee

V

0

Vee
15

ns/V

0

70

Vv'

4.5 V
5.5 V

V

0.45

'\,>'(>~

V

0.45

II

VI = VCC or 0

5.5 V

±1

/LA

ICC
Ci

VI = Vce or 0, 10

5.5 V

200

/LA
pF

Vi = VCC or 0

5V

switching characteristics (see Note)
PARAMETER

SN74ACT8847·30
MIN

MAX

Propagation delay from DAtDBII input register
tpd1

72

ns

70

ns

45

ns

"I\~~

ns

56

ns

to Y output
Propagation delay from input register to

tpd2

output buffer
Propagation delay from pipeline register to

tpd3

output buffer
Propagation from output register to

tpd4
tpd5
td1
td2

output buffer
Propagation delay from SElMStlS to Y output
Propagation delay time, input register to
output register
Delay time, input register to pipeline register or
pipeline register to output register .

..

~\ \C'1 ~"t:. 18
~~V""

,.
UNIT

30

ns

ns

captured in C register is data clocked into the

8

ns

2

ns

sum or product register by that clock
Delay time, ClKC after ClK to insure data
td4.

captured in C register is data clocked into the

.....
~

00
00

Delay. time, ClKC after ClK to insure data
td3

•

sum or product register by. the previous· clock
Note.: Switching data must be used with timing diagrams for different operating modes.

t;
«
~
.....
Z

en

setup and hold times
SN74ACT8847-30
MAX

PARAMETER

MIN

10
10

Instruction before ClK I
Data operand before ClK I
tsu Setup time

Data operand before second ClK I for
double-precision operation (input register

40

,\(":1

not enabled)
SRCC with respect to ClKC
Instruction input after ClK I
Valid Y bus output of the previous ClK
th

Hold time

UNIT

cycle after rising clock edge
Valid status output of the previous ClK
cycle after rising clock edge

I",~;')V '"

~ti,'t~J \'t:'l'l

ns

4

0
5.5

ns

3

clock requirements
SN74ACT8847-30

PARAMETER

MIN
ClK high

tw

Pulse duration

ClK low
CLK low l

Clock period
tClock mode 1 cannot be used.

7-28

10
10
10

MAX

UNIT

ns
ns

switching characteristics (see Note)
PARAMETER

SN74ACT8847-40
MIN

MAX

Propagation delay from DAIDSII input register
tpd1

to Y output
Propagation delay from input register to

tpd2

output buffer
Propagation delay from pipeline register to

tpd3

output buffer

,~;(;~;~~:~"

Propagation from output register to
tpd4
tpd5

output buffer

Propagation delay time. input register to
td1

output register
Delay time. input register to pipeline register or

td2

i,'it

Propagation delay from SElMS/lS to Y output

,,(~;3:)""

'

UNIT

95

ns

90

ns

60

ns

20

ns

20

ns

75

ns

':;r~O

ns

pipeline register to output register
Delay time. ClKC after ClK to insure data

td3

captured in C register is data clocked into the

9

ns

2

ns

sum or product register by that clock
Delay time. ClKC after ClK to insure data
td4

captured in C register is data clocked into the
sum or product register by the previous clock

Note: Switching data must be used with timing diagrams for different operating modes.

7-29

setup and hold times
SN74ACT8847-40

PARAMETER

MIN

Data operand before elK f
Data operand before second ClK f for
double-precision operation (input registe

52

ns

4.5

SRCC with respect to ClKC
Instruction input after elK f
Valid Y bus output of the previous ClK
th

!'~t;>$,j

."'i~,J:,,\)G"{

not enabled)

Hold time

UNIT

12
12

Instruction before elK f

tsu Setup time

MAX

cycle after rising clock edge
Valid status outPUt of the previous ClK
cycle after rising clock edge

0

5.5

ns

4

clock requirements
SN74ACT8847-40

PARAMETER

tw

Pulse duration

MIN
elK high

15

ClK low

,~.?-.l ,C·{ f'tl.';;·

elK lowt
Clock period
tClock mode 1 cannot be used.

7-30

MAX

UNIT

.. H~\t
ns

[1'·',6
ns

switching characteristics (see Note)
PARAMETER

SN74ACT8847-60
MIN

MAX

Propagation delay from DA/DS/I input register
tpdl

to Y output
Propagation delay from input register to

tpd2

output buffer
Propagation delay from pipeline register to

tpd3

output buffer
Propagation from output register to

tpd4
tpd5

output buffer
Propagation delay from SElMS/lS to Y output
Propagation delay time, input register to

tdl

output register
Delay time, input register to pipeline register or

td2

pipeline register to output register

.,:,·F"!

';i,~S:;!'l

UNIT

125

ns

120

ns

'"~i,,

ns



------:---of.

,,2

4

iiEffi
TPl TPO

;,'0 • vee

;,17

It

GNO

1 - - - -..... SELST1

SELMSI[§" ...---r---F------~

SELSTO

FROM
INSTRUCTION·
REGISTER

~~--~------~~~

'V>-------....

••

PYJ·PYO

Y31·YO

m

MSERR

UNORD
A GT B

A EQ B

INEX
OVER
UNDER
.OENORM

OENIN

RNOCO
SRCEX
CHEX

STEXl STEXO
NEG
IN'

Figure 1. •ACT884 7 Floating Point Unit

7-34

=

Input Data Parity Check
When BYTEP is high, internal odd parity is generated for each byte of input data at
the DA and DB ports and compared to the PA and PB parity inputs. If an odd number
of bits is set high in a data byte, the parity bit for that byte is also set high. Parity
bits are input on PA for DA data and PB for DB data. PAO and PBO are the parity bits
for the least significant bytes of DA and DB, respectively. If the parity comparison
fails for any byte, a high appears on the parity error output pin (PERRA for DA data
and PERRB for DB data).
A parity check can also be performed on the entire input data word by setting BYTEP
low. In this mode, PAO is the parity input for DA data and PBO is the parity input for
DB data.

Temporary Input Register
A temporary input register is provided to enable loading of two double- precision
numbers on two 32-bit input buses in one clock cycle. The contents of the DA bus
are loaded into the upper 32 bits of the temporary register; the contents of DB are
loaded into the lower 32 bits.
A clock mode signal (ClKMODE) determines the clock edge on which the data will
be stored in the temporary register. When ClKMODE is low, data is loaded on the
rising edge of the clock. With ClKMODE set high, the temporary register loads on
a falling edge and the RA and RB registers can then be loaded on the next rising edge.

RA and RB Input Registers
Two 64-bit registers, RA and RB, are provided to hold input data for the multiplier
and ALU. Data is taken from the DA bus, DB bus and the temporary input register,
according to configuration mode controls CONFIG1-CONFIGO (see Tables 3 and 5).
The registers are loaded on the rising edge of clock ClK. For single-precision operations,
CONFIG1-CONFIGO should ordinarily be set to 0 1 (see Table 4).

7-35

Table 3. Double Precision Input Data Configuration Modes
lOADING SEQUENCE
DATA LOADED INTO TEMP
DATA LOADED INTO RA/RB
REGISTER ON FIRST CLOCK
REGISTERS ON SECOND
ANDR.A/RB REGISTERS ON
CLOCK
SECOND CLOCKt
CONFIG1

CONFIGO

0

0

0

1

1

0

1

1

DA
B operand
(MSH)
A operand
(LSH)
A operand
(MSH)
A operand
(MSH)

DB
B operand
(LSH)
B operand
(LSH)
B operand
(MSH)
A operand
(LSH)

DA
A operand
(MSH)
A operand
(MSH)
A operand
(LSH)
B operand
(MSH)

DB
A operand
(LSH)
B operand
(MSH)
B operand
(LSH)
B operand
(LSH))

t On the first active clock edge (see CLKMODE, Table 62). data in this column is loaded into the temporary
register. On the next rising edge, operands in the temporary register and the DAIDB buses are loaded into
the RA and RB registers.

Table 4. Single Precision Input Data Configuration Mode
DATA LOADED INTO
RA/RB REGISTERS ON
FIRST CLOCK
CONFIG1

CONFIGO

DA

DB

0

1

A operand

B operand

NOTE
This mode is ordinarily used for singleprecision operations.

Table 5. Double Precision Input Data Register Sources
CONFIG1

CONFIGO

o

0

o
0

7-36

RA SOURCE
MSH
LSH

RB SOURCE
MSH
LSH

DA

DB

TEMP REG
(MSH)

TEMP REG
(LSH)

DA

TEMP REG
(MSH)

DB

TEMP REG
(LSH)

TEMP REG
(LSH)

DB

DA

DB

TEMP REG
(MSH)

DA

TEMP REG
(MSH)

TEMP REG
(LSH)

MultiplierlALU Multiplexers
Four multiplexers select the multiplier and ALU operands from the RA and RB registers,
the previous multiplier or ALU result, or the C register. The multiplexers are controlled
by input signals SELOP7-SELOPO as shown in Tables 6 and 7. For division and square
root operations, operands must be sourced from the input registers, RA and RB.

Table 6. M41tiplier Input Selection
A1 (MUX1) INPUT

131 (MUX2) INPUT

SELOP7

SElOP6

OPERAND SOURCEt

SElOP5

SElOP4

OPERAND SOURCEt

0
0
1
1

0
1
0
1

Reserved
C register
ALU feedback
RA input register

0
0
1
1

0
1
0
1

Reserved
C register
Multiplier feedback
RB input register

t For division or square root operations, only RA and RS registers can be selected as sources.

Table 7. ALU Input Selection
A2 (MUX3) INPUT

132 (MUX4) INPUT

SELOP3

SElOP2

OPERAND SOURCEt

SELOP1

SElOPO

OPERAND SOURCEt

0
0
1

0
1
0
1

Reserved
C register
Multiplier feedback
RA .input register

0
0
1
1

0
1
0
1

Reserved
C register
AlU feedback
RB input register

1

t For division or square root operations, only RA and RB registers can be selected as sources.

Pipelined ALU
The pipelined ALU contains a circuit for floating point addition and/or subtraction of
aligned operands, a pipeline register, an exponent adjuster and a normalizer/rounder.
An exception circuit is provided to detect denormal inputs; these can be flushed to
zero if the fast input is set high. If the FAST input is low, the ALU accepts a denormal
as input. A denorm exception flag (DENORM) goes high when the ALU output is a
denormaL
Integer processing in the ALU includes both arithmetic and logical operations on either
two's complement numbers or unsigned integers. The ALU performs addition,
subtraction, comparison, logical shifts, logical AND, logical OR, and logical XOR.
The ALU may be operated independently or in parallel with the multiplieL Possible ALU
functions during independent operation are given in Tables 8 through 11. Parallel
ALU/multiplier functions are listed in Table 16.

7-37

Lv88.L0\1vLNS
Table 8. Independent ALU Operations, Single Floating·Point Operand
(110 = 0,19 = 0,17 = 0, 16 =0)

'-I

W

(Xl

CHAINED

OPERAND

PRECISION

PRECIS ON

OUTPUT

OPERAND

ABSOLUTE

OPERATION

FORMAT

RA

RB

SOURCE

TYPE

VALUE A

110

o=

Not
Chained

19
0=
Floating
point

17

18

o=
1

=

A(SP)
A(DP)

o=

16

B(SP)

15

0= ALU
result

1

=

Single
Operand

ALU OPERATION

14

13-10

RESULT

O=A
1 = IAI

0000
0001
0010

Pass A operand
Pass - A operand
2's complement integer
to floating point
conversion t
Floating point to 2's
complement integer
conversion
Move A operand (pass
without NaN detect or
status flags active)
Pass B operand
Floating point to floating
point conversion l
Floating point to
unsigned integer
conversion
Wrap (denormal) input
operand
Unsigned integer to
floating point conversion
Unwrap exact number
Unwrap inexact number
Unwrap rounded input

0011

0100

0101
0110
0111

1000
1010
1100
1101
1110
-

---------------_ ... -

..

-

tThe precision of the integer to floating point conversion is set by 18.
'This converts single-precision floating point to double-precision floating point and vice versa. If the 18 pin is low to indicate a single-precision input. the result
of the conversion will be double precision. If the 18 pin is high, indicating a double-precision input, the result of the conversion will be single preCision.

Table 9. Independent AlU Operations. Two Floating-Point Operands
(110 = O. 19 = O. 15 = 0)
CHAINED
OPERATION

OPERAND PRECISION PRECISION OUTPUT OPERAND ABSOLUTE ABSOLUTE ABSOLUTE

110

19

= Not
chained

0=
Floating
point

o

RA

FORMAT

18

o

RB

SOURCE

17

16

B(SP) 0= ALU
0
1 = B(DP)
result.

= A(SP)
1 = A(DP)

TYPE

VALUE A

VALUE B

VALUE Y

ALU OPERATION

15

14

13

12

11-10

RESULT

0= Two
operands

0= A
1 = iAI

0= B
1 = IBI

0= V
1 = IVI

00
01
10
11

A+B
A - B
Compare A, B
B - A

Table 10. Independent AlU Operations. Single Integer Operand
(110 = 0, 19 = 1, 16 = 0)
CHAINED

OPERAND FORMAT/PRECISION

OPERATION
110

19

18

= Not
Chained

1 =
Integer

0

o

0

OUTPUT

OPERAND

SOURCE

TYPE

17

o

= SP 2's
complement
1 = SP
unsigned
integer

16

o

= ALU
result

ALU OPERATION

15

14-10

1 = Single
Operands

00000
00001
00010
00101
01000
01001
01101

RESULT
Pass A
Pass Negate
Pass B
Shift A
Shift A
Shift A

operand
A operand
A operand (1' s complement)
operand
operand left logical t
operand right logical t
operand right arithmetic t

t B operand is number of bit positions A is to be shifted (See instruction description for "Independent ALU Operations".)

"
iN

<.0

SN74ACT8847

Lv88.L:lVvLNS
-.J

~

Table 11. Independent ALU Operations, Two Integer Operands
(110 = 0,19 = 1, 16 = 0)

o

CHAINED

OPERAND FORMAT/PRECISION

OPERATION
110

19

18

= Not
Chained

1 =
Integer

0

o

---

.

- - - - - _.. _-

OPERAND
TYPE

ALU OPERATION

17

16

15

14-10

SP 2's
complement
1 = SP
unsigned
integer

0= ALU
result

0= Two
Operands

00000
00001
00010
00011
01000
01001
01010
01100
01101

o

0

OUTPUT
SOURCE

=

.

----~

--- '-------

-- -----

RESULT
A+B
A-B
Compare A, B
B -A
Logical AND (A, B)
Logical AND (A, NOT B)
Logical AND (NOT A, B)
Logical OR (A, B)
Logical XOR (A, B)

Table 12. Independent Multiplier Operations
ABSOLUTE
CHAINED

OPERAND FORMAT/PRECISION

OUTPUT MULTIPLY/ ABSOLUTE

VALUE B/

NEGATE

SOURCE

DIVIDE

VALUE A

DIV/SQRT

RESULT

WRAP A

17

16

15

14t

13 t

12t

11

= B(SP)
1 = B(DP)

1 =
Multiplier
result

0=
multiply

0= A
1 = IAI

0= B
1 = IBI

0= Y
1 = -y

OPERATION
110

o

= Not
chained

I

19

0=
floating
point
1 =
integer

18

o=

A(SP)
1 = A(DP)

0
0

o

o=

SP 2's
complement
1 = SP
unsigned
integer

1 =
Div/SORT

o
1

= A

= IAI

0= Div
1 = SORT

- - ~--- ... -.--- -

o

= Normal
format
1 = A is a
wrapped
number

WRAPB
10

o

= Normal
format
1 = B is a
wrapped
number

-----

tSee also Tables 13 a.nd 14. Operations involving absolute values or negated results are valid only when floating·point format is selected 119

0).

Pipelined Multiplier
The pipe lined multiplier performs a basic multiply function, division and square root.
The operands can be single-precision or double-precision numbers and can be converted
to absolute values before multiplication takes place. Independent multiplier operations
are summarized in Tables 12 through 15.
An exception circuit is provided to detect denormalized inputs; these are indicated
by a high on the DENIN signal. Denormalized inputs must be wrapped by the ALU before
multiplication, division, or square root. If results are wrapped (signaled by a high on
the DENORM status pin), they must be unwrapped by the ALU.
The multiplier and ALU can be operated simultaneously by setting the 110 instruction
input high. Possible operations in this chained mode are listed in Table 16. Division
and square root are performed as independent multiplier operations, even though both
multiplier and ALU are active during divide and SQRT operations.
Table 13. Independent Multiply Operations Selected by 14-12 (110 .. 0,16 .. 1,15 .. 0)
ABSOLUTE

ABSOLUTE

NEGATE

VALUE A

VALUE B

RESULT

14

13

0= A
1 = IAI

0= B
1 '" IBI

12

o=
1

=

Y
-y

OPERATION SELECTED

14-12

RESULTSt

000
001
010
011
100
101
110
111

A*B
-(A * B)
A * IBI
-(A * IBI)
IAI * B
- !lAI * B),
IAI * IBI
-(IAI * IBI)

Table 14. Independent Divide/Square Root Operations
Selected by 14-12 1110 .. 0, 16 .. 1, 15 .. 1)
ABSOLUTE

DIVIDEI

NEGATE

VALUE A

SQRT

RESULT

14

o=

13
A

l=A

o=

Divide

1 = SORT

.'

OPERA TlON SELECTED

12

14-12

RESULTSt

0=
Y
1 = -y

000

AlB
-(A I B)

001
010

SORT A

011

-(SORT A)

100

IAII B
-(IAI / B)

101
110

SORT IAI

111

-(SORT IAI)

t Operations involving absolute values or negated results are valid only when floating, point format is selected
(19

~

0),

7-41

Table 15. Formats Selected by 18-17 (110 - 0, 19 -0, 16 -1)
PRECISION
SELECT RA
18

PRECISION
RAINPUT

0

Single

0

Single
(Converted
to Double)

1
1

PRECISION
SELECT RB
17
0

PRECISION
RBINPUT

PRECISION
OF RESULT

$ingle

Single

1

Double

Double

Double

0

Single
(Converted
to Double)

Double

Double

1

Double

Double

Product, Sum, and C Registers
The results of the AlU and multiplier operations may optionally be latched into two
output registers on the rising edge of the system clock (ClK). The P (product) register
holds the result of the multiplier operation; the S (sum) register holds the AlU result.
An additional 64-bit register is provided for temporary storage of the result of an AlU
or multiplier opration l?efore feedback to the multiplier or AlU. The data source for
this C register is selected by SRCC; a high on this pin selects the multiplier result;
a low selects the AlU. A separate clock, ClKC, has been provided for this register.

Parity Generators
Odd parity is generated for the Y multiplexer output, either for each byte or for each
word of output, depending on the setting of BYTEP. When BYTEP is high, the parity
generator computes four parity bits, one for each byte of Y multiplexer output. Parity
. bits are output on the PY3-PYO pins; PYO represents parity for the least significant
. byte. A single parity bit can also be generated for the entire output data word by setting
BYTEP low. In this mode, PYO is the parity output.

Master/Slave Comparator

:s
C/)

,f:I.

A master/slave comparator is provided to compare data bytes from the Y. output
multiplexer and the status outputs with data bytes on the external Yand status ports
when OEY, OES and OEC are high. If the data bytes are not equal, a high signal is
generated on the master/slave error output pin (MSERR).

l>
(') Status and Exception Generation
-oJ

OJ A status and exception generator produces several output signals to indicate invalid

~ operations as well as overflow, underflow, nonnumerical and inexact results, in
"'-J

conformance with IEEE Standard 754-1985. If output registers are enabled
(PIPES2 = 0), status and exception results are latched in a status regis~er on the rising
edge of the clock. Status results are valid at the same time that associated data results

Table 16. Chained Multiplier/AlU Operations (110 = 1)

CHAINED

OPERAND FORMAT/PRECISION

OPERATION

110

19

1 =
Chained

0=
floating
point
1 =
integer

A(SP)
1 = A(DP)

0
0

,-

-

-

------------

NEGATE

ADD

MULTIPLY

ALU

MULTIPLIER
RESULT

SOURCE

ZERO

BY ONE

RESULT

16

15

14

13 t

12t

11-10

RESULT

B(SP)
1 = B(DP)

0=
ALU
result

o=

0=
Normal
operation
1 =
Negate
multiplier
result

A+B
A-B
2 - A
B - A

1 =
Multiplier
result

0=
Normal
operation
1 =
Negate
ALU
result

00
01
10
11

o = SP 2's
complement
1 = SP
unsigned
integer

0=
Normal
operation
1 =
Forces
B2 input
of ALU
to zero

o=

Normal
operation
1 =
Forces
B1 input
of multiplier to
one

t Operations involving negated results are valid only when floating-point format is selected (19

-.J

~

tv

SN74ACT8847

ALU
OPERATIONS

17

18

o=

NEGATE
OUTPUT

0).

are valid. Status outputs are enabled by two signals, OEC for comparison status and
OES for other status and exception outputs. Status outputs are summarized in
Tables 17 and 18.

Table 17. Comparison Status Outputs
SIGNAL

RESULT OF COMPARISON (ACTIVE HIGH)

AEOB

The A and B operands are equal. (A high signal on the AEOB output indicates a
zero result from the selected source except during a compare operation in the ALU.
During integer operations, Indicates zero status output.)

AGTB
UNORD

The A operand is greater than the B operand.
The two inputs of a comparison operation are unordered, i.e., one or both of the
inputs is a NaN.

Table 18. Status Outputs
SIGNAL

STATUS RESULT

CHEX

If 16 is low, indicates the multiplier is the source of an exception during a chained
function. If 16 is high, indicates the ALU is the source of an exception during a
chained function.

DENIN

Input to the multiplier is a denorm. When DENIN goes high, the STEX pins indicate
which port had the denormal input.

DENORM

The multiplier output is a wrapped number or the ALU output is a denorm. In the
FAST mode, this condition causes the result to go to zero.

DIVBYO

An invalid operation involving a zero divisor has been detected by the multiplier.

ED

Exception detect status signal representing logical OR of all enabled exceptions
in the exception disable register.
The result of an operation is not exact.

INEX
INF
IVAL

NEG

The output is the IEEE representation of infinity.
A NaN has been input to the multiplier or the ALU, or an invalid operation
(0 • 00 or ± 00 ± 00) has been requested. This signal also goes high if an operation
involves the square root of a negative number. When IVAL goes high, the STEX
pins indicate which port had the NaN.
Output value has negative sign

OVER

The result is greater than the largest allowable value for the specified format.

RNDCO

The mantissa of a wrapped number has been increased in magnitude by rounding
and the unwrap round instruction must be used to properly unwrap the wrapped
number (see Table 8).

SRCEX

The status was generated by the multiplier. (When SRCEX is low, the status was
generated by the ALU.)
A NaN or a denorm has been input on the B port.
A NaN or a denorm has been input on the A port.
The result is inexact and less than the minimum allowable value for the specified
format. In the FAST mode, this condition causes the result to go to zero.

STEXO
STEX1
UNDER

7-44

An exception mask register is available to mask selected exceptions from the multiplier,
ALU, or both. Multiply status is disabled during an independent ALU instruction, and
ALU status is disabled during multiplier instructions. During chained operation both
status outputs are enabled.
When the exception mask register has been loaded with a mask, the mpsk is applied
to the contents of the status register to disable unnecessary exceptions. Status results
for enabled exceptions are then ORed together and, if true, the exception detect (ED)
status output pin is set high. Individual status outputs remain active and can be read
independently from mask register operations.
During a compare operation in the ALU, the AEQB output goes high when the A and
B operands are equal. When any operation other than a compare is performed, either
by the ALU or the multiplier, the AEQB signal is used as a zero detect.
In chained mode, results to be output are selected based on the state of the 16 (source
output) pin (if 16 is low, ALU status will be selected; if 16 is high, multiplier status
will be selected). If the. nonselected output source generates an exception, CHEX is
set high. Status of the nongelected output source can be forced using the SELST pins,
as shown in Table 19.

Table 19. Status Output Selection (Chained Model
SELST1STATUS SELECTED

SELSTO

00
01
10
11

Logical
Selects
Selects
Normal

OR of ALU and multiplier exceptions (bit by bit)
multiplier status
ALU status
operation (selection based on result source specified by 16 input)

Flowthrough Mode
To enable the device to operate in pipelined or flowthrough mode.s, registers can be
bypassed using pipeline control signi'Jls PIPES2-PIPESO (see Table 20).

Table 20. Pipeline Controls (PIPES2-PIPESOI
PIPES2PIPESO
X X 0
X X 1
X
X
X 1 X
X X
1 X X

o

o

REGISTER OPERATION SELECTED
Enables input registers (RA, RB)
Disables input registers (RA, Ra)
Enables pipeline registers
Disables pipeline registers
Enables output registers (P, S, Status)
Disables. output registers (p, S, Status)

7-45

FAST and IEEE Modes
The device can be programmed to operate in FAST mode by asserting the FAST pin.
In the FAST mode, all denormalized inputs and outputs are forced to zero.
Placing a zero on the FAST pin causes the chip to operate in IEEE mode. In this mode,
the ALU can operate on denormalized inputs and return denormals. If a denorm is input
to the multiplier, the DENIN flag will be asserted, and the result will be invalid. Denormal
numbers must be wrapped before being input to the multiplier. If the multiplier result
underflows, a wrapped number will be output.

Rounding Modes
The' ACT884 7 supports the four IEEE standard rounding modes: round to nearest,
round towards zero (truncate), round towards infinity (round up), and round towards
minus infinity (round down). The rounding function is selected by control pins RNDl
and RNDO, as shown in Table 21.
Table 21. Rounding Modes
RND1·
ROUNDING MODE SEI..ECTED

RNDO

0 0
0 1
1 0
1 1

Round
Round
Round
Round

towards
towards
towards
towards

nearest
zero (truncate)
infinity (round up)
negative infinity (round down)

Test Pins
Two pins, TP1·TPO, support system testing. These may be used, for example, to place
all outputs in a high·impedance state, isolating the chip from the rest of the system
(see Table 22).
Table 22. Test Pin Control Inputs
TP1·

OPERATION

TPO

0 0
0 1
1 0
1 1

All outputs and I/Os are forced low
All outputs and I/Os are forced high
All outputs are placed in a high impedance state
Normal operation

Summary of Control Inputs
Control input signals for the 'ACT8847 are summarized in Table 23.

7·46

Table 23. Control Inputs
SIGNAL
BYTEP
CLK
CLKC
CLKMODE
CONFIG1CONFIGO
ENC_._B

HIGH
Selects byte parity generation and test
Clocks all registers (except C) on rising
edge
Clocks C register on rising edge
Enables temporary input register load on
falling clock edge
See Table 3 (RA and RB register data
source selects)
No effect

ENRA

If register is not in flow through, enables
clocking of RA register

ENRB

If register is not in flow through, enables
enables clocking of RB register
Places device in FAST mode
Causes output value to bypass C
register and appear on C register output
bus.
No effect

FAST
FLOW~C

HALT

OEC
OES
OEY
PIPES2PIPESO
RESET

Disables compare pins
Disables status outputs
Disables Y bus
See Table 20 (Pipeline Mode Control)

RND1RNDO
SELOP7SELOPO

See Table 21 (Rounding Mode Control)

SELMS/LS

SELST1SELSTO
SRCC
TP1-TPO

No effect

See Tables 6 and 7 (Multiplier/ALU
operand
selection)
Selects MSH of 64-bit result for output
output on the Y bus (no effect on singleprecision operands)
See Table 19 (Status Output Selection)
Selects multiplier result for input to C
register
See Table 22 (Test Pin Control Inputs)

lOW
Selects single bit parity
generation and test
No effect
No effect
Enables temporary· input· register
load on rising clock edge
See Table 42 (RA and RB
register data source selects)
Enables C register load when
CLKC goes high.
If register is not in flow through,
through, holds contents of RA
register
If rflgister is not in flow through,
holds contents of RB register
Places device in IEEE mode
No effect

Stalls device operation but
does not affect registers, internal
states, or status
Enables compare pins
Enables status outputs
Enables Y bus
See Table 20 (Pipeline Mode
Control)
Clears internal states, status,
internal pipeline registers, and
exception disable register. Does
not affect other data registers.
See Table 21 (Rounding Mode
Control)
See Tables 6 and 7
(Multiplier/ALU operand selection
Selects LSH of 64-bit result for
output on the Y bus (no effect on
single-precision operands)
See Table 19 (Status Output
Selection)
Selects ALU result for input to C
register
See Table 22 (Test Pin Control
Inputs)

7-47

Instruction Set
Configuration and operation of the' ACT884 7 can be selected to perform single or
double-precision floating-point and integer calculations in operating modes ranging from
flowthrough to fully pipe lined. Timing and sequences of operations are affected by
settings of clock mode, data and status registers, input data configurations, and
rounding mode, as well as the instruction inputs controlling the ALU and the multiplier.
The ALU and the multiplier of the 'ACT884 7 can operate either independently or
simultaneously, depending on the setting of instruction inputs 110-10 and related
controls.
Controls for data flow and status results are discussed separately, prior to the
discussions of ALU and multiplier operations. Then, in Tables 27 through 35, the
instruction inputs to the ALU and the multiplier are summarized according to operating
mode, whether independent or chained (ALU and multiplier in simultaneous operation).

loading External Data Operands
Patterns of data input to the' ACT884 7 vary depending on the precision of the operands
and whether they are being input as A or B operands. Loading of external data operands
is controlled by the settings of CLKMODE and CON FIG 1-CONFIGO, which determine
the clock timing for loading and the registers that are used.

Configuration Controls (CON FIG 1-CONFIGO)
Three input registers are provided to handle input of data operands, either single
precision or double precision. The RA, RB, and temporary registers are each 64 bits
wide. The temporary register is (ordinarily) used only during input of double-precision
operands.
When single-precision or integer operands are loaded, the ordinary setting of CONFIG 1CONFIGO is LH, as shown in Table 4. This setting loads each 32-bit operand in the
most significant half (MSH) of its respective register. The operands are loaded into
the MSHs and adjusted to double precision because the data paths internal to the device
are all double precision. It is also possible to load single-precision operands with
CONFIG 1-CONFIGO set to HH but two clock edges are required to load both the A
and B operands on the DA bus.

en
~
~

:t>
("')
-I
CO
CO
~

-..J

Double-precision operands are loaded by using the temporary register to store half
of the operands prior to inputting the other half of the operands on the DA and DB
buses. As shown in Tables 3 and 5, four configuration modes for selecting input sources
are available for loading data operands into the RA and RB registers.

ClKMODE Settings
Timing of double-precision data inputs is determined by the clock mode setting, which
allows the temporary register to be loaded on either the rising edge (CLKMODE = L)
or the falling edge of the clock (CLKMODE = H). Since the temporary register is not
used when single-precision operands are input, clock modes 0 and 1 are functionally
equivalent for single-precision operations.
7-48

The setting of CLKMODE can be used to speed up the loading of double-precision
operands. When the CLKMODE input is set high, data on the DA and DB buses are
loaded on the falling edge of the clock into the MSH and LSH, respectively, of the
temporary register. On the next rising edge, contents of the DA bus, DB bus, and
temporary register are loaded into the RA and RB registers, and execution of the current
instruction begins. The setting of CON FIG 1-CONFIGO determines the exact pattern
in which operands are loaded, whether as MSH or LSH in RA or RB.
Double-precision operation in clock mode 0 is similar except that the temporary register
loads only on a rising edge. For this reason the RA and RB registers do not load until
the next rising edge, when all operands are available and execution can begin.
A considerable advantage in speed can be realized by performing double-precision ALU
operations with CLKMODE set high. In this clock mode both double-precision operands
can be loaded on successive clock edges, one falling and one rising and the ALU
operation can be executed in the time from one rising edge of the clock to the next
rising edge. Both halves of a double-precision ALU result must be read out on the Y
bus within one clock cycle whIm the' ACT884 7 is operated in clock mode 1.

Internal Register Operations
Six data registers in the 'ACT8847 are arranged in three levels.albngthe data paths
through the multiplier and the ALU. Each level of registers can be enabled or disabled
independently of the other two levels by setting the appropriate PIPES2-PIPESO inputs.
The RA and RB registers receive data inputs from the temporary register and the DA
and DB buses. Data operands are then multiplexed into the multiplier, ALU, or poth.
To support simultaneous pipelined operations, the data paths through the multiplier
and the ALU are both provided with pipeline registers and output registers. The control
settings for the pipeline and output registers (PIPES2-PIPES 1 ) are registered with the
instruction inputs 110-10.
A seventh register, the constant (C) register is available for storing a 64-bit constant
or an intermediate result from the multiplier or the ALU. The C register has a separate
clock input (CLKC), input source select (SRCC) and write enable ENRC (active low).
The SRCC input is not registered with the instruction inputs. Depending on the operation
selected and the settings of PIPES2-PIPESO, an offset of one or more cycles may be
necessary to load the desired result into the C register. When the flowthrough control
FLOWC is high, the output value bypasses the C register without affecting C register
CQntents. Timing for FLOWC feedback is similar to P or S register feedback, which
is not affected by FLOWC feedback.
Status results are also registered whenever the output registers are enabled. Duration
and availability of status results are affected by the same timing constraints that apply
to data results on the Y output bus.

7-49

"

qex)
ex)

~

(.)
~

q-

"
Z

CJ)

Data Register Controls (PIPES2-PIPESO)
Table 20 shows the settings of the registers controlled by PIPES2-PIPESO. Operating
modes range from fully pipe lined (PIPES2-PIPESO = 000) to flowthrough
(PIPES2-PIPESO = 111).
In flowthrough mode all three levels of registers are disabled, a circumstance which
may affect some double-precision operations. Since double-precision operands require
two steps to input, at least half of the data must be clocked into the temporary register
before the remaining data is placed on the DA and DB buses.
When all registers (except the C register) are enabled, timing constraints can become
critical for many double-precision operations. In clock mode 1, the ALU can perform
a double-precision operation and output a result during every clock cycle, and both
halves of the result must be read out before the end of the next cycle. Status outputs
are valid only for the period during which the Y output data is valid.
Similarly, double-precision multiplication is affected by pipelining, clock mode, and
sequence of operations. A double-precise multiply may require two cycles to execute
and two cycles to output the result, depending on the settings of PIPES2-PIPESO.
Duration of valid outputs at the Y multiplexer depends on settings of PIPES2-PIPESO
and CLKMODE, as well as whether all operations and operands are of the same type.
For example, when a double-precision multiply is followed by a single-precision
operation, one open clock cycle must intervene between the dissimilar operations.

C Register Controls (SRCC, CLKC, FLOWC, ENRC)
The C register loads from the P or the S register output, depending on the setting of
SRCC, the load source select. SRCC = H selects the multiplier as input source.
Otherwise the ALU is selected when SRCC = L. In either case the C register only loads
the selected input on a rising edge of the CLKC signal when ENRC is low.
The C register does not load directly from an external data bus. One method for loading
a constant without wasting a cycle is to input the value as an A operand during an
operation which uses only the ALU or multiplier and requires no external data inputs.
Since the B operand can be forced to zero in the ALU or to one in the multiplier, the
A operand can be passed to the C register either by adding zero or multiplying by one,
~ then selecting the input source with SRCC and causing the CLKC signal to go .high.
-..J Otherwise, the C register can be loaded through the'ALU with the Pass A Operand
~ instruction, which requires a separate cycle.

l>

(')
~
(X)
(X)

Separate controls are available to enable the C register (ENRC) or to bypass the C
register when feeding an operand back on the C register output bus (FLOWC).

~

-..J

7-50

Operand Selection (SELOP7-SELOPO)
As shown in Tables 6 and 7, data operands can be selected five possible sources,
including external inputs from the RA and RB registers, feedback from the P andS
registers, and a stored value in the C register. Contents of the C register may be selected
as either the A or the B operand in the ALU, the multiplier, or both. When an external
input is selected, the RA input always becomes the A operand, and the RB input is
the B operand.
Feedback from the ALU can be selected as the A operand to the multiplier or as the
B operand to the ALU. Similarly, multiplier feedback may be used as the A operand
to the ALU or the B operand to the multiplier. During division or square root operations,
operands may not be selected except from the RA and RB input registers
(SELOPS7-SELOPSO = 11111111).
Selection of operands also interacts with the selected operations in the ALU or the
multiplier. ALU operations with one operand are performed only on the A operand.
Also, depending on the instruction selected, the B operand may optionally be forced
to zero in the ALU or to one in the multiplier.

Rounding Controls (RND1-RNDO)
Because floating point operations may involve both inherent and procedural errors,
it is important to select appropriate modes for handling rounding errors. To support
the IEEE standard for binary floating-point arithmetic, the' ACT884 7 provides four
rounding modes selected by RND1-RNDO.
Table 21 shows the four selectable rounding modes. The usual default rounding mode
is round to nearest (RND1-RNDO = Ll). In round-to-nearest mode, the 'ACT8847
supports the IEEE standard by rounding to even (LSB = 0) when two nearest
representable values are equally near. Directed rounding toward zero, infinity, or minus
infinity are also available.
Rounding mode should be selected to minimize procedural errors which may otherwise
accumulate and affect the accuracy of results. Rounding to nearest introduces a
procedural error not exceeding half of the least significant bit for each rounding
operation. Since rounding to nearest may involve rounding either upward or downward
in successive steps, rounding errors tend to cancel each other.

f'

~
ex)
ex)

In contrast, directed rounding modes may introduce errors approaching one bit for
each rounding operation. Since successive rounding operations in a procedure may
all be similarly directed, each introducing up to a one-bit error, rounding errors may
accumulate rapidly, especially in single-precision operations.

U
~

Status Exceptions

Z

~

f'

Status flags are provided to signal both floating point and integer exceptions. Integer
status is provided using AEQB for zero (Z), NEG for sign, and OVER for
overflow/carryout.

7-51

en

Status exceptions can result from one or more error conditions such as overflow,
underflow, operands in illegal formats, invalid operations, or rounding. Exceptions may
be' grouped into two classes: input exceptions resulting from invalid operations or
denormal inputs to the multiplier, and output exceptions resulting from illegal formats,
rounding errors, or both.
To simplify the discussion of exception handling, it is useful to summarize the data
formats for representing IEEE floating-point numbers which can be input to or output
from the FPU (see Table 24). Since procedures for handling exceptions vary according
to the requirements of specific applications, this discussion focuses on the conditions
which cause particular status exceptions to be signalled by the FPU.
IEEE formats for floating-point operands, both single and double precision, consist of
three fields: sign, exponent, and fraction, in that order. The leftmost (most significant)
bit is the sign bit. The exponent field is eight bits long in single-precision operands
and 11 bits long in double-precision operands. The fraction field is 23 bits in single
precision and 52 bits in double precision. Further details of IEEE formats and exceptions
are provided in the IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE
Std 754-1985.
Several status exceptions are generated by illegal data or instruction inputs to the FPU.
Input exceptions may cause the following signals to be set high: IVAL, DIVBYO, DENIN,
and STEX 1-STEXO. If the IVAL flag is set, either an invalid operation, such as the square
root of - Ix I, has been requested or a NaN (Not a Number) has been input. When
DENIN is set, a denormalized number has been input to the multiplier. DIVBYO is set
when the divisor is zero. STEX 1-STEXO indicate which port (RA, RB, or both) is the
source of the exception when either a denormal is input to the multiplier (DEN IN = H)
or a NaN (lVAL = H) is input to the multiplier or the ALU.
NaN inputs are all treated as IEEE signaling NaNs, causing the IVAL flag to be set.
When output from the FPU, the fraction field from a NaN is set high (all 1 's), regardless
of the original fraction field of the input NaN.

~

Output exception signals are provided to indicate both the source and type of the
exception. DE NORM, INEX, INF, NEG, OVER, UNDER, and RNDCO indicate the
exception type, and CHEX and SRCEX indicate the source of an exception. SRCEX
indicates the source of a result as selected by instruction bit 16, and SRCEX is active
whenever a result is output, not only when an exception is being signaled. The chainedmode exception signal CHEX indicates that an exception has be generated by the source
not selected for output by 16. The exception type signaled by CHEX cannot be read
unless status select controls SELST1-SELSTO are used to force status output from
the deselected source.

00
00

Output exceptions may be due either to a result in an illegal format or to a procedural

C/)

~
~

l>

~ error. Results too large or too small to be represented in the selected precision are
signalled by OVER and UNDER. When INF is high, the output is the IEEE representation
of infinity. Any ALU output which has been increased in magnitude by rounding causes
INEX to be set high. DE NORM is set when the multiplier output is wrapped or the ALU
7-52

Table 24. IEEE Floating Point Representations

TYPE OF
OPERAND

t

EXPONENT (e)

SPIHEX) DP IHEX)

FRACTION Ifl HIDDEN
(BINARY)
BIT

VALUE OF NUMBER REPRESENTED
SP IDECIMAL) t
DP (DECIMAL) t

Normalized
Nutnber(max)

FE

7FE

All 1'5

1

(-1)5 (2127) (2-2-23)

(-1)5 (2 1023 ) (2-2- 52 )

Normalized
Number (min)

01

001

All 0'5

1

(-1)5 (2- 126 ) (1)

(_1)5 (2- 1022) (1)

Denormalized
Number (max)

00

000

All 1'5

0

(1 _)5 (2 - 126) (1 - 2 - 23)

( - 1)5 (2 - 1022) (1 - 2 - 52)

Denormalized
Number (min)

00

000

000 ... 001

0

( - 1)5 (2 - 126) (2 - 23)

(-1)5 (2-1022) (2-52)

Wrapped
Number (max)

00

000

All 1'5

1

(-1)5 (2- 127 ) (2-2- 23)

( - l)S (2 - 1023) (2 - 2 - 52)

Wrapped
Number (min)

EA

7CD

All O's

1

{-1)S (2-(22+127» (1)

(-1)5 (2-(51 +1023)) (1)

Zero

00

000

Zero

0

(-1)5 (0.0)

(-1)5 (0.0)

Infinity

FF

7FF

Zero

1

( - 1)5 (infinity)

( - 1)5 (infinity)

NAN (Not a
Number)

FF

7FF

Nonzero

N/A

None

None

= sign bit.

-...j

0,
CAl

SN74ACT8847

output is denormalized. Wrapped outputs from the multiplier may be inexact or
increased in magnitude by roun'ding, which may cause the INEX and RNDCO status
signals to be set high. A denormal output from the ALU (DENORM = H) may also cause
INEX to be set, in which case UNDER is also signalled.

Handling of Denormalized Numbers (FAST)
The FAST inputselects the mode for handling denormalized inputs and ,outputs. When
the FAST input is set low, the ALU accepts denormalized inputs but the multiplier
generates an exception when a denormal is input. When FAST is set high. the DENIN
status exception is disabled and all denormalized numbers, both inputs and results,
are forced to zero.
A denormalized input has the form of a floating-point number with a zero exponent,
a nonzero mantissa, and a zero in the leftmost bit of the mantissa (hidden or implicit
bit). A denormalized number results from decrementing the biased exponent field to
zero before normalization is complete. Since a denormalized number cannot be input
to the multiplier, it must first be converted to a wrapped number by the ALU. When
the mantissa of the denormal is normalized by shifting it left, the exponent field
decrements from all zeros (wraps past zero) to a negative two's complement number
(except in the case of .1 XXX ... , where the exponent is not decremented.
Exponent underflow is possible during multiplication of small operands even when the
operands are not wrapped numbers. Setting FAST = L selects gradual underflow so
that denormal inputs can be wrapped and wrapped results are not automatically
discarded. When FAST is set high, denormal inputs and wrapped results are forced
to zero immediately.
When the multiplier is in IEEE mode and produces a wrapped number as its result.
the result may be passed to the ALU and unwrapped~ If the wrapped number can be
unwrapped to an exact denormal, it can be output without causing the underflow status
flag (UNDER) to be set. UNDER goes high when a result is an inexact denormal,and
a zero is output from the FPU if the wrapped result is too small to represent as a
denormal (smaller than the minimum denorm). Table 25 describes the handling of
wrapped multiplier results and the status flags that are set when wrapped numbers
are output from the multiplier.
Table 25. Handling Wrapped Multiplier Outputs
TYPE

STATUS FLAGS SET

NOTES

DENORM

INEX

RNOCO

UNDER

Wrapped,
exact

1

0

0

0

Unwrap with 'Wrapped
exact' ALU instruction

Wrapped,
inexact

1

1

0

1

Unwrap with 'Wrapped
inexact' ALU instruction·

Wrapped,
increased in
magnitude

1

1

1

1

Unwrap with 'Wrapped
rounded' ALU instruction

OF RESULT

When operating in chained mode, the multiplier may output a wrapped result to the
ALU during the same clock cycle that the multiplier status is output. In such a case
the ALU cannot unwrap the operand prior to using it, for example, when accumulating
the results of previous multiplications. To avoid this situation, the FPU can be operated
in FAST mode to simplify exception handling during chained operations. Otherwise,
wrapped outputs from the multiplier may adv.ersely affect the accuracy of the chained
operation, because a wrapped number may appear to be a large normalized number
instead of a very small denormalized number.
Because of the latency associated with interpreting the FPU status outputs and
determining how to process the wrapped output, it is necessary that a wrapped operand
be stored external to the FPU (for example, in an external register file) and reloaded
to the A port of the ALU for unwrapping and further processing.

Exception Disable Mask Register
The exception disable mask register can be loaded with a mask to enable or disable
selected status exceptions. Status bits for enabled exceptions are logically ORed, and
when the result is true, the ED pin goes high. During chained operations both multiplier
and ALU results are ORed. During independent operation the nonselected status results
are forced to zero.
If the FPU is reset (RESET = 0), the exception disable mask register is cleared. Table 26
describes the settings for the mask register load instruction and the status exceptions
which can be enabled or disabled with the mask.
Table 26. loading the Exception Disable Mask Register
INSTRUCTION

RESULTS

INPUTS
110-17=0111
16
15 t
14
13
12
11
10

Exception mask load instruction
Load ALU exception disable register
1 = Load multiplier exception disable register
a = IV AL exception enabled
1 = IV AL exception disabled
o = OVER exception enabled
1 = OVER exception dis'abled
o = UNDER exception enabled
1 = UNDER exception disabled
o = INEX exception enabled
1 = INEXexception disabled
o = DIVBYO exception enabled
1 = DIVBYO exception disabled t
a = DENORM exception enabled
1 = DENORM exception disabled

o=

t Disabling IV AL in multiplier exception mask register also disables DENIN exception
+Only significant when 16 = 1

7-55

Data Output Controls (SELMS/LS, OEY)
Selection and duration of results from the Y output multiplexer may be affected by
several factors, including the operation selected, precision of the operands, registers
enabled, and the next operation to be performed. The data output controls are not
registered with the data and instruction inputs. When the device is microprogrammed,
the. effects of pipelining and sequencing of operations should be taken into account.
Two particular conditions need to be considered. Depending on which registers are
enabled, an offset of one or more cycles must be allowed before a valid result is available
at the Y output multiplexer. Also, certain sequences of operations may require both
halves of a double-precision result to be read out within a single clock cycle. This is
done by toggling the SELMS/LS signal in the middle of the clock period.
When a single-precision result is output, the SELMS/LS signal has no effect. The
SELMS/LS signal is set low only to read out the LSH of a double-precision result.
Whenever this signal is selecting a valid result for output on the Y bus, the OEY enable
must be pull.ed low at the beginning of that clock cycle.

Status Output Controls (SELST1-SELSTO,OES, OEC)
Ordinarily, SELST1-SELSTO are set high so that status selection defaults to the output
source selected by instruction input 16. The ALU is selected as the output source when
16 is low, and the multiplier when 16 is high.
When the device operates in chained mode, it may be necessary to read the status
results not associated with the output source. As shown in Table 19, SELST1-SELSTO
can be used to read the status of either the ALU or the multiplier regardless of the
16 setting.
Status results are registered only when the output (P and S) registers are enabled
(PIPES2 = L). Otherwise, the status register is transparent. In either case, to read
the status outputs, the output enables (OES, OEC, or both) must be pulled low.

Stalling the Device (HALT)

en
Z

~

»
n

Operation of the' ACT884 7 can be stalled nondestructively by means of the HALT
signal. Pulling the HALT input low causes the device to stall on the next low level
of the clock. Register contents are unaltered when the device is stalled, and normal
operation resumes at the next low clock period after the HALT signal is set high. Using
HALT in microprograms can save power, especially using high clock frequencies and
pipelined stages.

-4

ex)
ex)
~

.....

7-56

For some operations, such as a double-precision multiply with CLKMODE = 1, setting
the HALT input low may interrupt loading of the RA, RB, and instruction registers,
as well as stalling operation. In clock mode 1, the temporary register loads on the falling
edge of the clock, but the HALT signal going low would prevent the RA, RB, and
instruction registers from loading on the next rising clock edge. It is therefore necessary
to have the instruction and data inputs on the pins when the HALT signal is set high
again and normal operation resumes.

Instruction Inputs (110-10)
Three modes of operation can be selected with inputs 110-10, including independent
ALU operation, independent multiplier operation, or simultaneous (chained) operation
of ALU and multiplier. Each operating mode is treated separately in the following
sections.
In addition to the ALU and multiplier instructions described below, a NOP (no operation)
instruction is provided, for example, to retain a double-precision result on the Youtput
bus for an additional cycle:
NOP 110-10

=

011 0000 0000

Independent ALU Operations
The ALU executas single- and double-precision operations which can be divided
according to the number of operands involved, one or two. Tables 27 and 29show
independent ALU operations with one operand, along with the inputs 110-10 which
select each operation. Conversions from one formatto another are handled in this mode,
with the exception of adjustments to precision during two-operand ALU operations.
Wrapping and unwrapping of operands is also done in this mode.
Logical shifts can be performed on integer operands using the instructions shown in
Table 68. The data operand to be shifted is input on the DA bus, and the number of
bit positions the operand is to be shifted is input on the DB bus. The shift number
on the DB bus should be in positive 3.2-bit integer format, although only the lowest
eight bits are used. Neither the data operand nor the shift amount can be selected
from sources other than the RA and RB registers, respectively.
Tables 28 and 29 present independent ALU operations with two operands. When the
operands are different in precision,one single and the other double, the settings of
the precision-selects 18-17 will identify the single-precision operand so that it can
automatically be reformatted to double precision before the selected operation is
executed, and the result of the operation will be double precision.

~
00
~

U

«

o::t
,.....
2

CJ'J

7-57

Table 27. Independent ALU Operations with One Floating Point Operand
ALU OPERATION

INSTRUCTION

ON A OPERAND

INPUTS 11 0-10

Pass A operand

NOTES

OOx 001 x 0000

Pass - A operand

OOx 001 x 0001

Convert from 2's
complement integer
to floating point t

OOx 00100010

Convert from floating
point to 2's complement
integer

OOx 001x 0011

Move A operand (pass
without NaN detect or
status flags active)

OOx 001 x 0100

Pass B operand

OOx 001x 0101

1 = A (DP)

Convert from floating
point to floating point
(adjusts precision of
input: SP ..... DP, DP ..... SP)

OOx 001 x 011 0
OOx 001x 0111

14 selects absolute value of
a operand:

x = Don't care

o=

A (SP)

0= A
1 = jAj

Floating point to
unsigned integer
conversion

During integer to floating
point conversion, j A j is not
allowed as a result.

Wrap denormal operand
Unsigned integer to
floating point
conversion

OOx 001 x 1000
OOx 001 x 1010

Unwrap exact number

OOx 001 x 1100

Unwrap inexact number

OOx 001x 1101

Unwrap rounded input

OOx 001 x 1110

t During this operation, 18 selects the precision of the result.

7-58

18 selects precision of A
operand

Table 28. Independent ALU Operations with Two Floating Point Operands
ALU OPERATIONS

INSTRUCTION

AND OPERANDS

INPUTS 11 0-10

Add A

+ 6
+ 6
Add A + 161
Add IAI + 161

OOx xOOO OxOO

Add IAI

OOx x001 OxOO

Subtract A - 6

OOx xOOO Ox01

Subtract I A I - 6

OOx xOO 1 OxO 1

Subtract A -

OOx xOOO 1 xO 1

IBI

Subtract IAI Compare A, 6

161

NOTES

OOx xOOO 1 xOO

x = Don't Care

OOx xOO 1 1xOO

18 selects precision of A
operand:

OOx x001 1x01
OOx xOOO Ox 10

0= A (SP)
1 = A (DP)
17 selects precision of 6
operand:

o=

6 (SP)

Compare IAI ,6

00xx0010x10

Compare A, 161

OOx xOOO 1x10

Compare IAI, IBI
Subtract 6 - A

OOx xOO 1 1 x 10

12 selects either V or its
absolute value:

OOx xOOO Ox 11

O=V

Subtract 6 - I A I

OOx x001 Ox11

1 = IVI

Subtract 161 - A

OOx xOOO 1 x 11

Subtract 161 - IAI

OOx x001 1x11

1 = 6 (DP)

Table 29. Independent ALU Operations with One Integer Operand
ALU OPERATION

INSTRUCTION

ON A OPERAND

INPUTS 110-10

NOTES

Pass A operand

010 x01 00000

x = Don't Care

Pass -A operand (2's complement)

010 x01 00001

Negate A operand (1's complement)

010 x010 0010

18 selects format of A integer
operand:

Pass B operand

010 x010 0101

o=

Shift left logical

010 x01 0 1000

Shift right logical

010 x010 1001

Shift right arithmetic

010 x010 1101

Single-precision 2's
complement

1 = Single-precision unsigned
integer

7-59

Table 30. Independent ALU Operath;ms with Two Integer Operands
ALU OPERATIONS

INSTRUCTION

AND OPERANDS

INPUTS 11 0-10

Add A

+ B

NOTES

010 xOOO 0000

Subtract A - B
Compare A, B

010 xOOQ 0001

x

010 xOOO 0010

Subtract B - A

010 xOOO 0011

17 selects format of A and B
operands:

Logical AND A, B

010 xOOO 1000

o = Single-precision

Logical AND A, NOT B

010 xOOO 1001

complement

Logical AND NOTA, B

010 xOOO 1010

Logical OR A, B

010 xOOO 1100

1 = Single-precision unsigned
integer

Logical XOR A, B

010 xOOO 1101

=

Don't Care

2's

Independent Multiplier Operations
In this mode the multiplier operates on the RA and RB inputs which can be either single
precision, double precision, or mixed. Separate instruction tables are provided for
floating point operations and integer operations.
Floating point operands may be normalized or wrapped numbers, as indicated by the
settings for instruction inputs 11-10. As shown in Table 31. the multiplier can be set
to operate on the absolute value of either or both floating point operands. and the
result of any operation can be negated when it is output from the multiplier. Converting
a single-precision denormal number to double precision does not normalize or wrap
the denormal. so it is still an invalid input to the multiplier.
Table 31. Independent Floating Point Multiply Operations
MULTIPliER OPERATION

INSTRUCTION

AND OPERANDS

INPUTS 11 0-10

*

Multiply A
B
Multiply - (A
B)
Multiply
Multiply
Multiply
Multiply
Multiply

7-60

*

*

IB I
-(A
IBI)
IA I
B
- ( IA I
B)
IA I
IBI
- ( IA I
IBI)

Multiply A

*
*
*

*
*

NOTES

=

OOx x 100 OOxx

x

OOx x1 00 01 xX

18 selects A operand
precision (0 = SP, 1

=

DP)

17 selects B operand
precision (0 = SP, 1

=

DP)

OOx x100 10xx
OOx x 100 11 xx
00xx10100xx

Don't Care

OOx x101 01xx

11 selects A operand format
(0 ;;= Normal, 1 = Wrapped)

OOx x101 10xx

10 selects B operand format

OOx x101 11xx

(0

= Normal.

1

= Wrapped)

Table 32. Independent Floating-Point Divide/Square Root Operations
MULTIPLIER OPERATION

INSTRUCTION

AND OPERANDS t

INPUTS 110-10

NOTES
x = Don't Care

Divide A I B

OOx x110 Oxxx

SQRT A

OOx x 11 0 1 xxx

Divide IAII 8

OOx x110 Oxxx

SQRT IAI

OOx x 111 1 xxx

18 selects A operand precision
and 17 selects B operand
precision (0 = SP, 1 = DP)
12 negates multiplier result
(0 = Normal, 1 = Negated)
11 selects A operand format and
10 selects 8 operand format
(0 = Normal, 1 = Wrapped)

tl7 shou,ld be low or equal to 18 for square root operations

Table 33. Independent Integer Multiply/Divide/Square Root Operations
MULTIPLIER OPERATION
AND OPERANDS

*

*8

Multiply A
Divide A 18
SQRT A

INSTRUCTION
INPUTS 110-10
010 x100 0000
010 x110 0000
010 x110 1000

NOTES
x = Don't care
17 selects operand format:
o = SP 2's complement
1 = SP unsigned integer

tOperatiol1s involving absolute values. wrapped operands. or negated results are valid only when floatingpoint format is selected (19 = 0).

Chained Multiplier/ALU Operations
In chained mode the' ACT8847 performs simultaneous operations in the multiplier
and the ALU. Operations include not only addition, subtraction, arid multiplication,
but also several optional operations which increase the flexibility of the device. Division
and square root operations are not available in chained mode.
The B operand to the AlU can be set to zero so that the ALU passes the A operand
unaltered. The B operand to, the multiplier can be forced to the value 1 so that the
A operand to the multiplier is passed unaltered.

7-61

Table 34. Chained Multiplier/ALU Floating Point Operations t
CHAINED OPERATIONS

OUTPUT

INSTRUCTION

SOURCE

INPUTS 110·10

NOTES

MULTIPLIER

ALU

A*B

A+B

ALU

1 Ox xOOO xxOO

A*B

Multiplier

lOx xl00 xxOO

A*B

A + B
A - B

ALU

lOx xOOO xxO 1

A*B

A - B

Multiplier

lOx xl00 xxOl

A * B

2 - A

ALU

lOx xOOO xxl0

x = Don't Care

A*B
A * B

2 - A

Multiplier

lOx x100 xxl0

B-A

ALU

10x xOOO xx11

18 selects precision of
RA inputs:

B-A

Multiplier

lOx xl00 xx11

0= RA (SP)

A+O

ALU

10xxOl0 xxOO

1 = RA (DP)

lOx x110 xxOO

17 selects precision of
RB inputs:

A * B
A*B
A*B
A*B
A * B
A * 1
A * 1

A+O
0- A

Multiplier

ALU

lOx xOl0 xxl1

O-A

Multiplier

lOx xll0 xxll

o

= RB (SP)

1 = RB (DP)

A + B

ALU

1 Ox xOO 1 xxOO

A + B
A-B

Multiplier

lOx xl 01 xxOO

ALU

lOx xOOl xxOl

A-B

Multiplier

lOx xl01 xxOl

1

A * 1
A * 1

2-A

ALU

1 Ox xOO 1 xx 1 0

2 - A

Multiplier

lOx xl0l xx10

12 negates multiplier
result:

A * 1
A * 1

B-A

ALU

1 Ox xOO 1 xx 11

B-A

Multiplier

1 Ox xl 01 xx 11
lOx xOl1 xxOO

A * 1
A * 1

A * 1
A* 1
A * 1

A+O

ALU

A+O
O-A

Multiplier

lOx xl11 xxOO

ALU

1 Ox xO 11 xx 11

A * 1

O-A

Multiplier

lOx xlll xxl1

13 negates ALU result:

o = Normal
=

Negated

o = Normal
1

=

Negated

tThe 110-10 setting lxx xxlx xxl0 is invalid, since it attempts to force the B operand of the ALU to both
o and 2 simultaneously.

7-62

Table 35. Chained Multiplier/ALU Integer Operations
CHAINED OPERATIONS
MULTIPLIER
A*B
A*B

A * B
A*B
A*B
A*B
A*B
A*B
A*B
A * B
A * B
A*B
A* 1
A * 1
A* 1
A* 1
A * 1
A* 1
A * 1
A* 1
A * 1
A * 1
A * 1
A * 1

ALU

A
A
A
A

+
+
-

B
B
B
B
2 - A
2 - A
B-A
B - A
A+O
A+O
O-A
0- A
A + B
A+B
A - B
A-B
2 - A
2 - A
B-A
B. - A
A+O
A+O
a-A
0- A

OUTPUT

INSTRUCTION

SOURCE

INPUTS 110-10

ALU

11 0 xOOOOOOO
110 xl00 0000
110 xOOO 0001
110 xl00 0001
110 xOOO 0010
110xl000010
110 xOOO 0011
110 xl00 0011
110 xOl0 0000
110 xl10 0000
11 0 xO 10 0011
110 xl1 0 0011
110 xOOl 0000
110 xl01 0000
110 xOOl 0001
110 xl01 0001
110 xOOl 0010
110 xl0l 0010
110 xOOl 0011
110 xl0l 0011
110 xOll 0000
110xlll 0000
110 xOl1 0011
110 x 111 xx 11

Multiplier

ALU
Multiplier

ALU
Multiplier

ALU
Multiplier

ALU
Multiplier

ALU
Multiplier

ALU
Multiplier

ALU
Multiplier

ALU
Multiplier

ALU
Multiplier

ALU
Multiplier

ALU
Multiplier

NOTES

x = Don't Care
17 selects format of A
and B operands:
o = SP 2's
complement

1 = SP unsigned
integer

7-63

MICROPROGRAMMING THE ' ACT884 7
Because the' ACTSS4 7 is microprogrammable, it can be configured to operate on either
single- or double-precision data operands, and the operations of the registers, ALU,
and multiplier can be programmed to support a variety of applications. The following
examples present not only control settings but the timings of the specific operations
required to execute the sample instructions.
Timing of the sample operations varies with the precision of the data operands and
the settings of CLKMODE and PIPES. Microinstructions and timing waveforms are given
for all combinations of data precision, clock mode, and register settings.
Division and square root operations are presented after the discussion of ALU and
multiplier operations. Following the presentation of ALU and multiplier operations is
a brief sum-of-products operation using instructions for chained operating mode.

Single-Precision Operations
Two single-precision operands canbe loaded on the 32-bit input buses without use
of the temporary register so CLKMODE has no effect on single-precision operation.
Both the ALU and the multiplier execute all single-precision instructions in one clock
cycle, assuming that the device is not operating in flowthrough mode (all registers
disabled). Settings of the register controls PIPES2-PIPESO determine minimum cycle
time and the rate of data throughput, as evident from the examples below.

Single-Precision ALU Operations
Precision of each data operand is indicated by the setting of instruction input IS for
single-operand ALU instructions, or the settings of IS-17 for two-operand instructions.
When the ALU receives mixed-precision operands (one operand in single precision and
the other in double precision). the single-precision data input is converted to double
and the operation is executed in double precision.
If both operands are single precision, a single-precision result is output by the ALU.
Operations on mixed-precision data inputs produce double-precision results.

en
2

-...J
~

»

(")
~

CO
CO

.~

-...J

It is unnecessary to use the 'convert float-to-float' instruction to convert the singleprecision operand prior to performing the desired operation on the mixed-precision
operands. Setting .IS and 17 properly achieves the same effect without wasting an
instruction cycle.

Single-Precision Multiplier Operations
Operand precision is selected by IS and 17, as for ALU operations. The multiplier can
multiply the A and B operands, either operand with theabsolute value of the other,
or the absolute values of both operands. The result can also be negated when it is
output. If both operands are single precision, a single-precision result is output.
Operations on mixed-precision data inputs produce double-precision results.

7-64

Sample Single-Precision Microinstructions
The following four single-precision microinstruction coding examples show the four
register settings, ranging from flowthrough to fully pipelined. Timing diagrams
accompany the sample microinstructions.
In the first example PIPES2-PIPESO are all set" high so the internal registers are all
disabled. This microinstruction sets up a wrapped result from the multiplier to be
unwrapped by the ALU as an exact denormalized number. In flowthrough mode the
'unwrap exact' operation is performed without a clock as soon as the instruction is
input. Single-precision timing in flowthrough mode is shown in Figure 2.
CLKMODE = 0

PIPES = 111

C CC
L 00 P P
KNN I I
M F F PP
0 II EE
DGGSS
E 1-02-0

I I
0-0

000 0010 11 00 0 01

Operation: Unwrap A operand exact

SS
EE
LL

00
PP
7--0

RR
NN
DO
1-0

111 xxxx 11 xx 00

FIRST INSTRUCTION

S
E
L
M
S S
BEE R
S
FEE S /
YLLEH
OOOTSSSATT
ANNR
SRRcIEEEETTELPP
TAB C S Y C S P 1 -0 T T 1-0
0 1 1 0 1 0 0 0 x 11

1 1 11

SECOND INSTRUCTION

INSTRUCTION: FUNC(10.01. RND(1.01. FAST

===><~

____

FI_RS_T_O_P_ER_A_N_DS____

~)(~____SE_C_ON_D_O_P_E_RA_N_D_S__-J)(~________________

DATA(31.0) A AND B INPUTS

1 4 - - -tpdl----t-1
OUTPUT(31.01. STATUS(18.0)

Figure 2. Single-Precision Operation, All Registers Disabled
(PIPES = 111, CLKMODE .. 0)

The second example shows a microinstruction causing the ALU to compare absolute
values of A and B. Only the input registers are enabled (PIPES2-PIPESO = 110) so
the result is output in one clock cyde.
CLKMODE = 0

PIPES = 110

CCC
L 00 P P
K N N I I
M FF PP
0 II E E
DGGSS
E 1-02-0

I I
0-0
0000001 1010

o

01

Operation: Compare

SS
EE
LL

00
PP
7-0

RR
NN
DO
1 -0

11 0 xxxx 1111 00

IA I ' I B I

S
E
L
M
S S
S
BEE R
FEE S /
Y L L EH
ANNR
OOOTSSSATT
SRRCLEEEETT ELPP
TAB C S Y C S P 1 -0 T T 1-0

o

1 101 000 x 11

load First Operands
Begin First Operation

load Second Operands
Begin Second Operation

~

~

1 1 11

ClK

I4-tSU1-':"th1~

I4-- t sul':"

INSTRUCTION: FUNC(10.0), RND(l,O). FAST

~I

thl

:
I

< Op~I~;~DS

I

~ o~i~~~~s ~
I

I4-tsu2...-th1~

I4-- t su2 M4

~

thl

DATA(31,O) A AND B INPUTS

14

tpdl - - - - - - . .

14-14----tpd2---~~

OUT(31,O) STATUS(18,O)

Figure 3. Single-Precision Operation, Input Registers Enabled
(PIPES = 110, CLKMODE = 0)

7-66

Input and output registers are enabled in the third example, which shows the subtraction
B - A. Two clock cycles are required to load the operands, execute the subtraction,
and output the result (see Figure 4).
CLKMODE = 0

I I
0-0
00000000011

CLK

PIPES = 010

C CC
L 00 P P
KNN I I
M FF PP
0 II E E
D GG SS
E 1-02-0

Operation:

SS
EE
LL
00
PP
7-0

RR
NN
DD
1-0

Subtract B - A
S
E
L
S S
M
BEE R
S
Y L L E H
FEE S /
ANNR
OOOTSSSATT
SRRCLEEEETT ELPP
TAB C S y C S P 1 -0 T T 1-0
00001000x111111

0 01 010 xxxx 1111 00

Load First Operands
Begin First Operation

Load Second Operands
Begin Second Operation

!

~
I

It-------td1----------.t
I

I

I

14-- t su1 *th1 +I

I

I4-- t su1 ..~
I

INSTRUCTION: FUNC(10.0). RND(1.0), FAST

(

OP~:;~DS ~ O~~~~~~S ~
I

l4- t su2-.t h1+i

I4-tsu2

..14

"I

th1

DATA(31,O) A AND B INPUTS

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _>@/

Figure 10. Double-Precision ALU Operation. All Registers Disabled
(PIPES - 111. CLKMODE - 1)
";"I
-.J

(0

SN74ACT8847

REST
FIRST

The second example executes subtraction of absolute values for both operands. Only
the RA and RB registers are enabled (PIPES2-PIPESO '" 110). Timing is shown in
Figure 11.
CLKMODE

I I
0-0

PIPES

C CC
LOO PP
K NN I I
M FF PP
0 II EE
D GG SS
E 1-02-0

001 ;0011011

11

IAI

S
E
L
M
S

SS
EE
LL

RR
NN
DD
1-0

00
PP
7-0

110 xxxx 1111 00

S S
BEE R
FEE S I
Y L L EH
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1 -0 T T 1-0

o

1 1 0 x 000 x xx

1 1 11

load half
of First
Operands

load Rest
of First
Operands

load Half
of Second
Operands

Load Rest
of Second
Operands

load Half
of Third
Operands

load Rest
of Third
Operands

+

+

+

+

I

I

+

+

I
I
I
I

CLK

Operation: Subtract IBI -

110

I

I

I

FIRST INSTRUCTION

I

~tsu1~

SECOND INSTRUCTION

THIRD INSTRUCTION

I

I4-th1~~tsu1

I

INSTRUCTION: FUNC(10.01. RND(1.01. FAST

I
I4--tsu2~ I4--tsu2~ I4-- t su2

CJ>

th1
th1
OATA(31.0) A AND B INPUTS

~

~ I4-tsu2 ___ th1~ I4---*-th1~ (4.tsu2~th1

th1

tsu2

2

-...J
~

l>
(")
-t

SElMSILS

~

QUT(31.0) STATUS(18.0)

00
00
-...J

Figure 11. Double-Precision ALU Operation, Input Registers Enabled
(PIPES - 110, CLKMODE = 1)
7-80

The third example shows a single denormalized operand being wrapped so that it can
be input to the multiplier. Both input and output registers are enabled
(PIPES2-PIPESO = 010). Timing is shown in Figure 12.
CLKMODE = 1

I I
0-0

PIPES = 010

C
L
K
M
0
D
E

CC
00 P P
N N I I
FF PP
II E E
GG SS
1-02-0

Operation: Wrap Denormal Input

SS
EE
LL
00
PP
7-0

RR
NN
DD
1-0

001 10101000 1 11 010 xxxx 11 xx 00

S
E
L
M
S S
BEE R
S
FEE S /
Y L L EH
OOOTSSSATT
ANNR
SRRCLEEEETTELPP
TAB C S Y C S P 1 -0 TT1-0

o1

0 0 x 0 0 0 x xx

1 1 11

7-81

L 17BB.l~:nf17LNS
-..J

00

load Rest
of First
Operands

N

load Half
of First
Operands

. Begin First
Operation

~

~

I
I

•

I

-.J..-------.,
elK

load Half
of Second
Operands

Begin Second
Operation

~

~

load Output

I

I
14

I

load Rest
of Second
Operands

I

"'--1----.

.,

td3---

I
FIRST INSTRUCTION

I

SECOND INSTRUCTION

THIRD INSTRUCTION

I

th1~

I4-- t su1--+1

I

I4- t su1-+1

14- th1 +t 14- tsu1~

I+-th1~

INSTRUCTION: FUNC(10,Ol. RND(1,Ol. FAST

HALF
1ST OPS

tsu2 "-

HALF
2ND OPS

I

~

~ I4-tsu2~

th1

th1

I4- t su2-*th1-+t

REST
2ND OPS

~

HALF
3RD OPS

th1~~

tsu2

th1 --+t

tsu2

REST
3RD OPS
~

th1

~

tsu2

DATA(31,O) A AND B INPUTS

--L

SElMS/lS

DUT(31,O) STATUS(18,O)

~

~

~

~

tpd4

tpd5

tpd4

tpd5

Figure 12. Double-Precision ALU Operation, Input and Output Registers Enabled
(PIPES = 010, CLKMODE = 1)

The fourth example shows a conversion from integer to floating point format. All three
levels of data registers are enabled (PIPES2-PIPESO) so that the FPU is fully pipelined
in this mode (see Figure 13).
CLKMODE = 1

I I
0-0

PIPES = 000

C
L
K
M
0
D
E

CC
00 P P
NN I I
FF PP
II EE
GG SS
1-02-0

Operation: Convert Integer to Floating Point

SS
EE
LL
00
PP
7-0

S
E
L
M
S

RR
NN
DD
1-0

001 10100010 1 11 000 xxxx 1100 00

S S
BEE R
FEE S /
Y L L EH
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1 -0 T T 1-0

o1

1 x x 0 0 0 x xx

1 1 11

7-83

L1788.13"17LNS
Load Rest
of Third

-..J

Co
~

Load Rest

Operands

of First
Load. Half
of First

!

PBr8ndS

j"------"
I
CLK

Load Rest

Load Half

Begin Third

Operands Load Half of Second
Begin First of Second Operands

of Third
Operands

Oparation
Load Plpallne

rperation

1perands

I

II

I

I

141d2

I

I

FIRST
INSTRUCTION

t!!U1~

1

tadPiPBline

toad .Output

r

I

-\4

"I

td2

SECOND
INSTRUCTION

FOURTH
INSTRUCTION

THIRD
INSTRUCTION

I
th1-!4-+1~tsu1th1~ I4---+t- t su1

th1~

th1-1+---+1·l4---+t-tsu 1

INSTRUCTION: FUNC(10,01. RND(1,01. FAST

~

I
~

~~

tsu2 tM

~

~~

t5u2 th1

~

~14

tsu2 th1

~

~~

tsu2th1

~

~~

tsu2 th1

~

~~

tsu2 th1

~

~~

tsu2 th1

~

tsu2

~

th1

DATA(31 ,0) A AND BINPUTS

L

SELMS/LS

OUT(31,0) STATUS(18,0.)

tpd4~

tpd5-!4--t>1 tpd4-t+-+1

tpd5~

Figure 13. Double-Precision ALU Operation, All Registers Enabled
(PIPES - 000, CLKMODE - 1)

tpd4-!4--t>1 tpd5~

Double-Precision Multiplier Operations
Independent multiplier operations may also be performed in either clock mode and with
various registers enabled. As before, examples for the two clock modes are treated
separately. A double-precision multiply operation requires two clock cycles to execute
(except in flowthrough mode) and from one to three other clock cycles to load the
temporary register and to output the results, depending on the setting of
PIPES2-PIPESO.
Even in flowthrough mode (PIPES2-PIPESO = 111) two clock edges are required, the
first to load half of the operands in the temporary register and the second to load the
intermediate product in the multiplier pipeline register. Depending on the setting of
CLKMODE, loading the temporary register may be done on either a rising or a falling
edge.

Double-Precision Multiplication with CLKMODE

=

0

In this first example, the A operand is multiplied by the absolute value of B operand.
Timing for the operation is shown in Figure 14:
CLKMODE = 0

PIPES

=

111

Operation: Multiply A

* IBI

S
C CC
L 00 P P

K NN I I
M FF P P
I I
0-0

o "
oGG

EE
SS
E 1-02-0

001 1100 1000 0 11

E
L

SS
EE
LL
00
PP

7-0

M

SS
S
BEE R
RR FEES/
YLLEH
NNANNR
OOOTSSSATT
DO SRRCLEEEETT ELPP
1-0 TAB C S Y C S P 1 -0 T T 1-0

111 1111 xxxx 00

0 x x x x 0 0 0 x xx

1 1 11

7-85

Lv88.l:>"vLNS
-..J

eX>

(l)

r-.

load Half of

_______-!r-·
ClK

(

FIRST INSTRUCTION

I

I

\4--- t 1 ---+t
SU

INSTRUCTION: FUNC(10.01. RND(1.01. FAST

( I-

~tsu2

X

l:t~S
..j.

th1

l::~~S

I~----~~~----~I--------------------------------------------------~
tsu3
~

DATA(31.01 A AND B INPUTS

SElMS/lS

~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

OUT(31.0) STATUS(1B.OI

~

tpd2

~

HALF
FIRST

~
~

~tpd5----+1

Figure 14. Double-Precision Multiplier Operation. All Registers Disabled
(PIPES ... 111. CLKMODE .. 0)

REST
FIRST

The second example assumes that the RA and RB input registers are enabled. With
CLKMODE = 0 one clock cycle is required to input both the double-precision operands.
The multiplier is set up to calculate the negative product of I A I and B operands:
CLKMODE

=0

PIPES

= 110

CCC
LOO PP
K NN I I
M FF PP
0 II E E
D GG SS
E 1-02-0

I I

0-0

SS
EE
LL
PP

RR
NN
DD

7-0

1 -0

00

001 11 0 1 01 00 0 11 1101111 xxxx 00
Load Rest
of First
Operands
Load half
of First
Operands

•I

l

I

Begin First
Operation

o

1 1 x x 000 x xx 1 1 11
Load Rest
of Second
Operands
Begin Second
Operation

load Pipeline

•I

B)

S
E
L
M
S S
BEE R
S
Y L L EH
FEE S /
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1 -0 T T 1-0

Load Half
of Second
Operands

•I

+

I

I

I
I
I

ClK

*

Operation: Multiply -(IAI

r

~ td2 ------+I

I

I

I
FIRST INSTRUCTION

SECOND INSTRUCTION

i+th1 ........... tsu1-+i
,

14-- th 1 ---+i

INSTRUCTION: FUNC(10,01. RND(1,0). FAST
HALF
1ST OPS

REST
1ST OPS

REST
2ND OPS

HALF
2ND OPS

I+-- t su2-+t+-- th1-+1 I+- tsu2--':'- th1 .......... t su2-+i4- th1 -.J
DATA(31 ,01 A AND B INPUTS

14

~4

th1-+1

tsu2

SELMSILS

HALF
REST
HALF
REST
~
2ND
2ND
1ST
1ST
------------------------------~
OUT(31.0) STATUS(18,0)

I4--+i

I4--+i

14-+1

14-+1

tpd2

tpd5

tpd2

tpd5

Figure 15. Double-Precision Multiplier Operation, Input Registers Enabled
(PIPES == 110, CLKMODE == 0)
7-87

Enabling both input and output registers in the third example adds an additional delay
of one clock cycle, as can be seen from Figure 16. The sample instruction sets up
calculation of the product of I A I and I B I :

a

CLKMODE =

PIPES

= 010

Operation: Multiply I A I

*

IB I

S

E
CCC
L 00 P P
K NN I I

M FF PP
o II E E
I I
0-0

D GG SS
E 1-0 2-0

00111011000

a

SS

EE
LL
00
PP

7-0

10 0101111 xxxx 00

+

a

11 x x

aaa

x xx

11 11

Load Rest
of Second
Operands

Load Rest
of First
Operands
Load Half
of First
Operands

L
M
SS
S
BEE R
RRFEES/
YLLEH
NNANNR
OOOTSSSATT
DD SRRCLEEEETT ELPP
1 -0 TAB C S Y C S P 1 -0 TT1-0

Load Half
of Second
Operands

Begin Second
Operation

Begin First
Operation

+
I
I+--- td2 --,...,.....--tdl~

eLK

I

I
FIRST INSTRUCTION

~tsu1

SECOND INSTRUCTION

~ th1-tJi
I

THIRD INSTRUCTION

... tsu1-t1Jt

FUNC(10.01. RND(1.01. FAST
I

I
REST
3RD OPS
I

1+ tsu2 +14- th 1 -.I 1+ tsu2" th 1 -.t 14- tsu2 +14- th 1 +I 14- tsu2 +1+ th 1 +I
DATA(31.0) A AND B INPUTS

L
SELMS/LS

~

---------------------~
OUT(31.01 STATUS(18.01
Figure 16. Double-Precision Multiplier Operation, Input and Output Registers Enabled
(PIPES -= 010, CLKMODE .. 0)
1'88

With all registers enabled, the fourth example shows a microinstruction to calculate
the negated product of operands A and B:
CLKMOOE = 0

I I
0-0
001 11000100

PIPES = 000

CCC
L 00 P P
K N N I I
M FF PP
0 II EE
oGG SS
E 1-02-0

o

Operation: Multiply -(A

SS
EE
LL
00
PP
7-0

RR
NN
DO
1 -0

01 000 1111 xxxx 00

*

B)

S
E
L
M
S S
BEE R
S
FEE S /
Y L L EH
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1 -0 TT1-0

o

1 1 x x 0 0 0 x xx

1 1 11

7-89

Lv88.l~nfvLNS
-...J

cO

o

-

Load Rest
of First
Operands

Load Rest
of Second
Operands

Load Half
of Third
Operands

Load Half
of Second
Operands

Begin Second
Operation

Load Pipeline

Load Half
of First
Operands

Begin First
Operation

Load Pipeline

Load Pipeline

Load Output

~

~

~

~

~

,

eLK

.'4

14--td2
I

~

td2

td2 ~

I

I

FIRST
INSTRUCTION

,

th1~

~tsu1~

THIRD
INSTRUCTION

SECOND
INSTRUCTION

I

~tsu1

th1~

_ _ _ t su 1

....... th1~

,

INSTRUCTION: FUNC110,01. RNDI1,0)' FAST

I4-tsu2~

th1

14
tsu2

th1

tsu2

th1

tsu2

th1

.14

tsu2

~

., '4

th 1

th1--.J

tsu2

DATAI31 ,0) A AND B INPUTS

SElMS/LS

----------------------------------------------------------------~

OUTI31,0) STATUSI18,0)

~

~

~

~

tpd4

tpd5

tpd4

tpd5

Figure 17, Double-Precision Multiplier Operation. All Registers Enabled
(PIPES = 000, CLKMODE = 0)

Double-Precision Multiplication with CLKMODE = 1
Setting the CLKMODE control high causes the temporary register to load on the falling
edge of the clock. This permits loading both double-precision operands within the same
clock cycle. The time available to output the result is also affected by the settings
of CLKMODE and PIPES2-PIPESO, as shown in the individual timing waveforms.
The first multiplication example with CLKMODE set high shows a multiplication in
flowthrough mode (PIPES2-PIPESO = 111). Figure 18 shows the timing for this
operating mode:
CLKMODE

I I
0-0

=1

PIPES = 111

CCC
L 00 P P
K NN I I
M FF PP
0 II EE
D GG SS
E 1-02-0

001 1100 1000 1 11

Operation: Multiply A

SS
EE
LL
00
PP
7-0

*

181

S
E
L
M
S S
8 EE R
S
Y L L EH
RR FEE S /
NN ANNR
OOOTSSSATT
DDS R R C [ E E E E TT E L P P
1-0 T A 8 C S Y C S P 1 -0 T T 1-0

111 1111 xxxx 00

ox

x x x 0 0 0 x xx

1 1 11

7-91

load Half
of Operands

load Pipeline

•

•

L

I

ClK

:

<

I~STRUCTION

FIRST

I+- t su1":
INSTRUCTION: FUNC(10,O}', RND(1,OL FAST

< l~:~~S

)(~_l_:_i_~~_s________________~:_______________________________
tf-tsu2~ '4
t su3-------+t.:
th1

DATA(31,O} A AND B INPUTS

SElMS/lS

~

--------------------------~
OUT(31,O} STATUS(18,O}

Figure 18. Double-Precision Multiplier Operation. All Registers Disabled
(PIPES - 111. CLKMODE == 1)
In the second example, the input registers are enabled and the instruction is otherwise
similar to the corresponding example for CLKMODE = O. Timing is shown in Figure 19.
CLKMODE = 1

en

2
.....,
~

(")

»

I I

.-of

0-0

00
00

~
.....,

001 1101 0100

7-92

PIPES = 110

C
L
K
M
0
D
E

CC
00
NN
FF
II
GG

Operation: Multiply -(IAI

*

B)

S
E
L
M
S

PP
I I
PP
EE
SS

SS
EE
LL
00
PP

RR
NN
DD

1-02-0

7-0

1 -0

11 110 1111 xxxx 00

S S
BEE R
FEE S I
Y L L EH
OOOTSSSATT
ANNR
SRRCLEEEETT ELPP
TAB C S Y C S P 1 -0 T T 1-0

o1

1 x x 0 0 0 x xx 1 1 11

Load Rest
of First
Operands
Load Half
of Fitst
Begin First
Operands Operation

l

1

~

I

I

I
I
I
I

~td2 - - - - . t

i

Load Half
of Second Begin Second
Operands Operation

~

~

I

I

I
I
I

FIRST INSTRUCTION

SECOND INSTRUCTION

I

~ tsu1

Load Pipeline

~
I

eLK

Load Rest
of Second
Operands

I

~I

~th1

I

INSTRUCTION: FUNC(10,OI. RND(1,OI. FAST
HALF
1ST OPS

REST
1ST OPS

14- tsu2..-.t I.

th1

tsu2

~.

th1_

REST
2ND OPS

HALF
2ND OPS

tsu2 14

~I.

..-1>11.
th1

th1-----.1

tsu2

DATA(31,O) A AND B INPUTS

SELMS/LS

~

---------------------~'-----.....;.--OUT(31,O) STATUS(18,O)
Figure 19. Double-Precision Multiplier Operation, Input Registers Enabled
(PIPES == 110, CLKMODE = 1)

7-93

With both input and output registers pipelined, the third example calculates the product
of IA I and 18 I. Enabling the output register introduces a one-cycle delay in outputting
the result (see Figure 20):
CLKMODE

=1

PIPES

C
L
K
M

I I
0-0

=

010

Operation: Multiply IA I

CC

00 P P

NN I I
FF PP
0 II EE
D GG SS
E 1-02-0

SS
EE
LL

00
PP
7-0

RR
NN
DD
1 -0

001 1101 1000 1 11 010 1111 xxxx 00

7-94

*

181

S
E
L
M
S S
S
8 EE R
FEE S /
Y L L E H
ANNR
555TSSSATT
SRRCLEEEETTELPP
T A 8 C S Y C S P 1 -0 TT1-0

o

1 1 x x 0

a0

x xx

1 1 11

Load Rest
of Second
Operands

Load Rest
of First
Operands
Load Half
of First
Operands

~

Begin First
Operation

Load Half
of Second
Operands

Begin Second
Operation

I

load Output

load Pipeline

~

+

~

~

SECOND INSTRUCTION

FIRST INSTRUCTION

~th1
I

INSTRUCTION: FUNC(10.01. RND(1.01. FAST
HALF

HALF

1ST OPS

2ND OPS

~ tsu2-----+t++114 ~14
th1 tsu2 th1
DATA(31,OI A AND B INPUTS

~

~tsu2--.1144""~~I'" ~14

~I

th1

th1 tsu2

SELMS/lS

~

-------------------------'~
1414--••+-1 tpd4
1414--.~+-1 tpd5

OUT(31,OI STATUSI18,OI

Figure 20. Double-Precision Multiplier Operation, Input and Output Registers Enabled
(PIPES - 010, CLKMODE = 11

7-95

The fourth example shows the instruction and timing (Figure 21) to generate the
negated product of the A and B operands. This operating mode with CLKMODE set
high and all registers enabled permits use of the shortest clock period and produces
the most data throughput, assuming that this is. the primary operating mode in which
the device is to function.
Additional considerations affecting timing and throughput are discussed in the section
on mi? The next four examples show double-precision floating point division. The operands
(')
-f
00
00

.Jlo

may be single or double precision, or a combination of both. However, wrapped single
precision numbers may not be used. A single-precision number should be loaded in
the most significant half of the double precision operand .

-..J

Each example includes a timing diagram for a different setting of the internal register
controls (PIPES2-PIPESO). The examples use both clock modes 0 and 1.

7-102

The first example shows a mixed-precision, mixed-mode operation with input registers
RA and RB enabled. A single precision number is divided by a double precision wrapped
number. The output, in double-precision format is available after thirteen rising clock
edges, and may be valid for that cycle only. If the next operation is double precision,
the first half of the operands may be loaded on the rising edge of clock 13 (using clock
mode 0). The second half operands and the instruction are loaded on the fourteenth
clock. A single-precision operation may only be loaded on the fourteenth rising edge.

=

CLKMODE

0

PIPES

= 110

Operation: A / B(wr)

S
E
C CC
L 00 P P
K.NN I I

L

SS

o

II E E
G G S S
E 1-02-0

o

000 111 0 0001

SS
S
BEE R
RRFEES/
YLLEH
NNANNR
555TSSSATT
DDS RR C [ E E E E T TEL P P
1 -0 TAB C S Y C S P 1-0 T T 1-0

EE
LL
00
PP

M FF PP
I
1 I
0-0

M

7-0

0 0 1 1 10 1 1 11 11 11 00

2

3

4

5

6

7

8

9

0 1 1 x x 0 0 0 x 1 1 1 1 11

10 1 i 12

14

13

elK

INST

J
l\
I

1\
DIV

I

~ Isu1
---\

Y

J

--------------<:

I:~i

UNDETERMINED

I++/- t h1
UNDETERMINED

(

I \

--JJ4)-:- - -

,-_N_EX_T_(O_P_1

tsu1~

+I

I

tsu1-l++1

J+.th1

~

: :L:!)----:

tpd3-+1

I+-

Figure 26. Double-Precision Floating Point Division
(PIPES2-PIPESO = 110)

7·103

In the next example, the divisor is a wrapped number. Since both numbers are double
precision, the result may overflow, setting the OVR flag. With the multiplier pipeline
and input registers enabled, the next double-precision operands and instruction may
be loaded on the twelfth and thirteenth rising clock edges (clock mode 0), as shown
in Figure 27.
CLKMODE

=a

=

PIPES

C
L
K
M

Operation: A / B(wr)

100

CC

00 P P

SS
EE
LL

NN I I
FF PP
0 II E E
DGGSS
E 1-0 2-0

1 I
0-0
00 1 11 1a 000 1

a

01
3

2

4

00
PP
7-0

RR
NN
DD
1 -0

100 1111 11 11 00
5

6

7

8

S
E
L
M
S S
BEE R
S
Y L L EH
FEE S /
OOOTSSSATT
ANNR
SRRCLEEEETT ELPP
TAB C S Y C S P 1 -0 T T 1-0

a

xxOOOx111111

1

9 10 11 12

14

13

elK

J

INST:\

I

DIV

I

*-* tsu1

y

\

UNDETERMINED

(

/i~I--";;';";;';;;';;;';';;';';;"------<1
~th1

NEXT

~tsu1

IDP~

I )
>.-:- - - - - - -

I+*-th1
I++t-tsu1

~~_____~____~U~ND~E~T~E~RM~IN~E~D_____________!~:~~
tpd3-+1

I+-

Figure 27. Double-Precision Floating Point Division
(PIPES2-PIPESO = 100)

7-104

____

A double-precision number is divided by a single-precision number in the third example.
Clock mode 1 is used, with input and output registers enabled (PIPES2-PIPESO = 010).
The output is available after the fourteenth rising clock edge and may only be valid
for that cycle. If the next operation is double precision, half the operands can be loaded
on the falling edge of the thirteenth clock, and the second half operands and instruction
load on rising edge of the fourteenth clock. If the next operation is single precision,
the instruction must be loaded on the fourteenth rising edge.
CLKMODE = 1

PIPES = 010

C
L
K
M
0
D
E

1 I
0-0
001 0110 0000

CC
00 P P
NN I I
FF PP
II EE
GG SS
1-02-0

SS
EE
LL
00
PP
7-0

RR
NN
DD
1 -0

1 01 010 1111 1111 00
3

2

Operation: A / 8

4

5

6

7

S
E
L
M
S S
S
8 EE R
FEE S I
Y L L EH
ANNR
OOOTSSSATT
SRRCLEEEETT ELPP
TAB C S Y C S P 1 -0 TT1-0
0

1 x x 0 0 0 x 11
14

13

8 9 10 11 12

1 1 11

elK
I

I

~__~I

INST

J
1\

UNDETERMINED

DIV

tsu1-J.,..:;j

v

I

\ji\.i...;....---;,;.;:;::..;;.;.=.:.;:;:.;;.;:::;..------4j '-__
(

\

N_EX_T_(D_PI....,...J/I).,----

I4-M-th1

tsu1~

~th1

I

I

I

I

~

\
UNDETERMINED
I
~\.-------.:..:..;.;;;.::.:..;:::.;;;.::;.;.:.:....-------.:..-.-,v:::::r
tpd4-.1

j4-

Figure 28. Double-Precision Floating Point Division
(PIPES2-PIPESO = 010)

7-105

The last example is a microinstruction for A / B with all registers enabled
(PIPES2-PIPESO == 000). Both operands are double precision. The output is availabie
after the fourteenth rising edge. The next double-precision operation may be loaded
on the. falling edge of clock 12 and the rising edge of clock 13 using clock mode 1.
If the next operation is single precision, the instruction must be loaded on the thirteenth
rising clock edge.
CLKMODE == 1

Operation: A / B

PIPES == 000

C
L
K
M
0
D
E

I
1 I
0-0

CC
00 P P
NN I I
FF PP
II E E
GG SS
1-02-0

SS
EE
LL
00
PP
7-0

RR
NN
DD
1-0

001 111 0 0000 1 00 000 1111 11 11 00
2

3

4

5

6

7

8

9

S
E
L
M
S S
BEE R
S
FEE S /
Y L L EH
ANNR
OOOTSSSATT
SRRCLEEEETT ELPP
TAB C S Y C S P 1-0 T T 1-0
0 1

10 11 12

x x 0 0 0 x 11
13

1 1 11

14

elK

UNDETERMINED

I

~

---\
UNDETERMINED
Y ---I)--------...;;.;.=.;..;;;.;.;==---------~

tpd4~

Figure 29. Double-Precision Floating Point Division
(PIPES2-PIPESO == 000)

7-106

14-

Integer Division
The following sample microinstructions perform division operations on single-precision
integer operands. Both operands must be in the same format (unsigned or two's
complement), and absolute value, wrapped numbers, and negated outputs are not
allowed. Each example includes a timing diagram for a different setting of the internal
register controls (PIPES2-PIPESO).
The first example shows A / B with only the input registers RA and RB enabled. Both
operands are in two's complement format. The result is available after the rising edge
of the fifteenth clock and may be valid for only that cycle. The next instruction and
data may be loaded on the sixteenth clock.

=

CLKMODE

=

PIPES

0

C
L
K
M
0
D
E

I
1 I
0-0

CC
00 P P
N N I I
FF P P
II E E
GG SS
1-02-0

01001100000 0 01
2

3

110

4

Operation: A / B

SS
EE
LL
00
PP
7-0

RR
NN
DD
1-0

1101111 1111 00
5

6

7

8

9

S
E
L
M
S S
BEE R
S
FEE S /
Y L L EH
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P1 -0 T T 1 -0
0 1 1 x x 0 0 0 x11

17

16

10 11 12 13 1415

11 11

eLK

-0'

I

I

INST

I

DIV

tsu1~

A.

UNDETERMINED
i-----..;.....;..-.........;
..............-----~---~

_____

""';:---4(

U;..;N..;.;;D;.;;E;.;. TE;;;.R;.;.;M;.;.;IN..;.;;E;;;.D_ _ _ _ _

tpd3-t1

Figure 31. Integer Division
(PIPES2-PIPESO = 100)

7-108

---.;...-----

~i

QUOTIENT

14-

)>-_____

In the third example, unsigned integer numbers are divided. The pipeline settings
(PIPES2-PIPESO = 010) enable the input and output registers. Timing for this
microinstruction is shown in Figure 32.
CLKMODE

=0

PIPES

= 010

Operation: A / B

CCC
L 00 P P
K NN I I
M FF PP
0 II EE
D GG SS
E 1-02'-0

I
1 I
0-0

SS
EE
LL
00
PP
7-0

RR
NN
DD
1-0

010 111 0 0000 0 01 010 1111 1111 00
2

3

4

5

6

7

8

S
E
L
M
S S
BEE R
S
Y L L EH
FEE S /
ANNR
555TSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1-0 T T 1-0
0 1

9 10 111213 14

elK
I

16

15

17

e
I

-V------.. . . ---.. . . ----------!C
UNDETERMINED

--"---

1 NEXT ~i

tsu1~

I
I4-tf- th 1

tsu1*-+/

I

j+-I"\- th 1
I

I
---\

1 1 11

I

I

~
INST

x x 0 0 0 x 11

UNDETERMINED

I

~

y ~~-----------;...;...------;...;...;.....;,~

\.Figure 32. Integer Division
(PIPES2-PIPESO = 010)

7-109

The final example has all internal registers enabled. The output is valid after the
sixteenth clock edge, but the next instruction can be loaded one cycle earlier.
CLKMODE

=

0

PIPES

=

CCC
L 00 P P
K NN I I
M FF PP
0 II EE
D GG SS
E 1-02-0

I
1 I
0-0

Operation: A I B

000

SS
EE
LL
00
PP
7-0

RR
NN
DD
1-0

01 0 111 0 0000 0 01 000 111 1 1111 00
2

3

4

5

6

7

8

0 1

xxOOOx 111111

9 10 11 12 13 14

elK
I

15

e
I

~
ID----------------<,
UNDETERMINED

tsu1~

I

NEXT

)-,- - , - - - - - - -

I
I+-*- th1

tsu1~

I4-*th1

,I
~

17

16

I

I
INST

S
E
L
M
S S
BEE R
S
FEE S I
Y L L EH
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1 -0 T T 1-0

,

,

UNDETERMINED

~

Y ~~---------------------'~f\::/

j4...
Figure 33. Integer Division
(PIPES2-PIPESO = 000)

en

~ Square Root Microinstructions

i:

Square root calculations are performed as independent multiplier operations, as
(") determined by the settings of instruction bits 110, 15, and 13. Independent multiplier
~ operation is selected by setting 110 low, while both 15 and 13 must be set high to select
(Xl a square root operation.
~

'-I

Taking the square root of a nonzero negative number sets the IVAL flag and produces
an NaN result. Square root of negative zero does not set IVAL and produces a negative
zero result. Only the A operand is used in a square root calculation. The operand may

7-110

be a single-precision integer, single-precision floating point number, or double-precision
floating point number. Since the B operand is unused, the 17 input should be set low
or set to match the 18 input, and the 10 input is a "Don't Care"

Single-Precision Floating Point Square Root
The following four sample microinstructions select square root operations on singleprecision floating point operands. Each example includes a timing diagram for a different
setting of the internal register controls (PIPES2-PIPESO).
The first example shows an instruction to perform SQRT I A I on a wrapped number
with only the RA and RB input registers enabled (PIPES2-PIPESO = 110). The result
is available after the tenth rising clock edge and may be valid only for that cycle. The
next instructions and data operand may be loaded on the following rising clock.
CLKMODE = 0

PIPES = 110

C
L
K
M
0
D
E

I
1 I
0-0

CC
00 P P
NN I I
FF PP
II EE
GG SS
1-02-0

000 011 1 101 x 0 01

Operation: SQRT IAI

SS
EE
LL
00
PP
7-0

11 0 111 1 1 11 1 00

23456789

eLK

10

-9

11

I

S. QUARE _ _ _ _ _ _ _
_ _ _ _ _ _ _ _-:-_ _-:<,
UNDETERMINED

I

ROOT,

I

--I

NEXT )-,_ _ _ _ __

tsu1 ~
,
~th1

tsu1-1+-+1
I
I'Ht"th1

~.

1 1 11

I

I

Y

0 1 1 x x 0 0 0 x 11

e

I
INST

RR
NN
DD
1 -0

S
E
L
M
S S
BEE R
S
FEE S /
Y L L EH
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1 -0 T T 1-0

UNDETERMINED

r:::::::'\.
QUARE )-_ _ _ _ _ __

'\.:::::J
If,Figure 34. Single-Precision Floating Point Square Root
IPIPES2-PIPESO = 110)

7-111

The square root of a wrapped number is calculated in the second example. Both the
input registers and multiplier pipeline are enabled, allowing the next instruction to be
loaded on the tenth rising clock (see Figure 35).
CLKMODE

=a

PIPES

C
L
K
M
0
D
E

1 I
0-0
000

a11 a 00 1 x a

CC
00
NN
FF
II
GG

= 100

Operation: SQRT A(wr)

PP
I I
PP
EE
SS

SS
EE
LL
00
PP

1-02-0

7-0

S
E
L
M
S S
BEE R
S
RR FEE S /
Y L L EH
NN ANNR
OOOTSSSATT
DDS R R C [ E EE E T TEL P P
1 -0 TAB C S Y C S P 1-0 T T 1-0

23456789

eLK
I
I

INST

SQUARE
ROOT

tsu1 ~

UNDETERMINED

~

---.I

aaa

x 1 1 1 1 11

11

10

e

----------~I

1

1

NEXT

t su1-1.--.!

~th1
Y

1 1 x x

I

-@
I

a

01 100 1111 1111 00

1- - - - - - - - - - -

....

I

j+-+t-th1
UNDETERMINED

I
I
tpd3-tj

~...-_______

I\:::::J
14-

PIPES (1101

Figure 35. Single-Precision Floating Point Square Root
(PIPES2-PIPESO =:' 100)

7-112

Enabling both the input and output registers (PIPES2-PIPESO = 010) in the next
example delays the output by one cycle. This instruction calculates - SQRT IA I
CLKMODE

= 0

PIPES

=

010

Operation: - SQRT IA I

S
E
C
L
K
M

CC
00 P P
NN I I
FF P P

o " EE

1 I
0-0

D GG SS
E 1-02-0

SS
EE
LL
00
PP

7-0

RR
NN
DD
1-0

000 011 0 01 Ox 0 0.1 01 0 1111 111 1 00
23456789

L
M
SS
S
BEE R
FEE S /
YL L EH
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1-0 T T 1-0

0 1 1 x x 0 0 0 x 11
10

1 1 11

11

elK

INST

8'

-§
I

SQUARE
ROOT

tsu1~

UNDETERMINED
~_ _ _ _ _
_ _ _ _ _ _ _-~I

I

I

tsu1-1+---i

14-+1- th 1
V ---\

--..I

.NEXT

)..,-------

I

j4-tf- th 1

~

UNDETERMINED

tp

;-;;;;:;:;'\).._ _ __

"~

d4-+j j4-

Figure 36. Single-Precision Floating Point Square Root
(PIPES2-PIPESO = 010)

7-113

The fourth instruction performs SQRT A with all registers enabled. The output is valid
after the .eleventh rising clock edge, and the next instruction may be loaded on the
tenth rising clock.
CLKMODE

=0

PIPES

=

000

Operation: SQRT A

S
E
C CC
LOO PP
KNN I I
M F F PP
0 II EE
D GG SS
E 1-02-0

1 I
0-0

SS
EE
LL

00
PP
7-0

RR
NN
DD
1-0

000 011 0 1OOx 0 01 000 1111 1 111 00
23456789

L
M
S S
BEE R
S
FEE S I
Y L L EH
ANNR
OOOTSSSATT
SRRCLEEEETT EtPP
TAB C S Y C S P 1-0 T T 1-0
0 1 1 x x 0 0 0 x 11 1 1 11

10

11

eLK
I
I

INST

I
I

~_ _ _ _U_N_D_ET_E_R_M_IN_E_D_ _--1--...:...--------~
I

tsu 1--f4-+/

~th1

y

=:J

tsu 1 ~

1

~th1

>--_ _ _UNDETERMINED
____

@

~

I
t p d4-11i

SQUARE

ROOT

j4-

Figure 37. Single-Precision Floating Point Square Root
(PIPES2-PIPESO = 000)

7-114

~_

Double-Precision Floating Point Square Root
The next four examples show square root operations on double-precision floating point
operands. Each example includes a timing diagram for a different setting of the internal
register controls (PIPES2-PIPESO). Both clock modes 0 and 1 are used in the examples.
The first sample instruction calculates - SORT A. Clock mode 1 is shown. With only
the input registers RA and RB enabled, the output is valid after the sixteenth rising
clock edge and may be stable for that cycle only. If the next instruction is a doubleprecision operation, the first half of the data operands may be loaded on the falling
edge of clock 16 (assuming clock mode 1). The second half of the data and the
instruction are loaded on the seventeenth rising clock edge. A single-precision operation
must be loaded on the seventeenth rising edge.
CLKMODE = 1

PIPES = 110

C CC
L 00 P P
KNN I I
M FF PP
0 II E E
D GG SS
E 1-02-0

I
1 I
0-0
001 0110 11 Ox
2

1 11
3

4

5

Operation: - SORT A

SS
EE
L L
00
PP
7-0

S
E
L
M
S S
BEE R
S
Y L L EH
RR FEE S /
NN ANNR
OOOTSSSATT
DDS R R C LE E E E T TEL P P
1 -0 TAB C S Y C S P 1 -0 T T 1-0

110 1111 1111 00
6

7

8

01 1 x x 0 0 0 x 11

9 1011 12 1314

15

1 1 11

17

16

eLK

UNDETERMINED

INST

I

I

_""-_ _'"""'1',"" ,I

-_-:-' I
I
I
**-th1

_____________

I

~tsu1
I

Y

=>~

~th1

I

I

U_N_DE_T_E_R_M_IN_E_D___________~I~@SQUARE~___
II
I I

ROOT

-.I I4-tpd3
Figure 3S. Double-Precision Floating Point Square Root
(PIPES2-PIPESO
110)

=

7-115

The second example shows an instruction to perform SQRT 1 A I. Because the multiplier
pipeline is enabled (PIPES2-PIPESO = 100), the next double-precision operand and
instruction may be loaded on the falling edge of clock 1 5 (using clock mode 1) and
the rising edge of clock 16. If the next operation is single precision, it must be loaded
on the sixteenth rising clock.
CLKMODE

= 0

PIPES = 100

C CC
L 00 P P
K NN I I
M FF PP
011 EE
D GG SS
E 1-02-0

I
1 I
0-0

001 0111 100x 0 01
2

3

4

5

Operation: SQRT IAI

SS
EE
LL
00
PP
7-0

RR
NN
DD
1-0

100 1111 1111 00
6

7

8

S
E
L
M
S S
BEE R
S
FEE S I
Y L L EH
ANNR
OOOTSS SATT
SRRCLEEEETTELPP
TAB C S Y C S P 1 -0 T T 1-0
0 1 1 x x 0 0 0 x 11

9 10 11 12 13 14 15

1 1 11

17

16

eLK

INST

UNDETERMINED
I

NEXT lOP)

I ___

1+--* t$u1

I

~_I

I

I

I4-+1-th1

~________________U_N_D~ET_E~R_M_IN~E~D____________~:~@SQUAAE~_____
I

I

ROOT

I I
-+I J+-tpd3

Figure 39. Double-Precision Floating Point Square Root
(PIPES2-PIPESO = 100)

7-116

In the third example, the operand is a Wrapped number. With both input and output
registers enabled (PIPES2-PIPESO = 010), the output is valid after the seventeenth
clock cycle. If the next operation is double precision, the first.halfoperands may be
loaded on the sixteenth rising clock edge, using clock mode O. The remaining operands
and instruction are then loaded on the seventeenth rising edge. If the next operation
is single precision, the instruction and operands are loaded on the rising edge of
clock 17.
CLKMODE = 1

PIPES = 010

C CC
LOa PP
K NN I I
M FF PP
a I I EE
D GG SS
E 1-02-0

1 I
0-0
001 011 0 101 x
2

3

Operation: SQRT A(wr)

SS
EE
LL

00
PP
7-0

RR
NN
DD
1-0

1 10 01 0 111 1 1 1 1 1 00
4

5

6

7

8

S
E
L
M
S S
BEE R
S
Y L L EH
FEE S /
OOOTSSSATT
ANNR
SRRCLEEEETT ELPP
TAB C S Y C S P 1 -0 T T 1-0
0 1 1 x x 0 0 0 x 11

9 10 11 12 13 14 15

16

1 1 11

17

elK

INST

UNDETERMINED
I

~----.-'I

I

I

r+*"th1

>-__________________U_N~D~E_T~ER~M_I~NE~D________________~:@SQUARE
I I

ROOT

I I
--+I I+- tpd4

Figure 40. Double-Precision Floating Point Square Root
IPIPES2-PIPESO = 010)

7-117

All registers are enabled in the fourth example, which calculates SORT A. Using clock
mode 0, the next double precision operation may be loaded on the fifteenth and
sixteenth rising clock edges. A single precision operat\on would load on the sixteenth
clock. The output is available after the sixteenth rising clock edge and may only be
valid for that cycle (see Figure 41).

a

CLKMODE =

PIPES = 000

Operation: SORT A

1 I
0-0

C
L
K
M
0
D
E

CC
00
NN
FF
II
GG
1-0

001 0110 100x

a

01 000 1111 1111 00

4

5

2

3

6

PP
I I
PP
EE
SS
2-0

7

SS
EE
LL
00
PP
7-0

8

RR
NN
DD
1-0

S
E
L
M
S S
BEE R
S
FEE S /
Y L L EH
OOOTSSSATT
ANNR
SRRCLEEEETTELPP
TAB C S Y C S P 1 -0 T T 1-0

a

aaa

1 1 x x

9 1011 121314 15

x 11

1 1 11

17

16

elK

I
INST

UNDETERMINED

NEXT lOP)

I
,
I '-----....,.JI

1+-+1- tsu 1

I

V

I
I
I
I

I

I

I

t h1

y~~______________~U_N_D_ET_E~R_M_IN~E~D________________-+l_®sauARE
I

I

ROOT

I I

-+I \4-t pd4
Figure 41. Double-Precision Floating Point Square Root
(PIPES2-PIPESO = 000)

7-118

Integer Square Root
The following example microinstructions perform square root operations on single
precision integer operands. Absolute values and negated results are not valid options
for integer calculations. Each example includes a timing diagram for a different setting
of the internal register controls (PIPES2-PIPESO).
The first instruction performs the square root of an unsigned integer with only the
RA and RBinput registers enabled. The output is available after the nineteenth rising
clock edge and may only be valid for that cycle. The next instruction may be loaded
on the twentieth rising edge.
CLKMODE

= 0

PIPES

= 110

C CC
L 00 P P
KNN I I
M FF PP
0 II EE
o GG SS
E 1-02-0

1 I
0-0
010 1100 OOOx
2

3

0 01
4

5

Operation: SQRT A

SS
EE
LL
00
PP
7-0

S
E
L
M
S S
S
BEE R
RR FEE S /
Y L L EH
NN ANNR
555TSS SATT
DO SRRCLEEEETT E L P P
1-0 TAB C S Y C S P 1 -0 T T 1-0

110 11111111 00
6

7

8

0 1 1 x x 0 0 0 x 11

9 1011 12131415161718

19

1 1 11
20

elK

INST

~
,

I

I

e-'

UNDETERMINED

SQUARE ~---------"';"';';'-"';=';';;';'~------I--_,
ROOT "

~th1

~I

,

I

tsu1-1+-+{
,
th 1-*+1

i+-+I- tsu 1

Y

NEXT

I

UNDETERMINED

@-SQUARE'''''''
I

I

o:::t

ROOT

I ,
-+I

00
00

*- tpd3

.....

u

Figure 42. Integer Square Root
(PIPES2-PIPESO = 110)

«
o:::t
,.....
2

en

7·119

Enabling the multiplier pipeline register (PIPES2-PIPESO = 100) in the second example
allows the next instruction to be loaded one cycle earlier, on the nineteenth clock.
The output will be valid after the nineteenth rising clock edge. (See Figure 43).
CLKMOOE = 0

PIPES = 100

CCC
L 00 P P
KNN I I
M FF PP
0 II E E
oGG SS
E 1-02-0

1 I
0-0

010 1100000x 001
2

3 4

5

Operation: SQRT A

SS
EE
LL
00
PP
7-0

RR
NN
DO
1 -0

1001111111100
6

7

8

S
E
L
M
S S
BEE R
S
FEE S /
Y L L EH
ANNR
555TSSSATT
SRRCLEEEETT ELPP
TAB C S Y C S P 1 -0 T T 1-0
011 x x 000 x 11

20

19

9 1011 12131415161718

1111

elK

e'>-,----r§I

INST

~
,

I
I

y

UNDETERMINED

SQUARE .------------------~I
ROOT I

I

14-+1- tsu 1

~~Y'

NEXT

tsu 1-14--+1

UNDm~N'D

-+I
Figure 43. Integer Square Root
(PIPES2-PIPESO =100)

7-120

I

I+--tpd3

The third example instruction performs SORT A on a two's complement integer
operand. With both input and output registers enabled (PIPE2-PIPEO = 010), the output
is valid after the twentieth rising clock edge. The next instruction may be loaded on
the twentieth clock.
CLKMODE = 0

PIPES = 010

C
L
K
M
0
D
E

1 I
0-0
010 0100 OOOx
2

CC
00
N N
FF
II

PP
I I
PP
EE
GG SS
1-02-0

o 01

3 4

5

Operation: SORT A

SS
EE
LL
00
PP
7-0

S
E
L
M
S

RR
NN
DD
1-0

01011111111 00

S S
BEE R
Y L L EH
FEE S I
555TSSSATT
ANNR
SRRCLEEEETTELPP
TAB C S Y C S P 1 -0 T T 1-0

o1

1 x xOOOx 11

6 7 8 91011 12131415161718

19

1 1 11

20

elK
I
INST

I

~
1
I
I

UNDETERMINED

I

1

I
:

i+-+I- t h1

NEXT )-1- - -

I
**-th1
J

i+-+j- t su1

'+-*-t su 1

y

8

SQUARE ~--------':"""';-"":"----------000004:
ROOT I

.~~___________....:..U~ND~E~T~E~RM~IN~E~D____________~i:~
~

J4-tpd4

Figure 44. Integer Square Root
(PIPES2-PJPESO = 010)

"

~

00
00
I-

U

«
~

z"

en

7-121

The final example shows SORT A with all registers enabled. The next instruction may
be loaded on the nineteenth rising clock edge, but the output will not be available until
after the twentieth rising .clock.

= 0

CLKMODE

PIPES

= 000

CCC
L 00 P P
K NN I I
M FF PP
0 II E E
D GG SS
E 1-02-0

1 I
O~O

0100100 OOOx
2

3 4

Operation: SORT A

SS
EE
LL
00
PP
7-0

RR
NN
DD
1-0

0 01 000 1111 1111 00

S
E
L
M
S S
S
BEE R
FEE S I
Y L L EH
ANNR
555TSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1 -0 T T 1-0
0 1 1 x x 0 0 0 x 11

5 6 7 8 9 1011 1213141516 17 18

19

1 1 11

20

elK

INST

UNDETERMINED

~__________________U~N~D~E~T~ER~M~I~N~ED~______________~@-SQUARE

-.I
Figure 45. Integer Square Root
(PIPES2-PIPESO = 000)

7~122

I
ROOT
I
I4-tpd4

Chained Multiplier!ALU Operations
Simultaneous multiplier and ALU functions can be selected in chained mode to support
calculation of sums of products or products of sums. Operations selectable in chained
mode overlap partially with those selectable in independent multiplier or ALU operating
mode. Format conversions, absolute values, and wrapping or unwrapping of denormal
numbers are not available in chained mode.
To calculate sums of products, the FPU can operate on external data inputs in the
multiplier while the ALU operates on feedback from the previous calculation. The
operand selects SELOPS7-SELOPSO can be set to select multiplier inputs from the
RA and RB registers and ALU inputs from the P and S registers.
The sample microinstruction sequence shown in Tables 36 and 37 performs the
operations for multiplying sets of data operands and accumulating the results, the basic
operations involved in computing a sum of products.
Table 36 represents the operations, clock cycles, and register contents for a singleprecision sum of four products. Registers used include the RA and RB input registers
and the product (P) and sum (S) registers.

Table 36. Single-Precision Sum of Products (PIPES2-PIPESO ... 010)
CLOCK
CYCLE
1

MUL TlPLIER/ALU
OPERATIONS
Load A, B

*

2

A
B
Pass P(AB) to S
Load C, D

3

C
D
S(AB) + P(CD)
Load E, F

4

E
F
S(AB + CD)
Load G, H

*

+ P(EF)

*

6

New Instruction

P(AB) + 0 -+ S(AB)
E ..... RA, F ..... RB
C
D -+ P(CD)
S(AB) + P(CD) ..... S(AB
G -+ RA, H ..... RB
F ..... P(EF)
E

*

*

G
H
S(AB + CD) + EF)

A -+ RA, B -+ RB

C -+ RA, D -+ RB
B -+ P(AB)
A

*

5

PSEUDOCODE

+ P(GH)

*
*

S(AB + CD) + P(EF)
G
H -+ P(GH)
S(AB

-+

+ CD)

S(AB

+ CD + EF)

+ CD + EF) + P(GH) ..... S(AB + CD + EF + GH)

A microcode sequence to generate this sum of product is shown in Table 37. Only
three instructions in chained mode are required, since the multiplier begins the
calculation independently and the ALU completes it independently.

'"o:t

OJ
OJ
I-

~
o:t

'"

2

en

7-123

Table 37. Sample Microinstructions for Single-Precision Sum of Products

S
E
C CC

L

L 00 pp
K NN I I

I I
9-0

00
10
10
10
00

0100
0110
0000
0000
0000

0000
0000
0000
0000
0000

xx xxxx xxxx

SS
EE
LL

M FF pp
0 II EE

00

D GG SS
E 1-0 2-0

7-0

a
a
a
a
a

01
01
01
01
01

x xx

pp

M

S
RR F E E S
NN ANN R
DD S R R C
1-0 T A B C

010 1111 xxxx 00
010 1111 xxxx 00
010 11111010 00
010 xxxx 1010 00
010 xxxx 1010 00

xxx

xxxx xxx x xx

a
a
a
a
a

x
x
x
x
x x x
x x x x
1

B
I
Y
000 T
LEE E E
S yes p
x
x
x
x
x
X

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

aa a

x
x
x
x
x
x

S S
EE
LL
SS
TT
1-0

R
EH
SAT T
E L pp
T T 1-0

xx
xx
xx
xx
xx
xx

1 1 11
1 1 11
11
11
11
11

Fully Pipelined Double-Precision Operations
Performing fully pipelined double-precision operations requires a detailed understanding
of timing constraints imposed by the multiplier. In particular, sum of products and
product of sums operations can be executed very quickly, mostly in chained mode,
assuming that timing relationships between the ALU and the multiplier are coded
properly.
Pseudocode tables for these sequences are provided, (Table 38 and Table 39) showing
how data and instructions are input in relation to the system clock. The overall patterns
of calculations for an extended sum of products and an extended product of sums
are presented. These examples assume FPU operation in CLKMODE 0, with the CONFIG
setting HL to load operands by MSH and LSH, all registers enabled
(PIPES2 - PIPESO = LLL), and the C register clock tied to the system clock.

(J)

2

~

In the sum of products timing table, the two initial products are generated in
independent multiplier mode. Several timing relationships should be noted in the table.
The first chained instruction loads and begins to execute following the sixth rising
edge of the clock, after the first product P1 has already been held in the P register
for one clock. For this reason, P1 is loaded into the C register so that P1 will be stable
for two clocks.

l>

("') On the seventh clock, the ALU pipeline register loads with an unwanted sum, P1 + P1.
-f However, because the ALU timing is constrained by the multiplier, the S register will

CO
CO not load until the rising edge of CLK9, when the ALU pipe contains the desired sum,
~ P1 + P2. The remaining sequence of chained operations then execute in the desired
'-J
manner.

7-124

Table 38. Pseudocode for Fully PipelinedDouble-Precision Sum of Products t
(CLKM=O, CON FIG = 10, PIPES ... OOO, CLKC-SYSCLK)

ClK

DA
BUS

DB
BUS

-;-'
~

(J"I

INS
BUS

INS
REG

RA
REG

RB
REG
B1

MUl
PIPE

P

C

REG

REG

AlU
PIPE

S

y

I

REG BUS,

I1
Iz
I3
I4
I5

A1 *B1

A1

A2 MSH B2 MSH A2,B2MSH A2*B2 A1 *B1

Al

B1

A1 *B1

B2 LSH A2,B2MSH A2*B2 A2*B2

A2

B2

A1 *B1

A2

B2

A2*B2

P1

I6

A3 LSH

A3

B3

A2 *B2

P1

P1

I7

A4 MSH B4 MSH A4,B4MSH

A3

B3

A3*B3

P2

P1

P1 +P1

Is

A4 LSH

A4

B4

A3*B3

P2

P1

Pl +P2

I9

A5 MSH B5 MSH A5,B5MSH

A4

B4

A4*B4

P3

P2

S1 +P2

S1

Sio

A5 LSH

A5

B5

A4*B4

P3

P3

S1 +P3

S1

..111

A6 MSH B6 MSH A6,B6(M)

A5

B5

A5*B5

P4

P3

XXXXX

S2

A1 MSH B1 MSH A1,B1MSH Al *B1
A1 LSH

A2 LSH

B1 LSH A 1,B1 MSH A1 *B1

i

PR+CR
A3 MSH B3 MSH A3,B3MSH

B3 LSH A3,B3MSH

B4 LSH A4,B4MSH

B5 LSH A5,B5MSH

..112

N

TEMP
REG

tpR = Product Register
SR = Sum Register
CR = Constant (C) Register

SN74ACT8847

A3*B3

A2*B2

PR+CR PR+CR,
A3*B3 A3*B3
PR+SR PR+SR,
A4*B4 A3*B3
PR+SR PI'l+SR,
A4*B4 A4*B4
PR+SR PR+SR,
A5*B5 A4*B4
PR+SR PR+SR,
A5*B5 A5*B5
PR+SR PR+SR,
A6*B6 A5*B5

L1788.L3"'17LNS
-;J

Table 39. Pseudocode tor Fully Pipelined Double-Precision Product of Sums t
(CLKM = 0, CON FIG = 10, PIPES = 000, CLKC-SYSCLK)

~

N

en

eLK

I1
I2
I3
I4
I5

DA
BUS

BUS

TEMP
REG

INS
BUS

A11MI

B11MI

A1,B1IMI

A 1 + B1

A 11LI

B11LI

A1,BlIMI

A2.IMI

B2IM)

A2,B2IM)

A21Li

B21Li

A2,B2IM)

DB.

A3IM)

B3IM)

A3,B3IM)

I6

A31LI

B31Li

A3,B3IM)

I7

XXX

XXX

XXX

Is

A4IM)

B4IM)

A4,B4IM)

I9

A41LI

B4IL)

A4,B4IM)

Sio

XXX

XXX

XXX

Si1

A5IM)

B5IM)

A5,B5IM)

J12

A5IL)

B5IL)

A5,B5IM)

NOTE:
t PR =
SR =
CR =

INS
REG

RA
REG

RB
REG

A 1 + B1

A 1 +B1

A1

B1

A2+B2

A 1 +B1

A1

B1

A1 +B1

A2+B2

A2+B2

A2

B2

A 1 + B1

51

A2+B2

51

51

A2+B2

52

51 *52

51

A3+B3

52

51 *52

51

A3+B3 XXX

CR*5R
A3+B3

A2+B2

CR*5R CR*5R
A3+B3
NOP
PR*5R
A4+B4

A3+B3
CR*5R
A3+B3
NOP

PR*5R

PR*5R

A4+B4

A4+B4

NOP
PR*5R
A5+B5

PR*5R
A4+B4
NOP

PR*5R

PR*5R

A5+B5

A5+B5

NOP instruction is 011 0000 0000.
Product Register
Sum Register
Constant (C) Register

A2

B2

A3

B3

A3

B3

ENRA =L ENRB = l

MUL
PIPE

P

C

REG

REG

ENRC=L
51

ALU
PIPE

S

A3

B3

A4

B4

XXX

P1

51

XXX

53

A4

B4

P1 *S3

P1

51

A4+B4

53

51

A4+B4 XXX

ENRA =L ENRB=L
A4

B4

A5

B5

P1 *53 XXX

XXX

P2

51

X

Y

REG BUS

54

In the product of sums timing table, the two initial sums are generated in independent
ALU mode. The remaining operations are shown as alternating chained operations
followed by NOPs (no operations). The NOPs are necessary to provide an extra cycle
during which the multiplier outputs the current intermediate product. The current sum
and the latest intermediate product are then fed back to the multiplier inputs for the
next chained operations .. In this manner a double-precision product of sums is generated
in three system clocks, as opposed to two clocks for a double-precision sum of
products.

Mixed Operations and Operands
Using mixed-precision data operands or performing sequences of mixed operations
may require adjustments in timing, operand precision, and control settings. To simplify
microcoding sequences involving mixed operations, mixed-precision operands, or both,
it is useful to understand several specific requirements for mixed-mode or mixedprecision processing.
Calculations involving mixed-precision operands must be performed as double-precision
operations. The instruction settings (18-17) should be set to indicate the precision of
each operand from the RA and RB input registers. (Feedback operands from internal
registers are also double-precision.) Mixed-precision operations should not be performed
in chained mode.
Timing for operations with mixed-precision operands is the same as for a corresponding
double-precision operation. In a mixed-precision operation, the single-precision operand
must be loaded into the upper half of its input register.
Most format conversions also involve
single- and double-precision floating
operations. During integer to floating
loaded into the upper half of the RA

double-precision timing. Conversions between
point format are treated as mixed-precision
point conversions, the integer input should be
register.

In applications where mixed-precision operations is not required, it is possible to tie
the 18-17 instruction inputs together so that both controls always select the same
precision.
Sequences of mixed operations may require changes in multiple control settings to
deal with changes in timing of input, execution, and output of results. Figure 46 shows
a simplified timing waveform fora series of mixed operations:

,.....

~
00

JU

«o:::t

,.....
Z

(/)

7·127

CLOCK CYCLE

FUNCTION
AND DATA

A,B

2

3

4

A,B

C,D

C,D

RESULTS
AND STATUS

XXXX A,B

5

xxx X

6

7

8

9

10

11

12

E,F

G,H

G,H

I,J

I,J

K,L

M,N

C,D

E,F

E,F

G,H

G,H

I.J

K,L

13

M,N

A,B,C,D - double precIsion multiply; E,F - single precIsion operation; G,H,I,J - double
precision add; K,L - single precision opration. A double precision number is not required to
be held on the outputs for two cycles unless it is followed by a like double precision function.
If a double precision multiply is followed by single precision operation, there must be one open
clock cycle.

Figure 46. Mixed Operations and Operands
(PIPES2-PIPESO == 110, CLKMODE = 01
In this sequence, the fifth cycle is left open because a single-precision multiply follows
a double-precision mUltiply. If the SP multiply were input during the period following
the fourth rising clock edge, the result of the preceding operation would be overwritten,
since an SP multiply executes in one clock cycle. To avoid such a condition, the FPU
will not load during the required open cycle.
Because the sequence of mixed operations places constraints on output timing, only
one cycle is available to output the double-precision (C
DI result. By contrast, the
SP multiply (E
F) is available for two cycles because the operation which follows
it does not output a result in the period following the seventh rising clock edge .. In
general, the precision and timing of each operation affects the timing of adjacent
operations.

*

*

Control settings for CLKMODE and registers must also be considered in relation to
precision and speed of execution. In Figure 47, a similar sequence of mixed operations
is set up for execution in fully pipelined mode:
CLOCK CYCLE

2

en

:2

"l>
~

FUNCTION
AND DATA
RESULTS
AND STATUS

A,B

3
C.D

4

5

6

7

8

9

10

E,F

G,H

I,J

K.L

M,N

Q,P

A,B

A.B

C,D

E,F

G.H

I,J

11

12

13

Q,R
K.L

M,N

M.N

("')

-I
CO
CO
~

"

A,B,C,D - double precision multiply; E,F - single precision operation; G,H, - double precision
add; I,J,K,L,M,N - single precision operation; O,P,Q.R - double precision multiply. In clock
mode 1. a double precision result is two cycles long only when a double precision multiply is
followed by a double precision mUltiply.

Figure 47. Mixed Operations and Operands
(PIPES2"PIPESO == 000, CLKMODE = 11

7-128

Although the data operands can be loaded in one clock cycle with CLKMODE set high,
B) result one cycle beyond
enabling two additional internal registers delays the (A
the previous example. Again, an open cycle is required after the (C
D) operation
because the next operation is single precision. The result of the (C
D) multiply is
available for one cycle instead of two, also because the following operation is single
precision. With this setting of CLKMODE and PIPES2-PIPESO, a double-precision result
is only available for two clock cycles when one DP multiply follows another DP mUltiply.

*

*
*

Matrix Operations
The' ACT884 7 floating point unit can also be used to perform matrix manipulations
involved in graphics processing or digital signal processing. The FPU multiplies and
adds data elements, executing sequences of microprogrammed calculations to form
new matrices.

Representation of Variables
In state representations of control systems, an n-th order linear differential equation
with constant coefficients can be represented as a sequence of n first-order linear
differential equations expressed in terms of state variables:
dx(n -1)
= xn
dt
For example, in vector-matrix form the equations of an nth-order system can be
represented as follows:
dx1
-cit

d
dt

xl
x2

a 11

=

x 2, ... ,

a1n

a12

b11

rn
:

xn

an1

=

ax + bu

or, X

~

b1n

x2

an2

ann

u2

+

xn

bn1

bnn

un

Expanding the matrix equation for one state variable, dx1/dt, results in the following
expression:
X1 = (a11
where X1

=

*

x1

+

+

a1n

*

xn)

+

(b11

*

u1

+ ... +

b1n

*

un)

,....

~

(X)
~

U

«

~
,....

dx1/dt.

Z

(J)

7-12.9

Sequences of multiplications and additions are required when such state space
transformations are performed. and the' ACT884 7 has been designed to support such
sum-of-products operations. An n x n matrix A multiplied by an n x n matrix X yields
an n x n matrix C whose elements cij are given by this equation:
n

cij

=

E

aik

* xkj

for i = 1 •...• n

j = 1 •...• n

(1 )

k=1
For the cij elements to be calculated by the' ACT884 7. the corresponding elements
aik and xkj must be stored outside the' ACT884 7 and fed to the •ACT884 7 in the
proper order required to effect a matrix multiplication such as the state space system
representation just discussed.

Sample Matrix Transformation
The matrix manipulations commonly performed in graphics systems can be regarded
as geometrical transformations of graphic objects. A matrix operation on another matrix
representing a graphic object may result in scaling. rotating. transforming. distorting.
or generating a perspective view of the image. By performing a matrix operation on
the position vectors which define the vertices of an image surface. the shape and
position of the surface can be manipulated.
The generalized 4 x 4 matrix for transforming a three-dimensional object with
homogeneous coordinates is shown below:

a
e

b

m

n

c
g
k

T

d
h
I

• . o.

0

p

The matrix T can be partitioned into four component matrices. each of which produces
a specific effect on the resultant image:
(J)

2:
-....I
~

l>

3

(")

3 x 3

-4

00
00

x

..

~

1 x 3

-....I

7-130

1 x 1

The 3 x 3 matrix produces linear transformation in the form of scaling, shearing and
rotation. The 1 x 3 row matrix produces translation, while the 3 x 1 column matrix
produces perspective transformation with multiple vanishing points. The final single
element 1 x 1 produces overall scaling. Overall operation of the transformation matrix
T on the position vectors of a graphic object produces a combination of shearing,
rotation, reflection, translation, perspective, and overall scaling.
The rotation of an object about an arbitrary axis in a three-dimensional space can be
carried out by first translating the object such that the desired axis of rotation passes
through the origin of the coordinate system, then rotating the object about the axis
through the origin, and finally translating the rotated object such that the axis of rotation
resumes its initial position. If the axis of rotation passes through the point P = [a b c1 L
then the transformation matrix is representable in this form:

[x y z

hJ

[x y z 1 J

1

a
a
-a

a
1

a
-b

a a
a a
1 a
-c

I
translation
to origin

1

a a
a 1 a
a a
1

G
I
rotation
about
origin

a

b

a
a
a

(2)

c

translation
back to initial
position

,....
~

00
00
IU

«~

,....
Z

en

7-131

where R may be expressed as:

R

n12 + (1-n)2 cos

n 1n2( l-cos

n 1 n3( l-cos

0

n 1n2( l-cos

n22 + (1-n2)2 cos

n2n3(1-cos

0

n 1 n3( l-cos

n2n3( 1-cos

n3 2 + (1-n3)2 cos

0

o
and

n1

=

o

o

q1/(q1 2 + q22 + q3 2 )1/2

direction cosine for x-axis of
rotation

n2 = q2/(q1 2 + q2 2 +q3 2 )1/2

direction cosine for y-axis of rotation

n3 = q3/(q1 2 + q2 2 + q3 2 ) 1 /2 = direction cosine for z-axis of rotation

n=

(n1 n2 n3)

= unit vector for

Q

Q = vector defining axis of rotation = Iq 1 q2 q3]
 == the rotation angle about Q
A general rotation using equation (2) is effected by determining the Ix y z] coordinates
of a point A to be rotated on the object, the direction cosines of the axis of rotation
[n 1 ,n2, n31. and the angle  of rotation about the axis, all of which are needed to
define matrix [R]. Suppose, for example, that a tetrahedron ABeD, represented by
the coordinate matrix below is to be rotated about an axis of rotation RX which passes
through a point P = [5 - 6 3 1] and whose direction cosines are given by unit vector
[n1 = 0.866, n2 = 0.5, n3 = 0.707]. The angle of rotation 0 is 90 degrees (see
Figure 24). The rotation matrix [R] becomes

C/'J

2
1
2
2

Z

-...J

~

»
(")

-3

-2
-1
-2

3
2
2
2

A
B

C
D

-f
00
00
~

-...J

R

7-132

0.750
-0.274
1.112
0

1.140
0.250
-0.513
0

0.112
1.220
0.500
0

0
0
0

Y

z'

r-I

(2)1

+---- ----------,

DT

BT """'--AT

55°

a

I

111)

I
I

x'+-----------~~~~~~~4~5~0----------b~----------------~)X
I
CR
L_.-.
BR

I

DR

I

z

/ / 10 .. P'
,/
I
I
I
I C'

L-..!.3L_~'~D'

o

900

~ ·----~--"___:lr::.P (5,

/

-6, 31

I
I

I

Y'

(1) THIS ARROW DEPICTS THE FIRST TRANSLATION
(2) THIS MOW DEPICTS THE 90° ROTATION
(31 THIS ARROW DEPICTS THE BACK TRANSLATION

Figure 48. Sequence of Matrix Operations
The point transformation equation (2) can be expanded to include all the vertices of
the tetrahedron as follows:
xa
xb
xc
xd

va
vb
vc
Vd

za
zb
zc
zd

3 1
1 -2 2 1
2 -1 2 1
2·~3

2 -2 2 1

h1
h2
h3
h4

1 0 00
0.750 1.140 0.112 0 1 000
01 00 -0.274 0.250 1.22 0 0 100
1.112 -0.513 0.5000 0 010
00 1 0
-56-31
1 5-6 3 1
0
0
0

I
translation
to origin

I

I

rotation about origin

translation
back to
initial
position

"

"'0000"

(3)

IU

«

"ZtfJ"'"
7-133

The 'ACT884 7 floating-point unit can perform matrix manipulation involving
multiplications and additions such as those represented by equation (1). The matrix
equation (3) can be solved by using the' ACT884 7 to compute, as a first step, the
product matrix of the coordinate matrix and the first translation matrix of the righthand side of equation (3) in that order. The second step involves postmultiplying the
rotation matrix by the product matrix. The third step implements the back~translation
by pre multiplying the matrix result from the second step by the second translation
matrix of equation (3). Details of the procedure to produce a three-dimensional rotation
about an arbitrary axis are explained in the following steps:
Step 1
Translate the tetrahedron so that the axis of rotation passes through the origin. This
process can be accomplished by multiplying the coordinate matrix by the translation
matrix as follows:

2
1
2

-3
-2
-1

3
2
2

1

0

0
0

1

0
0
1

2

-2

2

-5

0
6

0
0
0

-3

1

(-3+6)
(-2+6)
(-1 +6)
(-2+6)

(3-3)
(2-3)
(2-3)
(2-3)

I

I

translation
to origin

vertices of translated
tetrahedron

-3
-4
-3
-3

7 c 134

(2-5)
(1 - 5)
(2-5)
(2-5)

+3
+4
+5
+4

0
-1
-1
-1

AT
BT
CT
DT

1
1
1
1

The' ACT8847 could compute the translated.coordinates AT, BT, CT, DT as indicated
above. However, an alternative method resulting in a more compact solution is
presented below.
Step 2
Rotate the tetrahedron about the axis of rotation which passes through the origin after
the translation of Step 1. To implement the rotation of the tetrahedron, postmultiply
the rotation matrix [R] by the translated coordinate matrix from Step 1. The resultant
matrix represents the rotated coordinates of the tetrahedron about the origin as follows:

-3
-4
-3
-3

3
0
4 -1
5 -1
4 -1

1
1.140 0.112 0
0.750
1 -0.274
0.250 1.22 0
1
1.112 -0.513 0.500 0
1
1
0
0
0

-3.072 -2.670
-5.208 -3.047
-4.732 - 1.657
-4.458 -1.907

3.324
3.932
5.264
4.044

1
1
1
1

I
rotation about origin

rotated coordinates

Step 3
Translate the rotated tetrahedron back to the original coordinate space. This is done
by premultiplying the resultant matrix of Step 2 by the translation matrix. The following
calculations produces the final coordinate matrix of the transformed object:

-3.072
-5.208
-4.732
-4.458

- 2.670
-3.047
-1.657
-1.907

3.324
3.932
5.264
4.044

1
1
1
1

1 0
1
0
0
0
5 -6

0
0
1
3

0
0
0

1.928
-0.208
0.268
0.542

- 8.670 6.324
-9.047 6.932
-7.657 8.264
-7.907 7.044

I

I

translate back

final rotated coordinates

,....

~

CO
CO

....
«

(,)
~

,....

2

CJ)

7-135

A more compact solution to these transformation matrices is a product matrix that
combines the two translation matrices and the rotation matrix in the order shown in
equation (3). Equation (3) will then take the following form:

xa
xb
xc
xd

va
Vb
VC
Vd

za
zb
zc
zd

h1
h2
h3
h4

2
1
2
2

-3
-2
-1

3
2
2

-2

2

0.750
-0.274
1.112
-3.730

1.140
0.250
-0.513
- 8.661

0.112
1.220
0.500
8.260

I
transformation matrix

7-136

0
0
0
1

The newly transformed coordinates resulting from the postmultiplication of the
transformation matrix by the coordinate matrix of the tetrahedron can be computed
using equation (1) which was cited previously:
n

cij =

E aik * xkj

for i = 1, ... ,n

j = 1, ... ,n

(1 )

k=l
For example, the coordinates may be computed as follows:
xa

= cll

all * xll + a12 * x21 + a13 * x31 + a14 * x41
2 * 0.750 + (-3) * (-0.274) + 3 * 1.112 + 1 * (-3.73)
1.5 + 0.822 + 3.336 - 3.73
1.928

ya

= c12

all * x12 + a12* x22 + a13 * x32 + a14 * x42
2 * 1.140 + (-3) * 0.250 + 3 * (-0.513) + lx(-8.661)
2.28 -0.75 - 1.539 - 8.661
-8.67

za = c13

h1

= c 14 =

----+

all * x13 + a12 * x23 + a13 * x33 + a14 *x43
2 * 0.112 + (-3) "* 1.220 + 3 * 0.500 + 1 * 8.260
0.224 - 3.66 + 1.5 + 8.260
6.324
a 11 * x 14 + a 1 2 * x24 + a 13 * x34 + a 14 * x44
2 * 0 + (- 3) * 0 + 3 * 0 + 1 * 1
0+0 +0 + 1
1

A'

=

[1.928 - 8.67 6.324 1 J

The other rotated vertices are computed in a similar manner:
8' = [- 5.208 - 3.047 3.932 1 J
C' = [- 4. 732 - 1.657 5.264 1)
0' = [- 4.458 - 1. 907 4.044 1 J

"

'!:t
00
00
lt)

«'!:t

Microinstructions for Sample Matrix Manipulation
The 'ACT884 7 FPU can compute the coordinates for graphic objects over a broad
dynamic range. Also, the homogeneous scalar factors hl, h2, h3 and h4 may be made
unity due to the availability of large dynamic range. In the example presented below,
some of the calculations pertaining to vertex A' are shown but the same approach
can be applied to any number of points and any vector space.
7-137

"en2

The calculations below show the sequence of operations for generating two
coordinates, xa and ya, of the vertex A' after rotation. The same sequence could be
continued to generate the remaining two coordinates for A' (za and h1). The other
vertices of the tetrahedron, B', C', and D', can be calculated in a similar way.
A microcode sequence to generate this matrix multiplication is shown in Table 40.
Table 41 presents a pseudocode description of the operations, clock cycles, and register
contents for a single-precision matrix multiplication using the sum-of-products sequence
presented in an earlier section. Registers used include the RA and RB input registers
and the product (P) and sum (S) registers.
Table 40. Microinstructions for Sample Matrix Multiplication

I I
10-0

~
.....,J

+:>

C
L
K
M
0
D
E

CC
00
N N
FF
II
GG
1-0

PP
I I
PP
EE
SS
2-0

SS
EE
LL
00
PP
7-0

RR
NN
DD
1-0

S
E
L
M
S S
BEE R
S
Y L L EH
FEE S /
ANNR
OOOTSSSATT
SRRCLEEEETTELPP
TAB C S Y C S P 1-0 T T 1-0

000
100
100
100
100

0100 0000 a
a11 a 0000 a
0000 0000 a
0000 0000 a
0000 0000 a

01
01
01
01
01

0101111
0101111
0101111
0101111
0101111

x'Xxx
xxx x
1010
1010
1010

00
00
00
00
00

a
a
a
a
a

1

100
100
100
100
100

a11 a 0000 a
0000 0000 a
0000 0000 a
0000 0000 a
0110 0000 a

01
01
01
01
01

0101111 xxxx
01011111010
01011111010
0101111 1010
10 1111 xxx x

00
00
00
00
00

a
a
a
a
a

1
1
1
1
1

a

1
1

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

xx
xx
xx
xx
xx

11
11
11
11
11

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

xx
xx
xx
xx
xx

11
11
11
11
11

Six cycles are required to complete calculation of xa, the first coordinate, and after
four more cycles the second coordinate ya is output. Each subsequent coordinate can
be calculated in four cycles so the 4-tuple for vertex A' requires a total of 18 cycles
to complete.

:t>

Calculations for vertices B', C', and D', can be executed in 48 cycles, 16 cycles for
each vertex. Processing time improves when the transformation matrix is reduced,
-I
00 i.e., when the last column has the form shown below:
00

n

+:>

.....,J

7-138

Table 41. Single-Precision Matrix Multiplication (PIPES2-PIPESO
CLOCK
CYCLE

MULTlPLIER/ALU
OPERATIONS

=

010)

PSEUDOCODE

2

Load a12, x21
SP Multiply
Pass P to S

all .... RA, xll .... RB
pl = all
xll
a12 .... RA, x21 .... RB
p2 = a12
x21
pl .... P(pl)

3

Load a13, x31
SP Multiply
Add P to S

a13 .... RA, x31 .... RB
p3 = a13
x31, p2 .... P(p2)
P(pl) + 0 .... S(pl)

4

Load a14, x41
SP Multiply
Add P to S

a14 .... RA, x41 .... RB
p4 = a14
x41, p3 .... P(p3)
P(p2) + S(p1) .... S(pl + p2)

5

Load all , xl 2
SP Multiply
Add P to S

all .... RA,x12 .... RB
p5 = all
x12, p4 .... P(p4)
P(p3) + S(pl + p2) .... S(pl + p2 + p3)

6

Load a12, x22
SP Multiply
Pass P to S
Output S

a12 .... RA, x22 .... RB
p6 = a12
x22, p5 .... P(p5)
P(p4) + S(pl + p2 + p3) ....
S(pl + p2 + p3 + p4)

7

Load a13, x32
SP Multiply
Add P to S
Load a 14, x42
SP Multiply
AddP to S

a 13 .... RA, x32 .... RB
p7 = 813
x32, p6 .... P(p6)
P(p5) + 0 .... S(p5)
a 14.... RA, x42 -RB
p8 = 814 * x42, p7 - P(p7)
P(p6) + S(p5)- S.(p5 + p6)

9

Next operands
Next instruction
Add P to S

A - RA, B - RB
pi = A
B, p8 - P(p8)
P(p7) + S(p5 + p6) - S(p5 + p6 + p7)

10

Next operands
Next instruction
Output S

C .... RA, 0 - RB
pj = C
D, pi - P(pi)
P(p8) + S(p5 + p6 + p7) S(p5 + p6 + p7 + p8)

Load all, xll
SP Multiply

8

*
*
*
*
*

*
*

*

*

The h-scalars h 1, h2, h3, and h4 are equal to 1 . The number of clock cycles to generate
each 4-tuple can then be decreased from 16 t013 cycles. Total number of clock cycles
to calculate all four vertices is reduced from 66 to 54 clocks. Figure 49 summarizes
the overall matrix transformation.

'"

.~
ex)

t;

<{
~

'"

2

en

7-139

y

Z'

x'--------------------~~~--------------~------------------~x

,0

,

I

Z

I
I
I

0

B

C'

.0

0'

B'

,,:A'

90°
P {5, -6,31

,I
Y'

Figure 49, Resultant Matrix Transformation

This microprogram canalso be written to calculate sums of products with (III pipelinlil
registers enabled so that the FPU can operate in its fastest mode. Because of timing
relationships, the C register is used in some steps to hold the intermlildiate sum of
products. Latency due to pipelining .and chained data manipulation is 11 cycllils for
calculation of the first coordinate, and four cycles each for the other three coordinates.
After calculation of the first vertex, 16 cycles are required to calculate the four
coordinates of each subsequent vertex. Table 42 presents the sequence of calculations
for the first two coordinates, xa and ya.

7-140

Table 42. Fully Pipelined Sum of Products (PIPES2-PIPESO == 000)
(Bus or Register Contents Following Each Rising Clock Edge)

CLOCK
CYCLE

I
BUS

OA
BUS

DB
BUS

I
REG

RA
REG

RB
REG

MUL
PIPE

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Mul
Mul
Chn
Mul
Chn
Chn
Chn
Chn
Chn
Chn
Chn
Chh
Chn
CM
Chn
Chn

xll
x21
x31
x41
x12
x22
x32
x42
x13
x23
x33
x43
x14
x24
x34
x44

all
a12
a13
a14
all
a12
a13
a14
all
a12
a13
a14
all
a12
a13
a14

Mul
Mul
Chn
Mul
Chn
Chn
Chn
Chn
Chn
Chn
Chn
Chn
Chn
Chn
Chn

xl1
x21
x31
x41
x12
x22
x32
x42
x13
x23
x33
x43
x14
x24
x34

all
a12
a13
a14
all
a12
a13
a14
all
a12
a13
a14
all
a12
a13

pl
p2
p3
p4
p5
p6
p7
p8
p9
pl0
pl1
p12
p13
p14

ALU
PIPE

51
t

52
53
54
xA
55
56
57
yA
58
59

P
REG

pl
p2
p3
p4
p5
p6
p7
p8
p9
pl0
pl1
p12
p13

S
REG

C Y
REG BUS

51

p2
p2
p2
52
p6
p6 xA
p6
s5
pl0
pl0 yA
pl0

t

52
53
54
xA,
55
56

57
yA
58

t Contents of this register are hot valid during this cycle,

Products in Table 42 are numbered according to the clock cycle in which the operands
and instruction were loaded into the RA, RS, and I register, and execution of the
instruction began. Sums indicated in Table 42. are listed below:

s1
s2
s3
s4

= p1 +
= p1 +
= p2 +
= p5 +

0
p3
p4
0

55 = p5 + p7
56 = p6 + p8
57 = p9 + 0
s8 = p9 + p11

s9

= p10 +

xA
yA

=

p12
+ p2 + p3 + p4
p5 + p6 + p7 + p8

=p1

,....
'lid'

CIO
CIO

....(.)
i
r~~--R

I,
I
1

P
N
M
L

I

K

1

J

35,6 (1.4001 REF H

I

L
,

G
F
E

D
C
B

-A

r--.

0,508 (0.0201-.11.0,406 (0.0161
DIA TYP

j

ll,27 (0.0501 NOM
DIA (4 PLACESI

~4---------------------~

2,54 (0.1001 T.P.
(See Note AI

000000000000000
000000000000000n
000000000000000
00000000000000.0
000000000000000
000000000000000
000000000000000 ALL POSSIBLE PIN LOCATIONS ARE
000000000000000 SHOWN. SEE APPLICABLE PRODUCT
SHEETS FOR ACTUAL PIN
.000000000000000 DATA
LOCATIONS USED.
000000000000000
000000000000000
000000000000000
000000000000000
0@0000000000000
000000000000000

...caca

o

"i
CJ

'cca

.c

CJ
CD

1 2 3 4 5 6 7 8 9101112131415

NOTE A: Pins are located within 0,13 (0.005) radius of true position relative to each other at
maximum material condition and within 0,381 (0.051) radius relative to the center of
the ceramic.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

9·9

~

15 x 15 GC pin grid array ceramic package

r ---

INDEX CORNER
MARK OR CHAMfER
1.2710.051.45°

40.1
11.580)
37.611.480)

-------l

--------5.72 (0.225)

~~I~=~n Ii,U.U1l 1~ ~J~~r'
I

2.54 (0.100)

LJ

llJLlr

0.406 (0.016)
OIA TYP

2.5410.1001 T.P.

r±--±--=--:-----.--------R

(See Note Al

000000t.
AZ 85021, (602) 995·, 007

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~~:~:~~T.eo~~ol~~t~uo~~~~ (~)o~~t6~~S:

PB106,

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1"

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8M

TEXAS

INSTRUMENTS

Erratum to SN74ACT8837 User's Guide
Format conversion from floating point to integer for numbers
between 1.111 ... 111 x 231 and 2 32 , when rounding up,
causes the resulting integer to go to zero without causing the
device to signal an overflow. This condition occurs whenever
rounding causes the integer operand to be incremented. If the
user anticipates that this condition may occur in a system being
designed, a software trap can be implemented to monitor correct
operation of the format conversion.

lJ1

TEXAS
INSTRUMENTS
Printed in U.S.A .

788 - 12

SCSS006A



---

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