1988_TI_Standard_TTL_Logic_Data_Book 1988 TI Standard TTL Logic Data Book
User Manual: 1988_TI_Standard_TTL_Logic_Data_Book
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•
TEXAS
INSTRUMENTS
TTL Logic
Standard TTL, Schottky,
Low-Power Schottky
1988
1988
The TTL Data Book
General Information
TTL Devices
Mechanical Data
The TTL Logic
Data Book
",
TEXAS
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to
discontinue any semiconductor product or service identified in this
publication without notice. TI advises its customers to obtain the latest
version of the relevant information to verify, before placing orders,
that the information being relied upon is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with Tl's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Unless mandated by government
requirements, specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability for TI applications assistance, customer product
design, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represent that any, license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or
relating to any combination, machine, or process in which such
semiconductor products or services might be or are used.
Specifications contained in this User's Guide supersede all data for
these products published by TI in the United States of America before
March 1988.
Copyright 1985, 1988, Texas Instruments Incorporated
Printed in the U.S.A.
Revised March 1988
SDLD001A
INTRODUCTION
In this volume, Texas Instruments presents pertinent technical information on our broad line of TTL integrated
circuits. You will find complete specifications on the following TTL products:
•
•
Standard
- Series
Schottky
- Series
- Series
TTL circuits
54/74
TTL circuits
54LS/74LS, Low-Power Schottky
54S/74S, Schottky
This edition is designed for ease of circuit selection with an alphanumerical index of devices in this book as
well as a functional index. The functional index includes all standard bipolar and CMOS logic device types available
or under development showing the available technologies for each type. Included in the functional index are
the following families of products:
•
•
•
•
••
Standard TTL
Schottky - S
Advanced Schottky - AS
Low-Power Schottky - LS
Advanced Low-Power Schottky - ALS
74F
•
••
•
•
High-speed CMOS - HC/HCT
Advanced CMOS Logic - AC/ACT
BiCMOS bus interface - BCT
Programmable Logic - TIBPAL
VLSI Processors
The general information section includes an explanation of the function tables, parameter measurement
information, and typical characteristics related to the TTL products listed in this volume.
Package dimensions given in the Mechanical Data section of this book are in metric measurement (and
parenthetically in inches) to simplify board layout for designers involved in metric conversion and new designs.
Complete technical data for any TI semiconductor/component products are available from your nearest TI field
sales office, local a~thorized TI distributor, or by writing direct to: Texas Instruments Incorporated, P.O. Box
809066, Dallas, Texas 75380-9066.
We sincerely hope you find the new Standard TTL Data Book a meaningful addition to your technical library.
/
vi
The TTL Data Book
General Information
1-1
Contents
Title
: . NUMERICAL ~NDEX ........................................................ .
Page
1-3
",
1-7
' FUNCTIONAL INDEX, , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .......... , ... ,
GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ............ , ....... .
-...
5'
o....
3t:»
c)"
~
1-2
1-39
EXPLANATION OF FUNCTION TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . , .......... , ... .
1-43
PARAMETER MEASUREMENT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-45
TYPICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-51
NUMERICAL INDEX
Device Type
SN5400
SN54LSOO
SN54S00
SN5401
SN54LSOI
SN5402
SN54LS02
SN54S02
SN5403
SN54LS03
SN54S03
SN5404
SN54LS04
SN54S04
SN5405
SN54LS05
SN54S05
SN5406
SN5407
SN5408
SN54LS08
SN54S08
SN5409
SN54LS09
SN54S09
SN5410
SN54LS10
SN54S10
SN54LSll
SN54S11
SN5412
SN54LS12
SN5413
SN54LS13
SN5414
SN54LS14
SN54LS15
SN54S15
SN5416
SN5417
SN5420
SN54LS20
SN54S20
SN54LS21
SN5422
SN54LS22
SN54S22
SN5423
SN5425
SN5426
SN54LS26
SN5427
SN54LS27
SN5428
SN54LS28
SN5430
SN54LS30
SN7400 ............... ,
SN74LSOO · , - .... ' ......
SN74S00 ... , ' , , . , , . , , , .
SN7401 . . . . . . . . . . . . . . . .
SN74LSOI . , " ' " .... ".
SN7402 ................
SN74LS02 · ........ , ' ...
SN74S02 ... , , , , . , , , . , , ,
SN7403 ..... , ... , .. , , ..
SN74LS03 ..............
SN74S03 . , , .... , , , . , , ..
SN7404 ..... , , , . , , , . , , .
SN74LS04 · . . . . . . . . . . . .
SN74S04 ... ' , , , . , , . ' , , ,
SN7405 .. , , , , . , . , , . , , ..
SN74LS05 ....... , ......
SN74S05 , , , , , , , , , , , , .. ,
SN7406 ................
SN7407 .. , . ' .... , , , , .. ,
SN7408 ................
SN74LS08 . , ' ...........
SN74S08 .. , , , , , . , , , . , , .
SN7409 . ......... ......
SN74LS09 .... .... ... ...
SN74S09 ......... ......
SN7410 .. , , .... , , , . ' , ..
SN74LS10 ..............
SN74S10 . , , , , , , . , , . , , , .
SN74LS11 " ...... , .....
SN74S11 ..... ..........
SN7412 .. , . ' . , , ' . , . , , , .
SN74LS12 ..............
SN7413 ."" , ... , ,., , ..
SN74LS13 ... .... .... ".
SN7414 ... , ..... , ,., , ..
SN74LS14 · .............
SN74LS15 · .............
SN74S15 , , , .... , ... ' ...
SN7416 .. , , ..... , .. , ...
SN7417 ..... ........ ...
SN74LSI9A" .... " . , .. ,
SN7420 ... , , .. , . , , . , ...
SN74LS20 · .............
SN74S20 . , , , , . , . , , . , ...
SN74LS21 .. ...... ......
SN7422 ................
SN74LS22 ..............
SN74S22 .. , ..... , .. ' , . ,
SN7423 , ' , , .. , , , .. , , .. ,
SN74LS24A , .... , , .. , , ..
SN7425 , , . , .. , , , , . , , . , ,
SN7426 . , . , ..... , .. , , ..
SN74LS26 ....... ... ....
SN7427 .. , , .... , , .. , , ..
SN74LS27 ..............
SN7528 .. , , , , , , . , , , , , , .
SN74LS28 ..............
SN7430 .. , , , .. , . , , , , , . ,
SN74LS30 ..............
.
Page No.
Device Type
2·3
2·3
2-3
2-9
2-9
2-13
2·13
2-13
2·19
2-19
2·19
2-25
2·25
2-25
2·31
2·31
2·31
2·37
2·39
2-41
2·41
2-41
2-47
2·47
2-47
2·53
2-53
2·53
2-59
2·59
2·63
2-63
2·67
2·67
2·77
2·77
2·87
2-67
2·37
2-39
2·91
2·95
2·95
2·95
2·101
2·105
2-105
2·105
2·111
2·91
2-111
2·115
2·115
2·119
2·119
2·123
2·123
2·127
2·127
SN54S30
SN54LS31
SN5432
SN54LS32
SN54S32
SN5433
SN54LS33
SN5437
SN54LS37
SN54S37
SN5438
SN54LS38
SN54S38
SN5439
SN5440
SN54LS40
SN54S40
SN5442A
SN54LS42
SN5445
SN5446A
SN5447A
SN54LS47
SN5448
SN54LS48
SN54LS49
SN5450
SN5451
SN54LS51
SN54S51
SN5453
SN5454
SN54LS54
SN54LS55
SN54LS56
SN54LS57
SN54S64
SN54S65
SN54LS68
SN54LS69
SN5470
SN5472
SN5473
SN54LS73A
SN5474
SN54LS74A
SN54S74
SN5475
SN54LS75
SN5476
SN54LS76A
SN5477
SN54LS77
SN54LS78A
SN5483A
SN54LS83A
SN5485
SN54LS85
SN54S85
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, "TEXAS 75265
Page No.
SN74S30 .... , , , , ..... , ,
SN74LS31 ..............
SN7432 .................
SN74LS32 · . . . . . . . . . . . . .
SN74S32 .. , ............
SN7433 , . , ... , , , .......
SN74LS33 . .............
SN7437 ...... , , , ..... , .
SN74LS37 ........... ' "
SN74S37 ....... , ..... , .
SN7438 ...... , , ' ..... , ,
SN74LS38 · . . . . . . . . . . . .
SN74S38 .. , , ' , , ' . , ... , ,
SN7439 ...... , , , , , , .. , .
SN7440 ... , , , , , , ..... , ,
SN74LS40 ..............
SN74S40 .. , , , , , , .......
SN7442A ..... , . ' . , , .. , .
SN74LS42 ..............
SN7445 , .. , .... ' . , , . , , .
SN7446A . , , , . , , . , , , , .. ,
SN7447A , , , , ... , , , , , , , .
SN74LS47 ..............
SN7448 " . , ............
SN74LS48 ..............
SN74LS49 . .............
SN7450 , . , , , .. , . , . , ' .. ,
SN7451 ................
SN74LS51 ........ - , ....
SN74S51 ..........
SN7453 , , ' . , .... , .. , ...
SN7454 , , ... ' , . ' , . , ' , , ,
SN74LS54 . .............
SN74LS55 ..............
SN74LS56 · .............
SN74LS57 · . . . . . . . . . . . . .
SN74S64 , . , ..... , .. , .. ,
SN74S65 , , , , ..... , . , , , ,
SN74LS68 . .............
SN74LS69 ..............
SN7470 , , ...... , , .. ' ...
SN7472 . ...............
SN7473 ................
SN74LS73A ...... , , . ' , , .
SN7474 ....
.........
SN74LS74A ...... , . , , , , ,
SN74S74 ' ... ' , . , , .. , , ..
SN7475 . ' , , , ' , , .. , , , , , ,
SN74LS75 · .............
SN7476 . , , , , , , . , . , , , , , ,
SN74LS76A , , ' , .. , , , , , , .
.
......................
......................
SN74LS78A , , , , , ' , , , . , , ,
SN7483A , , , , , , , , , , . , , . ,
SN74LS83A , , ' , ' , , , , , . , ,
SN7485 , .... , , , , , .. , , . ,
SN74LS85 ..............
SN74S85 .. , . ' , , , ' , . ' , ..
2·127
2-133
2-137
2-137
2-137
2·143
2-143
2-147
2-147
2-147
2-153
2·153
2·153
2·159
2·161
2·161
2·161
2·167
2·167
2·173
2-175
2·175
2-175
2-175
2-175
2-175
2·189
2-193
2·193
2-193
2-199
2-201
2-201
2-205
2-207
2-207
2-211
2·211
2-215
2·215
2-221
2·225
2·229
2·229
2·235
2·235
2-235
2·241
2-241
2·247
2-247
2·241
2-241
2-253
2-257
2·257
2·263
2·263
2-263
C
0
'';:;
.
-.5.
ca
E
0
"i
G)
C
G)
C!J
1-3
NUMERICAL INDEX
DaYlea Type
t:)
CD
:::::s
...
CD
-.......
!.
:::::s
0
3
s:»
f+
O·
:::::s
1-4
SN5486
SN54LS86A
SN54S86
SN5490A
SN54LS90
SN5491A
SN54LS91
SN5492A
SN54LS92
SN5493A
SN54LS93
SN5494
SN5495A
SN54LS95B
SN5496
SN54LS96
SN5497
SN54107
SN54LS107A
SN54109
SN54LS109A
SN54111
SN54LS112A
SN54S112
SN54LS113A
SN54S113
SN54LS114A
SN54S114
SN54116
SN54120
SN54121
SN54122
SN54LS122
SN54123
SN54LS123
SN54S124
SN54125
SN54LS125A
SN54126
SN54LS126A
SN54128
SN54130
SN54132
SN54LS132
SN54S132
SN54S133
SN54S134
SN54S135
SN54136
SN54LS136
SN54LS137
SN54LS138
SN54S138
SN54lS139A
SN54S139
SN54S140
Page No.
SN7486 •...............
SN74LS86A .............
SN74S86 .. , .............
SN7490A ..... . , ........
SN74LS90 . . . . . . . . . . . . .
SN7491A ...............
SN74LS91 ." ............
SN7492A ...............
SN74LS92 ...............
SN7493A ...............
SN74LS93 .... ,- . . . . . . . . .
SN7494 ................
SN7495A ...............
SN74LS95B •.............
SN7496 ................
SN74LS96 '" ...........
SN7497 ...•.............
SN74107 ...............
SN74LS107A ............
SN74109 .. " ............
SN74LS109A .......
SN74111. ..............
SN74LS112A ............
SN7~S112 , .............
SN74LS113A ............
SN74S113 ... ; ..........
SN74LS114A ............
SN74S114 ....•.........
SN74116 ...............
SN74120 .. , ............
SN74121 . . . . . . . . . . . . . . .
SN74122 ..... : .........
SN74LS122 ........... ..
SN74123 ...............
SN74LS123 " . " . , ' .....
SN74S124 ..............
SN74125 ...........
SN74LS125A ............
SN74126 ..•............
SN74LS126A ............
SN74128 ..........
SN74130 ..............
SN74132 ...............
SN74LS132......
SN74S132 . , ............
SN74S133 ......
SN74S134 ...............
SN74S135 ..............
SN74136 ................
SN74LS136 , . . . . . . . . . . . .
SN74lS137 ... .... " ....
SN74LS138 .............
SN74S138A .............
SN74lS139A ............
SN74S139A .............
SN74S140 ...............
.
2-271
2-271
2-271
2-277
2-277
2-289
2-289
2-277
2-277
2·277
2-277
2-293
2-297
2-297
2-305
2-305
2-311
2-319
2-319
2-325
2-325
2-331
2-335
2-335
2-343
2-343
2-349
2-349
2-357
2-361
2-367
2-373
2-373
2-373
2-373
2-383
2-387
2-387
2-387
2-387
2-393
2-373
2-395
2-395
2-395
2-407
2-411
2-415
2-417
2-417
2-421
2-425
2-425
2-431
2-431
2-435
Device Type
SN54143
SN54145
SN54LS145
SN54147
SN54LS147
SN54148
SN54LS148
SN54150
SN54151A
SN54LS151
SN54S151
SN54153
SN54LS153
SN54S153
SN54154
SN54155
SN54LS155A
SN54156
SN54LS156
SN54157
SN54LS157
SN54S157
SN54LS158
SN54S158
SN54159
SN54160
SN54LS160A
SN54161
SN54LS161A
SN54162
SN54LS162A
SN54S162
SN54163
SN54LS163A
SN54S163
SN54164
SN54LS164
SN54165
SN54LS165A
SN54166
SN54LS166A
SN54167
SN54LS169B
SN54S169
SN54170
SN54LS170
SN54LS171
SN54173
SN54LS173A
SN54174
SN54LS174
SN54S174
SN54175
SN54lS175
SN54S175
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Page No.
SN74143 ...•....
SN74145 .....
SN74LS145 ......
SN74147 ...............
SN74LS147 .........
SN74148 .......
SN74LS148 . .. , ..
SN74150 '" ..
SN74151A .........
SN74LS151 .....
SN74S151 . . . . . . . .
SN74153 .. .........
SN74LS153
SN74S153 ........ ,.
SN74154 "
SN74155 ..
SN74LS155A ..
SN74156 ..
.... ......
SN74LS156
..........
SN74157 ..
SN74LS157 ............
SN74S157 ...
SN74LS158
SN74S158 ...
SN74159
SN74160 .....
SN74LS160A
SN74161
SN74LS161A ..
SN74162 .....
SN74LS162A.
SN74S162 ....
SN74163 ....
SN74LS163A ...
SN74S163
SN74164 ....
SN74LS164
SN74165 .......
SN74LS165A .....
SN74166 ..
SN74LS166A .
SN74167 ..
SN74LS169B
SN74S169 ...
SN74170
SN74LS170
SN74LS171
SN74i72 ...
SN74173 ....
SN74lS173A .. ..........
SN74174 ...
SN74LS174
SN74S174 .
SN74175 .. ..... , ...
SN74LS175
SN74S175 ...
2-439
2-447
2-447
2-451
2-451
2-451
2-451
2-457
2-457
2-457
2-457
2-465
2-465
2-465
2-471
2-475
2-475
2-475
2-475
2-483
2-483
2-483
2-483
2-483
2-489
2-493
2-493
2-493
2-493
2-493
2-493
2-493
2-493
2-493
2-493
2-515
2-515
2-521
2-521
2-529
2-529
2-537
2-543
2-543
2-555
2-555
2-565
2-569
2-575
2-575
2-581
2-581
2-581
2-581
2-581
2-581
NUMERICAL INDEX
Device Type
SN54176
SN54177
SN54178
SN54180
SN54LS181
SN54S181
SN54S182
SN54LS183
SN54190
SN54LS190
SN54191
SN54LS191
SN54192
SN54LS192
SN54193
SN54LS193
SN54194
SN54LS194A
SN54S194
SN54195
SN54LS195A
SN54S195
SN54196
SN54LS196
SN54S196
SN54197
SN54LS197
SN54S197
SN54198
SN54199
SN54221
SN54LS221
SN54LS2401
SN54S240
SN54LS241
SN54S241
SN54LS242
SN54LS243
SN54LS244
SN54S244
SN54LS245
SN54246
SN54247
SN54LS247
SN54LS248
SN54251
SN54LS251
SN54S251
SN54LS253
SN54S253
SN54LS2578
SN54S257
SN54LS258B
SN54S258
SN54259
SN54LS259B
SN54S260
SN54LS261
SN54265
Page No.
SN74176 ...............
SN74177 ...............
SN74178 ... ............
SN74180 ...............
SN74LS181 · ' ...........
SN74S181 . , ......... , - ,
SN74S182 ..............
SN74LS1B3 · " ' .........
SN74190 ...............
SN74LS190 · . . . . . . . . . . .
SN74191 " .......... ".
SN74LS191 , ............
SN74192 ...............
SN74LS192 · ............
SN74193 ...............
SN74LS193 · ........... ,
SN74194 ............
SN74LS194A ............
SN74S194 ..............
SN74195 ...............
SN74LS195A ............
SN74S195 ... ..... , .....
SN74196 ...............
SN74LS196 · ............
SN74S196 ..............
SN74197 ...............
SN74LS197 .............
SN74S197 ..............
SN74198 ...............
SN74199 ...............
SN74221 " , ............
SN74LS221 .............
SN74LS240 ..............
SN74S240 ..............
SN74LS241 .............
SN74S241 .. , ..... , .....
SN74LS242 .............
SN74LS243 , ............
SN74LS244 .............
SN74S244 ..............
SN74LS245 · .....
SN74246 ...............
SN74247 ...............
SN74LS247 · ....... , ....
SN74LS248 . , .....
SN74251 ...............
SN74LS251 .... .... .....
SN74S251 ..... .... .....
SN74LS253 ....... ......
SN74S253 ..............
SN74LS2578 ...........
SN74S257 ..... , ........
SN74LS2588 ............
SN74S258 ... .. ..... ....
SN74259 ... ... .........
SN74LS259B ... .... .....
SN74S260 ..............
SN74LS261 · ............
SN74265 ...............
.
2-587
2-587
2-593
2-597
2-601
2-601
2-611
2-617
2-619
2-619
2-619
2-619
2-633
2-633
2-633
2-633
2-645
2-645
2-645
2-655
2-655
2-663
2-663
2-663
2-663
2-663
2-663
2-663
2-671
2-671
2-681
2-681
2-691
2-691
2-691
2-691
2-697
2-697
2-691
2-691
2-701
2-705
2-705
2-705
2-705
2-715
2-715
2-715
2-723
2-723
2-729
2-729
2-729
2-729
2-735
2-735
2-739
2-743
2-751
Device Type
SN54LS266
SN54273
SN54LS273
SN54276
SN54278
SN54279
SN54LS279A
SN54LS2BO
SN54S280
SN54283
SN54LS283
SN54S283
SN542B4
SN542B5
SN54290
SN54LS290
SN54LS292
SN54293
SN54LS293
SN54LS294
SN54LS2958
SN54LS297
SN54298
SN54LS298
SN54LS299
SN54S299
SN54LS320
SN54LS321
SN54LS322A
SN54ALS323
SN54LS348
SN54S350
SN54LS352
SN54LS353
SN54LS354
SN54LS355
SN54LS356
SN54365A
SN54LS365A
SN54366A
SN54LS366A
SN54367A
SN54LS367A
SN54368A
SN54LS368A
SN54LS373
SN54S373
SN54LS374
SN54S374
SN54LS375
SN54376
SN54LS377
SN54LS378
SN54LS379
SN54LS381A
SN54S381
SN54LS382
SN54LS384
SN54LS385
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
Page No.
SN74LS266 .............
SN74273 ...............
SN74LS273 . ............
SN74276 ...............
SN74278 ...............
SN74279 ...............
SN74LS279A ............
SN74LS2BO . ............
SN74S2BO ..............
SN74283 ...............
SN74LS2B3 . ............
SN74S2B3 ..............
SN742B4 ...............
SN74285 ...............
SN74290 .........
SN74LS290 .......... ' "
SN74LS292 , ............
SN74293 ...............
SN74LS293 · . . . . . . . . . . .
SN74LS294 .............
SN74LS295B ............
SN74LS297 · ............
SN74298 ...............
SN74LS298 . ............
SN74LS299 .............
SN74S299 ..............
SN74LS320 . ............
SN74LS321 .............
SN74LS322A ............
SN74ALS323 .........
SN74LS348 . ............
SN74S350 ..............
SN74LS352 . ............
SN74LS353 .............
SN74LS354 . ............
SN74LS355 . ............
SN74LS356 . ............
SN74365A ..............
SN74LS365A ............
SN74366A ..............
SN74LS366A ............
SN74367A ..............
SN74LS367A ............
SN74368A ..............
SN74LS368A ............
SN74LS373 · . . . . . . . . . . .
SN74S373 ..............
SN74LS374 · ............
SN74S374 ..............
SN74LS375 .............
SN74376 ......... , .....
SN74LS377 .............
SN74LS378 · ............
SN74LS379 .............
SN74LS381A ............
SN74S381 ..............
SN74LS382 .............
SN74LS384 . ............
SN74LS385 .............
.
.
2-757
2-759
2-759
2-763
2-767
2-771
2-771
2-775
2-775
2-781
2-781
2-7Bl
2-7B7
2-7B7
2-791
2-791
2-799
2-791
2-791
2-799
2-807
2-811
2-817
2-817
2-823
2-823
2-829
2-829
2-835
2-841
2-845
2-849
2-855
2-859
2-863
2-863
2-863
2-873
2-873
2-873
2-873
2-873
2-873
2-873
2-873
2-883
2-883
2-883
2-883
2-891
2-893
2-895
2-895
2-895
2-899
2-899
2-899
2-907
2-913
C
0
'';:;
....E
ftS
0
.5
'!
'CD
C
CD
~
1-5
NUMERICAL INDEX
Devic~
•
C)
CD
:::s
...
(I)
!!.
-....
:::s
...
0
3
...0'
S»
:::s
Type
SIII54LS386A
SIII54390
SN54LS390
SN54393
SN54LS393
SN54LS395A
SN54LS396
SIII54LS399
SN54LS422
SN54LS423
SN54S436
SN54LS440
SN54LS441
SN54LS442
SN54LS444
SIII54LS445
SN54LS446
SN54LS449
SN54LS465
SN54LS466
SN54LS467
SN54LS468
SN54LS490
SN54LS540
SN54LS541
SN54LS590
SN54LS591
SN54LS592
SN54LS593
SN54LS594
SN54LS595
SN54LS596
SN54LS597
SN54LS598
SN54LS599
SN54LS604
SN54LS606
SN54LS607
SN54LS610
SN54LS612
SN54LS620
'-6
SIII74LS386A .......
SIII74390 .......
SN74LS390 .......
SN74393 .........
SN74LS393 .......
SN74LS395A .....
SN74LS396
SN74LS399
SN74LS422
SN74LS423 .... ........ ,
SN74S436 ..........
SN74LS440
...........
SN74LS441
SN74LS442
SN74LS444
SN74LS445
SIII74LS446
SN74LS449
SN74LS465 ..........
SIII74LS466
SN74LS467 .............
SN74LS468
SIII74LS490
SN74LS540 ........... '.
SIII74LS541 .............
SN74LS590
. ...... ....
SN74LS591
.........
SIII74LS592
. .. , ......
SN74LS593
SN74LS594 .... ... ......
SN74LS595
SN74LS596
SN74LS597
SN74LS598
SN74LS599
SN74LS600A ... . . . . . . . . .
SN74LS601A ...
SN74LS603A .........
SN74LS604
SN74LS606 .......
SN74LS607
SN74LS610
SN74LS611
SN74LS612
SN74LS613
SN74LS620
Page No.
Device Type
2·917
2-919
2-919
2-919
2-919
2-929
2-933
2-937
2-941
2-941,
2-947
2-951
2-951
2-951
2-951
2-957
2-959
2-959
2-963
2-963
2-963
2-963
2-967
2-973
2-973
2-977
2-977
2-981
2-981
2-989
2-993
2-993
2-999
2-999
2-989
2-1007
2-1007
2-1007
2-1015
2-1015
2-1015
2-1021
2-1021
2-1021
2-1021
2-1031
SIII54LS621
SN54LS624
SN54LS626
SN54LS628
SN54LS629
SN54LS630
SN54LS636
SN54LS637
SN54LS638
SN54LS639
SIII54LS640
SIII54LS641
SIII54LS642
SN54LS644
SN54LS645
SN54LS646
SN54LS647
SN54LS648
SIII54LS649
SN54LS651
SN54LS652
SN54LS653
SN54LS668
SN54LS669
SN54LS670
SN54LS671
SN54LS672
SN54LS673
SN54LS674
SN54LS681
SN54LS682
SN54LS684
SN54LS685
SN54LS687
SN54LS688
SN54LS690
SN54LS691
SN54LS693
SN54LS696
SN54LS697
SN54LS699
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
Page No.
SIII74LS621
SIII74LS623
SN74LS624
SIII74LS625
SN74LS626
SIII74LS627
SN74LS628
SN74LS629
SN74LS630
SN74LS636
SN74LS637
SN74LS638
SN74LS639
SIII74LS640
SIII74LS641
SIII74LS642
SIII74LS644
SN74LS645
SN74LS646
SIII74LS647
SN74LS648
SIII74LS649
SN74LS651
SN74LS652
SN74LS653
SN74LS668
SN74LS669
SN74LS670
SN74LS671
SN74LS672
SN74LS673
SN74LS674
SN74LS681
SN74LS682
SN74LS684
SN74LS685
SN74LS686
SN74LS687
SN74LS688
SN74LS690
SN74LS691
SN74LS693
SN74LS696
SN74LS697
SN74LS699
. ....
..
....
.........
......... , .
.........
.... , .. ' "
.,
......... , ...
............
.............
.............
.............
... ... , ....
"
..........
.... , ........
. .............
. ............
.............
.............
. ",.
........
",
'"
,,'
.............
..........
2-1031
2·1031
2-1037
2-1037
2-1037
2-1037
2-1037
2-1037
2-1047
2-1055
2-1055
2-1063
2-1063
2-1067
2-1067
2-1067
2-1067
2-1067
2-1075
2-1075
2-1075
2-1075
2-1085
2-1085
2-1085
2-1093
2-1093
2-1103
2-1111
2-1111
2-1117
2-1117
2-1123
2-1129
2-1129
2-1129
2-1129
2-1129
2-1129
2-1139
2-1139
2-1139
2-1149
2-1149
2-1149
FUNCTIONAL INDEX
Column heading Literature Number provides the latest available technical source for a particular product.
Tl's technical literature is identified by a seven- or eight-character product source code consisting of four
(4) alpha characters, three (3) numeric characters, and a revision letter, if applicable. If the fourth alpha
character is an "S", then the document is a stand-alone data sheet, e.g., SOAS 106A. The code is printed
at the upper right-hand corner on the front cover and the lower left-hand corner on the back cover of a
data book, and at the lower left-hand corner on the back page of a data sheet.
List of Applicable Oatabooks:
SCAD001 A = Advanced CMOS Logic Oatabook
SCLD001 B = High-Speed CMOS Logic Oatabook
SDAD001B = ALS/AS Logic Oatabook
SOF0001
= F Logic Oatabook
SOL0001 A = Standard TTL Logic Databook
SDV0001
= LSI Logic Oatabook
SDZD001 B = Programmable Logic Databook
..
c:
o
"
CO
E
...
o
.5
C6
...
Q)
c:
Q)
(!I
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
1-7
FUNCTIONAL INDEX
GATES
POSITIVE-NAND GATES
TECHNOLOGY
DESCRIPTION
II
f
it
!.
S"
....
o
•
8-lnput
LS
S
•
•
'30
ALS
AS
A
•
13-lnput
12-lnput
Dual2-lnput
•
'133
'134
'8003
'13
•
•
•
•
•
•
•
'20
Dual 4-lnput
'40
'1020
'11020
•
•
•
•
•
'10
'1010
"11010
A
•
•
'26
'37
Quad 2-lnput
'38
'39
'132
•
•
•
•
•
•
•
•
•
A
•
•
•
•
1-8
•
•
•
•
•
•
•
•
•
•
•
•
A
'804
'lB04
• •
... •
A ..
B •
TBA
•
A
'1000
'11000
Hex 2-lnput
•
•
•
•
•
ACT
A
A
•
AC
•
A
•
HC
•
Triple 3-lnput
'00.
F
•
'11030
!l
=
STD
TTL
3
s·
TYPE
•
A
A
A
B
A
•
Denotes available technology .
Denotes planned new.
Denotes "A" suffix available in the technology indicated.
Denotes "B" suffix available in the technology indicated.
• Denotes information To Be Announced.
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 865012 • DALLAS, TEXAS 75265
•
LITERATURE
NUMBER
SDLDOOIA
SDADoolB
SCLDoo18
SDFDool
SCADoolA
SDAOOO1B
SCLOOO18
SDLOOO1A
SDLDoolA
SDADOO18
SDLDoolA
SDLOOO1A
SDADOO18
SCLD001B
SDFDool
SDADOO1B
SDLDOO1A
SDADoo18
SCADoolA
SDLOOO1A
SDAD0018
SCLD001B
SDFDOOI
SDADoolB
SCADOO1A
SDADOOIB
SDLDoolA
SCLDoolB
SDFDool
SDLDOOIA
SDLD001A
SDADOO18
SDLDoolA
SDADoolB
SDLOOO1A
SDLDoolA
SCLDoolB
SDADOO18
SCAOOO1A
SDADOO1B
SCLooolB
SDADoolB
FUNCTIONAL INDEX
POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
Dual 4-lnput
'22
Triple 3-lnput
'12
'01
Quad 2-lnput
'03
•
•
•
•
LS
S
•
•
AS
F
LITERATURE
HC
AC
ACT
NUMBER
SDLDOO1A
SDAD001B
B
SDLD001A
SDAD001B
A
•
•
ALS
SDLDOO1A
•
•
'1003
SDAD001B
•
SCLD001B
SDLDOO1A
B
SDAD001B
•
A
SCLD001B
SDADOO1B
TECHNOLOGY
TYPE
STD
TTL
Triple 3-lnput
'15
•
Quad 2-lnput
Quad Schmitt
'09
LS
S
ALS
•
•
•
•
A
AS
F
LITERATURE
HC
c
«S
E
...
.2c
-
POSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTS
DESCRIPTION
..
.2
AC
ACT
NUMBER
SDLD001A
SDAD001B
ca...
Q)
C
Q)
o
SDLD001A
•
SDAD001B
•
'7001
•
•
SCLD001B
SDFD001
SCLD001B
•
Denotes available technology.
..
Denotes planned new.
A
Denotes "A" suffix available in the technology indicated.
B
Denotes "8" suffix available in the technology indicated.
TBA == Denotes information To Be Announced.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
'-9
FUNCTIONAL INDEX
POSITIVE-AND GATES
TECHNOLOGY
DESCRIPTION
III
Dual 4-I'nput
TYPE
STD
TTL
LS
S
ALS
AS
A
•
•
'21
F
•
'11021
•
G')
•
'11
~
..
-..3
::s
A
•
Triple 3-lnput
~
'lOll
'11011
e.
A
•
5'
o
•
•
•
'08
•
•
A
A
Quad 2-lnput
...0'
'1008
'11008
CI)
::s
•
HC
AC
ACT
•
•
•
•
•
•
•
AC
ACT
•
•
LITERATURE
NUMBER
SDADOO18
SDLD001A
SCLDoo18
SDFDool
SCAD001A
SDLD001A
SDADOO18
SCLDoo18
SDFD.ool
SDADOO18
SCADoolA
SDLD001A
SDADOO18
SCLDoo18
SDFDool
SDADoo18
SCAD001A
POSITIVE-OR GATES
TECHNOLOGY
DESCRIPTION
Triple 3-lnput
TYPE
STD
TTL
LS
S
•
•
•
ALS
AS
'32
'1032
'7032
'11032
'832
'1832
•
•
'" ..
A ..
B ..
TBA
1-10
HC
•
'4075
•
•
Quad 2-lnput
Hex 2-lnput
F
A
A
•
•
•
A
B
A
•
Denotes available technology.
Denotes planned new.
Denotes" A" suffix available in the technology indicated,
Denotes "S" suffix available in the technology indicated,
_ Denotes information To Be Announced.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
•
•
•
LITERATURE
NUMBER
SCLD0018
SDLD001A
SDAD001B
SClD001B
SDFD001
SDADOO18
SClD001B
SCADoolA
SDAD001B
SClDoo18
SDAD001B
FUNCTIONAL INDEX
POSITIVE-NAND GATES
TECHNOLOGY
DESCRIPTION
TYPE
STD
LS
TTL
Dual 4-lnput
with Strobe
'25
Dual 4-lnput
'4002
Dual 5-lnput
'260
ALS
AS
F
•
•
•
•
•
•
•
•
•
'02
'33
•
•
•
•
•
•
SCLDOO18
SDLDOO1A
•
SCLDOO1B
SDFDoOl
•
•
SCAD001A
SDLD001A
SDADOO1B
•
SCLDOO1B
SDFDOOl
SDLDOO1A
SDAD001B
A
SDLD001A
SOAD001B
A
'36
'1002
•
A
'1036
'7002
•
SCLDOO1B
A
'1805
a:J
E
o
....
.:
'ii
...
i
(!')
Q)
SDAOOO1B
•
B
•
•
•
A
Q
SDADOO1B
•
'80S
C
;:;
SDFDOOl
A
'11002
Hex 2-lnput
NUMHR
SDLDOO''''
SDADOO1B
'11027
Quad 2-lnput
ACT
AC
•
•
'27
'28
LITERATURE
HC
SDLD001A
•
Triple 3-lnput
S
SCLDOO18
SCAD001A
SDAD001B
SCLDOO1B
SDADOO1B
POSITIVE-OR/NOR GATES
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
8-lnput
•
...
A
B
TBA
'4078
II
LS
I
I
S
II
ALS
I
I
AS
II II
F
LITERATURE
HC
A
I
I
AC
I
I
ACT
NUMBER
SCLD001B
Denotes available technology.
Denotes planned new.
Denotes "A" suffix available in the technology indicated.
Denotes "6" suffix available in the technology indicated.
E
Denotes information To Be Announced.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
1-11
FUNCTIONAL INDEX
EXCLUSIVE-ORJ-NOR GATES
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
•
Quad 2-lnput
Exclusive-OR
'86
LS
S
A
•
ALS
•
Exclusive-OR
G')
Gates with Open-
CD
Collector Outputs
:::J
CD
'810
Gates
~...
•
•
'266
Exclusive-NOR
'7266
Exclusive-NOR
Gates with Open-
:::J
OR/-NOR Gates
...0'
SCLDOO'B
SDAD001B
•
•
•
•
•
Quad 2-lnput
3
CI)
SCLDOO1B
SDLDOO1A
'136
Quad 2-lnput
a;
•
•
•
NUMBER
SDAD001B
•
'386
Quad 2-lnput
HC
SDLD001A
Gates with
Totem-Pole Outputs
LITERATURE
AS
'811
SDAD001B
SDLDOO1A
•
SCLD001B
•
SCLD001B
SDAD001B
SDAD001B
Collector Outputs
Quad Exclusive-
•
'135
SDLD001A
AND·NOR GATES
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
2-Wide 4·lnput
4-Wide 4-2-3-2
Input
4-Wide 2-2-3-2
Input
Dual2·Wide
2-lnput
'55
LS
•
'64
'54
'51
•
•
•
•
S
ALS
AS
LITERATURE
HC
HCT
•
NUMBER
SDLDOO1A
•
•
SCLD001B
AND·NOR GATES WITH OPEN·COLLECTOR OUTPUTS
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
4-Wide 4-2-3-2Input
'65
LS
S
ALS
AS
•
TEXAS
HCT
NUMBER
SDLDOO1A
•
Denotes available technology.
Denotes planned new.
•
Denotes" A" suffix available in the technology indicated.
A
B
Denotes "B" suffix available in the technology indicated.
TBA .. Denotes information To Be Announced_
1-12
LITERATURE
HC
~
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TeXAS 75265
FUNCTIONAL INDEX
EXPANDABLE GATES
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
Dual2-Wide
AND-DR-Invert
'50
•
'23
•
LS
S
ALS
AS
LITERATURE
HC
HCT
Dual 4-lnput
Positive-NOR
NUMBER
SOLDOOIA
with Strobe
c
MULTIFUNCTION GATES AND ELEMENTS
CI
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
LS
S
ALS
LITERATURE
AS
HC
HCT
NUMBER
Invertar ,3-/4Input NAND/NOR
'7006
•
SCLDOOIB
'7008
•
SCLDOOIB
Combination
6-Section NAND
Invert, NOR
Quadruple
Complimentary
Output Logic
'265
•
'j
E
-~
SDLDOOIA
Element
DELAY ELEMENTS
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
LS
S
ALS
LITERATURE
AS
HC
HCT
NUMBER
Inverting and
Noninverting
Elements 2-lnput
'31
•
SDLDOOIA
NAND-Buffer
• ..
•
A
8 ..
TBA
Denotes available technology_
Denotes planned new.
Denotes "A" suffix available in the technology indicated.
Denotes "B" suffix available in the technology indicated.
i!! Denotes information To Be Announced.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
1-13
FUNCTIONAL INDEX
INVERTERS/NONINVERTING BUFFERS
HEX INVERTERS/NONINVERTERS
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
•..
•
LS
S
•
•
ALS
AS
B
•
'11004
CD
!!.
Hex Inverters
'05
'06
5'
....
o
3
..
'14
....
I»
o·
:s
Hex
Noninverter
•
"
A ~
B ==
TBA
1-14
'16
'19
'1004
'1005
'34
'11034
•
•
•
•
•
•
AC
ACT
•
NUMBER
SCLDOOIB
•
•
•
SCLDOOIB
SDFDOOI
SCADOOIA
SDLDOOIA
SDADOOIB
A
•
•
•
HCU
SDADOOIB
•
G)
:s
LITERATURE
HC
SDLDOOIA
'04
CD
F
SCLDOOIB
SDLDOOIA
SDLDOOIA
•
SCLDOOIB
SDLDOOIA
SDLDOOIA
•
•
•
SDADOOIB
A
SDADOOIB
•
Denotes available technology.
Denotes planned new.
Denotes" A" suffix available in the technology indicated.
Denotes "B" suffix available in the technology indicated.
.. Denote. information To 8e Announced.
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
•
•
SDADOOIB
SCADOOIA
FUNCTIONAL INDEX
DRIVER AND BUS TRANSCEIVERS
HEX DRIVERS
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
Hex 2-lnput
Driver
S
ALS
AS
A
B
A
•
'808
'1808
'07
'17
Hex Driver
LS
'35
•
•
'366
Hex Buffersl
Drivers
'367
'368
A
A
A
A
A
•
SCLD001B
SDAD001B
SDAD001B
•
A
NUMBER
SDAD001B
A
•
'1035
Noninverting
HCT
SDLD001A
'1034
'365
LITERATURE
HC
SDAD001B
A
SDAD001B
SDLD001A
•
•
•
•
A
A
SCLD001B
SDLD001A
SCLD001B
SDLD001A
SCLD001B
SDLD001A
SCLD001B
c
o
'+0
ca
...Eo
c
...ca
Q)
C
Q)
~
DRIVERS WITH OPEN-COLLECTOR OUTPUTS
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
Noninverting
Octal Buffers,
Drivers
Inverting
LS
S
ALS
AS
...
•
•
•
•
•
•
'757
'760
'756
Octal Buffers,
Drivers
'763
LITERATURE
HC
HCT
NUMBER
SDAD001B
SDAD001B
SDAD0018
SDAD001B
Inverting and
Noninverting
Octal Buffers,
•
'762
SDAD001B
Drivers
•
Denotes available technology.
...
Denotes planned new.
A
Denotes" A" suffix available in the technology indicated.
8
Denotes "B" suffix available in the technology indicated.
TBA '" Denotes information To Be Announced.
TEXAS
~
INSfRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-15
FUNCTIONAL INDEX
BUS TRAI\ISCEIVERS WITH OPEN-COLLECTOR OUTPUTS
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
LS
S
ALS
AS
F
HC
LITERATURE
NUMBER
Noninverting
Quad
II
'759
Transceivers
Inverting Quad
Transceivers
•
'758
•
'615
C)
A
CD
:J
CD
12-mA/24-mAI
'621
•
40-mA Sink
~
!!.
Transceivers
:J
'639
'641
o
3
'614
~
A
•
•
A
•A
'622
C»
12-mAl24-mAI
48-mA Sink
r+
0'
:J
'638
Inverting Output
Transceivers
'642
'653
12-mA/24-mAI
48-mA Sink, True
and Inverting
A
•
•
A
•
A
'647
12-mA/24-mAi
'654
A
•
•
SDADOOIB
•
•
•
Multiplexed
'649
SDLDOOIA
•
SDFDOOI
SDADOO18
SDLDOOIA
SDADOO18
SDLDOOIA
SDADOO18
•
•
•
SDADOO18
•
SDFDOOI
SDADOO18
SLDLOOIA
SDADOOIB
SDLDOOIA
SDADOOIB
SDLSOOIA
•
SDADOO18
•
SDADOO18
SDLDOOIA
•
•
SDVDOOI
SDLDOOIA
48-mA Inverting
•
Output Transceivers
Denotes available technology.
...
A
B
Denotes planned new.
Denotes HA" suffix available in the technology indicated.
Denotes "B" suffix available in the technology indicated.
TBA == Denotes informat!on To Be Announced.
1-16
SDADOO18
SDLDOOIA
Registered with
•
SDADOO18
SDLDOOIA
Output Transceivers
12-mA/24-mAI
•
•
Registered with
48-mA True
SDADOO18
•
'644
Output Transceivers
Multiplexed
•
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SDVDOOI
FUNCTIONAL INDEX
DRIVERS WITH 3-STATE OUTPUTS
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
LS
Quad Buffersl
Drivers with
'125
•
A
Independent
Output Controls
'126
•
A
S
ALS
AS
F
HC
LITERATURE
HCT
•
B
•
• •
•
•
B
•
•
'541
'1244
•
•
•
•
•
SCLDOOIB
•
A
A
SCLDOOIB
SDFDOOI
SCBSOO5
SCADOOIA
SDLDOOIA
SDADOOIB
•
'11244
•
SCLDOOIB
SDLDOOIA
SDADOOIB
•
'244
'467
NUMBER
SCLDOOIB
SDLDOOIA
'11241
•
BCT
•
•
'241
'465
ACT
SDLDOOIA
• •
Noninverting
Octal Buffersl
Drivers
AC
•
•
SDFDOOI
SCBSOO6
SCADOOIA
SDLDOOIA
SDADOOIB
SDADOOIB
SDLDOOIA
SDLDOOIA
•
•
A
•
SDADOOIB
SCLDOOIB
SDADOOIB
Denotes available technology.
4 " Denotes planned new.
Denotes" A" suffix available in the technology indicated.
A
B
Denotes "B" suffix available in the technology indicated.
TBA " Denotes information To 8e Announced.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • OALlAS, TeXAS 75265
1-17
FUNCTIONAL INDEX
DRIVERS WITH 3-STATE OUTPUTS (continued)
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
..
LS
S
'231
• •
ALS
AS
•
•
A
•
'240
F
HC
LITERATURE
HCT
'466
'468
'540
'1240
Inverting and
Noninverting
Octal Buffers!
•
BCT
SDAD001B
•
•
SCLDOO1B
•
•
•
SDFD001
SCBS004
SCAD001A
SDLD001A
A
SDAD001B
A
SDAD001B
•
•
NUMBER
SDLD001A
'11240
Buffer~!Drivers
ACT
SDAD001B
•
Inverting Octal
AC
SDLD001A
SDLD001A
•
•
SDAD001B
•
•
SCLD001B
SDAD001B
•
'230
SDAD001B
Drivers
Noninverting
10-Bit 8uffers!
Drivers
Inverting 10-8it
Buffers!Drivers
•
..
A
B
TBA
1-18
•
'2827
'29827
•
•
•
•
'2828
'29828
•
Denotes available technology.
Denotes planned new.
Denotes "A" suffix available in the technology indicated.
Denotes "B" suffix available in the technology indicated.
:5 Denotes information To Be Announced.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SCLS051
SDVD001
SCLS052
SCLS051
SOVOO01
SCLS052
FUNCTIONAL INDEX
BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
DESCRIPTION
TYPE
•
Noninverting
Quad
TECHNOLOGY
LS
'243
S
ALS
AS
Inverting Quad
'242
A
•
B
•
Tridirectional
'442
Transceivers
•
•
•
•
A
A
•
'11640
'1245
•
...
SDFD001
SCLD001B
SDFD001
SDAD001B
•
SDAD001B
•
•
•
SCLD001B
SDFD001
&
•
•
•
A
•
•
•
•
TBA
SCAD001A
SCLD001B
c
o
"';:;
CO
...Eo
c
ca...
Q)
C
Q)
(!)
SDAD003
SDFD001
•
&
•
•
SCBS001
SCAD001A
SCLD001B
SDAD001B
SDLD001A
&
A
•
•
&
'643
'11643
SCLD001B
•
'11620
'640
NUMBER
SDLD001A
'11245
Transceivers
BCT
SDLD001A
•
Octal
ACT
SDLD001A
'245
'620
AC
SDAD001B
•
•
Quad
LITERATURE
HCT
SDAD001B
•
Transceivers
'1242
HC
SDLD001A
Transceivers
•
F
•
•
SCAD001A
SCLD001B
SDAD001B
SDLD001A
•
A
•
•
SCAD001A
SDAD001A
&
TBA
Denotes
Denotes
qenotes
Denotes
available technology.
planned new.
A
"A" suffix available in the technology indicated.
B
"8" suffix available in the technology indicated.
TBA == Denotes information To Be Announced.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
1-19
FUNCTIONAL I.II0EX
BUS TRANSCEIVERS WITH 3-STATE OUTPUTS (continuedl
DESCRIPTION
TYPE
LS
S
ALS
AS
•
•
'543
'544
'646
•
Octal Bus
'64B
•
Transceivers
with Registers
'651
•
'652
'11646
TECHNOLOGY
F
HC
HCT
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
'659
'664
8-/9-Bit Bus
Transceivers
'665
'29833
with Parity
Checkerl
'29834
Generator
'29853
'29854
•
•
BCT
LITERATURE
NUMBER
•
SDFDOOI
SCLDOOIB
SDADOOIB
SDLDOOIA
SCLDOOIB
SDADOOIB
SDLDOOIA
SCLDOOIB
SDADOOIB
SDLDOOIA
...
...
...
...
SCLDOOIB
SDADOOIB
SDLDOOIA
...
...
...
...
SCADOOIA
•
SCLDOOIB
•
•
SDAS119A
•
•
•
•
•
•
•
Denotes available technology.
...
Denotes planned new.
A
Denotes "A" suffix available in the technology indicated.
B
Denotes "8" suffix available in the technology indicated.
TBA == Denotes information To Be Announced.
1-20
ACT
SDFDOOI
'11648
'11651
'11652
'658
AC
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SCBSOO3
SDAS119A
SCBSOO3
SDAS118
SCBSOO2
SDAS118
SCBSOO2
FUNCTIONAL INDEX
BUS TRANSCEIVERS WITH 3-STATE OUTPUTS Icontinued)
DESCRIPTION
Noninverting 9-
Bit Transceivers
Inverting 9-Bit
Transceivers
Noninverting 10-
Bit Transceivers
Inverting 10-Bit
Transceivers
TYPE
TECHNOLOGY
lS
S
AlS
'29864
'29861
'29862
•
'645
'654
'1640
'1645
'852
Transceiver!
'856
Port Controllers
'877
ACT
•
•
A
•
•
BCT
'"
'"
NUMBER
SCLS055
SDAS096A
TBA
SDAS097
SCLS056
SDAS097
T8A
SDAD001B
SDLD001A
•
•
•
•
SCLD001B
SDFD001
SCLD001B
SDAD001B
SDLD001A
•
SDAD001B
A
A
'11623
Universal
AC
•
12-mA/24-mAI
Transceivers
LITERATURE
HCT
SDAS096A
•
True Output
HC
•
A
48-mA Sink,
F
•
•
•
•
'29863
'623
AS
•
•
•
'"
'"
c
o
'';:;
CO
E
....5o
~
ca
~
Q)
SDLD001A
C
SDAD001B
(!J
Q)
SCAD001A
SDAD001B
•
Denotes available technology.
...
Denotes planned new.
A
Denotes" A" suffix available in the technology indicated.
B
Denotes "8" suffix available in the technology indicated.
TBA ;;;;; Denotes information To Be Announced.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
1-21
FUNCTIONAL INDEX
LINE DRIVERS/BUS TRANSCEIVERS/MDS DRIVERS
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
LS
S
ALS
•
'2242
Bus
Transceivers
'2620
'2623
'2640
'2645
•
'2240
'2240
line
Drivers
-:::s
....
'2241
HC
...
...
...
•
•
o
NUMBER
SDADOOIB
•
•
'2244
'2541
BCT
•
•
...
'2244
'2540
..
LITERATURE
AS
TBA
SDADOOIB
LINE DRIVERS
3
Q)
TECHNOLOGY
DESCRIPTION
o·"':::s
TYPE
STD
TTL
Octal Buffers
LS
S
'746
•
'747
•
AND/Line Drivers
with Input
Pull-up
ALS
LITERATURE
AS
Resistors
Octal/Line
'2540
•
'2541
•
Drivers/with
3-State Output
•
Denotes available technology .
Denotes planned new.
A
Denotes" A" suffix available in the technology indicated.
Denotes "S" suffix available in the technology indicated.
B
TBA :5 Denotes information To Be Announced.
.&
1-22
TEXAS •
INSTRUMENTS
POST OFFice BOX 655012· DALLAS, TEXAS 75265
HC
HCT
NUMBER
SDADOOIB
FUNCTIONAL INDEX
50-0HM/75-0HM LINE ORIVERS
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
Quad 2-lnput
Positive-NOR
Dual 4-lnput
Positive-NAND
Hex 2-lnput
Positive-NAND
Hex 2-lnput
Positive-NOR
Hex 2-lnput
Positive-AND
Hex 2-lnput
Positive-OR
'12S
LS
S
ALS
LITERATURE
AS
HC
HCT
•
NUMBER
SDLD001A
•
'140
A
'S04
'lS04
A
A
'B05
'1S05
A
A
'SOS
'lS0S
A
A
'S32
'lB32
A
B
•B
•
SDAD001B
•
SCLD001B
SDAD001B
'';:
•
SCLD001B
SDAD001B
B
•B
•
c
o
•
SCLD001B
SDAD001B
•
SCLD001B
SDAD001B
as
.
E
o
~
-a;..
Q)
C
Q)
~
MULTIFUNCTION DRIVERS
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
LS
S
ALS
LITERATURE
AS
HC
HCT
NUMBER
Dual Pulse
Synchronizers!
Drivers
'120
•
SDLD001A
•
Denotes available technology.
•
Denotes planned new.
A
Denotes "A" suffix available in the technology indicated.
Denotes "B" suffix available in the technology indicated.
B
TBA :;: Denotes information To 8e Announced.
TEXAS ...,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-23
FUNCTIONAL INDEX
FLIP-FLOPS
DUAL AND SINGLE FLIP-FLOPS
TECHNOLOGY
DESCRIPTION
III
TYPE
'78
'107
•
A
•
A
'76
I»
:s
~
LS
•
•
•
'73
f
•--
STD
TTL
S
ALS
Dual J-K EdgeTriggered
I»
A
A
•
•
•
A
A
•
'114
•
•
'11109
Dual4-8it
D-Type
Edge-Triggered
•
•
•
LITERATURE
NUMBER
SDLD001A
SCLD001B
SDLD001A
SCLD001B
SDLD001A
SCLDOO18
SDLD001A
SCLDOO18
SDLD001A
SDADOO18
SCLDOO18
SDFDOOl
SDLD001A
SOAOOO18
SCLD001B
SDFDOOl
SDLD001A
SDADOO1B
SCLD001B
SOFDOOl
SDLOOO1A
SDAD001B
SCLD001B
SDFDOOl
SCAD001A
SDLD001A
A
•
A
'74
'11074
'7074
'7075
'7076
'874
'876
'87B
'879
•
•
•
•
B
A
A
A
•
•
•
•
•
• • Denotes available technology.
• • Denotes planned new.
A • Denotes" A" suffix available in the technology indicated.
B • Denotes "8" suffix available in the technology indicated.
TBA .. Denotes information To Be Announced.
1·24
•
A
A
•
•
A
'113
DualD-Type
with 2-lnput
NAND/NOR Gates
•
A
A'
A
DualD-Type
F
•
0
'70
ACT
•
A
A
:s
Single J-K EdgeTriggered
AC
•
•
'112
ct.
HC
A
'109
-:3
AS
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
•
•
•
SDADOO18
SCLD001B
SDFDOOl
SCADOOlA
SCLD001B
SDAD001B
FUNCTIONAL INDEX
QUAD AND HEX FLlp·FLOPS
NO.
DESCRIPTION
OUTPUTS
OF
TECHNOLOGY
TYPE
FF.
STD
TTL
•
LS
S
•
•
'175
a,a
D·Type
•
•
'276
Q
4
'279
'376
•
l55
•
•
•
•
•
•
•
•
F
NUMBER
SDADOO1B
•
•
6
'378
HC
SDLOOO1A
•
'174
J·K
LITERATURE
AS
4
'379
Q
ALS
A
•
SCLOOO1B
•
SDFDOO1
SDLOOO1A
SCLDOO1B
•
SDFOOO1
SDLDOO1A
SDADOO1B
•
•
SCLOOO1B
•
SDFDOO1
SDLDOO1A
SCLDOO1B
•
SDFOOO1
SDLDOO1A
c
o
'';::
cu.
E
...o
.5
'!CD
c
CD
e,:,
Denotes available technology.
..
Denotes planned new.
Denotes" A" suffix available in the technology indicated.
A
B '" Denotes "B" suffix available in the technology indicated.
TBA ;;;;; Denotes information To Be Announced.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
'·25
FUNCTIONAL INDEX
OCTAL, 9-BIT, AND 10-BlT D-TYPE FLIP-FLOPS
DESCRIPTION
NO, OF
BITS
TECHNOLOGY
OUTPUTS
TYPE
STD
LS
S
• •
'374
True Data
ALS
AS
• •
'11374
•
2-State
•
'273
•
ACT
BCT
Clear
3-State
Octal
Enable
2-State
•
'575
A
'874
A
'878
A
•
'377
...
Inverting with
3-Stat.
Clear
Inverting with
3-State
Preset
A
'879
A
'876
A
'825
True
9-Bit
3-State
Inverting
3-Stat.
True
3-State
10-Bit
3-State
'823
'1823
•
• •
...
'821
'1821
'822
•
Denotes available technology_
Denotes planned new.
...
A
Denotes "A" suffix available in the technology indicated.
B
Denotes "B" suffix available in the technology indicated.
TBA == Denotes information To Be Announced.
-
SCADOO1A
SCLDOO1B
SDFDOO1
TEXAS""
'NSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SCLDOO1B
SDFDOO1
SDADOO1B
SCLDOO1B
T8A
•
SOFOOO1
SDADOO18
SCLD001B
•
•
•
•
•
•
'824
SDFDOO1
SDLDOO1A
•
•
•
•
-.
• •
•
'577
SDADOO1B
SDADOO1B
•
• •
'826
SDFDOOl
SDLDOO1A
•
A
'11534
•
SCLDOO1B
•
A
SCLDOO1B
TBA
•
•
•
'564
'576
NUMBER
SDADOO1B
'534
3-Sta!e
• •
•
• •
Inverting
F
SDADOO1B
• •
• •
True Data with
1-26
LITERATURE
AC
3-State
'574
Inverting
HCT
SDLDOO1A
A
True with
He
SDFDOOl
SDADOO1B
SDADOO1B
• •
SCAD001A
SDADOO1B
SDADOO1B
SDAS126
SDAD001B
SDAS131
SDAD001B
FUNCTIOtlAL INOEX
LATCHES AND MULTIVIBRATORS
QUAD LATCHES WITH 2·STATE OUTPUTS
TECHNOLOGY
DESCRIPTION
TYPE
'75
STD
TTL
•
Bistable
'375
S-R
'279
•
LS
S
ALS
AS
HC
•
•
HCT
SDLDOOIA
SCLDOOIB
SDLDOOIA
SCLDOOIB
SDLDOOIA
•
•
A
LITERATURE
NUMBER
. TECHNOLOGY
Single
Dual
TYPE
STD
TTL
'121
'122
'130
'123
'221
'423
•
•
•
•
•
LS
S
ALS
o
'j
MONOSTABLE MULTIVIBRATORS
DESCRIPTION
1:
AS
HCT
HC
LITERATURE
NUMBER
E
o
:e
.
CU
•
•
•
•
SDLDOOIA
G)
C
G)
(!)
D-TYPE OCTAL. 9·BIT, AND 10·BIT READ·BACK LATCHES
TECHNOLOGY
DESCRIPTION
NO. OF
BITS
TYPE
Edge-Triggered
Inverting and
Noninverting
Octal
'996
Octal
9-Bit
10·Bit
Octal
9-Bit
10·Bit
'990
'992
'994
'991
'993
'995
Octal
'666
•
Octal
'667
•
Transparent
True
Transparent
Noninverting
Transparent with
Clear and True
Outputs
Transparent
with Clear and
Inverting Outputs
•
•
...
!!!
A
B
TBA
STD
TTL
LS
S
ALS
•
•
•
•
•
•
•
AS
HC
HCT
LITERATURE
NUMBER
SDADOOIB
Denotes available technology.
Denotes planned new.
Denotes" A" suffix available in the technology indicated.
Denotes "B" suffix available in the technology indicated.
E
Denotes information To Be Announced.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265
'·27
FUNCTIONAL INDEX
OCTAL, 9-BIT, AND lO_BIT LATCHES
DESCRIPTION
NO, OF
BITS
TECHNOLOGY
OUTPUTS
TYPE
STD
TTL
LS
S
• •
•
'373
Transparent
OClal
ALS
AS
HC
HCT
'573
•
~
:J.
!!.
-....
Transparent
Octal
2-Stale
'116
•
...
• •
3-Stale
'873
6
'533
Inver,ing
Transparent
r+
O·
Octal
3-S1ate
A
3-State
'880
A
3-State
'604
DC
'607
Dual4-Bil
Inverting
Octal
Transparent
2-lnput
Multiplexed
Octal
2-State
'259
Addressable
Octal
True
lO-Bit
3-S1ate
True
9-Bit
3-State
True
Octal
3-State
'845
10-Bit
3-State
'842
9-Bit
3-State
'844
Octal
3-State
'846
Q only
Inverting
•
•
•
•
•6
'1843
SDFDOOl
SCAD001A
SDAD001B
SCLD001B
•
SDFDOOl
SCLD001B
SDAD001B
•
•
•
•
•
•
•
•
•
•
•
Denotes available technology.
A
Denotes planned new.
A
Denotes "Au suffix available in the technology indicated.
B
Denotes "B" suffix available in the technology indicated.
TBA := Denotes information To Be Announced.
1-28
•
SDLD001A
•
•
•
•
•
•
'843
SCLDOO16
TBA
SDLD001A
'4724
'1841
SCAD001A
SDAD001B
•
•
'841
SDFDOOl
SDLD001A
...
• •
• •
'580
SDADOO16
SDADOO16
• •
'11533
'563
SDFDOOl
SDADOO16
A
:J
•
SCLDOO16
""I
3$I)
SCLDOO16
•
• •
:J
0
NUMBER
T6A
•
• •
•
F
SDAD001B
•
'11373
Dual4-6it
BCT
3-State
Q
""I
ACT
SDLDOOlA
• •
6
~
LITERATURE
AC
. TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SCLD001B
SCLD001B
SDAD001B
SDAS130
SDAD001B
SDAS127
SDADOO16
FUNCTIONAL INDEX
REGISTERS
SHIFT REGISTERS
DESCRIPTION
BITS
Sign·
TYPE
S
S·
X
Protected
4
TECHNOLOGY
MODES
NO. OF
L
H
X
X
'322
STD
TTL
X
X
X
X
'194
X
X
X
X
'198
X
X
X
X
'299
S
ALS
LITERATURE
AS
•
•
A
•
•
•
8
ParalieHn
Parallel·ln
Serial· Out
Serial·ln
Serial·Out
NOTE: Modes; S·
X
'323
X
'95
X
X
'195
X
X
X
X
'295
8
X
X
X
X
8
X
4
5
Parallel·Out
X
X
Parallel·Out
Serial· In
X
X
X
'166
•
X
X
'674
X
16
X
8
X
'91
SDADOO1B
•
• •
SDADOO1B
•
•
•
•
A
A
•
•
SCLDOO1B
•
SDFDOO1
ca
..oE
~
.5
SDADOO1B
ca
SCLDOO1B
•
c:
o
~
SDLDOO1A
SDFDOO1
SDLDOO1A
SDADOO1B
.
CI)
C
CI)
~
SDLDOO1A
•
SCLDOO1B
SDLDOO1A
•
•
SCLDOO1B
SDLDOO1A
SDLDOO1A
•
A
X
X
8
NUMBER
SDLDOO1A
•
B
B
'165
'199
X
'164
L
•
•
•
•
•
X
= S·R, S = S·L,
A
'395
'96
F
SOLDOO1A
Bidirectional
X
HC
A
Parallel·ln
Parallel·Out
LS
SDLDOO1A
•
•
•
SCLDOO18
SDLDOO1A
SCLDOO18
SDLDOO1A
SCLDOO1B
SDLDOO1A
= Load, H = Hold
•
Denotes available technology.
...
Denotes planned new.
A
Denotes "A" suffix available in the technology indicated.
8 " Denotes "B" suffix available in the technology indicated.
TBA .. Denotes information To Be Announced.
TEXAS . "
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
1-29
FUNCTIONAL INDEX
SHIFT REGISTERS WITH LATCHES
TECHNOLOGY
NO. OF
DESCRIPTION
BITS
OUTPUT
4
3·State
Parallel·ln,
Parallel·Out
with Output
LS
TTL
'672
Buffered
'594
3·State
'595
OC
'599
16
2·State
'673
8
2·State
'597
Serial·ln
8
. with Output
Latches
Parallel·ln,
Serial·Out
with Input
S
LITERATURE
ALS
AS
•
•
•
•
•
•
•
'671
Latches
Parallel·Out
STD
TYPE
HC
NUMBER
SDLD001A
SDLD001A
•
SCLD001B
SDLD001A
SCLD0018
•
Latches
SDLD001A
Parallel 110
Ports with
Input Latches
8
•
'598
3·State
Multiplexed
Serial Inputs
SIGN·PROTECTED REGISTERS
DESCRIPTION
Sign·Protected
Registers
TECHNOLOGY
MOOES
NO. OF
TYPE
BITS
S·
8
X
S
L
H
X
X
STD
TTL
LS
'322
S
LITERATURE
ALS
AS
HC
A
NUMBER
SDLD001A
REGISTER FILES
TECHNOLOGY
DESCRIPTION
OUTPUT
TYPE
STD
LS
Dual 16 Words X
4 Bits
4 Words X 4 Bits
8 Words X 2 Bits
64 Words X 40
Bits
3·State
AS
'870
&
'871
&
•
OC
'170
3·State
'670
3·State
'172
3·State
'8834
•
•
S
•
•
Denotes available technology.
Denotes planned new.
A
Denotes" A" suffix available in the technology indicated.
B !!Ii Denotes "B" suffix available in the technology indicated.
TBA i: Denotes information To Be Announced.
1-30
•
9!
TEXAS . "
INSTRUMENTS
POST OFfiCE BOX 655012 • DALLAS, TEXAS 75265
HC
NUMBER
SDAD0018
SDLD001A
&
•
..
LITERATURE
ALS
TTL
TBA
FUNCTIONAL INDEX
OTHER REGISTERS
TECHNOLOGY
OESCRIPTION
TYPE
STO
TTL
Quadruple
Multiplexers
'298
•
lS
S
AlS
•
Shift Registers
Quadruple Bus
Buffer Register
'173
Data Selector!
Multiplexer!
•
'299
'356
•
•
A
'963
Shift Register
'964
8-Bit
Diagnosticl
Pipeline
Register
BCT
NUMBER
SDAOOO18
•
SClOOO1B
SDlDOO1A
•
SDADOO1B
SDLDOO1A
•
•
SClDOO1B
SDlDOO1A
Register
Dual-Rank 8-Bit
HC
SDlDOO1A
•
with Storage
a-Bit Universal
LITERATURE
AS
...
...
•
•
'819
'29818
•
SClDOO1B
SDVDOO1
SDAS105
...
c
o
"';:;
CO
-E
...
o
c
TBA
•
Denotes available technology .
.&.
Denotes planned new.
A
Denotes" A" suffix available in the technology indicated.
B
Denotes "B" suffix available in the technology indicated.
TBA == Denotes information To Be Announced.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-31
FUNCTIONAL INDEX
COUNTERS
SYNCHRONOUS COUNTERS - POSITIVE·EDGE TRIGGERED
DESCRIPTION
PARALLEL
LOAD
TECHNOLOGY
TYPE
STD
LS
TTL
•
S
ALS
Decade
CD
:::s
A
•
'162
B
•
•
CD
i-
'560
S'
Sync
...3ci'
I»
'168
'190
Decade ·Up/Down
:::s
Async
'192
Sync
•
•
•
•
•
Sync
A
•
•
•
'669
'691
'693
'8161
'8163
•
..
A
B
TBA
'·32
SDFDOOl
SDLOO01A
SDADOO1B
SCLDOO1B
•
SDFDOOl
SDADOO1B
SDAD001B
SDFDOOl
SDLDOO1A
SDAD001B
SCLD001B
SDLD001A
SDADOO1B
•
...
B
'561
•
•
•
•
SCLDOO1B
SDAD001B
•
SDFDOOl
SDLDOO1A
SDLD001A
SDAD001B
•
A
'163
SDAD001B
SCLDOO1B
•
•
B
'161
4·Bit Binary
•
•
•
•
A
•
NUMBER
SDLDOO1A
B
A
'568
'696
•
A
•
'692
d'
...
F
SDLD001A
B
•
Sync
HC
A
'160
G)
LITERATURE
AS
•
SCLDOO1B
•
SDFDOOl
SDLDOO1A
SDAD001B
SCLD001B
•
SDFDOOl
SDAD001B
SDLD001A
SDLD001A
SDLD001A
•
•
Denotes available technology.
Denotes planned new.
Denotes" A" suffix available in the technology indicated.
Denotes "8" suffix available in the technology indicated.
= Denotes information To Be Announced.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SDASl16
SDAS104
FUNCTIONALINUEX
SYNCHRONOUS COUNTERS - POSITIVE-EDGE TRIGGERED (continued)
DESCRIPTION
PARALLEL
LOAD
TECHNOLOGY
TYPE
STD
LS
TTL
'191
Async
'193
•
•
'169
Divide-By-8
Johnson Counter
Async CLR
'867
Sync CLR
'869
F
NUMBER·
SDAD0016
•
•
•
B
•
•
'8169
Johnson Counter
•
'569
'699
Up/Down
Divide-By-10
HC
SCLD001B
SDLD001A
SDAD001B
•
•
SCLD001B
SDLD001A
SDAS001B
A
'697
8-Bit
LITERATURE
AS
SDLD001A
•
B
Sync
ALS
•
4.~Bjt Binary
UplDown
S
•
SDFDOOl
•
SDFD001
SDAD001B
SDLD001A
•
•
•
SDAS117
•
•
SDVD001
CO
...
Q)
C
•
'4017
c
o
ca
E
...o
.5
"';:;
Q)
SCLD001B
~
•
'7022
•
,Denotes available technology.
...
Denotes planned new.
A
Denotes" A" suffix available in the technology indicated.
B
Denotes "8" suffix available in the technology indicated.
TBA ;: Qenotes information To Be Announced.
·
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 .. DALLAS, TEXAS 75265
1-33
FUNC1I10NAL INDEX
ASYNCHRONOUS COUNTERS (RIPPLE CLOCK) - NEGATIVE-EDGE TRIGGERED
DESCRIPnON
Decade
4-Bit Binary
PARALLEL
LOAD
Set-to-9
Ves
Ves
Set-to-9
None
Ves
Yes
None
Divide-By-12
Dual Decade
Dual4-Bit
Binary
7 -Bit Binary
12-Bit Binary
14-Bit Binary
TECHNOLOGY
TYPE
STD
TTL
'90
'176
'196
'290
'93
'177
'197
'293
'92
'390
Set-to-9
'490
None
'393
A
•
•
A
A
LS-
S
•
•
•A
•
•
•
•A
•
•
•
•
•
•
•
•
•
ALS
HC
LITERATURE
NUMBER
SDLD001A
•
'4024
'4040
'4020
'4060
'4061
• .. Denotes available technology.
.. s Denotes planned new.
A . • Denotes "A" suffix available in the technology indicated.
B • Denotes "B" suffix available in the tech'nology indicated.
TBA IE Denotes information To Be Announced.
1-34
AS
TEXAS ."
INSTRUMENTS
POST OFFice BOX 655012 • OALLAS, TEXAS 75265
•
•
•
•
•
•
•
•
SDLD001A
SCLDOO1B
SCLDOO1B
SDLD001A
SDLD001A
SCLDOO1B
SCLD001B
FUNCTIONAL INDEX
B-BIT BINARY COUNTERS WITH REGISTERS
OESCRIPTION
Parallel
Register
Outputs
PARALLEL
LOAD
TECHNOLOGY
TYPE
STD
LS
TTL
3-State
'590
DC
'591
2-State
'592
3-State
'593
Inputs
Parallel liD
ALS
LITERATURE
AS
•
•
•
•
Parallel
Register
S
HC
NUMBER
SDLDOO1A
•
SCLD001B
SDLD001A
c
o
"';;
CO
FREQUENCY DIVIDERS, RATE MULTIPLIERS
TECHNOLOGY
DESCRIPTION
TYPE
STD
TTL
60-Bit Binary
Rate Multiplier
Decade Rate
Multiplier
'97
'167
LS
S
ALS
AS
•
•
LITERATURE
HC
HCT
NUMBER
E
...
-o
c
SDLD001A
Programable
Frequency
•
'282
Dividers/Digital
Timers
•
..
A
8
TBA
'284
•
SDAD001B
SDLD001A
Denotes available technology.
Denotes planned new.
Denotes "A" suffix available in the technology indicated.
Denotes "8" suffix available in the technology indicated.
;:: Denotes information To Be Announced.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-35
FUNCTIONAL INDEX
PROGRAMMABLE LOGIC ARRAYS
STANDARD HIGH-SPEED PAL$ CIRCUITS (ALSI
TYPE
INPUTS
PAl16lBA
PAl16R4A
PAl16R6A
PAl16RBA
PAl16R6A-2
PAl16R4A-2
OUTPUTS
TYPE
NO.
B
4
Active Low
6
Registered
B
16
8
4
Active low
Registered
PAl16R6A-2
6
PAl16R8A-2
8
PAl20l8A
PAl20R4A
8
4
Active low
6
Registered
Active low
PAl20R4A-2
8
8
4
PAl20R6A-2
PAl20R8A-2
6
B
PAl20R6A
PAl20R8A
PAl20l8A-2
20
NO. OF
PINS
20
PACKAGES
LITERATURE
NUMBER
FK.FN.J.N
SDZD001B
24
FK.FN.JT.NT
Registered
HIGH PERFORMANCE PAl® CIRCUITS (AlSI
TYPE
INPUTS
TIBPAl16l8-10
TIBPAl16R4-10
OUTPUTS
NO.
8
6
TIBPAl16RB-10
TIBPAl16lB-12
B
TIBPAL16R4-12
nBPAl16R6-12
TIBPAl16RB-12
TIBPAl16HB-15
16
B
4
Active High
6
Register
Active High
B
20
4
6
TIBPAl16RB-15
B
LITERATURE
NUMBER
nBPAl16HB-25
TIBPAl16HDB-25
FK.FN.J.N
TBA
SDZDOO1B
TBA
Registered
SDZDOOIB
B
Active High
TBA
B
Active low
•
Denotes available technology.
...
Denotes planned new.
A
Denotes "A" suffix available in the technology indicated.
Denotes "8" suffix available in the technology indicated.
B
TBA == Denotes information To Be Announced.
PAL is a registered trademark of Monolithic Memories Inc.
1-36
PACKAGES
SDZD001B
Active Low
TIBPAl16lDB-15
TIBPAl16R4-15
TIBPAl16R6-15
TIBPAl16lDB-25
PINS
Register
nBPAL16lB-15
TIBPAl16lB-25
NO. OF
4
TIBPAl16R6-10
TIBPAl16HDB-15
TYPE
Active High
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SDZD001C
TBA
FUNCTIONAL ·INDEX
HIGH PERFORMANCE PAL' CIRCUITS (ALSI (continuedl'
TYPE
INPUTS
TIBPAL16R4-25
OUTPUTS
NO.
S
TIBPAL16RB-25
B
16
TIBPAL 16R4-30
6
B
TIBPAL20LB-15
S
TIBPAL20R4-15
4
TIBPAL20RS-15
6
TIBPAL20RB-15
S
TIBPAL20LB-25
B
TIBPAL20R4-25
4
TIBPAL20R6-25
S
TIBPAL20RB-25
B
20
TIBPAL20X4-20
Active Low
LITERATURE
NUMBER
20
FK,FN,J,N
SDZD001B
Registered
c
Active Low
o
"';::
«J
Registered
E
Active Low
SDZD001B
Registered
10
....o
c
Active Low
4
TIBPAL20XB-20
B
TIBPAL20X 10-20
10
TIBPAL20L 10-30
10
TIBPAL20X4-30
4
TIBPAL20XS-30
B
TIBPAL20X 10-30
10
TIBPALR19LB
B
TIBPALR 19R4
4
TlBPALR19RS
TIBPALT19LB
PACKAGES
Registered
B
TIBPAL 16RB-30
TIBPALR 19RB
PINS
4
TIBPAL 16RS-30
TIBPAL20L 10-20
NO. OF
4
TIBPAL 1SR6-25
TIBPAL 16LS-30
TYPE
Registered
TIBPALT19R4
FK,FN,JT,NT
TBA
Registered
Active Low
Registered
6
19
24
Active Low
S
SDZD001B
Active Low
B
4
TIBPALT19RS
6
TlBPALT19RS
B
Registered
HIGH PERFORMANCE CMOS PAL' CIRCUITS
TYPE
INPUTS
TICPAL 1 SLS-55
TICPAL 1SR4-55
TICPAL 1SRS-55
TICPAL 16RS-55
•
..
A
8
TBA
16
OUTPUTS
NO.
TYPE
B
Active High
NO. OF
PINS
4
20
Register
S
PACKAGES
JL,N
LITERATURE
NUMBER
TBA
B
Denotes available technology.
Denotes planned new.
Denotes ·'A" suffix available in the technology indicated.
Denotes "S" suffix available in the technology indicated.
!5 Denotes information To Be Announced.
PAL is a registered trademark of Monolithic Memories Inc.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-37
FUNCTIONAL INDEX
HIGH PERFORMANCE IMPACt PROGRAMMABLE ARRAY LOGIC
..
TYPE
OUTPUTS
INPUTS
TIBPAL22Vl0
NO.
NO. OF
TYPE
PACKAGES
PINS
12 Inputs or
TIBPAL22Vl0A
11 Inputs
TIBPAL22Vl0A
with eLK
24
110
10
NT,FN
LITERATURE
NUMBER
SDPS015
SDPS106
FIELD PIIOGRAMMABLE LOGIC ARRAY (ALS)
TYPE
C)
CD
INPUTS
OUTPUTS
NO.
TIFPLA839
..
-....
..3
:::s
TIFPLA840
CD
TIB82S167B
!!.
:::s
82S105A
ARRAY
PINS
3-State
14
PACKAGES
8
NI,IMBER
FK,FN,N,NT
24
SDZDOOIA
3-State
16
LITERATURE
14x32x6
oe
6
82S167A
TIB82S105B
NO. OF
TXPI;
14x48x6
3-State
28
3-State
FK,FN,JD,N
o
BIPOLAR MEMORY
CI)
r+
o·:::s
FIRST-IN FIRST-OUT MEMORIES (FIFOs)
TYPE
DESCRIPTION
TECHNOLOGY
OF
TYPE
3-State
'222
3-State
'224
3-State
'232
oe
'227
oe
'22B
3-State
'225
3-State
'229
3-State
'234
3-State
'233
64 Words x 4 Bits
3-State
'236
64 Words x 5 8its
3-State
'235
STD
TTL
16 Wordsx4 Bits
16 Words x 5 Bits
•
ALS
AS
LS
S
HC
•
•
A
•
•
A
PACKAGES
LITERATURE
NUMBER
J,N
D,N,FK,FN
J,N
•
•
•
A
•
Denotes availabie technology.
...
Denotes planned new.
A
Denotes" A" suffix available in the technology indicated.
B
Denotes "B" suffix available in the technology indicated.
TBA ;;;;;; Denotes information To 8e Announced.
1-38
HCT
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SDVDOOI
J,N
DW,FK,FN
DW,J,FK,FN
SDAS106
DW,FK,FN,J,N
SDVDOOI
DW,J,FK,FN
SDAS107
DW,FN,FK,N
SDAS10B
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
INTRODUCTION
These symbols, terms, and definitions are in accordance with those currently agreed upon by the JEDEC
Council of the Electronic Industries Association (EIA) for use in the USA and by the International
Electrotechnical Commission (IEC) for international use.
OPERATING CONDITIONS AND CHARACTERISTICS (IN SEQUENCE BY lETTER SYMBOLS)
f max
Maximum clock frequency
The highest rate at which the clock input of a bistable circuit can be driven through its required
sequence while maintaining stable transitions of logic level at the output with input conditions
established that should cause changes of output logic level in accordance with the specification.
c
o
'';::;
ICC
Supply current
The current into' the VCC supply terminal of an integrated circuit.
ICCH
Supply current, outputs high
The current into' the VCC supply terminal of an integrated circuit when all (or a specified number)
of the outputs are at the high level.
ICCl
Supply current, outputs low
The current into' the VCC supply terminal of an integrated circuit when all (or a specified number)
of the outputs are at the low level.
IIH
High-level input current
The current into' an input when a high-level voltage is applied to that input.
III
low-level input current
The current into' an input when a low-level voltage is applied to that input.
10H
High-level output current
The current into' an output with input conditions applied that, according to the product
specification, will establish a high level at the output.
IOl
low-level output current
The current into' an output with input conditions applied that, according to the product
specification, will establish a low level at the output.
lOS
Short-circuit output current
The current into' an output when that output is short-circuited to ground (or other specified
potential) with input conditions applied to establish the output logic level farthest from ground
potential (or other specified potential).
102
Off-state (high-impedance-state) output current (of a three-state output I
The current flowing into' an output having three-state capability with input conditions established
that, according to the production specification, will establish the high-impedance state at the output.
ta
Access time
The time interval between the application of a specified input pulse and the availability of valid
signals at an output.
ca
...oE
.5
ca...
Q)
C
Q)
e,:,
*Current out of a terminal is given as a negative value.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-39
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
C)
tdis
Disable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms,
with the three-state output changing from either of the defined active levels (high or low) to a
high-impedance (off) state. (tdis = tPHZ or tPLZ).
ten
Enable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms,
with the three-state output changing from a.high-impedance (off) state to either of the defined
active levels (high or low). (ten = tpZH or tPzLl.
tf
Fall time
The time interval between two reference points (90% and 10% unless otherwise specified) on
a waveform that is changing from the defined high level to the defined low level.
th
Hold time
The time interval during which a signal is retained at a specified input terminal after an active
transition occurs at another specified input terminal.
NOTES: 1. The hold time is the actual time interval between two signal events and is determined
by the system in which the digital circuit operates. A minimum value is specified that
is the shortest interval for which correct operation of the digital circuit is guaranteed.
CD
~
CD
!.
3"
...0
3CI)
r+
2. The hold time may have a negative value in which case the minimum limit defines
0'
the longest interval (between the release of the signal and the active transition) for
which correct operation of the digital circuit is guaranteed.
~
tpd
Propagation delay time
The time between the specified reference points on the input and output voltage waveforms with
the output changing from one defined level (high or low) to the other defined level. (tpd = tpHL
or tpLH).
Propagation delay time, high-to-Iow level output
The time between the specified reference points on the input and output voltage waveforms with
the output changing from the defined high level to the defined low level.
Disable time (of a three-state output) from high level
The time interval between the specified reference points on the input and the output voltage
waveforms with the three-state output changing from the defined high level to a high-impedance
(off) state.
Propagation delay time, low-to-high-Ievel output
The time between the specified reference points on the input and output voltage waveforms with
the output changing from the defined low level to the defined high level.
Disable timE! (of a three-state output) from low level
The time interval between the specified reference points on the input and output voltage waveforms
with the three-state output changing from the defined low level to a high-impedance (off) state.
.1-40
tPZH.
Enable time (of a three-state output) to high level
The time interval between the specified reference points on the input and output voltage waveforms
with the three-state output changing from a high-impedance (off) state to the defined high level.
tpZL
Enable time (of a three-state output) to low level
The time interval between the specified reference points on the input and output voltage waveforms
with the three-state output changing from a high-impedance (off) state to the defined low level.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
tr
Rise time
The time interval between two reference points (10% and 90% unless otherwise specified) on
a waveform that is changing from the defined low level to the defined high level.
tsu
Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent
active transition at another specified input terminal.
NOTES: 1. The setup time is the actual time interval between two signal events and is determined
by the system in which the digital circuit operates. A minimum value is specified that
is the shortest interval for which correct operation of the digital circuit is guaranteed.
2. The setup time may have a negative value in which case the minimum limit defines
c
the longest interval (between the active transition and the application of the other
signal) for which correct operation of the digital circuit is guaranteed.
"';::;
CO
Transition time (general)
The time interval between two reference points (10% and 90% unless otherwise specified) on
a waveform that is changing from the defined low level to the defined high level (rise time) or from
the defined high level to the defined low level (fall time).
o
E
...o
.5
Pulse duration (width)
The time interval between specified reference points on the leading and trailing edges of the pulse
waveform.
VIH
High-level input voltage
An input voltage within the more positive (less negative) of the two ranges of values used to
represent the binary variables.
NOTE: A minimum is specified that is the least-positive value of high-level input voltage for which
operation of the logic element within specification limits is guaranteed.
VIL
Low-level input voltage
An input voltage level within the less positive (more negative) of the two ranges of values used
to represent the binary variables.
NOTE: A maximum is specified that is the most-positive value of low-level input voltage for which
operation of the logic element within specification limits is guaranteed.
VOH
High-level output voltage
The voltage at an output terminal with input conditions applied that, according to the product
specification, will establish a high level at the output.
VOL
Low-level output voltage
The voltage at an output terminal with input conditions applied that, according to the product
specification, will establish a low level at the output.
VT +
Positive-going threshold level
The voltage level at a transition-operated input that causes operation of the logic element according
to specification as the input voltage rises from a level below the negative-going threshold voltage,
VT-·
VT _
Negative-going threshold level
The voltage level at a transition-operated input that causes operation of the logic element according
to specification as the input voltage falls from a level above the positive-going threshold voltage,
VT+·
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-41
G)
CD
:::s
...
CD
Q)
:::s
o...
3Q)
r+
o·
:::s
1-42
EXPLANATION OF FUNCTION TABLES
The following symbols are used in function tables on TI data sheets:
H
high level (steady state)
L
low level (steady state)
t
transition from low to high level
transition from high to low level
o
value/level or resulting value/level is routed to indicated destination
value/level is re-entered
x
irrelevant (any input, including transitions)
Z
off (high-impedance) state of a 3-state-output
a .. h
o
the level of steady-state inputs at inputs A through H respectively
a
00
level of
00
complement of QO or level of
were established
an
level of
...E
before the indicated steady-state input conditions were established
a before the
Sl..
one high-level pulse
l...S
one low-level pulse
TOGGLE
c
"';::
CO
0
before the indicated steady-state input conditions
o
.E
~
'ii
...
most recent active transition indicated by ~ or t
Q)
C
Q)
each output changes to the complement of its previous level on each active transition
C!)
indicated by ~ or t
If, in the input columns, a row contains only the symbols H, L, and/or X, this means the indicated output
is valid whenever the input configuration is achieved and regardless of the sequence in which it is achieved.
The output persists so long as the input configuration is maintained.
If, in the input columns, a row contains H, L, and/or X together with t and/or ~, this means the output
is valid whenever the input configuration is achieved but the transition(s) must occur following the
achievement of the steady-state levels. If the output is shown as a level (H, L, QO, or 00), it persists
so long as the steady-state input levels and the levels that terminate indicated transitions are'maintained.
Unless otherwise indicated, input transitions in the opposite direction to those shown have no effect at
the output. (If the output is shown as a pulse, nor U , the pulse follows the indicated input transition
and persists for an interval dependent on the circuit.)
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-43
EXPLANATION OF FUNCTION TABLES
Among the most complex function tables in this book are those of the shift registers. These embody most
of the symbols used in any of the function tables, plus more. Below is the function table of a 4-bit
bidirectional universal shift register, e.g., type SN74194.
FUNCTION TABLE
INPUTS
CLEAR
:s
...e.CD
-s
:....
o...
3
....
c)"
Q)
:s
CLOCK
OUTPUTS
SERIAL
PARALLEL
LEFT
RIGHT
A
B
C
X
X
X
H
L
1
H
X
X
X
X
X
a
X
X
X
X
X
X
X
t
t
t
X
X
X
X
X
X
X
c
X
X
X
X
X
S1
SO
X
X
X
H
X
X
H
H
H
H
L
H
H
L
H
H
H
H
L
t
L
H
L
L
X
X
L
C)
CD
MODE
L
H
L
b
X
X
X
X
X
0
X
X
QA
QB
Qc
Qo
L
L
L
L
OAO aBO OCO 000
d
a
X
X
X
X
X
H
b
OAn
L
OAn
OBn OCn
OBn QCn
QAO QBO
c
d
OBn OCn
OBn °Cn
H
OOn
L
QDn
QCO QDO
The first line of the table represents a synchronous clearing of the register and says that if clear is low, all
four outputs will be reset low regardless of the other inputs. In the following lines, clear is inactive (high)
and so has no effect .
. The secOnd line shows that so long as the clock input remains low (while clear is highl, no other input has
any effect and the outputs maintain the levels they assumed before the steady-state combination of clear
high and clock low was established. Since on other lines of the table only the rising transition of the clock
is shown to be active, the second line implicitly shows that no further change in the outputs will occur while
the clock remains high or on the high-to-Iow transition of the clock.
The third line of the table represents synchronous parallel loading of the register and says that if S 1 and SO
are both high then, without regard to the serial input, the data entered at A will be at output QA, data entered
at B will be at QB, and so forth, following a low-to-high clock transition.
The fourth and fifth lines represent the loading of high- and low-level data, respectively, from the Shift-right
serial input and the shifting of previously entered data one bit; data previously at QA is now at QB, the previous
levels of QB and QC are now at QC and QD respectively, and the data previously at QD is no longer in the
register. The entry of serial data and shift takes place on the low-to-high transition of the clock when Sl
is low and SO is high and the levels at inputs A through D have no effect.
The sixth and seventh lines represent the loading of high- and low-level data, respectively, from the shift-left
serial input and the shifting of previously entered data one bit; data previously at QB is now at QA, the previous
levels of QC and QD are now at QB and QC, respectively, and the data previously at QA is no longer in the
register. This entry of serial data and shift takes place on the low-to-high transition of the clock when S 1
is high and SO is low and the levels at inputs A through D have no effect.
The last line shows that as long as both mode inputs are low, no other input has any effect and, as in the
second line, the outputs maintain the levels they assumed before the steady-state combination of clear high
and both mode inputs low was established.
1-44
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74, 54LS/74LS, 54S/74S
VCC
'~"'{
CONDITIONS
(Se. Test Tabl.
and Not.)
TEST TABLE
OPENCOLLECTOR
OUTPUTS
IOH
FUNCTION
4--(+)
VOH
TOTEM-POLE
+IOH
+t
)NPUT CONDITIONS
Input under test at VIL max, ali others at 4.5 V
AND
All inputs at VIH min
NOR
All inputs at VIL max
OR
(-)
'=-
NAND
Input under test at VIH min, all others at GND
AND-OR
Inputs under test (a set including one input of
INVERT
each AND gate) at VIL max, all others at 4.5 V
All inputs of AND gate under test
AND-OR'
at VIH min. all others at GND
E
...
....o
FIGURE 1. VIH. VIL. VOH, IOH
.5
VCC
TEST TABLE
FUNCTION
IOL
NAND
4--(+)
ca...
CD
C
CD
Input under test at VIL max, all others at 4.5 V
(!)
Input under test at VIH min, others at GND
NOR
OR
All inputs at VIL max
AND-DR-
All inputs of AND gate under test
INVERT
NOTE: For functions having three-state outputs, input conditions
are maintained which will cause the outputs to be enabled
(low-impedance).
INPUT CONDITIONS
All inputs a1 VIH min
AND
o
lU
NOTE: For functions having three-state outputs, input conditions
are maintained which will cause the outputs to be enabled
(low-impedance) .
INPUT {
CONDITIONS
IS•• Test Tabl.
and Not.)
c
.~
at VIH min, all others at GND
Inputs under test (a set including one input of
AND-DR
each AND gate) at VIH min, all others at 4.5 V
FIGURE 2. VIH, VIL. VOL
Vee
liar IIH
1+)----+
VI - - - - " - - - - 1
OUTPUTIS)
OPEN
REMAINING {
INPUTS
OPEN
REMAINING
INPUTS
(S•• Not. B)
OUTPUTlS)
OPEN
'=NOTE: Each input is tested separately.
FIGURE 3. VI
NOTES: A. Each input is tested separately.
B. When testing AND-OR-INVERT or AND-OR gates,
each AND gate is tested separately with inputs of AND
gates not under ~est open when testing II and
grounded when testing IIH'
FIGURE 4. II, IIH
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
1-45
PARAMETER MEASU.REMENT INFORMATION
SERIES 54/74. 54LS/74LS. 54S/74S
4.5V
VCC
REMAINING
INPUTS
•
OUTPUT(S)
OPEN
NOTES: A. Each input is tested separately.
B. When testing AND-OR-INVERT or AND-OR gates. each AND
gate is tested separately with input of AND gates not under test
-=
G)
CD·
:::I
CD
open.
FIGURE 5. IlL
...e!..
TEST TABLE
-
FUNCTION
VCC
:::I
o
All inputs at GND
AND
All inputs at 4.5 V
,~,{
3I»
....
CONDITIONS
(5•• Test Tabl •
0"
.!
AU inputs at GND
OR
All inputs at 4.5 V
All inputs at GND
AND-OR
All inputs at 4.5 V
Vo
-=
NOR
AND-OR-INVERT
and Note)
:::I
INPUT CONDITIONS
NAND
NOTE: For functions having three-state
outputs, input conditions are maintained which will cause the outputs
to be enabled (low-impedance).
-=
FIGURE 6. lOS. 10
TEST TABLE
(+)
VCC
FUNCTION
NAND
ICC!
INPUT{
CONDITIONS
(5•• Test Tabl.
and Nota)
OUTPUT(S)
OPEN
AND
All inputs at 4.5 V
NOR
All inputs at GND
INPUT CONDITIONS FOR 'CCL
All inputs at 4.5 V
One input at 4.5 V
OR
all others at GND
AND-OR-INVERT
AND-OR
-=
INPUT CONDITIONS FOR ICCH
All inputs at GND
All inputs at GND
All inputs of one AND gate
at 4.5 V. all others at GND
All inputs at GND
One input at 4.5 V.
all others at GND
All inputs at GND
All inputs of one AND gate
at 4.5 V. all others at GND
All inputs at GND
NOTE: ICC is measured simultaneously for all functions in a package. The average-per-gate values are calculated
from the appropriate one of the following equations.:
total ICC. ICCH. or ICCl
ICC. ICCH. or ICCl (average per gate or flip-flop)
ICC (average per gate. 50% duty cycle)
(number of gates or flip-flops in package)
fCCH + fCCl
2 (number of gates in package)
FIGURE 7. ICC
1-46
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012·. DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74. 54LS/74LS. 54S/74S
VT+
-----l
-1
':'
c
o
FIGURE 8, VT +. IT +. VOL
(FOR NAND SCHMITT TRIGGERS)
FIGURE 9, VT -. IT -. VOH
(FOR NAND SCHMITT TRIGGERS)
NOTES: A, Switches are in position 1 for SN54'/SN74'
B, The IX limit for SN54' and SN74' circuits may be
verified by an alternate equivalent procedure. The
VXX source is replaced by a resistor (see table
below) in parallel with a voltmeter between the X
and X pins. If the measured voltage, VXX. is less
than 0.4, the specified limit for IX is met.
Vcc
OPEN
IOL
02
+-(+)
"';:;
..oE
-co..
C'CJ
c
Q)
C
Q)
(!)
':'
RESISTANCE VALUE TABLE
SN5423
1140
SN5450, SN5453
13B 0
SN7423
1050
SN7450, SN7453
1300
FIGURE 10, IX (FOR EXPANDABLE GATES)
Vcc
Vcc
IOL
IOH
4--(+)
H-+
':'
RXX
':'
+
VBE (a)
*
.,27 kn
(Adjust IX)
FIGURE 11, VBE(Q) (FOR EXPANDABLE GATES)
IT
FIGURE 12, VOH (FOR EXPANDABLE GATES)
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-47
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74. 54LS174LS. 54S/74S
Vee
Vee
4.5 V
10L
+-1+)
Vx -+---1_-)....
-o
Vx
IX
FIGURE 13. VOH IFOR EXPANDABLE GATES)
:J
...
+-(_)
IX
FIGURE 14. VOL IFOR EXPANDABLE GATES)
IX
3
C»
.2-1+)
4--(+)
Vee
vi(
r+
s·:J
-r
Vx
VIL
FIGURE 15. ON-STATE CHARACTERISTICS
FOR EXPANDERS
RX
FIGURE 16. OFF-STATE CHARACTERISTICS
FOR EXPANDERS
Vee
Vee
IX
4--(+)
Vx
VIL
FIGURE 17. ON-STATE CHARACTERISTICS
FOR EXPANDERS
ISee Notes { : OTHER
2 and 3)
_ INPUTS
To VIH or VIL { lSee Note 1)
-
OUTPUT
CONTROL
INPUTS
FIGURE 18. OFF-STATE CHARACTERISTICS
FOR EXPANDERS
10(011)
NOTES:
+ - (+)
(See Note 21
(-1--.
lSee Note 3)
Vo
~
1. Input conditions are maintained which will ensure that
the three-state outputls) is lare) disabled to the highimpedance state. See function table or logic for the
particular device.
2. When testing for current into the output with a high·level
output voltage. input conditions are applied that would
cause the output to be low if it were enabled.
3. When testing for current out of the output with a lowlevel output voltage, input conditions are applied that
would cause the output to be high if it were enabled.
FIGURE 19. IO(off) (THREE-STATE OUTPUTS)
1-48
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 and 545/745
TEST
POINT
TEST
POINT
VCC
VCC
FROM OUTPUT
UNDER TEST
FRDMOUTPUT
UNDER TEST
lSee Noto BI
I
CL
lSe. Not. AI
I
FROM OUTPUT
UNDER TEST
TEST
POINT
lSee NotoBI
CL
lSee Noto AI
.,..
LOAD CIRCUIT FOR
BI-STATE
TOTEM-I'OLE OUTPUTS
3V
OV
HIGH-LEVEL
PULSE
_t
---1: ... .
:+---3V
1.5V
1.5V
~
0V
I
IN.pHASE
OUTPUT
I
I
\1.5;--3V
I
tPHL~
OUT'()F.pHASE
=:~:FI
\
~tpLH
1 , .5 V
CONTRO~
(Low-laval
OV
~tPHL
-i,.-....I-~j--- VOH
/1 5 V I
)L,s ~
.
.
I
~
I
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
onablingl
~'.5V
,""
_ _ _ _ _ _ __
..--tpZL ~
----.-
VOL
--t:.~----~tpLZ
I
I
WAVEFORM 1 I SI closod,
ISea Nota C)
I S2 open
-l---"4.5V
1_5 V
~tPZH~
I
I
WAVEFORM 2
51 opon,
(Sea Not.o.C.I_ _52_c.IO.sod_,.J:_ ~ ~
I
I
I
: J-i
I
I
F
1.5I
V VOH
-
~
w
VOLTAGE WAVEFORMS
PULSE WIDTHS
tPLW*-1-
C!1
\,1.5 V t " . 5 V
OUTPUT7"""'\.
INPUT J 1 5 V
CD
C
CD
W
LOW-LEVEL
PULSE
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
-
~'_5V
t.tup~thold
DATA
INPUT
.
.
E
o
.5
"ii
LOAD CIRCUIT FOR
THREE-STATE OUTPUTS
LOAD CIRCUIT FOR
OPEN-COLLECTOR OUTPUTS
I!+-~~ ____
c
o
CO
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1 N3064 or equivalent.
TIMING
INPUT
.
"
-
tPHZ*-+!
~0V
OV
S1and
52 closod
~1.5V
~--- VOL
0.5 V
----':Ill1[-l
:
3V
r
O•5 V
_1. _ _ VOH
"'.5 V
S1 and
52 closed
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS
NOTES: C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
E. All input pulses are supplied by generators having the following characteristics: PRR s 1 MHz, Zout .. 50 II and:
For Series 54/74, tr S 7 ns, tf S 7 ns.
For Series 5451745, tr S 2.5 ns, tf S 2.5 ns.
F.· When measuring propagation delay times of 3-state outputs, switches 51 and 52 are closed.
G. The outputs are measured one at a time with one input transition per measurement.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
1-49
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS!74LS
TEST
POINT
TEST
POINT
Vec
VCC
fROM OUTPUT
UNOER TEST
RL
FROM OUTPUT
UNOER TEST
TEST
POINT
(See Note B)
CL
J(SeeNotlA)
LOAD CIRcUIT FOR
,
BI·BTATE
TOTEM.pOLE OUTPUTS
LOAI;) CIRCUIT FOR
THREE·STATE OUTPUTS
LOAD CIRCUIT FOR
OPEN-COLLECTOR OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1 N3064 or equivalent.
t
TIMING
INPUT
.-
3V
1.3V
- - - - - OV
HIGH·LEVEL
PULSE
~13V
~
LOW·LEVEL
PULSE
.L1•3V
\;:;;- -
I
I
,
"
~tPHL
1.3V
tPHL ~
OUT·Of·PHASE
~~!~~ef)
3V
I.
tPLH~
IN.pHASE
OUTPUT
\1.3V
:
1
1
OV
i;:3-;:
VOH
~
VOL
F
~1.3V··
~
~
•.~.
3V
OUTPUT:--\.
CONTRO~
(Low·I••el
1\ 1.3 V
I'"- - -.....- - -
I4--tpZL--+t
~tpLZ
I
WAVEFORM 1
I
1
1 1
~'
--"4.5V
) SS2 _Cloood
1.3 V
n '
(See Note CI
I
I
VOH
VOL
J.l.3V
T-------OV
enabling)
It----*-tpLH
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1\::..:...
VOLTAGE WAVEFORMS
PULSE WIDTHS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
--/0
.
~tw~
:t--":"3V
1.3V
1.3V
~
OV
IIATA.
INPUT
INPUT
•• ~ •
_tw~
tl8tUp~thold
WAVEFORM 2
I
t
:
ISland
I
S2 closed
I
A:ll.5V
VOL
i
1="'-___
I4--tPZH~
tPHZ-M---+!
0.5 V
I
:
£0.5 V
Slopen,
I
(See Note
S2;....0_
cI sed...._ ._ _
1.3_
V ,.
_C)_ _.....
-----\-i -]Ii
°
V
- - VOH
1 SI and II1I::I1.5 V
S2 closed
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE·STATE OUTPUTS'
NOTES: C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. In the examples abovtt, the phase relationships between inputs and outputs have been chosen arbitrarily.
E. All input pulses are supplied by generators having the foltowing characteristics: PRR :s 1 MHz, Zout ~ 50 II and for Series
54LS/74LS, tr :s 1.5 ns, tf :s 2.6 ns.
F. When measuting propagation delay times of 3-state outputs, switches Sl and S2 are closed.
G. The outputs are measured one at a time with one input transition per measurement .
'·50
. TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
TYPICAL CHARACTERISTICS
SERIES 54/74t
HIGH·lEVEl OUTPUT VOL TAGE
OUTPUT VOLTAGE
"
3.5
=t
vcc- sv
TA-1zsoe
.5
2.0
~
1.5
~
1.0
3.•
•
~
TAi"'c -
!
TA· ....... C
1- ~ \
vcc- sv
~
II
0.20.' D.' 0.8 1 1.2 1A 1.&
VI-InpUt VofbIgI-V
,.8
2.5
"-.: I\.
TA-'26°C
2.•
I'" ,,'\.
"
0.5
-5
t
~
d ••
~
~ 0.1
00
.!I"••1.
;:::::: V
I
iT
c~ -.J'F
1.
CL-1SpF
-75 -50 -26
.
r
vcc·.J
100 125
"
FREE·AIR TEMPERATURE
v..!.&J
I-- f--
~
-
T
CL-1IpF
I
75
HIGH·TO·LOW·lEVElOUTPUT
I
-76 -60 -2&
50
AL-4000
CL~''''F
o
25
PROPAGATION DELAY TIME,
"
cJ ..
0
FIGURE A4
FREE·AIR TEMPERATURE
-
G)
CL -tBOpF
~IN .
.0
PROPAGATION DELAY TIME.
LOW·To-HIGH LEVEL OUTPUT
AL· ...
e
~
35 RL-400n
FIGURE A3
.
i
f30
~~. ~-
'0 15 20 2& 30 3&
IOL -Low·L",II-Output eu,rent-mA
..E
cG)
! .. vcc- Sy
)~ ~~
~~
!.
-30
"
FREE·AIR TEMPERATURE
II
i ::
I
--25
-20
AVERAGE PROPAGATION DELAY TIME
TAI.lcl
VI-2AV
'"
-1&
ta
~
FIGURE A2
lOW·LEVEL OUTPUT CURRENT
0.&
-10
.~
'OH-HIgh-L....1Output Cumnt-mA
LOW·lEVEL OUTPUT VOLTAGE
=r
o
l\.
FIGURE A1
... vcc·. V
c
TA--66"C
•
•
2
VI-OAV
~ ~TA''''C
'1".
TA""'C- -1
00
HIGH·LEVEl OUTPUT CURRENT
:5j 1.'
\
• .s
3.5
1
~
t.
~
:r
"L·tt
3.0 TA ·-&~c
"
...
INPUT VOLTAGE
0
26
60
_f-f-- f-'"
........
•
76 100 121
--
t-
eL·160pF
CL-60pF
CL 1.pF
-16 -60 -26 0
25 10 16 100 126
TA-fNl-AlrT............-·C
T A-f.·Air T......mu..-·C
FIGURE A6
FIGURE A5
toata for temparatures below O·C and above 70·C are applicable for Series 54 circuits only.
Data as shown are applicable specifically for the NAND gates with totem-pole outputs.
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS. TEXAS 15265
1-51
TYPICAL CHARACTERISTICS
SERIES 54LS/74LSt
OUTPUT VOLTAGE
OUTPUT VOLTAGE
"
INPUT VOLrAGE
(PNP INPUT)
(DIODE INPUT)
'.0
f-3.5
'r
f
i
'?
~
-
•..
VCC"sV
RL "2kU
3.0
.\ ~TA"2"C
\ l\ I I
2.•
2.0
or
1.'
TA--5SoC
1.0
o
o
0.2 OA 0.6 0.8
1
2.
J
2.0
~
I I
0.5
t
TA
TA =
•
t
II
TA"'26°C
RL -2kn
3.0
-66'C
~
0.4
;-
0.3
1
!
j.
125"~\
TA"2.'C1.•
1.0
~
o
1.2 1.4 1.6 1.1 2
0.2 0.4 0.6 0,8
1
1,2 1A 1.6 1.8
2
~ I:?
.....A = 25'C
:::; ;7\1'"
o
012345678910
2
VI-Input Voitage-V
FIGURE 01·
J,tV
VCC" SV
V'r2V
T~'~~ ~ -::-
O. 1
~
0.'
o
VI-Input VoItagII-V
'"
LOW-LEVEL OUTPUT CURRENT
(STANDARD OUTPUT)
..•
'.0 vee-s v
II
I II
f-
lOW-LEVel OUTPUT VOLTAGE
"
INPU1VOLTAGE
lOt -Low-leval Output Current-rnA
FIGURE 03
FIGURE 02
LOW·lEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
"
LOW·lEVEL OUTPUT CUR RENT
0 .•
:r
I
vcc- sv
or
0.6
0.'
Ii
TA:'25'C~~ f"""
I.. ~~/TA"'25'C
I
TA--OS'C
.
iT
~
...--:;
0
0.2
g V
>
o
3 .•
25
Vee- 5V
20
25
1"0 ~
1.•
•o
1\
12
;:
10
RL = 2 kO
111l~
Ie
o
..1
0.'
FIGURE 06
"
LOAD CAPACITANCE
18
,.
V
! "
f ,.
RL=2kO
tpHL
I
VCC=5V
RL "21dl
TA = 25°C
12
tPLH
'p0---
- .,/
k
./
,/
I----
Y
. / tpLH
i
4
-75 -50 -25
0
25
60
75
100 125
I
f-Frequencv-MHz
20
VCC=5V
CL-15pF
•o
10 20 30 40
50 60 70 80 90 100
CL -load Capac:itanQl-pf
TA-free-Air Temperature-oC
FIGURE 08
FIGURE 07
tO ata for temperatures below
IlU
PROPAGATION DELAY TIMES
o
1-52
CL = 15pF
1'\."-..
"
j
•
10
I
FREE-A!'R TEMPERATURE
f
!
··V
CL"
RL" 2k"
FIGURE 05
b-
/
"
I
PROPAGATION DelAY TIMES
~
~
-10 -20 -30 -40 -50 -60 -70 -80
RGURE 04
"
Duty Cvcle" 50%
IOH-High-Lavel Output Current-mA
IOL-Low-len! Output Cur·rent-mA
,.
1
1-- TA=25"C
~ I'\.
TA=125C\
~ I'\.
1.0
30
".E
~~A=-55'
2 .•
VCC" 6V
TA = 25°C
~
~
2.5
0
15
~, 2.
.:::::: ~
> 0.'
10
FREQUENCY
HIGH·LEVEL OUTPUT CURRENT
:I:
0, 1
o
3.5
POWER DISSIPATION PER GATE
"
..•
(BUFFER OUTPUT)
o·e and above 70·e are applicable for Series 54LS circuits only .
. : TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
.4
I
CL=O
Rl =00
1.
••
TYPICAL CHARACTERISTICS
SERIES 54S/74St
INPUT·CLAMPING-DIODE
.
OUTPUT VOLTAGE
FORWARD VOLTAGE
"
FREE·AIR TEMPERATURE
INPUT VOLTAGE
....
'.0
...
TA~CT
:r 3.0
J 2••
> -1.00
vcl:':.~_v
I
1-0.. -0...
:i -0.80
r -0."
1-0·72
1.5
> 1.0
t-
....... r-.... 'OL · -2B ....
IOL·
-,.mAo ~~
I --r--..::
r-....
l::
..•
r-tL.~'O+I
> -8.10
I"'{...
-76 -60 -25 0
'IIi &0 1& 'OD 1.
TA-F,...AlrT............·C
00 0.2 OA 0.6 0.8 1.01.2 1A 1.8 1 .. 2.0
VI-Input VaiUtgI-V
FIGURE E1
FIGURE E2
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT YOLTAGE
HIGH· LEVEL OUTPUT CURRENT
LOW· LEVEl OUTPUT CURRENT
h
/ " TA •
-----.. ~
I~ ~
I~
TA· ......C
•
'.0
...
,2B',}
t
0.7
I
1
TA~-IfCl
0.8
"- \.
-10 -20 -3D -40 -10
..
-~
VCC-IV
'.8
~
.~
10.•
TA' Zl"c
~
c
o
.
..
o
o
-
-G.I2
TA· ......C
i2.0
~
o
vcc·.~
i0: -0."
RL-2800
-eo
]OA
TA' Zl"c,
0.3
~I '
!
!.0.3
i
-70
-ao
0.1
I
I-"'"
..... I "
..!::: ~
I;:?
00
"'-TA' ,2B'C
,0
&
,1
20
25
30
31
4D
a............FIGURE E4
IOH-Hith-...... OUtput CurNnt-fftA
IOL -Low-LneI OutpMt
FIGURE E3
..
.
INPUT CURRENT
HIGH-LEVEL INPUT CURRENT
INPUT VOLTAGE
FREE·AIR TEMPERATURE
'0 vcc- s
7
vcc- sv
V,-2.7V
TA ....C.~~-1~+--r~--+-~
ii
-2~~~~+-~~~+--+--1
i~~~H-+-~~f-+--+--1
1-'0 f-+t-+--+--+--j-t--+---l
0.;
OA
i 0.3
~ 0.'
b -'2 ~-+I'-t-+-~~f-+--+--1
-•• ~-H'-t-+-~~f-+--+--1
-II ~-If'-t-+-~~f-+--+--1
jom
'V 0...
iii
- om
-"-2':-...J_,:'-~-'--~-7--!:--=--:!
0.0'
V
-7& -10 -21
0
21
50
71
1OO,ZI
TA-,. .-Air T""",...,.-·C
FIGURE E8
FIGURE E5
tOata for tamperaturas below O·C and above 70·C are applicable for Sarle8 545 circuits only.
Data as shown are applicable specificallv for the NAND gates with totem-pole outputs.
TEXAS ~
INSlRUMENlS
POST OFfICE lOX 8850'2 • DALLAS. TEXAS 75285
1-53
TYPICAL CHARACTERISTICS
SERIES 54S/74S t
,.
PROPAGATION DELAY TIME,
PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
lOW-TO-HIGH-lEVEL OUTPUT
,.
"
fREE·AIR TEMPERATURE
L
-
1
VCC-;;SV
RL·2800
"
SUPPLY VOLTAGE
-
1
V f-"
CL -150 pf
1
' - - - - CL
CD
-r-r--J
'-r-
3
OJ
-....
o _'--
5'
o
3
Ca."" 16pF
1
1
1
___.. _II
-15 -60 -26
0
-I---
CL·JPF
~
CL -16pF
::::s
CD
150pf
1
C~.5•• F_ P ~
Ci)
RL -2800
TA"2!i"C
1
I
25
60
76 100
o
4.5
125
1
5.0
4.75
5.25
FIGURE E7
FIGURE E8
CIt
PROPAGATION DELAY TIME,
PROPAGATION DELAY TIME,
HIGH·TO-lOW·LEVElOUTPUT
HIGH·TO-lOW·LEVEL OUTPUT
(5'
FREE·AIR TEMPERATURE
'"
'0 ._....,-
::::s
5.5
VCC-Supply Voitage-V
TA-fr..·Air Temperature-°C
-::-""'o-C~
.,J.F
-...;;: J.
'"
,.
VCC- SV
-RL-280n
SUPPLY VOLTAGE
I
RL"280n
TA· ZSOC
CL = 150 pf
1
1
---
CL '"'so pF
CL-SOpF
I
CL-16pF
r-I-
CL-15pF
3
1
1
1
1
•
-75 -60 -26
0
26
60
76
•
100 126
4.5
4.75
TA-F ....-AIR TEMPERATURE-DC
FIGURE E10
..
POWER DISSIPATION PER GATE
AVERAGE PROPAGATION DELAY TIME
J1
r-.....
I
J
"L"·BOIl
6
I-
JI •
~76
-&0 -25
0
26
Ii
BO
TA-25°C
Duty Cycl. '" 50%
5.
30
I
!
20
1
E
10
1
50
vcc· sv
CL""15pf
I.
CL-16pF
+ ...
7.
I
CL'.!,.F
I--
~
"l
1
f
%
BO
VCC'"'6V
CL·'50~F=","",
.~
•
"
FReQUENCY
FREE·AIR TEMPERATURE
10
-~
I
0
75
100
125
,
7 ,.
20
f-Frequency-MHz
FIGURE E12
FIGURE E11
fO ata for temperatures below OOC and above 70°C are applicable for Series 545 circuits only.
Data as shown a'e applicable specifically fa, the NAND gates with totem·pole outputs.
1-54
5.5
5.25
VCC-Supply VoI1agl-V
FIGURE E9
J
1
5.0
TEXAS ,.,
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TeXAS 75265
40
70100
TYPICAL CHARACTERISTICS FOR FLlp·FLOPS
SERIES 54S/74St
HIGH-LEVEL OUTPUT VOLTAGE
lOW-LEVE l OUTPUT VOLTAGE
"
LOW-lEVEL OUTPUT CURRENT
HIGH·LEVEL OUTPUT CURRENT
~ ~ f-::Tl"~5'C
T
k
~~
~
TA=-5SoC-
1
o
I
f
~
o
~
f-
o
'r
TA=25 Q C
'"
I
-
c:
o
'';:;
<
ca
-'
~
0,1
!\.
°0L-~5-'~0-'~5~2~0~~~~~~~~~~@
-10 -20 -30 -40 -50 -60 -70 -80
'OL-Low-level Output Cu,rent-mA
'OH-High-Leval Output Current -mA
FIGURE E13
FIGURE E14
'5112, 'S113
INPUT CURRENT
HIGH-LEVEL INPUT CURRENT
ca...
FREE-AIR TEMPERATURE
c:
INPUT VOLTAGE
10
K
-2
1
i
.3
i
I
I
f
I
VI -J/KINPUTS
LII' PRESET/CLEAR INPUTS
III"--- CLOCK INPUT
-4
-6
....
-10
],.-12
0.7
]-
0.4
]
0.2
Vee = 5 V
TA= 2SoC
-1.
-1.
/
/
0, 1
0.07
- r--- -
0.02
V
0,0 1
-2
-1
-75 -SO -25
FIGURE E15
FREE-AlA TEMPERATURE
T
rV-C~C-=-5'V-"'-~-"'-~-"--~
.,
16
~
14 RL=280il--,t--+---I_+---I_-j
~
;:
!
~ 12t--+---I-+---I-+-+-f--1
a.
~~
10 I-----'9-0I;;:;=-+- u u>
3
13'
••.a
1111
'S:
Q)
o
...I
l-
I-
2
1 2019
18
NC
2Y
NC
2A
IZ'
la
2'
2a
3.
3a
en
Q)
(.)
~~Z>q-
logic symbol t
I.
II
'"
"'
I.'
9 10 1112 13
III
alQuctal
NZZMM
(!l
1121
NC - No internal connection
tThis symbol is in accordance with ANSI/lEEE Std. 91·1984 and
IEC Publication 617·12.
Pin numbers shown are for D, J, N, and W packages.
PRODUCTION DATA d•• umo.1S .antain inl.rmatian
.urrant .s of publlc.tian dlto. Products ••nform , •
• p..ifi.ati1l1l. per thl terma .f T.... Inllrumlnt.
~~=~~i~·{::1~7i ~::\:~'i:r lir;~:::~r":" no'
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-9
SN5401. SN54LS01.
SN7401. SN74LS01
QUADRUPLE 2·INPUT POSITIVE·NAND GATES WITH OPEN·COLLECTOR OUTPUTS
logic diagram (positive logic)
1A=D1B
1Y
ZA~2Y'
2B~
3A==D--'
4A==D--
3Y
3B
4Y
4B
positive logic: Y - A·B or Y -
A+
jj
schematics (each gate)
•
'LS01
'01
vee
r----4~-------vee
17kn
4 kll
-t
A
....-t
C
CD
<
r)'
8 kn
INPUTS
1.6 kll
B
INPUTS
A
OUTPUT
B
OUTPUT
y
CD
y
en
L-~--------~~~~-GND
~~~----~'--------4~--~~-GND
Resistor values shown are nominal.
absolute-maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1): '01, 'LS01 ..................................... 7 V
Input voltage: '01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
'LS01 ......................................................... 7 V
Off-state output voltage ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Operating free-air temperature range: SN54' ....... '.' ................... -55°e to 125°e
SN74' ................................. ooe to 70 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 1: Voltage values are" with respect to network ground'terminals.
2-10
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5401, SN7401
QUADRUPLE 2·INPUT POSITIVE·NAND GATES WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN5401
SN7401
UNIT
Vee
Supply voltage
VIH
High~level
Vil
Low-level input voltage
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
input voltage
V
V
2
V
0.8
0.8
VOH High-level output voltage
5.5
5.5
V
IOl
Low-level output current
16
16
mA
TA
Operating free-air temperature
70
"e
- 55
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VIK
IOH
SN5401
TEST CONDITIONS t
PARAMETER
MIN
TYP*
SN7401
MAX
MIN
MAX
TYP*
- 1.5
Vee = MIN,
II = -12 rnA
Vee = MIN,
Vil = 0.8 V,
VOH = 5.5 V
Vee = MIN,
Vil = 0.7 V,
VOH = 5.5 V
VOL
Vee = MIN,
VIH = 2 V,
IOl = 16 rnA
II
Vee = MAX,
VI = 5.5 V
-1.5
0.25
0.25
0.2
0.4
0.2
0.4
1
1
UNIT
V
mA
V
rnA
IIH
Vee = MAX,
VI = 2.4 V
40
40
~A
III
Vee = MAX,
VI = 0.4 V
-1.6
-1.6
rnA
leeH
Vee = MAX,
VI = 0
leel
Vee = MAX,
VI = 4.5 V
4
8
4
8
rnA
12
22
12
22
rnA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*AII typical values are at Vee = 5 V, TA = 25 De.
switching characteristics, Vee
= 5 V, T A = 25°e
FROM
TO
(lNPUTI
(OUTPUT)
A or B
Y
PARAMETER
TEST CONDITIONS
tpLH
tpHL
(see note 2)
MIN
TYP
MAX
UNIT
Rl"4k!!,
CL - 15 pF
35
55
ns
RL"400!!,
eL"15pF
8
15
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-11
SN54LS01, SN74LS01
QUADRUPLE 2·INPUT POSITIVE·NAND GATES WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN54LS01
SN74LS01
UNIT
..
vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.7
0.8
VOH High-Jevel output voltage
5.5
5.5
IOL
Low-level output current
4
8
mA
TA
Operating
70
°c
free~air
temperature
-55
125
0
V
V
electrical characteristics over recommended operating free-air temperature range {unless otherwise noted)
SN54LS01
TEST CONDITIONS t
PARAMETER
MIN.
TYP*
MAX
MIN
TYP*
Vee
'1=-18mA
IOH
Vee = MIN.
V'L = MAX.
VOH = 5.5 V
Vee = MIN.
VIH = 2 V.
IOL = 4 mA
Vee = MIN.
V'H = 2 V.
IOL = 8 mA
MAX
-1.5
-1.5
VIK
=
SN74LSOI
UNIT
MIN
0.1
0.1
V
mA
-I
-I
r-
VOL
CD
0
I,
Vee = MAX.
VI = 7 V
0.1
0.1
<
c:r
CD
'IH
Vc;e = MAX.
VI = 2.7 V
20
20
I'A
'IL
Vee = MAX.
VI - 0.4 V
-0.4
- 0.4
mA
leeH
Vee - MAX.
VI = 0
0.8
1.6
0.8
1.6
mA
leeL
Vee= MAX.
VI = 4.5 V
2.4
4.4
2.4
4.4
mA
en
t
0.25
0.4
0.25
0.4
0.35
0.5
V
mA
For condition~ shown as MIN or MAX. use the appropriate value ,pacified under recommended operating conditions.
t All typical values are at Vee"" 5 V, T A"" 25°C.
switching characteristics, Vee
= 5 V, T A = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
Ao, B
y
PARAMETER
tPLH
TEST CONDITIONS
TYP
MAX
17
32
ns
15
28
ns
UNIT
eL = 15 pF
RL=2kn.
tPHL
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2-12
MIN
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5402, SN54LS02, SN54S0~
SN7402, SN74LS02, SN74S02
QUADRUPLE 2·INPUT POSITIVE·NOR GATES
DECEMBER 1983-REVISED MARCH 1988
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN5402 •.. J PACKAGE
SN54LS02. SN54S02 ... J OR W PACKAGE
SN7402 ... N PACKAGE
SN74LS02. SN74S02 .•. 0 OR N PACKAGE
(TOP VIEW)
1Y
1A
1B
2Y
2A
2B
description
These devices contain four independent 2-inputNOR gates.
The SN5402, SN54LS02, and SN54S02 are
characterized for operation over the full military
temperature range of - 55 ac to 125 ac. The
SN7402, SN74LS02, and SN74S02 are
characterized for operation from 0 ac to 70 ac.
INPUTS
GND
SN5402 ... W PACKAGE
(TOP VIEW)
1A
1B
1Y
leach gate)
FUNCTION TABLE
OUTPUT
A
8
V
H
X
L
X
H
L
L
L
H
VCC
4Y
4B
4A
3Y
3B
3A
4Y
4B
4A
VCC
GND
2Y
2A
2B ""L_ _
~
In
3B
3A
3Y
CI)
(.)
'S;
CI)
o
logic symbol t
1A
18
2A
28
3A
38
4A
48
SN54LS02. SN54S02 ... FK PACKAGE
(2)
;;'1
(TOP VIEW)
(3)
....J
lI-
U
~~~~~
(5)
(6)
3
2
1
4B
(8)
1B
4
(9)
NC
5
NC
2Y
6
4A
(11)
NC
7
NC
(12)
2A
8
3Y
tThis symbol is in accordance with ANSI/IEEE Std.
lEe Publication 617·12.
Pin numbers shown are for D, J, and N packages.
91·1984 and
NC - No internal connection
logic diagram (positive logic)
1A
18
L>-IY
2A
28
[>-2Y
3A
38
L>-3Y
4A
48
L>-4Y
Y~A·8orY~A+B
PRODUCTION DATA d......IIt....llin informltion
......1 '" .f ,..IIOIlion dlt•. Prad.eII •••form 10
_Ifieetl...... t.e 1.1111 of T.... loltrum.oll
:="~~·i~:r.7i ~1:~I:r !i:O:::::'::." 001
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-13
SN5402, SN54LS02, SN54S02,
SN7402, SN74LS02; SN74S02
QUADRUPLE 2·INPUT POSITIVE·NOR GATES
schematics leach gatel
'02
INPUTS
A _ _- J
L-.---------~--------~~GND
'LS02
20 kll
r-
C
'S02
r---------~------------~--~-vcc
-I
-I
120H
r--1~----~----------~-vcc
v
2.8 kn
0.9kn
50n
INPUTS
CD
A
<
c;'
A
10kH
CD
OUTPUT
y
(I)
OUTPUT
~~~~----~-----y
B
B
~~------~--------~----~t--GND
~~----------'-----------~--~-----GND
Resistor values shown are nominal.
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: '02, 'S02 ..................... " . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
'LS02 ........................................................ 7 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Operating free-air temperature range: SN54' ........................... , -55°e to 125°e
SN74' ................................ aoe to 70 0 e
Storage temperature range ......................................... - 65 °e to 150 °e
NOTE 1. Voltage values are with respect to network ground terminal.
2-14
TEXAS •
INSTRUMENlS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
SN5402. SN7402
QUADRUPLE 2·INPUT POSITIVE·NOR GATES
I ..
recommended operating conditions
SN5402
SN7402
UNIT
Vee
Supply voltage
VIH
High·level input voltage
VIL
Low~level
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
V
2
input voltage
0.8
0.8
IOH
High-level output current
- 0.4
IOL
Low-level output current
16
TA
Operating free-air temperature
125
- 55
V
0
V
-0.4
rnA
16
rnA
70'
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN5402
TEST CONDITIONS t
PARAMETER
SN7402
UNIT
MIN
TYP*
2.4
3.4
MAX
MIN
TYP*
2.4
3.4
MAX
- 1.5
-1.5
V
VIK
Vee = MIN,
II =-12rnA
VOH
Vee = MIN,
VIL = O.B V,
IOH=-0.4rnA
VOL
Vee = MIN,
VIH=2V,
IOL=16rnA
II
Vee= MAX,
VI = 5.5 V
IIH
Vee= MAX,
VI = 2.4 V
40
40
IlA
IlL
Vee= MAX,
VI = 0.4 V
-1.6
- 1.6
rnA
C
IOS§
Vee = MAX
leeH
Vee = MAX,
VI = 0 V
leeL
Vee = MAX,
See Note 2
0.2
0.2
0.4
V
0.4
V
(I)
rnA
CJ
Q)
1
1
Q)
- 55
rnA
...I.
8
16
8
16
rnA
lI-
14
27
14
27
rnA
- 20
t For conditions shown as MIN or MAX. use the appropriate
f All typical values are at Vee := 5 V. T A = 2SoC.
'S;
- 55
-18
value specified under recommended operating conditions.
§ Not more than one output should be shorted at a time.
NOTE 2: One input at 4.5 V. all others at GNO.
switching characteristics.
Vee = 5 V. TA = 25° e (see note 3)
FROM
TO
(INPUT)
(OUTPUT)
Aor B
Y
PARAMETER
TEST CONDITIONS
tPLH
eL = 15 pF
RL =400 n,
tpHL
MIN
TYP
MAX
UNIT
12
22
ns
8
15
n5
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
l!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-15
SN54LS02, Sll74LS02 .
QUADRUPLE 2-INPUT POSITIVE·NOR GATES
recommendtd opl1lrating conditions
SN64LS02
SN74LS02
UNIT
VCC SupplV voltage
VIH
High·lavel input voltage
VIL
Low-level input. voltage
10H
High.. lavel output current
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
10L
Lo~level
TA
Operating free-air temperature
V
V
2
0.7
0.8
-0.4
-0.4
mA
8
mA
70
°c
output current
4
125
- 55
0
V
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN64LS02
t
VIK
VOH
~
r-
VCC· MIN,
~MAX,
MIN TVPt
-1.5
11'-18mA
VIL
MAX
2.5
10H = -0.4 mA
3.4
MAX
- 1.5
2.7
3.4
V
V
VCC· MIN,
VIH
= 2V,
10L =4mA
VCC· MIN,
VIH=2V,
10L"SmA
11
VCC" MAX,
VI = 7 V
0.1
0.1
VI=2.7V
20
20
p.A
VI"0,4V
-0.4
-0.4
mA
VOL
C
VCC· MIN,
SN74LS02
UNIT
MIN TYPt
0.25
0.4
0.25
0.4
0.35
0.5
V
mA
<
(i'
IIH
VCC= MAX,
IlL
VCC" MAX,
CD
losf
VCC=M.AX
-100
mA
ICCH
VCC· MAX,.
VI"OV
1.6
3.2
1.6
3.2
mA
ICC I..
VCC= MAX,
See Note 2
2.8
5.4
2.8
5.4
mA
CD
(II
t For conditions ,hown .a MIN
-20
-100
-20
or MAX, UH the appropriate valva specified under recommended operating condition,.
*All typical valu•• ar. at Vee" 5 V, T A
:III
2S0C
"Not mora than one output should be shorted at 8 time, and the du.ration of the .hort~clrcult should not e.accead on8 second.
NOTE 2; One Input .t 4.5 V, III other, at GND.
switching charac~ristics. Vee = 5 V. TA =25°e (see note 3)
FROM
TO
(lNPUTI
(OUTPUTI
Aor 8
Y
PARAMETER
tPLH
TEST CONDITIONS
RI..·2kn,
CL
~
tPHL
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-16
"
TEXAS'"
INSTRUMENTS
POST OFFICE BO)( 655012 • CALLAS. TEXAS 75266
MIN
15pF
TVP
MAX
10
15
ns
10
15
n.
UNIT
SN54S02, SN14S02
QUADRUPLE 2·INPUT POSITIVE·NOR GATES
recommended operating conditions
SN54S02
SN74S02
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
VCC
Supply vollage
VIH
High~level
VIL
Low-level input voltage
0.8
0.8
V
10H
High-level output current
-1
-1
rnA
20
rnA
70
°c
input voltage
2
10L
Low-level output current
TA
Operating free-air temperature
20
-55
125
V
V
2
0
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
t
TEST CONDITIONS
SN74S02
SN54S02
t
UNIT
MIN
TYP*
2.5
3.4
MAX
MIN
TYP*
2.7
3.4
-1.2
-1.2
VIK
Vcc =MIN.
II = -18 rnA
VOH
Vcc =MIN.
VIL = 0.8 V,
10H = -1 rnA
VOL
Vcc = MIN,
VIH = 2 V,
IOL=20rnA
II
VCC = MAX,
VI=5.5V
MAX
V
V
0.5
0.5
1
1
V
rnA
IIH
VCC =MAX,
VI = 2.7 V
50
50
/LA
IlL
VCC = MAX,
VI = 0.5 V
-2
-2
rnA
-100
rnA
-40
-100
-40
10s§
VCC=MAX
ICCH
VCC= MAX,
VI =0 V
17
29
17
29
rnA
ICCL
VCC = MAX,
See NOle 2
26
45
26
45
rnA
For conditions shown 8S MIN or MAX, use the appropriate value specified under recommended operating condition ••
l All typical values are at Vee c 5 V. T A"" 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not e)(ceed one second.
NOTE 2: One input at 4.5 V, all others at GND.
switching characteristics, Vee
=5 V, TA = 25°e (see note 3)
FROM
TO
(INPUT)
(OUTPUT)
TEST CONDITIONS
PARAMETER
IpLH
RL=280n.
UNIT
TVP
MAX
3.5
5.5
ns
3.5
5.5
ns
CL = 15 pF
tPHL
Aor B
MIN
V
IpLH
RL=280n.
5
ns
5
ns
CL = 50 pF
IPHL
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 655012
It
DALLAS. TEXAS 75265
2-17
2-18
SN5403, SN54LS03, SN54S03,
SN7403, SN74LS03, SN74S03
QUADRUPLE 2·INPUT POSITIVE·NAND GATES WITH OPEN·COLLECTOR OUTPUTS
DECEMBER 1983-REVISED MARCH 1988
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Caniers
and Flat Packages. and Plastic and Ceramic
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN&403 ..• J OR W PACKAGE
SN54LS03. SN64S03 ..• J OR W PACKAGE
SN7403 ••. N PACKAGE
SN74LS03. SN74S03 ... 0 OR N PACKAGE
(TOPVIEWI
lA
18
1Y
2A
28
2Y
description
These devices contain four independent 2·inputNAND gates. The open-collector outputs require
pull-up resistors to perform correctly. They may
be connected to other open-collector outputs to
implement active-low wired-OR or active-high
wired-AND functions. Open-collector devices are
often used to generate higher VOH levels.
GND
SN54LS03. SN54S03 ... FK PACKAGE
(TOPVIEWI
The SN5403. SN54LS03 and SN54S03 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN7403. SN74LS03 and SN74S03 are
characterized for operation from ooe to 70°C.
FUNCTION TABLE
INPUTS
3212019
OUTPUT
B
Y
H
H
L
X
X
L
L
H
4A
NC
4Y
NC
38
1Y
NC
2A
NC
28
leach gatel
A
VCC
48
4A
4Y
38
3A
3Y
U)
Q)
(J
";
Q)
o
...I
lI-
H
NC
logic symbol t
~
No internal connection
logic diagram (positive logic)
1A---18
Jp----1Y
1A
1B
2A~ __ 2Y
28~
2A
2B
3B
4A
4B
t This symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEe Publication 617·12.
Pin numbers shown are for D. J. N. and W packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Y=A.BorY=A+B
2-19
SN5403, SN54LS03, SN54S03,
SN7403, SN74LS03, SN74S03
QUADRUPLE 2·INPUT POSITIVE·NAND GATES WITH OPEN·COLLECTOR OUTPUTS
schematics (each gate)
'03
r - - - -.....- - -
Vee
1.6kn
INPUTS
A
OUTPUT
B
y
L-~----~~'-~GNO
'S03
'LS03
Vee
-t
....-t
17 kn
INPUTS
r---~~-------vee
8 kH
A
INPUTS
C
OUTPUT
B
(I)
A
:S.
n
(I)
y
B
(I)
OUTPUT
y
5 kn
GND
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: '03, 'S03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
'LS03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Operating free-air temperature range: SN54' . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
SN74' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ooe to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
NOTE 1; Voltage values are with respect to network ground terminal.
,
2-20
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TeXAS 75265
SN5403, SN7403
QUADRUPLE 2·INPUT POSITIVE·NAND GATES WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN5403
SN7403
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.S
5
5.5
4.75
5
5.25
V
0.8
0.8
V
VOH High-level output voltage
5.5
5.5
V
10L
Low-level output current
16
16
mA
TA
Operating free-air temperature
70
°c
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
2
V
2
- 55
125
0
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER
VIK
10H
SN5403
TEST CONDITIONSt
Vee
=
MIN,
Vee - MIN,
vee
VOL
II
Vee
= MIN,
= MIN,
Vee - MAX,
IIH
Vee
III
Vee
leeH
Vee
leel
Vee
= MAX,
= MAX,
= MAX,
= MAX,
=
II
= 0.7
V,
VIH = 2 V,
VI - 5.5 V
VI
VI
VI
VI
TYP*
= 2.4
= 0.4
=0
= 4.5
MAX
MIN
SN7403
TypJ
MAX
-1.5
-12 mA
Vil - 0.8 V,
Vil
MIN
-1.5
0.25
VOH - 5.5 V
VOH
IOL
= 5.5 V
= 16 rnA
0.25
0.2
0.4
0.4
0.2
1
1
UNIT
V
mA
V
rnA
V
40
40
~A
V
-1.6
-1.6
rnA
V
4
8
4
8
rnA
12
22
12
22
rnA
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
*AII typical values are at Vee = 5 V, TA = 25°e.
switching characteristics, Vee'" 5 V. TA'" 2Soe (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
PARAMETER
tPLH
tpHL
TEST CONDITIONS
Aor B
y
MIN
TYP
MAX
UNIT
RL=4kl!,
Cl = 15pF
35
45
ns
RL = 400 l!,
CL = 15 pF
8
15
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-21
SN54LS03, SN74LS03
QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN54LS03
Vee
Supply voltage
VIH
Highwlevel input voltage
VIL
Low-level input voltage
SN74LS03
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
0.7
0.8
VOH High-level output voltage
5.5
5.5
IOL
Low-level output current
4
8
TA
Operating free-air temperature
-55
125
V
V
2
0
70
V
V
mA
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS03
PARAMETER
SN74LS03
UNIT
TEST eONDITIONst
MIN
TVP*
MAX
MIN
MAX
-1.5
-1.5
0.1
0.1
V
VIK
Vee = MIN,
11=-18mA
IOH
Vee = MIN,
VIL = MAX,
Vee= MIN,
VIH
= 2 V,
IOL = 4 mA
Vee = MIN,
VIH = 2 V,
IOL = BmA
II
Vee· MAX,
VI = 7 V
0.1
0.1
IIH
Vee= MAX,
VI = 2.7 V
20
20
itA
IlL
Vee= MAX,
VI=OAV
-0.4
- 0.4
mA
leeH
Vee· MAX,
VI
=0
O.B
1.6
O.B
1.6
mA
leeL
Vee = MAX,
VI =4.5V
2.4
4.4
2.4
4.4
mA
VOH=5.5V
0.25
0.4
0.25
0.4
0.35
0.5
mA
V
VOL
t
TVP*
mA
For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:t All typical values are at Vee
=5
V, T A'" 2SoC.
switching characteristics, Vee'" 5 V, TA'" 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
Aor B
v
TEST CONDITIONS
PARAMETER
tPLH
RL=2kn,
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
,
TVP
MAX
17
32
os
15
28
os
eL = 15 pF
tpHL
2-22
MIN
"'i~
TEXAS V
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
UNIT
SN54S03, SN74S03
QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN54S03
SN74S03
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
VOH High-level output voltage
5.5
5.5
V
IOl
Low-level output current
20
20
rnA
TA
Operating free-air temperature
70
°c
VCC
Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
2
V
2
- 55
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VIK
IOH
VOL
TEST CONDITIONSt
Vec
Vec
Vec
Vec
II
VCC
IIH
Vec
III
Vec
ICCH
VCC
ICCl
Vec
= MIN.
= MIN.
= MIN,
= MIN,
= MAX,
= MAX,
= MAX,
= MAX,
= MAX,
II
=
MIN
SN54S03
Typf
MAX
SN74S03
Typf
MAX
-1.2
-18 rnA
= 0.8 V,
Vil = 0.7 V,
VIH = 2 V,
VI = 5.5 V
VI = 2.7 V
VI = 0.5 V
VI = 0
VI = 4.5 V
Vil
MIN
= 5.5 V
VOH = 5.5 V
IOl = 20 rnA
-1.2
0.25
VOH
0.25
0.5
0.5
UNIT
V
rnA
t/)
V
Q)
(,)
"S
1
1
rnA
50
50
~A
-2
-2
rnA
6
13.2
6
13.2
rnA
20
36
20
36
rnA
TYP
MAX
UNIT
2
5
7.5
ns
2
4.5
7
ns
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:J:AII typical values are at VCC = 5 V, TA = 25°e.
Q)
C
...:.I
lI-
switching characteristics, VCC = 5 V, T A = 25"C (see note 2)
PARAMETER
FROM
(lNPUTI
TO
(OUTPUT)
TEST CONDITIONS
tplH
RL
~
280 n,
CL = 15 pF
tpHl
Acr B
MIN
Y
tPLH
Rl = L80n,
7.5
ns
7
ns
Cl o50pF
tpHl
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-23
-t
-t
rC
CI)
<
n'
CI)
C/J
2-24
SN5404, SN54LS04, SN54S04.
SN740' SN74LSO' SN74S04
HEX INVERTERS
DECEMBER 19B3-REVISED MARCH 1988
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN5404 ... J PACKAGE
SN54LS04, SN54S04 ... J OR W PACKAGE
SN7404 ... N PACKAGE
SN74LS04. SN74S04 ... 0 OR N PACKAGE
(TOP VIEW)
Vee
lA
lY
2A
2Y
3A
3Y
GND
description
These devices contain six independent inverters.
The SN5404, SN54LS04, and SN54S04 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN7404, SN74LS04, and SN74S04 are
characterized for operation from O°C to 70°C.
6A
6Y
5A
5Y
4A
4Y
SN5404 ... W PACKAGE
(TOP VIEW)
lY
6A
6Y
GND
5Y
5A
4Y
lA
2Y
2A
FUNCTION TABLE (each inverter)
INPUTS
OUTPUT
A
V
Vee
H
L
L
H
3A
3Y
4A
(/)
Q)
.~
>
Q)
C
logic symbol t
SN54LS04, SN54S04 ... FK PACKAGE
lA
2A
3A
4A
SA
6A
(1)
(TOP VIEWI
IV
(31
..J
lI-
2V
(5)
(91
1111
(131
tThis symbol is in accordance with ANSI/IEEE Std. 91·1984 and
lEG Publication 617-12.
Pin numbers shown are for D. J, and N packages.
6Y
2A
4
NC
5
NC
2Y
6
5A
NC
7
Ne
3A
8
5Y
logic diagram (positive logic)
NC - No internal connection
lA--{>o-lY
2A--{>o-2Y
3A--{>o-3Y
4A~4Y
5A~5Y
6A--{>o-6Y
V
~
A
PRODUCTION DATA documents contain information
current I. of publication data. Praducta conform to
!pllcificltiDDS per the terms of raxas Instruments
:==~~i~·i~:1~7i ~!:~::i:; :I~":::::::t:~~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-25
SN5404, SN54LS04, SN54S04,
SN1404,SN14LS04, SN14S04
HEX INVERTERS
schematics (each gate)
'04
.------1~_1~VCC
130
n
INPUT
A
OUTPUT
y
~--.---~~--~GND
. LS04
'S04
r----.----------~-vcc
20 kU
8 kll
120 n
-I
-I
rC
INPUT
A_--foIHH
CD
<
5"
12 kn
CD
(II
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: '04, 'S04 .................................................... 5.5 V
'LS04 ......................................................... 7 V
Operating free-air temperature range: SN54' . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°e
SN74' ................................ ooe to 70 0 e
Storage temperature range ......................................... - 65 °e to 150 °e
NOTE 1: Voltage values are with respect to network ground terminal.
2-26
TEXAS
..If
INSTRUMENTS
POST OFFICE
eox 855012
• DALLAS. TEXAS 78285
8115404, SI7404
HEX INVERTERS
recommended operating conditions
SN7404
SN5404
UNIT
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
0.8
0.8
- 0.4
-0.4
16
IOL
Low-level output current
TA
Operating free-air temperature
- 55
125
V
V
2
0
V
mA
16
mA
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherw.ise noted)
SN5404
TEST CONDITIONS t
PARAMETER
SN7404
UNIT
MIN TYP*
MAX
MIN
TYP*
2.4
3.4
VIK
Vee" MIN,
11"-12mA
VOH
Vee
VIL"0.8V,
IOH" -0.4 mA
VOL
Vee" MIN,
VIH"2V,
IOL" 16 mA
II
Vee" MAX,
VI" 5.5 V
IIH
Vee" MAX,
VI"2.4V
40
40
itA
III
Vee" MAX,
VI" 0.4 V
- 1.6
-1.6
mA
0
MIN,
-1.5
MAX
2.4
3.4
0.2
Vee" MAX
leeH
Vee= MAX,
VI = 0 V
leel
Vee = MAX,
VI = 4.5 V
0.2
1
V
0.4
V
V
1
mA
- 55
mA
6
12
6
12
rnA
18
33
18
33
rnA
TYP
MAX
12
22
ns
8
15
ns
-20
IOS§
0.4
- t.5
- 55
-18
en
CD
(.)
"S;
CD
o
...
lI-
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee .-. 5 V, T A - 25°C.
§ Not more than one output should be shorted at a time.
switching characteristics, Vee = 5 V, T A = 25°e (see note 2)
PARAMETER
tplH
FROM
(INPUT)
TO
(OUTPUT)
A
y
TEST CONDITIONS
RL = 400
n,
MIN
UNIT
el = 15 pF
tpHl
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-27
SN54LS04. SN74LS04
HEX INVERTERS
recommended operating conditions.
SN74LS04
SN54LS04
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low~level
input voltage
IOH
High~level
output current
-0.4
-0.4
IOL
Lo,w-ievel output current
4
8
mA
TA
Operating free-air temperature
70
°e
2
V
2
-55
125
0
mA
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
lIB
-I
-I
SN74LS04
SN54LS04
t
MIN TVP*
MAX
MIN
TVP*
2.7
3.4
Vee·' MIN.
II =-18mA
Vee ·'MIN.
VIL = MAX.
IOH =-O.4mA
Vee· MIN.
VIH = 2V.
IOl =4mA
Vee =MIN.
VIH=2V.
IOL = 8 mA
2.5
3.4
0.25
MAX
-1.5
-1.5
VIK
VOH
VOL
r-
TEST CONDITIONS
UNIT
V
V
0.4
0.4
V
0.25
0.5
II
Vee= MAX,
VI =7V
0.1
0.1
0
CD
IIH
Vee =MAX,
VI =2.7V
20
20
p.A
<
c:r
CD
III
Vee = MAX,
VI =O.4V
-0.4
-0.4
rnA
10S§
Vee = MAX
leeH
Vee
leel
Vee= MAX.
(I)
= MAX,
-100
-100
rnA
VI~OV
1.2
2.4
1.2
2.4
rnA
VI = 4.5 V
3.6
6.6
3.6
6.6
rnA
-20
-20
mA
t For conditions shown as MIN or MAX, USB the appropriate value specified under recommended operating conditions.
t
All typical valuBs are at
Vee;; 5 V, T A;; 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, Vee
PARAMETER
tPLH
=5 V, TA = 25°e (see note 2)
FROM
(INPUT}
TO
(OUTPUT I
A
y
TEST CONDITIONS
Al = 2
kn.
NOTE 2: load circuits and voltage waveforms are shown in Section 1 .
-If
. TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
TVP
MAX
9
15
ns
10
15
ns
el=15pF
tPHl
2-28
MIN
SN54S04, SN74S04
HEX INVERTERS
recommended operating conditions
SN54S04
SN74S04
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
VCC
Supply voltage
VIH
High~level
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
-1
-1
rnA
20
20
rnA
70
°c
input voltage
2
IOL
Low-level output current
TA
Operating free-air temperature
-55
125
V
V
2
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VCC = MIN,
11=-18rnA
VOH
VCC = MIN,
VIL = 0.8 V,
SN74S04
SN54S04
t
MIN TYP
*
MAX
MIN
TYP
*
-1.2
2.5
IOH =-1 rnA
IOL=20rnA
-1.2
2.7
3.4
UNIT
MAX
V
V
3.4
0.5
0.5
V
VOL
VCC = MIN,
VIH=2V,
II
VCC = MAX,
VI = 5.5 V
1
1
rnA
IIH
VCC = MAX,
VI = 2.7 V
50
50
I'A
IlL
VCC = MAX,
VI =0.5V
C/)
2
rnA
-100
rnA
-2
-40
-100 -40
IOS§
VCC = MAX
ICCH
VCC= MAX,
VI =OV
15
24
15
24
rnA
ICCL
VCC= MAX,
VI = 4.5 V
30
54
30
54
rnA
TYP
MAX
UNIT
3
4.5
3
5
Q)
o
'S;
Q)
C
...I
~
I-
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
l All typical values are at Vee =' 5 V. T A = 2SoC.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
switching characteristics, Vee
PARAMETER
FROM
UNPun
=5 V, TA =25°e (see note 2)
TO
(OUTPUT)
TEST CONDITIONS
tpLH
RL = 280
tPHL
tPLH
A
n,
MIN
ns
CL = 15 pF
ns
Y
RL = 280
n,
4.5
ns
5
ns
CL =50pF
tpHL
NOTE 2: Load circuits and voltage waveforms are shown in SeQtion 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-29
-4
-4
r-
C
CD
<
(")
CD
C/I
2-30
SN5405, SN54LS05, SN54S05,
SN7405, SN74LS05, SN74S05
HEX INVERTERS WITH OPEN·COLLECTOR OUTPUTS
DECEMBER 1983 - REVISED MARCH 1988
• Package Option Includes Plastic "Small
Outline" Packages. Ceramic Chip Carriers
and Flat Packages. and Plastic and Ceramic
DIPs
SN5405 ... J PACKAGE.
SN54LS05. SN54S05 ... J OR W PACKAGE
SN7405 ... N PACKAGE
SN74LS05. SN74S05 ... 0 OR N PACKAGE
ITOP VIEWI
• Dependable Texas Instruments Quality and
Reliability
description
These devices contain six independent inverters.
The open-collector outputs require pull-up
resistors to perform correctly. They may be
connected to other open-collector outputs to
implement active-low wired-OR or active-high
wired-AND functions. Open-collector devices are
often used to generate high VOH levels.
BA
BY
5A
5Y
4A
4Y
GND
SN5405 ... W PACKAGE
ITOP VIEWI
lA
2Y
2A
The SN5405. SN54LS05. and SN54S05 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN7405. SN74LS05. and SN74S05 are
characterized for operation from O°C to 70°C.
FUNCTION TABLE
Vee
lA
lY
2A
2Y
3A
3Y
lY
6A
6Y
Vec
GND
3A
3Y
4A
CI)
5Y
CD
CJ
'S
4Y
CD
leach inverter)
INPUT
OUTPUT
A
Y
H
L
L
H
SN54LS05. SN54S05 ... FK PACKAGE
C
(TOP VIEWI
..J
....
....
3 2 1 2019
2A
NC
2Y
NC
3A
logic diagram (positive logic)
lA - - { : : > o - lY
9 10 111213
rOUr«
MZZc;toct
2A - - { : : > o - 2 Y
t?
3A - - { : : > o - 3Y
4A ---C>O--4Y
5A
---c>o--
NC - No internal connection
logic symbol t
lA
5Y
2A
3A
6A ---C>O--6Y
4A
5A
Y
=
A
6A
111
131
151
lY
2Y
3Y
191
1111
(131
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
PRODUCTIOI DATA doc.monts contoin info,mation
currant as of publicatioll date. PrDducts conform to
splciflC8tions par the terms at Texi. Instruments
:=~~~i~·{::I~'i ~:~::i:r :.~a:''':::::'::S~1 not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-31
. SN5405, SN54LS05, SN54S05,
SN7405, SN74LS05, SN74S05
HEX INVERTERS WITH OPEN·COLLECTOR OUTPUTS
schematics (each inverter)
'OS
'LS05
r-------~----------vcc
~--_.~------_vcc
20 kll
8 kll
INPUT
A
~--~~----~----e---GND
~----------~~-e~~--GND
'S05
INPUT.
A
Resistor values are nomjnal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1): '05, 'LS05, 'S05. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: '05, 'S05 .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
'LS05 ......................................................... 7 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Operating free-air temperature range: SN54' . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 De to 125°e
SN74' ................................ oDe to 70 0 e
Storage temperature range ......................................... - 65 °e to 150 De
NOTE 1: Voltage values are with respect to network ground terminal.
·2-32
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5405, SN7405
HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN5405
SN7405
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
VOH
High-level output voltage
5.5
5.5
V
IOL
Low-level output current
16
16
rnA
TA
Operating free-ai r temperature
70
°e
2
V
2
···55
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
IOH
SN5405
TEST CONDITIONSt
Vee
Vee
Vee
VOL
II
Vee
Vee
IIH
Vee
III
Vee
leeH
Vee
leel
Vee
= MIN.
= MIN.
= MIN.
= MIN.
= MAX.
= MAX.
= MAX.
= MAX.
= MAX.
II
=
MIN
TYP*
= 0.8 V.
Vil = 0.7 V.
VIH = 2 V.
VI = 5.5 V
VI = 2.4 V
VI = 0.4 V
VI = 0
VI = 4.5 V
MIN
MAX
TYP*
-1.5
-12 rnA
Vil
SN7405
MAX
= 5.5 V
VOH = 5.5 V
IOl = 16 rnA
-1.5
0.25
VOH
0.25
0.2
0.4
0.2
0.4
1
1
UNIT
V
rnA
V
rnA
40
40
~A
-1.6
-1.6
rnA
6
12
6
12
rnA
18
33
18
33
rnA
TVP
MAX
40
55
ns
8
15
ns
t For conditions shown as MIN or MAX. u'se the appropriate value specified under recommended operating conditions.
i All typical values are at
Vee
:=
5 V. TA
:==
25°C
switching characteristics, Vee = 5 V, T A = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
A
V
PARAMETER
tpLH
tpHl
MIN
TEST CONDITIONS
RL-4kH.
eL - 15 pF
RL
CL
=
400 II.
=
15 pF
UNIT
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
\
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-33
SN54LS05. SN74LS05
HEX INVERTERS WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN54LS05
SN74LS05
UNIT
VCC
Supply voltage
VIH
High~level
VIL
Low-level input voltage
input voltage
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.7
0.8
VOH High-level output voltage
5.5
5.5
IOL
tow-level output current
4
8
rnA
TA
Operating free-air temperature
70
°c
- 55
125
0
V
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
MIN.
VIK
Vee
IOH
Vee ". MIN,
Vee
~
SN74 LS05
UNIT
MIN
- "-
-I
-I
r
SN54LS05
TEST CONDITIONS t
PARAMETER
TYP*
11=-18rnA
VIL = MAX,
VOH = 5.5 V
MIN,
VIH = 2 V,
IOL =4rnA
Vcc = MIN,
VIH = 2 V,
IOL = 8 rnA
0.25
MAX
MIN
TYP*
MAX
- 1.5
- 1.5
0.1
0.1
0.4
0.25
0.4
0.35
0.5
V
VOL
C
V
rnA
-
CD
II
Vce = MAX,
VI = 7 V
n
IIH
Vce = MAX,
VI=2.7V
20
20
p.A
VI
IlL
Vcc= MAX,
VI =0.4 V
-0.4
-0.4
rnA
ICCH
Vcc= MAX,
VI = 0
1.2
2.4
1.2
2.4
rnA
ICCL
Vcc = MAX,
VI=4.5V
3.6
6.6
3.6
6.6
rnA
~.
CD
0.1
0.1
rnA
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
t
All typical values are at
Vee = 5 V, T A
= 2S o C.
switching characteristics, Vee = 5
V, TA = 250 e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
A
Y
PARAMETER
TEST CONDITIONS
tPLH
RL=2kn,
TYP
MAX
UNIT
17
32
ns
15
28
ns
CL = 15 pF
tpHL
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2-34
MIN
TE~S
."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54S05. SN74S05
HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN54S05
SN74S05
UNIT
MIN
NOM
MAx
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
VOH
High-level output voltage
5.5
5.5
V
IOL
Low-level output current
20
20
mA
TA
Operating free-air temperature
70
°c
2
V
2
- 55
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
IOH
t
Vee
Vee
Vee
VOL
Vee
= MIN,
= MIN,
= MIN,
= MIN,
= MAX,
II
Vee
IIH
Vee = MAX,
IlL
Vee
leeH
Vee
leeL
Vee
= MAX,
= MAX,
= MAX,
II
=
MIN
TVP*
MAX
= 5.5 V
VOH = 5.5 V
IOL = 20 mA
VI
VI
= 0.5
=0
= 4.5
UNIT
MAX
V
-1.2
0.25
VOH
mA
0.25
fIj
0.5
50
-2
V
V
V
0.5
1
1
VI - 2.7 V
VI
MIN 'TVP*
-1.2
-18mA
= 0.8 V,
VIL = 0.7 V,
VIH = 2 V,
VI = 5.5 V
VIL
SN74S05
SN54S05
TEST CONDITIONSt
mA
50
~A
-2
mA
FROM
TO
(INPUT)
(OUTPUT)
9
19.8
mA
C
30
54
30
54
mA
...J
MIN
TYP
MAX
UNIT
2
5
7.5
ns
RL: 280 fl,
2
4.5
7
ns
CL: 15 pF
tpHL
A
lI-
= 2Soe (see note 2)
TEST CONDITIONS
tpLH
Q)
19.8
iAIl typical values are at Vee '" 5V. TA "" 25°C
PARAMETER
-S;
9
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
switching characteristics, Vee = 5 V, TA
Q)
(.)
y
tpLH
RL=280n,
7.5
ns
7
ns
CL = 50pF
tpHL
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-35
2-36
SN5406. SN541L SN7406. SN7416
HEX INVERTER BUFFERS/DRIVERS WITH
OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
DECEMBER 1983-REVISED MARCH 1988
• Converts TTL Voltage Levels to MOS Levels
SN5406. SN5416 .•. J OR W PACKAGE
SN7406. SN7416 ... N PACKAGE
• High Sink-Current Capability
(TOP VIEW I
• Input Clamping Diodes Simplify System
Design
Vee
6A
6Y
5A
5Y
4A
1Y
• Open-Collector Driver for Indicator Lamps
and Relays
2Y
3A
3Y
GND
• Inputs Fully Compatible with Most TTL
Circuits
description
These monolithic TTL hex inverter buffers/drivers feature high-voltage open-collector outputs for interfacing with high-level
circ'!its (such as MOS), or for driving high-current loads (such as lamps or relaysl. and are also characterized for use as inverter buffers for driving TTL inputs. The SN5406 and SN7406 have minimum breakdown voltages of 30 volts and the
SN5416 and SN7416 have minimum breakdown voltages of 15 volts. The maximum sink current is 30 milliamperes for the
SN5406 and SN5416. and 40 milliamperes for the SN7406 and SN7416.
II)
logic symbol t
lA
2A
3A
4A
5A
6A
Q)
(,)
schematic
"S;
'06, '16
(1)
r----------.--~.------VCC
I>
(3)
Q)
o
....I
(5)
1.6 kn
(9)
OUTPUT
INPUT
A
(11)
lI-
y
(13)
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
logic diagram (positive logic)
1A
2A
3A
4A
5A
6A
----t>o------t>o------t>o------t>o------t>o------t>o---
L--------e--~~--~---e--GND
1Y
Resistor values shown are nominal.
2Y
3Y
4Y
5Y
6Y
Y~ A
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-37
SN540L SN541L SN740L SN7416
HEX INVERTER BUFFERS/DRIVERS WITH
OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply v';ltage, vee (see Note 11 ............................................................... 7 V
Input voltage (see Note 11 .......... , ............... ' ........... , ......... , .... , , ........ , ..... 5.5 V
Output voltage (see Note, 1 and 21: SN5406, SN7406 Circuits ....................................... 30 V
SN5416, SN7416 Circuits ....................................... 15V
Operating tre"'air temperature range: SN5406, SN5416 Circuits ............................. - 55°C to 125°C
SN7406, SN7416 Circuits ................................ O°C to 70°C
Storage temperature range ................................ _ . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
NOTES: 1. Voltage values are with respect to network ground terminal.
2. This is the maximum voltage which should be applied to any output when it is in the off state.
recommended operating conditions
SN5406
SN7406
SN5416
.__ ..
Vcc
Supply
VIH
High-lf!VI!I Illput voltage
Vil
Low·lev!!1 Input voltage
VOhdql!
SN7416
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
I
I
VOH
High-level output voltage
IOl
Low-level output current
TA
Operating free-air temperature
'16
- 55
V
V
2
'06
UNIT
0.8
0.8
30
30
V
V
15
15
30
40
rnA
70
'c
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN7406
SN5406
PARAMETER
TEST CONDITIONSt
VIK
VCC = MIN,
11=-12rnA
IOH
VCC - MIN,
Vil - 0.8 V,
VOL
Vcc = MIN,
VIH = 2 V
II
Vcc - MAX,
VI-5.5V
SN5416
MIN
",->-
TYP*
SN7416
MAX
MIN
TYP*
UNIT
MAX
- 1.5
-1.5
V
0.25
0.25
rnA
IIOl - 16 rnA
0.4
0.4
IIOL - ~
0.7
0.7
1
1
VOH'.\; ~
V
rnA
IIH
Vce = MAX,
VIH=2.4V
40
40
~A
III
Vcc - MAX,
VIL - 0.4 V
- 1.6
-1.6
rnA
lecH
Vcc - MAX
30
48
30
48
rnA
ICCl
Vcc - MAX
32
51
32
51
rnA
t For co~djtions shown as MIN or MAX, use t~e appropriate value specified under recommended operating conditions.
+ All
typIcal values are at Vce = 5 V, T A
~ VOH ~ 30 V for '06 and 15 V for '16.
~
IOL
= 25
C.
= 30 mA fOr SN54' and 40 mA for SN74'.
switching characteristics, Vee = 5 V, TA = 25°e (see note 3)
PARAMETER
tPlH
tPHl
FROM
TO
(INPUT)
(OUTPUT)
A
Y
TEST CONDITIONS
Rl=110n
CL = 15pF
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-38
TEXAS •
-INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
TYP
MAX
10
15
15
23
UNIT
ns
ns
SN5407. SN5417. SN7407. SN7417
HEX BUFFERS/DRIVERS WITH
OPEN·COLLECTOR HIGH·VOLTAGE OUTPUTS
DECEMBER 19B3-REVISED MARCH 1988
SN5407. SN5417 ... J OR W PACKAGE
SN7407. SN7417 ... N PACKAGE
(TOP VIEWI
• Converts TTL Voltage Levels to MOS Levels
• High Sink·Current Capability
• Input Clamping Diodes Simplify System
Design
lA
lY
2A
2Y
3A
3Y
• Open-Collector Driver for Indicator Lamps
and Relays
• Inputs Fully Compatible with Most TTL
Circuits
VCC
6A
6Y
5A
5Y
4A
4Y
GND
description
These monolithic TIL hex buffers/drivers feature high-voltage open-collector outputs for interfacing with high-level circuits
(such as MOS), or for driving high-current loads (such as lamps or relaysl. and are also characterized for use as buffers for
driving TIL inputs. The SN5407 and SN7407 have minimum breakdown voltages of 30 volts and the SN5417 and SN7417
have minimum breakdown voltages of 15 volts. The maximum sink current is 30 milliamperes for the SN5407 and SN5417.
and 40 milliamperes for the SN7407 and SN7417.
These circuits are completely compatible with most TIL families. Inputs are diode-clamped to minimize transmission-line effects which simplifies design. Typical power dissipation is 145 milliwatts and average propagation delay time is 14
nanoseconds. The SN5407 and SN5417 are characterized for operation over the full military temperature range of - 55° C to
125° C; the SN7407 and SN7417 are characterized for operation from 0" C to 70° C.
logic symbol t
lA
2A
3A
4A
SA
SA
(11
[>
(21 1Y
Q
(31
(41 2Y
(51
lSI 3Y
(91
181 4y
(111
(101 5y
(131
1121 SY
schematic
'07, '17
r-----~~----.--------Vcc
1.6kSl
INPUT
A
OUTPUT
1 This symbol is in accordance with ANSI/IEEE Std
Y
91-1984 and
IEC Publication 617-12.
logic diagram (positive logic)
~---'~---4~--~-----'--GND
lA - - - - t > - - l Y
2A
----t>--
Resistor values shown are nominal.
2Y
3A - - - - t > - - 3 Y
4A - - - - t > - - 4 Y
SA - - - - t > - - 5Y
SA - - - - t > - - S Y
y
~
A
PRODUCTION DATA do.umonls .onlain informalion
currant as of publication date. Products conform to
specifications par the terms of Taxas Instruments
=~~~::=i~8i~:1~7~ ~!:::~ti:; :1~O:=:~:t:~~S nat
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-39
SN5407. SN5417. SN7407. SN7417
HEX BUFFERS/DRIVERS WITH
OPEN-COLLECT9R HIGH-VOLTAGE OUTPUTS
absolute maximuinratings over operating free-air temperature range (unless otherwise noted)
Supply voltage Vcc (see Note 1) ................................................................ ] V
Input voltage (see Note 1) .................................................................... 5.5 V
Output voltage (see Notes 1 and 2): SN5407, SN7407 Circuits ...................................... 30 V
SN5417, SN7417 Circuits ...................................... 15 V
Operating free-air temperature range: SN5407, SN5417 Circuits ............................ _ 55°C to 125°C
SN7407, SN7417 Circuits ................................ OOC to 70°C
Storage temperature range ........................................... , .............. - 65°C to 150°C
NOTES: 1. Voltage values are with respect to network ground terminal,
2. This is the maximum voltage which should be applied to any output when it is in the off state.
recommended operating conditions
SN5407
SN7407
SN5417
-f
-f
r-
Vcc
Supply voltage
V,H
High·level input voltage
V,L
Low-level input voltage
VOH
High-level output voltage
IOL
TA
Low-level output current
SN7417
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
30
30
2
I
I
V
2
'07
'17
Operating free-air temperature
UNIT
MIN
-55
15
15
30
40
125
70
0
V
mA
°c
C
~
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
(i'
TEST CONOITIONS t
PARAMETER
CD
(II
SN5407
SN7407
SN5417
SN7417
MIN
t
UNIT
TYP* MAX
-1.5
V
VCC = MIN,
,,= -12mA
IOH
Vce = MIN,
V,L - 0.8 V,
VOL
VCC = MIN,
V,H = 2 V
VCC- MAX,
V,=5.5V
"
"H
VCC= MAX,
V'H-2.4V
40
40
~A
',L
ICCH
Vce - MAX,
V'L=O.4V
-1.6
-1.6
mA
VCC- MAX
29
41
29
41
mA
ICCL
Vce- MAX
21
30
21
30
mA
TYP
MAX
6
15
20
26
0.25
0.25
IOL = 16 mA
0.4
0.4
IOL =.
0.7
0.7
1
1
VOH -§
I
I
mA
V
mA
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
IOL
= 30 rnA
for SN54' and
= 25° C.
49 mA for SN74'.
switching characteristics. Vee = 5 V, TA
PARAMETER
tpLH
tpHL
tpLH
tpHL
FROM
(INPUT)
25°e (see Note 3)
TO
TEST CONDITIONS
IOUTPUT)
A
Y
RL
=
110 !l.
CL
=
15 pF
A
Y
RL
=
150 !l.
CL
=
50 pF
NOTE 3: Load circuits and voltage waveforms are shown in Section 1,
2-40
MIN
V,K
:I: All typical values are at Vee = 5 v, T A
§ VOH = 30 V for '07 and 15 V for '17 .
•
TYP* MAX
-1.5
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
15
26
UNIT
ns
ns
SN5408,SN54LS08, SN54S08,
SN7408, SN74LS08, SN74S08
QUADRUPLE 2·INPUT POSITIVE·AND GATES
DECEMBER 1983 - REVISED MARCH 1988
• Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers
and Flat Packages. and Plastic and Ceramic
DIPs
SN5408. SN54LS08. SN54S08 ... J OR W PACKAGE
SN7408 ... J OR N PACKAGE
SN74LS08. SN74S08 ... D. J OR N PACKAGE
(TOP VIEW)
VCC
• Dependable Texas Instruments Quality and
Reliability
48
4A
4Y
38
18
lY
2A
28
2Y
GND
description
These devices contain four independent 2-input
AND gates.
The SN5408. SN54LS08. and SN54S08 are
characterized for operation over the full military
temperature range of - 55 °e to 125°e. The
SN7408. SN74LS08 and SN74S08 are
characterized for operation from 0° to 70 0 e.
SN54LS08. SN54S08 ... FK PACKAGE
(TOP VIEW)
U
~ ~ ~ ~~
FUNCTION TABLE (each gate)
INPUTS
lY
4A
OUTPUT
NC
NC
tI)
B
Y
2A
4Y
H
H
H
NC
NC
CI)
()
L
X
L
28
38
X
L
L
A
.S;
CI)
C
....I
logic symbol t
l-
I-
&
lA
NC- No internal connection
(3) lY
18
logic diagram (positive logic)
2A
2B
3A
3B
4A
4B
(5)
(6) 2Y'
l A = D - lY
(9)
(10)
(B)
18
2A==D3A==D-'
4A==D-
3Y
2Y
(12)
(13)
2B
(11) 4Y
3B
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617·12.
Pin numbers shown are for D, J, Nt and W packages.
3Y
4Y
4B
Y=A·8 or Y=A+B
.1
PRODUCTION DATA d... mlnu.ont.in information
•• rront of p.blication data. Prod••U conform to
spacifications par thl terms of '118. Instruments
=:::~~i~ai~:I':J~ ~~:~ti:; :.~a;.~:::.!.~ nat
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-41
SN540B. SN5.4LSOB. SN54S0B.
SN740t SN74LSOB. SN74S0B
QUADRUPLE 2-INPUT POSITIVE-AND GATES
schematics (each gate)
'lS08
'08
~--~.---~~--------~~Vcc
20 kQ
10 kQ
S kQ
120Q
INPUTS
A -......---14~
B--+_-14"
INf
OUTPUT
A
y
B
'SOS
~------,-----.---------~-Vcc
sooQ
2.S kQ
A.~
50Q
___..J
OUTPUT
B-4---+--'
y
L----+------~--~~GND
Resistor values are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage: 'OB, 'SOB .................................................................... 5.5 V
'LSOB ........................................................................ 7 V
Operating free-air temperature range: SN54' ............................................ _55°C to 125°C
SN74' ............................................... oOe to 70°C
Storage temperature range ........................... '.' .............................. -65°e to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
2-42
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5408. SN7408
QUADRUPLE 2·INPUT POSITIVE·AND GATES
recommended operating conditions
SN7408
SN5408
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
V
Vee
Supply voltage
VIH
High-Ieve! input voltage
VIL
Low-level input voltage
0.8
0.8
IOH
High-level output current
0.8
-0.8
rnA
IOL
Low-level output current
16
16
rnA
TA
Operating free-air temperature
70
°e
2
V
2
- 55
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
t
t
TEST CONDITIONS
SN5408
t
SN7408
UNIT
VIK
Vee: MIN,
II: - 12 rnA
VOH
Vee: MIN,
VIH:2V,
IOH: - 0.8 rnA
VOL
Vee: MIN,
Vll:0.8V,
IOl:16rnA
II
Vee: MAX,
VI: 5.5 V
MIN
TVP*
2.4
3.4
MAX
MIN
TVP*
2.4
3.4
- 1.5
0.2
MAX
- 1.5
0.2
0.4
V
0.4
1
1
V
V
rnA
IIH
Vee: MAX,
VI : 2.4 V
40
40
~A
III
Vee: MAX,
VI : 0.4 V
-1.6
- 1.6
rnA
IOS§
Vee: MAX
- 55
rnA
leeH
Vee: MAX,
VI:4.5V
11
21
11
21
rnA
leel
Vee: MAX,
VI: 0 V
20
33
20
33
rnA
- 55
- 20
-18
For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vee"" 5 V, T A == 25°C.
§ Not more than one output should be shorted at a time.
switching characteristics,
Vee ~ 5 V, TA ~ 25° e
FROM
TO
(INPUT)
(OUTPUT)
A or B
V
PARAMETER
(see note 2)
TEST CONDITIONS
tPlH
Rl : 400 n,
MIN
TVP
MAX
UNIT
17.5
27
ns
12
19
ns
Cl:15pF
tpHl
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
.J.!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-43
SN54LSD8. SN74LSD8
QUADRUPLE 2·INPUT POSITIVE·AND GATES
recommended operating conditions
SN54LSD8
SN74LSDB
UNIT
Vee
Supply voltage
VIH
High-level Input voltage
VIL
Low-level input voltage
IOH
High·level output current
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
IOL
Low·level output current
TA
Operating free~air tempf!lillln ()
V
V
2
0.7
O.S
-0.4
-0.4
rnA
S
rnA
70
°e
4
- 55
125
0
V
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
-i
-i
TEST CONDITIONS
SN54LSDB
t
MIN.
11=-1SmA
MIN,
VIH =2 V,
IOH = - 0.4 rnA
Vee = MIN,
VIL = MAX,
IOL = 4 rnA
Vee = MIN,
Vil = MAX,
IOL = 8 rnA
VIK
Vee
VOH
Vee
0
SN74LSDB
UNIT
MIN
TYP*
2.5
3.4
MAX
MIN
TYP*
2.7
3.4
- 1.5
- 1.5
0.4
0.25
MAX
V
0.25
0.4
0.35
0.5
V
VOL
r-
V
C
II
Vee = MAX,
VI = 7 V
0.1
0.1
<
IIH
Vee = MAX,
VI = 2.7 V
20
20
~A
III
Vee = MAX,
)/1=O.4V
-0.4
- 0.4
rnA
eD
(;'
eD
en
t
rnA
IOS§
VCC = MAX
- 100
rnA
ICCH
VCC= MAX,
VI = 4.5 V
2.4
4.8
2.4
4.S
rnA
ICCl
VCC= MAX,
VI =OV
4.4
8.8
4.4
8.8
rnA
-20
- laO
- 20
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions .
All typical values are at Vee = 5 V, T A = 25°C
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
.t:
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
A or B
Y
PARAMETER
TEST CONDITIONS
tplH
Rl=2kn,
Cl = 15pF
tPHl
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2·44
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
TYP
MAX
UNIT
S
15
ns
10
20
ns
SN54S08, SN74S08
QUADRUPLE 2·INPUT POSITIVE·AND GATES
recommended operating conditions
SN54S08
VCC
Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
IOH
High-level output current
SN74S0B
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
IOl
Low-level output current
TA
Operating free-air temperature
UNIT
MIN
0.8
0.8
V
1
-1
mA
20
mA
70
°c
20
- 55
V
V
2
125
a
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN74S08
SN54S08
TEST CONDITIONS
PARAMETER
VIK
VOH
VOL
VCC = MIN,
II = -18 mA
VCC = MIN,
VIH=2V,
VCC = MIN,
t
UNIT
TYP*
2.5
3.4
MAX
MIN
TYP*
2.7
3.4
IOl = 20 mA
MAX
-1.2
-1.2
IOH = -1 mA
Vll=0.8V
MIN
V
V
V
0.5
0.5
1
mA
•
VI
Q)
(J
II
VCC = MAX,
VI = 5.5 V
1
IIH
VCC = MAX,
VI = 2.7 V
50
50
I'A
Q)
III
VCC = MAX,
VI =0.5 V
-2
-2
mA
C
IOS§
VCC = MAX
-40
-100
mA
32
18
32
mA
57
32
57
mA
-100
ICCH
VCC = MAX,
VI = 4.5 V
18
ICCl
VCC = MAX,
VI = 0 V
32
-40
oS
..oJ
lI-
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t
All typical values are at
Vee'"
5 V, T A'" 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
PARAMETER
TEST CONDITIONS
tplH
TYP
MAX
UNIT
4,5
7
ns
5
7,5
ns
Cl=15pF
Rl=2BOn,
tpHl
A or B
MIN
y
tPlH
Cl = 50 pF
Rl=280n,
tpHl
6
ns
7,5
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
l!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-45
-I
-I
r-
oCD
:So
(")
CD
C/)
2-46
SN5409. SN54LS09. SN54S09.
SN740~ SN74LSO~ SN74S09
QUADRUPLE 2·INPUT POSITIVE·AND GATES WITH OPEN·COLLECTOR OUTPUTS
DECEMBER 1983-REVISED MARCH 198B
• Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers
and Flat Packages. and Plastic and Ceramic
DIPs
SN5409. SN54LS09. SN54S09 ... J OR W PACKAGE
SN7409 ... N PACKAGE
SN74LS09. SN74S09 ... D OR N PACKAGE
(TOP VIEW)
• Dependable Texas Instruments Quality and
Reliability
1A
18
1Y
2A
28
2Y
GND
description
These devices contain four independent 2-input
AND gates. The open-collector outputs require
pull-up resistors to perform correctly. They may
be connected to other open-collector outputs to
implement active-low wired-OR or active-high
wired-AND functions. Open-collector devices are
often used to generate higher VOH levels.
VCC
48
4A
4Y
38
3A
3Y
SN54LS09. SN54S09 ... FK PACKAGE
(TOP VIEW)
The SN5409. SN54LS09. and SN54S09 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN7409. SN74LS09. and SN74S09 are
characterized for operation from ooC to 70°C.
3 2 1 2019
1Y
NC
en
Q)
.:;()
2A
NC
28
FUNCTION TABLE (each gate)
INPUTS
OUTPUT
A
B
Y
H
H
L
H
X
X
L
L
-'
lI-
L
NC - No internal connection
logic diagram (positive logic)
logic symbol
lA
18
(1 )
(2)
&
Q
lY
1 A = U - - 1Y
18
(6)
2Y
2A~ __
(8)
3Y
(11)
4Y
(3)
(4)
2A
28
3A
38
4A
48
Q)
o
(51
28~
2Y
(9)
(10)
3 A = U - - 3V
38
(12)
(13)
4 A = U - - 4V
48
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
PRODUCTION DATA do.uments contain inlormation
currant as of publication data. Products confarm to
spacifications par the tarms of Texas Instruments
:=::=i~I{::I~~i ~:~~~ti:; :.~u::::::~:~~ not
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
y ~ A.B or V ~
A +B
2-47
SN5409, SN54LS09, SN54S09,
SN7409, SN74LS09. SN74S09
QUADRUPLE 2·INPUT POSITIVE·AND GATES WITH OPEN·COLLECTOR OUTPUTS
~--~~----~--~~GND
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ......................... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: '09, 'S09 .................................................................... 5.5 V
'LS09 ........................................................................ 7 V
Off-state output voltage ...................................................................... 7 V
Operating free-air temperature range: SN54' ........................................... _55°C to 125°C
SN74' .............................................. oOe to 70°C
Storage temperature range .......................................................... -65°e to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
2·48
TEXAS . "
INSTRUMENTS
POST OFFiCe BOX 656012 • DALLAS. TeXAS 75265
SN5409. SN7409
QUADRUPLE 2·INPUT POSITIVE·AND GATES WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN5409
SN7409
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-Ievet input voltage
0.8
0.8
V
VOH
High-level output voltage
5.5
5.5
V
16
rnA
70
°e
2
V
2
16
IOL
Low·level output current
TA
Operating free-air temperature
- 55
1/.b
0
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
MIN
TEST CONDITIONSt
VIK
Vce = MIN,
II = - 12 rnA
IOH
Vee = MIN,
VIH=2V.
VOH = 5.5V
IOL = 16 rnA
VOL
Vee = MIN,
VIL=0.8V
II
VCC = MAX,
VI = 5.5 V
TYP*
0.2
MAX
UNIT
-1.5
V
0.25
rnA
0.4
1
V
Q)
(,)
'S
IIH
Vec = MAX,
VI = 2.4 V
40
}J.A
IlL
Vec = MAX,
VI=0.4V
-1.6
rnA
ICCH
Vee = MAX,
VI = 4.5 V
11
21
rnA
ICCL
Vec = MAX,
VI = 0 V
20
33
rnA
t For conditions shown as MIN or MAX, use the appropriate
t All typical values are at Vee = 5 V, T A = 2SoC.
II)
rnA
Q)
o
.......J....
value specified under recommended operating conditions.
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
Aor B
Y
TEST CONDITIONS
PARAMETER
tpLH
MIN
TYP
MAX
UNIT
21
32
ns
16
24
ns
eL = 15pF
RL=400B,
tpHL
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-49
SN54LSOL SN74LS09
QUADRUPLE 2·INPUT POSITIVE·AND GATES WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN54LS09
SN74LS09
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
V
Vee
Supply voltage
VIH
High-level input voltage
VIL
LOW-level input voltage
0.7
0.8
VOH
High-level output voltage
5.5
5.5
IOL
Low-level output current
4
8
mA
TA
Operating free-air temperature
70
°c
2
V
2
- 55
125
0
V
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
•
SN54LS09
TEST CONDITIONS t
PARAMETER
VIK
TVP*
11=-18mA
MAX
MIN
<
(:;'
CD
en
MAX
-1.5
-1.5
0.1
0.1
V
VIH= 2V,
Vee = MIN,
VIL = MAX,
IOL =4mA
Vec = MIN,
VIL =MAX,
IOL =8mA
II
VCC = MAX,
VI = 7 V
0.1
0.1
mA
IIH
VCC = MAX,
VI = 2.7 V
20
20
I'A
III
VCC= MAX,
VI=O.4V
-0.4
-0.4
mA
ICCH
VCC= MAX,
VI = 4.5 V
2.4
4.8
2.4
4.8
mA
ICCl
VCC= MAX,
VI =OV
4.4
8.8
4.4
8.8
mA
VOH=5.5V
0.25
0.4
0.25
0.4
0.35
0.5
mA
V
VOL
CD
TVP*
VCC = MIN,
IOH
-I
-I
rC
Vce = MIN,
SN74 LS09
UNIT
MIN
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
1: All typical values are at Vee = 5 V r T A = 25°C.
switching characteristics, Vee = S V, T A = 2Soe (see note 2)
PARAMETER
tpLH
tpHL
FROM
TO
(INPUT)
(OUTPUT)
Aor B
V
TEST CONDITIONS
CL=15pF
Rl=2kU,
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2·50
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
MIN
TVP
MAX
20
35
UNIT
ns
17
35
ns
SN54S09. SN74S09
QUADRUPLE 2·INPUT POSITIVE·AND GATES WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN54S09
SN74S09
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
VOH
High-level output voltage
5.5
5.5
V
IOL
Low-level output current
20
20
mA
TA
Operating free-air temperature
70
°c
2
- 55
12;
V
V
2
0
V
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONSt
MIN
TYP*
MAX
UNIT
VIK
Vcc = MIN,
11=-18mA
-1.2
V
IOH
Vcc = MIN,
VIH = 2 V,
VOH=5.5V
0.25
rnA
IOL =20rnA
0.5
VOL
VCC = MIN,
VIL = 0.8 V,
II
VCC= MAX,
VI=5.5V
1
rnA
V
IIH
VCC= MAX,
VI = 2.7 V
50
JJ.A
III
VCC= MAX,
VI=0.5V
-2
rnA
ICCH
VCC= MAX,
VI =4.5V
18
32
rnA
ICCl
VCC= MAX,
VI =OV
32
57
rnA
I/)
Q)
Co)
oS
Q)
C
..J
I-
....
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All tYpical values are at Vee"" 5 V, T A"" 25°C.
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
TEST CONDITIONS
PARAMETER
tplH
Rl = 280!!,
TYP
MAX
UNIT
6.5
10
ns
6.5
10
ns
CL = 15pF
tpHl
A or B
MIN
Y
tPLH
9
ns
9
ns
CL = 50pF
Rl=280n,
tpHL
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
-III
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-51
....r-....
C
CD
5.
(")
CD
C/I
2-52
SN541o, SN54LS1o, SN54S1o,
SN741o, SN74LS1o, SN74S1o
TRIPLE 3·INPUT POSITIVE·NAND GATES
DECEMBER 1983-REVISED MARCH 1988
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers
and Flat Packages. and Plastic and Ceramic
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN5410 ... J PACKAGE
SN54LS10. SN54S10 ... J OR W PACKAGE
SN7410 ... N PACKAGE
SN74LS10. SN74S10 ... 0 OR N PACKAGE
(TOP VIEW)
18
2A
28
2C
2Y
GND
description
These devices contain three independent 3-input
NAND gates.
The SN5410. SN54LS 10. and SN54S 10 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN7410. SN74LS10. and SN74S10 are
characterized for operation from O°C to 70°C.
FUNCTION TABLE
INPUTS
VCC
1C
1Y
3C
38
3A
3Y
1A
SN5410 ... W PACKAGE
(TOP VIEW)
1A
18
1Y
VCC
2Y
2A
(each gatel
OUTPUT
Y
1C
3Y
3C
GND
38
3A
A
B
C
H
H
H
L
L
X
H
X
X
L
X
X
H
SN54LS10. SN54S10 ... FK PACKAGE
X
L
H
(TOP VIEW)
28~_ _~2C
U
~ ~ ~ ~~
logic symbol t
lA
18
(1)
lY
2A
NC
&
(2)
28
lC
NC
2A
2C
NC
38
2Y
28
2C
3A
38
3C
(9)
(10)
NC - No internal connection
3Y
(11)
logic diagram (positive logic)
tThis symbol is in accordance with ANSI/IEEE Std. 91·1984 and
IEC Publication 617-12.
Pin numbers shown are for D. J. and N packages.
positive logic
I
~:
I
~:
I
:: I
~:1C
2C
Y=~orY=A+B+C
3C
}-1Y
}-2Y
}-3Y
}-4Y
4C
PRODUCTION DATA documlnts c.ntli. informltio.
current a. of publicatian date. Products conform to
specifications par the 'arms Taxes Instruments
:'~:::i~I{::1~7i ~:~:~ti:: :.~-:::::~:~~ nat
0'
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-53
SN5410, SN54LS10, SN54S10,
SN741~ SN74LS1~ SN74S10
TRIPLE 3·INPUT POSITIVE·NAND GATES
schematics (each gate)
'10
~----------'--vcc
INPUTS
A
B
c~l-I---e
'Ls10
'510
~~--~~------~t--Vcc
~--~~------~~vcc
20 kll
8 kll
120 Il
2.8 kll
900 Il
50 Il
INPUTS
A _____-MlI---..
8-I_--I+----e
c --I-l-.........f4---e-l'
A
8
C--I--I~
y
~~~------,-----~~--~-GND
Resistor values shown are nominal.
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: '10, 'S10 .................................................... 5.5 V
'LS10 ......................................................... 7 V
Operating free-air temperature range: SN54' . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
SN74' ................................ ooe to 70°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
2-54
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5410. SN7410
TRIPLE 3-INPUT POSITIVE-NAND GATES
recommended operating conditions
SN5410
SN7410
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low·level input voltage
0.8
0.8
IOH
High-level output current
0.4
-0.4
mA
'6
mA
70
°e
2
IOL
Low-level output current
TA
Operating free--air temperature
2
V
16
- 55
125
V
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
t
SN5410
TEST CONDITIONS t
PARAMETER
SN7410
UNIT
MIN
TYP;
2.4
3.4
MAX
MIN
TYP;
2.4
3.4
MAX
- 1.5
- 1.5
V
VIK
Vee = MIN,
11=-12mA
VOH
Vee = MIN,
VIL = 0.8 V,
IOH = - 0.4 mA
VOL
Vee = MIN,
VIH=2V,
IOL ='6 mA
II
Vee= MAX,
VI =5.5V
1
IIH
Vee= MAX,
VI = 2.4 V
40
IlL
Vee= MAX,
VI = 0.4 V
- '.6
mA
IOS§
Vee = MAX
-·55
mA
leeH
Vee = MAX,
VI = 0 V
3
6
3
6
mA
leeL
Vee = MAX,
VI = 4.5 V
9
16.5
9
16.5
mA
0.2
0.2
0.4
- 1.6
- 20
- 55
- '8
V
VI
,
V
Q)
mA
40
p.A
-s
o
0.4
CJ
Q)
...J
lI-
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee = 5 v, T A = 2SoC.
§ Not more than one output should be shorted at a time.
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
A, Bore
Y
PARAMETER
TEST CONDITIONS
tPLH
RL =400n,
eL = '5 pF
tpHL
MIN
TYP
MAX
"
22
ns
15
ns
7
UNIT
~OTE 2: Load circuits and voltage waveforms are shown in Section 1,
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-55
SN54LS1 D. SN74LS1D
TRIPLE 3·INPUT POSITIVE·NAND GATES
recommended operating conditions
SN54LS10
SN74LS10
UNIT
Vee
Supply voltage
V,H
High·h!vl!1 Input voltage
V,L
Low-level Input voltage
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
2
2
V
IOH
High·level output
CUIII!III
-0.4
-0.4
mA
IOL
Low-level output currellt
4
8
mA
TA
Operating free-air templ!tature
70
°e
- 55
125
0
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LS10
t
MIN TYP*
-I
-I
r-
SN74LS10
MAX
MIN TYP*
-1.5
-1.5
V,K
Vee = MIN,
1,=-18mA
VOH
Vee = MIN,
V,L = MAX,
IOH = - 0.4 mA
Vee = MIN,
V,H = 2 V,
IOL = 4 mA
Vee = MIN,
V'H=2V,
IOL=8mA
2.5
2.7
3.4
CD
n'
CD
til
V
V
Vee = MAX,
V, = 7 V
"H
Vee = MAX,
V, = 2.7 V
V, =O.4V
"
<
V
0.4
VOL
C
3.4
0.4
0.25
UNIT
MAX
0.25
0.1
0.1
mA
20
20
JlA
-0.4
mA
-100
mA
0.6
1.2
mA
1.8
3.3
mA
-0.4
',L
Vec = MAX,
IOS§
Vee = MAX
ICCH
Vee = MAX,
V, =0 V
0.6
1.2
leCL
Vee = MAX,
V, = 4.5 V
1.8
3.3
-100
-20
0.5
- 20
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee:: 5 V, TA:: 2Soc.
§ Not more than one output shol,lld be shorted at.a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, Vee
= 5 V, TA = 2Soe (see note 2)
FROM
TO
(lNPUTI
(OUTPUT)
A, Bore
V
PARAMETER
tPLH
TEST CONDITIONS
RL=2kn,
TVP
MAX
9
15
ns
10
15
ns
UNIT
eL = 15 pF
tPHL
NOTE 2: Load circuits and voltage wavefor:ms are shown in Section 1.
2·56
MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54S10. SN74S10
TRIPLE 3·INPUT POSITIVE·NAND GATES
recommended operating conditions
SN54S10
Vee
Supply voltage
V,H
High-level input voltage
SN74S10
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4,5
5
5,5
4.75
5
5.25
2
V
V
2
V,L
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
-1
-1
mA
20
mA
70
°c
IOL
Low-level output current
TA
Operating free-air temperature
20
- 55
125
0
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN54S10
t
SN74S10
UNIT
MIN
TYP*
MAX
MIN
TYP*
-1.2
1,'-18mA
V,K
VCC'MIN,
VOH
VCC'MIN,
V,L'O.8V,
'OH' -1 mA
VOL
VCC'MIN,
V,H'2V,
'OL'20rnA
2.5
2.7
3.4
MAX
-1.2
V
0.5
V
V
3.4
0.5
VCC'MAX,
V,'5.5V
1
1
"H
VCC'MAX,
V,'2.7V
50
50
jJA
',L
VCC'MAX,
V,'O.5V
-2
-2
mA
-100
mA
,.
rnA
"
-40
IOS§
Vce'MAX
ICCH
VCC'MAX,
V,' 0 V
ICCL
VCC'MAX,
V,, 4.5 V
-100
-40
7.5
12
7.5
12
mA
15
27
15
27
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee"" 5 V, T A"" 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
PARAMETER
TEST CONDITIONS
tPLH
RL'280n,
TYP
MAX
UNIT
3
4.5
ns
3
5
ns
CL'15pF
tPHL
A, B or C
MIN
Y
tpLH
RL' 280 I!,
4.5
ns
5
ns
CL' 50 pF
tpHL
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-57
-t
-t
rC
CD
<
n'
CD
CIl
2-58
SN54LS11. SN54S11.
SN74LS11. SN74S11
TRIPLE 3-INPUT POSITIVE-AND GATES
APRIL 1985-REVISED MARCH 1988
•
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers
and Flat Packages. and Plastic and Ceramic
DIPs
SN54LSll. SN74S11 ... J OR W PACKAGE
SN74LSll. SN74S11 ... 0 OR N PACKAGE
ITOP VIEW)
1A
18
2A
28
2C
2Y
GND
Dependable Texas Instruments Quality and
Reliability
description
These devices contain three independent 3-input
AND gates.
SN54LS11. SN54S11 ... FK PACKAGE
The SN54LS 11 and SN54S 11 are characterized
for operation over the full military temperature
range of - 55 ce to 125 ce. The SN74LS 11 and
SN74S 11 are characterized for operation from
oce to 70 ce.
FUNCTION TABLE
INPUTS
A
B
C
VCC
1C
1Y
3C
38
3A
3Y
ITOP VIEW)
u
al:,!:~~~
3 2
1 20 19
1Y
2A
(each gate)
NC
NC
OUTPUT
28
3C
Y
NC
NC
2C
38
H
H
H
H
L
X
L
X
X
L
X
X
X
L
L
9 10111213
L
NC - No internal connection
logic symbol t
lA
lB
1C
2A
2B
2C
3A
3B
3C
11 )
logic diagram (positive logic)
&
12)
112)
lY
11AB==:J
)----,
1Y
1 C - -......_ ....
(13)
13)
14)
16)
22AS--l
2C
•
2Y
~~d
15)
(9)
(10)
(8)
Y
3Y
(11 )
Y
)-
2Y
)-3Y
A.B.C or
~
A + B+ C
tThis symbol is in accordance with ANSI/IEEE Std. 91 1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, Nt and W packages.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications par the terms of Texas Instruments
~~~~~:~~i~ar::,~1~ ~!:~~~ti:f :IIO::~:~:t:;s~S not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·59
SN54LS11. SN54S11.
SN74LS11. SN74S11
TRIPLE 3·INPUT POSITIVE·AND GATES
schematics (each gate)
"LS11
r--.----.-----.--vee
20 kn
8kn
120n
INPUTS
A~~--f.4-"
B ~-.>--~.-.
e
-+~~H'-.
'---:!+--<......Nv-+- OUTPUT
y
GND
-I
-I
r-
'511
C
Vee
CD
<
2,8kn
rr
CD
2kfl goon
son
til
y
B
e-+--+-.....
Resistor values shown are nominal.
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ..... , . , ... , .. , .. , ....... , ............ , , . , . . . .. 7 V
Input voltage: '511 ....... , .. , ..... , .. , .. , .. , ....... , ........ , ...... , ... , .. 5.5 V
'LS11 . , .. , .... , ..... , . , ... , .. , ....... , ............. , .. , . . . . . .. 7 V
Operating free-air temperature range: SN54' ..... , .... , ......... , ..... ,. - 55°C to 125°C
SN74' , , .. , ....... , .. , .. , ............. ooe to 70°C
Storage temperature range, .. , ... , . , . , ... , .. , .......... , ... , .. , .... -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal,
2-60
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54LS11, SN74LS11
TRIPLE 3·INPUT POSITIVE·AND GATES
recommended operating conditions
SN54LSll
Vee
S uppl y va Itage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
SN74LSll
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
IOL
Low-level output current
TA
Operating free-air temperature
UNIT
MIN
2
V
0.7
0.8
- 0.4
-0.4
4
- 55
125
V
0
V
mA
8
mA
70
°e
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP*
MAX
MIN
TYP *
2.7
3.4
Vee" MIN,
11"-18mA
VOH
Vee" MIN,
VIH=211,
IOH =-O.4mA
Vee = MIN,
VIL = MAX,
IOL"4mA
Vee = MIN,
VIL = MAX,
IOL=8mA
II
Vee = MAX,
VI = 7 V
IIH
Vee = MAX,
VI=2.7V
IlL
Vee" MAX,
VI " 0.4 V
IOS§
Vee" MAX
2.5
3.4
0.25
MAX
- 1.5
- 1.5
VIK
VOL
SN74LS11
SN54LSll
t
0.4
UNIT
V
V
0.25
0.4
0.35
0.5
V
Q)
(.)
0.1
0.1
mA
'S:
20
20
/lA
C
........
- 0.4
- 100
- 20
en
- 20
- 0.4
mA
- 100
mA
IceH
Vee = MAX,
VI "4.5V
1.8
3.6
1.8
3.6
mA
leeL
Vee = MAX,
VI = 0 V
3.3
6.6
3.3
6.6
mA
TYP
MAX
UNIT
8
15
ns
10
20
ns
Q)
..J
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
i All typical valuesareat Vee'" 5 V, TA
= 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5 V, T A = 2Soe (see note 2)
PARAMETER
'PLH
FROM
IINPUT)
A, 8 or e
TO
(OUTPUT)
y
TEST CONDITIONS
RL = 2 kn,
MIN
eL=15pF
tpHL
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-61
SN54S11, SN74S11
TRIPLE 3·INPUT POSITIVE·AND GATES
recommended operating conditions
SN54S11
SN74S11
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
VCC
Supply voltage
VIH
Hl~Jh·h!vl!1
Vil
low-It!vel IIlput voltage
0.8
0.8
V
IOH
High-levI!! output
-1
-1
mA
Input voltage
2
2
CUI T!!II!
IOl
Low-level output clir It'lll
TA
Operating free-air
20
tl~/llpt'r,jture
- 55
125
V
V
0
20
mA
70
°c
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
-I
-I
r-
TEST CONOITIONS
MIN,
SN74S11
SN54S11
t
MIN TYP
*
MAX
MIN
TYP
- 1.2
11=-18mA
VIK
Vec
VOH
VCC . MIN,
V I H=2V,
IOH=-lrnA
VOL
Vec = MIN,
Vil = 0.8 V,
IOl
II
Vec = MAX,
VI = 5.5 V
=
2.5
20 rnA
MAX
-1.2
2.7
3.4
UNIT
*
V
V
3.4
0.5
0.5
1
1
V
mA
IIH
Vec = MAX,
VI = 2.7 V
50
50
IlA
III
Vec = MAX,
VI=0.5V
. 2
-2
rnA
~.
IOS§
Vce = MAX
CD
leCH
Vec = MAX,
VI = 4.5 V
Icel
VCC = MAX,
VI
oCD
n
fA
- 100
rnA
13.5
24
13.5
24
rnA
24
42
24
42
rnA
-40
=
0 V
-100 -40
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vee = 5 V, T A - 25°C.
t
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
switching characteristics, Vee
PARAMETER
FROM
(lNPUTI
= 5 V, T A = 25°e
TO
(OUTPUTI
(see note 2)
TEST CONOITIONS
tplH
Rl=280n,
tpHl
A. B orC
tplH
MAX
4.5
7
5
7.5
UNIT
ns
ns
6
ns
7.5
ns
Cl=50pF
tpHl
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2-62
TYP
Cl = 15 pF
y
Rl=280n,
MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 6550{2 • DALLAS, TeXAS 75265
SN5412. SN54LS12
SN7412. SN74LS12
TRIPLE 3·INPUT POSITIVE·NAND GATES WITH OPEN·COLLECTOR OUTPUTS
DECEMBER 1983 - REVISED MARCH 1988
• Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
SN5412. SN54LS12 ... J OR W PACKAGE
SN7412 ... N PACKAGE
SN74LSI2 ... D OR N PACKAGE
(TOP VIEW)
lA
• Dependable Texas Instruments Quality and
Reliability
VCC
lC
18
description
lY
28
3C
2C
38
2Y
3A
GND
3Y
These devices contain three independent 3-input NAND
gates with open-collector outputs. The open-collector
outputs require pull-up resistors to perform correctly.
2A
They may be connected to other open-collector outputs
to implement active-low wired-OR or active-high wired-
SN54LS12 ... FK PACKAGE
(TOP VIEW)
AND functions. Open-collector devices are often used to
generate higher VOH levels.
U
"'~~~~
The SN 5412 and SN 54LS 1 2 are characterized for
operation over the full military temperature range of
3 2
-55°C to 125°C. The SN7412 and SN74LS12 are
characterized for operation from DOC to 7DoC.
FUNCTION TABLE
INPUTS
leach gate)
OUTPUT
A
B
C
H
L
H
X
X
X
L
H
X
X
X
L
2019
2A
4
lY
NC
5
NC
I/)
28
6
3C
NC
7
CJ
NC
2C
8
38
9 10111213
Y
Q.)
'S:
Q.)
o
...I
....
....
L
H
H
H
NC - No internal connection
logic diagram (positive logic)
logic symbol t
lA
lB
lC
2A
2B
2C
3A
3B
3C
(1)
llAB ------.I
} - lY
----,
lC --""11_-'_
&
(2)
(3)
(4)
?
~
""-----
~~ ------i
}-
22AB
2C
(131
3A
2Y
(5)
Y
~
" , - - - - 2Y
3Y
A.B.C or
(9)
(10)
3Y
(11)
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
PRODUCTION DATA doc.mants contain information
current IS of publication data. Products conform to
specifications per the terms of Texas Instruments
:~~~~:~~i~ai~:I~~8 ~::i~:i:; ~~o::~:::~:~~s not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-63
SN5412, SN54LS12
SN7412, SN74LS12
TRIPLE 3·IIIIPUT POSITIVE·NANO GATES WITH OPEN·COLLECTOR OUTPUTS
schematics (each gate)
'LS12
'12
Vee
r-_---Vee
INPUTS
1.6 kn
17kn
8kn
A
INPUTS
A
B
B
OUTPUT
e
Y
e
GND
OUTPUT
y
Resistor values shown are nominal.
~~~--_--~~-~-GND
-I
-I
rC
absolute maximum ratings over operating free-air temperature range (unless otherWise noted)
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage: '12 ........................................................................ 5.5 V
'LS12 ........................................................................ 7 V
Off·state output voltage ...................................................................... 7 V
Operating free·air temperature: SN54' ................................................. -55°C to 125°C
SN74' ........................ ',' .......................... dOc to 70°C
Storage temperature range .......................................................... _65°C to 150°C
CD
<
Cr
CD
(I)
NOTE 1: Voltage values are with respect to network ground terminal.
2-64
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TeXAS 75285
SN5412, SN5412
TRIPLE 3·INPUT POSITIVE· NAND GATES WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN7412
SN6412
UNIT
, VCC
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
Supply voltage
V
V
VIH
High-level input voltage
VIL
Low·level input voltage
0.8
0.8
VOH
High~level
output voltage
5,5
5.5
V
IOL
Low-level output current
16
16
rnA
TA
Operating free-air temperature
70
°c
2
2
- 55
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VIK
IOH
SN5412
TEST CONDITIONSt
PARAMETER
MIN
TYP*
SN7412
MAX
MIN
MAX
TYP*
-1.5
VCC = MIN,
II = -12 rnA
VCC = MIN,
Vil = 0.8 V,
VOH = 5.5 V
VCC = MIN,
VIL = 0.7 V,
VOH = 5.5 V
VOL
VCC = MIN,
VIH = 2 V,
IOl = 16 rnA
II
VCC= MAX,
VI = 5.5 V
-1.5
0,25
0,25
0,2
0,2
0.4
0.4
1
1
UNIT
V
rnA
V
rnA
IIH
VCC = MAX,
VI = 2,4 V
40
40
p,A
III
VCC = MAX,
VI = 0.4 V
-1.6
-1.6
rnA
ICCH
VCC - MAX,
rnA
VCC = MAX,
VI =
VI = 4,5 V
6
ICCl
16,5
rnA
°
3
9
3
9
6
16,5
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*AII typical values are at VCC = 5 V, T A = 25 DC,
switching characteristics, Vee = S V, T A = 2Soe (see note 2)
FROM
TO
II NPUT)
(OUTPUT)
PARAMETER
tPLH
tpHL
TEST CONDITIONS
A, B or C
y
RL"4kl!,
CL = 15pF
RL = 400 l!,
CL = 15pF
MIN
TYP
MAX
UNIT
35
45
ns
B
15
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS .."
INSTRUMENTS
POST OfFICE BOX 655012 .. DALLAS, TEXAS 75265
2-65
SN54LS12. SN74LS12
TRIPLE 3·INPUT POSITIVE· NAND GATES WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN74LS12
SN54LS12
VCC
Supply voltage
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
V
V
2
VIH
High~lellel
VIL
Low-Iuvel input voltage
0.7
O.B
V
VOH
High-Ip.vel output voltage
5.5
5.5
V
IOL
Low-level output cur rent
4
B
TA
Operating free-air temperature
input voltage
125
- 55
70
0
mA
°c
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
SN54LS12
TEST CONDITIONS t
PARAMETER
-I
-I
rC
VIK
Vcc = MIN.
II = - lBmA
IOH
VCC = MIN.
VIL = MAX.
SN74LS12
UNIT
MIN
TYP*
VOH=5.5V
Vce = MIN,
VIH = 2 V,
IOL = 4 mA
Vce = MIN.
VIH = 2 V,
IOl = B mA
0.25
MAX
MIN
TYP*
MAX
-1.5
- 1.5
0.1
0.1
0.4
0.25
0.4
0.35
0.5
V
mA
V
VOL
II
VCC= MAX,
VI = 7 V
CD
:S.
IIH
Vce= MAX,
VI = 2.7 V
0.1
0.1
mA
20
20
itA
n
III
VCC= MAX,
VI - 0.4 V
CD
VI
ICCH
VCC= MAX,
VI = 0
0.7
1.4
0.7
1.4
rnA
ICCl
VCC = MAX,
VI = 4.5 V
1.B
3.3
1.8
3.3
mA
-0.4
- 0.4
t
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:t
AU typical values are at Vee
=5
V. T A
=
mA
25°C.
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
A, B orC
Y
PARAMETER
tpLH
TEST CONDITIONS
Rl=2kn,
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
TYP
MAX
17
32
ns
15
28
ns
UNIT
Cl = 15 pF
tPHL
2-66
MIN
-1!1
INSTRUMENTS
POST OFFICE Box 655012 • DALLAS, TEXAS 75265
SN5413. SN54LS13. SN7413. SN74LS13
DUAL 4·INPUT
POSITIVE·NAND SCHMITT TRIGGERS
DECEMBER 1 9B3-REVISED MARCH 19BB
SN5413, SN54LSI3 ... J OR W PACKAGE
SN7413 ... N PACKAGE
SN74LSI3 ... 0 OR N PACKAGE
• Operation from Very Slow Edges
• Improved Line-Receiving Characteristics
ITOP VIEW)
• High Noise Immunity
VCC
2D
2C
NC
2B
2A
2V
lA
lB
NC
lC
lD
IV
GND
description
Each circuit functions as a 4-input NAND gate, but
because of the Schmitt action, it has different input
threshold levels for positive (VT +) and for negative
going IVT _) signals.
These circuits are temperature-compensated and can
SN54LSI3 ... FK PACKAGE
be triggered from the slowest of input ramps and still
give clean, jitter-free output signals.
ITOP VIEW)
U
al~~~~
The SN5413 and SN54LS13 are characterized for operation over the full military temperature range of -55°C
to 125°C. The SN7413 and SN74LS13 are characterized for operation from DOC to 7DoC.
3
NC
NC
lC
NC
lD
logic symbol t
lA
lB
lC
10
2A
2B
2C
20
11)
2 1 20 19
2C
NC
NC
NC
2B
4
5
6
7
B
9 10111213
&IT
(2)
IV
(4)
15)
NC - No internal connection
(9)
logic diagram (positive logic)
(10)
2V
(12)
lA 11)
lB (2)
(13)
lC 14)
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
IEC Publication 617·13.
Pin numbers shown are for 0, J, N, and W packages.
1015)
(9)
2A
110)
28
1121
(13)
2C
20
y
PRODUCTION DATA documents contain Information
currant 81 of publication data. Products conform to
spacifications par the terms of TexIs Instruments
::~==i~ai~:I~'i ~:~::i:f ~r:=:::::t::':'
not
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 15265
~
ABeD
2-67
SN5413, SN54LS13, SN7413, SN74LS13
DUAL 4-INPUT
POSITIVE-NAND SCHMITT TRIGGERS
schematics
'13
INPUTS
A
~>-----\+,
B-t_-~-+
C-1H_-~
v
o -1H-+_!4-'
'LS13
20 kn
INPUTS
A_~--:F-{
OUTPUT
B-1H~-~
'-:t<~---.---*--
C-1H_-~
-I
-I
v
o --1H-+_f4-'
r-
C
CD
<
~~~~----+--~~-~-----------+--~---GND
c=i"
CD
IJI
Resistor values are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage. Vee (see Note 1) .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: '13 ........................................................................ 5.5 V
'LS13 ........................................................................ 7V
Operating free-air temperature: SN54' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°e to 125°e
SN74' ...................................... : ............. oOe to 700 e
Storage temperature range ......................................................... - 65°e to 1500 e
NOTE 1: Voltage values are with respect to network ground terminal.
2-68
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5413, SN7413
DUAL 4·INPUT
POSITIVE·NAND SCHMITT TRIGGERS
recommended operating conditions
SN5413
Vee
Supply voltage
10H
High-level output current
SN7413
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-0.8
rnA
16
rnA
70
°e
-0.8
16
10l
Low-level output current
TA
Operating free-air temperature
UNIT
MIN
- 55
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDITIONSt
PARAMETER
MIN
UNIT
TYP* MAX
VT+
Vee = 5 V
1.5
1.7
2
V
VT_
Vee - 5 V
0.6
0.9
1.1
V
0.4
0.8
Hysteresis
(VT+ -VT_)
Vee = 5 V
MIN.
II =
12rnA
V
1.5
VIK
Vee
VOH
Vee = MIN.
VI =0.6V.
10H = - 0.8 rnA
VOL
Vee = MIN.
VI - 2 V.
10l -16 rnA
IT+
Vee = 5 V,
VI = VT+
-0.65
IT-
Vee- 5 V,
VI - VT-
-0.85
II
Vee = MAX,
VI =5.5V
IIH
Vee= MAX,
VIH-2.4V
III
lOS §
Vee= MAX,
Vil = 0.4 V
Vee= MAX,
leeH
Vee
= MAX
leel
Vee = MAX
2.4
3.4
0.2
V
V
0.4
V
rnA
rnA
(/)
1
rnA
40
Q)
()
-1.6
JlA
rnA
-55
rnA
14
23
rnA
20
32
rnA
-1
-18
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
; All typical values are at
.:;
Q)
C
..J
lI-
Vee"" 5 V. TA "" 2SoC.
§ Not more than one output should be shorted at a time.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
tPlH
tpHl
FROM
TO
IINPUT)
(OUTPUT)
Any
Y
TEST CONDITIONS
Rl = 400 11,
el = 15 pF
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
MIN
TYP
MAX
18
27
UNIT
ns
15
22
ns
2-69
SN54LS13, SN74LS13
DUAL 4-INPUT
POSITIVE-NAND SCHMITT TRIGGERS
recommended operating conditions
SN54LS13
Vee
Supply voltage
IOH
High-Invel output current
IOL
Low-I(!vtll output current
TA
Oper"IJn~1
SN74LS13
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-0.4
rnA
- 0.4
4
125
- 55
free-air temperaturn
UNIT
MIN
0
8
rnA
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
-VT+
VT_
Vee" bV
""" .
vef_ bV
Hysteresis
(VT+-VT_I
SN54LS13
TEST CONDITIONS t
PARAMETER
Vee
!>V
TYPt
MAX
1.4
, 0.5
1.6
1.9
0.8
1
0.4
0.8
0.4
0.8
2.5
3.4
2.7
3.4
MIN,
VIK
Vee
VOH
Vee = MIN,
VOL
r0-
C
CD
<
c:;CD
C/)
UNIT
TYPt
MAX
1.4
1.6
1.9
V
0.5
0.8
1
V
MIN
V
--,
II = - 18 rnA
VI =0.5V,
-1.5
IOH = - 0.4 rnA
IIOl =4rnA
-i
-i
SN74LS13
MIN
Vee = MIN,
0.25
-1.5
0.4
VI = 1.9 V
IIOl = 8 rnA
V
0.25
0.4
0.35
0.5
IT+
Vee = 5 V,
VI = VT+
-0.14
- 0.14
IT_
Vee = 5 V,
VI = VT_
-0.18
-0.18
II
Vee= MAX,
VI = 7 V
IIH
Vee= MAX,
III
Vee = MAX,
V
V
rnA
rnA
rnA
0.1
0.1
VIH = 2.7 V
20
20
).LA
Vll=O.4V
-0.4
-0.4
rnA
IOS§
Vee = MAX
-100
rnA
leeH
Vee = MAX
2.9
6
2.9
6
rnA
leel
Vee=MAX
4.1
7
4.1
7
rnA
-100
- 20
- 20
t For' conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee = 5 V, T A'" 2SoC.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5 V , T A = 25°e
PARAMETER
tplH
tPHl
2-70
FROM
TO
IINPUT)
(OUTPUT)
Any
Y
TEST CONDITIONS
Rl = 2 kll,
el = 15 pF
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
MIN
TYP
MAX
15
22
ns
18
27
ns
UNIT
SN5413. SN54LS13. SN7413. SN74LS13
DUAL 4·INPUT
POSITIVE·NAND SCHMITT TRIGGERS
PARAMETER MEASUREMENT INFORMATION
TEST
POINT
VCC
INPUT
---..t
......~-<1""Hw-i~
O~:6~~ ~
TEST
I
I-t PHL
CL
I
--!
OV
~tPLH'"
~
"l\
OUTPUT
(see Note Bl
~VOH
Vo ref
1.3 V
VOL
(See Note Cl
lOAO CIRCUIT
NOTES:
\-V~~e~~--3V
VI ref(HI
FROM
VOLTAGE WAVEFORMS
A. All diodes are 1 N3064 or equivalent.
B. CL includes probe and jig capacitance.
C. Generator characteristics and reference voltages are:
Reference Voltages
Generator Characteristics
VI reflHI
1.7 V
VI refill
0.9 V
Vo ref
10 ns
tf
10 ns
15 ns
6 ns
1.6 V
O.B V
1.3 V
Zout
PRR
tr
SN54'!SN74'
50n
1 MHz
SN54LS' /SN74lS'
son
1 MHz
1.5V
TYPICAL CHARACTERISTICS OF '13 CIRCUITS
NEGATIVE·GOING THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
>
POSITIVE·GOING THRESHOLD VOLTAGE
vs
FREE·AIR TEMPERATURE
>
I
1.70
I 0.90
1
Vee = 5 V
&
JS
1.6 9
'tlI
1.61
~
~ 1.68
1,·66
..."0
0.87
t:.
'0
1.64
~
0.84
:
1.63
C!J
0.
1.62
.~
:;;
Z'
0,82
~
q>
:;
I
>tt
g)
c
·S
C
0.88
.... 1.65
Q)
o
Q)
0 .89
'"e 0.86
,/
,.....
Vee = 5V
0'
........
0.85
........
V
...I
lI-
........
0.83
Z
1 0.81
1.6 1
1.60
-75 -50 -25
I
0
25
50
75
TA - Free-Air Temperature -
100
I- 0.80
-75-50-25
>
125
°c
25
50
75
T A - Free-Air Temperature _
FIGURE 1
100
125
°c
FIGURE 2
HYSTERESIS
vs
FREE·AI R TEMPERATURE
850
Vee = 5 V
>
E
840
830
I
.a
820
e 810
t;
i
l - f-
-
.......
800
I
I 790
... 780
>
f"".
""""
I
...
+ 770
>
760
750
- 75 - 50 - 25
a
2S
50
75
TA - Free-Air Temperature _
100
125
°c
FIGURE 3
Data for temperatures below
aOe
and 70°C and supplV voltages below 4.75 V and above 5.25 V are applicable for SN5413 only.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-71
SN5413, SN7413
DUAL 4·INPUT
POSITIVE·NAND SCHMITT TRIGGERS
TYPICAL CHARACTERISTICS OF '13 CIRCUITS
THRESHOLD VOLTAGES
DISTRIBUTION OF UNITS
FOR HYSTERESIS
vs
SUPPLY VOLTAGE
2.0
ve~= L
TA-25°e
1.8
5
TA=25°e
I
"\
1.6
>
I
1.4
-
f-- I--
r--
~v~Going Threshold Voltage, VT+
! 1.2
'0
>
1.0
~
0.8
...
99% ARE
ABOVe
~
\
J
V
~
"
0.4
0.2
r-.
740 760 780 800 820 840 860
VT+ - VT-":" Hysteresis -mY
720
Negative·Going Threshold Voltage, VT_
0.6
o
880
4.75
5.25
5
VT+ - VT _ - Hysteresis - mV
4.5
FIGURE 4
FIGURE 5
HYSTERESIS
OUTPUT VOLTAGE
vs
vs
SUPPLY VOLTAGE
-r---.-""T"-T""""'-""
2.0 r-~-....
>
INPUT VOLTAGE
4
Vee=5V
TA = 25°e
-IT
0.4
0.8
-IT+
-
1.6 ~~--+--+--+--~~--+--l
I 1.4
.~
~~--+--+--+--~~--+--l
~
1.2
~~--+--+--+--~~--+--l
I
1.0
J---l--t--+-+--J---l--t---j
~
5.5
t
0.8
b...J--I--+"",,~=I==I==+=~
~
0.6
J---l--t--+-+--J---l--t---j
>
0.4
J---l--t--+-+--/-'---l--t---j
I-
0.2 ~~--+--+--+--+-~--+--l
0~~_-L_4-~_-L_~~~-"
4.5
4.75
5.25
o
o
1.2
1.6
Vee - Supply Voltage - V
Vee - Supply Voltage - V
FIGURE 6
FIGURE 7
Data for temperatures below
2·72
5.5
aOc and
70°C and supply voltages below 4.75 V and above 5.25 V are applicable for SN5413 onlv.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
SN54LS13, SN74LS13
DUAL 4·INPUT
POSITIVE·NAND SCHMITT TRIGGERS
TYPICAL CHARACTERISTICS OF 'LS13 CIRCUITS
POSITIVE-GOING THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
NEGATIVE-GOING THRESHOLD VOLTAGE
vs
FREEAIR TEMPERATURE
1.70
! 1.68
.
~
~
"'C
~
>
Vee' 5 V
1.69
'0
i
>
1-67
./
'0
1.66
~ 1.65
~
1.64
0.90
Vee' 5 V
I 0.89
---
:~ 1.63
'0
]
0.86
0.85
~
0.84
~
I 1.62
0.87
g.
"i
~
0.88
V
i-"'"
V
V""
V ....
0.83
0.82
I
~ 1-61
~ 0.81
>
1.60
-75 -50 -25
0
25
50
75
100
TA - Free-Air Temperature _ °c
125
0.80
25
50
75
100
-75 -50 -25
TA - Free-Air Temperature _ °c
FIGURE 8
125
en
Q)
CJ
FIGURE 9
'S;
Q)
o
-I
HYSTERESIS
vs
FREE-AIR TEMPERATURE
850
vel. t
Vee' 5 V
840
>
830
.~
810
J:
800
E
~ 820
;.
I
.!- 790
--
5
f-TA=25°C
~
.........
~
lI-
DISTRIBUTION OF UNITS
FOR HYSTERESIS
I
,
I ' ........
>
I 780
99% ARE
A80VE
... 770
+
>
or"
760
750
-75 -50 - 25
25
50
75 100
TA - Free-Air Temperature _ "'e
720
125
740
V
J
"
r-
760 780 800 820 840 860
VT+ - VT _ - Hysteresis - mV
FIGURE 11
FIGURE 10
\
880
Data for temperatures below O°C and above 70°C and supply voltages below 4.75 V and above 5.25 V are applicable for SN54LS13 only.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-73
SN54LS13. SN74LS13
DUAL 4·INPUT
POSITIVE·NAND SCHMITT TRIGGERS
TYPICAL CHARACTERISTICS OF 'LS13 CIRCUITS
THRESHOLD VOLTAGES AND HYSTERESIS
2.0
1.8
1.6
~ 1.4
!o1.2
OUTPUT VOLTAGE
v.
vs
SUPPLY VOLTAGE
INPUT VOLTAGE
TA = 25°e
-
j
1.0 !!
c
~ 0.8
--1---+-11
> 3
Positive-Going Threshold Voltage, VT+
I
Negativ1.GOinl Thre!hold tOltag!. VT
J-
~
o
Hysteresis, Vr+ - Vr-
I
~ 0.6
o
>
0.4
-t
-t
rC
CD
<
r--+-i-+--tt-t--t--I-+t-t--l
E
~
i2
1
f---+--+-+--+I-+-+-i-++-+---4
0.2
o
o~~~-~~-~~~-~~~
4.5
4.75
5
5.25
o
5.5
0.4
0.8
1.2
1.6
VI - Input Voltage - V
Vee - Supply Voltage - V
FIGURE 13
FIGURE 12
(i'
CD
I/)
Data for temperatures below O°C and above 70°C and supply voltages below 4.75 V and above 5.25 V are applicable for SN54LS13 only.
2-74
.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN5413. SN54LS13. SN7413. SN74LS13
DUAL 4-INPUT
POSITIVE-NAND SCHMITT TRIGGERS
TYPICAL APPLICATION DATA
I
-1
I TTL SYSTEM
t------I8-D---
CMOS
_______
~
I
I
~
L~
~--
SINE-WAVE
~SCILLATOR
I
I
TTL SYSTEM INTERFACE
FOR SLOW INPUT WAVEFORMS
PULSE SHAPER
f/)
Q)
0
0.1 Hz to 10 MHz
-VT+
oS
_VT_
0
Q)
330n
INPUT
I
I
I
II
II
I
II
..J
ll-
OUTPUT
THRESHOLD DETECTOR
MULTIVIBRATOR
liB
Open-collector
output
r----,
INPUT
I
----j
I
I
V
)
rI
OUTPUT
JT-
I
I
l-'lJ I
--I
PULSE STRETCHER
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-75
-i
-i
r0-
C
(I)
!S.
o(I)
CJ)
2-76
SN5414. SN54LS14.
SN7414. SN74LS14
HEX SCHMITT·TRIGGER INVERTERS
DECEMBER 1983-REVISED MARCH 1988
SN5414, SN54LS14 ... J OR W PACKAGE
SN7414 ... N PACKAGE
SN74LS14 ... 0 OR N PACKAGE
• Operation from Very Slow Edges
• Improved Line·Receiving Characteristics
(TOP VIEW)
• High Noise Immunity
1A
VCC
6A
6Y
5A
5Y
4A
4Y
1Y
description
2Y
3A
3Y
GND
Each circuit functions as an inverter, but because of the
Schmitt action, it has different input threshold levels for
positive (VT + ) and for negative going (VT_) signals.
These circuits are temperature-compensated and can
be triggered from the slowest of input ramps and still
give cle,In, jitter-free output signals.
SN54LS14 ... FK PACKAGE
(TOP VIEW)
U
The SN5414 and SN54LS14 are characterized for operation over the full military temperature range of -55°C
to 125°C. The SN7414 and the SN74LS14 are characterized for operation from 0° C to 70° C.
logic symbolt
1A
2A
3A
4A
(1)
~~~~~
3 2
1 2019
2A
NC
2Y
NC
3A
(3)
(5)
(9)
5A
(11)
6A
(13)
NC - No internal connection
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
Pin numbers shown are for D. J, N, and W packages.
logic diagram (positive logic)
1A~1Y
2A~2Y
3A~3Y
4A~4Y
5A~5Y
6A~6Y
Y
=
A
PRODUCTION DATA docomants conllin i.'o,mllio.
currant of publication dl'l. Products conform to
specification. par the terms at TI.I. IRStruml.ts
I'
:::::i;·i~:I:7i ~!:3::i~n :.~o::;::~::~ nDt
TEXAS .."
INSTRUMENlS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-77
SN5414. SN54LS14. SN7414. SN74LS14
HEX SCHMITT·TRIGGER INVERTERS
schematics
'14
6kn
INPUT
A ~-'-
I
t
~
"0
"0
-5
NEGATIVE·GOING THRESHOLD VOLTAGE
vs
FREE·AIR TEMPERATURE
>
1.70
0.90
Vee= 5 V
I
Vee'" 5 V
1.69
~ 0.89
V
1.68
~ 0.88
>
1.67
1.66
~
.c
~
0.87
ji
0.86
......-
' ; 0.85
l- 1.65
r'
c
ll'
'0 1.64
(;>
'0 0.84
(;>
: 0.83
~
g' 0.82
Z
I 0.81
I
I- 0.80
> -75 -50 -25
.!
I
1.63
V
VI-""
.~
1.62
1.61
+
~ 1.60
- 75 - 50 - 25
25
50
75
TA - Free-Air Temperature _
100
°c
FIGURE 1
125
25
50
75
TA - Free-Air Temperature -
HYSTERESIS
vs
FREE·AIR TEMPERATURE
100
125
°c
FIGURE 2
850
VCC '" 5 V
>
840
E 830
l - I""--
I
.;; 820
E
r--..- ........
~ 810
r-- -
t-- =-
>
::J: 800
I
~
790
I 780
+
~ 770
-
760
750
-75 -50 -25
25
50
75
TA - Free-Air Temperature _
FIGURE 3
100
125
°c
Data for temperatures below 0° C and 70° C and supplV voltages below 4.75V and above 5.25 V are appl icable for SN5414 only.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-81
SN5414, SN7414
HEX SCHMITT·TRIGGER INVERTERS
TYPICAL CHARACTERISTICS OF '14 CIRCUITS
THRESHOLD VOLTAGES
DISTRIBUTION OF UNITS
FOR HYSTERESIS
vs
SUPPLY VOLTAGE
2.0
Vee =5 V
TA=25°e
TA=25°e
1.8
1.6
I'
> 1.4
!
'0
\
vV
740
760
780
800
820
~tive.Going Threshold Voltage, VT+
I
..,>
1/
-I--+- t---"
,
840 860
~
1.2
1.0
0.8
~
Negative-Going Threshold Voltage, VT _
... 0.6
0.4
r-
0.2
o
880 900
4.5
VT + - VT _ -Hysteresis - mV
-I
-I
4.75
5.25
VT+ - VT- - Hysteresis - rylV
FIGURE 4
5.5
FIG,URE 5
r-
o
(1)
:$.
(")
(1)
HYSTERESIS
en
OUTPUT VOLTAGE
vs
vs
SUPPLY VOLTAGE
INPUT VOLTAGE
4
Vee =5 V
TA = 25°e
f-"--+-+-+--If--t-+--1
1.4 f--t-+-t-.,-+-t--t--t
> 1.6
I
~
~
1.2 f-~f-.-f--+--+-+-+--+-~
>
~
1.0
f-~'---f--+--+-+-+--+-~
~
0.8
b~--i--4==~=*:::=I===t:::::::J
~
0.6
f-~--f--+--+-+-+--+-~
....
f---I--+---+--+-+-+-+-----I
0.2 f---t-+-t-.,-+-t--t--t
>
....-!T
I
VT+
r--
3
I
!
~
;; 2
S-
c5
I
o
>
1
> 0.4
o
o
Vee - Supply Voltage - V
0.4
1.2
1.6
0.8
Vee - Supply Voltage - V
2
FIGURE 7
FIGURE 6
Data for temperatures below OoC and 70°C and supply voltages below 4.75 V and above 5,25 V are applicable for SN5414 only.
2·82
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS14, SN74LS14
HEX SCHMITT·TRIGGER INVERTERS
TYPICAL CHARACTERISTICS OF 'LS14 CIRCUITS
NEGATIVE-GOING THRESHOLD VOLTAGE
vs
FRE&AIRTEMPERATURE
POSITIVE-GOING THRESHOLD VOLTAGE
v.
FREE-AIR TEMPERATURE
1.70
>
Vee=5V
~
1.69
t~
tl.68
~ 1.67
...
'0
1
1.66
~ 1.65
./
..--
0.88
:8e 0.86
t;c 0.85
~
V ..
0.84
L,....--
....... .....
V ....
lO.83
~I 082
.
~1.61
-~
Vee = 5V
... 0.87
;g 1.64
:~ 1.63
iI 1.62
1.60
0.90
I 0.89
~ 0.81
>
-50 -25
0
25
50
75
TA - Free-Air Temperature _
100
125
0.80
- 75 - 50 - 25
°c
0
25
50
75
TA - Free-Air Temperature _
100
125
'>
FIGURE9
FIGURE 8
U)
CI)
(,)
°e
CI)
C
...J
HYSTERESIS
FREE-AIR TEMPERATURE
850
1 .1.
Vee= 5 V
840
>
e
.~
Vee· 5 V
f-TA = 25°e
830
~ 820
810
t!
isoo
--
io....
......... .........
I
.!.790
I
\
, ......
>
99% ARE
ABOVE
I 780
+
~ 770
760
750
-75-50-25
0
25
50
75100125
TA - Free-Air Temperature _ °c
~
720
/
\
J
"-
-
740 760 780 800 820 840 860 880
VT+ - VT-- Hysteresis - mV
FIGURE 11
FIGURE 10
Data for temperatures below
lI-
DISTRIBUTION OF UNITS
FOR HYSTERESIS
v.
aOe and above 70°C and supply voltages below 4.75 V and above 5.25 V are applicable for
TEXAS ...,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS14 only.
2-83
SN54LS14. SN74LS14
HEX SCHMITT·TRIGGER INVERTERS
TYPICAL CHARACTERISTICS OF 'LS14 CIRCUITS
OUTPUT VOLTAGE
THRESHOLD VOLTAGES AND HYSTERESIS
vs
vs
SUPPLY VOLTAGE
INPUT VOLTAGE
4
2.0
TA = 25°e
I.B
1.6
>
I
1.4
Vee=5V
TA' 25°e
L--I---j---I
i-- r--p'ositive-Going Threshold Voltage, VT+
>
~ 0.8
o=
Hysteresis, VT+
c--
3
t
~
J
~
.tT+
I
f1.2
~ 1.0 ~ Nega'i.l.GOin~ Th,.!hOld tOI.agi. VT ----=
:!!
rt
VT-
!2
I
~ 0.6
o
>
0.4
1
0.2
-I
-I
rC
CD
o
4.5
4.75
5.25
5
Vee - Supply Vol.age - V
5.5
o
o
0.8
1.2
1.6
VI -Input Voltage - V
FIGURE 12
FIGURE 13
Data for temperatures below OoC and above 70°C and supply voltages below 4.75 V and above 5.25 V are applicable for SN54LS14 only.
<
t=i'
CD
VI
2-84
0.4
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5414. SN54LS14.
SN7414. SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
TYPICAL APPLICATION DATA
-1
I
I
I TTL SYSTEM
CMOS
L
_______
r--~-I
~
I
~
SINE-WAVE
OSCILLATOR
~-I
I
TTL SYSTEM INTERFACE
FOR SLOW INPUT WAVEFORMS
PULSE SHAPER
U)
Q)
(.)
'S;
0.1 Hz to 10 MHz
Q)
C
330n
..J
l-
IINPUT
MUL TIVIBRATOR
THRESHOLD DETECTOR
Iy
Open·collector
,---,
output
INPUT
I
----1
I
I
)
1-....
--j
rI
I
I
l_>~J
lJ
OUTPUT
----
I
PULSE STRETCHER
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-85
-t
-t
rC
CD
5.
(')
CD
CIJ
2-86
SN54LS15. SN54S15.
SN74LS15. SN74S15
TRIPLE 3·INPUT POSITIVE·AND GATES WITH OPEN·COLLECTOR OUTPUTS
APRIL 1985-REVISEO MARCH 1988
SN54LS15. SN54S15 ... J OR W PACKAGE
SN74LS15. SN74S15 •.. 0 OR N PACKAGE
• Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers
and Flat Packages. and Plastic and Ceramic
DIPs
ITOP VIEW)
• Dependable Texas Instruments Quality and
Reliability
VCC
1C
1Y
3C
38
3A
28
2C
2Y
description
These devices contain three independent 3-input
AND gates with open-collector outputs. The
open-collector outputs require pull-up resistors
to perform correctly. They may be connected to
other open-collector outputs to implement
active-low wired-OR or active-high wired-AND
functions. Open-collector devices are often used
to generate high VOH levels.
GND
SN54LSI5. SN54S15 ... FK PACKAGE
(TOP VIEW)
U
e?~~~~
3 2
2A
NC
28
NC
2C
The SN54LS15 and SN54S15 are characterized
for operation over the full military temperature
range of - 55°C to 125°C. The SN74LS 15 and
SN74S15 are characterized for operation from
OOC to 70°C.
1Y
NC
4
5
6
NC
38
7
8
en
Q)
(,)
"S;
Q)
FUNCTION TABLE
INPUTS
A
B
C
(each gate)
..oJ
OUTPUT
C
V
H
H
H
H
L
X
X
L
X
L
X
L
X
X
L
L
NC - No internal connection
logic diagram (positive logic)
18
lC
2A
28
2C
3A
38
3C
(1)
(2)
I
I
I
~~
lC
~:
2C
logic symbol t
lA
~~
3C
&
Q
(12)
IV
(13)
Y
(3)
(4)
tt-
=
}-lV
}-2V
}-3V
A.B·C or
V=A + B+ C
(6)
2V
(5)
(9)
(10)
(8)
3V
(11)
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
PRODUCTION DATA documenls contain informalion
currant 8S of publication date. Products conform to
spacifications par the terms of Taxas Instruments
~~~~~:~~i~ai~:I~lJi ~!:~:~i:r ~~O:::~:t:~~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-87
SN54LS15. SN54S15.
SN74LS15. SN74S15
TRIPLE 3-INPUT POSITIVE·AND GATES WITH OPEN·COLLECTOR OUTPUTS
schematics (each gate)
'LS15
r -....~~....~............-vcc
INPUTS
20 kn
10 kn
A-.-+f--"
6-+-1..,..-..
OUTPUT
Y
C-H-.,.....-{
'S15
r-............. -....~....................--vcc
-I
-I
r-
OUTPUT
INPUTS
A
~
Y
6
<
C-H~
(i'
CI)
til
~~~""""""~""~~""~~""4--GND
Resistor values shown are nominal.
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage. Vee (See Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: 'S 1 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
·LS15 ................................................................. 7V
Off -state output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Operating free-air temperature range: SN54' ............... . . . . . . . . . . . . . . . . . . . .. - 55 De to 125 De
SN74' ........................................ oDe to 70 De
Storage temperature range .................................................. -65 De to 150 De
NOTE 1: Voltage values are with respect to network ground terminal.
2-88
. TEXAS"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS15, SN74LS15
TRIPLE 3·INPUT POSITIVE·AND GATES WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN54LS15
SN74LS15
UNIT
VCC
Supply voltage
VIH
High~level
VIL
Low-level input voltage
input voltage
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
V
V
2
V
0.7
O.B
VOH High-level output voltage
5.5
5.5
IOL
Low-level output current
4
B
mA
TA
Operating free-air temperature
70
°c
- 55
125
0
V
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
SN54LS15
PARAMETER
SN74LS15
TEST CONDITIONSt
UNIT
MIN
VIK
VCC = MIN.
II =-lBmA
IOH
VCC = MIN.
VIH = 2 V.
TVP* MAX
VOH=5.5V
VCC = MIN.
VIH
= 2 V.
IOL = 4 mA
Vee = MIN.
VIH' 2 V.
IOL = B mA
0.25
MIN
TVP*
MAX
-1.5
- 1.5
O.t
0.1
0.4
0.25
0.4
0.35
0.5
V
rnA
V
VOL
II
VCC= MAX.
VI = 7 V
0.1
0.1
mA
IIH
VCC= MAX.
VI=2.7V
20
20
/lA
IlL
VCC= MAX.
VI = 0.4 V
- 0.4
rnA
ICCH
VCC· MAX.
VI = 4.5 V
1.8
3.6
l.B
3.6
rnA
ICCL
VCC' MAX.
VI =OV
3.3
6.6
3.3
6.6
rnA
-0.4
t For conditions shown as MIN or MAX, usa the appropriate value
t: All typical values are at Vee'"' 5 V. T A = 25°C.
switching characteristics, Vee
=5 V, TA = 25° e (see note 2)
FROM
TO
UNPUTJ
(OUTPUT)
A, B,ore
V
PARAMETER
tpLH
specified under recommended operating conditions.
TEST CONDITIONS
RL = 2 kil.
MIN
TVP
MAX
UNIT
20
35
ns
17
35
ns
CL = 15 pF
tPHL
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-89
SN54S15. SN74S15
TRIPLE 3·INPUT POSITIVE·AND GATES WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN54S15
Vee
Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
SN74S15
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
V
V
2
V
0.8
0.8
VOH High-level output voltage
5.5
5.5
IOl
Low-level output current
20
20
rnA
TA
Operating free-air temperature
70
°e
-55
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
-t
-t
I""'"
o
CD
<
n'
CD
(I)
t
MIN
TEST eONDITIONSt
Vee = MIN,
11= -18 rnA
IOH
Vee = MIN,
VIH=2V,
VOH = 5.5 V
IOL = 20 rnA
Vee = MIN,
VIH = 2 V,
II
Vee = MAX,
VI = 5.5 V
MAX
-1.2
VIK
VOL
TYP*
0.25
0.5
1
IIH
Vee= MAX,
VI = 2.7 V
50
III
Vee = MAX,
VI =0.5V
-2
leeH
Vee= MAX,
VI =4.5V
leel
Vee = MAX,
VI =OV
UNIT
V
rnA
V
rnA
~A
rnA
10.5
19.5
rnA
24
42
rnA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
= 25°C.
:t. All typical values are at Vee::: 5 V, T A
switching characteristics, Vee
= 5 V, TA = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
PARAMETER
TEST CONDITIONS
tpLH
Rl=280n,
tPLH
MAX
UNIT
5.5
8.5
ns
6
9
ns
y
Rl = 280n,
8.5
ns
8
ns
el = 50 pF
tpHL
NOTE 2: Load circuits and voltage waveforms are shown in Section 1 .
2-90
TYP
eL = 15 pF
tPHL
A, B, or e
MIN
. TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN74LS19A. SN74LS24A
SCHMITT·TRIGGER POSITIVE·NAND GATES
AND INVERTERS WITH TOTEM·POLE OUTPUTS
JANUARY 1981 - REVISED MARCH 1988
•
Functionally and Mechanically Identical to
'LS13, 'LS14, and 'LS132, Respectively
•
Improved Line·Receiving Characteristics
•
P·N·P Inputs Reduce System Loading
•
Excellent Noise Immunity with Typical
Hysteresis of 0.8 V
SN74lS19A ... D. J. OR N PACKAGE
(TOP VIEW)
1Ah
IY
2A
2Y
3A
3Y
GND
1 V,4
2
13
3
12
4
11
5
10
6
9
7
8
Vec
6A
6Y
SA
SY
4A
4Y
description
Each circuit functions as a NAND gate or
inverter, but because of the Schmitt action, it
has different input threshold levels for positivegoing (VT +) and for negative-going (VT _ )
signals. The hysteresis or backlash, which is the
difference between the two threshold levels
(VT + - VT _), is typically 800 millivolts.
SN74lS24A ... D, J, OR N PACKAGE
(TOP VIEW)
2A
28
2Y
GND
These circuits are temperature-compensated and
can be triggered from the slowest of input ramps
and still give clean, jitter-free output signals.
lA
2A
3A
4A
SA
6A
11
5
6
7
U)
Q)
logic diagrams (positive logic)
logic symbols t
(1)
4
Vec
48
4A
4Y
38
3A
3Y
SN74lS19A
SN74lS19A
.IT
lA~lY
(3)
2A~2Y
(S)
(9)
CJ
·S
Q)
c
.....
....
....
3A~3Y
(11)
(13)
4A~4Y
5A~5Y
6A~6Y
Y
~
SN74lS24A
SN74lS24A
lA
18
2A
28
3A
38
4A
48
(1)
A
:: ____~I~JT__~~lY
&IJ
(2)
(4)
.rr
2 A = 1 9 - 2Y
28
(S)
:: ____~I_JT~~3Y
:: ____~I_jJ~~4Y
(9)
(10)
(12)
(13)
Y
~
AB
tThese symbols are in accordance with ANSIIIEEE Std 91-1984
and lEe Publication 617-12.
PRODUCTION DATA documant. contain information
cun8nt as of publication date. Products conform to
specifications per the terms of Texas Instruments
:~~:=~~~ar::I~'li ~=::i:; :.~a::;:~~:~~ not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-91
SN74LS19A, SN741S24A
SCHMITT·TRIGGER POSITIVE·NAND GATES
AND INVERTERS WITH TOTEM·POLE OUTPUTS
schematic (each gate)
r-----~~--~--------~----~--------------~----
25 kn
120n
NOM
NOM
VCC
INPUTS
A----~--------~
OUTPUT
Y
B------,----I
I
I
C------~-1---I
0- - - -
-
I
I
I
I
I
-l- I
.J. - . , -
I
I
'f 'f 'f
~~~~~--------~----~------_+----------~----------~--~---- GND
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ..... .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 70 DC
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 DC to 150 DC
recommended operating conditions
Supply voltage,
vee
NOM
MAX
5
5.25
V
-400
~A
8
mA
70
°c
High-level output current, 10H
Low-level output current, IOL
0
Operating free-air temperature, T A
2-92
TEXAS
-I./}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
MIN
4.75
SN74LS19A, SN74LS24A
SCHMITT·TRIGGER POSITIVE·NAND GATES
AND INVERTERS WITH TOTEM·POLE OUTPUTS
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
TEST CONDITIONSt
MIN
TYPf
MAX
UNIT
VT+
PARAMETER
Vee
~
5 V
1.65
1.9
2.15
V
VT-
Vee
~
5 V
0.75
1.0
1.25
V
Hysteresis
Vee
~
5 V
VIK
Vee
~
MIN,
II
VOH
Vee
~
MIN,
VI
IVT+ - VT-)
0.9
V
-1.5
V
0.4
-18 mA
~
.=
IOH
VT-min
~
-0.4 mA
2.7
V
3.4
IIOL ~ 4 mA
0.25
I IOL ~ 8 mA
0.35
0.5
-2
-20
-5
-30
0.4
V
VOL
Vee
~
MIN,
VI = VT +max
IT+
IT-
Vee
~
5 V,
Vee
~
5 V,
VI ~ VT+
VI ~ VT-
II
Vee
~
MAX,
VI
~7V
IIH
Vee
~
MAX,
VI
~
2.7 V
20
IlL
IOS§
Vee
~
MAX,
VI
~
0.4 V
-50
~A
Vee
~
MAX,
VI
~
Va
-100
mA
leeH
Vee
~
MAX,
VI
~OV
Vee
leeL
~
MAX,
~
VI
0.1
~
-20
0 V
4.5 V
~A
~A
mA
'LS19A
9.9
'LS24A
6.6
18
12
'LS19A
17
30
'LS24A
11
20
~A
mA
en
CD
mA
(.J
.S;
CD
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
I All typical values are at VCC ~ 5 V, TA ~ 25°C.
C
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
...I
lI-
switching characteristics. Vee - 5 V. TA = 25°e (see Figure 1)
FROM
TO
(INPUT!
(OUTPUT)
tpLH
Any
tpHL
Any
Y
Y
PARAMETER
tpLH
tpHL
~
~
TEST CONDITIONS
RL
~
2 kG,
eL
~
SN74LS24A
SN74LS19A
MIN
15 pF
MIN
UNIT
TYP
MAX
TYP
MAX
13
20
13
20
ns
18
30
25
40
ns
Propagation delay tim., low-to-high-l.v.1 output
Propagation delay time, high-to-Iow-I.vel output
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-93
SN74LS19A, SN74LS24A
SCHMITT·TRIGGER POSITIVE·NAND GATES
AND INVERTERS WITH TOTEM·POLE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
TEST
POINT VCC
RL
FROM
OUTPUT
UNDER
TEST
(See Note Al
1
CL,(See Note B)
':"
LOAD CIRCUIT
NOTES:
VOLTAGE WAVEFORMS
A. All diodes are IN3064 or equivalent.
B. CL includes probe and circuit capacitance.
C, The generator characteristics are: PRR ~ 1 MHz, tr
~
15 ns, tp
~
6 ns, Zo
FIGURE 1
~
~
r-
o
CD
<
Cr
CD
en
2-94
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
~
50 {J,
SN5420, SN54LS20, SN54S20,
SN7420, SN74LS20, SN74S20
DUAL 4·INPUT POSITIVE·NAND GATES
DECEMBER 1983 - REVISED MARCH 1988'
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN5420 ... J PACKAGE
SN54LS20, SN54S20 ... J OR W PACKAGE
SN7420 ... N PACKAGE
SN74LS20, SN74S20 ... 0 OR N PACKAGE
(TOP VIEW)
1A
1B
NC
1C
description
These devices contain two independent 4-input NAND
1D
1Y
GNO
gates.
The SN5420. SN54LS20. and SN54S20 are
characterized for operation over the full military range
of - 55 DC to 125 DC. The SN7420. SN74LS20. and
SN74S20 are characterized for opertion from 0 DC to
70 D C.
SN5420 ... W PACKAGE
(TOP VIEW)
B
C
0
H
H
H
H
L
L
X
X
X
X
X
X
H
L
X
X
X
X
L
L
X
X
VCC
NC
2A
2B
OUTPUT
A
10
1C
1B
GNO
2Y
20
2C
1A
1Y
NC
FUNCTION TABLE (each gatel
INPUTS
VCC
2D
2C
NC
2B
2A
2Y
V
H
H
H
SN54LS20. SN54S20 ... FK PACKAGE
(TOP VIEW)
U
Ill«~~~
logic symbol t
lA
lB
lC
10
2A
2B
2C
20
(1)
3
&
NC
NC
1C
NC
10
(2)
lV
(4)
(5)
(9)
1 2019
2C
NC
NC
NC
4
5
6
2B
8
10111213
(10)
>cu>«
~ZZNN
2Y
(12)
(!)
(13)
NC - No internal connection
tThis symbol is in accordance with ANSI/IEEE Std. 91~1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
logic diagram
~~==t }-,Y
10---....2
A - -__
_-
~~==i
20
}-2Y
positive logic Y = A'B'C'O or V =
PRODUCTION DATA doc.ments c.ntein informetion
currant 8S of publicatian date. Products conform to
specifications per the terms Df TeXIS Instruments
:'~~~:~~i~air::I~~i ~!:~:~ti:r ~~O::::::t:~~S
DOt
~
TEXAS
INSTRUMENTS
POST OFfiCE BOX 655012 • DALLAS, TEXAS 75265
Ii: + B + C + 0
2·95
SN5420, SN54LS20, SN54S20,
SN7420, SN74LS20, SN74S20
DUAL 4·INPUT POSITIVE·NAND GATES
schematics (each gate)
'20
INPUTS
A
B
OUTPUT
y
e-HI--t
D-+-+-+-.
'S20
'LS20
Vee
Vee
20 kll
-I
-I
rC
CD
<
5·
B kll
2.B kll
120 Il
900 Il
50 Il
A
B
e
0
OUTPUT
y
B
OUTPUT
e
y
0
CD
fI)
Resistor values shown are nominal.
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: '20, 'S20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
'LS20 ................................. ~ ....................... 7 V
Operating free-air temperature range: SN54' . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
SN74' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70°C
Storage temperature range ......................................... -65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminals.
2-96
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN5420, SN7420
DUAL 4·INPUT POSITIVE·NAND GATES
recommended operating conditions
SN5420
SN7420
UNIT
Vee. Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
IOL
Low-level output current
TA
Operating free-air temperature
0.8
0.8
-0.4
-0.4
rnA
16
rnA
70
°e
16
- 55
V
V
2
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN5420
t
SN7420
UNIT
MIN
TVP*
2.4
3.4
MAX
MIN
TVP*
2.4
3.4
-1.5
MAX
- 1.5
V
0.4
V
VIK
Vee = MIN,
11=-12rnA
VOH
Vee = MIN,
VIL = 0.8 V,
IOH = - 0.4 rnA
VOL
Vee = MIN,
VIH=2V,
IOL=16rnA
II
Vee = MAX,
VI = 5.5 V
1
1
rnA
IIH
Vee = MAX,
VI = 2.4 V
40
40
/lA
IlL
Vee = MAX,
VI = 0.4 V
-1.6
-1.6
rnA
IOS§
Vee = MAX
- 55
rnA
leeH
Vee= MAX,
VI = 0 V
2
4
2
4
rnA
leeL
Vee = MAX,
VI = 4.5 V
6
11
6
11
rnA
TVP
MAX
12
22
ns
8
15
ns
0.2
- 20
t For conditions shown as MI N or MAX, use the appropriate
t All typical values are at Vee"" 5 V, T A = 25°C.
0.4
- 55
0.2
-18
V
..
ell
Q)
CJ
'S
Q)
C
...J
II-
value specified under recommended operating conditions.
§ Not more than one output should be shorted at a time.
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
FROM
TO
!INPUT)
(OUTPUT)
Any
Y
PARAMETER
TEST CONDITIONS
tpLH
RL=400n,
MIN
UNIT
eL = 15 pF
tpHL
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-97
SN54LS20. SN74LS20
DUAL 4·INPUT PDSITIVE·NAND GATES
recommended operating conditions
SN54lS20
SN74lS20
UNIT
Vee
Supply voltage
V,H
High-level input voltage
V,L
Low-level input voltage
IOH
High-level output current
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
IOL
Low-level output curre'nt
TA
Operating free-air temperature
V
V
2
0.7
0.8
-0.4
-0.4
mA
8
mA
70
°e
4
- 55
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LS20
t
-I
-I
SN74lS20
UNIT
MIN TYP*
MAX
MIN TYP*
-1.5
V,K
Vee = MIN,
1,=-18mA
VOH
Vee = MIN,
V,L = MAX,
'OH= -0.4mA
Vee=MIN,
V'H=2V,
10L =4mA
Vee· MIN,
V,H = 2V,
10L = 8 mA
2.5
3.4
0.25
MAX
-1.5
2.7
0.4
V
V
3.4
0.4
V
r-
VOL
C
I,
Vee= MAX,
V, = 7 V
0.1
0.1
rnA
I'H
Vee = MAX,
V, = 2.7 V
20
20
/lA
I,L
Vee = MAX,
V, =O.4V
-0.4
-0.4
mA
10S§
Vee= MAX
-100
mA
leeH
Vee = MAX,
V, =OV
0.4
0.8
0.4
0.8
mA
leel
Vee= MAX,
V,=4.5V
1.2
2.2
1.2
2.2
rnA
CD
<
(;'
CD
(I)
0.25
-100
-20
t For conditions shown as MIN or MAX, use the appropriate value specified
t All typical values are at Vee"" 5 v, T A "" 25°C.
- 20
0.5
under recommended operating conditions.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
FROM
TO
(INPUT}
(OUTPUT)
Any
V
PARAMETER
TEST CONDITIONS
tpLH
RL=2kfl,
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
TVP
MAX
9
15
n,
10
15
n,
UNIT
eL = 15 pF
tPHL
2-98
MIN
.Jf
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54S20. SN74S20
DUAL 4-INPUT POSITIVE-NAND GATES
recommended operating conditions
SN54S20
SN74S20
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
-1
-1
mA
20
20
mA
125
70
°e
2
IOL
Low-level output current
TA
Operating free-air temperature
- 55
V
V
2
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN54S20
t
SN74S20
UNIT
VIK
Vee = MIN,
11=-18mA
VOH
Vee = MIN,
VIL = 0.8 V,
IOH = -1 mA
VOL
Vee = MIN,
VIH=2V,
IOL=20mA
II
Vee = MAX,
IIH
MIN
TYP*
2.5
3.4
MAX
MIN
TVP*
2.7
3.4
MAX
-1.2
-1.2
V
V
V
0.5
0.5
VI = 5.5 V
1
1
mA
Vee = MAX,
VI = 2.7 V
50
50
jJ.A
IlL
Vee = MAX,
VI=0.5V
IOS§
Vee = MAX
leeH
Vee= MAX,
VI =0 V
leeL
Vee = MAX,
VI = 4.5 V
-2
-2
-40
-100
-40
en
Q)
(.)
mAo
'>
Q)
C
....I
-100
mA
5
8
5
8
mA
10
18
10
18
mA
tt-
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+ All typical values are at Vee'" 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5 V, T A = 25°e (see note 2)
FROM
TO
\INPUT)
(OUTPUT)
PARAMETER
TEST CONDITIONS
tPLH
RL=280n,
TYP
MAX
UNIT
3
4.5
ns
3
5
ns
eL = 15 pF
tpHL
A, B,e or D
MIN
Y
tpLH
RL=280n,
4.5
ns
5
ns
eL=50pF
tpHL
NOTE 2: Load circuits and voltage waveforrns are shown in Section 1.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-99
2-100
SN54LS21, SN74LS21
DUAL 4·INPUT POSITIVE·AND GATES
APRil 1985 - REVISED MARCH 1988
SN54LS2l ... J OR W PACKAGE
SN74LS2l •.. 0 OR N PACKAGE
• Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
ITOPVIEWI
1A
1B
NC
1C
10
1Y
GNO
• Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent 4-input
AND gates.
The SN54LS21 is characterized for operation
over the full military temperature range of
- 55°C to 125°C. The SN74LS21 is
characterized for operation from O°C to 70°C.
SN54LS2l ... FK PACKAGE
ITOP VIEWI
U
~ ~ ~ ~~
FUNCTION TABLE (each gatel
INPUTS
B
C
0
y
H
H
H
H
L
X
X
X
X
X
X
L
X
X
X
X
L
H
L
L
3 2
OUTPUT
A
X
X
VCC
20
2C
NC
2B
2A
2Y
II)
Q)
(,)
'S
910111213
L
Q)
C
L
...J
L
NC - No internal connection
lI-
logic symbol t
lA
lB
lC
10
2A
2B
2C
20
111
121
logic diagram
&
(61
141
1Y
l
lB A p - lY
lC
151
10
191
1101
(81
1121
2
A p - 2Y
2B
2C
2Y
1131
20
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
IEC Publication 617· 12.
Pin numbers shown are for D, J, N, and W packages.
PRODUCTION DATA dacumlnts .'.lIio iol.r_i••
•• rr••, •••1 publlcati•• dill. "OIIucto ...tor.. ,•
.,lICilicltio•• PI' ,be , ...... of T•••• I••
.,.m....
::=~i;.i~:I:r~ ~=::i~n :.~:::~~~ lot
(positive logic) Y = A.B.C.D or Y = A + B + C + D
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
2-101
SN54LS21, SN74LS21
DUAL 4·INPUT POSITIVE·AND GATES
schematics leach gate)
r-----~-----.~----------~--vcc
20k n
A
10kn
120n
8kn
---4.--+oIt---....
B --IH'--+4--~
C
-ii-f.....-t<......
D--IH-+.....~...---f
....
~~~~--------~-------4~----
~
~
r-
oCD
~--~--GND
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
- 55°C to 125°C
Operating free-air temperature range: SN54' . . . . . . . . . . . . . . . . . . . . . . . . . . "
SN74' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ooe to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
<
,:;"
CD
UI
NOTE 1: Voltage values are with respect to network ground terminals.
2-102
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54LS21, SN74LS21
DUAL 4·INPUT POSITIVE·AND GATES
recommended operating conditions
SN54LS21
SN74LS21
UNIT
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
2
2
V
IOH
High-level output current
-0.4
-0.4
mA
IOL
Low-level output current
4
8
mA
TA
Operating free-air temperature
70
°e
- 55
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LS21
t
SN74LS21
UNIT
MIN TYP*
VIK
Vee' MIN,
1I'-I~mA
VOH
Vee' MIN,
VIH' 2 V,
IOH' -0.4 mA
Vee' MIN,
VIL'MAX,
IOL' 4 mA
Vee' MIN,
Vll'MAX,
IOL'8mA
MAX
MIN TYP*
-1.5
2.5
3.4
0.25
MAX
- 1.5
2.7
0.4
3.4
V
V
0.25
0.4
0.35
0.5
V
VOL
II
Vee' MAX,
VI' 7 V
IIH
Vee' MAX,
VI'2.7V
III
Vee' MAX,
VI' 0.4 V
IOS§
Vee' MAX
leeH
Vee' MAX,
VI' 4.5 V
1.2
2.4
leel
Vee' MAX,
VI' OV
2.2
4.4
0.1
0.1
mA
20
20
!J.A
-0.4
- 20
-100
- 0.4
mA
-100
mA
1.2
2.4
mA
2.2
4.4
mA
- 20
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t: All typical values are at Vee = 5 V, T A = 2SoC
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, Vee
= 5 V, TA = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
Any
Y
PARAMETER
tplH
TEST CONDITIONS
Rl'2kn,
MIN
TYP
MAX
UNIT
8
15
ns
10
20
ns
e l ' 15 pF
tpHl
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-103
2-104
SN5422, SN54LS22, SN54S22,
SN7422, SN74LS22, SN74S22
DUAL 4·INPUT POSITIVE·NAND GATES WITH OPEN·COLLECTOR OUTPUTS
DECEMBER 19B3 - REVISED MARCH 1988
• Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
SN5422, SN54lS22, SN54S22 •.. J OR W PACKAGE
SN7422 ... N PACKAGE
SN74lS22, SN74S22 ... 0 OR N PACKAGE
(TOP VIEWI
• Dependable Texas Instruments Quality and
Reliability
1A
1B
NC
1C
description
10
These devices contain two independent 4-input
NAND gates. The open-collector outputs require
pull-up resistors to perform correctly. They may
be connected to other open-collector outputs to
implement active-low wired-OR or active-high
wired-AND functions. Open-collector devices are
often used to generate higher VOH levels.
1Y
GNO
SN54LS22. SN54S22 ... FK PACKAGE
(TOP VIEW)
U
aJ«U UO
The SN5422, SN54LS22 and SN54S22 are
characterized for operation over the full military
temperature range of - 55 °e to 125°e. The
SN7422, SN74LS22, and SN74S22 are
characterized for operation from ooe to 70 oe.
FUNCTION TABLE
INPUTS
A
B
C
~~z>'"
3
H
H
H
L
X
L
X
X
L
X
X
X
H
X
X
X
X
X
X
L
H
2C
NC
II)
7
NC
NC
"S
8
28
o
6
Q)
(.)
Q)
9 10111213
)- 0
Y
L
1 20 19
5
(each gatel
H
2
4
OUTPUT
0
VCC
20
2C
NC
2B
2A
2Y
U
...J
)-.«
lI-
~ZZ"''''
(!l
NC -- No internal connection
H
H
logic diagram
1~===3
logic symbol t
10
2A
lA
lB
lC
10
2A
2B
2C
20
(1)
~g===1
&
(2)
20
1Y
(41
positive logic
(51
-
-
Y - A·B·C·D or Y : A + B + C + D
(9)
(101
2Y
(121
(13)
t This symbol is in accordance with ANSI/IEEE Std 91 1984 and
IEC Publication 617 ·12.
Pin numbers shown are for D, J, N, and W packages.
PRODUCTION DATA documents contain information
current as of publication date. Praducts conform to
spacifications per the terms of TeXIS Instruments
::C-:!:~~i~a:::1~1i ~!::i~:i:f :ljI:::::~::'~S
not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-105
SN5422, SN54LS22, SN54S22,
SN1422, SN14LS22, SN14S22
DUAL 4·INPUT PDSITIVE·NAND GATES WITH OPEN·COLLECTOR OUTPUTS
schematics (each gate)
'LS22
'22
. - -.....---Vee
Vee
INPUTS
1.6 kO
8 kn
A
INPUTS
B
OUTPUT
A
y
e
B
e
17 kn
0
1 kO
0
GND
L-~~~----.----
-I
-I
r-
__
~-~--GND
'S22
Vee
C
~
<
n·
~
en
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply yoltage, Vee (See Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input yoltage: '22, 'S22 ............................................................ 5.5 V
'LS22 ................................................................. 7 V
Operating free-air temperature range: SN54' .................................... -55°e to 125°e
SN74' ....................................... 0° e to 70 0 e
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 °e to 150 0 e
NOTE 1: Voltage values are with respect to network ground terminal.
2-106
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5422, SN7422
DUAL 4·INPUT POSITIVE·NAND GATES WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN7422
SN5422
Vee
SUpply voltage
VIH
High~evel
VIL
Low·level input voltage
VOH
High~evel
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.6
5
5.5
4.75
5
5.25
input voltage
V
V
2
2
0.8
0.8
output voltage
5.5
5.5
V
IOL
Low-level output current
16
16
rnA
TA
Operating free-air temperature
70
°e
-55
125
0
V
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
VIK
IOH
VOL
SN5422
TEST CONDITIONSt
PARAMETER
Vee
Vee
Vee
= MIN.
= MIN.
= MIN.
Vee - MIN,
II
Vee
IIH
Vee
III
Vee
leeH
Vee
leel
Vee
= MAX,
= MAX,
= MAX,
= MAX,
= MAX,
II
=
MIN
TYP*
= 0.8 V.
Vil = 0.7 V.
VIH = 2 V,
VI = 5.5 V
VI = 2.4 V
VI = 0.4 V
VI = 0
VI = 4.5 V
MIN
TYP*
MAX
-1.5
-12mA
Vil
SN7422
MAX
= 5.5 V
VOH = 5.5 V
IOl = 16 rnA
-1.5
0.25
VOH
0.25
0.2
0.4
0.2
0.4
UNIT
V
rnA
II)
V
Q)
(J
'S
1
1
rnA
40
40
p.A
-1.6
-1.6
rnA
C
....I
2
4
2
4
rnA
6
11
6
11
rnA
Q)
~
~
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*AII typical values are at Vee = 5 V, TA = 25°e.
switching characteristics, Vee = 5 V, T A = 25°e (see note 2)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
-
tpLH
Any
tpHL
TEST CONDITIONS
y
MIN
TYP
MAX
UNIT
Rl-4kn,
CL
= 15pF
35
45
ns
RL =400n,
eL = 15 pF
8
15
ns
NOTE 2: load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS'75265
2-107
SN54LS22, SN74LS22
DUAL4-INPUT POSITIVE-NAND GATES WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN54LS22
SN74LS22
UNIT
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
VOH High-level output voltage
0.7
0.8
V
5.5
5.5
V
4
IOL
Low-level output current
TA
Operating free-air temperature
-55
V
V
2
125
0
8
mA
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS22
PARAMETER
UNIT
MIN
-t
-t
VIK
Vee = MIN.
11=-lamA
IOH
Vee= MIN.
Vil = MAX.
VOH = 5.5 V
Vee= MIN.
VIH = 2 V.
IOl =4'mA
Vee= MIN,
VIH = 2 V,
IOl =8mA
VOL
r-
SN74 LS22
TEST eONDITIONSt
TVP* MAX
0.25
MIN
TVP*
MAX
-1.5
- 1.5
0.1
0.1
0.4
0.25
0.4
0.35
0.5
V
mA
V
II
Vee = MAX,
VI = 7 V
0.1
0.1
<
IIH
Vee = MAX,
VI = 2.7 V
20
20
IlA
IlL
Vee= MAX,
VI=0.4V
-0.4
-0.4
mA
et)
leeH
Vee= MAX,
VI =0
0.4
0.8
0.4
0.8
mA
leel
Vee = MAX,
VI = 4.5 V
1.2
2.2
1.2
2.2
mA
C
et)
n'
C/I
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*All typical values are at Vee"" 5 V, T A :::: 2SoC.
switching characteristics, Vee
=5 V, TA = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
Any
V
PARAMETER
tPLH
TEST CONDITIONS
Rl=2kn,
NOTE 2: load circuits and voltage waveforms are shown in Section 1.
TEXAS
TVP
MAX
UNIT
17
32
ns
15
28
ns
eL = 15pF
tPHL
2-108
MIN
-If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54S22, SN74S22
DUAL 4-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN54S22
VCC
Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
SN74S22
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.8
0.8
VOH High-level output voltage
5.5
5.5
V
IOl
Low-level output current
20
20
mA
TA
Operating free-air temperature
70
°c
- 55
125
0
V
electrical characteristics over recommended operating free-air temperature range. (unless otherwise
noted)
VIK
IOH
SN54S22
TEST CONDITIONS t
PARAMETER
Vee = MIN.
II = -18 rnA
Vee = MIN,
Vil = 0.8 V,
MIN
TYP*
SN74S22
MAX
MIN
TYP*
-1.2
MAX
-1.2
0.25
VOH = 5.5 V
UNIT
V
rnA
Vee = MIN,
Vll=0.7V,
VOH = 5.5 V
0.25
VOL
Vee = MIN,
VIH = 2 V,
IOl = 20 rnA
0.5
0.5
II
Vee = MAX,
VI = 5.5 V
1
1
rnA
IIH
Vee = MAX,
VI = 2.7 V
50
50
~A
III
Vee = MAX,
VI = 0.5 V
leeH
Vee = MAX,
VI = 0
leel
Vee = MAX,
VI = 4.5 V
-2
V
-2
rnA
3
6.6
3
6.6
rnA
10
18
10
18
rnA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, TA = 25°e.
switching characteristics,
PARAMETEH
FROM
II NPUT)
Vee
=
5
V,
T A = 25
MIN
TEST CONDITIONS
RL - 280H.
Any
Q)
CJ
-S
Q)
C
...J
lI-
e (see note 2)
TO
(OUTPUT)
tpLH
tPHl
en
CL
tpLH
o·
280 H.
CL
MAX
2
5
7.5
os
2
4.5
7
ns
UNIT
15 rF
y
RL
TVP
7.5
ns
7
ns
50 pF
tpHL
NOTE 2: Load circuits and voltage waveforms are shown In Section 1
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-109
-t
-t
r-
C
~
~.
(')
~
Cfj
2-110
SN5423. SN5425. SN7423. SN7425
DUAL 4-INPUT NOR GATES WITH STROBE
DECEMBER 1983 - REVISED MARCH 1988
SN5423 ... J OR W PACKAGE
SN7423 ... N PACKAGE
•
Package Options Include Plastic and
Ceramic DIPs and Ceramic Flat Packages
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEWI
description
These devices contain dual 4-input positive NOR gates
with strobe. They perform the Boolean function:
Y = G(A+B+C+O)
(with 1 X and 1X of '23 left open).
(TOPVIEWI
1A
1B
1G
1C
10
1Y
GNO
FUNCTION TABLE
A
B
C
OUTPUT
D
G
V
X
H
X
X
H
L
X
H
X
X
H
L
X
X
.H
X
H
L
X
X
X
H
H
L
L
L
L
L
X
H
X
X
X
X
L
H
Expander inputs are open.
H = high level, L "" low level, X
1X
20
2C
2G
2B
2A
2Y
SN5425 ..• J OR W PACKAGE
SN7425 ... N PACKAGE
The SN5423 and the SN5425 are characterized for
operation over the full military temperature range of
- 55 DC to 125 DC. The SN7423 and the SN7425 are
characterized for operation from 0 DC to 70 DC.
INPUTS
V~C
1X
1A
1B
1G
1C
10
1Y
GNO
VCC
20
2C
2G
2B
2A
2Y
CI)
Q)
CJ
-S
Q)
C
......
logic diagram
..J
A
OUTPUT
V
c
= irrelevant
o
G -....' - - "
y
GATE 1 OF
SN5423/SN1423
ONLY
logic symbols t
SN5425/SN7425
SN5423/SN7423
1G 141
G,
;;'1
lG
,.
1A (2)
,.
lA
\3\
lC \51
10 \61
lX \11
lC
17\ lV
10
lX (15)
]-
2G 1121
G2
2G
2A
;'1
2.
2A \101
2C
28 (11)
20
\3\
G1
;;;'1
G2
~1
111
121
141
151
1111
191
\10\
1121
1131
\9\ 2V
2C (13)
20" 4 \
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and lEG Publication 617-12.
Pin numbers are for J. N, or W packages.
PRODUCTION DATA d••um.nts .0AlSi. information
currant as of pUblication dot•• Products ••nform to
.p••Hicallo•• par tba torms of T.... Instrumants
::::::;·{nr:I~'l~ ~=::i:; ~r:::::t!.~
nat
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-111
SN5423. SN5425.SN7423. SNSN7425
DUAL4-INPUT NOR GATES WITH STROBE
schematic (each gate)
Vcc----------.-~~----~--~
loon
A~--J
B~-I--J
o ......--t-..J
II.
..
~
or-
G -......-t+..,
:; ~ ~{~-----------~ ~ 0
t:I
x-------------
iii
Boon
GNO--------------~--~--~
NOTES: A.
B.
C.
D.
'Vi'-
Component values shown are nominal.
Both expander inputs are used simultaneously for expanding.
If expander is nOt used leave X and X open.
A total of four expander gates can be connected to the expander inputs.
VCC bus
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage VCC (see Note 1) ............................................................... 7 V
Input voltage (see Note 1) .................................................................... 5.5 V
Interemitter voltage (see Note 2) ............................................................... 5.5 V
Operating free-air temperature range: SN5423, SN5425 Circuits ............................ - 55°C to 125°C
SN7423, SN7425 Circuits .............................. " OoC to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
NOTES: 1. Voltage values, except int.remitter voltage, af. with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor.
recommended operating conditions
'23, '25
MIN
Vce
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
TA
MAX
54 Family
4.5
5
5.5
74 Family
4.75
5
5.25
0.8
-0.8
54 Family
16
74 Family
54 Family
74 Family
Operating free--air temperature range
.
TEXAS ~
INSTRUMENTS
POST OFfiCE BOX 655012 • DALLAS, TeXAS 75265
UNIT
V
V
2
The '23 is designed for use with up to four '60 expanders.
2-112
NOM
16
-55
125
0
70
V
mA
mA
'e
SN5423, SN5425, SN7423, SN7425
DUAL 4·INPUT NOR GATES WITH STROBE
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
TEST CONOITIONSt
VI
Vce = MIN,
11=-12mA
VOH
Vee - MIN,
VIL = 0.8 V,
IOH - - 0.8 mA
VOL
Vee - MIN,
VIH = 2 V,
IOL=16mA
Vee - MAX,
VI = 5.5 V
Vee = MAX,
VI = 2.4 V
Vee = MAX,
VI=O.4V
II
data inputs
IIH
strobe inputs
data inputs
IlL
strobe inputs
MIN
TVP* MAX
2.4
V
0.4
V
3.4
0.2
V
1
40
160
-1.6
- 6.4
I
54 Family
- 20
74 Family
-18
UNIT
- 1.5
mA
jlA
mA
- 55
IOS§
Vee = MAX
leeH
Vee = MAX,
All inputs at 0 V
8
16
rnA
leeL
Vee = MAX,
All inputs at 5 V
10
19
mA
I
- 55
rnA
t
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type. Expander inputs X and X are open.
t
All typical values are at
Vee::
5 V, T A
= 2SoC.
§ Not more than one output should be shorted at a time,
electrical characteristics (SN5423 circuits) using expander inputs, Vee = 4,5 V, T A = - 55°e
PARAMETER
TEST CONDITIONS
MIN
VXX = 0.4 V,
IOL = 16 mA
Base·Emitter voltage of output
transistor (0)
IOL = 16 mA,
IX + IX = 0.41 mA,
RXX=O
VOH
High-level output voltage
IOH = - 0.4 mA,
IX =0.15mA,
IX = - 0.15 mA
VOL
Low-level output voltage
IOL = 16 rnA,
I X + I X - 0.3 mA,
RXX=114n
IX
Expander current
VSE(Q)
TVPt
2.4
MAX
UNIT
- 3.5
mA
1.1
V
0.4
V
3.4
0.2
V
electrical characteristics (SN7423 circuits) using expander inputs, Vee = 4,75 V, TA = ooe
PARAMETER
MIN
TEST CONDITIONS
Expander current
Base-Emitter voltage of output
transistor (a)
VXX = 0.4 V,
IOL = 16 mA
IOL = 16 rnA,
Ix + IX= 0.62 mA,
RXX=O
VOH
High-level output voltage
IOH = - 0.4 rnA,
IX = 0.27 mA,
IX = -0.27 rnA
VOL
Low-level output voltage
IOL=16mA,
IX + IX - 0.43 mA,
RXX' 130 n
IX
VSE(Q)
2.4
TVPt
MAX
UNIT
- 3.8
rnA
1
V
0.4
V
3.4
0.2
V
t All typical values are at Vce "" 5 V. T A = 25" c_
switching characteristics, Vee = 5 V, TA = 25°e, N= 10, (see note 3)
TVP
MAX
eL = 15pF
13
22
eL = 15 pF
8
15
TEST CONDITIONS
RL -400n,
MIN
NOTE 3: Switching characteristics of the SN5423 and SN7424 are tested with the expander pins open.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 65501 Z
• DALLAS. TEXAS 75265
2-113
-I
-I
r
oen
<
(")
en
(II
2-114
SN5426, SN54LS26, SN7426, SN74LS26
QUADRUPLE 2·INPUT
HIGH·VDLTAGE INTERFACE POSITIVE·NAND GATES
DECEMBER 1983-REVISED MARCH 1988
SN5426 ... J PACKAGE
SN54LS26 •.. J OR W PACKAGE
SN7426 ... N PACKAGE
SN74LS26 ... 0 OR N PACKAGE
• For Driving Low·Threshold·Voltage
MOS Inputs
(TOP VIEW)
Vee
18
lY
2A
28
2Y
GND
description
These 2-input open-collector NAND gates feature
high-output voltage ratings for interfacing with lowthreshold-voltage MOS logic circuits or other 12-volt
systems. Although the output is rated to withstand 15
volts, the Vee terminal is connected to the standard
5-volt source.
48
4A
4Y
38
3A
3Y
SN54LS26 ... FK PACKAGE
(TOP VIEW)
The SN5426 and SN54LS26 are characterized for operation over the full military temperature range of
- 55°C to 125°C. The SN7426 and SN74LS26 are
characterized for operation from ooe to 70°C.
U
e:! ~ ~ ~~
3 2 1 2019
4
5
6
logic diagram
l A - - - r -....
1B
~lY
2A
---r-'\..._ 2Y
7
8
9 10111213
2B~
>cu><
.... ZZI'lI'l
CI
: : _ _....._ } - - 3Y
NC - No Internal connection
::
}--4Y
positive logic
Y= AB
logic symbol t
1A
18
2A
28
3A
38
4A
48
I This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
PRODUCTION DATA d......nts •••tei. iotarmltia.
••,,,•••• of publicatio....... "adu......Iorm ••
• poeill•••io•• per .he terms .1 T••u 1.II,.men"
::=~i~'ir,::Je ~.:::I:~i:,. ~=;:.:~~. n..
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-115
SN5426. SN54LS26. SNSN7426. SN74LS26
QUADRUPLE 2·INPUT
HIGH:VOLTAGEINTERFACE POSITIVE-NAND GATES
schematics
'26
'LS26
~----<...----Vcc
4kn
r-----e~-----vcc
1.Skn
17kn
8kn
INPUTS
INPUTS
A
OUTPUT
Y
B--I--.
A -......- - - I 4 -......-.t.....-t
B --+-~"-i4-"'"
1kn
L--~----.-~--~-GNO
L--~------<
-I
-I
rC
__-4~--4~--GNO
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) .............................................................. 7 V
Input voltage: '26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
'LS26 ......................................................................... 7 V
Operating free·air temperature: SN54' ................................................. - 55°C to 125°C
SN74' .................................................... oOe to 70°C
Storage temperature range. . . . . . . . . . . . . . . . .
. .................................. - 65°C to 150°C
CD
<
n"
CD
VI
NOTE 1:
2-116
Voltage values are with respect to network ground terminal.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS26, SN74LS26
QUADRUPLE 2·INPUT
HIGH·VOLTAGE INTERFACE POSITIVE·NAND GATES
recommended operating conditions
SN54lS26
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
SN74lS26
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
UNIT
V
V
2
0.7
0.8
VOH High-level output voltage
15
15
V
IOl
Low-level output current
4
8
rnA
TA
Operating free-air temperature
70
°e
-55
125
0
V
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
VIK
IOH
VOL
SN54lS26
TEST eONDITIONst
MIN
Vee = MIN,
11=-18rnA
Vee= MIN,
Vil = MAX,
VOH=12V
Vee = MIN,
Vil = MAX,
VOH=15V
Vee = MIN,
VIH = 2 V,
IOl =4rnA
Vee= MIN,
VIH=2V,
IOl = 8 rnA
TYP*
SN74lS26
MAX
MIN
TYP*
- 1.5
50
50
1
0.25
MAX
-1.5
1
0.4
0.25
0.4
0.35
0.5
UNIT
V
IlA
rnA
V
II
Vee = MAX,
VI = 7 V
0,1
0.1
IIH
Vee= MAX,
VIH=2.7V
20
20
IlA
III
Vee= MAX,
Vll=O.4V
- 0.4
- 0.4
mA
leeH
lice = MAX,
VI =0
0.8
1.6
0.8
1.6
rnA
leel
Vee = MAX,
VI=4.5V
2.4
4.4
2.4
4.4
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t: All typical values are at Vee"" 5 V, T A"" 25°C.
.
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
PARAMETER
tPLH
FROM
TO
(INPUT)
(OUTPUT)
A or 8
Y
TEST CONDITIONS
Rl=2kn,
tPHl
el = 15 pF
MIN
TYP
MAX
17
32
15
28
UNIT
ns
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-117
SN5426, SN7426
QUADRUPLE 2·INPUT
HIGH·VOLTAGE INTERFACE POSITIVE·NAND GATES
recommended operating conditions
SN5426
MIN
4,5
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VOH High-level output voltage
IOL Low-level output current
Operating free-air temperature
TA
NOM
5
SN7426
MAX
5,5
MIN
4,75
MAX,
NOM
5
V
0.8
0.8
V
15
15
V
16
16
rnA
70
"C
2
V
2
- 55
UNIT
5.25
a
125
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER
VIK
Vee
Vee
IOH
Vee
Vee
Vee
~
~
VOL
Vee
r-
II
Vee
C
IIH
Vee
(1)
IlL
Vee
n'
leeH
Vee
leel
Vee
<
(1)
(I)
SN5426
TEST CONDITIONSt
=
=
=
=
=
=
=
=
=
=
=
=
MIN,
II
MIN,
Vll
MIN,
MIN,
MIN,
MIN,
MAX,
MAX,
MAX,
MAX,
MAX,
MIN
TYP*
MIN
TYP*
- 1.5
-12 rnA
= 0.8 V,
Vll = 0.7 V,
Vll = 0.8 V,
Vll = 0.7 V,
VIH = 2 V,
VI = 5.5 V
VI = 2.4 V
VI = 0.4 V
VI = 0
VI = 4.5 V
SN7426
MAX
= 12 V
VOH = 12V
VOH = 15 V
VOH = 15 V
10l = 16 rnA
MAX
- 1.5
50
VOH
50
1
1
0.4
0.4
1
1
UNIT
V
~A
rnA
V
rnA
40
40
~A
-1.6
-1.6
rnA
4
8
4
8
rnA
12
22
12
22
rnA
TYP
MAX
UNIT
16
24
ns
11
17
ns
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, TA = 25°e,
switching characteristics, Vee = 5 V, T A = 25°e (see note 2)
PARAMETER
tPLH
tpHL
FROM
TO
(INPUT)
(OUTPUT)
A or 8
y
TEST CONDITIONS
RL " 1 kl!,
CL
0
MIN
15 pF
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2-118
, TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5427, SN54LS27, SN7427, SN74LS27
TRIPLE 3·INPUT POSITIVE·NOR GATES
DECEMBER 1983- REVISED MARCH 1988
• Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers
and Flat Packages. and Plastic and Ceramic
DIPs
SN5427. SN54LS27 ... J OR W PACKAGE
SN7427 ... N PACKAGE
SN74LS27 ... 0 OR N PACKAGE
(TOP VIEW)
1A
18
2A
28
2C
2Y
GND
• Dependable Texas Instruments Quality and
Reliability
description
These devices contain three independent 3·input NOR
gates.
The SN5427 and SN54LS27 are characterized for operation over the full military temperature range of
- 55°C to 125°C. The SN7427 and SN74LS27 are
characterized for operation from ooC to 70°C.
SN54LS27 ... FK PACKAGE
(TOP VIEW)
FUNCTION TABLE (each gate)
INPUTS
A
B
H
X
X
X
L
H
X
L
CO <{ U
u
Uu
~~Z>~
3
OUTPUT
C
VCC
1C
1Y
3C
38
3A
3Y
2
1 2019
1Y
NC
3C
NC
38
4
Y
5
X
X
H
L
L
L
L
H
6
7
8
9 10111213
>-OU>-<{
NZZMM
(!l
logic symbol t
lA
lB
lC
2A
2B
2C
3A
3B
3C
(1)
NC - No internal connection
~1
(2)
logic diagram
(13)
(3)
(4)
IF==[>-lY
2Y
(5)
~~----=D-2Y
(9)
(10)
3Y
(11)
t This symbol is in accordance with ANSI/IEEE Std 91 1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
positive logic
Y
PRODUCTION DATA do.umonls .onlain informalio.
turrant 8S of publication data. Products conform to
spacifi••lions par Iho lorms of ro••• Inslrumonls
:~~~~:~~i~·{:~1~1~ ~:~:~Ii:; :1;";::::::I:~~s nol
~
A
+
8
+
C or Y
~
A • 8 • C
..
j
TEXAS
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
2-119
SN5427, SN54LS27, SN7427, SN74LS27
TRIPLE 3·INPUT POSITIVE·NOR GATES
schematics (each gatel
'27
Vee
INPUTS
A
OUTPUT
y
B
e
1 kU
GND
-t
-t
'LS27
r-
Vee
C
SkU
20kU
120U
V
CD
<
INPUTS
c5'
CD
A
til
10kU
OUTPUT
y
B
Resistor values shown are nominal.
~~4-------------~------~----~-----GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................... : ............................... 7 V
Input voltage: '27 ..................................... : ................................... 5.5 V
'LS27 ......................................................................... 7 V
Operating free-air temperature: SN54' ........ _ . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. _55°e to 125°C
SN74' ................... _................................ oOe to 700 e
Storage temperature range .............................................. _ . . . . . . . . . .. -65°e to 1500 e
NOTE 1: Voltage values are with respect to network ground te",minal.
2-120
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5427, SN7427
TRIPLE 3·INPUT POSITIVE·NOR GATES
recommended operating conditions
SN5427
SN7427
UNIT
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
0.8
0.8
-0.8
-0.8
16
- 55
125
V
V
2
0
V
mA
16
mA
70
De
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN,
SN5427
t
MIN TYP t
SN7427
MAX
MIN
TYPt
2.4
3.4
-1.5
11"-12mA
VIK
vee
VOH
Vee" MIN,
VIL"O,8V,
IOH" -0.8 mA
VOL
Vee" MIN,
VIH"2V,
IOL" 16 mA
II
Vee
~
MAX,
VI" 5,5 V
1
IIH
Vee" MAX,
VI" 2.4 V
40
VI"O.4V
2.4
3.4
UNIT
MAX
-1.5
V
0.4
V
Q)
1
mA
.~
40
J.lA
-1.6
mA
- 55
mA
V
If)
0.2
0.4
0.2
-1.6
IlL
Vee" MAX,
IOS§
Vee" MAX
leeH
Vee" MAX,
VI" OV
10
16
10
16
mA
leeL
Vee" MAX,
See Note 2
16
26
16
26
mA
- 20
- 55
-18
>
Q)
C
....I
lI-
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee 5 V, T A ,,- 25°C.
§ Not more than one output should be shorted at a time.
NOTE 2: One input at 4.5 V,all others at GND.
switching characteristics,
PARAMETER
tPLH
Vee = 5 V, T A = 25 e (see note 3)
D
FROM
(INPUT)
TO
(OUTPUT)
A, B or e
y
TEST CONDITIONS
RL "400n,
MIN
TYP
MAX
10
15
ns
7
11
ns
eL"15pF
tpHL
UNIT
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
-1!1
TEXAS
INSTRUMENTS
POST OFF'ICE BOX 655012 • DALLAS, TEXAS 75265
2-121
SN54LS27, SN74LS27
TRIPLE 3·INPUTPOSITIVE·NOR GATES
recommended operating conditions
SN54LS27
VCC SupplV 1IOI'8ge
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
TA
O~rating
SN74LS27
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
2
-55
0.8
-0.4
-0.4
125
V
V
0.7
4
free.oair temperature
UNIT
8
70
0
V
mA
mA
°c
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
-t
-t
r-
<
ci)"
C'D
(II
~
MIN,
SN74LS27
SN54LS27
t
MIN TYP*
MAX
MIN
TYP *
2.7
3.4
MAX
-1.5
11:-18mA
VIK
Vcc
VOH
Vcc :MIN,
VIL: MAX,
IOH: - 0.4 mA
VCC: MIN,
VIH :2V,
IOL:4mA
VCC :MIN,
VIH:2V,
IOL =8 mA
VOL
o
C'D
TEST CONDITIONS
2.5
3.4
0.25
-1.5
0.4
UNIT
V
V
0.25
0.4
0.35
0.5
V
mA
II
VCC = MAX,
VI = 7 V
0.1
0.1
IIH
VCC =MAX,
VI = 2.7 V
20
20
/'A
IlL
VCC =MAX,
VI :0.4V
- 0.4
- 0.4
mA
IOS§
VCC = MAX
-100
mA
ICCH
VCC :MAX,
VI = OV
ICCL
Vcc: MAX,
See Note 2
-100
- 20
-20
2
4
2
4
mA
3.4
6.8
3.4
6.8
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t:
All typical values are at Vee"" 5 V, T A = 2SoC.
§ Not more than ons output should be shorted at a time, and the duration of the short·circuit should not exceed One second.
NOTE 2: One input at 4.5 V, all others at GND.
switching characteristics, Vee = 5 V, TA = 25°e (see note 3)
PARAMETER
tpLH
FROM
(INPUT)
A, BorC
TO
(OUTPUT)
y
TEST CONDITIONS
RL:2kO,
TYP
MAX
UNIT
10
15
ns
10
15
ns
CL:15pF
tpHL
NOTE 3: Load circuits and voltage waveforms are shown in Section 1,
2·122
MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5428, SN54LS28, SN742l SN74LS28
QUADRUPLE 2·INPUT POSITIVE·NOR BUFFERS
DECEMBER 1983
• Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
SN5428, SN54LS28 ... J OR W PACKAGE
SN7428 ... N PACKAGE
SN74LS28 ... 0 OR N PACKAGE
(TOP VIEW)
1Y
1A
18
2Y
2A
28
GND
• Dependable Texas Instruments Quality and
Reliability
description
These devices contain four independent 2-input NOR
buffer gates.
The SN5428, and SN54LS28 are characterized for
operation over the full military temperature range of
-55°C to 125"C. The SN7428, and SN74LS28 are
characterized for operation from O°C to 70"C.
FUNCTION TABLE
VCC
4Y
48
4A
3Y
38
3A
SN54LS28 ... FK PACKAGE
(TOP VIEW)
(each gate)
3
INPUTS
A
B
OUTPUT
18
4
Y
NC
2Y
NC
2A
5
X
X
H
L
L
L
H
H
REVISED MARCH 1988
L
2
2019
48
NC
4A
NC
3Y
6
7
8
9 10 111213
aJou«aJ
NZZMM
positive logic
t:1
Cf)
Q)
tJ
oS
Q)
C
..oJ
lI-
NC - No internal connection
logic diagram
logic symbol t
lA
lB
2A
2B
3A
3B
4A
4B
(21
~~,~1y
;;>11>
: : ______ __
(31
(51
~~,~2Y
(61
: : ______ __
(81
:: ______
~~~,~3Y
: : ______
~~~~~4Y
(9)
(11)
(12)
t This symbol is in accordance wi1h ANSI/IEEE Std 91 1984 and
lEe Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
PRODUCTION DATA documents contain information
current as of publication date. Products conform 10
specifications par the terms of Texas Instruments
~~~~~:~~i~ai~:1~1e ~!:~~~ti:r :'IO::~:~:t::'s~ not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-123
SN5428, SN54LS28, SN7428, SN74LS28
QUADRUPLE 2·INPUT POSITIVE·NORBUffERS
schematics (each gate)
'28
r -....~......... -........................~.--vcc
4kn
4kn
600n
30n
-t
-t
r'LS28
C
.-................-..................... ....-.--vcc
CD
~
<
v
n'
CD
INPUTS
en
A~'---"
_ _ _...:O:.:U~UT
B-4-~~
L--4--........................~........~~........~........-GND
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage: '28 ........................................................................ 5.5 V
'LS28 ................................... ; .................................... 7 V
Operating free-air temperature: SN54' ................................................. _55°C to 125°C
SN74' .................................................... oOe to 70°C
Storage temperature range .......................................................... _65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
2·124
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN5428, SN7428
QUADRUPLE 2·INPUT POSITIVE·NOR BUFFERS
recommended operating conditions
SN5428
SN7428
UNIT
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
0.8
0.8
-2.4
-2.4
rnA
48
mA
70
°e
48
IOL
Low-level output current
TA
Operating free-air temperature
V
V
2
- 55
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Vee: MIN,
II: -12mA
t
MIN
TYP* MAX
-1.5
VOH
Vee: MIN,
VIL: 0.8 V,
IOH:-2.4mA
VOL
Vee: MIN,
VIH:2V,
IOL: 48 mA
II
Vee: MAX,
VI: 5.5 V
2.4
V
V
3.4
0.2
UNIT
0.4
1
V
rnA
IIH
Vee: MAX,
VI:2.4V
40
"A
IlL
Vee: MAX,
VI:0.4V
-1.6
mA
IOS§
Vee: MAX
-180
mA
leeH
Vee: MAX,
VI :OV
12
21
mA
leeL
Vee: MAX,
See Note 2
33
57
mA
-70
t
For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vee = 5 V. T A = 2SoC.
§ Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second.
NOTE 2: One input at 4.5 V, all others at GNO.
*
switching characteristics, Vee = 5 V, TA = 25°e (see note 3)
FROM
TO
(INPUT)
(OUTPUT)
TEST CONDITIONS
PARAMETER
tpLH
RL:133!l,
CL: 50 pF
tpHL
Aor 8
tPLH
MIN
TVP
MAX
6
9
ns
8
12
ns
10
15
ns
12
18
ns
V
RL:133!l,
UNIT
CL: 150pF
tpHL
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS. TEXAS 75265
2-125
SN54LS28, SN74LS28
QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS
recommended operating conditions
SN54lS28
SN74lS28
UNIT
MIN
NOM
MAX
,MIN
NOM
MAX
4,5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
VCC
Supply voltage
V,H
High·level input voltage
V,l
Low-level input voltage
IOH
High-level output current
-1.2
-1.2
mA
IOl
Low-level output current
12
24
mA
TA
Operating free-air temperature
70
°c
2
V
2
- 55
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
PARAMETER
-t
-t
SN54lS28
t
SN74lS28
UNIT
MIN
TVP*
2.5
3.4
MAX
MIN
TVP*
2,7
3.4
-1.5
V,K
VCC = MIN,
I, = - 18 mA
VOH
VCC = MIN,
V,l = MAX,
IOH=-1.2mA
VCC = MIN,
V'H=2V,
IOL = 12mA
VCC = MIN,
V,H = 2V,
IOL = 24 mA
0.25
-1.5
0.4
oCD
CD
til
t
V
0.24
0.4
0.35
0.5
mA
VCC = MAX,
V, = 7 V
0.1
0.1
I'H
VCC = MAX,
V,=2.7V
20
20
IlA
'lL
VCC = MAX,
V,=O.4V
-0.4
- 0.4
mA
"
<
c:;-
V
V
VOL
r-
MAX
IOS§
VCC = MAX
ICCH
VCC= MAX,
ICCl
VCC
MAX,
-130
mA
V, = 0 V
1.8
3.6
1.8
3.6
mA
See Note 2
6.9
13.8
6.9
13.8
mA
TVP
MAX
UNIT
12
24
ns
12
24
ns
-130
- 30
-30
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions,
t: All typical val ues are at Vee:=' 5 V, T A :=. 25°C.
§ Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second.
NOTE 2: One input at 4.5 V, all others at GND.
switching characteristics, Vee = 5 V, TA = 25°e (see note 3)
FROM
TO
(INPUT)
IOUTPUT)
A or B
V
TEST CONDITIONS
PARAMETER
tPLH
RL =667.11,
CL = 45 pF
tpHL
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-126
MIN
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN543D. SN54LS3D. SN54S30.
SN7430. SN74LS30. SN74S30
a-INPUT POSITIVE-NAND GATES
DECEMBER 1983 - REVISED MARCH 19BB
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN5430 ... J PACKAGE
SN54lS30. SN54S30 ... J OR W PACKAGE
SN7430 ... N PACKAGE
SN74lS30. SN74S30 ... 0 OR N PACKAGE
(TOP VIEW)
A
B
C
D
E
F
GND
description
These devices contain a single B-input NAND gate.
The SN5430, SN54LS30, and SN54S30 are
characterized for operation over the full military range
of - 55 DC to 125 DC. The SN7430, SN74LS30, and
SN74S30 are characterized for operation from 0 DC
to 70 D e.
SN5430 ... W PACKAGE
(TOP VIEW)
OUTPUT
V
All inputs H
L
One or more inputs L
H
NC
NC
Y
GND
H
G
F
NC
A
B
VCC
C
D
E
FUNCTION TABLE
INPUTS A THRU H
VCC
NC
H
G
NC
NC
Y
en
Q)
CJ
'S;
Q)
C
SN54LS30, SN54S30 ... FK PACKAGE
logiC diagram
m
«
..J
lI-
(TOP VIEW)
u
u uu
Z>Z
3 2 1 2019
C
NC
H
NC
4
5
D
6
NC
7
NC
NC
8
9 10111213
positive logic
u.
Y=A·B·e·D·E·F·G·H
or
Ou >- u
Z
ZZ
t!l
Y=A+B+C+D+E+F+G+H
NC - No internal connection
logic symbol t
A
III
&
121
III
0
141
181
151
v
(61
(11)
G
1121
tThis symbol is in accordance with ANSI/IEEE Std 91·1984
and lEe Publication 617-12.
Pin numbers shown are for Q, J, N, and W packages.
PRODUCTION DATA documonts contain information
current 88 of publication data. Products conform to
specifications par the tarms of Texas Instruments
:'::=i~ai~:I~~i ~!:~:~ti:; :'IO::;:::::t:~~ not
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-127
SN5430, SN54LS30, SN54S30,
SN7430, SN74LS30, SN74S30
8·INPUT POSITIVE·NAND GATES
schematics (each gate)
'30
INPUTS
A
y
B
c--+--1~
D-+-Hrl
G-+-HH-+-+...
H-++-HH-++..
1 k!!
'LS30
r----<_---....-vcc
-t
-t
INPUTS
C
c
<
D
A
r-
m
Cr
m
en
G
H
'S30
r---~-------<_vcc
900Q
50Q
INPUTS
A
y
c-+-H
D-+-t-t......
G-+-+-H-+-+.....
H-++-+-H-+-+.....
Reststor values shown are nominal.
2·128
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5430. SN7430
a·INPUT POSITIVE·NAND GATES
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage. Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN5430... . . . . . . . . . . . . . . . . . . . . . . .. - 55 DC to 125 DC
SN7430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ooe to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 DC to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN7430
SN5430
UNIT
vee
Supply voltage
VIH
High-level input voltage
VIL
Low·level input voltage
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
2
V
2
IOH
High-level output current
-0.4
-0.4
mA
IOL
Low-level output current
16
16
mA
TA
Operating free-air temperature
70
DC
CI)
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
'S;
125
- 55
0
CI)
CJ
CI)
SN7430
SN5430
TEST CONDITIONS t
PARAMETER
UNIT
MIN
TYP*
MAX
MIN
TYP*
- 1.5
VIK
Vee = MIN.
11=- 12 mA
VOH
Vee = MIN,
VIL = 0.8 V,
IOH = - 0.4 mA
VOL
Vee = MIN,
VIH=2V,
IOL = 16mA
II
Vee = MAX,
VI=5.5V
2.4
3.4
0.2
MAX
-1.5
2.4
0.4
V
3.4
0.2
0.4
1
1
V
Vee = MAX,
VI = 2.4 V
40
40
/lA
Vee = MAX,
VI = 0.4 V
-1.6
-1.6
mA
IOS§
Vee = MAX
-55
mA
leeH
Vee = MAX,
VI = 0
1
2
1
2
mA
leeL
Vee = MAX,
VI = 4.5 V
3
6
3
6
mA
TYP
MAX
13
22
ns
8
15
ns
t For conditions shown as MIN or MAX, use the appropriate
t All typical values are at Vee'" 5 V. T A = 25°C.
-18
~
V
IIH
- 55
...I
~
mA
IlL
- 20
C
value specified under recommended operating conditions.
§ Not more than one output should be shorted at a time.
switching characteristics, Vee = 5 V, T A = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
Any
Y
TEST CONDITIONS
PARAMETER
tPLH
RL =400n,
MIN
eL = 15 pF
tpHL
UNIT
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-129
SN54LS30, SN74LS30
a-INPUT POSITIVE-NAND GATES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage .............................................................. 7 V
Operating free-air temperature range: SN54LS30......... . . . . . . . . . . . . . . .. - 55 °e to 125 °e
SN74LS30 ............................ ooe to 70 0 e
Storage temperature range .................... ,.................... - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LSJD
SN74LSJD
UNIT
-I
-I
r-
o
Vee
Supply voltage
V,H
High-level input voltage
V'L
Low-level input voltage
IOH
High-level output current
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
IOL
low-level output current
TA
Operating free-air temperature
V
V
2
0.7
0.8
-0.4
-0.4
mA
8
mA
70
°e
4
- 55
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
(1).
PARAMETER
~.
TEST CONDITIONS
SN54LSJD
t
SN74LSJO
UNIT
MIN
TVP*
2.5
3.4
MAX
MIN TVP*
MAX
(')
(1)
fJl
-1.5
V,K
VeC = MIN,
" = - 18 mA
vOH
Vee = MIN,
V'L = MAX,
'OH = - 0.4 rnA
Vec = MIN,
V'H = 2 V,
IOl = 4 mA
Vee = MIN,
V'H=2V,
IOl = 8 rnA
0.25
- 1.5
2.7
3.4
V
V
0.4
0.4
V
VOL
0.25
0.5
Vee = MAX,
V, = 7 V
0.1
0.1
'IH
Vec = MAX,
V,=2.7V
20
20
I'A
'Il
Vee = MAX,
V, =O.4V
- 0.4
- 0.4
mA
IOS§
Vee = MAX
leCH
Vee = MAX,
V, = 0
leCl
Vee = MAX,
V,=4.5V
"
-100
-100
mA
0.35
0.5
0.35
0.5
mA
0.6
1.1
0.6
1.1
mA
- 20
- 20
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee = 5 V. T A:: 25°C
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching charaGteristics, Vee = 5 V, T A = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
Any
Y
PARAMETER
tPlH
TEST CONDITIONS
Rl = 2kll,
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
.
TYP
MAX
UN'T
8
15
ns
13
20
ns
Cl = 15 pF
tpHl
2-130
M'N
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
SN54S30, SN74S30
8·INPUT POSITIVE·NAND GATES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage ............................................................. 5.5 V
Operating free-air temperature range: SN54S30 ......................... - 55°C to 125°e
SN74S30 ............................. ooe to 70 0 e
- 65°C to 150 0 e
Storage temperature range .......................................
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN74S30
SN54S30
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
-1
-1
mA
20
mA
70
°e
2
V
2
20
IOL
Low-level output current
TA
Operating free-air temperature
125
- 55
0
CI)
CI)
(,)
oS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN54S30
t
MIN
t
t
TYP*
CI)
SN74S30
MAX
MIN
TYP*
UNIT
MAX
Vee = MIN,
11=-18mA
VOH
Vee = MIN,
VIL = 0.8 V,
IOH = -1 mA
VOL
Vee = MIN,
VIH=2V,
IOL =20mA
II
Vee = MAX,
VI = 5.5 V
IIH
Vee = MAX,
VI=2.7V
50
50
JJ.A
IlL
Vee = MAX,
VI=0.5V
-2
-2
mA
-100
mA
IOS§
Vee=MAX
leeH
Vee = MAX,
VI = 0
leeL
Vee = MAX,
VI = 4.5 V
-1.2
...I
vlK
-1.2
2.5
3.4
-40
2.7
3.4
0.5
1
1
-100
-40
lI-
V
V
0.5
C
V
mA
3
5
3
5
mA
5.5
10
5.5
10
mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vee = 5 V. T A=- 2SoC.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5 V, T A = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
PARAMETER
TEST CONDITIONS
tpLH
RL = 280 n,
TYP
MAX
4'
6
4.5
7
UNIT
ns
eL = 15pF
tpHL
Any
MIN
ns
y
tpLH
RL = 280n,
5.5
ns
6.5
ns
eL = 50 pF
tp'HL
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-131
~
~
rC
CD
crCD<
III
2·132
SN54LS31. SN74LS31
DELAY ELEMENTS
DECEMBER 1983-REVISED MARCH 1988
• Delay Elements for Generating Delay
Lines
SN54LS31 ... J OR W PACKAGE
SN74LS31 ... 0 OR N PACKAGE
(TOP VIEWI
• Inverting and Non-inverting Elements
1A
1V
2A
2Y
• Buffer NAND Elements Rated at
IOl of 12/24 rnA
• PNP Inputs Reduce Fan-In
IIll= -0.2 rnA MAXI
• Worst Case MINIMAX Delays Guaranteed
Across Temperature and Vce Ranges
Vee
6A
6Y
5A
5Y
4B
4A
4Y
3Y
GND
description
These •LS31 delay elements are intended to provide
well·defined delays across both temperature and Vee
ranges. Used in cascade, a limitless range of delay
gating is possible.
SN54LS31 ... FK PACKAGE
(TOP VIEW)
All inputs are PNP with IlL MAX of - 0.2 mAo Gates
1, 2, 5, and 6 have standard Low-Power Schottky
output sink current capability of 4 and 8 mA IOL.
Buffers 3 and 4 are rated at 12 and 24 mAo
3 2
I 20 19
en
Q)
(.)
":;
Q)
The SN54 LS31 is characterized for operation over the
full military temperature range of - 55 °e to 125°e.
The SN74LS31 is characterized for operation from
Doe to 70 oe.
C
-'
lINC - No internal connection
logic symbol t
lA
2A
3A
38
(1)
(3)
(5)
23 ns
32 ns
I
I
45 ns
48 ns
6 ns
6 ns
I
I
)
&1>
(6)
I
2V
3V
6 ns
6ns
4A (10)
I
lV
&1>
I
48 (11)
45 ns
SA (13)
I
23 ns
6A (15)
I
tThis symbol is in accordance wilh ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
PRODUCTION DATA d••umont. contain information
currant 81 of public.tiaR data. Products conform to
spacifications plr the terms of TeXIS Instruments
:!:::~~i~8i~:I~'8 ~!::::i:; :'~O::;:~:'::'s~ not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-133
SN54LS31, SN74LS31
DELAY ELEMENTS
Delay Element
Typical Delays
Logic
tPLH
tpHL
Gates 1 and 6
Inverting
32 ns
23 ns
27.5 ns
Gates 2 and 5
Non·lnverting
45 ns
48 ns
46.5 ns
Buffers 3 and 4
2-lnput NANO
6 ns
6 ns
6 ns
VCC------
(each gate)
OUTPUT
B
VCC
4B
4A
4Y
3B
logic symbol t
lA
18
2A
2B
3A
3B
4A
4B
(1)
;'1
(2)
NC - No internal connection
(3) lY
logic diagram
(4)
(5)
(6) 2Y
(10)
D
D
D
lA
(9)
lB
(8) 3Y
2A
(12)
(13)
(11) 4V
28
3A
38
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617·12.
Pin numbers shown are for D, J. N, or W packages.
4A
lV
2V
3V
D
48
4V
positive logic
v
PRODUCTION DATA documonts •••III.I.formlll••
•• rre.t •• of puIIlicatl •• d.t•• Products .o.form to
.,..ifi..tio.s par th. tarms 01 T.... I.strume.ts
::':!:~i~·{::;:.'Ji ~::I::':l' !\l"::;:~~:~~ .ot
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
= A
+ B or V
=
Ii. • B
2-137
SN5432, SN54LS32, SN54S32,
SN7432, SN74LS32. SN74S32
QUADRUPLE 2·INPUT POSITIVE·OR GATES
schematics (each gate)
'LS32
'32
r--e-----.------~---e--vcc
r-.-----~----~--------~--vcc
130n
20 kn
20 kn
II kn
8 kn
120n
INPUTS
INPUTS
A-~--f
A---I+--j-......-{
OUTPUT
B_i..-a-/
B -t--UU>
~~Z>""
3
FUNCTION TABLE
INPUTS
A
(each gate)
4
5
OUTPUT
6
2
1 2019
CI)
Q)
(.)
'S;
Y
B
Q)
8
H
X
X
H
L
L
L
H
L
9 10 111213
C
alOU«aI
-I
NZZMM
CI
logic symbol t
lA
18
2A
28
3A
38
4A
48
(2)
l-
I-
NC - No intemal connection
;;;'11>
(3)
logic diagram
(5)
~: ______~~
__~~lY
(6)
(8)
: : ______
~~_·~~2Y
: : ______
~~~~~3Y
(9)
(11)
112)
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEe Publication 617·12.
Pin numbers shown are for D, J, N, and W packages.
: : ______
~~~~~4Y
positive logic
y
PRODUCTION DATA documents contain informetion
currant I. of publication data. Products conform to
specifications par the tarms af Taxas Instruments
~:~:=i~ai~:1~2a ~!:~::i:r :'~U:=:::t::.s not
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DAL.LAS, TEXAS 75265
~
A + B or Y
~
A • B
2-143
SN5433, SN54LS33, SN7433, SN74LS33
QUADRUPLE 2·INPUT POSITIVE·NOR BUFFERS WITH OPEN·COLLECTOR OUTPUTS
schematics (each gate)
'33
Vee
4kn
4kn
soon
INPUTS
A
B
250 n
GND
-t
-t
r0
'LS33
Vee
CD
<
n'
CD
17kn
17kn
3kn
INPUTS
UI
A
---------e----------__
L---__
----~--GND
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage: '33 ........................................................................ 5.5 V
'LS33 ........................................................................ 7 V
Off-state output voltage ....................................................................... 7 V
Operating free-air temperature: SN54' ................................................. -55°e to 125°C
SN74' .................................................... aOe to 7aoe
Storage temperature range ............................... , .......................... _65°C to 15aoe
NOTE 1: Voltage values are with respect to network ground terminal .
.'
2·144
.:t,,s
'.
TEXAS 'V
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
SN5433, SN7433
QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN5433
SN7433
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
V
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
VOH
High-level output voltage
5.5
5.5
V
IOL
Low-level output current
48
48
rnA
TA
Operating free-air temperature
70
°C
2
2
-55
125
V
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VIK
IOH
SN5433
TEST CONDITIONSt
TVP*
-12 rnA
Vce
~
MIN,
II
Vee
~
MIN,
VIL
~
0.8 V,
0.7 V,
~
MIN
Vee
~
MIN,
VIL
~
VOL
Vee
~
MIN,
VIH
~
II
Vee
~
MAX, VI
~
2 V,
5.5 V
IIH
Vce
~
MAX, VI
~
2.4 V
IlL
Vee
~
MAX, VI
~0.4
leeH
Vee
~
lecL
Vee
~
MAX, VI ~ 0
MAX, See Note 2
SN7433
MAX
MIN
TVP*
-1.5
-1.5
~
VOH
~
0.25
5.5 V
~
VOH
IOL
MAX
0.25
5.5 V
0.2
16 rnA
0.4
0.2
1
V
0.4
1
UNIT
V
rnA
V
rnA
40
40
~A
-1.6
-1.6
rnA
3
6
3
6
rnA
9
16.5
9
16.5
rnA
TVP
MAX
UNIT
10
15
ns
12
18
ns
15
22
ns
16
24
ns
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAil typical values are at VCC ~ 5 V, TA ~ 25°C.
NOTE 2: One input at 4.5 V. all others at 0 V.
switching characteristics. Vee = 5 V. TA = 25°e (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpLH
tpHL
tpLH
tpHL
TEST CONDITIONS
RL
A or B
~
133 kO,
eL
~
50 pF
Y
RL
~
133 kO,
CL
~
150 pF
MIN
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-145
SN54LS33, SN74LS33
QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN54LS33
SN74LS33
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
VOH High-level output voltage
5.5
5.5
V
IOL
Low-level output current
12
24
rnA
TA
Operating free-air temperature
70
°c
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
2
V
2
-55
125
0
electrical characteristics over recommended operating free-air temperatyre range (unless otherwise noted)
.oCD
<
n'
CD
en
MIN
VIK
Vce = MIN.
11=-18rnA
IOH
Vee - MIN.
VIH - 2 V.
VIL - MAX. VOH - 5.5 V
IOl - 12 rnA
TYP*
0.25
SN74LS33
MAX
MIN
TYP*
MAX
UNIT
- 1.5
-1.5
V
0.25
0.25
rnA
Vee = MIN.
VIH - 2 V.
Vil - MAX.
VCC = MIN.
VIL = MAX.
IOl = 24 rnA
II
Vec- MAX.
VI-7 V
0.1
0.1
rnA
IIH
Vec - MAX.
VI-2.7V
20
20
IlL
Vce = MAX.
VI =O.4V
-0.4
-0.4
/LA
rnA
VOL
-I
-I
SN54LS33
TEST CONDITIONS t
PARAMETER
0.4
0.25
0.4
0.35
0.5
V
leCH
VCC= MAX.
VI = 0
1.8
3.6
1.8
3.6
rnA
ICCl
VCC = MAX.
See Note 2
6.9
13.8
6.9
13.8
rnA
TYP
MAX
UNIT
20
32
ns
18
28
ns
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
'All typical values are at Vec = 5 V. TA = 25°C.
NOTE 2: One input at 4.5 V, all others at 0 V.
switching characteristics, Vee = 5 V, T A = 25°e (see note 3)
PARAMETER
tPlH
FROM
TO
(INPUT)
(OUTPUT)
AorB
y
TEST CONDITIONS
RL=667 n.
eL = 45 pF
tPHL
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-146
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
SN5437. SN54LS37. SN54S37.
SN7437. SN74LS37. SN74S37
QUADRUPLE 2·INPUT POSITIVE·NAND BUFFERS
DECEMBER 1983- REVISED MARCH 1988
•
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers
and Flat Packages. and Plastic and Ceramic
DIPs
SN5437. SN54LS37. SN54S37 ... J OR W PACKAGE
SN7437 ... N PACKAGE
SN74LS37. SN74S37 ... D OR N PACKAGE
(TOP VIEW)
Dependable Texas Instruments Quality and
Reliability
1A
18
1Y
2A
28
2Y
GND
description
These devices contain four independent 2-input
NAND buffer gates.
The SN5437. SN54LS37 and SN54S37 are
characterized for operation over the full military
range of - 55 DC to 125 DC. The SN7437.
SN74LS37 and SN74S37 are characterized for
operation from oDe to 70 0e.
FUNCTION TABLE
VCC
48
4A
4Y
38
3A
3Y
SN54LS37. SN54S37 ... FK PACKAGE
(TOP VIEW)
leach gate)
INPUTS
1Y
NC
OUTPUT
A
B
Y
2A
H
H
L
L
X
H
NC
28
X
L
H
9 10 111213
>-ou>-
(2)
logic diagram
(4)
1A--.--'
18
)P----1Y
(5)
(9)
2A~
28~
(10)
(12)
(13)
2Y
:: _ _,,--_)r- 3Y
t This symbol is in accordance with ANSI/IEEE Std 91 1984 and
::
lEe Publication 617 -12.
Pin numbers shown are for 0, J, N, and W packages.
)r-4Y
positive logic
y
~
A • B or Y
~
A + B
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of TexIs Instruments
:~~~~:~~i~ai~:,~1e ~!:~~~ti:; :'IO::~:~:t:~~S not
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-147
SN5437, SN54LS37, SN437
SN7437, SN74LS37, SN7437
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS
schematics (each gate I
''S7
'LS'S7
vee
4kn
600n
vee
lOOn
3kn
17k11
lOOn
INPUTS
A
A
B
B
GND
750 n
-t
-t
r-
1.5kn
GND
0
(1)
<
C:;'
'537
(1).
Vee
(I)
1.4kn
2511
38011
INPUTS
A
B
............... -....-GND
Resistor values shown are nominal,
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supplv voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage: '37, 'S37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
'LS37 ........................................................................ 7 V
Operating free·air temperature: SN54' ................................................. -55°C to 125°C
SN74' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OoC to 70°C
Storage temperature range .......................................................... -65°C to 150°C
NOTE 1: Voltage values are'with respect to network ground terminal.
2-148
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5437, SN7437
QUADRUPLE 2·INPUT POSITIVE·NAND BUFFERS
recommended operating conditions
SN5437
MIN
Vee
Supply voltage
VIH
High-level input voltage
NOM
4.5
VIL
Low-level input voltage
IOH
High-level output current
5
SN7437
MAX
MIN
NOM
MAX
5.5
4.75
5
5.25
2
IOL
Low-level output current
TA
Operating free-air temperature
2
V
V
0.8
0.8
-1.2
-1.2
rnA
48
rnA
70
e
48
55
UNIT
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
t
t
TEST CONDITIONS
SN5437
t
MIN
VIK
Vee = MIN,
11=-12rnA
VOH
Vee - MIN,
VIL - 0.8 V,
IOH = -1.2 rnA
VOL
Vee = MIN,
IOL
II
Vee = MAX,
VIH 2 V,
VI-5.5 V
IIH
IlL
Vee MAX,
Vee- MAX,
IOS§
Vee- MAX
leeH
Vee- MAX,
VI-O V
leeL
Vee - MAX,
VI- 4.5 V
TYP*
SN7437
MAX
MIN
TYP* MAX
-1.5
2.4
48 rnA
3.3
0.2
-1.5
2.4
0.4
3.3
0.2
1
UNIT
V
V
0.4
1
V
rnA
VI=2.4V
40
40
p.A
VI-OAV
-1.6
-1.6
rnA
-20
-70
rnA
9
15.5
9
15.5
rnA
34
54
34
54
rnA
-70
-18
en
Q)
CJ
'S
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
Q)
All typical values are at Vee = 5 V. T A = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
o
switching characteristics. Vee = 5 V, TA = 25°e (see note 2)
lI-
PARAMETER
tpLH
tpHL-
FROM
TO
(INPUT)
(OUTPUT)
Acr B
Y
..J
TEST CONDITIONS
RL = 133 n,
eL = 45 pF
MIN
TYP
MAX
13
22
8
15
UNIT
ns
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1,
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·149
SN54LS37, SN74LS37
QUADRUPLE 2·INPUT POSITIVE·NAND BUFFERS
recommended operating conditions
SN54LS37
Vee
Supply voltage
VIH
High·level input voltage
VIL
Low-level input voltage
IOH
High·level output current
SN74LS37
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
IOL
Low-level out put current
TA
Operating free-air temperature
2
V
V
0.7
0.8
-1.2
-1.2
mA
24
mA
70
°e
12
-55
UNIT
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
C
t
t
CD
<
(i'
CD
en
SN54LS37
t
MIN
VIK
Vee = MIN,
'1=-18mA
VOH
Vee - MIN,
VIL = MAX,
IOH = -1.2 mA
Vee = MIN,
VIH =2 V,
IOL=12mA
IOL = 24 mA
VOL
-t
-t
r-
TEST CONDITIONS
Vee - MIN,
VIH-2V,
II
Vee- MAX,
VI = 7 V
TYP*
SN74 LS37
MAX
MIN
TYP*
2.5
3.4
0.25
MAX
-1.5
-1.5
2.7
0.4
3.4
V
V
0.25
0.4
0.35
0.5
0.1
UNIT
0.1
V
mA
IIH
Vee= MAX,
VI=2.7V
20
20
IlA
IlL
Vee= MAX,
VI =0.4 V
-0.4
-0.4"
mA
IOS§
Vee = MAX
leeH
Vee- MAX,
VI = 0 V
leeL
Vee= MAX,
VI =4.5 V
- 30
-130
mA
0.9
-130
2
-30
0.9
2
mA
6
12
6
12
mA
For cpnditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vee =: 5 V, T A"" 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5 V, T A=< 25°e (see note 2)
PARAMETER
tpLH
FROM
TO
(INPUT)
(OUTPUT)
Aor B
TEST CONDITIONS
y
RL = 667 n,
eL = 45 pF
tpHL
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS.
2·150
INSTRUMENTS
POST
OF~ICE
BOX 655012 • DALLAS, TEXAS 75265
MIN
TYP
MAX
12
24
12
24
UNIT
ns
ns
SN54S37. SN74S37
QUADRUPLE 2·INPUT POSITIVE·NAND BUFFERS
recommended operating conditions
SN54S37
SN74S37
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
V
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
O.S
0.8
2
2
V
IOH
High-level output current
-3
-3
mA
IOL
Low-level output current
60
60
mA
TA
Operating free-air temperature
70
°e
-55
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
t
t
TEST CONDITIONS
SN54S37
t
MIN
VIK
Vee - MIN,
II = -IS mA
VOH
Vee = MIN,
VIL =O.SV,
IOH=-3mA
VOL
Vee = MIN,
VIH-2V,
IOL - 60 mA
II
Vee - MAX,
VI - 5.5 V
2.5
SN74S37
TVP* MAX
-1.2
MIN
TVP* MAX
-1.2
2.7
3.4
UNIT
V
V
3.4
0.5
0.5
1
1
mA
V
IIH
Vee - MAX,
VI - 2.7 V
0.1
0.1
mA
IlL
Vee - MAX,
VI-0.5V
-4
-4
mA
IOS§
Vee= MAX
leeH
Vee - MAX,
VI- 0 V
20
36
leeL
Vee - MAX,
VI- 4.5
46
SO
- 225
- 50
-50
- 225
mA
20
36
mA
46
SO
mA
CI)
Q)
(,)
'S
For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
Q)
All typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed 100 milliseconds.
c
-'
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
tpLH
tpHL
tpLH
tpHL
A or B
TEST CONDITIONS
RL =93,n,
eL = 50 pF
RL =93,n,
eL = 150 pF
V
MIN
TVP
MAX
4
6.5
4
6.5
6
6
UNIT
lI-
ns
ns
ns
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1
TEXAS .",
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
2·151
2-152
SN5438. SN54LS38. SN54S38.
SN1438. SN14LS38. SN14S38
QUADRUPLE 2·INPUT POSITIVE·NAND BUFFERS WITH OPEN·COLLECTOR OUTPUTS
DECEMBER 1983
REVISED MARCH 1988
SN5438. SN54LS38. SN54S38 ... J OR W PACKAGE
SN7438 ... N PACKAGE
SN74LS38. SN74S38 ... D OR N PACKAGE
• Package Options Include Plastic •'Small
Outline" Packages. Ceramic Chip Carriers
and Flat Packages. and Plastic and Ceramic
DIPs
(TOP VIEW)
lA
lB
lY
2A
2B
2Y
GND
• Dependable Texas Instruments Quality and
Reliability
description
These devices contain four independent 2-input NAND
buffer gates with open-collector outputs. The opencollector outputs require pull-up resistors to perform
correctly. They may be connected to other opencollector outputs to implement active-low wired-OR or
active-high wired-AND functions. Open-collector
devices are often used to generate high VOH levels.
VCC
4B
4A
4Y
3B
3A
SN54LS38. SN54S38 ... FK PACKAGE
(TOP VIEW)
U
The 5N5438. 5N54L538. and 5N54538 are
characterized for operation over the full military
temperature range of -55°C to 125°C. The 5N7438.
5 N7 4 L538. and 5 N74 538 are characterized for operation from O°C to 70°C.
~;:t:~~~
4A
NC
NC
2A
INPUTS
A
2B
(each gate)
H
L
L
X
H
X
L
H
NC - No internal connection
logic diagram
l A - - - -...
logic symbol t
lA
18
2A
28
3A
38
4A
48
(11
Q)
o
lI-
Y
H
·S
...I
OUTPUT
B
Q)
CJ
NC
3B
NC
FUNCTION TABLE
I/)
lB
&1>
2A
):>---IY
----r-'\... .
2B~
(2)
2Y
(4)
(5)
(9)
(10)
112)
positive logic
(13)
Y=A·BorY~A+B
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617 -1 2.
Pin numbers shown are for D. J. N. and W packages.
PRODUCTIDN DATA d.cumonts c.ntain information
current IS of publicatian date. Products confarm to
spacifications per the terms of Texas InstrumaRts
=~~:~~i~I{:~~7i ~:~::i:r :.~,,:::::::.::.' not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-153
SN5438, SN54LS38, SN54S38,
SN7438, SN74LS38, SN74S38
QUADRUPLE 2·INPUT POSITIVE·NAND BUFFERS WITH OPEN·COLLECTOR OUTPUTS
s.chematics leach gate)
'38
'LS38
vee
60012
INPUTS
INPUTS
OUTPUT
A
y
OUTPUT
A
y
B
B
40012
GND
~~------------~~~~---GND
'S38
r-------~---------vee
A
B
~....~._-GND
Resistor values shown are nominal.
absolute maximum ratings over operating free·air temperature (unless otherwise noted)
Supply voltage. Vee (see Note 1) ..... : ......................................................... 7 V
Input voltage: '38 ......................................................................... 5.5 V
LS38 ......................................................................... 7V
Off'state output voltage ...... _............. -................ " .................................. 7 V
Operating free·air temperature ra~ge: SN54· ....... : .................................... - 55°C to 125°C
SN74' ................................................ oOe to 70°C
Storage temperature range ......................................................... , - 65~e to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
2-154
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5438. SN7438
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN7438
SN5438
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
V
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
V
VOH
High-level output voltage
5.5
5.5
V
48
mA
70
°e
V
2
2
48
IOL
Low-level output current
TA
Operating free-air temperature
- 55
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
Vee ~ MIN,
II
Vee ~ MIN,
VIL ~ 0.8 V,
Vee ~ MIN,
VIL
Val
Vee ~ MIN,
VIH ~ 2 V,
II
Vee ~ MAX,
VI
~
IIH
Vee
MAX,
VI
III
Vee ~ MAX,
leeH
leel
VIK
IOH
SN5438
TEST CONDITIONSt
PARAMETER
~
MIN
MIN
TYP*
- 1.5
-12 rnA
~
SN7438
MAX
TYP*
MAX
-1.5
VOH ~ 5.5 V
~
0.25
UNIT
V
rnA
5.5 V
0.25
16 rnA
0.4
0.4
5.5 V
1
1
rnA
~
2.4 V
40
40
VI
~
0.4 V
- 1.6
-1.6
"A
rnA
Vee ~ MAX,
VI
~
0
Vee ~ MAX,
VI
~
4.5 V
~
0.7 V,
VOH
IOl
~
V
5
8.5
5
8.5
rnA
34
54
34
54
rnA
III
Q)
(.)
">
Q)
o
...J
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*AII typical values are at Vee ~ 5 V, TA ~ 25°e.
lI-
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
PARAMETER
tPLH
tpHL
FROM
TO
(INPUT)
(OUTPUT)
A or B
Y
TEST CONDITIONS
eL
RL"133f!,
MIN
~45
pF
TYP
MAX
14
22
UNIT
ns
11
18
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-155
SN54lS38, SN74LS38
QUADRUPLE 2-INPUT POSITIVE·NAND BUFFERS WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN54LS38
SN74LS38
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
O.B
V
VOH High-level output voltage
5.5
5.5
V
IOL
Low-level output current
12
24
mA
TA
Operating free-air temperature
70
°c
VCC
Supply voltage
V,H
High-level input voltage
V,L
Low-level input voltage
2
V
2
125
- 55
0
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
TEST CONDITIONS t
PARAMETER
V,K
Vcc= MIN,
1,--18mA
IOH
VCC= MIN,
V,i. = MAX,
VCC= MIN,
V,H
2V,
IOL=12mA
VCC = MIN,
V'H=2V,
V,-7 V
IOL - 24 mA
VOL
VCC- MAX,
"
-t
-t
.-
MIN
TYP* MAX
- 1.5
0.25
0.25
VOH-5.5V
0.25
0.4
0.25
0.4
0.35
0.5
0.1
UNIT
V
mA
V
0.1
mA
"H
VCC= MAX,
V, = 2.7 V
20
20
',L
ICCH
VCC= MAX,
V, =OAV
-0.4
-0.4
IJA
mA
VCC- MAX,
V, =0
.ICCL
VCC= MAX,
V,-4.5V
t
CD'
f All typical values are at Vee == 5 V. T A == 25°C.
~.
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
UI
SN74LS38
MIN
-1.5
C
CD
SN54LS38
TYP* MAX
0.9
2
0.9
2
mA
6
12
6
12
mA
For conditons shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PARAMETER
tPLH
tpHL
FROM
TO
(INPUT)
(OUTPUT)
Aor B
y
TEST CONDITIONS
RL=667n,
CL = 45 pF
NOTE 2: Load circuits and voltage waveforms are shown in Section 1 .
2-156
. TEXAS.
INSTRUMENTS
POST OFFICE BOX 666012 • DAllAS, TEXAS 75265
MIN
TYP
MAX
20
32
UNIT
ns
lB
2B
ns
SN54S38. SN74S38
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN74S38
SN54S38
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
V
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
VOH
High-level output voltage
5.5
5.5
V
IOL
Low-level output current
60
60
mA
TA
Operating free-air temperature
70
DC
V
2
2
- 55
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VIK
IOH
SN54S38
TEST CONDITIONSt
PARAMETER
Vce
~
MIN,
II
Vee
~
MIN,
VIL
~
0.8 V,
MIN
TVP*
-18 mA
~
Vee
~
MIN,
VIL
~
VOL
Vee
~
MIN,
VIH
~
II
Vce
~
MAX,
VI
~
IIH
Vee
~
MAX,
VI
IlL
Vee ~ MAX,
VI
SN74S38
MAX
MIN
TVP*
-1.2
VOH
~
5.5 V
0.7 V,
VOH
~
5.5 V
0.25
2 V,
IOL ~ 60 mA
MAX
-1.2
0.25
UNIT
V
mA
V
0.5
0.5
5.5 V
1
1
mA
~
2.4 V
0.1
0.1
mA
CII
~
0.5 V
-4
-4
mA
Q)
(.)
0
20
36
20
36
mA
4.5 V
46
80
46
80
mA
lecH
Vee
~
MAX,
VI
~
leeL
Vee
~
MAX,
VI
~
>
Q)
o
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAil typical values are at Vee ~ 5 V, TA ~ 25°e.
switching characteristics,
PARAMETER
tPLH
D
FROM
TO
(INPUT)
(OUTPUT)
A or B
lI-
Vee = 5 V, TA = 25 e (see note 2)
tpLH
tPHL
...J
TEST CONDITIONS
RL=9311,
CL = 50pF
RL = 9311,
CL=150pF
y
tPHL
MIN
TVP
MAX
6.5
10
UNIT
ns
6.5
10
ns
9
ns
8.5
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
l!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-157
2-158
SN5439. SN7439
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS
WITH OPEN-COLLECTOR OUTPUTS
MAY 1983
REVISED MARCH 1988
SN5439 ... J PACKAGE
SN7439 ... N PACKAGE
• Current Sinking Capability up to 80 mA
• Guaranteed Fan-Out of 30 Series 54/74 Loads
(TOP VIEWI
• Dependable Texas Instruments Quality
and Reliability
lY
lA
lB
2Y
description
These devices contain four independent 2-input NAND
buffers. The open-collector outputs require pull-up
resistors to perform correctly. They may be connected
to other open-collector outputs to implement active-low
wired-OR or active-high wired-AND functions. Opencollector devices are often used to generate higher VOH
levels.
The SN5439 is characterized for operation over the full
military temperature range of - 55°e to 125°e. The
S N7439 is characterized for operation from 0 ° e to
70 o e.
2A
3Y
2B
GND
3B
-..._----', 3A
schematics (each gate)
, - - - - -...- - - - Vec
4kn
600n
INPUTS
A
logic symbol t
lA
lB
2A
2B
3A
3B
4A
4B
OUTPUT
Y
B-+-.....
CIl
Q)
0>"
Q)
(2)
&[>
(3)
C
lY
~
(5)
...--~--~-GNO
~-e~-
2Y
16)
(8)
3Y
(9)
logic diagram
(11)
18
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617·12.
2A
2B
IV
~2V
---L....-Jr--
3 A = D - 3V
FUNCTION TABLE (each gate)
INPUTS
---L....-J»-
lA _ _ _. r -...
4Y
(12)
..J
....
....
3B
OUTPUT
A
B
Y
4 A = D - 4V
H
H
L
4B
L
X
H
X
L
H
positive logic
Y=A·BorY = A + B
PRODUCTION DATA documents contain information
currant 81 Qf publication data. Products conform to
specifications par the tarms of Taxas Instruments
::~:~i~I{::I~'li ~.:\:~ti:; :'~D:=:::::':~~ not
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-159
SN5439. SN7439
QUADRUPLE 2·INPUT POSITIVE·NAND BUFFERS
WITH OPEN·COLLECTOR OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage. Vee (see Note 1) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7V
Off'state output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7V
Operating free·air temperature range: SN5439 ........................................... -55°C to 125°C
SN7439 .............................................. oOe to 70°C
Storage temperature range ........................................................... _65°C to 150°C
NOTE1:
Voltage values are with respect to network ground terminal.
recommended operating conditions
SN5439
----I
SN7439
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
V
V
Vee
Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
0.8
0.8
VOH
High-level output voltage
5.5
5.5
IOl
Low-level output voltage
60
60
TA
Operating free-air temperature
tThe extended limit applies only if
Vee
UNIT
MIN
2
V
2
-55
t
80e70
a
125
V
rnA
ra--e
is maintained between 4.75 and 5.25 V.
~
rC
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
CD
~.
PARAMETER
CD
VIK
n
til
IOH
VOL
SN5439
TEST CONDITIONS t
MIN
TYP
SN7439
MAX
MIN
TYP
MAX
Vee ~ MIN.
II
Vee ~ MIN.
Vil ~ 0.8 V.
VOH
~
Vee ~ MIN.
Vil ~ 0.7 V.
VOH
~
Vee ~ MIN.
IOl ~ 48 rnA
0.4
0.4
Vee ~ MIN.
IOl ~ 60 mA
0.5
0.5
~
-12 rnA
-1.5
-1.5
5.5 V
0.25
5.5 V
0.25
Vee ~ 4.75 V. IOl ~ 80 rnA
UNIT
V
rnA
V
0.6
II
Vee ~ MAX.
VI
~
5.5 V
1
1
IIH
Vee ~ MAX.
VI
~
2.4 V
40
40
~A
III
Vee ~ MAX.
VI
~
0.4 V
-1.6
-1.6
mA
leeH
Vee ~ MAX,
VI ~ 0
54
54
mA
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
switching characteristics, Vee = 5 V, T A = 25°e (see note 2)
PARAMETER
tplH
tPHl
FROM
TO
(INPUT)
IOUTPUT)
A or B
Y
SN5439
TEST CONDITIONS
Rl" 133l1,
el
MIN
45 pF
NOTE 2: Load CIrCUits [)nd voltage waveforms are shown in Section 1
2-160
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN7439
MAX
MIN
MAX
22
22
18
18
UNIT
ns
SN5440. SN54LS40. SN54S40.
SN7440. SN74LS40. SN74S40
DUAL 4·INPUT POSITIVE·NAND BUFFERS
APRIL 1985-REVISED MARCH 1988
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers
and Flat Packages in Addition to Plastic and
Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN5440 ••. J PACKAGE
SN54LS40. SN54S40 ... J OR W PACKAGE
SN7440 ... N PACKAGE
SN74LS40. SN74S40 ... D OR N PACKAGE
(TOP VIEWI
1A
1B
NC
1C
10
1Y
GND
description
These devices contain two independent 4·input
NAND buffer gates.
The SN5440. SN54LS40. and SN54S40 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN7440. SN74LS40. and SN74S40 are
characterized for operation from O°C to 70 o e.
FUNCTION TABLE
(TOP VIEWI
1A
1Y
NC
VCC
NC
2A
2B
OUTPUT
0
V
H
H
X
X
L
H
H
H
H
C
SN5440 ... W PACKAGE
(each gate)
INPUTS
A
B
H
L
H
X
X
L
X
X
X
X
L
X
X
X
X
L
VCC
2D
2C
NC
10
1C
1B
GND
2Y
VI
Q)
(,)
'S
Q)
C
..J
SN54LS40. SN54S40 ... FK PACKAGE
lI-
(TOP VIEW)
logic symbol t
lA
lB
lC
lD
2A
2B
2C
2D
(11
&t>
(21
(41
NC
1C
NC
10
IV
(51
(91
2C
NC
NC
NC
2B
5
6
7
8
1101
1121
2V
(131
NC - No internal connection
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J. N. and W packages.
logic diagram
----=t
-t
"-------
B
11 AC
~IY
1 0 - -.....- ' ·
_ »--2Y
2~ACB==t
2D
positive logic
y
~ A ' B • C ' D
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
or Y
~ A
-
-
-
+ B + C + D
2·161
SN5440, SN54LS40, SN54S40,
SN7440, SN74LS40, SN74S40
DUAL 4·INPUT POSITIVE·NAND BUFFERS
schematics (each gate)
'LS40
'40
r-------~--------~-vcc
r------.--------~~vcc
4 kO
6000
17 kO
1000
INPUTS
3 kO
1000
A
A
B
B
C
OUTPUT
0
y
C
0
-4
-4
~
rC
__~~--------~-------------4~GND
'S40
(I)
r------.---------.~vcc
~.
1.4 kO
(')
3800
250
(I)
en
y
A
B
c--+-+-..
D--+-+-+-"
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: '40, 'S40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
'LS40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range: SN54' . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 DC to 125 DC
SN74' ................................ oDe to 70 De
Storage temperature range ......................................... - 65 DC to 1 50 DC
NOTE 1: Voltage values are with respect to network ground terminal.
2-162
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN5440. SN7440
DUAL 4·INPUT POSITIVE·NAND BUFFERS
recommended operating conditions
SN5440
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
SN7440
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
IOL
Low-level output current
TA
Operating free-air temperature
V
V
2
0.8
0.8
-1.2
-1.2
rnA
48
rnA
70
°c
48
- 55
UNIT
125
a
V
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
MIN
SN7440
TYPt MAX
MIN
TYPt
-1.5
VIK
Vcc - MIN,
11=-12rnA
VOH
VCC - MIN,
VIL = 0.8 V,
IOH = -1.2 rnA
VOL
VCC = MIN,
VIH=2V,
IOL =48rnA
II
VCC- MAX,
VI - 5.5 V
2.4
3.3
0.2
MAX
-1.5
2.4
0.4
3.3
0.2
1
I'A
VI = 2.4 V
40
40
VCC - MAX,
VI - 0.4 V
-1.6
-1.6
IOS§
VCC = MAX
ICCH
VCC MAX,
VCC- MAX,
-18
rnA
-70
rnA
rnA
0
4
8
4
8
VI-4.5V
17
27
17
27
VI
V
rnA
VCC - MAX,
-70
V
1
IIH
- 20
UNIT
V
0.4
IlL
ICCL
t
t
SN5440
TEST CONOITIONS t
PARAMETER
CI)
Q)
CJ
rnA
·S
Q)
a
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vee := 5 V, T A "" 2SoC.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed 100 milliseconds.
switching characteristics, Vee = 5 V, TA = 25° C (see note 2)
PARAMETER
tPLH
FROM
(INPUT)
Any
TO
(OUTPUT)
Y
-oJ
TEST CONDITIONS
RL = 133n,
CL = 15 pF
tpHL
MIN
TYP
MAX
13
22
UNIT
ns
8
15
ns
lI-
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·163
SN54LS40. SN74LS40
DUAL 4·INPUT POSITIVE·NAND BUFFERS
recommended operating conditions
SN74LS40
SN54LS40
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2.
Low-level output current
Operating free-air temperature
V
V
2
0.7
08
-1.2
-1.2
mA
24
mA
70
°e
12
IOL
TA
UNIT
- 55
125
0
V
electrical'characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LS40
t
MIN
VIK
Vee" MIN,
II - - 18 mA
VOH
Vee - MIN,
VIL" MAX,
IOH - - 1.2 mA
Vee-MIN,
VIH - 2 V,
IOl -12mA
Vee - MIN,
VIH-2V,
IOl - 24 mA
II
Vee- MAX,
VI- 7 V
VOL
MAX,
TYPt
SN74LS40
MAX
MIN
TYPt
-1.5
2.5
3.4
-1.5
2.7
0.25
MAX
0.4
3.4
V
V
0.25
0.4
0.35
0.5
0.1
0.1
UNIT
V
mA
2.7 V
20
20
I'A
VI - 0.4 V
-0.4
-0.4
rnA
VI
IIH
Vee
III
Vee - MAX,
IOS§
Vee- MAX
leeH
Vee" MAX,
VI- 0
leel
Vee - MAX,
VI-4.5V
- 30
-130
- 30
- 130
mA
0.45
1
0.45
1
mA
3
6
3
6
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t:
All typical values are at
Vee
=
5 V, T A "" 25° C.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
switching characteristics, Vee
PARAMETER
tplH
tpHl
FROM
(INPUT)
Any
= 5 V, TA = 25°e (see note 2)
TO
(OUTPUT)
Y
TEST CONDITIONS
Rl"667H,
Cl" 45 pF
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2-164
"-II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
TYP
MAX
UNIT
12
24
ns
12
24
os
SN54S40. SN74S40
DUAL 4·INPUT POSITIVE·NAND BUFFERS
recommended operating conditions
SN54S40
Vee
Supply voltage
VIH
High-level input voltage
SN74S40
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
UNIT
V
V
2
Vil
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
-3
-3
mA
IOl
TA
60
mA
Operating free-air temperature
70
°c
Low-level output current
60
125
- 55
a
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
SN74S40
SN54S40
TEST CONDITIONS t
PARAMETER
MIN
VIK
Vee = MIN,
II '-1amA
VOH
Vee- MIN,
Vll' 0.8 V,
IOH' - 3 mA
VOL
Vee-MIN,
IOL=60mA
II
Vee' MAX,
VIH' 2 V,
VI-5.5V
IIH
Vee- MAX,
VI=2.7V
IlL
IOS§
Vee= MAX,
VI - 0.5 V
2.5
TYP* MAX
- 1.2
3.4
- 50
MIN
2.7
TYP* MAX
-1.2
3.4
UNIT
V
V
0.5
0.5
V
1
1
mA
0.1
0.1
mA
-4
-4
mA
- 225
mA
- 225
- 50
leeH
Vee- MAX
Vee= MAX,
VI = 0
10
18
10
18
mA
leel
Vee = MAX,
VI = 4.5 V
25
44
25
44
mA
t For conditions shown 8S MI N or MAX, use the appropriate value specified under recommended operating conditions.
*All tvpical values are at Vee;;;: 5 V, T A
PARAMETER
FROM
(INPUT)
(OUTPUT)
tPLH
tPHL
tPLH
tpHL
TEST CONDITIONS
RL=93f1,
Any
CL = 50 pF
Y
RL'93f1,
eL' 150pF
MIN
'S;
C
....t-
=S V, TA =2Soe (see note 2)
TO
Q)
to)
Q)
= 2SoC.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed 100 milliseconds.
switching characteristics, Vee
en
TYP
MAX
4
4
6.5
6.5
UNIT
t-
ns
ns
6
ns
6
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-165
-I
-I
r-
C
en
<
(")
en
en
2-166
SN5442A. SN54LS42. SN74442A. SN74LS42
4-LlNE BCD TO 10-LlNE DECIMAL DECODERS
MARCH 1974- REVISED MARCH 1988
•
All Outputs Are High for Invalid Input
Conditions
•
Also for Application as
4-Line-to-16-Line Decoders
3-Line-to-8-Line Decoders
•
SN5442A. SN54LS42 ... J OR W PACKAGE
SN7442A ... N PACKAGE
SN74LS42 ... D OR N PACKAGE
ITOP VIEW)
Diode-Clamped Inputs
TYPES
TYPICAL
TYPICAL
POWER
PROPAGATION
DISSIPATION
DELAYS
'42A
140 mW
17 ns
'LS42
35 mW
17 ns
A
B
e
4
D
5
6
9
8
7
GND
description
SN54LS42 ... FK PACKAGE
These monolithic BCD-to-decimal decoders
consist of eight inverters and ten four-input
NAND gates. The inverters are connected in
pairs to make BCD input data available for
decoding by the NAND gates. Full decoding of
valid input logic ensures that all outputs remain
off for all invalid input conditions.
ITOP VIEW)
u
u u
02>«
3
2
3
The SN5442A and SN54LS42 are characterized
for operation over the full military temperature
range of - 55
to 125
The SN7442A and
SN74LS42 are characterized for operation from
to 70 C.
ac
ac.
2
1 20 19
4
CI)
Q)
CJ
5
'S;
Ne
The '42A and 'LS42 feature inputs and outputs
that are compatible for use with most TTL and
other saturated low-level logic circuits. DC noise
margins are typically one volt.
oac
Vee
0
1
2
3
Q)
o
7
8
9 10111213
...J
....
....
NC - No internal connection
a
PRODUCTION DATA documents contain information
currant as of publication data. Products conform to
specifications par the terms of Taxas Instruments
=~~~~:~~i~ai~:1~1e ~!::i~~ti:r ~~O::~:::::t:~~S not
TEXAS •
INSTRUMENTS
POST OFF1CE BOX 655012 • DALLAS, TEXAS 75265
2-167
SN5442A, SN54LS42, SN7442A, SN74LS42
4·LlNE BCD TD 10·LlNE DECIMAL DECODERS
logic symbol t
BCDIDEC
0
A
B
C
0
(15)
2
(14)
3
(13)
(12)
2
4
4
5
8
6
t This symbol is in accordance with ANSIIIEEE Std 91-1984 and lEe Publication 617-12.
~
logic diagram (positive logic)
r-
~
<
INPUT A 1151
C:;'
CD
en
INPUT
e 1141
Pin numbers shown are for D. J, N. and W packages.
2-168
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
SN5442A. SN54LS42. SN7442A. SN74LS42
4·LlNE BCD TO 1D·LlNE DECIMAL DECODERS
schematics of inputs and outputs
'LS42
'42A
EQUIVALENT OF
EACH INPUT
EQUIVALENT OF
EACH INPUT
VCC ----<11----
- -
VCC
Req -
17 kO NOM
INPUT
INPUT
.
--
r,
J~
~
~t>
J,
VI
Q)
C.J
'S
Q)
C
'42A
'LS42
TYPICAL OF
ALL OUTPUTS
TYPICAL OF
ALL OUTPUTS
....I
....
....
VCC
--,.--VCC
1200 NOM
130 II NOM
' - - -....-OUTPUT
OUTPUT
"-!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·169
SN5442A, SN54LS42, SN7442A, SN74LS42
4-L1NE BCD TO 10-L1NE DECIMAL DECODERS'
FUNCTION TABLE
NO.
0
0
1
2
3
4
5
6
7
L
8
9
C
">
;!l;
-I
-I
rC
H
= high
L
DECIMAL OUTPUT
A
0
1
2
3
4
5
6
7
8
9
L
L
L
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
L
H
H
H
H
H
H
H
L
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
L
H
H
L
H
H
H
H
L
H
H
L
H
H
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
'L
L
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
H
H
L
H
H
H
H
L
H
H
H
H
"H
H
H
H
H
H
H
H
::::i
BCD INPUT
C
B
level. L
=
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
low level
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
CD
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . .. 7 V
Input voltage: '42A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,............... 5.5 V
'LS42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range: SN5442A, SN54LS42 ......... " ..... -55°e to 125 0 e
SN7442A, SN74LS42 .................... ooe to 70 0 e
Storage temperature range .... '., .................. , ...... , .. ,..... - 65°C to 150°C
<
Cr
CD
!II
NOTE 1: Voltage values are with respect to network ground terminal.
2-170
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN5442A, SN7442A
4-UNE BCD TO 10-UNE DECIMAL DECODERS
recommended operating conditions
SN5442A
MIN
Supply voltage,
Vee
NOM
4.5
SN7442A
MAX
MIN
5.5
4.75
5
NOM
MAX
5.25
V
·800
~A
5
800
High-level output current, IOH
16
Low-level output current, tOL
--55
Operating free-air temperature, T A
125
UNIT
16
70
0
mA
··C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
MIN
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
SN7442A
SN5442A
TEST CONDITIONSt
PARAMETER
Tvp:l: MAX
2
VCC" MIN,
II "-12mA
VCC - MIN,
VIH
VIL
= 0.8
V,
VCC" MIN,
LOW-level output voltage
VIH
II
Input current at maximum Input voltage
High-level input current
IlL
Low level mput current
lOS
Short-circuit output current ':
ICC
Supply current
2.4
-800~A
UNIT
Tvp:l: MAX
V
2
0.8
0.8
V
··1.5
-1.5
V
3.4
2.4
V
3.4
UJ
Q)
= 2V,
= 16mA
0.2
= 0.8V, 10L
VCC = MAX, VI = 5.5V
VCC = MAX, VI = 2.4 V
VCC = MAX, VI = 0.4 V
VCC = MAX
VCC = MAX, See Note 2
VIL
IIH
= 2V,
10H =
MIN
0.4
0.2
1
1
40
40
-1.6
20
·55
28
0.4
18
41
28
c.J
V
-S;
mA
~A
Q)
C
-1.6
mA
..oJ
--55
mA
l-
56
mA
I-
I For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.
:i-AII typical values £Ire at Vee" 5 V, T A'" 25"C.
~Not more than one output should be shorted at a time.
NOTE 2:
ICC is measured with all outputs open and all inputs grounded.
switching characteristics,
Vee = 5 V, T A = 25° C
PARAMETER
TEST CONDITIONS
Propagation delay time, high-to-Iow-Ievel
tpHL
output from A, B, C, or 0 through 3 levels of logic
Propagation delay time, low-to-h igh-Ievel
tPLH
output from A, B, C, and 0 through 2 levels of logic
CL~15pF,
RL
c
MAX
UNIT
14
25
ns
17
30
ns
10
25
ns
17
30
ns
400 l!,
See Note 3
Propagation delay time, low-to-high-Ievel
tPLH
TVP
output from A, B, C, or 0 through 2 levels of logic
Propagation delay time, high-to-Iow-Ievel
tpHL
MIN
output from A, B, C, and 0 through 3 levels of logic
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-171
SN54LS42, SN74LS42
4-L1NE BCD TO 10-L1NE DECIMAL DECODERS
recommended operating conditions
SN54lS42
Supply voltage, Vee
SN74lS42
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-400
8
I'A
mA
70
·e
High-level output current. IOH
-400
Low-level output current, IOL
4
Operating free-air temperature. T A
UNIT
MIN
-55
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
Vil
VIK
Low-level input voltage
I nput clamp voltage
Low-Jevel
o~tput
voltage
II
Vee= MIN,
II = -lBmA
Vee- MIN,
VIH=2V,
maximum input voltage
2.5
Vll = Vil max, 10H = -4001'A
Vee = MIN,
VIH=2V,
Vil = Vil max
Input current at
-4
-4
MIN
SN74lS42
TYPj: MAX
2
VOH High-level output voltage
Val
SN54lS42
TEST eONDITIONSt
VI = 7V
UNIT
V
0.7
0.8
V
-1.5
-1.5
V
3.5
2.7
0.4
II0l =8mA
Vee= MAX.
TYP* MAX
2
0.25
LIOl=4mA
MIN
3.5
V
0.25
0.4
0.35
0.5
0.1
0.1
V
mA
r-
IIH
High-level input current
Vee= MAX.
VI=2.7V
20
20
!'A
o
III
Low-level input current
Vee- MAX.
VI-O.4V
-0.4
-0.4
mA
lOS
Short-circuit output current §
Vee = MAX
-100
mA
CD
<
ICC
Supply current
Vee- MAX,
13
mA
c:r
CD
en
-20
-100
7
See Note 2
-20
13
7
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V. T A = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2. ICC is measured with all outputs open and inputs grounded.
switching characteristics, Vee = 5
V, T A = 25° e
PARAMETER
tpHl
TEST CONDITIONS
output from A, B, C, or 0 through 2 levels of logic
Propagation delay time, high-to-Iow-Ievel
tpHl
CL = 15pF,
output from A, B, C, or D. through 3 levels of logic
See Note 3
output from A, B, C, and 0 through 2 levels of logic
Propagation delay time, low-to-high-Ievel
tplH
output from A, B, C, and 0 through 3 levels of logic
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-172
TYP
MAX UNIT
15
25
ns
20
30
ns
15
25
n.
20
30
n.
RL = 2 kQ,
Propagation delay time, low-to-high-level
tpLH
MIN
Propagation delay time, high-to-Iow-Ievel
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
SN5445, SN7445
BCD-lO-DECIMAL DECODERS/DRIVERS
DECEMBER 1972-REVISED MARCH 19B8
FOR USE AS LAMP, RELAY, OR MOS DRIVERS
featuring
•
Full Decoding of Input Logic
•
SO-rnA Sink-Current Capability
•
All Outputs Are Off for Invalid
BCD Input Conditions
SN5445 ... J OR W PACKAGE
SN7445 •.. N PACKAGE
(TOPVIEWI
o
VCC
A
B
2
3
C
D
4
5
6
FUNCTION TABLE
NO.
D
1
2
3
4
5
6
7
8
9
C
J
«
>
~
INPUTS
0 C
L L
L L
L L
L L
L H
L H
L H
L H
H L
H L
H L
H L
H H
H H
H H
H H
B
OUTPUTS
A
L
L
L
H
H L
H H
L
L
L
H
H L
H H
L
L
L
H
H L
H H
L
L
L
H
H L
H H
0
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2 3
H H
H H
L H
H L
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
4
5
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
6 7
H H
H H
H H
H H
H H
H H
L H
H L
H H
H H
H H
H H
H H
H H
H H
H H
8
H
H
H
H
H
9
H
H
H
H
H
H H
H H
H H
L H
H L
H H
H H
H H
H H
H H
H H
9
8
7
GND
logic diagram (positive logic)
OUTPUT
a
OUTPUT 1
CI)
OUTPUT 2
'S;
OUTPUT 3
C
Q)
(,)
Q)
...I
OUTPUT 4
~
~
OUTPUT 5
OUTPUT 6
H = high level (off), L"" low level (on)
OUTPUT 7
description
These monolithic BCD-to-decimal decoders/drivers
consist of eight inverters and ten four-input NAND
gates. The inverters are connected in pairs to make BCD
input data available for decoding by the NAND gates.
Full decoding of valid BCD input logic ensures that all
outputs remain off for all invalid binary input conditions.
These decoders feature TTL inputs and highperformance, n-p-n output transistors designed for use
as indicator/relay drivers or as open-collector logiccircuit drivers. Each of the high-breakdown output
transistors (30 volts) will sink up to 80 milliamperes of
current. Each input is one normalized Series 54/74 load.
Inputs and outputs are entirely compatible for use with
TTL logic circuits, and the outputs are compatible for
interfacing with most MOS integrated circuits. Power
dissipation is typically 215 milliwatts.
OUTPUT 8
logic symbol
0
1
A
B
C
0
2
3
(15)
(14)
1
(13)
(12)
2
4
4
5
8
6
liEN
8
9
>9za
Pin numbers shown are for J, N, and W packages.
PRODUCTION DATA d••um...l••••llin informalio.
• urrenl II of publi••lion dill. Product••onform 10
speCifications p. the tlrml af TI.I. InltrumBntl
::~:~~i~·{:1~7i ~=:~ti~n lI~a;:;::~:~~ nDt
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-173
SN5445, SN7445
BCD-TO-DECIMAL DECODERS/DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage . . . . . . . .
Maximum current into any output (off-state)
Operating free-air temperature range: SN5445 Circuits
SN7445 Circuits
Storage temperature range
7V
5.5 V
1 mA
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN5445
MIN
SupplV voltage, Vee
4.5
NOM
SN7445
MAX
MIN
5.5
4.75
5
Off·state output voltage
NOM
5
30
Operating free-air temperature, T A
-55
UNIT
MAX
V
5.25
30
125
0
V
°e
70
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONOITIONSt
PARAMETER
V,H
High-level input voltage
V,L
Low-level input voltage
V,K
Input clamp voltage
VO(on)
On-state output voltage
'O(off)
Off-state output current
MIN
TYPt
MAX UNIT
2
Vee" MIN,
1,--12rnA
Vee" MIN,
V'H" 2V,
V,L "O.BV
I
I
V
0.5
'O(on) " BO rnA
O.B
V
-1.5
V
0.9
V
0.4
'O(on) " 20 rnA
Vee - MIN, V,H"2V,
250
)lA
Input current at maximum input voltage
Vee" MAX, V," 5.5V
1
rnA
"
"H
High-level input current
Vee- MAX, V," 2.4 V
40
)lA
',L
Low-level input current
Vee" MAX,
V, - 0.4 V
-1.6
rnA
lee
Supplv current
Vee" MAX, See Note 2
V,L "0.8V, VO(off) " 30 V
I
I
SN5445
43
62
SN7445
43
70
rnA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
tAli typical values are at Vee"" 5 V, T A"" 2soe.
NOTE 2: ICC is measured with atl inputs grounded and outputs open.
switching characteristics, Vee = 5 V, TA = 25°e
I
I tPLH
I tpHL
PARAMETER
TEST CONDITIONS
Propagation delay time, low-to-high-Ievel output
Propagation delay time, high-to-Iow-Ievel output
eL" 15 pF,
RL" 100!!,
See Note 3
I MIN
I
TYP
I
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
schematics of inputs and outputs
EaUIVALENT OF ALL INPUTS
TYPICAL OF ALL OUTPUTS
vcc _ _ _...._ __
INPUT
2-174
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MAX
50
50
IUNIT I
I ns I
I
ns
I
SN5446A, '47 A, '48, SN54LS47, 'LS48, 'LS49,
SN7446A, '47A, '48, SN74LS47, 'LS48, 'LS49
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
MARCH 1974-REVISED MARCH 1988
'48, 'LS48
'46A, '47A, 'LS47
feature
'LS49
feature
feature
• Open· Collector Outputs
Drive Indicators Directly
• Internal Pull·Ups Eliminate
Need for External Resistors
• Lamp·Test Provision
• Lamp·Test Provision
• Leading/Trailing Zero
Suppression
• Leading/Trailing Zero
Suppression
SN5446A.SN5447A. SN54LS47. SN5448.
SN54LS48 ... J PACKAGE
SN7446A. SN7447A.
SN7448 ... N PACKAGE
SN74LS47. SN74LS48 ... 0 OR N PACKAGE
(TOP VIEW)
B
C
LT
BiIRBO
RBI
• Open-Collector Outputs
• Blanking Input
SN54LS47. SN54LS48 ... FK PACKAGE
(TOP VIEW)
U 8
umz>_
3 2
1 20 19
VCC
9
f
BI/RBO
9
NC
a
NC
b
14
b
C
9 10111213
0
A
d
GND
e
«CUQ)-c
ZZ
(!)
SN54LS49 ... J OR W PACKAGE
SN74LS49 ... 0 OR N PACKAGE
(TOP VIEW)
SN54LS49 ... FK PACKAGE
(TOP VIEW)
U
8
B
C
VCC
umz>-
f
3 2 1 2019
BI
9
0
a
A
b
e
c
NC
GND
d
b
9
NC
a
9 10 111213
" C U
ZZ
-C
"
(!)
NC - No internal connection
PRODUCTION DATA documonts contain information
current a. of publication data. Products conform to
specifications per the tarms of Taxas Instruments
:~~~~:~~j~8i~:I~'~ ~~:~:~ti:; ~iU::~:::t:~~ not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75266
2-175
SN5446A, '47A, '48, SN54LS47, 'LS48, 'LS49,
SN7446A, '47A; '48, SN74LS47, 'LS48, 'LS49
BCD-TO-SEVEN-SEGME.NT DECODERS/DRIVERS
•
All Circuit Types Feature Lamp Intensity Modulation Capability
DRIVER OUTPUTS
TYPE
TYPICAL
ACTIVE
OUTPUT
SINK
MAX
POWER
LEVEL
CONFIGURATION
CURRENT
VOLTAGE
DISSIPATION
PACKAGES
SN5446A
low
open~collector
40 rnA
30 V
320 rnW
J, W
SN5447A
low
open-collector
40 rnA
15 V
320 rnW
J, W
SN5448
high
2-kO pull-up
6.4 rnA
5.5 V
265 rnW
J,W
SN54LS47
low
open-collector
12 rnA
15 V
35 rnW
J, W
SN54LS48
high
2-kO pull-up
2 rnA
5.5 V
125rnW
J, W
SN54LS49
high
open-collector
4 rnA
5.5 V
40rnW
J, W
SN7446A
SN7447A
low
open-collector
40 rnA
320rnW
J, N
low
open-collector
40 rnA
30 V
15 V
320 rnW
J, N
SN7448
high
2-kO pull-up
6.4 rnA
5.5 V
265 rnW
J, N
SN74LS47
low
open-collector
24 rnA
15 V
35 rnW
J, N
SN74LS48
high
2-kO pull-up
6 rnA
5.5 V
125 rnW
J, N
SN74LS49
high
open-collector
8 rnA
5,5 V
40rnW
J, N
-4
-4
r-
logic symbols t
C
CD
'46A, '47A, 'LS47
'48, 'LS48
cS'
BINI7-5EG [>
ITl)
;;'1
BIN/7·SEG
IT2)
<
_ _ (4)
CD
BI/RBO
III
&
RBI
G21
G21
[T
0(6)
12
(11)
• 2O,21Q
d 20,21Q
B (1)
c (2)
13)
• 20,21 <;)
b 20,21 Q
A (7)
4
(13)
A (7)
b
Bill
(10)
• 20,21 Q
f 20,21<;)
(9)
C 121
(15)
0 16)
(14)
• 20,21<;)
'LS49
BIN/7-SEG
(T3)
Bi
A
B
15)
11)
c
0
14)
.iiiQ
b iiiQ
.iiiQ
diiiQ
• iiiQ
fiiiQ
giiiQ
(13)
(12)
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
2-176
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
• 20,21~
d 20,21~
12 b
111)
(10)
• 20,21 ~
f 20,21~
19)
115)
• 20,21~
(14)
SN5446A, '41A, '48, SN54LS47, 'LS48, 'LS49,
SN1446A, '47A, '48, SN74LS47, 'LS48, 'LS49
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
description
The '46A, '47A, and 'LS47 feature active-low outputs designed for driving common-anode LEOs or incandescent
indicators directly. The '48, 'LS48, and 'LS49 feature active-high outputs for driving lamp buffers or common-cathode
LEOs. All of the circuits except 'LS49 have full ripple-blanking input/output controls and a lamp test input. The 'LS49
circuit incorporates a direct blanking input. Segment identification and resultant displays are shown below. Display
patterns for BCD input counts above 9 are unique symbols to authenticate input conditions.
The' 46A, '47 A, '48, 'LS47...!.l1nd 'LS48 circuits incorporate automatic leading and/or traiJklll.:!!!Sle zero-blanking control
(RBI and RBO). Lamp test (LT) of these types may be performed at any time when the BI/RBO node is at a high level.
All types (including the '49 and 'LS49) contain an overriding blanking input (si), which can be used to control the
lamp intensity by pulsing or to inhibit the outputs. Inputs and outputs are entirely compatible for use with TTL logic
outputs.
The SN54246/SN74246 and '247 and the SN54LS247/SN74LS247 and 'LS248 compose the
tails and were designed to offer the designer a choice between two indicator fonts.
5
and the
'3 with
t~lb
,
Ie
NUMERICAL DESIGNATIONS AND RESULTANT DISPLAYS
-d-
SEGMENT
IDENTIFICATION
'48A, '47A, 1-S47 FUNCTION TAILE ITII
DECIMAL
OR
FUNCTION
LT
RII
D
C
I
0
H
H
L
L
L
L
H
1
H
L
L
L
H
H
2
H
H
L
L
H
L
L
H
H
L
3
H
H
4
H
L
H
L
L
H
H
INPUTS
A
5
H
X
X
X
X
X
L
H
L
H
6
H
x
L
H
H
L
H
7
H
L
H
H
H
H
H
L
L
L
H
H
L
L
H
H
H
L
H
L
H
H
L
H
H
H
H
H
L
L
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
81
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
RBI
H
L
L
L
L
L
L
LT
L
X
X
X
X
X
H
8
H
9
H
10
H
11
H
12
H
13
H
14
H
15
H
OUTPUTS
iii/iiiiO t
•
ON
OFF
ON
ON
OFF
ON
OFF
ON
ON
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
b
ON
ON
ON
ON
ON
OFF
OFF
ON
ON
ON
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON
•
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
d
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
OFF
ON
ON
OFF
ON
ON
OFF
OFF
OFF
ON
NOTE
•
ON
OFF
ON
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
f
g
ON
OFF
OFF
OFF
ON
ON
ON
OFF
ON
ON
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
ON
OFF
OFF
ON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
ON
1
2
3
4
H :: high level, L = low level. X = Irrelevant
NOTES: 1. The blanking input (ii) must be open or held at a high logic level when output functions 0 through 15 are desired. The
ripple-blanking input (RBIl must be open or high if blanking of a decimal zero is not desired.
2. When a low logic 18(1el is applied directly to the blanking input (eil. all segment outputs are off regardless of the level of any
other input.
tiiiRiO
3. When ripple-blanking input (RBi) and inputs A, B, C, and 0 are at a low level with the lamp test input high, all segment outputs
go off and the ripple-blanking output (FleD) goes to a low level (response condition).
4. When the blanking input/ripple blanking output (BTiFiBO) is open or held high and a low is applied to the lamp·test input, all
segment outputs: are on.
is wire· AND logic serving as blanking input fBi) and/or ripple-blanking output (RBO).
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DAlLAS, TEXA.S 75266
2-177
SN5446A, '47A, '48, SN54LS47, 'LS48, 'LS49,
SN7446A, '47A, '48, SN74LS47, 'LS48, .'LS49
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
'48, 'LS4B
FUNCTION TABLE (T21
DeCIMAL
OR
FUNCTION
0
1
2
3
4
5
6
7
8
9
-I
-I
r-
o
CD
10
11
12
13
14
15
BI
RBI
LT
INPUTS
LT
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
L
RBI
H
D
L
L
L
L
L
L
L
L
H.
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OUTPUTS
iii/RBOt
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
a
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
L
L
L
L
L
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
c
b
H
H
H
H
H
L
L
H
H
H
L
L
H
L
L
L
L
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
H
L
L
L
L
H
H
H
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
H
NOTE
e
d
H
f
H
L
L
L
H
H
H
L
H
H
L
L
H
H
H
L
L
L
H
H
L
H
L
L
L
H
L
H
L
H
L
L
L
H
L
L
L
H
L
H
H
L
H
H
L
H
L
H
H
L
H
H
L
L
L
H
9
L
L
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
L
H
1
2
3
4
H "" high level, L '" low level, X = irrelevant
NOTES: 1. The blanking input (81) must be open or held at a high logic level when output functions
through 15 are desired. The
ripple-blanking input (FfBi 1 must be open or high, if blanking of a decimal zero is not desired.
2. When a low logic level is applied directly to the blanking input (81), all segment outputs are low regardless of the level of any
a
<:
other input.
c:;'
3. When ripple-blanking input (RBi) and inputs A. 8, C, and D are at a low level with the lamp-test input high, all segment outputs
CD
1/1
t
Bl/Ri3'O
go lo,!" and the ripple-blanking output (RBO) goes to a low level (response condition).
4. When the blanking input/ripple-blanking output (Br/RBO) is open or held high and a low is applied to the lamp-test input, all
segment outputs are high_
is wire-AND logic serving as blanking input (61) and/or ripple-blanking output (Ri3QL
'LS49
FUNCTION TABLE (T31
DECIMAL
OR
FUNCTION
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BI
H
= high level,
NOTES:
OUTPUTS
INPUTS
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
C
L
L
L
L
H
H
H
H
L
X
NOTE
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H·
X
X
X
L
BI
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
a
H
L
H
H
L
H
L
H
H
H
L
L
L
H
L
L
L
b
H
H
H
H
H
L
L
H
H
H
L
L
H
L
L
L
L
c
H
H
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L
d
H
L
H
H
L
H
H
L
H
L
H
H
L
H
H
L
L
e
H
L
H
L
L
L
H
L
H
L
H
L
L
L
H
L
L
L
9
L
L
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
1
2
L"" low level, X '" irrelevant
1. The blanking input Cal> must be open or "held at a high logic level when output functions 0 through 15 are desired.
2. When a low logic level is applied directly to the blanking input ('B0,'alt segment outputs are low regardless of the level of any
other input.
2·178
f
H
L
L
L
H
H
H
L
H
H
L
L
H
H
H
L
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DAllAS, TEXAS 75265
SN5446A, '47A, '48, SN54LS47, 'LS48,
SN7446A, '47A, '48, SN74LS47, 'LS48
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
logic diagrams (positive logic)
'46A, '47A, 'lS47
"»-Do-,I",13~) OUTPUT
Bl/RBO
BLANKING
INPUT OR
RIPPLE·BLANKING
OUTPUT
OUTPUT
CI)
)'{)o-'1c:.:15",-1 OU~UT
II)
(.)
·S
LT
LAMp.TEST (3)
INPUT
II)
=--t==-___-=5U
RBI
(5)
RIPPLE·BLANKING
INPUT
).-[)o-'1c:.14::c1 OUTPUT
C
...I
lI-
'48, 'LS48
INPUT
A
INPUT
B
OUTPUT
INPUT
C
OUTPUT
b
INPUT
o
OUTPUT
d
Bl/RBO
~~:~:~ ~14~)+-__~
OUTPUT
RIPPLE·BLANKING
OUTPUT
OUTPUT
f
LT
LAMp·TEST (3)
INPUT
RBI
RIPPLE·BLANK ING .:;15::.l
INPUT
t
==___
-=:=!U
OUTPUT
Pin numbers shown are for 0, J, N, and W packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-179
SN54lS49. SN74lS49
BCD·TO·SEVEN~SEGMENT
DECODERS/DRIVERS
logic diagrams (continued)
'LS49
INPUT (4)
D
-91)o--fi---ttI:Hfil~
OUTPUT
d
Bi
BLANKING ..!:13:!.)_--l
INPUT
-t
-t
rC
(I)
<
ri"
(I)
(II
Pin numbers shown are for D. J, N, and W packages.
2-180
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
SN5446A, '47 A, '48,
SN7446A, '47 A, '48
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
schematics of inputs and outputs
'46A, '47A, '48
'46A, '47A, '48
EQUIVALENT OF EACH INPUT
EXCEPT Bl/RBO
EQUIVALENT OF Bl/RBO
Vee
vee3-Req
INPUT
--
SN54'/SN74':
Aeq '" 6 kH NOM
SN54L'/SN74L':
Req "" 8 kH NOM
'48
'46A, '47A
I/)
CI)
t>
TYPICAL OF OUTPUTS
a THRU 9
TYPICAL OF OUTPUTS
a THRU 9
'S;
CI)
------------~----~-Vee
------------.-~~-----Vee
2 U!
OUTPUT
NOM
C
...J
lI-
OUTPUT
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·181
SN54LS47, 'LS48, 'LS49, SN74LS47, 'LS48, 'LS49
BCD·TD·SEVEN·SEGMENTDECDDERS/DRIVERS
schematics of inputs and outputs
'LS47, 'LS48, 'LS49
'LS47, 'LS48, 'LS49
q
EOUIVALENT OF EACH INPUT
EXCEPT Bl/RBO
vee
EQUIVALENT OF Bl/RBO
Vee
Req
INPUT
LT and RBi
10 kn
__
NOM
('LS47, 'LS48), Req ~ 20 kn NOM
Bi ('LS49),
A. B. C, and 0:
Req ~ 20 kn NOM
Req
=:
25 kf2. NOM
'LS47
'LS48
TYPICAL OF OUTPUTS
aTHRUg
TYPICAL OF OUTPUTS
a THRU 9
----------~~--_.-----vee
------------e---~.-Vec
2kn
NOM
OUTPUT
OUTPUT
'LS49
TYPICAL OF OUTPUTS
aTHRU 9
--------------;~----
2-182
Vee
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5446A. SN5447A. SN7446A. SN7447A
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
Supply voltage, V CC (see Note 1)
Input voltage . . . . . . .
Current forced into any output in the off state
Operating free·air temperature range: SN5446A, SN5447 A
SN7446A, SN7447A
Storage temperature range
5.5 V
1 mA
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
NOTE1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN5447A
SN5446A
MIN
Supply voltage,
Vee
4.5
NOM MAX
5
MIN
4.5
5.5
5
5.5
30
SN7447A
SN7446A
NOM MAX
MIN
NOM MAX
4.75
V
V
40
40
rnA
-200
-200
~A
8
rnA
70
"e
a thru 9
40
40
High-level output current, IOH
BlfRBO
-200
-200
Low-level output current, IOL
BlfRBO
8
8
8
-55
125
4.75
5
30
On-state output current, 'O(on)
125
UNIT
15
5.25
a thru 9
-55
NOM MAX
5.25
5
15
Off-state output voltage, VO(oH)
Operating free-air temperature, T A
MIN
70
0
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
MIN
Typ:l: MAX UNIT
V
2
lfifRBO
lfifRBO
Low-level output voltage
Vec = MIN,
11--12rnA
Vee - MIN,
VIH-2V,
VIL =0.8V,
10H = -200
Vee = MIN,
VIH=2V,
VIL = 0.8 V,
10L = 8 rnA
~A
2.4
a thru 9
VO(on) On-state output voltage
a thru 9
II
Input current at maximum input voltage
IIH
High-level input current
Any input
except Bi fR BO
0.27
Low-level input current
except BifRBO
Short-circuit output current
lee
Supply current
0.4
V
250
~A
0.4
V
VIH-2V,
VIL = 0.8 V,
10 (on)
Vee" MAX,
VI = 5.5 V
1
rnA
Vee =MAX,
VI = 2.4 V
40
~A
Vee = MAX,
VI =O.4V
0.3
= 40 rnA
>
Q)
C
...J
V
Vee - MIN,
lI-
-1.6
rnA
-4
BI/RBO
lOS
V
VO(offl = MAX
Any input
IlL
-1.5
VIL =0.8V,
Any input
except Bi fR BO
V
3.7
Vee = MAX, VIH=2V,
10(0111 Off-state output current
0.8
en
Q)
.~
BlfRBO
-4
Vee = MAX
Vee - MAX,
See Note 2
I
I
SN54'
64
85
SN74'
64
103
rnA
rnA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operatin!=j conditions.
:1:AII typical values are at V CC = 5 V, T A '" 25"C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5
v.
switching characteristics, Vee = 5 V, T A = 25°e
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX UNIT
100
toll
Turn-off time from A input
ton
Turn-on time from A input
eL"15pF,
toft
Turn-off time from RBI input
See Note 3
ton
Turn-on time from RBI input
RL = 12011,
100
100
100
ns
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-183
SN5448, SN7448
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
absolute maximum ratings over operating free;air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
Operating free·air temperature range: SN5448
SN7448
Storage temperature range
7V
5.5V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN5448
MIN
Supply voltage, Vee
4.5
High-level output current, IOH
Low-level output current, IOL
CD
<
Cr
CD
5.5 4.75
5
NOM MAX
5
5.25
-400
-400
BIIRBO
-200
-200
a thru 9
6.4
6.4
BIIRBO
8
-55
8
125
0
70
UNIT
V
~A
rnA
"e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
r-
C
MIN
a thru 9
Operatjng free-air temperature, T A
-4
-4
SN7448
NOM MAX
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
TEST eONDITIONSt
Output current
VOL
Low-level output voltage
TYP:~ MAX UNIT
V
2
en
10
MIN
Vee = MIN,
11= -12 rnA
a thru 9
Vee =MIN,
VIH = 2 V.
2.4
4.2
BIIRBO
VIL =0.8V,
10H = MAX
2.4
3.7
Vee = MIN,
Va = 0.85 V,
-1.3
-2
a thru 9
II
Input current at maximum input voltage
IIH
High-level input current
Input conditions as for VOH
Vee- MIN,
VIH=2V,
VIL =0.8V,
10L = MAX
0.27
except Bi/RBO
Any input
except iil/RBO
Low-level input current
Short-circuit output current
Supply current
V
V
rnA
0.4
BIIRBO
V
1
rnA
Vee = MAX, VI = 2.4 V
40
~A
-1.6
BIIRBO
lOS
-1.5
Vee = MAX, VI = 5.5 V
except Bi/RBO Vee = MAX, VI = 0.4 V
lee
V
Any input
Any input
IlL
0.8
rnA
-4
-4
Vee = MAX
Vee - MAX.
See Note 2
l SN5448
I SN7448
53
76
53
90
rnA
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AIJ typical values are at Vee'=' 5 V, T A = 2S"C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.
switching characteristics, Vee
=
5 V, TA
=
25°e
PARAMETER
TEST CONDITIONS
tpHL
Propagation delay time, high-to-Iow-Ievel output from A input
tpLH
Propagation delay time. low-to-high-Ievel output from A ir:tput
eL = 15 pF,
tpHL
Propagation delav time. high-to-Iow-Ievel output from RBI input
See·Note 3
tpLH
Propagation delay time. low-to-high-Ievel output from RBI input
TYP
MAX
100
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-184
MIN
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
RL = 1 kU
100
100
100
UNIT
ns
ns
SN54LS47, SN74LS47
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . .
Input voltage . . . . . . . . . . . , . . .
Peak output current (tw';; 1 ms, duty cycle';; 10%)
Current·forced into any output in the off state
Operating free-air temperature range: SN54LS4 7
SN74LS47
Storage temperature range
7V
7V
200mA
,
. 1 mA
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
NOTE 1; Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS47
MIN
Supply voltage, Vee
NOM
4.5
SN74LS47
MAX
MIN
NOM
5.5
4.75
5
5
MAX
5.25
UNIT
V
Off-state output voltage, VOlolfl
a thru 9
15
15
On--state output current, 10(on)
a thru 9
12
24
Highwlevel output current, IOH
BI/RBO
-50
-50
IlA
Low-level output current. IOl
Operating free-air temperature, T A
BI/RBO
1.6
3.2
rnA
"e
-55
125
0
70
V
rnA
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONSt
VIL
High-level input voltage
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage Bl/RBO
VOL
Low-level output voltage Bl/RBO
VIH
10(011)
Off-state output current
VO(on)
On-state output voltage
SN54LS47
MIN
Vee = MIN,
11=-18mA
Vee - MIN,
VIH= 2V,
VIL = VIL max, 10H = -SO IlA
Vee- MIN,
II0L= 1.6 rnA
VIH = 2 V,
VIL = VIL max IIOL = 3.2 rnA
Vee= MAX,
a thru 9
2.4
a thru 9
Vee= MAX,
VI = 7 V
High-level input current
Vee = MAX,
VI=2.7V
except Bi IR BO Vee = MAX,
BI/RBO
VI = 0.4 V
ICC
Short-circuit
output current
Bl/RBO
Supply current
Vee = MAX,
V
0.4
V
4.2
0.25
0.4
0.35
0.5
250
250
0.25
CJ
·S
Q)
o
.....
lI-
0.4
0.25
0.4
0.35
0.5
IlA
V
-0.3
Vee = MAX
0.8
-1.5
Q)
V
Any input
lOS
0.7
-1.5
2.4
en
UNIT
V
V
4.2
VIH=2V,
Input current at maximum input voltage
TYPt MAX
2
0.25
VIL = VIL max, VO(off) = 15 V
Vee- MIN,
110(on) = 12 rnA
VIH = 2 V,
VIL = VIL max 110(on) = 24 rnA
II
Low-level input current
MIN
2
IIH
IlL
SN74LS47
TYPt MAX
See Note 2
0.1
0.1
rnA
20
20
IlA
-0.4
-0.4
-1.2
-1.2
-2
7
-0.3
13
rnA
-2
rnA
13
rnA
7
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:[: All typical values are at V CC '" 5 V, T A '" 2Su C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 v.
switching characteristics, Vee - 5 V, TA - 25°e
TEST CONDITIONS
toll
PARAMETER
Turn-off time from A input
ton
Turn-on time from A input
toll
Turn-Oil time from
ton
Turn-on time from RBI input, outputs (a-f) only
IiBi input,
MIN
TYP
MAX
100
eL = 1 5 pF, RL = 665 !l,
See Note 3
outputs (a-I) only
100
100
100
UNIT
ns
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-185
SN54LS48. SN74LS48
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
absolute maximum ratings over operating free-air temperature
ran~e
(unless otherwise noted)
Supply voltage, Vee (see Note 1)
..... .
Input voltage . . . . . . .
..... .
Operating free-air temperature range: SN54LS48
SN74LS48
Storage temperature range
7V
7V
-55°e to 125°e
oOe to 700e
-65°e to 1500 e
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS48
NOM
MIN
4.5
Supply voltage, Vee
High-level output current, IOH
Low-level output current, tOl
SN74LS48
MAX
MIN
NOM
5.5
4.75
5
5
MAX
5.25
a thru 9
--100
-100
BIIRBO
-50
-50
a thru 9
2
6
BI/RBO
3.2
1.6
-55
Operating free-air temperature, T A
125
0
70
UNIT
V
IlA
mA
"e
electrical characterIStiCS over recommended operatmg free-air temperature range (unless otherwise noted)
PARAMETER
-I
-I
VIH
High-level input voltage
VIL
Low-level input voltage
o
CD
VIK
I nput clamp voltage
VOH
High-level output voltage
CD
10
Output current
r-
s.
n
Vee - MIN,
II" -18mA
a thru 9 and
Vee - MIN,
VIH-2V,
ill/RBO
VIL" VIL max, 10H" MAX
Vee" MIN,
a thru 9
a thru 9
VIL" VIL max
Low-level output voltage
Vee
SN74LS48
MAX
MIN
TVPr.
MIN,
Input current at
Any input
maximum input voltage
except ill/BRa
Low~level
input current
V
0.8
V
-1.5
-1.5
V
2.4
4.2
2.4
4.2
V
-1.3
-2
-1.3
-2
mA
0.25
10L" 2 rnA
0.4
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
V
IOL"6rnA
0.4
0.25
10L" 1.6 rnA
V
10L" 3.2 rnA
Vee" MAX,
VI" 7 V
Vee" MAX,
VI" 2.7 V
except ill/RBO Vee" MAX,
VI "O.4V
0.1
0.1
mA
20
20
IlA
Any input
except ill/RBO
BIfRBO
Short~circuit
lOS
ICC
output current
UNIT
0.7
Any input
IlL
MAX
2
VIH"2V,
VIL" VIL max
High-level input current
TVPt
VIH" 2 V,
ill/R80
IIH
Vo - 0.85 V,
Input conditions as for VOH
Vee- MIN,
II
MIN
2
en
VOL
SN54LS48
TEST eONDITIONst
BT/RBO
Vee- MAX,
-0.4
-1.2
-0.3
vee: MAX
Supply current
-0.4
-1.2
-2
25
See Note 2
-0.3
38
mA
-2
rnA
25
38
rnA
TVP
MAX
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:1: All typical values are at V CC = 5 V, T A 25" C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 v.
switching characteristics, Vee
=
5 V, TA
= 25°e
TEST CONDITIONS
PARAMETER
=
tpHl
Propagation delay time,
high~to~low~level
output from A input
el
tplH
Propagation delay time,
low~to-high-Ievel
output from A input
See Note 3
=
15pF, Rl
tpHl
Propagation delay time, high-to-Iow-Ievel output (a-t onlyl from RBI input
eL
tPlH
Propagation delay time, low-to-high-Ievel output (a-t only) from RBI input
See Note 3
15 pF, Rl
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
2-186
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
= 4kll,
MIN
100
100
=6
kll,
100
100
UNIT
ns
ns
SN54LS49, SN74LS49
BCD-TO-SEVEN-SEGMENT-DECODERS/DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
.... .
Input voltage . . . . . . .
.... .
Current forced into any output in the off state
Operating free-air temperature range: SN54LS49
SN74LS49
Storage temperature range
7V
7V
.
. 1 mA
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS49
MIN
Supply voltage, Vee
NOM
4.5
SN74LS49
MAX
MIN
NOM
5.5
4.75
5
5
High-level output voltage, VOH
-55
5.25
UNIT
V
5.5
5.5
4
8
mA
70
"e
Low-level output current, IOl
Operating free-air temperature, T A
MAX
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
I "put clamp voltage
IOH
High-level output current
MIN
TYP:t.
SN74LS49
MAX
2
Vee
MIN,
0
Vee - MIN,
VIL
~
VIH - 2 V,
IIOL
VIH~2V,
Low-level output voltage
~
5.5 V
~
4 mA
MIN
MAX
UNIT
V
0.7
0.8
V
-1.5
-1.5
V
250
250
JJ.A
C/)
Q)
oSu
Q)
C
0.25
0.4
0.25
0.4
0.35
0.5
..J
V
VIL~VILmax IIOL~8mA
~
TYPt
2
11~-18mA
VIL max, VOH
Vee -- MIN,
VOL
SN54LS49
TEST CONDITIONSt
II
Input current at maximum input voltage
Vee
MAX,
VI
~
7V
0.1
0.1
IIH
High-level input current
Vee - MAX,
VI
~
2.7V
20
20
JJ.A
IlL
Low-level input current
Vee
MAX,
VI-O.4V
-0.4
mA
lee
Supply current
Vee - MAX,
See Note 2
-0.4
15
15
mA
~
8
8
mA
lI-
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:!:AII typical values are at Vee == 5 V, TA == 25"C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.
switching characteristics, Vee
=
5 V, TA
=
25°e
TEST CONDITIONS
PARAMETER
tpHL
Propagation delay time,
high~to~low~level
output from A input
eL
tPLH
Propagation delay time,
low~to~high~level
output from A input
See Note 3
tpHL
Propagation delay time. high-to-Iow-Ievel output (a-f only) from RBI input
eL
tpLH
Propagation delay time, low-to-high-Ievel output (a-f only) from RBI input
See Note 3
~
~
15 pF, RL
15 pF, RL
~
4 kll,
MIN
TYP
MAX
100
100
~
6 kll,
100
UNIT
ns
ns
100
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
TEXAS
II
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
2-187
-t
-t
rC
CD
<
C')
CD
VI
2-188
SN5450, SN7450
DUAL 2-WIDE 2-INPUT AND-DR-INVERT GATES (ONE GATE EXPANDABLE)
DECEMBER 19B3 - REVISED MARCH 1988
•
Package Options Include Plastic and
Ceramic DIPs and Ceramic Flat Packages
•
Dependable Texas Instruments Quality and
Reliability
SN5450 ... J PACKAGE
SN7450 ... N PACKAGE
(TOP VIEW)
lA
2A
Vee
18
IX
IX
description
20
2Y
These devices contain two independent 2-wide
.2-input AND-OR-INVERT gates with one gate
expandable. They perform the Boolean function
y = AB + CD with X and X left open.
SN5450 ... W PACKAGE
(TOP VIEW)
10
Vee
logic symbol t
18
(1)
Ie
IV
GNO
The SN5450 is characterized for operation over
the full military temperature range of - 55°C to
125°C. The SN7450 is characterized for
operation from O°C to 70°C.
lA
10
Ie
IV
GNO
18
&
;>1
(/)
28
(13)
lC
Q)
(.)
'>
logic diagram (positive logic)
Q)
10
lX IX
lX
lX
...I
lI-
2A
lA
28
2C
C
(4)
18
&
1V
(5)
lC
20
positive logic: V = AB + CO
(with X and X open)
10
t This symbol is in accordance with ANSI/IEEE Std 91·1984 and
IEC Publication 617-12.
Pin numbers shown are for J and N packages.
2A
28
2Y
PRODUCTION DATA d•• umonls ••nllin inf.rmallon
current IS af publication date. Products conform to
specifications par the tllftlS of Taxn Instruments
::=~~i~.i~:ru7i ~!:~:~ti:; lI~D:::::::':~ not
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-189
•
SN5450, SN7450
DUAL 2-WIDE 2-INPUTAND-OR-INVERT GATES (ONE GATE EXPANDABLE)
schematic (each AND-OR-INVERT gate)
A
8
C
D
OUTPUT
y
1X----------------~
1X _ _.:..;.;;..c...;"",,-:;";':'':'''':;:''''''.--J
' - - . . -.....-
Resistor values shown are nominal.
If expander is not used, leave X and X open.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
. Operating free-air temperature range: SN5450.................. . . . . . . . .. - 55 °e to 125°e
SN7450 .............................. ooe to 70 0 e
Storage temperature range ......................................... - 65 °e to 1 50 °e
NOTE 1: Voltage values are with respect to network ground terminal.
2-190
... TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012. OAllAS;TEXA$ 75265
SN5450. SN7450
DUAL 2·WIDE 2·INPUT AND·DR·INVERT GATES (ONE GATE EXPANDABLE)
recommended operating conditions
SN5450
Vee
Supply voltage
VIH
High-level input voltage
VIL
Law-level input voltage
10H
High-level output current
SN7450
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
Low-level output current
Operating free-air temperature
- 55
V
V
2
0.8
0.8
-0.4
-0.4
mA
16
mA
70
°e
16
10l
TA
UNIT
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
SN5450
TEST CONDITIONSt
MIN
VIK
Vee = MIN.
II = -12mA
VOH
Vee = MIN,
Vil = 0.8 V,
10H = -O.4mA
VOL
Vee= MIN,
VIH=2V,
10l = 16 mA
II
Vee = MAX,
VI- 5.5V
TYPt
SN7450
MAX
MIN
TYP*
2.4
2.4
3.4
0.2
MAX
-1.5
-1.5
0.4
3.4
0.2
1
UNIT
V
V
0.4
II
V
1
mA
IIH
Vee= MAX,
VIH = 2.4 V
40
40
IlL
Vee- MAX,
VIL-O.4V
-1.6
-1.6
"A
mA
IOS§
Vee = MAX
- 55
mA
Q)
lecH
Vce - MAX,
VI = 0 V
lecL
Vec= MAX,
See Note 2
'S
IX"
VXX - 0.4 V,
IOL - 16 mA
VOH'
vOl1
- 55
-18
+ IX = 0.41 mA,
RXX - 0,
10l - 16 mA
RXX = 0,
IOL-16mA
IX - 0.15 mA,
IX=-0.15mA,
10H = -O.4mA
IX - 0.27 mA,
IX - - 0.27 mA,
10H - -0.4 mA
IX + IX - 0.3 mA,
RXX = 138 n,
IOL = 16mA
IX + IX - 0.43 mA,
RXX - 130 n,
IOL-16mA
CJ
8
4
8
mA
7.4
14
7.4
14
mA
-3.1
mA
C
V
...J
1.1
1
2.4
CI)
4
-.2.9
IX + IX - 0.62 mA,
IX
VSEIO)1
-20
3.4
2.4
0.2
Q)
lI-
V
3.4
0.4
V
0.2
0.4
TYP
MAX
13
22
ns
8
15
ns
t For conditions shown as MIN or MAX, use the appropriate value specified under reco"mmended operating conditions.
t All typical values are at Vee = 5 V, T A = 25° c.
§ Not more than one output should be shorted at a time.
, Using expander inputs, Vee"" MIN, T A"" MIN, except typical values.
NOTE 2: All inputs of one AND gate at 4.5 V,all others at GNO.
switching characteristics. Vee
PARAMETER
tpLH
tpHl
= 5 V. TA = 25°e (see note 3)
FROM
TO
(INPUT)
(OUTPUT)
Any
Y
TEST CONDITIONS
RL - 4009,
Cl
Expander pins open
= 15pF
MIN
UNIT
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-191
-t
-t
rC
CD
<
C:;'
CD
r.n
2-192
SN5451. SN54LS51. SN54S51.
SN7451. SN74LS51. SN74S51
AND·pR·INVERT GATES
DECEMBER 1983 - REVISED MARCH 1988
• Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
SN5451 ... J PACKAGE
SN54S51 ... J OR W PACKAGE
SN7451 ... N PACKAGE
SN74S51 ..• 0 OR N PACKAGE
ITOPVIEW)
• Dependable Texas Instruments Quality and
Reliability
lA
2A
2B
2C
20
2Y
description
VCC
1B
NU
NU
The '51 and 'S51 contain two independent 2-wide
2-input AND-DR-INVERT gates. They perform the
Boolean function Y = AB + CD.
GNO
The 'LS51 contains one 2-wide 3-input and one
2-wide 2-input AND-DR-INVERT gates. They perform the
Boolean functions lY = 11A'lB'lC) + 11D·1E·1F)
SN5451 ... W PACKAGE
(TOP VIEW)
and 2Y = 12A·2B) + 12C·2D).
NU
NU
The SN5451, SN54LS51, and SN54S51 are
characterized for operation over the full military
temperature range of -55°C to 125°C. The SN7451,
SN74LS51 and SN74S51 are characterized for operation
from DOC to 70°C.
1A
VCC
1B
2A
2B
logic diagrams
10
1C
1Y
1D
1C
1Y
GNO
II
2Y
20
2C
'51, 'S51
1 A - - r - -.....
SN54lS51 ... J OR W PACKAGE
SN74lS51 ... 0 OR N PACKAGE
(TOP VIEW)
1B
1Y
1 C - - r - -.....
1A
2A
2B
2C
20
2Y
10
2A
2B
2Y
2C
GNO
VCC
1C
1B
1F
1E
10
1Y
20
NC- No internal connection
'lS51
NU - Make no external connection
1A
18
lC
1Y
10--·--...- ........
1E
IF
2A--..----........
28
2Y
2C
20
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~ai~:I~~ ~!:~:~ti:f :I~O::::~:~:-S~S not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-193
SN5451, SN54LS51, SN54S51,
SN7451, SN74LS51, SN74S51
AND·OR·INVERT GATES
SN54S51 •.• FK PACKAGE
ITOPVlEWI
SN54LS51 •.. FK PACKAGE
ITOPVIEW,
U
U
~~~~~
~~~~~
3 2 1 20 19
3
2
lB
NC
NC
2C
IF
NC
NC
20
IE
9 10111213
9 10 111213
>CU>U
NZZ--
>CU>C
NZZ~~
"
"
NC - No internal connection
NU - Make no external connection
logic symbols t
'51, '551
-f
-f
,...
lA
,.
C
lC
CD
10
(:;-
2A
<
28
CD
2C
(II
2D
111
&
'lS51
,.
1131
191
>1
191
1111
121
2A
&
151
&
>1
131
2.
141
2C
positive logic: Y = AB+CO
8<
1101
"IF
131
141
>1
(13)
10
&
8<
1121
lC
8<
1101
121
111
lA
>1
&
151
20
positive logic:
lY = (IA'IB'IC)+(10'IE'IF)
2Y = (2A'2B)+(2C'20)
tThesa symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
schematics
'51
A
8---t-+-'
c
0---1-.....
OUTPUT
y
'-<~""'-GNO
2-194
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN5451, SN54LS51, SN54S51
SN7451, SN74LS51, SN74S51
AND-OR-INVERT GATES
schematics
'lS51
INPUTS
v
A-.-----t4Ih
B
-1--.---:14'"
OUTPUT
y
D -------GND
'S51
r----~----~>---¥-vcc
v
A
B-+--"
OUTPUT
y
c
D-I---"
---_ _>---GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (See Note 1): '51, 'LS51, 'S51
Input voltage: '51, 'S51 ..
. ......... .
'lS51 ...
Operating free-air temperature range: SN54'
SN74' ..
Storage temperature range ......... .
7V
5.5 V
.' 7 V
- 55°e to 125°e
. .. ooe to 70 0 e
- 65°e to 150 0 e
NOTE 1: Voltage values are with respect to network ground terminaL
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-195
8N5451,8N7451
AND·OR·INVERT GATE8
recommended operating conditions
SN5451
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
MIN
NOM
4.5
5
SN7451
MAX' MIN
5.5
NOM
MAX
5
5.25
4.15
0.8
0.8
-0.4
-0.4
mA
16
mA
·e
16
IOL
Low-level output current
TA
Operating free-air temperature
125
-55
V
V
2
2
UNIT
10
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
CD
<
c:;.
CD
II = -12mA
VIL = 0.8 V,
IOH = -0.4 mA
VOL
II
Vee- MIN,
VIH-2V,
IOL = 16mA
Vee = MAX,
VI=5.5V
VOH
C
MIN
Vee = MIN,
Vee = MIN,
VIK
:::t
r-
SN5451
TEST CONDITIONS t
PARAMETER
SN7451
TVP* MAX
-1.5
2.4
3.4
0.2
MIN
TVP* MAX
-1.5
2.4
0.2
1
V
V
3.4
0.4
UNIT
0.4
V
1
mA
IIH
Vee - MAX,
VI =2.4V
40
40
IlL
Vee= MAX,
VI = 0.4 V
-1.6
~1.6
IlA
mA
IOS§
Vee=MAX
leeH
Vee= MAX,
VI =OV
leeL
Vee- MAX,
See Note 2
-20
-55
mA
4
8
4
8
mA
1.4
14
1.4
14
mA
- 55
-18
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
.; All typical values are at
Vee
= 5 V, T A
= 25° C.
~ Not more than one output should be shorted at a time.
NOTE 2: All inputs of one AND gate at 4.5 V. all others at GND.
UI
switching characteristics, Vee
PARAMETER
tpLH
tpHL
FROM
= 5 V, TA = 25°e (see note 3)
(INPUT)
TO
(OUTPUT)
Any
y
TEST CONDITIONS
RL = 400 n,
eL=15pF
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-196
'.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
TVP
MAX
13
22
8
15
UNIT
ns
SN54LS51, SN74LS51
AND·OR·INVERT GATES
recommended operating conditions
SN54LS51
Vee
Supply voltage
VIH
High-level input voltage
SN74LS51
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
VIL
Low-level input voltage
IOH
High-Ieve! output current
IOL
TA
Operating free-air temperature
2
Low-level output current
V
V
0.7
0.8
-0.4
-0.4
mA
8
mA
°e
4
125
-55
UNIT
70
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS t
MIN
Vce =MIN,
11=-18mA
VOH
VcC-MIN,
VIL -MAX,
10H = -0.4 mA
Vcc - MIN,
VIH =2V,
10l = 4 mA
10l =8 mA
Vcc =MIN,
VIH =2V,
II
VCC=MAX,
VI = 7 V
IIH
Vcc -MAX,
VI-2.7V
III
Vcc =MAX,
VI-O.4V
SN74LS51
MIN
TVP*
2.7
3.4
-1.5
VIK
Val
SN54LS51
TVP* MAX
2.5
3.4
0.25
-1.5
0.4
UNIT
V
V
0.25
0.4
0.35
0.5
0.1
V
0.1
mA
20
20
-0.4
-0.4
IlA
mA
-100
-20
MAX
IOS8
Vcc -MAX
-100
mA
ICCH
VCC =MAX,
VI =OV
0.8
1.6
-20
0.8
1.6
mA
ICCl
VCC -MAX,
See Note 2
1.4
2.8
1.4
2.8
mA
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
: All typical valuesareat Vee = 5 V, TA == 2SoC.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
NOTE 2: All inputs of one AND gate at 4.5 V. all others at GNO.
switching characteristics, Vee
PARAMETER
tplH
tpHl
= 5 V, T A =25°e (see note 3)
FROM
TO
(lNPUTI
(OUTPUTI
Any
V
TEST CONDITIONS
Rl =2 kn,
Cl = 15 pF
MIN
TVP
MAX
UNIT
12
20
ns
12.5
20
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-197
SN54S51,SN74S51
AND·OR·INVERTGATES
recommended operating conditions
SN54S51
SN74S51
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
-1
-1
mA
20
mA
70
"C
2
IOL
Low-level output current
TA
Operating free...air temperature
20
-55
125
V
V
2
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
-t
-t
rC
(I)
~.
o(I)
SN54S51
TEST CONDITIONS t
MIN
VIK
VCC =MIN,
11=-18rnA
VOH
VCC = MIN,
VIL=O.8V,
IOH = -1 rnA
VOL
VCC =MIN,
VIH=2V,
IOL = 20 mA
II
VCC - MAX,
VI-5.5V
SN74S51
TVPt MAX
MIN
TVPt MAX
-1.2
2.5
3.4
-1.2
2.7
3.4
UNIT
V
V
0.5
0.5
1
1
V
rnA
IIH
VCC -MAX,
VI-2.7V
50
50
p.A
IlL
VCC=MAX,
VI=0.5V
-2
-2
mA
IOS§
VCC -MAX
-100
rnA
ICCH
VCC =MAX,
VI = OV
ICCL
VCC =MAX,
See Note 2
-40
-100
-40
8.2
17.8
8.2
17.8
rnA
13.6
22
13.6
22
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
NOTE 2: All inputs of one AND gate at 4.5 V, all others at GND.
fII
switching characteristics, Vee = 5 V, TA = 25°e (see note 3)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
Any
Y
tpLH
tpHL
tpLH
TEST CONDITIONS
RL =280n,
CL = 15 pF
RL =280n,
CL = 50 pF
tpHL
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-198
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
TVP
MAX
UNIT
3.5
5.5
ns
3.5
5.5
ns
5
ns
5.5.
ns
SN5453. SN7453
EXPANDABLE 4-WIDE AND-DR-INVERT GATES
DECEMBER 1983-REVISED MARCH 1988
•
Package Options Include Plastic and
Ceramic DIPs and Ceramic Flat Packages
•
Dependable Texas Instruments Quality and
Reliability
SN5453 ... J PACKAGE
SN7453 ... N PACKAGE
(TOP VIEW)
Vcc
0
description
These devices are expandable 4-wide AND-ORINVERT gates. They perform the Boolean
function Y = AB + CD + EF + GH + X with
X = output of SN5460/SN7460.
NC
GND
H
logic symbol t
B
C
D
&
;>1
\131
121
&
131
141
H
x
X
G
A
Y
B
GND
NC
C
F
0
E
II
CI)
Q)
(,)
oS
Q)
schematic
&
0
v
(51
G
X
VCC
ttl
G
Y
SN5453 ... W PACKAGE
(TOP VIEW)
The SN5453 is characterized for operation over
the full military temperature. range of - 55°C to
125°C. The SN7453 is characterized for
operation from O°C to 70°C.
A
B
X
X
H
vcc
130 fI
(91
...J
~
~
&
\101
\111
\121
}
positive logic: Y
X
=
AS + CD + EF + GH + X
SN5460/SN7460
~ output of
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for J and N packages.
c
o
logic diagram (positive logic)
A
X-
OUTPUT
Y
E
F
X
B
C
D
v
G
H
E
x
X
' -........-GND
--------------~
G
H
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Taxas Instruments
:~~~~:~~i~·[::1~1~ ~:~::i:r :.~~e::::9t:~~ not
Resistor values shown are nominal.
If expander is not used, leave X and
TEXAS . "
INSTRUME~TS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
X open.
2-199
SN5453. SN7453
EXPANDABLE 4-WIDE AND-OR INVERT GATES
absolute maximum ratings over operating free-air te'mperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage ..................................................... : ..... " 5.5 V
Operating free-air temperature range: SN5453...... . . . . . . . . . . . . . . . . . . . .. - 55°C to 125 DC
SN7453 .............................. ooe to 70°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminals.
recommended operating conditions
SN5453
-I
-I
Vce
Supply voltage
V,H
High~level
input voltage
V,L
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
SN7453
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
2
V
V
v
0.8
0.8
-0.4
-0.4
rnA
16
mA
70
°c
16
125
- 55
UNIT
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
r0-
PARAMETER
C
CD
<
nCD
CIl
SN5453
TEST CONDITIONSt
V,K
Vce= MIN,
1,=-12mA
VOH
Vee = MIN,
V,L = 0.8
VOL
Vee- MIN,
V,H = 2 V,
MIN
TVP*
SN7453
MAX
MIN
TVP*
-1.5
v,
IOH=-0.4mA
2.4
3.4
0.2
IOL = 16 mA
2.4
MAX
V
0.4
V
v
3.4
0.4
0.2
UNIT
-1.5
Vec= MAX,
v, = 5.5 V
1
1
"H
"
Vec= MAX,
V'H=2.4V
40
40
I'A
"L
Vec= MAX,
V'L=0.4V
-1.6
-1.6
mA
IOS§
Vee= MAX
leCH
Vec= MAX,
V, =0
leCL
Vce= MAX,
See Note 2
1
VXX = 0.4 V,
IOL = 16 mA
IX+IX = 0.41 mA
RXX = 0,
IX+IX = 0.62 rnA,
RXX = 0,
IOL = 16 mA
'x-0.15mA,
IX--0.15mA,
IOH=-0.4mA
IX = 0.27 mA,
IX = - 0.27 mA,
IOH = - 0.4 mA
IX+IX - 0.3 mA,
Rl(X - 138 n,
IOL -16mA
'X+'X - 0.43 mA,
RXX = 130n,
'OL = 16 mA
IX
VSE(O)'
VOH'
VOL'
- 20
v
-55
-18
- 55
mA
4
8
4
8
mA
5.1
9.5
5.1
9.5
mA
-3.1
mA
- 2.9
L1
IOL = 16 mA
1
2.4
mA
3.4
2.4
0.2
V
3.4
0.4
0.2
V
0.4
V
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee = 5 v, TA = 25°C.
§ Not more than one output should be shorted at a time.
, Using expander inputs, Vee = MIN, T A = MIN, except typical values.
NOTE 2: All inputs of one AND gate at 4.5 V, all others at GND.
switching characteristics, Vee = 5 V, TA = 25°e (see note 3)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
tPLH
tPHL
Any
y
TEST CONDITIONS
RL = 400 n,
eL=15pF#
# Expander pins open.
NOTE 3: Load circuits and voltage waveforms are shown in Section 1 .
2-200
. . TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
TVP
MAX
UNIT
13
22
ns
8
15
ns
SN5454, SN54LS54, SN7454, SN74LS54
4·WIDE AND·DR·INVERT GATES
DECEMBER 19B3 - REVISED MARCH 1988
•
•
SN5454 ... J PACKAGE
SN7454 ... N PACKAGE
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
ITOP VIEW)
VCC
B
NU
NU
H
G
y
Dependable Texas Instruments Quality and
Reliability
F
NC
GNO
description
These devices contain 4-wide ANO-OR-INVERT gates.
They perform the following Boolean functions:
'54 Y = AB + CO + EF + GH
LS54 Y = AB + COE +FGH + IJ
SN5454 ... W PACKAGE
ITOPVIEW)
The SN5454 and SN54LS54 are characterized for
operation over the full military temperature range of
- 55
to 125
The SN7454 and SN74LS54 are
characterized for operation from 0
to 70
ac
ac.
ac
H
G
NU
NU
A
ac.
logic diagrams (positive logic)
'54
II
Y
GNO
NC
F
VCC
B
C
0
(/)
CD
E
(,)
A
SN54LS54 ... J OR W PACKAGE
SN74LS54 .•• D OR N PACKAGE
B
ITOP VIEW)
....
c~----'r--
o
A
VCC
B
C
J
F
0
E
G
Y
GNO
H
G
F
NC
y
E
'>CD
C
........
....
H
SN54LS54 ... FK PACKAGE
'LS54
(TOP VIEW)
A
B
U
U
U
al«Z>-'
c
o
3
2 1
I
NC
H
NC
E
y
F
G
H ~---''---_,
G
9
>OUUL&.
ZZZ
c.:I
NC - No internal connection
NU - Make no external connection
PRODUCTION DATA d••• m••ts •••tai. informati••
cunent as of publication date. Products conform tospecificatioRs par the terms of TIXI. Instruments
=:::~~i~'{::1~7i ~:::~ti:;
:.r=::A::' not
S
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TeXAS 75265
2-201
,S15454, SN54LS54, SN7454, SN74LS54
4·WIDE AND·OR·INVERT GATES
logic aymbola t
'54
A
B
c
0
111
'LS54
.. ,
&
A
(131
(21
B
C
&
(31
141
(81
D
y
H
(91
F
G
&
1101
H
(21
(31
&
(41
(61 Y
(91
&
1101
1111
(121
positive logic: Y
..,
&
(51
&
(5)
G
(11
= AB + CO + EF + GH
&
1131
positive logic: Y
= AB + COE + FGH + IJ
tThese symbols are in accordance with ANSIIIEEE Std 91·1984 and lEe Publication 617-12.
Pin numbers shown are for D, J, and N package. For the SN54LS54 only, they apply also for the W package.
schematics
-t
'64
~
r- -- - - -
r--'---'--1~VCC
c
I
130n
I
I
I
CD
<
(;'
CD
I
fI)
'LS64
......-VCC
-r=-=-=-::"==H_--~..-
20kn
Skn 120n
v
INPUTS
A--<_-...
B-h~H*f
I
I
OUTPUT
Y
Le.........~GND
......-1..--4>---- GND
Resistor values shown are nominal.
The portion of the circuits within the dashed lines is repeated for each additional 2- or 3-input AND section, as shown in the logic diagram
and logic symbols.
2-202
TEXAS ."
INSlRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75285
SN5454, SN7454
4·WIOE AND·OR·INVERT GATES
absolute maximum ratings over operating free· air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................. .
. 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 V
-55°e to 125°e
Operating free-air temperature: SN5454.
SN7454 .............. .
. .................. ooe to 70 0 e
Storage temperature range ....... .
- 65°C to 1 50 0 e
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN5454
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
SN7454
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
2
V
2
IOH
High-level output current
- 0.4
-0.4
mA
IOL
Low-level output current
16
16
mA
TA
Operating free-air temperature
70
°e
- 55
125
0
electrical characterics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
SN5454
TEST CONDITIONSt
MIN
VIK
Vee - MIN,
11- - 12 mA
VOH
Vee' MIN,
VIL' 0.8 V,
IOH' - 0.4 mA
VOL
Vee- MIN,
VIH - 2 V,
IOL - 16 mA
II
Vee' MAX,
MIN
TVPt
-1.5
2.4
3.4
0.2
2.4
UNIT
0.4
1
Vee' MAX,
VI-2.4V
40
40
IlA
Vee- MAX,
VI'0.4V
-1.6
- 1.6
mA
- 55
mA
4
8
4
8
mA
5.1
9.5
5.1
9.5
mA
- 20
Vee' MAX
Vee- MAX,
VI- 0 V
leeL
Vee' MAX,
See Note 2
- 55
-18
...J
V
IIH
IOS§
C
lI-
mA
IlL
leeH
'S:
Q)
V
V
3.4
0.2
1
VI' 5.5 V
MAX
-1.5
0.4
Q)
CJ
SN7454
TVPt MAX
II)
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vee = 5 V. T A == 25° C.
§Not more than one output should be shorted at a time.
NOTE 2: All inputs of one AND gate at 4.5 V. all others at GND.
i
switching characteristics. Vee
PARAMETER
tpLH
tpHL
=5 V. TA = 25°e (see note 3)
FROM
TO
(INPUT)
(OUTPUT)
Any
V
TEST CONDITIONS
RL'400fl,
CL'15pF
MIN
TVP
MAX
13
22
UNIT
ns
8
15
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section ,.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-203
SN54LS54. SN74LS54
4-WIDE AND-DR-INVERT GATES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ....................................................... 7 V
Input voltage .... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Operating free-air temperature: SN54lS54.................. . . . . . . . . . . . . . . . . . . .. - 55 DC to 125 DC
SN74lS54 ......................................... oDe to 70 De
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 DC to 1 50 DC
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating corlditions
SN54LS54
-t
-t
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
SN74LS54
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
2
2
V
IOH
High-level output current
-0.4
-0.4
mA
IOL
Low·level output current
4
8
mA
TA
Operating free-air temperature
70
°e
125
- 55
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
r-
PARAMETER
C
SN54LS54
TEST CONOITIONSt
MIN
18mA
(I)
VIK
Vee= MIN,
II
ri'
(I)
VOH
Vee=MIN,
VIL = MAX,
IOH = - 0.4 mA
Vee - MIN,
VIH - 2 V,
IOL = 4 mA
IOL-8mA
<
VOL
en
TYP*
Vee= MIN,
VIH - 2 V,
II
Vee = MAX,
VI = 7 V
SN74LS54
MAX
MIN
-1.5
2.5
3.4
0.25
2.7
0.4
TYP* MAX
- 1.5
3.4
V
V
0.25
0.4
0.35
0.5
0.1
UNIT
V
0.1
mA
IIH
Vee= MAX,
VI=2.7V
20
20
IlL
Vee = MAX,
VI-0.4V
-0.4
-0.4
!J.A
mA
IOS§
Vee = MAX
leeH
Vee = MAX,
VI =OV
leeL
Vee = MAX,
See Note 2
- 20
-100
mA
0.8
1.6
0.8
1.6
mA
1
2
1
2
mA
-100
- 20
as M IN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee"" 5 V, TA "" 25° C.
t For conditions shown
§Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second,
NOTE 2: All inputs. of one AND gate at 4.5 V. all others at GND,'
switching characteristics, Vee'" 5 V, TA '" 25°e (see note 3)
PARAMETER
tpLH
FROM
TO
(INPUT)
(OUTPUT)
Any
TEST CONDITIONS
y
RL = 2 k!1,
eL=15pF
tPHL
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
2-204
.
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
UNIT
TYP
MAX
12
20
ns
12.5
20
ns
SN54LS55, SN74LS55
2·WIDE 4·INPUT AND·DR·INVERT GATES
DECEMBER 1S83-REVISED MARCH 1S88
•
Package Options Include "Small Outline"
Packages. Ceramic Chip Carriers and Flat
Packages. and Plastic and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54LS55 ... J OR W PACKAGE
SN74LS55 ... 0 OR N PACKAGE
(TOP VIEW)
description
These devices contain 2-wide 4-input AND-ORINVERT gates. They perform the Boolean function
Y = ABCD + EFGH.
The SN54LS55 is characterized for operation over the
full military temperature range of - 55 DC to 125 DC.
The SN74LS55 is characterized for operation from
DoC to 70 D C.
SN54LS55 ... FK PACKAGE
(TOP VIEW)
u
B
C
0
E
F
G
H
(1)
U
U
m«z>:t:
3 2
logic symbol t
A
VCC
H
G
F
E
B
C
D
NC
NC
GND
&
;;'1
(2)
en
Q)
(3)
U
'S
(4)
(10)
(8)
Q)
y
o
UCU:>U
ZZZ
&
Z
C!l
(11)
(12)
....I
lI-
NC - No internal connection
(13)
schematic
positive logic: Y = ABCD + EFGH
.-----~------_.--.__VCC
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and
lEe Publication 617-12.
.
Pin numbers shown are for D. J. N. and W packages.
logic diagram
-----_---GND
Resistor values shown are nominal.
PRODUCTION DATA .......nb .....in inf.....Ii.n
.......1 .. 0' publl..ti•• d.... Prod......nflrm t.
"Hificalio.. per tho t.rlll of T.III l.strulI.nb
=:=i~.[n':I~'li =:~I:: :'I":::~~~ not
TEXAS ,.,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·205
SN54LS55. SN74lS55
2·WIDE 4·INPUT AND·OR·INVERT GATES
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Operating free·air temperature: SN54LS55...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
SN74LS55 ......................................... ooe to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditic;ms
SN54lS55
-4
-4
r-
MIN
4.5
Vee
Supply vol tage
VIH
High-level input voltage
Vil
Low-level input voltage
IOH
High-level output current
SN74lS55
NOM
MAX
MIN
NOM
MAX
5
5.5
4.75
5
5.25
2
Low-level output current
Operating free-air temperature
V
V
2
0.7
0.8
-0.4
- 0.4
mA
8
mA
70
"e
4
IOl
TA
UNIT
-55
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
C
~
<
n'
ell
MIN
VIK
Vee = MIN,
11=-18mA
VOH
Vee= MIN,
Vil - MAX,
IOH = - 0.4 mA
Vee = MIN,
VIH=2V,
IOl =4mA
IOl=8mA
Val
~
SN54lS55
TEST eONDITIONSt
Vee- MIN,
VIH - 2 V,
II
Vee= MAX,
VI = 7 V
IIH
Vee= MAX,
III
Vee= MAX,
lOSS
Vee= MAX
leeH
Vee= MAX,
Vee= MAX,
leel
SN74lS55
TYPt MAX
MIN
TYPt
2.7
3.4
-1.5
-1.5
2.5
3.4
0.25
MAX
0.25
0.4
0.35
UNIT
V
V
0.4
0.5
v
0.1
0.1
mA
VI = 2.7 V
20
VI = 0.4 V
-0.4
20
- 0.4
-100
0.8
0.4
0.7
1.3
I'A
mA
- 20
-100
0.4
VI- 0 V
See Note 2
0.7
-20
0.8
1.3
mA
mA
mA
t For conditions shown as MIN 01; MAX, use the appropriate value specified under recommended operating conditions.
t
All typical values are at Vee = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
NOTE 2: All outputs of one AND gate at 4.5 V, all others at GNO.
switching characteristics, Vee = 5 V, TA·= 25°e (see note 3)
PARAMETER
tPLH
tPHl
FROM
(INPUT)
Anv
TO
(OUTPUT)
Y
TEST CONDITIONS
RL = 2 kn,
eL = 15pF
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-206
TEXAS
'If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
TYP
MAX
12
20
12.5
20
UNIT
ns
ns
SN54LS56. SN54LS57. SN74LS56. SN74LS57
FREQUENCY DIVIDERS
DECEMBER 1983-REVISED MARCH 1988
• 'LS56 Performs 50 to 1 Frequency Division
(5 to 1, 5 to 1, and 10 to 1)
SN54LS56. SN54LS57 ••• JG PACKAGE
SN74LS56, SN74LS57 .•. JG OR P PACKAGE
• 'LS57 Performs 60 to 1 Frequency Division
(6 to 1, 5 to 1, and 10 to 1)
(TOPVIEWI
• Available in P or JG package (two P or JG
Packages Fit in a Single 16-pin Socket)
C L K B [ 1 8 Oc
VCC 2
7 OB
OA
3
6 CLR
GND 4
5 CLKA
• Maximum Clock Frequency 25 MHz Typical
FOR CHIP CARRIER INFORMATION. CONTACT THE FACTORY.
description
These frequency dividers are particularly useful in generating one second or one hour timing pulses from 50 Hz (European
standard frequencyl or 60 Hz (United States standard frequency). 50 to 1 frequency division is accomplished in the 'LS56 by
connecting output OA to input CLKB. 60 to 1 frequency division in the 'LS57 is accomplished in the same way. More universal capabilities are evidenced by the 25 MHz typical f max and the almost limitless frequency division possibilities when used in
cascade. Two 'LS56 packages may be interconnected to give frequency division of 2500 to 1. 625 to 1.100 to 1. etc. Two
'LS57 packages can be connected to generate frequency divisions of 3600 to 1. 1800 to 1. 900 to 1 etc.
The 'LS56 and 'LS57 frequency dividers consist of three separate counters. A. B. and C on a single monolithic substrate.
The A counter divides by 5 to 1 in the 'LS56 and by 6 to 1 in the ·LS57. The B counter divides by 5 to 1 in both devices and is
internally tied to the C counter which divides by 2 to 1. The resulting C counter output is 10 to 1. Both the 'LS56 and 'LS57
feature a clear pin which is common to all three counters. A. B. and C. When the clear pin is low. the counters are enabled.
When the clear is high. the counters are disabled and their outputs are set to a low-level.
All three counters. A. B. and C trigger on the high-to-Iow transition of the clock input. All output waveforms are symmetrical
except for the 5 to 1 outputs (A and B of the 'LS56 and B of the 'LS57). See the output waveform drawings below.
input and output waveforms
logic diagram (positive logic)
(I)
Q)
(,)
'S;
Q)
o
...J
~
~
ClK
!l'-_ _ _ _~!l'__ __
QA·lS56 _ _ _ _ _.....
QA·lS57_ _ _ _ _..J
L
QB75 _ _ _ _~~r_l'__
_ _ _ _.....r_l'__ __
Dc 71_0_ _ _ _ _ _ _-'
ClR~'_
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
logic symbols t
'lS56
'LS57
• 'LS56 .;.5
'lS57 .;. 6
CLKA
eLKB
(3'
°A
(7J
(81
OB
' - -_ _=~--OC
tThese symbols are in accordance with ANSI/IEEE Std 91·1984
and IEC Publication 617·12.
PRODUCTION DATA doc.monts contoin informotion
curraot as of publication date. Products conform to
specifications per the tarms of Texas Instruments
:~~~~:~~i~a[::I~~e ~!::i:~ti:r :,~o:=::::t::-a~ not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-207
SN54LS56. SN54LS57. SN74LS56. SN74LS57
FREQUENCY DIVIDERS
schematics of inputs and outputs
EauivAlENT OF
ClKINPUTS
Vee-------
Vee---~~-
9kn NOM
5kn NOM
INPUT ...-11+4>--_
TYPICAL OF All OUTPUTS
EQUIVALENT OF
CLEAR INPUT
INPUT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
-f
-f
Supply voltage, Vec (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage: elR ........................................................................... 7 V
ClKA, ClKS .............................................................. '" . 5.5 V
Operating free-air temperature range: SN54lS' .......................................... _55°e to 125°C
SN74lS' ............................................ _o°c to 70°C
Storage temperature range ........................................................... _65 d e to 150°C
r-
C
CD
<
C;"
CD
NOTE 1: Voltage values are with respect to network ground terminal.
CfI
recommended operating conditions
SN74lS'
SN54lS'
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
fclock
Clock frequency
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
2
0.7
1
8
0
15
0
50
tr,tf
Rise and fall time of clock
'w
Pulse width of clock or clear
30
30
Clear inactive state set-up time
25
25
Operating free-air temperature
-55
'su
TA
2-208
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
125
0
UNIT
V
V
0.8
1
16
15
50
V
mA
mA
MHz
ns
ns
ns
70
'e
SN54LS5l SN54LS57, SN74LS56, SN74LS57
FREQUENCY DIVIDERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH
II =-18mA
VCC =MIN,
VIH =2V,
VCC=MIN,
CLKA,CLKB
CLR
CLKA,CLKB
IIH
VCC= MIN,
VIL = MAX
VOL
II
SN54LS'
TEST CONOITIONSt
CLR
CLKA;CLKB
VIH =2 V,
MIN
IOH = -1 mA
IOL=16mA
VCC = MAX
VI =5.5V
V =7 V
3.4
0.25
VI =2.7 V
VCC =MAX,
CLR=OV,
VI =O.4V
IOS§
CLR =OV,
VO=OV
ICC
VCC-MAX,
See Note 2
CLR
2.5
IOL =8 mA
VCC =MAX,
IlL
SN74LS'
MAX
MIN
TYPt MAX
-1.5
VIL =MAX
VCC=MAX,
TYPt
0.4
3.4
0.4
0.35
0.5
0.2
0.2
0.1
0.1
80
BO
20
20
- 3.2
-3.2
-100
-0.2
-20
30
17
V
V
0.25
-0.2
-20
17
t For conditions shown as MIN or MAX. use the appropriate value specified
t All typical values are at Vee = 5 V. T A = 2SoC.
-1.5
2.7
UNIT
V
mA
IlA
mA
-100
mA
30
mA
under recommended operating conditions.
§ Not more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured by applving 4.5 V to the CLR pin with all other inputs grounded and the outputs open.
fII
CI,)
(,)
'>
switching characteristics, Vee'" 5 V, T A'" 25°e (see note 3)
PARAMETER
fmax
f max
tpLH
tpHL
tPLH'
tPHL'
tpLH
FROM
(INPUT)
CLKA
CLKB
CLKB
CLKB
TO
(OUTPUT)
TEST CONOITIONS
°A
°B,OC
CI,)
'LS56
MIN
TYP
15
25
15
25
°B
°c
RL = 1 kn,
CL = 30 pF
MIN
TYP
15
25
15
25
MAX
UNIT
MHz
MHz
15
8
15
ns
14
25
14
25
ns
18
30
18
30
ns
24
35
20
25
30
30
30
24
35
ns
14
25
ns
12
°A
14
°A
17
tpHL
CLR
CLR
°B
17
tpHL
CLR
Oc
17
tpHL
'LS57
MAX
8
CLKA
tpHL
o
1B
30
ns
17
30
ns
17
17
30
30
nS
...........J
ns
.Times measured from elKS to output QC are taken with output aS unloaded.
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-209
2-210
SN54S64. SN54S65.
SN74S64. SN74S65
4·2·3·2 INPUT AND·OR·INVERT GATES
DECEMBER 1983 - REVISED MARCH 1988
• Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
SN54S64, SN54S65 .•• J OR W PACKAGE
SN74S64, SN74S65 ••. 0 OR N PACKAGE
(TOPVIEWI
• Dependable Texas Instruments Quality
and Reliability
VCC
D
C
B
K
F
G
H
description
These devices contain 4-2-3-2 input AND-OR-INVERT
gates. They perform the Boolean function
Y = ABCD + EF + GH( + JK. The 'S64 has totem-pole
outputs and the 'S65 has open-collector outputs.
GNO
SN54S64. SN54S65 ... FK PACKAGE
(TOPVIEWI
The SN54S64 and the SN54S65 are characterized for
operation over the full military temperature range of
- 55°C to 125°C. The SN74S64 and the SN74S65 are
characterized for operation from 0 °C to 70°C.
3
logic symbols t
B
C
0
E
F
G
H
(11
&
;;'1
(111
B
c
0
E
F
G
6
7
H
B
II)
CD
(.)
'S:
CD
C
(131
(21
.....
....
....
&
(31
(41
NC - No internal connection
y
&
logic diagram (each devicel (positive logicl
(51
(91
A
G
NC
C
NC
B
NC
K
(121
A----.r--....
B
_____
(61
K
1 20 19
5
'S64
A
2
C
o
&
~_,
(101
E--~'----"'"
(11
'S65
y
&
G - _ r - - -.....
H
1111
(121
(131
(21
&
K
(31
(41
&
(5)
H
(61
(9)
K
&
(101
tThese symbols are in accordance with ANSI/IEEE Std 91-1984
and lEG Publication 61 7 -12.
Pin numbers shown are for 0, J, N, and W packages.
PRODUCTION DATA documlnts contlin informltion
cumnt 8S of publication date. Products conform to
specifications par the terms of Texas Instruments
::=:~~i~8{::1~7~ ~:~::i:; :.~o:::::.::.s
not
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-211
SN54S64, SN54S65
SN74S64, SN74S65
4·2·3·2 INPUT AND·OR·INVERT GATES
schematics (each gate)
'S64
'S65
r--.--~~----vcc
r--------.-----~-1>--'vcc
A
A
B-Hp--'
B
C
C--H4
0,---1-+-+-+
OUTPUT
y
-1--+--.--'
o ---1H-I-+'
OUTPUT
y
K----+-+
RnJl1;or values shown are nominal and In ohms.
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Off-state output voltage, 'S65 . _........ _.. _ .. _................................................. 7 V
Operating free-air temperature range: SN54' ............................................ _ -55°C to 125°C
SN74' ................................................ aOe to 7aoe
Storage temperature range ......................................................... , - 65°C to 15aoC
NOTE 1: Voltage values are with respect to network ground terminal.
2-212
" TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
8N54864,8N74864
4·2·3·2 INPUT AND·OR·INVERT GATE8
recommended operating conditions
SN54S64
SN74S64
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
V
Vee
Supply vollage
VIH
High-level input voltage
VIL
Low-Ieve I i "put va Itage
0.8
0.8
V
IOH
High-level output current
-1
-1
mA
IOL
TA
20
Operating free-air temperature
mA
°e
2
V
2
Low-level output current
20
-55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Vee =MIN,
II = -18 mA
VOH
Vee-MIN,
VIL =0.8V,
IOH = -1 mA
VOL
II
Vee=MIN,
VIH -2V,
IOL = 20mA
Vee -MAX,
VI =5.5V
IIH
Vee =MAX,
VI =2.7V
IlL
IOS§
Vee=MAX,
VI-0.5V
MIN
TYP*
2.5
3.4
VI = 0
leeL
Vee =MAX,
VI-4.5V
MIN
TYP*
2.7
3.4
MAX
-1.2
UNIT
V
V
V
0.5
0.5
1
1
mA
50
50
-2
-2
/lA
mA
-100
mA
7
12.5
7
12.5
mA
8.5
16
8.5
16
mA
-40
Vee -MAX,
MAX
-1.2
Vee =MAX
leeH
SN74S64
SN54S64
t
-100
-40
typical values are at Vee 5 V. T A :s 25° C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
::::0
..J
lI-
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
'pLH
U
Q)
:t All
'PLH
tpHL
Q)
'S;
o
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PARAMETER
en
FROM
TO
(INPUT)
(OUTPUT)
Any
TEST CONDITIONS
RL = 280
n,
eL = 15 pF
RL = 280
n,
eL = 50 pF
Y
'pHL
MIN
TYP
MAX
3.5
5.5
3.5
5.5
UNIT
ns
ns
5
ns
5.5
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-213
SN54S64, SN14S64
4·2·3·2 INPUT AND·OR·INVERT GATES
recommended operating conditions
SN74S65
SN54S65
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
VOH High-level output voltage
5.5
5.5
V
Low-level output current
20
125
20
mA
°e
Vee
Supply wltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOL
TA
-55
Operating free-air temperature
V
2
2
70
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VIK
IOH
-I
-I
r-
i'<
c:r
C1)
SN54S65
TEST CONDITIONSt
VCC
= MIN,
II
=
MIN
-18mA
VIL - 0.8 V,
VOH - 5.5 V
= MIN,
= MIN,
VIL = 0.7 V,
VOH = 5.5 V
VCC
Vec
IIH
VCC
IlL
VCC
ICCH
Vec - MAX,
ICCl
Vee
Vee - MAX,
= MAX,
= MAX,
= MAX,
VIH
= 2 V,
SN74S65
MAX
MIN
TYP*
MAX
1.2
VCC - MIN,
VOL
II
TYP*
IOL
1.2
0.25
0.25
= 20 mA
0.2
0.4
0.2
0.4
V
mA
V
VI - 5.5 V
1
= 2.7 V
= 0.5 V
50
50
p.A
-2
-2
mA
VI
VI
VI - 0
VI = 4.5 V
1
UNIT
mA
6
11
6
11
mA
8.5
16
8.5
16
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
~AII typical values are at Vee = 5 V, TA = 25 o e.
o
switching characteristics, Vee
PARAMETER
=5 V, TA =25°e (see note 2)
FROM
TO
(lNPUTI
{OUTPUTI
tpLH
tpHL
tpLH
tpHL
Any
TEST CONDITIONS
RL =280n,
eL = 15 pF
RL =280 n,
CL = 50 pF
Y
NOTE 2: load circuits and voltage waveforms are shown in Section 1.
2-214
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
MIN
TYP
MAX
2
5
7.5
UNIT
ns
2
5.5
8.5
ns
8
ns
6.5
ns
SN54LS68, SN54LS69, SN74LS68, SN74LS69
DUAL 4·BIT DECADE OR BINARY COUNTERS
DECEMBER 1983 - REVISED MARCH 1988
5N54LS68, SN54LS69 , .. J PACKAGE
SN74LS68, SN74LS69 ... 0 OR N PACKAGE
• Heavy Duty Outputs IOL Rated at
8mA/16 mA
(TOP VIEWI
• Counter One of Either 'LS68 or 'LS69 Has
Individual Clicks for the A Flip·Flop
lCLKA
laB
lao
lClR
• Direct Clear for Each 4-Bit Counter
• Guaranteed Maximum Count Frequency is 50
MHz for 'LS69 and 40 MHz for 'LS68
VCC
lCLKB
lOA
lac
200
2CLR
20B
2CLK
20c
NC
description
Each of the 'LS68 and 'LS69 circuits contain two fourbit counters. The 'LS68 is a dual decade counter, while
the 'LS69 is a dual binary counter. Counter number one
of both the 'LS68 and 'LS69 has two clock pins. Clock 1
is for the A flip-flop, while clock 2 is for the B, C, 0 flipflops. Counter one of the 'LS68 can perform bi-quinary
counting. All lOA outputs are rated with sufficient IOL
to drive clock 2 while maintaining a full fan-out.
SN54LS68, SN54LS69 ... FK PACKAGE
(TOP VIEWI
100
lCLR
NC
All clocks trigger on the high-to-Iow transition of the
clock pulse. All counters have direct overriding clear pins
which, when low, reset OA, OB, OC, and 00 low
regardless of the state of the clock.
The SN54LS68 and SN54LS69 circuits are characterized for operation over the full military temperature range
of -55°C to 125°C. The SN74LS68 and SN74LS69
circuits are characterized for operation from O°C to 70 D C
NC - No internal connection
logic symbols t
'LS69
'LS68
CTROIV 2
CTROIV 2
[>
[>
1141 lOA
0
o
(21 laB
2
0
(31 lao
2
171 20A
o
(101 20B
2ClK
CT
3
(21 laB
(131 lOC
1131 lac
(31 lao
(71 20A
(10120B
CT
151 20C
(121 20 0
3
(51 20C
(12) 20 0
tThese symbols are in accordance with ANSI/IEEE SId 91-1984 and lEe Publication 617-12.
Pin numbers shown are for D, J, and N packages.
PRODUCTION DATA documont. contoin in'ormation
currant as of publication date. Products conform to
specifications par the terms of Texas Instruments
:::::~~i~ai~:1~1e ~!:~~~ti:; :'1U::::~~:~~s not
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-215
SN54LS68, SN54LS69, SN14LS68, SN14LS69
DUAL 4·B11 DECADE OR BINARY COUNTERS
count sequence tables
'LS68 DECADE COUNTER
'LS68 DECADE COUNTER
'LS69 BINARY COUNTER
aco COUNT SEQUENCE
(See Note 1)
al·QUINARY SEQUENCE
(See Note 2)
aCD COUNT SEQUENCE
(See Note 3)
Applies to Counters 1 & 2
COUNT
0
1
2
3
4
5
6
COUNT
Qa
L
QA
L
H
1
L
L
2
L
L
L
H
H
L
H
H
3
L
L
H
H
H
L
L
4
L
H
L
L
L
L
L
5
L
H
L
H
L
L
L
H
L
L
4
L
5
6
7
8
9
H
1
L
L
2
L
H
H
3
H
L
H
L
L
H
L
L
L
L
H
L
L
L
L
L
L
H
H
L
L
H
H
H
8
9
H
L
L
L
H
L
L
H
-4
-4
0
H
L
QA
L
L
H
L
L
H
6
L
H
H
L
H
L
H
L
7
L
H
H
H
H
L
H
H
H
L
L
L
L
8
9
10
11
12
13
14
15
H
L
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
L
H
H
L
H
H
1. Output 1QA is connected to 1CLK2 for BCD count.
'2. Output tQA 1$ connected to 1eLK1 for bi-quinary
count.
r-
OUTPUT
QC
L
Qa
L
0
Qa
L
COUNT
QD
L
Qc
L
QD
L
Oc
7
NOTES:
OUTPUT
QA
L
QD
L
Applies to Counters 1 & 2
Applies to Counter 1 only
OUTPUT
3. Output tQA is connected to 1 CLK2 for binary count.
C
H
H
H
L
H
H
H
H
CD
<
0'
CD
(I)
schematics of inputs and outputs
EQUIVALENT OF CLOCK
INPUTS
EQUIVALENT OF CLR
INPUTS
TYPICAL OF ALL
OUTPUTS
--------- VCC
----4.---
10kn NOM
VCC
120 n NOM
INPUT-......-I.
INPUT
'----4....- OUTPUT
lCLK1,2CLK
Req NOM
4.5k n
lCLK2
7.5k n
INPUT
2-216
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265
SN54LS68. SN54LS69. SN74LS68. SN74LS69
DUAL 4·BI1 DECADE OR BINARY COUNTERS
logic diagrams (positive logic)
, LS68
'LS69
lCLKl -'-'-ll1c--_ _ _-d>
lClK2
...:.:.:"-----+--d>
lOe
lQO
I/)
Q)
(,)
"S
Q)
0
..J
lI2QA
2CLK
(91
2elR
(11}
Pin numbers shown are for 0, J, and N packages.
-Ii}
TEXAS
INSTRUMENTS
POST OFFICE 130X 655012 • DALLAS. TEXAS 75265
2·217
SN54LS68, SN54LS69, SN74LS68, SN74LS69
DUAL 4·BIT DECADE OR BINARY COUNTERS
absolute maximum ratings over operatingfree-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 4) ............................................................... 7 V
Input voltage: Clear inputs .................................................................... 7 V
Clock inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range: SN54LS' .......................................... - 55" C to 125"C
Sm4L~ .............................................. ~Cm7~C
Storage temperature range .......................................................... - 65" C to 150" C
NOTE 4: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54lS'
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
VIH
High-level input voltage
Vil
Low-level input voltage
0.7
0.8
V
IOH
High-level output current
-1
-1
rnA
IOl
Low-level output current
16
rnA
f max Clock frequency
2
1CLK2
1CLK2
tw
Pulse width
2CLK
0
50
0
50
'LS68
0
20
0
20
0
25
0
25
'LS68
0
40
0
40
0
50
0
50
'LS69
10
10
'LS68
25
25
'LS69
20
20
'LS68
13
13
10
10
'LS69
CLEAR
15
15
25
tsu
Clear inactive-state set-up time
25
TA
Operating free-air temperature
- 55
2-218
V
'LS69
1CLK1
<
2
8
2CLK
CD
en
V
VCC
rC
c:r
CD
UNIT
Supply \/'oltag"e
1ClK1
~
~
SN74lS'
MIN
. TEXAS.Jf
'INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
125
0
MHz
ns
ns
70
"C
SN54LS68, SN54LS69, SN74LS68, SN74LS69
DUAL 4·BIT DECADE OR BINARY COUNTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Vec~
VIK
MIN.
VCC= MIN.
VOH
VCC· MIN.
II
Vee~
CLR
CLK
IIH
VIH = 2 V.
VIL· MAX
CLK
CLR
MIN
TVP*
2.5
3.4
10H= -1 mA
0.25
10L = 8 mA
leLK2
t
TVPt
2.7
3.4
MAX
-1.5
0.4
0.25
0.4
0.35
0.5
0.1
0.1
Vce· MAX.
VI = 7 V
0.1
0.1
VCC= MAX.
VI = 2.7 V
Vee· MAX.
VI=0.4V
Vce· MAX.
Vo=OV
VCC· MAX.
see Note 5
-20
40
40
20
20
-2
-2
-1.2
-1.2
-0.2
-0.2
-100
36
- 20
54
36
UNIT
V
V
VI = 5.5 V
MAX.
CLR
10S*
ICC
MIN
10L -16mA
lCLK1.2CLK
IlL
SN74LS'
MAX
-1.5
11=-18mA
VIH=2V.
VIL = MAX
VOL
SN54LS'
TEST eONDITloNst
V
mA
I'A
mA
-100
mA
54
mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee"" 5 v, T A::; 2SoC.
~
Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
CI)
NOTE 5: ICC is measured with all inputs grounded and all outputs open.
Q)
(,)
'S;
switching characteristics, Vee = 5 V, TA = 25°e (see note 6)
PARAMETER
f max
FROM
TO
(INPUT)
(OUTPUT)
lCLKl
lOA
lCLKl
tpLH
TVP
70
50
70
MHz
20
30
25
35
MHz
40
60
50
70
MHz
lOA
lOB
tpHL
lCLK2
tpHL
1Oc
RL = 1
tpLH
kn.
CL = 30 pF
1°0
tPHL
tpLH
20A
tpHL
tpLH
20B
2CLK
tpLH
2Oc
tpHL
tPLH
2°0
tpHL
tpHL
50
Any CLR
Q)
UNIT
MIN
20C. 2°0
tpHL
tpHL
TVP
1°0
20A.20B
f max
tpLH
MIN
lOB. lOC.
f max
tpLH
TEST CONDITIONS
'LS69
'LS68
Any °
MAX
MAX
7
11
7
11
14
21
14
21
8
12
7
11
12
18
14
21
15
23
16
24
21
32
21
32
8
12
25
38
13
20
30
45
7
11
7
11
14
21
14
21
16
24
14
21
19
29
19
29
23
35
23
35
27
40
27
40
16
24
32
48
19
29
36
54
20
30
20
30
Q
.....I
l-
I-
ns
ns
ns
ns
NOTE 6: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-219
-I
-I
r-
C
(1l
<
(i'
(1l
CII
2-220
SN5470, SN7470
AND-GATED J-K POSITIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH PRESET AND CLEAR
DECEMBER 1983-REVISED MARCH 1988
•
Package Options Include Plastic and
Ceramic DIPs and Ceramic Flat Packages
•
Dependable Texas Instruments Quality and
Reliability
SN5470 ••. J PACKAGE
SN7470 .•• N PACKAGE
!TOP VIEWI
NC
ClR
J1
J2
J
description
VCC
PRE
ClK
K2
K1
These monolithic, edge-triggered J-K flip-flops feature
gated inputs, direct ~ear and preset inputs, and complementary Q and Q outputs. Input information is
transferred to the outputs on the positive edge of the
clock pulse.
SN5470 ... W PACKAGE
Direct-coupled clock triggering occurs at a specific
voltage level of the clock pulse, and after the clock input
threshold voltage has been passed, the gated inputs are
locked out.
K1
ClK
PRE
These flip-flops are ideally suited for medium-to-highspeed applications and can result in a significant saving
in system power dissipation and package count where
input gating is required.
VCC
ClR
NC
J1
The SN5470 is characterized for operation over the full
military temperature range of -55°C to 125°C. The
SN7470 is characterized for operation from O°C to
70°C.
Q
K
GND
Q
ITOPVIEW)
K2
K
Q
GND
Q
J
II)
Q)
C.)
J2
':;
NC - No internal connection
Q)
C
logic symbol t
...I
lI-
FUNCTION TABLE
INPUTS
PRE
CLR
L
H
OUTPUTS
CLK
J
K
Q
H
L
X
X
H
L
L
L
X
X
H
L
L
X
X
X
L
Lt
H
H
t
L
L
00
00
H
H
H
L
H
L
H
H
t
t
L
H
L
H
H
H
t
H
H
H
H
L
X
X
L1
TOGGLE
00
lJ
18)
Q
Q
00
If inputs J and K are not used, they must be grounded. Preset or clear
function can occur only when the clock input is low.
tThis configuration is nonstable; that is, it will not persist when preset
and clear inputs return to their inactive (high I level.
lK
161 Q
tThis symbol is in accordance with ANSI/IEEE Std. 91·1984 and
lEe Publication 617-12.
Pin numbers shown are for J and N packages only.
positive logic
J = J1"J2"J
K=K1"K2"j(
PRODUCTION DATA documents contain information
currant as of publication data. Products conform to
specifications par tha tarms of Taxas Instrumants
:'::~~:~~i~.{nr:I~7i ~r;~:~ti:; ~~D::;::::~:~~ not
TEXAS . "
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS, TeXAS 75265
2-221
SN5470, SN7470
AND·GATED J·KPOSITIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH PRESET AND CLEAR
logic diagram (positive logic)
J:Ht-.--..ct
K1~~
>------Q
r---If-«CJ~~~-J1
K2
J2
'----J
-t
-t
rC
ClK
70-GATED J·K WITH CLEAR AND PRESET
schematics of input and outputs
CD
<
n·
CD
EaUIVAlENT OF EACH INPUT
TYPICAL OF All OUTPUTS
- -.....--VCC
til
V C C - - -....- -
130
n
NOM
Req
INPUT
OUTPUT
III MAX
-1.6mA
-3.2mA
2·222
Req NOM
4kn
2kn
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5410, SN1410
AND·GATED J·K POSITIVE·EDGE·TRIGGERED
FLlP·FLOPS WITH PRESET AND CLEAR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ................................................................7 V
Input voltage .............................................................................. 5.5 V
Operating free·air temperature: SN5470 ................................................ - 55°e to 125°C
SN7470 .................................................... O°C to 70°C
Storage temperature range ........................................................... - 65°e to 150°C
NOTE1: All voltage values are with respect to network ground terminal.
recommended operating conditions
SN5470
Vee
Supply voltage
VIH
High-level input voltage
Low-level input voltage
IOH
High-level output current
IOl
Low-level output current
tsu
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
Vil
tw
SN7470
MIN
2
0.8
0.8
-0.4
-0.4
mA
16
mA
I elK high
20
20
L elK low
30
30
LPRE or elR low
25
25
20
20
Setup time before elK t
th
Hold time-Data after eLK t
TA
Operating free-air temperature
5
U The arrow indicates the edge of the clock pulse used for reference:
Hor the rising edge,
125
V
ns
en
G)
ns
5
-55
V
V
16
Pulse duration
UNIT
U
'>
ns
0
70
°e
G)
C
+for the falling edge.
...........
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDITIONSt
PARAMETER
VIK
VOH
VOL
II
PRE or elR
IIH
All other
PRE or elR'
III
All other
11=-12rnA
Vee = MIN,
VIH=2V,
Vil = 0.8 V,
IOH = - 0.4 rnA
Vee= MIN,
VIH=2V.
IOl = 16 rnA
Vee- MAX,
VI-5.5V
Vee= MAX,
VI=2.4V
Vee= MAX,
IOS§
Vee= MAX
ICC
Vee - MAX,
TYP*
2.4
3.4
MAX
MIN
TYP*
2.4
3.4
0.2
0.2
0.4
80
40
40
-3.2
-3.2
- 57
-20
13
See Note 2
0.4
80
-1.6
-1.6
26
-18
13
UNIT
V.
V
1
1
VI=O.4V
MAX
-1.5
-1.5
Vee = MIN,
Vil = 0.8 V,
SN7470
SN5470
MIN
V
mA
I'A
mA
-57
mA
26
mA
tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time.
'Clear is tested with preset high and preset is tested with clear high.
NOTE 2: With ali outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input
is at 4.5 V.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-223
SN5470, SN7470
AND-GATED J,K POSITIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH PRESET AND CLEAR
switching characteristics, Vee = 5 V, T A = 25°e (see note 3)
PARAMETERt
FROM
TO
(INPUT)
(OUTPUT)
TEST CONDITIONS
f max
tPLH
PRE or CLR
QorQ
tpHL
tPLH
CLK
RL
= 400 n,
CL
TVP
20
35
QorQ
t f max == maximum clock frequency; tpLH == propagation delay time. low-to· high level output;
tpHL = propagation delay time, high-to-Iow level output.
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
-I
-I
rC
CD
<
5CD
en
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MAX
UNIT
MHz
50
ns
50
ns
27
50
ns
18
50
ns
= 15 pF
tpHL
2-224
MIN
SN5472. SN7472
AND·GATED J·K MASTER·SLAVE FLlP·FLOPS WITH PRESET AND CLEAR
DECEMBER 1983 - REVISED MARCH 1988
•
Package Options Include Plastic and
Ceramic DIPs and Ceramic Flat Packages
•
Dependable Texas Instruments Quality and
Reliability
SN5472 ... J PACKAGE
SN7472 ... N PACKAGE
ITOP VIEW)
NC
ClR
Jl
J2
J3
description
These J-K flip-flops are based on the master-slave
principle and each has AND gate inputs for entry into the
master section which are controlled by the clock pulse.
The clock pulse also regulates the state of the coupling
transistors which connect the master and slave sections.
The sequence of operation is as follows:
Q
GND
SN5472 ... W PACKAGE
ITOP VIEW)
1. Isolate slave from master
2. Enter information from AND gate inputs to
master
3. Disable AND gate inputs
4. Transfer information from master to slave
PRE
l
H
VCC
ClR
NC
Jl
L
H
H
H
H
H
H
H
.n
.n
.n
.n
L
L
H L
L
H
H H
00
00
H
L
J3
J2
II)
Q)
(,)
oS
Q)
C
logic symbol:$:
..J
....
....
-,
(81 0
-,
(6)
Q
Pin numbers shown are for J and N packages .
t This configuration is nonstable; that is, it will not
positive logic
persist when either preset or clear returns to its
inactive (high) level.
:'~=::i~·i:l~t ~~=:~i:r ~~U:::::A!'~~ nat
GND
Q
*This symbol is in accordance with ANSI/IEEE Std. 91-1984 and
lEe Publication 617-12 .
L
H
TOGGLE
PRODUCTION DATA d.cumenlS contain i.farmati••
current I' of publicatioR datI. PrDducts conform tD
spacifications par the tarms of Texi. Instruments
Q
NC - No internal connection
FUNCTION TABLE
INPUTS
OUTPUTS
Q
Q
ClR ClK J K
X
X X
H
H
l
X
X X
L
l
H
Ht
Ht
X
X X
l
H
K3
K2
Kl
ClK
PRE
The logical states of the J and K inputs must not be
allowed to change when the clock pulse is in a high
state.
The SN5472. and the SN54H72 are characterized for
operation over the full military temperature range of
- 55°C to 125°C. The SN7472 is characterized for
operation from ooC to 70°C.
VCC
PRE
ClK
K3
K2
Kl
Q
J; Jl • J2 • J3
K; Kl • K2· K3
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-225
SN5472, SN7472
AND·GATED J·K MASTER·SLAVE FLlp·FLOPS WITH PRESET AND CLEAR
logic diagram (positive logic)
Jo---.j-+-- Q
CLR--+-"
8 §=Kl
Jl~3=
K2
J2
K3
J3
-t
-t
ClK
r-
oCD
schematics of inputs and outputs
<
TYPICAL OF ALL OUTPUTS
--..--VCC
EQUIVALENT OF EACH INPUT
C')
VCC--......- -
CD
130!l NOM
til
INPUT
OUTPUT
III MAX
Req NOM
-1.6 rnA
4 k!l
-3.2 rnA
2 k!l
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage ........................................................................... " 5.5 V
Operating free-air temperature: SN54'................................................ - 55°e to 125°e
SN74' .................................................... oOe to 700 e
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°e to 1500 e
NOTE 1: Voltage values are with respect to network ground terminal.
2-226
.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5472, SN7472
AND·GATED J·K MASTER·SLAVE FLlP·FLOPS WITH PRESET AND CLEAR
recommended operating conditions
SN7472
SN5472
MIN
NOM
4.5
5
UNIT
MAX
MIN
NOM
MAX
5.5
4.75
5
5.25
V
0.8
0.8
V
VCC
Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
IOH
High-level output current
-0.4
-0.4
mA
IOl
Low-level output current
16
16
mA
Pulse duration
tw
V
2
2
I
ClK high
I
I
ClKlow
47
47
PRE or ClR
25
25
20
20
tsu
Input setup time before elK t
0
0
th
Input hold time-data after elK l
0
0
TA
Operating free-air temperature
125
-55
ns
ns
ns
0
70
'e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH
Vee = MIN,
11=-12mA
Vee=MIN,
VIH -2V,
Vil = 0.8 V,
VIH =2V,
VIL=0.8V,
Vee =MIN,
TVPt
2.4
3.4
Jor K
All other
J or K
All other
Vee=MAX,
Vee
= MAX,
IOS§
Vee -MAX
lee
Vee=MAX,
SN7472
MAX
MIN
TVPt
2.4
3.4
-1.5
0.2
IOL = 16mA
Vee = MAX,
II
IlL
MIN
IOH = - 0.4 mA
VOL
IIH
SN5472
TEST CONDITIONS t
VI =5.5V
VI =2.4V
VI=0.4V
0.4
0.2
See Note 2
10
0.4
1
40
40
80
80
-1.6
-1.6
-32
-18
10
20
V
en
Q)
V
1
-57
UNIT
-1.5
-3.2
-20
MAX
CJ
':;Q)
V
o
mA
.;.J
tt-
/lA
mA
-57
mA
20
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:t All typical values are at Vee"" 5 V. T A = 2SoC.
§ Not more than one output should be shorted at a time.
NOTE 2: With all outputs open,
grounded.
tcc
is measured with the Q and
a outputs high in turn.
At the time of measurement, the clock input is
switching characteristics, VCC = 5 V, TA = 25°C (see note 3)
PARAMETER
FROM
TO
IINPUT)
(OUTPUT)
TEST CONDITIONS
f max
tPLH
PRE or eLR
QorQ
eLK
QorO
tpHL
tpLH
tpHL
RL=400n,
eL = 15 pF
MIN
TVP
15
20
MAX
UNIT
MHz
16
25
ns
25
40
ns
16
25
ns
25
40
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-227
-t
-t
r-
o
CD
<
(r
CD
(II
2-228
SN5473, SN54LS73A, SN7473, SN74LS73A
DUAL J·K FLlp·FLOPS WITH CLEAR
DECEMBER 19B3 - REVISED MARCH 1988
•
Package Options Include Plastic "Small
Outline" Packages, Flat Packages, and
Plastic and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN5473, SN54lS73A ... J OR W PACKAGE
SN7473 ... N PACKAGE
SN74LS73A ... D OR N PACKAGE
(TOP VIEW)
1CLK
lCLR
1K
VCC
2CLK
2CLR
2J
description
The '73, and 'H73, contain two independent
J-K flip-flops with individual J-K, clock, and
direct clear inputs. The '73, and 'H73, are
positive pulse-triggered flip-flops. J-K input is
loaded into the master while the clock is high and
transferred to the slave on the high-to-Iow
transition. For these devices the J and K inputs
must be stable while the clock is high.
GND
4
2K
20
20
'73
FUNCTION TABLE
INPUTS
The 'LS73A contains two independent negativeedge-triggered flip-flops. The J and K inputs
must be stable one setup time prior to the highto-low clock transition for predictable operation.
When the clear is low, it overrides the clock and
data inputs forcing the Q output low and the Q
output high.
OUTPUTS
ClR
ClK
J
K
0
L
X
X
X
L
H
H
.IL
.IL
.IL
.IL
L
L
Qo
00
H
L
H
L
L
H
L
H
H
H
H
H
H
0
TOGGLE
Ul
Q)
CJ
":;
Q)
'LS73A
FUNCTION TABLE
The SN5473, SN54H73, and the SN54LS73A
are characterized for operation over the full
military temperature range of - 55 °e to 125 °e.
The SN7473, and the SN74LS73A are
characterized for operation from
to 70
ooe
1J
10
10
INPUTS
oe.
C
OUTPUTS
ClR
ClK
J
K
0
0
L
X
X
X
L
H
H
I
L
L
Qo
00
H
I
H
L
H
L
H
I
L
H
L
H
H
I
H
H
TOGGLE
H
H
X
X
Qo
...J
t:
00
FOR CHIP CARRIER INFORMATION,
CONTACT THE FACTORY
PROOUCTlOIL DATA do.umonts .ontain information
current as of publication date. Products conform to
specifications par the terms of Texas Instruments
:~~:~:~~i~8i~:1~78 ~:~:~ti:; :I~':=::~:~~S not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
2-229
SN5473, SN54LS73A, SN7473,SN74LS73A
DUAL J·K FlIP·FLOPS WITH CLEAR
logic symbols t
'LS73A
'73
tThese symbols are in accordance with ANSI/IEEE Std. 91·1984 and IEC Publication 617·12.
schematics of inputs and outputs
'73
EaUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
Vee
V C C - - -....- -
130 !~ NOM
-t
-t
INPUT
r-
oCD
<
n'
CD
OUTPUT
UI
Req NOM
IlL MAX
1.6mA
3,2 rnA
4 k!l
2
k~l
'LS73
EOUIVALENT OF
EACH INPUT
TYPICAL OF
ALL OUTPUTS
-
Vee
Vee
Req
--
r....
INPUT
•
j
"t>
~
~~
th
IlL MAX
2-230
- 0.4 rnA
Req NOM
30 k!!
-0.8 mA
8.25 kH
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 .. DALLAS. TEXAS 75265
SN5473. SN54LS73A. SN7473. SN74LS73A
DUAL J-K fliP-flOPS WITH CLEAR
logic diagrams (positive logic)
'73
o --i---*--q
CL R
--t-----+-----l
II)
Q)
(,)
K
-S;
Q)
0
...J
ClK
II-
'LS73A
o
o
'-----~~----+_-ClR
K--'======t
ClK
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage. Vee (See Note 1) ................... , .... , .. , ... , , ...... , ..... , ........ , 7 V
Input voltage: '73 ..... , ...... , . , .. , . , . , .. , .. , , .. , . , .. , . , .. , . , .. , , . , . , . . . . . . . . . . . .. 5.5 V
·LS73A, .. , ., ... , .... , ,., .. , ,., , .. , , , .. " ... , ........... , .... , .. , ., .... 7 V
Operating free-air temperature range: SN54' , . , . , , . , .... , ... , , , .. , , ... , ..... , . ,. - 55°e to 125°e
SN74' ., , . , , .. , , .. , . , ....... , ......... , . , , .. , 0° e to 70 0 e
Storage temperature range ...... , .. , ... , .. , . , , , , .. , ... , , . , . , .. , ...... , .. , .. , - 65 °e to 150 °e
NOTE 1: Voltage values are with respect to network ground terminal.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-231
SN5473, SN7473
DUAL J·K FLlp·FLOPS, WITH CLEAR
recommended operating conditions
SN5473
VCC
Supply voltage
VIH
High-level input voltage
VIL
IOH
Low-level input vol tage
High·level output current
IOL
Low-level output current
MIN
NOM
MAX
5.5
4.75
5
5.25
tsu
Input setup time before elK t
th
Input hold time data after CLK I
Operating free-air temperature
UNIT
V
V
2
0.8
0.8
-0.4
- 0.4
mA
16
mA
16
Pulse duration
TA
5
SN7473
MAX
2
I
tw
NOM
MIN
4.5
CLK high
20
20
J
CLK low
47
47
J
CLR low
25
25
ns
0
0
0
- 55
0
125
V
ns
ns
0
70
"c
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
SN5473
TEST CONDITIONSt
VIK
VOH
VCC" MIN.
II' - 12 mA
VCC" MIN.
VIH"2V.
VIL - 0.8 V.
VIH '. 2 V.
VIL' 0.8 V,
IOH" - 0.4 mA
VCC" MIN,
VOL
MIN
TVP*
2.4
3.4
0.2
IOL = 16 rnA
II
VCC" MAX,
VI' 5.5 V
CLR or CLK
VCC·MAX.
VI"2.4V
VCC· MAX,
VI=O.4V
J or K
CLR
IlL
CLK
~
ICCI
-
VCC'MAX
TVP*
2.4
3.4
0.4
0.2
,·20
0.4
40
40
80
-1.6
- 3.2
- 3.2
- 57
10
20
-18
20
UNIT
V
V
80
- 1.6
,,3.2
- 57
10
MAX
- 1.5
1
- 3.2
So. Nota 2
Vce' MAX,
MIN
1
Jar K
IIH
SN7473
MAX
- 1.5
V
rnA
~A
mA
rnA
mA
t For conditions shown 8& MIN or MAX., use the appropriate value specified undor recommonded operating conditions.
l All typical values .ra .t VCC ~ 5 V. TA = 2SoC.
I Not mar. than on. output should be shortod ot • timo.
, Averag. per flip-flop.
NOTE 2: With all outpUll open, ICC 10 me.ourad with the
pnd Q outputs high in turn. At the time of me.surement, the clock Input
is grounded.
a
switching characteristics, Vee'" 5 V, TA = 2Soe (see note 3)
PARAMETER#
. FROM
TO
!INPUT)
(OUTPUT I
TEST CONDITIONS
f max
tPLH
tPHL
tPLH
tPHL
C"CR
CLK
'0'
0
Rl " 400 !!,
CL" 15 pF
OorO
MIN
TVP
15
20
MAX
UNIT
MHl
16
25
ns
25
40
ns
16
25
ns
25
40
ns
#fmax = maximum clock frequency: tpLH ~ propagation delay time, low-ta,high-Ievel output; tpHL = propagation delay time. high·tolow-level output.
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-232
TEXAS . "
INSTRUMENTS
PPST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS73A. SN74LS73A
DUAL J·K FLlp·FLOPS WITH CLEAR
recommended operating conditions
SN54lS73A
V,,-C
Supply voltage
VIH
High-level input voltag.
Vil
Low-level input voltage
IOH
High-level output current
SN74lS73A
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
O.S
-0.4
-0.4
4
0
tw
Pulse duration
tsu
Set up time-before
th
Hold time-data after ClK I
TA
Operating free-air temperature
ClK~
30
S
ClK high
20
20
25
20
data high or low
20
20
CLR inactive
20
20
0
0
125
- 55
30
0
ClRlow
V
V
2
0.7
Low-level output current
IOl
fclock Clock frequency
UNIT
V
mA
mA
MHz
ns
ns
ns
70
0
'c
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIK
VOH
MIN
11=-1SmA
VCC= MIN,
VIH= 2V,
Vil
Vil = MAX,
VIH = 2 V,
=MAX,
VIH = 2 V,
=MAX,
IOH= -0.4mA
2.5
VCC= MIN,
Vil
MAX
3.4
MIN
TYP*
2.7
0.4
Jar K
ClR
VCC= MAX,
VI = 7 V
ClK
Jar K
ClR
IIH
VCC= MAX,
VI = 2.7 V
ClK
Jar K
III
ClR or ClK
lOSS
ICC (Totall
VCC= MAX,
VI=O.4V
VCC= MAX,
See Note 4
VCC= MAX,
Se. Note 2
UNIT
CI)
CD
V
U
oS;
V
3.4
0.25
0.4
0.35
0.5
C
...........
V
IOl = SmA
II
MAX
-1.5
CD
0.25
IOl =4mA
Val
TYP*
-1.5
VCC= MIN,
VCC= MIN,
SN74LS73A
SN54lS73A
TEST CONDITIONSt
PARAMETER
-20
0.1
0.1
0.3
0.3
0.4
0.4
20
20
60
SO
60
-0.4
-0.4
-O.S
-O.S
- 100
4
mA
/AA
SO
-20
4
6
mA
- 100
mA
6
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All tYpical values are at Vee"" 5 V, T A:::: 2SoC.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2: With all outputs open, ICC is measured with the a and
outputs high in turn. At the time of measurement, the clock input is
grounded.
NOTE 4: For certain devices where state commutation can be caused by shorting an output to ground, an equivalent test may be performed
with Vo = 2.25 V and 2.125 V for the 54 family and the 74 family, respectively, with the minimum and maximum limits reduced
to one half of their stated values.
a
switching characteristics, Vee
PARAMETER
=5 V, TA =25°e (see note 3)
FROM
TO
(INPUT)
(OUTPUT)
TEST CONDITIONS
f max
tPlH
ClR or ClK
QorQ
Rl=2k!l,
Cl = 15 pF
tPHl
MIN
TYP
30
45
MAX
UNIT
MHz
15
20
ns
15
20
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-233
2-234
SN5414. SN54LS14A. SN54S14.
SN1414. SN14LS14A. SN14S14
DUAL D·TYPE POSITIVE·EDGE·TRIGGERED FLlp·FLOPS WITH PRESET AND CLEAR
DECEMBER 1983 - REVISED MARCH 1988
• Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
SN5474 .•. J PACKAGE
SN54lS74A. SN54S74 ..• J OR W PACKAGE
SN7474 ... N PACKAGE
SN74LS74A. SN74S74 ... 0 OR N PACKAGE
ITOP VIEWI
• Dependable Texas Instruments Quality and
Reliability
lClR
10
lClK
lPRE
10
10
GND
description
These devices contain two independent Ootype
positive-edge-triggered flip-flops. A low level at the
preset or clear inputs sets or resets the outputs
regardless of the levels of the other inputs. When preset
and clear are inactive Ihighl, data at the D input meeting
the setup time requirements are transferred to the
outputs on the positive-going edge of the clock pulse.
Clock triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold time interval, data at the 0 input may
be changed without affecting the levels at the outputs.
VCC
2ClR
2D
2ClK
2PRE
20
20
4
SN5474 .•. W PACKAGE
ITOP VIEWI
lPRE
10
10
GNO
20
20
2PRE
lClK
10
lClR
VCC
2ClR
2D
2ClK
The SN54' family is characterized for operation over the
full military temperature range of - 55°C to 125°C.
The SN74' family is characterized for operation from
ooC to 70°C.
en
CI)
U
'S;
CI)
SN54LS74A. SN54S74 ... FK PACKAGE
t
-I
ITOPVIEWI
FUNCTION TABLE
INPUTS
lI-
OUTPUTS
PRE
L
CLR
H
ClK
0
a
X
X
H
L
H
L
X
X
L
L
X
x
l
Ht
H
Ht
a
H
H
·1
H
H
L
H
H
1
L
L
H
H
H
L
X
00
00
3
2
C
1 20 19
NC
2PRE
The output levels in this configuration are not guaranteed
9 10 111213
to meet the minimum levels in VOH if the lows at preset
and clear are near VIL maximum. Furthermore, this con"
figuration is nonstable; that is, it will not persist when
100 UIO 0
~ZZMM
<.!l
either preset or clear returns to its inactive (high) level.
NC - No internal connection
logic symbol*
logic diagram (positive logic)
tThis symbol is in accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617~12.
Pin numbers shown are for D. J. N. and W packages.
PRODUCTION DATA documants ••ntain information
current IS of publicatian dltl. Products conform to
specificatioRs per the terms of TI.IS Instruments
::==i~·i~:I~" ~:~~:i:r :Ir:::.:~::.s nat
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-235
SN5414, SN1414, SN54S14, SN14S14
DUAL D'TYPE POSITIVE·EDGE·TRIGGERED FLlP·FLOPS WITH PRESET AND CLEAR
schematics of inputs and outputs
74
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
V C C - - -....- -
--"--VCC
Req
130n NOM
INPUT
OUTPUT
-I
-I
rC
IlL MAX
-1.6mA
Req NOM
-3.2mA
2kn
4kn
CD
<
c:;.
CD
VI
'874
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
- - - - -....-VCC
V C C - - -....- 50 nNOM
INPUT
OUTPUT
2·236
IlL MAX
Req NOM
-2mA
-4mA
2.8 kn
1.4 kn
~mA
940
n
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TeXAS 75265
SN5474, SN54LS74A, SN54S74,
SN7474, SN74LS74A, SN74S74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
schematic
'LS74A
.-----------.-------~--------------~-------.----------~~--._--VCC
12011
9kll
16 kll
16 kll
9kll
12011
......- - - - Q
PRE
CL"R
en
Q)
u
·S
Q)
C
..J
v
lI18 kll
ClK
31 kll
0
......----GND
L---------------------------~----------~--------~--------
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage,
Vee
(see Note 1) " " " " , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , "
7
V
Input voltage: 74, 'S74 " " " " " " " " " " " " " " " " " " " " " " " " " " " " " "
5,5 V
'LS74A"""""", " " " , " " , " " " " , "" , " " " " " , "" " " " , " , 7 V
Operating free-air temperature range: SN54' '" , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , "
- 55°C to 125°C
SN74' , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , " ooe to 70°C
Storage temperature range, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , "
- 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-237
SN5474, SN7474
DUAL D·TYPE POSITIVE·EDGE·TRIGGERED FLlP·FLOPS WITH PRESET AND CLEAR
recommended operating conditions
SN5474
MIN
VCC
Supply voltage
VIH
High~level
4.5
input voltage
Vil
Low-level input voltage
10H
High-level output current
10l
Low-level output current
5
SN7474
MAX
MIN
NOM
MAX
5.5
4.75
5
5.25
2
ClK high
LClK low
I PRE or ClR low
Pulse duration
tsu
Input setup time before. elK t
th
Input hold time-data after elK t
TA
Operating free-air temperature
UNIT
V
V
2
0.8
0.8
-0.4
-0.4
rnA
16
rnA
16
I
tw
NOM
30
V
30
37
37
30
30
20
20
5
5
-55
125
ns
ns
ns
70
0
°c
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
~
~
r-
oCD
VIK
VoH
<
II
CD
IIH
(I)
MIN
VCC= MIN,
II = -12rnA
VCC= MIN,
VIH= 2 V,
Vil = 0.8 V,
VIH=2V,
Vil - 0.8 V,
2.4
VI = 5.5 V
0
Ci:"R
All Other
VCC= MAX,
VI = 2.4 V
VCC= MAX,
VI = 0.4 V
D
PRE!
III
CLRi
ClK
lOS'
VCC= MAX
ICC'
VCC= MAX,
SN7474
MAX
3.4
0.2
10l = 16 rnA
VCC= MAX,
TVP*
MIN
TVP*
-1.5
10H= -0.4rnA
VCC- MIN,
Val
(i'
SN5474
TEST CONDITIONSt
- 20
See Note 2
-1.5
2.4
0.4
3.4
0.2
0.4
1
1
40
120
120
80
80
-1.6
-1.6
-1.6
-1.6
-3.2
-3.2
-3.2
-3.2
-18
15
8.5
UNIT
V
V
40
- 57
8.5
MAX
V
rnA
~A
rnA
-57
rnA
15
rnA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*AII typical values are at VCC = 5 V, TA = 25°C.
§Clear is tested with preset high and preset is tested with clear high.
'Not more than one output should be shown at a time.
NAverage per flip-flop.
NOTE 2: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is
grounded.
switching charateristics, Vee = 5 V, TA = 25°e (see note 3)
PARAMETER
FROM
TO
(INPUT)
(OUTPUn
TEST CONDITIONS
f max
tPLH
tpHL
tplH
tpHl
PRE or ClR
ClK
QorQ
RL=400n,
NOTE 3: load circuits and voltage waveforms are shown in Section 1 .
TEXAS'"
INSTRUMENTS
2-238
TVP
15
25
POST OFFICE BOX 655012 • DALlAS. TEXAS 75265
MAX
UNIT
MHz
25
ns
40
ns
14
25
ns
20
40
ns
Cl = 15pF
QorQ
.
MIN
SN54LS74A, SN74LS74A
DUAL D·TYPE POSITIVE·EDGE·TRIGGERED FLlP·FLOPS WITH PRESET AND CLEAR
recommended operating conditions
SN74LS74A
SN54LS74A
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
Vce
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
-0.4
- 0.4
IOL
Low-level output current
4
8
rnA
fclock
Clock frequency
25
MHz
tw
Pulse duration
0
Setup time-bp.fore elK t
Isu
2
2
25
Hold time.cfata after eLK t
Operating free-air temperature
0
CLK high
25
25
PRE or CLR low
25
25
High-level data
20
20
low-level data
20
20
-55
125
rnA
ns
ns
ns
5
5
th
TA
V
70
0
°e
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
Vee -MIN"
VOH
~
TYP;
2.5
3.4
MAX
MIN
TYP*
2.7
3.4
-1.5
VIH
2V,
Vft = MAX,
VIL
MAX,
VIH - 2 V,
VIL =MAX,
VIH =2V,
IOH~~O.4rnA
VCC = MIN,
MIN
11~-18mA
VCC=MIN,
VIK
SN74LS74A
SN54LS74A
TEST CONDITIONSt
PARAMETER
0.25
MAX
-1.5
Vce - MIN,
0.4
V
V
0.25
0.4
0.35
0.5
IOL =4 rnA
VOL
UNIT
V
IOL =8 rnA
o orClK
II
Vce =MAX,
CLR orPRE
o orClK
Vee = MAX,
VI =2.7 V
Vce = MAX,
VI =0.4 V
IOS§
Vec =MAX,
See Note 4
ICC (Total)
Vec =MAX,
See Note 2
IIH
eLR or PRE
o orClK
III
CLR or PRE
0.1
0.1
0.2
0.2
20
20
40
40
-0.4
-0.4
VI = 7V
-0.8
-20
-100
4
-0.8
-20
4
8
rnA
p.A
rnA
-100
rnA
8
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee = 5 V. T A:::: 2SOC.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE :2: With all outputs open. ICC is measured with the Q and Q outputs high in turn. At the time of measurement. the clock input is
grounded.
NOTE 4: For certain devices where state commutation can be caused by shorting an output to ground. an equivalent test may be performed
with Va == 2.25 V and 2.125 V for the 54 family and the 74 family. respectively. with the minimum and maximum limits reduced to
one half of their stated values.
switching characteristics, Vee = S V, TA = 2Soe (see note 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
f max
tplH
tpHl
ClR,
PRE or ClK
OorO
RL = 2 k!l.,
Cl = 15pF
MIN
TYP
25
33
MAX
UNIT
MHz
13
25
25
40
ns
ns
Note 3: load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-239
SN54S74, SN74S74
DUAL D·TYPE POSITIVE·EDGE·TRIGGERED FLlp·FLOPS WITH PRESET ANO CLEAR
recommended operating conditions
SN54S74
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
Vec
Supply voltage
VIH
High·level input voltage
Vil
Low·level input voltage
0.8
0.8
V
10H
10l
High-level output cu rrent
-1
-1
mA
20
mA
2
6
7.3
7
3
3
ClK low
elR or PRE low
High-level data
Setup time, before elK t
tsu
th
Input hold time· data after ClK t
TA
Operatingfree-airtemperature
V
20
Pulse duration
tw
Low-level d.ata
V
2
Low-level output current
ClK high
-
SN74S74
MIN
6
7.3
7
3
3
2
ns
ns
2
-55
125
ns
0
70
°c
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
-
PARAMETER
TEST CONOITIONSt
MIN
-4
-4
r-
o
Vce = MIN,
II =- lamA,
VCC = MIN,
VIH =2V,
Vil
VIH
Vil - 0.8 V,
<
2V,
0.8 V,
2.5
3.4
Vec= MAX,
(1)
(II
3.4
UNIT
V
V
0.5
o.s
so
50
VI-5.5V
V
mA
o
VCC = MAX,
SN74S;4
TVP
MAX
- 1.2
2.7
10l = 20mA
c:;'
MIN
-1.2
10H =- 1 mA
VCC=MIN,
(1)
SN54S;4
TVP
MAX
150
150
PRE orClK
100
100
o
-2
-6
-4
-2
-6
-4
-4
mA
-100
mA
25
mA
VCC=MAX,
VI =2.7V
VI =0.5V
ClK
4
VCC= MAX,
-100
-40
VCC = MAX
lOS!
See Note 2
15
-40
15
25
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
'All typical values are at VCC = 5 V, TA = 2SoC.
§Nat more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second .
• Clear is tested with preset high and preset is tested with clear high.
# Average per flip·flop.
NOTE 2: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is
grounded.
switching characteristics, Vee = 5 V, T A = 25°e (see note 3)
FROM
(INPUT)
PARAMETER
TO
TEST CONDITIONS
(OUTPUT)
f max
tplH
lIRE or CLR
PRE or ClR (ClK high I
tpHl
tplH
PR E or ClR (ClK lowl
ClK
OorO
CorO
RL = 280
n,
Cl = 15 pF
TVP
75
110
QorQ
NOTE 3: Load circuits and voltage waveforms are shown in. Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
MAX
UNIT
MHz
4
6
9
13.5
5
8
9
6
6
tpHl
2-240
MIN
9
ns
ns
ns
ns
SN5475. SN5477. SN54LS75. SN54LS77.
SN7475. SN74LS75
4-BIT BISTABLE LATCHES
MARCH 1974 - REVISED MARCH 1988
SN5475, SN54LS75 ... J OR W PACKAGE
SN7475 ... N PACKAGE
SN74LS75 ... D OR N PACKAGE
(TOP VIEW)
FUNCTION TABLE
(each latch)
INPUTS
= high level,
H
00
L
= the level of
OUTPUTS
D
C
Q
Q
L
H
X
H
H
H
L
H
L
00
~
10
10
20
3C,4C
L
Vec
3D
40
40
= low level,
a
10
20
2'0
lC,2C
GNO
3'0
30
40
X = irrelevant
before the high-to-Iow transition of G
description
SN5477, SN54LS77 ... W PACKAGE
(TOP VIEW)
These latches are ideally suited for use as temporary
storage for binary information between processing units
and input/output or indicator units. Information present
at a data (0) input is transferred to the 0 output when
the enable (C) is high and the 0 output will follow the
10
20
3C,4C
Vec
data input as long as the enable remains high. When the
enable goes low. the information (that was present at
the data input at the time the transition occurred) is
retained at the 0 output until the enable is permitted to
go high.
3D
40
NC
10
20
lC,2C
GNO
NC
30
40
NC - No internal connection
The '75 and 'LS75 feature complementary 0 and Q
outputs from a 4-bit latch, and are available in various
16-pin packages. For higher component density
applications, the '77 and 'LS77 4-bit latches are available
in 14-pin flat packages.
These circuits are completely compatible with all popular
TTL families. All inputs are diode-clamped to minimize
transmission-line effects and simplify system design.
Series 54 and 54LS devices are characterized for
operation over the full military temperature range of
- 55 DC to 125 ·C; Series 74, and 74LS devices are
characterized for operation from o·e to 70·e.
logic symbols t
'75. 'LS75
'77. 'LS77
10
t14J 10
(13) 20
191
3Q
(8) 4Q
40
tThese symbols are in accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (See Note 1) .. .
Input voltage: 75, 77 . . . . . . . . . . . . . . . . . . . . . . . . . .
'LS75, 'LS77 . . . . . . . . . . . . . . . . . . . .
Interemitter voltage (see Note 2) . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54' . . . . . . . . . . . . .
SN74'
Storage temperature range . . . . . . . . . . . . . . . . . .
.. .. 7V
. .... 5.5 V
.. ........... 7V
. . . . . . . . . . . 5.5 V
-55·C to 125·C
C to 70·C
-65°C to 150·C
a·
NOTES: 1. Voltage values are with respect to network ground terminal.
2. This is the voltage between two emitters, of a multiple·emitter input transistor and is not applicable to the 'LS75 and 'LS77.
PRODUCTION DATA do•• ments .ontoin informe!ion
currant as of publication data. Products conform to
splcificltiaRs par the terms of TeXIS Instruments
==:i;.irnr:I~7~ ~~=::i:; :r.o;.e:::::r::.s not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-241
SN5475, SN5477, SN54LS75, SN54LS77,
SN7475, SN74LS75
4·BI1 BISTABLE LATCHES
logic diagrams (each latch) (positive logic)
'75, '77
Q
Q
('75)
ENABLE
C
DATA
#f?ro
'LS77
'LS75
~~~~:
DATA
TO
OTHER
LATCH
C
C
schematics of inputs and outputs
::Ir
'LS75, 'LS77
'75, '77
EQUIVALENT OF EACH INPUT
C
CD
<
EOUIVALENT OF EACH INPUT
-
VCC
Vcc------~-----
Req
(i'
CD
INPUT
II)
.....
-
u'O
INPUT
"
~~
"
1;7
Data:
Req = 2
Enable: Req = 1
kn
kn
Data:
NOM
NOM
Req
= 17
Enable: Req = 4.2
kn
kn
75,77
'LS75, 'LS77
TYPICAL OF ALL OUTPUTS
TYPICAL OF ALL OUTPUTS
--------~~---VCC
120n
./"____..... NOM
L...._....___ OUTPUT
2-242
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SN5475, SN5477, SN7475
4·BIT BISTABLE LATCHES
recommended operating conditions
SN5475, SN5477
MIN
Supply voltage, Vee
4.5
NOM
MIN
NOM
5.5
4.75
5
5
High-level output current, IOH
SN7475
MAX
-400
Low-level output current, tOl
MAX
5.25
-400
16
Width of enabling pulse, tw
Setup time, tsu
V
~A
mA
20
20
20
ns
20
ns
5
5
Hold time, th
Operating free-air temperature, T A
16
UNIT
-55
125
ns
70
0
"e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
TVPt
MAX UNIT
2
II
Input current at maximum input voltage
IIH
High-level input current
IlL
low-level input current
lOS
Short-circuit output current§
lee
TEST CONDITIONSt
o input
C input
o input
Cinput
Vee= MIN,
11=-12mA
Vee= MIN,
VIH = 2 V,
VIL = 0.8 V,
10H = -400 ~A
Vee = MIN,
VIH=2V,
VIL = 0.8 V,
10L = 16 mA
Vee= MAX,
VI=5.5V
Vee = MAX,
VI=2.4V
Vee = MAX,
,VI=O.4V
Vee= MAX
Supply current
2.4
V
0.8
V
-1.5
V
3.4
V
In
0.2
0.4
1
80
160
-3.2
-6.4
SN54'
-20
SN74'
-18
-57
-57
Vee= MAX,
SN54'
32
46
See Note 3
SN74'
32
53
V
mA
~A
mA
Q)
(J
>
Q)
o
...J
lI-
mA
mA
tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating condit/ons.
tAil typical values are at Vee = 5 V, T A = 25°c.
§Not more than one output should be shorted at a time.
NOTE 3: ICC is tested with all inputs grounded and all out.puts open.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
tpLH
tpHL
tpLH.
tpHL.
tpLH
tpHL
tpLH'
FROM
TO
UNPUT)
(OUTPUT)
0
Q
0
Q
TEST eONDITIONS
eL=15pF,
RL=400n,
e
Q
e
Q
See Figure 1
tPHL.
MIN
TVP
MAX UNIT
16
30
14
25
24
40
7
15
16
30
7
15
16
30
7
15
ns
ns
ns
ns
tpLH =: propagation delay time, low-to-high-Ievel output
tpH L :=0=: propagation delay time, high-to-Iow-Ievel output
not applicable for the SN5477.
11 These parameters are
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-243
SN54LS75, SN54LS77, SN74LS75
4·BI1 BISTABLE LATCHES
recommended operating conditions
SN54LS75
SN74LS75
SN54LS77
MIN
NOM
4.5
Supply vollage, Vee
MAX
MIN
NOM
5.5
4.75
5
5
-400
High-level output current. tOH
4
Low-level output current, tOl
Width of enabling pulse,
UNIT
MAl(
tw
Setup time, tsu
V
400
jlA
8
mA
20
20
20
20
ns
5
5
ns
Hold time, th
Operating free-air temperature. T A
5.25
125
55
ns
70
0
"e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS75
PARAMETER
TEST eONOITIONSt
MIN
..of
..of
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
I nput clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
2
r-
C
CD
<
5"
CD
til
Input current at
II
Vee- MIN,
11--18mA
Vee= MIN,
VIH = 2 V,
Vil = Vil max,
10H = -400jlA
Vee = MIN,
VIH=2V,
Vil = Vil max
Vee= MAX,
maximum input voltage
High-level input current
IIH
SN74LS75
SN54LS77
Typ:l: MAX
III
Low-level input current
Vee= MAX,
lOS
Short-circuit output current ~
Vee= MAX
ICC
Supply current
Vee = MAX,
10l =4mA
VI = 2.7 V
VI=0.4V
MAX
2
0.25
V
0.8
V
-1.5
-1.5
V
2.7
3.5
0.25
0.4
V
3.6
0.35
0.4
0.5
o input
0.1
0.1
C input
0.4
0.4
o input
20
20
C input
80
80
o input
-0.4
0.4
C input
-1.6
-1.6
-100
-20
See NOle 2
Typ:l:
0.7
10l - 8mA
VI = 7 V
Vee = MAX,
2.5
UNIT
MIN
\'lS75
6.3
12
'lS77
6.9
13
-100
-20
6.3
12
V
mA
"A
mA
mA
mA
t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
:!:AII typical values are at V cC '" 5 V, T A"" 25"C.
~Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second
NOTE 2:
ICC is tested with all inputs grounded and all outputs open.
switching characteristics, Vee =5 V, TA = 25°e
PARAMETER~
IPlH
IPHl
IPlH
IPHl
IPLH
IpHl
IPlH
IpHL
FROM
TO
(INPUT)
!OUTPUT)
0
0
TEST eONOITIONS
'LS75
MIN
Q
Q
el = 15pF,
Rl = 2 kn,
e
e
a
See Figure 1
Q
~ tpLH '" propagation delay time, low-to-high-Ievel output
tpLH = propagation delay time, high-to-Iow-Ievel output
2-244
.
TEXAS'"
INSTRUMENTS
POST OFFiCe BOX 656012 • DALLAS, TeXAS 75265
'LS17
TYP
MAX
TYP
MAX
15
27
11
19
9
17
9
17
12
20
MIN
UNIT
ns
ns
7
15
15
27
10
18
14
25
10
18
16
30
7
15
ns
ns
SN5475, SN5477, SN54LS75, SN54LS77,
SN7475, SN74LS75
4·BIT BISTABLE LATCHES
PARAMETER MEASUREMENT INFORMATION
switching characteristics t
INPUTS
OUTPUTS
~
~
D
a
C
a
1
RL
PULSE
GENERATOR A
(See Note Al
a
D
'J'
CL
ISee Note CI
15pF
. ..
(See Note B)
....
Q
PULSE
GENERATOR 8
ISee Note AI
r
.J- ~
~C
~
.
RL
I
r----
- ' - CL
l.
15pF
ISee Note 81
-
II)
TEST CIRCUIT
1
~s
.1
Q)
0
"I
llJS
Ir-_ _ __
I
DINPUT
'S;
Q)
3V
C
Vref
tsu
--l
I
1------
"r""--~-t::.~ - ~- -- - ,..---_
I
..J
....
....
OV
3V
Note 0)
OUTPUT Q
OUTPUT Q
I
I
I
I
I
f-
I
I
I-
tPLH
~
__________________
f"'"
J~ ~::
Vref
VOLTAGE WAVEFORMS
tComplementary Q outputs are on the '75 and 'LS75 only.
NOTES: A. The pulse generators have the following characteristics: Zout = 50 0; for pulse generator A, PAR ~ 500 kHz; for pulse
generator B, PRR ~ 1 MHz. Positions of 0 and C input pulses are varied with respect to each other to verify setup times.
B. CL includes probe and jig capacitance.
C. All diodes are 1 N3064 or equivalent.
D. When measuring propagation delay times from the D input. the corresponding C input must be held high.
E. For '75 and '77, Vref ~ 1.5 V; for 'LS75 and 'LS77, Vref ~ 1.3 V.
FIGURE 1
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·245
-I
-I
r-
C
CD
<:
("')
CD
VI
2-246
SN5476, SN54LS76A,
SN7476, SN74LS76A
DUAL J·K FLlP·FLOPS WITH PRESET AND CLEAR
DECEMBER 19B3-REVISED MARCH 19BB
•
Package Options Include Plastic and
Ceramic DIPs and Ceramic Flat Packages
•
Dependable Texas Instruments Quality and
Reliability
SN5476, SN54lS76A ... J PACKAGE
SN7476 ... N PACKAGE
SN74lS76A ... 0 OR N PACKAGE
(TOP VIEW)
description
The '76 contains two independent J-K flip-flops
with individual J-K, clock, preset, and clear
inputs. The '76 is a positive-edge-triggered flipflop. J-K input is loaded into the master while the
clock is high and transferred to the slave on the
high-to-Iow transition. For these devices the J
and K inputs must be stable while the clock is
high.
1CLK
1 PRE
1K
10
10
1J
VCC
2CLK
2 PRE
2 CLR
2K
20
20
2J
GND
'76
FUNCTION TABLE
INPUTS
The 'LS76A contain two independent negativeedge-triggered flip-flops. The J and K inputs
must be stable one setup time prior to the highto-low clock transition for predicatble operation.
The preset and clear are asynchronous active
low inputs. When low they override the clock
and data inputs forcing the outputs to the steady
state levels as shown in the function table.
OUTPUTS
ClK
J
K
a
H
X
X
X
H
L
L
X
X
X
H
X
X
L
HI
HI
til
L
L
0'0
L
H
o
::-
PRE
ClR
L
H
L
L
H
H
H
H
H
H
H
H
X
.n
.n
.n
.n
H
L
00
H
L
H
L
H
H
a
TOGGLE
Q)
Q)
o
...J
The SN5476 and the SN54LS76A are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN7476 and the SN74LS76A are characterized
for operation from OOC to 70°C.
~
~
'lS76A
FUNCTION TABLE
INPUTS
PRE
t
ClR
OUTPUTS
ClK
J
K
a
a
L
H
X
X
X
H
L
H
L
X
X
X
L
HI
H
0'0
L
H
L
L
X
X
X
H
H
I
L
L
H
H
I
H
L
00
H
H
H
I
L
H
L
H
H
I
H
H
H
H
H
X
X
HI
TOGGLE
00
0'0
This configuration is nonstable; that is, it will not persist
when either preset Dr clear returns to its inactive (high)
level.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
:~~~~:~~i~8i~:1~1~ ~!::i~~ti:r :1~O::~:~:t:rOs~S not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-247
SN5476. SN7476
DUAL J·K FLIP-FLOPS WITH PRESET AND CLEAR
logic diagrams (positive logic)
76
I-----.-+-PRE
-I
-I
I=====---K
r0-
C
Q)
~.
eLK
(')
Q)
en
2-248
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN5476. SN54LS76A.
SN7476. SN74LS76A
DUAL J·K FlIp·FLOPSWITH PRESET AND CLEAR
logic diagrams (positive logic) (continued)
'LS76A
o
PRE--~------~~------J
K
L-------~--------+--CLR
--=======~
CLK
logic symbols t
lPRE
lJ
lCLK
lK
lCLR
2PRE
2J
2CLK
2K
2CLR
,
(4)
(I)
III
'LS76A
76
(2)
lPRE
lJ
lCLK
lK
lCLR
2PRE
2J
2CLK
2K
2CLR
(15) 10
(2)
S
Q)
(J
(15)
10
oS;
10
C
Q)
..J
II-
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
schematics of inputs and outputs
76
EOUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
---_--VCC
VCC---~~--
130
n NOM
INPUT
OUTPUT
IlL MAX
Req NOM
-1.6mA
4kn
2kn
-3.2mA
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-249
SN5476, SN54LS76A,
SN7476, SN74LS76A
DUAL J·K FLlp·FLDPS WITH PRESET AND CLEAR
schematics of inputs and outputs (continued)
'LS76A
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
.-
VCC
--------- 120
Req
INPUT
..
Vcc
n
NOM
--
r,
~
-'
1......lM-.......- OUTPUT
"to
~
th
::q
IlL MAX
- 0.4 mA
Req NOM
-0.8mA
8.25
30
kn
kn
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
r-
Supply voltage. Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: '76......................................................... 5.5 V
'LS76A ....................................................... 7 V
Operating free-air temperature range: SN54' . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 DC to 125 DC
SN74' ................................ oDe to 70 De
Storage temperature range ......................................... -: 65 DC to 150 DC
o
CD
<
n·
CD
en
NOTE 1: Voltage values are with respect to network ground terminal.
2-250
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5476, SN7476
DUAL J·K FLlp·FLOPS WITH PRESET AND CLEAR
recommended operating cond itions
SN5476
Vec
Supply voltag.
V,H
High-level input voltage
V,l
Low-level input voltage
IOH
High-level output current
IOl
Low-level output current
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
Input setup time before elK t
Input hold time-data after elK ~
TA
Operating free-air temperature
V
O.S
O.S
-0.4
-0.4
mA
16
mA
I
ClK high
ClK low
47
47
I
PRE or ClR low
25
25
I
UNIT
V
2
16
th
tsu
NOM
2
Pulse duration
tw
SN7476
MIN
20
V
20
0
0
0
0
- 55
125
ns
ns
ns
0
70
°e
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
V,K
VOH
MIN
Vce = MIN.
1,=-12mA
Vee= MIN,
V'H-2V,
V,l - O.S V,
V'H-2V,
V'l=O.SV,
VCC= MIN,
TYP*
"
J or K
I'H
All other
Jar K
',l
All other'
V, = 5.5 V
Vee= MAX,
V, = 2.4 V
Vec= MAX,
V, = 0.4 V
IOS§
Vce= MAX
ICC#
Vce= MAX,
3.4
0.2
IOl = 16 mA
Vce= MAX,
SN7476
MAX
MIN
TYP*
2.4
3.4
MAX
-1.5
-1.5
2.4
IOH = - 0.4 mA
VOL
t For
SN5476
TEST CONDITIONSt
0.4
0.4
1
40
40
SO
SO
-1.6
-1.6
- 57
Se. Not. 2
10
-3.2
-lS
20
In
Q)
(.)
V
'S
mA
C
Q)
1
-.20
V
V
0.2
- 3.2
UNIT
10
..J
....
....
"A
mA
- 57
mA
20
mA
conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
= 5 V, TA = 25 ·C.
*All typical values are at VCC
§ Not more than one output should be shorted at a time.
, Clear is tested with preset high and preset is tested with clear high.
# Average per flip-flop.
NOTE 2: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input
is grounded.
switching characteristics, Vee
PARAMETER
= 5 V, T A = 25°e (see note 3)
FROM
TO
(INPUT)
(OUTPUT)
PRE or ClR
OorO
ClK
QorO
TEST CONDITIONS
15
f max
tplH
-
tPHl
tPlH
MIN
RL = 400
n,
Cl = 15 pF
-
tPHl
TYP
MAX
UNIT
MHz
20
16
25
ns
25
40
ns
16
25
ns
25
40
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-251
SN54LS76A. SN74LS76A
DUAL J·K FLIP· FLOPS WITH PRESET AND CLEAR
recommended operating conditions
SN54LS76A
VCC
Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
IOH
High-level output current
IOl
fclock
Low-level output current
tw
Pulse duration
NOM
4.5
5
SN74LS76A
MAX
MIN
5.5
4.75
2
NOM
MAX
5
5.75
0.7
O.S
-0.4
-0.4
0
tsu
Setup time before ClK)
th
Hold time.cJata atter ClK)
Operating free-air temperature
30
B
0
ClK high
20
20
PRE or ClR low
25
25
data high or low
20
20
eLR inactive
PRE inactive
20
25
20
25
0
0
-55
125
UNIT
V
V
2
4
Clock frequency
TA
MIN
30
V
mA
mA
MHz
ns
ns
ns
0
70
°c
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
-I
-I
r-
C
PARAMETER
VIK
VOH
MIN
VCC = MIN,
II = -lSmA
VCC= MIN,
VIH = 2 V,
Vil = MAX,
Vil = MAX,
VIH - 2 V,
Vil = MAX,
VIH = 2 V,
VCC= MIN,
<
TYP*
2.5
VCC = MIN,
en
3.4
0.25
IOl =4mA
VOL
SN74lS76A
MAX
MIN
TYP*
-1.5
IOH = - 0.4 mA
CD
n'
CD.
SN54lS76A
TEST CONDITIONst
2.7
IOl=SmA
<:D'I or JS"Rl:
VCC= MAX,
VI = 7 V
ClK
Jar K
ClR or PRE
IIH
VI = 2.7 V
VCC= MAX,
ClK
Jar K
VCC= MAX,
VI=O.4V
IOS§
VCC= MAX,
See Note 4
ICC (Total)
VCC= MAX,
See Note 2
III
All other
V
V
3.4
0.4
UNIT
0.25
0.4
0.35
0.5
V
J or K
II
MAX
- 1.5
0.1
0.1
0.3
0.3
0.4
0.4
20
20
60
60
SO
SO
-0.4
-0.4
-0.8
-20
-100
4
-0.8
-20
4
6
mA
itA
mA
-100
mA
6
mA
t For conditions shown as MIN or MAX, use the appropriate value specjfied under recommended operating conditions.
t All typical values are at Vee = 6 V, T A = 25°C.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2: With all outputs open, ICC is measured with the a and
outputs high in turn. At the time of measurement. the clock Input is
grounded.
NOTE 4: For certein devices where state commutation can be caused by shorting an output to ground. an equivalent test may be performed
with Vo = 2.25 V and 2.125 V for the 54 familv and the 74 family. respectivelv. with the minimum and maximum limits reduced to
one half of their stated values.
a
switching characteristics, Vee = 5 V, TA = 25°e (see note 3)
PARAMETER
f max
tplH
tPHl
FROM
TO
(INPUT)
(OUTPUT)
TEST CONDITIONS
..
--PRE, ClR or ClK
ooro
Rl = 2 kn,
Cl = 15pF
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
.
2-252
J,.s
TEXAS "V
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
TYP
30
45
MAX
UNIT
MHz
15
20
ns
15
20
ns
SN54LS78A. SN74LS78A
DUAL J·K FLlp·FLOPS WITH PRESET. COMMON CLOCK. AND COMMON CLEAR
DECEMBER 1983 - REVISED MARCH 1988
•
•
SN54LS7BA ... J OR W PACKAGE
SN74LS7BA ... 0 OR N PACKAGE
Package Options Include Plastic "Small
Outline" Packages, Flat Packages, and
Plastic and Ceramic DIPs
(TOP VIEW I
Dependable Texas Instrument Quality and
Reliability
description
The 'LS78A contains two negative-edge-triggered flipflops with individual J-K, preset inputs, and common
clock and common clear inputs. The logic levels at the
J and k inputs may be allowed to change while the
clock pulse is high and the flip-flop will perform
according to the function talbe as long as minimum
setup and hold times are observed. The preset and
clear are asynchronous active-low inputs. When low
they override the clock and data inputs forcing the
outputs to the steady-state levels as shown in the
function table.
CLK
1 PRE
1J
1K
10
10
VCC
CLR
2 PRE
2K
GND
2J
20
20
FUNCTION TABLE
OUTPUTS
INPUTS
The SN54LS78A is characterized for operation over
the full military temperature range of - 55 DC to
125 DC. The SN74LS78A is characterized for
operation from 0 DC to 70 DC.
PRE
CLR
CLK
J
K
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
L
X
X
X
L
Ht
H
Ht
H
H
L
00
00
H
H
L
H
L
In
H
H
I
I
I
L
H
L
H
L
H
H
H
j
H
H
H
H
H
X
X
o
>
Q)
Q
TOGGLE
00
00
tThis configuration is nonstable; that is, it
will not persist when preset and clear inputs
return to their inactive (high) level.
logic symbol t
ClK
ClR
Q)
C
....I
lI-
tPRE
tJ
lK
2PRE
2J
2K
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
PRODUCTION DATA documents contain information
currant as of publication date. Products conform to
spacifications per the terms of Texas Instruments
::~~:~~i~ai~:1~7i ~:::i~~ti:; :I~O::~:::~:~~S not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
2-253
SN54LS78A. SN74LS78A
DUAL J·K FLlp·FLOPS WITH PRESET. COMMON CLOCK. AND COMMON CLEAR
logic diagram (positive logic)
Q
PRE--+-------~-------J
L-------~--~---+-ClR
i<~====:::::j
ClK
-I
-I
TO OTHER F·F
schematics of inputs and outputs (continued)
rC
TYPICAL OF
All OUTPUTS
EQUIVALENT OF
EACH INPUT
CD
Vce
<
Vcc
----4~--.-
n'
Req
CD
III
r.
INPUT
J-
~
.. to
--
~
-'-
tf,
III MAX
Req NOM
- 0.4 mA
30 kn
-0.8mA
8.25 kn
- 1.6 mA
4.1 kn
absolute maximum ratings over operating free· air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Operating free-air temperature range: SN54LS78A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 DC to 125 DC
SN74LS78A ................................... oDe to 70 De
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 DC to 150 DC
NOTE 1: Voltage values are with respect to network ground terminal.
2-254
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SN54LS78A. SN74LS78A
DUAL J-K FLIP-FLOPS WITH PRESET. COMMON CLOCK. AND COMMON CLEAR
recommended operating conditions
SN74lS78A
SN54lS78A
Vee
Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
IOH
High-level output current
ou~put
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.75
2
IOl
Low-level
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time before elK
th
Hold time-data after elK ~
TA
Operating free-air temperature
0.7
0.8
-0.4
- 0.4
4
0
~
30
0
elK high
20
20
PAE or elA low
25
25
data high or low
20
20
PRE or CLR inactive
20
20
0
0
- 55
125
V
V
2
current
UNIT
V
mA
8
mA
30
MHz
ns
ns
ns
0
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
SNS4LS78A
TEST eONDITIONSt
MIN
11=-18mA
Vee = MIN,
VIH=2V,
Vil = 0.7 V,
VIH = 2 V,
Vil = 0.8 V,
Vil =MAX,
VIH = 2 V,
VIL = MAX,
VIH=2V,
Vee = MIN,
SN74lS78A
MAX
2.5
Vee= MIN,
II
0.25
0.4
0.1
0.3
0.3
0.8
0.8
~
VI = 7 V
Vee= MAX,
VI = 2.7 V
20
120
60
60
160
Jar K
-0.4
-0.4
~
~
-1.6
-1.6
-0.8
-0.8
-1.6
-1.6
Vee= MAX,
VI=0.4V
eLK
§
20
120
160
I
:t
0.5
0.6
eLK
t
0.35
0.6
~
IlL
0.4
0.1
~
IOS§
Vee= MAX,
See Note 4
ICC ITotall
Vee= MAX,
See Note 2
Q)
(J
V
o
V
eLK
IIH
0.25
eLR
Vee= MAX,
III
V
3.4
Jar K
~
UNIT
:::-
IOL=8mA
I
I
MAX
-1.5
2.7
IOL = 4mA
VOL
TYP*
3.4
IOH = -0.4mA
Vee = MIN,
MIN
-1.5
Vee = MIN.
IOH = -0.4 mA
VOH
TYP*
-20
-100
4
6
-20
4
Q)
.......J....
mA
/lA
mA
-100
mA
6
mA
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
All typical values are at Vee = 5 V. T A = 2SoC.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
a
a
NOTE 2: With all outputs open, ICC is measured with the
and
outputs high in turn. At the time of measurement, the clock input is
grounded.
NOTE 4: For certain devices where state commutation can be caused by shorting an output to ground, an equivalent test may be performed
with Vo:O 2.25 V and 2.125 V for the 54 family and the 74 family, respectively, with the minimum and maximum limits reduced
to one half of their stated values.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-255
SN54LS78A, SN74LS78A
DUAL J-K FLIP-FLOPS WITH PRESET, COMMON CLOCK, AND COMMON CLEAR
switching characteristics, Vee = 5 V, TA = 25°e (see note 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
PRE, ClR or ClK
QorO
TEST CONDITIONS
f max
tplH
tpHl
Rl=2kn,
Cl=15pF
NOTE 3: Load circuits and vo!tage waveforms are shown in Section 1.
-I
-I
r-
C
(1)
<
c:;(1)
UJ
2-256
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
TYP
MAX
30
45
15
15
20
20
UNIT
MHz
ns
ns
SN5483A, SN54LS83A, SN1483A, SN14LS83A
4·BIT BINARY FULL ADDDERS WITH FAST CARRY
MARCH 1974 - REVISED MARCH 1988
•
Full·Carry Look·Ahead across the Four Bits
•
Systems Achieve Partial Look·Ahead
Performance with the Economy of
Ripple Carry
•
SN5483A,SN54LS83A • _ . J OR W PACKAGE
SN7483A ••. N PACKAGE
SN74LS83A . _ . D OR N PACKAGE
ITOPVIEWI
SN54283/SN74283 and SN54LS283/SN74LS283
Are Recommended For New Designs as They
Feature Supply Voltage and Ground on Corner
Pins to Simplify Board Layout
23ns
43 ns
310mW
'LS83A
25 ns
45 ns
95mW
B4
D
L4
A3
C4
B3
CO
GND
VCC
I2
TYPICAL ADD TIMES
TWO
TWO
TYPICAL POWER
DISSIPATION PER
TYPE
8-BIT
16-BIT
4-BITADDER
WORDS
WORDS
'B3A
A4
B1
A1
1:1
B2
A2
SN54LS83A ... FK PACKAGE
ITOPVIEWI
description
U
lI!~~~lil
These improved full adders perform the addition of
two 4-bit binary numbers_ The sum (~) outputs are
provided for each bit and the resultant carry (C4) is
obtained from the fourth bit_ These adders feature
full internal look ahead across all four bits generating
the carry term in ten nanoseconds typically. This
provides the system designer with partial look-ahead
performance at the economy and reduced package
count of a ripple-carry implementation_
3
2 1 2019
A2
A3
1:1
D
NC
NC
A1
B1
A4
The adder logic, including the carry, is implemented
in its true form meaning that the end-around carry
can be accomplished without the need for logic or
level inversion.
~
NC· No Intarnal connection
FUNCTION TABLE
Designed for medium-speed applications, the circuits
utilize transistor-transistor logic that is compatible
with most other TTL families and other saturated
low-level logiC families,
Series 54 and 54LS circuits are characterized for
operation over the full military temperature range of
-55°C to 125°C, and Series 74 and 74LS circuits are
characterized for operation from O°C to 70°C_
logic symbol t
A1
A2
A3
AO
(101
(8,
"'
., "'m
111)
.2
.3
.0
(0,
(161
co 1131
]. "{
:}o
!
co
(9,
•• "'
(2,
(16)
f14)
E2
"'
"'
co
H = high level, L"" low level
NOTE: Input conditions at A1, 81. A2. 82, and CO are used to
CI
'This symbol is in accordance with ANSI/IEEE Std 91·1984
and IEC Publication 617-12.
Pin numbers are for D. J, N, and W packages.
PRODUCTIOI DATA do.um••ta _ i l i.formation
current I I of publicotl•• dill. Products .o.form to
IDMlfioati... per the _
of T_ Inst......ts
silntllrd w.rralty. Prodlction ~""";Ig ......ot
._.lrll, I.clude II1II.. of .11 par._....
determine outputs 1:; 1 and !;2 and the value of the internal
carry C2. The values at C2. AS, 83, A4, and B4 are then
used to determine outputs 1:3, 1:4, and C4.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-257
SN5483A, SN54LS83A, SN7483A, SN74LS83A
4·BIT BINARY FULL ADDDERS WITH FAST CARRY
sChematics of inputs and outputs
'S3A
TYPICAL OF ALL
OUTPUTS
EQUIVALENT OF
EACH INPUT
---------e---vec
R
VCC-----4....- -
INPUT
•
' - - -....-
co input: Req
Any A or B: Req
= 4 knNOM
= 3.5 kn NOM
OUTPUT
C4 output: R = 100 n NOM
Any~: R = 120 nNOM
'LS83A
EQUIVALENT OF
EACH INPUT
TYPICAL OF
ALL OUTPUTS
Vec
Vee--"'---
120 nNOM
Req
INPUT~o-toIHI~~'-
' - - - - -...-OUTPUT
co input: Req = 17 kn NOM
Any A or B: Req = 8.5 kn NOM
2-258
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN5483A, SN54LS83A, SN1483A, SN14LS83A
4-BI1 BINARY FULL ADDDERS WITH FAST CARRY
logic diagram (positive logic)
(14)
B4
A4
e4
(16)
(1)
>-_--'-(_15-'-) ~4
CI)
A3
Q)
(3)
(2)
U
-s:
~3
Q)
0
......
...I
B2 :(7~)---'J[f;~---il=~jj==J:=r------~
...,L..../
A2
Bl
.:..(8..:..)_ _ _
(6)
~2
(11 )
(9)
A 1 ~(l~O,-)---=1=~~----'
~1
CO -'-.(1_3,--)----1:>0------------'
Pin numbers shown are for D, J, N, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage: '83A
'LS83A
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN5483A, SN54LS83A
SN7483A,SN74LS83A
Storage temperature range
NOTES:
7V
5.5V
7V
5.5V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C
1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. This rating applies for the 'S3A only between the
following pairs: A1 and 81, A2 and 82, A3 and 83. A4 and 84.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS. TEXAS 75265
2-259
SN5483A. SN7483A
4·BIT BINARY FULL ADDDERS WITH FAST CARRY
recommended operating conditions
SN5483A
Supply Voltage, Vee
High-level output current, IOH
SN7483A
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
Any output except C4
-800
-800
Output e4
-400
-400
16
16
8
8
Any output except C4
Low-level output current. IOL
Output C4
Operating free-air temperature, T A
-55
125
0
70
UNIT
V
I'A
mA
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIH
High-level i npu t vol tage
VIL
Low-level input voltage
V 11<
Input clamp voltage
II
MIN
TYP*
MAX
2
VOH. High-level output voltage
VOL
SN7483A
SN5483A
TEST CONDITIONSt
PARAMETER
Low-level output voltage
Input current at maximum
Vee= MIN,
11=-12mA
Vee= MIN,
VIH = 2 V,
VIL = 0.8 V,
IOH =MAX
Vec= MIN,
VIH=2V,
VIL=0.8V,
IOL = MAX
TYP* MAX
2.4
UNIT
V
2
0.8
0.8
V
-1.5
-1.5
V
2.4
3.4
0.2
0.4
V
3.4
0.2
1
VCC= MAX, VI = 5.5V
input voltage
MIN
0.4
1
V
mA
IIH
High-level input current
Vce= MAX, VI =2.4 V
40
40
".A
IlL
Low-level input current
Short-circuit
Any output except C4
Vec- MAX, VI =0.4V
-1.6
-1.6
mA
lOS
output current §
I
I Output e4
VCC=MAX
20
55
18
55
-20
70
-18
-70
All B low, other
ICC
Vce = MAX, inputs at 4.5 V
Outputs open All inputs at
Supply current
,
4.5V
56
mA
56
mA
66
99
66
110
t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:J:AIJ typical values are at V Cc '" 5 V. T A ::: 250 c.
§OnIY one output should be shorted at a time.
switching characteristics, Vee =5 V, TA = 25°e
PARAMETER~
tpLH
FROM (INPUT)
Co
TO (OUTPUT)
Any
~
TEST CONDITIONS
tpHL
eL=15pF,
tpLH
See Note 3
AjorBj
'".
-,
CO
C4
tpHL
tPLH
tpHL
eL= 15pF,
tPLH
See Note 3
tpHL
Aior Bj
C4
'tPLH = propagation delay time, low-to-high-Ievel output
tpHL = propagation delay time. high-to-Iow-Ievel output
NOTE 3: Load circuits and voltage waveforms are shown in Section 1 .
2-260
.' TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
RL=400n,
RL=780n,
MIN
TYP
MAX UNIT
14
21
12
21
16
24
16
24
9
14
11
16
9
14
11
16
ns
ns
ns
ns
SN54LSB3A. SN74LSB3A
4-BIT BINARY FULL ADDDERS WITH FAST CARRY
recommended operating conditions
SN74LS83A
SN54LS83A
Supply voltage, Vee
Hjgh~level
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-400
I'A
S
mA
70
"e
-400
output current, IOH
4
Low-level output current, IOL
-55
Operating free-air temperature, T A
UNIT
MIN
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
High·level
IIH
IlL
lOS
11= -lSmA
Vee=MIN,
VIH - 2 V,
Vee= MIN,
VIL = VIL max,
2.5
SN74LS83A
MAX
TVP:j: MAX
UNIT
V
2
0.7
O.S
V
-1.5
-1.5
V
3.4
2.7
0.4
Any A or B
Vee= MAX,
MIN
10L = SmA
VI = 7V
eo
V
3.4
0.25
0.4
0.35
0.5
0.2
0.2
0.1
0.1
40
40
V
mA
en
Q)
I'A
'SQ)
(.)
Any A or B
input current
eo
Low-level
Any A or B
input current
eo
Short-circuit output current §
Vee = MAX,
VI=2.7V
Vee= MAX,
VI = 0.4V
All inputs
All B low, other
Vee = MAX,
Supply current
inputs at 4.5 V
Outputs open
All inputs at
4.5V
20
20
O.S
O.S
-0.4
-0.4
-100
-20
Vee= MAX
grounded
lee
TVP:j:
0.25
VIH=2V, JlOL=4mA
VIL = VIL max
at maximum
input voltage
Vee = MIN,
10H = -4001'A
VOL Low-level output voltage
II
MIN
2
VOH High-level output voltage
Input current
SN54LS83A
TEST CONDlTlONSt
PARAMETER
-100
-20
22
39
22
39
19
34
19
34
19
34
19
34
C
mA
..oJ
lI-
mA
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
~AII typical values are at Vee = 5 V, T A = 25° C.
§ Only one output should be shorted at a time, and duration of the short·circuit should not exceed one second.
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER~
FROM (INPUT)
TO (OUTPUT)
TEST CONDITIONS
MIN
TVP
MAX UNIT
16
24
tpHL
15
24
tpLH
15
24
15
24
11
17
tPHL
15
22
tpLH
11
17
12
17
tpLH
tpHL
tPLH
tpHL
eo
AiorBj
eo
Ajor Bj
Any
~
~.
I
eL=15pF,
See Note 3
e4
e4
RL = 2 kll,
ns
ns
ns
ns
'tPLH = propagation delay time, low·to~high-Ievel output
tpHL = propagation delay time, high-to-low~level output
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-261
-I
-I
r-
o
(t)
<
(")
(t)
CJ)
2-262
SN5485, SN54LS85, SN54S85
SN7485, SN74LS85, SN74S85
4·81T MAGNITUDE COMPARATORS
MARCH 1974 - REVISED MARCH 1988
TYPE
'85
'L585
'585
TYPICAL
POWER
DISSIPATION
275mW
52 mW
365 mW
SN5485, SN54LS85, SN54S85 •• _ J OR W PACKAGE
SN7485 ___ N PACKAGE
SN74LS85, SN74S85 _ .. 0 OR N PACKAGE
TYPICAL
DELAY
14-BIT WORDS)
23 ns
24 ns
11 ns
ITOP VIEWI
B3
description
These four-bit magnitude comparators perform
comparison of straight binary and straight BCD (B-4-2-1)
codes. Three fully decoded decisions about two 4-bit
words IA. B) are made and are externally available at three
outputs. These devices are fully expandable to any
number of bits without external gates. Words of greater
length may be compared by connecting comparators in
cascade. The A > B, A < B, and A = B outputs of a
stage handling less-significant bits are connected to the
corresponding A > B, A < B, and A = B inputs of the
next stage handling more-significant bits. The stage
handling the least-significant bits must have a high-level
voltage applied to the A = B input. The cascading paths
of the '85, 'LS85, and 'S85 are implemented with only
a two-gate-Ievel delay to reduce overall comparison times
for long words. An alternate method of cascading which
further reduces the comparison time is shown in the
typical application data.
VCC
A Bin
A3
A> Bout
A=Bout
A< Bout
GND
A1
B1
AO
BO
B2
A2
SN54LS85, SN54S85 ... FK PACKAGE
ITOP VIEW)
3
A=Bin
A> Bin
NC
A> Bout
5
6
7
A= Bout
8
2
1 20 19
4
NC - No internal connection
FUNCTION TABLE
COMPARING
CASCADING
INPUTS
OUTPUTS
INPUTS
A3, B3
A2.B2
A1, B1
AO. BO
A> B
AB
A 83
X
X
X
X
X
X
H
L
A = B
L
A3 < 83
X
X
X
X
X
X
L
H
L
A3 = 83
A2 > B2
X
X
X
X
X
H
L
L
A3" = B3
A2 < B2
X
X
X
X
X
L
H
L
A3 = 82
A2 = B2
Al > 81
X
X
X
X
H
L
L
A3 = 83
A2 = 82
Al < 81
X
X
X
X
L
H
L
A2 = 83
A2 = 82
AI = 81
AD> 80
X
X
X
H
L
L
A3 = 83
A2 = 82
AI = 81
AO < 80
X
X
X
L
H
L
A3 = 83
A2 = 82
AI = 81
AD = 80
H
L
L
H
L
L
A3 = 83
A2 = 82
AI = 81
AO = 80
L
H
L
L
H
L
A3 = 83
A2 = 82
AI = 81
AO = 80
X
X
H
L
L
H
A3 = 83
A2 = 82
AI = 81
AD = 80
H
H
L
L
L
L
A3 = 83
A2 = 82
AI = 81
AO = 80
L
L
L
H
H
L
PRODUCTION DATA d......nt••••toi. i.lor...ti••
current IS of publication dltt. Praducts co.fe'lA to
specificatiDns per the terms at rillS Instruments
:::==i~.i~:I:~i ~=:~ti:.n :'~D::;:::::.!.~
not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
2-263
SN5485, SN54LS85, SN54S85,
SN7485, SN74LS85, SN74585
4·81T MAGNITUDE COMPARATORS
logic diagrams (positive logic)
-
I
A3
B3
A2
B2
AB
-t
-t
~
Al
Bl
C
(151
.~
(11
(13)
)1141
(21
~->-
}--
Qk-,,,
-
;>
~
;:::F3
)-
(6)
(3)
4)
~
(121
p-
(11)
CD
<
L
~
-
(i'
(II
AO
~
-
(10)
(9)
81_",
)-
logic symbol t
PO
Pl
(101
P2
P3
PO
02
Q3
(7)
P
QO
01
COMP
}
(11)
(14)
(1)
:}
P>O
PO
tThis symbol is in aeeordanese with ANSI/IEEE Std 91-1984 and )Ee Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
2-264
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TeXAS 75265
A=B
)-
~~
CD
eo
A>B
A - - -
----<~--_
VCC---1IT---
~
ReQ - 17 k!2
' '"'W--
INPUT--~~~~-~
INPUT
A
Req
= B,
Any A or B:
Req = 1.67 kll NOM
A> B, A < B:
Req = 4 kll NOM
A
= B,
A
> B, A < B:
Any A or B:
Req = 933 II NOM
Req = 2.8 kll NOM
I/)
TYPICAL OF ALL OUTPUTS
FOR '85
TYPICAL OF ALL OUTPUTS
FOR'LS85
Q)
(,)
TYPICAL OF ALL OUTPUTS
FOR'S85
'S:
Q)
-----~~---VCC
--"'--VCC
120
n
o
-----~---VCC
NOM
-J
lI-
~~~--OUTPUT
OUTPUT
OUTPUT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN54'
SN74LS'
UNIT
7
7
7
V
Input voltage
5.5
7
5.5
7
V
Interemitter voltage (see Note 2)
5.5
Supply voltage,
Operating
Vee
free~air
(see Note 1)
temperature range
Storage temperature range
NOTES:
SN54LS'
SN74'
7
SN54S'
SN74S'
5.5
V
- 55 to 125
-0 to 70
°C
-65 to 150
-65to 150
°C
1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter input transistor. This rating applies to each A input in conjunction with
its respective B input of the '85 and 'S85.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-265
SN5485. SN1485
4-81T ,.,AGNITUDE COMPARATORS
recommended operating conditions
SN7485
SN5485
MIN
4.5
Supply voltage, Vee
NOM
MIN
NOM
MAX
5.5
4.75
5
5.25
-400
/lA
16
rnA
70
°e
5
-400
High-level output current, IOH
Low-level output current, tOl
Operating free-air temperature, T A
16
-55
UNIT
MAX
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
V,H
High-level input voltage
V,L
Low-level input voltage
V,K
I nput clamp voltage
VOH
VOL
TEST eONDITIONSt
2
High-level output voltage
Low-level output voltage
I nput current at maximum input voltage
"
-I
-I
rC
CD
<
(i"
MIN TYP* MAX UNIT
A
< B. A > 8
inputs
Vee = MIN,
1,=-12rnA
Vee - MIN,
V,H = 2 V,
V,L = 0.8 V,
10H = -400/lA
Vee = MIN,
V,H = 2 V,
V,L = 0.8 V,
10L = 16 rnA
Vee = MAX,
V, - 5.5 V
Vee = MAX,
V, = 2.4 V
Vee = MAX,
V, = 0.4 V
"H
High-level input current
',L
Low-level input current
'OS
Short-circuit output current§
Vee = MAX,
Vo =0
ICC
Supply current
Vee = MAX.
See Note 4
all other inputs
A < B, A > B inputs
all other inputs
2.4
V
0.8
V
-1.5
V
3.4
0.2
V
0.4
1
40
120
-1.6
-4.8
I SN5485
I SN7485
-20
-55
-18
-55
55
88
V
rnA
/lA
rnA
rnA
rnA
CD
fA
tFor conditions shown as MIN or MAX, usa the appropriate value specified under recommended operating conditions.
tAli tvpical values are at Vee"" S V, T A"" 2SoC.
§Not more than one output should be shorted at a time.
NOTE 4: ICC is measured with outputs open, A "" B grounded, and all other inputs at 4.5 V.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~
tPLH
FROM
TO
NUMBER OF
INPUT
OUTPUT
GATE LEVELS
Any A or B data input
A < B, A >B
TEST CONDITIONS
Any A or B data input
7
12
3
17
26
A=B
4
23
35
A< B, A>B
2
3
A=B
4
ns
11
eL = 15 pF,
RL = 400
See Note 5
n,
15
20
30
20
30
ns
tpLH
A < BorA = B
A>B
1
7
11
ns
tPHL
AB
11
17
ns
tpLH
A=B
A
B
1
2
13
20
ns
tPHL
A=B
A-B
2
11
17
ns
tPLH
A> BorA - B
A B or A = B
A<8
1
11
17
ns
'tPLH = propagation delay time. low-to-high-Ievel output
tPHl = propagation delay time, high-to-Iow-Ievel output
NOTE 5: Load circuits and voltage waveforms are shown in Section 1.
. TEXAS.
2-266
TYP MAX UNIT
2
1
tPHL
MIN
1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS8L SN74LS85
4·81T MAGNITUDE COMPARATORS
recommended operating conditions
SN54LS85
MIN
Supply voltage. Vee
NOM
4.5
SN74LS85
MAX
MIN
NOM
5.5
4.75
5
5
-400
High-level output current, IOH
MAX
5.25
V
-400
)JA
8
rnA
70
"e
4
Low-level output current, IOl
Operating free-air temperature, T A
-55
125
UNIT
0
electrical chilracteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
TEST eONDITloNst
Vee = MIN.
11=-18rnA
Vee - MIN.
VIH-2V.
VIL=VILrnax.IOH=-400)JA
Vee= MIN.
VOL Low-level output voltage
I nput current
A
2.5
A < B, A
> B inputs
input current
all other inputs
Low-level
A < B. A > B inputs
all other inputs
input current
TYPj:
IOL=8rnA
Vee= MAX.
VI = 7V
V
0.7
V
-1.5
-1.5
V
3.4
2.7
0.4
3.4
Vee = MAX.
VI=2.7V
Vee= MAX.
VI = 0.4 V
lOS
ICC
Supply current
Vee- MAX.
V
0.25
0.4
0.35
0.5
0.1
Vee= MAX
UNIT
V
VIH = 2 V.
VIL=VILrnax
Short-circuit output current ~
MAX
2
0.25
IIOL = 4 rnA
(I
MIN
0.7
0.1
rnA
all other inputs
input voltage
High-level
IlL
SN74LS85
MAX
< B, A > B inputs
atmaxirnum
IIH
TYP~:
2
VOH High-level output voltage
II
SN54LS85
MIN
0.3
0.3
20
20
60
60
-0.4
-0.4
-1.2
-1.2
-20
See Note 4
-100
10.4
-20
20
en
Q)
.~
:>
Q)
,.,A
C
rnA
-100
rnA
10.4
20
rnA
TYP
MAX
...J
lI-
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vec = 5 V, T A = 25°C.
~Not more than one output should be shorted at a time, and duration of the short·circuit should not exceed one second.
NOTE 4: ICC is measured with outputs open, A "" B grounded, and all other inputs at 4.5 V_
switching characteristics, Vee = 5 V, T A = 25° C
PARAMETER'I
FROM
TO
NUMBER OF
INPUT
OUTPUT
GATE LEVELS
TEST CONDITIONS
1
tPLH
tpHL
'tPLH
tpHL
=
Any A or B data input
Any A or B data input
A < B. A > B
MIN
UNIT
14
2
19
3
24
36
A-B
4
27
45
1
11
A < B. A> B
2
3
15
A=B
4
CL
RL
= 15pF.
= 2 kQ.
See Note 5
20
30
23
45
ns
ns
tpLH
AB
1
14
22
ns
tpHL
AB
1
11
17
ns
tPLH
A-B
A=B
2
13
20
ns
tPHL
A-B
A-B
2
13
26
ns
tpLH
A> B or A - B
ABorA~B
A B inputs
all other inputs
A < B, A > B inputs
all other inputs
Vee= MAX,
VI =2.7 V
Vec= MAX,
VI = 0.5 V
Supply current
V
V
mA
50
150
IJA
-100
73
I
SN54S85W
V
1
-6
-40
Vee = MAX, T A = 125" e,
See Note 4
V
-1.2
-2
Vec= MAX
(1)
(I)
0.8
0.5
VIL = 0.8 V,
Vce= MAX, See Note 4
lee
MIN
2
VOL
-t
-t
r(1)
TEST CONOITIONSt
mA
mA
115
110
mA
tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vce "" 5 V, T A = 25"C.
!*Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second_
NOTE 4: ICC is measured with outputs open, A :. B grounded, and all other inputs at 4.5 V.
switching characteristics, Vee =5 V, TA =25°e
PARAMETER'I
FROM
TO
NUMBER OF
INPUT
OUTPUT
GATE LEVELS
TEST CONOITIONS
A < B, A> B
tpLH
Any A or B data input
A-B
tpHL
Any A or B data input
tpLH
A < BorA = B
A>B
tpHL
tpLH
AB
A=B
tpHL
A-B
A-B
tPLH
A>BorA-B
A BorA
A B
MIN
5
1
TEXAS'"
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS, TeXAS 75266
7
11
16.5
11
16.5
ns
ns
5
7.5
ns
5.5
7
8.5
10.5
ns
5
7.5
ns
5
5.5
7.5
ns
8.5
ns
ns
SN5485, SN54LS85, SN54S85,
SN7485, SN74LS85, SN74S85
4·81T MAGNITUDE COMPARATORS
TYPICAL APPLICATION DATA
INP UTS
(MSB) B23
A23
B3
A3
COMPARISON OF TWO N-BIT WORDS
This application demo nstrates how these magnitude
comparators can be cascaded to compare longer
words. The example ill ustrated shows the comparison
of two 24-bit wor ds; however, the design is
expandable to n-bits. As an example, one comparator
can be used with fi ve of the 24-bit comparators
illustrated to expand the word length to 120-bits.
Typical comparison ti mes for various word lengths
using the '85, 'L585, or '585 are:
822
B2
A22
A2
821
Bl
Al
A21
820
A20
B19
A19
BO
AO
AB
BIS
AIS
B3
A3
B17
A17
B2
B16
Bl
A16
AO
BO
B15
A15
B14
A14
AO
A B
B3
A3
B12
B2
A2
Bl
Al
A9
B8
A9
B7
A7
B6
A9
BS
AS
B4
A4
B3
A3
82
A2
Bl
Al
(LSB) BO
AO
'S5
'LSS5, 'SS5
WORD
LENGTH
1·4 bits
5-24 bits
25-120 bits
A2
B13
A13
A12
Bll
All
Bl0
Ala
B9
AB
BO
AO
Aa
AB
NUMBER
OF PK GS
1
2·6
8-31
'85
23 ns
46 ns
69 ns
'LSB5
24 ns
48 ns
72 ns
'S85
11 ns
22 ns
33 ns
'S5
'LSS5, 'SS5
-A B
'S6
'LS86, 'S8S
B3
A3
B2
A2
Bl
AI
BO
r - - AO
, . - A a
OU TPUTS
AB I - -
r--
'86
'LS8S, 'S86
B3
A3
a2
A2
al
AI
BO
AO
Aa
AB
'8S
'LSSS, 'SSS
B3
A3
82
A2
Bl
Al
so
AO
L - AB
AB
'S5
'Lse5, '586
COMPARISON OF TWO 24·BIT WOROS
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-269
-I
-I
r-
C
CD
!S.
(")
CD
C/I
2-270
SN6486. SN64LS86A. SN64S86.
SN7486. SN74LS86A. SN74S86
QUADRUPLE 2·INPUT EXCLUSIVE·DR GATES
DECEMBER 1972 - REVISED MARCH 1988
•
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Standard Plastic and
Ceramic 300-mil DIPs
SN5486, SN64LS86A, SN64S66 •.• J OR W PACKAGE
SN7486 .•• N PACKAGE
SN74LS86A, SN74S86 ••• 0 OR N PACKAGE
(TOP VIEWI
1A
1B
1Y
2A
2B
2Y
Dependable Texas Instruments Quality and
Reliability
TYPE
TYPICAL AVERAGE
TYPICAL
PROPAGATION
TOTAL POWER
DELAY TIME
DISSIPATION
'86
14 ns
150mW
'LS86A
10 ns
30.5 mW
7 ns
250 mW
'S86
VCC
48
4A
4Y
38
3A
3Y
GND
SN54LS86A, SN54S86 .•. FK PACKAGE
(TOPVIEWI
u
description
~ ~ ~ ~~
These devices contain four independent 2-input
Exclusive-OR gates. They perform the Boolean
functions Y = A Ell B = AB + AS in positive
logiC.
3 2 1 20 19
1Y
4
NC
5
NC
2A
6
4Y
A common application is as a true/complement
element. If one of the inputs is low, the other
input will be reproduced in true form at the
output. If one of the inputs is high, the signal on
the other input will be reproduced inverted at the
output.
NC
7
NC
28
B
The SN5486, 54LS86A, and the SN54S86 are
characterized for operation over the full military
55°C to 125°C. The
temperature range of
SN7486, SN74LS86A, and the SN74S86 are
characterized for operation from 0 °C to 70°C.
NC - No internal connection
4A
CI)
Q)
(,)
.s:
38
Q)
9 10 111213
o
....
)-ou)-«
NZZMM
Cl
l-
I-
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE·OR
These are five equivalent Exclusive-OR symbols valid for an '86 or 'LS86A gate in positive logic; negation
may be shown at any two ports.
LOGIC IDENTITY ELEMENT
EVEN·PARITY
ODD·PARITY ELEMENT
=E}The output is active !lowl if all
inputs stand at the same logic
level (i.e., A =BI.
The output is active !low) if an
even number of inputs (i.e' r 0 or
The output is active (highl if an
odd number of inputs (i.e., only 1
21 are active.
of the 2) are active.
PRODUCTION DATA documants contain information
current as of publication data. Products conform to
specifications per the terms of Taxas Instruments
:~~~~:~~i~a{::1~7i ~::i:~ti:; :'~O::~:::::t:~~S not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-271
SN5486, SN54LS86A, SN54S86,
SN7486, SN74LS86A, SN74S86
QUADRUPLE 2·INPUT EXCLUSIVE·OR GATES
schematics of inputs and outputs
0--
logic symbol t
'86
TYPICAL OF
ALL OUTPUTS
EQUIVALENT OF
EACH INPUT
Vee
INPUT
4
kn
130
n
NOM
lA
lB
2A
Vee
2B
NOM
3A
--
3B
4A
OUTPUT
4B
(1)
=1
(2)
(3)
(4)
(6)
(5)
(9)
(8)
(10)
(12)
(11)
(13)
1V
2Y
3Y
4Y
tThis symbol is in accordance with
ANSI/IEEE Std. 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
'LS86A
FUNCTION TABLE
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
INPUTS
Vee
-I
-I
rC
12.5
kn
NOM
INPUT
OUTPUT
H
CD
<
C;CD
(II
'SB6
TYPICAL OF
ALL OUTPUTS
EQUIVALENT OF
EACH INPUT
vee
V~t~r
2.8
INPUT
2·272
kn
NOM
OUTPUT
--
.
TEXAS'"
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
:=
OUTPUT
Y
A
B
L
L
L
L
H
H
H
L
H
H
H
L
high level, L - low level
SN5486, SN7486
QUADRUPLE 2·INPUT EXCLUSIVE·OR GATES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
Supply voltage, Vee (see Note 1) . . . . .
Input voltage . . . . . . . . . . . . .
Operating free·air temperature range: SN5486
SN7486
Storage temperature range
5.5 V
-5Soe to 12Soe
oOe to 70°C
-6SoC to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN7486
SN5486
MIN
4.5
Supply voltage, Vee
High~level
NOM
5
MAX
5.5
MIN
4.75
NOM MAX
5
-BOO
output current, IOH
Low-level output currant, tOl
Operating free-air temperature, T A
16
125
-55
0
5.25
-800
16
70
UNIT
V
"A
mA
"e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONSt
MIN
High·leval input voltage
SN5486
TVP; MAX
2
VIH
VIL
V 11<
Input clamp voltage
VOH
High·level output voltage
VOL
Low·level output voltage
II
IIH
IlL
lOS
ICC
Input current at maximum input voltage
0.8
1.5
Low-level input vol tege
Vee' MIN,
Vec' MIN,
VIL = 0.8 V,
VCC' MIN,
VIL· 0.8 V,
11=-8mA
VIH' 2V,
10H' -800 "A
VIH' 2 V
10L '16mA
VCC' MAX, VI' 5.5 V
VCC'MAX, VI" 2.4 V
Vce' MAX, VI·0.4V
VCC· MAX
Vec'MAX, Sea Note 2
HIgh·levollnput current
Low·level input curront
Short·circuit output current~
Supply current
MIN
2
2.4
3.4
2.4
0.2
0.4
30
1
40
-1.6
-55
43
-20
SN7486
UNIT
TVp:l: MAX
V
V
0.8
1.5
V
3.4
V
0.2
0.4
V
mA
30
1
40
-1.6
-55
50
-18
"A
mA
mA
mA
tFor condition, ,hown II MIN or MAX. us. the appropriate ",.11.,. Ipeciflld under recomm,nded ope,atln; condltionl tor the applicable tyPI.
Ir. at Vee'" 0 V, T A'" 26(' C,
**AII typlca'ICCvllu ••mUlurod
with the
Not more than one output Ihoutd be shorted at II tIme,
NOTE 2:
II
Inputs groundld Ind thl outputs open.
switching characteristics, Vee"
PARAMETER~I
tpLH
tpHL
tPLH
tpHL
I)
V, TA" 21)°e
FROM
UNPUTI
TEST CONDITIONS
A or B
Other input low
A or B
Other input high
CL'15pF,
RL=400!l,
Se. No!e 3
MIN
TVP
15
11
18
13
MAX UNIT
23
17
30
22
n.
n.
'tPLH = propagation delay time, low-to-high-Iavel output
tPHL = propagation delay time, high-to-Iow-Ieval output
NOTE 3: Load circuits and voltage waveforms are shown In Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-273
SN54LS86A. SN74LS86A
QUADRUPLE 2·INPUT EXCLUSIVE·OR GATES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage,
Vee (see Note 1)
Input voltage
.....
.
7V
7V
.
-55°C to 125°C
oOe to 70°C
-65°C to 150°C
Operating free·air temperature range: SN54LS86A
SN74LS86A
Storage temperature range
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS86A
MIN
Supply voltage,
Vee
NOM
4.5
5
SN74LS86A
MAX
MIN
5.5
4.75
NOM
5
-400
High-level output current, IOH
4
Low-level output current, tOL
-55
Operating free-air temperature, T A
125
0
MAX
UNIT
5.25
V
-400
8
"A
mA
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
-I
-I
r-
VIH
High-level input voltage
C
VIL
Low-level input vol tage
S.
n
VIK
Input clamp voltage
VOH
High-level output voltage
(1)
(1)
VI
2
SN74LS86A
UNIT
MIN TYPt MAX
2
V
0.7
Vee- MIN,
Vee" MIN,
II" 18mA
VIH-2V,
VIL" VIL max, 10H "-400"A
Vee" MIN,
VOL Low-level output voltage
SN54LS86A
MIN TYPt MAX
TEST eONDITIONSt
PARAMETER
1.5
2.5
10L" 4mA
3.4
0.25
2.7
0.4
0.8
V
1.5
V
3.4
V
0.25
0.4
0.35
0.5
VIH"2V,
V
VIL "VILmax
IOL"8mA
II
Input current at maximum input voltage
Vee" MAX,
VI
0.2
0.2
mA
IIH
High-level input current
Vee- MAX,
VI-2.7V
40
40
IlL
Low-level input current
Vee
VI-O.4V
Short-circuit output current~
Vee- MAX
-0.8
-100
"A
mA
lOS
-0.8
-100
ICC
Supply current
Vee- MAX,
~
MAX.
~
7V
20
See Note 2
6.1
-20
10
6.1
10
mA
mA
tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions for the applicable typa.
tAil typical values are at V CC =- 5 V. T A ", 25" C.
!:i: Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER':
tpLH
FROM
A orB
tPHL
tPLH
tpHL
TEST CONDITIONS
IINPUT)
A or B
Other input low
Other input high
'tPlH = propagation delay time, low-to-high-Ievel output
tPHL = propagation delay time, high-to-Iow-Ievel output
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
2-274
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Cl
= 15 pF,
= 2 kQ,
Rl
See Note 3
MIN
TYP
MAX UNIT
12
23
10
17
20
13
30
22
ns
ns
S154S86, SI74S86
QUADRUPLE 2·IIPUT EXCLUSIVE·DR GATES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
.....
Operating free-air temperature range: SN54S86
SN74S86
Storage temperature range
7V
5.5V
-55°C to 125°C
oOe to 70°C
_65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54S86
MIN
Supply voltage, Vee
4.5
NOM
5
High-level output current. IOH
SN74S86
MAX
MIN
5.5
-1
4.75
Low·level output current, IOl
NOM
5
20
-55
Operating free-air temperature. T A
125
MAX
5.25
V
-1
rnA
20
mA
·e
70
0
UNIT
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONSt
MIN
SN54S86
TYp: MAX
II)
SN74S86
MIN
TYP. MAX
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
0.5
0.5
II
Input current at maximum input voltage
Vee
= MAX, VI = 5.5V
1
1
IIH
High-level input current
Vee = MAX, VI=2.7V
50
50
IJ.A
IlL
Low-level input current
Vee - MAX, VI
0.5V
2
2
mA
lOS
Short-circuit output current $?
Vee- MAX
lee
Supply current
Vee= MAX. See Note 2
2
Vee=MIN,
2
II = -18mA
Vee=MIN,
VIH=2V,
VIL = 0.8 V,
10H=-lmA
Vee-MIN,
VIH - 2V
VIL = 0.8 V,
101. = 20 mA
2.5
0.8
V
-1.2
-1.2
V
-40
2.7
-100
50
3.4
-40
75
'S:
V
0.8
3.4
50
CD
U
UNIT
CD
o
..J
V
lI-
V
mA
-100
mA
75
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type,
fAil typical values are at Vee = 5 V, T A = 25 u e.
1* Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2:
ICC is measured with the inputs grounded and the outputs open,
switching characteristics, Vee = 5
PARAMETER~
tpLH
V, TA = 25° e
FROM
A or8
tpHL
tPLH
tPHL
TEST CONDITIONS
(INPUT)
Other input low
eL=15pF,
RL=280n,
A or B
Other input high
See Note 3
MIN
TYP
MAX UNIT
7
10.5
6.5
10
7
10.5
6.5
10
ns
ns
1t
PLH = propagation delay time, low-to-high-Ievel output
tPHL = propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265
2-275
-I
-I
rC
CD
<
c:;-
CD
en
2-276
SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93,
SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93
DECADE. DIVIDE-BY-TWELVE AND BINARY COUNTERS
MARCH 1974-REVISED MARCH 1988
SN5490A, SN54LS90 ... J OR W PACKAGE
SN7490A ... N PACKAGE
SN74LS90 ... D OR N PACKAGE
'90A, 'LS90 ... Decade Counters
'92A, 'LS92 ... Divide By-Twelve Counters
(TOP VIEWI
'93A, 'LS93 ... 4-Bit Binary Counters
TYPES
TYPICAL
POWER DISSIPATION
'SOA
145mW
'S2A, 'S3A
130mW
'LSSO, 'LSS2, 'LS93
CKB
RO(1 )
CKA
RO(2)
QA
NC
NC
VCC
R91l)
R9(2)
45 mW
Qo
GNO
QB
8
Qc
description
Each of these monolithic counters contains four
master-slave flip-flops and additional gating to
provide a divide-by-two counter and a threestage binary counter for which the count cycle
length is divide-by-five for the '90A and 'LS90,
divide-by-six for the '92A and 'LS92, and the
divide-by-eight for the '93A and 'LS93.
SN5492A. SN54LS92 ... J OR W PACKAGE
SN7492A ... N PACKAGE
SN74LS92 ... D OR N PACKAGE
(TOP VIEWI
All of these counters have a gated zero reset and
the '90A and 'LS90 also have gated set-to-nine
inputs for use in BCD nine's complement
applications.
To use their maximum count length (decade,
divide-by-twelve, or four-bit binary) of these
counters, the CKB input is connected to the QA
output. The input count pulses are applied to
CKA input and the outputs are as described in
the appropriate function table. A symmetrical
divide-by-ten count can be obtained from the
'90A or 'LS90 counters by connecting the QD
output to the CKA input and applying the input
count to the CKB input which gives a divide-byten square wave at output QA-
CKA
CKB
NC
NC
NC
NC
QA
VCC
ROil)
RO(2)
QB
GNO
S
8
QC
QO
SN5493A, SN54LS93 ... J OR W PACKAGE
SN7493 •.. N PACKAGE
SN74LS93 ... D OR N PACKAGE
en
Q)
.2
>
Q)
o
..J
lI-
(TOP VIEWI
CKB
ROil)
RO(2)
NC
VCC
NC
NC
CKA
NC
QA
Qo
GNO
QB
QC
NC - No internal connection
PRODUCTION DATA documents contain information
currant as of publication date. Products conform to
spacifications per the tarms of Texas Instruments
::~::~~i~8i::I~~i ~!:~:~li:; ~r':::::~:~~ not
TEXAS
-II
INSTRUMENTS
POST OFFICE BOX 655012 .. DALLAS. TEXAS 75265
2-277
SN5490A, '92A,'93A, SN54LS90, 'LS92, 'LS93,
SN7490A, '92A, '93A, SN74LS90, 'LS92, 'LS93
DECADE, DIVIDE·B¥~TWELVE, AND BINARY COUNTERS
logic symbols t
'90
'93A, 'LS93
'92
&
Rom 161
CT-O
ROl21
&
&
CTR
ROlli 121
CT=O
ROl21 131
&
23
as
ac
O'V:Tf
as
3CT"4"1
aD
aD
ae
•
tTh8S8 symbols are In accordance with ANSI/IEEE Std. 91·1984 and lEe Publication 617·12.
~
~
C
CD
<
(i'
CD
en
2-278
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
eTR
CT=O
SN5490A, '92A, '93A, SN54LS90, 'LS92, 'LS93,
SN7490A, '92A, '93A, SN74LS90, 'LS92, 'LS93
DECADE, DIVIDE·BY·TWELVE, AND BINARY COUNTERS
'90A, 'LS90
BCD COUNT SEQUENCE
'90A, 'LS90
BI-QUINARY 15-2)
ISee Note A)
ISee Note B)
OUTPUT
COUNT
0
0
L
L
L
H
1
L
L
L
2
L
L
H
L
2
L
L
H
L
3
L
L
H
H
3
L
L
H
H
L
H
4
L
H
L
L
4
L
H
L
5
L
H
L
H
5
H
L
L
L
6
L
H
H
L
6
H
L
L
H
7
L
H
H
H
7
H
L
H
L
8
H
L
L
L
8
H
L
H
H
9
H
L
L
H
9
H
H
L
L
'90A, 'LS90
RESET/COUNT FUNCTION TABLE
ISee Note C)
RESET INPUTS
OUTPUT
COUNT
QO QC
QB
QA
ROIl)
H
L
L
H
OUTPUT
RO(2)
H
R9(l)
L
R9(2) QO QC QB QA
L
L
X
L
L
H
X
L
L
H
0
L
L
1
L
L
L
H
X
X
H
H
2
L
L
H
L
X
L
X
L
COUNT
L
L
L
L
L
H
3
L
L
H
H
L
X
L
X
COUNT
4
L
H
L
L
L
X
X
L
COUNT
X
L
L
X
COUNT
5
L
H
L
H
6
7
8
H
L
L
L
H
L
L
H
H
L
H
L
9
H
L
H
H
10
H
H
L
L
11
H
H
L
RESET INPUTS
QO
Oc
QB
QA
L
L
L
l
X
COUNT
X
L
COUNT
H
L
NOTES: A. Output QA is connected to input eKB for BCD count.
B. Output QO is connected to input CKA for bi-quinary
count.
C. Output QA is connected ~o input eKB.
high level, L
=
(.)
'S
Q)
C
...J
lI-
OUTPUT
QO QC
OUTPUT
RO(2)
Q)
ISee Note C)
COUNT
H
ROIl)
H
II)
'93A, 'LS93
COUNT SEQUENCE
'92A, 'LS92, '93A, 'LS93
RESET/COUNT FUNCTION TABLE
=
QA QO QC QB
L
L
L
L
1
'92A, 'LS92
COUNT SEQUENCE
D. H
OUTPUT
COUNT
QO QC QB QA
L
L
L
L
low level, X = irrelevant
..If
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
QB
QA
0
L
L
L
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
6
L
H
H
L
7
L
H
H
H
8
H
L
L
L
9
H
L
L
H
10
H
L
H
L
11
H
L
H
H
12
H
H
L
L
13
H
H
L
H
14
H
H
H
L
15
H
H
H
H
2-279
SN54S0A, 'S2A, 'SlA, SN54LSSO, 'LSS2, 'LSS3,
SN74S0A, 'S2A, 'S3A, SN74LSSO, 'LSS2, 'LSS3
DECADE, DIVIDE·BY·TWELVE,AND BINARY COUNTERS
logic diagrams (positive logic)
'S2A, 'LSS2
'SOA, 'LSSO
'S3A, 'LSS3
1'93AII'L931
CKB
111181
ROlli 121111
ROI2I 131121
The J and K inputs shown without connection are for reference only and are functionally at a high level.
Pin numbers shown in (I are for the 'LS93 and '93A and pin numbers shown in I J are for the 54l93.
schematics of inputs and outputs
'90A, 'S2A, '93A
EaUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC3-Req
INPUT
--
OUTPUT"
INPUT
CKA
CKB
CKB
('90A, '92A;
('93A)
All resets
2·280
Req NOM
2.5 kU
l,25k!!
2.5 k!!
6kl!
~
TEXAS
INSTRUMENTS
POST OFfiCE BOX 655012 • DALLAS, TEXAS 75265
SN54LS90, 'LS92, 'LS93,
SN74LS90, 'LS92, 'LS93
DECADE, DIVIDE·BY·TWELVE, AND BINARY COUNTERS
schematics of inputs and outputs (continued)
'LS90, 'LS92, 'LS93
EQUIVALENT OF EACH RESET INPUT
EQUIVALENT OF A ANO B INPUTS
TYPICAL OF ALL OUTPUTS
- - - - -....-VCC
R2
R1
VCC--.....- -
120 !lNOM
R3
2Ok!lNOM
INPUT
INPUT~~""-'"
INPUT
NOMINAL VALUES
R1
R2
R3
CKA
10 kn
CKB ('LS90, 'LS92) 6.7 kn
CKB ('LS93)
15 kn
10 kn
6.7 kn
15 kn
10 kn
5 kn
10 kn
...I
lI-
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 15265
2-281
SN5490A. SN5492A. SN5493A. SN7490A. SN7492A. SN7493A
DECADE. DIVIDE:BY-TWELVE. AND BINARY COUNTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
Interemitter voltage (see Note 2)
Operating free·air temperature range: SN5490A, SN5492A, SN5493A
SN7490A, SN7492A, SN7493A
Storage temperature range
NOTES;
7V
5.5 V
5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C
1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple emitter transistor. For these circuits, this rating applies between the two RO
inputs, and for the 'gOA circuit. it also applies between the two Rg inputs.
recommended operating conditions
SN5490A, SN5492A SN7490A, SN7492A
SN5493A
MIN
Supply voitage, Vee
4.5
NOM
5
Low-level output current, tOl
r-
C
en
<
n~
MIN
5.5
4.75
NOM
5
-SOO
High-level output current, IOH
-t
-t
SN7493A
MAX
Pulse width, tw
16
0
32
B input
0
16
A input
15
15
8 input
30
30
Reset inputs
15
15
Reset inactive-state setup time, tsu
25
Operating free-air temperature, T A
55
5.25
-SOO
16
A input
Count frequency. fcount (see Figure 1 ~
UNIT
MAX
0
32
0
16
rnA
MHz
ns
25
125
V
~A
ns
0
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER •
VIH
High-level input voltage
VIL
V IK
Low-level input voltage
Input clamp voltage
VOH High·level output voltage
VOL Low-level output voltage
Input current at
II
maximum input voltage
TEST eONOITIONSt
'90A
MIN
TYP:': MAX
2
Vee = MIN,
11= -12 rnA
Vee - MIN,
VIH - 2 V,
VIL =O.SV, 10H = -SOO ~A
Vee = MIN,
VIH = 2 V,
VIL = O.S V,
10L = 16 rnA~1
2.4
High·level
Low-level
IlL
eKA
eKB
input current
eKA
0.2
Vee = MAX, VI = 2.4 V
Vee = MAX, VI =O.4V
eKB
Short-circuit
I SN54'
I SN74'
output current ~
Vee" MAX
lee
Supply current
Vee = MAX, See Note 3
MIN
'93A
TYp:,:
MAX
UNIT
V
2
O.S
O.S
V
-1.5
-1.5
-1.5
.v
2.4
3.4
0.2
0.4
2.4
0.2
0.4
V
3.4
0.4
1
1
1
40
40
40
Vee= MAX,. VI = 5.5 V
lOS
MAX
O.S
3.4
Any reset
input current
'92A
TYp:,:
2
Any reset
IIH
MIN
SO
SO
SO
120
120
SO
-1.6
-1.6
-1.6
-3.2
-3.2
-3.2
~4.S
-4.S
-3.2
-20
-57
-20
-57
-20
-IS
-57
-IS
-57
-·18
29
42
26
39
-57
-57
26
39
V
rnA
~A
rnA
rnA
rnA
t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
~AII typical values are at V CC ~ 5 V, T A = 25'·C.
:.. Not more than one output should be shorted at a time.
-I QA outputs are tested at IOL "" 16 mA plus the limit value for IlL for the CKB input. This permits driving the eKB input while maintaining
full fan·out .capability.
NOTE 3: ICC is measured with ail outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.
2-282
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 855012 • DAllAS, TEXAS 75285
SN5490A, SN5492A, SN5493A, SN7490A, SN7492A, SN7493A
, DECADE, DIVIDE·BY·TWELVE, AND BINARY COUNTERS
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETERt
f max
'PLH
FROM
TO
IINPUT)
(OUTPUT)
CKA
°A
Os
CKB
CKA
'PHL
'pLH
CKA
'pHL
'pLH
tpLH
Os
eKB
°c
CKB
'pHL
'pLH
Set-to-O
5.'-'0-9
'PHL
32
'90A
'92A
'93A
TYP MAX MIN
TYP MAX MIN
TYP MAX
42
32
16
42
32
42
16
10
16
10
16
12
18
12
18
12
18
32
48
32
48
46
70
34
50
34
50
46
70
CL = 15pF,
10
16
10
16
10
16
n,
14
21
14
21
14
21
RL = 400
See Figure 1
°D
21
32
10
16
21
32
23
35
14
21
23
35
21
32
21
32
34
51
23
35
23
35
34
51
26
40
26
40
Any
26
40
°A,OO
20
30
°S,OC
26
40
t f max == maximum count frequency
UNIT
MHz
16
16
10
°D
CKB
'PHL
MIN
°A
'pHL
'pLH
tpHL
TEST CONDITIONS
ns
ns
ns
ns
ns
ns
ns
en
tpLH '" propagation delay time, low-to-high-Ievel output
tpHL " propagation delay time, high-to-Iow-Ievel output
CD
CJ
'S;
CD
o
-'
lI-
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-283
SN54LS90. SN54LS92; SN54LS93.
SN74LS90. SN74LS92, SN74LS93
DECADE, DIVIDE·BY·TWELVE, AND BINARY COUNTERS
absolute maximum ratings oyer operating free·air temperature range (unless otherwise noted)
7V
7V
5_5 V
_55°C to 125°C
O°C to 70°C
_65°0 to 150°C
Supply voltage, VCC (see Note 1)
Input voltage: R inputs
A and B inputs
Operating free-air temperature range: SN54LS' Circuits
SN74LS' Circuits
Storage temperature range
NOTE
~;
Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS90
SN74LS90
SN54LS92
SN74LS92
SN54LS93
MIN
4.5
Supply voltage, Vee
NOM
5
A input
4.75
0
32
5
5.25
.-400
16
8
0
32
0
16
B input
0
A input
15
15
B input
30
30
Reset i npu ts
30
30
-I
-I
Pulse width, tw
C
Reset inactive-state setup time, tsu
25
Operating free-air temperature, T A
-55
<
O·
5.5
UNIT
SN74 LS93
NOM MAX
4
Low-level output current, IOL
Count frequency, fcount {see Figure 11
(I)
MIN
-400
High-level output current, IOH
r-
MAX
rnA
MHz
ns
ns
25
125
V
~A
0
70
Pe
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
(I)
til
PARAMETER
TEST CONOITIONSt
SN54LS90
SN74 LS90
SN54LS92
SN74LS92
MIN
VIH
High-level input voltage
VIL
LOW-level input voltage
VIK
Input clamp voltage
VOH High-level output voltage
VOL LOW-level output voltage
II
Input current
Any reset
at maximum
CKA
input voltage
CKB
High-level
IIH
input current
Low-level
IlL
input current
Vec = MIN,
II = -18 rnA
Vee = MIN,
VIH = 2 V,
VIL = VILmax,
IOH = -400~A
Vee = MIN,
VIH=2V,
2.5
IIOL = 4 mA~
Vec = MAX,
VI = 7 V
Vee= MAX.
VI=5.5V
Vee = MAX,
VI = 2.7 V
eKB
Any reset
eKA
CKB
Vce= MAX,
VI =O.4V
V
V
-1.5
-1.5
V
2.7
0.4
Short-circuit output current§
Vee= MAX
Supply current
Vee = MAX,
-20
See Note 3
I 'LS90
0.4
0.35
0.5
I
'LS92
V
0.1
0.1
0.2
0.2
0.4
20
0.4
20
40
40
80
80
-0.4
-0.4
-2.4
-2.4
-3.2
rnA
-100
rnA
-100
9
9
V
3.4
0.25
-3.2
lOS
UNIT
MAX
0.8
jlOL =8 mA~
VIL = VIL max,
TYP*
0.7
3.4
0.25
Any reset
eKA
MIN
2
2
Ice
..
TYP; MAX
-20
15
9
15
15
9
15
rnA
IlA
rnA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions •
tAli typical values are at Vce =: 5 V, TA =: 25°C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
QA outputs are tested at specified IOL plus the limit value of II L for the eKB input. This permits driving the CKB input while maintaining
~
full fan-out capability.
NOTE 3: ICC fs measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other ilJputs
grounded.
.
2-284
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, nXAS 75265
SN54LS90, SN54LS92, SN54LS93,
SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE·BY·TWELVE, AND BINARY COUNTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIH
High-level input voltage
VIL
VIK
Low·level input voltage
Input clamp voltage
VOH High·level output voltage
VOL Low·level output voltage
Input current
SN74LS93
SN54LS93
TEST CONOITIONSt
PARAMETER
MIN
TYPt
MAX
MIN
2
VCC = MIN,
11=-18mA
VCC = MIN,
VIH = 2 V,
2.5
VIL=VILmax, 10H = -400 "A
VCC- MIN,
VIH=2V,
!lOL - 4 mA~
V
0.8
V
-1.5
-1.5
V
2.7
3.4
0.25
3.4
0.4
V
0.25
0.4
0.35
0.5
Any reset
Vce= MAX,
VI = 7 V
0.1
0.1
input voltage
CKAor CKB
VCC = MAX,
VI = 5.5 V
0.2
0.2
IIH
High-level
Any reset
input current
CKAor eKB
VCC = MAX,
VI = 2.7 V
IlL
low-level
input current
V
mA
at maximum
II
UNIT
0.7
IIOL=8mA~
VIL = VIL max
TYPt MAX
2
Any reset
CKA
VCC = MAX,
VI=O.4V
CKB
lOS
Short-circuit output current* VCC = MAX
Ice
Supply current
VCC = MAX,
-20
20
20
40
-0.4
80
-0.4
-2.4
-2.4
-1.6
-1.6
-100
9
See Note 3
-20
9
15
"A
rnA
-100
mA
15
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions
:~AII typical values are at Vee = 5 V, T A = 25"C.
~ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
~ QA outputs are tested at specified IOL plus the limit value for IlL for the CKB input. This permits driving the CKB input while maintaining
full fan-out capability.
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER#
f mc!)(
'pLH
FROM
TO
(INPUT)
(OUTPUT)
CKA
°A
32
CKB
°B
16
CKA
°A
'PHL
'PLH
CKA
TEST CONDITIONS
00
'PHL
'pLH
'PHL
IpLH
CKB
CKB
'PHL
'PLH
'PHL
IpHL
'PLH
IpHL
°B
'LS90
MIN
TYP MAX MIN
42
32
'LS93
'LS92
UNIT
TYP MAX MIN TYP MAX
42
32
16
42
MHz
16
10
16
10
16
10
16
12
18
12
18
12
18
32
48
32
48
46
70
34
50
34
50
46
70
CL=15pF,
10
16
10
16
10
16
RL=2kfl
14
21
14
21
14
21
See Figure 1
21
32
10
16
21
32
23
35
14
21
23
35
32
34
51
°c
eKB
21
32
21
°D
23
35
23
35
34
51
Set·to·Q
Any
26
40
26
40
26
40
°A,OD
20
30
°B,OC
26
40
Set-to-g
ns
ns
ns
ns
ns
ns
ns
#fmax ;:;;; maximum count frequency
tpLH
propagation delay time, low-to-high-Ievel output
tpHL " propagation delay time, high-to-Iow-Ievel output
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-285
sao!J\aa 1.1.1
N
'"
CHl.len
(Xl
m
rn22
n .....
U'I
~oIIoollo
C CD CD
PARAMETER MEASUREMENT INFORMATION
rn CI CI
" ~~
C" "
RESET-TO-S
INPUTS
- - - - - - - - - - - ____ -
M
tou
~~
~.
OUTPUTQA:
CLOC~~OINPUT
1
tpH L
I
f
tpHL ,-1_
_.
~
- - " ' -..... 1
OUTPUT QS
:
\
(See Note E)
1
Vrsf
tPHL
-
\
I
-
1.
I
.
_ _ _..J
Vref
,-
0,
I
attn+l
1
Vref
II
I
t.----.:
If"!
t
:ECl.len
'ov
......... U'I
rn22
~oIIoollo
."
"
L.---.f- tpHL - Measure at tn + 2
1
I
\ . V re!
Vref
~tPLH-Mea.ure
*.
r--rl-
f
~
I
Vref
II
tPHL
Vref
IS
tpLH-Measure at t + 8
('SOA, 'S3A, 'lSSO, ~LSS31,
'
or at tn + 6 ('92A, LSS2AI
, Vref
I
,-
Vref
1
O(} tPLH-Measure at tn+4 I_
I
1
1
~
1
{I
If
1
/Vref
-
I
I
~
,e
I
Ie
01
I
/
'\
II
Vref
NOTES: A. Input pulses are supplied by a generator having the following characteristics:
for 'SOA, 'S2A, 'S3A, tr S 5 ns, tf S 5 ns, PRR = 1 MHz, duty cycle = 50%, Zout ~ 50 ohms;
for 'LSSO, 'LS92, 'LSS3, tr S 15 ns, tf s5 ns, PRR = 1 MHz, duty cycle = 50%, Zout ~ 50 ohms.
B. Cl includes probe and jig capacitance.
C. All diodes are 1 N3064 or equivalent.
D. Each reset input is tested separately with the other reset at 4.5 V.
FIGURE 1A
1.3 V.
~
--f--d~
(See Note Al
INPUT A
I
CLT
I
See
IL _
NoteB':"
_ _ _ _ _ _ _ _ _ __.-.JI
2.4 V
TEST CIRCUIT
n
n---n n n----J1JlJlJ1IT--IUUlJ1J1
I U L_J U U L__
__
1
::tr-
CLOCK-PULSE
INPUT
C
INPUT A
CD
<
(;'
2
thru
7
L____
OUTPUTOH _ _ _ _ _ _ _
CD
8
9
thru
15
16
17
18
19 thru 23
24
25
26
27
____ -.lL ___________
Sl____
____ F L
(II
TVPICAL INPUT/OUTPUT WAVEFORMS
;r.:,,~--3V
CLOCK
INPUT
CLOCK
INPUT
I
-I----OV
I
I
I
r-------------3V
I
I
tPH L
INPUT
AOR B
I
I
I
---i-----'
-1- -
--..&.-
~-~-:-
tPLH-t---!
-- -----OV
th
-
-
-
-
---3V
INPUT
'--------------0 V
PROPAGATION DELAV TIMES VOLTAGE WAVEFORMS
SWITCHING TIMES VOLTAGE WAVEFORMS
NOTES: A. The generator has the following characteristics: tw(clockl = 500 ns, PRR " 1 MHz, Zout '" 50
t r " 10 ns and tf " 10 ns; for SN64LS91, tr = 15 ns, and tf = 6 ns.
8. CL includes probe and jig capacitance.
C. All diodes are lN3064 or equivalent.
D. For SN6491A/SN7491A, Vref
1.5 V; for'SN64LS911SN74LS91, Vref
1.3 V.
=
=
FIGURE I-SWITCHING TIMES
2-292
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS.. TEXAS 75285
n. For SN5491A/SN7491A,
SN5494, SN7494
4-81T SHIFT REGISTERS
DECEMBER 1972 - REVISED MARCH 1988
•
TTL MSI PARALLEL-IN SERIAL-OUT REGISTERS
for application as
• Serial-In Serial-Out Register
Dual-Source, Parallel-To-Serial Converter
SN5494 ... J OR W PACKAGE
SN7494 ... N PACKAGE
description
These monolithic shift registers which utilize transistor-transistor logic (TTL) circuits in the familiar
Series 54/74 configuration, are composed of four R-S
master-slave flip-flops, four AND-DR-INVERT gates,
and four inverter-drivers. Internal interconnections of
these functions provide a versatile register which
performs right-shift operations as a serial-in, serial-out
register or as a dual-source, parallel-to-serial converter. A number of these registers may be connected in
series to form an n-bit register.
(TOP VIEW I
P2A
PE2
P1A
PIB
PIe
PID
vee
PEl
SER
elK
P2B
P2e
GNO
P20
elR
QO
logic symbol t
SRG4
All flip-flops are simultaneously set to a low output
level by applying a high-level voltage to the clear
input while the internal presets are inactive (high).
See the preset function table below. Clearing is
independent of the level of the clock input.
PE1
PEl
elR
elK
SER
PlA
161
G1
(15)
II
G2
(10)
181
C3/-+
171
111
1S
(16)
The register may be parallel loaded by using the clear
input in conjunction with the preset inputs. After
clearing all stages to low output levels, data to be
loaded is applied to either the P1 or P2 inputs of each
register stage (A, B, C, and D) with the corresponding
preset enable input, PE 1 or PE2, high. Presetting, like
clearing, is independent of the level of the clock
input.
P18
PlB
II)
121
Q)
(.)
1S
2S
(14)
131
Ple
PlD
PlD
-S
(13)
141
191
(11)
Q)
o
00
...J
tThis symbol is in accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617-12.
l-
Transfer of information to the outputs occurs on the positive-going edge of the clock pulse. The proper information
must be setup at the R-S inputs of each flip-flop prior to the rising edge of the clock input waveform. The serial input
provides this information for the first flip-flop, while the outputs of the subsequent flip-flops provide information for
the remaining R-S inputs. The clear input must be at a low level and the internal presets must be inactive (high) when
clocking occurs_
PRESET FUNCTION TABLE
REGISTER FUNCTION TABLE
(BIT A TYPICAL OF ALI.I
PR ESET INPUTS
INTERNAL
PEl P1A PE2 P2A PRESET A
I-
INPUTS
INTERNAL PRESETS
A
B
C
0
INTERNAL OUTPUTS
CLEAR CLOCK SERIAL
I.
X
L
X
H (inactive)
H
H
H
H
H
L
X
X
L
H (inactive)
L
L
L
L
L
X
X
X
X
L
L
X
H (inactive)
H
H
H
H
L
L
L
L
H (inactive)
L
H
L
H
L
L
H
H
X
X
X
L (active)
H
H
H
H
L
X
X
H
H
L (active)
H
H
H
H
L
t
t
QA
OUTPUT
QO
QC
L
L
X
L
°B
L
X
X
X
H
H
H
H
GAO
H
GBO
GBO
GCO
H
GDO
H
H
GAn
°Bn
°Cn
L
L
°An
°Bn
°Cn
GDO
high level (steady state), L = low level (steady statel, X = irrelevant, t = transition from low to high level
QAO. 0so, QeD, Goo = the level of GA. 0B, DC, or GO. respectively, before the indicated steady-state input conditions were established.
0An, 0Sn' QCn
the level of 0A, 0B, or 0C, respectively, before the most-recent t transition of the clock.
H
=
0=
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
. .
Input voltage (see Note 2)
. .
Operating free-air temperature range: SN5494
SN7494
Storage temperature range
NOTES:
. . . .
. . . .
Circuits
Circuits
7V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
1. Voltage values are with respect to network ground terminal.
2. Input voltage must be zero or positive with respect to network ground terminal.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
:~~~~:~~i~ai~:1~1~ ~!~:i:~ti:; :llo::~:~:t::s~s not
.J.!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-293
SN5494, SN7494
4·811 SHIFT REGISTERS
logic diagram (positive logic)
PRESETS
r-______________--JA~_______________,
I
\
P2A
(16)
P1A
(1)
P1B
P2B
(2)
P2C
P1C
(14)
(13)
(3)
P10
(4)
P20
(11)
PRESET {PE2 (15)
ENABLE
(6)
INPUTS
PE1~~--_+_1~_+_;----1_~--1__+----+_~--t_+_--_+_,
-4
-4
QA
S
S
QB
ac
S
r-
CK
C
CK
S
QO
(9)
CK
CK
CD
<
R
n'
CD
QA
CLEAR
fie
R
CLEAR
CIl
CLEAR
R
CLEAR
(8)
CLOCK
CLEAR (10)
schematics of inputs and output
EQUIVALENT OF EACH INPUT
OUTPUT
Vee
----...----- Vee
INPUT
...- - - - - OUTPUT
PEl and PE2: R eq "" 1 kfi NOM
All others: Req:: 4
2·294
kn
NOM
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
OUTPUT
QO
SN5494, SN7494
4-811 SHIFT REGISTERS
recommended operating conditions
SN5494
Supply voltage, Vee
SN7494
NOM
MIN
4.5
5
MAX
MIN
5.5
4.75
NOM
5
-400
High-level output current, IOH
5.25
V
-400
jlA
16
rnA
16
Low-level output current, tOl
Width of clock pulse, twlclock)
35
35
Width of clear pulse, tw(clead
30
30
30
30
High-level data
35
35
Low-level data
25
25
0
0
Width of preset pulse, tw(presed
I
I
Setup time, tsu
Hold time, th
-55
Operating free-air temperature, T A
125
UNIT
MAX
n.
n.
n.
n.
n.
0
°e
70
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
VOL
SN5494
MIN
TYPt
MAX
2
MIN
SN7494
UNIT
TYPt MAX
V
2
0,8
0.8
Vee-MIN,
Low-level output voltage
VIH - 2 V,
VIL = 0.8 V,
IOH = -400jlA
Vee- MIN,
VIH = 2V,
2.4
0.2
VIL = 0.8 V,
II
Input current at maximum input voltage
IIH
High-level input current
IOL=16rnA
Vee = MAX, VI=5.5V
Presets 1 and 2
Other inputs
Presets 1 and 2
Vee= MAX, VI=2AV
IlL
Low-level input current
lOS
Short-circuit output current§
Vee = MAX
ICC
Supply current
Vee = MAX,
Other inputs
3.5
Vee = MAX, VI=0.4V
2.4
3.5
0.4
35
See Note 3
004
1
1
160
40
160
-604
-6.4
-57
V
rnA
jlA
40
rnA
-1.6
-18
50
&I
V
0.2
-1.6
-20
V
-57
rnA
58
rnA
35
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°e.
§ Not more than one output should be shorted at a time,
NOTE 3: ICC is measured with the outputs open, clear grounded following momentary application of 4.5 V, both preset¥enable inputs
grounded, and all other inputs at 4.5 V.
switching characteristics. Vee = 5 V. TA = 25°e
PARAMETER
f max
Propagation delay time,
tpLH
TEST CONDITIONS
low·to~high-Ievel
output from clock
Propagation delay time, high-to·low¥level
tpHL
output from clock
Propagation delay time, low¥to¥high level
tpLH
TYP
MAX
CL
~
15 pF,
RL = 400 Il,
UNIT
MHz
25
40
ns
25
40
ns
35
ns
40
ns
See Note 4
output from preset
Propagation delay time, high-to¥low¥level
tpLH
MIN
10
Maximum clock frequency
output from clear
NOTE 4: Load circuits and voltage waveforms are shown in Section 1,
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-295
-4
-4
r-
C
CD
5.
o
CD
en
2-296
SN5495A. SN54LS95B.
SN7495A. SN74LS95B
4·BIT PARALLEL·ACCESS SHIFT REGISTERS
MARCH 1974 - REVISED MARCH 1988
TYPICAL MAXIMUM
TYPICAL
CLOCK FREQUENCY
POWER DISSIPATION
'95A
36 MHz
195mW
SN5495A, SN54lS95B _ , , J OR W PACKAGE
SN7495A , , , N PACKAGE
SN74LS95B , , , D OR N PACKAGE
'LS95B
36 MHz
65mW
(TOPVIEWI
TYPE
SER
A
description
These 4-bit registers feature parallel and serial inputs,
parallel outputs, mode control, and two clock inputs,
The registers have three modes of operation:
VCC
QA
OB
B
QC
QO
CLK 1
CLK2
C
0
MODE
GNO
Parallel (broadside) load
Shift right (the direction OA toward 00)
Shift left, (the direction 00 toward 0A)
Parallel loading is accomplished by applying the four
bits of data and taking the mode control input high,
The data is loaded into the associated flip-flops and
appears at the outputs after the high-to-Iow transition
of the clock-2 input, During loading, the entry of
serial data is inhibited,
SN54lS95B , , , FK PACKAGE
ITOPVIEWI
ffiul3«
«cnz>O
B
Shift right is accomplished on the high-to-Iow transition of clock 1 when the mode control is low; shift
left is accomplished on the high-to-Iow transition of
clock 2 when the mode control is high by connecting
the output of each flip-flop to the parallel input of
the previous flip-flop (00 to input C, etc,) and serial
data is entered at input 0, The clock input may be
applied commonly to clock 1 and clock 2 if both
modes can be clocked from the same source, Changes
at the mode control input should normally be made
while both clock inputs are low; however, conditions
described in the last three lines of the function table
will also ensure that register contents are protected,
NC
C
4
5
6
If)
4)
(,)
NC
o
'>
8
4)
o
..J
lI-
NC - No internal connection
FUNCTION TABLE
INPUTS
MODE
CLOCKS
SERIAL
OUTPUTS
PARALLEL
QA
QB
Oc
QO
A
B
C
D
X
X
X
X
X
OAO
°BO
QeD
QOO
X
b
c
d
c
d
QBt
Qct
QDt
d
•
b
X
•
QBn
Qen
QDn
d
H
X
X
X
X
X
QAO
QBO
QeD
QDO
X
I
H
X
X
X
X
H
QAn
QBn
QCn
X
I
L
X
X
X
X
L
OAn
QBn
QCn
L
X
X
X
X
X
QAO
QBO
QeD
QDO
CONTROL
2 ILl
H
H
X
H
j
X
H
I
X
L
L
L
L
t
L
llRI
j
L
L
X
X
X
X
X
QAO
QBO
QCO
QDO
I
L
H
X
X
X
X
X
QAO
QBO
QeD
QDO
t
H
L
X
X
X
X
X
QAO
QBO
QeD
QDO
t
H
H
X
X
X
X
X
QAO
QBO
QCO
QDO
tShifting left requires external connection of aS to A, QC to B, and 00 to C. Serial data IS entered at input D.
H = high level (steady state), L:::: low level (steady state), X :::: irrelevant (any input, including transitions)
1 = transition from high to low level. t :::: transition hom low to high level
a. b, C, d :::: the level of steadY-state input at inputs A, B. C, or 0, respectively.
QAO. Qao. Qeo. 000 = the level of 0A, QS, 0C, or 00, respectively, before the indicated steady-state input conditions were established.
0An, 0Sn, 0Cn. aO n = the level of 0A, as, 0C, or QO, respectively, before the most·recent ~ transition of the clock.
PRODUCTION DATA documonts contain information
current IS of publication date. Products conform to
specificatioAs par the terms of rlxas Instrum'Ats
:~~~::~~i;.r::I~7.; ~!=:~ti:; :.~a::;:::::.:;:.s
nat
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-297
SN5495A, SN54lS958, SN7495A, SN74lS958
4·81T PARALLEL·ACCESS SHIFT REGISTERS
logic symbol t
ClK1
1C3/1-+
2C4
ClK2
SER
A
B
C
D
(3)
(4)
40
(5)
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for D. J. N. and W packages.
logic diagram (positive logic)
-4
-4
DATA INPUTS
'~A--------------B----~A~------C-------------D--\
r-
C
MODE
(6)
~
~
~
~
CONTROL~~~~~~~~--------~------------~----------~~-----------'
CD
<
SERIAL~11~1~~__t=======~~t1------~~--t1------~~~-t----~~
c:;'
INPUT
CD
en
CLOCK 1 (9)
RIGHT-SH 1FT :::.:...-+-----L....I
CLOCK 2 (8)
LEFT.!lHIFT =-------4...-/
(101
IQA
08
QC
QD,
~~----------------~-------'vr--------~~------------~
OUTPUTS
2-298
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN5495A. SN54LS95B. SN7495A. SN74LS95G
4·BIT PARALLEL·ACCESS SHIFT REGISTERS
schematics of inputs and outputs
'95A
'95A
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
Vee
VCC3-Req
INPUT
-OUTPUT
Mode control:
Clock inputs:
All other inputs:
Req = 3 kH NOM
Req = 4 Ul NOM
R eQ ·""' 6 kH NOM
'95A
R
lOOH
'L95"
R
500 H
'LS95B
'LS95B
'LS95B
EQUIVALENT OF CLOCK
AND MODE CONTROL INPUTS
EQUIVALENT OF DATA
AND SERIAL INPUTS
TYPICAL OF ALL OUTPUTS
v ee ---
Q)
...........J
tfmax :~ maximum clock frequency_
tpLH
.0=
propagation delay time, low-to-high-Ievel output.
tpHL -=.. propagation delay time, high-to-Iow-Ievel output.
TYPICAL APPLICATION DATA
This application demonstrates how the '97 can be cascaded to perform l8·bit rate multiplication. This scheme is
expandable to n·bits by extending the pattern illustrated.
~
____________________
~A~____________________
~
18-BIT RATE
INPUT
CLEAR
ENABLE {LOW!
DISABLE {HIGH!
ENABLE {LOW!
DISABLE {HIGH!
INVERTED OUTPUT
NONINVERTED OUTPUT
As illustrated, two of the 6·bit multipliers can be cascaded by connecting the Z output of unit A to the unity cascade
input of unit 8, in which case, a two·input NOR gate is used to cascade the remaining multipliers. Alternatively, all three
Y outputs can be cascaded with a 3·input NOR gate. The three unused unity cascade inputs can be conveniently
terminated by connecting each to its Z output.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-315
SN5497. SN7497
SYNCHRONOUS 6·BIT BINARY RATE MULTIPLIERS
PARAMETER MEASUREMENT INFORMATION
_---ENABLEO'---_\f--OISABLEO-
3V
CLOCK
_ _ _ _oJ
INPUT
I
OV
I
I -r 1- ..
frl-'5-V--"'\:l~'~~ ____ _
fsu ...
, . _ - _ .+-1.....--t....., th
~:p~;'\1'5V
10 ns
3V
OV
/
DUTPUTV
-t
-t
\--------VOL
ENABLING FROM POSITIVE·GOING
TRANSITION OF CLOCK PULSE
r0-
O
(I)
_OISABLEO"""'\r--ENABLEO~,..--OISABLEO _ _
<
,r
3V
(I)
CIl
,
CLOCK
INPUT
tsu
ENABLE
INPUT
--I
-i
3V
t-th
t-,
1.5 Vvr~-.5_-V-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_ ::H
OUTPUT
V
_
_- - - - l/
ENABLING FROM NEGATlVE·GOING
TRANSITION OF PREVIOUS CLOCK PULSE
1. Unity/Cascade and pin 2 (rate input). other inputs are low. Clear the counter and apply clock and enable pulse as illustrated.
2. Setup and hold times are Illustrated for enabling a single clock pulse (count). Continued application of the enable function will enable
subsequent clock pulse (counts) until disabling occurs (enable goes "igh). The total number of counts will be determined by the total
number of positive-going clock transition enabled.
NOTES:
A. The input pulse generator has the following characteristics:' tw(clock) = 20 ns, tTLH " 10 ns, tTHL " 10 ns, PAR;;: 1 MHz,
Zout ~ 50 n.
B. C L includes probe and jig capacit'ilnce.
C. All diodes are 1N3064 or equivalent.
FIGURE I-SWITCHING TIMES
2·316
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • D~LLAS, TEXAS 75265
SN5497. SN7497
SYNCHRONOUS 6·BIT BINARY RATE MULTIPLIERS
PARAMETER MEASUREMENT INFORMATION
RATE INPUT
\~.~V--
j.5V
I
OUTPUT OF DEVICE
UNDER TEST
--
Vee = MAX,
VI =O.4V
Vee - MAX,
See Note 4
VCC = MAX,
See Note 2
C
..J
....
....
0.1
0.3
0.3
0.4
0.4
20
20
60
60
80
80
J or K
III
II)
V
V
3.4
0.1
CLR
UNIT
V
IOL = 8 mA
II
TYP* MAX
-1.5
Q)
0.25
IOL=4mA
VOL
SN74LS107A
MAX
-1.5
IOH = - 0.4 mA
VCC=MIN,
TYP*
- 20
-0.4
-0.4
-0.8
-0.8
-100
4
- 20
4
6
mA
~A
mA
-100
mA
6
mA
tFor con.ditions shown as MIN or MAX, use t~e appropriate value specified under recommended operating conditions.
l All typIcal values are at Vee"" 5 V. T A = 25 C.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2: With all outputs open, ICC is measured with the Q and
outputs high in turn. At the time of measurement, the clock input is
grounded.
a,
NOTE 4: For certain devices where state commutation can be caused by shorting an output to ground, an equivalent test may be performed
with Va = 2.25 V and 2.125 V for the 54 family and the 74 family, respectively, with the minimum and maximum limits reduced
to one half of their stated values.
switching characteristics, Vee = S V, TA = 2Soe (see note 3)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
CLR or ClK
Oar Q
TEST CONDITIONS
f max
IPlH
IpHL
RL = 2 kn,
el = 15 pF
MIN
TYP
30
45
MAX
UNIT
MHz
15
20
ns
15
20
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-323
2-324
SN54109, SN54LS109A,
SN74109, SN74LS109A
DUAL J.j{ POSITIVE·EDGE·TRIGGERED FLlP·FLOPS WITH PRESET AND CLEAR
DECEMBER 19B3 - REVISED MARCH 19BB
• Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
SN54109, SN54LS109A ... J OR W PACKAGE
SN74109 ... N PACKAGE
SN74LS109A ... 0 OR N PACKAGE
(TOP VIEW)
lClR
lJ
lK
lCLK
lPRE
10
10
GND
• Dependable Texas Instruments auality and
Reliability
description
These devices contain two independent J-K positiveedge-triggered flip-flops. A low level at the preset or
clear inputs sets or resets the outputs regardless of the
levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the
setup time requirements are transferred to the outputs
on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of the clock pul~. Following the
hold time interval, data at the J and K inputs may be
changed without affecting the levels at the outputs.
These versatil':.,flip-flops can perform as toggle flip-flops
by grou nding K and tying J high. They also can perform
as D-type flip-flops if J and K are tied together.
VCC
2ClR
2J
2K
2CLK
2PRE
20
20
SN54LS109A ... FK PACKAGE
(TOP VIEW)
~I~
~-.
3
The SN54109 and SN54lS109A are characterized for
operation over the full military temperature range of
-55°C to 125°C. The SN74109 and SN74lS109A are
characterized for operation from O°C to 70°C.
u
Z
>~\d
N
2 1 2019
9 10111213
I~ ~ ~I~ ~
.
- -.....--Vcc
Vec ---e----
n
NOM
INPUT
<1>
(I)
OUTPUT
IlL MAX
-1.6 rnA
-3.2 rnA
-4.8 rnA
2·326
Req NOM
4kn
2kn
1.3 kn
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS. TEXAS 75265
SN54109, SN54LS109A,
SN74109, SN74LS109A
DUAL J-l( POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
schematic
r -_ _ _ _~---._-~'L=S~1~O=9A~-~--_.----~~~~-
9 kl1
12011
16 kl1
16 kl1
9 kl1
12011
VCC
v
a
0 -........- ..
PRE
CLR
(/)
Q)
(,)
-S
Q)
C
..J
v
II-
18 kl1
CLK
K
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage: '109........................................................................ 5.5 V
'LS109A ...................................................................... 7 V
Operating free·air temperature range: SN54' ........................................... - 55°C to 125°C
SN74' ............................................... oOe to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
2-327
SN54109, SN74109
DUAL J·i PDSITIVE·EDGE·TRIGGERED FLlp·FLOPS WITH PRESET AND CLEAR
recommended operating conditions
SN54109
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
SN74109
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
IOL
Low-level output current
tw
Pulse duration
tsu
Input setup time before CLK t
2
th
Input hold time·data after CLK t
TA
Operating free-air temperature
V
V
0.8
0.8
- 0.8
-0.8
mA
16
mA
16
I
.1
UNIT
CLK high or low
20
20
ffi or CCR low
20
20
10
10
6
ns
ns
6
125
- 55
V
ns
0
70
'c
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
VIK
~
ro
CD
VOH
MIN
VCC= MIN,
11- -12mA
VCC - MIN,
VIH = 2 V,
VIL = 0.8 V,
VIH = 2 V,
VIL - 0.8 V,
2.4
VCC- MAX,
VI - 5.5 V
Jor~
ri'
CLR
IIH
CD
VCC= MAX,
VI=2.4V
PREor
CLK
en
J or
K
CLR'
IlL
PRE'
CLK
VCC= MAX,
SN74109
MAX
3.4
0.2
IOL = 16mA
II
TVP*
MIN
TVP*
-1.5
IOH = -O.SmA
VCC- MIN,
VOL
<
SN54109
TEST CONDITIONSt
VI=O.4V
3.4
2.4
0.4
0.2
VCC= MAX
ICC'
VCC= MAX,
-30
See Note 2
9
0.4
1
1
40
160
160
80
80
-1.6
-1.6
-4.8
-4.8
-3.2
-3.2
-85
UNIT
V
V
40
-3.2
IOS§
MAX
-1.5
V
mA
I'A
mA
-3.2
-30
9
15
-85
mA
15
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*All typical value. are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time.
, Clear .is tested with preset high and preset is tested with clear high.
, Average per flip-flop.
NOTE 2: With all outputs open. ICC is measured with the Q and Q outputs high in turn. At the time of measurement. the clock input is
grounded.
switchi ng characteristics, Vee '" 5 V, T A '" 25° C (see note 3)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
TEST CONDITIONS
f max
TVP
25
33
MAX
UNIT
MHz
a
10
15
ns
tpHL
a'
23
35
ns
tpLH
CLR
a
10
15
ns
17
25
ns
CLK
aorO
10
16
ns
18
28
ns
tpLH
PRE
tPHL
tpLH
RL" 400
n,
CL = 15pF
a
tpHL
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-328
MIN
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54LS109A, SN74LS109A
DUAL J.j( POSITIVE·EDGE·TRIGGERED FlIp·FlOPS WITH PRESET AND CLEAR
recommended operating conditions
SN54LS109A
VCC
Supply vo Itage
VIH
High-level input voltage
VIL
Low-level input voltage
SN74LS109A
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
2
2
V
IOH
High-level output current
-0.4
-0.4
mA
IOL
Low-level output current
4
8
rnA
fclock
Clock frequency
25
MHz
0
tw
Pulse duration
tsu
Setup time before eLK f
th
Hold time-data after elK t
TA
Operating free-air temperature
25
0
ClK high
25
25
PRE or ClR low
25
25
High-level data
35
35
Low-level data
25
25
5
5
-55
125
ns
ns
ns
'c
70
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
SN54LS109A
TEST CONDITIONSt
VIK
VOH
TVP*
2.5
3.4
11--18mA
VCC =MIN,
VIH =2V,
VIL -MAX,
Vil = MAX,
VIH = 2 V,
Vil -MAX,
VIH=2V,
IOH=-O.4mA
0.25
IOl =4 mA
VOL
VCC = MIN,
SN74LS109A
MAX
MIN
TVP*
2.7
3.4
-1.5
VCC -MIN,
VCC =MIN,
MIN
J, K or ClK
VCC= MAX,
ClR or PRE
lit or ClK
CIJl orl'RE
J,
0.4
VI =2.7V
VCC= MAX,
VI=0.4V
IOS§
VCC= MAX,
See Note 4
ICC (Total)
VCC = MAX,
See Note 2
J,RorClK
III
CCRorl'm:
V
0.25
0.4
0.35
0.5
0.1
0.1
0.2
0.2
20
20
40
40
- 0.4
-0.4
-0.8
-100
- 20
4
-0.8
-20
8
4
t
For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
t
All typical values are at
Vee:::
V
V
VI = 7 V
VCC= MAX,
IIH
UNIT
-1.5
IOl =8 mA
II
MAX
mA
I'A
mA
-100
mA
8
mA
5 V, T A ;:: 25 0 C.
§Not more than one output should be shorted at a time, and the duration of the shOft circuit should not exceed one second.
NOTE 2: With all outputs open, ICC is measured wtih the Q and Q outputs high in turn. At the time of measurement, the clock input
is grol.lnded.
NOTE 4: For certain devices where state commutation can be caused by shorting an output to ground, an equivalent test may be
performed with Vo 2.25 V and 2.125 V for the 54 family and the 74 family, respectively with the minimum and maximum
limits reduced to one half of their stated values.
=
switching characteristics. Vee = 5 V. TA = 25°e (see note 3)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
TEST CONDITIONS
f max
tPlH
ern, PRE
tPHl
or ClK
QorQ
Rl = 2 kn,
Cl = 15 pF
MIN
TVP
25
33
MAX
UNIT
MHz
13
25
ns
25
40
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
~
TEXAS
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-329
2-330
SN54111, SN74111
DUAL J·K MASTER·SLAVE
FLlp·FLOPS WITH DATA LOCKOUT
DECEMBER 1983 - REVISED MARCH 1988
SN54111 ... J PACKAGE
SN74111 ... N PACKAGE
• Package Options Include Plastic and
Ceramic DIPs and Ceramic Flat Packages
(TaP VIEW)
• Dependable Texas Instruments Quality and
Reliability
lK
lPRE
lCLR
lJ
lCLK
10
10
description
The SN54111 and SN74111 are d-c coupled, variableskew, J-K flip-flops which utilize TTL circuitry to obtain
25-MHz performance typically. They are termed
"variable-skew" because they allow the maximum clock
skew in a system to be a direct function of the clock
pulse width. The J and K inputs are enabled to accept
data only during a short period (30 nanoseconds maximum hold time) starting with, and immediately following the rising edge of the clock pulse. After this, inputs
may be changed while the clock is at the high level
without affecting the state of the master. At the
threshold level of the falling edge of the clock pulse, the
data stored in the master will be transferred to the output. The effective allowable clock skew then is
minimum propagation delay time minus hold time, plus
clock pulse width. This means that the system designer
can set the maximum allowable clock skew needed by
varying the clock pulse width. Thus system design is
made easier and the requirements for sophisticated
clock distribution systems are minimized or, in some
cases, entirely eliminated. These flip-flops have an additional feature-the synchronous input has reduced sensitivity to data change while the clock is high because
the data need be present for only a short period of time
and the system's susceptibility to noise is thereby effectively reduced.
VCC
2K
2PRE
2CLR
2J
2CLK
20
GND "'-t.:'--_=->-' 20
logic symbol t
lPRE
1J
lCLK
lK
lClR
U)
2PRE
Q)
(J
2J
'>
2ClK
2K
Q)
c
2ClR
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
..J
lI-
The SN54111 is characterized for operation over the full
military temperature range of -55°e to 125°e; the
SN74111 is characterized for operation from Doe to
70 o e.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
ClR
ClK
J
K
a
a
L
H
X
X
X
H
L
H
L
X
X
X
L
L
L
X
X
X
HI
H
HI
H
H
H
H
H
H
H
H
Jl..
Jl..
Jl..
Jl..
00
L
L
ao
H
L
H
L
L
H
H
L
H
H
TOGGLE
:t.This configuration is non-stable; that is, it will not persist when preset
or clear return to their inactive (high) level.
PRODUCTION DATA documents conlein informalion
current as of publication data. Products conform to
specifications per the terms of Texas Instruments
:'~~~:~~i~ar::1~1e ~!:~~:i:r :,i"::~:~:t:~~S not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-331
SN54111, SN74111
DUAL J-K MASTER-SLAVE
FLIP-FLOPS WITH DATA LOCKOUT
logic diagram (positive logic)
ClR ---H~-L_./
::t
I"'"
elK
C
CD
<
cS"
schematics of inputs and outputs
~
EQUIVALENT OF EACH INPUT
TYPICAL OF All OUTPUTS
Vee
---4I~-Vee
Req
13011 NOM
INPUT
OUTPUT
III MAX
-1.6mA
-3.2mA·
-4.8mA
Req NOM
4kl1
2kl1
1.3 kl1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage ........................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54111 ................................. -.55°e to 125°C
SN74111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
2-332
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54111, SN74111
DUAL J·K MASTER·SLAVE FLlp·FLOPS WITH DATA LOCKOUT
recommended operating conditions
SN74111
SN54111
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
OB
O.B
V
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
-O.B
-O.B
mA
IOL
Low-level output current
16
16
mA
tw
Pulse duration
tsu
tho
Input setup time before elK t
TA
Operating free-air temperature
2
L
I
2
CLK high or low
25
25
PRE or CLR low
25
25
Input hold time data after elK t
0
0
30
30
-55
125
V
ns
ns
ns
0
70
"C
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
SN54111
TESTCONOITIONS t
PARAMETER
VIK
VCC - MIN,
II = - 12 mA
VOH
VCC = MIN,
VIH -2V,
VIL-O.BV,
IOH - - O.B mA
VOL
VCC = MIN,
VIH=2V,
VIL = O.B V,
IOL = 16 mA
VCC=MAX,
VI-5.5V
II
MIN
TYP*
2.4
3.4
IIH
0.2
TYP*
2.4
3.4
0.2
0.4
MAX
V
0.4
V
V
1
1
40
40
BO
BO
120
J or K
- 1.6
-1.6
I CLR'
-3.2
- 3.2
- 3.2
-3.2
VCC = MAX,
VI = 2.4 V
I PRE'
VCC= MAX,
-4.B
VCC =MAX
VCC - MAX,
fI)
Q)
(,)
mA
'S;
Q)
C
IlA
....I
lImA
VI =O.4V
~
IOS§
ICC#
•
UNIT
- 1.5
120
PRE
r-cu<
IlL
MIN
- 1.5
J or K
r-=CLR or
SN74111
MAX
-20
See Note 2
-57
14
-4.B
-1B
20.5
14
-57
mA
20.5
mA
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25°C.
*
§
Not more than one output should be shorted at a time.
, Clear is tested with preset high and preset is tested with clear high.
# Average per flip-flop.
NOTE 2: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is at 4.5 V.
switching characteristics, Vee = 5 V, TA = 2Soe (see note 3)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
TEST CONOITIONS
f max
tPLH
PRE or CLR
OorO
CLK
OorO
tpHL
tpLH
RL=400n,
CL=15pF
tpHL
MIN
TYP
20
25
MAX
UNIT
MHz
12
lB
ns
21
30
ns
12
17
ns
20
30
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2·333
-I
-I
r-
C
CD
<
n'
CD
(II
2-334
SN54LS112A, SN54S112, SN74LS112A, SN74S112A
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH PRESET AND CLEAR
02661. APRIL 1982-REVISEO MARCH 1988
SN54LS112A. SN54S112 ... J OR W PACKAGE
SN74LS112A. SN74S112A ... 0 OR N PACKAGE
•
Fully Buffered to Offer Maximum Isolation
from External Disturbance
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
(TOP VIEW)
•
1CLK
1K
1J
1PRE
10
10
20
GND
Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset and clear inputs sets or resets the
outputs regardless of the levels of the other
inputs. When preset and clear are inactive (high).
data at the J and K inputs meeting the setup time
requirements are transferred to the outputs on
the negative-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops
can perform as toggle flip-flops by tying J and
K high.
The SN54lS 11 2A and SN54S 112 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74lS 11 2A
and
SN74S 11 2A
are
characterized for operation from O°C to 70°C.
VCC
1CLR
2CLR
2CLK
2K
2J
2PRE
20
SN54LS1 12A. SN54S1 12 ... FK PACKAGE
(TOP VIEW)
~
ul5
2
1 2019
'"
u u Uu
~~Z>~
3
4
18
5
17
6
16
7
15
8
14
2CLR
2CLK
NC
2K
2J
9 1011 1213
0 U 0lti!
10
NZZNCl(!J
N
NC - No internal connection
logic symbolt:
FUNCTION TABLE (each flip-flop)
OUTPUTS
INPUTS
PRE
CLR
CLK
L
H
H
L
Q
J
X
X
X
K
Q
X
X
X
H
L
L
Ht
H
Ht
L
Qo
00
L
L
X
X
X
H
H
j
L
H
H
L
H
L
H
L
H
L
H
H
H
I
I
I
H
H
H
H
TOGGLE
H
H
H
X
X
Qo
00
lCLR
2PRE
2J
2CLK
2K
2CLR
20
20'
~This symbol is in accordance with ANSIIIEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for D. J, N, and W packages.
t The output levels in this configuration are not
guaranteed to meet the minimum levels
for VOH if the lows at preset and clear
are near V,l minimum. Furthermore, this
configuration is nonstable; that is, it will not
persist when either preset or clear returns to
its inactive (high) level.
PRODUCTION DATA do.umont••••t8i. informati ••
CIIHent IS of publication data. Praduets conform to
specifications per the tenns of TaxI. Instruments
:~~:~:~~irv8i::1~7i ~~::i:; :'~D::;:::::':~~ not
Copyright © 1982. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TeXAS 75265
2-335
SN54LS112A, SN54S112, SN74LS112A, SN74S112A
DUAL J·K 'NEGAtlVE·EDGE·TRIGGERED
FLIP· FLOPS WITH PRESET AND CLEAR
logic diagrams Ipositive logic)
'lSl12A
Q
K---=====~
ClK
SN54S112, SN74lS112A
Q
~---PRE
I-------K
ClK
2-336
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS112A, SN54S112, SN74LS112A, SN74S112A
DUAL J-K NEGATIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH PRESET AND CLEAR
schematics of inputs and outputs
'LS112A
EQUIVALENT OF
EACH INPUT
TYPICAL OF ALL OUTPUTS
Vcc--"'--
VCC
120 Il
NOM
Req
.w...-_
INPUT ...
~~""'OUTPUT
IlL MAX
-0.4 rnA
-0.8 mA
Req NOM
30 kll
8.25 kll
en
II)
U
'S;
SN54S112, SN74S112A
II)
EQUIVALENT OF
EACH INPUT
C
TYPICAL OF ALL OUTPUTS
..J
VCC
VCC------
lI-
50 Il NOM
INPUT
OUTPUT
IlL MAX
-1.6mA
-4 mA
-7mA
Req NOM
4kll
1.4 kll
9001l
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: 'LS 112A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
SN54LS112, SN74LS112A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54' . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°e
SN74' ................................ ooe to 70 0 e
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-337
SN54LSl12A. SN74LSl12A
DUAL J-K NEGATIVE-EDGE-TRIGGE8ED
FLIP-FLOPS WITH PRESET· AND CLEAR
recommended operating conditions
SN54LS112A
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
fclock
elock frequency
tw
Pulse duration
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
2
0.8
-0.4
-0.4
4
30
eLK high
Set up time-before eLK!
th
Hold time-data after eLK!
TA
Operating free-air temperature
20
a:R
0
25
Data high or low
20
20
CLR inactive
25
25
PRE inactive
20
20
0
125
V
mA
8
mA
MHz
ns
ns
ns
0
-55
V
30
20
25
low
UNIT
V
0.7
0
PRE or
tsu
SN74LS112A
MIN
0
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VIK
VOH
SN54LS112A
TEST eONDITIONSt
PARAMETER
MIN
Vee ~ MIN,
II ~ -1SmA
Vee ~ MIN,
VIH ~ 2 V,
VIL ~ MAX,
VIL ~ MAX,
VIH
VIL ~ MAX,
VIH ~ 2 V,
IOH
~
~
2.5
2 V,
3.4
0.25
IOL ~ 4 mA
Vee ~ MIN,
SN74LS112A
MAX
MIN
2.7
0.4
IOL ~ SmA
a:R or
PRE
Vee ~ MAX,
VI
~
7 V
eLK
Jar K
IIH
a:R or
PRE
Vee ~ MAX,
VI
~
2.7 V
eLK
Jar K
IlL
All other
Vee ~ MAX,
VI
~
0.4 V
IOS§
Vee
MAX,
see Note 2
lee lTotall
Vee ~ MAX,
see Note 3
~
MAX
-1.5
3.4
UNIT
V
V
0.25
0.4
0.35
0.5
V
Jar K
II
TYP*
-1.5
-0.4 mA
Vee ~ MIN,
VOL
TYP*
-20
.0.1
0.1
0.3
0.3
0.4
0.4
20
20
60
60
so
so
-0.4
-0.4
-O.S
-0.8
-100
4
6
-20
mA
~A
mA
-100
mA
6
mA
4
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*All typical values are at Vee ~ 5 V, TA ~ 25°e.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
NOTES: 2. For certain devices where state commutation can be caused by shorting an output to ground, an equivalent test may be performed
with Vo = 2.25 V and 2.125 V for the '54 family and the '74 family, respectively, with the minimum and maximum limits
reduced to one half of their stated values.
3. With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input
is grounded.
2-338
TEXAS . "
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS112A. SN74LS112A
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH PRESET AND CLEAR
switching characteristics. Vee
PARAMETER
FROM
(INPUT)
5 V. TA
=
25°e (see Note 41
TO
(OUTPUT)
TEST CONDITIONS
f max
tpLH
tpHL
CLR, PRE or CLK
Q
or ij
RL
~
2 kO,
CL
~
15 pF
MIN
TVP
30
45
MAX
UNIT
MHz
15
20
ns
15
20
ns
NOTE 4: load circuits and voltage waveforms are shown in Section 1.
rn
Q)
U
'S;
Q)
C
-I
lI-
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 65500' 2 • DA.LlAS, TEXAS 75265
2·339
SN54S112. SN74S112A
DUAL J'K NEGATIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH PRESET AND CLEAR
recommended operating conditions
SN54S112
Vee
Supply voltage
VIH
High-level input voltage
Vil
Low~level
10H
High-level output current
10l
Low-level output current
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
2
input voltage
V
V
-I
-1
rnA
20
rnA
6
6
ClK low
6.5
6.5
8
8
ClJi low
Data high or low
tsu
Set up time-before elK!
th
Hold time-data after ClK!
TA
Operating free-air temperature
7
7
0
0
-55
V
0.8
elK high
j5RE or
UNIT
0.8
20
Pulse duration
tw
SN74S112A
MIN
125
ns
ns
ns
0
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
-f
-f
r-
= MIN.
Vee = MIN.
IOH = -1 rnA
Vee = MIN.
10l = 20 rnA
Vec = MAX.
Vee
VIK
VOH
C
CD
<
VOL
tI)
IIH
Cr
CD
II
J or K
All other
J or
Vce
= MAX.
II
=
MIN
TYP*
PRE§
Vec
= MAX.
VIH
=
2 V.
Vil
=
VIH
=
2 V.
Vil
= 0.8
MAX.
2.5
3.4
V.
Vec
= MAX
= MAX.
MIN
TYP*
2.7
UNIT
V
V
3.4
0.5
V
VI
=
5.5 V
1
1
rnA
VI
=
2.7 V
50
100
50
100
~A
-1.6
-1.6
VI
= 0.5
V
-7
-7
-7
-7
-4
Vee
MAX
-1.2
0.5
ClK
lOS'
ICC#
SN74S112A
MAX
-1.2
-18 rnA
i<
elR§
III
SN54S112
TEST CONDITIONSt
-40
see Note 3
-100
15
25
rnA
-4
-40
15
-100
rnA
25
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vce = 5 V. TA = 25°e.
§Clear is tested with preset high and preset is tested with clear high.
~ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
#Values are average per flip-flop.
NOTE 3: With all outputs open. lee is measured with the Q and Q outputs high in turn. At the time of measurement. the clock input is
grounded.
*
2-340
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SN54S112, SN74S112A
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLlp·FLDPS WITH PRESET AND CLEAR
switching characteristics. Vee = 5 V. TA = 25°e (see Note 4)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
TEST CONDITIONS
f max
tplH
PRE or ClR
a or a
ern (ClK high)
PRE or ern (ClK low)
aorO
ClK
a ora
PRE or
tpHl
tplH
tpHl
Rl
=
280 \J,
Cl
=
15 pF
MIN
TYP
80
125
MAX
MHz
4
7
5
7
5
7
7
7
4
5
UNIT
ns
ns
ns
ns
NOTE 4: load circuits and voltage waveforms are shown in Section 1.
II)
Q)
(J
'S
Q)
c
-'
lI-
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-341
-I
-I
rC
CD
<
n'
CD
CI)
2-342
SN54LS113A. SN54S113. SN74LS113A. SN74S113A
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLlP·FLOPS WITH PRESET
02661, APRIL 1982 - REVISED MARCH 1988
SN54LS113A. SN54S113" ,J OR w PACKAGE
SN74LS113A, SN74S113A", D OR N PACKAGE
(TOP VIEW)
• Fully Buffered to Offer Maximum Isolation
from External Disturbance
• Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers
and Flat Packages. and Plastic and Ceramic
DIPs
1CLK
1K
1J
lPRE
10
10
GND
• Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent J-K
negative-edge-triggered flip-flops, A low level at
the preset input sets the outputs regardless of
the levels of the other inputs, When preset (PRE)
is inactive (high), data at the J and K inputs
meeting the setup time requirements are
transferred to the outputs on the negative-going
edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to
the rise time of the clock pulse, Following the
hold time interval. data at the J and K inputs may
be changed without affecting the levels at the
outputs, These versatile flip-flops can perform
as toggle flip-flops by tying J and K high,
The SN54LS113A and SN54S113 are
characterized for operation over the full military
temperature range of - 55°C to 125°C, The
SN74LS113A
and
SN74S113A
are
characterized for operation from OOC to 70°C.
VCC
2CLK
2K
2J
2PRE
20
20
SN54LS113A. SN54S113, "FK PACKAGE
(TOP VIEW)
In
Q)
CJ
.S;
Q)
o
-'
....
....
NC - No internal connection
logic symbol t
lPRE
FUNCTION TABLE (each flip-flop)
INPUTS
PRE
CLK
L
X
H
j
H
j
H
I
lJ
lCLK
OUTPUTS
J
X
L
H
L
K
Q
X
H
L
L
00
00
L
H
H
L
L
H
H
j
H
H
TOGGLE
H
H
X
X
00
PRODUCTION DATA documenl. c.nlain informalion
currant IS of publication date. Products conform to
specifications per the terms of Texas Instruments
:'~~~:~~i~ai~:I~~~ ~~:~ti:fn :1~o::;:::::t::S~s not
lK
Q
00
2PRE
2J
2CLK
2K
tThis symbol is in accordance with ANSI/IEEE Std 91 -'984 and
IEC Publication 617-12.
Pin numbers shown are for D. J, N. and W packages.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1982. Texas Instruments Incorporated
2-343
SN54LS113A. SN54S113. SN74LS113A. SN74S113A
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH PRESET
logic diagrams (positive logic)
'LS113A
Q
PRE---+--------~~----~
K--==========1
CLK
SN54S113, SN74S113A
-I
-I
rC
CD
Q
<
n'
CD
en
...----PRE
I====----K
CLK
2-344
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS113A. SN74LS113A. SN54S113. SN74S113A
DUAL J-K NEGATIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH PRESET
schematics of inputs and outputs
'LS113A
EQUIVALENT OF
EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC--...- -
VCC
120 !l
NOM
Req
INPUT ....~....- . L.....I~..... OUTPUT
IlL MAX
-0.4 rnA
-0.8 rnA
Req NOM
30 k!l
8.25 k!l
en
CD
(,)
-S;
SN54S113,SN74S113A
EQUIVALENT OF
EACH INPUT
CD
C
TYPICAL OF ALL OUTPUTS
...J
l-
VCC
VCC---4~--
I-
50!l NOM
INPUT
OUTPUT
IlL MAX
-1.6 rnA
-7mA
Req NOM
4k!l
900n
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: 'LS 113A ...................................................... 7 V
SN54S113, SN74S113A ......................................... 5.5 V
Operating free-air temperature range: SN54' . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°e
SN74' ................................ ooe to 70 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 1: Voltage values are with respect to network ground terminals.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-345
SN54LS113A. SN74LS113A
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH PRESET
recommended operating conditions
SN54LS113A
SN74LS113A
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
VCC
Supply voltage
V,H
High-level input voltage
Vil
Low~level
IOH
High-level output current
-0.4
-0.4
mA
IOl
Low-level output current
4
8
mA
30
MHz
2
input voltage
fclock
Clock frequency
tw
Pulse duration
0
Set up time-before ClK.
tsu
2
th
Hold time-data after ClK.
TA
Operating free-air temperature
30
0
ClK high
20
20
PRE or ClR low
25
25
Data high or low
20
20
PRE inactive
20
20
0
V
ns
ns
0
-55
125
ns
0
70
°c
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
-t
-t
r-
C
CD
PARAMETER
= MIN,
Vec = MIN,
IOH = -0.4
VCC = MIN,
IOl = 4 mA
Vec = MIN,
IOl = 8 mA
VOH
!S.
(")
CD
(/I
II
. VCC
VIK
VOL
SN54LS113A
TEST eONDITloNst
=
MIN
TYP*
=
Vil
=
MAX,
Vil
= MAX,
VIH
=
2 V,
Vil
=
VIH
=
2 V,
2 V,
mA
MAX,
2.5
PRE
0.25
=
MAX,
VI
=
7 V
Jar K
PRE
VCC
=
MAX,
VI
=
2.7 V
ClK
Jar K
I,l
0.4
3.4
VCC
PRE or ClK
IOS§
VCC
ICC lTotall
VCC
=
MAX,
=
=
MAX,
see Note 2
MAX,
see Note 3
VI
= 0.4
UNIT
V
V
0.25
0.4
0.35
0.5
0.1
VCC
MAX
V
elK
IIH
TYP*
-1.5
2.7
3.4
Jar K
II
MIN
-1.5
-18mA
VIH
SN74LS113A
MAX
V
-20
0.3
0.4
0.4
20
20
60
60
80
80
-0.4
-0.4
-0.8
-0.8
-100
4
0.1
0.3
6
-20
4
mA
~A
mA
-100
mA
6
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
* All typical values are at Vec = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
NOTES: 2. For certain devices where state commutation can be caused by shorting an output to ground, an equivalent test may be performed
with Vo = 2.25 V and 2.125 V for the '54 family and the '74 family, respectively, with the minimum and maximum limits
reduced to one half of their stated values.
3. With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input
is grounded.
2-346
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS. TEXAS 75265
SN54LS113A, SN74LS113A
DUAL J·K NEGATIVE·EDGE·TRIGGERED
FLlp·FLOPS WITH PRESET
switching characteristics. Vee = 5 V. TA .. 25°e (see Note 41
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
TEST CONDITIONS
Ima.
tPLH
i'm:orCLK
QorQ
RL
~
CL
2 kG.
~
15 pF
MIN
TVP
30
45
15
15
tpHL
MAX
UNIT
MHz
20
20
ns
ns
NOTE 4: Load circuits and voltage waveforms are shown in Section 1.
II)
CI)
(.)
'S;
CI)
C
....J
tt-
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-347
SN54S113, SN74S113A
DUAL J·K· NEGATlVE·EDGE·TRIGGERED
FLlP·FLOPS WITH PRESET·
.
recommended operating conditions
SN54S113
MIN
4.5
Supply voltage
VCC
VIH
High-level input voltage
NOM
MAX
5
5.5
2
2
low-level input voltage
High-level output current
Vil
IOH
IOl
Pulse. duration
Set up time-before ClK.
tsu
th
TA
0.8
-1
20
ClK high
ClK low
6
6.5
15m!: low
8
Data high or low
7
Hold time-data after ClK.
V
20
V
rnA
rnA
6
6.5
0
-55
Operating free-air temperature
UNIT
V
0.8
-1
Low-level output current
tw
SN74S113A
MIN NOM MAX
4.75
5.25
5
125
ns
8
7
ns
0
ns
0
70
°c
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
-t
-t
r
o
<
n·
(1)
(1)
tn
SN54S113
TEST CONDITIONS t
PARAMETER
VIK
VCC = MIN.
II = -18 rnA
VOH
VCC = MIN.
IOH=-1mA
VIH = 2 V.
Vil = 0.8 V.
VOL
VCC = MIN.
10l = 20 rnA
VIH = 2 V.
Vil = 0.8 V.
II
VCC = MAX.
VI = 5.5 V
VCC = MAX.
VI = 2.7 V
J or K
IIH
~orClK
MIN
TVP*
2.5
3.4
J or K
~§
III
VCC = MAX.
VI = 0.5 V
ClK§
lOS'
ICC g
-40
VCC = MAX
VCC = MAX.
see Note 3
SN74S113A
MAX
-1.2
TVP*
2.7
3.4
MAX
-1.2
UNIT
V
V
0.5
0.5
V
1
50
1
50
rnA
100
-1.6
100
-1.6
-7
-7
-4
-4
-100
15
MIN
-40
-100
15
25
25
/LA
rnA
rnA
rnA
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
*All typical values are at Vec = 5 V. TA = 25°C.
§ Clear is tested with preset high and preset is tested with clear high.
, Not more than one output should be shorted at a time. and the duration of the short-circuit should not exceed one second.
#Values are average per flip-flop:
NOTE 3: With all outputs open. ICC is measured with the Q and 0 outputs high in turn. At the time of measurement. the clock input is
. grounded.
switching characteristics. Vee - 5 V. TA .. 25°e (see Note 4)
FROM
(INPUT)
TO
(OUTPUTI
tplH
PRE
QorO
tPHl
PRE (ClK high)
PRE (ClK low)
Oor Q
tplH
tpHl
ClK
PARAMETER
TEST CONDITIONS
f max
Q or
Rl = 280 II.
Cl = 15 pF
TI
TVP
80
125
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MAX
UNIT
MHz
4
7
5
7
5
7
4
7
7
5
NOTE 4: Load circuits and voltage waveforms are shown in Section 1~
2-348
MIN
ns
ns
ns
ns
SN54LSl14A, SN54S114, SN74LS114A, SN74S114A
DUAL J·K NEGATlVE·EDGE·TRIGGERED FLlp·FLOPS
WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
MARCH 1973-REVISED MARCH 1988
SN54LS114A. SN54S114 ... J OR W PACKAGE
SN74LS114A. SN74S114A ... 0 OR N PACKAGE
•
Fully Buffered to Offer Maximum Isolation
from External Disturbance
•
Package Options Include Ceramic Carriers
and Flat Packages in Addition to Plastic and
Ceramic DIPs
(TOP VIEW)
•
ClR
1K
1J
1PRE
1Q
10
GND
Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset and clear inputs sets or resets the
outputs regardless of the levels of the other
inputs. When preset and clear are inactive (high),
data at the J and K inputs meeting the setup time
requirements are transferred to the outputs on
the negative-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops
can perform as toggle flip-flops by tying J and
K high.
The SN54LS114A and SN54S114 are
characterized for operation over the full military
temperature range of - 55 DC to 125 DC. The
SN74LS114A
and
SN74S114A
are
characterized for operation from ODC to 70 DC.
VCC
ClK
2K
2J
2PRE
20
20
SN54LS114A. SN54S114 ... FK PACKAGE
(TOP VIEW)
3
2
1 20 19
1J
NC
1PRE
NC
10
9 10 11 12 13
Id 0 U Id d
ZZNN
19
NC - No internal connection
logic symbol:!:
FUNCTION TABLE
INPUTS
OUTPUTS
L
H
X
H
L
X
L
L
X
J
X
X
X
H
H
j
L
H
H
j
H
H
j
H
H
H
H
PRE
CLR
CLK
K
Q
Q
X
H
L
X
L
H
X
Ht
Ht
L
00
DO
H
L
H
L
L
H
L
H
j
H
H
TOGGLE
H
X
X
00
10
10
1K
2PRE
2J
2K
20
20
+This symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEe Publication 617-12.
Pin numbers shown are for 0, J, Nt and W packages.
DO
t The output levels in this configuration are not
guaranteed to meet the minimum levels
for VOH if the lows at preset and clear
are near VIL minimum. Furthermore, this
configuration is nonstable; that is, it will not
perSist when either preset or clear returns to
its inactive (high) level.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~ar~:1~1e ~!:~~~ti:; :llo::::~:t:r~~s not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright
© 1973, Texas Instruments Incorporated
2-349
SN54LS114A, SN54S114, SN74LS114A, SN74S114A
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlp·FLOPS
WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
logic diagram (positive logic)
'lS114A
Q
' - - - - _ - - - + . - - ClR
PRE--+----.---~
K-=====~
----
ClK
TO OTHER F·F
-I
-I
SN54S114,SN74S114A
rC
(1)
<
n·
Q
(1)
(I)
ClR----.-..
t-----PRE
~==='----K
TO {
OTHER
F·F
ClK
2-350
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LSl14A. SN54S114. SN74LSl14A. SN74S114A
DUAL J·K NEGATIVE EDGE·TRIGGERED FLlp·FLOPS
WITH PRESET. COMMON CLEAR. AND COMMON CLOCK
schematics of inputs and outputs
'LSl14A
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF
EACH INPUT
VCC
120 II
NOM
VCC-_..-Req
INPUT -..:14-4-..-
OUTPUT
IlL MAX
-0.4 rnA
-0.8 rnA
-1.6 rnA
Req NOM
30 kll
8.25 kll
4.1 k!l
SN54S114. SN74S114A
EQUIVALENT OF
EACH INPUT
en
CD
CJ
TYPICAL OF ALL OUTPUTS
'S
- - -.....-VCC
CD
50 II NOM
VCC--~-
C
..J
........
INPUT
OUTPUT
IlL MAX
-1.6 rnA
-4 rnA
-7 rnA
Req NOM
4 kll
1.4 k!l
goon
absolute maximum ratings over operating free· air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage: 'LS114A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
SN54S114. SN74S114A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54' . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125 °e
SN74' ............................... ,
to 70 0
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150 °e
ooe
e
NOTE 1: Voltage values are with respect to network ground terminal.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-351
SN54LS114A, SN74LS114A
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlP·FLOPS
WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
recommended operating conditions
SN54lS114A
VCC
Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
IOH
High-level output current
IOl
Low·level output current
fclock
Clock frequency
tw
Pulse duration
tsu
-I
-I
rC
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
0.8
-0.4
-0.4
4
30
th
Hold time-data after CLK!
Operating free-air temperature
0
ClK
20
PRE or ClR low
25
25
Data high or low
20
20
CLR inactive
25
25
PRE inactive
20
20
125
V
mA
8
mA
MHz
ns
ns
0
0
V
30
20
-55
UNIT
V
0.7
0
TA
ns
0
70
°c
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VIK
VOH
SN54lS114A
TEST CONDITIONSt
~
Vce ~ MIN,
II
Vee ~ MIN,
VIH ~ 2 V,
Vce ~ MIN,
(1)
TVP*
2.5
3.4
~
MAX,
VIH
~
2 V,
VIL ~ MAX,
VIH
~
2 V,
0.25
IOL ~ 4 rnA
VOL
Vee ~ MIN,
SN74lS114A
MAX
MIN
TVP*
2.7
3.4
-1.5
VIL
MAX,
~
VIL
MIN
-18mA
IOH ~ -0.4 rnA
(i'
t/)
NOM
2
Set up time-before CLK!
(1)
<
SN74lS114A
MIN
-1.5
0.4
J or K
I eLR
I PRE
Vce ~ MAX,
VI
~
7 V
~
J or K
IIH
I-=eLR
I-=-
IlL
r--ern
r---
Vee ~ MAX,
VI
~
2.7 V
PRE
~
J or K
VCC
~
MAX,
VI
~
0.4 V
PRE
r-ru--VCC ~ MAX,
0.4
0.35
0.5
0.1
0.1
0.6
0.6
0.3
0.3
0.8
0.8
20
20
120
120
60
60
160
160
-0.4
-0.4
-1.6
-1.6
-0.8
-0.8
ICC (Totall
Vce
~
MAX,
-100
-20
See Note 2
V
V
0.25
-1.6
IOS§
UNIT
V
IOL ~ 8 rnA
II
MAX
4
See Note 3
6
rnA
~A
rnA
-1.6
-20
-100
rnA
6
rnA
4
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vce ~ 5 V, TA ~ 25°C.
§ Not more than one output should be shorted at a time. and the duration of the short-circuit should not exceed one second.
NOTES: 2. For certain devices where state commutation can be caused by shorting an output to ground, an equivalent test may De performed
with Vo == 2.25 V and 2.125 V for the '54 family and the '74 family, respectively. with the minimum and maximum limits
reduced to one half of their stated values.
3. With all outputs open. ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input
is grounded.
2-352
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54LS114A, SN74LS114A
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlP·FLOPS
WITH PRESET, COMM~N CLEAR, AND COMMON CLOCK
switching characteristics. Vee - 5 V. TA - 25°e (see Note 4)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
TEST CONOITIONS
f max
tplH
tpHl
ern. PRE or ClK
Q
orO
Rl
=2
kll.
Cl
=
15 pF
MIN
TYP
MAX
30
45
15
15
20
20
UNIT
MHz
ns
ns
NOTE 4: Load circuit and voltage waveforms are shown in Section 1.
I/)
Q)
(.)
'S;
Q)
C
-'
........
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-353
SN54S114, SN74S114A
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlp·FLOPS
WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
recommended operating conditions
SN74S114A
SN54S114
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
Vee
Supply voltage
VIH
High-level input voltage
Vil
low-level input voltage
0.8
IOH
High-level output current
-1
IOl
low-level output current
2
tw
Pulse duration
elK low
PRE or
ern low
6
6
6.5
6.5
8
8
Data high or low
Setup time
tsu
th
Hold time-data after elK!
TA
Operating free-air temperature
7
7
0
0
-55
125
V
V
2
20
elK
UNIT
0.8
-1
mA
V
20
mA
ns
ns
ns
70
0
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
. noted)
PARAMETER
-f
-f
r
o
CD
<
C:;'
CD
VIK
VOH
SN54S114
TEST CONDITIONS t
MIN
Vee - MIN.
II -
Vee = MIN.
VIH = 2 V.
VIL = O.S V.
-1S mA
VIH = 2 V.
Vil = O.S
VOL
2.5
3.4
V.
Vee = MAX.
VI = 5.5 V
~
IIH
~
Vee = MAX.
VI = 2.7 V
PRE
eLK
~
IlL
~
PRE
eLK
Vee
= MAX.
MIN
TYP*
MAX
-1.2
2.7
VI = 0.5 V
0.5
1
1
50
50
200
200
100
100
200
200
-1.6
-1.6
-14
-14
-7
-7
-S
IOS§
Vee = MAX
lee#
Vee
= MAX.
-40
See Note 3
-100
15
25
UNIT
V
V
3.4
0.5
IOl = 20 mA
II
en
SN74S114A
MAX
-1.2
IOH=-1mA
Vee = MIN.
TYP*
V
mA
pA
mA
-S
-40
-100
mA
25
mA
15
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
* All typical values are at Vee = 5 V. TA = 25°e.
§ Not more than one output should be shorted at a time, and the duration of the short~circuit should not exceed one second.
#Values are average per flip-flop.
NOTE 3: With all outputs open, ICC is measured with the Q and
grounded.
2-354
5
outputs high in turn. At the time of measurement, the clock input is
TEXAS
~
INSTRUMENTS
POST OFfiCE BOX 655012 • DALLAS, TEXAS 75265
SN54S114. SN74S114A
DUAL J·K NEGATIVE·EDGE·TRIGGERED FLlp·FLOPS
WITH PRESET. COMMON CLEAR. AND COMMON CLOCK
switching characteristics, Vee
PARAMETER
FROM
(INPUT)
5 V, TA = 25°e (see Note 4)
TO
TEST CONDITIONS
(OUTPUT)
f max
tplH
PRE or
a:R
PRE or ClR (ClK high)
tpHl
tplH
tpHl
Q or Q
a or Q
Rl = 280!l,
Cl = 15 pF
PRE or ClR (ClK lowl
ClK
Q ora
MIN
TVP
80
125
MAX
UNIT
MHz
4
7
5
7
5
4
5
7
7
7
ns
ns
ns
ns
NOTE 4: Load circuit and voltage waveforms are shown in Section 1.
TEXAS
-II
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2·355
2-356
SN54116, SN74116
DUAL 4·81T LATCHES WITH CLEAR
DECEMBER 1972 - REVISED MARCH 1988
SN54116 ... J OR W PACKAGE
SN74116 ... N PACKAGE
• Two Independent 4·Bit latches in a Single
Package
ITOP VIEWI
• Separate Clear Inputs Provide One·Step
Clearing Operation
lClR
lCl
lC2
101
101
102
102
103
103
104
104
GNO
• Dual Gated Enable Inputs Simplify Cascad·
ing Register Implementations
• Compatible for Use with TTL Circuits
• Input Clamping Diodes Simplify System
Design
VCC
204
204
203
203
202
202
201
201
2C2
2Cl
2ClR
description
These monolithic TIL circuits utlize Ootype bistables to implement two independent four-bit latches in a single package. Each
four-bit latch has an independent asynchronous clear input and a gated two-input enable circuit. When both enable inputs are
low, the output levels will follow the data input levels. When either or both of the enable inputs are taken high, the outputs remain at the last levels setup at the inputs prior to the low-to-high-Ievel transition at the enable input(s). After this, the data inputs are locked out.
':;
The clear input is overriding and when taken low will reset all four outputs low regardless of the levels of the enable inputs.
o
The SN54116 is characterized for operation over the full military temperature range of -55°C to 125°C; the SN74116 is
characterized for operation from O°C to 70°C.
....
....
INPUTS
H
00
ENABLE
Q)
CJ
Q)
...J
logic symbol t
FUNCTION TABLE
lEACH LATCH I
CLEAR
en
OUTPUT
DATA
0
C1
C2
H
L
L
L
L
H
L
H
H
H
X
L
H
X
H
H
X
X
°D
L
X
X
X
101
102
103
00
L
104
hi~liI
level, L
low level, X . Irrelevant
the level of Q before these input conditions were established.
201
201
202
202
203
204
2Q3
204
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and
lEe Publication 617-12.
PRODUCTION DATA d••umonts contoin i.farmatl••
current I. of publicatian data. Praduets conform ta
spacifications per the terms of T.xas Instruments
::~=~i;.{nr:r.!t; ~=::i:r :.~':;::~::s
not
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-357
SN54116, SN74116
DUAL 4·81T LATCHES WITH CLEAR
logic diagram (positive logic)
CLEAR~I~1,~1~3~1~:>-__________________~
15,171 Ql
Dl~14~,~1~6~1____-+~t-~
17,191 Q2
D2~1~6,~1~8~1____-+~t--I
19,211 Q3
-I
-I
D3~1~8~,2~0~1____-+~i-~
r-
oCD
<
t+-=:;t.J.+-ll;..:l,.:.;,2::.;;3,.:.;1 Q4
c:;'
CD
111
04
110,221
schematics of inputs and--outputs
EQUIVALENT OF CLEAR,
1:1, AND 1:2 INPUTS
VCC=Q--
4 k!! NOM
INPUT
--
EQUIVALENT OF
DATA INPUTS
TYPICAL OF
ALL OUTPUTS
VCC13--
VCC
Req
INPUT
--
OUTPUT
Initial Req
:=:
3 kH NOM
Steady-state Req
:=:
6 kH NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
_.......
Input voltage . . . . . . . . . . . . . . . .
Operating free· air temperature range: SN54116 Circuits
SN74116 Circuits
Storage temperature range
NOTE 1: Voltage values are with respect to network ground terminal.
2-358
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
7V
5.5 V
":55°C to 125°C
O°C to 70°C
-65°C to 150°C
SN54116.SN74116
DUAL 4·81T LATCHES WITH CLEAR
recommended operating conditions
SN54116
MIN
4.5
Supply voltage, VCC
High~level
NOM
SN74116
MAX
MIN
5.5
4.75
5
output current, IOH
NOM
5
-BOO
Low-level output current, tOl
16
Input pulse width, tw
Data setup time, tsu
Cl, C2
18
18
CLR
18
18
High logic level
8
8
Low logic level
14
14
Clear inactive-state setup time, tsu
8
Data release time, high-level data, trelease
Data hold time, low-level data, th
5.25
V
-800
pA
16
mA
ns
8
8
ns
2
8
-55
125
UNIT
ns
2
Operating free-air temperature, T A
MAX
0
70
ns
"C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt
PARAMETER
VIH
High-level input voltage
VL
VIK
Low-level input voltage
Input clamp voltage
VOH
High-level output voltage
MIN
TVP+
VCC= MIN,
11=-12mA
VCC= MIN,
VIH = 2 V,
VIL =
o.av,
10H = -HOOpA
VCC= MIN,
VOL
Low-level output voltage
II
Input current at maximum input voltage
IIH
High-Ie,,-el input current
Cl, C2, or clear
Any D
2.4
VIH =2V,
VIL = 0.8 V,
10L = 16mA
VCC= MAX,
VI=5.5V
VCC= MAX,
VI=2.4V
V
Any 0, initial peak
Low-level input current
0.2
ICC
Short-circuit output current §
V
(/)
Q)
(.)
':;
V
0.4
40
60
Q)
C
V
...I
lI-
mA
pA
-1.6
-2.4
VI=0.4V
VCC = MAX,
rnA
-1.6
VCC= MAX
Supply current
V
-1.5
1
Any D. steady-state
lOS
0.8
3.4
el, C2. or clear
IlL
MAX UNIT
2
SN54116
-20
SN74116
-18
-57
-57
VCC= MAX,
Condition A
60
100
See Note 2
Condition B
40
70
rnA
rnA
tFol'" conditions shown as MIN or MAX, use the appropriate value specified undel'" recommended operating conditions for the applicable device
type.
fAil typical values are at Vec = 5 V. T A == 25°C.
§Not more than one output should be shorted at 8 time.
NOTE 2: With outputs open, ICC is measured for the following conditions:
A. All inputs gl'"ounded.
B. All C inputs al'"e grounded and all other inputs al'"e at 4.5 V.
switching characteristics, Vee = 5
PARAMETER
tPLH
tpHL
tpLH
V. TA = 25° C
FROM
TO
UNPUTI
{OUTPUTI
Cl
or
C2
TEST CONDITIONS
Any Q
Data
0
tpHL
CLR
AnyQ
TVP
MAX UNIT
19
30
15
22
RL =40011,
10
15
See Figure 1
12
18
15
22
CL
tPHL
MIN
= 15pF,
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ns
ns
ns
2-359
SN54116. SN14116
DUAL 4·81T LATCHES WITH CLEAR
PARAMETER MEASUREM.ENT INFORMATION
VCC
FROM OUTPUT UNDER TEST
. .-
. .I-t~N-"'''''.~
LOAD CIRCUIT
CLEAR
INPUT
~
l'
.11.5V
'----------_____________
1.5V
3V
OY
,J-- tw -+-lt+-+f tsu
DATA
INPUT
ENABLE
(See
i
!
\
/ -------- ::
I
I
I ,.---.... I
I
~:=u,,~ __~:-----~f
.....-- Iw ---+I
~
1.5 V
~1.5V
f
1.5 V
I+-
!+tPHL.j
OUTPUT
I
tpHL
r--.... It--- tw ----tioj~
115 V
~
/
~1.5V
\
T ~"-
115 V
I+-
3V
0V
tPLH--1
fr1-.5-Y-- :::
SWITCHING TIMES FROM CLEAR AND ENABLE INPUTS
DATA
INPUT
1.5V
I
I
I
I
I
I
ENABLE
INPUT
(So. Not. 01
tpLH
OUTPUT
3V
,
(S•• Not. E)
,I
I
3V
\'-__--'t ~"-_
I
t
-I I-th
I+-Isu-+l
I
I
0V
I..tPHL~
~I
'---.11..--- 0 V
,\1.5
5V
1.
/
V
SWITCHING TIMES FROM DATA INPUTS
NOTES: A. Input pulses are supplied bV generators having the following characteristics: tr
50%, Zout ~ 50n.
8.
C.
D.
E.
~
CL includes probe and jig capacitance.
All diodes are 1 N3064 or equivalent.
The other enable input is low.
Clear input is high.
FIGURE 1
2-360
TEXAS . " .
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TeXAS 75265
10 ns, tf
iii;;
10 ns, PAR == 1 MHz, duty cycle "-
SN54120, SN74120
DUAL PULSE SYNCHRONIZERS/DRIVERS
SEPTEMBER 1
•
Generates Either a Single Pulse or Train of Pulses
Synchronized with Control Functions
•
Ideal for Implementing Sync-Control Circuits
Similar to those Used in Oscilloscopes
•
Latched Operation Ensures that Output Pulses
Are Not Clipped
•
High-Fan-Out Complementary Outputs Drive
System Clock Lines Directly
•
Internal Input Pull-Up Resistors Eliminate
Need for External Components
•
Diode-Clamped Inputs Simplify System Design
•
Typical Propagation Delays:
- REVISED MARCH 198B
SN54120 ... J PACKAGE
SN74120 ... N PACKAGE
(TOPVIEWI
1M
Vee
lSI
2M
152
2S2
2S1
2R
2e
2Y
fA
Ie
lY
IV
iv
GND
9 Nanoseconds through One Level
16 Nanoseconds through Two Levels
description
CI)
These monolithic pulse synchronizers are designed to synchronize an asynchronous or manual signal with a system
clock. Reliable response is ensured as the input signals are latched up; therefore duration of logic input is not critical
and the adverse effects of contact·bounce of a manual input are eliminated. The ability to pass output pulses is started
and stopped by the levels or pulses applied to the latch inputs 51, 52, or R in accordance with the function table.
High·speed circuitry is utilized throughout the clock paths to minimize skew with respect to the system clock.
INPUTS
When the mode control is set to pass a series of
pulses, the last pulse out is determined by two general
rules:
...I
I-
FUNCTION
R
X
81
L
X
Pass Output Pulses
X
X
L
Pass Output Pulses
L
H
H
H
I
H
Inhibit Output Pulses
Start Output Pulses
H
H
j
Start Output Pulses
I
H
H
Stop Output Pulses
H
H
H
Continue t
H .", high level (steady state)
L = low level (steady state)
a. When pulses are terminated by the S or R
inputs, conditions meeting the setup times
(specified under recommended operating
conditions) will dominate.
S2
CD
o
l-
FUNCTION TABLE
After initiation, the mode control (M) input determines
whether a series of pulses or only one pulse is passed.
In the absence of a stop command, the clock driver
will continue to pass clock pulses as long as the mode
control input is low (see Figures 2 through 4). After
the mode control input is taken high, only a single
clock pulse will be passed (see Figure 5).
CD
(,)
os:
J
= transition
from H to L
x = irrelevant
t Operation initiated bV last l transition continues.
b. Low·to·high·level transitions at the mode control input should be avoided during the 20·nanosecond period
immediately following the negative transition of the input clock pulse as transitions during this time period
mayor may not allow the next pulse to pass (see Figures 4 and 5). When pulses are terminated by the mode
control input, a positive transition at the mode control input meeting the high·level setup time, tsu (H),
(specified under recommended operating conditions) will pass that positive clock pulse then inhibit remaining
clock pulses. The clock input (e) is latch·controlled ensuring that once initiated the output pulse will not be
terminated until the full pulse has been passed.
PRODUCTION DATA d......o.. c.ot.in inla,m.ti.n
cu,rent II of publicoti.n dill. Produo.. c.n'.rm to
.p.oilio.Ii.1II PO' tb. terms ., T.... Inst.. m....
=:~~.f::,':!1i ~::\:~i:r :.:"::::::,:~ n.t
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-361
SN54120, SN74120
DUAL PULSE SYNCHRONIZERS/DRIVERS
description (continued)
This clock driver circuit is entirely compatible for use with either digital logic circuits or mechanical switches for input
controls since all inputs, except the clock, have internal pull-up resistors. This eliminates the requirement to supply an
external resistor to prevent the input from floating when the control switch is open. The internal resistor also means
that these inputs may be left disconnected if unused.
Typical propagation delay time is 9 nanoseconds to the Y output and 16 nanoseconds to the Y output from the clock
input. The outputs will drive 60 Series 54/74 loads at a high logic level and 30 loads at a low logic level. Typical power
dissipation is 127 milliwatts per driver. The SN54120 is characterized for operation from -55°C to 125°C; the
SN74120 is characterized for operation from O°C to 70°C.
logic symbol t
logic diagram (each driver) (positive logic)
1Ft
151
152
/41
R
&
SG1/Z2
R
Z5
S
(6)
1V
(7)
4R
5S
-I
-I
r-
l,3S
5R
2S
!NPUTS
C
G3
Z4
1M
(I)
<
n'
-
(I)
'}
Y
2;;
UUTPUTS
281
(10)
2V
252
'11
(9)
2V
M--------------~
tThis symbol is in accordance with ANSI/IEEE Std 91·1984
and lEe Publication 617·12.
schematics of inputs and outputs
EQUIVALENT OF
EACH C INPUT
vcc------~----
__
EQUIVALENT OF EACH
M, R, OR S INPUT
Vcc--'---~------
TYPICAL OF
ALL OUTPUTS
----------~----vcc
100 H NOM
NOM
INPUT
INPUT
'----+--- 0 UTPUT
2-362
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 656012" DALLAS. TEXAS 75265
SN54120. SN74120
DUAL PULSE SYNCHRONIZERS/DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
Input voltage . . . . . . . .
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN54120 Circuits
SN74120 Circuits
Storage temperature range . . . .
7V
5.5 V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies between the 51 and 52
inputs.
recommended operating conditions
SN54120
MIN
Supply voltage,
Vee
4.5
NOM
SN74120
MAX
MIN
NOM
MAX
5.5
4.75
5
5.25
5
High-level output current, IOH
2.4
rnA
48
48
rnA
12
tsu(H or U
Setup time (see Figures 2 thru 5)
Mode control
I tsu(H)
I tsulLi
Any input except mode control,
thlH or LI
Hold time (see Figures 3 and 5)
12
ns
0
0
12
12
3
3
20
Mode control, th(H or L)
Operating free-air temperature, T A
V
2.4
Low-level output current, tOl
Any input except mode control,
UNIT
en
Q)
(J
ns
'>
20
-55
125
0
Q)
"e
70
C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDlTlDNSt
MIN
High-level input voltage
VIH
VIL
Low-level input voltage
VIK
I nput clamp voltage
VOH
TYP:~
MAX
2
High-level output voltage
11-
Vee - MIN,
VIH - 2 V,
VIL = 0.8 V,
10H = -2.4 rnA
Vee = MIN,
VIH=2V,
VIL = 0.8 V,
10L = 48 rnA
Vee = MAX.
VI = 5.5 V
Vee = MAX,
VI=2.4V
Vee = MAX.
VI=O.4V
VOL
Low-level output voltage
II
I nput current at max imum input voltage
IIH
High-level input current
IlL
Low-level input current
lOS
Short-circuit output current*
Vee - MAX
lee
Supply current
Vee- MAX,
Clock input
Other inputs
Clock input
Other inputs
V
12 rnA
Vee - MIN,
2.4
0.8
V
1.5
V
0.4
1
-0.2
rnA
~A
-0.36
rnA
-3.2
See Note 3
V
80
-2.1
-35
~
~
V
3.4
0.2
-0.12
...J
UNIT
rnA
-90
rnA
51
90
rnA
TYP
MAX
t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions_
:tAII typical values are at V CC "" 5 V, T A = 25"C_
~ Not more than one output should be shorted at a time_
NOTE 3: ICC is measured with ground applied to all inputs except R which is at 4_5 V and all outputs open_
switching characteristics, Vee
PARAMETER~
tpLH
= 5 V, TA = 25°e
FROM
TO
(I NPUTI
IOUTPUTI
e
y
TEST CONDITIONS
tPHL
tpLH
tpHL
~:
tpLH
tpHL
-~
eL = 45 pF,
RL= 133!2.
y
e
See Figure 1
MIN
14
22
17
25
10
16
8
13
UNIT
ns
ns
PropagatIon delay tIme, low-to-hlgh-Ievel output
Propagation delay time, high-to-Iow·level output
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
2-363
SN54120, SN74120
DUAL PULSE SYNCHRONIZERS/DRIVERS
PARAMETER MEASUREMENT INFORMATION
VCC
NOTES:
A. The
clock
input
pulse
in figures 2
through 5
is
supplied bV 8 generator having the following char-
acteristics: tw{clockl d 15 ns,
Zout ~ 50 U.
PRR <;,; 1 MHz,
B. CL includes probe and jig capacitance.
C. All diodes are 1 N3064 or equivalent.
FIGURE l-LOAD CIRCUIT FOR SWITCHING TESTS
tw(clock)
CLOCK
INPUT
I
-f
-f
r
C
-------....Jt~~- -----
'--i-----"
....
I
tPHL--!
I
ISee Notel
CD
<
C;O
OV
~tsulHI
tsulLi
3V
OV
, . . . - - - - - - - VOH
Y OUTPUT
CD
t/)
tpLH
VOH
Y OUTPUT
' -_ _ _ _ _ _ VOL
NOTE: Mode control and
R inputs are
low and unused S input is high.
FIGURE 2-INITIATING AND TERMINATING PULSE TRAIN FROM S INPUTS
CLOCK
INPUT
I
I
I
I-----! tsulLI
I
......... tnlLi
~II
__
~ 1 or S2
1.5 V
INPUT
OV
3V
I
1.5 V
I
-----------------~----tsu I U
---------------~
-:------'y
3V
I
RINPUT
OV
th I U
1.5 V
, . . . - - - - - - - - VOH
Y OUTPUT
- - - - - - - - - - . VOL
NOTE:
Mode control Input is low and unused
S input
is high.
FIGURE 3-INITIATING PULS.E TRAIN FROM S AND TERMINATING WITH R INPUTS
2-364
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
and
SN54120. SN74120
DUAL PULSE SYNCHRONIZERS/DRIVERS
PARAMETER MEASUREMENT INFORMATION
_ _ _ ·llw(Clockl
I
CLOCK
INPUT
trlr~-*
MODE
CONTROL
INPUT
"'I"~-+- tsu(HI
Isu(LI
~~'5
__
V __________________
--J~~1.-~-~-_--_-_-_--_-_-_--_-_-_--_-_--_-_-_--_
OV
3V
OV
~-------------
"(OUTPUT
NOTE: At least one of the S inputs is low.
VOH
CI)
Q)
VOL
.s;(.)
Q)
0
FIGURE 4-INITIATING AND TERMINATING PULSE TRAIN WITH MODE CONTROL INPUT
....I
lICLOCK
INPUT
I
I
I
I
MODE CONTROL
INPUT
OV
14-
th(LI~_
tsu(HI
f·5V!
~~5_V_________________________________
i
----+~-~th-(H-I-~..j-----r
---------- -- ------ ---
_________________~-I~- _~_t~~I __________________ _
S1
or S2
INPUT
YOUTPUT
NOTE: Input
A is low and
the unusedS input is high.
"'----~-----------
3V
OV
3V
OV
VOH
VOL
FIGURE 5-ENABLING SINGLE PULSE
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-365
2-366
SN54121, SN14121
MONOSTABLE MULTIVIBRATORS
WITH SCHMITT·TRIGGER INPUTS
MAY 1983 - REVISED MARCH 1988
SN54121 ... J OR W PACKAGE
SN74121 ... N PACKAGE
ITOP VIEWI
•
Programmable Output Pulse Width
With R int ... 35 ns Typ
With Rext/Cext ... 40 ns to 28 Seconds
•
Internal Compensation for Virtual
Temperature Independence
Q
NC
Al
VCC
NC
NC
•
Jitter·Free Operation up to 90%
Duty Cycle
A2
Rext/Cext
Cext
Rint
NC
•
B
Q
GND
Inhibit Capability
FUNCTION TABLE
OUTPUTS
INPUTS
Q
Q
AI
A2
B
NC - No internal connection.
logic symbol*
L
X
H
L
H
X
L
H
Lt
Ht
X
X
L
Lt
Ht
H
H
X
Lt
Ht
H
I
H
I
H
H
j
j
H
L
X
t
X
L
t
AI
n..U
A2
8 15)
..
1&1 Q
111
II
1i
..n.
L..r
Jl.. L..r
Jl.. L..r
Jl.. L..r
U)
R int
Ce)l.t Rext/Cext
Q)
(,)
*This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
'>
For explanation of fu.netion table symbols, see page
t These lines of the function table assume that the indicated steady-state conditions at the A and B inputs have been setup long enough
C
-'
tt-
to complete any pulse started before the setup.
description
Q)
These multivibrators feature dual negative-transition-triggered inputs and a single positive-transition-triggered input
which can be used as an inhibit input. Complementary output pulses are provided.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse_
Schmitt-trigger input circuitry (TTL hysteresis) for the B input allows jitter-free triggering from inputs with transition
rates as slow as I volt/second. providing the circuit with an excellent noise immunity of typically 1.2 volts_ A high
immunity to VCC noise of typically 1.5 volts is also provided by internal latching circuitry_
Once fired. the outputs are independent of further transitions of the inputs and are a function only of the timing
components. Input pulses may be of any duration relative to the output pulse. Output pulse length may be varied from
40 nanoseconds to 28 seconds by choosing appropriate timing components. With no external timing components
(i.e_. Rint connected to Vcc. Cext and Rext/Cext open). an output pulse of typically 30 or 35 nanoseconds is achieved
which may be used as a doc triggered reset signal. Output rise and fall times are TTL compatible and independent of
pu Ise length.
Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature.
In most applications. pulse stabilitY will only be limited by the accuracy of external timing components.
Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing
capacitance (10 pF to 10 I'F) and more than one decade of timing resistance (2 kfl to 30 kfl for the SN54121 and
2 kfl to 40 kfl for the SN74121). Throughout these ranges. pulse width is defined by the relationship tw(out) =
CextRTln2 ~ 0.7 CextRT. In circuits where pulse cutoff is not critical. timing capacitance up to 1000 I'F and timing
resistance as low as 1.4 kfl may be used. Also. the range of jitter-free output pulse widths is extended if VCC is held
to 5 volts and free-air temperature is 25 CC. Duty cycles as high as 90% are achieved when using maximum
recommended RT'. Higherduty cycles are available if a certain amount of pulse-width jitter is allowed.
PRODUCTION DATA document. contein informetion
currant 8S of publication date. Products conform to
specifications par the terms of Taxas Instruments
==:~~i~8t::1~1i ~!:~::i:; :;jO:::::::':~~ not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-367
SN54121, SN74121
MONOSTABLE MULTlVIBRATORS
WITH SCHMITT·TRIGGER INPUTS
logic diagram (positive logic)
~_ _-,-(I:..:I::..I RextfCext
(61
Q
AI--"'''---1'r'-.....
(II
A2--'OJ[
Q
_"
B..:.::"------'
L._ _.:.:(I~O:...I Cext
Rint
=
2 kO NOM
Pin numbers shown on logic notation are for J or N packages.
NOTES:
1. An external capacitor may be connected between C ext (positive) and Rext/Cext.
2. To use the internal timing resistor, connect Aint to V
ce.
For improved pulse width
accuracy and repeatability, connect an external resistor between Aext/Cext and
Vee
with A int open-circuited.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF BOTH OUTPUTS
VCC----~-------
- - - - - - - - - VCC
INPUT
...- - - - - OUTPUT
INPUT
Al
A2
B
2·368
Req NOM
4kn
4kn
2 kn
Req -
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1300 NOM
SN54121. SN74121
MONOSTABLE MULTIVIBRATORS
WITH SCHMITT·TRIGGER INPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 3) ......... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage ............................................................. 5.5 V
Operating free-air temperature range: SN54121.................... . . . . .. - 55°C to 125°C
SN74121 ............................. ooe to 70°C
Storage temperature range ......................................... - 65°C to 1 50°C
NOTE 3: Voltage values are with respect to network ground terminal.
recommended operating conditions
Vee
Supply voltage
IOH
High-level output current
IOl
Low-level output current
dvldt
Rate of rise or faU of input pulse
twlinl
Input pulse width
Rext
External timing capacitance
Cext
External timing capacitance
Duty cycle
TA
Operating free-air temperature
I
I
I
I
MIN
NOM
MAX
54 Family
4.5
5
5.5
74 Family
4.75
5
5.25
V
-0.4
mA
16
mA
Schmitt input. B
1
Vis
logic inputs, A 1, A2
1
V/~s
50
1 54 Family
I 74 Family
I
I
UNIT
1.4
ns
30
1.4
40
0
1000
67
RT = 2 kG
90
RT = MAX Rext
I
54 Family
-55
125
I
74 Family
0
70
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
kll
~F
%
·e
2-369
SN54121, SN74121
MONOSTABlE MUlTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
TEST CONDITONSt
PARAMETER
=
=
=
=
=
=
=
=
MIN
TYP*
MAX
V,H
High-level input voltage at B input
VCC
V,l
Low-level input voltage at A input
VCC
VT+
Positive-going threshold voltage at B input
VCC
VT-
Negative-going threshold voltage at B input
VCC
V,K
Input clamp voltage
VCC
10H
High-level output voltage
VCC
VOL
Low-level output voltage
VCC
Input current at maximum input voltage
VCC
High-level input current
VCC = MAX,
V, = 2.4 V
A1 or A2
40
B
80
=
A1 or A2
-1.6
B
-3.2
"
"H
',l
Low-level input current
lOS
Short-circuit output current §
ICC
VCC
V,
=
VCC
Supply current
VCC
MIN
MIN
=
V
2
V
V
-1.5
V
1.55
MIN
MIN.
MIN,
MAX,
MAX,
0.4 V
=
V
0.8
MIN
MIN.
MAX
MAX
UNIT
2
" =
0.8
1.35
2.4
3.4
-12 mA
= MAX
10l = MAX
V, = 5.5 V
10H
V
0.2
0.4
V
1
54 Family
-20
-55
74 Family
-18
-55
Quiescent
13
25
Triggered
23
40
mA
p.A
mA
mA
mA
tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
'All typical values are at VCC = 5 V. TA = 25°C.
t Not more than one output should be shorted at a time.
switching characteristics. Vee
= 5 V. TA = 25°e
PARAMETER
tpLH
TEST CONDITIONS
MIN
TYP
MAX
45
70
ns
35
55
ns
50
80
ns
40
65
ns
110
150
ns
30
50
ns
600
700
800
ns
6
7
8
ms
Propagation delay time. low-ta-highlevel Q output from either A input
Propagation delay time, low-ta-hightplH
tpHl
tpHL
twlout)
Cext
Rint to VCC
level Q output from either A input
Propagation delay time, high-ta-Iow
level
Q output from B input
Cl
Rl
=
=
400
n,
See Note 4
=
Pulse width obtained using
Cext
internal timing resistor
Rint to VCC
Cext = 0,
zero timing capacitance
80 pF.
Rint to VCC
Cext = 100 pF,
RT = 10 kll
Pulse width obtained using
tw(outl
Cext = 1 ~F,
RT = 10 kll
external timing resistor
NOTE 4: Load circuits and voltage waveforms are shown in Section 1.
2-370
80 pF,
15 pF,
Pulse width obtained with
twlout}
=
level Q output from B input
Propagation delay time, high-ta-Iow
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
70
UNIT
SN54121, SN74121
MONOSTABLE MULTIVIBRATORS
WITH SCHMITT·TRIGGER INPUTS
TYPICAL CHARACTERISTICS t
DISTRIBUTION OF UNITS
for
OUTPUT PULSE WIDTH
Vcc =5 V
TA = 25°C
Cext = 101 pF
RT = 10 kn - t - - I - t - t - - i - - - - - i
IExternal)
VARIATION IN INTERNAL TIMING RESISTOR VALUE
vs
FREE-AIR TEMPERATURE
:;:
""
+30%
.~
+20%
II:
g'
·s
+10%
~S
+5%
.=c
.S!
o
~1
-5%
V
j.:
.::
,!!
r--
/
--
/
/
/'"
.=
694
691
697
700
703
706
f
-10%
I
-D
~
51
:; +0.5
~
"
So
0
0
o
.-/
'=
~
~
1-0.5
o
"
t
-----
Q.
"
.=c
..J
lI-
v---
>
."
"0
l
-1.0
4.5
4.75
f
...
.£;
" ' Iw(outl = 420 ns
@VCC=5V
l
5.0
1.6
-5
1\
1.5
~
~
I"-
.::
:::
·s.c
1.4
u
1.3
VCC= 5 V
VT _
-
!"'"r--
I---
Negative-Going Threshold VT _
>
5.5
IT+ J
~ositive-GOing Threshold VT+
.2'
'7...
5.25
lvsteLs =
1\
18.
Cext = 60 pF
RT = 10 kn IExternal)
TA = 25°C
I
1.7
"0
I I I I I
1.2
-50
o
50
100
VCC-SuppIV Voltage-V
TA-free-Air Temperature-OC
FIGURE 3
FIGURE 4
tO ata for temperatures below OOC and above 70°C are applicable for SN54121.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-371
SN54121, SN74121
MONOSTABLE· MULTlVIBRATORS
WITHSCHMITT·TRIGGER INPUTS
TYPICAL CHARACTERISTICSt (continued)
VARIATION IN OUTPUT PULSE WIDTH
OUTPUT PULSE WIDTH
VI
VI
FREE-AIR TEMPERATURE
TIMING RESISTOR VALUE
1.0%
~
~
I
jJ
l
10m.
+0.5%
J.
1 ms
VCC=5V
cT=60pF
RT= 10 kG
i/
17
-
...... tw(out) = 420
o TA· 25"c
f
n.
8
J
~."
100 ns
i.See.Note 3.
10ns
-1.0%
-50
-I
-I
7
V
o
.50
4
100
40
RT-Timing Resistor Value-kG
T A-F ....Air Temperatura-·C
r0-
10
C
CD
<
FIGURE 5
Cr
CD
FIGURE 6
DUTPUT PULSE WIDTH
en
VI
EXTERNAL CAPACITANCE
10m._..........
1
m.
lOOns
10 ns
10-"
10-9
10.7
10-5
Cext -Timing Cap.cita....-F
FIGURE 7
NOTE 5: These values of resistance exceed the maximum recommended use over the full temperature range of the SN54121.
tOata for temperatures below O·C and above 70·C are applicable for SN54121.
2-372
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
100
SN54122, SN54123, SN54130, SN54LS122, SN54LS123,
SN74122, SN74123, SN74130, SN74LS122, SN74LS123
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
DECEMBER 1983 - REVISED MARCH 1988
•
D-C Triggered from Active-High or ActiveLow Gated Logic Inputs
•
Retriggerable for Very Long Output Pulses,
Up to 100% Duty Cycle
•
Overriding Clear Terminates Output Pulse
•
SN54123, SN54130, SN54lS123 ... J OR W PACKAGE
SN74123, SN74130 ... N PACKAGE
SN74lS123 ... 0 OR N PACKAGE
(TOP VIEW) (SEE NOTES 1 THRU 4)
lA
VCC
1 Rext/Cext
lCext
10
lB
lClR
10
'122 and 'LS122 Have Internal Timing
Resistors
io
20
description
These doc triggered multivibrators feature output pu)seduration control by three methods. The basic pulse time
is programmed by selection of external resistance and
capacitance values (see typical application datal. The
'122 and 'lS 122 have internal timing resistors that allow
the circuits to be used with .only an external capacitor,
2ClR
2 Cext
2Rext/ Cext
GND
2B
2A
SN54lS122 ... FK PACKAGE
(TOP VIEW) (SEE NOTES 1 THRU 4)
~
if so desired. Once triggered, the basic pulse duration may
be extended by retriggering the gated low-level-active (A)
~
u
u -III
or high-level-active (BI inputs, or be reduced by use of
>a:
the overriding clear. Figure 1 illustrates pulse control by
(I)
Q)
CJ
3 2
retriggering and early clear.
':;
The 'lS122 and 'lS123 are provided enough Schmitt
Q)
hysteresis to ensure jitter-free triggering from the B input
C
with transition rates as slow as 0.1
millivolt per
...J
lI-
nanosecond.
9 10111213
The Rint in nominall 10 kll for '122 and 'lS122.
100 u 0 E
13 2 i£
SN54122, SN54lS122 ... J OR W PACKAGE
SN74122 ... N PACKAGE
SN74lS122 ... 0 OR N PACKAGE
(TOP VIEW) (SEE NOTES 1 THRU 41
Al
VCC
A2
Rexl/Cext
NC
Bl
B2
ClR
3
Cext
NC
0
SN54lS123 ... FK PACKAGE
(TOP VIEW) (SEE NOTES 1 THRU 4)
lClR
Rin!
0
GND
2
1 20 19
lC ext
4
5
10
6
NC
20
7
B
2ClR
NOTES: 1. An external timing capacitor may be connected
9 10111213
between C ext and Rext/Cext (positive),
2. To use the internal timing resistor of '122 or 'LS 122,
'123, '130, .S123
lA
18
lCLR
leext
1 Rext/Cext
2A
28
2CLR
2Cex t
2Rext/Cext
Pin numbers shown are for D, J, N, and W packages.
111
&
121
131
1141
1151
141
R
171
...I
~
10
~
1Q
CX
RX/CX
191
161
n
1131
&
1101
1111
Q)
C
n
151
R
1121
20
20
CX
RX/CX
tThese symbols are in accordance with ANSIIIEEE Std 91-1984
and lEe Publication 617-12.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-375
S154122. SI54123. SI54130. SI54LS122.S154LS123.
S114122. S174123. SI74130. SI74LS122. SI74LS123
RETRIGGERABLE MONOSTABLE MULTIVJ,fRATORS
schematics of inputs and outputs
'122, '123, '130 CIRCUITS
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
100 II NOM
Clear inputs : Req - 2 kll NOM
Other inputs : Req
=4
kll NOM
'LS122, 'LS123 CIRCUITS
-4
-4
EQUIVALENT OF EACH INPUT
r-
TYPICAL OF ALL OUTPUTS
o
CD
120 II NOM
<
5'
17 kll NOM
CD
(II
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) , , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: '122, '123, '130 ............................................... 5.5 V
'LS122, 'LS123 ............................................... " 7 V
Operating free-air temperature range: SN54' .......................... " - 55°C to 125°C
SN74' ................................ ooe to 70°C
Storage temperature range .......................................... - 65°C to 1 50°C
NOTE 1: Voltage values are with respect to network ground terminal.
2-376
. TEXAS.
INSTRUMENTS
POST OFFICE, BOX 655012 • DALLAS. TeXAS 75265
SN54122, SN54123, SN54130, SN74122, SN74123, SN74130
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
recommended operating conditions
SN54'
Supply voltage, VCC
High~evel
MIN
NOM
4.5
5
SN74'
MAX
MIN
NOM
5.5
4.75
5
-BOO
output current, 10H
MAX
5.25
V
-BOO
JlA
16
rnA
50
kr!
16
Low-level output current, IOl
40
Pulse duration, tw
40
External timing resistance, Rext
5
External capacitance. Cext
No restriction
25
ns
5
No restriction
50
Wiring capacitance at Rext/Cox terminal
Operating free--air temperature. T A
-55
UNIT
125
0
50
pF
70
°c
electrical characteristics over recommended free-air operating temperature range (unless otherwise noted)
TEST CONDITIONSt
PARAMETER
VIH
VIL
VIK
High-level input voltage
Low-level input vol tage
VOH
High-level output voltage
Input clamp voltage
VOL
Low-level output voltage
II
Input current at maximum input voltage
IIH
High-level input current
!
usta inputs
Clear input
Data inputs
IlL
Low-level input current
lOS
ICC
Short-circuit output current §
Supply current (quiescent or triggered)
Clear input
MIN
2
II = 12rnA
10H = BOOJlA,
VCC= MIN,
VCC = MIN,
See Note 5
VCC = MIN,
See Note 5
VCC - MAX,
VI = 5.5 V
VCC =MAX,
VI = 2.4 V
'122
TYPt
MIN
2
'123, '130
TYP:j: MAX
O.B
1.5
2.4
10L = 16 rnA,
3.4
0.4
23
1
40
BO
1.6
3.2
-40
36
10
O.B
1.5
2.4
0.2
VCC = MAX, VI=O.4V
VCC =MAX, See Note 5
VCC =MAX, See Notes 6 and 7
MAX
UNIT
V
V
V
V
3.4
0.2
0.4
V
mA
46
1
40
BO
1.6
3.2
40
66
10
IJ.A
mA
mA
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*All typical values are at VCC = 5 V, TA = 25"C.
§ Not more than one output should be shorted at a time.
NOTES:
a,
5. Ground Cext to measure VOH at a, VOL at A, or lOS at O. Cext is open to measure VOH at
VOL at a, or lOS at O.
6. Quiescent ICC is measured (after clearing) with 4.5 V applied to all clear and A inputs, B inputs grounded, all.outputs open and
Rext = 25 kll. Rint of '122 is open.
7. ICC is measured in the triggered state with 2.4 V applied to all clear and B inputs, A inputs grounded, all outputs open,
Cext = 0.02 ~F, and Rext = 25 kll. Rint of '122 is open.
switching characteristics, Vee = 5 V, TA = 25°e, see note 8
PARAMETER.
tPLH
tPHL
'tPLH =
tpHL =
twa =
NOTE 8:
FROM
(INPUT)
A
B
A
B
TO
10UTPUT)
MIN
a
0
a
tpHL
tPLH
twalminl
A or 8
a
twa
A or B
a
Clear
TEST CONDITIONS
Cext = 0,
CL=15pF,
Rext = 5 kr!,
RL =400r!
0
Cext = 1000 pF,
CL=15pF,
Rext = 10 kr!,
RL=400r!
3.0B
'122, '130
TYP MAX
22
19
30
27
lB
30
45
33
2B
40
36
27
40
65
3.42
3.76
MIN
2.76
'123
TYP MAX
33
2B
40
36
27
40
UNIT
22
19
30
27
lB
30
45
76
ns
3.03
3.37
IJ.S
ns
ns
ns
propagation delay time, low-to-high·level output
propagation delay time, high·to·low-Ievel output
duration of pulse at output a.
Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
2-377
SN54LS122, SN54LS123, SN74LS122, SN74LS123
RETRIGGERABLE MONOSTABLE MULTlVI,fIRATORS
recommended operating conditions
SN54LS'
SN74LS'
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-400
I'A
8
mA
260
ns
kn
Supply voltage. V CC
-400
High·level output current. 10H
Low-level output current. IOl
Pulse duration •. tw
External timing resistance. Rext
External capacitance, Cext
Wiring capacitance at Rext/Cext terminal
Operating free-air temperature, T A
UNIT
MIN
4
40
40
180
5
5
No restriction
No restriction
50
-55
125
0
50
pF
70
"C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
VII
VIK
High~level
VOH
High-level output voltage
Low-level input voltage
Input clamp voltage
VOL
II
IIH
IlL
lOS
ICC
TEST CONOITIONSt
input voltage
Low-level output voltage
Input current at
maximum input voltage
High-level input current
Low-level input current
Short-circuit output current§
Supply current
(quiescent or triggered)
Vee = MIN,
VCC = MIN.
VIL = VILmax
VCC = MIN,
VIL = VILmax
11=-18mA
VIH = 2 V,
IOH = -4001'A
VIH=2V,
POL 4mA
tlOL =8mA
VCC =MAX,
VI =7 V
VCC- MAX,
VCC = MAX,
VCC=MAX
VI = 2.7 V
VI- 0.4 V
VCC=MAX,
See Note 13
SN54LS'
SN74LS'
UNIT
MIN TYPt MAX MIN TYP± MAX
2
2
V
0.7
0.8
V
-1.5
-1.5
V
2.5
3.5
2.7
0.25
-20
'LSI22
!'LS123
6
12
0.4
3,5
0.25
0.35
V
0.4
0.5
V
0.1
0.1
mA
20
-0.4
100
11
20
20
0.4
100
11
20
I'A
mA
mA
20
6
12
mA
tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vec = 5 V, TA = .25°C.
§Not more than one output should be shorteQ.at a time and duration of the short-circuit should not exceed one second.
NOTES: 12. To measure VOH at a, VOL at a, or lOS at a, ground Rext/Cext, apply 2 V to B and clear, and pulse A from 2 V to 0 V.
13. With all outputs open and 4.5 V applied to all data and clear inputs. ICC is measured after a momentary ground. then 4.5 V.
is applied to A or B inputs.
switching characteristics, Vee = 5 V, TA = 25°e (see note 8)
PARAMETER~
tpLH
tPHL
FROM
(I NPUTI
A
B
A
B
TO
(OUTPUTI
TEST CONDITIONS
a
a
tpHL
tPLH
twa (min)
Clear
a
A or B
a
twa
Aor B
a
Cext = 0,
CL = 15pF,
Cext =1000 pF.
CL = 15 pF,
'tPLH = propagation delay time, low·to-high-Ievel output
tpHL = propagation delay time, high·to·low-Ievel output
twa = duration of pulse lit output a.
NOTE 8: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
2-378
MIN
a
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
R ext = 5 kn,
RL = 2 kn
Rext = 10 k!1,
RL = 2 kn
4
TYP
MAX
23
23
32
34
20
28
116
33
44
45
56
27
45
200
4.5
5
UNIT
ns
ns
ns
ns
!,S
SN54122, SN54123, SN54130
SN7412t SN7412t SN74130
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
TYPICAL APPLICATION DATA FOR '122, '123, '130
For pulse durations when C ext :,; 1000 pF, see
Figure 4.
The output pulse duration is primarily a function of the
external capacitor and resistor. For Cext > 1000 pF,
the output pulse duration (t w ) is defined as:
tw = K • RT • Cext
( 0.7)
1 + RT
termmal
terminal
TIMING COMPONENT CONNECTIONS
FIGURE 3
where
K is 0.32 for '122, 0.28 for '123 and '130
TYPICAL OUTPUT PULSE DURATION
vs
EXTERNAL TIMING CAPACITANCE
RT is in kl'! (internal or external timing
resistance. )
Cext is in pF
tw is in ns
II)
(J)
CJ
To prevent reverse voltage across Cext, it is
recommended that the method shown in Figure 2 be
employed when using electrolytic capacitors and in
applications utilizing the clear function. In all
applications using the diode, the pulse duration is:
tw
=
KD • RT • Cext
'S;
(J)
o
( 0.7)
'
...I
....
....
1 + RT
KD is 0.28 for '122, 0.25 for '123 and '130
10
20
40
100
200
400
1000
FIGURE 4
R ext ~ 0.6 Rextmax.
(See recommended operating
conditions for Rextmax.l
tThese values of resistance exceed the maximum recommended
for use over the full temperature range of the SN54' circuits.
Any silicon switching diode
such as 1 N 3064 or
equivalent.
To Cext
terminal
To Rext/Cext
terminal
TIMING COMPONENT CONNECTIONS WHEN
Cext ;. 1000 pF AND CLEAR IS USED
FIGURE 2
Applications requiring more precise pulse durations (up
to 28 seconds) and not requiring the clear feature can
best be satisfied with the '1 21 .
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-379
SN54LS122, SN54LS123, SN74LS122,SN74LS123
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
TYPICAL APPLICATION DATA FOR 'LS122, 'LS123
The basic output pulse duration is essentially
determined by the values of external capacitance and
timing resistance. For pulse durations when
Cext s 1000 pF, use Figure 6, or use Figure 7 where
the pulse duration may be defined as:
tw = K • RT • Cext
When Cext 2: 1 JLF, the output pulse width is defined
as:
To Cext To Aext/Cext
terminal
terminal
tw = 0.33 • RT • Cext
For the above two equations, .as applicable;
TIMING COMPONENT CONNECTIONS
K is multiplier factor, see Figure 7
RT is in kG (internal or external timing resistance)
Cext is in pF
tw is in ns
-I
-I
r-
C
(1)
<
ri"
FIGURE 5
For maximum noise immunity, system ground should
be applied to the Cext node, even though the Cext
node is already tied to the ground lead internally. Due
to the timing scheme used by the 'LS122 and 'LS123,
a switching diode is not required to prevent reverse
biasing when using electolytic capacitors.
'LS122, 'LS123
TYPICAL OUTPUT PULSE DURATION
(1)
en
vs
EXTERNAL TIMING CAPACITANCE
100000
:VCC - 5 V E -
RT = 260k ohm.\'
;'
'vvv
100
./
k
I-
RT- aOk 0 hm.
RT = 40k 0 hms
RT = 20k 0 hms
RT=10ko hms
RT= 5k 0 hms
---~
II
10
10
100
1111
1000
Cext- External Timing Capacitance - pF
tThis value of resistance exceeds the maximum recommended for use
over the full temperature range of the SN54LS circuits.
FIGURE 6
2-380
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 76265
SN54LS122, SN54LS123, SN74LS122, SN74LS123
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
TYPICAL APPLICATION DATA FOR 'LS122, 'LS123t
MULTIPLIER FACTOR
vs
EXTERNAL CAPACITOR
DISTRIBUTION OF UNITS
vs
OUTPUT PULSE DURATION
VCC=5 V
TA=25°C
u.
.."
I
flc
(K IS INDEPENDENT OF RI
e
0.1
"
a;
g
>
o
S
'uco
.....
u
E
.."
g
.-
\
a;
~
IlJ
'0
\
0.01
"
g
1
.
u.
\
0.001
MEDIAN
+ ~O% -; I'lS~ 221
I--MEDIAN
-20%
"-
I
c!
0.0001
.~
-8%
I
I
a;
a:
"'"
.I
_',
~ee N,ote 14
>
+18% _ll'lSll221
..........
I/)
'lSl,231
-'
Q)
CJ
">
I---MEDIAN-r-98% OF UNITS
0.25 0.30 0.35 0.40 0.45 0.50 0.55
K - Multiplier Factor -
twloutl-Output Pulse Duration
Q)
C
FIGURE 8
FIGURE 7
...J
VARIATION IN OUTPUT PULSE DURATION
vs
SUPPLY VOLTAGE
c
.~ 4%
Cext= 60 pF
::I
Q
3%
Rext = 10 K ohmsTA = 25°C
'3 2%
Q.
...
"'-
"- -......
:;
~
0
1%
.5
0%
c
'"
.~ -1%
'.
~ -2%
~
~
0-3%
-
tw(out) "" 370 ns
atVcc= 5V
1
'I
5:
~
:;
:;
o
:s
"'" -........
I
4.75
5.25
5
Vcc - Supply Voltage - V
FIGURE 9
5.5
Vcc= 5 V
Cext = 60 pF
RT = 10 K ohms
8%
6%
""-
4%
2%
0%
:i
-2%
~
-4%
co
"'"
12%
10%
Q
.5
J
<1-4%
4.5
:s
'!
"
...
~
lI-
VARIATION IN OUTPUT PULSE DURATION
vs
FREE-AIR TEMPERATURE
'-"
~ -6%
'i
u ~ u tl~
u..NZ>O
description
3 2
The '5124 features two independent voltagecontrolled oscililators (VCO) in a single monolithic
chip. The output frequency of each VCO is established
by an external capacitor in combination with two
voltage-sensitive inputs, one for frequency range and
one for frequency control. These inputs can be used
to vary the output frequency as shown under typical
characteristcs. These highly stable oscillators can be
set to operate at any frequency typically between
0.12 hertz and 85 megahertz. Under the conditions
used in Figure 1, the output frequency can be
approximated as follows:
5 X lQ-2
fo
where:
VCC
05C VCC
2 RNG
2CX2
2 CXI
2 EN
2V
GND
fo
Cext
1 RNG
CXl
NC
1 CX2
1 EN
1
4
5
en
2 RNG
2 CX2
NC
2 eXl
2 EN
6
7
8
Q)
CJ
·S
Q)
C
...I
9 10111213
lI-
)-CUC)-
~ZZZN
t:l
t:l
U
III
o
NC - No internal connection
logic
Cext
output frequency in hertz
external capacitance in farads.
While the enable input is low, the output is enabled.
While the enable input is high, the output is high.
These devices can operate from a single 5·volt supply. However, one set of supply-voltage and ground pins (VCC and
GND) is provided for the enable, synchronization·gating, and output sections, and a separate set aVee andeGND)
is provided for the oscillator and associated frequency·control circuits so that effective isolation can be accomplished in
the system.
The enable input of these devices starts or stops the output pulses when it is low or high, respectively. The internal
oscillator of the 'S124 is started and stopped by the enable input. The enable input is one standard load; it and the
buffered output operate at standard Schottky-clamped TTL levels.
The pulse synchronization·gating section ensures that the first output pulse is neither clipped nor extended. Duty
cycle of the square·wave output is fixed at approximately 50 percent.
The SN54S124 is characterized for operation over the full military temperature range of _55°C to 125°e; the
SN74S124 is characterized for operation from oOe to 70o e.
PRODUCTION DATA docu_ contlin information
current as of publicatio. dotl. Productl conform to
.,..ificatio.s par dI. tarms .f T.... lutrumants
=~~~·i:I~1i ~!:~::i~n :.~o::;:::.:;:s not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-383
SN54S124, SN74S124
DUAL VOLTAGE·CONtROLLED OSCILLATORS
logic symbol t
lEN
I RNG
I FC
ICXI
ICXZ
ZEN
2 RNG
2 FC
2CXI
2CX2
OSC GND
-I
-I
r-
C
tThis symbol is in accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617-12.
Pin numbers shown are fpr 0, J, N, and W packages.
schematics of inputs and outputs
CD
<
EQUIVALENT OF EACH
ENABLE INPUT
c:;'
CD
EQUIVALENT OF EACH FREQUENCY
CONTROL OR RANGE INPUT
TYPICAL OF BOTH OUTPUTS
----_>---VCC
til
Vce--____-._____
50!l NOM
Vee ----1>--INPUT
INPUT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (See Notes 1 and 2) ___ ... _ ......... ___ ...... __ ..... ___ .... _ . - .. - .... 7V
Input voltage _ ... _ .... _ ...... _ . . . . . . . . . . . . . . . . . . _ ........... _ ........... _ . . .. s_s V
Operating free-air temperature range: SNS4S124 .. _ .. _ .. ___ . _ ....... _ .......... _ _ -ssoe to 12Soe
SN74S124 ......... _ ...... _ ....... _ . . . . . . . . . .. oOe to 70°C
Storage temperature range .... _ ......... _ ... _ ....... _ .. _ ........ _ . _ ...... _ -6Soe to 1S0oe
NOTES: 1. Voltage values are with respect to the appropriate ground terminal.
2. Throughout this data sheet, the symbol Vee is used for the voltage applied to both the
wise noted.
2-384
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Vee
and
0vcc terminals,
unless other-
SN54S124, SN74S124
DUAL VOLTAGE·CONTROLLED OSCILLATORS
recommended operating conditions
SN54S124
MIN
SupplV voltage, Vee lsee Note 1)
SN74S124
NOM
MAX
MIN
NOM
MAX
5
5.5
4.75
5
5.25
5
1
4.5
1
Input voltage at frequency control or range input, VI(freq) or VI(rngl
5
-1
High·level output current, IOH
Low-level output current, tOl
20
-55
125
V
mA
20
mA
60
MHz
70
"e
Hz
60
Operating free-air temperature, T A
V
-1
1
1
Output frequency (enabled I , f 0
UNIT
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage at enable
VIL
Low-level input voltage at enable
VIK
Input clamp voltage at enable
TEST CONDITIONSt
II
MAX UNIT
V
11- -18mA
VeC" MIN,
VCe" MIN, VIH = 2V,
10H = -1 mA
Vce- MIN,
VOL Low-level output voltage
I SN54S'
I SN74S'
2.5
3.4
2.7
3.4
VIL - 0.8 V,
or range
I VI- 5V
Vee" MAX
0.8
V
-1.2
V
V
0.5
10L" 20mA
F req control
Input current
TYPj:
2
VOH High-level output voltage
II
MIN
10
50
1
15
I VI" 1 V
V
U)
~A
·S
mA
C
....I
Q)
Input current at
maximum input voltage
Enable
VCC" MAX,
VI" 5.5 V
1
IIH
High-level input current
Enable
Vee= MAX, VI" 2.7V
50
~A
IlL
Low-level input current
Enable
Vee - MAX, VI=0.5V
-2
mA
lOS
Short-circuit output current §
-100
mA
ICC
e
-40
Vce- MAX
VCC" MAX, See Note 3
Supply current, total into
Vee and
Q)
(,)
Vee = MAX, TA - 125"e,
Vee
l
105
W package
150
110
only
See Note 3
lI-
mA
tForconditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
tAli typical values are at VCC
5V. TA = 25°C.
'Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 3: ICC is measured with the outputs disabled and open.
=
switching characteristics, Vec = 5 V, RL = 280 n, CL = 15 pF, TA = 25°C (see note 4)
PARAMETER
10
tPHL
TEST CONDITIONS
=
2 pF
I Villreq)" 4 V, Vllrng) "
1V
Vilireq) - 1 V, Vllrng) - 5 V
Output frequency
C ext
Output duty cycle
Cext - 8.3 pF to 500
Propagation delay time,
10 = 1 Hz to 20 MHz
high-to-Iow-level output from enable
I
~F
MIN
60
25
TYP
85
40
UNIT
MHz
50%
1.4
10 1Hz)
70
10 " 20 MHz
MAX
s
ns
NOTE 4: load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-385
SN54S124, SN74S124
DUAL. VOL TAGE·CONTROLLED OSCILLATORS
TYPICAL CHARACT!:;RISTICS
BASE OUTPUT FREQUENCY
NORMALIZED OUTPUT FREQUENCY
vs
vs
EXTERNAL CAPACITANCE
INPUT VOLTAGE
1.2
1G
N
100M
J:
I
?;
.,c
g
...::>
e::>
10M
.::>
1M
LL
100 k
a
VCC = 5 V
Vl(freq) = Vl(rng) = 2 V
TA=25°C
'"
~
10k
1k
f!
'" '"
...::>
e
LL
::>
a
"-
.,
"0
.~
<;j
",,-
E
is
'\
10
z
0.1
10- 12
CD
<
cr
CD
I
..E
'\.
r-
C
10- 10
,1.1
C'
100
-I
-I
>
.,"::>c
10- 8
10-6
'"
Vl(rng) = 4.5 V
0.5
10-4
0
Cext - External Capacitance - F
en
FIGURE 1
NOT"E: fo
2·386
2
3
VI(freq)-lnput Voltage-V
FIGURE 2
= fn X fo(base)
TEXAS
~
INSTRUMENTS
, POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4
5
SN54125. SN54126. SN54LS125A. SN54LS126A.
SN74125. SN74126. SN74LS125A. SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3"STATE OUTPUTS
- REVISED MARCH 1988
SN54125,SN54126,SN54LS125A,
SN54LS126A ... J OR W PACKAGE
SN74125, SN74126 ... N PACKAGE
SN74LS125A, SN74LS126A ... 0 OR N PACKAGE
(TOPVIEWI
• Quad Bus Buffers
• 3-State Outputs
• Separate Control for Each Channel
1G,lG*
lA
1Y
2G,2G*
2A
2Y
GND
description
These bus buffers feature three-state outputs that,
when enabled, have the low impedence characteristics
of a TIL output with additional drive capability at high
logic levels to permit driving heavily loaded bus lines
without external pull-up resistors, when disabled, both
output transistors are turned off presenting a highimpedance state to the bus so the output will act neither
as a significant load nor as a driver. The. '125 and
'LS125A outputs are disabled when Gis high. The '126
and 'LS126A outputs are disabled when G is low.
VCC
4G,4G*
4A
4Y
3G,3G*
3A
3Y
SN54LS125A, SN54LS126A ... FK PACKAGE
(TOPVIEWI
logic diagram (each gate)
II)
3
'125, 'LS125A
1Y
NC
2G,2G*
NC
2A
:=t>-,
2
Q)
1
CJ
4A
NC
4Y
NC
3G,3G*
4
5
6
8
"S;
Q)
C
...I
....
I-
>-ou>-<
"'22"''''
(!)
'126, LS126A
"IT on
'125 and 'LS125A; G on 126 and 'LS126A
NC - No internal connection
positive logic Y
=
A
logic symbols t
',25
li3 111
lA 121
2G (41
2A (5)
3G 110l
3A (91
4G (131
4A
(12)
'LS125A
1
'V
(3) 1V
(6) 2V
18) 3Y
1G
lA (2)
2(; (4)
1[>
'V
131 1Y
(61 2V
2A (51
J'G" 1101
(8)
3A (9)
4G
(11) 4Y
EN
(13)
3Y
(111 4Y
4A 1121
'LS126A
'126
_ 111
EN
1G
111
EN
1
lA (2)
2G (41
2A (51
3G 1101
3A 191
4G 113)
4A 1121
'V
I"
1V
(6) 2V
(8)
3V
1G
111
3G l!l1o;o•.-l----i
4G
4Y
11>
(3) 1V
lA 121
2G 141
2A (5)
3A 191
1111
EN
111131"1----1
16}
181
zv
3Y
Ill} 4V
4A 1121
tThese symbols are in accordance with ANSIIIEEE Std. 91-1984 and IEC Publication 617-12.
Pin numbers shown are for 0, J, N. and W packages.
PRODUCTION DATA documonts contain in'ormalion
current as of publication data. Products conform to
spacifications par tha tarms of TaXIS Instruments
::~:~~i~.irnr:I'::li ~!:~:~ti:; lI~o::::::t:~~
not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-387
SN54125,SN54126, SN74125, SN74126
QUADRUPLE BUS BUFFERS WITH 3·STATE OUTPUTS
schematics (each gate)
r-----.---._------~~--~~--------._------~_.-VCC
OUTPUT
CONTROL
INPUT
V
G
DATA
INPUT
A
'125 CIRCUITS
r-----._--._----~~--~~----._--------~------~~~vcc
-t
-t
r0
C'D
<
c=i"
OUTPUT
CONTROL
INPUT
C'D
til
V
G
DATA
INPUT
A
L-----~~--~--~--+_~~--._~~--~----~------~---GND
'126 CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (See Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54' .................................... -55°e to 125°e
~W
........................................
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..
NOTE 1: Voltage values are with respect to network ground terminal.
2-388
'TEXAS . "
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS, TEXAS 75265
O~mro~
- 65 °e to 150 0 e
SN54LS125A, SN54LS126A, SN14LS125A, SN14LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
schematics (each gate)
r-----_.---e----~----~~----------._--_.----------~-vcc
OUTPUT
G
INPUT
~~'_-----4--------~-r~--------
__
--------~--~--~--_'--GND
AINPUT------------------------~
'LS125A CIRCUITS
U)
Q)
(,)
r-----t-----.---.------1~----~----------~~--_1~--------_.--vcc
'S;
18kn
Q)
C
...J
l-
I-
OUTPUT
L-----~----_*------------~_r~--------+-----~r_----~~--~-----GND
AINPUT----------------------------~
'LS126A CIRCUITS
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 11 ...
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54'
SN74' ..
Storage temperature range
.. ... 7 V
... 7 V
- 55°e to 125°e
ooe
to 70 0 e
- 65 °e to 1 50 °e
NOTE 1: Voltage values are with respect to network ground terminals.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 ,. DALLAS. TEXAS 75265
2-389
SN54125, SN54126, SN14125, SN14126
QUADRUPLE BUS BUFFERS WITH 3·STATE OUTPUTS
recommended operating conditions
SN54125, SN54126
SN74125, SN74126
MiN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
V
UNIT
Vee
Supply voltage
V,H
High-level input voltage
V,L
Low-level input voltage
0.8
0.8
10H
High-level output current
-2
- 5.2
mA
10L
Low-level output eu rrent
16
16
mA
70
"e
2
Operating free-air temperature
TA
2
- 55
125
V
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONOITIONS t
PARAMETER
V,K
VOH
VOL
-I
-I
10Z
r-
Vee - MIN,
,,- -12 mA
Vee" MIN,
V'H-2V,
Vee" MIN,
<
c:;'
CD
Vee" MAX,
10H ~ -2 mA
10H - -5.2 mA
2.4
-1.5
2.4
UNIT
V
V
3.1
0.4
0.4
LVO" 2.4 V
40
40
Vo - 0.4 V
-40
-40
1
1
I
V!L" 0.8 V
MAX
3.3
V,L - 0.8 V,
V'H-2V,
V'H"2V,
TVP*
V
I'A
MAX,
V," 5.5 V
"H
"
Vee" MAX,
V,-2.4V
40
40
I'A
',L
10S§
Vee- MAX,
V,"O.4V
-1.6
- 1.6
mA
-70
mA
ICC
en
MAX
10L" 16 mA
Vee
o
CD
SN74125, SN74126
MIN
TVP*
-1.5
I
I
V'L"0.8V
SN54125. SN54126
MIN
-30
Vee- MAX
-70
- 28
Vee- MAX,
I
'125
32
54
32
54
(see Note 2)
I
'126
36
62
36
62
mA
mA
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee ~ 5 V, TA ~ 25°C.
§ Not more than one output should be shorted at a time.
NOTE 2: Oata inputs ~ O.V; output control ~ 4.5 V for '125 and 0 V for '126.
switching characteristics, Vee = 5 V, TA = 25°e (see note 3)
PARAMETER
SN54174125
TEST eONOITIONS
TVP
MAX
tpLH
8
13
8
13
ns
tPHL
12
18
12
18
ns
11
17
11
18
ns
16
25
16
25
ns
5
8
10
16
ns
7
12
12
18
ns
RL" 400 n,
eL" 50 pF
tpHZ
tpLZ
RL"400n,
eL" 5 pF
NOTE 3: load circuits and voltage waveforms are shown in Section 1 .
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
UNIT
MAX
tpZL
2-390
SN54174126
TVP
tpZH
MIN
SN54LS125A, SN54LS126A, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH' 3-STATE OUTPUTS
recommended operating conditions
SN54LS125A
SN74LS125A
SN54LS126A
SN74LS126A
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4,5
5
5.5
4.75
5
5.25
V
V
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.7
0.8
2
2
V
IOH
High-level output current
-1
- 2.6
mA
IOL
Low-level output current
12
24
mA
TA
Operating free-air temperature
70
°c
- 55
125
a
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS125A
PARAMETER
TEST CONDITIONSt
MIN
VIK
VOH
VOL
IOZ
MIN.
11--18mA
Vee
MIN.
VIL
VIH = 2 V
IOH" -1 mA
VIL-0.8V.
VIL 0,7 V.
Vee = MIN.
VIH = 2 V
Vee = MAX.
VIH = 2 V
IOH - - 2.6 mA
MIN
UNIT
TVPt MAX
-1.5
IOL
VIL
0.8 V.
IOL
12mA
0.25
0.4
VIL
0.8 V.
IOL - 24 mA
0.35
05
VIL = 0.8 V
2.4 V
20
- 20
Vo
20
0.4 V
VI
7V
VI
2.7 V
Vce = MAX.
'LS125A·G input.
VI " 0.4 V
'LS125A·A inputs; 'LS126A All inputs
I
~A
0.1
0.1
20
20
~A
- 0.2
- 0.2
mA
- 0.4
mA
- 0.4
- 40
I
V
- 20
Vee = MAX.
VCC MAX
VCC = MAX,
(,ee Note 21
0.4
Vo 0.4 V
Vo - 2.4 V
Vo
VI L = 0.7 V
0.25
V
V
2.4
12mA
Vee - MAX.
ICC
SN74LS126A
MAX
2.4
II
IOS§
TVPt
-1.5
0.7 V.
IIH
IlL
t
Vee
SN74LS125A
SN54LS126A
'LS125A
'LS126A
- 225
- 40
- 225
11
20
11
20
12
22
12
22
mA
mA
mA
For conditions shown as MIN or MAX, use the appropriate value specified under reGomrnended operating conditions.
* All typical values are at Vee
~< 5 V, TA' C 25 C.
§ Not more than one output should be shorted at a time. and duration of the short circuit should not exceed one second.
NOTE 2: Data inputs··
a V; Output controls
4.5 V for 'LS125A and
av
for 'LS126A.
switching characteristics. Vee = 5 V. TA = 25°e (see note 3)
PARAMETER
SN54174LS125A
TEST CONDITIONS
MIN
tPLH
tPHL
RL = 667
tpZH
n,
CL=45pF
tpZL
tpHZ
tPLZ
RL
= 667 n,
CL
= 5 pF
TVP
MAX
9
15
7
18
12
20
15
25
SN54174LS126A
MIN
UNIT
TVP
MAX
9
8
15
ns
18
n.
16
25
n.
21
35
ns
20
25
n.
20
25
n.
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-391
-I
-I
rC
CD
:::.
o
CD
en
2-392
SN54128, SN74128
LINE DRIVERS
DECEMBER 19B3 - REVISED MARCH 1988
• Package Options Include Plastic and
Ceramic DIPs and Ceramic Flat Packages
SN54128 ... J OR W PACKAGE
SN74128 ... N PACKAGE
(TOPYIEWI
• Dependable Texas Instruments Quality and
Reliability
1Y
lA
1B
2Y
2A
2B
GND
description
These devices contain four independent 2-input-NOR
line drivers. They perform the Boolean function
Y = A + B or Y = A . B. The SN54128 is designed
to drive 75 ohm lines. The SN74128 is designed to drive
50 ohm lines.
The SN54128 is characterized for operation over the full
military temperature range of -55'e to 125'e. The
SN74128 is characterized for operation from oDe to
70 D e.
logic diagram (each driver)
Vee
4Y
4B
4A
3Y
38
3A
schematic (each driver)
.--.----.-----------.--Ycc
30n
INPUTS
A
OUTPUT
Y
B
•
.(/)
CD
C,)
'>CD
logic symbol t
C
....I
1A
L-4---------.---------~
18
2A
__
lI-
--~-GND
Resistor values shown are nominal.
28
3A
38
4A
48
tThis svmbol is in accordance with ·ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)......•.••.•••.•••••.••.•.•.••••.....••..•..••.•.•...•........... 7 V
Input voltage. • • . . . • • . . • • • • . • • • • . • • . • • • . . • • • • . . . . • • . . . . . • . . • . . . . . . . . . . . . • • . • . • . • . . . • • . • . .• 5.5 V
Operating free-air temperature range: SN54'............................................ - 55°C to 125°e
SN74' ••••••••.•.•••.•••••.••...•••••.•••.•..•••••.•. oOe to 70°C
Storage temperature range •.•.........•.•••.. _ • • . • . . • • . . . . . . . . . . . . . . . . . . • • . . • . . . • . .. - 65°e to 1500 e
NOTE 1: Voltage values are with respect to network ground terminal.
PRODU&TIOI DATA dacomltlllca.lllnl.l.rmoti••
..rn.t •• of p..liNII•• doto. ProdOoll oo.farm 10
IjIIClflootio•• PI' I~' ttrm••1 T.... I.otrum.nll
IlIld.nI
Prodlctio. ,_iag d... not
.......rlly inolodo lilting of .11 penmttlr•.
.I".ony.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·393
SN54128, SN74128
LINE DRIVERS
recommended operating conditions
SN54128
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
IOL
High-level output current
Low-level output current
TA
Operating free-air temperature
SN74128
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.8
0.8
-29
- 42.4
rnA
48
rnA
70
°e
48
-55
UNIT
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS t
PARAMETER
•
~
C
CD
<
c:r
CD
en
TYP*
MAX
UNIT
-1.5
V
11=-12rnA
Vee - MIN,
VIL - 0.8 V,
IOH - -2.4 rnA
2.4
Vee = MIN,
VIL =O.4V,
IOH = - 13.2 rnA
2.4
Vee - MIN,
VIL =O.4V,
IOH - MAX
VOL
Vee -MIN,
VIH=2V,
IOL =48 rnA
II
Vee - MAX,
VI -5.5V
IIH
Vee -MAX,
VI -2.4V
40
/lA
IlL
Vee -MAX,
VI-O.4V
-1.6
rnA
VOH
-I
-I
MIN
Vee = MIN,
VIK
3.4
V
2
0.26
0.4
1
-70
V
rnA
IOS§
Vee -MAX
-180
rnA
leeH
Vee- MAX
12
21
rnA
leeL
Vee -MAX
33
57
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t
All typical values are at V Cc
~ 5 V, T A
=
25° C.
§ Not more than one output should be shorted at a time.
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
PARAMETER
FROM
TO
(INPUT)
10UTPUT)
Aor B
Y
tpLH
tpHL
tpLH
tpHL
TEST CONDITIONS
RL = 133!1,
eL =50pF
RL=133!1,
eL = 150pF
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2-394
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
TYP
MAX
6
9
8
12
10
15
12
18
UNIT
ns
ns
ns
ns
SN54132, SN54LS132, SN54S132,
SN74131 SN74LS131 SN74S132
QUADRUPLE 2-INPUT POSITIVE-NAND SCHMITT TRIGGERS
DECEMBER 1983 - REVISED MARCH 1988
SN54132. SN54lS132. SN54S132 ... J OR W PACKAGE
SN74132 ... N PACKAGE
SN74LS132. SN74S132 ... 0 OR N PACKAGE
• Operation from Very Slow Edges
• Improved Line-Receiving Characteristics
(TOP VIEWI
• High Noise Immunity
Vee
4B
4A
4Y
3B
description
Each circuit functions as a 2-input NAND gate. but
because of the Schmitt action. it has different input
threshold levels for positive (VT + ) and for negative going (VT _) signals.
These circuits are temperature-compensated and can be
triggered from the slowest of input ramps and still give
clear. jitter-free output signals.
SN54LS132. SN54S132 ... FK PACKAGE
(TOP VIEWI
The SN54132. SN54LS132. and SN54S132 are
characterized for operation over the full military
temperature range of -55°e to 125°e. The SN74132.
SN74LS132. and SN74S132 are characterized for
operation from ooe to 70 oe.
3
2
1 20 19
CI)
(l)
CJ
"S;
logic diagram (positive logic)
(l)
lA---I""'"1B
_--IIL.,..D"...,J»----
C
9 10111213
...J
1Y
lI-
2A~2Y
2B~
:: _~I_.D"~}--
NC-No internal connection
3Y
logic symbol t
::_~I_Jrr~}__4Y
lA
18
2A
28
3A
38
4A
48
(1)
&D
(2)
(41
(5)
(9)
(10)
(12)
(13)
positive logic: Y = AB or Y =
A+ B
tThis symbol is in accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
PRODUCTION DATA documents contlin info,mation
currant I. of publication dat8. Products conform to
spacifications per the tarms of TaXIS Instruments
:!:=~i~.ir::I~~i ~!:~:~ti:; ~~o::~:::£:~~ not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 65S01 2 • DALLAS, TEXAS 75265
2-395
SN54132. SN54LS132.SN54S132.
SN74132. SN74LS132. SN74S132
QUADRUPLE 2·INPUT POSITIVE·NAND SCHMITT TRIGGERS
schematics
'LS132 CIRCUITS
'132 CIRCUITS
.-~~-.------~--~----~~--vcc
~~
~n
NOM
NOM
INPUTS
'--_-;:...;ouV
A-
~
i
;; 0.86
1.66
1.64
~
!
.~
0.88
......... ....
:g
~
f
Vee = 5 V
... 0.87
... 1.65
]
0.90
I 0.89
V ....
'" 0.85
c
.~
1.63
l.,...---
V
0.84
0.83
f 1.62
i 0.82
~ 1.61
~ 0.81
I
>
1.60
-75 -50 -25
0
25
50
75
100 125
0.80
-75 -50 -25
0
25
50
75
TA - Free-Air Temperature _
°c
TA - Free-Air Temperature -
100 125
II)
°c
Q)
CJ
'S
Q)
C
...J
HYSTERESIS
vs
DISTRIBUTION OF UNITS
FOR HYSTERESIS
FREE·AIR TEMPERATURE
lI-
650
840
~ 830
.r- r-..
I 820
.....
............
1
810
>
:t
Vee = 5 V
TA=25°e
Vee =5 V
........
I'
'-
800
I
I 790
~
I
I 780
+
~ 770
760
750
-75 -50 -25
0
25
50
75
TA - Free-Air Temperature _
-
/
./
740 760 780 800 820
100 125
\
'-.. ' -
840 860 880 900
VT+ - VT _ -Hysteresis - mV
°c
t Data for temperatures below 0° C and 70'" C and supply beluw 4.75 V and above 5.25 V are applicable for SN54132 only.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·401
SN54132, SN74132
QUADRUPLE 2·fNPUT POSITIVE·NAND SCHMITT TRIGGERS
TYPICAL CHARACTERISTICS OF '132 CIRCUITS
HYSTERESIS
THRESHOLD VOLTAGES
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
2.0
TA·25°e
1.8
--l-- I-- I--
1.6
;:. 1.4
>
--1.;;tive.c;oing Threshold Voltage. VT+
...>
1.0
1 0.8
!
-I
-I
r-
C
Nagative·Going Threshold Voltage, VT-
1--1-4-+-4--1----4--+--1
1--I~4-+-4--1----4--+--I
£!
1--1-4-+-4--1----4--+--1
.~
I
E1.2
"0
1.6
I 1.4
1.2
iI
1.0 ~-l--+--I--4---I--I--+--l
,.!.
>
0.81....J--+-+==l==I===l==:t:=~
0.6
~ 0.6 ~-l--+--I--4---I--I--+--l
0.4
!: 0.4 1--l--+--I--4---I--I--+--l
0.2
o
4.5
0.2
1--4-+-+----1--+-+----1I---l
OL--L__~~__~~__~~~
4.75
5.25
5.5
4.5
VT+ - VT- - Hvsteresis - mV
5.25
4.75
Vee - Supply Voltage - V
CD
<
c:r
CD
(II
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
4
Vee=5 V
TA = 25°e
I
I-JT_
VT+
i--
;:.3
I
t
~
~
2
&
c5
I
~1
o
o
0.4
0.8
1.2
1.6
Vee - Supply Voltage - V
t Data for temperatures below OG
2-402
e and 70°C and supply below 4.75 V
and above 5.25 V are applicable for SN54132 only.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
5.5
SN54LS132, SN74LS132
QUADRUPLE 2·INPUT POSITIVE·NAND SCHMITT TRIGGERS
TYPICAL CHARACTERISTICS OF 'LS132 CIRCUITS
POSITIVE·GOING THRESHOLD VOLTAGE.
vs
FREE·AIR TEMPERATURE
NEGATIVE·GOING THRESHOLD VOLTAGE
vs
FREE·AIR TEMPERATURE
1.70
~
f
o
>
o
"
1.68
1.67
" 0.87
-5 1.66
~
~
1.65
'0
~ 1.64
Vee = 5 V
I 0.89
~
./
--
0.88
]
V
:: 0.86
~en 0.85
~
0.84
~
0.82
I-"""
~
V
........ r--
c
1
:~ 1.63
~
0.90
.
i
>
Vee = 5 V
1.69
0 .83
1.62
I
+
~1.61
~ 0.81
1.60
25
50
75 100
-75 -50 -25
TA - Free-Air Temperature _ °c
>
125
0.80
-75 -50 -25
0
25
50
75 laO
TA - Free-Air Temperature _ °c
If)
125
Q)
(.)
'S
Q)
o
HYSTERESIS
vs
FREE·AIR TEMPERATURE
850
ve~=
Vee = 5 V
840
>
830
.~
810
:I:
I
-",",-
to-
BOO
....... ~
,!. 790
I
I 780
+
99% ARE
ABOVE
~ 770
~
760
750
-75 -50 -25
0
25
50
75 100
TA - Free-Air Temperature _ °c
aOc and
'\
I"'- ~
>
t Data for temperatures below
lI-
t
5
rTA = 25°C
E
~ 820
;.
..J
DISTRIBUTION OF UNITS
FOR HYSTERESIS
125
720
V
/
\
i'-.t'---
740 760 780 800 820 840 860
VT+ - Vr _ - Hysteresis - mV
880
above 700e and supply voltagE.:s below 4.75 V and above 5.25 V are applicable for SN54LS132 only.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-403
SN54LS13t SN74LS132
QUADRUPLE 2·INPUTPOSITIVE·NAND SCHMITT TRIGGERS
TYPICAL CHARACTERISTICS OF 'LS132 CIRCUITS
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
THRESHOLD VOLTAGES AND HYSTERESIS
vs
SUPPLY VOLTAGE
2.0
1.6
>
I
4
TA = 25°e
1.8
Jv
Vee TA = 25°e
~
,...-- ....Positive·Going Threshold Voltage, VT+
-t-
t+ -
1.4
~1.2
~ 1.0 r-- Negativl.GOin~ Thr.!hOld tltagl. VT J-:;:
."
'0
~ 0.8
Hysteresis, VT +
VT_
~ 0.6
0.4
0.2
-I
-I
o
r-
o
n·
CD
4.5
5.25
4.75
5
Vee - Supply Voltage - V
0.4
5.5
0.8
1.2
1.6
VI -Input Voltage - V
2
~
en
t Oata for temperatures below OoC and above 70°C and supply voltages below 4.75 V and above 5.25 V are applicable for SN54LS132 only.
2-404
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54132. SN54LS132. SN54S132.
SN74132. SN74LS132. SN74S132
QUADRUPLE 2-INPUT POSITIVE-NAND SCHMITT TRIGGERS
TYPICAL APPLICATION DATA
I
I
I TTL SYSTEM
-1
CMOS
~.
.
\•
______
~8-D--I
~
~,:
SINE-WAVE
OSCILLATOR
~
__
TTL SYSTEM INTERFACE
FOR SLOW INPUT WAVEFORMS
PULSE SHAPER
III
Q)
CJ
-S
0.1 Hz to 10 MHz
Q)
C
330n
..J
lI-
INPUT
MULTIVIBRATOR
THRESHOLD DETECTOR
Open-collector
output
INPUT
r---'"' p O U T P U T
- - - tI
I
I
y;
--i
)
rI
I
I
l_>~J
.IT--
1
PULSE STRETCHER
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265
2·405
2-406
SN54S133. SN74S133
13·INPUT POSITIVE·NAND GATES
DECEMBER 19B3 - REVISED MARCH 19BB
•
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers
and Flat Packages. and Plastic and Ceramic
DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54S133 ••. J OR W PACKAGE
SN74S133 ..• 0 OR N PACKAGE
(TOP VIEWI
A
Vee
M
L
K
B
e
D
description
J
I
E
F
G
GND
These devices contain a single 13-input NAND gate.
The SN54133 is characterized for operation over the full
military temperature range of -55"e to 125"e. The
SN74133 is characterized for operation from ooe to
70°C.
H
Y
SN54S133 ... FK PACKAGE
(TOPVIEWI
FUNCTION TABLE
INPUTS A THRU M
U
al
Q)
c
logic diagram
9 10 111213
..J
tt-
(!)OU>J:
ZZ
(!)
A
B
C
NC - No internal connection
o
E
F
--.r--.. .
G
H
I
--'L-_'
logic symbol t
y
A
J
B
K
L
M
C
0
E
positive logic
(11
&
(21
(31
(41
(51
(61
Y=A· B·e·D·E·F·G·H·I·J·K·L·M
or
Y=A+B+C+D+E+F+G+H+I+J+K+T+M
G
H
(71
(101
(111
(121
K
L
M
(131
(141
(151
tThis symbol is in accordance with ANSI/IEEE Std 91·1984
and IEC Publication 617-12.
Pin numbers shown are for 0, J, N. and W packages.
TEXAS .",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-407
SN54S133. SN74S133
13:INPUT .POSITIVE·NANO GATES
schematic
'5133
Vee
r
III11111I111I
INPUT5
A
~
B
-
50 n
2.8kn
900n
.
48::
3.5kn
~
e
K ....-
m
OUTPUT
y
0
E
25~
F
G
500n
H
-4
-4
4:
I
r-
C
K
CD
L
<
M
c:;-
~"
CD
til
.. ". .~ ".. ~ .. ~ . ~ ~ . .. ,,~ .. . ~,~ ~ . L"
"
~
~
~
~
~
.m
GND
Resistor values shown are nominal,
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) .................... . . . . . . . . . . . . . . .. . ......................... 7 V
Input voltage ............................................................................ 5.5 V
Operating free·air temperature range: SN54'............................................ - 55° C to 125°C
SN74' .... : ........................................... O"Cto 70'C
Storage temperature range ......................................................... - 65° C to 150' C
NOTE 1: Voltage values are with respect to network ground terminal.
2-408
TEXAS .. "
INSTRUMENTS
POST OFFICE BOX 85.5012 • DALLAS, TeXAS 75265
SN54S133, SN74S133
13·INPUT POSITIVE·NAND GATES
recommended operating conditions
SN54S133
SN74S133
UNIT
Vee
Supply voltage
VIH
High-level input voltage
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
V
2
2
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
-1
-1
mA
20
mA
70
°e
IOL
Low·level output current
TA
Operating free-air temperature
20
125
- 55
0
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
t
TEST CONDITIONS
SN54S133
t
SN74S133
UNIT
VIK
Vee = MIN,
11= -18 mA
VOH
Vee = MIN,
VIL= 0.8 V,
IOH = -1 mA
VOL
Vee = MIN,
VIH = 2 V,
IOL=20mA
II
Vee =MAX,
IIH
IlL
MIN
TVP*
2.5
3.4
MAX
MIN
TVP*
2.7
3.4
MAX
-1.2
-1.2
V
V
en
0.5
0.5
VI=5.5V
1
1
mA
Vee = MAX,
VI = 2.7 V
50
50
IlA
Vee =MAX,
VI=0.5V
-2
-2
mA
o
...I
IOS§
Vee=MAX
leeH
Vee= MAX,
VI =0 V
-40
leeL
Vee = MAX,
VI = 4.5 V
-100
-40
V
-100
mA
3
5
3
5
mA
5.5
10
5.5
10
mA
CD
CJ
'S;
CD
tt-
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee"'" 5 V, T A"" 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, Vee = S V, TA = 2Soe (see note 2)
FROM
TO
(INPUT)
IOUTPUT)
PARAMETER
TEST CONDITIONS
tpLH
RL = 280.n,
Any
TVP
MAX
4
6
4.5
7
UNIT
ns
eL = 15 pF
tpHL
tPLH
MIN
ns
V
RL = 280.n,
5.5
ns
6.5
ns
eL = 50 pF
tpHL
NOTE 2: load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-409
-I
-I
r0-
C
CD
<
n'
CD
(fI
2-410
S154S134. SN74S134
12·INPUT POSITIVE·NAND GATES WITH 3·STATE OUTPUTS
DECEMBER 1983 - REVISED MARCH 1988
• Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
SN54S134 •.. J OR W PACKAGE
SN74S134 ••. 0 OR N PACKAGE
ITOP VIEW)
Vee
oe
A
B
• Dependable Texas Instruments Quality and
Reliability
e
L
K
0
E
description
J
F
The '5134 feature three-state outputs that, when enabled, have the low impedance characteristics of a TTL
output with additional drive capability at high logic
levels to permit driving heavily loaded lines without external pull-up resistors. When disabled, both output
transistors are turned off presenting a high-impedance
state to the bus so the output will act neither as a significant load nor as a driver. The '5134 outputs are diabled
when G is high.
G
GND
H
y
SN54S134 ..• FK PACKAGE
ITOP VIEW)
U
::I:
ZZ
D
<.!)
E--+....I........
F
Y
G
NC - No internal connection
H--i--I
J
K
logic symbol t
L
&
EN
OC
A
B
positive logic
C
Y
=
A . B . C . 0 . E . F . G . H . I .
J . K . L or
0
Y=A+B+C+D+E+F+G+H+T+J+K+L
E
F
Output is off (disabled) when output control is high.
G
H
(2)
131
(4)
15)
161
"V
191
y
(7)
(10)
1111
(12)
(13)
K
L
(14)
tThis symbol is in accordance with ANSIIIEEE Std 91·1984
and IEC Publication 617·12.
Pin numbers shown are for 0, J, N, and W packages.
PRODUCTION DATA documents contain information
currant as of publication date. Products conform to
specifications per the terms of Texas Instruments
::~~:~~i~8{::I~~i ~:~~~ti:; ~~D::;:::::'::~ not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-411
SN54S134, SN74S134
12·INPUT POSITIVE·NAND GATES WITH 3·STATE OUTPUTS
schematic
~------~--------~.--e---vcc
2.Bkn
INPUTS
son
v
OUTPUT
~----y
A
B
C--ll-+.....
D--IH-I4
E -I-I-II-I~
F-l-hHH4
G-I-I-HHH.....
H-I-HHH-I-I4
K-I-I-I-+-+-+-+-+-+-+-.
L--IH-I-+-+~~~4-4-~
-I
-I
r
C
CD
<
,sCD
en
OUTPUT
CONTROL
~------~~-4--~-~--~~GND
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ................................................................ 7 V
Input voltage ............................................................................. 5.5 V
Voltage applied to a disabled 3'state output ...................................................... 5.5 V
Operating free-air temperature range: SN54· ............................................ - 55°C to 125°C
SN74' ................................................ ooe to 700 e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°e to 1500 e
NOTE1: Voltage values are with respect to network ground terminal.
2-412
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54S134. SN74S134
12-INPUT POSITIVE-NAND GATES WITH 3-STATE OUTPUTS
recommended operating conditions
SN54S134
Vee
Supply voltage
VIH
High·Jevel input voltage
SN74S134
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
2
UNIT
V
V
VIL
Low-level input voltage
0.8
0.8
IOH
High-level output current
-2
-6.5
rnA
20
rnA
70
°e
IOL
Low-level output current
TA
Operating free-air temperature
20
- 55
·125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDITIONSt
PARAMETER
VIK
VOH
Vee = MIN,
11=-18rnA
Vee - MIN,
VIH - 2 V
Vee - MIN,
VOL
IOZ
TYP*
MAX
VIH-2V,
IOH = - 2 rnA
I
I
VIH-2V,
MAX
-1.2
2.4
IOH = -6.5 rnA
VIL-0.8V,
VIL = 0.8 V
TVP*
3.4
2.4
UNIT
V
V
3.2
0.5
0.5
Vo - 2.4 V
50
50
Vo - 0.5 V
- 50
- 50
IOL = 20 rnA
Vee- MAX,
MIN
-1.2
I
I
VIL = 0.8 V
SN74S134
SN54S134
MIN
V
II
Vee = MAX,
VI
= 5.5V
1
1
rnA
IIH
Vee- MAX,
VI- 2.7V
50
50
/lA
IlL
Vee- MAX,
VI = 0.5 V
2
2
rnA
IOS§
Vee - MAX
-100
rnA
ICC
-40
I
I
Vee = MAX
-100
-40
Outputs high
7
13
7
13
Outputs low
9
16
9
16
14
25
14
25
I Outputs disabled
U)
/lA
Q)
(.)
-S
Q)
C
..J
lI-
rnA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at
Vee
=:
5 V, T A
=:
25°C.
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
switching characteristics, Vee
PARAMETER
= 5 V. TA = 25°e (see note 2)
TEST CONDITIONS
SN54S134
MIN
SN74S134
TVP
MAX
6
MIN
TVP
MAX
4
6
UNIT
tpLH
RL - 280 n,
eL -15pF
4
tpLH
RL=280n,
eL = 50pF
5.5
tPHL
RL-280n,
eL -15pF
7.5
RL = 280 n,
eL - 50 pF
5
7
7.5
tpHL
5
7
ns
ns
RL = 280 n,
eL = 50pF
13
19.5
13
19.5
ns
14
21
14
21
ns
RL = 280 n,
eL = 5 pF
5.5
8.5
5.5
8.5
ns
9
14
9
14
ns
tpZH
tpZL
tpHZ
tpLZ
ns
ns
5.5
NOTE 2: load circuits and voltage waveforms are shown in Section 1.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 6SS012 • DALLAS, TEXAS 75265
2-413
2-414
SN54S135, SN74S135
QUADRUPLE EXCLUSIVE-OR/NOR GATES
DECEMBER 1972 - REVISED MARCH 1988
•
Fully Compatible with Most TTL and
TTL MSI Circuits
•
Fully Schottky Clamping Reduces
Delay Times ... 8 ns Typical
•
SN54S135 ... J OR W PACKAGE
SN74S135 ... 0 OR N PACKAGE
ITOPVIEW)
1A
1B
1Y
1C,2C
2A
2B
2Y
Can Operate as Exclusive-OR Gate (C Input
Low) or as Exclusive-NOR Gate (C Input High)
FUNCTION TABLE
OUTPUT
INPUTS
A
B
C
Y
L
L
L
L
VCC
4B
4A
4Y
3C,4C
3B
3A
3Y
GND
L
H
L
H
H
L
L
H
SN54S135 ... FK PACKAGE
H
H
L
L
ITOP VIEW)
L
L
H
H
L
H
H
L
H
L
H
L
H
H
H
H
H == high level. l
='
u
~ ~ ~ ~~
3
lY
lC,2C
low level
logic diagram lone half)
NC
6
2A
7
IA
2 1 2019
4
5
8
9 10 11 1213
IV
18
>cu>OU><
NZZI')I')
1A~_
'B~lY
c:l
NC - No internal connection
2A~_2Y
2B~
3A----\r""\. .
3B~3Y
4A~_.
4B~4Y
positive logic
Y=A(±)B=A'B+A'B
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
OF '136
""~":~
INPUT
TYPICAL OF ALL OUTPUTS
OF '136
EQUIVALENT OF EACH INPUT
OF'LS136
TYPICAL OF ALL OUTPUTS
OF'LS136
vee
12.5 kH NOM
__ ~O"'M
... - -
INPUT
...
--
U'
_~O"""'
~~
,
~
Resistor vatu. shown are nominal.
PRODUCTION DATA docu.....ts contai. i.I.,lIIIIi••
current u .f pablicatian date. Praduet. cDnform to
specificltionl per the terms of TIXII Instraments
=~i~·r::I~7; ~~:~i:; 1Ir:::::~ .ot
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·417
SN54LS13l SN74LS136
QUADRUPLE 2·INPUT EXCLUSIVE·OR GATES
WITHOPEN·COLLECTOR OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage
.
.
.
.
.
.
.
7V
.
5.5 V
-55"e to 125°C
Operating free·air temperature range: SN54136
oOe to 7o"e
SN74136
Storage temperature range
NOTE 1:
-65"e to 150"e
Voltage values are with respect to network ground terminal
recommended operating conditions
SN54136
Supply voltage, Vee
High-level input voltage, V,H
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
O.B
O.B
High·level output voltage, VOH
5.5
5.5
V
16
16
mA
70
°e
-55
125
0
V
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted I
rC
V
Low-level input voltage, V,L
Operating free-air temperature, T A
~
UNIT
V
2
Low-level output current, tOl
~
SN74136
MIN
CD
TVP*
SN74136
MAX
MIN
MAX
TVP*
-1.5
-1.5
UNIT
~
MIN,
Vee
~
MIN,
" ~ -B mA
V,H ~ 2 V, V,L
Vee
~
MIN,
V,H
~
2 V,
V,L
Vee
~
MIN,
VIH
~
2 V,
V,L
Vee
~
MAX,
V,
~
I'H
I,L
Vee
~
MAX,
V,
~
2.4 V
40
40
~A
Vee
~
MAX,
V,
~
0.4 V
-1.6
-1.6
rnA
ICC
Vee
~
MAX,
See Note 2
50
mA
V,K
CD
IOH
C/)
MIN
Vee
S.
()
SN54136
TEST eONDITloNst
PARAMETER
VOL
"
~
O.B V,
VOH
~
0.7 V,
VOH
~
O.B V,
IOL
~
~
~
0.25
5.5 V
0.25
5.5 V
0.2
16 rnA
5.5 V
0.4
0.2
0.4
1
30
1
43
30
V
mA
V
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee := 5 V, TA = 25°C.
NOTE 2: ICC is measured with one input of each gate at 4.5 V. the other inputs grounded. and the outputs,open.
switching characteristics. VCC
PARAMETER'
tPLH
=
5 V, T A = 25"C
FROM
TEST CONDITIONS
IINPUT)
Other Input low
A or B
tPHL
tPLH
tpHL
A or B
Other Input high
tpLH propagation delay time, low-to-high-Ievel output
tpLH propagation delay time, high-to-Iow-Ievel output
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
2-418
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
CLo15pF,
RL ~ 400 l!,
See Note 3
MIN
TVP
MAX UNIT
12
18
39
14
42
50
22
55
ns
ns
SN54136, SN74136
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
WITH OPEN-COLLECTOR OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Operating free·air temperature range: SN54LS136
SN74LS136
Storage temperature range
7V
7V
_55°C to 125°C
oOe to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN74LS136
SN54LS136
MIN
4.5
Supply voltage, Vee
NOM
MAX
MIN
5.5
4.75
5
High-level output voltage, VOH
-55
5
MAX
5.25
UNIT
V
5.5
5.5
4
8
rnA
70
"e
Low-level output current, tOl
Operating free-air temperature, T A
NOM
125
0
V
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
VIH
SN54LS136
TEST eONDITIONst
MIN
Low-level input voltage
VIK
Input clamp voltage
IOH
High-level output current
VOL Low-level output voltage
SN74LS136
MAX
Vee - MIN,
11--18mA
Vee = MIN,
VIH = 2V,
MIN
TYPj:
MAX
UNIT
0.7
0.8
V
-1.5
-1.5
V
100
100
CJ
-S
Q)
p.A
C
V
lI-
VIL = VIL max. VOH = 5.5 V
Vee= MIN,
iloL = 4 mA
VIH=2V,
VIL=VILmaxI I OL=8mA
CI)
Q)
V
2
2
High-level input voltage
VIL
TVPj:
...J
0.25
0.4
0.25
0.4
0.35
0.5
mA
II
Input current at maximum input voltage
Vee = MAX,
VI = 7 V
0.2
0.2
IIH
High-level input current
Vee= MAX,
VI=2.7V
40
40
p.A
IlL
Low-level input current
Vee - MAX,
VI-0.4V
-0.8
-0.8
mA
ICC
SupplV current
Vee - MAX,
See Note 2
10
rnA
6.1
6.1
10
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at Vee'" 5 V, TAO: 25"e.
NOTE 2: lec is measured with one input of each gate at 4.5 V, the other inputs grounded, and the outputs open.
switching characteristics, Vee: 5 V, T A : 25° C
PARAMETER II
tpLH
FROM
TEST eONOITIONS
!INPUT)
A or B
Other input low
tpHL
tpLH
CL=15pF,
RL=2k!!,
AorB
Other input high
tpHL
(See Note 3)
MIN
TYP
MAX UNIT
18
30
18
30
18
30
18
30
ns
ns
'tPLH propagation delay time, low-to-high-Ievel output
tpLH propagation delay time. high-to-Iow-Ievel output
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-419
-I
-I
rC
(I)
~.
(")
(I)
CIJ
2-420
SN54LS137, SN74LS137
3·L1NE TO a·L1NE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
02416, JUNE· 1978 - REVISED MARCH 1988
SN54LS137 . , . J OR W PACKAGE
SN74LS137 ... 0 OR N PACKAGE
(TOP VIEW)
• Combines Decoder and 3·Bit Address Latch
• Incorporates 2 Enable Inputs to Simplify
Cascading
A
B
C
GL
G2
Gl
• Low Power Dissipation ... 65 mW Typ
description
The 'LS137 is a three-line to eight-line
decoder/demultiplexer with latches on the three address inputs. When the latch-enable input (GL) is low,
the 'LS 137 acts as a decoder/demultiplexer. When GL
goes from low to high, the address present at the select
inputs (A, B, and C) is stored in the latches. Further address changes are ignored as long as GL remains high.
The output enable controls, Gl and G2, control the
state of the outputs independently of the select or latchenable inp~ts. All of the outputs are high unless Gl is
high and G2 is low. The 'LS137 is ideally suited for
implementing glitch-free decoders in strobed (storedaddress) applications in bus-oriented systems.
VCC
YO
Yl
Y2
Y3
Y4
Y5
Y6
Y7
GND
SN54LS137 . , .FK PACKAGE
(TOP VIEW)
In <{
3
u
u uo
z>>1 2019
Yl
Y2
NC
Y3
Y4
C
GL
NC
G2
Gl
en
Q)
o
'S
Q)
9 10 111213
..... au
C
...J
>- ZZ >- >(!)
lI-
NC - No internal connection
schematics of inputs and outputs
EQUIVALENT OF EACH
ENABLE INPUT
Vce
---->3
2
1 20 19
e
G2A
If)
Ne
Q)
CJ
G2B
G1
'S
Q)
9 1011
C
!'outC\.!)
>-Zz>->-
...J
C!l
lI-
NC - No internal connection
logic symbols t
BIN/OCT
A (11
B (21
All of these decoder/demultiplexers feature fully
buffered inputs, each of which represents only
one normalized load to its driving circuit. All
inputs are clamped with high-performance
Schottky diodes to suppress line-ringing and to
simplify system design.
c
(31
Gl
(61
G2A (41
&
EN
G2B (51
V7
OR
The SN54LS138 and SN54S138 are
characterized for operation over the full military
temperature range of - 55°C to 125 DC. The
SN74LS138 and SN74S138A are characterized
for operation from ODC to 70 o
DMUX
A (11
B (21
c
e.
(31
:}Gt
tThese symbols are in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
PRODUCTION DATA do.ument. contain information
currant I. at publicatian date. Products conform to
.pacifications par the terms of T8.0 Instrumants
==:~~i~.t::I~~i ~:~::i:: lJ~O=::::t::.s not
Copyright @ 1972, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAL.LAS. TEXAS 75265
2-425
SN54LS13~ SN54S13~
SN74LS13B, SN74S13BA
3·LlNE· TO B·LlNE DECODERS/DEMULTIPLEXERS
logic diagram and function table
'lS138, SNB4S138, SN74S138A
Y1
Y2
Y3
Y4
":'::::';':-i.::>O-~I-
Q)
SN74S138A
TEST CONDITIONSt
II)
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vee = 5 V, TA = 25°e.
§ Not more than one output should be shorted at a time, and duration of the short circuit test should not exceed one second.
*
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-429
SN54S138, SN74S138A
3·LlNE TO 8·LlNE DECODERS/DEMULTIPLEXERS
switching characteristics,
PARAMETERt
FROM
IINPUT)
Vee
Binary
tPLH
tpHL
Select
LEVELS
IOUTPUT)
OF DELAY
tpLH
3
tpHL
RL
~
280O,
CL
See Note 2
~
15 pF,
TVP
Any
3
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
MAX
4.5
7
ns
7
10.5
ns
7.5
12
ns
8
12
ns
5
8
11
11
11
ns
7
7
7
t tpLH ~ propagation delay time, low-to-high-Ievel output
tPHL = propagation delay time. high·to-Iow-Ievel output
2-430
SN74S138A
MIN
Any
2
Enable
TEST CONOITIONS
2
tPLH
tpHL
SN54S138
TO
tpLH
tPHL
5 V, TA
ns
ns
ns
SN54LS139A, SN54S139, SN74LS139A, SN74S139A
DUAL 2-LlNE TO 4-LlNE DECODERS/DEMULTIPLEXERS
DECEMBER 1972-REVISED MARCH 19BB
•
•
•
SN54LS139A. SN54S139 ... J OR W PACKAGE
SN74LS139A. SN74S139A ... 0 OR N PACKAGE
Designed Specifically for High-Speed:
Memory Decoders
Data Transmission Systems
ITOP VIEW)
Vee
1G
fA
18
1YO
1Y1
1Y2
1Y3
Two Fully Independent 2- to 4-line
Decoders/Demultiplexers
Schottky Clamped for High Performance
description
These Schottky-clamped TTL MSI circuits are
designed to be used in high-performance
memory-decoding or data-routing applications
requiring very short propagation delay times. In
high-performance memory systems, these
decoders can be used to minimize the effects of
system decoding. When employed with highspeed memories utilizing a fast-enable circuit,
the delay times of these decoders and the enable
time of the memory are usually less than the
typical access time of the memory. This means
thatthe effective system delay introduced by the
Schottky-clamped system decoder is negligible.
2G
2A
28
2YO
2Y1
2Y2
2Y3
GND
SN54LS 139A. SN54S 139 ... FK PACKAGE
(TOP VIEW)
U
«~~Z>N
It? U Ult?
3
2
1 20 19
CI)
Q)
(J
'S;
Q)
The circuit comprises two individual two-line to
four-line decoders in a single package. The
active-low enable input can be used as a data
line in demultiplexing applications.
9 1011 1213
C
MOUMN
...I
>-zz>->~t?
NN
lI-
NC - No internal connection
All of these decoders/demultiplexers feature fully
buffered inputs, each of which represents only
one normalized load to its driving circuit. All
inputs are clamped with high-performance
Schottky diodes to suppress line-ringing and to
simplify system design. The SN54LS 139A and
SN54S 139 are characterized for operation range
of -55°C to 125°C. The SN74LS139A and
SN74S139A are characterized for operation
from O°C to 70°C.
logic symbols (alternatives) t
X/V
1A 121
141 1V0
1B 131
(5) lYl
6} 1Y2
171 1Y3
1121 2VO
1111 2V1
1101 2V2
191
2va
FUNCTION TABLE
INPUTS
ENABLE
-G
H
OUTPUTS
SELECT
DMUX
11>. 121
O} 0
141 1YO
,V,
B
A
YO
Y1
Y2
Y3
H
X
X
H
H
H
H
L
l
l
H
H
l
H
171 1Y3
l
l
H
H
l
H
H
1121 2VO
l
H
l
H
H
l
H
1111 2V1
l
H
H
H
H
H
l
1101 2V2
= high
1
G3
151
161 W2
191 2V3
level, L = low level, X = irrelevant
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984
and lEe Publication 617-12.
Pin numbers shown are for D, J, N. and W packages.
PRODUCTION DATA documant. contoin information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
=::~~~i~ai~:1~1e ~~:~::ti:; :'~O::::::::t::'s~ not
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1972, Texas Instruments Incorporated
2-431
SN54LS139A, SN54S139, SN74LS139A, SN74S139A
DUAL 2-LlNE TO 4-LlNE DECODERS/DEMULTIPLEXERS
logic diagram (positive logic)
lYO
lYl
lY2
SELECT{lA
INPUTS
lB ..!.::!~~>-~:D-""--'-.J
lY3
2YO
ENABLE 26
..:.:..;::.qP1f==;::~~:J
DATA
OUTPUTS
2Yl
2Y2
SELECT PA
INPUTS l : B
"':":';~I>:>-"'::D_""--L..J
2Y3
Pin numbers shown are for D, J, N, and W packages.
schematics of inputs and outputs
-I
-I
r-
EQUIVALENT OF EACH
INPUT OF 54S139, 74S139A
C
VCC--.....- -
CD
(II
INPUT
TYPICAL OF OUTPUTS
OF 54S139, 74S139A
VCC
VCC--.....- 20 kll NOM
<
n'
CD
TYPICAL OF OUTPUTS
OF'LS139A
EQUIVALENT OF EACH
INPUT OF 'LS139A
120 II NOM
VCC
50 II NOM
INPUT .....f+.....-~
OUTPUT
OUTPUT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (See Note 1) . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: 'LS 139A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
54S139, 74S139A ..................................................... 5.5 V
Operating free-air temperature range: SN54LS139A, SN54S139. . . . . . . . . . . . . . . . . . . . .. - 55°e to 125°e
SN74LS139A, SN74S139A ....................... 0° e to 70 0 e
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 °e to 150 0 e
NOTE 1: Voltage values are with respect to network ground terminal.
2-432
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS139A, SN74LS139A
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
recommended operating conditions
SN54LS139A
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low·level input voltage
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
SN74LS139A
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.7
0.8
-0.4
-0.4
mA
8
mA
70
°e
4
- 55
UNIT
125
a
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
. noted)
VIK
VOH
VOL
II
IIH
IlL
IOS§
lee
SN54LS139A
TVpf
MAX
TEST CONDITIONS t
PARAMETER
=
MIN
-1.5
Vee - MIN,
II
= MIN,
IOH = -0.4 mA
Vee = MIN,
VIL = MAX
Vee = MAX,
Vee = MAX,
Vee = MAX,
Vee = MAX
Vee = MAX,
VIH
=
2 V,
VIL
VIH
=
2 V,
IloL
Vee
-18 mA
IloL
VI
VI
VI
=
=
=
SN74LS139A
TVpf
MAX
MIN
= MAX,
=4
=8
2.5
3.4
0.25
mA
-1.5
2.7
0.4
3.4
0.4
0.35
7 V
2.7 V
0.4 V
-20
6.8
0.5
V
(I)
0.1
0.1
mA
20
-0.4
20
~A
-100
Outputs enabled and open
V.
V
0.25
mA
UNIT
-20
11
-0.4
mA
-100
rnA
11
rnA
6.8
Q)
.s:U
Q)
o
...I
lI-
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vee = 5 V, TA = 25°e.
*
§ Not more than one output should be shorted at a time, and duration of the short circuit test should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25°e (see Note 2)
PARAMETER'
FROM
(INPUT)
TO
LEVELS
(OUTPUT)
OF DELAV
tpLH
tpHL
Binary
tpLH
Select
tPHL
tpLH
tpHL
Enable
TEST CONDITIONS
MIN
2
Any
3
Any
SN54LS139A
SN74LS139A
RL
=
2 kO,
CL
2
=
15 pF
TVP
UNIT
MAX
13
20
ns
22
33
ns
ns
18
29
25
38
ns
16
24
n.
21
32
ns
~ tpLH
= propagation delay time, low-to-high-Ievel output
tpHL = propagation delay time, high-to-Iow-Ievel output
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-433
SN54S139, SN74S1.39A
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLIERS
recommended operating conditions
SN54S139
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low~level
IOH
High-level output current
IOL
TA
Operating free-air temperature
SN74S139A
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
2
input voltage
Low-level output current
V
V
0.8
0.8
V
-1
-1
mA
20
70
mA
20
-55
UNIT
125
0
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
SN54S139
PARAMETER
•
VIK
VOH
VOL
II
IIH
IlL
IOS§
lee
TEST CONDITIONSt
= MIN,
= MIN,
IOH = -1 mA
Vee = MIN,
IOL = 20 mA
Vee = MAX,
Vee = MAX,
Vee = MAX,
Vee = MAX
Vec = MAX,
=
Vee
II
Vee
VIH
VIH
VI
VI
VI
SN74S139A
MIN
TYP*
2.5
3.4
2.7
3.4
-1.2
-18 mA
=
=
2 V,
2 V,
= 5.5
= 2.7
= 0.5
UNIT
MAX
VIL
VIL
= 0.8
= 0.8
I SN54S'
I SN74S'
V,
V
V
V,
0.5
V
V
1
mA
V
50
-2
mA
-100
mA
90
mA
V
-40
Outputs enabled and open
60
pA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
= 5 V, T A = 25°e.
*All typical values are at Vee
§ Not
more than one output should be shorted at a time, and duration of the short circuit test should not exceed one second.
switching characteristics. Vee - 5 V. TA - 25°e (see Note 2)
PARAMETER1
FROM
(INPUT)
TO
(OUTPUT)
tpLH
tpHL
Binary
tPLH
Select
tPHL
tpLH
Enable
LEVELS
TEST CONDITIONS
OF DELAY
MIN
2
Any
3
Any
RL = 28011,
CL = 15 pF
2
tPHL
, tPLH = propagation delay time, low-to-high-Ievel output
tpHL = propagation delay time, high-to-Iow-Ievel output
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2-434
SN54S139
SN74S139A
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75266
UNIT
TYP
MAX
5
7.5
ns
6.5
10
ns
7
12
ns
8
12
ns
5
8
ns
6.5
10
ns
SN54S140, SN74S140
DUAL 4-INPUT POSITIVE-NAND 50-OHM LINE DRIVERS
DECEMBER 19B3-REVISED MARCH 198B
•
Package Options Include Ceramic Chip
Carriers and Flat Packages in Addition to
Plastic and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
SN54S140 ... J OR W PACKAGE
SN74S140 ... 0 OR N PACKAGE
(TOP VIEW)
VCC
20
2C
NC
28
2A
2Y
18
NC
lC
10
description
These devices contain two independent 4-input
positive-NAND 50-ohm line drivers. They
perform the Boolean function Y = ABCD.
GNO
SN54S140 ... FK PACKAGE
(TOP VIEW)
The SN54S 140 is characterized for operation
over the full military temperature range of
-55°C to 125°C. The SN74S140 is
characterized for operation from OoC to 70°C.
3
logic diagram leach driver)
lA§J2A§J18
lC
10
28
2
1 20 19
5
NC
NC
6
IV
8
9 10111213
)-oU)-
(2)
IV
(4)
(5)
(9)
(10)
2V
(12)
(13)
tThis svmbol is in accordance with ANSI/IEEE Std. 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for D, J. N. and W packages.
PRODUCTION DATA documents contain information
current as of publicatioo date. Products conform to
specifications per the terms of Taxas Instruments
:~~~~:~~i~ar::,~1i ~:::~ti:; lIID::~:~:t:~~s
not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-435
SN54S140. SN74S140
DUAL 4-INPUT POSITIVE-NAND 50-OHM LINE DRIVERS
schematic (each driver)
r----------.------------~-vcc
1.4 kll
25 !!
380 II
A
B
OUTPUT
Y
........
0---+--1-+....
C---+~
-.....-. .-
-I
-I
r-
....-GND
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
C
CD
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage ............................................................................ 5.5 V
Operating free-air temperature range: SN54' ........................................... - 55°C to 125°C
SN74' ............................................... aOe to 7aoe
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 15aoe
~n
CD
(I)
NOTE 1: Voltage values are·with respect to network ground terminal.
2-436
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54S140, SN74S140
DUAL 4-INPUT POSITIVE-NAND 50-OHM LINE DRIVERS
recommended operating conditions
SN54S140
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
SN74S140
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
IOL
Low-level output current
TA
Operating free-air temperature
2
0.8
-40
-40
60
125
V
V
0.8
- 55
UNIT
0
V
mA
60
mA
70
"C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH
VCC~
MIN,
TYP*
2.5
3,4
~
0.8 V,
10H =-3 mA
VCC~
VIL
~
0,5 V,
RO
VIH-2V,
II
VCC- MAX,
VI - 5,5 V
SN74S140
MAX
MIN
TYP* MAX
-1,2
VIL
MIN,
MIN
~-18mA
II
VCC~MIN,
VCC - MIN,
VOL
SN54S140
TEST CONDITIONSt
~
50 n to GND
-1.2
2.7
2
3.4
V
V
2
IOL~60mA
UNIT
V
0.5
0.5
1
1
mA
IIH
VCC- MAX,
VIH~2.7V
0.1
0.1
mA
IlL
VCC~
MAX,
VIL~0.5V
-4
-4
mA
10S§
VCC~
MAX
- 225
mA
ICCH
VCC= MAX,
VI
ICCL
VCC~
VI=4.5V
MAX,
-50
-225
~OV
t For conditions shown as MIN or MAX, use the appropriate
t All typical valussareat Vee = 5 V, TA = 25°C.
-50
10
18
10
18
mA
25
44
25
44
mA
value specified under recommended operating conditions.
PARAMETER
tPLH
to)
Q)
C
...J
= 5 V, TA = 25°e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
Any
Y
tPLH
tPHL
Q)
oS;
lI-
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed 100 milliseconds.
switching characteristics, Vee
en
TEST CONDITIONS
MIN
RL
~93n,
CL
~
50 pF
RL
~
CL
~
150pF
93 n,
tPHL
TYP
MAX
UNIT
4
6.5
ns
4
6.5
ns
6
ns
6
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-437
2-438
SN74143
4-81T COUNTER/LATCH, SEVEN·SEGMENT LED/LAMP DRIVER
NOVEMBER 1971-REVISED MARCH 1988
•
N PACKAGE
15-mA Constant· Current Outputs
(TOP VIEWI
For Driving Common· Anode LEDs such as
TIL302 or TIL303 Without Series Resistors
•
SCEI
ClK
ClR
RBI
Universal Logic Capabilities
Ripple Blanking of Extraneous Zeros
Latch Outputs Can Drive Logic Processors
Simultaneously
STRB
aD
BI
BI/RBO
DP
dp
d
Decimal Point Driver Is Included
•
VCC
PECI
MAX
Synchronous BCD Counter Capability
OC
OB
QA
b
a
Cascadable to N-Bits
Look-Ahead-Enable Techniques Minimize
Speed Degradation When Cascaded for
Large-Word Display
e
c
GND
g
Direct Clear Input
logic symbol f
en
Q)
lii/RBo
(61
(5)
(4)
(21)
.r--.
;;>1
l.....:: ~
...
.....
14
15
;;>1
16
&
J
{13
,
,
,
,
CTROIV10
(3)
.....
R
(23)
Vl1
(1)
(21
ClK
VII
L.r::..
G12
11+
17
130
Z14 1
130
Z15 2
130
Z16 4
CT-01;.,;
G18
BC6nSTG
.18 $2
C>
b18$2
[T31
c18 $2
.18$2
118$2
g18$2
Z17 8
,12CT=9
OP
(7)
'SQ)
QA
QB
(19)
Qc
(20)
Qo
(18)
C
.-....J
r
d18$2
130
CJ
(17)
C>
18$2
(15)
(16)
(14)
b
19)
(111
(101
(131
(221
(8)
MAX
dp
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
description
This TTL MSI circuit contains the equivalent of B6 gates on a single chip. logic inputs and outputs are completely
TTL compatible. The buffered inputs are implemented with relatively large resistors in series with the bases of the
input transistors to lower drive-current requirements to one-half of that required for a standard Series 54174 TTL input.
The serial-count-enable, actually two internal emitters, is rated as one standard Series 54174 load. The logic outputs,
except RBO, have active pull-ups.
The SN74143 driver output is designed specifically to maintain a relatively constant on-level sink current of approximately
15 milliamperes from output "a" through "g" and seven milliamperes from output "dp" over a voltage range from
one to five volts. Any number of lED's in series may be driven as long as the output voltage rating is not exceeded.
All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. Maximum clock
frequency is typically 1 B megahertz and power dissipation is typically 280 milliwatts. The SN74143 is characterized
for operation from a °c to 70 °C.
PRODUCTION DATA document. contain inlormation
currant as of publication date. Products conform to
spacificatiaRs par the tarms of Taxas Instrumants
=:~:~~i~~r::1~1i ~!~~~ti:; :'~O::::::::t:~~S
not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-439
SN74143
4·81T COUNTER/LATCH, SEVEN·SEGMENT LED/LAMP DRIVER
description (continued)
Functions of the inputs and outputs of these devices are as follows:
FUNCTION
CLEAR INPUT
PIN NO.
3
CLOCK INPUT
2
Each positive-going transition will increment the counter provided that the
circuit is in the normal counting mode (serial and parallel count enable
inputs low, clear input high).
PARALLEL COUNT
ENABLE INPUT (PCEI)
23
Must be low for normal counting mode. When high, counter will be
inhibited. Logic level must not be changed when the clock is low.
Must be low for normal counting mode, also must be low to enable
maximum count output to go low. When high, counter will be inhibited
and maximum count output will be driven high. Logic level must not be
changed when the clock is low.
SERIAL COUNT
ENABLE INPUT (SCEI)
-4
-4
r-
o
CD
<
Cr
CD
C/I
MAXIMUM COUNT
OUTPUT
22
Will go low when the counter is at 9 and serial count enable input is low.
Will return high when the counter changes to 0 and will remain high during
counts 1 through 8. Will remain high (inhibited) as long as serial count
enable input is high.
LATCH STROBE
INPUT
21
When low, data in latches follow the data in the counter. When high, the
data in the latches are held constant, and the counter may be operated
independently.
LA TCH OUTPUTS
(OA. OB, OC, 00)
17,18,19,20
The BCD data that drives the decoder :can be stored in the 4-bit latch and
is available at these outputs for driving other logic and/or processors. The
binary weights of the outputs are: OA = 1, OB = 2, Oc = 4, 00 = 8.
DECIMAL POINT
INPUT
7
Must be high to display decimal point. The decimal point is not displayed
when this input is low or when the display is blanked.
BLANKING INPUT
(BI)
5
When high, will blank (turn off) the entire display and force RBO low.
Must be low for normal display. May be pulsed to implement intensity
control of the display.
RIPPLE·BLANKING
INPUT (RBI)
4
When the data in the latches is BCD 0, a low input will blank the entire
display and force the RBO low. This input has no effect if the data in the
latches is other than O.
RIPPLE-BLANKING
OUTPUT (RBO)
6
Supplies ripple blanking information for the ripple blanking input of the
next decade. Provides a low if Bi is high, or if RBI is low and the data in
the latches in BCD 0; otherwise, this output is high. This pin has a resistive
pull-up circuit suitable for performing a wire-AND function with any
open-collector output. Whenever this pin is low the entire display will be
blanked; therefore, this pin may be used as an active-low blanking input.
LED/LAMP DRIVER
OUTPUTS
(a, b, c, d, e, f, g, dp)
15,16,14,9
11,10,13,8
Outputs for driving seven-segment LED's or lamps and their decimal
points. See segment identification and resultant displays on following
page.
SEGMENT
IDENTIFICATION
2-440
DESCRIPTION
When low, resets and holds counter at O. Must be high for normal
counting.
o
2
3
4
5
6
7
NUMERICAL DESIGNATIONS-RESULTANT DISPLAYS
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
8
9
SN74143
4-81T COUNTER/LATCH, SEVEN-SEGMENT LED/LAMP DRIVER
logic diagram (positive logic)
\
~
~
o __________
A
__________
J
~
I
~
::>
">::>
0.
"C
...I
«>->-
8~~
~rr=I:;;Z::>
~
o
~-----·Igg
"'z
en
Q)
0
(J)
>::>
">::>
a
u
a
CD
a
«
a
CJ
'S;
Q)
0
...J
II-
0
S1
"
0
...I
>Z
::>
0
u
x
«
:;;
...I
W
...I
::!:
...I
...I
«
'"w '"« u'"
'-,,-I 0
(J)
"-
...I
....
~(I)
U
ZeD>::>«::>
oz"uw~
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-441
SN74143
4-BITCOUNTER/LATCH, SEVEN-SEGMENT LED/LAMP DRIVER
schematics of inputs and outputs
EQUIVALENT OF
Iii/RBO
EQUIVALENT OF
EACH INPUT
EXCEPT Iii/FiBO
TYPICAL OF ALL
OUTPUTS EXCEPT iii/RBO
OUTPUT/INPUT
VCCC
Req I - INPUT
OUTPUT
--
20
L-~O-O-
seEI: Req
=<
n
_ _ _ _~ NOM
4 kf! NOM
Other
inputs: Req == 8
kn
NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Off-state current at outputs "a" thru "g" and "dp" ...................................... 250 /LA
Continuous total power dissipation at (or below) 70 DC free-air temperature (see Note 2) . . . . . . . . . . . .. 1.4 W
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 70 DC
Storage temperature range .................................................. -65 DC to 150 DC
-I
-I
rC
CD
<
5'
CD
o
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
MIN
NOM
MAX
UNIT
4.75
1
5
V
OA,OB,OC,OO
Maximum count
5.25
5
-240
-560
~
-120
Supply voltage, VCC
On-state voltage at outputs a thru g and dp 1'143 only)
High·level output current, 10H
Low·level output current, 10L
Clock pulse width, twlclock)
High logic level
Low logic level
Clear pulse width, tw(clearl
Setup time, tsu
25
55
25
Serial and parallel carry
30 t
Clear inactive state
60 t
0
Operating free· air temperature, T A
t The arrow indicates that the rising edge of the clock pulse is used for reference.
2-442
4.8
11.2
OA, 0B, 0C, OO,mm
Maximum count
TEXAS ",
INSTRUMENlS
POST OFFICE BOX 655012. DALLAS, TeXAS 75266
V
/LA
mA
ns
ns
n.
70
DC
SN74143
4-81T COUNTER/LATCH, SEVEN-SEGMENT LED/LAMP DRIVER
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt
PARAMETER
VIH
High-level input voltage
VIL
Low~level
VIK
Input clamp voltage
Vee = MIN, 11= -12 mA
QA, QB,Qe, QD
Maximum count
VOL
Low-level output voltage
VQlo!!)
VOlonl
QA QB, Qe, RBO
Vee = MIN, VIH = 2 V,
VIL = 0.8 V, 10H = MAX
Vee = MAX,IOH = 250 ~A
7
On-state output voltage
Outputs a thru g, dp
9
Outputs a thru g
Vee = MIN
Vee = MIN, Vo = 1 V
Vee = 5 V, Vo = 2 V
4.5
Output dp
Vee = MAX, Vo = 5 V
Vee = MIN, Vo = 1 V
Vee = 5 V, Vo = 2 V
RiiO
High-level input current
V
15
15
15
Vee = MAX,VI = 2.4 V
7
0.12
RiiO
Low-level input current
node
-1.5
See Note 3
Short-circuit
QA,QB,Qe,QD
output current
Maximum ·count
~A
mA
~A
-2.4
mA
-0.8
-9
,Vee = MAX
-27.5
-15
Vee = MAX, See Note 4
Supply current
ICC
mA
-1.6
Vee = MAX, VI = 0.4 V,
Other inputs
lOS
1
40
20
Serial carry
mA
12
-0.5
Other inputs
IlL
22
7
7
Vee = MAX, Vo = 5 V
Vee - MAX,VI - 5.5 V
node
V
V
Serial carry
IIH
V
0.4
VIL = 0.8 V, 10L = MAX
Outputs a thru g, dp
Input current at maximum input voltage
V
-1.5
V
Vee = MIN, VIH = 2 V,
Off-state output voltage
UNIT
0.8
2.4
Maximum count
On-state output current
II
MAX
V
input voltage
High-level output voltage
1010n)
Typf
2
R80
VOH
MIN
-55
56
93
mA
en
Q)
(,)
->
Q)
c
...I
lI-
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:j:
All typical values are at
NOTES: 3. IlL at
Vee =
'R'Im' node
5 V, TA
is tested with
=
25°C.
mgrounded and RBI at 4.5 V.
4. ICC is measured after the following conditions are established:
81 Strobe
= RBI =
DP
b)
Parallel count enable
c)
Clear (
= 4.5 V
=
serial count enable
=
m=
GND
) then clock until all outputs are on (
d) Outputs "a" through "g" and "dp" at 2.5 V, all other outputs open.
switching characteristics. Vee - 5 V, TA PARAMETER
25°e
FROM
TO
(INPUT)
IOUTPUT)
Serial look-ahead
Maximum count
Clock
Maximum count
TEST CONDITIONS
f max
tpLH
tpHL
tpLH
tpHL
tPLH
tpHL
Clock
QA,QB,Qe,QD
eL = 15 pF,
RL = 560 Il,
RL = 1.2 kll,
TEXAS ."
INSTRUMENTS
POST OFFICE
BO~
TYP
12
18
655012 • DALLAS. TEXAS 75265
MAX
UNIT
MHz
12
20
23
35
40
26
See Note 5
eL = 15 pF,
MIN
29
45
28
45
ns
ns
ns
2-443
Sa"!Ma l.LL
N
.;,.
.j:.
.j:.
II
.j::oen
'2
512 ....
..... .j::o
C')~
QW
c:
TYPICAL APPLICATION DATA
2
.....
m
This application demonstrates how the drivers may be cascaded for N-bit display applications. It features:
z
~
, "'" ""0"'
INPUT
re
itJ~
~~
z
MORE
w""
SIGNIFICANT
DIGIT
U14r
t
r<
III III !. IIIIII II
DllGi
abc d
STROBE
(>
f 9 dp
CK
abc d
STROBE
e f
T
II
4
LL U
MAX
SeEI
CLEAR
peEl
II LL
-
3:
m
2
.....
9 dp
CI<
r-
ow~'"
em
MAX
COUNT
-SCEI
C"i:EA"R
PCEi
0A 0B 0c 00 DP
QA 0B Qc DD DP
"I
H
C)
I ) I I I I I 1\
J
DECIMAL POINT { :
INPUTS
2
en
BLANK ING INPUT L
CLEAR INPUT
en
m
<
m
m
RBo
COUNT
81
OVERRIDING
:c
OIGIT
T
RBi
----<
;1:10
.....
C')
LEAST-SIGNIFICANT
LED/LAMP DRIVER OUTPUTS
MOST-SIGNIFICANT
RIPPLE BLANKINGINPUT
CLOCK INPUT
=
;;:
Synchronous, look-ahead counting
Ripple blanking of leading zeros; blanking of trailing zeros (not illustrated) can also be implemented
Overriding blanking for total suppression or intensity modulation of display
Direct parallel clear
Latch strobe permits counter to acquire next display while viewing current display
.
"
,
V
LATCH LOGIC OUTPUTS
tThe serial count-enable input of the least-significant digit is normally grounded; however, it may be used as a count-enable control for the
entire counter (high to disable, low to count) provided the logic level on this pin is not changed while the clock line is low or false counting
may result.
I
m
CI
;;:
;1:10
3:
-=
"'CI
CI
=
<:
m
=
FUNCTION TABLE
OUTPUTS
INPUTS
FUNCTION
CLOCK
PULSE
E'i:E"AR
LATCH
STROBE
RBi
Bi
DECIMAL
INPUT
SERIAL PARALLEL
RBI/RBO
CARRY
CARRY
MAXIMUM
LATCH
COUNT
DO Oc OB QA
OUTPUT
a
b
LED/LAMP DRIVERS
f
d
e
9
,
TYPICAL
NOTES
dp DISPLAY
Clear/Ripple Blank
L
L
L
X
X
X
X
L
H
L
L
L
L
OFF OFF OFF OFF OFF OFF OFF OFF
None
A. E
Blank
H
L
X
H
X
X
X
L
H
L
L
L
L
OFF OFF OFF OFF OFF OFF OFF OFF
None
A, D, E
0
H
L
H
L
H
L
L
H
H
L
L
L
L
1
H
L
H
L
L
L
L
H
H
L
L
L
H OFF ON
2
H
L
H
L
L
L
L
H
H
L
L
H
L
ON
ON OFF ON
3
H
L
H
L
L
L
L
H
H
L
L
H
H
ON
ON
Decimal
g
ON
ON
ON
ON
ON
ON OFF ON
ON OFF OFF OFF OFF OFF
ON
ON OFF ON OFF
ON OFF OFF ON OFF
4
H
L
H
L
L
L
L
H
H
L
H
L
L
OFF ON
ON OFF OFF ON
5
H
L
H
L
L
L
L
H
H
L
H
L
H
ON OFF ON
ON OFF ON
ON OFF
6
H
L
H
L
L
L
L
H
H
L
H
H
L
ON OFF ON
ON
ON OFF
ON
ON
ON OFF
7
H
L
H
L
L
L
L
H
H
L
H
H
H
ON
ON
ON OFF OFF OFF OFF OFF
8
H
L
H
L
L
L
L
H
H
H
L
L
L
ON
ON
ON
ON
ON
ON OFF
9
H
L
H
L
L
L
L
H
L
H
L
L
H
ON
ON
ON
ON OFF ON
ON OFF
0
H
L
H
L
L
L
L
H
H
L
L
L
L
ON
ON
ON
ON
1
H
L
H
L
L
L
L
H
H
L
L
L
H OFF ON
r-
2
H
L
H
L
L
L
L
H
H
L
L
H
L
ON
ON OFF ON
~i\; Ul4r
3
H
L
H
L
L
L
L
H
H
L
L
H
H
ON
ON
~-~ z
g: rJl
x
-l
~Al~
~~ c:~
~
I""l
~z
~
~
N
Latch
'"
~
Latch
Ripple Blank
ON
ON
ON OFF OFF
ON OFF OFF OFF OFF OFF
ON
ON OFF ON OFF
4
H
L
H
L
L
L
L
H
H
L
H
L
L
H
H
H
L
L
L
L
H
H
L
H
L
H
ON OFF ON
ON OFF ON
ON OFF
6
H
H
H
L
L
L
L
H
H
L
H
L
H
ON OFF ON
ON OFF ON
ON OFF
ON OFF OFF ON
ON OFF
7
H
H
H
L
L
L
L
H
H
L
H
L
H
ON OFF ON
ON OFF ON
ON OFF
8
H
L
H
L
L
L
L
H
H
H
L
L
L
ON
ON
ON
ON
ON
ON OFF
9
H
L
H
L
L
L
L
H
L
H
L
L
H
ON
ON
ON
ON OFF ON
ON OFF
0
H
L
L
X
L
L
L
L
H
L
L
L
L
B
,
B
~,
'-,,
,--,
,,-,
-,,
,=,,-,
,-,
-,
-' ,
,-,
,,
,--,
-,-,
ON OFF OFF ON OFF
5
OFF ON
,-,
,
,-'
.' ,,
ON
OFF OFF OFF OFF OFF OFF OFF OFF
'-,,
'--',-
,-,
-,,
,-,
,-,
'-',
None
--
NOTES:
A,
RBi/RsO
B
B
B
B
B
B
B
B. C
B
B
B
B
B
B
B. The blanking input (Si) must be low when functions DECIMALIO through 20/RIPPLE BLANK are desired,
C. The ripple·blanking input (RBi) must be open or high to display a zero during the decimal 0 input,
D, When a high logic level is applied directly to the blanking input (Si) all segment outputs are off regardless of any other input
condition.
dP.
.j>.
TTL Devices
n
CI
C
:2
-t
m
:=
r=
:a:-t
n
.:z:
en
m
<
m
:2
m
en
C)
B
A. B. E
-9,b
I'_,-:-,c
_
i!!!i:
m
:2
-t
r-
m
CI
r=
:a:-
3:
""CIen
CI:2
SEGMENT IDENTIFICATION
'"./:.
::::j
B
ripple·blanking output (RBO) goes to a low logic level (response condition),
U1
~
ta
B
----
is wire-AND logic serving as ripple blanking input (RBi) and/or ripple blanking output (ABO),
E, When the ripple·blanking input (RBI) and outputs QA through QD are at a low logic level, all segment outputs are off and the
B
:= ......
-~
<
m~
:=W
-I
-I
I
C
CD
<
(")
CD
C/J
2-446
SN54145, SN54LS145, SN74145, SN74lS145
BCD·lO·DECIMAL DECODERS/DRIVERS
MARCH 1974 - REVISED MARCH 1988
FOR USE AS LAMP, RELAY, OR MOS DRIVERS
•
Full Decoding of Input Logic
•
SN54145, SN74145, and SN74LS145 Have
aD-rnA Sink-Current Capability
SN54145, SN54LS145 .•. J OR W PACKAGE
SN74145 ... N PACKAGE
SN74LS145 ... 0 OR N PACKAGE
(TOP VIEWI
0
•
All Outputs Are Off for Invalid
BCD Input Conditions
•
Low Power Dissipation of 'LS145 ...
35 mW Typical
FUNCTION TABLE
INPUTS
NO.
0
C
B
0
L
L
L
1
L
L
L
2
L
L
H
OUTPUTS
0
1
2
L
L
H
H
H
H
L
H
L
H
H
L
A
4
5
6
H
H
H
H
H
H
H
H
H
H
H
H
3
7
8
9
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
H
5
L
H
L
H
H
H
H
H
H
L
H
H
H
H
6
7
8
9
L
H
H
L
H
H
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
2
3
H
L
L
L
H
H
H
H
H
H
H
H
L
H
NC
4
5
L
L
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
C
B
4
0
5
6
9
GND
7
8
u u
oZ>«
L
L
2
3
ITOPVIEWI
u
3
H
VCC
A
SN54LS145 ... FK PACKAGE
4
H
1
3
2
1 2019
o
9
0
H
L
H
H
H
H
H
H
H
H
H
H
H
H
9 10111213
::J
H
H
L
L
H
H
H
H
H
H
H
H
H
H
>
:!':
wou,......oo
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
«
II)
B
C
NC
ZZ
Q)
CJ
">
Q)
C
...I
lI-
(!l
NC
No internal connection
logic diagram
H = high level (off), L = low level (on)
description
These monolithic BCD-to-decimal decoder/drivers consist of eight inverters and ten four-input NAND gates.
The inverters are connected in pairs to make BCD input
data available for decoding by the NAND gates. Full
decoding of valid BCD input logic ensures that all outputs remain off for all invalid binary input conditions.
These decoders feature high-performance, n-p-n output
transistors designed for use as indicator/relay drivers or
as open-collector logic-circuit drivers. Each of the highbreakdown output transistors (15 volts) of the
SN54145, SN74145, or SN74LS145 will sink up to 80
milliamperes of current. Each input is one Series 54/74
or Series 54LS174LS standard load, respectively. Inputs
and outputs are entirely compatible for use with TIL or
DTL logic circuits, and the outputs are compatible for interfacing with most MOS integrated circuits. Power
dissipation is typically 215 milliwatts for the '145 and 35
milliwatts for the 'LS 145.
Pin numbers shown are for 0, J, N, and W packages.
PRODUCTION DATA documants co.tai. i.fomialio.
currant •• af puillication date. Products conform tD
spaclfic.,io.s par Iha lor... of Ta..s I.strumants
::=~i~·i~:1~7i ~::I~~I:: !Jlo;.":::~:'.~ .01
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-447
SN54LS145, SN74LS145
.BCD-TO-DECIMAL DECODERS/DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
Maximum current into any output (off·state)
Operating free·air temperature range: SN54145
SN74145
Storage temperature range
7V
5.5V
1 rnA
_55°C to 125°C
oOe to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN74145
SN54145
MIN
4.5
Supply voltage, Vee
Off·state output voltage, VO(of!)
NOM
MAX
MIN
5
5.5
4.75
NOM
5
15
Operating free-air temperature, T A
-55
125
0
MAX
5.25
UNIT
V
15
V
70
"e
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
TEST CONDITIONSt
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
IO(of!)
Off-state output current
MIN
TYP*
MAX UNIT
V
2
0.8
Vee = MIN,
11= -12 mA
Vee - MIN,
VIH = 2 V,
VIL = 0.8 V,
VO(of!) = 15 V
Vee = MIN,
VIH = 2 V,
VO(onl
On-state output voltage
II
Input current at maximum input voltage
Vee - MAX, VI-5.5V
0.5
110(onl = 80 mA
10(onl 20mA
VIL=0.8V
V
-1.5
V
250
itA
0.9
0.4
1
V
mA
IIH
High-level input current
Vee = MAX, VI-2.4V
40
itA
IlL
Low-level input current
Vee = MAX,
VI =0.4V
-1.6
mA
lee
Supply current
Vee = MAX. See Note 2
[SN54145
43
62
lSN74145
43
70
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:1:AII typical values are at
Vee
=
5 V, T A
= 25"C.
NOTE 2: ICC is measured with all inputs grounded and outputs open.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
tpLH
TEST CONDITIONS
Propagation delay time, low-to-high-Ievel output
I-'tP-'H"'L"--P=-r-o"'"p-ag'-a-t:-io-n-d:-e""la"'y-t""ime--'.-:h-:ig-:h:-.-to-.:-lo'-w-.I:-e-ve-:l-o-u-'tp'-u-t-l CL = 15 pF,
RL
= 100 n.
MIN
See Note 3
MAX
50
50
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
VCC _ _ _....._ _
OUTPUT
INPUT
2·448
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 6550'2 • DALLAS, TEXAS 75266
mA
SN54145, SN74145
BCD·TO·DECIMAL DECODERS/DRIVERS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage
Operating free·air temperature range: SN54LS145
SN74LS145
Storage temperature range
7V
7V
-55°C to 125°C
oOe to 70°C
_65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS145
MIN
Supply voltage, Vee
Off-state output voltage. VO(off)
4.5
SN74LS145
NOM
MAX
MIN
5
5.5
4.75
NOM
5
MAX
5.25
15
Operating free-air temperature, T A
-55
125
0
UNIT
V
15
V
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
Vil
Low-level input voltage
VIK
Input clamp voltage
1010ffi
Off-state output current
VOl on )
TEST eONOITIONSt
SN54LS145
TYPt
MIN
SN74LS145
MAX
2
On-state output voltage
Vee' MIN,
11--1SmA
Vee' MIN,
VIH' 2 V,
Vll' Vil max,
VOH' 15 V
Vee' MIN,
Llol' 12 mA
VIH' 2 V,
MIN
TYPt
MAX
UNIT
0.7
O.S
V
-1.5
-1.5
V
250
~A
250
OA
0.25
0.4
IIOl - 24mA
0.35
0.5
Vll' Vil max
pal -SOmA
2.3
3
0.25
II
Input current at maximum input voltage
Vee' MAX,
VI' 7 V
0.1
0.1
High-level input current
Vee' MAX,
VI' 2.7 V
20
20
~A
III
Low-level input current
Vee' MAX,
VI-OAV
-OA
-0.4
mA
lee
Su pply cu rren t
Vee- MAX,
See Note 2
13
mA
13
7
Q)
CJ
·S
Q)
o
..J
V
IIH
7
I/)
V
2
....
....
mA
~ For conditions shown as MIN or MAX, use t~e appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V. T A = 25 C.
NOTE 2: ICC is measured with all inputs grounded and outputs open.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-to-high-Ievel output
f-"P-'H'-'l-'----,P=-r-o'-pa-'g'-a""'ti-o-n-d'""e'""la-'-y-''"im-e-,"'"h"'"ig"'"h-.t-O-'.I":o'-w-'.I-ev-e"'"l-o-u-',p-u-,-I CL
MIN
See Note 3
= 45 pF.
MAX
50
50
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
schematic of inputs and outputs
EQUIVALENT OF EAeH INPUT
TYPICAL OF ALL OUTPUTS
vcc=q---
17 kn NOM
INPUT
--
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
2-449
2-450
SN54147, SN54148, SN54LS147, SN54LS148,
SN74147, SN74148 (TIM9907), SN74LS147, SN74LS148
10·L1NE TO 4·L1NE AND 8·L1NE TO 3·L1NE PRIORITY ENCODERS
OCTOBER 1976 - REVISED MARCH 1988
'147, 'LS147
SN54147. SN54LS147.
SN54148, SN54LS148 ... J OR W PACKAGE
SN74147, SN74148 ... N PACKAGE
SN74LS147, SN74LS148 . , . D OR N PACKAGE
{TOP VIEW)
'148, 'LS148
'147, 'LS147
• Encodes 10-Line Decimal to 4-Line BCD
• Applications Include:
Keyboard Encoding
Range Selection: '148, 'LS148
• Encodes B Data Lines to 3-Line Binary (Octal)
4
• Applications Include:
5
6
7
N-Bit Encoding
Code Converters and Generators
TYPE
TYPICAL
TYPICAL
DATA
POWER
DISSIPATION
DELAY
10 ns
10 ns
'147
'148
'LS147
'LS148
8
C
B
GND
3
2
7
EI
3
2
1
A2
9
A1
GND
A
GS
0
AO
SN54LS147, SN54LS148 ... FK PACKAGE
(TOP VIEW)
225mW
190mW
60mW
60mW
15 ns
15 ns
VCC
EO
D
4
5
6
VCC
NC
'LS148
'LS147
uu
Z>Z
'" ...
U
II)
Q)
(,)
U
U
"' ...
u uo
Z>w
oS;
3 2 1 2019
description
Q)
These TTL encoders feature priority decoding of the
inputs to ensure that only the highest-order data line
is encoded. The '147 and 'LS147 encode nine data
6
GS
7
3
NC
2
lines to four-line (8-4-2-1) BCD. The implied decimal
zero condition requires no input condition as zero is
0
...J
II-
9 10111213
encoded when all nine data lines are at a high logic
level. The '148 and 'LS148 encode eight data lines to
three-line 14-2-1) binary loctal). Cascading circuitry
(enable input EI and enable output EO) has been
provided to allow octal expansion without the need
for external circuitry. For all types, data inputs and
outputs are active at the low logic level. All inputs are
buffered to represent one normalized Series 54174 or
mou
zz
(!)
NC - No internal connection
54LS174LS load, respectively.
'147, 'LS147
FUNCTION TABLE
INPUTS
'148, 'LS148
FUNCTION TABLE
INPUTS
OUTPUTS
OUTPUTS
A2 A1 AO GS EO
1
2
3
4
5
6
7
8
9
D
C
B
A
EI
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
H
H
H
H
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
L
H
L
H
H
H
L
X
X
X
X
X
X
X
L
L
L
L
L
H
X
X
X
X
X
X
L
H
H
H
L
L
L
L
X
X
X
X
X
X
L
H
L
L
H
L
H
X
X
X
X
X
L
H
H
H
H
L
L
H
L
X
X
X
X
X
L
H
H
L
H
L
L
H
X
X
X
X
L
H
H
H
H
H
L
H
L
L
X
X
X
X
L
H
H
H
L
H
H
L
H
X
X
X
L
H
H
H
H
H
H
L
H
H
L
X
X
X
L
H
H
H
H
H
L
L
L
H
X
X
L
H
H
H
H
H
H
H
H
L
L
L
X
X
L
H
H
H
H
H
H
L
H
L
H
X
L
H
H
H
H
H
H
H
H
H
L
H
L
X
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H '" high logic level, L
= low
1
2
3
4
5
6
7
H
logic level, X = irrelevant
PRODUCTION DATA d••ume.1s .0.lai. i.formatio.
currant as of publication data. Products conform to
specifications par the terms of TaXI. Instruments
:~=:~~i~.i~:I~~e
0
=::i:; :.. .::~:::::t::S~1
not
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-451
SN54147, SN54148, SN54LS147. SN54LS148,
SN74147, SN74148 (TIM9907), SN74LS147, SN74LS148
10·lINE TO 4·LlNE AND 8·LlNE TO 3·LlNE PRIORITY ENCODERS
logic symbols t
'147, 'LS147
'148, 'LSl48
HPRI/BCD
HPRI/BIN
0
(101
(111
2
3
4
5
6
(121
(13)
(1)
(2)
(3)
(4)
0/Z10
10
1/Z11
11
2/Z12
12
3/Z13
13
4/Z14
14
5/Z15
15
6/Z16
16
7/Z17
17
V18
--I
-I
r-
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for Of J, N, and W packages.
EI
(5)
EN"
logic diagrams
'147, 'LS147
'148, 'LSl48
o
(10)
1 (11)
2 (12)
3
(13)
4
(1)
5
(2)
6
(3)
(4)
EI
(5)
Pin numbers shown are for D, J, N, and W packages.
2-452
TEXAS .."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
;'1
18
(15) EO
SN54147, SN54148, SN54LS147, SN54LS148,
SN74147, SN74148 (TIM9907), SN74LS147, SN74LS148
to·L1NE TO 4-L1NE AND 8·L1NE TO 3-L1NE PRIORITY ENCODERS
schematics of inputs and outputs
'147, '148
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
Vee---........- - -
- - - < t - - - Vee
INPUT
OUTPUT
o input
('148):
Req '" 2 kH NOM
All other inputs: Req "" 4 kU NOM
'LS147, 'LS148
EQUIVALENT OF ALL INPUTS
TYPICAL OF ALL OUTPUTS
til
Vee
CP
CJ
- - - - -...- - Vee
oS;
Req
CP
INPUT
u
C
"'"
...J
'-"M'+--- OUTPUT
lI-
,
~
~~
Ii
'LS148 inputs 1 thru 7: Req
= 9 kO
NOM
All other inputs: Req "" 18 kfl NOM
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
_ 7V
Supply voltage, VCC (see Note 1)
Input voltage: '147, '148
'LS147, 'LS148
I nteremitter voltage: '148 only (see Note 2)
Operating free-air temperature range: SN54', SN54LS Circuits
SN74', SN74LS Circuits
Storage temperature range
NOTES:
5_5 V
_7V
5.5 V
_55°C to 125°C
O°C to 70°C
_65°C to 150°C
1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For "48 circuits, this rating applies between any two of
the eight data lines, 0 through 7.
recommended operating conditions
MIN
Supply voltage,
Vee
4.5
High-level output current, IOH
5
MAX
MIN
5.5
4.75
SN74'
NOM MAX
MIN
5.25
4.5
5
-800
-800
16
Low-level output current, tOL
Operating free-air temperature, T A
SN54'
NOM
55
125
TEXAS
70
MIN
NOM
MAX
5.5
4.75
5
5.25
V
-400
I'A
8
mA
70
°e
5
-400
16
0
SN74LS'
SN54LS'
NOM
MAX
4
55
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
125
0
UNIT
2-453
SN54147, SN54148, SN74147, SN74148 (TIM9907)
10-LlNE TO 4-LlNE AND 8-LlNE TO 3-LlNE PRIORITY ENCODERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
'148
'147
TEST CONDITIONst
PARAMETER
V,H
High~level
V,L
V,K
Low-level input voltage
Input clamp voltage
VOH
High-level output voltage
VOL
input voltage
2
VCC=MIN,
I, = -12mA
VCC=MIN,
V'H=2V,
10H = -800~A
V'L=0.8V,
VCC= MIN,
Low-level output voltage
Input current at maximum input voltage
"
IIH
MIN TYPt MAX MIN TYPt MAX
o input
High-level input current
Any input except 0
o input
',L
Low-level input current
lOS
Short-circuit ou~put current
ICC
Supply current
V,L = 0.8 V,
10L = 16mA
VCC=MAX,
V, - 5.5 V
VCC = MAX,
V, = 2.4 V
VCC= MAX,
Any input except 0
*
2.4
V,H = 2 V,
2
VCC= MAX
V
0.8
0.8
V
-1.5
-1.5
V
3.3
2.4
0.2
0.4
3.3
0.2
V
0.4
1
1
40
80
40
-1.6
V, = 0.4 V
UNIT
-1.6
-85
-35
~A
mA
-85
rnA
VCC - MAX, ICondition 1
50
70
40
60
rnA
1Condition 2
42
62
35
55
rnA
See Note 3
-35
-3.2
V
mA
NOTE 3: For '147, ICC (condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (condition 2) is measured With
-I
-I
all inputs and outputs open. For '148, ICC (condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open;
ICC (condition 2) is measured with all inputs and outputs open.
r-
tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
C
tAil typical values are at Vee'" s V, T A '" 2S"C.
~ Not more than one output should be shorted at a time.
CD
<
n"
CD
SN54147, SN74147 switching characteristics, Vee = 5 V, T A = 25°e
UI
PARAMETER~
tPLH
FROM
TO
(INPUT)
(OUTPUT)
Any
WAVEFORM
In·phase
Any
output
Out-af-phase
tpHL
tpLH
Any
tpHL
Any
output
SN54148, SN74148 switching characteristics, Vee
PARAMETER~I
tPLH
FROM
TO
(INPUT)
(OUTPUT)
AO,Al,orA2
tpLH
tpHL
1 thru 7
AO, Al, or A2
tPLH
tpHL
tpLH
tpHL
tpLH
tpHL
tPLH
tpHL
tpLH
\
Othru 7
Othru 7
EI
EI
EI
EO
RL=400!!,
See Note 4
9
14
7
11
13
19
12
19
ns
ns
10
15
9
14
output
Out-af-phase
output
AO,Al,orA2
GS
EO
TVP MAX UNIT
output
Out-of·phase
In-phase
GS
TEST CONDITIONS MIN
In-phase
output
tpHL
In-phase
output
CL =
n
pF,
RL = 400 !l,
See Note 4
13
19
12
6
19
10
14
25
18
30
14
10
25
15
10
15
In-phase
8
12
output
10
15
In-phase
10
15
output
17
30
1tPlH
= propagation delay time, low-to-high-level output
tpHl = propagation delay time, high-to-Iow·level output
NOTE 4: load circuits and voltage waveforms are sho~n in Section 1.
2-454
CL= 15pF,
TYP MAX UNIT
= 5 V, T A = 25°C
WAVEFORM
1 thru 7
tpHL
TEST CONDITIONS MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ns
ns
ns
ns
ns
ns
ns
SN54LS147. SN54LS14B. SN74LS147. SN74LS14B
10·L1NE TO 4·L1NE AND B·L1NE TO J·L1NE PRIORITY ENCODERS
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
VIH
High~level
VIL
Low-level input voltage
VIK
Input clamp voltage
2
II
Vec - MIN,
Vec
VIL
~
~
MIN,
VIH
0.8 V,
10H
VCC - MIN,
ilOL
VIL
Input current at
'LS148 inputs 1 thru 7
maximum input voltage
All other inputs
'LS148 inputs 1 thru 7
High-level input current
All other inputs
'LS148 inputs 1 thru 7
IlL
Low-level input current
lOS
Short-circuit output current§
ICC
Supply current
All other inputs
~
2 V
~-400!J.A
2.5
~4mA
0.8
-1.5
-1.5
3.4
2.7
0.25
VCC~MAX,
VCC~
MAX,
Vec~
MAX
VI
VI
VI
~
~
~
V
0.7
0.4
V
V
V
3.4
0.25
0.4
0.35
0.5
V
~ VILmaxllOL ~ 8 mA
Vec~MAX,
UNIT
2
~-18mA
VIH~2V,
VOL Low-level output voltage
IIH
SN74LS'
MIN TYP:j: MAX MIN TYP:j: MAX
input voltage
VOH High-level output voltage
II
SN54LS'
TEST eONDITlONst
7V
2.7 V
0.4 V
0.2
0.2
0.1
0.1
40
40
20
20
-0.8
-0.8
-0.4
-20
-0.4
-100 -20
mA
!J.A
mA
-100
mA
VCC ~ MAX,
ICondition 1
12
20
12
20
mA
See Note 5
I Condition 2
10
17
10
17
mA
NOTE 5: For 'LS147, ICC (condition 1) is measured with Input 7 grounded, other inputs and outputs open; ICC (condition 2) is measured
with all inputs and outputs open. For 'LS148, ICC (condition 1) is measured with inputs 7 and EI grounded, other inputs and
•
outputs open, ICC (condition 2) is measured with all input'S and outputs open.
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j: All typical values are at Vee"" 5 V, T A :: 25 0 c.
~ Not more than one output should be shorted at a time.
SN54LS147 SN74LS147 switching characteristics , Vee = 5 V , TA = 25°e
PARAMETER~
tPLH
tpHL
. tPLH
tpHL
FROM
TO
(INPUT)
IOUTPUT)
Anv
Anv
Anv
WAVEFORM
TEST CONDITIONS MIN
In·phase
eL~15pF,
output
Out-of-phase
Anv
RL~2kn,
See Note 4
output
TYP MAX UNIT
12
18
12
18
21
33
15
23
ns
ns
SN54LS148, SN74LS148 switching Characteristics, Vee = 5 V, TA = 25°e
PARAMETER~
tPLH
tpHL
tpLH
tpHL
tPLH
tpHL
tPLH
tPHL
tpLH
tPHL
tpLH
tPHL
tPLH
FROM
TO
(lNPUTI
IOUTPUT)
1 thru 7
AD. Al. or A2
1 thru 7
o thru 7
WAVEFORM
AD. Al, or A2
EO
o thru 7
GS
EI
AD, Al. or A2
EI
GS
EI
EO
tPHL
TEST CONDITIONS MIN
TVP MAX UNIT
In-phase
output
Out-of·phase
14
18
15
25
20
36
output
Out-of-phase
16
29
output
In-phase
output
In-phase
CL
RL
= 15 pF,
= 2 kQ,
See Note 4
7
18
25
40
35
55
9
21
16
25
12
25
output
In-phase
12
17
output
14
36
In-phase
output
12
21
23
35
ns
ns
ns
ns
ns
ns
ns
~ tPlH == propagation delay tIme, low·to high·level output
tPHL =: propagatiOn delay time, high·to low level output
NOTE 4: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-455
SN54147, SN54148 (TIM9907), SN54LS147, SN54LS148,
SN74147, SN74148, SN74LS147, SN74LS148
10-L1NE TO 4-L1NE AND 8-L1NE TO 3-L1NE PRIORITY ENCODERS
TYPICAL APPLICATION DATA
~________________
~A
___________________
~
16-LINE DATA
(ACTIVE
LOW)
I
0
1
2
3
4
5
6
7
8
ENABLE
(ACTIVE LOW)
10 11 12 13 14 15 \
'148I'LS148
EO
AO
-t
-t
r-
A1
A2
\ 0
PRIDRITY FLAG
(ACTIVE LOW)
3 I
2
'---...,V,-----'
C
ENCODED DATA (ACTIVE LOW)
CD
~-
(")
CD
en
l6-LlNE DATA (ACTIVE
LOW)
r--______________
________________
~A~
I
0
1
2
3
4
5
6
7
8
8
9
10
'148/'LS148
EO
AO
A1
~
11 12 13 14 15 \
ENABLE
(ACTIVE LOW)
'1481'LS148
A2
EO
AO
A1
3 /
'---""IVt----..J
A2
GS
PRIORITY FLAG
(ACTIVE HIGH)
ENCODED DATA (ACTIVE HIGH)
Since the '1471'LS147 and '148/,LS148 are combinational logic circuits, wrong addresses can appear during input transients. Moreover,
for the '148/'LS148 a change frpm high to low at input EJ can cause a transient Iowan the GS output when all inputs are high. This
must be considered when strobing the outputs.
2-456
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
SN54150, SN54151A, SN54LS151, SN54S151,
SN74150, SN74151A, SN74LS151, SN74S151
DATA SELECTORS/MULTIPLEXERS
DECEMBER 1972-REVISED MARCH 1988
SN54150 ... J OR W PACKAGE
SN74150 ... N PACKAGE
•
'150 Selects One-of-Sixteen Data Sources
•
Others Select One-of-Eight Data Sources
•
All Perform Parallel-to-Serial Conversion
•
All Permit Multiplexing from N Lines to One
Line
ITOP VIEW)
•
Also For Use as Boolean Function Generator
•
Input-Clamping Diodes Simplify System
Design
•
Fully Compatible with Most TTL Circuits
TYPICAL AVERAGE
TYPICAL
PROPAGATION DELAY TIME
POWER
DATA INPUT TO W OUTPUT
DISSIPATION
13 ns
200 mW
'151A
8 ns
145mW
'LS151
13 ns
30mW
'S151
4.5 ns
225 mW
TYPE
'150
G
A
B
GNO
e
(TOP VIEW)
W
en
D4
Q)
05
06
07
'S
CJ
Q)
o
A
B
G
GNO
-'
lI-
e
SN54LS151, SN54S151 ... FK PACKAGE
(TOP VIEW)
~
3
The '1 51 A and '1 52A incorporate address buffers that
have symmetrical propagation delay times through the
complementary paths. This reduces the possibility of
transients occurring at the output(s) due to changes
made at the select inputs, even when the '151 A
outputs are enabled (i.e., strobe low).
TEXAS
Vee
03
02
01
DO
Y
The '150 has only an inverted W output; the '151 A,
'LS151, and 'S151 feature complementary Wand Y
outputs.
:::~:~~i~a{::I~J~ ~:~:~i:; ~~D::~:::::t:~~S not
0
SN54151A, SN54LS151. SN54S151 ... J OR W PACKAGE
SN741S1A ... N PACKAGE
SN74LS151, SN74S151 ... D OR N PACKAGE
These monolithic data selectors/multiplexers contain
full on-chip binary decoding to select the desired data
source. The '150 selects one-of-sixteen data sources;
the '151A, 'LS151, and 'S151 select one-of-eight
data sources. The '150, '151A, 'LS151, and 'S151
have a strobe input which must be at a low logic level
to enable these devices. A high level at the strobe
forces the W output high, and the Y output (as
applicable) low.
specifications per the tarms of Texas Instruments
E8
E9
El0
Ell
E12
E13
E14
E15
W
description
PRODUCTION DATA d•• ume.ts .o.tai. i.formatio.
current 8S of publication datI. Products conform to
Vee
E7
E6
E5
E4
E3
E2
El
EO
01
DO
4
5
Ne
Y
6
U
8 ~ ~C'l
2
20 19
05
06
Ne
07
8
A
9
10 111213
1<.:1 Cl U U ----JC
~
(111
~r-..
C
DO
ADDRESS BUFFERS FOR 'LSl5l, 'S151
ADDRESS BUFFERS FOR '15lA
,,~~::[:~iir'l
l~~r--r---_---J' .
(BINARY)
Pin numbers shown are for 0, J, N, and W packages.
2~460
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54150, SN54151A, SN54LS151, SN54S151,
SN74150, SN74151A, SN74LS151, SN74S151
DATA SELECTORS/MULTIPLEXERS
'151A, 'LS151, 'S151
STROBE
(7)
G
DO
01
(4)
(3)
02 (2)
03
DATA
INPUTS
(11
04 (151
D5 (141
06 (131
07 (121
II)
,AAe BCC ,
C1)
TO ADDRESS BUFFERS
'S
CJ
C1)
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 2): '150, 'ISlA, 'S151 ........................................... 5.5 V
'LS151 ...................................................... 7V
Operating free-air temperature range: SN54' .................................... - 55°C to 125°C
SN74' ........................................ DoC to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 1 50°C
NOTES: 1: Voltage values are with respect to network ground terminal.
2. For the '150, input voltages must be zero or positive with respect to network ground terminal.
TEXAS
.Jf
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-461
....I
lI-
SN54150, SN54151A, SN74150, SN74151A
DATA SELECTORS/MULTIPLEXERS
recommended operating conditions
SN54' .
MIN
Supply voltage, Vee
4.5
NOM
5
High-level output current, IOH
SN74'
MAX
MIN
5.5
4.75
MAX
5.25
V
-800
MA
16
mA
70
°e
5
-800
Low-level output current, tOl
UNIT
NOM
16
-55
Operating free-air tempe.rature, T A
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise notedl
PARAMETER
VIH
High-level input voltage
Vil
. VII<
Low-level input voltage
V
OH
r-
C
CD
<
C:;"
CD
en
MIN
TYP*
'151A
MAX
MIN
2
Input clamp voltage
High-level outRut voltage
~
Vee
~
MIN,
II
Vee
~
MIN,
VIH
~
2 V,
2
0.8 V,
10H
~
-800
~
Vil
~
Vee
~
Vil
-8 mA
V
-1.5
MIN,
VIH
~
2 V,
0.8 V,
10l
~
16mA
II
Input current at maximum input voltage Vee
~
MAX, VI
~
~~
2.4
UNIT
MAX
TYP*
0.8
VOL .Low·'evel output. voftage
-I
-I
'150
TEST eONDITIONSt
3.4
0.2
2.4
0.8
V
-1.5
V
3.4
0.4
V
0.2
0.4
1
5.5 V
V
mA
1
IIH
High·level input current
Vee
~
MAX, VI
~
2.4 V
40
40
.A
III
Low·level input current
Vee
~
MAX, VI
~
0.4 V
-1.6
-1.6
mA
lOS
Short·circuit output current§
Vee
~
MAX
ICC
Supply current
Vee
~
MAX, See Note 3
I SN54'
I SN74'
-20
-55
-20
-18
-55
-18
40
-55
mA
-55
68
29
mA
48
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type.
t All typical velues at Vee ="5 V, TA
=
25°C.
§ Not more than one output of the' 151 A should be shorted at a time.
NOTE 3: ICC is measured with the strobe and data select inputs at 4.5 V. all other inputs and outputs open.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETERII
TO
TEST
IOUTPUT)
CONDITIONS
tPLH
A, B,ore
tPHL
141evelsl
tpLH
A, B, e, or D
tpHL
13 levelsl
tplH
Strobe
tpHL
tPlH
Strobe
tpHl
tpLH
G
G
DO thru D7
tpHL
EO thru E15, or
tpLH
,.
FROM
(INPUT)
DOth,u D7
ir'HL
TYP
MAX
y
W
y
W
eL
~
15pF,
Rl
~
400
n,
See Note 4
W
1tPLH '" propagation delay time, low-to-high-Ievel output
tpHl ~ prQpagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
MIN
TYP
MAX
25
38
25
38
23
35
17
26
22
33
19
30
21
33
22
33
14
21
15
23
13
20
15.5
24
21
30
y
.
2-462
'151A
'150
MIN
18
27
8.5
14
8
14
13
20
8
14
UNIT
ns
ns
ns
ns
ns
ns
SN54LS151. SN74LS151
OAT A SELECTORS/MULTIPLEXERS
recommended operating conditions
SN74LS151
SN54LS151
MIN
Supply voltage,
Vee
NOM
4.5
5
MAX
MIN
5.5
4.75
NOM
5
-400
High-level output current, IOH
MAX
V
-400
8
"A
rnA
70
"e
4
Low-level output current, IOL
-55
Operating free-air temperature, T A
125
UNIT
5.25
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH High-level output voltage
VOL Low-level output voltage
Input current at
II
t
maximum input voltage
SN54LS151
TEST CONDITIONS t
PARAMETER
MIN
TYP*
SN74LS151
MAX
2
Vee
~
MIN.
II
Vee
~
MIN.
VIH
~
10H
~
VIL ~ VILmax.
~
Vee
MIN.
~
2.5
-400 pA
MAX
UNIT
V
0.7
0.8
V
-1.5
-1.5
V
3.4
VIH ~ 2 V. IIOL ~ 4 rnA
2.7
0.25
0.4
IIOL ~ 8 rnA
VIL ~ VILmax
TYP*
2
-18 rnA
2 V.
MIN
3.4
V
0.25
0.4
0.35
0.5
V
U)
Vee
~
MAX.
VI
~7V
~
0.1
0.1
mA
CI)
(,)
'S;
IIH
High-level input current
Vee
MAX.
VI
~
2.7 V
20
20
pA
IlL
Low-level input current
Vee ~ MAX.
VI
~
0.4 V
-0.4
-0.4
mA
lOS
Short-circuit output current § Vee
~
MAX
-100
mA
Supply current
Vee
~
ICC
MAX.
10
mA
-20
-100
Outputs open,
6.0
All inputs at 4.5 V
-20
10
6.0
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type.
= 5 V. TA == 25°C.
Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second.
CI)
C
......J....
t All typical values are at VCC
§
switching characteristics.
PARAMETER'
tpLH
Vee
= 5
TO
(OUTPUT)
A, B, or e
(4 levels)
tpLH
A. B. or e
tPHL
(3 levels)
Strobe
tPHL
tPLH
tpHL
T A 25°C
(INPUT)
tpHL
tpLH
V.
FROM
G
TEST CONDITIONS
Y
W
Y
CL
RL
Strobe
G
~
~
15 pF.
2 kll.
See Note 4
W
MIN
TYP
MAX
27
43
1B
30
14
23
20
32
26
42
20
32
15
24
18
30
20
32
tpHL
16
26
tPLH
13
21
12
20
tPLH
Any D
Any D
Y
W
tpHL
UNIT
ns
ns
ns
ns
ns
ns
'tPLH =: propagation delay time, low-to-high-Ievel output
tpHL =: propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-463
SN54S151. SN74S151
DATA SELECTORSIMULTlPLEXERS
recommended operating conditions
SN54S151
MIN
Supply voltage, Vee
NOM
4.5
5
SN74S151
MAX
MIN
5.5
4.75
NOM
5
-1
High·level output current, IOH
Low-level output current, IOl
MAX
5.25
V
-1
mA
20
mA
70
"e
20
Operating free-air temperature, T A
-55
125
UNIT
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONOITIONSt
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
VOL
-I
-I
r-
C
CD
~.
(")
CD
CII
TYP:!:
MIN
MAX UNIT
V
2
High-level output voltage
Low-level output voltage
Vee - MIN,
11- -18mA
Vee - MIN,
VIH"2V,
I SN54S151
VIL" 0.8 V,
10H" -1 mA
Vee - MIN,
VIH-2V,
VIL" 0.8 V,
10L" 20 mA
I SN74S151
2.5
3.4
2.7
3.4
0.8
V
-1.2
V
V
0.5
V
II
Input current at maximum input voltage
Vee" MAX, VI" 5.5 V
1
mA
IIH
High-level input current
Vee- MAX, VI- 2.7V
50
IlL
Low-level input current
Vee
2
IlA
mA
lOS
Short-circuit output current~
mA
Supply current
Vee MAX
Vee - MAX,
-100
lee
70
mA
MAX,
VI-0.5V
-40
All inputs at 4.5 V,
45
All outputs open
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
tAil typical values are at Vee = 5 V, T A = 25"C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
switching characteristics. Vee
PARAMETER'
=
5 V. TA 25°e
FROM
TO
IINPUT)
(OUTPUT)
tPLH
A, B, or C
tPHL
(4 levels)
tpLH
A, B, or C
tpHL
(3 levels)
tpLH
Y
W
Y
Any D
CL
tPHL
tpLH
RL
Any D
W
tpHL
tpLH
Strobe
tpHL
tpLH
tpHL
TEST CONDITIONS
Strobe
G
= 15 pF,
= 280 kll,
See Note 4
Y
G
W
'tPLH = propagation delay time, low-to-high-Ievel output
tpHL = propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuits and voltage waveforms are shown in Section 1.
2-464
TEXAS'~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
TYP
MAX
12
18
12
18
10
15
9
13.5
8
12
8
12
4.5
7
4.5
7
11
16.5
12
18
9
13
8.5
12
UNIT
ns
ns
ns
ns
ns
ns
SN54153. SN54LS153. SN54S153
SN74153. SN74LS153. SN74S153
DUAL 4-LlNE TO HINE DATA SELECTORS/MULTIPLEXERS
DECEMBER 1972 - REVISED MARCH 1
•
Permits MUltiplexing from N lines to 1 line
•
Performs Parallel-to-Serial Conversion
•
Strobe (Enable) Line Provided for Cascading
(N lines to n lines)
•
High-Fan-Out, Low-Impedance, Totem-Pole
Outputs
•
Fully Compatible with most TTL Circuits
TYPICAL AVERAGE
PROPAGA nON DELAY TIMES
TYPE
'153
'L5153
'5153
FROM
DATA
14 ns
14 ns
6 ns
SN54153, SN54LS153, SN54S153 , . ,J DR W PACKAGE
SN74153. , ,N PACKAGE
SN74LS153, SN74S153, . ,0 OR N PACKAGE
(TOP VIEW)
FROM
SELECT
17 ns
19 ns
9.5 ns
22 ns
POWER
DISSIPATION
22 ns
18DmW
31 mW
12 ns
225 mW
VCC
B
2<3
A
2C3
2C2
2Cl
2CO
2Y
lC3
lC2
lCl
lCO
lY
GND
TYPICAL
FROM
STROBE
lG
•
SN54LS153. SN54S153 , . ,FK PACKAGE
(TOP VIEWI
U
all~ ~ ~I~
I/)
3 2
description
Q)
U
4
'S;
5
Each of these monolithic, data selectors/multiplexers
contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to
the AND-OR gates. Separate strobe inputs are provided
for each of the two four-line sections.
Q)
6
C
-'
7
........
8
9 10111213
>OU>O
ZZNU
t!l
N
FUNCTION TABLE
SELECT
DATA INPUTS
STROBE
OUTPUT
B
A
CO
Cl
C2
C3
G
Y
x
x
x
x
x
X
H
L
L
L
L
X
X
X
L
L
L
L
H
X
X
X
L
H
INPUTS
L
H
X
L
X
X
L
L
L
H
X
H
X
X
L
H
H
L
X
X
L
X
L
L
H
L
X
X
H
X
L
H
H
H
X
X
X
L
L
L
H
H
X
X
X
H
L
H
NC - No internal connection
Select inputs A and B are common to both sections.
H = high level. L = low level, X = irrelevant
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (See Note 11 .. ,., .. ,., ... ,.,., .... ,.,.,., ... , . , . , . , ' , . , . , . . .
7 V
Input voltage: '153, 'S 153 .. , . , " , . " . , " , . , . , . , . " .... ,., ...................... ,.,' 5.5 V
Ul~,., ........... , .... , .......... , . , . , . , . , . " " " , . " , " ' , .. , .. , ... 7V
Operating free-air temperature range: SN54' , . , . , . , . , " , . , . , " , . , .. , ..... , ...... -55°C to 125°C
SN74' ... ,.,., .... , ........... ,., ... , . , " , ... , ooC to 70°C
Storage temperature range. , ... , ... , , . , . , . , , .... , .. , . , , , , , , . , .. , ... , ..... , .. - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
PRODUCTION DATA documents c.ntain information
currant as of publicatian date. Products conform to
specifications per the tarms of Texas Instruments
:::::~~i~ai~r:,~l~ ~:\:~ti:; :'~O=:::::t!O:S
not
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-465
SN54l53. SN54LS153. SN54S153
SN74l53. SN74LS153. SN74Sl53
DUAL 4·UNE TO l·UNE DATA SELECTORS/MULTIPLEXERS
logic symbol t
(14)
A
O}
0
1
G 3'
(2) .
B
"1
(1)
r--..
MUX
r
EN
(6)
lCO
0
(5)
(7)
lCl
IV
1
(4)
lC2
2
(3)
lC3
3
(15)
20
r--..
(0)
2CO
(11)
(9)
2V
2Cl
(12)
2C2
(13)
2C3
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and lEe
Publication 617-12.
logic diagrams (positive logic)
STROBE lG (1)
(ENABLE)
ICO (6)
[
lCl~(5~)________~~~~-/
DATA 1 11C2 (4)
lC3-"(3'-'-)--------+--1~+-L-./
2CO (10)
DATA 2
2C2 (12)
2C3 (13)
STROBE2G~
(ENABLE) f1srv-------------4-L--../
Pin numbers shown are for 0, J, N, and W packages.
2-466
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54153, SN54LS153, SN54S153
SN74153, SN14LS153, SN14S153
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
schematics of inputs and outputs
c
EQUIVALENT OF INPUTS OF 'S153
EQUIVALENT OF INPUTS OF '153
YCC
VCC13--
4 kH NOM
INPUT
2.8 kn NOM
--
INPUT
--
en
Q)
EQUIVALENT OF ALL OTHER INPUTS
OF'LS153
EQUIVALENT OF 1G. 2(; IN PUTS
OF LS153
vcc
VCC--~"---
f
20 kn NOM.
INPUT
INPUT
i>
CJ
.S;
Q)
C
-'
....
....
,,
n
TYPICAL OF OUTPUTS OF '153
TYPICAL OF OUTPUTS OF 'LS153
TYPICAL OF OUTPUTS OF 'S153
---_-VCC
R~120!!
NOM
"L-+-OUTPUT
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-467
SN54153, SN74153
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
recommended operating conditions
SN54153
MIN
Supply voltage. Vee
NOM
4.5
SN74153
MAX
MIN
5.5
4.75
5
NOM
-800
High-level output current. IOH
MAX
V
-BOO
I'A
16
mA
°e
16
Low-level output current, IOl
Operating free-air temperature, T A
125
-55
UNIT
5.25
5
0
70
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
..
-4
-4
rC
(I)
<
SN54153
TEST eONDITIONSt
TYPt
MIN
SN74153
MAX
MIN
TYPt
MAX
UNIT
V
VIH
High-level input voltage
Vil
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current at maximum input voltage
Vee~MAX,
VI
~
5.5 V
IIH
High-level input current
Vee~
MAX,
VI
~
2.4 V
40
40
I'A
III
Low-level input current
Vee
MAX.
VI-0.4V
1.6
1.6
mA
-57
mA
60
mA
2
Vee- MIN.
11--12mA
Vee~
VIH
10H
MIN.
~0.8V.
Vil
Vee - MIN.
~
Vil
Short-circuit output current~
lOS
leel Supply current, output low
0.8 V,
2V.
~
2.4
-800!lA
IOl
~
0.8
0.8
V
-1.5
-1.5
V
2.4
3.4
VIH-2V,
0.2
16mA
0.4
-20
MAX. See Note 2
-55
36
V
3.4
0.2
1
Vee- MAX
Vee
2
0.4
1
-18
52
36
V
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at
Vee = 5
V, T A = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 2: ICCL is measured with the outputs open and all inputs grounded.
switching characteristics, Vee = 5 V, T A = 25° C
PARAMETER~I
FROM
TO
(INPUT)
(OUTPUT)
TEST CONDITIONS
TYP
MAX UNIT
tPlH
Data
Y
12
18
ns
tpHl
Data
Y
15
23
ns
tplH
Select
Y
eL~30pF.
22
34
ns
tpHl
Select
y
See Note 3
22
34
ns
tplH
Strobe G
y
19
30
ns
tpHl
Strobe G
Y
15
23
ns
'tPlH = propagation delay time, low-to-high-Ievel output
tpHl = propagation delay time, high-to-Iow-Ievel output
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
2-468
MIN
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
Rl~400n,
SN54LS153, SN74LS153
DUAL 4-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS
recommended operating conditions
SN54lS153
VCC
Supply voltage
VIH
High-level input voltage
Vil
Low-Jevel input voltage
IOH
High-level output current
SN74lS153
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
IOl
Low-level output current
TA
Operating free-air temperature
UNIT
MIN
2
V
V
0.7
0.8
-0.4
-0.4
rnA
8
rnA
70
°c
4
-55
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIK
VOH
Val
IlL
VCC= MIN,
II = -18 rnA
VCC- MIN,
VIH - 2 V,
MIN
Vcc- MIN,
Vil = MAX
VIH-2V,
VIL = MAX,
MAX,
2.5
IIH
VCC- MAX,
VI-2.7V
VCC = MAX,
VI = 0.4 V
VCC- MAX
ICCL
VCC - MAX,
SN74lS153
MAX
I
IOL = 4 mA
I
IOL=8rnA
3.4
0.25
VI-7 V
VCC
IOS§
TYPt
MIN
TYPt
-1.5
IOH = -0.4 mA
II
l ro, 2G
I All other
SN54lS153
TEST CONDITIONS t
PARAMETER
2.7
0.4
V
0.25
0.4
0.35
0.5
mA
20
20
~A
-0.2
-0.2
-100
6.2
t For conditions shown as MIN or MAX, use the appropriate
t All typical values are at Vee = 5 V, T A = 25°C.
V
0.1
-0.4
See Note 2
V
3.4
0.1
- 20
UNIT
MAX
-1.5
rnA
-0.4
- 20
10
-100
rnA
10
rnA
6.2
value specified under recommended operating conditions.
l:? Not more than one output should be shorted at a time.
NOTE 2: leeL is measured with the outputs open and all inputs grounded.
switching characteristics, Vee = 5 V, TA = 25°e
FROM
TO
(INPUT)
(OUTPUT)
tPLH
Data
Y
tpHL
Data
Y
tpLH
Select
Y
tpHL
Select
y
y
y
PARAMETER~
tPLH
Strobe G
tPHL
Strobe G
TEST CONDITIONS
CL=15pF,
RL=2kn,
See Note 3
MIN
TYP
MAX UNIT
10
15
17
26
19
29
25
38
16
24
21
32
ns
ns
ns
ns
ns
ns
'tPLH = propagation delay time, low-to-high-Ievel output
tpHL = propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-469
SN54S153, SN74S153
DUAL 4·UNE TO l·UNE DATA SELECTORS/MULTIPLEXERS
re(:ommended operating conditions
SN54S153
MIN
Supply voltage, Vee
4.5
5
fre~air
5.5
MIN
NOM
MAX
4.75
5
5.25
-1
High-level output current, IOH
Low-level output current, IOl
Operating
SN74S153
NOM MAX
20
temperature, T A
-55
125
0
UNIT
V
-1
mA
20
mA
70
"e
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
..of
..of
TEST CONDITIONSt
High-level input voltage
VIL
VIK
Low-level input voltage
I "put clamp voltage
VOH
High-level output voltage
Vee= MIN,
II = -18mA
Vee = MIN,
VIH = 2V,
V
IS.,ies54S
2.5
3.4
I
2.7
3.4
10H = -1 mA Series 74S
Vee=MIN,
VIH=2V,
VIL = 0.8 V,
10L = 20mA
II
Input current at maximum input voltage
C
IIH
High-level input current
<
IlL
Low-level input current
lOS
Short-circuit output current§
Vee -MAX
n'
CD
MAX UNIT
-1.2
VIL = 0.8 V,
Low-level output voltage
CD
TYPt
0.8
VOL
r-
MIN
2
VIH
V
V
0.5
V
1
mA
Vee = MAX, VI - 2.7 V
50
Vee - MAX, VI =0.5V
-2
"A
mA
-100
mA
70
mA
Vee = MAX, VI=5.5V
leeL Supply current, low·level output
V
-40
Vee=MAX, See Note 2
45
til
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t. All typical values are at Vee = 5
V. T A "" 25° c.
§Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second.
NOTE 2: ICCL is measured with the outputs open and all i~puts grounded.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~
FROM
TO
(INPUT)
(OUTPUT)
TEST CONt:?ITIONS
tpLH
Data
tpHL
Data
Y
Y
tPLH
Select
y
eL=15pF,
tpHL
Select
y
See Note 3
tPLH
Strobe G
tpHL
Strobe
G
TYP
MAX UNIT
6
6
9
9
ns
11.5
18
ns
12
18
ns
y
10
15
ns
Y
9
13.5
ns
.tPLH = propagation delay time. low~to~high-Ievel output
tpHl = propagation delay time, high-to-Iow·level output
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
2-470
MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 ;. DALLAS. TEXAS 75265
RL = 280u,
ns
SN54154. SN74154
4·LlNE TO 16·LlNE DECODERS/DEMULTIPLEXERS
DECEMBER 1972 - REVISED MARCH 88
• '154 is Ideal for High-Performance Memory
Decoding
SN54154 ... J OR W PACKAGE
SN74154 ... N PACKAGE
• Decodes 4 Binary-Coded Inputs into One of
16 Mutually Exclusive Outputs
(TOP VIEW)
0
• Performs the Demultiplexing Function by
Distributing Data From One Input line to Any
One of 16 Outputs
1
2
3
4
5
6
7
• Input Clamping Diodes Simplify System
Design
• High Fan-Out, Low-Impedance, Totem-Pole
Outputs
8
9
10
GND
• Fully Compatible with Most TTL and MSI
Circuits
TYPICAL AVERAGE
PROPAGATION DELAY
STROBE
3 LEVELS OF LOGIC
23 ns
TYPICAL
POWER DISSIPATION
19 ns
Vee
A
B
e
G1
15
14
13
12
logic symbols (alternatives I t
170 mW
lJ)
Q)
(,)
description
'>
Each of these monolithic, 4-line-to-16-line decoders
utilizes TTL circuitry to decode four binary-coded inputs
into one of sixteen mutually exclusive outputs when
both the strobe inputs, G1 and G2, are low. The
demultiplexing function is performed by using the 4 input lines to address the output line, passing data from
one of the strobe inputs with the other strobe input low.
When either strobe input is high, all outputs are high.
These demultiplexers are ideally suited for implementing
high-performance memory decoders. For ultra-high
speed systems, SN54S138/SN74S138 and
SN54S139/SN74S139 are recommended.
Q)
C
........
..J
These circuits are fully compatible for use with most
other TTL circuits. All inputs are buffered and input
clamping diodes are provided to minimize transmissionline effects and thereby simplify system design.
The SN54154 is characterized for operation over the full
military temperature range of - 55 °e to 125°e. The
SN 7 41 54 is characterized for operation from ooe to
70 o e.
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and
lEe Publication 617-12.
PRODUCTION DATA documents contain information
current as of publication data. Products conform to
specifications per the terms of Texas Instruments
=~~~~:~~i;ai::I~'a ~!:~~~j:f :'IO::~:::t::'~ not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-471
SN54154. SN74154
4·LlNE TO 16·LlNE DECODERS/DEMULTIPLEXERS
FUNCTION TABLE
OUTPUTS
INPUTS
,
~
~
G1
G2
0
C
B
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H'
L
L
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
r-
H
L
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
C
H
H
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
CD
H = high level, L = low level, X :::: Irrelevant
<
rr
CD
en
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
V C CReq
3c 6 kll NOM
INPUT
2-472
--
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54154, SN74154
4·LlNE TO 16·LlNE DECODERS/DEMULTlPEXERS
logic diagram (positive logic)
A
1181
(19)
A
INPUTS
B
c
(1)
B
C
0
A
B
~G
C
.... A
(21)
(20)
...........
(3)
L.!:: ~
...........
A
15)
(6)
0
1
2
3
4
5
~6
.... B
p~ B
~
18)
...........
(9)
c
c
o
(2)
(4)
~ TV
~
...........
0
...........
-
0
0
0
...........
-
C
A
B
C
(11)
(13)
(14)
(15)
...........
(16)
GL-...,..-..
(17)
A
OUTPUTS
8
II)
9
.S;
10
C
11
..J
Q)
(10)
...........
B
7
12
CJ
Q)
lI-
13
14
15
0
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-473
SN54154, SN74154
4·LlNE TO 16·LlNE DECODERS/DEMULTIPLEXERS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
7V
5.5V
-55°C to 125°C
O°C to 70°C
--65°C to 150°C
Supply voltage, VCC (see Note 1)
Input voltage. . . . . . . .
Operating free·air temperature range: SN54154 Circuits
SN74154 Circuits
Storage temperature range
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54154
MIN
Supply voltage, Vee
High~leve'
4.5
NOM
SN74154
MAX
MIN
5.5
4.75
5
output current, IOH
5.25
V
16
/iA
rnA
70
"e
16
Operating free-air temperature, T A
-55
125
UNIT
-800
5
-800
Low-level output current, tOl
MAX
NOM
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
-I
-I
rC
VIH
High·level input voltage
VIL
Low·level input voltage
VIK
I nput clamp voltage
VOH
High·level output voltage
<
(1)
til
VOL
Low-level output voltage
II
Input current at maximum input voltage
Vee= MAX, VI = 5.5V
MIN
TYP
SN74154
MAX
2
Vee - MIN,
11--12rnA
Vee - MIN,
VIH = 2V,
VIL = 0.8 V,
10H = -800/iA
Vee - MIN,
VIH - 2 V,
VIL = 0.8 V,
10L = 16 rnA
(1)
(i'
SN54154
TEST CONDITIONSt
PARAMETER
2.4
MIN
TYpt
MAX
UNIT
V
2
0.8
0.8
V
-1.5
-1.5
V
3.4
2.4
0.4
0.2
V
3.4
0.2
1
0.4
1
V
rnA
IIH
High·level input current
Vee= MAX, VI=2.4V
40
40
/iA
IlL
Low-level input current
Vee = MAX, VI = 0.4 V
-1.6
-1.6
rnA
lOS
Short-circuit output current~
Vee = MAX
-57
rnA
lee
Supply current
Vee- MAX, See Note 2
56
rnA
-20
-55
34
-18
49
34
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
~AII typical values are at VCC -= 5 V, TA '" 25"C.
~Not more than one output should be shorted at a time.
NOTE 2:
ICC is measured with all inputs grounded and all outputs open.
switching characteristics, Vee = 5 V, TA = 25°e
TEST CONDITIONS
PARAMETER
Propagation delay time, low-to-high-Ievel output,
tpLH
from A. B. C, or D inputs through 3 levels of logic
Propagation delay time, high-to-Iow-Ievel output.
tPHL
tPLH
from A, B. C, or D inputs through 3 levels of logic
CL=15pF,
Propagation delay time. low-to-high-Ievel output,
See Note 3
from either strobe input
Propagation delay time, high-to-Iow-Ievel output,
tpHL
from either strobe input
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TeXAS 75265
RL = 400 II,
MIN
TYP
MAX UNIT
24
36
ns
22
33
ns
20
30
ns
18
27
ns
SN54155, SN54156, SN54LS155A, SN54LS156,
SN74155, SN74156, SN74lS155A, SN74LS156
DUAL 2-UNE TO 4-UNE DECODERS/DEMULTIPLEXERS
MARCH 1974 - REVISED MARCH 1988
• Applications:
Dual 2-to 4-Line Decoder
Dual 1-to 4-Line Demultiplexer
3-to 8-Line Decoder
1-to 8-Line Demultiplexer
SN54155, SN54156, SN54LS155A,
SN54LS156 , •. J OR W PACKAGE
SN74155, SN74156 ... N PACKAGE
SN74LS155A, SN74LS156 ... 0 OR N PACKAGE
ITOPVIEWI
lC
lG
B
VCC
2C
2G
lY3
lY2
lYl
lYO
GND
2Y3
2Y2
2Yl
2YO
• Individual Strobes Simplify Cascading for
Decoding or Demultiplexing Larger Words
• Input Clamping Diodes Simplify System
Design
• Choice of Outputs:
Totem Pole ('155, 'LS155A)
Open-Collector ('156, 'LS156)
TYPES
'155, '156
'LS155A
'LS156
TYPICAL AVERAGE
PROPAGATION DELAY
3 GATE LEVELS
21 ns
18 ns
32 ns
TYPICAL
POWER
DISSIPATION
125mW
31 mW
31 mW
A
SN54LSI55A, SN54LS156 .•. FK PACKAGE
ITOPVIEWI
ICl u u
~IU
~~Z>N
description
3
2
1 2019
26
B
These monolithic transistor·transistor·logic (TTL) cir·
cuits feature dual 1·line·to·4-line demultiplexers with
individual strobes and common binary-address inputs
in a single 16·pin package. When both sections are
enabled by the strobes, the common binary-address
inputs sequentially select and route associated input
data to the appropriate output of each section. The
individual strobes permit activating or inhibiting each
of the 4-bit sections as desired. Data appl ied to input
1 C is inverted at its outputs and data applied at 2C is
not inverted through its outputs. The inverter fol·
lowing the 1 C data input permits use as a 3·to·B-line
decoder or 1-to-8·line demultiplexer without external
gating. Input clamping diodes are provided on all of
these circuits to minimize transmission-line effects
and si mplify system design.
lY3
NC
1Y2
lYl
A
NC
2Y3
2Y2
9 10111213
couo>Zz»
~Cl
NN
NC - No intemal connection
logic symbols (2·line to 4-line decoder) t
'155, 'LS155A
'156, 'LS156
x/v
lG
x/v
lVO
lVl
lV2
EN"
lC",",,"---f
lV3
A-'-''''''""-I
B.....:.:~-I
lG
lC
A
B
2VO
2C
EN~
1151
1Y3
2VO
2Vl
2Vl
2G (141
lVO
lVl
lV2
2V2
2G
2V2
2V3
2<:
2V3
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and lEe Publication 617-12. For alternative symbols for other applications,
see the following page,
Pin numbers shown are for 0, J, N, and W packages.
PRODUCTION DATA do.umantl.ontain info'lRllion
.urr.nt .s of plbli.ation dilL ProdOOll oonlorm to
spRill••tion. par the tor... of T•••• Instrum.ntl
:'~=:=i~.{nr:.:ri =::i~n IIr=~'::1
not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·475
SN54155, SN54156, SN54LS155A, SN54LS156,
SN74155, SN74156, SN74LS155A, SN74LS156
DUAL 2·LlNE TO 4·LlNE DECODERS/DEMULTIPLEXERS
additional logic symbols (alternatives) t
'155, 'LS155A
3-line to 8-line Decoder
1-lino to 4-lin. DMUX
1-lin. to 8-lin. DMUX
XIV
DMUX
2VO
A
B
(131
2Vl
131
A
A
B
2V2
2V3
C
lYO
G
B
lYl
lYl
1V2
C
lVO
lG
lY2
lC
2Vl
(31
·2V2
111
1151
lVO
2V3
G
lVl
lV2
lV3
lV3
2VO
(131
lV3
2VO
2Vl
2V3
2V4
'156, 'LS156
3-line to 8-line Decoder
-t
-t
,...
0
DMUX
2VO
A
en
<
n'
en
1-lino to 8-lin. DMUX
1-line to 4-line DMUX
X/V
1131
2V1
A
A
B
B
2V2
B
C
2V3
C
lVO
1VO
G
1V1
1V1
VI
1V2
1V3
1V2
1V3
2V1
131
2V2
111
1151
2V3
lYO
G
1V1
lV2
1V3
2VO
2V1
2V3
2V4
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12_
Pin numbers shown are for D, J, N, and W packages.
q
schematics of inputs and outputs
-155_ '156
EQUIVALENT OF EACH INPUT
'155
'156
TYPICAL OF ALL OUTPUTS
TYPICAL OF ALL OUTPUTS
VCC
VCC
4 kU NOM
INPUT
2-476
_ _ ~OUTPUT
--
OUTPUT
TEXAS.'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2VO
1131
SN54155. SN54156. SN54LS155A. SN54LS156.
SN74155. SN74156. SN74LS155A. SN74LS156
DUAL 2·UNE TO 4·UNE DECODERS/DEMULTIPLEXERS
schematics of inputs and outputs (continued)
'LS155A, 'LS156
'LS155A
'LS156
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
TYPICAL OF ALL OUTPUTS
Vcc
Vcc--~--
20 kH NOM
_ _ ~OUTPUT
I N PUT """1~1-4~.....-
'-----1f--OUTPUT
logic diagram (positive logic)
FUNCTION TABLES
2-LlNE-TO-4-UNE DECODER
ST~§BE-.-:12:=:1_ _ _,
OR '-LiNE-TO-4-LlNE DEMULTIPLEXER
INPUTS
DATA
Ie --
~
B
A
DATA
IVO
IVI
IV2
IV3
H
H
H
H
10
IC
X
H
X
L
L
L
H
L
H
H
H
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
H
H
H
L
H
H
H
H
L
X
X
X
L
H
H
H
H
X
SELECT
B
OUTPUTS
STROBE
(/)
INPUTS
DATA
20
2C
X
H
X
L
L
L
L
H
L
H
L
L
H
H
X
X
X
D~lA -.-:1..:;15:::1_ _- .
STROBE 114:
2G
-"--'--------'
'>
CI)
a
...I
lI-
OUTPUTS
STROBE
I SELECT
B
A
CI)
(J
2VO
2VI
2V2
2V3
H
H
H
H
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
L
H
H
H
L
X
H
H
H
H
H
FUNCTION TABLE
3-lINE-TO-8-L1NE DECODER
OR '-UNE-TO-8-LlNE DEMULTIPLEXER
INPUTS
SELECT
CiBA"
OUTPUTS
STROBE
101
OR DATA
o·
I"
2VO 2VI
121
131
141
lSI
161
171
2V2 2V3 1VO 1Y1 1Y2 1Y3
X
X X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
L
L H
L
H
L
H
H
H
H
H
H
L
H
L
L
H
H
L
H
H
H
H
H
L
H H
L
H
H
H
L
H
H
H
H
H
L
L
L
H
H
H
H
L
H
H
H
H
L H
L
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
H
H
H
L
H
H
H H
L
H
H
H
H
H
H
H
L
t C '" inputs 1 C and
2C connected together
:1:13 = inputs 1 G and
2(; connected together
H = high level, L
TEXAS ."
INSlRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
= low
level, X
= irrelevant
2·477
SN5415i SN54156, SN54LS155A, SN54LS15l
SN74155, SN74156, SN74LS155A, SN74LS156
DUAL 2-LlNE TO 4-LlNE DECODERS/DEMULTIPLEXERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
I"put voltage: '155, '156
'LS155A, 'LS156
Off· state output voltage: '156
'LS156
Operating free·air temperature range: SN54', SN54LS' Circuits
SN74', SN74LS' Circuits
Storage temperature range
7V
5.5 V
7V
5.5 V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54155
MIN
Supply voltage,
Vee
4.5
NOM
SN74155
MAX
MIN
5.5
4.75
5
High-level output current, IOH
NOM
MAX
-800
V
-800
16
"A
rnA
70
°e
16
Low-level output current, IOL
Operating free-air temperature, T A
-55
125
UNIT
5.25
5
0
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
-I
-I
PARAMETER
r-
C
CD
~.
(')
CD
C/'I
SN54155
SN74155
TEST CONDITIONSt
Typ:i:
MIN
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
2
High-level output voltage
VOH
UNIT
MAX
Vee" MIN,
II" -8 rnA
Vee" MIN,
VIH" 2 V,
VIL" 0.8 V,
10H = -800 "A
Vee - MIN,
VIH - 2 V,
V
2.4
0.8
V
-1.5
V
3.4
V
VOL
Low-level output voltage
VIL"0.8V,
IOL"16rnA
II
Input current at maximum input voltage
Vee" MAX,
VI" 5.5 V
1
rnA
IIH
High-Jevel input current
Vee - MAX,
VI-2.4V
40
IlL
Low-level input current
Vee" MAX,
VI"O.4V
-1.6
"A
rnA
lOS
Short-circuit output currentS
Vee" MAX
Ice
Supply current
0.2
0.4
SN54155
-20
-55
SN74155
-18
-57
Vee" MAX,
SN54155
25
35
See Note 2
SN74155
25
40
V
rnA
rnA
tFor condItIons shown as MIN or MAX, use the approprIate value specIfied under recommended operating condItions.
tAil typical values are at V
Cc
= 5 V, T A = 25" c.
§ Not more than one output should be shorted at a time.
NOTE 2:
ICC is measured with outputs open, A, B, and 1 C inputs at 4.5 V, and 2C, 1 G, and 2G inputs grounded.
switching characteristics, Vee
PARAMETER
FROM
TO
LEVELS
(OUTPUT)
OF LOGIC
Y
2
Y
2
1G,or2(;
A, B, 2C,
tpHL
25°e
=
(lNPUTI
A, B, 2C,
tpLH
5 V, TA
=
1(;, or 2(;
SN54155
TEST CONDITIONS
CL
~
15 pF,
RL
~
400 n,
UNIT
TYP
MAX
13
20
ns
18
27
ns
21
32
ns
21
32
ns
tpLH
A or B
y
3
tpHL
A or B
Y
3
tpLH
1C
Y
3
16
24
ns
tpHL
1e
Y
3
20
30
ns
See Note 3
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-478
SN74155
MIN
-I.!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54156, SN74156
DUAL 2·UNE TO 4·UNE DECODERS/DEMULTIPLEXERS
recommended operating conditions
SN54156
MIN
Supply voltage,
High~level
Vee
NOM
4.5
SN74156
MAX
MIN
5.5
4.75
5
output voltage, VOH
MAX
NOM
5
5.5
Low-level output current, tOl
V
5.5
V
16
mA
"C
16
Operating free-air temperature, T A
-55
125
UNIT
5.25
0
70
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54156
PARAMETER
TEST CONOITIONSt
SN74156
TYP:j:
MIN
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
lOH
High-level output current
UNIT
MAX
2
V
O.S
VCC - MIN,
II - -SmA
VCC" MIN,
VIH-2V,
~
VIL" O.S V,
VOH
VCC- MIN,
VIH-2V,
5.5V
V
-1.5
V
250
I'A
VOL
Low-level output voltage
VIL" O.S V,
IOL" 16mA
V
I/)
II
Input current at maximum input voltage
VCC" MAX,
VI" 5.5V
1
mA
Q)
(,)
IIH
High-level input current
VCC- MAX,
VI- 2.4 V
40
/-IA
'S;
IlL
Low-level input current
VCC- MAX,
VI - 0.4 V
1.6
mA
ICC
VCC" MAX,
Supply current
See Note 2
0.2
I SN54156
I SN74156
0.4
25
35
25
40
mA
Q)
C
....I
lI-
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 2SoC.
NOTE 2: ICC is measured with outputs open, A, B, and 1C inputs at 4.5 V, and 2C, 1G, and 2G inputs grounded.
switching characteristics. Vee = 5 V. TA '" 25°e
PARAMETER§
FROM
TO
LEVELS
(INPUT!
IOUTPUT!
OF LOGIC
Y
2
A, B, 2C,
tpLH
1G, or 2G
A, B, 2C,
SN54156
TEST CONDITIONS
SN74156
MIN
=
UNIT
TYP
MAX
15
23
ns
Y
2
CL
15 pF,
20
30
ns
tPLH
A or B
y
3
23
34
n.
tpHL
A or B
Y
3
RL = 400 Il,
See Note 3
23
34
ns
tPLH
lC
Y
3
18
27
ns
tpHL
lC
Y
3
22
33
ns
tpHL
lG,or2G
§tPLH = propagation delay time, low-to-high-Ievel output
tpHL = propagation delay time, high·to·low~level output
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-479
•
SN54LS155A,. SN14LS155A
DUAL 2-UNE TO 4-UNE DECODERS/DEMULTIPLEXERS
recommended operating conditions
SN54LS155A
MIN
Supply voltage, Vee
NOM
4.5
5
High·level output current, IOH
SN74LS155A
MAX
MIN
5.5
4.75
NOM
5
-400
MAX
5.25
V
-400
IJA
8
mA
°e
4
Low-level output current, IOl
Operating free-air temperature. T A
125
-55
0
UNIT
70
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIH High-level input voltage
VIL Low-level input voltage
VIK Input clamp voltage
VCC-MIN,
II = -18mA
VCC=MIN,
VIH =2V,
C
C'D
~.
MIN
TVP* MAX
2
2.5
Input current at
VCC= MAX,
VI = 7V
High-level input current
VCC= MAX,
VI =2.7V
IlL
Low.. level input current
VCC- MAX,
VI = 0.4 V
lOS Short-circuit output current §
ICC SupplV current
VCC= MAX
Vce= MAX,
0.25
2.7
0.4
POL = 8 mA
IIH
maximum input voltage
3.4
3.4
6.1
V
V
V
0.25
0.4
0.35
0.5
V
0.1
0.1
mA
20
20
iJA
-0.4 mA
-100 mA
-0.4
-100 -20
-20
See Note 2
UNIT
V
0.8
-1.5
-1.5
VIL = VIL max, 10H = -400 IJA
VCC- MIN,
VIH - 2V,
IIOL=4mA
VIL = VIL max
.-
SN74LS155A
TVPt MAX
0.7
VOL Low-level output voltage
II
MIN
2
VOH High-level output voltage
-t
-t
SN54LS155A
TEST eONDITIONSt
PARAMETER
10 mA
6.1
10
(')
C'D
en
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee =' 5 V, T A""" 25°C.
~ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with outputs open, A, S, and lC inputs at 4.5 V, and 2C, lG, and 2G inputs grounded.
switching characteristics, Vee = 5 V, T A = 25°e
PARAMi:TER'1
tpLH
FROM
(INPUT)
A, B,2C,
TO
LEVELS
(OUTPUT)
OF LOGIC
y
2
1G,or2G
A, B, 2<:,
SN54LSI55A
TEST CONDITIONS
TVP
MAX
10
15
ns
v
2
CL=15pF,
19
30
ns
tpLH
AorB
V
3
17
26
ns
tpHL
Aor8
y
3
RL=2kn,
See Note 3
19
ns
tPLH
1C
V
tpHL
1C
y
3
3
30
27
27
tPHL
1G,or2G
18
18
= propagation delay time, low~to~high~level output
tPHL = propagation delay time. high~to~low-level output
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
1tPlH
2-480
UNIT
SN74LS155A
MIN
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ns
ns
SN54LS156, SN74LS156
DUAL 2·UNE TO 4·UNE DECODERS/DEMULTIPLEXERS
recommended operating conditions
SN54LSI56
Supply voltage, V CC
MIN
NOM
4.5
5
MIN
NOM
MAX
5.5
4.75
5
5.25
High-level output voltage, VOH
Low-level output current, tOl
Operating free-air temperature, T A
SN74LS156
MAX
-55
UNIT
V
V
5.5
5.5
4
8
mA
70
.,c
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
IOH
High-level output current
Low-level output voltage
VOL
Input current at
II
SN54LS156
TEST CONDITIONSt
PARAMETER
maximum input voltage
MIN
TVpj:
MAX
11--18mA
VCC - MIN,
VIH-2V,
VIL' VIL max,
VOH'5.5V
VCC'MIN.
VIH-2V,
VIL' VIL max
0.7
0.8
V
-1.5
-1.5
V
100
IIOL - 4 mA
0.25
100
0.4
IIOL' 8 mA
VCC'MAX,
VI' 7 V
UNIT
V
2
2
VCC'MIN,
SN74LS156
TVpj: MAX
MIN
0.25
0.4
0.35
0.5
0.1
0.1
~A
V
IIH
High-level input current
VCC'MAX,
VI' 2.7 V
20
20
~A
IlL
Low-level input current
VCC
MAX,
VI- 0.4 V
-0.4
-0.4
mA
ICC
Supply current
VCC- MAX,
See Note 2
10
mA
6.1
10
6.1
(I)
mA
Q)
(J
"S;
Q)
C
..J
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:t:AII typical values are at Vee::. 5 V, T A = 25°C.
NOTE 2: ICC is measured with outputs open, A. at and 1 C inputs at 4.5 V. and 2C, 1 G. and 2G inputs grounded.
l-
I-
switching characteristics, Vee = 5 V, TA = 25° C
PARAMETER§
FROM
TO
LEVELS
(INPUT)
(OUTPUT)
OF LOGIC
V
2
A,B,2C
tPLH
10,or20
A,B,2C,
tpHL
-
§tPLH
tpHL
=
=
10,or20
tPLH
Aor B
tPHL
A orB
tPLH
lC
tpHL
lC
SN54LSI56
TEST CONDITIONS
SN74LSI56
MIN
UNIT
TVP
MAX
25
40
ns
34
51
ns
31
46
34
51
ns
ns
V
2
Y
Y
3
Y
Y
3
32
48
ns
3
32
48
ns
CL'15pF,
RL' 2 kH,
See Note 3
3
propagation delay time, low-to-high-Ievel output
propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-481
2-482
SN54157. SN54LS157. SN54LS158. SN54S157. SN54S158.
SN74157. SN74LS157. SN74LS158. SN74S157. SN74S158
QUADRUPLE 2·UNE TO 1·UNE DATA SELECTORS/MULTIPLEXERS
MARCH 1974 - REVISED MARCH 1988
•
•
Buffered Inputs and Outputs
SN54157, SN54LS157, SN54S157,
SN54LS158, SN54S158 ... J OR W PACKAGE
SN74157 ... N PACKAGE
SN74LS157, SN74S157,
SN74LS158, SN74S158 ... D OR N PACKAGE
(TOP VIEWI
Three Speed/Power Ranges Available
TYPES
TYPICAL
AVERAGE
TYPICAL
PROPAGATION
'157
'LS157
TIME
9 ns
Vee
G
1A
1B
lY
2A
2B
2Y
GND
49mW
250mW
24mW
5 ns
7 ns
4 ns
'5158
AlB
150mW
9 ns
'S157
'LS158
POWER
DISSIPATION
195mW
applications
•
Expand Any Data Input Point
•
MUltiplex Dual Data Buses
•
Generate Four Functions of Two Variables
(One Variable Is Common)
•
Source Programmable Counters
4A
4B
4Y
3A
3B
3Y
SN54LS157, SN54S157, SN54LS158,
SN54S158 ... FK PACKAGE
(TOP VIEWI
ell
Q)
(.)
description
1B
These monolithic data selectors/multiplexers contain
inverters and drivers to supply full on·chip data
selection to the four output gates. A separate strobe
input is provided. A 4-bit word is selected from one
of two sour~es and is routed to the four outputs. The
'157, 'LS157, and 'S157 present true data whereas
the 'LS 158 and'S 1 58 present inverted data to
minimize propagation delay time.
FUNCTION TABLE
INPUTS
STROBE SELECT
G
A/B
H
.=
A
Il
H
X
X
X
L
L
L
L
L
H
X
5
Q)
6
C
-oJ
lI-
8
910111213
>-OU>-al
NZZ"''''
(!l
NC - No intemal connection
OUTPUTY
'157,
'LS151, '5157
L
X
'S:
4
L
H
'LS158
'5158
H
H
L
L
H
X
l.
L
H
L
H
X
H
H
L
high level, L'" low level, X '" irrelevant
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (See Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: '157, 'S158 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
'LS157, 'LS158 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range: SN54' .................................... -55°e to 125°e
SN74' ........................................ ooe to 70 0 e
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 °e to 150 0 e
NOTE 1: Voltage values are with respect to network ground terminal.
PRODUCTION DATA documents c.ntain information
current IS of publication data. Products conform to
specifications par the tarms of Tax8$ Instrumants
~~~~::~~i~ai~:1~7e ~!:::i:; l!~D:::::::t:~~S not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS. TEXAS 75265
2-483
SN54157, SN§4LS157, SN54LS158, SN54S157, SN54S158,
SN74157, SN74LS157, SN74LS158, SN74S157, SN74S158
QUADRUPLE 2-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS
logic symbols t
logic diagram (positive logic)
'167
'157, 'LS157, 'S157
lA
lB
2A
(4) 1Y
2B
2Y
28
3A (11)
3A
3Y
38 (10)
3B
4A (14)
4Y
48 (13)
4A
'158, 'LS158, '5158
121
131
151
161
1111
(101
1141
4B
SELECT AlB (1)
-I
-I
r-
1Y
o
CD
2Y
c;o
3Y
<
CD
en
4Y
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and
lEe Publication 617,12,
Pin numbers shqwn are for 0, J, N, and W packages.
schematics of inputs and outputs
'157
'157
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
VCC--_>----
INPUT
2-484
TEXAS . "
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN54LS157. SN54LS158. SN54S157. SN54S158.
SN74LS157. SN74LS158. SN74S157. SN74S158
QUADRUPLE 2·UNE TO l·UNE DATA SELECTORS/MULTIPLEXERS
schematics of inputs and outputs
logic diagrams (positive logic)
'LS157, 'LSI58
'LS157, '5157
EQUIVALENT OF EACH INPUT
121
lA--------------------------;-~
1B ....:1:.:.31'--________________-+__--1
Vc,c---_INPUT~M-~1""
lSI
2A---------------------+--~-~~
2B
161
---------------------+--~
S or G inputs: Req = 8.5 krl NOM
A or B inputs; Req =: 17 kU NOM
1111
3A'--'-------------------+--r-;
TYPICAL OF ALL OUTPUTS
3B
1101
....:....:'-------------------+~~
---~-Vcc
1141
4A---------------------+--~
CI)
OUTPUT
1131
CD
CJ
4B ---------------------t--t-,-~
'S;
STROB EG _1_l_51______~_-a::
"S;
3 2
o
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed
counting designs. The '160,'162,'LS160A,'LS162A,
and 'S162 are decade counters and the
'161,'163,'LS161A,'LS163A, and '5163 are 4-bit
binary counters. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that the
outputs change coincident with each other when so instructed by the count-enable inputs and internal gating.
This mode of operation eliminates the output counting
spikes that are normally associated with asynchronous
(ripple clock) counters, however counting spikes may
occur on the (RCO) ripple carry output. A buffered clock
input triggers the four flip-flops on the rising edge of the
Q)
(,)
Q)
2019
A
4
S
5
NC
6
QA
QS
NC
8
QC
QD
C
0
....J
lI-
9 10 11 1213
"-. ClUClI-
zw zz«Z
(!)
Ow
...J
NC-No internal connection
clock input waveform.
These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next
clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should
be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to
the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161 ,'LS160A, and 'LS161 A is asynchronous
and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162,'163,'LS162A,'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished
with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000
(LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable
and load inputs are high at or before the transition.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~at::1~1e ~!~:i~~ti:; :1~o::~:~:t::S~s
not
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-493
SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A,
SN54S162,SN54S163, SN74160 THRU SN74163,
SN74LS160A THRU SN.74LS163A, S174S162, SI74S163
SYNCHRONOUS 4·BITCOUNTERS
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating.
Instrumental in accomplishing this function are two count,enable inputs and a ripple carry output. Both count-enable inputs
(P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus
enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output.
This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-Iow-Ievel transitions at
the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T
inputs of the 'L5160A thru 'L5163A 01 '5162 and '5163 are allowed regardless of the level of the clock input.
'L5160A thru 'L5163A,'5162 and '5163 feature a fully independent clock circuit. Changes at control inputs (enable PorT, or
load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled,
disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times.
logic symbols t
'161
CUi
i:OAo
CUi
i:OAo
(15)
-I
-I
ENT
ENP
ENP
r-
ClK
C
A
B
CD
(15)
RCO
ENT
<
C
C:;"
0
RCO
ClK
(4)
(14)
(13) OA
(5)
(12)
DB
(6)
(11)
Dc
B
C
0
00
18J
CD
A
(14)
(13)
(4)
121
(5)
(12)
141
(6)
(11)
181
OA
DB
Dc
00
CI)
'162
CUi
i:OAo
Ml
ENT
G3
ENP
G4
M2
A
C
0
-13CT=9
(15)
(4)
(5)
(6)
1,50
CUi
i:OAo
Ml
ENT
G3
ENP
G4
M2
OA
A
12J
DB
B
14J
DC
C
18J
00
0
(4)
(5)
(6)
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
2-494
(15)
-13CT=15
RCO
C5/2.3.4+
ClK
(141
11J
5CT=O
RCO
C5/2,3,4+
ClK
B
'163
CTROIV16
CTROIV10
5CT=O
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
1,50
(11
12J
14J
18J
I
(141
(131
(121
(111
OA
DB
Dc
00
SN54LS160A THRU SN54LS163A, SN54S162, SN54S163,
SN74LS160A THRU SN74LS163A, SN74S162, SN74S163
SYNCHRONOUS 4·81T COUNTERS
logic symbols (continued I t
'LS161A'
'LS160A
CTROIV10
CTROIV16
ill
lOAo
ill
lOAo
(15)
ENT
ENP (7)
(2)
CLK
A
(3)
(4)
C
0
(5)
(6)
3CT: 9
(15)
RCO
ENP
CLK 12)
CS/2.3.4+
(14)
[1)
[2]
[4]
[8]
3CT:15
ENT
(13)
(12)
(11)
A
OA
13)
B 14)
DB
Dc
C
o
00
15)
16)
RCO
C5/2,3,4+
1,50
[1]
[2[
[4]
[8[
114)
(13)
112)
111)
OA
°B
Dc
00
II)
CI)
()
'S;
CI)
o
'LS162A, 'S162
CTRDIV16
5CT:O
ill
lOAo
3CT: 9
115)
115)
RCO
B
0
(4)
15)
16)
[1)
[2]
[4]
[8[
3CT:15
ENT
ENP (7)
CLK (2)
C5/2,3,4+
A
..........J
'LS163A, 'S163
114)
113)
112)
111)
A 13)
OA
B 14)
°B
C
Dc
o
00
151
16)
RCO
C5/2.3,4+
[1]
[2]
[4[
[8)
114)
113)
112)
(11)
OA
°B
Dc
DO
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and
)Ee Publication 617-12,
Pin numbers shown are for D. J, N, and W packages.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2·495
SN54160. SN54162. SN74160. SN74162
SYNCHRONOUS 4-BIT COUNTERS
logic diagram (positive logic)
SN54160. SN74160 SYNCHRONOUS DECADE COUNTERS
SN54162, SN74162 synchronous decade counters are similar;
however the clear is synchronous as shown for the SN54163,
SN74163 binary counters at right.
LOAD--~(~9)~~>---------------~r1~~____-r~
(3)
DATAA--~------II------------Jrr-~~__+l~
(13) oB
DATAB~~(~4~)-------ri--1----------t-r-~~__+hL-~
-f
,...-f
C
CD
CLK--~(~2L)--t>o--ti-~==========t=========~====~~__J
(12)
Oc
(11)
00
DATAC---(~5~)-------i-t-r1---------~[ir-~~__~L-~~~~
<
C;"
CD
en
DATAD
CLR
ENP
ENT
(6)
(1)
(7)
(15) RCO
(10)
Pin numbers shown are for 0, J, N. and W packages
2-496
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
SN54161, SN54163, SN74161, SN74163
SYNCHRONOUS 4·BIT COUNTERS
logic diagram (positive logic)
SN54163. SN74163 SYNCHRONOUS BINARY COUNTERS
SN54161, SN74161 synchronous binary counters are similar;
however, the clear is asynchronous as shown for the SN54160,
SN74160 decade counters at left.
-
(9)
DATA A
~~~
"T
(3)
;-~ ....
1
DATAB
ClK
~
(2)
".....
>-~
DATAC
(5)
~
>--'
DATAD
(6)
(1)
ENP
ENT
~
..--
IP.
...--
I
----
f-L-.. J
i---
'---c
~
(11)
CK
---K
L
}-
I
(12)
Q
I,:D >t$~
"
(13)
Q
~KCK
~
(7)
(10)
J
"~>f ~KCK
===t
-"
....
CK
~
IP. >-f f-l...J
~~
"" I
(4)
n
(14)
(15)
RCO
Pin numbers shown are for 0, J, N, and W packages.
,If
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-497
SN54LS160A, SN54LS162A, SN74LS160A, SN74LS162A .
SYNCHRONOUS 4-811 COUNTERS
logic diagram (positive logic)
SN54LSl60A, SN74LSl60A SYNCHRONOUS
DECADE COUNTERS
SN54LS162A, SN74LS162A synchronous decade
counters are similar; however the clear is synchronous
as shown for the SN54LS163A, SN74LS163A binary
counters at right.
ClK
ClR
lOAD
ENP
ENT
-I
-I
DATA A
(2)
(1)
(9)
(7)
(10)
(3)
r-
(13)
0B
(12)
Oc
o
m
<
C:;"
m
(I)
DATAC~(~5L)~~-Jr!-rt-It-----t----~
DATAD--(~6~)~-l-J~--t--tc:-~_-_-~~_i~-~_-_-_-_~
______________~
L______~=============t~~----------~(~15~1 RCO
Pin numbers shown are for D, J, N, ard W packages.
2-498
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54LS161A, SN54LS163A, SN74LS161A, SN74LS163A
SYNCHRONOUS 4·81T COUNTERS
logic diagram (positive logicl
SN54LS163A, SN74LS163A SYNCHRONOUS
BINARY COUNTERS
SN54LS161A, SN74LS161A synchronous binary
counters are similar; however, the clear is
asynchronous
as shown for the SN54LS160A,
SN74LS160A decade counters at left.
CLK~I=2)~~~------------r--------------'
LOAD ---.t"_ _
DATA A...!1~3)!....-W-l..J-t--1-t----------...J
(I)
~----------~--------~
D
Q
(13)
as
CK
II)
(,)
oS
II)
Q
0
DATAB...!I~4)!....-W-l..J~--1-t------t-----'
...I
lI(12)
Oc
CK
Q
DATAC...!I~5)!....-W-l..J~1-t1------lr-----'
~---------r------...J
(11)
00
DATAD~I~6)~~-l..J----t1-------rt-----...J
~--------------~
(15) RCO
Pin numbers shown are for 0, J, N. and W packages.
TEXAS ,..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·499
SN54S162. SN74S162
SYNCHRONOUS 4-81T COUNTERS
logic diagram (positive logic)
SN54S162, SN74S162 SYNCHRONOUS DECADE COUNTER
CLK
(2)
LOAD~(9~)------~==r-»~____- ,
cr:R(1)
DATAA~(3~)____________________~~~
DATAB
(4)
(13)
OB
-f
-f
r-
0
CD
<
Cr
CD
DATAC
(5)
(12)
Oc
(I)
DATAD~(6~)~r+----+-t---------H-~-'
ENP
(7)
ENT~(l~O~)t~~~~~__i~~
Pin numbers shown are for D, J, N. and W packages.
2-500
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
(11)
aD
(15)
RCO
SN54S163, SN74S163
SYNCHRONOUS 4·81T COUNTERS
logic diagram (positive logic)
SN54S163. SN74S163 SYNCHRONOUS DECADE COUNTER
ClK
(2)
C'["R
DATAA~~------------------~HH~
(14)
DATAB
(4)
(13)
aB
(I)
Q)
(,)
oS;
Q)
DATAC
C
(5)
(12)
DATAD~(6~)~~----+-----------4-~-'
ENP
ENT
~
ac
tt-
(11)
_21~~~~+===~~~~==================~n(1~5)L-RCO
(7)
(10)
L..----D.......
Pin numbers shown are for D, J, N. and W packages.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-501
SN54160, SN54162, SN54LS160A, SN54LS162A, SN54S162,
SN74160,SN74162, SN74LS160A, SN74LS162A, SN74S162
SYNCHRONOUS 4·811 COUNTERS
'160, '162, 'LS160A, 'LS162A, 'S162 DECADE COUNTERS
typical clear, preset, count, and inhibit sequences
Illustrated below is the following sequence:
1. Clear outputs to zero ('160 and 'LS160A are asynchronous; '162,_ 'LS162A,and '5162 are synchronous)
2. Preset to BCD seven
3. Count to eight, nine, zero, one, two, and three
4. Inhibit
CLii~
1
I
U
t:oAi)
c=
L=
c=
A....J
DATA
INPUTS
-i
-i
r-
s....J
c....J
C
-
I--
a>
D
a>
CLK
<
C:;.
en
I
--
ENP
I
ENT
1
:I
--,--j
QA_
-..!
_I
I
- -,
Qs_
-..!
OUTPUTS
1
1
1
I
1
,
1
-'_1~r :Il.-___________~
I
ac= -: ~L...-----------~---------------
-, --11
QD__ __I
RCO
I
I
:.-'---.......,
L...__________~______________________
:
I
I
:
I
I
II
11
r---1
I
IL_ _ _ _ _ _
I
I
:7
IS
9
I
I
I, I
I
-+_________________
0
2
SYNC PRESET
CLEAR
ASYNC
CLEAR
2-502
3
I...
L I · - - - - C O U N T - - - - ·.. · - - - I N H I B I T - - -....
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54161, SN54163, SN54LS161A, SN54LS163A, SN54S163,
SN74161, SN74163, SN74LS161A, SN74LS163A, SN74S163
SYNCHRONOUS 4-BIT COUNTERS
'161, 'LS161A, '163, 'LS163A, 'S163 BINARY COUNTERS
typical clear, preset, count, and inhibit sequences
Illustrated below is the following sequence:
1. Clear outputs to zero ('161 and 'LS161 A are asynchronous; '163, 'LS163A, and 'S163 are synchronous)
2. Preset to binary twelve
3. Count to thirteen, fourteen fifteen. zero. one, and two
4. Inhibit
ClR~
U
lOAD
DATA
INPUTS
A
I-I
B
1-1_-
c.J
1 1_-
D~
11_-
fI)
Q)
CJ
'S;
Q)
C
..J
lI-
ClK
ENP
,
I
:-<
ENT _ _-:-_...;.1_ _
:
1
-, -,
-
---l
_1,_---'_---'
-,
-,
QB _ _I
OUTPUTS
-
Qc _
I
,....:...1_ _ _ _ _ _ _ _ _ __
-"--7-,___---'
'--___...1 :
- , _j~
-,
'~--------,'--_ _ _...;.11_ _ _ _ _ _ _ _ __
--l
I
QD= -; :J__J
I
I
I
I
RCO
I
I
I
,
I'
SYNC
____~_____________
---_,.1.0--___
r-l~
I
:12
13
1
11....- - - - COUNT
14
15
0
2:
INHIBIT - - - -
PRESET
CLEAR
ASYNC
CLEAR
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-503
SN54160 THRU SN54163. SN74160 THRU SN74163
SYNCHRONOUS 4-81T COUNTERS
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
----..---vee
vee--------~--------
Req
INPUT
OUTPUT
-I
-I
rC
CD
<
CDi,
eLK: Req = 2,8 k!1 NOM
ENT: Aeq = 2 kfl NOM
ENP: Req=4k!1NOM
A, B,C, 0: Aeq = 6 kn NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
c;CD
en
Supply voltage, VCC (see Note 1)
Input voltage " " " ' .
Interemitter voltage (see Note 2)
Operating free·air temperature range: SN54' Circuits
SN74' Circuits
Storage temperature range
NOTES:
7V
5.5V
5.5V
-55°C to 125°C
O°C to 70°C
_65°C to 150°C
1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For these circuits, this rating applies between the count
enable inputs P and T.
recommended operating conditions
SN54160, SN54161
SN74160, SN74161
SN54162, SN54163
SN74162, SN74163 UNIT
MIN NOM MAX
MIN
Supply voltage, Vee
4.5
High-level output current, IOH
Low-level output current, IOL
5
5.5
-800
4.75
16
Clock frequency, fclock
0
25
0
5
5.25
-800
V
16
IlA
rnA
25
MHz
Width of clock pulse, tw(clock)
25
25
ns
Width of clear pulse, tw(clead
20
20
20
20
ns
20
25
20
Data inputs A, 8, e, 0
Setup time, tsu (see Figures 1 and 2)
ENP
LOAD
eLR t
0
-55
tThis applies only for '162 and '163, which have synchronous clear inputs.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
ns
25
20
20
Hold time at any input, th
Operating free-air temperature, T A
2-504
NOM MAX
0
125
0
70
ns
"e
SN54160 THRU SN54163, SN74160 THRU SN74163
SYNCHRONOUS 4·81T COUNTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High·level input voltage
VIL
Low-level input voltage
V 11<.
Input clamp voltage
VOH
High·level output voltage
TEST CONOITIONSt
Low~level
II
Input current at maximum input voltage
IlL
lOS
SN74160, SN74161
SN54162, SN54163
SN74162. SN74163 UNIT
MIN
MIN
TVP:j:
MAX
2
VOL
IIH
SN54160, SN54161
output voltage
High·level
CLK or ENT
input current
Other inputs
Low-level
CLK or ENT
input' current
Other inputs
VCC - MIN,
II =-12rnA
VCC = MIN,
VIH =2V,
VIL = 0.8 V,
10H = -800)lA
VCC=MIN,
VIH =2V,
VIL = 0.8 V,
10L = 16 rnA
2.4
0.2
VCC= MAX, VI = 5.5 V
VCC=MAX, VI=O.4V
VCC = MAX
-20
V
0.8
0.8
V
-1.5
-1.5
V
3.4
VCC= MAX, VI =2.4V
Short-circuit output current§
TVP:j: MAX
2
2.4
3.4
0.2
0.4
V
0.4
1
1
80
80
40
40
-3.2
-3.2
-1.6
-1.6
-57
-18
V
rnA
)lA
rnA
-57
rnA
ICCH Supply current, all outputs high
VCC= MAX, See Note 3
59
85
59
94
rnA
ICCL Supply current, all outputs low
VCC= MAX, See Note 4
63
91
63
101
rnA
tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
fAil typical values are at Vee = 5 V. T A = 25°C.
§Not more than one output should be shorted at a time.
NOTES: 3. 'CCH is measured with the load input high, then again with the load input low, with all other inputs high and all outputs open.
4. ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open,
switching characteristics, Vee = 5 V, T A = 25°e
FROM
(INPUT)
(OUTPUT)
CLK
RCO
tPLH
ClK
Any
CL
tpHL
(LOAD input high)
Q
RL
tPLH
ClK
Any
tpHL
(LOAD input low)
Q
ENT
RCO
CLR
AnyQ
PARAMETER1
TO
TEST CONDITIONS
f max
tpLH
tpHL
tpLH
tPHL
tpHL
MIN
TVP
25
32
MAX UNIT
MHz
23
35
23
35
13
20
15
23
See Figures 1 and 2
17
25
and Note 5
19
29
11
16
= 15 pF,
= 4002,
11
16
26
38
ns
ns
ns
ns
ns
,fmax = Maximum clock frequency
tPLH = propagation delay time, low·to·high·level output
tpHL = propagation delay time, high-to-Iow-ievel output
NOTE 5: Propagation delay for clearing is measured from the clear input for the' 160 and' 161 or from the clock input transition for the.'162 and '163.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-505
SN54LS160A THRU SN54LS163A, SN74LS160A THRU SN74LS163A
SYNCHRONOUS.4·8IT COUNTERS
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
--....................~... VCC
VCC--............~~........120 !l.NOM
INPUT ........-MI-. .~J-....
' -....~~- OUTPUT
Data: Req
= 25 k!l
NOM
CLK,ENT,[QAB: Req = 10 k!l NOM
ENP: Req = 20 k!l NOM
CLR ('LSI60A, 'LSI61A): Req = 20 k!l NOM
C'[R ('LSI62A, 'LSI63A): Req = 10 k!l NOM
-t
-t
rC
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
CD
Supply voltage, VCC (see Note 7)
....... .
Input voltage . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS' Circuits
SN74LS' Circuits
Storage temperature range
<
ci'
CD
UI
7V
7V
.-55°C to 125°C
OOC to 70°C
.~65°C to 150°C
NOTE 7: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS'
Vce
Supply voltage
10H
High-level output current
10L
low-level output current
fclock
Clock frequency
UNIT
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-400
8
IlA
mA
25
MHz
-400
4
0
25
0
tw(clockl Width of clock pulse
25
25
ns
tw(clear) Width of clear pulse
20
20
ns
Data inputs A, B, C. D
20
20
ENP or ENT
20
20
LOAD
20
20
LOAD inactive state
20
20
CLR t
20
20
CLR inactive state
25
25
tsu
t
SN74LS'
MIN
Setup time, (see Figures 1 and 2)
th
Hold time at any input
TA
Operating free-air temperature
This applies onlv for 'L.S162 and 'LS163. which have synchronous clear inputs.
2-506
TEXAS •
INSTRUMENTS
POST OFFiCe BOX 655012 • DALLAS, TeXAS 76265
ns
3
3
-55
ns
125
0
70
'e
SN54LS160A THRU SN54LS163A, SN74LS160A THRU SN74LS163A
SYNCHRONOUS 4-81T COUNTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
I nput clamp voltage
SN54LS'
TEST CONDITIONSt
PARAMETER
MIN
TYPj:
2
VOH High-level output voltage
VCC- MIN,
II - -18 mA
Vce- MIN,
VIH-2V,
2.5
VIL = VIL max, 10H = -400 "A
Vee= MIN,
at maximum
II
input voltage
IIH
CLR ('LS160A, 'LS161A)
VCC= MAX.
-1.5
-1.5
2.7
0.4
VI = 7 V
CLR ('LS162A. 'LS163A)
3.4
0.25
0.4
0.35
0.5
0.1
0.1
0.2
0.2
0.1
0.1
0.2
0.2
20
20
LOAD, CLK, or ENT
40
40
input current
CLR ('LS160A, 'LS161A)
input current
VI = 2.7V
20
20
40
40
Data or ENP
-0.4
-0.4
LOAD, CLK, or ENT
-0.8
-0.8
CLR ('LS160A, 'LS161A)
VCC= MAX,
VI = 0.4 V
CLR ('LS162A, 'LS163A)
Short-circuit output current§
-20
VCC = MAX
V
V
V
Data or ENP
Vce= MAX,
UNIT
V
0.8
High-level
Low-level
lOS
MAX
V
CLR ('LS162A, 'LS163A)
IlL
TYPj:
0.7
3.4
Data or ENP
LOAD, eLK, or ENT
MIN
2
0.25
IIOL = 4 mA
VIH = 2V,
VIL = VILmax IIOL = 8 mA
VOL Low-level output voltage
I nput current
SN74LS'
MAX
-0.4
-0.4
-0.8
-0.8
-100
-20
-100
mA
"A
en
mA
'S;
Q)
mA
o
...J
ICCH Supply current, all outputs high
Vce - MAX,
See Note 3
18
31
18
31
mA
leel
Vee- MAX,
See Note 4
19
32
19
32
mA
Supply current, all outputs low
Q)
(J
lI-
tFor conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee"" 5 V, T A = 25°C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTES: 3. ICCH is measured with the load input high, then again with the load input low, with all other inputs high and all outputs open.
4. leeL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open.
switching characteristics, Vee = 5 V, T A = 25° C
PARAMETER~
FROM
TO
!INPUT)
(OUTPUT)
CLK
RCO
TEST CONDITIONS
f max
tPLH
tpHL
tpLH
CLK
Any
tpHL
(LOAD input high)
Q
tpLH
CLK
Any
tpHL
(LOAD input low)
Q
tpLH
tpHL
tpHL
CL=15pF,
RL = 2 kll,
See fjgures
1 and 2 and
Note 8
ENT
RCO
eLR
AnyQ
MIN
TYP
25
32
MAX
UNIT
MHz
20
35
18
35
13
24
18
27
13
24
18
27
9
14
9
14
20
28
ns
ns
ns
ns
ns
,fmax = Maximum clock frequency
tpLH = propagation delay time, low-to-high-Ievel output.
tpHL = propagation delay time, high-to-Iow-level output.
NOTE 8:
Propagation delay for clearing is measured from the clear input for the 'LS160A and 'LS161A or from the clock transition for the 'LS162A and
'lS163A.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-507
SN54S162. SN54S163. SN14S162. SN14S163
.SYNCHRONOUS 4-81T COUNTERS
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
----------~~---VCC
,
VCC~~----__- - - - - - -
50n NOM
!
20 kn NOM
(OPfN FOR CLOCK ~
AND DATA INPUTSI,
I
INPUT-. . . . .- '
OUTPUT
=
ENP or ENT inputs: Req
1.9 kn NOM
eLK and Data inputs: Req == 2.8 kn NOM
Other inputs; Req = 3.5 kn NOM
-t
~
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
.Input voltage . . . . . . . .
Interemitter voltage (see Note 2)
Operating free·air temperature range: SN54S162, SN54S163 (see' Nate 10)
SN74S162,SN74S163
Storage temperature range
o
CD
<
CiCD
en
7V
5.5 V
5.5 V
-55°C ta 125°C
O°C ta 70"C
-65"C ta 150"C
recommended operating conditions
Supply voltage,
SN54S162, SN54S163
SN74S162, SN74S163
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
-1
4.75
5
5.25
-1
Vee
High-level output current, IOH
20
Low-level output current, IOL
0
Clock frequency. fclock
0
V
mA
20
mA
40
MHz
Width of clock pulse, tw{clock) (high or low)
10
10
ns
Width of clEJar pulse, tw(clearl
10
10
ns
4
12
4
12
CLR
14
14
14
14
LOAD inactive-state
12
12
CLR inactive-state
12
Data inputs, A, 8, C, D
ENP or ENT
LOAD
Setup tlrne, Isu (sec F igurc 4)
Release time, treleasp. (see Figure 4)
Hold time, th(sce Figure 4)
LOAD
CLR
Operating frecoair tempt)rature. T A bee Note 10)
NOTES:
3
0
0
.. ·55
ns
12
4
4
ENP or ENT
Data inputs A, B, C, D
ns
3
0
ns
0
125
0
70
C
1. Voltage values, except tnteremitter voltage. are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple emitter transistor. For these circuits, this rating applies between the count
enable inpu ts P and T.
10. An SN54S162 or SN54S163 in the W packagoJ operating
See Figures 1, 3, and 4
MIN
TYP
40
70
MAX
UNIT
MHz
14
25
17
25
8
15
10
15
10
15
10
15
C
-I
lI-
ns
ns
ns
~Ifmax ==maxlmum clock frequency
tpLH == propagation delay time, low-to high·level output
tpH L
~
propagation delay time, high-to low level output
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-509
SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A,
SN54S162, SN54S163, SN74160 THRU SN74163,
SN74LS160A THRU SN74LS163A, SN74S162, SN74S163
SYNCHRONOUS 4·811 COUNTERS
PARAMETER MEASUREMENT INFORMATION
I.-'w(clockl..l
I
1
3V
1
CLK
INPUT
~tPLH
I
(measure at tn+11
L..---.:-I
I
1
I
OUTPUT
oA _ _ _""--'
tpH L
(measure at tn+21
1
\LVrel
V reI
~:::
/
ySr---J.
1
----.l- tpLH
J.....-.-i- tpHL
I
I (measure at t n+4) I
I
I
I
~\-S_ _:---Jl~el
OUTPUT
oB
-I
-I
r-
~'PHL
C
CD
~.
()
CD
en
(measure at t n+2)
I
:
VOH
___
_
-
I
(measure at tn+81
OU6~UT---7---------~~~S~
__
I
____
~ tPLH
(measure at t n +10
I
I
(measure at tn+81
I
VOH
_ _ _ _ _ _ _ VOL
(measure at tn+10
or t n +161 (See Note BI
l,.v-re-I------..~~
RCO _ _ _ _ _
VOL
1'-1--1-0
tPHL
I
:
-
or tn+161
·~s. .____-,lV~1
aD
-
""10---1-1-tPLH
' \ . v(::e Note BI
OUTPUT
VOL
__
-
I
-
(measure at t n +4)
~;_J~V~1
o l-l-tPHL
1f4--_
I
-
~tPLH
-
-
-
-
-
-
--
-
-
VOH
-
VOLTAGE WAVEFORMS
NOTES:
A. The input pulses are supplied by a genel"8tor having the following characteristics: PRR 0;;;; 1 MHz, duty cycle':;;'; 50%, Zout A:I 50 n;
for '160 thru '163, 1: r ':;;';10n5, 1f':;;'; 10ns;for'LS160Athru'LS163A}:r ~ 15n5,1f"":;; 6ns;and for '5162, '5163, 1:r<2.5n5,
1f '" 2.5 ns. Vary PRR to measure f max ·
B. Outputs QO and carry are tested at 1:n+10 for'160,'162,'LS160A,'LS162A,and'S162, and at t n +16 for '161, '163,'LS161A,
'LS163A, and 'S163, where tn is the bit time when all outputs are low.
C. For '160 thru '163, '5162, and '5163, Vref.= 1.5 V; for 'LS160A thru 'LS163A, Vref = 1.3 V.
FIGURE l-SWITCHING TIMES
2-510
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A,
SN74160 THRU SN74163, SN74LS160A, THRU SN74LS163A
SYNCHRONOUS 4·81T COUNTERS
PARAMETER MEASUREMENT INFORMATION
-_-_-_-_-_-_-_-_--_-_-_-_-_-_--
~~~: I:~~~i~-~------------"""\"'
t"-~-I
3V
OV
,-'wlcIOck).-.i
I
CLR
INPUT
-\:_l: __ nnju_
-'wlcle.ri-'
I I
___~----------\I
,-
,
su
'
i
1
I.-
OV
_____
U~'~
LOAD
INPUT
3V
tsu --:
3V
n
_ _ _
u
__
~:---------------
DATA INPUTS
OV
3V
A, S, C, .nd D
---_~'I-t-PH-L-:-I+-I-------..J
~f;~¥~~kUTPUTS i \ . .
I
V_re_I_ _ _ _ _....;..._ _ _ _ _
-J/~r: __________ _
VOH
In
Q)
0
VOL
I.
tPLH (measure at tn+2 or t n +4)
.'
: ,)C~~~~~-_~-_-_-~~~
\"
and Oc OUTPUTS
'160, 'LS160A
~------------------------
1
:..!
~ tpH L l.-
as
OV
_ I tPLH l+-
VOH
...J
VOL
3V
ENP or
ENT
Vref
OV
tPLH+--,
I-..I--'PHL
lC-i-\~,---
___~---------~-----.;...--------1
~~~, 1'~~~;2;---\
\1.'\
J:
Ii V
RCa
1- 'su
I
VIIV rei
'163, 'lS163;
\
' - -____..J
~
Vrel
I
-I
I
-I -
~
-
-
-
-
-
-
-
-
-
-
-
--I 'PH L :-~_ _ _ _ _ _-:":._J.: - ;;L;:;- (';'.;;;re-;;, ;;;+;'r ~+~
'162, 'LS162A
i '\
- , 'PLH
Vrel
-
-
- - OV
~r---------------
0A and 0D OUTPUTS
'162, 'LS162A
Os and Oc OUTPUTS
VOL
3V
°'163,
OUTPUTS
'LS163A
'PHL
VOH
V r e l i ' l rei
---j
VOH
IVrel
-
-
-
-
Ir-----------
~,
;t~r: _ _ _ _ _ _ _ _ _ _ _ _
\Vrel
VOL
VOH
VOL
VOLTAGE WAVEFORMS
NOTES:
A. The input pulses are supplied by generators having the following characteristics: PRR ~ 1 MHz, duty cycle ~ 50%, Zout
R::
50
n;
for "60 thru "63, tr";;; 10 ns, tf'-:;; 10 ns; and for 'LS160A thru 'LS163A, tr ,;;;; 15 ns, tf .,;;: 6 ns.
B. Enable P and enable T setup times are measured at tn+OC. For ',60 thru '163, Vref = 1.5 V; for 'LS160A thru 'LS163A. Vref
=
1.3 V.
FIGURE 2-SWITCHING TIMES
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
>
Q)
C
2-511
~
~
8N548162. 8N548163. 8N748162. 8N748163
8YNCHRONOU8 4·811 COUNTER8
PARAMETER MEASUREMENT INFORMATION
-I"
ENT
INPUT
~::---------::
I
I-- tpH l ---t
I
I+--
tPlH ~
I
I
I
_______-.J!1.5
RCO
\1.~---VOH
V
1....----VOl
VOL TAGE WAVEFORMS
NOTES:
A. The input pulse is supplied by a generator having the following charactenstics: tr '", 2.5 ns, If~: 2.5 ns, PRR'
cycle
<{
50%, Zout
'>::
1 MH1, duly
50 H.
B. tpLH and tpHL from enable T Input to carry output assume that the counter is at the maximum count (QA and Q D hl~Jh for
'5162, all Q outputs high for '5163).
FIGURE 3-PROPAGATION DELAY TIMES FROM ENABLE T INPUT TO CARRY OUTPUT
I-- twiclock).-,
-t
-t
r-
C
ClK
INPUT
r-- twiclock) --I
I
I
I
I
I
I
I
'-----1
I
I
CD
~.
J+- tsu
th
I (active state) J.-
n
CD
~"
(II
ClR
INPUT
I
I+----
3V
1.5 V
"!"---OV
I
I--- tsu ~
---+J
(inactive statel
:
I
:
3V
jl
,
tw(elearl
I
1.5V
I
T----l
:--
I
1
I
I
- - i - - - - - - - - - i - - - OV
tsu - ,
t----:- tsu ~
r·
I (active ,state) .... th ~
I
I
I
lOAD
\.5V
(mactlve state)
5V
I
3V
:
1.
...._ _ _-:-_J.
_ _ _ _ _ _ _ _ _ _ _ _ _ ov
INPUT
l-
tsu
--I
I.
I
DATAINPUTS_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
A. B. C, and D
J-~."
T'
-I
I
I
I
th
-------.J---- 3V
!
\1.5 V
OV
I---
tsu
I
ENPor
ENT
--______________________________
--J~-"
VOL TAGE WAVEFORMS
NOTE
A: The input pulses are supplied by generators having the following characteristics: t r · 2.5 ns, t f '
cycle.: 50%, Zout ~ 50
!l.
FIGURE 4-PULSE WIDTHS, SETUP TIMES. HOLD TIMES, AND RELEASE TIME
2-512
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2.5 ns, PRR'
1 MHl, duty
SN54160 THRU SN54163. SN54LS160A THRU SN54LS163A.
SN54S162. SN54S163. SN74160 THRU SN74163.
SN74LS160A THRU SN74LS163A. SN74S162. SN74S163
SYNCHRONOUS 4·81T COUNTERS
TYPICAL APPLICATION DATA
This application demonstrates how the ripple mode carry circuit (Figure 11 and the carry~look~ahead circuit (Figure 21 can be
used to implement a high~speed N~bit counter. The '160, '162, 'L5160A, 'L5162A, or '5162 will count in BCD and the '161,
'163, 'L5161 A, 'L5163A, or '5163 will count in binary. When additional stages are added the fMAX decreases in Figure 1,
but remains unchanged in Figure 2.
N~BIT
LD
ABC
D
SYNCHRONOUS COUNTERS
INPUTS
INPUTS
INPUTS
,...--J'----..
~
~
LD A B C
0
LD A B C
0
LD
ABC
0
So,
Note 1
H - COUNT
L
DISABLE
EN P
H
L
COUNT
DISABLE
EN T
EN P
EN P
RCa
EN T
RCa
EN P
RCa
EN T
EN T
RCa
TO MORE
II)
SIGNIFICANT
STAGES
CK
CK
CK
Q)
(J
.S;
CK
Q)
o
....J
CLR---r--~~~~~-----r--'-+-+-+-~--+---~-r-r-r~---+--~
l-
IOUTPUTS
OUTPUTS
OUTPUTS
OUTPUTS
CLK--~----------------~--------------'---------------~--~----------~
fMAX ~ l/lCLK'oRCO'PLHI + IENT'oRCOtpLHIIN-21 + (ENTtsul
FIGURE 1
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2~513
SN54160 THRU S,N54163, SN54LS160A THRU SN54LS163A,
SN54S162, SN54S163, SN74160 THRU SN74163,
SN74LS160A THRU SN74LS163A, SN74S162. SN74S163
SYNCHRONOUS 4·BITCOUNTERS
TYPICAL APPLICATION DATA
INPUTS
INPUTS
~
~
INPUTS
~
LD A B C
0
LD A B C
0
LD A B C
0
LDABCD
EN P
H.= COUNT
L" DISABLE
EN T
EN P
EN P
RCO
RCO
EN T
CK
CK
EN P
ENT
RCO
ENT
RCO
CK
CK
CLR
-f
-f
rC
OUTPUTS
OUTPUTS
OUTPUTS
CLK
CD
<
n'
CD
'MAX
~
l/(CLK to RCO tPLHl + (ENP tsul
FIGURE 2
UI
2-514
See
Note 1
H = COUNT
L'" DISABLE
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
OUTPUTS
TO MORE·
SIGNIFICANT
STAGES
SN54164. SN54LS164. SN74164. SN74LS164
8·BIT PARALLEL·OUT SERIAL SHIFT REGISTERS
MARCH 1974 - REVISED MARCH 1988
• Gated Serial Inputs
SN54164, SN54LS164 ... J OR W PACKAGE
SN74164 ... N PACKAGE'
SN74LS164 ... D OR N PACKAGE
(TOP VIEW)
• Fully Buffered Clock and Serial Inputs
• Asynchronous Clear
TYPE
'164
'LS164
TYPICAL
MAXIMUM
CLOCK FREQUENCY
36 MHz
36 MHz
TYPICAL
POWER DISSIPATION
A
VCC
OH
B
21 mW per bit
OA
10 mW per bit
°B
OF
Oc
QL
00
ClR
ClK
description
°G
GNO
These 8-bit shift registers feature gated serial inputs and
an asynchronous clear. The gated serial inputs (A and
B) permit complete control over incoming data as a low
at either input inhibits entry of the new data and resets
the first flip-flop to the low level at the next clock pulse.
SN54LS164 ... FK PACKAGE
(TOP VIEW)
A high-level input enables the other input which will
then determine the state of the first flip-flop. Data at the
serial inputs may be changed while the clock is high or
low, but only information meeting the setup-time requirements will be entered. Clocking occurs on the lowto-high-Ievel transition of the clock input. All inputs are
diode-clamped to minimize transmission-line effects.
U
u
U ,:I:
alO
The SN54164 and SN54lS164 are characterized for
operation over the full military temperature range of
- 55 DC to 125 DC. The SN74164 and SN74LS164 are
characterized for operation from O°C to 70°C.
NC - No intE'1rnal connection
FUNCTION TABLE
INPUTS
OUTPUTS
CLEAR CLOCK A
B
QA
QB ... QH
X
X
L
L
L
L
X
H
L
X
X
QAO QBO
QHO
H
!
H
H
H
QAn
QGn
L
X
H
!
L
QAn
QGn
H
t
X
L
L
QAn
QGn
H = high level (steady state), L =: low level (steady state)
X = irrelevant (any input, including transitions)
t = transition from low to high leveL
DAD. OeD. aHO "" the level of QA. 0B; or QH. respectively, before the indicated
QAn. QGn
=
steady-state input conditions were established.
the level of OA or 0G before the most-recent t transition of the
clock; indicates a one-bit shift.
schematics of inputs and outputs
'LS164
'164
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
-~--VCC
VCC(
5--4-kO
Req
INPUT
EQUIVALENT OF EACH INPUT
VCC
R - 2000
NOM
NOM
-OUTPUT
l
_n
'''~d-
TYPICAL OF ALL OUTPUTS
---~--VCC
OUTPUT
Clear. clock: 17 k!1 NOM
Serial in: 25 k!1 NOM
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-515
SN54164, SN54LS164, SN74164, SN74LS164
8·BIT PARALLEL·OUT SERIAL SHIFT REGISTERS
typical clear, shift, and clear sequences
u
mAR---U
L-Jl~
SERIAL {
INPUTS
A
B_~
________~________
_ _ _ _..J
CLOCK
--"',
---,
---,
QA ___
.~
________
QB ___
.~I~
QC ___
~I
~
_________
~
~~------~-------
~~----~-------~L_ _~_______ _
_ _ _ _ _ _ _ _ _ _ _ _..J
QD==-.~JL-
___________~
~L-~_ _ _ _ _ __
I
OUTPUTS
----,
I
QE ___ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~I
LnL-______
~
-I
-I
r-
OF ----,
___ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-...I
o
ell
QG ___
n'
ell
QH ___ I
~I
---,
~I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-J
I
---...1.,______________________________~!l,' ___________
<
I
en
CLEAR
CLEAR
logic symbol t
°A
Os
(6)
(10)
(11)
(12)
(13)
Qc
°D
°e
OF
°G
°H
tThis symbol is in accordance with ANSI/IEEE Std. 91·1984 and lEe Publication 617-12.
Pin numbers shown are for D. J. N. and W packages.
2-516
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SN54164, SN54LS164, SN74164, SN74LS164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
logic diagram (positive logic)
M
>~
Q.
:I:
>-0
~
0
~
>-
~Cl
>-0
~
0
-
>~
Q.
II.
>-0
~
0
~
>-
~
Q.
Ell
W
>-0
~
0
§
VI
>~
Q.
Q)
0
CJ
>-0
-S;
~
0
Q)
C
-
"'
__
-_
>-
..J
~ U
Q.
lI-
>-0
~
o
....- - -~- 5~
~~
r-~--~~
§
>-
~
Q.
«
>-0
~
0
~
w
f
"-
;::
]
z
-;
ci
.e
w
'"c
~
0
-;;
i!!
w
.c
E
~
c
c
0::
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-517
SN54164, SN74164
8·BIT PARALLEl·OUT SERIAL SHIFT REGISTERS
absolute maximum ratings over oprating free-air temperature range (unless otherwise notedl
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54164.......................... - 55 °e to 125°e
SN74164 ............................. OOet070oe
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54164
Supply voltage, V cc
SN74164
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-400
p.A
-400
High-level output current, IOH
0
Clock frequency, f clock
r-
C
25
rnA
MHz
20
20
ns
Data setup time, tsu (see Figure 1)
15
15
ns
Data setup time, tsu (Clear Inactive) (see Figure 1)
20
20
ns
5
5
Data hold time, th (see Figure 1)
Operating free-air temperature. T A
-55
125
ns
0
70
·C
electrical characteristics over recommended operating free-air temperature range (unless otherwise notedl
~.
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH High-level output voltage
VOL Low-level output voltage
SN54164
TEST eONDITloNst
PARAMETER
(')
CD
0
Width of clock or clear input pulse, tw
CD
(II
8
25
8
Low-level output current, IOL
~
~
UNIT
MIN
SN74164
TVP* MAX
MIN
11"-12rnA
VCC - MIN.
VIH"2V,
VIL" O.B V,
10H" -400 pA
Vec- MIN,
VIH-2V,
VIL" O.B V,
10L"BmA
TVP*
MAX
O.B
O.B
V
-1.5
-1.5
V
3.2
2.4
UNIT
V
2
2
VeC" MIN.
MIN
2.4
0.2
0.2
0.4
V
3.2
0.4
1
1
V
mA
II
Input current at maximum input voltage
Vec - MAX, VI - 5.5 V,
IIH
High-level input current
VCC- MAX, VI"2.4V
40
40
pA
IlL
Low-level input current
Vec - MAX, VI-O.4V
-1.6
-1.6
rnA
lOS
Short-circuit output current ~
VCC" MAX
-27.5
mA
ICC
Supply current
-10
VCC - MAX, I VI(clock) - 0.4 V
See Note 2
I VI(clock) -
2.4 V
-27.5
-9
30
37
30
54
37
54
rnA
t For conditions shown at MIN or MAX, use the appropriate value specified under recommended operating conditions.
t: All
typical values are at VCC "" 5 V, T A == 25°C.
§ Not more than two outputs should be shorted at a time.
NOTE 2: ICC is measured with outputs open, serial inputs grounded, and a momentary ground, then 4.5 V, applied to clear.
switching characteristics, Vee = 5 V, T A = 25° e
PARAMETER
TEST CONDITIONS
CL=15pF
f max Maximum clock frequency
tpHL
2-518
36
MAX
36
2B
42
B
17
27
CL - 50pF
10
20
30
Propagation delay time, high-to-Iow-Ievel
CL = 15pF
10
21
32
Q outputs from the clock input
CL - 50 pF
10
25
37
Q outputs from clock input
CL" 50pF
RL"BOOn,
See Figure 1
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
MHz
24
CL" 15 pF
Q outputs from clear input
Propagation delay time, low-to-high-Ievel
tPLH
TVP
25
CL - 15pF
Propagation delay time, high-to-Iow-Ievel
tPHL
MIN
ns
ns
ns
SN54LS164. SN74LS164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............. .
Input voltage ..
Operating free-air temperature range: SN54LS 164 ..
SN74LS164 .
Storage temperature range ..
7V
7 V
-55°e to 125°e
. .. ooe to 70 0 e
- 65 °e to 150 °e
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS164
Vee
Supply voltage
V,H
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
SN74LS164
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
2
UNIT
V
V
0.7
0.8
-- 0.4
- 0.4
V
mA
8
mA
25
MHz
IOL
Low-level output current
fclock
Clock frequency
tw
Width of clock or clear input pulse
20
20
ns
tsu
Data setup time (See Figure 1)
15
15
ns
tsu
Clear inactive setup time (See Figure 1)
Data hold time (See Figure 1)
20
5
ns
th
20
5
TA
Operating free-air temperature
4
0
25
- 55
0
Q)
.s:
(.)
ns
0
125
CJ)
70
°e
Q)
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
V,K
Vee ~ MIN.
~
Vee
VOH
MIN,
"
~
V,H
MIN
~
~
V,L
MIN,
V,H
~
2 V,
~
SN74LS164
MAX
MIN
V,L
~
MAX,
2.5
I'OL ~ 4 mA
2 V,
2.7
3.5
0.25
~
0.4
7 V
"
I'H
Vee
~
MAX,
V,
~
2.7 V
',L
Vee
~
MAX.
V,
~
0.4 V
lOS
Vee
~
MAX
ICC
Vee
~
MAX,
MAX
-1.5
IIOL ~ 8 mA
V,
TYP*
-1.5
MAX
Vee ~ MAX.
TYP*
-18 mA
IOH ~ -0.4 mA
Vee
VOL
SN54LS164
TEST CONDITIONSt
3.5
0.25
0.4
0.35
0.5
-20
-100
See Note 3
16
-20
27
lI-
V
V
0.1
mA
-0.4
mA
-100
mA
27
mA
~A
20
-0.4
...J
V
0.1
20
UNIT
C
16
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
"All typical values are at Vee ~ 5 V, TA ~ 25°C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 3: ICC is measured with outputs open, serial inputs grounded, the clock input at 2.4 V, and a momentary ground, then 4.5 V applied
to clear.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
TEST CONDITIONS
f max Maximum dock frequency
Propagation delay time, high-to·low-Ievel Q outputs from clear
tpHL
input
Propagation delay time, low-to-high-Ievel Q outputs from clock
tPLH
input
RL
~
2 kl1.
eL~15pF,
See Figure 1
Propagation delay time, high-to-Iow-Ievel Q outputs from clock
tpHL
input
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
TYP
25
36
MAX
UNIT
MHz
24
36
ns
17
27
ns
21
32
ns
2-519
SN54164. SN54LS164. SN74164. SN74LS164
8·BIT PARALLEL.QUT SERIAL SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION
AANDB
PULSE
OUTPUT
VCC
GENERATOR
A
B
CLOCK
PULSE
GENERATOR
CLOCK
{See Note CI
I
CLEAR
PULSE
GENERATOR
CL
{See Note BJ
TEST CIRCUIT
-t
-t
rC
CD
<
twtclear)
CLEAR
PULSE
GENERATOR
IPRR" 1 MHz}
----t-- \~:~~iVe) -----1
I r---------~------------~S-----------------------------3V
I
I
tsu
1
I _1_
I..-- 'wlclock} -.t
'---_..1.-- _
n'
CD
CIl
I
I
I
I
I
CLOCK
PULSE
GENERATOR
IPRR'; 1 MHz}
-- --
-
- - - - - - -------oV
,.----- 3V
I
Vref
I
I
-: I-'h
3V
~-~II
SERIAL INPUTS
A AND B PULSE
GENERATOR
IPRR" MHz}
-t
II
I
1
-I
--I
'PLH
~'PHLt-
~--jj.fr-------~~ ,~
QAOUTPUT
(See Note D)
VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: duty cycle .:S 50%, Zout::::: 500; for '164, tr:s: 10 ns, tf :s 10 ns; and for
B.
C.
D.
E.
F.
'LS 164, Ir " 15 ns, If " 6 ns.
CL includes probe and jig capacitance.
All diodes are 1N3064 or equivalent.
QA output is illustrated. Relationship of serial input A and B data to other Q outputs is illustrated in the typical shift sequence.
Outputs are set to the high level prior to the measurement of tpHl from the clear input.
For '164, Vref = 1.5 V; for 'LS164, Vref = 1.3 V.
FIGURE I-SWITCHING TIMES
2·520
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
OCTOBER 1976 - REVISED MARCH 198B
SN54165. SN54LS165A ... J OR W PACKAGE
SN74165 ... N PACKAGE
SN74LS165A ... D OR N PACKAGE
(TOP VIEW)
• Complementary Outputs
• Direct Overriding Load (Datal Inputs
• Gated Clock Inputs
SH/lO
ClK
E
F
G
H
• Parallel-to-Serial Data Conversion
TYPICAL MAXIMUM
CLOCK FREQUENCY
TYPICAL
POWER DISSIPATION
'165
26 MHz
210 mW
'LSI65A
35 MHz
90 mW
TYPE
VCC
ClKINH
0
C
B
A
SER
QH
QH
GNO
description
The '165 and 'lS 165A are 8-bit serial shift registers that
shift the data in the direction of QA toward QH when
clocked. Parallel-in access to each stage is made
available by eight individual direct data inputs that are
enabled by a low level at the shiftlload input. These
registers also feature gated clock inputs and complementary outputs from the eighth bit. All inputs are
diode-clamped to minimize transmission-line effects,
thereby simplifying system design.
Clocking is accomplished through a 2-input positiveNOR gate, permitting one input to be used as a clockinhibit function. Holding either of the clock inputs high
inhibits clocking and holding either clock input low with
the shift/load input high enables the other clock input.
The clock-inhibit input should be changed to the high
level only while the clock input is high. Parallel loading is
inhibited as long as the shift/load input is high. Data at
the parallel inputs are loaded directly into the register
while the shift/load input is low independently of the
levels of the clock, clock inhibit, or serial inputs.
SN54lS165A ... FK PACKAGE
(TOP VIEW)
J:
19
~
U::w:::
.JJ:uu
.J
::w::: -
U(/)z>u
3
2
U)
CI)
1
E
4
o
F
NC
5
6
C
NC
G
7
B
H
B
CJ
-S;
CI)
o
...J
....
....
A
9 10111213
J:CU J:a:
10
t§
Z 0
m
logic symbol t
SRGB
SH/j]j
(15)
ClK INH
ClK (2)
FUNCTION TABLE
INPUTS
INTERNAL
SHIFT!
CLOCK
LOAD
INHIBIT
L
x
X
x
, ... h
H
L
L
X
X
H
L
CLOCK SERIAL
t
H
PARALLEL
A ... H
X
OUTPUTS
aA
SER (10)
AlII)
aH
,
aB
b
h
aAO
H
aBO
DAn
DAn
DBO
aHO
DGn
DGn
DHO
H
L
t
L
X
L
H
H
X
X
X
DAD
C2/ ....
OUTPUT
B (12)
C (131
o
10
10
(14)
(31
(41
G
151
H (6)
10
tThis symbol is in accordance with ANSI/IEEE Std. 91·1984 and lEe
Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
PRODUCTION DATA documents contain information
curreot as of publication date. Products conform to
specifications per the terms of Texas Instruments
:~~~~:~~i~a{::I~tle ~!::i~~ti:r ~~o:::::::9t::s~S not
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-521
SN54165. SN54LS165A. SN74165. SN74S165A
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
schematics of inputs and outputs
'165
EQUIVALENT OF EACH INPUT
TYPICAL OF BOTH OUTPUTS
VCC
VCC
INPUT
OUTPUT
Shift/load: Req ~ 3 kQ NOM
Other inputs: Req ~ 6 kQ NOM
'LS165A
-I
-I
rC
CD
<
Cr
CD
EQUIVALENT OF PARALLEL INPUTS
AND SERIAL INPUT
EQUIVALENT OF ALL OTHER INPUTS
TYPICAL OF BOTH OUTPUTS
------~-VCC
120 QNOM
VCC--_-24kQ
NOM
INPUT
(II
INPUT'-e...f.lll-+-_
L-.--+-OUTPUT
Oock, Clock inhibit; Req ~ 10 kQ NOM
Shift/load; Req ~ 13 kQ NOM
2-522
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL· LOAD 8·BIT SHIFT REGISTERS
logic diagram (positive logic)
"
I/)
Q)
CJ
'>
Q)
w
o
-I
lI-
"C
C
~
;i
-;
ci
"-Z 'U"
'"
.J
.J
0::
W
'"
U
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-523
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
typical shift, load, and inhibit sequences
CLOCK
CLOCK INHIBIT
SERIALINPUT ______
~L________~---------------------------------------------
SHIFT/LciAD~
I
I
A ~~______~_________________________________________
B
I
L
I
C
D
I
~~
______~____________________________________________
I L
I
DATA
I
E~~______L-_________________________________________
F
-I
-I
I L
I
I
r-
G ~L_______~__________________________________________
C
I
CD
H~L-______~__________________________________________
<
n'
CD
I
o
OUTPUTOH
I
I
OUTPUTOH
I--
H
H
L
L
I
INHIBIT
--11. .----------
SERIAL SHIFT - - - - - - - - - - - - - - - - - -
LOAD
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V CC (see Note 1) ................................................................ 7 V
Input voltage: SN54165, SN74165 ............................................................ 5.5 V
SN54LS165A, SN74LS165A ....................................................... 7 V
Interemitter voltage (see Note 2) .............................................................. 5.5 V
Operating free·air temperature range: SN54165, SN54LS165A ............................. - 55°C to 125°C
SN74165,SN74LS165A ................................. O°Ct070°C
Storage temperature range ............. '.............. , .............................. -65°Cto 150°C
NOTES 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. This rating applies for the '165 to the shift/load input in.
conjunction with the clock·inhibit inputs.
2-524
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, Tl;:XAS 75265
SN54165, SN74165
PARALLEL·LOAO 8·BIT SHIFT REGISTERS
recommended operating conditions
SN54165
MIN
Supply voltage, Vee
NOM
4.5
SN74165
MAX
MIN
5,5
4.75
5
NOM
5
-800
High-level output current. IOH
MAX
5.25
-800
16
Low-level output current, IOL
0
Clock frequency. fclock
20
0
UNIT
V
~A
16
rnA
20
MHz
Width of clock input pulse, tw(clock)
25
25
ns
Width of load input pulse, tw(loadl
15
15
ns
Clock-enable setup time, tsu (see Figure 1)
30
30
ns
Parallel input setup time, tsu (see Figure 1)
10
10
ns
Serial input setup time, tsu (see Figure 21
20
20
ns
Shift setup time, tsu (see Figure 2)
45
45
ns
0
0
Hold time at any input, th
-55
Operating free-air temperature, T A
125
0
70
ns
"e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
I nput clamp voltage
SN54165
TEST eONDITIONSt
MIN
SN74165
TVP:t MAX
2
VOH High-level output voltage
VOL
Low-level output voltage
II
Input current at maximum input voltage
IIH
High-level input current
Shift/load
Other inputs
Shift/load
Vee = MIN,
11= -12 rnA
Vee - MIN,
VIH - 2V,
VIL = 0.8 V,
10H = -800~A
Vee = MIN,
VIH=2V,
VIL = 0.8 V,
IOL=16rnA
Vee - MAX,
VI=5.5V
Vee = MAX,
VI = 2.4 V
IlL
Low-level input current
lOS
Short-circuit output current~
Vee = MAX
ICC
Supply current
Vee - MAX,
Vee = MAX,
Other inputs
2.4
MIN
TVPt MAX
2
VI =O.4V
V
0.8
0.8
V
-1.5
-1.5
V
3.4
0.2
2.4
0.4
3.4
0.2
See Note 3
V
0.4
V
1
1
rnA
80
40
80
. 40
~A
--3.2
-3.2
-1.6
-20
UNIT
-55
42
-1.6
-18
42
63
rnA
-55
rnA
63
rnA
NOTE 3: With the outputs open, clock inhibit and clock at 4.5 V, and a clock pulse applied to the shift/load input, ICC IS measured first
with the parallel inputs at 4.5 V, then with the parallel inputs grounded.
tFor conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
tAli
typical values are at
Vee""
5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
switching characteristics, Vee
PARAMETER~
=5 V, T A =25°e
FROM
TO
IINPUT)
(OUTPUT)
TEST eONOITIONS
f max
tpLH
Any
Load
tpHL
tPLH
Any
Clock
tPHL
tPLH
See figures 1 thru 3
H
OH
tPHL
tPLH
CL ·15pF. RL = 400 n,
H
QH
tPHL
MIN
TVP
20
26
MAX UNIT
MHz
21
31
27
40
16
24
21
31
11
17
24
36
18
27
18
27
ns
ns
ns
ns
~fmax := maximum clock frequency
tpLH := propagation delay time, low-to-high-Ievel output
tpH L ::::: propagation delay time, high-to-Iow-Ievel output
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75265
2-525
SN54LS165A, SN.74LS165A
PARALLEL· LOAD 8·BIT SHIFT REGISTERS
recommended operating conditions
SN54LS165A
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
-I
-I
r-
C
NOM
MAX
MIN
NOM
MAX
4,5
5
5,5
4,75
5
5:25
2
IOL
low-level output current
fclock
Clock frequency
twfcloc.
3V
INPUT
-l
RL
~~~~RO~;;~T
,
-l
~
SERIAL
CLOCK
INPUT
m
::..
- --
:0
O. For '165, Vrel ~ 1.5 V; lor 'LS165A, Vrel ~ 1.3 V.
~
~
:l>
S
i---++-'PHL
---VOH
re!
C. The input pulse generators have the following characteristics: PRR " 1 MHz, duty cycle" 50% Zout::: 50
tor 'LS165A, tr ~ 15 ns, tf ~ 6 ns.
N
VOH
VOL
,
tpLH~
,V re!
re !
-0
:l>
tPLH~,--I
Vref
B. Prior to test, high-level data is loaded into H input.
~ Ul4r
~
,V re!
-- 3 V
1
1
I.-.I-tPHL
ov
1
I'
tPLH~
-
NOTES: A. The remaining six data inputs and the serial input are low.
Z
'"
Vref
-
--
+----OV
, - - - - - ; - 1""""'\1
I I
~,
OUTPUT
QH
I+-..j-tPHL
tpHL
Vref
Vref
tPLH~
1'l(Jl
~
I
OUTPUT
~
r-------~I.~~I
\I
3V
-
1
---1---t""-+I- t PH L
1 '-----..J
clock IS high
lOW).,
I
Vref
LOAD
!
---OV
:.j..
I
SHIFT!
- ~';bYewhHe
-
_I - - - 1- - - J
j4 tw(cJOCk~tw(CJOCk I
1
1
INPUTS
-
~V~
'"
----+I
F AND H
-
~
~
tI
•
l0iii'
TeL
~ ~ ~
o
Z
tn
NOTES: A. The eight data inputs and the clock-inhibit input are low. Results are monitored at output 0H
at tn+7.
8. The input pulse generators have the following characteristics: PRR " 1 MHz, duty cycle cn
FUNCTION TABLE
L
G
GND
The '166 and 'lS166A S-bit shift registers are compatible with most other TIL logic families. All '166 and
'lS166A inputs are buffered to lower the drive requirements to one Series 54/74 or Series 54lS174lS
standard load, respectively. Input clamping diodes
minimize switching transients and simplify system
design.
CLEAR
VCC_
SH/lD
H
QH
E
F
(3)
(4)
2.30
(5)
(10)
(11)
(12)
G
(14)
H
(13)
QH
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe
Publication 617-12.
Pin numbers shown are for D. J, N, and W packages.
PROOUeTiO. DATA documents contain infarmation
curranl as of publication date. Products c.nform to
spacifications p.. t., terms of T,x•• Instruments
~=~i~lt::,:ri ~.=:::; ~r::::~:~~ not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-529
SN54166. SN54LS166A. SN74166. SN74LS166A
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
typical clear, shift, load, inhibit, and shift sequences
I-
u.
:i:
g'"
a:
~
--_---_ -_______ - - -------_ -______ ~ 1
TI§
l[
z
-
Q
r
I-
u.
*~
w
'"
__________________________________ 1
--
'-'0"
U
U
I-
§
:I:
~
'g"
-'
U
2-530
~
I-
::I
0.
:!:
-'
«
iX
w
I~
«
.,
--- -,-,
I
I
I
U
\
W
0
V
-'
I-
u.
:i:
en
TEXAS
Cl
I
:I:
I
:I:
0
I-
::I
0.
W'"
-'l-
I-
«0.
a:z
«a.
0
-'::I
'"
II.
-I/}
INSTRUMENlS
POST OFFICE BOX 65501.2 • DAllAS. TEXAS 75265
::I
-
a:
~
-'
U
SN54166, SN54LS166A, SN74166, SN74LS166A
PARALLEL· LOAD 8·BIT SHIFT REGISTERS
schematics of inputs and outputs
'166
EQUIVALENT OF EACH INPUT
OUTPUT
- -....-Vee
V e e - -...........- -
lOOn
INPUT
OUTPUT
If)
Q)
'LS166A
EQUIVALENT OF PARALLEL
AND SERIAL INPUTS
Vee----4r.---
(,)
EQUIV ALENT OF EACH INPUT
OUTPUT
--------1~Vee
Vee
-
Q)
C
...J
Req
lI-
~24knNoM
INPUT--1~"""""""-
·S
INPUT
L - -.....-OUTPUT
Shift/Load Req : 13 kn NOM
All Other Req : 10 kn NOM
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-531
SN54166, SN54LS166A, SN74166, SN74LS166A
PARALLEL· LOAD 8·BIT SHIFT REGISTERS
logic diagram (positive logic)
SERIAL INPUT -:':":_.......1
_H-...,...""'
SHI FT/Li5Ao ....:...:;~Dc.....
A-=:"'-_...J
B...::.:.....----l-I--L..I
~
rC
o...::.:.....----l-I--L...J
CD
<
(=r
CD
(II
H ~~----~~
CLOCK
CLOCK INHIBIT
~===JC:~-----~
.!
"'1..---..,.J
Pin numbers shown are for 0, J, N, and W packages.
2-532
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54166, SN74166
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
......... .
Input voltage . . . . . . .
......... .
Operating free·air temperature range: SNS4166 (see Note 2)
SN74166
Storage temperature range
7V
S.SV
-5Soe to 12Soe
oOe to 70°C
-6Soe to lS00e
recommended operating conditions
SN74166
SN54166
MIN
Supply voltage, Vee
NOM MAX
4.5
5
MIN
NOM MAX
4.75
5.5
5
-800
High-level output current. IOH
Low-level output current, tOl
5.25
-800
16
Clock frequency. fclock
0
25
0
UNIT
V
16
"A
rnA
25
MHz
Width of clock or clear pulse, tw (see Figure 11
20
20
ns
Mode-control setup time, tsu
Data setup time, tsu Isee Figure 1)
30
30
ns
20
20
ns
0
0
Hold time at any input, th (see Figure 1)
Operating free-air temperature, T A (see Note 2)
-55
125
70
0
ns
°e
en
Q)
(.)
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
SN54166
TEST eONDITloNst
MIN
SN74166
TYPt MAX
MIN
2
VOH High-level output voltage
Vee- MIN,
11--12rnA
Vee=MIN,
VIH = 2V,
VIL=0.8V,
10H = -800 "A
Vee = MIN,
VIH = 2V,
VIL=0.8V,
IOL=16mA
VOL
Low-level output voltage
II
Input current at maximum input voltage
Vee = MAX, VI - 5.5 V
2.4
TYP, MAX
2
C
V
...I
0.8
V
-1.5
-1.5
V
2.4
0.4
0.4
1
V
1
rnA
IIH
High-level input current
Vee -MAX, VI - 2.4 V
40
40
IlL
Low-level input current
Vee = MAX, VI =O.4V
-1.6
-1.6
"A
rnA
lOS
Short-circuit output current §
Supply current
-57
rnA
Vee = MAX, See Note 3
127
rnA
ICC
Vee -MAX
-20
-57
90
-18
127
90
........
V
3.4
0.2
Q)
UNIT
0.8
3.4
0.2
-S;
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°C.
Not more than one output should be shorted at a time.
*
NOTES:
1. Voltage values are with respect to network ground terminal.
2. An SN54166 in the W package operating at free-air temperatures above 113"C requires a heat-sink that provides a thermal
resistance from case to free air, RaCA, of not more than 4SoC/W.
3. With all outputs open, 4.5 V applied to the serial input, all other inputs except the clock grounded, ICC is measured after a
momentary ground. then 4.5 V, is applied to the clock.
switching characteristics, Vee = 5
V, T A = 25° e
PARAMETER
!max
TEST CONDITIONS
Maximum clock frequency
MIN
TYP
25
35
MAX UNIT
MHz
Propagation delay time, high-to-
tpHL
low-level output from clear
Propagation delay time, high-to-
tpHL
low-level output from clock
eL = 15pF.
See Figure 1
Propagation delay time, low-to-
tpLH
"-.
23
35
ns
20
30
ns
17
26
ns
RL = 4oo!!.
high-level output from clock
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-533
SN54LS166A, SN74LS166A
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage ............................................................................... 7 V
Operating free-air temperature range: SN54LS166A ....................................... - 55°C to 125°C
SN74LS166A ......................................... oOe to 70°C
Storage temperature range ........................................................... -65°eto 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS166A
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
SN74LS166A
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
2
V
2
IOH
High-level output current
-0.4
-0.4
IOL
Low-level output current
4
8
mA
fclock
Clock frequency
25
MHz
tw
Width of clear pulse (See Figure 1)
20
20
tw
Width of clock pulse (See Figure 1)
25
25
0
25
0
mA
ns
tsu
Mode-control setup time
30
30
-I
-I
tsu
th
Data setup time (See Figure 1)
20
20
ns
0
0
ns
o
TA
r-
Hold time at any input (See Figure 1 and Note 4)
NOTE 4:
-55
Operating free air temperature
The hold time limit of 0 ns apphes only If the rise time
IS
125
ns
0
70
°e
less than or equal to 10 ns.
CD
<
c:;"
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
CD
II)
VIK
VOH
VOL
SN54LS166A
TEST CONDITIONS t
PARAMETER
Vee = MIN,
11=-18mA
Vee= MIN,
VIH-2V,
MIN
VIH- 2V,
VIL = MAX
SN74LS166A
MAX
MIN
TYP*
VIL - MAX,
2.5
3.4
0.25
IIOL - 4 mA
2.7
3.4
0.4
POL = 8 mA
II
Vee= MAX,
VI = 7 V
MAX
-1.5
-1.5
IOH = -0.4 mA
Vee= MIN,
TYP*
V
V
0.25
0.4
0.35
0.5
0.1
UNIT
0.1
V
mA
IIH
Vee= MAX,
VI = 2.7 V
20
20
IlA
IlL
IOS§
Vee= MAX,
VI = 0.4 V
-0.4
-0.4
mA
100
mA
lee
Vee= MAX,
32
mA
20
Vee= MAX
100
20
See Note 5
20
32
20
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:l:Al1typical values are atVCC = 5V, TA = 25°C.
§Not more than one output should be shorted at a time, and duration for short-circuit should not exceed one second.
NOTE 5: With aU outputs open, 4.5 V applied to the serial input and all other inputs except the clock grounded, ICC is measured after a momentary ground,
than 4.5 V, is applied to clock.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
TEST· CONDITIONS
f max Maximum clock frequency
MIN
TYP
25
35
Propagation delay time, high-to-
tPHL
tPHL
tpLH
2-534
low-level output from clock
CL = 15pF,
UNIT
MHz
ns
19
30
7
14
25
ns
5
11
20
ns
low-level output from clear
Propagation delay time, high-to-
MAX
RL = 2 kn,
See Figure 1
Propagation delay time, low-tohigh-level output from clock
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54166. SN54LS166A. SN74166. SN74LS166A
PARALLEL·LOAD 8·BIT SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION
TEST
POINT
Vec
TEST TABLE FOR SYNCHRONOUS INPUTS
FROM
~~~~~T
-
. .~. . . . . . .
t--.t-t....--,
TEST
DATA INPUT
ISee Note D
OUTPUT TESTED
SHIFT/LOAD
FOR TEST
(SEE NOTE F)
~CL=15PF
H
OV
QH attn+l
.J...ISee Note CI
Serial
Input
4.5V
QH at tn+8
LOAD FOR OUTPUT UNDER TEST
_ _ _....,-41
CLEAR" INPUT
Vref
tw(clear)
~
Ir-----------------------
~ Vref
0---L- -I
I
I
I
I tn+1
tn
r--
(See Note G)
~
-~---3V
CLOCK INPUT
r----Li~ th
"- 0 V
Vref~~ef----oV
INPUT
(SEE TEST - - - - - ' - - - - - - - '
TABLE)
tpHl
---..l
(clear-O)
Q
I
--I tpHl j--
r-
-----""'\
til
(I)
Q)
"
oS;
~tSU~3V
DATA
OUTPUT
- - OV
tn+1
tn
Ir---"",
I
3 V
Q)
C
...J
I-I--
(ClK·Q)
\~ef--
Vref
-
VOH
'----vOL
VOLTAGE WAVEFORMS
NOTE: A. All pulse generators have the following characteristics: Zout:::::50Q; for '166, t r " 7 ns and tf<7 os; for'LS166A, t,< 15 nsand
tf" 6 ns.
B. The clock pulse has the following characteristics: tw(clock) '" 20 os and PRR = 1 MHz. The clear pulse has the following
characteristics: tw(dear) " 20 ns and thold = 0 ns. When testing f max , vary the clock PRR.
CL includes probe and jig capacitance.
All diodes are lN3064. lN916. or equivalent.
A clear pulse is applied prior to each test.
Propagation delay times (tpLH and tPHLI are measured at tn + l' Proper shifting of data is verified at tn + 8 with a functional test.
tn = bit time before clocking transition
tn + 1 = bit time after one clocking transition
tn + 8 = bit time after eight clocking transitions
H. For '166 Vref = 1.5 V; for ·lSl66A Vro! = 1.3 V.
C.
D.
E.
F.
G.
FIGURE 1
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-535
E1
-I
-I
r
oCD
<
C')
CD
(fl
2-536
SN54167. SN74167
SYNCHRONOUS DECADE RATE MULTIPLIERS
DECEMBER 1972 - REVISED MARCH 1988
SN54167 ... J OR W PACKAGE
SN74167 ... N PACKAGE
(TOP VIEWI
•
Perform Fixed-Rate or Variable-Rate
Frequency Division
•
For Applications in Arithmetic, Radar,
Digital-to-Analog (D/A), Analog-to-Digital
(A/DI, and other Conversion Operations
•
NC
B2
B3
SET-TO-9
Typical Maximum Clock
Frequency . . . 32 MHz
Z
Y
ENout
GND
description
These
monolithic,
fully synchronous,
programmable counters utilize Series 54174 TTL
circuitry to achieve 32-megahertz typical
maximum operating frequencies. These decade
counters feature buffered clock, clear, enable
and set-to-nine inputs to control the operation
of the counter, and a strobe input to enable or
inhibit the rate input/decoding AND-OR-INVERT
gates. The outputs have additional gating for
cascading and transferring unity-count rates.
The counter is enabled when the clear, strobe
set-to-nine, and enable inputs are low. With the
counter enabled, the output frequency is equal
to the input frequency multiplied by the rate
input M and divided by 10, Ie.:
'out =
where: M
=
VCC
B1
BO
ClR
UNITY/CAS
ENin
STRB
ClK
Mo'in
--;063 02 3 + 62 0 22 + 61 0 21 + 60 0 20
NC-No internal connection
logic symbol t
[~ ]
I/)
G4
Q)
CJ
0:;;
z
UNITY/CAS
(131
CLR
(41
SET·TO·9
(141
60
(151
81
(21
B2
(31
B3
Q)
Y
CT=O
CT=9
;;
(i'
O}
ENABLE
C
...J
l-
I-
4P
IRATE]
Ga/3
for decimal zero through nine.
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC
When the rate input is binary 0 (all rate inputs
Publication 617-12.
low), Z remains high. In order to cascade devices
to perform two-decade rate multiplication (0-99),
the enable output is connected to the enable and
strobe inputs of the next stage, the Z output of each stage is connected to the unity/cascade input of
the other stage, and the SUb-multiple frequency is taken from the Y output. For longer words, see typical
application data, Figure 1.
The unity/cascade input, when connected to the clock input, may be utilized to pass the clock frequency
(inverted) to the Y output when the rate input/decoding gates are inhibited by the strobe. The unity/cascade
input may also be used as a control for the Y output.
All of the Inputs of these counters are diode-clamped, and each input, except the clock input, represents
one normalized Series 54/74 load. The buffered clock input, used with the strobe gate, is only two Series
54/74 loads. Full fan-out to 10 Series 54174 loads is available from each of the output. These devices
are completely compatible with most TTL and DTL families. Typical dissipation is 270 milliwatts. The
SN54167 is characterized for operation over the full military temperature range of - 55°C to 125°C, and
the SN74167 is characterized for operation from ooe to 70°C.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications par the terms of Texas Instruments
::~:~~i~ai~:1~1e ~:~~:i:;
:.. .::~::::~:~~s not
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-537
SN54167, SN74167
SYNCHRONOUS DECADE RATE MULTIPLIERS
STATE AND/OR RATE FUNCTION TABLE (See Note AI
OUTPUTS
INPUTS
LOGIC LEVEL OR
NUMBER OF
BCD "ATE
Y
Z
ENABLE
NOTES
H
B2
X
BO
X
B3
X
Bl
H
X
X
X
H
L
H
H
L
L
L
L
L
L
L
10
H
L
H
1
L
L
L
L
L
L
H
10
H
1
1
1
B
C
C
L
L
L
L
L
H
L
10
H
C
L
L
L
L
H
H
10
H
1
L
L
L
L
H
L
L
10
H
L
L
L
L
H
L
H
10
H
L
L
L
L
H
H
L
10
H
6
2
3
4
5
6
1
L
2
3
4
5
L
L
L
L
H
H
H
10
H
7
7
1
L
L
L
H
L
L
L
10
H
1
L
L
L
H
L
L
H
10
H
L
L
L
H
L
H
L
10
H
L
L
L
H
L
H
H
10
H
L
L
L
H
H
L
L
10
H
8
9
8
9
8
9
8
9
9
1
C
C
C
C
C
C
C
C,D
C,D
C,D
C,D
C,D
C,D
1
E
CLEAR ENABLE STROBE
•
NOTES:
NUMBER OF PULSES
UNITY/
CLOCK PULSES CASCADE
L
L
L
H
H
L
H
10
H
L
L
L
H
H
H
L
10
H
L
L
L
H
H
H
H
10
H
8
9
8
9
8
9
8
9
L
L
L
H
L
L
H
10
L
H
1
1
1
1
1
1
1
1
1
A. H "" high level. L "" low level, X "" irrelevant. All remaining entries are numeric counts.
8. This is a 'simplified illustration of the clear function. The states of clock and strobe can affect the logic level of Y and Z. A low
unity/cascade will cause output Y to remain high.
C. Each rate illustrated assumes a constant value at rate inputs; however, these illustrations in no way prohibit variable-rate inputs.
D. These input conditions exceed the range of the decimal rate inputs.
E. Unity/cascade can be used to inhibit output Y.
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
vee
vee----1>---
INPUT
OUTPUT
Clock: Req = 2
kn
NOM
All others: Req =- 4 k{l NOM
2-538
. TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54167. SN74167
SYNCHRONOUS DECADE RATE MULTIPLIERS
logic diagram (positive logic)
w ....
.... ::1
CD
I>.
~~
wO
C
....
Q
Q
10
w O
w
CIl
a:
I>.
....
;
a:
«
w
c
....
CD
U
w ....
.... ::1
«I>.
....
a:!!:
::I
I>.
....
::I
0
>
....w
CIl
w
a:
I>.
§
a:
....
«
w
....
Ul
Q)
(,)
U
'S;
....
::I
§ I>.
....
::I
0
N
N
Q)
0
..J
lI-
w
Q
«
U
~
g
N
CD
w ....
.... ::1
«I>.
> ....
.... ::1
Z~
::1_
a:!!:
M
CD
w ....
.... ::1
«I>.
a:!!:
w
........
~~
Zz
w_
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-539
SN54167, SN74167
SYNCHRONOUS DECADE RATE MULTIPLIERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
Operating free-air temperature range: SN54167
SN74167
Storage temperature range
7V
5.5V
_55°C to 125°C
DoC to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54167
MIN NOM
Supply voltage. Vee
4.5
SN74167
MAX
MIN NOM
5
5.5 4.75
High-level output current, IOH
-400
16
Low-level output current, IOL
0
Clock frequency, fclock
25
UNIT
5.25
V
-400
~A
16 rnA
25 MHz
0
Width of clock pulse, tw(clock)
20
20
ns
Width of clear pulse, tw(clear)
15
15
ns
Width of set-ta-nine pulse tw(set-to-9)
15
15
ns
(See Note 2)
Enable setup time, tsu:
~
~
From positive-going transition of clock pulse
rC
From positive-going transition of clock pulse
From negative-going transition of previous clock pulse
n'
Operating free-air temperature, T A
NOTE 2:
ns
0
t w (clock)-10
0
t w (clock)-10
ns
0
'w(clock)-10
t cp -l0
0
20
t w (clock)-10
t cp -10
ns
20
-55
125
0
70
°c
(See Note 2)
Enable hold time. th:
<
25
25
from negative-going transition of previous clock pulse
CD
~
MAX
5
ns
tw(clock) is the interval in which the clock is high. tcp is the total clock cycle starting with a negative transition. See Figure 1 on
SN5497. SN7497 data sheet.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDITIONSt
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
MIN
TvPt
MAX UNIT
V
2
VI
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current at maximum input voltage
IIH
High-level input current
IlL
Low-level input current
lOS
Short circuit output current §
clock input
other inputs
clock inputs
other inputs
Vce-MIN,
11--12rnA
Vec-MIN,
VIH = 2V,
VIL = 0.8 V,
10H = -400J,tA
VeC- MIN,
VII~=2V,
VIL=0.8V,
IOL=16rnA
Vce- MAX,
VI- 5.5V
Vee = MAX,
VI = 2.4 V
Vee = MAX,
VI=O.4V
2.4
V
-1.5
V
3.4
0.2
V
0.4
1
80
40
-3.2
-1.6
-18
Vce- MAX
0.8
-55
IceH Supply current, output high
Vec=MAX,
See Note 3
43
leCL Supply current, output low
Vec- MAX,
See Note 4
65
V
rnA
J,tA
rnA
rnA
rnA
99
rnA
NOTES: 3. ICCH is measured with outputs open and all inputs low.
4. leCL is measured with outputs open and all inputs high except the set-to-nine input which is low.
tFor test conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
+AII typical values are at
Vec =
5 V, T A == 25° C.
§ Not more than one output should be shorted at a time.
2-540
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54167. SN74167
SYNCHRONOUS DECADE RATE MULTIPLIERS
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETERS t
FROM
TO
INPUT
OUTPUT
Enable
Enable
Strobe
Z
TEST CONDITIONS
f max
tPLH
tpHL
tPLH
tpHL
tPLH
Clock
V
Clock
Z
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
Z
Rate
Unity/Cascade
V
tpHL
tPLH
tpHL
tpLH
CL~15pF.
RL~400n.
Strobe
V
Clock
Enable
See Note 5
Clear
tpHL
tPHL
tpLH
Sot-to-9
Any Rate Input
TVP
25
32
MAX
20
14
21
12
18
15
23
26
39
20
30
12
18
17
26
9
14
6
10
9
14
6
10
19
30
22
33
19
30
33
V
24
36
Z
15
23
Enable
18
27
15
23
15
23
V
tPHL
UNIT
MHz
13
22
tpHL
tpLH
MIN
ns
ns
os
os
os
os
os
ns
en
Q)
os
'S;
(.)
Q)
os
C
os
...J
tfmax is maximum clock frequency.
tPLH is propagation delay time, low-to-high-Ievel output.
tpHL is propagation delay time, high-to-Iow-Ievel output
NOTE 5: load circuit. voltage waveforms, and input conditions for measuring switching characteristics are the same as those for the SN5497
aod SN7497.
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
lI-
2-541
sa:>!l\ a a 1.1.1
t-.l
a,
-I>
en en
t-.l
o
m
~
/
::1:1
~
\
m
L
SL
z
~
~~
CK
L
c~
~Ul
Z
U5~
L
CK
ENABLE
INPUT
SET·TO
NINE
c::
n
:::!
STROBE
ENABLE
OUTPUT
'167
Y
z
UNITY!
CASCADE
H
OUTPUT
ENABLE
INPUT
STROBE
ENABLE
OUTPUT
'167
CLEAR
CLEAR
LI
Y
»
r
»
CK
SET-TO
NINE
ENABLE
INPUT
SET-TO
NINE
STROBE
ENABLE
OUTPUT
'167
CLEAR
Z
UNITY/
CASCADE
Y
Z
UNITY!
CASCADE
H
H
OUTPUT
s-L
NC
s:
~
:!:!
""r
n
~
o
:2
Cl
~
»
~
"'tIl
~
iTi
::1:1
en
SN54LS169B, SN54S169,
SN74LS169B, SN74S169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
OCTOBER 1976-REVISED MARCH 19BB
SN54LS169B, SN54S169 ... J OR W PACKAGE
SN74LS169B, SN74S169 ... 0 OR N PACKAGE
• Programmable Look-Ahead Up/Down
Binary Counters
(TOP VIEWI
• Fully Synchronous Operation for Counting
and Programming
UfD
ClK
A
B
C
D
ENP
GND
• Internal Look-Ahead for Fast Counting
• Carry Output for n-Bit Cascading
• Fully Independent Clock Circuit
VCC
RCO
QA
QB
QC
QD
ENT
lOAD
SN54LS169B, SN54S169 ... FK PACKAGE
(TOP VIEWI
~IO
....J ........
description
U
UIO
uu
u=>z>a:
These synchronous presettable counters feature an
internal carry look-ahead for cascading in high speed
counting applications. The 'lS169B and 'S169 are
4-bit binary counters. Synchronous operation is
provided by having all flip-flops clocked
simultaneously so that the outputs change coincident
with each other when so instructed by the countenable inputs and internal gating. This mode of
operation helps eliminate the output counting spikes
that are normally associated with asynchronous
(ripple-clock) counters. A buffered clock input triggers
the four master-slave flip-flops on the rising (positivegoing) edge of the clock waveform.
.
3 2
Q)
(J
-S;
.Q)
o
9 10111213
...I
Iw(!l° ulOl1gw
lI-
zzz---
TYPICAL OF
ALL Q OUTPUTS
TYPICAL OF
RCOOUTPUT
- - -.......-VCC
-----t--VCC
VCC--......- - -
20 kn NOM
INPUT
INPUT....,~>--_
OUTPUT
OUTPUT
INPUT
Req NOM
ENT
6.5 kn
Others
13 kn
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................ " ., ........................... : ..... 7 V
Input voltage ................................................................................ 7 V
Operating free-air temperature range: SN54LS169B ... _. _................................. - 55°C to 125°C
SN74LS169B .......................................... oOe to 70°C
Storage temperature range ........................................................... - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN74LS169B
SN54LS169B
VCC
Supply voltage
VIH
High-level-input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
RCO
-0.4
-0.4
mA
Any Q
-1.2
-1.2
mA
4
8
mA
12
24
mA
20
MHz
RCO
AnyQ
0
fclock
Clock frequency
tw(clock,l
Width of clock pulse (high or low) (see Figure 1)
tsu
Setup time, (see Figure 1)
0
25
25
30
30
ENp'or ENT
30
30
LOad
35
35
35
35
UfD
Hold time at any input with respect to clock (see Figure 1)
TA
Operating free-air temperature
2-548
20
Data inputs A, B, C, D
th
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ns
ns
ns
0
0
-55
V
2
2
Low-level output current
UNIT
MIN
125
0
70
°c
SN54LS169B. SN74LS169B
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH
VCC=MIN,
11=-18rnA
Vcc =MIN,
VIH=2V,
Any 0
RCO
VIH=2V,
VIL =MAX
MIN
TvPt
MAX
SN74lS169B
TVPt MAX
MIN
-1.5
RCO
VIL =MAX
VCC =MIN,
VOL
SN54lS169B
TEST CONDITIONSt
AnyO
IOH = -0.4 rnA
2.5
IOH =-1.2rnA
2.4
IOH =4 rnA
3.4
-1.5
2.7
3.2
3.4
2.4
0.25
0.4
IOL=12rnA
0.25
0.4
IOL - 24 rnA
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
II
VCC =MAX,
VI = 7 V
0.1
0.1
IIH
VCC = MAX,
VI=2.7V
20
20
-0.2
-0.2
IlL
VCC = MAX,
VI =0.4 V
IOS~
VCC =MAX,
Vo =OV
ICC
VCC =MAX,
See Note 2
UfD, lOAD, ENP, CLK
All other inputs
-0.4
RCO
-20
Any 0
-30
28
-0.4
-100
-20
-130
-30
-100
-130
45
V
V
3.2
IOL-8rnA
UNIT
28
45
V
rnA
~A
rnA
rnA
rnA
t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
:tAil typical values are at
Vee = 5 V. T A = 25° C.
~Not more than one output should be shorted at a time, and dUration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured after applying a momentary 4,5 V, then ground, to the clock input with all other inputs grounded and the outputs
U)
Q)
(.)
open.
-S;
switching characteristics, Vee = 5 V, T A = 25°e (see note 3)
PARAMETER~
FROM
(INPUT)
TO
(OUTPUT)
Q)
TEST CONDITIONS
f max
tpLH
tpHL
tPLH
tPHL
tpLH
tpHL
tPLH
tpHL
CLK
ENT
UfO
ClK
RL=2kn,
CL=15pF
ReD
AnyQ
MIN
TVP
20
35
26
RCO
RCO
'LS169B
RL = 667 n,
CL = 45 pF
MAX
UNIT
..oJ
lI-
MHz
40
17
25
15
25
11
20
23
35
15
25
16
25
17
25
C
ns
ns
ns
ns
• Propagation delay time from up/down to ripple carry must be measured With the counter at eIther a minimum or a maximum count. As the
logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output transisti on will be in phase. If the count is maximum (15), the ripple carry output will be out of phase.
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-549
SN54S169. SN74S169
SYNCHRONOUS 4·BIT UP/DOWN BINARY COUNTERS
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
----------~~-Vee
EQUIVALENT OF EACH INPUT
, 50n NOM
Vee-l~--~~----
20kn NOM
(LOAD INPUT
ONLY)
INPUT
OUTPUT
ENT input: Req == 1.4 kn NOM
LOAD input: Req '" 3.5 kn NOM
All other inputs: Aeq.e 2.8 kn NOM
absolute maximum ratings over operating free-air temperature range 'unless otherwise notedl
Supply voltage, Vee (See Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Interemitter voltage (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54S 169 (see Note 6) . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
SN74S169 .................
ooe to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
recommended operating conditions
SN54S169
Supply voltage,
Vee
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-1
rnA
-1
Low-level output current, IOl
20
Clock frequency, fclock
0
Width of clock pulse, twlclockl·lhigh or lowllsee Figure 1)
Data inputs A.
a,
40
0
10
10
4
4
14
14
C, 0
ENP or ENT
Load
9
6
UfO
20
20
1
Hold time at any input with respect to clock, tw (see Figure 1)
-55
Operating free-air temperature, T A (see Note 6)
UNIT
NOM
High-level output current, IOH
Setup time, tsu (see Figure 1)
SN74S169
MIN
20
rnA
40
MHz
ns
ns
1
125
0
ns
70
°C
NOTES: 4. Voltage values, except interemitter voltage, are with respect to network ground terminal.
5. This is the voltage between two emitters of a multiple-emitter transistor. For these circuits, this rating applies between the
count enable inputs ENP and ENT.
6. A SN54S169 in the W package operating at free-air temperatures above 91°C requires a heat sink that provides a thermal
resistance from case to free-air, RaCA. of not more than 26 °C/W.
2-550
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54S169. SN74S169
SYNCHRONOUS 4-B11 UP/DOWN BINARY COUNTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS t
PARAMETER
SN54S169
MIN
TVP*
SN74S169
MAX
2
VIH High·level input voltage
VIK Input clamp voltage
VOH High-level output voltage
MIN.
II
Vee
~
MIN,
VIH
~
2 V,
0.8 V,
10H
~
-1 rnA
MIN,
VIH
~
2 V,
0.8 V,
10L
~
20 mA
~
~
Vee
VIL
II
Input current at maximum input voltage
IIH
High-level input current
-18 mA
~
VIL
VOL Low-level output voltage
~
Vec
~
Vee
~
MAX,
VI
~
5.5 V
Vee
~
MAX,
VI
~
2.7 V
2.5
V
V
-1.2
-1.2
V
3.4
-10
2.7
3.4
Vee
~
MAX,
lOS Short-circuit output current §
Vee
~
MAX,
lee Supply current
Vee
~
MAX,
Other inputs
VI
~
0.5
1
1
-200
0.5 V
-200
50
50
-4
-4
See Note 2
-100
100
V
mA
100
-10
-2
-40
V
0.5
Other inputs
ENT
UNIT
0.8
100
Load
MAX
0.8
ENT
Low-level input current
TYP*
2
VIL Low·level input voltage
IlL
MIN
-2
-40
160
100
~A
rnA
-100
rnA
160
rnA
en
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:t: All typical values are at Vee = 5 V. T A = 25°C.
Q)
NOTE 2: ICC is measured after applying a momentary 4.5 V, then ground, to the clock input with all other inputs grounded and the outputs open.
.2
>
switching characteristics. Vee = 5 V. T A = 25°e
C
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
Q)
PARAMETER~I
FROM
TO
(INPUT)
(OUTPUT)
TEST CONDITIONS
f max
tpLH
eLK
tpHL
tpLH
tpHL
tpLHO
tpHLO
TYP
40
70
Reo
eL~15pF,
eLK
AnyQ
tpHL
tpLH
UtD - HIGH
MIN
RL
~
280Q,
See Figures 2 and 3
-ENl
UfD
ReO
and Note 3
ReO
MAX
UtD - LOW
TYP MAX
MIN
40
UNIT
MHz
55
14
21
14
20
28
20
28
8
15
8
15
11
15
11
15
21
7.5
11
6
12
15
22
15
25
9
15
8
15
10
15
16
22
..J
lI-
ns
ns
ns
ns
, t max -= maximum clock frequency
tpLH = propagation delay time, low-to-high-Ievel output
tpHL = propagation delay time, high-to-Iow-Ievel output
Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the logic
level of the up/down input is changed, the ripple carry output will follow. If the count is minimum to)' the ripple carry output transition will be
in phase. If the count is maximum (15 for'S 1691, the ripple carry output will be out of phase.
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-551
SN54LS169B, SN54S168,
SN74LS169B, SN74S169
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
PARAMETER MEASUREMENT INFORMATION
,,
I-- 'wi clock)
3V
I
ClK
,
----I
--.I
INPUT
_
tsu -.I
I lactive sta,e) I.-
~
'h -.t
I '
LOAD
INPUT
' Vref
f
II
"----~I---.-
"
r-
'su
-I.-
th
tsu
linactive state)
,
T--Vref
~
'
3V
I
I
Vr'f:
I
- - - - - T - - -
I
--t
OV
I
,
------f---OV
I
\t~':----~II- -------~II---3V
DATAINPUTSJlvref
A, B, C, and D
~__________~--------------------~-------OV
I
......t
:
EN? or ENT
:C
'-1-' th
I-
, ,..----r-I------,
U/O
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _.Jlvref
OV
i l_V:~3V
!
1..... tsu
INPUT
I
---r-t
'h
'\~~
-.Jr-+-
Isu
"
1
____
\Vref
th
3V
Fov
VOLTAGE WAVEFORMS
NOTES: A. The input pulses are supplied by a generator having the following characteristics: PAR :s; 1 MHz, duty cycle s 50%, Zout;::: 500;
for 'LS169B, tr '" 15 ns; tl '" 6 ns, and lor '5169, tr '" 2.5 ns, tf '" 2.5 ns.
B. For 'LS169B, Vr.1 = 1.3 V; lor '5168 and '5169, Vr.1 = 1.5 V.
FIGURE 1-PULSE WIDTHS, SETUP TIMES, HOLD TIMES
J4
~,
ENT
INPUT
"f\",V_re_1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
I
!+--'PHL
3V
Vref _ _ _ _ _ _ _ _ OV
--.I
\.-- tPLH ---.I
,
I
I
I
'vr.1
VOL
lVre, - - - V O H
VOLTAGE WAVEFORMS
NOTES:
=
A. The input pulses are supplied by a generator having the following characteristics: PRR '" MHz, duty cycle", 50%, Zout 500;
lor 'LS169B, tr '" 15 ns, tf '" 5 ns; and for '5169, tr '" 2.5 ns, tf '" 2.5 ns.
B. tpLH and tpHL from enable T input to ripple carry output assume that the counter is at the maximum count, all Q outputs high.
C. For 'LS169B, Vrel = 1.3 V; for '5169, Vref = 1.5 V.
O. Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum
count. As the logic level of the up/down input is changed, the ripple carry output will follow. II the count is minimum 10)
the ripple carry output transition will be in phase. II the count is maximum 115), the ripple carry output will be out of phase.
FIGURE 2-PROPAGATION DELAY TIMES TO CARRY OUTPUT
2-552
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS169B, SN54S169,
SN74LS169B, SN74S169
SYNCHRONOUS 4·BITUP/DOWN BINARY COUNTERS
PARAMETER MEASUREMENT INFORMATION
l..'wlClockl..l
I
1
I
ClK
INPUT
3V
PlH
l.-.i-'
I (measure at t
I
1
OUTPUT
°A
1
I..--.L- 'PH L
n +1)
1
V
-'T
____
I
1
Vref
I.
Imeasure attn+21
~J)-------'/
.1
,
~:::
1
tpHL
1 Imeasure at tn+41
---...I-tPLH
I (measure at t n +2)
I
1
1
~rS_ _:--Jl~f
OUTPUT
°B
I..-.-.L. tpHL
I
I'
I.
.,
1
(measure at tn+81
I
VOH
I/)
Q)
_____
tPLH
C
(measure at tn+41
..J
1
OU;;UT----:--------...:..-""\~\-s--......:.:-..IIV~f
___
l-
I-
_
-
1·>-----·
..
...I-tPHL
Ir-.-....
I -tpLH
,
f
I
(measure at t n+10
or tn+161
------------.....;~"""'\SI
ISee Note BI
~~
00
o
>
Q)
--VOL
Vref
"'1.>-----.1-1-
-
-
VOL
(measure at tn+8 1
1
S.,.-----J- V~f
VOH
_ _ _ _ _ _ VOL
tplH
1
UP-COUNT VOLTAGE WAVEFORMS
NOTES: A. The input pulses are supplied by a generator having the lollowing characteristics: PRR s 1 MHz, duty cycle s 50%,
Zout" 500; lor 'LS169B, tr s 15 ns; tl s 6 ns, and 'S169, tr s 2.5 ns, tl s 2.5 ns. Vary PRR to measure Imax.
B. Outputs QD and carry are tested at tn+ 16. where tn is the bit-time when all outputs are low.
C. For 'LS169B, Vrel
~
1.3 V; for 'S169, Vrel
~
1.5 V.
FIGURE 3-PROPAGATION DElAV TIMES FROM CLOCK
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·553
-t
-t
r-
C
CD
<
(i'
CD
en
2-554
SN54170. SN54LS170. SN74170. SN74LS170
4·BY·4 REGISTER FILES WITH OPEN·COLLECTOR OUTPUTS
MARCH 1974 - REVISED MARCH 1988
•
Separate ReadlWrite Addressing Permits
Simultaneous Reading and Writing
•
Fast Access Times ... Typically 20 ns
SN54170. SN54LS170 ... J OR W PACKAGE
SN74170 ... N PACKAGE
SN74LS170 ... 0 OR N PACKAGE
(TOP
•
Organized as 4 Words of 4 Bits
•
Expandable to 1024 Words of n·Bits
•
For Use as:
Scratch·Pad Memory
Buffer Storage between Processors
Bit Storage in Fast Multiplication Designs
•
•
VIEW)
D2
D3
D4
RB
RA
Q4
Vee
D1
WA
'!IB
t:}.W
GR
Q3
Q1
GND
Q2
Open·Collector Outputs with Low
Maximum Off-State Current:
'170 ... 30IlA
'LS170 ... 20llA
SN54LS170 ... FK PACKAGE
SN54LS670 and SN74LS670 Are
Similar But Have 3-State Outputs
ooz>o
(TOP
M N
description
VIEW)
U
U
U .....
~
The '170 and 'LS170 MSI 16-bit TTL register files
incorporate the equivalent of 98 gates. The register
file is organized as 4 words of 4 bits each and separate
on-chip decoding is provided for addressing the four
word locations to either write-in or retrieve data. This
permits simultaneous writing into one location and
reading from another word location.
WA
WB
NC
GW
GR
RB
Ne
RA
Q4
In
CI)
(,)
"S
CI)
o
...J
8~~!:la
lI-
C)
NC - No internal connection
Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined
by the write-address inputs A and B in conjunction with a write-enable signal. Data applied at the inputs should be in its
true form. That is, if a high-level signal is desired from the output, a high level is applied at the data input for that
particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate
inputs are high. When this condition exists, data at the D input is transferred to the latch output_ When the write-enable
input, GW, is high, the data inputs are inhibited and their levels can cause no change in the information stored in the
internal latches. When the read-enable input, GR, is high, the data outputs are inhibited and remain high_
The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding
gates are used to complete the address for reading a word. When the read address is made in conjunction with the
read-enable signal, the word appears at the four outputs.
This arrangement-data-entry addressing separate from data-read addressing and individual sense line-eliminates recovery
times, permits simultaneous reading and writing, and is limited in speed only by the write time (30 nanoseconds
typical) and the read time (25 nanoseconds typical). The register file has a nondestructive readout in that data is not
lost when addressed.
All '170 inputs and all inputs except the read enable and write enable of the 'LS170 are buffered to lower the drive
requirements to one Series 54/74 or Series 54LS/74LS standard load, respectively. Input-clamping diodes minimize
switching transients to simplify system design. High-speed, double-ended AND-OR-INVERT gates are employed for the
read-address function and drive high-sink-current, open-collector outputs. Up to 256 of these outputs may be wire-AND
connected for increasing the capacity up to 1024 words. Any number of these registers may be paralleled to provide
n-bit word length.
The SN54170 and SN54LS170 are characterized for operation over the full military temperature range of -55°e to
125°C; the SN74170 and SN74LS170are characterized for operation from O°C to 70°C.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
spacifications per the terms of TexIs Instruments
::~=~~i~ar::,~le ~:~~~ti:; lIr::;::~:~~s not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TeXAS 75265
2-555
SN54170. SN74170
4·BY·4 REGISTER FILES WITH OPEN·COLLECTOR OUTPUTS
logic diagram (positive logic)
en
I:>
0-
I-
:>
0
I~
0
1:j
"
'"0
-t
-t
r-
C
CD
<
(:;'
CD
en
~
....
."
~
co
Co
!t
.
'0
C
z·
-;
o'
.S!
.
~
V
en
~I-
1-:>
~Oo!,:
~
OJ
;
'"
ICl;;: ;;: ;;:~
~
WI-
0::"-
;;:!i:
TEXAS .",
INSTRUMENTS
POST OFF1CE BOX 656012 • DALLAS, TEXAS 75265
~
0
-;;
e!
'-v--' ..,E
!::>
2-556
c
"
c
f
SN54LS170, SN74LS170
4·8Y·4 REGISTER FILES WITH OPEN·COlLECTOR OUTPUTS
logic diagram (positive logic I
...
II>
::l
...::l
0-
0
"
N
C;
0
M
0
CI)
Q)
.>CJ
Q)
o
......
...J
..
"
'"'"'"
"'"
Co
3:
"0
C
...::l ;;i-i'"
0-
1!: c:i
w
!: oS
a: i!!
~
'"c
~
0
\0
N
c
v
'"c
"c
-;;
.
l!!
.c
~~
E
::>
c
c
il:
~
1D
logic diagram (positive logic)
CI)
2D
CLR
NC
NC
30
3Q
CLK
:>
4D
o
Q)
(J
Q)
......
...J
IOOUIOO
C")ZZ'
--
CI)
C
OUTPUT
....
lI-
2W/RO. 2W/R1. 2W/R2.
lOW. 2GW, or Clock: Req - 4 kU NOM
Other inputs: Req .. 8 kfl NOM
logic symbol t
Section 1 permits the writing of data into any two-bit
word location while reading two bits of data from
another location simultaneously. To provide this
flexibility. independent decoding is incorporated.
lWO
lWl
lW2
lRO
Section 2 of the register file is similar to section
with the exception that common read/write address
circuitry is employed. This means that section 2 can
be utilized in one of three modes:
Vcc
TYPICAL OF ALL OUTPUTS
1R1
lR2
RAM 8)(2
12)
111
1231
:}
lA~
191
181
171
: } 2A
¥
lGW
lGR
2W/RO
2W/Rl
1) Writing new data into two bits
2) Reading from two bits
3) Writing into dnd simultaneously
reading from the same two bits.
2W/R2
2GvV
2GR
CLOCK
lOA
Regardless of the mode. the operation of section 2 is
entirely independent of section 1.
20A
20A
lOB
20B
laB
20B
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and
lEe Publication 617-12.
PRODUCTION DATA doc.mento.o.lli. I.formallo.
currant IS 01 publlCllio. dota_ Prod.clI conlorm to
Ipa.ill••llo.1 par the terms of Ta••• Instrumanto
:.:=~~rvr::I~~i ~~::I:~I:r :'I"::~:=~~ not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76266
2-569
SN741}2
·16·81T MULTIPLE·PORT REGISTER FILE WITH 3·STATE OUTPUTS
description (continued)
The three-state outputs of this register file permit connection ot up to 129 compatible outputs and one Series 54/74
high· logic· level load to a common system bus. The outputs are controlled by the read-enable circuitry so that they
operate as standard TTL totem-pole outputs when the appropriate read·enable input is low or they are placed in a
high·impedance state when the associated read-enable input is at a high logic level. To minimize the possibility that two
outputs from separate register files will attempt to take a common bus to opposite logic levels, the read-enable circuitry
is designed such that disable times are shorter than enable times.
All inputs are buffered to lower the drive requirements of the clock, read/write address, and write-enable inputs to one
normalized Series 54174 load, and of all other inputs to one·half of one normalized Series 54174 load.
Functions of the inputs and outputs of the SN74172 are as shown in the following table.
FUNCTION
-I
-I
SECTION 1
SECTION 2
Write Address
lWO, 1Wl, lW2
2W/RO, 2W/Rl, 2W/R2
Write Enable
lGW
2GW
When low, permits the writing of new data into
the selected word location on a positive transition
of the clock input.
2DA,2DB
Data at these inputs is entered on a positive
transition of the clock input into the location
selected by the write address inputs if the write
enable input is low. Since the two sections are
independent, it is possible for both write functions
to be activated with both write addresses selecting
the same word location. If this occurs and the
information at the data inputs is not the same for
(Le.,
both
sections
lDA,*2DA
andlor
1 DB 2DB) the low-level data will predominate
in each bit and be stored.
DESCRIPTION
Binary write address selects one of eight two·bit
word locations.
r-
oCD
<
C)'
CD
fA
Data Inputs
lOA, lOB
'*
Read Address
lRO,lR1,lR2
Common with
write address
Read Enable
lGR
2GR
Data Outputs
lOA, lOB
20A,20B
Clock
When read enable is low, the outputs assume the
levels of the data stored in the location selected by
read address inputs. When read enable is high, the
associated outputs remain in the high·impedance
state and neither significantly load nor drive the
Iines to which they are connected.
The positive-going transition of the clock input
will enter new data into the addressed location if
the write enable input is low. The clock is
common to both sections.
CK
..
2-570
Binary write address selects one of eight two-bit
word locations.
"'is.
TEXAS WV"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
S174172
16-81T MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS
READ
ADDRESS
IR
WRITE
ADDRESS
IW
WRITE
ENABLE 13~
IGW
,I
~
12~
--
II ~
~
CLOCK
1231
19~
16~
18~
17~
READ
r - - ENABLE
IGR
115~
------- - - - - - - -- ----,
I
~~~~~
I
I
I
I
I
IDA~
DUAL
I-LINE TO 8-LINE
DUAL
8-LlNE TO I-LINE
DEMULTIPLEXER
MULTIPLEXER
I
I
14~ I
1-----"\
r-----v'
IDBi
.....--:S==~:----'
IL - S E~~I
CTiON2---
I
I
I
I
I
I
12::c1-,-1-t--I
2DA-,,
1-----"\
r-----v'
BY2-BIT
STORAGE
REGISTER
I
~IOA
I
~
r-----v
I
~
DUAL
8-LlNE TO I-LINE
DEMULTIPLEXER
MULTIPLEXER
...I
'"::>
f--
~
~
0-
f--
::>
0
I
~ 20A
I
I
I
2DBi. . .
I
11111
-r-I
!'!""""-,---r_r-'
20B
"'--r--'-r-"T"""~-'
I
I
I
I
I
WRITE 1201
ENABLE 2GW
Q)
C
I
I
I
I
I
~
DUAL
I-LINE TO 8-LlNE
L_
-S;
lOB
t---------~I
I
I
151
CI)
Q)
(,)
:
~
8-WORD
I
I
I
------------------~
1171 1181 1191
1161
~
ADDRESS
READ
-ENABLE
2GR
WRITE/READ
2W/R
FIGURE 1
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 76265
2-571
SN74172
16·81T MULTIPLE·PORT REGISTER FILE WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage (see Note 1)
I nput voltage . . . . .
Output voltage (see Note 2)
Operating free·air temperature range
Storage temperature
..... .
NOTES:
lV
5.5V
5.5V
oOe to lOoe
-65°C to 150°C
1. Voltage values are with respect to network ground terminal.
2. This is the maximum voltage which should be applied to any output when it is in the high-impedance state.
recommended operating conditions
Supply voltage, vee
MIN
NOM
4.75
5
MAX UNIT
High-level output current. IOH
low-level output current, IOL
Clock frequency, f clock
Width of clock pulse, tw(clock)
0
High·level data
Setup time, tsu(see Figure 1)
Hold time, thlsee Figure 1)
r0-
O
Data release time, trelease (see Figure 1)
CD
<
n'
CD
en
V
mA
mA
20
MHz
25
Write select
-I
-I
5.25
-5.2
16
ns
Iwlclock)+10
30
Low-level data
45
Write enable
35
Write select
0
Write enable
0
High-level data
0
Low-level data
0
Operating free-air temperature, T A
ns
ns
ns
70
0
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONOITIONSt
PARAMETER
VIH
MIN
High·level input voltage
2
TVP* MAX UNIT
V
VIL
Low·level input voltage
VIK
Input clamp voltage
Vee= MIN,
11=-12mA
VOH
High·level output voltage
Vee MIN,
VIL=0.8V,
VIH 2V,
10H= -5.2mA
Vee- MIN,
VIH -2V,
VIL = 0.8 V,
10L= 16mA
Vee= MAX,
VO=2.4V
40
Vee = MAX,
VO=0.4V
-40
2.4
V
V
3
V
VOL
Low-level output voltage
1010ft)
Off·state (high~impedance state) output current
II
Input current at maximum input voltage
Vee- MAX,
VI = 5.5 V
1
mA
IIH
High~level
Vee= MAX,
VI- 2.4 V
40
I'A
Vee= MAX,
VI = 0.4 V
IlL
input current
Low-level input current
12W/RO, 2W/R1, 2W/R2,
1GW, 2GW, or clock
0.2
lOS
lee
Short~circuit
output current§
Supply current
0.4
-1.6
I Any other input
V
I'A
mA
-0.8
-18
Vee = MAX
Vee- MAX,
All inputs at 4.5 V,
Outputs open
tt=or conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°e.
§Not more than one output should be shorted at a time.
2-572
0.8
-1.5
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
112
-55
mA
170
mA
SN74172
16·81T MULTIPLE·PORT REGISTER FILE WITH 3·STATE OUTPUTS
switching characteristics, Vee = 5 V, TA = 25°e, RL = 400 n
TEST
PARAMETER
CONOITIONS
f max
Maximum clock frequency
IPLH
Propagation delay time,
'PHL
Propagation delay time, high-to-'ow-Ievel output from read select
'pLH
Propagation delay time, low-to-high-Ievel output from clock
'pHL
Propagation delay time, high-to-Iow-Ievel output from clock
'pZH
tpZL
tpHZ
Output disable time from high level
'PLZ
Output disable time from low level
MIN
TVP
MAX UNIT
20
low~to·high-Ievel
output from read select
MHz
35
45
45
50
35
50
Output enable time to high level
14
30
Output enable time to low level
16
30
6
20
11
20
33
30
CL=50pF,
See Figure 2
CL = 5 pF,
See Figure 2
ns
ns
ns
ns
PARAMETER MEASUREMENT INFORMATION
I - - t w---1
J/."
\l...
CLOCK
INPUT
I ..
(See
3V
Zj_l:'~ _____ OV
t+-" 10 ns---=r'·5 V
~~te C)+-M th
WRITE - - - - I
SELECT
V
INPUTS
•
' - __________
~.5
l r---I
*.5 V
".----OV
~
I.
Isu
Ii
l_~.L'~e~,,-
DATA INPUT
(HIGH·LEVEL DATAl
Y,.5 V
I_
1.5 V "
WRITE
~~:~~i
____ 3V
~.
3
..~i
~.5 V
1.57
";Q)
C
tt-
V
I
-R;;;-----
11~.o-------ISU----_.I
~.
Q)
(,)
..J
ov
~ tratease
I
DATA INPUT
(LOW·LEVEL DATAl
I
'1
'su
en
3V
1
ov
3V
~,,1_.5_V_.;..._ _ _ _ _ _-;.i.ol!Z::'"1:'~ ___ 0 V
!-tPLH-+-l
l
OUTPUT
1 . 5 " - VOH
I--tPLH
VOL
--I
~VOH
OUTPUT
7""1.5 V
------------------
- - VDL
SWITCHING TIMES FROM CLOCK INPUT
VOLTAGE WAVEFORMS
FIGURE 2
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAL.LAS, TEXAS 75266
2-573
SN74172
16·81T MULTIPLE·PORT REGISTER FILE WITH 3·STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
~:p~~LE ~1.5V
~:~
r--tZL---+l
- - - : - - - - -....-1---,
1Sl closed,
i.5 V
I S2 open
WAVEFORM 1
(See Note B)
I--- tZH - I
tLZ!-t
45 V
1
Sl and
.
1
1 S2 closed
_ _ _+_~¥
> 1.5 V
------TVOL
tHZ [+---+j 0.5 V
0.5 V
____ :t
I
1
~~:::'::d E~ov
WAVEFORM 2
(See Note B)
______ : :
~===-VOH
Sland
S2 closed
ENABLE AND DISABLE TIMES FROM READ ENABLE
NOTES:
A. Input waveforms are supplied by pulse generators
having the following characteristics: tr"; 7 os,
<
tf
ns, PRR "" 1 MHz, Zout ~ 50 n.
B. Waveform 1 is for an output with internal conditions
such that the output is low except when disabled.
Waveform 2 is for an output with internal conditions
-t
-t
rC
eD
<
n·
eD
, such that the output is high except when disabled.
C. Write select setup time, as specified, will protect data
written into previous address.
D. Load circuit is shown on page
VOLTAGE WAVEFORMS
FIGURE 2 (continued)
C/I
2·574
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
"1.5V
SN54173, SN54LS173A, SN74173, SN74LS173A
4-81T OoTYPE REGISTERS WITH 3-STATE OUTPUTS
OCTOBER 1976- REVISED MARCH 19BB
SN54173, SN54lS173A ... J OR.W PACKAGE
SN74173 ... N PACKAGE
SN74lS173A ... D OR N PACKAGE
(TOPVIEWI
• 3-State Outputs Interface Directly with
System Bus
• Gated Output-Control Lines for Enabling
or Disabling the Outputs
M
• Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of
of Two Modes:
VCC
ClR
10
20
3D
40
N
10
20
30
40
ClK
GNO
Parallel Load
Do Nothing (Hold)
• For application as Bus Buffer Registers
G2
SN54LS173A ... FK PACKAGE
(TOPVIEWI
TYPICAL
MAXIMUM
TYPICAL
PROPAGATION
CLOCK
POWER
FREOUENCY DISSIPATION
DELAY TIME
'173
23 ns
35 MHz
250 mW
'LS173A
18 ns
50 MHz
95mW
u ~5
z::!;z>u
TYPE
10
20
NC
30
40
4
CI)
10
20
NC
3D
40
5
6
7
8
Q)
(J
'>
Q)
C
......
..J
description
The '173 and 'LS173A four-bit registers include O-type
flip-flops featuring totem-pole three-state outputs
capable of driving highly capacitive or relatively lowimpedance loads. The high-impedance third state and
increased high-logic-level drive provide these flip-flops
with the capability of being connected directly to and
driving the bus lines in a bus-organized system without
need for interface or pull-up components. Up to 128 of
the SN74173 or SN74LS173A outputs may be connected to a common bus and still drive two Series 54174
or 54LS/74lS TTL normalized loads, respectively.
Similarly, up to 49 of the SN54173 or SN54LS173A
outputs can be connected to a common bus and drive
one additional Series 54174 or 54lS/74lS TTL normalized load, respectively. To minimize the possibility
that two outputs will attempt to take a common bus to
opposite logic levels, the output control circuitry is
designed so that the average output disable times are
shorter than the average output enable times.
NC - No internal connection
FUNCTION TABLE
INPUTS
OATA ENABLE
DATA
OUTPUT
CLEAR
CLOCK
Gl
G2
D
H
X
X
X
X
l
L
l
X
X
X
L
t
t
t
t
00
00
00
l
l
L
Q
H
X
X
X
H
X
l
l
l
l
l
l
H
H
When either M or N (or bothl is (arel high the output is
disabled to the high-impedance Slate; however sequential
operation of the flip-flops is not affected.
Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both data-enable
inputs are low, data at the 0 inputs are loaded into their respective flip-flops on the next positive transition of the buffered
clock input. Gate output control inputs are also provided. When both are low, the normal logic states (high or low levels) of
the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the
clock by a high logic level at either output control input. The outputs then present a high impedance and neither load nor
drive the bus line. Detailed operation is given in the function tab!e.
PRODUCTION DATA doc.ments contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
:~~::~~i~a{::I~~e ~!:~:~ti:f :llo:=:~~:~~s
not
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-575
SN54173, SN54LS173A, SN14173, SN14LS173A
4·81T D·TYPE REGISTERS WITH 3·STATE OUTPUTS
logic symbols t
'LS173A
'173
(;1
(;2
ClK
(3)
10
20
30
40
(4)
(5)
3D
4D
II)
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
logic diagram (positive logic)
OUTPUT { M
CONTROL
N
-I
-I
r-
(I)
C
CD
<
(:;'
CD
CIl
DATA.;..(1_3)~--~~::~~~rtt::J
2D
-+
CLOCK
.;.;(7~)---"1>~f-__r-____
DATA
3D
.:..:(1=c2)'--__~:::::j~L)
DATA (II)
40
~-'----~f_----r_,
CLEAR~(1=c5.:..:)~:»------------~
Pin numbers shown are for D, J, N, and W packages.
2-576
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75285
(6)
10
20
30
40
SN54173. SN54LS173A. SN74173. SN74LS173A
4·81T O·TYPE REGISTERS WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage: '173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
'LS173A
......................................................... 7 V
Off·state output voltage
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range: SN54173, SN54LS173A . . . . . . . . . . . . . . . . . . . . . . . _55°e to 125°e
SN74173, SN74LS173A . . . . . . . . . . . . . . . . . . . . . . . . . . OOeto 700 e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _65° e to 1500 e
NOTE 1: Voltage valu •• ara with respect to network ground terminals.
Q
schematics of inputs and outputs
'173
'LS173A
EQUIVALENT OF EACH INPUT
EQUIVALENT OF EACH INPUT
v ee
VCC--~--
4 kfl NOM
INPUT
20 kfl NOM
--
INPUT_.,....._~
,.
fI)
Q)
(,)
'S;
TYPICAL OF ALL OUTPUTS
Q)
-,,--Vee
TYPICAL OF ALL OUTPUTS
----..--VCC
o
..J
tt-
OUTPUT
OUTPUT
TEXAS ."
INSTRUMENTS
POST OFFice BOX 655012. DALLAS, TEXAS 75266
2-577
SI54173, SN74173
4·81T D·TYPE REGISTERS WITH 3·STATE OUTPUTS
recommended operating conditions
SN&4173
SN74173
UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, V CC
4.5
5
5.5
-2
High·level output current. 10H
Low-level output current. 10L
I nput clock frequency, f clock
Width of clock or clear pulse. tw
Data enable
Data
Setup time, tsu
Claar inactive state
Data eneble
Hold time. th
16
25
0
20
17
10
10
2
10
-55
Date
Operating free-air temperature, T A
4.75
5
0
20
17
10
10
V
5.25
-5.2 mA
16 mA
25 MHz
ns
ns
2
10
125
ns
70
0
·C
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
::Ir-
VIH
PARAMETER
High-level input voltage
VIL
VIK
Low-level input voltage
I nput clamp voltage
VOH
TEST CONDITIONSt
2
VCC· MIN.
VCC-MIN,
High-level output voltage
C
CD
Low-level output voltage
<
VOL
CD
fII
10(011) Off-state (high-impedance state) output current
(;'
II
IIH
IlL
lOS
ICC
MIN TVP; MAX UNIT
11--12mA
VIL = 0.8 V.
VIH -2V.
10H -MAX
VCC· MIN.
VIH = 2 V.
VIL = 0.8 V,
IOL-16mA
2.4
0.4
40
I Vo -0.4V
-40
VCC· MAX,
VCC= MAX.
VCC= MAX.
VCC· MAX
VI=5.5V
VI = 2.4 V
VI =O.4V
VCC= MAX.
See Note 2
V
V
V
V
VCC=MAX.' VO=2.4V
VIH = 2 V
Input current at maximum input voltage
High-level input current
Low-level input current
Short-circuit output currentS
Supply current
0.8
-1.5
30
50
V
/loA
1
mA
40
-1.6
70
/loA
mA
mA
mA
72
tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
:iAIi typical values are at
Vee = 5
V, T A'" 25u C.
§ Not more than one output shOUld be shorted at 8 time.
NOTE 2: ICC is measured with all outputs open; clear grounded following momentary connection to 4.5 V; N. G1, G2, and all data inputs
grounded; and the clock input and M at 4.5 V.
switching characteristics, Vee = 5 V, TA = 25°e, RL = 400 n
PARAMETER
TEST CONDITIONS
f ma )(
Ma)(imum clock frequency
tpHL
tPLH
tpHL
Propagation delay time, high-to-Iow-Ievel output from clear input
. tpZH
tpZL
tPHZ
tPLZ
Propagation delay time, low-to-high-Ievel output from clock input
Propagation delay time, high-to-Iow-Ievel output from clock input
CL·50pF,
See Note 3
Output enable time to high level
7
Output enable time to low level
7
3
3
Output disable time from high level
CL = 5 pF,
Output disable time from low level
See Note 3
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-578
MIN TVP MAX UNIT
MHz
25
35
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
18
28
19
16
21
5
27
43
31
30
30
14
11
20
ns
ns
ns
ns
SN54LS173A. SN74LS173A
4·81T O·TVPE REGISTERS WITH 3·STATE OUTPUTS
recommended operating conditions
SN54LS173A
SN74LS173A
MIN
NOM
MAX
MIN
NOM
4,5
5
5,5
4.75
5
Supply voltage, Vee
-1
High·level output current, IOH
12
Low·level output current, tOl
0
Input clock frequency, fclock
Width of clock or clear pulse, tw
Data enable
Data
Clear inactive state
Data enable
Setup time, tsu
Hold time, th
30
Operating free-air temperature, T A
UNIT
5.25
V
-2.6
mA
24
mA
30
MHz
25
25
n.
35
17
35
17
n.
10
10
0
0
n.
3
3
-55
Data
0
MAX
125
70
0
'e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
SN54LS173A
SN74LS173A
UNIT
MIN TYP~ MAX MIN TYP; MAX
TEST CONDITIONSt
2
1010ft) Off-state (high-impedance state) output current
Vee= MIN,
11=-18mA
Vee=MIN,
VIH - 2 V,
VIL = VILmax
10H = MAX
2.4
2
0.8
V
-1.5
-1.5
V
2.4
3.4
0.25
V
0.7
3.1
V
0.25
0.4
0.35
0.5
Vee = MIN,
IOL=12 rn A
VIL=0.8V
10L = 24 rnA
Vec = MAX,
Vo = 2.7 V
20
20
VIH = 2 V
VO=0.4V
-20
-20
0.4
V
jl.A
II
Input current at maximum input voltage
Vee- MAX,
VI- 7 V
0.1
0.1
IIH
High-level input current
Vee = MAX,
VI = 2.7 V
20
20
jl.A
IlL
Low-level input current
Vee = MAX,
VI=0.4V
-0.4
-0.4
mA
lOS
Short-circuit output current§
Vee = MAX
-130
mA
lee
Supply current
Vee =MAX,
24
rnA
-30
See Note 2
-130
19
-30
30
19
•
en
Q)
(,)
'S:
Q)
a
..J
lI-
mA
t For condi tions shown as MIN or MAX, use the appropriate value specified under recommended operati~9 conditions.
+AII typical values are at Vee"" 5 V, TA = 2SoC.
§ Not more than one output should be shorted at a time.
NOTE 2: iCC is measured with all outputs open; clear grounded following momentary connection to 4.5 V; N, G1, G2, and all data inputs
grounded; and the clock input and M at 4.5 V.
switching characteristics, Vee
= 5 V, TA = 25°e, RL = 667 n
PARAMETER
TEST CONDITIONS
f max
Maximum clock frequency
tPHL
Propagation delay time, high-to-Iow-Ievel output from clear input
tPLH
Propagation delay time, low-to-high-Ievel output from clock input
CL = 45 pF,
See Note 3
MIN TYP MAX UNIT
30
MHz
50
26
35
17
22
25
tpHL
Propagation delay time, high-to-Iow-Ievel output from clock input
tpZH
Output enable time to high level
15
23
tpZL
Output enable time to low level
18
tpHZ
Output disable time from high level
eL = 5 pF,
11
27
20
tpLZ
Output disable time from low level
See Note 3
11
17
30
n.
ns
n.
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-579
2-580
SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175,
SN74174, SN74175, SN74LS174, SN74LS175, SN74S174, SN74S175
HEX/QUADRUPLE D·TYPE FLlp·FLOPS WITH CLEAR
DECEMBER 1972-REVISED MARCH 1988
'174, 'LS174, 'S174 ... HEX D·TYPE FLlp·FLOPS
'175, 'LS175, 'S175 ... QUADRUPLE D·TYPE FLlP·FLOPS
•
'174, 'LS174, 'S174 Contain Six Flip·Flops
with Single·Raii Outputs
•
'175, 'LS175, 'S175 Contain Four Flip·Flops
with Double·Rail Outputs
•
Three Performance Ranges Offered: See
Table Lower Right
•
Buffered Clock and Direct Clear Inputs
•
Individual Data Input to Each Flip·Flop
•
Applications include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
SN54174. SN54lS174. SN54S174 ... J OR W PACKAGE
SN74174 ... N PACKAGE
SN74lS174. SN74S174 •.. D OR N PACKAGE
(TOP VIEW)
ClR
10
VCC
60
60
50
50
40
40
ClK
20
3D
30
GND
SN54lS174. SN54S174 ... FK PACKAGE
(TOP VIEW)
015
tlo
_uz>'"
description
U
These monolithic, positive-edge· triggered flip·flops
utilize TIL circuitry to implement O·type flip·flop logic.
All have a direct clear input, and the '175, 'LS175, and
'S 175 feature complementary outputs from each flip·
flop.
Information at the 0 inputs meeting the setup time
requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse. Clock triggering
occurs at a particular voltage level and is not directly
related to the transition time of the positive-going pulse.
When the clock input is at either the high or low level,
the 0 input signal has no effect at the output.
I/J
Q)
CJ
'S
Q)
C
....I
lISN54175, SN54lS175, SN54S175 ... J OR W PACKAGE
SN74175 ... N PACKAGE
SN74lS175. SN74S175 ... D OR N PACKAGE
(TOP VIEWI
These circuits are fully compatible for use with most
TIL circuits.
elR
10
FUNCTION TABLE
10
20
20
20
GNO
lEACH FLIP FLOPI
INPUTS
CLEAR CLOCK
OUTPUTS
0
X
a
at
L
x
H
H
t
t
L
H
H
H
L
L
H
H
L
X
00
00
L
4
5
6
12
11
10
9
VCC
40
40
4D
3D
30
30
ClK
SN54lS175. SN54S175 ... FK PACKAGE
H "" high Javal (steady state)
l. "" low level (steacty state)
(TOPVIEWI
t "" transition from low to high leval
ol~u
tlo
_uZ>oot
00::: the level of a before the Indicated steady-state
3 2 1 20 19
x "" irrelevant
t
input conditions were established.
'LS175, and 'S175 onlv
= '175,
TYPICAL
TYPES
TYPICAL
MAXIMUM
POWER
CLOCK
DISSIPATION
FREOUENCY PER FLIP-FLOP
'174, '175
35 MHz
'LS174. 'LS175
40 MHz
14 mW
110 MHz
75 mW
'S174. '5175
38 mW
NC - No internal conneotion
PRODUCT PREVIEW docum.nta .ontlin Informltlon
• n product. In 'M formative .r d••ign ph ••• of
devel.pment. Ch.r••terlsti. data .n~ other
~=::~=:Ir~':t ~~I:CI=::I~r T3t:::~~~::~:!,,':
praduOll without natl...
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • OAL.LAS, TEXAS 75265
2-581
SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175,
SN74174, SN74175, SN74LS174, SN74LS175, SN74S174, SN74S175
HEX/QUADRUPLE D·TYPE FLlP·FLOPS WITH CLEAR
logic symbols t
'174
'175
CLR
CLR
CLK
CLK
(21
10
20
30
40
50
60
10
(51
20
(71
30
(101
40
(121
50
(151
60
(41
(61
(111
(131
(141
10
10
10
20
20
20
30
30
30
40
40
40
tThese symbols are in accordance with ANSI/IEEE Std. 91·1984 and lEe Publication 617-12.
Pin numbers shown are for D, J, N. and W packages.
logic diagrams (positive logic)
-I
-I
'174, 'LS174, 'S174
r-
'175, 'LS175, 'S175
(2)
10 (4)
10
C
CD
<
n'
CD
151
I/)
171
(10)
20
30
40
CLOCK -.,~~
CLEAR
50
-'--'-----IH-I
1121 50
60
..:..:.c'-----IH-I
(15) 60
CLOCK
CLEAR
--""'1./"-
Pin numbers shown are for 0, J, N, and W packages:
2-582
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175,
SN74174, SN74175, SN74LS174, SN74LS175, SN74S174, SN74S175
HEX/QUADRUPLE D·TYPE FLlP·FLOPS WITH CLEAR
schematics of inputs and outputs
SN54174,SN54175,SN74174,SN74175
~----------------------------~
EQUIVALENT OF ALL INPUTS
~----~------------------------~
TYPICAL OF ALL OUTPUTS
-~-Vee
VCC--_--
INPUT
OUTPUT
Clock, D: Req
Clear: Req
= 8 k.n
= 4 k!1
NDM
NDM
~--EI
SN54LS174, SN54LS 175, SN
...7_4_L_S_l_74...:.,_S_N_74_L_S_l_7_5______________----,
r------:'EQ:-:U-:-:I':":V~AL:-:E:':'N:::T:-:O:-:F:-:A"':"L~L-:-:IN-:-:P:-:U:::TS:--'----~
TYPICAL OF ALL OUTPUTS
I/)
Q)
CJ
"S
- - - - - 1 " - - - Vee
Vee
Q)
C
120 !1
Req
INPUT
u
~~
NOM
...
...J
lI~
'---+-OUTPUT
~,
r.
-,,£ock: Req = 23 kll NOM
Cle.r, 0: Req = 28 kll NOM
SN54S174, SN54S175, SN74S174,SN74S175
r----~E~QU:-:I:-:V~A~LE~N~T:-:O:-:F:-:A:-:L~L:-:IN:-:P~U~T~S-'----~
r--'---~T:-:Y:::PI:-:C:-:A:-:L~O~F:-:A:-:LL:-:O:-:U:-:T~P:-:U~TS~-----'
Vee--~--
INPUT
'---+-OUTPUT
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-583
SN5417' SN54175, SN7417' SN74175
HEX/QUADRUPLE D·TYPE FLlP·FLOPS WITH CLEAR
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage . . . . . . .
Operating free·air temperature range: SN54174, SN54175 Circuits
SN74174, SN74175 Circuits
Storage temperature range
7V
5.5 V
-55°C to 125°C
O°C to 70°C
_65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
Supply voltage, Vee
SN54174, SN54175
SN74174, SN74175
MIN
MAX
MIN
NOM
5.5
4.75
5
NOM
4.5
5
High-level output current, IOH
-800
Low-level output current, 10 L
16
Clock frequency. fclock
Width of clock or clear pulse, tw
III
-I
-I
r-
25
0
I Data input
Setup time, tsu
I
Clear inactive-state
UNIT
5.25
V
-800
IJA
16
rnA
25
MHz
20
20
ns
20
20
ns
25
25
ns
5
5
Data ho Id time. th
Operating free-air temperature, T A
0
MAX
-55
125
ns
0
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
C
TEST eONDITIONSt
PARAMETER
CD
VIH
High-level input voltage
ri"
CD
VIL
Low-level input voltage
VIK
I nput clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
II
<
(I)
MIN
TYP+
MAX
2
Vee = MIN,
11=-12rnA
Vee = MIN,
VIH=2V,
VIL = 0.8 V,
10H = -BOOIJA
Vee - MIN,
VIH - 2 V,
2A
UNIT
V
0.8
V
-1.5
V
3A
0.2
V
OA
V
VIL = 0.8 V,
10L = 16 rnA
Input current at maximum input voltage
Vee- MAX,
VI - 5.5 V
IIH
High-level input current
Vee- MAX,
VI - 2A V
40
IJA
IlL
Low-level input current
Vee = MAX,
VI-OAV
-1.6
rnA
lOS
Short-circuit output current~
Vee
lee
Supply current
~
MAX
Vee = MAX,
See Note 2
1
SN54'
-20
SN74'
-18
-57
-57
'174
45
65
'175
30
45
rnA
mA
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
tAli typical values are at V cC
=
5 V, T A = 25° C.
*Not more than one output should be shorted at a time.
NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is
applied to clock.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
f max
TEST CONDITIONS
Maximum clock frequency
Propagation delay time, low-tcrhigh-Ievel output from clear
tpLH
(SN54175, SN74175 only)
tpHL Propagation delay time, high-tcrlow-Ievel output from clear
tpLH
Propagation delay time, low-to-high-Ievel output from clock
tpHL Propagation delay time, high-to-Iow-Ievel output from clock
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-584
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
eL=15pF,
RL =400n,
See Note 3
MIN
TYP
25
35
16
MAX
UNIT
MHz
25
ns
23
35
ns
20
30
ns
24
35
ns
SN54LS17' SN54LS175, SN74LS17' SN74LS175
HEX/QUADRUPLE D·TYPE FLlp·FLOPS WITH CLEAR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
7V
Supply voltage, VCC (see Note 1)
. . . . .
Input voltage . . . . . . .
. . . . .
Operating free·air temperature range: SN54LS174, SN54LS175 Circuits
SN74LS174, SN74LS175 Circuits
Storage temperature range
NOTE1:
_55°C to 125°C
O°C to 70°C
_65°C to 150°C
Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS174
SN74LS174
MIN
Supply voltage,
Vee
4.5
NOM MAX
5
Low-level output
CUffent,
5.5
MIN
NOM MAX
4.75
5
-400
High-level output current, IOH
UNIT
SN74LS175
SN54LS175
IOL
5.25
V
-400
/lA
mA
8
4
0
Clock frequency. fclock
Width of clock or clear pulse, tw
I Data input
I Clear inactive-state
Setup time, tsu
30
5
70
20
20
20
25
25
-55
Operating free-air temperature, T A
0
20
5
Data hold time, th
30 MHz
ns
ns
ns
ns
0
125
CI)
Q)
(.)
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
SN54LS174
SN54LS175
TEST CONDITIONSt
MIN
.
VIH
High-level input voltage
VIL
VIK
Low-level input voltage
VOH
High-level output voltage
VOL
Low-level output voltage
II
IIH
-,=-
Input clamp voltage
I nput current at
maximum input voltage
High-level input current
II L
Low-level input current
------
TVPt MAX
MIN
Vee
~
TVPt MAX
VIH=2V,
2.5
VIL = VILmax, 10H = -400 "A
Vee = MIN,
VIL
VIH = 2 V,
= VIL max
VI = 7 V
Vee - MAX,
Vee - MAX,
VI-2.7V
VI-OAV
Short-circuit output current ~
Vee - MAX
lee
Supply current
Vee" MAX,
0.25
= 4 mA
2.7
004
IIOL - 8 mA
Vee = MAX,
lOS
Ii0L
3.5
-20
See Note 2
I 'LS174
I 'LS175
0.8
V
-1.5
V
....
....
V
3.5
0.25
0.4
0.35
0.5
0.1
C
..J
V
-1.5
11- -18mA
MIN,
UNIT
2
0.7
Vee - MIN,
'S
Q)
SN74LS174
SN74LS175
2
&I
DC
V
0.1
rnA
/lA
20
20
-0.4
-0.4
rnA
-100 -20
-100
mA
16
26
16
26
11
18
11
18
mA
I For conditions shown as MIN or MAX, use the appropriato value specified under recommended operating conditions.
:j"AIl typical values are at Vee
5 V, T A
25 'c.
~ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground. than 4.6 V, is
applied to clock
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
TEST CONDITIONS
f max Maximum clock frequency
'LS174
MIN
TVP
30
40
MIN
TVP
30
40
MAX
30
35
20
30
20
30
13
25
21
30
16
25
eL = 15pF,
tpHL Propagation delay time, high-to-Iow-Ievel output from clear
RL = 2 kil,
23
tPLH Propagation delay time, low-to-high-Ievel output from clock
See Note 3
UNIT
MHz
20
tpLH Propagation delay time, low-to-high-Ievel output from clear
tpH L Propagation delay time, high-to-Iow-Ievel output from clock
'LS175
MAX
n.
ns
ns
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
~
TEXAS
INSTRUMENTS
POST OFFICE
aox 655012
• DALLAS, TEXAS 75265
2-585
SN54S174, SN54S175, SN74S174, SN74S175
HEX/QUADRUPLE D·TYPE FLlP·FLOPS WITH CLEAR
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . .
Input voltage . . . . . . . . . . . . . . . . . . . . . .
Operating free·air temperature range: SN54S174, SN54S175 Circuits
SN74S174, SN74S175 Circuits
Storage temperature range
7V
5.5V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to netv:"ork ground terminal.
recommended operating conditions
SN54S174,SN54S175
Supply voltage, Vee
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-1
mA
-1
20
LOW-level output current, tOl
Pulse width, tw
Setup time, tsu
r-
C
CD
en
0
Clock
7
7
Clear
10
10
Data input
5
5
Clear inactive-state
5
5
Data hold time, th
3
20
mA
75
MHz
ns
ns
ns
3
-55
Operating free-air temperature, T A
125
e
70
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
<
~;CD
75
0
Clock frequency. fclock
UNIT
NOM
High-level output current, IOH
-4
-4
SN74S174,SN745175
MIN
TEST eONOITIONSt
PARAMETER
VIH
High-level input voltage
VIL
VIK
Low-level input voltage
MIN
TVP*
MAX UNIT
V
2
I"put clamp voltage
VOH High-level output voltage
VOL low-level output voltage
Vee' MIN,
II' -18mA
Vee' MIN,
VIH' 2V,
ISN54S'
2.5
3.4
VIL'0.8V,
10H'-1 mA
ISN74S'
2.7
3.4
Vee' MIN,
VIH-2V,
VIL' 0.8 V,
10L' 20mA
0.8
V
-1.2
V
V
0.5
V
II
Input current at maximum input voltage
Vee' MAX, VI' 5.5V
1
IIH
High-level input current
Vee' MAX, VI' 2.7 V
50
IlA
IlL
Low-level input current
Vee- MAX, VI-0.5V
-2
mA
lOS
Short-circuit output current§
Vee- MAX
-100
mA
lee
-40
Vee' MAX, See Note 2
Supply current
1'174
90
144
1'175
60
96
mA
mA
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions for the applicable device
type.
!AII typical values are at
Vee = 5 V,
T A = 25 Q e.
s: Not more than one output should be shorted at a time, and duration of the short~circuit should not exceed one second.
NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs. ICC is measured after a momentary ground, then 4.5 V, is
applied to clock.
switching characteristics, Vee = 5 V, TA = 25°C
TEST eONOITIONS
PARAMETER
f max Maximum clock frequency
Propagation delay time,
tPLH
low~to-high-Ievel
a output from clear
(SN54S175, SN74S175 only)
tpHL Propagation delay time, high-to-Iow-Ievel Q output from clear
tPLH Propagation delay time, low-to-high-Ievel output from clock
tpHL Propagation time, high-to-Iow-Ievel output from clock
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-586
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
MIN
TVP
75
110
MAX UNIT
MHz
15
ns
13
22
8
12
11.5
17
ns
ns
ns
eL' 15pF,
10
RL·280n,
See Note 3
SN54176, SN54177, SN74176, SN74177
35-MHz PRESETTABLE DECADE AND
BINARY COUNTffiS/LATCHES
MAY 1971 -REVISED MARCH 1988
•
Reduced-Power Versions of SN54196,
SN54197, SN74196, and SN74197
50-MHz Counters
•
D-C Coupled Counters Designed to Replace
Signetics 8280, 8281, 8290, and 8291
Counters in Most Applications
•
SN54176, SN54177 ... J PACKAGE
SN74176, SN74177 ... N PACKAGE
(TOP VIEWI
LOAD
VCC
ClR
OD
Oc
C
A
Performs BCD, Bi-Quinary, or Binary
Counting
D
B
°A
ClK2
•
Fully Programmable
•
Fully Independent Clear Input
•
Counts at Input Frequencies from 0
to 35 MHz
•
Input Clamping Diodes Simplify System
Design
OB
GND
ClK1
logic symbols t
'176
i1iAo
description
ClR
These high-speed monolithic counters consist of
four doc coupled master-slave flip-flops which
are internally interconnected to provide either a
divide-by-two and a divide-by-five counter
(SN54176, SN74176) or a divide-by-two and a
divide-by-eight counter (SN54177, SN74177).
These counters are fully programmable; that is,
the outputs may be preset to any state by
placing a Iowan the count/load input and
entering the desired data at the data inputs. The
outputs will change to agree with the data inputs
independent of the state of the clocks.
These counters may also be used as 4-bit latches
by using the count/load input as the strobe and
entering data at the data inputs. The outputs will
directly follow the data inputs when the
count/load is low, but will remain unchanged
when the count/load is high and the clock inputs
are inactive.
These high-speed counters will accept count
frequencies of 0 to 35 megahertz at the clock-1
input and 0 to 17.5 megahertz at the clock-2
input. During the count operation, transfer of
information to the outputs occurs on the
negative-going edge of the clock pulse. The
counters feature a direct clear which when taken
low sets all outputs low regardless of the states
of the clocks.
ClK1
(51
I/)
Q)
(,)
OA
A
"S;
Q)
ClK2
B
c
0
(101
(31
(111
:}1CT
crt
(91
C
OB
...J
....
....
(21
Oc
(121
00
'177
lOAD
CIA
ClK1
(51
OA
A
ClK2
B
(101
(91
OB
(21
C
(31
o
(111
(121
Oc
00
t These symbols are in accordance with ANSIIIEEE Std. 91-1984
All inputs are diode-clamped to minimize
and lEG Publication 617-12.
transmission-line effects and simplify system
design. The circuits are compatible with. most
TTL logic families. Typical power dissipation is
150 milliwatts, The SN54176 and SN54177 circuits are characterized for operation over the full military
temperature range of - 55°C to 125°C; the SN74176 and SN74177 circuits are characterized for operation
from O°C to 70°C.
PRODUCTION DATA documants .ontain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
:~:::~~i~ai~:I~~i ~~:~:~i:; :.~O::;:::~~~~S
not
TEXAS
+
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-587
SN5417~ SN54177, SN7417~ SN74177
35-MHz PRESETIABLE DECADE AND
BINARY COUNTERS/LATCHES
typical count configurations
SN54176 and SN74176
FUNCTION TABLES
SN54176, SN74176
The output of flip-flop A is not internally connected
to the succeeding flip-flops; therefore, the count may
be operated in three independent modes:
1. When used as a binary-coded-decimal decade
counter, the clock-2 input must be externally
connected to the OA output_ The clock -1 input
receives the incoming count, and a count
sequence is obtained in accordance with the
BCD count sequence function table shown at
right.
-I
-I
r-
C
(I)
n-<
(I)
en
2. If a symmetrical divide-by-ten count is desired
for frequency synthesizers (or other applications requiring division of a binary count by
a power of ten), the OD output must be
externally connected to the clock-1 input_ The
input count is then applied at the clock-2 input
and a divide-by-ten square wave is obtained at
output OA in accordance with the bi-quinary
function table_
DECADE IBCO)
BI-OUINARY 15-21
ISee Note A)
ISee Note B)
COUNT
0
1
2
3
4
5
6
OUTPUT
COUNT
QO QC QB QA
L
L
L
L
H
L
L
L
L
L
H
L
L
L
H
H
L
H
H
L
L
L
H
L
L
H
H
L
7
L
H
H
H
8
9
H
L
L
L
H
L
L
H
0
1
2
3
4
5
6
7
8
9
OUTPUT
QA QO QC QB
L
L
L
L
L
L
L
L
L
H
H
L
L
L
H
H
L
H
L
L
H
L
L
L
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
L
H "" high level. L "" low level
NOTES: A. Output QA connected to clock-2 input.
B. Output 90 connected to clock-1 input.
3_ For operation as a divide-by-two counter and a divide-by-five counter, no external interconnections are required.
Flip-flop A is used as a binary element for the divide-by-two function_ The clock-2 input is used to obtain binary
divide-by-five operation at the 0B. OC. and OD outputs. In this mode. the two counters operate independently;
however. all four flip-flops are loaded and cleared simultaneously.
FUNCTION TABLE
SN54177 and SN74177
SN54171. SN74117
ISee Note AI
The output of flip-flop A is not internally connected to the succeeding flip-flops.
therefore the counter may be operated in two independent modes:
COUNT
1. When used as a high-speed 4-bit ripple-through counter. output OA must be
externally connected to the clock-2 input. The input count pulses are applied to
the clock-1 input. Simultaneous divisions by 2. 4. 8. and 16 are performed at the
0A. 0B. OC. and OD outputs as shown in the function table at right.
0
1
2
2. When used as a 3-bit ripple-through counter. the input count pulses are applied
to the clock-2 input. Simultaneous frequency divisions by 2. 4. and 8 are
available at the 0B. OC. and OD outputs_ Independent use of flip-flop A is
available if the load and clear functions coincide with those of the 3-bit
ripple-through counter.
L
L
L
L
~
L
4
5
6
7
8
9
10
11
12
13
14
15
H
OUTPUT
QO QC QB QA
L
L
L
L
= high
L
H
H
H
H
L
L
L
H
H
L
L
L
H
L
H
H
L
L
H
H
H
L
H
L
L
L
H
L
L
H
H
H
L
H
H
L
H
H
L
H
H
H
H
H
H
H
hwel, L
=
L
L
L
H
H
H
H
L
low level
NOTE A: Output QA connected
to clock-2 input.
2-588
TEXAS .".
INSTRUMENTS
POST OFFICE; BQX 655012 • DAL.LAS, TEXA$ 7!'j2e5
SN54176, SN54177, SN74176, SN74177
35-MHz PRESETTABLE DECADE AND
BINARY COUNTERS/LATCHES
logic diagrams (positive logic)
§
r-<'"
......
:t...
z
'"......:
..
....
r<'"
W
~
z
'"
....
..
-<'"
.::
"""!!
««Z«
>:1 0
.... ::JO
«0
..
au
I! .
0
u
«
/\
Y
a:
m
-0
....«
«a
....«
«a
~
..0
U
u
III
....I
....
....
8
0
0
~
~
§
....
Y
U
N
....«
«
0
u
-<'"
A
§
~
III
~
..
Il
0
~
....
;
-J
-~
N
~
!!!
~
),
r-<
'"
....
..
r<'"
;:!
u
.....
~.~
-<0
....
/\
Y
.~
-<'"
;:!
Q
~
z
'"...rD
I"
z
11
~
'"
)
m
eRi
-
~-
g
i
~
N
~
..
U
o
u
§
u
«
....
g
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
U
~~
.....
11
I
-a
;:
«
a
2-589
SN54176, SN54177, SN74176, SN74177
35·MHz PRESETTABLE DECADE AND
BINARY COUNTERS/LATCHES
schematics of inputs and outputs
EQUIVALENT OF COUNT/LOAD,
CLEAR, AND DATA INPUTS
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF CLOCK INPUTS
____...._____ vcc
...
vcc--------~------
INPUT
OUTPUT
NOMINAL VALUES OF
R1, R2. and R3
= kn
Data, Count/load: Req 4
Clear: Req = 2
-I
-I
kn
NOM
NOM
INPUT
Clock 1
Clock 2
'176
'177
4kn
4kn
4kn
6 kn
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
r-
7V
5.5 V
5.5 V
_55°C to 125°C
O°C to 70°C
-65°C to 150°C
Supply voltage, VCC (see Note 1)
Input voltage . . . . . . .
Interemitter voltage (see Note 2)
Operating free·air temperature range: SN54176, SN54177 Circuits
SN74176, SN74177 Circuits
Storage temperature range
o
<
c:r
CI)
CI)
CII
NOTES:
1. Voltage values are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies between the clear and
count/load inputs.
recommended operating conditions
MIN
Supply voltage, VCC
SN54'
4.5
5
I
SN74'
4.75
5
5.5
5.25
UNIT
V
High-level output current, IOH
-800
I'A
Low-level output current, tOl
16
rnA
Count frequency (see Figure 1)
Pulse width, tw (see Figure 1)
Input hold time, th (see Figure 1)
Input setup time, tsu (see Figure 11
Clock-1 input
0
35
Clock·2 input
0
17.5
Clock-1 input
14
Clock-2 input
28
Clear
20
Load
25
High·level data
twOoad)
Low-level data
H igh·level data
'wOoad)
15
Low-level data
20
SN54'
Operating free-air temperature, T A
SN74'
NOTE 3: Minimum count enable time is the interval immediately preceding the
count/load and clear inputs must both be high to ensure counting.
negativ~oing
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MHz
ns
ns
ns
25
Count enable time, tenable (see Note 3 and Figure 1)
2-590
NOM MAX
I
ns
-55
125
0
70
°c
edge of the clock pulse during which interval the
SN54176, SN54177, SN74176, SN74177
35-MHz PRESETTABLE DECADE AND
BINARY COUNTERS/LATCHES
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
SN54176, SN74176 SN54177, SN74177
TEST CONDITIONSt
MIN
TVPt MAX
VIH
Vil
Low-level input voltage
VIK
I "put clamp voltage
VOH
High-level output voltage
Val
Low-level output voltage
II
Input current at maximum input voltage
VCC - MIN,
11- -12mA
VCC - MIN,
VIH - 2 V,
Vil = 0.8 V,
10H = -800 ~A
VCC - MIN,
VIH-2V,
Vil = 0.8 V,
10l = 16
2.4
VI
=
2.4 V
Clock 2
Data, count/load
III
Low-level input current
Clear
VCC = MAX,
Clock 1
VI = 0.4 V
Clock 2
lOS
Short-circuit output current §
VCC= MAX
ICC
Supply current
VCC = MAX, See Note 4
V
-1.5
-1.5
V
2.4
0.4
V
3.4
0.2
0.4
1
1
40
40
80
80
120
80
-1.6
-1.6
-3.2
-3.2
-4.8
-4.8
-4.8
-3.2
I SN54'
-20
-57
-20
I SN74'
-18
-57
-18
30
V
0.8
VCC- MAX, VI - 5.5 V
VCC = MAX,
High-level input current Clear, clock 1
UNIT
0.8
3.4
0.2
mA~
TVPt MAX
2
Data, count/load
IIH
MIN
2
High-level input voltage
48
-57
-57
30
48
V
mA
~A
mA
mA
en
Q)
(.)
mA
.s:
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
~ All
typical values are at VCC
§ Not
=
5 V, T A
=
25°C.
Q)
C
more than one output should be shorted at a time.
, QA outputs are tested at 10l = 16 mA plus the limit value of III for the clock-2 input. This permits driving the clock-2 input while fanning
out to 10 Series 54/74 loads.
NOTE 4: ICC is measured with all inputs grounded and all outputs open.
-oJ
~
....
switching characteristics, Vee = S V, RL = 400 n, eL = 15 pF, T A = 25°e, see figure 1
PARAMETER#
f max
tPlH
tpHl
tPlH
tpHL
tpLH
FROM (INPUT)
TO (OUTPUT)
Clock 1
QA
Clock 1
QA
Clock 2
QB
Clock 2
QC
tPHl
tplH
tpHL
tplH
Clock 2
QD
A,B,C,D
QA, QB, QC, QD
tpHl
tplH
SN54176, SN74176 SN54177, SN54177
Load
Any
Clear
Any
tpHL
tpHL
MIN
TVP
35
50
MAX
MIN
TVP
35
50
MAX
UNIT
MHz
8
13
8
13
11
17
11
17
11
17
11
17
17
26
17
26
41
27
41
27
34
51
34
51
13
20
44
66
17
26
50
75
19
29
19
29
31
46
31
46
29
43
29
43
32
48
32
48
32
48
32
48
ns
ns
ns
ns
ns
ns
ns
#fmax == maximum count frequency.
tplH '" propagation delay time, low-to-high-Ievel output.
tPHl '" propagation delay time, high-to-Iow-Ievel output.
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-591
sao!J\aa 1.Ll
u,
'"
CD
~~:----3V
CLOCK·' OR
Vcc
I
!.-tPLH...!
FROM OUTPUT
UNDER TEST
I
I
OUTPUT
GA. OS. QC. or QO
LOAD CIRCUIT
I
.
QA, OS, aC. or QO
:
I
I
VOH
OUTPUT
QA
\,5 V
~z
-=t::)
I
--
~
..,
~
~
CLOCK ENABLE TIME VOLTAGE
WAVEFORMS
CLEAR
3V
,
,5V
15V I
I
--- -- -
-
-I--;,u--:j
-
DATA INPUTS
I
I
I
I
I
A. B, C, AND D
:
I--th..-l
-----
3V
I
15 V
.... ....
-CCl .....
'
!:jm(l)
»
"
:l:1
»
s:m
I
~.~
I
I
:
-I 'PHL I_
- - -..... I
OUTPUT'S
,
\l
QA'°-S.Qc,ANDUn
"
----et
'1,5 V
'PLH . . -
1.5 V
-.a tpHL
i
VI
.
I
I
\:
I
~
_
\l..1.5 V
_
tPLH
',5
,
I.-
I
-
-
-
tPHL _
I
-
-
3 V
ov
t \ : J 1 VOH
V I
I 1.5 V
CLEAR AND LOAD VOLTAGE WAVEFORMS
FIGURE 1
NOTES: A. The i:npu1. pulse is supplied by a generator having the following characteristics: PRR
speclfied, tf < 5 ns. When testing f max • vary PRR.
B. CL includes probe and jig capacitance.
O. Unless otherwise specified, QA is connected to clock 2.
C
:l:1
2
o"
:l:1
s:
»
-I
(5
2
- - - VOL
C. AU CK
LOAD (91 1101
CLEAR
OATAB~(..;;11....:12:::.:}_ _ _ _ __+~rr~
(6) [7} OB
t-t+--Ct>CK
R
CLEAR
(8) [91 Oc
OATA C (131 1151
~-+--CI>CK
-I
-I
R
r-
CLEAR
C
CO
<
OATAO~(1~2~)~[1..;;4}_ _ _ _ _~~~
Cr
CO
00
(101 [111 00
QO
[121
~-+--cI>CK
CII
SHIFT (111 (131
R
CITAii
CLEAR
(SN64179
ONLY)
aD
(SN54179
ONLY)
11 _....q
....:[co.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
------vcc
V C C - - -....- - -
INPUT
OUTPUT
2-594
TEXAS
'iii
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54178, SN74178
4-81T PARALLEL-ACCESS SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5_5 V
Operating free-air temperature range: SN54178.......................... - 55°C to 125°C
SN74178 ............................. ooe to 70°C
Storage temperature range ......................................... - 65°C to 1 50°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54178
SN74178
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
-800
4.75
5
5.25
-800
Supply voltage. V CC
High-level output current. IOH
Low-level output current, IOL
16
0
Clock Irequency, 1clock
Width 01 clock or clear pulse, tw (see Figure 1)
Setup time tsu (see Figure 1)
I Shift (H or L) or load
J Data
25
0
20
20
35
35
30
30
5
Hold time at any input, th
Operating free-air temperature, TA
UNIT
V
~A
16
mA
25
MHz
ns
ns
5
-55
125
In
n.
CD
CJ
°c
70
0
os:
CD
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
TEST CONDITIONSt
MIN
Low-level input voltage
VIK
I nput clamp voltage
VOH
High-level output voltage
TYP* MAX
2
High-level input voltage
VIL
SN74178
SN54178
Vee= MIN,
11=-12rnA
Vee=MIN.
VIH -2V.
VIL = 0.8 V,
IOH = -800 "A
Vee=MIN.
VIH = 2 V,
VIL = 0.8 V.
VOL
Low-level output voltage
II
I nput current at maximum input voltage
Vec=MAX.
10L = 16 rnA
VI = 5.5 V
IIH
High-level input current
Vee=MAX,
VI = 2.4 V
IlL
Vee-MAX.
VI = 0.4 V
lOS
Low-level input current
Short-circu it output current §
ICC
Supply current
Vee = MAX, See Note 2
Vee= MAX
2.4
MIN
TYP* MAX
2
0.2
0.8
0.8
V
-1.5
V
2.4
0.4
3.4
0.2
V
0.4
V
mA
40
1
40
-1.6
-1.6
"A
rnA
57
rnA
75
rnA
57
46
70
18
46
..J
lI-
V
1
20
UNIT
-1.5
3.4
o
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
tAli typical values are at Vee'" 5 V, T A:;;: 25°C.
§ Not more than one output should be shorted at a time.
NOTE 2: lee is measured as follows:
a) 4.5 V is applied to serial inputs, load, shift. and
Cie8r,
b) Parallel inputs A through D are grounded.
c) 4.5 V is momentarily applied to clock which is then grounded.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-595
SN54178, SN74178
4·81T PARALLEl·ACCESS SHIFT REGISTERS
switching characteristics, Vee
PARAMETERt
=5 V, T A =25°e
FROM
TO
(INPUT!
(OUTPUT)
TEST CONDITIONS
f max
tPLH
aD
Clear
tpHL
CL=15pF.
0A. 0B. 0C. 0D
tpLH
Clock
MIN
TYP
25
39
RL = 400 fl.
tfmax
!Ie
17
23
35
24
Any output
tPHL
MHz
23
36
26
15
See Figure 1
MAX UNIT
ns
ns
Maximum clock frequency
tpHL '" Propagation delay time. high-to-Iow-Ievel output
tPLH '" Propagation delay time. low-to-high-Ievel output
PARAMETER MEASUREMENT INFORMATION
OUTPUT
VCC
FROMOUTPUT ....~....~I-~~-ilt-ilt-ilt-,
UNDER TEST
See Note 0
CL ·-15pF
ISee Note CI
-t
-t
r-
T-=
C
CD
LOAO CIRCUIT
<
c:;.
~ tw(cleari-t
CD
til
~1.5V
SHIFT
~15V
Joe--eI-
I
I
LOAD
I
DATA
ISee Note BI
I.-- tsu
: /15V
--~I~
I---
t-- tsu
:
CLOCK
tsu
I ;(15 V
--"I~
I
3V
,f':.5: _____________ 0v
CLEAR
I
tsu
(~~
~
________ :~
I
~~71-----------3V
---I
-..
I
&.-~_L
_____ .... _____ 3V
0 V
r"k.,15 V :
---'
~
I ~--+I---ts-u--"7"------- 0 V
rr-__~
... th
15 V
--~--,
~----,
I
0 V
,..-_ _ _ _ _ _
_ _.....;- ___ VOH
I.-tPHL-!
1.5V~
a OUTPUT
. " - - - VOL
ISee Note BI
VOLTAGE WAVEFORMS
NOTES:
A. Input pulses are supplied by generators having the following characteristics: tTLH:O;;;; 10 ns, tTHL ~ 10 ns, PRR'" 1 MHz,
Zout ~ 50 il.
B. Data input and Q output are any related pair. Serial and other data inputs are at GND. Serial data input is tested in conjunction
with QA output in the shift mode.
C. CL includes probe and jig capacitance.
D. All diodes are 1 N3064 or equivalent.
FIGURE l-SWITCHING TIMES
2-596
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54180, SN74180
9·BIT ODD/EVEN PARITY GENERATORS/CHECKERS
DECEMBER 1972-REVISED MARCH 1988
SN54180 ... J OR W PACKAGE
SN74180 ... N PACKAGE
FUNCTION TABLE
INPUTS
(TOP VIEW)
OUTPUTS
G
VCC
H
F
EVEN
ODD
!EVEN
!ODD
GND
E
0
C
);
);
);OFH'sAT
EVEN ODD
ATHRUH
EVEN ODD
EVEN
H
L
H
L
ODD
H
L
L
H
EVEN
L
H
L
H
ODD
L
H
H
L
X
H
H
L
L
X
L
L
H = high level, L = low level. X
H
H
=
B
A
irrelevant
description
These universal, monolithic, 9-bit (8 data bits plus 1 parity bit) parity generators/checkers, utilize familiar Series 54/74
TTL circuitry and feature odd/even outputs and control inputs to facilitate operation in either odd or even-parity
applications. Depending on whether even or odd parity is being generated or checked, the even or odd inputs can be
utilized as the parity or 9th-bit input. The word-length capability is easily expanded by cascading.
The SN54180/SN74180 are fully compatible with other TTL or DTL circuits. Input buffers are provided so that each
data input represents only one normalized series 54/74 load. A full fan-out to 10 normalized series 54/74 loads is
available from each of the outputs at a low logic level. A fan-out to 20 normalized loads is provided at a high logic level
to facilitate the connection of unused inputs to used inputs. Typical power dissipation is 170 mW.
The SN54180 is characterized for operation over the full military temperature range of _55°C to 125°C; and the
SN74180 is characterized for operation from O°C to 70°C.
fI)
Q)
(.)
'S
Q)
C
....I
lI-
absolute maximum ratings over operating free·air temperature range (unless otherWise noted)
Supply voltage, VCC (see Note 1) . . . . . . . .
Input voltage . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54180 Circuits
SN74180 Circuits
Storage temperature range
7V
5.5 V
_55°C to 125°C
O°C to 70°C
_65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54180
MIN
Supply voltage, V CC
4.5
High-level output current. IOH
Low-level output current. IOl
Operating free-air temperature, T A
PROOUCTIOI DATA dDCumonts cantain infurmation
cu......... of public.tio. dais. Products conform to
specilicatio.. par the tanns 01 T.... Instro_
:=~~a~I':.'li ~::I:i:: £:e:::::::.:~ not
NOM
5
SN74180
MAX
MIN
5.5
4.75
-800
16
-55
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
125
0
NOM
5
MAX
UNIT
5.25
V
-800
"A
mA
16
70
"C
2-597
SN54180. SN74180
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
VIK
VOH
High-level output voltage
VOL
Lo~level
II
Input current at maximum input voltage
Any data input
Vee=MIN,
11=-12rnA
Vee-MIN,
VIH - 2V,
VIL =0.8V,
IOH=-8OO IlA
Vee- MIN,
VIL = 0.8 V,
VIH 2V,
IOL= 16mA
Vee- MAX,
VI = 5.5 V
MIN
TYP; MAX
2
3.3
0.2
Any data input
Vee=MAX, VI = 0.4 V
lOS
ICC
Supply current
Vee = MAX, See Note 2
2.4
0.4
0.2
-1.5
V
V
0.4
40
40
80
-1.6
80
-55
34
V
1
-1.6
-3.2
-20
0.8
3.3
1
Vee = MAX
-3.2
-18
49
UNIT
V
-1.5
2.4
Vee = MAX, ,VI = 2.4 V
Even or odd input
Low-level input current
Even or odd input
Short-circuit output current §
IlL
SN74180
TYP; MAX
0.8
output voltage
High-level input current
MIN
2
Low-level input voltage
Input clamp voltage
IIH
SN54180
TEST CONDITIONSt
34
V
mA
IlA
m1>l
-55
mA
56
rnA
NOTE 2: ICC is measured with even and odd inputs at 4.5 V, all other inputs and outputs open.
-t
-t
I"""
C
(1)
<:
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at Vee = 5 V, T A = "250 C.
§Not more than one output should be shorted at a time.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~
C:;'
tpLH
(1)
tpHL
VI
tPLH
tpHL
tpLH
tpHL
tPLH
FROM
TO
{INPUT}
(OUTPUT)
Data
E Even
Data
I;
Data
}; Even
I)ata
I;
TEST CONDITIONS
eL = 15pF,
RL = 400 n,
Odd input grounded, See Note 3
Odd
eL = 15pF,
RL =400n,
Even input grounded, See Note 3
Odd
tpHL
tpLH
Even or Odd
I;
eL-15pF,
Even or I; Odd
RL - 400 n,
See Note 3
tpHL
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
logic svmbol t
EVEN
ODD
A
(5)
B
J;
EVEN
e
0
E
F
G
H
(12)
(13)
(I)
(2)
3
(6)
4
J;
ODD
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
2-598
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
TYP
MAX UNIT
40
60
45
68
32
48
25
38
32
48
25
38
40
60
45
68
13
20
7
10
ns
ns
ns
ns
ns
SN54180, SN74180
9·81T DOD/EVEN PARITY GENERATORS/CHECKERS
schematics of inputs and outputs
EQUIVALENT OF
EACH INPUT
TYPICAL OF BOTH
OUTPUTS
---il~-Vcc
V C C - - -....- - -
1300.
INPUT
OUTPUT
Data inputs: Req
Even and odd: Req
'=
=
4 kn.
2 kn
en
Q)
(.)
oS
logic diagram (positive logic)
Q)
C
181
A
191
...J
B
LEVEN
OUTPUT
C 1101
lI-
Dllli
DATA
INPUTS
~
G
H
1121
1131
L ODD
OUTPUT
111
121
ODD
INPUT
141
EVEN
INPUT
131
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-599
-f
-f
r-
C
CD
<
(::;'
CD
en
2-600
SN54LS181, SN54S181,
SN74LS181, SN74S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
DECEMBER 1972-REVISED MARCH 1988
SN54LS181, SN54S181 ... J OR W PACKAGE
SN74LS181, SN74S181 ... DW OR N PACKAGE
(TOP VIEW)
•
Full Look-Ahead for High-Speed
Operations on Long Words
•
Input Clamping Diodes Minimize
Transmission-Line Effects
AO
Al
81
Darlington Outputs Reduce Turn-Off
Time
53
52
51
50
•
•
•
80
vcc
"
"
Cn
Arithmetic Operating Modes:
Addition
Subtraction
Shift Operand A One Position
Magnitude Comparison
Plus Twelve Other Arithmetic
Operations
,.
,.
,.
2O
M
1'0
1'1
1'2
GND
"
"
A3
83
G
en ~
4
14
A
B
13
F3
17
1O
A2
82
P
~
SN54LS181, SN54S181 ... FK PACKAGE
(TOP VIEW)
u
~!~!~ ~ ~1~lm
Logic Function Modes:
Exclusive-OR
Comparator
AND, NAND, OR, NOR
Plus Ten Other Logic Operations
4
52
51
50
NC
Cn
M
1'0
3
'1
1 28 '}726
•
•
7
•
•
A2
2'
23
82
A3
"
83
2O
G
"
Cn +4
"
10
"
2.
1213 14 1516 17 18
NC
NC - No internal connection
TYPICAL ADDITION TIMES
NUMBER
OF
BITS
1 to 4
5 to 8
9 to 16
17 to 64
ADDITION TIMES
USING 'LS181
USING'S181
AND 'SlB2
AND'S182
24 ns
11 ns
40 ns
18 ns
44 ns
19 ns
68 ns
28 ns
PACKAGE COUNT
LOOK-AHEAD
ARITHMETIC!
LOGIC UNITS
CARRY GENERATORS
1
2
3 or 4
5 to '6
1
2 to 5
CARRY METHOD
BETWEEN
ALUs
NONE
RIPPLE
FULL LOOK-AHEAD
FULL LOOK-AHEAD
description
The 'L5181 and '5181 are arithmetic logic units (ALU)!function generators that have a complexity of 75 equivalent
gates on a monolithic chip. These circuits perform 16 binary arithmetic operations on two 4-bit words as shown in
Tables 1 and 2. These operations are selected by the four function-select lines (50, 51, 52, 53) and include addition,
subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal carries must
be enabled by applying a low-level voltage to the mode control input (M). A full carry Jook-ahead scheme is made
available in these devices for fast, simultaneous carry generation by means of two cascade-outputs (pins 1 5 and 17)
for the four bits in the package. When used in conjunction with the SN54S182 or 5N74S182 full carry look-ahead
circuits, high-speed arithmetic operations can be performed. The typical addition times shown above illustrate the
little additional time required for addition of longer words when full carry look-ahead is employed. The method of
cascading 'S182 circuits with these ALUs to provide multi-level full carry look-ahead is illustrated under typical
applications data for the'S 182.
If high speed is not of importance, a ripple-carry input (C n ) and a ripple-carry output (C n + 4) are available. However,
the ripple-carry delay has also been minimized so that arithmetic manipulations for small word lengths can be performed
without external circuitry.
PRODUCTIOIII DATA doeumanl. eonl.in information
current IS of publication data. Products conform to
specificatiDRs per the terms of Taxas Instruments
:==~~;8r'::I~7e ~~:~:i:r :'~O::~:~i:~~S not
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-601
SN54LS181, SN54S181
SN74LS181, SN74S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
description (continued)
The 'L5181 and '5181 will accommodate active-high data if the pin designations are interpreted as follows:
PIN NUMBER
Active-low data (Table 1)
Active-h igh data (Table 2)
Subtraction is accomplished by l's complement addition where the l's complement of the subtrahend is generated
internally. The resultant output is A-B-l, which requires an end-around or forced carry to provide A-B.
The 'L51 81 or '5181 can also be utilized as a comparator. The A = B output is internally decoded from the function
outputs (FO, Fl, F2, F3) so that when two words of equal magnitude are applied at the A and B inputs, it will assume
a high level to indicate equality (A = B). The ALU must be in the subtract mode with Cn = H when performing this
comparison. The A = B output is open-collector so that it can be wire-AND connected to give a comparison for more
than four bits. The carry output (C n + 4) can also be used to supply relative magnitude information. Again, the ALU
must be placed in the subtract mode by placing the function select inputs 53, 52, 51, 50 at L, H, H, L, respectively.
INPUTCn OUTPUT Cn+4
ACTIVE·LOW OATA
(FIGURE 1)
ACTIVE-HIGH DATA
A.;;B
(FIGURE 2)
H
H
A;>B
H
L
AB
L
L
H
A>B
A';;B
A< B
A;>B
L
These circuits have been designed to not only incorporate all of the designer's requirements for arithmetic operations,
but also to provide 16 possible functions of two Boolean variables without the use of external circuitry. These logic
functions are selected by use of the four function-select inputs (50,51,52.53) with the mode-control input 1M) at a
high level to disable the internal carry. The 16 logic functions are detailed in Tables 1 and 2 and include exclusive-OR,
NAND, AND, NOR, and OR functions.
5eries 54, 54L5, and 545 devices are characterized for operation over the full military temperature range of - 55·C
to 125 ·C; 5eries 74L5 and 74S devices are characterized for operation from O·C to 70 ·C.
signal designations
In both Figures 1 and 2, the polarity indicators (~) indicate that the associated input or output is active-low with
respect to the function shown inside the symbol, and the symbols are the same in both figures. The signal designations
in Figure 1 agree with the indicated internal functions based on active-low data, and are for use with the logic functions
and arithmetic operations shown in Table 1. The signal designations have been changed in Figure 2 to accommodate
the logic functions and arithmetic operations for the active-high data given in Table 2. The 'L5181 and '5181, together
with the '5182, can be used with the signal designation of either Figure 1 or Figure 2.
2-602
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 76265
SN54LS181, SN54S181,
SN74LS181, SN74S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
logic symbols t and signal designations (active-low datal
'S182
'LS181 OR'S181
AlU
50(6)
51 (5)
52(41
53(31
M(BI
Cn (71
CPG
0
0
M31
4
(0 __ _ 15) CP
(0 .. _ 151 CG
6(P=QI
(0 ___ 151
Q
co
(15) ji
(17)
G
(14) A=B
(161 Cn +4
COl
(61 Cn + B
111
C03
(lli Cn + 16
121
C05
(17I Cn + 24
C07
(22I Cn + 32
141
IBI
U)
Q)
CJ
'S;
tThese symbols are in accordance with ANSIIIEEE Std, 91-1984 and lEG Publication 617-12.
Pin numbers shown are for dual-in-line and "small outline" packages.
Q)
FIGURE 1 {USE WITH TABLE 11
C
TABLE 1
lI-
...J
ACTIVE-LOW OATA
SELECTION
M-H
M = L; ARITHMETIC OPERATIONS
LOGIC
Cn= L
Cn= H
FUNCTIONS
(no carry)
(with carry)
S3
S2
51
SO
L
L
L
L
F=A
F=AMINUS1
L
L
L
H
F = AS
F = AB MINUS 1
F = AB
L
L
H
L
F=A+B
F= ABMINUS 1
F=AB
-
F=A
L
L
H
H
F=1
F = MINUS 1 (2', COMPi
F = ZERO
L
H
L
L
F=A+B
F = A PLUS (A + 81
F = A PLUS (A + 81 PLUS 1
L
H
L
H
F= B
F = AB PLUS (A + BI
L
H
H
L
F=AG)B
F = A MINUS B MINUS 1
F = A MINUS B
F = (A + 81 PLUS 1
F = AB PLUS fA + Bi PLUS 1
L
H
H
H
F=A+B
F=A+B
H
L
L
L
F = AB
F = A PLUS (A + BI
F = A PLUS (A + BI PLUS 1
H
L
L
H
F=AG)B
F = A PLUS B
F = A PLUS B PLUS 1
H
L
H
L
F=B
F = ABPLUS (A + BI
F=
H
L
H
H
F=A+B
F = (A + BI
F = (A + SI PLUS 1
H
H
L
L
F=O
F - A PLUS At
F = A PLUS A PLUS 1
H
H
L
H
F = AB
F = AS PLUS A
F = AS PLUS A PLUS 1
AB
F=ASPLUSA
F=
F= A
F = A PLUS 1
-
H
H
H
L
F
H
H
H
H
F=A
=
-
As PLUS (A + BI
As PLUS
PLUS 1
A PLUS 1
tEach bit is shifted to the next more significant position.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-603
SN54LS181, SN54S181,
SN74LS181, SN74S181
ARITHMETIC LOGIC UNITS/FUNCTIONS GENERATORS
logic symbols t and signal designations (active-high datal
'LS181 OR '5181
'5182
ALU
SO(61
Sl (51
S2(41
S3(31
JIII(SI
C (71
0
0
M3i'
,-=-.:..:.:..--t CI
(0 ••. 151 CG
6(PmQI Q
(0 ... 151 CO
4
CPG
(151 X
(0. .. 151 CP ~~~~------+-~~~~CPO
(171 Y
(141 A-B
(16I Cn + 4
COl
(61Cn+S
(11
C03
(11I Cn + 16
(21
C05
(17I Cn + 24
C07
(22I Cn + 32
141
lSI
-t
-t
rC
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12.
Pin numbers shown are for dual~in-line and "small outline" packages.
CD
<
FIGURE 2 IUSE WITH TABLE 21.
c:;'
CD
TABLE 2
en
ACTIVE-HIGH DATA
SELECTION
M=H
SO
M
LOGIC
~
L; ARITHMETIC OPERATIONS
S2
Sl
L
L
L
L
F=A
F=A
F = A PLUS 1
L
L
L
H
F'= A + B
F-A+B
F = (A + BI PLUS 1
L
L
H
L
F = AB
F=A+S
F = (A + Bi PLUS 1
L
L
H
H
F=Q
F = MINUS 1 (2', COMPLI
F = ZERO
F = A PLUS AS PLUS 1
FUNCTIONS
(no carry)
L
H
L
L
F = AB
F = A PLUS AS
L
H
L
H
F= B
F = (A + BI PLUS AS
F = (A + BI PLUS AS PLUS 1
L
H
H
L
F = A (t) B
F = A MINUS B MINUS 1
F=AMINUSB
F= ASMINUS 1
F= AS
F = A PLUS AB
F = A PLUS AB PLUS 1
L
H
H
H
F = Ail
H
L
L
L
F=
H
L
L
H
F = A (t) B
F = A PLUS B
F = A PLUS B PLUS 1
H
L
H
L
F=B
F = (A +SI PLUS AB
F = (A + Bi PLUS AB PLUS 1
F= AB
A+ B
H
L
H
H
F = AB
F = AB MINUS 1
H
H
L
L
F=1
F=APLUSAt
F = A PLUS A PLUS 1
H
H
L
H
F=A+S
F = (A + BI PLUS A
F = (A + BI PLUS A PLUS 1
H
H
H
L
F=A+B
F = (A + Bi PLUS A
F = (A +
H
H
H
H
F= A
F = A MINUS 1
F= A
t Each bit is shifted to the next more significant position.
2-604
Cn = L
(with carryl
Cn~H
S3
TEXAS
-II
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TeXAS 75265
Bi PLUS A PLUS 1
8N54L8181, 8N548181, 8N74L8181, 5N748181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
logic diagram (positive logic)
SO
(6)
83
or 83
-
A3 or A3
(18)
~
(19)
51
(5)
52
(4)
53
~
(3)
~
(17)
(16)
~
~
~
I ~==t)
PorX
,~
~
I
I
lUor A2
(21)
Cn+4 or
I:n+4
(15)
(13)
,JU
82 or 82 ~
GorY
F3 or F3
~.
II)
Q)
CJ
':;
Q)
o
...J
,~
(22)
Bl0,Bl1 - ~
~
~
~
Al or Al
F2 or F2
lI-
~
(23)
])
(1)
80 or BO1 -
>-<{)
~
(10)
~
~
I
AD orAD
(11)
(9)
Fl or Fl
FO or FO
(2)
~
(8)
(1)
Pin numbers shown are for OW, J, N, and W packages.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-605
SN54LS181, SN74LS181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
absolute maximum ratings over recommended operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
7V
Input voltage . . . . . . . .
Interemitter voltage (see Note 2)
Operating free·air temperature range: SN54LS181
SN74LS181
Storage temperature range
. . . . . .
NOTES:
. . . . 5.5 V
. . . . 5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C
1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies to each A input in
conjunction with inputs 52 or 53, and to each 8 input in conjunction with inputs SO or 53.
recommended operating conditions
SN54LSI81
Supply Voltage, Vee
SN74LS181
NOM MAX
MIN
4.5
5
5.5
UNIT
MIN
4.75
NOM MAX
5
-400
High·level output currerlt, IOH (All outputs except A = B)
5.25
IlA
8
mA
70
°e
4
Low-level output current, IOL
Operating free-air temperature, T A
-55
125
V
-400
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
-4
-4
r-
C
CD
:::.
(')
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
Vee- MIN,
11- -18mA
High-level output voltage,
Vee= MIN,
VIH - 2V,
any output except A
VIL = VIL max, IOH = -4OOIlA
VOH
CD
en
IOH
A = B output only
VIL = VIL max, VOH = 5.5 V
VIL = VIL max
max. input
Any S input
voltage
Carry input
Low·level
current
Any A or 8 input
Any S input
lee
Vee= MAX,
0.25
IOL - 16 mA
8mA
Any S input
Vee= MAX,
Supply current
V
2.7
=
0.4
0.25
0.4
0.35
0.5
0.47
0.7
0.36
0.5
-6
0.1
0.1
0.3
0.3
0.4
0.4
0.5
0.5
20
20
60
60
80
80
100
100
-0.4
-0.4
-1.2
-1.2
-1.6
-1.6
-2
-2
-40
-5
-42
Condition A
20
32
20
34
Condition 8
21
35
21
37
2SoC.
§Not more than one output should be shorted at a time.
NOTE 3: With outputs open, ICC is measured for the following conditions:
A. SO through 53, M, and A inputs are at 4.5 V, all other inputs are grounded.
B. SO through 53 and M are at 4.5 V, all other inputs are grounded.
2-606
V
100
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee"" 5 v. T A
3.4
0.6
VI =O.4V
See Note 3
-1.5
0.7
VI=2.7V
Vee= MAX
Vee= MAX,
V
-1.5
0.35
VI=5.5V
TEXAS . •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
V
0.47
Carry input
any output except A = B §
MAX
0.8
IOL =8mA
Mode input
B input
TVPt
0.7
3.4
Carry input
Short-circuit output current,
lOS
Vee= MAX,
MIN'
2
Mode input
Any A or
SN74LS181
MAX
100
IOL
Mode input
input
VIH = 2 V,
OutputI'
Any A or B input
current
IlL
Output G
2.5
IOL = 4 mA
Vee= MIN,
Input
input
TVPt
VIH - 2 V,
All outputs
current at
High-level
IIH
B
Vee - MIN,
Low-level
II
=
MIN
2
High-level output current,
VOL output
voltage
SN54LS181
TEST CONDITIONSt
IlA
~
mA
IlA
mA
mA
mA
SN54LS181, SN74LS181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
switching characteristics, Vee = 5 V, T A = 25°e, (eL = 15 pF, RL = 2 kn, see note 4)
PARAMETERt
FROM
TO
(INPUT)
(OUTPUT)
tpLH
Cn
tpHL
tPLH
Any
tpHL
tpLH
Any
A Of B
C n +4
A or B
C n +4
tPLH
Any
tpHL
tpLH
Any
tpHL
tpLH
Any
G
A or B
G
If. or B
P
tpHL
tpLH
Any
tPHL
tPLH
A orB
P
AiOrBj
Fj
AjorBj
Fj
tPHL
tpLH
tPHL
tpLH
27
20
53 - 4.5 V,
25
38
S1 "S2 " 0 V (SUM model
25
38
M-OV,SO-S3-0V
27
41
~
S1
~
4.5 V (DIFF model
27
41
17
26
(SUM or DIFF model
13
20
~
19
29
M-OV
M " 0 V, 50
~
S1
~
S2
S3
~
4.5 V,
0 V (SUM model
M-OV,SO~S3-0V,
~
S1
M
52
~
~
S1
4.5 V (DIFF model
0 V, 50
51 " 52
~
~
53
~
4.5 V,
0 V, (SUM model
Any
tPHL
A or '8
32
30
20
30
~
22
33
21
32
13
20
21
32
S2
~
~
~
52
S2
M
M
51
21
20
30
4.5 V (DIFF model
~
~
S3 - 4.5 V,
0 V (SUM model
M - 0 V, SO - S3 - 0 V,
A~B
23
32
20
S1
S1
15
21
M-OV,50-S3-0V,
M - 0 V, SO
Fj
AjorBj
S2
v, 50 -
~
~
4.5 V (DIFF model
4.5 V lIogic model
tPHL
tpLH
MAX UNIT
13
Any F
A or B
TYP
18
M- 0
Cn
tpHL
MIN
Cn +4
tPHL
tpLH
TEST CONDITIONS
~
OV,SO-S3
52
~
OV,
4.5 V (DIFF model
21
32
22
33
26
38
33
50
41
62
ns
ns
ns
ns
ns
ns
ns
ns
t/)
Q)
ns
o
oS;
ns
Q)
C
ns
...J
.....
.....
ns
ttPLH ., propagation delay time, low-to-high-Ievel output
tpHL ., propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuits and voltage wveforms are shown in Section 1. Refer to Parameter Measurement Information page for test conditions.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
Vee---"---
A=BOUTPUT
TYPICAL OF ALL OUTPUTS
EXCEPT A = B
-----'1'--
Vee
Vee
INPUT
'L-~~-OUTPUT
OUTPUT
Mode control: Aeq = 17 kfl NOM
AnVAor'B: Req = 5.67 kn NOM
Any 5: Req = 4.25 kn NOM
C n : Req
= 2.86 kn
NOM
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75266
2-607
SN54S181, SN74S181
ARITHMETIC lOGIC UNITS/FUNCTION GENERATORS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Interemitter voltage (see Note 2)
Operating free-air temperature: SN54S181
SN74S181
Storage temperature range
NOTES:
7V
5.5 V
5.5V
_55°C to 125°C
oOe to 70°C
-65°C to 150°C
1. Voltage values, except interemitter voltage, are with respect to network ground termi nal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies to each
conjunction with inputs 52 or 53, and to each
B
A input in
input in conjunction with inputs SO or 83.
recommended operating conditions
SN54S181
MIN
4.5
Supply voltage, Vee
NOM
5
<
(S-
PARAMETER
125
5
0
VIH
High-level input voltage
Low-level input voltage
VIK
Input clamp voltage
Vee- MIN,
11- -IBmA
High·level output voltage,
Vec~
V'H - 2V,
any output except A = B
VIL
High~level
Vee- MIN,
VOH
10H
VOL
output current,
A;: B output only
Low~level
output voltage
Input current at
II
maximum input voltage
High~level
IIH
input
current
Low-level
IlL
input
current
SN54S181
TEST eONDITIONst
VIL
CD
(I)
4.75
MAX
UNIT
5.25
V
-1
mA
20
mA
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
r-
CD
5.5
NOM
20
-55
Operating free·air temperature. T A
C
MIN
-1
High-level output current, 'OH (All outputs except A - B)
Low-level output current, IOL
-f
-f
SN74S181
MAX
MIN
Any S input
~
MIN,
O.B V,
10H
~
VOH~5.5V
VIH-2V,
~
O.B V,
Vee= MAX,
10L
~
Vee= MAX,
20mA
V, = 5.5 V
VI =2.5V
Carry input
MAX
V
V
-1.2
-1.2
V
2.7
3.4
V
250
250
/JA
0.5
0.5
V
1
1
50
50
150
150
200
200
250
250
-2
-2
Any A or B input
-6
-6
Any S input
Vee= MAX,
V,=O.5V
Carry input
any output except A ;: B §
Vee= MAX
Supply current
MAX,
TA~125°e,
See Note 3
J
-40
I All packages
-B
-10
120
220
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAil typical values are at Vee = 5 V, T A=: 25° C.
§Not more than one output should be shorted at a time.
NOTE 3: ICC is measured for the following conditions (the typical and maximum values apply to both):
A. SO through $3, M, and A inputs are at 4.5 V, all other inputs are grounded, and all outputs are open.
B. SO through 83 and M are at 4.5 V, all other inputs grounded, and all outputs are open.
TE~.
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
-100
195
only
See Note 3
-B
-10
-100 -40
W package
UNIT
O.B
Mode input
Vee- MAX,
2-608
TYPt
O.B
3.4
VIH-2V,
Vec- MIN,
VIL
2.5
-1 mA
V'L ~ O.B V,
Vee~
ICC
MIN
2
Mode input
Any A or B input
SN74S181
MAX
2
Short-circuit output current,
lOS
TYPt
mA
/JA
mA
mA
rnA
120
220
SN54S181. SN74S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
switching characteristics, VCC = 5 V, T A = 25°C (CL = 15 pF, RL = 280 n, see note 4)
PARAMETERt
FROM (lNPUTI
tpLH
Cn
tpHL
tpLH
C n +4
Any
A or B
C n +4
tPLH
Cn
tpHL
tpLH
Any
tpHL
tpLH
tpHL
tPLH
tPLH
tPLH
tPHL
tpLH
tpHL
tPLH
tPHL
Any
G
Any
A orB
P
Any
A orB
-
Ai orBj
l'
Fj
AjorBj
f'i
AjorBj
Fi
A orB
- 4.5 V,
83
OV,
TYP
MAX UNIT
7
10.5
7
10.5
12.5
18.5
12.5
18.5
15.5
23
15.5
23
M-OV
7
12
(SUM or DIFF model
7
12
--
Sl "52" 4.5 V (DIFF model
Me OV,SO=S3"4.5V,
8
12
7.5
12
10.5
15
Sl "S2 " 4.5 V (DIFF model
10.5
15
Sl "S2 "0 V (SUM model
M = 0 V,
so - 53 -
0 V,
M - 0 V, SO - S3 - 4.5 V,
7.5
12
Sl "S2 " 0 V (SUM model
7.5
12
M - 0 V, SO - S3 - 0 V,
10.5
15
Sl "82" 4.5 V (DIFF model
10.5
15
M - 0 V, SO - S3 - 4.5 V,
11
16.5
Sl "S2" 0 V ISUM model
11
16.5
14
20
14
22
14
20
M-OV,SO
Any
MIN
Sl "S2" 0 V (SUM model
F
G
A or B
tpHL
tpHL
is. or B
so " S3
M--OV,SO
Any
tpHL
tpLH
MoO V,
A or B
tpHL
TEST CONDITIONS
C n +4
Any
tpHL
tpLH
TO (OUTPUn
Sl
= S2"
M
A~B
Sl
S3
OV,
4.5 V (DIFF model
= 4.5 V (logic model
14
22
M-OV,SO-S3-0V,
15
23
= S2
20
30
" 4.5 V (DIFF model
ns
ns
ns
ns
ns
ns
ns
ns
ns
fIl
(1)
ns
.~
ns
C
>
(1)
..J
ns
l-
t tpLH " propagation delay time, low-to-high-Ievel output
tpHL 50 propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuits and voltage wveforms are shown in Section 1. Refer to Parameter Measurement Information page for test conditions.
I-
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
Vee - - - . . . - - -
TYPICAL OF ALL OUTPUTS
EXCEPT A = B
- - - - - - . - - Vee
A =BOUTPUT
Vee
OUTPUT
INPUT
'---+---QUTPUT
Mode control:
Any A or B:
Any S:
Cn :
Req = 2.8 k!l NOM
Req "" 940 H NOM
Req = 700 n NOM
Req = 560 n NOM
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
2-609
SN54LS181, SN54S181, SN74LS181, SN74S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
PARAMETER MEASUREMENT INFORMATION
SUM MODE TEST TABLE
FUNCTION INPUTS: SO = 153 = 4.5 V. SI = S2
INPUT
PARAMETER
OTHER INPUT
OUTPUT
SAME BIT
UNDER t-:A:::P:::PL:-:y7'i~A=PP::-L7.Y:-+-:-A·::PP:::L""Y"""-A:CP=P::-L::y-j UNDER
TEST
TEST
4.5 V
GND
4.5 V
GND
IpLH
None
Ai
Bi
None
tpHL
Remaining
AandB
Remaining
AandB
None
None
AandB,C n
tpU1
Remaining
None
A and B. en
Remaining
tpHL
Remaining
jj
tpLH
Remaining
Remaining
None
tpHL
tpLH
tplH
rC
None
None
None
Ai
None
None
Bi
PARAMETER
n"
(I)
s,
A,
UNDER
8,
A,
A,
None
tpHL
tPLH
Any F
or C n +4
Remaining
Remaining
S
A,e n
Remaining
Remaining
4.5 V
GND
Remammg
AandB,C n
Remaining
tpHL
tPLH
tpHL
None
None
None
Bi
None
A,
A,
None
fii
fi,
tpLH
A,
None
None
None
None
None
Remaining
F,
In-Phase
Out-of-Phase
A
Ali
None
A andS
Out-of-Phase
G
Ii. andS, Cn
Remaining
In-Phase
G
Remaining
"S,C n
None
In-Phase
Out-af-Phase
A aodS, Cn
Remaining
None
OUTPUT
F,
Remaining
A
A,
OUTPUT
AandB,C n
Remaining
None
Out-af-Phase
Remaining
tPLH
None
Out-af-Phase
APPLY
Remainmg
None
In-Phase
= M =0 V
None
Bi
In-Phase
8
tpHL
A,
In-Phase
All
APPLY
Nane
In-Phase
A
OTHER DATA INPUTS
A,
In-Phase
8
TEST
~
Fi
All
None
INPUT
<
In-Phase
A,e n
DIFF MODE TEST TABLE
FUNCTION INPUTS: SI = S2 = 4.5 V, SO = S3
~
OUTPUT
WAVEFORM
(See Note 4)
e,
Remaining
tpHL
tpLH
-f
-f
=M =0 V
OTHER DATA INPUTS
A
B
tn-Phase
A"B
Out-ot Phase
C n +4
In-Phase
orany F
Remaining
Out-of-Phase
A,B,C n
Remaining
In -Phase
A,B,C n
LOGIC MODE TEST TABLE
FUNCTION INPUTS: SI = S2 = M = 4.5 V, SO
= S3 = 0 V
OTHER INPUT
INPUT
PARAMETER
UNDER
TEST
A,
s,
SAME BIT
OUTPUT
I-A:;P::::P""Ly:;-or:A""PP:::L""'Y:-!---:A:::P"'PL'"'Y"--::A:::PP"L""C
Y' - ; UN DE R
4.5 V
GND
4;5 V
s,
None
None
A,
None
NOTE 4: Load circuits and voltage waveforms are shown in Sectton
2-610
OTHER DATA INPUTS
None
GND
Remammg
A andS, Cn
Remaining
A andB,C n
1.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALl.AS, TEXAS 75265
OUTPUT
TEST
WAVE FORM
(See NDte 4)
F,
Out"of-Phase
e,
Out-of-Phasf!
SN54S182. SN74S182
LOOK·AHEAD CARRY GENERATORS
DECEMBER 1972 ... REVISED MARCH 1988
•
Directly Compatible for Use With:
SN54S182 ... J OR W PACKAGE
SN74S182. . D OR N PACKAGE
SN54lS181/SN74lS181,
SN54S281/SN74S281, SN54S381,
SN74S381, SN54S481/SN74S481
(TOP VIEWI
G1
P1
GO
PO
G3
P3
P
GND
PIN DESIGNATIONS
AL TERNATIVE
DESIGNATIONSt
GO, Gl, G2, G3
GO. Gl. (;2, G3
~-:"2,
P-3
________
PIN NOS.
3,1,14,5
PO,Pl,P?,P3 __
~~?,15.6
FUNCTION
CARRY GENERATE INPUTS
E
S
CARR Y PROP A G AT-INPUT
f--__~C~n~___ +__~~C~n-----~f__-l~~----C n+ x , Cnt-y,
Cn~ z
--~--r---P
--,-o---t-CC'A-R~I,"'Y-:G:-:E:-:N-:E:-:R:-A:-:T:-:E=-=-O"'UCT::-pu-:-r--l
Y
P2
G2
Cn
C n +)(
c:n + y
G
Cn + z
CAfiRY PROPAGATE OUTPUT
,---------.--V?c-.----------t-~1~6--f----------~(,,.,.N"'D'-----------;- 8
~_'".
CARRY INPUT _____
CARRY OUTPUTS
12. 11,9
\icc
___________ ._ _ _
L..-_~
SUPPLY VOL TAGE~
GROUND
___ ._
SN54S182 ... FK PACKAGE
--
(TOP VIEWI
tlnterpretations are illustrated in the LS181, 'S181 dota sheet.
.-- .-- U
u
UN
I"-Ie) Z >1"-
=-
logic symbol:l:
3
CPG
Co
.,
PO
GO
(13)
021
COO
-
111)
Cal
CO2
191
Cn + x
C n +y
Cn+:z
Gl
P2
G2
.3
G3
(]I
CP
2
1 20 19
GO
PO
NC
G2
Cn
NC
G3
P3
C n +x
Cn -y
P
(/j
CD
(.)
>
CD
C
...I
10 11 1213
II-
(10)
CG
G
1"-
t This symbol is in accordance with ANSI/IEEE Std. 91 1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
NC
ou
ZZ
e)
~Ie)
c
U
. No internal connection
description
The 5N545 182 and 5N745182 are high-speed, look-ahead carry generators capable of anticipating a carry across
four binary adders or group of adders. They are cascadable to perform full look-ahead across n-bit adders. Carry, generatecarry, and propagate-carry functions are provided as enumerated in the pin designation table above.
When used in conjunction with the 'L5181 or '5181 arithmetic logic unit (ALUI, these generators provide high-speed
carry look-ahead capability for any word length. Each '5182 generates the look-ahead (anticipated carryl across a
group of four ALUs and, in addition, other carry look-ahead circuits may be employed to anticipate carry across sections
of four look-ahead packages up to n-bits. The method of cascading '5182 circuits to perform multilevel look-ahead
is illustrated under typical application data.
The carry functions (inputs, outputs, generate, and propagatel of the look-ahead generators are implemented in the
compatible forms for direct connection to the ALU. Reinterpretations of carry functions as explained on the 'LS 181
and '5181 data sheet are also applicable to and compatible with the look-ahead generator. Logic equations for the
'5182 are:
C n + x ~ GO + PO C n
Cn + y ~ Gl + Pl GO + Pl PO Cn
Cn +z ~ G2 + P2 G1 + P2 P1 GO + P2 P1 PO Cn
G ~ G3 + P3 G2 + P3 P2 Gl + P3 P2 Pl GO
P ~ P3 P2 Pl PO
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~ar~:I~~e ~~~~~~ti~t" :llo~:~:~:t:r~~s not
or
Cn +x =
Cn +y -Cn+z ~
YO
Yl
Y2
Y = Y3
X = X3
{XO + Cnl
[Xl + YO (XO + Cnll
{X2 + Yl [Xl + YO (XO + Cnl])
(X3 + Y2) (X3 +X2 +Yll (X3 + X2
+ X2 + Xl + XO
.J!}
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
+ Xl +YOI
2-611
SN54S182, SN74S182
LOOK·AHEAD CARRY GENERATORS
logic diagram (positive logic)
GOUTPUT
FUNCTION TABLE FOR
OUTPUT
INPUTS
G3
G2
Gl
GO
P3
P2
Pl
G
L
X
X
X
X
X
X
L
X
L
X
X
L
X
X
L
X
X
L
X
L
L
X
L
X
X
X
L
L
L
L
L
H
All other combinations
FUNCTION TABLE
FUNCTION TABLE
FORPOUTPUT
FOR C n+x OUTPUT
L
L
L
INPUTS
OUTPUT
INPUTS
P3 P2 Pl
OUTPUT
PO
P
GO
PO
Cn
C n+x
L
L
L
X
X
H
X
L
H
H
All other
H
combinations
All other
combinations
-I
-I
P30rX3~(6~)-+~~~-r~-f--l
G30rY3.~(5~)-+~+--+-r~~__~
L
P2orX27.(1~5~)~~--~~+-,-~
FUNCTION TABLE
r-
G2orY2~(~14~)+-~--~~~
FOR Cn +y OUTPUT
C
CD
INPUTS
<
Cr
CD
X
X
X
Cn +v
H
X
L
L
X
X
H
X
X
L
L
H
H
L
(I)
OUTPUT
X
Gl
GO Pl
PO C n
All other
-
combinations
(2)
~lorX17(1~)~-+----rt--~
GlorYl~-+------r*--f-i
L
FUNCTION TABLE FOR Cn +z OUTPUT
INPUTS
OUTPUT
G2
Gl
GO
P2
Pl
PO
Cn
C n+z
L
X
X
X
X
X
X
H
X
L
X
L
X
X
X
H
X
X
L
L
L
X
X
H
X
X
X
L
L
L
H
H
All other combinations
Pin numbers shown are for D, J, N, and W packages.
L
H = high level, L ::: low level, X = irrelevant
Any inputs not shown in a given table are irrelevant with respect to
that output.
2-612
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SN54S182, SN74S182
LOOK-AHEAD CARRY GENERATORS
schematics of inputs and outputs
EOUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
----------~--Vce
50!l NOM
Vee
INPUT
INPUT
Req NOM
Cn
2.8 k!l
1.4 k!l
940 !!
700 !l
400 !l
350 !l
P3
P2
PO,Pl, <33
GO. 84
81
OUTPUT
en
tJ.)
(.)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Interemitter voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54S 182 . . . . . . . . . . . . . . . . . . . . . . . . - 55°C to 125 °e
SN74S182 . . . . . . . . . . . . . . . . . . . . . . . . . . . . ooe to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
'S
tJ.)
C
..J
lI-
NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter input transistor. For these circuits, this rating applies to each
G input in conjunction with any other G input or in conjunction with any 15 input.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-613
SN54S182, SN74S182
LOOK·AHEAD CARRY GENERATORS
recommended operating conditions
SN54S182
MIN
Supply voltage, VCC
NOM
4.5
SN74S182
MAX
MIN
5.5
4.75
5
High-level output current, 10H
NOM
5
MAX
V
-I
rnA
20
rnA
70
°c
-I
Low-level output current, IOl
Operating free-eir temperature, T A
20
125
-55
UNIT
5.25
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54S182
TEST CONDITIONSt
PARAMETER
V,H
High-level input voltage
V,L
V,K
Low-level input voltage
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
"
Input current at maximum input voltage
Cn input
MIN
2
VCC- MIN,
VCC-MIN,
V'L=O.SV,
10H=-1 rnA
VCC=MIN,
V'H=2V,
V,L =O.SV,
10L = 20 rnA
2.5
P2 input
PO, PI, or G3 input
3.4
3.4
0.5
0.5
1
1
50
50
100
100
150
150
200
GO or <32 input
350
350
GI input
400
400
-2
-2
-4
-4
C n input
1'3 input
P2 input
1'0,1'1, or G3 input
VCC=MAX, V, = 0.5V
GI input
Short-circuit output current §
-6
-6
-S
-8
14
-14
-16
-40
VCC= MAX
-100
V
V
V
200
Vcc = MAX, V,=2.7V
UNIT
V
-1.2
2.7
GO or G2 input
lOS
MAX
O.S
-1.2
" = -18mA
V,H -2V,
VCC- MAX, V, = 5.5V
input current
input current
TVP*
O.S
High-level
Low·level
',L
MIN
2
P3 input
"H
SN74S182
TVP* MAX
V
mA
p.A
rnA
-16
-40
ICCH Supply current, all outputs high
VCC- 5 V,
See Note 3
35
65
35
ICCL Supply current, all outputs low
VCC= MAX, See Note 4
69
99
69
-100
rnA
70
109
rnA
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time and duration of the short-circuit test should not exceed one second.
NOTES: 3. ICCH is measured with all outputs open, inputs P3 and G3 at4.5 V, and all other inputs grounded. MAX is determined at 5.5 V.
4. ICCl is measured with all outputs open; inputs GO, Gl, and (32 at 4.5 V; and all other inputs grounded.
*
switching characteristics, Vee = 5 V, TA =25°e
FROM
TO
(lNPUTI
(OUTPUTI
tPlH
GO, Gl, G2, 63,
Cn+x, Cnry,
4.5
7
tPHL
po, PI, P2, or P3
orC n+z
4.5
7
tplH
GO, GI, G2, G3,
tPHl
PI, P2, or P3
PARAMETER
tPLH
TEST CONDITIONS
(i
Rl=2S0n, Cl= 15pF,
PO, PI, P2, or P3
P
Cn
Cn +x , Cnry ,
or Cn+z
See Note 5
tpHl
tPlH
tpHl
NOTE 5: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . . ,
2-614
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
TVP
MAX UNIT
5
7.6
7
10.5
4.5
6.5
6.5
10
6.5
10
7
10.5
ns
ns
ns
ns
TYPICAL APPLICATION DATA
'LS181, '5181, '5281, '5381, or '5481
z
~
t:lr;;1
~~
Z
U1~
,....
e
e
;:00::
::i:o
::z:
rn
64·BIT ALU, FULL·CARRY LOOK·AHEAD IN THREE LEVELS
Remaining inputs and outputs of 'LS 181, 'S 181, 'S281, 'S381, and 'S481 are not shown.
>
e(l)
(")Z
>CZ1
::1:1+>0
::1:1(1)
+>0
-f(l)
e_
::1:1 co
N
m
()l
(I) N
TTL Devices
-t
-t
r-
C
CD
cr C.
§Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
NOTES: 3. ICCL is measured with all outputs open and all inputs grounded.
4. ~CCH is measured with all outputs open and all inputs at 4.5 V.
switching characteristics, Vee = 5 V, TA = 25° C
TEST CONDITIONS
PARAMETER
Propagation delay time, low-to-high-Ievel output
CL=15pF,
tPHL Propagation delay time, high-ta-Iow-Ievel output
See Note 5
tpLH
NOTE 5: Load circuits and voltage waveforms are shown in Section 1.
2-618
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
RL=2kn,
MIN
TYP
MAX
9
15
20
33
SN5419D. SN54191. SN54LS19D. SN54LS191.
SN7419D. 8N74191. SN74LS19D. SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
DECEMBER 1972-REVISED MARCH 1988
SN54190, SN54191, SN54LS190,
SN54LS191 ... J PACKAGE
SN74190, SN74191 ... N PACKAGE
SN74LS190, SN74LS191 ... D OR N PACKAGE
(TOP VIEW)
• Counts 8-4-2-1 BCD or Binary
• Single Down/Up Count Control Line
• Count Enable Control Input
• Ripple Clock Output for Cascading
a
Qa
QA
CTEN
D/U
Qc
QD
GND
• Asynchronously Presettable with Load
Control
• Parallel Outputs
• Cascadable for n-Bit Applications
TYPICAL
TYPE
AVERAGE
PROPAGATION
DELAY
'190:191
'LS190:LS191
20"0
20"0
MAXIMUM
TYPICAL
CLOCK
POWER
FREQUENCY DISSIPATION
25MHz
325mW
25MHz
100mW
VCC
A
ClK
RCO
MAX/MIN
lOAD
C
D
SN54LS190, SN54LS191 ... FK PACKAGE
(TOP VIEW)
U
co u u
dcoz>«
description
The '190, 'lS190, '191, and 'lS191 are synchronous,
reversible up/down counters having a complexity of 58
equivalent gates. The '191 and 'lS191 are 4-bit binary
counters and the '190 and 'lS190 are aCD counters.
Synchronous operation is provided by having all flipflops clocked simultaneously so that the outputs change
coincident with each other when so instructed by the
steering logic. This mode of operation eliminates the
output counting spikes normally associated with asynchronous (ripple clock) counters.
I/)
Q)
U
'S
Q)
o
...I
lI-
NC - No internal connection
The outputs of the four master-slave flip-flops are triggered on a low-to-high transition of the clock input if the enable input is
low. A high at the enable input inhibits counting. level changes at the enable input should be made only when the clock input is high. The direction of the count is determined by the level of the down/up input. When low, the counter count up and
when high, it counts down. A false clock may occur if the down/up input changes while the clock is low. A false ripple carry
may occur if both the clock and enable are low and the down/up input is high during a load pulse.
These counters are fully programmable; that is, the outputs may be preset to either level by placing a low on the load input
and ·entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the
level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count
length with the preset inputs.
The clock, down/up, and load inputs are buffered to lower the drive requirement which significantly reduces the number of
clock drivers, etc., required for long parallel words.
Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count. The
latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when
the counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in width to the lowlevel portion of the clock input when an overflow or underflow condition exists. The counters can be easily cascaded by
feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input
if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed
. operation.
Series 54' and 54lS' are characterized for operation over the full military temperature range of - 55°C to 125'C; Series 74'
and 74lS' are characterized for operation from O°C to 70°C.
PRODUCTIOI DATA d••• ments ••ntain inf.rmati.n
currant 8S of publication date. Products conform to
specifications par the terms of Texas Instruments
:::=~~i~·{::I~~~ ~=:~ti:r :'~O::~:~:t:~~ not
TEXAS •
INSTRUMENTS
POST OFF1CE BOX 655012 • DALLAS, TEXAS 75265
2-619
SN54190, SN54191, SN54LS190, SN54LS191,
SN74190, SN74191, SN74LS190, SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
logic symbols t
'190, 'LS190
CTROV10
112}
MAX/MIN
31CT
= 9}Z6
6,1,4
[lJ
+---,
[2J
[4J
113}RCO
13}
12} °A
16} DS
17} DC
[8J
DO
'191, 'LS191
112}
MAXIMIN
-f
-f
r-
o
CD
(3) D
(2)
A
~.
(')
IS} DS
CD
mOe
en
DO
tThese symbols are accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12,
Pin numbers shown are for D, J, and N packages.
2-620
TEXAS . .
INSTRUMENlS
POST .oFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54190, SN54LS190, SN74190, SN74LS190
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
logic diagram (positive logic)
'190, 'lS190 DECADE COUNTERS
ClK
Diu
(14)
r-
(5)
-
r-i
1
DATA (15)
INPUT A
(4)
I
-
~r
D
I
(13)
rP
(12) MAXIMIN
OUTPUT
"\.
A
s
~
-
lJ
(3)
f----1 ~OU
.--<: >Cl
'--
r--
-
f>-
lK
R
'T
DATA (1)
INPUT B
I
"\.
tJ)
r~
lJ
1 -~ ~Cl
L -
s
Q)
(.)
(2)
~~OU TPUTQB
'S
p-
C
Q)
lK
...I
R
}>-<
DATA (10)
INPUTC
n
lI-
i'
~
I
J
6.
S
r~
-r
r
L
I-- 1J
(6)
----1
OU TPUTQC
~ I>Cl
I--
lK
C)-
R
Y
_oJ
DATA (9)
INPUT D
I
"\.
1s
'-t-=-:1
1"-
lJ
~ lK
171
!-----< OU TPUTQD
I>Cl
pR
h
(11)
J
Pin numbers shown are for D. J. and N packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-621
SN54191,SN54LS191, SN74191, SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
logic diagram (positive logic)
'191, 'LS191 BINARY COUNTERS
(14)
Diu
-
(5)
I
DATA (15)
INPUT A
(4)
-
I
~+
TI-
I
(13)
rP
"\.
f
(12) MAXIMIN
OUTPUT
,l,
S
l - f-- lJ
~ PCl
' - - f-- lK
t- t-
(3)
----i
OU
:>R
y
f
-I
-I
DATA (1)
INPUTB
I
r0-
"\.
<'>
S
r
J
C
-r
CD
<
n"
CD
L
~
-
lJ
DATA (10)
INPUTC
OU TPUTOB
f> Cl
0-
lK
R
n
CII
(2)
----i
I'
I~
f
<'>
S
r
-
(6)
----i
OU TPUTOC
~ ~Cl
L -
~
lJ
P-
lK
R
Y
I
DATA (9)
INPUT D
J
./
A
s
------i
rl-
L:::
...--...
Pin numbers shown are for D, J, and N packages.
2-622
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 6550~.2: • DALLAS, TEXAS 75265
171
----4
i>Cl
lK
pR
-n
111)
lJ
I'
0 UTPUTOD
SN54190, SN54LS19~ SN7419~ SN74LS190
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
'190, 'LS190 DECADE COUNTERS
typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1.
2.
3.
4.
Load (preset) to BCD seven.
Count up to eight, nine (maximum), zero, one, and two.
Inhibit.
Count down to one, zero (minimum!, nine, eight, and seven.
I
L
DATA
INPUTS
I
B-.J
L..
til
I
Q)
(,)
L
C-.J
'>
r
D
Q)
I
C
...J
CLOCK
lI-
DIU,
ffiiii,
,
OB ___
I
,..:-'_ _ _ _~_
...Jr-:L.'-______.....I11
- - - -
I
I
I
~===~~~I
____________ ______ __________
~
-- -..,
OD ____
_;
LiJI!
~~
I
_.....Ir___
L-
L
== _...;:....:.._--IIlL._____.;-.____
I I
MAXIMIN
=~IL.
---~
I
I I
I
I I
RCO - - - - ,
Il
..:....._,:-_....I
U
8
9
I
I
0
2
2
2
I I ..
I·---COUNT UP - - -...
·I_INHIBIT--I
~
I
I
I----
U
0
9
COUNT DOWN
8
7
-----<~..
LOAD
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-623
SN54191, SN54LS191, SN74191, SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
'191, 'LS191 BINARY COUNTERS
typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1.
2.
3.
4.
Load (preset) to binary thirteen.
Count up to fourteen, fifteen (maximum), zero, one, and two.
Inhibit.
Count down to one, zero (minimum), fifteen, fourteen, and thirteen.
Ti5AD-U
I
I
A-.J
I
L..._
I
I
r-
-I --
I
B
-4
-4
I--
I
I
DATA
INPUTS
r-
0
L...._
C-.J
I
<
c;"
-
--
-'
L..._
D-.J
CD
CLOCK
CD
tn
DiU!
I I
I I
CTEN !
,, ,,
I I
I
I
I'
L...i1I 'i-..,----,
- - .,
OB ___
Oc __
- --I
...J
00 -
--I
- --I
--..,LI_":"';_ _.J1
~
MAXIMIN ___
~
I'"'_ _ _ _-:_ _ _ _-:-_~-.....I
U
RCO::]
: 13
14
15
I
I
:
0
2,
:
2
I~·-INHIBIT
I
I·-----COUNT
..
U P - - - ·..
~
2
--I
LOAD
2-624
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
I
1
1.._ _ _ _ _ __
u
0
J..----COUNT
15
14
13
DOWN----·~I
SN54190. SN54191. SN54LS190. SN54LS191.
SN74190. SN74191. SN74LS190. SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . .
Input voltage: SN54', SN74' Circuits. . .
SN54LS', SN74LS' Circuits.
Operating free·air temperature range: SN54', SN54LS' Circuits.
SN74', SN74I:.S' Circuits.
Storage temperatu re range
7V
5.5 V
7V
. - 55°C to 125°C
O°C to 70°C
. _65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
Vee
Supply voltage
10H
High-level output current
SN54190, SN54191
SN74190, SN74191
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
- 0.8
mA
- 0.8
16
UNIT
16
mA
20
MHz
10L
Low-level output current
fclock
Input clock frequency
'wlclock)
Width of clock input pulse
25
25
'wlload)
Width of load input pulse
35
35
ns
'su
Setup time
20
20
20
20
ns
'hold
TA
Data hold time
20
0
I Data, high or low (See Figure 1 and 2)
I Load inactive state
0
ns
0
0
-55
Operating free-air temperature
ns
125
'e
70
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST eONDITIONSt
VIH
High-level input voltage
Vee
VIL
Low-level input voltage
Vee - MIN
VIK
Input clamp voltage
Vee
VOH
High-level output voltage
VOL
Low-level output voltage
~
~
SN54190, SN54191
SN74190, SN74191
MIN
MIN
MIN
MIN,
TYP:j: MAX
2
2
11=-12mA
Vee - MIN,
VIH-2V,
VIL = 0.8 V,
10H = - 0.8 mA
Vee - MIN,
VIH - 2V,
VIL = 0.8 V,
10L = 16mA
Vee = MAX,
VI = 5.5 V
2.4
TYP:j: MAX
V
0.8
0.8
V
-1.5
-1.5
V
3.4
0.2
UNIT
2.4
3.4
0.2
0.4
V
0.4
V
High-level input current at
II
maximum input voltage
1
1
mA
40
40
!J.A
120
120
!J.A
-1.6
-1.6
mA
-4.8
mA
-65
mA
105
mA
High·level input current
IIH
at any input except enable
High·level input current
IIH
Vee
~
MAX,
VI" 2AV
at enable input
Low·level input current
IlL
at any input except enable
Low·level input current
IlL
Vee
0
MAX,
VI=OAV
-4.8
at enable input
lOS
Short·circuit output current §
Vee = MAX
lee
Supply current
Vee- MAX,
-·20
See Note 2
-65
65
99
-18
65
tFor conditions shown as MAX or MIN, use appropriate value specified under recommended operating conditions.
tAli typical values are at Vee == 5 V, T A'=' 25°C.
§Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all inputs grounded and all outputs open.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
2-625
SN5419~ SN54191, SN7419~ SN74191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETERt
FROM
TO
(INPUT)
(OUTPUT)
'190. '191
TEST CONDITIONS
f max
tpLH
tpHL
tpLH
tpHL
tPLH
Load
0A. 0B. 0e. 00
Data A. B. e. 0
0A. 0B. 0e. 00
ClK
tPLH
tpHl
tpLH
tPHL
tpLH
tpHL
RL
~
400
TYP
20
25
n.
See Figures 1 and 3 thru 7
CLK
0A. DB. DC. 00
tPHL
tpLH
CL~15pF.
RCO
tpHL
MIN
MaxIMin
CLK
Diu
RCO
DIU
MaxIMin
33
33
50
14
22
35
50
13
20
16
24
16
24
24
36
28
42
37
52
30
45
30
45
21
33
22
33
=-
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
vcc--------e-------
---+--___ v CC
Req
INPUT
...-----OUTPUT
kn NOM
kn NOM
Enable input: Req = 1.3
All other inputs:
2-626
Req = 4
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
UNIT
MHz
22
t f max
maximum clock frequency
tpLH '" propagation delay time. low-to-high-Ievel output
tPHL .. propagation delay time. high-to-Iow-Ievel output
EQUIVALENT OF EACH INPUT
MAX
ns
ns
ns
ns
ns
ns
ns
SN54LS190. SN54LS191. SN74LS190. SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
recommended operating conditions
SN74LS190
SN54LS190
SN74LS191
SN54LS191
Vee
Supply voltage
IOH
High-level output current
MIN
NOM
4.5
5
MAX
MIN
NOM
5.5
4.75
5
UNIT
MAX
-0.4
5.25
V
- 0.4
mA
4
8
mA
20
MHz
IOL
Low-level output current
fclock
Clock frequency
tw(clock)
Width of clock input pulse
25
25
ns
tw(load)
Width of load input pulse
35
35
ns
'su
Data setup time (See Figures 1 and 2)
20
20
ns
'su
Load inactive state setup time
30
30
ns
'h
th
Data hold time
5
5
ns
Enable hold time
0
0
ns
tenable
Count enable time (see Note 3)
40
40
TA
Operating free-air temperature
0
20
-55
0
125
ns
"e
70
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN74LS1~O
SN54LS190
PARAMETER
TEST CONDITIONSt
SN54LS191
MIN
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
High-level input
input voltage
High-level
IIH
input current
input current
11--18mA
Vee- MIN,
VIH = 2 V,
Vee - MIN,
VIH=2V,
VIL = VIL max
2.5
Vee= MAX,
Enable
I - - - Vee = MAX,
Others
Enable
I Others
Vee
0
MAX,
lOS
Short-circuit output current §
Vee= MAX,
ICC
Supply current
Vee= MAX,
UNIT
0.8
V
-1.5
V
0.4
I'OL = 8mA
3.4
Q)
o
...J
V
0.25
0.4
0.35
0.5
0.3
0.3
0.1
0.1
60
60
20
20
-1.2
-0.4
-1.2
-0.4
VI = 7 V
Q)
'S:
V
0.7
2.7
In
U
TYP* MAX
-1.5
3.4
0.25
I'OL - 4 mA
MIN
2
Enable
r--Others
Low-level
IlL
Vee - MIN,
VIL = VIL max, IOH = -4001lA
VOL Low-level output voltage
current at maximum
SN74LS191
MAX
2
VOH High-level output voltage
II
TYP*
lI-
V
mA
VI=2.7V
VI =O.4V
-100
-20
See Note 2
20
-20
35
20
IlA
mA
-100
mA
35
mA
tFor conditions shown as MAX or MIN. use appropriate value specified under recommended operating conditions for the applicable device
type.
tAli typical values are at Vee
!:l Not
= 5
V. T A
=:
25°C.
more than one output should be shorted at a time. and duration of the short-circuit should not exceed one second.
NOTES: 2. ICC is measured with all inputs grounded and all outputs open.
3, Minimum count enable time is the interval immediately preceeding the
rising edge of the clock pulse during which interval the
count enable input must be low to ensure counting.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-627
SN54LS190, SN54LS191, SN74LS190, SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
switching characteriStics, Vee =5 V. r A = 25°e
FROM
(INPUT)
PARAMETERt
TO
(OUTPUT)
'LS190, 'LS191
UNIT
MIN TVP MAX
TEST CONDITIONS
f max
tpLH
tPHL
tpLH
tpHL
-I
-I
....
C
(I)
<
(;'
tpLH
tpHl
tPlH
tpHl
tplH
tpHl
tPlH
tpHl
tPlH
tpHl
tplH
tpHL
20
Load
. 0A. 0B. OC, 00
Data A, B. C, 0
0A. 0B. 0C, 0D
ClK
RCO
CL· 15 pF, Rl· 2 kO,
See Figures 1 and 3 thru 7
ClK
0A. 0B. OC. 00
ClK
MaxIMin
DIU
RCO
DIU
MaxIMin
CffiJ
RCO
25
22
33
20
27
13
16
16
24
28
37
30
30
21
22
21
22
t f max
.II maximum clock frequency
tpLH • propagation delay time, low-to-high-Ievel output
tpHL .. propagation delay time. high-to-Iow-Ievel output
schematics of inputs and outputs
(I)
en
EQUIVALENT OF EACH INPUT
TVPICAL OF ALL OUTPUTS
---~_-Vcc
1200 NOM
VCC------~~--------
..,.... +-_.... __
INPUT~HIW
....
l--+-OUTPUT
Enable Input: Req = 8.33 k(l NOM
Load Input: Req = 25 kG NOM
All other inputs: Req = 17 kO NOM
2-628
.' TEXAS ."
INSTRUMENTS
~ST OFFICE BOX 65501'2 • DALLAS. TE)EAS 75265
MHz
33
50
32
40
20
24
24
36
42
52
45
45
33
33
33
33
ns
ns
ns
ns
ns
ns
ns
ns
SN54180, SN54181, SN54LS180, SN54LS181,
SN74180, SN74181, SN74LS180, SN74LS181
SYNCHRONOUS UP/OOWN COUNTERS WITH OOWN/UP MODE CONTROL
PARAMETER MEASUREMENT INFORMATION
OUTPUT
VCC
(SEE NOTE BI
MAXIMIN.
RIPPLE CLOCK.,----+....,~-......................h
CA. CB. Ce. OR Co
CL=15pF
(SEE NOTE AI
1.,..
FIGURE I-LOAD CIRCUIT
FOR SWITCHING TIME MEASUREMENT
......,j
~N~~~
JEvlll!r~::m~.~---------~9~~::':'r'!!l~i--- ----------- 3V
(SEE NO_T_E_C_'_....;.10;,;%.;..;3J'¥!
v,
-'"'?
'" 10~i!
1
LOAD
INPUT
(SEE NOTE CI
~.; 10 ns
--.J
-I
"--.; 10 ns
I
1
10%
--1 f---.;
90%
~ .; 10 ns
I
l\k
1 .;.;.;.;---1------
.-.
.
.
.
,
"1~it=-------::
1
--..I
o OUTPUT
·af
I
OV
10 ns
~::
'/
FIGUTE 2·DATA SETUP TIME VOLTAGE WAVEFORMS
~';10ns
-..I
~
I
1
1
..r-9O%--~9O%~!!I.:--1--
- - - --- 3 V
I
INPUT
(SEE NOTECI
_ _......
10%.-.,;;;r 1
1
10%
~";';';""-----OV
1
1
t+-tpLH-+i
1
NON INVERTING
OUTPUT
1
1
I
- - - - VOL
_---VOH
INVERTING
OUTPUT
VOL
Sea waveform sequences in figurll4 through 7 for propagation time, from 8 specific Input to a specific output. For ,Implication. puis.
rl •• tlmas, refer.neelevels, etc., have not been shown In figures 4 through 7.
FIGURE 3·GENERAL VOLTAGE WAVEFORMS FOR PROPAGATION TIMES
NOTES: A. CL include. probe and jig capacitance.
B. All diodes are 1 N3064 or equivalent.
C. The input pulses. are supplied by generators having the following characteristics: Zout" 50
O. Vraf - 1.5 V for '190 and '191 j 1.3 V for 'LS190 and 'LS191.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAUAS, TEXAS 75266
n. duty cycla <: 60%, PRR .;;; 1 MHz.
2-629
SN54190. SN54191. SN54LS190. SN54LS191
SN74190. SN74191. SN74LS190. SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
PARAMETER MEASUREMENT INFORMATION (continued)
LJ
LJ
I
I
ANY DATA INPUT_ _ _ _ _ _- - J
,-!,I
j
CORRESPONDING---- - Q OUTPUT
- - - - - - L-_ _ _.....
tpLH ~
:-
-I
I
I
I
-:
I
!-I_ __
I
I
--! :- tpHL
:-tPHL
NOTE E: Conditions on other inputs are irrelevant.
FIGURE 4-LOAD TO OUTPUT AND DATA TO OUTPUT
~
D/U
CLOCK
~
~
CTEN
r-
RCO
(1)
<
e:;'
I
I
I
I
I
tPHL--l
0
l-
I
I
I
I
I
I
~
:-tPLH
I
tPHL-:
(4-
I
I
tpLH --t
r-
I
MAX/MIN
(1)
VI
II
NOTE F: All data inputs are low.
FIGURE 5-ENABLE TO RIPPLE CLOCK, CLOCK TO RIPPLE CLOCK, DOWN/UP TO RIPPLE CLOCK, AND DONN/UP TO MAX/MIN
2-630
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54190. SN54191. SN54LS190. SN54LS191.
SN74190. SN74191. SN74LS190. SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
PARAMETER MEASUREMENT INFORMATION (continued)
switching characteristics (continued)
U
--r----------------_
DATA
INPUTS
- _
- _
- _- _ -_ _
- _- _-_ _
- _
- _
- _.....J ___
(SEE
NOTES
G TO 1I-_ -_ _
1
Diu
~_:~I~~-t~PL~H~---------~-~:-;~tPHL
COUNT
L-_ _ _ _ _
OUTPUT(SI UNDER IEITl
ENABLE
NOTES:
~
I
•
L.I_ _ _ _ _ _ _ __
LOW
G. To test QA. as. and QC outputs of '190 and 'LS190: Data inputs A, B. and C are shown by the solid line. Oats input 0 is shown
by the dashed line.
H. To test QO output of '190 and 'LS190: Data inputs A and 0 are shown by the solid line. Data inputs Band C are held at the tow
logic level.
I.
To test QA.
aS. 0c. and QO outputs of '191
and 'LS191: All four data inputs are shown by the solid line.
FIGURE 6-CLOCK TO OUTPUT
u
DATA A
I _________ _
DATA B, C, AND D
(SEE NOTE_J_I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _...
DIU
COUNT
l::!---li-I
:-tPLH
MAX/M.,;;,IN;....-_ _ _
L::J
:-tPHL
~
:-tPLH
~
l-tPHL
~;;;';"'--'--;L..I________.....Ii-~..;..---..J"--;L_
ENABLE = LOW
NOTE J: Data inputs Band C are shown by the dashed line for the '190 and 'LS190 and the solid line for the '191 and 'LS191: Data input 0
is shown by the solid line for both devices.
FIGURE 7·CLOCK TO MAXIMIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2·631
-I
-I
r-
oCD
:::.
"en
CD
2-632
SN54192. SN54193. SN54LS192 SN54LS193.
SN74192. SN74193. SN74LS192. SN74LS193
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
DECEMBER 1972 _. REVISED MARCH 1988
• Cascading Circuitry Provided Internally
SN54192, SN54193, SN54LS192,
SN54LS193 ... J OR W PACKAGE
SN74192, SN74193 ... N PACKAGE
SN74LS192, SN74LS193 ... 0 OR N PACKAGE
(TOP VIEW)
• Synchronous Operation
• Individual Preset to Each Flip-Flop
• Fully Independent Clear Input
8
TYPES
'192:193
'LS192:LS193
TYPICAL MAXIMUM
COUNT FREOUENCY
32 MHz
TYPICAL
POWER OISSIPATION
325mW
32 MHz
95 mW
VCC
A
CLR
80
CO
LOAD
C
D
Q8
QA
DOWN
UP
QC
QD
GND
description
These monolithic circuits are synchronous reversible
(up/down) counters having a complexity of 55
equivalent gates. The' 192 and 'LS 192 circuits are
8CD counters and the '193 and 'LS 193 are 4-bit
binary counters. Synchronous operation is provided
by having all flip-flops clocked simultaneously so that
the outputs change coincidently with each other when
so instructed by the steering logic. This mode of
operation eliminates the output counting spikes which
are normally associated with asynchronous (rippleclock) counters.
SN54LS192, SN54LS193 ... FK PACKAGE
(TOP VIEW)
U
ID
U U
OIDZ>«
II)
Q)
3 2 1 20 19
U
5
6
The outputs of the four master-slave flip-flops are triggered by a low-to-high-Ievel transition of either count
(clock) input. The direction of counting is determined by
which count input is pulsed while the other count input
is high.
'S
CLR
80
NC
CO
LOAD
4
8
Q)
o
....I
lI-
9 10111213
00 U 0
OZZ
U
(.!)
All four counters are fully programmable; that is, each
NC - No internal connection
output may be preset to either level by entering the
desired data at the data inputs while the load input is
low. The output will change to agree with the data inputs independently of the count pulses. This feature
allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.
A clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function is
independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements.
This reduces the number of clock drivers, etc., required for long words.
These counters were designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are
available to cascade both the up- and down-counting functions. The borrow output produces a pulse equal in width to the
count-down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count-up
input when an overflow condition exists. The counters can then be easily cascaded by feeding the borrow and carry outputs
to the count-down and count-up inputs respectively of the succeeding counter.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
I
SN54'
SN54LS'
7
7
5.5
7
I
-55 to 125
-65 to 150
I
Supply voltage, Vee (see Note 1)
Input voltage
Operating tree-air temperature range
Storage temperature range
I
I
I
SN74LS'
7
7
o to 70
-65 to 150
SN74'
7
5.5
UNIT
V
V
°e
°e
NOTE 1: Voltage values are with respect to network ground terminal.
PROOUCTIO. DATA do•• mlnlS .ont.in inform.tion
•• rrant .1 of pullileotio. d.ta. PredgclS .onform to
.peciflcatiDns ..... the tIIrml at TI.I. Instruments
:::=~~I~'{nr:I~'~ ~~:~ti:r :.~u::::~:.' nat
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-633
SN54192, SN54LS192, SN74192,SN74LS192
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
logic diagram (positive logic)
(131
BO
DATA...:(~15~1--------~ittt=t~~--~~__- .______-,
rL-'
INPUT A
DOWN...:(~41____~~~~-H*++-+-+r__~
V
(51
UP
DATA
INPUT B
rf
(31
1-......- - - - - OUTPUT
0A
>+---+~T
~
(II
~
------------1;:fl::f:f:f=f=fF.r3-L..,.r1-»---.......----f---,-4S
-
~
-I
-I
(21
1--_--..:...:.... OUTPUT 0B
If
>+----+~T
u.m:~_L.)
rC
CD
<
n'
CD
DATA
Vl
INPUTC
(IO~I_-iWE~p.~b~~~::u
~
~
+t-t+-+I-i:±:=;O=3_-,
h
+ ..:.'-.
jl-o--...----'
(61
OUTPUT
°c
-
1(~91~------~dJJJ~iiif~~~~~~~~~==~
DATA
INPUT
D"':
'\.
J
CLR -'.(1_4-'..1----I-{>o-I
>o.....
U-t=::t=:t=:~f=t~-.J
~-
+t--.-----'-.:..(7)
R~
LOAD-(I-I-I--~>--J~ii======~~~--~~i:~~I=='~~
Pin numbers shown are for D, J, N, and W packages.
2-634
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
OUTPUT °D
SN54193, SN54LS193, SN74193, SN74LS193
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
logic diagram (positive logic)
(131
~
(121
co
-.~~
~~
DATA
I NPUT A
....
--~~~~
BO
(15)
--~~~~--;::I=I=:I=I=:I=I=HH=f~p-~·-4~-
DOWN
(41
UP
(51
(3)
-- ..- - - - OUTPUT QA
--\=-__-~.-._<--~-.--
IN~~; ~ ~2...~_._ ~U+t+t+t++=+==1-
-----
121
.~--
C/)
Q)
OUTPUT QB
(.)
'S
Q)
o
...J
lIDAT A
~ __. ____ _
l=tiiHt+tI=t
I N PUT C
DATA
191
~~".-----
INPUT D
CLR
17!
- - - OUTPUT QD
Pin numbers shown are for D, J, N, and W packages.
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-635
SN54192, SN54193, SN54LS192, SN54LS193
SN74192, SN74193, SN74LS19t SN74LS193
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
logic symbols t
'193
'192
CTRDIV 16
CTRDIV 10
2+
DOWN
A
B
C
D
(31
[1]
(1)
(2) QA
[2]
(10)
(9)
(6) Qs
[4]
(7) Qc
[8]
QD
A
[1]
B
[2]
C
[4]
D
[81
tThese svmbols are in accordance with ANSI/IEEE Std. 91-1984 and lEe Publication 617-12.
Pin numbers shown are for D, J; N, and W packages.
schematics of inputs and outputs
-t
-t
r-
TYPICAL OF OUTPUTS
OF '192, '193
EQUIVALENT OF INPUTS
OF '192, '193
C
Vce
CD
<
n'
CD
en
.
V C CReq
3-INPUT
.
-OUTPUT
'192, '193: ReQ
'192, '193: R = 130 n NOM
= 4 kn NOM
TYPICAL OF OUTPUTS
OF 'LSI92, 'LS193
EQUIVALENT OF INPUTS
OF 'LSI92, 'LS193
Oot Req
INPUT
- - -.......-Vee
--
Vee
i u-
120 n NOM
-'------"-- OUTPUT
~11
,
Load Input: Req - 25 kn NOM
All other Inputs: Req = 17 kn NOM
2-636
TEXAS.
INSTRUMENTS
P,?ST OFFICE BOX 655012 • DALLAS, TEXAS 75285
SN54192. SN54LS192. SN74192. SN74LS192
SYNCHRONOUS 4·81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
'192, 'LS192 DECADE COUNTERS
typical clear, load, and count sequences
Illustrated below is the following sequence:
1.
2.
3.
4.
Clear outputs to zero.
Load (preset) to BCD seven.
Count up to eight, nine, carry, zero, one, and two.
Count down to one, zero, borrow, nine, eight, and seven.
u
I
L-
I
'---:---:-'1 L-
CI)
(1)
(J
0>
...-----..,,I
L-
(1)
I
- -_ _ _ _ _
C
r- -
-J
~I
lI-
°A
I
°B
I
=:1
==:1
=:1
~--------~~
I
I
OUTPUTS
°c
L -_ _ _ _ _ _ _ _ _ _
~_ _~_ _ _ _ _ _ _ _ _ _~~
I
°0
co
I
~
u
1ffi
I
SEQUENCE
ILLUSTRATED
NOTES:
10 1
I
17
~~
I
I
r-8
9
0
CQUNTUP
~
A. Clear overrides load, data, and count inputs.
B. When counting up, count-down input must be high; when counting down. count-up input must be high.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-637
SN54193, SN54LS193, SN74193, SN74LS193
SYNCHRONOUS 4·81T UPIDOWN COUNTERS (DUAL CLOCK WITH CLEAR)
'193, 'LS193 BINARY COUNTERS
typical clear, load, and count sequences
Illustrated below is the following sequence:
1.
2.
3.
4.
Clear outputs to zero.
Load (presl\t) to binary thirteen.
Count up to fourteen, fifteen, carry, zero, one, and two.
Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
CLR~
I
I
I
LciAi5
A
u
- - - - - - - - - - - - - - -.-J,..---:----;1~---------------I
-I
-I
_ _-:---:-_"":""..JI~---------------______ - - _______ - -
r-
DATA
C
C
CD
<
D
en
UP
n'
CD
DOWN
,..----....:....-;1- -
.J
-
-
-
-
-
-
-
--- -
----
I~----------------
- - - -- - - - - -- - ---.-J.--:--"---:-';,~---------------I
L..flJLS1JLJ
I
I
°A
I
°B
I
:.J
=:1
~
I
I'
OUTPUTS
Oc
=-,
I
°D
co
u
U
60
I
SEOUENCE
ILLUSTRATED
NOTES:
T
,0
14
13
1
~ COUNT D O W N - - - '
A. Clea' overrides load, data, and count inputs.
8. When counting UP. count-down input must be high; when counting down, count-up Input must be high.
2-638
I
15
TEXAs . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
SN54192. SN54193. SN74192. SN74193
SYNCHRONOUS 4·BIT UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
recommended operating conditions
Vee
Supply voltage
10H
High-level output current
SN54192
SN74192
SN54193
SN74193
MIN
NOM
4.5
5
MAX
MIN
NOM
5.5
4.75
5
UNIT
MAX
-0.4
5.25
V
-0.4
rnA
16
16
rnA
25
MHz
10L
Low-level output current
fclock
Clock frequency
tw
Width of any input pulse
20
20
ns
tsu
Data setup time, (see Figure 1 )
20
20
ns
th
Hold time
TA
Operating free-air temperature
25
0
I
I
0
Data, high or 10~
0
0
LOAD
3
3
-55
125
ns
"e
70
0
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
TEST eONDITIONst
PARAMETER
SN54192
SN74192
SN54193
SN74193
MIN
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
MAX
Vee = MIN,
11=-12mA
Vec = MIN,
VIL = 0.8 V,
VIH=2V,
10H = -0.4 rnA
Vce = MIN,
VIH = 2 V
VIL =0.8V,
IOL=16mA
2.4
MIN
TYPt
UNIT
MAX
2
2
High-level output voltage
VOH
TYPt
V
0.8
V
Q)
-1.5
-1.5
V
'S
V
c
.....
2.4
3.4
0,2
3.4.
0.2
VOL
Low-level output voltage
II
Input current at maximum input voltage
Vce=MAX,
VI = 5.5 V
1
1
mA
IIH
High-level input current
Vee = MAX,
VI=2.4V
40
40
/JoA
IlL
Low-level input current
Vee - MAX,
VI-O.4V
-1.6
rnA
lOS
Short-circuit output currentS
Vee = MAX
lee
Supply current
Vee - MAX, See Note 2
0.4
-1.6
-20
CIl
0.8
-65
65
-18
89
65
0.4
CJ
Q)
V
-65
rnA
102
mA
lI-
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
!AII typical values are at Vee = 5 V, T A = 25'-'C.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all outputs open, clear and load inputs grounded, and all other inputs at 4.5 V.
switching characteristics, Vee
PARAMETER II
=
5 V, T A = 25° C
FROM
TO
INPUT
OUTPUT
UP
CO
DOWN
60
TEST CONDITIONS
f max
tpLH
tpHL
tpLH
tpHL
eL=15pF,
RL =400n,
tpLH
Q
UP OR DOWN
See
Figures 1 and 2
tpHL
--
tpLH
tpHL
tpHL
LOAD
Q
eLR
Q
MIN
TYP
25
32
MAX
UNIT
MHz
17
26
16
24
16
24
16
24
25
38
31
47
27
40
29
40
22
35
ns
ns
ns
ns
ns
~fmax :=::: maximum clock frequency
tpLH
== propagation
tpH L
~
delay time, low·to-high·level output
propagation delay time, high·to·low-Ievel output
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·639
SN54LS192, SN54LS193, SN74LS192, SN74LS193
SYNCHRONOUS 4·BIT UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
recommended operating conditions
SNS4LS1ez
SN74LS1ez
SNI54LS183
VCC
Su pply voltage
IOH
Hlgh·level output current
10L
Low-level output current
fclock
tw
Clock frequency
t.u
MIN
NOM
4.5
6
SN74LS183
MAX
MIN
NOM
6.5
4.75
5
-400
UNIT
MAX
5.25
V
-400
,.A
8
mA
25
MHz
4
0
25
0
Width of any Input pul.e
20
20
n.
I
Clear inactlve·.tate .etup time
15
15
n.
I
Load inactive-state setup time
Oata .etup tim. (,•• Figure 1)
16
15
ns
20
20
ns
5
5
0
n.
J
th
Data hold time
TA
Operating free-air temperature range.
125
65
70
'c
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
~
oCD
r<
C:;'
CD
fII
SN54LS1ez
SN54LS193
TEST CONDITIONSt
MIN
VIH
VIL
High-level input voltage
VIK
Input clamp voltage
SN74LS192
SN74LS193
TVP* MAX
2
MIN
V
2
Low-level input voltage
0.7
VOH High-level output voltage
VCC~MIN,
11=-18mA
VCC~MIN,
VIH = 2V,
-1.5
VIL = VIL max, 10H = -400,.A
VCC=MIN,
VIH- 2V,
POL =4mA
VOL Low·level output voltage
VIL =VILmax
UNIT
TYP* MAX
2.5
3.4
2.7
0.25
0.4
IIOL=8mA
0.8
V
-1.5
V
3.4
V
0.15
0.4
0.35
0.5
V
II
Input current at maximum
input voltage
VCC=MAX,
VI =7 V
0.1
0.1
IIH
High-level input current
VCC=MAX,
VI=2.7V
20
20
,.A
IlL
Low-level input current
VCC=MAX,
VI = 0.4 V
Short-Circuit output current §
VCC~MAX
-0.4
-100
mA
lOS
-0.4
-100
ICC
Supply current
VCC=MAX,
34
mA
-20
See Note 2
19
-20
19
34
mA
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
= 5 V, T A = 2SoC.
§Not more than one output should be shorted at a time ,and duration of the short~clrcuit should not exceed one second.
NOTE 2: ICC is mealured with all outputs open, clear and load inputs grounded, and all other in'puts at 4.5 V.
tAil typical values are at Vee
switching characteristics, Vee =5 V, T A =25° e
PARAMETER
FROM
TO
INPUT
OUTPUT
TEST CONDITIONS
f max
tPLH
tpHL
tPLH
CO
BO
CL" 15pF,
UP OR DOWN
Q
AL=2kSl,
See Figures 1 and 2
tPLH
tpHL
LOAD
Q
tpHL
CLA
Q
tpHL
tpLH
tpHL
2-640
UP
OOWN
TEXAS·'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
TVP
25
32
MAX UNIT
MHz
17
18
26
24
16
24
15
24
27
30
38
24
40
25
40
23
35
47
ns
ns
ns
ns
ns
Q"}
°c
. - - - - 0B
VCC
I
.----- °A
T
DATA
PULSE
GENERATOR
(See Note AI
(3
'"
-I
~
"'~Z
~~
~~~
;; C~
~~
~!"'I
~Z
CLEAR
PULSE
GENERATOR
(See Note Al
1
r-- A
~
1
BO
OPEN
CO
OPEN
B
0A
C
°B
I..- o
0c
H~
LOAD
PULSE
GENERATOR
(See Note Al
r-------- - - - - - - -
UP
DOWN
CLR
00
I
I
I
~
II 1 (S~e
. .., ..
I
~
I
I
I
I
I
(See Note CI
.lc
Note BI
-
I
.,
_J
r----
~
L ___ .
~ Ul4r
r---'
I
.,
_J
----iL ____
.'"'"
~
~
r---·
L ___ ~=~~~=~~
~
I
...J
.,
___ J
TEST CIRCUIT
NOTES: A. The pulse generators have the following characteristics: Zout ~ 50 II and for the data pulse generator PRR '" 500 kHz. duty
cycle = 50%; for the load pulse generator PRR is two times data PRR. duty cycle = 50%
B. CL includes probe and jig capacitance.
C. Diodes are 1 N3064 or equivalent.
D. tr and tf '" 7 ns.
E. Vrel is 1.5 V for '192 and '193,1.3 V for 'LS192 and 'LS193.
FIGURE 1A - CLEAR, SETUP AND LOAD TIMES
.,
I
I
RL
IL ____
LOAD
~
OUTPUTS
;g
:lJ
l>
3:
m
-I
m
:lJ
3:
m
en
l>
c
:lJ
m
3:
m
2
-I
Z
"TI
0
:lJ
3:
l>
-I
a2
en
<
2
n
:z:
:.
a
2
a
C
en
of"
IIZII
=t
C
.:!!
aenen
a2 2
=e .... c:n
201:iool:io
nCDCD
a.!"'.!'"
ien en
-4
m 22
.... c:n
:.oI:iool:io
en-caCD
--
6~~
cenen
2
"'2
r- .... c:n
nol:iool:io
r-r-raenen
n-~CDCD
=e~.!'"
_enen
-422
:z: .... c:n
nol:iool:io
r-r-rm enen
:.CDCD
_w~
,.,--
I\l
C,
""
~
TTL Devices
sao!l\ao 11.1.
I'.)
m
en en en
.j>.
I'.)
-<22
2 ..... UI
noliloolilo
:-::a mm
CI.!"-'.!"-'
tr -.l
-..t1 II.- tf
k-
1
2enen
Cl
22
1
C
CLR
2i
DATA
INPUT
~z
~~
g;:tlr;;1
;:;C:~
;~
~!"I"I
~z
~Ul"
10%
I
Vref
I'
~ ~tr
I
~:90%
I
10%
1
I"
OUTPUT
Vref
I1
~ tf
---+----'""'="'90""%,;;,::3k, 1
I
---l
I*-
'-.l ~
'
~Vref
V.• f !*90%
i~ 10%
10%
~tPLH
1
10%
~I
I . .
tsu
~
tpHL
Q
90%~-:----------------- 3V
Vref
71""
-.J
------~--------
1
~I
tsu
\..,
V.. !*90%
3V
f
j"\
j-..-t
r
1~1
"~
OV
~Vref
f.,.--tPHL
/ I Vref
In
-I
m
:s:
m
~
c:
_ _ _ _ VOH
:D
'-.______ VOL
:s:
m
m
NOTES: A. The pulse generators have the following characteristics: Zout ~ 50 Il and for the data pulse generator PRR
cycle = 50%; for the load pulse generator PRR is two times data PRR, duty cycle = 50%
B. CL includes probe and jig capacitance.
C. Diodes are 1 N3064 or equivalent.
D. tr and tf :S 7 ns.
E. Vref is 1.5 V for '192 and '193,1.3 V for 'LS192 and 'LS193.
FIGURE 1B - CLEAR, SETUP, AND LOAD TIMES
500 kHz, duty
c::--
2 m m
NN
n' .
Clenen
C22
2 ..... UI
..... oIiIoolilo
mr-r::a en en
en--
,..CI==
C
r-
Z
n
o
:s:
:s
CloIiIoolilo
Clr-rcenen
r-
:D
VOLTAGE WAVEFORMS
22
-a .....
UI
_
Z
-I
"T1
~
m
'"'"m
OV
:D
~m
:D
10%f'-l _______
1 . . . - 1 t--tr
i
Cenen
~
-..j I-+-tf
1 1
1 1
I
LOAD
INPUT
i:aWW
::;.
.
_ 10%
~~--------------------------------------------------OV
.
,
~
!il
l3(J)
~
.....
UI
en oliloolilo
~
• m m
.......
I,
I'
190% 90%~t-------------------------------3V
»
-I
oZ
n
CI
=-=
:e
::;
:
n
,..m
r-
.2!:!
.
SN54192, SN54193, SN54LS192, SN54LS193,
SN74192, SN74193, SN74LS192, SN74LS193
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
PARAMETER MEASUREMENT INFORMATION
.---------------°0
..-----------OC
,--------OB
OUTPUTS
,....------OA
,....---CARRY
r----BORROW
.,.
4V
PULSE
GENERATOR
ISee Note AI
VCC
i
r-~>UP
~
i
~>OOWN
~f--?_
Sl
T
BO
;-- A
CO
J--- B
°A
J--J---
C
°B
c-
D
Oc
-<
~ CLR
III
Q)
(J
-S
0D -4
L------I-<:1 LOAD
Q)
o
..J
l-
I-
TEST CIRCUIT
The pulse generators have the following characteristics: PRR ~ 1 MHz, Zout ~ 5011, duty cycle = 50%.
CL includes probe and jig capacitance.
Diodes are 1 N3064 or equivalent.
Cout-up and dount-down pulse shown are forthe '193 and 'LS193 binary counters. Count cycle for '192 and 'LS192 decade
counters is 1 through 10.
E. Waveforms for outputs QA, aS. and QC are omitted to simplify the drawing.
F. tr and tf S 7 ns.
G. Vref is 1.5 V for '192 and '193,1.3 V for 'LS192 and 'LS193.
NOTES: A.
B.
C.
D.
FIGURE 2A - PROPAGATION DELAY TIMES
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-643
SN54192, SN54193, SN54LS192, SN54LS193,
SN74192, SN74193, SN74LS192, SN74LS193
SYNCHRONOUS 4"81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
PARAMETER MEASUREMENT INFORMATION
tf--l
COUNT
UP
INPUT
(See Note D)
f----l !...-tr
~I:
II ~~---3V
-2--1
1
90%
10%
8
--
Vref
I
9
15
Vref
I-- tPLH
---l
I
~
Vref
T----
I
I
I
I
-L
~~
OUTPUT
16
I
1
I
(See Note E) - - - - - - - - - - - - - - - - - '
--+t
______________________________________________________
tpHL
~
l-t
i-1
I
t.;;
~
~O~:~
INPUT
(S.e Note D)
-I
-I
rC
OU~~UT
BO
VOL
II
II
r9ii%~.L2-LH~
8
~ 9 , . ( h\::...J
15 r;;;;:..'
16 v;.;-- 3V
-;~Io~ " \..:Ji Vref \.:..../
vref~~-- OV
""'\
1
\.:..../
I
--l
\
I
!--tPHL
I tPLH.J1
I
I
V ref
I
tpHL...J
I
<
VOL
--11---11-- tr
(5•• Not. E)
CD
VOH
I~tPLH
tpHL VOH
Vref~
tf
OV
i
t-I
i-l
~
i.r,;-:-
71 V ref
r.
VOH
VOL
tpLH
--------------------------------V-re-f~ VOH
C:;"
VOL
CD
VI
VOLTAGE WAVEFORMS
The pulse generators have the following characteristics: PRR ~ 1 MHz, Zout ~ 50 0, duty cycle = 50%.
CL includ~s probe and jig capacitance.
Diodes are 1 N3064 or equivalent.
Cout-up and daunt-down pulse shown are forthe '193 and 'LS193 binary counters. Count cycle for '192 and 'LS192 decade
counters is 1 through 10.
E. Waveforms for outputs QA, 0a, and QC are omitted to simplify the drawing.
F. tr and tf S 7 ns.
G. Vref is 1.5 V for '192 and '193,1.3 V for 'LS192 and 'LSI93.
NOTES: A.
B.
C.
D.
FIGURE 2B - PROPAGATION DELAY TIMES
2-644
TEXAS •
INSTRUMENTS
POST OFFICE BOX 65,5012 • DALLAS, TeXAS 75265
SN54194, SN54LS194A, SN54S194,
SN74194, SN74LS194A, SN74S194
4-BI1 BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
•
Parallel Inputs and Outputs
•
Four Operating Modes:
Synchronous Parallel Load
Right Shift
Left Shift
Do Nothing
SN54194, SN54LSI94A, SN54S194 , , . J OR W PACKAGE
SN74194 ... N PACKAGE
SN74LSI94A. SN74S194 ... 0 OR N PACKAGE
(TOP VIEW)
ClR
SR SER
A
•
Positive Edge-Triggered Clocking
•
Direct Overriding Clear
TYPICAL
TYPE
MAXIMUM
CLOCK
FREQUENCY
Oc
S
C
QO
ClK
0
SlSER
GNO
TYPICAL
51
SO
POWER
DISSIPATION
'194
36 MHz
195mW
'LSI94A
36 MHz
75mW
105 MHz
425mW
'S194
VCC
QA
Qs
SN54LSI94A, SN54S194 ... FK' PACKAGE
ITOP VIEW)
a::w
"'Ia::
a:: U uU «
",uz>c
...I
description
en
These bidirectional shift registers are designed
to incorporate virtually all of the features a
system designer may want in a shift register, The
circuit contains 46 equivalent gates and features
parallel inputs, parallel outputs, right-shift and
left-shift serial inputs, operating-made-control
inputs, and a direct overriding clear line, The
register has four distinct modes of operation,
namely:
(1)
Qs
Qc
'S;
NC
Qo
C
CJ
(1)
ClK
...J
lI-
a::cuo~
wzz"''''
"'(!1
...I
Inhibit clock (do nothing)
Shift right (in the direction QA toward QO)
Shift left (in the direction QO toward QA)
Parallel (broadside) load
'"
NC - No intemai connection
logic symbol t
Synchronous parallel loading is accomplished by
applying the four bits of data and taking both
mode control inputs, SO and S1, high, The data
are loaded into the associated flip-flops and
appear at the outputs after the positive transition
of the clock input, During loading, serial data
flow is inhibited,
Shift right is accomplished synchronously with
the rising edge of the clock pulse when SO is high
and S 1 is low, Serial data for this mode is entered
at the shift-right data input, When SO is low and
S 1 is high, data shifts left synchronously and
new data is entered at the shift-left serial input,
Clocking of the shift register is inhibited when
both mode control inputs are low, The mode
controls of the SN54194/SN74194 should be
changed only while the clock input is high,
PRDDUCTIDI DATA do.umants contain infarmation
.urrant a. of publi.ation data, Products .o.form to
.pacifi.llio•• par th. t8rms of To,," IOslrdmants
=':.:i;af::.':.'li =:~ti:: lIlo:::~:,:,~ .ot
SR SER
(151
A
(14)
B
(131
SL SER
(7)
(12)
QA
aB
aC
QD
2,4D
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and
lEG Publication 617·12.
Pin numbers shown are for D. J, N, and W packages.
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-645
SN54194, SN54LS194A, SN54S194
SN74194, SN74LS194A, SN74S194
4·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
FUNCTION TABLE
INPUTS
CLEAR
~
CLOCK
SERIAL
OUTPUTS
PARALLEL
00
L
L
S1
SO
A
B
C
D
°A
L
X
X
X
X
X
X
X
X
X
L
L
H
X
X
L
X
X
X
X
X
X
QAO
H
H
H
t
X
X
a
b
c
d
a
QBO
b
H
L
H
t
X
H
X
X
X
X
H
QAn QBn QCn
H
L
H
t
X
L
X
X
X
X
L
QAn
H
H
L
t
H
X
X
X
X
X
QBn
QCn QOn
H
H
L
t
L
X
X
X
X
X
QBn
QCn
QDn
H
L
L
X
X
X
X
X
X
X
QAO
QBO
QCO QOO
LEFT RIGHT
°B
Oc
QCO QDO
c
QBn
d
H = high level (steady state)
L "" low level (steady state)
X = irrelevant (any input, including transitions)
t = transition from low to high level
B, b, c, d "" the level of steady-state input at
inputs A, 8, C, or Of respectively.
QAD. QSO. QeQ. 000 = the level of 0A'
OS, 0C. or QD. respectively, before the
indicated steady-state input conditions
QCn
H
were established.
L
QAn. 0Sn. 0Cn. QDn "" the level of QAf
0B, 0C. respectively. before the mostrecent t transition of the clock.
schematics of inputs and outputs
'194
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
-..----VCC
VCC1
3-Req
-I
-I
INPUT
--
r-
OUTPUT
C
CD
<
n'
CD
CLK input: Req
All others: Req
= 4 kn NOM
= 6 kn NOM
(I)
'L8194A
EQUIVALENT OF R, L,
A, B, C, AND D INPUTS
VCC - - - - . - - 15kn NOM
EQUIVALENT OF CLEAR,
CLOCK, SO, AND S1 INPUTS
TYPICAL OF ALL OUTPUTS
- - - - - f " - - VCC
VCC---4~--
17 kn NOM
INPUT --1~H>'---.-
INPUT
--
(10)
Sl
~
;cr;;i
~~
rll
gHH
-z
~~
I rll
0§:
rll
CC
J
)11
Mntl
rL~
m
=i
5!5!
CI
;;
CLOCK "",(1~1:....)- - - - I
CLEAR--<
m
n
-t
....
(1)
lR R
lR R
lR R
Cl
Cl
tf
(13)
(14)
OB
2
:110
rC
2
Cl
Cl
lS
(15)
OA
Ci
Dc
y
PARALLEL OUTPUTS
I--<
<:
m
:a
en
(12)
0"0
:110
en
en 2
r-
=U'I
-~
.,.,-t CD
:a~
Pin numbers shown are for D, J, N, and W packages.
men
~2
en .....
-t~
m-
:a CD
'"m
.j>.
....
en~
TTL Devices
SN54LS194A, SN54S194
SN74LS194A, SN74S194
4·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
logic diagrams (continued)
~~
~ E . . . - - - - - - - - - -.....--------~-8
......
~~
:!!:
g
&
~
::>
a.
~
::>
u
...0
......w
§
c(
a:
-t
-t
::>
(1)
......l1l:w
...
a.
r0
<
c:r
(1)
en
~
~
...
iii'"
0
~
~
II>
.;
~
."'"
.
:=
..
"""c-
oo:
~
0
'0
c:
;;i
(;
-,
c
~
.
i!!
c:
°1c:
"
06>
.!1
c:
0
c:
~
0
.<:
.,
'"
II:
f!
W
..J
.Q
u
u
u
0
..J
MOOE
CONTROL
"E
"c:c:
;;:
INPUTS
2-648
00:
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54194, SN54LS194A, SN54S194,
SN74194, SN74LS194A, SN74S194
4·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
typical clear, load, right-shift, left-shift, inhibit, and clear sequences
CLOCK
MODE
CONTROL
{so --
INPUTS
__ .JI
Sl
:I
I
==0L-+---------!
~'--+--------~_4--------~------~
lS"
CLEAR~:
SERIAL{ R
DATA
INPUTS
L
i ii
r-l~_________~~--------~
:
--i:c--;-:_-:-________-;--+-'
I
,
A--1JHTl~
j
I
PARALLEL
DATA
INPUTS
________-7_~------+_------_+---
i i
B
L
--i,~;-,-~---------;--+-------+--------;---
C
---1.JH[I
:
I -+---------+-~------+--------+---
I
D
°A
I
,: L:,
=:l......f--L..J-I
, "
L------!-_4------...J..:I - - - - - - . . ; L
=:1, 1 t-"-LI!
n i
:
,
I
0B
OUTPUTS
Dc : : '
I
I
II)
Q)
.~
>
Q)
o
..J
lI-
I
I
i---SHIFT RIGHT----i
!---SHIFT LEFT
CLEAR LOAD
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
.1.
INHIBIT---.j
CLEAR
2·649
•
SN54194, SN741.94
4·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
absolute maximum ratings over operating .free·air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage . . . . . . . .
Operating free-air temperature range: SN54194
SN74194
Storage temperature range
7V
5.5V
-55°C to 125°C
O°C to 70°C
_65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54194
Supply voltage, Vee
High~level
SN74194
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
Low-level output current, IOL
16
25
0
Clock frequency. f clock
Width of clock or clear pulse, tw
Mode control
I Serial and parallel data
I Clear inactive-state
Setup time, tsu
Hold time at any input, th
V
-SOO
-SOO
output current, IOH
UNIT
I'A
16 rnA
25 MHz
0
ns
20
20
30
30
ns
20
20
ns
25
25
ns
0
-55
0
ns
125
70 "e
0
-I Operating free-air temperature, T A
-I
r- electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
C
PARAMETER
CD
<
c:r
CD
en
VIH
High-level input voltage
VIL
VIK
Low-level input voltage
SN54194
TEST CONDITIONSt
MIN
TYP*
SN74194
MAX
MIN
2
Input clamp voltage
VOH High-level output voltage
VOL Low-level output voltage
Vee = MIN,
11= -12 rnA
Vee = MIN,
VIH-2V,
VIL = O.S V,
10H= -SOOI'A
Vee- MIN,
VIH-2V,
IIH
High-level input current
10L = 16mA
Vee= MAX, VI = 5.5V
Vee= MAX, VI = 2.4V
IlL
Low-level input current
Vee = MAX, VI-O.4V
lOS
Short-circuit output current§
lee
Supply current
Vee- MAX
Vee = MAX, See Note 2
Input current at maximum input voltage
2
2.4
O.S
-1.5
3.4
0.2
2.4
0.4
3.4
0.2
-57
39
-18
V
1
40
rnA
p.A
-1.6
rnA
-57
rnA
63
rnA
39
63
V
0.4
40
-1.6
V
V
1
-20
UNIT
V
O.S
-1.5
VIL = 0.8 V,
II
TYP* MAX
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
typical values are at Vee = 5 V, T A = 25 0 c.
§Not more than one output should be shorted at a time.
NOTE 2: With all outputs open, inputs A through D grounded, and 4.5 V applied to SO, Sl, clear, and the serial inputs, ICC is tested with a
momentary GND, then 4.5 V applied to clock.
:t All
switching characteristics, Vee" 5 V, TA = 25°e
TEST CONDITIONS
PARAMETER
2-650
f max
Maximum clock frequency
tpHL
Propagation delay time, high-to-Iow·level output from clear
tpLH
Propagation delay time, low-to-high-Ievel output from clock
tpHL
Propagation delay time, high·to·low-Ievel output from clock
eL
~
15 pF,
RL
~
400
n,
See Figure 1
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 65501'2 • DALLAS, TEXAS 75265
MIN
TYP
25
36
MAX
UNIT
MHz
19
30
ns
14
22
ns
17
26
ns
SN54LS194A. SN74LS194A
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1 )
Input voltage . . . . . . .
Operating free·air temperature range: SN54LS194A
SN74LS194A
Storage temperature range
7V
7V
-55°e to 125°e
o°c to 700 e
-65°C to 1500 e
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS194A
Supply voltage, Vee
MIN
NOM
4.5
5
SN74LS194A
MAX
MIN
NOM
5.5
4.75
5
-400
High-level output current, IOH
Low-level output current, IOL
MAX
5.25
V
-400
B
"A
rnA
25
MHz
4
0
Clock frequency, fclock
Width of clock or clear pulse, tw
I Mode control
I Serial and parallel data
Setu p time, tsu
I Clear inactive-state
25
0
20
20
ns
30
30
ns
20
20
ns
25
25
ns
0
Hold time at any input, th
Operating free-air temperature, T A
UNIT
125
en
ns
0
-55
Ell
70
0
CI)
°e
.2
>
CI)
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input clamp voltage
SN74LS194A
SN54LSl94A
TEST CONDITIONSt
MIN
TYP*
MAX
MIN
2
VOH High-level output voltage
II
Vee = MIN,
VIH=2V,
2.5
VIL = VIL max, 10H = -400 "A
Vee - MIN,
VOL Low-level output voltage
Input current at
O.B
V
-1.5
V
2.7
IIOL ~ BrnA
3.5
V
0.25
0.4
0.35
0.5
V
Vee = MAX,
VI = 7 V
0.1
0.1
rnA
IIH
High-level input current
Vee - MAX,
VI - 2.7 V
20
20
IlL
Low-level input current
Vee
= MAX,
VI - 0.4 V
-0.4
-0.4
"A
rnA
lOS
Short-circuit output current ~
Vee- MAX
-100
rnA
lee
Supply current
Vee- MAX,
23
rnA
II
maximum input voltage
-20
-100
15
See Note 2
-20
15
23
...J
lI-
V
1.5
0.4
C
UNIT
0.7
3.5
0.25 .
VIH-2V, IIOL =4mA
VIL = VIL max
MAX
2
lBmA
Vee = MIN,
TYP*
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
~:AII typical values are at Vee = 5 V, T A = 25"C
*Not more than one output should be shorted at a time, and duration of the short·circuit should not exceed one second.
NOTE 2: With all outputs open, inputs A through 0 grounded, and 4.5 V applied to SO, 51, clear, and the serial inputs, ICC is tested with a
momentary GND, then 4.5 V, applied to clock.
switching characteristics.
Vee
=
5
V.
TA - 25 De
TEST CONDITIONS
PARAMETER
f max
Maximum clock frequency
tpHL
Propagation delay time, high-to-Iow-Ievel output from clear
tpLH
Propagation delay time, low-to-high level output from clock
tpHL
Propagation delay time, high-to-Iow level output from clock
= 15 pF,
RL = 2 kll,
CL
See Figure 1
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
TYP
25
36
MAX
UNIT
MHz
19
30
ns
14
22
ns
17
26
ns
2-651
SN54S194, SN74S194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Operating free·air temperature range: SN54S194
SN74S194
Storage temperature range
7V
5.5V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54S194
Supply Voltage, V CC
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-1
mA
-1
Low-level output current, IOL
20
Clock frequency, fclock
0
Width of clock pulse, twlclock}
Width of clear pulse, twlclearl
I Mode control
I Serial and parallel data
I Clear inactive-state
Setup time, tsu
C
CD
Hold time at any input, th
Operating free-air temperature, T A
PARAMETER
C')
CD
70
0
20
mA
70
MHz
7
7
ns
12
ns
11
12
11
5
5
ns
9
9
ns
3
3
-55
125
ns
0
70
ns
·C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
~.
III
UNIT
NOM
High-level output clirrent, IOH
-I
-I
r-
SN74S194
MIN
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
TEST CONDITIONst
SN54S194
MIN
TYP*
SN74S194
MAX
MIN
TYP* MAX
2
2
V
0.8
VOH High-level output voltage
VOL Low-level output voltage
VCC= MIN,
II =-18mA
VCC= MIN,
VIH=2V,
VIL =0.8V,
10H= -1 mA
VCC= MIN,
VIH=2V,
VIL = a.8V,
10L = 20 mA
-1.2
2.5
,
2.7
3.4
UNIT
0.8
V
-1.2
V
3.4
V
0.5
0.5
V
II
Input current at maximum input voltage
VCC= MAX, VI = 5.5V
1
1
mA
IIH
High-level input current
VCC= MAX,
VI = 2.7V
50
50
IlL
Low-level input current
VCC= MAX,
VI=0.5V
-2
-2
"A
mA
lOS
Short·circuit output current §
VCC= MAX
-100
mA
-40
VCC= MAX, See Note 2
ICC
-100
85
VCC- MAX'I
T A = 12s"C, W package
Supply current
-40
135
135
85
mA
110
See Note 2
tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V. T A"" 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: With all outputs open, inputs A through 0 grounded, and 4.5 V applies to SO, 51, clear, and the serial inputs, ICC is tested with a
momemtary GND, then 4.5 V, applied to clock.
switching characteristics, Vee - 5 V, TA .. 25°e
TEST CONDITIONS
PARAMETER
f ma•
Maximum clock frequency
tpHL
Propagation delay time, high-to-Iow-Ievel output from clear
tpLH
Propagation delay time, low·to-high·level output from clock
tpHL
Propagation delay time, high-to-Iow-Ievel output from clock
2-652
CL=15pF,
RL = 280O,
See Figure 1
TEXAS'"
INSTRUMENTS
POST OFFice BOX 656012 • DALLAS. TeXAS 75265
MIN
TYP
70
106
MAX
UNIT
MHz
12.5
18.5
4
8
12
ns
4
11
16.5
ns
ns
SN54194. SN54LS194A. SN54S194.
SN74194. SN74LS194A. SN74S194
4·BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION
TEST TABLE FOR SYNCHRONOUS INPUTS
OUTPUT
DATA INPUT
VCC
SO
A
4.5 V
4.5V
QAat tn+1
B
4.5V
4.5V
QB at tn+1
C
4.5V
4.5V
QC at tn+1
D
4.5V
4.5V
QD at tn+1
L Serial Input
4.5V
OV
QA at tn+4
R Serial Input
OV
4.5V
QD attn+4
FROM
OUTPUT
UNDER
TEST
LOAD FOR OUTPUT UNDER TEST
,"
CLEAR
"I
OUTPUT TESTED
S1
FOR TEST
(SEE NOTE E)
tvv(clear)
''"'w~:'.------------------I
tsu
1,
r-
Itn+1
t
-,
CLOCK
n
t--~
!-I-
(See Note FI
,
tPHL
t
OUTPUTQ
Vret
...I
3V
II-
,
,
-~~---
OV
3V
OV
,
I---t--tPHL
I
~tPLHr.2
I
II)
0
n
~
,
I
,
-I--t
'>
OV
Vref
,,
,
1
II)
(,,)
tn+1
th
DATA
INPUT
(SEE TEST
TABLE)
II)
3V
Vref
\Vret
\~:---
VOH
VOL
VOLTAGE WAVEFORMS
NOTES:
A. The clock pulse generator has the following characteristics: Zout ~ 50 nand PRR, 1 MHz, For '194, tr.so;. 7 ns and tf
For 'LS194A, tr '" 15 ns and tf " 6 ns. For '5194. tr "2.5
and tf EO;; 2.5 os. When testing f max • vary PRR.
"5
~
7 ns.
B. CL includes probe and jig capacitance.
C. All diodes are lN3064 or lN916.
D. A clear pulse is applied prior to each test.
E. For '194 and 'S194, Vref = 1.5 V; for 'LS194A, Vref
= 1.3 V.
F. Propagation delay times (tPLH and tpHL) arB measured at t n +1' Proper shifting of data is verified at tn+4 with a functional test.
G. tn = bit time before clocking transition.
tn+1 "" bit time after one clocking transition.
to+4 = bit time after four clocking transitions.
FIGURE 1-SWITCHING TIMES
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 6550t 2 • DALLAS, TEXAS 75265
2-653
2-654
SN54195, SN54LS195A, SN54S195,
SN74195, SN74LS195A, SN74S195
4-81T PARALLEL-ACCESS SHIFT REGISTERS
MARCH 1974-REVISED MARCH 1988
• Synchronous Parallel Load
SN54195, SN54LS195A, SN54S195 ..• J OR W PACKAGE
SN74196 .•. N PACKAGE
SN74LS196A, SN74S195 •.• 0 OR N PACKAGE
(TOP VIEW)
• Positive-Edge-Triggered Clocking
• Parallel Inputs and Outputs from
Each Flip-Flop
ClR
VCC
• Direct Overriding Clear
J
• J and K Inputs to First Stage
A
B
OA
OB
Oc
00
K
• Complementary Outputs from Last Stage
C
• For Use in High Performance:
Accumulators/Processors
Serial-to-Parallel, Parallel-to-Serial
Converters
aD
ClK
SH/lO
0
GNO
SN54LS195, SN54S195 ••• FK PACKAGE
(TOP VIEW)
description
These 4-bit registers feature parallel inputs, parallel
outputs, J-K serial inputs, shiftlload (SH/LO) control
input, and a direct overriding clear. All inputs are
buffered to lower the input drive requirements. The
register has two modes of operation:
5
u
tl «
1
.,uz>o
K
Parallel (broadside) load
Shift (in the direction OA toward 00)
OB
Oc
U)
A
NC
NC
B
00
'S:
C
aD
Parallel loading is accomplished by applying the four
bits of data and taking SH/LO low. The data is loaded
into the associated flip-flop and appears at the outputs
after the positive transition of the clock input. During
loading, serial data flow is inhibited.
Q)
U
Q)
C
....I
~
~
NC • No internal connection
Shifting is accomplished synchronously when SH/LO
is high. Serial data for this mode is entered at the J-K
inputs. These inputs permit the first stage to perform
as a J-K, D-, or T-type flip-flop as shown in the
function table.
TYPE
'195
'LS195A
'S195
The high-performance 'S195, with a 105-megahertz
typical maximum shift-frequency, is particularly attractive for very-high-speed data processing systems. In
most cases existing systems can be upgraded merely
by using this Schottky-clamped shift register.
TYPICAL
MAXIMUM CLOCK
FREQUENCY
39 MHz
39 MHz
105 MHz
TYPICAL
POWER
DISSIPATION
195mW
70mW
350mW
FUNCTION TABLE
OUTPUTS
INPUTS
CLEAR
SHIFTI
LoAD
CLOCK
SERIAL
J
K
PARALLEL
A
B
C
0
QA
QB
Qc
QD
L
L
L
H
b
c
d
if
00
L
X
X
X
X
X
X
X
X
L
H
H
L
H
t
X
X
a
b
c
d
a
L
X
X
X
X
X
H
H
H
t
t
t
t
L
H
X
X
X
L
L
X
X
X
X aAO aSO aCO aDO 000
X aAO aAO asn aCn aCn
L aAn aSn Cen acn
X
H
H
H
H
H
H
H
X
X
X
X
H
L
X
X
X
X GAn aAn aBn Cen ficn
PRODUCTION DATA doc.ments contain information
current as of publication date. Products conform to
specifications par the terms of Texas Instruments
~::==i~.i:I~7i ~=::i:; 1I~a::;:::t!s~ nat
H
aAn aBn aCn aCn
H "" high level (steady state)
L :0 low level (steady state)
X = irrelevant (any input, including transitions)
t ;: transition from low to high level
a. b, c, d "" the level of steady-state input at A, B.
C, or D. respectively
QAO. Qeo. QeD. Qoo the level of QA. aB. QC.
=
or
aD. respectively. ba-
fore the indicated steady·
state
QAn. 0Sn. 0Cn
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
input
conditions
were established
level of CA. 0a. or QC.
respectively. before the most-
= the
recent transition of the clock
2-655
SN54195. SN54LS195A •. SN54S195,
SN74195, SN74LS195A, SN74S195
4·81T PARALLEL·ACCESS SHIFT REGISTERS
logic diagram (positive logic)
;:;
18
c
0
IX:
~
c
c:;
E
M
(5
...
In
::J
...
Q.
IX:
~
-I
-I
r-
0
(1)
~.
(')
(1)
...en
u
::J
c:;
0
-'
w
-'
-'
«
IX:
«
§
Q.
::J
Q.
~
;
-'
w
-'
-'
«
cr
«
co
0
II:
~
Q.
c:;
(fI
co
§
IX:
«
i{:
~
§
• "C
-"'c:
oc: '"•
~
"'z•
OJ
-'
I+-
L_
0
!:::
"
-'
u
2-656
TEXAS
I~
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54195. SN54LS195A. SN54S195.
SN74195. SN74LS195A. SN74S195
4·81T PARALLEL·ACCESS SHIFT REGISTERS
typical clear, shift, and load sequences
CLK
CLR
J ___
SERIAL {
INPUTS
~
I
I
-+____+-__________________
....____________________
~~
I
K
....- ______________________
~
I
~I
____
~
_____________________
I
I
----~------~I-------------------------,LL_J~~~--------------------
SH/LO
I
--:....--_I~ _
A
PARALLEL{
DATA
8
INPUTS
C ____
I
_~f"H"T"lI....-:._
~------~----------------------~~
....~~-------------------.
I
L I
I
I
I
I
....----.
8 --- ; :
Oc
I
:
:
OA
o
__
L :
I
o
OUTPUTS {
____
:::+-'_~r----1,---_ _ _~r----1,------_ __
I
---,
:::1
I
I
0 0 ::::'
I
I
CLEAR
....
' --------
~_ _ _ _ __
I
I
I
I
I
It------SERIALSHIFT----e-tl
LOAD
I
t/)
I
I---SERIALSHIFT-
Q)
CJ
'S;
Q)
C
-'
logic symbols t
'195
'L5195, '5195
SRG4
SRG4
lI-
J
K
A
OA
8
08
Dc
00
aD
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and lEe Publication 617-12.
Pin numbers are for 0, J, N, and W packages.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS; TeXAS 75265
2-657
SN5419~ SN54LS195A. SN54S19~ SN74195. SN74LS195A. SN74S195
4·811 PARALLEL·ACCESS SHIFT REGISTERS
schematics of inputs and outputs
'195
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
-_..----vcc
vcc------~-----
INPUT
OUTPUT
Clock input: Req"" 4
kn
NOM
All other inputs: Req = 6 kfl NOM
'LS195A
-I
-f
r-
C
CD
!S.
C')
EQUIVALENT OF J, K,
A, B, C, AND D INPUTS
EQUIVALENT OF ClR, ClK, AND
SH/lD INPUTS
TYPICAL OF ALL OUTPUTS
--------.----vcc
120nNOM
vcc-----~----
vcc------~---17 kn
15 kn NOM
CD
!II
1-._~_ _
I NPUT-oH.......- _ -
'S195
EQUIVALENT OF EACH INPUT
TYPICAL OF All OUTPUTS
----------~----vcc
vcc-----~-----
INPUT
50 n NOM
"L.._+___
CLR, SH/LD: Req::: 4 kf2 NOM
All other inputs: Req == 2.8 k,Q NOM
2-658
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
OUTPUT
OUTPUT
SN54195, SN74195
4-BIT PARALLEL-ACCESS SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise notll,d)
7V
Supply voltage, VCC (see Note 1)
Input voltage . . . . . . .
Operating free·air temperature range: SN54195
SN74195
Storage temperature range
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54195
MIN
Supply voltage, Vee
NOM
4.5
SN74195
MAX
MIN
NOM
5.5
4.75
5
5
-800
High-level output current, IOH
Low-level output current, tOl
MAX
V
-800
IJA
16
Clock frequency, f c lock
0
30
UNIT
5.25
0
16
mA
30
MHz
Width of clock input pulse, tw(clock)
16
16
ns
Width of clear input pulse, tw(clead
12
12
ns
25
25
I Shift/load
I Serial and parallel data
I Clear inactive-state
Setup time, tsu (see Figure 1)
20
20
25
25
10
Shift/load release time, trelease (see Figure 1)
Serial and parallel data hold time, th (see Figure 1)
0
125
0
Q)
(,)
10
ns
'S
70
ns
"e
C
0
-55
Operating free-air temperature. T A
I/)
ns
Q)
..J
lI-
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
VIK
Low-level input voltage
TEST eONOITIONst
MIN
Input clamp voltage
Vee - MIN,
VOH High-level output voltage
Vee - MIN,
VIH-2V,
VIL = 0.8 V.
10H = -800
~A
Vee - MIN,
VIH - 2 V,
10L = 16 mA
I nput current at maximum input voltage
Vee - MAX,
VI - 5.5 V
Low-level output voltage
II
IIH
High-level input current
Vee
IlL
Low-level input current
Vee - MAX,
lOS
Short-circuit output cUHent~
Vee = MAX
lee
Supply current
V
11- -12mA
VIL = 0.8 V,
VOL
TVP+ MAX UNIT
2
MAX,
2.4
V
-1.5
V
3.4
V
0.2
0.4
1
V
mA
2.4 V
40
IJA
VI- 0.4 V
-1.6
mA
VI
I
SN54195
-20
I SN74195
-18
See Note 2
Vee = MAX,
0.8
-57
-57
39
63
mA
mA
tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
tAli
typical values are at
Vee
=
5 V, T A = 2SoC_
§ Not more than one output should be shorted at a time,
NOTE 2:
With all outputs open, shift/load grounded, and 4.5 V applied to the J,
K.
and data inputs, ICC is measured by applying a
momentary ground, followed by 4.5 V, to clear and then applying a momentary ground, followed by 4.5 V, to clock.
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER
TEST CONOITIONS
f max Maximum clock frequency
tpHL Propagation delay time, high-to-Iow-Ievel output from clear
tpLH Propagation delay time, low-to-high-Ievel output from clock
tpHL Propagation delay time, high-to-Iow-Ievel output from clock
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
eL=15pF,
RL=400n,
See Figure 1
MIN
TVP
30
39
MAX UNIT
MHz
ns
19
30
14
22
ns
17
26
ns
2-659
SN54LS195A, SN74LS195A
4·81T PARALLEL·ACCESS SHIFT REGISTERS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
Operating free-air temperature range: SN54LS195A
SN74LS195A
Storage temperature range
7V
7V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN74LS195A
SN54LS195A
MIN
Supply voltage, Vee
High~level
4.5
NOM
5
output current, IOH
MAX
MIN
5.5
4.75
low-level output current, IOl
16
16
12
12
25
25
Setup time, tsu (see Figure 1)
Shift/load
L Serial and parallel data
15
15
Clear inactive-state
25
25
I
C
Serial and parallel data hold time, th (see Figure 1)
V
-400
l'A
Operating free-air temperature, T A
S
mA
30
MHz
ns
ns
ns
10
0
20
ns
70
·e
ns
0
-55
125
UNIT
5.25
0
Width of clear input pulse, twlclear)
Shift/load release time, trelease (see Figure 1)
<
30
Width of clock or clear pulse, tw(clock)
r-
C)'
MAX
4
0
I
(1)
5
400
Clock frequency. fclock
-I
-I
NOM
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
(1)
(I)
PARAMETER
VIH
High-level input voltage
Vil
Low-level input voltage
VIK
Input clamp voltage
TEST eONDITIONSt
TVP+
SN74lS195A
MAX
2
VOH High-level output voltage
Vee - MIN,
11--18mA
Vee-MIN,
VIH-2V,
Vil
~
VIL max, IOH
Vee - MIN,
VOL Low-level output voltage
VIL
Input current at
II
SN54lS195A
MIN
maximum input voltage
~
~
-400 "A
2.5
MAX,
VI
~7
~
MAX
UNIT
V
2
O.S
V
-1.5
-1.5
V
2.7
3.4
0.4
tlOl -SmA
Vee~
TVP+
0.7
0.25
VIH-2V, IIOL -4mA
VIL max
MIN
0.25
0.4
0.35
0.5
0.1
V
V
3.4
V
0.1
mA
IIH
High-level input current
Vee~
MAX,
VI
2.7 V
20
20
III
Low-level input current
Vec~
MAX,
VI-0.4 V
-0.4
-0.4
"A
mA
lOS
Short-circuit output current§
Vee~
MAX
-100
mA
ICC
Supply current
Vee~
MAX,
21
mA
-20
-100
14
See Note 2
-20
21
14
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
TAli typical values are at Vee "- 5 V, T A '" 25 C.
~ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second,
NOTE 2: With all outputs open, shift/load grounded. and 4.5 V applied to the J. K. and data inputs, ICC is measured by applYing a momentary
ground. followed by 4.5 V. to clear and then applying a momentary ground. followed by 4.5 V. to clock
switching characteristics, Vee
= 5 V, TA = 25·e
TEST CONDITIONS
PARAMETER
~a-ximum
clock frequency
tPHL Propagation delay time, high-to-Iow-Ievel output from clear
tPLH Propagation delay time, low-to-high-Ievel output from clock
tpHL Propagation delay time, high-to-Iow-Ievel output from clock
2-660
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
CL"15pF.
RL"2kll.
See Figure 1
MIN
30
TVP
MAX UNIT
MHz
39
19
30
ns
14
22
ns
17
26
ns
SN54S195, SN74S195
4-81T PARALLEL-ACCESS SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
I nput voltage
... . . . .
Operating free·air temperature range:
7V
5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C
SN54S195
SN74S195
Storage temperature range
NOTE 1:
Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54S195
MIN
Supply voltage. Vee
4.5
NOM
SN74S195
MAX
MIN
5.5
4.75
5
NOM
5
-I
High·level output current, IOH
Low-level output current, tOl
20
0
Clock frequency, fclock
Setup time, tsu (see Figure 1)
I
Shift/load
I
Serial and parallel data
0
V
-1
rnA
20
rnA
70
MHz
7
7
ns
12
ns
11
11
I Clear inactive-state
Shift/load release time, trelease (see Figure 1)
Serial and parallel data hold time, th (see Figure 1)
5
5
9
9
ns
-55
125
CJ
ns
6
3
3
(I)
Q)
2
Operating free--air temperature. T A '
5.25
12
Width of clock input pulse, tw(clockl
Width of clear input pulse, tw(clearl
70
UNIT
MAX
'S
ns
Q)
°e
70
0
C
...J
l-
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
TEST eONDITIONSt
MIN
High-level input voltage
TVP+
MAX
Low-level output voltage
Vee - MIN,
11- -18mA
Vce- MIN.
VIH= 2V.
VIL = 0.8 V.
10H = -1 mA
Vce - MIN,
VIH - 2 V.
VIL = 0.8 V,
10L = 20mA
I SN54S195
I SN74S195
UNIT
2.5
3.4
2.7
3.4
0.8
V
-1.2
V
V
0.5
V
II
Input current at maximum input voltage
Vee= MAX.
VI = 5.5 V
1
IIH
High-level input current
Vec- MAX.
VI - 2.7 V
50
~A
IlL
Low-level input current
Vee - MAX.
VI = 0.5V
-2
mA
lOS
Short-circuit output current§
Vee = MAX
-100
mA
ICC
Supply current
Vee= MAX.
-40
See Note 2
I-
V
2
I SN54S195
70
99
I SN74S195
70
109
mA
rnA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
fAil typical values are at
Vee
=
5 V, T A
=
2SoC.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second,
NOTE 2: With all outputs open, shift/load grounded, and 4.5 V applied to the J, K, and data Inputs, ICC is measured by applying a momentary
ground, followed by 4.5 V. to clear, and then applying a momentary ground, followed by 4.5 V, to clock.
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER
TEST CONDITIONS
f max Maximum clock frequency
tpHL Propagation delay time, high·to·low·level output from clear
tPLH Propagation delay time, low-to·high·level output from clock
tpHL Propagation delay time, high-to-Iow-Ievel output from clock
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
CL = 15 pF.
RL=280n.
See Figure 1
MIN
TVP
70
105
MAX
UNIT
MHz
12.5
18.5
ns
8
12
ns
11
16.5
ns
2-661
SN54195, SN54LS195A, SN54S195,
SN74195, SN74LS195A, SN74S195
4·81T PARALLEL·ACCESS SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION
OUTPUT
VCC
FROM OUTPUT
UNDERTES~T~'--MI-~--~~~It.,
Cl"15pF
ISee Note B)
lOAD FOR OUTPUT UNDER TEST
I.
a::R
------~:
'I
twlcleari
I
\:::,.(_~: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ OV
3V
,
~
~
-...r
tou
ClK
tn...,r+ 'n+l
..-J"- 'n+l
V re!
I
I--l-""':'=;==--
r-
C
CD
(;'
r--
CD
tsu
I
(I)
I
---I
,-
"I
"\ -----t
v
11::.~---- ov
r
r--
I
trelease
I"I--tpHl - -
!--'PlH-I
,
1~2
' \ v re!
}
v re!
0V
i
I '''----
~
tsu
SHiro ---------;,----""8,.v-r-e!-+I---------l2,\ v re!
ASSOCIATED
OUTPUTQ
V re!
~'h
'"'" 'su.,.j
,
DATA
(See Note G)
<
____
~'n----, 3V
3V
"!
,.
II
trelease
l~~l----
___ ::
!--tPHl ......1
~
VOH
VOL
VOLTAGE WAVEFORMS
NOTES:
A. The clock pulse generator has the following characteristics: Zout l'iioi 60 nand PRR <; 1 MHz. For '195, tr.eo;. 7 ns and 1f
For 'LS195A, tr '" 15 ns and tf" 6 os. For 'S195. tr c; 2.5 ns and 'tf = 2.5 ns. When testing f max • vary the clock PAR.
u
These high-speed monolithic counters consist of four
doc coupled, master-slave flip-flops, which are internally
interconnected to provide either a divide-by-two and a
divide-by-five counter ('196, 'LS196, 'S1961 or a divideby-two and a divide-by-eight counter ('197, 'LS197,
'S197). These four counters are fully programmable;
that is, the outputs may be preset to any state by placing
a Iowan the count/load input and entering the desired
data at the data inputs. The outputs will change to agree
with the data inputs independent of the state of the
clocks,
During the count operation, transfer of information to
the outputs occurs on the negative-going edge of the
clock pulse, These counters feature a direct clear which
when taken low sets all outputs low regardless of the
states of the clocks.
QD
D
S
3 2
:'~~~:~~~I[::I~li ~::i~:i:; :'~D::~::~:~~' not
'S:Q)
2019
C
...J
....
....
QA
9
III
NCU
><:zz ><:0
..J
...Jl!)
U
U
NC - No internal connection
logic symbols t
'197, 'L5197, '5197
'196, 'LS196, 'S196
(5)
Os
PRODUCTION DATA d........1s •••lIIi. i.f.rmlti ••
current I ••f publication dlta. Products conform tD
'pacificltiDns Plr the terms of TaxI. Instruments
Q)
(,)
C
NC
A
NC
These counters may also be used as 4-bit latches by using the count/load input as the strobe and entering data
at the data inputs. The outputs will directly follow the
data inputs when the count/load is low, but will remain
unchanged when the count/load is high and the clock
inputs are inactive.
All inputs are diode-clamped to minimize transmissionline effects and simplify system design. These circuits
are compatible with most TTL logic families, Series 54,
54LS, and 54S circuits are characterized for operation
over the full military temperature range of - 55°C to
125°C; Series 74, 74LS, and 74S circuits are
characterized for operation from O°C to 70°C.
I/)
ac
QD
CLK2 (6)
B (10)
c (3)
0 (11)
as
ac
DO
t These symbols are in accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-663
SN54196, SN54197, SN54lS196,SN54LS197, SN54S196, S154S197,
SN74196, SN74197, SN74LS196, SN74LS197, SN74S196,SN74S197
50/30/100·MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES
typical count configurations
'196, 'LS196, and 'S196 typical count configurations and function tables are the same as those for '176.
'197, 'LS197, and 'S197·typical count configurations and function tables are the same as those for '177.
logic diagrams
'196, 'LS196, and 'S196 logic diagrams are the same as those for '176.
'197, 'LS197, and 'S197 logic diagrams are the same as those for '177.
schematics of inputs and outputs
EQUIVALENT OF LOAD, CLEAR,
AND DATA INPUTS.
EQUIVALENT OF CLOCK INPUTS
VCC__4_--4_........_
V C C - -.....- -
R1
R2
R3
TYPICAL OF ALL OUTPUTS
---
Q)
o
...J
lI-
NOTE 1: Voltage values aro with respect to network ground terminal.
recommended operating conditions
SN54S196, SN54S197
Supply voltage, VCC
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-1
mA
20
mA
-1
output current, IOl
Clock frequency
Pulse width, tw
Input hold time, th Isee Note 3)
Input setup time, tsu (see Note 3)
Count enable time. ten Isee Note 4)
Operating free-.air temperature, T A
UNIT
NOM
High·level output current, IOH
Low~level
SN74S196, SN74S197
MIN
20
Clock·1 input
0
100
0
100
Clock-2 input
0
50
0
50
Clock-1 input
5
Clock-2 input
10
10
Clear
30
30
Load
5
5
High--level data
31
31
Low..jevel data
31
31
High-level data
61
61
Low-level data
61
61
12
-55
MHz
5
ns
ns
ns
12
125
0
ns
70
°c
NOTES: 3. Setup and hold times are with respect to the falling edge of the load input.
4. Minimum count enable time is the interval immediately preceding the negative-going edge of the clock pulse during which
interval the count/load and clear inputs must both be high to ensure counting.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-669
SN54S196,SN54S197, SN74S196, SN74S197
1~O-MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES
.electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
t
TEST CONDITIONS
SN54S196,
SN54S197,
SN74S196
SN74S197
MIN
TYP;
MAX
2
VIH
VIK
VCC - MIN,
11=-18rnA
VOH
VCC MIN,
VIL =0.8V,
VIH
VCC- MIN,
VIH - 2 V,
VOL
Clock 1, clock 2
IIH
All other inputs
Data, Load
Clear
IlL
2.5
3.4
2.S
3.4
74S
VIL -0.8V,
2.7
3.4
2.7
3.4
I
IOH=-l rnA
Clock 1
VCC= MAX,
VI-S.SV
VCC= MAX,
VI = 2.7 V
VCC= MAX,
VI = O.SV
C
<
C:;'
-1.2
54S
VCC- MAX
ICC
VCC = MAX,
-30
I
See Note 5
..
t For conditions shown as MIN or MAX, use the appropriate value
i All typical values are at Vee 5 V, T A = 25°C.
V
V
V
0.5
1
1
150
lS0
so
50
Jl.A
-0.75
-0.75
mA
-8
-8
-6
mA
-110
mA
-10
IOS§
V
O.S
Clock 2
CD
V
0.8
-1.2
I
2 V,
UNIT
MAX
2
IOL = 20 rnA1
II
r-
TYP;
0.8
VIL
-I
-I
MIN
-110
-30
S45
75
110
75
110
I 74S
75
120
75
120
rnA
mA
mA
specified under recommended operating conditions.
0:
~QA
outputs are tested at IOL = 20 mA plus the limit value of I, L for the clock-2 input. This permits driving the clock-2 input while fanning
out to 10 Series 54S/74S loads.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 5: ICC is measured with all input grounded and all outputs open.
CD
(II
switching characteristics, Vee = 5
PARAMETER #
f max
tpLH
(FROM
TO
(INPUT)
(OUTPUT)
Clock 1
QA
Clock 1
QA
tpHL
tpLH
Clock 2
tpHL
tPLH
Clock 2
tpHL
tpLH
tpHL
tPLH
SN54S196,
QC
QD
A,B,C,D
QA,QB,QC,QD
Load
Any
Clear
Any
RL = 280
n,
MIN
TYP
100
140
CL = lSpF
See Note 7
tpHL
tpHL
#f max ;;;;;
tpLH '"
tpHL ::
NOTE 7:
2-670
SN54S197
SN74S196
TEST CONDITIONS
QB
Clock 2
tpHL
tpLH
V, TA = 25° e
SN74S197
MAX
MIN
TYP
100
140
5
10
5
TEXAS~
INSTRUMENTS
MHz
10
6
10
6
10
5
10
5
10
8
12
8
12
12
18
12
18
16
24
15
22
5
10
18
27
8
12
22
33
12
7
12
7
12
18
12
18
10
18
10
18
12
18
12
18
26
37
26
37
maximum count frequency.
propagation delay time, low·to·high·level output.
propagation delay time, high-to-Iow-Ievel output.
Load circuit, input conditions, and voltage waveforms are the same as those shown in Section 1
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
MAX
ns
ns
ns
ns
ns
ns
ns
SN54198, SN54199 SN74198, SN74199
8·BIT SHIFT REGISTERS
DECEMBER 1972-REVISED MARCH 1988
description
SN54198 ... J OR W PACKAGE
SN74198 .•. N PACKAGE
These 8-bit shift registers are compatible with most
other TTL and MSI logic families. All inputs are
buffered to lower the drive requirements to one
normalized Series 54/74 load, and input clamping
diodes minimize switching transients to simplify
system design. Maximum input clock frequency is
typically 35 megahertz and power dissipation is
typically 360 mW.
ITOPVIEW)
SO
SR SER
A
OA
B
OB
C
Oc
D
OD
ClK
GND
Series 54 devices are characterized for operation over
the full military temperature range of -55°C to
125°C; Series 74 devices are characterized for
operation from O°C to 70°C.
SN54198 and SN74198
VCC
Sl
Sl SER
H
OH
G
OG
F
OF
E
OE
ClR
These bidirectional registers are designed to incorporate virtually all of the features a system designer may
want in a shift register. These circuits contain 87
equivalent gates and feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating·mode·
control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:
til
(1)
U
">
Inhibit Clock (Do nothing)
Shift Right (In the direction QA toward QH)
Shift Left (In the direction QH toward QA)
Parallel (Broadside) Load
(1)
C
...I
Synchronous parallel loading is accomplished by applying the eight bits of data and taking both mode control inputs,
SO and Sl, high. The data is loaded into the associated flip·flop and appears at the outputs after the positive transition
of the clock input. During loading, serial data flow is inhibited.
lI-
Shift right is accomplished synchronously with the rising edge of the clock pulse when SO is high and Sl is low. Serial
data for this mode is entered at the shift-right data input. When SO is low and Sl is high, data shifts left synchronously
and new data is entered at the shift·left serial input.
Clocking of the flip·flop is inhibited when both mode control inputs are low. The mode controls should be changed
only while the clock input is high.
'198
FUNCTION TABLE
INPUTS
CLEAR
H
X
::=
::=
I
MOOE
S,
CLOCK
So
L
X
X
X
H
X
X
L
H
H
H
H
L
H
OUTPUTS
SERIAL
PARALLEL
LEFT RIGHT
A ... H
X
X
X
X
X
X
t
X
X
a ... h
t
X
H
X
QA
QB
L
L
QAO QBO
a
b
...
QG
QH
L
L
QGO QHO
9
h
H
QAn
QFn QGn
L
QAn
H
L
H
!
X
L
X
H
H
L
!
H
X
X
aBn QCn
QFn QGn
QHn H
H
H
L
!
L
X
X
QBn QCn
QHn
H
L
L
X
X
X
X
QAO QBO
QGO QHO
L
high level (steady state), L"" low level (steady state)
irrelevant (any input, including transitions)
t "" transition from low to high level
a ... h ::= the level of steady-state input at inputs A thru H, respectively.
QAO. 0BO. QGO. QHO = the level of 0A. 0B. QG. or 0H, respectively, before the indicated steady-state input conditions were established.
DAn. 0Bn. etc. "" the level of QA. OS. etc., respectively. before the most-recent t transition of the clock.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications par the terms of Texas Instruments
::~:~~i~a[::1~1i ~~:~~~ti:r :.~o::~:~~:~~s not
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-671
SN54198, SN54199 SN74198, SN74199
8·BIT SHIFT REGISTERS
.
SN54199 _ ; _J OR W PACKAGE
SN74199 ___ N PACKAGE
SN54199 and SN74199
These registers feature parallel inputs, parallel
outputs, J-.K serial inputs, shift/load control input, a
direct overriding clear line, and gated clock inputs_
The register has three modes of operation:
(TOPVIEWI
K
J
A
OA
8
08
C
Inhibit Clock (Do nothing)
Shift (In the direction OA toward 0H)
Parallel (Broadside) Load
Parallel loading is accomplished by applying the eight
bits of data and taking the shiftlload control input
low when the clock input is not inhibited. The data is
loaded into the associated flip-flop and appears at the
outputs after the positive transition of the clock
input. During loading, serial data flow is inhibited.
VCC
SH/lO
H
OH
G
°G
F
OF
E
OE
ClR
ClK
Oc
0
00
ClKINH
GNO
Shifting is accomplished synchronously when shift/load is high and the clock input is not inhibited. Serial data for this
mode is entered at the J-K inputs. See the function table for levels required to enter serial data into the first flip-flop.
80th of the clock inputs are identical in function and may be used interchangeably to serve as clock or clock-inhibit
inputs. Holding either high inhibits clocking, but when one is held low, a clock input applied to the other input is
passed to the eight flip-flops of the register. The clock-inhibit input should be changed to the high level only while the
clock input is high.
-I
-I
,...
o
(1)
These shift registers contain the equivalent of 79 TTL gates. Average power dissipation per gate is typically 4_55 mW.
<
c:;(1)
'199
en
FUNCTION TABLE
INPUTS
CLEAR
SHIFTI
CLOCK
CLOCK
OUTPUTS
SERIAL
PARALLEL
QC ••• QH
LOAD
INHIBIT
J
K
A ... H
QA
QB
L
X
X
X
X
X
X
L
L
L
L
H
X
L
L
X
X
X
aAO
aBO
b
Oeo
aHO
h
H
L
L
1
X
X
a ... h
H
H
L
1
L
H
X
H
H
L
1
L
L
X
H
H
L
1
H
H
X
H
H
L
1
H
L
X
H
X
H
!
X
X
X
a
c
aAO aAO aBn
L
aAn °Bn
H
°An °Bn
aGn
aGn
!lAn °An °Bn
aAO aBO aBO
aHO
aGn
aGn
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
vcc--_>---
INPUT
Clear, A thru H: Aeq '" 6 kH NOM
All others: Req "" 4 kH NOM
2-672
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • OAlLAS, TEXAS 75265
SN54198, SN74198
8-BIT SHIFT REGISTERS
logic symbol t
logic diagram (positive logic)
CLOCK -,-(,-,11,,-)_ _- ;
SRG8
SHIFT RIGHT
SERIAL INPUT
-"'"---ti----,
Sl
SR seR
(4)
A
(6)
c
0
(8)
(9)
(10)
(15)
(14)
F (17)
(16)
G (19)
H (21)
SL SER (22)
(18)
e
3,40
(20)
SO
OA
A
-=---"----~ttt=?:=<
B
-'-'15"-1---~lli±~~
C
~17~1_ _ _ _~~-H
OB
Oc
00
Oe
OF
°G
OH
2,40
tThis symbol is in accordance with ANSI/IEEE Std, 91-1984 and
IEC Publication 617-12.
II)
__/
Q)
CJ
'S
' " = = - - - - + + - 4 - ' - " ' - Oc
Q)
C
D ~19~1_ _ _ _~~~L-/
E
1151
F
1171
G
1191
..J
tt-
H _12_1_1_ _ _ _ _+-~_L~
S~~II~: ~~;~T
...:1"'22"'1_ _ _ _ _ _H
CLEAR
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-673
SN54199. SN74199
8·BIT SHIFT REGISTERS
logic symbol t
logic diagram (positive logic)
CLOCK (13)
CLOCK INHIBIT (l!l!JllL-1....)~-----1
(2)
SERIAL INPUTS
~111t=====-=--=--:,-,
SHIFT/LOAD (_2_3), .........".--.
C3/1_
. (4)
K
{
QA
A
(6)
B
(8)
C
(10)
0
-f
-f
r-
E
(16)
(15)
F
(18)
(17)
G
(20)
(19)
H
(22)
(21)
QB
Oc
Qo
B (5)
QE
QF
QG
QH
t This symbol
is in accordance with ANSIIIEEE Std. 91-1984 and
lEe Publication 617-12.
C (7)
C
CD
<
n'
CD
o
(9)
VI
E (16)
F (18)
G (20)
H (22)
-CL-E-A-R~(1~4~)_ _ _ _--~;~-~
2-674
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DAllAS, TEXAS 75265
.-..
-<
"'0
n'
2!.
C"l
Cb
,9.;
CLOCK
so
I
- --
0
Q)
poo
I
I
~
Sl ~L~________________________________~
CLEAR
--U I
:
I
SERIAL{R
INPUTS
~
~
~~
8 ;:o~
N
C~
~ ~"(JJ
fBiTAlL-______________________________~~--------------------------------~
I
,"'
I
L
:
I
:;;
~~------------------------------------~~---------------------------------l------------------~-
D
~'~L~~--------------------------------~--~----------------------------~
:
I
L
I
I
~ Ul4r
Cb
,
'"
I:
I
QB===:~
~
OUTPUTS
GO
~=~:
=~::
°G
===:
OE
OH
::
(g
,00
Vl
....2
c:
::
:::I
00
(g
C"l
CD
'"
Il':
L
===l
OF
!!l
:g
.0
CD
~~~---------------~------------------~======~
QA==J~
L
~
~
Q)
c..
H~
Vl
?" 2c.n
C"l
G~_~
______________________________~~----------------------------L-------------~--,
I
~z
5'
::r
5'
:::I
I
E~~___________________________L~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_
F
Frrl
::r
L __~,--+:--~------------------------------------~~~~
C~~--------------------------------~~--------------------------~--------------~-PARALLEL
DATA
INPUTS
.;,
:;;
,.-..
A~
I
B
"'~z
I
Cb
;::t
.;,
::r
DATA
~
LS
I
cEo
::r
.-..
c:o
CCI
=ien
Z
en
:cUI
_01=0
..,,-
==~:
I_
SHIFT RIGHT
_I I"
SHIFT LEFT
'1-
-f ce
INHIBIT---ti
CLEAR
CLEAR LOAD
::a~
men
!2z
en-..l
-f0l=0
m_
::ace
en=
N
en
-J
01
TTL Devices
SN54199, SN74199
8·BIT SHIFT REGISTERS
, SN54199,SN74199
typical clear, shift, load, and inhibit sequences
-I
-I
,...
o
(1)
<
c)'
:r
-'
:r
(1)
(I)
---- -------- __1
a:
-~-'
~
3
Q)
C
..oJ
~
~
V
mA
~A
mA
mA
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
jAil typical values are at Vee ~ 5 V, TA ~ 25°C.
§ Not
more than one output should be shorted at a time.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-683
SN54221,SN74221
..
DUAL MONOSTABLEMULTIVIBRATORS
WITH SCHMITT·TRIGGER INPUTS
switching characteristics, Vee = 5
V, T A = 25° e
FROM
TO
«.INPUT!
(OUTPUTI
A
a
45
70
B
a
35
55
A
a
50
80
B
Q
40
65
'PHL
Clear
a
'PLH
Clear
a
PARAMETERt
'PLH
'PHL
'w(outl
AorB
TEST CONDITIONS
Cex• = 80 pF, Rex." 2 kn
CL=15pF,
RL=400n,
See Figure 1
and No.e 2
Cex• = 80pF, Rex. - 2 kn
Cex • = 0,
Rex. = 2 kn
Cex • = 100 pF ,Rex. = 10 kn
aorQ
Cex • = 11lF,
t tpLH
Propagation delay time, low-to-high-Ievel output
tpHL .. Propagation delay time, high-to-Iow-Ievel output
IE
tw(outl .. Output pulse width
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
-t
-t
r-
o
CD
<
C)"
CD
(II
2-684
MIN
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Rex. = 10 kn
70
TYP
110
MAX UNIT
ns
ns
27
ns
40
ns
150
20
30
50
650
700
750
6.5
7
7.5
ns
ms
SN54LS221. SN74LS221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMITT·TRIGGER INPUTS
recommended operating conditions
SN54LS221
Supply voltage, Vee
High-level input voltage at A input, VIH
SN74LS221
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
2
low-level input voltage at B input, VIL
High-level output current, 10H
Low-level output current, IOL
Input pulse width
V
0.8
-400
-400
~A
V
8
mA
Schmitt, B
1
1
Vis
Logic input, A
1
1
V/~s
A or B, tw(in)
50
50
elear, tw(clear)
40
40
15
15
Clear-inactive-state setup"time, tsu
External timing resistance, Rext
External timing capacitance, Cext
I RT
Output duty cycle
V
0.7
4
Rate of rise or fall of input pulse, dv/dt
UNIT
I RT
~
2 kG
~
MAX Rext
ns
ns
1.4
70
1.4
100
kG
0
1000
0
1000
~F
50
50
90
-55
Operating free-air temperature, T A
90
125
0
SN54LS221
Typt
MAX
MIN
70
%
°e
recommended operating conditions
PARAMETER
TEST CONDITIONSt
Positive-going threshold
VT+
Vee ~ MIN
voltage at B input
Negative-going threshold
VT-
1.0
Vee ~ MIN
voltage at B input
Input clamp voltage
Vee
~
MIN,
II
VOH High-level output voltage
Vee
~
MIN,
10H
Low-level output voltage
Vee
~
MIN
Vee
~
MAX,
VI
Vee
~
MAX,
VI
VIK
VOL
Input current at
II
IIH
IlL
maximum input voltage
High-level input current
Low-level input current
MIN
~
Input B
Vee
~
MAX,
~
0.7
0.9
2.5
3.4
-18 mA
~
-400
Short-circuit output current §
Vee
Ice
Supply current
Vee
~
~
IIOL ~ 4 mA
1.0
0.8
0.9
2.7
3.4
0.25
VI
~
7V
~
2.7 V
~
0.4 V
-20
I Quiescent
I
2
0.4
V
V
0.4
0.35
0.5
V
0.1
0.1
mA
20
20
~A
-0.4
-0.4
-0.8
-0.8
-0.8
-0.8
-100
-20
...J
lI-
V
0.25
-100
4.7
11
4.7
11
19
27
19
27
Triggered
UNIT
V
-1.5
IIOL ~ 8 mA
MAX
MAX
2
-1.5
~A
elear
lOS
SN74LS221
Typt
MAX
mA
mA
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee ~ 5 V, TA ~ 25°e.
§Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-685
SN54LS221, SN74LS221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMITT·TRIGGER INPUTS
switching charact8ristics. Vee = 5 V. TA = 25°e
PARAMETERt
tPLH
tPHL
tPHL
tpLH
FROM
UNPUTI
TO
(OUTPUTI
A
a
45
70
B
a
35
A
a
B
Clear
Clear
a
a
a
55
80
65
TEST CONDITIONS
Cext = 8OpF, Rext
RL =2 kn,
See Figure 1
AorB
aoro
Cext = 8OpF, Rext - 2 kn
Rext = 2 kn
Cext = 0,
Cext = 100 pF ,R axt = 10 kn
Coxt = 1 "F,
t tpLH _
tpHL ..
tw(out)
NOTE 3:
Propagation delay time, low-to-high-Ievel output
Propagation delay time, high-to-Iow-Ievel output
.. Output pulse width
Load circuits and voltage waveforms are shown in Section 1.
-t
-t
rC
CD
<
c:;'
CD
CI)
2-686
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
R. xt
= 10 kn
TVP
50
= 2 kn
40
CL = 15pF,
and Note 3
iw(outJ
MIN
MAX UNIT
ns
ns
55
ns
65
ns
150
20
670
36
44
120
47
740
70
810
ns
6
6.9
7.5
ms
70
SN54221. SN54LS221. SN74221. SN74LS221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMITT·TRIGGER INPUTS
PARAMETER MEASUREMENT INFORMATION
r+--twlinl4
1 , , - - - - - - ---------3V
~
BINPUT----A'
~--------------------------ov
I
~;,60ns~
I'-------------
----~----------~I
3V
~------------OV
CLEAR:
~tPLH
~tPHL
-I:__...JI
~::
Q OUTPU_T__
J..---+tPHL
I+----*-tPLH
,r-_--_--_--_-----_----_--_--_-_ ~::
'\
Q OUTPUT
A input is low.
TRIGGER FROM B, THEN CLEAR-CONDITION 1
BINPUTJ,
\
-------:~
1.--;'60 nS-----1
V--_________ :~
CLEAR
QOUTPUT
\\.-------------------------------- ~::
/
_--...J
A input is low
n
1
;'50 ns
>
Q)
C
-J
t\-----:~
I~I;;.==~.~I tsetup
_______I-_______~...J
CLEAR~•
Q)
.~
lI-
TRIGGER FROM B, THEN CLEAR-CONDITION 2
BINPUT
If)
-
r.::;,0
f
.
3V
_ _ _ _ _ _ _ _ _ _ _ _ _ OV
TRIGGERED
-----,
Q
OUTP~
____
~~_____________________':
NOT TR IGGERED
A input is low
CLEAR OVERRIDING B, THEN TRIGGER FROM B
I
\
B INPUT______________JI
1
______________ OV
!-"-- ;,50 ns~
--x. __________.J1 __________
1.--;'50 ns..-j
C-L-E-A-R
I~
_ _ _ _ 3V
QOUTPUT
1
3V
0 V
/
-----~
A input is low
TRIGGERING FROM POSITIVE TRANSITION OF CLEAR
FIGURE l-SWITCHING CHARACTERISTICS
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2·687
SN54221. SN54LS221. SN74221. SN74LS221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMITT·TRIGGER INPUTS
PARAMETER MEASUREMENT INFORMATION
r--
AINPU~
tw(inl---t
r---;;.s0
i
CLEAR
.I __ ~ ____ .,. ____
ns-.,
W ~ _____
tPLH~
~
I
3V
OV
~tPHL
I.r"""·~-----VOH
VOL
I
QOUTPUT
3V
OV
: \:..
~tPLH
a OUTPUT
I
/1,.-------_______
\
I
~
_ _ _....J
VOH
VOL
tPHI:--loI"_--~.'
B input is high
TRIGGER FROM A, THEN CLEAR
,.-___________________ 3V
A
INPU~\._ _ _ _
VOH
_____-I ~tw(outl-----...
.tl
VOL
__ _ _ _.., I"
.'-=-
VOH·
a OUTPUT
Band
NOTES:
..
tw(out)_
"
CI::'E'A'R inputs are high
VOL
TRIGGER FROM A
A. Input pulses are supplied by generators having the following characteristics: PRR" 1 MHz. Zout ~ 50 n; for '221, tr:S;;; 7 ns,
tf EO; 7 ns, for 'LS221, tr EO; 15 ns, tf "6 os.
B. All measurements are made between the 1.5 V points of the indicated transitions for the '221 or between the 1.3 V points for the
'LS221.
FIGURE ,-SWITCHING CHARACTERISTICS (CONTINUED)
2-688
OV
,---
QOUTPUT
i
_JI __________
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 76285
SN54221. SN74221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMITT·TRIGGER INPUTS
TYPICAL CHARACTERISTICS ('221 ONL y)t
DISTRIBUTION OF UNITS
for
OUTPUT PULSE WIDTH
VARIATION IN OUTPUT PULSE WIDTH
vs
SUPPL y VOLTAGE
1%
Vcc = 5 V
TA = 25°C
5:
:;
.J
Cext = 60 pF
-R ext = 10 kn
TA = 25°C
0.5%
~
0-
!
I
o
.S
c:
.o
0%
/
.,
."'"
I--
_MEDIAN _
-0.5%
_ MEDIAN_
tOi5~
I 1.1
MEDIAN
1
,-
b'"
I
-0.5%
,/
:;J
-
o
-I 98% OF UNITS.
-1%
4.5
5l
"3
...
0-
FIGURE 2
FIGURE 3
C.
;'
S
0
0%
c:
.-
0
.~
."'"
>I
~
-0.5%
~
~,,'Il
0.5%
--
..... --- -
~(out) "" 420 ns_
.......--at TA = 25°C
.c:
1 ms
-0
~
5:
~
:::=:=:::-Ce)l.t
10l's
0
::J
0
-1%
-75 -50 -25
II's
25
50
75
.-
1
0' Il~
" O·
...--
.-
~
00 I'~
=
- ",
=Ce)l.t
...---
I" ,0 I'~
Vee = 5 V Ce)l.t
100 ns
100 125
.
TA = 25°e
10 ns
0
Il~
=+- ",0001'
=Ce)l.t
:.;::;-- ,
J
<1
~
,,0.'
====:Ce)l.t
0-
Sa.
'5
>--C~
1001's
:;
h
J
0
5.5
OUTPUT PULSE WIDTH
vs
TIMING RESISTOR VALUE
10 ms
::J
.S
5.25
VCC-Supply Voltage-V
Vcc = 5 V
-Cext = 60 pF
Rext = 10 kn
~
5
4.75
tw(out)-Output Pulse Width
1%
'5
-
tw(out) "" 420 ns
atVcc=5V
_
/'
VARIATION IN OUTPUT PULSE WIDTH
vs
FREE-AIR TEMPERATURE
:g
/
::J
1
2
=m~ee
4
.-
Note 4
7 10
20
40
TA--Free-Air Temperature-°c
Rext - Timing Resistor Value-kn
FIGURE 4
FIGURE 5
70100
NOTE 4: These values of resistance ex.ceed the maximum recommended for use over the full temperature range of the SNS4221.
tO ata for temperatures below O°C and above 70°C. and for supply voltages below 4.75 V and above 5.25 V are applicable for the SN54221
.only.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-689
2-690
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244,
SN14LS240, SN14LS241, SN14LS244, SN14S240, SN14S241, SN14S244
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
APRIL 1985-REVISED MARCH 1988
• 3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
SN54LS', SN54S' ... J OR W PACKAGE
SN74LS', SN74S' ... OW OR N PACKAGE
(TOP VIEW)
• PNP Inputs Reduce D-C Loading
vee
lG
lAl
2Y4
lA2
2Y3
• Hysteresis at Inputs Improves Noise Margins
description
These octal buffers and line drivers are designed
specifically to improve both the performance and densi·
ty of three-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters. The
designer has a choice of selected combinations of inverting and noninverting outputs, symmetrical G lactiv~
low output control) inputs, and complementary G and G
inputs. These devices feature high fan·out, improved
fan-in, and 400-mV noise-margin. The SN74LS' and
SN74S' can be used to drive terminated lines down to
133 ohms.
2G/2G*
lYl
2A4
lY2
2A3
lY3
2A2
lY4
2Al
1A3
2Y2
lA4
2Yl
GND
SN54LS', SN54S' ... FK PACKAGE
(TOP VIEW)
The SN54' family is characterized for operation over the
full military temperature range of -55 D e to·125 D e. The
SN74' family is characterized for operation from oDe to
70 D e.
3 2 1 2019
*2G for 'LS241 and '5241 or 2G for all other drivers.
schematics of inputs and outputs
'LS240, 'LS241, 'L5244
'S240, '5241, 'S244
EQUIVALENT OF
EACH INPUT
EQUIVALENT OF
EACH INPUT
TYPICAL OF ALL
OUTPUTS
----..-VCC
VCC--........._
9kn NOM
INPUT
INPUT
OUTPUT
GND
G and
PRODUCTION DATA documents conl.in information
current as of publication date. Products conform to
specifications per the terms of Taxas Instruments
.:~~~~:~~i~8i~:1~7i ~!::i:~i:; :I~U:=::~:~~S not
G inpulS:
Req = 2 kn NOM
A inputs: Req = 2.8 kn NOM
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
'LS240, 'LS241, 'LS244;
R = 50 n NOM
'5240, 'S241 , '5244
R = 25 n NOM
2-691
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244,
SN74SL240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
OCTAL BUFFERS AND LINE DRIVERS WITH ]-STATE OUTPUTS
logic symbols t
,.
,ii
r:!;--:--........1--
{lSI lVl
F--"':"'-"':"L
(16) lV2
(181
'A'
(161
lA2
(14)
lA3
(12)
lA4
lV'
'A'
lV2
lA2
(1S)
1161
(14)
lV3
lA3
lV4
lA4
2Vl
2Al (11)
2V2
2A2 1131
m
ZA3 (151
)5
2A4 (17)
(3)
1121
lV'
lV2
lV3
lV4
2G
ZA1 (11)
'V
(9)
(9) 2V,
2Al
t7I 2Y2
2A2 (13)
m
2A3 (15)
(5)
2A4
(3)
2A2 (13)
ZA3 (15)
(5) 2V3
2A4 (17)
(3) 2Y4
'V
(17)
2V3
2V4
(9)
'V
2V'
2V2
2V3
2V4
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and lEG Publication 617-12.
logic
diagra~s (positive logic)
'LS241, 'S241
'LS240, 'S240
16 (11
-4
-4
r-
C
CD
<
n'
CD
'LS244, 'S244
16 (1)
lJ~--.,
(18) lVl
(18) lY'
lA2 (4)
(161 1Y2
(16) lY2
lA3 (61
(14) 1V3
lA4 (81
(121 1V4
(141 1V3
lA3 (6)
lAl (2)
(18) lVl
(16) lY2
1A3 (61
(141 1Y3
C/I
(12) 1Y4
(121 1Y4
(91 2Vl
(9) 2Vl
2G ('9)
(9)
2Vl
ZA' (11)
m
2V2
(7) zVz
(7) 2V2
(5)
2Y3
(51 2Y3
(5) 2V3
(3)
2Y4
(31 2Y4
(31 2V4
Pin numbers shown are for OW, J, N, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ................................................................. 7 V
Input voltage: 'LS Circuits...................................................................... 7 V
'S Circuits ..................................................................... 5.5 V
Off-state output voltage ........................................... '........................... 5.5 V
Operating free-air temperature range: SN54LS', SN54S' Circuits ............................. - 55" C to 125" C
SN74LS', SN74S' Circuits ................................ 0' C to 70' C
Storage temperature range ........................................................... - 65' C to 150' C
NOTE 1.:
2-692
Voltage values are with respect to network ground terminaL
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS24D, SN54LS241, SN54LS244, SN74LS240, SN74LS241, SN74LS244
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
recommended operating conditions
SN54lS'
PARAMETER
SN74lS'
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
Vee
Supply voltage Isee Note 1)
VIH
High-level input voltage
Vil
Low-level input voltage
IOH
High-level output current
-12
-15
mA
IOL
Low-level output current
12
24
mA
TA
Operating free.-air temperature
70
°e
2
2
-55
125
V
0
NOTE 1: Voltage values are with respect to network ground terminal.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDITIONSt
PARAMETER
Vee = MIN,
VIK
VIH=2V,
VIL = MAX,
VIH=2V,
VIL = 0.5 V,
VIH=2V,
IOl = 12 mA
IOH = -3 mA
VOH
Vee = MIN,
VOL
Vee= MAX,
IOZl
VIL = MAX
VIH=2V,
II
Vee= MAX,
VI = 7 V
Vee=MAX,
VI = 2.7 V
IlL
Vee= MAX,
Vll-O.4V
IOS§
Vee= MAX
0.4
0.2
0.4
2.4
3.4
2.4
3.4
All outputs
UNIT
V
V
V
2
2
til
0.4
0.4
0.5
Output open
disabled
->CJ
/LA
o
Q)
20
20
VO=O.4V
-20
-20
0.1
0.1
mA
20
20
-0.2
/LA
mA
- 225
mA
-0.2
-225
All
Vee=MAX,
V
Vo = 2.7 V
-40
Outputs high
Outputs low
MAX
-1.5
IOL = 24 mA
IIH
lee
TYP*
Q)
VIL = MAX
IOZH
MIN
0.2
IOH = MAX
Vee= MIN,
MAX
-1.5
Vee = MIN
Vee= MIN,
TYP*
11=-18mA
Hysteresis
IVT+-VT_)
SN74lS'
SN54lS'
MIN
-40
17
27
44
26
44
46
27
46
29
50
29
50
32
54
32
54
17
27
'LS240
26
'LS241 , 'LS244
27
'LS240
'LS241, 'lS244
..J
....
....
mA
t For conditions shown as MI N or MAX. use the appropriate value specified under recommended operating conditions.
:t: All typical values are at Vee = 5 V, TA "" 2SoC.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
MIN
tplH
RL = 667
n,
'lS241, 'LS244
'lS240
TEST CONDITIONS
eL = 45 pF,
TYP
MAX
9
14
MIN
UNIT
TYP
MAX
12
18
ns
12
18
12
18
ns
tpZL
20
30
20
30
ns
tpZH
15
23
15
23
ns
10
20
10
20
15
25
15
25
ns
ns
tpHL
See Note 2
n,
tPLZ
RL = 667
tPHZ
See Note 2
eL = 5 pF,
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-693
SN54S240, SN·54S241, SN54S244, SN74S240, SN74S241, SN74S244,
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
recommended operating conditions
Vee
Supply voltage, Isee Note 1)
VIH
High·level input voltage
VIL
Low·level input voltage
IOH
IOL
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
UNIT
V
V
2
0.8
0.8
High-level output current
-12
-15
mA
Low·level output current
48
40
,64
mA
40
k!1
70
'e
External resistance between any input and Vee or ground
-55
Operating free·air temperature (see Note 3)
TA
SN74S'
SN54S'
PARAMETER
125
0
V
NOTES: 1. Voltage values are wIth respect to network ground terminal.
3. An S~54S241J operating at free-air"temperature above 116°C requires a heat sink that provides a thermal resistance from case to
free-air ReCA. of not more than 40 C/W.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Vee = MIN,
VIK
SN54S'
TEST eONDITIONst
MIN
0.2
Vee= MIN
Vee=MIN,
-I
-I
SN74S'
MAX
0.4
Vee - MIN,
VOH
CD
o·
CD
Vee - MIN,
VOL
en
Vee= MAX,
IOZL
VIL = 0.8 V,
V
3.4
V
VIH- 2V,
VIL - 0.8 V,
VIH-2V,
VIL - 0.5 V,
VIH-2V,
VIL -0.8V,
0.55
0.55
VIH-2V,
I
VO-2.4V
50
50
1
VO=0.5V
- 50
- 50
2.4
3.4
2.4
2
2
!-LA
II
Vee - MAX,
VI- 5.5 V
1
1
mA
Vee = MAX,
VI = 2.7 V
50
50
!-LA
Vee = MAX,
VI = 0.5 V
-400
-400
!-LA
-2
-2
rnA
-225
rnA
'1
Any A
Any G
-50
Vee - MAX
IOS§
'5240
Outputs high
-225
80
123
- 50
80
135
95
147
95
160
'S240
100
145
100
150
'S241 , 'S244
120
170
120
180
Outputs
'S240
100
145
100
150
disabled
'S241 , 'S244
120
170
120
180
Outputs low
'S241 , 'S244
Vee = MAX,
Outputs open
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:t All typical values are at Vee::; 5 V. T A
= 25° C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
2-694
V
IIH
IILI
lee
V
2.7
IOL = MAX
IOZH
UNIT
0.4
VIL = 0.8 V,
IOH= MAX
<
MAX
VIH=2V,
IOH= -3rnA
Vee- MIN,
TVP~
-1.2
0.2
IOH = -1 rnA
rC
MIN
-1.2
11=-18rnA
Hysteresis
IVT+-VT )
TVP~
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
rnA
SN54S240. SN54S241. SN54S244.SN74S24l SN74S241. SN74S24'
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
switching characteristics,
PARAMETER
Vee
= 5 V, T A = 25°e
'5241, '5244
'5240
TEST CONDITIONS
TYP
MAX
4.5
4.5
tpZL
tpZH
MIN
tpLH
tpHL
RL" 90 n,
See Note 4
tpLZ
RL-90n,
tPHZ
See Note 4
CL"50pF,
CL - 5 pF,
MIN
UNIT
TYP
MAX
7
6
9
ns
7
6
9
ns
10
15
10
15
6.5
10
8
12
ns
ns
10
15
10
15
6
9
6
9
ns
ns
NOTE 4: Load circuits and voltage waveforms are shown in Section 1.
I/)
Q)
()
'S;
Q)
C
..J
lI-
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-695
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244,
SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
DRIVER
1/8 'LS2411'S241
lOll
REPEATER
LONG-LINE
REPEATER
_I
REPEATER
~~~~241I'Sr
:t CL
jt
:t
jt
~
~
~
RECEIVER
1/8 LS2411'S241
B>0UTPUT
~
:::~~::B:':'~:'EE~:'B:~E:~~:'':-8:'::
j::_-S:. _____'i-_-J,: _____ -:J_-_-J;:. _____i __-J,: _____ -:J~_"±_
O,3v _ _ _ _ _
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
'LS241, 'S241 USED AS REPEATER/LEVEL RESTORER
OUTPUT {
CONTROL
-t
-t
~--------------~vr--~--~~--~--~
C
'LS2401'S240 USED AS SYSTEM AND/OR MEMORV BUS DRIVER-4-BIT
ORGANIZATION CAN BE APPLIED TO HANDLE BINARY OR BCD
r-
SYSTEM AND/OR MEMORY-ADDRESS BUS
CD
<
c:r
CD
en
1/4 'LS241/'S241
OUTPUT
PORTS
FROM
DATA
BUS
INPUT A
PARTY-LINE
MULTIPLE-INPUT/OUTPUT BUS
--+--1
I---:--I!IIPUT B
~3~~~~R _-+---."':-.J
1-.:._-l_~~3WEH::
--!----!I--<.
OUTPUT A __
">--I--1--0UTPUT B
~
BUS
CONTROL
-~
INPUT
PORTS
H
L
L
H
TO
DATA
BUS
L
L
H
RECEIVERS
INPUT
OUTPUT
-A--BB
A
A
NONE
B
B
A
NONE
BUS
CONTROL
-L---LH
H
L
L
L
H
H
H
PARTY-LINE BUS SYSTEM
WITH MULTIPLE INPUTS, OUTPUTS, AND RECEIVERS
INDEPENDENT 4-BIT BUS OR IVERS/RECEIVERS
IN A SINGLE PACKAGE
2-696
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54LS242. SN54LS243. SN74LS242. SN74LS243
QUADRUPLE BUS TRANSCEIVERS
APRIL 1985-REVISEO MARCH 1988
• Two-Way Asynchronous Communication
Between Data Buses
SN54LS242, SN54LS243 ..• J OR W PACKAGE
SN74LS242, SN74LS243 ... 0 OR N PACKAGE
ITOP VIEWI
• PNP Inputs Reduce D-C Loading
GAB
NC
A1
A2
A3
A4
• Hysteresis (Typically 400 mY) at Inputs
Improves Noise Margin
description
These four-data-line transceivers are designed for asynchronous two-way communications between data
buses. The SN74LS' can be used to drive terminated
lines down to 133 ohms.
The SN54' family is characterized for operation over the
full military temperature range of - 55 DC to 125 DC. The
SN74' family is characterized for operation from DoC to
VCC
GBA
NC
B1
B2
B3
B4
GND
SN54LS242, SN54LS243 ... FK PACKAGE
ITOP VIEW)
ID
U«U
70 D C.
ZI(!) Z
3
2
«
U
UID
>
(!)
1 2019
FUNCTION TABLE (EACH TRANSCEIVERI
4
INPUTS
5
6
(/l
7
(,J
8
:>
GAB
GBA
'LS242
'LS243
L
L
Ato B
Ato B
H
H
Bto A
B to A
H
L
Isolation
Isolation
L
H
Latch A and B
(A=BI
Latch A and B
Q)
Q)
C
IA = B)
NC-No internal connection
...I
....
....
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
----~-VCC
VCC----...---
50 fl NOM
INPUT
OUTPUT
...-
-....-<~.-
PROOUCTIOI DATA documants contain information
currant 81 of publication dati. P"ducts conform to
spacifications par the terms of TaXI. Instruments
:=:=i~.i;:I~~i ~::i:~ti:r :.~.::;:::~:~~ not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
GND
2-697
SN54LS242, SN54LS243, .SN74LS242, SN74LS243
QUADRUPLE BUS TRANSCEIVERS
logic symbols t
'LS243
'LS242
GBA
GBA
GAB
GAB
A1
A1
B1
A2
A2
B2
A3
A3
B3
A4
A4
B4
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12.
logic diagrams (positive logic)
'LS242
'LS243
-I
-I
r-
C
CD
<
Cr
CD
til
Pin numbers shown are for D, J. N. and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage .............................................................................. 7 V
Off-state output voltage .................................................................... 5.5 V
Operating free-air temperature range: SN54LS·......................................... - 55°C to 125°C
SN74LS' ............................................. oOe to 70°C
Storage temperature range ......................................................... - 65°C to 150°C
NOTE1: Voltage values are with respect to network ground terminal.
2-698
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS242, SN54LS243, SN74LS242, SN74LS243
QUADRUPLE BUS TRANSCEIVERS
recommended operating conditions
SN54LS'
Vee
Supply voltage, (see Note 1 )
VIH
High~level
VIL
Low-level input voltage
10H
High-level output current
10L
Low-level output current'
TA
Operating free-air temperature
input voltage
SN74LS'
!\(lIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.7
0.8
-12
-15
mA
24
mA
70
"c
12
- 55
UNIT
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
Aor B
VIK
MIN
VIH=2V,
VIL = MAX,
VIH=2V,
VIL-0.5V,
VIH=2V,
10L = 12mA
10H = - 3 mA
Vee = MIN,
10H= MAX
Vee = MIN,
VOL
VIL = MAX
10ZH
Vee - MAX,
10ZL
VIL = MAX
I
II
Aor B
GAB or GSA
II
A inputs
IlL
B inputs
GAB or GBA
VIH-2V,
Vee= MAX,
Vee = MAX,
VI=2.7V
Vee = MAX,
VI = 0.4 V,
0.2
0.4
2.4
3.1
2.4
3.1
Vee = MAX,
All outputs
See Note 2
0.25
V
0.4
0.25
0.4
0.35
0.5
fI)
CJ
40
40
}.I A
VO=O.4V
- 200
-200
}.IA
VI =5.5V
0.1
0.1
VI = 7 V
0.1
0.1
20
20
-0.2
- 0.2
- 0.2
- 0.2
-0.2
- 225
Q)
V
VO-2.7 V
-40
disabled
V
2
VI=O.4V
Outputs open,
UNIT
V
2
VI = 0.4 V,
Vee= MAX,
MAX
-1.5
0.4
GAB and GBA at 4.5 V
Outputs low
TYP*
0.2
GAB and GBA at 0 V
Vee= MAX,
Outputs high
ICC
MIN
IOL=24mA
Vee - MAX
105§
SN74LS'
MAX
-1.5
Vee- MIN
Vee = MIN,
VOH
TYP*
11=-lSmA
Vee= MIN,
Hysteresis (VT+ - VT I
SN54LS'
TEST CONOITIONSt
PARAMETER
>
Q)
o
mA
....J
lI-
}.IA
mA
- 0.2
- 40
-225
'LS242, 'LS243
22
38
'LS242, •LS243
29
50
29
50
'LS242
29
50
29
50
'LS243
32
54
32
54
22
mA
38
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
1: All typical values are at Vee"" 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with transceivers enabled in one direction only, or with all transceivers disabled.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
TEST CONDITIONS
'LS242
MIN
tpLH
tpHL
RL=667f2
See Note 3
tpZL
eL = 45 pF,
tpZH
i--___tPLZ
tpHZ
--
RL = 667
n,
eL = 5 pF,
See Note 3
TYP
'LS243
MAX
MIN
TYP
MAX
UNIT
9
14
12
18
ns
12
18
12
18
ns
20
30
20
30
ns
15
23
15
23
ns
10
20
10
20
ns
15
25
15
25
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-699
-f
-f
r-
oCD
!S.
(")
CD
CIl
2-700
SN54LS245, SNa4LS245
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
OCTOBER 1976-REVISED MARCH 1988
SN54LS245 ••. J OR W PACKAGE
SN74LS245 ••• OW OR N PACKAGE
(TOP VIEW)
• Bi-directional Bus Transceiver in a HighDensity 2O-Pin Package
• 3-State Outputs Drive Bus Lines Directly
CURRENT)
10H
(SOURCE
CURRENT)
SN54LS245
12 rnA
-12 rnA
SN74LS245
24mA
-15 rnA
Bl
B2
B3
B4
B5
B6
B7
B8
A4
A5
A6
A7
• Typical Propagation Delay Times.
Port-to-Port ... 8 ns
10L
(SINK
G
A2
A3
• Hysteresis at Bus Inputs Improve Noise
Margins
TYPE
Vec
DIR
Al
• PNP Inputs Reduce D-C Loading on Bus Lines
AS
GND
SN54LS245 .•. FK PACKAGE
(TOP VIEW)
description
These octal bus transceivers are designed for asyn·
chronous two·way communication between data
buses. The control function implementation minimizes
external timing requirements.
~
~ !!:
«
0
tl
> ICl
(I)
3 2 1 2019
CI,)
(,)
->
The devices allow data transmission from the A bus to
the B bus or from the B bus to the A bus depending
upon the logic level at the direction control (DIR) input.
The enable input (G) can be used to disable the device
so that the buses are effectively isolated.
'
CI,)
c
...J
........
The SN54LS245 is characterized for operation over the
full military temperature range of -55°C to 125°C. The
SN74LS245 is characterized for operation from O°C to
70°C.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCCfrf---
FUNCTION TABLE
TYPICAL OF ALL OUTPUTS
---~-VCC
9 kn NOM
INPUT
OUTPUT
ENABLE
G
DIRECTION
CONTROL
OPERATION
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
H = high level, L "" low level, X = irrelevant
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
2-701
SN54LS245. SN74LS245
OCTAL BUS TRANSCEIVERS WITH 3~STATE OUTPUTS
logic symbol t
logic diagram (positive logic)
G (191. r--.
DIR
A't
A2
A3
A4
A5
A6
A7
A8
(1)
r-...
L
(2)
L
DIR ..:.(1.;.;.).....--1
G3
3 EN1(BA)
,
(19)
3 EN2 (AB)
r
\71
2\7
(18)
---.l
(3)
(17)
(4)
(16)
(5)
(15)
(6)
(14)
(7)
,(13)
(8)
(12)
(9)
(11)
Bl
G
(2)
Al
(18) Bl
B2
B3
(3)
A2
B4
(17) B2
B5
B6
(4)
A3
B7
(16)
B3
B8
A4 (~)
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for OW, J, N, and W packages.
(15)
B4
A5
(6)
(14) B5
A6 (7)
(13)
B6
A7 (8)
(12) B7
A8 (9)
(11) B8
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54LS245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
SN74LS245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DoC to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
2-702
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
recommended operating conditions
SN54LS245
PARAMETER
Supply vol tage, Vee
MIN
NOM
4.5
5
High-level output current, IOH
SN74LS245
MIN
NOM
MAX
5.5
4.75
5
5.25
V
-15
mA
24
mA
70
°e
-12
Low-level output current, IOL
12
Operating free-air temperature, T A
UNIT
MAX
-55
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST eONDITIONSt
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
Vee = MIN,
Hysteresis (VT+ - VT_~A or B input
Vee - MIN
High-level output voltage
Vee = MIN,
10L = 12 mA
Vee= MAX,
Off-state output current,
e; at2
I nput current at
UNIT
V
0.7
0.8
V
-1.5
-1.5
V
0.2
0.4
0.2
0.4
2.4
3.4
2.4
3.4
V
2
2
0.4
0.4
V
IOL=24mA
0.5
Q)
I
AorS
I DIR or G
20
VO=2.7V
Vo = 0.4 V
VI-5.5V
Vee = MAX,
":;
20
~A
V
VI
7V
-200
-200
0.1
0.1
0.1
0.1
mA
IIH
High-level input current
Vee = MAX,
VIH = 2.7 V
20
20
~A
Low-level input current
Vee = MAX,
VIL=O.4V
-0.2
-0.2
mA
lOS
Short-circuit output current §
Vee = MAX
-225
mA
-40
I Total, outputs high
Supply current (Total, outputs low
.-
.-~-
-
I Outputs at Hi-Z
Vee = MAX,
Outputs open
-225
48
70
62
64
-40
48
70
90
62
90
95
64
95
Q)
C
IlL
ICC
II)
CJ
high-level voltage applied
maximum input voltage
MAX
VIH=2V,
low-level voltage applied
II
TYPt
V
10H = MAX
Off-state output current,
10ZL
IOH=-3mA
MIN
2
11= -18mA
VIL = VIL max
VIL = VIL max
10ZH
SN74LS245
MAX
VIH=2V,
Low-level output voltage
VOL
TYPt
2
Vee = MIN,
VOH
SN54LS245
MIN
..........J
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee ~ 5 V, TA ~ 25°C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
switching characteristics. Vee = 5 V, T A = 25°e
PARAMETER
TEST CONDITIONS
Propagation delay time,
tPLH
low-to-high-Ieveloutput
Propagation delay time,
tpHL
high-to-Iow-Ievel output
eL = 45 pF,
RL=667U,
See Note 2
MIN
TYP
MAX
8
12
UNIT
ns
8
12
ns
tPZL
Output enable time to low level
27
40
ns
tpZH
Output enable time to high level
25
40
ns
tPLZ
Output disable time from low level
15
25
ns
tpHZ
Output disable time from high level
15
28
ns
eL = 5 pF,
RL =667U,
See Note 2
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
2-703
-I
-I
r-
C
CD
c::
C'l
CD
II)
2-704
SN54246. SN54247. SN54LS247. SN54LS248
SN74246. SN74247. SN74LS247. SN74LS248
BCD-TD-SEVEN-SEGMENT DECODERS/DRIVERS
MARCH 1974-REVISED MARCH 1988
'246, '247, 'LS247
'LS248
feature
feature
•
Open-Collector Outputs Drive Indicators
Directly
•
Internal Pull-Ups Eliminate Need for External
Resistors
•
Lamp-Test Provision
•
Lamp-Test Provision
•
Leading/Trailing Zero Suppression
•
Leading/Trailing Zero Suppression
•
All Circuit Types Feature Lamp Intensity Modulation Capability
DRIVER OUTPUTS
TYPE
TYPICAL
ACTIVE
OUTPUT
SINK
MAX
POWER
LEVEL
CONFIGURATION
CURRENT
VOLTAGE
DISSIPATION
SN54246
low
open-collector
40 rnA
30 V
320rnW
SN54247
low
open-collector
40 rnA
15 V
320rnW
J,W
SN54LS247
low
open-collector
12 rnA
15 V
35rnW
J,W
SN54LS248
high
2-kl! pull-up
2 rnA
5.5 V
125rnW
J,W
SN74246
low
open-collector
40 rnA
low
open-collector
40 rnA
320rnW
320rnW
J.N
SN74247
30 V
15 V
SN74LS247
low
open-collector
24 rnA
15 V
35rnW
J.N
SN74LS248
high
2-kl! pull-up
6 rnA
5.5 V
125rnW
J.N
SN54246. SN54247 ... J PACKAGE
SN54LS247 THRU SN54LS248 ... J OR W PACKAGE
SN74246_ SN74247 ... N PACKAGE
SN74LS247. SN74LS248 ... D OR N PACKAGE
J.N
ITOPVIEW\
U
UU
UIDZ> ...
Vee
B
J,W
SN54LS247. SN54LS248 ... FK PACKAGE
ITOPVIEW\
e
PACKAGES
3 2
1 20 t9
f
9
Bl/RBO
4
RBI
b
0
c
A
d
GND
Ne - No internal connection
PRODUCTION DATA d•••m..........i. inform.ti••
current 81 of pablicatioD date. Products conlor.. to
specifications per the tlrms of TexH Instruments
:~=~~ir,·i~:r.~i ~::::r 11r::::::~~~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-705
SN54246. SN54247. SN54LS247.· SN54LS248
SN74246. SN74247. SN74LS247. SN74LS248
BCD·TO·SEVEN·SEGMENTDECODERS/DRIVERS
description
The '246 and '247 are electrically and functionally identical to the SN5446A/SN7446A, and
SN5447A/SN7447A respectively, and have the same pin assignments as their equivalents. The 'LS247
and 'LS248 are electrically and functionally identical to the SN54LS47/SN74LS47 and
SN54LS48/SN74LS48, respectively, and have the same pin assignments as their equivalents. They can
be used interchangeably in present or future designs to offer designers a choice between two indicator
fonts. The '46A, '47A, 'LS47, and 'LS48 compose the b and the
without tails and the '246, '247,
'LS247, and 'LS248 compose the 5 and the 9 with tails. Composition of all other characters, including
display patterns for BCD inputs above nine, is identical. The '246, '247, and 'LS247 feature active-low
outputs designed for driving indicators directly, and the 'LS248 features active-high outputs for driving
lamp buffers. All of the circuits have full ripple-blanking input/output controls and a lamp test input. Segment
identification and resultant displays are shown below. Display patterns for BCD input counts above 9 are
unique symbols to authenticate input conditions.
All of these circuits incorporate automatic leading and/or trailing-edge zero-blanking control (RBI and RBO).
Lamp test (LT) of these types may be performed at any time when the BI/RBO node is at a high level.
All types contain an overriding blanking input (BI) which can be used to control the lamp intensity by pulsing
or to inhibit the outputs. Inputs and outputs are entirely compatible for use with TTL logic outputs.
Series 54 and Series 54LS devices are characterized for operation over the full military temperature range
of - 55 DC to 125 DC; Series 74 and Series 74LS devices are characterized for operation from 0 DC to 70 DC.
-i
-i
rC
.
.'I_
L }
CD
n·
"I-,,-I,
CIl
SEGMENT
IDENTIFICATION
<
CD
NUMERICAL DESIGNATIONS AND RESULTANT DISPLAYS
logic symbols t
'LS248
'246. '247, 'LS247
(4)
(5)
BINIY.j-~~G C>
.....
1...::: sz
.....
(4)
BiIRBO
;>1
&
RBI
G21
(3)
L
V20
A
B
C
D
(7)
(1)
(2)
(6)
1
LT
a 20,21 Q
b 20.21 Q
d 20.21 Q
4
e 20.21 Q
8
f
20.21Q
9 20.21Q
(13)
(12)
(11)
b
A
(10)
B
(9)
C
(15)
D
.....
&
(7)
L
G21
(1)
(2)
(6)
CT=OL
V20
1
a iii.21 ~
(13)
~
(121
(11)
b 20.21
c 20.21~
2
d 20,21 ~
4
e 20.21
8
f
(14)
~
20.21~
9 20.21~
tThese symbols are in accordancewilh ANSIIIEEE Std. 91-1984 and lEG Publication 617-12.
Pin numbers shown are for Of J, N, and W packages.
2-706
BIN/7-SEG
IT2J
;>1
(3)
cT=oL __
c 20.21Q
2
(5)
....
1...::: sz
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012. DALL.AS. TEXAS 75265
(10)
(9)
(15)
(14)
b
SN54246. SN54247. SN54LS247. SN54LS248
SN74246. SN74247. SN74LS247. SN74LS248
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
'246, '247, 'LS247 FUNCTION TABLE IT1)
DECIMAL
INPUTS
OR
OUTPUTS
Bf/RBOt
FUNCTION
LT
RBI
0
H
H
L
L
L
L
1
H
X
L
L
L
H
2
H
X
L
L
H
3
4
H
X
L
L
H
X
I
5
H
X
6
H
7
NOTE
•
a
b
c
H
ON
ON
ON
ON
ON
ON
9
OFF
H
OFF
ON
ON
OFF
OFF
OFF
OFF
L
H
ON
ON
OFF
ON
ON
OFF
ON
H
H
H
ON
ON
ON
ON
OFF
OFF
ON
H
L
L
H
OFF
ON
ON
OFF
OFF
ON
ON
L
H
L
H
H
ON
OFF
ON
ON
OFF
ON
ON
X
L
H
H
L
H
ON
OFF
ON
ON
ON
ON
ON
H
X
L
H
H
H
H
ON
ON
ON
OFF
OFF
OFF
OFF
D
C
B
A
d
f
1
8
H
X
H
L
L
L
H
ON
ON
ON
ON
ON
ON
ON
9
H
X
H
L
L
H
H
ON
ON
ON
ON
OFF
ON
ON
10
H
X
H
L
H
L
H
OFF
OFF
OFF
ON
ON
OFF
QN
11
H
X
H
L
H
H
H
OFF
OFF
ON
ON
OFF
OFF
ON
12
H
X
H
H
L
L
H
OFF
ON
OFF
OFF
OFF
ON
ON
13
H
X
H
H
L
H
H
ON
OFF
OFF
ON
OFF
ON
ON
14
H
X
H
H
H
L
H
OFF
OFF
OFF
ON
ON
ON
ON
15
H
X
H
H
H
H
H
OFF
OFF
OFF
OFF
OFF
OFF
OFF
BI
X
X
X
X
X
X
L
OFF
OFF
OFF
OFF
OFF
OFF
OFF
2
R81
H
L
L
L
L
L
L
OFF
OFF
OFF
OFF
OFF
OFF
OFF
3
LT
L
X
X
X
X
X
H
ON
ON
ON
ON
ON
ON
ON
4
I/)
CI)
(,)
oS;
CI)
C
...I
'LS24B FUNCTION TABLE IT2)
DECIMAL
OR
FUNCTION
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
81
RBI
LT
INPUTS
RBI
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
H
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D
L
L
L
L
L
L
L
L
H
H
H
H
H
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
OUTPUTS
BfiiUiO t
LT
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
a
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
H
L
H
H
H
H
H
L
L
L
H
L
L
L
L
H
b
H
H
H
H
H
L
L
H
H
H
L
L
H
L
L
L
L
L
H
c
H
H
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
H
d
H
L
H
H
L
H
H
L
H
H
H
H
L
H
H
L
L
L
H
e
H
L
H
L
L
L
H
L
H
L
H
L
L
L
H
L
L
L
H
lI-
NOTE
f
H
L
L
L
H
H
H
L
H
H
L
L
H
D~
L
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
H
1
2
3
4
H = high level. L = low level, X "" irrelevant
NOTES: 1. The blanking input (ei) must be open or held at a high logic level when output functions 0 through 15 are desired. The
ripple·blanking input
must be open or high if blanking of a decimal zero is nOt desired.
(RBil
2. When a low logic level is applied directly to the blanking input (sT), all segment outputs are low regardless of the level of any
other input.
3. When ripple-blanking input CAEii') and inputs .A. B, C, and 0 are at a low level with the lamp test input high, all segment outputs
go low and the ripple-blanking output (ABO) goes to a low level (response condition).
4. When the blanking input/ripple-blanking output (aUABO) is open or held high and a low is applied to the lamp"test input, all
segment outputs are high.
tBT/RBO
is wire·AND logic serving as blanking input (ei) and/or ripple-blanking output (RBO)'
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·707
SN54246, SN54247, SN54LS247,
SN74246, SN74247, SN74LS247
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
logic diagram (positive logicl
'246, '247, 'LS247
INPUT (6)
o
Bl/RBO
BLANKING
(4)
INPUT OR
RIPPLE·BLANKING
OUTPUT
RBI
RIPPLE'BLANKING.!:(5:!.)~---,
INPUT
..::t.---'
L . . . - - - -_ _ _ _
Pin numbers shown are for D, J, N, and W packages.
2-708
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75·265
SN54LS248, SN74LS248
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
logic diagram (positive logic)
'LS248
INPUT.::12:':')---I...r"'-'"
~~----H±~iG~
C
INPUT (6)
o
I/)
Q)
(.)
0>
BLANKING
INPUT OR
(4)
RIPPLE.BLANKING':":':'-+---·
OUTPUT
Q)
C
...J
lI-
-+_.J
LAMP-TEST .:::13,,-)
INPUT
Pin numbers shown are for 0, J, N, and W packages.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-709
SN54246. SN54247. SN74246. SN74247
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
schematics of inputs and outputs
'246, '247
'246, '247
Q
EaUIVALENT OF EACH INPUT
EXCEPT Bl/RBO
VCC
EaUIVALENT OFBl/RBO
6 kn NOM
INPUT
-I
-I
r
--
'246, '247
TYPICAL OF OUTPUTS
a THRU 9
C
CD
<
----------~--._----VCC
c)'
OUTPUT
CD
(/)
2·710
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54LS247. SN54LS248. SN74LS247. SN74LS248
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
schematics of inputs and outputs
'LS247, 'LS248
'LS247, 'LS248
EOUIVALENT OF EACH INPUT
EXCEPT BI/RBO
EOUIVALENT OF iii/RBO
Vee
[-1
vee::E---
10k!"!
Req
'"eo'
[1' and
RBi:
A, B. C, and D:
NOM
Req '" 20 k{l NOM
Req = 25
kn
NOM
'LS247
'LS248
TYPICAL OF OUTPUTS
a THRU 9
TYPICAL OF OUTPUTS
a THRU 9
C/)
Q)
(.)
:>
Q)
C
-----------1~---.------Vee
----------~.---~~VCC
2kn
NOM
r
lI-
OUTPUT
-,~/
OUTPUT
.r-~
,L
...J
_ _ _ - ._ _ _ _ _
..---j~_.--------'
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-711
SN54246, SN54247, SN74246, SN74247
BCD·TD·SEVEN·SEGME!IIT DECODERS/DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . .
Input voltage . . . . . . . . . . . . .
Current forced into any output in the off state
Operating free·air temperature range: SN54246, SN54247
SN74246, SN74247
Storage temperature range
7V
5.5V
1 mA
-55°C to 125°C
O°C to 70°C
_65°C to 150°C
NOTE1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54246
MIN
Supply voltage, Vee
•
4.5
5
SN74246
SN54247
NOM MAX
MIN
5.5
NOM MAX
4.5
5
MIN
5.5
4.75
SN74247
NOM MAX
MIN
5.25
4.75
5
15
30
NOM MAX
5
30
UNIT
5.25
V
15
V
mA
Off·state output voltage, VO(oW
a thru 9
On-state output current. 10(on)
a thru 9
40
40
40
40
High-level output current, fOH
BI/RBO
-200
-200
-200
-200
p.A
Low-level output current, tOl
BI/RBO
8
8
8
8
mA
De
-55
Operating free-air temperature. T A
125
-55
125
0
70
0
70
electrical characteristics over recommended operatmg free·alr temperature range (unless otherwise noted)
-I
-I
rC
(I)
<
C;"
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
TEST eONDITloNst
VOL
TYPt MAX UNIT
V
2
Bi/RBO
(I)
en
MIN
Low-level output voltage
BI/RBO
10(off)
Off-state output current
a thru 9
VO(on)
On-state output voltage
a thru 9
II
Input current at maximum input voltage
IIH
High-level input current
Any input
except BI/RBO
Any input
except BI/RBO
Vee = MIN,
11=-12mA
Vee- MIN,
VIH - 2 V,
VIL = 0.8 V,
10H = -200#A
Vee- MIN,
VIH - 2 V,
VIL = 0.8 V,
10L = 8 mA
2.4
VIH -2V,
VIL = 0.8 V,
10(on) = 40 mA
0.27
0.3
except Bi/RBO
Low·level input current
BI/RBO
Short·circuit output current
Supply cu rren t
V
0.4
V
250
#A
0.4
V
1
mA
Vee = MAX, VI=2.4V
40
#A
-1.6
Vee = MAX, VI =O.4V
mA
-4
BI/RBO
lOS
lee
V
Vee = MAX, VI=5.5V
Any input
IlL
V
1.5V
3.7
Vee MAX, VIH 2V,
VIL = 0.8 V, VO(oW = MAX
Vee- MIN,
0.8
--4
Vee= MAX
Vee= MAX, See Note 2
64
103
mA
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee'" 5 V. T A = 25°C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.
switching characteristics, Vee
= 5 V, TA = 25°e
PARAMETER
toff
Turn·off time from A input
ton
Turn·on time from A input
toff
Turn·off time from
ton
Turn·on time from RBI input
TEST eONDITIONS
TYP
MAX UNIT
100
eL=15pF,
RBI input
See Note 3
RL=120n,
100
100
100
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-712
MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ns
ns
SN54LS247. SN74LS247
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . .
Input voltage . . . . . . . . . . . . . . .
Peak output current (tw";; 1 ms, duty cycle";; 10%)
Current forced into any output in the off state
Operating free·air temperature range: SN54LS247
SN74LS247
Storage temperature range
7V
7V
200mA
. . . . 1 mA
_55°C to 125°C
o°c to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN74LS247
SN54LS247
MIN
Supply voltage, Vee
4.5
NOM
5
MAX
MIN
NOM
5.5
4.75
5
MAX
5.25
UNIT
V
Off·stat. output voltag., VOloffl
a thru 9
15
15
V
On-state output current, 10(on)
a thru 9
12
24
mA
High-level output current. IOH
BI/RBO
50
50
Low-level output current. tOl
IIT/RBO
1.6
3.2
/J A
mA
70
e
-55
Operating free--air temperature, T A
125
0
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
MIN
High-level input voltage
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage Bi/RBO
VOL
Low-level output voltage Bt/RBO
1010ffl
Off-state output current
Vee· MIN,
Vee= MIN,
11-
18mA
VIH=2V,
2.4
VIL· VIL max, 10H· -50/JA
Vee· MIN,
IIOL·l.6mA
VIH = 2 V,
VIL. VIL max iIOL· 3.2 mA
Vee· MAX,
a thru 9
0.25
0.25
Il0lonl· 12 mA
VIH· 2 V,
VIL = VIL max II0loni = 24 mA
II
Input current at maximum input voltage
Vee· MAX,
VI = 7V
IIH
High-level input current
Vee· MAX,
VI = 2.7 V
lOS
ICC
Low-level input current
Short-circuit
output current
except iii/ABO Vee· MAX,
BIIRBO
IiT/RBO
VI =0.4V
Vee· MAX,
1.5
V
2.4
0.4
0.25
0.4
0.35
0.5
·S
CD
C
......
-I
V
4.2
250
0.4
0.25
0.4
0.35
0.5
/JA
0.1
0.1
mA
20
20
I'A
-0.4
-0.4
-1.2
-1.2
-2
-0.3
Vee= MAX
Supply current
1.5
CD
U
V
Any input
IlL
V
250
Vee= MIN,
a thru 9
0.8
en
V
VIH=2V,
On-state output voltage
V
0.7
4.2
VIL· VIL max, VOloff)· 15 V
VOlonl
SN74LS247
UNIT
TVP; MAX
MIN
2
2
VIL
VIH
SN54LS247
TVP; MAX
TEST eONDITloNst
PARAMETER
7
S•• Not. 2
-0.3
7
13
mA
-2
mA
13
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions_
tAli typical values are at Vec =: S V, T A = 2SoC.
NOTE 2: Ice is measured with all outputs open and all inputs at 4.5 v.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
toff
Turn-off time from A input
ton
Turn-on time from A input
toff
Turn-off time from RBI input
ton
Turn-on time from RBI input
TEST CONDITIONS
MIN
TVP
MAX UNIT
100
CL
~
15pF, RL=665n,
S.e Note 3
100
100
100
ns
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2·713
SN54LS248. SN74LS248
BCD·TO·SEVEN·SEGMENT DECODERS/DRIVERS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . .
Input voltage
Operating free·air temperature range: SN54LS248
SN74LS248
Storage temperature range
<
•
•
•
•
•
•
•
•
•
•
•
•
•
7V
7V
•
-55°C to 125°C
. oOe to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS24B
MIN
Supply voltage, Vee
4.5
High-level output current, IOH
Low-level output curren~. IOl
r0
<
High-level input vortage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
10
Output current
-50
-50
a thru 9
2
6
Vee = MIN,
VIH-2V,
Bi/RsO
VIL = VIL max, 10H = MAX
Vo = 0.85 V,
Input conditions as for VOH
en
a thru 9
2
Low~level
input current
Short~circuit
ICC
output current
V
-1.5
-1.5
V
4.2
V
-1.3
-2
-1.3
-2
rnA
0.25
0.4
0.25
0.25
0.4
0.35
0.5
0.4
0.25
0.4
0.35
0.5
V
Vee= MAX,
VI=2.7V
except Bl/RBO Vee=MAX,
VI = 0.4 V
BI/RBO
lOS
V
2.4
Any input
IlL
Bi/RBO
Vee = MAX,
0.1
0.1
rnA
20
20
p.A
-0.4
-0.4
-1.2
--1.2
-0.3
Vee = MAX
Supply current
UNIT
4.2
IOL=1.6rnA
VI = 7 V
except Bi IRBO
°e
0.8
10L = 3.2 rnA
Vee=MAX,
Any input
rnA
0.7
VIH=2V,
Any input
p.A
V
VIL = VIL max
input current
SN74LS24B
MIN TVP* MAX
10L =6rnA
Vee= MIN,
except Bi/RBO
V
2.4
10L = 2 rnA
VIL = VIL max
Bt/RBO
High~level
70
VIH=2V,
Low-level output voltage
Input current at
maximum input voltage
o
UNIT
,"n'''' om"";" """")
SN54LS24B
MIN TVPt MAX
a thru 9 and
3.2
1.6
125
....... ~..
11=-18rnA
Vec= MIN,
5.25
Bi/RBO
Vee= MIN,
athru 9
MAX
-100
"""...., f ....', _
Vee = MIN,
IIH
5
2
(I)
II
4.75
-100
TEST CONDITIONSt
VIH
VOL
NOM
5.5
5
-55
PARAMETER
(I)
c=r
MIN
Bi/RBO
• •,""''''''' ,h..".""",, ..., ..~m""'od
-t
-t
SN74LS24B
MAX
a thru 9
Operating free-air temperature, T A
.
NOM
See Note 2
-2
25
-0.3
38
25
rnA
-2
rnA
38
rnA
tFor con(jitions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:tAli typical values are at Vee"" 5 V, T A 25° C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.
switching characteristics, Vee
=
5 V, TA
=
25°e
PARAMETER
TEST CONDITIONS
tPHL
Propagation delay time,
tpLH
Propagation delay time, low-to-high-Ievel output from A input
tpHL
Propagation delay time,
tpLH
Propagation delay time, low-to-high-Ievel output from RBI input
high~to-Iow-Ievel
high~to-Iow-Ievel
output from A input
output from RBI input
eL = 15 pF,
See Note 3
eL = 15pF,
See Note 3
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
2-714
RL = 4 k!l.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75266
MIN
TVP
MAX
100
100
RL=6k!l,
100
100
UNIT
ns
ns
SN54251, SN54LS251, SN54S251,
SN74251, SN74LS251, (TIM9905), SN74S251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
DECEMBER 1972-REVISED MARCH 19BB
•
•
•
•
•
•
Three-State Versions of '151, 'LS151, 'S151
Three-State Outputs Interface Directly with
System Bus
Perform Parallel-to-Serial Conversion
Permit Multiplexing from N-lines to One Line
Complementary Outputs Provide True and
Inverted Data
Fully Compatible with Most TTL Circuits
TYPE
SN54251, SN54LS251, SN54S251 ..• J OR W PACKAGE
SN74251 ... N PACKAGE
SN74LS251, SN74S251 ..• 0 OR N PACKAGE
(TOP VIEW)
49
129
17 ns
17 ns
250mW
SN74251
SN54LS251
49
17 ns
35mW
SN74LS251
129
17 ns
8 ns
8 ns
35mW
SN54S251
39
SN74S251
129
D4
05
06
07
DO
y
A
B
W
G
MAX NO.
TYPICAL AVG PROP
TYPICAL
DELAY TIME
OF COMMON
POWER
OUTPUTS
(DTOY)
DISSIPATION
SN54251
Vee
03
02
01
e
GNO
SN54LS251, SN54S251 ... FK PACKAGE
250mW
(TOP VIEW)
u
275mW
Ela~~C!i
275mW
3 2
2019
05
06
description
Ne
These monolithic data selectors/multiplexers contain
full on·chip binary decoding to seJect one-of-eight
data sources and feature a strobe·controlled threestate output. The strobe must be at a low logic level
to enable these devices. The three-state outputs per·
mit a number of outputs to be connected to a com·
mon bus. When the strobe input is high, both outputs
are in a high·impedance state in which both the upper
and lower transistors of each totem-pole output are
off, and the output neither drives nor loads the bus
significantly. When the strobe is low, the outputs are
activated and operate as standard TTL totem·pole
outputs.
•
07
A
9 10111213
ICl 0
U
zz
U
ID
Cl
NC - No internal connection
FUNCTION TABLE
INPUTS
SELECT
To minimize the possibility that two outputs will
attempt to take a common bus to opposite logic
levels, the output control circuitry is designed so that
the 'average output disable time is shorter than the
average output enable time. The SN54251 and
SN74251 have output clamp diodes to attenuate
reflections on the bus line.
OUTPUTS
ENABLE
V
w
C
B
A
G
x
X
X
H
L
L
L
L
L
L
H
L
L
H
L
L
Z
DO
01
02
03
D:i
0'
05
06
07
54
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
L
H
H
H
L
Z
00
i51
02
Ds
00
D1
H = high logic level, L = low logic level
X = irrelevant, Z = high impedance (off)
DO. D1 ... 07 "" the level of the respective 0 input
PRODUCTION DATA documents ••ntain inf.rmation
8'
currant of publication data. Products confarm to
specific.tianl par the terms of Texas Instruments
=~~~::~~i~·r::1~7i ~r:~:~:; :'iU:::::~::.s not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-715
SN54251, SN54LS251, SN54S251,
SN74251, SN74LS251, (TIM9905), SN74S251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
logic diagram (positive logic)
171
ENABLE
G
DO
01
02
DATA
INPUTS
03
04
05
D6
07
14)
131
121
151
.-....--- OUTPUT V
111
JeH_ _I,-,-S,--1 OUTPUT W
1151
1141
1131
1121
A.
A
-t
-t
B
B
rO
C-
c
CD
~.
n
CD
VI
logic symbol t
MUX
G
A
B
C
DO
01
02
03
04
05
06
07
(11)
(10)
(91
(41
(3)
(2)
(1)
(151
(14)
(131
(121
EN
:)G*
0
1
2
\1
\1
(5)
(6)
V
w
3
4
5
6
7
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and lEe Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages .
2-716
. TEXAS.
INSTRUMENTS
POST. OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54251, SN74251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
5.5V
5.5V
-55°e to 125°e
O°C to 70°C
-65°e to 150°C
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
Off·state output voltage
Operating free·air temperature range: SN54251
SN74251
Storage temperature range
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54251
MIN
Supply voltage, Vee
4.5
NOM
5
SN74251
MAX
MIN
5.5
4.75
NOM
5
-2
High-level output current, 'OH
Low-level output current, tOl
16
Operating free-air temperature, T A
125
-55
0
MAX
UNIT
5.25
V
-5.2
mA
16
rnA
70
"e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
TEST CONOITIONSt
TYP*
MAX UNIT
V
2
0.8
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
10Z
Off-state (high-impedance-state) output current
Vo
MIN
Output clamp voltage
Vee-MIN,
II =-12rnA
Vee=MIN,
VIL = 0.8 V,
VIH 2V,
10H = MAX
Vee = MIN,
VIH=2V,
VIL = 0.8 V,
10L = 16mA
-1.5
2.4
V
V
3.2
0.2
V
0.4
Vee=MAX,
Vo = 2.4 V
40
VIH = 2 V
VO-0.4V
-40
Vee = MAX,
10=-12mA
VIH=4.5V
10= 12mA
-1.5
V
IJA
V
II
Input current at maximum input voltage
Vee=MAX,
VI-5.5V
Vee+1.5
1
IIH
High-level input current
Vee=MAX,
VI=2.4V
40
IJA
IlL
Low-level input current
Vee- MAX,
VI =O.4V
-1.6
mA
lOS
Short-circuit output current ~
Vee=MAX
lee
Supply current
Vee=MAX,
-18
All inputs at 4.5 V,
All outputs open
38
mA
-55
mA
62
rnA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:t: All typical values are at Vee = 5 V, T A "" 25° C.
§Not more than one output should be shorted at a time.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-717
SN54251, SN74251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
switching characteristics, Vee = 5 V, TA = 250 C
PARAMETERt
FROM
TO
!INPUT)
(OUTPUT)
tpLH
A,B,orC
tpHL
(4 levels)
tpLH
A,B,orC
tpHL
(3 levels)
tPLH
TEST CONDITIONS
Y
W
Any D
Y
tpHL
RL=400n,
tPLH
Any D
W
G
Y
G
W
tpHL
tpZH
tpZL
tpZH
tpZL
.tpHZ
oCD
~.
C')
CD
en
tpHl
tpZH
tpZl
tpHZ
tpLZ
=
w
G
tpLZ
t tPLH
See Note 2
CL = 5 pF,
RL=400n,
tpHZ
r-
Y
G
tpLZ
-I
-I
CL = 50 pF,
See Note 2
MIN
TYP
45
28
45
20
33
21
33
17
28
18
28
10
15
9
15
17
27
26
40
17
27
24
40
5
8
15
23
5
8
15
23
Propagation delay time, low-to-high-Ievel output
= Propagation delay time, high-to-Iow-Ievel output
= Output enable time to high level
= Output enable time to low level
= Output disable time from high level
= Output disable time from low level
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF BOTH OUTPUTS
vcc------~-----
------<,--1>- vee
100 n NOM
INPUT
OUTPUT
Select: Req "" 6
Other inputs: Req = 4
2-718
kn
kn
NOM
NOM
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MAX UNIT
29
ns
ns
ns
ns
ns
ns
ns
ns
SN54LS251, SN74LS251
DATA SELECTORS/MULTIPLEXERS WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
Off·state output voltage
Operating free·air temperature range: SN54LS251
SN74LS251
Storage temperature range
7V
7V
5.5V
55°C to 125°C
oOe to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS251
SN74LS251
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.7
0.8
10H
High-level output current
-1
- 2.6
mA
8
70
mA
lOL
Low-level output current
TA
Operating free-air temperature
2
4
125
- 55
V
V
2
0
V
'e
en
Q)
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH
VOL
TEST eONDITIONSt
Vee - MIN,
11--18mA
Vee - MIN,
VIH-2V,
10H" MAX
Vee MIN,
VIH"2V,
VIL" MAX
10Z
Vee" MAX,
VIH" 2 V
II
Vee- MAX,
VI-7 V
IIH
Vee
IlL
IOS§
ICC
i Enable G
I All other
SN54LS251
MAX,
Vee" MAX,
MIN
MIN
TYP* MAX
- 1.5
VIL - MAX
2.4
3.4
0.25
10L "4mA
- 1.5
3.1
2.4
0.4
0.25
0.4
0.35
0.5
20
20
VO-O.4V
-20
- 20
0.1
0.1
20
20
- 0.2
- 0.2
VI" 2.7 V
VI" 0.4
-0.4
-30
See Note 3
-130
-0.4
- 30
Q)
UNIT
C
V
...J
....
....
V
10L 8mA
YO" 2.7 V
Vee" MAX
Vee" MAX,
TYP* MAX
CJ
'S
SN74LS251
-130
Condition A
6.1
10
6.1
10
Condition B
7.1
12
7.1
12
V
",A
mA
j.lA
mA
mA
mA
t
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
t
All typical values are at
Vee
~ 5 V, T A"" 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 3: ICC is measured with the outputs open and all data and select inputs at 4.5 V under the following conditions:
A. Enable grounded.
8, Strobe at 4.5 V.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-719
•
SN54LS251, SN74LS251 (TIM9905)
DATA SELECTORS/MULTIPLEXERS WITH 3·STATE OUTPUTS
switching characteristics, Vee
=5 V, TA =25°e
PARAMETERt
FROM
(INPUT)
tPLH
A, B,orC
tpHL
(4 levels)
tpLH
A,B,orC
(310vols)
W
Any 0
Y
tpHL
tpLH
tpHL
tPLH
Any 0
TO
(OUTPUT)
TEST CONOITIONS
tpZL
tPHZ
tPLZ
tpHZ
tPLZ
G
CL
29
45
45
17
18
= 15 pF,
= 2 kll,
RL
See Note 2
W
Y
W
G
Y
CL
w
RL = 2 kll,
See Note 2
= 5 pF,
MAX UNIT
28
20
21
G
G
TYP
Y
tpHL
tPZH
tpZL
tpZH
MIN
33
33
28
28
10
15
9
15
30
26
45
40
17
27
24
40
30
45
15
37
25
15
55
25
t tpLH = Propagation delay time, low-to-high-Ievel output
tpHL = Propagation delay time, high-to-Iow-Ievel output
tpZH = Output enable time to high level
tpZL = Output enable time to low level
tpHZ =. Output disable time from high level
tPLZ = Output disable time from low level
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
schematics of inputs and outputs
EQUIVALENT OF GINPUT
EQUIVALENT OF ALL OTHER INPUTS
TYPICAL OF BOTH OUTPUTS
Vee-~P--
Vee
l00!2NOM
V e e - - -.....- -
r+........-
INPUT .....
INPUT
OUTPUT
A, B, e: Req
DO thru 07: Req
2-720
= 20 kn
= 17 kn
NOM
NOM
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75285
ns
ns
ns
ns
ns
ns
ns
ns
SN54S251, SN74S251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Off-state output voltage
Operating free-air temperature range: SN54S251
SN74S251
Storage temperature range
7V
5.5V
5.5 V
-55°C to 125°C
oOe to 70°C
_65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN74S251,
SN54S251
MIN
Supply voltage, Vee
NOM
4.5
5
High-level output current, IOH
MAX
MIN
5,5
4.75
NOM
5
-2
Low-level output current, IOl
20
Operating free-air temperature, T A
-55
125
0
MAX
UNIT
5,25
V
-6.5
rnA
20
rnA
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
'TEST CONDITIONSt
PARAMETER
VIH
High-level input voltage
VIL
VIK
Low-level input voltage
Input clamp voltage
VOH
High-level ou tpu t vol tage
VOL
Low-level output voltage
10Z
Off-state (high-impedance-state) output current
II
Input current at maximum input voltage
Vee - MAX,
IIH
High-level input current
Vee· MAX.
IlL
Low-level input current
Vee
lOS
Short-circuit output current:.:
Vee - MAX
ICC
TYPt
V
Vee" MIN,
II =-18 rnA
Vee - MIN,
VIH - 2 V.
I
SN54S'
2,4
3.4
VIL" 0,8 V,
IOH" MAX
I
SN74S'
2,4
3,2
Vee - MIN,
Vi'H - 2 V,
VIL" 0,8 V.
IOL" 20 rnA
I
I
Vee- MAX,
MAX,
Vee - MAX,
va -
0.8
V
-1.2
V
2.4 V
50
-50
1
/lA
rnA
2.7 V
50
/lA
-2
rnA
-100
rnA
85
rnA
All outputs open
55
..J
l-
V
VI-0.5V
-40
Q)
I-
VO=0,5V
All Inputs at 4.5 V,
Q)
(.)
os>
o
V
0.5
VI" 5.5V
VI
In
MAX UNIT
2
VIH" 2 V
Supply current
MIN
t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
tAli typical values are at Vce
'=
5 V. T A = 25°C.
§ Not more than one output should be .shorted at a time, and duration of the short-circuit should not exceed one second.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-721
SN54S251, SN74S251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
switching characteristics, Vee = 5 V, TA = 25° e
PARAMETERt
FROM
TO
(INPUT)
(OUTPUT)
tPLH
A, B,orC
tpHL
(4 levels)
A.
tPLH
Y
~,orC
W
(3 levels)
tPHL
tpLH
tpHL
tpLH
tpHL
tpZH
Any 0
Y
Any 0
W
13
tpZL
TEST CONOITIONS
Y
w
13
tpZL
tPHZ
13
tPLZ
Y
G
w
tPLZ
18
13
19.5
10
15
9
13.5
See Note 2
8
12
8
12
4.5
4.5
7
7
13
19.5
14
21
13
19.5
CL=50pF,
See Note 2
CL = 5 pF,
See Note 2
14
21
5.5
8.5
9
14
5.5
8.5
9
14
ttPlH = Propagation delay time, low-to-high-Ievel output
tpHL = Propagation delay time, high·to·low·level output
tpZH = Output enable time to high level
tpZL = Output enable time to low level
tpHZ = Output disable time from high level
tpLZ = Output disable time from low level
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF BOTH OUTPUTS
-----.---vcc
vcc---+---
INPUT
OUTPUT
2-722
MAX UNIT
12
RL =280n,
RL = 280 n,
tpHZ
TYP
CL=15pF,
RL=280n,
tpZH
MIN
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ns
ns
ns
ns
ns
ns
ns
ns
SN54LS253, SN54S253, SN74LS253, SN74S253
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
SEPTEMBER 1972 - REVISED MARCH 1988
SN54lS253, SN54S253 ... J OR W PACKAGE
SN74lS253. SN74S253 ... 0 OR N PACKAGE
ITOP VIEW)
• Three-State Version of SN54/74LS153,
SN54/74S153
• Schottky-Diode-Clamped Transistors
vcc
lG
B
lC3
lC2
1Cl
• Permits Multiplexing from N Lines to 1 Line
• Performs Parallel-to Serial Conversion
• Fully Compatible with Most TTL Circuits
• Low Power Dissipation
'LS253 ... 35 mW Typical
'S253 ... 225 mW Typical
2<3
A
lCD
2C3
2C2
2Cl
lY
2CD
GND
2Y
SN54lS253, SN54S253 ... FK PACKAGE
(TOP VIEW)
description
Each of these Schottky·clamped data selectors/mul·
tiplexers contains inverters and drivers to supply
fully complementary, on·chip, binary decoding data
selection to the AND·OR gates. Separate output con·
trol inputs are provided for each of the two four·line
sections.
U
1(.9 U UIC!}
CO..--2>N
i 2 1 2019
The three·state outputs can interface with and drive
data lines of bus·organized systems. With all but one
of the common outputs disabled (at a high·impedance
state) the low·impedance of the single enabled out·
put will drive the bus line to a high or low logic level.
9 10 111213
NC-No internal connection
FUNCTION TABLE
SELECT
INPUTS
A
B
OUTPUT
OUTPUT
CONTROL
DATA INPUTS
CO
C1
C2
C3
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
H
X
X
L
H
G
H
L
L
L
L
L
L
L
L
Y
z
L
H
L
H
L
H
L
H
Address Inputs A and B are common to both sections.
H
high level, L - low level. X - lrrele\lant, Z
high Impedance (off)
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note I) ............................................................. " 7 V
I nput voltage: 'LS253 ....................................................................... 7 V
'S253 ...................................................................... 5.5 V
Off· state output voltage .................................................................... 5.5 V
Operating free·air temperature range: SN54LS253, SN54S253 ............................. - 55°C to 125°C
SN74LS253, SN74S253 .................................. oOe to 70°C
Storage temperature range ......................................................... - 65°C to 150°C
NOTE1: Voltage values are with respect to network ground terminal.
PRODUCTION DATA documonts contain information
current as of publication date. Products conform to
$pacifications par the terms of TeJ.as Instruments
:~~::~~i~.{~:I~~i ~!:~:~ti:fn ~iO::;:::~r~~s
not
TEXAS
-If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-723
SN54LS253. S154S253. SN74LS253. SN74S253
DUAL4·lINE TO 1·lINE DATA SElECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
logic svmbolt
B
1(;
lCO
lV
lCl
2V
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
........
r-
logic diagram (positive logic)
OUTPUT III
CONTROL
,-a
0
CD
<
161
C;'
CD
en
1Cl
151
OUTPUT
lV
DATA 1
1C2
141
131
121
{
SELECT
-',;.;::...c:'--'M>--~
AB 1141
2CO ...;1..;.,10;;.;.1-------t-+-t:I=-r-,
2C1 1111
DATA 2
1121
2C2~-------~F=~;r~
OUTPUT (15)
CONTROL~~)------~~---~
2G
Pin numbers shown are for 0, J, N, and W packages.
2-724
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
OUTPUT
2V
SN54LS253, SN74LS253,
DUAL 4·LlNE TO HINE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
schematic (each selector/multiplexer, and the common select section)
G 11 ,15)
CO 16,10)
Cl 15,11)
C2 14, 12)
U)
Q)
(.)
'S;
Q)
o
C3 13,13)
...J
....
....
wrrr
llS)VCC
v
TO OTHER SELECTOR/MUL TIPLEXER
ISEE FUNCTIONAL BLOCK DIAGRAM)
18)
[TGND
Pin numbers shown are for 0, J, N. and W packages.
TEXAS . .
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-725
SN54LS253, SN74LS253
DUAL 4·LlNE TO HINE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
recommended operating conditions
SN74LS253
SN54LS253
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
Vee
Supply voltage
VIH
High-level inpu.t voltage
VIL
Low-level input voltage
10H
High-level output current
1
2.6
mA
10L
. TA
Low-level outp.ut current
4
8
mA
70
°e
125
55
Operating free-air temperature
V
2
2
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
•
VIK
Vee = MIN,
11=-18mA
VOH
Vee - MIN,
VIH-2V,
VOL
Vee= MIN,
VIH=2V,
10Z
Vee= MAX,
VIH = 2 V
II
Vee= MAX,
VI = 7 V
IIH
Vee- MAX,
VI=2.7V
IlL
Vee= MAX,
VI =O.4V
<
c:;.
10S§
Vee= MAX
CD
lee
-I
-I
rC
CD
CIl
SN54LS253
TEST eONDITIONSt
Vee = MAX,
MIN
2.4
10H= MAX
VIL = MAX,
3.4
0.25
10L = 4 mA
VIL = MAX
SN74LS253
TYP* MAX
-1.5
MIN
TYP* MAX
-1.5
2.4
0.4
10L = 8 mA
0.4
0.25
0.5
20
20
-20
-20
0.1
0.1
20
20
-0.2
-0.2
- 0.4
-30
See Note 2
0.25
VO=2.7V
All other
-130
V
V
3.1
VO=O.4V
G
UNIT
-0.4
-30
-130
Condition A
7
12
7
12
Condition B
8.5
14
8.5
14
V
p.A
mA
IJA
mA
mA
mA
t For conditions shown as MIN or MAX, use the appropriate value spcified under recommended operating conditions.
t
All typical values are at
Vee
= 5 V, T A'" 25°C.
§ Not more than one output should be shorted at a time, and duration for the short-circuit should exceed one second.
NOTE 2: ICC is measured with the outputs open under the following conditions:
A. All inputs grounded.
B. Output control at 4.5 V, all inputs grounded.
switching characteristics, Vee = 5 V, T A = 25° C
PARAMETER
tPLH
tpHL
tpLH
FROM
TO
(INPUT)
(OUTPUT)
Data
Y
Select
y
tpHL
tpZH
Output
tpZL
Control
tpHZ
Output
tpLZ
Control
TEST CONDITIONS
eL=15pF,
RL=2kn,
See Note 3
Y
Y
eL=5pF,
RL-2kn,
See Note 3
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-726
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
TYP
MAX UNIT
17
25
13
20
30
45
21
32
15
15
28
23
27
41
18
27
ns
ns
ns
ns
SN54S253, SN74S253
DUAL 4·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
recommended operating conditions
SN54S253
SN74S253
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
VCC
Supply voltage
VIH
High·level input voltage
VIL
LowMlevel input voltage
0.8
0.8
IOH
HighMlevel output current
-2
-6.5
mA
IOL
Low·level output current
Operating free-air temperature
20
mA
70
°c
TA
2
V
20
-55
V
2
125
0
V
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
VIK
MIN
TEST CONDITIONSt
Vcc = MIN,
TYP*
UNIT
MAX
-1.2
11=-18mA
I
Series 545
2.5
3.4
I Series 745
2.7
3.4
V
V
VOH
Vcc= MIN,
VIH=2V,
VIL=0.8V,
IOH= MAX
VOL
Vcc= MIN,
VIH = 2 V,
VIL = 0.8 V,
IOL = 20 mA
IOZ
VCC= MAX,
VIH = 2 V
II
VCC= MAX,
VI=5.5V
1
mA
IIH
Vee
2.7 V
50
I'A
MAX,
IlL
Vec= MAX,
IOS§
VCC= MAX
VI
0.5
I VO-2.4V
I Vo 0.5 V
I
I
VI = 0.5 V
I
I
V
50
I'A
50
G = 0.8 V,
-2
mA
G=2V
-0.25
-40
Condition A
-100
45
mA
70
ICC
See Note 2
VCC= MAX,
Condition B
65
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
•
mA
85
:t: All typical values are at Vee"" 5 V. T A = 25° C.
Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second.
NOTE 2: ICC is measured with the outputs open under the following conditions:
A. All inputs grounded.
B. Output control at 4.5 V, all inputs grounded.
switching characteristics, Vee
PARAMETER
tPLH
tpHL
tPLH
tpHL
=5 V, TA = 25°e
FROM
TO
(INPUT)
(OUTPUT)
Data
y
Select
y
TEST CONDITIONS
RL = 280 11.,
CL = 15 pF
See Note 3
tpZH
Output
tpZL
Control
tPHZ
Output
tpLZ
Control
Y
y
RL - 280 11.,
CL - 5 pF
See Note 3
. MIN
TYP
MAX
6
6
9
9
11.5
18
12
18
11
16.5
12
18
6.5
9.5
10
15
UNIT
ns
ns
ns
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-727
2-728
SN54LS257B. SN54LS258B. SN54S257. SN54S258.
SN74LS257B. SN74LS258B. SN74S257. SN74S258
QUADRUPLE 2·UNE TO '·UNE DATA SELECTORS/MULTIPLEXERS
OCTOBER 1976 - REVISED MARCH 19BB
SN54LS257B, SN54S257,
SN54LS258B, SN54S258 ... J OR W PACKAGE
SN74LS257B.SN74S257,
SN74LS258B. SN74S258 ... D OR N PACKAGE
(TOP VIEW)
• Three·State Outputs Interface Directly
with System Bus
• 'LS2S7B and 'LS258B Offer Three
Times the Sink·Current Capability
of the Original 'LS2S7 and 'LS258
1B
2A
2B
2Y
GND
• Provides Bus Interface from Multiple
Sources in High·Performance Systems
AVERAGE PROPAGATION
TYPICAL
OELAY FROM
DATA INPUT
POWER
DISSIPATIONt
'L5257B
'L5258B
'5257
'5258
t Off
9
9
4.8
4
~ee
G
4A
4B
4Y
3A
3B
3Y
AlB
• Same Pin Assignments as SN54LS157,
SN74LS157, SN54S157, SN74S157, and
SN54LS158, SN74LS158, SN54S158,
SN74S158
ns
55 mW
ns
55 mW
ns
ns
320 mW
280 mW
SN54LS257B, SN54S257,
SN54LS258B, SN54S258 •.. FK PACKAGE
(TOP VIEW)
II)
CI)
(J
state (worst case)
'S
4
5
6
description
These devices are designed to multiplex signals from
four-bit data sources to four-output data lines in busorganized systems. The 3-state outputs ",:!II not load the
data lines when the output control pin (GI is at a highlogic level.
CI)
C
7
8
14
9 10 111213
...J
....
....
>-OU>-al
"'22<')<')
(!l
Series 54LS and 54S are characterized for operation
over the full military temperature range of - 55 D to
125 D e; Series 74L5 and 745 are characterized for
e.
operation from oDe to 70 D
e
NC-No internal connection.
FUNCTION TABLE
INPUTS
OUTPUT
OUTPUTY
'LS257B
'LS258B
'S257
'S258
SELECT
A
B
H
X
X
X
Z
Z
L
L
L
X
L
H
L
L
H
X
H
L
L
H
X
L
L
H
L
H
X
H
H
L
CONTROL
H - high level, L - low level, X = Irrelevant,
Z = high impedance (off)
PRODUCTION DATA documanls conlain informalion
current as of publication date. Preducts cDnform to
specifications per the terms of Texas Instrumants
:~~~~:~~i~ai~:I~li ~!:~~~i:r :llo:::::9t::s~s not
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-729
SN54LS257B, SN54LS258B, SN54S257, SN54S258,
SN74LS257B, SN74LS258B, SN74S257, SN74S258
QUADRUPLE 2·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS
logic diagrams (positive logic)
'LS257B, 'S257
'LS258B, 'S258
G
1A
1A
16
16
2A
2A
26
28
3A
3A
36
38
4A
4A
-4
-4
48
48
C
AlB
A/8
~~
__________
1Y
3Y
r-
CD
<
c:;.
logic symbols t
'LS257B
CD
en
G
AlB
lA
lB
2A
2B
3A
3B
4A
4B
AlB
(4)
lA
lB
2A
2B
3A
3B
4A
4B
1V
2Y
(9)
3Y
(12) 4Y
lA
lB
2A
2B
3A
3B
(14)
4A
(13)
4B
(2)
(3)
(5)
(6)
111)
(10)
(14)
(13)
G
G
AlB
AlB
lA
lB
2A
2B
3A
3B
4A
4B
lY
2Y
3Y
(12)
4Y
(5)
(6)
111)
(10)
(14)
(13)
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
2-730
~
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54LS257B. SN54LS258B. SN54S257. SN54S258.
SN74LS257B. SN74LS258B. SN74S257. SN74S258
QUADRUPLE 2·LlNE TO '·LlNE DATA SELECTORS/MULTIPLEXERS
schematics of inputs and outputs
'LS257B, 'LS258B
EQUIVALENT OF
AlB INPUT
EQUIVALENT OF ALL
OTHER INPUTS
TYPICAL OF ALL OUTPUTS
--------+- VCC
Vcc------~------
100n NOM
v c c - - -.....- - 18 kn
NOM
INPUT
;l4-
INPUT ..... e _ _- -
OUTPUT
CI)
Q)
(.)
·S
'8257, '5258
EQUIVALENT OF EACH INPUT
Q)
TYPICAL OF ALL OUTPUTS
o
.-.-
- - - - - - - -......-Vcc
..J
son NOM
Vcc - - - - _ - - -
INPUT
OUTPUT
Select: Req
All other inputs: Req
= 1.4 kn NOM
= 2,8 kn NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ,'" , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , " 7 V
Input voltage: 'LS257B, 'LS25BB Circuits" , " " , " , , , , , , , " , , , " , , " , " ' , , , , , , , ' , , , , , , " " , , , , " 7 V
'S257, 'S25B Circuits, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , " 5,5 V
Off-state output voltage, , , , .. , , , , , , , , , , , , , , , , , _, , , , , , , , , , , , , , , , , , , , , , , , , , , _ , , , , , , , , _, , , , , , , " 5,5 V
Operating free-air temperature range: SN54LS', SN54S' Circuits, , , , , , , , , , , , , , , , _ , , , , _ , , , , , , , _55°C to 125°C
SN74LS', SN74S' Circuits, , , , , , , , , , , , , , , , , , , , , , , , , , _, , , " OoC to 70°C
Storage temperature range, , , , , , , , , , , , , , , , , , _, , , , , , , , , , , , , , , , , , , , , , _ , , _ , _ , , , , , , , , , , _, _65°C to 150°C
NOTE1: Voltage values are with respect to network ground terminal.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-731
SN54LS2578, SN54LS2588, SN74LS2578, SN74LS2588
QUADRUPLE 2·UNE TO 1·UNE DATA SELECTORS/MULTIPLEXERS
recommended operating conditions \
SN64LS'
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
SN74LS'
MIN
NOM
MAX
MIN
NOM
4.5
5
5.5
4.75
5
MAX
UNIT
5.25
V
0.7
0.8
V
2
V
2
IOH
High-level output current
-1
-2.6
mA
IOL
Low-level output current
12
24
mA
TA
Operating free-air temperature
70
°e
-55
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH
r-
C
CD
11=-18mA
Vee = MIN,
VIH = 2V,
VIL =MAX,
VIH-2V,
IIOL-12mA
VIH =2V,
IIOL = 24 mA
VO=2.7V
VO-0.4V
VIL = MAX,
SN74LS'
MAX
TYP*
MIN
MAX
TYP*
-1.5
2.4
3.4
-1.5
2.4
0.25
0.4
UNIT
V
V
3.1
0.25
0.4
0.35
0.5
V
IOZH
Vee- MAX,
IOZL
Vee-MAX,
VIH -2V,
II
Vee = MAX,
VI-7V
IIH
Vec =MAX,
VI-2.7V
20
20
J,lA
IlL
Vec=MAX,
VI-0.4V
-0.4
-0.4
mA
-130
mA
-30
VCC- MAX,
IOS§
8
All outputs low
All outputs off
ICC
All outputs high
'LS257B
VCC =MAX,
See Note 2
All outputs low
20
20
-20
-20
J,lA
0.1
0.1
mA
-130
All outputs high
<
(I)
Vee = MIN,
Vee=MIN,
(i'
CD
MIN
IOH =MAX
VOL
-I
-I
SN64LS'
TEST eONDITIONst
'LS258B
All outputs off
-30
12
8
12
12
18
12
18
13
19
13
19
6
9
6
9
10
15
10
15
11
16
11
16
J,lA
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t.AII typical values are at Vee"" 5 V. T A = 25°C.
§Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with all outputs open and all possible inputs grounded while achieving the stated output conditions.
switching characteristics, Vee
PARAMETER'
tpLH
tpHL
tpLH
tpHL
2-732
TO
(INPUT)
(OUTPUT)
Data
Select
tpZH
Output
tpZL
Control
tpHZ
Output
tpLZ
Control
'tPLH ~
tpHL ~
tpZH ~
NOTE 3:
= 5 V, TA = 25°e, RL = 66711
FROM
'LS257B
TEST CONDITIONS
MIN
Any
Any
CL =45 pF,
See Note 3
Any
Any
eL = 5 pF,
See Note 3
propagation delay time, low-to-high-Ievel output
propagation delay time, high-to-Iow-Ievel output
output enable time to high level
Load circuits and voltage waveforms are shown in Section 1.
'LS258B
TYP
MAX
MIN
TYP
MAX
12
8
13
7
10
15
11
17
16
21
14
21
17
24
19
24
15
30
15
30
19
30
20
30
18
30
18
30
16
25
16
25
tpZL = output enable time to low level
tpHZ ~ output disable time from high level
tPLZ = output disable time from low level
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
SN54S257, SN54S258, SN74S257, SN74S258
QUADRUPLE 2·LlNE TO HINE DATA SELECTORS/MULTIPLEXERS
recommended operating conditions
SN54S'
MIN
Supply voltage, Vee
SN74S'
NOM
MAX
MIN
NOM
5
5.5
4.75
5
4.5
High-level output current, IOH
Low-level output current, IOl
-2
MAX
5.25
V
-6.5
mA
20
mA
70
°e
20
Operating free-air temperature, T A
-55
125
UNIT
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIH
High-level input voltage
VIL
Low-level input voltage
Input clamp voltage
VIK
VOH
VOL
10ZH
10ZL
High-level output voltage
Low-level output voltage
IlL
lOS
Vee=MIN,
VIH=2V,
Any other
input current Any other
Short-circuit output current§
2.7
0.8
V
-1.2
-1.2
V
2.7
SN54S'
2.4
3.4
2.4
3.4
SN74S'
2.4
3.2
2.4
3.2
Vee= MIN,
VIH - 2V,
VIL = 0.8 V,
10L = 20 mA
'=-
V
0.5
0.5
V
50
50
",A
-50
-50
",A
1
1
mA
100
100
CD
Vee=MAX, VI = 5.5V
Vee = MAX, VI=2.7V
VI=0.5V
50
50
-4
-4
-100
44
Vee = MAX, See Note 2
All outputs off
-40
68
56
60
93
52
81
64
99
56
87
CD
0
",A
..oJ
tt-
mA
mA
-100
36
(.)
"S;
-2
-2
-40
Vee = MAX
outputs high
Supply currentl All outputs low
V
0.8
10H= MAX
Vee = MAX
UNIT
MAX
2
VIL = 0.8 V,
VO=0.5V
S input
SN74S'
TVPt
10H=-1 mA
low-level voltage applied
low-level
MIN
VIH-2V,
Vee=MAX, VIH=2V,
input current
MAX
Vee= MIN,
Of1-state output current.
5 input
'S258
TYpt
VIL =0.8 V,
Vo = 2.4 V
I All
ICC
11= -18mA
Vee- MAX, VIH-2V,
High-level
IIH
Vee = MIN,
Off"'5tate output cu rrent,
input voltage
MIN
2
high-level voltage applied
Input current at maximum
II
'S257
TEST eONDITIONSt
PARAMETER
mA
tFor conditions shown liS MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with all outputs open and all possible inputs grounded while achieving the stated output conditions.
switching characteristics, Vee = 5 V, TA = 25°e, RL = 280 n
PARAMETER.
tPLH
tpHL
tpLH
tpHL
FROM
TO
TEST
ClNPUT)
(OUTPUT)
CONDITIONS
Data
Select
tpZH
Output
tpZL
Control
tpHZ
Output
tPLZ
Control
'S257
MIN
MAX
5
7.5
4
6
4.5
6.5
4
6
eL = 15pF,
8.5
15
8
12
See Note 3
8.5
15
7.5
12
13
19.5
13
19.5
14
21
14
21
CL=5pF,
5.5
8.5
5.5
8.5
See Note 3
9
14
9
14
Any
Any
Any
Any
'S258
TVP
MIN
TVP
MAX
UNIT
ns
ns
ns
ns
=
,fmax - Maximum clock frequency
tpLH ;: propagation delay time, low-to-high-Ievel output
tPHL = propagation delay time, high-to-Iow-Ievel output
tpZH "" output enable time to high level
tpz L output enable time to low level
tpHZ = output disable time from hIgh level
tPLZ:::;;; output disable time from low level
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-733
-4
-4
r
C
CD
<
n'
CD
(I)
2-734
SN54259, SN54LS259B, SN74259, SN74LS259B
8-BIT ADDRESSABLE LATCHES
DECEMBER 1983 - REVISED MARCH 1988
• 8-Bit Parallel-Out Storage Register Performs
Serial-to-Parallel Conversion with Storage
SN54259. SN54LS259B ... J OR W PACKAGE
SN74259 ... N PACKAGE
SN74LS259B ... 0 OR N PACKAGE
• Asynchronous Parallel Clear
(TOPVIEWI
• Active High Decoder
SO
S1
S2
00
01
• Enable/Disable Input Simplified Expansion
• Expandable for N-Bit Applications
• Four District Functional Modes
• Package Options Include Ceramic Chip
Carriers and Flat Packages in Addition to
Plastic and Ceramic DIPs
VCC
CLR
G
0
07
Q2
Q6
OJ
05
04
GND
SN54LS259B ... FK PACKAGE
ITOP VIEW)
• Dependable Texas Instruments Quality and
Reliability
~
0
~15
u
(/)(/)Z>u
description
These 8-bit addressable latches are designed for general
purpose storage applications in digital systems. Specific
uses include working registers, serial-holding registers,
and active-high decoders or demultiplexers. They are
multifunctional devices capable of storing single-line
data in eight addressable latches, and being a 1-of-8
decoder or demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs as
enumerated in the function table. In the addressablelatch mode, data at the data-in terminal is written into
the addressed latch. The addressed latch will follow the
data input with all unaddressed latches remaining in
their previous states. In the memory mode, all latches
remain in their previous states and are unaffected by the
data or address inputs. To eliminate the po~blity of
entering erroneous data in the latches, enable G should
be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the
addressed output will follow the level of the 0 input with
all other outputs low. In the clear mode, all outputs are
low and unaffected by the address and data inputs.
en
CI)
(,)
'>
CI)
C
..oJ
lI-
NC - No internal connection
logic symbol t
O}SM..!!.
2
7
GS
9.00
10.0R
141
9,10
151 01
00
10.1R
02
The SN54259 and SN54LS259B are characterized for
operation over the full military temperature range of
-55°C to 125°C. The SN74259 and SN74LS259B are
characterized for operation from OoC to 70°C.
9,30
10~R
9.40
10.4R
9,50
10,5R
9,60
10:iiR
9,70
10.7R
03
04
1101 05
11 06
1121 07
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and lEe
Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
PRODUCTION DATA d•••mlnts c••,ai. i.'.rmati••
cu,,"n, IS ., pubUcati•• datI. Pradu.....nform to
specifications p. the 'e'lil .f Tal•• Instruments
:'~=::i;li~:I~" ~r:~::i:; l!~O:::;;£~' not
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-735
SN54259, SN54LS259B, S174259, SN74LS259B
8·BIT ADDRESSABLE LATCHES
LATCH SELECTION TABLE
FUNCTION TABLE
INPUTS
OUTPUT OF
EACH
ADDRESSED
OTHER
LATCH
SELECT INPUTS
FUNCTION
S2
SI
SO
ADDRESSED
'etlf
G
L
L
L
H
L
0
aiO
Addressable Latch
L
L
H
H
H
aiO
L
H
L
L
0
aiO
L
Memory
L
a-Line Demultiplexer
L
H
H
L
H
L
L
Clear
H
L
L
H
L
H
H
H
L
0
1
2
3
4
5
6
H
H
H
7
LATCH
OUTPUT
H =: high level, L :::: low level
0== the level at the data input
QiO
==
the level of OJ (j
= 0,
1, ••• 7. as appropriate) before the indi-
cated steady-state input conditions were established.
schematic of inputs and outputs
'259
'259
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
---------Vee--~--
Vce
lOon
NOM
INPUT
-t
-t
r-
L-_+_ OUTPUT
C
CD
<
(5'
13: Req = 2.2 kn NOM
All other inputs: Req = 4 kn NOM
CD
en
'LS259B
'LS259B
• LS259B
EQUIVALENT OF lrlNPUT
EQUIVALENT OF ALL OTHER INPUTS
TYPICAL OF ALL OUTPUTS
Vce---'-
INPUT
----------
Vee--
VOL
Low~evel
output voltage
II
Input current at maximum input voltage
PARAMETER
TEST CONDITIONSt
G
High-le""l input
IIH
Other inputs
currant
Low-laval input
lOS
G
Other inputs
Short-circuit output current§
ICC
Supply current
IlL
current
Vee = MIN,
11= 12mA
Vee = MIN,
VIH=2V,
VIL = 0.8 V,
10H= -800/LA
Vee=MIN,
VIH-2V,
VIL = 0.8 V,
IOL=16mA
Vee = MAX,
VI = 5.5 V
Vee = MAX,
VI = 2.4 V
Vee = MAX,
VI =0.4 V
0.2
V
3.4
0.4
0.2
0.4
1
1
80
80
40
40
~.2
-3.2
-1.6
-1.6
See Note 2
-57
60
-18
V
mA
CI)
CJ
Q)
o
...I
lI-
/LA
mA
-57
mA
90
mA
60
90
UNIT
V
2
2.4
3.4
-18
Vee= MAX
Vee = MAX,
2.4
MIN TYP* MAX
t For conditions shown as MIN or MAX, usa the appropriate value specified under recommended operating conditions,
:t: All typical values are at Vee =
5
V. T A = 25° c,
§ Not more than one output should be shorted at a time,
NOTE 2: ICC is measured with the inputs grounded and the outputs open.
switching characteristics, Vee
PARAMETER
tpHL
tpLH
tPHL
tPLH
tpHL
tPLH
tPHL
= 5 V, TA = 25°e
FROM
TO
(INPUT)
(OUTPUT)
CLR
Any Q
Data
Address
G
TYP
MAX
UNIT
16
25
ns
14
24
eL = 15 pF,
11
20
RL = 400n,
15
28
See Note 3
17
28
12
20
11
20
TEST CONDITIONS
Any Q
Any Q
Any Q
MIN
ns
ns
ns
tPLH = propagation delay time, low-to-high-Ievel output
tPHL = propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuits and voltage waveforms are shown in . Section 1.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-737
SN54LS259B, SN74LS259B
8-BIT ADDRESSABLE LATCHES
recommended operating conditions
SN74LS259B
SN54LS259B
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.7
0.8
V
10H
High-level output current
0.4
0.4
rnA
10
Low-level output current
4
8
rnA
Pulse dUration
tw
Set up time
tsu
Held time
th
17
Glow
17
CLR low
10
10
Data before G t
20
20
Address before G t
17
17
Address before G+
Data after Gt
0
0
0
0
Address after G t
0
0
-55
Operating free-air temperature
TA
V
2
2
125
ns
ns
ns
70
0
°c
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
-t
-t
r-
PARAMETER
C
VOH
VIK
CD
<
nCD
VOL
UI
VCC= MIN,
11=-18rnA
VCC= MIN,
VIH=2V,
MIN
SN74LS259B
MIN
TYP
-1.5
VIL = MAX,
2.5
10H = -0.4 rnA
VCC= MIN,
VIH - 2 V,
3.4
0.25
IIOL-4rnA
VIL = MAX
MAX
-1.5
2.7
0.4
tlOL = 8 rnA
3.4
UNIT
V
V
0.25
0.4
0.35
0.5
V
II
VCC- MAX,
VI-7 V
0.1
0.1
rnA
IIH
VCC= MAX,
VI = 2.7 V
20
20
IlL
VCC= MAX,
VI - 0.4 V
-0.4
-0.4
IJA
rnA
IOS§
VCC= MAX
-100
rnA
ICC
VCC= MAX,
36
rnA
t For conditions shown
:t All
SN54LS259B
TYP
MAX
TEST CONDITIONSt
- 20
See Note 2
-100
27
-20
36
22
as MIN or MAX, use the appropriate value specified under recommended operating conditions
typical values are at Vee"'" 5 v, T A
=:
25° C.
§ Not more than one output should be shorted at a time, and duration short-circuit should not exceed one second.
NOTE 2:
ICC is measured with the inputs grounded and the outputs open.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
tPHL
tPLH
tpHL
tPLH
FROM
(INPUT)
TO
(OUTPUT)
CLR
Any 0
Data
Any 0
CL = 15pF,
Address
Any 0
tpHL
tpLH
tpHL
TEST CONDITIONS
G
RL = 2 kn,
See Note 3
Any 0
tpLH = propagation delay time, lowwto-highwlevel output
tpHL = propagation delay time, highwto-Iow-Ievel output
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-738
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
TYP
MAX
12
18
19
30
13
20
17
27
14
20
15
24
15
24
UNIT
ns
ns
ns
ns
SN54S260, SN74S260
DUAL 5·INPUT POSITIVE·NOR GATES
DECEMBER 1983 - REVISED MARCH 1988
SN548260 •.. J OR W PACKAGE
SN74S260 ... 0 OR N PACKAGE
• Package Options Include Ceramic Chip
Carriers and Flat Packages in Addition to
Plastic and Ceramic DIPs
(TOP VIEW)
1A
1B
1C
2A
lY
2Y
GNO
• Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent 5-input positive
-NOR gates. They perform the Boolean function
Y = A+ B+ C+ 0+ E in positive logic.
The SN54S260 is characterized for operation over the
full military temperature range of -55°C to 125°C. The
SN74S260 is characterized for operation from O°C to
70°C.
VCC
1E
10
2E
20
2C
2B
SN54S260 ••. FK PACKAGE
ITOP VIEW)
(J
IIJ
~ ~ ~~
logic diagram (each gate)
en
Q)
CJ
.S;
Q)
C
..oJ
logic symbol t
lA
18
lC
10
lE
2A
III
NC - No internal connection
;;>1
lI-
(2)
(3)
lY
(12)
(13)
(4)
(8)
28
2C
20
2E
(9)
(10)
(11)
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC
Publication 617~12.
Pin numbers shown are for D, J, N, and W packages.
PRODUCTION DATA do.uments .ontein Information
currant I I of publication data. Products conform to
specifications par the terms Texas Instruments
:'~=~~~·i~:I~1Ji
0'
=::i:r :.~u:.e:::~:.s not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-739
SN54S260. SN14S260
DUAL 5·INPUT POSITIVE~NOR GATES
schematic (each gate)
r---f-----.~------------._--vcc
2.8 kll
0.6 kll
50 II
INPUTS
A --"'---'
OUTPUT
r-
Y
I
I
I
2.8 kH
I
I
I
I
B -'--+--4~
I
-I
-I
I
L_
r-
C
CD
L--4~--------------~f---------~----~--
<
n'
CD
en
GND
Resistor values shown are nominal.
The portion of the schematic within the dashed-line is repeated for each additional input.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage .................. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range: SN54' ........................................... - 55°C to 125°C
SN74' ............................................... O°C to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
2·740
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54S260, SN74S260
DUAL 5·INPUT POSITIVE·NOR GATES
recommended operating conditions
SN74S260
SN54S260
MIN
TYP
MAX
MIN
TYP
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
V
Vec
Supply voltage
VIH
High~level
VIL
LOW-level input voltage
0.8
0.8
V
IOH
High-level output current
-1
-1
rnA
20
rnA
70
°c
input voltage
IOL
Low-level output current
TA
Operating free-air temperature
V
2
2
20
125
-55
0
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
SN74S260
SN54S260
TEST COND ITiONS t
PARAMETER
MIN
TYP*
MAX
MIN
TYP'
-1.2
VIK
Vcc = MIN,
11=-18rnA
VOH
VCC - MIN,
VIL-O.8V,
IOH - -1 rnA
VOL
VCC = MIN,
VIH =2V,
IOL = 20 rnA
II
VCC =MAX,
VI-5.5V
2.5
2.7
3.4
MAX
-1.2
3.4
UNIT
V
V
0.5
0.5
1
1
V
rnA
IIH
VCC -MAX,
VIH - 2.7 V
50
50
;m
C
MULTIPLIER
M2
M1
MO
Q4
03
02
01
00
L
X
X
X
H
L
L
L
040 Q30 Q20 Q10 QOo
L
H
L
L
L
H
L
L
H
B4
B4
L
H
L
B4
B2
B2
H
L
H
H
B4
B4
B3
B3
B1
H
B3
B2
B1
80 113)
H
H
L
L
B4
B3
B2
B1
BO
BO
81
(14)
H
H
L
H
B4
B2
B1
(151
H
H
H
L
B4
B4
B4
B3
82
B3
B2
181
B3
(1)
H
H
H
H
H
L
L
L
L
84
(2)
logic symbol t
(101 00
MO
(11)
Ml
(12)
i91 01
(7) Q2
H = high level, L = low level, X = irrelevant
0.40 ... 000 = The logic level of the same output before the
high-to-Iow transition of C.
84 ... BO = The logic level of the indicated multiplicand (B) input.
(6) 03
M2
(5) 04
141
B1
131
* Partial·Product Generator
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and lEG
Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
PRODUCTION DATA documants contain inlormation
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~:~~i~a[::I~~~ ~r:~:~ti:r ~~O:=::~:is~ not
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-743
SN54LS261, SN74LS261
2·B11 BY 4·B11 PARALLEL BINARY MULTIPLIERS
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF QO, Q1, 02, Q3 OUTPUTS
---_+_-vcc
vcc--+--
TYPICAL OF
vcc:-_-
04 OUTPUT
---~-vcc
17 kG NOM
I NPUT...,jIl--
~
I
tPLH(W)-tPHL(Y)
Q)
-------
-
-0.5 -tPHL(W) tPLH(Y)
-1
'"'"c.
c. -3
e'"
.
c:
Q)
Cl
C>
0-
1.5
Q)
2
E
Cl
c
I
3 f- CL = 15 pF
Q)
>
c:
~ -1.5
-4
-5
fIl
CI)
(.)
-2
-75 -50 -25
0
25
50
75
100
125
4.75
4.5
T A -Free-Air Temperature-°c
5
5.25
5.5
CI)
C
VCC-SuppIV Voltage--V
...J
FIGURE 2
FIGURE 1
'S;
lIPROPAGATION DELAY TIME DIFFERENCE vs LOAD CAPACITANCE
2
2
~
c:
VCC = 5 V
1.5 TA = 25°C
1lc:
-...........
e
Q)
:::
~
0.5
E
~
0
~
c:
I
--
1lc
e
~4k.n
~
is
Q)
-.......
~-0.5
i=
--I-
I'
~ -1
o
1-
~~00t1
0-
C
3 --0.5
r.s
,/"
.....
0-
-1
:J
...---
RL
:t: -1.5
3-1.5
~
~
-2
15
~~~
0.5
E
.............
):
VCC= 5 V
1.5 TA = 25°C
20
25
30
35
40
45
50
--2
15
20
25
4kn
I
I
30
35
40
CL -Load Capacitance-pF
CL -Load Capacitance-pF
FIGURE 3
FIGURE4
45
50
t Data for temperatures below aOc and above 70°C and for supplv voltages below 4.75 V and above 5.25 V are applicable for SN54265 only.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-753
SN54265, SN74265
QUADRUPLE COMPLEMENTARY·OUTPUT ELEMENTS
TYPICAL APPLICATION DATA
r----------------cLocK
CLOCK
1/4 SN74265
CLOCK
CLOCK
-G-E-N-E-RA-T-O-R--Ivt)------ CLOcR
N
~----------CLOCK
FIGURE A - TYPICAL CLOCK/CLOCK GENERATOR CIRCUIT
FIGURE B - SKEWLESS CLOCK/CiJ5CR GENERATOR C1RCUIT
~
~
rC
0
CD
INPUT A
<
n'
CD
2
C/I
3
2
3
INPUT 8
r--INPUT
INPUT A , - ' -
-
f.--INPUT
-
-
-
-- - - - :
INPUT 8 , - - - - - - - - - - :
INPUT7""l-- -
INPUT~-
-
INPUT{ A
2
I _! _______
":8-----..;1 - - - I
L
_H
OUTPUT 2
'Ll________
FIGURE C - TYPICAL DECODER/CODE CONVERTER
2·754
--:
!---SYMMETRICAL DECODE H
I __
AT { - - - - I
INPU
GATE
2
-----L
___ ---H
8
L -_______________ L
L
. - DECODER SPIKE
------:
--- -- -
--I,.._+I__D_E_C_O_DE_R_SK_E_W_ _ H
U~
-
r
H
______~
__________________
H
NO DECODE SPIKE
L
OUTPUT 2_ _ _ _ _ _ _ _ _ _ _ _ L
FIGURE D - SYMMETRICAL DECODER/CODE CONVERTER
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54265, SN74265
QUADRUPLE COMPLEMENTARY·OUTPUT ELEMENTS
TYPICAL APPLICATION DATA
390
n
1/4 SN74265
,J--4---W
l>------Y
5V
=:--I n n
.....- - - V O H
U U 1___.... _ - - - VOL
W OUTPUT
n n I
_/UU
----VOH
YOUTPUT
WOUTPUT
\
,..----·VOH
- - - - VOL
----VOH
'-----VOL
L....---VOL
WITH FEEDBACK TO
STABILIZE INPUT
WITHOUT FEEDBACK
FIGURE E - SWITCH DEBOUNCER
en
Q)
CJ
YOUTPUT
'>
Q)
C
...J
lI-
Noise immunity typically 3 V
for either high level or low level data
FIGURE F - DIFFERENTIAL LINE DRIVER
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-755
2-756
SN54LS266, SN74LS266
QUADRUPLE 2·INPUT EXCLUSIVE·NOR GATES
WITH OPEN·COLLECTORS OUTPUTS
DECEMBER 1972 - REVISED MARCH 1988
SN54LS266 ... J OR W PACKAGE
SN74LS266 ... 0 OR N PACKAGE
• Can Be Used as a 4-Bit Digital Comparator
• Input Clamping Diodes Simplify System
Design
ITOP VIEW)
FUNCTION TABLE
,INPUTS OUTPUT
A
B
Y
L
L
H
L
H
L
H
L
L
H
H
H
H = high level, L
=
Vee
1A
1B
1Y
2Y
2A
2B
GND
• Fully Compatible with Most TTL Circuits
4B
4A
4Y
3Y
3B
SN54LS266 ... FK PACKAGE
(TOP VIEW)
low level
U
~ ~ ~ ~~
description
3
2
1 2D 19
The 'LS266 is comprised of four independent 2-input
exclusive-NOR gates with open-collector outputs. The
open-collector outputs permit tying outputs together for
multiple-bit comparisons.
logic symbol (each gate)
9 10 111213
CIICU
ffi B ; AB + AB
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and lEe
••
I
Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
I
TYPICAL OF ALL OUTPUTS
--~'"
__
PRODUCTION DATA doc.manls contain information
currant as at publicatioo data. Products conform to
spacifications per the terms of TaxIs Instruments
:==i;.i~:1~7i ~:~::i:; :.~O::~::~:~~ not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
OUTPUT
2-757
SN54LS266, SN74LS266
QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES
WITH OPEN-COLLECTOR OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Operating free-air temperature range: SN54LS266
SNl4LS266
Storage temperature range
NOTE 1:
lV
lV
-55°C to 125°C
oOe to looe
-65°C to 150°C
Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS266
MIN
4.5
Supply voltage, Vee
NOM
SN74 LS266
MAX
MIN
5.5
4.75
5
High-level output voltage, VOH
-55
5
MAX
5.25
UNIT
V
5.5
5.5
4
8
rnA
70
"e
low-level output current, tOl
Operating free-air temperature. T A
NOM
125
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
IOH
High-level output current
VOL
Low-level output voltage
SN54LS266
TEST CONDITIONSt
PARAMETER
MIN
Tvp:l:
MAX
11- -18mA
Vee - MIN,
VIH-2V,
V
2
2
VCC'- MIN,
SN74LS266
UNIT
TVpj: MAX
MIN
0.7
0.8
V
-1.5
1.5
V
100
100
~A
VIL" VIL max, VOH" 5.5 V
Vee- MIN,
VIH=2V,
\IOL"4 rnA
0.25
0.4
0.25
0.4
0.35
0.5
V
VIL"VILmax IIOL"8mA
II
Input current at maximum input voltage
VCe" MAX,
VI
0.2
0.2
IIH
High-level input current
Vce - MAX,
VI" 2.7 V
40
40
IlL
Low-level Input current
Vee
0.4 V
-0.8
Ice
Supply current
Vee" MAX,
MAX,
7V
VI
See Note 2
8
13
8
-0.8
13
rnA
~A
rnA
rnA
I For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
tAil typical values are at Vee S v, T A 25 e.
NOTE 2: ICC is measured wIth one Input of each gate at 4.5 V, the other inputs grounded, and the outputs open.
switching characteristics, Vee = 5 V, TA = 25"e
PARAMETER§
tpLH
FROM
TEST CONDITIONS
IINPUT)
A or B
Other input low
tpHL
tpLH
RL" 2 kn,
A or B
Other input high
tpHL
§tPlH = propagation delay time, low-to-high-level output
tPHl = propagation delay time, high-to-Iow-Ievel output
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
2-758
eL=15pF,
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
See Note 3
MIN
TVP
18
MAX UNIT
30
18
30
18
30
18
30
ns
ns
SN54273. SN54LS273. SN74273. SN74LS273
OCTAL O·TYPE FLlp·FLOP WITH CLEAR
OCTOBER 1976 - REVISED MARCH 19B8
•
SN54273, SN74lS273 ... J OR W PACKAGE
Contains Eight Flip-Flops with
Single-Rail Outputs
SN74273 ... N PACKAGE
SN74lS273 ...
•
Buffered Clock and Direct Clear Inputs
•
Individual Data Input to Each Flip-Flop
•
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
ow OR N
PACKAGE
(TOP VIEWI
ClR
VCC
80
80
70
70
60
60
50
50
10
10
20
20
30
3D
40
40
GNO
description
These monolithic, positive·edge-triggered flip-flops
utilize TTL circuitry to implement D-type flip·flop
logic with a direct clear input.
ClK
SN54lS273 ... FK PACKAGE
Information at the D inputs meeting the setup time
requirements is transferred to the Q outputs on the
positive·going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and is
not directly related to the transition time of the
positive-going pulse. When the clock input is at either
the high or low level, the D input signal has no effect
at the output.
(TOP VIEWI
0015tlo
~u>'"
CI)
3 2 I
Q)
(.)
4
'>
5
6
Q)
c
7
These flip-flops are guaranteed to respond to clock
frequencies ranging from 0 to 30 megahertz while
maximum clock frequency is typically 40 megahertz.
Typical power dissipation is 39 milliwatts per
flip-flop for the '273 and 10 milliwatts for the
'lS273.
00><=00
~t5GLt)1l)
logic symbol t
ClK
(EACH FLiP-FlOPI
CLEAR CLOCK 0
lI-
9 10 111213
FUNCTION TABLE
INPUTS
..J
8
(21
10
OUTPUT
0
20
L
X
X
L
3D
H
t
H
H
40
H
1
L
L
50
H
L
X
00
60
70
80
(41
(51
(71
(61
(81
(91
(131
(121
(141
(151
(17)
(16)
(18)
(191
10
20
30
40
50
60
70
80
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for DW, J, N, and W packages.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications par the terms of Texl. Instruments
::~=~~i;ai~:1~7i ~~:~::i:r ~~D::::::~!~~S
not
TEXAS •
INSTRUMENTS
POST OFfICE BOX 655012 • DALLAS, TEXAS 75265
2-759
SN54273, SN74273
OCTAL O·TYPE FLlp·FLOP WITH CLEAR
schematics of inputs and outputs
'273
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
---'--VCC
VCC---~--
INPUT
OUTPUT
Clear: Req = 3 kn NOM
Clock: Req = 6 kn NOM
All other inputs: Req = 8 kn NOM
-I
-I
r-
'LS273
~------------------~
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
C
VCC
(I)
120n NOM
<
n'
VCC
20kn NOM
(I)
en
'.
r.
INPUT
L--~-OUTPUT
"to
th
logic diagram (positive logic)
20
10
131
10
lSI
171
20
30
1131
40
Pin numbers shown are for OW, J, N, and W packages.
2-760
60
50
40
3D
141
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
50
so
7D
11S1
(17)
1141
60
70
SN54LS273, SN74LS273
OCTAL O·TYPE FLlP·FLOP WITH CLEAR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1). . . . . .
Input voltage . . . . . . . . . . . . .
Operating free-air temperature range:SN54273
SN74273
Storage temperature range
· . . . . 7V
· . . . 5.5V
_55°C to 125°C
• oOe to 70°C
_65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54273
Supply voltage, Vee
SN74273
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-SOO
IlA
High-level output current, IOH
-800
Low-level output current, tOl
Clock frequency. fclock
16
30
0
Width of clock or clear pulse, tw
I
I
Set-up time, tsu
16
30
0
16.5
16.5
Data input
201
201
Clear inactive state
25t
25t
Data hold time, th
51
Operating free-air temperature, T A
UNIT
MIN
mA
MHz
n,
n,
ns
51
-55
125
0
·e
70
U)
CD
tThe arrow indicatel that the rising edge of the clock pulse is used for reference.
U
oS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
Vil
VIK
Input clamp voltage
TEST eONDITIONSt
MIN
TYP+ MAX UNIT
V
2
Low-level input voltage
VOH High-level output voltage
Vee = MIN,
11= -12mA
Vee= MIN,
VIH=2V,
Vil = 0.8 V, 10H = -8001lA
Vee = MIN,
Val Low-level output voltage
2.4
Input current at maximum input voltage
IIH
High-level input current
VIH =2V,
Clear
Low-level input current
lOS
Short-circuit output current§
Vee= MAX
ICC
Supply current
Vee = MAX, See Note 2
Clock or 0
80
40
-3.2
Vee = MAX, VI = 0.4 V
-1.6
-18
62
....
I:
V
1
Vee = MAX, VI = 2.4 V
III
V
0.4
Vee = MAX, VI = 5.5 V
Clear
Clock or 0
V
3.4
Vll=0.8V, 10l = 16mA
II
0.8
-1.5
CD
C
V
mA
IlA
mA
-57
rnA
94
mA
tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee == 5 V, T A"" 2Soc.
§Not more than one output should be shorted at a time.
NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.6 V, is
applied to clock.
switching characteristics, Vee = 5 V, T A = 25° C
PARAMETER
TEST CONDITIONS MIN
f max Maximum clock frequency
tpHL Propagation delay time, high-to-Iow-Ievel output from clear
tplH Propagation delay time, low-to-high-Ievel output from clock
tpHL Propagation delay time, high-to-Iow-Ievel output from clock
el= 15pF,
Rl=400n,
See Note 3
30
TYP
MAX UNIT
MHz
40
18
27
17
27
ns
ns
18
27
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
2-761
SN54273, SN74273
OCTAL O·TYPE FLlp·FLOP WITH CLEAR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (seeNote 1) . . . . . .
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS273
SN74LS273
Storage temperature range
..... 7 V
..... 7 V
_55°C to 125°C
oOe to 70°C
-65°e to 150°C
NOTE 1: Voltage values are with respect to network ground terminal
recommended operating conditions
SN74lS273
SN54lS273
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-400
",A
Supply voltage. Vee
High·level output current. IOH
-400
Low-level output current, IOL
4
Clock frequency. fclock
0
Width of ·clock or clear pulse. tw
I
I
Set-up time. tsu
UNIT
MIN
30
0
20
20
Data input
201
201
Clear inactive state
251
251
51
51
Data hold time, th
Operating free-air temperature, T A
-55
125
8
rnA
30
MHz
ns
ns
ns
70
0
°e
tThe arrow indicates that the rising edge of the clock pulse is used for reference.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
Vil
Low-level input vOltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
MIN TVP*
SN74lS273
MAX MIN TVP*
Vee = MIN,
11= -18mA
Vee = MIN,
Vil = Vilmax,
VIH 2 V,
10H = -400 ",A
Vee - MIN,
VIH - 2 V,POL - 4 rnA
Vil = Vilmax
II
Input current at maximum input voltage
Vee
High-level input current
Vee MAX,
VI - 2.7 V
Vee=MAX,
VI - 0.4 V
III
Low-level
lOS
Short-circuit output current §
current
Vee = MAX
lee
Supply current
Vee - MAX,
VI-7 V
V
0.8
V
-1.5
-1.5
V
3.4
0.25
2.7
0.4
0.25
0.4
0.35
0.5
17
V
0.1
0.1
rnA
20
20
",A
0.4
See Note 2
V
3.4
-100 -20
-20
UNIT
0.7
jlOl = 8 rnA
IIH
MAX,
2.5
MAX
2
2
Low-level output voltage
i~put
SN54lS273
TEST eONDITIONSt
27
17
0.4
rnA
-100
rnA
27
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:J:AII tvpical values are at Vec = 5 V, T A = 2SoC.
§Not more than one output should be shorted at a time and duration of short circuit should not exceed one second.
NOTE 2: With all outputs open and 4.5
applied to clock.
.
V
applied to all data and clear inputs, Ice is measured after a momentary ground, then 4.5 V is
switching characteristics Vee = 5 V TA = 25°e
PARAMETER
TEST CONDITIONS
MIN
TYP
30
40
MAX
UNIT
f max
Maximum clock frequency
tpHL
Propagation delay time. high-to-Iow-Ievel output from clear
el = 15pF,
18
27
ns
tPlH
Propagation delay time, low-to-high-Ievel output from clock
RL = 2 kn,
17
27
ns
tpHL
Propagation delay time, high-to-Iow-Ievel output from clock
See Note 4
18
27
ns
NOTE 4: load cir(:uits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MHz
SN54276, SN74276
QUADRUPLE J.j( FLlp·FLOPS
OCTOBER 1976 - REVISED MARCH 1988
•
Four J-K Flip-Flops in a Single Package ...
Can Reduce FF Package Count by 50%
•
Separate Negative-Edge-Triggered Clocks with
Hysteresis ... Typically 200 mV
•
Typical Clock Input Frequency •.. 50 MHz
•
Fully Buffered Outputs
SN54276 ..• J PACKAGE
SN74276 •.. N PACKAGE
(TOP VIEW)
CLR
lJ
lCLK
lK
lQ
2Q
2K
2CLK
2J
GND
description
These quadruple TTL J-K flip-flops incorporate a
number of third-generation IC features that can
simplify system design and reduce flip-flop package
count by up to 50%. They feature hysteresis at each
clock input, fully buffered outputs, and direct clear
capability, and are presettable through a buffer that
also features an input hysteresis loop. The negativeedge-triggering clocks are directly compatible with
earlier Series 54/74 single and dual pulse-triggered
flip-flops_ These circuits can be used to emulate
D- or T-type flip-flops by hard-wiring the inputs, or
to implement asychronous sequential functions.
The SN54276 is characterized for operation over the
full military temperature range of _55°C to 125°C;
the SN74726 is characterized for operation from O°C
to 70°C.
en
PRE
L
lJ
lCLK
C
~
(21
(31
(\)
Ds
(11
....
(41
(5)
lJ
IT
lK
ClR
ClK
J
K
Q
H
X
X
X
H
2CLK
(7)
2;(
3J
H
L
X
X
X
L
L
L
X
X
X
Ht
3CLK
H
H
I
L
H
00
3;(
H
H
I
H
H
H
4J
H
H
I
L
L
L
4CLK
H
H
I
H
L
TOGGLE
H
H
H
X
X
00
it may not
persist when preset and clear return to their inactive
(81
(6)
4K
20
ro-
...
(15)
(12)
(13)
...
(14)
...
(161
(19)
(18)
...I
lI-
10
Cl
2J
OUTPUT
t This configuration is nonstable; that is,
.S;
(111
(9)
FUNCTION TABLE (EACH FlIP·FlOPI
INPUTS
(\)
(,)
logic symbol:!:
1;(
COMMON INPUTS
VCC
4J
4CLK
4K
4Q
3Q
3K
3CLK
3J
PRE
...
30
40
(171
;This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
(high) level.
PRODUCTION DATA documants contain information
currant IS af publication data. Preducts conform to
spacifications par the tarms of Taxa. Instruments
:~~=:~~8ir::I~'~ ~,=:~ti:; ~-=::~~~
not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-763
SN54276. SN74276
QUADRUPLE J.j( FLlP·FLOPS
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
--~--~--Vee
Vee---....- - -
65n
Req
NOM
INPUT
Q
CLR, J, K: Req = 4 kn NOM
eLK: Req = 10.2 kn NOM
PRE: Req = 11.6 Kn NOM
-I
-I
rC
CD
<
C:;"
CD
en
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................. , ................. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range: SN54276 ......................................... - 55"e to 125"C
SN74276 .............................................. ooe to 70"e
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65" e to 150" C
NOTE 1: Voltage values are with respect to network ground terminal.
2-764
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54276, SN74276
QUADRUPLE J.j( FLlp·FLOPS
recommended operating conditions
SN54276
Supply voltage, Vee
MIN
NOM
4.5
5
SN74276
MAX
MIN
NOM
5.5
4.75
5
-SOO
High·level output current, IOH
16
Low-level output current, IOl
0
Clock frequency
Pulse width, tw
Setup time. tsu
MAX
0
35
Clock high
13.5
13.5
Clock low
15
15
Preset or clear low
J, K inputs
12
12
31
31
Clear and preset inactive state
101
101
101
-55
101
Input hold time, Ih
Operating free-air temperature. TA
125
UNIT
5.25
V
-SOO
p.A
16
rnA
35
MHz
ns
ns
0
70
ns
°e
.J. The arrow indicates that the falling edge of the clock pulse is used for reference.
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
TEST CONOITIONSt
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
2
Vee = MIN,
II =-12rnA
Vec=MIN,
VIH -2 V,
VIL = O.S V,
10H = -SOOp.A
Vee = MIN,
VIH = 2 V,
2.4
TvPt
MAX
UNIT
V
I/)
O.S
V
Q)
(J
-1.5
V
'S
V
3.4
0.2
0.4
V
VIL = O.S V,
IOL=16rnA
II
Input current at maximum input voltage
Vee = MAX,
VI = 5.5 V
IIH
High-level input current
Vee = MAX,
VI =2.4V
40
p.A
IlL
Low-level input current
Vee = MAX,
VI = 0.4 V
-1.6
rnA
lOS
Short-circuit output current§
Vee- MAX
-S5
rnA
ICC
SupplV current
Vee=MAX
S1
rnA
1
-30
60
rnA
Q)
C
...J
lI-
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:tAli typical values are at Vee"" 5 V, TA = 2SoC.
§Not more than one output should be shorted at a time.
switching characteristics. Vee - 5 V. TA - 25°e
tPLH
PARAMETER
Maximum clock frequency
Propagation delay time, low-to-high-Ievel output from preset
tpHL
Propagation delay time, high-to-Iow-Ievel output from clear
tPLH
Propagation delay time, low-to-high level output from clock
tpHL
Propagation delay time, high-to-Iow level output from clock
f max
TEST CONDITIONS
eL
RL
= 15 pF,
= 400 Il,
See Note 2
UNIT
MIN
TVP
MAX
35
50
15
25
ns
18
30
ns
17
30
ns
20
30
ns
MHz
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-765
2-766
SN54278, SN74278
4-BIT CASCADABLE PRIORITY REGISTERS
MAY 1972 -REVISED MARCH 1988
•
•
Latched Data Inputs Serve as Buffer Register
and Can also:
Synchronize Data Acquisition
"Debounce" Mechanical Switch Input
SN5427S •. _ J OR W PACKAGE
SN74278 .•. N PACKAGE
ITOPVIEW)
STRB
D3
Cascading Input PO and Output P1
Provides "Busy"Signal Inhibiting All
Lower-Order Bits
VCC
D2
D4
•
Full TTL Compatibility
•
Use for:
Priority Interrupt
Synchronous Priority Line Selection
PO
P1
Df
NC
Y1
Y4
Y2
GND
Y3
NC-No internal connection
description
FUNCTION TASLE
The SN54278 and SN74278 each consist of four data
latches, full priority output gating, and a cascading
gate. The highest-order data applied at a D latch input
is transferred to the appropriate Y output while the
strobe input is high, and when the strobe goes low all
data is latched. The cascading input PO is fully
overriding and on the highest-order package this input
must be held at a low logic level. The P1 output is
intended for connection to the PO input of the next
lower-order package and will provide a "busy"
(high-level) signal to inhibit all subsequent lowerorder packages.
After the overriding PO input, the order of priority is
D1, D2, D3, and D4, respectively, within the package.
INTERNAL
INPUTS
OUTPUTS
LATCH NOOES
PO
G
01 02 03 04 01 0203 Q4 V1 V2 V3 V4 PI
L
H
H
X
X
X
L
X
X
X
H
L
L
L
H
L
H
L
H
X
X
H
X
X
L
H
H
H
L
L
H
X
H
L
X
L
L
L
H
L
L
L
H
L
H
L
H
L
L
L
H
H
H
H
L
L
L
L
H
H
L
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
X
X
X
X
Latched when
H
L
X
X
X
X
L
L
L
L
H
Internal Q levels are same
function of D inputs as on
first 5 lines
L
L
L
L
H
G goes low
H
H
H"" high level, L
=
II)
Q)
CJ
L
Same function of Q
nodes as on 1st
•
-S
Q)
C
...I
5 lines
lI-
low level, X = irrelevant
logic diagram (positive logic)
INPUT
PO
STROBE
G
INPUT
04
INPUT
03
INPUT
02
INPUT
01
14)r-__~~____~+1_3_)~__________~~1~2_)~__________~~~ll~3~).-__________-,
OUTPUT
PI
OUTPUT
OUTPUT
OUTPUT
Y4
Y3
Y2
PRODUCTION DATA documents .ontain information
currant 8S of publication date. Products conform to
specifications paf the terms of Texas Instruments
:~~~~:~~i~8r::1~1i ~!:~~~ti:; :.~o;=:::~:~~s
not
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
(12)
OUTPUT
V1
2-767
SN54278, SN74278
4-BIT CASCADABLE PRIORITY REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN54278 Circuits
SN74278 Circuits
Storage temperature range
NOTES:
7V
5.5V
5.5V
_55°C to 125°C
O°C to 70°C
-65°C to 150°C
1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multlple-emitter transistor. For this circuit, this rating applies between the strobe
input and any of the four data inputs.
recommended operating conditions
SN54278
SN74278
MIN NOM MAX MIN NOM MAX
Supply voltage. Vee
111
~
~
r-
i'
4.5
High-level output current, IOH
Low-level output current, IOL
tw
(I)
5
Operating free-air temperature, T A
V
IlA
16
mA
16
(see Figure 1)
UNIT
5.25
-800
20
20
ns
5
5
ns
20
20
Data hold time, th Isee Figure 1)
Strobe pulse width,
4.75
-800
Data setup time, tsu (s~e Figure.' ~
-55
125
0
70
ns
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
<
ci"
CD
5.5
5
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current at maximum input voltage
IIH
High-level input current
TEST eONolTIONst
MIN
TYP
V
PO input
V
-1.5
V
11=-12mA
Vee = MIN,
VIH = 2 V,
VIL = 0.8 V,
10H=-800IlA
Vee = MIN,
VIH = 2V,
VIL = 0.8V,
IOL = 16mA
Vee = MAX,
VI=5.5V
1 mA
Vee= MAX.
VI = 2.4 V
200 IlA
2.4
3.4
0.2
.
V
0.4
320
-3.2
Any 0 input
PO input
Vee=MAX,
VI=0.4V
-8 mA
G input
-12.8
lOS
Short-circuit output current§
Vee = MAX 1
:::~~:
ICC
Supply current
Vee = MAX,
See Note 3
-18
-55
-18
-57
55
type.
t: All typical
values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 3: ICC is measured with the PO input grounded, all other inputs at 4.5
V, and
outputs open,
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
mA
80 mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
2-768
V
80
G input
Low--Ievel input current
0.8
Vee = MIN.
Any 0 input
IlL
MAX UNIT
2
SN54278, SN74278
4·BIT CASCADABLE PRIORITY REGISTERS
switching characteristics, Vee = 5 V. TA = 25°e
PARAMETERt
tpLH
tpHL
tpLH
FROM
TO
IINPUT!
(OUTPUT)
Data
y
Data
y
TEST
WAVEFORMS
CONDITIONS
MIN
TYP MAX UNIT
A BndC
30
(with strobe high)
39
Aand D
38
tPHL
(with strobe high)
31
tpLH
A and E
46
PI
Data
tpHL
tPLH
tpLH
Strobe
PI
Band E
PO
PI
F andG
30
See Figure 1
orBandD
tpHL
39
RL=400n,
Band C
Any Y
Strobe
CL= 15pF,
(with strobe high~
31
38
42
tpHL
tpLH
tpHL
23
30
t tPLH = propagation delay time, low-to-high-Ievel output
tpHl = propagation delay time, high-to-Iow-Ievel output
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
VCC _ _.......""""_ _
ns
ns
ns
ns
ns
ns
•
--<~-Vcc
INPUT
OUTPUT
Any D: Req = 2.5 kn NOM
PO: Req = , kn NOM
G: Req "" 0.6 kn NOM
logic symbol t
03 (2)
02 (13)
01
PO
(12)
(6) Y4
50
G4
50
G3
0,1.2
50
G2
0.1
50
Gl
0
1,2.3,4
(S) V3
(9) V2
(10) Yl
(5)
PI
tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and IEC Publication 617-12.
TEXAS •
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS, TEXAS 75265
2-769
SN54278, SN74278
4·BI1 CASCADABLE PRIDRITY REGISTERS
PARAMETER MEASUREMENT INFORMATION
TEST
POINT
VCC
RL=400n
CL includes probe and jig capacitance.
All diodes are 1 N3064.
LOAD CIRCUIT
3V
DATA INPUT D
./.
(WAVEFORM AI - . . / : 1.5 V
OV
I
~
r-
I
'"---tsu _ _ _- !
STROBE INPUT G
(WAVEFORM BI
I
I
I
C
m
<
C:r
m
(II
3V
I
NONINVERTING
OUTPUT
(WAVEFORM CI
:-----ttPLH
I
'
~.5V
~tPLH!---!
I
INVERTING
OUTPUT
(WAVEFORM 01
OUTPUT P1
(WAVEFORM EI
:
~.~~-----
: - - - r ,
~.5V
:
:
,
I
I
t-tpHL---+!
I
\--tPLH-i
}/,.5V
I tpLH
,._ _ _ _ __
Z,1_1:~ ____ _ VOL
I
r-tPLHr---i
I
_tpHL-i
I
~1-1~~----
:
i l l
I+--tpHL----I
~,..-5-V--------'~~~-----INPUT PO
(WAVEFORM FI _______J
I
I--tPLH""1
OUTPUTP1
(WAVEFORM GI
VOH
!.....--J.tPHL-:
I
I
:,
I
I
:-----ttPHL
I
;----I-tPHL
I
I
>+---tpLH-l
-
3V
OV
;.-tPHL-J
~~ ~-
________...,)/,.5 V
VOLTAGE WAVEFORMS
NOTE: Input pulses are supplied by a generator having the following
characteristics: tr '" 7 ns, tf .so;; 7 ns, PRR" MHz, Zout ~ 50n.
FIGURE 1-5WITCHING TIMES
2-770
OV
1 ...........- " ' I
r---tw~
r-tw--+j
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
VOH
SN54279, SN54LS279A, SN74279, SN74LS279A
QUADRUPLE Soli LATCHES
DECEMBER 1983 - REVISED MARCH 1988
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
SN54279, SN54LS279A ... J OR W PACKAGE
SN74279 ..• N PACKAGE
SN74LS279A ... 0 OR N PACKAGE
(TOP VIEW)
lR
151
152
10
2R
25
20
Dependable Texas Instruments Quality and
Reliability
description
•
The '279 offers 4 basic S-R flip-flop latches in one
16-pin, 300-mil package. Under conventional operation, the S-R inputs are normally held high. When the
S input is pulsed low, the 0 output will be set high.
When R is pulsed low, the 0 output will be reset low.
Normally, the S-R inputs should not be taken low simultaneously. The 0 output will be unpredictable in
this condition.
VCC
45
4R
40
352
351
3R
30
GND
SN54LS279A ... FK PACKAGE
(TOP VIEWI
FUNCTION TABLE
(each latch)
3 2
INPUTS
OUTPUT
St,
-
-R
Q
H
H
00
L
H
H
H
L
L
L
L
Ht
152
10
NC
2R
25
1 20 19
4
tn
Q)
(.)
5
6
oS
7
o
Q)
8
...J
o c u
= high level
L = low level
tFor latches with double S inputs:
00 = the level of Q before the indicated input conditions were
established.
+: This configuration is nonstable: that is, it may not persist when
the 5 and A inputs return to their inactive (high) level.
H = both S inputs high
L = one or both 5 inputs low
Ola:
NZZ<'l<'l
H
t!l
lI-
NC - No internal connection
logic symbol §
logic diagram (positive logic)
(latches 1 and 3)
(latches 2 and 4)
Q
PRODUCTION DATA documants contain inlo,mation
currant as of publication date. Products conform to
specifications per the terms of Texas Instruments
=~~~~:~~i~a{:I~'~ ~!:~:~ti:r :.~o::;::::9t:~~s not
Q
§This symbol is in accordance with ANSI/lEEE Std. 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-771
S154279, S154LS279A, S174279, SN74LS279A
QUADRUPLE I·R LATCHES
schematics of inputs and outputs
'279 CIRCUITS
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS '
--'--Vee
Vce--+---
INPUT
OUTPUT
::Ir-
'LS279A CIRCUITS
C
CD
EQUIVALENT OF ALL INPUTS
<
C:;'
TYPICAL OF ALL OUTPUTS
Vee
CD
Vee
Req
fI)
120 !l NOM
INPUT
..---+-OUTPUT
~ INPUTS - Req
S INPUTS· Req
Q
Q
9 k !l NOM
15 k!l NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ................................................................ 7 V
Input voltage: '279........................................................................ 5.5 V
'LS279A ...................................................................... 7 V
Operating free-air temperature range: SN54' TYPES ............................ '. . . . . . . . .. - 55° C to 125° e
SN74' TYPES ... .. . . . . . .. . . . . . . . . .. . . .. .. . . .. . .. .. .. .. 0° e to 70" e
Storage temperature range ......................................................... , - 65° e to 150" e
NOTE1: Voltag. values are with respect to network ground terminal.
2-772
TEXAS •
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TEXAS 75285
SN54279. SN74279
QUADRUPLE S-H LATCHES
recommended operating conditions
SN54279
SN74279
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
V
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
0.8
0.8
mA
16
mA
70
°c
2
2
V
16
IOL
Low-level output current
tw
Pulse duration, low
TA
Operating free-air temperature
20
ns
20
-55
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
t
t
SN74279
SN54279
TEST CONOITIONS t
PARAMETER
MIN
VIK
Vee- MIN,
11--12mA
VOH
Vce= MIN,
VIL = 0.8 V,
IOH=-0.8mA
VOL
Vee-MIN,
VIH - 2 V,
IOL = 16 mA
II
Vee= MAX,
VI = 5.5 V
TYP*
MAX
MIN
TYP*
-1.5
2.4
3.4
0.2
MAX
-1.5
3.4
2.4
0.4
0.2
1
UNIT
V
V
0.4
1
V
mA
IIH
Vee- MAX,
VI=2.4V
40
40
IJ.A
IlL
IOS§
Vee = MAX,
VI
0.4 V
1.6
1.6
mA
Vee- MAX
- 57
mA
lee
Vee= MAX,
30
mA
-18
See Note 2
For conditions shown as MIN or MAX, use the
- 55
18
..
appropriate value specified
-18
30
..
under recommended operating conditions •
18
All typical values are at Vee = 5 V, T A = 2SoC.
§ Not more than one output should be shorted at a time.
PARAMETER
tpLH
tpHL
tpHL
-:;
Q)
c
..J
= 5 V, TA = 25°e (see note 3)
FROM
TO
(INPUT)
(OUTPUT)
S
Q
TEST eONolTIONS
eL=15pF
RL = 400 n,
R
Q)
(.)
lI-
NOTE 2: ICC is measured with all R inputs grounded, all S inputs at 4.5 V. and atl outputs open.
switching characteristics, Vee
rn
Q
NOTE 3: load Circuits and voltage waveforms are shown
In
MIN
TYP
MAX
12
22
9
15
15
27
UNIT
ns
ns
Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-773
SN54LS279A, SN74LS279A
QUADRUPLE S·l( LATCHES
recommended operating conditions
SN54LS279A
MIN
4.5
NOM
MAX
5.5
SN74LS279A
MIN NOM MAX
4.75
5.25
5
UNIT
VIH
Supply voltage
High~level input voltage
VIL
Low-level input voltage
0.7
0.8
V
IOH
High-level output current
0.4
0.4
rnA
IOL
tw
8
rnA
Pulse duration, low
TA
Operating free-air temperature
70
°e
Vee
5
2
2
Low-level output current
V
4
20
-55
125
V
ns
20
0
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
MIN
Vee= MIN,
II =-18 rnA
VOH
Vee=MIN,
VIL - MAX,
IOH= - 0.4 rnA
Vee= MIN,
VIH=2V,
IOL-4rnA
IOL =8rnA
Vee=MIN,
VIH = 2V,
II
Vee-MAX,
VI = 7 V
IIH
Vee = MAX,
VI = 2.7 V
IlL
IOS§
Vee- MAX,
VI =O.4V
ICC
Vee=MAX,
TYP*
SN74LS279A
MAX
MIN
TYP*
-1.5
VIK
VOL
t
t
SN54LS279A
TEST CONDITIONSt
PARAMETER
2.5
3.4
0.25
2.7
.0.4
- 20
See note 2
..
V
0.25
0.4
0.25
0.5
V
0.1
rnA
20
20
IlA
-0.2
-0.2
rnA
-100
rnA
7
rnA
-100
3.8
UNIT
V
3.4
0.1
Vee- MAX
MAX
-1.5
-20
7
3.8
..
For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at
Vee = 5
V, TA
= 2SoC.
§ Not more than one output should be shorted at e time, and the duration of the short-circuit should be less than one second.
NOTE 2: ICC is measured with all R inputs grounded, all S inputs at 4.5 V. and all outputs open.
switching characteristics, Vee = 5 V, TA = 2Soe (see note 3)
PARAMETER
tpLH
tpHL
tpHL
FROM
(INPUT!
TO
(OUTPUT)
5
Q
R
Q
TEST CONDITIONS
RL=2k!l,
CL = 15 pF
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-774
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. n:;XAS 75265
MIN
TYP
MAX
12
22
13
21
15
27
UNIT
ns
ns
SN54LS2BO, SN54S2BO, SN74LS2BO, SN74S2BO
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
DECEMBER 1972 - REVISED MARCH 1988
• Generates Either Odd or Even Parity
for Nine Data Lines
SN54LS280. SN54S280 ... J OR W PACKAGE
SN74LS280. SN74S280 ... 0 OR N PACKAGE
(TOP VIEWI
• Cascadable for n-Bits
• Can Be Used to Upgrade Existing
Systems using MSI Parity Circuits
(TOP VIEWI
~ODD
0,2,4,6,8
H
L
1,3,5,7,9
L
H
U
D
= low level
NC
NC
NC
l:EVEN
2k
4
E
5
6
NC
7
8
o
en
CI)
NC
'S;
(.)
C
CI)
C
9
191
1101
(5)
Ill)
..J
OOU«al
OZZ
~
lI-
~I!l
EVEN
(12)
~
(13)
NC - No internal connection
000
(1)
G
U
U
J:I!lZ>u..
logic symbol t
B
B
A
OUTPUTS
2: EVEN
C
C
SN54LS280, SN54S280 ... FK PACKAGE
THRU I THAT ARE HIGH
181
E
l:EVEN
:WDD
GND
FUNCTION TABLE
A
F
0
• Typical Power Dissipation:
'LS280 ... 80 mW
'S280 ... 335 mW
H = high level, L
VCC
H
NC
• Typical Data-to-Output Delay of Only 14 ns
for 'S280 and 33 ns for 'LS280
NUMBER OF INPUTS A
G
(2)
H
(4)
tThis symbol is in accordance with ANSIIIEEE Std. 91·1984 and IEC
Publication 617·12.
Pin numbers shown are for 0, J, N. and W packages.
description
These universal, monolithic, nine-bit parity generators/checkers utilize Schottky-clamped TTL high-performance circuitry and
feature odd/even outputs to faciliate operation of either odd or even parity application. The word-length capability is easily expanded by cascading as shown under typical application data.
Series 54LS174LS and Series 54S/74S parity generators/checkers offer the designer a trade-off between reduced power
consumption and high performance. These devices can be used to upgrade the performance of most systems utilizing the
'180 parity generator/checker. Although the 'LS280 and 'S280 are implemented without expander inputs, the corresponding
function is provided by the availability of an input at pin 4 and the absence of any internal connection at pin 3. This permits the
'LS280 and 'S280 to be substituted for the '180 in existing designs to produce an identical function even if 'LS280's and
'S280's are mixed with existing '180's.
These devices are fully compatible with most other TTL circuits. All 'LS280 and 'S280 inputs are buffered to lower the drive
requirements to one Series 54LS174LS or Series 54S174S standard load, respectively.
PRODUCTION DATA documants contain information
currant 88 of publication date. Products conform ta
specifications par the tarms of TeJls Instruments
=~~=~~i~.{:~~l~ ~=:~ti:r :'~D::~:::::':~~s
not
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-775
SN54LS280, SN54S280, SN74LS280, SN74S280
9·81T ODD/EVEN PARITY GENERATORS/CHECKERS
schematics of inputs and outputs
'L8280
r-----------~----~
TYPICAL OF OUTPUTS
EQUIVALENT OF INPUTS
~------------~~VCC
120fl
NOM
-
VCC
20 kflNOM
INPUT
r.
•
.....---I4I--....- - - -....-0UTPUT
~,
~t~,
m
-I
-I
~
C
'8280
r----------------------,
CD
<
EQUIVALENT OF INPUTS
rr
CD
~--------------------~
TYPICAL OF OUTPUTS
- - - - - - -....-VCC
!II
50flNOM
VCC - - - - - -. . .- - -
INPUT
OUTPUT
absolute maximum ratings over operating free·air temperature rpnge (unless otherwise noted)
Supply voltage (see Note 1) .................................................................... 7 V
Input voltage: 'LS2S0 ........................................................................ 7 V
'S280 ....................................................................... 5.5 V
Operating free-air temperature range: SN54' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
SN74' ................................................ oOe to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
2-776
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54LS280. SN74LS280
9·81T ODD/EVEN PARITY GENERATORS/CHECKERS
recommended operating conditions
SN74LS280
SN54LS280
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
-0.4
0.4
mA
8
mA
70
°c
4
IOL
Low-level output current
TA
Operating free-air temperature
V
2
2
UNIT
125
-··55
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Vee
VIK
VOH
VOL
MIN,
0
Il
Vee - MIN,
VIH-2V,
VIL~MAX,
IOH
Vee - MIN,
VIH"2V,
VI L
~
MIN
TYP*
~
MAX
MIN
2.5
- 0.4 mA
MAX
- 1.5
2.7
3.4
0.25
lIOL" 4mA
0.4
IIOL ~ 8 mA
MAX
TYP*
-1.5
-18mA
o
SN74LS280
SN54LS280
TEST CONOITIONS
UNIT
V
V
3.4
0.25
0.4
0.35
0.5
V
II
Vee
0.1
0.1
IIH
Vee - MAX,
VI-2.7V
20
20
pA
IlL
Vee" MAX,
VI-O.4V
-0.4
0.4
mA
IOS~
Vee - MAX
100
mA
27
mA
~
MAX,
~
7 V
- 20
Vee - MAX,
lee
VI
See Note 2
-100
16
20
16
27
mA
II)
Q)
(j
oS;
Q)
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t
All typical values are at
Vee
=
5 V, T A
C
25°C.
=
~ Not more than one output should be shalted at a time and duration of the short circuit should not exceed one second.
NOTE 2:
..J
lI-
ICC is measured with all inputs grounded and all outputs open.
switching characteristics, VCC
PARAMETER~I
tpLH
=
5 V, T A
=
25"C
FROM
TO
IINPUT)
(OUTPUT)
Data
~
tpHL
tpLH
tpHL
Even
TEST CONDITIONS
CL
=
15pF,RL
~
MIN
2 kll,
Inputs not under test at 0 V,
Data
~
Odd
See Note 3
TYP
MAX
33
50
29
45
23
35
31
50
UNIT
ns
ns
~:tPLH
propagation delay time, low-to-high-Ievel output. tpHL
propagation delay time, high to-low-level output
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
0;-
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-777
SN54S280, SN74S280
9·BIT ODD/EVEN PARITY GENERATORS/CHECKERS
recommended operating conditions
SN54S280
MIN
Supply voltage, V ce
NOM
4.5
SN74S280
MAX
MIN
5.5
4.75
5
High·level output current, IOH
NOM
5
-1
Low-level output current, tOL
20
Operating free-air temperature, T A
-55
125
0
MAX
UNIT
5.25
V
-1
mA
20
mA
70
"e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
~
~
TEST CONOITIONSt
CD
Low-level output voltage
CD
en
MAX UNIT
Vec' MIN,
11"-18mA
VCe" MIN,
VIH=2V,
VIL' 0.8 V,
10H = -1 mA
VeC" MIN,
VIH-2V,
VIL = 0.8 V,
10L = 20mA
I SN54S'
I SN74S'
V
2.5
3.4
2.7
3.4
0.8
V
-1.2
V
V
0.5
V
II
Input current at maximum input voltage
VCC= MAX, VI = 5.5V
1
IIH
High-level input current
VCC = MAX, VI = 2.7 V
50
~A
IlL
Low-level input current
VeC" MAX, VI = 0.5 V
-2
mA
lOS
Short-circuit output current~
-100
mA
Vee = MAX
-40
VCC = MAX, See Note 2
ICC
Supply current
VeC" MAX, TA=125'C,
<
(;'
TVpj:
2
rC
MIN
See Note 2
SN54S280
67
99
SN74S280
67
105
94
SN54S280N
mA
mA
mA
f For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
~AII typical values are at Vee = 5 V. T A ~ 25" C.
*Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
NOTE 2: ICC is measured with all inputs grounded and all outputs open.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETERII
tpLH
tpHL
tpLH
tPHL
FROM
TO
(INPUT)
(OUTPUT)
Data
:r Even
Data
~
Odd
TEST CONDITIONS
CL
= 15pF,
MIN
RL' 280n,
See Note 3
1tPLH = propagation delay time, low~to~high~level output: tpHL = propagation delay time, high·to~low·level output
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
2-778
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TVP
MAX UNIT
14
21
11.5
18
14
21
11.5
18
ns
ns
SN54LS280, SN54S280, SN74LS280, SN74S280
9-81T ODD/EVEN PARITY GENERATORS/CHECKERS
logic diagram (positive logic)
Ell
Pin numbers shown are for 0, J, N. and W packages.
TYPICAL APPLICATION DATA
81·LlNE PARITY/GENERATOR CHECKER
25·LlNE PARITY/GENERATOR CHECKER
A
B
C
0
E
l:
Three 'LS280's or 'S280'5 can be
used to implement a 25"line parity
generator/checker. This arrangement
will provide parity in typicallv 75 or
25 nanoseconds respectively.
EVEN
F
G
H
I
B
F
l:
A
B
C
0
E
l:
EVEN
EVEN
l:
A
B
C
0
E
H = EVEN
L - 000
H
=
ODD
bits
or
in
typically
75 or 25 nanc"
seconds respectively.
l:
G
H 'L5280/
'5280
I
As an alternative, the outputs of two
or three parity generators/checkers
can be decoded with a "2-input ('S86
'LS86)
B
C
0
E
H 'L5280/
I '5280
A
EVEN
A
l:
EVEN
F
G
L - EVEN
B
F
cascading 'LS2BO's
generated for word lengths up to 81
F
000
G
H 'L5280/
I '5280
C
0
E
by
'S280'5. As shown here, parity can be
G
'L5280/
H
'5280
I
'L5280/
'5280
A
C
0
E
Longer word lengths can be implemented
3-input
('S135)
exclusive-OR gate for 18- or 27·line
A
B
C
0
E
H
=
EVEN
L * 000
l:
F
000
G
'LS280/
H
I '5280
H = 000
L
=
EVEN
l:
EVEN
~
F
G
H
I
l:
EVEN
'L5280/
'5280
TO OTHER
'L5280/
'5280
parity applications.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-779
2-780
SN54283. SN54LS283. SN54S283.
SN74283. SN74LS283. SN74S283
4-BIT BINARY FULL ADDERS WITH FAST CARRY
OCTOBER 1976 - REVISEO MARCH 19B8
•
Full-Carry Look-Ahead Across the Four
Bits
•
Systems Achieve Partial Look-Ahead
Performance with the Economy of Ripple
Carry
•
SN54283, SN54LS283 ... J OR W PACKAGE
SN64S283 ... J PACKAGE
SN74283 ... N PACKAGE
5N74LS283, SN74S283 ... D OR N PACKAGE
(TOP VIEWI
:r2
TYPICAL AOO TIMES
TWO
TWO
TYPICAL POWER
8-IIIT
16-BIT
OISSIPATION
TYPE
WOROS
WOROS
PER ADDER
'283
23n5
43n5
310 mW
'L5283
25n5
45ns
95 mW
'5283
15ns
30ns
516 mW
VCC
B3
A3
B2
A2
1:1
A1
B1
CO
Supply Voltage and Ground on Corner
Pins to Simplify P-C Board Layout
1:3
A4
B4
1:4
C4
GND
SN54LS283, SN54S283 ... FK PACKAGE
(TOP VIEW)
U
!II ~ lil ~~
A2
1:1
description
The '283 and 'LS283 adders are electrically and
functionally identical to the '83A and 'LS83A,
respectively; only the arrangement of the terminals
has been changed. The 'S283 high performance
versions are also functionally identical.
These improved full adders perform the addition of
two 4-bit binary words, The sum (~) outputs are
provided for each bit and the resultant carry (C4) is
obtained from the fourth bit. These adders feature
full internal look-ahead across all four bits generating
the carry term in ten nanoseconds, typically, for the
'283 and 'LS283, and 7.5 nanoseconds for the 'S283.
This capability provides the system designer with
partial look-ahead performance at the economy and
package
count
of
ri pple-carry
reduced
implementation.
The adder logic, including the carry, is implemented
in its true form. End around carry can be accomplished without the need for logic or level inversion.
Series 54, Series 54LS, and Series 54S circuits are
characterized for operation over the full temperature
range of -55°C to 125°C. Series 74, Series 74LS, and
Series 74S circuits are characterized for O°C to 70°C
operation.
A3
1:3
NC
NC
A1
B1
A4
B4
NC - No internal connection
FUNCTION TABLE
OUTPUT
INPUT
%%
% % % 1% 1% % %
co- L
COsH
_iii
WHEN
ct.""
C2.~
%~~
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
L
L
L
H
L
L
H
L
L
H
L
L
L
H
L
H
H
L
L
L
H
L
H
H
L
L
L
H
L
L
H
H
H
H
L
H
L
H
H
L
L
L
H
L
H
H
L
H
H
L
L
L
H
H
H
H
L
L
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
H
L
L
H
H
H
L
L
L
H
L
L
L
H
L
H
H
H
L
L
L
H
H
H
L
H
L
L
H
H
L
H
L
L
H
H
L
L
H
H
L
H
H
L
H
H
H
L
H
L
H
H
L
H
H
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H = high level, L = low level
NOTE: Input conditions at A1, 81, A2, 82, and CO are used to
determine outputs l; 1 and ~2 and the value of the internal
carry C2. The values at C2. A3, 83, A4, and 84 are then
used to determine outputs ~3. ~4. and C4.
PRODUCTION DATA doc.monls contain information
currant 88 of publication data. Products conform to
specifications per the tarms af TaXIS Instruments
:'~~~:~~i~I{~:1~1~ ~~:\:~ti:r :1~D:=:::::t:~~ not
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-781
SN54283. SN54LS283. SN54S283.
SN74283•. SN74LS283. SN74S283
4"BIT BINARY FULL ADDERS WITH FAST CARRY
schematics of inputs and outputs
logic symbol t
AI
A2
A3
A4
81
82
83
84
CO
(5)
(3)
(14)
(12)
(6)
2)
(15)
(11)
(7)
'283
~
]- {
}
CO
TYPICAL OF ALL
OUTPUTS
EQUIVALENT OF
EACH INPUT
(4)
~1
II)
(10)
(9)
VCC
V~=Cr
~2
(13)
Req
~3
~4
INPUT
-OUTPUT
C4
CI
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
CO input: Req = 4 kn NOM
Any A or B: Req = 3.5 kn NOM
C4 output: R = 100 n NOM
Any~: R = 120 n NOM
'LS283
EQUIVALENT OF
EACH INPUT
logic diagram (positive logic)
TYPICAL OF ALL OUTPUTS
VCC--......- -
-4
-4
r-
---~~-VCC
Req
INPUT~*+--,t-
C
OUTPUT
CD
<
(=j"
CD
CIl
CO input: Req = 17 kn NOM
Any A or B: Reo = 8.5 kn NOM
c
'S283
EQUIVALENT OF
EACH INPUT
VCC
TYPICAL OF ALL OUTPUTS
---~~-VCC
2.8 kn NOM
INPUT
--
OUTPUT
Pin numbers shown are for 0, J, N, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage: '283, 'S283
'LS283 . . _ .
I nteremitter voltage (see Note 2)
Operating free-air temperature range: SN54283, SN54LS283, SN54S283 _
SN74283, SN74LS283, SN74S283 .
Storage temperature range
NOTES:
7V
5,5V
7V
5.5V
. -55°C to 125°C
oOe to 70°C
. -65°eto 150°C
1. Voltage values, except interemitter voltage,. are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. This rating applies for the '283 and 'S283 only between
the following pairs: Aland 81, A2 and 82, A3 and 83, A4 and B4.
2-782
TEXAS ."
fNSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54283, SN14283
4-BIT BINARY FULL ADDERS WITH FAST CARRY
recommended operating conditions
SN54283
Supply Voltage, Vee
High-level output current, IOH
SN74283
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
~.5
4.75
5
5,25
Any output except C4
-800
-800
Output C4
-400
- 400
16
16
Any output except C4
Low-level output current, IOL
Output C4
8
8
Operating free-air temperature, T A
-55
125
0
70
UNIT
V
"A
rnA
'e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
SN54283
TEST CONDITIONSt
TYP+
MIN
SN74283
MAX
2
VOH
High-level output voltage
VOL
Low-level output voltage
Input current at maximum
VCC - MIN,
11--12rnA
VCC: MIN,
VIH:2V,
VIL: 0.8 V,
IOH: MAX
VCC: MIN,
VIH: 2 V,
VIL: 0.8 V,
IOL: MAX
Vce: MAX,
2.4
MIN
TYP+
MAX
UNIT
V
2
0.8
0.8
V
-1.5
-1.5
V
2.4
3.6
0.2
0.4
V
3.6
0.2
0.4
V
VI: 5.5V
1
1
rnA
IIH
High-level input current
VCC - MAX, VI-2.4V
40
40
IlL
Low-level input current
Vec - MAX, 'VI-0.4V
-1.6
1.6
"A
rnA
II
input voltage
Short-circuit
lOS
l Any output except C4
output current ~
I Output C4
ICC
Supply current
Vec: MAX
-20
-55
-18
-55
-20
-70
-18
-70
All B low, other
Vce: MAX, inputs at 4.5 V
Outputs open All inputs at
56
56
rnA
66
4.5 V
rnA
99
66
110
TYP
MAX
14
21
12
21
16
24
16
24
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:~AII typical values are at Vee
=
5 V, T A
=
25() C.
~OnIY one output should be shorted at a time.
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER~
tpLH
tPHL
tPLH
FROM (INPUT)
CO
TO (OUTPUT)
Any 1:
TEST CONDITIONS
CL:15pF,
R L : 400 n,
See Note 3
Ai orBi
1:j
tpHL
tpLH
CO
C4
tPHL
CL: 15pF,
tpLH
See Note 3
tpHL
Ai or Bj
MIN
C4
RL:780n,
9
14
11
16
9
14
11
16
UNIT
ns
ns
ns
ns
'tPLH = propagation delay time, low-to-high-Ievel output
tpHL = propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS .."
INSTRUMENTS
POST OFFiCe BOX 655012 • DALLAS, TeXAS 75265
2-783
SN54LS283, SN74LS283
4·BIT BINARY FULL ADDERS WITH FAST CARRY
recommended operating conditions
SN54LS283
Supply voltage, V CC
SN74LS283
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-400
IlA
B
mA
70
°c
High·level output current, 10H
-400
Low-level output current, IOL
Operating free-air temperature. T A
UNIT
MIN
4
-55
125
0
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
rC
II
IIH
CD
<
,;"
CD
IlL
lOS
VCC= MIN,
11- -18mA
VCC- MIN,
VIH - 2V,
VIL - VIL max,
10H =-400IlA
VCC= MIN,
VOL Low-level output voltage
-I
-I
MIN
VIH-2V,
VIL = VIL max
2.5
CO
High·level
Any A or B
input current
CO
Low·level
Any A orB
input current
CO
VCC= MAX,
Short-circuit output current§
VCC= MAX,
VCC= MAX,
UNIT
V
O.B
V
-1.5
-1.5
V
3.4
2.7
0.4
V
3.4
0.25
0.4
0.35
0.5
0.2
0.2
0.1
0.1
40
40
V
mA
VI =7V
VI =2.7V
VI =0.4V
VCC= MAX
grounded
VCC= MAX,
All B low, other
Outputs open
inputs at 4.5 V
All inputs at
4.5V
20
20
-O.B
-O.B
-0.4
-0.4
-100
-20
All inputs
Supply current
MAX
0.7
Any Aor B
atrnaximum
input voltage
TYP*
2
0.25
jlOL=4mA
MIN
pOL-SmA
en
ICC
SN74LS283
TYP* MAX
2
VOH High-level output voltage
Input current
SN54LS283
TEST CONDITIONSt
-20
-100
22
39
22
39
19
34
19
34
19
34
19
34
IlA
mA
mA
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII tvpical values are at Vee = 5 V, T A = 2SoC.
§Only one output should be shorted at a time and duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~
tpLH
FROM (INPUT)
CO
TO (OUTPUT)
Any
TEST CONDITIONS
~
tPHL
tpLH
tpHL
tPLH
AjorBi
CO
C4
AjorBj
C4
tpHL
tpLH
~i
CL
= 15pF,
See Note 3
tPHL
1tPLH = propagation delay time, low-to-high-Ievel output
tpHL = propagation delay time. high-to-Iow-Ievel output
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-784
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
RL=2kU,
MIN
TYP
MAX UNIT
16
24
15
24
15
24
15
24
11
17
11
22
11
17
12
17
ns
ns
ns
ns
SN54S283, SN74S283
4·BIT BINARY FULL ADDERS WLTH FAST CARRY
recommended operating conditions
SN74S283
SN64S283
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
Supply voltage, VCC
5.25
V
-1
-1
mA
-500
-500
/LA
20
20
10
mA
70
°c
Any output except C4
High·level output current, IOH
Output C4
Any output except C4
Low-level output current. IOL
10
OutputC4
-55
Operating fre.air temperature, T A
UNIT
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIH
PARAMETER
High-level input voltage
VIL
Low·level input voltage
VIK
Input clamp voltage
VOH
VOL
High·level output voltage
TEST CONDITIONSt
IIH
IlL
lOS
UNIT
V
0.8
V
-1.2
V
VCC = MIN,
II =-18mA
VCC- MIN,
VIH=2V,
2.5
3.4
ISN74S283
VIL = 0.8 V,
IOH = MAX
2.7
3.4
VCC = MIN,
VIH - 2 V,
VIL =0.8 V,
IOL= MAX
VCC=MAX,
VI = 5.5V
VCC = MAX,
VI=2.7V
50
/LA
VCC -MAX,
VI = 0.5 V
mA
-40
-2
100
-20
-100
input voltage
High-level input current
Low-level input current
Short-circu it
I Any output except C4
I
MAX
(SN54S283
Low-level output voltage
output current§
TVP.
2
Input current at maximum
II
MIN
0.5
1
VCC = MAX
Output C4
V
V
II)
mA
U
.S;
Q)
CI)
C
....I
....
....
mA
All B low. other
ICC
Supply cu rrent
VCC= MAX,
inputs at 4.5 V
Outputs open
All inputs at
BO
mA
95
4.5V
160
tFor conditions shown 81 MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
typo.
fAil typical values are at Vee
=5
V. TA = 25 0 C.
§ Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER.
tpLH
tpHL
tpLH
tpHL
tpLH
FROM (INPUT)
CO
Ai or Bj
CO
TO (OUTPUT)
Any I:
TEST CONDITIONS
CL = 15pF, RL = 280
I:i
C4
CL = 15 pF, RL = 660
tpLH
S.. Note 3
Ai or Bj
n,
See Note 3
tpHL
tpHL
MIN
C4
n,
TVP
11
MAX
18
12
18
12
18
11.5
18
6
11
7.5
11
7.5
12
8.5
12
UNIT
ns
ns
ns
ns
'tPLH = propagation delay time, low-to-high-Ievel output
tpHL =:= propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76285
2-785
-I
-I
r-
C
CD
<
ri'
CD
en
2-786
SN54284. SN54285. SN74284. SN74285
4-BIT BY 4-BIT PARALLEL BINARY MULTIPLIERS
MAY 1972 - REVISED MARCH 1988
•
Fast Multiplication of Two Binary Numbers
a-Bit Product in 40 ns Typical
•
Expandable for N-Bit-by-n-Bit Applications:
16-Bit Product in 70 ns Typical
32-Bit Product in 103 ns Typical
•
Fully Compatible with Most TTL Circuits
•
Diode-Clamped Inputs Simplify System
Design
SN54284 ... J OR W PACKAGE
SN74284 ..• N PACKAGE
(TOP VIEW)
2C
28
2A
10
lA
18
lC
GNO
description
SN54285 ... J OR W PACKAGE
SN74285 ... N PACKAGE
(TOP VIEW)
These high·speed TTL circuits are designed to be used
in high·performance parallel multiplication applica·
tions. When connected as shown in Figure A, these
circuits perform the positive·logic multiplication of
two 4-bit binary words. The eight·bit binary product
is generated with typically only 40 nanoseconds
delay.
This basic four-by·four multiplier can be utilized as a
fundamental building block for implementing larger
multipliers. For example, the four·by·four building
blocks can be connected as shown in Figure 8 to
generate submultiple partial products. These results
can then be summed in a Wallace tree, and, as
illustrated, will produce a 16·bit product for the two
eight-bit words typically in 70 nanoseconds.
SN54H 183/SN74H 183
carry·save adders
and
SN54S181/SN74S181 arithmetic logic units with the
SN545182/SN74S182 look·ahead generator are used
to achieve this high performance. The scheme is
expandable for implementing N X M bit multipliers.
VCC
20
GA
G8
Y4
Y5
Y6
Y7
2C
28
2A
10
lA
18
lC
GNO
VCC
20
GA
G8
YO
Yl
Y2
Y3
II)
CI)
CJ
'S;
CI)
C
..J
logic symbols t
lI-
'284
lA (5)
lB (6)
lC 171
(12) Y4
10 (4)
2A (3)
2B (2)
111) V5
(10) V6
(9) V7
2C (1)
20 (15)
The SN54284 and SN54285 are characterized for
operation over the full military temperature range of
-55D C to 125D C; the SN74284 and SN74285 are
characterized for operation from ODC to 70D C.
liB (13)
GA (14
'285
1A IS)
lB (6)
lC (7)
10 (4)
2A (3)
28 (2)
2C (1)
20 (15)
(12) VO
(11LYl
(10)
V2
(9)
Y3
GB (13)
GA (14)
tThese symbols are in accordance with ANSI/IEEE Std. 91·1984 and
IEC Publication 617·12.
PRDDueTIO. DATA documants "Rtein information
current IS of publil:llti.1 data. Products conform to
specificationl par the tarms af Texas Instrumaldl
.=~:::i;·{::1~7~ ~r::\:~:; ~iU::::~::S
nat
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-787
SN54284, SN54285, SN74284, SN74285
4·BIT BY 4·BIT PARALLEL BINARY MULTIPLIERS
schematics
TYPICAL OF
ALL OUTPUTS
EQUIVALENT OF
EACH INPUT
Vcc---+--OUTPUT
6kn NOM
INPUT
BINARY INPUTS
WQRD 2
-I
-I
r-
WORD 1
~~
I
C
CD
<
ri"
CD
UI
I
2D 2C
2A
1D
1C
1B
1A
SN54284/SN74284
fGA
GB
Y7
~
2B
I
2D
I
2C
2A
1D
1C
1B
SN54285/SN74285
fGA
GB
Y5
Y4
Y3
I I
I
I
Y6
I
2B
Y2
Y1
I I
YO
I
~
25
~
23
22
21
20
~. . . . . . . . . . . . . . . . . . . . . .~V~. . . . . . . . . . . . . . . . . . . . . . . .~'
\ 27
BINARY OUTPUTS
FIGURE A-4 X 4 MUL TIPL!ER
2-788
TEXAS
~
INSlRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1A
8-II'T INPUT
WORD'
ToT
tJ:\
~.
.. x .......nPUER
cs.F .... At
•
I ~:j
~
"
.. X .. MUL TIPLlER
IS-F .... AI
r
C
.
."
0
~
0
:::-
f;jZ
~~
~ iC~
~C:~
~~
;4
.
'X4MULTlPLlEA
ISH Figu.eAI
"zO
.
r~
.. X 4 MULTIPllEA
IS.. FIgUre A)
___
z8 \
'ft
2'0
2'1
~
(FOUR
A
I
2ii
2'
2" \
25
SUBMULTIPLE
PRODUCTS
~~ ~~A~~:~S!~~ ~~
,p,
=
::::j
CD
~lTl
~Z
~ Ci14r
a::
3
2
1 2019
II)
Q)
CJ
"S;
Q)
C
All of these counters have a gated zero reset and the
'290 and 'LS290 also have gated set-to-nine inputs for
use in BCD nine's complement applications.
...J
lI-
To use the maximum count length (decade or four-bit
binary) of these counters, the B input is connected to
the OA output. The input count pulses are applied to
input A and the outputs are as described in the
appropriate function table. A symmetrical divide-byten count can be obtained from the '290 and 'LS290
counters by connecting the 00 output to the A input
and applying the input count to the B input which
gives a divide-by-ten square wave at output 0A.
9 10111213
~~~8c1
(!l
'LS2!13
NC
NC
Oc
NC
9 10 111213
NC - No internal connection
PRODUCTION DATA documents contain information
currant 8S of publication date. Products conform to
spacifications per the terms of Texas Instruments
::~~:~i~ai~:1~1~ ~!:~~:~; :.~:=::9t::s~s not
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-791
SN54290. SN54293. SN54LS290. SN54LS293.
SN74290, SN74293. SN74LS290. SN74LS293
DECADE AND 4·BIT BINARY COUNTERS
logic symbols t
'290, 'LS290
>OW {
-f
-f
aA
(5)
aB
(4)
CT
(8)
2
3CT=4
(9)
Oc
aD
'293, 'LS293
....
RO(l) (12)
C
RO(2) (13)
&
CD
CTR
CT=O
<
C;'
.," f
CD
(I)
CT
2
(9)
aA
(5)
aB
(4)
(8)
Oc
aD
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
2·792
.. 11EXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
5N54290, 5N54293, 5N54L5290, 5N54L5293,
5N74290, 5N74293, 5N74L5290, SN74LS293
DECADE AND 4·BIT BINARY COUNTERS
'290, 'LS290
BI-QUINARY (5-2)
'290, 'LS290
BCD COUNT SEQUENCE
(S..
COUNT
(See Not. B)
Note A)
OUTPUT
OUTPUT
COUNT
QO QC Os QA
'293, 'LS293
COUNT SEQUENCE
'290, 'LS290
RESET/COUNT FUNCTION TABLE
QA QD QC QS
ROlli ROl21 R9111
H
H
L
0
L
L
L
L
0
L
L
L
L
1
L
L
L
H
L
L
L
H
H
2
3
L
L
H
L
L
L
H
L
L
L
H
H
1
2
3
L
L
H
H
4
L
H
L
L
4
L
H
L
L
L
5
L
H
L
H
5
H
L
L
L
L
X
6
L
H
H
L
6
H
L
L
H
X
L
L
H
H
H
X
L
L
X
X
L
L
X
X
X
X
X
L
X
OUTPUT
COUNT
R9121 QD QC QS QA
L
X
L
L
L
L
H
(SoeNot. C)
OUTPUT
RESET INPUTS
L
L
L
L
L
H
QD Qc
COUNT
COUNT
COUNT
COUNT
Qs QA
0
L
L
L
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
L
H
H
L
7
L
H
H
H
7
H
L
H
L
7
L
H
H
H
8
H
L
L
L
8
H
L
H
H
8
H
L
9
H
L
L
H
9
H
H
L
L
'293, 'l!.S293.
RESET/COUNT FUNCTION TABLE
RESET INPUTS
NOTES:
A. Output 0A is connected to input B for BCD count.
B. Output
aD
is connected to input A for bi-quinary
count.
C. Output QA is connected to input B.
D. H = high level, L"" low tevel, X "" irrelevant
6
OUTPUT
L
L
9
H
L
L
H
10
H
L
H
L
11
H
L
H
H
ROlli
ROl21
QD
QC
QS
QA
12
H
H
L
L
H
H
L
L
L
L
13
H
H
L
H
14
H
H
H
L
15
H
H
H
H
L
X
X
L
COUNT
COUNT
U)
logic diagrams (positive logic)
Q)
CJ
'290, 'LS290
'S;
'293, 'LS293
Q)
+-__--
(91
a
J
OA
INPUT A (1O)
INPUT A .:.(1:.:0-'-)_ _ _
C
(9)
OA
CK
K
..J
~
~
(51 0B
(5) OB
INPUT B (11)
INPUT B .:.(1:...:1-,-)--.tt----4>
(4)
(4)
Oc
Oc
(8)
aD
ROil) ....(1-",2",,)~r--.....
RO(2) _(1_3_)---;,--/
(81 aD
Pin numbers shown are for D. J. N. and W packages.
The J and K inputs shown without connection are for reference only and are functionally at a high level.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-793
SN54290, SN54293, SN74290, SN74293
DECADE AND 4·BIT BINARY COUNTERS
3--
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EOUIVALENT OF EACH INPUT
Vee
Vee
Req
INPUT
--
OUTPUT
INPUT
A
B ('2901
B ('293)
All resets
Req NOM
2.5 kH
1.25 kH
2.5 kH
SkH
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage " . . . . .
Interemitter voltage (see Note 2)
Operating free·air temperature range: SN54' Circuits
SN74' Circuits
Storage temperature range
"""i
"""i
r-
o
CD
NOTES;
<
c;'
7V
5.5V
5.5 V
-55°C to 125°C
O°C to 70°C
_65°C to 150°C
1'. Voltage values, except interernitter voltage, are with respect to network ground terminal.
2. This is the vOltage between two emitters of a multiple-emitter transistor. For these circuits, this rating applies between the two
RO inputs, and for the '290 circuit, it also applies between the two A9 inputs.
CD
til
recommended operating conditions
SN54'
MIN
Supply voltage, Vee
4.5
Low-level output current, IOL
Pulse width, tw
2-794
5
SN74'
MAX
MIN
5.5
4.75
-800
High-level output current, IOH
Count frequency, fcount
NOM
16
A input
0
32
B input
0
15
16
A input
B input
30
30
Reset inputs
15
15
Reset inactive-state setup time, tsu
25
Operating free-air temperature, T A
55
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
NOM
5
MAX
UNIT
5.25
V
-BOO
IJA
16
rnA
0
32
0
16
MHz
15
ns
25
125
0
ns
70
°e
SN54290, SN54293, SN74290, SN74293
DECADE AND 4-BIT BINARY COUNTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High·level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
TEST CONOITIONSt
MIN
'290
TYP:,
'293
UNIT
Typj: MAX
V
0.8
Low-level output voltage
II
Input current at maximum input voltage
Vee - MIN,
11- -12rnA
Vee;MIN,
VIH;2V,
VIL; 0.8 V,
10H; -800/LA
Vee - MIN,
VIH; 2 V,
VIL; 0.8 V,
10L; 16 rnA~
High-level input current
0.2
VI;2.4V
Vee;MAX,
B input
Any reset
Low-level input current
2.4
3.4
A input
VI;O.4V
Vee= MAX,
B input
1
40
80
80
120
80
-1.6
-1.6
-3.2
-3.2
-4.8
-3.2
-20
-57
-20
-18
-57
-18
Vee;MAX
ICC
Supply current
Vee; MAX, See Note 3
SN74'
29
0.4
1
I
Short-circuit output current §
42
-57
-57
26
V
V
V
40
I SN54'
lOS
3.4
0.2
0.4
Vee;MAX, VI=5.5V
A input
0.8
-1.5
-1.5
2.4
Any reset
IlL
MIN
2
2
VOL
IIH
MAX
39
V
rnA
/LA
rnA
rnA
II)
Q)
rnA
(,)
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
.:;:
:j:AII typical values are at Vee = 5 V. T A = 2SoC.
§Not more than one output should be shorted at a time.
~QA outputs are tested at tOL = 16 rnA plus the limit value of IlL for the B input. This permits driving the B input while maintaining full
C
fan-out capability.
NOTE 3: ICC is measured with all outputs open, both AO inputs grounded following momentary connection to 4.5 V. and all other inputs
grounded.
Q)
..J
~
....
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER'
f max
tPLH
tpHL
tPLH
IpHL
IPLH
IPHL
IpLH
IpHL
IpLH
tpHL
IpHL
'PLH
'PHL
FROM
TO
UNPUTI
(OUTPUTI
A
B
'290
TEST CONDITIONS
MIN
TYP
QA
32
42
QB
16
A
QA
A
QO
eL=15pF,
B
RL ; 40011,
QS
See Note 4
B
Qe
'293
MAX
TYP
32
42
UNIT
MAX
MHz
16
10
16
10
16
12
18
12
18
32
48
46
70
34
50
46
70
10
16
10
16
14
21
14
21
21
32
21
32
23
35
23
35
21
32
34
51
23
35
34
51
26
40
B
QO
Set-to-O
Any
26
40
QA,QO
20
30
QB,Qe
26
40
Sol-'0-9
MIN
ns
ns
ns
ns
ns
ns
ns
# f max = maximum count frequency
tpLH = propagation delay time, low-to-high-Ievel output
tpHL = propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-795
SN54LS290, SN54LS293, SN74LS290, SN74LS293
DECADE AND 4·BIT BINARY COUNTERS
schematics of inputs and outputs
EQUIVALENT OF EACH RESET INPUT
EQUIVALENT OF A AND B INPUTS
TYPICAL OF ALL OUTPUTS
Vee
Vee
Rl
V e e - - -....- -
R2
120n NOM
R3
20kn NOM
INPUT
INPUT--~II_4
_ _-
L - -......-OUTPUT
INPUT
A
B ('LS290)
B ('LS293)
~
~
r-
NOMINAL VALUES
Rl
R2
R3
10kn 10kn 10kn
6.7kn 6.7 kn 5 kn
15kn 15kn 10kn
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 5)
Input voltage: R inputs
A and B inputs
Operating free-air temperature range: SN54LS290, SN54LS293
SN74LS290,SN74LS293
Storage temperature range
C
CD
<
n'
CD
(I)
NOTE 5:
7V
7V
5.5V
_55°C to 125°C
oOe to 70°C
_65°C to 150°C
Voltage values are with respect to network ground terminal.
recommended operating conditions
SN74LS'
SN54LS'
MIN
Supply voltage, Vee
4.5
Low-level output current, IOL
Pulse width, tw
MIN
5.5
4.75
4
32
A input
0
B input
A input
0
15
B input
30
30
Reset inputs
30
30
Reset inactive-state setup time, tsu
25
Operating free-air temperature. T A
-55
2-796
5
MAX
-400
High-level output current, IOH
Count frequency, fcount
NOM
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TEXAS 75285
16
NOM
5
MAX
5.25
V
-400
8
I'A
rnA
0
32
0
15
16
0
MHz
n'
n,
25
125
UNIT
70
°e
SN54LS290. SN54LS293. SN74LS29l SN74LS293
DECADE AND 4·BIT BINARY COUNTERS
electrical characteristics over recommended operating free·air temperature range (unless otherwIse noted)
PARAMETER
TEST CONDITIONSt
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
Input current
input voltage
Any reset
Vee= MIN,
II = -18 mA
Vee-MIN,
VIH=2V,
VIL""VILmax,
10H =-400IlA
Vee = MIN,
VIH = 2 V,
IIOL=4mA~
0.25
A input
input current
B of 'LS290
Low-level
A input
input current
B of 'LS290
0:4
0.5
0.1
0.2
0.2
Vee = MAX,
VI = 5.5 V
0.4
0.4
0.2
0.2
Vee= MAX,
VI = 2.7 V
Vee = MAX,
VI = 0.4 V
-20
Short-circuit output current§ Vee = MAX
Supply current
0.25
VI- 7 V
B of 'LS293
ICC
0.4
I 'LS290
I 'LS293
See Note 3
Vee = MAX,
V
V
0.1
20
20
40
40
80
80
40
40
-0.4
-0.4
-2.4
-2.4
-3.2
-3.2
-1.6
-1.6
-100
V
V
Vee- MAX,
B of 'LS293
High-level
-1.5
3.4
0.35
A input
B of 'LS290
UNIT
V
\IOL = 8 mA~
VIL = VIL max
MAX
0.8
2.7
3.4
Any reset
lOS
TVP+
-1.5
2.5
B of 'LS293
IlL
MIN
2
Any reset
IIH
SN74LS'
MAX
0.7
VOL Low-level output voltage
at maximum
TVPt
2
VOH High-level output voltage
II
SN54LS'
MIN
-20
-100
9
15
9
15
9
15
9
15
mA
IlA
rnA
(I)
Q)
CJ
mA
'S
rnA
o
Q)
..J
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°C.
....
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
~QA outputs are tested at specified IOL plus the limit value of IlL for the B input, This permits driving the B input while maintaining full
t--
fan-out capability.
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.
switching characteristics, Vee
PARAMETER#
f max
tPLH
tpLH
tPLH
TO
(OUTPUT)
A
°A
Os
S
A
A
S
B
tpLH
tpHL
TVP
32
42
'LS293
MAX
16
00
RL
Os
= 15 pF,
= 2 kQ,
°c
TVP
32
42
MAX
MHz
16
10
°A
UNIT
MIN
16
10
16
12
18
12
18
32
48
46
70
34
50
46
70
10
16
10
16
14
21
14
21
21
32
21
32
23
35
23
35
21
32
34
51
B
00
23
35
34
51
Set-to-O
Any
26
40
26
40
°A,OO
20
30
OS, DC
26
40
tpHL
tpHL
MIN
See Note 4
tPHL
tpLH
'LS290
TEST CONDITIONS
eL
tPHL
tpLH
5 V, T A = 25° e
IINPUTI
tpHL
tpHL
=
FROM
Set-to-9
ns
ns
ns
ns
ns
ns
ns
#f max = maximum count frequency
tpLH = propagation delay time, low-to-high-Ievel output
tpHL = propagation delay time. high-to-Iow-Ievel output
NOTE 4: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-797
-of
-of
r-
C
(1)
<
n'
(1)
VI
2-798
SN54LS292, SN54LS294, SN74LS292, SN74LS294
PROGRAMMABLE FREOUENCY DIVIDERS/DIGITAL TIMERS
02628. JANUARY 1981 - REVISED MARCH 1988
SN54LS292 .•• J OR W PACKAGE
SN74LS292 ..• N PACKAGE
• Count Divider Chain
• Digitally Programmable from ~ to 2"
In = 31 for 'LS292, n = 15 for 'LS294)
ITOPVIEW)
B
E
TP 1
ClK 1
CLK2
TP2
• Useable Frequency Range from DC to 30 MHz
• Easily Expandable
• Applications
• Frequency Division
• Digital Timing
0
TP3
NC
ClR
A
NC
Q
GND
description
These programmable frequency dividers/digital timers
contain 31 flip-flops plus 30 gates ('lS292) or 15 flipflops plus 29 gates ('lS294) on a single chip. The count
modulo is under digital control of the inputs provided.
Both types feature an active-low clear input to initialize
the state of all flip-flops. To facilitate incoming inspection, test points are provided (TP1, TP2, and TP3 on the
'lS292 and TP on the 'lS294). These test points are not
intended to drive system loads. Both types feature two
clock inputs; either one may be used for clock gating.
(See the function table below.)
A brief look at the digital timing capabilities of the
'lS292 will show that with a l-MHz input frequency,
programming for 21 0 will give a period of 1 .024 ms, and
220 will give a period of 1 .05 sec, 226 will give a period
of 1.12 min, and 2 31 will give a period of 35.79 min.
SN54LS292 .•• FK PACKAGE
(TOPVIEWI
U
U U
wmz>u
321
TP 1
ClK 1
NC
ClK2
TP2
ClK1
ClK2
a OUTPUT MOOE
L
X
X
Cleared to L
H
t
L
Count
H
L
t
Count
H
H
X
Inhibit
X
H
Inhibit
TP3
NC
NC
ClR
In
Q)
Co)
'S
Q)
o
ocuu<
zzz
(!l
SN54LS294 •.• J OR W PACKAGE
SN74LS294 ..• N PACKAGE
-'
tt-
(TOP VIEWI
VCC
C
0
NC
NC
ClR
NC
NC
B
A
TP
ClK 1
ClK2
NC
FUNCTION TABLE
CLEAR
o
4
5
9
These devices are easily cascadable giving limitless
possibilities to timing delays that can be achieved.
H
VCC
C
Q
GND
SN54LS294 ••• FK PACKAGE
(TOP VIEWI
u
UU
u
TP
ClK 1
NC
ClK2
NC
ocuuu
zzzz
(!l
NC -
No interna I connection.
PRODUCTION DATA documents contain information
currut I. of publication date. Products conform to
spacificltiDDS par the tarms af rexas Instruments
=~~:~~i;·r::1~7e ~!:~:~ti:; :.~o;:~::::~:~~ not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-799
SN54LS292, SN54LS29' SN14LS29t SN14LS294
PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS
schematics of inputs and outputs
TYPICAL OF Q OUTPUTS
EQUIVALENT OF EACH INPUT
TYPICAL OF TP OUTPUTS
- -.....-VCC
VCC---_--
OUTPUT
INPUT
--~
-.-:J......- ....OUTPUT
elK: Req = 10 kll NOM
All others: Req = 20 kG NOM
operation
The functional block diagram shows that the count modulo is controlled by an XIV decoder connected to the mode control inputs of several flip-flops. These flip flops with mode controls each have a "0" input connected to the parallel clock line and a
"T" input driven by the preceding stage. The parallel clock frequency is always the input frequency divided by four.
The XIV decoder output selected by the programming inputs goes low. While a mode control is low, the "0" input of that
flip-flop is enabled, and the signal from the parallel clock line (fin + 4) is passed to the "T" input of the following stage. All the
other mode controls are high enabling the "T" inputs and causing each flip-flop in turn to divide by two.
PARAllEL CLOCK
----t, - - - - ACTIVE·lOW CLEAR
OUTPUT OF
PRECEDING
STAGE
-,,-1
n =01
[n'" 1]
A (10)
B (I)
C (IS)
0(14)
E (2)
[1;[
[TPll
[TP2[
[TP31
},* to=~
(3)
(6)
(13)
TPI
TP2
TP3
ClKl (4)
ClK2 (5)
[to]
R
;>1
[n = 01
[n = II
(7)
a
B (1)
C (15)
0(14)
[TPI
I;j
A (2)
~fo"'2o
:}nl*
tThese symbols are in accordance with ANSI/IEEE Std 91·1984 and IEC Publication 617·12.
Pin numbers shown are for J, N, and W packages.
2-800
[1;1
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
(31
(7)
TP
Q
SN54LS29t SN54LS29' SN74LS29t SN74LS294
PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS
logic diagram (positive logic)
'LS292
(11)
ClKl
~A
R
R
~TO>T
ClK2 (5)
x/v
R....
,W -
R
20 R
T
C~2TC~T
28
~
-
26
24
cO> C> co>
C>
~ TPl
T T
I~
20 R
en
~
Q)
CJ
R
'S;
..(J>2TC~T
22
M2
Q)
C~
cpo
P
20
18
16
\.!.!.2!.
A
C
C
c
>
c
~
0>
~.
TP2
..J
t-
I-
s.ill. _ 2
T T
C~ I-- 4
16 6R
20 R
0.!.!.1! I-- 8
E.E!.
-
16
..(J>2TC~T
14
C~
M2
C~
12
10
8
~OR
cO> C> CO>'2T
~.TP3
~
T
+
-C>T
6
4
2
20
R
C>2TCPT
-M2
C
P
C
20 R
poO
S
3D
> 2T C >3T
~
~Q
~
Pin numbers shown are for J. N, and W packages.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-801
SN54LS292, SN54LS294, SN74LS292, SN74LS294
PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS
logic diagram (positive logic)
'LS294
(11)
ClKl
~ff
ClK2 (5)
P.TCPOT
XIV
oW
lP-
25"R
f-o >
~
14
13
12
11
10
-i
-i
r
,...EL..
A
C
Bi~2
n'
CD
c:~4
en
I-"-'l.
C
"--p.
'-'
i,-I
~>
____Cp.
.....
1-"-'
~~~~
9
1
CD
<
i,-I
2TCpo
8
~R ~
o.~8
.....
2T
M2 Cp.
...
"-C>
--0>
......
'-C>
7
6
5
4
3
-
TP
I~
_
3bS
O>3T~Q
----
-M3
2
Pin numbers shown are for J, N, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
Operating free·air temperature range: SN54LS292, SN54LS294 . . . . . . . . . . . . . . . . . . . . . . .. _55°C to 125°C
SN74LS292, SN74LS294 . . . . . . . . . . . . . . . . . . . . . . . . . .. oOe to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _65°C to 150°C
NOTE1: Voltage values are with respect to network ground terminal.
2-802
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54LS292, SN54LS294, SN74LS292, SN74LS294
PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS
recommended operating conditions
SN54LS'
MIN
4,5
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current (Q only)
SN74LS'
NOM
MAX
MIN
NOM
MAX
5
5,5
4.75
5
5.25
2
IOL
Low-level output current (0 only)
fclock
tw
Clock frequency
tw
Duration of clear pulse
tou
TA
Clear inactive-state setup time
Operating free-air temperature
2
0.8
.,-1.2
12
Duration of clock input pulse
30
0
16
16
I'LS292
55
55
I'LS294
35
35
15
15
-55
125
V
V
0.7
-1,2
0
UNIT
V
mA
24
mA
30
MHz
ns
ns
0
70
ns
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)'
PARAMETER
VIK
VOH
Q
VOL
TP'
II
IIH
eLK1.eLK2
IOS§
lee
Vee=MIN.
11=-18mA
Vee = MIN.
VIH=2V.
MIN
All others
Vee= MIN.
IIOL=12mA
VIH =2V.
I IOL = 24 mA
VIL = MAX
Vee=MAX,
Vee= MAX,
V
Vee=MAX,
2.4
SN74LS'
MAX
3.4
0.25
MIN
TYP*
2.4
OA
3A
VI =OAV
OA
0.35
0.5
'LS292
All" i~puts grounded,
Vee = MAX,
All outputs open
-30
V
mA
20
-0,8
20
I'A
-0.8
-0.4
mA
-130
mA
-30
40
75
40
75
30
50
30
50
Q)
CJ
'S:
C
...I
0.4
0.1
-130
o
Q)
V
0.1
-0.4
Vee= MAX
UNIT
V
0,25
0.25
VI =2,7V
MAX
-1.5
I IOL = 0,5 mA
VI =7 V
Q
'LS294
TYP*
-1.5
IOH = - 1,2 mAo
VIL = MAX
Q
IlL
SN54LS'
TEST CONDITIONSt
~
~
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee = 5 V, TA = 25°e,
§ The duration of the short-circuit should not exceed one second.
, The TP output or outputs are not intended to drive external loads but are solely provided for test points.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-803
SN54LS29t SN54LS29' SN74LS292. SN74LS294
PROGRAMMABLE FREOUENCY DIVIDERS/DIGITAL TIMERS
switching characteristics.
Vee ..
V.
5
T A ... 25 o e. RL
n. eL
667
FROM
TO
(INPUT)
(OUTPUT)
CLK1 or 2
Q
Modulo set at 22,
Q
A thru E = LLLH L ('LS292)
A thru D = LLHL ('LS2941
= 45 pF (see Figure 1)
'LS292
'LS294
TEST CONOITIONS
PARAMETERt
UNIT
MIN
TYP
30
50
f max
tPLH
tpHL
Q
CLR
tpHL
MAX
MIN
TYP
30
50
MAX
MHz
55
90
55
90
ns
80
120
80
120
ns
85
130
35
65
ns
t fMAX = maximum clock frequency
tPLH = Propagation delay time, low-to-high-Ievel output
tpHL = Propagation delay time, high-to-Iow-Ievel output
NOTE 2: load circuits and voltage waveforms are shown in Section 1. To be used on TP outputs only.
'LS292 FUNCTION TABLE
FREQUENCY DIVISION
PROGRAMMING
Q
INPUTS
TP3
TP2
TPl
-I
-I
r-
E
D
C
B
A
BINARY
L
L
L
L
L
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
oCD
L
L
L
L
H
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
L
L
L
H
L
22
L
L
L
H
H
23
8
L
L
H
L
L
16
L
L
H
L
H
~
25
L
L
H
H
L
L
L
H
H
H
L
H
L
L
L
L
H
L
L
H
L
H
L
H
L
<
Cr
CD
I/)
2-804
26
27
28
29
DeCIMAL
4
32
64
128
256
512
L
H
L
H
H
2 10
211
L
H
H
L
L
212
4,096
L
H
H
L
H
L
H
H
H
L
2 13
214
16,384
1,024
2,048
8,192
L
H
H
H
H
H
L
L
L
L
2 15
216
65,536
32,768
H
L
L
L
H
217
131,072
H
L
L
H
L
262,144
H
L
L
H
H
2 18
2 19
524,288
H
L
H
L
L
220
1,048,576
H
L
H
L
H
221
2,097,152
H
L
H
H
L
222
4,194,304
H
L
H
H
H
H
H
L
L
L
2 23
224
16,777,216
225
226
8,388,608
DECIMAL
BINARY
DECIMAL
BINARY
DECIMAL
Inhibit
Inhibit
512
217
131,072
224
16,777,216
512
217
131,072
224
16,777,216
512
217
131,072
224
16,777,216
512
217
131,072
224
16,777,216
29
29
512
217
131,072
224
16,777,216
512
217
131,072
224
16,777,216
29
29
512
217
131,072
22
512
217
131,072
22
4
29
29
512
131,072
24
16
512
217
217
131,072
24
16
29
29
512
217
131,072
64
512
217
131,072
26
26
29
29
512
Disabled Low
512
29
29
512
Disabled Low
23
23
29
29
29
29
28
28
4
64
256
256
32
512
25
25
2 10
2 10
212
32
212
4,096
512
27
128
214
16,384
27
128
214
16,384
29
29
512
2 16
216
65,536
262,144
512
29
29
512
29
29
512
Disabled Low
Disabled Low
211
8
8
512
1,024
1,024
4,096
65,536
23
23
8
8
211
2,048
2 18
2 18
32
2 13
2 13
8,192
220
1,048,576
8,192
32,768
2 20
222
4,194,304
2,048
H
H
L
L
H
H
H
L
H
L
H
H
L
H
H
227
134,217,728
25
25
H
H
H
L
L
268,435,456
27
128
H
H
H
L
H
2 28
2 29
536,870,912
27
128
215
2 15
32,768
222
4,194,304
H
H
H
H
L
1,073,741,824
512
217
131,072
224
16,777,216
H
H
H
H
H
29
29
512
217
131,072
224
16,777,216
230
231
33,554,432
BINARY
67,108,864
2,147,483.648
32
TEXAS
.Jf
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
262,144
1,048,576
SN54LS292, SN54LS294, SN74LS292, SN74LS294
PROGRAMMABLE FREQUENCY DIVIDERS/DIGITAL TIMERS
'LS294 FUNCTION TABLE
FREQUENCY DIVISION
TP
Q
PROGRAMMING INPUTS
D
C
B
A
BINARY
DECIMAL
BINARY
DECIMAL
L
L
L
L
Inhibit
Inhibit
Inhibit
Inhibit
L
L
L
H
Inhibit
Inhibit
Inhibit
Inhibit
L
L
H
L
22
L
L
H
H
23
4
8
16
32
64
128
256
512
1,024
2,048
4,096
8,192
16,384
32,768
29
29
29
29
29
512
512
512
512
512
L
H
L
L
24
L
H
L
H
25
L
H
H
L
~
L
H
H
H
H
L
L
L
H
L
L
H
27
28
29
2 10
211
212
H
L
H
L
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
213
214
2 15
Disabled Low
22
23
24
25
26
27
28
29
4
8
16
32
64
128
256
512
II)
Q)
(J
·S
Q)
switching loads
C
...J
I-I--
FROM OUTPUT
UNDER TEST
FIGURE 1
'LS292 and 'LS294 timing diagram
CLK1
L
~
____________~r-
CLK2------------------------------------~
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-805
-i
-i
r-
o
(1)
<
o(1)
VI
2-806
SN54LS295B, SN74LS295B
4·BIT RIGHT·SHIFT LEFT·SHIFT REGISTERS
WITH 3·STATE OUTPUTS
OCTOBER 1976 - REVISED MARCH 1988
SN54lS295B ... J OR W PACKAGE
SN74lS295B •.. 0 OR N PACKAGE
• 'LS295B Offers Three limes the
Sink·Current Capability of 'LS296A
(TOP VIEW)
• Schottky·Diode·Clamped Transistors
SER
A
B
C
D
LD/SH
GND
• Low Power Dissipation ... 80 mW Typical
(Enabled)
• Applications:
N-Bit Serial-To-Parallel Converter
N-Bit Parallel-To-Serial Converter
N-Bit Storage Register
VCC
QA
OB
Oc
OD
ClK
OC
description
SN54lS295B ... FK PACKAGE
(TOP vIew)
These 4-bit registers feature parallel inputs, parallel outputs, and clock (ClKI. serial (SERI, mode (LD/SH),
and outputs control (OC) inputs. The registers have
three modes of operation:
ffiutl«
«ooZ>O
Parallel (broadside) load
Shift right (the direction QA toward QD)
Shift left (the direction QD toward QA)
3
2 1 20 19
4
5
6
7
Parallel loading is accomplished by applying the four bits
of data and taking the mode control input high. The data
is loaded into the associated flip-flops and appears at the
outputs after the high-to-Iow transition of the clock input. During parallel loading, the entry of serial data is
inhibited.
QB
NC
Qc
NC
8
I/)
Q)
(J
'S
QD
Q)
9 10111213
I~ ~ ~
c
'V
(13)
aA
(12)
aB
ac
(11)
(10)
00
tThis symbol is in accordance with ANSIIIEEE Std. 91-1984 and lEe
Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-807
SN54LS295B, SN74LS295B
4·BIT RIGHT·SHIFT LEFT·SHIFT· REGISTERS
WITH 3·STATE OUTPUTS
logic diagram (positive logic)
DATA INPUTS
/~--A------------B----~A~-----C--~--------D~
m
w
m
~
1101
~~--------~~--~vr----~----------~
OUTPUTS
Pin numbers shown are for 0, J, N, and W packages.
schematics of inputs and outputs
EQUIVALENT OF SERIAL
AND DATA INPUTS
EQUIVALENT OF ClK,
LDiSH,AND
OelNPUTS
TYPICAL OF All OUTPUTS
----_e_-Vee
Vee
INPUT
~f
Vee--_-Req
U'
~"
20kn NOM
I NPUT_'*......----1r
.:It?
.Jf,
n
Serial: Req = 30 kn NOM
A,B,C, D: Req = 20 kn NOM
2-808
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, :rEXAS 75265
OUTPUT
SN54LS295B. SN74LS295B
4·BI1 RIGHT·SHIFT LEFT·SHIFT REGISTERS
WITH 3·STATE OUTPUTS
FUNCTION TABLE
INPUTS
OUTPUTS
PARALLEL
LO/SH
CLK
H
H
X
H
X
H
+
+
X
L
H
X
Qat
X
l
+
+
H
X
l
X
l
SER
QB
QBO Oco QOO
b
c
d
B
C
D
X
X
X
X
QAO
a
b
c
d
a
A
Qct Qot
X
X
X
X
X
X
Oc
QA
QD
d
Qan Ocn QDn
QAO QBO QCO 000
H
QAn Qan QCn
l
QAn QBn Ocn
d
X
X
X
When the output control i. low. the outputs ar. disabled to the hlgh-impedanC8Itata;
however. sequential operation of the registers Is not affected.
fShifting left requires external connection of
entered at input D.
aS to A, QC to B. and 00 to C. Sari a' data Is
(steadY state), L = low level (steady state), X = irrelevant (any input, including transitions)
~ ... tr8nsltion from high to low laval.
8, b, c, d .... the leval of steady-stata input at inputs A, B, C, or D, respectively.
QAO, aBO. Qco. 000"" the leval of QAf aS. Qc. or GO. respectively, before the indicated steady-state input condition. ware established.
QAn. 0So_ Oen. aDo = the laval of QAf Oa. Cle, or 00. respectively. before the most-recent J. transition of the clock_
H
= high level
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
]V
Supply voltage, VCC (see Note 1) . . . . . . .
I nput voltage . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS295B
SN74LS295B
Storage temperature range
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
NOTE 1: Voltage valu•• are with respect to network ground terminal.
recommended operating conditions
SN54LS295B
VCC
SupplV valtage
IOH
High-level output current
SN74LS29&B
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-2.6
mA
24
30
mA
MHz
-1
IOl
Low-level output current
fclock
Clock frequency
tw(clock)
Width of clack pulse
16
16
ns
tsu
Setup time, high-level or low-level data
20
20
ns
tsu
Setup time, lD/SH ta ClK
th
Hald time, high-level ar law-level data
th
Hald time, high-level ar law-level lO/SH ta ClK
Operating free-sir temperature
TA
12
0
.
30
0
I
high-level
25
25
I
low-level
30
30
20
20
0
0
-55
125
0
ns
ns
70
ns
·C
~
TEXAS "V
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
2·809
SN54LS295B, SN74LS295B
4·BIT RIGHT·SHIFT LEFT·SHIFT REGISTERS
WITH 3·STATE OUTPUTS
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
TEST eONDITIONst
PARAMETER
VIH
High~level
input voltage
Vil
Low~level
input voltage
VIK
Input clamp voltage
Cfj
2
10H= MAX
VIH-2V,
V
-1.5
-1.5
V
3.4
2.4
0.25
II0l = 12 mA
Vee = MAX,
0.4
IIOL =24mA
VIL = VIL max,
VIH-2V,
VO=0.4V
Input current at
V
0.8
V
3.1
0.25
0.4
0.35
0,5
V
20
20
IJA
-20
~20
IJA
Vee = MAX,
VI =7 V
0.1
0.1
mA
IIH
High-Ievellnput current
Vee = MAX,
VI =2.7V
20
20
IlL
LOW-level input current
Vee = MAX,
VI = 0.4 V
-0.4
-0.4
IJA
mA
lOS
Short-circuit output current §
Vee = MAX
ICC
Supply current
Vee = MAX,
II
c:r
= Vil max,
2.4
SN74lS295B
UNIT
TYP; MAX
MIN
0.7
VO= 2.7 V
10ZL low.level voltage applied
(1)
VIH=2V,
Vee = MAX,
Off-state outpu.t current,
<
Vee=MIN,
Vil = Vil max
Off-state output current,
(1)
11--18mA
Vee = MIN,
10ZH high.level voltage applied
C
Vee=MIN,
Vil
VOL Low-level output voltage
r-
TYP:j: MAX
2
VOH High·level output voltage
-I
-I
SN54lS295B
MIN
maximum input voltage
-30
See Note 2
ICondition A
20
-130
29
ICondition B
22
33
-30
20
-130
29
22
33
mA
rnA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time,and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with the outputs open, the serial input and mode control at 4.5 V, and the data inputs grounded under the following
conditions:
A. Output control at 4.5 V and a momentary 3 V, then ground, applied to clock input.
B. Output control and clock input grounded.
switching characteristics, Vee
= 5 V, TA = 25 e, RL = 667 n.
TEST CONDITIONS
PARAMETER
f max Maximum clock frequency
tpLH Propagation delay time, low·to·high·level output
MIN
TYP
30
45
MAX UNIT
MHz
14
20
ns
19
30
ns
tpZH Output enable time to high level
18
26
ns
tPZL Output enable time to low level
20
30
ns
20
20
ns
eL = 45 pF,
tpHL Propagation delay time, high·to-Iow·level output
See Note3
tpHZ Output disable time from high level
eL = 5 pF,
13
tpLZ Output disable time from low level
See Note 3
13
NOTE 3: Load circuits and voltage waveforms are show!l in Section 1.
2-810
TEXAS . "
INSTRUMENTS
POST OFFICE
-sox 655012
• DALLAS, TEXAS 75265
ns
SN54LS297. SN74LS297
DIGITAL PHASE·LOCKED·LOOP FILTERS
02629, JANUARY 1981 - REVISED MARCH 1988
SN54LS297 ... J OR W PACKAGE
SN74lS297 ... N PACKAGE
• Digital Design Avoids Analog
Compensation Errors
(TOP VIEW)
• Easily Cascadable for Higher Order Loops
B
A
• Useful Frequency from DC to:
50 MHz Typical (K Clock)
36 MHz Typical (I/O Clock)
VCC
C
ENCTR
K ClK
liD ClK
description
0
gJA2
ECPO OUT
XORPO OUT
gJB
DIU
liD OUT
The SN54lS297 and SN74lS297 devices are designed
to provide a simple, cost-effective solution to highaccuracy, digital, phase-locked-loop applications. These
devices contain all the necessary circuits, with the exception of the divide-by-N counter, to build first order
phase-locked loops as described in Figure 1.
GNO '-1.::._-"J..... gJA 1
SN54lS297 ... FK PACKAGE
ITOP VIEW)
U
Both exclusive-OR (XORPO) and edge-controlled
(ECPO) phase detectors are provided for maximum
flexibility,
Proper partitioning of the loop function, with many of
the building blocks external to the package, makes it
easy for the designer to incorporate ripple cancellation or
to cascade to higher order phase-locked loops.
U
U
<(102)U
3 2
ENCTR
U)
Q)
liD ClK
CJ
·S
DIU
9 10111213
The length of the up/down K counter is digitally proCCU-IO
grammable according to the K counter function table.
:::::~2~&
With A, B, C, and 0 all low, the K counter is disabled.
NC-No internal connection
With A high and B, C, and 0 low, the K counter is only
three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C, and 0
are all programmed high, the K counter becomes seventeen stages long, which narrows the bandwidth or capture range and
lengthens the lock time. Real-time control of loop bandwidth by manipulating the A thro.ugh D inputs can maximize the overall
perfor..,ance of the digital phase-locked loop.
Q)
C
...I
~
~
MODULO CONTROLS
,D-e"B- .A.
K-COUNTER
141
CLOCK
:61
DOWN/UP CONTROL
K-COUNTER
131
ENABLE
I/O CLOCK
PHASE A1
151
171
HI----'-'-I/D OUTPUT
191
1101
PHASE B
PHASE A2
1131
FIGURE l-SIMPLIFIED BLOCK DIAGRAM
Pin numbers shown are for J, Nand W packages.
PROOUCTIOM DATA d...ma_contain informati••
• arrant .s of publicatio. data. Prodacts .onform to
spacificatiDRS ... the tarm. If TIXII Instruments
::'~~~~·i:~7.; ~::\:~i::
.ot
lll-::::=:'::'"
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-811
SN54LS297, SN74LS297
DIGITAL PHASE·LOCKED·LOOP FILTERS
description (continued)
The 'LS297 can perform the classic first-order phase-locked loop function without using analog components. The accuracy
of the digital phase-locked loop (OPLL) is not affected by VCC and temperature variations, but depends solely on accuracies
of the K clock, 110 clock, and loop propagation delays. The 110 clock frequency and the divide-by-N modulos will determine
the center frequency ofthe OPLL. The center frequency is defined by the relationship fc = 110 Clock12N (Hz).
logic diagram (positive logic)
A (2)
r - - - - - - - - - - - - - - - - - - - - Ki:OUNTER - - - - - - - - - - - - - -
8 (1)
c +i(1~51-"'1-':'::::::::~
-I
I
I
XIV
1
D~
I
I
KCLK"(4:1._1-_ _ _......~--...,
-I
-I
ENCTR (31
I
r-
I
I
C
I
CD
I
<
n'
CD
(I)
L _______
I
I/DCLK(51
-----------------------~~~~---I/O CIRCUIT
I
I
I
I
I
I
I
I
I
I
I
I
I
i--------------Ex~~~oo~~~mroR----------1
.Al"'(9.:..1---ir-...
I
----r---.
>-_______________________~Ir_(~I~II~~~PD
08 (101
----------------------------------~I
. -_ _ _ _ _ _ _ _ _ _ _ _E_D,GE.CONTROLLED PHASE DETECTOR
I
I
oA2
"'"'(13~1-r-_r~~-=::~-L~
~-----------------------------------~
Pin numbers shown are for J, N. and W packages.
2-812
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
(121 ECPD
OUT
SN54LS297, SN74LS297
DIGITAL PHASE·LOCKED·LOOP FILTERS
FUNCTION TABLE
K COUNTER FUNCTION TABLE
EXCLUSIVE·OR PHASE DETECTOR
(OIGITAL CONTROL I
XORPDOUT
D
C
B
A
MODULO (KI
L
L
L
Inhibited
"'A1
L
B
L
L
L
L
L
L
H
23
L
H
H
L
L
H
L
:z4
H
L
H
L
L
H
H
25
H
H
L
L
H
L
:z6
L
H
L
L
H
L
H
H
L
28
29
FUNCTION TABLE
27
EDGE-CONTROLLED PHASE DETECTOR
q,A2
B
H or L
I
H
H
2 10
211
I
H or L
H
L
212
H or L
t
L
No change
L
H
H
H or L
No change
L
L
2 13
214
t
H
H
L
H
H
H
L
H
H
H
L
H
H
H
H
L
L
L
H
L
L
H
L
H
H
H
H
H
ECPDOUT
H == steady-state high level
L "" steady-state low level
l "" transition from high to low
2 15
2 16
217
t
= transition
from low to high
U)
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
Q)
(.)
TYPICAL OF I/D OUTPUT
VCC - - - - _ - -
VCC
1000NOM
"S;
TYPICAL OF
ECPD AND XORPD OUTPUTS
- - - - -...- - VCC
1200NOM
Q)
o
...I
lI-
I NPUT-.--:-l......- _
'l...a/l~-- OUTPUT
A, B, C, D, 1/>A2: Req
",s: Req
'I...~""-- OUTPUT
= 20 kO NOM
= 6 kO NOM
All others: Req = 10 kO NOM
operation
The phase detector generates an error signal waveform that, at zero phase error, is a 50% duty cycle square wave. At
the limits of linear operation, the phase detector output will be either high or low all of the time, depending on the
direction of the phase error ("'in - "'out). Within these limits, the phase detector output varies linearly with the input
phase error according to the gain kd' which is expressed in terms of phase detector output per cycle of phase error,
The phase detector output can be defined to vary between ±1 according to the relation:
PO Output _ % high - % low
(1)
100
The output of the phase detector will be kd "'e, where the phase error "'e = 4>in - 4>out.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2·813
SN54LS297, SN74LS297
DIGITAL PHASE·LOCKED·LOOP FILTERS
Exclusive-OR .phase detectors (XORPD) and edge-controlled phase detectors (ECPD) are commonly used digital types.
The ECPD is more complex than the XORPD logic function, but can be described generally as a circuit that changes
states on one of the transitions of its inputs. kd for an XORPD is 4 because its output remains high (PD output = 1)
for a phase error of 1/4 cycle. Similarly, kd for the ECPD is 2 since its output remains high for a phase error of 112
cycle. The type of phase detector will determine the zero-phase-error point, i.e., the phase separation of the phase
detector inputs for q,e defined to be zero. For the basic DPll system of Figure 2, q,e = 0 when the phase detector
output is a square wave. The XORPD inputs are 1/4 cycle out of phase for zero phase error. For the ECPD, q,e = 0
when the inputs are 1/2 cycle out of phase.
r - -----------------,
KCLK
I
I ON
DIVIDE-BY-N
COUNTER
CARRY
I
BORROW
I
I
II
fin,ot>in - - - - - -.....=.;....-~
I
I
I
-t
-t
r-
C
I/DCLK
I
out - - _.....~....- - - - I
CD
en
FIGURE 2-DPLL USING EXCLUSIVE-OR PHASE DETECTION
The phase detector output controls the up/down input to the K counter. The counter is clocked by input frequency
Mfc , which is a multiple M of the loop center frequency f c . When the K counter recycles up, it generates a carry pulse.
Recycling while counting down generates a borrow pulse. If the carry and borrow outputs are conceptually combined
into one output that is positive for a carry and negative for a borrow, and if the K counter is considered as a frequency
divider with the ratio Mfc/K, the output of the K counter will equal the input frequency multiplied by the division
ratio. Thus the output from the K counter is (kd ot>eMfcl/K.
The carry and borrow pulses go to the increment/decrement (I/D) circuit, which, in the absence of any carry or
borrow pulse, has an output that is 112 of the input clock I/D ClK. The input clock is just a multiple, 2N, of the loop
center frequency. In response to a carry or borrow pulse, the I/D circuit will either add or delete a pulse at I/D OUT.
Thus the output of the I/D circuit will be Nfc + (kdot>eMfclI2K.
The output of the N counter (or the output of the phase-locked loop) is thus:
If this result is compared to the equation for a first-order analog phase-locked loop, the digital equivalent of the gain
of the VCO isjust Mfc/2KN or fc/K for M = 2N.
Thus the simple first-order phase-locked loop with an adjustable K counter is the equivalent of an analog phase-locked
loop with a programmable VCO gain.
2-814
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54LS297, SN74LS297
DIGITAL PHASE-LOCKED-LOOP FILTERS
r------------------,I
_ _ _ _ _ _ _~I~K~C~L~K~--b
Mfe
I
DIU
CARRY
I ENCTR
I
I
I
DIVIDE-BY-K
COUNTER
BORROW
XORPDOUT
:
I
I
I
fout, ¢Out --I----~a-I~...-.j.../
I
I
<'I---.--+--
2Nfc
en
FIGURE 3-0PLL USING BOTH PHASE OETECTORS IN A RIPPLE-CANCELLATION SCHEME
Q)
(.)
absolute maximum rating over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) _______________________________________________________________ 7 V
Input voltage _______________________________________________________________________________ 7 V
Operating free-air temperature range: SN54LS297 _______________________________________ - 55° e to 125° C
SN74LS297 ___________________________________________ 0° e to 70° e
Storage temperature range __________________________________________________________ - 65° e to 150° C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS297
VCC
Supply voltage
output current
IOH
High~'evel
IOL
Low-level output current
fcrock
Clock frequency
tw
Width of clock input pulse
tsu, to K
th
TA
SN74LS297
MIN
NOM
MAX
MIN
NOM
MAX
4_5
5
5_5
4_75
5
5_25
UNIT
V
110 OUT
-1.2
-1.2
EXOR, ECPO
-400
-400
/-IA
12
24
mA
I/O OUT
4
XOR, ECPO
K Clock
I/O Clock
0
32
0
16
0
0
mA
8
mA
32
MHz
16
MHz
K Clock
16
16
ns
110 Clock
33
33
ns
Setup time to K Clock t
U/i), ENCTR
30
30
ns
t
Operating free-air temperature
U/i'i, ENCTR
0
0
Hold time from K Clock
-55
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
125
0
ns
70
°c
2-815
'>
Q)
C
..;,J
lI-
SN54LS297. SN74LS297
DIGITAL PHASE·LOCKED·LOOP FILTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High~e"'l
VIL
Low·level input voltage
Input clamp voltage
VIK
VOH
VOL
SN54LS297
TEST CONOITIONSt
MIN
input voltage
High·le..,1
output voltage
VCC= MIN,
11=-18mA
110 OUT
VCC=MIN,
VIH = 2 V,
Others
VIL = VILmax
SN74LS297
TVP;
MAX
2
V
-1.5
-1.5
V
10H = MAX
2.5
2.7
0.4
10L = 24mA
0.25
V
0.8
2.4
0.25
UNIT
0.7
2.4
IOL =4 mA
V IL = VIL max
Others
MIN
IOH -MAX
10L -12mA
V IH =2V,
VCC= MIN,
output voltage
MAX
2
I/O OUT
Low·level
TVP;
0.4
10L =8mA
V
0.25
0.4
0.35
0.25
0.5
0.4
0.35
0.5
V
Input current at
II
maximum input
VCC=MAX,
VI
=7 V
0.1
0.1
mA
voltage
IIH
IlL
lOS
ICC
High·level
input current
Low-level
UID, EN,
___---'
schematics of inputs and outputs
'298
CD
<
(;'
EQUIVALENT OF EACH INPUT
CD
TYPICAL OF ALL OUTPUTS
-~-Vee
Vee--~-
tn
lOa!'! NOM
INPUT
OUTPUT
Clock: Req = 4 k!'! NOM
All other inputs: Req = 6 k!'! NOM
'LS298
EQUIVALENT OF DATA INPUTS
VCC
-
EQUIVALENT OF OTHER INPUTS
-
Vec
17 k!'! NOM
15k!'! NOM
INPUT
-
INPUT
. r,
I"
-
~r
2-818
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54298, SN74298
QUADRUPLE 2·INPUT MULTIPLEXERS WITH STORAGE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
5.5V
-55°e to 125°e
O°C to 70°C
-65°C to 150°C
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
Operating free·air temperature range: SN54298
SN74298
Storage temperature
NOTE1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN74298
SN54298
Supply vol'age, Vee
MIN
NOM
4.5
5
MAX
MIN
NOM
5.5
4.75
5
-800
High-level output current, IOH
16
Low-level output current, tOl
Width of clock pulse, high or low level, tw
Data
Word select
Setup time, tsu
20
15
15
25
25
5
5
Hold time, th
Word select
5.25
V
"A
mA
n.
n.
n.
0
0
-55
Operating free-air temperature, T A
125
UNIT
-800
16
20
Data
MAX
0
70
°e
U)
Q)
(.)
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt
PARAMETER
VIH
High-level input voltage
VIL
VIK
Input clamp voltage
MIN
2
VOH High-level output voltage
VOL Low-level output voltage
II = -12mA
Vee =MIN,
VIH=2V,
VIL =0.8 V,
10H = -800 "A
Vee = MIN,
VIH= 2 V,
VIL = 0.8 V,
10L = 16mA
2.4
0.8
V
-1.5
V
0.4
lI-
V
1
mA
"A
mA
II
I "put current at maximum input voltage
Vee = MAX, VI = 5.5 V
High-level input current
Vee= MAX, VI - 2.4 V
40
IlL
Low-level input current
Vee-MAX, VI=O.4V
-1.6
lOS
Short-circuit output current§
Vee = MAX
ICC
Supply current
Vee = MAX, See Note 2
-20
-57
-18
-57
39
...I
V
3.2
IIH
I SN54298
I SN74298
Q)
Q
V
Low-level input voltage
Vce = MIN,
.S;
TYPt MAX UNIT
65
mA
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee;; 5 V, T A;; 25°C.
§Not more than one output should be shorted at a time.
NOTE 2: With all outputs open and all inputs except clock low, lec is measured after applying a momentary 4.5 V, followed by ground, to
the clock input.
switching characteristics, Vee = 5 V. TA = 25°e
PARAMETER
TEST CONDITIONS
I-"P"L",H~P::-r....
o.::cp.::;a9::.:a....
'i....o_n....d:-e-:,la....Y_'-:,im
....e.::;,-:lo
....w-:-,-'_0.-ch..:i9:..h-c.I_ev....e..,l_o_u..:'p....u_'_ _ _ _ _ _ _-l eL = 15 pF,
tpHL Propagation delay time, high-to-Iow-Ievel output
See Note 3
RL = 400 n,
MIN
TYP
MAX
18
27
21
32
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-819
SN54LS298. SN74LS298
QUADRUPLE 2·INPUT MULTIPLEXERS WITH STORAGE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . .
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS298
SN74LS298
Storage temperature range
7V
7V
-55°e to 125°e
oOe to 70°C
-65°C to'1500e
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS298
MIN
NOM
4.5
5
SupplV voltage. Vee~
High-level output current, 10H
..
SN'14LS298
MAX
MIN
NOM
5.5
4.75
5
-400
Low.level output current, IOL
20
Data
Word select
Data
Word select
Setup time, tsu
Hold tima, th
5.25
-400
4
Width of clock pulse, high or low level, tw
MAX
8
20
15
15
25
25
6
0
-55
5
UNIT
V
pA
mA
n•
ns
ns
0
70 'e
125
0
-I Operating free-air temperature, T A
-I
r- electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
oCD
PARAMETER
<
r;'
CD
en
VIH
High-level input voltage
VIL
Low~evel
VIK
Input clamp voltage
SN54LS298
TVP:> MAX
TEST CONDITIONSt
MIN
2
VOH High·level output voltage
VOL Low-level output voltage
II =-18mA
Vee- MIN,
VIH-2V,
0.7
-1.5
2.5
VIL = VIL max, IOH=-4oopA
Vee=MIN,
VIH-2V,
IIOL =4mA
VIL = VIL max
V
2
input voltage
Vee = MIN.
SN74LS298
UNIT
TVP; MAX
MIN
3.4
2.7
0.25
0.4
IIOL =8mA
0.8
V
-1.5
V
3.4
V
0.25
0.4
0.35
0.5
V
II
Input current at
maximum input voltage
Vee = MAX,
VI =7 V
0.1
0.1
mA
IIH
High-level input current
Vee = MAX,
VI=2.7V
20
20
pA
IlL
Low-level input current
Vee = MAX,
VI =0.4V
Short-circuit output current§
Vec=MAX
-0.4
-100
mA
lOS
ICC
Supply current
Vee = MAX,
21
mA
-0.4
-100
-20
See Note 2
13
-20
21
13
mA
tFor conditions shown 8S MIN or MAX, use the appropriate value specified under recommended operating condition,.
:tAli typical values are at Vee - 5 V, T A = 25° C.
§Not more than ana output should be shorted at 8 time, and duration of the short-circuit should not exceed one second.
NOTE 2: With all outputs open and all inputs except clock low, ICC is measured after applying a momentary 4.5 V. followed by ground, to
the clock input.
switching characteristics, Vee = 5 V, T A = 25° C
tPL
PARAMETER
Propagation delay time, low-to-high-Ievel output
TEST CONDITIONS
CL = 15pF,
tpHL Propagation delay time, high.tOolow-level output
See Note 3
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-820
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
RL = 2 kG,
MIN
TVP
18
MAX
27
21
32
SN54298, SN54LS298, SN74298, SN74LS298
QUADRUPLE 2·INPUT MULTIPLEXERS WITH STORAGE
TYPICAL APPLICATION DATA
This versatile multiplexer/register can be connected to operate as a shift register that can shift N·places in a single
clock pulse.
The following figure illustrates a BCD shift register that will shift an entire 4·bit BCD digit in one clock pulse.
PARALLEL LOAO
Ir.............................................JA~........................................~\
I
ILl
WS
WS
OA
A2
Bl '298
or OB
B2 'LS298
'-- Cl REG
OA-
A2
Bl '298
°BB2 'L~;98
..... Cl REG
1 0{;
C2
' - - 01
00
02
'--
~
CLOCK
I
l Al
C2
01
02
~
2
Dc
C~
00
l Al
-
A2
OA
A
'!'
~
OIGIT 1
WORO SELECT
.... Bl '298
or OB
B2'LS298
'--- Cl REG
3 0{;
C2
' - - 01
02 CK 0 0
.....
~
~
WS
en
Q)
.s:
(.)
~
0lGIT2
0lGIT3
Q)
o
When the word·select input is high and the registers are clocked, the contents of register 1 is transferred (shifted) to
register 2 and etc. In effect, the BCD digits are shifted one position. In addition, this application retains a parallel·load
capability which means that new BCD data can be entered in the entire register with one clock pulse. This arrangement
can be modified to perform the shifting of binary data for any number of bit locations.
..J
lI-
Another function that can be implemented with the '298 or 'LS298 is a register that can be designed specifically for
supporting multiplier or division operations. The example below is a one place/two·place shift register.
'181, 'LS181, or 'S181
'181, 'LS181, or 'S181
(ALU)
FO
Fl
F2
F3
(ALU)
FO
Fl
F2
Al A2Bl B2Cl C201 02
F3
Al A2 Bl B2 Cl C2 01 02
WS
CLOCK~~==~==~==~==~==~~ ,-~~====~==~==~==~WORO
SELECT
When word select is low and the register is clocked, the outputs of the arithmetic/logic units (ALU's) are shifted one
place. When word select is high and the registers are clocked, the data is shifted two places.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-821
2-822
SN54LS299, SN54S299, SN74LS299, SN74S299
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
MARCH 1974 - REVISED MARCH 1988
SN54LS299, SN54S299 ... J OR W PACKAGE
SN74LS299, SN74S299 .•• OW OR N PACKAGE
• Multiplexed Inputs/Outputs Provide
Improved Bit Density
(TOPVIEWI
so
• Four Modes of Operations:
Hold (Store)
Shift Left
Shift Right
Load Data
GIG(;
E/QE
C/De
A/QA
QA'
ClR
GND
• Operates with Outputs Enabled or at High Z
• 3-State Outputs Drive Bus Lines Directly
• Can Be Cascaded for N-Bit Word Lengths
D/QD
B/QB
ClK
SR
SN54LS299, SN54S299 ... FK PACKAGE
• SN54LS323 and SN74LS323 Are Similar But
Have Synchronous Clear
(TOPVIEWI
• Applications:
Stacked or Push-Down Registers
Buffer Storage. and Accumulator
Registers
3
G/QG
GUARANTEED
TYPE
VCC
51
Sl
QH'
H/QH
F/QF
G1
G2
E/QE
C/Qc
A/QA
QA'
TYPICAL
SHIFT (CLOCKI
POWER
FREQUENCY
DISSIPATION
2
1 201!:J
4
'
III
6
Q)
(,)
7
'>
B
910111213
Q)
'LS299
25 MHz
175mW
C
'S299
50 MHz
700mW
...J
....
....
description
These Schottky TTL eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data
handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose
the modes of operation listed in the function table.
Synchronous parallel loading is accomplished by taking both function-select lines, SO and S1, high. This places the
three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked
into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. A direct
overriding input is provided to clear the register whether the outputs are enabled or off.
FUNCTION TABLE
INPUTSIOUTPUTS
INPUTS
MODE
FUNCTION
CUi'
Hold
Shift Right
Shift Left
Load
L
CLK
SERIAL
SL
OUTPUTS
AIQA BIQB CIQc DIQD EIQE FIQF GIll(; HIQH QA'
QH'
SR
L
L
X
l
l
l
X
l
L
X
X
X
l
L
L
L
L
l
l
L
l
l
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
l
L
°BO
°BO
°An
°An
°Cn
°Cn
°CO
°CO
Osn
°Sn
°On
°On
c
000
°EO
°EO
Dan
°FO
°FO
°En
°En
°Gn
°Gn
°GO
°GO
°Fn
°Fn
°Hn
°Hn
f
9
H
H
H
H
H
H
H
X
L
L
X
l
l
l
L
X
X
X
X
X
L
l
l
X
X
L
H
H
L
l
!
X
H
°AO
°AO
H
L
L
!
X
L
L
L
l
L
!
H
X
L
X
°Sn
°Sn
X
X
l
H
H
H
L
L
L
!
H
X
X
!
.
b
l
L
X
l
l
L
Clear
SELECT
51
SO
OUTPUT
CONTROL
Glt G2 t
000
°Cn
OCn
°En
°En
d
l
°Dn
°Fn
°Fn
.
l
l
l
°HO °AO aHa
°HO °AO °HO
H °Gn
°Gn
L
°Gn
°Gn
H
H
OSn
l
h
°Sn
a
L
h
tWhen one or both output controls are high the eight input/output terminals are disabled to the high-Impedance state; however,
sequential operation or clearing of the register is not affected.
a ... h
=
the level of the steady-state input at inputs A through H. respectively. These data are loaded into the flip-flops while the flip-flOp
outputs are isolated from the input/output terminals.
PRODUCTION DaTA dacu ...nts ...tain i.lo.mation
cu.raot "' 01 publlCltlo. data. Pmucts c••
to
~ClltiDRI per the terms af Tlxu Iistramints
Ia".
::=~ri:;-r::I:r~ =:~:; :.r:::.::~!~~ Rat
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-823
SN54LS299, SN54S299, SN74LS299, SN74S299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
logic symbol t
-t
-t
rC
CD
<
C::;'
CD
en
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12,
Pin numbers shown are for OW, J, N, and W packages.
logic diagram (positive logic)
~~~~j~~~iJl_..J.!11!!!....81 SHIFT LEFT
SERIAL
SHIFT RIGHT
SERIAL INPUT
FOUR
IDENTICAL
CHANNELS
NOT
SHOWN
Q
A
,
~-;::::==I:±:::l:::=::l-.:±:t~=:
CLR
OUTPUT {o1
CONTROLS
G2-=----'
I{O PORTS NOT SHOWN;
161 C:O c
IS) E.OE
11410'00
115) F'Q F
Pin numbers shown are for OW, J, N, and W packages.
2-824
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
INPI'~
SN54LS299. SN74LS299
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
o
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC
TYPICAL OF OUTPUTS
TYPICAL OF OUTPUTS
QA'THRUQH'
QA THRU QH
---t--Vcc
Req
INPUT
__
OUTPUT
SO, SI: Req= 9 kl! NOM
All other inputs: Req= 18 kH NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
I nput voltage
Off·state output voltage
Operating free-air temperature range: SN54LS299
SN74LS299
Storage temperature
. 7V
. 7V
5.5 V
_55°C to 125°C
oOe to 70°C
-65°C to 150°C
NOTE1: Voltage values are with respect to network ground terminal,
recommended operating conditions
SN54LS299
Supply voltage,
Vee
High-level output current, IOH
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
QA thru 0H
Width of clear pulse, tw(clear)
Setup time, tsu
Hold time, th
-2.6
-0.4
-0.4
12
24
QA' orQH'
4
0
Clock frequency, fclock
Width of clock pulse, tw(clock)
-1
QA thru 0H
0A' orOH'
Low-level output current, IOL
SN74LS299
MIN
20
8
0
Clock high
30
30
Clock low
18
10
Clear low
25
20
Select
351
351
High-level data t
201
201
Low-level data t
201
201
Clear inactive-state
241
201
Select
101
101
Data t
31
Operating free-air temperature, T A
-55
20
0
V
mA
mA
MHz
ns
ns
ns
ns
01
125
UNIT
70
°c
t Data includes the two serial inputs and the eight input/output data lines.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-825
SN54LS299, SN74LS299
8;81T UNIVERSAL SHIFT/STORAGE REGISTERS
electrical char.acteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt
PARAMETER
f--:-c-
VIH
High-level input voltage
VIL
Low~evel
VIK
Input clamp voltage
VOH
High..Jevel output voltage
input voltage
Vee = MIN,
11=-18mA
QA thruQH
Vee - MIN,
VIH=2V,
2.4
QA'orQH'
VIL = VILmax,
IOH = MAX
2.5
QA thru QH
VOL
Vee =MIN,
Low-level output voltage
VIH=2V,
QA'orQH'
Off-state output current,
10ZH
high~evel
input vol tage
IIH
r0-
C
(I)
<
C:;'
(I)
en
Vee= MAX,
Vee=MAX,
Athru H
Vee=MAX
Any other
A thru H, SO, 51
High-level input current
Any other
50,51
IlL
Low-level input current
lOS
Short-circuit output current §
ICC
Supply current
Any other
QA thruQH
QA' or0H'
IOL=12mA
Vee =MAX,
Vee=MAX,
V
-1.5
-1.5
V
2.4
3.4
3.1
2.7
0.4
0.25
0.4
VIH = 2 V,
V
3.4
0.25
IOL =8mA
VIH-2V,
0.4
0.35
0.5
0.25
0.4
0.35
0.5
40
I'A
I'A
--400
-400
200
200
I VI = 5.5 V
100
100
VI-7 V
100
100
40
40
VI = 0.4 V
Vee = MAX
20
20
-0.8
-0.8
-0.4
-0.4
-30
-130 -30
-20
-100 -20
33
Vee = MAX
V
40
I VI-7 V
VI =2.7V
V
0.8
IOL - 24 mA
IOL=4mA
UNIT
0.7
0.25
VO=0.4V
SO,Sl
SN74LS299
3.2
VO=2.7V
QA thru QH
voltage applied
Input current at maximum
II
-t
-t
low~evel
VIL= VI Lmax
QA thru QH
voltage applied
Off-state output current,
10ZL
SN54LS299
MIN TYPt MAX MIN TYP* MAX
2
2
-130
-100
53
33
53
I'A
I'A
mA
mA
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee"" 5 V. T A"" 25 Q C.
§Nat more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER.
FROM
TO
(INPUT)
(OUTPUT)
f max
tPLH
tPHL
tpHL
eLK
QA' orQH'
eLR
QA' or QH'
tPLH
eLK
QA thru QH
eLR
QA tnru QH
(31,(32
QA thru QH
tPHL
tpZL
tPHZ
RL = 2 kn.
RL=665n.
tPHL
tpZH
TEST CONDITIONS
See Note 2
(31,(32
tPLZ
QA thru QH
eL=15pF
eL = 45 pF
MIN
TYP
20
35
22
39
27
40
17
25
26
39
40
19
eL - 5 pF
21
30
10
20
10
15
~ f max == maximum clock frequency
tPLH == propagation delav time, low-to-high-Ievel output.
tpHL == propagation delay time, high-to-Iow-Ievel output
tpZH == output enable time to high level
tpZL == output enable time to low level
tPHZ == output disable time from high level
tPLZ ::E output disable time from low level
NOTE 2: For testing f max , all outputs are loaded simultaneously, each with CL and RL as specified for the propagation times.
Load circuits and voltage waveforms are shown in Section 1.
2-826
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
MHz
33
26
26
13
RL = 665 n,
MAX
ns
ns
ns
ns
ns
ns
SN54S299, SN74S299
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
·
a
schematics of inputs and outputs
EQUIVALENT OF Gl
AND G21NPUTS
EQUIVALENT OF CLOCK AND
CLEAR INPUTS
v eC
vcc~--
Req
INPUT
EQUIVALENT OF A THRU Ht, SO, SI,
SHI FT RIGHT, AND SHI FT LEFT INPUTS
VCC~3.5k{l
NOM
2.8 k{l
NOM
••
--
INPUT
INPUT
Clock: Req = 2.8 kO NOM
Clear: Req:: 3.5 kO NOM
;--
tWhen 3-5tate outputs are disabled.
TYPICAL OF OUTPUTS
TYPICAL OF OUTPUTS
QA THRUQH
QA'ANDQH'
---....---vcc
---",,---vee
OUTPUT
OUTPUT
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Off-state output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54S299 (See Note 1) .............. - 55 °e to 125°e
SN74S299 ............................ ooe to 70 0 e
Storage temperature range ................................. .
NOTE
......JI-
1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54S299
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
-2
-0.5
20
4.75
5
5.25
-6.5
-0.5
20
Supply voltage, VCC
High-level output current, IOH
QA thru QH
QA' or QW
LOW-level output current, IOL
QA thru QH
QA' orQH'
Clock frequency, f clock
Width of clock pulse, tw(clockl
Width of clear pulse, tw(clear)
Clock high
Clock low
Clear low
Select
Setup time, tsu
Hold time, th
High·level data"
Low-level data t
Clear inactive-state
Select
Data;
Operating free-air temperature, T A
SN74S299
MIN
0
10
10
10
15t
7t
5t
lOt
5t
5t
-55
6
50
125
0
10
10
10
15t
7t
5t
lOt
5t
5t
0
6
50
UNIT
V
rnA
rnA
MHz
ns
ns
ns
ns
70
"C
t Data includes the two serial inputs and the eight input/output data lines.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-827
SN54S299, SN74S299
.
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
V,H
High-level input voltage
V,L
Low-level input voltage
V,K
Input clamp voltage
VOH
VOL
TEST CONDITIONSt
High-level output voltage
1,--18mA
QA thruQH
VCC=MIN,
V,H = 2 V,
2.4
3.2
QA'orQH'
V,L = 0.8 V,
10H = MAX
2.7
3.4
VCC=MIN,
V,H = 2 V,
V,l = 0.8 V,
10l = MAX
VCC= MAX,
V,H = 2 V,
LOW-level outPut voltage
QA thru QH
high-level voltage applied
QA thruQH
low-level voltage applied
Input current at maximum input voltage
"
-C:)"
(I)
Any other
low-level input current
I,L
VCC -MAX,
V,H =2V,
Vo = 0.5 V
VCC = MAX,
V, = 5.5 V
VCC = MAX,
V, = 2.7 V
50,51
VCC = MAX,
lOS
Short-circuit output current§
ICC
Supply current
QA thruQH
QA'or QH'
V
-1.2
V
V
0.5
V
100
itA
-250
itA
1
100
mA
50
V,=0.5V
-500
-250
-40
VCC = MAX
-100
-100
-20
VCC - MAX
UNIT
0.8
-2
Any other
o
<
A thru H, SO, 51
Vo = 2.4 V
ClK or ClR
-t
-t
r(I)
High-level input current
"H
MAX
V
VCC-MIN,
Off-state output current,
10ZL
TYPt
2
Off-state output current,
10ZH
MIN
140
225
TYP
MAX
itA
mA
!LA
itA
mA
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at
Vee
==
5 V, T A == 25°C.
~ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VI
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER.
FROM
TO
!INPUT)
(OUTPUT)
ClK
QA' orQH'
f max
tPlH
tPHL
tPHL
tPLH
tpHl
tpHL
tpZH
tPlZ
MIN
50
See Note 2
ClR
RL = 1 kn,
CL = 15 pF
QA'or QH'
ClK
QA thruQH
ClR
QA thru QH
131,132
QA thruQH
131,132
QA thru QH
tPZl
tPHZ
TEST CONDITIONS
Rl=280n,
RL-280n,
CL = 45 pF
CL - 5 pF
1fmax = maximum clock frequency
tplH = Propagation delay time, low-to-high-Ievel output
tpHl = Propagation delay time, high-to-Iow-Ievel output
tpZH = output enable time to high level
tpZL = output enable time to low level
tpHZ = output disable time from high level
tplZ = output disable time from low level
NOTE 2: For testing f max • all outputs are loaded simultaneously, each with Cl and Rl as specified for the propagation times.
Load circuits and voltage waveforms are shown in Section 1.
2-828
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLA.S, TEXAS 75265
70
UNIT
MHz
12
20
ns
13
20
14
21
15
15
21
21
ns
16
24
ns
10
18
12
18
7
12
7
12
ns
ns
ns
SN54LS320, SN54LS321, SN74LS320, SN74LS321
CRYSTAL-CONTROLLED OSCILLATORS
0241 B. DECEMBER 1978 - REVISED MARCH 1988
'LS320
•
Crystal-Controlled Oscillator Operation
from 1 MHz to 20 MHz
•
2-Phase Driver Outputs
SN54LS320 ..• J OR W PACKAGE
SN74LS320 ... N PACKAGE
(TOP VIEW)
TANK1
TANK2
GND1
FFQ
FFD
NC
F
GND2
'LS321
•
Similar to 'LS320 But Includes f/2 and
f/4 Count-Down Outputs
description
The 'LS320 is a crystal-controlled oscillator I clock
driver. It features complementary standard and highcurrent driver outputs. A synchronization flip-flop is
included.
TANK1
TANK2
GND1
FFQ
FFD
F/4
F
GND2
These circuits were designed for crystal control of
frequency and capacitive control is not recommended.
If a fundamental crystal is used, an inductor of 5 to 160
"H is required to be connected between the tank 1 and
tank 2 inputs. t
VCC
XTAL2
XTAL1
Q)
(.)
'>
F'
F'
Q)
C
...t
FREQUENCY LIMITS
OUTPUTS IN USE
Driver outputs only
Other outputs only
Driver and any other outputs
Vee
5V
VCC'
f max
5V
20 MHz
5V
Open
20 MHz
5V
5V
10 MHz
'LS321
171
G
JU"L
F
F
TANK2
XTAL1
F'
XTAL2
F'
(4)
F'
TANK2
F'
(13)
XTALl
CTROIV4
XTAL2
Cl
FFO 15)
FFO
F
F
TANKl
'LS320
lI-
For chip carrier information.
contact the factory,
G
10
(I)
F
VCC'
.I1.IL
TANKl
FI2
NC - No internal connection
logic symbols:l:
FFO 15)
F'
F'
(TOP VIEW)
The 'LS321 is identical to the 'LS320 except it
additionally features two count-down outputs, F/2 and
F/4.
The SN54LS320 and SN54LS321 are characterized for
operation over the full military temperature range of
- 55°C to 125°C, The SN74LS320 and SN74LS321
are characterized for operation from ooC to 70°C.
VCC'
SN54LS321 ... J PACKAGE
SN74LS321 ... N PACKAGE
The driver outputs, F' and F' have very-low impedance
and can be used to drive highly capacitive TTL-level
lines. If the driver outputs are not used, then the V CC'
terminal can be left open.
Interaction of the driver outputs with the other outputs
limits useful frequencies as shown in the frequencylimits table.
VCC
XTAL2
XTAL1
NC
F
10
16)
14)
F/2
F/4
FFO
tThe value of the inductor is selected from the graph in Figure 2. Use the next higher standard inductor value if the selected value is not available. If a third over·
tone crystal is used, a tuned tank is necessary. The center frequency of the tuned tank is determined by the equation f = y., m[LC.
*These symbols are in accordance with ANSI/IEEE Std. 91-1984 and lEG Publication 617-12.
PRODUCTIOI DATA d••u..lOta.lltain infarmltl••
curront II ., pablicoti•• date, Products ••nf.rm t.
IpICiliutil.1 por the lar..1 of Taul (nltru ..11III
==i~·i:l~i ~~:~~: N!":::A:~~. not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-829
SN54LS320, SN54LS321, SN74LS320, SN74LS321
CRYSTAL·CONTROLLED OSCILLATORS
logic diagram (positive logic)
FFD~I~5)~------------------------------ilD 1-______----"14:::...) FFO
i>o-----<~Cl
TANK 1
III
TANK 2 ~'----I
CSC
XTAL 1-("'-1"'4)'------\
(7)
F
(12)
F
.----VCC'
rDR~ER'
XTAL 2
: SECTION:
<--------t--I
(10) F'
19)
F'
IL ___ .JI
- - ------,
r
'LS321
ONLY
-I
-I
r-
I
>_--->:(6::..) F/4
I
I
I
I
I
I
I
I
L-_ _ _~,>--..!(.:.:13::...) F/2
I
IL __________ _ _ _ _ _ _ _ _ _ _ .JI
I
C
CD
s.
n
CD
en
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Supply voltage, Vee' . . , . .
Input voltage to FFD terminal
Operating free·air temperature range: SN54 LS320, SN54 LS321
SN74LS320,SN74LS321
Storage temperature range
. . . . . 7V
7V
-0.5 V to 7 V
-55°C to 125°C
oOe to 70°C
_65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminals.
recommended operating conditions
SN74LS320
SN54LS320
Supply voltage,
Supply voltage,
Hjgh~level
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
4.5
5
5.5
4.75
5
5.25
Vee
Vee
output current, IOH
Low-level output current, IOL
Output frequency. f out
F' or F'
F,
F, F/2,
-12
24
-0.4
-0.4
12
24
4
B
F, F/2, F/4
0.5
10
0.5
F/4 ('LS321)
0.25
5
0.25
5
1
20
1
20
-55
125
0
70
F
Input and output schematics are similar to those shown for SN74LS326.
2-830
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V
V
rnA
rnA
10
F/2 ('LS321)
For
Operating free-air temperature, T A
F/4
F'or F'
F,
UNIT
SN74LS321
SN54LS321
MHz
°c
SN54LS32L SN54LS321, SN74LS32L SN74LS321
CRYSTAL·CONTROLLED OSCILLATORS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONSt
MIN
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
High-level
VOH
F',
output voltage
F',
Low-level
VOL
F'
Others
output voltage
F'
Others
SN54LS320
SN74LS320
SN54LS321
SN74LS321
TYP:j:
MAX
MIN TYP:j:
2
VCC = MIN,
VCC' = MIN,
11=-18mA
VCC = 4.5 V,
Vcc: = 4.5 V,
10H =-12 mA
VCC = 4.75 V,
VCC' = 4.75 V, 10H =-24mA
VCC- MIN,
VIH-2V,
VCC = MIN,
VCC' = MIN
VCC = MIN,
VIL = VILmax
Input current at
10H - -400
V
2
2.4
3.3
2.4
3.4
~A
UNIT
MAX
IOL=12mA
0.7
0.8
V
-1.5
-1.5
V
0.25
2.7
3.3
2.7
3.4
0.4
IOL=24mA
0.25
10L =4 mA
0.4
IOL-8mA
V
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
V
VCC= MAX,
VI = 7 V
IIH
High-level input current
VCC= MAX,
VI = 2.7 V
20
20
JJA
IlL
Low-level input current
VCC= MAX,
VI=O.4V
-0.4
-0.4
mA
-100
mA
II
maximum input voltage
0.1
0.1
mA
Short--circuit
lOS
VCC=MAX
output current §
Supply current
ICC
from VCC
-20
VCC= MAX,
FFD at GNO
VCC = MAX,
VCC' = MAX,
-100
-20
'LS320
42
70
42
70
r'LS321
47
75
47
75
4
8
4
8
en
G)
mA
CJ
'>
Supply current
ICC'
from VCC
FFD at GND
mA
G)
C
...J
I--
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAil typical values are at
Vee
=
5 V. Vee'
=5
~
V, and T A"" 25°C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. Outputs F' and
not have short-circuit protection and these'limits do not apply.
.
.
F'
do
switching characteristics Vee = 5 V Vee = 5 V TA = 25°e
PARAMETER
OUTPUTS
'LS320
TEST CONDITIONS'
F/2
f max
Maximum operating
F/4
frequency
All others
CL = 100pF
MIN
RL=2kn
t,
CL = 100pF
20
RL = 667 n
CL = 200pF
Rise time, 1 V to 3 V
CL=50pF
Others
Fall time, 3 V to 1 V
Others
TYP
10
15
5
7.5
20
30
MAX
6
12
6
12
7
14
7
14
7
14
7
14
11
22
11
22
40
25
40
70
45
70
5
10
5
10
5
10
5
10
CL = 200pF
6
12
6
12
CL=50pF
6
12
6
12
10
20
10
20
17
30
17
30
CL=100pF
CL=100pF
RL=667n
RL=2kn
CL = 200pF
UNIT
MHz
25
RL=2kn
CL = 50pF
t,
30
MIN
45
CL=100pF
CL = 200pF
F', F'
'LS321
MAX
RL = 667 n
CL-50pF
F', F'
TYP
ns
ns
, load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-831
SN54LS320, SN54LS321, SN74LS320, SN74LS321
CRYSTAL·CONTROLLED OSCILLATORS
TYPICAL APPLICATION DATA
The SN54174LS320 and 'LS321 are crystal-controlled oscillators. Figure 1 shows the device with all required
external components.
r-------~--------------------------------_o5.0V
r-------------------O F
100 nF
-I
-I
c
r-
C
CD
L-------------~~--------------~--_1~--_oGND
<
C:;"
CD
FIGURE 1.
(II
1.
Where:
CRYSTAL-CONTROLLED OSCILLATOR 'LS320/321
Determination of C and L are as follows:
a. Inductance L
Select Inductance L according to Figure 2.
b. Capacitor C
C
= CS-Cp-CL
Cp
CL
L
Cs
= parasitic board capacitance
= parasitic capacitance of the inductor
= inductance
= required capacitance calculated as follows:
Cs
(2.n .f q )2.L
for fq
2.
>
12 MHz, C
= 0 pf
Electrical characteristic for the crystal:
The quartz crystal used as a frequency reference should be designed for series mode operation
with a resistance in the 20 Q to 75 Q range and be capable of a minimum 2 mw power dissipation.
It is recommended to use a tuned tank also for fundamental crystals.
2-832
TE~ . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS32D. SN54LS321. SN74LS32D. SN74LS321
CRYSTAL"CONTROLLEO OSCILLATORS
160
140
\
\
\
:::I.
I
w
:;)
....c(
>
100
a:
0
c
!
60
...I
....
....
\
~
2
c(
Q)
C
~
...S
I-
"S;
,
N
~
c(
en
Q)
(J
1\
\
80
2
l-
= OpF
~
ICJ
:;)
C
,
:a:: 120
40
\.
'\
20
o
o
2
4
~
......
I'-...
6
8
10
12
14
16
18
20
FUNDAMENTAL CRYSTAL FREQUENCY -MHz
FIGURE 2
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75265
2-833
2-834
SN54LS322A. SN74LS322A
8-BIT SHIFT REGISTERS WITH SIGN EXTEND
02411. OCTOBER 1977 - REVISED MARCH 1988
SN54LS322A ... J OR W PACKAGE
SN74LS322A ... OW OR N PACKAGE
• Multiplexed Inputs/Outputs
Provide Improved Bit Density
nop VIEWI
• 3-State Outputs Drive Bus
Lines Directly
VCC
G
SIP
00
A/OA
• Sign Extend Function
• Direct Overriding Clear
description
These low-power Schottky eight-bit shift registers
feature multiplexed inputloutput data ports to achieve
full eight-bit data handling in. a single 20-pin package.
Serial data may be entered into the shift-right register
through either the 00 or the D1 input as selected by the
data select input. A serial output (OH') is also provided
to facilitate expansion. Synchronous parallel loading is
accomplished by taking both the register enable and the
S/p inputs low. This places the three-state input/output ports in the data input mode. Data are entered on
the low-to-high transition of the clock. The data extend
function repeats the sign in the 0A flip-flop during shifting. A direct overriding clear input clears the internal
registers when taken low whether the outputs are enabled or off. The output enable does not interfere with synchronous operation of the register.
C/Oc
DS
SE
D1
BlOB
E/OE
D/OD
G/OG
DE
F/OF
H/OH
CLR
°H'
GND
CLK
SN54LS322A ... FK PACKAGE
(TOP VIEWI
ol~
13 en
oenlC!l> 0
321
A/OA
4
C/OC
E/OE
G/OG
DE
5
SE
D1
BlOB
D/OD
F/OF
6
7
8
9 10111213
FUNCTION TABLE
INPUTS
REGISTER
OPERATION
ClR
ENABLE
sip
G
I NPUTS/OUTPUTS
SIGN
DATA
OUTPUT
EXTEND
SELECT
ENABLE
SE
OS
OE
OUTPUT
ClK
A/OA
BlOB
C/Oc·· .H/OH
°H
L
H
X
X
X
L
X
L
L
L
L
L
X
H
X
X
L
X
L
L
L
L
H
H
X
X
X
L
X
OAO
°BO
OCO
OHO
aHO
H
L
H
H
L
L
t
DO
°An
aSn
°Gn
°Gn
H
L
H
H
H
L
t
D1
°An
°Sn
°Gn
Sign Extend
H
L
H
L
X
L
t
H
L
L
X
X
X
t
°An
b
°Sn
Load
°An
a
°Gn
aGn
c
h
h
Clear
Hold
Shift Right
L
L
aGn
When the output enable is high, the eight input/output terminals are disabled to the high-impedance State; however, sequential operation
or clearing of the register is not affected. If both the register enable input and the sip input are low while the clear input is low. the register is cleared while the eight input/output terminals are disabled 1:0 the high-impedance state.
H = high level (steady state)
L = low level (steady state)
X", irrelevant (any input, including transitions)
t '" transition from low to high level
QAO' .. aHO = the level of QA through QH. respectively. before the indicated steady-state conditions were established
QAn ... 0H n "" the level of 0A through 0H. respectively. before the most recent t transition of the clock
~O, 01 = the level of steady-state inputs at inputs DO and 01 respectively
a ... h '" the level of steady-state inputs at inputs A through H respectively
PRODUCTION DATA d.cumlntl contlin informltion
current I. of publicltiaR dlte. Products canfDrm to
specificltion. per the terms of T8111 Instruments
:':~:~i~li~:I~~i ~!:1::i:; :.r::::~::.s nat
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-835
sao!J\aa 11.1.
'"ciow
.85'
Ol
REGISTER
ENABLE
0..
....
fnen
ii1
3
-·N
"'N
;:;:
sip-----f /
Sf
Dl (17)
(!l
~
Q
~z
q':> I
j
I
II
-en~
.....
.8
men
::a
w
-I ....
en N
:e;
=i
=
en
m
><
-I
m
DO (3)
Z
CI
;;;c~
~ ~tJj
(12)
~~.
lD
~U5~
Cl
R
'"
°H'
Cl
Cl
R
R
~
~
-1:110
::a"
men
c;,z
2
g~r;;i
'"
'"'"
=w
a:;
DATA
SELECT
DS
~~
-I~
~'
§.:
SIGN
(18)
EXTEND
CLDCK
CLEAR
~!:~~
(8)
~
OE
(16)
AIOA
BlaB
INPUTSIOUTPUTS NOT SHOWN
(5) CIOc
(15) O/OD
(6) EIOE
(14) FIOF
Pin numbers shown are for OW. J, N, and W packages.
Cl
R
en
~'
f
G
CD
'z
!!!c.n
SN54LS322A, SN74LS322A
8·BIT SHIFT REGISTERS WITH SIGN EXTEND
logic symbol t
SRGO
DE
G
SIP
C6i1
CLK
IT
(10)
G4
0,4,1,60
OS
DO
01
AIOA
BlOB
(19)
(3)
(17)
(4)
G5
4,5,1,60
4,5,1,60
27
t>
20
t>
214
(12)
Ow
tThis symbol is in accordance with ANSIIIEEE Std. 91-1984 and lEe Publication 617-12.
Pin numbers shown are for OW, J, N, and W packages.
schematics of inputs and outputs
EOUIVALENT OF EACH INPUT
Vee
TYPICAL OF OUTPUTS
0A THRUOH
---.-vee
Vee
INPUT -,f"'''"''1>OUTPUT
OUTPUT
Sign extend: Req 6 kS2 NOM
Data select: Req "- 9 kH NOM
= 18 kil NOM
0.:
All other inputs: Req
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-837
SN54LS322A, SN74LS322A
8·BIT SHIFT REGISTERS WITH SIGN EXTEND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
I nput voltage . , . . . . . .
Off-state output voltage
Operating free-air temperature range: SN54LS322A
SN74 LS322A
Storage temperature
7V
7V
7V
_55°C to 125°C
oOe to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54lS322A
-4
-I
rC
VCC
Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
IOH
High-level output current
IOl
Low-Jevel output current
fclock
Clock frequency
twlclock)
Width of clock pulse
SN74lS322A
MIN
NOM
MAX
MIN
NOM
MAX
4.5
2
5
5.5
4.75
2
5
5.25
QA thru QH
QH'
QA thru QH
QH'
0.7
-1
-0.4
12
4
20
(i'
Data select
0
30
10
20
10t
CD
High-level data t
20t
20t
Low-level data t
20t
201
20t
201
351
501
101
CD
<
Clock high
Clock low
Clear low
twlclear}
(I)
tsu
Setup time
Clear inactive-state
Register enable G high
Register enable Glow
Data select
th
Hold time
Data t
Register enable
high or low
TA
Operating free-air temperature
351
501
101
21
21
01
01
-55
tOata includes the two serial inputs and the eight input/output data lines.
tThe arrow indicates that the rising edge of the clock pulse is used for reference.
2-838
0
30
10
20
10t
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
125
0
0.5
-2.6
-0.4
24
8
20
UNIT
V
V
V
rnA
rnA
MHz
ns
ns
ns
ns
70
°c
SN54LS322A, SN74LS322A
8-BIT SHIFT REGISTERS WITH SIGN EXTEND
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
Vce= MIN,
11=-18rnA
QA thru QH
Vee = MIN,
VIH=2V,
QH'
10H = MAX
VIK
VOH
QA thru QH
VOL
QH'
SN54LS322A
TEST eONDITloNst
PARAMETER
MIN
SN74LS322A
MAX
MIN
TYpi
- 1.5
2.4
VIL = MAX,
2.5
10L -12rnA
Vee = MIN,
Typi
VIH=2V,
3.2
2.4
3.4
0.4
0.25
0.4
IOL=24mA
VIL = MAX
IOL=4mA
3.1
2.7
0.25
MAX
-1.5
10L -8rnA
UNIT
V
V
3.4
0.25
0.4
0.35
0.5
0.25·
0.4
0.35
0.5
V
10ZH
QA thru QH
Vce= MAX,
VIH=2V,
VO=2.7V
40
40
I'A
10ZL
QA thru QH
Vee= MAX,
VIH=2V,
Vo = 0.4 V
-0.4
-0.4
rnA
II
A thru H
VI - 5.5 V
0.1
0.1
Data select
VI = 7 V
0.2
0.2
VI = 7 V
0.3
0.3
VI = 7 V
0.1
0.1
40
40
Sign extend
Vee = MAX
Any other
A thru H, DS
IIH
Sign extend
VCC = MAX,
VI = 2.7 V
60
60
20
20
-0.8
- 0.8
-1.2
- 1.2
Any other
Data select
IlL
Sign extend
VCC= MAX,
VI =0.4V
Any other
QA thru QH
10S*
QH
-0.4
Vee = MAX,
Va = 2.25 V Ifor 54lS only)
-65
- 30
- 130
-10
-50
- 20
-100
35
60
35
t
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t
All typical values are at
Vee""
5 V, T A
=
I'A
II)
Q)
(.)
rnA
-S
- 0.4
-15
VCC= MAX
ICC
rnA
60
Q)
rnA
C
rnA
....I
l-
I-
25°C.
~ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~
FROM
TO
(INPUT)
(OUTPUT)
CLK
QH
CLR
QH
CLK
QA thru QH
CLR
QA thru QH
DE
QA thru QH
TEST CONDITIONS
f max
tPLH
tPHL
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
See Note 2
20
CL=15pF,
See Note 2
RL = 665 n,
~ maximum clock frequency
== propagation delay time, low-to-high-Ievel
tpHL == propagation delay time, high-to-Iow-Ievel
tpZH == output enable time to high level
tpZL
output
tpHZ
output
tpLZ
CL = 45 pF,
See Note 2
RL = 665 n,
QA thru QH
DE
• f max
tpLH
RL = 2kn,
MIN
CL = 5 pF,
See Note 2
TYP
MAX
35
UNIT
MHz
22
33
26
35
27
35
16
25
22
33
22
35
15
35
15
35
15
25
15
25
ns
ns
ns
ns
ns
ns
=
output enable time to low level
== output disable time from
== output disable time from
high level
low level
NOTE 2: For testing f max • all outputs are loaded simultaneously, each with CL and RL as specified for the propagation times.
Load circuits an.~ voltage waveforms are shown in Section 1.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS. TEXAS 75265
2-839
-f
-f
r-
C
CD
5.
(")
CD
fA
2-840
SN54LS323. SN74LS323
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
OCTOBER 1976 -
REVISED MARCH 1988
SN54LS323 ... J OR W PACKAGE
SN74LS323 ... OW DR N PACKAGE
• Multiplexed Inputs/Outputs Provide
Improved Bit Density
(TOP VIEWI
• Four Modes of Operation:
Hold (Store)
Shift Left
Shift Right
Load Data
50
(31
VCC
51
5l
OH'
H/OH
F/OF
G2
• Operates with Outputs Enabled or at High Z
• 3·State Outputs Drive Bus Lines Directly
• Can Be Cascaded for N·Bit Word Lengths
0100
BlaB
• Typical Power Dissipation ... 175 mW
ClK
5R
• Exceptionally Stable Shift (Clock)
Frequency ... 25 MHz
SN54LS323 ... FK PACKAGE
(TOP VIEWI
• Applications:
Stacked or Push·Down Registers,
Buffer Storage, and
Accumulator Registers
No-a
1"'1'"
3 2
(f)
u
U .....
>
(f)
1 20 19
• SN54LS299 and SN74LS299 Are Similar
But Have Direct Overriding Clear
(I)
Q)
(J
'S;
910111213
Ia::
C
a::
~
Q)
o
III
..Jz(J)-Jd
U(!)
description
Ua-J
These Low-Power SchottkYI eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight·bit data
handling in a single 20'pin package. Two function-select inputs and two output-control inputs can be used to choose
the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both
function-select lines, SO and 51, high. This places the three·state outputs in a high-impedance state, which permits data
that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished
while the outputs are enabled in any mode. The clear function is synchronous, and a low level at the clear input clears
the register on the next low-to-high transition of the clock.
-'
l-
I-
FUNCTION TABLE
INPUTS
MOOE
Clear
Hold
Shift Right
Shift Left
Load
ClR
INPUTSIOUTPUTS
FUNCTION
OUTPUT
SELECT
CONTROL
Glt G2t
S1
so
L
L
x
L
L
X
L
L
L
L
elK
SERIAL
SL
SR
I
I
x
X
X
X
OUTPUTS
AIDA BlOB CIOc 0100 EIOE FIOF G/Dc; H/OH °A·
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
°H·
L
L
L
L
H
H
x
X
t
X
X
X
X
X
X
X
X
X
H
L
L
L
L
X
X
X
DAO
DBO
DCO
DOO
DEO
DFO
DGO
DHO DAO OHO
H
X
X
L
L
L
X
X
aCO
DOO
DEO
DFO
DGO
DHO
L
H
L
L
I
X
H
DAO
H
DBO
H
DAn
DBn
DCn
DOn
DEn
DFn
DGn
H
L
H
L
L
f
X
L
L
DAn
DBn
DCn
aO n
DEn
DFn
H
H
L
L
L
f
H
X
DBn
DCn
DOn
DEn
DFn
DGn
aHn
DGn
H
H
H
L
f
L
X
DBn
DCn
aHn
L
X
I
X
X
DEn
d
DGn
X
DOn
c
DFn
H
L
H
L
H
e
f
9
h
.
b
DAO DHO
H aGn
L
DGn
H
DBn
DBn
a
L
h
tWhen one or both output controls are high the eight Input/output terminals are disabled to the high-Impedance state; however.
sequential operation or clearing of the register is not affected.
a . . . h '" the level of the steady-state input at inputs A through H, respectively. These data are loaded into the flip-flops while the flip·flop
outputs are isolated from the input/output terminals.
PRODUCTION DATA d...........ntai. inf.rmlti.n
c.rr.nt II of publicDan dlt•. ProdUCtl cDnfarm to
IpIICifiClti_ ,.. til. t ..lI••f T.... I.ltr.......
~:.=.~~·i~:,:Ji =:~:; lIr=~":t:~~ n.t
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-841
SN54LS323, SN74LS323
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
logic symbol t
IBI
117)
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12.
Pin numbers shown are for OW, J, N, and W packages.
logic diagram (positive logic)
51
(l91
CL:R
SO
111
191
rtt-tt__.:.:I1",BI:...
FOUR
IDENTICAL
CHANNELS
NOT
SHOWN
OUTPUT {Gl
CONTROLS
G2-,-;:~--...J
141
(13)
BlaB
Pin numbers shown are for OW, J, N, and W packages.
2-842
G/OG
INPUTS/OUTPUTS NOT SHOWN:
(61 C/oe
(5) E/Oe
{14} 0100
(15} F/OF
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SL
SN54LS323, SN74LS323
8·BIT UNIVERSAL SHIFT/STORAGE REGISTERS
schematics of inputs and outputs, absolute maximum ratings, recommended operating conditions, and
electrical characteristics
Same as SN54LS299 and SN74LS299, except tsu (Clear Inactive) does not apply_
switching characteristics, Vee
PARAMETERt
= 5 V, TA = 25°e
FROM
TO
IINPUT)
IOUTPUT)
tPlH
tpHL
tpLH
tpHl
tPZH
ClK
ClK
QA' orQH'
<31,<32
<31,<32
=
RL=2kll
QA thru QH
RL = 665 Il
QA thru QH
QA thru QH
tPLZ
t t max
Cl = 15pF,
Cl =45pF,
tpZl
tpHZ
TEST CONDITIONS
See Note 1
f ma )(
CL =5pF,
RL=6651l
MIN
TYP
25
35
MAX
MHz
22
33
26
39
17
25
25
39
21
14
UNIT
20
30
10
20
10
15
ns
ns
ns
ns
maximum clock frequency
tplH = Propagation delay time, low-to-high-Ievel output
tpHl = Propagation delay time. high-to-Iow-Ievel output
tpZH = Output enable time to high level
tpZL = Output enable time to low level
tpHZ = Output disable time from high level
tpLZ = Output disable time from low level
NOTE 1: For testing fmax • all outputs are loaded simultaneously. each with CL and RL as specified for the propagation times.
Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
CI)
Q)
.2
>
Q)
o
......
-I
2-843
2-844
SN54LS348, SN74LS348 (TIM9908)
B·LlNE TO 3·LlNE PRIORITY ENCODERS
WITH 3·STATE OUTPUTS
OCTOBER 1976 - REVISED MARCH 19BB
•
3·State Outputs Drive Bus Lines Directly
•
Encodes 8 Data Lines to 3·Line Binary (Octal)
•
Applications Include:
N·Bit Encoding
Code Converters and Generators
•
Typical Data Delay ... 15 ns
•
Typical Power Dissipation ... 60 mW
SN54lS34B __ • J OR W PACKAGE
SN74LS348 • __ D OR N PACkAGE
ITOP VIEWI
description
These TTL encoders feature priority decoding of the
inputs to ensure that only the highest-order data line
is encoded_ The 'LS348 circuits encode eight data
lines to three-line (4-2-1) binary (octal)_ Cascading
circuitry (enable input El and enable output EO) has
been provided to allow octal expansion_ Outputs AO,
A1, and A2 are implemented in three-state logic for
easy expansion up to 64 lines without the need for
external circuitry. See Typical Application Data_
2
X
GS
H
H
AO
Z
Z
H
L
L
L
L
L
L
H
H
L
L
H
L
H
H
L
H
L
L
H
H
L
H
H
H
L
H
H
L
L
L
H
H
H
L
H
L
H
4
5
6
7
A2
X
H
X
H
X
X
X
H
H
X
X
X
X
L
H
X
L
H
H
X
L
H
H
H
H
H
L
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
L
L
H
H
H
L
X
X
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
L
2
1
0
AO
(TOP VIEWI
U
Ill..t
~ ~@
GS
3
7
NC
El
A2
II)
Q)
(J
'>
Q)
C
H = high logic level. L = low logic level, X
Z:: high-impedance state
= irrelevant
....I
EO
Z
Z
A1
Z
Z
3
0
X
L
3
OUTPUTS
INPUTS
1
X
EO
GS
SN54LS348 _ •• FK PACKAGE
FUNCTION TABLE
EI
Vec
4
5
6
7
El
A2
Al
GND
lI-
H
NC - No internal connection
logic symbol t
HPRI BIN
0
(101
( 111
2
3
4
5
6
(121
(131
(11
(21
(31
(41
I>
0/Z10
10
1/Z11
11
2/Z12
12
3/Z13
13
4/Z14
14
S/Z15
15
6/Z16
16
7/Z17
17
;;'1
18
(151 EO
V18
EI
(5)
G19
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for D. J, N, and W packages.
PRODUCTIOI DATA documonll ...llin inl.,..IIi.n
curront II .1 pullilcalion dotl- P,odoell •• nl.... I•
• p..IIi••ti••• por Iho II,... of TOIII. Inllrumont.
=~~r,·[:~~7i ~:t;:~ti:r liIO:::~~:"~ not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-845
SN54LS348, SN74LS348 (TIM99D8)
8·L1NE TO 3·L1NE PRIORITY ENCODERS WITH 3·STATE OUTPUTS
logic diagram (positive logic)
E1
(5)
o
(10)
1 (11)
2 (121
3 (131
4 (11
-I
-I
r-
C
5 (21
CD
~.
(")
CD
en
6 (31
7 (41
Pin numbers shown are for 0, J. N, and W packages.
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC--""""--
TYPICAL OF OUTPUTS
AO,A1,A2
---...--VCC
TYPICAL OF OUTPUTS
EO,ES
---~-VCC
ReQ
I NPUT_"*-+------- -
-
-
- - -
234
Al
~
-
o
1
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
234
I
I
5 6
'LS348
AO
Al
T
T
FIGURE l-PRIO~ITY ENCOOER WITH UP TO 64 INPUTS_
2-848
I
111111
----< EO
LSB
7
Elp-E NABLE
I NPUT
GS
AZ
I
I
1
6
I
- - -
- -
5
'LS348
AD
GS
1
1
-< EO
7
EI""l.,.
A2
T
GS
.LSTROBE
MSB
OUTPUT
SN54S350, SN74S350
FOUR·BIT SHIFTER WITH THREE·STATE OUTPUTS
02745, DECEMBER 1983 - REVISED MARCH 1988
SN54S350 . , , J PACKAGE
SN74S350 , , , 0 DR N PACKAGE
• Shifts 4-Bits of Data to O. 1. 2 or 3
Places Under Control of Two Select Lines
(TOP VIEWI
• Three-State Outputs for Bus Organized
Systems
Vee
D-3
D-2
D-1
DO
D1
D2
D3
• 6.5 ns Typical Data Propagation Delay
description
The 'S350 is operationally equivalent to a 4-input
multiplexer with the inputs connected so that the select
code causes shifts of the data word. This makeS it possible to perform shifts of 0, 1, 2, or 3 places on words of
any length, with suitable interconnection,
YO
Y1
OE
Y2
Y3
SO
S1
SN54S350 , , , FK PACKAGE
A 7 -bit data word is introduced at the D inputs and is
shifted according to the code applied to the select inputs SO and S1. YO through Y3 are 3-state outputs controlled by an output enable, OE, When OE is ..!£.w,
the outputs follow the selected data inputs; when OE is
high, the outputs are in a high-impedance state, This
feature allows shifters to be cascaded on the same output lines or to a common bus, The shift function can be
logical with zeroes pulled in at either or both ends of the
shifting field, arithmetic with the sign bit repeated
during a shift down,' or end-around with the data word
forming a continuous loop.
(TOP VIEW)
<)I
"? u ~o
002>>3 2
2019
II
FUNCTION TABLE
INPUTS
NC - No internal connection
OUTPUTS
OE
51
so
VO
Vl
V2
V3
H
X
X
Z
Z
Z
Z
L
L
L
DO
01
02
03
L
L
H
0·1
DO
01
02
L
H
L
0-2
0·1
DO
01
L
H
H
0-3
0-2
0-1
DO
PRODUCTION DATA d....antl c••bi. i.farmatio.
current I I .f publicltiDn data. Products co.farm ta
specificationl pM' the terms of Ta.l. Instrumlnts
==:~~i~.i~:I:ri ~=::i:;
lIr:::::::.::.-
nat
logic equations
YO = So 51 DO + SO Si 0·1 + SO 51 0-2 + SO 51 0-3
Yl =soSi 01 +505100+50510·1 +50510·2
Y2 = so 51 02 + SO Si 01 + so 51 DO + SO 51 0-1
Y3 = 50 Si 03 + SO Si 02 +
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
so 51 01 + SO 51 DO
2-849
SN54S350, SN74S350
FOUR·BIT SHIFTER WITH THREE·STATE OUTPUTS
logic diagram (positive logic)
logic symbol t
OE
so
(13)
....:..:(1.:::0:"')_-1
S1 ....::;(9c..)--004
(11)
03
02
01
DO
0-1
•
0-2
0-3
(7)
Y3
(6)
(12)
(5)
Y2
(4)
(3)
(14)
(2)
Y1
(1)
....._"'(1,:;5:..)_ YO
16
tThis symbol isin accordance with ANSI/IEEE Std. 91·1984 and
IEC Publication 617-12.
Pin numbers shown are for OW, J, and N packages:
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
-----~-VCC
50n
vCC----~-
NOM
Req
INPUT ...---<....-i
OUTPUT
0-2,02: Req
0-1,01: Req
DO: Req
All other: Req
2-850
= 1.4 kn NOM
= 0.93 kn NOM
= 0.7 kn NOM
= 2.8 kn NOM
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 76265
SN54S350. SN74S350
FOUR·BIT SHIFTER WITH THREE·STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ..•......•..........•..•.•....•.•.•....•.••..•.•.•...•.••.....• 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled 3-state output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range: SN54S350 .......... . . . . . .. ...................... - 55°C to 125°C
SN74S350 ........................................... OoC to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54S350
SN74S350
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
Vee
Supply voltage
V,H
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
IOH
High-level output current
-2
-6.5
mA
20
mA
70
·C
IOL
Low-level output current
TA
Operating free.-air temperature
20
-55
125
V
V
2
2
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONSt
Vee= MIN,
II =-18mA
Vee= MIN,
VIH= 2 V,
Vil = 0.8 V,
VIH - 2 V,
Vil - 0.8 V,
Vee = MIN,
TYP
SN74S350
MAX
2.4
3.4
IOZH
Vee- MAX.
VO=2.4V
50
Vee= MAX,
VO-0.5V
-50
Vee= MAX,
VI=5.5V
01,02 inputs
Vee= MAX,
VI = 2.7 V
All others
0-2.0-1 0-0.
III
01,02 inputs
Vee= MAX.
VI = 0.5 V
All others
IOS§
VCC- MAX.
ICC
VI- 0
Vce- MAX,
All inputs = GNO
3.4
-40
VO- 0
I'A
I'A
75
50
-3
-3
-2
-2
-40
60
...I
lI-
V
50
50
85
V
-50
1
75
-100
60
UNIT
V
0.5
,
0-2,0-1,0-0.
MAX
-1.2
2.4
IOZl
IIH
TYP
0.5
IOl=20mA
II
MIN
-1.2
IOH= MAX
VOL
SN54S350
MIN
mA
IlA
mA
-100
mA
85
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical valuesars at Vee = 5 V. TA = 2SoC.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-851
SN54S350. SN74S350
FOUR·BIT SHIFTER WITH THREE·STATE OUTPUTS
switching characteristics, Vee = 5 V, T A = 25°e (see note 2)
PARAMETER
tPLH
tpHL
tpLH
tpHL
FROM
TO
(INPUT)
(OUTPUT)
Data
Select
TEST CONDITIONS
Any Y
Any Y
RL = 280 n.
CL = 15 pF
MIN
TYP
OE
5
9
ns
12
ns
11
17
ns
13
20
ns
19.5
ns
21
ns
8
13
ns
10
15
ns
Any Y
tpHZ
tpLZ
OE
Any Y
RL=280n.
CL = 5 pF
NOTE 2: load circuits and voltage waveforms are shown in Section 1.
-I
-I
rC
(I)
<
n·
(I)
(II
2-852
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
UNIT
8
tpZH
tpZL
MAX
SN54S350. SN74S350
FOUR·BIT SHIFTER WITH THREE·STATE OUTPUTS
TYPICAL APPLICATION DATA
16·Bit Shift·Up 0 to 3 Places. Zero Backfill
o
~
6 7
8 91011
12131415
~~~~~~8
~~~g~~8
1Fr~ ZZ~g"22
1 2 3
4
TI I
r--
-
I
I
0000000
WN':'O...&NW
SO
S1
,.----
SO
r-- S1
r4 OE YO Y1 Y2 V3
I
I
.--- SO
r-- S1
; - S1
rc OE VO
V1
rC
V2 V3
I
OE VO V1
Y2 V3
rC
OE VO V1 V2 V3
so
S1
OE
o
1
2
3
4
5
8
6
9
10
11
12
13 14
15
S1 SO
L L NO SHIFT
L H SHI FT 1 PLACE
H L SHI FT 2 PLACES
H H SHIFT3PLACES
8·Bit End·Around Shift 0 to 7 Places
o
1 2 3
4 5 6 7
I 11
T
r..lW
-51
roC OEVO
V1 V2 V3
.--50
r-- S1
wr\)':" 0
r--H
2C2 (12)
2C3 (13)
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
~
~
r-
C
CD
<
Ci·
CD
en
Pin numbers shown are for D, J, N, and W packages.
schematic of inputs and outputs
eQUIVALENT OF Gl. G2 INPUTS
EQUIVALENT OF ALL OTHER INPUTS
Vee
10kS'! NOM
---~VCC
20kS'! NOM
VCC19
INPUT
TYPICAL OF BOTH OUTPUTS
INPUT .......~-.OUTPUT
2-860
.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
SN54LS353, SN74LS353
DUAL 4·LlNE TO '·LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3·STATE OUTPUTS
recommended operating conditions
SN54LS353
SN74LS353
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
V
VCC
Supply voltage
V,H
High-level input voltage
V,L
Low-level input voltage
0.7
0.8
2
V
2
IOH
High-level output current
-1
-2.6
mA
IOL
Low-level output current
8
TA
Operating free-air temperature
4
125
mA
·C
-55
70
0
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
V,K
VOH
Vcc =MIN,
1,=-18mA
V,H -2V,
V,L -MAX,
V,H -2V,
IOL =4mA
IOH = MAX
VOL
V,L =MAX
VCC =MAX,
V,H = 2 v
I,
VCC =MAX,
v,-7 V
VCC
"H
I
Gl,Gl
I
All other
3.4
0.25
MIN
TYP* MAX
-1.5
2.4
3.1
0.4
V
0.25
0.4
0.35
0.5
V
20
20
-20
-20
0.1
0.1
mA
20
20
p.A
-0.2
-0.2
VI =O.4V
-0.4
- 30
See Note 2
V
VO=O.4V
V,=2.7V
VCC =MAX,
UNIT
VO=2.7V
VCC=MAX
ICC
t
MAX,
VCC = MAX,
10S§
2.4
TYP* MAX
-1.5
10L =8mA
'OZ
'lL
MIN
VCC =MIN,
VCC =MIN,
SN74LS353
SN54LS353
TEST CONDITIONS t
PARAMETER
-130
-0.4
-30
-130
I
Condition A
7
12
7
12
I
Condition B
8.5
14
8.5
14
p.A
•
mA
mA
mA
For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
t
All typical values are at Vee =: 5 V. T A;; 25° C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with the outputs open under the following conditions;
A. All inputs grounded.
B. Output control at 4.5 V. all inputs grounded.
switching characteristics, Vee
PARAMETER.
tpLH
FROM
TO
(INPUT)
(OUTPUT)
Data
Y
Select
y
tpHL
tpLH
= 5 V, TA = 25°e
tpZH
tpZL
Control
tPHZ
Output
tpLZ
Control
CL=15pF,
RL =2 kn,
See Note 3
tpHL
Output
MIN
TEST CONDITIONS
Y
Y
CL - 5 pF,
RL
=2 kn,
See Note 3
TYP
MAX
11
25
13
20
20
45
21
32
11
23
15
23
27
41
12
27
UNIT
ns
ns
ns
ns
, tPlH = Propagation delay time, low·to·high-Ievel output
tpHl = Propagation delay time, high-to·low-Ievel output
tpZH = Output enable tima to high level
tpZl = Output enable time to low level
tpHZ ... Output disable time from high level
tplZ = Output disable time from low level
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·861
-t
-t
r
C
(1)
<
(i'
(1)
(/I
2-862
SN54LS354, SN54LS355, SN54LS356
SN74LS354, SN74LS355, SN74LS356.
B-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS/REGISTERS
02544, JULY 1979-REVISEO MARCH 1988
•
Transparent Latches on Data Select Inputs
•
Complementary Outputs
•
Easily Expandable
•
High-Density 20-Pin Package
DATA
REGISTERS
'LS354
SN54LS354. SN54LS355 ••• J PACKAGE
SN74LS354, SN74LS355 ... ow OR N PACKAGE
(TOPVIEWI
,.
07
05
17
D2
01
Transparent
3-State
'LS355
Transparent
Open-Coliector
'LS356
Edge-Triggered
3-State
Y
W
G3
3
D4
03
OUTPUTS
vee
,.
• ,.
• ,.
• ,.
06
DO
•'0
Dc
GNO
G2
G,
SO
51
S2
'3
'2
Sc
"
description
SN54LS354, SN54LS355 , , . FK PACKAGE
These monolithic data selectors/multiplexers
contain full on-chip binary decoding to select one
of eight data sources. The data-select address
is stored in transparent latches that are enabled
by a low level on pin 11, SC, On the 'LS354 and
'LS355 a similar enable for data is obtained by
a low level on pin 9, DC, The edge-triggered data
registers of the 'LS356 is clocked by a low-tohigh transition on pin 9, CLK. Complementary
outputs are available in either three-state
versions ('LS354 and 'LS356) or open-collector
version ('LS355).
The SN54LS354 through SN54LS356 are
characterized for operation over the full military
temperature range of - 55°C to 125°C. The
SN74LS354 through SN74LS356 are
characterized for operation from 0 °C to 70°C.
(TOP VIEWI
,.
D4
00
02
•
01
7
DO
•
W
17
G3
16
15
'4
G2
G1
so
fI)
Q)
CJ
'>
9 10 11 12 13
Q)
o
SN54LS356 . , , J OR W PACKAGE
SN74LS356 , , , OW OR N PACKAGE
(TOPVIEWI
,
07
2
3
06
05
D4
00
02
01
•
DO
•
elK
GNO
10
,.,.
,.
20
vee
17
Y
W
G3
...I
....
....
G2
15
Gl
'4
so
51
'3
'2
52
Sc
"
SN54LS356 • , , FK PACKAGE
(TOPVIEWI
u
~ 8 B ~>3
2
1 2019
D4
00
02
01
4
,.
•
17
W
G3
16
15
G2
DO
•
'4
so
G1
9 10111213
PRODUCTION DATA documlnts cantlin informllion
• urrenl as of publulion dill, Prod.cts ••nform 10
specifiClitiaDs par the terms af TI.I. Instruments
::':!~~·:::I~~i ~:~::i:r :'~':a-:::£::~ lot
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-863
SN54LS354. SN54LS355. SN54LS356
SN74LS354. SN74LS355. SN74LS356
B·L1NE TO 1·UNE DATA SELECTORS/MULTIPLEXERS/REGISTERS
FUNCTION TABlE
schematics of inputs and outputs
INPUTS
DATA
SELECT
S2 SI
-of
-of
,...
C
CD
<
ri'
CD
en
X
X
X
X
SO
X
X
X
L
L
L
X
CONTROL
CLOCK
I'LS354.
('LS3561
'LS3651
OUTPUT
EQUIVALENT OF EACH DATA OR SELECT INPUT
OUTPUTS
ENABLES
~1
~2 G3
W
Y
Z
Z
Z
Z
Z
Z
H
DO
00
L
H
L
L
H
DOn OOn
01
01
L
L
H
L
L
H
01n 01n
02 02
X
X
H
X
X
X
X
X
H
X
X
X
X
X
X
L
L
L
t
L
L
L
L
H
H or L
L
L
L
H
L
t
L
L
H
H
H or L
L
H
L
L
t
L
H
L
H
H or l
L
L
L
H
H
L
!
L
L
H
H
02n D2n
03 03
L
H
H
H
H or L
L
L
H
03 n
H
L
L
L
t
L
L
H
04
H
L
L
H
H or l
L
L
H
H
L
H
L
t
L
L
H
H
L
H
H
H or L
L
L
H
H
H
L
L
t
L
L
H
H
H
L
H
H or L
L
L
H
H
H
H
L
t
L
L
H
H
H
H
H
H or l
L
L
H
VCC---
90
(19)
90
\l
90
3
90
4
90
5
90
6
90
7
(1)
17)
02 (6)
y
03 (5)
04 (4)
(3)
05
06 (2)
W
0
07 (1)
~
1
I>
90
90
2
90
3
90
4
90
5
90
6
90
7
0
(19)
y
•
en
CI)
W
(.)
'$
CI)
C
-I
~
~
'lS356
MUX
EN
S2
ClK (9)
00
01
(8)
90
0
(7)
' 1
[>
90
(6)
02
03 (5)
90
2
90
3
(19)
\l
y
(4)
04
(3)
05
06 (2)
07
90
4
90
5
90
6
W
(1)
90
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12.
Pin numbers shown are for OW, J, N, and W packages.
TEXAS .."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-865
SN54LS354. SN54LS355. SN74LS354. SN74LS355
B·LlNE TO 1·LlNE DATA SELECTORSIMULTIPLEXERSIREGISTERS
logic diagram (positive logic)
'LS354, 'LS355
OUTPUT
ENABLES
OATA
SELECT
(BINARYI
-I
-I
r
C
CD
<
c:;'
CD
en
DATA
INPUTS
Pin numbers shown are for OW, J and N packages.
2-866
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN54LS356. SN74LS356
B·LlNE TO l·LlNE DATA SELECTORS/MULTIPLEXERS/REGISTERS
logic diagram (positive logic)
'LS356
G1 ':":'::;'-------,
E~~~LUE~ G2 "-'-"'-----<4
G3
DATA
SELECT
(BINARYI
Sl (131
S2 (121
DO
01
02 (61
03 (51
DATA
INPUTS
D4 (41
05
(31
D6 (21
07
Pin numbers shown are for OW, J, N. and W packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TeXAS 75265
2-867
SN54LS354, SN54LS356,SN14LS354, SN14LS356
8~L1NE TO 1·L1NE DATA SelECTORS/MULTIPLEXERS/REGISTERS
WITH 3·STATE OUTPUTS
recommended operating conditions
SN74LS354
SN54LS354
SN54LS366
Vee Supply voltage
High·lo.el input .oltage
VIL
IOH
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
2
VIH
Low-level output current
Isu
Setup timos, high·o,·low·lo.el data (with respect to t at pin 9)
th
Hold times, hlgh-o,·low·lo.el data (with ,espact to t at pin 9)
TA
Operating free-air temperature
0.8
-2.6
24
'LS354
15
15
'LS356
15
15
'LS354
15
15
'LS356
0
V
mA
mA
ns
nS
0
125
-55
V
V
0.7
-1
12
Low-level input voltage
High-level output current
IOL
UNIT
SN74LS366
MIN
70
0
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN74LS354
SN54LS354
PARAMETER
-I
-I
TEST eONOITIONst
SN54LS356
MIN
r-
VIK
C
VOH
<
VOL
CD
n'
CD
(I)
Vee· MIN,
II =-lamA
Vee=MIN,
VIH = 2 V,
VIL
IOH = MAX,
Vee-MIN,
VIH = 2 V,
IOL=12mA
VIL = MAX
= MAX
UNIT
SN74LS366
TYP* MAX
-1.5
2.4
MIN
TYP* MAX
-1.5
2.4
0.25
IOL =24mA
VO=2.7V
VO=0.4V
0.4
V
V
0.25
0.4
0.35
0.5
V
20
-20
20
-20
/lA
IOZ
Vee= MAX
II
Vee· MAX,
VI = 7 V
0.1
0.1
rnA
IIH
Vee = MAX,
VI - 2.7 V
20
20
/lA
Vee· MAX,
VI· 0.4 V
-0.2
-0.2
mA
-0.4
-130
-0.4
-130
mA
46
mA
1~~eLK,
IlL
Gt, G2,G3
I All others
IOS§
Vee= MAX
lee
Vee=MAX,
-30
Soe Note 2
29
46
-30
29
t For conditions shown as MIN or MAX. ule the appropriate values specified under recommended operating conditions.
*All typical values are at Vee'" 5 V. T A = 26 C.
0
§ Not more than one Qutput should be shorted at a time, and duration of the short-circuit should not exceed on8 second.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.
2-868
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
SN54LS354, SN54LS356, SN74LS354, SN74LS356
B·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS/REGISTERS
WITH 3·STATE OUTPUTS
switching characteristics, Vee
PARAMETER
FROM
(INPUT)
tpLH
tpHL
tPLH
tpHL
tPLH
OC
CLK
tpLH
36
23
35
TYP
MAX
28
42
18
27
26
39
33
50
22
33
24
36
33
50
18
27
CL = 45 pF,
29
44
30
45
See Note 3
24
45
28
48
28
42
36
54
34
51
30
45
34
51
36
54
31
47
40
60
Y
5C
ns
27
41
32
48
40
60
36
54
tPZH
14
27
14
25
tpZL
18
27
17
25
15
25
16
24
W
tpHL
Y
tPHZ
tPLZ
tpZH
G1,G2
tpZL
W
tPHZ
CL = 5 pF,
See Note 3
15
25
16
24
CL=45pF,
12
24
14
23
See Note 3
16
24
16
23
15
25
16
23
CL=5pF,
tPLZ
See Note 3
15
25
16
23
tPZH
CL-45pF,
15
29
15
27
See Note 3
19
29.
18
27
CL - 5 pF,
15
25
16
25
tpZL
Y
tpHZ
tpLZ
tpZH
tPZL
tpHZ
tPLZ
G3
W
See Note 3
15
25
16
25
CL=45pF,
13
25
14
25
See Note 3
17
25
16
25
CL - 5pF,
15
25
16
25
15
25
16
25
See Note 3
-
UNIT
ns
27
W
tpLH
24
MIN
44
W
y
MAX
18
Y
50,5152
'LS356
TYP
29
or
tpHL
tpHL
'LS354
MIN
W
tpLH
tpHL
TEST
CONDITIONS
Y
tPHL
tpHL
TO
(OUTPUT)
00-07
tPLH
tpLH
= 5 V, TA = 25°e, RL = 667 n
ns
ns
ns
ns
ns
ns
CII
ns
ns
Q)
.s:CJ
Q)
C
ns
ns
..J
lI-
ns
ns
ns
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-869
SN54LS355,SN74LS355
B·LlNE TO 1·LlNE DATA SELECTORS/MULTIPLEXERS/REGISTERS
WITH OPEN·COLLECTOR OUTPUTS
recommended operating conditions
SN54LS355
SN74LS355
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.7
0.8
VOH
High-level output voltage
5.5
5.5
V
IOL
Low-level output current
12
24
mA
2
2
V
V
V
tsu
Setup times, high-or-Iow-Ievel data, (with respect to I at pin 9)
15
15
ns
th
Hold times, high-or low-level data (with respect to I at pin 9)
15
15
ns
TA
Operating free-air temperature
-55
125
0
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
VIK
IOH
-I
-I
r-
VOL
C
(1)
II
IIH
Cr
IlL
<
Vee = MIN,
11=-18mA
Vee - MIN,
VIH = 2 V,
TYP*
VIL - MAX
VOH=5.5V
Vee = MIN,
VIH=2V,
VIL = MAX
SN74LS355
SN54LS355
TEST eONDITIONSt
IIOL -12mA
0.25
-1.5
0.1
0.1
0.4
IIOL-24mA
MIN
UNIT
TYP* MAX
-1.5
MAX
0.25
0.4
0.35
0.5
V
mA
V
0.1
mA
20
I'A
-0.2
- 0.2
mA
- 0.4
-0.4
0.1
Vee = MAX,
VI = 7 V
Vee = MAX,
VI = 2.7 V
20
Vee= MAX,
VI = 0.4 V
l~e~eLK,
Gl, G2, G3
I All others
(1)
en
lee
Vee = MAX,
See Note 2
29
46
29
46
mA
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operatmg conditions for the applIcable type.
t
All typical values are at Vee'" 5 V, T A
NOTE 2:
2-870
=
25°C.
ICC is measured with the inputs grounded and the outputs open.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS355, SN74LS355
B·LlNE TO '·LlNE DATA SELECTORS/MULTIPLEXERS/REGISTERS
WITH OPEN·COLLECTOR OUTPUTS
switching characteristics. Vee - 5 V. T A .. 25°e. RL - 667 {}
PARAMETER
FROM
(INPUT)
tpLH
tpHL
Y
W
tpHL
tpHL
tpLH
tpHL
DC
CLK
y
W
tpLH
tpLH
Y
W
tpHL
tpLH
y
~1, "G2
W
tpHL
tpLH
tPHL
tpLH
tpHL
CL = 45 pF,
See Note 3
5C
tpHL
tpHL
W
50,51,52
tpHL
tpHL
y
or
tpLH
tPHL
tpLH
TEST
CONOITIONS
00-07
tpLH
tpLH
TO
(OUTPUT)
Y
G3
W
'LS355
MIN
TYP
MAX
34
41
26
30
39
45
33
50
38
31
57
47
33
50
39
59
39
59
36
49
32
48
39
58
45
68
42
63
44
66
45
68
21
22
32
33
18
27
19
29
24
36
25
40
19
31
19
29
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
•
ns
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
2-871
-I
-I
r-
C
(1)
:::.
n
(1)
C/)
2-872
SN54365A THRU SN54368A, SN54LS365A THRU SN54LS368A
SN74365A THRU SN74368A, SN74LS365A THRU SN74LS36BA
HEX BUS DRIVERS WITH 3·STATE OUTPUTS
DECEMBER 1983-REVISEO MARCH 1988
•
3-State Outputs Drive Bus Lines Dr Buffer
Memory Address Registers
•
Choice of True or Inverting Outputs
•
Package Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers
and Flat Packages, and Plastic and Ceramic
DIPs
•
SN54365A, 366A, SN54LS365A, 366A ... J PACKAGE
SN74365A, 366A ... N PACKAGE
SN74LS365A, SN74LS366A ... 0 OR N PACKAGE
(TOPVIEWI
G1
A1
Y1
A2
Y2
A3
Y3
GND
Dependable Texas Instruments Quality and
Reliability
'365A, '367A, 'LS365A, 'LS367A True
Outputs '366A, '368A, 'LS366A, 'LS368A
Inverting Outputs
VCC
G2
A6
Y6
A5
Y5
A4
Y4
SN54LS365A, SN54LS366A ... FK PACKAGE
(TOPVIEWI
description
U
::(It;
These Hex buffers and line drivers are designed
specifically to improve both the performance and
density of three-state memory address drivers, clock
drivers, and bus oriented receivers and transmitters.
The designer has choice of selected combinations of
inverting and noninverting outputs, symmetrical G
(active-low control) inputs.
Yl
A2
Y2
A3
~ ~I~
4
5
6
7
8
(I)
NC
Q)
~~~)!:~
...J
(!l
The SN54365A thru SN54368A and SN54LS365A
thru SN54LS368A are characterized for operation
over the full military temperature range of - 55°C to
125°C. The SN74365A thru SN74368A and
SN74LS365A thru SN74LS368A are characterized for
operation from ooC to 70°C.
CJ
'>
C
These devices feature high fan-out, improved fan-in,
and can be used to drive terminated lines down to
133 ohms.
Q)
SN54367A, 368A, SN54LS367A, 368A ... J PACKAGE
SN74367A, 368A •.. N PACKAGE
SN74LS367A, SN74LS368A ... 0 OR N PACKAGE
....
....
(TOPVIEWI
1G
lAl
lY1
lA2
lY2
1A3
lY3
GND
VJ:;C
2G
2A2
2Y2
2Al
2Yl
lA4
1Y4
SN54LS367A. SN54LS368A ... FK PACKAGE
(TOPVIEWI
u
~
~I~~ ~I~
3
2
1 2019
lYl
1A2
NC
lY2
lA3
2A2
2Y2
NC
2Al
2Yl
9 10111213
NC - No internal connection
~ (!l
~~)!: ~
~
~
~
PRODUCTION DATA documants contain information
current IS of publication data. Products conform to
specifications per the terms of Texas Instruments
::~~:~~i~a{::I~'e ~~:~~~ti:r :lr:::::t:~~S nol
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-873
SN54365A THRU SN54368A, SN54LS365A THRU SN54LS368A
SN74365A THRU SN74368A, SN74LS365A THRU SN74LS368A
HEX BUS DRIVERS WITH 3·STATE OUTPUTS
schematics of inputs and outputs
'365A thru '368A
EQUIVALENT OF ALL INPUTS
TYPICAL OF ALL OUTPUTS
VCC--'--
VCC
INPUT
OUTPUT
'LS365A thru 'LS368A
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF ALL G INPUTS
EQUIVALENT OF ALL DATA INPUTS
---+-VCC
VCC
VCC--......- -
18 kfl NOM
-I
-I
r-
INPUT
INPUT
C
OUTPUT
(I)
<
C:;'
(I)
(I)
logic diagrams (positive logic)
'365A, 'LS365A
'366A, 'LS366A
'368A, 'LS368A
'367A, 'LS367A
(1)
'Gl (1)
<31
02
G2
AI
AI
VI
lAl
(3) lVl
lAl
lVl
A2
A2
V2
lA2
(5) lV2
lA2
lV2
A3
A3
Y3
lA3
(7) lV3
lA3
lY3
A4
A4
V4
lA4
lA4
lY4
A5
A5
V5
2G
A6
A6
V6
2Al
2Al
(11) 2Yl
10
2A2
Pin numbers shown are for 0, J, and N packages.
2·874
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
(11) 2Yl
2A2
SN54365.A THRU SN54368A, SN54LS365A THRU SN54LS368A
SN74365A THRU SN74368A, SN74LS365A THRU SN74LS368A
HEX BUS DRIVERS WITH 3·STATE OUTPUTS
logic symbols t
'365A
'366A
G1
G2
A1
A2
A3
A4
A5
A6
G1
G2
(31
Y1
(51
Y2
(71
Y3
(91
Y4
Y5
Y6
(41
(61
(101
(121
(141
Y1
Y2
Y3
A1
(41
A2
(61
A3
(101
A4 (121
A5
A6 (141
Y4
Y5
V6
'368A
'367A
(I)
1G
1G
1A1
1Y1
1Y2
1A2
1A3
1A4
1Y3
1Y4
1A1
1A2
1A3
1A4
Go)
(.)
'S
1Y1
Go)
1Y2
1Y3
1Y4
C
-I
II-
2G
2(;
2A1
2Y1
2A2
2Y2
2Y1
2Y2
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D. J, and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage: '365A, '366A, '367A, '368A ... .. .. . . .. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. 5.5 V
'LS365A, 'LS366A, 'LS367 A, 'LS368A .............................................. 7 V
Voltage applied to a disabled 3-state output ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature: SN54'................................................ - 55°C to 125°C
SN74' .................................................... oOe to 70°C
Storage temperature range ......................................................... - 65°C to 150°C
NOTE1: Voltage values are with respect to network ground terminal,
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-875
SN54365A, SN54367A
SN74365A, SN74367A
HEX BUS DRIVERS WITH 3·STATE OUTPUTS
recommended operating conditions
SN74365A
SN74367A
SN54365A
SN54367A
Vee
Supply voltage
VIH
High-level input voltage
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
VIL
Low-level input voltage
0.8
0.8
10H
High.level output current
-2
- 5.2
10L
Low-level output current
TA
Operating free-air temperature
32
- 55
125
V
V
2
0
V
rnA
32
rnA
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
•
PARAMETER
SN54365A
SN54367A
TESTCONOITIONSt
MIN
VIK
-t
-t
Vee= MIN,
II =-12mA
Vee = MIN,
VIH=2V,
TVP*
SN74365A
SN74367A
MAX
MIN
TVP*
-1.5
UNIT
MAX
-1.5
V
VIL = 0.8 V,
2.4
VOH
3.3
2.4
3.1
V
10H = MAX
,...
Vee= MIN,
VIH = 2 V,
VIL = 0.8 V,
VOL
C
0.4
0.4
40
40
-40
-40
V
IOL=32mA
CD
<
c:r
CD
Vee= MAX,
VIH=2V,
VIL = 0.8 V,
VO=2.4V
/lA
10Z
en
vee = MAX,
VIH = 2 V
VIL=0.8V,
VO=O.4V
II
Vee = MAX,
VI = 5.5 V
1
1
mA
IIH
Vee= MAX,
VI=2.4V
40
40
/lA
Vee = MAX,
VI = 0.5 V,
Either G input at 2 V
-40
-40
/lA
Vee = MAX,
VI = 0.4 V,
Both
-1.6
- 1.6
Vee= MAX,
VI = 0.4 V
-1.6
-1.6
A Inputs
IlL
G Inputs
G inputs at 0.4
V
rnA
10S§
Vee = MAX
ICC
Vee = MAX,
-40
Data inputs"" 0 V,
Output controls'" 4.5 V
- 130
65
-40
85
65
-130
rnA
85
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at Vee = 5 V, T A::: 2SoC.
§ Not more than one output should be shorted at a time.
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
FROM
TO
UNPUTI
(OUTPUTI
PARAMETER
TEST CONDITIONS
TVP
MAX
UNIT
tPLH
16
ns
tPHL
22
ns
35
ns
tpZL
37
ns
tpHZ
11
ns
27
ns
tpZH
RL=400n,
Any
eL = 50 pF
Y
RL =400 n,
eL = 5 pF
tpLZ
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2-876
MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54366A, SN54368A
SN74366A, SN74368A
HEX BUS DRIVERS WITH 3-STATE OUTPUTS
recommended operating conditions
SN54366A
SN54368A
Vee
Supply voltage
VIH
High·level input voltage
SN74366A
SN74368A
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
VIL
Low-level input voltage
0.8
0.8
IOH
High-level output current
-2
- 5.2
IOL
Low-level output current
TA
Operating free-air temperature
32
- 55
125
V
V
2
0
V
mA
32
mA
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
SN54366A
SN54368A
TEST eONOITIONSt
MIN
VIK
Vee = MIN,
11=-12mA
Vee = MIN,
VIH=2V,
TVP*
SN74366A
SN74368A
MAX
MIN
TVP*
UNIT
MAX
-1.5
-1.5
V
VIL = 0.8 V,
2.4
VOH
3.3
2.4
V
3.1
til
IOH = MAX
Vee = MIN,
VIH = 2 V,
Q)
(.)
VIL=0.8V,
0.4
VOL
0.4
-S;
V
IOL = 32 mA
Vee = MAX,
Q)
VIH=2V,
C
VIL=0.8V,
40
40
..oJ
Vo = 2.4 V
lI-
jlA
IOZ
Vee = MAX,
VIH = 2 V
VIL = 0.8 V,
-40
-40
VO= 0.4 V
II
Vce= MAX,
VI = 5.5 V
1
1
mA
IIH
Vee = MAX,
VI = 2.4 V
40
40
jlA
Vee = MAX,
VI = 0.5 V,
Either
-40
-40
IJ,A
Vee = MAX,
VI = 0.4 V,
Both G inputs at 0.4 V
-1.6
-1.6
Vee= MAX,
VI e 0.4 V
-1.6
-1.6
G input at
2 V
A Inputs
IlL
G Inputs
t
IOS§
Vee = MAX
lee
Vee = MAX,
-40
Data inputs = 0 V,
Output controls"" 4.5 V,
-130
59
- 40
59
77
rnA
-130
mA
77
mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions'l
t
All typical values are at Vee = 5 V, T A"" 2SoC.
§ Not more than one output should be shorted at a time.
switching characteristics, Vee = 5 V, TA = 25°e (see note 2)
FROM
TO
(lNPUTI
(OUTPUT!
PARAMETER
TEST CONDITIONS
MIN
TVP
MAX
UNIT
tpLH
17
ns
tPHL
16
ns
RL =400
n,
eL=50pF
35
ns
tPZL
37
ns
tpHZ
11
ns
27
ns
tpZH
Any
V
RL·=400
n,
eL = 5 pF
tPLZ
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-877
SN54LS365A. SN54LS367A
SN74LS365A. SN74LS367A
HEX BUS DRIVERS WITH 3-STATE OUTPUTS
reGPmmended operating conditions
SN54LS365A
SN54LS367A
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
SN74 LS365A
SN74LS367A
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
IOL
Low-level output current
Operating free-air temperature
0.7
O.B
-1
- 2.6
12
- 55
125
V
V
2
2
TA
UNIT
MIN
0
V
mA
24
mA
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
VIK
Vee= MIN,
11=-1BmA
Vee= MIN,
VIH=2V,
SN74 LS365A
SN74LS367A
SN54LS365A
SN54LS367A
TEST CONDITIONSt
TYP*
MAX
MIN
TYP*
-1.5
UNIT
MAX
-1.5
V
VIL = MAX,
2.4
VOH
2.4
3.3
V
3.1
10H = MAX
Vee = MIN,
VIL = MAX,
VIH=2V,
0.25
0.4
0.25
0.4
0.35
0.5
IOL=12mA
V
VOL
Vee= MIN,
VIH = 2 V,
VIL=O.BV,
IOL=24mA
Vee= MAX,
VIH = 2 V,
VIL = MAX,
20
20
- 20
- 20
0.1
0.1
mA
20
20
I'A
- 20
-20
I'A
-0.4
- 0.4
-0.2
- 0.2
VO=2.4V
I'A
10Z
Vee = MAX,
VIH=2V,
VIL = MAX,
Vo=O.4V
II
Vee= MAX,
VI = 7 V
IIH
Vee = MAX,
VI=2.7V
Vee= MAX,
VI = 0.5 V,
Either
Vee = MAX,
VI = 0.4 V,
Both G input. at 0.4 V
Vee= MAX,
VI = 0.4 V
G input at 2
V
A Input.
IlL
Glnput.
10S§
Vee= MAX
ICC
Vee= MAX,
-40
Data inputs = 0 V,
Output controls
= 4.5 V,
t
- 225
14
24
mA
-40
14
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
t
2-878
TEXAS . "
INSTR.UMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
- 225
mA
24
mA
SN54LS365A. SN54LS361A
SN14LS365A. SN14LS361A
HEX BUS DRIVERS WITH 3·STATE OUTPUTS
switching characteristics, Vee = S V, T A = 2Soe (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tpLH
10
16
ns
tpHL
9
22
ns
19
35
ns
24
40
ns
30
ns
35
ns
RL=667n,
tpZH
Any
CL = 45 pF
y
tpZL
tpHZ
RL =667 n,
CL = 5 pF
tPLZ
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·879
SN54LS366A. SN54LS36BA
SN74LS366A.SN74LS3IiBA
HEX BUS DRIVERS WITH 3-STATE OUTPUTS
recommended operating conditions
SN74LS366A
SN74LS366A
SN54LS366A
SN54LS366A
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.7
0.8
IOH
High-level output current
-1
- 2.6
12
IOL
Low-level output current
TA
Operating free-air temperature
125
- 55
V
V
2
2
0
V
mA
24
mA
70
°e
.electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS366A
SN54LS368A
TEST eONOITIONS t
PARAMETER
MIN
-I
-I
rC
VIK
Vee = MIN,
11=-18mA
Vee = MIN,
VIH = 2 V,
TYP*
SN74 LS366A
SN74LS368A
MAX
MIN
TYP*
-1.5
UNIT
MAX
-1.5
V
VIL= MAX,
2.4
VOH
3.3
2.4
V
3.1
IOH = MAX
CD
Vee= MIN,
~C')
VIH = 2 V,
VIL = MAX,
0.25
0.4
0.25
0.4
0.35
0.5
IOL=12mA
V
VOL
CD
Vee = MIN,
(II
VIH = 2 V,
VIL = 0.8 V,
10L = 24 mA
Vee = MAX,
VIH = 2 V,
VIL = MAX,
20
20
- 20
- 20
0.1
0.1
mA
20
20
"A
- 20
- 20
uA
-0.4
-0.4
- 0.2
-0.2
Vo= 2.4 V
10Z
Vee= MAX,
VIH=2V,
"A
VIL = MAX,
Vo= 0.4 V
II
Vee = MAX,
VI = 7 V
IIH
Vee = MAX,
VI = 2.7 V
Vee = MAX,
VI = 0.5 V,
Either G input at 2 V
Vee = MAX,
VI = 0.4 V,
Both G inputs at 0.4 V
Vee= MAX,
VI=O.4V
A'inputs
IlL
G Inputs
10S§
Vee = MAX
ICC
Vee= MAX,
mA
-40
Data inputs
= 0 V,
Output controls = 4.5 V,
t For conditions shown as MIN or MAX, use the appropriate value specified
:t. All typical values are at Vee = 5 V. T A = 25°C.
- 225
12
-40
21
12
under recommended operating conditions.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
2-880
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
-225
mA
21
mA
SN54LS366A, SN54LS368A
SN74LS366A, SN74LS368A
HEX BUS DRIVERS WITH 3·STATE OUTPUTS
switching characteristics, Vee
=5 V, TA =25"e (see note 2)
FROM
TO
(INPUT)
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tPLH
7
15
ns
tPHL
12
18
ns
18
35
ns
28
45
ns
32
ns
35
ns
tpZH
RL~667n,
Any
.CL
~45pF
y
tpZL
tpHZ
RL
~
667 n,
CL
~
UNIT
5 pF
tPLZ
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
U)
Q)
(J
·S
Q)
o
-J
lI-
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
2-881
2-882
SN54LS373. SN54LS374. SN54S373. SN54S374.
SN74LS373. SN74LS374. SN74S373. SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
OCTOBER 1975-REVISEO MARCH 19B8
SN54LS373, SN54LS374, SN54S373,
SN54S374 ••• J OR W PACKAGE
SN74LS373, SN74LS374, SN74S373,
SN74S374 ... OW OR N PACKAGE
• Choice of 8 Latches or 8 OoType Flip-Flops
In a Single Package
• 3-State Bus-Driving Outputs
ITOPVIEWI
• Full Parallel-Access for Loading
oe
• Buffered Control Inputs
• Clock/Enable Input Has Hysteresis to
Improve Noise Rejection ('S373 and 'S3741
• P-N-P Inputs Reduce O-C Loading on
Data Lines ('S373 and 'S3741
'LS373, 'S373
FUNCTION TABLE
OUTPUT
ENABLE
ENABLE
LATCH
0
OUTPUT
H
Vee
so
10
10
20
20
30
3D
40
40
GNO
SO
70
70
60
60
50
50
t
e
L
H
H
L
H
L
L
L
L
X
00
SN54LS373, SN54LS374, SN54S373,
SN54S374 ... FK PACKAGE
H
X
X
Z
ITOPVIEWI
e ~Ig ~g
'LS374, 'S374
FUNCTION TABLE
OUTPUT
ENABLE
L
L
L
H
en
Q)
(.)
u
oS;
Q)
C
CLOCK
0
OUTPUT
t
t
H
H
L
L
L
X
00
X
X
Z
....I
lI60
description
These S-bit registers feature three-state outputs
designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance
third state and increased high-logic-level drive provide
these registers with the capability of being connected
directly to and driving the bus lines in a bus-organized
system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers.
tc for 'LS373 and 'S373; ClK for 'lS374 and '5374.
The eight latches of the 'L5373 and '5373 are
transparent O-type latches meaning that while the
enable (el is high the 0 outputs will follow the data (D)
inputs, When the enable is taken low the output will be
latched at the level of the data that was set up.
PRODUCTION DATA d.......to ••ntain inf.rmati.n
current 8S of publicatioR date. Products conform to
S~ic8tiDnl par the terms af Texas Instruments
:=::=i;ai~:1~7~ ~!:t1:~ti:fn :.~u:.e;::A:~~S
nat
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-883
SN54LS373, SN54LS314, SN54S313, SN54S314,
SN14LS313, SN14LS314, SN14S313, SN14S314
OCTAL D·TYPE TRANSPARENT LATCHES AND EDGE·TRIGGERED FLlp·FLOPS
description (continued)
The eight flip-flops of the 'LS374 and 'S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q
outputs will be set to the logic states that were setup at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the 'S373 and 'S374 devices, simplify system design as ac and dc
noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output control input can be used to
place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the highimpedance state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or
new data can be entered even while the outputs are off.
logic diagrams (positive logic)
'lS373, 'S373
'lS374, 'S374
TRANSPARENT LATCHES
POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
Dc
111
ClK 1111
10
20...;1...;.41'--_+-1
141
20-'-'-'---+-1
3D 171
3D 171
40.:.1;:;81~_+-I
40.:.I;:;SI~_+-I
50 1131
50 1131
60 1141
60 1141
70 1171
70 1171
SO I1SI
SO 11S1
Dfor 'S373 only
Dfor ·S374 only
Pin numbers shown are "for DW, J, N, and W packages.
2·884
10
10 131
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN54LS373, SN54LS374, SN74LS373, SN74LS374
OCTAL D·TYPE TRANSPARENT LATCHES AND
EDGE·TRIGGERED FLlp·FLOPS
schematic of inputs and outputs
(
EQUIVALENT OF DATA INPUTS
VCC--"'--
'LS373
EQUIVALENT OF ENABLE AND
OUTPUT CONTROL INPUTS
VCC-----~~----
17 kO NOM
Req = 20kO NOM
TYPICAL OF ALL OUTPlITS
----4"'""""VCC
1000 NOM
INPUT
INPUT ....1+....-
.....
II)
Q)
U
'SQ)
C
'LS374
EQUIVALENT OF
DATA INPUTS
VCC..,....-. . .- -
EQUIVALENT OF CLOCK
AND OUTPUT CONTROL INPUTS
VCC------~~----
17 kO NOM
30kO NOM
......
..J
TYPICAL OF ALL OUTPUTS
----4","""" vee
1000 NOM
INPUT
INPUT ....14'...-
...-
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
2·885
SN54LS373, SN54LS374, SN74LS373, SN74LS374
OCTAL D·TYPE TRANSPARENT LATCHES AND
EDGE· TRIGGERED FLlP·FLOPS
absolut!l maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage
Off·state output voltage
Operating free-air temperature range: SN54LS'
SN74LS'
Storage temperature range
7V
7V
5.5V
_55°e to 125°e
oOe to 700e
_65°e to 1500 e
NOTE 1: VOltage values are with respect to network ground terminal.
recommended operating conditions
SN54lS'
Vee
SN74lS'
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
Supply voltage
VOH High-level output voltage
10H High-level output current
10l
Low-level output current
tw
Pulse duration
-f
-f
r-
tsu
Data setup time
C
th
CD
<
c:;"
CD
TA
-1
-2.6
mA
24
mA
15
15
elK low
15
15
'lS373
5+
5+
'lS374
20f
20f
'LS373
20+
20+
5f
Of
Operating free-air temperature
-55
V
5.5
elK high
'LS374 t
V
5.5
12
Data hold time
UNIT
MIN
125
ns
ns
ns
0
°e
70
tThe th specification applies only for data frequency below 10 MHz. Designs above 10 MHz should use a minimum of 5 ns. (Commercial only)
C/I
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
TEST CONDITIONSt
Vee - MIN,
11- -18mA
Vee=MIN,
VIH=2V,
2.4
VIL =VILmax,IOH = MAX
Vee=MIN,
Low-level output voltage
10ZH
Off-state output current,
high-level voltage applied
Vo = 2.7 V
Off-state output current,
Vee = MAX,
low-level voltage applied
Vo = 0.4 V
VIH=2V,
VIL = VILmax
Input current at
TYP:j:
SN74lS'
MAX
2
VOL
10ZL
SN54LS'
MIN
Vee = MAX,
TYP:j:
MAX
0.7
0.8
V
-1.5
-1.5
V
3.4
2.4
0.4
iloL - 24 rnA
VIH = 2 V,
VIH=2V,
UNIT
V
2
0.25
IIOL=12rnA
MIN
V
3.1
0.25
0.4
0.35
0.5
V
20
20
~A
-20
-20
~A
rnA
Vee = MAX,
VI =7 V
0.1
0.1
IIH
High-level input current
Vee=MAX,
VI = 2.7 V
20
20
~A
IlL
Low-level input current
Vee- MAX,
VI = 0.4 V
-0.4
-0.4
rnA
lOS
Short-circuit output current §
Vee=MAX
-130
rnA
II
lee
maximum input voltage
Supply current
-130
-30
-30
Vee= MAX,
i'LS373
24
40
24
40
Output control at 4.5 V
I'LS374
27
40
27
40
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee"" 5 V, T A = 2SoC.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
2-886
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
rnA
SN54LS373, SN54LS374, SN74LS373, SN74LS374
OCTAL D·TYPE TRANSPARENT LATCHES AND
EDGE·TRIGGERED FLlp·FLOPS
switching characteristics.
PARAMETER
Vee
= 5
FROM
TO
(INPUT)
(OUTPUT)
V.
TA
TEST CONDITIONS
'LS374
'LS373
MIN
TYP
MAX
f max
tpLH
Data
tpLH
Clock or
tpHL
enable
tpZH
Output
tpZL
Control
Output
tPHZ
Control
Output
tpLZ
Control
Any Q
Any Q
MAX
UNIT
MHz
12
18
20
30
15
28
18
30
19
28
15
28
20
26
25
36
21
28
15
25
15
28
ns
12
20
12
20
ns
See Notes 2 and 3
Any Q
50
18
CL = 45 pF, RL = 667 !l
Any Q
TYP
35
12
Any Q
tPHL
MIN
CL = 5 pF, RL = 667 !l
See Note 3
NOTES: 2. Maximum clock frequency is tested with all outputs loaded.
3. Load circuits and voltage waveforms are shown in Section 1.
f max ;;;;; maximum clock frequency
tpLH == propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output
tpZH '" output enable time to high level
tpZL == output enable time to low level
tpHZ '" output disable time from high level
tpLZ 5: output disable time from low level
ns
ns
ns
I/)
CI)
(.)
'S
CI)
C
...J
lI-
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·887
8N548373, 8N548374, 8N748373; 8N748374
OCTAL O-TYPE TRAN8PARENT LATCHE8 AND
EOGE~TRIGGEREO FLiP-FLOP8
schematic of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
-------.~--VCC
50.11
NOM
Vcc-------------e------2.8 kn
NOM
OUTPUT
INPUT _",_+--1
-I
-I
r-
C
CD
<
(;'
CD
en
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
•
Supply voltage, Vee (see Note 1)
Input voltage . . . . . .
Off-state output voltage
Operating free·air temperature range: SN54S'
SN74S'
Storage temperature range
7V
5.5 V
5.5 V
_55°C til 125°C
O°C to 70°C
_65°C to 150°C
NOTE 1: Voltage values are with rHpect to network ground terminal.
recommended operating conditions
SN74S'
SN54S'
Supply voltage, VCC
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.6
4.75
5
6.25
High-Iavel output voltage, VOH
5.5
5.5
High~avel
-2
-6.5
output current, IOH
Width of Clock/enable pulse, tw
Data setup time, tlU
Data hold time, th
Operating free--air temperature, T A
2-888
High
Low
'1373
'S374
'S373
'1374
6
6
7.3
7.3
O.j.
O.j.
51
10.j.
51
10.j.
21
-55
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALI.AS. TEXAS 75265
0
V
V
mA
n.
ns
ns
2t
125
UNIT
70
°c
SN54S373, SN54S374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONSt
MIN
TYP*
MAX
UNIT
2
VIH
V
0.8
V
-1.2
V
Vil
VIK
VOH
I
SN54S'
I
SN74S'
Vee
~
MIN,
II
~
Vee
~
MIN,
VIH
2 V,
Vil
~
0.8 V,
IOH
~
MIN,
~
0.8 V,
IOl ~ 20 mA
-18 mA
~
~
MAX
2.4
3.4
2.4
3.1
V
VOL
Vee
VIH ~ 2 V,
Vil
IOZH
Vee ~ MAX,
VIH ~ 2 V,
Vo
~
2.4 V
50
IOZl
II
Vee - MAX,
VIH ~ 2 V,
VI ~ 5.5 V
Vo
~
0.5 V
-50
~A
Vee ~ MAX,
1
mA
~A
0.5
V
~A
IIH
Vee ~ MAX,
VI
~
2.7 V
50
III
Vee - MAX,
VI
~
0.5 V
-250
~A
IOS§
Vee ~ MAX
-100
mA
-40
outputs high
'S373
Vee ~ MAX
lee
'S374
160
outputs low
160
outputs disabled
190
outputs high
outputs low
140
outputs disabled
160
110
elK and oe at 4 V, 0 inputs at 0 V
mA
(/)
Q)
CJ
'S
180
Q)
o
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*AII typical values are at Vee ~ 5 V, TA ~ 25°e.
§Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
...I
lI-
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER
FROM
(INPUT)
TO
TEST CONDITIONS
(OUTPUT)
'8373
'8374
MIN TYP MAX
MIN TVP MAX
f max
tPlH
tpHl
75
Data
tPLH
Clock or
tPHl
enable
tPZH
Output
IPZl
Control
IPHZ
Output
tPLZ
Control
7
Any Q
Cl~15pF, Rl~280n,
Any Q
See Notes 2 and 4
Any Q
AnyQ
el
~
5 pF,
Rl
~
280 n,
See Note 3
100
UNIT
MHz
12
ns
7
12
7
14
8
15
12
18
11
17
8
15
8
15
11
18
11
18
6
9
5
9
8
12
7
12
ns
ns
ns
NOTES: 2. Maximum clock frequency is tested with all outputs loaded.
4. Load circuits and voltage waveforms are shown in Section 1.
f max 5: maximum clock frequency
tPlH "propagation delay time, low-to-high-Ievel output
tpHL $ propagation delay time, high-to-Iow-Ievel output
tpZH '= output enable time to high level
tpZL == output enable time to low level
tpHZ '" output disable time from high level
tPLZ == output disable time from low level
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-889
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373,SN74LS374, SN74S373, SN74S374
OCTAL D·TYPE TRANSPARENT LATCHES AND EDGE·TRIGGERED FLlP·FLOPS
TYPICAL APPLICATION DATA
OUTPUT
CONTROL 1
BIDIRECTIONAL BUS DRIVER
),
lQ
2Q
3Q
4Q
10
20
3D
40
50
60
BIDIRECTIONAL
DATA BUS 1
'LS374
OR
'S374
70
80
7Q
8Q
.~
)
CLOCK 1
CLOCK 2
(
' - lQ
-
2Q
10 r20 t--
~
' - - - 3Q
-
4Q
'---
CLOCK 1 H
BUS
EXCHANGELS
CLOCK
CLOCK2 H
BIDIRECTIONAL
DATA BUS2
5Q
6Q
=:£=
6Q
6Q
7Q
8Q
'LS374
OR
'S374
3D f-40 t--50 f - - 60
70
80
'1'
0 UTPUT
CONTROL 2
L..J
-,
r
L......J
CLOCK CIRCUIT FOR BUS EXCHANGE
EXPANDABLE 4·WORD·BY-8·BIT GENERAL REGISTER FILE
'LS374 OR 'S374
1/2 SI\I74LSI39
OR SN74S139
'LS374 OR 'S374
ENABLE SELECT {
'LS374 OR 'S374
'LS374 OR 'S374
1/2 SN74LSI39
OR SN74S139
C'i::Oc'K
SELECT
2-890
..
UCLOCK
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 76265
SN54LS375, SN74LS375
4·BIT BISTABLE LATCHES
OCTOBER 1976 - REVISED MARCH 1988
•
SN54LS375 .•. J OR W PACKAGE
SN74LS375 ... 0 OR N PACKAGE
(TOP VIEW)
Supply Voltage and Ground on Corner
Pins To Simplify P-C Board Layout
10
10
10
1C,2C
20
20
20
GNO
description
The SN54LS375 and SN74LS375 bistable latches are
electrically and fu nctionally identical to the
SN54LS75 and SN74LS75, respectively. Only the
arrangement of the terminals has been changed in the
SN54LS375 and SN74LS375.
These latches are ideally suited for use as temporary
storage for binary information between processing
units and input/output or indicator units. Informa·
tion present at a data (0) input is transferred to the a
output when the enable (e) is high and the a output
will follow the data input as long as the enable
remains high. When the enable goes low, the information (that was present at the data input at the time
the transition occurred) is retained at the a output
until the enable goes high.
VCC
40
40
40
3C,4C
30
30
30
SN54LS375 .•. FK PACKAGE
(TOPVIEWI
3
2 1 20 19
10
1C,2C
NC
20
20
All inputs are diode-clamped to minimize transmissionline effects and simplify system design. The SN54LS375
is characterized for operation over the full military
temperature range of - 55·C to 125°C; SN74LS375 is
characterized for operation from O°C to 70·C.
40
40
NC
3C,4C
30
CI)
Q)
(,)
.>
Q)
o
..J
0 0 u 010
lI-
NZZMM
t!l
NC - No internal connection
FUNCTION TABLE
(EACH LATCHI
INPUTS OUTPUTS
Q
Q
0
G
L
H
L
H
H
H
H
L
X
L
00
00
logic diagram (each latch)
~'.~ ,a
""'"'"
LATCH
H "" high level, L = low level, X :::: irrelevant
00"" the level of Q before the high-to-Iow transition of C.
logic symbol t
ENABLE
schematics of inputs and outputs
10 (11
10
lC,2C
20
(31
10
10
2Q
EQUIVALENT OF
EACH INPUT
VCC---,.--
2Q
3Q
3D
TYPICAL OF ALL OUTPUTS
Req
INPUT-,'OI'II~-~
30
4Q
40
tThis symbol is in accordance with ANSIIIEEE Std. 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
PRDDUCTIDI DATA d_IIInts .....i. information
.urr.nt II ., p.blicoti•• doto. Prodactl ...forll to
lpICi!icotians per tilt tenRI at TUll l.m.....111
=i~·i:=
=::r=,:~~.ot
Data: Req=17kU
Enable: Req "" 4.2 kU
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265
2-891
SN54LS375, SN74LS375
4·BI1 BISTABLE LATCHES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
7V
_55°C to 125°C
. oOe to 70°C
~65°e to 150°C
Supply voltage, Vee (see Note 1) . . . . . .
Input voltage . . . . . . . . . . . . . .
Operating free·air temperature range: SN54LS375
SN74LS375
Storage temperature range
NOTE1: Voltage values are with .respect to network ground terminal.
recommended operating conditions
SN54LS375
MIN
4.5
Vee
Supply voltage
VIH
High-level input voltage
NOM
5
SN74 LS375
MAX
5.5
MAX
5.25
5
2
2
0.7
-0.4
VIL
Low-level input voltage
IOH
High-level output current
IOL
tw
Width of enabling pulse
20
20
Setup time
20
20
0
0
--55
Hold time
Operating free-air temperature
125
UNIT
V
V
O.S
-0.4
mA
S
mA
70
e
4
Low-level output current
tsetup
thold
TA
NOM
MIN
4.75
0
V
n.
n.
n.
-I
-I electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
rC
<
VIK
C:;"
VOH
CD
UI
VOL
SN54 LS375
TEST CONDITIONS t
PARAMETER
CD
MIN
Vee= MIN,
11- -ISmA
Vee- MIN,
VIH = 2 V,
VIL = MAX
VIH=2V,
IOL =4mA
2.5
IOH= -0.4mA
Vee= MIN,
VIL = MAX
Vee= MAX,
VI = 7 V
IIH
Vee= MAX
VI = 2.7 V
Vee = MAX,
IOS§
ICC
Vee = MAX
Vee = MAX.
3.5
0.25
MIN
3.5
0.25
0.35
0.5
u.
u.
C input
0.4
0.4
o input
20
20
C input
SO
-0.4
80
-0.4
C input
-1.6
-20
See Note 2
-100
6.3
-1.6
-20
12
UNIT
V
V
I U Input
o input
VI =0.4V
TVP* MAX
-1.5
2.7
0.4
IOL = 8 mA
II
IlL
SN74LS375
TVP* MAX
-1.5
-100
12
6.3
V
mA
itA
mA
mA
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*All typical values are at VCC = 5 V. T A = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is tested with all Inputs grounded and all outputs open.
switching characteristics, Vee = 5 V. T A = 25°e (see note 3)
PARAMETER
tpLH
tpHL
tpLH
tpHL
tpLH
tPHL
tpLH
tPHL
FROM
IINPUTI
D
0
TO
(OUTPUT)
TVP
MAX
a
15
27
9
17
a
12
20
C
a
e
a
TEST CONDITIONS
RL
= 2kn.
eL· 15 pF
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-892
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75285
MIN
7
15
\.5
27
14
25
16
7
30
15
UNIT
n.
n.
n.
n.
SN54376, SN74376
QUADRUPLE J·t FLlp·FLOPS
OCTOBER 1976 - REVISED MARCH 1988
•
Four J.i{ Flip·Flops in a Single Package, , ,
Can Reduce FF Package Count by 50%
•
Common Positive-Edge-Triggered Clocks
with Hysteresis, , , Typically 200 mV
SN54376 ... J PACKAGE
SN74376 ... N PACKAGE
(TOP VIEW)
CLR
lJ
•
Fully Buffered Outputs
lK
•
Typical Clock Input Frequency, , , 45 MHz
10
20
2K
description
2J
These quadruple TTL J.j( flip-flops incorporate a
number of third·generation Ie features that can
simplify sysrem design and reduce flip·flap package
count by as much as 50",(,. They feature hysteresis at
the clock input, fully buffered outputs, and direct
clear capability. The positive-edge·triggered SN54376
and SN74376 are directly compatible with most
Series 54/74 MSI registers.
The SN54376 is characterized for operation over the
full military temperature range of -55°C to 125°C;
the SN74376 is characterized for operation from oOe
to 70o e.
INPUTS
CLEAR
CLOCK
J
K
OUTPUT
Q
l
X
X
X
l
H
t
L
H
Qo
H
t
H
H
logic symbol t
CLR
ClK
lJ
lK
H
H
!
L
L
L
H
t
H
l
TOGGLE
H
L
X
X
Qo
(1)
3J
3K
4J
4K
,....
(9)
(3)
(6)
R
,
(2)
2J 171
2K
FUNCTION TABLE lEACH FLlP.FlOP)
COMMON INPUTS
GND '--I.::::"--'OJ-'CLK
,....
.IT Cl
r
1J
14)
fI)
10
CD
CJ
lK
(5)
,....
'>CD
20
C
(10)
(12)
111) ,....
..oJ
30
I-I--
(15)
(13)
(14) .........
40
tThis symbol is in accordance with ANSI/IEEE Std. 91·1984 and
lEe Publication 617·12.
schematics of inputs and outputs
EQUIVALENT OF
EACH INPUT
TYPICAL OF ALL
OUTPUTS
- - -....._VCC
Vcc--+-INPUT
Q
Clear, J, K: Req = 4 kr! NOM
Clock: Req = 11.6 kr! NOM
Resistor values shown are nominal.
PRODUCTION DATA documonts contain informotion
currant as of publication data. Products conform to
specifications per the terms of Texas Instruments
::~::~~i~a{::I~t ~~~~ti:; ~IO::::~:~~ nat
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-893
SN54316, SN14316
QUADRUPLE J.j( FLlP·FLOPS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54376.......................... - 55°C to 125°C
SN74376 ........ : .................... ooe to 70°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminals.
recommended operating conditions
SN54376
MIN
NOM
4.5
5
Supply voltage, VCC
SN74376
MAX
MIN
NOM
5.5
4.75
5
-800
High-level output current, 'OH
0
Pulse width, tw
22
Clock low
12
12
Preset or clear low
J, K inputs
Clear inactive state
12
12
Setup time, tsu
r-
Input hold time, th
C
Operating free-air temperature, T A
n'
CD
C/)
V
IlA
a
30
Clock high
-I
-I
CD
<
5.25
-800
16
Low-level output current, IOl
Clock frequency
16
mA
30
MHz
22
at
at
lOt
lOt
20t
ns
ns
ns
20t
125
-55
t+The arrow indicates the edge of the clock pulse used for reference:
UNIT
MAX
t for the rising edge,
.j,
a
'c
70
for the falling edge.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONSt
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
MIN
MAX
TYP*
UNIT
2
VCC~
MIN,
VCC - MIN,
VIL
~
0.8 V,
VCC- MIN,
V
11--12mA
VIH -2 V,
2.4
'OH ~ -8001lA
VIH
~
2 V,
0.8
V
-1.5
V
3.4
V
VOL
LOW-level output voltage
'I
IIH
Input current at maximum input voltage
VCC~MAX,
VI
High-level input current
VCC- MAX,
VI~2.4V
40
IlA
IlL
LOW-level input current
VCC - MAX,
VI~O.4V
-1.6
mA
lOS
Short-circuit output currentS
VCC - MAX
-85
mA
ICC
Supply current
VCC~MAX
74
mA
VIL
~
0.8 V,
0.2
IOL~16mA
~
0.4
5.5 V
V
1
-30
52
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:tAil typical values are at Vee = 5 V, T A = 25°e.
§Not more than one output should be shorted at a time.
switching characteristics, Vee = 5 V, T A = 25°C
PARAMETER
TEST CONDITIONS
f max
Maximum clock frequency
tpHL
Propagation delav time. high-to-Iow-Ievel output from clear
tpLH
Propagation delay time, low-to-high-Ievel output from clock
tPHL
Propagation delay time. high-to-low-level output from clock
CL
15pF,
RL~400n,
See Note 2
NOTE 2: Load circuits and voltage waveforms are show~ in Section 1.
2-894
~
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS. TEXAS 75265
MIN
TYP
30
45
MAX
UNIT
MHz
17
22
30
24
35
35
ns
ns
ns
SN54LS377, SN54LS378, SN54LS379,
SN74LS377, SN74LS378, SN74LS379
OCTAL. HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE
•
'LS377 and 'LS378 Contain Eight and
Six Flip-Flops, Respectively, with SingleRail Outputs
•
'LS379 Contains Four Flip-Flops with
Double-Rail Outputs
•
Individual Data Input to Each Flip-Flop
•
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
SN54LS377 ..• J PAGKAGE
SN74LS377 •.. ow OR N PACKAGE
(TOP VIEW)
G
10
10
20
20
30
3D
40
40
GNO
VCC
80
80
70
70
60
60
50
50
ClK
description
SN54LS377 ... FK PACKAGE
These monolithic, positive-edge-triggered flip-flops
utilize TTL circuitry to implement Ootype flip-flop
logic with an enable input. The 'LS377, 'LS378, and
'lS379 devices are similar to 'lS273, 'LS174, and
'LS175, respectively, but feature a common enable
instead of a common clear.
(TOP VIEW)
U
~ ~I~ ~g
3 2
en
Q)
CJ
-S
Information at the D inputs meeting the setup time
requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse if the enable
input G is low. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going pulse. When the
clock input is at either the high or low level, the D
input signal has no effect at the output. The circuits
are designed to prevent false clocking by transitions
at the Ginput.
Q)
9 10 111213
-ot i3 d """
G
10
10
2D
20
3D
30
GNO
CLOCK
DATA
X
X
(TOP VIEW)
U
t
H
0
0
00
00
L
t
L
00
H
L
X
L
X
00
50
50
40
40
ClK
SN54LS378 ... FK PACKAGE
~1c:J ~ ~~
OUTPUTS
G
-oJ
lI-
SN54LS378 ... J OR W PACKAGE
SN74LS378 ..• 0 OR N PACKAGE
(TOP VIEW)
FUNCTION TABLE
(EACH FLIP FLOP)
H
L
C
001<:00
These flip-flops are guaranteed to respond to clock
frequencies ranging from 0 to 30 MHz while
maximum clock frequency is typically 40 megahertz.
Typical power dissipation is 10 milliwatts per
flip-flop.
INPUTS
1 2019
3
2
I 2019
L
H
OOUI<:O
"'i3
Z
d-ot
NC - No internal connection
PRODUCTION DATA documenlS conlain informalion
current as of publication date. Products conform to
specifications per the terms at Texas Instruments
::~=~~i~8{::1~1i ~:~:~i:; :.~a::::~:~~
not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-895
SN54LS377, SN54LS378, SN54LS379,
SN74LS377, SN74LS378, SN74LS379
OCTAL, HEX, AND QUAD D·TYPE FLlp·FLOPS WITH ENABLE
SN54LS379 ... J OR W PACKAGE
SN74LS379 ... D OR N PACKAGE
ITOPVIEW)
SN54LS379 ... FK PACKAGE
ITOPVIEW)
G
10
40
3D
30
"";'----':.J-'
30
elK
NC - No intemal connection
logic diagram lpositive logic)
D
-I
-I
r-
CLOCK----i
C
D
CD
TO
7
5
3
OTHER
<
c:;.
CD
(I)
Q
Q
Q
('LS379
ONLY)
Q
('LS377)
('LS378)
('LS379)
FLlP·FLOPS
ENABLE _ _ _-QL_./
G
logic symbols t
'LS378
'LS377
G
eLK
10
20
3D
40
50
60
70
80
'LS379
G
G
elK
elK
(2)
14)
15)
17)
16)
18)
113)
19)
112)
114)
115)
1111
118)
116)
119)
10
10
20
20
30
3D
40
40
50
50
60
60
(2)
(4)
15)
16)
111)
17)
110)
113)
112)
114)
10
20
30
40
50
115) 60
70
80
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for OW, J, and N packages.
2-896
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
10
20
10
10
20
SN54LS377. SN54LS378. SN54LS379.
SN74LS377. SN74LS378. SN74LS379
OCTAL. HEX. AND QUAD D·TYPE FLlP·FLOPS WITH ENABLE
schematics of inputs and outputs
EQUIVALENT OF DATA
INPUT
EQUIVALENT OF CLOCK
INPUTS
vcc----_---- -
VCC----------~_-
Req
INPUT~r_-~.~._--_+
'LS379
others
Req
Req
= 30 kQ NOM
= 25 kQ NOM
'LS379 :Req = 17 k2 NOM
others :Req = 20 k2 NOM
EQUIVALENT OF ENABLE
INPUTS
TYPICAL OF ALL OUTPUTS
Q)
(,)
.S;
--------+-VCC
vcc----------~--
---+
I/)
Q)'
Req
C
I NPUT .....r_--:!
......
..J
lI-
L--i>---OUTPUT
= 25 kQ NOM
others :Req = 20 kQ NOM
'LS379 :Req
absolute maximum rating over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage
. . . . .
Operating free-air temperature range: SN54LS'
SN74LS'
Storage temperature range
NOTE" 1
, .... 7 V
. .... 7 V
_55°C to 125°C
O°C to 70°C
_65°C to 150°C
Voilaqe values are wIth re'>peC'1 to neTwork qrouncl termined.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-897
SN54LS377, SN54LS378, SN54LS379,
SN74LS377, SN74LS378, SN74LS379
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE
recommended operating conditions
SN54LS'
MIN
Supply vo'tage, Vee
SN74LS'
NOM MAX MIN
5
5.5 4.75
-400
4.5
High·'eve' output current, 'OH
Low-level output current, tOl
NOM MAX
5
5.25
-400
4
0
20
Clock frequency, fclock
Width of clock pulse, tw
Setup time. tou
Hold time, til
30
Data input
20t
Enable active-state
Enable inactive-state
25t
Data and enable
30
20t
25t
V
"A
mA
MHz
ns
ns
lOt
lOt
5t
ns
5t
125
-55
Operating free-air temperature. TA
8
0
20
UNIT
0
70
"e
tThe arrow indicates that the rising edge of the clock pulse is used for reference.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
-I
-I
V'H
High-level input voltage
V'L
Low-level input voltage
V'K
Input clamp voltage
CtI
VOH
High-'eve' output vo'tage
n'
CtI
VOL
Low-level output voltage
rC
<
en
Input current at
Vee = M'N
Vee=M'N,
V'H=2V,
'OH = -400 "A
i'OL=4mA
V'H=2V,
Vee = MAX,
V, =7V
High-level input current
Vee = MAX,
V,=2.7V
"L
lOS
Low-level input current
Vee=MAX,
Vee=MAX
V,
Vee = MAX,
SN74LS'
MAX MIN TYP*
2
MAX
0.7
-1.5
0.8
-1.5
3.5
2.7
0.25
0.4
l'OL=BmA
"H
Supply cu rrent
2.5
V'L = V'L max,
Vee -M'N,
V,L = V,L max
maximum input voltage
'ee
MIN TYP*
2
11--18mA
"
Short-circuit output current§
SN54LS'
TEST CONDITIONSt
=
-20
See Note 2
V
V
V
V
3.5
0.25
0.4
0.35
0.5
V
0.1
mA
20
20
-0.4
-100
-0.4
-100
"A
mA
mA
0.1
0.4 V
UNIT
-20
'LS377
/'LS378
17
13
28
22
17
13
22
rnA
rnA
I'LS379
9
15
9
15
mA
2B
t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
:j: All tvpical values are at Vee = 5 V, T A "" 25° C,
§ Note more than one input should be shorted at a time, and duration of the short-circuit should not exceed one second.
'NOTE 2: With all outPuts open and ground applied to all data and enable inputs, ICC is measured after a momentary ground,
then 4.5 V, is applied to clock.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
TEST CONDITIONS MIN
f max
Maximum clock frequency
tPLH
Propagation delay time, low-to-high·level output from clock
eL=15pF,
RL = 2 kn
tPHL Propagation delay time. high-to-low-Ievel output from clock
See Note 3
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-898
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
30
TYP MAX UNIT
MHz
40
17
27
ns
18
27
ns
SN54LS381A, SN54S381, SN74LS381A, SN54LS382A, SN74LS382A, SN74S381
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
02430, JANUARY 1981 - REVISED MARCH 1988
PIN DESIGNATIONS
DESIGNATION
PIN NOS.
FUNCTION
A3, A2, Al, AD
B3, B2, Bl, BO
17,19,1,3
WORD A INPUTS
WORD B INPUTS
S2, Sl, SO
7,6,5
16,18,2,4
SN54LS381A,SN54S381
... J OR W PACKAGE
SN74LS381A,SN74S381
... OW OR N PACKAGE
SN54LS381A,SN54S381
... FK PACKAGE
(TOP VIEW)
(TOP VIEW)
FUNCTION-SELECT
Al
INPUTS
VCC
A2
CARRY INPUT FOR
Cn
15
F3,F2,Fl,FO
12,11,9,8
B2
A3
B3
ADDITION, INVERTED
CARRY INPUT FOR
Cn
p
G
SUBTRACTION
p('LS381A
'S3810NLYI
GI'LS381A
'S3810NLYI
14
13
('LS382A
Cn + 4 ONLYI
14
OVR {'LS382A
ONLYI
13
VCC
GND
20
10
FUNCTION OUTPUTS
ACTIVE·LOW CARRY
PROPAGATE OUTPUT
'---~
ACTIVE·LOW CARRY
GENERATE OUTPUT
SN54LS382A ...
J OR W PACKAGE
SN74LS382A ...
DW OR N PACKAGE
(TOP VIEW)
RIPPLE·CARRY
OUTPUT
OVERFLOW
OUTPUT
SUPPLY VOLTAGE
Al
Bl
AO
GROUND
• Fully Parallel 4-Bit ALUs in 20-Pin Package
for O.300-lnch Row Spacing
P Outputs
SN54LS382A ... FK PACKAGE
(TOP VIEW)
CI)
VCC
A2
B2
A3
B3
Cn
SI
52
• Ideally Suited for High-Density Economical
Processors
• 'LS3B1A and 'S381 Feature G and
for Look-Ahead Carry Cascading
F3
F2
3
(,)
'S;
CI)
o
...I
Cn +4
OVR
F3
F2
Fl
GND
CI)
2 1 20 19
lI-
9 10 111213
U::~~[2g;
0
(!)
FUNCTION TABLE
• 'LS382A Features Ripple Carry (C n + 4) and
Overflow (OVR) Outputs
SELECTION ARITHMETIC/LOGIC
S2
• Arithmetic and Logic Operations Selected
Specifically to Simplify System
Implementation:
A Minus B
B Minus A
A Plus B
and Five Other Functions
SI
L
SO
L
OPERATION
CLEAR
L
L
H
B MINUSA
L
H
L
A MINUS B
L
H
H
A PLUS B
H
H
L
L
L
H
H
H
H
H
L
H
A0B
A + B
AB
PRESET
L
H = high level,
description
~ =
low level
The 'LS381 A, '5381 and 'L5382A are low-power Schottky and Schottky TTL arithmetic logic units (ALUsl/function generators
that perform eight binary arithmetic/logic operations on two 4-bit words as shown in the function table. The exclusive-OR,
AND, or OR function of the two Boolean variables is provided without the use of external circuitry. Also, the outputs can
be cleared (low) or preset (highl as desired. The 'LS381A and 'S381 provide two cascade outputs (p and
G for expansion
utilizing SN54S182/SN74S182 look-ahead carry generators. The 'LS382 provides a C n +41 output to ripple the carry to
the Cn input of the next stage. The 'LS382A detects and indicates two's complement overflow condition via the OVR output.
The overflow output is logically equivalent to Cn + 3" Cn + 4. When the 'LS382A is cascaded to handle word lengths longer
than four bits in length, only the most significant overflow (OVR) output is used.
The SN54' family is characterized for operation over the full military temperature range of - 55°C to 125°C. The SN74'
family is characterized for operation from O°C to 70°C.
PRODUCTION DATA documenls contain information
current as of publication data. Products conform to
specifications par the tarms of Texas Instruments
=:::~~i~8i~:I~~~ ~!:~::i:r :'~D::;::::~::'~S not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-899
SN54LS381A. SN54S381. SN14LS381A. SN54LS382A. SN14LS382A. SN14S381
ARITHMETIC LOGIC UNITS/FUNCTIONS GENERATORS
function table
Certein differences exist in the G, is ('LS381 A, 'S381) and OVR, Cn +4 ('.L8382A) function table compared with similar
parts from other technologies and other vendors. No differences exist In the arithmetic modes (B minus A, A minus B, and
A plus B), where these outputs perform valuable cascade functions. There are slight differences in the other modes (CLEAR,
A + B, A Ell B, AB, and PRESET), where these outputs are strictly "don't care".
This function table is a condansad version and assumes for An that AO, A 1, A2, and A3 inputs all agree and for Bn that
BO, B1, B2, and B3 inputs all agree. This table is intended to point out the response of these ll',1' ('LS381A, '8381) and
OVR, Cn + 4 ('LS382A) outputs in all modes of operation to facilitate incoming inspection.
FUNCTION TABLE
ARITHMETIC/LOGIC
OUTPUTS
INPUTS
OPERATION
82
SI
so
CLEA~
L
L
L
('LS381A, '83811
ii
it
OVR
L
H
H
H
L
H
L
L
L
L
L
H
H
L
H
L
L
L
H
L
L
H
H
H
L
L
L
L
H
L
L
H
L
L
H
H
H
L
L
H
L
L
H
H
H
L
L
L
L
H
H
L
L
L
L
H
L
H
F3
F2
X
Bn
X
L
L
L
L
H
L
H
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
L
L
H
H
L
L
L
r-
L
L
L
H
H
H
L
L
H
L
L
L
C
CD
<
L
H
L
H
H
H
B MINUS A
L
L
H
~
H
L
('Ls3a2AI
FO
Fl
L
An
X
Cn
H
H
L
C n+4
H
L
H
H
H
H
H
H
H
L
L
L
H
L
L
L
L
L
L
H
L
L
H
(;'
H
L
H
L
L
L
H
H
H
L
L
CD
H
H
L
H
H
H
H
L
H
L
H
H
H
H
L
L
L
L
H
L
L
H
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
L
L
L
H
A MINUS B
L
H
L
en
A PLUS B
A0B
A
,
B
L
H
H
H
L
L
H
L
H
L
H
H
H
H
H
L
L
H
L
H
L
L
L
L
L
H
H
H
L
L
H
L
H
L
L
L
L
H
L
L
H
H
H
L
L
L
L
L
H
L
L
H
H
H
H
H
H
H
H
L
H
L
H
X
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
H
H
L
L
L
H
H
H
L
H
PRESET
2-900
H
H
H
H
L
H
H
L
H
H
H
H
L
H
L
H
H
H
H
H
L
L
L
H
H
L
H
H
H
.H
H
L
H
H
L
X
H
H
L
L
L
L
H
H
L
X
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
H
H
L
L
L
H
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
L
H
H
X
AB
L
L
L
L
L
L
L
H
H
L
L
X
L
H
L
L
L
L
H
H
L
L
X
H
L
L
L
L
L
H
H
L
L
L
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
X
X
H
H
H
H
H
L
L
L
H
X
X
H
H
H
H
H
L
H
H
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54lS381A. SN54lS382A. SN74lS381A. SN74lS382A
ARITHMETIC lOGIC UNITS/FUNCTION GENERATORS
logic diagram (positive logic)
80
'LS381A, 'LS382A
(5)
~
'"
82 ~
81
'"
1
IT
l
1
ee t
J I-~
:Y99
lfj
(15)
AD
~
AB
~
AB
AS
AS
(S)
0
~
BO.~
AB
r '"
AB
AS
~~
~
A1
~
AB
r-AS
AS
~~
~
B1
~
r-AB
'=""
AB
Ail
A2
1?
(~
~
AB
r-
AB
AS
B2
;::::;
r
AS
AB
AB
AS
~
~~
AB
(171[
A3
...
---t,::
AB
~
r
(16)
B3
...
AS
~}
~
f-
t/)
Q)
.~
>
Q)
C
F2
r
r
F3
(13)
OVR
~
-'"
-
...J
(14)
l
'LS3B2
C n +4
I-<
!::=,...,
r==
~
l>
F1
l.-.-
AB
~~~
AB
~
FO
~
(14)
}
'L8381 A
(13)
G
L.....-
Pin numbers shown are for OW, J, N, and W packages.
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-901
SN54S381. SN74S381
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
logic diagram and schematics of inputs and outputs
'8381
c
(15)
(4)
n
BO~~r------,
r~
-t
-t
F1
rC
B2
CD
(18)
<
O·
CD
IJI
A2~1~
F2
(17)
A3- -
(13) _
G
Pin numbers shown are for OW, J, N, and W packages.
2-902
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS381A. SN54S381. SN74LS381A. SN54LS382A. SN74LS382A. SN74S381
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
logic symbols t
'LS381 A, 'S381
so 15)
ALU
so lSI
Sl 16)
S2
'LS382A
ALU
a } MO
2
7 IFIP.QI '" 15) CP
17)
51 16)
52 17)
[FIP.Q) " 16) CG
11121 B. [1)
AO 13)
18)
[1)
BO 14)
Fa
Q
80
Al 11)
19)
[2)
81 12)
Al
Fl
0
81
A2 119)
111)
[4]
82 118)
A2
F2
Q
82
A3 117)
83 116)
Q
112)
[8]
F3
A3
181
[1]
14)
Fa
Q
III
P
12)
Q
19)
[2]
1191
118)
111)
[4]
Q
1131
Fl
F2
OVR
1111
[8]
83
116)
Q
112)
tThese symbols are in accordance with ANSIIIEEE Std 91 -1984 and
IEC Publication 617-12.
Pin numbers shown are for OW, J, N, and W packages.
In
F3
Q)
(,)
'S;
Q)
C
schematics of inputs and outputs
'LS381. 'LS382A
EQUIVALENT OF EACH INPUT
...J
TYPICAL OF ALL OUTPUTS
VCC --~r---
II-
VCC
INPUT
OUTPUT
Any S: Req = 10 kn
Cn ('LS381A): Req = 2.5 kn
All others: Req = 2 kn
'S381
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
Vcc
Req - VCC=O
INPUT
--_
OUTPUT
AnyAorB: Req= 1 kn
Cn: Req = 800 n
Any S: Req = 6 kn
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-903
SN54LS381A, SN54LS382A, SN74LS381A, SN74LS382A
ARITHMETIC LOGIC UN1TS/FUNCTION GENERATORS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (See Note 1) ....................................................... 7 V
Input voltage . '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Operating free-air temperature range: SN54LS381A, SN54LS382A ................... -55 D e to 125 D C
e
SN74LS381A, SN74LS382A ..................... " oDe to 70 D
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 De to 150 DC
NOTE 1: VolttiQa values are with respect to the network ground terminal.
recommended operating conditions
SN54LS'
Vee
Supply voltege
VIH
High·level input voltege
VIL
IOH
High·level output current
IOl
Low-level output current
TA
Operating
NOM
MAX
MIN
NOM
MAX
4.5
2
5
5.5
4.75
5
5.25
2
Low-level input voltage
free~air
SN74LS'
MIN
I Goutput of 'lS381A
0.7
0.8
-0.4
- 0.4
16
16
I All other outputs
4
temperature
- 65
125
8
70
a
UNIT
V
V
V
mA
mA
"e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC~
VIK
Vec~
VOH
IOH
(l' ('lS381AI
VOL
Other outputs
II
Any 5
Any A or B
IIH
TEST CONDITIONSt
Cn ('lS381AI
en I'LS382AI
MIN,
MIN,
=-
VIH=2V,
VIH
Vee~
VI
= MAX,
~
~
2 V,
Vil
= MAX,
2.5
I IOl = 16 mA
I IOl ~ 4 mA
t lOl- 8mA
3.4
IlL
en ('lS381AI
Vec~
MAX,
lee
t
t
Vcc~
MAX
Vee~
MAX,
0.47
0.25
0.4
0.35
0.5
~O.4V
- 20
0.1
20
20
100
100
80
80
100
100
-0.2
-0.2
-1
-1
-0.8
-0.8
-0.8
-0.8
35
- 20
65
For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vee"'" 5 V, T A == 25°C.
§ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
2-904
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
35
V
0.7
0.1
-100
UNIT
V
0.4
7V
All inputs grounded, outputs open
3.4
2.7
0.7
en I'LS382AI
IOS§
MAX
-1.5
0.25
VI~2.7V
VI
TYP*
0.47
Any 5
AnyAorB
SN74LS'
MIN
-1.5
0.4mA
MAX,
SN54lS'
Tvpi MAX
11~-18mA
Vee = MIN,
Vil ~ MAX
Vee
MIN
V
rnA
p.A
mA
-100
mA
65
mA
SN54LS381A. SN54LS382A. SN74LS381A. SN74LS382A
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
switching characteristics, Vee = 5 V, T A = 25°e (see note 3)
PARAMETER
tPLH
FROM
TO
(INPUT)
(OUTPUT)
TEST CONDITIONS
'LS381A
MIN
MAX
27
18
27
14
21
14
21
AnyAorB
G
20
30
21
33
P
21
33
23
33
20
30
AnyAorB
tpHL
tPLH
TVP
18
Any F
tPHL
tPLH
MAX
Cn
tPHL
tPLH
'LS382
TVP
AjorBj
Fi
MIN
ns
20
30
15
23
15
23
53
35
53
34
51
34
51
31
47
32
48
28
42
26
39
23
35
tPHL
27
41
tPLH
38
57
36
54
10
15
13
23
13
21
11
20
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tpLH
50,51,52
Fi
SO, 51, 52
G or P
Any Aor B
Any A or B
50,51,52
tPH
tPLH
tPHL
tPLH
tPHL
-
RL = 2 kn,
CL = 15pF
Cn+4
OVR
Cn +4 or
OVR
Cn
OVR
Cn
Cn +4
ns
ns
35
tPHL
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2·905
SN54S381, SN74S381
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
absolute maximum ratings over operating free-air temperature range (unless oj;herwise noted)
. 7V
Supply voltage, Vee (se. Note 1)
Input voltage . . . . . . .
Interemitter voltage (see Note 2)
Operating free·air temperature.range: SN54S381
SN74S381
Storage free·air temperature range . . . . .
NOTES:
5.5V
5.5V
-55°eto 125°e
oOe to 70 0e
-65°eto 1500 e
1. Voltage values, except interemitter voltage. are with respect to network ground terminal.
2. This is the voltage b~een two emitters of a multiple-emitter transistor. For this circuit, this rating applies to each A input in
conjunction with its respective B input; for example AO with BO, etc.
recommended operating conditions
SN54S381
Supply voltage, Vee
SN74S381
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
-1
High-level output current, IOH
20
Low-level output current, tOl
Operating free-air temperature, T A
-55
125
0
UNIT
V
-1
mA
20
mA
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONOITIONSt
MIN
TYPt
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current at maximum input voltage
IIH
High-level input current
-1.2
Vee' MIN,
11'-18mA
I SN54S381
Vee = MIN,
VIH - 2 V,
2.4
3.4
I SN74S381
VIL' 0.8 V,
IOH =-1 rnA
2.7
3.4
Vee - MIN,
VIH - 2 V,
en
All others
en
All others
V
V
V
0.5
VIL = 0.8 V,
10L = 20mA
Vee- MAX,
VI-5.5V
1
Vee' MAX,
VI = 2.7 V
250
V
rnA
50
/lA
200
Any S inpu
Low-level input current
UNIT
V
0.8
Any S input
IlL
MAX
2
VIH
-2
Vee' MAX,
-8
VI' 0.5 V
mA
-6
lOS
Short-circuit output current§
Vee'
lee
Supply current
Vee = MAX
-40
MAX
105
-100
mA
160
mA
tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended oper~ting conditions.
tAli typical values are at Vec = 5 V, T A"" 2SoC.
§Not more than one output should be shorted at a time.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
tpLH
tpHL
tPLH
FROM
TO
(INPUT)
(OUTPUT)
en
Any F
tpHL
tPLH
tpHL
tpLH
P
Any A or B
eL= 15pF,
See Note 3
Fj
AiorSj
AnyS
Any
tpHL
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
2-906
TEXAS . "
INSTRUMENTS
POST OFFICE BOX
655012·~
MIN
TYP
10
G
Any A or B
tPHL
tPLH
TEST eONDITIONS
DALLAS, TEXAS 75265
RL·280n,
MAX UNIT
17
10
17
12
20
12
20
11
18
11
18
18
16
27
25
18
30
18
30
ns
ns
ns
ns
ns
SN54LS384, SN74LS384
8·BIT BY l·BIT TWD'S·CDMPLEMENT MULTIPLIERS
02419. JANUARY 1981 - REVISED MARCH 1988
•
SN54LS384 ... J PACKAGE
SN74LS384 ... N PACKAGE
Two's-Complement Multiplication
•
Magnitude Only Multiplication
•
Cascadable for Any Number of Bits
•
8-Bit Parallel Multiplicand Data Input
•
Serial Multiplier Data Input
•
Serial Data Output for Multiplication
Product
•
40 MHz Typical Maximum Clock Frequency
(TOP
VIEW)
ClR
X3
VCC
Y
X4
X5
X6
X7
X2
Xl
XO
PROD
elK
GND
K
MODE
description
SN54LS384 ... FK PACKAGE
(TOP
The 'lS384 is an 8-bit by l-bit sequential logic
element that performs digital multiplication of two
numbers represented in two's-complement form to
produce a two's-complement product without
external correction by using Booth's algorithm
internally. The device accepts an 8-bit multiplicand
(X input) and stores this data in eight internal latches.
These X latches are controlled via the clear input.
When the clear input is low, all internal flip-flops are
cleared and the X latches are opened to accept new
multiplicand data. When the clear input is high, the
latches are closed and are insensitive to X input
changes.
The multiplier word data is passed by the Y input in a
serial bit stream, least significant bit first. The
product is clocked out the PROD output, least
significant bit first.
VIEW)
"'xuz»
15 u ~
3
2
20 19
III
CI)
CJ
'>
CI)
c
..J
lI-
NC - No internal connection
The multiplication of an m-bit multiplicand by an n-bit multiplier results in an (m + n)-bit product. The 'lS384 must
be clocked for m + n clock cycles to produce this two's complement product. The n-bit multiplier (Y-input) sign bit
data must be extended for the remaining m bits to complete the multiplication cycle.
The device also contains a K input so that devices can be cascaded for longer length X words. The PROD output of one
device is connected to the K input of the succeeding device when cascading. The mode input is used to indicate which
device contains the most significant bit. The mode input is wired high or low depending on the position of the 8-bit
slice in the total X word length. The device with the most significant bit is wired low and all lower order bit packages
are wired high.
The SN54lS384 will be characterized for operation over the full military temperature range from _55°e to l25°e.
The SN74lS384 will be characterized for operation from oOe to 70 o e.
PRODUCTION DATA d••um ......ntlin informltio.
current II of p.bliootio. data. Products conf.rm to
IpacifiCltial' par thl tarms of Tlxas Instruments
~=~~~·{.':~1i ~:\:~i:r :.~o::::~~ not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-907
SN54LS384, SN74LS384
8-BIT BY 1-BIT TWO'S-COMPLEMENT MULTIPLIERS
FUNCTION TABLE
INPUTS
CLR
CLK
Xi
Y
INTERNAL
V_1
OUTPUT
L
X
Data
X
L
L
H
t
X
L
L
Output
H
t
X
L
H
per
Add multiplicand to sum register and shift
H
t
X
H
L
Booth's
Subtract multiplicand from sum register and shift
H
t
X
H
H
algorithm
Shift sum register
H == high-level, L
=
FUNCTION
PROD
Load new multiplicand and clear internal sum and carry registers
Shift sum register
low-level. X == irrevelant. t == low-to-high-Ievel transition
logic symbol t
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VeC---4""'--
PROD OUTPUT
Vee
INPUT
OUTPUT
(61 PROD
~
~
Y: Roq = 3 kn NOM
Clock: Aeq == 6 kn NOM
X, Mode: Req = 19 kn NOM
K. Clear: Aeq == 8 kil NOM
rC
(I)
<
n-
(I)
en
logic diagram (positive logic)
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and
lEe Publication 6' 7·12.
Pin numbers shown are for J and N packages.
X4
A4
A3
A2
Al
ADDER/SUBTRACTER AND REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
Input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free·air temperature range: SN54LS384
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. _55°C to 125°C
SN74 LS384
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. oOe to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _65°C to 150°C
NOTES:
2-908
1. Voltage values are with respect to network ground terminal.
2. Input voltages must be zero or pOSitive with respect to network ground terminal.
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS38~ SN74LS384
8·BIT BY 1·BIT TWO'S·COMPLEMENT MULTIPLIERS
recommended operating conditions
SN54LS384
SupplV voltage,
SN74LS384
MIN
NOM
MAX
4.5
5
5.5
Vee
MIN NOM
4.75
-400
High-level output current, IOH
MAX
5
V
-400
J.lA
4
Low-level output current, IOL
0
Clock frequency, fclock
Setup time, tsu
Pulse width, tw
0
Y before Clock t
45
38
K before Clock t
30
24
X before Clear t
23
19
Clear inactive-state set up time before Clock t
Hold time, th
25
30
20
Y after Clock t
0
0
K after Clock t
0
0
X after Clear t
2
2
Clock high
20
20
Clock low
20
20
Clear low
38
33
Operating free-air temperature, T A
125
-55
UNIT
5.25
8
mA
25
MHz
ns
ns
ns
70
0
"C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS384
TEST eONDITIONSt
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
TYP:j:
2
11"-18mA
VCC - MIN,
VIH-2V,
VIL" VIL max,
VOH" -400J.lA
Vee - MIN,
VIH"2V,
2.5
3.4
0.4
VI" 5.5 V
input current
K, Clear
VCe" MAX,
VI" 2.7 V
Clock
X, Mode
Low~level
input current
K, Clear
Clock
VCC" MAX,
VI"OAV
Y
lOS
Short~circuit output current§ Vee" MAX
ICC
Supply current
VCC- MAX,
-20
See Note 3
-1.5
V
0.4
0.35
0.5
1
20
20
30
40
40
80
80
-0.48
-0.48
-1.2
-1.2
-1.6
-1.6
-3.2
-3.2
-100
91
-20
CIJ
...........J
V
mA
I'A
mA
-100
mA
91
132
mA
MIN
TYP
MAX
25
40
132
(.)
'S;
o
V
30
Y
IlL
V
0.25
1
X, Mode
High-level
IIH
0.8
3.4
IIOL - 8 mA
VCC" MAX,
UNIT
V
2.7
0.25
IIOL"4mA
MAX
2
-1.5
Vee" MIN,
VIL "VILmax
input voltage
TYP+
0.7
Input current at maximum
II
MIN
IJj
CIJ
SN74LS384
MAX
I.
tFor conditions shown at MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAil tYpical values are at Vec = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short·circuit should not exceed one second.
NOTE 3: ICC is measured with the clear input grounded and all other inputs and outputs open.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
TEST CONDITIONS
UNIT
f max
Maximum clock frequency
tPLH
Propagation delay time, low~to~high~level output from clock
CL" 15pF,
15
23
tPHL
Propagation delay time, high-to-Iow-Ievel output from clock
RL"2kr1,
15
23
ns
tPHL
Propagation delay time, high~to-low~level output from clear
See Note 4
17
25
ns
MHz
ns
NOTE 4: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-909
SN54LS384, SN}4LS384
8·BIT BY 1·BIT TWO'S·COMPLEMENT MULTIPLIERS
TYPICAL APPLICATION OATA
'lS384
ax 1 2'5 COMP 1r
(1)
CLEAR (LI
CLOCK
Z1/C2
(LOW FOR MSBl
L~
m
r A23
A22
A21
A20
A19
AlB
A17
A16
C3/~
(11)
(121
~O
(131
'--
(141
-
.
r
SRG8
~
(21
P
'--
(31
(41
(51
m
(151
L
.
1
-7
R
3D
~
3D 4 Q
N4
m
L~
C1
=1
'LS384
r-
(11 ....
H~
C
CD
C7I
<
(=r
A15
CD
en
A14
24·BIT
MULTIPLICAND,<
A13
A12
A11
A10
(111
(121
(131
(141
(21
~
(31
(41
A9
(51
A8
(151
(101
'LS384
(11 ....
H~
C7I
A7
AS
AS
A4
A3
A2
Al
....
MULTIPL IER
AO
(111
"1
i
(121
(131
(141
(21
(31
(41
(51
(151
(101
FIGURE I-BASIC 24·BIT SERIAL/PARALLEL CONNECTION
2-910
TEXAS . . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PRODUC T
SERIAL
OUTPUT
~
SN54LS384, SN74LS384
8-BIT BY 1-BIT TWO'S-COMPLEMENT MULTIPLIERS
TYPICAL APPLICATION DATA
SN54LS322
SN74LS322
I~
OUTPUT ENABLE III
SE RIAL IHI/PARALLEL ILl
REGISTER ENABLE ILl
CLOCK
SIGN EXTENOILI
H 181 ,..,
111 ,..,
121
11~
SRG8
R
:lENI5
G3
3M! (SHIFTl
3M2 (PAR LOAOl
C611 __
I>
1181
G4
8,i,1,60
1191
L~ G5
~
L 141
4,5,1,60
4,5,1,60
1167+-
';77,15
I>
2,60
1514-
•
27
2,60
28
';78,15
en
1151
G,)
(J
161
"S;
1141
171
1131
BO
Bl
4-
G,)
C
I>
2,60
';714,15
~
I
B2
B3
BUS
....
1121
B4
l-
I-
I
B5
B6
B7
CLEAR ILl
CLOCK
'LS384
111 r-
~
171
151
141
131
121
1141
1131
1121
1111
~
8x 1 2's COMP
11'
211C2
(LOW FOR MSB)
C3/ __
2.!!..
----
0
-7
.
SRG8
P
.
1
R
3D
~
""'iii""
3D 4 Q
N4
"1'ii""
1101
L - Cl
FIGURE 2-8-8IT BY 8-BIT MLiL T1PLlER, BUS ORGANIZED,
WITH 8-BIT TRUNCATED PRODUCT
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-911
2-912
SN54LS385, SN74LS385
QUADRUPLE SERIAL ADDERS/SUBTRACTORS
02412, NOVEMBER 1977 - REVISED MARCH 1988
•
Four Synchronous Elements in a
Single 20-Pin Package
•
Buffered Clock and Direct Clear Inputs
•
Independent Two's-Complement
Addition/Subtraction
SN54lS385 , , • J PACKAGE
SN74lS385 ..• OW OR N PACKAGE
{TOPVIEWI
ClK
VCC
n:
4l:
4S/A
ISlA
4B
4A
3A
3B
lB
lA
2A
2B
description
The 'LS385 is a general purpose adder/subtractor
and is particularly useful as a companion part to the
SN54LS384{SN74LS384 serial/parallel two's-complement multiplier. The 'LS385 contains four independent adder/subtractor elements with common
clock and clear.
3S/A
2S/A
3l:
2l:
GND
Each ofthe four independent sum (k) outputs reflects
its respective A and B input as controlled by the S/A
control. When S/A is high th·e k function is A minus
B. When S/A is low the k function is A plus B.
ClR
SN54LS385 ... FK PACKAGE
(TOPVIEWI
~
I<{
When low, the clear input asynchronously resets the
sum flip-flop low and the carry flip-flop either high in
the subtract mode or low in the add mode. The clock
is positive-edge triggered and controls the sum and
carry flip·flops according to the function table.
u
cn~d~~
CI)
3
Q)
(.)
2 1 20 19
lB
lA
2A
2B
4B
4A
3A
3B
2S/A
'>
Q)
C
..J
....
....
FUNCTION TABLE
SELECTED
FUNCTION
Clear
Add
Subtract
H
= high
INPUTS
DATA IN CARRY FLIP-FLOP
BEFORE t
AFTER t
kOUTPUT
AFTER t
ClR
S/A
A
B
ClK
L
L
H
X
X
X
X
X
X
L
H
L
H
L
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
L
L
H
L
H
H
H
L
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
H
H
L
L
H
L
H
H
L
L
H
H
H
H
H
level, L = low level, X = irrelevant,
t = transition from low to high level at the clock input
PRQDUCTIDN DATA dO••1IHHI1s oontlin information
curnnt as of publication date. Products conform to
spacifications par the tarms If Texas Instruments
:=~~.i~:1~7i
=::i:; :.. .::::::~:~~ not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-913
SN54LS385. SN74LS385
QUADRUPLE SERIAL ADDERS/SUBTRACTORS
logic symbol t
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS
Vee
CLR 111)
21
CLK III
C2
18k!),
l:/P-Q
NOM
lSllI (31
lA (51
18 (41
OUTPUT
M3
2D
1
3C0/3CI
1
a
4(~CII3BII
1
(ZI
1~
(91
Z~
R
20
3R
Z4
3S
2!'./A (81
ZA (61
2B (71
3S/A (131
3A (151
38 1141
4Siii.
1181
4A (161
1191 4~
48 (171
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and
lEe Publication 617-12.
-f
-f
~
logic diagram (each adder/subtractor, positive logic)
CLK~(~I)~----~)~--------------------------~----------------------+~~~:~~~BTRAeToRS
C
A (5,6, 15, 16)
CD
r--;:lJC?liI'):>-!------------J
<
(:;'
20
(2,9, 12, 19)
~
[SUM]
~-------<4>e2
R
B (4,7, 14, 17)
CD
Ul
siA (3,8, 13, 18)
} TO OTHER
CLR~(~l~l)~--~:>_~~)K~--------------------------------~----------•. AOOER~UBTRAeToRS
Pin numbers shown are for OW, J, or N packages.
2-914
TEXAS . "
INSfRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS385. SN74LS385
QUADRUPLE SERIAL ADDERS/SUBTRACTDRS
recommended operating conditions
SN54LS385
Supply voltage, Vee (see Note 11
High~level
output current, IOH
Low~level
output current, tOl
SN74LS385
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-400
p.A
-400
4
30
0
8
rnA
30
MHz
Clock frequencv. fclock
0
Width of clock pulse, tw
16
16
ns
Setup time, tsu
10
10
ns
3
3
Hold time, th
Operating free-air temperature, T A
-55
125
ns
0
70
°e
NOTE 1: Voltage values are with respect to network ground terminal.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High~level
VIL
low-level input voltage
VIK
Input clamp voltage
MIN
input voltage
TYPt
MAX
High-level output voltage
VOL
Low-level output voltage
Vee = MIN,
11=-18mA
Vee-MIN,
VIH =2V,
VIL = VILmax,
10H = -400p.A
Vee - MIN,
VIH =2V,
VIL = VILmax
MIN
TYPt
MAX
UNIT
V
2
2
VOH
0.7
0.8
V
-1.5
-1.5
V
CD
V
'S;
V
C
rnA
lI-
(I)
(,)
2.5
i IOL=4mA
2.7
3.5
0.25
0.4
IIOL =8 rnA
3.5
0.25
0.4
0.35
0.5
CD
....I
Input current at
II
SN74LS385
SN54LS385
TEST CONDITIONSt
Vee =MAX,
maximum input voltage
VI =7 V
0.1
0.1
IIH
High-level input current
Vee
MAX,
VI =2.7V
20
20
p.A
IlL
Low-level input current
Vee -MAX,
VI-0.4V
-0.4
-0.4
mA
-100
mA
75
mA
lOS
Short-circuit output current§
Vee -MAX
lee
Supply current
Vee =MAX,
-100
-20
See Note 2
48
-20
75
48
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at
Vee.:
5 V, T A""
2soe.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all inputs grounded and all outputs open.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
FROM
TO
(iNPUT)
(OUTPUT)
TEST CONDITIONS
f max
tPLH
30
elock
1:
Clear
1:
tPHL
tPHL
MIN
eL=15pF,
See Note 3
RL = 2
kn,
TYP
MAX
40
UNIT
MHz
14
22
18
27
18
30
ns
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section .1.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-915
-I
-I
r0-
C
(I)
<
(i'
(I)
en
2-916
SN54LS386A. SN74LS386A
QUADRUPLE 2·INPUT EXCLUSIVE·DR GATES
MARCH 1974 - REVISED MARCH 1988
•
SN54LS3B6A •.. J OR W PACKAGE
SN74LS3B6A •.• 0 OR N PACKAGE
Electrically Identical to
SN54LS86A/SN74LS86A
•
(TOP VIEW)
Mechanically Identical to
Vee
SN54L86/SN74L86
•
Total Average Propagation Delay
Times ... 10 ns
•
Typical Total Power
Dissipation ... 30.5 mW
1B
1Y
:4B
4A
4Y
3Y
3B
3A
2B
GND
FUNCTION TABLE
(EACH GATE)
INPUTS
A
B
SN54LS3BBA ... FK PACKAGE
(TOP VIEW)
OUTPUT
L
L
L
L
H
H
H
L
H
H
H
L
3 2 1 2019
H "" high level
L = low level
logic symbol t
lA
(1)
(3)
=1
(2)
18
(5)
2A
1Y
(4)
(6)
28
(81
3A
191
38
1121
4A
(131
48
(10)
(11)
..oJ
NC - No internal connection
2Y
logic diagram leach gate)
3Y
4Y
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
lI-
:--+D)---Y
positive logic
Y = A€>B
schematics of inputs and outputs
=
AB + AB
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
----------~----VCC
--
VCC
250 Il NOM
12.5 kll NOM
INPUT
.,.
--
u ...
1.....__.....____ OUTPUT
"
~~
~,
m
PRODUCTION DATA documents contain information
currant as of publication date. Products conform to
specifications per the terms of rexas Instruments
=:~~:~~i~ai::,~l~ ~~::i~~ti:; :'~O::~:::::t::s~S not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-917
SN54LS386A, SN74LS386A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
I nput voltage . . . . . . .
Operating free-air temperature range: SN54LS386A
SN74LS386A
Storage temperature range
7V
7V
_55°C to 125°C
oOe to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS386A
MIN
Supply voltage, Vee
4.5
High-level output current, IOH
Low-level output current, IOl
Operating free-air temperature, T A
NOM
SN74LS386A
MAX
MIN
NOM
5.5
4.75
5
5
-400
MAX
5.25
V
-400
jlA
8
rnA
70
"e
4
-55
125
UNIT
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
-t
-t
rC
CD
<
c:;-
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
I nput clamp voltage
VOH High-level output voltage
CD
en
MIN
TVPt
MAX
2
Vee
MIN.
II
Vee = MIN.
VIH=2V.
VIL = Vil
VIH=2V.
I
2.5
MIN
TVP*
MAX
UNIT
V
2
-18 rnA
max. 10H = -400 jlA
VIL = VIL
Vee - MIN
VOL Low-level output voltage
SN74LS386A
SN54LS386A
TEST eONDITIONSt
0.7
0.8
V
-1.5
-1.5
V
3.4
2.7
V
3.4
-
IOL=4rnA
0.25
0.4
0.25
0.4
0.35
0.5
V
maxi 10l = 8 rnA
rnA
II
Input current at maximum input voltage
Vee- MAX.
VI-7 V
0.2
0.2
IIH
High-level input current
Vee = MAX,
VI-2.7V
40
40
jlA
III
Low-level input current
Vee = MAX,
VI = 0.4 V
-0.8
-0.8
rnA
lOS
Short-circuit output current ~
Vee = MAX
ICC
Supply current
Vee
MAX,
-20
See Note 2
-100
6.1
-20
10
-100
rnA
6.1
10
rnA
TVP
MAX
12
23
10
17
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAil typical values are at V CC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.
switching characteristics, Vee = 5 V. TA = 25°e
PARAMETER
tplH
FROM
(INPUT)
Aor8
TEST CONDITIONS
Other input low eL=15pF,
tpHL
tplH
RL=2kn,
Aor8
Other input high See Note 3
tpHL
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-918
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
20
30
13
22
UNIT
ns
ns
SN54390. SN54LS390. SN54393. SN54LS393.
SN74390. SN74LS390. SN74393. SN74LS393
DUAL 4·BIT DECADE AND BINARY COUNTERS
OCTOBER 1976 - REVISED MARCH 1988
•
Dual Versions of the Popular '90A, 'LS90
and '93A, 'LS93
•
'390, 'LS390 •. , Individual Clocks for A and B
Flip-Flops Provide Dual 7 2 and 7 5 Counters
•
'393, 'LS393 , , , Dual 4-Bit Binary Counter
with Individual Clocks
•
All Have Direct Clear for Each
4-Bit Counter
•
Dual4-Bit Versions Can Significantly Improve
System Densities by Reducing Counter Package
Count by 50%
•
Typical Maximum Count Frequency, , , 35 MHz
•
Buffered Outputs Reduce Possibility of Collector
Commutation
SN54390. SN54LS390 ... J OR W PACKAGE
SN74390 ... N PACKAGE
SN74LS390 ... D OR N PACKAGE
(TOP VIEW)
lCKA
lCLR
lOA
lCKB
lOB
1OC
10 0
GNO
SN54LS390 ... FK PACKAGE
(TOP VIEWI
2CLR
20A
NC
2CKB
20B
lOA
lCKB
NC
lOB
1OC
description
Each of these monolithic circuits contains eight
master-slave flip-flops and additional gating to implement two individual four-bit counters in a single
package_ The '390 and 'LS390 incorporate dual
divide-by-two and divide-by-five counters, which can
be used to implement cycle lengths equal to any
whole and/or cumulative multiples of 2 and/or 5 up
to divide-by-100_ When connected as a bi-quinary
counter, the separate divide-by-two circuit can be
used to provide symmetry (a square wave) at the final
VCC
2CKA
2CLR
20A
2CKB
20B
2OC
20 0
CI)
CI)
(,)
'S;
CI)
C
00 u 0 U
02200
...... (!)
...J
NN
SN54393. SN54LS393 ... J OR W PACKAGE
SN74393 ... N PACKAGE
SN74LS393 ... D OR N PACKAGE
(TOP VIEW)
output stage_ The '393 and 'LS393 each comprise
two independent four-bit binary counters each having
a clear and a clock input. N-bit binary counters can
be implemented with each package providing the
capability of divide-by-256. The '390, 'LS390, '393,
and 'LS393 have parallel outputs from each counter
stage so that any submultiple of the input count
frequency is available for system-timing signals.
Series 54 and Series 54LS circuits are characterized
for operation over the full military temperature range
of _55°C to 125°C; Series 74 and Series 74LS
circuits are characterized for operation from oOe
to 70°C.
lA
lCLR
lOA
lOB
1OC
100
GNO
lI-
VCC
2A
2CLR
20A
20B
2OC
20 0
8
SN54LS393 ..• FK PACKAGE
(TOP VIEWI
lOA
NC
lOB
NC
10c
2CLR
NC
20A
NC
20B
5
6
7
8
9 10 111213
00 U
0
U
02200
..... (!)
NN
NC . No internal connection
PRODUCTION DATA documents conlain information
current I I of publication datI. Products conform to
specifications par the terms of Texas Instruments
::=~~i;I:::1~7~ ~!~:~i:; :I~O::;::::~:~~ not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-919
SN54390. SN54LS390. SN54393. SN54lS393.
SN74390. SN74LS390. SN74393. SN74LS393
DUAL 4"BIT DECADE AND BINARY COUNTERS
FUNCTION TABLES
'390, 'LS390
BCD COUNT SEQUENCE
(EACH COUNTER)
'390, 'LS39D
BI-OUINARV (5-2)
(EACH COUNTER)
(See Note A)
(Soo Noto B)
COUNT
0
1
L
L
L
0
1
H
OUTPUT
QA QD QC QB
L
L
L
L
L
L
L
H
2
L
L
H
L
2
L
L
H
L
L
L
H
H
3
L
L
H
H
4
L
H
L
L
4
L
H
L
L
5
6
L
H
L
H
5
H
L
L
L
L
H
H
L
L
L
H
L
H
H
H
H
L
H
L
8
H
L
L
L
H
L
H
H
9
H
L
L
H
6
7
8
9
H
7
H
H
L
L
A. Output QA is connected to input B for BCD count.
B. Output aD Is connected to input A for bi-quinary
count.
C. H "" high level, L "" low level.
-f
-f
<
c;"
L
°B °A
L
L
H
1
L
L
L
2
L
L
H
L
3
L
H
H
4
L
L
H
L
L
5
6
7
8
L
H
L
H
L
H
H
L
L
H
H
H
H
L
L
L
9
H
L
L
H
10
H
L
H
L
11
H
L
H
H
12
H
H
L
L
13
H
H
L
H
14
H
H
H
L
15
H
H
H
H
'390, 'LS390
'390, 'LS39D
CD
Dc
0
QD
L
logic symbols t
logic diagrams (positive logic)
C
CD
COUNT
OUTPUT
COUNT
3
NOTES:
r-
OUTPUT
QD QC QB QA
L
L
L
L
'393, 'LS393
COUNT SEQUENCE
(EACH COUNTER)
11,15\
INPUT A - - - - - - - - - - - - - < > I >
til
(31
1QA
CLEAR
1----::::","""--1
(&)
IS)
as
171
IS, 11) OUTPUT
INPUT B-'I-'4,_'Z_'+_ _ _ _ _-.-f~
DB
I.,
O)W
101 OUTPUT
CT
DC
f
'Os
'ac
100
113)
ZO.
1111
zo.
110)
(9)
Z
ZOe
ZOo
ac
CLEAR
'393, 'LS393
17,
Qo
9)
CTRDIV16
OUTPUT
Do
leLR
aD
IZ,
CLEAR 14\
INPUT
CLEAR
--t;><....t!=========~=~
12)
cr-o
err
13)
'D.
(4)
(5)
'Os
'ac
(S)
'°0
1111
zo.
no)
(B)
(8)
ZO.
ZDc
ZOo
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and
IEC Publication 617-12,
Pin numbers shown are for 0, J, N, and W packages.
2-920
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54390, SN54LS390, SN54393,SN54LS393,
SN74390, SN74LS390, SN74393, SN74LS393
DUAL 4·BIT DECADE AND BINARY COUNTERS
'393, 'LS393
logic diagrams (continued)
13, 11) OUTPUT
(1,13)
°A
----4 T
INPUT A
CLEAR
14, 10) OUTPUT
DB
15,9) OUTPUT
QC
16, 8) OUTPUT
QO
CLEAR
CLEAR 12. 12) ~",l.-=:':jr""
INPUT
;
schematics of inputs and outputs
Q
Pin numbers shown are for 0, J, Nand W packages.
'390, '393
EQUIVALENT OF EACH INPUT
VCC
TYPICAL OF ALL QUTPUTS
Req
INPUT
A
--
INPUT
('390).
ReQ NOM
.... 3 k!!
B
('390) ...... 1.5 k!!
A
('393)...... 3 kH
Any clear.
8 kn
'LS390, 'LS393
EQUIVALENT OF EACH
A AND B INPUT
EQUIVALENT OF EACH
CLEAR INPUT
VCC3--
TYPICAL OF ALL OUTPUTS
VCC=:E~~M
Req
' '"' q--
INPUT
--
INPUT
Req NOM
A ('LS3901. ........ 4.3 kH
B ('LS390) ......... 2.7 kH
A ('LS393) ......... 4.3 k!!
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·921
SN54390, SN54393, SN74390, SN74393
DUAL 4·BIT DECADE AND BINARY COUNTERS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Operating free-air temperature range: SN54390, SN54393
SN74390, SN74393
Storage temperature range
7V
5.5V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54390
SN74390
SN54393
SN74393
MIN
Supply voltage, Vee
4.5
NOM
5
High-level output current. IOH
Low-level output current, IOL
oCD
<
(:;'
NOM
5.5
4.75
5
16
A input
B input
Pulse width, tw
0
25
0
20
5.25
V
-800
/lA
rnA
16
25
0
20
20
20
B input high or low
25
25
Clear high
20
20
-55
125
MHz
ns
n,
251
251
Operating free-air temperature, T A
UNIT
MAX
0
A input high or low
Clear inactive-state setup time, tsu
r-
MIN
-800
Count frequency. fcount
-I
-I
MAX
70
0
DC
"The arrow indicates that the falling edge of the clock pulse is used for reference.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
CD
en
TEST eONDITIONst
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
IIH
Low-level output voltage
IlL
maximum input voltage
High-level input current
Low-level input current
TvPt
'393
MAX
2
Input current at
II
'390
MIN
~
~
Input B
~
Input A
Vee - MIN,
11=-12rnA
Vee=MIN,
VIH = 2 V,
VIL=0.8V,
IOH = -800/lA
Vee=MIN,
VIH =2V,
VIL = 0.8 V,
IOL = 16rnA~
Vee= MAX,
VI = 5.5 V
Vee = MAX,
2.4
MIN
TVPt
MAX
0.8
0.8
V
-1.5
-1.5
V
3.4
0.2
VI = 2.4 V
UNIT
V
2
2.4
0.4
3.4
0.2
V
0.4
1
1
40
40
80
80
V
rnA
/lA
120
Vee = MAX,
VI=o.4V
""inj);rtB
-1
-1
-3.2
-3.2
rnA
-4.8
lOS
Short-circuit output current §
Vee= MAX
lee
Supply current
Vee =
ISN54'
-20
-57
-20
ISN74'
-18
-57
-18
MAX, See Note 2
42
69
-57
-57
38
64
rnA
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*All typical values are at Vee = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time.
, The QA outputs of the '390 are tested at IOL = 16 rnA plus the limit value for I,L for the B input. This permits driving the B input while maintaining
full fan-out capability.
NOTE 2: ICC is measured with all outputs open, both clear inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.
2-922
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN5439l SN5439t SN7439l SN74393
DUAL 4·BIT DECADE AND BINARY COUNTERS
switching characteristics, Vee
PARAMETER
f max
tpLH
tPLH
tPLH
tpHL
tpLH
25°e
(OUTPUT)
A
TEST CONDITIONS
'390
MIN
TYP
OA
25
35
S
Os
20
30
A
OA
A
S
'393
MAX
MIN
TYP
25
35
MAX
20
12
20
12
13
20
13
20
CL"15pF,
37
60
40
60
0D of '393
RL"400n,
39
60
40
60
See Note 3
13
21
and
14
21
24
39
26
39
13
21
Os
Figure 1
QC
B
QD
Clear
Any
14
21
24
39
UNIT
MHz
Oc of '390
S
tpHL
tpHL
=
(INPUT)
tPHL
tpHL
5 V, T A
TO
tpHL
tPLH
=
FROM
ns
ns
ns
ns
m
24
39
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
I/)
Q)
o
'S;
Q)
C
...J
lI-
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-923
saO!AaO
I\)
«>
I\)
lJ.J.1I
.'"=
cun
~
=2
r-~
of"
a:I=
:::j~
.W
c;,2
m'"
n~
~~~~~
~:5V---~I-----------~I---------::
{1.5V
I
I
t--
tsu
i-
l
~
1
~
;cr;;i
r----r-OUTPU:~~ ---+I-"'\~
~~
~
..
I
·390B
INPUT
I
1.5 V
tPHL
,\'.5 V
'.5 V
M••sure
."n+'
!IoU
!'----I-I
I
~
I
~ tpHL
~ tpLH - Measure at tn+2
l. '.5V
\
1
-- --'I
I -\-
I
:
1
'i"
f'.5V
t----:I}
I
'.5V
~ tpHL
_ _ _ ~'
"\','.5 V
,
((
I
r----t:
I
tpLH - Measure at t n+4
I !'.5V
I .
~ tpLH -
..
I
I
I
I.
VOL
tpHL - Measure at to+4
Measure at to+8
I
!'.5V
- - - - - - -....- - - - - - - - - 1 1 1 ·
I,
I
-t
at tn+8
Z
"T1
~
LV
OL
Measure at t n+10 for '390
-VOH
ortn+16 fo ('393
te---:}t PHL ~'.5V
'\:.VOL
VOLTAGE WAVEFORMS
NOTE A: Input pulses are supplied by a generator having the following characteristics tr '" 5 ns, tf ..; 5 ns, PRR :::: 1 MHz, duty cycle"'" 50%, Zout~ 50 ohms.
FIGURE 1
m
m
Z
\:.
I
I
~:D
:s::
);.'.5V
VOL
q} tpHL - Measure
i
n ......
:s::
If-I--VOH
'.5V
" ,
I"
I
~
W
a:l
-CD
m
m
~
c;, ......
••
:a en
-t
VOH
22
~m
:D
(f-I--VOH
I
\
I
I
I I ·
i
OUTPUT 00
I
I
I
~ tpHL
OUTPUTOC
I
,-U-1 , -- - -
:
!
OV
I
I
tPHL - Measur.
at 'n+2
1\ '.5V
'.5V
:D
'.5 V
I
I
t
'.5 V
_--~I
OUTPUTOB
-;
-,
tpLH~
I
m!-'
.en
--I
tw(clockl
I~~--- 3V
IN:UT
z
c;,CD
o
:D
:s::
~
oz
2=
-<2
Q~
c:=
.....
ZW
m
:a
en
SN54LS390, SN54LS393, SN74LS390, SN74LS393
DUAL 4·BIT DECADE AND BINARY COUNTERS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Clear input voltage . . . . .
Any A or B clock input voltage
Operating free-air temperature range: SN54LS390, SN54LS393
SN74LS390,SN74LS393
Storage temperature range
. 7V
. 7V
5.5 V
_55°C to 125°C
oOe to 70°C
_65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS390
SN54LS393
MIN
Supply voltage. Vee
NOM
4.5
MAX
MIN
NOM
5.5
4.75
5
5
High-level output current, IOH
SN74LS390
SN74LS393
5.25
-400
Low-level output current, IOL
-400
4
A input
Count frequency. fcount
8 input
Pulse width, !w
S
0
25
0
12.5
0
25
0
12.5
A input high or low
20
20
B input high or low
40
40
Clear high
20
20
251
251
Clear inactive-state setup time, tsu
Operating free-air temperature. T A
-55
UNIT
MAX
125
V
~A
rnA
MHz
n.
CI)
Cl)
CJ
n.
0
70
oS
'e
Cl)
J. The arrow indjcates that the falling edge of the clock pulse is used for reference.
C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDITIONSt
PARAMETER
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
Low-level output voltage
Input current at
II
IIH
maximum input voltage
High-level input current
MIN TYP+
Vee 0 MIN,
11 0 -18mA
Vee - MIN,
VIH -2V,
-400~
VIL 0 VILmax,
10H ~
Vee 0 MIN,
VIH 0 2 V,
VIL 0 O.S V,
~
~
2.5
IOLo4mA~
0.25
VI-7 V
VI 05.5 V
Input B
~
~ Vee 0 MAX,
Low-level input current
~ Vee 0 MAX,
~
VI 02.7 V
Vl o O.4V
Input B
lOS
Short-circuit output current~
lee
Supply current
V
-1.5
-1.5
V
2.7
0.4
-20
Vee - MAX
V
3.4
0.25
0.4
0.35
0.5
0.1
0.1
0.2
0.2
0.4
0.4
0.02
0.02
0.1
0.1
0.2
0.2
-0.4
-0.4
-1.6
-1.6
-2.4
-2.4
-100
lI-
V
O.S
3.4
...J
UNIT
0.7
10L-SmA'1
Vee 0 MAX
MAX
2
Input B
IlL
MAX MIN TYP+
2
VIH
VOL
SN74LS'
SN54LS'
-20
-100
Vee - MAX,
'LS390
15
26
15
26
See Note 2
'LS393
15
26
15
26
V
mA
rnA
rnA
rnA
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t. All typical values are at Vee = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
, The QA outputs of the 'LS390 are tested at tOL = MAX plus the limit value for IlL for the clock B input. This permits driving the clock B input
while maintaining full fan-out capability.
NOTE 2: ICC is measured with all outputs open, both clear inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-925
SN54LS39~
SN54LS39t SN74LS39~ SN74LS393
DUAL 4·BIT DECADE AND BINARY COUNTERS
switching characteristics, Vee
PARAMETER
f max
tpLH
QA
25
35
8
Q8
12.5
20
A
A
8
•
TEST CONDITIONS
MIN
TYP
12
QA
QC of 'LS390
QO of 'LS393
QC
8
QO
Clear
Any
20
MIN
TYP
25
35
12
MAX
13
20
13
20
60
40
60
RL"2kn,
39
60
40
60
See Note 4 and Figure 2
13
21
14
21
24
39
26
39
13
21
14
21
24
39
-t
-t
rC
CD
<
(')
CD
VI
-111
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
MHz
20
37
NOTE 4: Load circuits and voltage waveforms are shown in Section 1.
2-926
'LS393
MAX
CL"15pF,
Q8
8
tPHL
tpHL
'LS390
A
tpHL
tpLH
25°e
(OUTPUT)
tpHL
tPLH
=
(INPUT)
tpHL
tPLH
5 V, TA
TO
tPHL
tPLH
=
FROM
ns
ns
ns
ns
ns
24
39
ns
SN54LS39t
SN54LS39~
SN74LS39~
SN74LS393
DUAL 4-BIT DECADE AND BINARY COUNTERS
PARAMETER MEASUREMENT INFORMATION
>
M
>
o
N
;
~
"'
"!
~
u
J
------ -
J:
>
~
!3
...;
I
- - J..
-
i>
i>
D..:3
a..
~
I
oJZ
u-
I
«00 ~
dZ~ ~
.... ctcn z
j
:-1-
..
I-
w
a:
::J
CI
ii:
......
...J
oJ
0
>
to)
r--- r
~
t~-~ t~--~
t
5______ _ _____ f--- 0:1
wo.
if
N
w
i>-'>
~
0
IJ.
w
>
«
;;:
«
I-
---
D..
C
CI
>
M
(1)
'"a:
:;;
I
oJ
M
-S;
~
I
>
(1)
-t--If~-l
oJ
:;;
.,
.3
1;;
1~ --~
~
o
o
"'
~~
o
N
I
if
I
co
5
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-927
-t
-t
....
C
en
~.
(")
en
VI
2-928
SN54LS395A. SN74LS395A
4-BIT CAS CAD ABLE SHIFT REGISTERS WITH 3-STATE OUTPUTS
OCTOBER 1916 - REVISEO MARCH 1988
• Three-State, 4 Bit, Cascadable, Parallel-In,
Parellel-Out Registers
SN54LS395A ... J OR W PACKAGE
SN74LS395A ... D OR N PACKAGE
{TOP VIEWI
• 'LS395A Offers Three Times the Sink-Current
Capability of 'LS396
• Low Power Dissipation _ . . 75 mW Typical
(Enabled)
• Applications:
N-Bit Serial-To-Parallel Converter
N-Bit Parallel-To-Serial Converter
N-Bit Storage Register
ClR
SER
VCC
OA
Os
Oc
A
S
C
0
lO/SH
GNO
00
00'
ClK
OC
description
These 4-bit registers feature parallel inputs,parallel outputs, and clock (ClK), serial (SER), load shift (LD/SH),
output control (OC) and direct overriding clear (ClR)
inputs.
SN54lS395A ... FK PACKAGE
(TOP VIEWI
15
ffi u tl O
Shifting is accomplished when the load/shift control is
low. Parallel loading is accomplished by applying the
four bits of data and taking the load/shift control input
high. The data is loaded into the associated flip-flops
and appears at the outputs after the high-to-Iow transition of the clock input. During parallel loading, the entry
of serial data is inhibited.
When the output control is low, the normal logic levels
of the four outputs are available for driving the loads or
bus lines. The outputs are disabled independently from
the level of the clock by a high logic level at the output
control input. The outputs then present a high impedance and neither load nor drive the bus line;
however, sequential operation of the registers is not affected. During the high-impedance mode, the output at
00' is still available for cascading.
3 2 1 2019
•
t/)
CI)
CJ
'S;
CI)
C
..oJ
lINC ~ No internal connection
logic symbol t
tThis symbol is in accordance with ANSI/IEEE Std. 91·1984 and
IEC Publication 617-12.
Pin numbers shown are for D. J, N. and W packages.
PRODUCTION DATA dec.m.nts aenloin inlar..lti••
cum.1 o. of publicoli•• ~It.. Praducts aenfarm t.
sp.cificatlons plr Ih. II.... of T.x•• Instrum.ots
stlndard wlmlty. Producti•• pra....i•• dOlI oot
....... ril' includ. IIstin. of III pI.. mota...
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 15265
2-929
SN54LS395A, SN74LS395A
4-BIT CASCAOABLE SHIFT REGISTERS WITH 3·STATE OUTPUTS
logic diagram (positive logic)
DATA INPUTS
•
(151
1131
Oc
(141
QA
Q8
(121
Qo
(111
,
QO'
3·STATE OUTPUTS
-4
-4
CASCADE
OUTPUT
r-
Pin numbers shown are for D, J, N. and W packages.
schematics of inputs and outputs
CD
<
(61
(51
(41
\
C
o
C
8
A
(31
t=;"
CD
EQUIVALENT QF SERIAL
AND DATA INPUTS
(I)
o
EQUIVALENT OF
OTHER INPUTS
Vee --....,--vee
TYPICAL OF QA, 0B, 0C, QD
OUTPUTS
---.._-vee
TYPICAL OF QD' OUTPUTS
---_-vee
20k!! NOM
INPUT-H.....-........
INPUT-
-OUTPUT
Serial: Req = 30 kn NOM
A, B, C, D: Req = 20 kn NOM
2-930
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
OUTPUT
SN54LS395A. SN74LS395A
4-BIT CASCADABLE SHIFT REGISTERS WITH 3-STATE OUTPUTS
FUNCTION TABLE
INPUTS
3-STATE OUTPUTS
PARALLEL
CASCADE
OUTPUT
CLR
LD/SH
CLK
SER
L
X
X
X
X
X
X
X
H
H
H
X
X X
X
H
H
I
X
a
b
c
X OAO 0BO Oeo 000
d
d
a
b
c
000
d
H
L
H
X
X
X
X
L
I
H
X
X
X
H
L
I
L
X
X
X
X 0AO 0BO OCO 000
H 0An 0Bn °Cn
X
X
L
0An 0Bn 0Cn
000
H
A B C D
°A
°B
°c
°D
L
L
L
L
°D'
L
°Cn
°Cn
When the output control is high, the 3-5tate outputs are disabled to the high-impedance state;
however, sequential operation of the registers and the output at aD' are not affected.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage. Vee (see Note 1)
...... .
Input voltage . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS395A
SN74LS395A
Storage temperature range
7V
7V
_55°C to 125°C
O°C to 70°C
-65°C to 150°C
I/)
Q)
(.)
-S
Q)
NOTE 1: Voltage vatues are with respect to network ground terminal.
C
..oJ
recommended operating conditions
SN54LS395A
Supply vollage. V CC
High-level output current, IOH
0A. 0B.
MIN
NOM
MAX
MIN
NOM
4.5
5
5.5
4.75
5
Ce. 00
00
low-level output current, tOL
OA, OB,
Ce. 00
0
Width of clock pulse, Iw/clocki
I LO/SH
I All other inputs
Hold time. high-level or low-level data. th
5.25
V
-2.6
rnA
-400
-400
I'A
12
24
rnA
30
0
16
16
40
40
20
20
-55
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAL.LAS, TEXAS 75265
8
rnA
30
MHz
125
0
....
....
ns
ns
10
10
Operating free-air temperature, T A
MAX
UNIT
-1
4
00
Clock frequency. fclock
Setup time, high-level or low-level data, tsu
SN74LS395A
70
ns
°c
2-931
SN54LS395A, SN74LS395A
4·BIT CASCADABLE SHIFT REGISTERS WITH 3·STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIH
High-level input voltage
VIL
low-level input voltage
Input clamp voltage
VIK
VOH
High~evel
outpUt voltage
Vee=MIN,
11=-lamA
Vee= MIN,
VIH=2V,
VIL = VIL max,
IOH = MAX
r
C
CD
<
c:;.
CD
Vil = Vil max,
Dc,OD
Dc,OD
IOl-24mA
VIH = 2 V
OD'
VIH = 2V,
Vee= MAX,
VO=2.7V
Of1-5tate output current.
Vee- MAX,
low-level voltage applied
VO=0.4V
II
Input current at
maximum input voltage
Vee = MAX,
VI = 7 V
IIH
High-level input current
Vee= MAX,
VI =2.7V
III
Low-level input current
Vee = MAX,
VI =0.4V
lOS
Short-circuit output current§
Vee= MAX
SN74LS395A
MAX
Vee = MAX,
MIN
TYP*
MAX
UNIT
V
2
0.7
o.a
V
-1.5
-1.5
V
3,4
2.4
2.7
3.4
0.25
0.4
0.25
0.4
IOl =amA
OA,OB,
3.1
V
3,4
V
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
V
V
20
20
I'A
-20
-20
I'A
0.1
0.1
mA
20
20
-0.4
-0.4
I'A
mA
Dc,OD
VIH=2V,
°A,Oa,
Dc,OD
-30
-130
-30
-130
mA
-20
-100
-20
-100
mA
Dc,OD
OD
Supply current
2.5
IOl -4 mA
OA,OB,
ICC
TYP*
2.4
°D'
IOl = 12 mA
Off-state output current,
IOZl
-t
-t
Low-level output voltage
OA,Oa,
OA,OB,
high·level voltage applied
IOZH
MIN
2
Vee=MIN,
VOL
SN54LS395A
TEST CONDITIONSt
PARAMETER
See Note 2
Condition A
22
34
22
34
Condition B
21
31
21
31
mA
(I)
t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:tAli typical values are at Vee ::= 5 V. T A = 2Soc.
§ Not more than one output should be shorted at a time,and duration of the short~circuit should not exceed one second.
is measured with the outputs open, the serial input and mode control at4.5 V, and the data inputs grounded under the following
conditions:
A. Output control at 4.5 V and a momentary 3 V, then ground, applied to clock Input.
·B. Output control and clock input grounded.
NOTE 2: IcC
switching characteristics, Vee = 5 V, T A = 25° C
PARAMETER
f max
tpHl
tPlH
tpHl
TEST CONDITIONS
Maximum clock frequency
Propagation delay time, high-to-Iow-Ievel output from clear
Propagation delav time,low-to-high-level output
Propagation delay time, high~to-Iow-Ievel output
See Note 3,
OA, 0B, Dc, 0D outputs:
Rl = 667 n, el = 45 pF
aD' output:
MIN
30
TYP
MAX
45
UNIT
MHz
22
35
ns
15
30
ns
20
30
ns
15
25
ns
tpZl
Output enable time to high level
Output enable time to low level
17
25
ns
tPHZ
Output disable time from high level
el = 5 pF,
11
17
ns
tPlZ
Output disable time from low level
See Note 3
12
20
ns
tpZH
Rl=2kn,el=15pF
NOTE 3: load circuits and voltage waveforms are shown in Section 1.
2-932
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS396. SN14LS396
OCTAL STORAGE REGISTERS
02329, MARCH 1977 - REVISED MARCH 1988
•
Parallel Access
•
Typical Propagation Delay Time, , , 20 ns
•
Typical Power Dissipation" , 120 mW
•
Applications:
N-Bit Storage Files
Hex/BCD Serial-To-Parallel Converters
SN54LS396 ... J OR W PACKAGE
SN74LS396 ... 0 OR N PACKAGE
ITOPVIEWI
201
101
01
202
VCC
G
204
104
D4
203
103
03
102
description
02
ClK
GNO
These octal registers are organized as two 4·bit bytes
of storage. Upon application of a positive-going clock
signal, the information stored in byte 1 is transferred
into byte 2 as a new 4-bit byte is loaded into the
byte 1 location via the four data lines. The full 8-bit
word is available at the outputs after two clock
cycles. Both the clock and the strobe lines are fully
buffered.
SN54LS396 ... FK PACKAGE
ITOP VIEWI
u
~~
~ ~ ~ ~1C!l
logic symbol t
101
201
01
4
202
NC
5
6
102
02
7
204
104
NC
D4
203
8
102
Q)
CJ
'S;
Q)
C
.......I....
202
103
203
10'
204
0'
II)
NC - No internal connection
tThis symbol is in accordance with ANSIIIEEE Std. 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for Of J, N, and W packages.
FUNCTION TABLE
INPUTS
STROBE
Ii
CLOCK
OUTPUTS
BYTE 1
DATA
BYTE 2
01
02
03
04
101
102
103
104
201
202
203
204
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
t
a
b
c
d
a
b
c
d
lOin
102n
103 n
104"
H = high level (steady state), L = low level (steady state), X = irrelevant (any input, including transitions)
t = transition
from low to high level
1Q1 n • 1Q2 n • 1Q3 n • 1Q4n = the level of 1Q1, 1Q2, 1Q3, and 1Q4, respectively, before the most recent
t
transition of the clock.
PRODUCTIOI DATA documents •••tain information
currant
I' of publication date. Products canform ta
spacificationl par tha terml of Tuas Instrumants
TEXAS . .
nat
INSTRUMENTS
:=~~~a{:I-:.r~ ~r:\::i:
:.r:::=s
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
2-933
SN54LS396. SN74LS396
OCTAL STORAGE REGISTERS
logic diagram (positive logic)
schematics of inputs and outputs
~-::--l.fS~:=:~~==,,=,,"=o--d
CLOCK",,17,,-}
0--
EQUIVALENT OF EACH
INPUT
01 13}
TYPICAL OF ALL OUTPUTS
----z>O
3
description
This monolithic quadruple two-input multiplexer with
storage provides essentially the equivalent functional
capabilities of two separate MSI functions
(SN54LS157/SN74LS157 and SN54LS175!
SN74LS175) in a single 16-pin package.
When the word-select input is low, word 1 (A 1, Bl,
Cl, Dl) is applied to the flip-flops. A high input to
word select will cause the selection of word 2 (A2,
B2, C2, D2). The selected word is clocked to the
output terminals on the positive-going edge of the
clock pulse.
Al
4
A2
5
NC
B2
Bl
6
DA
DB
..J
lI-
WS
ClK
Al
(21
A2
m
C2
(121
DO
01
(141
0
(131
L
t
01
b1
c1
dl
f
02
b2
c2
d2
X
L
QAO
QBO
QCO
QOO
===i~·tnr:l:ri ~:\::i:r lIr::;::~::a~1 nat
CJ
QA
QB
Cl
H
PRODUCTIOI DATA documants c.nlain information
currl.t II of puillicetion dati. Preducts cDRfann to
specifications per the terml of Till. Instrumentl
CI)
os:
logic symbol t
B2
DC
en
NC - No internal connection
OUTPUTS
CLOCK
01
02
NC
C2
Cl
CI)
FUNCTION TABLE
WORD
1 20 19
o
Bl
SELECT
2
9 10 111213
Typical power dissipation is 37 milliwatts. The
SN54LS399 is characterized for operation over the full
military range of - 55 DC to 125 DC. The SN74LS399
is characterized for operation from 0 DC to 70 DC.
INPUTS
ac
(101
(151
Qc
Qo
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-937
SN54LS39~ SN74LS399
QUADRUPLE 2·INPUTMULTIPLEXERS WITH STORAGE
logic diagram (positive logic)
A1--------;-""""
WORD
s
~
SELECT
DA
C1
A2---+--+-+--L-'
--
1R
B1-----+-+--;-""""
lS
DB
Cl
B2~------~~4-~
C1-----+-+--r"""""
Qc
Cl
C2-----+-+--LJ
-t
-t
,r-
D1-----+-+-r-~
C
CD
DD
~.
D2-------L--I
~
VI
Cl
L---+--l1R
CLOCK - - - - - - - - - -
schematics of inputs and outputs
--
VCC
INPUT
....
'.,....
~~
-
----+-VCC
Req
INPUT
'""'...."
'-
OUTPUT
,Ir
Il
2-938
--
VCC
30 k!!
NOM
i~
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF
OTHER II~PUTS
EQUIVALENT OF
EACH DATA INPUT
1
~~
r.
Clock: Req
Word select: Req
~
17 k!! NOM
25 k!! NOM
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLA.S, TEXAS 75265
SN54LS399, SN74LS399
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range: SN54LS399. . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
SN74LS399 ........................... DoC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminals.
recommended operating conditions
SN54LS399
Supply vollage, vee
SN74LS399
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-400
p.A
8
mA
High-level output current, IOH
-400
Low-level output current, tOl
4
Width of clock pulse, high or low level, tw
Setup time, tsu
Hold time, th
20
20
Data
25
25
Word select
45
45
Data
0
0
Word select
0
Operating free-air temperature, T A
UNIT
MIN
ns
ns
ns
0
-55
125
0
70
en
G)
"e
CJ
'S;
G)
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS399
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
II
Low-level output voltage
TEST eONDITIONSt
MIN TYP:j:
SN74LS399
MAX MIN
2
Vee = MIN,
11=-18mA
Vee=MIN,
VIH = 2 V,
VIL = VILmax
10H = -400p.A
Vee = MIN,
VIH=2V,
2.5
VIL = VILmax
TYp:j:
MAX
2
UNIT
V
0.7
0.8
V
-1.5
-1.5
V
3.4
0.25
IIOL -4mA
C
2.7
0.4
riaL =8mA
3.4
...J
~
V
0.25
0.4
0.35
0.5
V
Input current at
Vee = MAX,
VI = 7 V
0.1
0.1
IIH
High-level input current
Vee=MAX,
VI = 2.7 V
20
20
p.A
IlL
Low-level input current
Vee- MAX,
VI=0.4V
-0.4
-0.4
mA
lOS
Short-circuit output current§
Vee=MAX
-100
mA
ICC
Supply current
Vee = MAX,
13
mA
maximum input voltage
-20
See Note 2.
-100
7.3
-20
13
7.3
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 2SoC.
§ Not more than one output should be shorted at a time, duration of the short-circuit should not exceed one second.
NOTE 2: With all outputs open and all inputs except clock low,
the clOck input.
lec
is measured after applving a momentary 4.5 V, followed by ground, to
switching characteristics, Vee = 5 V TA = 25°e
PARAMETER
TEST CONDITIONS
IpLH
Propagation delay time, low-to-high-Ievel output eL=15pF,
IpHL
Propagation delav time, high-to-Iow-Ievel output See Note 3
RL = 2 kf!,
MIN
TYP
MAX
18
27
21
32
UNIT
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-939
-t
-t
r-
oCD
~.
C')
CD
CII
2-940
SN54LS422, SN54LS423, SN74LS422, SN74LS423
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
JANUARY 1980 - REVISED MARCH 1988
• Will Not Trigger from Clear
SN64LS422 ... J OR W PACKAGE
SN74LS422 ... 0 OR N PACKAGE
• D-C Triggered from Active-High or ActiveLow Gated Logic Inputs
(TOP VIEWI (SEE NOTES 1 THRU 41
AI
VCC
RextlCext
NC
A2
• Retriggerable for Very Long Output Pulses.
Up to 100% Duty Cycle
81
~
• Overriding Clear Teminates Output Pulse
CLR
Cext
NC
GND
Rint
0
a
• 'LS422 Hes Internal Timing Resistor
description
The 'LS422 and 'LS423 are identical to 'LS122 and
'LS 123 except they cannot be triggered via clear.
SN64LS422 ... FK PACKAGE
(TOP VIEW) (SEE NOTES 1 THRU 41
These doc triggered multivibrators feature output-pulsewidth control by three methods. The basic pulse time is
programmed by selection of external resistance and
capacitance values Isee typical application datal. The
'LS422 contains an internal timing resistor that allows
the circuits to be used with only an external capacitor, if
so desired. Once triggered, the basic pulse width may be
extended by retriggering the gated low-level-active IAI
or high-level-active 181 inputs, or be reduced by use of
the overriding clear. Figure 1 illustrates pulse control by
retriggering and early clear.
J
ulc
~<~~cl
9 10111213
The 'LS422 and 'LS423 have enough Schmitt hysteresis
to ensure jitter-free triggering from the 8 input with transition rates as slow as 0.1 millivolt per nanosecond. The
'LS422 Rint is nominally 10k ohms.
10 ~ ~ 0 ~
CJ
The SN54LS422 and SN54LS423 are characterized for
operation over the full military temperature range of
-- 55°C to 125°C. The SN74LS422 and SN74LS423
are characterized for operation from O°C to 70°C.
SN54LS423 ... FK PACKAGE
(TOP VIEW) (SEE NOTES 1 THRU 4)
J
SN54LS423 ... J OR W PACKAGE
SN74LS423 ... 0 OR N PACKAGE
~
(TOP VIEWI (SEE NOTES 1 THRU 4)
lA
18
lCLR
{O
20
2Cext
2Rext /Cext
GND
NOTES:
VCC
1 Rext/Cext
lCext
10
20
2CLR
28
2A
2Cext
1. An external timing capacitor may be connected between C ext and Rext/Cext (positivel.
2. To use the internal timing resistor of 'LS422, connect Rint to Vee3. For improved pulse width accuracy and repeatability, connect an external resistor between
Rext/C~xt
and
Vee
with Rlnt
open-circuited.
4. To obtain variable pulse widths, connect an external variable resistance between Rint or Rsxt/Cext and
Vee.
PRODUCTION DATA documents contain information
current 8S of publicatiDn data. Products cDnfDrm tD
spacificatiDns par the tarms at T8xas Instrumants
::-::!:~~i~air::1~7i ~~:~::i:r :1~U::::::~::'s nat
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-941
SN54LS422. SN54LS423. SN74LS422.SN74LS423
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
description (continued)
'LS422
FUNCTION TABLE
OUTPUTS
0
0
INPUTS
CLEAR A1 A2 B1
'LS423
FUNCTION TABLE
B2
L
X
X
X
X
L
H
x
x
x
H
H
X
X
Lt
Ht
X
Lt
Ht
L
H
x x L
x x X
x !
L
H
H
L
X
H
!
ct
J1
J1
H
X
L
I
H
n.
H
x
L
H
I
J1
"
"
"
H
I
I
H
H
"
H
I
I
"
Ht
U
U
OUTPUTS
Q
a
A
B
L
X
X
L
H
X
H
x
Lt
Ht
x
x
L
Lt
Ht
H
L
!
I
H
J1
Il
H
U
U
U
U
U
li
n.
n.
n. u
"
H
INPUTS
CLEAR
t These lines of the functional tables assume that the indi·
cated steady-state conditions at the A and B inputs have
been set up long enough to complete any pulse started before the set up.
-4
-4
rC
RETRIGGER PULSE
Is.. Notel
• INPUT
CD
~________~~L______________~_______
I
<
n'
CD
en
I
I - - - - tw + tplH-------I
I
I
OUTPuroJ.~_. _----+.,1
: _______L ,-
w
fQUTPUT WITHOUT RETRIGGER
OUTPUT PULSE CONTROL USING RETRIGGER PULSE
BINPUT~L-____________________________________
CLEAR
OUTPUT
a
,.--______---,LJ
J
OUTPUT WITHOUT CLEAR
L I_ _
- __
-_
-_
_
-_
- - - - ' : ' - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
OUTPUT PULSE CONTROL USING CLEAR INPUT
NOTE:
Retrigger pulses starting before 0.22 C ext (in picofrads)
nanoseconds after the initial trigger pulse will be ignored
and the output pulse will remain unchanged.
FIGURE 1-TYPICAL INPUT/OUTPUT PULSES
2-942
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS422. SN54LS423. SN74LS422. SN74LS423
RETRIGGERABLE MONOSTABLE MUL TlVIBRATORS
logic symbols t
'LS422
&
11.
1A
16)
m
10
1B
18) 0
1CLR
11
lC ex t
1 Rut/Cext
lSI
2A
20
20
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagrams (positive logic)
'LS422
113)
19)
Al
Ill)
A2
Bl
B2
CLR
18)
Rext/Cext
Rint
Cext
Q
.Ji!_ _ _J-"'L...-1
_1~5~1________________-aR
16)
a
•
II)
CI)
(,)
'S;
CI)
C
..J
l-
Rint is nominally 10 k ohms
I-
'LS423
~~:::~..
CLR
R
Q
Pin numbers shown are for D, J, N, and W packages.
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
~~~"O"
_t ~M
17 kl!
.".
~~
--~
r
1
rl
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-943
SN54LS422, SN54LS423, SN74LS422, SN74LS423
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
recommended operating conditions
SN54LS'
SN74LS'
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-400
p.A
8
mA
260
kn
Supply voltage, V CC
High-level output current, IOH
-400
Low-level output current, IOl
4
Pulse width, tw
40
40
External timing resistance, Rext
External capacitance. Cext
180
5
ns
5
No restriction
No restriction
50
Wiring capacitance at Rext/Cext terminal
Operating free-air temperature, T A
UNIT
MIN
-55
125
0
50
pF
70
°c
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
-t
-t
r
<
,;,
CD
en
VOH
High-level output voltage
VOL
IIH
IlL
lOS
ICC
t For
TEST CONOITIONSt
Low-level output voltage
Input current at
II
C
CD
VIH
ViL
VK
High-level input voltage
Low-level input voltage
Input clamp voltage
maximum input voltage
High-level input current
Low-level input current
Short-circuit output current §
Supply current
(quiescent or triggered)
VCC- MIN,
VCC - MIN,
VIL = VILmax
VCC- MIN,
VIL = VILmax
II =-1BmA
VIH-2V,
IOH = -4001'A
IIOL -4 mA
VIH 2 V,
IIOL BmA
VCC = MAX,
VI = 7 V
VCC -MAX,
VCC MAX,
VCC -MAX
VI = 2.7 V
VI-0.4V
VCC =MAX,
See Note 6
SN54LS'
SN74LS'
UNIT
MIN TYPt MAX MIN TYPt MAX
2
V
2
0.7
O.B
V
-1.5
-1.5
V
2.5
3.5
2.7
0.25
-20
6
12
'LS422
I'LS423.
0.4
V
3.5
0.25
0.35
0.4
0.5
V
0.1
0.1
mA
20
-0.4
100
11
20
20
-0.4
100
11
20
I'A
mA
mA
20
6
12
mA
c~nditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time and duration of the sho'rt-circuit should not exceed one second.
NOTES: 5. To measure VOH at 0, VOL at Q. or lOS at 0, ground Rext/Cext, apply 2 V to B and clear, and pulse A from 2 V to 0 V.
6. With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground. then 4.5 V, is applied
to clock.
switching characteristics, Vee = 5 V, T A = 25°e, see note 7
PARAMETER.
tPLH
tPHL
FROM
(INPUT)
A
B
A
B
TO
(OUTPUT)
TEST CONDITIONS
a
a
a
tPHL
tpLH
twa (min)
Clear
a
A or B
a
twa
Aor B
a
Cext = 0,
CL=15pF,
Cext = 1000 pF,
CL=15pF,
, two == width of pulse output O.
NOTE 7: load circuits and voltage waveforms are shown in Section 1.
2-944
MIN
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
R ext = 5 kn,
RL = 2 kn
R ext = 10 kn,
RL = 2 kn
4
TYP
MAX
23
23
32
34
20
2B
116
33
44
45
56
27
45
200
4.5
5
UNIT
ns
ns
ns
ns
1"
SN54LS422. SN54LS423. SN74LS422. SN74LS423
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
TYPICAL APPLICATION DATA FOR 'LS422, 'LS423t
The basic output pulse width is essentially determined
by the values of external capacitance and timing
resistance. For pulse widths when Cext :s 1000 pF,
use Figure 3. For Cext between 0.1 nF and 1 I'F, the
pulse width may be defined as:
VCC
tw '" K.RT'Cext
RT
with K obtained from Figure 4.
When Cext
as:
«
1 I'F, the output pulse width is defined
tw '" 0.33.RT'Cext
Where
To Cext
RT is in kilohms (internal or external timing
resistance)
Cext is in pF
tw is in nanoseconds
terminal
To Rext/Cext
terminal
TIMING COMPONENT CONNECTIONS
FIGURE 2
For maximum noise immunity, system ground should
be applied to the Cext node, even though the Cext
node is already tied to the ground lead internally. Due
to the timing scheme used by the 'LS422 and 'LS423,
a switching diode is not required to prevent reverse
biasing when using electrolytic capacitors.
•
'LS422, 'LS423
TYPICAL OUTPUT PULSE WIDTH
VI
EXTERNAL TIMING CAPACITANCE
100000
Vce 2:.~
TA -
==
ohm,
RT " 2iuik'
RT ".160k. ,hm.
2
I
i=
;'
10000
.....
i
i
,;'
k
"""
1000
dI
J
/'"
RT' SOk oh~~ I
RT= 40k ohm.
RT= 20k ohm.
RT= 10k ohm.
RT= 5kohms
Vi"
100
~
II illl
10
1
10
100
1000
Cext-External Timing C8pacitance-pF
t This value of resistance exceeds the maximum recommended for use over
the full temperature range of the SN54LS circuits.
FIGURE 3
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-945
SN54LS422, SN54LS423, SN74LS422, SN74LS423
RETRIGGERABLE MONOSTABLE MULTlVIBRATORS
TYPICAL APPLICATION DATA FOR 'LS422. 'LS423 t
MUTIPLIER FACTOR
vs
EXTERNAL CAPACITOR
DISTRIBUTION OF UNIT
vs
OUTPUT PULSE WIDTH
...
.,"I
fl
c
(K IS INDEPENDENT OF R)
"
OJ
l!
0.1
§
o
>
g
.~
!
'0
\
0.01
.,c~ ~ -MEDIAN
-20%
"
~
\
OJ
E
l!!
.ll
co
a:
r-
C
FIGURE 4
CD
<
n'
CD
en
.<:
~
4%
3%
ill
-;
D..
2%
~
"
So
1%
"
.=c
0%
:~
-1%
0
'" "
"-
I
-2%
FIGURE 5
VARIATION IN OUTPUT PULSE WIDTH
-
~
6-3%
vs
12"10
10%
~
8%
D..
6%
~
So
"
""-
0
.=c
""'"
I
.g
........
.~
~
co
i'--
I
5.25
4.75
5
Vcc - Supply Voltage - V
FIGURE 6
5.5
>
"'"
4%
2%
0%
-2%
I -4%
/
Vcc= 5 V
Cext = 60 pF
RT = 10 K ohms
:::I
J
l.
VARIATION IN OUTPUT PULSE WIDTH
vs
SUPPLVVOLTAGE
-E
~otek
~ 8% ~ (LS~221
-8%
I
I
a;
.........
0.25 0.30 0.35 0.40 0.45 0.50 0.55
K - Multiplier Factor -
0.0001
See
>
.;:
'" '"
x
cJ
MEDIAN
+ 20% - (LS422)
....,
1\
0.001
I
-I
-I
Vcc= 5 V
TA = 25°C
I'---
g-6%
J -8%
Q)
C
A2
...J
~
~
A3
FUNCTION TABLE
INPUTS
Cs
TRANSFERS BETWEEN BUSES
'LS440
S1 SO GA GB GC
'LS441
'LS442
'LS444
DEVICE
OUTPUT
'LS440
Open-Collector
True
'LS441
Open-Collector
Inverting
3-State
3-State
True/Inverting
H
X
X
X
X
X
None
None
None
'LS442
X
H
H
X
X
X
None
None
None
'LS444
X
X
X
H
H
H
None
None
None
X
L
L
X
H
H
None
None
None
X
L
H
H
X
H
None
None
None
X
H
L
H
H
X
None
None
None
L
L
L
X
L
L
A. B, A· C A· B, A· C A • B, A. C
L
L
H
L
X
L
B· C, B. A B .C,B·A B. C, B. A
L
H
L
L
L
X
C· A, C. B C 'A,C' B
L
L
L
X
L
H
L
L
H
H
X
L
H
L
L
H
C . A,C -
A·B
A·B
A·B
L
B-C
B.C
X
C.A
B·C
C.A
L
L
L
X
H
L
C·A
A.C
L
L
H
L
X
H
B•A
B.A
A·C
B.A
L
H
L
H
L
X
C·B
C.B
C·B
A-C
PRODUCTION DATA documants .ontoin information
current IS of publication data. Products conform to
specifications par the tarms of TaXIS Instruments
=~~:~~i~8ir::I~~i ~=:~:.n :.~a::::::.:~~
not
LOGIC
True
B
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-951
SN54LS440 THRU SN54LS442, SN54LS444
SN1·4LS440 THRU SN14LS442, SN74LS444
QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS
logic symbols t
'LS440
so 1111
81 (121
O}
1
'LS441
0
G3
tThese symbols are in accordance with ANSIIIEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for OW, J, and N packages.
2-952
TEXAS •
INSTRU.MENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS440 THRU SN74LS442, SN54LS444
SN74LS440 THRU SN74LS442, SN74LS444
QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS
logic diagram (composite showing one of four transceivers from each type. positive logic)
cs
r------------------,
GA--T------------+-+~
GB--~-----------+~
GC--+----------~
COMMON
CONTROLS
SO
S1 -+-f~H":)o--,
.....--+--1-.. i
I
A
I
I
II
B
I
I
ONE OF FOUR
'LS440I'LS442
TRANSCEIVERS
I
I
I
I
C
...J
- .,
A
ONE OF FOUR
'LS441
TRANSCEIVERS
B
C
A
ONE OF FOUR
B
'LS444
TRANSCEIVERS
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
7V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Off-state output voltage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range: SN54LS'
., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. _55°C to 125°e
SN74LS'
., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. oOe to 700 e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
NOTE 1; Voltage values are with respect to network ground terminal.
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75266
2-953
SN54LS440. SN54LS441
SN74LS440. SN74LS441
QUAD TRIDIRECTIONAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN74LS440
SN54LS440
SN54LS441
MIN NOM
4.5
Supply voltage, V CC (see Note 1)
SN74LS441
MAX
5.5
5
MIN NOM
4.75
125
-55
Operating free-air temperature. T A
V
5.25
5
5.5
. 12
High-level output voltage, VOH
Low-level output current, IOl
UNIT
MAX
0
5.5
V
24
mA
70
C
NOTE 1: Voltage values are with respect to the network ground terminal.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIH
High-level input voltage
VIL
Low-level input voltage
Input clamp voltage
VCC= MIN,
Hysteresis (VT+ - VT _)!A,B,C input
VCC=MIN
VIK
IOH
VOL
Low-level output voltage
II
maximum input voltage
SN74LS'
TYP* MAX
MIN
TYP* MAX
18mA
VCC= MIN,
VOH - 5.5 V,
VIH=2V,
VCC- MIN,
IOL=12mA
UNIT
V
2
0.6
1.5
V
100
IlA
0.25
0.4
V
0.35
0.5
V
1.5
0.1
0.4
0.2
0.25
0.4
V
V
0.4
100
VIL= VI Lmax
VIH = 2 V,
VIL = VILmax
II
MIN
2
0.5
High-level output current
Input current at
SN54LS'
TEST CONOITIONSt
PARAMETER
I A,B,C input
I All others
VCC=MAX
IOL =24mA
VI-5.5V
0.1
0.1
VI=7 V
0.1
0.1
IIH
High-level input current
VCC= MAX,
IlL
Low-level input current
VCC-MAX,
VI-2.7V
VI 0.4 V
ICC
Supply current
VCC=MAX,
Outputs open
IOutputs low
! Outputs disabled
..
mA
20
20
uA
-0.4
-0.4
mA
62
90
62
90
64
95
64
95
mA
t For conditions shown as MIN or MAX, use the appropnate value speCified under recommended operating conditions.
tAli tvPical values are at Vee"" 5 V. T A
switching characteristics at Vee
PARAMETER
tpLH
tpLH
5 V. RL - 667 n. eL - 45 pF. TA
FROM
(INPUT)
TO
(OUTPUT)
MIN
25°e. see not~ 2
'LS441
TYP
MAX
MIN
TYP
MAX
B
24
35
21
30
C
24
35
21
30
Propagation delay time,
B
A
24
35
21
30
low-to-high level output
B
C
24
35
21
30
C
A
B
24
35
21
24
35
21
30
30
15
Propagation delay time,
high-to-Iow level output
Propagation delay time,
low-to-high level output
high-to-Iow level output
C
A
B
20
30
9
A
C
20
30
9
15
B
A
20
30
9
15
B
C
20
30
9
15
C
A
20
30
9
15
C
B
20
30
9
15
AnyG
A,B,C
29
45
23
35
50,51
A,B,C
33
50
27
40
CS
A,B,C
31
45
26
40
Any G
A,B,C
27
40
20
30
50,51
A,B,C
32
50
26
40
CS
A,B,C
28
45
21
30
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2-954
=
'LS440
A
Propagation delay time,
'tPHL
=
A
,
tpHL
= 25° c.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
n.
n.
n.
n.
SN54LS442, SN54LS444
SN74LS442, SN74LS444
QUAD TRIDIRECTIONAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
recommended operating conditions
Supply voltage, Vee (see Note 11
SN54LS442
SN74LS442
SN54LS444
SN74LS444
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
-15
mA
24
mA
70
°e
-12
High-level output current, IOH
12
Low-level output current, IOl
125
-55
Operating free-air temperature, TA
UNIT
0
NOTE 1: Voltage values are with respect to the network ground terminal.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDITIONSt
PARAMETER
High-level input voltage
Low-level input voltage
VIK
Input clamp voltage
Vee - MIN,
Hysteresis (VT+ - VT _IIA,B,e input
Vee~MIN
VOL
High-level output voltage
Vee
~
MIN.
VIH
~
2 V,
MAX
~
10L~
voltage applied
Vee~
Off-state output current, low-level
CS at 2 V
MAX,
voltage applied
IA,B,e
I
maximum input voltage Others
Vee
~
MAX
IIH
High-level input current
Vee - MAX,
Low-level input current
Vee
~
lOS
Short circuit output current §
Vee
~
I Outputs low
I
Supply current Outputs at Hi~Z
Vee~
MAX,
MAX
Ifill
V
0.5
0.6
-1.5
-1.5
0.1
0.4
0.2
0.4
2.4
3.4
2.4
3.4
2
V
V
V
en
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
~
u
H
::i
«
u
~oz>Iel
U)
CD
(.)
'S;
CD
o
.....I
I:
The SN54LS446 and SN54LS449 are characterized for operation over the full military temperature
range of -55°C to 125°C. The SN74 LS446 and
SN74LS449 are characterized for operation from
oOe to 70°C.
NC· No internal connection
FUNCTION TABLE
ENABLE
DIRECTION
OPERATION
'LS446
GBA
GAB
DIR
H
H
X
X
L
H
A data to B Bus
L
X
L
B data to A
X
H
H
Isolation
H
X
L
Isolation
OPERATION
'LS449
Isolation
Bus
Isolation
A data to B Bus
B data to A Bus
Isolation
Isolation
H'" high level, L;::: low level, X = irrelevant
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply Voltage, VCC (see Note 11
.............................................. . . . . .
7V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
Off-state output voltage
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.5 V
Operating free-air temperature range: SN54LS'
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. _55°C to 125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°Ct070oC
SN74LS'
_65°C to 150°C
Storage temperature range
NOTE 1: Vol taga values are with respect to the network ground terminal.
PRODUCTIOI DATA docum.....ontain information
currant as at publication data. Products canfarm to
specifications par the terms of TaXIs Instrume.ts
=I;·[:~~'li =:~Ii:; r.i-:::::~~~ lot
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75285
2-959
SN54LS446, SN54LS449, SN74LS446, SN74LS449
QUADRUPLE BUS TRANSCEIVERS WITH INDIVIDUAL DIRECTION CONTROLS
logic diagrams (positive logic)
logIc symbols t
'LS446
'LS446
DIR2
GAB
DIR3
DIR 1
(13)
DIR4
A1
A1
(2)
A2
82
A3
83
~
A.
8.
TO OTHER THREE
TRANSCEIVIERS
'LS449
'LS449
-I
-I
r-
C
DIR2
<
DIR3
Q)
1V4
C
2G
2Al
(13) 2V2
(16)
2A3
(lS)
2M
(15) 2V3
(17) 2V4
2A2
(11)
2Vl
(13)
2V2
(15)
2V3
(17)
2V4
(11) 2Vl
(14)
2A4
..J
II-
tThese symbols are in accordance with ANSIIIEEE Std. 91-1984 and lEe Publication 617-12.
Pin numbers shown are for OW, J, and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
Off·state output voltage
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.5 V
Operating free-air temperature range: SN54LS465 thru SN54LS468 . . . . . . . . . . . . . . . . . . . . _55°e to 125°e
SN74LS465 thru SN74LS468 . . . . . . . . . . . . . . . . . . . . . . . oOe to 700 e
Storage temperature range . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. _65°e to 150°C
NOTE 1: Voltage values are with respect to the network ground terminal.
recommended operating conditions
SN54LS'
Supply voltage,
Vee
UNIT
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
-1
4.75
5
5.25
-2.6
mA
24
mA
70
'e
High-level output current, IOH
Low-level output current, IOl
Operating free-air temperature, T A
SN74LS'
MIN
-55
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
..
12
125
0
V
2-965
SN54LS465 THRU SN54LS46B, SN74LS465 THRU SN74LS468
OCTAL BUFFERS WITH 3"STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
1nput clamp voltage
Vee
MIN, VIH
~
2 V,
IOH--1 mA
2V,
10L
10L
MIN
Vee - MAX, VIH - 2 V,
VO~
2.4
Vee
low-level voltage applied
VO~0.4V
~
MAX, VIH
~
VIL
~
V
0.8
V
-1.5
-1.5
V
0.4
24 mA
VIL max,
Vee~MAX,VI~7V
V
3.1
2.4
0.25
VIL - VIL max,
2 V,
UNIT
0.7
2.7 V
Off-state output current,
MAX
3.3
12mA
~
TYP*
2
2.6 mA
10H
Vee MIN, VIH
VIL ~ VIL max
Low-level output voltage
0.25
0.4
0.35
0.5
V
20
20
IlA
-20
-20
/LA
mA
0.1
0.1
High~level
input current
Vee
2.7 V
20
20
IlA
IlL
Low~level
input current
Vee - MAX, VI- 0.4 V
lOS
Short·circuit output current§
-0.2
-130
-0.2
-130
mA
mA
input voltage
-I
-I
~
MAX, VI
~
-30
Vee-MAX,VO-OV
Outputs low
'LS465,
r-
'LS467
lee
Supply current
Vee" MAX
'LS466,
CD
<
(/)
SN74LS'
MAX
IIH
II
n"
CD
~
VIL"" VIL max
Input current at maximum
C
TYP*
Vee~MIN, 11~-18mA
Off-state output current,
IOZH high-level voltage applied
10ZL
MIN
2
VOH High-level output voltage
VOL
SN54lS'
TEST CONDITIONSt
'LS468
-30
Outputs high
Output Hi·Z
19
13
32
22
19
13
32
22
22
37
22
37
Outputs low
14
23
14
23
Outputs high
Ou"tputs Hi~Z
6
10
6
10
17
28
17
28
mA
t For conditions shown as MI N or MAX. use the appropriate value specified under recommended operating conditions.
:j: All typical values are at Vee::: 5 V. T A"" 25°C.
§ Not more than one output should be shorted at a time, and duration of the short·circuit should not exceed one second.
switching characteristics, Vee = 5 V, T A = 25°e, see note 2
FROM
TO
!INPUT)
(OUTPUTI
tPLH
Ai
Yi
tpHL
Ai
Yi
tPZH
G
j
Y
tpZL
G
j
Y
tpHZ
G t
Y
tPLZ
G t
Y
PARAMETER
TEST CONDITIONS
RL" 66Hl, eL
RL"667!l,
~
'LS465, 'LS467
MIN
45 pF
eL~5pF
MAX
TYP
MAX
9
15
7
12
12
18
9
15
25
40
25
40
29
45
29
45
MIN
llNIT
ns
ns
25
40
25
40
ns
ns
ns
30
45
30
45
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1,
2-966
'LS466, 'LS468
TYP
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS490, SN74LS490
DUAL 4·81T DECADE COUNTERS
OCTOBER 1976 - REVISED MARCH 1988
SN54LS490 ... J OR W PACKAGE
SN74LS490 ... 0, J OR N PACKAGE
(TOP VIEW)
•
Dual Versions of Popular SN54LS90 and
SN74LS90 Counters
•
Individual Clock. Direct Clear. and Set-to-9
Inputs for Each Decade Counter
•
Dual Counters Can Significantly Improve
System Densities as Package Count Can Be
Reduced by 50%
•
ICLK
ICLR
lOA
ISET9
20A
2SET9
lOB
IOC
Maximum Count Frequency ... 35 MHz
Typical
20B
20C
10 0
GNO
Buffered Outputs Reduce Possibility of
Collector Commutation
•
VCC
2CLK
2CLR
description
20 0
SN54LS490 ... FK PACKAGE
(TOP VIEW)
Each of these monolithic circuits contains eight masterslave flip-flops and additional gating to implement two
individual4-bit decade counters in a single package. Each
decade counter has individual clock, clear, and set-to-9
inputs. BCO count sequences of any length up to divideby-l00 may be implemented with a single 'LS490.
4
2CLR
5
20A
NC
Buffering on each output is provided to ensure that
lOA
lSET9
susceptibility to collector commutation is reduced
significantly. All inputs are diode·clamped to reduce the
effects of line ringing. The counters have parallel outputs
NC
6
lOB
10C
7
8
from each counter stage so that submultiples of the input
count frequency are available for system timing signals.
20B
00 U
0
-C)
NN
U
02200
The SN54LS490 is characterized for operation over the
full military temperature range of - 55°C to 125°C; the
SN74LS490 is characterized for use in industrial systems
operating from O°C to 70°C.
2SET9
NC - No internal connection
logic symbol t
CTRDIV10
lCLR (21
CT=O
ISET9 (41
CT=9
BCD COUNT SEQUENCE
cr{
(31
(51
(61
(71
lOA
lOa
IDe
lao
lEACH COUNTER)
(131
OUTPUT
COUNT
Qo Qc QB QA
0
L
L
L
L
1
L
L
L
H
2
L
L
H
L
L
H
4
L
H
L
H
L
5
L
H
L
H
6
L
H
H
L
7
L
H
H
H
8
H
L
L
L
9
H
L
L
H
2CLR
FUNCTION TABLE
2SET9
(EACH COUNTER)
2CLK
INPUTS
L
3
CLEARISET·TO·9
OUTPUTS
CLEAR SET·TO·9 QA QB QC Qo
H
L
L
L
L
L
L
H
L
H
L
H = high level,
L
PRODUCTION DATA documants contain information
currant I. of publication data. Products conform to
specifications per the terms of Texas Instruments
::=:~~i~8r::I~li ~:~ti:r lI~D:=::::':~~s
L
L
COUNT
not
H
(111
(101
(91
20A
20a
20c
20 0
TThis symbol is in accordance with ANSI/IEEE Std. 91·1984 and
lEG Publication 617·12.
Pin numbers shown are for D. J, N. and W packages.
= low level
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-967
SN54LS490, SN74LS490
DUAL 4"81T DECADE COUNTERS
schematics of inputs and outputs
EQUIVALENT OF EACH
CLOCK INPUT
EQUIVALENT OF EACH
CLEAR AND SET·TO·NINE INPUT
TYPICAL OF ALL OUTPUTS
Vce
120!1 NOM
Vec----....- -
VCC------.-----
18 k!1 NOM
INPUT
INPUT ...~...-
-t
-t
r
...-
OUTPUT
logic diagram (each counter)
C
(4,12)
SET·TO-9.;..;.--'---{;>c......- - -....- - - - - - - - . ,
CD
<
n"
CD
VI
S
(3,13) OUTPUT
(1,15)
QA
CLOCK~--------~---~~T
R
(5, 11) OUTPUT
QB
(6, 10) OUTPUT
QC
T
S
T
R
(2,14)
CLEAR--'-~~I;.>------~-------"
Pin numbers shown are for 0, J, N, and W packages.
2-968
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
(7, g)
OUTPUT
QO
SN54LS490. SN14LS490
DUAL 4-BIT DECADE COUNTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
. 7V
. 7V
5.5V
_55°C to 125°C
O°C to 70°C
-65°C to 150°C
Supply voltage, VCC (see Note 1)
Clear and set-to-9 input voltage
Clock input voltage . . . . . .
Operating free-air temperature range: SN54LS490
SN74LS490
Storage temperature range
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS490
MIN
Supply voltage, Vee
NOM
4.5
5
High-level output current, IOH
SN74LS490
MAX
MIN
NOM
5.5
4.75
5
-400
MAX
5.25
-400
4
Low-level output current, tOl
0
Count frequency. fcount
25
0
UNIT
V
jlA
8
rnA
25
MHz
Pulse width, tw (any input)
20
20
Clear or 5et-t0-9 inactive-state setup time, tsu
251
251
n,
n,
0
°e
Operating free-air temperature, T A
~ The
-55
125
70
fIl
Q)
o
>
Q)
arrow indicates that the falling edge of the clock pulse is used for reference.
c
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONSt
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
LOW-level output voltage
MIN
Vee = MIN,
11= -18mA
Vee = MIN,
VIH - 2 V,
2.5
VIL = VILmax
Clear,
maximum input voltage ~
Vee=MAX,
elock
IOL=4mA
High-level input current set-to-9 Vee =MAX,
-elock
Low-level input current
TVP*
MAX
0.25
V
-1.5
-1.5
V
0.4
~
Vee = MAX,
V
3.4
0.25
0.4
0.35
0.5
V
10L =8rnA
VI =7 V
0.1
0.1
VI = 5.5 V
0.2
0.2
20
20
100
100
VI = 2.7 V
VI=O.4V
elock
los
Short-circuit output current§
Vee = MAX
lee
Supply current
Vee - MAX,
lI-
V
0.8
2.7
-'
UNIT
0.7
3.4
Clear,
IlL
MIN
2
Clear,
IIH
MAX
VIH = 2 V,
VIL = VILmax
Input current at
TVPt
SN74LS490
2
Vee - MIN,
II
SN54LS490
-0.4
-1.6
-100
-20
See Note 2
-0.4
-1.6
15
26
-20
15
mA
jlA
mA
-100
mA
26
rnA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
~:AII typical values are at Vee"" 5 V, T A "'- 25"C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with all outputs open, both clear inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-969
SN54LS490, SN74tS490
DUAL 4-81T DECADE COUNTERS
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETERt
FROM
TO
(INPUT I
(OUTPUT!
Clock
QA
f max
tpLH
Clock
QA
Clock
QS.QO
tpHL
tPLH
tpHL
tpLH
Clock
tpHL
Clear
tpHL
tPLH
Set-to-9
tpHL
TEST CONDITIONS
CL
~
ISpF.
RL= 2 kn
See Figure 2 and Note 3
QC
TVP
25
35
MAX
20
13
20
24
39
26
39
32
54
36
54
Any
24
39
24
39
Q8. QC
20
36
tpLH = Propagation delay time, low~to·high·level output
tpHL = Propagation delay time. high-to-low-Ievel output
NOTe 3: Load circuits and voltage waveforms are shown in Section 1.
-f
-f
rC
(1)
~-
(')
(1)
en
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
UNIT
MHz
12
QA.QO
tfmax = maximum count frequency
2-970
MIN
ns
ns
ns
ns
ns
SET·TO·9
INPUT
J1.3V
' I
14
CLEAR
INPUT
i
_..;.-_ _ _---i
'\
.
1 3V
1
~
:
1
I
z
~
OUTPUTOA
LJ
1.3V
~ tpHL
1
I
--1----.1
OUTPUTOD
~~
I
I
\ 1.3 V
I
~tPHL
I
I
OUTPUTOC
I
',I
' \ 1.3V
1
1
-+"\ 1.3V
1
~
1I
~~J
I4---+t-
r
t
tpLH-Measure
at tn+l
1.3V
tpHL
1
~tPLH
I
attn+2
tpHL
+\
1.3V
I
~ tpHL
I
1
ottn+4
3V
\!.
I
1
1.3V
:
r.
'-Sf
I
I_
1
1.3 V
pi f
1I
I ff------....:....---J
I
I
tpHL -Measure
at tn+2
tPLH-Measur.--"--"
1
I
I
1
OV
0V
-;.---+t
I1
H
~
~
:
tpLH-Measure
\:;-
1
1
f
\-\ 1.3V
I
I
11
I
•
-,-,
I
OUTPUT 0B
Irl- - - - - - - .. 'w(clock) ~
-+t
--{-'I
+
__ 1_
I
/
~ tpHL
:
IS
I
'su
I
I
I
~r;;i
~~
1
: y
~;--!--------------------3V
I
~ tpLH
OV
--J
1
I
SrS- - - - - - - -
SS
tsu
I
CLOCK
INPUT
3V
'\:;:-3;------------- - - -
1.3 V
I
I1
rI
~
-
I
OH
V
OL
tpHL -Measure
__
~'
1.3 V
~:;~+4
V
1
OL
I4-----*- tpLH-Meosureattn+8
I
I - - VOH
I
~
1.3V
I
tpHL -Measure at tn+8 ~
V
I4---+t-
c
VOL
tpHL -Measure at tn+10
\!..1.3vr~I---VOH
\
f
11.3V
~
1.3V
1.3V
~---------~II
VOL
c
....
:I>
'f"en
ICIIlIz
:::::jut
01:0
C ....
men
nol:O
:I>
VOL TAGE WAVEFORMS
NOTES: A. Input pulses are supplied by a generator having the following characteristics: tr ,,; 15 ns. tf ,,; 6 ns. PRR ,,; 1 MHz. duty
cycle
=
50%. Zout
~
50 ohms.
CD
C CI
m"
n en
c ....
zj!!:
-ten
mol:O
:::a CD
en CI
Cl 2
FIGURE 2
N
cO
-..J
TTL Devices
II
2-972
SN54LS54t SN54LS541, SN74LS540, SN74LS541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3·STATE OUTPUTS
02546, AUGUST 1979-REVISED MARCH 1988
• 3·State Outputs Drive Bus Lines or
Buffer Memory Address Registers
SN54LS540, SN54LS541 , , . J OR W PACKAGE
SN74LS540, SN74LS541 ... OW OR N PACKAGE
(TOP VIEW)
• P-N-P Inputs Reduce D-C Loading
• Hysteresis at Inputs Improves Noise Margins
• Data Flow-thru Pinout (All Inputs on
Opposite Side from Outputs)
Vee
G2
Yl
Y2
Y3
Y4
Y5
Y6
Y7
YB
Gl
Al
A2
A3
A4
A5
A6
A7
AB
GND
descri ption
These octal buffers and line drivers are designed to
have the performance of the popular SN54LS240/
SN74LS240 series and, at the same time, offer a
pinout having the inputs and outputs on opposite
sides of the package. This arrangement greatly enhances printed circuit board layout.
SN54LS540, SN54LS541 , , , FK PACKAGE
The three-state control gate is a 2-input NOR such
that if either G1 or G2 are high, all eight outputs are
in the high-impedance state,
(TOP VIEW)
U
~ :;(I(!; ~I(:l
II)
2
The 'LS540 offers inverting data and the 'LS541
offers true data at the outputs.
A3
A4
A5
A6
A7
The SN54LS540 and SN54LS541 are characterized
for operation over the full military temperature range
of _55°e to 125°e. The SN74LS540 and SN74LS541
are characterized for operation from oOe to 70 o e,
1 2019
Q)
to)
::Q)
o
6
....J
lI-
9 10 11 1213
~~~>=~
(,!)
lYJ'ICAL POWER
DISSIPATION
(ENABLED)
'LS541
'LS540
RATED
RATED
IOL
(SINK
CURRENT)
IOH
(SOURCE
CURRENT)
SN54LS'
12mA
-12mA
92.5 mW
120 mW
SN74LS'
24 mA
-15mA
92.5 mW
120mW
TYPE
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
----<....-VCC
50 !1
NOM
VCC - - -....- - - - - -
Req
INPUT
OUTPUT
Enable Inputs: Req =
9
All Other Inputs: Req = 10
kn NOM
kn NOM
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~a{::1~1e ~!:~:~ti:r ~IO::::~:t:~~S not
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-973
SN54LS540, SN54LS541, SN74LS540, SN74LS541
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
logic symbols t
'LS540
'LS541
A1 121
A1 121
A2 131
A2 131
1111 V2
A3 141
A3 141
1161 V3
A4 lSI
A4 lSI
1151 V4
AS 161
A5 161
1141 V5
A6 17l
A6 17l
1131 V6
A7 181
AS 191
A7 181
AS 191
1121 V7
(11)
va
11"1 V1
1111 V8
t These symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
logic diagram (positive logic)
'LS541
'LS540
I
~-----
A2~
~-----
A3~
~-----
I
--I
~Y2
~-----
I
--I
A2~
~Y2
f..----- -,
A3~
~Y3
f..----- -,
A4~
~Y4
-1
~Y3
--I
A4~
~Y4
~------,
r------,~Y5
A5~
~Y5
A5~
A6~
~Y6
A6!ZL..j
~Y6
~Y7
A7!!!L..t
r-Jill Y7
A8~'- _ _ _ _ _ J~Y8
A8~L
~----- -~
~------~
r-------1
~------i
A7~
1------ -~
1------ --I
_____
Jt----l!-!lY8
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) " " , ....................................................... , .. 7 V
Input voltage ............................................................................... 7 V
Operating free·air temperature range: SN54LS540, SN54LS541 ............................. - 55°e to 125°e
SN74LS540, SN74LS541 ................................. oOeto 700 e
Storage temperature range ........................................................... - 65°e to 1500 e
NOTE1: Voltage values are with respect to the network ground terminal.
2-974
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 ,. DALLAS. TEXAS 75265
SN54LS540. SN54LS541. SN74LS540. SN74LS541
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
recommended operating conditions
SN54LS'
PARAMETER
Supply voltage, Vee Isee Note 11
MIN
NOM
4.5
5
SN74LS'
MIN
NOM
MAX
5.5
4.75
5
5.25
V
-15
rnA
24
rnA
70
°e
-12
High-level output current. IOH
Low-level output current, IOL
12
-55
Operating free-air temperature, T A
UNIT
MAX
125
0
NOTE 1: Voltage values are with respect to network ground terminal.
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONSt
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
Vee = MIN,
Hysteresis IVT + - VT-I
Vee = MIN
VOL
High-level output voltage
Low-level output voltage
Off-state output current.
10ZH
high-level voltage applied
Off-state output current,
10Zl
low-level voltage applied
Input current at maximum
II
input voltage
Vee = MIN,
VIH = 2V,
VIL = 0.5 V,
10H = MAX
Vee = MIN,
10L = 12 rnA
MIN
TYP*
MAX
V
0.6
V
-1.5
-1.5
V
0.2
0.4
0.2
0.4
2.4
3.4
2.4
3.4
V
(/l
V
2
2
0.25
0.4
0.4
0.35
0.5
Q)
V
Vil = Vil max
Vee = MAX,
Va = 2.7 V
20
20
VIL = Vil max
Va = 0.4 V
-20
-20
Vee = MAX,
VI =7V
0.1
0.1
20
20
~A
-0.2
-0.2
rnA
-225
rnA
Low-level input current
Vee = MAX,
lOS
Short-circuit output current §
Vee = MAX
-40
'lS540
Outputs high
-225
13
25
-40
13
C
...J
~A
VIH = 2 V,
VI = 2.7 V
VI = 0.4 V
Q)
(,)
'S
0.25
10L = 24 rnA
IIH
lI-
rnA
25
'lS541
18
32
18
32
Vee = MAX,
'LS540
24
45
24
45
Outputs open
'lS541
30
52
30
52
All outputs
'lS540
30
52
30
52
disabled
'lS541
32
55
32
55
Outputs low
UNIT
0.6
VIH = 2 V,
III
Supply current
SN74LS'
MAX
2
11= -18 rnA
VIH = 2 V,
VIL = VIL max, 10H = -3 rnA
High-level input current, any input Vee = MAX,
lee
TYP*
2
Vee = MIN,
VOH
SN54LS'
MIN
rnA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
'All typical values are at Vee = 5 V, TA = 25°e.
§Not more than one output should be shorted at a time, and duration of the short·circuit should not exceed one second.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-975
SN54LS540, SN54LS541, SN74LS540, SN74LS541
OCTAL BUFFERS AND LINE DRIVERS WITH 3·STATE OUTPUTS
switching characteristics.
vee" 5 V.
PARAMETER
tpLH
tpHL
TA -
25°e
TEST CONDITIONS
'LS540
MIN
MAX
9
9
Propagation delay time,
low-to-high-Ievel output
Propagation delay time,
high-to-Iow-Ievel output
CL = 45 pF,
See Note 2
RL
=
6670,
Output enable time to low level
Output enable time to high level
tPZL
tpZH
tpLZ
Output disable time from low level
CL
tpHZ
Output disable time from high level
See Note 2
=
5 pF,
RL
MIN
UNIT
TYP
MAX
15
9
15
ns
15
10
18
ns
25
38
25
38
ns
15
25
20
32
ns
10
18
10
18
ns
15
25
18
29
ns
= 6670,
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
-t
-t
r-
C
CD
<
n'
CD
fI)
2·976
'LS541
TYP
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 ,. DALLAS. TEXAS 75265
SN54LS590, SN54LS591, SN74LS590, SN74LS591
8·BIT BINARY COUNTERS WITH OUTPUT REGISTERS
02632, JANUARY 1981 -
•
MARCH 1988
SN54LS590, SN54LS591 ... J OR W PACKAGE
SN74LS590, SN74LS591 ... N PACKAGE
(TOPVIEWI
B-Bit Counter with Register
•
Parallel Register Outputs
•
Choice of 3·State ,'LS5901 or Open·
Collector ,'LS5911 Register Outputs
•
Guaranteed Counter Frequency:
DC to 20 MHz
QB
QC
QO
QE
QF
QG
QH
description
These devices each contain an 8-bit binary counter that
feeds an 8-bit storage register. The storage register has
parallel outputs. Separate clocks are provided for both
the binary counter and storage register. The binary
counter features a direct clear input CCLR and a count
enable input CCKEN. For cascading, a ripple carry output RCO is provided. Expansion is easily accomplished
for two stages by connecting RCO of the first stage to
CCKEN of the second stage. Cascading for larger count
chains can be accomplished by connecting RCO of each
stage to CCK of the following stage.
VCC
QA
G
RCK
CCi
0
1 2019
CI)
Q)
(.)
Both the counter and register clocks are positive-edge
triggered. If the user wishes to connect both clocks
together, the counter state will always be one count
ahead of the register. (nternal circuitry prevents clocking from the clock enable.
'>
Q)
C
9 10111213
..J
~
:x: 0 UIO\a::
OZZU-'
(!l
a::tl
NC - No internal connection
schematics of inputs and outputs
EQUIVALENT OF CCK INPUT
EQUIVALENT OF ALL OTHER INPUTS
RCOOUTPUT
VCC
Req
VCC1B
INPUT
_.
OUTPUT
RCK: Req = 10 kG NOM
ALL OTHER: Req - 13 kG NOM
TYPICAL OF Q OUTPUTS ('LS5901
TYPICAL OF Q OUTPUTS ('LS5911
VCC
___ ~OUTPUT
OUTPUT
PRODUCTION DATA d_m..l......i. i.f.,mlli••
.urnnt I I .f publi••tion d.... P'....cb ••nfarm Ia
.....ili..I1... 1M' th. lar....f T.... I••trum....
....
=ri~.i~:I':.'l.i =:~i:; :.\.;:~~:.:~
1
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-977
SN54LS590. SN54LS591. SN74LS590. SN74LS591
8·81T BINARY COUNTERS WITH OUTPUT REGISTERS
logic diagram (positive logic)
1141
RCK
CCK
1131
~
-
I
F""i
(111
(101
.....
Lrl rtI:J
~~
~ T~
~ ...llL
~~
Lfl r
Lfl -t:r
~ .J!L
~~
i>= t-!!L
I
1S
.r.::-L.
-f
-f
r0-
C
CD
<
n'
CD
(I)
1S
r,;;-L
~.
15
T
1
I
ct>= ...!J!L
~
ct>= ~
18
Lfl fJ
Lfl -t:r
>]
15
(S= ~
18
.Lfl r ~
Lfl +-Cl
r-"'1"
18
r,;-'L
15
Pin numbers shown are for J, Nand W
packag~s.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
1
~ ...ill..
r;R"1-
2-978
»- ...!!!..
~
>]
(71
OE
SN54LS590, SN54LS591, SN14LS590, SN14LS591
8·BIT BINARY COUNTERS WITH OUTPUT REGISTERS
logic symbols t
'LS591
'LS590
CTR8
CCT· 2551 Z4
(151 0
(II 0:
C21
Oc
C31
OD
C41
Oe
C51
OF
C.I OG
C7I
(l51 0A
(1 10a
C21' Dc
C31 OD
C41 Oe
~-------------t------i_C51 OF
COI OG
C7IOH
OH
tThese symbols are in accordance with ANSIIIEEE Std. 91·1984 and IEC Publication 617-12.
Pin numbers shown are for J, N, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
I/)
Supply voltage, Vee (see Note 1) ........ " ................................................. , ... 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Off·state output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range: SN54LS590, SN54LS591 ............................ - 55°C to 125°C
SN74LS590, SN74LS591 ................................ oOe to 70°C
Storage temperature range ................. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to 150°C
Q)
CJ
'S;
Q)
C
....J
lI-
NOTE1: Voltage values are with respect to the network ground terminal.
recommended operating conditions
SN54LS'
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
lOH
High-level output current
SN74LS'
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.8
V
V
2
V
2
0.7
Q. 'LS591 only
5.5
5.5
RCO
-1
-1
Q, 'LS590 only
-1
-2.6
8
16
12
24
RCa
mA
lOL
Low-level output current
ICCK
Counter clock frequency
0
20
0
20
MHz
IRCK
Register clock frequency
0
25
0
25
MHz
twICCK)
Duration of CQunter clock pulse
25
25
ns
twICCLR)
Duration of counter clear pulse
20
20
ns
twIRCK)
Duration of register clock pulse
20
20
ns
20
20
Q
CCKEN low belore CCK'
tsu
Setup time
CCLR inactive before CCK f
CCK before RCK'
th
Hold time
TA
Operating free-air temperature
(see Note 2)
CCKEN low alter CCK'
20
20
40
40
0
- 55
ns
ns
0
125
0
mA
70
°C
NOTE 2: This setup time ensures the register will see stable data from the counter outputs. The clocks may be tied together in which case the
register state will be one clock pulse behind the counter.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-979
SN54LS590. SN54LS591. SN74LS590. SN74LS591
8·BIT BINARY COUNTERS WITH OUTPUT REGISTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Vce- MIN,
VIK
'LS590 Q
Vee= MIN,
VOH
Vce- MIN,
'LS591 Q
I
I
VIH = 2V,
VCC- MAX,
'lS590 Q
Vee - MAX,
II
eCK
All others
'lS590 Q
RCtl
'LS591
2.4
3.2
VIH - 2 V,
TYPt MAX
-1.5
VIH=2V,
IOl=24mA
2.4
3.1
2.4
3.2
0.1
0.25
0.25
IOl=8mA
VIH - 2 V,
VIL = MAX,
VIH=2V,
Vil = MAX,
Vo = 0.4 V
IIH
ICC
3.2
VO= 2.7 V
'LS590 Q
'lS590
MIN
0.4
0.4
~
~
leez
lecH
~
VI = 7 V
Vce- MAX,
VI-2.7V
Vee= MAX,
VI=O.4V
Vce= MAX,
VO=OV
UNIT
V
V
0.1
IOl- 16 mA
Vee- MAX,
IOS§
2.4
IOH - - 2.6 mA
1 mA
IOH VOH = 5.5 V,
Vil = MAX
RCO
IlL
IOH- -1 mA
IOL-12mA
Vee= MIN,
SN74LS'
MAX
-1.5
Q
IOZl
TYP*
VIL = MAX
VOL
IOZH
MIN
11=-18mA
VIL = MAX
RC5
IOH
SN54LS'
TEST eONDITIONSt
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
mA
V
20
20
- 20
-20
IlA
0.1
0.1
mA
20
20
0.8
0.8
- 0.2
- 0.2
-30
-130
- 30
-130
-20
-100
- 20
-100
33
55
33
55
Vec= MAX,
All possible inputs grounded,
44
65
44
65
46
65
46
65
All outputs open
35
55
35
55
42
65
42
65
IlA
IlA
mA
mA
mA
t For conditions shown as MI N or MAX. use the appropriate value specified under recommended operating conditions.
i All typical values are at Vee = 5 V, T A = 25°C
§ Not more than one output should be shorted at a time and
the duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5 V. TA = 25°e (see note 3)
FROM
TO
(INPUT)
(OUTPUT)
f max
ReK
Q
RL - 667
tPLH
CCKf
tPHL
eeKf
RC5
ReO
RL=lkn,
tPLH
CCLRI
tPLH
RCKt
tPHL
RCKt
Q
tpZH
GI
Q
tpZL
GI
Q
tPHZ
~f
Q
PARAMETER
TEST CONDITIONS
n,
CL - 45 pF
'LS590
MIN
TYP
20
35
MIN
TYP
20
35
MAX
22
16
24
20
30
25
38
RCO
30
45
32
48
Q
12
18
25
38
22
33
28
42
25
38
34
50
32
48
tPLZ
Gf
Q
tPLH
Gf
Q
tPHL
ITI
Q
RL = 667 n,
CL = 45 pF
RL = 667 n,
CL = 5 pF
RL=667n,
CL = 45 pF
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
30
45
20
30
25
38
UNIT
MHz
14
CL = 30pF
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-980
'LS591
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SN54LS592, SN54LS593, SN74LS592, SN74LS593
8·BIT BINARY COUNTERS WITH INPUT REGISTERS
02633, JANUARY 1981 - REVISED MARCH 1988
SN54LS592 . , . J OR W PACKAGE
SN74LS592 ... N PACKAGE
• Parallel Register Inputs ('LS592)
• Parallel 3·State 1/0: Register Inputsl
Counter Outputs ('LS593)
(TOP VIEWI
vcc
B
C
• Counter has Direct Overriding Load and
Clear
• Accurate Counter Frequency:
DC to 20 MHz
A
CLOAO
RCK
CCKEN
CCK
CClR
RCa
G
H
GNO
description
The 'LS592 comes in a 16-pin package and consists of a
parallel input, 8-bit storage register feeding an 8-bit binary
counter, Both the register and the counter have individual
positive-edge-triggered clocks. In addition, the counter has
direct load and clear functions. A low-going RCa pulse will be
obtained when the counter reaches the hex word FF. Expansion is easily accomplished for two stages by connecting RCa
of the first stage to CCKEN of the second stage. Cascading
for larger count chains can be accomplished by connecting
RCa of each stage to CCK of the following stage.
The 'LS593 comes in a 20-pin package and has all the
features of the 'LS592 plus 3-state 1/0, which provides
parallel counter outputs. The tables below show the operation
of the enable (CCKEN, CCKENI inputs. A register clock
enable (RCKENI is also provided.
SN54LS592 . , . FK PACKAGE
(TOP VIEWI
3212019
o
4
5
E
NC
F
6
7
G
8
14
910111213
:J: z
C
C)
NC -
UIQI'
"
a:tl
Z
u
....J
No internal connection
SN54LS693 ... J OR W PACKAGE
SN74LS593 ... OW OR N PACKAGE
(TOPVIEWI
VCC
OUTPUT ENABLE CONTROL ('593 ONLYI
G
G
L
L
input mode
L
H
input mode
H
L
output mode
H
G
G
RCiffii
A/QA thru H/QH
H
RCK
CCKEN
CCKEN
H/QH
CLOAO
input mode
CCK
CClR
RCa
9
GNO
COUNTER CLOCK ENABLE CONTROL
CCKEN
CCiffiii
EFFECT ON CCK
L
L
Enable
SN54LS593 . , . FK PACKAGE
(TOP VIEWI
U0
"0
"
0
iii
u
< ~<:J
L
H
Disable
<:J
H
L
Enable
3212019
H
H
Enable
9 1011 1213
PRODUCTIOM DATA d••um••tl ....l8i. i.f.rmlti••
currant .s at publication dati. Proda. canfarm to
spacificltionl per the tlnns of TI••• Instruments
:~~=~i;·i~:I~~i ~=::i:;
:.r:.-:::.::.-
not
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
2-981
SN54LS592. SN54LS593. SN74LS592. SN74LS593
B-BIT BINARY COUNTERS WITH INPUT REGISTERS
schematics of inputs and outputs
EQUIVALENT OF A THRU H INPUTS
EQUIVALENT OF 'LS592 CCK INPUT AND
'LS593 CCK AND RCK INPUTS
EQUIVALENT OF ALL OTHER INPUTS
vee~
Req
Vce-~-
25kO NOM
INPUT
••
I NPUT -flot+-~
'LS592 ReK: Req
ALL OTHER: Req
=
=
10 kn NOM
13 kn NOM
TYPICAL OF Q OUTPUTS ('LS5Q3)
RCOOUTPUT
Vee
Vee
OUTPUT
-I
-I
OUTPUT
r
C
CD
<
0CD
logic symbols t
CII
'LS593
'LS592
eClR
~
CCK
CLOAD
RCK
A
B
(2)
C
(3)
D
E
F
G
H
(4)
(5)
(6)
(7)
tThese symbols are in accordance with ANSIIIEEE Std. 91-1984 and lEe Publication 617-12.
Pin numbers shown are for OW, J, N, and W packages.
2-982
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS592, SN74LS592
8-BIT BINARY COUNTERS WITH INPUT REGISTERS
logic diagram (positive logic)
CCLR
1121
CCK
CLOAO
RCK
A
'LS592
1101
1111
1141
~
- - :=[J
1151
'--'"
-
III
~}"
--- H) 0
~
~
10
131
10
---
R
.-5
~j
10
-
R
r--
r--
_ ~~T
:=J "'f -
(6)
10
>-oP.Cl
1-->-
r--
~S
»~~T
r-.!!...-
D
Cl
5
L P.T
~
-........f ~L-
~ >Cl
10
R
.--
G
t=[>- :D:T:~.
>Cl
L-c t>
l~T
U' R..>
._"'-
:> Cl
10
~
171
~
--:=[J 0
141
H
C~T
-r-
~
G
...--
t:::J'-
10
121
lSI
S
~
~f>T
]}- :L>
R
>Cl
~t>Cl
___ b-
o
r---
10
~ t>Cl
C
~
RCO
1131
~
B
(9)
I
J
r--
lS
M
M
M
M
1
1
-1
VI
Q)
(.)
-S;
Q)
o
...J
lI-
f=
~
~
~
=
=
1
~
~T
~t:D- .!!-t---
Pin numbers shown are for J, N, and W packages.
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-983
SN54LS593. SN74LS593
8·BIT BINARY COUNTERS WITH INPUT REGISTERS
logic diagram (positive logic)
'LS593
G (191
G
CCLR
CCKEN
CCKEN
CCK
CLOAD
(1BI
t
(12).
~
114)
(131
~~
(91
Gating for RCK
is similar in detail
to that shown for
;-:;=r
iiCKEiii
RCK
AlaA
(171
G2
(16)
(11
-
2
CCK.
.-
BIas 121
1:-
n°
C/Oc
CD
(31
til
1:-
I'.......f ~R
~
~
I)-
DiaD
-
l:-~
w-->
L;:-~
1 lD
~
..-..c >Cl
~
.......f
l;:-~
lD
1 lD
~
-
E/ae
-
(6)
1
~
lD
..-..c I>Cl
-
G/OQ
(7)
1
~
"-
>Cl
-
(B)
H/Oti
__ l;:-~
--
~;:-~
~
.......f ~
.!L-
1:- D ~ ~;:-~
-r)-
--<: >Cl
~.l!..-
Pin numbers shown are for OW J and N acka9 es.
2-984
~.!L-
~
.......f ~.>--cL~
lD
~L-
~
.......f ~R
..-..c f>Cl
(51
~l~~
I}-
1
..-..c >Cl
(4)
C
~;:-~
~
~
~ f>Cl
C
CD
<
RCO
:>-
~ f>Cl
-I
-I
(11)
.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
M
M
M
~
t::
~
1
~~
=
=
J
SN54LS592, SN54LS593, SN74LS592, SN74LS593
8·BIT BINARY COUNTERS WITH INPUT REGISTERS
typical operating sequences
'LS592
CCK
CCKEN
r 1. . _____
RCK
--Ill...-____________
A THRU H
'NPUT HEX
FCX/lllTIIlI/Ollr!2~·\WEVJ///l/lmU/
~
RCO
'LS593
G
G _ _ _ _---I
CCLR
CLOAO
-.J
---------r--------,L-j
CCK
CCKEN ----------r-------------r-------------~
CCKEN _________
_____________________ _ J
~
RCK
------4---~r-l~_+---------------------------
RCKEN ---------~--'L_Jr----~-------------------------------------
I
A/QA THRU H/QH
_ _ _ _-J)---<'INPUTHEXFC>----tC
OUTPUT HEX
Fe
,.--,O",UT.!!:PU"-,T-"H",,EX,--~ OUTPUT HEX OUTPUT HEX OUTPUT HEX
~
X
RCO --------~r-----------~r-----------------------_,
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·985
SN54LS592, SN5.4LS593, SN74LS592, SN74LS593
8-BIT BINARY COUNTERS WITH INPUT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage (excluding I/O ports) .............................................................. 7 V
Off-state output voltage (including I/O ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54LS592, SN54LS593 .... . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
SN74LS592, SN74LS593 ................................ oOe to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
NOTE1: Voltage values are with respect to the network ground terminal.
recommended operating conditions
SN54LS'
....
-t
....
C
CD
~.
VCC
Supply voltage
VIH
High·level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
fCCK
Counter clock frequency
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
2
0.8
RCO
-1
-1
Q 'LS593 only
-1
- 2.6
RCO
0
8
16
12
24
20
0
V
V
0.7
Q •LS593 only
UNIT
20
V
mA
mA
MHz
twICCK)
Duration of counter clock pulse
25
25
ns
tw ICCLR)
Duration of counter clear pulse
20
20
ns
twIRCK)
Duration of register clock pulse
20
20
ns
40
40
ns
RCKEN low to RCK , , 'LS593
20
20
ns
CCKEN low, 'LS592
30
30
30
30
n
tw (CLOAO) Duration of counter load pulse
C/I
tsu
CD
SN74LS'
MIN
Register enable setup time
Counter enable setup time
tsu
tsu
before CCK t
Setup time
th
Hold time
TA
Operating free-air temperature
CCKEN lowor
CCKEN high, 'LS593
CCLR inactive before CCK t
20
20
CLOAD inactive before CCK ,
20
20
RCK , before CLOAD t Isee Note 2)
30
30
Data A thru H before RCK t
20
20
Data A thru H after RCK t
0
0
All others
0
0
- 55
NOTE 2: This time insures the data saved by RCK
2-986
t
will also be loaded into the counter.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS,' TEXAS 75265
125
0
ns
ns
ns
70
°c
SN54LS592, SN54LS593, SN74LS592, SN74LS593
8-BIT BINARY COUNTERS WITH INPUT REGISTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
'LS593 Q
VOH
Vcc = MIN,
Vil
RCa
TYP*
2.4
3.2
V,
2.4
3.2
VIH = 2 V,
= MAX
Vcc = MAX,
'lS593 Q
10H
=
-1 rnA
IOH = -2.6 rnA
10H = -1 rnA
10l
0.25
0.25
10l = 8 rnA
VIH
=2
V,
Vcc = MAX,
'lS593 Q
VIH = 2 V,
Vil = MAX,
Vil
= MAX,
Va = 0.4 V
VI = 5.5 V
Vcc = MAX
Others
Vcc = MAX,
I VI = 7 V
VI
= 2.7
V
CCK
~
TYP*
MAX
-1.5
2.4
3.1
2.4
3.2
0.4
= 24 rnA
Va = 2.7 V
IIH
0.4
UNIT
V
V
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
V
20
20
"A
-0.4
-0.4
rnA
0.1
0.1
0.1
0.1
20
20
-0.8
-0.8
rnA
"A
fI)
-0.2
-0.2
-0.8
-0.8
A thru H
-0.4
-0.4
'S:
Others
-0.2
-0.2
o
RCK
III
lOS!
MIN
-1.5
-18 rnA
=2
MAX
10l = 16 rnA
'lS593 Q
II
VIH
MIN
10l = 12 rnA
'lS593 Q
VOL
10Zl
II
VCC = MIN,
Vil = MAX
RCa
10ZH
=
VCC = MIN,
SN74LS'
SN54LS'
TEST CONDITIONSt
'lS593
'lS593 Q
Vcc
RCa
'lS592
~
ICCl
ICC
'lS593
Vcc
~
~
ICCZ
= MAX,
= MAX,
VI = 0.4 V
Vo
=0
-30
V
-20
-130
-30
-100
-20
-130
-100
40
60
40
60
Vcc = MAX,
40
60
40
60
All possible inputs grounded,
47
70
47
70
All outputs open
53
80
53
80
57
85
57
85
rnA
Q)
(,)
Q)
rnA
........
....I
rnA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:tAU typical values are at Vee = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time and the duration of the short~circuit should not exceed one second.
TEXAS .."
INSTRUMENlS
POST OFFICE BOX 855012 • DALLAS. TeXAS 75265
2-987
SN54LS592, SN54LS593, SN74LS592, SN74LS593
8·BIT BINARY COUNTERS WITH INPUT REGISTERS
switching characteristics, Vee
PARAMETER
= S V, TA =2Soe, (see note 3)
FROM
TO
(INPUT)
(OUTPUT)
TEST CONDITIONS
RL = 1 kfl,
CL - 30 pF
'LS592
MIN
TYP
20
35
MIN
TYP
20
35
MAX
UNIT
MHz
f max
CCK
RCO
tPLH
CCKt
Q
14
21
tpHL
CCKt
Q
26
39
ns
ns
ns
tPLH
CLOAO I
Q
34
51
tpHL
CLOAO I
Q
28
42
ns
tpHL
tpZH
CCLR I
Q
25
38
Gt
Q
31
47
tpZL
G t
Q
27
40
ns
ns
ns
tpZH
G I
Q
29
45
ns
tpZL
G I
Q
31
47
ns
tpHZ
G
j
Q
33
50
ns
tPLZ
G I
Q
35
52
ns
tPHZ
G t
Q
26
39
tPLZ
G t
Q
28
42
ns
ns
RL = 667 fl,
RL = 667 fl,
CL=45pF
CL = 5 pF
tpLH
CCK t
RCO
15
23
14
21
ns
tPHL
CCK t
RCO
20
30
20
30
ns
tPLH
CLOAD
j
FfCO
31
47
31
47
ns
tPHL
CLOAD I
RCO
27
41
27
41
ns
tpLH
CCLR I
RCO
30
45
30
45
ns
tPLH
RCKt
RCO
RL = 1 kn;
35
53
42
63
tpHL
RCKt
RCO
CLOAD = L
30
45
33
50
ns
ns
RL = 1 kn,
CL = 30 pF
CL - 30pF
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-988
'LS593
MAX
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALl.AS, TEXAS 76285
SN54LS594, SN54LS599, SN74LS594, SN74LS599'
8·BIT SHIFT REGISTERS WITH OUTPUT LATCHES
02747, JUNE 1983 - REVISED MARCH 1988
SN54LS594, SN54LS599 .•. J OR W PACKAGE
SN74LS594, SN74LS599 .•. N PACKAGE
•
8-Bit Serial-In, Parallel-Out Shift
Registers with Storage
•
Choice of Output Configurations:
'LS594 ... Buffered
'LS599 ... Open-Collector
•
•
•
(TOP VIEW)
08
00
VCC
OA
SER
Guaranteed Shift Frequency:
DCto20MHz
OE
RCLA
OF
ACK
Independent Oirect-Overriding Clears on
Shift and Storage Registers
OG
SACK
Oc
SACLA
OH
GNO
OH'
Independent Clocks for Both Shift and
Storage Registers
SN54LS594, SN54LS599 ... FK PACKAGE
description
(TOP VIEW)
Ualutl<
These devices each contain an a-bit D-type storage
register. The storage register has buffered ('LS5941 or
open-collector ('LS5991 outputs. Separate clocks and
direct-overriding clears are provided on both the shift
and storage registers. A shift output (QH 'I is provided
for cascading purposes,
00
z > 0
3 2 1 2019
SEA
ACLR
I/)
Q)
.~
NC
>
Q)
RCK
9 1011 1213
o
IIa:
a:
lI-
SRCK
Both the shift register and the storage register clocks
are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always
be one ciock pulse ahead of the storage register.
...J
::I: C U
Clzzod
Cl
If)
NC -
No internal connection
schematics of inputs and outputs
EQUIVALENT OF SERIAL INPUT
EQUIVALENT OF ALL OTHER INPUTS
Req
VCClS
VCC-~--
20 kn NOM
INPUT
__
TYPICAL OF QH' OUTPUTS
INPUT-ff....--.---t-Vcc
RCK, SRCK: Req = 10 kn NOM
ALL OTHER: Req - 13 kn NOM
TYPICAL OF ALL OTHER OUTPUTS ('LS594)
VCC
TYPICAL OF ALL
OTHER OUTPUTS ('LS599)
OUTPUT
___ ~OUTPUT
OUTPUT
PROIiuCTIDN DATA documents contain information
currant as of publication data. Praducts conform to
specifications per the terms of Taxas Instrumants
=~~::~~i;8f::I~'~ ~!::i:~ti:; :.~~:~::::.::s~s
not
TEXAS . . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-989
'SN54LS594, SN541S599, SN74LS594, SN74LS599
8·BIT SHIFT REGISTERS WITH OUTPUT LATCHES
logic diagram (positive logic)
Pin numbers shown are for J, N, and W packages.
2-990
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS594, SN54LS599, SN74LS594, SN74LS599
8-BIT SHIFT REGISTERS WITH OUTPUT LATCHES
logic symbols t
'LS594
'LS599
RCLR 1131~1=-----'
RCLR 1131~Ir.R:::3-----'
RCK
(12)
(121
RCK
SACK
20 l>
3
(15)
0)
201> 30
QA
(lSI
(1}
121 OB
(3) Oc
(3)
00
t>
3
I>
Qc
141
0,
151
(4) 00
(61
oG
171
OH
191
/---+----1-161161 0,
(5)
0,
20
QA
(21 °B
OE
(1) QG
201> 30
(9) QH
I>
°H'
OH
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for J, N, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 11 ................................................................ 7 V
Input voltage ............................................................................... 7 V
Off-state output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54LS594, SNS4LS599 .... , ....................... - 55°C to 12Soe
SN74LS594, SN74LS599 ................................ oOe to 70°C
Storage temperature range .......................................................... - 6Soe to 150°C
NOTE1: Voltage values are with respect to the network ground terminal.
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
IOH
High-level output current
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.8
V
2
V
2
0.7
QA thru QH, 'LS599 only
5.5
5.5
QH'
-1
-1
QA thru QH, 'LS594 only
-1
- 2.6
QH
Q
8
16
12
24
V
rnA
Low-level output current
fSRCK
Shift clock frequency
fRCK
Register clock frequency
twlSRCK}
Duration of shift clock purse
25
25
ns
twlRCK}
Duration of register clock pulse
20
20
ns
'wlSRCLR}
Duration of shift clear purse, low revel
20
20
ns
twlRCLR}
Duration of register clear purse, low level
35
35
ns
20
20
SRCLR inactive before SRCKt
'h
TA
Setup time
Hold time
C
I-
SN74LS'
IOL
'su
::Q)
lSN54LS'
Supply voltage
Q)
-~
..J
recommended operating conditions
VCC
I/)
0
20
0
25
20
MHz
0
25
MHz
SER before SRCKt
20
20
SRCKt before RCKt Isee No'e 2)
40
40
SRCLR low before RCK t
40
40
RCLR high before RCKt
20
20
SER after SRCK!
Operating free-air temperature
-55
ns
0
0
125
rnA
0
0
ns
70
'c
NOTE 2: This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be connected together, in
which case the storage register state will be one clock pulse behind the shift register.
TEXAS •
INsrRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-991
SN54LS594. SN54LS599. SN74LS594. SN74LS599
8-BIT SHIFT REGISTERS WITH OUTPUT LATCHES
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIK
'LS594 Q
VOH
Vee = MIN,
11=-18mA
VCC = MIN,
VIH =2 V,
VIL = MAX
QH'
VIH = 2 V,
VCC =MIN,
VI-7 V
IIH
VCC -MAX,
VI-2.7V
'LS594 Q
CD
<
c:;-
CD
CI)
VCC= MAX,
QH'
'LS594
IOH - - 2.6 rnA
VIL -MAX,
TVP* MAX
-1.5
2.4
3.1
2.4
3.2
0.25
0.4
0.25
0.4
0.35
0.5
0.25
0.4
0.25
0.4
0.35
0.5
IOL =24rnA
rnA
V
0.1
rnA
20
20
p.A
-0.4
- 0.4
-0.2
-30
-130
-30
-130
-20
-100
-20
-100
All outputs open
'LS599
V
0.1
-0.2
Vo =0
UNIT
V
0.1
0.1
VCC= MAX,
All possible inputs grounded,
'LS599
'LS594
ICCL
3.2
MIN
-1.5
VI=0.4V
VCC=MAX,
All others
ICCH
2.4
SN74LS'
MAX
IOL -16 rnA
VCC = MAX,
r-
3.2
IOL =8 rnA
II
SER
C
VIH = 2V,
VIL =MAX
QH'
-t
-t
2.4
IOH --1 rnA
IOL-12rnA
Q
IOS§
TVP*
VOH=5.5V
VOL
IlL
MIN
IOH =-1 rnA
VCC=MIN,
'LS599 Q
IOH
SN54LS'
TEST eONolTIONS t
PARAMETER
34
50
34
50
30
45
30
45
42
65
42
65
38
55
38
55
rnA
rnA
rnA
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions,
t
All typical values are at
Vee;:
5 V, T A
=
25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
switching characteristics, Vee = 5
FROM
(INPUT)
(OUTPUT)
SRCKt
QH'
RL = 1 kfl,
CL = 30 pF
RCKt
QA thru QH
RL = 667 fl,
CL = 45 pF
tpHL
SRCLRI
QH'
tpHL
RCLRI
QA thru QH
RL 1 kfl,
RL =667 fl,
PARAMETER
tpLH
tpHL
tpLH
tpHL
TO
V, T A = 2S o e, (see note 3)
TEST CONDITIONS
TVP
MAX
MIN
TVP
MAX
UNIT
12
18
12
18
ns
15
23
17
25
ns
12
18
28
42
ns
20
30
24
35
ns
CL - 30 pF
22
33
24
35
ns
CL - 45 pF
38
57
40
60
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-992
'LS599
'LS594
MIN
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS595, SN54LS596, SN74LS595, SN74LS596
8·BIT SHIFT REGISTERS WITH OUTPUT LATCHES
02634, JANUARY 1981 - REVISED MARCH 1988
SN54lS595, SN54LS596 .•• J OR W PACKAGE
SN74lS595, SN74LS596 ... N PACKAGE
(TOP VIEW)
• a·Bit Serial-In, Parallel-Out Shift
Registers with Storage
• Choice of 3-State ('LS595) or
Open-Collector ('LS596) Parallel Outputs
• Shift Register Has Direct Clear
• Accurate Shift Frequency:
DC to 20 MHz
description
Os
vcc
Oc
00
OA
SER
OE
G
OF
RCK
OG
SRCK
SRCLR
OH
GNO
These devices each contain an B-bit serial-in,
parallel-out shift register that feeds an B-bit D-type
storage register. The storage register has parallel
3-state ('LS595) or open-collector ('LS596) outputs.
Separate clocks are provided for both the shift register
and the storage register. The shift register has a
direct-overriding clear, serial input, and serial output
pins for cascading.
OH'
SN54lS595, SN54LS596 ... FK PACKAGE
(TOP VIEW)
•
UalU~«
00 Z > 0
3
2
1 2019
In
Both the shift register and storage register clocks are
positive-edge triggered. If the user wishes to connect
both clocks together, the shift register state will always
be one clock pulse ahead of the storage register.
Q)
.~
>
Q)
C
9 1011 1213
II5
...J
IOU
OZZOu
C)
lI-
et:
en
NC - No internal connection
schematics of inputs and outputs
EQUIVALENT OF SERIAL INPUT
EQUIVALENT OF ALL OTHER INPUTS
TYPICAL OF QH' OUTPUTS
---_VCC
Req
VCC1ij
VCC-......- 2Ok!1 NOM
INPUT
_.
OUTPUT
INPUT -.+...--<1....
RCK, SRCK: Req = 10 k!1 NOM
ALL OTHER: Req -13 k!1 NOM
TYPICAL OF ALL OTHER OUTPUTS ('LS595)
TYPICAL OF ALL OTHER OUTPUTS ('LS596)
Vee
---r;;:;-
OUTPUT
OUTPUT
PRODUCTION DATA documenls contain in'ormation
currant as of publication date. Products conform to
specifications per the terms of TIXIS Instruments
::~:~~i~·r::I-:.t ~:~:::f :'i'::~::~~BI nat
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-993
SN54LS595, SN54LS596, SN74LS595, SN74LS596
8·BIT SHIFT REGISTERS WITH OUT.PUT LATCHES
logic diagram (positive logic)
G (13)
RCK
SRCLR
SRCK
SER .:.:..:.~--+-+----t
>--+-.....;(-,-1) as
(2)
QC
-I
-I
rC
(I)
:::.
(3)
QO
(")
(I)
VI
(4) QE
>--+-......:;(5;,:.) QF
'--_ _ _ _ _ _-Cl>--.:.;(9;.:.) QH'
Pin numbers shown are for J, N, and W packages.
2-994
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS595, SN54LS596, SN74LS595, SN74LS596
8-BIT SHIFT REGISTERS WITH OUTPUT LATCHES
logic symbols t
'LS595
'LS596
G
G
RCK
RCK
SRCLR
SRCLR
SRCK
SRCK
(15)
SER
(1)
(2)
(3)
(4)
OA
(15)
SER
(1)
Os
(2)
Oc
(3)
00
(4)
(5) °E
OF
20 [> 3 \7
(5)
OA
Os
Oc
00
OE
OF
(6)
(6)
(7) °G
°H
(9)
Ow
(7) °G
OH
20 [> 3 Q
(9)
Ow
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and lEe Publication 617-12.
Pin numbers shown are for J. N, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, vee (see Note 1) ............................................................... 7 V
Input voltage ............................................................................... 7 V
Off·state output voltage .................................................................... 5.5 V
Operating free·air temperature range: SN54LS595, SN54LS596 ............................ - 55°C to 125°C
SN74LS595, SN74LS596 ................................. oOe to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
NOTE 1: Voltage values are with respect to the network ground terminal.
CI)
Q)
CJ
-S;
Q)
C
-I
lI-
recommended operating conditions
SN54LS'
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
IOH
High-level output current
IOL
Low-level output current
fSRCK
Shift clock frequency
SN74LS'
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.8
V
2
2
0.7
V
QA thru QH, 'LS596 only
5.5
5.5
QH'
-1
-1
QA thru QH, 'LS595 only
-1
-2.6
QH'
Q
0
8
16
12
24
20
0
20
V
rnA
rnA
MHz
tw(SRCK)
Duration of shift clock pulse
25
25
tw(RCKI
Duration of register clock pulse
20
20
ns
'w(SRCLRI
Duration of shift clear pulse, low level
20
20
ns
SAC LA inactive before SACK t
20
20
SER before SRCK t
20
20
'su
Setup time
SRCK t before RCK t (see Note 21
40
40
SRCLR low before RCK t
40
40
'h
TA
Hold time
Operating
SER after SRCK t
free~air
temperature
0
- 55
ns
ns
0
125
0
ns
70
°c
NOTE 2: This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be connected together, in
which case the storage register state will be one clock pulse behind the shift register.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-995
SN54LS595, SN54LS596, SN74LS595, SN74LS596
8·BIT SHIFT REGISTERS WITH OUTPUT LATCHES
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
VIK
'LS595 Q
VOH
QH'
'LS596Q
IOH
Q
VOL
QH'
•
IOH --1 mA
VIL - MAX, VOH-5.5V
2.4
3.2
VIH - 2 V,
IOL-12mA
Vee=MIN,
VIH=2V,
IOL -8mA
VIL -MAX,
VOH=0.4V
leeL
lecz
QH'
'LS595
'LS596
-1.5
2.4
3.1
2.4
3.2
0.25
0.35
0.4
0.5
0.25
0.4
0.25
0.4
0.35
0.5
- 30
-20
33
'LS595
Vee = MAX,
All possible inputs grounded,
'LS596
All outputs open
30
42
36
'LS595
44
20
-20
0.1
20
- 0.4
-0.2
-130
-100
50
45
65
55
65
0.1
20
t:
All typical values are at Vee;;; 5 V, T A'" 25°C.
§ Not
·2·996
more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second,
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
V
p.A
p.A
mA
-0.2
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
mA
0.1
20
-130
-20
V
20
-0.4
-30
UNIT
V
0.1
0.4
Vee = MAX, VI=O.4V
Vee = MAX, Vo=OV
MAX
0.25
Vee = MAX, VI = 7 V
Vee= MAX, VI-2.7V
All others
TYP*
IOL = 16 mA
Vee -MAX, VIH = 2 V,
'LS595 Q
MIN
IOL =24 mA
VIL = MAX
'LS595 Q
~.
en
MIN,
3.2
IOZL
II
C
CD
Vee
2.4
I
SN74LS'
TYP* MAX
-1.5
IOH =-1 mA
IOH --2.6mA
VOH=2.7V
leeH
C')
VIL = MAX
I
VIL -MAX,
IOS§
CD
VIH = 2V,
Vee = MAX, VIH =2V,
SER
r-
11=-18mA
Vec=MIN,
'LS595 Q
IIH
-I
Vee-MIN,
MIN
IOZH
IlL
-I
SN54LS'
TEST CONDITIONS t
-100
33
50
30
45
42
65
36
44
55
65
p.A
mA
mA
mA
mA
mA
SN54LS595, SN54LS596, SN74LS595, SN74LS596
8·BIT SHIFT REGISTERS WITH OUTPUT LATCHES
switching characteristics, Vee = 5 V, T A = 25°e (see note 3)
PARAMETER
tPLH
FROM
TO
(INPUT)
(OUTPUT)
SRCKt
QH'
RCKt
QA thru QH
tpHL
tpLH
tpHL
tpZH
Cil
QA thru QH
Cit
QA thru QH
tpLH
Gt
QA thru QH
tpHL
GI
QA thru QH
tpHL
SRCLR I
QH'
tpZL
tpHZ
tPLZ
TEST CONDITIONS
RL = 1kn,
'LS595
MIN
CL = 30 pF
RL =667n,
CL = 45 pF
RL=667n,
CL = 5 pF
RL = 667 n,
CL =45pF
RL = 1 kn,
CL - 30 pF
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TYP
'LS596
MAX
MIN
TYP
MAX
UNIT
12
18
14
21
ns
17
25
20
30
ns
12
18
28
42
ns
24
35
24
35
20
30
ns
25
38
ns
20
30
ns
25
38
24
35
ns
ns
40
60
ns
25
38
ns
24
35
ns
•
II)
Q)
.~
>
Q)
o
...J
~
~
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-997
-.-.
r-
oCD
<
(")
CD
CIl
2-998
SN54LS597, SN54LS598, SN74LS597, SN74LS598
8-BIT SHIFT REGISTERS WITH INPUT LATCHES
02635, JANUARY' 98, - REVISED MARCH '988
• 8-Bit Parallel Storage Register Inputs
('LS597)
SN54LS597 ... J OR W PACKAGE
SN74LS597 ... N PACKAGE
(TOP VIEWI
• Parallel 3-State I/O, Storage Register
Inputs, Shift Register Outputs ('LS598)
VCC
A
• Shift Register has Direct Overriding Load
and Clear
SER
SRLOAO
F
RCK
G
• Accurate Shift-Frequency __ , DC to 20
MHz
SACK
SRCLR
OH'
description
The 'LS597 comes in a 16-pin package and consists of
an B-bit storage latch feeding a parallel-in, serial-out
B-bit shift register. Both the storage register and shift
register have positive-edge triggered clocks. The shift
register also has direct load (from storage I and clear inputs.
SN54LS597 ... FK PACKAGE
(TOPVIEWI
u
u
CD
u u
z >
0(
SER
SRlOAO
The 'LS59B comes in a 20-pin package and has all the
features of the 'LS597 plus 3-state 1/0 ports that provide parallel shift register outputs and also has
multiplexed serial data inputs.
NC
en
RCK
SRCK
Q)
(.)
-S;
Q)
C
SN54LS598 ... J OR W PACKAGE
LS598 ... OW OR N PACKAGE
(TOP VIEWI
BIOe
vcc
os
cloe
SERQ
AlOA
DiaD
E/Qe
F/QF
G/QG
H/QH
-I
I-I--
SER'
G
RCK
SRCKEN
SRCK
SRCLR
SRLOAO
GNO
OH'
SN54LS598 ... FK PACKAGE
(TOP VIEWI
uco«
000 u
;:; d:i::(~:g
3212019
0/0 0
E/OE
F/QF
18
17
SERO
SERl
16
G
G/OG
15
RCK
H/QH
14
SRCKEN
6
9 1011 1213
NC - No internal connection
PRODUCTION OATA·d.....anta conilin information
carmt .1 01 pabUclliln doll, Praducts conl.rm to
lpocilicllionl
thl "'.... 01 TI. .I Ilotru..lnto
,or
::=~~i~'I~:I~li ~=::i~n ~l":::::~~~ nil
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-999
SN54LS597, SN54LS598, SN74LS597, SN74LS598
8·BIT SHIFT REGISTERS WITH INPUT LATCHES
schematics of inputs and outputs
EQUIVALENT OF SERIAL AND
A THRU H INPUTS
EQUIVALENT OF SRCK INPUT
('LS598 ONLY)
VCC---t-Req
EQUIVALENT OF ALL OTHER INPUTS
VCC
15kn
NOM
s
Req
INPUT
I NPUT -.,!~--~
('LS597) RCK, SRCK: Req a 10 kn NOM
,'LS598) RCK: Req· 10 kn NOM
ALL OTHER: Req = 13 kn NOM
SERIAL: Req - 20 kn NOM
A thru H: Req - 25 kn NOM
TYPICAL OF Qt{ OUTPUTS
TYPICAL OF QA THRU QH OUTPUTS
('LS598 ONLY)
---._VCC
Vec
-I
-I
r
o
<
,;,
OUTPUT
OUTPUT
(I)
(I)
en
logic symbols t
'LS598
20
~lsIr--+----1
H
191 Ow
(111 Ow
tThis symbol is in accordance with ANSI/IEEE Std. 91·1984 and lEe Publication 617-12.
Pin numbers shown are for OW, J, N, and W packages.
2-1000
__
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54LS597, SN74LS597
8-BIT SHIFT REGISTERS WITH INPUT LATCHES
logic diagram (positive logic)
'LS597
4-______4-______~________--,
SER~(1~41~__~__________
A 1151
B (11
I/)
Q)
(.)
'SQ)
C (2)
C
.......J....
[) (3)
E (41
F (51
G (61
H(7J
Pin numbers shown are for OW, J, N, and W packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1001
SN54LS598, SN14LS598
8·BIT SHIFT REGISTERS WITH INPUT LATCHES
logic diagram (positive logic)
G(18)
~~(1~~~
~
~
r0
'LS598
____________________--,
B/Qs(21
CD
<
(=;'
CD
C/Qc (3)
Ul
D/QD (4)
..
E/QE;;;;(S,:,,). . .__+~
"'-+-6-f
F/QF;;;;16",,)
G/llG.;;(7.:,.1
_--+. . .
-t
---+. . .
H/QH .l::(8::...)
2-1002
~
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54LS597, SN54LS598, SN74LS597, SN74LS598
8-BIT SHIFT REGISTERS WITH INPUT LATCHES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage (excluding 1/0 ports) .............................................................. 7 V
Off·state output voltage (including 1/0 ports) .................................................... 5.5 V
Operating free·air temperature range: SN54LS597, SN54LS598 ..... . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°e
SN74LS597, SN74LS598 ................................ oOe to 700 e
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°e to 1500 e
NOTE 1: Voltage values are with respect to the network ground terminal.
recommended operating conditions
SN54LS'
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
Low-level output current
fSCK
Shift clock frequency
'h
TA
MIN
4.5
5
5.5
4.75
NOM
MAX
5
5.25
QH
-1
-1
QA thru QH, 'lS598 only
-1
- 2.6
QH'
Q A thru QH, 'LS598 only
I high
J low
RCK
8
16
12
24
20
0
15
15
35
35
20
20
SRClR
20
20
SRlOAO
40
40
Data before RCK t
20
20
30
OS before SRCK t ('lS598 only)
30
SRCKEN low before SRCK t ('lS598 only)
20
20
SRCLR inactive before SRCK t
25
25
SRLOAD inactive before SRCK t
30
30
RCK t before SRlOAO t (see Note 2)
40
40
SER before SRCK t
20
20
Hold time
0
Operating free-air temperature
- 55
20
V
0
V
mA
mA
(I)
Q)
MHz
.~
ns
C
>
Q)
...J
lI-
ns
ns
0
125
UNIT
V
2
0.8
0
Pulse duration
Setup time
MAX
0.7
SRCK
'su
NOM
2
IOl
tw
SN74LS'
MIN
70
"C
NOTE 2: The RCK t before'SR"LOAiJ t setup time ensures the data saved by ACK t will also be loaded into the shift register.
"J1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1003
SN54LS597, SN54LS598, SN74LS597, SN74LS598
8·BIT SHIFT REGISTERS WITH INPUT LATCHES
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST eONDITloNst
VIK
VOH
'lS598 a
'lS598 a
VOL
°H'
IOZL
'lS598 a
'lS598 a
rC
',l
'LS598 SRCK
SER, A Thru H
(1)
3.2
2.4
3.2
0.25
V,H = 2 V,
Vee= MAX,
V,H = 2 V,
V'H-2V,
V,l=MAX,
0.25
V,=5.5V
V, = 7 V
Vec- MAX,
V,- 2.7 V
Vec= MAX,
V, = 0.4 V
IOS§
'lS598 a
°H'
Vee= MAX,
Vo= OV
'lS597
Ice
'lS598
VI
~
leel
~
leel
~
TYP* MAX
-1.5
2.4
2.4
0.4
3.1
3.2
0.25
-30
- 20
Vee= MAX,
All possible inputs grounded,
All outputs open
35
35
45
54
56
TEXAS ""
INSTRUMENTS
POST OFFICE BOX 65501.2 • DALLAS. TEXAS 75265
V
V
V
20
/iA
-0.4
- 0.4
rnA
0.1
0.1
20
0.8
- 0.4
-0.2
-130
-100
53
53
68
80
85
0.1
0.1
20
0.8
-0.4
-0.2
-130
-100
0.4
-30
-20
35
35
45
54
56
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions .
.; All typical values are at Vee = 5 V, T A = 25°C
§Not more than one output should be shorted at a time and the duration of the shortRcircuit should not exceed one second.
2-1004
UNIT
0.4
0.5
0.4
0.5
0.35
0.25
0.35
20.
Others
(1)
S.
o
2.4
Vec= MIN,
Vil = MAX
Vec= MAX
Others
MIN
-1.5
IOH= -1 rnA
IOH - 2.6 rnA
IOH--1 rnA
'Ol=12mA
'Ol- 24 rnA
IOl-8mA
IOl=16mA
V,l = MAX,
Vee MAX,
Vo= 0.4 V
"H
-I
-I
V,H = 2 V,
SN74LS'
TYP* MAX
Vo= 2.7 V
'lS598 a
"
11=-18mA
Vee = MIN,
V,l = MAX
°H'
IOZH
Vee= MIN,
SN54LS'
MIN
53
53
68
80
85
rnA
/iA
rnA
rnA
rnA
SN54LS597, SN54LS598, SN74LS597, SN74LS598
8·BIT SHIFT REGISTERS WITH INPUT LATCHES
switching characteristics. Vee
PARAMETER
5 V. TA
FROM
TO
IINPUT}
(OUTPUT)
25°e. (see note 3)
TEST CONDITIONS
'LS597
MIN
TYP
f max
SRCK
Q
RL - 667O,
CL - 45 pF
20
35
f max
SRCK
QH'
RL = 1 kll,
CL = 30 pF
20
35
tpLH
SRCKt
QH'
tpHL
SPCKt
QH'
tpLH
SRLOADI
QH'
RL = 1 k(J,
CL = 30 pF
tpHL
SRLOADI
tpHL
'LS598
MAX
MIN
TYP
20
35
MAX
UNIT
MHz
MHz
15
23
11
17
ns
20
30
15
23
ns
38
57
28
42
ns
QH'
29
44
20
30
ns
SRCLRI
QH'
24
36
18
27
ns
tpLH
RCKt
QH'
RL = 1 kll,
41
60
32
48
ns
tpHL
RCKt
QH'
SRLOAD = L
32
48
24
36
ns
tpLH
SRCKt
Q
12
18
ns
tpHL
SRCKt
Q
19
28
ns
tpLH
SRLOADI
Q
32
48
ns
tpHL
SRLOADI
Q
27
40
ns
tpHL
SRCLRI
Q
25
38
ns
tpZH
GI
Q
26
31
ns
tpZL
GI
Q
29
43
ns
tpHZ
Gt
Q
25
38
ns
tpLZ
Gt
Q
20
30
ns
CL=30pF
RL = 6670,
RL = 6670,
CL = 45 pF
CL = 5 pF
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
•
til
Q)
CJ
'S;
Q)
C
..J
lI-
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
2-1005
SN54LS597, SN54LS598, SN74LS597, SN74LS598
8·BIT SHIFT REGISTERS WITH INPUT LATCHES
typical operating sequences
'LS597
-----1
SRCLR
L.J
SRLOAD
SRCK
______
RCK
~fl~
_______________________________
SER
A
IOON'T CARE'A
vllOomOWlllOWOOOl7,DON'T CARElllW77001lO0WOW77l11
B
ZDON'TCARE~
WI1IIImomoomllOm,DDN'T CAREoomvollmummOIV/Z
,DON'T CARE'd
WomOOijmOlOlmWZDON'TCAREwmzzooooowmoom
D
2DON'TCAAE~
voomzmmmmmOO/UDON'TCAREWIOOOmmlllmmmm
E
jOON'TCARE'I1
VZOWlII0I0I1OIIIWM/I,DON'T CAREI/I//III//OOL7lO7lO001/O
F
lOON'T CARE~
voozmOOzmmzZOOWl/,DON'TCAREi/WW/lOOO/MOzmoo
G
IOON'T CARE'A
WO/717mmzmOOZOOIll DON 'T CARE'ZOOWl7lwzmoomom
H
2DON'TCARE~
C
0H'
'LS598
G --.J
SRCLR
-.J
U
SRLOAD
SRCK
SRCKEN
RCK
I/lWnDo"'T CAREIZZWII/I
V!OON'T CARE'!,
0 ZZZOOZZ,DON'TCAREl/ZZ171lA
vZOOI/lZ/lDON'T CARE / ;
DS
SER
____-JrlL_______________________
SER 1
mOZlZlDoN'TcAREZZZOZOZZ1l/OZ7lA
V/OON'TCARE//
AlOA
BlOB
C/Oc
D/OD
E/QE
FIOF
G/QG
~---1
HIOH
0H'
--.lOUT· ~ ...IINPUT~ 1-~1------SHIFT&OUTPUT-----t'1
IPUT+f HI-Z
"'HI-Zf4
t"'"
2-1006
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SN74LS600A, SN74LS601A, SN74LS603A
MEMORY REFRESH CONTROLLERS
02547, JANUAII'V 1981 - REVISED MARCH 1988
SN74LS' ... DW OR N PACKAGE
(TOP VIEWI
•
Controls Refresh Cycle of 4K, 16K, and
64K Dynamic RAMs
•
Creates Static RAM Appearance
•
Choice of Transparent, Cycle Steal, or
Burst Refresh Modes
•
•
BUSY
3-State Outputs Drive Bus lines Directly
AD
VCC
RC BURST
A1
SEE TABLE
A2
SEE TABLE
A3
}lOLD
A4
RAS
A5
REF RE02
A6
REF REOI
SEE TABLE
Critical Times Are User RC-Programmable
to Optimize System Performance
RC RAS LO
GND
RC RAS HI
FOR CHIP CARRIER INFORMATION
CONTACT THE FACTORY
SELECTION TABLE
DEVICE
REFRESH MODES
MEMORY SIZE
'LS600A
Transparent, Burst
'LS601A
'LS603A
•
PIN ASSIGNMENTS
PIN 9
PIN 17
PIN 18
4Kor 16K
4KI16K
LATCHED RCO
RESET LATCHED RCO
Transparent, Burst
64K
A7
LATCHED RCO
RESET LATCHED RCO
Cycle Steal, Burst
64K
A7
READY
RC CYCLE STEAL
I/)
Q)
(.)
'S;
description
Q)
The 'LS600A, 'LS601A, and 'LS603A memory refresh controllers contain one 8-bit synchronous counter, nine 3-state buffer
drivers, four RC-controlled multivibrators, and other control Circuitry on a single monolithic chip. These devices are designed
to provide RAS-only refresh on 4K, 16K, and 64K dynamic RAMs. The 'LS600A and 'LS601A provide transparent refresh
while the 'LS603A provides cycle-steal refresh. In addition, a burst-mode timer is provided to warn the CPU that the maximum
allowable refresh time is about to be violated,
C
...J
lI-
operating modes
In the transparent refresh mode ('LS600A or 'LS601 AI. row-refresh cycles occur only during inactive CPU-memory times.
In most cases the entire memory refresh sequence can be completed "transparently" without interrupting CPU operations.
During idle CPU-memory periods, the REF REO pins should be taken high so as many rows as possible can be refreshed.
A low from BUSY will signal the CPU to wait until the end of that current row refresh before reinstating operations. If all
row addresses have been refreshed before the burst-mode timer expires, the burst-mode timer will reset.
If the maximum allowable refresh time of the dynamic RAM is about to be exceeded, the burst mode timer will expire causing
the HOLD pin to go low. This signals the CPU that a burst-mode refresh is mandatory and the burst-mode refresh will
be accomplished when the CPU takes the REF REO pins high. To ensure that all rows are refreshed, the address counter
is reset to zero whenever the burst-mode timer expires. After the last row has been refreshed, the HOLD pin will return
high, and the burst-mode timer will reset. The CPU can then return to normal transparent operation.
A LATCHED RCO output pin is also provided on the 'LS600A and 'LS601 A to detect when the last row has been refreshed.
Upon seeing a RCO from the address counter, the LATCHED RCO output will be set high. This latch is reset by providing
a high-going pulse on the RESET LATCHED RCO input.
In the cycle-steal refresh mode ('LS603AI, refreshing is accomplished by dividing the safe refresh time into equal segments
and refreshing one row in each segment. The segment time is programmed via the RC CYCLE STEAL input and will produce
a low level on the READY output at the end of each segment period. This indicates to the CPU to suspend operations for
one memory cycle for a row refresh. In effect it "steals" one memory cycle from the CPU. After the CPU recognizes the
cycle-steal signal from the READY output, it must take both REF REO pins high. These devices will then refresh one row
and return control back to the CPU by taking READY high. The burst-mode timer is also provided to prevent exceeding the
maximum allowable refresh time, and operates in the same manner as in the 'LS600A and 'LS601 A. In applications where
the burst-mode timer is not required, it can be disabled by connecting the RC Burst input to ground.
Copyright @ 1983. Texas Instruments Incorporated
PRODUCTION DATA documents contain information
currant IS of publication data. Products conform to
specifications per the tarms of Tlxas Instruments
~'=:~~i~8{::I: ~!:~:ti:fn :.~O:;::~:~~ not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1007
SN74LS600A, SN74LS601A
MEMORY REFRESH CONTROLLERS
'LS600A
.---------.....------------------------1 "'J_------'I~IS::!..1 RAli
">----------+--41......1 "'X1--____..!.(1~1 ilmV
4-,
RCRASHI~I~II~I~~______________
RCRASLO~I~I.~I~*_---,
erR7
I> 4\7
I> 4\7
I>
I>
I>
I>
•
121
131
141
lSI
161
171
AO
AI
A'
A3
A4
AS
I>
4K/i6K .!19::!.1---+-+-l
R
-t
-t
RC BURST ..:.11.::9::...1~
RESET
(18)
LATCHED .!.!.::!.----I~>---------------------------------_01
RCO
<
(i'
n>
en
'LS601A
~----.....-------------l~>c~---~(1~SI ~
-d>_ _ _ _ _
RCASHHI1"~I~'~~-------~
RCASHLOlll~2~1~.(1"'81'--_-1 ~~---------------------_d
RCO
Pin numbers shown are for OW and N packages.
2-1008
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
---<~"')c>__---.:.(1::.1
IillSV
SN74LS603A
MEMORY REFRESH CONTROLLERS
r---------.------------------------I "':>o-______---'I~'5~1 ~
RC~HI~I~l1~I~~------------~~
> ________---<..-.....-1 '::oo-____--'IC!!.1) BUSY
RC~LO~I'~2~1~~----,
~--__----------~4_--_4;.~----~116~1 HOLD
RC BURST
-,-1'-",9:<.. 1~~-I
CI)
Q)
Q
'>
o
Q)
...J
Pin numbers shown are for OW and N packages.
lI-
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1009
SN74LS600A, SN74LS601A, SN74LS603A
MEMORY REFRESH CONTROLLERS
PIN FUNCTION TABLE
PIN
PIN NAME
FUNCTIONAL DESCRIPTION
1
BUSY
16
HOLD
Active output should be a priority interrupt to the CPU for emergency burst refresh.
15
RAS
3-5tate output row address strobe.
11
RC RAS HI
Timing node for high-level portion of RAS. See Note 1.
12
RC RAS LO
Timing node for low-level portion of RAS. See Note 1.
2-8
AO thru A6
3-state output row address lines.
9
A7
MSB row address line for 'LS601 A and 'LS603A (64K-bit memory controllers).
9
4K/16K
input makes the count chain 5 bits long while the low-level makes the count chain
17
READY
Interrupt to CPU for cycle steal refresh ('LS603A).
17
LATCHED RCa
18
RC CYCLE STEAL
Normally high-level, will latch low upon RCa of counter ('LS600A or 'LS601A).
Timing node that controls the READY output ('LS603A). See Note 1.
18
RESET LATCHED
Normally high-level, when pulsed low the LATCHED RCO output will be reset ('LS600A and
Active output indicates to the CPU that a refresh cycle is in progress.
A high input level disables the AS row address line for 'lS600A. (The high-level
6 bits long.)
RCa
'LS601A).
19
RC BURST
13,
REF REal,
14
REF RE02
20, 10
Vr.r., GND
NOTE 1:
Timing node for burst refresh. See Note 1.
High level on both pins starts and continues row refresh. Low on either pin inhibits refresh.
5-V power supply and network ground pins.
AU timing nodes require a resistor to Vee and a capacitor to GND.
schematics of inputs and outputs
EQUIVALENT OF REF REQ, 4K/16K,
TYPICAL OF RAS AND A
TYPICAL OF BUSY, HOLD, READY
AND RESET LATCHED RCO INPUTS
OUTPUTS
AND LATCHED RCO OUTPUTS
V C C - - -....- - -
- -....>---VCC
lOon
~_ _~NOM
REO
VCC
120 n NOM
INPUT--~~~~-~-
OUTPUT
REF REO: Req
4K/i"6i<:
Req
=
=
'---+--- OUTPUT
20 kH NOM
30 kH NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage,
Input voltage
Vee
(see Note 2)
.....................................................
..............................................................
Off-state output voltage
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 2:
2-1010
Voltage values are with respect to network ground terminal.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX
655~12
• DALLAS, TEXAS 75265
V
7 V
...........................................................
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
7
5.5 V
OOC to 70 °e
- 65°C to 150 °C
SN74LS600A, SN74LS601A, SN74LS603A
MEMORY REFRESH CONTROLLERS
recommended operating conditions
MIN
NOM
MAX
4.75
5
5.25
UNIT
V
A, RAS
-2.6
mA
All others
-400
p.A
A.RAS
All others
24
Supply voltage, VCC
High-level output current, IOH
low-level output current, IOl
8
75
High, tSHSl
RAS output pulse t
low, tSlSH
Duration of RESET lATCHED RCO pulse, tRHRl
35
Duration of REF REO pulse during CYCLE STEAL operation, tOHOl
20
Duration or
External timing resistor r Rext
ns
75
I
RC RAS lO, RC RAS HI
I
RC BURST, RC CYCLE STEAL
Operating free-air temperature, T A
inA
ns
ns
1
6
1
1000
70
0
kll
DC
tMaximum operating frequency for the address counter corresponds to its minimum period, which is the sum of ~w(RAS-H) min and twIRAS-Ll min .
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIH
High-level input voltage
Vil
Low-level input voltage
VIK
Input clamp voltage
High-level output
VOH
voltage
A,liAS
voltage
= 2 V,
= O.B V
VIH
All Others
low-level output
VOL
VCC - 4.75 V, II VCC = 4.75 V,
A,liAS
Vil
VCC
VIH
= 4.75
= 2 V,
= 0.8 V
All Others
Vil
A,liAS
VCC = 5.25 V
REF REO at
Typt
MAX
UNIT
V
-1.B rnA
0.8
V
-1.5
V
•
(I)
Q)
(.)
':;
Q)
IOH
=
-2.6 rnA
2.4
2.9
400p.A
2.7
3.1
IOH V,
MIN
2
IOl = 12 rnA
IOl - 24 rnA
V
C
....J
0.25
0.4
0.5
IOl - 4 mA
0.35
0.25
IOl - 8 rnA
0.35
0.5
0.4
lIV
Off-state output
IOZH current, high-level
voltage applied
Off-state output
II
Input current at maximum
input voltage
IIH
III
lOS
ICC
High-level input curre!'t
Low-level input current
A,RAS
Short-circuit
output current§
I All others
Vee =
V
=
2.7 V
20
p.A
Vo
= 0.4 V
-20
p.A
VCC
=
5.25 V,
VI
=
7 V
0.1
rnA
VCC
5.25 V,
VI
VCC
=
=
5.25 V,
VI
= 2.7 V
= 0.4 V
20
-0.4
rnA
VCC
= 5.25
V
VCC - 5.25 V, RC RAS lO
Supply current
tAli typical values are at
= 0.8
Vil
IOZl current, low-level
voltage applied
Vo
-30
-130
-20
-100
a~d
REF REO at 0 V
5 V. TA
=
50
85
p.A
rnA
rnA
2S D C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second .
.
TEXAS"
INSTR.UMENTS
'POST OFFICE BOX·655012.• DALLAS: "'!.EXAS 75265
2-1011
SN74LS600A, SN74LS601A, SN74LS603A
MEMORY REFRESH CONTROLLERS
switching characteristics,
Vee
25°C, see note 3
5V, TA
PARAMETER
FROM (INPUT)
TO (OUTPUT)
tQHBL
tSLBH t
REF REQt
BUSY
l1A!lt
BUSY
tQHSV
REF REQt
RAS
tSHSZ t
1iASt
RAS
tQHAV
REF REQt
1iASt
ADDRESS
ADDRESS
RESET LATCHED
LATCHED
tSHAZ
tRHCL
RCOt
RCa
tSHYH
tSLSH t
'i'Wl t
REAiJ'1'
RASI
1iAS
tSHSL t
RASt
tDHDL •
tYLYL'
HOLD!
RAS
HOLD
READY I
READY
TEST CONDITIONS
CL
=
15 pF, RL
=
MIN
2 k!l
= 320 pF, RL = 667!l
CL = 5 pF, RL = 667!l
CL
CL - 160 pF, RL - 667!l
CL - 5 pF, RL - 667!l
CL
CL
CL
=
=
15 pF, RL
=
=
667!l
=
2 k!l
320 pF, RL
=
1 5 pF, RL
2 k!l
TYP
MAX
30
45
ns
245
300
ns
47
70
ns
245
300
ns
38
245
65
ns
300
ns
37
55
ns
64
85
ns
UNIT
210
ns
245
ns
3.56
ms
27
p.S
tDepends on RC network at pin 11 (4 k!l, 200 pF used for testing).
t Dependes on RC network at pin 12 14 k!l, 200 pF used for testing).
§Depends on RC network at pin 19 (680 k!l, 0.022 ~F used for testing).
'Depends on RC network at pin 18 (10 k!l, 0.01 ~F used for testing).
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
explanation of letter symbols
This data sheet uses a new type of letter symbol to describe time intervals. The format is:
tAB-CD
where:
subscripts A and C indicate the names of the signals for which changes of state or level or establishment of
state or level constitute signal events assumed to occur first and last, respectively, that is, at the beginning
and end of the time interval.
Subscripts Band D indicate the direction of the transitions and/or the final states or levels of the signals represented
by A and C, respectively. One or two of the following is used:
H
L
V
X
Z
= high or transition to high
= low or transition to low
= a valid steady-state level
= unknown, changing, or "don't care" level
= high-impedance (off) state.
The hyphen between the Band C subscripts is omitted when no confusion is likely to occur. For these letter symbols
on this data sheet, the signal names are further abbreviated as follows:
SIGNAL
AorC
NAME
SUBSCRIPT
BUSY
HOi])
B
0
S
A
Y
C
R
Q
RAS
AO - A7
READY
LATCHED RCa
RESET LATCHED RCa
REF REQ
2-1012
TEXAS . "
INSTRUMENTS
POST OFFICE B"-X 655012 • DALLAS. TEXAS 75265
SN74LS600A. SN74LS601A. SN74LS603A
MEMORY REFRESH CONTROLLERS
TIMING DIAGRAMS
I-
REF REQIQ)
\'----!------t
----'1--1- tQHBL
tSLBH
BUSYIB)
1
1
,-
:
"
-------tr
r--tQHSV--t
RASIS)
I.
L
AO-A7IAJ
J
tSL_S_H_-.---,_",\ ~___
tQHAV-r-----!
X
----~D
tSHAZ~
X,-__D--
FIGURE 1 - TRANSPARENT REFRESH
----..J,r----------..,
Il--o------tYLYL -------t1
r
READYIY) \ ' -_ _
-n
tQHQL
REF REQIQ)
---r=:"1
I
:\
I
tQHSV ~ .
RASIS)
•
CI)
1
BUSYIB)
0.. . ___
!
--1
I
\'-__
!--tSHYH
----~~-------------~
CI)
(.)
'S;;
CI)
C
..J
l-
I-
AO-A7IA) - - - - - {
FIGURE 2 - CYCLE STEAL REFRESH
tDHDL----------t-1 ~_ _ _ __
10
I
HOLDID)\
MCPU RESPONSE TIME'
REF REQIQ)
BUSYIB)
I
\'-____
,~,------~
\~---------_--------~I
RASIS)~
AO-A7IA)
----CY--x: :=x--><=>---
LATCHED
RCOIC) _ _ _ _ _ _ _ _ _ _ _ _-1
--t
i--tRHCL
I
~------.J
1-'---
R~~I~ -------------III-r--------...I'L
it
During testing. an 'LS04 is used to invert HOLD to provide the REF REO input.
FIGURE 3 - BURST MODE REFRESH
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1013
SN74lS600A, SN74lS601A, SN74lS603A
MEMORY REFRESH CONTROllERS
TYPICAL CHARACTERISTICS
PULSE DURATION, RAS LOW
vs
EXTERNAL TIMING RESISTOR
CYCLE STEAL REFRESH CYCLE TIME
vs
EXTERNAL TIMING RESISTOR
500
.. 100
l!!
~
..E
..
u
j.:
400
..J
I~a:
c
u>
E
't
300
.~
o"
9!
:;
a:
50
AI
/
I
j,
20
/
)<
10
a
200
..
~C
= 0.01 /IF
C = 0.005 /IF
C = 0.001 /IF
I-C = 500 pF
(I)
u
5
/
>
I
I
..J
>
..J
~
2
~
1
0
1
<
2
3
4
5
Rext-Timing Resistor-kn
C:;"
6
/
V
1/
U
:t:
~ 100
C
(I)
/
IV
iii
CL
-t
-t
r-
VCC=5V
TA = 25°C
T-
VCC=5V
TA = 25°C
/
V
IIIII
V
1
10
100
Rext-Timing Resistor-kn
1000
FIGURE4
FIGURE 5
PULSE DURATION, RAS HIGH
vs
EXTERNAL TIMING RESISTOR
PULSE DURATION, BURST REFRESH
vs
EXTERNAL TIMING RESISTOR
(I)
en
.
6.---.----.----.----.---.----.
500
VCC=5V
TA = 25°C
c
1
.2'
400
:t:
(I)
:
(!)
The SN54LS604, SN54LS606, and SN54LS607 are characterized for operation over the full military temperature range
of - 55 °e to 125 °e; the SN74LS604, SN74LS606, and SN74LS607 are characterized for operation from 0°e to 70 o e.
FUNCTION TABLE
INPUTS
OUTPUTS
Al-A8
Bl-B8
A data
B data
L
A data
B data
H
X
X
X
L
X
X
L
H
B register stored data
X
H
H
A register stored data
X
H
=
SELECT AlB
high level (steady state I
CLOCK
Yl-Y8
t
t
B data
AdetB
Z or Off
L = low level (steady state)
Z
X = irrelevant
= high-impedance state
Off = H if pull-up resistor is connected to open-collector output
t
= transistion from low to high level
PRODUCTION DATA d.cumonls c.ntoin inf.rmlli.n
cumnt 8S of pull.ieltian data. Products conform to
specifications per the terms of Tax.I
Instruments
:':~:~~i;8i~:1~1i ~!:g::i:; :'r'::::::.:~~s not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-1015
SN54LS604, SN54LS606, SN54LS607, SN74LS604, SN74LS606, SN74LS607
OCTAL 2·INPUT MULTIPLEXED LATCHES
sch~matics
of inputs and outputs
EQUIVALENT OF A AND B INPUTS
EQUIVALENT OF CLOCK INPUTS
VCC
VCC--......- 22kSl
NOM
_>-
EQUIVALENT OF SELECT INPUTS
4kSl
NOM
INPUT_-lII-.......
INPUT
TYPICAL OF ALL OUTPUTS
('LS604, 'LS606)
TYPICAL OF ALL OUTPUTS
('lS607)
•
__ ~OUTPUT
-I
-I
r0-
C
CD
<
n·
CD
logic symbols t
en
'lS604
'lS606
'lS607
elK
Vl
Vl
V2
V2
V3
V3
V4
V4
(16) V5
125Jl-----I
(17)
V5
V6
V6
(lS) V7
-mn----~
(19)
V7
VS
VS
tThese symbols ~re in accordance with ANSI/IEEE Std. 91-1984 and )EC Publication 617-12.
Pin numbers shown are for JD a.nd N packages.
2-1016
TEXAS •
INSTRUMENTS
POST OFFICE BOX 6550i 2 • DALLAS. TEXAS 75265
SN54LS604. SN54LS606. SN54LS607. SN74LS604. SN74LS606. SN74LS607
OCTAL 2·INPUT MULTIPLEXED LATCHES
logic diagram (positive logic)
SELECT 121
AlB
CLOCK 111
Bl
Al
B2
A2
B3
A3
141
13)
1151
VI
16)
151
1131
V2
181
171
1121
V3
B4 !101
•
til
Cl)
A4
CJ
191
1111
V4
'S
Cl)
85
A5
86
A6
B7
A7
B8
A8
C
1261
..J
1271
1161
V5
~
~
1241
1251
1171
V6
1221
1231
1181
V7
1201
1211
1191
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
VB
2·1017
SN54LS604, SN54LS606, SN74LS604, SN74LS606
OCTAL 2·INPUTMULTIPLEXED LATCHES WITH 3·STATE OUTPUTS
recommended operating conditions
MIN
4.5
Supply voltage, Vrr (see Note 1)
High-level output current, In .....
Low-level output current, InL
Width of clock pulse. tw
SN54LS604
SN54LS606
NOM
MAX
5
5.5
-1
12
20
Setup time, tsu
Hold time, th
201
01
-55
Operating free-air temperature, T A
125
SN74LS604
SN74LS606
UNIT
MIN
NOM
MAX
4.75
5
5.25
V
-2.6 mA
24 mA
ns
20
201
ns
ot
ns
0
70 °c
NOTE 1: Voltage values are with respect to network ground terminal.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
-4
-4
,...
V'L
High-level input voltage
V
VII<"
Input clamp voltage
VOH
High-level output voltage
(I)
<
,;"
(I)
Low-level input voltage
Low-level output voltage
VOL
10ZH
C
TEST CONDITIONSt
10Zl
Off-state output current,
high-level voltage applied
Off-state output current,
low-level voltage applied
Input current at
II
maximum input voltage
Vrr= MIN,
VCC=MIN,
VIL = VIL max,
VCC- MIN,
Vll = Vll max,
VCC=MAX,
Vll = Vll max,
VCC-MAX,
Vll = Vll max,
I =-18mA
VIH =2 V,
10H=MAX
VIH = 2 V,
SN54LS604
SN54LS606
MIN TYpt
MAX
2
0.7
-1.5
2.4
3.1
0.25
10l = 12mA
10l - 24mA
VIH = 2 V,
VO=2.7V
VIH = 2V,
Vo = 0.4
VCC= MAX,
VI =7 V
t/)
IIH
High-level input current
VCC= MAX,
VI = 2.7 V
III
Low-level input current
VCC=MAX,
VI =0.4V
lOS
~Cr~~f~~~;~nt §
VCC=MAX
ICC
Supply c.urrent
VCC=MAX,
A,B
ClK,SElECT
A.B
ClK,SElECT
A, B
ClK SELECT
-30
See Note 2
55
SN74LS604
SN74LS606
UNIT
MIN TYPt
MAX
V
2
0.8
V
-1.5
V
3.1
2.4
0.4
0.25
0.35
V
0.4
0.5
V
20
20
/lA
-20
-20
/lA
0.1
0.1
20
20
-0.4
0.2
-130
0.1
0.1
20
20
0.4
0.2
-130
-30
70
55
70
mA
/lA
mA
mA
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:tAli typical values are at
Vee = 5
V, T A
=
25°C.
§ Note more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2:
ICC is tested with atl inputs grounded and all outputs open.
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER
tPLH
tPHl
tPlH
tPH
tpZH
tpZl
tpHZ
tplZ
tpLH
tpH L
tpZH
tpZL
tpHZ
tpLZ
FROM
(INPUT)
Select ATB
(Oata: A = H, B = l)
Select AiB
(Oata: A = l, B = H)
TroST CONDITIONS
Cl =45pF,
MIN
Rl=667!l,
See Note 3
Clock
Clock
Cl - 5 pF,
Rl-667!l,
See Note 3
propagation delay time, low-to-hlgh-fevel output
propagation delay time, low-to-high-Ievel output
outPut enable time to high level
outPut enable time to low level
output disable time from high level
output disable time from low level
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2-1018
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
'LS604
TYP
MAX
15
25
23
35
31
45
30
19
30
19
40
28
20
30
15
25
MIN
'LS606
TYP
36
16
22
22
27
35
20
15
MAX
50
30
35
35
40
50
30
25
UNIT
ns
ns
ns
ns
SN54LS607, SN74LS607
OCTAL 2-INPUT MULTIPLEXED LATCHES WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN54LS607
MIN
NOM
4,5
5
Supply voltage, V CC (see Note 1 )
High-level output voltage, VOH
NOM
MAX
5.5
4.75
5
5.25
V
5.5
V
24
mA
12
tw
Setup time, tsu
Hold time, th
Operating free-air temperature, T A
UNIT
MIN
5.5
Low-level output current, IOl
Width of clock pulse,
SN74LS607
MAX
20
20
ns
20t
20t
ns
at
ot
-55
125
ns
a
70
'c
NOTE1: Voltage values are with respect to network ground terminal.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
VIH
High-level input voltage
Vil
Low-level input voltage
VIK
Input clamp voltage
IOH
High-level output current
VCC= MIN,
II =-18mA
VCC= MIN,
VIH =2V,
Vil = Vil max,
VOH=5.5V
VCC=MIN,
VIH = 2 V,
MAX
MIN
VCC= MAX,
maximum input voltage
IIH
High-level input current
VCC=MAX,
VI=2.7V
III
Low-level input current
VCC= MAX,
VI=O.4V
ICC
Supply current
VCC= MAX,
See Note 2
UNIT
MAX
V
0.7
0.8
V
en
-1.5
-1.5
V
(,)
250
IJ-A
250
0.4
10l = 24 mA
VI =7V
TYP~
2
0.25
IOl = 12 mA
Vil = Vil max
Input current at
II
TYP~
2
Low-level output voltage
VOL
SN74LS607
SN54LS607
TEST CONDITIONSt
A, B
0.1
ClK, SELECT
0.25
0.4
0.35
0.5
0.1
0.1
0,1
A,B
20
20
ClK,SElECT
20
20
A, B
-0.4
-0.4
ClK,SElECT
-0.2
-0.2
40
40
60
60
V
mA
Q)
-S;
Q)
C
..J
lI-
IJ-A
mA
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at VCC
NOTE 2:
=5
V, T A = 25°C.
ICC is tested with all inputs grounded and all outputs open.
switching characteristics. Vee
PARAMETER
tpLH
tpHL
tpLH
tpHL
tpLH
=
5 V. TA _25°e
FROM
TEST CONDITIONS
(INPUT)
Select AlB
(Data: A
=
H, B
=
L)
Select AlB
(Data: A
=
L, B
CL
=
H)
= 45
pF,
RL
=
667 II,
See Note 3
Clock
tpHL
'LS607
MIN
TYP
MAX
51
70
21
30
28
40
28
40
30
45
32
45
UNIT
ns
ns
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1019
-I
-I
rC
CD
5.
(')
CD
en
2-1020
SN54LS610, SN54LS612, SN7 4LS61 0 THRU 74LS613
MEMORY MAPPERS
D2549, JANUARY 1981-REVISED MARCH 1988
•
Expands 4 Address Lines to 12 Address
Lines
•
Designed for Paged Memory Mapping
•
Output Latches Provided on 'LS610 and
'LS611
•
Choice of 3-State or Open-Collector Map
Outputs
SN54LS' .. , JD PACKAGE
SN74LS' , . , JD OR N PACKAGE
ITOP VIEW)
•
RS2
MA3
RS3
CS
STROBE
Riiiii
Compatible with TMS9900 and Other
Microprocessors
OAOA{
BUS 1/0
DEVICE
OUTPUTS
LATCHED
D4
D5
MM
MAP
OUTPUT TVPE
'LS610
Ves
3-State
'LS611
Ves
Open-Collector
'LS612
No
3-State
'LS613
No
Open-Collector
DO
D1
D2
D3
fDO
M01
MAP
OUTPUTS
description
Each 'LS610 through 'LS613 memory-mapper
integrated circuit contains a 4-line to 16-line
decoder, a 16-word by 12-bit RAM, 16 channels
of 2-line to 1-line multiplexers, and other
miscellaneous circuitry on a monolithic chip,
Each 'LS610 and 'LS611 also contains 12
latches with an enable control.
M02
M03
M04
M05
GND
VCC
MA2
RS1
MA1
RSO
MAO
D11
D10
D9
DB
}DAOA
BUS 110
D7
D6
C (NC)t
MD"}
M010
M09
MOB
M07
M06
MAP
OUTPUTS
III
Q)
(.)
':;
Q)
ME
C
tThis pin has no internal connection on 'LS612 and 'LS613
...I
lI-
The memory mappers are designed to expand a
microprocessor's memory address capability by
eight bits, Four bits of the memory address bus
(see System Block Diagram) can be used to
select one of 16 map registers that contain 12
bits each, These 1 2 bits are presented to the
system memory address bus through the map
output buffers along with the unused memory
address bits from the CPU, However,
addressable memory space without reloading the
map registers is the same as would be available
with the memory mapper left out, The
addressable memory space is increased only by
periodically reloading the map registers from the
data bus, This configuration lends itself to
memory utilization of 16 pages of 2(n -4)
registers each without reloading (n = number of
address bits available from CPU).
PRODUCTIOI DATA d......ots ••otai. i.lan.oli••
currlnt II af publicatian dati. Pr.ducts cDnfarm to
IplCifiCitioll1 p. the term. of Till. IAstruments
::=~:O:-;.':I~t,Ja ~:~~~; =::~::.s
..
t
Copyright © 19B1. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-1021
SN54LS610, SN54LS612, SN74LS610THRU SN74LS613
MEMORY MAPPERS
MEMORY ADDRESS BUS
SYSTEM
CPU
DATA AND CONTROL BUS
SYSTEM BLOCK DIAGRAM
These devices have four modes of operation: read, write, map, and pass. Data may be read from or loaded
into the map register selected by the register select inputs (RSO thru RS3) under control of R/W whenever
chip select (CS) is low. The data 1/0 takes place on the data bus DO thru 07. The map operation will output
the contents of the map register selected by the map address inputs (MAO thru MA3) when CS is high
and MM (map mode control) is low. The 'LS612 and 'LS613 output stages are transparent in this mode,
while the 'LS610 and 'LS611 outputs may be transparent or latched. When CS and MM are both high
(pass mode), the address bits on MAO thru MA3 appear at MOS-M011, respectively, (assuming appropriate
latch control) with low levels in the other bit positions on the map outputs.
-I
-I
r-
C
logic diagram (positive logic)
CD
<
C:;"
C
(INTERNAL) ALL a LOW FOR MO()'M07 - - / - - - - ,
(II
ME
I
a
CD
ONLY
'LS610
I
I
LATCH
I
~~~:11 !
4
I
I
I
RAM 16X12
°
O).Ai5
"3
r---'
L../Cl
I
I
I
~---
VCC
2Z
2Y
2CXl
2CX2
2FC
20SC VCC
20SC GND
lOSC VCC
lOSC GND
crCD
N
t:l
U
U
>
SN64LS625 ... FK PACKAGE
(TOP VIEW)
C
U
~i3~~~
3 2
CD
<
C U
Z Z
SN54LS626 ... J OR W PACKAGE
SN74LS626 ... 0 OR N PACKAGE
(TOPVlI:WI
III
GND
lZ
lY
lEN
lCXl
VCC
2Z
2Y
2EN
2CXl
2CX2
2FC
lFC
UU
t:l
UU
N
~l3uuo
321
NC
2CX1
NC
2CX2
""'---~
SN54LS628 ... J OR W PACKAGE
SN74LS628 ..• 0 OR N PACKAGE
(TOP VIEW}
OSC GND
U
!1
1
9 10111213
>OU>O
-ZZNZ
OSC VCC
FC
RX
Cl
Cl
U
l3
N
NC
en
Vee
SN54LS628 •.. FK PACKAGE
z
""'-_--'r-
(TOP VIEW}
c
Z
SN54LS629 •.. J OR W PACKAGE
SN74LS629 •.. 0 OR N PACKAGE
Cl
ClU
IY
ose GND
NC~No
C
U
...J
lI-
3 2
VCC
OSC VCC
2RNG
2CXl
2CX2
2EN
2Y
GND
CX1
CJ
.S;
Q)
U
>
ZCIlUCilU
a::OZOIL
(TOP VIEW}
IFC
IRNG
ICXI
ICX2
U
Q)
RK
4
5
NC
RX
NC
NC
6
9 1011 1213
>
C
U N
ZZ
Cl
U
U
>
internal connection
SN54LS629 ... FK PACKAGE
(TOP VIEW}
IRNG
ICX1
NC
ICX2
4
5
6
7
2EN
8
>CUO>
-ZZZN
Cl
U
Cl
l3
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1039
SN54LS624 THRU SN54LS629.
SN74LS624 THRU SN74LS629
VOL TAGE·CONTROLLED OSCILLATORS
logic diagram (positive logic)
cx{:---_*--I
FC
l----Z
_ _ _---jL--!FC
RC
('LS624,
'LS628,
'LS629 only)
-t
-t
~.-...- y
logic symbols t
r-
'LS626
'LS625
'LS624
0
CD
OSCVCC
n
en
(141
~.
EN
RNG
FC
CXl
(6)
(8)
CX2
OSCGND
lY
lOse VCC
10SCGND
lFC
CD
Y
Z
lZ
lCXl
lCX2
lEN
1Y
lFC
lCXl
lZ
lCX2
20SC VCC
20SC GNO
2Y
2Y
2FC
2CXl
2Z
2Z
2CX2
OSCGND
'LS627
'LS629
'LS628
OSC VCC
(14)
10seVCC
10seGND
lFC
lY
EN
lCX.l
lCX2
RNG
20seVCC
20SCGND
2FC
CX2
RX
2CX1
2CX2
(6)
FC
CX1
(8)
Y
Z
RX
lEN
1 RNG
1 FC
1Y
2EN
2 RNG
2 FC
2CXl
2CX2
OSCGND
OSCGND
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12.
Pin numbers shown are for 0, J, N, and W packages.
2-1040
•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
SN54LS624 THRU SN54LS629,
SN74LS624 THRU SN74LS629
VOLTAGE-CONTROLLED OSCILLATORS
schematics of inputs and outputs
EQUIVALENT OF EACH
ENABLE INPUT
('LS624, 'LS626, 'LS62B, AND 'LS629)
EQUIVALENT OF EACH FREQUENCY
CONTROL OR ('LS624, 'LS628, AND 'LS629)
RANGE INPUT.
TYPICAL OF ALL OUTPUTS
--------~.--Vee
Vee
Vee
25 kn
NOM
9kn NOM
70 kn
NOM
INPUT
OUTPUT
INPUT
20 kn
NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Notes 1 and 2)
Input voltage: Enable input t
Frequency control or range input t
Operating free-air temperature range: SN54LS' Circuits
SN74LS' Circuits
Storage temperatu re range
CI)
. 7V
. 7V
VCC
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
t The enable input is provided only on the 'LS624, 'LS626, 'LS628, and 'LS629.
t The range input is provided onlv on
NOTE:
'LS624, 'LS628, and 'LS629.
Q)
(.)
'S;
Q)
C
...J
lI-
1. Voltage values are with respect to the appropriate ground terminal.
2. Throughout the data sheet, the symbol Vee is used for the voltage applied to both the Vee and OSC Vee terminals, unless
otherwise noted.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-1041
SN54LS624 THRU SN54LS629,
SN74LS624 THRU SN74LS629
VOL TAGE·CONTROLLED OSCILLATORS
recommended operating conditions
SN54LS'
Supply voitage, Vee
SN74LS'
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
5
0
0
Input voltage at frequency control or range input, Vl(freq) or Vl(rng)'
High-level output current, IOH
5
-1.2
Low-level output current, IOL
12
-55
125
V
mA
24
mA
20
MHz
70
°e
Hz
20
Operating free-air temperature, TA
V
-1.2
1
1
Output frequency, fa
UNIT
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST eONDITIONSt
SN54LS'
MIN TYPt
High-level input
VIH
SN74LS'
MAX
2
voltage at enable'
MIN TYPt
MAX
2
UNIT
V
Low-level input
VIL
VIK
VOH
VOL
II
voltage at enable#
Input clamp voltage at enable# Vee = MIN,
High-level output voltage
Low-level output voltage
Input current
Freq control
or range'
II =-18mA
EN at VIL
Vee-MIN,
max,
10H = -1.2 mA, See Note 3
Vee= MIN,
2.5
10L= 12mA
EN at V,L max,
See Note 3
0.8
V
-1.5
V
3.4
2.7
V
3.4
a4
0.25
0.4
0.35
0.5
50
250
50
250
10
50
10
50
0.25
10L = 24 mA
VI 5V
VI-I V
Vee= MAX
0.7
-1.5
V
)LA
Input current
II
at maximum
input voltage
High-level
IIH
input current
Low-level
IlL
lOS
input current
Enable N
Vee= MAX,
VI = 7V
0.2
0.2
mA
Enable#
Vee = MAX,
VI=2.7V
40
40
I'A
Enable'
Vee= MAX,
VI=O.4V
-0.8
-0.8
mA
-225
mA
Short-circuit output current §
Supply current, total into
lee
Vee and ose Vee pins
-40
Vee= MAX
Vee
= MAX,
= 4.5 V
Enable N
See Note 4
-225
'LS624
20
35
-40
20
35
'LS625
35
55
35
55
'LS626
35
55
35
55
'LS627
55
35
55
'LS628
35
20
35
20
35
'LS629
35
55
35
55
mA
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, TA = 25°e.
§Not more than one output should be shorted at a time and duration 'of the shortwcircuit should not exceed one second.
hhe range input is provided only on the 'LS624, 'LS628, and 'LS629.
#The enable input is provided only on the 'LS624, 'LS626, 'LS628, and 'LS629.
NOTES: 3. VOH for Y outputs and VOL for Z outputs are measured while enable inputs are at VIL MAX, with individual 1 ~kD resistors
connected from eXl to Vee and from CX2 to ground. The resistor connections are reversed for testing VOH for Z outputs
and VOL for Y inputs.
4. For 'LS624, 'LS626, 'LS628, and 'LS629, lee is measured with the outputs disabled and open. For 'LS625 and 'LS627,
lee is measured with one ose Vee = MAX, and with the other ose Vee and outputs open.
2-1042
TEXAS .."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS624 THRU SN54LS629,
SN14LS624 THRU SN14LS629
VOLTAGE·CONTROLLED OSCILLATORS
switching characteristics, VCC = 5 V (unless otherwise noted), R L = 667
PARAMETER
fa
TEST CONDITIONS
Output frequency
Cext
= 50 pF
n, CL = 45 pF, T A
'LS624, 'LS628, 'LS629
MIN
= 5 v, VI(rng) = 0 V
= 1 v, Vl(rng) = 5 V
Vl(freq) = 5 V
Vl(freq) = 0 V
TYP
MAX
Vl(freq)
15
20
25
Vl(freq)
1.1
1.6
2,1
= 25°C
'LS625, 'LS626, 'LS627
MIN
TYP
7
9,5
12
0.9
1.2
1.5
MAX
UNIT
MHz
TYPICAL CHARACTERISTICS
'LS624,'LS628,'LS629
'LS624, 'LS628, 'LS629
OUTPUT FREQUENCY
vs
FREQUENCY·CONTROL INPUT VOLTAGEt
OUTPUT FREQUENCY
vs
FREQUENCY·CONTROL INPUT VOLTAGEt
30
VCC = 5 V
Cext = 50 pF
Rext = 600 n ('LS628)
TA=25°C
N
::c 25
:2
~ 25
::;;;
I
~20~~--~~--~~--~~--
>20~4-~--4--4--
c:
"c:
:J
:J
'"
Q)
g 15~~--~~--~~--~~--~~~
.t
u:g15~~--~~--~~-~~
~
~
:J
:J
%10~~--~~--~~~~~~~
%10~~--~~~~-b~~
a
a
"
..P
OC=~-L~L-~-L~
__L--L~~
o
2
3
4
5
Vl(freq) - Frequency·Control Input Voltage - V
1
2
.3
VI (freq) - Frequency·Control Input Voltage - V
FIGURE 1
FIGURE 2
tDue to the effects of stray capacitance the output frequency may be unstable when the frequency
control voltage is less than 1 volt.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
2-1043
SN54LS624 THRU SN54LS629.
SN14LS624 THRU SN14LS629
VOLTAGE·CONTROLLED OSCILLATORS
TYPICAL CHARACTERISTICS
'LS624, 'LS628, 'LS629
'LS625,'LS626,'LS627
OUTPUT FREQUENCY
OUTPUT FREQUENCY
vs
vs
EXTERNAL CAPACITANCE
FREQUENCY-CONTROL INPUT VOLTAGE t
100 M r - - - r - - - - . - - - - , - - - r - - - . - - - - - - ,
10
VCC=5V
J: 10M I--.,..-...p....,--t--+-----l- T A = 25°C
I
~
lMI-"""'d---"o..:-t"""",
N
9
N
V
,8 r-TA = 25°C
J:
:E
/
1 7
~
iii
~ 100 KI---t---"cl-
u.
S
V~C';5VI
I- Cext = 50 pf
iii 6
g 5
:::l
10 k I--+--t----'''-.:
a-
d
u:
S 4
a-
1 k I--+--t--+-"""",
I
d
100 f---+--+--+---+-~
.2
-I
-I
r-
10~-+--1_-_+_-_+-_1~~
C
10-11 10-10 10-9
./
.2
V
/
V
V
o
o
lL-_l-_~_-L_~_~_~
10-8
V
3
1 2
V
1/
/
10-7 10-6 10-5
CD
Cext - External Capacitance - F
5
2
3
4
VI(freq) - Frequency-Control Input Voltage - V
n'
CD
FIGURE3
FIGURE 4
<
VI
25
:E
'LS625, 'LS626, 'LS627
OUTPUT FREQUENCY
OUTPUT FREQUENCY
vs
vs
FREQUENCY-CONTROL INPUT VOLTAGE
EXTERNAL CAPACITANCE
30
~
'LS625, 'LS626, 'LS627
100 M ,----r----.------y--r---,-----,
~CC ~ 5 ~
10 M ~::".".+_-_+_---+--+_-1_--l
_ Cext= 15pF
TA = 25°C
N
'I
>20
g
'"
/
:::l
~15
u.
...
:::l
./
~10
o
1
.2 5
/'
,/
/'
./
J:
/
11M
~
iii lOOk
:::l
0-
,/
f-----l-~~~~~--+----+--4
J:
...
10k f---+--+---"'..t--:~'_d_---+,__-4
~
1 k f---+--+--~+_~'_d_~~f---4
:::l
o
~
I
100~-__l_-_+_---+--+_~~~~
.2
,/'
o
o,
f--~d___=~'4----+--+----l---l
10
1L-_~
4
3
5
VI(freq) - Frequency-Control Input Voltage - V
2
_ _ L ___L_~_~_ _~
10-11 10-10 10-9 10-8 10-7
FIGURE 5
10-6
10-5
Cext - External Capacitance - F
FIGURE 6
t Due to the effects of stray capacitance the output frequency may be unstable when the frequency control voltage is less than 1 volt.
2-1044
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS624 THRU SN54LS629,
SN74LS624 THRU SN74LS629
VOL TAGE·CONTROLLED OSCILLATORS
TYPICAL CHARACTERISTICS
ENABLE TIME
vs
FREQUENCY
1000
VCC 5V
TA - 25°C
~
c:
I
"-
'"
E
i=
'"
:0
'"c:
100
w
I
i'-...
=
_1.33V~
V --OV---
c:
$
~
-
-+j [-ten
-1.3~=l..JlJ
10
1
4
10
20
40
2
fo - Output Frequency - MHz
100
FIGURE 7
TYPICAL APPLICATIONS DATA
Cext
C ext
H§
H§
FREO
CONT
VCO
Y
RNGt
EN*
L
FREO
CONT
VCO
tRNG
EN*
1
t The range input is provided only on the 'lS624, 'LS628, and 'LS629.
I The enable input is provided only on the 'LS624, 'LS626, 'LS628, and 'LS629.
§ Input voltages may be variable (analog) depending upon application.
L
FIGURE A-PHASE·LOCKED LOOP.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·1045
-I
-I
r-
C
(1)
<
(")
(1)
CIJ
2-1046
SN54LS630, SN74LS630
16-81T PARALLEL ERROR DETECTION
AND CORRECTION CIRCUITS
D2550. MARCH 1980-REVISED MARCH 1988
(TIM99630)
•
Detects and Corrects Single-Bit Errors
5N54L5630, ... JO PACKAGE
5N74L5630 ... N PACKAGE
• Detects and Flags Dual-Bit Errors
•
•
(TOP VIEWI
Fast Processing Times:
Write Cycle: Generates Check Word in
46 ns Typical
Read Cycle: Flags Errors in Xl ns Typical
Vcc
SEF
DB1
DB2
DB3
Power Dissipation 600 mW Typical
S1
SO
The 'LS630 device is a 16-bit parallel error detection
and correction circuit (EDAC) in a 28-pin. 600-mil
package. It uses a modified Hamming code to generate
a 6-bit check word from a 16-bit data word. This
check word is stored along with the data word during
the memory write cycle. During the memory read
cycle. the 22-bit words from memory are processed
by the EDAC to determine if errors have occurred in
J
~:! }
DATA
BITS
description
\ CONTROL
CHECK
CB3
CB4
CB5
DBB
DB9
~:~:}
DB13
'--L_ _
-'~
BITS
DATA
BITS
DB12
ell
Q)
5N54L5630 ... FK PACKAGE
memory.
.~
(TOP VIEWI
>
Q)
Single-bit errors in the 16-bit data word are flagged and
corrected.
C
4
Single-bit errors in the 6-bit check word are flagged. and
the CPU sends the EDAC through the correction cycle
even though the 16-bit word is not in error. The correction cycle will simply pass along the original 16-bit word
in this case and produce error syndrome bits to pinpoint
the error-generating location.
Dual-bit errors are flagged but not corrected. These dual
errors may occur in any two bits of the 22-bit word from
memory (two errors in the 16-bit data word, two errors
in the 6-bit check word, or one error in each word),
3
2
..J
1 28 2726
lI-
12131415161718
o
OC'\lMo:::t~
~~i3~~i5~
The gross-error condition of all lows or all highs from
memory will be detected. Dtherwise, errors in three or
more bits of the 22-bit word are beyond the capabilities
of these devices to detect.
CONTROL FUNCTION TABLE
Memory
Control
EDAC FUnction
Data 1/0
Check Word 1/0
Error Flags
I
I
Cycle
51
SO
WRITE
L
L
Generate Check Word
Input Data
Output Check Word
L
READ
L
H
Re~d
Input Data
Input Check Word
L
READ
H
H
Latch & Flag Errors
Latch Data
Latch Check Word
Enabled
READ
H
L
Output Corrected Data
Output Syndrome Bits
Enabled
Data & Check Word
Correct Data Word &
Generate Syndrome Bits
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
:~~~~:~~i~ar::I~~i ~!:~::i:; lI~o::;:~:,:~~s not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
SEF
OEF
T
L
L
2-1047
SN54LS630, SN74LS630
16·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
functional block diagram
Si
so
FUNCTIO
SELECTO
S1
AA
SO·S1
SO·S1
!
~
6
r - r.-~
~C
CHECK BIT I/~~
CBO THRU CBS
4- I--
•
PARITY
GENERATOR
I
OE
ERROR
DETECTOR
12
6/
BUFFER
12
,
OE
r--
r.-
---+ SEF
---+ DEF
12
,
16~
LATCH
~ C
-4
-4
OATA BIT I
IOj~
DBOTHRUD B1S
16
r-
C
CD
4--
<
C:r
16
BUFFER
ERROR
CORRECTOR
~
ERROR
DECODER
OE
CD
en
ERROR FUNCTION TABLE
Error Rags
Total NUmber of Errors
16-8it Oat.
6·Bit Chackword
SEF
DEF
Data Correction
0
0
L
L
Not Applicable
1
0
H
L
Correction
0
1
H
L
Correction
1
1
H
H
Interrupt
2
0
2
H
H
Interrupt
H
H
Interrupt
0
In order to be able to determine whether the data from the memory is acceptable to use as presented to the bus, the
EDAC must be strobed to enable the error flags and the flags will have to be tested for the zero condition.
The first case in the error function table represents the normal, no--arror co~dition. The CPU sees lows on both flags.
The next two cases of single-bit errors require data correction. Although the EDAC can discern the single check bit
error and ignore it, the error flags are identical to the single error in the 16-bit data word. The CPU will ask for data
correction in both cases. An interrupt condition to the CPU results in each of the last three cases, where dual errors
occur,
error detection and correction details
During a memory write cycle, six check bits (CBO-CB5) are generated by eight-input parity generators using the data
bits as defined below. During a memory read cycle, the 6-bit check word is retrieved along with the actual data.
2-1048
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS630. SN74LS630
16-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
CHECKWORD
16·BIT DATA WORD
BIT
0
1
CBO
x
x
x
CBl
CB2
CB3
x
x
x
CB4
2
x
x
x
3
4
x
x
x
x
x
x
5
x
x
x
6
7
x
x
x
CBS
8
9
10
x
x
x
x
x
x
x
11
13
x
x
14
15
x
x
x
x
x
x
x
x
x
x
x
12
x
x
x
x
x
x
x
The six check bits are parity bits derived from the matrix of data bits as Indicated by "x" for each bit.
Error detection is accomplished as the 6·bit check word and the 16·bit data word from memory are applied to internal
parity generators/checkers. If the parity of all six groupings of data and check bits are correct, it is assumed that no
error has occurred and both error flags will be low. (It should be noted that the sense of two of the check bits, bits CBO
and CB1, is inverted to ensure that the gross·error condition of all lows and all highs is detected.)
If the parity of one or more of the check groups is incorrect, an error has occurred and the proper error flag or flags will
be set high. Any single error in the 16·bit data word will change the sense of exactly three bits of the 6·bit check word.
Any single error in the 6·bit check word changes the sense of only that one bit. In either case, the single error flag will
be set high while the dual error flag will remain low.
Any two·bit error will change the sense of an even number of check bits. The two·bit error is not correctable since the
parity tree can only identify single·bit errors. Both error flags are set high when any two-bit error is detected.
Three or more simultaneous bit errors can fool the EDAC into believing that no error, a correctable error, or an uncor·
rectable error has occurred and produce erroneous results in all three cases.
Error correction is accomplished by identifying the bad bit and inverting it. Identification of the erroneous bit is
achieved by comparing the 16·bit data word and 6·bit check word from memory with the new check word with one
(check word error) or three (data word error) inverted bits.
As the corrected word is made available on the data word I/O port, the check word I/O port presents a 6·bit syndrome
error code. This syndrome code can be used to identify the bad memory chip.
ERROR SYNDROME TABLE
ERROR LOCATION
OBO
OBI
OB2
OB3
0B4
OBS
OBS
OB7
OBS
OB9
OB10
OBll
OB12
OB13
OB14
OB15
CBO
CBl
CB2
CB3
CB4
CBS
NO ERROR
CBO
L
L
H
L
L
H
H
H
L
L
L
H
H
L
H
H
L
H
H
H
H
H
H
CBl
L
H
L
L
H
L
L
H
L
H
H
L
H
H
L
H
H
L
H
H
H
H
H
SYNDROME ERROR CODE
CB4
CB3
CB2
H
H
L
H
L
L
H
L
L
H
L
H
H
L
L
L
L
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
L
H
H
L
H
L
L
H
H
L
H
H
L
H
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
TEXAS . "
INSTRUMENTS
POST OFFICE. BOX 665012 • DALLAS, TEXAS 75265
CB5
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
L
H
2-1049
SN54LS630, SN14LS630
. .
16-81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
schematics of inputs and outputs
EaUIVALENT OF EACH INPUT
VCC
TYPICAL OF DEF AND SEF OUTPUTS
.
TYPICAL OF CB ANO DB
Vec
VCC
INPUT
yW"......-
OUTPUT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
Supply voltage, VCC Isee Note 1)
Input voltage: SO and S 1 ........ .
7V
CB and DB ...................... .
. ................................. 5.5V
Off-state output voltage ....
. .................................. 5.5V
........... , ............. -55°C to 125°C
Operating free-air temperature range: SN54LS630 ...
SN74LS630 ................ , .................... ooC to 70°C
Storage temperature range. . . . .
. ..... , . . . . . . . . . . . . .. - 65°C to 150°C
-I
-I
rC
NOTE 1: Voltage values are with respect to network ground terminal.
CD
<
c:r
CD
recommended operating conditions
en
SN54LS630
VCC
MIN
NOM
4.5
5
Supply voltage
IOH
High-level output· current
VOH
High-level output voltage
IOL
Low-Ip.vel output current
tsu
Setup time
th
Hold time
TA
Operating free-air temperature
CB or DB, 'LS630 only
SN74LS630
MIN
NOM
MAX
5.5
4.75
5
5.25
-1
-1
- 0.4
DEF or SEF
CB or .DB, 'LS631 only
CB or DB
DEF or SEF
- 0.4.
5.5
5.5
12
24
8
4
CB or DB before SIll
15
15
CB or DB before 81 U
45
45
CB or DB after S11
15
15
55
125
0
t This time guarantees the input data and checkword will be latched.
:t This time guarantees the input data and checkword will be latched plus that no glitch will occur on SEF or DEF flags.
t
The upward-pointing arrow indicates a transition from low to high.
2-1050
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
MAX
V
mA
V
mA
ns
ns
70
'c
SN54LS630, SN74LS630
16-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN74LS630
SN54LS630
PARAMETER
VIH
HighMlevel input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
TEST CONDITIONS
VCC = MIN,
VCC - MIN,
CB or DB
DEF or SEF
VIH = 2 V,
Vce = MIN,
Low-level output voltage
VIH = 2 V,
DEF or SEF VIL = VIL max
Off-state output current,
high-level voltage applied
Off-state output current,
IOZL
II
low-level voltage applied
MIN
Vee - MAX,
eB or DB
11- -18mA
-1.5
CB or DB
3.3
2.4
3.2
IOH = -400 ~A
2.5
3.4
2.7
3.4
0.25
Input current at maximum
eB or DB
Vee= MAX,
So or Sl
VIH =4.5 V
0.25
0.4
IOL -24mA
IOL=4mA
0.25
0.4
IOL = 8 mA
Vo - 2.7 V,
Vo = 0.4 V,
SO and Sl at 2 V
input voltage
-
2.4
IOL -12mA
VI = 5.5V
I VI = 7 V
0.8
V
-1.5
V
V
0.4
0.35
0.5
0.25
0.4
0.35
0.5
20
~A
-200
-200
~A
0.1
0.1
0.1
0.1
High-level input current
Vce- MAX,
VI = 2.7 V
20
20
IlL
Low-level input current
Vce - MAX,
VI-O.4V
-0.2
-0.2
IOS§
CB or DB
current
DEF or SEF
Vce = MAX
V
20
IIH
Short-circuit output
UNIT
V
IOH" MAX
SO and Sl at 2 V
Vce = MAX,
TYP* MAX
2
0.7
CB or DB
IOZH
MIN TYP* MAX
2
VIL = VIL min
VOL
t
-30
-130
-30
-130
-20
-100
-20
-100
mA
I/J
~A
Q)
mA
-S
Supply current
All CB and DB pins grounded,
143
230
DEF and SEF open
143
230
Q)
mA
Q
Vee - MAX, so and Sl at 4.5 V,
ICC
CJ
mA
...I
l-
I-
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*" All typical values are at Vee = 5 V, TA = 25°e.
§ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1051
SN54LS630, SN74LS630
16-81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
switching characteristics, Vee
= 5 V, TA = 25°e, eL = 45 pF
PARAMETER
tpLH Propagation delay time, low·to·high-Ievel output t
tPHL Propagation delay time.
tPLH
TO
(OUTPUT)
DB
high-to-Io~-Ievel output t
Propagation delay time, low-to-high-Ievel output;
S1!
tPZH Output enable time to high level §
SOl
CB
SOatO V,
R L = 667
n, See
SEF
See Figure 1
CB, DB
CB,DB
tPHZ Output disable time from high level'
SO!
CB,DB
SO!
CB,DB
'LS630
MIN
S1 atO V,
SOat3 V,
SOl
t
TEST CONDITIONS
DEF
tpZL Output enable time to low level §
tpLZ Output disable time from low level'
•
FROM
(INPUT)
S1 at3 V,
Figure 1
RL=2kO,
RL=6670,
See Figure 2
S1 at 3 V,
RL=6670,
See Figure 1
SI at3 V,
RL =6670,
See Figure 2
S1 at3 V,
RL = 667 n,
See Figure 1
TVP MAX
UNIT
31
65
ns
45
65
ns
27
40
20
30
24
40
ns
30
45
ns
43
65
ns
31
65
ns
ns
t These parameters describe the time intervals taken to generate the check word during the memory write cycle.
t These parameters describe the time intervals taken to flag errors during the memory read cycle.
§ These parameters describe the time intervals taken to correct and output the data word and to generate and output the syndrome error code during the
-I
-I
memory read cycle.
, These parameters describe the time intervals taken to disable the CB and DB buses in preparation for a new data word during the memory read cycle.
r-
C
PARAMETER MEASUREMENT INFORMATION
.CD
<
n'
VCC
CD
=5 V
Rl
Ul
OUTPUT
OF CIRCUIT
~
I
Cl =45pF
FIGURE I-OUTPUT LOAD CIRCUIT
2-1052
FIGURE 2-0UTPUT LOAD CIRCUIT
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS630, SN74LS630
16·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
typical operating sequences
READ, FLAG, AND CORRECT MODE SWITCHING WAVEFORMS
50---------------------,
Sl--------------~
I---tsu-":'-thold ...:
I
DBO-DB15
I
I
I
INPUT DATA WORD
I
OUTPUT CORRECTED DATAWORD
........-ten--"":
~tsut-++-thold ....
CBO-CB5----J{
INPUTCHE~KWORD ~
OUTPUT SYNDROME CODE
I4-ten~
~
i+-ldis-
~, tpd~~________~__~~__--------~\
SEF--------------~----------L~------------V~A~L~I~D~S~E~F~F~LA~G~------~-----________
l4i4------t pd
-----t!,,.----------~~----,-------.......\
t .
details.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS,' TeXAS 75265
See recommended operating conditions for
Q)
.~
DEF--------------~------------~~~-------V~A~L~ID~D~E~F~F~LA~G~------~-------_____
t NOTE: There are two conditions specified for tsu of Data or Checkword before 51
I/)
>
Q)
C
...J
lI-
2-1053
--I
-I
r-
C
(I)
<
n"
(I)
(fI
2-1054
SN54LS636, SN54LS637, SN74LS636, SN74LS637
8-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
02728. APRIL 1983-REVISEO MARCH 1988
SN54LS' .•. J PACKAGE
SN74LS' ••. DW OR N PACKAGE
• Detects and Corrects Single-Bit Errors
(TOP VIEWI
• Detects and Flags Dual-Bit Errors
DEF
DBO
DBl
DB2
DB3
DB4
DB5
DB6
DB7
GND
• Fast Processing Times:
Write Cycle: Generates Check Word in
45 ns Typical
Read Cycle: Flags Errors in Z1 ns
Typical
• Power Dissipation 500 mW Typical
• Choice of Output Configurations:
'LS636 ... 3-State
'LS637 ... Open Collector
Sl
SO
CBO
CBl
CB2
CB3
NC
CB4
•
SN54LS' •.• FK PACKAGE
(TOPVIEWI
3
description
DB2
DB3
DB4
DB5
DB6
The 'LS636 and 'LS637 devices are 8-bit parallel error
detection and correction circuits (EDACs) in 20-pin,
300-mil packages. They use a modified Hamming
code to generate a 5-bit check word from an 8-bit data
word. This check word is stored along with the data
word during the memory write cycle. During the
memory read cycle, the 13-bit words from memory
are processed by the EDACs to determine if errors
have occurred in memory.
2
1 20 19
4
5
6
7
8
9 10111213
NC-No internal connection.
Single-bit errors in the 8-bit data word are flagged and corrected.
Single-bit errors in the 5-bit check word are flagged, and the CPU sends the EDAC through the correction cycle even
though the 8-bit word is not in error. The correction cycle will simply pass along the original 8-bit word in this case
and produce error syndrome bits to pinpoint the error-generating location.
Dual-bit errors are flagged but not corrected. These dual errors may occur in any two bits of the 13-bit word from
memory (two errors in the 8-bit data word, two errors in the 5-bit check word, or one error in each word).
The gross-error condition of all highs from memory will be detected. Otherwise, errors in three or more bits of the
1 3-bit word are beyond the capabilities of these devices to detect.
CONTROL FUNCTION TABLE
MEMORY
CONTROL
EDAC FUNCTION
DATA I/O
CHECK WORD I/O
ERROR FLAGS
CYCLE
S1
SEF
I
DEF
WRITE
L
L
Generate Check Word
Input Data
Output Check Word
L
L
READ
L
H
Read Data & ,Check Word
Input Data
Input Check Word
I
I
READ
H
H
Latch & Flag Errors
Latch Data
Latch Check Word
L
L
Enabled
READ
H
L
Correct Data Word &
Generate Syndrome'Bits
Output Corrected Data
Output Syndrome Bits
Enabled
SO
PROOUCTIOII DATA documants contlin information
current as of publication data. Preducts conform to
specifications par the terms of Taxas Instruments
::~~:~~i~.t::1~7i ~:\~:i:r :'~O:=:::~~I not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-1055
SN54LS636, SN54LS637, SN74LS636, SN74LS637
a·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
functional block diagram
51
so
FUNCTIO
SELECTO
S1
-
+-
so
SO-S1
SO-S1
-=0-
5.-
.-
LATCH
PARITY
GENERATOR
..... C
I/~~
CHECK BIT
CBOTHRU CB4
V
10
8
-+- -
BUFFER
10...
5.-
/
OE
-f
-f
....
+-
r-
f----+ SEF
~ DEF
~O
8
LATCH
OE
ERROR
DETECTOR
/
8
C
I'-
DATA BIT
I/O,~
DBOTHRU DB7
8
C
CD
<
c;'
1 - BUFFER
CD
til
8
ERROR
CORRECTOR
~
ERROR
DECODER
OE
ERROR FUNCTION TABLE
TOTAL NUMBER OF ERRORS
ERROR FLAGS
DEF
DATA
8-BIT DATA
50BIT CHECKWORD
SEF
0
1
0
1
2
0
0
0
L
L
Not Applicable
H
L
H
H
L
Correction
Correction
H
Interrupt
H
H
Interrupt
H
H
Interrupt
1
1
0
2
CORRECTION
In order to be able to determine whether the data from the memory is acceptable to use as presented to the bus,
the EDAC must be strobed to enable the error flags and the flags will have to be tested for the zero condition.
The first case in the error function table represents the normal, no-error condition. The CPU sees lows on both flags_
The next two cases of single-bit errors require data correction_ Although the EDAC can discern the single check bit
error and ignore it, the error flags are identical to the single error in the a-bit data word. The CPU will ask for data
correction in both cases. An interrupt condition to the CPU results in each of the last three cases, where dual errors occur_
error detection and correction details
During a memory write cycle, five check bits (CBO-CB4) are generated by eight-input parity generators using the data
bits as defined below. During a memory read cycle, the 5-bit check word is retrieved along with the a-bit data word_
2-1056
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS636. SN54LS637. SN74LS636. SN74LS637
8·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
CHECKWORD
8·BIT DATA WORD
BIT
0
1
CBO
X
X
CBl
X
CB2
C83
X
2
X
X
X
X
X
3
4
X
X
X
X
~
X
CB4
5
6
X
X
7
X
X
X
X
X
X
X
The five check bits are parity bits derived from the matrix of data bits as indicated by "X" for each bit.
Error detection is accomplished as the 5-bit check word and the 8-bit data word from memory are applied to internal
parity generators/checkers. If the parity of all five groupings of data and check bits are correct, it is assumed that
no error has occurred and both error flags will be low.
If the parity of one or more of the check groups is incorrect, an error has occurred and the proper error flag or flags
will be set high. Any single error in the 8-bit data word will change the sense of exactly three bits of the 5-bit check
word. Any single error in the 5-bit check word changes the sense of only that one bit. In either case, the single error
flag will be set high while the dual error flag will remain low.
Any two-bit error will change the sense of an even number of check bits. The two-bit error is not correctable since
the parity tree can only identify single-bit errors. Both error flags are set high when any two-bit error is detected.
II
C/)
Q)
Three or more simultaneous bit errors can fool the EDAC into believing that no error, a correctable error, or an
uncorrectable error has occurred and produce erroneous results in all three cases.
Error correction is accomplished by identifying the bad bit and inverting it. Identification of the erroneous bit is achieved
by comparing the 8-bit data word and 5-bit check word from memory with the new check word with one (check word
error) or three (data word error) inverted bits.
As the corrected word is made available on the data word 1/0 port, the check word 1/0 port presents a 5·bit syndrome
error code. This syndrome code can be used to identify the bad memory chip.
o
>
Q)
o
..........J
ERROR SYNDROME TABLE
ERROR LOCATION
SYNDROME ERROR CODE
CBO
CBl
CB2
CB3
CB4
DBO
L
L
H
L
H
DBl
L
H
L
L
H
DB2
H
L
L
L
H
DB3
L
L
L
H
H
H
L
DB4
H
L
DBS
H
L
L
H
L
L
L
DB6
H
L
H
L
DB7
H
H
L
L
L
cao
L
H
H
H
H
CBl
CB2
H
H
H
H
H
H
CB3
H
CB4
NO ERROR
L
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-1057
SN54LS636, SN54LS637, SN74LS636, SN74LS637
8·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC
TYPICAL OF OEF AND SEF OUTPUTS
----+--VCC
INPUT
OUTPUT
TYPICAL OF CB AND DB ('LS636)
TYPICAL OF CB AND DB ('LS637)
1~QVCC
__ ~OUTPUT
_~OUTPUT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
~upply
voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
7V
Input voltage: SO and Sl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
eB and DB ...................................................... .
5.5V
Off-state output voltage
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range: SN54LS636, SN54LS637 . . . . . . . . . . . . . . . . . . . . . . _55°C to 125°C
SN74LS636, SN74LS637 . . . . . . . . . . . . . . . . . . . . . . . . . oOe to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _65°C to 150°C
NOTE1: Voltage values are with respect to network ground terminal.
recommended operating conditions
SN54LS636
SN74LS636
SN54LS637
VCC
Supply voltage
IOH
High-level output current
VOH
High-level output voltage
IOL
Low-level output current
'su
Setup time
1:j,
Hold time
TA
Operating free-air temperature
SN74LS637
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
CB or DB, 'L5636 only
DEF or SEF
CB or DB, 'L5637 only
CB or DB
DEF or SEF
-1
-1
-0.4
-0.4
5.5
5.5
12
24
4
B
CB or DB before S1 tt
15
15
CB or DB before 51U
45
45
CB or DB after 51 t
15
15
-55
125
0
t This time guarantees the input data and check word will be latched.
tThis time guarantees the input data and checkword will be latched plus that no glitch will occur on SEF or DEF flags.
t The upward-pointing arrow indicates a transition from low to high.
2-1058
UNIT
MIN
"If
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V
mA
V
mA
ns
ns
70
°c
SN54LS636, SN54LS637, SN74LS636, SN74LS637
8-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS636
TEST CONDITIONSt
PARAMETERS
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
II =-18mA
VCC- MIN,
CB or DB
DEF or SEF
Low-level output voltage
VCC= MIN,
VIH =2 V,
VIL =VILmin
Off-state output current,
high-level voltage applied
Off-state output current,
IOZL
II
low-level voltage applied
CB or DB
CB or DB
2.4
IOH = -400/lA
2.5
3.4
V
-1.5
-1.5
V
VO-O.4V,
SO and Sl at 2 V
CB or DB
VCC= MAX,
:;u or Sl
VIH =4.5 V
2.7
3.4
V
0.25
0.4
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
20
20
-0.2
-0.2
0.1
0.1
0.1
0.1
SOandSl at2V
Input current at maximum
3.2
0.4
Vo - 2.7 V,
VCC= MAX,
input voltage
2.4
IOL =BmA
VCC= MAX,
V
0.8
0.25
IOL=4mA
UNIT
0.7
IOL =24mA
VIH = 2 V,
DEF or SEF VIL = VILmax
IOZH
IOH=MAX
3.3
IOL=12mA
VCC= MIN,
TYP+ MAX
MIN
2
2
CB or DB
VOL
SN74LS636
MIN TYP+ MAX
VI-5.5V
I VI-7V
V
/lA
rnA
rnA
II
III
IIH
High-level input current
VCC= MAX,
VI=2.7V
20
20
/lA
IlL
Low-level input current
VCC= MAX,
VI-O.4V
-0.2
-0.2
rnA
Q)
(.)
rnA
'S;
IOS§
ICC
Short-circuit output
CB or DB
current
DEF or 5EF
VCC=MAX
-30
-130
-30
-130
-20
-100
-20
-100
VCC MAX, SO and 51 at 4.5 V,
All CB and DB pins grounded,
Supply current
100
160
100
160
rnA
DEF and 5EF open
TEST CONDITlON5 t
PARAMETER
VIH
High-level input voltage
VIL
VIK
Low-level input voltage
Input clamp voltage
VOH
High-level output voltage
IOH
High-level output current
TYP+ MAX MIN TYP+ MAX
2
DEF or SEF
CBor DB
CBor DB
VOL
5N74LS637
SN54LS637
MIN
VCC= MIN,
II = -18mA
VCC= MIN,
V'IH = 2 V,
IOH = -400 /lA,
VCC= MIN,
VOH = 5.5 V,
VIH=2V,
VIL = VILmax
VCC=MIN,
Low·level output voltage
VIH=2V,
DEF or SEF
VIL = VIL max
2.5
VIL = VILmax
V
2
0.8
V
-1.5
-1.5
V
2.7
0.25
0.4
10L - 24 mA
IOL =4 mA
0.25
0.4
V
3.4
0.1
IOL = 12 mA
0.1
IOL -8mA
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
mA
V
I "put cu rrent at
CB or DB
VCC- MAX,
VI=5.5V
0.1
0.1
maximum input voltage
SOorSl
VIH"4.5V
VI = 7 V
0.1
0.1
IIH
High-level input current
VCC= MAX
VI = 2.7 V
20
20
/lA
IlL
Low-level input current
VCC=MAX,
VI =O.4V
-0.2
-0.2
rnA
IOS§
Short-circuit output
current
-100
mA
ICC
Supply current
144
mA
II
DEF or SEF
VCC= MAX
-20
-100
..J
....
....
UNIT
0.7
3.4
Q)
o
-20
mA
VCC = MAX, SO and 51 at 4.5 V,
All CB and DB grounded,
90
144
90
SEF and DEF open
t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee. "" 5 V, T A = 2SoC.
§ Not more than one output should be shorted 8't a time, and duration of the short.circuit should not exceed one second.
TEXAS , . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-1059
SN54LS636, SN54LS637,SN74LS636, SN74LS637
8·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
'LS636 switching characteristics, Vee
PARAMETER
FROM
(INPUT)
tPLH Propagation delay time, low-to-high-Ievel output t
tpHL Propagation delay time, high-to-Iow-Ievel outputt
DB
tPLH Propagation delay time, low-to-high-Ievel output1:
SIt
tpZH Output enable time to high level §
SO.
SOatO V,
SEF
tPLZ Output disable time from low level 1
SOt
CB,DB
SI atO V,
31
45
n.
65
n.
SOat3V,
RL=2k!l,
See Figure 1
27
40
20
30
24
40
n.
30
45
n.
43
65
n.
31
45
n.
RL=667!l,
See Figure 1
SI at3 V,
RL=667!l,
See Figure 2
SI at3 V,
RL=667!l,
See Figure 1
PARAMETER
tPLH Propagation delay time, low·to-high level output t
tPH L Propagation delay timo, high·,o·low·level outpu,t
DB
tPLH Propagation delay time, low-to-high-level output';
Sit
C;'
tPHL Propagation delay time, high-to-Iow-Ievel output·§
CD
tPLH Propagation delay time, low·,o-high·level ou,pu,'
SO.
sot
TO
(OUTPUT)
CB
DEF
SEF
CB,DB
CB,DB
UNIT
45
= 5 V, TA = 25 o e, eL = 45 pF, see Figure
FROM
(INPUT)
'LS636
TYP MAX
RL = 667!l, See Figure 1
SI at3 V,
CB,DB
CB, DB
MIN
SI at3 V,
RL=667!l,
See Figure 2
CB,DB
SOt
CD
<
TEST CONDITIONS
CB
tPHZ Output disable time from high level 1
'LS637 switching characteristics, Vee
0
TO
(OUTPUT)
DEF
SO.
tpZL Output enable time to low level §
-t
-t
r-
45 pF
5 V, TA
TEST CONDITIONS
SOatOV,
1
'LS637
MIN
SI atOV,
RL=667!l
SOat3V,
RL = 2 k!l
S1at3 V,
SI a,3V,
RL =667 k!l
RL=667k!l
n.
UNIT
TYP
MAX
3B
55
45
65
n.
27
40
n.
20
30
n.
28
45
50
n.
33
ns
ns
tThese parameters describe the time intervals taken to generate the check word during the memory write cycle.
*These parameters describe the time intervals taken to flag errors during the memory read cycle.
§These parameters describe the time intervals taken to correct and output the data word and to generate and output the syndrome error
code during the memory read cycle.
'These parameters describe the time intervals taken to disable the CB and DB buses in preparation for a new data word during the memory
read cycle.
PARAMETER MEASUREMENT INFORMATION
VCC=5V
~
RL
OUTPUT
OF CIRCUIT
l'
CL =45pF
FIGURE I-OUTPUT LOAD CIRCUIT
2-1060
FIGURE 2-0UTPUT LOAD CIRCUIT
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS636, SN54LS637, SN74LS636, SN74LS637
8-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
6
typical operating sequences
READ, FLAG, AND CORRECT MODE SWITCHING WAVEFORMS
so--------------------~
Sl--------------~
:....-tsut--.:.·-thold
I
DBO-DB7
I
I
...l
I
INPUT DATA WORD
OUTPUT CORRECTED DATAWORD
FJI
C/)
Q)
~, tpd~r--------~~~~~~--------'\
U
SEF--------------~----------,L-------------V-A~L~I~D~S~EF~FL~A~G~------~-------_____
'S;
Q)
:~
tpd
C
-----t!.;,.-------.,...--,....-=..".-.....,...------"""""\
DEF--------------~------------~~~-------V~A~L~ID~D~E~F~F~LA~G~------~--------___
-'
lI-
t NOTE: There are two conditions specified for tsu of Data or Checkword before S1t • See recommended operating conditions for detail.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76266
2-1061
2-1062
SN54LS638. SN54LS639. SN74LS638. SN74LS639
OCTAL BUS TRANSCEIVERS
02636, JANUARY 1981-REVISED MARCH 1988
SN54LS638, SN54LS639 ••• J PACKAGE
SN74LS638, SN74LS639 ••• DW OR N PACKAGE
• Bidirectional Bus Transceivers in HighDensity 20-Pin Packages
(TOPVIEWI
• Hysteresis at Bus Inputs Improves Noise
Margins
Vee
G
DIR
A1
• Choice of True or Inverting Logic
A2
• A Bus Outputs are Open-Collector,
B Bus Outputs are 3-8tate
A4
A5
A6
A7
description
These octal bus transceivers are designed for asyn·
chronous two-way communication between opencollector and 3-state buses. The devices transmit data
from the A bus (open-collector) to the B bus (3-state)
or from the B bus to the A bus depending upon the
level at the direction control (D IR) input. The enable
input (G) can be used to disable the device so the
buses are isolated.
B1
B2
B3
B4
85
86
87
88
AS
GND
SN54LS638, SN54LS639 ••. FK PACKAGE
(TOPVIEWI
en
FUNCTION TA8LE
OPERATION
CONTROL
INPUTS
G
DIR
Q)
(J
'S
Q)
'LS639
'LS638
L
L
B data to A bus
B data to A bus
L
H
A data to B bus
A data to B bus
H
X
Isolation
Isolation
H
=
C
...J
lI-
high level, L = low level, X = Irrelevant
DEVICE
A OUTPUT
B OUTPUT
'LS638
Open~Collector
3.-5tate
LOGIC
Inverting
'LS639
Open-Collector
3-State
True
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF A OUTPUTS
TYPICAL OF B OUTPUTS
Vcc
VCC------~.-------
50 n NOM
10kn NOM
INPUT
OUTPUT
PRODUCTID. DATA 0I00UIIIIIII ..0IIio i.,",motio.
curront II of plbIicItio. date. P,odUeII ..nfo'IR 10
.plOiliClti... por tile tor... of T.... 1.11.....l1li
:;'=~i~"i~:I:; ~:t;:~i:; l!r:::~:.:~~ not
TEXAS •
INSTRUMENTS
POST OfFICE BOX 655012 • DALLAS, TEXAS 75265
2-1063
SN54LS638, SN54LS639, SN74LS638, SN74LS639
OCTAL BUS TRANSCEIVERS
logic symbols t
'LS638
'LS639
G (191
DIR..;.(I~I~""'f
-I
-I
rC
((88~1~~-------t-+~
A7 -'-
CD
:!:.
n
CD
en
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for OW, J, and N packages.
. logic diagrams (positive logic)
'LS639
'LS638
G_-------,
G------1--'
DIR --<>----Ie--'
AI
81
A1
81
A2
82
A2
82
TO SIX OTHER TRANSCEIVERS
TO SIX OTHER TRANSCEIVERS
absDlute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
Input voltage (DI R or (3) . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . • . . . . • . • • . . • • • . . . . . . . •
7V
Off-state output voltage (A or B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54LS638, SN54LS639 . . . . . . . . . . . . . . . . . . . . . . . _55°C to 125°C
SN74LS638, SN74LS639 . . . . . . . . . . . . . . . . . . . . . . . . . . oOe to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _65°C to 150°C
NOTE 1: Voltage values are with respect to the network ground terminal.
2-1064
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
SN54LS638, SN54LS639, SN74LS638, SN74LS639
OCTAL BUS TRANSCEIVERS
recommended operating conditions
SN54LS'
Supply voltage, Vee
SN74LS'
MIN
NOM
MAX
MIN
NOM
4.5
5
5.5
4.75
5
MAX
5.25
UNIT
V
High-level output voltage, VOH (A bus)
5.5
5.5
V
High-level output current. IOH (B bus)
-12
-15
mA
24
mA
70
°c
Low-level output current, tOl (A or B bus)
12
Operating free-air temperature, T A
-55
125
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
VOH
VOL
Input clamp voltage
Vee" MIN, II - -18 mA
Hysteresis (VT+-VT_I
Vee= MIN
II
MIN
TYP*
low-level voltage applied
0.4
0.1
VOH=5.5V
2.4
2
2
V
V
0.1
2.4
V
rnA
Vee - MIN, VIH - 2 V,
IOH--3rnA
VIL = MAX
10H - MAX
Vee - MIN, VIH - 2 V,
IOL-12rnA
VIL = MAX
10L - 24 rnA
B
Vee= MAX,G at2V,
VO=2.7V
20
20
I"A
A or B
Vee = MAX, Gat 2 V,
Vo = 0.4 V
- 0.4
-0.4
rnA
VI - 5.5 V
0.1
0.1
VI = 7 V
0.1
0.1
Low-level output voltage A or B
high-level voltage applied
-1.5
0.2
0.4
UNIT
V
0.6
-1.5
0.1
MAX
2
Vee - MIN, VIH - 2 V, VIL - MAX,
High-level output voltage B
Off-state output current
10ZL
SN74LS'
MAX
TYP*
0.5
Off-state output current,
10ZH
MIN
2
High-level output current A
IOH
SN54LS'
TEST CONDITIONSt
Input current at maxi-
A or B
mum input voltage
DIR orG
Vee = MAX
0.25
V
0.4
0.25
0.4
0.35
0.5
II)
Q)
CJ
V
'S;
rnA
IIH
High-level input current
Vee = MAX, VI = 2.7 V
20
20
I"A
IlL
Low-level input current
Vee - MAX, VI - 0.4 V
-0.4
-0,4
rnA
Short-circuit
lOS
B
output current §
leez
-225
rnA
Vee = MAX, Outputs open
-40
48
70
48
70
rnA
Vee - MAX, Outputs open
62
90
62
90
rnA
Vee - MAX, Outputs open
64
95
64
95
rnA
Vee = MAX
leeH Supply current, outputs high
leeL Supply current, outputs low
Supply current, outputs off
-225
-40
•
Q)
C
..J
lI-
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:
All typical values are at Vee
:=
5 V, T A
=
25° C,
§ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
switch ing characteristics, Vee = 5
PARAMETER
tpLH
V. TA = 25° C. see note 2
FROM
TO
(INPUT)
(OUTPUT)
'LS638
A
B
6
10
8
15
B
A
17
8
25
19
25
15
11
15
14
25
16
25
26
40
23
40
os
TEST CONDITIONS
MIN
TYP
'LS639
MAX
MIN
TYP
MAX
UNIT
os
A
B
B
A
tpLH
G
A
tpHL
G
A
43
60
34
50
os
tPZH
G
B
23
40
26
40
os
tpZL
G
B
31
40
31
40
os
tpHZ
G
B
15
25
15
25
os
tPLZ
~
B
15
25
15
25
os
tPHL
eL = 45 pF, RL = 667
eL = 5 pF, RL = 667
n
n
os
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1065
SN54LS638, SN54LS639, SN74LS638, SN74LS639
OCTAL BUS TRANSCEIVERS
TYPICAL CHARACTERISTICS
SN54LS'
INVERTING OUTPUT VOLTAGE
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
5
4
>I
~
------ ~
3
>
§:
~
=>
s-
a"
I
a
2
15
~'"
,
0
0
CD
\
0.5
l
>
,
I
I
it.
~
1 : \ ..
i
~ \ "
2~---+-~~1~-~~+---~
b
I
,. ~
I
I
~
......
-----
I-----I---~:....~ct-h\---+-----i
3
::
6fr
1~
>
-I
-I
rC
••••••••• T A = 70°C
---TA=25°C
4 ~----l----+-~~-TA = OoC -
.. ................
11
~
5
r
°
•••••••• TA = 125 C
---TA=25°C
TA=-55°C
>I
"0
SN74LS'
INVERTING OUTPUT VOLTAGE
\
L \:
\
OL-_ _L-_ _ _L-____
o
2
1.5
0.5
~
__
~
1.5
VI-Input Voltage-V
VI-Input Voltage-V
FIGURE 1
FIGURE 2
SN54LS'
NONINVERTING OUTPUT VOLTAGE
SN74LS'
NONINVERTING OUTPUT VOLTAGE
2
:So
(")
CD
en
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
5
4
>I
i:~····:···
!!,
~
"0
s-"
••••••••1TA = 70° C
---TA=25°C
4 ~---+----+--~~TA = OOC
............ ............
>I
"
C>
3
:,
>...
a"
I
a
5
J
°
••••••••• TA=125C
---TA25°C
TA=-55°C
•
2
>
,
I
:'
:''1
1.!.
I
,
,
P
:,
:1
:'
0
0
s-"
a"
I
a
>
1I
.1
3
>...
I
:,
.'
~
0
2
,
I
I
I
I
I
I
.J
0
1.5
2
0
VI-Input Voltage-V
0.5
1.5
VI-Input Voltage-V
FIGURE 3
2·1066
I
I
+
I
___ .JI
0.5
:
:
;: ,:
FIGURE 4
TEXAS·"
INSTRUMENTS
POST OFFICE BOX 655012 .. DALLAS, TEXAS 75265
2
SN54LS640 THRU SN54LS642, SN54LS644, SN54LS645
SN74LS640 THRU SN74LS642, SN74LS644, SN74LS645
OCTAL BUS TRANSCEIVERS
02420, APRIL 1979- REVISED MARCH 1988
SN54LS' ... J PACKAGE
SN74LS' ... OW OR N PACKAGE
(TOP VIEWI
•
SN74LS64X-1 Versions Rated at IOL
of 48 mA
•
Bi-directional Bus Transceivers in HighDensity 2O-Pin Packages
•
Hysteresis at Bus Inputs Improves Noise
Margins
•
Choice of True or Inverting Logic
•
Choice of 3-State or Open-Collector
Outputs
DEVICE
'LS640
'LS641
'LS642
'LS644
'LS645
OUTPUT
3-State
Vee
OIR
A1
A2
G
B1
B2
83
B4
B5
B6
B7
B8
A5
A6
LOGIC
Inverting
Open-Collector
True
Open-Collector
Open-Collector
3-State
Inverting
SN54LS' ... FK PACKAGE
(TOP VIEW)
True and inverting
True
"I
~!!: ~
3
2 1 2019
fII
« « c > l(!l
A3
description
B1
B2
B3
A4
A5
A6
A7
These octal bus transceivers are designed for asynchronous two-way communication between data buses.
The devices transmit data from the A bus to the B bus or
from the B bus to the A bus depending upon the level at
the direction control (OIR) input. The enable input (G)
can be used to disable the device so the buses are effectively isolated.
CI)
Q)
(,)
":;
Q)
C
......
..J
B5
FUNCTION TABLE
The -1 versions ofthe SN74LS640 thru SN74LS642,
SN74LS644, and SN74LS645 are identical to the
standard versions except that the recommended
maximum IOL is increased to 48 milliamperes. There
are no -1 versions of the SN 54LS640 thru
SN54LS642, SN54LS644, and SN54LS645.
The SN54LS640 thru SN54LS642, SN54LS644, and
SN54LS645 are characterized for operation over the
full military temperature range of - 55 DC to 125 DC.
The SN74LS640 thru SN74LS642, SN74LS644, and
SN74LS645 are characterized for operation from 0 DC
to 70 D C.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the larms of Taxas Instruments
:~~~~:~~i~.i~:1~1i ~!:~~~i:f :,~O:::::::~:~~ not
CONTROL
OPERATION
INPUTS
G
DIR
L
L
L
H
H
X
'LS640
'LS641
'LS642
'LS645
B data to A bus B data to A bus
A data to B bus A data to B bus
Isolation
H = high level, L= low level, X
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 .. DALLAS, TEXAS 75265
Isolation
'LS644
8 data to A bus
A data to 8 bus
Isolation
= irrelevant
2-1067
t:-'
o
m
(Xl
sa!)!J\aa
""0
:r
~
'LS640
-I
m <
OJ 3
~
[
~
m
'LS642
'LS641
E :3 m
<'"m
Q>
co m
~C:~
~~
e:::
enQQ
B3
z»
.., z
~~
s:;cr;r
men en
A3
!- g
"'~'2.
....
.... ...., U'I
~oIiIoolilo
,..,..,..
.~~
~
~
i-
Q en en
n
••
~
B4
B5
A7E-SB7
AB
~~
""0
en en
<
~
en
en
en en
oIiIoolilo
in
~
en en
...., U'I
,.. ,..
(')
r
oIiIoolilo
NN
oIiIoolilo
BB
"-
g
~
<~::
m,..,..
'LS644
...., U'I
,.. ,..
oIiIoolilo
-~
G
OIR III
••
'LS645
ii
G3
3 EN1 (BAI
en en
en en
DIR
oIiIoolilo
!"
A1~Ql
Q)
DIR
...J
DIR-+----..J
~
IB1
B1
A1
A1
TO SEVEN OTHER TRANSCEIVERS
TO SEVEN OTHER TRANSCEIVERS
'LS645
G-----...,
DIR _ + -_ _ _..J
A1
81
TO SEVEN OTHER TRANSCEIVERS
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-1069
SN54LS640, SN54LS645
SN74LS640, SN74LS645
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: All inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
110 ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54LS640, SN54LS645 ............. - 55°C to 125°C
SN74LS640, SN74LS645 ................. ooe to 70°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
PARAMETER
~
~
rC
vee
Supply voltage
VIH
High-lvel input voltage
Vil
Low-level input voltage
IOH
High-level output current
IOl
Low-level output current
TA
Operating free-air temperature
SN54LS640
SN74LS640
SN54LS645
SN74LS645
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
2
2
V
0.5
0.6
-12
-15
12
24
4St
125
- 55
V
0
70
V
mA
mA
"e
CD
tThe 4S-mA limit applies for the SN74LS640-1 and SN74LS645·1 only.
~.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
<
Ul
PARAMETER
TEST CONDITIONS*
SN54LS640
SN74LS640
SN54LS645
SN74LS645
MIN TYP§
Vee = MIN,
VIK
Hysteresis
(VT+- VT_I
VOH
VOL
Vee= MIN,
Vee= MIN,
Vil = MAX
VIH-2V,
Vee = MIN,
VIH=2V,
0.2
0.4
IOH--·3rnA
2.4
3.4
2.4
3.4
10H MAX
IOl-12rnA
"'0.25
Gat 2 V,
Vee- MAX,
Gat 2 V,
Vo - 0.4 V
IDIRorG
Vee= MAX
0.4
24 rnA
Vee- MAX,
V
V
2
2
10ZH
MAX
-1.5
0.4
IOZl
IAorB
TYP§
0.1
IOl = 4B rnA #
Vo - 2.7 V
II
MIN
A or B input
IOl
Vil = MAX
MAX
-1.5
II = -18mA
UNIT
0.25
0.4
0.35
0.5
0.4
0.5
V
20
20
~A
-0.4
- 0.4
rnA
VI - 5.5 V
0.1
0.1
VI- 7 V
0.1,
0.1
mA
IIH
Vee - MAX,
VIH - 2.7 V
20
20
~A
IlL
Vee - MAX,
Vil - 0.4 V
-0.4
0.4
rnA
- 225
rnA
lOS'
ICC
-40
Vee- MAX
I Outputs high
I Outputs low
I
Vee= MAX,
Outputs open
Outputs at Hi·Z
- 225
-40
48
70
48
70
62
90
62
90
64
95
64
95
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
§AII typical values are at Vee = 5 V, TA = 25°C.
1Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
'The 4B-mA condition applies for the SN74LS640-' and SN74LS645-1 only.
2-1070
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
rnA
SN54LS640, SN54LS645
SN74LS640, SN74LS645
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
switching characteristics.
PARAMETER
tpLH
tpHL
Propagation delay time,
tpLZ
tpHZ
TO
TEST
(lNPUTI
(OUTPUTI
CONDITIONS
A
B
A
low-to-high-Ievel output
B
Propagation delay time,
A
B
high-to-Iow-Ievel output
B
G
G
G
G
G
G
G
G
A
Output enable time to
tpZL
low level
tpZH
Vee
FROM
Output enable time to
high level
Output disable time
from low level
Output disable time
from high level
A
B
CL
= 45
'LS640, 'LS640-1
MIN
TYP
MAX
6
6
8
8
31
31
23
23
15
15
15
15
10
pF,
RL = 6670,
See Note 2
A
B
A
B
A
B
CL
=
5 pF,
RL = 6670,
See Note 2
'LS645, 'LS645-1
MIN
TYP
MAX
15
10
8
8
15
11
15
15
40
11
31
40
40
31
40
40
26
40
40
26
40
25
15
25
25
15
25
25
25
15
25
15
25
15
15
UNIT
ns
ns
ns
ns
ns
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
schematics of inputs and outputs
III
EQUIVALENT OF EACH INPUT
CI)
()
TYPICAL OF OUTPUTS
"S;
VCC------4... - - - - -
- -.....-vcc
50 II NOM
10 kH NOM
CI)
o
..J
tt-
INPUT
OUTPUT
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1071
SN54LS640, SN54LS645
SN74LS640, SN74LS645
OCTAL BUS TRANSCEIVERS WITH 3·STATE OUTPUTS
TYPICAL CHARACTERISTICS
SN74LS'
INVERTING OUTPUT VOLTAGE
SN54LS'
INVERTING OUTPUT VOLTAGE
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
5
4
------ ~
8.
l!!
3
>
~
>I
~
0
'\
2
1
0
>
~
~
r-
'" 3
l!!
f'\'
0
C
>...
e
"
~
~
t
\
,
0
>
i
\ \
~
,
L
0
2
1.5
0.5
2
1
0
I
I
I
I
~
L......
0
~
(;
p.
1
-----
"
~
B-
~ = 70°C
••••••••• TA
---TA=25°C
4 I-----+---+-~~-TA = OoC _
..................
>1
(;
5
_I
°
•••••••• TA = 125 C
---TA=25°C
TA = -55°C
\:
1.5
0.5
0
2
Cb
VI-Input Voltage-V
VI-Input Voltage-V
0"
FIGURE 1
FIGURE 2
SN54LS'
NONINVERTING OUTPUT VOLTAGE
SN74LS'
NONINVERTING OUTPUT VOLTAGE
<
Cb
en
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
5
5
I = 125° C
••••••••• TA
---TA25°C
TA = _55°C
4
>1
:l·· .... ·:··· . .............. .. ...........
l!! 3
,
8.
(;
>
...
t
~
B~
0
I
0
2
:1
:1
:1
3
:
,
~
I
B-
lI
0
~
I
I
I
___ .II
0
1.5
0.5
2
,
~.
I
1
1
I
I
I·
I
~---r~~~~~
0
VI-Input Voltage-V
1.5
0.5
VI-Input Voltage-V
FIGURE 4
FIGURE 3
2-1072
I
1
1
+,
1
0
lI
,
i ' ,
2
>
0
0
:=
>...
I
'1p
>
"
(;
I
I
,I
°
>1
'"
l!!
:,
!I
:'
'I
1.!.
:1
I
-------- T A = 70 C
---TA=25°C
4 I------+---+---~TA = OoC
..If
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2
SN54LS641, SN54LS642, SN54LS644
SN74LS641, SN74LS642, SN74LS644
OCTAL BUS TRANSCEIVERS WITH OPEN"COLLECTOR OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage: All inputs and I/O ports ........................................................... 7 V
Operating free·air temperature range: SN54LS641, SN54LS642, SN54LS644 .................. - 55'e to 125'e
SN74LS641, SN74LS642, SN74LS644 ...................... O"e to 70'e
Storage temperature range .......................................................... - 65' e to 150' e
NOTE 1: Voltage values are with respect to network ground terminal.
recommended operating conditions
PARAMETER
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
SN54LS641
SN74LS641
SN54LS642
SN74LS642
SN54LS644
SN74LS644
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.5
0.6
V
5.5
5.5
12
24
2
2
VOH High-level output voltage
IOL
Low-level output current
TA
Operating free-air temperature
UNIT
V
4S§
- 55
125
70
0
V
mA
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS t
SN54LS641
SN74LS641
SN54LS642
SN74LS642
SN54LS644
MIN
VIK
Hysteresis
(VT+- VT_)
IOH
VOL
II
l Aor B
I DIR orG
Vce=MIN,
11=-18mA
Vee= MIN,
Aor B input
Vee-MIN,
VIH = 2 V,
VIL = MAX,
VOH=5.5V
Vee MIN,
VIH = 2 V,
IOL=12mA
VIL = MAX
IOL = 48 mA§
Vee= MAX
TYP*
0.1
0.4
0.4
0.1
0.25
0.4
IOL = 24 mA
0.1
0.25
0.4
0.35
0.5
0.4
0.5
0.1
0.1
VI =7 V
0.1
0.1
IIH
IlL
VCC= MAX,
VI =0.4V
-0.4
Vce= MAX,
Outputs open
I Outputs at Hi·Z
lI-
V
V
VI=5.5V
20
o
MAX
- 1..5
0.2
VI = 2.7 V
I Outputs high
I Outputs low
TVP*
-1.5
VCC= MAX,
Ice
MIN
"S:
Q)
....I
UNIT
SN74LS644
MAX
Q)
CJ
§The 48 mA limit applies for the SN74LS641-1. SN74LS642-1, and SN74LS644-1 only.
PARAMETER
•
II)
'e
20
-0.4 1
4S
70
48
70
62
90
62
90
64
95
64
95
mA
V
mA
I'A
mA
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:I: All typical values are at Vee = 5 V, T A = 25° e.
§The 48 rnA condition applies for the SN74LS641-1, SN74LS642-1, and SN74LS644-1 only.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-1073
sao!J\aa 1.L.L
t:-'
o
..,.-..J
o en en
nzz
switching characteristics at Vee: 5 V, T A: 25°e
FROM
TO
(INPUT)
(OUTPUT)
A
B
low-to-high-Ievel output
B
A
Propagation delay time,
A
B
high-to-Iow-level output
B
A
Output disable time
G,DIR
A
from low level
G,DIR
B
Output enable time
G,DIR
A
from high level
G,DIR
B
PARAMETER
Propagation delay time,
tPLH
tpHL
tPLH
tpHL
-I~U'I
TEST CONDITIONS
CL =45pF,
RL =667 n,
See Note 2
MIN
TYP
MAX
17
'LS642, 'LS642-1
MIN
TYP
MAX
25
19
'LS644, 'LS644-1
MIN
TYP
MAX
25
17
25
17
25
19
25
19
25
16
25
14
25
14
25
16
25
14
25
16
25
23
40
26
40
26
40
25
40
28
40
25
40
34
50
43
60
43
60
37
50
39
60
37
50
-I en en
:D ZZ
ns
ns
ns
~~U'I
Z4la4la
en
........
nenen
menen
UUl
These devices consist of bus transceiver circuits with
3-state or open-collector outputs, D-type flip-flops,
and control circuitry arranged for multiplexed transmission of data directly from the input bus or from
the internal registers. Data on the A or B bus will be
clocked into the registers on the low-to-high transition
of the appropriate clock pin (CAB or CBA). The following examples dernonstrate the four fundamental
bus-management functions that can be performed
with the octal bus transceivers and registers.
4
3
2
'S;
1
Q)
5
B1
6
7
C
...I
lI-
8
9
10
11
12 1314151617 18
....CX>CUCX> .... co
««ZZOl OlOl
t!l
1211
131
G
OIR
L
L
111
(231
CAB CBA
X
(21
(221
(211
(31
111
(23)
(21
SAB
SBA
G
OIR
CAB
CBA
SAB
SBA
X
L
L
H
HorL
X
L
X
Hor L
REAL-TIME TRANSFER
REAL·TIME TRANSFER
BUSBTOBUSA
BUSATO BUSB
1221
PRODUCTION DATA documents contain information
current as of publication data. Products conform to
specifications per the terms of Taxas Instruments
:~~:~:=i;ai~:1~7~ ~!:~~~ti:; :.~o::;::::9t:::.s not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-1075
SN54LS646 THRU SN54LS649, SN74LS646 THRU SN74LS649
OCTAL BUS TRANSCEIVERS AND REGISTERS
'-.;-I
(21)
(3)
(1)
(23)
(2)
(22)
(21)
(3)
(1)
(23)
(2)
(22)
G
DIR
CAB
CBA
SAB
SBA
G
DIR
CAB
CBA
SAB
SBA
X
X
X
X
X
t
X
X
X
X
X
X
X
L
L
H
X
X
H
L
X
X
X
X
H
X
H
-I
-I
r
TRANSFER
STORAGE FROM
STORED DATA
A,B,OR AAND B
TOAOR B
Enable (G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode, data
present at the high-impedance port may be stored in either register or in both, The select controls (SAB and SBA) can
multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data
when enable G is active (low). In the isolation mode (control G high), A data may be stored in one register and/or B
data may be stored in the other register.
oCD
<
n'
CD
en
When an output function is disabled, the input function is still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time.
The SN54' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74'
family is characterized for operation from 0° to 70°C.
FUNCTION TABLE
INPUTS
DATA Ilot
OPERATION OR FUNCTION
G
DIR
CAB
CBA
SAB
SBA
Al THRUA8
Bl THRU B8
X
X
t
X
X
X
Input
Not specified
Store A. B unspecified
Store A, B unspecified
X
X
X
X
Not specified
Input
Store B, A unspecified
Store B. A unspecified
X
t
t
t
X
H
X
X
H
X
H or L
H or L
X
Input
L
L
X
H or L
X
X
L
Input
L
L
X
X
X
H
L
H
H or L
X
L
X
L
H
X
X
H
X
Output
Input
Input
Output
LS646, LS647
LS648. LS649
Store A and B Data
Store A and 8 Data
Isolation, hold storage
Isolation, hold storage
Real-Time B Data to A Bus
Real-Time B Data to A Bus
Stored B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus
Real-Time A Data to 8 Bus
Stored A Data to B Bus
Stored A Data to B Bus
t The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled. i.e••
data at the bus pins will be stor4td on every low-to-high transition on the clock Inputs,
2-1076
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS646 THRU SN54LS649, SN74LS646 THRU SN74LS649
OCTAL BUS TRANSCEIVERS AND REGISTERS
logic diagrams (positive logic)
'LS646, 'LS647
a-=;.:......-...q-,
OIR-r.l;~~=LJ+-------:-----...,
CBA~~---4-------W~---~
SBA~~---~-~~~~
CAB~~»-,
~B~~~--~~~~~~
r -
T Qj:'ii CHANNELS - - - - - - - - - - -
--1
I
I
I
I
I
(4)
:(20)
I
B1
I
I
I
I
I
I
- -------- -- -
-
------
en
CI)
CJ
'S
I
--"
CI)
C
~~----~~vr~----~~
..J
....
....
TO 7 OTHER CHANNELS
'LS648, 'LS649
a
(21)
OIR
(3)
CBA 23)
SBA (22)
CAB -:.;(1"-1)iJi:)o...,
~B (2)
r -
TOF'iiCHANNELS - - - - - - - - - - -
--1
10
I
Cl~~~~C1
:I
I
:-
~
A 1-+-+!-1-+~
I
I
B1
I
I
~
I
I
_____~~+-~u~
- - -- - - - - - - - - - - - - - - -
:
-_ ..
~~------~~v~-------~-J
TO 7 OTHER CHANNELS
Pin numbers shown are for OW, JT, and NT packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-1077
SN54LS646, SN54LS647, SN74LS646, SN74LS647
OCTAL BUS TRANSCEIVERS AND REGISTERS
logic symbols t
'LS647
'LS646
Ii"
(21)
DIR (3)
Ii"
G3
(21)
DIR (3)
3 ENI [BA)
SBA (22)
(1)
CAB
(2)
SAB
CBA (23)
.ITC4
SBA (22)
(1)
CAB
(2)
SAB
.IT G5
.ITC6
Bl
5
.ITC4
.ITG5
.IT C6
.ITG7
(20)
(20)
;;.1
3 ENI [BA)
3 EN2 [AB)
3 EN2 [AB)
CBA (23)
G3
Al
(4)
5
Al
"'5
5
7
"1
;;.1
7
(19)
(5)
B2
A2
B3
A3
r-
C
CD
<
()'
CD
til
B4
(8)
B5
B2
17)
(17)
(8)
116)
(9)
(15)
(10)
114)
(11)
(13)
B3
A3
B4
A4
AS
B5
115)
B6
A6
A6
(14)
B7
A7
1111
A8
B6
A7
113)
B8
B7
A8
tThese symbols are in accordance with ANSIIIEEE Std. 91·1984 and IEC Publication 617·12.
Pin numbers shown are for OW, JT, and NT packages.
2-1078
(19)
(18)
(16)
A5
-:;
(6)
(17)
A4
.IT
A2
(18)
~
~
Bl
.IT
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
B8
SN54LS648. SN54LS649. SN74LS648. SN74LS649
OCTAL BUS TRANSCEIVERS AND REGISTERS
logic symbols t (continued)
'lS649
'lS648
G
(21)
DIR (3)
G
G3
DIR
3 ENl [BAJ
3 EN2 [ABJ
CBA (23J
SBA 1221
111
CAB
121
SAB
141
CBA
D C4
SBA
lJG5
CAB
DC6
SA8
DG7
1201
,,1
81
5
Al
(23)
1221
111
121
G3
3 ENl [BAJ
3 EN2 [ABJ
D C4
lJ G5
D C6
DG7
(4)
5
Al
5"
5
7
15)
7
,,1
(6)
1191
B4
A4
85
A5
B6
A6
87
A7
88
A8
D
7
161
(7)
(81
(9)
(10)
1141
A7
(11)
A3
(15)
A6
(10)
B3
(161
AS
(9)
A2
1171
A4
(8)
151
B2
1181
A3
(71
D
7
A2
AS
1211
(3)
(13)
1111
tThese symbols are in accordance with ANSI/IEEE Std. 91·1984 and IEC Publication 617-12.
Pin numbers shown are for OW, JT, and NT packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1079
SN54LS646 THRU SN54LS649,
SN14LS646 THRU SN14LS649
OCTAL BUS TRANSCEIVERS AND REGISTERS
schematics of inputs and outputs
EQUIVALENT OF DIRECTION INPUTS
EQUIVALENT OF ALL OTHER INPUTS
Vee
VCC
9 kll NOM
INPUT
INPUT
_
A and B: Req
G, eAB and CBA: Req
SAB and SBA: Req
TYPICAL OF ALL 'LS646, 'LS648 OUTPUTS
=
10 kll NOM
6 kll NOM
TYPICAL OF ALL 'LS647, 'LS649 OUTPUTS
Vce
50 II NOM
OUTPUT
2-1080
= 15 kll NOM
=
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TeXAS 75265
SN54LS646, SN54LS648, SN74LS646, SN74LS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc ......................................................................... 7 V
Input voltage: Control inputs .................................................................. 7 V
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range: SN54LS646, SN54LS648 ............................ - 55°C to 125°C
SN74LS646, SN74LS648 ................................ aOc to 7aoC
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 15aoC
recommended operating conditions
SN54LS646/648
SN74LS646/648
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.5
0.6
V
Vee
Supply voltage
VIH
High~level
input voltage
VIL
Low~level
input voltage
IOH
High-level output current
-12
-15
rnA
IOL
Low-level output current
12
24
rnA
2
Pulse duration
tw
Setup time
tsu
before eABt or eBA t
Hold time
th
eBA or CAB high
15
15
eBA or CAB low
30
30
Data high or low
30
30
Aor B
15
15
Aor B
after eABt or eBA t
0
Operating free-air temperature
TA
V
2
ns
ns
ns
0
- 55
125
0
70
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST eONDITIONSt
Hysteresis
AorS
(VT+-VT_)
input
VIH=2V,
VIL = MAX
II
IOH =-3 mA
IOH - -12rnA
MAX
-1.5
0.4
0.2
0.4
2.4
3.4
2.4
3.4
2
0.25
IOL=12mA
0.4
0.25
0.4
0.35
0.5
Vee = MAX, VI = 7 V
0.1
0.1
Vee = MAX, VI- 5.5 V
0.1
0.1
20
20
20
20
A or B ports'
IOS§
Vee = MAX, VI = 2.7 V
Vee= MAX,
VI=O.4V
-40
Vee = MAX, Vo-OV
LS646
Vee = MAX
ICC
-0.4
-0.4
-0.4
-0.4
-225
-40
-225
Outputs high
91
145
91
145
Outputs low
103
165
103
165
Outputs disabled
103
165
103
165
91
145
91
145
Outputs high
LS648
V
V
2
A or 8 ports
A or B ports'
UNIT
V
Control inputs
Control inputs
IlL
TVP*
IOL=24mA
VIL =MAX
Control inputs
IIH
VIH = 2 V,
SN74LS646/648
MIN
0.1
IOH --15 mA
Vee = MIN,
VOL
MAX
-1.5
Vee = MIN
Vee = MIN.
VOH
TVP*
11=-18mA
Vee = MIN.
VIK
SN54LS646/648
MIN
Outputs low
103
165
103
165
Outputs disabled
120
180
120
180
V
mA
I'A
rnA
rnA
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*All typical values are at Vee = 5 V. TA = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
, For 110 ports, the parameters IIH and IlL include the off-state output current.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
2-1081
SN54LS646, SN54LS648, SN74LS646, SN74LS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3·STATE OUTPUTS
switching characteristics,
PARAMETER
Vee =S V, TA = 2sOe
FROM
TO
(INPUT)
(OUTPUTI
'LS646
TEST CONDITIONS
'LS648
MAX
TVP
MAX
15
25
15
25
ns
tpHL
23
35
24
40
ns
tPLH
12
18
12
18
ns
13
20
15
25
ns
26
40
37
55
ns
21
35
24
40
ns
33
50
26
40
ns
CAB or CBA
AorS
Aor B
B or A
tpHL
tpLH
SAB or SSAt
MIN
UNIT
TVP
tpLH
MIN
with Bus
tpHL
tPLH
input high
SAS or SSA
AorS
RL = 667 n,
CL = 45 pF,
See Note 2
with Bus
tpHL
tpZH
tpZL
Input low
G
A or 8
tpZH
tpZL
tPHZ
-I
-I
rC
CD
<
tpLZ
tpHZ
DIR
G
Aor B
DIR
RL=667n,
CL = 5 pF,
See Note 2
tpLZ
14
25
23
40
ns
33
55
30
50
ns
42
65
37
55
ns
28
45
23
40
ns
39
60
30
45
ns
23
35
28
45
ns
22
35
22
35
ns
20
30
24
35
ns
19
30
19
30
ns
t These parameters are measured with the internal output state of the storage register opposite to that of the input.
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
n'
CD
en
2-1082
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS647, SN54LS649, SN74LS647, SN74LS649
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH OPEN-COLLECTOR OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................... 7 V
Input voltage (control inputs) .................................................................. 7 V
Off·state output voltage (A and B ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range: SN54LS647, SN54LS649 ............................ - 55°C to 125°C
SN74LS647, SN74LS649 .............................. - oOe to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
recommended operating conditions
SN74LS647
SN54LS647
UNIT
SN74LS649
SN54LS649
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.5
0.6
VOH
High-level output voltage
5.5
5.5
V
IOL
Low-level output voltage
12
24
rnA
tw
Pulse duration
Setup time
tsu
before CAB t or CBA t
after CAB t or CBA t
CBA or CAB high
15
15
CBA or CAB low
30
30
Data high or low
30
30
Aor B
15
15
ns
->CJ
A or B
0
0
ns
c
Operating free-air temperature
TA
V
ns
(/)
Q)
Q)
Hold time
th
V
V
2
2
-55
125
0
70
°c
..J
l-
Ielectrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS647
PARAMETER
TEST CONDITIONSt
MIN
VCC = MIN,
VIK
Hysteresis
A or B input
(VT+-VT_I
IOH
0.1
VIH = 2 V,
VCC = MIN,
VIH = 2 V,
VIL = MAX
I
AorB
I All others
SN74LS649
MAX
MIN
0.4
VIL =MAX,
IOL=12rnA
0.2
0.4
0.1
0.25
UNIT
MAX
-1.5
0.4
IOL = 24 rnA
VCC= MAX
TYPt
-1.5
VOH = 5.5 V
VOL
II
TYP*
II =-18 rnA
VCC= MIN
VCC= MIN,
SN74LS647
SN54LS649
V
V
0.1
0.25
0.4
0.35
0.5
VI = 5.5 V
0.1
0.1
VI = 7 V
rnA
V
rnA
0.1
0.1
IIH
VCC= MAX, VI = 2.7 V
20
20
)JA
IlL
VCC= MAX, VI=O.4V
-0.4
-0.4
rnA
'LS647
VCC=MAX, Outputs open
ICC
'LS649
VCC= MAX, Outputs open
Outputs high
79
130
79
130
Outputs low
94
150
94
150
Outputs high
79
130
79
130
94
150
94
150
Outputs low
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
; All tvpical values are at Vee"" 5 V. TA = 2soe.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-1083
SN54LS647. SN54LS649. SN74LS647. SN74LS649
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH.OPEN·COLLECTOR OUTPUTS
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
FROM
TO
UNPUT)
(OUTPUT)
TEST CONDITIONS
'LS647
'LS649
MAX
TYP
MAX
22'
35
17
30
ns
tpHL
28
45
28
45
ns
tPLH
17
26
15
25
os
18
27
20
30
ns
33
50
37
55
ns
CAB or CBA
AorB
Aor B
BorA
tpHL
tpLH
SAB or S8At
MIN
UNIT
TYP
tPLH
MIN
with Bus
tpHL
tPLH
Input high
Aor B
SAB or SBAt
RL~667n,
CL=45pF,
See Note 2
29
45
28
45
ns
39
60
30
45
ns
19
30
26
40
ns
25
40
21
40
ns
33
50
34
50
ns
23
35
19
30
ns
25
40
27
45
ns
with Bus
tpHL
tPLH
tpHL
tPLH
input low
G
A or B
DIR
tpHL
--t
t These parameters are measured with the internal outputs state of the storage register opposite to that of the bus input.
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
-4
r-
C
CD
<
,;"
CD
en
2-1084
TEXAS •
INSTRUMENTS
POST OFFICE BOX ·655012 • DALLAS, TEXAS 75265
SN54LS651 THRU SN54LS653
SN74LS651 THRU SN74LS653
OCTAL BUS TRANSCEIVERS AND REGISTERS
02637, JANUARY. 1981 -REVISED MARCH 1988
• Bus Transceivers/Registers
• Independent Registers and Enables for A and
B Buses
SN54LS' ... JT PA"CKAGE
SN74LS' ..• OW OR NT PACKAGE
(TOPVIEWI
CAB
SAB
GAB
Al
• Multiplexed Real-Time and Stored Data
• Choice of True and Inverting Data Paths
• Choice of 3-State or Open-Collector
Outputs to A Bus
A2
A3
A4
• Dependable Texas Instruments Quality and
Reliability
DEVICE
'LS651
'LS652
'LS653
B OUTPUT
3-State
3-State
3-State
A OUTPUT
3-State
3-State
Open-collector
VCC
CBA
SA
GBA
B1
B2
B3
B4
B5
B6
B7
B8
A5
A6
A7
LOGIC
Inverting
True
Inverting
M
GND
SN54LS' ... FK PACKAGE
(TOPVIEWI
description
These devices consist of bus transceiver circuits. D-type
en
flip-flops, and control circuitry arranged for multiplexed
Q)
(J
transmission of data directly from the data bus or from
4
the internal storage registers. Enable GAB and GBA are
provided to control the transceiver functions. SAB and
3 2
oS;
1
Q)
SBA control pins are provided to select whether realtime
C
or stored data is transferred. A low input level selects
real-time data, and a high selects stored data. The
following examples demonstrate the four fundamental
lI-
..J
bus· management functions that can be performed with
the 'LS651, 'LS652, and 'LS653.
12 1314 151617 18
!;;:~~~!lllD~
Cl
NC - No internal connection
~
GAB GBA CAB CBA SAB
L
L
X
X
X
~
GAB GBA CAB
SBA
L
H
::'~=~~I~"r::I':.'1i ~=::i:; :':":::::~~I not
X
CBA SAB
X
L
SBA
X
REAL·TlME TRANSFER
BUSA TO BUS B
REAL·TIME TRANSFER
BUS BTO BUSA
PRODUCTION DATA doc....nls c••llin informltlon
currant II of publiClti.n dlle. Products ...IDr. . .
,pICiliclli... per the llnal .1 T••I. Instru.I'"
H
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1085
SN54LS651 THRU SN54LS653
SN74LS651 THRU SN74LS653
OCTAL BUS TRANSCEIVERS AND REGISTERS
'--v---"
'-.,---.'
GAB GBA CAB CBA SAB
X
X
H
t
X
L
X
l
H
X
X
X
SBA
GAB GBA CAB
CBA SAB
Horl Horl H
H
l
X
X
X
SBA
H
TRANSFER
STOREOOATA
TOAANDIOR B
STORAGE FROM
AANOIOR B
Oata on the A or B data bus, or both, can be stored in the internal 0 flip-flop by low-to-high transitions at the appropriate
clock pins (CAB or CBA) regardless of the select or enable control pins. When SAB or SBA are in the real-time transfer mode,
it is also possible to store data without using the internal O-type flip-flops by simultaneously enabling GAB and GBA.
In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are
at high impedance, each set of bus lines will remain at its last state.
The SN54lS651 through SN54lS653 are characterized for operation over the full military temperature range of - 55·C
to 125 ·C. The SN74LS651 through SN74LS653 are characterized for operation from O·C to 70 ·C.
FUNCTION TABLE
...
GAB GBA
l
H
L
H
X
H
H
H
X
L
L
L
L
L
L
H
H
H
INPUTS
CBA
CAB
H or L H or L
t
t
t
H or L
t
t
t
H or L
t
t
SAB
SBA
X
X
X
X
X
X
Input
X
X
Input
X
X
Not specified
Input
Hold A, Store B
X
X
Output
Input
Output
Input
Store 8 in both registers
Real-Time 8 Data to A Bus
Input
Output
X
X
X
L
H
X
H or L
X
L
H
X
X
L
X
H
H or L
X
H
X
L
H or L
H or L
OPERATION OR FUNCTION
'lS651 , 'LS653
'LS652, 'LS654
DATA 1/0'
A1 THRUA8 B1 THRU B8
H
H
Input
Output
Input
Isolation
Isolation
Store A and 8 Data
Store A and B Data
Not specified Store A, Hold B
Output
Store A in both registers
Output
Stored B Data to A Bus
Real-Time A Data to B 8us
Store A, Hold B
Store A in both registers
Hold A, Store B
Store B in both registers
Real-Time B Data to A 8us
Stored B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and
Stored A DatB to B Bus and
Stored B Data to A Bus
Stored B Data to A 'Bus
• The data output functions·may be enabled or disabled by various signals at the GAB and 13SA inputs, Data input functions are always
enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
2-1086
TEXAS •
INSTRUMENTS
POST OFFICe BOX 655012 • DAllAS. TEXAS 75265
SN54LS651 THRU SN54LS653
SN74LS651 THRU SN74LS653
OCTAL BUS TRANSCEIVERS AND REGISTERS
logic diagrams (positive logic)
'LS651, 'LS653
GBA"";;;;"-:::----~~----------------~------,
CBA ~~=-------+-------:-----c:---------t
SBA -7.iC'--:,------+-----l
CAB
SAB --=------+--iH
:»----_+___,
,
r
10F8
CHANNELS
C1
<*>----+-H
'-~illtt------~~W(2~O~) B1
(4)
A1---.-r-+H
I
I
I
I
..J
~--------------~vr---------------J
TO 7 OTHER CHANNELS
'LS652
GBA --';;;;"--;:---~--~--------------~------~
CBA -=~=-------+---------------~ ;>o---+-t
SBA -7.'C'--:,-------+-----l
CAB
SAB -='------+-H
-,
r
I
(20)
H-+-;-'-B1
(4)
A1-+-0....-++. .
v
TO 7 OTHER CHANNELS
Pin numbers shown are for DW, JT or NT packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1087
SN54LS651 THRU SN54LS653
SN14LS651 THRU SN14LS653
OCTAL BUS TRANSCEIVERS AND REGISTERS
logic symbols t
'LS651
GBA (21)
GAB (3)
CBA (23)
SBA (22)
(1)
CAB
(2)
SAB
'LS652
GBA (21)
ENl [BA]
EN2 [AB]
C4
GAB --:(",3,.,.)_ - I
CBA ...:(::23:.<.)
C4
(22)
G5
SBA
(1)
CAB
C6
(2)
SAB
G7
_--.,!>
G5
(20)
(18)
117)
(8)
(16)
(9)
115)
(10)
114)
(11)
113)
B3
B6
B7
A8
B8
B8
c:;-
CD
en
'LS653
GBA (21)
GAB (3)
CBA (23)
SBA (22)
(1)
CAB
(2)
SAB
ENl [BA]
EN2 [AB]
C4
G5
C6
120)
(4)
Bl
Al
A2
(5)
119)
(6)
118)
(7)
117)
(8)
(16)
(9)
(15)
(10)
(14)
(11)
(13)
B2
A3
B3
A4
84
AS
85
A6
86
A7
B7
A8
88
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Pub/ication 617-12.
Pin numbers shown are for OW, JT, or NT packages.
2-1088
B4
B5
A7
B7
(13)
A8
(7)
B2
A6
B6
(14)
A7
C
CD
<:
(18)
AS
B5
(15)
A6
(6)
A4
B4
(16)
AS
(19)
A3
B3
(17)
A4
(5)
A2
B2
A3
Bl
Al
(19)
A2
(20)
(4)
Bl
Al
-I
-I
r-
ENl [BA]
EN2 [AB]
TEXAS .."
INSTRUMENlS
. POST OFFICE BOX 65501 ~ • DALLAS, TEXAS 75265
SN54LS651. SN54LS652. SN74LS651. SN74LS652
OCTAL BUS TRANSCEIVERS AND REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc ...............................................................7 V
Input voltage: Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
liD ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54LS651, SN54LS652 . . . . . . . . . . . . . . . . . . . . . . . . - 55°C to 125°e
SN74LS651, SN74LS652. . . . . . . . . . . . . . . . . . . . . . . . . .. oOe to 700 e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°e to 150°C
recommended operating conditions
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
tw
Setup time
Hold time
after CAB t or eBA t
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
V
2
0.7
0.8
-12
-15
mA
V
24
mA
eBA or CAB high
15
CBA or CAB low
15
15
Data high or low
15
15
Aor B
15
15
ns
Aor 8
0
0
ns
15
-55
Operating free--air temperature
TA
UNIT
MIN
12
before CAB tor eBA t
th
SN74LS651
SN74LS652
2
Pulse duration
'su
SN54LS651
SN54LS652
125
ns
70
0
°c
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN74LS651
SN54LS651
PARAMETER
TEST CONDITIONSt
MIN
VIK
VOH
IOH =-3mA
IOH=-12rnA
2.4
TYP* MAX
-1.5
3.4
VIH - 2 V,
MIN
UNIT
TYP* MAX
-1.5
2.4
V
2
IOL-12mA
0.25
0.4
IOL = 24 mA
0.25
0.4
0.35
0.5
Control inputs
Vce- MAX,
VI = 7 V
0.1
0.1
A or B ports
Vce = MAX,
VI-5.5V
0.1
0.1
20
20
A or B ports'
Vce= MAX,
VI = 2.7 V
VCe= MAX,
VI=O.4V
Vce - MAX,
VO=OV
LS651
VCe= MAX
ICC
LS652
20
20
-0.4
-0.4
-0.4
-0.4
A or B ports'
lOS!
V
3.4
2
IOH = -15mA
VIL = MAX,
Control inputs
IlL
VIH = 2 V,
Vec = MIN,
Control inputs
IIH
11=-18mA
VCC= MIN,
VIL = MAX,
VOL
II
Vce = MIN,
SN74 LS652
SN54LS652
-40
-225
-40
- 225
Outputs high
95
145
95
145
Outputs low
103
165
103
165
Outputs disabled
103
165
103
165
Outputs high
95
145
95
145
Outputs low
103
165
103
165
Outputs disabled
120
180
120
180
V
rnA
~A
rnA
rnA
rnA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
i All typical values are at VCC
=
5 V, TA
= 25°C.
§ Not more than one output should be shorted at a time. and duration of the short-circuit should not exceed one second.
, For 1/0 ports. the parameters IIH and IlL include the off-state output current.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-' 089
SN54LS651, SN54LS652, SN74LS651, SN74LS652
OCTAL BUS TRANSCEIVERS AND REGISTERS
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER
tPLH
FROM
TO
(INPUT!
(OUTPUT!
Clock
tpHL
tPLH
Bus
tpHL
tpLH
Select, with
tpHL
bus input
high t
tPLH
Select, with
'LS651
TEST CONDITIONS
MIN
Bus
Bus
Bus
RL
= 667 n,
CL
= 45 pF,
See Note 2
bus input
tPHL
tpZH
tPZL
•
tpZH
tpZL
tPHZ
tPLZ
tpHZ
-I
-I
.oC1I
!S.
n
C1I
III
tPLZ
lowt
GBA
A Bus
GAB
B Bus
GBA
A Bus
GAB
B Bus
RL = 667
n,
CL
= 5 pF,
See Note 2
'LS652
MAX
TYP
MAX
14
24
15
25
ns
23
35
24
36
ns
9
18
12
18
ns
20
30
13
20
ns
31
47
23
35
ns
22
33
21
32
ns
23
35
33
50
ns
19
30
15
23
ns
29
44
30
45
ns
40
60
36
54
ns
19
29
20
30
ns
26
40
25
38
ns
25
38
25
38
ns
19
30
19
30
ns
25
38
25
38
ns
19
30
19
30
ns
MIN
tplH = propagation delay time, low-to-high-Ievel output.
tpHL = propagation delay time. high-to-Iow-Ievel output
tpZH = output enable time to high level
tpZL = output enable time to low level
tpHZ = output disable time from high level
tplZ = output disable time from low level
t These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
schematics of inputs and outputs
EQUIVALENT OF GAB INPUTS
EQUIVALENT OF ALL OTHER INPUTS
VCC
Vcc
TYPICAL OF ALL OUTPUTS
VCC
9k!:2NOM
INPUT
INPUT
OUTPUT
A and B: Req
GSA, CAS and CSA: Req
SAB and SBA: Req
2-1090
= 15 k!:2 NOM
= 10 k!:2 NOM
= 6 k!:2 NOM
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
TYP
SN54LS653, S1174LS653
OCTAL BUS TRANSCEIVERS AND REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee ......................................................... 7 V
Input voltage: All inputs and A 1/0 ports ................................ . . . . . . . . .. 7V
B 1/0 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54LS653........................ - 55 °e to 125°e
SN74LS653 ........................... ooe to 70 0 e
Storage temperature range ........................................
- 65 °e to 150 0 e
recommended operating conditions
SN64LS663
VCC
Supply voltage
VIH
High~level
VIL
Low-level input voltage
input voltage
High-level output voltage
I Aports
IOH
High-level output current
I
IOL
Low-level output current
Pulse duration
before CAB t or CBA t
TA
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
5.5
5.5
V
12
15
mA
24
mA
V
2
Bports
CBA or CAB high
15
15
CBA or CAB low
30
30
Data high or low
30
30
Aor B
15
15
ns
Aor B
0
0
ns
•
ns
fI)
CI)
(.)
"S;
Hold time
th
MAX
12
Setup time
tsu
UNIT
NOM
2
VOH
tw
SN74LS663
MIN
after CAB t or CBA t
Operating free-air temperature
-55
125
0
70
CI)
C
'c
..J
~
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH
IOH
B ports
A ports
VOL
II
IlL
11=-18mA
VCC= MIN,
VIH
= 2V,
VIL = MAX
Vee= MIN,
VOH = 5.5 V
Vee= MIN,
VIH = 2 V,
VIL = MAX
TVP*
2.4
3.4
SN74LS653
MAX
MIN
-1.5
I
I
IOH =-3mA
I
IOH=-15mA
I
I
IOL=12mA
IOH = -12mA
2.4
UNIT
TVP* MAX
-1.5
2
V
2
0.1
0.25
0.1
0.4
IOL = 24mA
0.25
0.4
0.35
0.5
Vce= MAX,
VI = 7 V
0.1
0.1
Vee- MAX,
VI=5.5V
0.1
0.1
20
20
20
20
-0.4
A or B ports'
Vee= MAX,
VI = 2.7 V
Vee= MAX,
VI=O.4V
Control inputs
B ports
Vee= MAX.
-0.4
VO=OV
-40
Outputs high
LS653
Vee= MAX
ICC
LS654
V
3.4
A or 8 ports
A or B ports'
IOS§
Vce- MIN,
MIN
Control inputs
Control inputs
IIH
TEST eONDITIONSt
SN54LS663
-0.4
-225
145
95
-40
95
-225
145
103
165
103
165
Outputs disabled
103
165
103
165
95
145
95
145
105
170
105
170
120
180
120
180
Outputs low
Outputs disabled
V
mA
",A
mA
-0.4
Outputs low
Outputs high
mA
mA
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vee
5 V, TA
25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
, For I/O ports, the parameters IIH and IlL include the off-state output current.
*
=
=
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-1091
SN54lS653, 'SN74lS853
OCTAL BUS TRANSCEIVERS AND REGISTERS
switching characteristics. Vee - 5 V. TA - 25°e
PARAMETER
tpLH
tpHL
tpLH
tPHL
tpLH
C
<
c;'
CD
o
TYP
MAX
25
26
15
24
10
20
21
16
38
39
23
36
18
30
32
24
38
26
57
39
ns
A Bus
34
23
61
36
ns
B Bus
32
22
4B
33
ns
24
20
23
37
19
25
26
19
36
30
35
55
29
3B
39
29
A Bus
CAB
B Bus
A Bus
B Bus
B Bus
A Bus
tpLH
tpHL
SBAt
(with B high)
A Bus
tpLH
tpHL
SBAt
(with Blow)
tpLH
tpHL
SABt
(with A high)
tpLH
tpHL
tpLH
tpHL
tpZH
tpZL
tpHZ
tpLZ
CD
Tq
(OUTPUT)
CBA
tPHL
tpLH
tpHL
=1r-
FROM
(INPUT)
SABt
TEST CONDITIONS
RL = 667 n,
See Note 2
MIN
CL = 45 pF,
B Bus
(with A lowl
a::
100mW
VI
Q)
(,)
description
These synchronous presettable counters feature an internal carry look-ahead for cascading in high-speed
counting applications. The 'LS668 are decade counters
and the 'LS669 are 4-bit binary counters. Synchronous
operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident
with each other when so instructed by the count-enable
inputs and internal gating. This mode of operation helps
eliminate the output counting spikes that are normally
associated with asynchronous (ripple-clock) counters.
A buffered clock input triggers the four master-slave
flip-flops on the rising (positive-going) edge of the clock
waveform.
A
B
4
5
NC
6
"S;
Q)
C
....I
C
o
lI-
8
1
CulCl1-
0zzzCl
r-
1
D
~
I
1141
I-~
-r;o~)
........... I>Cl
I-~
.F
L_
CD
<
»-
c:;'
CD
th
DATAC
DATA 0
151
~
-
161~
,
~
I
~
I
r
r
1121
~I>Cl
~~
rkYbJF-Fr-IO
111)
'---< I>Cl
~1
-----.--...
1151
L....t.
'---==f
Pin numbers shown are for D. J, N, and W packages.
2-1094
I--r;o
.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
aD
SN54LS669, SN74LS669
SYNCHRONOUS 4·811 UP/DOWN COUNTERS
logic diagram (positive logic) (continued)
SN54LS669. SN74LS669. BINARY COUNTERS
C~OCK
(2)
UfO
11)
•
OATAA.:.:13;.;.)+---L---1
en
Q)
C)
.S;
DATABJI~4)1==1==)-t-----~-+----------------~~---t----~
Q)
o
...J
lI-
DATAC!15~)X==l~~~----tl-t-r--------~-----l~---r----~
DATAD~16~)==JL~~-------t~+-r-------------------------~
L-____~==~~~~-~~------------------------------~(1~5)RCO
Pin numbers shown are for D, J, N, and W packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1095
SN54LS668, SN74LS668
SYNCHRONOUS 4-BIT UP/DOWN COUNTERS
'LS668 DECADE COUNTERS
logic symbol t
typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1. Load (preset) to BCD seven'
2. Count up to eight, nine (maximum), zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum). nine, eight, and seven
"4) QA
'31
D
61
~
141
(12)
lSI
'") OD
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
LOAD~
-t
-t
rC
eD
<
DATA
INPUTS
5'
eD
I
A.J
1..
s.J
i
c.J
1..
L..
i
,r-
D
(I)
CLOCK
P AND T
IL-+-_.:....;__________. . .
I
I
I
~--------~~
I:
I
Os
°c
I
----r--"'j"l
'--_ _ _ _~-.....!
- - -I - r - n :
I
I
___ -J
___ ,
Oo ____
I
I ~i----------~---~-~---------...I
I I
L-
LiJ
II
RCa - - -..J
,
___
IL...-JI
II II
:7118
l j l. .
9
II
0
2
11_
_--COUNT UP - - -••
2
12
INHIBIT--I
LOAD
2-1096
.-
,...:"----~...;
; I!_ _ _ _ _ _ _ _...111
___ .,j
TEXAS •
INSIRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
LJ
I
I
I
1
0
9
8
7
~ COUNT DOWN - - - - _
SN54LS669, SN74LS669
SYNCHRONOUS 4-BIT UP/DOWN COUNTERS
'LS669 BINARY COUNTERS
logic symbol t
r--,=",=,-.,
typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1.
2.
3.
4.
Load (preset) to binary thirteen
Count up to fourteen, fifteen (maximum). zero, one, and two
Inhibit
Count down to one, zero (minimum), fifteen, fourteen, and thirteen
tThis symbol is in accordance with ANSI/lEEE Std. 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
DATA
, INPUTS
C
Ir---':"'. - .-.J
L-_
D
Ir---'I - .-.J
L-_
CLOCK
- --I
_oJ
I
UfO
t
P AND T --'L-+-_~
,
__________-'
___ I
LJ
-I
RCO - -_......
: 13
U.
14
15
'
I
I
I
0
2,
2
I 2
I·_--COUNT UP - - -...I--'NH'8IT-..I
I
I
I
1
LJ
0
15
14
13
~COUNTDOWN------
LOAD
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1097
SN54LS668, SN54LS669, SN14LS668, SN14LS669
SYNCHRONOUS 4~BIT UP/DOWN COUNTERS
schematics of inputs and outputs
EQUIVALENT OF EACH ,INPUT
TYPICAL OF ALL OUTPUTS
o
------Cl
3 2
1
description
The SN54LS670 and SN74LS670 MSI 16-bit TTL
register files incorporate the equivalent of 98 gates. The
register file is organized as 4 words of 4 bits each and
separate on-chip decoding is provided for addressing
the four word locations to either write-in or retrieve
data. This permits simultaneous writing into one location and reading from another word location.
en
CI)
(.)
-S;
9 10111213
CI)
C
..oJ
NC -
No internal connection.
Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined by the
write-address inputs A and B in conjunction with a write-enable signal. Data applied at the inputs should be in its true form.
That is, if a high-level signal is desired from the output, a high-level is applied at the data input for that particular bit location.
The latch inputs are arranged so that new data will be accepted only if both internal address gate inputs are high. When this
condition exists, data at the 0 input is transferred to the latch output. When the write-enable input, GW, is high, the data inputs are inhibited and their levels can cause no change in the information stored in the internal latches. When the read-enable
input, GR, is high, the data outputs are inhibited and go into the high-impedance state.
lI-
The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding gates
are used to complete the address for reading a word. When the read address is made in conjunction with the read-enable
signal, the word appears at the four outputs.
This arrangement~data-entry addressing separate from data-read addressing and individual sense line~eliminates recovery
times, permits simultaneous reading and writing, and is limited in speed only by the write time (27 nanoseconds typical) and
the read time (24 nanoseconds typical). The register file has a nondestructive readout in that data is not lost when addressed.
All inputs except read enable and write enable are buffered to lower the drive requirements to one Series 54LS/74LS standard
load, and input-clamping diodes minimize switching transients to simplify system design. High-speed, double-ended ANDOR-INVERT gates are employed for the read-address function and have high-sink-current, three-state outputs. Up to 128 of
these outputs may be bus connected for increasing the capacity up to 512 words. Any number of these registers may be
paralleled to provide n-bit word length.
The SN54LS670 is characterized for operation over the full military temperature range of - 55° C to·125° C; the SN74LS670
is characterized for operation from 0° C to 70° C.
PRODUCTION DATA doc.menls conlain information
current 8S of publication date. Products conform to
specifications per the terms of Taxas Instruments
~~~':!:~~i~8i~':I~~i ~:=~:i:; :'ID::::~:~~ nDt
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-1103
SN54LS610. SN14LS610
4·8Y·4 REGISTER FILES WITH 3·0UTPUTS
logic symbol t
RAM 4x4
O}IA~
1
3
0}2A~3
1
C4 [WRITE)
(101 01
Dl
(91 02
D2
D3
(21
(71 03
D4
(31
(61 04
tThis symbol is in accordance with ANSI/IEEE Std. 91-1984 and lEe Publication 617-12.
Pin numbers shown are for D. J. N. and W packages .
•
READ FUNCTION TABLE (SEE NOTES A AND 01
WRITE FUNCTION TABLE (SEE NOTES A. B. AND CI
WRITE INPUTS
-t
-t
WB
L
L
WA
L
H
C
H
L
CD
H
n'
CD
X
r-
<
en
NOlES:
WORD
0
O=D
GW
L
L
00
H
L'
L
X
H
00
00
00
1
2
3
00
0=0
00
00
00
O=D
00
00
00
00
00
OUTPUTS
READ INPUTS
A. H"" high level, L == low level. X "" irrelevant, Z
GR
L
01
02
03
Q4
WOBI
WOB2
WOB3
WOB4
H
L
W1Bl
W1B2
W1B3
W1B4
L
L
W2Bl
W2B2
W2B3
W2B4
H
H
L
W3Bl
W3B2
W3B3
W3B4
X
X
H
Z
Z
Z
Z
RB
L
RA
L
00
L
00
0=0
H
00
= high impedance (off)
B. (0'" 0) '" The four selected internal flip·flop outputs will assume the states applied to the four external data inputs.
C. 00'"" the level of Q before the indicated Input conditions were established.
D. WOBl " The first bit of word 0, etc.
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EOUIVALENTOF EACH INPUT
------+--Vee
n
-
vee
100
NOM
Req
INPUT
--
IW
u'"
L.._-4I-_ _
~i'
~,
,~
n7
Any 0, R, or W: Req
GR: Req
= 20 kO NOM
= 6.67 kO NOM
GW: Req = 10 kO NOM
2-1104
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
OUTPUT
SN54LS670, SN74LS670
4-BY-4 REGISTER FILES WITH 3-STATE OUTPUTS
logic diagram (positive logic)
Q1
(/)
Q)
(.)
-S;
Q)
C
..J
lI-
1121
WB
RS
WA
'--v---'
GR
RA
"--y----J
READ INPUT
WRITE INPUT
Pin numbers shown are for 0, J, N, and W packages.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-1105
SN54LS670, SN74LS670
4·8Y·4 REGISTER FILES WITH 3·STATE OUTPUTS
absolute maximum ratings over operatingfree·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Off-state output voltage
Operating free·air temperature range: SN54LS670
SN74LS670
Storage temperature range
7V
7V
5.5V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C
recommended operating conditions
SN54LS670
MIN
Supply voltage,
Vee
4.5
High~level
Setup times, high- or low-level data
write enable; t 5U (0)
(see Figure 2)
Write select with respect to
write enable, tsulW)
Data input with respect to
Hold times, high- or low-level data
write enable, th(DI
C
(see Note 2 and Figure 2)
Write select with respect to
<
(i'
latch time for new data, tlatch (see Note 3)
Operating free-air temperature range, T A
CD
en
NOTES:
NOM
5.5
4.75
5
MAX
UNIT
5.25
V
2.6
rnA
8
rnA
25
25
n.
10
10
n'
15
15
ns
15
15
n.
5
5
ns
write enable, th(W)
CD
MIN
4
Data input with respect to
,...
5
SN74LS670
MAX
1
output current, IOH
Low-level output current, IOL
Width of write-enable or read-enable pulse, tw
-I
-I
NOM
ns
25
25
-55
125
0
70
°c
1. Voltage valuBs are with respect to network ground terminal.
2. Write-select setup time will protect the data written into the previous address. If protection of data in the previous address is not
required, tsu(W) can be ignored as any address selection sustained for the final 30 ns of the write-enable pulse and during th(W)
will result in data being written into that location. Depending on the duration of the input conditions, one or a number of
previous addresses may have been written into.
3. Latch time is the time allowed for the internal output of the latch to assume the state of new data. See Figure 2. This is important
only when attempting to read from a location immediately after that location has received new data.
2-1106
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN54LS670, SN74LS670
4·BY·4 REGISTER FILES WITH 3·STATE OUTPUTS
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
VIK
I nput clamp voltage
VOH High-level output voltage
VOL Low-level output voltage
Off-state output current,
IOZH high-level voltage applied
Off-state output current,
10Zl
II
low-level voltage applied
Vee - MIN.
II - -18 mA
Vee~
VIH - 2 V,
MIN,
Vee - MIN,
MAX,
VIH
Vee~
MAX,
VIH~2V,
Vee· MAX,
VI
~
7V
~
MAX,
High-level input current
Vee~
VI
MAX,
~0.4V
lOS
Short-circuit output current §
Vee~
MAX
ICC
Supply current
Vee~
MAX,
2.4
-1 mA
SN74LS670
MAX
~
~
TVP*
MAX
0.8
-1.5
-1.5
3.4
2.4
0.4
UNIT
V
0.7
8 mA
V
V
V
3.1
0.25
0.4
0.35
0.5
V
2.7V
20
20
"A
VO~O.4V
"A
VO~
2V,
MIN
2
0.25
10L - 4 mA
10L
Vee~
maximum input voltage
Low-level input current
TVP;
10H - -2.6mA
VIH-2V,
VIL· Vil max
Input current at
~
10H
VIL"" VIL max
VI· 2.7 V
IlL
MIN
2
Vee
IIH
SN54L5670
TEST eONDITIONst
-20
-20
Any D, R, orW
0.1
0.1
GW
0.2
0.2
GR
Any 0, R, orW
0.3
0.3
20
20
GW
40
40
GR
Any D, R, orW
60
60
-0.4
-0.4
GW
-0.8
-0.8
GR
-1.2
-1.2
-130
-30
See Note 4
30
-30
50
30
mA
"A
fIj
Q)
(J
mA
.s:
-130
rnA
C
50
mA
Q)
...I
II--
tFor cond it ions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAil typical values are at Vee""" 5 V, T A = 25° C.
!:*Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 4: Maximum lee is guaranteed for the following worst-case conditions: 4.5 V is applied to all data inputs and both enable inputs, all
address inputs are grounded and all outputs are open.
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER
tpLH
FROM
TO
(INPUT)
(OUTPUT)
Read select
AnyQ
tPHL
tpLH
Write enable
AnyQ
Data
AnyQ
tPHL
tplH
tpHl
tPHZ
eL~15pF,
Read enable
AnyQ
tpLZ
RL~2k!l,
See Figures 1 and 2
el~15pF,
RL~2k!l,
See Figures 1 and 3
eL-15pF,
tPZH
tpZl
TEST CONDITIONS
RL~2k!l,
See Figures 1 and 4
eL
~
5 pF,
RL~2kll,
See Figures 1 and 4
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
TVP
MAX' UNIT
23
40
25
45
26
45
28
50
25
45
23
40
15
35
22
40
30
50
16
35
ns
ns
ns
ns
ns
2-1107
SN54LS670, SN74LS670
4·BY·4 REGISTER FILES WITH 3·STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
NOTES:
A. C L includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
LOAD CIRCUIT
FIGURE 1
~'------""\- - - - - - - - - - - 3 V
1.3 V
1.3 V
I
I ..._______________ 0 V
WRITE.SELECT
INPUT WA or WB
(See Not. Al
--l t-- t,u(WI
-----1
I
DATA INPUT
~:~~:t~~lor 04
-----+-""\..,
~.3V I
I
/4- th (WI
,,~:. _ _ _ _ _ _ _ _ OV
~th(Dl
- - - " " " ~ tw--l
t1.3V
3 V
1
I.----.t- t,u(ol
I
~~~~~~AaLE
I
I
l~:.
__ ______
3V
--OV
I+-- 'latch - - - - ,
READ·SELECT
INPUT RA or Ra
(See Note BI
\1~V
)'1.3 V
-------',
I.
I
!--tPHL-!
-- -
--::
t PLH,
\1.3'-___Jt·~ __
OUTPUT
01,02,03, or 04
Ir---VOH
V
VOL
VOLTAGE WAVEFORMS (S1 AND S2 ARE CLOSED I
NOTES:
A. High-level input pulses at the ,eJect and data inputs are illustrated; however, times associated with low-level pulses are measured
from the same reference points.
B. When measuring delay times from a read-select input, the read-enable input is low.
C. Input wav'etorms are supplied by generators having the following characteristics: PRR 010; 2 MH:Z, Zout :0:::= 50 n, duty cycle'" 50%.
tr EO;. 15 ns, tr ~ 6 ns,
FIGURE 2
2-1108
.
TEXAS'"
INSTRUMENTS
POS} OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN54LS670. SN74LS670
4·BY·4 REGISTER FILES WITH 3·STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
\-------- - --- 3V
J3V
OATAINPUT
01,02,03, or 04
OV
I
~i
WRITE-ENABLE
INPUTGW
____ ________
~~
!--'PLH.,
~~ __ ~}_3V
OUTPUT
01,02,03, or 04
VOLTAGE WAVEFORM 1 (S1 AND S2 ARE CLOSEDI
3V
DATA INPUT
D1, 02, 03, or 04
(fj
Q)
- - - - - - - - - - ov
----'------J~
WRITE-ENABLE
INPUTGW
t-:~
,~
----,
OUTPUT
01,02,03, or 04
_
_
_
_
_
3V
--
C
~ '_P_LH_______
r------+'PHL
~'r
....Jr,~
\.1._3_V_ _ _ _ _ _ _ _ _ _ _ _
.2
>
Q)
...J
OV
l-
I"
n
_
"
VOLTAGE WAVEFORM 2 (Sl AND S2 ARE CLOSEDI
NOTES:
A. Each select address is tested. Prior to the start of each of the above tests both write and read address inputs are stabilized with
WA = RA and Ws = RB- During the test GR is low.
8. Input waveforms are supplied by generators having the following characteristics: PAR";;; 1 MHz, Zout -::::; 50
n, duty
cycle';;;; 50%,
tr .;;;; 15 ns, tr .:;;; 6 ns.
FIGURE 3
READ~
tf-3~________ ::
UV
~\.._______________
ENABLE
: - -tp Z L
------1
WAVEFORM 1
:I
Sl closed,
(See Note A)
:
52 open
I-tPLZ--1
-t----~4,5V
1.3 V
I
(See Note A)
Slopen,
S2closed
l
I
:
~tPZH----t
WAVEFORM 2
I
I
51 and
I'n_L
I
S2c1osed
.:. 1.5V
-,----VOL
r-tpHz4 0.5 VO.5 V
~
_ _ _ _ _..:'
.J-----VOH
'" Sl
r
~~·~~-~ov
and
'1.5 V
52 closed
VOL TAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS
NOTES:
A. Wavetorms 1 is for an output with internal conditions such that the output is low except when disabled by the read·enable input.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the read·enable input.
S. When measuring delay times from the read·enable input, both read-select inputs have been established at steady states.
C. Input waveforms are supplied by generators having the following characteristics: PRR ~ 1 MHz, Zout ~ 50 n, duty cycle ~ 50%,
tr
~
15 ns, tr
~
6 ns.
FIGURE 4
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
2-1109
•
2-1110
SN54LS611, SN54LS612, SN14LS611, SN14LS612
4·81T UNIVERSAL SHIFT REGISTERS/LATCHES
WITH 3·STATE OUTPUTS
02638, JANUARY 1981 - REVISED MARCH 1988
SN54LS671, SN54LS672, . ,J PACKAGE
SN74LS671, SN74LS672. , ,OW OR N PACKAGE
(TOP VIEWI
• 4-Bit Universal Shift Registers/Latches
• Multiplexed Outputs for Shift Register
or Latched Data
SER R
SRCK
A
B
C
• Choice of Direct SR Clear I'LS671) or Syn·
chronous SR Clear ('LS672)
• 3-Stata Outputs Drive Bus Lines Directly
• Expandable to Any Word Length
description
The 'LS671 and 'LS672 each contain a 4-bit universal
shift register (similar to the 'LS 194A) and a 4-bit
storage register (similar to the 'LS175) multiplexed to a
3-state output stage (similar to the 'LS258), The user
has the option of selecting the shift or storage register
via the register/shift select input R/S, The 'LS671 has a
direct-overriding shift register clear while the 'LS672
features a synchronous shift register clear. The shift
register has four distinct modes of operation, namely:
VCC
CASC
QA
QB
Qc
Qo
SO
Sl
G
R/S
SER L
SRCLR
RCK
GNO
SN54LS671, SN54LS672 .. ,FK PACKAGE
(TOPVIEWI
Inhibit clock (do nothing)
Shift right (in the direction QA toward QO)
Shift left (in the direction QO toward QA)
Parallel (broadside) load
~a:
U
~ ffi ~~
«cncn>U
3
B
2
1 20 19
4
•
5
6
A cascade output for the shift register is provided so
that full shift register functionality is provided even
while the outputs are in the high-impedance mode. The
cascade output presents QA data in the shift-left mode,
QO data in the shift-right mode.
7
8
9 10111213
1j
~1~1t!)
a:t!)a:
en
Both the shift register clock and the latch clock are
triggered on the positive transition. The output control
(G) activates QA thru QO when low, it places QA thru
QO into the high-impedance state when high.
PRODUCTION DATA d••umants .ontain information
currant as af pubiicatiDR data. Products conform to
spacifications par the tarms of TaxI. Instruments
:~:=~~;·i~:I-::.ri ~:~:~:fn :.~o::;:::.::.s
nat
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1111
SN54LS671. SN54LS672. SN74LS671. SN74LS672
4·81T UNIVERSAL SHIFT REGISTERS/LATCHES WITH 3·STATE OUTPUTS
logic diagram (positive logic)
G (12)
RiS 111)
RCK~19~f
______________________________-4~
SRCLR...:.18::..)_ _ _ _~
so
__- '
1
114)
'LS671
R
(1)
20
SER R
•
(18)
CA
14)
-I
-I
.-
C
CD
<
5'
CD
(I)
c
15)
SER L _17_)
------"G~=t:j:f:**t1
Co
Pin numbers shown are for OW, J and N packages.
2-1112
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54LS671, SN54LS672, SN74LS671, SN74LS672
4·81T UNIVERSAL SHIFT REGISTERS/LATCHES WITH 3·STATE OUTPUTS
logic symbols t
'LS672
'LS671
ii
MUX
1121
RIS (111
1,24/2,23
EN22
G21
1191
ii
CASC
MUX
1121
1,24/2,23
EN22
RIS (111
1191
CASC
G21
RCK (91
RCK (91
SRG4
SRG4
SRCK
1181 QA
1181 QA
B (41
(171 QB
C (51
1161 Qc
0(61
SEA L (71
0(61
3,40
(151 00
2,40
SER L (71
3,40
(171 QB
3,40
1161 Qc
3,40
2,40
(15)
II
en
Q)
Qo
C.)
"S;
tThese symbols are in accordance with ANSIIIEEE Std, 91-1984 and IEC Publication 617-12,
Pin numbers shown are for OW, J, and N packages.
Q)
C
FUNCTION TABLE
..J
SRCK
SRMOOE
-G
-
;::
CD
III
RIS SRCLR
SERIAL
PARALLEL
PARALLEL
...
INPUTS
INPUTS
OUTPUTS
N
tt-
CD
III
S1
SO
:-'
:-'
SL
SR
A
B
C
0
QA
QB
Dc
QO
L
L
L
X
X
X
1
X
X
X
X
X
X
L
L
L
L
I*l
L
L
H
X
X
L
L
X
X
X
X
X
X
QAO
QBO
QCO
QDO
(*1
QAO
H
QBO
QCO
QDO
H
QAn
QBn
QCn
QCn
QCn
H
QCn
L
QBn
H
L
L
H
L
L
X
X
X
X
X
X
X
X
L
L
H
L
H
1
1
X
H
X
X
X
X
L
L
H
L
H
1
1
X
L
X
X
X
X
L
QAn
QBn
L
L
H
H
L
1
t
H
X
X
X
X
X
QBn
QCn
QDn
L
L
H
H
L
t
1
L
X
X
X
X-
X
QCn
b
QDn
c
d
CASC*
QBn
L
L
H
H
H
1
1
X
X
a
b
c
d
QBn
a
H
X
X
L
H
1
1
X
X
)(
X
X
X
Z
Z
Z
Z
QCn
1-1
X
X
H
L
1
t
X
X
X
X
X
X
Z
Z
Z
Z
QBn
L
H
X
X
X
X
X
X
X
X
X
X
X
Internal register contents
(*1
When the output control G is high, the 3-state outputs are disabled to the high-impedance state; however, sequential operation
of the shift register and the output at CASe are not affected.
H = high level (steady statel
L = low level (steady statel
X
= irrelevant (any input, including transitions)
t
= transition from low to high level
a, b, c, d = the level of steady-state input at A, B. C, or 0, respectively
QAO' 0BO. QCD, QDO = the level of QA. QS. OC. or AD. respectively. before the indicated steady·state input conditions were established
0An. 0Bn. 0Cn = the level of 0A. 0B. or 0C. respectively. before the most-recent transition of the clock
Z = high·impedance state
The cascade output displays the D bit of the shift regist.r in mode 1 (51, SO = L, HI, the A bit in mode 2 (51, SO = HLJ. and is inactive (HI
in modes 0 and 3 (51, SO = LL and HH).
*
TEXAS . . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-1113
SN54LS671, SN54LS672, SN74LS671, SN74LS672
4·811 UNIVERSAL SHIFT REGISTERS/LATCHES WITH 3·STATE OUTPUTS
schematics of inputs and outputs
-o
EQUIVALENT OF A THRU 0,
SER L, AND SER R INPUTS
VCC
EQUIVALENT OF
ALL OTHER
INPUTS
--
OUTPUTS
--_-VCC
13 kll
NOM
VC
C1§
25 kll
NOM
INPUT
TYPICAL OF CASCADE
OUTPUT
TYPICAL OF QA THRU QD
INPUT
__
OUTPUT
11--------------'------------absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage Vee (see Note 1)
...................................................
7V
Input voltage . " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
Off·state output voltage
... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range: SN54LS671, SN54LS672 . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C
SN74LS671, SN74LS672 . . . . . . . . . . . . . . . . . . . . . . . . . . oOe to 70°C
Storage t ..mperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
NOTE 1: Voltage values are with respect to the network ground terminal.
recommended operating conditions
SN54LS'
VCC
Supply voltage
IOH
High-level output current
IOL
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
Cascade out
QA' QB, QC. QD
Low-level output current
SN74LS'
MIN
Cascade out
- 0.4
-0.4
-1
-2.6
4
8
12
24
UNIT
V
mA
mA
tw
QA, QB. QC. QD
Width of SRCK, RCK, or SRCO'i ('LS671 only) input puis.
30
30
ns
tsu
Inactive state setup time
SRCLR before SRCK t ('LS671 only)
SO or SI to SRCK t
SRCLR I ('LS6n only) to SRCK t
30
30
ns
45
45
25
25
A, B, C, 0 to SRCK t
30
30
SRCK t to RCK t
30
30
SER to SRCK t
35
35
tsu
th
TA
2-1114
Setup time
Hold time
Any input from SRCK t
Operating free-air temperature
0
55
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ns
0
125
0
70
ns
·C
SN54LS671, SN54LS672, SN74LS671, SN74LS672
4·81T UNIVERSAL SHIFT REGISTERS/LATCHES WITH 3·STATE OUTPUTS
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
Input clamp voltage
VIK
VOH
High-level output voltage
TEST eONDITIONst
Low-level output voltage
Off-state output current,
high-level voltage applied
Off-state output current,
10ZL
low-level voltage applied
QA-Qo
Vee = MIN,
10H=-1 mA
QA-QO
VIH =2V,
10H =-2.6mA
CASe
VIL=VILmax 10H - -400p.A
II
Vee=MIN,
10L = 24 mA
CASe
VIH = 2 V
10L =4mA
IlL
Low-level input current
lOS
Short-circuit output current §
ICC
Supply current
MIN
TYP*
QA-QO
QA-QO
A,B,e,O
All others
QA-QO
CASe
I All outputs low
I All outputs high
I QA thru QD. at Hi-Z
Vee= MAX,
Vo = 2.7 V,
VIH=2V,
VIL = VIL max
Vee=MAX,
VO=O.4V,
VIH = 2 V,
VIL = VIL max
Vee=MAX,
VI = 7 V
Vee = MAX,
VI = 2.7 V
Vee=MAX,
VI =0.4V
Vee=MAX,
VO=OV
MAX
3.1
2.5
3.2
0.25
0.25
UNIT
V
0.7
0.8
V
-1.5
-1.5
V
2.4
3.1
2.7
3.2
0.4
0.4
10L =8mA
input voltage
High-level input current
2.4
IOL-12mA
QA-QO
Input current at maximum
IIH
SN74LS'
MAX
2
Vee - MIN, 11=-18mA
CAse
10ZH
TYP*
2
QA-QO
VOL
SN54LS'
MIN
V
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
V
20
20
p.A
-20
-20
p.A
0.1
0.1
mA
20
-0.4
20
-0.4
-0.2
-0.2
-30
-130
-30
-130
-20
-100
-20
-100
Vee = MAX,
See Note 2
35
70
35
70
All outputs
See Note 3
30
65
30
65
open
See Note 4
37
70
37
70
p.A
ell
G)
CJ
mA
'$
mA
mA
G)
C
~
lI-
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
'*' All
typical values are at V CC = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time and duration of the short~circult should not exceed one second.
NOTES: 2. leCL is tested after two O-V to 4.5 V to O-V pulses have been applied to SACK and ACK while SO is at 4.5 V and all other inputs
are grounded.
3. ICCH is tested after two 4.5-V to o-v to 4.5-V pulses have been applied to SACK and ACK while all other Inputs are at 4.5 V.
4. ICCZ is tested after two o-v to 4.5-V to O-V pulses have been applied to SACK and ACK while SO and G are at 4.5 V and all
other inputs are grounded.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1115
SN54LS671, SN54LS672, SN74LS671, SN74LS672
4·81T UNIVERSAL SHIFT REGISTERS/LATCHES WITH 3·STATE OUTPUTS
switching characteristics, VCC = 5 V, TA = 25°C, see note 5
FROM
PARAMETER
(INPUT)
tPLH
tpHL
OR RIGHT
t
SRCK
14
45
31
45
25
14
RL = 2 kn.,
25
11
20
12
20
CL=15pF
11
20
12
20
19
30
19
30
25
10
20
16
10
25
10
16
20
10
20
15
25
15
25
17
30
SRCK
t
SR LOAD
SR CLEAR
SRCLR
tpLH
RCK
tpHL
tpLH
tpZL
~
tpHZ
c:r
tpLZ
LATCH
QA-QD
10
20
10
20
15
25
15
25
12
25
13
25
15
25
15
25
17
16
16
19
16
16
25
25
17
16
25
25
25
16
25
30
19
30
25
16
25
25
16
25
3·STATE
G~
ENABLE
Gt
30
CL =45pF
RIS ~
3·STATE
RL-667n.,
DISABLE
CL = 5 pF
UNIT
20
RL = 667 n.,
MUX
tPLH
tpHL
C
t
21
~
RIS t
tpHL
tpZH
~
31
OR RIGHT
I"""
en
MAX
SHIFT LEFT
tpHL
tpHL
<
TYP
MIN
tpLH
tpLH
-f
-f
MAX
tpHL
tpHL
•
TYP
MIN
SR CLEAR
~
SRCLR
'LS672
'LS671
LOAD
SHIFT LEFT
CASCADE
SO,SI
tPHL
tpHL
TEST CONDITIONS
MODE
t
SRCK
tPLH
tpHL
TO
(OUTPUT)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE 5: Load circuits and voltage waveforms are shown in Section 1.
TYPICAL APPLICATION DATA
The 'LS671 or 'LS672 can easily be expanded utilizing the cascade output and the SER Land SER R inputs. A typical
expansion is shown below.
SERIAL OUTPU T
(LEFT SHIFT)
SERIAL RIGHT
INPUT, SER R
-
SR
'LS671
or
'LS672
CASC
SL
-t
SR
'LS671
or
'LS672
CASC
SL
t
SR
'LS671
or
'LS672
CASC
SERIAL OUTPUT
(RIGHT SHIFT)
..r-
SERIAL LEFT
SL - I
NPUT, SER L
FIGURE 1 - 'LS671 , 'LS672 EXPANDED TO 12 BITS, (3 PACKAGES)
Any desired word length may be obtained using the scheme shown. Corresponding control pins of all the packages are
tied in common, i.e., all SO pins are connected together, all.51 pins are connected together, etc.
2-1116
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS673, SN54LS674, SN74LS673, SN74LS674
16·81T SHIFT REGISTERS
02421, MARCH 1985 - REVISED MARCH 1988
SN54LS673 , , , J OR W PACKAGE
SN74LS673 ... OW OR N PACKAGE
'LS673
• 16-Bit Serial-In, Serial-Out Shift
Register with 16-Bit Parallel-Out
Storage Register
(TOPVIEWI
• Performs Serial-to-Parallel Conversion
'LS674
• 16-Bit Parallel-In, Serial-Out
Shift Register
• Performs Parallel-to-Serial Conversion
description
SN64LS673, SN74LS673
The 'LS673 is a 16-bit shift register and a 16-bit storage
register in a single 24-pin package. A three-state
input/output (SER/Q15) port to the shift register allows
serial entry and lor reading of data. The storage register
is connected in a parallel data loop with the shift register
and may be asynchronously cleared by taking the storeclear input low, The storage register may be parallel
loaded with shift-register data to provide shift-register
status via the parallel outputs. The shift register can be
parallel loaded with the storage-register data upon command,
CS
SH CLK
R/W
STRCLR
MODE/STRCLK
SER/Q15
YO
Yl
Y2
Y3
Y4
GND
SN54LS673 . , . FK PACKAGE
(TOPVIEWI
'"
....I
I~a::CIlU
~ICIl
4
3
U
U",
2
5
MODE/STRCLK
6
Y12
7
A high logic level at the chip-level (CS) input disables
both the shift-register clock and the storage register
clock and places SER/Q15 in the high-impedance state.
The store-clear function is not disabled by the chip
select.
Caution must be exercised to prevent false clocking of
either the shift register or the storage register via the
chip-select input. The shift clock should be low during
the low-to-high transition of chip select and the store
clock should be low during the high-to-Iow transition of
chip select.
VCC
Y15
Y14
Y13
Y12
Yll
Yl0
Y9
YB
Y7
Y6
Y5
8
9
Yl
Yl0
Y9
YB
10
11
12 1314 15161718
<') >
Z
t!l
z»>
NC - No internal connection
SN64LS674. SN74LS674
The 'LS674 is a 16-bit parallel-in, serial-out shift
register. A three-state input/output (SER/Q15) port
provides access for entering a serial data or reading the
shift-register word in a recirculating loop.
The device has four basic modes of operation:
1)
2)
3)
4)
Hold (do nothing)
Write (serially via input/output)
Read (serially)
Load (parallel via data inputs)
Low-to-high-Ievel changes at the chip select input
should be made only when the clock input is low to prevent false clocking.
PRODUCTION DATA do.umants.onlain information
currant IS of publication data. Praduets confarm to
specifications par the tarms of raxi. Instrumants
::=:~~i~·i'::I~~ ~!:~::i~n :,~U:::::A::.s not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1117
SN54LS673, SN54LS674. SN74LS673, SN74LS674
16·81T SHIFT REGISTERS
SN54LS674 ••• J OR W PACKAGE
SN74LS674 •.• OW OR N PACKAGE
ITOPVIEWI
SN54LS674 ... FK PACKAGE
ITOPVIEWI
I~
:Sl'" u ~~:!
CS
ClK
VCC
P15
Riw
NC
P14
P13
NC
P13
MODE
SER/015
P12
Pll
MODE
SER/015
P12
Pll
PO
Pl0
NC
NC
Pl
P9
P8
PO
Pl0
Pl
P7
P2
P9
P8
P2
P3
a:uuz>~~
4
P6
P4
GND
3 2
1 28 2726
12 1314 15161718
P5
~it~~:f~n::
(!)
'LS673
FUNCTION TABLE
-f
-f
,...
INPUTS
C
~
R/VV
SH CLK
STRCLR
<
n'
H
X
en
L
L
L
H
X
X
l
X
X
(1)
X
X
L
H
j
X
X
X
L
H
j
L
H
L
L
l
X
(1)
MODEl
Q15
SHIFT
STRCLK
X
X
X
X
Q15
L
Q14n
L
H
H
H
L
STORAGE
SHIFT REGISTER FUNCTIONS
SERI
Z
NO
REGISTER
READ FROM
WRITE INTO
PARALLEL
SERIAL OUTPUT
SERIAL INPUT
LOAD
NO
NO
NO
FUNCTIONS
CLEAR
LOAD
NO
YES
Z
YES
NO
YES
YES
YES
YES
NO
L
NO
YES
YES
YES
H
Y15n
NO
YES
YES
NO
NO
T
Z
NO
NO
NO
YES
NO
NO
NO
NO
NO
H = high level (steady state)
'LS674 FUNCTION TABLE
INPUTS
es
H
R/W MODE
X
X
H
l
H
H
SERf
elK
X
a'.
Q14n
p,.
L
=
low level (steady state I
f = transition from low to high level
J ::: transition from high to low level
OPERATION
X = irrelevant (any input including transitions)
Do nothing
Z '" high impedance, input mode
Shift and write (serialloadl
014n = content of 14th bit of the shift register before
the most recent l transition of the clock.
Q15.= present content of 15th bit of the shift register
Shift and read
Parallel toad
Y 15n '" content of the 15th bit of the storage register
before the most recent ~ transition of the clock.
P15 = level of input P15
2-1118
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
NO
SN54LS673, SN54LS674, SN74LS673, SN74LS674
16-BIT SHIFT REGISTERS
logic symbols t
14)
MOOE/STRClK
R/W
cs
SH ClK
"
'lSS73
'lS674
SRG1S
SRG1S
RS
IS)!
MOOE
G'
2
13)1
11)
12)
R/W
ES
Gl/2 EN5
G
ClK
.
PO
C4/3 ....
r
Pl
P2
7,3,40
10,3,40
11,3,40
P3
50
SO
17)
SZ10
IS)
SZll
19)
110)
(111
113)
114)
115)
11S)
(17)
I1S)
119)
(20)
121)
VO
P4
Vl
PS
V2
PS
V3
P7
V4
P8
VS
P9
VS
Pl0
V7
Pll
VS
P12
V9
P13
Vl0
P14
Vll
P15
l,2M3
(3)
C5
-"'- G2
l..r::.
(5)
(1)
(2)
Gl/2 EN
"G
h
(7)
(S)
G2
C4/3+
3,40
r
3,40
~
3,40
(9)
(10)
(11)
(13)
(14)
(15)
I/)
(lS)
Q)
(17)
-S;
CJ
(lS)
Q)
(19)
C
..J
(20)
lI-
(21)
(22)
(23)
(S)
3,40
I>
V
SER/015
V12
V13
122)
50
25,3,40
I>
SZ25
5V
Z7
~
V14
123)
V15
(S)
SER/015
tThese symbols are in accordance with ANSI/lEEE Std. 91·1984 and lEe Publication 617·12.
Pin numbers shown are for DW. J, N. and W packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1119
SN54LS673, SN54LS674, SN74LS673, SN74LS674
16~BIT SHIFT REGISTERS
.
functional block diagrams '
SN54lS673, SN74lS673
SERI015
(6)
'lS673
16
(7-11,13-23)
00-0151----,7'---+-1...;00-015 YO-Y15
16
SHClK~(2~)------+--r~-i
ClK
16
YO-Y15
ClK
16-81T
STORAGE
......-"'C~lrR'----' REGISTER
•
SN54lS674, SN74lS674
(6)
SER/015
tWhen PE is active. data is synchronously parallel loaded into the shift registers from the 16 P inputs and no shifting takes place.
Pin numbers shown are for OW. J. N, and W packages.
2-1120
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265
SN54LS673, SN54LS674, SN74LS673, SN74LS674
16·81T SHIFT REGISTERS
schematics of inputs and outputs
EQUIVALENT OF SER/Q15
EQUIVALENT OF
OTHER INPUTS
AND PARALLEL INPUTS
TYPICAL OF YO THRU Y15
OUTPUTS ('LS673 ONLY)
SER/015 OUTPUT
------<_-VCC
VCC--......- -
------1'---VCe
VCC---"-20 kn NOM
I NPUT--..,.jiI-6--_
INPUT~~~~-,-
OUTPUT
OUTPUT
SER/Q15: Req = 20 kn NOM
PARALLEL INPUTS:
Req:: 30 kfl NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
Input voltage: SER/Q15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
All others
........................................................
7V
Off-state output voltage
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.5 V
Operating free-air temperature range: SN54LS673, SN54LS674
... . . . . . . . . . . . . . . . . . .. -55°C to 125°C
... . . . . . . . . . . . . . . . . . . . . .. oOe to 70°C
SN74LS673, SN74LS674
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _65°C to 150°C
High-level output current
IOl
Low-_Ievel output current
SN74LS'
MIN
NOM
MAX
MIN
NOM
4.5
5
5.5
4.75
5
SER/Q15
YOthru Y15
SER/Q15
YOthru Y15
0
MAX
5.25
-1
-2.6
-0.4
-0.4
12
24
4
8
20
MHz
Clock frequency
20
20
ns
twiclear)
Width of clear input pulse
20
20
ns
20
20
PO thru P15
20
20
Mode
35
35
RIW.CS
35
35
25
25
0
0
SH ClK j to ModelSTR ClK !
See Note 2
SER/Q15
th
Holdtirne
TA
Operating free-air temperature
PO thru P15
Mode
NOTE 2:
0
rnA
Width of clock input pulse
SER/Q15
20
V
mA
fclock
Setup time
Q)
C
UNIT
twiclock)
tsu
CJ
'S
I-
SN54LS'
Supply voltage
Q)
l-
recommended operating conditions
IOH
I/)
..J
NOTE 1. Voltage values are with respect to network ground terminal.
Vee
•
I 'lS673
I 'lS674
0
0
5.0
5.0
0
- 55
ns
ns
0
125
0
70
°e
This setup time ensures the storage register will see stable data from the shift register.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1121
SN54lS673, SN54lS674, SN74lS673, SN74lS674
16-BITSHIFT REGISTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
V,H
High~level
V,L
Low-level input voltage
V,K
Input clamp voltage
VOH
High-level output voltage
II
-I
-I
10ZL
I,
I'H
Vec- MIN,
,,= -18mA
SER/a15
Vec-MIN,
V,H - 2 V,
2.4
YO thru Y15~
V,L = V, Lmax,
10H =MAX
2.5
Off-state output current.
high-level voltage applied
Off-state output current.
SER/a15
SER/a15
Others
High-level input current
Low-level input current
C
ICC
Supply current
(1)
SER/a15
YO thru Y15~
'LS673
'LS674
TYP~
VO=2.7V
VCC - MAX,
V,H - 2 V,
V,L = V,Lmax,
Vo = 0.4 V
I V,
V
O.S
V
-1.5
-1.5
V
3.2
2.4
3.4
3.1
0.4
0.25
0.4
VCC=MAX,
V, =O.4V
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
40
I'A
-0.4
- 0.4
mA
0.1
0.1
0.1
0.1
40
40
20
20
-0.4
-20
VCC=MAX
V
40
-30
VCC= MAX
V
3.4
2.7
0.25
=5.5V
V, =2.7V
UNIT
0.7
V, = 7 V
Vee = MAX,
MAX
2
V,H = 2 V,
V,L = V,Lmax,
Vce=MAX
Others
MIN
'OL-SmA
SER/a15
low-level voltage applied
Input current at maximum
input voltage
Short-circuit output current§
(I)
IOL=4mA
V,L = V,Lmax
VCC = MAX,·
SER/a15
lOS
(1)
SN74LS'
MAX
10L =24 mA
V,H = 2 V,
IlL
<
10L = 12 mA
VCC= MIN,
Low-level output voltage
r(;'
TYP~
2
YO thru Y15~
10ZH
MIN
input voltage
SER/a15
VOL
SN54LS'
TEST CONDITIONSt
PARAMETER
-0.4
-130
-30
-100
-20
-130
-100
50
SO
52
SO
25
40
25
40
mA
I'A
rnA
rnA
rnA
tFor conditions shown as MIN or MAX use the appropriate value specified under recommended operating conditions.
tAli typical values are at VCC = 5 V, TA = 2SoC.
§ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
~ 'LS673 only.
switching characteristics, Vee = 5 V, TA = 25°e, see note 2
PARAMETER
'LS673
'LS674
FROM
TO
FROM
TO
f max
SH CLK
SER/Q15
CLK
SER/a15
tpHL
STRCLR
YO thru Y15
tPLH
MODEl
tPHL
STRCLK
TEST CONDITIONS
RL = 667 n, CL = 45 pF
RL =2kn,cL = 15pF
YO thru Y15
TYP
20
2S
MAX
40
28
45
30
45
21
33
26
40
tpZH
30
45
tPZL
tpHZ
SHCLK
CS, R/W
CS,R/fiJ
SER/a15
SER/a15
SER/a15
CLK
CS, R/W
CS, R/W
SER/a15
SER/a15
SER/a15
R L = 667 n, CL = 45 pF
RL = 667 n, CL = 45 pF
RL =667 n,cl = 5 pF
tPLZ
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
MHz
25
tPHL
tPLH
2-1122
MIN
30
45
25
40
25
40
ns
ns
ns
ns
SN54LS681, SN74LS681
4-BIT PARALLEL BINARY ACCUMULATORS
02422, JANUARY 1981 - REVISED MARCH 1988
• Full4-Bit Binary Accumulator in a Single 2O-Pin
Package
SN54LS661 ... J OR W PACKAGE
SN74LS681 ... OW OR N PACKAGE
(TOP VIEW)
• Contains Two Synchronous Registers:
Word A
Word B Shiftl Accumulator
elK
RS2
RS1
RSO
Ll/RO
Cn
• 16 Arithmetic Operations Including
B Minus A and A Minus B
• 16 Logic-Mode Operations
3
18
4
17
5
6
16
15
14
13
G
• Expandable to Handle N-Bit Words
with Full Carry Look-Ahead
8
en+~
Vee
RI/LO
ASO
AS1
AS2
M
1/00
1/01
1/02
1/03
P
GND
• Bus Driving I/O Ports
description
SN54LS681 ... FK PACKAGE
These low-power Schottky IC's integrate a high-speed
arithmetic logic unit (AlU) complete with word A and
word B registers on a single chip. The ALU performs 16
arithmetic and 16 logic functions (see Tables 1 and 2).
Full carry look-ahead is provided for fast carry of four-bit
words, The carry input (C n ) and propagate and generate
outputs (P and G) are provided for direct use
with SN54S182/SN74S182 carry look-ahead
generators for optimum performance with longer words.
II
ITOPVIEWI
_
N
~
o
U.-J
en tf.)...J u::::
a:a:u>a:
en
CI)
CJ
'S
CI)
C
..J
The A and B registers are controlled by three inputs
(RSO, RS1, and RS2). These pins define eight distinct
register modes (see Table 3), The A register is a simple
storage register while the B register is a combination
storagelshiftlaccumulator register. The contents of the
A and B registers provide the A and B words for the
AlU.
lI-
9 10111213
Ie.. 0
M
C'\I_
zOOO
C,!):::::::::::::::
Four 1/0 ports (1/00 thru 1/03) are provided for parallel loading of word A andlor word B into their respective registers.
These same ports also serve as bus driving outputs for the ALU/accumulator results (Fj). Two additional 110 ports (RI/LO and
Ll/RO) are provided to allow expansion of the accumulator for words greater than four bits in length.
The A or B register can be parallel loaded from the four 1/0 ports. The B register can also be parallel loaded from the AlU as
an accumulator register and in addition, the B register can be serially loaded from either the RI/lO or the Ll/RO ports.
The SN54lS681 is characterized for operation over the full military temperature range from -55°C to 125°C. The
SN74lS681 is characterized for operation from O°C to 70°C.
PRODUCTION DATA documonts contain information
currant as af publication datI. Products canfarm to
specifications par the tarms of TexIs Instruments
:'~::~~i~.tnr:I~'i ~:\::i:; :1~u::::9t:~~. not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1123
SN54LS681, SN74LS681
4·BIT PARALLEL BINARY ACCUMULATORS
functional block diagram (positive logic)
CLOCK
(8)
(1)
...
~
1/00
c'f<
A3
A2
•
(5)
.
~
,
LI/RO
83
B2
CVK
l-
r- f--.
~
i
REGISTER
CONTROL
~~
(2)
Fl
FO Cn +4
Al
AD
f--.
QBl
aBO
RI/LO
I
I
F2
pJ!L
II l'
(3)
3-STATE
CONTROL
81
BO
M
i
Cn
I
1(4)
RS2 RSI
oJ!!!..-
B3
rr- ~ B2
QB3
QB2
BO
(19)
~
~
A3 F3
A2
ARITHMETIC
LOGIC UNIT
(ALU)
BSHIFT
REGISTER
~ Bl
RI/LO
0A3 r-QA2 r-QAl f-QAO f--
A
REGISTER
Al
AD
LI/RO
I
I
(11)
I/O 3
(12)
I/O 2
(13)
I/O 1
(14)
RSO
(16) (17) (18) (15) (6)
AS2 ASI ASO MODE Cn
schematics of inputs and outputs
EQUIVALENT OF CLOCK INPUT
VCC------~~~---
INPUT~--t--I
EQUIVALENT OF
OTHER INPUTS
TYPICAL OF LI/RO
AND RI/LO OUTPUTS
TYPICAL OF I/O
AND ALL OTHER OUTPUTS
----t--VCC
VCC--_-----
INPUT_":i
u~"'-I---'--'--"""-"'-OUTPUT
OUTPUT
--'--H
Il
Cn: R eq "2.5 kn NOM
2-1124
I/O, L1/RO: R eq "10 kn NOM
I/O:
All Others: R eq "18 kn NOM
All Others:
. TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • OAllAS~ TEXAS 75265
R eq " 100
Req" 120
n
n
NOM
NOM
SN54LS681, SNl4lS681
4·BIT PARALLEL BINARY ACCUMULATORS
FUNCTION TABLES
TABLE t - ARITHMETIC FUNCTIONS
TABLE 2 - LOGIC FUNCTIONS
Mode Control (M! = Low
Mode Control (M!
ACTIVE-HIGH OATA
ALU
SELECTION
Cn = L
Cn=H
(with carry!
AS2 ASt ASO
ALU
SELECTION
(no carry!
=L
= B MINUS A
=H
~
High
ACTIVE-HIGH DATA
ASt
L
L
L
L
L
H
L
H
L
= H, F 1 = F2 = F3 = L
= Aj G:> Bj PLUS 1
Fj = Aj (j) Bj PLUS 1
H
Fj = L
ASO
L
L
L
Fj
L
L
H
F
L
H
L
F=AMINUSB
L
H
H
F = A PLUS B PLUS t F = A PLUS B
L
H
H
L
L
F = B PLUS 1
Fj = Bj
H
L
L
H
L
H
F
=ii PLUS 1
Fj = iij
H
L
H
H
H
L
F = A PLUS 1
Fj=Aj
H
H
L
= AjBj PLUS 1
= Aj + Bj PLUS 1
Fj = AjBj PLUS 1
H
H
H
F = A PLUS 1
Fj=Aj
H
H
H
Fj = Aj
Fj
F = B MINUS A MINUS 1
F
=A
MINUS B MINUS 1
TABLE 3
-
Cn = L
(no carrv!
Cn=H
(with carry!
AS2
=L
FO
Fj
Fj
Fj = Aj
G:>
Bj
=Aj (j)
Fj =H
Bj
Fj
Fj
Fj = AjBj
Fj
Fj
Fj
+ Bj PLUS 1
=Aj + Bj
=AjBj
Fj = Aj
+ Bj
•
REGISTER FUNCTIONS
INTERNAL OUTPUTS AFTER L TO H CLOCK TRANSITION
REGISTER
A REGISTER
B SHIFT REGISTER
ALU
DATA INPUTS
SELECTION
RS2 RS' RBO LIIRO 1/03 1/02 I/O • 1/00 RI/LO 0A3 QA2 QA. OAO LI/RO OB3 OB2 OBI OBO RI/LO F3 F2 F.
F3 n
FOn
Z
F3 F2 F.
Z
F3
F2
FI
FO
Z
Z
L
L
L
CA30 CA20 CA.O CAIlo
F2n
F' n
Z
Z Z
Z
H
Z
bl
Z
Z
b3
b2
bO
L
L
03
02
bO
CA30 CA20 CA' 0 QAOo
INPUTS BEFORE L TO H CLOCK TRANSITION
FUNCTION
ACCUM
LCAOB
O.
FO
FO
Z
LEFT
L
H
L
II
F3
F2
FI
FO
CBO
CA30 CA20 CA I 0 CAIlo
H
H
L
H
H
II
F3
F2
FI
FO
CSO
CA30 OA20 CA 10 OAIlo
H
QB3n
H
L
L
OS3
F3
F2
FI
FO
,;
OA3a OA20 QA 10 QAOO QB2n
H
L
H
OS2
F3
F2
F.
FO
,;
OA30 OA20 OAIO CAIlo
HOLD
H
H
L
a3
2
Z
OA3a OA2a QA·O CAIlo
H
.,
FO
H
F2
.2
FI
H
Z
Z
F3
LOAD A
SHIFT
OB3 n QS2 n 081" OS1"
F3
F2
F.
FO
QB2n OSl" 081n
F3
F2
FI
FO
LOGICAL
LEFT
SHIFT
H
ARITH
RIGHT
SHIFT
OS2" QSt" Q80n
,I
,I
F3
'2
••
FO
QS1" Q83 n OS1" aBOn
,;
,I
F3
'2
FI
FO
Z
F30 F20 F·O FOO
LOGICAL
RIGHT
SHIFT
ARITH
.0
.3
.2
.,
.0
Z
Z
OS30 OB20 CB.O CBIlo
OS3n OS2n CB'n oSOn
Z
z
z
z
z
H = high level (steady state)
L = low level (steady state)
Z = high impedance (output off)
aO ..• 83, bO ••. b3 = the level of steady - state condition at I/O a thru I/O 3, respectively and intended as A or B input data
FO .•• F3 :;internal ALU results
QAOO .•• 0800' FOa'" F3 0 = the lavel of QAO thru OS3 and FO thru F3, respectively, bafore tha indicated steady-stete input conditions were
established
OAO n... aS3 n = the level of OAO thru QS3 before the most recent t transition of the clock
r"i, Ii "" the level of steady-state conditions at RI/LO or L.I/AO, respectively
TEXAS . . ,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 15265
2-1125
SN54LS681, SN74LS681
4·BIT PARALLEL BINARY ACCUMULATORS
logic symbol t
ASO
(18)
(17)
ASl
(16)
AS2
(15)
M
(6)
Cn
RSO
}~[ALU[
(0 ... 7)CP
yr
(0 ... 7) CG
13
(0 ... 7)CO
Cn+4
CI [1)
RSl
O}EN
RS2
ClK
2
~27
C28
22+/24+[abed,logieal)
•
23+/25+[abe.arithmetie)
AlU
REG4
30,27,280
~
~
P[1)
P[2)
31,27,280
32,27,280
r-
P[4)
P[8)
33,27,280
C
(1)
(19)
<
c:;'
(1)
RI/LO
SRG4
(24/25)280
la)
0[1)
31(20/21 )280
[b)
0[2)
32(20/21 )280
23,280
[e)
0[4)
'\722/23
30(20/21 )280
C/)
LI/RO
[>
1/00
1/01
1/02
1/03
'\725
'\724
22,280
[d)
0[8)
33(20/21 )280
tThis symbol is in accordance with ANSI/IEEE Std. 91·1984 and lEe Publication 617·12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
Operating free-air temperature range: SN54LS681
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. _55°C to 125°C
SN74LS681
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. oOe to 70°C
Storage temperature range ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. _65°C to 150°C
NOTE 1: Voltage values are with respect to the network ground terminal.
2-1126
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS681, SN74LS681
4-BIT PARALLEL BINARY ACCUMULATORS
recommended operating conditions
SN54LS681
Supply voltage, V CC
MAX
MIN
NOM
MAX
4,5
5
5.5
4.75
5
5.25
V
P, G, Cn+4
-1
- 0.4
-2.6
mA
- 0.4
mA
12
24
8
I/O
Low-level output current, IOL
Cn+4, LI/RO, RI/LO
4
P
8
8
G
16
16
Clock frequency, fclock
20
0
Width of clock pulse, tw(clock)
Setup time, tsu
I
0
25
25
RSO·RS2 to CLK!
35
30
Oata I/O to CLK!
25
25
0
Hold time, th
Operating free-air temperature. T A
UNIT
NOM
LI/RO, I/O, RI/LO
High-level output current, IOH
SN74LS681
MIN
20
125
MHz
ns
ns
ns
0
-55
mA
0
70
·C
electncal characterIStiCS over recommended operating free-air temperature range (unless otherWise noted)
PARAMETER
VIH
VIK
VOH
VCC-MIN,II- 18mA
High·level
All I/O
VCC-MIN, VIW2 V,
output voltage
P,
output voltage
G, Cn+4
II
IIH
2.4
3.1
2.4
3.2
2.5
3.4
2.7
3.4
0.25
IOL=12 mA
VCC=MAX, VIH=2 V,
10L 4mA
VIL=VIL max
IOL-8mA
0.25
0.4
0.4
0.35
0.5
0.5
0.5
VCC=MAX, VIW2 V,
I/O, LI/RO
VCC=MAX, VIW2 V,
VO=O.4 V
High-level
Cn
All I/O
VIL=VILmax,
40
VO=2.7 V
RI/LO
All others
Supply current
0.25
0.35
VIL =VIL max,
I VI-5.5 V
VCC=MAX
VI=7 V
VCC=MAX, VI=2.7 V
All others
I/O, LI/RO
CLK
VCC=MAX, VI=O.4 V
All others
ICC
0.5
0.5
input voltage
output current§
0.4
0.35
0.35
All I/O
Short-circuit
0.25
IOL-16mA
Cn
lOS
0.4
G
Cn
input current
-1.5
0.35
Input current
Low-level
IlL
-1.5
0.5
at maximim
input current
0.8
0.35
current, low-level
voltage applied
0.7
IOL-8mA
current, high-level I/O, LI/RO, RI/LO
Off-state output
0.7
IOL-24 mA
I/O
LI/RO, RI/LO,
VCC=MAX
P, G, Cn+4
VCC=MAX, RSO at 4.5 V,
All other I/O at 0 V
40
-0.8
-0.8
-0.4
- 0.4
0.1
0.1
0.5
0.5
0.1
0.1
100
100
40
40
20
20
-4
-4
-0.8
-0.8
-0.2
-0.2
-0.4
-0.4
-30
-130 -30
-130
-20
-100 -20
-100
ioo
150
UNIT
V
0.7
P
voltage applied
10ZL
VIL-VIL max,
10WMAX
LI/RO, RI/LO, Cn+4
Off-state output
10ZH
2
I Cn
I
input voltage
All others
I nput clamp voltage
Low-level
SN74LS681
2
I/O
VOL
SN54LS681
MIN TYP* MAX MIN TYP* MAX
High-level input voltage
Low-level
VIL
TEST CONDITIONSt
100
150
II
V
U)
Q)
V
-S;
V
C
CJ
Q)
...I
V
tt-
I'A
mA
mA
I'A
mA
mA
mA
..
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operations .
fAil typical values are at VCC := S V, T A = 2SoC.
§Not more than one output should be shorted at a time, and duration of the short.cir~uit should not exceed one second.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1127
SI54LSB81, SN74LSBlt1
4-BIT PARALLEL BINARY ACCUMULATORS
switching characteristics. Vee - 5 V. TA - 25°e. see note 2
PARAMETER
FROM
(INPUT)
tPLH
tpHL
TEST CONOITIONS
p
tPLH
G
tPHL
tPLH
tpHL
TO
(OUTPUT)
RL s667 n.
CL =45pF
I/O
CLOCKt
tPLH
tpHL
Cn+4
tPLH
tpHL
LliRO
tPLH
tpHL
RL = 2 kn.
CL = 15 pF
RI/LO
TVP
MAX
25
40
30
45
26
40
27
40
27
29
40
40
36
55
34
50
25
40
23
35
19
30
17
30
30
45
tPHL
30
45
tPLH
tpHL
27
35
28
31
45
29
39
55
34
50
9
25
tPLH
p
G
RL = 667 n,
I/O
tPLH
Cn+4
tPHL
tPLH
tpHL
RL = 2 kn,
CL = 15 pF
p
tpHL
tpLH
CL = 45 pF
ASD-AS2
tPLH
tpHL
RL = 667 n,
Cn
CL
= 45 pF
I/O
35
45
9
20
17
35
13
20
20
30
16
25
40
tPLH
tpHL
Cn+4
tPLH
P
28
29
40
G
21
30
23
30
45
tPHL
tPLH
tPHL
tPLH
tpHL
RL = 2 kn,
RL = 667 n,
30
Cn+4
RL = 2 kn,
I/O
RL = 667 n
tpZH
tPHZ
CL = 5 pF
tPLZ
tpZH
CL = 15 pF
RS1-RS2
LI/RO
RL=2kn
CL = 5 pF
tPLZ
tPZH
tpZL
tPHZ
tpLZ
CL = 15 pF
CL = 45 pF
tpZL
tPHZ
CL=45pF
I/O
tpHL
tpZL
CL=15pF
MODE
tPLH
CL= 15pF
RI/LO
RL=2kn
CL = 5 pF
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2-1128
MIN
TEXAS . "
INSTRUMENTS
POST OFFiCe BOX 665012 • DALLAS, TeXAS 75265
28
40
40
60
37
50
26
45
28
45
35
65
39
65
40
25
22
21
40
40
34
60
22
40
24
40
11
30
16
40
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SN54LS68~ SN54LS68~
SN54LS687, SN54LS68~
SN74LS682, SN74LS684 THRU SN74LS688
8·BIT MAGNITUDE/IDENTITY COMPARATORS
SN54LS68t
02617, JANUARY 1981-REVISED MARCH 1988
•
Compares Two·8-Bit Words
•
Choice of Totem-Pole or Open-Collector
Outputs
•
Hysteresis at P and Q Inputs
SN54LS682. SN54LS684. SN54LS685 , , . J PACKAGE
SN74LS682. SN74LS684. SN74LS685 , , , OW OR N PACKAGE
(TOP VIEW)
~
p>o
PO
P~o
07
P7
Q()
•
'LS682 has 20-kO Pullup Resistors on the Q
Inputs
•
SN74LS686 and 'LS687 , , . JT and NT
24-Pin, 300-Mil Packages
PI
Q6
P6
TYPE
P-O p>o
OUTPUT
ENABLE
OUTPUT
Q5
20·kO
P3
P5
03
Q4
GNO
P4
CONFIGURATION PULLUP
'LS682
yes
yes
no
totem-pole
yes
'LS684
yes
yes
no
no
'LS685
yes
yes
no
totem-pole
open-collector
SN74LS686
yes
yes
yes
yes
yes
yes
'LS688
yes
no
yes
totem-pole
open-collector
totem-pole
no
'LS687
SN54LS682. SN54LS684. SN54LS685 , .. FK PACKAGE
(TOP VIEW)
no
0
no
3
Pl
2
1 20 19
4
SN54LS687 , • , JT PACKAGE
SN74LS686, SN74LS687 , , . OW OR·NT PACKAGE
Q1
(TOP VIEW)
Q2
7
P3
8
p>o
131
PO
II
UIO
1
8~~j'l
no
18
17
P2
16
15
14
Vee
132
05
9 1011 1213
p~o
Q()
07
P7
Ne
PI
01
Ne
SN54LS688 , . , J PACKAGE
SN74LS688 , , , OW OR N PACKAGE
Q6
P6
(TOP VIEW)
Q5
P3
P5
03
Q4
GNO
P4
13
PO
SN54LS687 , , , FK PACKAGE
Vee
p=o
07
P7
PI
01
Q6
Q2
Q5
P3
P5
P6
(TOP VIEW)
Q4
GNO
4
Q()
PI
Q1
Ne
NC
P2
10
Q2
11
3 '2
P4
1 28 27 26
25
24
23
22
07
P7
NC
Ne
21
Q6
20
19
P6
05
SN54LS688 , .. FK PACKAGE
(TOP VIEW)
UIO
8~1",j'l
12131415161718
3 2
PI
Q1
P2
Q2
NC - No internal connection
1 20 19
~.
~,
17
07
P7
6
16
Q6
"
I.
Q5
18
P3
P6
9 1011 12 13
PRODUCTION DATA documenls contain informalion
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
:'~~~:~~i~at::1~1i ~~:1~:i:; :1~O::~:~:t::S~S not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX f?55012 • DALLAS, TEXAS 75265
2-1129
SN54LS682, SN54LS684, SN54LS685, SN54LS687, SN54LS688
SN74LS682, SN74LS684 THRUSN74LS688
8;81T MAGNITUDE/IDENTITY· COMPARATORS
FUNCTION TABLE
description
•
""'"
C
P,Q
p=o
~,lrf
~
L
'LS688 have totem-pole outputs, while the 'LS685 and
'LS687 have open-collector outputs. The 'LS682 features
P>Q
pQ
X
PI
P2
CD
P3
CD
P5
C:;"
P4
P6
P7
00
01
02
03
04
05
06
07
(4)
(6)
18)
111)
113)
115)
117)
13)
15)
171
19)
112)
1141
116)
118)
X
L
H
L
H
L
H
H
H
X
X
H
H
X
H
H
H
H
H
H
H
'LS686
il}
COMP
(2)
PO
J
l
(4)
PI
(6)
P2
(8)
P3
(11)
P4
62
PO
PI
P2
P3
P4
117)
P7
00
01
02
03
04
05
06
07
il7
P5
13)
P6
15)
l
171
19)
112)
114)
116)
118)
P7
p;Q
00
Q1
02
03
04
IT7
05
06
07
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and )EG Publication 617-12.
Pin numbers shown are for OW, J, JT, N, and NT packages.
2-1130
,
t>
61
115)
P6
P>"Q
COMP
t>
113)
P5
P=O
il7
J»1I
'lS685
t>
(2)
p;;(l
NOTES: 1. The last three lines of the function table applies only
to the devices having enable inputs, i.e., 'LS686
thru 'LS688.
2. The P < 0 function can be generated by applying
the P = Q and P> Q outputs to a 2-input NAND
gate .
3. For 'LS686 and 'LS687, (31 enables P = Q and (32
enables P> Q.
COMP
<
(I)
DATA
'lS6B2, 'lS6B4
PO
ENABLES
two eight-bit binary or BCD words. All types provide
P = 0 outputs and all except 'LS688 provide'
P > 0 outputs as well. The 'LS682, 'LS684, 'LS686, and
logic symbols t
""'"
r-
OUTPUTS
INPUTS
These magnitude comparators perform comparisons of
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
(3)
15)
(8)
110)
113)
il}
115)
(17)
120)
lP=O
P=O
2P>Q
P>O
ill
14)
16)
19)
111)
114)
116)
118)
1211
l
ill
SN54LS682. SN54LS68' SN54LS68i SN54LS687. SN54LS68L
SN74LS682. SN74LS684 THRU SN74LS688
8·BIT MAGNITUDE/IDENTITY COMPARATORS
logic symbols t (continued)
'LS687
Gl
G2
PO
Pl
P2
P3
P4
P5
P6
P7
00
OJ
Gill
Gl
COMP
[>
PO 121
131
151
181
1101
1131
O}
Pl 141
P2 161
P3 181
P4 1111
P5 1131
1151
1171
1201
P6 1151
P7 1171
117
00 131
141
161
191
02
1111
03
1141
04
1161
05
1181
06
1211
Q1
'LS688
COMP
[>
01
02
03
04
151
171
(91
1121
as 1141
1161
06
1181
07
l
l
[J7
lP-=Q
1191
p·o
"}
&I
[J7
[J7
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for OW. J, JT, N, and NT packages.
schematics of inputs and outputs
EQUIVALENT OF EACH Q INPUT
OF 'LS682 ONLY
VCC
INPUT
EQUIVALENT OF ALL
OTHER INPUTS
VCC
----+-
TYPICAL OF OUTPUTS OF
TYPICAL OF OUTPUTS OF
'LS682, 'LS684, 'LS686, 'LS688
'LS685, 'LS687
--_-Vce
INPUT
.......L..A.-OUTPUT
TEXAS ."
INSfRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 15265
2·1131
SN54LS682, SN54LS684, SN54LS685
SN74LS682, SN74LS684, SN74LS685
8·BIT MAGNITUDE/IDENTITY COMPARATORS
'LS682, 'LS684, 'LS685 logic diagram (positive logic)
Pin numbers shown are for OW, J, and N packages,
2-1132
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS687
SN74LS686, SN74LS687
8·BIT MAGNITUDE/lDENTlTY COMPARATORS
'LS686, 'LS687 logic diagram (positive logic)
(22) P=Q
-
}--
}-
~====g§",p}--
Pin numbers shown are for OW, JT, and NT packages.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1133
SN54LS682, SN54LS684, SN54LS685, SN54LS687, SN54LS688
SN74LS682, SN74LS684 THRU SN74LS688
8·BIT IDENTITY COMPARATORS
'LS688 logic diagram (positive logic)
P7
07
P6
06
P5
Q5
P4
Q4
(19)
p=o
P3
03
P2
~
~
r-
Q2
C
P1
<
01
CD
PO
CD
C:)"
(/)
QO
Pin numbers shown are for OW, J, and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: Q inputs of 'LS682 ........................................... " 5.5 V
All other inputs ................................................. 7 V
Off-state output voltage: 'LS685, 'LS687 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Operating free-air temperature range:
SN54LS682, SN54LS684, SN54LS685, SN54LS687, SN54LS688 ........ -55°C to 125°C
SN74LS682, SN74LS684 thru SN74LS688 ............................. ooe to 70°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminal .
2-1134
." TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS682, SN54LS684, SN54LS688
SN74LS682, SN74LS684, SN74LS686, SN74LS688
8-BIT MAGNITUDE/IDENTITY COMPARATORS WITH TOTEM-POLE OUTPUTS
recommended operating conditions
MIN
4.5
Supply voltage, Vee
High·level output current, IOH
Low·level output current, IOL
SN54LS'
NOM MAX
5
5.5
-400
12
-55
Operating free-air temperature, T A
125
SN74LS'
MIN NOM MAX
4.85
5 5.25
-400
24
70
0
UNIT
V
p.A
mA
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONSt
High-level input voltage
VIH
Low-level input voltage
VIL
VT + - VT _ Hysteresis
P or
inputs
Input clamp voltage
VIK
I
VOH
VOL
Q
High-level output voltage
Low-level output voltage
IQ
II
IIH
IlL
IOS§
2
11= --18 mA
VIH = 2 V,
IOH = -400 ~A
Vee = MIN,
VIL = VILmax,
Vee - MIN,
IIOL = 12 mA
VIH = 2 V,
VIL = VILmax IIOL = 24 mA
High-level input current
Vee - MAX,
VI = 2.7 V
Vee = MAX,
VI = 0.4 V
input current IAII other inputs
Short-circuit output current
Vee = MAX,
Supply current
'LS6B4
'LS686
Vee = MAX,
0.4
-1.5
2.5
0.4
UNIT
V
V
•
V
-1.5
2.7
0.25
V
V
0.25
0.4
0.35
0.5
en
V
II)
CJ
0.1
0.1
mA
20
-0.4
-0.2
20
-0.4
~A
Vo = 0
-20
See Note 1
'LS688
-100
-0.2
-20
-100
42
70
42
70
40
44
40
65
75
40
44
40
65
75
65
'>
II)
C
....
VI = 7 V
'LS682
lee
0.8
0.4
Vee = MIN
Vee = MIN,
VI = 5.5 V
IQ inputs, 'LS6B2
SN74LS'
MIN TYP; MAX
2
0.7
Input current
inputs, 'LS682 Vee = MAX,
at maximum
Vee = MAX,
input voltage I All other inputs
Low-level
SN54LS'
MIN TYP; MAX
mA
lI-
mA
mA
65
t For
conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.
~AlltypicalvaluesareatVee = 5V,TA = 25°e.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 1: lee is measured with any G inputs grounded, all other inputs at 4.5 V, and all outputs open.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1135
SN54LS682, SN54LS684, SN54LS688
SN74LS682, SN74LS684, SN74LS686, SN74LS688
8·BIT MAGNITUOE/lOENTlTY COMPARATORS WITH TOTEM·POLE OUTPUTS
switching characteristics.
PARAMETERt
tPLH
tpHL
tpLH
tpHL
tpLH
FROM
TO
TEST
(lNPUTSI
(OUTPUTI
CONDITIONS
P
p;;(i
Q
P=Q
~,~1
tpHL
tpLH
tpHL
tpLH
tpHL
tPLH
tpl-Il
vee" 5 V. TA
P=Q
P>Q
RL = 667 II,
CL = 45 pF,
inputs low,
See Note 2
Q
P>Q
~2
P>Q
25°e
'LS682
All other
P
..
'LS684
'LS686
'LS688
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
13
25
15
25
13
25
12
18
15
25
17
25
20
30
17
23
14
25
16
25
13
25
12
18
15
25
15
25
21
30
17
23
11
20
12
18
19
30
13
20
20
30
22
30
19
30
15
30
17
30
15
30
21
30
24
30
18
30
19
30
20
30
19
30
21
30
25
16
ttPLH " propagation delay time, low-to-high-Ievel outputs; tPHL " propagation delay time, high-to-Iow-Ievel output.
NOTE 2: load circuits and voltage waveforms are shown in Section 1.
-t
-t
rC
CD
::.
C')
CD
(I)
2-1136
.
TEXAS-If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
UNIT
ns
ns
ns
ns
ns
ns
SN54LS685, SN54LS687
SN74LS685, SN74LS687, SN74LS688
8-BIT MAGNITUDE/IDENTITY COMPARATORS WITH TOTEM-POLE OUTPUTS
recommended operating conditions
SN64LS'
MIN
4.5
Supply voltage. Vee
High·level output current. VOH
Low-level output current. IOL
NOM
5
-55
Operating free-air temperature. TA
MAX
5.5
SN74LS'
MIN NOM MAX
4.85
5 5.25
5.5
12
5.5
24
125
0
70
UNIT
V
V
mA
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
High-level input voltage
V,H
Low-level input voltage
V,L
P or Q inputs
VT+ - VT _ Hysteresis
Input clamp voltage
V,K
I
IOH
VOL
High-level output voltage
Low-level output voltage
High-level input current
',L
Low·level input current
lee
current
I'LS685
I'LS887
MIN
TYP
SN74LS'
MAX
2
MIN
TYP
Vee
= MIN
Vee - MIN.
Vee = MIN,
= MAX.
= MAX.
= MAX.
V, - 7 V
Vee
Vee
Vee
= MAX.
See Note 1
V,
V,
= 2.7
= 0.4
0.25
V
V
V
-1.5
-1.5
V
250
100
0.4
0.4
0.25
0.35
V
V
40
44
UNIT
0.8
0.4
" - -18 mA
V,H = 2 V,
V,L = V,Lmax. VOH = 5.5 V
Vee - MIN, I'OL = 12 mA
V,H = 2 V.
V,L = V,Lmax I'OL = 24 mA
MAX
2
0.7
Vee
""H
Supply
SN54LS'
TEST CONDITIONSt
~A
en
CI)
'S:
(,)
0.5
0.1
0.1
mA
20
-0.2
20
-0.2
~A
65
75
40
44
85
75
Ell
V
0.4
mA
mA
CI)
C
...I
1=
tFor conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.
tAli typical values are at Vee = 5 V. TA = 25·e.
NOTE 1: lee is measure with any G inputs grounded. all other inputs at 4.5 V, and all outputs open.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALl.AS. TeXAS 75265
2-1137
SN54LS685, SN54LS687
SN74LS685, SN74LS687
8·BIT MAGNITUDE/IDENTITY COMPARATORS WITH OPEN·COLLECTOR OUTPUTS
switching characteristics.
PARAMETER
tpLH
tpHL
tpLH
tPLH
tpHL
tpLH
tpHL
tPLH
tPHL
=
TO
(INPUT)
(OUTPUT)
P
p=o
Q
tpHL
tPHL
tpLH
Vee
FROM
5
V.
TA = 25°C
TEST CONDITIONS
P=Q
RL = 667
G, G1
'LS685
MIN
P=Q
n,
P>Q
inputs low,
See Note 2
Q
G2
MAX
TYP
MAX
30
19
45
24
35
35
20
30
24
45
24
35
23
35
20
30
21
18
35
30
CL = 45 pF,
All other
P
'LS687
TYP
l'>Q
MIN
32
45
24
35
16
35
16
30
30
45
24
35
20
35
16
30
24
15
35
30
J5>Q
ttPLH = propagation delay time, low-to-high-Ievel outputs; tPHL = propagation delay time, high-to-Iow-Ievel output.
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2-1138
TEXAS .".
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
ns
ns
ns
ns
ns
ns
SN54LS690. SN54LS691. SN54LS693. SN74LS690. SN74LS691. SN74LS693
SYNCHRONOUS COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3-STATE OUTPUTS
02423. JANUARY 1981-REVISED MARCH 1988
•
4-Bit Counters/Registers
•
Multiplexed Outputs for Counter or Latched
Data
•
3-State Outputs Drive Bus Lines Directly
•
'LS690 ... Decade Counter, Direct Clear
'LS691 ... Binary Counter, Direct Clear
'LS693 ... Binary Counter, Synchronous
Clear
SN54LS690, SN54LS691, SN54LS693 ... J PACKAGE
SN74LS690. SN74LS691, SN74LS693 ... OW OR N PACKAGE
(TOPVIEWI
CCLR
CCK
VCC
RCO
OA
OB
B
C
D
Oc
aD
ENT
description
LOAD
These low-power Schottky LSI devices incorporate
synchronous counters, four-bit D-type registers, and
quadruple two-line to one-line multiplexers with threestate outputs in a single 20-pin package. The counters
can be programmed from the data' inputs and have enable
P inputs and enable T inputs and a ripple-carry output for
easy expansion. The register/counter select input,
selects the counter when low or the register when high
for the three-state outputs, OA, 0B, OC, and aD. These
outputs are rated at 12 and 24 milliamperes (54LS/74LS)
for good bus-driving performance.
Ric,
G
RCK
GND
RIC
SN54LS690, SN54LS691, SN54LS693 ... FK PACKAGE
(TOP VIEWI
~15
U
U uo
uu
a:
3
•
II)
Go)
2 t
U
'S;
Individual clock and clear inputs are provided for both the
counter and the register. Both clock inputs are positiveedge triggered: The clear line is active low and is
asynchronous on the 'LS690 and 'LS691, synchronous
on the 'LS693. Loading of the counter is accomplished
when LOAD is taken low and a positive-transition occurs
on the counter clock CCK.
Go)
C
....I
l-
I-
9 to 11 t2 t3
~ CIUIC!lIC
~~~
Expansion is easily accomplished by connecting RCO of
the first stage to ENT of the second state, etc. All ENP
inputs can be tied common and used as master enable
or disable control.
...~
schematics of inputs and outputs
EQUIVALENT OF
A, B, C, 0 INPUTS
EQUIVALENT OF
ALL OTHER INPUTS
TYPICAL OF
ALL Q OUTPUTS
RCOOUTPUT
---------1~--Vee
Vee
Vee
20 kSl NOM
INPUT
INPUT
'"
w
OUTPUT
~~
,
PRODUCTION DATA .....m••II_.io iofD'III1iOO
cu....t n of pubIIc.tiDn "'11. PrHucta .00""'" to
.p..IIi.lli••• per th. 11.111 ., TOil. 101lrlll.nII
:'==i:;"::~':.'l~ ~::i~~ti:: :Ir:::~~ not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-1139
SN54LS890, SN74LS8.90
SYNCHRONOUS COUNTERS WITH .OUTPUT REGISTERS
AND MULTIPLEXED 3·STATEOUTPUTS
logic diagrams (positive logic)
•
o
2-1140
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN54LS691, SN74LS691
SYNCHRONOUS COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
logic diagrams (positive logic) (continued)
•
II)
Q)
CJ
'SQ)
C
...J
lI-
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-1141
SN54LS693, SN74LS693
SYNCHRONOUS COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED3·STATE OUTPUTS
logic diagrams (positiva logic) (continued)
•
-f
-f
r-
C
CD
<
(;'
CD
en
2-1142
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS69L SN54LS691. SN54LS693. SN74LS69L SN74LS691. SN74LS693
SYNCHRONOUS COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
logic symbols t
'lS690
'lS691
MUX
MUX
3CT=9
22
Z22
1191
1181
B 14
5
C
o 16
117)
[21
1161
[41
115)
[81
RCO
3CT=15
Z22
22
119)
(181
OA
117)
OB
B
Oc
C
[41
00
0
[81
116)
115)
RCO
OA
Os
Oc
00
II
tn
Q)
(,)
'S.
Q)
'lS693
C
...I
lI-
3CT=15
Z22
22
119)
RCO
CCK
OA
A
Os
B
Oc
C
0
6
00
tThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and lEe Publication 617-12,
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1143
SN54LS690, SN54LS69.1, SN54LS693, SN74LS690, SN74LS691, SN74LS693
SYNCHRONOUS COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
absolute
maxlmu~
ratings over operating free·alr temperature range (unless otherwise noted)
Supply voltage, Vee (See Note 1) . . . • . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . • . . . . . .. 7 V
Input voltage. . . . . . . . • ... . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Off-state output voltage ........ '.......... , ' . . . . • . . • . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . • .. 5.5 V
Operating free-air temperature range: SN54LS690, SN54LS691, SN54LS693 ............ -55°C to 125°C
SN74LS690, SN74LS691, SN74LS693 ...•.......•... ooe to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •. - 65°C to 150°C
NOTE 1: Voltage vllues are with respect to network ground tormlnal.
recommended operating conditions
SN64LS'
:1r-
VCC
Supply voltage
VIH
High·level input voliage
VIL
Low-level input voltage
IOH
High.le~el output current
IOL
Low-level output current
fclock
Clock frequency
CD
<
tw
Pu Ise duration
C:;"
I'LSS90, 'LSS91
CD
III
tsu
Sstup time
before CCI( t
L' LS693
I 'LSS90, 'LS691
tsu
Setup time
before RCI( t
I 'LSe90, 'LS691
I
th
TA
MAX
MIN
NOM
MAX
4.5
5
6.5
4.76
6
5.25
V
0.7
0.8
V
a
RCO
a
RCO
CCI(
-1
-2.6
-0.4
- 0.4
mA
mA
12
24
mA
4
8
mA
0
20
MHz
0
20
MHz
0
20
0
20
26
26
RCI( high or low
25
~Iow
20
25
20
CCLRlow
20
20
A thru 0
ENPor ENT
30
30
30
LOAD I
CCLR I
30
40
30
eCLR t inactive
eCI< t (see Note 2)
26
30
30
RCLR t inactive
26
20
26
20
Hold lime
I
Operating free-air temperature
0
-55
V
2
CCI( high or low
RCLR I
'LS693
Any Input from CCI( t or RCI< t
UNIT
NOM
2
RCI(
C
SN74LS'
MIN
ns
30
ns
40
25
n8
n8
0
125
0
70
'c
NOTE 2: This let up time ensures the regllter will lae stabla data from the counter outputs. The clock. mav be tied together In which call tha
ragllt8r stat8 will be one clock pulse behind the counter.
, "1(1-
2-1144
TEXAS 'V
INSTRUMENTS
POST OFFICE BOX 6550"2 • DALl.AS. TEXAS 75265
SN54LS690, SN54LS691, SN54LS693, SN74LS690, SN74LS691, SN74LS693
SYNCHRONOUS COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3·STATE OUTPUTS
electrical characteristics over recommended operating free·air temperature range (unless otherwise noted)
SN54LS'
TEST eONDITloNst
PARAMETER
Vee = MIN, II -
VIK
Any Q
VOH
Any Q
ReO
Any Q
AnyQ
VOL
RCO
IOZL
Any Q
Any Q
Vec = MIN, VIH = 2 V,
VIL = MAX
= MIN, VIH = 2 V,
VIL = MAX
VCC
A thru D
All others
AnyQ
IOS§
ICCH
leCL
IOH=-1 mA
IOH= 2.6mA
2.4
3.1
IOH=-0.4mA
IOL=12mA
2.5
3.2
RCO
MIN
TYP*
1.5
2.4
3.1
2.7
0.4
0.4
0.25
0.4
0.25
0.4
0.35
0.5
IOL - 8 mA
VCC = MAX, VIH = 2 V, VIL = MAX,
VO=2.7V
UNIT
V
V
0.25
IOL=24mA
IOL = 4 mA
MAX
3.2
0.25
0.35-
0.5
V
20
20
-20
-20
I'A
0.1
0.1
mA
20
20
-0.4
I'A
I'A
Vce = MAX, VIH = 2 V, VIL = MAX,
VO=0.4V
VCC = MAX, VI = 2.7 V
IIH
SN74LS'
MAX
-1.5
Vce = MAX, VI = 7 V
II
IlL
TYP*
18mA
RCO
IOZH
MIN
-0.4
Vec = MAX, VI = 0.4 V
-0.2
VCC=MAX,VO=OV
VCC= MAX,
All outputs open
Icez
-30
-130
-30
-0.2
-130
-20
-100
-20
-100
See Note 3
46
65
46
65
See Note 4
48
70
48
70
See Note 5
48
70
48
70
mA
mA
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
; All typical values are at Vee = 5 V, T A "" 25°C.
§ Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second.
NOTES: 3. leCH is measured after two 4.5 V to o-V to 4.5~V pulses have been applied to CCK and RCK while G is grounded and all other inputs are at 4.5 V.
4. 'eeL is measured after two o-V to 4.5-V to o-V pulses have been applied to CCK and RCK while all other inputs are gro4nded.
5. ICCZ Is measured after two O-V to 4.5-V to o-v pulses have been applied to CCK and RCK while G is at 4.5 V and all other Inputs are grounded.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-1145
SN54LS690, SN54[S691,SN54LS693, SN74LS690, SN74LS691, SN74LS693
SYNCHRONOUS' COUNTERS WITH OUTPUT REGISTERS
AN.D MULTIPLEXfD 3"STATE OUTPUTS
switching characteristics, Vee = 5 V, TA = 25°e (see note 6)
PARAMETER
tpLH
tpHL
tPLH
tpHL
tpLH
CCKt
ENT
TO
(OUTPUT)
. RCO
a
tPLH
tpHL
RCKt
a
tPHL
CCLR~
Q
tPHL
tPLH
RCLR~
a
a
tPHL
tpZH
tpZL
tpHZ
·tPLZ
RIC
TEST CONDITIONS
'LS690, 'LS691
G~
a
Gt
Q
MAX
MIN TVP
23
40
23
40
23
13.
40
23
40
20
13
20
13
20
20
12
20
13
12
17
12
17
23
20
16
16
19
19
17
17
25
17
12
17
25
RL = 2 kll, CL = 15pF
RL = 667 11, CL = 45 pF
RL = 66711, CL = 5 pF
NOTE 6: load circuits and voltage waveforms ara shown in Section 1.
c:;.
CD
II)
2-1146
'LS693
MIN TVP
RCO
CCKt
tpHL
:Iri'<
FROM
(INPUT)
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
20
25
MAX
20
20
UNIT
ns
ns
ns
ns
25
40
ns
ns
30
25
25
16
16
25
25
ns
30
19
30
19
30
30
ns
30
17
17
30
30
ns
30
SN54LS690. SN74LS690
SYNCHRONOUS COUNTERS WITH OUTPUT REGISTERS
AND MULTIPLEXED 3-STATE OUTPUTS
typical operating sequences
~
Ifj
Q)
to
5'c"
e
.c
It)
(,,)
'S;
t.)
20:
>..1
Q)
_(I)t.)
u
c
i
M
r;i
w
IZ
o
..J
....
....
-~(1)..10:
~t.)
N
....
::J
8w
N
c
5
w
c
o
~
ID
~
-~~
2
0:
(1)..1
~t.)
It!!
o
I-
2
t.)
w
0:
TEXAS
..J!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1147
SN54LS691. SN54LS693. SN74LS691. SN74LS693
SYNCHRONOUS COUNTERS WITH· OUTPUT REGISTERS
AND MULTIPLEXED 3-STATE OUTPUTS
typical operating sequences (continued)
T
t-
iii
i
z
~t
~
i
.1
..'" '"
~
-I
-I
r-
C
CD
<
(=)'
CD
CJ)
~
u~
CD
~U
::l ~
::l
It>
~
>--'
..-'" u
..-~ a:
~
'" "
'"
~
«en
a: a:
N
WW
1-1-
ZZ
00
~
::l::l
UU
N
»ecce
««
zz
iii iii
~M
"''''
en en
"''''
::-l::-l
10
2-1148
U
za:
o
'" 0
o '"
..c: 0
"..c:
>-t:
>-
. TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
"'.../
«u
SN54LS696, SN54LS697, SN54LS699, SN74LS696, SN74LS697, SN74LS699
SYNCHRONOUS UP/DOWN COUNTERS
WITH OUTPUT REGISTERS AND MULTIPLEXED 3·STATE OUTPUTS
02424. JANUARY 1981-REVISED MARCH 1988
•
4-Bit Counters/Registers
•
Multiplexed Outputs for Counter or Latched
Data
•
3·State Outputs Drive Bus Lines Directly
•
SN54LS696, SN54LS697,
SN54LS699 ••. J OR W PACKAGE
SN74LS696, SN74LS697,
SN74LS699 ... OW OR N PACKAGE
(TOP VIEW)
'LS696 .. Decade Counter, Direct Clear
'LS697 .. Binary Counter, Direct Clear
'LS699 .. Binary Counter, Synchronous
Clear
description
U/o
CCK
A
B
C
°A
°B
°c
0
00
ENT
LOAD
G
ENP
CCLR
RCK
GNo
These low-power Schottky LSI devices incorporate
synchronous up/down counters, four-bit Ootype registers,
and quadruple two-line to one-line multiplexers with three
state outputs in a single 20-pin package. The up/down
counters are programmable from the data inputs and
feature enable P and enable f and a ripple-carry output
for easy expansion. The register/counter select input
selects the counter when low and the register when high
for the three-state outputs, OA, 0B, 0C, and 00. These
outputs are rated at 12 and 24 milliamperes (54LS/74LS)
for good bus driving performance.
RIC
II
SN54LS696, SN54LS697,
SN54LS699 ..• FK PACKAGE
Ric,
(TOP VIEW)
UIO
(/)
Q)
"':10
u
. . . . uu
«u::J>a::
3
2
(.)
'S
1
Q)
C
Both the counter CCK and register clock RCK are positiveedge triggered. The counter clear CCLR is
active low and is asynchronous on the 'LS696 and
'LS697, synchronous on the 'LS699. Loading of the
counter is accomplished when LOAD is taken low and
a positive transition occurs on the counter clock CCK.
...I
....
....
9 10111213
",: OIUIC!1I°
~t5~ ~
Expansion is easily accomplished by connecting RCO
of the first stage to ENT of the second stage, etc. All
EiiiP inputs can be tied common and used as a master
enable or disable control.
-c
VCC
RCO
..J
schematics of inputs and outputs
eQUIVALENT OF
EQUIVALENT OF
TYPICAL OF
A, B, C, 0 INPUTS
ALL OTHER INPUTS
ALL Q OUTPUTS
13 kn NOM
VCCl$
'OO~s{"
VCC
20 kn NOM
INPUT
--
INPUT
~OUTPUT
PRODUCTION DATA documlnla contain inform.tion
cur.....1 •• of pull/icalio. dill. ProduclI conform 10
.pecification. p. Ihl lerm. of TI.IS Instrum.nll
:'~::::i~{;~w:li ~=:i~n :.r::::9t::'~1
nat
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
RCOOUTPUT
VCC
OUTPUT
2-1149
SN54LS696, SN54LS697,SN54LS699, SN74LS696, SN74LS697, SN74LS699
SYNCHRONOUS UP/DOWN COUNTERS
'
WITH OUTPUT REGISTER,S AND MULTlPL~XED 3-STATE OUTPUTS
logic symbols t
'LS697
'LS696
•
1181 0A
A
-t
-t
s
c
~
D
s
[8[
C
C
[4)
o
[8]
CD
<
CiCD
(I)
'LS699
cr l121 .....Jr::EN:-::2~4--""""tlM:;;UVX---...,
RIC 111
RCK (91
G21
Cll
CTRDIV16
3,5CT=15
Z22
4,5CT=O
V23
22,23
19 RCO
1181 0A
[2]
B
C
D
5
61
14]
[8]
(171 0
(161 ~
(151 0 0
lThese symbols are in accordance with ANSI/IEEE Std. 91-1984 and lEe Publication 617-12.
2-1150
TEXAS •
INSTRUMENlS
POST OFFICE BOX "655012 • DALLAS, TEXAS 75265
(171 Os
(161 0c
(151 0D
SN54LS696, SN74LS696
SYNCHRONOUS UP/DOWN COUNTERS
WITH OUTPUT REGISTERS AND MULTIPLEXED 3-STATE OUTPUTS
logic diagrams (positive logic)
II
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1151
SN54LS697. SN74lS697
SYNCHRONOUS UPIDOWN COUNTERS
WITH OUTPUT REGISTERS AND MULTIPLEXED 3·STATE OUTPUTS
logic diagrams (positive logic) (continued)
-t
-t
rC
CD
<
C:;"
CD
1/1
§
10
2-1152
IQ
a:
"
u
u
«
III
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
u
o
SN54LS698. SN74LS698
SYNCHRONOUS UP/DOWN COUNTERS
WITH OUTPUT REGISTERS AND MULTIPLEXED 3·STATE OUTPUTS
logic diagrams (positive logic) (continued)
~
o'"
•
I/)
Q)
(J
'S;
Q)
C
-'
....
....
'"ua:
I~
I~ I~
'"uu
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·1153
SN54LS699, SN74LS699
SYNCHRONOUS UP/DOWN COUNTERS
WITH OUTPUT REGISTERS AND MULTIPLEXED 3·STATE OUTPUTS
logic diagrams (positive logic) (continued)
•
-t
-t
r-
C
CD
<
c:;"
CD
(I)
2-1154
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN54LS696, SN54LS697, SN54LS699, SN74LS696, SN74LS697, SN74LS699
SYNCHRONOUS UP/DOWN COUNTERS
WITH OUTPUT REGISTERS AND MULTIPLEXED 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage .............................................................. 7 V
Off-state output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: SN54LS696, SN54LS697, SN54LS699 .. , - 55°C to 125°C
SN74LS696, SN74LS697, SN74LS699 ....... ooe to 70°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: Voltage values are with respect to network ground terminals.
recommended operating conditions
SN54LS'
MIN
VCC
IOH
4.5
Supply voltage
High-level output current
0
RCO
Q
IOL
LOW-level output current
fctock
Clock frequency
tw
Pulse duration
tsu
RCO
NOM
5
SN74LS'
MAX
5.5
MIN
4.75
NOM
MAX
5
5.25
-1
-2.6
-0.4
-0.4
12
24
4
8
CCK
0
20
0
20
RCK
0
20
0
20
CCK high or low
25
RCK high or low
25
25
'LS696, 'LS697 CCLR low
20
20
A thru 0
30
30
ENP or ENT
30
30
Setup time
LOAD
30
30
before CCK I
UfD
35
35
25
25
'LS699, CCLR
30
30
30
30
0
0
tsu
Setup time CCK I before RCK I Isee Note 2)
Hold time
TA
Operating free-air temperature
-55
V
mA
mA
MHz
II
25
'LS696, 'LS697, CCLR inactive
th
UNIT
125
0
ns
ns
ns
ns
70
°c
NOTE,2: This set up time ensures the 'register will see stable data from the counter outputs. The clocks may be tied together in which case the
register state will be one clock pulse behind the counter.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-1155
SN54LS696, SN54LS697, SN54LS699, SN74LS696, SN74LS697, SN74LS699
SYNCHRONOUS UPIDOWNCOUNTERS
WITH OUTPUT REGISTERS· AND· MULTIPLEXED 3·STATE· OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VIL
High-level input voltage
Low-level input voltage
VIK
Input clamp voltage
VOH
High~level
VIH
lOW-I rnA
VCC~MIN, VIW2 V,
IOW-4OO I'A
AnyO
VCC=MIN, VIW2 V,
IOL=24mA
RCO
VIL=VIL max
lo,=4mA
RCO
output current,
AnyO
high·level voltage applied
Off~tate output current,
AnyO
10ZL
low-level voltage applied
Input current at maxiII
mum input voltage
,...
A thru 0
Low-level input current
C
lOS
Short-circuit
output current §
<
c:r
CD
ICCH Supply current, outputs high
(I)
2.5
3.2
0.25
0.25
All others
Any 0
-1.5
-1.5
2.4
3.1
2.7
3.2
0.4
V
V
V
0.25
0.4
0.35
0.5
0.25
0.4
0.35
0.5
V
at 2 V,
VO~2.7
V
20
20
I'A
VCC=MAX,
0
at 2 V,
VO=0.4 V
-20
-20
I'A
0.1
0.1
mA
20
20
I'A
-0.4
-0.4
VCC=MAX, VI=0.4 V
VCC=MAX,
ICCL Supply current. outPuts low
ICCZ SupplV current, outputs off
V
0.8
0.4
UNIT
0
-0.2
-0.2
-30
VCC=MAX, VO=O V
RCO
MAX
VCC~MAX,
VCC=MAX, VI=2.7 V
IlL
CD
3.1
VCC=MAX, VI=7 V
High-level input current
TVP'
0.7
IOL=8mA
Off~state
-4
-4
MIN
2
2.4
IOL=12mA
AnyO
10ZH
•
SN74LS'
MAX
IOH=-2.6rnA
VIL=VILrnax
FiCO
IIH
TVP'
VCC~MIN,II=-18 rnA
Any 0
VOL
MIN
2
output voltage Any 0
Low·level output voltage
SN54LS'
TEST CONDITIONSt
PARAMETER
-20
-130
-30
-130
-100
-20
-100
I See Note 3
46
65
46
See Note 4
See Note 5
48
70
48
70
48
70
48
70
All outputs open
mA
mA
65
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*All typlca' values are at Vee"" 5 V, T A == 25° C.
§OnIV one output should be shorted at a time, and duration of the short~circult should not exceed one second.
G is grounded and all other inputs are at 4.5 V.
4. .eCL is measured after two 0 V to 4.5 V to 0 V pulses have been applied to CCI<. and ReI( while all other Inputs are grounded.
6. ICCZ Is measured after two 0 V to 4.5 V to 0 V pulses have been applied to CCK and RCI( while G is at 4.5 V and all other inputs are grounded.
NOTES: 3. ICCH is measured after two 4.5 V to 0 V to 4.5 V pulses have been applied to CCK and ReI( while
switching characteristics, Vee'" Ii V, T A'" 25°e (see note 6)
PARAMETER
tpLH
tpHL
tPLH
tpHL
tPLH
FROM
TO
(INPUT)
(OUTPUT)
CCKt
TEST CONDITIONS
fiCO
RL = 2
ENT
CCKt
kn, CL = 15 pF
RCO
0
tPHL
tPLH
tPHL
tPHL
tPLH
tPHL
tpZH
tPZL
tPHZ
tPLZ
RCKt
~~
0
Q
RIC
0
O.
Q
Ot
0
R L = 667
n, CL = 45 pF
RL = 667 n, CL = 6 pF
NOTE 6: Load circuits· and voltage ~aveforms are shown in Section 1.
2-1156
'LS699
'LS696, 'LS697
MIN
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 6550t 2 • DALLAS. TEXAS 75265
UNIT
TVP
MAX
TVP
MAX
23
40
23
40
ns
23
40
40
ns
13
20
23
13
20
ns
13
20
13
20
ns
12
12
20
ns
17
20
25
17
ns
12
20
12
25
20
17
23
25
17
25
n.
16
·25
16
25
ns
16
25
16
25
ns
19
30
19
30
ns
19
30
19
30
ns
17
17
30
30
17
30
ns
17
30
ns
MIN
ns
ns
40
SN54LS696, SN74LS696
SYNCHRONOUS UP/DOWN COUNTERS
WITH OUTPUT REGISTERS AND MULTIPLEXED 3·STATE OUTPUTS
typical operating sequences
T
I-
0;
i
~
CD
,..
CIO
Ol
Z
s:
o
g
~
Z
:::l
II
I-
~
0
"oc
o
u
In
CD
N
..c:
(,)
"c
~
'"
"S:
ex:
w
'"
C
Z
Ul
«
~
~
CD
......
..J
o
()
w
c
«
()
w
'"
C
«
t/lW
«-'
u
2-1157
SN54LS697. SN54LS69l SN74LS697. SN74LS699
SYNCHRONOUS UP/DOWN COUNTERS
WITH OUTPUT REGISTERS AND MULTIPLEXED 3-STATE OUTPUTS
typical operating sequences (continued)
•
co _
.. co
~d
:J
~
-t
-t
rC
CD
o :J
C 0
o c
1:u.::.
c u
> c
~~
e
ci ,c'
<
ww
......
zz
CII
(.)(.)
,s-CD
~~
00
»
a:
a:
««
zz
1010
....
m$
,..,..
"''''
."
2-1158
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
The TTL Data Book
Mechanical Data
3-1
II
...c
Q)
Q)
3-2
ORDERING INSTRUCTIONS
Electrical characteristics presented in this data book, unless otherwise noted, apply for circuit type(s) listed
in the page heading regardless of package. The availability of a circuit function in a particular package is denoted
by an alphabetical reference above the pin-connection diagram(s). These alphabetical references refer to
mechanical outline drawings shown in this section.
Factory orders for circuits described in this catalog should include a four-part type number as explained in the
following example.
EXAMPLE:
SN
54LS01 J
4
....J!
1. prefix _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
MUST CONTAIN TWO TO FOUR LETTERS
SN
SNJ
JANB
Standard Prefix
JEDEC Publication 101, Class B
MIL-M-38510 Qualified
2. Unique Circuit Description-------------------J
MUST CONTAIN FOUR TO NINE CHARACTERS
(From Individual Data Sheet)
Examples:
5410
545112
74LS295A
74LS645-1
3. Package - - - - - - - - - - - - - - - - - - - - '
~
CO
J, JO, JG, JT, N, NT, P, W (Dual-in-line packages)t
0, OW ("Small Outline" packages)
FK (Leadless ceramic chip carriers)
(From pin-connection diagram on individual data sheet)
4. Instructions (Dash No.) _ _ _ _ _ _ _ _ _ _ _---J
3
•
co
MUST CONTAIN ONE OR TWO LETTERS
PEP processing, level 3 (N or NT packages only)
C
Cii
CJ
"2
CO
.c
CJ
CD
:!:
tThese circuits in duaHn-line packages are shipped in one of the carriers shown below. Unless a specific method of shipment is specified
by the customer (with possible additional costs), circuits will be shipped in the most practical carrier. Please contact your TI sales
representative for the method that will best suit your particular needs.
Oual-in-line (0, OW, J, JO, JG, JT, N, NT, P, W)
-Slide Magazines
-A-Channel Plastic Tubing
- Tape and Reel
-Barnes Carrier (W only)
-Sectioned Cardboard Box
-Individual Plastic Box
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
3-3
•
:s:
C'D
(')
::r
Q)
_.
::l
(')
!.
c
Q)
r+
Q)
3-4
MECHANICAL DATA
0008. 0014. and 0016 plastic "small outline" packages
Each of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulated
within a plastic compound. The compound will withstand soldering temperature with no deformation, and
circuit performance characteristics will remain stable when operated in high-humidity conditions. Leads
require no additional cleaning or processing when used in soldered assembly.
0008, 0014, and 0016
(16-pin package used for illustration I
f
I
6.20 10.2441
5.80 10.2281
4.0010.1571
1,7510.0691
1.35 10.0531
i
7" NOM
4 PLACES
j
l
0,457 10.0181
0.356 10.0141
II
....
0,7910.0311
0,28 {O.011)
PIN SPACING
1.27 10.0501
(See Note AI
~
DIM
A MIN
A MAX
co
CO
8
14
16
4,80
8,55
9,80
(0.189)
(0.337)
(0.386)
5,00
8,74
10,00
(0.197)
(0.344)
(0.394)
C
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
16
CJ
E:
CO
.r:.
CJ
NOTES: A. leads are within 0,25 (0.010) radius of true position at maximum material dimension.
B. Body dimensions do not include mold flash or protrusion.
C. Mold flash or protrusion shall not exceed 0,15 (0.006).
D. Lead tips to be planar within ±O,051 (0.002) exclusive of solder.
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
Q)
:2
3-5
MECHANICAL DATA
DW016. DW020. DW024. and DW028 plastic "small outline" packages
Each of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulated
within a plastic compound. The compound will withstand soldering temperature with no deformation, and
circuit performance characteristics will remain stable when operated in high-humidity conditions. Leads
require no additional cleaning or processing when used in soldered assembly.
DW016. DW020. DW024. and DW028
120-pin package used for lIIustrationl
45·Lr:;:=. .
9,0 (0.3541
0.' (0.021
x
(0.33.1
~
~~
r .'
~
'40
0,230 10,0091
0,785 (0.031)
)ih,
\.- 7° NOM
4PLACESP
1.27 (0.0501
~
~)
~
16
20
24
28 1
A MIN
10.16
(0.4001
12.70
(0.5001
15.29
(0.6021
17.68
A MAX
10.36
10.4081
12.90
(0.5081
15.49
10.6101
DIM
10.6961
17.88
10.7041
ALL LINEAR DiMENSiONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
tThe 28-pin package drawing is presently classified as Advance Information.
NOTES: A. Leads are within 0.25 10.0101 radius of true position at maximum material dimension.
B. Body dimensions do not include mold flash or protrusion.
C. Mold flash or protrusion shall not exceed 0.15 10.0061.
D. Lead tips to be planar within ±0.051 10.0021 exclusive of solder.
3-6
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MECHANICAL DATA
FK020 and FK028 ceramic chip carrier packages
Each of these hermetically sealed chip carrier packages has a three-layer ceramic base with a metal lid
and braze seal. The packages are intended for surface mounting on solder lands on 1,27 (O.050-inch)
centers. terminals require no additional cleaning or processing when used in soldered assembly.
FK package terminal assignments conform to JEDEC Standards 1 and 2.
FK020 and FK028
128-te.minal package shown)
CERAMIC CHIP CARRIERS
JEOEC
OUTLINE
DESIGNATION'
NO.OF
TERMINALS
MS004CB
20
MS004CC
28
A
B
MIN
MAX
MIN
MAX
8.69
(0.3421
11.23
10.442)
9.09
10.3581
11.63
10.4581
7.80
(0.307)
10.31
10.406)
9.09
(0.358)
11.63
(0.458)
• All dimensions and notes for the specified JEDEC outline apply .
•
~
I
0.71 (0.028)
0,56 (0.022)->J
2,03 (0.080)
1,63 (0.064)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-7
MECHANICAL DATA
J014 ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7,62 (0.3001 centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped"lleads require no additional
cleaning or processing when used in soldered assembly.
J014
~19.9410.7851
---I
-I
i: ::::::
!
19.1810.7551
i@@@@@cv®1
0.6310.025IRNOM
7.8710.3101
\4--.....r-
j
7.1110.;~~ 10.2901
m
0)
0 0) 0 0) ® 0
6,22 10.2451
.I
-,
7
0,51 10.0201 MIN
1,2
10.0501 NOM
1~:
-SEATING PLANE
14 PLACESr-I~
0,3610.0141
020 100081
s:
14 PLACES
CD
n
8
GLASS
5.0~~~200)
3,30 10.1301
MIN
SEALANT
~
~
-I r-
2,54 10.1001
1,78 (0,070)
4 PLACES
O.6;4(~~X~k~'N
0.58 10.0231 14 PLACES
o,~~~~.~!~~.• & CI
PIN SPACING 2,54 (0.100) T.P.
(See Note AI
Falls Within JEDEC TO·1 16 and EIA MO·001AA Dimensions
::r
D)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
j
ri"
!.
c
NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal pOSition.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above the
seating plane.
D)
r+
D)
3-8
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MECHANICAL DATA
J016 ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped") leads require no additional
cleaning or processing when used in soldered assembly.
J016
1
r
1.78 (0.070) MAX 16 PLACES
g8
-+- JlA A
! ..~'~~~ l~1 li-lU
.,..----
5,~;:00l
I
3.3~\~ 1301
0,305 (0 012) MIN
4 PLACES
~
GLASS
~~
SEALANT
U L 0.6~21~~~~IE~IN
jr-~ 8:;: mg~~1
PIN SPACING 2.5410.1001 T.P.
(See Note AI
16 PLACES
IS8. Notes Band CI
~:~~ :~:~~~: 4 PLACES
• For memories of 64 bits and up, a few MSI/LSI products in Series 54174 and Series 54S174S that are
•
...co
CO
Q
derived from memory circuit bars. and complex HCMOS parts, this maximum is 7,62 (0.300). All other
dimensions apply without modification.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder·dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above the
seating plane.
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 665012 • DAl.LAS, TEXAS 75265
3-9
MECHANICAL DATA
J020 ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base. ceramic cap. and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7.62 (0.300) centers. Once the leads are compressed and inserted. sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped") leads require no additional
cleaning or processing when used in soldered assembly.
J020
24.7610.9751
rl4-----23.6210.9301
6
'i.
"~'"-"'~{~~~~~~~~j
'i.
1
E/!\
~
20 PLACES
-------;·~I
~:~~:~:~:~:
7.6210.3001
6.22 10.2451
1.78 (0.0701 MAX 20 PLACES
1.2710.0501 NOM
GLASS
1!-1I!".,.;-;I!""'III".......II!""'II!""IIII""'III"ot....
_S~t~~~G
t
• ~
3.3".:t1301
, -_ _ _ _ __
.-J\..-~:~ :~:~~::
20 PLACES
f
0.30510.0121 MINJ
4 PLACES
'1
U
SEALANT
1)4-1t--t+-+It-~::~~g~~1
MIN
~:~: :~:~~~:
20 PLACES
(See Notes B & CI
PIN SPACING 2,54 (0.100) T. P.
(See Note AI
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0.25 (0.0101 of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified. dipped area of the lead extends from the lead tip to at least 0.51 10.0201 above the
seating plane.
3-10
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MECHANICAL DATA
JT024 ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped") leads require no additional
cleaning or processing when used in soldered assembly.
JT024
\00-----32.5111 2801 MAX
----oj
GLASS
SEALANT
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.0101 of its true longitudinal position.
B. This dimension does not apply for solder·dipped leads.
C. When solder-dipped leads
seating plane.
a~e
•
...mm
Q
specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above the
TEXAS
-II
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-11
MECHANICAL DATA
JW024 ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 15,24 (0.600) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped") leads require no additional
cleaning or procesing when used in soldered assembly.
JW024
1 - - - - - - - ~~:: :~:~:: - - - - - - ' 1
@@@@@)@@@@@)@@
0,63 W.02S} R
NOM
14,2 (0.560)
13,1 10.5151
1,91 (0.075)
L~
1,27 (00501 NOM
GLASS SEALANT
-
~~~~~NG
J2::
MMAJl ~
178 100701 MAX 24 PLACES
~
i-j
l~r~022S)
3.810'501
I" I
0,51 (0020) !II~
0,41 (00161" r',18It.0701
0,51 fa 020)
24 PLACES
,
4,06 (0 1601
~~~~~~~~
0,71 (0028) MIN
24 PLACES
ISee Notes B and C)
PIN SPACING 2,54 (0.100) T.P.
(See Note AJ
2,54 (0.1001
"(5'2 (0.060)
4 PLACES
Falls Within JEDEC MO-015AA Dimensions
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES:
A. Each pin centerline is located within 0,25 (0.0101 of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 10.020) above the
seating plane.
...c
Q)
Q)
3-12
.
TEXAS"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
MECHANICAL DATA
JD ceramic side-braze dual-in-line packages
This is a hermetically sealed ceramic package with a metal cap and side-brazed tin-plated leads.
JD016. JD018. JD020. JD022. JD024 (2 versionsl. JD028. JD040. JD048. JD052. and JD064
~b-.
-_BMAX~~·I
, ";': :. ~- - -.n l D []T
~
OR N U M B E R l b J
(0-------------------
Ii
Ii
j . - - - A---o!
1_ _I
~
_ SEATING
1;;..
PLANE
j
t
,
~rffifmmm5.0810.200IMAX
•
~
1.9\1~i.~~~SMAX
II 0.38 10.0151
--II-- 0.20 10.0081
1.7810.0701
0.76 10.03.01
0.51 (0.0201 MIN
1'-1
-01
-..j
~NI
0.3810.0151
....coCO
18
20
22
24
7.62
7.62
10.16
7.62
(0.3001
(0.3001
(0.3001
(0.4001
(0.3001
20.57
23.11
25.65
27.94
30.86
(0.8101
(0.9101
(1.0101
(1.1001
(1.2151
7.37
7.37
(0.2901
7.37
9.91
(0.3901
7.37
C (NOM I
(0.2901
•
0.5310.0211
~~~.S~::::~~
16
A +0.51 (+0.0201
-0.25 (-0.0101
j
7.62
DIM
8 (MAXI
10--2.5410.1001 NOM
3.1810.;251 MIN
(0.2901
C
-u
CO
'2
(0.2901
CO
.s:::.
~NI
u
64
G)
15.24
22.86
~
(0.600)
10.9001
24
28
40
48
52
A +0.51 (+0.020)
15.24
-0.25 (-0.010)
(0.6001
15.24
(0.600)
15.24
(0.600)
15.24
(0.600)
31.8
(1.2501
36.8
52.1
(2.050)
62.2
(2.4501
67.3
82.6
(1.4501
(2.6501
(3.2501
15.0
(0.5901
15.0
(0.5901
15.0
(0.590)
15.0
(0.590)
15.0
(0.6901
22.6
(0.890)
DIM
8 (MAXI
C (NOM I
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY (N INCHES
NOTE A: Each pin centerline
IS
located within 0,25 (0.010) of its true longitudinal position.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-13
MECHANICAL DATA
JG008 ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and an 8-pin lead
frame. The package is intended for insertion in mounting-hole rows 7,62 (0.300) centers (see Note A).
Once the leads are compressed and inserted, sufficient tension is provided to secure the package in the
board during soldering.
JGOOB
0,6310.025) R NOM
/4------1>1--
~:~~ !~:~~~:
8000
7,1110.280)
/4-------~~6,2210.245)
-J
'1
En
1,7810.070) MAX 8 PLACES
1,27 10,050) NOM
1
f
.
I
5,08 10.200)
MAX
GLASS
--SEATING PLANE-~,--lI'-----~1
105'
90'
8 PLACES
J I..-- 0,36
.-Y\\0,20
10.0141
10.0081
8 PLACES
I I
l I
F+I
C
....
I»
I»
I
PIN SPACING
2,5410.100) T.P.
ISee Note A)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
3-14
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
•
MECHANICAL DATA
NO 14 plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation, and circuit
performance characteristics will remain stable when operated in high-humidity conditions. The package
is intended for insertion in mounting-hole rows on 7,62 (0.300) centers (see Note A). Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
N014
19,8 10.7801
'i.
7,62' 0,25
1+---......+-10.300'0.0101
6,35 ± 0,25
10.250,0.0101
I
-.i.
I~
--1
2,010.0801 NOM
"""Tn0,2510.010)
l
•
U:-!-_~
14PLACES
n-SEATING
NOM
PLANE
~.
-I\..-g'~~lg014)
1:'PLA~
18ee Notes Band CI
1-"1,7810.0701 MAX 14 PLACES
'O'5110'020)~
508 10.200) MAX MIN
'.--*-,
.-I
I
,
,
oJ,
,)~
3,1710.125) MIN
2,03:t 0.51
10.080 • 0.020)
4 PLACES
I
~
j.--
0,8410.033) MIN
14 PLACES
--11-0533100211
0:381 (0.015)
(See ~;;$A;:~d CI
PIN SPACING 2,54 10.100) T. P.
(See Note A)
II
....
ca
ca
Falls Within JEDEC TO-116 and EIA MO-001AA Dimensions
C
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
"i
NOTES: A. Each pin centerline is located within 0,25 (0.0101 of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating
plane.
u
'2
ca
.c
u
CD
:IE
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
3-15
MECHANICAL DATA
N016 plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperatljre with no deformation.
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 7.62 (0.300) centers. Once the leads are
compressed and inserted. sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
N016
7,62:t 0.25
(0.300:t 0.010)
6,35 t 0,25
(0.250 ± 0.010)
• 2,0 (0.080) NOM
0,84 iO.033) MIN
(See Notes 8 and C)
(See Notes B and C)
Parts may be supplied in accordance
s:
CD
ALTERNATE SIDE VIEW
with the alternate side view at the
option of TI plants located in Europe.
In this case, the overall length of the
package is 22,1 (0.8701 max.
n
:::r
I»
::s
---1 1-- ,
,78 (0.070) MAX 16 PLACES
f O'51~~~20)mwwo
5,08 (0.200) MAX L
(i"
-C
3,17 (0.125) MIN
I»
I»
r+
I»
LI I
~
L
~
0,84 (0.033) MIN
16 PLACES
-II-- g:~~~ :g:g~~i
IS.:~:t~~~E:"d
2,41 (0,095)
1,02 (0.040)
PIN SPACING 2,54 (0.100) T.P.
4 PLACES
(See Note Al
CI
ALL LINEAR D(MENS(ONS ARE (N MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES:
3-16
A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating
plane.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 65501.2 • DALLAS, TEXAS 75265
MECHANICAL DATA
N020 plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
N020
7,62 + 0,25
(0.300 t 0.010)
(See Notes Band C1
J~ ~
L
r-1,02 (O.040j
4 PLACeS
VIEW A
Parts may be supplied in accordance
with the alternate side view at the
option of TI. European-manufactured
parts may have pin 1 as shown in
view A. Alternate-side·view parts
manufactured outside of the USA
may have a maximum package length
of 26,7 11.050).
4 PLACES
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating
plane.
TEXAS ~
INSlRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-17
MECHANICAL DATA
N028 plastic dual-In-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 15,24 (0.600) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require. no additional cleaning or processing when used in soldered assembly.
N028
10------36.611.4401 M A X - - - - - - 0 1
0.51 10.0201
•
s:
CD
10.011 ± D.0031
2. PLACES
IS.. Notes Band CI
jl
~;;::;::;:;:;:;;::;::;:::;:;::::;;::::;~:;::;:J-r
.~ . ~~~::,!=
MIN
10.G18 ± D.0031
28 PLACES PIN SPACING 2.5410 1001 T.P.
ISee NOles B and C)
(See Note
Al
~~ :'~8::;:::N
1,40 ± 0,18
1,27 ± 0 51
10.050 ± 0:0201
4 PLACES
10.055 ± 0.00701
n
::r
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
CD
:::s
n°
e.
c
NOTES: A. Each pin centerline is located within 0,2510.0101 of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified. dipped area of the lead extends from the lead tip to at least 0,51 10.0201 above seating
plane.
S
3-18
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
MECHANICAL DATA
N040 plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation.
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 15.24 (0.600) centers. Once the leads are
compressed and inserted. sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
N040
I'
'I
53,"2.00" MAX
m,~:~~~i::::::::::::::::::I.'.10---
-~@
"- 15,24'.0,25 "110.600 ~ 0.010)
!r
~.
goe
0,51(0.020)
Jj
~h=lWiri:;;::::;;:::;;;:::;;:::;;~;:::;;:::;;:::;;::;;::=;;::;::;;::::;;:::;;:;=;:;::;;:::;;:::;;:;;:;:150!10200IMAX
-SEATINGPLANE,-V
a,2aiD,OS
(0.011 t O,00311r-40 PLACES
1\
ISee NOles B and CI
~ V1[ ~
0457+0076'""""11"'"1
{O 018' 0 0031
40 PLACES
ISee Notes Bend CI
I
~ PIN SPACING 2 54 (0 lOa) T P
{Slit! Note Al
~ ~'7(0125)MIN
~
084 (0033) MIN
2,41 (0095)
140 (0055)
1,52 fO 060) NOM
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
L -______________________________________________~______________~
NOTES:
A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C, When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 10,020) above seating
plane.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
II
....
m
m
C
3-19
MECHANICAL DATA
NT024 plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
NOTE: For all except 24-pln packages, the letter N is used by itself since only the 24-pin package is available in more than one row-spacing.
For the 24-pin package, the 7.62 10.3001 version is designated NT; the 15.2410.6001 version is designated NW. If no second
letter or row-spacing is specified, the package is assumed to have 15,24 10.600) row-spacing.
NT024
~
31,811.2501
I~~
I
I
7,1 (0.280) MAX
• -..j
I
lOS'
!iii'
24 PLACES
-:~O'25(0'010INOM5'08~
c
~
MAX
-SEA TlNG PLANE
J\..-- 0,36 (0.014)
' I \'
0,25 (0.010)
24 PLACES
ISee Note. B
and CI
S»
r+
S»
0000000000@<0
2,010.0801 NOM
±MIN--01 10--- 1.78 (0.070) 24 PLACE. S
~~1~1___'_.'_4_(0_.0_4_5_)__________________~
li1
~
0,38 (0.015)
I
28,6(1.1251
---i1C---~JT
_
4.06 (0.160)
3,17 (0.125)
2.16 (0.085)
0,71 (0.028)
4 PLACES
-
- ~
-0\
I
~
~ 1.14 (0:045) MIN
24 PLACES
I
~ L.;....c:o-"~co.,
7.0 10. 275
ISe. Not. B)
21.8410.860)
21.3410.840)
]6.
IS•• Not. Ch ~
7310.265)
5.97 10.235)
--r
t
2.03 10.0601~
1.27 (0.050)~
~.48310.019)
0.38110.015)
14 LEADS
~~~~~~
)-
!ca
8.0010.316)
6.86 [10,270)
C
1.0210.0401_
0.5110.020) -
I[-
.-I ~ 0.64 10.025)
~ 8.8910.350) ----=-'-1- 0.25 (0.010)
,..--- 8.56 10.337) 4 PLACES
0000000
Fall Within JEDEC MO·004AA Dimensions
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
ca
C,)
·C
ca
.cC,)
CD
:E
JIIOTES: A. Leads are within 0.13 10.005) radius of true position (T.P.) at maximum material condition.
B. This dimension determines a zone within which all body and lead irregularities lie.
C. Index point is provided on cap for terminal identification only.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
3-23
I
f:
MECHANICAL DATA
WO 16 ceramic flat packages
This hermetically sealed flat pac/
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