1988_TI_TMS34010_Users_Guide 1988 TI TMS34010 Users Guide

User Manual: 1988_TI_TMS34010_Users_Guide

Open the PDF directly: View PDF .
Page Count: 664

Download
Open PDF In Browser	View PDF

"TEXAS

INSTRUMENTS

TAfS34010

1988

Graphics Products

TAfS34010 Use,'s Guide

TEXAS

INSTRUMENTS

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to discontinue
any semiconductor product or service identified in this publication without
notice. TI advises its customers to obtain the latest version of the relevant information to verify, before placing orders, that the information being relied
upon is current.
TI warrants performance of its semiconductor products to current specifications in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this
warranty. Unless mandated by government requirements, specific testing of
all parameters of each device is not necessarily performed.
TI assumes no liability for TI applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
Nor does TI warrant or represent that license, either express or implied, is
granted under any patent right. copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or
process in which such semiconductor products or services might be or are
used.

Contents

Section
1
1.1
1.2
1 .3
1.3.1
1 .3.2
1.4
1.5
1.6

Introduction
TMS34010 Overview . . . . .
Key Features
.... .
Architectural Overview
TMS34010 Block Diagram . . . .
Other Special Processing Hardware
........ .
Typical Applications
Manual Organization . . . . . . . . . . . . . . . . . . . .
Related Documentation, References, and Suggested Reading

Pin Functions
Pinout and Pin Descriptions
Host Interface Bus Signals ..
Local Memory Interface Signals
Video Timing Signals . . . . . . .
Hold and Emulator Interface Signals
Power, Ground, and Reset Signals

2.1
2.2
2.3
2.4
2.5
2.6

Page
1-1
1-2
1-3
1-4
1-5

1-7
1-8
1-9
1-11

2-1
2-2
2-5

2-7
2-9
2-10
2-11

Memory Organization
3.1
Memory Addressing
3.2
Memory Map
3.3
Stacks . . . . . . .
System Stack
3.3.1
Auxiliary Stacks
3.3.2

3-1

4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.4

Hardware-Supported Data Structures
Fields . . . . . . . . .
Pixels . . . . . . . . .
Pixels in Memory .
Pixels on the Screen
Display Pitch
XV Addressing
. .
XV -to- Linear Conversion
Pixel Arrays . . . . . . . . .

4-1

5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.2
5.3
5.4
5.4.1
5.4.2
5.4.3

CPU Registers and Instruction Cache
General-Purpose Registers
..... .
Register File A
..... .
Register File B
Stack Pointer . . . . . . .
Implied Graphics Operands
Status Register
Program Counter . . . . . . .
Instruction Cache . . . . . . .
Cache Hardware
..... .
Cache Replacement Algorithm
Cache Operation
...... .

5-1

3-2
3-4
3-6
3-6
3-9

4-2
4-6
4-6

4-7
4-10

4-11
4-12
4-15

5-2
5-2
5-3
5-4
5-5
5-18
5-19
5-20
5-20
5-21
5-22

iii

Self-Modifying Code . . . . . . . . . . . . . . . . . .
5.4.4
5.4.5
Flushing the Cache
..................
Cache Disable . . . . . . . . . . . . . . . . . . . . . .
5.4.6
Performance with Cache Enabled versus Cache Disabled
5.4.7
5.5 Internal Parallelism . . . . i. . • • • . • • . • • • • • • • .
6
6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.4

I/O Registers
I/O Register Addressing
.....
Latency of Writes to I/O Registers
I/O Registers Summary . . . . . .
Host Interface Registers
Local Memory Interface Registers
Interrupt Interface Registers
Video Timing and Screen Refresh Registers
Alphabetical Listing of I/O Registers . . . . .

7
Graphics Operations
7.1
Graphics Operations Overview
Pixel Block Transfers . . . . .
7.2
7.2.1
Color- Expand Operation
7.2.2
Starting Corner Selection .
7.2.3
Interrupting PixBlts and Fills
7.3
Pixel Transfers
....... .
Incremental Algorithm Support
7.4
7.5 Transparency . . . . . . . .
Plane Masking
....... .
7.6
7.7
Pixel Processing
...... .
7.8
Boolean Processing Examples
7.8.1
Replace Destination with Source
Logical OR of Source with Destination
7.8.2
7.8.3
Logical AND of NOT Source with Destination
Exclusive OR of Source with Destination
7.8.4
7.9
Multiple-Bit Pixel Operations
......... .
Examples of Boolean and Arithmetic Operations
7.9.1
7.9.2
Operations on Pixel Intensity . . . . .
7.1 0 Window Checking
........... .
7.10.1
W=1 Mode-Window Hit Detection
W=2 Mode - Window Miss Detection
7.10.2
W=3 Mode - Window Clipping
7.10.3
7.10.4
Specifying Window Limits
7.10.5
Window Violation Interrupt
7.10.6
Line Clipping . . . . . . .

8
8.1
8.2
8.3
8.4
8.5
8.5.1
8.6
8.7
8.8
8.8.1
8.8.2
iv

Interrupts. Traps. and Reset
Interrupt Priorities and Vector Addresses
Interrupt Interface Registers
External Interrupts
Internal Interrupts ..
Interrupt Processing
Interrupt Latency
Traps
....... .
Illegal Opcode Interrupts
Reset . . . . . . . . . .
Asserting Reset
Suspension of DRAM-Refresh Cycles During Reset

.
.
.
•

5-23
5-23
5-24
5-24
5-25

6-1
6-2
6-4
6-5
6-7
6-8
6-8
6-9
6-10

7-1
7-2
7-4
7-5
7-7
7-8
7-10
7-10
7-11
7-12
7-15
7-17
7-18
7-18
7-18
7-18
7-19
7-19
7-22
7-25
7-26
.7-27
7-27
7-28
7-29
7·29

8-1
8-2
8-3
8-3
8·5
8·6
8·7
8-9
8·9
8-10
8·10
8·11

8.8.3
8.8.4
8.8.5

State of VCLK During Reset
Initial State Following Reset
Activity Following Reset

8-11
8-11
8-12

9
Screen Refresh and Video Timing
9.1
Screen Sizes
........................ .
9.2 Video Timing Signals . . . . . . . . . . . . . . . . . . . . .
9.3 Video Timing Registers . . . . . . . . . . . . . . . . . . . .
9.4
Relationship Between Horizontal and Vertical Timing Signals
9.5
Horizontal Video Timing
9.6 Vertical Video Timing . . . . .
9.6.1
Noninterlaced Video Timing
9.7
Display Interrupt
9.8
Dot Rate
......... .
9.9
External Sync Mode
9.9.1
A Two-GSP System ' ..
9.9.2
External Interlaced Video
9.10 Video RAM Control . . . . .
9.10.1
Screen Refresh
.... .
9.10.2
Video Memory Bulk Initialization

9-1
9-2
9-3
9-4
9-5
9-6
9-8
9-9
9-13
9-14
9-15
9-15
9-17
9-18
9-18
9-26

10
Host Interface Bus
10.1 Host Interface Bus Pins
10.2 Host Interface Registers
10.3 Host Register Reads and Writes
10.3.1
Functional Timing Examples
10.3.2
Ready Signal to Host
10.3.3
Indirect Accesses of Local Memory
10.3.4
Halt Latency
...........
.
10.3.5
Accommodating Host Byte-Addressing Conventions
10.4 Bandwidth
10.5 Worst-Case Delay

10-1

11
Local Memory Interface
11.1 Local Memory Interface Pins
11.2 Local Memory Interface Registers
11.3 Memory Bus Request Priorities .
11.4 Local Memory Interface Timing
11.4.1
Local Memory Write Cycle Timing
11.4.2
Local Memory Read Cycle Timing
11.4.3
Local Register-to-Memory Cycle Timing
11.4.4
Local Memory-to-Register Cycle Timing
11.4.5
Local Memory RAS-Only DRAM Refresh Cycle Timing
11.4.6
Local Memory CAS-before-RAS DRAM Refresh Cycle Timing
11.4.7
Local Memory Internal Cycles
11.4.8
I/O Register Access Cycles ..
11.4.9
Read- Modify-Write Operations ..
11 .4.10 Local Memory Wait States
11.4.11 Hold Interface Timing . . . . . . .
11.4.12 Local Bus Timing Following Reset
11.5 Addressing Mechanisms . . . . . . .
11.5.1
Display Memory Hardware Requirements
11.5.2
Memory Organization and Bank Selecting
11.5.3
Dynamic RAM Refresh Addresses
11.5.4
An Example - Memory Organization and Decoding

11-1

10-2
10-2
10-4
10-5
10-8
10-11
10-19
10-20
10-22
10-23

11-2
11-3
11 -4
11-5
11-7
11-8
11-9
11-10
11 -11
11 -12
11-13
11-13
11-15
11-16
11-18
11-22
11-23
11-24
11-25
11-25
11-28

12
TMS34010 Instruction Set
12.1 Style and Symbol Conventions . . . . .
12.2 Addressing Modes and Operand Formats
Immediate Values and Constants
12.2.1
12.2.2
Absolute Addresses . . . . .
12.2.3
Register-Direct Operands . . . . . .
12.2.4
Register-Indirect Operands . . . . .
12.2.5
Register-Indirect with Offset
12.2.6
Register-Indirect with Postincrement
12.2.7
Register-Indirect with Predecrement
12.2.8
Register-Indirect in XV Mode
12.3 Instruction Set Summary Table . . . . . . .
12.4 Arithmetic, Logical, and Compare Instructions
12.5 Move Instructions Summary
12.5.1
Register-to- Register Moves
Value-to- Register Moves
12.5.2
XV Moves . . . . . . . .
12.5.3
12.5.4
Multiple-Register Moves
12.5.5
Byte Moves . . . . . . .
12.5.6
Field Moves . . . . . . .
12.6 Graphics Instructions Summary
12.6.1
Comparing a Point to a Window . . . . . .
12.6.2
Converting an XV Address to a Linear Address
12.6.3
Drawing a Pixel and Advancing to the Next Pixel Address
12.6.4
Draw a Line . . . . . . . . . . . . . . . . .
Filling a Pixel Block . . . . . . . . . . . . .
12.6.5
.......... .
12.6.6
Moving a Single Pixel
12.6.7
Moving a Two-Dimensional Block of Pixels
12.6.8
Implied Operands . . . . . . . . . . . . . . . .
12.7 Program Control and Context Switching Instructions
12.7.1
Subroutine Calls and Returns
......... .
12.7.2
Interrupt Handling
............... .
Setting, Saving, and Restoring Status Information
12.7.3
Jump Instructions
....... .
12.7.4
12.8 Shift Instructions . . . . . . . . . . .
12.9 XV Instructions . . . . . . . . . . . .
12.10 Alphabetical Reference of Instructions

12-1
12-2
12-4
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
12-12
12-19
12-20
12-20
12-20
12-20
12-21
12-21
12-22
12-26
12-26
12-26
12-26
12-26
12-26
12-27
12-27
12-28
12-29
12-29
12-29
12-29
12-30
12-32
12-33
12-34

13
Instruction Timings
13.1 General Instructions
.............. .
13.1 .1
Best Case Timing - Considering Hidden States
13.1.2
Other Effects on Instruction Timing
13.2 MOVE and MOVB Instructions . . . . . .
13.2.1
Moves Between Registers and Memory
13.2.2
Memory-to-Memory Moves
MOVE Timing Example
13.2.3
13.3 FILL Instructions
13.3.1
FILL Setup Time
FI LL Transfer Timing
13.3.2
13.3.3
FILL Timing Examples
Interrupt Effects on FILL Timing
13.3.4
13.4 PIXBLT Instructions
13.4.1
PIXBLT Setup Time ..
13.4.2
PIXBLT Transfer Timing

13-1
13-2
13-2
13-3
13-4
13-5
13-6
13-8
13-10
13-10
13-11
13-14
13-17
13-18
13-18
13-20

13.4.3
PIXBLT Timing Examples . . . . . . . . . . ..
13.4.4
The Effect of Interrupts on PIXBLT Instructions
13.5 PIXBLT Expand Instructions
PIXBLT Setup Time . . .
13.5.1
13.5.2
PIXBLT Transfer Timing
13.5.3
PIXBLT Timing Examples
13.5.4
The Effect of Interrupts
A
8
C

TM S3401 0 Data Sheet
System Design Considerations
Software Compatibility with Future GSPs
Glossary

13-26
13-30
13-31
13-31
13-32
13-37
13-40

A-1
8-1
C-1
0-1

vii

Illustrations

Figure
1-1

1-2
2-1
2-2
3-1

3-2
3-3
3-4

3-5
3-6
3-7
4-1
4-2
4-3
4-4

4-5
4-6
4-7
4-8

4-9
4-10
4-11
4-12
5-1

5-2
5-3
5-4
5-5

5-6
5-7
5-8
5-9
6-1
6-2
6-3
7-1
7-2
7-3
7-4

7-5
7-6
7-7

7-8
7-9
7-10
7-11
7-12

8-1
9-1

viii

System Block Diagram
....................................... .
Internal Architecture Block Diagram
............................. .
TMS34010 Pinout (Top View)
'" .............................. .
TMS34010 Major Interfaces
................................... .
Logical Memory Address Space
................................ .
Physical Memory Addressing
.................................. .
TMS34010 Memory Map
..................................... .
System Stack ............................................... .
Stack Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
An Auxiliary Stack that Grows Toward Lower Addresses ............. .
An Auxiliary Stack that Grows Toward Higher Addresses
............ .
Field Storage in External Memory ............................... .
Field Alignment in Memory .................................... .
Field Insertion
.............................................. .
Pixel Storage in External Memory ............................... .
" .......................... .
Mapping of Pixels to Monitor Screen
Configurable Screen Origin .................................... .
Display Memory Dimensions ................................... .
Display Memory Coordinates
.................................. .
Pixel Addressing in Terms of XY Coordinates ...................... .
...................... .
Concatenation of XY Coordinates in Address
............... .
Conversion from XY Coordinates to Memory Address
Pixel Array ................................................. .
Register File A .............................................. .
Register File B .............................................. .
Stack Pointer Register ........................................ .
............................................. .
Status Register
Program Counter ............................................ .
TMS34010 Instruction Cache .................................. .
....................................... .
Segment Start Address
Internal Data Paths
.......................................... .
Parallel Operation of Cache, Execution Unit, and Memory Interface
I/O Register Memory Map
.................................... .
Correlation Between SRFADR and Logical Address Bits
............. .
Correlation Between DPYADR Bits and Row/Column Addresses
...... .
Color-Expand Operation
...................................... .
..................................... .
Starting Corner Selection
Transparency ............................................... .
Read Cycle With Plane Masking
................................ .
................. .
Write Cycle With Transparency and Plane Masking
................................ .
Graphics Operations Interaction
Examples of Operations on Single-Bit Pixels
...................... .
Examples of Boolean and Arithmetic Operations
................... .
Examples of Operations on Pixel Intensity
........................ .
.................................... .
Specifying Window Limits
Outcodes for Line Endpoints ................................... .
Midpoint Subdivision Method
................................. .
......................................... .
Vector Address Map
Horizontal and Vertical Timing Relationship
....................... .

Page
1-4
1-5

2-2
2-3
3-2
3-3
3-4
3-7

3-8
3-10
3-11
4-2
4-3

4-5
4-7
4-7
4-8

4-9
4-9
4-11

4-12
4-13

4-15
5-2

5-3
5-4
5-18
5-19
5-20

5-21
5-25

5-26
6-2
6-18
6-18
7-6
7-7

7-11
7-13
7-14

7-16
7-17
7-19
7-22
7-28
7-30

7-31
8-2
9-5

9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
11 -1
11 -2
11 -3
11 -4
11-5
11-6
11-7
11-8
11 -9
11 -10
11-11
11 -1 2
11 -13
11 -14
11 -15
11 -16
11 -17
11-18
11 -19
11 -20
11-21
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9

Horizontal Timing
........................................... .
Horizontal Timing Logic - Equivalent Circuit
...................... .
Example of Horizontal Signal Generation
......................... .
Vertical Timing for Noninterlaced Display ......................... .
Vertical Timing Logic - Equivalent Circuit ......................... .
Electron Beam Pattern for Noninterlaced Video
.................... .
Noninterlaced Video Timing Waveform Example .................... .
Electron Beam Pattern for Interlaced Video ........................ .
Interlaced Video Timing Waveform Example ....................... .
.......................... .
External Sync Timing - Two GSP Chips
Screen-Refresh Address Registers ............................... .
Logical Pixel Address
........................................ .
Screen - Refresh Address Generation
............................. .
Equivalent Circuit of Host Interface Control Signals ................. .
Host 8- Bit Write with HCS Used as Strobe
....................... .
Host 8- Bit Read with H CS Used as Strobe
....................... .
Host 16-Bit Read with R"READ Used as Strobe
.................... .
Host 16-Bit Write with HWRITE Used as Strobe
................... .
Host 16-Bit Write with RlJ)S, "RUDS Used as Strobes
.............. .
Host 16-Bit Read with HLDS, HUDS Used as Strobes
.............. .
Host Interface Timing - Write Cycle With Wait ..................... .
Host Interface Timing - Read Cycle With Wait
..................... .
Host Indirect Read from Local Memory (INCR=1) .................. .
................... .
Host Indirect Write to Local Memory (INCW=1)
Indirect Write Followed by Two Indirect Reads (INCW=1, INCR=O)
Calculation of Worst-Case Host Interface Delay .................... .
Triple Multiplexing of Addresses and Data
........................ .
Rowand Column Address Phases of Memory Cycle
................ .
Local Bus Write Cycle Timing
.................................. .
Local Bus Read Cycle Timing
.................................. .
Local Bus Register-to-Memory Cycle Timing
...................... .
Local Bus Memory-to-Register Cycle Timing
...................... .
Local Bus RAS-Only DRAM-Refresh Cycle Timing
................. .
Local Bus CAS-before-RAS DRAM-Refresh Cycle Timing
........... .
Local Bus Internal Cycles Back to Back
.......................... .
I/O Register Read Cycle Timing
................................ .
I/O Register Write Cycle Timing
................................ .
Local Bus Read Cycle with One Wait State
....................... .
Local Bus Write Cycle with One Wait State
....................... .
Local Bus Register-to- Memory Cycle with One Wait State
........... .
TMS34010 Releases Control of Local Bus
........................ .
TM S3401 0 Resumes Control of Local Bus ........................ .
Local Bus Timing Following Reset
.............................. .
External Address Format
...................................... .
Row Address for 0 RAM - Refresh Cycle
.......................... .
Address Decode for Example System
............................ .
Display Memory Dimensions for the Example ...................... .
An Example of Immediate Addressing ............................ .
An Example of Absolute Addressing
............................. .
An Example of Register-Direct Addressing
........................ .
An Example of Register-Indirect Addressing ....................... .
An Example of Register-Indirect with Offset Addressing
............. .
An Example of Register-Indirect with Postincrement Addressing ....... .
An Example of Register-Indirect with Predecrement Addressing
....... .
Register-to-Memory Moves
................................... .
Memory-to- Register Moves
................................... .

9-6
9-7
9-7
9-8
9-9
9-9
9-10
9-11
9-12
9-16
9-19
-9-21
9-22
10-4
10-5
10-6
10-6
10-7
10-7
10-8
10-10
10-10
10-13
10-15
10-16
10-23
11-5
11-6
11-7
11-8
11-9
11 -10
11 -11
11-12
11 -13
11-14
11-15
11 -16
11 -17
11 -18
11-19
11-21
11-22
11-23
11-27
11-28
11-29
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-23
12-24
ix

12-10
12-11
12-12
12-13
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16

Memory-to-Memory Moves
.......................... ..... .....
Implied Operand Setup for LINE Timing Example ....................
LINE Timing Example
... ........... ............... .... ........
LINE Examples
..............................................
Field Alignments in Memory .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Source Data, Alignment G ......................................
Destination Location, Alignment E
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pixel Block Alignment in X
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pixel Block Alignments
'" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Implied Operand Setup for FILL Example . . . . . . . . . . . . . . . . . . . . . . . . ..
FI LL XY Timing Example .......................................
Pixel Block Alignment in X
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pixel Block Alignments
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Source to Destination Alignments ................................
Implied Operand Setup for PIXBLT Timing Examples .................
PIXBLT XY,L Timing Example ...................................
Pixel Block Alignment in X
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Pixel Block Row Alignments ....................................
Implied Operand Setup for PIXBLT - Expand Examples
. . . . . . . . . . . . . . ..
PIXBLT B,XY Timing Example ...................................

12-25
12-10
12-10
12-10
13-4
13-8
13-8
13-11
13-12
13-14
13-15
13-21
13-22
13-23
13-26
13-27
13-33
13-34
13-37
13-38

Tables

Table
1 -1

2-1
2-2
2-3
2-4
2-5
2-6
5-1
5-2
5-3
5-4
6-1
7-1
7-2
8-1
8-2
8-3
8-4
8-5
8-6
8-7
9-1
9-2
10-1
10-2
10-3
10-4
11 -1

Page
Typical Applications of the TMS3401 0 ........................... .
............................................ .
Pin Descriptions
Host Interface Signals ........................................ .
Local Bus Interface Signals .................................... .
Video Timing Signals
........................................ .
Hold and Emulator Interface Signals ............................. .
.............................. .
Power, Ground, and Reset Signals
B-File Registers Summary ..................................... .
............................. .
Definition of Bits in Status Register
Decoding of Field-Size Bits in Status Register ..................... .
.................................. .
Instruction Effects on the PC
I/O Registers Summary ....................................... .
Boolean Pixel Processing Options
.............................. .
.................... .
Arithmetic (or Color) Pixel Processing Options
Interrupt Priorities
........................................... .
..................................... .
External Interrupt Vectors
Interrupts Associated with Internal Events
........................ .
Six Sources of Interrupt Delay
................................. .
Sample Instruction Completion Times ............................ .
Illegal Opcodes Ranges ....................................... .
State of Pins During a Reset ................................... .
.................... .
Programming GSP #2 For External Sync Mode
Screen-Refresh Latency
...................................... .
............................... .
Host Interface Register Selection
.................................... .
Five Sources of Halt Delay
Sample Instruction Completion Times ............................ .
Host Interface Estimated Bandwidth ............................. .
Priorities for Memory Cycle Requests
............................ .

1-8
2-3
2-5
2-7
2-9
2-10
2-11
5-5
5-18
5-19
5-19
6-5
7-15
7-15
8-2
8-4
8-5
8-8
8-8
8-9
8-11
9-16
9-25
10-2
10-20
10-20
10-22
11-4

12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
B-1

Instruction Set Symbol and Abbreviation Definitions .. . . . . . . . . . . . . . .. 12-2
Summary of Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-20
Summary of Operand Formats for the MOVB Instruction
.. . . . . . . . . . . .. 12-21
Summary of Operand Formats for the MOVE Instruction
. . . . . . . . . . . . .. 12-22
Summary of Operand Formats for the PIXT Instruction
. . . . . . . . . . . . . .. 12-27
Summary of Array Types for the PIXBLT Instruction
. . . . . . . . . . . . . . . .. 12-27
Implied Operands Used by Graphics Instructions ...... . . . . . . . . . . . . .. 12-28
Condition Codes for JRcc and JAcc Instructions .................... 12-31
Summary of XV Instructions
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-33
LINE Transfer Timing
......................................... 12-10
Per-Word Timing Values for Pixel Processing (P)
. . . . . . . . . . . . . . . . . .. 12-10
MOVE and MOVB Memory-to-Register Timings
. . . . . . . . . . . . . . . . . . .. 13-5
MOVE and MOVB Register-to- Memory Timings
. . . . . . . . . . . . . . . . . . .. 13-6
Alignment Indices for Memory-to-Memory Moves ................... 13-6
MOVE Memory-to-Memory Timings .............................. 13-7
FILLSetupTime
............................................. 13-10
FILL Transfer Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-11
Timing Values per Word for Graphics Operations (G)
. . . . . . . . . . . . . . .. 13-13
PIXBLTSetupTime ........................................... 13-18
PIXBLT Transfer Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-20
Timing Values per Word for Graphics Operations (G)
. . . . . . . . . . . . . . .. 13-24
PIXBLT Expand Setup Time
.................................... 13-32
PIXBLT Expand Transfer Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-32
Timing Values per Word for Graphics Operations (G)
. . . . . . . . . . . . . . .. 13-36
Loading .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. B-2

xii

Section 1

Introduction

The TMS34010 Graphics System Processor (GSP) is an advanced 32-bit
microprocessor, optimized for graphics systems. The TMS3401 0 is a member
of the TMS340 family of computer graphics products from Texas Instruments.
A single TMS3401 0 provides a cost-effective solution in applications that require efficient data manipulation. The TMS3401 0 can be configured to serve
in either a host-based or a stand-alone environment. Systems based on multiple TMS34010 devices are implemented using special features of the
TMS34010's local and host interfaces.
The TMS3401 0 is well supported by a full set of hardware and software development tools, including a full-speed emulator, a software simulator, an
IBM-PC development board, a C compiler, predeveloped software libraries,
and assembly language tools.
Topics covered in this introductory section include:

Section
Page
1.1 TMS34010 Overview ................................................................................ 1 -2
1.2 Key Features ............................................................................................... 1 -3
1.3 Architectural Overview .............................................................................. 1 -4
1.4 Typical Applications .................................................................................. 1 -8
1.5 Manual Organization ................................................................................. 1-9
1.6 Related Documentation, References, and Suggested Reading ......... 1 -11

1-1

Introduction - TMS3401 0 Overview

1.1 TMS34010 Overview
The TMS3401 0 combines the best features of general-purpose processors and
graphics controllers to create a powerful and flexible Graphics System Processor. Key features of the TMS34010 are its speed, high degree of programmability, and efficient manipulation of hardware-supported data types
such as pixels and two-dimensional pixel arrays.
The TMS34010's unique memory interface reduces the time needed to perform tasks such as bit alignment and masking. The 32-bit architecture supplies the large blocks of continuously-addressable memory that are necessary
in graphics applications. TMS34010 system designs can take advantage of
video RAM (such as the TMS4461) technology to facilitate applications such
as high-bandwidth frame buffers; this circumvents the bottleneck often encountered when using conventional DRAMs in graphics systems.
The TMS3401 0 instruction set includes a full complement of general-purpose
instructions, as well as graphics functions, from which you can construct efficient high-level functions. The instructions support arithmetic and Boolean
operations, data moves, conditional jumps, and subroutine calls and returns.
The TMS34010 architecture supports a variety of pixel sizes, frame buffer
sizes, and screen sizes. On-chip functions have been carefully selected so that
no functions tie the TMS34010 to a particular display resolution. This enhances the portability of graphics software, and allows the TMS34010 to
adapt to graphics standards such as MIT's X, CGI/CGM, GKS, NAPLPS,
PHIGS, and evolving industry and display management standards.

1-2

Introduction - Key Features

1.2 Key Featu res
•

Fully programmable 32-bit general-purpose processor

•

128-megabyte address range

•

Instruction cycle times:
132 ns (TMS34010-60)
160 ns (TMS34010-50)
200 ns (TMS34010-40)

•

On-chip peripheral functions include:
Programmable CRT control (horizontal sync, vertical sync, and
blanking)
Direct interfacing to conventional DRAMs and multiport video
RAMs
Automatic CRT display refresh
Direct communications with an external (host) processor

•

Instruction set includes special graphics functions such as pixel
processing, XY addressing, and window clip/hit

•

Programmable 1, 2, 4, 8, or 16-bit pixel size with 16 Boolean and
6 arithmetic pixel-processing options

•

30 general-purpose 32-bit registers

•

256-byte on-chip instruction cache

•

Dedicated 8/16-bit host-processor interface and HOLD/HLDA interface

•

32-bit and 64-bit integer arithmetic

•

High-level language support

•

Full line of hardware and software development tools including:
C compiler
Macro assembler
Linker
Archiver
Software application libraries
XDS (Extended Development Support) in-circuit emulator
Software development board (SDB)
ROM utility
Simulator
Symbolic debugger

•

68-pin PLCC package

•

5-V CMOS technology

1-3

Introduction - Architectural Overview

1.3 Architectural Overview
Figure 1 -1 illustrates the TMS34010's major internal functions and its interfaces to external devices. The on-chip processor executes both graphics instructions and general-purpose instructions. The TMS3401 0 is a true 32-bit
processor, with 32-bit internal data paths, a 32-bit ALU, and a large address
space. Thirty 32-bit general-purpose registers, a 32-bit stack pointer, and a
256-byte instruction cache increase performance. Nonprocessor functions
included on the chip include CRT timing, screen refresh, and DRAM refresh.
Separate physical interfaces are provided for communicating with a host processor, for providing the video timing signals necessary to control a CRT
monitor, and for connecting directly to dynamic RAMs (like the TMS4256 or
TMS4C1024) and video RAMs (such as the TMS4461).

~~~~B_~~_~~~~_~~d~ ___ ] _
I
HoIt-GraphloB
Interface

GraphloB
Procseeor

Conventional
DRAMa

·.:'~;

'----v----J
Program and
Data storage

..:I.:.:::I:!
..

I:'T--:i.~!:i.~ I:::::~
1111

::!!!:

: :~:

I
I
I
I
:

.....

::::i.

:I:1. . ..:1.::

:i:'.:1:
...

: : : : : : :::::

:1: .:.

.. ...

=:i
Control

ff~:~ .- "c~g
Control

Control

I
---1-II
~
I t~...l.

:I &$
!::::

L ___________________ ~--J

Figure 1-1. System Block Diagram

1-4

Frame Buffer

=: - :~-,.c..!. .

CRT
Monitor

Introduction - Architectural Overview

1.3.1 TMS34010 Block Diagram
Figure 1 -2 illustrates the internal architecture of the TMS3401 0; the following
subsections describe the individual blocks shown in Figure 1-2.

Ir----------------------------------,
VO R.gllters
Ext.mll
Int.rrupt
R.queBta

Instruction
Cach.

Interrupt

IlIIIruotlon

Decod.

R.gIat....

Reset
Host
Interfac.
R.gIat....

Host
Int.rface
Bus

---:"1
Program
Count.r

VIdeo Timing

$ync and
Blanking

R.gIat....

statue R.glst.r
ALU

Mlcroccntrol
ROM

Barrel Shifter
Register Fli. A
Locll M.mory
Contrcl

R.gIst.r FII. B

R.gIIt....

stack Pclnt.r
Clock
Int.mII Clock
Circuitry

Outputs

Clock
Inputs

Lccll M.mory
Interfac. Bus

Figure 1-2. Internal Architecture Block Diagram

1.3.1.1 CPU Internal Functions
The center portion of Figure 1 -2 highlights the main internal functions of the
TMS34010:
•

The 32-bit program counter (PC) points to the next instruction word
to be fetched. The PC's four LSBs are always O. Section 5.3 (page
5-18) discusses the program counter.

•

The 32-bit status register (ST) specifies the status of the TMS3401 0
processor. It contains the sign, carry, zero, overflow, interrupt enable,
and PixBlt execution status bits. It also specifies the lengths and field
extension modes of fields 0 and 1. Section 5.2 (page 5-17) discusses
the status register.
1-5

Introduction - Architectural Overview

•

Register files A and B each contain 15 general-purpose registers,
Ao-A14 and Bo-B14, respectively. The B-file registers are also used as
implied operands for the graphics instructions. Section 5.1 (page 5-2)
discusses the register files.
The general-purpose register files are dual ported to support parallel data
movement. Two separate internal buses route data from the registers to
the ALU, and a third bus routes results back to the registers.

•

The stack pointer, or SP, is available to instructions that operate on
either register file.

•

The 32-bit barrel shifter shifts or rotates 32-bit operands from 1 to
32 bit positions in a single machine state.

•

The 32-bit ALU is connected to the other CPU components by 32-bit
data paths. This allows most register-to-register operations to be performed in a single machine state. (Accessing external memory requires
a minimum of two states.) The following actions occur in parallel during
a single state:

2)
3)

Two operands are transferred from the selected general-purpose
register file to the ALU.
The ALU performs the specified operation on the operands.
The result is routed back to the general-purpose register file.

1.3.1.2 Instruction Cache
The TMS3401 0 contains a 256-byte instruction cache that can contain up to
128 instruction words (an instruction word may be an entire single-word instruction or 16 bits of a multiple-word instruction). Section 5.4 (page 5-19)
describes instruction cache operation.

1.3.1.3 I/O Registers
Twenty-eight 16-bit, on-chip I/O registers are dedicated to peripheral control
functions. The I/O registers are divided into four categories:
•

Seven local memory interface registers are dedicated to memory
interface control and configure the memory controller.

•

Fourteen video timing and screen refresh registers generate the
sync and blanking signals used to drive a CRT, and schedule screenrefresh cycles.

•

Five host interface registers are accessible to external host processors as well as to the TMS34010. Status information can be communicated directly through these registers.
Large blocks of data in
TMS34010 memory can be accessed indirectly through pointer registers.

•

Two interrupt control registers provide status information about
.interrupt requests.

Section 6 provides individual descriptions of each I/O register.
1-6

Introduction - Architectural Overview

7.3.7.4 Microcontrol ROM
The TMS34010 transfers decoded instructions to the microcontrol ROM for
interpretation. The microcontrol ROM has 166 control outputs and 808 microstates.

1.3.1.5 Clock Timing Logic
The clock timing logic converts the clock input signals to internal timing signals and generates the clock output signals, LCLK1 and LCLK2, used by external devices. The machine state is a fundamental time unit of the graphics
processor in the TMS3401 0; it is the time interval during which the processor
is in a particular microinstruction state. The instruction timing for each assembly language instruction is specified in multiples of machine states. The
TMS34010's machine state is a single local clock period (the time from one
LCLK1 low-to-high transition to the next) in duration.

1.3.2 Other Special Processing Hardware
The TMS3401 0 CPU also supports the following special processing functions
in hardware:
•
•
•

Detecting whether a pixel lies within a specified display window
Detecting the leftmost one in a 32-bit register
Expanding a black-and-white pattern to a variable pixel-depth pattern

1-7

Introduction - Typical Applications

1.4 Typical Applications
The TMS34010's 32-bit processing power and its ability to handle complex
data structures make it well suited for a variety of applications. These include
display systems, imaging systems, mass storage, communications, high-speed
controllers, and peripheral processing. The TMS3401 O's efficient bit manipulation facilitates demanding tasks such as high-quality, proportionallyspaced text; this capability makes it especially useful in applications such as
desktop publishing. In graphics display systems, the TMS34010 provides
cost-effective performance for color or black-and-white bit-mapped displays.
Table 1 -1 lists typical end uses of the TMS3401 O.

Table 1-1. Typical Applications of the TMS34010
Computers
- Terminals and CRTs
- Windowing systems
- Electronic publishing
- Laser printers
- Personal computers
- Printers and plotters
- Engineering workstations
- Copiers
- Document readers

- FAX
-

Imaging
Data processing

Industrial Control
-

Telecommunications
- Video phones

- PBX
Consumer Electronics
- Automotive displays
- Information terminals
- Cable TV
- Home control
- Video games

1-8

Robotics
Process control
Instrumentation
Motor control
Navigation

Introduction - Manual Organization

1.5 Manual Organization
The TMS34010 User's Guide describes TMS3401 0 operation, focusing on the
TMS34010's role in applications that involve CRT -based, bit-mapped, graphics systems. The user's guide is divided into four major sections:
1)
2)
3)
4)

General information (Section 1 )
Architecture (Sections 2-8)
Timing (Sections 9-11)
Instruction set (Sections 7, 12, and 13)

A glossary, an index, and a reference card are also provided.

Section 1

Introduction
Provides an overview of the TMS3401 0 and TMS3401 0 architecture, including key features, a block diagram, and typical applications. Discusses manual
organization and lists suggested reading.

Section 2

Pin Functions
Illustrates the TMS3401 0 pinout and contains general pin descriptions. Also
describes specific pin functions regarding the host interface, the local bus interface, video timing signals, hold and emulator interface pins, and power,
ground, and reset pins.

Section 3

Memory Organization
Discusses 32-bit addressing methods, the TMS3401 0 memory map, and the
stack.

Section 4

Hardware-Supported Data Structures
Discusses hardware-supported data structures (such as fields and pixels) and
XY addressing.

Section 5

CPU Registers and Instruction Cache
Describes general-purpose register files A and B (including a reference of the
B registers' graphics functions), the status register, the program counter, and
the instruction cache.

Section 6

I/O Registers
Provides a detailed discussion of host interface registers, memory-interface
control registers, video timing and screen refresh registers, interrupt interface
registers, and I/O register addressing. Includes an alphabetical reference of
the I/O registers.

Section 7

Graphics Operations
Discusses graphics instructions such as PixBlts, PIXTs, and related topics such
as 2-dimensional arrays of pixels, window checking, XY-to-linear conversion,
and plane masking.

Section 8

Interrupts, Traps, and Reset
Describes external and internal interrupts, interrupt processing, and reset.
1-9

Introduction - Manual Organization

Section 9

Screen Refresh and Video Timing
Describes the horizontal sync, vertical sync, and blanking signals, horizontal
and vertical timing, and video RAM control.

Section 10

Host Interface Bus
Discusses host interface pins, registers, and timing.

Section 11

Local Memory Interface Bus
Discusses local memory interface timing, addressing mechanisms, and data
manipulation at the local memory interface.

Section 12 Assembly Language Instruction Set
Discusses addressing modes, summarizes MOVE, PIXBlT, and PIXT instruction variations, and presents the entire TMS34010 assembly language
instruction set in alphabetical order.

Section 13

Instruction Timings
Contains an overview of timing for general instructions, and specific timing
information for move and graphics instructions.

Appendix A TMS34010 Data Sheet
Appendix B Emulation Guidelines for Prototyping
Appendix C Software Compatibility with Future GSPs
Appendix D Glossary

1-10

Introduction - Related Documentation, References, and Suggested Reading

1.6 Related Documentation, References, and Suggested Reading
The following books and articles provide further background in graphics and
system concepts associated with graphics.
Artwick, Bruce A. Applied Concepts in Microcomputer Graphics. Englewood
Cliffs, New Jersey: Prentice-Hall, 1984.
Asal, Short, Preston, Simpson, Roskell, and Guttag. "The Texas Instruments
34010 Graphics System Processor." IEEE Computer Graphics and Applications voL6 no.10, pp. 24-39.
Bresenham, J.E. "Algorithm for Computer Control of a Digital Plotter." IBM
Systems Journal 4 No.1 (1965): 25-30.
Bresenham, J.E. "A Linear Algorithm for Incremental Display of Digital Arcs."
Communications of the ACM 20 (Feb. 1977): 100-106.
Cody, William J. Jr., and William Waite. Software Manual for the Elementary
Functions. Englewood Cliffs, New Jersey: Prentice- Hall, 1980.
Foley, James, and Andries van Dam. Fundamentals of Interactive Computer
Graphics. Reading, Massachussetts: Addison-Wesley, 1982.
Gupta, Satish. "Architectures and Algorithms for Parallel Updates of Raster
Scan Displays." Tech. Report CMU-CS-82-111, Computer Science Dept.,
Carnegie Mellon University, 1981.
Ingalls, D.H. "The Smalltalk Graphics KerneL" Special issue on Smalltalk,
Byte, August 1981, pp. 168-194.
Kernighan, B., and D. Ritchie The "C" Programming Language. Englewood
Cliffs, New Jersey: Prentice- Hall, 1978.
Killebrew, C.R. Jr., "The TMS3401 0 Graphics System Processor." BYTE, December 1986, pp. 193-204.
Kochan, Stephen G. Programming in C. Hasbrouck Heights, New Jersey:
Hayden Book Company, 1983.
Newman, W.M., and R.F. Sproull. Principles of Interactive Computer
Graphics. 2nd ed. New York: McGraw- Hill, 1979.
Pike, Rob. "Graphics in Overlapping Bitmap Layers." ACM Transactions On
Graphics 2 (April 1983): 135-160.
Pinkham, R., M. Novak, and K. Guttag. "Video RAM Excels at Fast Graphics."
Electronic Design, August 18, 1983, pp. 161-168.
Pitteway, M.L.V. "Algorithm for Drawing Ellipses or Hyperbolae with a Digital
Plotter." Computer Journal 10 (November 1967): 24-35.
Porter, T. and T. Duff. "Composing Digital Images." Computer Graphics, July
1 984, pp. 253-259.
Sproull, R.F. and I.E. Sutherland. "A Clipping Divider." Fall Joint Computer
Conference Washington, DC: Thompson Books, 1968.
1-11

Introduction - Related Documentation, References, and Suggested Reading

Van Aken, Jerry R. nAn Efficient Ellipse- Drawing Algorithm. n IEEE Computer
Graphics & Applications 4 (Sept. 1984): 24-35.
Wientjes, Guttag, and Roskell. "First Graphics Processor Takes Complex Orders to Run Bit-Mapped Displays." Electronic Design Vol. 34, No.2
(January 23, 1986): 73-80.
The following TMS34010 documents are available from Texas Instruments.
To obtain a copy of any of the TI documents listed below, please call the Texas
Instruments Customer Response Center (CRC) at 1-800-232-3200.

1-12

•

The TMS34010 Application Guide (literature number SPVA007) is a
collection of individual application reports. Each application report discusses a specific TMS34010 application; for example, using a
TMS34010 in a 512 x 512-pixel minimum-chip system, designing
TMS34010-based systems that are compatible with various graphics
standards, and interfacing the TMS3401 0 to a variety of host processors.

•

The TMS34010 Assembly Language Tools User's Guide (literature
number SPVU004) tells you how to use the TMS34010 assembler,
linker, archiver, object format converter, and simulator.

•

The TMS34010 C Compiler User's Guide (literature number
SPVU005) tells you how to use the TMS34010 C compiler. This C
compiler accepts standard Kernighan and Ritchie C source code and
produces TMS3401 0 assembly language source code. We suggest that
you use The C Programming Language (written by Brian W. Kernighan
and Dennis M. Ritchie, published by Prentice-Hall) as a companion to
the TMS34010 C Compiler Usels Guide.

•

The TMS34010 Math/Graphics Function Library User's Guide
(literature number SPVS006) describes a collection of mathematics and
graphics functions that can be called from C programs.

•

The TMS34010 Software Development Board User's Guide (literature number SPVU002) describes using the TMS3401 0 software development board (a high-performance, PC-based graphics card) for
testing and developing TMS3401 O-based graphics systems.

•

The TMS34010 Software Development Board Schematics (literature number SPVU003) is a companion to the TMS34010 Software
Development Board Usels Guide.

•

The TMS34010 Font Library User's Guide (literature number
SPVU007) describes a set of fonts that are available for use in a
TMS3401 O-based graphics system.

Section 2

Pin Functions

This section discusses the TMS34010 pin functions. Section 2.1 contains a
TMS34010 pinout, summarizes the pin functions, and categorizes the signals
by function; Section 2.2 through Section 2.6 describe the functional categories.
Topics in this section include:

Section
Page
2.1 Pinout and Pin Descriptions .................................................................... 2-2
2.2 Host Interface Bus Signals ....................................................................... 2-5
2.3 Local Memory Interface Signals .............................................................. 2-7
2.4 Video Timing Signals ................................................................................ 2-9
2.5 Hold and Emulator Interface Signals .................................................... 2-10
2.6 Power, Ground, and Reset Signals ....................................................... 2-11

2-1

Pin Functions - Pinout and Pin Descriptions

2.1

Pinout and Pin Descriptions
The TMS34010 is packaged as a 68-pin plastic leaded chip carrier (PLCC).
Figure 2-1 shows a pinout of the TMS3401 0 processor, and Table 2-1 summarizes the pin functions at each interface. Appendix A contains mechanical
information.

9 8 7 6 5 4 3 2 1 6867666564636261

44
V~~~~~~~~~~~~~~Qa

U~ lUlU I~ 1« 1-'« V) ~ 12 IV) IV) I~.020
IWI~ >
U~~222~
N

V)~w««

>dd»«~-'>oo~u
-,-,~~al~

I~~~
~
J:

Figure 2-1. TMS34010 Pinout (Top View)

As Figure 2-2 shows, the TMS3401 O's 68 pins are divided among several interfaces:
25
29
4
3
7

Host interface
Local memory interface
Video timing interface
Hold and emulator interfaces
Power and reset
Total:

2-2

pins
pins
pins
pins
pins

68 pins

Pin Functions - Pinout and Pin Descriptions

<>,br:illl'>"i
"

HDO-HD15

•

, "Z>!;¥1JI HFSo-HFS1

Host Interface

~
~

fIW

'mIaE

~
~

{

VCLI<

";'

Power, Ground
end Raeet

VCC

{

DDOJ:i

Ram

Video Timing

L.ADO-I.AD15

Vee

REm'

LooII Memory
Interface

LRDY

IJiili'1-DA'F2
LCLK1
LCL.K2
INCLI<

FmJ:D

Holclend
Emulator
} Interfaoae

Figure 2-2. TMS34010 Major Interfaces

Table 2-1. Pin Descriptions
Host Interface Bus Pins

Name

I/O

HDo-HD15

44-51,53-60

I/O

HFSO,HFS1

67,68

Host function select

'F!TIiIT

Host interrupt request

Host lower data select

Host upper data select

HRDY

Host ready

R"R'EAI5

Host read strobe

"RWR'ITE

Host write strobe

Description
Host chip select
Host bidirectional data bus

2-3

Pin Functions - Pinout and Pin Descriptions

Table 2-1. Pin Descriptions (Concluded)
Locsl Interlsce Bus Pins

Name

Description

DDOUT

I/O
0
0
0
0

10-17.19-26

I/O

0
0

Local address latched

Local interrupt request pins

Local ready

TR"/rrE

Local shift-register transfer or output enable

0
0

INCLK

Input clock

LADo-LAD15

tAr
LCLK1.LCLK2
mlT1.mlT2
LRDY

28.29
6,7

Local row-address strobe
Local column-address strobe
Local data direction out
Local data enable
Local address/data bus
Local output clocks

Local write strobe

Hold and Emu/stion

Name
'FfITL[)

Description

I/O

Hold request

RUN/mD'

Run/Emulate

Jm)A/muA'

Hold acknowledge or emulate acknowledge

Video Timing Signsls

Name

mvNe

VCLK

Description

I/O
0

Blanking

I/O
I

Video clock

Horizontal sync

Vertical sync
I/O
Power, Ground, and Reset Signsls

I/O

Vee

27,61

Nominal 5-volt power supply

Vss

1,18,35,52

Ground

Name
~

2-4

'IITANT{

Description
Device reset

Pin Functions - Host Interface Bus Signals

2.2 Host Interface Bus Signals
The host interface pins are used for communication between the TMS3401 0
and a host processor. Signals output on these pins are assumed to be asynchronous With respect to local clocks LCLK1 and LCLK2. To software running
on a host processor, the TMS3401 O's host interface appears as a peripheral
device containing a block of four 16-bit registers. Table 2-2 describes the
host interface pins. Section 6 describes the host interface registers, and Section 10 discusses host interface operation.

Table 2-2. Host Interface Signals
I/O

Description

Host Chip Select. ~ is driven active low to enable access to the 16-bit host
interface register that is selected by HFSO and HFS1. During the low-to-high
transition of "REm, the level on the ~ input determines whether the
TMS34010 is halted (if ~ is high), or begins immediately executing its reset
service routine (if ~ is low). In the second case, the ~ and ~ pins
may be tied directly together.

HFSO, HFS1

Host Function Select. HFSO and HFS1 determine which of the four 16-bit
host interface registers is selected during a read or write cycle that is initiated
by the host processor.

Signal

HFS1 HFSO
0
0
1
0
0
1
1
1

Description
LSBs of pointer address
MSBs of pointer address
Data buffer register
Control register

HREAD

Host Read Strobe. HREAD is driven active low during a read cycle that is
initiated by the host processor. This enables the contents of the selected host
interface register to be output on H Oo-H 015. "RREAD should not be active low
at the same time that HWmTE is active low.

HWR1'ir

Host Write Strobe. HWRTiE" is driven active low during a write cycle that is
initiated by the host processor. This enables the contents of H Oo-H 015 to be
written to the selected host interface register. HWRITE should not be active low
at the same time that Fi1ITAJ) is active low.

HLDS

Host Lower Data Select. HLDS is driven active low during a read or write
cycle that is initiated by the host. This enables the lower byte (bits 0-7) of the
selected host interface register to be accessed.

"RUi5S

Host Upper Data Select. "RUi5S is driven active low during a read or write
cycle that is initiated by the host processor. This enables the upper byte (bits
8-15) of the selected host interface register to be accessed.

In systems that do not use the host interface, it may be desirable to pull these inputs up to the +VCC
level.

2-5

Pin Functions - Host Interface Bus Signals

Table 2-2. Host Interface Signals (Concluded)
Signal

I/O

Description

HRDY

Host Ready. H RDY indicates when the TMS3401 0 is ready to complete a read
or write cycle that is initiated by the host. Except during an access of a host
interface register, HRDY is always high. HRDY is driven low if the host processor attempts to initiate an access of a host interface register before the
TMS34010 has had sufficient time to complete all processing resulting from an
access initiated previously by the host. HRDY always goes low briefly at the
start of a HSTCTL register access. When HRDY is driven low, the host must
wait to complete the access until HROY is again driven high. While HCS is high,
HRDY is driven high.

HiNT

Host Interrupt Request. HINT follows the INTOUT bit in the HSTCTL register; it is typically used to transmit interrupt requests from the TMS3401 0 to the
host processor. When INTOUT is set to 1 by the TMS34010, 'HTIiiT is driven
active low. 'HTIiIT remains active low until the host writes a 0 to INTOUT, at
which time HTRT becomes inactive high.

I/O

Host Bidirectional Data Bus. The host data pins, HOo-HD15, form a bidirectional 16-bit bus which is used to transfer data between the selected 16-bit
host interface register and the host processor. H DO is the LSB and H 015 is the
MSB.

HDo-HD15

2-6

Pin Functions - Local Memory Interface Signals

2.3 Local Memory Interface Signals
The TMS3401 0 uses the local bus interface pins to communicate with external
memory and with memory-mapped I/O devices. The signals at this interface
are used directly to control DRAMs (dynamic RAMs) and VRAMs (video
RAMs). Section 11 discusses local memory interface operation.

Table 2-3. Local Bus Interface Signals
I/O

Description

DEN

Signal

Local Data Enable. DEN is an active-low output; it drives the active-low
output-enable inputs on the bidirectional transceivers (such as the
74ALS245) which are used to buffer data input and output on the
LADO-LAD15 pins. External buffering may be required on the LADQ-LAD15
pins when the TMS34010 is interfaced to a large number of local memory
devices.

DDOUT

Local Data Direction Out. DDOUT drives the direction control inputs on
the bidirectional transceivers (such as the 74ALS245) which are used to buffer data input and output on the LADQ-LAD15 pins. External buffering may
be required on the LADQ-LAD15 pins when the TMS3401 0 is interfaced to a
large number of local memory devices. During write cycles, DDOUT is driven
high to enable data to be output from the LADQ-LAD15 pins while D'EN is
driven active low. During read cycles, DDOUT goes low to enable data to be
input to the LADQ-LAD15 pins while tfm' is driven active low. At all other
times, DDOUT remains driven to the default high level.

IA[

Local Address Latched. An external latch can use the high-to-Iow transition of IAr to capture the column address from the LADQ-LAD15 pins. When
a transparent latch such as a 74ALS373 is used, the address remains latched
as long as IAr remains active low.

Local Row Address Strobe.
DRAMs and VRAMs.

Local Column Address Strobe. The ~ output drives the ~ inputs of
DRAMs and VRAMs.

Local Write Strobe. The active-low 'Ii output drives the 'Ii inputs of
DRAMs and VRAMs. Vi can also be used as the active-low write enable to
static memories and other devices connected to the TMS3401 0 local interface.
During a local memory read cycle, 'Ii remains inactive high while ~ is
strobed active low. During a local memory write cycle, Vi is strobed active low
while ~ is low. During shift-register-transfer cycles, the state of Vi indicates
whether the transfer is from shift register to memory (Vi is low) or memory to
shift register ('Ii is high). At all other times, 'Ii lis driven to the default high
,
level.

iiVOl:

Local Shift Register Transfer or Output Enable. This pin connects directly to a VRAM's 'm/CE (or t5T/m) pin. During local memory read cycles,
the 'm/m pin functions as an active-low output enable to gate data from
memory to the LADQ-LAD15 pins. During VRAM shift-register-transfer cycles, iA'/tre' is driven active low during the high-to-10w transition of'RAS'.

INCLK

Input Clock. INCLK is the input clock used to generate the LCLK1 and
LCLK2 outputs, to which all processor functions in the TMS34010 are synchronous. A separate input clock, VCLK, controls the video timing registers.

The 'RAS' output drives the 'RAS inputs of

2-7

Pin Functions - Local Memory Interface Signals

Table 2-3. Local Bus Interface Signals (Concluded)
Signal

I/O

Description

LCLK1, LCLK2

Local Output Clocks. These two output clocks, 90 degrees out of phase with
each other, provide convenient synchronous control of external circuitry to the
TMS34010's internal timing. All clocked signals output from the TMS34010,
with the exception of the CRT timing signals, are synchronous to these clocks.

LRDY

Local Ready.
LRDY is driven low by external circuitry to inhibit the
TMS34010 from completing a local memory cycle it has initiated. While LRDY
remains low, the TMS34010 continues to wait. When LR DY is again driven
high, the TMS34010 completes the cycle. While LRDY is low, the TMS34010
generates internal wait states in increments of one full LCLK1 cycle in duration.
LRDY can be driven low to extend local memory read and write cycles, shiftregister-transfer cycles, and DRAM refresh cycles. During internal cycles, the
TMS34010 ignores LRDY.

mrr1,IiNT2

Local Interrupt Request Pins. I nterrupt requests from external devices are
transmitted to the TMS3401 0 on the UNi1 and LlNT2 pins. Each pin activates
the request for one of two external interrupt request levels. An external device
generates an interrupt request by driving the appropriate interrupt request pin
to its active-low state. The pin should remain active low until the TMS34010
has recognized the request.
Transitions on the two interrupt request pins are assumed to be asynchronous
with respect to local clocks LCLKl and LCLK2; the signals on these pins are
synchronized internally before being used internally.

LADD-LAD15

I/O

Local Address/Data Bus.
LADD-LAD15 form the local multiplexed
address/data bus. At the start of a memory cycle, two addresses (row and column) are output on LADD-LAD15. During a read cycle, data are input on
LADD-LAD15 during the latter part of the cycle. During a write cycle, data are
output on LADD-LAD15 during the latter part of the cycle. LADO is the LSB,
and LAD15 is the MSB. During the time the row address is output on
LADD-LAD14, status bit RF is output on LAD15. RF is active low at the start
of a DRAM-refresh cycle (either RAS-only or CAS-before-RAS). During the time
that the column address is output on LADD-LAD13, status bits TR and lAO are
output on LAD15 and LAD14, respectively. lAO is active high during a read
cycle in which the TMS34010 fetches an instruction word from the local memory. During all other cycles, lAO is inactive low. m is active low during
shift-register-transfer cycles. (The level output on LAD14 during the highto-low transition of CAS is always the same as the level output on iFi/ITE during
the high-to-Iow transition of RAS.)

Notes: 1) The system designer must ensure that LR DY is not held low for so long that the TMS3401 0
is prevented from performing the necessary number of DRAM refresh cycles or is prevented
from refreshing the display by performing a VRAM memory-to-shift-register cycle during
horizontal retrace.
2) The operation of UNi1 and LlNT2 is affected by the RUN/EMU pin. Make sure this pin is in
the proper state.

2-8

Pin Functions - Video Timing Signals

2.4 Video Timing Signals
The video timing signals (BLANK, HSYNC, and VSYNC) control the horizontal
and vertical sweep rates of the video monitor. They also synchronize the display on the monitor to video data that is output from the VRAMs. Section 9
discusses video timing and screen refresh operations.

Table 2-4. Video Timing Signals
Signal

I/O

Description

I/O

Horizontal Sync. ~ is the horizontal sync signal used to control external
video circuitry. It is programmed as either an input or an output by means of
two control bits in the DPYCTL register. When configured as an output. the
active-low horizontal sync signal is generated by the TMS3401 O's on-chip video timers. When configured as an input, the TMS3401 0 synchronizes its video
timers to externally-generated horizontal sync pulses. Immediately following
reset, ~ is configured as an input.

I/O

Vertical Sync. ~ is the vertical sync signal used to control external video
circuitry. It is programmed as either an input or an output by means of a control
bit in the DPYCTL register. When configured as an output, the active-low vertical sync signal is generated by the TMS3401 O's on-chip video timers. When
configured as an input, the TMS34010 synchronizes its video timers to externally-generated vertical sync pulses. Immediately following reset, 'iJS'Y'lijl!" is
configured as an input.

'lITANK

Blanking. "!iIAiII1( is a composite blanking signal used to turn off the electron
beam of a CRT during both horizontal and vertical retrace intervals. This signal
may also be used to control the starting and stopping of the VRAM shift registers.

VCLK

Video Clock. VCLK is derived from the dot clock of the external video system
and is used internally to drive the TMS3401 O's video timing logic. The signals
output at the BLANK, HSYNC, and ~ pins are synchronous to VCLK. VCLK
is not required to have any timing relationship with respect to INCLK; that is,
VCLK and INCLK can be asynchronous. In order to read HCOUNT and
VCOUNT registers reliably, VCLK should be held high during the read. In systems which do not use the video timing reg'isters or require automatic screen
refreshing, VCLK can be strapped high.

Note: The operation of HSYNC and 'i7S"'?'N"E
proper state.

affected by the RUN/EMU pin. Make sure thiS pin

IS In

the

2-9

Pin Functions - Hold and Emulator Interface Signals

2.5 Hold and Emulator Interface Signals
The TMS3401 0 hold interface permits other devices to request and be granted
control of the local interface bus.
The emulator interface is used to control the TMS34010 when it is used for
emulation. The RUN/mu pin may remain unconnected in nonemulation applications.

Table 2-5. Hold and Emulator Interface Signals
Signal

HLDA/EMUA

I/O

Description

Hold Request. The"R"U"CIT pin is driven active low by an external device to
signal a request that the TMS3401 0 release ownership of the local memory bus.
Once the TMS3401 0 has acknowledged the hold request via a hold acknowledge signal, the external device assumes ownership of the bus. The device must
continue to assert its hold request until it has released the bus.

Hold Acknowledge and Emulate Acknowledge. The HLDA/EMUA pin is
multiplexed between two functions: (1) acknowledgment of hold requests and
(2) acknowledgment of emulation requests.
The hold acknowledge signal (FrrnA) is output during phases Q3 and Q4 of the
local clock cycle. The emulate acknowledge signal (El'irnA) is output during
phases Q1 and Q2. RIl5A is driven active low in response to a hold request from
an external device, but not until the TMS34010 has released the bus to the requesting device. The device must delay taking possession of the bus until it
has received an active "H"Il5A signal. Once an active-low hold acknowledge
signal has been transmitted during Q3-Q4. it will continue to be transmitted
during Q3-Q4 of each local clock period until the external device ceases to assert its hold request.

E1iiiD"A is driven active low to indicate to external circuitry that the TMS34010

has halted in response to an mu command input on the RUN/EMU pin.
HLDA/EMUA is also driven low when an EMU opcode is executed by the
TMS34010. but only during phases Q1 and Q2 of a single LCLK1 cycle. Execution of an EMU opcode causes an active-low signal to be output at the
RIl5A/muA pin during phases Q1 and Q2. so external devices that generate
hold requests should avoid interpreting these signals as hold acknowledgment.

RUN/mIT

Run/Emulate. This pin is defined as a no-connect during normal system operation. The RUN/EMU pin should not be pulled low except during factor
testing or chip emulation. An internal pull-up load permits RUN/EMU to remain
unconnected during normal use.
If RUN/mIT is pulled low. "R!m. iJliJT1. iJliJT2. ~, and ~ are reconfigured to perform special functions used only during emulation and factory
testing.

2-10

Pin Functions - Power, Ground, and Reset Signals

2.6 Power, Ground, and Reset Signals
Six TMS34010 pins are dedicated to ground and power supply.
provides more details about RESET.

Section 8

Table 2-6. Power, Ground, and Reset Signals
Signal

I/O

Description

Vee

Vee (2 pins). Two +5-volt power supply inputs.

VSS

VSS (4 pins). Four electrical ground inputs.

i'ITSE'f

Reset. RESET is pulled low to reset the device during normal operation.
While RESET is asserted low, the internal registers of the TMS3401 0 are set
to an initial known state, and all output and bidirectional pins are driven either to inactive levels or to high impedance. The behavior of the TMS3401 0
chip following reset depends on the level of the m:;s input just prior to the
low-to-high transition of RESET. If m:;s is low, the TMS3401 0 begins executing the instructions pointed to by the reset vector. If m:;s is high, the
TMS34010 is halted until a host processor writes a 0 to the HLT bit in the
HSTCTL register.
Transitions on the i'ITSE'f pin are assumed to be asynchronous with respect
to local clocks LCLK1 and LCLK2; the signal input on this pin is synchronized internally before it is used internally.

2-11

Pin Functions

2-12

Section 3

Memory Organization

This section presents details of physical and logical addresses, illustrates the
TMS34010 memory map, and describes stack operation.

Section
Page
3.1 Memory Addressing .................................................................................. 3-2
3.2 Memory Map .............................................................................................. 3-4
3.3 Stacks .......................................................................................................... 3-6

3-1

Memory Organization - Memory Addressing

3.1

Memory Addressing
The TMS34010 is a bit-addressable machine with a 32-bit internal memory
address. The total memory capacity is four gigabits (or 512 megabytes); the
TMS34010 supports external addressing of 128 megabytes.
Memory is accessed as a continuously addressable string of bits. Each 32-bit
address points to an individual bit within memory. Groups of adjacent bits
form data structures called fields. A field is specified by its starting bit address and its length. The TMS3401 0 supports field lengths from 1 to 32 bits.
Bit addresses range from OOOOOOOOh to OFFFFFFFFh.
Figure 3-1 illustrates the logical memory structure.
32-81t

Logical Address

Memory

Figure 3-1. logical Memory Address Space

Figure 3-2 illustrates physical memory organization. The TMS34010 communicates with memory over a 16-bit data bus, and always reads or writes a
complete 16-bit word from or to memory. A word accessed during a memory
cycle always begins on an even 16-bit boundary; thus, the four LSBs of the
32-bit starting address of the word are Os. Bits within a word are numbered
from 0 to 15; bit 15 is the MSB and bit 0 is the LSB. A word is identified by
the address of its LSB. In this document, the LSB of a memory word is depicted as the rightmost bit in the word.

3-2

Memory Organization - Memory Addressing

32-81t Logical Addreae
2
MSBs I
31 30129

Memory

28-BIt
Physical Addreae
N

J LSBa
413

"--v---'

---.,.-....-

Not Used
Externally

Select BIt Soun dary
WIthin Word

Word N+1

Word N

Word N-1

15 14 13 12 11 10 9 8 7 8 5 4 3 2 1

I 1 1 1 1 1 1 1 1 I I I 1 1 1 1-'

MSB

LSB

Figure 3-2. Physical Memory Addressing

The four LSBs of the 32-bit logical address in Figure 3-2 do not appear on the
local memory bus. When the TMS3401 0 extracts a data structure that does
not begin and end on even word boundaries, these four LSBs are used internally to indicate a bit boundary within an accessed word. Control logic at the
local memory interface automatically performs the bit alignment and masking
necessary to extract a data structure from physical memory; this is completely
transparent to software. If the data structure being extracted straddles word
boundaries, multiple read cycles are required. Similarly, inserting a data
structure into memory may require a series of read and write cycles, accompanied by the internal masking and shifting of data to properly align the data
structure within memory. The memory-control logic performs these tasks automatically.
The two MSBs of the 32-bit logical address are not output. The TMS3401 0
supports an external address range of 128 megabytes of physical memory.

3-3

Memory Organization - Memory Map

3.2 Memory Map
Figure 3-3 illustrates the TMS34010 memory map. Memory is logically organized as four gigabits, but is physically accessed 16 bits at a time. Locations
are shown as 16-bit words, identified by 32-bit addresses whose four LSBs
are Os. Word addresses range from OOOOOOOOh to FFFFFFFOh (bit address
OOOOOOOOh is the rightmost bit in the word at the bottom of Figure 3-3, and
bit address FFFFFFFFh is the leftmost bit in the word at the top.) Reading
or writing to an address in the range COOOOOOOh to C00001 FOh accesses an
internal I/O register. Reading or writing to any address outside this range
accesses off-chip memory (or a memory-mapped device) external to the
TMS34010.

Address

FFFF FFFO r-f""T"------..,r--..,

FFFF FCOO .,..,+,..,..,...."r'7'~,...,...,..,
FFFF FBFO
FFFF EOOO
FFFF DFFO

"""''''''""''''''''''""''''''''''""'''''''''''"''1

COOO 2000 .,..,....rr-r'7'"7~r-r.,...."..,...
COOO 1FFO
COOO0200
COOO 01FO I"'--~""'-''"'"''''''"''~'''"''Ir'''-'''
COOOOOOO
BFFF FFFO

t--+-----.....-f
3

2 28 words

Bit 0
(first bit in memory)

Figure 3-3. TMS34010 Memory Map

As Figure 3-3 shows, memory is divided into several regions:

•

General use
Addresses ranges Oh-BFFFFFFOh and C0002000h-FFFFDFFOh are for
general use (executable code, data tables, etc.).

•

I/O registers
Addresses COOOOOOOh-C00001 FOh are reserved for the 16-bit I/O registers. Section 6 discusses the I/O registers; it contains a map of this

3-4

Memory Organization - Memory Map

memory area which associates each I/O register with the appropriate
address.
•

Interrupt. Reset. and Trap Vectors
Addresses FFFFFCOOh-FFFFFFEOh are reserved for 32 interrupt, reset,
and trap vectors. A vector is a 32-bit address that points to the starting
location in memory of the appropriate interrupt, reset, or trap service
routine. Each address is stored in physical memory as two consecutive
16-bit words, with the 16 LSBs at the lower address. Section 8 contains
more information about interrupts and traps.

•

Reserved memory
Addresses C0000200h-C0001 FFOh are reserved for future expansion of
the I/O registers.
Addresses FFFFEOOOh-FFFFFBFOh are reserved for future expansion of
the interrupt vectors.

3-5

Memory Organization - Stacks

3.3 Stacks
The TMS3401 O's system stack is implemented in local memory and managed
in hardware. The stack is used to store return addresses and processor status
information during interrupts, traps, and subroutine calls. The contents of
general-purpose registers can be pushed onto the stack and popped off the
stack. The system stack can also be used for dynamically allocated data storage.
The stack is accessed through a dedicated 32-bit internal register, called the
stack pointer, or SP. The SP points to the top of the system stack; it can be
accessed as register 15 in either register file.
In addition to the system stack, you can define your own auxiliary stacks. The
system stack always grows toward lower memory addresses; an auxiliary stack
can be defined to grow toward either lower or higher addresses. The MOVE
and MOVB instructions, combined with the automatic predecrement and
postincrement addressing modes, facilitate pushing and popping auxiliary
stack data. One or more registers in the A or B files can be used by software
as auxiliary stack pointers and frame pointers. The indexed addressing modes
can be used in conjunction with a frame pointer to access variables embedded
within the stack.

3.3.1

System Stack
Figure 3-4 shows the structure of the system stack, which grows in the direction of lower memory addresses.
The SP points to the top of the stack; it contains the 32-bit address of the LSB
(bit 0) of the value on top of the stack. The SP can contain any 32-bit address; however, stack operations execute more efficiently when the four LSBs
of the SP are Os. This aligns the SP to word boundaries in memory, reducing
the number of memory cycles necessary to push values onto the stack or pop
values off the stack.
Any instruction that manipulates general-purpose registers (Ao-A14 or
Bo-B14) can also be used to manipulate the SP. The SP can be specified as
the source or destination operand in any instruction that operates on the
general-purpose registers. Instructions that manipulate the SP include:

Instructions that Push
Values on the Stack
MMTM SP, register list
CALL Rs
CALLA absolute address
CALLR relative address
TRAP number
PUSHST
MOVE Rs, -*SP

3-6

Instructions that Pop
Values from the Stack
MMFM SP, register list
RETI
RETS
POPST
MOVE *SP+, Rd

Memory Organization - Stacks

Memory

,-----''''---""\
Highest Address

stack Bottom

Lowest Address

Figure 3-4. System Stack

3.3.1.1 Saving Registers on the System Stack
Register information can be stored on the stack during an interrupt or a subroutine call. This frees up the register for use by an interrupt routine or a subroutine, and allows you to restore the original register values from the stack
when the routine finishes executing.
During an interrupt, the contents of the PC and ST are automatically saved
on the stack; if you want to save values that are in general-purpose registers,
you can use the MMTM and MMFM instructions. MMTM pushes multiple
general-purpose registers onto the stack, and MMFM pops multiple general-purpose registers from the stack.
When the contents of a 32-bit register are pushed onto the stack, they are
stored in two consecutive 16-bit words. The 16 MSBs are stored at the higher
memory address, and the 16 LSBs are stored at the lower address. This is
shown in Figure 3-5, which demonstrates the effects of the following instruction sequence:
MMTM SP, AD
MMFM SP, Al

Push register AD onto stack
Pop stack into register Al

3-7

Memory Organization - Stacks

•
•
•

Figure 3-5 a shows the original state of the stack and registers.
Figure 3-5 b illustrates the state after AO is pushed onto the stack.
Figure 3-5 c shows the result of popping the top of the stack into A1.
General-Purpose
Register File A

Memory

lsi

r--"-----.
t ' - - - 16

--t

................
................
,................
.............. .
•••••••••••••••

Stack Bottom

r--"-----.
t'---32

---1

................
.........
, ..... .

.................
,'::..:::..:::::...
................
................

Lowest Address- --- :::::::::::::::. 0
General-Purpose
Register File A

Memory

r--"-----.
Ibl

t ' - - - 16

--t

................
.................
....... ..... . ..
................
................

r--"-----.
t'---32

---1

Stack Bottom _

................
................
................
................

Lowest Address - - ••••• ', •••• ',',', •••• ',',', ••••• 0

General~Purpose

Memory

lei

r--"-----.
t ' - - - 16

--t

r--"-----.
t ' - - - 32

--t

................
................
... , ........... .
................
................
................

Lowest Address - - - - . . : , ..
::.;..:.:.
.. .:.;
...:,:
...:,:
..:.;..':';".:.:.1" 0

Figure 3-5. Stack Operations
The TMS3401 0 performs two steps to push the contents of a 32-bit register
onto the top of the stack:
1)
2)

Decrement the PC by 32.
Push the register contents onto the stack.

The TMS3401 0 performs two steps to pop the top of stack into a 32-bit register:
1)
2)

3-8

Pop the 32 bits at the top of the stack into the register.
Increment the SP by 32.

Memory Organization - Stacks

3.3.1.2 Saving Information On the System Stack During an Interrupt
During an interrupt, the TMS3401 0 pushes the PC and ST onto the stack; this
allows the interrupted routine to resume execution when the interrupt processing is completed. An interrupt routine performs the following actions:
1)
2)
3)
4)

Decrement the SP by 32.
Push the PC onto the stack.
Decrement the SP again by 32.
Push the ST onto the stack.

During a return from an interrupt:
1)
2)
3)
4)

Pop the 32 bits at the top of the stack into the ST.
Increment the SP by 32.
Pop the 32 bits at the top of the stack into the PC.
Increment the SP again by 32.

3.3.1.3 Saving Information On the System Stack During a Subroutine Call
A subroutine call saves the state of the calling routine on the stack; this allows
the routine to resume execution when the subroutine completes. A subroutine
call performs the following actions:
1)
2)

Decrement the SP by 32.
Push the PC onto the stack.

During a return from a subroutine:
1)
2)

Pop the 32 bits at the top of the stack into the PC.
Increment the SP by 32.

3.3.2 Auxiliary Stacks
Auxiliary stacks can be managed in software. Any A- or B-file register, except
the SP, can be used as the auxiliary stack pointer. Auxiliary stacks are typically
used to contain dynamically allocated data storage.
In the following discussion, STK represents the auxiliary stack pointer. STK
is a symbol that must be equated to one of the general-purpose registers; for
example:
STK

.set

The STK may contain any 32-bit value; however, stack operations execute
more efficiently when the four LSBs of the STK are Os. This aligns the STK
to word boundaries in memory, reducing the number of memory cycles necessary to push values onto the stack or pop values off the stack.
As Figure 3-6 and Figure 3-7 show, the auxiliary stack can be configured to
grow in either direction in memory. The memory is shown in these figures as
a string of continuously addressable bits.
3-9

Memory Organization - Stacks

3.3.2.1 An Auxiliary Stack that Grows Toward Lower Addresses
Figure 3-6 shows a stack that grows toward lower memory addresses:
•

Figure 3-6 a shows the original stack.

•

In Figure 3-6 b, a field of arbitrary size is pushed onto the stack with this
instruction:
MOVE

Rs, * -STK

(Rs and STK represent general-purpose registers.)

•

In Figure 3-6

MOVE

*STK-,

the field is popped off the stack with this instruction:

(Rd and STK represent general-purpose registers.)
Between instructions, the STK always points to the lowest bit address in the
stack - this corresponds to the very top of the stack. You can use the M MTM
STK,register list instruction to save multiple registers on the stack in Figure
3-6. Later, you can restore the registers to their former values with an
M M FM STK,register list instruction.

Stack
II

(s)

+-~~:ress

Low~

Address

STI(

stack
II

(b)

Reid

I
T

STI(

Stack
II

(c)

STI(

Figure 3-6. An Auxiliary Stack that Grows Toward Lower
Addresses

3-10

Memory Organization - Stacks

3.3.2.2 An Auxiliary Stack that Grows Toward Higher Addresses
Figure 3-7 shows a stack that grows toward higher memory addresses:
•

Figure 3-7 a shows the original stack.

•

In Figure 3-7 b, a field of arbitrary size is pushed onto the stack using
the following instruction:
MOVE Rs, * STK+

•

In Figure 3-7

the field is popped off the stack with this instruction:

MOVE *-STK,

Between instructions, the STK always points to one plus the highest bit address in the stack - this location is one bit beyond the very top of the stack.
Stack

(a)

High

Addre!a:~

+-- Adclre....

STK

stack
(b)

STK

Stack

(0)

STK

Figure 3-7. An Auxiliary Stack that Grows Toward Higher
Addresses

3-11

Memory Organization

3-12

Section 4

Hardware-Supported Data Structures

The TMS3401 0 supports several data structures at the machine level:

•

Fields are configurable data structures whose length can be defined
within the range 1 to 32 bits. Two field sizes can be defined simultaneously. A field can begin and end at arbitrary bit addresses.

•

Bytes are a special case of field in which the field length is fixed at eight
bits and is sign extended. Bytes can begin on any bit boundary within
a word.

•

Pixels are configurable data structures; pixel length can be programmed
to be 1, 2, 4, 8, or 16 bits (always a power of two). Pixels are aligned
so that they do not cross word boundaries in memory.

•

Two-dimensional pixel arrays, or pixel blocks, are rectangular groups
of pixels that are manipulated using the PIXBLT (pixel block transfer)
and FILL (pixel block fill) instructions. A pixel array can be moved from
one area of memory to another in a single PixBlt operation. It can be
combined with another array of the same size by performing Boolean or
arithmetic operations on the corresponding pixels of the two arrays.

The number of bits in a pixel, field, or array is programmable, but byte length
is fixed. Two field sizes and one pixel size can be specified simultaneously.
The size and starting addresses of the pixel arrays that are manipulated during
a PixBlt operation are specified by the values loaded into dedicated hardware
registers.
Topics in this section include:

Section
Page
4.1 Fields ........................................................................................................... 4-2
4.2 Pixels ........................................................................................................... 4-6
4.3 XY Addressing ......................................................................................... 4-11
4.4 Pixel Arrays ............................................................................................... 4-15

4-1

Hardware-Supported Data Structures - Fields

4.1

Fields
The TMS34010 supports two software-configurable field types, field 0 and
field 1. A field in memory is defined by two parameters:
•
•

Starting address and
Field size (1 to 32 bits)

A field's starting address is the address of the field's LSB. A field can begin
at an arbitrary bit address in memory. When a field is moved from memory to
a general-purpose register, the field is right justified within the register; that
is, the field's LSB coincides with the register's rightmost bit (bit 0). The register bits to the left of the field are all 1 s or all Os, depending on the values of
both the appropriate FE (field extension) bit in the status register, and the sign
bit (MSB) of the field. If FE=1, the field is sign extended; if FE=O, the field
is zero extended.
Field size can range from 1 to 32 bits. The lengths of fields 0 and 1 are defined
by two 5-bit fields in the status register, FSO and FS1.
Figure 4-1 illustrates a field in memory. In this example, the field straddles the
boundary between words Nand N+ 1 in memory. Field extraction and insertion is performed by on-chip hardware:
•

To move the field to a general-purpose register, the TMS3401 0 extracts
the field from memory by reading word N and word N+ 1 in separate
cycles.

•

To move the field from a general-purpose register, the TMS3401 0 inserts
the field into memory by reading and writing word N, and reading and
writing word N+ 1.

The memory operations necessary to insert or extract a field are performed
automatically by special hardware, and are transparent to software.
14--------~12_1i11t

Logical AClclr...

--------tI

28-B1t
P/lyaloal AClClr_

Memory
""---. w~ ... N+1----tolf---lIIrOrCl

L
r
- Slza----'.I
FlelCI

Figure 4-1. Field Storage in External Memory
4-2

Hardware-Supported Data Structures - Fields

In Figure 4-1, word N is pointed to by a 26-bit physical address output by the
TMS34010 to memory. This 26-bit address corresponds to bits 4-29 of the
field's 32-bit logical address. The four LSBs of the logical address point to the
beginning of the field within word N.
The number of memory cycles required to extract or insert a field depends on
how the field is aligned in memory. Field manipulation is more rapid when
fields are stored in memory so that they do not cross word boundaries. Figure
4-2 illustrates various cases of alignment and nonalignment of fields to word
boundaries in memory. Given a field starting address and field length, the
memory controller will recognize the specified field alignment as one of the
seven cases in Figure 4-2. Field extraction and field insertion are performed
in a manner that requires the minimum number of memory cycles.
Case A

Case B

Word N+1
Word N
32-B1t Field

Case C

,
-

Case 0

LJE!N+1

Word N

Field

Case E

Word N+l.

Case F

Word N+1
ii===Fleld

Case G

Word N+2

Word N
Field

Word N

Word N+1
FIeld

Word N

Figure 4-2. Field Alignment in Memory
Case A A 16-bit field is aligned on word boundaries. Field extraction requires a single
read cycle, and field insertion requires a single write cycle.
Cases
B1-B3 The field length is less than 16 bits.
•
In Case B1, the field starting address is not aligned to a word boundary,
although the end of the field coincides with the end of the word.
•
In Case B2, the field starting address is aligned to a word boundary, but
the end of the field does not coincide with the end of the word.
•
In Case B3, the field length is 14 bits or less, and neither the start nor the
end of the field is aligned to a word boundary.
4-3

Hardware-Supported Data Structures - Fields

For Cases 81-83, a field extraction requires a single read cycle. A field insertion requires the following sequence of memory cycles:
1) Read word N
2) Write word N

Case C A 32-bit field is aligned on word boundaries. A field extraction requires the
following sequence of memory cycles:
1) Read word N
2) Read word N+ 1
A field insertion requires the following sequence of memory cycles:
1 ) Write word N
2) Write word N+ 1

Case D The field size is greater than 16 bits. The field starting address is not aligned
to a word boundary, but the end of the field coincides with the end of the
word. A field extraction requires the following sequence of memory cycles:
1) Read word N
2) Read word N+ 1
A field insertion requires the following sequence of memory cycles:
1) Read word N
2) Write word N
3) Write word N+ 1

Case E The field size is greater than 16 bits. The field starting address is aligned to a
word boundary, but the end of the field does not coincide with the end of the
word. A field extraction requires the following sequence of memory cycles:
1) Read word N
2) Read word N+ 1
A field insertion requires the following sequence of memory cycles:
1 ) Write word N
2) Read word N+ 1
3) Write word N+ 1

Case F The field straddles the boundary between two words. Neither the start nor the
end of the field is aligned to a word boundary. A field extraction requires the
following sequence of memory cycles:
1) Read word N
2) Read word N+ 1
A field insertion requires the following sequence of memory cycles:
1) Read word N
2) Write word N
3) Read word N+ 1
4) Write word N+ 1

Case G The field size ranges from 18 to 32 bits, and the field straddles two word
boundaries. Neither the start nor the end of the field is aligned to a word
boundary. A field extraction requires the following sequence of memory cycles:
1) Read word N
2) Read word N+ 1
3) Read word N+2
4-4

Hardware-Supported Data Structures - Fields

A field insertion requires the following sequence of memory cycles:
1) Read word N
2) Write word N
3) Write word N+ 1
4) Read word N+2
5) Write word N+2
A field insertion modifies only the portion of a word that lies within a field.
The TMS3401 0 memory controller must perform a read-modify-write operation when a field that does not begin and end on even 16-bit word boundaries
is to be written to memory. This occurs when the four LSBs of the address
are not 0, or when the specified field size is a value other than 16 or 32. The
memory controller uses these two parameters (address LSBs and field size) to
produce a mask that identifies the bits in the word corresponding to the field.
Hardware uses the mask to perform the read-modify-write cycle. The
TMS34010's local memory control logic automatically generates the mask and
executes the read-modify-write operation; this is transparent to software.
Figure 4-3 shows an example of inserting a 5-bit field stored in a register to
logical address OOOOOOOBh.
•
•
•
•
•

In Figure 4-3 a, the field to be inserted is shown right-justified in the
16 LSBs of the designated general-purpose register.
In b, memory controller hardware has rotated the field to align it with the
destination in memory.
In c, the TMS3401 0 reads the original word from the destination in memory.
In d, the mask is generated to designate the bits to be modified.
In e, the field is inserted into the word from memory, and the result is
written back to the destination address in memory.
II

(8) Field to be Inserted

(b) Rotate to align to bit 8

(e) Initial destination data

(d) Mask generated

(e) Final destination data

16 14 13 12 11 10

Figure 4-3. Field Insertion
In the more complex case in which a field straddles one or two word boundaries in memory, the portion of the field lying within each word is inserted into
that word using the methods described above.

4-5

Hardware-Supported Data Structures - Pixels

4.2 Pixels
The term pixel has two meanings in the context of a TMS34010-based
graphics system. Outside the TMS34010, a pixel is a picture element on a
display surface.
Inside the TMS34010, a logical pixel is a softwareconfigurable data structure supported by the TMS3401 0 instruction set. The
logical pixel data structure in TMS34010 memory contains the information
needed to specify the attributes of a picture element visible on a screen. The
information for a horizontal line of pixels on the screen is usually stored in
consecutive words in memory.

4.2.1

Pixels in Memory
Within TMS3401 0 memory, the pixel data structure is defined by two parameters:
•
•

Starting address and
Pixel size

A pixel's starting address is the address of the LSB of the pixel.
Pixel size (the number of bits per pixel) is defined in the PSIZE register. A
pixel can be 1, 2, 4, 8, or 16 bits long. The TMS3401 0 treats pixels as a special case of a field in which the field size is constrained to be a power of two.
However, pixels do not cross word boundaries within memory; they are
aligned within memory so that an integral number of pixels is contained within
the boundaries of a memory word. For example, a 2-bit pixel should begin at
an even bit address whose LSB is 0, a 4-bit pixel should begin at a bit address
whose two LSBs are Os, and so forth.
When a pixel is moved from memory to a general-purpose register, the pixel
is right justified within the register. That is, the LSB of the pixel coincides
with the rightmost bit (bit 0) of the register. Register bits to the left of the
pixel are loaded with Os.
Figure 4-4 illustrates pixel storage in memory. The pixel is located within the
word pointed to by the 26-bit physical address corresponding to bits 4-29 of
the 32-bit logical address of the pixel. The four LSBs of the logical address
specify the displacement of the pixel within the word. When the pixel length
is less than 16, each word contains two or more pixels.
Pixel extraction and insertion is performed by on-chip hardware in a manner
that requires the minimum number of memory cycles. (The operations are
transparent to the programmer.) In the worst case, two memory cycles (a read
followed by a write) are required to insert a pixel of less than 16 bits. Inserting
a 16-bit pixel requires a single write cycle, and extracting a pixel (1 to 16 bits)
requires a single read cycle.

4-6

Hardware-Supported Data Structures - Pixels

14---------32-BIt Logical AOI3rEIII8---------+I

28-B1t

MSBI

Phyalcal Acldreea

Memory

Pixel Size

Figure 4-4. Pixel Storage in External Memory

4.2.2 Pixels on the Screen
Figure 4-5 illustrates the mapping of pixels from memory to a display screen.
The screen refresh function outputs pixels in the sequence of ascending pixel
addresses. However, the electron beam sweeps from the left edge of the
screen to the right edge during each horizontal scan interval, so pixels appear
on the screen in the opposite order of their representation in memory. That is,
the least significant pixel (in terms of bit address) appears on the left, and the
most significant pixel appears on the right.
Video Monitor Screen
Word Wcrd Word
N+1
N-1
N

:====t';~T====]
r-

'--

Memory

I
I
I

IPixel Pixel Pixel Pixel I
I
I
I

I
I
I

4N+3 4N+2 4N+1 4N

~wordN+1

WordN

-I-

wordN-1~

Figure 4-5. Mapping of Pixels to Monitor Screen

4-7

Hardware-Supported Data Structures - Pixels

The TMS3401 0 allows a pixel to be identified either in terms of its XV coordinates on the screen, or in terms of the address of the. logical pixel in memory.
These two methods are called XV addressing and linear addressing, respectively.
When XV addressing is used, the origin can be selected to lie in either the
upper left or lower left corner of the screen. The position of the origin is
controlled by the ORG bit in the DPVCTL register. Figure 4-6 a illustrates the
default coordinate system (ORG =0), in which the origin of the two coordinate
axes is located in the upper left corner of the screen. Figure 4-6 b shows the
alternate coordinate system (ORG=1) in which the origin is located in the
lower left corner of the screen.

x
(8)
"""-Default

Soreen

Monitor
n
sor

Ortgln
y

(I)

Alternate
Screen

/orlgln

'-----+x
Figure 4-6. Configurable Screen Origin
Using the default screen origin, Figure 4-7 illustrates the mapping of pixels
from memory to the screen. In Figure 4-7, horizontal movement represents
travel in the X direction on the screen. Vertical movement represents travel in
the V direction. The depth of the buffer represents the pixel size. The "onscreen memory" contains the pixels that appear on the screen.
The display memory shown in Figure 4-7 is shown in terms of a "screen format" rather than the "memory format" used in the memory map shown in
Figure 3-3 on page 3-4. The screen format places the lowest pixel address
at the upper left corner of the memory map. This is the same relative orientation in which pixels appear on the screen. Compare this to the memory
format shown in Figure 3-3, which places the lowest bit address at the lower
right corner of the memory map. This convention is frequently used in industry to represent the relative location of addresses in memory. In this document, assume the standard memory format is used unless the screen format
is indicated.
Figure 4-8 illustrates the mapping of XV coordinates to the on-screen memory.
For simplicity, assume that the screen origin coincides with the upper left
4-8

Hardware-Supported Data Structures - Pixels

corner of the display memory. P represents the X extent of the display memory
and N represents the Y extent. Each box represents a pixel within the memory.
The number within the box represents the pixel's memory location, relative to
the beginning of the on-screen memory. The number in the box is multiplied
by the number of bits per pixel to produce the address offset of the pixel from
the start of the display memory. Since the pixel size is constrained to be a
power of two, the multiply can be replaced by a simple shift operation.
Display Memory

...-------+X

•

1----------,
I
I

I
I

On-Screen
Memory

orr-Screen
Memory

I
I
IL. _ _ _ _ _ _ _ _ _ _ I

...
~------x-Ext-ent-------------~~:::.~· Plxel81ze
(blta/plxel)

Figure 4-7. Display Memory Dimensions

~ Incr"xaalng

Increasing
V

x=o

X=1

X=2

X=P-2

X=3

V=O

V=1

P+1

P+2

P+3

V=2

2P+1

2P+2

2P+S

X=P-1

P-2

P-1

2P-2

2P-1

} 1 SP-2

SP-1

Display Memory
P = X Extent
N = V Extent

(N:~)P (N-1 )P
-1

NP-2

NP-1

Each box contains a pixel.
The number Inside the box
II the pixel's '1N addreaa.

Display Pitch

(X extent) x (pixel size)
Differences in 32-bit memory addresses
of two vertically adjacent pixels

Figure 4-8. Display Memory Coordinates

4-9

Hardware-.Supported Data Structures - Pixels

4.2.3 Display Pitch
The term display pitch refers to the difference in memory addresses between
two pixels that appear in vertically adjacent positions (one directly above the
other) on the screen. In Figure 4-8, the pitch is calculated as P times the pixel
size, where P is the X extent of the display memory.
The display pitch must be a power of two in order to support XY addressing
of pixels on the screen. Linear addressing of pixels on the screen imposes
fewer restrictions. In particular, the display pitch for linear addressing may be
any value that is a multiple of 16; that is, the four LSBs of the address must
be Os. Features such as automatic window checking are available with XY
addressing, but are not available with linear addressing.
The pitch of a pixel array is the difference in memory addresses of two vertically adjacent pixels in the array. If the array occupies a rectangular area of the
screen, the array pitch is the same as the display pitch.
During a pixel operation such as a Pix Bit, the source and destination array
pitches are specified in separate dedicated hardware registers. This facilitates
the transfer of pixel arrays between on-screen and off-screen memory, which
may have different pitches.
A sample display pitch calculation is shown below. In this example, the pixel
size is four bits and the X extent of the pixel display is 640 pixels. However,
since XY addressing and windowing are to be used, the physical memory is
organized so that there are 1024 pixels between successive scan lines. Thus,
the X extent of physical display memory is 1024, and the display pitch is:
Display Pitch

(1024 pixels/line) x (4 bits/pixel)
4096 (which is 212)

4-10

Hardware-Supported Data Structures - XV Addressing

4.3 XV Addressing
The TMS34010 allows pixel addresses to be specified in terms of twodimensional XY coordinates that correspond to locations on the screen. This
is referred to as XY addressing. XY addressing has several benefits:
•

TMS34010 software can be easily ported from one display configuration
to another. System-dependent details such as the number of bits per
pixel and the X extent of the display memory are transparent to the
software, but are used by the machine to automatically convert the XY
coordinates to the address of a pixel in memory.

•

XY addressing allows you to think in terms of the high-level concept of
XY coordinates rather than in terms of the machine-level mapping of
pixels into memory.

•

XY addressing facilitates such functions as window clipping.

Figure 4-9 illustrates XY addressing format. The XY address is stored in a
32-bit general-purpose register. The X and Y components are each treated
as 16-bit signed integers. The X component resides in the 16 LSBs of the
register, and is right justified to bit of the register. The Y component occupies the 16 MSBs of the register, and is right justified to bit 16 of the register.
XY coordinates in the range (-32768,-32768) to (+32767, +32767) can be
represented. The clipping window, which identifies the pixels that can be altered during drawing operations, is restricted to positive X and Y coordinate
values, (0,0) to (+32767,+32767). Thus, pixels identified by negative X or
Y coordinates must always lie outside the window.

I+---- 32----1
II--~~------~~X

v
Figure 4-9. Pixel Addressing in Terms of XV Coordinates

4-11

Hardware-Supported Data Structures - XV Addressing

4.3.1 XV-to-Linear Conversion
The TMS3401 0 automatically converts a pixel's XV address to a 32-bit logical
address (linear address) for all instructions that use XV addressing. Three
parameters are used to perform XV -to-linear conversion:
•
•
•

The logical pixel size (stored in the PSIZE register)
A pitch conversion factor (stored in the CONVSP or CONVDP registers)
An offset defining the XV origin (stored in the OFFSET register)

The TMS3401 0 uses the following formula to calculate the physical address
associated with the XV address:
Address = [(V x display pitch) OR (X x pixel size)] + offset
Since the display pitch and pixel size are both powers of two, the calculation
is performed using only shift, OR, and add operations. Window clipping may
be used to detect out-of-bounds (negative) X or V values before this calculation is performed.
Linear addresses are formed from XV addresses by simply concatenating the
binary numbers that represent the X and V coordinate values, as shown in
Figure 4-10. The number of Os to the right of the X component of the address
depends on the number of bits per pixel; and equals 1092(pixel size). The
displacement of the V component within the 32-bit logical address in Figure
4-10 is equa~ to 1092(display pitch). Finally, a 32-bit offset is added to the
address in Figure 4-10 to calculate the address in memory of the pixel at coordinates (X,V). The offset corresponds to the linear address in memory of the
pixel at (0,0).

0 ... 0

MSBa are Oe

y
Component

X
Component

0 ... 0

LSBa are Oe

Note: The shift value for the Y component is contained in
CONVSP or CONVDP register, depending on the instruction being executed.

Figure 4-10. Concatenation of XV Coordinates in Address

The TMS34010 uses the pitch conversion factors CONVSP and CONVDP
to compute the displacement of the V component within the address, as
shown in Figure 4-10. The V component is displaced from bit 0 of the address
by an amount equal to 1092(pitch), which the hardware obtains by inverting
the five LSBs of the appropriate CONVSP or CONVDP register. These values
must be loaded through software before executing an instruction that uses
XV addressing. CONVSP (source address pitch) is used if the XV address
points to a source pixel or pixel array; CONVDP (destination address pitch) is
used if the XV address points to a destination pixel or pixel array. The pixel
size stored in the PSIZE register is used similarly to determine the displacement of the X component, as shown in Figure 4-10.
4-12

Hardware-Supported Data Structures - XV Addressing

The OFFSET register contains the linear memory address of the pixel located
at coordinates (0,0) on the monitor screen. The OFFSET register is used in
translating XY coordinates into linear addresses, but does not control which
region of the display memory is output to refresh the video screen. It is a virtual screen origin. It allows the coordinate axes of the XY address to be
translated to an arbitrary position in memory. The OFFSET register supports
the use of "window relative" addressing in which the X and Y coordinates are
specified relative to coordinate offsets in the display memory. The position
and size of a window can be specified arbitrarily. A new offset specified in
terms of XY coordinates can be converted to a linear address using the CVXYL
instruction. CVXYL converts an XY address to a linear address for the purpose
of absolute memory addressing, or to use special features available to instructions that use linear addressing. Figure 4-11 illustrates the XY -to-linear
conversion process.
0
16 15
31
lal Original XV address

10000001

Ibl Extract 16 LSBs and
extend with Os

100000000000000000000001

(cl Rotate X left by
1092 (pixel sizel

1000000000000000000001

(dl Extract 16 MSBs from
original XV address
(el Rotate V left by
16 + 1092 (vertical pitchl
(fl Bitwise logical-OR together
shifted X and V components
(gl Add offset from B4 to
displacement above to
get final memory address

I~ign I

100

10000000000000000

I:~g~ 1

1000000000000

I I

00
.&..---'_

I..o.;;.f;..Y:..L.
_ _ _ _ _ _ _......_ _ _ _ _ _

Memory Address

Figure 4-11. Conversion from XV Coordinates to Memory Address

•
•
•
•
•
•
•

Step a shows the original XY address.
The X component is extracted in step b.
In step C, the X component is shifted left by lo92(pixel size). The result
of step c represents the product of the X component and the pixel size.
The Y component is extracted in step d.
In step e, the Y component is rotated left by 16+lo92(display pitch).
The result of step e is Y multiplied by the display pitch.
In step f, the results of steps c and e are bitwise-ORed to form the displacement in memory of the pixel at (X,Y) from the pixel at the origin.
In step G, the offset is added to produce the final memory address.

The example of Figure 4-11 corresponds to a pixel size of four bits and a pitch
of 4,096. The six MSBs of the X half of the XY address (bits 10-15) in Figure
4-11 must be Os to produce a valid memory address. For this example, the
4-13

Hardware-Supported Data Structures - XV Addressing

clipping window should be set to disable writes to pixels having X coordinate
values outside the range 0 to + 1023.
Generally, given a display with a pitch of 2 n, a valid memory address is produced by the XY translation process shown in Figure 4-11 when only the n
LSBs of the X half of the XY address are nonzero (that is, when the 16-n
MSBs are 0). X values may be in the range -32768 to +32767 before clipping. However, after clipping, the X value should be a positive number in the
range 0 to (Xextent -1), where Xextent = pitch/pixel size. The TMS34010's
automatic window clipping can be configured to clip pixels lying outside the
window; hence, no software overhead is incurred in clipping. Y values lying
outside the window are clipped in a similar fashion.

4-14

Graphics Operations - Pixel Arrays

4.4 Pixel Arrays
A rectangular area of the screen that is DX pixels wide and DY pixels high is
an example of a data structure called a two-dimensional pixel array. The
array contains OX x OY pixels, but can be manipulated by the TMS3401 0 as
one structure. The TMS34010's instruction set includes a powerful set of
raster operations, called Pix Bits, that manipulate pixel arrays on the screen and
elsewhere in memory.
Figure 4-12 shows a pixel array occupying a rectangular region in display
memory. The OX pixels in each row of the array are packed together into adjacent cells in the display memory. Rows do not generally occupy adjacent
areas of memory, but are separated from each other by a constant displacement called the array pitch. The array pitch is the difference in memory addresses between the start of one row and the start of the row directly beneath
it. In the Figure 4-12 example, the array pitch is equal to the display pitch.
The product of the array width OX and the pixel size must be less than or equal
to the pitch.
Display Memory

.--------+x
Default

2-D1mell81onll
Pixel Array

starting

Address

L.,.'

,..

ll.Y

ll.X
ll.X
ll.Y

= Pixels per row of array
= Pixels per oolumn of array

Figure 4-12. Pixel Array

A pixel array is specified in terms of its width, height, pitch, and starting address. The starting address is the address of the first pixel to be moved during
a PixBIt. The default starting address is simply the base address of the array;
that is, the address of the pixel that has the lowest address in the array.
In Figure 4-12, the XV origin is located in its default position at the upper left
corner of the screen. The default starting address is the address of the pixel
located in the upper left corner of the array. When a PixBlt operation moves
the pixels from a source pixel array to a destination array, the pixels in each
row are moved in sequence from left to right, and the rows are moved in sequence from top to bottom.
4-15

Graphics Operations - Pixel Arrays

Certain Pix Bit operations allow the starting pixel to be specified as one of the
pixels in the other three corners of the array. This feature is provided so that
when the source and destination arrays overlap, the appropriate starting corner
can be selected to ensure that no data is lost by being overwritten during
PixBlt execution. The order in which pixels in the array are moved can be altered to be from right to left or from bottom to top as appropriate to accommodate the change in starting corner.
The starting address of a pixel array can be specified either in terms of the XY
coordinates of the starting pixel (XY address), or the memory address of the
starting pixel (linear address):
•

An array whose starting location is specified as an XY address is referred
to as an XY array. In this format, the starting location of the array is
identified by the XY coordinates of the first pixel in the array.

•

A pixel array whose starting location is specified as a memory address
is referred to as a linear array. In this format, the location of the array is
identified by the memory address of the first pixel (the pixel that has the
lowest bit address) in the array.

The XY array format has two advantages. First, the starting location of the
array is specified in system-independent Cartesian coordinates rather than as
a system-dependent memory address. Second, the TMS34010's window
checking (which allows it to automatically detect an attempt to write a pixel
inside or outside a specified window) can only be used in conjunction with
XY addressing.
The linear format's main advantage is that the array pitch does not have to be
a power of two. This supports a wider variety of memory organizations. Using
XY format, the array pitch is constrained to be a power of two.
The general rules governing array pitch are as follows. When an array is specified in XY format, the pitch must be a power of two. The pitch for an array
specified in linear format may be any multiple of 16; that is, the four LSBs of
the pitch must be Os. There are a few important exceptions to the second rule
which are discussed below.
For the special case of a PIXBLT B,XY or PIXBLT B,L instruction, the source
pitch may be any value. This feature supports efficient use of memory by allowing adjacent rows of the source array to be packed together with no intervening gaps. The destination pitch must still be a multiple of 16.
Under certain conditions the linear source array specified for a PIXBLT L,XY
or PIXBLT B,XY must have a pitch that is a power of two. This is necessary
when the linear start address for the array has to be adjusted in the Y direction
due to one of the following conditions:

4-16

•

The source array is automatically preclipped to lie within a rectangular
window.

•

One of the lower two corners of the source array (refer to Figure 4-12)
is selected to be the start address.

Graphics Operations - Pixel Arrays

In either case, the start addresses specified for.both the source and destination
arrays are automatically adjusted, and for this purpose the conversion factors
specified in the CONVSP and CONVDP registers must be valid.
While PixBlts are useful for moving arrays from one area of the screen to another, they can also be used to move arrays to the screen from other parts of
memory, and vice versa. The pitch for the off-screen pixel array can be specified independently of the pitch for the on-screen array. This permits offscreen data to make efficient use of storage, regardless of the display pitch.
On-screen objects may be defined as XV arrays but may be more efficiently
stored as linear arrays in off-screen memory. The PIXBLT instructions support
the transfer of a linear array to an XV array, and vice versa. PIXBLT instructions can also be used to rapidly move blocks of non-pixel data (ASCII
characters, for example) from one location in memory to another.

4-17

Hardware-Supported Data Structures

4-18

Section 5

CPU Registers and Instruction Cache

The TMS3401 0 has two on-chip general-purpose register files, file A and file
B. Each register file contains 15 32-bit registers. The two files share a 32-bit
hardware stack pointer (SP) that automatically manages the system stack
during interrupts and subroutine calls. The TMS3401 0 also has two dedicated
32-bit registers - a program counter and a status register. An on-chip cache
holds up to 128 instruction words, and is transparent to software. The CPU
registers and instruction cache are discussed in the following sections:

Section
Page
5.1 General-Purpose Registers ....................................................................... 5-2
5.2 Status Register ......................................................................................... 5-18
5.3 Program Counter ..................................................................................... 5-19
5.4 Instruction Cache .................................................................................... 5-20
5.5 Internal Parallelism .................................................................................. 5-25
In addition to the CPU registers, the TMS3401 0 contains 28 memory-mapped
registers that are dedicated to I/O functions; Section 6 discusses the I/O registers.

5-1

CPU Registers and Instruction Cache - General-Purpose Registers

5.1 General-Purpose Registers
The TMS3401 0 has 30 32-bit general-purpose registers, divided into register
files A and B. In addition, a single stack pointer (SP) is common to both register files.
The multiple internal data paths that link the ALU and general-purpose registers provide single machine state execution of most register-to-register instructions.
Single-state instructions include add, subtract, Boolean
operations, and shifts (1 to 32 bits). During a single-state instruction, the
following actions occur:
1)
2)
3)

Two 32-bit operands are read in parallel from the general-purpose
registers.
The ALU performs the specified operation.
The 32-bit result is stored in the specified general-purpose register.

The general-purpose registers are dual-ported to permit operands to be read
from two independent registers at the same time.

5.1.1 Register File A
Fifteen of the 30 general-purpose registers, Ao-A14, form register file A.
These registers can be used for data storage and manipulation. No hardware-dedicated functions are associated with these general-purpose registers.
All register-to-register instructions (except MOVE Rs, Rd) require both registers to be in the same file. Instructions that manipulate registers Ao-A14 can
also manipulate the stack pointer. The SP can be specified in place of an Afile register in any of these instructions. Figure 5-1 illustrates register file A.
MSB

LSB

bit 31

bit 0

AO
A1
A2
A3
A4

A5
A6

AS
A9
A10
A11
A12
A13
A14

Stack Pointer

Figure 5-1. Register File A

5-2

CPU Registers and Instruction Cache - General-Purpose Registers

5.1.2 Register File B
Register file B consists of 15 general-purpose registers, Bo-B14. All register-to-register instructions (except MOVE RS,Rd) require both registers to be
in the same file. Instructions that manipulate registers So-B14 can also manipulate the stack pointer. The SP can be specified in place of a S-file register
in any of these instructions.
Registers So-B14 can be used for general-purpose functions such as data
storage and manipulation. During Pix Bit and other pixel operations, however,
these registers are assigned hardware-dedicated functions.
LS6
bit 0

MS6
bit 31
60

SADDR

Source address

SPTCH

Source pitch

DADDR

Destination address

DPTCH

Destination pitch

OFFSET

Offset

WSTART

Window start address

WEND

Window end address

DYDX

68
69

COLORa

Color 0

COLORl

Color 1

610

TEMP or COUNT

611

TEMP or INCl

612

TEMP or INC2

613

TEMP or PATTRN

614

TEMP

Stack Pointer

Delta Y/Delta X

Figure 5-2. Register File B

As Figure 5-2 shows, registers Bo-S9 are used as special-purpose registers
during pixel operations. These registers must be loaded with specific parameters before execution of pixel operations. Registers S1 o-S14 are used as
special-purpose registers for the LINE instruction. During pixel operations,
registers S1 O-B14 are used for temporary storage; their previous contents are
destroyed. Register functions may vary for individual instructions.
Section 5.1.4 describes the B-file registers in detail.

5-3

CPU Registers and Instruction Cache - General-Purpose Registers

5.1.3 Stack Pointer
The stack pointer (SP) is a 32-bit register that contains the bit address of the
top of the system stack. The TMS34010 contains only a single SP. However,
this SP can be addressed as a member of either register file, as register A15
or register B15. Any instruction that uses a general-purpose register as an
operand can also use the SP as an operand.
Figure 5-3 illustrates the stack pointer; Section 3.3 (page 3-6) describes stack
operation in detail.

Wore! Address

Bit Addr

1+14---28 blts----1~1I414-4 blt8~

Figure 5-3. Stack Pointer Register
The system stack grows in the direction of smaller addresses. During an interrupt. the PC and ST are pushed onto the stack to permit the interrupted
routine to resume execution when interrupt processing is completed. A subroutine call saves the PC on the stack to allow the calling routine to resume
execution when subroutine execution is completed.
The stack pointer always points to the value at the top of the stack. Specifically, the SP contains the 32-bit address of the LSB of that value. While the
four LSBs of the SP may be set to an arbitrary value, stack operations execute
more efficiently when the four LSBs are Os. Setting these bits to Os aligns the
stack pointer to 16-bit word boundaries in memory, reducing to two the
number of memory cycles necessary to push or pop the contents of a 32-bit
register.
The SP can be specified as the source or destination operand in any instruction that operates on the general-purpose registers. The SP can be accessed as register 15 in file A or B. Refer to the descriptions of the specific
instructions for details.

5-4

CPU Registers and Instruction Cache - General-Purpose Registers

5.1.4 Implied Graphics Operands
Table 5-1 summarizes the B-file register functions during graphics operations.
These registers are referred to as implied graphics operands. Several I/O registers, described in Section 6, are also implied graphics operands.

Table 5-1. B-File Registers Summary
Reg.
BO

Function
SADDR

Description
Source Address. Address of the upper left corner of the source pixel array
(lowest pixel address in the array). SADDR is a linear or XV address, depending on the instruction which uses it.
B1
Source Pitch. Difference in linear start addresses between adjacent rows of
SPTCH
a source pixel array.
B2
DADDR
Destination Address. Address of the upper left corner of the destination
pixel array (lowest pixel address in the array). DADDR is a linear or XV address, depending on the instruction which uses it.
DPTCH
B3
Destination Pitch. Difference in linear start addresses between adjacent
rows of a destination pixel array.
B4
OFFSET
Offset. Linear bit address corresponding to XV-coordinate origin (X=O, V=O).
WSTART
B5
Window Start Address. XV address of the upper left corner of the window
(smallest X and V coordinate values in the array).
Window End Address. XV address of the lower right corner of the window
WEND
B6
(largest X and V coordinate values in the array).
B7
Delta V jDelta X. The 16 LSBs of this register specify the width (X dimenDVDX
sion) of the destination array. The 16 MSBs specify the height (V dimension)
of the destination array. If either DV = 0 or OX = 0, then nothing is moved.
B8
COLORO
Pixel value corresponding to "color 0". COLORO contains the source
background color to be used during a color-expand operation (PIXBLT B,XV
or PIXBLT B,L). The pixel value should be replicated throughout the 16 LSBs
of register B8 (see note below). Non-replicated patterns may be entered for
dithering effects. The 16 MSBs are ignored during the expand operation. For
example, at four bits per pixel, COLORO contains four identical pixel values,
as shown below.
B9
COLOR1
Pixel value corresponding to "color 1". COLOR1 contains the source
foreground color to be used during a color-expand, fill, or draw-and-advance
operation. The pixel value should be replicated throughout the 16 LS Bs of
register B9 (see note below). Nonreplicated patterns may be entered for dithering effects. The 16 MSBs are ignored during the expand operation. For example, at four bits per pixel, COLOR1 contains four identical pixel values, as
shown below.
B10-B14
PixBlt temporary registers. PixBlt instructions use these registers for
storing temporary values and context information necessary to resume execution of a partially-completed PixBlt operation in the event of an interrupt.
SP
SP
Stack pointer. SP contains the bit address of the top of the stack.
...
Notes: To provide upward compatibility with future versions of the GSP, replicate the pixel value
throughout all 32 bits of COLORO or COLOR1, as shown.

5-5

Source Address Register

80
Format

Y
or

31
Linear Bit Address

Description

SADDR contains the source array address for PIXBLTs. Generally, SADDR
points to the pixel with the lowest address in the source array. When the
selected starting corner is not the upper left corner, the TMS34010 automatically adjusts SADDR to point to the selected starting corner of the
source array. (For PIXBLT L,L, however, you must manually adjust SADDR
to point to the starting corner. This feature allows you to use PIXBLT L,L
for manipulating pixel arrays with pitches that are not powers of two.)
SADDR is in either XY or linear format. If the first operand of a PIXBLT
instruction is an L (such as PIXBLT L,XY), then SADDR is in linear format.
If the first operand of a PIXBLT instruction is an XY (such as PIXBLT XY,L),
then SADDR is in XY format.
During PIXBLT operations, SADDR is used in linear format. When the
PIXBLT is completed, SADDR points to the starting location of the row that
follows the last row in the array. If a PIXBLT is interrupted, SADDR points
to the next word of pixels to be read.
During LINE operation, SADDR contains the current decision variable value.
The following instructions use SADDR as an implied operand:

Instruction
LINE
PIXBLT B,L
PIXBLT B,XY
PIXBLT L,L
PIXBLT L,XY
PIXBLT XY,L
PIXBLT XY,XY

Example

5-6

SADDR

SADDR Format and Function
Contains d=2b-a, used for the line draw.
Linear address; points to the beginning of a binary source
array (a bit map).
Linear address; points to the beginning of a binary source
array (a bit map).
Linear address with special requirements when PBH = 1
or PBV = 1. Refer to the PIXBLT L,L for a description of
its unique requirements.
Linear address; points to the beginning of a source array.
XY address; points to the beginning of a source array.
XY address; points to the beginning of a source array.

.set

MOVI

000800l5h, SADDR

MOVI

OOOlOAFCh, SADDR

Move XY value l5h,8h
into BO
Move linear value
lOAFCh into BO

Source Pitch Register

Format

31
Linear Bit Address

Description

SPTCH specifies the linear difference in the start addresses of adjacent rows
of the source array for PIXBLT and FILL instructions. The TMS3401 0 uses
the value in SPTCH to move from row to row through the source array.
SPTCH must be an integer multiple of 16 (except for the special cases of
PIXBLT B,L and PIXBLT B,XY). SPTCH is constrained in some cases to
be a power of two; this allows XY addressing and allows SADDR to be
automatically adjusted to point to an alternate starting corner.
The following instructions use SPTCH as an implied operand.

Instruction
PIXBLT B,L
PIXBLT B,XY
PIXBLT L,L
PIXBLT L,XY
PIXBLT XY,L
PIXBLT XY,XY

Example

SPTCH

SPTCH Format and Function
Linear; any value.
Linear; power of two for windowing, any value otherwise.
Linear; multiple of 16.
Linear; power of two ~ 16 for windowing or PBV = 1,
multiple of 16 otherwise.
Linear; power of two ~ 16.
Linear; power of two ~ 16.

.set

MOVI

OOOOlOOOh, SPTCH

MOVI

OOOlOAFCh, SPTCH

Power of two for
PIXBLT XY,L
Any value for
PIXBLT B,L

5·7

B2
Format

Destination Address Register

Y
or

31
Linear Bit Address
Description

DADDR contains the destination array address for PIXBL Ts. Generally,
DADDR points to the pixel with the lowest address in the destination array.
When the selected starting corner is not the upper left corner, the
TMS34010 automatically adjusts DADDR to point to the selected starting
corner of the destination array. (For PIXBLT L,L, however, you must manually adjust DADDR to point to the starting corner. This feature allows you
to use PIXBLT L,L for manipulating pixel arrays with pitches that are not
powers of two.)
DADDR is also used in conjunction with DYDX to perform a common rectangle function for some instructions (FILL XV, PIXBLT B,XY, PIXBLT
L,XY, and PIXBLT XY,XY, with window option 1). In these cases, DADDR
is set to the starting XY address of the common rectangle that represents
the intersection of the original destination array and the clipping window
indicated by WSTART and WEND. No drawing is performed. If the array
and the window do not intersect, the V bit is not set and the contents of
DADDR are undefined.
DADDR is in either XY or linear format. If the second operand of the
PIXBLT instruction is an L (such as PIXBLT XY,L), then DADDR is in linear
format. If the second operand of the PIXBLT instruction is an XY (such as
PIXBLT XY,XY), then DADDR is in XY format.
If DADDR is specified in XY format, the PIXBLT converts it to the corresponding linear address prior to the start of the pixel array transfer. During
PIXBLT operation, DADDR is maintained in linear format. When the
PIXBLT completes, DADDR points to the linear starting address of the row
following the last row in the array. If a PIXBLT is interrupted, DADDR
points to the next word of pixels to be read.
For the LINE instruction, DADDR contains the XY address of the next point
on the line.
The following instructions use DADDR as an implied operand.

Instruction
FILL L
FILL XY
LINE
PIXBLT B,L
PIXBLT B,XY
PIXBLT L,L
PIXBLT L,XY
PIXBLT XY,L
PIXBLT XY,XY

5-8

DADDR Format and Function
Linear; points to the beginning of the destination array.
XV; points to the beginning of the destination array.
XV; points to the current pixel.
Linear; points to the beginning of the destination array.
XV; points to the beginning of the destination array.
Linear with special requirements when PBH=1 or PBV=1.
Refer to the PIXBLT L,L for a description of its unique requirements.
XV; points to the beginning of the destination array.
Linear; points to the beginning of the destination array.
XV; points to the beginning of the destination array.

Destination Address Register

Example

DADDR

.set

MOVI

000800l5h, DADDR

MOVI

OOOlOAFCh, DADDR

Move XY value l5h,8h
into B2
Move linear value
lOAFCh into B2

5-9

83
Format

Destination Pitch Register

31
Linear Bit Address

Description

DPTCH specifies the linear difference in the starting memory addresses of
adjacent rows of the destination array for PIXBLT and FILL instructions.
The TMS3401 0 uses the value in DPTCH to move from row to row through
the destination array. DPTCH must be an integer multiple of 16 (except
for FILL L when DX=1). DPTCH is also constrained in some cases to be
a power of two; this allows XV addressing and allows DADDR to be automatically adjusted to point to an alternate starting corner.
The following instructions use DPTCH as an implied operand.
Instruction
FILL L
FILL XV
PIXBLT B,L
PIXBLT B,XV
PIXBLT L,L
PIXBLT L,XV
PIXBLT XV,L
PIXBLT XV,XV

Example

5-10

DPTCH

DPTCH Format and Function
Linear; unused when DV=1.
Linear; power of two ~ 16.
Linear; multiple of 16.
Linear; power of two ~ 16 for windowing, multiple of 16
otherwise.
Linear; mUltiple of 16.
Linear; power of two ~ 16.
Linear; power of two us.> 16 for PBV = 1, multiple of 16
otherwise.
Linear; power of two ~ 16.

.set

MOVI

OOOOlOOOh, DPTCH

MOVI

000 10AFCh , DPTCH

Power of two for
PIXBLT XY,L
Any value for
PIXBLT L,L

XV Addressing Offset Register

Format

31
Linear Bit Address

Description

OFFSET contains the linear address of the first pixel in the XV coordinate
space for instructions using XV addressing. This corresponds to the linear
address of the XV origin (X=O,V=O). This value is used as the memory base
for performing XV to linear address conversions.
OFFSET is always in linear format. It may be placed at any position in the
TMS34010 linear address space and should contain a pixel-aligned value
for proper XV address conversions, transparency, pixel processing, and
plane masking. Instructions that use OFFSET as an implied operand do not
modify the contents of OFFSET.
The following instructions use OFFSET as an implied operand.

Instruction
CVXVL RS,Rd
DRAV RS,Rd
FILL XV

LINE
PIXBLT B,XV
PIXBLT L,XV
PIXBLT XV,L
PIXBLT XV,XV
PIXT RS,Rd.XV
PIXT Rs.XV,Rd
PIXT Rs.XV,Rd.XV

Example

OFFSET

OFFSET Format and Function
Linear address of XV origin
Linear address of XV origin
Linear address of XV origin
Linear address of XV origin
Linear address of XV origin
Linear address of XV origin
Linear address of XV origin
Linear address of XV origin
Linear address of XV origin
Linear address of XV origin
Linear address of XV origin

.set

MOVI

00042000h, OFFSET

Linear value on
pixel boundary

5-11

85
Format

Window Start Address Register

Window start Y

Description

Window start X

WSTART specifies the XY address of the least significant pixel contained
in the rectangular destination clipping window. WSTART must be valid for
instructions that use an XY destination address and a window option. The
least significant pixel is the pixel with the lowest address in the array. For
a screen with the ORG bit of the DPYCTL register set to 0, this corresponds
to the pixel in the upper left corner of the pixel array.
WSTART may be placed at any position in the positive quadrant of the XY
address space. It describes an inclusive pixel; that is, the pixel at the XY
location contained in WSTART is included in the window. The value in
WSTART is used with WEND, DADDR, and DYDX to preclip pixels, lines,
and pixel arrays. WSTART is not modified by instruction execution.
The following instructions use WSTART as an implied operand.

Instruction
CPW RS,Rd
DRAV RS,Rd
FILL XY
LINE
PIXBLT B,XY
PIXBLT L,XY
PIXBLT XY,XY
PIXT RS,Rd.XY
PIXT Rs.XY,Rd.XY
Example

5-12

WSTART

WSTART Format and Function
XY value of least significant window
XY value of least significant window
XY value of least significant window
XY value of least significant window
XY value of least significant window
XY value of least significant window
XY value of least significant window
XY value of least significant window
XY value of least significant window

.set

MOVI

00400l00h, WSTART

corner
corner
corner
corner
corner
corner
corner
corner
corner

XY value (256,64)

stored in WSTART

Window End Address Register

Format

16
Window end Y

Description

15
Window end X

WEND specifies the XY address of the most significant pixel contained in
the rectangular destination clipping window. WEND must be valid for instructions that use an XY destination address and a window option. The
most significant pixel is the pixel with the highest address in the array. For
a screen with the ORG bit of the DPYCTL register set to 0, this corresponds
to the pixel in the lower right corner of the pixel array.
WEN D may be placed at any position in the positive quadrant of the XY
address space. It describes an inclusive pixel; that is, the pixel at the XY
location contained in WEND is included in the window. The value in
WEND is used with WSTART, DADDR, and DYDX to preclip pixels, lines,
and pixel arrays. WEND is not modified by instruction execution.
The following instructions use WEND as an implied operand.

Instruction
CPW RS,Rd
DRAV RS,Rd
FILL XY
LINE
PIXBLT B,XY
PIXBLT L,XY
PIXBLT XY,XY
PIXT RS,Rd.XY
PIXT Rs.XY,Rd.XY

Example

WEND

WEN D Format and Function
XY value of most significant window
XY value of most significant window
XY value of most significant window
XY value of most significant window
XY value of most significant window
XY value of most significant window
XY value of most significant window
XY value of most significant window
XY value of most significant window

.set

MOVI

00400100h, WEND

corner
corner
corner
corner
corner
corner
corner
corner
corner

XY value (256,64) stored
in WEND

5-13

Delta Y /Oelta X Register

87
Format

31
Delta Y

Description

15
Delta X

DYDX specifies the X and Y dimensions of the rectangular destination array
for PIXBLT and FILL instructions. Both the X and Y dimensions are in
pixels; that is, the DX value is number of pixels in width of the array, and
DY is the number of rows of pixels in the destination array.
When the window clipping option is selected, the pixel block dimensions
for the transfer are determined by the relationships between WSTART,
WEND, DADDR, and DYDX. If either the X or Y dimension is 0, then the
block is interpreted as having a dimension of 0; no transfer is performed.
The values for DY and DX may range up to the coordinate extent of the
display (up to 65,535, depending on the display pitch and pixel size selected).
For window operations, the relationship between DYDX,
WSTART, and WEN D is such that DY = Yend - Y start + 1 and DX = Xend
- Xstart + 1. The value in DYDX is used with WSTART, DADDR, and DYDX
to preclip pixels, lines, and pixel arrays.
Most graphics instructions do not modify the contents of DYDX. For FILL
XV, PIXBLT B,XY, PIXBLT L,XY, and PIXBLT XY,XY, with window option
1, however, DYDX is used with DADDR to perform a common rectangle
function. In this case, the instruction sets DYDX to the dimensions of the
common pixel block described by the intersection of the original destination
array and the window identified by WSTART and WEND. No drawing is
performed. If there is no common rectangle, the V bit is not set and the
value of DYDX is indeterminate. See these instructions for further information.
The following instructions use DYDX as an implied operand.

Instruction
FILL L
FILL XY
LINE
PIXBLT B,L
PIXBLT B,XY
PIXBLT L,L
PIXBLT L,XY
PIXBLT XY,L
PIXBLT XY,XY

Example

This example illustrates the relationship of DYDX to WSTART and WEND.
WSTART
WEND
DYDX

5-14

DVDX Format and Function
Array dimensions in XY format.
Array dimensions in XY format; special results when W=1
is selected, as previously noted.
Dimensions of the rectangle described by the line to be
drawn.
Array dimensions in XY format
Array dimensions in XY format; special results when pick
is selected, as previously noted.
Array dimensions in XY format.
Array dimensions in XY format; special results when pick
is selected, as previously noted.
Array dimensions in XY format.
Array dimensions in XY format; special results when pick
is selected, as previously noted.

.set
.set
.set

BS
B6
B7

MOVE
SUBXY
ADDI

WEND, DYDX
WSTART, DYDX
lOOOlh, DYDX

Put WEND into DYDX
Generate (WEND - WSTART)
Increment by 1 in each
dimension

Background Color Register

Format

31
Replicated Pixel Value

Description

COLORO specifies the replacement color for 0 bits in the source array for
PIXBLT B,L and PIXBLT B,XY instructions. These two instructions transform binary pixel array information to multiple bits per pixel arrays using the
color information in COLOR1 and COLORO. The lower 16 bits of COLORO
are used for the 0 or background color. There is a direct correspondence
between the alignment of pixels within the COLORO register and pixels
within memory words to be altered. That is, individual pixels within
COLORO are used as they align with destination pixels in the destination
word.
Execution of graphics instructions does not modify COLORO.
To provide upward compatibility with future versions of the GSP, the plane
mask should be replicated through all 32 bits of COLORO.
The following instructions use COLORO as an implied operand.
Instruction
PIXBLT B,L
PIXBLT B,XY

Example

COLORO Contents
Background pixel color for color-expanded array
Background pixel color for color-expanded array

This example is for 4-bit pixels. A pixel value of 5 is replicated throughout
the register.

COLORO

.set

MOVI

55555555h, COLORO

store uniform pixel
value in COLORO

5-15

89
Format

Foreground Color Register

31
Replicated Pixel Value

Description

COLOR1 specifies the replacement color for pixels to be altered at the destination pixel or pixel block for FILL, DRAV and LINE instructions.
For PIXBLT B,L and PIXBLT B,XY instructions, COLOR1 specifies the replacement color for 1 bits in the source array. These two instructions
transform binary pixel array information to multiple-plane pixel arrays using
color information in COLOR1 and COLORO. There is a direct correspondence between the alignment of pixels within the COLOR1 register and pixels within memory words to be altered. That is, individual pixels within
COLOR1 are used as they align with destination pixels in the destination
word.
Execution of graphics instructions does not modify COLOR1.
To provide upward compatibility with future versions of the GSP, the plane
mask should be replicated through all 32 bits of COLOR1.
The following instructions use COLOR1 as an implied operand.

Instruction
DRAV RS,Rd
FILL L
FILL XY
LINE
PIXBLT B,L
PIXBLT B,XY
Example

This example is for 4-bit pixels. A pixel value of 3 is replicated throughout
the register.
COLOR 1

5-16

COLOR1 Contents
Pixel color for pixel draw
Pixel color for filled array
Pixel color for filled array
Pixel color for line draw
Foreground pixel color for color-expanded array
Foreground pixel color for color-expanded array

.set

MOVI

33333333h, cOLORl

Store uniform pixel
value in cOLORl

810-814

Reserved Registers

Format

31
Various Formats

Description

The functions of these registers depend on which instruction uses them:
•

PIXBLT and FILL instructions use registers B10 through B14 as temporary registers that hold intermediate values.

•

The LINE instruction uses these registers as implied operands with the
following functions:
B11 is the INC1 register; it specifies the X and Y increments for
a diagonal step.
B12 is the I NC2 register; it specifies the X and Y increments for
a nondiagonal step.
B10 is the COUNT register; it specifies the number of pixels to
be drawn in the line.
B13 is the PATTRN register; it is reserved for future LINE draw
enhancement. It should be set to OFFFFFFFFh before executing
the LINE instruction to ensure software compatibility.
B14 is a temporary register (TEM P) that holds intermediate values.

5-17

CPU Registers and Instruction Cache - Status Register

5.2 Status Register
The status register (ST) is a special-purpose, 32-bit register that specifies the
processor status. The ST also contains several parameters that specify the
characteristics of two programmable data types, fields 0 and 1. The ST is initialized to 00000010h at reset.
Figure 5-4 illustrates the status register. Table 5-2 lists the functions associated with the status bits. Table 5-3 describes the encoding of the field size
bits in FSO and FS1.

Note: The status register bits marked reserved (bits 12-20, 22-24, and 26-27)
are currently unused. When read, a reserved bit returns the last value
written to it. At reset, all reserved bits are forced to Os.

Figure 5-4. Status Register
Table 5-2. Definition of Bits in Status Register
Bit
No.

Field
Name

0-4

FSO

Field Size O. length in bits of first memory data field (see Table 5-3 for values).

FEO

Field Extend O. Bit determines whether field from memory is extended with Os or
with the sign' bit when loaded into 32-bit general-purpose register.

Function

FEO = 0 selects zero extension for field 0
FEO = 1 selects sign extension for field 0
6-10

FS1

Field Size 1. length in bits of second memory data field (see Table 5-3 for values).

FE1

Field Extend 1. Bit determines whether field from memory is extended with Os or
with the sign bit when loaded into 32-bit general-purpose register.
FE1 = 0 selects zero extension for field 1
FE1 = 1 selects sign extension for field 1

PBX

Interrupt Enable. Master interrupt enable/disable bit.
IE = 0 disables all maskable interrupts
IE = 1 enables all maskable interrupts
PixBlt Executing. Indicates upon return from an interrupt that the interrupt occurred between instructions or in the middle of a PIXBlT or Fill instruction.
0= Indicates interrupt occurred at PIXBlT or Fill instruction boundary
1 = Indicates interrupt occurred in the middle of a PIXBlT or FILL instruction

Overflow. Set according to instruction execution.

Zero. Set according to instruction execution.

30
31

Carry. Set according to instruction execution.

Negative. Set according to instruction execution.

Reserved

12
20
22-24
26-27

5-18

CPU Registers and Instruction Cache - Status Register/Program Counter
Table 5-3. Decoding of Field-Size Bits in Status Register

Five FS
Bits

Field
Sizet

Five FS
Bits

Field
Sizet

Five FS
Bits

00001
00010
00011
00100
00101
00110
00111
01000

1
2
3
4
5
6
7
8

01001
01010
01011
01100
01101
01110
01111
10000

9
10
11
12
13
14
15
16

10001
10010
10011
10100
10101
10110
10111
11000

Field
Sizet
17
18
19
20
21
22
23
24

Five FS
Bits

Field
Sizet

11001
11010
11011
11100
11101
11110
11111

25
26
27
28
29
30
31

00000

In bits

5.3 Program Counter
The program counter (PC) is a dedicated 32-bit register that points to the next
instruction word to be executed. Instructions are always aligned on even
16-bit word boundaries, and as shown in Figure 5-5, the four LSBs of the PC
are always Os.
31

"8
Word Addr_

0
0 0

Figure 5-5. Program Counter

An instruction consists of one or more instruction words. The first word
contains the opcode for the instruction. Additional words may be required for
immediate data, displacements, or absolute addresses. As each instruction
word is fetched, the PC is incremented by 16 to point to the next instruction
word. The PC contents are replaced during a branch instruction, subroutine
call instruction, return instruction, or interrupt.. Instructions may be categorized according to their effect on the PC, as indicated in Table 5-4.

Table 5-4. Instruction Effects on the PC
Category

Description

Non-branch

The PC is incremented by 16 at the end of the instruction.
allowing execution to proceed sequentially to the next instruction.

Absolute Branch
(TRAP. CALL. JAcc)

The PC is loaded with an absolute address; the four LSBs
of the address are set to Os.

Relative Branch
(JRcc. DSJxx)

The signed displacement (8 or 16 bits) is added to the
current contents of the PC. The signed displacement is
treated as a word displacement; that is. it is shifted left four
bit positions before it is added to the PC.

I ndirect Branch
(JUMP. CALL.
EXGPC)

The PC is loaded with the register contents. The four LSBs
are set to Os.

5-19

CPU Registers and Instruction Cache - Instruction Cache

5.4 Instruction Cache
Most program execution time is spent on repeated execution of a few main
procedures or loops. Program execution can be speeded up by placing these
often used code segments in a fast memory. The TMS34010 uses a 256-byte
instruction cache for this purpose.
Only instruction words (memory words that are pointed to by the PC) can be
accessed from the cache. This includes opcodes, immediate operands, displacements, and absolute addresses. Instructions and data may reside in the
same area of memory; therefore, data may occasionally be copied into the instruction cache along with instruction words. However, the processor cannot
access data from the cache. All reads and writes of data in memory bypass the
cache.

5.4.1 Cache Hardware
The instruction cache contains 256 bytes of RAM, used to store up to 128
16-bit instruction words. Each instruction word in cache is aligned on an even
word boundary. Figure 5-6 illustrates cache organization.
p

,==
--.
-18I
I ~}_2
_ _ 84 _ _

SeA RegIater 1

SeA Re!!later 2

S8A RegIIIter 3

........

SUbaegment 2
of segment 1

I~-'

Figure 5-6. TMS34010 Instruction Cache
The cache is divided into four 32-word segments. Each cache segment may
contain up to 32 words of a 32-word segment in memory. This memory seg-

5-20

CPU Registers and Instruction Cache - Instruction Cache
ment is a block of 32 contiguous words beginning at an even 32-word
boundary in memory.
Each cache segment is divided into eight subsegments; each subsegment
contains four words. Dividing each segment into subsegments reduces the
number of word fetches required from memory when fewer than 32 words of
a memory segment are used. Each of the four cache segments is associated
with a segment start address (SSA) register. Figure 5-7 shows how an instruction word is partitioned into the components used by the cache control
algorithm.

~1t-------32-BIt Unear Addreaa

23BIta

Ln.~._~M_
word address are aIWay8 O.
Instruction word address
within aub8egment

L -_ _ _ _ _ _ _ _ _ _ _ _ _

Subaegment address
Segment start addreas
(SSA register)

Figure 5-7. Segment Start Address
The 23 bits of the SSA register correspond to the 23 MSBs of the segment's
memory address. These 23 MSBs are common to all eight subsegments within
a segment. The next three bits (bits 6-8) identify one of the eight subsegments. Bits 4 and 5 identify one of the four words contained in a subsegment.
The four LSBs are always Os because instructions are aligned on word boundaries.

5.4.2 Cache Replacement Algorithm
When the TMS3401 0 requests an instruction word from a segment that is not
in the cache, the contents of one of the four cache-resident segments must
be discarded to make room for the segment that contains the requested word.
A modified form of the least-recently-used (LRU) replacement algorithm is
used to select the segment to be discarded.
The LRU segment manager (part of the cache control logic) maintains an LRU
stack to track use of the four segments. The LRU stack contains a queue of
segment numbers, 0 through 3. Each time a segment is accessed, its segment
number is moved to the top of the stack, pushing the other segment numbers
down as necessary to make room at the top. Thus, the number at the top of
the LRU stack identifies the most-recently-used segment and the number at
the bottom identifies the least-recently-used segment.
When a new segment must be loaded into cache, the least-recently-used
segment is discarded. The eight P flags (described in Section 5.4.3) of the
selected segment are set to Os, and the segment's SSA register is loaded with
the new segment address. After the requested subsegment has been loaded
from memory, its P flag is set to 1, and the requested instruction fetch is allowed to complete.
Following a reset, all P flags in the cache are set to 0 and the four segment
numbers in the LRU stack are stored in numerical order (0-1-2-3).

5-21

CPU Registers and Instruction Cache - Instruction Cache
5.4.3 Cache Operation
When the TMS3401 0 requests an instruction word, it checks to see if the word
is contained in cache. First, it compares the 23 MSBs of the instruction address to the four SSA registers. If a match is found, the processor searches for
the appropriate subsegment. A present (P) flag, associated with each subsegment, indicates the presence of a particular subsegment within a cache
segment. P=1 indicates that the requested word is in cache; this is called a
cache hit. If there is no match, or if there is a match and P=O, the word is not
in cache; this is called a cache miss.

5.4.3.7 Cache Hit
The cache contains the requested instruction word. The processor performs
the following actions:
1)

A short (one machine state) access cycle reads the instruction word from
cache.

The segment number is moved to the top of the LRU stack, pushing the
other three segment numbers toward the bottom of the stack.

Due to pipelining, instruction fetches from the cache frequently overlap completion of preceding instructions. The overhead due to instruction fetches in
such cases is effectively zero.

5.4.3.2 Cache Miss
The cache does not contain the instruction word.
cache miss - subsegment miss and segment miss.
•

•

5-22

There are two types of

Subsegment Miss. The 23 MSBs of the instruction word address
match one of the four SSA registers' 23 MSBs; that is, the appropriate
segment is in the cache. However, the P flag for the requested subsegment is not set. The processor performs the following actions:
1)

The four-word subsegment containing the requested instruction
word is read from local memory into the cache.

The segment number is moved to the top of the LRU stack, pushing the other three segment numbers toward the bottom of the
stack.

The subsegment's P flag is set.

The instruction word is read from the cache.

Segment Miss. The instruction word address does not match any of
the SSA registers. The processor performs the following actions:
1)

The least-recently-used segment is selected for replacement; the P
flags of all eight subsegments are cleared.

The SSA register for the selected segment is loaded with the 23
MSBs of the address of the requested instruction word.

CPU Registers and Instruction Cache - Instruction Cache
3)

The four-word subsegment in memory that contains the requested
instruction word is read into the cache. It is placed in the appropriate subsegment of the least-recently-used segment. The subsegment's P flag is set to 1.

The LRU stack is adjusted by moving the number of the new segment from the bottom (indicating that it is least recently used) to
the top (indicating that it is most recently used). This pushes the
other three segment numbers in the stack down one position.

The instruction word is read from the cache.

5.4.4 Self-Modifying Code
Avoid using self-modifying code; it can cause unpredictable results. When a
program modifies its own instructions, only the copy of the instruction that
resides in external memory is affected. Copies of the instructions that reside
in cache are not modified, and the internal control logic does not attempt to
detect this situation.

5.4.5 Flushing the Cache
Flushing the cache sets it to an initial state which is identical to the state of
the cache following reset. The cache is empty and all 32 P flags are set to O.
The cache is flushed by setting the CF (cache flush) bit in the HSTCTL register
to 1. The CF bit retains the last value loaded until a new value is loaded or
until the TMS3401 0 is reset. The contents of the cache remain flushed as long
as the CF bit is set to 1. All instruction fetches bypass the cache and are accessed directly from memory.
Unless the cache is disabled, normal cache operation will resume when the
CF bit is set to O.
One use for flushing the cache is to facilitate downloading new code from a
host processor to TMS34010 local memory. The host typically halts the
TMS34010 during downloading by writing a 1 to the H LT bit in the HSTCTL
register. Before allowing the TMS34010 to execute downloaded code, the
host should flush the cache to purge it of stale instructions.
For performance reasons, the CD bit should not remain set to 1 for long periods. While CD=1, each instruction-word fetch is interpreted as a cache miss,
causing the four words in the subsegment to be fetched from memory.
Though the word pointed to by the PC is executed, none of the four words is
preserved in cache.

5-23

CPU Registers and Instruction Cache - Instruction Cache
5.4.6 Cache Disable
Disabling the cache facilitates program debugging and emulation. The cache
is disabled by setting the CD (cache disable) bit in the CONTROL register to
1. While disabled. the cache is bypassed and all instructions are fetched from
external memory.
CD=1 is similar in effect to CF=1. with several exceptions:
•

While CD=1 and CF=O. data already in the cache are protected from
change. When the CD bit is set back to 0, the state of the cache prior
to setting the CD bit to 1 is restored. The instructions in the cache are
once again available for execution. If the contents of the cache become
invalid while CD=1, they can be flushed by setting CF to 1.

•

While CD=1 and CF=O, each instruction word is fetched from memory
as it is requested, but the other three words in the subsegment are not
fetched. In contrast, if CF=1 and CD=O, all four words in the subsegment that contain the requested instruction word are fetched, although
all but the requested word are immediately discarded.

The CD bit can be manipulated to preserve code in the cache for faster execution in some time-critical applications. For example. if an inner loop just
exceeds 256 bytes, most of the loop, but not all of it, can fit in the cache.
During execution of the few instructions that are not in the cache, the CD bit
can be set to 1 to prevent the code in the cache from being replaced. In this
instance, the loop's execution speed is improved by eliminating the thrashing
of cache contents. Use this technique carefully; in some cases, it can negatively affect execution speed.

5.4.7 Performance with Cache Enabled versus Cache Disabled
When the instruction cache is disabled, instruction words are fetched from
external memory. Assuming no wait states are necessary, each instruction
fetch from external memory adds 3 machine cycles to the access time. This is
considerably slower than a program which uses the cache efficiently (when
each word in cache is used several times before it is replaced).
A less efficient use of cache occurs when words in cache are used only once
before replacement. This produces a cache miss every fourth word (even in
this case, operation is usually much better than operation when the cache is
disabled). With the cache enabled, the time penalty due to cache misses in
this case is 2.25 machine states per single-word instruction (compare this to
3 states when the cache is disabled), which is calculated as follows:
•
•
•

Eight machine cycles are required to load four words into cache from
memory.
An additional machine state is required to start processing the instruction.
Dividing the total of nine machine states by four instruction words yields
an average of 2.25 machine states per instruction word.

Performance using the cache is nearly always better than performance with the
cache disabled. There are two exceptions. The first occurs when the code
contains so many jumps that only a portion of each subsegment is executed
before control is transferred to another subsegment. The second occurs when
5-24

CPU Registers and Instruction Cache - Cachet Internal Parallelism
an inner loop is larger than the cache, in which case only some portion of the
instructions in the inner loop can be contained in the cache at any time. In this
case, performance may be improved by manipulating the CD bit as described
in Section 5.4.6.
While the cache is disabled, the TMS34010's internal memory controller
fetches each instruction word from memory only as it is requested by the internal execution unit. This differs from operation with the cache enabled, in
which case a cache miss causes the entire four-word subsegment containing
the requested instruction word to be loaded into the cache at once.

5.5 Internal Parallelism
Figure 5-8 illustrates the internal data paths associated with TMS3401 0 processor functions. The TMS3401 0 has a single, logical memory space for storage of both data and instructions. However, internal parallelism provides the
TMS34010 with the benefits found in architectures which contain separate
data and instruction storage (sometimes referred to as Harvard architectures).
The ability to fetch instructions from cache in parallel with data accesses from
memory greatly enhances execution speed. Hardware parallelism allows the
following three storage areas to be accessed simultaneously:
•
•
•

Instruction cache
Dual-ported, general-purpose register files A and B
External memory
~------------------------------1

S4010
lnIInIotIon
Cache

:=
General-

CPU

lnIItructlOI\8

Data

Memory
Interface

External

Memory

Figure 5-8. Internal Data Paths

5-25

CPU Registers and Instruction Cache -, Internal Parallelism
Each storage area can also be accessed independently of the other two. This
allows the TMS3401 0 to perform the following actions in parallel during a pair
of machine states:
•
•
•

One external memory cycle
Two instruction fetches from cache
Four reads and two writes to the general-purpose register files

The need to schedule conflicting internal operations can limit the TMS3401 O's
ability to perform these actions in parallel. For example, an instruction which
requires the memory controller to perform a read must finish executing before
the next instruction can be executed.
Figure 5-9 illustrates an example of internal parallelism. Figure 5-9 a shows
three activities occurring in parallel:
•
•
•

Instructions are fetched from cache.
Instructions are executed through the general-purpose registers and
the ALU.
The local memory interface controller performs memory accesses.

Figure 5-9 a represents execution of the code in Figure 5-9 b, which is the
inner loop of a graphics routine. The memory controller accesses pixels while
the ALU fetches instructions from cache. The memory controller completes a
write cycle while execution begins on the next instruction.
(al

State:

--+It-1-+/f-2*3*4*&*8*7*8*9-+14-1O*11*12*-

MOVE
lnatructlon Fatch:t~l.l~j

ADD

Read Cycle

L1:

MOVE
ADD

PIXT
ADD

D8J8

PIXT

ADD DSJ8

B M:~~~t~]

t!i!B

Memory Interface:

(b)
It.
B
C

One iteration

Read

Gat DELTA)(

BlO,88

AdjU8t pixel pointer
Draw next pixel
Add flakI IIZe

BO,B1

B11,L1

MOVE

III

1181+,810,0
1181,1IB8

0 H~~~;~~r:1

wrrte

Loop N TIm..

Figure 5-9. Parallel Operation of Cache, Execution Unit, and Memory Interface

5-26

Section 6

I/O Registers

The TMS34010's 28 on-chip I/O registers control and monitor the following
functions:
•

Host interface communications

•

Local memory interface control

•

Interrupt control

•

Video timing and screen refresh

This section describes these functions, I/O register addressing, and then provides an alphabetical presentation of the I/O registers:

Section
Page
6.1 I/O Register Addressing ........................................................................... 6-2
6.2 Latency of Writes to I/O Registers .......................................................... 6-4
6.3 I/O Registers Summary ............................................................................. 6-5
6.4 Alphabetical Listing of I/O Registers .................................................... 6-10

6-1

I/O Registers - Addressing

6.1 1/0 Register Addressing
TMS34010 I/O registers occupy addresses COOOOOOOh to C00001 FFh. These
registers can be directly accessed by the TMS34010; they can also be indirectly accessed by a host processor through the host interface registers. For
example, the host processor can indirectly read the contents of the PSIZE register by loading the address C0000150h into the HSTADRL and HSTADRH
registers, and reading the HSTDATA register. Figure 6-1 illustrates the I/O
register memory map.
C00001FOh
C00001EOh
C00001DOh
C00001COh
C00001 BOh
C00001AOh
C0000190h
C0000180h
C0000170h
C0000160h
C0000150h
C0000140h
C0000130h
C0000120h
C0000110h
C0000100h
COOOOOFOh
COOOOOEOh
COOOOODOh
COOOOOCOh
COOOOOBOh
COOOOOAOh
C0000090h
C0000080h
C0000070h
C0000060h
C0000050h
C0000040h
C0000030h
C0000020h
C0000010h
COOOOOOOh

REFCNI
DPYADR
VCOUNT
HCOUNT
DPYTAP

DRAM Refresh Count
Display Address
Vertical Count
Horizontal Cou nt
Display Tap Point

Reserved
PMASK
PSIZE
CONVDP
CONVSP
INTPEND
INTENB
HSTCTLH
HSTCTLL
HSTADRH
HSTADRL
HSTDATA
CONTROL
DPYINT
DPYSTRT
DPYCTL
VTOTAL
VSBLNK
VEBLNK
VESYNC
HTOTAL
HSBLNK
HEBLNK
HESYNC

Plane Mask
Pixel Size
Destination Conversion Pitch
Source Conversion Pitch
Interrupt Pending
I nterrupt Enable
Host Control (MSBs)
Host Control (LSBs)
Host Address (MSBs)
Host Address (LSBs)
Host Data
Control
Display Interrupt
Display Start
Display Control
Vertical Total
Vertical Start Blank
Vertical End Blank
Vertical End Sync
Horizontal Total
Horizontal Start Blank
Horizontal End Blank
Horizontal End Sync

Figure 6-1. I/O Register Memory Map
The two MSBs of an I/O register's 32-bit internal address are not output on
the TMS34010 pins; however, the address is fully decoded internally. Thus,
the two MSBs of a 32-bit address must both be 1s for an address to be recognized as that of an I/O register. When an I/O register is accessed, the accompanying memory cycle (as seen at the TMS3401 0 pins) is altered so that
the row address strobe is output, but the column address strobe is inhibited.
This is true whether the access is initiated directly by the TMS3401 0 or indirectly by a host processor.

6-2

I/O Registers - Addressing

An access of any address in the range COOOOOOOh-COOOO1 FFh is decoded as
an access of an on-chip register location, and the column address strobe remains inactive high through the cycle. An access of any location outside this
range is treated as an access of an external memory location.
All I/O registers, with one exception, are cleared to 0 at reset. The exception
is the H LT (halt) bit in the HSTCTL register, which is set depending on the
value at the HCS input pin at the end of the reset pulse:
•
•

If HCS is high at reset. the HLT bit is set to 1
If HCS is low at reset. the H LT bit is set to 0

6-3

I/O Registers - Latency of Writes to I/O Registers

6.2 Latency of Writes to I/O Registers
When an instruction alters the contents of an I/O register, the memory write
cycle that modifies the register may not be completed before execution of the
next instruction begins. If the second instruction relies on the I/O register
value loaded by the first instruction, the second instruction may cause incorrect results. This type of problem could occur, for example, if a PIXBLT instruction were immediately preceded by a MOVE register-to-memory
instruction that modified the CONTROL register. This situation is easily
avoided by ensuring that the write to the I/O register is allowed to complete
before the I/O register value is used as an implied operand by a subsequent
instruction. For example, by immediately following a write to an I/O register
with a read of the register, the write is certain to have been completed by the
time subsequent instructions begin execution.
Internal to the TMS34010, the memory controller operates semi-autonomously with respect to the execution unit that processes instructions. Parallelism between the execution unit and memory controller may allow a write
initiated by an instruction to be completed only after one or more subsequent
instructions have been executed. An instruction that alters an I/O register (or
any other address in memory) transmits its request for a write cycle to the
memory controller. Once the request is accepted, the memory controller is
responsible for completing the write cycle; in the meantime, execution of the
next instruction can begin.
A field insertion request submitted to the memory controller can take as many
as five cycles to complete in the case in which a field of 18 or more bits
straddles two word boundaries. This case requires a read-modify-write operation to one word, a write to a second word, and a read-modify-write operation to a third word. Although this would be an unusual way of altering
locations in the I/O register file, it represents the theoretical worst case number
of memory cycles for a field insertion.
The start of a pending field-insertion cycle may be delayed by the following
conditions:
•
•
•
•
•

Screen-refresh cycle
DRAM-refresh cycle
Host-indirect read or write cycle
Wait states required for slower memories
Hold request from an external device

Any uncertainty as to whether a pending write to memory has been completed
can be eliminated by making use of the fact that only one field insertion request can be queued at the memory controller at a time. An instruction that
requests a second memory access before the earlier field insertion has been
completed will be forced to wait. Hence, by following an instruction that alters an I/O register with an instruction that requests a second memory access
(any memory access). the I/O register is certain to have been updated before
the second instruction finishes executing.

6-4

I/O Registers - Summary

6.3 I/O Registers Summary
Table 6-1 summarizes the I/O registers.
of I/O registers follow the table.

Descriptions of the four categories

Table 6-1. I/O Registers Summary
Host Interface Registers
Register

Address

HSTADRH

COOOOOEOh

Host interface address. high word. Contains the 16 MSBs of a
32-bit pointer address used by a host processor for indirect accesses of
TMS34010 local memory.

Description

HSTADRL

COOOOODOh

Host interface address. low word. Contains the 16 LSBs of a 32-bit
pointer address used by a host processor for indirect accesses of
TMS34010 local memory.

HSTCTLH

COOOO100h

Host interface control. high byte Contains seven programmable bits
that control host interface functions:
NMI (bit 8)
- Nonmaskable interrupt
NMIM (bit 9) - NMI mode bit
INCW (bit 11) - Increment pointer address on write
INCR (bit 12) - Increment pointer address on read
LBL (bit 13) - Lower byte last
CF (bit 14)
- Cache flush
HLT (bit 15) - Halt TMS3401 0 execution
Bits 0 throug h 7 and 10 are reserved

HSTCTLL

COOOOOFOh

Host interface control. low byte. Contains eight programmable bits
that control host interface functions:
MSGIN (bits 0-2) - I nput message buffer
INTIN (bit 3)
- Input interrupt bit
MSGOUT (bits 4-6) - Output message buffer
INTOUT (bit 7)
- Output interrupt bit
Bits 8 through 15 are reserved

HSTDATA

COOOOOCOh

Host interface data. Buffers data transferred between TMS3401 0 local
memory and a host processor.

Address

Local Memory Interface Registers

Description

CONTROLt COOOOOBOh

Memory control. Contains several parameters that control local memory interface operation:
RM (bit 2)
- DRAM refresh mode
RR (bits 3-4)
- DRAM refresh rate
T (bit 5)
- Transparency enable
W (bits 6-7)
- Window violation detection mode
- PixBlt horizontal direction
PBH (bit 8)
PBV (bit 9)
- PixBlt vertical direction
PPOP (bits 10-14) - Pixel processing operation select
CD (bit 15)
- Cache disable
Bits 0 and 1 are reserved

CONVDPt

COOOO140h

Destination pitch conversion factor. Used during XV to linear conversion of a destination memory address.

CONVSPt

COOOO130h

Source pitch conversion factor. Used during XV to linear conversion
of a source memory address.

Implied graphics operands

6-5

I/O Registers - Summary

Table 6-1. I/O Registers Summary (Continued)
Local Memory Interface Registers (Continued)
Description

Address
COOO0160h

Plane mask register. Selectively enables/disables the various planes
in the bit map of a display system in which each pixel is represented by
multiple bits.

PSIZEt

COOO0150h

Pixel size register. Specifies the pixel size (in bits).
sizes include 1, 2, 4, 8, and 16 bits.

REFCNT

COOO01FOh

Refresh count register. Generates the addresses output during DRAM
refresh cycles and counts the intervals between successive DRAM refresh
cycles:
RINTVL (bits 2-7)
- Refresh interval counter
ROWADR (bits 8-15) - Row address
Bits 0 and 1 are reserved

Address

Possible pixel

Interrupt Control Registers
Description

INTENB

COOO0110h

Interrupt enable. Contains the interrupt mask used to selectively
enable/disable the three internal and two external interrupts:
X1 E (bit 1 )
- External interrupt 1 enable
X2E (bit 2)
- External interrupt 2 enable
HIE (bit 9)
- Host interrupt enable
DIE (bit 10)
- Display interrupt enable
WVE (bit 11) - Window violation interrupt enable
Bits 0, 3 through 8, and 12 through 15 are reserved

INTPEND

COOO0120h

Interrupt pending. Indicates which interrupt requests are currently
pending:
X1 P (bit 1)
- External interrupt 1 pending
- External interrupt 2 pending
X2P (bit 2)
- Host interrupt pending
HIP (bit 9)
DIP (bit 10)
- Display interrupt pending
WVP (bit 11) - Window violation interrupt pending
Bits 0, 3 through 8, and 12 through 15 are reserved

Address

DPYADR

COOO01EOh

Display address. Counts the number of scan lines output between
successive screen refresh cycles and contains the source of the row and
column addresses output during a screen refresh cycle:
- Scan line counter
LNCNT (bits 0-1 )
SRFADR (bits 2-15) - Screen refresh address

DPYCTL

COOOO080h

Display control. Contains several parameters that control video timing
signals:
HSD (bit 0)
- Horizontal sync direction
DUDATE (bits 2-9) - Display address update
ORG (bit 10)
- Screen origin select
SRT(bit11)
- VRAM serial-register transfer enable
SRE (bit 12)
- Screen refresh enable
DXV (bit 13)
- Disable external video
NIL (bit 14)
- Noninterlaced video enable
ENV (bit 15)
- Enable video
Bit 1 is reserved.

DPYINT

COOOOOAOh

Display interrupt. Specifies the next scan line that will cause a display
interrupt request.

Video Timing and Screen Refresh Registers

Implied graphiCS operands

6-6

Description

I/O Registers - Summary

Table 6-1. I/O Registers Summary (Concluded)
Video Timing and Screen Refresh Registers (Continued)

Address

DPYSTRT

COOOOO90h

Display start address. Provides control of the automatic memory-toregister cycles necessary to refresh a screen:
lCSTRT (bits 0-1) - Specifies the number of scan lines to
be displayed between screen refreshes
SRSTRT (bits 2-15)- Starting screen-refresh address

Description

DPYTAP

COOOO1BOh

Display tap point address. Contains a VRAM tap point address output
during shift register transfer cycles.

HCOUNT

COOOO1COh

Horizontal count. Counts the number of VClK periods per horizontal
scan line.

HEBlNK

COOOOO10h

Horizontal end blank. Designates the endpoint for horizontal blanking.

HESYNC

COOOOOOOh

Horizontal end sync.
interval.

HSBlNK

COOOOO20h

Horizontal start blank. Specifies the starting point of the horizontal
blanking interval.

HTOTAl

COOOOO30h

Horizontal total. Specifies the total number of VClK periods per horizontal scan line.

VCOUNT

C00001 DOh

Vertical count. Counts the horizontal scan lines in a video display.

VEBlNK

COOOOO50h

Vertical end blank. Specifies the endpoint of the vertical blanking interval.

Specifies the endpoint of the horizontal sync

VESYNC

COOOOO40h

Vertical end sync. Specifies the endpoint of the vertical sync pulse.

VSBlNK

COOOOO60h

Vertical start blank. Specifies the starting point of the vertical blanking interval.

VTOTAl

COOOOO70h

Vertical total. Specifies the value of VCOUNT at which the vertical
sync pulse begins.

6.3.1 Host Interface Registers
Five I/O registers are dedicated to host interface communications, allowing the
TMS34010 to:
•

Directly transfer status messages or command information

•

Indirectly transfer large blocks of data through local memory

•

Receive interrupt requests from a host processor

•

Transfer interrupt requests to a host processor

The ability to indirectly transfer large blocks of data makes the host interface
extremely flexible. For example, a host can transfer blocks of commands to the
TMS34010, can halt the TMS3401 0 temporarily to download a new program
for the TMS3401 0 to execute, or can read blocks of graphics data generated
by the TMS3401 O.
The host interface registers occupy five TMS3401 0 register locations, and are
typically mapped into four consecutive 16-bit locations in the memory or I/O
address space of the host processor. The host processor accesses the
6-7

I/O Registers - Summary

HSTCTLL and HSTCTLH registers as the eight LSBs and eight MSBs, respectively, of a single location (the HSTCTL register).
The HSTCTL (host control) register controls functions such as the transfer of
interrupt requests and 3-bit status codes between a host processor and the
TMS34010. These requests are typically used by software to coordinate the
transfer of large blocks of data through TMS34010 local memory. The
HSTCTL register also allows the host to flush the instruction cache, halt
TMS34010 execution, and transmit nonmaskable interrupt requests to the
TMS34010.
The host processor uses the remaining three host interface registers to indirectly access selected data blocks within TMS34010 local memory. The
HSTADRL and HSTADRH registers contain a 32-bit address that points to the
current word location in memory. The HSTDATA register buffers data transferred to and from the memory under control of the host processor. The host
interface can be programmed to automatically increment the address pointer
following each transfer, providing the host with rapid access to a block of sequential locations.

6.3.2 Local Memory Interface Registers
Six of the I/O registers support local memory interface functions such as:
•

Frequency of DRAM refresh cycles

•

Type of DRAM refresh cycles

•

Pixel size

•

Color plane masking

•

Various pixel access control parameters

6.3.3 Interrupt Interface Registers
Two I/O registers monitor and mask interrupt requests to the TMS34010.
These include two external and three internal interrupts. External interrupt requests are transmitted to the TMS3401 0 via input pins LlNT1 and LlNT2. The
TMS34010 can be programmed to generate an internal interrupt request in
response to any of the following conditions:

•

Window violation - an attempt is made to write a pixel to a location inside or outside a specified window, depending on the selected windowing mode.

•

Host interrupt - the host processor sets the INTIN interrupt request bit
in the HSTCTL register.

•

Display interrupt - the specified line number in a frame is displayed on
the monitor.

A nonmaskable interrupt occurs when the host processor sets the NMI bit in
the HSTCTL host interface register. Reset is controlled by a dedicated pin.

6-8

I/O Registers - Summary

6.3.4 Video Timing and Screen Refresh Registers
Fifteen 110 registers support video timing and screen refresh functions. The
TMS34010's on-chip CRT timing generator creates the sync and blanking
signals used to drive the CRT monitor in a bit-mapped display system. The
timing of these signals can be controlled through the appropriate 110 registers,
allowing the TMS3401 0 to support various screen resolutions and interlaced
or non interlaced video.
The TMS3401 0 directly supports VRAMs (such as the TMS4461) by generating the memory-to-register cycles necessary to refresh the screen of a CRT
monitor. Programmable features include the locations in memory to be displayed on the monitor, as well as the number of horizontal scan lines displayed
between individual screen-refresh cycles.
The TMS34010 can optionally be programmed to synchronize to externally
generated sync signals. This permits TMS34010-created graphics images to
be superimposed upon externally-created images. This external sync mode
can also be used to synchronize the video timing of two or more TMS3401 0
devices in a multiple-TMS3401 0 display system.

6-9

I/O Registers - Alphabetical Listing

6.4 Alphabetical listing of I/O Registers
The remainder of this section describes the I/O registers individually; they are
listed in alphabetical order. Fields within each register are identified and
functions associated with each register are discussed.
Bits within I/O registers that are identified as reserved are not used by the
TMS34010. When read, a reserved bit returns the last value written to it. No
control function, however, is affected by this value. All reserved bits are
loaded with Os at reset. A good software practice is to maintain Os in these
bits.

6-10

Memory Control Register

CONTROL

COOOOOBOh

Address

15 14

ICDI

Fields

0-1
2
3-4
5
&-7

8
9
10-14
15

•

IPBVlpBH I

Name

Bits

Description

12
PPOP

6
W

5
T

3
RR

IRM I reserved I

Function

Reserved

Not used

DRAM refresh mode

D RAM refresh rate

Pixel transparency enable

W
PBH

Window violation detection mode

PBV

PixBlt vertical direction

PixBlt horizontal direction

PPOP

Pixel processing operation select

Instruction cache disable

The CONTROL register contains several control parameters used to configure local memory interface operation.
RM (DRAM refresh mode, bit 2)
The RM bit selects the type of DRAM refresh cycle to be performed. Depending on the value of this bit, the TMS34010 performs each DRAMrefresh cycle as either a RAS-only cycle or as a CAS-before-AAs cycle.
DRAMs and VRAMs that rely on the TMS3401 0 to generate an 8-bit row
address during a refresh cycle typically use the RAS-only refresh cycle, while
those that generate their own 9-bit row address internally use the CAS-before- RAS refresh cycle.

RM
0
1

•

Description
Selects RAS-only refresh cycle
Selects ~-before-RAS refresh cycle

RR (DRAM refresh rate, bits 3 and 4)
The RR field controls the frequency of DRAM refresh cycles.
The
TMS34010 automatically generates DRAM refresh cycles at regular intervals. The duration of the interval is specified by the value of RR. If required,
DRAM refreshing can be disabled by setting RR to the appropriate value.
The initial value of RR after reset is 002. No DRAM refresh cycles are performed while the TMS3401 0 RESET signal is active.

6-11

CONTROL

Memory Control Register

RR
00
01
10
11

•

Description
Refresh every 32 local clock periods
Refresh every 64 local clock periods
Reserved code
No DRAM refreshing

T (Pixel transparency, bit 5)
The T bit enables or disables the pixel attribute of transparency. When
transparency is enabled, a value of 0 resulting from a pixel operation on
source and destination pixels is inhibited from overwriting the destination
pixel. In the case of a replace operation (PPOP = O), a source pixel value
of 0 is inhibited from overwriting the destination pixel. Disabling transparency allows a pixel value of 0 to be written to the destination.

•

T
0

Disable transparency

Enable transparency

Effect

W (Window checking, bits 6 and 7)
The W field selects the course of action to be taken when a pixel operation
will cause a pixel to be written to a location lying either inside or outside the
specified window limits. Window checking applies only to attempts to write
to pixel locations defined by XV addresses; writes to pixel locations defined
by linear memory addresses are not affected. Nonpixel data writes are not
affected.
Description

00
01
10
11

No pixel writes are inhibited. and no interrupt requests are generated
Generate interrupt request on attempt to write to pixel lying inside window.
and inhibit all pixel writes
Generate interrupt request on attempt to write to pixel lying outside window
Inhibit pixel writes outside window. but do not request interrupt

A request for a window violation interrupt can occur when W=012 or
W=102. The WVP bit in the INTPEND register is set to 1 to indicate that a
window violation has occurred. This in turn causes the TMS3401 0 to be
interrupted if the WVE bit in the INTENB register and the status IE bit are
set to 1.

•

PBH (PixBlt horizontal direction, bit 8)
The PBH bit determines the horizontal direction (increasing X or decreasing
X) of pixel processing for the following instructions:
PIXBLT XV,XV
PIXBLT L,XV

6-12

Memory Control Register

CONTROL

PIXBLT XY,L
PIXBLT L,L

•

PBH
0

Increment X (move from left to right)

Decrement X (move from right to leh)

Effect

PBV (PixBlt vertical direction. bit 9)
The PBV bit determines the vertical direction (increasing Y or decreasing
Y) of pixel processing for the following instructions:
PIXBLT
PIXBLT
PIXBLT
PIXBLT

XY,XY
L,XY
XY,L
L,L

•

PBV
0

Increment Y (move from top to bottom)

Decrement Y (move from bottom to top)

Effectt

Default screen origin assumed

PPOP (Pixel processing operation. bits 10-14)
The PPOP field selects the operation to be performed on the source and
destination pixels during a pixel operation. The following 16 PPOP codes
perform Boolean operations on pixels of 1, 2, 4, 8, and 16 bits.
PPOP
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111

Description

Operation
S~D

SAND D ~
S AND IT .....
O .....
S OR IT .....
S XNOR D ~
IT .....
S NOR D .....
S OR D .....
D .....
S XOR D .....
SAND D .....
1 .....
S OR D .....
S NAND D .....
S .....

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

Replace destination with source
AND source with destination
AND source with NOT destination
Replace destination with Os
OR source with NOT destination
XNOR source with destination
Negate destination
NOR source with destination
OR source with destination
No change in destination t
XOR source with destination
AND NOT source with destination
Replace destination with 1s
OR NOT source with destination
NAND source with destination
Replace destination with NOT source

Although the destination array
memory cycles still occur.

not changed by this operation,

The following six PPOP codes perform arithmetic operations on 4-, 8-, and
16-bit pixels (but not 1 or 2 bits).

6-13

Memory Control Register

CONTROL

PPOP

Operation
D + S .... D
10000
10001 ADDS(D,S) .... D
D - S .... D
10010
10011 SUBS(D,S) .... D
MAX(D,S) .... D
10100
MIN(D,S) .... D
10101

Description
Add source to destination
Add S to D with saturation
Subtract source from destination
Subtract S from D with saturation
Maximum of source and destination
Minimum of source and destination

PPOP codes 101102 through 111112 are reserved.
Standard addition and subtraction allow the result of the operation to overflow. However, add-with-saturation and subtract-with-saturation (ADDS
and SUBS) do not allow overflow or underflow. In cases in which addition
would allow an overflow, ADDS produces a result whose value is all 1s. In
cases in which subtraction would allow an underflow, SUBS produces a
'result whose value is all Os.

•

CD (Cache disable, bit 15)
The CD bit selectively enables or disables the instruction cache.
CD

Effect

0
1

Enable instruction cache
Disable instruction cache

When the cache is disabled, cache contents (including data, P flags, SSA
registers, and so on) remain undisturbed. While the cache remains disabled,
all instructions are fetched from memory rather than cache. When the cache
is subsequently enabled, its previous state (before it was disabled) is restored. The instructions retained within the cache are once again available
for execution.

6-14

Destination Pitch Conversion Factor

Address

C0000140h

I
Description

CONVDP

15 14

CONVDP

CONVDP is a full 16-bit register that contains a control parameter used
during execution of a pixel operation instruction. CONVDP is used with:
•

XY addressing

•

Window clipping

•

PIXBLTs or FILLS (except for PIXBLT L,L) that process pixels from
the bottom of the array to the top (PBV=1 )

CONVDP is calculated as the result of an LMO instruction whose input
operand is the destination pitch value in register B3 (DPTCH). The following assembly code calculates the CONVDP value.
LMO B3,AO
MOVE AO,@CONVDP,O

; Convert DPTCH value
; Place result in CONVDP register

In this example, AO is used as a scratch register. Constant CONVDP has
the value OC0000140h, and the size of Field 0 is 16 bits.
TMS34010 internal hardware uses the CONVDP value during XY -to-linear
conversion of a destination address. PIXBLT and FILL instructions which
specify the destination address in XY format use the DPTCH and CONVDP
values to convert the XY coordinates to a linear memory address before
actually beginning the pixel block move. During a PIXBLT or FILL instruction that requires preclipping of the destination array in the Y direction,
the TMS34010 uses the CONVDP value to calculate the effect of the
clipped starting Y coordinate on the starting linear address of the destination array. When a PIXBLT instruction's starting Y coordinate is specified
to lie in one of the lower two corners of the destination array (when
PBV=1), the TMS34010 uses CONVDP to calculate the linear address
corresponding to the specified starting coordinates.
The value contained in the five LSBs of CONVDP should be the 1 s complement of 1092(DPTCH). When an XY address is specified for the destination, DPTCH must bea power of two; thus, 1092(DPTCH) is an integer.
During XY-to-linear conversion, the product of the Y value and the destination pitch is calculated by shifting Y left by 1092(DPTCH).
One instruction, the PIXBLT XY,L instruction, specifies the destination address in linear format but also requires DPTCH to be a power of two. This
restriction is necessary when the PBV bit is set to 1.

6-15

CONVSP

Address

Source Pitch Conversion Factor

C0000130h
15 14

I
Description

CONVSP

CONVSP is a full 16-bit register that contains a control parameter used
during execution of a pixel operation instruction. CONVSP is used with:
•

XY addressing

•

Window clipping

•

PIXBLTs or FILLS (except for PIXBLT L,L) that process pixels from
the bottom of the array to the top (PBV=1)

CONVSP is calculated as the result of an LMO instruction whose input
operand is the source pitch value in register B1 (SPTCH). The following
assembly code calculates the CONVSP value
LMO Bl,AO
MOVE AO,@CONVSP

; Convert SPTCH value
; Place result in CONVSP register

In this example, AO is used as a scratch register. Constant CONVSP has the
value OC0000130h, and the size of Field 0 is 16 bits.
TMS34010 internal hardware uses the CONVSP value during XY -to-linear
conversion of a source address. PIXBLT and FILL instructions which specify the source address in XY format use the SPTCH and CONVSP values
to convert the XY coordinates to a linear memory address before actually
beginning the pixel block move. During a PIXBLT or FILL instruction that
requires preclipping of the destination array in the Y direction, the starting
source address is modified to accommodate the resulting changes to the
starting destination address .. When a PIXBLT instruction's starting Y coordinate is specified to lie in one of the lower two corners of the destination
array (when PBV=1), the TMS3401 0 uses CONVSP to calculate the linear
address at the corresponding corner of the source array.
The value contained in the five LSBs of CONVSP should be the 1s complement of 1092(SPTCH). When an XY address is specified for the source,
SPTCH must be a power of two; thus, 1092(SPTCH) is an integer. During
XY -to-linear conversion, the product of the Y value and the source pitch is
calculated by shifting Y left by 1092(SPTCH).
Two instructions that specify the source address in linear format also require
SPTCH to be a power of two. This is necessary when window clipping is
required during execution of either of the following instructions:
•
•

PIXBLT B,XY
PIXBLT L,XY

It is also necessary when either of these two instructions is executed and
the PBV bit in the CONTROL register is set to 1. If PBV=O and window
clipping is disabled, or if window clipping is enabled but the specified array
does not require preclipping in the Y dimension, CONVSP is not used, and
SPTCH is not required to be a power of two.
6-16

Display Address Register

Address

DPYADR

C00001EOh
15 14

I
Fields

Description

•

SRFADR
Bits

Name

0-1
2-15

LNCNT

Scan line counter

SRFADR

Screen refresh address

210

I LNCNT I

Function

The 16-bit DPYADR register contains two separate counters that control
the generation of screen-refresh cycles. A screen-refresh cycle transfers the
video data for a new scan line to the VRAMs' serial data registers.

LNCNT (Scan line counter, bits 0 and 1)
LNCNT counts the number of scan lines output to the screen between successive screen-refresh cycles. Providing explicit control over the line count
permits the implementation of systems that do not reload the VRAMs' internal serial data register on every horizontal scan line. The two-bit LNCNT
field is loaded from the two-bit LCSTRT field of the DPYSTRT register at
the end of each screen-refresh cycle. The value loaded determines whether
the next screen-refresh cycle occurs after 1, 2, 3 or 4 scan lines:
When LCSTRT = 0, a screen-refresh cycle occurs after every line.
When LCSTRT = 1, 2 or 3, a screen-refresh cycle occurs after every
2,3 or 4 lines, respectively.

•

SRFADR (Screen refresh address, bits 2-15)
SRFADR is the source of the row and column addresses output during a
screen-refresh cycle. The 14 bits of SRFADR are output as logical address
bits 10-23 during screen-refresh cycles.
During row address time,
DPYADR4-DPYADR15 are output on LADo-LAD11, and Os are output on
the remaining LAD pins (except as modified by the contents of the DPYTAP
register). During column address time, DPYADR2-DPYADR7 are output
on LAD6-LAD11 and Os are output on the remaining LAD lines. Following
the completion of each screen-refresh cycle, the value in SRFADR is decremented by the amount indicated in the DUDATE field of the DPYCTL register.
The following diagrams illustrate the mapping of bits to LADo-LAD15 from
1)
2)

The logical address as seen by the programmer and
The bits of the DPYADR register

The bits of a 32-bit logical address are numbered 0 to 31, beginning with
the LSB. The 14 MSBs of DPYADR, shown in Figure 6-2, are output as
logical address bits 10-23 during a screen-refresh cycle. DPYADR2 corresponds to logical address bit 10, DPYADR3 corresponds to logical address
bit 11, and so on.

6-17

DPYADR

Display Address Register

OPVADR
Logical
Adar. .

15 14 18 12 11 10

SRFADR

iLNCNT

I
I

I
I
128 22 21 20 19 18 17 18 15 14 18 12 11 10

Figure 6-2. Correlation Between SRFADR and Logical Address
Bits

Figure 6-3 shows the mapping of logical addresses to LAOQ-LA015 during
the row and column address times of the cycle. The symbol xx indicates
status information output with the row and column addresses.
LAD Pin Number

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Logical Row
Address Bits
Corresponding
DPYADR bits
Logical Column
Address Bits
Corresponding
DPYADR bits

xx 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Row

15 14 13 12 11 10 9 8 7 6 5 4
xx xx 29 28 27 14 13 12 11 10 9 8 7 6 5 4

7 6 5 4 3 2

Address
Time

Column
Address
Time

Figure 6-3. Correlation Between DPYADR Bits and Row/Column
Addresses

A board designer typically selects eight consecutive address lines from
LAOQ-LA011 to connect to the multiplexed address inputs of the VRAMs.
For example, by selecting the eight lines LA02-LA09, bits 14-21 of the
logical address become the row address bits output to the RAMs, and bits
6-13 of the logical address become the column address bits. This means
that during a screen-refresh cycle, bits 6-13 of OPYAOR become the row
address bits output to the RAMs, and bits 4-5 of OPYAOR become the two
MSBs of the tap point address.

6-18

Display Control Register

Address

DPYCTL

C0000080h

Bit
Assignments

DUDATE

Fields

Bits

Name

0 HSD

Description
•

210
I Res IHSDI

Function
Horizontal sync direction

Reserved

2-9
10
11
12
13
14
15

DUDATE

Display address update

ORG

Screen origin select

Not used

SRT

Shift register transfer enable

SRE

Screen refresh enable

DXV

Disable external video

NIL

Noninterlaced video enable

ENV

Enable video

The DPYCTl register contains several parameters that control video timing
signals and serial-register transfer cycles using VRAMs.
HSD (Horizontal sync direction. bit 0)
The HSD bit controls the direction (input or output) of the HSYNC (horizontal sync) pin when the TMS3401 0 is in external video mode (DXV=O).
If HSD=O, HSYNC is configured as an input, the same as VSYNC. In this
case, the on-chip horizontal sync interval begins when either:
The start of the external horizontal sync pulse input at the HSYNC pin
is detected, or
HCOUNT = HTOTAl,
whichever condition occurs first. VSYNC and HSYNC are configured as inputs or outputs according to the values of the HSD and DXV bits:

HSD

UXV

ti!ViiiC

0
0
1
1

0
1
0
1

Input

Output

Input

V!Vlire

Undefined

When VSYNC and HSYNC are both configured as inputs, the on-chip vertical
sync interval begins when any of the following conditions occur:
The start of the external vertical sync pulse input at the VSYNC pin is
detected, or
VCOUNT=VTOTAl, and the start of the horizontal sync pulse input
at the HSYNC pin is detected, or
VCOUNT=VTOTAl and HCOUNT=HTOTAL.

6-19

Display Control Register

DPYCTL

When VSYNC is an input and HSYNC is an output, the vertical sync interval
begins when either the first or third of the listed conditions occurs.

•

DUDATE (Display update amount. bits 2-9)
The DUDATE field indicates the amount by which the SRFADR field in the
DPYADR register is incremented (if ORG=O) or decremented (ORG=1)
following completion of each memory-to-register cycle used to refresh the
screen. DUDATE is loaded with a value containing seven Os and a single
1. The 1 indicates the bit position at which DPYADR is to be incremented
(or decremented if ORG=1).
DUDATE

Increment
Size

00000000
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000

0
1
2
4
8
16
32
64
128

The increment size is undefined when more than one bit in the DUDATE
field is a 1. When interlaced scan mode is enabled. SRFADR is incremented/decremented by half the value indicated in DUDATE at the start of a
vertical blanking interval preceding the start of an even field, just after
DPYADR2-DPYADR15 have been loaded from DPYSTRT2-DPYSTRT15.
For non interlaced scanning, DUDATE is programmed to increment the
screen address by one scan line. For interlaced scanning, DUDATE is programmed to increment the screen address by two scan lines. Larger increments are typically not used since screen-refresh cycles do not occur more
often than once per active scan line.
•

ORG (Screen origin select. bit 10)
The ORG bit controls the origin of the screen coordinate system.
ORG

Effect

XY coordinate origin located in upper left corner of screen

XY coordinate origin located in lower left corner of screen

If ORG=O then DPYADR is updated by being incremented by the value in
the DUDATE field. If ORG=1 then DPYADR is updated by being decremented by the value in the DUDATE field. Unless explicitly stated otherwise, the discussion in this document assumes that the default origin
(ORG=O) is used.

6-20

Display Control Register

•

DPYCTL

SRT (Shift-register-transfer enable, bit 11)
The SRT bit enables conversion of an ordinary pixel access into a VRAM
serial-register transfer cycle.
SRT

Effect

Pixel access cycles occur normally
Pixel access cycles are converted into
VRAM shift-register-transfer cycles

The TMS34010 instruction set includes several instructions (DRAV, PIXT,
LINE, FILL, and PIXBLT) that operate specifically on pixels. By default.
SRT=O and memory accesses performed during accesses of pixel data are
the usual memory read and write cycles. When SRT=1, however, accesses
of pixel data are converted to shift-register-transfer cycles:
A pixel read cycle is converted to a memory-to-register cycle
A pixel write cycle is converted to a register-to-memory cycle
This register-transfer cycle is performed under explicit program control, as
opposed to the screen-refresh cycles enabled by the SRE bit. which are automatically generated at regular intervals.
Uses of the SRT bit include bulk initialization of the entire VRAM array; the
entire screen can be cleared to a specified background color in only 256
memory cycles. (While the TMS4461 has this capability, not all VRAMs
support this function.) Only pixel accesses are affected by the state of the
SRT bit. Instruction fetches and non-pixel data accesses are not altered in
any way.

•

SRE (Screen-refresh enable, bit 12)
The SRE bit enables automatic screen refreshing. Screen refreshes are performed by means of the VRAM memory-to-register cycles which the
TMS34010 performs automatically during selected horizontal blanking intervals. The frequency of screen-refresh cycles and the generation of the
addresses output during these cycles are programmed by means of the
DPYSTRT and DPYCTL registers.
SRE

0
1

Effect
Disable screen refresh
Enable screen refresh

Changing the value of the SRE bit affects screen refreshes with the start of
the next horizontal blanking interval. When SRE changes from 0 to 1, the
first screen-refresh cycle occurs at the start of the next horizontal blanking
level. When SRE changes from 1 to 0, screen-refresh cycles are disabled
beginning at the start of the next horizontal blanking level.

6-21

Display Control Register

DPYCTL

•

DXV (Disable external video, bit 13)
The DXV bit selects between internally generated or externally generated
video timing.
DXV

0
1

Effect
Selects external video source
Selects internally generated video timing

When DXV=O, the TMS3401 0 video timing circuitry is programmed to lock
onto an external video source. The VSYNC pin is configured as an input and
is connected to an external vertical sync signal. If HSD=O, HSYNC is also
configured as an input and is connected to an external horizontal sync signal.
When DXV=1, the TMS3401 0 generates its own video timing, according to
the values loaded into the video timing registers. The HSYNC and VSYNC
pins are configured as outputs, and provide the horizontal and vertical sync
signals required to drive the video monitor.

•

NIL (Noninterlaced video enable, bit 14)
The NIL bit selects between an interlaced or a non interlaced display. The
video timing signals output by the TMS3401 0 are modified according to this
selection. The timing differences between interlaced and non interlaced
displays are described in Section 9.
NIL

•

Effect

Selects interlaced video timing

Selects non interlaced video timing

ENV (Enable video, bit 15)
The ENV bit enables or disables the video display. The display remains
blanked when ENV=O. During this time, the signal output at the BLANK pin
is forced to remain at its active-low level throughout the frame, and setting
of the DIP (display interrupt) bit in the INTPEND register is inhibited. (If
DIP is already set at the time the ENV is changed from 1 to 0, DIP remains
set until explicitly cleared.) When ENV=1, the video display is enabled. The
BLANK output signal is controlled according to the parameters contained in
the video timing registers, and the DIP bit becomes set when the condition
VCOUNT = DPYINT occurs.
ENV

6-22

Effect

Blank entire screen

Enable video

Display Interrupt Register

Address

COOOOOAOh
15 14

I
Description

DPYINT

The DPYINT register designates the next scan line at which a display interrupt will be requested. This register facilitates the coordination of software activity with the refreshing of selected horizontal lines on the screen
of a video monitor.
The contents of DPYINT are compared to the VCOUNT register. When
VCOUNT = DPYINT, a display interrupt is requested and the DIP bit in the
INTPEND register is set to 1. This coincides with the start of the horizontal
blanking interval that marks the end of the line designated by the value
contained in DPYINT.
For split-screen applications, a new value can be loaded into the DPYADR
register immediately following detection of the 0-to-1 transition of DIP.
The new DPYADR value will not affect the line that immediately follows the
end of the current horizontal blanking interval, but will affect the next line.
The details of this timing are as follows. A screen-refresh cycle may be
scheduled to occur at the start of the same horizontal blanking interval
during which DIP becomes set. At the end of the screen-refresh cycle, the
screen-refresh address in the DPYADR register will be automatically incremented. Requests for screen-refresh cycles have a higher priority than requests for cycles initiated by the on-chip processor. Hence, if the processor
loads a new value into DPYADR immediately following detection of DIP's
transition from 0 to 1, the value will become the address used for the next
screen-refresh cycle, which cannot occur before the next horizontal blanking interval. Between the time that DIP becomes set to 1 and the completion of the next screen-refresh cycle at least one full scan line later, the
DPYADR register is guaranteed not to be incremented. Its contents will
change during this interval only if it is loaded with a new value under explicit program control. The display interrupt is disabled when the ENV bit
in the DPYCTL register is O.

6-23

DPYSTRT

Address

Display Start Address Register

C0000090h
15 14

I
Fields

Description
•

SRSTRT
Bits

Name

0-1
2-15

LCSTRT

Starting line count

SRSTRT

Starting screen-refresh address

I LCSTRTI

Function

The DPYSTRT register contains two parameters that control the automatic
memory-to-register cycles necessary to refresh the screen.
LCSTRT (Starting line count bits 0 and 1)
lCSTRT is a two-bit code designating the number of scan lines to be displayed between screen refreshes.
LCSTRT
Value

00
01
10
11

Scan Lines
Between
Refresh
Cycles

1
2
3
4

lCSTRT is loaded into the lNCNT field of the DPYADR register at the end
of each screen-refresh cycle. lCSTRT is also loaded into lNCNT at the start
of the last horizontal blanking interval preceding the first active scan line of
a new frame.
•

SRSTRT (Starting screen-refresh address, bits 2-15)
The 14-bit SRSTRT field contains the starting address loaded into the
DPYADR register at the start of each frame. Its value identifies the start of
the region of the graphics bit map to be displayed on the screen. SRSTRT
is loaded into the SRFADR field of the DPYADR register at the beginning
of each vertical blanking interval. (loading occurs coincides with the start
of the horizontal blanking interval at the end of the last active scan line in
the frame.)
The sense of the SRSTRT value depends on the value of the ORG (origin
select) bit in the DPYCTl register. When ORG =0, SRSTRT is loaded with
the 1'5 complement of the starting address. When ORG=1, SRSTRT is
loaded with the unmodified starting address. Regardless of the value of the
ORG bit, the starting address points to the location in memory of the first
pixel output to the screen during each frame. For a typical CRT display, the
first pixel of each frame is output to the top left corner of the screen. Refer
to the description of the DPYADR register for mOre information on the
generation of screen-refresh addresses.

6-24

Display Tap Point Address Register

Address

C00001BOh
15 14

IReserved I

Fields

Description

DPYTAP

Bits

Name

0-13
14-15

DPYTAP

Display tap point address

Reserved

Not used

Function

The DPYTAP register contains a VRAM tap point address output during a
screen-refresh (memory-to-register) cycle. (The contents of DPYTAP are
not output during a serial-register transfer initiated under program control
while the SRT bit in the DPYCTL register is set to 1.) During a screenrefresh cycle, the 16 bits of the DPYTAP register are bitwise-ORed with the
value output at the LAD0-LAD15 pins during the column address time.
DPYTAP bit 0 is ORed with LADO, DPYTAP bit 1 is ORed with LAD1, and
so on. This means that the column address output during the cycle is the
OR of bits 2-7 of DPYADR and bits 0-15 of DPYTAP.
One application of the DPYTAP register is to permit horizontal panning of
the screen over a frame buffer that is wider than the screen. A DPYTAP
value of 0 locates the scree~ at its leftmost position within the frame buffer.
Incrementing DPYTAP causes the display to pan to the right through the
frame buffer.
DPYTAP is typically used to alter (set to a value other than all Os) only
those column address bits of the SRFADR field of DPYADR that are never
incremented. For instance, given a VRAM that requires an 8-bit column
address, assume that SRFADR alternately sets the two MSBs of the column
address to 002, 012, 102, and 112. In this case, DPYTAP should contain
1 s only in the bit positions corresponding to the six LSBs of the column
address.

6-25

HCOUNT

Address

Horizontal Count Register

C00001 COh
15 14

I
Description

HCOUNT

The HCOUNT register is a 16-bit counter used in the generation of the
horizontal sync and blanking signals. HCOUNT is incremented on the failing edge of the video input clock, and is used to count the number of video
clock periods per horizontal scan line. To generate horizontal sync and
blanking signals, the value of HCOUNT is compared to the value of the four
horizontal timing registers: HESYNC, HEBLNK, HSBLNK, and HTOTAL.
When external sync mode is disabled and the value in HCOUNT = HTOTAL, HCOUNT is reset to 0 on the next VCLK falling edge and the HSYNC
output is driven active low. HCOUNT is also reset to 0 if the external sync
mode is enabled and the input signal HSYNC is driven low.
Two separate, asynchronous elements of the TMS34010 logic can access
the HCOUNT register:
•

The internal processor, which runs synchronously to local clocks
LCLK1 and LCLK2, can access HCOUNT as an 1/0 register.

•

The video timing control logic, which runs synchronously to the video
clock VCLK, increments and clears HCOUNT in generating the sync
and blanking signals.

No synchronization between these two subsystems is provided, and
HCOUNT can only be reliably read or written to while VCLK is held at the
logic-high level. HCOUNT is typically not read or written to except during
chip test.

6-26

Horizontal End Blank Register

Address

C0000010h
15 14

I
Description

HEBLNK

The HEBLNK register is used during the generation of the blanking signal
output to the video monitor. The 16-bit value loaded into HEBLNK is
compared to HCOUNT, and designates the point at which the horizontal
blanking interval ends. The blanking signal output at the BLANK pin is a
composite of the internal horizontal and vertical blanking signals. When the
value in HCOUNT = HEBLNK, the BLANK output is driven inactive high
unless vertical blanking is currently active. Most video monitors require
HEBLNK to be set to a value that is less than the value in HSBLNK, but
greater than the value in HESYNC.

6-27

HESVNC

Address

Horizontal End Sync Register

COOOOOOOh
15 14 13

I
Description

HESYNC

The HESYNC register is used during generation of the horizontal sync signal output to the video monitor. The 16-bit value loaded into HESYNC
determines the point at which the horizontal sync pulse ends. When the
value in HCOUNT = HESYNC, the signal output from the HSYNC pin is
driven inactive high to signal the end of the horizontal sync interval. Typical
monitors require that HESYNC be set to a value less than the value contained in the HEBLNK register. (However, the HESYNC value is not required to be less than the HEBLNK value.) The minimum value of HESYNC
is O.
When external video is enabled and the HSYNC pin is configured as an input, HESYNC should be loaded with a value that ensures that the condition
HCOUNT = HESYNC occurs after the external HSYNC signal has gone inactive-high, but before HSYNC goes active low again. For example, a good
HESYNC value might be the average of the values in HEBLNK and
HSBLNK.

6-28

Horizontal Start Blank Register

Address

C0000020h
15 14

I
Description

HSBLNK

The HSBLNK register is used during generation of the blanking signal output to the video monitor. The 16-bit value in HSBLNK is compared to
HCOUNT, and designates the point at which the horizontal blanking interval begins. The blanking signal output at the BLANK pin is a composite of
the internal horizontal and vertical blanking signals. When the condition
HCOUNT = HSBLNK occurs, the BLANK output is driven from its inactive-high level to its active-low level (unless it is already low due to vertical
blanking being active).
Several internal events coincide with the start of horizontal blanking. First,
when a screen-refresh cycle is programmed to occur during a particular
horizontal scan line, a request for the cycle is sent to the memory controller
at the beginning of the horizontal blanking interval that occurs at the end
of the line. Second, if a display interrupt request is programmed to occur
during a particular horizontal scan line, the request is generated at the start
of horizontal blanking. Typical monitors require that HSBLNK be set to a
value that is less than the value in HTOTAL, but greater than the value in
HEBLNK.

6-29

HSTADRH

Address

Host Interface Address Register, High Word

COOOOOEOh
15 14

I
Description

HSTADRH

The HSTADRH register contains the 16 MSBs of a 32-bit pointer address;
the 16 LSBs are contained in HSTADRL. The contents of HSTADRL and
HSTADRH are concatenated to form a single 32-bit address during an indirect access by a host processor. The pointer address can be accessed by
both the host processor and the TMS3401 O. The host accesses the pointer
address through two 16-bit host interface registers that are mapped into the
host's memory or I/O address space.
The four LSBs of the 32-bit pointer address are forced to 0 to point to an
even word boundary in memory. If the address pointer is incremented past
the largest word address in memory, it will wrap around to the lowest address (all Os).
When you use the HSTADRH and HSTADRL registers to read data indirectly from the host, be sure that you access them in the correct order. If
LBL=O, HSTADRH should be written last. If LBL=1, HSTADRL should
be written last.
Note:
When the TMS34010's on-chip processor writes to HSTADRH or
HSTADRL, the referenced data is not automatically read into
HSTDATA. For more information about the host interface, refer to
Section 10.

6-30

Host Interface Address Register, Low Word

Address

COOOOODOh
15 14

I
Description

HSTADRL

The HSTADRL register contains the 16 LSBs of a 32-bit pointer address;
the 16 MSBs are contained in HSTADRH. The contents of HSTADRL and
HSTADRH are concatenated to form a single 32-bit address during an indirect access by a host processor. The pointer address can be accessed by
both the host processor and the TMS3401 O. The host accesses the pointer
address through two 16-bit host interface registers that are mapped into the
host's memory or I/O address space.
The four LSBs of the 32-bit pointer address are forced to 0 to point to an
even word boundary in memory. If the address pointer is incremented past
the largest word address in memory, it will wrap around to the lowest address (all Os).
When you use the HSTADRH and HSTADRL registers to read data indirectly from the host, be sure that you access them in the correct order. If
LBL=O, HSTADRH should be written last. If LBL=1, HSTADRL should
be written last.
Note:
When the TMS34010's on-chip processor writes to HSTADRH or
HSTADRL, the referenced data is not automatically read into
HSTDATA. For more information about the host interface, refer to
Section 10.

6-31

HSTCTLH
·Address

Host Interface Control Register, High Byte

C0000100h

Bit
Assignments

I HLT I CF I LBL IINCRIINCWI Res INMIMI NMII

Fields

Description

Bits

Name

0-7
8
9

Reserved

Not used

NMI

Nonmaskable interrupt

NMIM

Mode bit for NMI

Reserved

Function

Reserved

Not used

INCW

Increment pointer address on write

INCR

Increment pointer address on read

LBL

Lower byte last

Cache flush

HLT

Halt TMS3401 0 processing

The HSTCTLH register contains seven programmable bits used to control
host interface communications. A host processor can access the control
bits in the HSTCTLL and HSTCTLH registers as a single host interface register, HSTCTL. The bits of the host interface's HSTCTL register are
mapped into two separate I/O register locations in the TMS3401 O's memory map, HSTCTLL and HSTCTLH, to allow the TMS3401 0 to alter the bits
in one location without affecting the bits in the other.
The HSTCTLH bits can be both written to and read by both the host processor and the TMS34010. Unpredictable results occur if the TMS3401 0
and host simultaneously write different values to the HSTCTLH bits. Typically only the host alters the bits in HSTCTLH.

•

NMI (Nonmaskable interrupt, host to TMS34010, bit 8)
The nonmaskable interrupt allows the host processor to redirect the execution flow of TMS3401 0 processing to an NMI routine, regardless of the
current state of the interrupt mask flags. The host writes a 1 to the NMI bit
to send a nonmaskable interrupt request to the TMS34010. The interrupt
request cannot be disabled, and will always be executed (unless the
TMS34010 is reset before it can complete interrupt execution). The interrupt is initiated immediately upon NMI becoming set (at the time the current
instruction completes execution, or in the case of a pixel array instruction,
at the next interruptible point in the instruction). Once the interrupt is taken,
internal logic automatically clears the NMI bit to O.
One use of the NMI is to generate a soft reset after the host downloads new
program code into TMS34010 memory. Following execution of a nonmaskable interrupt, screen-refresh and DRAM-refresh functions continue
unaffected. The contents of internal registers other than the HSTCTL register are not altered by the interrupt, although they can be modified by the
NMI service routine.

6-32

Host Interface Control Register, High Byte

•

HSTCTLH

NMIM (Nonmaskable interrupt mode, bit 9)
The NMI mode bit determines whether or not the context of the interrupted
program is saved when a nonmaskable interrupt occurs. When NMIM=O,
the context is saved on the system stack before the N M I service routine is
executed. When NMIM=1, the context is discarded when the NMI service
routine is executed.
The NMIM=O mode supports applications such as single stepping of instructions where the status and PC must be preserved between consecutive
nonmaskable interrupts. When NMIM=1, a nonmaskable interrupt can be
used to simulate a hardware reset in software (using the NMI vector).
Saving the context may be of no benefit if either:
Control is never to be returned to the interrupt program or
The integrity of the stack pointer is suspect.
The nonmaskable interrupt does not cause the I/O registers to be reset.
Consequently, if an NMI is used to simulate a hardware reset, the I/O registers should be reset by software within the NMI service routine.
NMI NMIM

•

Effect

0
0

No effect

Undefined

NMI (save context on stack)

NMI (discard previous context)

CF (Cache flush, bit 14)
While CF is set to 1, the contents of the instruction cache are flushed. All
four P (present) flags in the cache control logic remain forced to 0 as long
as CF remains 1. When CF=1, the cache is disabled; instruction words are
fetched from local memory one at a time as they are needed for execution
by the TMS3401 O. Normal cache operation resumes when CF is set to 0,
assuming the CD bit in the CONTROL register is also O. When the value of
CF is changed from 1 to 0, the cache begins operation in the same initial
state as that which immediately follows reset.
One use of the CF bit is during downloads of new software from the host
processor to TMS34010 local memory. By setting CF to 1 and then to 0
again, the host processor forces the TMS3401 0 to begin to load new instructions into the cache from memory rather than continue execution of
stale instructions already contained in the cache. A 0 must be loaded into
CF for normal cache operation to resume.
CF

0
1

Effect
No effect
Flush and disable cache

6-33

HSTCTLH

•

Host Interface Control Register, High Byte

LBL (Lower byte last, bit 13)
The LBL bit specifies whether an indirect access of TMS34010 memory,
initiated by a host register access, begins when the upper or lower byte of
the register is accessed by the host processor.
LBL is provided to accommodate host processors with 8-bit data paths.
An 8-bit processor must access a 16-bit TMS3401 0 host interface register
as a series of two 8-bit bytes. Processors which access the lower byte (bits
0-7) first and the upper byte (bits 8-15) second should typically set LBL to
0, and those that access bytes in the opposite sequence should set LBL to

1.
When LBL is 0, a local bus cycle is initiated if:
The host writes to the upper byte of HSTADRH, or
The host reads from or writes to the upper byte of HSTDATA.
If LBL is 1, a local bus cycle is initiated if
The host accesses the lower byte of HSTDATA, or
The host writes to the lower byte of HSTADRL
With this capability, the TMS3401 0 is capable of automatically resolving so
called "Little-Endian/Big-Endian" byte addressing incompatibilities between various processors, and promotes software transparency between 8and 16-bit versions of the same processor architecture (such as the 8088
and 8086).

•

LBL

Effect

Initiate 16-bit local bus cycle on host access of upper byte of HSTDATA.
or on load of upper byte of HSTADRH

Initiate 16-bit local bus cycle on host access of lower byte of HSTDATA,
or on load of lower byte of HSTADRL

INCR (Increment address before local read, bit 12)
The INCR bit controls whether or not the 32-bit address pointer contained
in the HSTADRL and HSTADRH registers is incremented before each read.
INCR
0
1

Effect

Do not increment address pointer before read cycle on local memory bus
Increment address pointer before read cycle on local memory bus

When INCR=1, the 32-bit address contained in registers HSTADRL and
HSTADR H is incremented by 16 before being used for the next read of the
TMS34010 memory. This means that HSTDATA is updated to the contents
of the next sequential word in the local memory in preparation for the next
anticipated read 'of HSTDATA by the host processor. A local read cycle also
occurs when the host loads a new address into the HSTADRL and
HSTADRH registers, but the address is not incremented in this case. When
incrementing is enabled, repeated reads of the HSTDATA register by the

6-34

Host Interface Control Register, High Byte

HSTCTLH

host result in a series of adjacent words in TMS34010 memory being read;
otherwise, the same memory word is read each time. Regardless of the value of the INCR bit, each time HSTDATA is read by the host, a new word
is automatically read into HSTDATA from the TMS34010's memory.

•

INCW (Increment address after local write, bit 11)
The INCW bit controls whether or not the 32-bit address pointer contained
in the HSTADRL and HSTADRH registers is incremented after each write.
INew
0
1

Effect
Do not increment address pointer after write cycle on local memory bus
Increment address pointer after write cycle on local memory bus

When INCW=1, the 32-bit address contained in registers HSTADRL and
HSTADRH is incremented by 16 after being used as the memory write address. When incrementing is enabled, repeated writes to the HSTDATA register by the host cause a series of adjacent words in TMS34010 memory
to be modified; otherwise, the same memory word is modified repeatedly.
Regardless of the value of the INCW bit, each time HSTDATA is written to
by the host, a new cycle is initiated to write the contents of HSTDATA to
the TMS3401 O's memory.
•

HLT (Halt TMS34010 program execution, bit 11)
When the HLT bit is set to 1, the TMS3401 0 suspends instruction processing at the next instruction boundary. Once halted, the TMS3401 0 does not
respond to interrupt requests (including NMI). Local memory refresh and
video timing functions continue unaffected while the TMS3401 0 is halted.
When H LT is again set to 0, the TMS3401 0 continues execution.
While the TMS3401 0 is halted, external bus-master devices can arbitrate for,
obtain, and release control of the local bus via the TMS3401 0 hold interface. While the TMS3401 0 is in the hold state, it cannot perform DRAMrefresh or screen-refresh cycles.
The state of the H LT bit immediately following reset is determined by the
state of the HCS pin at the time of the low-to-high transition of RESET:
If HCS is low, HLT is set to 0, and the TMS3401 0 is enabled to begin
executing its reset routine.
If HCS is high, HLT is set to 1, and the TMS3401 0 is halted.
Both the host processor and TM S3401 0 can write to the H LT bit; this means
the TMS3401 0 can halt itself by loading a 1 into H LT.
HlT

Effect

Allow TMS3401 0 to run

Halt TMS3401 0 instruction execution

6-35

HSTCTLL

Address

Host Interface Control Register, Low Byte

COOOOOFOh

Bit
Assignments

Fields

8765432

Reserved
Bits

Description

13 12

Name

Function

0-2

MSGIN

3
4-6

INTIN

Input interrupt bit

MSGOUT

Output message buffer

INTOUT

Output interrupt bit

8-15

Reserved

Not used

Input message buffer

The HSTCTLL register contains eight programmable bits used to control
host interface communications. A host processor can access the control
bits in the HSTCTLL and HSTCTLH registers as a single host interface register, HSTCTL. The bits of the host interface's HSTCTL register are
mapped into two separate I/O register locations in the TMS3401 O's memory map, HSTCTLL and HSTCTLH, to allow the TMS3401 0 to alter the bits
in one location without affecting the bits in the other.
The HSTCTLH bits can be read by both the host processor and the
TMS34010. The following restrictions apply to writes:
•
•
•
•
•
•

The MSGOUT field can be modified only by the TMS3401 O.
The MSGIN field can be modified only by the host.
The host can write a 1 to the INTIN bit, but writing a 0 has no effect.
The TMS3401 0 can write a 0 to the INTIN bit, but writing a 1 has no
effect.
The TMS3401 0 can write a 1 to the I NTOUT bit, but writing a 0 has
no effect.
The host can write a 0 to the INTOUT bit, but writing a 1 has no effect.

Internal arbitration logic permits the TMS3401 0 and host processor to access HSTCTLL at the same time without hazard. Synchronization of asynchronous signals at the host interface pins is performed internally.
•

MSGIN (Message in, host to TMS34010, bits 0-2)
The MSGIN field buffers a 3-bit interrupt message to the TMS3401 0 from
the host. The MSGIN field can be both written to and read by the host, but
only read by the TMS34010. The MSGIN field typically contains a command or status code from the host, which is read by the TMS3401 0 in response to a host-generated interrupt (INTlN=1). The meaning of this code
is defined in the software of the host and TMS3401 O.

6-36

Host Interface Control Register, Low Byte

•

HSTCTLL

INTIN (Interrupt in, host to TMS34010, bit 3)
The INTI N bit controls the interrupt request to the TMS3401 0 from the host.
To generate an interrupt request, the host processor loads a 1 to INTI N. The
TMS34010 deactivates the request by loading a 0 to INTIN. An attempt by
the host to load a 0 to INTIN has no effect. Similarly, an attempt by the
TMS34010 to load a 1 to INTIN has no effect. A read-only copy of the
INTIN bit is available as the HIP bit in the INTPEND register. The HIP bit
faithfully represents the state of the INTIN bit at all times.
INTIN

•

Effect

No interrupt request to TMS3401 0

Send interrupt request to TMS3401 0

MSGOUT (Message out TMS34010 to host bits 4-6)
The MSGOUT field buffers a 3-bit interrupt message to the host from the
TMS34010. The MSGOUT field can be both written to and read by the
TMS34010, but only read by the host. The MSGOUT field permits an interrupt request generated by means of the INTOUT bit to be qualified by an
additional command or status code, the meaning of which is defined in the
software of the host and TMS3401 O.

•

INTOUT (Interrupt out TMS34010 to host bit 7)
The I NTOUT bit controls the interrupt request to the host processor from the
TMS34010. An interrupt request is transmitted to the host by means of an
active-low level on the HINT pin. When INTOUT is 1, HINT is driven active
low; when INTOUT is 0, HINT is driven inactive high. The TMS3401 0 activates the interrupt request by loading a 1 to INTOUT, and the host deactivates the interrupt request by loading a 0 to INTOUT. An attempt by the
TMS34010 to load a 0 to INTOUT has no effect. Similarly, an attempt by
the host to load a 1 to INTOUT has no effect.
INTOUT

Effect

No interrupt request to host

Send interrupt request to host

6-37

HSTDATA

Address

Host Interface Data Register

COOOOOCOh
15 14

I
Description

6-38

HSTDATA

The HSTDATA register buffers data transferred through the host interface
between TMS34010 local memory and a host processor. HSTDATA can
be accessed by the TMS3401 0 at address COOOOOCOh. It is one of the four
16-bit registers that can be accessed by the host register through the
TMS34010 host interface. HSTDATA is typically accessed by the host
rather than the TMS34010. Using the HSTDATA register, the host can either read the TMS3401 O's memory or write to it. The host initiates the indirect access through the host interface using the 32-bit pointer address in
the HSTADRL and HSTADRH registers. During each indirect access, a
16-bit word is transferred between the HSTDATA register and TMS34010
memory. The host processor can access the contents of the HSTDATA register in one 16-bit data transfer or two 8-bit transfers. When the
TMS34010's on-chip processor reads from or writes to HSTDATA, no automatic read or write cycle takes place between HSTDATA and the memory
word pointed to by HSTADRL and HSTADRH.

Horizontal Total Register

Address

C0000030h
15 14

I
Description

HTOTAL

The HTOTAL register is used during generation of the horizontal sync signal
output to the video monitor from the TMS3401 O. It determines the duration of each horizontal scan line on the screen in terms of the number of
VCLK (video clock) periods. The contents of HTOTAL are compared with
the horizontal count in HCOUNT to determine the point at which the horizontal sync pulse begins, which also represents the beginning of a new
scan line. HCOUNT counts from 0 to the value contained in HTOTAL.
When HCOUNT = HTOTAL, the HSYNC output is driven active low on the
next falling edge of the VCLK signal, and HCOUNT is reset to 0 on the same
clock edge.
HTOTAL is loaded with a 16-bit value greater than that contained in
HSBLNK, but less than or equal to 65535. In interlaced scan mode, the
value in HTOTAL should be an odd number (LSB=1) to achieve equal
spacing between adjacent scan lines. The total number of VCLK video
clocks in each horizontal scan line is calculated as HTOTAL + 1. When
external sync mode is enabled (DXV=O) and HSYNC is configured as an
input (HSD=O), HTOTAL should be loaded with a value greater than the
value of HCOUNT at the point at which the external sync pulse is expected.
If the external sync pulse does not occur, HCOUNT will be reset when
HCOUNT = HTOTAL.

6-39

Interrupt Enable Register

INTENB

Address

C0000110h

Bit
Assignments

14 13

Reserved

Fields

Name

Bits

Not used

X1E

External interrupt 1 enable

X2E

External interrupt 2 enable

HIE

I X2E I X1 E I Res I

Function

Reserved

9
10
11
12-15

Reserved

3-8 Reserved

Description

IWVEI DIE I HI§

Not used
Host interrupt enable

DIE

Display interrupt enable

WVE

Window-violation interrupt enable

Reserved

Not used

The INTENB register contains the interrupt mask used to selectively enable
the three internally and two externally generated interrupt requests. The
following interrupts are enabled by the INTENB register:
•

External interrupts 1 and 2 are generated by active-low signals on the
input pins LlNT1 and LlNT2, respectively.

•

The host interrupt is generated when the host processor sets the INTIN bit in the HSTCTL register to 1.

•

The display interrupt is generated when the vertical count in the
VCOUNT register reaches the value contained in the DPYINT register.

•

The window-violation interrupt is caused by an attempt to write a
pixel to a region of the bit map lying outside the limits of the currently-defined window.

The status register contains a global interrupt enable bit, I E. The I NTEN B
register contains individual interrupt enable bits associated with each of the
interrupts (X1 E, X2E, HIE, DIE, and WVE). Interrupts are enabled through
a combination of setting the IE bit and the appropriate bit in the INTENB
register. When IE=O, all interrupts are disabled regardless of the values of
the bits in the INTENB register. When IE=1, each interrupt is enabled or
disabled according to the corresponding enable bit in the INTENB register
(1 enables the interrupt, 0 disables it).

6-40

INTPEND

Interrupt Pending Register

Address
Bit
Assignments

C0000120h

Fields

Reserved

Name

Bits

Not used

X1P

External interrupt 1 pending

X2P

External interrupt 2 pending

HIP

IX2P IX1 P IRes I

Not used
Host interrupt pending

DIP

Display interrupt pending

WVP

Window-violation interrupt pending

Reserved

Not used

15-12

Function

Reserved

3-8 Reserved

Description

Iwvpl DIP IHlrl

The INTPEND register indicates which interrupt requests are currently
pending. INTPEND's six active bits indicate the status of the following interrupts:
•

External interrupts 1 and 2 are generated by active-low signals on the
input pins LlNT1 and LlNT2, respectively.

•

The host interrupt request is generated when the host processor sets
the INTIN bit in the HSTCTL register to 1.

•

The display interrupt request is generated when the vertical count in
the VCOUNT register reaches the value contained in the DPYINT register.

•

The window-violation interrupt request is caused by an attempt to
write a pixel to a region of the bit map lying inside or outside the limits
of the currently-defined window, depending on the selected windowing mode.

The individual pending bits in the INTPEND register reflect the status of
interrupt requests. The interrupt is requested if the corresponding pending
bit is 1. There is no request if the pending bit is O. The status of each interrupt request is reflected in the INTPEND register regardless of whether
the interrupt is enabled or not; this allows the TMS3401 0 to poll interrupts.
The X1 P and X2P bits of INTPEND are read only. They reflect the input
levels on the LlNT1 and LlNT2 pins, and are not affected when the INTPEND
register is written to. The LlNT1 and LlNT2 pins are asynchronous inputs,
but the signals to these pins are synchronized internally so that the X1 P and
X2P bits in the INTPEND register may be reliably read at any time. If an
external interrupt is disabled, the interrupt request is ignored, even though
the corresponding pending flag in INTPEND is set. The interrupt will be
taken by the TMS34010 only if the external request is maintained at the
corresponding interrupt request pin until the interrupt is again enabled.

6-41

INTPEND

Interrupt Pending Register

The DIP and WVP bits in the INTPEND register reflect the status of interrupt
requests generated by conditions internal to the TMS3401 O. These two bits
are implemented as latches. Once set, DIP or WVP wili remain set until a
o is written to it (or the TMS3401 0 is reset). Writing a 1 to either of these
bits has no effect at any time. While an internal interrupt is disabled, the
interrupt request is ignored, even though the corresponding pending flag
in INTPEND is set. If the interrupt is subsequently enabled while the interrupt pending flag remains set (because of a prior interrupt request) then
the interrupt will be taken by the TMS3401 O.
The HIP bit in the INTPEND register is a read-only bit that always displays
the current contents of the INTIN bit in the HSTCTL register. Writing to the
INTPEND register has no effect on the HIP bit. A host interrupt request is
generated when the host processor writes a 1 to the INTIN bit of the
HSTCTL register. The TMS3401 0 clears the interrupt request by writing a
to the INTI N bit.

.//

6-42

Plane Mask Register

Address

C0000160h
15 14

I
Description

PMASK

12 11

PMASK

The PMASK register selectively enables or disables various planes in the
bit map of a display system in which each pixel is represented by multiple
bits. PMASK contains a 16-bit value that determines which bits of each
pixel can be modified during execution of a DRAV, PIXT, FILL, LINE, or
PIXBLT instruction. Via the PMASK register, the programmer specifies
which bits within each pixel are protected (mask bit=1) and not protected
(mask bit=O) from modification. During a pixel write operation, the Os in
the plane mask represent bit positions within the destination pixel that are
to be modified by the pixel operation. The 1s in the plane mask represent
bit positions in the destination pixel that are protected from modification.
During a pixel read operation, the Os in the mask indicate which bits within
a pixel may be read; bits corresponding to 1s in the mask are always read
as Os.
The organization of a display memory is sometimes described in terms of
bit planes. If the pixel size is four bits, for example, and the bits in each
pixel are numbered from 0 to 3, the display memory is said to be composed
of four bit planes, numbered from 0 to 3. Plane 0 contains all the bits
numbered 0 from all the pixels, plane 1 contains all the bits numbered 1
from all the pixels, and so on. A 4-bit mask is constructed such that bit 0
of the mask enables (if 0) or disables (if 1) writes to the bits in plane 0,
mask bit 1 enables or disables writes to plane 1, and so on.
The plane mask for a 4-bit pixel is four bits; the plane mask for an 8-bit pixel
is eight bits; and so on. The plane mask must be replicated throughout the
16 bits of the PMASK register. For example, with four bits per pixel, the
PMASK register is loaded with four identical copies of the corresponding
4-bit plane mask, as indicated below.
15

PMASK

1211
MASK

87
MASK

MASK

With a pixel size of eight bits, the corresponding 8-bit plane mask is replicated twice - once in bits 0-7 of PMASK, and again in bits 8-15. In general, all 16 bits of the register are used, and a mask for a pixel size of less
than 16 bits must be duplicated n times, where n is 16 divided by the pixel
size.
The individual bits of the PMASK register are associated with the corresponding bits of the 16-bit local data bus (data are in fact multiplexed over
the same LADo-LAD15 pins as addresses). PMASK register bit 0 is associated with bit 0 of the data bus (the bit transferred on LADO), PMASK bit
1 is associated with bit 1 of the data bus, and so on. In general, if PMASK
bit n is a 0, then bit n of the data bus is enabled by the mask; if PMASK
bit n is a 1, bit n is disabled by the mask.
Plane masking is effectively disabled (allowing all bits of each pixel to be
modified) by loading all Os into the PMASK register. This is the default
state of PMASK following reset.
6-43

PMASK

Plane Mask Register

To. maintain upward compatibility with future versions of the GSP, software
d~·vers should treat the PMASK register as a 32-bit register beginning at
a dress C0000160h. In other words, software should write the plane mask
v lue not only to the 16-bit word at address C0000160h, but also to the
vyord at C0000170h. Writing the second word will have no effect on the
TMS34010, but will ensure software compatibility with future graphics
processors which may extend the PMASK register from 16 to 32 bits.

6-44

PSIZE

Pixel Size Register

Address

C0000150h
15 14

I
Description

PSIZE

The PSIZE register is used to specify the pixel size in bits. If the pixel size
is four, for example, PSIZE is loaded with the value four. If the pixel size
is eight, PSIZE is loaded with the value eight, and so on. All 16 bits of the
PSIZE register can be written to or read. Legal pixel sizes are 1,2,4,8, and
16 bits; any other value of PSIZE is undefined.
PSIZE

Pixel Size

0OO1h
0OO2h
0OO4h
0OO8h
0010h

1 bit/pixel
2 bits/pixel
4 bits/pixel
8 bits/pixel
16 bits/pixel

6-45

REFCNT

Address

Refresh Count Register

C00001FOh
15 14
!

Fields

6543210

ROWADR

RINTVL

! Reserved!

Function

Bits

Name

0-1

Reserved

2-7

RINTVL

Refresh interval

ROWADR

Row address

8-15

Description

Not used

The REFCNT register generates the addresses output during DRAM refresh
cycles and counts the intervals between successive DRAM refresh cycles.
DRAMs require periodic refreshing to retain their data. The TMS34010
automatically generates DRAM refresh cycles at regular intervals. The interval between refresh cycles is programmable. The DRAM refresh mode
is selected by loading the appropriate value to the two-bit RR (refresh rate)
field in the CONTROL register. DRAM refreshing can be disabled in systems that do not require it. The modes are defined as follows.

Description

Refresh every 32
local clock periods

Refresh every 64
local clock periods

Reserved for future
expansion

No DRAM refreshing

At reset, the RR field is set to the initial value 002. During the time that the
reset signal to the TMS34010 is active, no DRAM-refresh cycles are performed.
Bits 2-15 of REFCNT form a continuous binary counter. Bits 2-7 form the
RINTVL field, which counts the intervals between successive requests for
DRAM-refresh cycles. When RR=012, the RINTVL field is decremented
by 1 every local clock cycle; that is, the register is decremented at bit 2. This
means that RINTVL underflows into ROWADR (a borrow ripples from bit
7 to bit 8 of REFCNT) every 64 local clock cycles. The underflow has two
effects:
•

ROWADR is decremented by 1 and

•

A request for a DRAM-refresh cycle is sent to the memory control
logic.

When RR=002, the RINTVL field is decremented by 2 every local clock
period. This means that a DRAM-refresh cycle is generated every 32 local
clock periods, twice the rate that results when RR=012' When RR=112,
DRAM refreshing is disabled and no DRAM-refresh cycles occur.

6-46

Refresh Count Register

REFCNT

During a DRAM-refresh cycle, the row address output to memory is taken
from the 8-bit ROWADR field of REFCNT. Specifically, bits 8-15 of
REFCNT are output on LADO-LAD7. REFCNT bits 8-14 are simultaneously
output on LAD8-LAD14. (The RF bus status signal is output as a low level
on LAD15.) This means that the 8-bit row address needed to refresh a
DRAM can be taken from any eight adjacent LAD pins in the range
LADQ-LAD14. Note that as ROWADR counts from 255 to 0, the refresh
addresses output at the selected eight LAD pins will sequence through all
256 values in the range 255 to 0, though not necessarily in the same order
as ROWADR.
REFCNT is set to 0 at reset; after that, refresh address generation is automatic. Typically there is no reason to read this register or write to it. although it can be accessed similarly to the way other 1/0 registers are
accessed. In order to reliably write a value to REFCNT, DRAM refresh
should be disabled (by setting RR to 112) before writing to REFCNT.

6-47

VCOUNT

Address

Vertical Count Register

C00001 DOh
15 14

I
Description

VCOUNT

The VCOUNT register is a 16-bit counter used during generation of the
vertical sync and blanking signals. VCOUNT counts the horizontal lines in
the video display, incrementing at the same clock edge at which HCOUNT
is internally reset to O. This causes the falling edges of HSYNC and VSYNC
to coincide.
In order to generate vertical sync and blanking signals, the value of
VCOUNT is compared to the value of the four vertical timing registers,
VESYNC, VEBLNK, VSBLNK, and VTOTAL. When HCOUNT = HTOTAL
and VCOUNT = VTOTAL at the same time, VCOUNT is reset to 0 on the
next VCLK falling edge and the VSYNC output is driven active low.
If interlaced scan mode is enabled and the current field is even, and if
VCOUNT = VTOTAL and HCOUNT = HTOTAL/2, then VCOUNT is reset
to 0 and VSYNC goes low (HCOUNT is not reset until it reaches the value
HCOUNT = HTOTAL). When external sync mode is enabled, VCOUNT is
reset to 0 when the VSYNC input signal goes active low.
A display interrupt request is generated when VCOUNT = DPYINT. This
can be used to coordinate software activity with the refreshing of selected
lines on the screen.
Two separate, asynchronous elements of the TMS3401 0 internal logic can
access VCOUNT:
•

The internal processor, which runs synchronously to local clocks
LCLK1 and LCLK2, can access VCOUNT as an I/O register.

•

The video timing control logic, which runs synchronously to the video
clock VCLK, increments and clears VCOUNT in the course of generating the sync and blanking signals.

No synchronization between these two subsystems is provided, and
VCOUNT can only be reliably read or written while VCLK is held at the
logic-high level. VCOUNT is typically not read or written to except during
chip test.

6-48

Vertical End Blank Register

Address

C0000050h
15 14

I
Description

VEBLNK

8
7
VEBLNK

VEBLNK is a video timing register that designates the time at which the
vertical blanking interval ends. The 16-bit value contained in VEBLNK is
compared to VCOUNT to determine when to end the vertical blanking interval. The vertical blanking interval ends when the following conditions
are satisfied:
•
•

VCOUNT = VEBLNK
HCOUNT = HTOTAL

The end of the vertical blanking interval coincides with the start of the
horizontal sync, occurring at a time when the internal horizontal blanking
signal is active. The blanking signal output from the BLANK pin is a composite of the horizontal and vertical blanking signals generated internally,
and will not reach its inactive-high level until both internal blanking signals
have become inactive.
When external video is enabled (DXV=O) and the HSYNC pin is configured
as an input (HSD=O), the vertical blanking interval ends when the following conditions are satisfied:
•
•

VCOUNT = VEBLNK and
The leading edge of the external horizontal sync pulse is detected

The beginning of the sync pulse is seen as a high-to-Iow transition at the
HSYNC pin.
Typical video monitors require VEBLNK to be set to a value less than the
value in VSBLNK, and greater than the value in VESYNC.

6-49

Vertical End Sync Register

VESYNC

Address

C0000040h
15 14

I
Description

VESYNC

VESYNC is a video timing register that designates the time at which the
vertical sync pulse ends. The 16-bit value contained in VESYNC is compared to VCOUNT to determine when to end the vertical sync pulse. The
sync pulse ends when the following conditions are satisfied:
•
•

VCOUNT = VESYNC
HCOUNT = HTOTAl

The VSYNC output is driven inactive high to signal the end of the vertical
sync interval.
When interlaced mode is enabled and the next vertical field is odd, VSYNC
is driven high when VCOUNT = VESYNC and HCOUNT = HTOTAl/2.
Typical video monitors require VESYNC to be set to a value less than the
value contained in the VEBlNK register; the minimum value of VESYNC is

O.
When external sync mode is enabled (DXV=O), the end of the external
vertical sync pulse is detected as a low-to-high transition at the VSYNC pin,
which is configured as an input. VESYNC should be loaded with a value
greater than the value in VCOUNT at the point at which the external VSYNC
input signal should go inactive high, but lower than the value in VCOUNT
when the external VSYNC should again become active low. For example,
VESYNC could be loaded with the sum of the values in VEBlNK and
VSBlNK divided by two.

6-50

Vertical Start Blank Register

Address

C0000060h
15 14

I
Description

VSBLNK

VSBLNK is a video timing register that designates the time at which the
vertical blanking interval starts. The 16-bit value contained in VSBLNK is
compared to VCOUNT to determine when to start the vertical blanking interval. The vertical blanking interval starts when the following conditions
are satisfied:
•
•

VCOUNT = VSBLNK
HCOUNT = HTOTAL

The start of the vertical blanking interval coincides with the start of the
horizontal sync, occurring at a time when the internal horizontal blanking
signal is active. The blanking signal output from the BLANK pin is a composite of the horizontal and vertical blanking signals generated internally,
and reaches its active-low level when either or both internal blanking signals are active.
When external video is enabled (DXV=O) and the HSYNC pin is configured
as an input (HSD=O), the vertical blanking interval starts when the following conditions are satisfied:
•
•

VCOUNT = VSBLNK
The leading edge of the external horizontal sync pulse is detected

The beginning of the horizontal sync pulse is seen as a high-to-Iow transition at the HSYNC pin.
VSBLNK should be set to a value less than the value in VTOTAL, and
greater than the value in VEBLNK.

6-51

VTOTAL
Address

Vertical Total Register

C0000070h
15 14

I
Description

VTOTAL

VTOTAL contains a 16-bit value that designates the value of VCOUNT at
which the vertical sync pulse begins. The contents of VTOTAL are cgmpared to VCOUNT to determine when to start the vertical sync pulse. Vertical sync begins when the following two conditions are satisfied:
•
•

VCOUNT == VTOTAL
HCOUNT == HTOTAL

These conditions cause HCOUNT to begin counting from 0 again.
The VSYNC output is driven active low to signal the start of the vertical sync
interval. The high-to-Iow transitions of VSYNC and HSYNC occur at the
same clock edge.
When interlaced mode is enabled and the next vertical field is odd, VSYNC
is driven low when VCOUNT == VESYNC and HCOUNT == HTOTAL/2. The
total number of horizontal lines in each vertical field is calculated as VTOTAL + 1. In interlaced mode the total number of horizontal lines in both
fields of the vertical frame is calculated as 2 x VTOTAL-1 .
When external video is enabled (DXV==O), the VSYNC pin is configured as
an input rather than an output. The high-to-Iow transition of VSYNC is recognized as the beginning of 1.'he vertical sync pulse, unless the condition
VCOUNT == VTOTAL and the start of horizontal sync are detected first.
VTOTAL should be loaded with a value at least as large as the value of
VCOUNT at which the external sync pulse should begin. Should the external sync pulse not occur, VCOUNT wi" be reset one VCLK period after
the conditionsVCOUNT == VTOTAL and HCOUNT == HTOTAL occur.
VTOTAL should be set to a value greater than the value in VSBLNK. The
maximum value that can be loaded into VTOTAL is 65535.

6-52

Section 7

Graphics Operations

This section provides an overview of the graphics drawing capabilities of the
TMS34010. Topics in this section include:

Section
Page
7.1 Graphics Operations Overview ............................................................... 7-2
7.2 Pixel Block Transfers ................................................................................ 7-4
7.3 Pixel Transfers ......................................................................................... 7-10
7.4 Incremental Algorithm Support ............................................................ 7-10
7.5 Transparency ........................................................................................... 7 -11
7.6 Plane Masking ........................................................................................ 7-12
7.7 Pixel Processing ..................................................................................... 7-15
7.8 Boolean Processing Examples .............................................................. 7-17
7.9 Multiple-Bit Pixel Operations ............................................................... 7-19
7.10 Window Checking .................................................................................. 7-25

7-1

Graphics Operations - Overview

7.1

Graphics Operations Overview
The TMS3401 0 instruction set provides several fundamental graphics drawing
operations:
•

The PIXBlT and Fill instructions manipulate two-dimensional arrays
of pixels.

•

The LINE instruction implements the fast inner loop of the Bresenham
algorithm for drawing lines.

•

The DRAV (draw and advance) instruction draws a pixel and increments
the pixel address by a specified amount. This function supports the implementation of incremental algorithms for drawing circles, ellipses, arcs,
and other curves.

•

The PIXT (pixel transfer) instruction transfers individual pixels from one
location to another.

The PIXBlT instruction plays an important role in rapidly drawing highquality, bit-mapped text. In particular, the PIXBlT B,XY and PIXBlT B,l instructions expand character patterns stored as bit maps (at one bit per pixel)
into color or gray-scale characters of 1, 2, 4, 8 or 16 bits per pixel. This allows
character shape information to be stored independently of attributes such as
color and intensity, providing greater storage efficiency.
The TMS34010 provides several methods for processing the values of the
source and destination pixels before the result is written to the destination.
These operations include:
•

Boolean and arithmetic pixel processing operations for combining source
pixels with destination pixels.

•

A plane mask which specifies which bits within pixels can be altered
during pixel operations.

•

Transparency, an option which permits objects written onto the screen
to have transparent regions through which the background is visible.

Pixel processing, plane masking, and transparency can be used simultaneously. These operations on pixel values can be used in combination with any
of the pixel drawing instructions listed above. The arithmetic operations are
especially important in displays that use multiple bits per pixel to encode color
or intensity information. For example, the MAX and MIN operations allow two
objects with antialiased edges to be smoothly merged into a single image.
The TMS3401 0 has features such as automatic window checking to support
windowed graphics environments. Three window-checking modes are provided:

7-2

•

Clipping a figure to fit a rectangular window.

•

Requesting an interrupt on an attempt to write to a pixel outside of a
window.

Graphics Operations - Overview

•

Requesting an interrupt on an attempt to write to a pixel inside of a
window.

The last of these modes can be used to identify screen objects that are pointed
to by a cursor. The window checking modes can be used with any of the pixel
drawing instructions that use XY addressing. Window checking is optional
and can be turned off.
The TMS3401 0 provides further support for windowed environments by rapidly detecting the following conditions:
•

Whether a point lies inside or outside a rectangular window.

•

Whether a line lies entirely inside or entirely outside a window.

Lines that lie entirely outside a window can be trivially rejected, meaning that
they take no further processing time. These conditions are detected via the
CPW (compare point to window) instruction, which takes only one machine
state to compare the XY coordinates of a point to all four sides of a window.
Another operation that occurs frequently in windowed environments is calculating the region where two rectangles intersect. This is a feature available
with the PIXBLT and FILL instructions. Based on the window-checking
mode, one of two methods can be selected to calculate the region of intersection:
•

The destination pixel array is preclipped to a rectangular window before
the Pix Bit or fill operation begins.

•

The intersection of the destination pixel array with a rectangular window
is calculated, but no pixels are transferred.

7-3

Graphics Operations - Pixel Block Transfers

7.2 Pixel Block Transfers
The TMS34010 supports a powerful set of raster operations, known as
Pix Bits (pixel block transfers), that manipulate two-dimensional arrays of bits
or pixels. A pixel array is defined by the following parameters:
•

A starting address (by default, the address of the pixel with the lowest
address in the array)

•

A width DX (the number of pixels per row)

•

A height DY (the number of rows of pixels)

•

A pitch (the difference between the starting addresses of two successive
rows)

A pixel array appears as a rectangular area on the screen. The array pitch is the
same in this case as the pitch of the display. The default starting address is
the address of the pixel in the upper left corner of the rectangle. (This assumes
that the ORG bit in the DPYCTL register and the PBH and PBV bits in the
CONTROL register are all set to their default values of 0.)
Two operands must be specified for a PIXBLT instruction:
•
•

A source pixel array and
A destination pixel array

The two arrays must have the same width and height, although they may have
different pitches. Each pixel in the source array is combined with the corresponding pixel of the destination array. A Boolean or arithmetic pixel processing operation is selected and applied to the PIXBLT operation. The default
pixel processing operation is replace. If replace is selected, source pixel values
are simply copied into destination pixels.
Before executing a PIXBLT instruction, load the following parameters into the
appropriate GSP internal registers:

DYDX

Composed of two portions: OX, which specifies the width of the
array, and DY, which specifies the height of the array.

PSIZE

Pixel size (number of bits per pixel).

SADDR

Starting address of source array (XY or linear address).

DADDR

Starting address of destination array (XY or linear address).

SPTCH

Source pitch, or difference in memory addresses of two vertically
adjacent pixels in the source array.

DPTCH

Destination pitch, or difference in memory addresses of two vertically adjacent pixels in the destination array.

If either the source or destination array is specified in XY format, the contents
of the CONVSP and CONVDP registers will be used in instances in which the
Y component of the starting address must be adjusted prior to the start of the

7-4

Graphics Operations - Pixel Block Transfers

PixBlt. The Y component may require adjustment. either to preclip the array
or to select a starting pixel in one of the lower two corners of the array.
Pitches and starting addresses must be specified separately for the two arrays
(source and destination). The width, height, and pixel size are common to
both arrays. (During a color expand operation, only the destination pixel size
is specified; the source pixel size is assumed to be one bit.)
The starting address of a pixel array can be specified as a linear (memory)
address or as an XY address. Window checking can be used only when the
destination array is pointed to by an XY address.
On-screen objects may be defined as XY arrays but may be more efficiently
stored as linear arrays in off-screen memory. An array specified in linear format
can be transferred to an array specified in XY format (and vice versa) by means
of the PIXBLT L,XY and PIXBLT XY,L instructions.
The FI LL instruction fills a specified destination pixel array with the pixel value
specified in the COLOR1 register. A fill operation can be thought of as a
special type of PixBlt that does not use a source pixel array. The source pixel
value used in pixel processing is the value in the COLOR1 register. The destination array of a FILL instruction can be specified in either XY or linear format.

7.2.1 Color-Expand Operation
The TMS3401 0 allows shape information to be stored separately from attributes such as color and intensity. A shape can be stored in compressed form
as a bit map containing 1s and Os. The color information is added as the shape
is drawn to the screen; the 1s in the bit map are expanded to the specified
Color 1 value, and the Os are expanded to the Color 0 value. This saves a
significant amount of memory when the pixel size in the display memory is two
bits or more.
Two PIXBLT instructions, PIXBLT B,XY and PIXBLT B,L, provide the colorexpand capability. The source array for either instruction is a bit map (one bit
per pixel) stored off-screen in linear format for greater storage efficiency. The
destination array can be specified in either XY or linear format. The pixel size
for the destination array is governed by the value in the PSIZE register. The
colors to which the 1s and Os in the source array are expanded are specified
in the COLOR1 and COLORO registers.
A primary benefit of the color-expand capability is the reduction in table area
needed to store text fonts. Font bit maps are stored in compressed form at one
bit per pixel. The color-expand operation adds color to a character shape at
draw time, allowing color to be treated as an attribute separate from the shape
of the character. The alternative would be to store the fonts in expanded form,
which can be costly. The amount of table storage necessary to store red letters
A-Z, blue letters A-Z, and so on, multiplied by the number of font styles
needed for an application program, would be prohibitive. Furthermore, the
color-expand operation is inherently faster than using pre-expanded fonts
because far fewer bits of character shape information have to be read from the
font table when a character is drawn to the screen.
Figure 7 -1 shows the expansion of a bit map, one bit per pixel and four bits
wide, into four 4-bit pixels (transforming 0-1-1-0 into yellow-red-red-yellow,
7-5

Graphics Operations - Pixel Block Transfers

for example). Before transferring the expanded source array to the destination
array, any of the Boolean or arithmetic pixel processing operations can be applied.
Four bIIB per plxe' example
of 001« expand

Four bit I*Iary or IRI8xpanded ImIge

'0 '0 I, '0 I 'gig" In I

COLOR1
'0' Q"'0 I I pi gl,' QI ReglBter

COLORO
la 11 Ui III I a131 aIII I al jig I j I I al j I aI j I Regl8ter
Execute Expand

!
,

Reaultlng 18-b1t expanded Image

Figure 7-1. Color-Expand Operation

The expand function is also useful in applications that generate shapes or
patterns dynamically. During the first stage of this process, a compressed image is constructed in an off-screen buffer area at one bit per pixel. The image
is built up of geometric objects such as rectangles, circles or polygons. Patterns can also be added. When complete, the compressed image is colorexpanded onto the screen. This method defers the application of color and
intensity attributes until the final stage.
Combining color expand with the replace-with-transparency operation yields
a new operation that is particularly useful in drawing overlapping or kerned
text. The color value used to replace the Os in the source array is selected by
the programmer as all Os, which is the transparency code. The GSP defers the
check for transparency until after the color-expand operation has been performed. As the color-expand operation is performed, the Os in the source array
are expanded to all Os. Only the pixels in the destination array that correspond
to nontransparent pixels in the resulting source array are replaced.
The PIXBLT B,XY and PIXBLT B,L instructions can be used in conjunction
with pixel processing, transparency and plane masking. Source pixels are expanded before being processed. Window checking can be used with PIXBLT
B,XY.

7-6

Graphics Operations - Pixel Block Transfers

7.2.2 Starting Corner Selection
The default starting address of a pixel array is the lowest pixel address in the
array. When an array is displayed on the screen, as shown in Figure 7-2 a, the
starting address is the address of the pixel in the upper left corner of the array.
(The XY origin is located in its default position at the upper left corner of the
screen.) During a PixBlt operation, this pixel is processed first. The PixBlt
processes pixels from left to right within each row, beginning at the top row
and moving toward the bottom row. The pixel at the lower right corner of the
array is processed last.
Certain Pix Bit operations allow any of the other three corners to be used as the
starting location. This may be necessary, for instance, if the source and destination arrays overlap. The sequence in which pixels are moved when the
arrays overlap should be controlled so as to not overwrite the pixels in the
source array before they are written to the destination array.
Figure 7 -2 shows how the PBV and PBH bits in the CONTROL register determine the starting corner for the PixBlt operation. The starting corner is indicated for each of four cases. PBH selects movement in the X direction, from
left to right or right to left. PBV selects movement in the Y direction, from top
to bottom or bottom to top.

r-:

Pixel Array
Address

Pixel Array

Addreaa

PBH=O, PBV=O

PBH=1, PBV=O

Pixel Array
Address

PIxel Array

Addreaa

PBH=O, PBV=1

PBH=1, PBV=1

Note: Starting corners are shaded.

Figure 7-2. Starting Corner Selection

7-7

Graphics Operations - Pixel Block Transfers

PBH=O

The PixBlt processes pixels from left to right; that is, in the direction
of increasing X.

PBH=1

The PixBlt processes pixels from right to left; that is, in the direction
of decreasing X.

PBV=O

The PixBlt processes rows from top to bottom; that is, in the direction of increasing Y.

PBV=1

The PixBlt processes rows from bottom to top; that is, in the direction of decreasing Y.

All the pixels in one row are processed before moving to the next row.
When one or both of the arrays is specified in XY format, the GSP automatically calculates the actual starting address (specified by PBH and PBV) from
the default starting address (that is, the lowest pixel address in the array) and
the width and height of the array. Automatic starting address adjustment is
available with the following instructions:
•
•
•

PIXBLT L,XY
PIXBLT XY,L
PIXBLT XY,XY

The programmer supplies the default starting addresses for these PixBlts in the
SADDR and DADDR registers. During the course of instruction execution,
SADDR and DADDR are automatically adjusted to the address of the corner
selected by PBH and PBV.
When both arrays are specified in linear format, the starting addresses of the
appropriate corner pixels must be provided by the programmer. The PIXBLT
L,L instruction allows any of the four corners to be used as the starting location, but in this case the programmer must adjust the addresses in SADDR
and DADDR to the corner selected by PBH and PBV.

7.2.3 Interrupting PixBlts and Fills
PIXBLT and FILL are interruptible instructions. An interrupt can occur during
execution of one of these instructions; when interrupt processing is completed, execution of the PIXBLT or FILL resumes at the point at which the interruption occurred.
The execution time of a PIXBLT or FILL instruction depends on the specified
pixel array size. In order to prevent high-priority interrupts from being delayed
until completion of PixBlts and fills of large arrays, the PIXBLT and FILL instructions check for interrupts at regular intervals during their execution.
When a PIXBLT or FILL instruction is interrupted the PBX (PixBlt executing)
status bit is set to 1. This records the fact that the interrupt occurred during
a pixel array operation. The PC and the ST are pushed onto the stack, and
control is transferred to the appropriate interrupt service routine. At the end
of the interrupt service routine, an RETI (return from interrupt) instruction is
executed to return control to the interrupted program. The RETI instruction

7-8

Graphics Operations - Pixel Block Transfers

pops the ST and PC from the stack. When the PBX bit is detected, execution
of the interrupted PIXBLT or FI LL instruction resumes.
At the time of the interrupt, the state of the PIXBLT or FILL instruction is saved
in certain B-file registers. The source and destination address registers contain
intermediate values. The source and destination pitches may also contain intermediate values, depending on the instruction. The SAD DR, SPTCH,
DAD DR, DPTCH registers and registers B1 o-B14 (as well as the original set
of implied operands) contain the information necessary to resume the instruction upon return from an interrupt.
If the interrupt routine uses any of these registers, they should be saved on the
stack and restored when interrupt processing is complete. By following this
procedure, PIXBLT or FILL instructions can be safely executed within interrupt
service routines.
Note:
The PBX bit is not set to 1 when a PIXBLT or FILL instruction is aborted
due to a window violation.

7-9

Graphics Operations - Pixel Transfers/Incremental Algorithm Support

7.3 Pixel Transfers
The TMS3401 0 uses the PIXT (pixel transfer) instructions to transfer individual pixels from one location to another. The following pixel transfers can be
performed:
•
•
•

From an A- or B-file register to memory,
From memory to an A- or B-file register, or
From one memory location to another.

The address of a pixel in memory can be specified in XY or linear format. Linear addresses must be pixel aligned.
The pixel size for all PIXTs is specified by the value in the PSIZE register. Pixel
sizes are restricted to 1, 2, 4, 8, or 16 bits to facilitate XY address computations, window checking, transparency, and arithmetic pixel processing.
The PIXT instruction can be used in conjunction with window checking,
Boolean or arithmetic pixel processing, plane masking, and transparency.

7.4 Incremental Algorithm Support
The TMS3401 0 supports incremental drawing algorithms via its DRAV (draw
and advance) and LINE instructions. The DRAV instruction is used primarily
in the construction of algorithms for incrementally drawing circles, ellipses,
arcs, and other curves. The DRAV instruction can also be used in the inner
loop of algorithms for drawing straight lines incrementally. Lines, however,
are treated as a special case by the TMS3401 0 in order to achieve even faster
drawing rates. A separate instruction, LINE, implements the entire inner loop
of the Bresenham algorithm for drawing lines.
The DRAV (draw and advance) instruction draws a pixel to a location pointed
to by a register; the pointer register is then incremented to point to the next
pixel. The pointer is specified as an XY address. The X and Y portions of the
address are incremented independently, but in parallel. The value written to
the destination pixel in memory is taken from the COLOR1 register.
The DRAV instruction is embedded in the inner loop of an incremental algorithm to speed up its execution. As an incremental algorithm plots each pixel
on a curve, it also determines where the next pixel will be drawn. The next
pixel is typically one of the eight pixels immediately surrounding the pixel just
plotted on the screen. Advancing in this manner, the algorithm tracks the
curve from one end to the other.
The DRAV and LINE instructions may be used in conjunction with Boolean
or arithmetic pixel processing operations, window checking, plane masking
and transparency.

7-10

Graphics Operations - Transparency

7.5

Transparency
When a PixBlt is used to draw an object to the screen, some of the pixels in
the rectangular pixel array that contains the object may not be part of the object itself. Transparency is a mechanism that allows surrounding pixels in
the array to be specified as invisible. This is useful for ensuring that only the
object. and not the rectangle surrounding it, is written to the screen.
Transparency is enabled by setting the T bit in the CONTROL register to 1, or
disabled by setting the T bit to O. When enabled, a pixel that has a value of 0
is considered transparent. and will not overwrite a destination pixel. Trans-

parency detection is applied not to the source pixel values, but to the pixel
values resulting from plane masking and pixel processing. When an operation
performed on a pair of source and destination pixels yields a a result. the GSP
detects this and prevents the destination pixel from being altered. In the case
of pixel processing operations such as AND, MIN, and replace, a source pixel
value of 0 ensures that the result of the operation will be a transparent pixel.
Figure 7-3 illustrates how transparency works in the GSP. Assuming four bits
per pixel, the hardware must detect strings of as of length four falling between
pixel boundaries. While bit strings A and B are both of pixel length, only
string A is detected as transparent. String B crosses the pixel boundary. The
memory interface logic generates an internal mask to govern which bits are
modified during a write cycle. This mask contains as in the bits corresponding
to the transparent pixel. Only destination bits corresponding to 1 s in the mask
will be modified.

I-- String A-1 I-- String B--I
Data to be written

010

Mask generated

~------~~------~--------~--------~

Data to be modified

Resulting data

AlB

B B B Ie

1 I B

B 11

e ID

01 0

D D DI

Note: This example assumes four bits per pixel.
Figure 7-3. Transparency
Figure 7 -7 (page 7-17) and Figure 7 -8 (page 7-20) illustrate several pixel
processing operations. Figure 7-8 h shows an example of a replace operation
performed with transparency enabled. The pixels surrounding the letter A
pattern in the source array are transparent (all Os). Compare Figure 7-8 h with
Figure 7-7 d; this replace-with-transparency operation is analogous to the
logical OR operation in a one-bit-per-pixel display.
Transparency can be used with any instruction that writes to pixels, including
the PIXBLT, FILL, DRAV, LINE, and PIXT instructions. Transparency does not
affect writes to non-pixel data.
7-11

Graphics Operations - Plane Masking

7.6 Plane Masking
The plane mask is a hardware mechanism for protecting specified bits within
pixels. Mask-protected pixels will not be modified during graphics instructions. The plane mask allows the bits within pixels to be manipulated as
though the display memory were organized into bit planes (or color planes)
that can selectively be protected from modification. The number of planes
equals the number of bits per pixeJ.
Consider an example in which the pixel size is four bits. The bits within each
pixel are numbered 0-3, and belong to planes 0-3, respectively. All the bits
numbered 0 in all the pixels form plane 0, all the bits numbered 1 in all the
pixels form plane 1, and so on.
The plane mask allows one or more planes to be manipulated independently
of the other planes. Given four planes of display memory, for example, three
of the planes can be dedicated to eight-color graphics, while the fourth plane
can be used to overlay text in a single color. The plane mask can be set so that
the text plane can be modified without affecting the graphics planes, and vice
versa.
The PMASK register contains the plane mask. Each bit in the plane mask
corresponds to a bit position in a pixel. The 1s in the mask designate pixel
bits that are protected, while Os in the mask designate pixel bits that can be
modified. Those pixel bits that are protected by the plane mask are always
read as Os during read cycles, and are protected from alteration during write
cycles. While no single control bit enables or disables plane masking, it is effectively disabled by setting PMASK to all Os; this is the default condition
following reset.
The logical width of a quantity in the plane mask is the same as the pixel size.
However, in order to maintain a consistent effect on all of the pixels within a
destination region, regardless of their position within the destination words,
you should replicate the mask for a single pixel to fill the entire 16-bit PMASK
register. (To provide upward compatibility with future versions of the GSP,
you should replicate the plane mask through the 32 bits beginning at address
C0000170h.) For example, if the pixel size is four bits, the 4-bit mask is replicated four times within PMASK; in bits 0-3, 4-7, 8-11, and 12-15. These
four copies of the mask are applied to the four pixels in a word written to or
read from memory. A 16-bit PMASK value for pixels of 1, 2, 8, or 16 bits is
constructed similarly by replicating the mask 16, 8, 2, or 1 times, respectively.
The plane mask affects only pixel accesses performed during execution of the
PIXBLT, FILL, PIXT, DRAV, and LINE instructions. Data accesses by nongraphics instructions are not affected.
The following list summarizes operation of the PMASK register during pixel
reads and writes:

•

Pixel Read:
The Os in PMASK correspond to unprotected bits in the source pixel that
are seen by the GSP to contain the actual values read from memory.
The 15 in PMASK correspond to protected bits in the source pixel that
are seen as Os by the GSP, regardless of the values read from memory.

7-12

Graphics Operations - Plane Masking

•

Pixel Write:
The Os in PMASK specify those bits in the destination pixel in memory
which may be altered.
The 1s in PMASK specify protected bits in the destination pixel which
cannot be altered.

When a pixel is being transferred from a source to a destination location, plane
masking is applied to the values read from the source and destination before
pixel processing is applied. As the operands are read from memory, the bits
protected by the plane mask are replaced with Os before the specified Boolean
or arithmetic pixel processing operation is performed. and destination before
pixel processing is applied. Transparency detection is performed on the result
of this operation. When the result is written back to the destination, those bits
of the destination that are protected by the plane mask are not modified.
Source pixels that originate from registers are not affected by the plane mask,
and undergo pixel processing in unmodified form. The FILL, DRAV, LINE,
PIXT RS,*Rd, and PIXT RS,*Rd.XY instructions obtain their source pixels from
registers.
Figure 7-4 shows how special hardware in the local memory interface of the
TMS34010 applies the plane mask to pixel data during a read cycle. The pixel
size for this example is eight bits per pixel. This could represent the execution
of a PIXT *Rs.XY,Rd instruction, for instance.
Move thIS pIXel
Into a GSP register

(e) Original data In memory (2 plxele)
(b) Plane mask (PMASK)

(e) Data read Into GSP reglater

Notes:

1.
2.

7
B

8
A

o 11

o10

This example assumes eight bits per pixel.
The pixel moved into the GSP register is left justified. All register bits to the left of
the pixel are zero filled.

Figure 7-4. Read Cycle With Plane Masking

•

Figure 7 -4 a shows the 16-bit word containing the pixel as it is read
from memory.

•

The word is ANDed with the inverse of the plane mask shown in b.

•

The result in Figure 7 -4 c shows that the bits within the data word that
correspond to 1 s in the mask have been set to Os.

7-13

Graphics Operations - Plane Masking

After plane masking, the designated pixel is loaded into the eight LSBs of the
32-bit destination register, and the 24 MSBs of the register are filled with Os.
Figure 7-5 shows the effect of combining plane masking with pixel transparency. Again, the performance of the special hardware in the local memory
interface controller is demonstrated. The example shows the transfer of two
pixels during the course of a PixBlt operation with transparency enabled, the
pixel size set at eight bits, and the replace pixel processing operation. The
inverse of PMASK is ANDed with the source data, and transparency detection
is applied to the resulting entire pixel. In other words, the result is used to
control the write in the manner described in the previous discussion of pixel
transparency. Since the three LSBs of the source pixel in bits 8-15 are Os, and
the rest of the pixel is masked off, the entire source pixel is interpreted as
transparent. The memory interface logic generates an internal mask to govern
which bits are modified during a write cycle. This mask contains Os in the bits
corresponding to the transparent pixel.
(I) Original data In memory (2 pixels)

Cbl 8o..oe data In memory
(to be moved)
(01 Plene mask (PMASK)
(d) Mask source data for traneparency detection (SAC - ~
(el Tranaparency mask
(f) Combined mask ~. trane-

parenoy mask)

(g) Reaultlng memory data after

write cycle (Combined Mask.
SRC DATA + comblliid Milk-

15(MSBI
A A A

A A

7
B

O(LSBI
B B

OIJ

A A A

A A

IA
IV
I1

I0
I0
IA

I
Z I

1
0

A B

CST DATAl

Note: This example assumes eight bits per pixel.

Figure 7-5. Write Cycle With Transparency and Plane Masking

•
•
•
•
•

•

7-14

Figure 7-5 a shows the original data at the destination location.
b shows the source data.
In c, the source data is ANDed with the inverse of the plane mask.
d shows the intermediate result produced by c.
This result is used to generate the transparency mask in e, which is
ANDed with the inverse of the plane mask in c to produce the composite
mask shown in f.
The result in G is produced by replacing with the source only those bits
of the destination corresponding to 1s in the composite mask in f.

Graphics Operations - Pixel Processing

7.7 Pixel Processing
Source and destination pixel values can be combined according to the pixel
processing operation (or raster operation) selected. The TMS34010's pixel
processing operations include 16 Boolean and 6 arithmetic operations. The
Booleans are performed in bitwise fashion on operand pixels of 1, 2, 4, 8, or
16 bits. The arithmetic operations treat operand pixels of 4, 8, or 16 bits as
unsigned binary numbers.
When a pixel is read from its source location, it is arithmetically combined with
the corresponding destination pixel according to the Boolean or arithmetic
pixel processing option selected, and the result is written to the destination
pixel. The pixel processing operation is selected by the PPOP field in the
CONTROL register. Table 7-1 and Table 7-2 list the 22 PPOP codes and their
meanings.

Table 7-1. Boolean Pixel Processing Options
PPOP Field

Operation

00000

Source ...... Destination

00001

Source AND Destination ...... Destination

00010

Source AND - Destination ...... Destination

00011

Os ...... Destination

00100

Source OR - Destination ...... Destination

00101

Source XNOR Destination ...... Destination

00110

- Destination ...... Destination

00111

Source NOR Destination ...... Destination

01000

Source OR Destination ...... Destination

01001

Destination ...... Destination

01010

Source XOR Destination ...... Destination

01011

-Source AND Destination ...... Destination

01100

1s ...... Destination

01101

-Source OR Destination ...... Destination

01110

Source NAND Destination ...... Destination

01111

-Source ...... Destination

Table 7-2. Arithmetic (or Color) Pixel Processing Options
PPOP Field

Operation

10000

Source + Destination ...... Destination

10001

ADDS(Source, Destination) ...... Destination

10010

Destination - Source ...... Destination

10011

SUBS(Source, Destination) ...... Destination

10100

MAX(Source, Destination) ...... Destination

10101
1 011 0-11111

MIN(Source, Destination) ...... Destination
Reserved

7-15

Graphics Operations - Pixel Processing

In Table 7 -2, pixel processing codes 1 OOOO~ and 100102 correspond to standard 2s complement addition and subtraction. A result that overflows the
specified pixel size causes the pixel value to wrap around within its 4, 8, or
16-bit range. Carry bits are, however, prevented from propagating to adjacent
pixels.
The ADDS (add with saturation) and SUBS (subtract with saturation) operations shown in Table 7-2 produce results identical to those of standard addition or subtraction, except when arithmetic overflow occurs. When the
ADDS operation would produce an overflow result, the result is replaced with
all 1s. When the SUBS operation would produce an underflow result, the result is replaced with all Os.
The MAX operation shown in Table 7 -2 compares the source and destination
pixels and then writes the greater value to the destination location. The MIN
operation is similar, but writes the lesser value to the destination.
Figure 7 -6 depicts the interaction of pixel processing with other graphics operations when a source pixel is transferred to a destination pixel. Note that this
is a general description; some of these operations do not occur if they are not
selected. Pixels are first read from memory and modified by the plane mask.
Pixel processing is then performed on the modified pixel values. The plane
mask is applied to the result. Bits which are 1 s in the PMASK produce 0 bits
in the result of this process. Thus, some processed pixels may become transparent as the result of plane masking. Next, transparency detection is applied
to the data, and finally, a read-modify-write operation is invoked.

t Not performed if replace is selected.
t Only performed when plane masking or transparency is active and the pixel size is not
16, or the data being written is not word-aligned.

Figure 7-6. Graphics Operations Interaction

7-16

Graphics Operations - Boolean Processing Examples

7.8 Boolean Processing Examples
Figure 7-7 illustrates the effects of five commonly used Boolean operations
when applied to one-bit pixels. Black regions contain Os, and white regions
contain 1 s. Figure 7 -7 a and b show the original source and destination arrays. The source operand in a is the letter A, and the destination in b is a
calligraphic-style X.

(B) ORIGINAL DESTINATION
MRAY

(D) OR

•

(F) AND

(E) AND-NOT

(G) XOR

Figure 7-7. Examples of Operations on Single-Bit Pixels

7-17

Graphics Operations - Boolean Processing Examples

7.8.1

Replace Destination with Source
A simple replacement operation overwrites the pixels of the destination array
with those of the source. Figure 7 -7 c shows the letter A written over the
center portion of a larger X using the replace operation. The rectangular region
around the letter A obscures a portion of the X lying outside the A pattern.
Other operations allow only those pixels corresponding to the A pattern within
the rectangle to be replaced, permitting the background pattern to show
through. These are the logical OR and logical AND-NOT (NOT source AND
destination) operations. The replace-with-transparency operation performs
similarly in color systems.

7.8.2 logical OR of Source with Destination
Figure 7 -7 d illustrates the use of the logical OR operation during a PixBIt.
For a one-bit-per-pixel display, the OR function leaves the destination pixels
unaltered in locations corresponding to Os in the source pixel array. Destination pixels in positions corresponding to 1 s in the source are forced to 1 s.

7.8.3 logical AND of NOT Source with Destination
Logically ANDing the negated source with the destination is complementary
to the logical OR operation. Destination pixels corresponding to 1 s in the
source array remain unaltered, but those corresponding to Os in the source are
forced to Os. Figure 7-7 e is an example of the AND-NOT PixBlt operation
(notice the negative image of the letter A). For comparison, Figure 7 -7 f
shows the result of simply ANDing the source and destination.

7.8.4 Exclusive OR of Source with Destination
The XOR operation is useful in making patterns stand out on a screen in instances where it is not known in advance whether the background will be 1s
or Os. At every point at which the source array contains a pixel value of 1, the
corresponding pixel of the destination array is flipped - a 1 is converted to a
0, and vice versa. XOR is a reversible operation; by XORing the same source
to the same destination twice, the original destination is restored. These properties make the XOR operation useful for placing and removing temporary
objects such as cursors, and in "rubberbanding" lines. As seen in the example
of Figure 7 -7 g, however, the object may be difficult to see if both the source
and destination arrays contain intricate shapes.

7-18

Graphics Operations - Multiple-Bit Pixel Operations

7.9 Multiple-Bit Pixel Operations
The Boolean operations described in Section 7 .8 are sufficient for single - bit
pixel operations, but they may be inappropriate for multiple-bit pixel oper ations, especially when color is involved. For example, the result of a bitw ise - OR operation on a black - and - white (one bit per pixel) display is easily
predicted - DRing black and white yields white. However, the meaning of this
operation is less intuitive when it is applied to multiple-bit pixels. For example, in a population -density map, colors may be used to represent numeric
values. If one color, such as red , represents one level of population density,
and blue represents another, what happens when the two colors are bitwise - ORed? When pixels represent numeric values, numerical operations such
as addition and subtraction yield more useful results.
Boolean operations are usually inadequate for merging antialiased objects into
a single bit - mapped image. Older graphics systems that are limited to Boolean
operations on pixels are incapable of supporting many practical applications
on multiple - bit - per- pixel images. For instance, where two antialiased lines
cross, AND and OR operations yield chaotic pixel intensities that defeat the
purpose of the antial iasing . However, merging the two lines by means of the
GSP's MAX operation (for white on black) or MIN operation (for black on
white) yields a smooth and aesthetically pleasing image.

7.9.1

Examples of Boolean and Arithmetic Operations
Figure 7 -8 illustrates Boolean and arithmetic operations on multiple-bit pixels.
Figure 7 -8 a illustrates a source array that contains a red letter A ; the red pixels
have the value 8 (10002) and the black background pixels have the value 0
(00002) . Figure 7 - 8 b shows the destination array, a yellow X; the yellow
p ixels have the value 12 (11002) and the pixels in the blue background pixels
have the value 2 (00102) '
Boolean operations can be applied to multiple -bit pixels by combining the
corresponding bits of each pair of source and destination pixels on a bit - by - bit
basis according to the specified Boolean operation . Figure 7 -8 c through 9
show the effects of combin ing the source and destination arrays using the re place, OR , AND-NOT, AND, and XOR PixBlt operations. Compare these to
Figure 7-7 (page 7 - 17) .
Arithmetic operations treat 4 - bit, 8-bit, and 16-bit pixels as unsigned binary
numbers. An n-bit pixel represents a positive integer in the range 0 to 2n - 1
(all 1 s) . Examples of arithmetic operations on source and destination pixels
are shown in Figure 7 -8 i through n and discussed in Section 7 .9.1.1 through
Section 7 .9 .1.4.

(a) Source

(b) Destination

Figure 7-8. Examples of Boolean and Arithmetic Operations

7 -19

Graphics Operations - Multiple-Bit Pixel Operations

(e) Src Replaces Dst

(d) Src OR Dst

(e) Src AND Dst

(9) Src XOR Dst

(h) Replace with
Transparency

(i) Add

(i) Subtract

(k) Add with Saturation

(I) Subtract with
Saturation

(m) MAX

(n) MIN

(f)

Sr~

AND Dst

Figure 7-8 . Examples of Boolean and Arithmetic Operations (Concluded)

7 - 20

Graphics Operations - Multiple-Bit Pixel Operations

7.9.7.4 Figure 7-8 n - Minimum
Figure 7 - 8 n illustrates the results of the MIN operation on the source and
destination arrays . MIN compares two pixel values and replaces the destina tion pixel with the smaller value. MIN is similar to the Boolean AN D function.
MIN can be used with priority - encoded pixel values, similar to MAX, but the
effect is reversed . In Figure 7 -8 n, the priorities of the two objects are reversed
from that of the MAX example shown in Figure 7 - 8 m. The MIN operation
also has uses similar to those of MAX in smoothly comb ining ant ialiased ob jects that overlap.

7.9.2 Operations on Pixel Intensity
Figure 7 - 9 illustrates the visual effects of various PixBlt operations on two
intersecting disks. In these examples, each pixel is a four - bit value representing an intensity from 0 (black) to 15 (white). Before the PixBlt operation ,
only a single disk resides on the screen , as shown in Figure 7 - 9 a. The in tensity of the disk is greatest at the center (where the value is 12) , and grad ually falls off as the distance from the center increases. Figure 7 - 9 b through
f show the effects of combining a second, identical disk with the first. Figure
7 -9 b through e are produced using arithmetic operations; f is the result of a
logical OR of the source and destination. These operations are discussed in
Section 7 .9 .2.1 through Section 7.9 .2.4 .

(a) Original Disk

(b) Replace with Transparency

(d) Add with Saturate

(e) MAX

(f) OR

Figure 7-9. Examples of Operations on Pixel Intensity

7-22

Graphics Operations - Multiple-Bit Pixel Operations

7.9.1.4 Figure 7-8 n - Minimum
Figure 7-8 n illustrates the results of the MIN operation on the source and
destination arrays. MIN compares two pixel values and replaces the destination pixel with the smaller value. MIN is similar to the Boolean AND function.
MIN can be used with priority-encoded pixel values, similar to MAX, but the
effect is reversed. In Figure 7 -8 n, the priorities of the two objects are reversed
from that of the MAX example shown in Figure 7-8 m. The MIN operation
also has uses similar to those of MAX in smoothly combining antialiased objects that overlap.

7.9.2 Operations on Pixel Intensity
Figure 7-9 illustrates the visual effects of various PixBlt operations on two
intersecting disks. In these examples, each pixel is a four-bit value representing an intensity from 0 (black) to 15 (white). Before the PixBlt operation,
only a single disk resides on the screen, as shown in Figure 7-9 a. The intensity of the disk is greatest at the center (where the value is 12), and gradually falls off as the distance from the center increases. Figure 7 -9 b through
f show the effects of combining a second, identical disk with the first. Figure
7 -9 b through e are produced using arithmetic operations; f is the result of a
logical OR of the source and destination. These operations are discussed in
Section 7.9.2.1 through Section 7.9.2.4.

(a) Original Disk

(b) Replace with Transparency

(d) Add with Saturate

(e) MAX

(f) OR

Figure 7-9. Examples of Operations on Pixel Intensity

7-22

Graphics Operations - Multiple-Bit Pixel Operations

The gradual change in intensity at the edge of the disk in Figure 7 -9 a is similar
to the result produced by certain antialiasing techniques whose purpose is to
reduce jagged-edge effects. A text font might be stored in antialiased form,
for example, to give the text a smoother appearance. When two characters
from the font table are PixBlt'd to adjacent positions on the screen, they may
overlap slightly. The particular arithmetic or Boolean operation selected for the
PixBlt determines the way in which the antialiased edges of the characters are
combined within regions of overlap.

7.9.2.7 Figure 7-9 b - Replace with Transparency
In Figure 7-9 b, a second disk is PixBlt'd into a position near the first disk. A
replace-with-transparency operation is performed. Those pixels of the first
disk that lie within the rectangular region containing the second disk, but are
not part of the second disk, remain intact. The visual effect is that the second
disk (at the right) appears to lie in front of the original disk (at the left).
However, assuming that the gradual change in intensity at the perimeter of the
disks is done for the purpose of antialiasing, the sharp edge that results where
the second disk covers the first defeats this purpose. In other applications, this
sharp edge may be desirable; for example, it might be used to make a text
character or a cursor stand out from the background. The replace-withtransparency operation also supports object priority by writing objects to the
screen in ascending order of priority.

7.9.2.2 Figure 7-9 c - Add with Overflow and Subtract with Underflow
In Figure 7 -9 C, a second disk is PixBlt'd into an area overlapping the first disk,
using an add-with-overflow operation. In this example, when 1 is added to
an intensity of 15, the sum is truncated to four bits to produce the result O.
The effect of arithmetic overflow is visible at the intersection of the two disks
as discontinuities in intensity.
This effect is useful for making objects stand out against a cluttered background. Add with overflow has an additional benefit - the object can be removed by subtracting (with underflow) the object image from the screen.

7.9.2.3 Figure 7-9 d - Add and Subtract with Saturation
In Figure 7-9 d, the original disk is on the left. A second disk is PixBIt'd into
a region overlapping the original disk, using an add-with-saturate operation.
Whenever the sum of two pixels exceeds the maximum intensity value, which
is 15 for this example, the sum is replaced with 15. The bright region that
occurs where the two disks intersect is produced when the corresponding
pixels of the two disks are added in this manner. Subtract-with-saturate is the
complementary operation; when the difference of the two pixel values is negative, the sum is replaced by the minimum intensity value, O.
The add-with-saturate operation shown in Figure 7 -9 d approximates the effect of two light beams striking the same surface; the surface is brightest in the
area in which the two beams overlap.
These operations can be used to achieve an effect similar to that of an airbrush
in painting. Consider a display system that represents each pixel as 12 bits,
and dedicates four bits each to represent the intensities of the three color

7-23

Graphics Operations - Multiple-Bit Pixel Operations

components, red, green, and blue. This method permits the intensity of each
component to be directly manipulated. With each pass of the simulated airbrush over the same area of the screen, the color changes gradually toward the
color of the paint in the airbrush. For example, assume that the paint is yellow
(a mixture of red and green). Each time a pixel is touched by the airbrush, the
intensity of the red and green components is increased by 1, and the intensity
of the blue component is decreased by 1. With each sweep of the airbrush,
the affected area of the screen turns more yellow until the red and green
components reach the maximum intensity value (and are not allowed to overflow), and the blue component reaches 0 (and is not allowed to underflow).

7.9.2.4 Figure 7-9 e - MAX and MIN Operations
In Figure 7-9 e, the original disk is on the left. A second disk is PixBlt'd into
the rectangular region to its right using the MAX operation. In the region in
which the disks overlap, each pair of corresponding pixels from the two disks
is compared and the greater value is selected. This produces a relatively
smooth blending of the two disks. Unlike add with saturate, the MAX function
does not generate a "hot spot" where two objects intersect.
The visual effect achieved using the MAX operation is desirable in an application, for instance, in which white antialiased lines are constructed on top of
each other over a black background. MAX also smooths out places in which
the lines are overlapped by antialiased text. MAX is successful in maintaining
two visually distinct antialiased objects, while the add-with-saturate tends to
run them together.
MIN, which is complementary to MAX, can be used· similarly to smooth the
appearance of intersecting black antialiased lines and text on a white background.
The MAX and MIN operations are particularly useful in color applications in
which the number of bits per color gun is small (eight bits or less). Other
operators could also be used to smooth the transition between the two overlapping antialiased objects in Figure 7 -9 e, but any additional accuracy attained by using a more complex smoothing function would probably be lost
in truncating the result to the resolution of the integer used to represent the
intensity at each point.

7-24

Graphics Operations - Window Checking

7.10 Window Checking
The TMS34010's hardware window clipping confines graphics drawing operations to a specified rectangular window in the XY address space. Other
window checking modes cause an interrupt to be requested on a window hit
or a window miss.
Window checking affects only pixel writes performed by the following graphics instructions:
•

PIXBLT

•

FILL

•

LINE

•
•

DRAV
PIXT

Data writes by non-graphics instructions are not affected.
A window is a rectangular region of display memory specified in terms of the
XY coordinates of the pixels in its two extreme corners (minimum X and Y, and
maximum X and V). The corner pixels are considered to lie within the window.
Window checking is available only in conjunction with XY addressing; it is not
available with linear addressing. Specifically, the destination pixel address
must be an XY address.
One of four window checking modes is selected by the value loaded into the
W field of the CONTROL register:

W=O: Window checking disabled. No window checking is performed.
W=1: Window hit detection.
window.

Request interrupt on attempt to write inside

W=2: Window miss detection. Request interrupt on attempt to write outside
window.
W=3: Window clipping. Clip all pixel writes to window.
When window checking is enabled (modes 1,2 or 3), an attempt to write to
a pixel outside the window causes the V (overflow) bit in the status register
to be set to 1; a write (or attempt to write) to a pixel inside the window sets
V to O. When window checking is turned off (mode 0), the V bit is unaffected
during pixel writes.

7-25

Graphics Operations - Window Checking

7.10.1 W=1 Mode - Window Hit Detection
The W=1 mode detects attempts to write to pixels within the window. This
form of window checking supports applications which permit objects on the
screen to be picked by pointing to them with a cursor. In this mode, all pixel
writes are inhibited, whether they address locations inside or outside the
window. A window violation interrupt is requested on an attempt to write to
a pixel inside the window.
For the PIXBLT and FILL instructions, the V (overflow) bit is set to 1 if the
destination array lies completely outside the window. No interrupt request is
generated (the WVP bit in the INTPEND register is not affected) in this case.
However, if any pixel in the destination array lies within the window, the V
bit is set to 0 and a window violation interrupt is requested (the WVP bit is
set to 1). If the interrupt is enabled, the saved PC points to the instruction that
follows the PIXBLT or FILL that caused the interrupt. If the interrupt is disabled, execution of the next instruction begins.
While no pixel transfers occur during the PIXBLT and FILL instructions executed in this mode, the specified destination array is clipped to lie within the
window. In other words, the DADDR and DYDX registers are adjusted to be
the starting address, width, and height of the reduced array that is the intersection of the two rectangles represented by the destination array and the
window. This function can be adapted to determine the intersection of two
arbitrary rectangles on the screen - a calculation that is often performed in
windowed graphics systems.
In the case of a DRAV or PIXT instruction, an attempt to write to a pixel outside the window causes the V bit to be set to 1. No interrupt request is generated (the WVP bit is not affected). An attempt to write to a pixel inside the
window causes the V bit to be set to 0, and a window violation interrupt request is generated (the WVP bit is set to 1).
At the end of a LINE instruction, the V bit is 0 if any destination pixel processed by the instruction lies within the window; otherwise, V is 1. Attempts
to write to pixels outside the window do not cause interrupt requests to be
generated (the WVP bit is not affected). An attempt to write to a pixel inside
the window causes a window violation interrupt to be requested (the WVP
bit is set to 1) and the LINE instruction aborts. If the interrupt is enabled, the
PC saved during the interrupt points to the instruction that follows the LINE
instruction. If the interrupt is disabled, execution of the next instruction begins.
The W=1 mode can be used to pick an object on the screen by means of the
following simple algorithm. An object previously drawn on the screen is
picked by moving the cursor to the object's position and selecting it. To determine which object is pointed to, the software first sets the window to a
small region surrounding the position of the cursor. The software next steps
a second time through the same display list used to draw the current screen
until one of the objects causes a window interrupt to occur. This should be
the object pointed to by the cursor. If no object causes an interrupt, the pick
window can be enlarged and the process repeated until the object is found.
If two objects cause interrupts, the size of the pick window can be reduced
until only one object causes an interrupt.

7-26

Graphics Operations - Window Checking

7.10.2 W=2 Mode - Window Miss Detection
The W=2 mode permits a PIXBlT or Fill instruction to be aborted if any pixel
in the destination array lies outside the window. The destination array is
written only if the array lies entirely within the window, in which case the V
(overflow) bit is set to 0, and no interrupt request is generated (the WVP bit
is not affected). If any pixel in the destination array lies outside the window,
the V bit is set to 1, and a window violation interrupt is requested (the WVP
bit is set to 1).
For the DRAV and PIXT instructions, the destination pixel is drawn only if it
lies within the window. In this case, the V bit is set to 0, and no interrupt request is generated (the WVP bit is not affected). If the destination location
lies outside the window, the pixel write is inhibited, the V bit is set to 1, and
a window violation interrupt is requested (the WVP bit is set to 1).
At the end of a LINE instruction, the V bit is 0 if the last destination pixel
processed by the instruction lies within the window; otherwise, V is 1. Attempts to write to pixels inside the window do not cause interrupt requests to
be generated (the WVP bit is not affected). An attempt to write to a pixel
outside the window causes a window violation interrupt to be requested (the
WVP bit is set to 1) and the instruction aborts. If the interrupt is enabled, the
PC saved during the interrupt points to the instruction that follows the LINE
instruction. If the interrupt is disabled, execution of the next instruction begins.

7.10.3 W=3 Mode - Window Clipping
In the W=3 mode, only writes to pixels within the window are permitted;
writes to pixels outside the window are inhibited. No interrupt request is
generated for any case.
For a PIXBlT or Fill instruction, only the portion of the destination array lying within the window is drawn. At the start of instruction execution, the
specified destination array is automatically preclipped to lie within the window
before the first pixel is transferred. Hence, no execution time is lost attempting
to write destination pixels which lie outside the window. In the case of a
PIXBlT, the source array is preclipped to fit the adjusted dimensions of the
destination array before the transfer begins.
During execution of a DRAV or PIXT instruction, a write to a pixel inside the
window is permitted, and the V bit is set to O. An attempted write to a pixel
outside the window is inhibited, and the V bit is set to 1.
For the LINE instruction, writes to pixels outside the window are inhibited at
drawing time; no preclipping is performed. The value of the V bit at the end
of a LINE instruction is determined by whether the last pixel calculated by the
instruction fell inside (V=O) or outside (V=1) the window.

7-27

Graphics Operations - Window Checking

7.10.4 Specifying Window Limits
The limits of the current window are specified in the WSTART (window start)
and WEN D (window end) registers. WSTART specifies the minimum XY coordinates in the window, and WEND specifies the maximum XY coordinates.

As Figure 7-10 shows, WSTART specifies the XY coordinates (Xstart,Ystart)
at the upper left corner of the window, and WEND specified the XY coordinates (Xend, Yend) at the bottom right corner of the window. The origin is located in its default position in the top left corner of the screen.
OIapIay

Memory

r+Y

WindoW

A pixel with coordinates (X,V)
Ilea within the window If both
X start S X S Xend and Y Itart S Y S Yend

Figure 7-10. Specifying Window Limits
Figure 7-10 shows that a pixel that has coordinates (X,Y) lies within the
window if Xstart S; X S; Xend and Ystart S; Y S; Yend. If a pixel does not meet
these conditions, it lies outside the window.
When Xstart > Xend or Ystart> Yend, the window is empty; that is, it contains
no pixels. Under these conditions, the window checking hardware detects all
destination pixel addresses as lying outside the window. Note that the conditions Xstart = Xend and Ystart = Yend together specify a window containing
a single pixel.
Window start and end coordinates must lie in the range (0,0) to
(+32767,+32767). A window cannot contain pixels with negative X or Y
coordinates.

7-28

Graphics Operations - Window Checking

7.10.5 Window Violation Interrupt
A window violation (WV) interrupt is requested (the WVP bit in the INTPEND
register is set to 1) when:
•
•

W=1 and an attempt is made to write to a pixel inside the window or
W=2 and an attempt is made to write to a pixel outside the window

The interrupt occurs if it is enabled by the following conditions:
•
•

The WVE bit in the INTENB register is 1
The IE bit in the status register is 1

Alternatively, if the WV interrupt is disabled (IE=O or WVE=O), the window
violation can be detected by testing the value of either the V bit in the status
register or the WVP bit following the operation.
When a WV interrupt occurs, the registers that change during the LINE,
PIXBLT and FILL instructions contain their intermediate values at the time the
violation was detected.

7.10.6 Line Clipping
The TMS34010 supports two methods for clipping straight lines to the
boundaries of a rectangular window: postclipping and preclipping. Postclipping means that just before each pixel on the line is drawn, it is compared with
the window limits. If it lies outside the window, the write is inhibited. In
contrast, preclipping involves determining in advance of any drawing operations which pixels in the line lie within the window. The algorithm draws
only these pixels, and makes no attempt to write to pixels outside the window.
A preclipped line may take less time to draw since no calculations are performed for pixels lying outside the window. In contrast, postclipping spends
the same amount of time calculating the position of a pixel outside the window as it does calculating a pixel inside the window.
When postclipping is used, special window comparison hardware compares
the coordinates of the pixel being drawn against all four sides of the window
at once. The W=3 window-checking mode is selected, and window checking
is performed in parallel with execution of the LINE instruction, so no overhead
is added to the time to draw a pixel. However, unless this form of clipping is
used carefully, another type of overhead may become significant. For example,
in a CAD (computer-aided design) environment where only a small portion
of a system diagram is to be displayed at once, potentially a great deal of time
could be spent performing calculations for points (or entire lines) lying offscreen.
Preclipping is generally faster than postclipping, depending on how likely a
line is to lie outside the window. The first step in preclipping a series of lines
is to identify those that lie either entirely inside or outside the window. This
is accomplished by using an "outcode" technique similar to that of the Cohen-Sutherland algorithm. Those lines lying entirely outside are "trivially rejected" and consume no more processing time. Those lines lying entirely
within are drawn from one endpoint to the other with no clipping required.
This still leaves a third category of lines that may cross a window boundary,
and these require intersection calculations. However, this technique is pow7-29

Graphics Operations - Window Checking

erful for reducing the number of lines that require such calculations. While the
calculation of outcodes could be performed in software, this would represent
significant overhead for each line considered. The TMS3401 0 provides a more
efficient implementation via its CPW (compare point to window) instruction,
which compares a point to all four sides of the window at once.
The outcode technique classifies a line according to where its endpoints fall
in relation to the current clipping window. The area surrounding the window
is partitioned into eight regions, as indicated in Figure 7 -11. Each region is
assigned a 4-bit code called an outcode. The outcode within the window is
00002' When an endpoint of a line falls within a particular region, it is assigned the outcode for that region. If the two endpoints of a line both have
outcodes 00002, the line lies entirely within the window. If the bitwise AND
of the outcodes of the two endpoints yields a value other than 00002, the line
lies entirely outside the window. Lines that fall into neither of these categories
mayor may not be partially visible within the window.

0101

0100

0001

0000

,,: 0110
,,
,,
---------+-----;'---------- V. V MIN
0010

+-...,.--t---------- V = V MAX
1010
Window

X=XMIN

X"XMAX

Figure 7-11. Outcodes for Line Endpoints
For those lines that require intersection calculations after the outcodes have
been determined, midpoint subdivision is an efficient means of preclipping.
The object again is to ensure that drawing calculations are performed only for
pixels lying within the window. An example of the midpoint subdivision
technique is illustrated in Figure 7 -12. The line AB lies partially within the
window. The first step is to determine the coordinates of the line's midpoint
at C. These are calculated as follows:
(Xc' YC) =

7-30

+ XB
2

+ YB
2

Graphics Operations - Window Checking

J - - - - - - - - - ! I ! f - - V = V MAX
X=XMlN

X=XMAX

v ) =(~
VA +VB)
2'
2

C' C

(XO,V O) =~A;XC,VA2VC)

Figure 7-12. Midpoint Subdivision Method
Comparing the outcodes of Band C, segment BC lies entirely outside the
window and can be trivially rejected. Segment AC still lies partially within the
window and will be subdivided again. The coordinates of point D, the midpoint of AC, are calculated as before. Point D is determined to lie within the
window. The LINE instruction is now invoked two times, for segments DC
and DA, with D selected as the starting point in each case. For each segment
the W=2 window-checking mode is selected, but the window violation interrupt is disabled. When each line crosses the window boundary, the window-checking hardware detects this and the LINE instruction aborts. In this
way the LINE instruction performs drawing calculations only for portions of
DA and DC lying within the window.

7-31

Graphics Operations

7-32

Section 8

Interrupts, Traps, and Reset

The TMS3401 0 supports eight interrupts, including reset. Memory addresses
FFFFFCOOh to FFFFFFFFh contain the 32 vector addresses used during interrupts, software traps and reset. Each vector is a 32-bit address that points
to the beginning of the appropriate interrupt service routine.
This section includes the following topics:
Section
Page
8.1 Interrupt Priorities and Vector Addresses ............................................... 8-2
8.2 Interrupt Interface Registers ..................................................................... 8-3
8.3 External Interrupts ...................................................................................... 8-3
8.4 Internal Interrupts ...................................................................................... 8-5
8.5 Interrupt Processing .................................................................................. 8-6
8.6 Traps ............................................................................................................ 8-9
8.7 Illegal Opcode Interrupts .......................................................................... 8-9
8.8 Reset ......................................................................................................... 8-10

8-1

Interrupts, Traps, and Reset - Interrupt Priories and Vector Addresses

8.1 Interrupt Priorities and Vector Addresses
Table 8-1 and Figure 8-1 summarize the TMS3401 0 interrupt vector addresses
and the interrupt priorities. RESET has the highest priority. and the illegal opcode interrupt has the lowest. If two interrupts are requested at the same time.
the highest priority interrupt is serviced first (assuming it is enabled). RESET
and the nonmaskable interrupt cannot be disabled.

Table 8-1. Interrupt Priorities
Int.

Priority

Internal/
External

Reset

NMI

HI
01

3
4

I
I

INT1

INT2
ILLOP

E
I

Description and Source

Device reset. Taken when the input signal at the
RESET pin is asserted low.
Nonmaskable interrupt. Generated by a host
processor.
Host interrupt. Generated by a host processor.
Display interrupt. Generated by the TMS3401 O.
Window violation interrupt. Generated by the
TMS34010.
External interrupts 1 and 2. Generated by
external devices.
Illegal opcode interrupt. Generated by the
TMS34010 when an illegal opcode is encountered.

T...

~
0

~
OFFFFFfEOh

OFFFFFFCOh
OFfFFfFAOh

He'"
External Interrupt ,

INTI
INT2

ExteI'MI Interrupt 2

OFFFFFF80h

OFfFFfF80h
OFFFFFF40h

Traps 3·7

OFFFFFF2Oh

OFFFFFFOOh
OFFFFfEEOh
OFFFfFECOh
10
II
12
13
14
IS
I.

OFFFFFEAOh

OFFFfFDCOh

18
19
20
21
22
23

OFFFFFDAOh

24
2S
2.
27
28
29

30
31

OFFFfFE8Oh
OFFFfFE8Oh
OFFFfFE4Oh

MNI
HI
DI

Non.......bIe

WIndowV~

Hoat

In~pt

DIsplay Interrupt

OFFFFFE20h
OFFFFFEOOh
OFFFFFDEOh

OFFFfFD8Oh
OFFFFFD6Qh
OFfFfFD4Oh

T'8PS12 29
K

OFFFFFD20h
OFfFfFDOOh
OFFFFFCEOh
OFFFfFCCOh

OFFFFFCAOh
OFFFfFC80h
OFFFfFC8Oh
OFfFfFC4Oh
OFfFFfC20h
OFFFFFCOOh

ILl.OP
31

1_IOpcodo

1---32~
Figure 8-1. Vector Address Map

8-2

Interrupts, Traps, and Reset - Registers/External Interrupts

8.2 Interrupt Interface Registers
Two registers, a subset of the I/O registers discussed in Section 6, monitor and
mask interrupt requests. These registers are summarized below; for more information, please refer to the register descriptions in Section 6.
The interrupt enable register, INTEN B, contains the interrupt mask that selectively enables various interrupts. An interrupt is enabled when the status
IE (global interrupt enable) bit qnd the appropriate bit in the INTENB register
are both set to 1 .

•
•

•
•
•

X1 E (bit 1) enables external interrupt 1.
X2E (bit 2) enables external interrupt 2.
HIE (bit 9) enables the host interrupt.
DIE (bit 10) enables the display interrupt.
WVE (bit 11) enables the window violation interrupt.

The interrupt pending register, INTPEND, indicates which interrupts are currently pending. When an interrupt is requested, the appropriate bit in the
INTPEND register is set.

•
•

•
•
•

X1 P (bit 1) indicates that external interrupt 1 is pending.
X2P (bit 2) indicates that external interrupt 2 is pending.
HIP (bit 9) indicates that the host interrupt is pending.
DIP (bit 10) indicates that the display interrupt is pending.
WVP (bit 11) indicates that the window violation interrupt is pending.

8.3 External Interrupts
External interrupt requests are received through input pins L1NT1 and L1NT2.
The two request pins are level-sensitive, active-low inputs. Each pin is dedicated to an individual interrupt, allowing two independent interrupt requests
to be generated. (The pins are not encoded.) The state of the L1NT1 and
L1NT2 inputs is reflected in the X1 P and X2P bits in the INTPEND register.
The register bit is 1 if the corresponding request is active.
The interrupts generated by requests at the L1NT1 and L1NT2 inputs are referred
to as INT1 and INT2. Interrupts INT1 and INT2 are selectively enabled by
means of the X1 E and X2E bits in the INTENB register. If external interrupt
requests become active at L1NT1 and L1NT2 at the same time, and both interrupts are enabled, INT1 will be serviced first. If one or both of these interrupts
is disabled, the state of the L1NT1 and L1NT2 inputs continues to be reflected
in the X1 P and X2P bits. These bits may be polled by software to detect
transitions at the interrupt inputs.
Table 8-2 shows the interrupt trap vectors for INT1 and INT2.

8-3

Interrupts, Traps, and Reset - External Interrupts

Table 8-2. External Interrupt Vectors
Name

INT1
INT2

Input
Pin
LlNT1
LlNT2

Vector
Address
FFFFFFCOh
FFFFFFAOh

Once an interrupt request has been initiated by driving an interrupt request pin
low, the input should continue to be driven low until the interrupt service
routine can respond to the interrupting device. If the interrupt pin is permitted
to go inactive high before it has been recognized by the interrupt service routine, the request may be missed. If the active level is maintained after returning
from the interrupt service routine, however, the interrupt will be taken once
again.
The RETI instruction restores the ST (status) and PC (program counter) registers to their original state just prior to the interrupt. (This would not be the
case, however, if for some reason the values for these registers, saved on the
stack, were altered by the interrupt service routine). Assuming that the IE bit
in the restored ST is a 1, interrupts are again enabled by the time the RETI instruction finishes executing. If an interrupt request is active during the last
state of the RETI instruction, and the interrupt is enabled in the INTENB register, the interrupt will be taken immediately following the RET!.
The interrupt service routine typically writes to the interrupting device to clear
the interrupt· request before executing an RETI (return from interrupt) instruction. An example of the last three instructions in a typical interrupt service
routine is shown below, where DEVICE is the symbolic address of the interrupting device:
CLR
MOVE
RETI

AO
AO,@DEVICE

The interrupt request is cleared by the MOVE instruction above, which writes
a 0 to the device address. The maximum asynchronous delay from the end of
the write cycle (measured from the low-to-high transition of iN) to the resulting low-to-high transition at the GSP's interrupt request input should be no
more than six local clock periods.
Signals input to the local interrupt pins are assumed to be asynchronous to the
GSP local clocks, and are synchronized internally by the GSP before they are
processed. The GSP samples the state of the LlNT1 and LlNT2 inputs at each
high-to-Iow transition of LCLK1, and updates the X1 P and X2P bits in the
INTPEND register accordingly (an active-low input is seen as a one in the
appropriate register bit). The delay from the transition at the input to the
corresponding change in the X1 P or X2P bit is from one to two states, depending on the transition's phase relationship to LCLK1.

8-4

Interrupts, Traps, and Reset - Internal Interrupts

8.4 Internal Interrupts
Several internal conditions are associated with specific interrupts. Table 8-3
summarizes these interrupts. If two internal interrupts are requested simultaneously, or if two or more internal interrupt requests are pending, the highest
priority interrupt is serviced first; NMI has the highest priority, followed by HI,
01, and WV. When internal and external interrupts are pending, the internal
interrupts are serviced first (with the exception of the ILLOP interrupt).
Table 8-3. Interrupts Associated with Internal Events
Name
NMI

Function

Level

Vector
Location

FFFFFEEOh

FFFFFECOh

Description

Nonmaskable
interrupt
Host interrupt

The host processor sets the NMI bit in the
HSTCTL register to a 1.
The host processor sets the INTIN bit in the
HSTCTL register to a 1.
A particular horizontal line on the video display
is being refreshed. The line number is specified
in the DPYINT register.

Display interrupt

FFFFFEAOh

Window violation
interrupt

FFFFFE80h

An attempt has been made to move a pixel to a
destination location that lies inside or outside a
specified window, depending on the selected
windowing mode.

ILLOP

Illegal operand
interrupt

FFFFFC20h

See Section 8.7.

The nonmaskable interrupt, or NMI, occurs when a host processor requests
an interrupt by writing a 1 to the NMI bit in the HSTCTL register. This interrupt cannot be disabled, and always occurs as soon as possible following the
request. The NMI is delayed only for completion of an instruction already in
progress, or until the next interruptible point of an interruptible instruction
such as a PIXBLT is reached.
The NMI mode bit in the HSTCTL register determines whether or not context
information is saved on the stack when a nonmaskable interrupt occurs:
•

If NMIM = 0, the PC and ST are pushed on the stack before the interrupt
is serviced.

•

If NMIM = 1, nothing is saved on the stack before the interrupt is serviced.

The TMS3401 0 automatically clears the NMI bit at the time it takes the interrupt. After setting the NMI bit, the host processor can determine when the
TMS34010 has taken the interrupt by polling the NMI bit until it changes from
a 1 to a O.
The display interrupt (01) is used to coordinate processing activity with the
refreshing of particular areas of the display. The display interrupt request becomes active when a particular display line, specified in the OPYINT register,
is output to the monitor screen. At the start of each horizontal blanking period,
the VCOUNT register is compared to the OPYINT register. When the vertical
count value in VCOUNT = OPYINT, a display interrupt request is generated.
If enabled, the interrupt is taken.

8-5

Interrupts, Traps, and Reset - Interrupt Processing

8.5 Interrupt Processing
An interrupt is said to be pending if it has been requested but has not yet been
processed. If a pending interrupt is enabled, and no interrupt of higher priority
is pending at the same time, the interrupt is accepted by the TMS3401 0 at the
end of the current instruction (or at the next interruptible point in the middle
of a PIXBLT or FILL instruction). When the TMS3401 0 takes an interrupt, it
performs the following actions:
1)

The TMS3401 0 pushes the PC on the stack.

The TMS34010 pushes the ST on the stack. PIXBLT and FILL instructions that are interrupted by external, host, and nonmaskable (if
NMIM=O) interrupts set the PBX bit in the ST before pushing the ST.

The TMS3401 0 modifies the contents of the ST as follows:

The TMS34010 fetches the interrupt vector from external memory into
the PC.

The TMS3401 0 begins executing the instruction pointed to by the new
PC value.

In step 5, the TMS3401 0 resumes instruction execution at the entry point of
the interrupt service routine. At the time the first instruction of the service
routine begins execution, the new status register contents imply the following
conditions:
•
•
•

All interrupts are disabled (except NMI and reset)
Field 0 is 16 bits long and is zero extended
Field 1 is 32 bits long and is zero extended

The service routine can allow itself to be interrupted by loading a new interrupt-enable mask into the I NTEN B register and setting status bit I E to 1. The
INTENB mask value is selected to determine which interrupts can interrupt the
currently executing service routine. The service routine can also load new field
sizes if values other than the defaults are required.
The last instruction in any interrupt service routine must be RETI (return from
interrupt). Unlike the RETS (return from subroutine) instruction, which only
pops the PC from the stack, RETI pops both the ST and PC. This restores the
original state of the interrupted program so that execution can proceed from
the point at which the interrupt occurred.

8-6

Interrupts, Traps, and Reset - Interrupt Processing

8.5.1

Interrupt Latency
An external interrupt, host interrupt request, or N M I request is delayed by an
amount of time that depends on the instruction in progress and on the local
memory bus traffic at the time of the request.
The delay from an interrupt request to the time that the first instruction of the
interrupt service routine begins execution is the sum of six potential sources
of delay:
1)
2)
3)
4)
5)
6)

Interrupt request recognition
Screen-refresh cycle
DRAM-refresh cycle
Host-indirect cycle
Instruction interrupt
Interrupt context switch

In the best case, items 2 through 5 cause no delay. The minimum delay due
to items 1 and 6 is 17 machine states.
•

The interrupt request recognition delay is the time required for a
request to be internally synchronized to the local clock. In the case of
an external interrupt request, the delay is measured from the high-to-Iow
transition of the INT1 or INT2 pin. In the case of a host interrupt or NMI
request, the delay is measured from completion of the host's write to the
INTIN or NMI pin.

•

The screen-refresh and DRAM-refresh cycles are a potential source
of delay, but in fact occur rarely and are unlikely to delay an interrupt.

•

The likelihood of a delay caused by a host-indirect cycle is small in
most instances, but this depends on the application. The delay due to a
single host-indirect cycle is two machine states, assuming no wait states,
but multiple host-indirect cycles occurring within a brief period of time
could cause additional delays. Theoretically, a fast host processor could
generate so many local memory cycles that the TMS34010 would be
prevented from servicing interrupts for an indefinite period.

•

The instruction interrupt time refers to the time required for an instruction that was already executing at the time the interrupt request was
received to either complete or to reach the next interruptible point in an
instruction (such as a PIXBLT, FILL, or LINE).

•

The interrupt context switch operation pushes the PC and ST onto
the stack, and fetches the PC for the interrupt service routine from the
appropriate vector in memory.

Table 8-4 shows the minimum and maximum times for each of the six operations listed. The interrupt latency is calculated as the sum of the numbers in
the six rows. In the best case, the interrupt latency is only 17 machine states.
The worst-case latency can be as high as 22 machine states plus the delays
due to host-indirect cycles and instruetion completion. Table 8-5 shows instruction interrupt times for some of the longer, noninterruptible instructions.
Table 8-5 also shows the instruction completion time for a JRUC instruction

8-7

Interrupts, Traps, and Reset - Interrupt Processing

that jumps to itself - the TMS3401 0 may be executing this instruction if the
software is simply waiting for an interrupt.

Table 8-4. Six Sources of Interrupt Delay
Operation

Latency (In States)
Min

Max

Interrupt recognition

Instruction interrupt

See Table 8-5

DRAM-refresh cycle

2
See Note 2

Screen-refresh cycle

2
See Note 2

Host-indirect cycle

See Note 1

Interrupt context switch

Notes:

1) The latency due to host-indirect cycles depends on both the
hardware system and the application. Theoretically, a host processor could generate so many local memory cycles that the
TMS34010 could effectively be prevented from servicing interrupts. The delay due to a single host-indirect cycle is two machine
states, assuming no wait states.
2) DRAM-refresh and screen-refresh cycle times assume no wait
states.
3) Context switch time assumes that the SP is aligned to a word
boundary; that is, the four LSBs of the SP are Os. If the SP is not
aligned, the delay is 28 states.

Table 8-5. Sample Instruction Completion Times
Instruction

Worst-Case Instruction
Interrupt Time (In States)
SP Aligned
43

MMFM SP,ALL

144

MMTM SP,ALL

169

Wait: JRUC wait

Notes:

8-8

SP Not Aligned

DIVS AO,A2

1) The worst-case Instruction Interrupt time 15 equal to the instruction
execution time less one machine state (except for PIXBLTs, FILLs,
and LINE).
2) The SP-aligned case assumes that the SP is aligned to a word
boundary in memory.

Interrupts, Traps, and Reset - Traps/Illegal Opcodes

8.6 Traps
The TMS34010 supports 32 software traps, numbered 0 through 31. Software traps behave similarly to interrupts, except that they are initiated when
the TMS34010 executes a TRAP instruction. Unlike an interrupt, a software
trap cannot be disabled.
When the TMS34010 executes a TRAP instruction, it performs the same sequence of actions that it performs for interrupts. The TRAP 1 through TRAP
31 instructions cause the status register and the PC to be pushed onto the
stack. TRAP 0 is similar to a hardware reset because it does not push the
status register or PC onto the stack; it differs from a hardware reset because it
does not cause the TMS3401 O's internal registers to be set to a known initial
state. TRAP 8 is similar to an NMI interrupt, except that the NMIM (NMI
mode) bit in the HSTCTLL register has no effect on instruction execution; the
status register and PC are stacked unconditionally when TRAP 8 is executed.
A 32-bit vector address is associated with each software trap. To determine
the vector address for a trap number N, where N = 0 through 31, subtract
32N from FFFFFFEOh. Figure 8-1 on page 8-2 shows the vector addresses
for the software traps.

8.7 Illegal Opcode Interrupts
The TMS3401 0 recognizes several reserved opcodes as illegal. When one of
these opcodes is encountered in the instruction stream, the TMS3401 0 traps
to vector number 30, located at memory addressFFFFFC20h. An illegal opcode is similar in effect to a TRAP 30 instruction. The illegal opcode interrupt
cannot be disabled. Table 8-6 lists ranges of illegal opcodes.

Table 8-6. Illegal Opcodes Ranges
0200h
0400h
0800h
OAOOh
OCOOh
OEOOh
3400h
7000h
9EOOh
BEOOh
D800h
FEOOh

through
through
through
through
through
through
through
through
through
through
through
through

02FFh
04FFh
08FFh
OAFFh
OCFFh
OEFFh
37FFh
7FFFh
9FFFh
BFFFh
DEFFh
FFFFh

8-9

Interrupts, Traps, and Reset - Reset

8.8 Reset
Reset puts the TMS3401 0 into a known initial state that is entered when the
input signal at the RESET pin is asserted low. RESET must remain active low
for a minimum of 40 local clock (LCLK1 or LCLK2) periods to ensure that the
TMS34010 has sufficient time to establish its initial internal state. While the
reset signal remains asserted, all outputs are in a known state, no DRAMrefresh cycles take place, and no screen-refresh cycles are performed.
At the low-to-high transition of the RESET signal, the state of the HCS input
determines whether the TMS3401 0 is halted (host-present mode) or whether
it begins executing instructions (self-bootstrap mode):

•

Host-Present Mode
If HCS is high at the end of reset, TMS34010 instruction execution is
halted and remains halted until the host clears the H LT (halt) bit in
HSTCTL (host control register). Following reset, the eight RAS-only
refresh cycles required to initialize the dynamic RAMs are performed
automatically by the TMS3401 0 memory control logic. As soon as the
eight RAS-only cycles are completed, the host is allowed access to
TMS34010 memory. At this time, the TMS34010 begins to automatically perform DRAM refresh cycles at regular intervals. The TMS3401 0
remains halted until the host clears the HLT bit. Only then does the
TMS34010 fetch the level-O vector address from location FFFFFFEOh
and begin executing its reset service routine.

•

Self-Bootstrap Mode
If HCS is low at the end of reset, the TMS3401 0 first performs the eight
RAS-only refresh cycles required to initialize the DRAMs. Immediately
following the eight RAS-only cycles, the TMS3401 0 fetches the level-O
vector address from location FFFFFFEOh, and begins executing its reset
service routine.

Unlike other interrupts and software traps, reset does not save previous ST or
PC values. This is because the value of the stack pointer just before a reset is
generally not valid, and saving its value on the stack is unnecessary. A TRAP
o instruction, which uses the same vector address as reset, similarly does not
save the ST or PC values.

S.S.1 Asserting Reset
A reset is initiated by asserting the RESET input pin at its active-low level. To
reset the TMS3401 0 at power up, RESET must remain active low for a minimum of 40 local clock periods after power levels have become stable. At times
other than power up, the TMS3401 0 is also reset by holding RESET low for a
minimum of 40 clock periods. The 40-clock interval is required to bring
TMS34010 internal circuitry to a known initial state. While RESET remains
asserted, the output and bidirectional signals are driven to a known state.
The TMS34010 drives its RAS signal inactive high as long as RESET remains
low. The specifications for certain DRAM and VRAM devices, including the
TMS4161, TMS4164 and TMS4464 devices, require that the RAS signal be
driven inactive-high for 100 microseconds during system reset. Holding the
RESET signal low for 150 microseconds causes the RAS signal to remain high
8-10

Interrupts, Traps, and Reset - Reset

for the 100 microseconds required to bring the memory devices to their initial
states. DRAMs such as the TMS4256 specify an initial RAS high time of 200
microseconds, requiring that RESET be held low for 250 microseconds. In
general, holding RESET low for t microseconds ensures that RAS remains high
initially for t - 50 microseconds.

8.8.2 Suspension of DRAM-Refresh Cycles During Reset
An active-low level at the RESET pin is considered to be a power-up condition,
and DRAM refresh is not performed until RESET goes inactive high. Consequently, the previous contents of the local memory may not be valid after a
reset.

8.8.3 State of VCLK During Reset
In many systems, the VCLK pin continues to be clocked during reset. However, a system in which VCLK is not clocked during reset should maintain
VCLK at the logic high level while it is not being clocked. This is necessary
to ensure that the video counters are reset properly. In fact, VCLK should be
held at the logic high level when it is not being clocked regardless of whether
the device is being reset. While VCLK is low, storage nodes in the VCOUNT
and HCOUNT registers rely on their internal capacitance to maintain their
state. If VCLK remains low for a sufficiently long period, these registers are
subject to bit errors due to charge leakage.

8.8.4 Initial State Following Reset
While the RESET pin is asserted low, the TMS3401 O's output and bidirectional
pins are forced to the states listed in Table 8-7.

Table 8-7. State of Pins During a Reset
Outputs Driven
To High level

Outputs Driven
To Low Level

DDOUT
HRDyt
DEN
LAL
TR/ill
RAS
CAS

BLANK

Bidirectional
Pins Driven to
High Impedance
HSYNC
VSYNC
HDG-HD15
LADG-LAD15

HINT
HLDA/EMUA
HRDY will stay high during reset if the HCS mput is also high.

Immediately following reset, all I/O registers are cleared (set to OOOOh), with
the possible exception of the HLT bit in the HSTCTL register. The HLT bit is
set to 1 if HCS is high just before the low-to-high transition of RESET.

8-11

Interrupts, Traps, and Reset - Reset

Just before execution of the first instruction in the reset routine, the
TMS34010's internal registers are in the following state:
•

General-purpose register files A and Bare uninitialized.

•

The ST is set to 00000010h.

•

The PC contains the 32-bit vector fetched from memory address
FFFFFFEOh.

The instruction cache is in the following state at this time:
•

The SSA (segment start address) registers are uninitialized.

•

The LRU (least recently used) stack is set to the initial sequence 0,1,2,3,
where 0 occupies the most-recently-used position, and 3 occupies the
least -recently- used position.

•

All P (present) flags are cleared to Os.

S.S.5 Activity Following Reset
Immediately following the low-to-high transition of RESET, the TMS34010
performs a series of eight RAS-only memory cycles to bring the DRAMs and
VRAMs to their initial operating states. These cycles are completed before any
accesses of the TMS34010's memory (by either the TMS3401 0 or host processor) are allowed to occur. If the host processor attempts to access the
TMS34010 memory indirectly before the eight RAS-only cycles have completed, it receives a not-ready signal from the TMS3401 0 until the cycles have
completed. The eight RAS-only cycles occur regardless of the initial value to
which the H LT bit in the HSTCTL register is set.
Each of the eight RAS-only cycles is a standard DRAM-refresh cycle. The RF
bus status signal output with the row address is active low. The row address
is all Os.
Following the eight RAs-only cycles, the TMS3401 0 automatically begins to
initiate a new DRAM-refresh cycle every 32 TMS34010 local clock cycles.
The first DRAM refresh cycle begins approximately 32 local clock periods after
the end of reset. A DRAM-refresh cycle is initiated every 32 TMS3401 0 clock
cycles until the DRAM-refresh rate is changed by the TMS34010 or host
processor.
The TMS3401 0 is configured by means of an external signal input on the HCS
pin to either:

8-12

•

Begin executing instructions immediately after reset is completed (selfbootstrap mode), or

•

Halt until the host processor instructs it to begin executing (host-present
mode).

Interrupts, Traps, and Reset - Reset

8.8.5.1 Self-Bootstrap Mode
In self-bootstrap mode, the TMS34010 begins executing instructions immediately following reset. This mode is typically used in a system in which the
reset vector and reset service routine are contained in nonvolatile memory,
such as a bootstrap ROM. This type of system does not necessarily require a
host processor, and the TMS34010 may be responsible for performing host
processor functions for the system.
The TMS3401 0 is configured in self-bootstrap mode when the HCS pin is low
just before the low-to-high transition of RESET. The low HCS level forces the
HLT bit to O. Immediately following the end of reset and the eight RAS-only
cycles, the TMS3401 0 fetches the level-O vector address and begins executing
the reset interrupt routine.
At the low-to-high transition of RESET, the HCS input is internally delayed
before being checked to determine how to set the HLT bit. In a system without a host processor, for instance, this permits the HCS and RESET pins to be
tied together, eliminating the need for additional external logic.
Transitions of the HCS and RESET signals are assumed to be asynchronous
with respect to the TMS3401 0 local clock. HCS and RESET are internally synchronized to the local clock by being held in latches for at least one clock period before being used by the TMS3401 O. The delay through the synchronizer
latch is from one to two local clock periods, depending on the phase of the
signal transitions relative to the clock. To permit the HCS and RESET pins to
be wired together, TMS34010 on-chip logic delays the HCS low-to-high
transition to ensure that it is detected after the RESET low-to-high transition.
The level of the delayed HCS signal at the time the low-to-high RESET transition is detected determines the setting of the HLT bit.

8.8.5.2 Host-Present Mode
Host-present mode assumes that a host processor is connected to the
TMS34010's host interface pins. In this mode; the TMS3401 0 local memory
can be composed entirely of RAM (no ROM). Following reset, the host processor must download the initial program code, interrupt vectors, and so on,
before allowing the TMS3401 0 to begin executing instructions.
The TMS3401 0 is configured in host-present mode as follows. On the trailing
edge of RESET, the HCS (host interface chip select) input is sampled. If the
HCS pin is inactive high, internal logic forces the HLT (halt) bit to a 1. In this
fashion, the TMS34010 is automatically halted following reset, and does not
begin execution of its reset service routine until the host processor loads a 0
to HLT. In the meantime, the host processor is able to load the memory and
I/O registers with the appropriate initial values before the TMS3401 0 begins
executing instructions. This may include writing the reset vector and reset
service routine into the TMS3401 O's memory, for example.
No additional external logic is required to force HCS high before the low-tohigh transition of RESET. The simple external decode logic typically used
drives the HCS input active low only when one of the TMS3401 O's host interface registers is addressed by the host processor. Assuming that the host
processor is not actively chip-selecting the TMS3401 0 at the end of reset, HCS
is high.

8-13

Interrupts. Traps. and Reset

8-14

Section 9

Screen Refresh and Video Timing

The TMS34010 generates the synchronization and blanking signals used to
drive a video screen in a graphics system. The GSP can be programmed to
support a variety of screen resolutions and interlaced or noninterlaced video.
If desired, the GSP can be programmed to synchronize to externally generated
video signals. The GSP also supports the use of video RAMs by generating
the memory-to-register cycles necessary to refresh a screen.
This section includes the following topics:

Section
Page
9.1 Screen Sizes ............................................................................................... 9-2
9.2 Video Timing Signals ................................................................................ 9-3
9.3 Video Timing Registers ............................................................................. 9-4
9.4 Relationship Between Horizontal and Vertical Timing Signals ........... 9-5
9.5 Horizontal Video Timing ........................................................................... 9-6
9.6 Vertical Video Timing ................................................................................ 9-8
9.7 Display Interrupt ...................................................................................... 9-13
9.8 Dot Rate .................................................................................................... 9-14
9.9 External Sync Mode ................................................................................ 9-15
9.10Video RAM Control ................................................................................. 9-18

9-1

Screen Refresh and Video Timing - Screen Sizes

9.1 Screen Sizes
The TMS3401 O's 26-bit word address provides direct addressing of up to 128
megabytes of external memory. This address reach supports very highresolution displays. For example, the designer of a large TMS34010-based
system could decide to use the lower half of the address space for display
memory, and use the upper half for storing programs and data. Half of this
memory space, for example, could be used as a display memory, and the remaining memory can be used for programs and data. The 64-megabyte display memory in this example could support the following display sizes:
•

8192 by 4096 pixels at 16 bits per pixel

•

8192 by 8192 pixels at 8 bits per pixel

•

16,384 by 8192 pixels at 4 bits per pixel

•

16,384 by 16,384 pixels at 2 bits per pixel

•

32~768 by 16,384 pixels at 1 bit per pixel

The video timing registers also support high-resolution displays. The 16-bit
vertical counter register, VCOUNT, directly supports screen lengths of up to
65,536 lines. The 16-bit horizontal counter register, HCOUNT, does not directly limit the horizontal resolution. Each horizontal line can be programmed
to be up to 65,536 VCLK (video clock) periods long. The VCLK period,
however, is an arbitrary number of dot-clock periods in length, depending on
the external divide-down logic used to produce the VCLK signal from the dot
clock. Thus, the number of pixels per line supported by the GSP horizontal
timing registers is limited only by the amount of video memory that is present.
Note that frame buffers in excess of 224 bits may require an external counter
to determine which VRAM serial outputs should be enabled during a scan line.
This external counter would increment upon detecting a 1 -to-O transition of
the logical address bit 23 during successive screen-refresh cycles. To support
applications requiring panning and scrolling of the frame buffer, the initial value of this counter immediately following vertical retrace should be capable of
being loaded under program control.

9-2

Screen Refresh and Video Timing - Video Timing Signals

9.2 Video Timing Signals
The TMS3401 0 generates horizontal sync, vertical sync, and blanking signals
(HSYNC, VSYNC, and BLANK) on chip. The GSP's video timing logic is driven
by the video input clock (VCLK). The sync and blanking signals control the
horizontal and vertical sweep rates of the screen and synchronize the screen
display to data output by the VRAMs.

HSYNC is the horizontal sync signal used to control external video circuitry.
It may be configured as an input or an output via the DXV and HSD
bits in the DPYCTL register. When DXV=O and HDS=O, external
video is selected and HSYNC is an input. Otherwise, HSYNC is an
output.
VSYNC is the vertical sync signal used to control external video circuitry. It
may be configured as an input or an output via the DXV bit in the
DPYCTL register. If DXV=1, internal video is selected and VSYNC is
an output. If DXV=O, external video is selected and VSYNC is an input.
BLANK is used to turn off a CRT's electron beam during horizontal and
vertical retrace intervals. The signal output at the BLANK pin is a
composite of the internally generated horizontal and vertical blanking signals. BLANK can also be used to control starting and stopping
of the VRAM shift registers.
VCLK

is derived from the dot clock of the external video system. VCLK
drives the internal video timing logic.

Holding VCLK low for long periods may cause video counter errors. When
VCLK is not being clocked for long periods, it should be held at the logic high
level. While VCLK is low, the storage nodes within the device rely on their
internal capacitance to maintain state information, and if VCLK is held low for
a sufficiently long time, charge leakage may cause bit errors.

9-3

Screen Refresh and Video Timing - Video Timing Registers

9.3 Video Timing Registers
The video timing registers are a subset of the I/O registers described in Section
6. The values in the video timing registers control the video timing signals.
These registers are divided into two groups:

•

Horizontal timing registers control the timing of the

HSYNC signal

and the internal horizontal blanking signal.

HCOUNT counts the number of VCLK periods per horizontal scan
line.
HESYNC specifies the point in a horizontal scan line at which the
HSYNC signal ends.
HEBLNK specifies the endpoint of the horizontal blanking interval.
HSBLNK specifies the starting point of the horizontal blanking
interval.
HTOTAL defines the number of VCLK periods allowed per horizontal scan line.

•

Vertical timing registers control the timing of the VSYNC signal and
the internal vertical blanking signal.
VCOUNT counts the horizontal scan lines in the screen display.
VESYNC specifies the endpoint of the VSYNC signal.
VEBLNK specifies the endpoint of the vertical blanking interval.
VSBLNK specifies the starting point of the vertical blanking interval.
VTOTAL specifies the value of VCOUNT at which VSYNC may
begin.

9-4

Screen Refresh and Video Timing - Horizontal vs. Vertical Signals

9.4 Relationship Between Horizontal and Vertical Timing Signals
Figure 9-1 illustrates the relationship between the horizontal and vertical timing signals in the construction of a two-dimensional raster display pattern.
The vertical sync and blanking signals span an entire frame. The horizontal
sync and blanking signals span a single horizontal scan line within the frame.

Hortzontal Intarnal--tl

LHSVNC
LHBLNK

~---.""':::"""P.!@~ff.~~::=::=i.

start
New

Fram

vartJoal

Aotlva
Dlaplay

VSBlH<

"larval

~OT&

:;)

0
0

TT
o

I; I~

start New Llna

Figure 9-1. Horizontal and Vertical Timing Relationship

Figure 9-1 illustrates the following terms and phrases, which are used
throughout this section:
•

HBLNK and VBLNK are internal horizontal and vertical blanking signals
that combine to form the BLANK signal output. (HBLNK and VBLNK
cannot be accessed at TMS34010 pins.) The display is active (not
blanked) only when HBLNK and VBLNK are both inactive high.

•

Horizontal front porch refers to the interval between the beginning
of horizontal blanking and the beginning of the horizontal sync signal.

•

Horizontal back porch is the interval between the end of the horizontal sync signal and the end of horizontal blanking.

•

Vertical front porch refers to the interval between the beginning of
vertical blanking and the beginning of the vertical sync signal.

•

Vertical back porch is the interval between the end of the vertical sync
signal and the end of vertical blanking.

9-5

Screen Refresh and Video Timing - Horizontal Video Timing

9.5 Horizontal Video Timing
The following discussion applies to internally generated video timing (the DXV
and HSD bits in the DPYCTL register are set to 1 and 0, respectively). Horizontal timing signals are the same for interlaced and non interlaced video.
The HESYNC, HEBLNK, HSBLNK, and HTOTAL registers control horizontal
signal timing as shown in Figure 9-2. All horizontal timing parameters are
specified as multiples of VCLK. The time between the start of two successive
HSYNC pulses is specified by HTOTAL. HCOUNT counts from
to the value
in HTOTAL and then repeats. The value in HTOTAL represents the number
of VCLK periods, minus one, per horizontal scan line. The value in HESYNC
represents the duration of the sync pulse, minus one. The values in HEBLNK
and HSBLNK specify the beginning and end points of the horizontal blanking
interval.

I Horz. I
I Front I
I Porch I

-~-\

Horz.
Sync

I
I

r~
I
I
I
I

HESVNC+~

14
I

Horz.
Baok
Porch

I
I
I

I
I
I
I

HSBLNK+1

rHESLNK+1~

I
I

I
I
I
I

!t~-----HTOTAI.+1----~.1

Figure 9-2. Horizontal Timing
Figure 9-3 shows the internal logic used to generate the horizontal timing
signals. HCOUNT is incremented once each VCLK period (on the high-to-Iow
transition) until it equals the value in HTOTAL. On the next VCLK period
following HCOUNT=HTOTAL, HCOUNT is reset to 0, and begins counting
again.
The limits of the horizontal sync pulse are defined by the values in HESYNC
and HTOTAL. HSYNC is driven active low when HCOUNT=HTOTAL; it is
driven inactive high when HCOUNT=HESYNC. After HCOUNT becomes
equal to HTOTAL or HESYNC, there is a one-clock delay before the
active/inactive transition takes place at the HSYNC pin.
The internal HBLNK signal is driven active low after HCOUNT=HSBLNK; it is
driven inactive high after HCOUNT=HEBLNK. HBLNK is logically ORed (negative logic) with VBLNK to produce the BLANK signal; that is, BLANK goes low
when either HBLNK or VBLNK is low. After HCOUNT becomes equal to
HSBLNK or HEBLNK, there is a one-clock delay before the transition takes
place at the BLANK pin.

9-6

Screen Refresh and Video Timing - Horizontal Video Timing

VCLK---....

Figure 9-3. Horizontal Timing Logic - Equivalent Circuit
Figure 9-4 illustrates horizontal signal generation.
In this example,
HTOTAL=N, HSBLNK=N-2, HESYNC=2, and HEBLNK=4. Signal transitions
at the HSYNC and BLANK pins occur at high-to-Iow VCLK transitions. After
HCOUNT becomes equal to HTOTAL, HSBLNK, HESYNC, or HEBLNK, there
is a one-clock delay before the transition takes place at the HSYNC or BLANK
pin. When HCOUNT=HSBLNK (shortly before the end of the horizontal
scan), horizontal blanking begins. At this time, the DIP (display interrupt) bit
in the INTPEND register is set to 1 if VCOUNT=DPYINT. The next screenrefresh cycle may also occur at this time - the GSP can be programmed to refresh the screen after one, two, three, or four scan lines.
VCLK

Horizontal
Front Poroh

HSBLNK = N-2
HESYNC
2

Horizontal
Syno PUIH

Horizontal
Back Poroh

HTOTAL = N
HEBLNK 4

Figure 9-4. Example of Horizontal Signal Generation

9-7

Screen Refresh and Video Timing - Vertical Video Timing

9.6 Vertical Video Timing
The following discussion applies to internally generated video timing (the DXV
bit in the DPYCTL register is set to 1).
The VESYNC, VEBLNK, VSBLNK, and VTOTAL registers control vertical signal
timing as shown in Figure 9·5. All vertical timing parameters are specified as
multiples of the horizontal sweep time H, where
H = (HTOTAL + 1) )( (VCLK period)
VTOTAL specifies the time interval between the start of two successive vertical
sync pulses; this value is the number of H intervals, less one, in each vertical
frame. VESYNC represents the duration of the VSYNC pulse, less one, in each
vertical frame. VSYNC's high-to-Iow and low-to-high transitions coincide with
high-to-Iow transitions at the HSYNC pin.
.
VSBLNK and VEBLNK specify the starting and ending points of vertical
blanking.
Blanking begins when VCOUNT=VSBLNK and ends when
VCOUNT=VEBLNK. Assuming that horizontal blanking is active at the start
of each HSYNC pulse, transitions of the internal vertical blanking signal,
VBLNK, occur while horizontal blanking is active.

I Vert.
Vert.
I Front
I Porch I Syno

------t

r~
I

vert. I
I Baok I
I Porch I

IVESVNC+1
J4

I
I

I
I
I

VSBLNK+1

jf--VEBLNK+1--+1

VTOTAL+1----~

Figure 9-5. Vertical Timing for Noninterlaced Display
Figure 9-6 shows the internal logic that generates the vertical timing signals.
VCOUNT increments at the beginning of each HSYNC pulse until it equals the
value in VTOTAL. When VCOUNT=VTOTAL, VCOUNT is reset to 0 and begins counting again. VSYNC is driven active low after VCOUNT=VTOTAL; it
is driven inactive high after VCOUNT=VESYNC. The internal VBLNK signal is
driven active low after VCOUNT=VSBLNK; it is driven inactive high after
VCOUNT=VEBLNK. VBLNK is logically ORed (negative logic) with HBLNK to
produce the BLANK signal. This description applies to a noninterlaced display.
The vertical timing changes slightly for an interlaced display.

9-8

Screen Refresh and Video Timing - Vertical Video Timing

HSYNe - - - - - t I

Figure 9-6. Vertical Timing Logic - Equivalent Circuit

9.6.1

Noninterlaced Video Timing
Noninterlaced scan mode is selected by setting the NIL bit in the DPYCTL
register to 1. In this mode, each video frame consists of a single vertical field.
Figure 9-7 shows the path traced by the electron beam on the screen. Box A
shows the vertical retrace, which is an integral number of horizontal scan lines
in duration. Box B shows the active portion of the frame. Solid lines represent
lines that are displayed; dashed lines are blanked.
Monitor Screen

......................•...........................
.:t.:::::.:::............. ."

......... " ..... ..

......................:::..
..........

Monitor Screen
.u::::::::::::.::...................... .

=: : : : : : : : : : : : : : : : :.:.: .:u~.:~ : :.~.:. :.~.:~:.: : :'.=- I

_································if···················.......... ~

........

....

......

.........

....

......

.........

_································4····················........... ~
--.,································5···················· ............-

_································if···················...................................................
"

(a)

................

:~~~~..:::::::..~~.....~........::=.

...• """:::::::::::::::::::::::::::::::..::::::..

(b)

Figure 9-7. Electron Beam Pattern for Noninterlaced Video
Figure 9-8 illustrates the video timing signals that generate the display. In this
example, VSBLNK=8, VTOTAL=9, VESYNC=1, and VEBLNK=2. (In actual

9-9

Screen Refresh and Video Timing - Vertical Video Timing

applications, much larger values are used; these values were chosen for illustration only.) Each horizontal scan line is preceded by a horizontal retrace.
The horizontal scan pattern repeats until VCOUNT=VTOTAL; VCOUNT is then
reset to 0, and vertical retrace returns the beam to the top of the screen. BLANK
is active low during both horizontal and vertical retrace intervals.
VCOUNT is incremented each time HCOUNT is reset to 0 at the end of a scan
line. The VSYNC outp~ins when VCOUNT=VTOTAL, coinciding with the
start of HSYNC. The \'is'1N'C output ends when VCOUNT=VESYNC; this also
coincides with the start of an HSYNC pulse.
The starting screen-refresh address is loaded from DPYSTRT into DPYADR
at the end of the last active horizontal scan line preceding vertical retrace. This
load is triggered when HCOUNT=HSBLNK and VCOUNT=VSBLNK.

VCOUNT

"HBLNK"

I
I
I
I

"VBLNK"

I
I
I
I

~~----~I~~

~~I----

V;~~----------~~'~~~lL____---------------------lr~
I
I
I
Horizontal
Sweep

•

~-.~!•.-----------~(!)~----------~~
VSBLNK =.8
VESYNC = 1

VTOTAL = 9
VEBLNK = 2

Figure 9-8. Noninterlaced Video Timing Waveform Example

9-10

Screen Refresh and Video Timing - Vertical Video Timing

9.6.1.1 Interlaced Video Timing
Interlaced scan mode is selected when the NIL bit in the DPYCTL register is
set to O. In this mode, each display frame is composed of two fields of horizontal scan lines. The display consists of alternate lines from the two fields.
This doubles 'the display resolution while only slightly increasing the frequency
with which data is supplied to the screen.
Figure 9-9 illustrates the path traced by the electron beam on the screen.
Figure 9-10 shows the timing waveforms used to generate the display in FigIn this example, VSBLNK=6, VTOTAL=7, VESYNC=1, and
ure 9-9.
VEBLNK=2. (In actual applications, much larger values are used; these values
were chosen for illustration only.)
In interlaced mode, two separate vertical scans are performed for each frameone for the even line numbers (even field) and one for the odd line numbers
(odd field). The even field is scanned first, starting at the top left of the screen
(see Figure 9-9 b). When VCOUNT=VTOTAL, the vertical retrace returns the
beam to the top of the screen, and the odd field is scanned (Figure 9-9 d).
The electron beam starts scanning the odd and even fields at different points.
The reason for this is illustrated in Figure 9-10. The end of the VSYNC pulse
that precedes the even field coincides with start of an HSYNC pulse; however,
the VSYNC pulse that precedes the odd field ends exactly halfway between two
HSYNC pulses
Even Aeld

r-~~~~

____

~A~~~

Monitor Screen

.......................

__~____~

Monitor Screen

Odd Aeld

~~~~~____JA~~~~~____~

Monitor Screen

..............................
(a)

(b)

(d)

Juxtaposition of even
and odd fields on ::.--...tiI--

monitor screen.

Figure 9-9. Electron Beam Pattern for Interlaced Video
In interlaced mode, video timing logic operation is altered so that the odd field
begins when HCOUNT=HTOTAL/2. The beam is thus positioned so that
horizontal scan lines in the odd field fall between horizontal scan lines in the
even field. To place each line of the odd field precisely between two lines of
the even field, load HTOTAL with an odd number.

9-11

Screen Refresh and Video Timing - Vertical Video Timing

The transition from d to a in Figure 9-9 shows that the vertical retrace at the
end of the odd field begins at the end of a horizontal scan line; that is, it coincides with the start of an HSYNC pulse, which results from the condition
HCOUNT=HTOTAL. The VSYNC pulse duration is an integral number of horizontal scan retrace intervals. When vertical retrace ends and the active portion
of the next even field begins, the beam is positioned at the beginning of a
horizontal scan line.
Horizontal timing is similar for interlaced and noninterlaced displays.
HCOUNT is reset to 0 at the end of each horizontal scan line. A screen-refresh
cycle begins before the end of the line, coinciding with the start of the horizontal blanking interval. Assuming that the starting corner of the display is the
upper left corner, the DUDATE field of the DPYCTL register is added to the
screen-refresh address (SRFADR in the DPYADR register) to generate the row
address for the next screen-refresh cycle. In interlaced mode, the DUDATE
value must be twice that of the value needed to produce the same display in
non interlaced mode (that is, two times the difference in addresses between
consecutive scan lines). This causes the screen refresh to skip alternate lines
during the odd and even fields.
At the beginning of each vertical blanking interval, the screen-refresh address
(SRFADR in the DPYADR register) is loaded with the starting value specified
by the DPYSTRT register. When vertical blanking precedes an even field, the
new DPYADR row address is incremented by half the value in the DUDATE
field. This is in preparation to display line 2 (Figure 9-9 b). When vertical
blanking precedes an odd field, the row address loaded into DPYADR from
DPYSTRT is not incremented. In this case, the starting row address in
DPYSTRT points to the beginning of line 1 (Figure 9-9 d).

VCOUNT

4
t--H/2

I
I
I

"RIi[JiK"

"VBlN"·l
I

I
I

I
I
I
I

:I
I

~
I

Sw_ ~_l'
:
_____ +""T----.
V~
__----------------~
I
r
I

Ho".......

I
I

i
I

~~~.I_.------~

Even Reid

I
I

III

.1.
v

VSBLNK "" 6

VTOTAL == 7

VESYNC

VEBLNK =

Odd Field

Figure 9-10. Interlaced Video Timing Waveform Example

9-12

Screen Refresh and Video Timing - Display Interrupt

9.7 Display Interrupt
The TMS3401 0 can be programmed to interrupt the display when a specified
line is displayed on the screen. This is called a display interrupt. It is enabled by setting the DIE bit in the INTENB register to 1 and loading the DPYINT register with the desired horizontal scan line number. When VCOUNT =
DPYINT, the interrupt request is generated to coincide with the start of horizontal blanking at the end of the specified line.
The display interrupt request can be polled by disabling the interrupt (setting
DIE=O) and checking the value of the DIP bit in the INTPEND register.
Writing a 0 to DIP clears the request.
The display interrupt has several applications. It can be used to coordinate
modifications of the bit map with the display of the bit map's contents, for
example. While the bottom half of the screen is displayed, the GSP can modify
the bit map of the top half of the screen, and vice versa.
Another use for the display interrupt is in maintaining a cursor on the monitor
screen. The cursor image resides in the on-screen memory only during the
time the electron beam is scanning the lines containing the cursor. The cursor
remains free from flicker even during periods in which the TMS34010 busy
drawing to the screen. The technique is to load the DPYINT register with the
VCOUNT value of a scan line just above where the top of the cursor is to appear. When the display interrupt occurs, the interrupt service routine performs
the following tasks:
•
•
•

Sets DPYINT to the scan line just below the cursor,
Saves the portion of the screen where the cursor is to appear, and
PixBlts the cursor onto the screen.

The cursor remains on the screen until the electron beam reaches the bottom
of the cursor, at which time a second interrupt request occurs. The original
screen is then restored, and the TMS3401 0 can resume drawing to the screen.
The display interrupt is also useful in split screen applications. By modifying
the contents of the DPYADR register halfway through a frame, different parts
of the bit map can be displayed on the top and bottom halves of the screen.
No special steps are necessary to ensure that loading a new value to DPYADR
does not interfere with an ongoing screen-refresh cycle. The display interrupt
is requested at the beginning of the horizontal blanking interval. If a screenrefresh cycle occurs during the same horizontal blanking interval, the GSP
cannot respond to the interrupt request until the refresh cycle and subsequent
updating of DPYADR are complete. This is true whether the interrupt is taken
or the GSP simply polls the DIP bit and detects a 0-to-1 transition. After DIP
has been set to 1, DPYADR can be loaded with a new value to achieve the
split screen anytime before the next screen-refresh cycle.
In interlaced mode, the display interrupt can be used to detect the start of the
even field. For this purpose, the DPYINT register is loaded with the value from
the VESYNC register. Figure 9-10 (page 9-12) shows that during the odd
field, VCOUNT is incremented by 1 halfway through the horizontal interval
when the condition VCOUNT=VESYNC is detected.
Assuming that
HSBLNK=HTOTAL/2, VCOUNT contains the value VESYNC+1 by the time
horizontal blanking begins. This means that if DPYINT=VESYNC, the display
interrupt is effectively prevented from occurring during the odd field.

9-13

Screen Refresh and Video Timing - Dot Rate

9.8 Dot Rate
A typical screen must be refreshed 60 times per second for a non interlaced
scan or 30 times per second for an interlaced scan. For a non interlaced display, the dot period (time to refresh one pixel) is estimated as:
Dot Period =

(O.S) (1/60 second)
(pixels/line) )( (lines/frame)

For an interlaced display, the dot period is estimated as
Dot Period

(O.S) (1/30 second)
(pixels/line) )( (lines/frame)

The O.S factor in the numerator accounts for the fact that the display is typically blanked for about 20% of the duration of each frame. This factor varies
somewhat from monitor to monitor.
During each dot period, the complete information for one pixel must be obtained from the display memory (or frame buffer). Thus, the rate at which video data must be supplied from the display memory (which is usually the
limiting factor for large systems) is a function of pixel size as well as screen
dimensions.

9-14

Screen Refresh and Video Timing - External Sync Mode

9.9 External Sync Mode
External sync mode allows the TMS3401 0 to use horizontal and vertical sync
signals from an external source. This permits graphics images generated by
the GSP to 'be superimposed upon or mixed with images from external
sources.
External sync mode is selected by setting the DXV and HSD bits in the
DPYCTL register to O. HSYNC and VSYNC are now configured as inputs. (Alternately, HSYNC can be configured as an output and VSYNC as an input by
setting DXV=O and HSD=1.) When an active-low sync pulse is input to one
of these pins, the corresponding counter (HCOUNT or VCOUNT) is forced to
all Os. By forcing the counters to follow the external sync signals, the blanking
intervals and screen-refresh cycles are also forced to follow the external video
signals.
The HSYNC and VSYNC inputs are sampled on each VCLK rising edge.
HCOUNT or VCOUNT are cleared 2.5 clock periods (on a VCLK falling edge)
following a high-to-Iow transition at the HSYNC or VSYNC pin, respectively.
BLANK remains an output, but its timing is affected because the point at which
HCOUNT and VCOUNT are cleared is controlled by the external sync signals.
The 2.5-clock delay must be considered when selecting values for the
HSBLNK and HEBLNK registers.

9.9.1 A Two-GSP System
One GSP can generate video timing for two GSPs. As Figure 9-11 shows,
GSP #1 is configured for internal sync mode (DXV=1) and generates the sync
timing. GSP #2 is configured for external sync mode (DXV=O and HSD=O),
and receives the HSYNC and VSYNC inputs from GSP #1. Assume that the video timing registers of the two devices are named as follows:

GSP #1
HCOUNT1
HESYNC1
HSBLNK1
HEBLNK1
HTOTAL1
VCOUNT1
VESYNC1
VSBLNK1
VEBLNK1
VTOTAL1

GSP#2
HCOUNT2
HESYNC2
HSBLNK2
HEBLNK2
HTOTAL2
VCOUNT2
VESYNC2
VSBLNK2
VEBLNK2
VTOTAL2

GSP #2's registers should be programmed in terms of the values in GSP #1 's
registers, as shown in Table 9-1. The BLANK signals from GSP #1 and GSP
#2 are the same, and switch in unison on the same VCLK edges. When
HCOUNT1 is cleared on a VCLK falling edge, HCOUNT2 is cleared three full
VCLK periods later. For short horizontal blanking periods, HEBLNK2 may
need to be loaded with a value that is less than zero. For example, assume that
HSBLNK1 =HTOTAL1-4 and HEBLNK1 =1 (that is, the horizontal blanking
interval is six VCLK periods). To ensure that GSP #2's horizontal blanking
interval begins and ends at the same time as GSP #1 's, GSP #2's registers
must be loaded with values so that HSBLNK2=HTOTAL1-8 and
HEBLNK2=HTOTAL1-2.
9-15

Screen Refresh and Video Timing - External Sync Mode

VCLJ(
~

HCOUNT

______________
(output

~~4_-------------------

HSYNC
to GSP -2)
i!if..S;

HCOUNT
Figure 9-11. External Sync Timing - Two GSP Chips

The values in HTOTAL2 and VTOTAL2 must be large enough so that the
conditions HCOUNT=HTOTAL and VCOUNT=VTOTAL do not cause
HCOUNT and VCOUNT, respectively, to be cleared before the leading edges
of the external horizontal and vertical sync pulses occur. In the example in
Table 9-1, HTOTAL2 and VTOTAL2 are set to their maximum values. The
value of HESYNC2 must be such that HCOUNT=HESYNC2 occurs between
the end of an external HSYNC pulse and the beginning of the next external
HSYNC pulse. The value of VESYNC2 must be such that VCOUNT=VESYNC2
occurs between the end of an external VSYNC pulse and the beginning of the
next external VSYNC pulse.

Table 9-1. Programming GSP #2 For External Sync Mode
HEBLNK2
HSBLNK2
HTOTAL2
HESYNC2
VEBLNK2
VSBLNK2
VTOTAL2
VESYNC2

HEBLNK1 - 3
HSBLNK1 - 3
65535
(HEBLNK2 + HSBLNK2)/2 t
VEBLNK1
VSBLNK1
65535
(VEBLNK2 + VSBLNK2)/2 t

t Suggested value; see description in text.

Since the internal counter can only be resolved to the nearest VCLK edge,
precise synchronization with an external video sourc~ can be achieved only
when VCLK is harmonically related to the external horizontal sync signal. In
general, however, the HSYNC and VSYNC inputs are allowed to change asynchronously with respect to VCLK, although the precise VCLK edge at which
an external sync pulse is recognized can be guaranteed only if the setup and
hold times specified for sync inputs are met.

9-16

Screen Refresh and Video Timing - External Sync Mode

9.9.2 External Interlaced Video
External sync mode can be used for both interlaced and non interlaced displays. When locking onto external interlaced sync signals, the GSP discriminates between the odd and even fields of the external video signals based on
whether its internal horizontal blanking is active at the time that the start of the
external vertical sync pulse is detected. In Figure 9-10, for example, the even
field begins at a point where HBlNK is active low, and the odd field begins
while HBLNK is high.
In interlaced mode, the discrimination between the even and odd fields of an
external video source is based on the value of HCOUNT at a point two VCLK
periods past the rising VCLK edge at which the GSP detects the VSYNC input's
high-to-Iow transition. If HCOUNT contains a value greater than the value in
HEBLNK, but less than or equal to the value in HSBLNK, the GSP assumes
that the vertical sync pulse precedes the start of an odd field. Otherwise, the
next field is assumed to be even. Alternatively, the GSP can be placed in
non interlaced mode, even though the external sync signals it is locking onto
are for an interlaced display. In this case, the GSP simply causes identical
display information to be output to the monitor during the odd and even fields.
The program can determine at any time whether an even or odd field is being
scanned by inspecting the least significant bits of the DPYADR register to
determine whether they have been incremented by DUDATE/2. Recall that
that at the start of an even field, the initial address loaded into DPYADR from
the DPYSTRT register is automatically incremented by DUDATE/2 (that is,
incremented by half the value specified in the DUDATE field of the DPYCTL
register). At all other times, DPYADR is incremented by DUDATE rather than
DUDATE/2.

9-17

Screen Refresh and Video Timing - Video RAM Control

9.10 Video RAM Control
The TMS34010 automatically schedules the VRAM (video RAM) memoryto-register cycles needed to refresh a video monitor screen. These cycles are
referred to as screen-refresh cycles.
In addition to automatic screen-refresh cycles, the GSP can be configured to
perform memory-to-register and register-to-memory cycles under the explicit
control of software executing on the GSP's internal processor. One of the
primary uses for this capability is to facilitate nearly instantaneous clearing of
the screen. The screen is cleared in 256 memory cycles or less by means of a
technique referred to here as bulk initialization of the display memory.

9.10.1

Screen Refresh
A screen-refresh cycle loads the VRAM shift registers with a portion of the
display memory corresponding to a scan line of the display. The internal requests for these cycles occur at regular intervals coinciding with the start of
the horizontal blanking intervals defined by the video timing registers. When
horizontal blanking ends, the contents of the shift registers are clocked out
serially to drive the video inputs of a monitor. A screen-refresh cycle typically
occurs prior to each active line of the display.

9.10.1.1 Display Memory
The display memory is the area of memory which holds the graphics image
output to the video monitor. This memory is typically implemented with
VRAMs. During a screen-refresh cycle, a portion of the display memory corresponding to one (or possibly more) scan lines of the display are loaded into
the VRAM shift registers. Depending on the screen dimensions selected, not
all portions of the display memory are necessarily output to the monitor.
The width of the display memory is referred to as the screen pitch, which is the
difference in 32-bit memory addresses between two vertically-adjacent pixels
on the screen. The screen pitch is also the difference in starting memory addresses of the video data for two consecutive scan lines. When XY addressing
is used, the screen pitch must be a power of two to facilitate the conversion
of XY addresses to memory addresses. The value loaded into the DUDATE
field of the DPYCTL register represents the screen pitch, and is the amount
by which the screen-refresh address is incremented (or decremented) following each screen-refresh cycle.
The portion of display memory that is actually output to the monitor is referred
to as the on-screen memory. The starting location of the on-screen memory
is specified by the SRFADR field in the DPYSTRT register.
The starting screen-refresh address is output during the screen-refresh cycle
that occurs at the start of each frame. At the end of the screen-refresh cycle,
the address is incremented to point to the area of memory containing the pixels
for the second scan line. The process is repeated for each subsequent scan
line of the frame.

9-18

Screen Refresh and Video Timing - Video RAM Control

A screen-refresh cycle typically affects all video RAMs in the system. A memory-to-register cycle transfers data from a selected row of memory to the
internal shift register of each VRAM. The data is then shifted out to refresh the
display.
A screen-refresh cycle takes place during the horizontal blanking interval that
precedes a scan line to be displayed. Typically, the shift registers containing
the video data for the line are clocked only during the active portion of the
scan line, that is, when the BLANK output is high. At higher dot rates, the pixel
clock or dot clock used to shift video data to the monitor is run through a
frequency divider to create the VCLK signal input to the GSP.
The 8-bit row address output during the screen-refresh cycle specifies the row
in memory to be loaded into the shift register internal to the VRAM. The
number of bits of video data transferred to the shift registers of all the VRAMs
in the system during a single screen-refresh cycle is calculated by multiplying
the number of VRAMs times the length of the shift register in each VRAM.
For example, 64 TMS4161 (64K-by-1) VRAM devices are sufficient to contain the bit map for a 1024-by-1 024-pixel display with four bits per pixel. The
length of the shift register in each TMS4161 is 256 bits. Thus, in a single
screen-refresh cycle, a total of 64 times 256, or 16,384, bits are loaded. This
is enough data to refresh four complete scan lines of the display. In general,
a single screen-refresh cycle performed during a horizontal blanking interval
is sufficient to supply one or more complete scan lines worth of data to the
video monitor screen.
9.10.1.2 Generation of Screen-Refresh Addresses
The DPYADR, DPYCTL, DPYSTRT, and DPYTAP registers are used to generate the addresses output during screen-refresh cycles. Figure 9-12 shows
these four registers, and indicates the register fields which determine the way
in which screen-refresh addresses are generated.
15

DPYAOR

DP'I'STRT

:#M

1514131211109
DPYC1\.

210

E'1j Lry}:;;;rij I : : QUijAii : : 1;,i;::?ll'4
NIL

ORG

151413

DPYTAP

Pitt?'l : : : : : D;PYt~

: : : : :

Figure 9-12. Screen-Refresh Address Registers

9-19

Screen Refresh and Video Timing - Video RAM Control

•

DPYADR contains the SRFADR field, which is a counter that generates
the addresses output during screen-refresh cycles.

•

DPYSTRT contains the SRSTRT field, the starting address loaded into
SRFADR at the beginning of each frame.

•

DPYCTL contains several fields that affect screen-refresh addresses. The
8-bit DUDATE field is loaded with seven Os and a single 1 that points
to the bit position within SRFADR (bits 2-9 of DPYADR) at which the
address is to be incremented (or decremented) at the end of each
screen-refresh cycle. The ORG bit determines whether the screenrefresh address is incremented or decremented. If ORG =0, the screen
origin is located at the top left corner of the screen and the address is
incremented; otherwise, it is decremented. The NIL bit determines
whether the GSP is configured to generated an interlaced (NIL=O) or
non interlaced (NIL=1) display. The generation of screen-refresh addresses can be modified to accommodate either type of display.

•

The D PYT AP register is used to specify screen - refresh address bits to
right of the position at which D U DATE increments the address. D PYTAP provides the additional control over screen-refresh address generation necessary to allow the screen to pan through the display memory.

Bits not directly involved in address generation are shaded in Figure 9-12.
The address output during a screen-refresh cycle identifies the starting pixel
on the scan line about to be output to the monitor. Figure 9-13 (page 9-21)
shows a 32-bit logical address of the first pixel on one of the scan lines appearing on the screen. The screen-refresh address consists of bits 4-23 of the
logical address, which are generated by combining the values contained in
SRFADR and DPYTAP. Where SRFADR and DPYTAP overlap (bits 10-17
of the logical address), the address bits are generated by logical ~Ring the
corresponding bits of SRFADR and DPYTAP. The 8-bit DUDATE value contains seven Os and a single 1 pointing to the position at which SRFADR is to
be incremented (or decremented). The DPYTAP register should be loaded
with the portion of the pixel address in Figure 9-13 lying to the right of the
position indicated by the DUDATE pointer bit. SRFADR contains the portion
of the pixel address that is incremented by the DUDATE pointer bit.
Following system power up, the software should load the starting screenrefresh address into the SRSTRT field of the DPYSTRT register, and load the
increment to the screen-refresh address into the DPYCTL register. For a typical CRT display, the starting address is the address in memory of the pixel that
appears in the upper left corner of the display. If ORG bit in DPYCTL is 0, the
15 complement of the starting address should be loaded into DPYSTRT. If
ORG =1, the starting address loaded into DPYSTRT should not be complemented.
DPYADR is automatically loaded with the starting display address from
DPYSTRT prior to the start of each frame. As shown in Figure 9-14 a, bits
2-15 of DPYSTRT (SRSTRT) are loaded into bits 2-15 of DPYADR
(SRFADR). The load occurs coincident with the start of the horizontal
blanking interval that occurs just at the end of the last active scan line of the
preceding frame.

9-20

Screen Refresh and Video Timing - Video RAM Control

output During Row________
Address llme
r-________
~A~

i
:

r-__

I
I
I

24:

~ Output During
Column Address llme

I
~:

~A~________~\

I
I
I

____

20
18
12:
32-BIt Logical Pixel Ad re88

4 :

SRFADR

(DPVADR BIts 2-15)
I i
I
I
I

I
I
I

U
r:

DUDATE
(DPYCTL Bits 2-9)

~~I

I
I
I
I
I

DPYTAP
rif-L----- (BIts

0-13) ----~

Figure 9-13. Logical Pixel Address

The address output during each screen-refresh cycle is contained in bits 2
through 15 of the DPYADR register (the 14-bit SRFADR field). As shown in
Figure 9-14 b, DPYADR bits 4-15 are output at the LADe-LAD11 pins during
the row address time of the screen-refresh cycle. If ORG=O, the DPYADR bits
are inverted before being output; otherwise, they are output unaltered. Zeros
(logic-low level) are output on LAD12-LAD14, and a one (logic-high level)
is output on LAD15; this is the RF status bit.
During the column address time of the screen-refresh cycle, bits 2-6 of
DPYADR are output at LAD6-LAD10. If ORG=O, the DPYADR bits are inverted before being output. DPYTAP bits 6-11 are ORed with DPYADR bits
2-7 and output at LAD6-LAD11. Bits 0-5 and 12-13 of DPYTAP are output
at LADO-LAD5 and LAD11-LAD13, respectively.
Zeros are output at
LAD14-LAD15 (the TR and IAQ status bits).
After the row and column addresses have been output, the address in
DPYADR bits 2-15 is decremented by the 8-bit value in DPYCTL bits 2-9 (the
DUDATE field). This is done in preparation for the next screen-refresh cycle.
The 8-bit DUDATE value is a binary number consisting of seven Os and a
single 1. This single 1 indicates the position at which DPYADR is decremented. If ORG=O, the screen-refresh address in DPYADR is effectively incremented; the 1 s complement of the address contained in DPYADR is
decremented by the DUDATE amount, but is inverted before being output.
This is equivalent to incrementing the address. If ORG =1, the address is decremented.

9-21

Screen Refresh and Video Timing - Video RAM Control

6R6TRT
II

DPYSTRT
Regllter

15 14 13 12 11 10 9 8 7 8 5 4 3 210

DPYADR

ReglBter ,I

v
SRFADR

(a) Display-Address Initial Value

DPYADR

1514131211109878543210

LAD Bus Pins

I-----~

o
2

ORG - - - I

'::_-------..J

3
4
5
8
7
8
9
10
11

-i--+ II
I
--t-+
I
--r--+ 15(RF) I

o
12
o --+--+ 13
o
14
~

_____ I

(b) Row-Address Time

Figure 9-14. Screen-Refresh Address Generation

9-22

I
I
I

Screen Refresh and Video Timing - Video RAM Control

DPYADR
Register

;

l)AAAAJJ ~_ ---,
Bus Pins

I
I
I

DPYTAP
Register

I
I

--13

12
11

10
9

8
7

6
5
4

3
2
1

---

!
i

L-

!
i

2
3
4

6
7

---c:

---c;:

r--

!
i
I

10
11
12

°r141TRI

0~1511AQI
L ____ .J
(c) Column-Address Time
'\

Figure 9-14. Screen-Refresh Address Generation (Continued)

9-23

Screen Refresh and Video Timing - Video RAM Control

0'
~

c...N ......

-'"..

.. f--

~r-

r--

"--"'

...
"CD
OI
~

::
:::!
~

"'~-

'~i
".

NI.

......

I---

r----!:

---! ~

~'"

--~
~

..... ~

(

"'I·
"I·
"' I·
.. I· (

<
<
<

"L·
I.
CD

OIl!:
~f--

<
(
'"

::
:::!
~

~'--

(d) Display-Address Update
Figure 9-14. Screen-Refresh Address Generation (Concluded)

9-24

Screen Refresh and Video Timing - Video RAM Control

9.10.1.3 Screen Refresh for Interlaced Displays
The size of the DUDATE increment specified for an interlaced display should
be twice that required for a non interlaced display of the same dimensions.
This allows every other line to be skipped during the even or odd field of an
interlaced frame. Before the start of the even field, half the value of the DUDATE increment is added to the starting address loaded into DPYADR to obtain the necessary starting displacement. The SRSTRT field in DPYSTRT
points to the area of memory containing the video data for scan line 1 in the
example of Figure 9-9 on page 9-11.

9.10.1.4 Panning the Display
The DPYTAP register supports horizontal panning of the screen across a display memory that is larger than the screen. The value contained in the loworder bits of DPYTAP furnish the LSBs of the column address output during
the screen-refresh cycle. Incrementing this value results in panning to the
right; decrementing this value results in panning to the left.

9.10.1.5 Scheduling Screen-Refresh Cycles
The internal request for a screen-refresh cycle is generated when horizontal
blanking begins. This gives the GSP essentially the entire horizontal blanking
interval in which to perform the screen-refresh cycle. The delay from the start
of horizontal blanking to the start of the screen-refresh cycle is called the
screen-refresh latency, and is determined by the internal memory controller.
The best and worst case screen-refresh latencies are given in Table 9-2. In the
best case, the delay from the high-to-Iow transition of the BLANK output to the
start of the screen-refresh cycle (the time the row address is output) is only
3.25 machine states (or local clock periods). In the worst case, the delay is
(7.25 + 2W) states, where W represents the number of wait states required
per memory cycle. The worst case number is based on the fact that the start
of the screen-refresh cycle can be delayed by up to three states if a readmodify-write operation began one state before the memory controller received
the request for the screen-refresh cycle. A screen-refresh request is given
higher priority than requests for DRAM-refresh, host-indirect or GSP CPU
cycles; hence, no further delays occur unless an external device generates a
hold request.

Table 9-2. Screen-Refresh Latency
Min

Max

3.25 states

(7.25 + 2W) states

Note: W is the number of wait states per memory
cycle.

The horizontal blanking interval should be sufficiently long in duration for the
screen-refresh cycle to be completed before blanking ends. The required minimum blanking interval is therefore about (9.25 + 3 W) machine states, depending on how soon after the end of blanking the external video logic begins
clocking the VRAM shift registers. Of course, this time must be translated from
9-25

Screen Refresh and Video Timing - Video RAM Control

machine states (local clock periods) to VCLK periods to program the HEBLNK
register.
The horizontal sync pulse is permitted to be as small as a single VCLK period
in duration.
No screen-refresh cycles are performed during vertical blanking until nearly the
end of vertical blanking - at the start of the horizontal blanking interval that
precedes the first active scan line of the new frame.
The screen-refresh latency specified in Table 9-2 assumes that a local bus hold
request (HOLD low) is not asserted between the start of blanking and the start
of the screen-refresh cycle. If a hold request prevents the TMS34010 from
initiating a scheduled screen-refresh cycle during this time, the TMS3401 0 is
forced to delay its screen-refresh cycle until the bus is released by the external
device asserting the hold request. A hold request occurring during the horizontal blanking interval preceding an active scan line on the display should
be deasserted in time to allow the TMS34010 to complete the pending
screen-refresh cycle before blanking ends. If a screen-refresh cycle is pending
at the time the external device releases the bus, the screen-refresh cycle is the
first cycle performed by the TMS3401 0 after it regains control of the bus.

9.10.2 Video Memory Bulk Initialization
VRAMs may be rapidly loaded with an initial value using a special GSP feature
that converts pixel accesses to register transfers. This rapid loading method
is referred to I!S bulk initialization of the video memory, and can be used with
VRAMs such as the TMS4461. When the SRT (shift register transfer) bit in
the DPYCTL register is set to a 1, all reads and writes of pixel data are converted at the memory interface of the GSP to register-transfer cycles. When
SRT=O, pixel accesses are performed in normal fashion.
When SRT=1, the processor can initiate register-transfer cycles under explicit
program control. By performing a series of such cycles, some or all of the
display memory can be set to an initial background color or pattern very rapidly
(in a small fraction of one frame time). First, the VRAM shift registers are
loaded with the initial value. The video memory is then set to the initial color
or pattern one row at a time by writing the shift register contents to the memory.
During a register-transfer cycle (when SRT=1), the row and column addresses
are output in unaltered form; that is, the address is not affected by the state
of SRT. The 8-bit row address output during the cycle designates which row
in memory is involved in the transfer. The direction of the transfer is determined by whether the cycle is a read or a write. A write cycle such as a PIXT
transfer from a general-purpose register to memory is converted to a VRAM
register-to-memory cycle. Similarly, a read cycle such as a PIXT transfer from
memory to a general-purpose register is converted to a VRAM memory-toregister cycle.
Only pixel transfers are affected by the SRT bit. The manner in which all other
data accesses and instruction fetches are performed is not affected.

9-26

Screen Refresh and Video Timing - Video RAM Control

Before bulk initialization of the display memory, the VRAM shift registers are
loaded with the solid color or pattern with which the display memory is
loaded. This can be done in one of two ways, by either:
•

Serially shifting bits into the shift register
or

•

First loading a row of display memory with the color or pattern using a
series of "normal" pixel writes (when SRT=O), and then loading the
contents of this row into the shift register by means of a PIXT memory-to-register instruction (executed while SRT=1).

To speed up the bulk initialization operation further, a series of transfers can
be made more rapidly by using a single FILL instruction in place of a series of
PIXT instructions. The fill region is selected so that each pixel write cycle
generates a new row address. The fill region is specified to be precisely 16
bits wide, the width of the memory data bus. Also, plane masking is disabled,
transparency is turned off, and the pixel processing replace operation is selected. This ensures that each row is addressed only once during the course
of the fill operation.
The number of bits of the display memory that are altered by a single register-to-memory transfer cycle is calculated by multiplying the number of VRAM
devices by the number of shift register bits in each device. The entire frame
buffer is loaded with the initial color or pattern in 256 memory cycles.

9-27

Screen Refresh and Video Timing

9-28

Section 10

Host Interface Bus

A host processor can communicate with the TMS3401 0 by means of an interface bus consisting of a 16-bit data path and several transfer-control signals. The TMS34010's host interface provides a host with access to four
programmable 16-bit registers (resident on the TMS34010), which are
mapped into four locations in the host processor's memory or 110 address
space. Through this interface, commands, status information, and data are
transferred between the TMS3401 0 and host processor.
A host processor may read from or write to TMS3401 0 local memory indirectly
via an autoincrementing address register and data port. This optional autoincrement feature supports efficient block moves. The TMS3401 0 and host can
send interrupt requests to each other. A pin is dedicated to the interrupt request from the TMS34010 to the host. To allow block moves initiated by a
host to take place more efficiently, the host may suspend TMS3401 0 program
execution to eliminate contention with the TMS34010 for local memory.
DRAM-refresh and screen-refresh cycles continue to occur while the
TMS34010 is halted.
This section includes the following topics:

Section
Page
10.1 Host Interface Bus Pins ......................................................................... 10-2
10.2 Host Interface Registers ........................................................................ 10-2
10.3 Host Register Reads and Writes ............................................... ., .......... 10-4
10.4 Bandwidth ............................................................................................ 10-22
10.5 Worst-Case Delay ................................................................................ 10-23

10-1

Host Interface Bus - Pins/Registers

10.1 Host Interface Bus Pins
The TMS3401 O's host interface bus consists of a 16-bit bidirectional data bus
and nine control lines. These signals are described in detail in Section 2.
HDo-HD15
form a 16-bit bidirectional bus, used to transfer data between the
TMS34010 and a host processor.
is the host chip select signal. It is driven active low to allow a host
processor to access one of the host interface registers.
HFSO, HFS1
are function select pins. They specify which of four host interface
registers a host can access (see Section 10.2).
HREAD

is driven active low to allow a host processor to read the contents
of the selected host interface register, output on H OQ-H 015.

HWRITE

is driven active low to allow a host processor to write the contents
of H OQ-H 015 to the selected host interface register.
is driven low to enable a host processor to access the lower byte
of the selected host interface register.
is driven low to enable a host processor to access the upper byte
of the selected host interface register.

HRDY

informs a host processor when the TMS34010 is ready to complete an access cycle initiated by the host.
transmits interrupt requests from the TMS3401 0 to a host processor.

10.2 Host Interface Registers
The host interface registers are a subset of the I/O registers discussed in Section 6. The host interface registers can be accessed by both the TMS3401 0
and the host processor. These registers occupy four 16-bit locations in the
host processor's memory or I/O address map. One of these four locations is
selected by placing a particular code on the two function select inputs, HFSO
and HFS1, as shown in Table 10-1.

Table 10-1. Host Interface Register Selection
HFS1

HFSO

Selected
Register

0
0
1

HSTADRL
HSTADRH
HSTDATA
HSTCTL

1
0
1

A 16-bit host processor typically connects two of its low-order address lines
to HFSO and HFS1. An 8-bit processor typically connects two low-order address lines to HFSQ-HFS1 and uses a third low-order address bit to enable
either the upper or lower byte of the selected register by activating one of the

10-2

Host Interface Bus - Registers

byte select inputs, HUDS or HLDS. In the second case, the registers occupy
eight 8-bit locations in the host processor's memory map.
•

The HSTADRl and HSTADRH registers contain the 16 lSBs and 16 MSBs,
respectively, of a 32-bit pointer address. A host processor uses this address
to indirec~ly access TMS3401 0 local memory.

•

The HSTDATA register buffers data that is transferred through the host interface between TMS34010 local memory and a host processor. HSTDATA
contains the contents of the address pointed to by the HSTADRL and
HSTADRH registers.

•

The HSTCTl register is accessible to the TMS3401 0 as two separate I/O registers, HSTCTLL and HSTCTLH, but is accessed by a host processor as a
single 16-bit register. HSTCTL contains several programmable fields that
control host interface functions.
NMI (nonmaskable interrupt, bit 8): Allows a host processor to interrupt
TMS34010 execution.
NMIM (NMI mode, bit 9): Specifies if the context of an interrupted
program is saved when a nonmaskable interrupt occurs.
CF (cache flush, bit 14): Setting this bit flushes the contents of the
TMS34010 instruction cache. A host processor can force the TMS3401 0
to execute new code after a download by flushing old instructions out
of cache.

LSL (lower byte last, bit 13): Specifies which byte of a register an 8-bit
host processor accesses first.
INCR (increment address before local read, bit 12): Controls whether the
32-bit pointer in the HSTADR registers is incremented before being used
in a local read cycle that updates the HSTDATA register.
INCW (increment address after local write, bit 11): Controls whether the
32-bit pointer in the HSTADR registers is incremented after being used
in a local write cycle that transfers the contents of the HSTDATA register
to memory.

HLT (halt TMS3401 0 program execution, bit 15): A host processor can
halt the TMS3401 O's on-chip processor by setting this bit to 1.
MSGIN (message in, bits 0-2): Buffers a 3-bit interrupt message from a
host processor to the TMS3401 O.
IN TIN (input interrupt bit, bit 3): A host must load a 1 into this bit to
generate an interrupt request to the TMS3401 O.
MSGOUT (message out, bits 4-6):
from the TMS3401 0 to a host.

Buffers a 3-bit interrupt message

INTOUT (Interrupt out, bit 7): The TMS3401 0 must load a 1 to this bit
to send an interrupt request to a host processor.

10-3

Host Interface Bus - Reads and Writes

10.3 Host Register Reads and Writes
Host interface read and write cycles are initiated by the host processor and are
controlled by means of the HCS, HWRITE, HREAD, HUDS, and HLDS signals.
Host-initiated accesses of the register selected by the function-select code
input on HFSO and HFS1 are controlled as follows:
•

While HCS, HLDS, and HWRITE are active low, the contents of HOD-H07
are latched into the lower byte of the selected register.

•

While HCS, HUDS, and HWRITE are active low, the contents of
H08-H015 are latched into the upper byte of the selected register.

•

While HCS, HLDS, and HREAD are active low, the contents of the lower
byte of the selected register are driven onto HOD-H07.

•

While HCS, HUDS, and HREAD are active low, the contents of the upper
byte of the selected register are driven onto H08-H015.

As this list indicates, at least three control signals must be active at the same
time to initiate an access. The last of the three signals to become active begins
the access, and the first of the three signals to become inactive signals the end
of the access. A signal that begins or completes an access is referred to in the
following discussion as the strobe signal for the cycle. Any of the signals
listed above may be a strobe. Figure 10-1 shows a functional representation
of the logic that controls the TMS3401 O's host interface.
TMS34010

wrtte to upper
byte of aeIeoted
register

wrtte to lower
byte of aeleoted
register

Read frc:.:r
byte of
ed
register

Reed from lower
byte of . .!ected
regl8ter

Figure 10-1. Equivalent Circuit of Host Interface Control Signals

10-4

Host Interface Bus - Reads and Writes

The designer must ensure that HREAD and HWRITE are never active low simultaneously during an access of a host interface register; this may cause internal damage to the device.

10.3.1 Functional Timing Examples
The functional timing examples in this section are based on the circuit shown
in Figure 10-1.
•

The HCS input is the strobe in Figure 10-2 and Figure 10-3.

•

The HWRITE signal is the strobe in Figure 10-4.

•

The HREAD signal is the strobe in Figure 10-5.

•

The HUDS and HLDS signals are strobes in Figure 10-6 and Figure 10-7.

HFSo-HFS1

,'----

HREAD

--.J

HWRITE

HLDS

Enable write to Lower Byte

I
I

HUDS

--.J

inhibit write to Upper Byte

,'-_ _ __

HCS

' ___....II

HDO-HD15

HRDY

(HIgh)

Figure 10-2. Host a-Bit Write with HCS Used as Strobe

10-5

Host Interface Bus - Reads and Writes

HF804FS1

HWRfTE

Hii£AD

ii:i5i

HOi5i

:J
='
:J
\

HCS

\
!
inhibit Read from Lower Byte

Enable Read from Upper Byte

HDO-HD15 - - - - - - - - - - (

!
Valid Data Out

}--------

HRDY

Figure 10-3. Host 8-Bit Read with

HWRITE:J
HCS='
HLDS='
HUDS ='

HCS

Used as Strobe

,'---!

Enable Read from Lower Byte

Enable Read from Upper Byte

'\,..._ _....J!
HDO-HD15 - - - - - - - - - - (

HRDY

Valid Data Out

}--------

(High)

Figure 10-4. Host 16-Bit Read with HREAD Used as Strobe

10-6

Host Interface Bus - Reads and Writes

HFSO-HFS1

"'READ
HCB
HLDS

HUOB

\~--

='
='
='

Enable Wl'lte to Lower Byte

!
!

Enable Wl'lte to Upper Byte

HWRITE

,___-J!

HDO-HD15

HRDY

(HIgh)

Figure 10-5. Host 16-Bit Write with HWRITE Used as Strobe

HFSO-HFS1

HREAD

HCB

HWRITE

\~--I

HLDB

, strobe Low Byte

HUDB

\ strobe High Byte

HDO-HD16

HRDY

Figure 10-6. Host 16-Bit Write with

(High)

i=iI'i5S.

HUeS Used as Strobes

10-7

Host Interface Bus - Reads and Writes

HFSO-HFS1

I
\\0..-__

I
\ strobe Low Byte

\ strobe High Byte

HDO-H015 - - - - - - - - - - {

Valid Data Out

}--------

HRDY

Figure 10-7. Host 16-Bit Read with HLDS, HUDS Used as Strobes

10.3.2 Ready Signal to Host
The default state of the bus ready output pin, HRDY, is active high. HRDY is
driven inactive low to force the host processor to wait in circumstances in
which the TMS3401 0 is not prepared to allow a host-initiated register access
to be completed immediately.
HRDY is always driven low for a brief period at the beginning of a read or write
access of the HSTCTL register. When the host attempts to read from or write
to the HSTCTL register, HRDY is driven low at the beginning of the access,
and is driven high again after a brief interval of one to two local clock cycles.
When the host processor performs certain types of host interface register accesses, a local memory cycle results. For example, in reading from or writing
to the HSTDATA register, a read or write cycle on the local bus results. If the
host processor attempts to perform an access that initiates a second local
memory cycle before the TMS34010 has had sufficient time to complete the
first, the TMS3401 0 drives its HRDY output low to indicate that the host must
wait before completing the access. When the TMS3401 0 has completed the
local memory cycle resulting from the previous access, it drives HRDY high to
indicate that the host processor can now complete its second access.
A data transfer through the host interface takes place only when some combination of HCS, HREAD, HWRITE, HUDS, and HLDS are active simultaneously;
however, the HRDY signal is activated by the HCS input alone. HRDY can be
active-low only while the TMS34010 is chip-selected by the host processor,

10-8

Host Interface Bus - Reads and Writes

that is, while HCS is active low. A high-to-Iow transition on HRDY follows a
high-to-Iow transition on HCS. The benefit of this mode of operation is that
HRDY becomes valid as soon as HCS goes low, which typically is early in the
cycle. HRDY is always driven high when HCS is inactive high.
A transient low level on the HCS input may cause a corresponding low pulse
on the HRDY output. Systems that cannot tolerate such transient signals must
be designed to prevent HCS from going low except during a valid host interface access.
In summary, the following rules govern the HRDY output:
1)

If a high-to-Iow HCS transition occurs while the TMS34010 is still
completing a local memory cycle resulting from a previous host-indirect
access, HRDY goes low. If the register selected is HSTDATA, HSTADRL
or HSTADRH, HRDY remains low until the local memory cycle is completed. If the register selected is HSTCTL, the HRDY output remains low
for one to two local clock periods.

If the host is given a ready signal (HRDY high) to allow it to complete
a register access that causes a local memory read or write cycle, HRDY
stays high to the end of the access. The access ends when the strobe
for the cycle ends. The strobe ends when HREAD and HWRITE are both
inactive high, or when HLDS and HUDS are both inactive high, or when
HCS is inactive high, whichever is the first to occur. As soon as the
strobe ends, a low level on HCS allows HRDY to go low again. If the
strobe is an input other than HCS, and HCS remains low after the strobe
ends, HRDY can go low as a delay from the end of the strobe. If HCS is
the strobe for the access, the access ends when HCS goes high, and
HRDY can go low again as soon as HCS goes low again.

If HSTCTL is selected (FSO = FS1 = 1) at the high-to-Iow transition
of HCS, HRDY goes low as a delay from the fall of HCS, and remains low
for one to two local clock periods. To avoid a low-going pulse on HRDY
when accessing a register other than HSTCTL, FSO and FS1 should be
valid prior to the high-to-Iow transition of HCS.

Figure 10-8 and Figure 10-9 (page 10-10) show examples of host interface
register accesses in which HRDY is driven low.

10-9

Host Interface Bus - Reads and Writes

IC
HREADJ

)III

VaRd Funotlon select

HFSO-HFS1

HCB\

RM.~

HRDY

KlO-HD1S

Figure 10-8. Host Interface Timing - Write Cycle With Wait

HFSD-!f=S1

iMfiii'E
HCS

I
I

~
HRDY

Valid FunctIon Select

\
\

HDO-HD15 -.H-Z-----

I
IK VIIIId Data out } - - - -

Figure 10-9. Host Interface Timing - Read Cycle With Wait

10-10

Host Interface Bus - Reads and Writes

10.3.3 Indirect Accesses of Local Memory
The host processor indirectly accesses TMS34010 local memory by reading
from or writing to the HSTDATA register. HSTDATA buffers data written to
or read frQm the local memory. The word in local memory that is accessed is
the word pointed to by the 32-bit address contained in the HSTADRL and
HSTADRH registers. The pointer address is loaded into HSTADRL and
HSTADRH by the host processor before performing one or more indirect accesses of local memory using the HSTDATA register.
The four LSBs of HSTADRL are forced to Os internally so that the address
formed by HSTADRL and HSTADRH always points to a word boundary in
local memory. Between successive indirect accesses of local memory using
the HSTDATA register, the local memory address contained in the HSTADR
registers can be autoincremented by 16. This allows the host processor to
access a block of sequential words in local memory without the overhead of
loading a new address prior to each access.
During a sequence of one or more indirect reads of local memory by the host,
the TMS34010 maintains in HSTDATA a copy of the local memory word currently addressed by the HSTADRL and HSTADRH registers. Reading from
HSTDATA returns the word prefetched from the local memory location
pointed to by the HSTADRL and HSTADRH registers, and causes HSTDATA
to be updated from local memory again. Writing to HSTDATA causes the
word written to HSTDATA to subsequently be written to the location in local
memory pointed to by the HSTADRL and HSTADRH registers.
Two increment-control bits, INCR and INCW (contained in the HSTCTL register), are set to 1 to cause the pointer address in HSTADRL and HSTADRH
to be incremented by 16 during reads and writes, respectively. In preparing
to use the autoincrement feature, the appropriate increment-control bit. INCR
or (NCW, is loaded with a 1, and the HSTADRL and HSTADRH registers are
set up to point to the first location of a buffer region in the local memory.
•

When INCR=1, a read of HSTDATA causes the address in HSTADRL
and HSTADRH to be incremented before it is used in the local memory
read cycle that updates HSTDATA.

•

When INCW=1, a write to HSTDATA causes the address in HSTADRL
and HSTADRH to be incremented after it is used in the local memory
read cycle that writes the new contents of HSTDATA to local memory.

Loading the pointer address automatically triggers an update of HSTDATA to
the contents of the local memory word pointed to. No increment of HSTADRL
and HSTADRH takes place at this time regardless of the state of the increment
bits. Each subsequent host access of HSTDATA causes HSTADRL and
HSTADRH to be automatically incremented (assuming INCR or INCW is set)
to point to the next word location in the local memory. In this manner, a series
of contiguous words in local memory can be accessed following a single load
of the HSTADRL and HSTADRH registers without additional pointermanagement overhead.

10-11

Host Interface Bus - Reads and Writes

70.3.3.7 Indirectly Reading from a Buffer
Figure 10-10 illustrates the procedure for reading a block of words beginning
at local memory address N. Assume that the INCR bit in the HSTCTL register
is set to 1 and the LBL bit in HSTCTL is set to O.
•

In Figure 10-10 a, the host processor loads the 32-bit address N into
HSTADRL and HSTADRH.

•

The loading of the second half of the address into HSTADRH causes the
TMS34010 host interface control logic to automatically initiate a read
cycle on the local bus. This read cycle, shown in Figure 10-10 b,
transfers the contents of memory address N to the HSTDATA register.

•

In c, the host processor reads the HSTDATA register, fetching'the data
previously read from address N.

•

The read of HSTDATA by the host processor causes the TMS3401 0 to
automatically increment the contents of HSTADRL and HSTADRH by
16, as shown in d.

•

The contents of the new address are read into HSTDATA, as shown in
Figure 10-10 e. This data will be available in HSTDATA the next time
it is read by the host processor.

The process shown in C through e repeats for every word read from
TMS34010 local memory.

10-12

Host Interface Bus - Reads and Writes

Host

Host
Proceaaor

Local

Memory

Interface
Registers
HSTADRH HSTADRL

--......t--i''---i N+18
1--~---1N

(a)

_ _ _",,0

Host

Looal

Host
Interface
Registers

Proc8880r

Memory

HSTADRH HSTADRL
N

I-

(b)

HSTDATA
A 14--

----.

6
A

N+18
N

o
Host

Host

Proceaaor

Local

Memory

Interface
Registers
HSTADRH HSTADRL
N

(c)

~ --r

.....

---.

6
A

N+18
N

HSTDATA
A

o
Host
Procaaaor

Local

Host
Interface
Registers

Memory

HSTADRH HSTADRL
_6

N+1U

''t.0I

(d)

N+18
N

HSTDATA
A
I

o
Host

Proce880r

Host

Local

Memory

Interface
Registers
HSTADRH HSTADRL
N+1U

(e)

HSTDATA
B .J-'

.... /

N+18
N

o
Figure 10-10, Host Indirect Read from Local Memory (lNCR=1)

10-13

Host Interface Bus - Reads and Writes

10.3.3.2 Indirectly Writing to a Buffer
Figure 10-11 illustrates the procedure for writing a block of words to
TMS34010 local memory. The block begins at address N. Assume that the
INeW bit is set to 1 and the LBL bit is set to O.
•

In Figure 10-11 a, the host processor loads the 32-bit address N into
HSTADRL and HSTADRH.

•

The loading of the second half of the address into HSTADRH causes the
TMS34010 host interface control logic to automatically initiate a read
cycle on the local bus. This read cycle, which takes place in Figure
10-11 b, fetches the contents of memory address N into HSTDATA.

•

The data loaded into this register is not used, however. Instead, the host
processor writes to the HSTDATA register in Figure 10-11 c, overwriting
its previous contents.

•

In response to the host's write to HSTDATA, the TMS34010 automatically initiates a write cycle to transfer the contents of HSTDATA to the
local memory address N as shown in d.

•

Following the write, the TMS34010 automatically increments the address in HSTADRL and HSTADRH to point to the next word, as shown
in e. At this point the host interface registers are ready for the host processor to write the next word to HSTDATA.

The process shown in c through e repeats for every word written to
TMS34010 local memory.

10-14

Host Interface Bus - Reads and Writes

Host

Local
Memory

Hoat
Interface
Registers

Proc8ll8Or

HSTADRH HSTADRL

.J--

III

(a)

~
I

....

B
A

N+18
N

o
Host

Host

Proo8ll8Or

Looal
Memory

Interface
Registers
HSTADRH HSTADRl.
III

I-

(b)

HSTDATA
A
-,..-

-----.

N+18
N

o
Host

Local
Memory

Host

Proo888Ol'

Interface
Registers
HSTADRH HSTADRl.
1\1

(c)

.....

N+18
N

HSTDATA
C

o
Host

Host

Proo8ll8Or

Local
Memory

Interface
Registers
HSTADRH HSTADRL
1\1

r--

HSTDATA

(d)

CI--

c;;

N+18
N

o
Host

Host

Pro08ll8Or

Interfaoe
Registers

Looal
Memory

HSTADRH HSTADRL
N+16

(e)

N+18
N

HSTDATA
!:;
I

o
Figure 10-11. Host Indirect Write to Local Memory (lNCW=1)

10-15

Host Interface Bus - Reads and Writes

10.3.3.3 Combining Indirect Reads and Writes
If the HSTDATA register in Figure 10-11 is read by the host processor following step e, the value returned is the value that the host previously loaded
into the register. The host must read HSTDATA a second time to access data
from TMS34010 local memory. This principle is illustrated in Figure 10-12,
which shows how the host interface performs when a write is followed by two
reads. For this example, INCW=1 and INCR=O.
•

In Figure 10-12 a, HSTADRL and HSTADRH together point to location
N in the TMS3401 O's local memory. The host processor is shown writing to HSTDATA.

•

In b, the data buffered in HSTDATA is written to location N in memory.

•

The address registers are incremented in c.

•

In d, the host processor reads the HSTDATA register, which returns the
value that the host loaded into the register in step a.

•

Reading HSTDATA causes a memory read cycle to take place in e, which
loads the value from memory address N+16 into HSTDATA.

•

In f, a second read of HSTDATA by the host processor returns the value
from memory address N+16.
Local

Host
Interface
Registers

Host

Prooesaor

Memory

HSTADRH HSTADRL
N

(a)

""---t

N+18
N

HSTDATA
C

o
Host

Proceaaor

Local

Host
Interface
Registers

Memory

HSTADRH HSTADRL
N

(b)

HSTDATA

Cl--

t--

N+18
N

.-/
o

Figure 10-12. Indirect Write Followed by Two Indirect Reads
(lNCW=1,INCR=0)

10-16

Host Interface Bus - Reads and Writes

Host

Local
Memory

Host

Proce880r

Interface
Registers
HSTADRH HSTADRL

N+ll1

(c)

''t.0l
I

N+18
N

HSmATA
~

o
Host

Proc8880r

(d)

Looal
Memory

Host

Interface
Registers
HSTADRH HSTADRL
N+.111

N+18
N

HSTDATA

I---f

o
Host

Local
Memory

Host

Proc888or

Interface
Registers
HSTADRH HSTADRL

N+.ll1

(e)

HSmATA
B
l+--

N+18
N

o
Host
Pr008880r

Heat
Interface
Registers

Local
Memory

HSTADRH HSTADRL
(I)

N+.lII

N+18
N

HSTDATA
r--t

o
Figure 10-12, Indirect Write Followed by Two Indirect Reads (INCW=1,
INCR=O) (Concluded)

10-17

Host Interface Bus - Reads and Writes

70.3.3.4 Accessing Host Data and Address Registers
When the TMS34010 internal processor accesses the HSTDATA, HSTADRL,
or HSTADRH register, no subsequent cycle occurs to transfer data between
HSTDATA and local memory. Also, the address in HSTADRL and HSTADRH
is not incremented, regardless of the state of the INCR and INCW bits.
The host processor can indirectly access any register in the TMS34010's internal I/O register file by first loading HSTADRL and HSTADRH with the address of the register, and they writing to or reading from HSTDATA.
No hardware mechanism is provided to prevent simultaneous accesses of the
HSTDATA, HSTADRL and HSTADRH registers by the host processor and by
the TMS3401 0 internal processor. Software must be written to avoid simultaneous accesses, which can result in invalid data being read from or written
to these registers.

70.3.3.5 Downloading New Code
The TMS34010 host interface provides a means of efficiently downloading
new code from a host processor to TMS3401 0 local memory. The host initiates this operation through the following process:
•

Before downloading, the host interrupts and halts the TMS34010 by
writing 1s to the H LT and N M I bits in the HSTCTL register. The host
processor should then wait for a period of time equal to the TMS3401 0
interrupt latency. (TMS34010 hardware resets the NMI bit if the nonmaskable interrupt is initiated before the halt occurs.)

•

The code is then downloaded using the auto-increment features of the
host interface registers.

•

After downloading the code, the host should flush the cache as described in Section 5.4.5, Flushing the Cache (page 5-23).

•

The nonmaskable interrupt vector is written through the host port to location FFFFFEEOh so that the new code begins execution at the vectored address.

•

The NMI bit in the HSTCTL register should be set to 1 to initiate a nonmaskable interrupt. At the same time, the NMIM bit in the HSTCTL register should be set to 1. If the host does not need the current context
to be stored on the stack, or if the nonmaskable interrupt was taken in
the first step, the NMIM bit should be set to 1. Otherwise, NMIM should
be set to O.

•

The host restarts the TMS34010 by writing a 0 to the H LT bit in the
HSTCTL register.

Setting the HLT and NMI bits to 1 simultaneously reduces the worst-case
delay (compared to setting HLT only). NMI latency is the delay from the 0to-1 transition of the NMI bit and the start of execution of the first instruction
of the NMI service routine. Halt latency is the delay from the 0-to-1 transition
of the HLT bit and the time at which the TMS3401 0 actually halts (see Section 10.3.4). The maximum N M I latency may be much less than the halt la10-18

Host Interface Bus - Reads and Writes

tency if a PIXBLT, FILL, or LINE instruction is in progress at the time of the
NMI or halt request. An NMI request interrupts instruction execution at the
next interruptible point, but a halt request is ignored until the executing instruction completes or is interrupted. When NMI and HLT are set to 1 simultaneously, the TMS34010 halts before beginning execution of the first
instruction iri the N M I service routine. Therefore, the delay from the setting
the N M I and H LT bits to the time that the TMS3401 0 actually halts is simply
the N M I latency.

10.3.4 Halt Latency
The TMS34010 may be halted by a host processor via the H LT bit in the
HSTCTL register. The delay from the receipt of a halt request to the time that
the TMS3401 0 actually halts is the sum of five potential sources of delay:
1)
2)
3)
4)
5)

Halt request recognition
Screen-refresh cycle
DRAM-refresh cycle
Host-indirect cycle
Instruction completion

In the best case, items 2 through 5 cause no delay. The minimum delay to due
to item 1 is one machine state.
•

The halt request recognition delay is the time required for the setting
of the HLT bit to be internally synchronized after the low-to-high transition of the HRDY pin.

•

The screen-refresh and DRAM-refresh cycles are a potential source
of delay, but in fact occur rarely and are unlikely to delay a halt.

•

The likelihood of a delay caused by a host-indirect cycle is small in
most instances, but this depends largely on the application. It would
only occur if the host had written to the data register just prior to writing
to the HLT bit. The delay due to a single host-indirect cycle is two machine states, assuming no wait states.

•

The instruction completion time refers to the time required for an instruction that was already executing at the time the halt request was received to complete. Note that the TMS3401 0 halt condition is entered
only on instruction boundaries. This means that a PIXBLT, FILL, or
LINE instruction that is already in progress runs to completion before the
TMS34010 halts.

Table 10-2 shows the minimum and maximum times for each of the five operations listed. The halt latency is calculated as the sum of the numbers in the
five rows. In the best case, the halt latency is only one machine state. The
worst-case latency is six machine states plus the delays due to host-indirect
cycles and instruction completion. Table 10-3 shows instruction completion
times for some of the longer instructions. However, a PIXBLT, FILL, or LINE
instruction may take longer than the times shown in Table 10-3, depending
on the size of the pixel array or line specified. Table 10-3 also shows the instruction completion time for a JRUC instruction that jumps to itself - the
TMS34010 may be executing this instruction if the software is simply waiting
for a halt.
10-19

Host Interface Bus - Reads and Writes

Table 10-2. Five Sources of Halt Delay
Operation

Latency (In States)
Min

Max

Halt recognition

Instruction completion

See Table 10-3

DRAM-refresh cycle

2
See Note 2

Screen-refresh cycle

2
See Note 2

Host-indirect cycle

See Note 1

Notes:

1) The latency due to host-indirect cycles depends
on both the hardware system and the application.
The delay due to a single host-indirect cycle is two
machine states, assuming no wait states.
2) DRAM-refresh and screen-refresh cycle times assume no wait states.

Table 10-3. Sample Instruction Completion Times
Instruction

Worst-Case Instruction
Completion Time (In States)
SP Aligned

DIVS AO,A2

SP Not Aligned

43
72
144
MMTM SP,ALL
73
169
PIXBLT, FILL, and LINE
See Note 1
See Note 1
Wait: JRUC wait
1
1
Notes: 1) The worst-case instruction completion time IS equal to the instruction execution time less one machine state.
2) The SP-aligned case assumes that the SP is aligned to a word
boundary in memory.
MMFM SP,ALL

10.3.5 Accommodating Host Byte-Addressing Conventions
Processor architectures differ in the manner in which they assign addresses to
bytes. The TMS3401 0 host interface logic can be programmed to accommodate the particular byte-addressing conventions used by a host processor.
This ability is important in ensuring software compatibility between 8- and
16-bit versions of the same processor, such as the 8088 and 8086 or the
68008 and 68000. The 8088 transfers a 16-bit word as a series of two 8-bit
bytes, low byte first, high byte second. The 68008 transfers the high byte first,
and low byte second.
The HSTCTL register's LBL bit is used to configure the TMS3401 0 host interface to accommodate different byte-accessing methods. The host interface
is configured to operate according to the following two principles:

10-20

Host Interface Bus - Reads and Writes

First, when a host processor with an 8-bit data bus reads from or writes
to the HSTDATA register, it accesses the high and low bytes of the register in separate cycles. The TMS3401 0 does not initiate its local memory access until both bytes of HSTDATA have been accessed.

Second, when HSTADRH and HSTADRL are loaded by the host, the
TMS34010 must not initiate its read of the local memory until the complete pointer address has been loaded into HSTADRL and HSTADRH.

When LBL=O:
•

A local memory read cycle is intitiated by the TMS3401 0 when the host
processor reads the high byte of HSTDATA, or writes to the high byte
of HSTADRH.

•

A local memory write cycle is initiated by the TMS3401 0 when the host
processor writes to the high byte of HSTDATA.

When LBL=1:
•

A local memory read cycle is initiated by the TMS3401 0 when the host
processor reads the low byte of HSTDATA, or writes to the low byte of
HSTADRL.

•

A local memory write cycle is initiated by the TMS3401 0 when the host
processor writes to the low byte of HSTDATA.

When the host processor is an 8088, for example, the TMS3401 0 is typically
configured by setting the LBL bit of the HSTCTL register to O. When configured in this manner, the TMS34010 expects the HSTADRL register to be
loaded first, and HSTADRH loaded second. Furthermore, the high byte of the
HSTADRH register is expected to be loaded after the low byte. When LBL is
set to 0, a local read cycle is initiated when the upper byte of the HSTADRH
register is written to by the host processor. This permits the lower byte of
HSTADRH to be loaded first without causing side effects.

10-21

Host Interface Bus - Bandwidth

10.4 Bandwidth
One measure of the performance of the host interface is its data rate, or
bandwidth. The bandwidth is the number of bits per second that can be
transferred through the host interface during a block transfer of data to or from
TMS34010 memory. Assume that the host interface address register is programmed to autoincrement. The maximum data rate through the host interface
can be expected to approach the bandwidth of the TMS3401 O's memory. For
example, assume a 50-MHz TMS34010 and a memory requiring no wait
states. The memory cycle time is about 320 nanoseconds (bandwidth = 50
megabits/second). The host's access cycle time at the host interface is somewhat longer than this due to certain additional delays inherent in the operation of the TMS34010's internal host interface logic. Also, the throughput
of the host interface may depend on whether or not the TMS3401 0 is halted.
The bandwidth is calculated as the width of the host data path (16 bits) times
the frequency of access cycles through the host interface. Given a continuous
series of word accesses, with successive accesses occurring at regular intervals, what is the minimum interval between host accesses that the interface
can sustain without having to send not-ready signals to the host? (The
TMS34010 drives its HRDY output low temporarily to inform the host when
the TMS3401 0 is not yet ready to complete the host's current access.)
First, when the TMS34010 is halted, the host interface should support continuous accesses occurring at regular intervals no less than about 400 nanoseconds apart. As long as the host attempts to maintain a throughput no
greater than this limit, delays due to not-ready signals occur rarely, if at all.
The bandwidth for this case is calculated in Table 10-4 a as approximately 40
megabits per second. This value can be expected to vary slightly with system-dependent conditions such as the frequency of DRAM-refresh and
screen-refresh cycles.
When the TMS3401 0 is running, the host interface should support continuous
accesses occurring at regular intervals no less than approximately 550 nanoseconds. The bandwidth for this case is calculated in Table 10-4 as approximately 29 megabits per second. This value varies slightly with conditions such
as the frequency of DRAM-refresh and screen-refresh cycles, and also with the
characteristics of the program being executed by the TMS3401 O.
Table 10-4. Host Interface Estimated Bandwidth
Assumptions

10-22

Approximate Throughput

TMS34010 halted
50-MHz TMS34010
No wait states

16 bits/transfer
400 ns/transfer

TMS34010 running
50-MHz TMS34010
No wait states

550 ns/transfer

16 bits/transfer

= 40 megabits/s
= 29 megabits/s

Host Interface Bus - Worst-Case Delay

10.5 Worst-Case Delay
In some applications, designers must determine not only the effective
throughput of the host interface, but also the delays that can occur under
worst-case conditions. These conditions occur too rarely to affect overall
throughput, but the important consideration here is not how often they occur,
but that they can occur at a". First, with the TMS34010 halted, the worst
delay is given by the formula (6 + 2N) T, where N is the number of wait states
per TMS3401 0 memory cycle, and T is the local clock period (nomina"y 160
nanoseconds for a 50-MHz TMS3401 0). Second, with the TMS3401 0 running, the worst delay is given by the formula (9 + 4N) T. The derivation of
these formulas, summarized in Figure 10-13, may be helpful in illustrating the
mechanisms of the host interface.
2T

(2 + N)T
(2 + N)T

+ 2N)T

Synchronization delay
Screen-refresh cycle
DRAM-refresh cycle
Worst-case delay (total)

(a) Worst-Case Delay with TMS34010 Halted

2T
(1 + N)T
(2 + N) T
(2 + N) T
+ (2 + N)T
(9

+ 4N) T

Synchronization delay
TMS34010 CPU read
TMS34010 CPU write
Screen-refresh cycle
DRAM-refresh cycle
Worst-case delay (total)

(b) Worst-Case Delay with TMS34010 Running

= Number of wait states per memory cycle

Local clock period (nominal 160 nanoseconds for 50-MHz device)

Note: These are worst-case delays and have negligible effect on performance. The case
shown in a, for example, could be expected to occur less than once per thousand
(0.1 percent of) host accesses in a typical system.

Figure 10-13. Calculation of Worst-Case Host Interface Delay

Consider case a, in which the TMS3401 0 is halted, first; the worst-case delay
is calculated as the sum of the three delays. The first of these delays is the time
required to internally synchronize the host interface cycle to the TMS34010
local clock.
The host's signals are generally not synchronous to the
TMS34010 local clocks. A signal from the host must therefore be passed
through a synchronizer latch (part of the TMS34010 on-chip host interface
logic) before being used by the TMS34010. The delay through the synchronizer is from one to two local clock periods (1 T to 2T), depending on the
phase of the host clock relative to the TMS3401 O's local clock. The second
and third delays in Figure 10-13 represent the time needed to perform a
screen-refresh cycle followed by a DRAM-refresh cycle. The arbitration logic
internal to the TMS3401 0 assigns these two types of cycles higher priorities
than host-requested indirect accesses. (Screen refresh has a higher priority
than DRAM refresh.) Thus, a host access requested at the same time as one
of these cycles must wait. The worst-case assumption is that a screen-refresh
cycle is generated internal to the TMS3401 0 on the same clock edge at which
the request for the host access arrives. Furthermore, a DRAM-refresh cycle is
10-23

Host Interface Bus - Worst-Case Delay

requested during this same clock edge or during the next 1 + N clock edges.
An equivalent delay occurs in the case in which a DRAM refresh and host
access are requested on the same clock edge (the DRAM refresh wins), and
a screen refresh is requested on a later clock edge before the host access can
begin. This case is not shown in Figure 10-13, but the delay in this instance
is also (6 + 2N)T. In a typical system, DRAM-refresh cycles consume about
2 percent of the available memory bandwidth, and screen-refresh cycles take
about 1.5 percent (using VRAMs). The probability of either sequence of
events is therefore very small (less than one in a thousand, assuming N = 0;
that is, no wait states), and the performance degradation due to these unlikely
events is negligible.
Now consider the case in which the TMS3401 0 is running. Host accesses are
of higher priority than TMS34010 instruction fetches and data accesses, but
still of lower priority than DRAM-refresh or screen-refresh cycles. The worstcase delay is calculated as the sum of the five delays indicated in Figure 10-13
b. This assumes that the TMS34010 begins a read-modify-write operation
on a memory word (this is performed as a read cycle followed by a separate
write cycle) just one clock before the TMS3401 0 receives the host access request. The TMS3401 0 CPU read cycle is actually (2 + N) T in duration, but
since it begins one clock before the host access is requested, only (1 + N) T
is left in the cycle. The TMS34010's local memory controller treats a readmodify-write operation as indivisible; once the read has started, no other request can be granted until the write completes. The write cycle is (2 + N) T
in duration. Again, assume that sometime before the write cycle does complete, screen-refresh and DRAM-refresh cycles are also requested. The probability of this case is somewhat more difficult to calculate than that of Figure
10-'3 a, since the frequency of read-modify-write operations is very program
dependent. This sequence of events rarely occurs, however.

10-24

Section 11

Local Memory Interface

The TMS34010 local memory interface consists of a triple-multiplexed
address/data bus and associated control signals. Several types of memory
cycles, including read, write, screen-refresh, and DRAM-refresh cycles are
supported. During a memory cycle, the row address, column address, and data
are transmitted over the same physical bus lines. The row and column addresses necessary to address DRAMs and VRAMs are available directly at the
address/ data pins, eliminating the need for external multiplexing hardware.
The TMS34010 interfaces directly to DRAMs (such as the TMS4256 and
TMS4C1024) and VRAMs (such as the TMS4461), and can be programmed
to perform DRAM-refresh cycles at regular intervals. CAS-before-RAS or
RAS-only refresh cycles may be selected. The TMS34010 can also be programmed to perform screen refresh by scheduling VRAM register-transfer cycles to occur at regular intervals.
The local memory interface provides a hold/hold acknowledge capability that
allows external devices to request control of the bus. After acknowledging a
hold request, the TMS3401 0 releases the bus by driving its address/data bus
and control outputs into high impedance.

Section
Page
11.1 Local Memory Interface Pins ................................................................ 11-2
11.2 Local Memory Interface Registers ........................................................ 11 -3
11.3 Memory Bus Request Priorities ............................................................ 11 -4
11.4 Local Memory Interface Timing ............................................................ 11 -5
11.5 Addressing Mechanisms ..................................................................... 11-23

11-1

Local Memory Interface Bus - Local Memory Interface Pins

11.1 Local Memory Interface Pins
Section 2 describes TMS34010 pin functions in detail. This section briefly
summarizes the local memory interface pins.
LADD-LAD15
These pins form the local multiplexed address/data bus.
DEN

The local data enable signal is driven active low to allow data to
be written to or read from LADo-LAD15. (Connects to the G pins
of a pair of optional '245-type octal bus transceivers.)

DDOUT

The local data direction out signal is driven high to enable data to
be output on LADo-LAD15. It is driven low to enable data to be
input on LADo-LAD15. (Connects to the DIR pins of a pair of
optional '245-type octal bus transceivers.)

LAL

The high-to-Iow transition of the local address latched signal is
used by an external '373-type latch to capture the column address
from LADo-LAD15.

RAS

The local row address strobe signal drives the RAS inputs of
DRAMs and VRAMs.

CAS

The local column address strobe signal drives the CAS inputs of
DRAMs and VRAMs.

The local write strobe signal drives the Vii inputs of DRAMs and
VRAMs.

TR/QE

The local register transfer/output enable signal connects to the
TR/QE (or DT/OE) pins of a VRAM.

LRDY

The local ready signal is driven low by external circuitry to inhibit
the TMS3401 0 from completing a local memory cycle.

INCLK

TMS34010 processor functions are synchronous to this input
clock signal. (Video timing is controlled by VCLK.)

LCLK1,
LCLK2
LlNT1,
LlNT2

11-2

These output clocks are available to the board designer for synchronous control of external circuitry.
Interrupt requests are transmitted to the TMS3401 0 on these pins.

Local Memory Interface Bus - Local Memory Interface Registers

11.2 Local Memory Interface Registers
The local memory interface registers are summarized below. These registers
are a subset of the I/O registers which are detailed in Section 6.
•

The memory CONTROL register contains several programmable parameters that provide control of the local memory interface:

RM (DRAM refresh mode, bit 2):
CAS-before-RAS refresh cycles.

Selects

RAS-only or

RR (DRAM refresh rate, bits 3 and 4): Controls the frequency of
DRAM refresh cycles.

T (transparency enable, bit 5): Enables or disables the pixel attribute of transparency.
W (window violation detection mode, bits 6 and 7): Selects the
course of action the TMS3401 0 follows when it detects a window
violation.

PBH (PIXBLT horizontal direction, bit 8): Determines the horizontal direction (increasing X or decreasing X) for pixel operations.
PBV (PIXBLT vertical direction, bit 9): Determines the vertical direction (increasing Y or d~greasing Y) for pixel operations.
PPOP (pixel processing operation select, bits 10-14): Selects
among several Boolean and arithmetic pixel processing options.
CD (instruction cache disable, bit 15): Enables or disables the instruction cache.
•

The CONVDP register contains the destination pitch conversion factor
that is used during XY -to-linear conversion of a destination pixel address.

•

The CONVSP register contains the source pitch conversion factor that
is used during XY-to-linear conversion of a source pixel address.

•

The PMASK (plane mask) register selectively disables or enables various planes in a multiple-bit-per-pixel bit map display.

•

The PSIZE (pixel size) register specifies the number of bits per pixel.

•

The REFCNT (refresh count) register generates the addresses output
during DRAM-refresh cycles and counts the intervals between successive DRAM-refresh cycles.

11-3

Local Memory Interface Bus - Memory Bus Request Priorities

11.3 Memory Bus Request Priorities
The TMS34010's local memory interface controller assigns priorities to requests from various sources, both on and off chip, for local memory cycles.
Table 11-1 lists these priorities (priority 1 is highest).

Table 11-1. Priorities for Memory Cycle Requests
Priority

Memory Cycle Requested

Hold request from external bus master device

Screen-refresh cycle

DRAM-refresh cycle

Host-initiated indirect read or write cycle

TMS34010 CPU memory cycle

A TMS34010 CPU memory cycle is a read or write performed by the
TMS34010's on-chip 32-bit processor. Insertion of a field (or a portion of a
field spanning multiple words) into a word requires two CPU memory cycles
when the field does not begin and end on word boundaries. The two cycles
are a read followed by a write. This sequence is called a read-modify-write
operation. The read and write are performed as separate memory cycles, but
are treated as indivisible; that is, the memory controller does not permit another
memory request to be serviced between the read and its accompanying write.
The only exception to this statement is the hold request. If a read-modifywrite is interrupted by a hold, the entire read-modify-write operation is restarted after the hold is released.
While a read-modify-write operation on an individual memory word is indivisible, the accesses necessary to extract or insert a field spanning multiple
memory words are not. For example, if a field spans portions of two memory
words, a higher priority access such as a host-indirect cycle can occur between the two read-modify-write operations required to insert the field.
The hold request has the highest priority. An external device requests control
of the bus by signalling a hold request to the TMS3401 O. The external device
may perform multiple memory cycles following acknowledgment from the
TMS34010. However, the device should not control the bus for so long that
necessary screen-refresh and DRAM-refresh cycles are prevented from occurring. Indirect accesses initiated by a host processor are blocked as long as the
external device continues to control the bus. If the host processor attempts
to initiate another indirect access during this time, the host is forced to wait
at the host interface (the TMS34010 sends it a not-ready signal) until the
external device releases the local bus.
A memory cycle already in progress is always permitted to complete, even if a
higher priority request is received while the cycle is still in progress.

11-4

Local Memory Interface Bus - Local Memory Interface Timing

11.4 Local Memory Interface Timing
The TMS34010 memory interface contains a triple-multiplexed address/data
bus on which row addresses, column addresses and data are transmitted.
Figure 11 -1 illustrates multiplexing of addresses and data.

RF = DRAM-Refreah bus status bit
IAQ = Instruction acquisition bus status bit
TR = \/RAM Shlft-Reglater-Transfer bus status bit

Figure 11-1. Triple Multiplexing of Addresses and Data

The TMS34010 LAD pins directly provide the multiplexed row and column
addresses needed to drive dynamic RAMs (like the TMS4256) and video
RAMs (such as the TMS4461). Any eight adjacent pins in the range
LADQ-LAD1 0 provide 16 contiguous logical address bits; the eight MSBs are
output as part of the row address, and the eight LSBs are output as part of the
column address. For example, Figure 11 -1 shows that logical address bits
5-20 are output at LAD1-LAD8.
The control signals output to memory support direct interfacing to DRAMs
and VRAMs. At the beginning of a memory cycle, the address is output in
multiplexed fashion as a row address followed by a column address. The remainder of the cycle is used to transfer data between the TMS34010 and
memory.
Figure 11 -2 (page 11 -6) illustrates general timing (the local
address/data pins are identified as the LAD Bus)
11-5

Local Memory Interface Bus - Local Memory Interface Timing

LAD Bus

RA8
CAS

=:::x

Row
6slUli

X;::X

Data

\
\

x::

Figure 11-2. Rowand Column Address Phases of Memory Cycle

Figure 11 -3 through Figure 11 -8 show functional timing of the local memory
interface. Several timing features are common to the memory read and write
cycles in Figure 11 -3 and Figure 11 -4, and to the register-transfer cycles in
Figure 11 -6 and Figure 11 -7. A row address is output on LADo-LAD15 at the
start of the cycle, and is valid before and after RAS falls. A column address is
then output on LADo-LAD15. The column address is valid briefly before and
after the falling edge of LAL, but is not valid at the falling edge of CAS. The
column address is clocked into an external transparent latch (such as a
74AS373 octal latch) on the falling edge of LAL to provide the hold time on
the column address required for DRAMs and VRAMs. A transparent latch is
required so that the row address is available at the outputs of the latch during
the start of the cycle.

11-6

Local Memory Interface Bus - Local Memory Interface Timing

11.4.1 Local Memory Write Cycle Timing
Figure 11 -3 illustrates a memory write cycle.
Data are output on
LADQ-LAD15 following the latching of the column address. DEN goes active
low at the same time the data become valid, and remains low as long as the
data remain valid. In a large system that requires buffering of the data bus to
memory, DEN is typically used as the enable signal to an external bidirectional
buffer (such as a 74AS245 octal buffer). DDOUT is used as the direction
control signal to the buffer. The write strobe, W, goes active low after the data
have become valid and CAS is low. This is interpreted as a "late write" cycle
by the DRAMs and VRAMs, which are prevented by the inactive-high TR/OE
signal from enabling their read drivers. Because the data are valid on both
sides of the Vii write strobe, external devices can latch the data on either the
high-to-Iow or low-to-high edge of W.
1~1~IOOI~I~I~IOOI~I~1

I
LCLK1 (
LCLI<2

L.ADO-LAD16

11\ I
. I
I
I
I r--III---I\I
I
I
I
I

I
I

I
L...V
I

----v.
r-i"

Row

I I(,--tI -",,1\
I _
I
I.
I
I
I
I I
I
I
I
I I
I
I

1\ : V
vtiv
I"'ri" I

I I(~-+-III :.
I
I
I
'" I I

I: I

i~'-ii~I_-I!V-

Data

x:::::

II Ii I
I
I
I " I
I
1---;'--""1\
I
I I I
I " I
I
I
I
I '--!j-+!-+j--+I--I--"""j : I
I
I : IV~--ILAL '"'11-01--1-1-1-1'"""'It. I
,I:~ I, I
i I I

RAS I

CAS!I

Vi I

I
I
I

I
_
I
TRJOEI
I

;1;\ !
I:

I : I~
I: I
I
I i I
I
III
I
I I I
I
I

!
IV:!

I t'l
I
I
I i I

I
I
I
I

1:1

I : I
I : I
I

DDOUT

LADY

Figure 11-3. Local Bus Write Cycle Timing

11-7

Local Memory Interface Bus - Local Memory Interface Timing

11.4.2 Local Memory Read Cycle Timing
Figure 11 -4 illustrates a memory read cycle. LADQ-LAD15 are forced to high
impedance following the latching of the column address. DEN and TR/QE both
go active low after CAS becomes low in order to enable read data from the
memory to the LAD pins. TR/QE enables the output drivers of the DRAMs and
VRAMs. DEN enables the external bidirectional buffers needed with memories
so large that external buffering (using a device such as a 74AS245 octal buffer) of the data bus is required. The DDOUT signal serves as the direction
control for the external bidirectional buffers, and is low well in advance of the
high-to-Iow transition of DEN, and remains low well after the low-to-high
transition of DEN. The data that is read from memory must be valid during the
middle of the Q4 clock phase, as indicated in Figure 11-4. The low-to-high
transitions of TR/QE and DEN occur well in advance of the time at which the
LAD drivers turn on to output the row address of the next cycle. This prevents
bus conflicts.

I 01
LCLK1

V~-:--~

I 01

I 03

~,---,-+-->V'---'---

LADO·LAD15

[AI

Vrl-I-+--

I --,--r.-

1
DDOUT

Figure 11-4. Local Bus Read Cycle Timing

11-8

Local Memory Interface Bus - Local Memory Interface Timing

11.4.3 Local Register-to-Memory Cycle Timing
A register-to-memory cycle is a special type of cycle used in systems with
VRAMs. The cycle transfers the contents of the VRAM's internal serial-data
register to a selected row of its internal memory array. The cycle typically affects a" VRAMs in the system. During the register-to-memory cycle shown
in Figure 11 -5, both TR/QE and Vii are low during the fa" of RAS. VRAMs recognize this timing as the beginning of a register-to-memory cycle. Conventional DRAMs may need to be de-selected (by withholding the row or column
address strobe, for example) to prevent them from interpreting the cycle as a
conventional read cycle. Alternately, the output enable signal required by a
DRAM such as the TMS4464 can be synthesized by connecting DEN and
DDOUT to the inputs of a two-input OR gate. (In fact, any pair of the signals
DEN, DDOUT, and TR/QE wi" work.) The low-to-high transition of TR/OE
occurs after the fa" of CAS but prior to the rising edge of RAS. This timing
provides compatibility with a variety of VRAMs.
The TMS3401 0 performs a register-to-memory cycle when writing to a pixel
while the DPYCTL register's SRT bit is set to 1. For example, the instruction
PIXT AO, *Al writes the pixel in AO to the address pointed to by A1. The
PSIZE register should contain the value 16 so that the write cycle is not preceded by a read cycle. When SRT is set to 1, this write is converted to the
register-to-memory cycle shown in Figure 11 -5. The row address is selected
from bits 12-26 of A1, which are output on LADo-LAD14 during the cycle.
I Q11 Q2 I Q3 I Q4 I Q1 I Q2 I Q3 I Q4 I Q1 I

LCLK1 ('

I
I
I
Ii
LCLK2 !L...-....V

LADO-LAD15

"
'\
,
II

'(
I" '.
,
', \
.': 'I

'II'~'I

------t--t H1oz1--V I i"--t--tH1oZt--Vi--I -r--TH1oZr-I
I
II

I
II

I
I

I
I
I
I
1;r--1\1

I
I

I
I
I
I
1r---1\'

I
I

: DoQ:
I

!At

'-+-+--+-li--i'r
II
II

+--1-+---1-..

:
r+---I..
I

I
I

1--r--rH"T--I I I: 1--t--r H1oz l--Tli/liI -t----i--+----i--t---!--+I--+I--+I-....I\.._L_~ HlozL __
I I II

1111

i i i

V1- -tH1oZt--I

I
I

Figure 11-15. TMS34010 Releases Control of Local Bus

In Figure 11 -15, the first active-low pulse of the HLDA/EMUA output is an
early acknowledgment, and the bus is not released for another three quarters
11-19

Local Memory Interface Bus - Local Memory Interface Timing

of a clock. The early acknowledgment gives advance warning to the device
requesting the hold that the bus is about to be released by the TMS34010,
allowing the device time to prepare to become the new bus master. The
TMS34010 outputs the active hold acknowledge signal only when it is prepared to release the bus within the next clock period. If the TMS3401 0 must
wait longer than this to release the bus, its hold acknowledgment is withheld
until it can release the bus.
For instance, if the LRDY signal in Figure 11-15 were low instead of high at
the second rising edge of LCLK2, the TMS3401 0 would be forced to wait, and
would therefore not acknowledge the hold request until later, when the notready condition was removed. Also, if the hold request in Figure 11-15 was
asserted initially during the first LCLK2 rising edge rather than the second, the
TMS34010 would delay its hold acknowledgment until the second LCLK1 low
clock phase, knowing that the cycle in progress would not be completed until
the third 02 phase in the diagram.
A hold request has a higher priority than any internally generated memory cycle requests, including:
•
•
•
•

Screen refresh
DRAM refresh
Indirect access by the host processor
TMS34010 instruction fetch or data access

A hold request is delayed only to allow a memory cycle already in progress to
complete.
External devices can activate or deactivate the HOLD input during any clock
of an ongoing cycle, as long as the input is stable during the rising edge of
LCLK2. The HOLD input is synchronous and is required to meet specified
setup and hold times to ensure that the TMS3401 0 operates correctly. After
the TMS3401 0 grants the bus to an external device (via an active-low level
on the HLDA/EMUA output during the 03 clock phase), it continues to acknowledge the hold request during the 03 phases of subsequent clock cycles.
The external device retains control of the bus until it deactivates its hold request.
External devices should avoid placing the TMS3401 0 in hold for long periods.
While the TMS34010 is in hold, it can perform neither screen-refresh nor
DRAM-refresh cycles. Furthermore, a host processor attempting to access the
TMS34010's local memory through the host interface registers while the
TMS34010 is in hold may receive a not-ready signal. When this occurs, the
host is forced to wait to complete its access until the TMS34010 leaves the
hold state. (Refer to Section 9.10.1.5, Scheduling Screen-Refresh Cycles, on
page 9-27 for more information.)
If a request for a DRAM-refresh or screen-refresh cycle is generated within the
TMS34010 while an external device controls the bus, the TMS3401 0 retains
the request and perform the DRAM-refresh or screen-refresh cycle after the
external device has returned control of the bus to the TMS3401 O. However,
if a requested DRAM-refresh cycle is prevented from occurring for so long that
a second DRAM-refresh cycle is requested before the first DRAM-refresh cycle can occur, the first DRAM-refresh request is lost. Similarly, if a screenrefresh request is prevented from occurring for so long that a second
11-20

Local Memory Interface Bus - Local Memory Interface Timing

screen-refresh cycle is requested before the first screen-refresh cycle can occur, the first screen-refresh request is lost.
The HLDA/EMUA output is multiplexed between the hold acknowledge
(HLDA) and emulate acknowledge (EMUA) signals. The HLDA signal is output
during the LCLK1 low phase, and the EMUA signal is output during the LCLK1
high phase.

I 01
LCLK1

LCLK2

JI
I
I
I

02: 03

f\
I

04 : 01

V
I
I
I

02 II 03

f\
I

04 : 01

Figure 11-16. TMS34010 Resumes Control of Local Bus

11-21

Local Memory Interface Bus - Local Memory Interface Timing

11.4.12 Local Bus Timing Following Reset
Figure 11 -17 shows the timing of the local bus signals following reset. At the
end of reset, the TMS3401 0 automatically performs a series of eight RAS-only
refresh cycles, as required to initialize certain DRAMs (such as the TMS4256
and TMS4464) and VRAMs (such as the TMS4461) following power-up;
The asynchronous low-to-high transition of RESET is sampled at the second
high-to-Iow LCLK1 transition in Figure 11-17. In less than two local clock
periods following this LCLK1 transition, the first of the eight RAS-only cycles
begins, as shown at the right side of Figure 11-17.
Each of the eight RAS cycles f.ollowing reset is two clock periods in duration,
but can be extended by a not-ready signal (LRDY low). The timing for each
cycle is identical to that of a RAS-only DRAM-refresh cycle, including the bus
status codes output during the row and column address times. The row address for each of the eight RAS-only cycles is all Os.

FIRST OF 8 HAS-ONLY

1 4 - - - - - 7 t Q - - - - - I..
-I /

Q3i Q4 I Q1

I
I
I

LCLK1

CYCLES 8EGINS

Q2 i Q3

I
I
I

LCLK2

LADO-LAD15

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I JI
-4 HI-Zr--I--.,-_.L_-r--I--j---I---,--4--T--I--1\.
I
I
I
I
:
I
I
I
I
I
I
I
I
I,
:
I
:
I
I
I
:
I
:
I
:
I
:
:

I
I
;
ROW

.
I

;-~~'-~r-~-r--r-+--T-+--;-;-~--'-~
iiA'§

I
:
I

I
I
I

K
:

"
I
I
I
I
I

I
I
:

~.w.m/~. ~~~-+--+-~--~--~-+--~~~-+--+-~--~--r--+--+
imii.DDOUT

Figure 11-17. Local Bus Timing Following Reset

11-22

Local Memory Interface Bus - Addressing Mechanisms

11.5 Addressing Mechanisms
The TMS3401 0 addresses memory by means of a 32-bit logical address. As
explained in Section 3, each 32-bit logical address points to a bit in memory.
Logical address bits are numbered from 0 to 31, where bit 0 is the LSB and
bit 31 is the MSB. Figure 11 -18 illustrates the manner in which address bits
4-29 are output to physical memory. Each column in the figure indicates an
address/data bus pin, LADO-LAD15, and below it is the corresponding bit of
the logical address output at the LAD pin during the fall of RAS and during the
fall of CAS. Bus status bits RF, TR, and lAO are output on LAD14-LAD15.

At Fall
of RAS
At Fall
lAC TR 29 28 27 14 13 12 11 10 9
of CAS
Bus status signals:
RF - DRAM refresh cycle
lAO - Instruction acquisition cycle
TR - Register-transfer cycle

TMS34010
Logical
Addfess
Bits
t

LAD Pin Numbers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Rl' 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12

Figure 11-18. External Address Format

Key features of the local bus addressing mechanism include the following:
•

The two MSBs of the 32-bit logical address (bits 30 and 31) are not
output.

•

The four LSBs of the 32-bit logical address (bits 0 to 3) are not output,
but are used internally to designate a bit boundary within a 16-bit word
accessed in the external memory.

•

The address bits output on LADQ-LAD10 during the falling edges of RAS
and CAS are aligned so that 16 consecutive bits from the logical address
are available at any eight consecutive pins in the range LADO to LAD10.
The address bits are output in this way in order that the 8-bit row address and 8-bit column address presented to the dynamic RAMs can always be taken from the same eight address/data pins. This eliminates
the need for external address multiplexers.

•

Logical address bits 12-14 are output twice during a memory cycle during both the RAS and CAS falling edges - but at different pins. This
allows a variety of memory organizations and decoding schemes to be
used.

Pins LADQ-LAD10 form an 11-bit zone in which logical address bits 12-14
are overlapped (that is, they are issued in both cycles, but on different pins).
The row and column address bus is connected to any eight consecutive pins
within this zone. The actual position is determined by the bank-decoding
scheme selected for a particular memory organization.

11-23

Local Memory Interface Bus - Addressing Mechanisms

Output along with the address are three bus status signals:
•

The RF (DRAM refresh) bit is output on LAD15 during the fall of RAS.
It is low if the cycle that is just beginning is a DRAM-refresh cycle (either RAS-only or CAS-before-RAS); otherwise, RF is high.

•

The TR (VRAM register transfer) bit is output on LAD14 during the fall
of CAS, and is low if the cycle in progress is a video RAM register
transfer. Otherwise, TR is high. In either event, the state of the TR bit
reflects the state of the TR/QE output during the falling edge of RAS
within the same cycle.

•

The lAO bit is output on LAD15 during the fall of CAS, and is high if the
cycle is an instruction fetch; otherwise, lAO remains low. The term instruction fetch includes not only reads of opcodes, but also immediate
data, immediate addresses, and so on.

lAO is active high when words are fetched from memory to load the instruction cache. A cache subsegment (a block of four words) is loaded in a
series of read cycles, during which lAO is active high. The PC points to an
instruction word within the block, but the block may contain data as well as
instruction words (opcodes, immediate addresses, immediate data, and so on).
Only during execution can the TMS3401 0 distinguish instruction words from
data words residing in the cache. Instruction words are fetched from the
cache as they are needed, but data inadvertently loaded into the cache is ignored and all memory data reads or writes result in accesses of the memory
rather than the cache.
When the cache is disabled, lAO is active high only when the first word of an
instruction is fetched; in the case of a multiple-word instruction, lAO is inactive while the additional words are fetched.

11.5.1 Display Memory Hardware Requirements
The minimum number of bits of memory required to implement the display
memory is the product of the total number of pixels (on-screen and off-screen
areas combined) and the number of bits per pixel. The minimum number of
VRAMs required to contain the display memory is calculated as follows:
N um b er 0 f VRAM s =

(pixels per line) x (lines per frame) x (bits per pixel)
Number of bits per VRAM

This calculation yields the minimum number of VRAMs needed, but additional
VRAMs may be required in some applications. For instance, XV addressing
can be supported by making the number of pixels per line of the display memory a power of two, but this may require more than the minimum number of
VRAMs needed to contain the display.

11-24

Local Memory Interface Bus - Addressing Mechanisms

11.5.2 Memory Organization and Bank Selecting
During a single local memory cycle, one data word (16 bits) is transferred
between the TMS34010 and the selected bank of memory. The memory is
partitioned into a number of banks, where each bank contains the number of
memory devices that can be accessed in a single memory cycle. The number
of devices per bank is therefore determined by dividing the width of the data
bus by the number of data pins per device. The TMS3401 0 data bus is 16 bits
wide, and can access 16 memory data pins during a single cycle. This means,
for example, that a bank composed of 64K-by-1 RAMs contains 16 RAM devices. A bank composed of 64K-by-4 RAMs contains 4 RAM devices.
In a typical system, the local memory is divided into two parts, one consisting
of the display memory and the other consisting of additional DRAMs needed
to store programs and data. This additional RAM can be called the system
memory. A high-order address bit is typically used to select between the display memory and system memory. Within the display memory or system memory, some address bits are provided as the row and column addresses to the
selected bank, while other address bits are used to select one of the banks.
The number of banks of VRAM needed for the display memory is calculated
by dividing the total number of VRAMs by the number of VRAMs per bank.
This in turn determines how many bank select bits must be decoded.

11.5.3 Dynamic RAM Refresh Addresses
DRAMs (and VRAMs) require periodic refreshing to retain their data. The
TMS34010 automatically generates DRAM-refresh cycles at regular intervals.
The interval between refresh cycles is programmable, and DRAM refreshing
can be disabled in systems that do not require it.
The TMS34010 can be configured to generate one of two types of DRAMrefresh cycle timing:
•
•

RAs-only (see Figure 11-7) or
CAS-before-RAS (see Figure 11-8).

During a RAS-only refresh cycle, the TMS34010 provides the 8-bit row address needed to refresh a particular row within each of the DRAMs in the
memory system. DRAMs that support CAS-before-RAS cycles each contain
an on-chip counter which generates the row address needed during the cycle.
In other words, these devices do not rely on the TMS3401 0 to provide the row
address during the CAS-before-RAS cycle.
The row address output by the TMS3401 0 during a DRAM-refresh cycle is the
same regardless of whether the TMS34010 is configured for RAS-only or
CAS-before-RAS refresh timing. Since the TMS34010 outputs a valid row
address during a CAS-before-RAS cycle, a system can contain some DRAMs
that use CAS-before-RAS refresh timing and others that use RAS-only timing.
This hybrid approach configures the TMS34010 to perform CAS-before- RAS
refresh, and relies on external decode logic to prevent the active-low column
address strobe from reaching those DRAMs that require RAS-only refreshing.
The decode logic detects the fact that CAS falls before RAS during a CAS-before-RAS cycle, and uses this to inhibit transmitting the CAS signal to the
RAS-only DRAMs.
11-25

local Memory Interface Bus - Addressing Mechanisms

Several bits in the CONTROL register determine the manner in which the
TMS34010 performs DRAM refreshing. The RM bit selects the type of
DRAM-refresh cycle:
•
•

RM=O selects RAS-only cycles
RM=1 selects CAS-before-RAS cycles

The RR bits determine the interval between DRAM-refresh cycles:
•
•
•
•

RR=002
RR=012
RR=102
RR=112

selects refreshing every 32 local clock periods.
selects refreshing every 64 local clock periods.
is a reserved code.
inhibits DRAM refreshing.

At reset, internal logic forces the RM bit to 0 and the RR field to 002. While
the RESET signal to the TMS34010 is active, no DRAM-refresh cycles are
performed. Following reset, the TMS3401 0 begins to automatically perform
DRAM-refresh cycles at regular intervals.
Both the interval between DRAM-refresh cycles and the addresses output
during the cycles are generated within the REFCNT (DRAM-refresh count)
register. Bits 2-15 of REFCNT form a continuous binary counter. The RINTVL
field occupies bits 2-7, and counts the length of the interval between successive internal requests for DRAM-refresh cycles. The eight MSBs of REFCNT
form the ROWADR field, containing the row address output to memory during
the DRAM-refresh cycle.

11-26

Local Memory Interface Bus - Addressing Mechanisms

GaP

LAD1"
LAD13

FF (DRAM Rafreah
Bus Btatua BIt)
ROWADR8 REFCNT1"
ROWADR6 REFCNT13

LAD12
LAD11

ROWADR"
ROWADR3

LAD10

ROWADR2

LADS

ROWADR1

LAD16

LADS

ROWADRO

LAD7

ROWADR7

LAD8

ROWADR8

LADS

ROWADRS

LAD"
LAD3

ROWADR"
ROWADR3

LAD2

ROWADR2

LAD1

ROWADR1

LADO

ROWADRO

=
=
=REFCNT12. etc.

Example:

LAD2-lAD9 provide 1118
8-b1t row addr_ to a
blook of DRAMa or VRAMI.

Figure 11-19. Row Address for DRAM-Refresh Cycle

During a DRAM-refresh cycle, the S-bit row address in the ROWADR field of
the REFCNT register is output on the LAD pins during the high-to-Iow transition of RAS. As shown in Figure 11-19, the eight bits of ROWADR are output on LADo-LAD7. The seven LSBs of ROWADR are also output on
LADS-LAD14. LAD15 transmits the RF bus status signal, low during the fall
of RAS.
.
Assume that LAD2-LAD9 are used as the S-bit row address by a bank of
DRAMs, as indicated in Figure 11-19.
The address bits output on
LAD2-LAD9 are the same eight bits output on LADo-LAD7, but in a different
order. During a series of 256 DRAM-refresh cycles, the row addresses output
on LADo-LAD7 and LAD2-LAD9 contain the same bits. Thus, if the addresses output on LADo-LAD7 cycle through all 256 row addresses then the
addresses output on LAD2-LAD9 also cycle through all 256 row addresses,
but in a different order.

11-27

Local Memory Interface Bus - Addressing Mechanisms

11.5.4 An Example - Memory Organization and Decoding
As an example, consider a memory organization based on the address decoding scheme shown in Figure 11-20. Three logical address bits (4,21, and 26)
are used as bank-select bits. Logical address bits 5-12 are used as the 8-bit
column address, and bits 13-20 are used as the 8-bit row address. Referring
to Figure 11 -18, the row and column addresses are multiplexed out on the
same eight pins, LAD1-LAD8. The total number of address bits used to address external memory is 19, for a total address reach of one megabyte. The
remaining address bits output by the TMS3401 0 are not used for this example.

987 8
v
8-811: Row
Addr888

Bank

seleot

BIt 2

(882)

v
8-811: Column
Addr888

Bank

Bank
Seleot

BIt 1
(881)

(880)

Select

BIt 0

Figure 11-20. Address Decode for Example System
Bank select bit 2 (BS2) in Figure 11-20 selects between the display memory
(BS2=0) and the system memory (BS2=1). System memory is a block of
conventional DRAM (such as the TMS4256 and TMS4C1 024) used for program and data storage. BS2 becomes valid before RAS falis, and thus can be
used to determine whether the row-address strobe is gated to the display
memory or to the system memory. The average power dissipation is reduced
because only one or the other (the display memory or the system memory) is
enabled during a particular memory read or write cycle.
Figure 11 -21 shows the structure of the display memory. Its dimensions are
1024 by 1 ()24 at four bits per pixel. Bank select bit 1 (BS1) selects between
the top (BS1 =0) and bottom (BS1 =1) halves of the display memory. Since
BS1 becomes valid before the fali of RAS, it can be used to gate RAS to either
the upper or lower half of the display memory during a memory read or write
cycle. By transmitting the row address strobe to only half of the display memory, the power dissipation for the cycle is significantly reduced.
Bank select bit 0 (BSO) selects between the even word and odd word of each
pair of adjacent words in the display memory. Each word contains four adjacent pixels. Odd and even words are stored in two separate banks of VRAMs,
and the decode logic gates the column address strobe to the selected bank
only. The row address strobe is gated to both banks (odd and even words).
This increases the power dissipation over that required if only one bank were
active. A compensating benefit of this organization, however, is that it reduces
the rate at which each VRAM must supply serial data to refresh the screen.
During screen refresh, the bank containing the even words and the bank containing the odd words alternately provide data to the video monitor. Alternating between the two banks in this fashion reduces the data bandwidth

11-28

Local Memory Interface Bus - Addressing Mechanisms

requirements of each bank to about 10M Hz, which is an eighth of the video
bandwidth.
EVen Word
(880 = 0)

(

/\
4

//
..

Odd Word
(880 = 1)

/
I

512 Unea

~r
(BSr 1)

512 Linea

1024 Pixels per Une

~~perBItsPixel

Figure 11-21. Display Memory Dimensions for the Example

The decode logic must be capable of more than just selecting a particular bank
of the display memory or system memory during a memory read or write cycle.
It must also be capable of enabling all DRAMs and VRAMs during a
DRAM-refresh cycle, and enabling all VRAMs during a screen-refresh (memory-to-register) cycle. This means that the decode logic must distinguish
DRAM-refresh and screen-refresh cycles from memory access cycles, and
during a refresh cycle broadcast the row and column address strobes to all
devices that require them. The timing of the RF and TR bus status bits has
been designed to make these signals convenient for the design of the decode
logic.
During a read or write cycle, the value of BS2, output with the row address,
determines whether RAS is gated to the display memory or to system memory.
During a DRAM-refresh cycle, the decode logic must broadcast the rowaddress strobe to all dynamic RAMs (including the VRAMs). The decode
logic must be able to determine prior to the fall of the row address strobe
whether the cycle that is beginning is a DRAM-refresh cycle, or a memory read
or write cycle. This is the reason the TMS34010 outputs the RF bus status
signal prior to the fall of RAS.
The decode logic uses the value of BS1 to determine whether the top or bottom half of the display memory receives an active row-address strobe during
a memory read or write cycle. The same logic must also be capable of broadcasting RAS to all VRAMs during either a DRAM-refresh cycle or a registertransfer cycle.
The decode logic therefore monitors the state of the
TMS34010's TR/QE output prior to the fall of RAS. A low level on TR/QE indicates that the cycle just beginning is a register-transfer cycle, and that RAS
should be broadcast.

11-29

Local Memory Interface Bus - Addressing Mechanisms

While the decode logic uses the value of BSO to determine whether the even
or odd word receives a column-address strobe during a read or write cycle
involving the display memory, the same logic must be capable of broadcasting
CAS to all VRAMs during a screen-refresh cycle. Rather than require an external latch to capture the state of the TR/QE during the fall of RAS, the
TMS34010 outputs the same information a second time in the form of the TR
bus status signal, which is valid prior to and during the fall of CAS.

11-30

Section 12

TMS34010 Instruction Set

This section contains the TMS34010 instruction set (in alphabetical order).
Related subjects, such as addressing modes, are presented first.

Section
Page
12.1 Style and Symbol Conventions .......................................................... 12-2
12.2 Addressing Modes and Operand Formats ........................................ 12-4
12.3 Instruction Set Summary Table ....................................................... 12-12
12.4 Arithmetic, Logical, and Compare Instructions ............................. 12-19
12.5 Move Instructions Summary ............................................................ 12-20
12.6 Graphics Instructions Summary ....................................................... 12-26
12.7 Program Control and Context Switching Instructions ................. 12-29
12.8 Shift Instructions ............................................................................... 12-32
12.9 XY Instructions ................................................................................... 12-33
12.10 Alphabetical Reference of Instructions ........................................... 12-34

12-1

Instruction Set - Style and Symbol Conventions

12.1 Style and Symbol Conventions
Table 12-1 defines symbols and abbreviations that are used throughout this
section; the list following the table describes style conventions used in the
instruction set descriptions. Section 12.2 (page 12-4) defines the symbols
that indicate various addressing modes.
Table 12-1. Instruction Set Symbol and Abbreviation Definitions
Symbol

Symbol

Definition

Source register

Definition

Destination register

RsX

X half of source register

RsY

Y half of source register

RdX
An

X half of destination register
Register n in register file A

RdY

Y half of destination register

Program counter

PC'

Pointer register

PC prime, specifies the address of
the next instruction (current PC +
length of the current instruction)

Status Register

Stack pointer (A15 or B15)

Carry bit

Sign bit

Overflow bit

Zero bit

Global interrupt enable bit

IE
SAddress

Source address

SOffset

Source offset

TOS

Top of stack

DAddress

Destination address

DOffset

Destination offset
Most significant bit

Least significant bit

MSB

MSW

Most significant word

LSW

Least significant word

16-bit immediate value

32-bit immediate value

5-bit constant

Condition code for a jump

Optional field select parameter
for MOVE instructions,
F=O selects FSO/FEO, and
F=1 selects FS1/FE1

Register file select. indicates
which register file (A or B) the
operand registers are in. R=O
specifies register file A, R=1
specifies register file B

LSB

Program listings, coding examples, filenames, and symbol names are shown
in a special font. Some examples and listings use a bold version of
the special font for emphasis. Here is a sample program listing:

0011
0012
0013
0014

00000210
00000212
00000215
00000220

0001
0003
0006

.fie1d
.fie1d
.fie1d
.even

1, 2
3, 4
6, 3

In syntax descriptions, the font indicates which parts of the syntax must
be entered as shown, and which parts act as place holders indicating the type
of information that should be entered. In addition, square brackets identify
optional parameters.
•

12-2

The instruction and any part of the instruction that should be entered as
shown are in a bold face. Parameters that describe the type of information that should be entered are in italics. Here is an example of an
instruction syntax:

Instruction Set - Style and Symbol Conventions

CVXVl Rs, Rd
CVXVl is an instruction that has two parameters, Rs and Rd Rs and Rd
are abbreviations for source register and destination register; when you
use CVXYL, these parameters must be real register names (such as AO,
B1, etc.). Applying these rules, a valid CVXYL instruction is CVXYL AO,
A3.

Another example of an instruction syntax is:

PIXBLT B,XV
In this case, B and XV do not specify values or data; they specify the
type of PIXBLT instruction, and the instruction should be entered as
shown: PIXBLT B,XY.
•

Square brackets ( [ and ] ) identify an optional parameter.
example of an instruction that has an optional parameter:

Here's an

CMPI IW, Rd [, WJ
The CMPI instruction has three parameters. The first two parameters,
IW and Rd, indicate a 16-bit value and a destination register; these parameters are required. The third parameter, W, is optional. As this syntax
shows, if you use the optional third parameter, you must precede it with
a comma.
Each instruction contains an instruction execution field that describes the
actions that occur during instruction execution. These descriptions the following symbols and conventions:
•

The -+ symbol means becomes the contents of. For example, Rs -+ PC
means that the contents of the source register become the contents of
the PC; that is, the contents of the source register are copied into the
PC.

•

The

•

The: symbol indicates concatenation. For example, Rd:Rd+ 1 identifies
the concatenation of two consecutive registers, such as AO and A1.

I I symbols indicate an absolute value.

Numeric constants such as hexadecimal, octal, and binary numbers are
identified by a letter suffix. Valid suffixes include:
•
•
•

b or B (binary)
q or Q (octal)
h or H (hexadecimal)

Decimal constants have no suffix. Note that all constants must start with a
numeral; for example, ABCDh is an illegal constant; OABCDh is the legal form.

12-3

Instruction Set - Addressing Modes

12.2 Addressing Modes and Operand Formats
The TMS34010 instruction set supports eight addressing modes. Most instructions have register-direct operands or a combination of register-direct and
immediate operands; however, the move and graphics instructions use more
complex combinations of operands. This section discusses the TMS34010
addressing modes, and defines the symbols used in instruction syntax to indicate an addressing mode.

12.2.1 Immediate Values and Constants
An instruction syntax may use one of these symbols to indicate an immediate
source operand:
IW is a 16-bit (short) signed immediate value.
IL is a 32-bit (long) signed immediate value.
K
is a 5-bit constant.

Instructions that have immediate source operands have register-direct destination operands. Many instructions that have an immediate value can use either a short or a long value.
Figure 12-1 illustrates a MOVI (move immediate) instruction whose first operand is a 32-bit immediate value. The syntax for this MOVI is:

MOVI IL, Rd {, LJ
The instruction in Figure 12-1 is:

MOVI

OFCOh, A2, L

Figure 12-1 shows the object code (at address N) in memory and the effect
of the instruction on the CPU registers. The value OFCOh is copied into register A2 as a zero-extended 32-bit value. (Note that this is a 2-word instruction; the next instruction to be executed is at address N=2.)
CPU Registers

r - ....

MOV! OFCOOh, A2,L {

N+

I
I

I
\

instruction

.... __

'-'"'"

I
I

09E2h
FCOOh

N+2

•

AI4
80

r--------tI~pTC~4
N

•

PC' =N+2

Figure 12-1. An Example of Immediate Addressing

12-4

Instruction Set - Addressing Modes

12.2.2 Absolute Addresses
An instruction syntax may use one of these symbols to indicate an absolute
operand:
@SAddress is a source address that contains the source data.
@DAddress is a destination address.

Note that the @ character is entered as part of the operand (this distinguishes
it from an immediate operand).
Figure 12-2 illustrates a MOVB (move byte) instruction that has an absolute
operand (the first parameter is a 32-bit source address). The syntax for this
MOVB is:

MOVB @SAddress, Rd
The instruction in Figure 12-2 is:
MOVB

@RoutineA, A13

Figure 12-2 shows the object code (at address N) in memory and the effect
of the instruction on the CPU registers. @RoutineA is the address of a byte;
this MOVB instruction copies the byte at address RoutineA into register A13.
(Note that this is a 3-word instruction; the next instruction to be executed is
at address N=3.)

cpu

Memory

MOVB@RoutineA, A13{ N+

07EDh
RoutineA (MSW)
RoutineA (LSW)
next
instruction

N+2
N+3

RoutineA I'/////~

'-...
I

55h

----_

...

Registers

I
I
I

I A14
I 80
I

A13

I!Ci4

....._ _......;N.:...._ _--'.

PC' = N+3

Figure 12-2. An Example of Absolute Addressing

12-5

Instruction Set - Addressing Modes

12.2.3 Register- Direct Operands
An instruction syntax may use one of these symbols to indicate a registerdirect operand:
Rs
Rd

is a source register that contains the source data.
is a destination register that will contain the result.

When both operands of an instruction are register-direct operands, the registers must be in the same file. (The MOVE RS,Rd instruction is an exception
to this rule.)
Figure 12-3 illustrates a MOVE (move field) instruction that has two register-direct operands. The syntax for this MOVE is:

MOVE Rs, Rd [, F]
The example shows this instruction:

MOVE

AO, Bl

Figure 12-3 shows the object code (at address N) in memory and the effect
of the instruction on the CPU registers. Assume that the field size for the move
is 32 bits; the entire contents of register AD are copied into register B1. (Note
that this is a 1 -word instruction; the next instruction to be executed is at address N=1.)

CPU Registers
FCOOOCOOh

0
AO

Memory
15

MOVE AO, Bl{ N

N+1

I
~

/-~
I

4E01h
next
instruction

'-..,/"

• • • ••

A14
BO
B1

I .

__I
N

IE'

PC'=N+1

Figure 12-3. An Example of Register-Direct Addressing

12-6

Instruction Set - Addressing Modes

12.2.4 Register-Indirect Operands
An instruction syntax may use one of these symbols to indicate a registerindirect operand:

* Rs

* Rd

is a register that contains the address of the source data.
is a register that contains the destination address.

Note that the * character is entered as part of the operand (this distinguishes
it from a register-direct operand).
Figure 12-4 illustrates a MOVE (move field) instruction that has two register-indirect operands. The syntax for this MOVE is:

MOVE

*Rs, *Rd

The example shows this instruction:

MOVE

*A4, *A3

Figure 12-4 shows the object code (at address N) in memory and the effect
of the instruction on the destination address. The contents of register A4
specify the address of data to be moved; the contents of register A3 specify
the destination address. Assume that the field size for the move is 16 bits; the
16 bits of data at * A4 is moved to the location at * A3.. (Note that this is a
1 -word instruction; the next instruction to be executed is at address N=1.)

Memory

MOVE *A4, *A3

,._.....

,
0

",,- .....

aaa3h

CPU Registers

next
instruction

N+1

L-....

I--~'_""')

1
1
1

OOOOAOOOh
oQOOCOaOh

'_ ....1
1
1

A3
A4

1~4

OOOOAOOOh

1.
OOOOC080h

__ I
\.

- ,,"
.....

1~4

PC' =N+1

Figure 12-4. An Example of Register-Indirect Addressing

12-7

Instruction Set - Addressing Modes

12.2.5 Register-Indirect with Offset
An instruction syntax may use one of these symbols to indicate a registerindirect operand that uses a signed offset:
* Rs(offset)
*Rd(offset)

is a source address formed by adding an offset to the contents
of the source register.
is a destination address formed by adding an offset to the
contents of the destination register.

The offset is only used to form an address - the contents of the register are
not affected. Note that the * character is entered as part of the operand. If
both operands use offsets, the syntax may list the operands as * Rs(SOffset)
or *Rd(DOffset).
Figure 12-5 illustrates a MOVE (move field) instruction; the first operand of
this instruction is a register-direct operand; the second operand is a registerindirect operand with an offset. The syntax for this MOVE is:
MOVE

Rs, *Rd(offset) [, F]

The example shows this instruction:

MOVE

B5, *B7(32)

Figure 12-5 shows the object code (at address N) in memory and the effect
of the instruction on the destination location. The destination address is specified by adding the offset (32 bits, which is equivalent to 2 words) to the
contents of register B7; this yields a destination location of 05020h. Assume
that the field size for the move is 16 bits; the 16 LSBs in register B5 are copied
into the destination location. (Note that this is a 2-word instruction; the next
instruction to be executed is at address N=2.)
Memory

15 ;/~1-,

31
MOVEB5,*B7 ( 2),1{

N+ 1

BOB7h
0020h

N+2

next
instruction

I
'-v-'

00005000h
+20h

~--------------~1:~4

I
.:

,_....

... -_1
/

o
1.

00005020h

Registers

I------~IA~

'-.. .1

I
I
I

CPU

1:
1234ABCDh

r--

B5
B6

0OOO5000h

~~4
1
~======:N:======jpc
SP

PC'=N+2

Figure 12-5. An Example of Register-Indirect with Offset
Addressing

12-8

Instruction Set - Addressing Modes

12.2.6 Register-Indirect with Postincrement
An instruction syntax may use one of these symbols to indicate a registerindirect operand that is postincremented:

* Rs+ is a register that contains the address of the source data.
*Rd+ is a register that contains the destination address.
After the operation is performed, the contents of the specified source or destination register are incremented by the field size used for the operation.

Note that the

and + characters are entered as part of the operand.

Figure 12-6 illustrates a MOVE (move field) instruction; both the source and
the destination operands are postincremented register-indirect operands. The
syntax for this MOVE is:

MOVE

*Rs+, *Rd+ [. FJ

The example shows this instruction:
MOVE

*B4+ I

*B14+

Figure 12-6 shows the object code (at address N) in memory and the effect
of the instruction on the destination location and the CPU registers. The
contents of register B4 are the address of the source data; the contents of register B14 specify the destination address. Assume that the field size for the
move is 16 bits; the 16 bits of data at the source address are copied into the
destination location. After the move, both registers are incremented by 16 bits
(1 word). (Note that this is a 1-word instruction; the next instruction to be
executed is at address N=1.)
Memory

MOVE *B4+ ,*B14+

_)0
31

1--

I .

instruction

Lo_...

r-...~'_.)
I

I---------il A~

989Eh
next

N+1

CPU Registers

'-""'1I

I
00001020h~I~~~~
I
I

C0000200h"IIIm"~~

~------------~1:~4
~..::O:...:O::..;O:::.:::.O..:.1..::0;.:2:...;0::..h:.:.-~184.

O~
-FiEEE'S"
••"
::.".,
After Move

I .
~-=0-:::C-::0'-;:0""'0:-:0""2::-0::-::-0':""h--f 814 + 10~.+"';;;;".M

~------------~ SP
ST

~-----:N"..-------f PC PC'

::.".,

After Move

= N+ 1

Figure 12-6. An Example of Register-Indirect with Postincrement
Addressing

12-9

Instruction Set - Addressing Modes

12.2.7 Register-Indirect with Predecrement
An instruction syntax may use one of these symbols to indicate a registerindirect operand that is predecremented.
Before the operation is performed, the contents of the specified source or
destination register are decremented by the field size used for the operation.

* -Rs
* -Rd

the decremented register contents are the address of the source data.
the decremented register contents specify the destination address.

Note that the

* and

- characters are entered as part of the operand.

Figure 12-7 illustrates a MOVE (move field) instruction; the source operand
is a register-direct operand the the destination operand is a predecremented
register-indirect operand. The syntax for this MOVE is:

MOVE Rs, *-Rd [, FJ
The example shows this instruction:

MOVE

A4, *-A3

Figure 12-7 shows the object code (at address N) in memory and the effect
of the instruction on the destination location and the CPU registers. Assume
that the field size for the move is 16 bits. Register A4 contains the source data.
The contents of register A3, minus the field size (16 bits, or 1 word) form the
destination address - 5150h. The 16 LSBs in A4 are copied to address 5150h.
(Note that this is a 1 -word instruction; the next instruction to be executed is
at address N=1.)

Memory

MOVE A4, *A3

1~_ ....."'"
N

o
31

AOS3h

N+ 1

next
instruction

~::~,~

00OO5150h

'-"'1

,,_ .../ . . .

r"",

--::O~O:-:O~O;:-::-5":"1"::'a-:::O-:"h--'

I---'::":-Se';fo"::re"::-:M:";ov::"e;::"':':'--J

CPU Registers

• •~

- 1Oh

--I[::A S C02 2 2 2

I
I
I

••,.
~

~!8".".j

A3
A4

1:~4
I .
IS;4

N~~

PC'=N+1

Figure 12-7. An Example of Register-Indirect with Predecrement
Addressing

12-10

Instruction Set - Addressing Modes

12.2.8 Register-Indirect in XV Mode
An instruction syntax may use one of these symbols to indicate that the a register operands contains an XV address.
*Rs.XV is a register that contains the XV address of the source data.
* Rd.XV is a register that contains the XV destination address.
Note that the * and .XV characters are entered as part of the operand. Here's
an example that uses an indirect-XV destination operand:

PIXT

AD, *A6.XY

This instruction moves the contents of register AO into the XV address specified by the contents of register A6.

12-11

Instruction Set - Summary Table

12.3 Instruction Set Summary Table
Arithmetic, Logical, and Compare Instructions
Words

Machine
States

ABSRd
Store absolute value
ADDRs, Rd
Add registers

1,4

0000 0011

1,4

0100 0005 SSSR DODD

ADDCRs, Rd
Add registers with carry
ADDI/W, Rd
Add immediate (16 bits)

1,4

0100 001S SSSR DODD

2,8

0000 1011

OOOR DODD

ADDIIL, Rd
Add immediate (32 bits)

3,12

0000 1011

001R DODD

ADDKK, Rd
Add constant (5 bits)
ADDXY Rs, Rd
Add registers in XV mode

1,4

0001

1,4

1110 0005 SSSR DODD

AND Rs, Rd
AND registers

1,4

0101

ANDIIL, Rd
AND immediate (32 bits)

3,12

0000 1011

ANDN Rs, Rd
AND register with complement

1,4

0101

ANDNIIL, Rd
AND not immediate (32 bits)

3,12

0000 1011

BTSTK, Rd
Test register bit, constant
BTST Rs, Rd
Test register bit. register

1,4

0001

2,5

0100 101 S SSSR DODD

CLR Rd
Clear register

1,4

0101

CLRC
Clear carry

1,4

0000 0011

CMP Rs, Rd
Compare registers

1,4

0100 100S SSSR DODD

CMPI/W, Rd
Compare immediate (16 bits)

2,8

0000 1011

010R DODD

CMPIIL, Rd
Compare immediate (32 bits)

3,12

0000 1011

011 R DODD

CMPXY Rs, Rd
Compare X and V halves of registers

3,6

1110 010S SSSR DODD

DECRd
Decrement register

1,4

0001

Syntax and Description

12-12

16- Bit Opcode
MSB

LSB
100R DODD

OOKK KKKR DODD

OOOS SSSR DODD
100R DODD

0015 SSSR DODD
100R DODD

11 KK KKKR DODD

0110 DOOR DODD
0010 0000

0100 001R DODD

Instruction Set - Summary Table

Arithmetic. Logical. and Compare Instructions (Continued)
Syntax and Description

Words

Machine
States

16-Bit Opcode
MSB

LSB

DIVS Rs. Rd
Divide registers signed

40.43 Il 0101
39.42

100S SSSR DODD

DIVU Rs. Rd
Divide registers unsigned

37.40

101S SSSR DODD

LMO Rs. Rd
Leftmost one

1.4

0110 101 S SSSR DODD

MODS Rs. Rd
Modulus signed

40.43

0110 110S SSSR DODD

MODU Rs. Rd
Modulus unsigned

35,38

0110 111 S SSSR DODD

MPYS Rs, Rd
Multiply registers (signed)

20,23

0101

110S SSSR DODD

MPYU Rs, Rd
Multiply registers (unsigned)

21,24

0101

111 S SSSR DODD

NEGRd
Negate register

1.4

0000 0011

101R DODD

NEGB Rd
Negate register with borrow

1.4

0000 0011

110R DODD

NOTRd
Complement register

1,4

0000 0011

111 R DODD

OR Rs. Rd
OR registers

1.4

0101

ORIIL. Rd
OR immediate (32 bits)

3,12

0000 1011

101R DODD

SETC
Set carry

1.4

0000 11 01

1110 0000

SEXT Rd. F
Sign extend to long

3,6

0000 01 F1

OOOR DODD

SUB Rs, Rd
Subtract registers

1.4

0100 010S SSSR DODD

SUBB Rs, Rd
Subtract registers with borrow

1.4

0100 011 S SSSR DODD

SUBIIW, Rd
Subtract immediate (16 bits)

2,8

0000 1011

111 R DODD

SUBIIL, Rd
Subtract immediate (32 bits)

3,12

0000 1101

OOOR DODD

SUBKK, Rd
Subtract constant (5 bits)

1.4

0001

SUBXY Rs, Rd
Subtract registers in XY mode

1.4

1110 001S SSSR DODD

XOR Rs. Rd
Exclusive 0 R registers

1,4

0101

XORIIL, Rd
Exclusive OR immediate value (32 bits)

3,12

0000 1011

1100 DODD

ZEXT Rd, F
Zero extend to long

1,4

0000 01 F1

001R DODD

0101

010S SSSR DODD

01KK KKKR DODD

011 S SSSR DODD

Il Rd even/Rd odd
12-13

Instruction Set - Summary Table

Move Instructions
16-Bit Opcode

Words

Machine
States

MMFM Rs {. List]
Move multiple registers from memory

0000 1001

101 R

DODD

MMTM Rs (. List]
Move multiple registers to memory

0000 1001

100R

DODD

MOVBRs. *Rd
Move byte. register to indirect

1000 110S SSSR

DODD

MOVB *Rs. Rd
Move byte. indirect to register

1000 111 S SSSR

DODD

MOVB Rs. Rd
Move byte. indirect to indirect

1001

110S SSSR

DODD

MOVB Rs. *Rd(offset)
Move byte. register to indirect with offset

1010 110S SSSR

DODD

MOVB *Rs(offset). Rd
Move byte. indirect with offset to register

1010 111 S SSSR

DODD

MOVB *Rs(SOffset). *Rd(DOffset)
Move byte. indirect with offset to
indirect with offset

1011

DODD

MOVB Rs. @DAddress
Move byte. register to absolute

0000 0101

111 R SSSS

MOVB @SAddress. Rd
Move byte. absolute to register

0000 0111

111 R

MOVB @SAddress. @DAddress
Move byte. absolute to absolute

0000 0011

0100 0000

MOVERs. Rd
Move register to register

1,4

0100 11MS SSSR

DODD

1000 OOFS SSSR

DODD

1010 OOFS SSSR

DODD

MOVE Rs. Rd+ [. F]
Move field. register to indirect (postincrement)

1001

OOFS SSSR

DODD

MOVE *Rs. Rd [. F]
Move field. indirect to register

1000 01FS SSSR

DODD

MOVE -*Rs. Rd [. F]
Move field. indirect (predecrement) to register

1010 01FS SSSR

DODD

MOVE *Rs+. Rd {. F]
Move field. indirect (postincrement) to register

1001

DODD

Syntax and Description

MOVE Rs. Rd [. F]
Move field. register to indirect

MOVE Rs. - Rd [. F]
Move field. register to indirect (predecrement)

t See instruction
1T See Section 13.2. MOVE and MOVB Instructions Timing

12-14

MSB

LSB

110S SSSR

01FS SSSR

DODD

Instruction Set - Summary Table

Move Instructions (Continued)

Words

Machine
States

MOVE * Rs, * Rd [. FJ
Move field, indirect to indirect

1000 10FS SSSR DODD

MOVE -*Rs, -*Rd [, FJ
Move field, indirect (predecrement) to
indirect (predecrement)

1010 10FS SSSR DODD

MOVE *Rs+, *Rd+ [. FJ
Move field, indirect (postincrement) to
indirect (postincrement)

1001

10FS SSSR DODD

MOVE Rs, *Rd(offset) [. FJ
Move field, register to indirect with offset

1011

OaFS SSSR DODD

MOVE *Rs(offset), Rd [. FJ
Move field, indirect with offset to register

1011

01FS SSSR DODD

MOVE *Rs(offset), *Rd+ [. FJ
Move field, indirect with offset to
indirect (postincrement)

1101

OOFS SSSR DODD

MOVE * Rs(SOffset), * Rd(DOffset) [. FJ
Move field, indirect with offset to
indirect with offset

1011

10FS SSSR DODD

MOVE Rs, @DAddress [. FJ
Move field, register to absolute

0000 01 F1

100R SSSS

MOVE @SAddress, Rd [. FJ
Move field, absolute to register

0000 01 F1

101R DODD

MOVE @SAddress, * Rd+ [. FJ
Move field, absolute to indirect (postincrement

1101

MOVE @SAddress, @DAddress [. FJ
Move field, absolute to absolute

0000 01 F1

1100 0000

MOVI/W, Rd
Move immediate (16 bits)

2,8

0000 1001

110R DODD

MOVIIL, Rd
Move immediate (32 bits)

3,12

0000 1001

111 R DODD

MOVKK. Rd
Move constant (5 bits)

1.4

0001

MOVXRs, Rd
Move X half of register

1.4

1110 11 as SSSR DODD

MOVY Rs, Rd
Move Y half of register

1.4

111 0 111 S SSSR DODD

Syntax and Description

16- Bit Opcode
MSB

LSB

01FO OOOR DODD

10KK KKKR DODD

See instruction

~ See Section 13.2, MOVE and MOVB Instructions Timing

12-15

Instruction Set - Summary Table

Graphics Instructions
Words

Machine
States

1.4

1110 011S SSSR DODD

CVXVLRs, Rd
Convert XV address to linear address

3,6

1110 100S SSSR DODD

DRAV Rs, Rd
Draw and advance

1111

FILL L
Fill array with processed pixels, linear

:I:

0000 1111

FILL XV
Fill array with processed pixels. XV

:I:

0000 111 1 1110 0000

LINE [0.1J
Line draw

1101

PIXBLT B. L
Pixel block transfer. binary to linear

:1::1:

0000 1111

1000 0000

PIXBLT B, XV
Pixel block transfer and expand. binary to XV

:1::1:

0000 1111

1010 0000

PIXBLT L, L
Pixel block transfer. linear to linear

0000 111 1 0000 0000

PIXBLT L. XV
Pixel block transfer. linear to XV

0000 1111

0010 0000

PIXBLT XV. L
Pixel block transfer. XV to linear

0000 1111

0100 0000

PIXBLT XV. XV
Pixel block transfer. XV to XV

0000 1111

0110 0000

PIXT Rs, *Rd
Pixel transfer. register to indirect

1111

100S SSSR DODD

PIXT Rs, * Rd.XY
Pixel transfer. register to indirect XV

1111

OOOS SSSR DODD

PIXT *Rs. Rd
Pixel transfer. indirect to register

1111

101S SSSR DODD

PIXT * Rs, * Rd
Pixel transfer. indirect to indirect

1111

110S SSSR DODD

PIXT * Rs.XY, Rd
Pixel transfer. indirect XV to register

1111

001S SSSR DODD

PIXT * Rs.XY. * Rd.XY
Pixel transfer. indirect XV to indirect XV

1111

010S SSSR DODD

Syntax and Description

CPWRs, Rd

16-Bit Opcode
MSB

LSB

Compare point to window

See
See
t+ See
§ See

t
t

12-16

instructIOn
Section 13.3. FI LL Instructions Timing
Section 13.5. PIXBLT Expand Instructions Timing
Section 13.4. PIXBLT Instructions Timing

011S SSSR DODD

1111

1100 0000

Z001

1010

Instruction Set - Summary Table

Program Control and Context Switching Instructions
Syntax and Description

Words

Machine
16-Bit Opcode
States
MSB
LSB
3+(3),9
0000 1001 001R DODD
3+(9),158

CALLRs
Call subroutine indirect

CALLA Address
Call subroutine address

4+(2),158 0000 1101 0101
4+(8),21 -

1111

CALLR Address
Call subroutine relative

3+(2),11 8 0000 1101 0011
3+(8),17-

1111

DINT
Disable interrupts

3,6

0000 0011

0110 0000

EINT
Enable interrupts

3,6

0000 1101

0110 0000

EMU
Initiate emulation

6,9

0000 0001

0000 0000

EXGF Rd, F
Exchange field size

1.4

1101

01 F1

OOOR DODD

EXGPC Rd
Exchange program counter with register

2,5

0000 0001

001R DODD

GETPC Rd
Get program counter into register

1.4

0000 0001

010R DODD

GETST Rd
Get status register into register

1.4

0000 0001

100R DODD

NOP
No operation

1.4

0000 0011

0000 0000

POPST
Pop status register from stack

8,11
0000 0001
10,138

1100 0000

PUSHST
Push status register onto stack

1110 0000

PUTST Rs
Copy register into status

2+(3),8
0000 0001
2+(8),138
3,6
0000 0001

RETI
Return from interrupt

11,1~ 0000 1001

0100 0000

RETS [N]
Return from subroutine

7,1~ 0000 1001
9,1

011 N NNNN

REVRd
Find TMS3401 0 revision level

1.4

SETF FS, FE, F
Set field parameters

1.4
2,5

101 R DODD

15,1

1
TRAPN
Software interrupt
t See instruction
8 First values for SP aligned, second values for SP nonaligned

0000 0000 001R DODD
0000 01 F1

01FS SSSS

16,198 0000 1001
30,33-

OOON NNNN

:j:

12-17

Instruction Set - Summary Table

Jump Instructions

Syntax ,and Description

Words

Machine
States

16-Bit Opcode
MSB

LSB

DSJ Rd, Address
Decrement register and skip jump

3,9
2,8

0000 11 01

100R DDDD

DSJEQ Rd, Address
Conditionally decrement register and
skip jump

3,9
2,8

0000 1101

101 R DDDD

DSJNE Rd, Address
Conditionally decrement register and
skip jump

3,9
2,8

0000 1101

110 R DDDD

DSJS Rd, Address
Decrement register and skip jump short

2,5
3,6

0011

JAcc Address
Jump absolute conditional

3,6
4,7

1100 code

1000 0000

JRcc Address
Jump relative conditional

3,6
1,4

1100 code

0000 0000

JRcc Address
Jump relative conditional short

2,5
2,5

1100 code

xxxx xxxx

JUMP Rs
Jump indirect

2,5

0000 0001

011R DDDD

1 Dxx xxx R DDDD

Shift Instructions

Syntax and Description

Words

Machine
16-Bit Opcode
States
MSB
LSB
'0011 OOKK KKKR DDDD
1,4

RLK, Rd
Rotate left, constant

RLRs, Rd
Rotate left. register

1,4

0110 1005 SSSR DDDD

SLAK. Rd
Shift left arithmetic, constant

3,6

0010 OOKK KKKR DDDD

SLARs. Rd
Shift left arithmetic, register

3,6

0110 0005 SSSR DDDD

SLLK. Rd
Shift left logical, constant

1,4

0010 01KK KKKR DDDD

SLLRs. Rd
Shift left logical, register

1,4

0110 0015 SSSR DDDD

SRAK, Rd
Shift right arithmetic, constant

1,4

0010 10KK KKKR DDDD

SRARs. Rd
Shift right arithmetic, register

1,4

0110 0105 SSSR DDDD

SRLK. Rd
Shift right logical, constant

1,4

0010 11 KK KKKR DDDD

SRLRs, Rd
Shift right logical, register

1,4

0110 0115 SSSR DDDD

First values for Jump, second values for no Jump

12-18

Instruction Set - Arithmetic, Logical, and Compare Instructions

12.4 Arithmetic, Logical. and Compare Instructions
The TMS3401 0 supports a full range of arithmetic, logical, and compare instructions. Most of these instructions use register-direct operands; some use
a combination of immediate and register-direct operands. Some instructions
have several versions; each uses a different operand format. For example, the
ADD instruction has several versions:
•

The ADD instruction uses register-direct operands for both the source
and destination operands.

•

The ADDI instruction uses an immediate source with a destination register.

•

The ADDK instruction uses a 5-bit constant as the source operand with
a destination register.

•

The ADDXY instruction is similar to the ADD instruction - both operands are register-direct operands - however, the registers contain XV
values.

Some instructions that have immediate values as source operands (such as the
ADDI instruction) have two forms: a short form and a long form. In the short
form, the source operand is a 16-bit immediate value and the instruction occupies two words. In the long form, the source operand is a 32-bit immediate
value and the instruction occupies three words. Each form of the instruction
has an optional third operand: W for short and L for long. If you don't use the
W or L operand, the assembler chooses the short or the long form, depending
on the size of the source operand. Using W or L forces the assembler to use
the short or long form, respectively. If you use Wand the source value is
greater than 16 bits, the assembler discards all but the 16 LSBs and issues a
warning message. If you use L and the source value is less than 32 bits, the
assembler sign-extends the value to 32 bits.
Some instructions that use immediate operands have only one version. In this
case, the operand is long (32-bits).

Note:
When an instruction's source and destination operands are both register-direct operands, the registers must be in the same file. (The MOVE
Rs, Rd instruction is an exception to this rule.)

12-19

Instruction Set - Move Instructions

12.5 Move Instructions Summary
The TMS3401 0 supports a variety of move instructions, allowing you to move
immediate values into registers, move data between registers, and move data
between registers and memory. Table 12-2 summarizes the various types of
move instructions.

Table 12-2. Summary of Move Instructions
Move Type

Mnemonic

Description

MOVE

Move register to register

Constant

MOVK

Move constant (5 bits)

MOVI

Move immediate (16 bits)

MOVI

Move immediate (32 bits)

MOVX

Move 16 LSBs of register (X half)

MOVY

Move 16 MS Bs of register (Y half)

Multiple register

MMFM

Move multiple registers from memory

MMTM

Move multiple registers to memory

Byte

MOVB

Move byte (8 bits, 9 addressing modes)

Field

MOVE

Move field to/from memory/register
(15 addressing modes)

12.5.1 Register-to-Register Moves
The MOVE RS,Rd instruction is a register-to-register move; it moves a full 32
bits of data between any two general-purpose registers. This is the only

MOVE instruction that allows you to move data between register files A and

12.5.2 Value-to-Register Moves
The MOVI and MOVK instructions move immediate values into registers.
MOVK moves a zero-extended value into a register; the value must be in the
range of 1 to 32. The MOVI instruction has two forms; it can move a 16-bit
or a 32-bit immediate value.

12.5.3 XV Moves
The MOVX and MOVV instructions move values into the 16 LSBs or 16
MSBs, respectively, of a register.

12-20

Instruction Set - Move Instructions

12.5.4 Multiple-Register Moves
The MMTM and MMFM instructions use register-direct operands. MMTM
allows you.to save several register values in memory; MMFM allows you to
retrieve register values from memory. Both instructions have two types of
operands:
•

The Rp operand is a register pointer. For the MMTM instruction, Rp
contains the memory address where MMTM stores the register values.
For the MMFM instruction, Rp contains the memory address from which
MMFM loads the stored register values.

•

The register list operand is an optional list of registers. It specifies which
registers are stored or retrieved, and also indicates the storing or retrieval
order.

Note that Rp and all the registers in the list must be in the same register file.

12.5.5 Byte Moves
The MOVB instruction is a special form of the MOVE instruction; when you
use MOVB, the field size is restricted to 8 bits. MOVB supports nine combinations of operand formats. There are three basic combinations:
•
•
•

Register to memory (requires a field insertion),
Memory to register (requires a field extraction), and
Memory to memory (requires both field insertion and extraction).

Note that the MOVB instruction does not move data between registers.
The MOVB instruction allows a byte to begin on any bit boundary in memory.
The byte's memory address points to the LSB of the byte. When a byte is
moved into a register, the byte's LSB coincides with the register's LSB; the
byte is sign-extended into the 24 MSBs of the register.
Table 12-3 lists the valid combinations of operand formats for the MOVB instruction.
Table 12-3. Summary of Operand Formats for the MOVB
Instruction
Destination
Source

Rs
*Rs
* Rs(SOffset)
@SAddress

J
J
J

*Rd

* Rd(DOffset

@DAddress

J
J

Sequences of byte moves are more efficient if the byte addresses are aligned
on even 8-bit boundaries. Twice as many memory cycles are required to access a byte that straddles a word boundary.

12-21

Instruction Set - Move Instructions

12.5.6 Field Moves
The MOVE instruction supports eighteen combinations of operand formats.
There are four basic combinations:
•
•
•
•

The MOVE instruction moves a field. A field is a configurable data structure
that is identified by its starting address and its length. Field lengths can range
from 1 to 32 bits. A field's memory address points to the LSB of the field; the
field occupies contiguous bits. A field in a register is right-justified within the
register; the field's LSB coincides with the register's LSB.
Note that all forms of the MOVE instruction have an optional F parameter.
(MOVE RS,Rd is an exception to this; it doesn't have an F parameter because
it always moves 32 bits.) F selects the field size and field extension for the
MOVE:
•

If F=O, FSO and FEO determine the field size and extension.

•

If F=1, FS1 and FE1 determine the field size and extension.

If you don't specify 0 or 1, 0 is used as the default. The selected field size
determines the size of the field that is moved. A moved field is either signextended or zero-extended, depending on the value of the appropriate field
extension bit. You can use the SETF instruction to set the field size and extension.
Table 12-4 summarizes the valid combinations of operand formats for the
MOVE instruction.
Table 12-4. Summary of Operand Formats for the MOVE Instruction
Destination
Source

Rs
*Rs
*Rs+
-*Rs
* Rs(SOffset)
@SAddress

12-22

*Rd

*Rd+

-*Rd

* Rd(DOffset

@DAddress

.J
.J
.J
.J
.J
.J

.J
.J

.J
.J
.J
.J

.J
.J

Instruction Set - Move Instructions

12.5.6.1 Register-to-Memory Field Moves
Figure 12-8 illustrates the register-to-memory move operation. In this type
of move, the source register contains the right-justified field data (width is
specified by the field size). The destination location is the bit position pointed
to by the destination memory address. The address consists of a portion defining the starting word in which the field is to be written and an offset into
that word, the bit address. Depending on the bit address within this word and
the field size, the destination location may extend into two or more words.
Move from Register to Memory

31
Destination Memory Addreaa

4 3

L.1_ _ _ _ _ _w_O_rd_Ad_dr_eaa
______

31
Source Register

~I..lAd~rlUreaa=_......1
0

ReldData~

~ReldSlz~

--+~ \ j::-\

Delltlnatlon Memory Location

~
~

0116

Reld:oata

r-Aeld Size
Reid Size

= 1 to

.~
32 bits

Figure 12-8. Register-to-Memory Moves

12-23

Instruction Set - Move Instructions

12.5.6.2 Memory-to-Register Field Moves
Figure 12-9 shows the memory-to-register move operation. The source memory location is the bit position pointed to by the source address. The address
consists of a portion defining the starting word in which the field is to be
written and an offset into that word, the bit address. Depending on the bit
address Within this word and the field size, the source location may extend
into two or more words. After the move, the destination register LSBs contain
the right-justified field data (width is specified by the field size). The MSBs
of the register contain either all 1 s or all Os.
Move from Memory to Register

souroe Memory Adc:Ir_

1..______w_o_rcl_Acl_d_r_ _ _ _ _ _ _IL....iAcl:;:c:ll1.l~=_...1

SCwoe Memory Location

0
FIeld Data

DestInation Reglater, FE=O

SljBIt

31
Dutlnatlon Register, FE=1

SIgn BIt
FIeld IIze

= 1 to

32 bits

Figure 12-9. Memory-to-Register Moves

12-24

0
FIeld Data

Instruction Set - Move Instructions

12.5.6.3 MemorY-fo-Memory Field Moves
Figure 12-10 shows a memory-to-memory field move operation. The source
memory location is the bit position pointed to by the source address. The
destination location is the bit position pointed to by the destination memory
address. Depending on the bit addresses within the respective words and the
field size, either the source location or destination locations may extend into
two or more words. After the move, the destination location contains the field
data from the source memory location.
Move from Memory to Memory

SOurce Memory Acldr_

SOurce Memory LcclUon

31
DestlnlUon Memcry Acldr_
Word Acldr_ 8+18

Word AcIdr_ B ' \

15
DeatlnlUcn Memory LcclUon
~oI+-_ _ DeaunlUon

BIt Acldr_

Field IIze

= 1 tc

---tI

32 bits

Figure 12-10. Memory-to-Memory Moves

12-25

Instruction Set - Graphics Instructions

12.6 Graphics Instructions Summary
The TMS3401 0 instruction set supports several fundamental graphics drawing
operations.

12.6.1 Comparing a Point to a Window
The CPW instruction compares a point to the window limits defined by the
WSTART and WEND registers. The source operand Rs contains an XY address. After the compare operation is performed, bits 5-8 contain a code that
indicate the point's location with respect to the window limits. The description of the CPW instruction shows these point codes.

12.6.2 Converting an XV Address to a Linear Address
The CVXVL instruction converts an XY address to a 32-bit linear address. The
source register contains the XY address; the linear address is put in the destination register.

12.6.3 Drawing a Pixel and Advancing to the Next Pixel Address
The DRAV instruction draws the pixel value in the COLOR1 register to the
XY address specified by the destination register. After the pixel is drawn, the
Y half of Rs is added to the Y half of Rd, and the X half of Rs is added to the
X half of Rd.

12.6.4 Draw a Line
The LINE instruction performs the inner loop of Bresenham's line-drawing
algorithm to draw an arbitrarily oriented, straight line. The optional operand
may be a 0 or a 1; this selects one of two algorithms. The default for this operand is O.

12.6.5 Filling a Pixel Block
The FILL instruction fills a two-dimensional pixel array with the value in the
COLOR1 register. Note that L and XV are not actually operands; they are part
of the instruction mnemonic, identifying the form of the FILL instruction. FILL
L specifies that the array has a linear starting address; FILL XY specifies that
the array has an XY starting address.

12-26

Instruction Set - Graphics Instructions

12.6.6 Moving a Single Pixel
The PIXT instruction transfers a pixel from one location to another. PIXT can
transfer a pixel:
•
•
•

From a register to memory,
From memory to a register, or
From memory to memory.

Table 12-5 summarizes the valid combinations of operand formats for the PIXT
instruction. Note that all addresses are linear unless the operand is suffixed
with .XV.
Table 12-5. Summary of Operand Formats for the PIXT Instruction
Destination Pixel
Source
Pixel

Rs
*Rs
*Rs.XY

..j
..j

*Rd

*Rd.XY

..j
..j

12.6.7 Moving a Two-Dimensional Block of Pixels
The PIXBlT instruction moves a two-dimensional block of pixels from one
memory location to another. Note that B, l, and XV are not actually
operands; instead, they identify the source or destination array starting addresses as binary, linear, or XV addresses. The source and destination addresses of the arrays are designated by the SADDR and DADDR registers,
respectively.
Table 12-6 summarizes the various combinations of pixel block transfers.
Table 12-6. Summary of Array Types for the PIXBlT Instruction

Destination Array
Source
Array

Linear

Binary

..j
..j
..j

Linear

The graphics instructions use the B-file registers and several I/O registers as
implied operands. These registers must be loaded with appropriate values
before the instruction is executed. The TMS3401 0 obtains information from
these registers during instruction execution. Table 12-7 summarizes the implied operands that are used by the graphics instructions. The TMS34010
User's Guide contains a complete discussion of these registers and describes
the types of information they should contain.

12-27

Instruction Set - Graphics Instructions

12.6.8 Implied Operands
The graphics instructions require additional information that you supply by
loading appropriate values into specific B registers and I/O registers. When
these registers are used for this purpose, they are called implied operands.
Section 5 discusses the functions of B registers as implied operands; Section
5 discusses the functions of I/O registers as implied operands.
Note that the LINE instruction uses registers B1 0-813 as implied operands;
as implied operands, these registers have the following functions:
B10: COUNT register
B11: INC1 register

B12: INC2 register
B13: PATTRN register

Table 12-7 identifies the implied operands that each graphics instruction uses.
Table 12-7. Implied Operands Used by Graphics Instructions

~:
,::c,:,:,:,:,:;:, Changed

by instruction execution
Used; no particular format
XY Register is in XY format
L
Register is in linear format
P
Register is in pixel format
pat Register is in pattern format

12-28

(1)
(2)
(3)
(4)
(5)

Changed as a result of common rectangle function with window hit operation (W=1)
CONTROL bits used: pp, W, T
CONTROL bits used: PP, T
CONTROL bits used: PP, W, T, PBH, PBV
CONTROL bits used: PP, T, PBH, PBV
Used when PBV=1

Instruction Set - Program Control and Context Switching Instructions

12.7 Program Control and Context Switching Instructions
The TMS34010 supports a variety of instructions that allow you to control
program flow and to save and restore information by letting you:
•
•
•
•
•

Call and return from subroutines,
Enable or disable interrupts,
Set software interrupts,
Set, save, or restore status information, and
Use jump instructions to redirect program flow.

Most of these instructions use register-direct or absolute operands; however,
several of them have no operands.

12.7.1 Subroutine Calls and Returns
The TMS3401 0 allows you to call a subroutine in three ways:
•
•
•

Indirectly, by loading an address into a register;
Directly, by using an absolute address; and
Relatively, by specifying an address that is an offset.

These CALL instructions automatically save status information on the stack.
The RETS (return from subroutine) instruction pops status information off of
the stack and returns control to the program or routine that called the subroutine.

12.7.2 Interrupt Handling
The TMS3401 O's EI NT and 01 NT instructions allow you to enable or disable
hardware interrupts by providing control of the IE (global interrupt enable)
status bit. The TMS3401 0 also supports a TRAP instruction that provides you
with control over 32 software interrupts.

12.7.3 Setting, Saving, and Restoring Status Information
Although some instructions automatically save or restore status information,
you will often want explicit control over these functions. The TMS34010
supports several instructions that allow you to save and restore PC and ST
information. The TMS3401 0 also supports a SETF instruction that allows you
to set field-0/field-1 information in the status register.

12-29

Instruction Set - Program Control and Context Switching Instructions

12.7.4 Jump Instructions
The TMS34010 supports both conditional and unconditional jumps. The
conditional jumps use absolute operands or a combination of register-direct
and absolute operands.
•

There are four DSJ instructions:
DSJ and DSJS decrement the contents of a register and jump to
the specified address if the new contents of Rd do not equal 0. If
Rd is decremented to 0, then execution continues with the next
instruction.
DSJ provides a jump range of -32,768 to +32,767 words; DSJS
provides a jump range of ±32 words (excluding O).
The operation of DSJ EO and DSJ N E depends on the value of the
Z (zero) status bit.
DSJEO decrements the contents of Rd when Z=1 and jumps to
the specified address if the new contents of Rd do not equal 0. If
Rd is decremented to 0, then execution continues with the next
instruction. If Z=O, DSJEQ skips the jump and execution continues with the next instruction.
DSJNE decrements the contents of Rd when Z=O and jumps to
the specified address if the new contents of Rd do not equal 0. If
Rd is decremented to 0, then execution continues with the next
instruction. If Z=O, DSJNE skips the jump and execution continues with the next instruction.
The address specified for the DSJ instructions is relative; the assembler
uses this address automatically to calculate a displacement, and then it
inserts the displacement into the instruction.

•

The JUMP instruction is unconditional.
the address for the jump.

The source register contains

•

The conditional jump instructions, JAec and J Ree, use the condition
codes listed Table 12-8.
The J Ree instruction has a long and a short form. The short form supports a jump range of ±127 words (excluding O). The long form supports a jump range of ±32K words (excluding O).

The 32-bit address specified for the JAee instruction is absolute; the assembler
inserts this address into words 2 and 3 of the instruction. The address specified for the J Ree instructions is relative; the assembler uses this address automatically to calculate a displacement, and then it inserts the displacement into
the instruction. The short form has an 8-bit displacement that is inserted into
bits 0-7 of the opcode; the opcode is 1 word long. The long form has 16-bit
displacement; the opcode is 2 words long, and the displacement occupies the
entire 16 bits of the second word.
Table 12-8 lists the condition codes used with the J Ree and JAee instructions. (To use the codes, replace the ee with the appropriate mnemonic
code; for example, JRUC, JALS, JRYGT, etc.) Before using one of these jump
instructions, use the CMP, CMPI, or CMPXY instruction; the compare instructions set the condition codes for the jump by subtracting a source value

12-30

Instruction Set - Program Control and Context Switching Instructions

from a destination value. The first mnemonics code column in Table 12-8 lists
the codes that can be used for a jump following a CMP or CMPI. The second
mnemonics code column list codes that can be used for a jump following a
CMPXY (codes that are preceded with an X can be used with the result of the
X comparison and codes that are preceded with a Y can be used with the result
of the Y comparison).

Table 12-8. Condition Codes for JRcc and JAcc Instructions
Mnemonic
Code
Unconditional
Compares
Unsigned
Compares

LO (C)
YLE
LS
HI
YGT
HS (NC)
EO (Z)
NE (NZ)

Signed
Compares

LT
XLE
LE
GT
GE
XGT
EO (Z)
NE (NZ)

Compare to
Zero

General
Arithmetic

Z
NZ
P
N
NN

YZ
YNZ

XZ
XNZ

Z
YZ
NZ
YNZ
YN
C
NC
YNN
B (C)
NB (NC)
vt
XN
NVt
XNN

Result of Compare

Status Bits

Code

don't care

0000

C
C+Z
CoZ

0001
0010
0011
1001
1010
1011

Unconditional
Ost lower than Src
Ost lower or same as Src
Ost higher than Src
Ost higher or same as Src
Ost = Src
Ost :J: Src
Ost < Src
Ost S Src
Ost> Src
Ost > Src
Ost -;;- Src
Ost :J: Src
Result = zero
Result :J: zero
Result is positive
Result is negative
Result is nonnegative

C
Z
Z
(N o_V) +_( NoV)
(N
V_+ (N "-V).::!: Z_
(N V Z) + (~ y. Z)
(N
V) + (N
V)
Z
Z
Z
Z
i\ioz
N
i\i
Z
Z
C
C
C
C
V
0

Result is zero
Result is nonzero
Carry set on resu It
No carryon result
Borrow set on result
No borrow on result
Overflow on result
V
No overflow on result
Note: A mnemonic code In parentheses IS an alternate code for the preceding code.
t Also used for window clipping
+ Logical OR
Logical AND
Logical NOT

0100
0110
0111
0101
1010
1011
0101
1011
0001
1110
1111
1010
1011
1000
1001
1000
1001
1100
1101

12-31

Instruction Set - Shift Instructions

12.8 Shift Instructions
The TMS3410 supports several instructions that left-rotate, left-shift, or
right-shift the contents of the destination register. These instructions use register-direct operands or a combination of register-direct and immediate operands; the shift amount is specified by the value of a 5-bit constant or by the
value specified in the 5 LSBs of a source register. (Note that the SRA Rs, Rd
and SRL Rs, Rd use the 2s complement value of the 5 LSBs in Rs.)

12-32

•

The RL instruction left-rotates the contents of the destination register
by. (This rotation is a barrel shift.) The bits shifted out of the MSB are
shifted into the LSB. The C (carry) bit is set to the final value shifted
out of the MSB.

•

The SLA instruction left shifts the contents of the destination register.
Os are shifted into the LSBs. The MSBs are shifted out through the C
(carry) bit so that the C bit is set to the final value shifted out of the
MSB. If either the N (sign) bit or any of the bits shifted out differ from
the original sign bit, the V (overflow) bit is set.

•

The SLL instruction left shifts the contents of the destination register.
Os are shifted into the LSBs. The MSBs are shifted out through the C
(carry) bit so that the C bit is set to the final value shifted out of the
MSB. The main difference between SLL and SLA is that SLL does not
check to see if the sign bit changes.

•

The SRA instruction right shifts the contents of the destination register.
The value of the sign bit is shifted into the MSBs; this sign-extends the
value and preserves the original value of the sign bit. The LSBs are
shifted out through the C (carry) bit so that the C bit is set to the final
value shifted out of the LSB.

•

The SRL instruction right shifts the contents of the destination register.
Os are shifted into the MSBs, beginning with bit 31. The LSBs are
shifted out through the C (carry) bit so that the C bit is set to the final
value shifted out of the LSB. The main difference between SRL and SRA
is that SRL does not preserve the original value of the sign bit.

Instruction Set - XV Instructions

12.9 XV Instructions
The TMS3401 0 allows you to use XY addresses. This is useful for specifying
pixel addresses on the screen. Many of the graphics instructions use XY addressing; the TMS34010 instruction set also supports several other instructions that allow you to manipulate XY addresses.
An XY address is a 32-bit address that is divided into two parts. The 16 LSBs
of the address are the X half of the address or register; the 16 MSBs of the
address are the Y half of the address or register. The two parts are treated as
completely separate values; for example, using the ADDXY instruction, the X
half does not propagate into the Y half.
Table 12-9 summarizes the instructions that use XY addresses.
Table 12-9. Summary of XY Instructions
Instruction
ADDXY Rs, Rd

Description
Add registers in XY

CPW Rs, Rd

Compare point to window PIXBLT L, XY

CMPXY Rs, Rd

Compare registers in XY
mode
Convert XY address to
linear address

PIXBLT XV. L

DRAV Rs. Rd

Draw and advance

PIXT Rs,

FILL XY

Fill array with processed
pixels

PIXT *Rs.XY, Rd

LINE [0, 1]

Line draw with XY
addressing
Move X half of Rs to X
half of Rd
Move Y half of Rs to Y
half of Rd

PIXT * Rs.XY,

CVXYL Rs, Rd

MOVX Rs, Rd
MOVY Rs, Rd

Instruction
PIXBLT B.XY

PIXBLT XY.XY

* Rd.XY
* Rd.XY

SUBXY Rs, Rd

Description
Pixel block transfer
(binary to XV)
Pixel block transfer
(linear to XV)
Pixel block transfer (XY
to linear)
Pixel block transfer (XY
to XV)
Pixel transfer (register to
indirect XV)
Pixel transfer (indirect XY
to register)
Pixel transfer (indirect XY
to indirect XV)
Subtract registers in XY
mode

•

The PIXBLT and FILL instructions in Table 12-9 use XY source and/or
destination addresses.

•

The PIXT instructions in Table 12-9 use the contents of registers as XY
addresses.

•

The LINE instruction draws a line along points that are calculated as XY
addresses.

•

The move instructions in Table 12-9 (MOVX and MOVY) move the X
or Y half of a source register into the X or Y half of a destination register.

•

The arithmetic and logical instructions in Table 12-9 (ADDXY, SU BXY,
and eM PXY) add, subtract. or compare the X and Y halves of the registers separately.

12-33

Instruction Set - Alphabetical Reference

12.10 Alphabetical Reference of Instructions
The remainder of this section is an alphabetical reference of the TMS34010
assembly language instructions. Each instruction discussion begins on a new
page, and contains the following information:

•

Syntax: Shows you how to enter an instruction. (Section 12.1, page
12-2, describes the symbols used in instruction syntaxes.)

•

Execution: Illustrates the effects of instruction execution on CPU registers and memory.

•

Instruction Words: Shows the object code generated by an instruction.

•

Description: Discusses the purpose of the instruction and any other
general information related to the instruction.

•

Machine States: Lists the instruction cycle timing. Two timings are
listed for each instruction; the first number is the cache-enabled case, the
second number is the cache-disabled case.

•

Status Bits: Lists the effects of instruction execution on the status bits
(N, C, Z, and V).

•

Examples: Show the effects of the instruction on memory and registers
using various sets of data and initial conditions.

Several instructions discuss additional topics; for example, the conditional
jump instructions list the conditions codes and mnemonics for various jumps,
and the graphics instructions list the implied operands that they use.

12-34

Store Absolute Value

Syntax

ABS

Execution

IRdl

Instruction
Words
Description

ASS

Rd
-+

15 14

ABS stores the absolute value of the contents of the destination register
back into the destination register. This is accomplished by:
•

Subtracting the contents of the destination register data from 0 and

•

Storing the result back into Rd if status bit N indicates that the result
is positive.

If the result of the subtraction is negative, then the original contents of the
destination register are retained.

Machine
States

1,4

Status Sits

N
C
Z
V

Examples

Set to the sign of the result of 0 - Rd; typically, N=O if the original
contents of Rd are negative (unless Rd = 80000000h), 1 otherwise
Unaffected
1 if the original data is 0, 0 otherwise
1 if there is an overflow, 0 otherwise; an overflow occurs if Rd contains
80000000h (80000000h is returned)

Code
ABS
ABS
ABS
ABS
ABS
ABS
ABS

Al
Al
Al
Al
Al
Al
Al

Before

After

NCZV

7FFFFFFFh
FFFFFFFFh
80000000h
80000001h
0OOOOOO1h
OOOOOOOOh
FFFAOO11h

1xOO
OxOO
1 x01
OxOO
1xOO
Ox10
OxOO

7FFFFFFFh
0OOOOOO1h
80000000h
7FFFFFFFh
000OOOO1h
OOOOOOOOh
0005FFEFh

12-35

ADD

Add Registers

Syntax

ADD

Execution

Rs + Rd

15 14

Instruction
Words
Description

Rs,Rd
Rd
9

ADD adds the contents of the source register to the contents of the destination register, and stores the result in the destination register.
You can is the ADD instruction with the ADDC instruction to perform
multiple-precision arithmetic.
Rs and Rd must be in the same register file.

Machine
States

1.4

Status Bits

N
C
Z
V

Examples

Code
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD

12-36

1 if
1 if
1 if
1 if

the result is negative, 0 otherwise
there is a carry, 0 otherwise
the result is 0, 0 otherwise
there is an overflow, 0 otherwise

AI,AD
AI,AD
AI,AD
AI,AD
AI,AD
AI,AD
AI,AD
AI,AD
AI,AD

Before

After

NCZV

FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
7FFFFFFFh
7FFFFFFFh
7FFFFFFFh
00000002h

FFFFFFFFh
00000001h
00000002h
80000000h
80000001h
80000001h
80000000h
00000001h
00000002h

1100
0110
0100
0101
1100
0110
1000
1001
0000

FFFFFFFEh
OOOOOOOOh
00000001h
7FFFFFFFh
80000000h
OOOOOOOOh
FFFFFFFFh
80000000h
00000004h

ADDC

Add Register with Carry
Syntax

ADDC

Execution

Rs + Rd + C -+ Rd

Instruction
Words
Description

Rs. Rd

15 14 13 12 11

0
Rd

AD DC adds the contents of the source register, the carry bit. and the contents of the destination register, and then stores the result in the destination
register. Note that the status bits are set on the final result.
Rs and Rd must be in the same register file.

Machine
States

1.4

Status Bits

N
C
Z
V

Examples

Code

1 if
1 if
1 if
1 if

ADDe
ADDe
ADDe
ADDe
ADDe
ADDe
ADDe
ADDe
ADDe
ADDe
ADDe
ADDe
ADDe
ADDe
ADDe
ADDe
ADDe
ADDe

the result is negative, 0 otherwise
there is a carry, 0 otherwise
the result is 0, 0 otherwise
there is an overflow, 0 otherwise

After

Before

Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO

1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0

FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
7FFFFFFFh
00000002h
FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
7FFFFFFFh
7FFFFFFFh
7FFFFFFFh
00000002h

FFFFFFFFh
00000001h
00000002h
80000000h
80000001h
80000001h
80000000h
00000001h
00000002h
FFFFFFFFh
00000001h
00000002h
80000000h
80000001h
80000001h
80000000h
00000001h
00000002h

NCZV
1100
0100
0100
1100
1100
0100
0110
1001
0000
1100
0110
0100
0101
1100
0110
1000
1001
0000

FFFFFFFFh
0OOOOOO1h
0OOOOO02h
80000000h
80000001h
80000001h
OOOOOOOOh
80000001h
00000005h
FFFFFFFEh
OOOOOOOOh
00000001h
7FFFFFFFh
80000000h
OOOOOOOOh
FFFFFFFFh
80000000h
00000004h

12-37

Add Immediate - 16 Bits

ADDI
Syntax

ADDI

Execution

IW + Rd .... Rd

Instruction
Words

15 14 13 12 11

000

IW, Rd [, Wj

987

6
0

olR

16-bit value

Description

This ADDI instruction adds a sign-extended, 16-bit immediate value to the
contents of the destination register, and stores the result in the destination
register. (The symbol IW in the syntax above represents a 16-bit, signextended immediate value.)
The assembler uses the short (16-bit) add if the immediate value is previously defined and is in the range -32,768 to 32,767. You can force the
assembler to use the short form by following the register operand with a

W:
ADDI

IW,Rd,W

If you use the W parameter and the value is outside the legal range, the
assembler discards all but the 16 LSBs and issues an appropriate warning
message.
You can use the ADDI instruction with the ADDC instruction to perform
multiple-precision arithmetic.

Machine
States

2,8

Status Bits

N
C
Z
V

Examples

Code

1 if
1 if
1 if
1 if

ADDI
ADDI
ADDI
ADD I
ADDI
ADDI

12-38

the result is negative, 0 otherwise
there is a carry, 0 otherwise
the result is 0, 0 otherwise
there is an overflow, 0 otherwise

Before
1,AO
2,AO
1,AO
2,AO
32767,AO
OFFFFOOIOh,AO,W

After

NCZV

FFFFFFFFh
FFFFFFFFh
7FFFFFFFh
00000002h
00000002h
FFFFFFFOh

0110
0100
1001
0000
0000
0110

OOOOOOOOh
00000001h
80000000h
00000004h
00008001h
OOOOOOOOh

Add Immediate - 32 Bits

ADDI

Syntax

ADDI

Execution

IL + Rd .... Rd

Instruction
Words

15 14 13 12 11
0

IL. Rd [. LJ

16 LSBs of IL
16 MSBs of IL

Description

This ADDI instruction adds a 32-bit. signed immediate value to the contents of the destination register. and stores the result in the destination register. (The symbol IL in the syntax above represents a 32-bit, signed
immediate value.)
The assembler uses the long (32-bit) AD D I if it cannot use the short form.
You can force the assembler to use the long form by following the register
operand with an L:

ADDI IL,Rd,L

Machine
States

3,12

Status Bits

N
C
Z
V

Examples

Code

1
1
1
1

if
if
if
if

the result is negative, 0 otherwise
there is a carry, 0 otherwise
the result is O. 0 otherwise
there is an overflow. 0 otherwise

Before

AO
ADDI
ADDI
ADDI
ADDI
ADDI

OFFFFFFFFh,AO
80000000h,AO
80000000h,AO
32768,AO
2,AO,L

FFFFFFFFh
FFFFFFFFh
7FFFFFFFh
7FFFFFFFh
FFFFFFFFh

After

NCZV

1100
0101
1000
1001
0100

FFFFFFFEh
7FFFFFFFh
FFFFFFFFh
80007FFFh
00000001h

12-39

ADDK

Add Constant (5 Bits)

Syntax

ADDK K,Rd

Execution

K + Rd

Instruction
Words
Description

15 14

10 0 0

0 01

ADDK adds a 5-bit constant to the contents of the destination register and
stores the result in the destination register. (The symbol K in the syntax
above represents a 5-bit constant.)
The constant is treated as an unsigned number in the range 1-32; if the original value of K=32, then K is converted to 0 in the opcode. The assembler
issues an error if you try to add 0 to a register.
You can use the ADDK instruction with the AD DC instruction to perform
mu Itiple-precision arithmetic.

Machine
States

1,4

Status Bits

N
C
Z
V

Examples

Code

1 if the result is negative, 0 otherwise
1 if there is a carry, 0 otherwise
1 if the result is 0, 0 otherwise
1 if there is an overflow, 0 otherwise

ADDK
ADDK
ADDK
ADDK
ADDK
ADDK

12-40

Before
1,AO
2,AO
1,AO
1,AO
32,AO
32,AO

After

NCZV

FFFFFFFFh
FFFFFFFFh
7FFFFFFFh
80000000h
80000000h
00000002h

0110
0100
1001
1000
1000
0000

OOOOOOOOh
00000001h
80000000h
80000001h
80000020h
00000022h

Add Registers in XV Mode
Syntax

ADDXV Rs, Rd

Execution

RsX + RdX .... RdX
RsV + RdV .... RdV

Instruction
Words

15 14

11
Description

ADDXV

000

2
Rd

ADDXY adds the signed source X value to the signed destination X value.
adds the signed source Y value to the signed destination Y value. and stores
the result in the destination register. The source and destination registers
are treated as if they contained separate X and Y values. Any carry out from
the lower (X) half of the register does not propagate into the upper (Y) half.
If you only want to add the X halves together, then one of the Y values must
be 0 (the method for adding the Y halves is similar).
You can use this instruction to manipulate XY addresses in the register file;
ADDXY is also useful for incremental figure drawing.
Rs and Rd must be in the same register file.

Machine
States
Status Bits

1,4

N
C
Z

Examples

1 if resulting X field is all Os, 0 otherwise
The sign bit of the Y half of the result
1 if Y field is all Os, 0 otherwise
The sign bit of the X haff of the result

Code
ADDXY
ADDXY
ADDXY
ADDXY
ADDXY
ADDXY
ADDXY
ADDXY
ADDXY
ADDXY
ADDXY
ADDXY
ADDXY
ADDXY
ADDXY
ADDXY

Before
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO

After

NCZV

OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
OOOOFFFFh
OOOOFFFFh
OOOOFFFFh
OOOOFFFFh
FFFFOOOOh
FFFFOOOOh
FFFFOOOOh
FFFFOOOOh
FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
FFFFFFFFh

OOOOOOOOh
00000001h
00010000h
00010001h
00000001h
00010001h
00000002h
00010002h
00010000h
00010001h
00020000h
00020001h
00010001h
00010002h
00020001h
00020002h

OOOOOOOOh
00000001h
00010000h
00010001h
OOOOOOOOh
00010000h
00000001h
00010001h
OOOOOOOOh
00000001h
00010000h
00010001h
OOOOOOOOh
00000001h
00010000h
00010001h

1010
0010
1000
0000
1010
1000
0010
0000
1010
0010
1000
0000
1010
0010
1000
0000

12-41

AN D

AN D Registers \

Syntax

AND

EXBcution

Rs AND Rd

Instruction
Words

15 14

10
Description

MachinB
States

0 0 01

AND bitwise-ANDs the contents of the source register with the contents
of the destination register and stores the result in the destination register.
Rs and Rd must be in the same register file.

1,4

Status Bits

N
C
Z
V

ExamplBs

Code
AND
AND
AND
AND
AND
AND
AND

12-42

Rs. Rd

Unaffected
Unaffected
1 if the result is 0.0 otherwise
Unaffected

AI,AO
AI,AO
AI,AD
AI,AD
AI,AO
AI,AD
AI,AD

Before

After

NCZV

FFFFFFFFh
FFFFFFFFh
OOOOOOOOh

FFFFFFFFh
OOOOOOOOh
OOOOOOOOh
55555555h
AAAAAAAAh
55555555h
AAAAAAAAh

xxOx
x x 1x
xx1 x
x x 1x
xxOx
xxOx
xx1 x

FFFFFFFFh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
AAAAAAAAh
55555555h
OOOOOOOOh

AAAAAAAAh
AAAAAAAAh

55555555h
55555555h

AND Immediate (32 Bits)

Syntax

ANDI

Execution

IL AND Rd ..... Rd

Instruction
Words

Description

ANDI

IL, Rd

15 14
0
0

13
0

12
0

6
5
4
0
oI R
1 s complement of 16 LSBs of I L
1 s complement of 16 MSBs of IL

10
0

ANDI bitwise-ANDs the value of a 32-bit immediate value with the contents of the destination register, and stores the result in the destination register. (The symbol IL in the syntax above represents a 32-bit immediate
value.)
This is an alternate mnemonic for ANDNI IL,Rd. Note that the assembler
stores the 1 s complement of I L in the two extension words.

Machine
States
Status Bits

3,12

N
C
Z

Examples

Unaffected
Unaffected
1 if the result is 0, 0 otherwise
Unaffected

Code

AND!
AND!
AND!
AND!
AND!
AND!
AND!

Before

OFFFFFFFFh,AO
OFFFFFFFFh,AO
OOOOOOOOh,AO
OAAAAAAAAh,AO
OAAAAAAAAh,AO
55555555h,AO
55555555h,AO

After

NCZV

FFFFFFFFh
OOOOOOOOh
OOOOOOOOh
55555555h

xxOx
xx1x
xx1x
xx1x
xxOx
xxOx
xx1x

FFFFFFFFh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh

AAAAAAAAh
55555555h

AAAAAAAAh

AAAAAAAAh
55555555h
OOOOOOOOh

12-43

ANON

AND Register with Complement

Syntax

ANON Rs. Rd

Execution

(NOT Rs) AND Rd

Instruction
Words
Description

15 14

13
0

11
0

Rd
10
0

AN DN bitwise-AN Ds the 1 s complement of the contents of Rs with the
contents of Rd. and stores the result in the destination register.
Rs and Rd must be in the same register file. Note that ANDN Rn, Rn has the
same effect as CLR Rn.

Machine
States

1,4

Status Bits

N
C
Z
V

Examples

Code

Unaffected
Unaffected
1 if the result is 0, 0 otherwise
Unaffected

ANDN
ANDN
ANDN
ANDN
ANDN
ANDN
ANDN

12-44

Before
AI,AO
AI,AO
AI,AO
AI,AO
AI,AO
AI,AO
AI,AO

A1
FFFFFFFFh
FFFFFFFFh
OOOOOOOOh
AAAAAAAAh
AAAAAAAAh
55555555h
55555555h

After
AO
FFFFFFFFh
OOOOOOOOh
OOOOOOOOh
55555555h
AAAAAAAAh
55555555h
AAAAAAAAh

NCZV AO

xx
xx
xx
xx
xx
xx
xx

1x
1x
1x
Ox
1x
1x
Ox

OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
55555555h
OOOOOOOOh
OOOOOOOOh
AAAAAAAAh

AND Not Immediate (32 Bits)
Syntax

ANONI

Execution

(NOT IL) AND Rd ..... Rd

Instruction
Words

15 14
0
0

ANONI

IL. Rd

13
0

12
0

11
1

10
0

6
0

oI R I

16 LSBs of IL
16 MSBs of IL

Description

Machine
States
Status Bits

ANDNI bitwise-ANDs the 1s complement of a 32-bit immediate value with
the contents of the destination register, and stores the result in the destination register. (The symbol IL in the syntax above represents a 32-bit
immediate value.) ANDI also uses this opcode.
3,12

N
C
Z

Examples

Unaffected
Unaffected
1 if the result is 0, 0 otherwise
Unaffected
Before

Code
ANONI
ANONI
ANONI
ANONI
ANONI
ANONI
ANONI

OFFFFFFFFh,AO
OFFFFFFFFh,AO
oOOOOOOOh,AO
OAAAAAAAAh,AO
OAAAAAAAAh, AO
55555555h,AO
55555555h,AO

After

NCZV

FFFFFFFFh
OOOOOOOOh
OOOOOOOOh
55555555h

xx1x
xx1x
xx1x
xxOx
xx1x
xx1x
xxOx

OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
55555555h
OOOOOOOOh
OOOOOOOOh

AAAAAAAAh
55555555h

AAAAAAAAh

12-45

Test Register Bit - Constant

BTST

Syntax

BTST K, Rd

Execution

Set status on value of bit K in Rd

Instruction
Words
Description

15 14
0

13
0

10
1

4
R

2
Rd

BTST tests a bit in the destination register bit and sets status bit Z accordingly. This form of the BTST instruction uses a 5-bit constant to specify the
bit in Rd that is tested (the symbol K in the syntax above represents a 5-bit
constant). The K value must be an absolute expression that evaluates to a
number in the range 0 to 31; if the value is greater than 31, the assembler
issues a warning and truncates the K operand value to the five LSBs.
Note that the assembler 1 s-complements the value of K before inserting it
into the opcode.

Machine
States
Status Bits

1,4

N
C
Z

Examples

Unaffected
Unaffected
1 if the bit tested is 0, 0 if the bit tested is 1 .
Unaffected

Code

BTST
BTST
BTST
BTST
BTST
BTST
BTST
BTST
BTST
BTST
BTST
BTST

12-46

D,AD
lS,AD
31,AD
D,AD
lS,AD
31,AD
O,AO
lS,AO
31,AO
O,AO
lS,AO
31,AO

Before

After

AO
55555555h
55555555h
55555555h

NCZV
xxOx
xx1x
xx1x
xx1x
xxOx
xxOx
xxOx
xxOx
xxOx
xx1x
xx1x
xx1x

AAAAAAAAh
AAAAAAAAh
AAAAAAAAh
FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh

Test Register Bit - Register

BTST

Syntax

BTST Rs, Rd

Execution

Set status on value of specified bit in Rd

Instruction
Words
Description

15 14

2
Rd

BTST tests a bit in the destination register bit and sets status bit Z accordingly. This form of the BTST instruction uses the 5 LSBs of the source register to specify the bit in Rd that is tested (the symbol Rs in the syntax
above represents the source register). Note that the 27 MSBs of Rs are
ignored.
Rs and Rd must be in the same register file.

Machine
States
Status Bits

2,5

N
C

Z
V

Examples

Unaffected
Unaffected
1 if the bit tested is 0, 0 if the bit tested is 1
Unaffected

Code

BTST
BTST
BTST
BTST
BTST
BTST
BTST
BTST
BTST
BTST
BTST
BTST
BTST

Before
AI,AO
AI,AO
AI,AO
AI,AO
AI,AO
AI,AO
AI,AO
AI,AO
AI,AO
AI,AD
AI,AO
AI,AO
AI,AO

After

NCZV

OOOOOOOOh
OOOOOOOFh
0000001Fh
OOOOOOOOh
OOOOOOOFh
0000001Fh
FFFFFF8Fh
OOOOOOOOh
OOOOOOOFh
0000001Fh
OOOOOOOOh
OOOOOOOFh
0000001Fh

55555555h
55555555h
55555555h

xxOx
xx1x
xx1x
xx1x
xxOx
xxOx
xxOx
xxOx
xxOx
xxOx
xx1x
xx1x
xx1x

AAAAAAAAh
AAAAAAAAh
AAAAAAAAh
FFFF7FFFh
FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh

12-47

CALL

Call Subroutine - Indirect

Syntax

CAll Rs

Execution

PC' -+ TOS
Rs -+ PC
SP - 32 -+ SP

Instruction
Words
Description

15 14

CALL pushes the address of the next instruction (PC') onto the stack, then
jumps to a subroutine whose address is contained in the source register.
You can use this instruction for indexed subroutine calls. Note that when
Rs is the SP, Rs is decremented after being written to the PC (the PC
contains the original value of Rs).
The TMS3401 0 always sets the four LSBs of the program counter to 0, so
instructions are always word aligned.
The stack pointer (SP) points to the top of the stack; the stack is located
in external memory. The stack grows in the direction of decreasing linear
addresses. PC' is pushed onto the stack and the SP is predecremented by
32 before the return address is loaded onto the stack. Stack pointer alignment affects timing as indicated in Machine States, below.
Use the RETS instruction to return from a subroutine.

Machine
States

3+ (3),9 (SP aligned)
3+ (9),15 (SP nonaligned)

Status Bits

N
C
Z
V

Example

CALL AO

Unaffected
Unaffected
Unaffected
Unaffected

Before
AO

After
PC

01234560h 04442210h

F000020h

01 234560h

FOOOOOOh

Memory contains the following values after instruction execution:

Address
F000010h
F000020h

12-48

Data
2220h
0444h

Call Subroutine - Absolute

Syntax

CALLA Address

Execution

PC' ... TOS
Address'" PC

Instruction
Words

Description

15 14
0
0

13
0

12
0

CALLA

9
8
7
6
5
1
0
1
0
0
16 LSBs of Address
16 MSBs of Address

CALLA pushes the address of the next instruction (PC') onto the stack,
then jumps to the address contained in the two extension words. The Address operand is a 32-bit absolute address. This instruction is used for long
(greater than ±32K words) or externally referenced calls.
The lower four bits of the program counter are always set to 0, so instructions are always word-aligned.
The stack pointer (SP) points to the top of the stack; the stack is located
in external memory. The stack grows in the direction of decreasing linear
address. PC' is pushed onto the stack and the SP is predecremented by 32
before the return address is loaded onto the stack. Stack pointer alignment
affects timing as indicated in Machine States, below.
Use the RETS instruction to return from a subroutine.

Machine
States

4+(2),15 (SP aligned)
4+(8),21 (SP nonaligned)

Status Bits

N
C
Z
V

Example

CALLA 01234560h

Unaffected
Unaffected
Unaffected
Unaffected

Before

After

04442210h

OF000020h

01234560h

OFOOOOOOh

Memory contains the following values after instruction execution:

Address
F000010h
F000020h

Data
2240h
0444h

12-49

Call Subroutine - Relative

CALLR
Syntax

CALLR Address

Execution

PC' -+ TOS
PC' + (offset x 16)

Instruction
Words

Description

15 14

PC
10

9
0

0
1

offset

CALLR pushes the address of the next instruction (PC') onto the stack,
then jumps to the subroutine at the address specified by the sum of the next
instruction address and the signed word offset. This instruction is used for
calls within a specified module or section.
The Address operand is a 32-bit address within ±32K words (-32,768 to
32,767) of the PC. The address must be defined within the current section;
the assembler does not accept an address value that is externally defined
or defined within a different section than PC'. The assembler calculates the
offset value for the opcode as (Address - PC')/16.
The lower four bits of the program counter are always set to 0, so instructions are always word aligned.
The stack pointer (SP) points to the top of the stack; the stack is located
in external memory. The stack grows in the direction of decreasing linear
address. The PC is pushed on to the stack and the SP is predecremented
by 32 before the return address is loaded onto the stack. Stack pointer
alignment affects timing as indicated in Machine States, below.
Use the RETS instruction to return from a subroutine.

Machine
States

3+ (2), 11 (SP aligned)
3+(8),17 (SP nonaligned)

Status Bits

N
C
Z
V

Examples

Code

Before

CALLR 0447FFFOh
CALLR 04480000h

04400000h
04400000h

Unaffected
Unaffected
Unaffected
Unaffected

After

SP
OF000020h
OF000020h

0447FFFOh
04480000h

oFOOOOOOh
OFOOOOOOh

Memory contains the following values after instruction execution:

Address
F000010h
F000020h

12-50

Data

OOOOh
0440h

CLR

Clear Register

Syntax

CLR

Execution

Rd XOR Rd ..... Rd

Instruction
Words
Description
Machine
States
Status Bits

15 14

CLR clears the destination register by XORing the contents of the register
with itself. This is an alternate mnemonic for XOR Rd,Rd.
1,4

N
C
Z
V

Unaffected
Unaffected
1
Unaffected

Examples

Before

AO
CLR
CLR
CLR
CLR

AO
AO
AO
AO

FFFFFFFFh

00000001h
80000000h
AAAAAAAAh

After

OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh

NCZV

xx1x
xx1x
xx1x
xx1x

12-51

CLRC

Clear Carry

Syntax

CLRC

Execution

Instruction
Words
Description

15 14
0
10

13
0

12
0

11
0

10
0

4
0

3
0

2
0

0
0

CLRC sets the C (carry) bit in the status register to 0; the rest of the status
register is unaffected. (Note that the SETC instruction sets the C bit.)
This instruction is useful for returning a true/false value (in the carry bit)
from a subroutine without using a general-purpose register.

Machine
States
Status Bits

1,4

N
C

Z
V

Examples

Unaffected

0
Unaffected
Unaffected

Code

Before

ST
CLRC
CLRC
CLRC

12-52

FOOOOOOOh
40000010h
BOOOO01Fh

After

NCZV
1111
0100
1011

ST
BOOOOOOOh
00000010h
BOOOO01Fh

NCZV
1011
0000
1011

CMP

Compare Registers
Syntax

CMP Rs. Rd

Execution

Set status bits on the result of Rd - Rs

Instruction
Words
Description

15 14
10

13
0

12
0

10
0

6
Rs

2
Rd

CMP sets the status bits on the result of subtracting the contents of Rs from
the contents of Rd. This is a nondestructive compare; the contents of the
registers are not affected. This instruction is often used in conjunction with
the JAcc or JRcc conditional jump instructions.
Rs and Rd must be in the same register file.

Machine
States

1.4

Status Bits

N
C
Z
V

Examples

Code

Before

eMP
eMP
eMP
eMP
eMP
eMP
eMP

00000001h
00000001h
00000001h
00000001h
FFFFFFFFh
FFFFFFFFh
80000000h

1
1
1
1

if the result is negative. 0 otherwise
if a there is a borrow, 0 otherwise
if the result is 0,0 otherwise
if there is an overflow, 0 otherwise

Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO

After Jumps Taken

00000001h
00000002h
FFFFFFFFh
80000000h
7FFFFFFFh
80000000h
7FFFFFFFh

NCZV
0010
0000
1000
0001
1101
1100
1101

UC,NN,NC,Z,NV,LS,GE,LE,HS
UC,NN,NC,NZ,NV,P,HI.GE,GT,HS
UC,N,NC,NZ,NV,P,HI,LT,LE,HS
UC,NN,NC,NZ,V,HI,LT,LE,HS
UC,N,C,NZ,V,LS,GE,GT,LO
UC,N,C,NZ,NV,LS,LT,LE,LO
UC,N,C,NZ,V,LS,GE,GT,LO

12-53

Compare Immediate - 16 Bits

CMPI
Syntax

CMPI IW, Rd [, Wj

Execution

Set status bits on the result of Rd - IW

Instruction
Words

15 14

000

5
0

2
Rd

1s complement of IW

Description

CMPI sets the status bits on the result of subtracting a 16-bit, signextended immediate value from the contents of the destination register.
(The symbol/W in the syntax above represents a 16-bit, signed immediate
value.) This is a nondestructive compare; the contents of the destination
register are not affected. This instruction is often used in conjunction with
the JAcc or JRcc conditional jump instructions.
Note that the assembler inserts the 1 s complement of the 16-bit value into
the second instruction word.
The assembler uses the short form of the CMPI instruction if the immediate
value is previously defined and is in the range -32,768 to 32,767. You can
force the assembler to use the short form by following the register operand
withW:

CMPI

IW,Rd,W

The assembler truncates the upper bits and issues an appropriate warning
message if the value is greater than 16 bits.

Machine
States

2,8

Status Bits

N
C
Z
V

Examples

Code

1 if
1 if
1 if
1 if

CMPI
CMPI
CMPI
CMPI
CMPI
CMPI
CMPI
CMPI
CMPI
CMPI

12-54

the result is negative, 0 otherwise
there is a borrow, 0 otherwise
the result is 0, 0 otherwise
there is an overflow, 0 otherwise

Before

I,AD
I,AD
I,AD
I,AD
I,AD
-2,AD
-2,AD
-2,AD
-2,AD
-I,AD

After Jumps Taken

NCZV

00000002h
00000001h
OOOOOOOOh
FFFFFFFFh
80000000h
OOOOOOOOh
FFFFFFFFh
FFFFFFFEh
FFFFFFFDh
7FFFFFFFh

0000
0010
1100
1000
0001
0100
0000
0010
1100
1101

UC,NN,NC,NZ,NV,P,HI,GE,GT,HS
UC,NN,NC,Z,NV,LS,GE,LE,HS
UC,N,C,NZ,NV,LS,LT.LE,LO
UC.N.NC,NZ,NV.P.HI.LT.LE.HS
UC,NN,NC,NZ,V,HI,LT,LE,HS
UC,NN,C,NZ,NV,P.LS,GE,GT,LO
UC,NN.NC.NZ.NV.P.LI.GE.GT.HS
UC.NN.NC.Z,NV,LS,GE.LE.HS
UC.N.C.NZ.NV.LS.LT.LE.LO
UC,N.C,NZ,V,LS.GE,GT.LO

Compare Immediate - 32 Bits

CMPI

Syntax

CMPI Ii, Rd [. l}

Execution

Set status bits on the result of Rd - IL

Instruction
Words

15 14
0

2
Rd

1s complement of 16 LSBs of I L
1s complement of 16 MSBs of IL

Description

CMPI sets the status bits on the result of subtracting a 32-bit, signed immediate value from the contents of the destination register. (The IL symbol
in the syntax above represents a 32-bit. signed immediate value.) This is a
nondestructive compare; the contents of the destination register are not affected.
Note that the assembler inserts the 1s complement of the 16 LSBs of the
value into the second instruction word. and inserts the 1 s complement of
the 16 MSBs of the value into the third instruction word.
The assembler uses this form of the CMPI instruction if it cannot use the
short form. You can force the assembler to use the long form by following
the register operand with an l:
eMP!

!L,Rd,L

This instruction is often used in conjunction with the JAcc or JRcc conditional jump instructions.

Machine
States
Status Bits

3.12
N
C
Z
V

1
1
1
1

if
if
if
if

the result is negative. 0 otherwise
there is a borrow. 0 otherwise
the result is 0.0 otherwise
there is an overflow. 0 otherwise

Examples
eMP!
eMP!
eMP!
eMP!
eMP!
eMP!
eMP!
eMP!
eMP!
eMP!

8000h,AO
8000h, AO
8000h,AO
8000h,AO
8000h, AO
OFFFF7FFFh,AO
OFFFF7FFEh,AO
OFFFF7FFEh,AO
OFFFF7FFEh,AO
OFFFF7FFFh,AO

Before

After

NCZV
0000
0010
1100
1000
0001
0100
0000
0010
1100
1101

00008001h
00008000h
00007FFFh
FFFFFFFFh
80007FFFh
OOOOOOOOh
FFFF7FFFh
FFFF7FFEh
FFFF7FFDh
7FFF7FFFh

Jumps Taken
UC,NN,NC,NZ,NV,P,HI,GE,GT,HS
UC,NN,NC,Z,NV,LS,GE,LE,HS
UC,N,C,NZ,NV,LS,LT,LE,LO
UC,N,NC,NZ,NV,P,HI,LT,LE,HS
UC,NN,NC,NZ,V,HI.LT,LE,HS
UC,NN,C,NZ,NV,P,LS,GE,GT,LO
UC,NN,NC,NZ,NV,P,HI,GE,GT,HS
UC,NN,NC,Z,NV,LS,GE,LE,HS
UC,N,C,NZ,NV,LS,LT,LE,LO
UC,N,C,NZ,V,LS,GE,GT,LO

12-55

CMPXV

Compare X and V Halves of Registers

Syntax

CMPXY Rs, Rd

Execution

Set status bits on the results of:
RdX - RsX
RdY - RsY

Instruction
Words

15 14 13

11
Description

12 11
0

4
R

CMPXV compares the source register to the destination register in XV mode
and sets the status bits as if a subtraction had been performed. This is a
nondestructive compare; the contents of the register are not affected. The
source and destination registers are treated as signed XV registers. Note
that no overflow detection is provided.

Rs and Rd must be in the same register file.

Machine
States

1,4

Status Bits

N
C
Z
V

Examples

Code

1 if source
Sign bit of
1 if source
Sign bit of

CMPXY
CMPXY
CMPXY
CMPXY
CMPXY
CMPXY
CMPXY
CMPXY
CMPXY

12-56

X field =
V half of
V field =
X half of

destination X field, 0 otherwise
the result
destination V field, 0 otherwise
the result

Before
AI, AD
Al,AD
Al,AD
Al,AD
AI, AD
Al,AD
Al,AD
AI, AD
Al,AD

After Jumps Taken

NCZV

00090009h
00090009h
00090009h
00090009h
00090009h
00090009h
00090009h
00090009h
00090009h

00010001 h
00090001 h
00010009h
00090009h
00000010h
00090010h
00100000h
00100009h
0010001 Oh

0101
0011
1100
1010
0100
0010
0001
1000
0000

NN.C.NZ.V.LS.LT
NN.NC.Z.V.LS.LT
N.C.NZ.NV.LS.LT
N.NC.Z.NV.LS.LT
NN.C.NZ.NV.LS.GE
NN.NC.Z.NV.LS.GE
NN.NC.NZ.V.HI.LT
N.NC.NZ.NV.HI.LT
NN.NC.NZ.NV.HI.GE

Compare Point to Window
Syntax

CPW RS,Rd

Execution

point code

Instruction
Words
Description

CPW

15 14 13

2
Rd

CPW compares a point represented by an XY value in the source register to
the window limits in the WST ART and WEN D registers. The contents of
the source register are treated as an XY address that consists of 16-bit
signed X and Y values. WSTART and WEND are also treated as signed
XV-format registers. WSTART and WEND must contain positive values;
negative values produce unpredictable results. The location of the point
with respect to the window is encoded as shown below; the code is loaded
into the destination register.

Cod...
0101

0100

0110
31
88
54
0
1000....000 CODE 000001 Rd

1001

1000

1010

The following list describes the contents of the destination register after
CPW execution:

Bit Postion: Contents:
~4

Os
1 if
1 if
1 if
1 if
Os

5
6
7
8
9-31

WSTART.X > Rs.X, 0 otherwise
Rs.X > WEND.X, 0 otherwise
WSTART.Y > Rs.Y,O otherwise
Rs.Y > WEND.Y, 0 otherwise

This instruction can also be used to trivially reject lines that do not intersect
with a window. The CPW codes for the two points defining the line are
ANDed together. If the result is nonzero, then the line must lie completely
outside the window (and does not intersect it). A 0 result indicates that the
line may intersect the window, and a more rigorous test must be applied.
Rs and Rd must be in the same register file.

Implied
Operands

B File Registers
Register
B5

Name
WSTART

WEND

Format

XY
XY

Description
Window start. Defines inclusive starting
corner of window (lesser value corner).
Window end. Defines inclusive ending
corner of window (greater value corner).

12-57

Compare Point to Window

CPW
Machine
States
Status Bits

Examples

1,4

N Unaffected
C Unaffected
Z Unaffected
V 1 if point lies outside window, 0 otherwise
You must select appropriate implied operand values before executing the
CPW instruction. In this example, the implied operands are set up as follows, specifying a block of 36 pixels.
WSTART = 5,5
WEND
= A,A
CPW AI,AD

Before
A1

0OO40004h
0OO40005h
0OO4000Ah
0OO4000Bh
0OO50004h
0OO50005h
0OO5000Ah
0OO5000Bh
OOOAOOO4h
OOOAOOO5h
OOOAOOOAh
OOOAOOOBh
OOOBOOO4h
OOOBOOO5h
OOOBOOOAh
OOOBOOOBh

12-58

After
NCZV

xxxO
xxxO
xxxO
xxx1
xxx1
xxxO
xxxO
xxxO
xxxO
xxx1
xxx1
xxxO
xxxO
xxxO
xxxO
xxxO

OOOOOOAOh
0OOOOO80h
0OOOOO80h
OOOOOOCOh
0OOOOO20h
OOOOOOOOh
OOOOOOOOh
0OOOOO40h
0OOOOO20h
OOOOOOOOh
OOOOOOOOh
0OOOOO40h
0OOOO120h
0OOOO100h
0OOOO100h
0OOOO140h

NCZV

xxx1
xxx1
xxx1
xxx1
xxx1
xxxO
xxxO
xxx1
xxx1
xxxO
xxxO
xxx1
xxx1
xxx1
xxx1
xxx1

Convert XV Address to Linear Address
Syntax

CVXYl Rs, Rd

Execution

RsXY

Instruction
Words
Description

15 14
11

CVXYL

linear address in Rd
13

10
0

4
R

2
Rd

CVXYL converts an XY address to a linear address:
•

The source register contains an XY address. The signed X value occupies the 16 LSBs of the register and the signed Y value occupies
the 16 MSBs. The X value must be positive.

•

The XY address is converted into a 32-bit linear address which is
stored in the destination register.

The following conversion formula is used:

Address

[(Y x Display Pitch) OR (X x Pixel Size)] + Offset

Since the TMS3401 0 restricts the screen pitch and pixel size to powers of
two (for XY addressing), the multiply operations in this conversion are actually shifts. The offset value is in the OFFSET register. The CONVDP value
is used to determine the shift amount for the Y value, while the PSIZE register determines the X shift amount.
Rs and Rd must be in the same register file.

Implied
Operands
Register
63
64

Name
DPTCH
OFFSET

Address
COOO0140h
COOO0150h

Name
CONVDP
PSIZE

B File Registers
Format
Description
Linear
Destination pitch
Linear
Screen origin (location 0,0)
I/O Registers
Description and Elements (Bits)
XY-to-linear conversion (destination pitch)
Pixel size (1,2.4.8,16)

Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
CVXYL instruction. To ensure that this register contains the correct value
for execution, you may want to follow the write to that location with an
instruction that reads the same location (such as a MOVE SAddress,Rd instruction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.

Machine
States
Status Bits

3,6
N
C
Z
V

Unaffected
Unaffected
Unaffected
Unaffected

12-59

CVXVL

Convert XV Address to Linear Address

Examples

CVXYL
CVXYL
CVXYL
CVXYL
CVXYL
CVXYL
CVXYL
CVXYL
CVXYL

12-60

Before

After

OFFSET

PSIZE

CONVDP

0014h
00400030h
OOOOOOOOh 0010h
00020300h
0014h
00400030h
OOOOOOOOh 0008h
00020180h
0014h
OOOOOOOOh 0004h
00020000h
00400030h
0014h
00400030h
00028000h
00008000h 0004h
oFOOOOOOh 0004h 0014h OF020000h
00400030h
0014h
00020060h
OOOOOOOOh 0002h
00400030h
0014h
00020030h
OOOOOOOOh 0()01h
00400030h
0013h
00040030h
OOOOOOOOh 0001h
00400030h
0015h
00400030h
00010000h
OOOOOOOOh 0001h
CONVDP = 0013h corresponds to DPTCH = 00001000h
CONVDP = 0014h corresponds to DPTCH = 00000800h
CONVDP = 0015h corresponds to DPTCH = 00000400h

AO,Al
AO,Al
AO,Al
AO,Al
AO,Al
AO,Al
AO,Al
AO,Al
AO,Al

Decrement Register

DEC

Syntax

DEC

Execution

Rd - 1

Instruction
Words

15 14 13 12 11

Description

4
R

0
Rd

DEC subtracts 1 from the contents of the destination register and stores the
result in the destination register. This instruction is an alternate mnemonic
for SUBK I, Rd.
You can use the DEC instruction with the SUBB instruction to perform
multiple-precision arithmetic.

Machine
States

1,4

Status Bits

N
C
Z
V

Examples

Code

Before

DEC
DEC
DEC
DEC
DEC

00000010h
00000001h
OOOOOOOOh
FFFFFFFFh
80000000h

1 if
1 if
1 if
1 if

the result is negative, 0 otherwise
there is a borrow, 0 otherwise
the result is 0, 0 otherwise
there is an overflow, 0 otherwise

Al
Al
Al
Al
Al

After

OOOOOOOFh
OOOOOOOOh
FFFFFFFFh
FFFFFFFEh
7FFFFFFFh

NCZV

0000
0010
1100
1000
0001

12-61

DINT

Disable Interrupts

Syntax

DINT

Execution

Instruction
Words

15 14
0

1 0

Description

IE
13
0

12
0

11
0

10
0

7
0

Status Bits

3,6
N

C
Z

Unaffected
Unaffected
Unaffected
Unaffected

V
IE 0

Examples

Before
DINT
DINT

12-62

4
0

3
0

2
0

0
0

DINT disables interrupts by setting the global interrupt enable bit (IE, status
bit 21) to O. All interrupts except reset and NMI are disabled; the interrupt
enable mask in the INTENB register is ignored. The remainder of the status
register is unaffected.
The EINT instruction enables interrupts.

Machine
States

After

00000010h
00200010h

00000010h
00000010h

Divide Registers - Signed

DIVS

Syntax

DIVS

Execution

Rd Even: Rd:Rd+1/Rs
Rd Odd: Rd/Rs .... Rd

....

15 14

Instruction
Words
Description

Rs. Rd

Rd. remainder .... Rd+1

0 01

DIVS performs a signed 32-bit or 64-bit divide. The source register contains the 32-bit signed divisor. The destination register contains a 32-bit
signed dividend or the most significant half of a 64-bit signed dividend.
depending on whether Rd is an odd register (for example. A1 or B3) or an
even register (for example. A8 or B2):
Rd Even

DIVS performs a signed divide of the 64-bit operand contained
in the two consecutive registers. starting at the specified destination register. by the 32-bit contents of the source register.
The specified even-numbered destination register. Rd. contains
the 32 MSBs of the dividend. The next consecutive register
(which is odd-numbered) contains the 32 LSBs of the dividend. The quotient is stored in the destination register. and the
remainder is stored in the following register (Rd+1). The remainder is always the same sign as the dividend (in Rd:Rd+1).
Avoid using A14 or B14 as the destination register. since this
overwrites the SP; the assembler issues a warning in this case.

Rd Odd

DIVS performs a signed divide of the 32-bit operand contained
in the destination register by the 32-bit value in the source register. The quotient is stored in the destination register; the remainder is not returned.

Rs and Rd must be in the same register file.

Machine
States

Rd Odd
Normal
39,42
41,44
Result
80000000h
7.10
Rs
0
treated as normal
Rd ~ Rs

Status Bits

Rd Even
40,43
41,44
7.10
7.10

0 if:
•
•
•

Rs = O. or
Rd is even and Rd ~ Rs. or
Quotient is nonnegative.

1 if:
•
•

Result = 80000000h or
Quotient is negative.

C Unaffected
Z 0 if:
•
•

Rs = O. or
Rd is even and Rd ~ Rs. or
12-63

Divide Registers - Signed

DIVS

••

Result = 80000000h, or
Quotient ¢ O.

•

Quotient

1 if:

= O.

V 1 if quotient overflows (cannot be represented by 32 bits), 0 otherwise
The following conditions cause an overflow and set the overflow flag:
•
•

Divisor (Rs) is 0
Quotient cannot be contained within 32 bits

Example 1 This example divides the contents of register AO by the contents of register
A2, and stores the result in register AO. Note that the contents of register A2 are not affected by instruction execution.

OIVS

A2,AO

Before

AO
12345678h
EDCBA987h
EDCBA987h
12345678h
12345678h
OOOOOOOOh
OOOOOOOOh
87654321h

After

A1
87654321h
789ABCDFh
789ABCDFh
87654321h
87654321h
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh

A2
87654321h
87654321h
789ABCDFh
789ABCDFh
OOOOOOOOh
OOOOOOOOh
87654321h
87654321h

AO
D95BC60Ah
26A439F6h
D95BC60Ah
26A439F6h
12345678h
OOOOOOOOh
OOOOOOOOh
87654321h

A1
15CA1DD7h
EA35E229h
EA35E229h
15CA1DD7h
87654321h
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh

A2
87654321h
87654321h
789ABCDFh
789ABCDFh
OOOOOOOOh
OOOOOOOOh
87654321h
87654321h

NCZV
1xOO
OxOO
1xOO
OxOO
Ox01
Ox01
Ox10
Ox01

Example 2 This example divides the contents of register A1 by the contents of of register A2, and stores the result in register AO. Note that the contents of
register A2 are not affected by instruction execution.

OIVS A2,Al
Before

AO
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh

12-64

After

A1
87654321h
87654321h
789ABCDFh
789ABCDFh
87654321h
OOOOOOOOh

A2
12345678h
OEDCBA988h
OEDCBA988h
12345678h
OOOOOOOOh
OOOOOOOOh

AO
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh

A1
FFFFFFFAh
0OOOOOO6h
FFFFFFFAh
0OOOOOO6h
87654321h
OOOOOOOOh

A2
12345678h
EDCBA988h
EDCBA988h
12345678h
OOOOOOOOh
OOOOOOOOh

NCZV
1xOO
OxOO
1xOO
OxOO
Ox01
Ox01

DIVU

Divide Registers - Unsigned

Syntax

DIVU

Execution

Rd Even: Rd:Rd+1/Rs
Rd Odd: Rd/Rs -+ Rd

Instruction
Words
Description

Rs. Rd

15 14

13
0

Rd, remainder

Rd+1

DIVU performs an unsigned 32-bit or 64-bit divide. The source register
contains the 32-bit divisor. The destination register contains a 32-bit dividend or the most significant half of a 64-bit dividend, depending on
whether Rd is an odd register (for example, A1 or B3) or an even register
(for example, A8 or B2):
Rd Even

DIVU performs an unsigned divide of the 64-bit operand contained in the two consecutive registers, starting at the destination register, by the 32-bit contents of the source register. The
specified even-numbered destination register, Rd, contains the
32 MSBs of the dividend. The next consecutive register
(which is odd-numbered) contains the 32 LSBs of the dividend. The quotient is stored in the destination register, and the
remainder is stored in the following register (Rd+1). Avoid
using A 14 or B 14 as the destination register, since this overwrites the SP; the assembler issues a warning in this case.

Rd Odd

DIVU performs an unsigned divide of the 32-bit operand contained in the destination register by the 32-bit value in the
source register. The quotient is stored in the destination register; the remainder is not returned.

Rs and Rd must be in the same register file.

Machine
States

Rd Odd
37,40
5,8,
treated as normal

Normal
Rs
0
Rd ~ Rs

Status Bits

Unaffected

0 if:
•
•
•

Rd Even
37,40
5,8
5,8

Rs = 0, or
Rd is even and Rd ~ Rs, or
Quotient 'I< O.

1 if:
•

Quotient = O.

V 1 if quotient overflows (cannot be represented by 32 bits), 0 otherwise
The following conditions cause an overflow and set the overflow flag:
•

Divisor (Rs) is 0
12-65

DIVU

Divide Registers - Unsigned

•

Quotient cannot be contained within 32 bits

Example 1 This instruction divides the contents of register AO by the contents of register A2, and stores the unsigned result in register AO. Note that the
contents of register A2 are not affected by instruction execution.

DIVU ' A2,AO
Before

AO
12345678h
12345678h
OOOOOOOOh
OOOOOOOOh
87654321h

After

A1
87654321h
87654321h
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh

A2
789ABCDFh
OOOOOOOOh
OOOOOOOOh
87654321h
87654321h

AO
26A439F6h
12345678h
OOOOOOOOh
OOOOOOOOh
87654321h

A1
15CA1DD7h
87654321h
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh

A2
789ABCDFh
OOOOOOOOh
OOOOOOOOh
87654321h
87654321h

NCZV

xxOO
xx01
xx01
xx10
xx01

Example 2 This instruction divides the contents of register A1 by the contents of register A2, and stores the unsigned result in register A1. Note that the
contents of register A2 are not affected by instruction execution.

DIVU

A2,A!

Before

AO
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh

12-66

After

A1
789ABCDFh
12345678h
OOOOOOOOh
OOOOOOOOh
87654321h

A2
12345678h
OOOOOOOOh
OOOOOOOOh
87654321h
87654321h

AO
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
OOOOOOOOh

A1
0OOOOOO6h
12345678h
OOOOOOOOh
OOOOOOOOh
0OOOOOO1h

A2
12345678h
OOOOOOOOh
OOOOOOOOh
87654321h
87654321h

NCZV

xxOO
xx01
xx01
xx10
xxOO

Draw and Advance

DRAV

Syntax

DRAV Rs, Rd

Execution

COLOR1 pixels -+ *Rd
RsX + RdX -+ RdX
RsY + RdY -+ RdY

Instruction
Words

Description

15 14

DRAV writes the pixel value in the COLOR1 register to the location pointed
to by the XV address in the destination register. Following the write, the
XV address in the destination register is incremented by the value in the
source register: the X half of Rs is added to the X half of Rd, and the V half
of Rs is added to the V half of Rd. Any carry out from the lower (X) half
of the register does not propagate into the upper (V) half.
COLOR1 bits 0-15 are output on data bus lines 0-15, respectively. The
pixel data used from COLOR1 is that which aligns to the destination location, so 16-bit patterns can be implemented. Rs and Rd must be in the
same register file.

Implied
Operands

B File Registers
Register
83
84
85
86
89

Name
DPTCH

Format
Linear

OFFSET
WSTART
WEND

Linear
XY

COLOR1

Address
COOOO080h

Name
CONTROL

COOO0140h
COOO0150h

CONVDP

COOO0160h

PSIZE
PMASK

XY
Pixel

Description
Destination pitch
Screen origin (location 0,0)
Window starting corner
Window ending corner
Pixel color

I/O Registers
Description and Elements (Bits)
PP- Pixel processing operations (22 options)
W -Window checking operation
T -Transparency operation
XY-to-linear conversion (destination pitch)
Pixel size (1,2,4.8,16)
Plane mask - pixel format

Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
DRAV instruction. To ensure that this register contains the correct value for
execution, you may want to follow the write to that location with an instruction that reads the same location (such as a MOVE SAddress,Rd instruction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.

Pixel
Processing

Set the PPOP field in the CONTROL register to select a pixel processing
operation. This operation is applied to the pixel as it is moved to the destination location. At reset, the default pixel processing operation is rep/ace
(S -+ D). For more information, see Section 7.7, Pixel Processing, on page
7-15.

12-67

DRAV

Window
Checking

Draw and Advance

Select a window checking mode by setting the W bits in the CONTROL
register. If you select an active window checking mode (W = 1, 2, or 3),
the WSTART and WEND registers define the XY starting and ending corners
of a rectangular window. The X and Y values in both WSTART and WEND
must be positive.
When the TMS3401 0 attempts to write a pixel inside or outside a defined
value, the following actions may occur:

W=O No window operation. The pixel is drawn and the WVP and V bits
are unaffected.

W=1 Window hit. No pixels are drawn. The V bit is set to 0 if the pixel lies
within the window; otherwise, it is set to 1. The WVP bit is set to 1
if the pixel lies within the window; otherwise, it is not affected.

W=2 Window miss. If the pixel lies outside the window, the WVP and V
bits are set to 1 and the instruction is aborted (no pixel is drawn).
Otherwise, the pixel is drawn, the V bit is set to 0, and the WVP bit
is unaffected.

W=3 Window clip. If the pixel lies outside the window, the V bit is set to
1 and the instruction is aborted (no pixels are drawn). Otherwise,
the pixel is drawn and the V bit is set to O.
For more information, see Section 7.10, Window Checking, on page 7 -27.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
source pixels after it processes the source data. At reset, the default case
for transparency is off.
Plane Mask

The plane mask is enabled for this instruction.

Shift Register
Transfers
When this instruction is executed and the SRT bit is set. normal memory
read and write operations become SRT reads and writes. Refer to Section
9.10.2, Video Memory Bulk Initialization, on page 9-28 for more information.
Machine
States

The states consumed depend on the operation selected, as indicated below.

Window
Violation
PSIZE Replace Boolean
ADD
ADDS
SUB
SUBS MIN/MAX W=1 W=2 W=3
1,2.4,8 4+(3),10 6+(3),12 7+(3),13 7+(3),13 7+(3),13 8+(3),14 7+(3),13 5,8 3,6 5,8
16
4+(1 ),8 6+(1),10 6+(1),10 7+(1),11 7+(1),11 8+(1),12 7+(1),11
5,8 3,6 5,8
Pixel Processing Operation

Status Bits

12-68

N
G
Z
V

Unaffected
Unaffected
Unaffected
1 if a window violation occurs, 0 otherwise; unaffected if window
clipping is not used.

DRAV

Draw and Advance

Examples

These DRAV examples use the following implied operand setup.
Register File B:
DPTCH (83)
= 200h
OFFSET (84)
= 00010000h
WSTART (85) = 00100000h
= 003C0040h
WEND (86)
COLOR1 (89) = FFFFFFFFh

I/O Registers:
CONVDP = 0016h

Assume that memory contains the following values before instruction execution:
Address
00018040h
Before

Code

DRAV
DRAV
DRAV
DRAV
DRAV
DRAV
DRAV
DRAV
DRAV

Data
8888h

AI/AO
AI/AO
AI/AO
AI/AO
AI/AO
AI/AO
AI/AO
AI/AO
AI/AO

00400040h
00400020h
00400010
00400008
00400004
00400004
00400004
00400004
00400004h

After
A1

001 0001 Oh
00100010h
00100010h
001 0001 Oh
001 0001 Oh
OOOOFFFFh
FFFFOOOOh
00010001h
00400004h

PSIZE PP

PMASK AO

0001h
0002h
0004h
0008h
0010h
0010h
0010h
0010h
0010h

00
00
00
00
00
00
00
11
00

OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
OOFFh

00000
00000
00000
00000
00000
01010
10011
00000
00000

00500050h
00500030h
00500020h
00500018h
00500014h
00400003h
003FOO04h
0041 0005h
00800008h

@18040h

a889h
888Bh
888Fh
88FFh
FFFFh
OOOOh
OOOOh
OOOOh
FFOOh

12-69

DSJ

Decrement Register and Skip Jump

Syntax

DSJ

Execution

Rd - 1 -+ Rd
IfRd ¢ O.then (offset x 16) + PC' -+ PC
If Rd = O. then go to next instruction

Instruction
Words

Rd. Address

15 14 13 12 11

000

2
Rd

offset

Description

DSJ decrements the contents of the destination register by 1. Depending
on the decremented value of Rd. the TMS3401 0 either jumps or skips the
jump:
•

Rd - 1

The TMS3401 0 jumps. The current PC points to the instruction word
that immediately follows the second word of the DSJ instruction. The
signed word offset is converted to a bit offset by multiplying by 16.
The new PC address is then obtained by adding the resulting signed
offset (offset x 16) to the address of the next instruction.
•

Rd - 1

The TMS3401 0 skips the jump and continues and program execution
with the next sequential instruction.
The Address operand is a 32-bit address. The assembler calculates the
offset as (Address - PC')/16; this results in a jump range of -32.768 to
+32.767 words. (The offset is the second instruction word of the opcode.)
The DSJ instruction is useful for large loops involving a counter.
shorter loops. the assembler translates this into a DSJS instruction.

Machine
States
Status Bits

3.9 (Jump)
2.8 (No jump)
N

C
Z

Examples

12-70

Unaffected
Unaffected
Unaffected
Unaffected

Code

Before

After

DSJ A5,LOOP
DSJ A5,LOOP
DSJ A5,LOOP

00000009h
00000001h

00000008h

OOOOOOOOh

FFFFFFFFh

Jump taken?

Yes
No
Yes

For

Conditionally Decrement Register
and Skip Jump

Syntax

DSJ EQ

Execution

If Z = 1.
If
If
If Z = 0,

Instruction
Words

DSJEQ

Rd. Address
then Rd - 1 -+ Rd
Rd ¢ 0, then PC' + (offsetx16) -+ PC
Rd = 0, then go to next instruction
then go to next instruction

15 14 13 12
000

4
R

2
Rd

offset

Description

The DSJ EO instruction evaluates the status Z bit. Depending on the value
of that bit, the TMS3401 0 either skips the jump, or decrements Rd and then
makes a decision to jump or skip the jump:

•

Z = 1
The TMS34010 decrements the contents of the destination register
by 1.

Rd - 1

The TMS34010 jumps relative to the current PC. The current
PC points to the instruction word that immediately follows the
second word of the DSJEO instruction. The signed word offset
is converted to a bit offset by multiplying by 16. The new PC
address is then obtained by adding the resulting signed offset
(offset x 16) to the address of the next instruction.

Rd - 1

The TMS34010 skips the jump and continues program execution at the next sequential instruction.
•

The TMS3401 0 skips the jump and continues program execution at
the next sequential instruction.
The Address operand is a 32-bit address. The assembler calculates the
offset as (Address - PC')/16; this results in a jump range of -32.768 to
+32,767 words. (The offset is the second instruction word of the opcode.)
You can use this instruction after an explicit or implicit compare to O. Additional information on these types of compares can be obtained in the
CMP and CMPI. and MOVE-to-register instructions, respectively.

Machine
States
Status Bits

3,9 (Jump)
2,8 (No jump)
N
C
Z
V

Unaffected
Unaffected
Unaffected
Unaffected

12-71

Conditionally Decrement Register
and Skip Jump

DSJEQ

Examples

Before
A5

DSJEQ
DSJEQ
DSJEQ
DSJEQ
DSJEQ
DSJEQ

12-72

A5,LOOP
A5,LOOP
A5,LOOP
A5,LOOP
A5,LOOP
A5,LOOP

00000009h
00000001h

OOOOOOOOh

00000009h
00000001h

OOOOOOOOh

After
NCZV

xx1x
xx1x
xx1x
xxOx
xxOx
xxOx

Jump taken?

00000008h

OOOOOOOOh

FFFFFFFFh
00000009h
00000001h

OOOOOOOOh

Yes
No
Yes
No
No
No

Conditionally Decrement Register
and Skip Jump

Syntax

DSJNE

Execution

If Z = 0,
If
If
If Z = 1,

Instruction
Words

Rd, Address
then Rd - 1 -+ Rd
Rd ¢ 0, then PC' + (offset x 16) -+ PC
Rd = 0, then go to next instruction
then to to next instruction

15 14 13 12 11

DSJNE

aiR

2
Rd

offset

Description

The DSJ N E instruction evaluates the status Z bit. Depending on the value
of that bit, the TMS3401 0 either skips the jump, or decrements Rd and then
makes a decision to jump or skip the jump:

•

= 0,

The TMS34010 decrements the contents of the destination register
by 1.
Rd - 1

The TMS34010 jumps relative to the current PC. The current
PC points to the instruction word that immediately follows the
second word of the DSJNE instruction. The signed word offset
is converted to a bit offset by multiplying by 16. The new PC
address is then obtained by adding the resulting signed offset
(offset x 16) to the address of the next instruction.

Rd - 1

The TMS34010 skips the jump and continues program execution at the next sequential instruction.
•

Z = 1
The TMS3401 0 skips the jump and continues program execution at
the next sequential instruction.

The Address operand is a 32-bit address. The assembler calculates the
offset as (Address - PC')/16; this results in a jump range of -32,768 to
+32,767 words. (The offset is the second instruction word of the opcode.)
You can use this instruction after an explicit or implicit compare to O. Additional information on these types of compares can be obtained in the
CMP, CMPI, and MOVE-to-register instructions.

Machine
States
Status Bits

3,9 (Jump)
2,8 (No jump)
N
C
Z

Unaffected
Unaffected
Unaffected
Unaffected

12-73

Conditionally Decrement Register
and Skip Jump

DSJNE

Examples

Before
A5

DSJNE
DSJNE
DSJNE
DSJNE
DSJNE
DSJNE

12-74

A5,LOOP
A5,LOOP
A5,LOOP
A5,LOOP
A5,LOOP
A5,LOOP

00000009h
00000001h

OOOOOOOOh

00000009h
00000001h

OOOOOOOOh

After
NCZV

xx1x
xx1x
xx1x
xxOx
xxOx
xxOx

Jump taken?

00000009h
00000001 h

OOOOOOOOh

No
No
No

00000008h

Yes

FFFFFFFFh

Yes

OOOOOOOOh

Decrement Register and Skip Jump - Short

Syntax

DSJS

Execution

Rd - 1 -+ Rd
If Rd ¢ 0, then PC' + (offsetx16) -+ PC
If Rd = 0, then go to next instruction

Instruction
Words

Rd, Address

15 14

DSJS

ID I

2
Rd

offset

Fields

Description

DSJS decrements the contents of the destination register by 1. Depending
on the result, the TMS3401 0 either jumps or skips the jump:

is a 1 -bit direction bit (from PC' to Address):
D=O - forward jump
D=1 - backward jump

•

Rd - 1

The TMS34010 jumps relative to PC'. PC' points to the instruction
word that immediately follows the DSJS instruction. Internally, the
5-bit offset is multiplied by 16 to convert it to a bit offset. This allows
a jump range of -30 to +32 words from the PC.

If direction bit D

The new PC address is obtained by adding the resulting offset
to PC'.

If direction bit D

The new PC address is obtained by subtracting the resulting
offset from PC'.
•

Rd - 1

The TMS34010 skips the jump and continues program execution at
the next sequential instruction.
The Address operand is a 32-bit address. The assembler calculates the
offset as (Address - PC'}/16; this results in a jump range of -30 to +32
words from the PC. (The offset is encoded as part of the instruction word.)
This instruction is useful for coding tight loops for cache-resident routines.

Machine
States
Status Bits

2,5 (Jump)
3,6 (No jump)
N

C
Z

Examples

Unaffected
Unaffected
Unaffected
Unaffected

Code
DSJS A5,LOOP
DSJS A5,LOOP
DSJS A5,LOOP

Before

After

00000009h
00000001h

00000008h

OOOOOOOOh

OOOOOOOOh
FFFFFFFFh

Jump taken?

Yes
No
Yes
12-75

EINT

Enable Interrupts

Syntax

EINT

Execution

Instruction
Words
Description

15 14
0
0

13
0

12
0

7
0

Status Bits

3,6
N
C
Z
V
IE

Unaffected
Unaffected
Unaffected
Unaffected
1

Examples

Before
EINT
EINT

12-76

4
0

3
0

2
0

0
0

EINT sets the global interrupt enable bit (IE) to 1, allowing interrupts to be
enabled. When IE=1, individual interrupts are enabled by setting the appropriate bits in the INTENB interrupt mask register. The rest of the status
register is unaffected.
The DINT instruction disables interrupts.

Machine
States

After

00000010h
00200010h

00200010h
00200010h

EMU

Initiate Emulation
Syntax

EMU

Execution

Instruction
Words

15 14

1 0

Description

Machine
States
Status Bits

Rd and conditionally enter emulator mode

0
0

The EMU instruction pulses the EMUA pin and samples the RUN/EMU pin.
Ifthe RUN/EMU pin is in the RUN state, the EMU instruction acts as a NOP.
If the pin is in the EMU state, emulation mode is entered. This instruction
is not intended for general use; refer to the TMS34010 XDS/22 User's
Guide for more information.
8,11 (or more if EMU mode is entered)

N
C
Z
V

Indeterminate
Indeterminate
Indeterminate
Indeterminate

12-77

EXG F

Exchange Field Definition

Syntax

EXGF Rd [, F}

Execution

Ad .... FSO, FEO or Ad .... FS1, FE1
FSO, FEO .... Ad or FS1, FE1 .... Ad

Instruction
Words

15 14

11
Description

1F 1

2
Rd

EXGF exchanges the six LSBs of the destination register with the selected
six bits of field information (field size and field extension). Bit 5 of the 6-bit
quantity in Rd is exchanged with the field extension value. The upper 26
bits of Ad are cleared.

Status Register
EXGF's F parameter is optional:
F=O selects FSO, FEO to be exchanged
F=1 selects FS1, FE1 to be exchanged
If you do not specify an F parameter, the default is O.

Status Bits

N
C
Z
V

Unaffected
Unaffected
Unaffected
Unaffected

Examples

Before
EXGF A5,O
EXGF A5,l

12-78

After

FFFFFFCOh
FFFFFFCOh

FOOOOFFFh
FOOOOFFFh

0000003Fh
0000003Fh

FOOOOFCOh
F000003Fh

Exchange Program Counter

Syntax

EXGPC

Execution

Instruction
Words
Description

PC, PC'

EXGPC

15 14

EXGPC exchanges the next program counter value with the destination register contents. After this instruction has been executed, the destination
register contains the address of the instruction immediately following the
EXGPC instruction.
Note that the TMS34010 sets the four LSBs of the program counter to 0
(word aligned).
This instruction provides a "quick call" capability by saving the return address in a register (rather than on the stack). The return from the call is
accomplished by repeating the instruction at the end of the "subroutine."
Note that the subroutine address must be reloaded following each callreturn operation.

Machine
States

2,5

Status Bits

N
C
Z
V

Examples

Code

Unaffected
Unaffected
Unaffected
Unaffected

EXGPC Al
EXGPC Al

Before

After

00001C10h
00001C50h

00002080h
00002080h

00002090h
00002090h

00001C10h
00001C50h

12-79

Fill Array with Processed Pixels - Linear

FILL
Syntax

FILL

Execution·

COLOR1 pixels

Instruction
Words
Description

L
-+

15 14

pixel array (with processing)
11

FILL processes a set of source pixel values (specified by the COLOR1 register) with a destination pixel array.
This instruction operates on a two-dimensional array of pixels using pixels
defined in the COLOR1 register. As the FILL proceeds, the source pixels
are combined with destination pixels based on the selected graphics operations.
Note that the L parameter in the instruction syntax does not represent a
value or a register - the L is entered as part of the instruction and identifies
the starting address of the pixel array as an L address. That is, the instruction is entered as FILL L.
The following set of implied operands govern the operation of the instruction and define both the source pixels and the destination array.

Implied
Operands
Register
82t
83
87
89
81Q-814t
Address
COOOO080h
COOO0150h
COOO0160h
t Changed by

Destination
Array

Due to the pipelining of memory writes, the last 1/0 register that you write
to may not, in some cases, contain the desired value when you execute the
FILL instruction. To ensure that this register contains the correct value for
execution, you may want to follow the write to that location with an instruction that reads the same location (such as a MOVE SAddress,Rd instruction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
The contents of the DAD DR, DPTCH, and DYDX registers define the location of the destination pixel array:
•

12-80

B File Registers
Description
Format
Linear
Pixel array starting address
Pixel array pitch
Linear
XY
Pixel array dimensions (rows:columns)
Pixel
Fill color or 16-bit pattern
Reserved registers
I/O Registers
Description and Operations
Name
CONTROL
PP- Pixel processing operations (22 options)
T - Transparency operation
PSIZE
Pixel size (1,2,4,8,16)
PMASK
Plane mask - pixel format
FILL during execution.
Name
DADDR
DPTCH
DYDX
COLOR1

At the outset of the instruction, DADDR contains the linear address
of the pixel with the lowest address in the array.

FILL

Fill Array with Processed Pixels - Linear

During instruction execution, DADDR points to the next pixel (or
word of pixels) to be modified in the destination array. When the array transfer is complete, DADDR points to the linear address of the
pixel following the last pixel written.

Pixel
Processing

•

DPTCH contains the linear difference in the starting addresses of adjacent rows of the destination array. DPTCH must be a multiple of
16, except when a single pixel-width line is drawn (DY=1). In this
case, DPTCH may be any value.

•

DYDX specifies the dimensions of the destination array in pixels. The
DY portion of DYDX contains the number of rows in the array, while
the OX portion contains the number of columns.

Set the PPOP field in the CONTROL register to select a pixel processing
operation. This operation is applied to the pixel as it is moved to the destination location. There are 16 Boolean and
arithmetic operations; the
default operation at reset is rep/ace (S -+ D). Note that the destination data
is read through the plane mask and then processed. The 6 arithmetic operations do not operate with pixel sizes of one or two bits per pixel. For
more information, see Section 7.7, Pixel Processing, on page 7 -15.

Window
Checking

Window checking cannot be used with this instruction. The contents of
the WSTART and WEND registers are ignored.

Corner Adjust There is no corner adjust for this instruction. The direction of the FILL is
fixed as increasing linear addresses.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
source pixels after it processes the source data. At reset, the default case
for transparency is off.
Interrupts

This instruction can be interrupted at a word or row boundary of the destination array. When the FILL is interrupted, the TMS3401 0 sets the PBX
bit in the status register and then pushes the status register on the stack.
At this time, DPTCH and B1 o-B14 contain intermediate values. DADDR
points to the linear address of the next word of pixels to be modified after
the interrupt is processed.
Before executing the RETI instruction to return from the interrupt, restore
any B-file registers that were modified (also restore the CONTROL register
if it was modified). This allows the TMS34010 to resume the FILL correctly.

Plane Mask

The plane mask is enabled for this instruction.

Shift Register
Transfers
If the SRT bit in the DPYCTL register is set. each memory read or write initiated by the FI LL generates a shift register transfer read or write cycle at
the selected address. This operation can be used for bulk memory clears
or transfers. (Not all VRAMs support this capability.) See Section 9.10.2,
Video Memory Bulk Initialization, on page 9-28 for more information.
Machine
States

See Section 13.3, FILL Instructions Timing.
12-81

FILL

Status Bits

Fill Array with Processed Pixels - Linear

C
Z
V

Examples

Unaffected
Unaffected
Unaffected
Unaffected

These FILL examples use the following implied operand setup.
Register File B:
DADDR (B2)
= 00002010h
= 00000080h
DPTCH (B3)
DYDX (B7)
= 0002000Dh
COLOR1 (B9) = 30303030h

I/O Registers:
PSIZE
= 0008h

Assume that memory contains the following values before instruction execution.
Linear
Data
Address
02000h 1100h, 3322h, 5544h, 7766h, 9988h, BBAAh,DDCCh, FFEEh
02080h 1100h, 3322h, 5544h, 7766h, 9988h, BBAAh,DDCCh, FFEEh

Example 1

This example uses the pixel processing replace (5 -+ D) operation. Before
instruction execution, PMASK = OOOOh and CONTROL = OOOOh (T=O,
PP=OOOOO).
After instruction execution, memory contains the following values:
Linear
Data
Address
02000h 1100h, 3030h, 3030h, 3030h, 3030h, 3030h, 3030h, FF30h
02080h 1100h, 3030h, 3030h, 3030h, 3030h, 3030h, 3030h, FF30h

Example 2

This example uses the (S and D) -+ D pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = 2COOh (T=O,
PP=01010).
After instruction execution, memory contains the following values:
Linear
Data
Address
02000h 1100h, 0302h, 4544h, 4746h, 8988h, 8B8Ah, CDCCh,FFCEh
02080h 1100h, 0302h, 4544h, 4746h, 8988h, 8B8Ah, CDCCh,FFCEh

Example 3

This example uses transparency and the (5 and D) -+ D pixel processing
operation. Before instruction execution, PMASK = OOOOh and CONTROL
= 0420h (T=1, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear
Data
Address
02000h 1100h, 3020h, 1044h, 3020h, 1088h, 3020h, 10CCh, FF20h
02080h 1100h, 3020h, 1044h, 3020h, 1088h, 3020h, 10CCh, FF20h

12-82

Fill Array with Processed Pixels - Linear

Example 4

FILL

This example uses plane masking - the four MSBs are masked. Before instruction execution, PMASK = OFOFOh and CONTROL = OOOOh (T=O,
PP=OOOOO).
After instruction execution, memory contains the following values:
Linear
Data
Address
02000h 1100h, 3020h, 5040h, 7060h, 9080h, BOAOh, DOCOh, FFEOh
02080h 1100h, 3020h, 5040h, 7060h, 9080h, BOAOh, DOCOh, FFEOh

12-83

Fill Array with Processed Pixels - XY

FILL
Syntax

FILL XV

Execution

COLOR1 pixels

Instruction
Words

15 14
10

Description

pixel array (with processing)
11

o
o

FILL processes a set of source pixel values (specified by the COLOR1 register) with a destination pixel array.
This instruction operates on a two-dimensional array of pixels using pixels
defined in the COLOR1 register. As the FILL proceeds, the source pixels
are combined with destination pixels based on the selected graphics operations.
Note that the XV parameter in the instruction syntax does not represent a
value or a register - it is entered as part of the instruction and identifies the
starting address of the pixel array as an XV address. That is, the instruction
is entered as FILL L, XY.
The following set of implied operands govern the operation of the instruction and define both the source pixels and the destination array.

Implied
Operands

B File Registers
Format
Description
XY
Pixel array starting address
Linear
Pixel array pitch
Screen origin (address of O,O)
Linear
XY
Window starting corner
XY
Window ending corner
Pixel array dimensions (rows:columns)
XY
Fill color or l6-bit pattern
Pixel
Reserved registers
1/0 Registers
Address
Name
Description and Elements (Bits)
CONTROL
PP- Pixel processing operations (22 options)
COOOOOBOh
W - Window checking operation
T - Transparency operation
XY-to-linear conversion (destination pitch)
COOO0140h
CONVDP
COOOO150h
PSIZE
Pixel size (1 ,2,4,S,16)
Plane mask - pixel format
COOOO160h
PMASK
t Changed by FILL dUring execution.
:/: Used for common rectangle function with window hit operation (W=l).
Register
B2"N:
B3
B4
B5
B6
B7"N:
B9
Blo-B14t

Name
DADDR
DPTCH
OFFSET
WSTART
WEND
DYDX
COLOR1

12-S4

Fill Array with Processed Pixels - XY

Destination
Array

Pixel
Processing

Window
Checking

FILL

The location of the destination pixel array is defined by the contents of the
DADDR, DPTCH, CONVDP, OFFSET, and DYDX registers. At the outset
of the instruction, DADDR contains the XV address of the pixel with the
lowest address in the array. It is used with OFFSET and CONVDP to calculate the linear address of the starting location of the array. DPTCH contains the linear difference in the starting addresses of adjacent rows of the
destination array (typically this is the screen pitch). DPTCH must be a
power of two (greater than or equal to 16) and CONVDP must be set to
correspond to the DPTCH value. CONVDP is computed by operating on
the DPTCH register with the LMO instruction; it is used for the XY calculations involved in XY addressing and window clipping. DYDX specifies
the dimensions of the destination array in pixels. The DY portion of DYDX
contains the number of rows in the array, while the DX portion contains the
number of columns. During instruction execution, DADDR points to the
next pixel (or word of pixels) to be modified in the destination array. When
the array transfer is complete, DADDR points to the linear address of the
pixel following the last pixel written. This is that pixel on the last row that
would have been written had the array transfer been wider in the X dimension.
Pixel processing can be used with this instruction. The PPOP field of the
CONTROL register specifies the pixel processing operation that is applied
to pixels as they are processed with the destination array. There are 16
Boolean and 6 arithmetic operations; the default case at reset is the replace
(5 -+ D) operation. Note that the destination data is read through the plane
mask and then processed. The 6 arithmetic operations do not operate with
pixel sizes of one or two bits per pixel. For more information, see Section
7.7, Pixel Processing, on page 7-15.
The window operations described in Section 7.10, Window Checking, on
page 7-27. can be used with this instruction. You can select window pick,
violation detect, or preclipping by setting the W bits in the CONTROL register to 1, 2, or 3, respectively. Window pick modifies the DADDR and
DYDX registers to correspond to the common rectangle formed by the
destination array and the clipping window defined by WSTART and WEND.
DADDR is set to the XY address of the pixel with the lowest address in the
common rectangle, while DYDX is set to the X and Y dimensions of the
rectangle. If no window operations are selected, the WSTART and WEND
registers are ignored. At reset no window operations are enabled.

12-85

FILL

Fill Array with Processed Pixels - XY

Before executing the RETI instruction to return from the interrupt, restore
any B-file registers that were modified (also restore the CONTROL register
if it was modified). This allows the TMS3401 0 to resume the FILL correctly.
Plane Mask

The plane mask is enabled for this instruction.

Shift Register
Transfers
If the SRT bit in the DPYCTL register is set, each memory read or write initiated by the FILL generates a shift register transfer read or write cycle at
the selected address. This operation can be used for bulk memory clears
or transfers. (Not all VRAMs support this capability.) See Section 9.10.2,
Video Memory Bulk Initialization, on page 9-28 for more information.
Machine
States

See Section 13.3, FI LL Instructions Timing.

Status Bits

N
C
Z
V

Examples

These FILL examples use the following implied operand setup.

Unaffected
Unaffected
Unaffected
1 if a window violation occurs, 0 otherwise; unaffected if window
clipping is not enabled

Register File B:
DADDR (B2)
= 00520007h
DPTCH (B3)
= 00000100h
OFFSET (B4)
= 00010000h
WSTART (B5) = 0030000Ch
WEND (B6)
= 00530014h
DYDX (B7)
= 00030012h
COLOR1 (B9) = FFFFFFFFh

I/O Registers:
CONVDP
= 0017h
PSIZE
= 0004h
PMASK
= OOOOh
CONTROL = OOOOh
(W=OO, T=O, PP=OOOOO)

Assume that memory contains the following values before instruction execution.

Linear
Data
Address
15200h 3210h, 7654h, BA98h, FEDCh, 321 Oh, 7654h, BA98h, FEDCh
15300h 3210h, 7654h, BA98h, FEDCh, 321 Oh, 7654h, BA98h, FEDCh
15400h 3210h, 7654h, BA98h, FEDCh, 321 Oh, 7654h, BA98h, FEDCh
Example 1

This example uses the replace (S -+ D) pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = OOOOh (T=O,
W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:

Linear
Data
Address
15200h 3210h, F654h, FFFFh, FFFFh, FFFFh, FFFFh, BA9Fh, FEDCh
15300h 3210h, F654h, FFFFh, FFFFh, FFFFh, FFFFh, BA9Fh, FEDCh
15400h 3210h, F654h, FFFFh, FFFFh, FFFFh, FFFFh, BA9Fh, FEDCh

12-86

Fill Array with Processed Pixels - XY

FILL

XV Addressing
X Address

000 0 0 0 0 0 0 000 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 111
0123456789ABCDEF0123456789ABCDEF

d 52 0 1 2 3 4 5 6 F F F F F F F F F F F F F F F F F F 9 ABC D E F
d

r 53 0 1 2 3 4 5 6 F F F F F F F F F F F F F F F F F F 9 ABC D E F
e
s 540123456FFFFFFFFFFFFFFFFFF9ABCDEF
s
Example 2

This example uses the (0 XOR S) -+ 0 pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = 2800h (T=O,
W=OO, PP=01 01 0).
After instruction execution, memory contains the following values:

X Address

0 0 0 0 0 0 0 0 0 0 0 000 001 1 1 1 1 1 1 1 1 111 1 111
0123456789ABCDEF0123456789ABCDEF

d 52012345687654321 OFEDCBA9879ABCDEF
d

r 53012345687654321 OFEDCBA9879ABCDEF
e
s ~ 0123456876543210FEDCBA9879ABCDEF
s
Example 3

This example uses transparency, the (0 subs S) -+ 0 pixel processing operation. Before instruction execution, COLOR1 = 88888888h, PMASK =
OOOOh, and CONTROL = 4C20h (T=1, W=OO, PP=1 0011).
After instruction execution, memory contains the following values:
X Address

000 0 0 000 0 0 0 0 0 0 0 0 1 1 111 1 1 1 1 111 111 1
0123456789ABCDEF0123456789ABCDEF

d 52 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 ABC D E F
d

r 5301234567812345670123456789ABCDEF
e
s 5401234567812345670123456789ABCDEF
s

12-87

FILL

Example 4

Fill Array with Processed Pixels - XY

This example uses window operation 3 - the destination is clipped. Before
instruction execution, PMASK = OOOOh and CONTROL = OOCOh (T=O,
W=11, PP=OOOOO).
After instruction execution, memory contains the following values:
X Address

0 0 0 0 0 0 0 000 0 0 0 0 0 0 1 1 111 1 1 1 1 1 111 111
0123456789ABCDEF0123456789ABCDEF

d 520123456789ABFFFFFFFFF56789ABCDEF
d
r

530123456789ABFFFFFFFFF56789ABCDEF
e
s 540123456789ABCDEF0123456789ABCDEF
s

Example 5

This example uses plane masking - the most significant bit is masked. Before instruction execution, PMASK = 8888h and CONTROL = OOOOh
(T=O, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:

X Address

00000000000000001111111111111111
0123456789ABCDEF0123456789ABCDEF

d 5201234567FFFFFFFF77777777F9ABCDEF
d
r

5301234567FFFFFFFF77777777F9ABCDEF
e
s 5401234567FFFFFFFF77777777F9ABCDEF
s

12-88

Get Program Counter into Register
Syntax

GETPC Rd

Execution

PC'

Instruction
Words

15 14

Description

Machine
States

GETPC

GETPC increments the PC contents by 16 to point past the GETPC instruction, and copies the value into the destination register. Execution
continues with the next instruction. You can use GETPC with the EXGPC
and JUMP instructions for quick call on jump operations. You can also use
GETPC to access relocatable data areas whose position relative to the code
area is known at assembly time.
1,4

Status Bits

N
C
Z
V

Examples

Code

Before
PC

GETPC Al
GETPC Al

00001 BDOh
00001C10h

00001 BEOh
00001C20h

Unaffected
Unaffected
Unaffected
Unaffected
After

12-89

GETST

Get Status Register into Register

Syntax

GETST

Execution

Instruction
Words

15 14 13 12 11
0

1 0

Description

01 R

1,4

Status Bits

N
C
Z
V

Examples

Code

Before

After

GETST Al
GETST Al

20200010h
00000010h

12-90

0
Rd

GETST copies the contents of the status register into the destination register.

Status Register

Machine
States

Unaffected
Unaffected
Unaffected
Unaffected

INC

Increment Register

Syntax

INC

Execution

Rd + 1

Instruction
Words
Description

Rd
-+

15 14 13 12 11

4
R

0
Rd

INC adds 1 to the contents of the destination register and stores the result
in the destination register. This instruction is an alternate mnemonic for
ADDK 1,Rd.

You can accomplish multiple-precision arithmetic by using INC in conjunction with the ADDC instruction.

Machine
States

1,4

Status Bits

N
C
Z
V

Examples

Code
INC
INC
INC
INC
INC

1
1
1
1

if
if
if
if

Al
Al
Al
Al
Al

the result is negative, 0 otherwise
there is a carry, 0 otherwise
the result is 0, 0 otherwise
there is an overflow, 0 otherwise

Before

After

NCZV

OOOOOOOOh
OOOOOOOFh
FFFFFFFFh
FFFFFFFEh
7FFFFFFFh

00000001h
00000010h
OOOOOOOOh
FFFFFFFFh
80000000h

0000
0000
0110
1000
1001

12-91

JAcc

Jump Absolute Conditional

Syntax

JAcc Address

Execution

If condition· true, then Address -+ PC
If condition false, then go to next instruction

Instruction
Words

15 14 13
1
1
0

10 9
8
7
6
5
code
0
0
I 1
16 LSBs of Address
16 MSBs of Address

4
0

3
0

2
0

o
0

Fields

code

Description

The JAcc instruction conditionally jumps to an absolute address. The cc
is part of a mnemonic that represents the condition for the jump; for example, if cc is UC, then the instruction is JAUC. (See the condition mnemonics and codes listed below.) If the specified condition is true, the
TMS34010 jumps to the address and continues execution from that point.
If the specified condition is false, the TMS3401 0 skips the jump and continues execution at the next sequential instruction. Note that the lower four
bits of the program counter are set to 0 (word aligned).

is a 4-bit digit that identifies the condition for the jump within
the opcode. (See the condition codes table below.)

The Address operand in the syntax represents the 32-bit absolute address.
Note that the second and third instruction words contain the address for the
jump.
The JAcc instructions are usually used in conjunction with the CMP and
CMPI instructions. The JAV and JANV instructions can also be used to
detect window violations or CPW status.
Condition
Codes
Unconditional
Compares
Unsigned
Compares

Signed
Compares

Compare to
Zero

12-92

Result of Compare
Unconditional

Dst lower than Src

Mnemonic
JAUC
JALO
(JAC)
JALS
JAHI
JAHS
JANC
JAEQ
(JAZ)
JANE
(JANZ)
JALT
JALE
JAGT
JAGE
JAEQ
(JAZ)
JANE
(JANZ)
JAZ
JANZ
JAP
JAN
JANN

JAYLE
JAYGT

Dst lower or same as Src
Dst higher than Src
Dst higher or same as Src

0001

C+Z
CoZ
C

0010
0011
1001

= Src

1010

Src

1011

(N 03) +_( NoV)
{N 0 V_+ (N ":-V) .:!: Z _
(N 0 V 0 Z) + (N 0 y.. 0 Z)
(N 0 V) + (N 0 V)
Z

0100
0110
0111
0101
1010

1011

Z
Z
NoZ
N
N

0101
1011
0001
1110
1111

JAYZ
JAYNZ

Result = zero
Result ¢ zero
Result is positive
Result is negative
Result is nonnegative

JAXZ
JAXNZ

Dst

Dst < Src
Dst S Src
Dst > Src
Dst> Src
Dst -;;;- Src

Code
0000

Dst

-JAXGT
-

JAXLE

Status Bits
don't care

Dst

Src

Jump Absolute Conditional

JAcc

Condition
Codes
(continued)

Result of Compare
Result is zero
Result is nonzero
Carry set on resu It
No carryon result
Borrow set on result

Mnemonic

General JAZ JAYZ
Arithmetic JANZ JAYNZ

Status Bits
Z

Code
1010
1011
1000
1001
1000

C
JAC JAYN
JANC JAYNN
C
JAB
C
(JAC)
No borrow on result
C
JANB
JANC
JAVt JAXN
Overflow on result
V
JANVt JAXNN No overflow on result
'ii
Note: A mnemonic code In parentheses IS an alternate code for the preceding code.
t Also used for window clipping
+ Logical OR
.: Logical AND
Logical NOT

Machine
States

3,6
4,7

(Jump)
(No jump)

Status Bits

N
C
Z
V

Unaffected
Unaffected
Unaffected
Unaffected

Examples

Code

Flags for Branch
NCZV

JAUC
JAP
JALS
JAHI
JALT
JAGE
JALE
JAGT
JAC
JANC
JAZ

HERE
HERE
HERE
HERE
HERE
HERE
HERE
HERE
HERE
HERE
HERE

Note that the

NCZV

Code

NCZV

xxxx
JAV HERE
OxOx
JANZ HERE
xx1x x1xx
JANN HERE
JANV HERE
xOOx
Oxx1 1xxO
JAN HERE
OxxO 1 xx1
JAB HERE
Oxx1 1xxO xx1x JANB HERE
JALO HERE
OxOO 1 x01
x1xx
JAHS HERE
xOxx
JANE HERE
JAEQ HERE
xx1x
TMS34010 jumps when anyone or

1001
1100
1101

Flags for Branch
NCZV

NCZV NCZV

xxx1
xxOx
Oxxx
xxxO
1xxx
x1xx
xOxx
x1xx
xOOx xx1 x
xxOx
xx1x
more of the Flags for

Branch listed above are set as indicated.

12-93

Jump Relative Conditional - ± 127 Words

JRcc

Syntax

JRcc Address

EXBcution

If condition true, then offset + PC' -+ PC
If condition false, then go to next instruction

Instruction
Words

15 14

code

offset

Fields

code

Description

The J Rcc instruction conditionally jumps to an address that is relative to the
current PC. The cc is part of a mnemonic that represents the condition for
the jump; for example, if cc is UC, then the instruction is JAUC. (See the
condition mnemonics and codes listed below.) If the specified condition
is true, the TMS3401 0 jumps to a new location. The assembler calculates
the address of this location by adding the address of the next instruction
(PC') to the signed word offset. The TMS3401 0 then continues execution
from this point. If the specified condition is false, the TMS3401 0 skip the
jump and continues execution at the next sequential instruction.

is a 4-bit digit that identifies the condition for the jump within
the opcode. (See the condition codes table below.)

The Address operand in the syntax represents the 32-bit relative address.
The assembler calculates the offset as (Address - PC') /16 and inserts the
resulting 8-bit offset into the opcode. The range for this form of the J Rcc
instruction is ±127 words (excluding 0).
If the offset is outside the range of ±127 words, the assembler automatically substitutes the longer form of the JRcc instruction. If the offset is 0,
the assembler substitutes a NOP instruction. The assembler does not accept an address which is externally defined or an address which is relative
to a different section than the PC. Note that the four LSBs of the program
counter are always 0 (word aligned).
The JRcc instructions are usually used in conjunction with the CMP and
CMPI instructions. The JRV and JRNV instructions can also be used to
detect window violations or CPW status.

Condition
Codes
Unconditional
Compares
Unsigned
Compares

Mnemonic
JRUC

JRLO
(JRC)
JRLS JRYLE
JRHI JRYGr
JRHS
JRNC
JREQ
(JRZ)
JRNE
(JRNZ)

12-94

Result of Compare
Unconditional

Status Bits
don't care

Code

0001

C·z

C+Z

0010
0011
1001

Ost = Src

1010

Ost ¢ Src

1011

Ost lower than Src
Ost lower or same as Src
Ost higher than Src
Ost higher or same as Src

0000

Jump Relative Conditional - ±127 Words

JRcc

Condition
Codes
(continued)
Signed
Compares

Mnemonic
JRLT JRXLE
JRLE
JRGT
JRGE JRXGT
JREG
(JRZ)
JRNE
(JRNZ)

Result of Compare
Dst < Src
Dst :S Src
Dst> Src
Dst> Src
Dst ~ Src

Compare to
Zero

JRZ
JRNZ
JRP
JRN
JRNN
General
JRZ
Arithmetic JRNZ
JRC
JRNC
JRB
(JRC)
JRNB
JRNC
JRVt
JRNVt

Status Bits
(N ·_V) "t-( N • V)
(N • V_+ (N :_y).:!: Z_
(N • V • Z) + ( N . Y.. • Z)
(N • V) + (N • V)
Z

Code
0100
0110
0111
0101
1010

1011

0101
1011
0001
1110
1111
1010
1011
1000
1001
1000

No borrow on result

1001

Overflow on result
No overflow on result

1100
1101

Dst ¢ Src
Result = zero
Result ¢ zero
Result is positive
Result is negative
Result is nonnegative
Result is zero
Result is nonzero
Carry set on result
No carryon resu It
Borrow set on resu It

JRYZ
JRYNZ

JRXZ
JRXNZ
JRYZ
JRYNZ
JRYN
JRYNN

JRXN
JRXNN

Z
N·Z
N

N
Z

Z
C

Note: A mnemonic code in parentheses is an alternate code for the preceding code.
t Also used for window clipping
+ Logical OR
..:. Logical AND
Logical NOT

Machine
States
Status Bits

2,5 (Jump)
1,4 (No jump)
N
C
Z

Examples

Unaffected
Unaffected
Unaffected
Unaffected
Flags for Branch

Code

NCZV

JRUC
JRP
JRLS
JRHI
JRLT
JRGE
JRLE
JRGT

HERE
HERE
HERE
HERE
HERE
HERE
HERE
HERE

xxxx
OxOx
xx1x
xOOx
Oxx1
OxxO
Oxx1
OxOO

NCZV

x1xx
1xxO
1 xx1
1xxO
1 x01

Flags for Branch

Code

NCZV

xx1x

JRC
JRNC
JRZ
JRNZ
JRV
JRNV
JRN
JRNN

HERE
HERE
HERE
HERE
HERE
HERE
HERE
HERE

NCZV

x1xx
xOxx
xx1x
xxOx
xxx1
xxxO
1xxx
Oxxx

Note that the TMS34010 jumps when anyone or more of the Flags for
Branch listed above are set as indicated.

12-95

JRcc

Jump Relative Conditional - ±32K Words

Syntax

J Ree Address

Execution

If condition true, then offset + PC' -+ PC
If condition false, then go to next instruction

Instruction
Words

15 14

code

o
o

offset

Fields

code

Description

The JRec instruction conditionally jumps to an address that is relative to the
current PC. The ee is part of a mnemonic that represents the condition for
the jump; for example, if ee is UC, then the instruction is JAUC. (See the
condition mnemonics and codes listed below.) If the specified condition
is true, the TMS3401 0 jumps to a new location. The assembler calculates
the address of this location by adding the address of the next instruction
(PC') to the signed word offset. The TMS3401 0 then continues execution
from this point. If the specified condition is false, the TMS3401 0 skips the
jump and continues execution at the next sequential instruction.

is a 4-bit digit that identifies the condition for the jump within
the opcode. (See the condition codes table below.)

The Address operand in the syntax represents the 32-bit relative address.
The assembler calculates the offset as (Address - PC')/16 and inserts the
resulting offset into the second instruction word of the opcode. The range
for this form of the JRee instruction is -32,768 to +32,767 words (excluding 0).
If the offset is 0, the assembler substitutes a NOP instruction. If the address
is out of range, the assembler uses the JAee instruction instead. The assembler does not accept an address which is externally defined or an address which is relative to a different section than the PC. Note that the four
LSBs of the program counter are always 0 (word aligned).
The JRee instructions are usually used in conjunction with the CMP and
CMPI instructions. The JRV and JRNV instructions can also be used to
detect window violations or CPW status.

Condition
Codes
Unconditional
Compares
Unsigned
Compares

Mnemonic
JRUC

Result of Compare
Unconditional

JRLO
(JRC)
JRLS JRYLE
JRHI JRYGT
JRHS
JRNC
JREQ
(JRZ)
JRNE
(JRNZ)

Dst lower than Src

12-96

Status Bits
don't care

Code

0001

C+Z

C·ZC

0010
0011
1001

Dst = Src

1010

Dst ¢ Src

Z-

1011

Dst lower or same as Src
Dst higher than Src
Dst higher or same as Src

0000

JRcc

Jump Relative Conditional - ±32K Words

Condition
Codes
(continued)

Mnemonic
Result of Compare
Status Bits
(N • V) + ( N • V)
JRLT JRXLE Dst < Src
JRLE
Dst S Src
(N • 'if_+ (fJ :....V) .:!: Z _
(N • V • Z) + ( N • V • Z)
JRGT
Dst > Src
(N • V) + (fJ • 'if)
JRGE JRXGT Dst> Src
Dst;:; Src
Z
JREQ
(JRZ)
JRNE
Z
Dst '" Src
(JRNZ)
JRYZ
Compare to
Result = zero
JRZ
Z
Zero JRNZ JRYNZ Result'" zero
Z
l\j·Z
JRP
Result is positive
JRN
Result is negative
JRXZ
N
l\j
JRNN JRXNZ Result is nonnegative
General
Result is zero
Z
JRZ
JRYZ
Arithmetic JRNZ JRYNZ Result is nonzero
Z
JRC JRYN
Carry set on resu It
C
JRNC JRYNN No carryon result
C
JRB
Borrow set on result
C
(JRC)
JRNB
No borrow on result
C
JRNC
JRVt JRXN
Overflow on result
V
JRNVt JRXNN No overflow on result
'if
Note: A mnemonic code In parentheses IS an alternate code for the preceding code.
t Also used for window clipping
+ Logical OR
..:. Logical AN 0
Logical NOT
Signed
Compares

0100
0110
0111
0101
1010
1011

0101
1011
0001
1110
1111
1010
1011
1000
1001
1000

1001

Machine
States

Code

1100
1101

3,6 (Jump)
4,7 (No jump)

Status Bits

N
C
Z
V

Examples

Code

Unaffected
Unaffected
Unaffected
Unaffected

Flags for Branch

Code

NCZV NCZV NCZV
JRUC
JRP
JRLS
JRHI
JRLT
JRGE
JRLE
JRGT
JRC
JRNC
JRZ

HERE
HERE
HERE
HERE
HERE
HERE
HERE
HERE
HERE
HERE
HERE

xxxx
OxOx
xx1x
xOOx
Oxx1
OxxO
Oxx1
OxOO
x1xx
xOxx
xx1x

x1xx
1xxO
1 xx1
1xxO
1 x01

xx1x

NCZV NCZV NCZV
JRV
JRNZ
JRNN
JRNV
JRN
JRB
JRNB
JRLO
JRHS
JRNE
JREQ

HERE
HERE
HERE
HERE
HERE
HERE
HERE
HERE
HERE
HERE
HERE

xxx1
xxOx
Oxxx
xxxO
1xxx
x1xx
xOxx
x1xx
xOOx
xxOx
xx1x

xx1x

Note that the TMS34010 jumps when anyone or more of the Flags for
Branch listed above are set as indicated.

12-97

Jump Indirect

JUMP
Syntax

JUMP Rs

Execution

Rs .... PC

Instruction
Words
Description

Machine
States

15 14
0
0

13
0

12
0

11
0

10
0

5
1

0
Rs

JUMP jumps to the address contained in the source register. The
TMS34010 sets the four LSBs of the program counter to 0 (word aligned).
This instruction can be used in conjunction with the GETPC and/or EXGPC
instructions.
2,5

Status Bits

N
C
Z
V

Examples

Code

Before

JUMP Al
JUMP Al
JUMP Al

00001EEOh
00001EE5h

Unaffected
Unaffected
Unaffected
Unaffected

12-98

9
0

FFFFFFFFh

After
PC
00555550h
00555550h
00555550h

PC
00001EEOh
00001EEOh

FFFFFFFOh

LINE

Line Draw with XV Addressing

Syntax

LINE

Execution

The two execution algorithms for the LINE instruction are explained below.
These algorithms are similar, varying only in their treatment of d=O.

Instruction
Words

15 14

11
Fields

{O,1}

7
6
5
ZOO

The assembler sets bit 7 in the instruction word (the Z bit) to 0 or 1, depending on which LINE algorithm you select:
Z=O selects algorithm 0
Z=1 selects algorithm 1

Description

LINE performs the inner loop of Bresenham's line-drawing algorithm. This
type of line draw plots a series of points (Xj.vj) either diagonally or laterally
with respect to the previous point. Movement from pixel to pixel always
proceeds in a dominant lateral direction. The algorithm mayor may not also
increment in the direction with the smaller dimension (this produces a diagonal movement). Two XV-format registers supply the XY increment values for the two possible movements. The LINE instruction maintains a
decision variable, d, that acts as an error term, controlling movement in either the dominant or diagonal direction. The algorithm operates in one of
two modes, depending on how the condition d=O is treated.
During LINE execution, some portion of a line [(XO.vO)(X1.v1)] is drawn.
The line is drawn so that the axis with the largest extent has dimension a
and the axis with the least extent has dimension b. Thus, a is the larger (in
absolute terms) of Y1 - YO or x1 - xO and b is the smaller of the two. This
means that a .::. b .::. O.
The following values must be supplied to draw a line from (XO,YO) to
(X1,Y1):
1)

Set the XY pointer (Xj.vj) in the DADDR register to the initial value
of (XO,YO).

Use the line endpoints to determine the major and minor dimensions
(8 and b, respectively) for the line draw; then set the DYDX register
to this value (b:a).

Place the signed XY increment for a movement in the diagonal (or
minor) direction (d.::. 0 for Z=O, d > 0 for Z=1) in the INC1 register.

Place the signed XY increment for a movement in the dominant (or
major) direction (d < 0 for Z=O, d :s 0 for Z=1) in the INC2 register.

Set the initial value of the decision variable in register 80 to 2b -

Set the initial count value in the COUNT register to

Set the LINE color in the COLOR1 register.

Set the PATTRN register to all1s.

+ 1.

12-99

LINE

Line Draw with XV Addressing

The LINE instruction may use one of two algorithms, depending on the
value of Z:
Algorithm 0 (Z=O):
While COUNT> 0
COUNT = COUNT - 1
Draw the next pixel
If d > 0
-d = d + 2b - 2a
POINTER = POINTER + INC1
Else d = d + 2b;
POINTER = POINTER + INC2
Algorithm 1 (Z=1):
While COUNT> 0
COUNT = COUNT - 1
Draw the next pixel
Ifd> 0
d=d+2b-2a
POINTER = POINTER + INC1
Else d = d + 2b;
POINTER = POINTER + INC2
LINE 1 is commonly used to draw lines with decreasing y values; LINE 0
is used to draw lines with increasing y values. For horizontal lines, use FILL
or LINE O.
Implied
Operands
Register

Name

B File Registers
Format

Description

Decision variable. d
Starting point {Yj:Xj}, usually {Yo:xo}
Screen origin {O,O}
Window starting corner
Window ending corner
b:a minor:major line dimensions
Pixel color to be replicated
Loop count
Minor axis {diagonal} increment, INC1
Major axis {dominant} increment, INC2
Future pattern register, must be set to all
Temporary register
I/O Registers
Description and Elements (Bits)
Address
Name
PP- Pixel processing operations
COOOOOBOh
CONTROL
W -Window clipping operation
T -Transparency operation
XY-to-linear conversion {destination pitch}
COOO0140h
CONVDP
COOO0150h
PSIZE
Pixel size {1.2.4.8,16}
COOO0160h
PMASK
Plane mask - pixel format
t These registers are changed by instruction execution
BOt
B2t
B4
B5
B6
B7
B9
B10t
B11
B12
B13t
B14

12-100

SADDR
DADDR
OFFSET
WSTART
WEND
DYDX
COLOR1
COUNT
INC1
INC2
PATTRN
TEMP

Integer
XY
Linear
XY
XY
XY
Pixel
Integer
XY
XY
Pattern

Line Draw with XV Addressing

LINE

Due to the pipelining of memory writes, the last I/O register that you write
to may not. in some cases, contain the desired value when you execute the
LINE instruction. To ensure that this register contains the correct value for
execution, you may want to follow the write to that location with an instruction that reads the same location (such as a MOVE SAddress,Rd instruction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
Pixel
Processing

Window
Checking

The PP field in the CONTROL I/O register specifies the operation to be
applied to the pixel as it is written. There are 22 operations; the default case
at reset is the pixel processing replace (S .... D) operation. For more information, see Section 7.7, Pixel Processing, on page 7-15.
Window clipping or pick is selected by setting the W bits in the CONTROL
I/O register to the appropriate value. The WSTART and WEND registers
define the window in XY -coordinate space.
Options include:

No window clipping. LINE draws the entire line. Neither the WVP or
V bit are affected. WSTART and WEND are ignored.

Window hit. The instruction calculates points but no pixels are actually
drawn. As soon as the pixel to be drawn lies inside the window, the
WVP bit is set, the V bit is cleared, and the instruction is aborted. At
this point. registers BO, B2, B10, B13, and B14 are set so as to draw
the next pixel in the line; BO is set to the value for the pixel beyond the
next pixel on the line. If the line lies entirely outside the window, then
the WVP bit is not affected, the V bit in the status is set. and the instruction completes execution.

Clip and set WVP. LINE draws pixels until the pixel to be drawn lies
outside the window. At this point. the WVP bit is set. the V bit is set.
and the instruction is aborted. At this point. registers BO, B2, B1 0, B13,
and B14 are set so as to draw the next pixel in the line; BO is set to the
value for the pixel beyond the next pixel on the line. If the entire line
lies within the window, then the WVP bit is not affected, the V bit
is cleared and the instruction completes execution. The initial value of
WVP does not affect instruction execution.

Clip. LINE calculates all the points, but only draws the points that lie
inside the window. The V bit tracks the state of the last pixel. If the
pixel was outside the window, V is set to 1; otherwise, it is O. The instruction traverses the entire line.

The default case at reset is no window clipping. For more information, see
Section 7.10, Window Checking, on page 7-25.
Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register t01. The TMS34010 checks for 0 (transparent)
source pixels after it processes the source data. At reset. the default case
for transparency is off.
Plane Mask

The plane mask is enabled for this instruction.

Interrupts

LINE may be interrupted after every pixel in the line draw except for the last
pixel. If the instruction is interrupted, the PC is decremented by 16 to point
back to the LINE instruction (the one being executed) before the PC is
12-101

LINE

Line Draw with XV Addressing

pushed on the stack. Thus, the LINE instruction is resumed upon return
from the interrupt. In order for the LI N E to be resumed correctly, any B -file
registers that are modified by the interrupting routine must be restored, and
the RETI instruction must be executed. Note that a LINE instruction that
is aborted because of window checking options 1 or 2 does not decrement
the PC before pushing it on the stack. In this case, the LINE is not resumed
after returning from the interrupt service routine.

Machine
States

The total LINE instruction timing is obtained by adding a setup time to a
transfer time:
LINE time = LINE setup time + LINE transfer time
•

LINE setup time is the overhead incurred from initiating the LINE
instruction. The setup sequence executes an initialization sequence,
performing any necessary setup operations and translations. The

setup time is always 4 machine states.
•

The transfer sequence performs the actual data transfer from the
source register to the destination pixels. Table 12-10 shows LINE
transfer timing. LINE transfer timing may be influenced by window
and pixel processing operations; their affects are discussed in the list
that follows Table 1 2 -1 O.
Table 12-10. LINE Transfer Timing
Window Option

Instruction

W=O (Off)

W=1
Window Hit
5q + 5
5q + 5

(3+P)£
LINE 0
(3+P)£
LINE 1
t Add 5 for a Window violation
Key:
£ Number of pixels written
q Number of pixels calculated, but not written
P Selected pixel processing operation

W=2, Interrupt
On Clip
(3+ P)£ t
{3+ P)£t

W==3
Clipping
(3+P)£ + 5q
(3+ P)£ + 5q

Although window operations affect the setup time of most instructions,
they are performed during transfer execution of the LINE instruction, affecting it on a per-pixel basis. Window operations that affect the LINE instruction include:
•
•
•

No window checking
Window clip: V flag set, LINE aborted on first write outside window
Window hit: WVP flag set, V flag cleared, abort LINE on first write
inside window

Pixel processing operations influence the LINE transfer timing. (The effects
of other graphics operations, such as plane masking and transparency, are
already included.) Pixel processing consumes 2, 4, 5, or 6 machine states
per pixel, depending on the operation selected. Table 12-11 shows the
effects of pixel processing on LINE timing.

12-102

LINE

Line Draw with XV Addressing

Table 12-11. Per-Word Timing Values for Pixel Processing (P)
Replace

Other
Booleans
or ADD

ADDS.SUBS
MAX or MIN

SUBS

Figure 12-11 illustrates timing for a LIN E 0, drawing a line from (3h,52h)
to (19h,55h).

**************************************************
* Implied operand setup for LINE example (assume *
*
* that B re~ister and I/O register names are

* equated w~th the proper registers)
*
**************************************************
MOVI OFFFFFFFOh, BO
Decision variable d=2b-a=-16
MOVI 00520003h, B2
DADDR
DPTCH (CONVDP=14)
MOVI 00000800h, B3
MOVI 00000100h, B4
OFFSET
MOVI 00300003h, B5
WSTART
MOVI 00550025h, B6
WEND
MOVI 00030016h, B7
b:aj b=3 and a=22
COLOR 1 (color of the line)
MOVI 44444444h, B9
MOVI 00000017h, BlO
COUNT (a+l)
Diagonal increment (+1,+1)
MOVI 00010001h, Bll
MOVI 00000001h, B12
Nondiagonal increment (0,+1)
MOVI OFFFFFFFFh, Bl3
PATTRN (all Is)
MOVI OOCOh, AO
MOVE AO, @CONTROL
W=3, T=O, PP=O,
CLR
AO
MOVE AO, @PMASK
No plane masking
Figure 12-11. Implied Operand Setup for LINE Timing Example

Figure 12-12. LINE Timing Example
Follow these steps to determine the number of machine states consumed
by this LINE example:
1)

The setup time for a LINE instruction is always 4 machine states.

Determine the transfer time. Transfer time comprehends windowing, the number of pixels drawn, and graphics operations.
a)
b)

Windowing: is on for this LINE 0 instruction; as Table 12-10
shows, the transfer timing is (3+P)£ + 5Q.
Graphics operations: The pixel processing replace operation has
been selected; according to Table 12-11, P=2.
12-103

LINE

Line Draw with XV Addressing

Number of pixels drawn: Register B10 indicates the total number of pixels in the line (23). Since the line fits within the window, all pixels calculated are drawn; thus, E = 23 and 0=0.

The total machine states required for this instruction are:
LINE time

= LINE setup time
=4
= 4
= 119 states

+ LINE transfer time

+
+

~+~E+50

(3+2) x 23 + 0

11 9 states are needed to draw these 23 pixels.
The LINE instruction may be interrupted on any pixel boundary during the
transfer portion of the algorithm. The context of the LINE is saved in reserved registers; the PC is decremented before it is pushed on the stack, so
that execution returns to the LINE opcode. This operation takes 20 machine states for the interrupt to be recognized. The time for the context
switch must be added; see the TRAP instruction for context switch timing.

Status Bits

12-104

N
C
Z
V

Undefined
Undefined
Undefined
Set depending upon window operation.

Line Draw with XV Addressing

LINE

Linedraw Code
The following code segment shows setup and execution of the LINE instruction.
*********************************************************************

* Draw a line from point (xs,~s) to point (xe,ye) using Bresenham's
* algorithm. When -draw_line 1S called, xs is in the 16 LSBs of B2,
* ~s is in the 16 MSBs of B2, xe is in the 16 LSBs of BO, and ye is
* 1n the 16 MSBs of BO.

*
*

*********************************************************************

.global
_draw_line:
SUBXY

*
*
*
*

_draw_line
B2, BO

; Calculate a and b

Now set up B7
(a,b) and B11 = (dx_diag,dy_diag). Assume that
a < 0 and b < 0; if a >= 0 or b >= 0, make corrections later.
Register B11 (INC1) contains dy_diag::dx_diag
Register B12 (INC2) contains dy_nondiag::dx-nondiag
dx-diag = dy_diag - 1
Constant = 1

MOVI
-1, B11
MOVK
1, B12
CLR
B7
SUBXY
BO, B7
JRNC
L1
* Handle case where b >= 0:
MOVY
BO, B7
SRL
15, B11
L1:
JRNV
L2

B7 = (-a,-b)
Jump if b < 0
Make a in B7 positive
Change dy_diag to +1
Jump if a < 0

* Handle case where a >= 0:
L2:

MOVX
MOVX

BO, B7
B12, B11

Take absolute value of a
Change dx-diag to +1

MOVX

B11, B12

dx_nondiag=dx-diag, dy_nondiag=O

Compare magnitudes of a and b:
MOVE
B7, BO
Copy a and b
Move b into 16 LSBs
SRL
16, BO
CMPXY
BO, B7
Compare a and b
JRNV
L3
Jump if a >= b

Handle case where a < b; must swap a and b so that a >= b:
MOVX
B7, BO
Copy b into BO
RL
16, B7
Swap a and b halves of B7
CLR
B12
dx_nondiag=O, dy_nondiag=dy_diag
MOVY
B11, B12

Calculate initial values of decision variable (d) and

* loop counter:

L3:

ADD
MOVX
SUB
ADDK

BO = 2 x b
B10 = a
BO = d (2 x b - a)
Loop count = a + 1 (in B10)

BO, BO
B7, B10
B10, BO
1, B10

* Draw line and return to caller:
LINE
RETS

0
0

; Inner loop of line algorithm
; Return to caller

12-105

LINE

Example 7

Line Draw with XV Addressing

This example draws a line from (3,52) to (19,55). Window checking is off,
transparency and the pixel processing replace operation are selected, and
plane masking is disabled. Assume the following registers have been
loaded with these values:
BO
B2
B3
B4
B5
B6
B7
B9
B10
B11
B12
B13

=
=
=
=
=
=
=
=
=
=
=
=

FFFFFFF1 h
00520003h
00000800h
000001 OOh
00300003h
00550025h
00030016h
44444444h
00000017h
00010001 h
00000001 h
FFFFFFFFh

Decision variable d = 2b - a = -1 5
DADDR
DPTCH (CONVDP=13)
OFFSET
WSTART
WEND
b:a; b=3 and a=22
COLOR1 (color of the line)
COUNT (a+1)
Diagonal increment (+1,+1)
Nondiagonal increment (0,+1)
PATTRN (all1s)

This line is shown in Figure 12-13, represented by.s.
Before LINE execution, DADDR contains the first pixel to be drawn. During
LINE execution, DADDR is updated so that it always points to the next
pixel to be drawn. After this example is completed, DADDR equals
0055001 Ah. Register B7 contains the X and Y dimensions of the line.
Register B10 indicates the number of pixels that are drawn; if you want the
endpoint to be drawn (in this case, (19,55», B10 should equal a+1.
B11 contains the XY increment for diagonal moves. You can see the line
progressing in a diagonal direction when it moves from (6,52) to (7,53); it
is incremented by 1 in both the X and the Y dimensions. B12 contains the
XY increment for nondiagonal moves. You can see the line progressing in
a nondiagonal direction when it moves from (3,52) to (4,52); it is incremented by 1 in the X dimension.

~------------~v~------------~
a=22

Figure 12-13. LINE Examples

12-106

Line Draw with XV Addressing

Example 2

LINE

This example draws a line from (19,52) to (3,55). Window checking is off,
transparency and the pixel processing replace operation are selected, and
plane masking is disabled. Assume the following registers have been
loaded with these values:
80
82
83
84
85
86
87
89
810
811
812
813

=
=
=
=
=
=
=
=
=
=
=
=

FFFFFFF1 h
00520019h
00000800h
000001 OOh
00300003h
00550025h
00030016h
22222222h
00000017h
0001 FFFFh
OOOOFFFFh
FFFFFFFFh

Decision variable d = 2b - a = -15
DADDR
DPTCH (CONVDP=13)
OFFSET
WSTART
WEND
b:a; b=3 and a=22
COLOR1 (color of the line)
COUNT (a+1)
Diagonal increment (+1,-1)
Nondiagonal increment (0,-1)
PATTRN (all 1 s)

This line is shown in Figure 12-13, represented by Xs.
8efore LINE execution, DADDR contains the first pixel to be drawn. During
LINE execution, DADDR is updated so that it always points to the next
pixel to be drawn. After this example is completed, DADDR equals
00550002h. Register 87 contains the X and Y dimensions of the line.
Register 810 indicates the number of pixels that are drawn; if you want the
endpoint to be drawn (in this case, (3,55)), 810 should equal a+1.
811 contains the XY increment for diagonal moves. You can see the line
progressing in a diagonal direction when it moves from (F,53) to (E,54); it
is decremented by 1 in the X dimension and incremented by 1 in the Y dimension. 812 contains the XY increment for nondiagonal moves. You can
see the line progressing in a nondiagonal direction when it moves from
(14,53) to (13,53); it is decremented by 1 in the X dimension.

12-107

LMO

Find Leftmost One

Syntax

LMO

Execution

31 - (bit number of leftmost 1 in Rs)

Instruction
Words
Description

Rs, Rd

15 14

LMO locates the leftmost (most significant) 1 in the source register. It then
loads the 1s complement of the bit number of the leftmost-1 bit into me
five LSBs of the destination register. The 27 MSBs of the destination register are loaded with Os. Bit 31 of Rs is the MSB (leftmost) and bit 0 is the
LSB. If the source register contains all Os, then the destination register is
loaded with all Os and status bit Z is set.
You can normalize the contents of the source register by following the LMO
instruction with an RL RS,Rd instruction, where Rs is the destination register of the LMO instruction and Rd is the source register.
Rs and Rd must be in the same register file.

Machine
States

1,4

Status Bits

N
C
Z
V

Examples

Code
LMO
LMO
LMO
LMO
LMO

12-108

Unaffected
Unaffected
1 if the source register contents are 0, 0 otherwise
Unaffected

AO,AI
AD,AI
AD,AI
AD,AI
AD,AI

Before

After

NCZV
xx1x
xxOx
xxOx
xxOx
xxOx

OOOOOOOOh
0OOOOOO1h
0OOOOO10h
08000000h
80000000h

A1
OOOOOOOOh
0OOOOO1Fh
0OOOOO1Bh
00OOOOO4h
OOOOOOOOh

Move Multiple Registers from Memory

MMFM

Syntax

MMFM

Execution

For each register Rn in the register list,
32 bits of data at the address specified in Rp ..... Rn
Rp + 32 ..... Rp

Instruction
Words

Rp, register list

15 14 13

12
0

9
0

4
R

binary representation of the register list

Description

MMFM loads the contents of a specified list of either A or B file registers
(not both) from a block of memory.
•

The Rp operand is a register that points to the first location in the
block of memory.

•

The register list is a list of registers separated by commas (such as AO,
A1, A9). These are the registers that MMFM loads new values into.

The MMTM and MMFM instructions are "stack" instructions for storing
multiple registers in memory and then retrieving their values. Both instructions use Rp as a "stack pointer" that contains the bit address of the
top of the stack. The stack grows toward lower addresses so that the bottom of the stack is the highest address in the stack. MMTM stores the registers in memory. MMFM reverses the action of the MMTM instruction
by "popping" register values from memory. At the outset of the MMFM
instruction, Rp must contain the address of the 16 LSBs of the highest order register in the list. The LSW is moved into the register, and then the
contents of the next consecutive word are moved into the MSW of the register. After a register is "popped", the contents of Rp are incremented by
32 to point to the address of the LSW of the next register to be restored.
Rp and the registers in the list must all be in the same register file. The registers in the list can be specified in any order; the highest order register is
always restored first (that is, the value at the top of the stack - the lowest
address in the stack - is loaded into the highest order register). Don't include Rp as one of the registers in the register list, because this produces
unpredictable results. The original contents of Rp should be aligned on a
word-boundary; the alignment of Rp affects the instruction timing as indicated in Machine States, below.
The second word of the MMFM instruction is a binary-mask representation
of the registers in the list. The R bit (bit 4) in the first word indicates which
register file is affected; the bits that are set to 1 in the mask indicate which
registers are restored. The bit assignments in the mask are:

12-109

MMFM

Machine
States

Move Multiple Registers from Memory

Cache Enabled
Rp Aligned:
3 + 4n + (2)
Rp Nonaligned: 3 + 6n + (4)

Cache Disabled
11 + 4n
13 + 6n

Status Bits

N
C
Z
V

Examples

This example restores several B-file registers:

Unaffected
Unaffected
Unaffected
Unaffected

MMFM

BO,Bl,B2,B3,B7,B12,B13,B14,SP

This instruction uses register BO as the stack pointer. Assume that BO =
00010000h; this is the address of the top of the stack. MMFM moves the
data at this location into the LSW of the SP (which is the highest order
register listed in this example). Assume that memory contains the following
values before instruction execution:
Address

000100FOh
000100EOh
000100DOh
0OO100COh
000100BOh
0OO100AOh
0OO10090h
0OO10080h

Data
1111h
01 B1 h
2222h
OB2B2h
3333h
03B3h
7777h
B7B7h

Address

00010070h
00010060h
00010050h
00010040h
00010030h
00010020h
00010010h
00010000h

Data
CCCCh
BCBCh
DDDDh
BDBDh
EEEEh
BEBEh
FFFFh
BFBFh

After the M M FM instruction is executed, the registers in the list have the
following values:
BO
B1
B2
B4
B8

000101 OOh
1111 B1 B1 h
2222B2B2h
3333B3B3h
= 7777B7B7h

=
=
=
=

B12 = CCCCBCBCh
B13 = DDDDBDBDh
B14 = EEEEBEBEh
SP = FFFFBFBFh

The other B-file registers (which weren't specified in the register list) are
not affected by this instruction. Note that BO now contains the value
10100h; the last part of the data that was restored was for B1, and BO
points to the word past that data.

12-110

Move Multiple Registers to Memory

MMTM

Syntax

MMTM

Execution

For each register Rnin the register list,
Rp - 32 -+ Rp
32 bits of data at the address specified in Rn

Instruction
Words

Rp, register list

15 14 13

2
Rd

binary representation of the register list

Description

MMTM stores the contents of a specified list of either A or B file registers
(not both) in memory.
•

The Rp operand is a register that points to the first location in a block
of memory.

•

The register list is a list of registers that are separated by commas
(such as AO, A1, AS). These are the registers that MMTM stores in
memory.

The MMTM and MMFM instructions are "stack" instructions for storing
multiple registers in memory and then retrieving their values. Both instructions use Rp as a "stack pointer" that contains the bit address of the
top of the stack. The stack grows toward lower addresses so that the bottom of the stack is the highest address in the stack. M MTM stores the registers in memory. Before a register's contents are "pushed" onto the stack,
the Rp is decremented by 32 bits; the register is then pushed, LSW first.
Thus, at the outset of the M MTM instruction, Rp must contain an incremented value. This value is the address where you want to store the LSW
of the lowest-order register, plus 32 bits; this assures that Rp is predecremented to point to the correct location in memory.
When MMTM execution is complete, the contents of the lowest-order register in the list reside at the highest address in the memory "stack," and Rp
points to the address of the highest-order register in the list.
Rp and the registers in the list must all be in the same register file. The registers in the list can be specified in any order; the lowest order register is
always saved first. Don't include Rp as one of the registers in the register
list, because this produces unpredictable results. The original contents of
Rp should be aligned on a word boundary; the alignment of Rp affects the
instruction timing as shown in Machine States, below.
The second word of the MMFM instruction is a binary-mask representation
of the registers in the list. The R bit (bit 4) in the first word indicates which
register file is affected; the bits that are set to 1 in the mask indicate which
registers are restored. The bit assignments in the mask are:

12-111

MMTM

Machine
States

Status Bits

Move Multiple Registers to Memory

Cache Enabled
Rp Aligned:
2 + 4n + (2)
Rp Nonaligned: 2 + 10n + (8)
N

C
Z
V

Examples

Cache Disabled
8 + 4n + 2
10{n + 1)

Set to the sign of the result of 0 - Rp. (This value is typically 1 if the
original contents of Rp are positive; otherwise, it is O. The only exceptions to this are when Rp=80000000h, N is set to 0, and when
Rp=O, N is set to 1.)
Unaffected
Unaffected
Unaffected

This example saves the values of several A-file registers in memory:

MMTM

Al,AO,A2,A4,A8,A12,A13,A14,SP

This instruction uses register A1 as the stack pointer. Assume that A1
100000h before instruction execution; this value is decremented by 32 to
point to the address where the contents of AO (the lowest order register in
the list) are stored. Assume that the registers in the list contain the following values before instruction execution:
AO
A2
A4
A8

=
=
=
=

OOOOAOAOh
2220A2A2h
4444A4A4h
8888A8A8h

A12 = CCCCACACh
A13 = DDDDADADh
A14 = EEEEAEAEh
SP = FFFFAFAFh

MMTM saves these register values in memory as shown below:

Address
OOOFFFOOh
000FFF10h
000FFF20h
OOOFFF30h
000FFF40h
000FFF50h
OOOFFF60h
OOOFFF70h

Data
AFAFh
FFFFh
AEAEh
EEEEh
ADADh
DDDDh
ACACh
CCCCh

Address
OOOFFF80h
OOOFFF90h
OOOFFFAOh
OOOFFFBOh
OOOFFFCOh
OOOFFFDOh
OOOFFFEOh
OOOFFFFOh

Data
A8A8h
8888h
A4A4h
4444h
A2A2h
2222h
AOAOh
OOOOh

After instruction execution, register A1 = OOOFFFOOh. Note that A1 now
contains the value OFFFOOh; this is the address of the last portion of register
data that is saved.

12-112

MODS

Modulus - Signed

Syntax

MODS RS,Rd

Execution

Rd mod Rs ..... Rd

Instruction
Words

15 14

10
Description

MODS performs a 32-bit signed divide of the 32-bit dividend in the destination register by the 32-bit value in the source register, and returns a
32-bit remainder in the destination register. The remainder is the same sign
as the dividend. The original contents of the destination register are always
overwritten.
Rs and Rd must be in the same register file.

Machine
States

Status Bits

40,43 (normal case)
41,44 if resu It = 80000000
3,6 if Rs = 0
N
C
Z
V

Unaffected
Unaffected
Unaffected if RS=O, 1 if quotient is 0, 0 otherwise
1 if the quotient overflows (cannot be represented by 32 bits), 0 otherwise
The following conditions set the overflow flag:

•
•

The divisor is 0
The quotient cannot be contained within 32 bits

Examples Code
MODS
MODS
MODS
MODS
MODS
MODS
MODS
MODS
MODS
MODS
MODS
MODS
MODS

Before
AD,AI
AD,AI
AD,AI
AD,AI
AD,AI
AD,AI
AD,AI
AD,AI
AD,AI
AD,AI
AD,AI
AD,AI
AD,AI

After

NCZV

OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
00000004h
0OOOOOO4h
0000OOO4h
00OOOOO4h
00000004h
FFFFFFFCh
FFFFFFFCh
FFFFFFFCh
FFFFFFFCh
FFFFFFFCh

OOOOOOOOh
00000007h
FFFFFFF9h
00000008h
0OOOOOO7h
OOOOOOOOh
FFFFFFF9h
FFFFFFF8h
00000008h
00000007h
OOOOOOOOh
FFFFFFF9h
FFFFFFF8h

Ox01
Ox01
Ox01
Ox10
OxOO
Ox10
1xOO
Ox10
Ox10
OxOO
Ox10
1xOO
Ox10

OOOOOOOOh
00000007h
FFFFFFF9h
OOOOOOOOh
0OOOOOO3h
OOOOOOOOh
FFFFFFFDh
OOOOOOOOh
OOOOOOOOh
00000003h
OOOOOOOOh
FFFFFFFDh
OOOOOOOOh

12-113

MODU

Modulus - Unsigned

Syntax

MODU

Execution

Rd mod Rs -

Instruction
Words

15 14

Description

Rs, Rd

Rd
12
0

MODU performs a 32-bit unsigned divide of the 32-bit dividend in the
destination register by the 32-bit value in the source register, and returns a
32-bit remainder in the destination register. The original contents of the
destination register are always overwritten.
Rs and Rd must be in the same register file.

Machine
States

35,38
3,6 if Rs

Status Bits

N
C
Z
V

Examples

Code

Unaffected
Unaffected
Unaffected if RS=O, 1 if quotient is 0, 0 otherwise
1 if divisor Rs equals 0, 0 otherwise

MODU
MODU
MODU
MODU
MODU
MODU
MODU

12-114

Before
AO,Al
AO,Al
AO,Al
AO,Al
AO,Al
AO,Al
AO,Al

After

NCZV

OOOOOOOOh
OOOOOOOOh
OOOOOOOOh
00000004h
00000004h
00000004h
00000004h

OOOOOOOOh
00000007h
FFFFFFF9h
00000008h
00000007h
OOOOOOOOh
FFFFFFF9h

xx01
xx01
xx01
xx10
xxOO
xx10
xxOO

OOOOOOOOh
00000007h
FFFFFFF9h
OOOOOOOOh
00000003h
OOOOOOOOh
00000001h

Move Byte - Register to Indirect
Syntax

MOVB

Execution

8 LSBs of Rs .... *Rd

Instruction
Words
Description

Rs, *Rd

15 14

MOVB

2
Rd

MOVB moves a byte from the source register to the memory address contained in the destination register. The source operand byte is right justified
in the source register; only the 8 LSBs of the register are moved. The memory address is a bit address and the field size for the move is 8 bits.
Rs and Rd must be in the same register file.

Machine
States

1 + (3),7 (when the destination address is aligned on a byte boundary)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z
V

Examples

Assume that memory contains the following values before instruction execution:

Unaffected
Unaffected
Unaffected
Unaffected

Address
5000h
5010h
Code
MOVB
MOVB
MOVB
MOVB

Data
OOOOh
OOOOh
After

Before
AO, *Al
AO,*Al
AO,*Al
AO,*Al

AO
89ABCDEFh
89ABCDEFh
89ABCDEFh
89ABCDEFh

A1
00005000h
00005001h
00005009h
0000500Ch

@5000h
@5010h
OOEFh
OOOOh
01 DEh
OOOOh
ODEOOh 0001h
FOOOh
OOOEh

12-115

Move Byte - Register to Indirect with Offset

MOVB

Syntax

MOVB Rs, *Rd(offset)

Execution

8 LS Bs of Rs

Instruction
Words

* Rd

+ offset

15 14 13 12 11

2
Rd

Rs
offset

Description

MOVB moves a byte from the source register to the destination memory
address. The source operand byte is right justified in the source register;
only the 8 LSBs of the register are moved. The destination memory address
is a bit address and is formed by adding the contents of the specified register to the signed 16-bit offset. This is a field move, and the field size for
the move is 8 bits.
Rs and Rd must be in the same register file.

Machine
States

3+(3),9 (when the destination address is aligned on a byte boundary)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z
V

Examples

Unaffected
Unaffected
Unaffected
Unaffected

Assume that memory contains the following values before instruction execution:
Address
10000h
10010h

Data
OOOOh
OOOOh
Before

Code
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB

12-116

AO,*A1(O)
AO,*A1(1)
AO,*A1(9)
AO, * A1 ( 12 )
AO,*Al(32767)
AO,*A1(-32768)

After

89ABCDEFh
89ABCDEFh
89ABCDEFh
89ABCDEFh
89ABCDEFh
89ABCDEFh

00010000hOOEFh
00010000h01DEh
00010000hDEOOh
00010000hFOOOh
00008001hOOEFh
00018000hOOEFh

@10000h @10010h

OOOOh
OOOOh
0001h
OOOEh
OOOOh
OOOOh

Move Byte - Register to Absolute

Syntax

MOVB Rs, *DAddress

Execution

8 LSBs of'Rs .... DAddress

Instruction
Words

15 14
0
0

13
0

12
0

11
0

10
1

9
0

MOVB

IR I

2
Rs

16 LSBs of destination address
16 MSBs of destination address

Description

MOVB moves a byte from the source register to the destination memory
address. The source operand byte is right justified in the source register;
only the 8 LSBs of the register are moved. The specified destination memory address is a bit address and the field size for the move is 8 bits.
Rs and Rd must be in the same register file.

Machine
States

1 +(3),7 (when the destination address is aligned on a byte boundary)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z
V

Examples

Assume that memory contains the following values before instruction execution:

Unaffected
Unaffected
Unaffected
Unaffected

Address
5000h
5010h

Data
OOOOh
OOOOh

Code
MOVB
MOVB
MOVB
MOVB

AO,@5000h
AO,@5001h
AO,@5009h
AO,@500Ch

Before

After

@5000h
OOEFh
01 DEh
DEOOh
FOOOh

89ABCDEFh
89ABCDEFh
89ABCDEFh
89ABCDEFh

@5010h
OOOOh
OOOOh
0001h
OOOEh

12-117

MOVB

Move Byte - Indirect to Register

Syntax

MOVB

Execution

byte at

Instruction
Words

Description

*Rs, Rd

* Rs

15 14
0
1

..... Rd

13
0

12
0

MOVB moves a byte from the memory address contained in the source register to the destination register. The source memory address is a bit address and the field size for the move is 8 bits. When the byte is moved into
the destination register, it is right justified and sign extended to 32 bits.
This instruction also performs an implicit compare to 0 of the field data.
Rs and Rd must be in the same register file.

Machine
States

3,6 (when the source data is aligned on a byte boundary)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z

1 if the sign-extended data moved into register is negative, 0 otherwise
Unaffected
1 if the sign-extended data moved into register is 0, 0 otherwise

V 0
Examples

Assume that memory contains the following values before instruction execution:
Address
5000h
5010h
Code
MOVB
MOVB
MOVB
MOVB

12-118

*AO,Al
*AO,Al
*AO,Al
*AO,Al

Data
OOEFh
89ABh
Before

After

NCZV

00005000h
00005001h
00005008h
0000500Ch

FFFFFFEFh
00000077h
OOOOOOOOh
FFFFFFBOh

1xOO
OxOO
Ox10
1xOO

Move Byte - Indirect to Indirect

Syntax

MOVB

Execution

byte at *Rs

Instruction
Words
Description

*Rs, *Rd

15 14 13

*Rd

0 0

MOVB

MOVB moves a byte from the source memory address to the destination
memory address. The source address is specified by the contents of Rs, and
the destination address is specified by the contents of Rd. Both memory
addresses are bit addresses and the field size for the move is 8 bits.
Rs and Rd must be in the same register file.

Machine
States

3+ (3),7 (when the source data and destination address are aligned on byte
boundaries)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z
V

Examples

Assume that memory contains the following values before instruction execution:

Unaffected
Unaffected
Unaffected
Unaffected

Address
5000h
5010h
6000h
6010h
Code
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB

Data
CDEF
89AB
0000
0000
Before

*AO,*Al
*AO,*Al
*AO,*Al
*AO,*Al
*AO,*Al
*AO,*Al
*AO,*Al
*AO,*Al
*AO,*Al
*AO, *Al
*AO,*Al
*AO, *Al
*AO,*Al
*AO, *Al
*AO,*Al
*AO,*Al

After

00005000h
00005000h
00005000h
00005000h
00005001h
00005001h
00005001h
00005001h
00005009h
00005009h
00005009h
00005009h
0000500Ch
0000500Ch
0000500Ch
0000500Ch

00006000h
00006001h
00006009h
0000600Ch
00006000h
00006001h
00006009h
0000600Ch
00006000h
00006001h
00006009h
0000600Ch
00006000h
00006001h
00006009h
0000600Ch

@6000h
OOEFh
01DEh
DEOOh
FOOOh
00F7h
01 EEh
EEOOh
7000h
00E6h
01CCh
CCOOh
6000h
DOBCh
0178h
7800h
COOOh

@6010h
OOOOh
OOOOh
0001h
OOOEh
OOOOh
OOOOh
0001h
OOOFh
OOOOh
OOOOh
0001h
OOOEh
OOOOh
OOOOh
0001h
OOOBh

12-119

MOVB

Move Byte - Indirect with Offset to Register

Syntax

MOVB

Execution

byte at (* Rs + offset) .... Rd

Instruction
Words

15 14

*Rs(offset), Rd

13 12 11

876

offset

Description

MOVB moves a byte from the source memory address to the destination
register. The source memory address is a bit address and is formed byadding the contents of the specified register to the signed 16-bit offset. The
field size is 8 bits. When the byte is moved into the destination register, it
is right justified and sign extended to 32 bits. This instruction also performs
an implicit compare to 0 of the field data.
Rs and Rd must be in the same register file.

Machine
States

5,11 (when the source data is aligned on a byte boundary)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z

1 if the sign-extended data moved into register is negative, 0 otherwise
Unaffected
1 if the sign-extended data moved into register is 0, 0 otherwise

V 0
Examples

Assume that memory contains the following values before instruction execution:
Address
10000h
10010h

Data
OOEFh
89ABh

Code
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

12-120

*AO(O),Al
*AO(l) ,AI
*AO(8),Al
*AO(12) ,AI
*AO(32767) ,AI
*AO(-32768) ,AI

Before

After

NCZV

00010000h
00010000h
00010000h
00010000h
00008001h
00018000h

FFFFFFEFh
00000077h
OOOOOOOOh
FFFFFFBOh
FFFFFFEFh
FFFFFFEFh

1xOO
OxOO
Ox10
1xOO
1xOO
1xOO

Move Byte - Indirect with Offset
to Indirect with Offset

MOVB

Syntax

MOVS

Execution

byte at (*Rs + SOffset) .... (*Rd + DOffset)

Instruction
Words

*Rs(SOffset). *Rd(DOffset)

15 14 13 12 11
1

10
1

6
Rs

2
Rd

source offset
destination offset

Description

MOVB moves a byte from the source memory address to the destination
memory address. Both the source and destination memory addresses are
bit addresses and are formed by adding the contents of the specified register to its respective signed 16-bit offset. The field size is 8 bits.
Rs and Rd must be in the same register file.

Machine
States

5+(3).9 (when the source data and destination address are aligned on byte
boundaries)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z

Unaffected
Unaffected
Unaffected
Unaffected

12-121

Move Byte -Indirect with Offset
to Indirect with Offset

MOVB

Examples

Assume that memory contains the following values before instruction execution:
Address

Data

10000h
10010h
11000h
11010h

CDEFh
89ASh
OOOOh
OOOOh

Code
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB

Before
*AO{O),*A1{O)
*AO(O),*A1(1)
*AO(O),*A1(9)
*AO(O),*A1(12)
*AO(O),*A1(32767)
*AO(O),*A1(-32768)
*AO(12),*A1(O)
*AO(12),*A1(1)
*AO(12),*A1(9)
*AO (12) , *A1 (12)
*AO(12),*A1(32767)
*AO(12),*A1(-32768)
*AO(32767),*A1(O)
*AO(32767),*A1(1)
*AO(32767),*A1(9)
*AO(32767),*A1(12)
*AO(32767),*A1(32767)
*AO(32767),*A1(-32678)
*AO(-32768),*A1(O)
*AO(-32768),*A1(1)
*AO{-32768) ,*A1(9)
*AO{-32768),*A1{12)
*AO(-32768),*A1{32767)
*AO{-32768),*A1(-32678)

12-122

AO
00010000h
00010000h
00010000h
00010000h
00010000h
00010000h
00010000h
00010000h
00010000h
00010000h
00010000h
00010000h
00008001h
00008001h
00008001h
00008001h
00008001h
00008001h
00018000h
00018000h
00018000h
00018000h
00018000h
00018000h

After
A1

00011000h
00011000h
00011000h
00011 OOOh
00009001h
00019000h
00011000h
00011000h
00011000h
00011 OOOh
00009001h
00019000h
00011000h
00011000h
00011000h
00011 OOOh
00009001h
00019000h
00011000h
00011000h
00011000h
00011000h
00009001h
00019000h

@11000h

@11010h

OOEFh
01 DEh
DEOOh
FOOOh
OOEFh
OOEFh
OOSCh
0178h
7800h
COOOh
OOSCh
OOSCh
OOEFh
01 DEh
DEOOh
FOOOh
OOEFh
OOEFh
OOEFh
01 DEh
DEOOh
FOOOh
OOEFh
OOEFh

OOOOh
OOOOh
0001h
OOOEh
OOOOh
OOOOh
OOOOh
OOOOh
0001h
OOOSh
OOOOh
OOOOh
OOOOh
OOOOh
0001h
OOOEh
OOOOh
OOOOh
OOOOh
OOOOh
0001h
OOOEh
OOOOh
OOOOh

Move Byte - Absolute to Register

Syntax

MOVB

Execution

byte at SAddress

Instruction
Words

15 14
0

MOVB

@SAddress, Rd
-+

IR I

16 LSBs of source address
16 MSBs of source address

Description

MOVB moves a byte from the source memory address to the destination
register. The specified source memory address is a bit address and the field
size for the move is 8 bits. When the byte is moved into the destination
register, it is right justified and sign extended to 32 bits. This instruction
also performs an implicit compare to 0 of the field data.
Rs and Rd must be in the same register file.

Machine
States

5,14 (when the source data is aligned on a byte boundary)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z

1 if the sign-extended data moved into register is negative, 0 otherwise
Unaffected
1 if the sign-extended data moved into register is 0,0 otherwise

V 0
Examples

Assume that memory contains the following values before instruction execution:

Address
10000h
10010h

Data
OOEFh
89ABh

Code
MOVB
MOVB
MOVB
MOVB

After
@lOOOOh,Al
@lOOOlh,Al
@lOOOBh,Al
@lOOOCh,Al

A1
FFFFFFEFh
00000077h
OOOOOOOOh
FFFFFFBOh

NCZV

1xOO
OxOO
Ox10
1xOO

12-123

Move Byte - Absolute to Absolute

MOVB

Syntax

MOVB @SAddress. @DAddress

Execution

byte at SAddress ... DAddress

Instruction
Words

15 14 13 12
0
0
0
0

11
0

10
0

7
0

6
1

5
0

4
0

3
0

2
0

o
0

16 LSBs of source address
16 MSBs of source address
16 LSBs of destination address
16 MSBs of destination address

Description

Machine
States

MOVB moves a byte from the source memory address to the destination
memory address. Both the source and destination addresses are interpreted
as bit addresses and the field size for the move is 8 bits.
7+(3),25 (when the source data and destination address are aligned on
byte boundaries)
For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z
V

Examples

Assume that memory contains the following values before instruction execution:

Unaffected
Unaffected
Unaffected
Unaffected

Address
10000h
10010h
11000h
11010h

12-124

Data
CDEFh
89ABh

OOOOh
OOOOh

Move Byte - Absolute to Absolute

MOVB

After

Code

@11000h
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB

@lOOOOh,@llOOOh
@HJOOOh,@llOOlh
@lOOOOh,@llOO9h
@lOOOOh,@llOOCh
@lOOOlh,@llOOOh
@lOOOlh,@llOOlh
@lOOOlh,@llOO9h
@lOOOlh,@llOOCh
@lOOO9h,@llOOOh
@lOOO9h,@llOOlh
@lOOO9h,@llOO9h
@lOOO9h,@llOOCh
@lOOOCh,@llOOOh
@lOOOCh,@llOOlh
@lOOOCh,@llOO9h
@lOOOCh,@llOOCh

OOEFh
01 DEh
DEOOh
FOOOh
00F7h
01 EEh
EEOOh
7000h
00E6h
01CCh
CCOOh
6000h
OOBCh
0178h
7800h
COOOh

@11010h

OOOOh
OOOOh
0001h
OOOEh
OOOOh
OOOOh
0001h
OOOFh
OOOOh
OOOOh
0001h
OOOEh
OOOOh
OOOOh
0001h
OOOBh

12-125

Move - Register to Register

MOVE

Syntax

MOVE Rs, Rd

Execution

Instruction
Words

15 14 13 12 11

IM I

4
R

2
Rd

Description

MOVE moves the 32 bits of data from the source register to the destination
register. Note that this is not a field move; therefore, the field size has no
effect. The source and destination registers can be any of the 31 locations
in the on-chip register file. Note that this is the only MOVE instruction that
allows the source and destination registers to be in different files. This instruction also performs an implicit compare to 0 of the register data.

Fields

The assembler sets bit 9 (the M bit) in the instruction word to specify
whether the move is within a register file or if it crosses the register files.
The assembler sets M to 0 if the source and destination registers are in the
same file; it sets M to 1 if the registers are in different files.
The assembler sets bit 4 (the R bit) in the instruction word to specify which
file the registers are in. The assembler sets R to 0 if the registers are in file
A; it sets R to 1 if the registers are in file B.
Note that when M =0, R specifies the register file for both registers; if M = 1,
R specifies the register file for the source register

Machine
States
Status Bits

1,4
N
C
Z

1 if the 32-bit data moved is negative, 0 otherwise
Unaffected
1 if the 32-bit data moved is 0, 0 otherwise

V 0
Examples

Code
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

12-126

AO,Al
AO,Al
AO,Al
AO,Bl
AO,Bl
AO,Bl

Before

After

OOOOFFFFh
OOOOOOOOh
FFFFFFFFh
OOOOFFFFh
OOOOOOOOh
FFFFFFFFh

OOOOFFFFh
OOOOOOOOh
FFFFFFFFh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh

xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
OOOOFFFFh
OOOOOOOOh
FFFFFFFFh

NCZV

OxOO
Ox10
1xOO
OxOO
Ox10
1xOO

Move Field - Register to Indirect

Syntax

MOVE

Execution

field in Rs

Instruction
Words
Description

Rs. *Rd [. FJ
*Rd

15 14

MOVE

MOVE moves a field from the source register to the memory address contained in the destination register. This memory address is a bit address.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F parameter determines the field size and extension for the move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension. Rs and Rd must be
in the same register file.

Machine
States

The following typical cases assume that the destination address is aligned
on a 16-bit boundary:
16-Bit Field
1+(1),5

32-Bit Field
1 +(3),7

For other cases, see MOVE and MOVB Instructions Timing. Section 13.2.

Status Bits

N
C
Z
V

Examples

Assume that memory contains the following values before instruction execution:

Unaffected
Unaffected
Unaffected
Unaffected

Address
15500h
15510h
15520h

Data
OOOOh
OOOOh
OOOOh

Before
AO,*Al,O
AO,*Al,l
AO, *Al,O
AO,*Al,l
AO,*Al,O
AO,*Al,l
AO,*Al,O
AO,*Al,l

A1
00015500h
00015503h
0OO15508h
0001550Bh
0OO1550Dh
0001550Ch
0OO15512h
0OO15510h

After
FSO/1

5/x
x/8
13/x
x/16
19/x
x/24
27/x
x/32

@15500h @15510h @15520h
001Fh OOOOh OOOOh
07F8h OOOOh OOOOh
FFOOh 001Fh OOOOh
F800h 07FFh OOOOh
EOOOh
FFFFh OOOOh
FOOOh
FFFFh OOOFh
FFFCh 1 FFFh
OOOOh
FFFFh
FFFFh
OOOOh

12-127

Move Field - Register to
Indirect (Postincrementj

MOVE
Syntax

MOVE Rs, *Rd+ [, F]

Execution

field in Rs .... * Rd
Rd + field size .... Rd

Instruction
Words
Description

15 14

11 0 0

0 01

9
F

MOVE moves a field from the source register to the memory address co ......
tained in the destination register. This memory address is a bit address.
After the move, the contents of the destination register are postincremented
by the selected field size. The field size for the move is 1-32 bits, depending
on the selected field size; the field is right justified within the source register. The optional F parameter determines the field size and extension for the
move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension. Rs and Rd must be
in the same register file.

Machine
States

The following typical cases assume that the destination address is aligned
on a 16-bit boundary:

16-Bit Field
1+(1),5

32-Bit Field
1+(3),7

For other cases, see. MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z

Examples

Unaffected
Unaffected
Unaffected
Unaffected

Assume that memory contains the following values before instruction execution:

Address
15500h
15510h
15520h

Data
OOOOh
OOOOh
OOOOh

12-128

Move Field - Register to
Indirect (Postincrementj

MOVE
After

Before
A1

MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

AO, *Al+, 0
AO,*Al+,l
AO,*Al+,O
AO,*Al+,l
AO,*Al+,O
AO,*Al+,l
AO,*Al+,O
AO,*Al+,l

00015528h
00015525h
00015520h
0001551 Dh
00015516h
00015507h
00015507h
00015500h

FSO/1

5/x
x/8
13/x
x/16
19/x
x/24
27/x
x/32

0001552Dh
0001552Dh
0001552Dh
0001552Dh
0001 5529h
0001551Fh
0001551Fh
00015520h

@15500h @15510h @15520h

OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
FF80h
FF80h
FFFFh

OOOOh
OOOOh
OOOOh
EOOOh
FFCOh
7FFFh
FFFFh
FFFFh

1FOOh
1 FEOh
1 FFFh
1 FFFh
01FFh
OOOOh
0003h
OOOOh

12-129

Move Field - Register to
Indirect (Predecrement)

MOVE
Syntax

MOVE Rs, -*Rd [, FJ

Execution

Rd - field size
field in Rs -+

Instruction
Words

15 14

11
Description

* Rd

0 0 01

9
F

MOVE moves a field from the source register to the memory address contained in the destination register; the destination address is predecremented
by the field size. The memory address is a bit address. Before the move,
the field size is subtracted from the contents of the destination register to
determine the location that the field is moved to. (This value is also the final value for the register.)
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F parameter determines the field size and extension for the move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension. Rs and Rd must be
in the same register file.

Machine
States

The following typical cases assume that the destination address is aligned
on a 16-bit boundary:

16-Bit Field
2+(1 ),6

32-Bit Field
2+(3),8

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z

Examples

Unaffected
Unaffected
Unaffected
Unaffected

Assume that memory contains the following values before instruction execution:

Address
15500h
15510h
15520h
Register AO

12-130

Data
OOOOh
OOOOh
OOOOh

= FFFFFFFFh

Move Field - Register to
Indirect (Predecrement)

MOVE

Before
A1

MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

AO,-*Al,O
AO,-*Al,l
AO,-*Al,O
AO,-*Al,l
AO, -*Al, 0
AO, -*Al, 1
AO,-*Al,O
AO,-*Al,l

0001530h
000152Dh
0001528h
0001528h
0001523h
0001520h
0001524h
0001520h

After
FSO/1

5/x
x/8
13/x
x/16
19/x
x/24
27/x
x/32

000152Bh
0001525h
000151 Bh
0001518h
0001510h
0001508h
0001509h
0001500h

@15500h @15510h @15520h

OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
FFOOh
FEOOh
FFFFh

OOOOh
OOOOh
F800h
FFOOh
FFFFh
FFFFh
FFFFh
FFFFh

F800h
1FEOh
OOFFh
OOFFh
0007h
OOOOh
OOOFh
OOOOh

12-131

Move Field - Register to
Indirect with Offset

MOVE
Syntax

MOVE Rs, *Rd(offset) [, FJ

Execution

field in Rs -+ *(Rd + offset)

Instruction
Words

15 14 13 12 11

876

2
Rd

offset

Description

MOVE moves a field from the source register to the destination memory
memory address. The destination memory address is a bit address and is
formed by adding the contents of the destination register to the signed
16-bit offset. The field size for the move is 1-32 bits, depending on the
selected field size; the field is right justified within the source register. The
optional F parameter determines the field size and extension for the move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension. Rs and Rd must be
in the same register file.

Machine
States

The following typical cases assume that the destination address is aligned
on a 16-bit boundary:

16-Bit Field

32- Bit Field

3+(1),7

3+(3).9

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

12-132

N
C
Z
V

Unaffected
Unaffected
Unaffected
Unaffected

Move Field - Register to
Indirect with Offset

Examples

MOVE

Assume that memory contains the following values before instruction execution:
Address
15530h
15540h
15550h

Data
OOOOh
OOOOh
OOOOh

FFFFFFFFh

Code

Before

MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

00015530h
0001552Fh
0001552Dh
0001551Ch
00015435h
00014531h
0000D531 h
00015540h
0001 D530h
00015540h
00015548h
0001554Dh
00015520h
00015520h

A1
AO,*Al(OOOOh),1
AO,*Al(OOOlh),0
AO,*Al(OOOFh),0
AO,*Al(0020h),1
AO,*Al(OOFFh),0
AO,*Al(OFFFh),0
AO,*Al(7FFFh),1
AO,*Al(OFFF2h),1
AO,*Al(8000h),0
AO,*Al(OFFFOh),0
AO,*Al(OFFECh),1
AO,*Al(OFFECh),0
AO,*Al(OOlDh),0
AO,*Al(0020h),1

After
FSO/1

@15530h

@15540h

@15550h

x/1
5/x
8/x
x/13
16/x
19/x
x/22
x/25
27/x
31/x
x/31
32/x
32/x
x/32

0001h
001Fh
FOOOh
FOOOh
FFFOh
FFFFh
FFFFh
FFFCh
FFFFh
FFFFh
FFFOh
FEOOh
EOOOh
OOOOh

OOOOh
OOOOh
OOOFh
01 FFh
OOOFh
0007h
003Fh
07FFh
07FFh
7FFFh
FFFFh
FFFFh
FFFFh
FFFFh

OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
0007h
01FFh
1 FFFh
FFFFh

12-133

Move Field - Register to Absolute

MOVE
Syntax

MOVE Rs, @DAddress [, FJ

Execution

field in Rs ..... DAddress

Instruction
Words

15 14
0

IF I

IR I

16 LSBs of destination address
16 MSBs of destination address

Description

MOVE moves a field from the source register to the destination memory
address. The specified destination memory address is a linear bit address.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F parameter determines the field size and extension for the move:
F=O selects FSO
F=1 selects FS1
SETF sets the field size and extension.

Machine
States

The following typical cases assume that the destination address is aligned
on a 16-bit boundary:

32-Bit Field
3+(3),9

16-Bit Field
3+(1),7

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

C
Z
V

Examples

Unaffected
Unaffected
Unaffected
Unaffected

Assume that memory contains these values before instruction execution:

Address
15500h
15510h
15520h

Data
OOOOh
OOOOh
OOOOh

Before
FSO/1

MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

12-134

AO,@15500h,O
AO,@15503h,1
AO,@15508h,O
AO,@1550Bh,1
AO,@1550Dh,O
AO,@15510h,1
AO,@15512h,O
AO,@1550Ch,1

5/x
x/8
13/x
x/16
19/x
x/24
27/x
x/32

After
@15500h @15510h @15520h
001Fh
OOOOh
OOOOh
OOOOh
07F8h
OOOOh
FFOOh
001Fh
OOOOh
07FFh
F800h
OOOOh
FFFFh
EOOOh
OOOOh
OOOOh
OOFFh
FFFFh
OOOOh
1 FFFh
FFFCh
FOOOh
OFFFh
FFFFh

Move Field - Indirect to Register

Syntax

MOVE

Execution

field at

Instruction
Words
Description

*Rs. Rd [. FJ

* Rs

15 14

MOVE

MOVE moves a field from the source memory address to the destination
register. The contents of the source register specify the address of the field.
When the field is moved into the destination register, it is right justified and
sign extended or zero extended to 32 bits, according to the value of FE.
This instruction also performs an implicit compare to 0 of the field data.
The field size for the move is 1-32 bits, depending on the selected field size;
the optional F parameter determines the field size and extension for the
move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension. Rs and Rd must be
in the same register file.

Machine
States

The following typical cases assume that the source data is aligned on a
16-bit boundary:

16-Bit Field
3,6

32- Bit Field
5,8

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z

1 if the field-extended data moved to register is negative, a otherwise
Unaffected
1 if the field-extended data moved to register is 0, otherwise

12-135

MOVE
Examples

Move Field - Indirect to Register

Assume that memory contains the following values before instruction execution:
Data
7770h
7777h

Address
15500h
15510h
Register AO

0OO15500h

Code

FSO!1

MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

12-136

After

Before
*AO,Al,l
*AO,Al,O
*AO,Al,l
*AO,Al,O
*AO,Al,l
*AO,Al,O
*AO,Al,l
*AO,Al,O
*AO,Al,l
*AO,Al,O
*AO,Al,l
*AO,Al,O

x/1
5/x
x/5
12/x
x/12
18/x
x/18
27/x
x/27
31/x
x/31
32/x

FEO!1

x/1
O/x
x/1
1/x
x/O
O/x
x/1
1/x
x/O
O/x
x/1
x/x

NCZV

OOOOOOOOh
0OOOOO10h
FFFFFFFOh
0OOOO770h
0OOOO770h
0OO37770h
FFFF7770h
FF777770h
07777770h
77777770h
F7777770h
77777770h

Ox10
OxOO
1xOO
OxOO
OxOO
OxOO
1xOO
1xOO
OxOO
OxOO
1xOO
OxOO

MOVE

Move Field - Indirect to Indirect

Syntax

MOVE

Execution

field at *Rs -

Instruction
Words
Description

15 14

*Rs. *Rd [. FJ

*Rd
12

11 0 0 0

9
F

MOVE moves a field from a source address to a destination address. Both
memory addresses are bit addresses; the source register contains the address of the field and the destination register specifies the address that the
field is moved to. The field size for the move is 1-32 bits, depending on the
selected field size; the optional F parameter determines the field size and
extension for the move:
F=O selects FSO
F=1 selects FS1
SETF sets the field size and extension. Rs and Rd must be in the same register file.

Machine
States

The following typical cases assume that the source data and the destination
address are aligned on 16-bit boundaries:

16- Bit Field
3+(1 ),7

32-Bit Field
5+(3),11

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z
V

Unaffected
Unaffected
Unaffected
Unaffected

12-137

Move Field - Indirect to Indirect

MOVE

Examples

Assume that memory contains the following values before instruction execution:
Address

Data

Address

Data

15500h
15510h
15520h

FFFFh
FFFFh
FFFFh

15530h
15540h
15550h

OOOOh
OOOOh
OOOOh

Before

Code
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

*AO,*Al,l
*AO,*Al,O
*AO,*Al,l
*AO,*Al,O
*AO,*Al,l
*AO,*Al,O
*AO,*Al,l
*AO,*Al,O
*AO,*Al,l
*AO,*Al,O
*AO,*Al,l
*AO,*Al,O
*AO,*Al,O

12-138

After

00015500h
00015500h
00015500h
00015500h
00015504h
0001550Ah
0001550Dh
0001550Dh
00015505h
00015508h
00015508h
0001550Ah
00015500h

00015530h
00015534h
0001553Ah
0001553Fh
00015530h
00015530h
00015534h
00015530h
00015535h
00015536h
00015531h
00015530h
0001553Ah

FSO/1 @15530h @15540h @15550h

x/1
5/x
x/10
19/x
x/7
13/x
x/a
28/x
x/23
31/x
x/31
32/x
x/32

0001h
01FOh
FCOOh
aOOOh
007Fh
1 FFFh
OFFOh
FFFFh
FFEOh
FFCOh
FFFEh
FFFFh
FCOOh

OOOOh
OOOOh
OOOFh
FFFFh
OOOOh
OOOOh
OOOOh
OFFFh
OFFFh
FFFFh
FFFFh
FFFFh
FFFFh

OOOOh
OOOOh
OOOOh
0003h
OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
001 Fh
OOOOh
OOOOh
03FFh

Move Field - Indirect
(Postincrement) to Register

Syntax

MOVE *Rs+. Rd [. FJ

Execution

field at * Rs .... Rd
Rs + field size .... Rs

Instruction
Words

Description

15 14

MOVE

4
R

MOVE moves a field from memory to the destination register. The source
register contains the address of the field; after the move. the contents of the
source register are incremented by the field size. When the field is moved
into the destination register, it is right justified and sign extended or zero
extended, as specified by the selected field extension. This instruction also
performs an implicit compare to 0 of the field data.
The field size for the move is 1-32 bits, depending on the selected field size;
the optional F parameter determines the field size and extension for the
move:
F;;O selects FSO
F;;1 selects FS1
The SETF instruction sets the field size and extension. Rs and Rd must be
in the same register file.

Machine
States

The following typical cases assume that the source data is aligned on a
16-bit boundary:
.

16-Bit Field
3,6

32-Bit Field

5,8

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z

1 if the field-extended data moved to register is negative, 0 otherwise
Unaffected
1 if the field-extended data moved to register is 0, 0 otherwise

V 0

12-139

Move Field - Indirect
(Postincrementj to Register

MOVE
Examples

Assume that memory contains the following values before instruction execution:
Address

Data

15500h
15510h

7770h
7777h

Code

FSO/1

MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

*AO+,Al,l
*AO+,Al,l
*AO+,Al,O
*AO+,Al,O
*AO+,Al,l
*AO+,Al,O
*AO+,Al,l
*AO+,Al,O
*AO+,Al,l
*AO+,Al,O
*AO+,Al,l
*AO+,Al,O

12-140

x/1
x/5
5/x
12/x
x/12
18/x
x/18
27/x
x/27
31/x
x/31
32/x

After
FEO/1

x/O
x/O
1/x
O/x
x/1
1/x
x/O
O/x
x/1
1/x
x/O
x/x

NCZV

0OO15501h
0OO15505h
0OO15505h
0OO1550Ch
0OO1550Ch
0OO15512h
0OO15512h
0OO1551Bh
0OO1551Bh
0OO1551Fh
0OO1551Fh
0OO15520h

OOOOOOOOh
0OOOOO10h
FFFFFFFOh
0OOOO770h
0OOOO770h
FFFF7770h
0OO37770h
07777770h
FF777770h
F7777770h
77777770h
77777770h

Ox10
OxOO
1xOO
OxOO
OxOO
1xOO
OxOO
OxOO
1xOO
1xOO
OxOO
OxOO

Move Field -Indirect (Postincrementj

to Indirect (Postincrementj
Syntax

MOVE

Execution

field at *Rs ..... *Rd
Rs + field size ..... Rs
Rd + field size ..... Rd

Instruction
Words
Description

*Rs+, *Rd+ [, FJ

15 14

MOVE

oIF

6
Rs

2
Rd

MOVE moves a field from one memory address to another. The source register contains the bit address of the field; the destination register contains
the bit address of field's destination. After the move, the contents of both
instructions are incremented by the field size.
The field size for the move is 1-32 bits, depending on the selected field size;
the optional F parameter determines the field size and extension for the
move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.
If Rs and Rd specify the same register, the data read from the location
pointed to by the original contents of Rs is written to the location pointed
to by the incremented value of Rs(Rd). Rs and Rd must be in the same
register file.

Machine
States

The following typical cases assume that the source data and the destination
address are aligned on 16-bit boundaries:

16-Bit Field
4,7

32-Bit Field
6+(2),11

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z
V

Unaffected
Unaffected
Unaffected
Unaffected

12-141

Move Field - Indirect (Postincrementj
to Indirect (Postincrementj

MOVE
Examples

Assume that memory contains the following values before instruction execution:

Address
15500h
15510h
15520h

Data
FFFFh
FFFFh
FFFFh

Address
15530h
15540h
15550h

Data
OOOOh
OOOOh
OOOOh

MOVE *AO+,*Al+,F

Before

After

1
0
1
0
1
0
1
0
1
0
1
0
1

00015500h
0OO15505h
0001550Ah
0001550Dh
00015510h
00015511h
00015513h
0OO15510h
0OO1551Bh
00015510h
00015511h
00015510h
0OO15500h

0001553Dh
0001553Bh
0001553Fh
00015530h
00015532h
0001553Ah
0001553Fh
0001553Ah
00015534h
00015530h
0001553Dh
0001553Fh
00015530h

12-142

FSO/1
x/1
5/x
x/10
19/x
x/7
13/x
x/8
2B/x
x/23

31 Ix
x/31
32jx
x/32

0OO15501h
0OO1550Ah
00015514h
00015520h
0OO15517h
0OO1551Eh
0001551Bh
0001552Ch
0001552Fh
0001552Fh
00015530h
00015530h
00015520h

0001553Eh
0001553Dh
00015549h
00015543h
00015539h
00015547h
00015547h
00015556h
0001554Bh
0001554Fh
0001555Ch
0001555Fh
00015550h

@15530h @15540h @15550h
2000h
OOOOh
OOOOh
1 FOOh
OOOOh
OOOOh
BOOOh
01FFh
OOOOh
FFFFh
0007h
OOOOh
01 FCh
OOOOh
OOOOh
FCOOh
007Fh
OOOOh
BOOOh
007Fh
OOOOh
FCOOh
FFFFh
003Fh
FFFOh
07FFh
OOOOh
FFFFh
7FFFh
OOOOh
FFFFh
EOOOh
OFFFh
BOOOh
FFFFh
7FFFh
FFFFh
FFFFh
OOOOh

Move Field -Indirect
(Predecrement) to Register

Syntax

MOVE

Execution

Rs - field size -+ Rs
field at * Rs -+ Rd

Instruction
Words
Description

15 14

MOVE

-*Rs, Rd [, FJ

10
1

9
F

MOVE moves a field from memory to the destination register. The source
register contains a bit address; before the move, the contents of the source
register are decremented by the field size to form the address of the field.
(This value is also the final value for the register.)
The field size for the move is 1-32 bits, depending on the selected field size;
the optional F parameter determines the field size and extension for the
move:
F::::O selects FSO
F::::1 selects FS1
The SETF instruction sets the field size and extension.
When the field is moved into the destination register, it is right justified and
sign extended or zero extended to 32 bits according to the value of FE for
the particular F bit selected. This instruction also performs an implicit
compare to 0 of the field data.
Rs and Rd must be in the same register file. If Rs and Rd are the same register, the pointer information is overwritten by the data fetched.

Machine
States

The following typical cases assume that the source data is aligned on a
16-bit boundary:

16-Bit Field

32-Bit Field

4,7

6,9

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z

1 if the field-extended data moved to register is negative, 0 otherwise
Unaffected
1 if the field-extended data moved to register is 0, 0 otherwise

V 0

12-143

Move Field - Indirect
(Predecrement) to Register

MOVE
Examples

Assume that memory contains the following values before instruction execution:
Data
7770h
7777h

Address

15500h
15510h

Before
FSO!1

MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

-*AO,Al,l
-*AO,Al,O
-*AO,Al,l
-*AO,Al,O
-*AO,Al,l
-*AO,Al,O
-*AO,Al,l
-*AO,Al,O
-*AO,Al,l
-*AO,Al,O
-*AO,Al,l
-*AO,Al,O

12-144

x/1
5/x
x/5
12/x
x/12
18/x
x/18
27/x
x/27
31/x
x/31
32/x

After
FEO/1

x/O
1/x
x/O
O/x
x/1
1/x
x/O
O/x
x/1
1/x
x/O
x/x

0001551Fh
0001551Bh
0001551Bh
00015514h
00015514h
0001550Eh
0001550Eh
00015505h
00015505h
00015501h
00015501h
00015500h

OOOOOOOOh
OOOOOOOEh
OOOOOOOEh
00000777h
00000777h
0001 DDDDh
0001 DDDDh
03BBBBBBh
03BBBBBBh
3BBBBBB8h
3BBBBBB8h
77777770h

NCZV
Ox10
OxOO
OxOO
OxOO
OxOO
OxOO
OxOO
OxOO
OxOO
OxOO
OxOO
OxOO

Move Field - Indirect (Predecrement)
to Indirect (Predecrement)
Syntax

MOVE

Execution

Rs - field size ~ Rs
Rd - field size -+ Rd
(field)*Rs -+ (field)*Rd

Instruction
Words
Description

15 14

MOVE

-*Rs. -*Rd [. FJ

9
F

6
Rs

4
R

MOVE moves a field from one memory address to another. Both registers
contain bit addresses; before the move. the contents of both registers are
decremented by the field size. The source register then contains the address
of the field. and the destination register specifies the destination address for
the move.
The field size for the move is 1-32 bits, depending on the selected field size;
the optional F parameter determines the field size and extension for the
move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.
Rs and Rd must be in the same register file. If Rs and Rd are the same register, then the final contents of the register are its original contents decremented by twice the field size.

Machine
States

The following typical cases assume that the source data and the destination
address are aligned on 16-bit boundaries:

16- Bit Field
4+(1),8

32-Bit Field
6+(3),12

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z
V

Unaffected
Unaffected
Unaffected
Unaffected

12-145

Move Field - Indirect (Predecrement)
to Indirect (Predecrement)

MOVE

Examples

Assume that memory contains the following values before instruction execution:
Address
15500h
15510h
15520h

Data
FFFFh
FFFFh
FFFFh

Address
15530h
15540h
15550h

Data
OOOOh
OOOOh
OOOOh

MOVE -*AO,-*Al,F

Before

After

1
0
1
0
1
0
1
0
1
0
1
0
1

0OO15501h
0OO15505h
0OO1550Ah
0OO15513h
0OO1550Bh
0OO15517h
0OO15515h
0OO15529h
0OO1551Ch
0OO15527h
0OO15527h
0OO1552Ah
0OO15520h

0OO15531h
0OO15539h
0OO15544h
0OO15552h
0OO15537h
0OO1553Dh
0OO1553Ch
0OO1554Ch
0OO1554Ch
0OO15555h
0OO15550h
0OO15550h
0OO1555Ah

12-146

FSO/1
x/1
5/x
x/10
19/x

xl7
13/x
x/8
28/x
x/23
31/x

x/31
32/x
x/32

0OO15500h
0OO15500h
0OO1550hO
0OO15500h
0OO15504h
0OO1550Ah
0OO1550Dh
0OO1550Dh
0OO15505h
0OO15508h
0OO15508h
0OO1550Ah
0OO15500h

0OO15530h
0OO15534h
0OO1553Ah
0OO1553Fh
0OO15530h
0OO15530h
0OO15534h
0OO15530h
0OO15535h
0OO15536h
0OO15531h
0OO15530h
0OO1553Ah

@15530h @15540h @15550h

0OO1h
01FOh
FCOOh
8000h
007Fh
1 FFFh
OFFOh
FFFFh
FFEOh
FFCOh
FFFEh
FFFFh
FCOOh

OOOOh
OOOOh
OOOFh
FFFFh
OOOOh
OOOOh
OOOOh
OFFFh
OFFFh
FFFFh
FFFFh
FFFFh
FFFFh

OOOOh
OOOOh
OOOOh
0OO3h
OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
001Fh
OOOOh
OOOOh
03FFh

Move Field - Indirect with Offset to Register

Syntax

MOVE

Execution

field at (* Rs + offset)

Instruction
Words

MOVE

*Rs(offset), Rd [, F]

15 14 13

876

2
Rd

offset

Description

This MOVE instruction moves a field from a memory address to the destination register. The address of the source data is formed by adding a
signed, 16-bit offset to the contents of Rs. When the field is moved into
the destination register, it is right justified and sign extended or zero extended to 32 bits, according to the value of the current FE bit. This instruction also performs an implicit compare to 0 of the field data.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F parameter determines the field size and extension for the move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.
Rs and Rd must be in the same register file.

Machine
States

The following typical cases assume that the source data is aligned on a
16-bit boundary:

16-Bit Field

5,11

32- Bit Field
7,13

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z

1 if the field-extended data moved to register is negative, 0 otherwise
Unaffected
1 if the field-extended data moved to register is 0, 0 otherwise

V 0

12-147

MOVE

Examples

Move Field - Indirect with Offset to Register

Assume that memory contains the following values before instruction execution:
Address

Data

15530h
15540h
15550h

3333h
4444h
5555h
Before

Code

MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

12·148

*AO(OOOOh),Al,l
*AO(OOO3h),Al,l
*AO (OOOlh) ,Al,O
*AO(OOOFh),Al,O
*AO(OO20h),Al,l
*AO(OOFFh),Al,O
*AO(OFFFh) ,Al,O
*AO(7FFFh),Al,l
*AO(OFFF2h),Al,l
*AO(8000h) ,Al,O
*AO(OFFFOh),Al,O
*AO(OFFEOh),Al,l
*AO(OFFECh) ,Al,O
*AO(OOlDh) ,Al,O
*AO (0020h) ,Al, 1

AO
00015530h
0001552Fh
0001552Fh
0001552Dh
0001551Ch
00015435h
00014531h
OOOOD531h
00015540h
0001 D530h
00015540h
00015558h
0001554Dh
00015520h
00015520h

After

FSO!1 FEO!1

NCZV.

x/1
x/2
5/x
8/x
x/13
16/x
19/x
x/22
x/25
27/x
31/x
x/31
32/x
32/x
x/32

FFFFFFFFh
OOOOOOOOh
00000013h
00000043h
00000443h
00004333h
FFFC3333h
00043333h
01110CCCh
FC443333h
44443333h
D5444433h
AAA22219h
AAAA2221h
55554444h

1xOO
Ox10
OxOO
OxOO
OxOO
OxOO
1xOO
OxOO
OxOO
1xOO
OxOO
1xOO
1xOO
1xOO
OxOO

x/1
x/O
O/x
1/x
x/O
1/x
1/x
x/1
x/O
1/x
O/x
x/1
O/x
1/x
x/O

Move Field - Indirect with Offset
to Indirect (Postincrementj
Syntax

MOVE

Execution

field at (* Rs + offset)
Rd + field size -> Rd

Instruction
Words

15 14

MOVE

*Rs(offset), *Rd+ [, F}

11
0

* Rd

oIF

876
Rs

2
Rd

offset

Description

MOVE moves a field from the one memory location to another. Both the
source and destination registers contain bit addresses. The source memory
address is formed by adding the contents of the source register to the
signed 16-bit offset. The destination register contains the address of the
field's destination; after the move, the contents of Rd are incremented by
the selected field size.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F parameter determines the field size and extension for the move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.
Rs and Rd must be in the same register file.

Machine
States

The following typical cases assume that the source data and the destination
address are aligned on 16-bit boundaries:

16-Bit Field
5+(1),12

32-Bit Field
7+(3),16

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z
V

Unaffected
Unaffected
Unaffected
Unaffected

12-149

Move Field - Indirect with Offset
to Indirect (Postincrement)

MOVE
Examples

Assume that memory contains the following values before instruction execution:

Address
15500h
15510h
15520h

Data

OOOOh
OOOOh
OOOOh

Address
15530h
15540h
15550h

Before
AO
MOVE *AO(OOOOh),*Al+,l 00015530h
MOVE *AO(OOOlh),*Al+,l 0001552Fh
MOVE *AO(OOOFh),*Al+,l 00015520h
MOVE *AO(0020h),*Al+,1 0001551 Ch
MOVE *AO(OOFFh),*Al+,l 00015535h
MOVE *AO(OFFFh),*Al+,l 00015531 h
MOVE *AO(7FFFh),*Al+,1 00000531 h
MOVE *AO(OFFF2h),*Al+,1 00015540h
MOVE *AO(8000h),*Al+,1 0001 0530h
MOVE *AO(OFFFOh),*Al+,l 00015540h
MOVE *AO(OFFEOh),*Al+,l 00015558h
MOVE *AO(OFFECh),Al+,l 00015540h
MOVE *AO(OOlDh),Al+,l
00015520h
MOVE *AO(0020h),Al+,1
00015520h

12-150

Data
3333h
4444h
5555h
After

A1
FSO/1
0015500h
x/1
00015504h 5/x
0001550Ch 8/x
00015f' JDh x/13
0001550Ch 16/x
00015510h 19/x
00015508h x/22
0015500h x/25
00015503h 27 Ix
00015501 h 31 Ix
00015508h x/31
0001550Ah 32/x
00015510h 32/x
00015510h x/32

A1
00015501h
00015509h
00015514h
0001551 Ah
0001551 Ch
00015523h
0001551Eh
00015519h
0001551Eh
0001552Ah
00015527h
00015528h
00015530h
00015530h

@15500h
@15520h
@15610h
0001h OOOOh OOOOh
0130h OOOOh OOOOh
3000h 0004h OOOOh
6000h 0088h OOOOh
3000h 0433h OOOOh
OOOOh 3333h 0004h
3300h 0433h OOOOh
OCCCh 0111 h OOOOh
9998h 2221h OOOOh
6666h 8888h OOOOh
3300h 4444h 0055h
3200h 4444h 0155h
OOOOh 2221 h AAAAh
OOOOh 4444h 5555h

Move Field - Indirect with Offset

to Indirect with Offset

MOVE

Syntax

MOVE

Execution

field at (*Rs + SOffset)

Instruction
Words

15 14
1

Description

*Rs(SOffset), *Rd(DOffset) {, FJ

(*Rd + DOffset)

6
Rs
source offset
destination offset
F

4
R

This MOVE instruction moves a field from one memory location to another.
Both the source and destination registers contain bit addresses. The address of the source address is formed by adding a signed 16-bit offset to
the contents of the source register. The address of the destination location
is formed by adding a signed 16-bit offset to the contents of the destination
register.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F parameter determines the field size and extension for the move:

F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.
Rs and Rd must be in the same register file.

Machine
States

The following typical cases assume that the source data and the destination
address are aligned on 16-bit boundaries:

16-Bit Field

32-Bit Field

5+(1).15

7+(3),19

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z

Unaffected
Unaffected
Unaffected
Unaffected

12-151

Move Field - Indirect with Offset
to Indirect with Offset

MOVE
Examples

Code

Assume that memory contains the following values before instruction execution:

Address

Data

Address

Data

15500h
15510h
15520h

OOOOh
OOOOh
OOOOh

15530h
15540h
15550h

3333h
4444h
5555h

Before

AO
MOVE *AO(0000h),*A1(0000h),1
00015530h
MOVE *AO(0001h),*A1(0000h),0
0001552Fh
MOVE *AO(000Fh),*A1(000Fh),0
0001552Dh
MOVE *AO(0020h),*A1(001Dh) ,1
0001551Ch
MOVE *AO(OOFFh) ,*A1(OFFF8h),0
00015435h
MOVE *AO(OFFFh),*A1(OFFFh),0
00014531h
MOVE *AO(7FFFh),*A1(8000h) ,1
OOOOD531h
MOVE *AO(OFFF2h),*A1(7FFFh) ,1
00015540h
MOVE *AO(8000h),*A1(0020h) ,0
0001 D530h
MOVE *AO(OFFFOh) ,*A1(0010h) ,0
00015540h
MOVE *AO(OFFEOh),*A1(OFFEOh),1 00015558h
MOVE *AO(OFFECh),*A1(OFFECh),O 0001554Dh
MOVE *AO(001Dh),*A1(OO20h),O
00015520h
MOVE *AO(0020h),*A1(OO20h),1
00015520h

12-152

After
A1
FSO/1
0015500h
x/1
00015504h 5/x
000154FDh 8/x
0001 54FOh x/13
00015514h 16/x
00014511 h 19/x
0001 D508h x/22
0000D501 h x/25
000154E3h 27/x
000154F1 h 31/x
00015528h x/31
0001551 Dh 32/x
000154FOh 32/x
000154FOh x/32

@15500h
@15520h
@15510h
0001h OOOOh OOOOh
0130h OOOOh OOOOh
3000h 0004h OOOOh
5000h 0088h OOOOh
3000h 0433h OOOOh
OOOOh 3333h 0004h
3300h 0433h OOOOh
OCCCh 0111 h OOOOh
9998h 2221h OOOOh
6666h 8888h OOOOh
3300h 4444h 0055h
3200h 4444h 0155h
OOOOh 2221h ~h
OOOOh 4444h 5555h

Move Field - Absolute to Register

Syntax

MOVE @SAddress. Rd [. FJ

Execution

field at SAddress

Instruction
Words

15 14
0

MOVE

IF I

IR I

2
Rd

16 LSBs of source address
16 MSBs of source address

Description

This MOVE instruction moves a field from memory to the destination register. The field data for the move is contained at a source-memory bit address. When the field is moved into the destination register, it is right
justified and sign extended or zero extended to 32 bits according to the
selected value of FE. This instruction also performs an implicit compare to
o of the field data.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F parameter determines the field size and extension for the move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.

Machine
States

The following typical cases assume that the source data is aligned on a
16-bit boundary:

16-Bit Field
5,15

32-Bit Field
7,13

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z

1 if the field-extended data moved to register is negative, 0 otherwise
Unaffected
1 if the field-extended data moved to register is 0, 0 otherwise

V 0

12-153

Move Field - Absolute to Register

MOVE

Examples

Assume that memory contains the following values before instruction execution:
Address
15500h
15510h

Data
7770h
7777h

----

r.nrlA

FEO/1

MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

12-154

After

Before
@15500h,Al,1
@15500h,Al,O
@15503h,Al,1
@15500h,Al,O
@1550Dh,Al,1
@15504h,Al,O
@15500h,Al,1
@15500h,Al,O
@15500h,Al,1
@15501h,Al,O
@15501h,Al,1
@15500h,Al,O

x/O
O/x
x/1
O/x
x/1
1/x
x/O
O/x
x/1
O/x
x/1
x/x

FSO/1

x/1
5/x
x/5
12/x
x/12
18/x
x/18
27/x
x/27
30/x
x/30
32/x

NCZV

OOOOOOOOh
0OOOOO10h
OOOOOOOEh
0OOOO770h
FFFFFBBBh
FFFF7777h
0OO37770h
07777770h
FF777770h
3BBBBBB8h
FBBBBBB8h
77777770h

Ox10
OxOO
OxOO
OxOO
1xOO
1xOO
OxOO
OxOO
1xOO
OxOO
1xOO
OxOO

MOVE

Move Field - Absolute to Indirect (Postincrement)

Syntax

MOVE @SAddress, *Rd+ [, FJ

Execution

field at SAddress -+ *Rd
Rd + field size -+ Rd

Instruction
Words

15 14
1

1 Flo

16 LSBs of source address
16 MSBs of source address

Description

This MOVE instruction moves a field from one location in memory to another. The source address is a 32-bit address; the destination address is
specified by the contents of Rd. After the move, the contents of the destination register are incremented by the field size.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F parameter determines the field size and extension for the move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.
Rs and Rd must be in the same register file.

Machine
States

The following typical cases assume that the source data and the destination
address are aligned on 16-bit boundaries:

16-Bit Field

32-Bit Field

5+(1),15

7+(3),19

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z
V

Unaffected
Unaffected
Unaffected
Unaffected

12-155

MOVE

Move Field - Absolute to Indirect (Postincrement)

Examples

Assume that memory contains the following values before instruction execution:

Address

Data

Address

Data

15500h
15510h
15520h

FFFFh
FFFFh
FFFFh

15530h
15540h
15550h

OOOOh
OOOOh
OOOOh

Code

MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

12-156

Before

@15500,*Al+,l
@15500,*Al+,O
@15500,*Al+,l
@15500,*Al+,O
@15504,*Al+,l
@1550A,*Al+,O
@1550D,*Al+,l
@1550D,*Al+,O
@15505,*Al+,l
@15508,*Al+,O
@15508,*Al+,l
@1550A,*Al+,O
@15500,*Al+,l

00015530h
00015534h
0001553Ah
0001553Fh
00015530h
00015530h
00015534h
00015530h
00015535h
00015536h
00015531h
00015530h
0001553Ah

After
A1

00015531h
00015539h
0OO15544h
00015552h
00015537h
0001553Dh
00015536h
0001554Ch
0001554Dh
00015555h
00015548h
00015550h
0001555Ah

FEO!1
x/1
5/x
x/10
19/x
x!7
13/x
x/8
28/x
x/23
31/x
x/31
32/x
x/32

00015531h
00015539h
0OO15544h
00015552h
00015537h
0001553Dh
00015536h
0001554Ch
0001554Dh
00015555h
00015548h
00015550h
0001555Ah

@15500h
@15526h
@15510h
0001h OOOOh OOOOh
01FOh OOOOh OOOOh
FCOOh OOOFh OOOOh
8000h FFFFh 0003h
007Fh OOOOh OOOOh
1FFFh OOOOh OOOOh
OFFOh OOOOh OOOOh
FFFFh OFFFh OOOOh
FFEOh OFFFh OOOOh
FFCOh FFFFh 001 Fh
FFFEh FFFFh OOOOh
FFFFh FFFFh OOOOh
FCOOh FFFFh 03FFh

Move Field - Absolute to Absolute
Syntax

MOVE

Execution

field at SAddress -+ DAddress

Instruction
Words

@SAddress. @DAddress [. FJ

15 14

IF I

MOVE

o
0

16 LSBs of source address
16 MSBs of source address
16 LSBs of destination address
16 MSBs of destination address

Description

This MOVE instruction moves a field from one location in memory to another. Both memory addresses are 32-bit addresses.
The field size for the move is 1-32 bits, depending on the selected field size;
the field is right justified within the source register. The optional F parameter determines the field size and extension for the move:
F=O selects FSO
F=1 selects FS1
The SETF instruction sets the field size and extension.

Machine
States

The following typical cases assume that the source data and the destination
address are aligned on 16-bit boundaries:

16- Bit Field
7+(1),12

32-Bit Field
9+(3),27

For other cases, see MOVE and MOVB Instructions Timing, Section 13.2.

Status Bits

N
C
Z
V

Unaffected
Unaffected
Unaffected
Unaffected

12-157

Move Field - Absolute to Absolute

MOVE
Examples

Assume that memory contains the following values before instruction execution:
Address

Data

15500h
15510h
15520h

FFFFh
FFFFh
FFFFh

"1!'~"'nL

',","'.,;)VII

"nnnL..
VVVVII

15540h
15550h

OOOOh
OOOOh

Code

Before
FSO{1

MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE

12-158

@15500h,@15530h,1
@15500h,@15534h,O
@15500h,@1553Ah,1
@15500h,@1553Fh,O
@15504h,@15530h,1
@1550Ah,@15530h,O
@1550Dh,@15534h,1
@1550Dh,@15530h,O
@15505h,@15535h,1
@15508h,@15536h,O
@15508h,@15531h,1
@1550Ah,@15530h,O
@15500h,@1553Ah,O

x/1
5/x
x/10
19/x
x/7
13/x
x/8
28/x
x/23
31/x
x/31
32/x
x/32

After

@15530h @15540h @15550h

0OO1h
01FOh
FCOOh
8000h
007Fh
1 FFFh
OFFOh
FFFFh
FFEOh
FFCOh
FFFEh
FFFFh
FCOOh

OOOOh
OOOOh
OOOFh
FFFFh
OOOOh
OOOOh
OOOOh
OFFFh
OFFFh
FFFFh
FFFFh
FFFFh
FFFFh

OOOOh
OOOOh
OOOOh
0OO3h
OOOOh
OOOOh
OOOOh
OOOOh
OOOOh
001Fh
OOOOh
OOOOh
03FFh

Move Immediate - 16 Bits

Syntax

MOVI

EXBcution

IW ..... Rd

Instruction
Words

15 14 13 12 11

MOVI

IW. Rd [. W}

000

10
o

987
o

5
o

16-bit value

Description

MOVI stores a 16-bit. sign-extended immediate value in the destination
register. (lW in the instruction syntax represents the 16-bit value.)
The assembler uses the short form if the immediate value has been previously defined and is in the range -32.768 through 32.767. You can force
the assembler to use the short form by following the register operand with

.W:
MOVI IW,Rd,W

The assembler truncates the upper bits and issue an appropriate warning
message.

Machine
States
Status Bits

2.8
N
C
Z

1 if the data being moved is negative. 0 otherwise
Unaffected
1 if the data being moved is O. 0 otherwise

V 0
Examples

Code

After

MOVI
MOVI
MOVI
MOVI
MOVI
MOVI
MOVI

32767,AO
1,AO
O,AO
-l,AO
-32768,AO
OOOOh,AO
7FFFh,AO

00007FFFh
00000001h
OOOOOOOOh
FFFFFFFFh
FFFF8000h
OOOOOOOOh
00007FFFh

NCZV

OxOO
OxOO
Ox10
1xOO
1xOO
Ox10
OxOO

12-159

Move Immediate - 32 Bits

MOVI
Syntax

MOVI IL, Rd [, LJ

Execution

Instruction
Words

15 14 13 12
0
0
0
0

10
0

I
Description

9
6
8
7
1
0
1
16 LSBs of IL

16 MSBs of IL

MOVI stores a 32-bit immediate value in the destination register. (lL in the
instruction syntax represents the 32-bit value.)
The assembler uses this opcode if it cannot use the MOVI IW, Rd opcode,
or if the long opcode is forced by following the register operand with ,L:
MOVI IL,Rd,L

Machine
States
Status Bits

3,12
N
C
Z

1 if the data being moved is negative, 0 otherwise
Unaffected
1 if the data being moved is 0, 0 otherwise

V 0
Examples

12-160

Code

After

MOVI 2147483647,AO
MOVI
32768,AO
MOVI
-32769,AO
MOVI -2147483648,AO
MOVI
8000h,AO
MOVI OFFFFFFFFh,AO
MOVI
OFFFFh,AO,L

AO
7FFFFFFFh
00008000h
FFFF7FFFh
80000000h
00008000h
FFFFFFFFh
FFFFFFFFh

NCZV

OxOO
OxOO
1xOO
1xOO
OxOO
1xOO
1xOO

Move Constant (5 Bits)

Syntax

MOVK

Execution

Instruction
Words

15 14

Description

MOVK

K.Rd

Rd
13

10 0 0

7
K

MOVK stores a 5-bit constant in the destination register. (K in the instruction syntax represents the constant.) The constant is treated as an
unsigned number in the range 1-32, where K = 0 in the opcode corresponds to a value of 32. The resulting constant value is zero extended to
32 bits.
Note that you cannot set a register to 0 with this instruction. You can clear
a register by XORing the register with itself; use CLR Rd (an alternate
mnemonic for XOR) to accomplish this. Both these methods alter the Z bit
(set it to 1).

Machine
States

1,4

Status Bits

N
C
Z
V

Examples

Code

Unaffected
Unaffected
Unaffected
Unaffected

After

AO
MOVK
MOVK
MOVK
MOVK

l,AO
S,AO
16,AO
32,AO

00000001h
00000008h
00000010h
00000020h

12-161

MOVX

Move X Half of Register

Syntax

MOVX Rs. Rd

Exacution

RsX

Instruction
Words
Description

15 14

RdX
13

12
0

MOVX moves the X half of the source register (16 LSBs) to the X half of
the destination register. The Y halves of both registers are unaffected.
You an also use the MOVX and MOVY instructions for handling packed
16-bit quantities and XY addresses. You can use the RL instruction to
swap the contents of X and Y.
Rs and Rd must be in the same register file.

Machine
States

1.4

Status Bits

N
C
Z
V

Examples

Code

Before

MOVX AO/A!
MOVX AO/A!
MOVX AO/AI

OOOOOOOOh

Unaffected
Unaffected
Unaffected
Unaffected

12-162

12345678h

FFFFFFFFh

After
A1

FFFFFFFFh
OOOOOOOOh
OOOOOOOOh

00005678h

FFFFOOOOh
OOOOFFFFh

MOVY

Move Y Half of Register

Syntax

MOVY Rs, Rd

Execution

RsY

Instruction
Words

15 14

RdY
13

Description

MOVY moves the Y half of the source register (16 MSBs) to the Y half of
the destination register. The X halves of both registers are unaffected.
You an also use the MOVX and MOVY instructions for handling packed
16-bit quantities and XY addresses. You can use the RL instruction to
swap the contents of X and Y.
Rs and Rd must be in the same register file.

Machine
States

1,4

Status Bits

N
C
Z
V

Examples

Code

Before

MOVY AD,A!
MOVY AD,A!
MOVY AD,A!

OOOOOOOOh

Unaffected
Unaffected
Unaffected
Unaffected

12345678h

FFFFFFFFh

After
A1

FFFFFFFFh
OOOOOOOOh
OOOOOOOOh

OOOOFFFFh
12340000h

FFFFOOOOh

12-163

M PYS

Multiply Registers - Signed

Syntax

MPYS RS,Rd

Execution

Rd Even: Rs x Rd
Rd Odd: Rs x Rd

Instruction
Words
Description

15 14 13
0
0

-+
-+

Rd:Rd+1
Rd
10

0
I

MPYS performs a signed multiply of a variably-sized field in the source register by the 32 bits in the destination register. This produces a 32-bit to
a 64-bit result, depending on the register and field definitions. Note that
Rs and Rd must be in the same register file.
The value of field size 1 (FS1) defines the size of the multiplier in Rs. FS1
may have any even value n from 2 to 32 (that is, n = 2, 4, 6 ... 30, 32).
The instruction executes a 32-bit-by-n-bit mUltiply - multiplying the 32 bits
in Rd by the n bits in Rs. All values are signed. The MSB of the source field
(bit n - 1 in Rs) defines the sign of the field; the bits to the left of bit n are
ignored. The MSB of Rd defines the sign of the multiplicand.
Contents of Rs (n = FS1):
31
n-1
n-bit multiplier

Contents of Rd:

32-bit multiplicand

sign bit

MPYS has two modes, depending on whether Rd is even or odd:
•

Rd Even:
MPYS multiplies the contents of Rd by the n-bit field in Rs, and stores
the result in two consecutive registers, Rd and Rd+1. (For example,
if Rd=B4, the result is stored in registers B4 and B5.) The result is
sign extended and right justified; the 32 MSBs are stored in Rd and
the 32 LSBs are stored in Rd+1. Note that all 32 bits of both registers
are used, regardless of the field size of the multiply.
Do not use A14 or B14 as the destination register, because Rd+1
(A15 or B15) is the stack pointer register (SP). It is not desirable to
write over the contents of the SP.
Contents of Rd (even register):
~

I sign I
•

Contents of Rd+1 (odd register):

n MSBs of result

32 LSBs of result

Rd Odd:
MPYS multiplies the contents of Rd by the n-bit field in Rs, and stores
the 32 LSBs of the result in Rd; Rs is not changed. If the result is
greater than 32 bits, the extra MSBs are discarded, regardless of the
field size.
Contents of Rd (odd register):

32 MSBs are discarded

12-164

0
32 LSBs of result

Multiply Registers - Signed

Machine
States
Status Bits

5 + FS1/2, 8 + FS1/2
1 if the result is negative, 0 otherwise
Unaffected
1 if the result is 0, 0 otherwise
Unaffected

C
Z

Example 7

MPYS

MPYS Al, AO

Before

Example 2

After

FS1

NCZV

OOOOOOOOh
7FFFFFFFh
7FFFFFFFh
FFFFFFFFh
FFFFFFFFh
80000000h
80000000h
80000001h
8040156Fh
8040156Fh
8040156Fh
8040156Fh
8040156Fh
8040156Fh
8040156Fh
8040156Fh
8040156Fh

OOOOOOOOh
7FFFFFFFh
FFFFFFFFh
7FFFFFFFh
FFFFFFFFh
7FFFFFFFh
80000000h
80000000h
7FF3B074h
7FF3B074h
7FF3B074h
7FF3B074h
7FF3B074h
7FF3B074h
7FF3B074h
7FF3B074h
7FF3B074h

32
32
32
32
32
32
32
32
32
24
20
16
14
8
6
4
2

OOOOOOOOh
3FFFFFFFh
FFFFFFFFh
FFFFFFFFh
OOOOOOOOh
COOOOOOOh
40000000h
3FFFFFFFh
C0262CDCh
000624B1h
FFFE28B2h
000027B2h
00OOO7C2h
FFFFFFC6h
00OOOO05h
FFFFFFFEh
OOOOOOOOh

OOOOOOOOh
00000001h
80000001h
80000001h
00000001h
80000000h
OOOOOOOOh
80000000h
53E486F8h
53E486F8h
594486F8h
17EC86F8h
1 C0206F8h
1 D0766F8h
FCFF3BF8h
01004158h
OOOOOOOOh

Ox1x
OxOx
1xOx
1xOx
OxOx
1 xOx
OxOx
OxOx
1xOx
OxOx
1xOx
OxOx
OxOx
1xOx
OxOx
1xOx
Ox1x

FS1

NCZV

OOOOOOOOh
7FFFFFFFh
7FFFFFFFh
FFFFFFFFh
FFFFFFFFh
80000000h
80000000h
80000001h
7FF3B074h
7FF3B074h
7FF3B074h
7FF3B074h
7FF3B074h
7FF3B074h
7FF3B074h
7FF3B074h
7FF3B074h

OOOOOOOOh
7FFFFFFFh
7FFFFFFFh
7FFFFFFFh
FFFFFFFFh
7FFFFFFFh
80000000h
80000000h
80401056h
80401056h
80401056h
80401056h
80401056h
80401056h
80401056h
80401056h
80401056h

32
32
32
32
32
32
32
32
32
24
20
16
14
8
6
4
2

unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged

OOOOOOOOh
0OOOOOO1h
80000001h
80000001h
00000001h
80000000h
OOOOOOOOh
80000000h
53E486F8h
53E486F8h
594486F8h
17EC86F8h
1 C0206F8h
1 D0766F8h
FCFF3BF8h
01004158h
OOOOOOOOh

Ox1x
Ox Ox
1xOx
1xOx
OxOx
1 xOx
OxOx
OxOx
1xOx
OxOx
1xOx
OxOx
OxOx
1xOx
OxOx
1xOx
Ox1x

MPYS AO,Al

Before

After

12-165

MPYU

Multiply Registers - Unsigned

Syntax

MPYU

Execution

Rd Even: Rs x Rd
Rd Odd: Rs x Rd

Instruction
Words

15 14
i

I0
Description

Rs, Rd

13
0

-+
-+

Rd:Rd+1
Rd
10

6
Rs

4
i

0
i

MPYU performs an unsigned multiply of a variably-sized field in the source
register by the 32 bits in the destination register. This produces a 32-bit to
a 64-bit result, depending on the register and field definitions. Note that
Rs and Rd must be in the same register file.
The value of field size 1 (FS1) defines the size of the multiplier in Rs. FS1
may have any even value n from 2 to 32 (that is, n = 2, 4, 6 ... 30, 32).
The instruction executes a 32-bit-by-n-bit multiply - multiplying the 32 bits
in Rd by the n bits in Rs. All values are unsigned.
Contents of Rs (n = FS1):
31
n n-1

I ignored I

n-bit multiplier

Contents of Rd:

32-bit multiplicand

MPYS has two modes, depending on whether Rd is even or odd:
•

Rd Even:
MPYU mUltiplies the contents of Rd by the n-bit field in Rs, and
stores the result in two consecutive registers, Rd and Rd+1. (For
example, if Rd=B4, the result is stored in registers B4 and B5.) The
result is zero extended and right justified; the 32 MSBs are stored in
Rd and the 32 LSBs are stored in Rd+1. Note that all 32 bits of both
registers are used, regardless of the field size of the multiply.
Do not use A14 or B14 as the destination register, because Rd+1
(A15 or B15) is the stack pointer register (SP). It is not desirable to
write over the contents of the S P.
Contents of Rd (even register):
~

I
•

Contents of Rd+1 (odd register):

n MSBs of result

32 LSBs of result

Rd Odd:
MPYU multiplies the contents of Rd by the n-bit field in Rs, and
stores the 32 LSBs of the result in Rd; Rs is not changed. If the result
is greater than 32 bits, the extra MSBs are discarded, regardless of the
field size.
Contents of Rd (odd register):

32 MSBs are discarded

12-166

0
32 LSBs of result

Multiply Registers - Unsigned

Machine
States

MPYU

Rs nonnegative: 5 + FS1/2, 8 + FS1/2
Rs negative: 6 + FS1/2, 9 + FS1/2
Unaffected
Unaffected
1 if the result is 0, 0 otherwise
Unaffected

Status Bits

N
C
Z
V

Example 1

MPYU AI,AO

Before

After

FS1

NCZV

FFFFOOOOh
FFFFOOOOh
FFFFOOOOh
FFFFOOOOh
FFFFOOOOh
08001056h
08001056h
08001056h
08001056h
08001056h
08001056h
08001056h

10000000h
10001010h
10001 01 Oh
10001 01 Oh
10001010h
0003B074h
0003B074h
0003B074h
0003 B074h
0003B074h
0003B074h
0003B074h

32
32
16
8
4
32
16
14
8
6
4
2

OFFFFOOOh
1000000Fh
0000100Fh
OOOOOOOFh
OOOOOOOOh
00001D83h
00000583h
00000183h
00000003h
00000001h
OOOOOOOOh
OOOOOOOOh

OOOOOOOOh
EFFOOOOOh
EFFOOOOOh
FFFOOOOOh
OOOOOOOOh
DC4486F8h
AB4286F8h
A31786F8h
A00766F8h
A0035178h
20004158h
OOOOOOOOh

xxOx
xxOx
xxOx
xxOx
xx1x
xxOx
xxOx
xxOx
xxOx
xxOx
xxOx
xx1x

Example 2

MPYU AO,AI

Before

After

FS1

10000000h
10001 01 Oh
10001 01 Oh
10001010h
10001010h
0003 B074h
0003 B074h
0003 B074h
0003B074h
0003 B074h
0003 B074h
0003 B074h

FFFFOOOOh
FFFFOOOOh
FFFFOOOOh
FFFFOOOOh
FFFFOOOOh
08001056h
08001056h
08001056h
08001056h
08001056h
08001056h
08001056h

32
32
16
8
4
32
16
14
8
6
4
2

unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged

NCZV

OOOOOOOOh
EFFOOOOOh
EFFOOOOOh
FFFOOOOOh
OOOOOOOOh
DC4486F8h
AB4286F8h
A31786F8h
A00766F8h
A0035178h
20004158h
OOOOOOOOh

xxOx
xxOx
xxOx
xxOx
xx1x
xxOx
xxOx
xxOx
xxOx
xxOx
xxOx
xx1x

12-167

NEG

Negate Register

Syntax

NEG

Execution

2s complement of Rd

Instruction
Words
Description
Machine
States

Rd
-+

15 14

6
0

NEG stores the 2s complement of the contents of the destination register
back into the destination register.
1,4

Status Bits

N
C
Z
V

Examples

Code

Before

After

NEG
NEG
NEG
NEG
NEG
NEG

AO
OOOOOOOOh
55555555h
7FFFFFFFh
80000000h
80000001h
FFFFFFFFh

NCZV
0010
1100
1100
1101
0100
0100

12-168

1 if
1 if
1 if
1 if

AD
AD
AD
AD
AD
AD

the result is negative, 0 otherwise
there is a borrow (Rd ¢ 0),0 otherwise
the result is 0, 0 otherwise
there is an overflow (Rd = 80000000h), 0 otherwise

AO
OOOOOOOOh
AAAAAAABh
80000001h
80000000h
7FFFFFFFh
00000001h

Negate Register with Borrow

Syntax

NEGB

Execution

(2s complement of Rd) - C

Instruction
Words
Description

Machine
States

NEGB

15 14

10 0 0 0 0 0

..... Rd
9

NEGB takes the 2s complement of the destination register's contents and
decrements by 1 if the borrow bit (C) is set; the result is stored in the destination register. This instruction can be used in sequence with itself and
with the NEG instruction for negating multiple-register quantities.
1,4

Status Bits

N
C
Z
V

Examples

Code

1 if
1 if
1 if
1 if

NEGB
NEGB
NEGB
NEGB
NEGB
NEGB
NEGB
NEGB
NEGB
NEGB
NEGB
NEGB

the result is negative, 0 otherwise
there is a borrow, 0 otherwise
the result is 0, 0 otherwise
there is an overflow, 0 otherwise
Before

AD
AD
AD
AD
AD
AD
AD
AD
AD
AD
AD
AD

AO
OOOOOOOOh
OOOOOOOOh
55555555h
55555555h
7FFFFFFFh
7FFFFFFFh
80000000h
80000000h
80000001h
80000001h
FFFFFFFFh
FFFFFFFFh

After
C

0
1
0
1
0
1
0
1
0
1
0
1

NCZV
0010
1100
1100
1100
1100
1100
1101
0100
0100
0100
0100
0110

AO
OOOOOOOOh
FFFFFFFFh
AAAAAAABh
AAAAAAAAh
80000001h
80000000h
80000000h
7FFFFFFFh
7FFFFFFFh
7FFFFFFEh
00000001h
OOOOOOOOh

12-169

NOP

No Operation

Syntax

NOP

Execution

No operation

Instruction
Words

15 14

Description

o
0

The program counter is incremented to point to the next instruction. The
processor status is otherwise unaffected.
You an use the NOP instruction to pad loops and perform other timing
functions.

Machine
States
Status Bits

1,4

N
C
Z
V

Example

Before
NOP

12-170

Unaffected
Unaffected
Unaffected
Unaffected

After

00020000h

00020010h

NOT

Complement Register

Syntax

NOT

Execution

NOT Rd

Instruction
Words
Description
Machine
States
Status Bits

Rd
-+

15 14 13 12 11

5
1

0
Rd

NOT stores the 1s complement of the destination register's contents back
into the destination register.
1,4

N
C
Z
V

Unaffected
Unaffected
1 if the result is 0, 0 otherwise
Unaffected

Examples

Before
NOT
NOT
NOT
NOT

AO
AO
AO
AO

After

NCZV

OOOOOOOOh
55555555h
FFFFFFFFh
80000000h

xxOx
xxOx
xx1x
xxOx

FFFFFFFFh

AAAAAAAAh

OOOOOOOOh
7FFFFFFFh

12-171

OR Registers

Syntax

Execution

Rs DR Rd -

Instruction
Words

15 14

RS,Rd

10
Description

This instruction bitwise-DRs the contents of the source register with-the
contents of the destination register; the result is stored in the destination
register.
Rs and Rd must be in the same register file.

Machine
States

1,4

Status Bits

N
C
Z
V

Examples

Code
OR
OR
OR
OR

12-172

Unaffected
Unaffected
1 if the result is 0, 0 otherwise
Unaffected

AD,AI
AD,AI
AD,AI
AD,AI

Before

After

NCZV

FFFFFFFFh
OOOOOOOOh
55555555h
OOOOOOOOh

OOOOOOOOh
FFFFFFFFh
AAAAAAAAh
OOOOOOOOh

FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
OOOOOOOOh

xxOx
xxOx
xxOx
xx1x

OR Immediate (32 Bits)

Syntax

ORI IL, Rd

Execution

IL OR Rd -+ Rd

Instruction
Words

15 14 13
0

12
0

ORI

IR I

2
Rd

16 LSBs of IL
16 MSBs of IL

Description

Machine
States

This instruction bitwise-ORs a 32-bit immediate value with the contents of
the destination register and stores the result in the destination register. (lL
in the syntax represents the 32-bit value.)

3,12

Status Bits

N
C
Z
V

Examples

Code

Before

After

OR!
OR!
OR!
OR!

AO
OOOOOOOOh
FFFFFFFFh
55555555h
OOOOOOOOh

AO
FFFFFFFFh
FFFFFFFFh
FFFFFFFFh
OOOOOOOOh

Unaffected
Unaffected
1 if the result is 0, 0 otherwise
Unaffected

OFFFFFFFFh,AO
OOOOOOOOh,AO
OAAAAAAAAh,AO
OOOOOOOOh,AO

NCZV
xxOx
xxOx
xxOx
xx1x

12-173

Pixel Block Transfer - Binary to Linear

PIXBLT
Syntax

PIXBlT

Execution

binary pixel array

Instruction
Words

15 14
/0

Description

B. l

linear pixel array (with processing)

o
o

0 /

This PIXBLT instruction expands. transfers, and processes a binary source
pixel array with a destination pixel array.
This instruction operates on two-dimensional arrays of pixels using linear
starting addresses for both the source and the destination. The source pixel
array is treated as a one bit per pixel array. As the PixBlt proceeds, the
source pixels are expanded and then combined with the corresponding
destination pixels based on the selected graphics operations.
Note that the parameters are entered exactly as shown in the syntax; that
is, the instruction is entered as PIXBLT B, L. The first parameter, B, indicates that the starting address of the source array is a linear address but the
source array is a binary array. The second parameter, l, indicates that the
starting address of the destination array is a linear address. The foilowing
set of implied operands govern the operation of the instruction and define
the source and destination arrays.

Implied
Operands
Register
BOt

Name

B File Registers
Format
Description

SADDR

Linear

Source pixel array starting address

B1
B2t

SPTCH

Linear

Source pixel array pitch

DADDR

Linear

Destination pixel array starting address

DPTCH

Linear

Destination pixel array pitch

DYDX

Pixel array dimensions (rows:columns)

COLORO

Pixel

Background expansion color

COLOR1

Pixel

Foreground expansion color

B1O-B14t

Reserved registers
1/0 Registers
Address
Name
Description and Elements (Bits)
PP- Pixel processing operations (22 options)
COOOOOOBOh CONTROL
T - Transparency operation
Pixel size (1,2,4,8,16)
COOO0150h
PSIZE
COOOO160h
PMASK
Plane mask - pixel format
t These registers are changed by PIXBLT execution.

Due to the pipelining of memory writes, the last I/O register that you write
to may not. in some cases, contain the desired value when you execute the
PIXBLT instruction. To ensure that this register contains the correct value
for execution, you may want to follow the write to that location with an
instruction that reads the same location (such as a MOVE SAddress,Rd instruction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.
12-174

Pixel Block Transfer - Binary to Linear

PIXBLT

Source Array The source pixel array for the expand operation is defined by the contents
of the SADDR, SPTCH, and DYDX registers:

Source
Expansion

Destination
Array

•

At the outset of the instruction, SADDR contains the linear address
of the pixel with the lowest address in the array. During instruction
execution, SADDR points to the address of the next set of 32 pixels
to be read from the source array. When the transfer is complete,
SADDR points to the linear address of the first pixel on the next row
of pixels that would have been moved if the block transfer continued.

•

SPTCH contains the linear difference in the starting addresses of adjacent rows of the source array. For this PIXBLT instruction, SPTCH
can be any value.

•

DYDX specifies the dimensions, in pixels, of both the source and
destination arrays. The DY portion of DYDX contains the number of
rows in the array; the DX portion contains the number of pixels per
row.

The actual values of the source pixels are determined by the interaction of
the source array with the contents of the COLOR1 and COLORO registers.
In the expansion operation, a 1 bit in the source array selects a pixel from
the COLOR1 register for operation on the destination array. A 0 bit in the
source array selects a COLORO pixel for this purpose. The pixels selected
from the COLOR1 and COLORO registers are those that align directly with
their intended position in the destination array word.
The location of the destination pixel block is defined by the contents of the
DADDR, DPTCH, and DYDX registers:
•

At the outset of the instruction, DADDR contains the linear address
of the pixel with the lowest address in the array. During instruction
execution, DADDR points to the next pixel (or word of pixels) to be
modified in the destination array. When the block transfer is complete, DADDR points to the linear address of the first pixel on the
next row of pixels that would have been moved if the block transfer
continued.

•

DPTCH contains the linear difference in the starting addresses of adjacent rows of the destination array (typically this is the screen ~itch).
DPTCH must be a mUltiple of 16.

•

Corner Adjust No corner adjust is performed for this instruction
PBH and PBV are' ignored. The pixel transfer simply proceeds in the order
of increasing linear addresses.
Window
Checking

You cannot use window checking with this PixBlt instruction. The contents of the WSTART and WEN D registers are ignored.
12-175

Pixel Block Transfer - Binary to Linear

PIXBLT

Pixel
Processing

You can select a pixel processing option for this instruction by setting the
PPOP bits in the CONTROL register. The pixel processing operation is
applied to expanded pixels as they are processed with the destination array;
that is, the data is first expanded and then processed. There are 16 Boolean
and 6 arithmetic operations; the default case at reset is the replace (S -+
D) operation. The
6 arithmetic operations
do ,.not
with
L: .... _ _ _ _ _ =___ 1
=_L _____
. ... : __operate
___
__
... : ___ pixel
...,.., sizes
n:. __ 1
_Z,

______

UI Ullt: VI

...

r"" ______ .• _

LVVU

Ull~

IJtH

fJ1At:I.

rUI

((Iun:;: IIIIUlilldllUII,

~t:t::

":)t:(';LlUIl

1.1, rlxt;:1

Processing, on page 7 -15.

Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
pixels after it expands and processes the source data. At reset. the default
case for transparency is off.
Plane Mask

The plane mask is enabled for this instruction.

Interrupts

This instruction can be interrupted at a word or row boundary of the destination array. When the PixBlt is interrupted, the TMS3401 0 sets the PBX
bit in the status register and then pushes the status register on the stack.
At this time, DPTCH, SPTCH, and B1 o-B14 contain intermediate values.
DADDR points to the linear address of the next word of pixels to be modified after the interrupt is processed. SADDR points to the address of the
next 32 pixels to be read from the source array after the interrupt is processed.
The PIXBLT instruction uses several I/O and B-file registers as implied operands. If an interrupt service routine modifies a register that the PIXBLT
uses as an implied operand, you must restore that register to the value it had
when the routine began, before returning from the routine. (You can use
the MMFM and MMTM instructions to save and restore the B-file registers.) In order to maintain compatibility with future TMS340 devices, use
only the RETI instruction to return from an interrupt routine.

Shift Register
Transfers
If the SRT bit in the DPYCTL I/O register is set, each memory read or write
initiated by the PixBlt generates a shift register transfer read or write cycle
at the selected address. This operation can be used for bulk memory clears
or transfers. (Not all VRAMs support this capability.)
Machine
States

See PIXBLT Expand Instructions Timing, Section 13.5.

Status Bits

N
C
Z
V

Examples

Before executing the PIXBLT instruction, load the implied operand registers
with appropriate values. These PIXBLT examples use the following implied
operand setup:

Undefined
Undefined
Undefined
Undefined

00002030h
00000100h
00033000h

I/O Registers:
PSIZE
= 0010h

Pixel Block Transfer - Binary to Linear

DPTCH (B3)
DYDX (B7)
COLORO (B8)
COLOR1 (B9)

PIXBLT

00001000h
00020010h
FEDCFEDCh
BA98BA98h

Additional implied operand values are listed with each example.
For this example, assume that memory contains the following data before
instruction execution.

Example 1

linear
Address
02000h
02080h
02100h
02180h

xxxxh,
xxxxh,
xxxxh,
xxxxh,

33000h
33080h

FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh
FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh

34000h
34080h

FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh
FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh

Data
xxxxh,
xxxxh,
xxxxh,
xxxxh,

xxxxh,
xxxxh,
xxxxh,
xxxxh,

1 234h,
xxxxh,
5678h,
xxxxh,

xxxxh,
xxxxh,
xxxxh,
xxxxh,

xxxxh
xxxxh
xxxxh
xxxxh

This example uses the replace (S -+ 0) pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = OOOOh (T=O,
PP=OOOOO).
After instruction execution, memory contains the following values:
linear
Data
Address
33000h FEDCh, FEDCh, BA98h, FEDCh, BA98h, BA98h, FEDCh, FEDCh
33080h FEDCh, BA98h, FEDCh, FEDCh, BA98h, FEDCh, FEDCh, FEDCh
34000h
34080h

Example 2

FEDCh, FEDCh, FEDCh, BA98h, BA98h, BA98h, BA98h, FEDCh
FEDCh,BA98h, BA98h,FEDCh,BA98h,FEDCh,BA98h,FEDCh

This example uses the (0 - S) -+ 0 pixel processing operation. Before instruction execution, PMASK = OOOOh and CONTROL = 4800h (T=O,
PP=10010).
After instruction execution, memory contains the following values:
linear
Data
Address
33000h 0123h, 0123h, 4567h, 0123h, 4567h, 4567h, 0123h, 0123h
33080h 0123h, 4567h, 0123h, 0123h, 4567h, 0123h, 0123h, 0123h
34000h
34080h

0123h, 0123h, 0123h, 4567h, 4567h, 4567h, 4567h, 0123h
0123h, 4567h, 4567h, 0123h, 4567h, 0123h, 4567h, 0123h

12-177

Pixel Block Transfer - Binary to Linear

PIXBLT

Example 3

This example uses transparency with COLORO = OOOOOOOOh. Before instruction execution, PMASK = OOOOh and CONTROL = 0020h (T=1,
W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:

linear

Data

Address
33000h FFFFh, FFFFh, BA98h, FFFFh, BA98h, BA98h, FFFFh, FFFFh
33080h FFFFh, BA98h, FFFFh, FFFFh, BA98h, FFFFh, FFFFh, FFFFh
34000h
34080h

Example 4

FFFFh, FFFFh, FFFFh, BA98h, BA98h, BA98h, BA98h, FFFFh
FFFFh, BA98h, BA98h, FFFFh, BA98h, FFFFh, BA98h, FFFFh

This example uses plane masking
the four LSBs are masked. Before instruction execution, PMASK = OOOFh
and CONTROL = OOOOh (T=O, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:

linear

Data

Address
33000h FEDFh, FEDFh, BA9Fh,FEDFh, BA9Fh,BA9Fh,FEDFh, FEDFh
33080h FEDFh, BA9Fh,FEDFh, FEDFh, BA9Fh,FEDFh, FEDFh, FEDFh
34000h
34080h

12-178

FEDFh, FEDFh, FEDFh, BA9Fh, BA9Fh,BA9Fh, BA9Fh,FEDFh
FEDFh, BA9Fh, BA9Fh,FEDFh, BA9Fh,FEDFh, BA9Fh,FEDFh

PIXBLT

Pixel Block Transfer - Binary to XY

Syntax

PIXBLT

Execution

binary pixel array ..... XY pixel array (with processing)

Instruction
Words
Description

B, XV

15 14

0
0

This PIXBLT instruction expands, transfers, and processes a binary source
pixel array with a destination pixel array.
This instruction operates on two-dimensional arrays of pixels using a linear
starting address for the source and an XY address for the destination. The
source pixel array is treated as a one bit per pixel array. As the PixBlt proceeds, the source pixels are expanded and then combined with the corresponding destination pixels based on the selected graphics operations.
Note that the parameters are entered exactly as shown in the syntax; that
is, the instruction is entered as PIXBLT B,XY. The first parameter, B, indicates that the starting address of the source array is a linear address but the
source array is a binary array. The second parameter, XV, indicates that the
starting address of the destination array is an XY address.
The following set of implied operands govern the operation of the instruction and define the source and destination arrays.

Implied
Operands

B File Registers
Format
Description
Source pixel array starting address
Linear
B1
Linear
Source pixel array pitch
B2t+
XY
Destination pixel array starting address
Destination pixel array pitch
B3
Linear
B4
Linear
Screen origin (O,O)
B5
XY
Window starting corner
XY
Window ending corner
B6
B7+
XY
Pixel array dimensions (rows:columns)
B8
Pixel
Background expansion color
Pixel
Foreground expansion color
B9
B10-B14t
Reserved registers
I/O Registers
Address
Name
Description and Elements (Bits)
COOOOOOBOh CONTROL
pp- Pixel processing operations (22 options)
W - Window clipping or pick operation
T - Transparency operation
COOOO130h
CONVSP
XY-to-linear conversion (source pitch)
Used for source preclipping.
COOOO140h
XY-to-linear conversion (destination pitch)
CONVDP
COOOO150h
PSIZE
Pixel size (1.2,4,6,8,16)
COOOO160h
PMASK
Plane mask - pixel format
t These registers are changed by PIXBLT execution.
+ Used for common rectangle function with window hit operation (W=1).
Register
BOt

Name
SADDR
SPTCH
DADDR
DPTCH
OFFSET
WSTART
WEND
DYDX
COLORO
COLOR1

12-179

Pixel Block Transfer - Binary to XY

PIXBLT

Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
PIXBLT instruction. To ensure that this register contains the correct value
for execution, you may want to follow the write to that location with an
instruction that reads the same location (such as a MOVE SAddress,Rd instruction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.

Source Array The source pixel array for the expand operation is defined by the contents
of the SADDR, SPTCH, DYDX, and (possibly) CONVSP registers:

Source
Expansion

Destination
Array

12-180

•

At the outset of the instruction, SADDR contains the linear address
of the pixel with the lowest address in the array. During instruction
execution, SADDR points to the address of the next set of 32 pixels
to be read from the source array. When the block transfer is complete,
SADDR points to the linear address of the first pixel on the next row
of pixels that would have been moved if the block transfer continued.

•

SPTCH contains the linear difference in the starting addresses of adjacent rows of the source array. SPTCH can be any value for this
PIXBLT. For window clipping, SPTCH must be a power of two, and
CONVSP must be set to correspond to the SPTCH value.

•

CONVSP is calculated by taking the LMO of SPTCH; this value is
used for the XY calculations involved in XY addressing and window
clipping.

•

DYDX specifies the dimensions, in pixels, of both the source and
destination arrays in pixels. The DY portion of DYDX contains the
number of rows in the array; the the OX portion contains the number
of pixels per row.

The actual values of the source pixels are determined by the interaction of
the source array with contents of the COLOR1 and COLORa registers. In
the expansion operation, a 1 bit in the source array selects a pixel from the
COLOR1 register for operation on the destination array. A 0 bit in the
source array selects a COLORa pixel for this purpose. The pixels selected
from the COLOR1 and COLORa registers are those that align directly with
their intended position in the destination array word.
The location of the destination pixel block is defined by the contents of the
DADDR, DPTCH, CONVDP, OFFSET, and DYDX registers:
•

At the outset of the instruction, DADDR contains the XV address of
the pixel with the lowest address in the array; it is used with OFFSET
and CONVDP to calculate the linear address of the array. During instruction execution, DADDR points to the linear address of next
pixel (or word of pixels) to be modified in the destination array. When
the block transfer is complete, DADDR points to the linear address
of the first pixel on the next row of pixels that would have been
moved if the block transfer continued.

•

DPTCH contains the linear difference in the starting addresses of adjacent rows of the destination array (typically this is the screen pitch).
DPTCH must be a power of two (greater than or equal to 16) and
CONVDP must be set to correspond to the DPTCH value.

Pixel Block Transfer - Binary to XY

PIXBLT

•

CONVDP is determined by taking the LMO of the DPTCH register;
this value is used for the XY calculations involved in XY addressing
and window clipping.

•

Corner Adjust No corner adjust is performed for this instruction. The transfer executes in
the order of increasing linear addresses. PBH and PBV are ignored.
Window
Checking

You can use window checking with this instruction by setting the W bits
in the CONTROL register to the desired value. If you select window
checking mode 1,2, or 3, the WSTART and WEND registers define the XY
starting and ending corners of a rectangular window.

No windowing. The entire pixel array is drawn and the WVP and V bits
are unaffected.

1 Window hit. No pixels are drawn. The V bit is set to 0 if any portion of
the destination array lies within the window. Otherwise, the V bit is set
to 1.
If the V bit is set to 0, the DADDR and DYDX registers are modified to
correspond to the common rectangle formed by the intersection of the
destination array with the rectangular window. DADDR is set to the XY
address of the pixel in the starting corner of the common rectangle.
DYDX is set to the X and Y dimensions of the common rectangle.
If the V bit is set to 1, the array lies entirely outside the window, and the
values of DADDR and DYDX are indeterminate.
2 Window miss. If the array lies entirely within the active window, it is
drawn and the V bit is set to O. Otherwise, no pixels are drawn, the V
and WVP bits are set to 1, and the instruction is aborted.
3 Window clip. The source and destination arrays are preclipped to the
window dimensions. Only those pixels that lie within the common rectangle (corresponding to the intersection of the specified array and the
window) are drawn. If any preclipping is required, the V bit is set to 1.

Pixel
Processing

You can select a pixel processing option for this instruction by setting the
PPOP bits in the CONTROL register. The pixel processing operation is
applied to expanded pixels as they are processed with the destination array;
that is, the data is first expanded and then processed. There are 16 Boolean
and 6 arithmetic operations; the default case at reset is the S ..... D operation.
The 6 arithmetic operations do not operate with pixel sizes of one or two
bits per pixel. For more information, see Section 7.7, Pixel Processing, on
page 7-15.

12-181

Pixel Block Transfer - Binary to XY

PIXBLT

Plane Mask

The plane mask is enabled for this instruction.

Interrupts

This instruction can be interrupted at a word or row boundary of the destination array. When the PixBlt is interrupted, the TMS3401 0 sets the PBX
bit in the status register and then pushes the status register on the stack.
At this time, DPTCH, SPTCH, and B1 o-B14 contain intermediate values.
DADDR points to the linear address of the next word of pixels to be modified after the interrupt is processed. SADDR points to the address of the
next 32 pixels to be read from the source array after the interrupt is processed.
The PIXBLT instruction uses several I/O and B-file registers as implied operands. If an interrupt service routine modifies a register that the PIXB LT
uses as an implied operand, you must restore that register to the value it had
when the routine began, before returning from the routine. (You can use
the MMFM and MMTM instructions to save and restore the B-file registers.) In order to maintain compatibility with future TMS340 devices, use
only the RETI instruction to return from an interrupt routine.

Shift Register
Transfers
If the SRT bit in the DPYCTL I/O register is set. each memory read or write
initiated by the PixBlt generates a shift register transfer read or write cycle
at the selected address. This operation can be used for bulk memory clears
or transfers. (Not all VRAMs support this capability.)
Machine
States
Status Bits

12-182

See PIXBLT Expand Instructions Timing, Section 13.5.
N
C
Z
V

Undefined
Undefined
Undefined
1 if a window violation occurs, 0 otherwise; undefined if window
checking is not enabled (W=OO)

Pixel Block Transfer - Binary to XY
Examples

PIXBLT

Before executing a PIXBLT instruction, load the implied operand registers
with appropriate values. These PIXBLT examples use the following implied
operand setup.
Register File B:
SADDR (BO)
= 00002010h
SPTCH (B1)
= 00000010h
DADDR (B2)
= 00300022h
DPTCH (B3)
= 00001000h
OFFSET (B4)
= 00010000h
WSTART (B5) = 00000026h
WEND (B6)
= 00400050h
DYDX (B7)
= 00040010h
COLORO (BS) = OOOOOOOOh
COLOR1 (B9) = 7C7C7C7Ch

I/O Registers:
PSIZE
= OOOSh
CONVSP = 001 Bh
CONVDP = 0013h

Additional implied operand values are listed with each example.
For this example, assume that memory contains the following data before
instruction execution.
Linear
Data
Address
2000h
xxxxh, 0123h, 4567h, S9ABh, CDEFh, xxxxh, xxxxh, xxxxh

40000hto
43200h FFFFh
Example 1

This example uses the replace (5 -+ D) pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = OOOOh (T=O,
W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear
Data
Address
40100h FFFFh, 7C7Ch, OOOOh, 7COOh, OOOOh, 007Ch, OOOOh, OOOOh
401 SOh OOOOh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh

41100h
411S0h

FFFFh, 7C7Ch,007Ch, 7COOh, 007Ch, 007Ch, 007Ch, OOOOh
007Ch, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh

42100h
421 SOh

FFFFh, 7C7Ch, 7COOh, 7COOh, 7COOh, 007Ch, 7COOh, OOOOh
7COOh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh

43100h
431 SOh

FFFFh, 7C7Ch, 7C7Ch, 7COOh, 7C7Ch,007Ch, 7C7Ch,OOOOh
7C7Ch, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh, FFFFh

12-183

Pixel Block Transfer - Binary to XY

PIXBLT
XV Addressing

X Address
222222222222222233333
0123456789ABCDEF01234

Y
A

~FFFF7C7C0000007C00007COOOOOOOOOOOOOOFFFFFF

d
d

r 31 FF FF 7C 7C 7C 00 00 7C 7C 00 7C 00 7C 00 00 00 7C 00 FF FF FF
e
s 32 FF FF 7C 7C 00 7C 00 7C 00 7C 7C 00 00 7C 00 00 00 7C FF FF FF
s
33 FF FF 7C 7C 7C 7C 00 7C 7C 7C 7C 00 7C 7C 00 00 7C 7C FF FF FF
Example 2

This example uses the XOR pixel processing operation. Before instruction
execution, PMASK = OOOOh and CONTROL = 2800h (T=O, W=OO,
PP=01 01 0).
After instruction execution, memory contains the following values:
X Address
2 2 2 2 2 222 2 2 2 222 2 233 333
0123456789ABCDEF01234

Y
A
~

FF FF 83 83 FF FF FF 83 FF FF 83 FF FF FF FF FF FF FF FF FF FF

r 31 FF FF 83 83 83 FF FF 83 83 FF 83 FF 83 FF FF FF 83 FF FF FF FF
e
s 32 FF FF 83 83 FF 83 FF 83 FF 83 83 FF FF 83 FF FF FF 83 FF FF FF
s
33 FF FF 83 83 83 83 FF 83 83 83 83 FF 83 83 FF FF 83 83 FF FF FF
Example 3

This example uses transparency. Before instruction execution, PMASK =
OOOOh and CONTROL = 0020h (T=1, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
X Address
222222222222222233333
0123456789ABCDEF01234

FF FF 7C 7C FF FF FF 7C FF FF 7C FF FF FF FF FF FF FF FF FF FF

r 31 FF FF 7C 7C 7C FF FF 7C 7C FF 7C FF 7C FF FF FF 7C FF FF FF FF
e
s 32 FF FF 7C 7C FF 7C FF 7C FF 7C 7C FF FF 7C FF FF FF 7C FF FF FF
s
33 FF FF 7C 7C 7C 7C FF 7C 7C 7C 7C FF 7C 7C FF FF 7C 7C FF FF FF

12-184

Pixel Block Transfer - Binary to XY

Example 4

PIXBLT

This example uses window operation 3 (clipped destination). Before instruction execution, PMASK = OOOOh and CONTROL = OOCOh (T=O,
W=11, PP=OOOOO).
After instruction execution, memory contains the following values:
Y

X Address
222222222222222233333
0123456789ABCDEF01234

A
d ~FFFFFFFFFFFF007C00007COOOOOOOOOOOOOOFFFFFF
d
r 31 FF FF FF FF FF FF 00 7C 7C 00 7C 00 7C 00 00 00 7C 00 FF FF FF

e
s 32 FF FF FF FF FF FF 00 7C 00 7C 7C 00 00 7C 00 00 00 7C FF FF FF
s
33 FF FF FF FF FF FF 00 7C 7C 7C 7C 00 7C 7C 00 00 7C 7C FF FF FF
Example 5

This example uses plane masking; the four LSBs of each pixel are masked.
Before instruction execution, PMASK = OFOFh and CONTROL = 0020h
(T=1, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Y

X Address
222222222222222233333
0123456789ABCDEF01234

A
d 30 FF FF 7F 7F FF FF FF 7F FF FF 7F FF FF FF FF FF FF FF FF FF FF
d
r 31 FF FF 7F 7F 7F FF FF 7F 7F FF 7F FF 7F FF FF FF 7F FF FF FF FF

e
s 32 FF FF 7F 7F FF 7F FF 7F FF 7F 7F FF FF 7F FF FF FF 7F FF FF FF
s
33 FF FF 7F 7F 7F 7F FF 7F 7F 7F 7F FF 7F 7F FF FF 7F 7F FF FF FF

12-185

PIXBLT

Example 6

Pixel Block Transfer - Binary to XY

This example shows how to use the PIXBLT B,XY instruction's window
preclipping capabilitied when the source pitch is not a power of 2.

*----------------------------------------------------------------------* Assume that the registers have been loaded as follows:
*
BO
linear start address of source bitmap
* Bl SPTCH (no restrictions)
* B2 start ~ coord. ytop in 16 MSBs, start x coord.
*
xleft ~n 16 LSBs
B3
DPTCH (mu~L L~ ~UW~L of 2)
* B4 OFFSET
* B5 WSTART
* B6 WEND
* B7 DY::DX (array height in 16 MSBs, array width in 16 LSBs)
* B8
COLORO
*
B9
COLOR1
* FS1)= 16 (assume multiplier for MPYS below is less than 16 bits)
* CONVSP will not be used.
*
Implied operands in other I/O registers (incl. CONVDP) are valid.
*
Window option = 3
*----------------------------------------------------------------------_color_expand:
B2,B10
MOVY
;copy ytop
SUBXY
B5,B10
;window y overlap = ytop - ystart
JRYNN
INWINDOW
;jump if ytop below top of window
* Need to clip destination array to top edge of clipping window
MOVY
B5,B2
;clip ytop to top of w~ndow
;shift y overlap to 16 LSBs
SRA
16,B1O
MOVE
B1,B11
;copy SPTCH
MPYS
B10,B11
;(y overlap) * SPTCH
B11,BO
;clip SADDR to top of window
SUB
SLL
16,B10
;shift y overlap to 16 MSBs
ADDXY
B10,B7
;clip DY to top of window
;done if DY<=O (completely
JRLS
DONE
;above window)
* PIXBLT instruction will do any additional clipping required
INWINDOW:
;color expand bitmap to screen
PIXBLT
B,XY
* Restore registers and return
DONE:
RETS
o
;done
.end

12-186

Pixel Block Transfer - Linear to Linear
L, L

Syntax

PIXBLT

Execution

linear pixel array

Instruction
Words
Description

15 14 13

PIXBLT

linear pixel array (with processing)

12 11
0

0
0

The PIXBLT instruction transfers and processes a source pixel array with a
destination pixel array.
This instruction operates on two-dimensional arrays of pixels using linear
starting addresses for both the source and the destination. As the PixBlt
proceeds, the source pixels are combined with the corresponding destination pixels based on the selected graphics operations.
Note that the parameters are entered exactly as shown in the syntax; that
is, the instruction is entered as PIXBLT L,L. The first parameter, L, indicates that the starting address of the source array is a linear address; the
second parameter, L, indicates that the starting address of the destination
array is also a linear address.
The following set of implied operands govern the operation of the instruction and define the source and destination arrays.

Implied
Operands

B File Registers
Format
Description
Linear
Source pixel array starting address
Linear
Source pixel array pitch
Linear
Destination pixel array starting address
Linear
Destination pixel array pitch
XY
Pixel array dimensions
(rows:columns)
B1o-B14t
Reserved registers
I/O Registers
Address
Description and Elements (Bits)
Name
COOOOOOBOh CONTROL
PP- Pixel processing operations (22 options)
T - Transparency operation
PBH- PixBlt horizontal direction
PBV- PixBlt vertical direction
COOOO150h
Pixel size (1,2,4,8,16)
PSIZE
COOOO160h
PMASK
Plane mask - pixel format
t These registers are changed by PIXBlT execution.
t You must adjust SADDR and DADDR to correspond to the corner selected by the
values of PBH and PBV. See Corner Adjust below for additional information.
Register
BOtt
B1t
B2tt
B3
B7

Name
SADDR
SPTCH
DADDR
DPTCH
DYDX

Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
PIXBLT instruction. To ensure that this register contains the COrrect value
for execution, you may want to follow the write to that location with an
instruction that reads the same location (such as a MOVE SAddress,Rd instruction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.

12-187

PIXBLT

Pixel Block Transfer - Linear to Linear

Source Array The source pixel array for the processing operation is defined by the contents of the SADDR, SPTCH, and DYDX registers:

Destination
Array

•

At the outset of the instruction, SADDR contains the linear address
of the pixel at the appropriate starting corner of the array as determined by the PBH and PBV bits in the CONTROL I/O register. (See
Corner Adjust below.)
During instruction execution, SADDR
points to the next pixel (or \A/ord of pixels) to be read from the gOlJrc~
array. When the block transfer is complete, SADDR points to the
starting address of the next set of 32 pixels that would have been
moved had the block transfer continued.

•

SPTCH contains the linear difference in the starting addresses of adjacent rows of the source array. SPTCH must be a multiple of 16.

•

The location of the destination pixel array is defined by the contents of the
DADDR, DPTCH, and DYDX registers:
•

At the outset of the instruction, DADDR contains the linear address
of the pixel at the appropriate starting corner of the array as determined by the PBH and PBV bits in the CONTROL I/O register. (See
Corner Adjust below.)
During instruction execution, DADDR
points to the next pixel (or word of pixels) to be modified in the destination array. When the block transfer is complete, DADDR points
to the linear address of the first pixel on the next row of pixels that
would have been moved had the block transfer continued.

•

DPTCH contains the linear difference in the starting addresses of adjacent rows of the destination array. DPTCH must be a multiple of
16.

•

DYDX specifies the dimensions, in pixels, of both the source and
destination arrays in pixels. The DY portion of DYDX contains the
number of rows in the array, while the OX portion contains the number of columns.

Corner Adjust The PBH and PBV bits in the CONTROL I/O register govern the direction
of the PixBIt. If the source and destination arrays overlap, then PBH and
PBV should be set to prevent any portion of the source array from being
overwritten before it is moved.
Note that this PIXBLT's corner adjustment is unique. The PBH and PBV
bits control the direction of the PIXBLT; however, the adjustment of
SADDR and DADDR to point to the appropriate starting corner is not automatic. You must explicitly set these two registers to point to the selected
starting corners of the source and destination arrays, respectively, as indicated by PBH and PBV. This facility allows you to use corner adjust for
screen definitions that do not lend themselves to XY addressing (those not
binary powers of two). In effect, you supply your own corner adjust operation in software and the PixBlt instruction provides directional control.

12-188

Pixel Block Transfer - Linear to Linear

PIXBLT

•

For PBH
0 and PBV
0, set SADDR and DADDR as they are
normally set for linear PixBlts. Set both registers to correspond to the
linear address of the first pixel on the first line of the array (that is,
the pixel with the lowest address).

•

For PBH = 0 and PBV = 1, set SADDR and DADDR to correspond
to the linear address of the first pixel on the last line of the array.
In other words,
SADDR = (linear address of 1st source pixel) + [(DY-1) x SPTCH)]

and
DADDR = (linear address of 1st destination pixel) + [(DY-1) x DPTCH)]

For PBH
1 and PBV
0, set SADDR and DADDR to correspond
to the linear address of the pixel following the last pixel on the first
line of the array. In other words,

•

SADDR = (linear address of 1st source pixel) + (DX x PSIZE)
and
DADDR = (linear address of 1st destination pixel) + (DX x PSIZE)
For PBH = 1 and PBV = 1, set SADDR and DADDR to correspond
to the linear address of the pixel following the last pixel on the last
line of the array. In other words,

•

SADDR = (linear address of 1 st source pixel) + [(DY -1) x SPTCH)]
+ (DX x PSIZE)
and
DADDR = (linear address of 1st destination pixel) + [(DY-1) x
DPTCH)] + (DX x PSIZE)

Window
Checking
Pixel
Processing

Window operations are not enabled for this instruction. The contents of the
WST ART and WEN D registers are ignored.
You can select a pixel processing option for this instruction by setting the
PPOP bits in the CONTROL register. The pixel processing option is applied
to pixels as they are processed with the destination array. Note that the
data is read through the plane mask and then processed. There are 16
Boolean and 6 arithmetic operations; the default case at reset is the replace
(S -> D) operation. The 6 arithmetic operations do not operate with pixel
sizes of 1 or 2 bits per pixel. For more information, see Section 7.7, Pixel
Processing, on page 7-15.

Transparency You can enable transparency for this instruction by setting the T bit in the
CONTROL I/O register to 1. The TMS34010 checks for 0 (transparent)
pixels after it expands and processes the source data. At reset, the default
case for transparency is off.
Plane Mask

The plane mask is enabled for this instruction.

12-189

PIXBLT

Pixel Block Transfer - Linear to Linear

Interrupts

See Section 13.4, PIXBLT Instructions Timing.

Status Bits

N
C
Z
V

Examples

Before executing a PIXBLT instruction, load the implied operand registers
with appropriate values. These PIXBLT examples use the following implied
operand setup.

Undefined
Undefined
Undefined
Undefined

Register File B:
SADDR (BO)
= 00002004h
= 00000080h
SPTCH (B1)
DADDR (B2)
= 00002228h
DPTCH (B3)
= 00000080h
= OOOOOOOOh
OFFSET (B4)
DYDX (B7)
= 0002000Dh

I/O Registers:
PSIZE
= 0004h

Additional implied operand values are listed with each example.
For these examples, assume that memory contains the following data before
instruction execution.
Linear
Address
02000h
02080h
02100h
02180h
02200h
02280h
02300h

12-190

Data
OOOxh,
OOOxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,

1111 h,
1111 h,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,

2222h,
2222h,
xxxxh,
xxxxh,
FFxxh,
FFxxh,
xxxxh,

xx33h,
xx33h,
xxxxh,
xxxxh,
FFFFh,
FFFFh,
xxxxh,

xxxxh,
xxxxh,
xxxxh,
xxxxh,
FFFFh,
FFFFh,
xxxxh,

xxxxh,
xxxxh,
xxxxh,
xxxxh,
xFFFh,
xFFFh,
xxxxh,

xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,

xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh

Pixel Block Transfer - Linear to Linear

Example 1

PIXBLT

This example uses the replace (S -+ 0) pixel processing operation. Before
instruction execution, PMASK = OOOOh and CONTROL = OOOOh (T=O,
W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear
Address
02000h
02080h
02100h
02180h
02200h
02280h
02300h

Example 2

Data
OOOxh,
OOOxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,

1111 h,
1111 h,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,

2222h,
2222h,
xxxxh,
xxxxh,
OOxxh,
OOxxh,
xxxxh,

xx33h,
xx33h,
xxxxh,
xxxxh,
1110h,
1110h,
xxxxh,

xxxxh,
xxxxh,
xxxxh,
xxxxh,
2221 h,
2221 h,
xxxxh,

xxxxh,
xxxxh,
xxxxh,
xxxxh,
x332h,
x332h,
xxxxh,

xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,

xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh

This example uses the (0 - S) -+ 0 pixel processing operation. Before instruction execution, PMASK = OOOOh and CONTROL = 4800h (T=O,
W=OO, PP=10010).
After instruction execution, memory contains the following values:
Linear
Address
02000h
02080h
02100h
02180h
02200h
02280h
02300h

Example 3

Data
OOOxh,
OOOxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,

1111 h,
1111 h,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,

2222h,
2222h,
xxxxh,
xxxxh,
FFxxh,
FFxxh,
xxxxh,

xx33h,
xx33h,
xxxxh,
xxxxh,
EEEFh,
EEEFh,
xxxxh,

xxxxh, xxxxh, xxxxh,
xxxxh, xxxxh, xxxxh,
xxxxh, xxxxh, xxxxh,
xxxxh, xxxxh, xxxxh,
DDDEh,xCCDh, xxxxh,
DDDEh,xCCDh, xxxxh,
xxxxh, xxxxh, xxxxh,

xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh

This example uses transparency. Before instruction execution, PMASK =
OOOOh and CONTROL = 0020h (T=1, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:
Linear
Address
02000h
02080h
02100h
02180h
02200h
02280h
02300h

Data
OOOxh,
OOOxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,

1111 h,
1111 h,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,

2222h, xx33h,
2222h, xx33h,
xxxxh, xxxxh,
xxxxh, xxxxh,
OFFxxh, 111 Fh,
OFFxxh, 111 Fh,
xxxxh, xxxxh,

xxxxh,
xxxxh,
xxxxh,
xxxxh,
2221 h,
2221 h,
xxxxh,

xxxxh,
xxxxh,
xxxxh,
xxxxh,
x332h,
x332h,
xxxxh,

xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,

xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh

12-191

Pixel Block Transfer - Linear to Linear

PIXBLT

Example 4

This example uses plane masking (the MSB of each pixel is masked). Before instruction execution, PMASK = 8888h and CONTROL = OOOOh
(T=O, W=OO, PP=OOOOO).
After instruction execution, memory contains the following values:

Linear
Address
02000h
02080h
02100h
02180h
02200h
02280h
02300h

12-192

Data
OOOxh,
OOOxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,

1111 h,
1111 h,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,

2222h,
2222h,
xxxxh,
xxxxh,
88xxh,
88xxh,
xxxxh,

xx33h,
xx33h,
xxxxh,
xxxxh,
9998h,
9998h,
xxxxh,

xxxxh, xxxxh,
xxxxh, xxxxh,
xxxxh, xxxxh,
xxxxh, xxxxh,
AAA9h,xBBAh,
AAA9h,xBBAh,
xxxxh, xxxxh,

xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,
xxxxh,

xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh

PIXBLT

Pixel Block Transfer - Linear to XY
Syntax

PIXBLT

Execution

linear pixel array .... XV pixel array (with processing)

Instruction
Words

15 14
10

Description

L. XV

The PIXBlT instruction transfers and processes a source pixel array with a
destination pixel array.
This instruction operates on two-dimensional arrays of pixels using a linear
starting address for the source array and an XV address for the destination
array. As the Pix Bit proceeds, the source pixels are combined with the
corresponding destination pixels based on the selected graphics operations.
Note that the parameters are entered exactly as shown in the syntax; that
is, the instruction is entered as PIXBLT L, XY. The first parameter, L, indicates that the starting address of the source array is a linear address; the
second parameter, XV, indicates that the starting address of the destination
array is an XV address.
The following set of implied operands govern the operation of the instruction and define the source and destination arrays.

Implied
Operands
Register
BOt
B1
B2t:l:

Name
SADDR
SPTCH
DADDR

B File Registers
Format
Description
Linear
Source pixel array starting address
Linear
XY

Source pixel array pitch
Destination pixel array starting address
Destination pixel array pitch
Screen origin (0,0)

DPTCH

B4
B5
B6
B7:1:

OFFSET
WSTART

Linear
Linear
XY

WEND

DYDX

B1O-B14t
Address

Name

COOOOOOBOh

CONTROL

COOO0130h

CONVSP

COOO0140h
COOO0150h

CONVDP
PSIZE

Window starting corner
Window ending corner
Pixel array dimensions (rows:columns)
Reserved registers

I/O Registers
Description and Elements (Bits)
PP- Pixel processing operations (22 options)
W - Window operations
T - Transparency operation
PBH- Pix Bit horizontal direction
PBV- PixBlt vertical direction
XY -to-linear conversion (source pitch)
Used for preclipping and corner adjust
XY-to-linear conversion (destination pitch)

Pixel size (1,2,4,8,16)
Plane mask - pixel format
COOO0160h
PMASK
t These registers are changed by PIXBLT execution.
t Used for common rectangle function with window pick.

Due to the pipelining of memory writes, the last I/O register that you write
to may not, in some cases, contain the desired value when you execute the
12-193

PIXBLT

Pixel Block Transfer - Linear to XY

PIXBLT instruction. To ensure that this register contains the correct value
for execution, you may want to follow the write to that location with an
instruction that reads the same location (such as a MOVE SAddress,Rd instruction). For more information, refer to Section 6.2, Latency of Writes to
I/O Registers.

Source Array The source pixel array for the processing operation is defined by the con+on+"
"'" ."u ...
..,.f +ho
".,V

Destination
Array

12-194

_C:lI.nn~
. . . _ _ I I,

C:PT(,I-I

15 14 13 12
000

4
R

2
Rd

1 s complement of IW

Description

SUBI subtracts a sign-extended, 16-bit immediate value from the contents
of the destination register, and stores the result in the destination register.
(The IW in the syntax represents a sign-extended, 16-bit immediate value.)
The assembler uses this form of the SUBI instruction if the immediate value
was previously defined and is in the range -32,768 to 32,767. You can
force the assembler to use the short form by by following the register operand with ,W:
SUBI

IW,Rd,W

The assembler truncates any upper bits and issues an appropriate warning
message. You can accomplish multiple-precision arithmetic by using SUBI
in conjunction with the SUBB instruction.

Machine
States

2,8

Status Bits

N
C
Z
V

Examples

Code

1
1
1
1

SUBI
SUBI
SUBI
SUBI
SUBI
SUBI
SUBI
SUB I
SUB I
SUBI

if
if
if
if

the result is negative, 0 otherwise
a borrow is generated, 0 otherwise
the result is 0, 0 otherwise
there is an overflow, 0 otherwise

32765,AO
32766,AO
32767,AO
32766,AO
32767,AO
-32766,AO
-32767,AO
-3276B,AO
-32767,AO
-3276B,AO

Before

After

NCZV

00007FFEh
00007FFEh
00007FFEh
80007FFEh
80007FFEh
FFFF8001h
FFFF8001h
FFFF8001h
FFFF8000h
7FFF8000h

00000001h
OOOOOOOOh
FFFFFFFFh
80000000h
7FFFFFFFh
FFFFFFFFh
OOOOOOOOh
00000001h
7FFFFFFFh
80000000h

0000
0010
1100
1000
0001
1100
0010
0000
0100
1101

12-249

Subtract Immediate - 32 Bits

SUBI

Syntax

SUBI IL. Rd [. lJ

Execution

Rd - IL

Instruction
Words

15 14
10
0

13
0

12
0

9
8
765
4
0
o 0 0 R
1s complement of 1 6 LS Bs of I L

2
Rd

1 s complement of 16 MSBs of IL

Description

SUBI subtracts a signed 32-bit immediate value from the contents of the
destination register, and stores the result in the destination register. (The
IL in the syntax represents a signed 32-bit immediate value.)
The assembler uses this version of the SUBI instruction if it cannot use the
SUBI IW.Rd opcode, or if you request the long opcode by following the
register operand with .l:
SUBI

IL,Rd,L

You can accomplish multiple-precision arithmetic by using SUBI in conjunction with the SUBB instruction.

Machine
"'..... _...... _~U"tI:f

.......

Status Bits

N
C
Z
V

Examples

Code

Before

After

SUBI 2147483647,AO
SUBI
32768,AO
SUBI
32769,AO
SUBI
32770,AO
32768,AO
SUBI
32769,AO
SUBI
SUBI -2147483648,AO
SUBI
-32769,AO
SUBI
-32770,AO
SUBI
-32771,AO
SUBI
-32770,AO
SUBI
-32771,AO

AO
7FFFFFFFh
00008001h
00008001h
00008001h
80008000h
80008000h
80000000h
FFFF7FFEh
FFFF7FFEh
FFFF7FFEh
7FFF7FFDh
7FFF7FFDh

AO
OOOOOOOOh
00000001h
OOOOOOOOh
FFFFFFFFh
80000000h
7FFFFFFFh
OOOOOOOOh
FFFFFFFFh
OOOOOOOOh
00000001h
7FFFFFFFh
80000000h

12-250

.;;),IL

1 if the result is negative, 0 otherwise
1 if there is a borrow, 0 otherwise
1 if the result is 0, 0 otherwise
1 if there is an overflow, 0 otherwise

NCZV
0010
0000
0010
1100
1000
0001
0010
1100
0010
0000
0100
1101

Subtract Constant

SUBK

Syntax

SUBK

Execution

Rd - K

Instruction
Words

15 14

Description

K,Rd
-+

Rd
12

11
0

10
1

SUBK subtracts the 5-bit constant from the contents of the destination register; the result is stored in the destination register. The K in the syntax
represents a constant that is treated as an unsigned number in the range
1-32. Note that K=O in the opcode corresponds to the value 32; the assembler converts the value 32 to O. The assembler issues an error if you try
to subtract 0 from a register.
You can accomplish multiple-precision arithmetic by using SUBK in conjunction with the SUBB instruction.

Machine
States

1,4

Status Bits

N
C
Z
V

Examples

Code

1
1
1
1

SUBK
SUBK
SUBK
SUBK

if
if
if
if

the result is negative, 0 otherwise
there is a borrow, 0 otherwise
the result is 0, 0 otherwise
there is an overflow, 0 otherwise

S,AO
9,AO
32,AO
l,AO

Before

After

AO
00000009h
00000009h
00000009h
80000000h

AO
NCVZ
00000004hOOOO
00000000h0010
FFFFFFE9h 1100
7FFFFFFFhOO01

12-251

SUBXV

Subtract Registers in XV Mode

Syntax

SUBXY Rs, Rd

Execution

RdX - RsX
RdY - RsY

Instruction
Words
Description

15 14

-+\
-+

RdX
RdY
12 11 10
000

4
R

2
nd

SUBXY subtracts the source X and Y values individually from the destination X and Y values; the result is stored in the destination register.
You can use this instruction for manipulating XY addresses; it is particularly
useful for incremental figure drawing. These addresses are stored as XY
pairs in the register file.
Rs and Rd must be in the same register file.

Machine
States

1,4

Status Bits

C
Z
V

Examples

1 if source
1 if source
1 if source
1 if source

12-252

X fjeld,
Y field,
Y field,
X field,

0
0
0
0

otherwise
otherwise
otherwise
otherwise

Before

Code
SUBXY
SUBXY
SUBXY
SUBXY
SUBXY
SUBXY
SUBXY
SUBXY
SUBXY

X field = destination
Y field> destinatioll
Y field = destination
X field> destination

Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO
Al,AO

After

NCZV

00090009h
00090009h
00090009h
00090009h
00090009h
00090009h
00090009h
00090009h
00090009h

00010001h
00090001h
00010009h
00090009h
00000010h
00090010h
00100000h
00100009h
00100010h

00080008h
00000008h
00080000h
OOOOOOOOh
0009FFF9h
0000FFF9h
FFF90009h
FFF90000h
FFF9FFF9h

0000
0010
1000
1010
0001
0011
0100
1100
0101

Software Interrupt

TRAP

Syntax

TRAP N

Execution

PC -+ -*5P
5T -+ -*5P
trap vector N

Instruction
Words

15 14

Description

10
0

9
0

TRAP executes a software interrupt. The N parameter is a trap number from
o to 31 that selects the trap to be executed. During a software interrupt,
•
•
•
•

The return address (the address of next instruction) is pU5hed on the
stack.
The status register is pushed on the stack.
The IE (interrupt enable) bit in 5T is set to 0, disabling maskable interrupts, and 5T is set to 00000010h.
Finally, the trap vector is loaded into the PC.

The TM53401 0 generates the trap vector addresses as shown below:
Trap

Number

o
1
2

4
5
8
7
8
8
10

12
13
14
15
18
17
18
18

28
28
30

Aden.
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF
>FFFF

l=:::JiiiL==1 Reaet
Extemal Interrupt 1

FFEO
FFCO
FFAO
FFBO
FF80
FF40
Tr
3-7
FF20
FFOO I - - - - d r - - - I
FEEO
FECO
FfAO
FE80
FE80
FE40
FE20
FEOO

FOEO
FCCO
FIlo\O
FD80
FD80
1"040
FD20

Extemal Interrupt 2

Non Muklble Interrupt

Holt Interrupt
DIIipIay lnternJDt
WIndow Vlolatfon

Traps 12-28

FDOO

FCEO

FCCO
FCAO

FCBO
FCBO

>FFFF
~~~;:::::::I Illegal Opcode
>FFFF FC40
FC20 I>FFFF FCOO h-....I...irl"--rI

The stack, which is located in external memory, grows toward lower addresses. The PC and 5T are pushed on the stack M5W first. and the 5P is
predecremented before each word is loaded onto the stack.

12-253

TRAP

Software Interrupt

Notes:
1. The level 0 trap differs from all other traps; it does not save the old
status register or program counter. This may be useful in cases
where the stack pointer is corrupted or uninitialized; such a situation could cause an erroneous \A!!"ite.
2. The NMI bit does not affect the operation of TRAP S.

For more information, refer to Section S (Interrupts, Traps, and Reset).

Machine
States

16,19 (SP aligned)
30,33 (SP nonaligned)

Status Bits

a
a
z a
v a
N

Examples

12-254

After

Code

Before

TRAP 0
TRAP 1

PC
xxxxxxxxh
xxxxxxxxh

SOOOOOOOh
SOOOOOOOh

FFFFFFEOh
FFFFFFCOh

"'or,
L LlICU. IUIIUVV::' Lilt: ldUIt::.

Table 13-9. PIXBLT Transfer Timingt
PBH= 0
Row Lengths
and Alignment

Short (N=1)
O>S
OS
OS
OS
O"S
OS
OS
O"1

RESET

-1.L

HOS'
INTERFACE

*1I

BUS

SYNC AND
BLANKING

.I
V.L--....

INTERRUPT
REGISTERS

1
1
1
1

INSTRUCTION
DECODE

1
1

II
11
1
1
1
1

INSTRUCTION
CACHE

I"'"

HOST
INTERFACE.....

REGISTERS

1
1

.....
1_--I
1
COUNTER
1
1 I-~==---I 1
1
STATUS
1+0---1
PROGRAM

1 r-......;.R=E;.;:G=IS:..:.T,:ER:':""'--I 1

T Ll

VIDEO TIMING........
REGISTERS

L __________ J
LOCAL MEMOR~
CONTROL
REGISTERS

----I

....----

I
1
I
1 t-------i 1
I
I
ALU

GPR FILE A

MICRO CONTROL
ROM

GPR FILE B

1
1
1 STACK POINTER 1-+---1
1L ___________ J1
EXECUTION UNIT

LOCAL MEMORY
CONTROL LOGIC
AND BUFFERS

INTERNAL CLOCK
CIRCUITRY

~--'

CLOCK
OUTPUTS
CLOCK
INPUTS

------------l}-------------------------J
LOCAL MEMORY
INTERFACE BUS

FIGURE 1. TMS34010 INTERNAL ARCHITECTURE

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

A-5

TMS34010
GRAPHICS SYSTEM PROCESSOR

The TMS3401 0 provides single-cycle execution of most common integer arithmetic and Boolean operations
from its instruction cache. Additionally, the TMS3401 0 incorporates a hardware barrel shifter that provides
a single-state bidirectional shift and rotate function for 1 to 32 bits.
A microcoded local memory controller supports pipelined memory write operations of variable-size fields
that can be performed in parallel with subsequent instruction execution.
TMS34010 graphics processing hardware supports pixel and pixel-array processing capabilities for both
monochrome and color systems that have a variety of pixel sizes. The hardware incorporates two-operand
raster operations with Boolean and arithmetic operations, XY addressing, window clipping, window checking
operations, 1 to n bits per pixel transforms, transparency, and plane masking. The architecture further
supports operations on single pixels (PIXT instructions) or on two-dimensional pixel arrays of arbitrary size
(PixBlts).
The TMS3401 O's flexible graphics processing capabilities allow software-based graphics algorithms without
sacrificing performance. These algorithms include: arbitrary window size, custom incremental curve drawing,
and two-operand raster operations.
register files
Boolean, arithmetic, byte, and field move instructions operate on data within the TMS3401 O's generalpurpose register files. The TMS3401 0 contains thirty-one 32-bit registers, including a system stack pointer
(SP). The SP is accessible to both Register File A and B as the sixteenth register. Transfers between registers
and memory are facilitated via a complete set of field MOVE instructions with selectable field sizes. Transfers
between registers are facilitated via the MOVE instruction.
The fifteen general-purpose registers in Register File A are used for high-level language support and assembly
language programming. The fifteen registers in Register File B are dedicated to special functions during
PixBlts and other pixel operations, but can be used as general-purpose registers at other times.

A-6

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

TMS34010
GRAPHICS SYSTEM PROCESSOR

31IMSB)

31(MSB)

OILSB)

OILSB)
SOURCE ADDRESS
IPIXBLTS)

SADDR

SPTCH

SOURCE PITCH

DADDR

DESTINATION ADDRESS
IPIXBLTS AND FillS)

DPTCH

DESTINATION PITCH

OFFSET

WSTART

WEND

WINDOW END

DYDX

DELTA YI DELTA X

COlORO

COlORO
IBINARY PIXBlTS)

COLOR1

COlOR1
IBINARY PIXBlTS, FilLS AND DRAV)

A10

B10

TEMPORARY REG)STER

A11

B11

TEMPORARY REGISTER

A12

B12

TEMPORARY REGISTER

A13

B13

TEMPORARY REGISTER

A14

B14

TEMPORARY REGISTER

STACK POINTER

WINDOW START

THESE ARE USED AS TEMPORARY
STORAGE FOR PIXBLT AND
FilL INSTRUCTIONS.

STACK POINTER

FIGURE 2. REGISTER FILES A AND B
program counter (PC)
The TMS3401 O's 32-bit program counter register points to the next instruction-stream word to be fetched.
Since instruction words are aligned to 16-bit boundaries, the four LSBs of the PC are always zero.
instruction cache
An on-chip instruction cache contains 256 bytes of RAM and provides fast access to instructions. It operates
automatically and is transparent to software. The cache is divided into four 64-byte segments. Associated
with each segment is a 23-bit segment address register to identify the addresses in memory corresponding
to the current contents of the cache segment. Each cache segment is further partitioned into eight
subsegments of four words each, Each subsegment has associated with it a present (P) flag to indicate
whether the subsegment contains valid data.

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

A-7

TMS34010
GRAPHICS SYSTEM PROCESSOR

P
FLAGS

SEGMENT START ADDRESS

,..-J>-.

'.....-------23-------_.1

DATA REGISTERS

11111~H:H~!HH:illlll

SUBSEGMENT 0

SUBSEGMENT 1
SUBSEGMENT 2
5UDSi:Giv1~r.iT

SUBSEGMENT 4
SUBSEGMENT 5
SUBSEGMENT 6

rMm"

SUBSEGMENT 7

SUBSEGMENT 0
SUBSEGMENT 1

WORD 0

SUBSEGMENT 2

WORD 1

SUBSEGMENT 3

WORD 2

SUBSEGMENT 4

WORD 3

SUBSEGMENT 5

IIIII~H:H~!HH:~IIIII

SUBSEGMENT 6

SUBSEGMENT 7

SUBSEGMENT 2
OF SEGMENT 1

SUBSEGMENT 0
SUBSEGMENT 1

SUBSEGMENT 2

SUBSEGMENT 3

SUBSEGMENT 4

SEGMENT 2
MOST
RECENTLV_
USED

SUBSEGMENT 5

SUBSEGMENT 6
SUBSEGMENT 7

LRU
>STACK

SUBSEGMENT 0

LEAST
RECENTLV_
USED

SUBSEGMENT 1

SUBSEGMENT 2

SUBSEGMENT 3

SUBSEGMENT 4

>SEGMENT 3

SUBSEGMENT 5

SUBSEGMENT 6
SUBSEGMENT 7

FIGURE 3. INSTRUCTION CACHE

A-8

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

TMS34010
GRAPHICS SYSTEM PROCESSOR

The cache is loaded only when an instruction requested by the TMS3401 0 is not already contained within
the cache. A least-recently-used (LRU) algorithm is used to determine which of the four segments of the
cache is overwritten with the new data. For this purpose, an internal four-by-two LRU stack is used to
keep track of cache usage.
status register
The status register (ST) is a special-purpose 32-bit register dedicated to status codes set by the results
of implicit and explicit compare operations and parameters used to specify the length and behavior of fields
and 1.

98765432
FSl

N . Sign bit
C • Carry bit

Z - Zero bit
V . Overflow bit
PBX - Pix Bit executing

IE
FE 1
FS 1
FEO
FSO

.
•

FSO

Interrupt enable bit
Field extension bit 1
Field size bit 1
Field extension bit 0
Field size bit 0

FIGURE 4. STATUS REGISTER
fields, bytes, pixels, and pixel arrays
A 26-bit address output by the TMS3401 0 selects a 16-bit word of physical memory; logically, however,
the TMS3401 0 views memory data as fields addressable at the bit level. Primitive data types supported
by the TMS34010 include: bytes, pixels, two 1- to 32-bit fields, and user-defined pixel arrays.
Fields 0 and 1 are specified independently to be from 1 to 32 bits in length. Bytes are special 8-bit cases
of the field data type, while pixels are 1, 2, 4, 8 or 16 bits in length. In general, fields (including bytes)
may start and terminate on arbitrary bit boundaries; pixels must pack evenly into 16-bit words.
pixel operations
Pixel arrays are two-dimensional data types of user-defined width, height, pixel depth (number of bits per
pixel), and pitch (distance between rows). A pixel or pixel array may be accessed by means of either its
memory address or its XY coordinates. Transfers of individual pixels or pixel blocks are influenced by the
pixel processing, transparency, window checking, plane masking, or corner adjust operations selected.
I/O registers
The GSP contains an on-chip block of twenty-eight 16-bit I/O registers mapped into the TMS3401 0' s
memory address space. They can be accessed either by the TMS3401 O's CPU or by the host processor
via the host interface. The I/O registers contain control parameters necessary to configure the operation
of the following interfaces: interface to host processor (5 I/O registers), interface to local memory (6
registers), video timing and screen refresh functions (15 registers), and externally and internally generated
interrupts (2 registers). The I/O registers also furnish status information on these interfaces.

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

A-9

TMS34010
GRAPHICS SYSTEM PROCESSOR

ADDRESS

,--"'--.
OC00001FOh

REFCNT

DRAM REFRESH COUNT

OC00001EOh

DPYADR

DISPLAY ADDRESS

OCOOOO1DOh

VCOUNT

VERTICAL COUNT

OC00001COh

HCOUNT

HORIZONTAL COUNT

OC00001BOh

DPYTAP

DISPLAY TAP POINT

OC00001AOh
OC0000190h
OC00001BOh
OC0000170h

t - RESERVED
-

PLANE MASK

OC0000160h

PMASK

OC0000150h

PSIZE

OC0000140h

CONVDP

OC0000130h

CONVSP

CONVERSION (SOURCE PITCH)

OC0000120h

INTPEND

INTERRUPT PENDING

OC0000110h

INTENB

INTERRUPT ENABLE

OC0000100h

HSTCTLH

HOST CONTROL (S MSB'S)

OCOOOOOFOh

HSTCTLL

HOST CONTROL (S LSB'S)

OCOOOOOEOh

HSTADRH

HOST ADDRESS (16 MSB'S)

OCOOOOODOh

HSTADRL

HOST ADDRESS (16 LSB'S)

OCOOOOOCOh

HSTDATA

HOST DATA

OCOOOOOBOh

CONTROL

OCOOOOOAOh

DPYINT

OC0000090h

DPYSTRT

OCOOOOOSOh

DPYCTL

DISPLAY CONTROL

OC0000070h

VTOTAL

VIDEO TOTAL

OC0000060h

VSBLNK

VERTICAL START BLANK

OC0000050h

VEBLNK

VERTICAL END BLANK

OC0000040h

VESYNC

VERTICAL END SYNC

OC0000030h

HTOTAL

HORIZONTAL TOTAL

OC0000020h

HSBLNK

HORIZONTAL START BLANK

OC0000010h

HEBLNK

HORIZONTAL END BLANK

OCOOOOOOOh

HESYNC

HORIZONTAL END SYNC

PIXEL SIZE
CONVERSION (DESTINATION PITCH)

CONTROL
DISPLAY INTERRUPT
DISPLAY START

FIGURE 5. I/O REGISTERS
host interface registers
The host interface registers are provided for communications between the TMS34010 and the host
processor. The registers are mapped into five of the I/O register locations accessible to the TMS3401 O.
These same registers are mapped into four locations in the GSP interface to the host.
One of the registers is devoted to host interface control functions such as the passing of interrupt requests
and 3-bit status codes from host to TMS3401 0 and from TMS34010 to host. Other control functions
available to the host processor include flushing the instruction cache, halting the TMS34010, and
transmitting a non-maskable interrupt request to the TMS3401 O.

A-10

TEXAS

"!1

INSTRUMENTS
POST OFFICE BOX 1443

•

HOUSTON. TEXAS 77001

TMS34010
GRAPHICS SYSTEM PROCESSOR

The remaining host registers are used for block transfers between the TMS3401 0 and host processor.
The host uses these registers to indirectly access blocks within the TMS3401 O's local memory. Two of
the 16-bit registers contain the 32-bit address of the current word location in memory. Another 16-bit
register buffers data transferred to and from the memory by the host processor. The host interface can
be programmed to automatically increment the pointer address following each transfer to provide the host
with rapid access to a block of sequential addresses.
memory interface control registers
Six of the I/O registers are dedicated to various local memory interface functions including:
•
•
•
•

Frequency and type of DRAM refresh cycles
Pixel size
Masking (write protection) of individual color planes
Various pixel access control parameters
- Window checking mode
- Boolean or arithmetic pixel processing operation
- Transparency
- Pix Bit direction control

video timing and screen refresh
Fourteen I/O registers are dedicated to video timing and screen refresh functions. The TMS3401 0 generates
the horizontal sync (HSYNC), vertical sync (VSYNCL and blanking (BLANK) signals used to drive a video
monitor in a graphics system. These signals are controlled by means of a set of programmable video timing
I/O registers and are based on the input video clock, VCLK. VCLK does not have to be synchronous with
respect to INCLK, the TMS3401 O's CPU input clock.
The TMS34010 directly supports multiport video RAMs (VRAMs) by generating the memory-to-register
load cycles necessary to refresh the display being shown on the video monitor. The memory locations
from which display information is taken, as well as the number of horizontal scan lines displayed between
memory-to-register load cycles, are programmable. VRAM tap point addresses are also fully programmable
to support horizontal panning.
The TMS34010 supports various screen resolutions and either interlaced or non interlaced video. The
TMS34010 can optionally be programmed to synchronize to externally generated sync signals so that
graphics images created by the TMS3401 0 can be superimposed upon images created externally. The
external sync mode can also be used to synchronize the video signals generated by two or more TMS3401 0
chips in a multiple-TMS34010 graphics system.
interrupt interface registers
Two dedicated I/O registers monitor and mask interrupt requests to the TMS3401 0, including two externally
generated interrupts and three internally generated interrupts. An internal interrupt request can be generated
on one of the following conditions:
• Window violation: an attempt has been made to write a pixel to a location inside or outside a
specified window boundary.
• Host interrupt: the host processor has set the interrupt request bit in the host control register.
• Display interrupt: a specified line number in the frame has been displayed on the screen.
A nonmaskable interrupt occurs when the host processor sets a particular control bit in the host interface
registers. The TMS3401 0 reset function is controlled by a dedicated pin.

TEXAS .."
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

A-11

TMS34010
GRAPHICS SYSTEM PROCESSOR

memory controller/local memory interface
I

The memory controller manages the TMS3401 O's interface to the local memory and automatically performs
the bit alignment and masking necessary to access data located at arbitrary bit boundaries within memory.
The memory controller operates autonomously with respect to the CPU. It has a "write queue" one field
(1 to 32 bits) deep that permits it to complete the memory cycles necessary to insert the field into memory
without delaying the execution of subsequent instructions. Only when a second memory operation is
required before ihe rnernory (;oniruiit:H hi:l::i GUIIIJ,Jieitlu the filst ope.-ation is the Trv1S3401 0 forced to defer

instruction execution.
The TMS34010 directly interfaces to all standard dynamic RAMs and, in particular to JEDEC standard
64K and 256K video RAMs such as the TMS4161 and TMS4461 Multiport VRAMs. The TMS34010
memory interface consists of a triple-multiplexed address/data bus plus the associated control signals.
Row address, column address, and data are multiplexed over the same address/data lines. DRAM refresh
is supported with a variety of modes including CAS-before-RAS refresh.
TMS34010 memory map
From the programmer's point of view, the TMS3401 0 treats data and instructions as residing in the same
memory space.
BIT 232 _1
(LAST BIT IN MEMORYI
ADDRESS
OFFFFFFFOh

1
64 W}RDS

OFFFFFCOOh
OFFFFFBFOh

OFFFFEOOOh
OFFFFDFFOh
OC0002000h
OC0001FFOh

:- INTERRUPT
VECTORS
,~

51210RDS

226_~024

•

:- RESERVED

WORDS

GENERAL
USE

to RESERVED

51210RDS
OC0000200h
OC00001FOh

,,+~ }

INTERNAL I/O
REGISTERS

OCOOOOOOOh
OBFFFFFFOh

3x2 26 WORDS

OOOOOOOOOh

}

GENERAL
USE

BIT 0
(FIRST BIT IN MEMORYI

FIGURE 6. MEMORY MAP

A-12

TEXAS •
INSTRUMENTS
POST OFFICE BOX t 443 •

HOUSTON. TEXAS 77001

TMS34010
GRAPHICS SYSTEM PROCESSOR

instruction set
The TMS3401 0 instructions fall into three categories. The graphics instructions manipulate pixel data,
accessed via memory addresses or XV coordinates. They provide support for graphics operations such
as array and raster ops, pixel processing, windowing, plane masking, and transparency. The move
instructions comprehend bit addressing and field operations; they manipulate fields of data using linear
addressing for transfer to and from memory and the register file. The TMS34010 general-purpose
instructions provide a complete set of arithmetic and Boolean operations on the register file as well as
general program control and data processing. Partial timing information is provided in the table below.
The two values given for jump instructions in the Minimum Cycles column indicate the jump and no-jump
conditions, respectively. Full timing information can be obtained in the TMS34010 User's Guide (number
SPVU001A).
The following abbreviations are used below in the opcodes: S (source register), D (destination register),
R (register file select), F (field select), K (constant), M (cross AlB file boundary), Z (draw option), code
(jump select code), X (don't care), N (trap select and stack adjust), RS (source register), RD (destination
register), xxxx (address displacement), IL (32-bit immediate operand), and IW (16-bit immediate operand).

GRAPHICS INSTRUCTIONS
SYNTAX

STATUS

NO.
MINIMUM
WORDS CYCLES

DESCRIPTION

16-BIT OPCODE
MSB

ADDXY Rs, Rd
CMPXY Rs, Rd
CPW Rs, Rd
CVXYL Rs, Rd
DRAV Rs, Rd

Add Registers in XY Mode
Compare X and Y Halves of Registers

Compare Point to Window

1
3
t

Convert XV Address to Linear Address

FILL L
FILL XY

Draw and Advance
Fill Array with Processed Pixels: Linear
Fill Array with Processed Pixels: XY

LINE Z
MOVX Rs, Rd

Line Draw
Move X Half of Register

MOVY Rs, Rd
PIXBLT B,L
PIXBLT B,XY

Move Y Half of Register
Pixel Block Transfer: Binary to Linear
Pixel Block Transfer and Expand: Binary to XY

PIXBLT L,L
PIXBLT L,XY

Pixel Block Transfer: Linear to Linear
Pixel Block Transfer: Linear to XY
Pixel Block Transfer: XY to Linear

PIXBLT XY, L
PIXBLT XY,XY
PIXT Rs,"Rd
PIXT Rs, "Rd.XY
PIXT "Rs, Rd
PIXT "Rs,"Rd
PIXT "Rs.XY, Rd
PIXT "Rs.XY, "Rd.XY
SUBXY Rs,Rd

Pixel Block Transfer: XY to XY
Pixel Transfer: Register to Indirect
Pixel Transfer: Register to Indirect XY
4
t

Pixel Transfer: Indirect to Register

Pixel Transfer: Indirect to Indirect
Pixel Transfer: Indirect XY to Register

Pixel Transfer: Indirect XY to Indirect XY
Subtract Registers in XY Mode

BITS
LSB

1110 ODDS SSSR
1110 010S SSSR
1110 011S SSSR
1110 100S SSSR

DODD N C Z V
DODD N C Z V
DODD
v
DODD

1111 011S SSSR DODD
0000 1111 1100 0000
0000 1111 1110 0000

1101 1111 Z001 1010
1110 11 OS SSSR DODD
1110 111S SSSR DODD
0000 1111 1000 0000

0000 1111 1010 0000
0000 1111 0000 0000
0000 1111 0010 0000
0000 1111 0100 0000

0000 1111 0110 0000
1111 1ODS SSSR DODD
1111 ODDS SSSR DODD
1111 101S SSSR DODD

1111

11 OS SSSR DODD

1111 001S SSSR DODD
V
1111 010S SSSR DODD
1110 001S SSSR DODD N C Z V

tNumber of cycles depends on pixel size and/or pixel array size and graphics option selected. See TMS3401 0 User's Guide (SPVU001 AI.

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

A-13

TMS34010
GRAPHICS SYSTEM PROCESSOR

MOVE INSTRUCTIONS
SYNTAX

NO. MINIMUM
WORDS CYCLES

DESCRIPTION

STATUS
16-BIT OPCODE
MSB

BITS

LSB
SSSR DODD
SSSR DODD
SSSR DODD
SSSR DODD
SSSRDDDD

MOVB RS,*Rd
MOVB *Rs.Rd

Move Byte: Register to Indirect
Move Bvte: Indirect to Register

MOVB *Rs,*Rd
MOVe Rs, *Rd(offset)

Move Byte: Indirect to Indirect
Move Byte: Register to Indirect with offset.

MOVB *Rs(offset),Rd
Move *Rs(offset), *Rd(offset)

Move Byte: Indirect with offset. to Register
Move Byte: Ind. with offset. to Ind.
with offset.
Move Byte: Register to Absolute

1011 110S SSSR DODD -

MOVB Rs,@Daddress

Move Byte: Absolute to Register
Move Byte: Absolute to Absolute

3
5

00000101
00000111
0000 0011
0100 llMS

Move @Saddress,Rd
MOVB @Saddress,@Oaddress
MOVE RS,Rd
MOVE Rs, *Rd,F
MOVE Rs, - *Rd,F

Move Register to Register
Move Field: Register to Indirect
Move Field: Register to Indirect (pre-dec)

MOVE
MOVE
MOVE
MOVE

Move
Move
Move
Move

Rs,*Rd+,F
*Rs,Rd,F
- *Rs,Rd,F
*Rs+,Rd,F

Field:
Field:
Field:
Field:

2
2

1000
1000
1001
1010
1010

110S
IllS
110S
110S
IllS

l11R
l11R
0100
SSSR

SSSS
DODD
0000
DODD

N
N

Z
Z

0
0

-Z 0
- Z 0

- N
N N -

N
N

1000 OOFS SSSR DODD 1010 OOFS SSSR DODD -

1001
1000
1010
1001

OOFS
01FS
01FS
01FS

SSSR
SSSR
SSSR
SSSR

DODD
DODD
DODD
DODD

Z 0
Z 0
Z 0

MOVE *Rs, *Rd,F
MOVE - *Rs, - *Rd,F
MOVE *Rs+,*Rd+,F

Move Field: Indirect to Indirect
Move Field: Ind. (pre-dec) to Ind. (pre-dec)
Move Field: Ind. (post-inc) to Ind. (post-inc)

1
1

MOVE Rs, * Rd(offset),F
MOVE *Rs(offset),Rd,F

Move Field: Register to Indirect with offset.
Move Field: Indirect with offset. to Register

1011 OOFS SSSR DODD - 1011 01FS SSSR DODD N -

- Z 0

MOVE *Rs(offset), *Rd + ,F

1101 OOFS SSSR DODD -

MOVE *Rs(offset).*Rd(offset),F

Move Field: Ind. with offset. to Ind.
(post-inc)
Move Field: Ind. with offset. to Ind.

MOVE Rs,@Daddress,F

with offset.
Move Field: Register to Absolute

1011 10FS SSSR DODD - 0000 01Fl 100R SSSS - -

MOVE @Saddress,Rd,F
MOVE @Saddress,*Rd+,F
MOVE @Saddress,@Oaddress,F

Move Field: Absolute to Register
Move Field: Absolute to Indirect (post-inc)
Move Field: Absolute to Absolute

3
3
3
3
5

000001Fl 101R DODD N 1101 01FO OOOR DODD - 000001Fl 11000000 - -

Z 0
---

1000 10FS SSSR DODD 1010 10FS SSSR DODD 1001 10FS SSSR DODD -

tNumber of cycles depends on field size and alignment. See TMS3401 0 User's Guide (SPVUOOI A).

A-14

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

TMS34010
GRAPHICS SYSTEM PROCESSOR

GENERAL INSTRUCTIONS
SYNTAX

DESCRIPTION

NO.

MINIMUM

WORDS

CYCLES

STATUS
16-BIT OPCODE

BITS
LSB

MSB
ABS Rd

Store Absolute Value

0000 0011

ADD Rs,Rd

Add Registers

0100 OOOS SSSR DODD

looR DODD

N C Z V

Z 0

ADDC Rs,Rd

Add Register with Carry

0100 001S SSSR DODD

N C Z V

ADDllW,Rd

Add Immediate (16 Bitsl

N C Z V

Add Immediate (32 Bits)

2
3

0000 1011 OOOR DODD

ADDllL,Rd

2
3

0000 1011 001R DODD

N C Z V

ADDK K,Rd

Add Constant (5 Bits)

0001

OOKK KKKR DODD

N C Z V

AND Rs,Rd

0101

OOOS SSSR DODD

ANDllL,Rd

AND Registers
AND Immediate (32 Bits)

ANON Rs,Rd

AND Register with Complement

ANDNllL,Rd

AND Not Immediate (32 Bits)

BTST K,Rd

Test Register Bit - Constant

BTST RS,Rd

Test Register Bit - Register

CLR Rd
CLRC

Clear Register

0101

Clear Carry

0000 0011

CMP Rs,Rd

Compare Registers

0100 100S SSSR DODD

N C Z V

0000 1011

010R DODD

N C Z V

0000 1011

011R DODD

N C Z V

1
3

CMPllW,Rd

Compare Immediate (16 Bits)

CMPllL,Rd

Compare Immediate (32 Bits)

DEC Rd

Decrement Register

1
3

0101

2
3
1
3

2
3

001S SSSR DODD

100R DODD

l1KK KKKR DODD

0100 101S SSSR DODD

0000 1011
0001

0001

0110 DOOR DODD
0010 0000

Disable Interrupts

DIVS Rs,Rd

Divide Registers Signed

0101

DIVU Rs,Rd

Divide Registers Unsigned

EINT

Enable Interrupts

0101 101S SSSR DODD
0000 1101 0110 0000

EXGF Rd,F

Exchange Field Size

LMO RS,Rd
MMFM Rs,Register List

Leftmost One
Move Multiple Registers from Memory

MMTM Rd,Register List

Move Multiple Registers to Memory

MODS Rs,Rd

Modulus Signed

MODU RS,Rd

Modulus Unsigned
Move Immediate (16 Bits)

MOVllW,Rd
MOVllL,Rd
MOVK K,Rd

Move Immediate (32 Bits)

0000 0011

1101

0100 001R DODD

DINT

3
1

100R DODD

0000 1011

0110 0000

100S SSSR DODD

01Fl

Z V

OOOR DODD

0110 101S SSSR DODD

1
2
2
1

0110 110S SSSR DODD
0110 111S SSSR DODD

2
3

35
2
3

Move Constant (5 Bits)

Z V

0000 1001

101R DODD

0000 1001

100R DODD
N

Z V

0000 1001

110R DODD

0000 1001

l11R DODD

0001

10KK KKKR DODD

0101

110S SSSR DODD

F~l

0101

111S SSSR DODD

Z V

Z 0
Z 0

MPYS Rs,Rd

Multiply Registers (Signed)

5+ FSl
2

MPYU Rs,Rd

Multiply Registers (Unsigned)

NEG Rd

Negate Register

0000 0011

101R DODD

N C Z V

NEGB Rd

Negate Register with Borrow

0000 0011

110R DODD

N C Z V

NOP

No operation

0000 0011

0000 0000

NOT Rd

Complement Register

0000 0011

l11R DODD

OR Rs,Rd

OR Registers
OR Immediate (32 bits)

0101 010S SSSR DODD
0000 1011 101R DODD

RL K,Rd
RL RS,Rd

Rotate Left - Constant

SETC

Set Carry

0000 1101

1110 0000

SETF FS,FE,F

Set Field Parameters

1,2

0000 01 Fl

01 FS SSSS

SEXT Rd,F

Sign Extend to Long

0000 01Fl

OOOR DODD

ORllL,Rd

0011

Z
Z
Z

C Z
C Z

OOKK KKKR DODD

0110 100S SSSR DODD

Rotate Left - Register

Z
Z

tNumber of cycles depends on number of registers in list and stack alignment. See TMS34010 User's Guide (SPVU001A).

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

A-15

TMS34010
GRAPHICS SYSTEM PROCESSOR

SYNTAX

DESCRIPTION

NO.

MINIMUM

WORDS

CYCLES

STATUS
16-BIT OPCODE
MSB

SLA K,Rd

Shift Left Arithmetic - Constant

SLA Rs,Rd

Shift Left Arithmetic - Register

SLL K,Rd

3
3

BITS
LSB

0010 OOKK KKKR DODD N C

0110 ODDS SSSR DODD N C

Shift Left Logical - Constant

0010 01KK KKKR DODD

C
C
SSSR DODD N C
KKKR DODD
C

Z
Z
Z
Z

Shift Right Logical - Constant

OnO
0010
0110
0010

SRL Rs,Rd

Shift Right Logical - Register

0110 011S SSSR DODD

SUB RS,Rd

Subtract Registers

0100 010S SSSR DODD N

SUBB RS,Rd

Subtract Registers with Borrow

0100 011S SSSR DODD N

SUBIIW,Rd

Subtract Immediate (16 Bits)

1011

111R DODD N C

SUBIIL,Rd

Subtract Immediate 132 Bits)

0000

1101

ODOR DODD N C

SUBK K,Rd

Subtract Immediate 15 Bits)

0001

01KK KKKR DODD N C

XOR RS,Rd

Exclusively OR Registers

0101

011S SSSR DODD

XORIIL,Rd

Exclusively OR Immediate Value 132 Bits)

ZEXT Rd,F

Zero Extend to Long

SLL HS,Hd

:Shift Lett Logical

SRA K,Rd

Shift Right Arithmetic - Constant

Heglster

SRA RS,Rd

Shift Right Arithmetic - Register

SRL K,Rd

2
3
1
3

00"15
10KK
010S
11 KK

0000

SSSH DODD

KKKR DODD N

0000 1011

1100 DODD

0000 01Fl

001R DODD

PROGRAM CONTROL AND CONTEXT SWITCHING
NO.
SYNTAX

MINIMUM

STATUS

WORDS CYCLESt

DESCRIPTION

16-BIT OPCODE
MSB

BITS
LSB

CALL Rs

Call Subroutine Indirect

0000 1001 001R DODD

CALLA Address

Call Subroutine Absolute

0000

CALLR Address

Call Subroutine Relative

DSJ Rd,Address

Decrement Register and Skip Jump

DSJEQ Rd,Address

Conditionally Decrement Register and Skip Jump

DSJNE Rd,Address

Conditionally Decrement Register and Skip Jump

2
2
2
2

DSJS Rd,Address

Decrement Register and Skip Jump

5
3,2
3,2
3,2
2,3

EMU

Initiate Emulation

Short

0101

1111

0000 1101 0011

1101

1111

0000 1101

100R DODD

0000

1101

101R DODD

0000

1101

110R DODD

0011

lDxx

xxxR DODD

0000 0001

0000 0000

0000 0001

001R DODD

0000 0001

010R DODD

EXGPC Rd

Exchange Program Counter with Register

GETPC Rd

Get Program Counter into Register

GETST Rd

Get Status Register into Register

JAcc Address

Jump Absolute Conditional

JRcc Address

Jump Relative Conditional

3
2

JRcc Address

Jump Relative Conditional - Short

JUMP Rs

Jump Indirect

0000 0001

100R DODD

3,4

11 00

code

1000 0000

3,2

1100 code

0000 0000

2,1

1100

code

xxxx

011R DODD

PO PST

Pop Status Register from Stack

0000 0001

1 100 0000

PUSHST

Push Status Register onto Stack

0000 0001

1110 0000

PUTST Rs

Copy Register into Status

0000 0001

101R DODD N C

RETI

Return from Interrupt

0000

1001

0100 0000

RETS IN)

Return from Subroutine

0000 1001

011N NNNN

REV Rd

Get Revision Number

0000 0000 001R DODD

TRAP N

Software Interrupt

0000 1001

NeZ

OOON NNNN 0

tWhere two numbers appear, the first number assumes that the jump is taken, and the second assumes that the jump is not taken.

A-16

TEXAS

-1!1

INSTRUMENTS
POST OFF1CE BOX 1443 •

HOUSTON, TEXAS 77001

TMS34D1D
GRAPHICS SYSTEM PROCESSOR

development systems and software support
Texas Instruments, together with third party suppliers, offers a full range of hardware and software
development tools for the TMS34010. The support environment is aimed at four areas of support with
the key tools based on the IBM PC, DEC VAX, SUN, MAC II, APOLLO and TI Professional computers:
DESIGNER
Hardware

TOOLS
XDS-22 Real Time Emulator (with PC-based Debugger Interface)
PC Software Development Board (with Debugger Interface)

Software

Assembly Language Package, including:
Assembler, Linker, Archiver, ROM Object Format Converter, Software Simulator (PC only)
Graphics/Math Function Library
Bit-Mapped Font Library
CCITT Data Compression/Decompression Function Library

8514A Emulation Function Library
Languages

C Compiler Package including:
TMS34010 C Compiler
Runtime Support

Systems

Window Management Support
Image Processing Support

Graphics Interfaces and Standards
Debugger Adaptation Software

Further support is provided through a network of Regional Technology Centers (RTCs).

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

A-17

TMS34010
GRAPHICS SYSTEM PROCESSOR
TMS340 FAMILY HARDWARE AND SOFTWARE SUPPORT
SILICON
Graphics System Processor 68-Pin PLCC
Video System Controller 68-Pin PLCC
Color Palette 22-Pin OIP
64Kx 1 Multiport Memory 22-LeQd PLCC (120 and 150 ns)
64Kx 1 Multiport Memory 22-Pin DIP (120 and 150 ns)
64Kx4 Multiport Memory 24-Pin DIP (l2U and 1 bO nsl

PART NUMBER
TMs34010FNL
TMS34061 FNL
TMS34070NL
TMS4161FML
TMS4161NL
TMS446iNi..

SOFTWARE TOOLS
TMS34010 Assembler Package:
Assembler, Linker, Archiver,
Object Format Converter, Simulator
TMS34010 Assembler Package:
Assembler, Linker, Archiver,
Object Format Converter

COMPUTER

TMS34010 C Compiler Package

Combination packages:
Assembler, Linker, Archiver,
Object Format Converter, Simulator.
C Compiler with runtime support
TMS34010 Graphics/Math
Function Library

OPERATING
SYSTEM

IBMITI PC

MS-DOS 2.11

+ TMDS3440808002

VAX
VAX
VAX
HP
Sun
Mac 11
Apollo
IBM/TI PC
VAX
VAX
VAX
HP
Sun
Mac II
Apollo

VMS
ULTRIX
System V
System V
System V
MPW
System V
MS-DOS 2.11
VMS
ULTRIX
System V
System V
System V
MPW
System V

TMDS3440200059
TMDS3440200069
TMDS3440200089
TMDS3440500089
TMDS3440550086
TMDS3440560021
TMDS3440570088
TMDS3440805002
TMDS3440205059
TMDS3440205069
TMDS3440205089
TMDS3440505089
TMDS3440555086
TMDS3440565021
TMDS3440575088

IBM/TI PC

MS-DOS 2.11

+ TMDS3440804003

IBM/TI PC - Source
VAX - Source

TMS34010 Bit-Mapped Font Library

IBM/TI PC
VAX

TMDS3440802202
TMDS3440802208
MS-DOS 2.11
ALL

+ TMDS3440802302
TMDS3440202308

IBM/TI PC
MS-DOS 2.11 + TMDS3440802102
VAX
All
TMDS3440202108
8514/A Emulation Libraif,MDS- IBM/TIPC,
MS-DOS 2.11 +
3440
8020
02

TMS34010 CCITT Function Library
TMS34010

TMS34010 PC Debugger Development Package
(For Internal Use)

IBM/TI PC

MS-DOS 2.11 + TMDS3440806002

TMS3401 0 PC Debutfer Development Package
(For Resale)

IBMITI PC

MS-DOS 2.11 + TMDS3440806003

HARDWARE TOOLS
TMS34010 XDS-22 Real-Time Emulator with BT&T

COMPUTER

Color Graphics Controller Board (TMS34061, TMS34070)
TMS34010 Software Development Board

VERSION
U.S.
Europe

IBMITI PC
IBM/TI PC

DESIGN KITS
TMS340 Graphics Design Kit, including TMS34061, TMS34070, TMS4161s
TMS34010 Graphics Design Kit, including TMS34010, TMS34070, TMS4461 s, PC Assembler

A-18

PART NUMBER

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

PART NUMBER
TMDS346991 0000
TMDS3469981000
TMDS3471804000
TMDS3411804420
PART NUMBER
TMS340GDK
TMS34010GDK

TMS34010
GRAPHICS SYSTEM PROCESSOR
reset
Reset puts the TMS3401 0 into a known initial state. It is entered when the input signal at the RESET
pin is asserted low. RESET must remain active low for a minimum of 40 local clock (LCLKl and LCLK2)
periods to ensure that the TMS3401 0 has sufficient time to establish its initial internal state.
While RESET remains asserted, all outputs are in a known state, no DRAM-refresh cycles take place, and
no screen-refresh cycles are performed.
At the low-to-high transition of the RESET signal, the state of the HCS input determines whether the
TMS34010 will be halted or begin executing instructions. The TMS3401 0 may be in one of two modes,
host-present or self-bootstrap mode.
1 . Host-Present Mode
If HCS is high at the end of reset, TMS34010 instruction execution is halted and remains halted
until the host clears the HLT (halt) bit in HSTCTL (host control register). Following reset, the eight
RAS-only refresh cycles required to initialize the dynamic RAMs are performed automatically by the
TMS34010 memory control logic. As soon as the eight RAS-only cycles are completed, the host is
allowed access to TMS34010 memory. At this time, the TMS34010 begins to automatically perform
DRAM refresh cycles at regular intervals. The TMS34010 remains halted until the host clears the
HLT bit. Only then does the GSP fetch the level-O vector address from location OFFFFFFEOh and begin
executing its reset service routine.
2. Self-Bootstrap Mode
If HCS is low at the end of reset, the TMS34010 first performs the eight RAS-only refresh cycles
required to initialize the DRAMs. Immediately following the eight RAS-only cycles, the TMS34010
fetches the level-O vector address from location OFFFFFFEOh, and begins executing its reset service
routine.
Unlike other interrupts and software traps, reset does not save previous ST or PC values. This is because
the value of the stack pointer just before a reset is generally not valid, and saving its value on the stack
is unnecessary. A TRAP 0 instruction, which uses the same vector address as reset, similarly does not
save the ST or PC values.
asserting reset
A reset is initiated by asserting the RESET input pin at its active-low level. To reset the TMS3401 0 at power
up, RESET must remain active low for a minimum of 40 local clock periods after power levels have become
stable. At times other than power up, the TMS3401 0 is also reset by holding RESET low for a minimum
of 40 clock periods. The 40-clock interval is required to bring TMS34010 internal circuitry to a known
initial state. While RESET remains asserted, the output and bidirectional signals are driven to a known state.
The TMS34010 drives its RAS signal inactive high as long as RESET remains low. The specifications for
certain DRAM and VRAM devices, including the TMS4161, TMS4164 and TMS4464 devices, require that
the RAS signal be driven inactive-high for 100 microseconds during system reset. Holding RESET low for 150
microseconds will cause the RAS signal to remain high for the 100 microseconds required to bring the
memory devices to their initial states. DRAMs such as the TMS4256 specify an initial RAS high time of
200 microseconds, requiring that RESET be held low for 250 microseconds. In general, holding RESET
low for t microseconds ensures that RAS remains high initially for t- 50 microseconds.

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

A-19

TMS34010
GRAPHICS SYSTEM PROCESSOR

suspension of DRAM-refresh cycles during reset
An active-low level at the RESET pin is considered to be a power-up condition, and DRAM refresh is not
performed until RESET goes inactive high. Consequently, the previous contents of the local memory may
not be valid after a reset.
initial state following reset
While the RESET pin is asserted low, the TMS3401 O's output and bidirectional pins are forced to the states
listed below.

INITIAL STATE OF PINS FOLLOWING A RESET
OUTPUTS DRIVEN

OUTPUTS DRIVEN

BIDIRECTIONAL

TO HIGH LEVEL

TO LOW LEVEL

PINS DRIVEN TO

DDOUT

BLANK

HIGH IMPEDANCE
HRDY

HSYNC
VSYNC

DEN

HDO-HD15

LA[

LADO-LAD15

'fR/QE
RAS
CAS

W
HINT
HLDA/EMUA

Immediately following reset, all I/O registers are cleared (set to Oh), with the possible exception of the
HLT bit in the HSTCTL register. The HLT bit is set to 1 if HCS is high just prior to the low-to-high
transition of RESET.
Just prior to execution of the first instruction in the reset routine, the TMS3401 O's internal registers are
in the following state:
• General-purpose register files A and Bare uninitialized.
• The ST is set to 00000010h .
• The PC contains the 32-bit vector fetched from memory address OFFFFFFEOh.

TMS34010 local memory interface
The TMS34010 local memory interface consists of a triple-multiplexed address/data bus on which row
addresses, column addresses, and data are transmitted. The associated memory control signals support
direct interfacing to both DRAMs and VRAMs. At the beginning of a typical memory cycle, the address
is output in multiplexed fashion as a row address followed by a column address. The remainder of the
cycle is used to transfer data between the TMS34010 and memory.

A-20

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TeXAS 77001

TMS34D1D
GRAPHICS SYSTEM PROCESSOR

TMS34010 local memory interface
The TMS3401 0 local memory interface consists of a triple-multiplexed address/data bus on which row
addresses, column addresses, and data are transmitted. The associated memory control signals support
direct interfacing to both DRAMs and VRAMs. At the beginning of a typical memory cycle, the address
is output in multiplexed fashion as a row address followed by a column address. The remainder of the
cycle is used to transfer data between the TMS34010 and memory.

TMS34010

ROW
ADDRESS

Ri'
26
25
24
23
22
21

-20-19
18
17
16
15

BIT 31
(MSB)

Ri'

lAO

BIT 0
(LSB)

COLUMN
ADDRESS
lAO

fR
29
28
27
14
13

DATA
15
1
1
12
11
1
9
8
7
6
5
4
3
2

BIT 15
(MSB)

BIT 0
(LSB)

DRAM-REFRESH BUS STATUS BIT
INSTRUCTION ACOUISITION BUS STATUS BIT
VRAM SHIFT-REGISTER-TRANSFER BUS STATUS BIT

FIGURE 7. TRIPLE MULTIPLEXING OF ADDRESSES AND DATA

The following types of memory cycles are supported: read, write, VRAM memory-to-shift-register, VRAM
shift-register-to-memory, RAS-only DRAM refresh and CAS-before-RAS DRAM refresh. The functional
timing for these cycles is shown in the next six figures. Each memory cycle is a minimum of two machine
states (a state is one local clock period) in duration. The seventh figure indicates the timing signals output
during an internal cycle, i.e., a cycle during which no memory access takes place. An internal cycle is
one state in duration.
During a memory cycle, the row address, column address, and data are transmitted over the same physical
bus lines. The manner in which logical addresses are output at the memory interface makes external
multiplexing hardware unnecessary, while supporting a wide variety of memory configurations. For example,
in Figure 7, 16 consecutive address bits (5 through 20) are output on LAD1-LAD8 during the row and
column address times. Output along with the address are bus status signals that indicate when DRAM
refresh cycles, screen refresh IVRAM memory-to-shift-register) cycles, and instruction fetch cycles are
occurring.

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

A-21

TMS34010
GRAPHICS SYSTEM PROCESSOR

The following remarks apply to memory timing in general. A row address is output on LADO-LAD15 at
the start of the cycle, and is valid before and after the fall of RAS. Next a column address is output on
LA DO-LAD 1 5. The column address is valid briefly before and after the falling edge of LAL, but is not valid
at the falling edge of CAS. The column address is clocked into an external transparent latch
(e.g., a 74AS373 octal latch) on the falling edge of LAL to provide the hold time on the column
address required for dynamic RAMs and video RAMs. A transparent latch is required in order that the row
address be avaiiabie at the outputs of the iatc.;h duriny ilre star"t of the cycle.
Very large memory configurations may require external buffering of data lines. The DEN signal serves as
the drive-enable signal to external bidirectional buffers, e.g., 74AS245 octal buffers. The DDOUT signal
serves as the direction control for the buffers.
When an I/O register is addressed by the TMS3401 0, a special memory read or write cycle is performed.
During this cycle, the external RAS signal falls, but the external CAS remains inactive-high for the duration
of the cycle.
The timing shown in the first six functional timing diagrams assumes that the LRDY input remains high
during the cycle. The LRDY pin is pulled low by slower memories requiring a longer cycle time. The
TMS34010 samples the LRDY input at the end of Q1, as indicated in the figures. If LRDY is low, the
TMS34010 inserts an additional state, called a "wait" state, into the cycle. Wait states continue to be
inserted until LRDY is sampled at a high level. The cycle then completes in the manner indicated in the
functional timing diagrams. A wait state is one local clock period in duration. Three additional timing diagrams
provide examples of cycles extended by wait states.
The LRDY input is ignored by the TMS3401 0 during internal cycles.
A hold/hold acknowledge capability is also built into the local memory interface to allow external devices
to request control of the bus. After acknowledging a hold request, the TMS3401 0 releases the bus by
driving its address/data bus and control outputs into high impedance.

A-22

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

TMS34010
GRAPHICS SYSTEM PROCESSOR

write cycle timing

DDOUT

!
I

r
I

I
I

I I I
I

I
I

I!
I

I
I

~,~!~

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

A-23

TMS34010
GRAPHICS SYSTEM PROCESSOR

read cycle timing

I
I
I

LCLK1

I
i

I
'VI

I
I

. "'--::~----!.I\
I
!\

i i i
I
I'
I
I
LCLK2

I
I

I I

i i i

I
I

'''-i-I
-I
,I

'I'

',I,'

_1~_---t'VI
I

~"u,,' i ~!~?$>

I
I

I
' I

,
,

I
I

I '
I
I

"
I ,

TAllIE,

I '

lI,\.

V
I
,
,

CAS:

W :

DEN

i,
,

DDOUT

.
,

I
I'
'I. I
I'
I
'I'
,
,

I
I
I
I
I
,
"
I,
,
I ,
"
I
I
' I

'I\.'

I I : 1\ ! :
! !
I!
(HIGH)

V
I

I,
I

I
,

i
I'

l\ I

,
,

t,II
'I
'I'

I
I'
I
'
I II
I
I
I
I

I
I
I
I

Ie
,

,,
,
,
I
,
I,
,
I

I
I
I,
I
I
I
I

LAL ,

i
I'

I
'I
I
,
I'
'I
I
'I'

I
I
lV'

i ~i

I
,
I
I
I
I
I

,
,

I
I

I '-+-1--!,f--~r
I',
I

I\.

I
I

RAS

I
,

)

" ,

I ,I , ", I
,

I ,

1\1

'v'

,
' I ,

'I
'I
I

I
I
..
i i '

!\.,

I
,

i
,

I'
I"
I
,

, I .'V-II
"
I
I

'III'I~

LRDY~

A-24

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

TMS34010
GRAPHICS SYSTEM PROCESSOR

memory-to-register cycle timing

i
lClKl

lClK2

,Q3

' I

Q4'

V :"
.;oV,.--I!f----i.i\ I

,',

'I
,
,i

'
,I,
,
,

~oo~'" ! X ~w ~
V

lAl'l

,
,

TR/QE

II
I
I
I

~
,r

:
I

:
,

I
'
I'

"
I,
,'
I

, I'
I
I
'"
,,~,
I,
I
,

'VI

i\ I:

I,
"

,',

. I i"
,
',
'I
'
I'
'V'

I
I,

'
I
I
'

I
I
I
I

'.V

'V,

IV
I

, )

V,
I

"""~"'~: ~

II
I
I
I
,
I,
i
I i i
I
I'
I
,
,I
, ' "
I

! f\ :

'"
I ''
I

I
I,

I'
II
I
I
,
:
I
I
II
I
I
I
I

,''----+-----i--+---i---~'------4

.
I
II
I
I
~--+,--+,--+,-----;,-----4----~

I
,
I
,
II IHIGH),"

,
DDOUT

CAS:

I
,
II
iN I
I
,
I

IV"--i---~~,!
I
" I,'
,

RAS ,

Q2'

1 - 1_ _

I, I

',I',

I '

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

II
I

A-25

TMS34010
GRAPHICS SYSTEM PROCESSOR

DDOUT

i
I
I

I I I

I
I

LRDY~~

A-26

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TeXAS 77001

TMS34010
GRAPHICS SYSTEM PROCESSOR

RAS"-only DRAM refresh cycle timing

i I i i !
iVr--+!---I.~ !--1--Vr---I-I--"';'1\
I

LCLK1

I
I
I

LCLK2

LADO-LAD15

I '---4-1
I
I
I
I
,--+-I----1."
I--........f'
I
!\
I

I
I
I
IV
I
-

1
I
I
I
I

I
I

I
I
LALV

I
I
!

I
I
I

I
I

I '---+I--tI-+----+---~I~-----l'1
I
I
I
I
I

I
I

!!
! f\

I
I
I

I\
I
I I I

I
I

I
I
I
I
I

+,. ,;::

I
I

Vi!

I I...f-l----i,l----I'l

~'-----r~O---lW~::

RAS!

t - - - - - - - - t :

I
I

I
I
I
Ii ; -

If
I

I
I

VI! !
I
V !
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i-----;,--IHIGH)-l--+I--;---+-----;----i'I---;-1-t--i-I- - - + , - CAS
I
i
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i-----;,--IHIGHI--+,-+--+--"""T---;,---,r-+-i-I
w
I
i
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i---II--IHU;JHI--+I--i--+----i----iII---;--+--i-I---+!-TR/OE
I
I
I
I
I
I
I
I
I
I
I
I

---+,--

DEN

!
I

I
I

! !

V
i

I
DDOUT

IJ
V

I
i _ I
I

I
I

LRDY~_

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

A-27

TMS34010
GRAPHICS SYSTEM PROCESSOR

CAS-before-RAS refresh cycle timing
I

LCLK1

LCLK2

I
I

r---~--~~

1\
I
I
I
I

LADO.LAD15!! - - - - - (

i
I

I
1
I

LAL

I
I
I r---~--~

I
I

. I
I

'Ow: :

I
I

II
1

l II
1\

II
1

1
1
1

I
1

.
I
I

I
I
I

I~ i

I
I

I
1
1
1

II '-+-1I --I-----r
I
I
I
I

: ""~.~ :
I

IVI
.

II
1

1
I

r--~I-----

V
~!----~~'-___+!----~--+-~----~~----~----~~~ !

V
1
I

CAS

I
I
I

r---!~----;~I
i
i iV I
i
i
i
I
I
V
I-----r
I

RAS

1\
1
1
1

I
I

I
I
1
1
I

1
1
I
1
1
I
W 1-1----+---IHIGHI
1
1
I
1
1
1
1 1
1
I
I
1
1
I
I
1
1
I
I
I
TRtOE i-I-----+---IH GHI---!-+-+---+---+---+~I--iI-----I--1
I
1

DDOUT

!
1
1

I
1
1

I I

1
1

LRDY

A-28

TEXAS .."

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

I
1

TMS34010
GRAPHICS SYSTEM PROCESSOR

internal cycles back to back
I
I

LCLK1

V
I
I
I

LCLK2

I
I
I
I

LADO-LAD15

!
I
J

I
RAS I
I
I
I
LAL

V
J
J

I
I

CAS J

I
I

I
I
W I

I
I
I
I
I
I
I

V
J
J
J

DEN

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

I
I

DDOUT

i
I

II
J

I
(HIGH)

I
I
I
I
I
I
I
I
I
I

(HIGH)

I
I

I
I
I

f\1

I
I
I
I
I
I
I
I

I
I
I
I
I
I
I

J
J

I
I
I
I
I

J
J

I
I
I
I
I
I
I

I
04

V
I
I

UNDE~INED
I
I
I
I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I

I
I
I

I
I

: ;

I
I
I

i
I
I
I

I
I

I
I
I
I
I
I
I
I
I
I
I
I

I
I
I

J
J

f\1

I
I
I
I

I
I
I

J
J
J
J

I
I
I

I
I
I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I

VI
I

I
I
I
I
I
I
I
I
I
I
I
I

I
I

I
I
I
I
I

!
(HIGH)
i
I
I

I
I
I
I
I
I

I
I
I
I

I
J

I
I
I
I
I

I
I

(HIGH)

V
V

I
I
I
I
I

>< :

J
J
J

TR/QE

I
I
I
I

I
I

J
J
J

I
I

J
J
J

I
I

I
I
I
I
I
I

LRDY

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

A-29

TMS34010
GRAPHICS SYSTEM PROCESSOR

write cycle with one wait state

r-1

LCLK1

02/ 03

yr.-r--'r\
I

DDOUT!

II
I

I 01 I 02 I 03 I 04 I 01

I '--'-~
I
r-+I_~

I
I
I

LCLK2

1 04

r,
V
I
I

I
I
I

WA1T STATE----"1

'02

, 03

'--!-~

'--'-~

!! I I I ! I I! I
I
I
I

I
I
I

LRDy~~!~I~

A-30

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TeXAS 77001

TMS34D1D
GRAPHICS SYSTEM PROCESSOR

read cycle with one wait state
i W A I T STATE,

I
lClK1

I
I

lClK2

I
I
I
I
I
I
I
I

lADO-lAD7

RAS

lAl

TR/OE

DEN

DDOUT

lRDY

V
I
I

I
I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

II
I
I
I
I
I
I
I
I
I
I
I
I

I
I
I

1\
I
I

I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I

I
I
I

I
I

I
I
I
I
I

I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I

I
I
I
I
I

I
I
I

I
I
I
I
I
I
I

I
I
I
I

I
I

I
I
I

1\
I
I

I
I
I
I
I
I
I
I
I

I
I
I
I

I
I
I

I
I
I
I

I
I
I

I
I
I
I
I
I
I
I
I
I

I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I

I
I
I
I

I
I
I
I
I

I
I
I
I

I
I
I
I
I

I
I

I
I
I
I

f\
I
I

I
I
I
I

I
I

V
I
I

I
I

I
I
I
I
I

I
I
I
I
I
I

I
I
I
I
I
I
I
I

I
I
I
I
I
I

I
I
I

I
I
I
I
I
I

{HIGH)

I
I

I
I
I
I
I

I
I

I
I
I
I

:ROW

I
I

I
I
I
I
I
I
I
I
I
I

X ~

I
I

CAS

I
I
I
I
I

i~E
_g~1i~~_ i~!~~

TEXAS

-1!1

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

A-31

TMS34010
GRAPHICS SYSTEM PROCESSOR

LCLK1

LCLK2

--V
I

i\. i
i/
IW--V
I
I
I

I
I
I
I

I
I
I

II
I
I
I

LAL

CAS

I II
I
1\ I

I
I

III

I
I

I
I
I

I
I

III I III

II
I

I
I

I
I!\

I
I
I
I

I
I
I
I
I

TR/QE!
I
I
I

OOOUTI
I
I

I
I
I

I
I
I
I
I

I
I
I

I
I
I
I

I
II

i\.

I
I
I

I
I

I
I
I
I
I

I
I
I
I

I
I

I
I
I

_-:-_-,-_--:-:"_N_OE_F....
r_E_O--:-_-..._--:I,..-_*=

I
I
I

I
I

_-+-_!---+II
I __l~-+_-'----fl"
.
I

I
II

I
I

/'1l

I
I
I
.

II ~-+I-~--4--4I--4I~-~-~
I
I

I
I
I

II
I
I
I
I

,..-;1-I
I
I
I
II
I
I
I

I
I
I
I
I

I \.tl_-+-I
I
I
I
I
I
I
I
I

I
I
I

I
I

i\. i
i/
IW--V
I
I
I

~oou" i ~:-w ~~r;
RAS

I
I
I

I
I
I
I

I
I
I

I
I
I
I

I
I
I

I
I
I
I

I
I
I

I
I
I
I

I
I
I

I
I
I
I

LROY~HirH~_!~ ~
A-32

TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

TMS34010
GRAPHICS SYSTEM PROCESSOR
absolute maximum ratings over operating free-air temperature range t
Supply voltage, Vee ......................................................... 7 V
Input voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 20 V
Off-state output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 2 V to 7 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ooe to 70 0 e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 10 °e to 1 50 °e
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating

only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions"
section of this specification is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
Voltage values are with respect to the VSS pins of the chip.

recommended operating conditions
VCC

Supply voltage

VSS

Supply voltage t

10H

High-level output current

10L
TA

Low-level output current

MIN

NOM

MAX

UNIT

4.75

5.0

5.25

0
-400

p.A

2.0~

°c

Operating free-air temperature

z
o

t Care should be taken by card designers to provide a minimum inductance path between the V SS pins and system ground in order to
minimize VSS noise.
~Output current of 2.0 mA is sufficient to drive five low-power Schottky TTL loads or 10 advanced low-power Schottky TIL loads (worst case).

DC electrical characteristics
PARAMETER
High-level input

TEST CONDITIONS

All inputs
except INCLK

VIH§ voltage, TTL-level
signal

VIL

All inputs

voltage, TIL-level

except INCLK

MINt

TYpt

2.2

MAXt

3.0

VCC+0.3

-0.3

0.8

-0.3

0.8

VCC = min,

TTL-level signal

10H = max,

Low-level output voltage,

VCC = max,

10
II

ICC
CI

bidirectional pins
Input current

2.6

All inputs except

RUN/EMU§

Supply current

Vcc=max

VO=2.8 V

VO-0.6 V

-20

VI=VSS to VCC

±20

VCC - max, 40 MHz

125

VCC = max, 50 MHz

150

VCC = max, 60 MHz

175

Output capacitance (except
Co

0.6
20

Input capacitance

address/data lines)

~
)::Ii

---r===\,---

FIGURE 9. TTL-LEVEL INPUTS
Transition times for TTL-compatible inputs are specified as follows. For a high-to-Iow transition on an input
signal, the level at which the input is said to be "no longer high" is 2.2 volts, and the level at which the
input is said to be "low" is 0.8 volts. For a low-to-high transition on an input signal, the level at which
the input is said to be "no longer !ow" is 0.8 volts, and the level at which the input is said to be "high"
is 2.2 volts.

"T1

:::0

~
o

2.2 V

=:1-----\:.:=.0.8 V

test measurement
The test load circuit shown in Figure 1 0 represents the programmable load of the tester pin electronics,
which are used to verify timing parameters of TMS34010 output signals.

._...,
I
I
I
I

TESTER PIN
ELECTRONICS

VLOAD

I
I
I
I
I
._-1
Where:

IOL = 2.0 mA DC level verification (all outputs)
IOH = 400 p.A (all outputs)
VLOAD = 1.5 V DC level verification
0.7 V Timing verification
CT = 65 pF typical load circuit capacitance
FIGURE 10. TEST LOAD CIRCUIT

A-34

OUTPUT

>--1~-----r--O UNDER

TEXAS ."

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

TEST

TMS34010
GRAPHICS SYSTEM PROCESSOR

timing parameter symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten
the symbols, some of the pin names and other related terminology have been abbreviated as follows:
Al
C
CA
CK
CK1
CK2
CS
D
DD
EN
F
HK
HR

lAl
CAS
Column address
lClK 1 and lClK2
lClK1
lClK2
HCS
Data
DDOUT
DEN
HFSO, HFSl
HlDA/EMUA
HOLD

HS
ICK
lR
OE
R
RA
RS
RY
S
TR
VCK
W
WS

HSYNC or VSYNC
INClK
lRDY
TR/OE, when used as output enable
RAS
Row address
HREAD
HRDY
HREAD or HWRITE
TR/OE, when used as shift register enable
VClK

Vii
HWRITE

lowercase subscripts and their meaning are:
a
c
d
h
su
w

access time
cycle time (period)
delay time
hold time
setup time
transition time
pulse duration (width)

The following additional letters and symbols and their meaning are:
H
l
V
Z

i
~

High
low
Valid
High impedance
No longer low
No longer high

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

A-35

ADVANCE
INFORMATION

TMS34010
GRAPHICS SYSTEM PROCESSOR

host interface timing parameters
The timing parameters for host interface signals are shown in the next four figures. The purpose of these
figures and the accompanying table is to quantify the timing relationships among the various signals. The
explanation of the logical relationships among signals will be found in the TMS34010 User's Guide (number

SPVU001A).
The wriie :;iaue reierfed to in the following tab;e is the enabling signa: dUiing a vV'i:ta to one of the host
interface registers (see comment 2 on the next page). Similarly. the read strobe is the enabling signal during
a read.
Quarter clock time tQ. which appears in the following table. is one quarter of a local output clock period.
or twice the input clock period. tc(lCK).

NO.

TMS3401 0-40

PARAMETER

MIN

:I:-

):II,

Setup time of HWRITE/HREAD high or HFSO.

tsu(FV-Sll

td(WSl-DVI

tdlSl-Sll

HFS 1 valid to read or write strobel
Delay from write strobe l to data in valid. write cycle
Delay from read or write strobe low to next

tWISll

read or write strobel

tdiSH-Sll

thIWSH-DVI Hold time of data in valid after write strobe high, write cycle

o":::a
s:
~
o

8
9
10

10,

O§

read cycle with no wait

Hold time of data out valid after read strobet. read cycle

Delay from read strobe high to data out high impedance,

thICSl-RYHI Hold time of HRDY high after HCSl, cycle with wait

tdlCSl-RYll

Delay from HCS low to HRDY low. cycle with wait

tw(RYll

Pulse duration of HRDY low. cycle with wait

tdIRYl-RYHI Delay from HRDY l to HRDY high. cycle with wait
Hold time of write strobe low after HRDYt,
thIRYH-WSll write cycle with wait

read cycle

td(RSH-DZI

tdIRYH-DVI

30§

ns
40

ns
ns

Delay from HRDYt to data out valid. read cycle with wait

ns
ns

read cycle with wait

90
0

30§

read cycle

Hold time of read strobe low after HRDYt,
th(RYH-RSll

HFS1 valid after read or write strobe high

2tO

read or write strobe!

Delay from read strobe low to data out valid,
th(RSH-DVI

Hold time of data high impedance after read strobel,

tdIRSl-DVI

UNIT

MAX

7tO+l0

Hold time of HWRITE/HREAD high or HFSO.

thIRSl-DZI

MIN

2tO

Delay from read or write strobe high to next

thISH-FVI

TMS3401 0-60

7tO+l0

Duration of read or write strobe low

(')

MAX

TMS3401 0-50

ns
ns

NOTE: Advance information notices apply only to the TMS34010-60.
t Parameter 14 is a function of local bus memory contention. This parameter is not tested. Refer to the TMS34010 User's Guide for details.
t:parameter 15 is specified as minimum 0 ns to indicate that a low-going pulse on HRDY can be arbitrarily narrow.
§These values are derived from characterization and are not tested.

A-36

TEXAS

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

TMS34D1D
GRAPHICS SYSTEM PROCESSOR

general comments on host interface timing
The following general comments apply to host interface timing:
1. The HRDY signal is enabled by an active-low level on the HCS input. When HCS is inactive-high,
HRDY is forced high regardless of the internal state of the device. Low-going transient pulses on
HCS may result in low-going transient pulses on HRDY, but otherwise have no effect unless
accompanied by active levels on other control signals.
2. A host interface write cycle occurs when HCS, HWRITE, and HLDS are low, or when HCS,
HWRITE, and HUDS are low. The combination of these signals defines a write strobe. In either case,
the last of the three signals to make the high-to-Iow transition is the strobe (write strobe) that begins
the cycle. The first of the three signals to make the low-to-high transition ends the cycle. Similarly,
a host interface read cycle occurs when HCS, HREAD, and HLDS are low, or when HCS, HREAD,
and HUDS are low. The combination at these signals define a read strobe. In either case, the last
of the three signals to make the high-to-Iow transition is the strobe (read strobe) that begins the
cycle. The first of the three signals to make the low-to-high transition ends the cycle. All access
times are specified with respect to the strobing edges that begin and end the cycle.
3. During a host interface read or write, HWRITE and HREAD must not be active-low simultaneously.
4. Host interface input signals HCS, HUDS, HLDS, HFSO, HFS1, HREAD, and HWRITE are assumed
to be asynchronous with respect to the output clocks LCLK1 and LCLK2.

host interface timing: write cycle with no wait

HFSO, HFS1

W<
1-1 -'I

HREAD

14--7

---i

I~7~

=07~1~I

fr'

I I..

_ _ _ _ _ _1
HCS, HWRITE,
HLDS,HUDS

VALID FUNCTION SELECT

i~
I~

-J\.l

'-_ __

)

-5---.l'
~
~~~._ ___

'---4
. I
I-- 2- 'I - - ; \--6--'
I

HDO.HD15

VALID DATA IN

HRDY

TEXAS .."
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

A-37

TMS34010
GRAPHICS SYSTEM PROCESSOR

host interface timing: read cycle with no wait

HFSO. HFS1

VALID FUNCTION SELECT

1r--

HWRITE

1
1.-7

1
14"1--1 I..

HCS. HREAD.
HLDS. HUDS

HDO-HD15 --HI-Z

r--

---1\.'----..I
I

5 -----i \."'___
14" 11-1
j,...1 O...-!+-

1 \.
1 L..---- 4
1 1--;-9

7----..(

31
I'1

-----01.~11!

~
I

---i

to-- 8 " t VALID DATA OUT

~,.--------

HRDY

host interface timing: write cycle with wait

HFSO.HFS1

~_ _ _ _ _ _ _ _ _V_A_LI_D_F_U_N_C_TI_O_N_S_E_LE_C_T_ _ _ _ _ _~~
~1

!- 7--1I

-r

~I
!
~ I--t-

J\'----

t- 7 --l

I 1~"~----------3-------~1---~"~1
I 1
1

HWRITE.
HLDS.HUDS

------1{11~1"~---------4----------~~{t1
~

I
I

HCS

_ _ _ _ _ _ _ _ _ _ _ _ _ _~ I

~1"~---------3-----------+1--------~..~:

~13

I
I

X
I I
I..

""-2":";

HDO-HD15

A-38

l\-

1 t-- 5-----t
......._ - - 1 6 -------..ojI I

12~ '--14------1
HRDY

_!~

~5--t

---~}J:"'-------4------"'11
I

Jlf

1
"I

I
I
I

~I 6

~~------V-A-L-ID-D-A-T-A-I-N-----~~

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

TMS34010
GRAPHICS SYSTEM PROCESSOR

host interface timing: read cycle with wait
HFSO. HFS1

HWRITE

~:..-_ _ _ _ _ _ _V_A_L_ID_F_U_N_C_TI_O_N_S_E_LE_C_T_ _ _ _ _ _ _ _..2~

I1-.J1
1
.If 11
---./ ~1-l
1 I"
1 I..

HREAD.

HCS

----..,;tl~
l

HLDS. HUDS

-----,jN

r~:

I--s -----,

"'1

,l,f

r - - 1S --f

:5---1

11
IAr------+I~I-----------

14-----1

-----------1_
1

.11

--r---'
I"
1
~~
1

HDO-HD15

1:r--- ---i~'----

11---+-13

HRDY

...:

II..
1 I'"

I.-7--l1
1
l'\'---l.-7--l
I1
-I
!
1
1

+:
rl

J-17-l

TEXAS .."
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

1 ~11

10-k--"'n

DA~~L~UT

]J.------

A-39

TMS34010
GRAPHICS SYSTEM PROCESSOR

ADVANCE
INFORMATION

reset timing
The timing parameters for device reset are shown in the next two figures. The purpose of these figures
is to quantify the timing relationships among the RESET, HCS, and LCLK1 signals. RESET and HCS are
asynchronous inputs that are internally synchronized by latches internal to the TMS34010. The timing
relationships specified for these signals relative to LCLK 1 need be met only to guarantee recognition of
a transition of one of these signals at a particular clock edge. The explanation of the logical relationships
dr.-iong signa;s wi;; be found in the ilviS340iO U:if1r':; Guiut:J.
Quarter clock time tQ which appears in the following table, is one quarter of a local output clock period,
or twice the input clock period, tc(lCK).
NO.

MIN

»
~
»
:2

:2
."

:::D

~
o

Duration of HCS low to configure GSP to run

twICSL)

tsuICSL-REH)

in self-bootstrap mode
Setup time of HCS low to RESETt to configure
the GSP to run in self-bootstrap mode
Duration of RESET low to ensure that GSP

twIREL)

is properly reset

tdICSH-REH)

tsuIREV-CK 1 L)

thlCKl L-REV)

25
26

thlCKl L-CSV)

TMS34010·60

MAX

MIN

UNIT

MAX

4tO+55

8tO+55

160tO-40

16OtO-40

Delay from HCSt to RESET high, end of reset,

TMS3401 0·50

TMS3401 0·40

PARAMETER

4tO-50t

to configure GSP to run in self-bootstrap mode
Setup time of RESET valid to LCLK H to

4tO-50t

40t

40*

10*

Setup time of HCS valid to LCLK H to
tsuICSV-CKl L) guarantee recognition at a particular clock edge

40*

Hold time of HCS valid after LCLK 1 low to
guarantee recognition at a particular clock edge

10*

guarantee recognition at a particular clock edge
Hold time of RESET valid after LCLK 1 low to
guarantee recognition at a particular clock edge

NOTE: Advance information notices apply only to the TMS3401 0-60.
tparameter 22 is the maximum amount by which the RESET low-ta-high transition can be delayed after the HCS low-ta-high transition
and still guarantee that the GSP is configured to run in self-bootstrap mode IHLT bit = 0) following the end of reset. HCS may be held
low for some time past the low-to-high RESET transition, and will be ignored by the GSP for 17 local clock periods following the clock
edge at which the low-to-high RESET transition is detected. Following completion of the eight RAS-only cycles that automatically follow
reset, however, a low HCS level will be interpreted as a chip select.
*RESET and HCS are asynchronous inputs. The specified setup and hold times of these signals with respect to the high-to-Iow transition
of LCLK 1 need be met only to guarantee that a transition of RESET or HCS is detected by the device at a particular clock edge.

reset: asynchronous timing relationships

!-- 19----1

\t.

I----- 22 -----t

1-1------

...
i o----------

A-40

20 - - - - - a j
~~ _______________________~j(

,.",.."., ----...
RE~ET

I
I
I

---------!!

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

TMS34010
GRAPHICS SYSTEM PROCESSOR

ADVANCE
INFORMATION

reset: synchronous timing relationships

i\__-----'r

LCLK1J

23;------t
I
I

-JX

RESETt _ _ _ _

!-----+- 24

X,..----l-----!-X,..----

V;UD

25-T-----1

-JX

HCSt _ _ _ _

VALID

tRESET and HCS are asynchronous inputs. The specified setup and hold times of RESET or HCS with respect to the high-ta-Iow LCLK 1
transition must be met only to guarantee that a RESET or HCS transition is detected by the device at a particular clock edge.

o
~

local bus timing parameters
The following six figures show the timing parameters for the signals of the local memory interface bus,
often simply referred to as the local bus. The purpose of these figures and the accompanying tables is
to quantify the timing relationships among the various signals. The explanation of the logical relationships
among signals will be found in the TMS34010 User's Guide (number SPVU001).

a:::

oLL

A number of parameter values are expressed in terms of quarter clock time ta, which is one quarter of
a local clock period, or twice the input clock period, tc(lCK).
Input clock INCLK is divided internally by 8 to produce output clocks LCLK 1 and LCLK2. Transitions of
the other local interface output signals are also generated as delays from INCLK transitions. The dividedown logic that converts INCLK to the internal clocks used to generate LCLK 1 and LCLK2 introduces
significant propagation delays from the transitions of INCLK to the corresponding transitions of LCLK 1
and LCLK2. While the frequency of INCLK is precisely eight times the frequency of LCLK 1 or LCLK2, no
timing relationship other than the frequency is specified between transitions of input clock INCLK and
transitions of the output clocks LCLKl and LCLK2.
NO.

TMS340 10-40

PARAMETER

TMS34010-50

TMS3401 0-60

MIN

MAX

MIN

MAX

MIN

MAX

tc(lCK)

Period of INCLK

62.5

16.5

62.5

twIlCKH)

Pulse duration of INCLK high

6.5*

tw(lCKL)

Pulse duration of INCLK low

6.5*

tt(lCK)

Transition time Irise and fall) of INCLK

(.)

TMS3401 0-40

Hold time of CAS high
after LAL low
Hold time of RAS high

Delay time from

RAS

low

tdIRL-CL)

to~low

thICH-WH)

CAS high, shift register
transfer follows read

thIRL-CL)

twlCH)

2ta+2O

2ta+ 10

2ta+1O

Hold time of W high after

Hold time of

CAS low

after RAS low
Pulse duration,

CAS high

Hold time of LAL low after

thIWH-ALL)

tsuIWH-CL)

Vii

high, write cycle

Setup time of W high to
end of write

CAS~,

1.5ta- 15

1.5ta- 1O

5. 5ta- 25

5. 5ta- 1O

4. 5ta- 15

4. 5ta- 1O

0. 5ta- 15

0. 5ta- 1O

0.5ta- 1O

4. 5ta- 15

4. 5ta- 1O

4.5ta- 1O

NOTE: Advance information notices apply only to the TMS34010-60.
tThis is a functional minimum and is not tested.

A-44

TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

TMS34010
GRAPHICS SYSTEM PROCESSOR

local bus timing: the RAS. CAS. and LAL outputs

- -----f
N

o'"

~ 1- ~----r--,___ t

...

----------]- ;:

.....

i'" 1----:g --T
__ ______ __ 1 f ,-- --- 1- M
'"

-- ----- - -, ~

o
.....

oa::

0'"
<0
o~

-'<
-'

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

13:

A-45

TMS34010
GRAPHICS SYSTEM PROCESSOR

ADVANCE
INFORMATION

local bus timing parameters (continued)
Quarter clock time tQ. which appears in the following table. is one quarter of a local output clock period.
or 2tc(lCK).

NO.

MiN
74
75

Setup time of W low to RAS.!.. shift register
tsuIWL-RL)
thIRL-WL)

Setup time of
tsuITRL-RL)

thIRL-TRL)

thICL-TRL)

»2

tsuITRH-RH)

tsuITRH-CH)

(")

Tfi/OE low to RAS.!.,

to-20

to-10

to-20

to-lO

4tO-20

4tO-10

2tO-20

2tO-10

to-20

to-10

1.5tO-25

1. 5tO-10

shift

register transfer cycle
Hold time of TR/OE low after RAS low, shift
register transfer cycle
Hold time of TRIOE low after CAS low, shift
register transfer cycle
Setup time of TR/OE high to RASt, shift
register transfer cycle
Setup time of TR/'IlE high to CASt, shift
register transfer cycle

UNIT

MAX

to-lO

shift

W low after RAS low.

TMS3401 0-60

Mit..

iviAX

to-20

transfer cycle
Hold time of

TMS34010-50

TMS3401 0-40

PARAMETER

NOTES: 1. Advance information notices apply only to the TMS34010-60.
2. Parameters 81 and 82 intentionally omitted.

." I local bus timing parameters: shift register transfer cycle

:::D

s:l>.

::!

01
LADO- ________
LAD15

~)(~____R_O_W_____~______________________________~)(

ROW

o
2

~~------------~j

I.I I
I I

II
d
I I

\'------+--~/

I I
I I
I I

I.
I

I t..
..II
I I

_I
I
I

I I _~yl,
'i1l:.1 ---IIH-I
II

\1
I
I

1
I

I
I

_I!

I
I

' - - 7 8 - - - 1 1"---80----.1

_ ______~76~-t~.-~..~1 ~1..
.-----------77

A-46

I.
I

-I I

y~--------~\~----

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

\~-

HOUSTON. TEXAS 77001

ADVANCE
INFORMATION

TMS34010
GRAPHICS SYSTEM PROCESSOR

local bus timing parameters (continuedl
Quarter clock time tQ, which appears in the following table, is one quarter of a local output clock period,
or 2tc(lCK).
NO.

TMS3401 0-40

PARAMETER

MIN
83
84
85
86

Access time from
ta(RL-DVI

MAX

liAS low to data

TMS3401 0-50
TMS3401 0-60
MAX
MIN

5. 5tO-40 1

in valid, read cycle

5. 5tO-25 1

UNIT

tsu(CH-ALHI

Setup time of ~ high to LAL t

0. 5tO-15

0. 5tO-l0

tsuIENH-ALHI

Setup time of DEN high to LAL t

0.5tO-15

0.5tO-l0

Access time from CAS low to data
ta(CL-DVI

th(CH-DVI

th(CH-RAZI

thICL-OELI

tsuICAZ-OELI

3. 5tO-25 1

3. 5tO-40 1

in valid. read cycle

Hold time of data in valid after ~t,
read cycle
Hold time of row address high impedance after
CAS high, end of read cycle
Hold time of TR/OE low after ~ low,
read cycle
Setup time of column address high impedance

to TR/OE., read cycle

1.5tO -10*

1.5tO-l0*

3. 5tO-25

3.5tO-l0

to-l0*

to-IO*

thIOEH-DVI

Hold time of data in valid after TR/OEt,
read cycle

td(CL-OELI

Delay time from CAS. to TR/QE low,
read cycle

to+20

to+l0

ta(OEL-DVI

Access time from 'i'ii/QE low to data
in valid, read cycle

2. 5tO-40 1

2. 5tO-25 1

th(OEH-RAZI

Hold time of row address high impedance
after TR/OE high, end of read cycle

tw(OELI

Pulse duration, 'i'ii/OE low, read cycle

td(CL-ENLI

thIENH-DVI

lsuICAZ-ENLI

thIENH-RAZI

100

ta(ENL-DVI

101

th(ENH-DDHI

102

tsu(DDL-ENLI

DEN low,

1.5tO-l0*

1.5tO-IO*

2. 5tO-25

2. 5tO-l0

to+20

read cycle

Hold time of data in valid after DEN I ,
read cycle
Setup time of column address high impedance
to DEN I, read cycle
Hold time of next row address high impedance
after DEN high, end of read cycle
Access time from
read cycle

DEN low to

ti~

oLL
Z

Delay time from ~ low
to

z
o

read follows write cycle
Setup time of DDOUT low to DEN I,
read cycle

to-l0*

1.5tO-l0*

1. 5tO-l0*

data in valid,

Hold time of DDOUT high after DEN high,

to+l0

2. 5tO-25 1

2.5tO -40 1

W
(.)

I{~-~,~,~------------~,
II
.J.

,153-------,

1----

~-_l'I__--------"'+'
,
'
,

150 -!----i
, L.--149-----l

,
,
LAL

148~

U_N_OE_F_IN_ED
______

1--144----.1

iiAS

l<'--_____

ROW

.ti"~---

""141------158 - - - - - I..
-il

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

A-55

TMS34010
GRAPHICS SYSTEM PROCESSOR

ADVANCE
INFORMATION

local bus timing parameters (continued)
Quarter clock time tQ, which appears in the following table, is one quarter of a local output clock cycle,
or 2tc(lCK).
NO.

TMS34010·50

TMS34010-40

PARAMETER

MIN

MAX

TMS34010-60

MIN

UNIT

MAX

Hold time of RAS high after LCLK2 high, all
159

th(CK2H-RH)

cycles except internal and

ta- 15

ta-lO

ta- 2O

ta- 1O

ta- 15

ta- 1O

ta- 2O

ta-lO

ta- 15

ta-lO

ta- 2O

ta-lO

0. 5ta- 15

0. 5ta- 1O

0. 5ta- 15

0. 5ta- 1O

ta- 15

ta-lO

ta- 2O

ta- 1O

ta- 15

ta- 1O

ta- 2O

ta- 1O

ta- 15

ta-lO

ta- 2O

ta- 1O

0. 5ta- 15

0. 5ta- 1O

CAS-before-RAS refresh

»
~

Setup time of RAS low to LCLK2., all cycles

160

t su(RL-CK2L)

161

th(CKI L-RH)

162

tsu(RL-CK 1H)

163

thiCK 1L-RL)

164

Hold time of RAS high after LCLK 1 low,

tsu(RH-CK 1H)
th(CK2L-ALH)

(")

166

tsu(ALL-CK 1 H)

167

th(CK2L-ALL)

168

t su(ALH-CK2H)

169

thiCK 1H-CH)

~
o

170

all cycles except internal
Setup time of RAS high to LCLK 11,

165

CAS-before-RAS refresh
Hold time of RAS low after LCLKI low,

»
"T1

CAS-before-RAS refresh
Setup time of RAS low to LCLK 1i,

all cycles except internal

Hold time of LAL high after LCLK2 low,

m
2

except internal and CAS-before-RAS refresh

all cycles except internal
Setup time of LAL low to LCLK11,
all cycles except internal
Hold time of LAL low after LCLK2 low,
all cycles except internal
Setup time of LAL high after LCLK2i,
all cycles except internal
Hold time of CAS high after LCLK 1 high,
CAS-before-RAS refresh
Setup time of CAS low to LCLK.,

tsu(CL-CK 1LI

CAS-before-RAS refresh
Hold time of CAS high after LCLK2 low,

171

th(CK2L-CH)

cycles except internal,
DRAM refresh and CAS-before-RAS refresh
Setup time of CAS low to LCLK2i,

172

t su(CL-CK2H)

all cycles except internal, DRAM refresh,
and CAS-before-RAS refresh

173

Hold time of CAS low after LCLK2 low, all
th(CK2L-CL)

cycles except internal and DRAM refresh
Setup time of CAS high to LCLK 11, all

174

tsu(CH-CK 1H)

0. 5ta- 15

0. 5ta- 1O

175

Hold time of W high after LCLK 1 high,
thiCK 1 H-WH)TR shift register transfer

ta- 15

ta- 1O

176

Setup time of W low to LCLKH,
tsu(WL-CK 1 L)TR shift register transfer

ta- 2O

ta- lO

cycles except internal and DRAM refresh

NOTE: Advance inforrl'ation notices apply only to the TMS3401 0-60.

A-56

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

ADVANCE
INFORMATION

GRAPHICS SYSTEM PROCESSOR
TMS34010

local bus timing parameters (concluded)
Quarter clock time tQ. which appears in the following table. is one quarter of a local output clock cycle.
or 2tc(lCK).
NO.

TMS34010-40

PARAMETER

MIN
Hold time of W low after LCLK 1 low.

177

thiCK 1 L-WLI

178

tsuIWH-CK I HI

shift register transfer

Setup time of W high to LCLK 1t,

MAX

TMS34010-50
TMS34010-60
MIN

UNIT

MAX

to-15

to-1O

to-20

to-1O

thICK1H-WHI

Hold time of W high after LCLK 1 high, write

to-15

to-1O

tsuIWL-CK1LI

Setup time of W low to LCLKU, write

to-20

to-l0

1!!1

thICK2L-WL)

Hold time of W low after LCLK2 low, write

0. 5tO-15

0. 5tO-l0

182

tsulWH-CKl H)

Setup time of W high to LCLK 1i, write

0. 5tO-15

0. 5tO-l0

to-15

to-l0

to-20

to-l0

to-15

to-1O

to-20

to-1O

179
180

shift register transfer

Hold time of TR/OE high after LCLK 1 high,

183

thiCK 1 L-TRH)

184

tsuITRL-CKl H)

185

thICK2H-TRL)

shift register transfer

Setup time of TR/OE low to LCLKU.
shift register transfer

Hold time of TR/OE low after LCLK2 high.
shift register transfer

Setup time of TR/OE high to LCLK2.,

o!;:
~

a::

186

tsuITRH-CK2L)

187

thlCKl H-OEH)

Hold time of TR/OE high after LCLK 1 high, read

to-15

to-1O

188

tsu IOEL-CKl L)

Setup time of TR/QE low to LCLK H, read

to-20

to-1O

189

thICK2L-OEL)

Hold time of TR/OE low after LCLK2 low. read

0. 5tO-15

0. 5tO-l0

190

tsuIOEH-CK 1 H) Setup time of TR/OE high to LCLK 1t, read

0. 5tO-15

0. 5tO-l0

191

thICK2L-ENH)

to-15

to-1O

()

192

tsuIENL-CK2H)

Setup time of DEN low to LCLK2i, read

to-20

to-1O

193

thiCK 1 H-ENL)

Hold time of DEN low after LCLK I high. write

to-15

to-l0

194

tsuIENH-CK 1 L)

Setup time of DEN high to LCLK H. write

to-20

to-1O

195

thICK1H-ENH)

Hold time of DEN high after LCLK 1 high, read

to-15

to-1O

196

tsuIENL-CKl L)

Setup time of DEN low to LCLKU, read

to-20

to-1O

197

thICK2L-ENL)

Hold time of DEN low after LCLK2 low. read

0. 5tO-15

0. 5tO-l0

198
199

0. 5tO-15

0. 5tO-l0

to-15

10- 10

200

tsuIENH-CK 1 H) Setup time of DEN high to LCLK 1i, read
thICK2L-DDH) Hold time of DDDUT high after LCLK2 low. read
tsuIDDL-CK2H) Setup time of DDOUT low to LCLK2i, read

to-20

10- 10

201

thiCK 1 H-DDL)

Hold time of DDOUT low after LCLK 1 high, read

to-15

10- 10

202

tsuIDDH-CK I L) Setup time of DDOUT high to LCLK 1 •• read

to-20

10- 10

to-15

to-1O

to-20

10- 10

203
204

shift register transfer

Hold time of

DEiii high

after LCLK2 low, write

Hold time of LAL high after LCLK2 high.
thICK2H-ALH)

CAS-before-RAS refresh
Setup time of LAL low to LCLK2.,

tsuIALL-CK2L)

CAS-before-RAS refresh

oLL
2

NOTE: Advance information notices apply only to the TMS3401 0-60.

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

A-57

TMS34010
GRAPHICS SYSTEM PROCESSOR

local bus timing: relationship of control signals to clocks

LCLK1

Ji"';---.. . .!\."'
. ___

I I
11

/!"f"1

----;1----'

1
I
I
I
I
I

I1 1I

1 159 I..

Ifi

.....JI

LCLK2

1
I
I
1-168

182

I
1 I

iN
Ij.-.!....:.J

I-t

1 ,

190

!-t-189

1
I

r-r
N'- ':-~'195
1
1

192

I'
1

191-l----t

199

-+----i

r--t- 200
I

------------~ I
DDOUT

A-58

t->f-

1
1

I r------t-194

f.-.I-

r
r

I 202 +----i

201~T~:-------

TEXAS . "

INSTRUMENTS
POST OFFICE BOX 1443 •

-I

I: 1*I!
D'
L
:t

198

1 197-1
!----+-196

1 I
1 ~193
I'
1

HOUSTON, TEXAS 77001

TMS34010
GRAPHICS SYSTEM PROCESSOR

ADVANCE
INFORMATION
video interface timing parameters

Thetiming parameters forTMS3401 Ovideo interface signals are shown in the nextthree tables and diagrams.
The video interface includes the following TMS34010 pins: VCLK (video input clock), BLANK
(blanking), HSYNC (horizontal sync, bidirectional), and VSYNC (vertical sync, bidirectional). HSYNC and
VSYNC are inputs if external sync mode is enabled; otherwise they are outputs.

video input clock timing parameters
TMS3401 0·50

TMS3401 0·40

PARAMETER

NO.

MIN

TMS3401 0-60

MAX

MIN

UNIT

MAX

205

tc(VCK)

Period of video input clock VCLK

100

206

tw(VCKH)

Pulse duration of VCLK high

207

tw(VCKL)

Pulse duration of VCLK low

208

tt(VCK)

Transition time (rise and fall) of VCLK

ns
5t

NOTE: Advance information notices apply only to the TMS3401 0-60.
tThis value is determined through computer simulation and is not tested.

video input clock timing
I..

1-- --1

VCLKJ

206

t:(

205

208--1 ~

j.,...-207---' 1

"\ ~,

)LI:...._

208 - - ; ~

Ir___

a::

_----=-Y

oLL
Z

video interface timing parameters: outputs
NO.

TMS3401 040

PARAMETER

MIN
209

Delay from VCLK low to HSYNC. VSYNC. or BLANK low

td(VCKL-HSL)

MAX

TMS3401 0-50
TMS34010-60
MIN

UNIT

MAX
30

210

td(VCKL-HSH) Delay from VCLK low to HSYNC, VSYNC. or BLANK high

211

th(VCKL-HSH)

Hold time of HSYNC. VSYNC, or BLANK high after VCLKl

212

th(VCKL-HSL)

Hold time of HSYNC, VSYNC, or BLANK low after VCLKl

W
(.)

NOTE: Advance information notices apply only to the TMS34010-60.

video output timing

VCLK

~F----:--....J/
I

_'1211--l11
HSYNC.
VSYNC
IOUTPUTS)

I ~210

1-209--\

"\!

\"----

I
};r------------l'

212-ji-i
II

\ . . . 2 0 9 , . J l " - - - - - - - t - 1+1..
""""".1

..... 211--11

212

210

yr------------

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TeXAS 77001

A-59

ADVANCE
INFORMATION

TMS34010
GRAPHICS SYSTEM PROCESSOR
video interface timing: external sync inputs

TMS34010-50
NO.

PARAMETER

TMS340 10-40
MIN

TMS3401 0-60

MAX

MIN

UNIT

MAX

213

tsu(HSV-VCKH)

Setup time of HSYNC, VSYNC valid to VCLKt

20t

214

th(VCKH-HSV)

Hold time of HSYNC, V5YNC valid after VCLK high

20t

SetuptlmeofRSYNC, VSYNC high to VCLK:

20'

I 215 I tsu(HSH-VCKH)

NOTE: Advance information notices apply only to the TMS34010-60.
tSpecified setup and hold times on asynchronous inputs are required only to guarantee recognition at indicated clock edge.
tThis value is determined through computer simulation.

VCLK

I
I
I

I
I

»
2

C')

~213----l
1----214------.1 j 2 1 5 - - t
VSyNC--------------~~~ill______________________________~}IT

HSYNC,
(INPUTS)

t---214i

INOTE 1)

(NOTE 2)

NOTES: 1. If the falling edge of the sync signal occures more than thISV-VCH) past VCLK edge A, and at least tsu(SV-VCH) before edge
B, the transition will be detected at edge B instead of edge A.
2. If the rising edge of the sync signal occurs more than th(SV.VCH) past VCLK edge C, and at least tsu(SV-VCH) before edge
D, the transition will be detected at edge D instead of edge C.

:::rI

~
o
2

A-60

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON, TEXAS 77001

TMS34010
GRAPHICS SYSTEM PROCESSOR

MECHANICAL DATA

~0.25

(0.010) R MAX

IN 3 PLACES

1.27 (0.050) T.P.
(SEE NOTE B)

25.27 (0.995)
25.02 (0.985)
24.33 (0.956)
24.13 (0.950)
(SEE NOTE A)

0.94 (0.037) R
0.69 (0.027)

I
I

"." "."" "" .,-11
0

24.13 (0.950)
25.27 (0.995)
25.02 (0.985)

SEATING PLANE

.on

1.22 (0.048) x 45°
1.07 (0.042)

0.81 (0.032)
O.66 (0.026)

~11t2 (0.060) MIN

0.51 (0.020)
0.36 (0.014)

JL' l

o.64 (0.025) MIN

LEAD DETAIL
NOTES: A. Centerline of center pin each side is within 0,10 (0.004) of package centerline as determined by this dimension.
B. Location of each pin is within 0,127 (0,005) of true position with respect to center pin on each side.

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.

TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •

HOUSTON. TEXAS 77001

A-61

Printed in U.S.A.

SPVS002B

Appendix B

System Design Considerations

Please read these emulation guidelines before starting a system design that
requires use of an XDS emulator. In-circuit emulators place added constraints
on the system hardware and software design; the XDS TMS34010 emulator
minimizes these constraints as much as possible. Many of the emulator signals
come directly from the device itself keeping the delays to a minimum. The
information provided in this appendix will allow your design to be compatible
with the TMS3401 0 XDS emulator.
Topics in this section include:
Section
Page
B.1 Pin Loading ................................................................................................ B-2
B.2 Signal Timing and Delay .......................................................................... B-4
B.3 Transmission Line Phenomena ................................................................ B-5
B.4 Host Port Operation .................................................................................. B-5
B.5 Reset Buffering .......................................................................................... B-5
B.6 Local Ready Timing .................................................................................. B-6
B.7 Memory Substitution ................................................................................ B-6
B.8 Write Protecting Memory ......................................................................... B-6
B.9 Tracing and Cache .................................................................................... B-7

B-1

Appendix B - System Design Considerations

B.1 Pin loading
The loading provided by the emulator differs from the device loading; in some
cases, this additional loading can cause a system to fail or pass. For instance,
within the emulator the VCLK and INCLK clocks are buffered by an AS157
device. If the target clocks are driven by an AS driver over a long distance, the
system may operate satisfactorily with the emulator's loading. When the device is used, the clocks can ring, causing the system to faiL
To minimize ringing caused by the emulator, all the outputs and II0s are terminated with 22-ohm series resistors. Most of the signals are connected directly to the target connector to minimize the added delays. Table 8-1 shows
the device loads that are placed on the emulator pins.
In Table 8-1, pin refers to the emulator target pin. An arrow (-+) indicates
that the specified device drives the device(s) it the arrow points to. Devices
in parallel are separated by commas; devices in series are in brackets. As an
example, consider LADO; the pin connects to a 22-ohm series resistor, and the
other side of the resistor is connected to an ALS245, AS573, and the
TMS34010.
Table B-1. Loading
Pin

Signal

1
2

Vss
RUN/EMU

FfE'S"ET

VCLK

pin, 330PU, 51 OPD, A5157 -+ TMS34010

INCLK

pin .... [AS157] -+ TMS34010

I/O
pin, 4.7KPU, ALS08

pin, 4.7KPU, TIBPAL-12, TMS9901, ALS574, A5257
-+ [ALS08 + AS04 + ALS08 + AS874 + AS04] -+
TMS34010

DNT1

pin, 4.7KPU -+ [A5257] -+ TM534010

DNT2

pin, 4.7KPU -+ [AS257] -+ TMS34010

'R('j"[[)

pin, 4.7KPU, AS874, TMS34010

LRDY

pin, 4.7KPU, [TIBPAL-12] -+ TMS34010

10
11

LADO

I/O

pin .... [22S] .... ALS245, AS573, TMS34010

LAD1

I/O

pin .... [22S] -+ ALS245, AS573, TMS34010

LAD2

I/O

pin -+ [22S] -+ ALS245, AS573, TMS34010

LAD3

I/O

pin -+ [22S] -+ ALS245, A5573, TMS3401 0

LAD4

I/O

pin -+ [22S] -+ ALS245, AS573, TMS3401 0

LAD5

I/O

pin -+ [225] .... ALS245, AS573, TMS34010

LAD6

I/O

pin -+ [22S] .... ALS245, AS573, TMS3401 0

LAD7

pin -+ [22S] -+ ALS245, AS573, TMS34010
\ISS
19
pin -+ [225] -+ AL5245, AS573, TMS34010
LAD8
I/O
PO - Pull down
PU - Pull up
S - Series resistor
[] - Devices in series
pin - Emulator target cable pin
18

B-2

I/O

Appendix B - System Design Considerations

Table 8-1. loading (Continued)
Pin

Signal

I/O

LAD9

I/O

pin -+ [22S] .... ALS245. AS573, TMS34010

LAD10

I/O

pin -+ [22S] -+ ALS245, AS573. TMS34010

LAD11

I/O

pin -+ [22S] .... ALS245. AS573. TMS3401 0

LAD12

I/O

pin .... [22S] .... ALS245. AS573. TMS34010

LAD13

I/O

pin .... [22S] .... ALS245. AS573. TMS34010

LAD14

I/O

pin -+ [22S] .... ALS245. AS573. TMS34010

LAD15

I/O

pin -+ [22S] .... ALS245, AS573, TMS3401 0

27
28

Vee
LCLK1

LCLK2

0
0

HSYNC

I/O

VSYNC

I/O

TMS34010, ALS573 .... [225] .... pin

BLANK

0
0
0

TMS34010, ALS573 .... [22S] .... pin

TMS34010 -+ [TIBPAL-12 + 22S] -+ pin

TMS34010. AS244, AS04 .... [22S] .... pin
TMS34010, AS244 -+ [22S] .... pin
TMS34010, ALS573 .... [22S] .... pin

TMS34010 .... [AS08 + 10S] -+ pin

HLDA/EMU

LAL

35
36

Vss
DDOUT

RAS"

0
0
0

39
40

'CAS

TMS34010 .... [TIBPAL-12 + 22S] -+ pin

wmTE

TMS34010 .... [TIBPAL-12 + 22S] .... pin
TMS34010 .... [TIBPAL-12 + 22S] .... AL244, pin

TMS34010, 100KPU, AS11, AS04 -+ [22S] .... pin

TMS34010 -+ [TIBPAL-12 + 22S] .... pin
TMS34010 AS157, 100KPU .... [22S] .... pin

TR/QE

HINT

HRDY

0
0
0

HAD15

I/O

TMS34010 .... [22S] .... pin

HAD14

I/O

TMS34010 .... [22S] .... pin

HAD13

HAD12

I/O
I/O

TMS34010 .... [22S] .... pin
TMS34010 .... [22S] .... pin

HAD11

I/O

TMS34010 .... [22S] .... pin

HAD10

I/O

TMS34010 .... [22S] .... pin

HAD9

I/O

TMS34010 .... [22S] .... pin

HAD8

I/O

TMS34010 .... [22S] .... pin

52
PO
PU
5
[]
pin

TMS34010 ALS244 -+ [22S] .... pin
TMS34010 -+ [AS08 + 10S] -+ pin

Vss
Pull down
Pull up
Series resistor
Devices in series
Emulator target cable pin

B-3

Appendix B - System Design Considerations

Table B-1. Loading (Concluded)
Pin

Signal

I/O

HAD7

I/O

TMS34010 .... [22S] .... pin

HAD6

I/O

TMS34010 .... [22S] .... pin

55
56

HAD5

I/O

TMS34010 .... [22S] .... pin

HAD4
HAD3

I/O
I/O

TMS34010 .... [22S] .... pin
TMS34010 .... [22S] .... pin

HAD2

I/O

TMS34010 .... [22S] .... pin

HAD1

I/O

TMS34010 .... [22S] .... pin

60
61

HADO

I/O

TMS34010 .... [22S] .... pin

HU15S

pin, 100KPU, TMS34010

pin, 1OOKPU, TMS3401 0

pin. 100KPU, ALS573, TMS34010

pin, 100KPU, AS573, TMS34010

RmS"
'!mEAD
HWRlTE'
'FfCS"

pin, 4.7KPU .... [AS232 + AS08 + TMS3401 0] ....
ALSOO, ALS74, TI BPAL-12, LS02

HFSO

pin, 100KPU, ALS573, TMS34010

HFS1

pin, 1OOKPU, ALS573, TMS3401 0

64
65

PO
PU
S
[]
pin

._ ..

Vee

Pull down
Pull up
Series resistor
Devices in series
Emulator target cable pin

B.2 Signal Timing and Delay
The target cable delays all signal timings by approximately four nanoseconds;
the following signals impose an additional delay:
Signal Delay
VCLK
6ns
6ns
INCLK
6ns
LlNT1
LlNT2
6ns
DDOUT 12ns
DEN
12ns

Signal Delay
12ns
12ns
12ns
12ns
HRDY
6ns
HCS
12ns

CAS
WRITE
TR/QE
LRDY

Remember these additional delays when you are calculating system timings.
The cable delays should cancel out when comparing the signal to the clock;
for instance, the clock is delayed by four nanoseconds and so is the address.
The problem comes from setup times required by the TMS34010. For instance, CAS out is delayed by 16 nanoseconds and data-in is delayed by four
nanoseconds. This 20 nanoseconds must be added to the memory access
time. For this reason, it is important not to use CAS to control LRDY. Both

B-4

Appendix B - System Design Considerations

LRDY and CAS are delayed by 12 nanoseconds; combined, this adds 24 nanoseconds to the LRDY setup, which violates the device requirements.

B.3 Transmission Line Phenomena
Since the XDS target cable is approximately 20 inches long, use of advanced
CMOS or fast/advanced Schottky-TTL may cause line reflections (ringing
above input thresholds) on input lines to the XDS. Series termination resistors
(22 to 68 ohms) can help to eliminate this problem. In some cases where
significant additional signal length is added to XDS outputs, the series resistors on the XDS may not be sufficient to control reflections. In this case, additional corrective actions may be necessary.

B.4 Host Port Operation
The emulator host port supports two modes of operation:
•

The first mode blocks the host port while the emulator is in control mode
(that is, not running) and when the XDS emulator requires its internal
TMS34010 as a resource. Systems that access the host port when in
control mode have HRDY inactive when they start an access and remain
inactive until the emulator is put into run mode. This is a problem for
PCs because they use DMA cycles to perform DRAM refresh and are
prevented from performing any further memory cycles.

•

The second mode of operation allows host accesses while the emulator
is in control mode. When the emulator is halted, a snapshot is taken of
the I/O registers before transferring control to the user. While halted, the
host has access to the TMS34010's I/O registers and memory space.
Data read from the I/O and memory space may not represent the actual
data as the host can be changing the data through the host port. Data
written through the XDS user interface to any I/O registers or memory
locations used by the host port can cause unpredictable results. This
mode is the typical dual-allocation problem that is prevalent in multiport
memory systems.

B.5 Reset Buffering
The RESET input from the target system is buffered so that reset cannot abort
a memory cycle that is in progress. This is necessary to prevent corruption of
the substitution memory. Reset is ANDed with RAS and CAS and clocked on
the rising edge of LCLK1. If reset is active and RAS and CAS are inactive, then
reset is applied to the processor. While the RESET input is active, internal
emulator logic provides CAS-before-RAS refreshes for emulator memory, but
not for your system memory; target memory is not refreshed during reset.
Therefore, you shouldn't perform a target reset following a download of object
code into target memory, because this may destroy the contents of target memory.

8-5

Appendix B - System Design Considerations

If the target system also generates a reset during the emulator-TMS3401 0 reset, and HCS is high (which, under normal circumstances, would halt the
TMS34010), the emulator reset takes precedence and does not halt the
TMS34010.

The ready logic requires special attention; the target system should not depend
on having CAS to clear ready. This can cause a deadlock situation if the memory is write protected. In this case, the emulator blocks the CAS output to
the target and the target system is locked waiting for CAS to release LRDY.
Thus, if you are working with the emulator and write-protecting memory, your
ready logic should use a combination of RAS and clock delays instead of CAS.

B.7 Memory Substitution
The 256K bytes of substitution memory is implemented with two banks of
64Kx4 DRAMs. This memory can be mapped on 2K word boundaries. The
memory can be selected as write-only using the memory protect feature described below. When a memory access is made that is mapped into substitution memory the signals are modified as follows:
•

DEN, CAS, WR, and TR/QE are blocked from going active.

•

Ready is accepted from the target to allow adding wait states to the
substitution memory.

Ready should not be controlled by DEN, CAS, WR or TR/OE because these signals are blocked and a deadlock condition would take place.
All the other signals operate as though a standard memory cycle were taking
place. Be aware that when you're using substitution memory, it can only be
accessed by the processor and host port and cannot be accessed when the
TMS34010 is put into hold. The target system should not drive the LAD bus
unless CAS and DEN are active.

B.8 Write Protecting Memory
The emulator allows memory to be write-protected in blocks of 2048 words.
The memory can be external memory as well as the substitution memory. The
memory write operations are inhibited by blocking the CAS output. As with
the substitution memory, ready should not be controlled by CAS because a
deadlock condition will take place. External system memory is only write
protected from CPU and host accesses and not DMA accesses initiated with
a HOLD/HOLDA sequence.

8-6

Appendix B - System Design Considerations

B.9 Tracing and Cache
Please note that the breakpoint trace and timing capabilities are used to monitor bus activity. The TMS3401 O's pipelined-cache-based architecture fetches
the current instruction and the three associated instructions in the cache subsegment when a cache miss occurs. This is indicated as four fetches even
though only one instruction may be executed. Also, when the cache is enabled, code already located in cache does not generate any instruction-fetch
activity on the memory bus when it is executed. If you want to create a complete trace history, run the TMS34010 with cache disabled. By disabling
cache, all instructions executed are moved over the external memory bus every
time they are executed, allowing them to be captured in the trace buffer.

B-7

Appendix B - System Design Considerations

8-8

Appendix C

Software Compatibility with Future GSPs

This appendix provides guidelines for writing TMS34010 programs that will
be compatible with future versions of TMS340xO devices. In some cases,
following these guidelines may not produce the fastest TMS34010 code;
however, your code should run without modification on future GSPs.
These guidelines cover several areas:

Section
C.1
C.2
C.3
C.4
C.5
C.6

Page

General Guidelines ....................................................................................
Graphics Compatibility .............................................................................
Memory Map Compatibility .....................................................................
1/0 Register and Video Timing Compatibility .......................................
Interrupts Compatibility ............................................................................
Host Interface Compatibility ....................................................................

C-2
C-2
C-3
C-4
C-4
C-5

C-1

Appendix C - Software Compatibility with Future GSPs

C.1 General Guidelines
•

Future GSPs may have different instruction execution times than the
TMS34010 has; therefore, timing loops based on TMS3401 0 instruction
execution time may not be compatible with future GSPs. Even if future
devices are generally faster than the TMS3401 0, specific cases may run
slower. To avoid this, timing could be based on DPYINT (the display
interrupt) or on an external tirile SOiin~e (via LINT1 Oi LINT2). Nota that
if you use DPYINT, you must consider different display resolutions and
refresh rates.

•

For optimum performance on future GSPs, align data on 32-bit boundaries (instead of 16-bit boundaries). This could reduce the number of
memory cycles for future GSPs, and in most cases will have little impact
on the TMS3401 O. In particular, keeping the stack pointer (SP) aligned
to 32-bit boundaries will speed up subroutine calls and interrupts.

•

Future GSPs may use the reserved bits in the status register and in the
I/O registers. During context switches, the values of reserved bits should
be saved and restored as if they were valid; do not assume that these bits
have known values. If you don't follow this guideline, your code may
inadvertently enable/disable new options or features.
Unless otherwise noted in this user's guide, when reserved bits have a
value of 0, they will cause future GSPs to behave like the TMS34010.
However, you should not set these bits to 0, because this may incorrectly
reset a bit.

•

Use the REV instruction to determine which version of the GSP you are
using. You can use this instruction to decide whether to enable or disable version-dependent code.

•

Instruction cache statistics characteristics (including cache size, loading
order, number of bytes loaded per cache miss, and time per cache fetch)
may differ between versions of GSPs. Code should not depend on the
state of any of these characteristics.

C.2 Graphics Compatibility

C-2

•

Extend the values in the COLORO and COLOR1 registers to 32 bits. The
TMS34010 uses only the 16 LSBs of these registers; future GSPs may
use all 32 bits.

•

Treat the PMASK register as a 32-bit register. The TMS3401 0 uses only
the 16 bits at address OC0000160h; however, future GSPs may also use
the 16 bits at address OC0000170h. Whenever you save/restore the
value at OC0000160h, you should also save/restore the value at
OC0000170h.

•

When you save/restore the graphics context (this includes all graphics
operations control registers), you should also save/restore the I/O reg-

Appendix C - Software Compatibility with Future GSPs

isters that are reserved in the TMS34010 I/O register map (addresses
OC0000130h-OC00001 AOh).
•

At initialization, load register B13 with all 1 s. Future GSPs may use B13
as a pattern register; if you don't set B13 to the suggested value, future
devices may draw a patterned line where the TMS3401 0 would draw a
solid line.

•

If an instruction uses the CONVSP register, then SPTCH (B1) must
agree with CONVSP (the 5 LSBs of CONVSP must equal the 1 s complement of 1092 SPTCH, which is given by the LMO of SPTCH). Future
GSPs may have instructions that use SPTCH to determine the pitch values instead of using CONVSP; that is, the instruction may perform the
1092 conversion automatically.
Set the 11 MSBs of CONVSP to 0; the TMS34010 ignores the values
of these bits, but future GSPs may use these bits.

•

If an instruction uses the CONVDP register, then DPTCH (B3) must
agree with CONVDP (the 5 LSBs of CONVDP must equal the 1 s complement of 1092 DPTCH, which is given by the LMO of DPTCH). Future
GSPs may have instructions that use DPTCH to determine the pitch values instead of using CONVDP; that is, the instruction may perform the
1092 conversion automatically.
Set the 11 MSBs of CONVDP to 0; the TMS34010 ignores the values
of these bits, but future GSPs may use these bits.

C.3 Memory Map Compatibility
•

The 32 16-bit words following the TMS3401 0 I/O registers (addresses
OC0000200h-oC00003FOh) are currently reserved. Future GSPs may
use these addresses for additional I/O registers, so do not write code that
uses these addresses.

•

Do not use any reserved addresses in the TMS3401 0 memory map; future GSPs may use these locations. Specifically, address OFFFFEOOOh,
which is currently reserved, may be used for system configuration information.

C-3

Appendix C - Software Compatibility with Future GSPs

C.4 I/O Register and Video Timing Compatibility

c.s

•

Future GSPs may use different I/O registers to control video timing and
VRAM shift register control. The vertical and horizontal counters may
DPYADR, DPYCTL,
still be accessible at their current locations.
DPYSTRT, and DPYTAP may have new functions and/or addresses.
HESYNC, HEBLNK, HSBLNK, HTOTAL, VESYNC, VEBLNK, VSBLNK,
and VTOTAL may have simiiar functions but different addresses. These
video control functions may be redefined so that future GSPs can take
advantage of new advances in video RAM technology.

•

Code that accesses video timing registers should be separated from other
code so that you can easily replace it.

•

Future GSPs may use different DRAM refresh methods; the TMS3401 0
provides control every 32 or 64 CPU cycles, and it may be necessary to
have more control.

Interrupts Compatibility
•

Interrupt service routines should not make assumptions about the state
of the stack (except for the location of the ST and the PC). Future GSPs
may push additional parameters or status information on the stack before
pushing the PC and ST.

Note:
You must use RETI to return from an interrupt service routine. This ensures that any additional parameters that future GSPs may push on the
stack will also be popped from the stack, and also ensures that the correct
internal registers will be restored.
•

PIXBLT interruption may behave differently on future GSPs. An interrupted PIXBLT may store status information on the stack instead of in
registers, and different information may be stored.
Note:
Do not modify values stored in the register file by an interrupted PIXBLT.
Future GSPs may not use this information or these locations.

C-4

•

Opcodes that the TMS34010 flags as illegal may be valid opcodes for
future GSPs. Therefore, if you want to use a software trap, use the TRAP
instruction instead of an illegal opcode.

•

Traps 3-7 and 12-15 are reserved for future interrupts.

Appendix C - Software Compatibility with Future GSPs

C.6 Host Interface Compatibility
•

Certain features of the TMS3401 0 host interface may need to be implemented in external hardware for future GSPs. However, the host interface registers and their functions wi" remain the same so that TMS3401 0
code that uses these registers wi" be compatible with future GSPs.

•

Code written for a host processor that accesses the GSP host interface
may have to be modified to comprehend a modified host interface.

C-5

Appendix C - Software Compatibility with Future GSPs

c-s

Appendix 0

Glossary

aliasing: A stairstep effect on a raster display of a line or arc segment.
antialiasing: A method for reducing the severity of aliasing effects seen in
lines and edges drawn on a bit-mapped display device. This method adjusts
the intensity of a pixel used to represent a portion of a line or edge according
to the pixel's distance from the line or edge. Antialiasing requires that the
display device be capable of producing one or more intermediate intensity
levels between bright and off.
asynchronous communications: A method of transmitting data in which
the timing of character placement of connecting transmitting lines is not critical. The transmitted characters are preceded by a start and followed by a stop
bit, thus permitting the interval between characters to vary.
aspect ratio: The ratio of width to height. For the rectangular picture
transmitted by a television station, the aspect ratio is 4:3.
back porch: The portion of a horizontal blanking pulse that follows the
trailing edge of the horizontal synchronizing pulse.
background illumination: The average brightness of a screen.
bandwidth:
device.

The number of bits per second that can be transferred by a

binary array: Alternate name for a two-dimensional bit map in which each
pixel is represented as single bit.
BitBlt: Bit aligned block transfer. Transfer of a rectangular array of pixel
information from one location in a bitmap to another with potential of applying
1 of 16 boolean operators during the transfer.
bit map: 1. The digital representation of an image in which bits are mapped
to pixels. 2. A block of memory used to hold raster images in a device-specific
format.
bit plane:

Hardware used as a storage medium for a bit map.

black level: The amplitude of the composite signal at which the beam of the
picture tube is extinguished (becomes black) to blank retrace of the beam.
This level is established at 75% of the signal amplitude.
blanking signal: Pulses used to extinguish the scanning beam during horizontal and vertical retrace periods.

0-1

Appendix 0 - Glossary

breakpoint: A place in a routine specified by an instruction, instruction digit, or other condition, where the routine may be interrupted by external intervention or by a monitor routine.
clipping: Removing parts of display elements that lie outside a given boundary, usually a window or a viewport.
comDosite video:

The color-oicture siamlf ollis ;:III hl;:lnkinn ;:Inn svnr.hrn-

nizing signals. The signal i~clud'es i~~i~a~nc-e ';;nd- chro~-i~a-~~~ ;ig~';I~~-~~rti
cal- and horizontal-sync pulses, vertical- and horizontal-sync pulses,
vertical-and horizontal-blanking pulses, and the color-burst signal.

DAC: Digital-to-analog converter. A device that converts a digital input
code to an analog output voltage or current. The analog output level represents the value of the digital input code.
direct access: Pertaining to the process of obtaining data from, or placing
data into, storage where the time required for such access is independent of
the location of the data most recently obtained or placed in storage.
display area: The rectangular part of the physical display screen in which
information coded in conformance with a video encoding standard is visibly
displayed. The display area does not include the border area.
display element:
display image.

A basic graphic element that can be used to construct a

display memory: The area of memory which is used to hold the graphics
image output to the video monitor.
display pitch: The difference in memory addresses between two pixels that
appear in vertically adjacent positions (one directly above the other) on the
screen.
display unit:

A device which provides a visual representation of data.

dot clock: The dot clock cycles the rate at which video data is output to a
CRT monitor.

DRAM refresh: The operation of maintaining data stored in dynamic
RAMs. Data are stored in dynamic RAms as electrical charges across a grid
of capacitive cells. The charge stored in a cell will leak off over time.
execution unit: The portion of a central processing unit that actually executes the data operations specified by program instructions.
field: 1. A group of contiguous bits in a register or memory dedicated to a
particular function or representing a single entity. 2. A software-configurable
data type in the TMS3401 0 whose length can be programmed to be any value
in the range 1 to 32 bits.
fill: Solid coloring or shading of a display surface, often achieved as a pattern of horizontal segments.
frame: 1. The time required to refresh an entire screen. 2. The screen image
output during a single vertical sweep.

D-2

Appendix D - Glossary

frame buffer: A portion of memory used to buffer rasterized data to be
output to a CRT display monitor. The contents of the frame buffer are often
referred to as the bit map of the display and contain the logical pixels corresponding to the points on the monitor screen.
front porch: The portion of a horizontal blanking pulse that precedes the
leading edge of the horizontal sync pulse.
GKS: Graphical Kernel System. An application programmer's standard interface to a graphics display.
glue logic: The small- and medium-scale-integrated devices necessary to
complete the interface between two or more large or very-large-scale integrated devices.
gray scale:

A scale of light intensities from black to white.

GSP: Graphics System Processor. A single-chip device embodying all the
processing power and control capabilities necessary to manage a highperformance bit-mapped graphics system. The TMS34010 is the first such
device.
high-impedance: The third state of a three-state output driver, in which the
output is driven neither high or low but behaves as an open connection.
hold signal: A signal from a device capable of controlling a processor bus
(for example, a processor or a DMA controller) which the device sends to a
bus arbiter to request control of the bus. Typically, the arbiter signals the
granting of the request by sending a hold-acknowledgement signal to the requesting device.
hold time: The minimum amount of time that valid data must be present at
an input after the device is clocked to ensure proper data acceptance.
horizontal blanking interval: The time during which the display is
blanked to cover the horizontal retracing of the electron beam.
horizontal sync: The synchronization signal that enables horizontal retrace
of the electron beam of a CRT display.
icon: A graphic symbol representing a menu item.
interlaced scanning: A system of TV-picture scanning. Odd-numbered
scanning lines, which make up an odd field, are interlaced with the evennumbered lines of an even field. The two interlaced fields constitute one
frame. In effect, the number of transmitted pictures is doubled, thus reducing
flicker.
lookup table: A table used during scan conversion of the digital image that
converts color-map addresses into the actual color values displayed.
LRU: Least-recently-used cache-replacement algorithm. When a cache miss
occurs, a cache-replacement algorithm selects which cache segment will be
overwritten, based on the likelihood that the data in the discarded segment
will not be needed again for some time. The LRU algorithm selects the segment which was used least recently.

0-3

Appendix D - Glossary

mask: A pattern of characters that is used to control the retention or elimination of portions of another pattern of characters.
memory map:

A map of memory space partitioned into functional blocks.

monotonicity: The quality of proceeding in a uniform manner. For example, the analog level output from a DAC should increase with each increase in
the value of the digital input code.
multiplexing: Refers to a process of transmitting more than one set of signals at a time over a single wire or communications link.
NABTS:

North American Broadcast Teletext Specification

NAPLPS: Abbreviation for the North American Presentation Level Protocol
Syntax, which is a proposed standard for Videotex services.
nonmaskable interrupt: An interrupt request that cannot be disabled.
NMI: Nonmaskable interrupt. The NMI is an interrupt that is permanently
enabled; it cannot be disabled.
NTSC: Abbreviation for the National Television System Committee, a group
representing a wide range of interests in the television broadcast and video
industry. The NTSC is instrumental in developing standards.
operand: That which is operated upon. An operand is usually identified by
an address part of an instruction.
origin: The zero intersection of X and Y axes from which all points are calculated.
overlay: The plane of a graphics display that can be superimposed on another plane.
pack: To compress data in a storage medium by eliminating redundant information in such a way that the original data can later be recovered.
palette: A digital lookup table used in a computer graphics display for
translating data from the bit map into the pixel values to be shown on the
display.
pan: Apparent horizontal or vertical movement of a computer graphics screen
(or window) over an image contained in a frame buffer that is too large to be
completely displayed in a single static picture.
phase: The time interval for each clock period in a system is divided into two
phases. One phase corresponds to the time the clock signal is high, and the
other phase corresponds to the time the clock signal is low.
PHIGS: The programmer's Hierarchical Interactive Graphics Standard
pipelining: A design technique for reducing the effective propagation delay
per operation by partitioning the operation into a series of stages, each of
which performs a portion of the operation. A series of data is typically clocked
through the pipeline in sequential fashion, advancing one stage per clock period.

0-4

Appendix D - Glossary

pitch: The difference in starting addresses of two adjacent rows of pixels in
a two-dimensional pixel array.
pixel: Picture element. 1. The smallest controllable point of light on a CRT
display screen. 2. In a bit-mapped display, the logical data structure that
contains the attributes to be shown at the corresponding physical pixel position on the CRT display screen.
pixel processing operation: A specified Boolean or arithemetic operation
used to combine two pixel values (source and destination).
PixBlt: (Abbreviation of Pixel Block transfer) Operations on arrays of pixels
in which each pixel is represented by one or more bits. PixBlt operations are
a superset of BitBlt operations, and include not only the commonly-used
boolean functions, but also integer arithmetic and other multi-bit operations.
plane: (Also bit plane or color plane.) A plane is a bit-map layer in a display
device with mUltiple bits per pixel. If the pixel size is n bits, and the bits in
each pixel are numbered 0 to n-1 , plane 0 is made up of bits numbered 0 from
all the pixels, and the plane n-1 is made up of bits numbered n-1 from all the
pixels. A layered graphics display allows planes or groups of planes to be
manipulated independently of the other planes.
primary colors: A set of three colors from which all other colors may be
regarded as derived; hence, any of a set of visual stimuli from which all colors
may be produced by mixture. Each primary color must be different from the
others, and a combination of two primaries must be capable of producing a
third. In color television, the three primary colors are red, green and blue.
propagation delay: The time required for a change in logic level at an input
to a circuit to be translated into a resulting change at an output.
protocol: A set of rules, formats, and procedures governing the exchange
of information between peer processes at the same level.
pulse width: Pulse width, T w. The time interval between specified reference points on the leading and trailing edges of the pulse waveform.
Random Access Memory (RAM): A memory from which all information
can be obtained at the output with approximately the same time delay by
choosing an address randomly and without first searching through a vast
amount of irrelevant data.
raster: A rectangular grid of picture elements whose intensity levels are
manipulated to represent images. In a bit-mapped display, the bits within a
portion of the memory referred to as the frame buffer are mapped to the raster
pattern of a CRT monitor.
raster display: A CRT display generated by an electron beam that illuminates the CRT by sweeping the beam horizontally across the phosphor surface
in a predetermined pattern, providing substantially uniform coverage of the
display area.
raster graphics: Computer graphics in which a display image is composed
of an array of pixels arranged in rows and columns.

0-5

Appendix D - Glossary

Raster-Op: The arithmetic or logical combination operation that takes place
during the transfer of pixel arrays from one location to another.
raster scan: The grid pattern traced by the electron beam on the face of the
CRT in a television or similar raster-scan display device.
ready signal: A signal from a memory or a memory-mapped peripheral that
informs the processor when it is ready to complete a memory cycle. Slower
memories or memory-mapped peripherais must extend the length of the memory cycle by negating the ready signal (in other words, by sending the processor a "not ready" signal until such time as the cycle can be completed.
resolution: The number of visible distinguishable units in the device coordinate space.
refresh: Method which restores charge on capacitance which deteriorates
because of leakage.
reset: To restore to normal action.
resolution: The number of visible distinguishable units in the device coordinate space.
retrace: The line traced by the scanning beam or beams of a picture tube
as it travels from the end of one horizontal line or field to the beginning of the
next line or field.
RGB monitor: Red-Green-Blue Monitor. An RGB monitor is a CRT monitor capable of displaying colors and having separate inputs for the three signals used to drive the red, green and blue guns of the CRT.
relative coordinates:

Location of a point relative to another data point.

rotate: To transform a display or display item by revolving it around a specified axis or center point.
scale: A size change made by mUltiplying or dividing the coordinate dimensions by a constant value.
scale factor: The value by which you divide or multiply the display dimensions in a scaling operation.
scaling: Enlarging or reducing all or part of a display image by multiplying
the coordinates of display elements by a constant value.
scan line: A horizontal line traced across a CRT by the electron beam in a
television or similar raster-scan device.
screen refresh: The operation of dumping the contents of the frame buffer
to a CRT monitor in synchronization with the movement of the electron beam.
scrolling:

Moving text strings or graphics vertically or horizontally.

segment: A collection of display elements that can be manipulated as a unit.
sequencing: Control method used to cause a set of steps to occur in a
particular order.

0-6

Appendix 0 - Glossary

setup time: The minimum amount of time that valid data must be present
at an input before the device is clocked to ensure proper data acceptance.
shift register transfer: A transfer between the RAM storage and internal
shift register in a video RAM.
sprite: A graphic object of a specified pattern appearing on its plane in a
position determined by a single coordinate pair, specifying the sprite's location
on the screen in the horizontal and vertical axis.
stairstepping: A visual effect seen in bit-mapped display devices which
produce images by brightening or dimming individual picture elements (or
pixels) contained in a two-dimensional grid of such elements. Stairstepping
(also called aliasing) is the rough or jagged appearance of lines and edges
which are not perfectly horizontal or vertical, resulting from transitions of the
line or edge from one row or column of elements to another.
superimposed: Refers to the process that moves data from one location to
another, superimposing bits or characters on the contents of specified locations.
tap point: The column address provided to a VRAM during a memory-toshift-register cycle. The column address specifies the point at which the shift
register is to be "tapped;" in other words, which cell of the shift register is to
be connected to the serial output of the VRAM.
trace:

A line of the graphics display.

transformation: Geometric alteration of a graphics display, such as scaling,
translation, or rotation.
transparency: When a pixel with the attribute of transparency is written to
the screen, it is effectively invisible, and does not alter that portion of the
screen it is written to. For example, in a pixel array containing the pattern for
the letter A, all pixels surrounding the A pattern could be given a special value
indicating that they are transparent. When the array is written to the screen,
the A pattern, but not the pixels in the rectangle containing it, would be invisible.

VOl:

Virtual Device Interface. The standard interface between the deviceindependent and the device-dependent levels of a graphics system.

VOM: Virtual Device Metafile. A standard mechanism for retaining and and
transporting graphics data and control information at the level of the Virtual
Device Interface.
vertical blanking interval: The time during which the display is blanked
to cover the vertical retracing of the electron beam.
vertical blanking pulse: A positive or negative pulse developed during
vertical retrace and appearing at the end of each field. It is used to blank out
scanning lines during the vertical retrace interval.
vertical sync: The synchronization signal that enables vertical retrace of the
electron beam of a CRT display.
video display processor: A microprocessor device dedicated to the tasks
of display memory management (storage, retrieval, and refresh) and gener0-7

Appendix 0 - Glossary

ation of all required video, control, and synchronization signals required by a
TV display or CRT monitor.
video overlay: The mixing of one video signal with another such that parts
of the image carried by the first signal replace the corresponding parts of the
image carried by the second signal.
video RAM, VRAM: Video Random-Access Memorv. A dual-Dorted memory device for computer graphics applications, containing two· interfaces;
one interface to allow a processor to read or write data from an internal memory array; a second interface to provide a serial stream of screen refresh data
to a CRT display device.
viewport: The specified window on the display surface that marks the limits
of a display.
virtual coordinate system: A coordinate system created by mapping a
portion of the world coordinate system to the space available on your device.
virtual space:
cation.

Space referenced with the coordinates defined by the appli-

wait state: A clock period inserted into a memory cycle in order to permit
accesses of slower memories and slower memory-mapped peripherals.
window:
play.

A specified rectangular area of a virtual space shown on the dis-

window clipping: Allowing text and graphics drawing to occur only within
a specified rectangular window on the screen.
wire frame: A three-dimensional image displayed as a series of line segments outlining its surface.
zoom: To scale a display or display item so it is magnified or reduced on the
screen.

0-8

Index

A
ABS instruction 12-35
absolute branch 5-19
absolute operands 12-5
ADD instruction 12-36
add with saturation 7 -16
ADDC instruction 12-37
ADDI instruction 12-38, 12-39
ADDK instruction 12-40
addressing 3-2-3-3
addressing modes 12-4
ADDXY instruction 12-41
A-file registers 5-2
airbrush effect 7 -23
ALU 1-6
AN D instruction 12-42
ANDI instruction 12-43
ANDN instruction 12-44
ANDNI instruction 12-45
antialiasing 7-23
applications 1 -8
arithmetic instructions 12-19
array pitch 4-16

B
background color register 5-15
bank selection 11 -25
barrel shifter 1 -6
B-file registers 5-3, 5-5-5-17
BLANK 2-9, 9-3
blanking 2-9,6-27,6-29,6-49,6-51
block diagram 1-5
Boolean operations 7 -1 7
Boolean pixel processing 6-13
Bresenham line algorithm 7-2,7-10
BTST instruction 12-46, 12-47
bulk initialization of VRAMs 9-18, 9-26
bus request priorities 11 -4
bus request signal 2-10
byte addressing 10-20
bytes 4-1
BO (SAD DR) 5-6

B1 (SPTCH) 5-7
B10 (COUNT) 5-17
B11 (INC1) 5-17
B12 (INC2) 5-17
B13 (PATTRN) 5-17
B13 (TEMP) 5-17
B2 (DADDR) 5-8
B3 (DPTCH) 5-10
B4 (OFFSET) 5-11
B5 (WSTART) 5-12
B6 (WEND) 5-13
B7 (DYDX) 5-14
B8 (COLORO) 5-15
B9(COLOR1) 5-16

c
Cbit 5-18
C compiler 1-12
cachedisable 6-14
cache hit 5-22
cache miss 5-22
cache replacement algorithm 5-21
CALL instruction 12-48
CALLA instruction 12-49
CALLR instruction 12-50
Cartesian coordinates 4-16
CAS 2-7,11-2
CD bit 5-24,6-11,6-14
CF bit 5-23, 5-24, 6-32, 6-33
chip select pin 2-5
clearing ...
a register 12-51
the carry bit 12-52
clock timing logic 1 -7
CLR instruction 12-51
CLRC instruction 12-52
CMP instruction 12-53
CMPI instruction 12-54, 12-55
CMPXY instruction 12-56
Cohen-Sutherland algorithm 7-30
color planes 7 -12
color-expand operation 7-5
COLORO register 5-15
COLOR1 register 5-16
Index-1

column address strobe 2-7
compare instructions 12-19
compare point to window 7-3
context switching instructions 12-29
CONTROL 6-11
CONTROL register 6-11
CONVDP 7-4
CONVDP register 4-12,6-15
conversion factor 6-15, 6-16
CONVSP 7-4
CONVSP register 4-12,6-16
COUNT register 5-17
CPW instruction 12-57
CVXYL instruction 12-59

o
DADDR register 5-8
data enable pin 2-7
data paths 1 -6, 5-25
data select pins 2-5
data structures
bytes 4-1
fields 4-1, 4-2-4-5
pixel arrays 4-1
pixels 4-1,4-6-4-10
DDOUT 2-7, 11-2
DEC instruction 12-61
DEN 2-7,11-2
destination address register 5-8
destination conversion factor 6-15
destination pitch register 5-10
development tools list 1 -3
DIE bit 6-40
DINT instruction 12-62
DIP bit 6-41
direct operands 12-6
display interrupt 8-5, 9-13
display memory 9-18
display pitch 4-10,5-7,5-10,6-15,
6-16,9-18
DIVS instruction 12-63
DIVU instruction 12-65
dot rate 9-14
DPTCH register 5-10,6-15
DPYADR register 6-17
DPYCTL register 6-19
DPYINT register 6-23
DPYSTRT register 6-24
DPYTAP register 6-25
DRAM 6-11,11-5

Index-2

refresh cycles 6-11
refresh interval 6-46
refresh rate 6-11
DRAM refresh 11-11,11-12,11-25
DRAV instruction 12-67
draw and advance 7-10
DSJ instruction 12-70
DSJEQ instruction 12-71
DSJ NE instruction 12-73
DSJS instruction 12-75
DUDATE bits 6-19,6-20
DXV bit 6-19, 6-22
DYDX register 5-14

E
EI NT instruction 12-76
EMU instruction 12-77
emulation 2-10
enabling interrupts 12-76
ENV bit 6-19
EXG F instruction 12-78
EXGPC instruction 12-79
external interlaced video 9-17
external interrupts 8-3
external synchronization 9-15
external video 6 -19

F
FE bit 4-2
FEO bit 5-18
FE1 bit 5-18
field size 5-18, 5-19
fields 4-1, 4-2-4-5
addressing 4-2
alignment 4-3
extraction 4-2
insertion 4-2, 4-5
size 4-2
fill 7-5
FILL instruction 12-80, 12-84
font library 1 -12
foreground color register 5-16
FSO 4-2
FSO bits 5-18
FS1 4-2
FS1 bits 5-18
function select pins 2-5

G
general-purpose register files 1 -5, 5-25-17
GETPC instruction 12-89
GETST instruction 12-90
graphics instructions 12-26
graphics standards 1-2

H
halt latency 10-1 9
halt program execution 6-35
HCOUNT register 6-26
HCS 2-5, 10-2
HDO-HD15 2-6,10-2
HEBLNK register 6-27
HESYNC register 6-28
HFSO, HFS1 2-5,10-2
hidden states 13-2
HIE bit 6-40
HINT 2-6, 10-2
HIP bit 6-41
HLDA/EMUA 2-10
H LOS 2-5, 10-2
H LT bit 5-23, 6-3, 6-32, 6-35
HOLD 2-10
hold and emulation signals 2-4, 2-10
'R'I:DA/EMUA 2-10
HODS 2-10
RUN/EMU 2-10
hold interface 11 -18
hold request 11 -4
horizontal back porch 9-5
horizontal front porch 9-5
horizontal sync 2-9
horizontal timing 9-12
horizontal timing registers
HCOUNT 6-26, 9-4
HEBLNK 6-27, 9-4
HESYNC 6-28, 9-4
HSBLNK 6-29, 9-4
HTOTAL 6-39,9-4
horizontal video timing 9-6, 9-7
host interface 10-1, 10-24
bandwidth 10-22
data transfer 10-8
indirect accesses of local
memory 1 0-11
reads and writes 10-4
ready signal to host 10-8
registers 6-7

HSTADRH 10-3
HSTADRH register 6-30
HSTADRL 6-31,10-3
HSTCTL 10-3
HSTCTLH 6-32, 10-3
HSTCTLL 6-36, 10-3
HSTDATA 6-38,10-3
selection 10-2
signals 10-2
timing examples 10-5
host interface bus pins 2-3, 2-5
HCS 2-5
HDO-HD15 2-6
HFSO,HFS1 2-5
'RiNi 2-6
HLDS 2-5
HRDY 2-6

H'R'EAi5 2 -5
Fi1Ji5S 2-5

HWRITE 2-5
host interrupt 8-5
host read/write strobes 2-5
host-present mode 8-10,8-13
HRDY 2-6,10-2,10-8
HREAD 2-5,10-2
HSBLNK register 6-29
HSD bit 6-19
HSTADRH register 6-30
HSTADRL register 6-31
HSTCTLH register 6-32
HSTCTLL register 6-36
HSTDATA register 6-38
~ 2-9,6-22,6-26,9-3
HTOTAL register 6-39
~ 2-5,10-2
HWRITE 2-5, 10-2

I/O registers 1-6,6-1-6-52
addressing 6-2
at reset 6-3
host interface registers 6-7
interrupt interface registers 6-8
latency of writes 6-4
local memory interface registers 6-8
memory map 6-2
summary 6-5
video timing and screen refresh registers 6-9
IE bit 5-18
illegal opcode interrupts 8-9
illegal operand 8-5
Index-3

immediate operands 12-4
implied graphics operands 5-5
INC instruction 12-91
INClK 2-7,11-2
INCR bit 6-32,6-34,10-11
incremental algorithms 7 -10
I NCW bit 6-32, 6-35, 10-11
INC1 register 5-17
INC2register 5-17
indirect accesses of local memory 10-11
indirect branch 5-19
indirect operands 12-7, 12-8, 12-9,
12-10,12-11
in XV mode 12-11
with offset 12-8
with postincrement 12-9
with predecrement 12-10
input clock 2-7
instruction cache 1 -6, 5-20-5-25
cache disable 6-14
cache flush 6-33
cache hit 5-22
cache miss 5-22
cache replacement algorithm 5-21
disabling 5-24
downloading new code 5-23
flushing 5-23
lRU stack 5-21
operation 5-22
P flag 5-22
segment miss 5-22
segments 5-21
SSA register 5-21
subsegment miss 5-22
instruction set 12-1
addressing modes 12-4
arithmetic instructions 12-19
compare instructions 12-19
condition codes 12-31
graphics instructions 12-26
jump instructions 12-30
logical instructions 12-19
move instructions 12-20
operand formats 12-4
program control instructions 12-29
shift instructions 12-32
instruction words 5-20
INTENB register 6-40
interlaced display 9-25
interlaced video 9-11, 9-17
internal interrupts 8-5
interrupt interface

Index-4

registers 6-8
INTENB 6-40,8-3
INTPEND 6-41,8-3
interruptible instructions 7-8
interrupts 2-6,8-1-8-8
display interrupt 6-23,8-5,9-13
enable bit 5-18
external interrupts 8-3
host interrupt 8-5
host interrupt request signal 2-6
IE bit 5-18
illegal opcode interrupts 8-9
illegal operand 8-5
INTENB 6-40
internal interrupts 8-5
interrupt request pins 8-3
interrupt requests 6-37
INTIN bit 6-37
INTOUT bit 6-37
INTPEND 6-41
local interrupt request signals 2-8
nonmaskable interrupt 6-32, 6-33,
8-5
priorities 8-2, 8-5
processing 8-6
registers 8-3
RESET 2-11
stack operations 3-8
vector addresses 8-2
window interrupt 8-5
intersecting rectangles 7-3
INTIN bit 6-36,6-37
INTOUT bit 6-36,6-37
INTPEND register 6-12, 6-41

J
JAcc instruction 12-92
J Rcc instruction 12-94, 12-96
J U M P instruction 12-98
jump instructions 12-30

K
key features of the TMS3401 0

1 -3

LRDY

LADO-LAD15 2-8,11-2
LAL 2-7,11-2
LBL bit 6-32, 6-34
LCLK1,LCLK2 2-8, 11 -2
LCSTRT bits 6-24
line clipping 7 -29
LINE instruction 12-99
linear addressing 4-10
LlNT1,LlNT2 2-8,8-3,11-2
LMO instruction 12-108
LNCNT bits 6-17,6-24
local address/data bus 2-8
local memory interface 11 -1 , 11 -30
addressing mechanisms 11 -23
hold interface timing 11 -18
I/O register access cycles 11-13
internal cycles 11 -13
memory bus request priorities 11 -4
read cycle 11 -8
read-modify-write operations 11-15
registers 6-8
CONTROL 6-11, 11-3
CONVDP 6-15, 11-3
CONVSP 6-16, 11 -3
PMASK 6-43, 11 -3
PSIZE 6-45, 11-3
REFCNT 6-46, 11-3
register-transfer cycles 11-9
signals 11 -2
timing 11 -5-11-22
wait states 11 -1 6
write cycle 11 -7
local memory interface pins 2-4, 2-7 -2-8
CAS 2-7
DDOUT 2-7
i5EN 2-7
INCLK 2-7
LADO-LAD15 2-8
ill 2-7
LCLK1,LCLK2 2-8
LlNT1,LlNT2 2-8
LRDY 2-8
RAS 2-7
TR/OE 2-7
W 2-7
local read/write strobes 2-7
logical instructions 12-19
logical pixels 4-6

2-8, 11-2

MAX operation 7 -16
memory bus request priorities 11 -4
memory map 3-4
message buffers 6-36, 6-37
microcontrol ROM 1 -7
midpoint subdivision 7 -30
MIN operation 7-16
MMFM instruction 12-109
MMTM instruction 12-111
MODS instruction 12-113
MODU instruction 12-114
MOVB instruction 12-115,12-116,12117,12-118,12-119,12-120,12-121,
12-123,12-124
MOVE instruction 12-126,12-127,12128,12-130,12-132,12-134,12-135,
12-137,12-139,12-141,12-143,12145,12-147,12-149,12-151,12-153,
12-155,12-157,12-159,12-160
move instructions 12-20
M OVK instruction 12 -161
MOVX instruction 12-162
MOVY instruction 12-163
M PYS instruction 12-164
MPYU instruction 12-166
MSGIN bits 6-36
MSGOUT bits 6-36, 6-37
multiple-GSP systems 9-15

N
N bit 5-18
NEG instruction 12-168
NEGB instruction 12-169
NIL bit 6-19,6-22
NMI bit 6-32
non-branch 5-19
non interlaced video 9-9
nonmaskable interrupt 6-8, 6-32, 8-5
nonmaskable interrupt mode 6-33
NOP instruction 12-170
NOT instruction 12-171

Index-5

o
OFFSET register 4-12,5-11
on -screen memory 9-18
OR instruction 12-172
ORG bit 6-19,6-20
ORI instruction 12-173
outcode ;-30
output clocks 2-8

p
P flag 5-22
panning 9-25
PATTRN register 5-17
PBHbit 6-11,6-12
PBV bit 6-11,6-13
PBX bit 5-18
PC 5-19
pick window 7 -26
picture elements 4-6
pin descriptions 2-2
pinout 2-2
pitch 7-4
pitch conversion factors 4-12
PixBlt direction 6-13
PIXBLT instruction 12-174,12-179,
12-187,12-193,12-200,12-206
PixBlts 4-15, 7-4
pixel array 4-15
pixel block transfers 4-15, 7-4
pixel processing 6-13, 7 -15
pixels 4-1,4-6-4-10
addressing 4-6
on the screen 4-7
pixel size 6-45
PSIZE register 6-45
representation in a register 4-6
size 4-6
storage in memory 4-7
XV addressing 4-8
PIXT instructions 12-213, 12-215, 12218,12-220,12-222,12-224
plane mask 7 -12
plane masking 6-43
PMASK register 6-43
POPST instruction 12-227
postclipping 7 -29
PP bit 6-11
PPOP bits 6-13
preclipping 7-29
.
program control instructions 12-29
Index-6

program counter 1 -5, 5-19
PSIZE register 4-12,6-45
PUSHST instruction 12-228
PUTST instruction 12-229

R
RAS 2-7, 11 -2
REFCNT register 6-46
references 1 -11
register file A 5-2
register file B 5-3, 5-5-5-17
register-direct operands 12-6
related documentation 1 -12
relative branch 5-19
re lace operation 7 -18
RE ET 2-11,8-10-8-13
effect on cache 5-21
effect on instruction cache 8-11
effect on TMS34010 registers 8-12
effects on I/O registers 6-3
HLTbit 6-35
RETI instruction 12-230
RETS instruction 12-232
REV instruction 12-233
RINTVL bits 6-46
RL instruction 12-234,12-235
row address strobe 2-7
row and column addressing 11 -6
ROWAOR bits 6-46
RR bit 6-11
RUN/EMU 2-10

s
SAOOR register 5-6
scan line counter 6-17
screen orlgm 4-8,6-19,6-20
screen refresh 6-21,6-24,9-1-9-27
screen refresh enable 6-19
screen size limits 9-2
screen-refresh address 6-17
screen-refresh cycles 9-18
SOB 1-12
segment miss 5-22
self-bootstrap mode 8-10,8-13
self-modifying code 5-23
SETC instruction 12-236
SETF instruction 12-237
SEXT instruction 12-238
shift instructions 12-32

shift register transfer enable pin 2-7
shift register transfers 6-19
sign (N) bit 5-18
SLA instruction 12-239, 12-240
SLL instruction 12-241, 12-242
software development board 1 -1 2
software traps 8-9
source address register 5-6
source conversion factor 6-16
source pitch register 5- 7
SP 1 -6, 3-6, 5-2, 5-4
SPTCH register 5-7,6-16
SRA instruction 12-243, 12-244
SRE bit 6-19, 6-21
SRFADR bits 6-17,6-24
SRL instruction 12-245, 12-246
SRSTRT bits 6-24
SRT bit 6-19, 6-21
SSA register 5-21
ST 5-18
stack 3-6-3-11
multiple-register operations 3-8
operation during a subroutine 3-9
operation during interrupts 3-9
structure 3-7
32-bit register operations 3-8
stack pointer 5-2, 5-4
starting address of array 4-15, 7 -7
starting corner selection 7-7
status register 1 -5, 5-18-5-19
strobes 10-4
SUB instruction 12-247
SUBB instruction 12-248
SUBI instruction 12-249,12-250
SUBK instruction 12-251
subroutine calls 12-48, 12-49, 12-50
subsegment miss 5-22
subtract with saturation 7 -16
SUBXY instruction 12-252

T
T bit 6-11
tap point register 6-25
TEMP register 5-17
TR/QE 2-7, 11-2
transparency 7 -11
enabling (T bit) 6-12
TRAP 8-9
TRAP instruction 12-253
traps 8-9
two-dimensional arrays 4-15, 7-4

v
V bit 5-18
and window checking 7-25
VCLK 2-9, 9-3
VCOUNT register 6-23,6-48
VEBLNK register 6-49
vector addresses 8-2
vertical back porch 9-5
vertical front porch 9-5
vertical sync 2-9
vertical timing registers
VCOUNT 6-48,9-4
VEBLNK 6-49,9-4
VESYNC 6-50,9-4
VSBLNK 6-51,9-4
VTOTAL 6-52,9-4
vertical video timing 9-8-9-12
VESYNC register 6-50
video clock 2-9
video enable 6-19
video timing 9-1-9-27
video timing and screen refresh
display address 6-17,6-19
display interrupt 6-23
registers 6-9
DPYADR 6-17
DPYCTL 6-19
DPYINT 6-23
DPYSTRT 6-24
DPYTAP 6-25
HCOUNT 6-26, 9-4
HEBLNK 6-27,9-4
HESYNC 6-28, 9-4
HSBLNK 6-29,9-4
HTOTAL 6-39,9-4
VCOUNT 6-48,9-4
VEBLNK 6-49, 9-4
VESYNC 6-50,9-4
VSBLNK 6-51,9-4
VTOTAL 6-52,9-4
video timing signals 9-3
video timing signals 2-4, 2-9
BLANK 2-9
HSYNC 2-9
VCLK 2-9
VSYNC 2-9
VRAM 11-5
VRAMs 6-9, 9-18
bulk initialization 9-26
tap point address 6-25
VSBLNK register 6-51

Index-7

VSVNC 2-9, 6-22, 9-3
VTOTAL register 6-52

w
W

2-7,11-2
Wbit 6-11,6-12
\AJEND register 5 13
window checking 4-16, 6-12, 7 -25
window clipping 7-27
window end address register 5-13
window hit detection 7-26
window interrupt 8-5
window miss detection 7-27
window start address register 5-12
windows 5-12, 5-13
WEND register 5-13
WSTART register 5-12
WSTART register 5-12
WVE bit 6-40
WVP bit 6-41

x
XOR instruction 12-255
XORI instruction 12-256
XV addressing 4-8, 4-10, 4-11, 4-14,
5-14
benefits 4-11
DVDX register 5-14
format 4-11
OFFSET register 5-11
XV -to-linear conversion 4-12, 6-15,
6-16
X1 E bit 6-40
X1 P bit 6-41
X2E bit 6-40
X2P bit 6-41
X3E bit 6-40
X3P bit 6-41

z
Z bit 5-18
ZEXT instruction

Index-S

12-257

TEXAS

INSTRUMENTS
Printed in U.S.A., August 1988
1604899-9703

SPVU001A

Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:08:01 08:29:54-08:00 Modify Date : 2017:08:01 09:12:57-07:00 Metadata Date : 2017:08:01 09:12:57-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:cfcb6a4f-66b1-bc4f-a96a-b7504fbb9133 Instance ID : uuid:64ba042e-2641-584f-977a-a49db6f7c3f3 Page Layout : SinglePage Page Mode : UseNone Page Count : 664
EXIF Metadata provided by EXIF.tools

1988_TI_TMS34010_Users_Guide 1988 TI TMS34010 Users Guide

Navigation menu

Versions of this User Manual:

Views

Navigation