1988_Toshiba_TLCS 48_90_8_Bit_Microcontroller 1988 Toshiba TLCS 48 90 8 Bit Microcontroller
User Manual: 1988_Toshiba_TLCS-48_90_8_Bit_Microcontroller
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TOSHIBA AMERICA, INC.
Notice to Potential TLCS-90* Customers:
This Databook contains a preliminary Data Sheet for Toshiba's new TLCS-90 Series 8-bit
Microcontrollers. Although the Data contained therein is generally believed to be current, it is
recommended that you contact you local Toshiba Sales Person or Office to obtain the latest
Specs prior to any actual System Design.
Thus you will be ensured of having the latest Device Electrical Specs to incorporate into your
System Design Process.
* The TLCS-90 Series currently includes the following devices:
•
•
•
•
•
TM P90C840 N
TMP80C840F
TMP90C841 N
TM P90C841 N
TMP90C840E
Future TLCS-90 Series Devices will be added to this expanding Family.
a-BIT
MICROCONTROLLER
TLCS 48,90
Additional Literature- Available:
Literature Description
•
•
•
•
•
Microcomputer Products Summary
4-Bit Microcontroller
B-Bit Microcontroller
B-Bit Microprocessor
16-Bit Microprocessor'
• Speech Devices
• Micro Peripherals
Device Families
All CPU Products
TLCS-42. TLCS-4 7/470
TLCS-4B. TLCS-90
TLCS-ZBO. TLCS-85
TLCS-6BOOO
Speech Prod ucts
Other Micro Peripherals
Plus Various Development System Manuals
November 1988
INDEX
PART 1
TLCS-48 Series
PART 2
TLCS-90 Series
APPENDIX
(TLCS-90)
PART 1
TLCS·48
LSI DEVICES
TLCS-48 LSI DEVICE
TOSHIBA
CONTENTS
CONTENTS
TMP8()48A/TMP8035A, TMP8049A/TMP8039A ••••••••••••••••••••••••••••••• MCU48TMP8048A/TMP80C35A •••••••••••••••••••••••••••••••••••••••••.••••••••••••
35
TMP80C49A/TMP80C39A •••••••••••••••••••••••••••••••••••••••••••••••••••••
59
TMP80C50A/TMP80C40A •••••••••••••••••.•••.•••••••••••.•••••••••••••••••••
83
TMP8048PI/TMP8035PI
107
TMP8049PI-6/TMP8039PI-6 ••••••••.••••••••••••••••••••••••••••••••••••••••
137
TMP8243P/TMP8243PI
•••••••••••••••••••••••••••••.••••••••••••••••••••••••
167
•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
176
TJ:.-IP82C43P
MCU48-i
TMP 8048A/TMP 80 35A, TMP 8049A/TMP 80 39A
TOSHIBA
NMOS 8-BIT MICROCONTROLLER (TLCS-48)
TMP8048AP /TMP8035AP
TMP8049AP /TMP8039AP
TMP 804BAT /TMP 80 35 AT
TMP 8049AT /TMP 80 39AT
GENERAL DESCRIPTION
The TMP804BAP /TMP8049AP, from here on referred to as the TMP8048A except
in case of no need to specify each parts, is a single chip microcontroller
internal 8-bit parallel architecture.
The following basic architectural functions of a computer have been
included in a single chip; an 8-bit CPU, R&~ data memory, ROM program memory,
27 I/O lines and an 8-bit timer/event counter.
The TMP804BA is particularly efficient as a controller. It has extensive
bit handing capability as well as facilities for both binary and BCD arithmetic.
The TMP 8035A/TMP 8039A is the equivalent of a TMP 8048A/TMP 8049A wi thout
ROM program memory on chip. By using this device with external EPROM or RAM,
software debugging becomes easy.
The TMP 8048AP /TMP B035AP, TMP 8049AP /TMP 8039AP are packaged in a standard
40 pin Dual Inline Plastic Package.
The TMP 8048AT /TMP 8035AT, TMP 8049AT /TMP 8039AT are packaged in
standard type 44pin PLCC (Plastic Leaded Chip Carrier).
the JEDEC
FEATURES
·
•
•
·
1.36 us Instruction Cycle
All instruction 1 or 2 cycles
Over 90 instructions; 70% single byte
Easy expandable memory and I/O
Parts Number
TMP8048A
TMP B049A
TMPB03SA
TMPB039A
Program Memory (ROM)
1 k Byte
•
·
•
•
27 I/O lines
Interval Time/Event Counter
Single level interrupt
Single SV supply
Data Memory (RAM)
64
128
64
128
2 k Byte
MCU48-1
Byte
Byte
Byte
Byte
TMP 8048A/TMP 80 35A, TMP 8049A/TMP 80 39A
TOSHIBA
PIN CONNECTIONS (Top View)
TO
XTALI
XTAL2
RESET
SS
INT
EA
RD
PSEN
Vee (+5V)
Tl
P27
P26
P 2S
P24
P17
P16
PIS
P14
P13
P12
Pll
PIa
VDD(+SV)
PROG
P23
P22
WR
ALE
DBa
DBI
DB2
DB3
DB4
DBs
DB6
DB7
(OV)VSS
P21
P 20
P24
P17
P16
PlS
Pl4
EA
RD- ;.:
PSEN
WR
NC
!t:
NC
ALE
DBa
DBI
DB2
DB3
~
PI3
ru
P12
~
PlI
~
PIa
~..,
VDD
~Ln..cr-U)UO.-4N~~
COCOCOCOU'lZNNNNO
0000>
1l41l41l41l4c::
Il4
MCU48-2
TMP8048A/TMP8035A,TMP8049A/TMP8039A
TOSHIBA
PIN NAMES AND PIN DESCRIPTION
VSS (Power Supply)
Circuit GND potential
VDD (Power Supply)
+5V during operation Low power standby pin for TMP8048A RAM
VCC (Main Power Supply)
+5V during operation
PROG (Output)
Output strobe for the TXP8243P I/O exapnder
PlO-P17 (Input/Output) Port 1
8-bit quasi-bidirectional port (Internal Pullup
50 kohm).
P20-P27 (Input/Output) Port 2
8-bit quasi~bidrectional port (Internal Pullup = 50 kohm).
P20-P23 Contain the four high order program counter bits during an
external program memory fetch and serve as a 4-bit I/O expander bus for
the TMP 8243P •
DBO-DB7 (Input/Output, 3 State)
True~idirectional port which can be written or read synchronously using
the RD, WR strobes. The port can also be statically latched. Contains
the 8 low order program counter bits during an external program mem~
fetch, and receives the addressed instruction under the control of PSEN.
Also contains the address and data during an external RAM data store
instruction, under control of ALE, RD and WR.
TO
(Input/Output)
Input pin testable using the conditional transfer instructions JTO and
JNTO. TO can be designated as a clock output using ENTO CLK instruction.
Tl
(Input)
Input pin testable using the JTl and JNTI instruction. Can be designated
the event counter input using the timer/STRT CNT instruction.
INT
(Input)
External interrupt input. Initiates an interrupt if interrupt is
enabled. Interrupt is disabled after a reset. Also testable with
conditional jump instruction. (Active Low)
RD
(Output)
Output strobe activated during a Bus read. Can be used to enable data
onto the Bus from an external device. Used as a Read Strobe to External
Data Memory (Active Low).
WR
(Output)
Output strobe during a Bus write (Active Low). Used as a Write Strobe to
External Data Memory.
MCU48-3
TOSHIBA
TMP 8048A/TMP 8035A, TMP 8049A/TMP 8039A
BLOCK DIAGRAM
DBO- DB7
Oscillation
2
Mask ROM
1k X 8 (80W)
2k X 8 (8049'\)
(Program
Area)
6
'-----;.."".r I
Accumulator
Bit Test
RAM
64 X 8 (804M)
128 X 8 (8049,\)
Circuit
Control and Timing Circuit
XTAL
....::s
~
c
2
mn
XTAL 1
0
til
.......
n
"en III.,.,
.,0
'"
nI
til
nI
~
....
::s
~
C
""
rnT EA
........
O-\"I'l
::I ::s
"1 )(
C nI
"""1
"1
en
en
~~
c:
nI
~
nI
"1
enS
,., ....
nI >
~
nI ....
n 0-
'"
I
55 ALE P'S"EN RD WR PROG
en
,...
~~
....
nI
n "1
=rill
en
~
::s
00
~
III
~
~O-
en
"1
0
C"
III
til
til
til."
~
"1
"1
0
o
00
nI
~
C""1
S
---i'
~
~
en
.,
~
0
C"
en\"l'l
~~
o ~
Note 1)
The lower order 4 bits of
port 2 output latch are
used also for input/output operations with the
I/O expander.
Note 2)
The output latch of port
o is also used for
address output.
C"::s
nlOnI
.,
nI
en
MCU48-4
TOSHIBA
TMP 8048A/TMP 8035A, TM? 8049A/TMP 8039A
RESET (Input)
Active Low signal which is used to initialize the Processor.
during Power down.
ALE
Also used
(Outpu t)
Address Latch Enable. This signal occurs once during each cycle and is
useful as a clock output. The negative edge of ALE strobes address into
external data and program memory.
PSEN (Output)
Program Store Enable. This output Qccurs only during a fetch to external
program memory (Active Low).
SS
(Input)
Single Step input can be used in conjunction with ALE to "single step"
processor through each instruction when 55 is low the CPU is placed into
a wait state after it has completed the instruction being excuted.
EA
(Input)
External Access input which forces all program memory fetchs to reference
external memory. Useful for emulation and debug and essential for
testing and program verification. (Active High).
XTAL 1 (Input)
One side of crystal input for internal oscillator.
external source.
Also input for
XTAL 2 (Input)
Other side of crystal input.
FUNCTIONAL DESCRIPTION
1.
System Configuration
• The following system functions of the TMP8048A are described in detail.
(6) Stack (Stack Pointer)
Program Memory
(7)
(2) Data Memory
Flag 0, Flag 1
(3) I/O Port
(8) Program Status Word (PSW)
(9)
(4) Timer/Counter
Reset
(5)
(10) Oscillator Circuit
Interrupt Control Circuit
0)
(1)
Program Memory
• The maximum memory that can be directly addressed by the TMP8048A is
4096 bytes. The first 1024 bytes from location 0 through 1023
(TMP8048A) or the first 2048 bytes from location 0 to 2047 (TMP8049A)
can be internal resident mask ROM. The rest of the 3072 bytes or the
2048 bytes of addressable memory are external to the chip. The
TMP8035A and TMP8039A have has no internal resident memory; all memory
must be external.
MCU48-S
TOSHIBA
TMP8048A/TMP8035A,TMP8049A/TMP8039A
There are three locations in Program Memory of special importance.
Address
4095
Memo ry Bank 1
2048
2047
Memory Bank 0
Program Memory Area
• Location 0
Activating the Reset line of the processor causes the first instruction
to be fetched from Location O.
• Location 3
Activating the interrupt line of the processor (if interrupt enabled)
causes a jump to subroutine defined by address held in Location 3.
• Location 7
A timer / counter interrupt resul ting from a timer/counter overflow (if
enabled) causes a jump to a subroutine defined by address held in
Location 7.
• Program address 0-2047 and 2048-4095 are called memory banks 0 and 1 respectively switching of memory banks is achieved by changing the most
significant bit of the program counter (PC) during execution of an
uncoditional jump instruction or call instruction executed after using SEL
MBO or SEL MBI.
Reset operation automatically selects Bank O.
(2)
Data Memory
• Resident Data Memory (volatile RAM) is organized as 64 words (TMP8048A)
or 128 words (TMP8049A) by 8-bits wide •
• The first 8 locations (0 - 7) of the memory array are designed as
working registers and are directly addressable by several instructions.
By executing a Register Bank switch instruction (SEL RBI) locations 24
- 31 are designated as the working registers in palce of 0 - 7.
MCU48-6
TOSHIBA
TMP 8048A/TMP 8035A, TMP 8049A/TMP 8039A
Addre8S~------------~
121
Data Memory
32
31 -R-;;1~;;;'-Ba-;;kl-
24
RBI
23----------8 Level Stack
8
(16 byte)
1"R-;;i-;t~-; -B~;k-O-
o
RBO
Internal Data Memory Area
RAM locations 8 - 23 serve a dual role in that they contain the program
counter stack which is a stack 2 bytes wide by 8 levels deep.
These
locations store returning addresses from subroutines. If the level of
subroutine nesting is less than the permitted 8, you free up 2 bytes of
RAM for general use for every level of nesting not utilized.
• All
64 (TMP8048A)
or
128
(TMP8049A)
locations
are
indirectly
addressable through eitheF of two R&~ Pointer Registers which reside at
RO and R1 of the Register array.
The TMP8048A architecture allows extension of the Data Memory to 256
words.
(3)
Input/Output Ports
• The TMP8048A has 27
output.
These I/O
bidirectional lines
sequences when tested
I/O lines which can be used for either input or
I ines are grouped into 3 ports each having 8
and 3 "test" inputs which can after program
by conditional jump instructions.
• Ports 1 and 2 are each 8-bits wide and have identical characteristics.
Data written to these ports is statically latched and remains unchanged
unt i 1 rewri t ten.
As input ports these lines are non-lat ching, i. e • ,
inputs must be present until read by an input instruction.
• All lines of Ports 1 and 2 are called quasi-bidirectional because of a
special output circuit structure (illustrated in Figure 1). Each line
is continuously pulled to a +SV level through a high impedance
res is t i ve devi ce (SOkohm) wh ich is suffi cient to provide t he source
current for a TTL high level yet can be pulled low by a standard TTL
gate thus allowing the same pin to be used for both input and output.
I n order to speed up the "0" to "1" trans i t ion a low impedance device
(5kohm) is swi t ched in momentari ly whenever a "1" is wr i tt en to 1 ine •
When "0" is written to line a low impedance device overecomes the
pullup and provides TTL current sinking capability.
MCU48-7
TOSHIBA
TMP 8048A/TMP 80 35A, TMP 8049A/TMP 80 39A
ANt, ORt
+SV
+5V
SOkn
Internal ·Bus---1-..A--f 0
Q
D-Type
Flip-Flop
CLK
Write
SOkn I/O pins
Portl or 2
Q ~+----~
Puls~---+~--------------~
Inter Buffer
IN
Fig.l
Input/Output Circuit of Port 1, Port 2
• Reset initializes all lines to a high impedance "1" state.
• When external data memory area is not addressed during execution of an
internal program, Port 0 (DBO - DB7) becomes a true bidirectional port
(bus) with associated input and output strobes.
If bidirectional
feature not needed Bus can serve as either a statically latched output
port or a non-latched input port.
However, I/O lines of this port
cannot be intermixed.
• As a static port data is written and latched using the OUTL instruction
and inputted using the INS instruction these two commands generate
pulses on the corresponding RD and WR strobe lines.
• As a bidirectional port the MOVX instructions are used
write the port which generate the RD and ~ strobes.
to read
and
• When not being written or read, the Bus lines are in a high impedance
sta te.
(4)
Timer/Event Counter
• The 8-bit binary up counter can use either of the following frequency
inputs
(1)
Internal clock (1/480 of asc frequency)
•••••••••••••• Timer mode
MCU48-8
TOSHIBA
TMP 8048A/TMP 8035A, TMP8049A/TMP 8039A
(2)
External input clock form Tl terminal
(minimum cycle time 3 x ALE cycle)
.........•.• Event Counter mode
The counter is presettable and readable with two MOV instructions
wh i ch ti- ans fe r the con ten t of the ac cumula t or to the count er and vi ce
versa.
The counter content is not affected by a Reset and is
initialized solely by the MOVT, A instruction. The counter is stopped
-by a Reset or STOP TCNT instruction and remains stopped until started
by STRT T instruction or as an event counter by a srRT CNT.
One
started the counter will increment to its maximum count (FF) and
overflow to Zero continuing its count until stopped by a STOP TCNT
instruction or RESET.
The increment from maximum count to Zero (overflow) results in the
setting of an overflow flag and the generation of an interrupt request.
When interrupt acknowledged a subroutine call to Location 7 will be
initiated. Location 7 should store the starting address of the timer
or counter service routine. The state of the overflow flag is testable
with the conditional Jump (JTF). The flag is reset by excuting a JTF
or by RESET.
Figure 2 illustrates the concept of the timer circuit.
XTAL/lS
1/32
Pre-scaler
Cleared on Start Timer
JTF Instruction
8-Bi t Timer/
STOP TCNT 0
r-------~Edge
Detector
Counter
IT
Read/Write Enable
Timer In te rrupt
Request Flip-Flop
INT
Titre r Int e rrupt Enab 1 e
Fig. 2
Concept of Timer Circuit
MCU48-9
TOSHIBA
TMP 8048A/TMP 80 35A, TMP 8049A/TMP 8039A
Re se t
Conditional Jump Logic
S
JTF
Instruction
Timer
Flag F-F
>--+-_01 R
---:L~
Timer Overflow
--------~~s
Q~----_01
Timer
Overflow
Timer Interrupt
Execution------~~
R F-F
RETR
Reset
tion
INT pin
r---~:;--...,External
CLK
ALE
Q
interrupt Recognized
Last cycle
of Instruct
CLR
EN I
N TCl:T 1
S
Instruction
Instruction
~
Q
~
... ...
~~~
Execution of Interrupt Call Instruction
R~.s~
Reset----~~----------------~
DIS TCNTl
Instruction
Fig. 3
(5)
Instruction
Concept of Interrupt Control Circuit
Interrupt Control Circuit
• There are two distinct types of Interrupts in the TMP8048A.
(1)
External Interrupt from the INT terminal
(2)
Timer Interrupt caused by timer overflow
MCU48-l0
TOSHIBA
TMP 8048A/TMP 80 35A, TMP 8049A/TMP 8039A
• The interrupt system is single level in that once an interrupt is
detected all further interrupt requests are ignored until execution of
an RETR (which should occur at the end of an interrupt service routine)
reenables the interrupt logic.
· An interrupt sequence is initiated by applying a low level "0" to the
INT pin..
INT is level triggered and active low which allows "Wire
Gring" of several interrupt sources.
The interrupt level is sampled
every machine cycle during ALE and when detected causes a "jump to
·subroutine" at Location 3.
As in any call to subroutine, the Program
Counter and Program Status Word are saved in the stack.
• When an overflow occurs in the internal timer/event counter an
interrupt request is generated which is reserviced as outlined in
previous paragraph except that a jump to Location 7 is used instead of
3.
If INT and times overflow occur simultaneously then external
request 1Nf takes precedence.
If an extra external interrupt is needed in addition to INT this can be
achieved by enabling the counter interrupt, loading FFH in the counter
(one less than the terminal count), and enabling the event counter
mode. A "1" to "0" transition on Tl will cause an interrupt vector to
Location 7.
The interrupt service routine pointed to be addresses in Location 3 or
7 must reside in memory between a and 2047, i.e., Bank O.
Figure 3 illustrates the concept of the interrupt control circuit.
(6)
Stack (Stack Pointer)
• An interrupt or Call to subroutine causes the contents of the program
counter to be stored in one of the 8 register pairs of the Program
Counter Stack.
The pair to be used is determined by a 3-bit stack
pointer which is part of the Program Status Words (PSW explained in
section (8)). Data RAM locations, 8 through 23 are available as stack
registers and are used to store the program counter and 4-bits of PSW
as shown in the figure.
The stack pointer when initialized points to RAM location 8 and 9. The
first subroutine jump or interrupt results in the program counter contents being transferred to Locations 8 and 9.
Then the stack pointer
is incremented by one to point to Locations 10 and 11. Eight levels of
subroutine are obviously possible.
· At the end of a subroutine signalled by a RET or RETR causes the stack
pointer to be decremented by one and the contents of the resulting pair
to be transferred to the Program Counter.
MCU48-11
TOSHIBA
TMP 8048A/TI1P 80 35A, TMP 8049A/TMP 80 39A
,
I
7
23
I
I
22
I
21
,
I
6
3
,
20
19
18
17
16
15
14
2
I
I
I
13
1
I
I
I
I
5
I
I
I
,
4
I
I
,,
I
:
12
I
11
,
10
I
1
I
I
PSW
, PCS'" 11
9
PCD'" 3
8
o --------+--------PC4'" 7
I
1
Stack
Pointer
(7)
RAM
Address
Flag 0, Flag 1 (FO, Fl)
• The TMP8048A has two flags FO and Fl which are used for conditional
jump. These flags can be set, reset and tested with the conditional
jump instruction JFO.
FO is a part of the program status word (PSW) and is saved ln the stack
area when a subroutine is called.
(8)
Program Status Word (PSW)
. An 8-bit status word which can be loaded to and from the accumulator
exists called the Program Status Word (PSW). The PSW is read by a MOV
A, PWS and written to by a MOV PSW, A. The information available in
the PSW is shown in the diagram below.
MCU48-12
TOSHIBA
TMP 8048A/TMP 8035A, TMP 8049A/TMP 8039A
Stack Pointer
/
I C IAC I FO I BS 11 I S2 I Sl I SO
MSB
I
II
' _ _ _ _ _ 11
Saved in stack area
at the time of Subroutine Call.
Bits 0 - 2
Bit 3
Bit 4
LSB
Spare ("1" during Read)
Stack Pointer Bits (SO, 51, 52)
Not used ("1" level when read.)
Working Register Bank Switch Bit (BS)
o
==
Bank 0
1 == Bank 1
Bit 5
Bit 6
Flag 0 (FO)
Auxiliary Carry CAC) carry bit generated by an ADD
instruction and used by the decimal adjust instruction
DA, A (Ae)
Bit 7
(9)
Carry (C) flag which indicates that the previous operation has resulted in the accumulator. (C)
Reset
• The reset input provides a means for initialization of the processor.
This Schmitt trigger input has an internal pullup register which in
combination with an external luF capacitor provides an internal reset
pulse sufficient length to guarantee that all internal logic is
initialized.
RESET
MCU48-13
TOSHIBA
TMP 8048A/TMP 8035A, TMP 8049A/TMP B039A
If the pulse is generated externally the reset pin must be held at ground
(~O.8V) for at least lOmS after the power supply is within tolerance •
. Reset performs the following functions within the chip:
(i)
(ii)
( iii)
(iv)
(v)
( vi)
(vii)
(vi ii)
(ix)
(x)
(xi)
Sets PC to Zero.
Sets Stack Pointer to Zero.
Selects Register Bank O.
Selects Memory Bank O.
Sets BUS (DBO - DB?) to high impedance state. (Except when EA=5V)
Sets Ports 1 and 2 to input mode.
Disables interrupts (timer and external).
Stops Timer.
Clears Timer Flag.
Clears FO and Fl.
Disables clock output from TO.
(10) Oscillator Circuit
TMP8048A can be operated by
the external clock input
crystal oscillator as shown below.
in addition to
+5V
XTAL 1
XTAL 1
XTAL Z
----~h---~----y
XTAL 2
(a) Crystal Parameters and External Capacitance
The frequency of the oscillator will be calculated from the following
formula.
f -
(1+CO/2{CL+C»/2n~
Load Capacitance~L
CL=(Cl+Cfl)(C2+Cf2)/«Cl+Cfl)+(C2+Cf2»
Cfl
Input Capacitance (4pF Typ.)+Stray Capacitance (less than SpF)
Cf2 : Output Capacitance(6pF Typ.)+Stray Capacitance (less than SpF)
MCU48-14
TOSHIBA
TMP 8048A/TMP 803SA, TMP 8049A/TMP 8039A
However the recommended value in the following table will be used
better by the reason of the start of the oscillation will depend on the
Equivalent Series Resistance Rl and the External Capacitances Cl+Cfl,
C2+Cf2.
Frequency
f(MHz)
11
11
10
10
Eq~ivalent
External Capacitance
Cl=C2(pF)
Series Res.
R(ohm)
Recommended Typical
Value
Allowance
25
30
25
30
30
40
40
80
50
80
100
150
100
200
400
500
800
8
8
6
6
5
5
4
4
3
3
2
2
1
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
5 to
5 to
5 to
5 to
5 to
5 to
5 to
5 to
5 to
5 to
5 to
5 to
5 to
5 to
5 to
5 to
10 to
10
10
10
10
15
10
20
10
20
15
15
10
20
15
25
15
25
17
15
20
17
25
20
35
17
40
o
25
30
20
40
25
40
~
---r-
•
·
7777
I
(b) Ceramic Resonator and External Capacitance
Frequency
f(MHz)
3 to 11
1 to
3
External Capacitance
Recommended Value
C1=C2 (pF)
33
100
C
2.
C f2 :
25
40
Basic Operation and Timing
The following basic operations and timing are explained
(1) Instruction Cycle
(2) External Memory Access Timing
(3) Interface with I/O Expander TMP8243P
(4) Internal Program Verify (Read) Timing
(5) Single Step Operation Timing
(6) Low Power Stand-by Mode
MCU 48-15
··
·
·
·
·
·
7777
----- .. ---i
I
TOSHIBA
(1)
TMP8048A/TMP8035A,TMP8049A/TMP8039A
Instruction Cycle
• The instruction of TMP8048A are executed in one or two machine cycles,
and one machine cycle contents of five states.
Fig. 4 illustrates its relationship with the clock input to CPU.
•
~2
clock shown in Fig. 4 is derived to outside by ENIO CLK instruction.
• ALE can be also used as the clock to indicate the machine cycle as well
as giving the external address latch timing.
(2)
External Memory Access Timing
(i) Program Memory Access
• TMP8048A programs are executed in the following three modes.
(1) Execution of internal program only.
(2) Execution of both external and internal programs.
(3) Execution of external program only.
The external program memory is accessed (instructions are fetched)
automatically when the internal ROM address is exceeded in mode (2) and
from initial start address 0 in mode (3).
• In the external program memory access operation, the following will
occur
• The contents of the 12-bit program counter will be output on BUS(DBO
- DB7) and the lower 4-bits of Port 2.
Address Latch Enable (ALE) will indicate the time at which address is
valid. The trailing edge of ALE is used to latch the address
externally .
• Program Store Enable (PSEN) indicates that an external instruction
fetch is in progress and serves to enable the external memory device.
Bus (DBO - DB7) reverts to Input mode and the processor accepts its
8-bit contents as an Instruction Word.
• Figure 5 illustrates the timing.
(ii) Access of External Data Memory
• In the extended data memory access operation during READ/WRITE cycle
the following occurs
The contents of RO Rl is output onto BUS (DBO - DB7).
ALE indicates address is valid. The trailing edge of ALE is used to
latch the address externally.
A read RD or write WR pulse on the corresponding output pins
indicates the type of data memory access in progress. Output data
valid at trailing edge of WR and input data must be valid at trailing
edge of RD.
Data (8-bits) is transferred over BUS.
MCU48-16
TOSHIBA
XTALl
TMP 8048A/TMP 8035A, TMP 8049A/TMP 8039A
J np lit
(6MHz)
4>1
(2MHz)
Generated
internally 4>2
__---.In'-__ n
State
....J
2
Decode
1
Instruction
.Fetch
1 State
n
n
3
4
Execution
Execution
1
Execution
1 Cycle
~
ALE
(400kHz)
Fig. 4
Next Address Latch Timing
Instruction Cycle Timing
Address
Address
P20 - P23
n
5
Address
DBC - On7
ALE
\
Fig. 5
L
Timing of External Program Memory Access
MCU48-17
TOSHIBA
TMP 8048A/TMP 80 35A, TMP 8049A/TMP 80 39A
Program Address
Program Address
Data Address
DBO - DB7
InSLruction
ALE
RD (WR)
I
\
PSEN
I
\
r
\
External Data Memory Access lnstt'uctio,n
Suggest we have two
ALE
dia~rams
r \ Read
----1
\-------------------
ALE
BUS
BUS
\
Fig. 6
,-
WR
n
Write
§----<
\
Timing of Accessing External Data Memory
MCU48-18
Data
>--
,-
TMP 8048A/TMP 8035A, TMP 8049A/TMP 8039A
TOSHIBA
• Figure 6 illustrates the tlmlng of accessing the external data memory
during execution of external program.
(3)
Interface with I/O Expander (TMP8243P)
. The T~8048A I/O can be easily expanded using the TMP8243 I/O Expander.
This device uses only the lower half 4-bits of Port 2 for communication with the T~8048A. The TMP8243 contains for 4-bit I/O ports which
serve as extensions of on~ chip I/O and are addressed as Ports (4-7).
All communication takes place over the lower half of port 2 (P20 - P23)
with timing provided by an output pulse on the PROG pin. Each transfer
consists of two 4-bit nibbles the first containing the "OP Code" and
port address and second containing the actual 4-bits of data.
EA
+12V
o~r------------------------------------------------------
mET
OV
------------~!~/----~~
ALE
DBO - DB7
P20. P21
,";
J(
Input of Internal
ROM Address
Output of Internal
ROM Data
Input of Internal
ROM Address
Input of Internal ROM Address
Fig. 7
Input of Internal
ROM Address
Timing of Reading Internal Program Memory
5V
10K
SV
SV
n
s o t-----74
JO-........- - - t T
R
Q
AtE
Fig. 8(a)
Single Step Circuit
MCU48-19
TOSHIBA
TMP 8048A/TMP 8035A, TMP 8049A/TMP 8039A
Reading of Internal Program Memory
The processor is placed in the READ mode by applying +12V to the EA pin
and OV to the RESET pin.
The address of the location to be read is
then applied to BUS and the low order 2 or 3 bits of Port 2.
The
address is latched by a 0 to 1 transition on RESET and the high level
causes the contents of program memory location addressed to appear on
the eight lines of BUS.
Figure 7 illustrates the timing diagram for this operation.
(5)
Single Step Operation.
• A single step feature useful for debug can be implemented by utilizing
a circuit shown in Figure 8 (a) combined with the 5S pin and ALE pin.
• A D-type flip flop with set and reset is used to generate 55.
In the
run mode S:S is held high by keeping the fIiE-flop set. To enter single
step, set is removed allowing ALE to bring 55 low via reset input. The
next instruction is started by clocking a "1" into the FF which will
not appear on 55 unless ALE is high removing reset. In response to 5S
going high the processor begins an instruction fetch which brings ALE
low resetting FF and causing the processor to again enter the stopped
state.
• The timing diagram in this case is as shown in Figure 8 (b). (EA=5V)
(6)
Lower Power Stand-by Mode
• The Lower TMP8048A has been organized to allow power to be removed from
all but the volatile, 64 x 8 or 128 x 8 data RAM array. In power down
mode the contents of data ruu~ can be maintained while drawing typically
10 - 15% of normal operating power requirements.
· vee
serves as the 5V supply for the bulk of the TMP8048A while the VDD
supplies only the RAM array. In standby mode vee is reduced to OV but
VDD is kept at 5V. Applying a low level to reset inhibits any access
to the RAM by the processor and guarantees that ~~ cannot be inadvertently altered as power is removed from vee.
ss
I
\
\
ALE
/
Instruction Input
DBO - DB7
P20-P23
Address (PC)
Address (PC)
>-0
X
<
X
i
i
I
I
For two
'-----------.j lnst
ruct ion
Address (PC+l)
Address (pC+l)
Port20 - 23
Data
Fig. 8(b)
Single Step Operation Timing
MCU48-20
TOSHIBA
TMP 8048 A/TMP 8035 A, TMP 8049 A/TMP 8039 A
INSTRUCTION
ACCUMULA TOR INSTRUCTION
I Mnemonic
I
I ADD A,Rr
I
IADD A,~Rr
I
I ADD A,ifData
I
IADDC A,Rr
I
I ADDC A,@Rr
I
I
I ADDC A, iFData
I
I ANL A, Rr
I
I ANL A,@Rr
I
I
I
I
I
1
I
IANL A,iFData I
I
I
ORL A,Rr
I
1
I
ORL A,@Rr
I
I
ORL A,iFData I
I
XRL A, Rr
1
I
XRL A,@Rr
I
I
XRL A, 4FDat a I
I
INC A
DEC A
CLR A
CPL A
IDA A
I
I SWAP A
I
I
I
I
I
I
I
I
I
I
I
Instruction Code
D71D61051041031D21Dli00
01 11 11 01 11 rl rl r
I
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I
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I
01 11 11 01 01 01 01 r
I
I I I I I
I
01 01 01 01 01 01 11 1
d71d61dSld41d31d21dlidO
01 1 I 1 I 1 I 1 I r I rl r
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01 11 11 1101 01 01 r
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01 01 01 11 01 01 11 1
d71d61dSld41d31d21dlidO
01 11 01 11 11 rl rl r
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I
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I
I
01 11 01 11 01 01 01 r
I
1
1
1
J I
I
01 1 I 01 1 I 01 01 1 I 1
d71d61dSld41d31d21dlidO
ul 11 01 01 11 rl rl r
I
I I I I I I
I
01 11 01 01 01 01 01 rl
I
I
I
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01 11 01 01 01 01 11 11
d71d61dSld41d31d21dlidOI
11 11 01 11 11 rl rl rl
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I I I
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11 11 01 11 01 01 01 rl
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01 11 01 01 01 01 11 11
d71d61dSld41d31d21d11dOI
01 01 01 11 01 11 11 11
01 01 01 01 01 11 11 11
01 01 1 I 01 01 1 I 1 I 1 I
01 01 11 11 01 11 11 11
01 11 01 11 01 11 11 11
I
I
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I
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01 1 I ot 01 0 I 1 I 1 I 1 I
I I I I I I I I
I I I 1 I I I I
Operation
IBytes
I
(A)(-(A)+(Rr)
I 1
r = 0 - 7
I
(A)(-(A)+«Rr))
I 1
r = 0,1
I
(A)(-(A)+Data
I 2
I
(A)(-(A)+(Rr)+(C) I 1
r = 0 - 7
I
( A) ( - ( A) + ( (Rr ) )
I 1
+(C)
I
r = 0,1
I
(A)(-(A)+Data+(C) I 2
1
(A)(-(A)and(Rr)
r =0 - 7
(A)(-(A)and«Rr))
r = 0,1
(A)(-(A)and Data
1
(A)(-(A)or(Rr)
r =0 - 7
(A) (-(A) or «Rr))
r = 0,1
(A)(-(A)or Data
1
(A)(-(A)Eor(Rr)
r =0 - 7
(A)(-(A)Eor«Rr)) I
r = 0,1
I
(A)(-(A)Eor Data I
1
1
2
ICyclesl
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1
MCU48-21
(-
I
1
1
I
2
1
2
I
(A)(-(A)+l
(A)(-(A)-l
(A)(-O
(A)(-NOT (A)
Decimal Adjust
Accumulator
(A4-7)->(AO-3)
I
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1
1
1
1
1
1
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2
1
1
2
1
1
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1
1
1
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Flagl
CIACI
0I 0I
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0I 0I
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0 I 0 I
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0 I 0 I
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0 I 0 I
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0 I 0 I
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-I -I
1
I
-I -I
I
1
-I -I
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-I -I
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-I -I
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-I -I
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-I -j
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-I -I
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-I -I
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-I -I
-I -I
-I -I
-I -I
01 -I
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-I -I
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TOSHIBA
I Mnemonic
I
IRL A
I
I RLC A
I
I
I
IRR A
I
I
I RRC A
I
I
I
TMP 8048A/TMP 8035A, TMP 8049A/TMP 8a39A
Instruction Code
I
071061051041031021011001
111111 al alII 11 11
I I I I I I I I
11 11 11 11 alII 11 11
I I I I I I I I
I I I I I I I I
I I I I I I I I
01 11 11 11 01 11 11 11
I I I I I I I I
I I I I I I I I
alII 11 al alII 11 11
I I I I I I I I
I I I I I I I I
I I I I I I I I
Operation
(An +1) <- (An)
n= a - 6
(An+ 1) <-(An)
n= a - 6
(C)<-(A7)
(Aa)<-(C)
(An)<-(An+l)
n =a - 6
(An <-(AO)
(An)<-(An+l)
n = a - 6
(C)<-(AO)
(A7)<-(C)
IBytes
I
I 1
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I 1
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I 1
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I 1
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ICyclesl Flagl
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ICTACI
1 I -I·-I
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I I I
1 I -I -I
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I I I
I I I
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I I I
1 I -I -I
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I I I
I
I I I
1 I -I -I
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I I I
I
I I I
I
I I I
Input/Output Instruction
Operation
IBytes
I Instruction Code
I
1071061051041031021011001
I
I al 01 01 alII al pi pi (A)<-(Pp)
I 1
I I I I I I I I I p = 1, 2
I
I al alII 11 11 al pi pi (Pp)<-(A)
I 1
I I I I I I I I I p = 1, 2
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I 11 al alII 11 al pi pi (Pp)<-(Pp)and Datal 2
Id71d61d51d41d31d21dlidOI p = 1, 2
I
I 11 01 al alII al pi pi (pp)<-(Pp)or Oatal 2
Id71d61d51d41d31d21dl1dal p = 1, 2
I
I al al al alII al 01 01 (A)<-(BUS)
INS A,BUS
I 1
OUTL BUS ,A
101 al al 01 al 01 11 01 (BUS)<-(A)
I 1
ANL BUS, iftoata 11 al alII 11 al 01 al (BUS)(Rr )
<-I I I I I I I I
I I I I I I I I r =0 - 7
oI 0 I 1 I 0 I a I 0 I 0 I r I (A) -- >( (Rr ) )
<-I I I I I 1 I I
I I I I I I I I r = 0, 1
nl alII 11 01 al 01 rl(AO-3)-->«RrO-3))
<-I I I I I I I I
I I I I I I I I r = 0, 1
11 01 01 01 al al al r I (A)<--«Rr))
I I I I I I I I r = 0, 1
11 01 01 11 01 al al rl «Rr))<--(A)
I I I I I I I I r = a, 1
11 alII 01 al alII 11 (p CO-7 ) <-- (A)
I I I I I I I I (A) <-- «PC))
11 11 11 al al alII 11 (p CO-7) <-- (A)
I I I I I I I I (PC8-11) <--aal1
I I I I I I I I (A)<--«pc))
MCU48-2S
IBytes
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I 1
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I 1
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I Z
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I 1
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I 1
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I Z
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I Z
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I 1
I 1
I 1
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ICyclesl
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Flagl
CIACI
-I -I
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1
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-I -I
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-I -f
I I
-I -I
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-I -I
-I -I
-I -I
I I
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-I -I
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-I -I
I I
I I
-I -I
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-I -I
I I
-I -I
I 1
-I -I
I I
I I
TOSHIBA
TMP 8048A/TMP 8035A, TMP 8049A/TMP 8039A
Timer/Counter Instruction
I
Mnemonic
Instruction Code
I
Operation
IBytes ICyclesl Flagl
__________o_7~1-0-6~10~5~10-4~1~0~3~10-2~1-0-11~0~0~1~~~~______~I--~~I__--_TI_C~I-A-CI
I MOV A, T
a I 1 I 0 I 0 I 0 I 0 I 1 I 0 1(A) <-- (T )
1 I
1 I -I - I
I MOV T, A
a I 11 11 a I 0 I 0 I 11 0 I (T) <-- (A)
1 I
1 I -I -I
ISTRT T
01 11 01 11 01 11 01 11Counting is
1 I
1
I -I -I
I
I
I
I
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I
Istarted in the
I
I
I
I
I
I
I I I I I I I timer mode
I
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I STRT CNT
a I 11 a I 0 I 0 I 11 0 I 11 Count ing is
1 I
1
I -I -I
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1st art ed in the
I
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I ev.ent counter
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Imode
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a I 11 11 0 I 01 11 0 I 11 Stop both time
1 I
1 I -I -I
I STOP TCNT
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I I accumulation and
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I event count ing
lEN TCNTI
01 01 11 01 01 11 01 11Timer interrupt
1 I
1 I -I -I
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I I I is enab led
I
I
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I
IDIS TCNT1
01 01 11 11 01 11 01 11Timer interrupt
1 I
1
I -I -I
I __________~~I~I---~I~I--~I~1__1~~ll~·s~d~is~a~b~l~ed~____~____~I_____~I~I__ 1
Control Instruction
Mnemonic
EN I
OIS I
SEL RBO
SEL RB1
SEL MBO
SEL MB1
ENTO CLK
NOP
Instruction Code
I
Operation
IBytes ICyclesl~
071061051D4103102011001
I
I ci AC
I
1 I
01 01 01 01 01 1 0 11External interrupti
1
I -I lis enabled
I
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01 01 01 11 01 1 0 11External interrupti
1 I -I lis disabled
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11 11 01 01 01 1 0 11 (BS)<-- 0
1 I -I I
1 I
11 11 01 11 01 1 0 11 (BS)<-- 1
1
I -I I
1 I
11 11 11 01 01 1 0 11 (OBF)<-- 0
1 I -I I
1 I
1 I 1 I 1 I 1 I 01 1 0 11 (OBF)<-- 1
1 I -I I
1 I
01 11 11 11 01 1 a liTO is enabled to
1
I -I lact as the clock
I
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loutput
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01 01 01 01 01 0 a OINo operation
1 I
1 I-I
MCU48-26
TOSHIBA
TMP8048A/TMP803SA,TMP8049A/TMP8039A
I SYMBOL I
ITEM
I
RATTING
----_v_DD____~I-v-DD--S-u~p~p~ly~V-o-l-t-a~g-e-(~w_i_t_h__
re_s~p_e_c~t__
to__G_ND
__~(-V-SS~)~)----~I--O-.-S-V-t_o__+_7_V___
Ivcc
IVINA
IVINB
IPD
ITSOLDER
ITSTG
ITOPR
Ivcc Supplv Voltage (with respect to GND (VSS»
IInput Voltage (Except EA)
IInput Voltage (Only EA)
IPower. Dissi ation (Ta = 70'C)
Soldering Tern erature (Solderin Time 10 sec)
Storage Temperature
/Operating Temperature
I-o.sv to +7V
I-O.SV to +7V
I-o.sv to +13V
I
I.SW
I
260'C
I-ss'c to IS0'C
I O·C to 70'C
DC CHARACTERISTICS
TA=OoC to 70°C, VCC=VDD=+SV~10%, VSS=OV, Unless Otherwise Noted.
I SYMBOL
IVIL
IVIH
I
I
IInput Low Voltage
IInput High Voltage
I (Except XTALl,XTAL2,RESET
ITEST CONDITIONSIMIN.ITYP. IMAX. I UNIT I
I
I-o.SI - I 0.81
V I
I
I 2.01
I vcci
V I
I
I
I
I
I
I~V~IH-l--~I~I-n-pu-t~H~i-g-h-V-o~l~t-a-g-e~--------~I------------~1--3-.8~I--~-v-c-c-I~---v I
1______~I(~XT--AL-l~,-X-TA-L-2~,-RE-S-E-T~)~~----__I~----------~I~~I~~~--~I____ I
I VOL
IOutput Low Voltage (BUS)
IIOL=2.OmA
I - I
0.451
V I
IVOLl
IOutput Low Voltage
IIOL=I.8mA
I - I
0.451
V I
I______~I(~M~,-W-R~,-P-S-EN~,~&-E~)~--~----~I__________~I--~I--~--~I----I
IVOL2
IOutput Low Voltage (PROG)
IIOL=I.OmA
I - I
0.451
V I
IVOL3
IOutput Low Voltage
IIOL=I.6mA
I - I
0.4sl
V 1
I
I (For other output pins)
I
I
I
I
I
I-V-OH----~I~O-u-tp-u-t--H~i-gh~V-o~l-t~a-ge~(~B~U-S~)----~I-I-OH-=---4-0-0-u-A----~1--2-.4-1~--~--~I-----V I
IVOHI
IOutpu~Hi~oltage
I IOH=-IOOuA
I 2.41
- I
V I
I
I (M, WR, PSEN, &E)
I
I
I
I
I
I~V-OH-2--~I-O-u-tp~u-t~H~i-gh--V~o~l-t-a-g~e----------~I-I-O-H=---4-0-u-A----~1--2-.4~1---~I-----~I----V I
1______~I~(-F-or--o-t-h~e-r-o~u-t~p-u-t-p~l-·n-s~)------~I____________~I----I~--~I--~I--___ I
I
I
I
I
I
I
I
I
JILl
IInput Leak Current (T1, INT)
Ivss ~ VIN ~ vcci - I - I +101 uA I
I_____~I------------__- -__-----~I---------__---~I---~I---~I-----~I---_I
IIL11
IInput Leak Current
IVSS+0.4S<
<:
::
C'J
..;.
20
z
~____________5_1~._3~~f~A~X~~________________~
i
1 5. 24
J
± 0.25
I
\
1t
\ ' - -_ _ _ _-J
,,'
"
0.5 ± 0.15
1. 4
2.54 ±0.25
± 0.15
~
Note: 1. This dimension is measured at the center of bending point of leads.
2. Each lead pitch is 2.54mm, and all the leads are located within
+0.2Smrn from their theoritical positions with respect to No.1 and
No .40 leads.
MCU48-33
TOSHIBA
TMP 8048A/TMP 8035A, TMP 8049A/TMP 8039A
OUTLINE DRAWING
TMP 8048AT /TMP 80 35AT, TMP 8049AT /TMP 80 39AT
PRELIMIN AR Y
Unit in mm
6
40
1 44
o
7
39
29
17
28
17.52::0.12
~
16.6 TYF.
lr-#l±O.l
I
~_I~l±O.l
f--
.j j}.Z7 TYJ ;
N
o
+t
0"-
r-
15.76 TYP.
N
0
MCU48-34
TOSHIBA
TMP 80 C48AP / -6, TMP 80 C35 AP / -6, TMP 80 C48AF / -6,
TMP80C48AT,TMP80C35AT
8-BIT SINGLE-CHIP MICROCOMPUTER
TMPBOC48AP /TMP80C48AP-6
TMP80C35AP /TMP80C35AP-6
TMP80C48AF/TMP80C48AF-6
TMP80C48AT/TMP80C35AT
GENERAL DESCRIPTION
The TMP 80 C48A is a single chip mi crocomputer fabri ca ted in Si 1 i con Gat e Q10S
technology which provides internal 8-bit parallel architecture.
The following basic architectural functions of a computer have been included
in a single chip; an 8-bit CPU,
64 x 8 RAM data memory, lK x 8 ROM program
memory, 27 I/O lines and an 8-bit timer/event counter.
The TMP80C48A is particularly efficient as a controller. It has extensive bit
handling capability as well as facilities for both binary and BCD arithmetic.
The TMP80C35A/-6 is the equivalent of a TMP80C48A/-6 without ROM program
memory on chip.
By using this device with external EPROM or RAM, software
debugging becomes easy.
The TMP80C48AP/-6 and TMP80C35AP/-6 are 1n a standard Dual Inline Package.
The TMP80C48AF/-6 is in a 44-pin Flat Package.
The TMP80C48AT and TMP80C35AT are packag~d in the JEDEC standard type 44pin
PLCC (p las t ic Leaded Ch ip Carrier)
FEATURES
.TMP80C48AP/TMP80C35AP/TMP80C48AF/
TMP80C48AT/TMP80C35AT
l.36~s Instruction Cycle Time
O·C to 70·C, 5V ± 10%
• TMP80C48AP-6/TMP 80C3SAP -6/TMP 80 C48AF-6
2.S ~s Instruction Cycle Time
-40·C to 8S·C, SV ± 20%
• Software Upward Compatible with
TMP8048AP/INTEL's 8048
• HALT Instruction (Additional Instruction)
• lK x 8 masked ROM
.64x8RAM
• 27 I/O lines
• Interval Timer/Event Counter
MCU48-3S
• Low Power
lOrnA MAX. in Normal Operation
(VCC=SV, fXTAL=6MHz)
lO~A Max. in Power Down Mode
(VCC=SV, fXTAL : DC)
• Single Power Supply
• Power Down Mode (Stand-by Mode)
• Halt Mode (Idle Mode)
TMP 80 C48AP / -6, TMP 80 C35AP / -6, TMP 80 C48AF / -6,
TMP80C48AT,TMP80C35AT
TOSHIBA
PIN CONNECTIONS (TOP VIEW)
70
1.0
XTALl
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
~~~li
SS
m'
LA
RD
PSEN
lrn
ALE
DBo
DBl
DB2
DB3
DB ..
DES
DBb
DB,
21.
23
22
21
VSS
VCC(+SV)
T}
P27
P26
P2S
P2~
P 17
P lb
f 15
P1a.
Pl3
P12
Pll
~o
PROG
P23
P22
1'21
P2 0
PLCC
Flat Package
r-
..J..J
tr.l«
0
r--..c'"
Itr.l loW f-< f-< co U u .... N N N
tr.la:><>f-< e. e.e.
oil, 'S' '4' ']1 '2' '1' .. 10 0(2 oC) .0
...
NC
P25
P26
P27
Tl
vee
.......... oJ
" .....
a." ""'" .... __
l"_
~
PROG
EA
;.L
:l(
P23
P22
jffi
:;.:
P21
P20
TO'P VIEW
~..1
!NT
NC
TO
Vss
XTALl
XTA.L2
DB7
DBB
Ji:ESf'f
R
D~
D~
.....
....
PSEI'\ ,;:
li:
WR -.-
:li
NC ~
ALE
~
'NC
~
~
PI]
. Pl2
Pll
PIO
~:
Ps
-
:~
DBO ~
DBI ~
DB2 ~
...
DB3 ""-
~
~
;;~~;~~~;;~~g
QQQC>
NC: No
Conll~r\)(1n
MCU48-36
P24
PI7
P16
PIS
Pl4
AoAoAo .. "
Ao
TMP 80 C48AP /-6, TMP 80 C35AP /-6, TMP 80 C4BAF /-6,
TMP80C48AT,TMPBOC35AT
TOSHIBA
BLOQ( DIAGRAM
2
MASK ROM
lK X 8
(PROGRAM AREA)
64 X 8
ACC UMULA TOR
EIT
TEST
POWER
SAVE
PS
XTALZ
XT ALl
'R'Es'"ET
.... 0
!Z:oo
"tIO
c: ....
"';t'"
OJt'"
>
...;
g
::c
rh
t"3
...;
....!Z:
"tI
c:
...;
IIJT
ES
........
CIlt"3
"tI"';
t"'...;
~!
?5~
...;!Z:
""0
t'"
!Z:!z:
c:
...;
t"3><
>
>
I='
I='
::c
SS
ALE
CIlOJ t"'>
>1='
t"3!Z: "';1='
...; ......
"tIQ o::c
t'" ::t:t"3
t"3
OJ
CIlOJ
...;
::c
PS'EN 1m
CIl"tl
Sis
oQ
tI1~
l'3s::
WR
~
001='
...;;>
::c...;
0>
tI1
l'3
PRO G
CIlt"3
...;><
::c""O
0>
tJ:l!Z:
t"31='
CIl
l'3
::c
0
tI1
l'3
b5
C'I.l
Note 1)
Note 2)
The lower order 4 bi t of port 2 output lat ch are used
input/output operations with the I/O expander.
The output latch of port a is also used for address output.
MCU4B-37
al so
for
TOSHIBA
PIN NAMES AND PIN DESCRIPTION
TMP 80C48AP /-6, TMP80 C3SAP / -6, TMP 80C48AF /-6,
TMP80C48AT,TMP80C3SAT
VSS (p ower Supp ly)
Circuit GND potential
VCC (p ower Supp ly)
+SV during operation
PS (Input)
The control signal for the power saving at the power down mode
Low)
(Active
PROG (Output)
Output strobe for the TMP82C43P I/O expander.
P10 - P 17 (Input/Output) Port 1
8-bit quasi-bidirectional port (Internal Pullup
SOKn) .
P20 - P27 (Input/Output) Port 2
8-bit quasi-bidirectional port (Internal Pullup
= SOKn) •
P20 - P23 contain the four high order program counter bits during an external
program memory fetch and serve as a 4-bit I/O expander bus for the
TMP8243P.
DBO - DB7 (Input/Output, Tri-State)
True bidirectional port which can be written or read synchronously using
the RD, WR strobes. The port can also be statically latched.
Contains
the 8 low order program counter bi ts during an external program memory
fetch, and receives the addressed instruction under the control of PSEN.
Also contains the address and data duri~ an external RAM data store instruction, under control of ALE, RD, and WR.
TO (Input/Output)
Input pin testable using the conditional transfer instructions JTO and
JNTO. TO can be designated as a clock output using ENTO CLK instruction.
Tl (Input)
Input pin testable using the JTl and JNTl instruction. Can be designated
the event counter input using the timer/STRT CNT instruction.
INT (Input)
External interrupt input. Initiates an interrupt if interrupt is enabled.
Interrupt is disabled after a reset. Also testable with conditional jump
instruction. (Active low)
RD (Output)
Output strobe activated during a Bus read.
Can be used to enab Ie data
onto the Bus from an external device. Used as a Read Strobe to External
Data Memory (Active Low).
WR (Output)
Output strobe during a Bus write (Active Low).
External Data Memory.
MCU48-38
Used as a Write Strobe to
TOSHIBA
TMP80C48AP /-6, TMP80 C35AP / -6 ,TMP80C48AF /-6,
TMP80C48AT,TMP80C35AT
RESET (Input)
Active Low signal which is used to initialize the Processor.
during the power down mode.
Also used
ALE (Oupput)
Address Latch Enable.
This signal occurs once during each cycle and is
useful as a clock output. The negative edge of ALE strobes address into
external data and program memory.
PSEN (Output)
Program Store Enable. This output occurs only during a fetch to external
program memory (Active Low).
SS (Input)
Single step input can be used in conjunction with ALE to "single step"
processor through each instruction when SS is low the CPU is placed into a
wait state after it has completed the instruction being executed.
Also
used during the power down mode.
EA (Input)
External Access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug and essential for testing
and program verification. (Active High)
XTAL 1 (Input)
One side of crystal input for internal oscillator.
nal source.
XTAL 2 (Input)
Other side of crystal input.
MCU48-39
Also input for exter-
nes-q liST Of
TlCS-~8
tNSTRttTHJtS (1f.)
Object Colle
(1stJ
Function
Flag Cycle
81n.
l
c
c
,
•
,
I
I
t
•
r
n
,
t
C. ~C
Hex.
·.-·:Rr
.::}
,
O(C·······.·······_- 00000111
ot
A
00100111 .... 21
elR
(A).::.(M.:1···································
(A) ...O ... . . . ...................
1
·f
... ~~ . ·~:~:~~r~~·~::::::::::::·~:::::::::::··~·. : . :
I
41 . (A)<7:4> ... fAl<:Eo>···············
Rl _ .• ·--···-111001'-1 .__ . E7 . (A)·· ':-(A) ...................-.... .
I
(A) ... (A)<7>
RRC --.-- r······_···· . ·011"001"11 ··"s7·
.r~_ ..• _. Pp
oooo100p 08+p
,,
1 ...
..
1
n=O-6
(A)<1> "'(A)
(A)~(A)<~1>·--··························
(C) .... (A)
(A)<7> ... (C)
t
t
··f····
.
r·· ....,...
~O-6
(A)!::"lppl..... _........................ _.... P..=1.2 ....................... 2
oI ----"--"'--"'--- . _. __. . --.. . . . . . . .-.. . . . _. . . ._. . . _. . _. . ._. . . . -.. . . _. . . ._. . . . . . . . . . . . . . . . ..
Assclllbler
HncRlOn Ic
~
01101rrr 68 4 r (A)"'(A)+(Rr)
rzG-7 t t 1
ADO
•• !Rr 0110000;' ~r· (A)~(A).[(Rrn·················r;O.r··· . t t ··T··
ADO· .·.Ii· 00000011· 03····(A)f-.(A).j· ·····························tf1·
i i Ii iii i i i
·Aooc·--f·;···Rr· 01111rrr la+r (Al~·(A)+(R·rF(Cf ··········~O::l· ··f1 .; ....
AOOC···- •• IRr 0111000r 7~r (A)"'(Ai+((Itdl+(Cr····r",0.1 ..... If 1
·AOOC-·r .Ii ....- 00010011
13 (A)4.:.:(A}+14(C)·· .
! t···2
iiiliiil
Ii
. f···
Ail"·
·01011rrr584 r lM+=lA)"""I\C"Rr)"""·············r:;.o::r
.,.C-_·· A ••Rr 0101000r S()4r .. (A)'::'(.)" "UHr) r····_··· r,.0.1 ..
Ml
•• Ii
0,0100,,· 53· (A)"'(A)i\i··· .............
iii iii I i i i
-ORe--·-r-: Ri- 01oo1r"'r ·1"+r ··rAl;:lAr·VrRrr·················F-~r
····r····
ORt·- - A-.·!" ... ·- 0100000r 404 " ' . (A)+-(A)·"\/((Rrlr··.. ···· r~O. 1 ............ ·····f···
ORt
A • ti ..- 01000011 . 43 (A)"'(A) "",Ii
............
2
ililitlt
II
... ..... .
Pl-l·-;-Rr· ··11011rrr OS.... ·(Aft:."(Kr·V(Rr)"" ············~O::'r
···1· . .
XRl .• jRr .. ·;'01000r OO~r (A)~(Afv{(Rrjr···-·····~o.f····
XRl ·•• Ii
11010011
03·· (Af.... (A) ·vl
..........
2
iii Ii iI I
iI
·iiiC···· -l····· ···000101'" .....,7" .·lA)"+=fAl. r··································
··1··· -
o RiC· --·-r····· . ·-nno·,fr ·ft ··(A)·········· ...
n
(C) .... (A)
(A) .... (C)
norG-6
·RR---·"· .......... ··011ToH,.···Tf·· (A)····;:·(A)<·il+f>···.. ········n-=O-6
I
I~
•• Rr
~ ~:l:.
~~~~~~~
c -SW.,·_· ..·_-_····- 01000111
t
i
~ II
(2nd)
AD[
re
LIST Of INSTROCTlI1CS (2/4)
OUll
PP. A
Object Cooc
(1st)
Flaq ~Ie
function
(2m)
Bin.
!lex.
00111000 38~0 ... (Pp) "-IA)
C,AC
P=1.2.
,
2
....... -
·A·HC-····liJ;··n···· -'-OM10jip·
98·~p
I
liiliiii
ii
N ·O·itC······lp)r···· 1000100p 88 4 p
P
Iii iii i i
ii
U -"1MS······· A·-··.·8Ii~f 00001000 08
T OUT (:.::·Bu~i. A
000000 10
02
f
(pp) '::'(Po)/\ i
·~1,Z
·z
(pp) ':(Pp)V I
P"(2
·"i·
··TA)':(81~i)
2
2
( BUS) ..- I At)
t\, .
o
....-.. ·2
U ·~"r········B·tij(··.... i 1"0011"000· ···00 . ··(8OS}~·(BUSl
T i l iii iii
ii
PORC· ······8·05·:··.... 10001000 88·(8·i~f;:'(8IJSl vi
U ......_........._............... i i IJi iJi ..Ii I
f
I _.
T
HOV"if"-..··A··;Pp·· 000011po
mvtr····po:· ··A··· 001"11100
AHlD····· PP. 1\ ....
~~B~ A·
IHC
Rr
(1) IHC·······@R·j-·· ....
DEC
Rr
JHP
a
oC~j)
_·"(A·)<3:0> ... (Pp)
p.: 4"':' 1
··2-·
x·· 0
(A)<7:4> .-0
.(pp) "-IA)<3:0>
p= 4...... 7
2
-
100111po !)(>p IPp) t-IPp)I\IA)<3:o> p 4":"1
2
10oo11pp Be· D . (PP1-=.!rp) v (A):L<=3 0>_r-.1r--...:.4......
_':...-.J.._-4-=-2---I·
r~0 ...... 1
1
000l1rrr 18~r (Rr) .... IRr)·,
0001000r 10+r ((Rr)) t-(Rr)1·'
r=O, 1
1
r=O ...... T
1
11001rrr ca+r (Rr) .... (Rr)-l
2
a1l00100 all~4 (PC)<10:0> +-a
(PC) t-(08f)
aHl
2
I
=:
8 ·JHpp········@l-············ ·'0·110011 ···63·· (Pc)..::pRo((PCf<11:8)·~·(An
r -OJMr-···Rr;"···a ... _. 11101rrr E"S+r (Rr)" t-(Rrl-1
",0-1
a
aHl
Jc········a .-.. .... 11110110
h
aHl
n
c
JHC·········-a-··········· 11100110
fS
H(Rr) *Othen(PC)<1:0>+-aHl
else no oooration
i f(t)-1 then(PC)<7:0> ..... aHl
el so no operat Ion
H
~
(XI
o
n
"2
HVJ
2
(XI~
~\J1
0_
nl
+--0\
f
·2
i f(C)~O ·then(PC)t:aHf··
else no operation
n ·Jr······ ··a······. ········· -nOO011Cf ·"Cs i f(A)=O then(PC)4.:.:aHl·······
2
s
aHl
else no ot'eration
t ""JNI··········il········ ....... 10010110 ···96 if(Al*O then(PC)<1:0> ·~aHl
···2·aHl
else no ooeration
jTI,...·······j·················.. 00110110
36 .. if TQ..1 then(PC)<1:·0> .....·aHL
aHl
el se no o('C~ra:..:...ti:;:on..!..-_ _- - J L - - - 1 . . _ - J
lU ...... Reqister lnstltlctlon
"£6
0\
aHl
'z··
(Xlv
>H
H
v
~
H(XI
~~
(XI+-(XI
o
n>
VJ"'1
\J1_
>1
Ho\
1
•
s
Object Code
(1st)
MneIIIOnic
(2nd)
Bin.
HelC.
.PI10 a
00100110
26
aHl
JT1
,
"'01010110 ··..56
h;1
Assellbier
• JMit. a
r
•
afR
[ l,
Funet Ion
I'
Flaq Cycle
TO:O thcn(PC)<7:0> ..... aHl
'is .
2'
"1".
ion ... .
"
~
2
else no oooration
. if n-t then(PC)<7:0>+-aHC'
el se no ooorat ion
01000110' ...
if T1~0 theri(PC)+-aiK'" . .
aHL
. eI Sf! Mooorat
'10110110'B6 if rtFl then(PC)<7:·0>+-aHr··..
t JFO,
h
aHL
else no ooorat ion
In'---'j .... -..-. 0'1110110" "76 if t1"lthen(PC)<7:0>+':aHC'"
aHL
el se no oflCrat Ion
if H-l' then(PC) ;:aHr'"
r ._. ____.____ .... _.... aHl._ ......._•......... else~.. operation ..................... .
2'"
.. f .
,
,
2....
r"
c
::s::
(")
c::
.p.
00
I
t
,I
.
...
Jib' .... -•.. _.....-. "b6b100'fb "&+'12 . ff . ·(Ar·~ffhe·n· . ······
f'
aHl
(PC)<7:0>+-aHl
else no OJ)erat Ion
1J..0-7
IH10100 aH41~ J (Spn.~(I>SW)51._:.4~...~. {pcl.............
aHl
(SP) +-(SP)+l
.p.
~fR-"----"
CLR
C
CPl
C
(3) eLR ~.::: to'···--·"
CPl
FO
ClR-"-"f1
CPl
F1
(PC)<11> +-(080
··CSP)"·+-{SP·)-l ................................ _..
(PC) .... ((SP)]<11 :0>
"'s3" ··(SP)··;:.CSP)-1······ ..········ ..·..········..·· ..···
(PC) .... (SP))
(PSW)<1:4> ~[(SP)l<15:12>
HOV
H
Rr.' i
HOV··. ·"@"itr':',r"
o
v t«lV . ···(PS\r··
'"
eHOV ·Psw. A .'
XCH . A. Rr
XC"
A. 'Rr·····
n.. XCtlD .,. A. @Rr
S t«)VX' '" 'Rr,A'
t HOVX '" A. 'Rr' ...
HOVP' ····~.~A······
HOvpj..··.. A.@A
TC HOV
A.1
io t«)V··T.A···
IIIJ STR'·····,
en STRT ····Off'······
rt STOP TCHT
TCHTI
0 IN
r OIS .. ······lCKTJ
(1st)
(2M)
Bin.
/lex.
10111rrr 88' r
ii
iii i Ii i i
1011000r 804r
j;
iii i ii i i
C7
11000111
11010111
07
00101rrr 2R· r
00lOO00r 20·r
0011000r 304r
1001000r 90· ,..
1000000r BOor
10100011
A3
11100011 '. E3
01000010
~2
01100010
62
01010101
~5
01000101
45
01100101
6~
00100101
25
00110101
35
runet ion
Flap
Lie
I
C.At
(Rr) ..... i
r:rO.1
(A) ':"(PSw)'
(PSW) ..... (A)
(A) .... (~r)
(A) -((Rr)]"
(A)<3:0> ..... ((Rr)<3:0»
[XT((Rr)j .... (A)
(A) ..... [xT! (Rr) )
2
1
r.,O--7
rrO.;
r..O.1·
·.J'wO.1
1
1
1
.1.
1.
~O. 1
1
(A)' ..... PRO[(PC)<11 :8>'~'(A))"
1 .
(A) o-PROi (PC)<11>· 011· (A))
(A) ..... (lR)
(TR) ..... (A) . .
Start Tieer
. . ..
'1
1
1
I 1
Starlcounter
'" . 1
Stop
TiMer/Counter
[natlle Tilt(?r/Counter Interrupt
1
Disable liller/COt!nter InterruPt ....
, ..
I
I
..2
(PC) +-1
(2) Rfl---
Hoe.onle
alii
C AC
Object 'Code
Assembler
Ie
(5) .......................................................... .
10000011"'-'83"
f0010011"
10010111
10100111
10000101
10010101
10100101
10110101
97
Al
85
(C) ....O
(C) +-MoHer:...:::::.:::::.:::::·.:::·::::.....::.. ::·.·:::::::. .
nO) +-0
9~
(fO)'~MOHto"'''''''
'" ..................
......... _. I
·f'f·····f····
C
1
T .
,.
"1 .
'r"
A5 ···(Flf··~o···············......·-....··. ····..·····. · ..····............
&5' (fl)·+-MOtHlr.. ····· . ···························
.,
our. . ·"'r'
n DIS
t S(l
rSEl
o SEl
I SH
I
RBO"
R81
H80
HBI
EHTO:::::.:.CLK
(2. _ •• SUbroutine Instruction
ft) ~ IMtnJttlon
(3) •••••• flaG Instruct,on
...
"'--r
"
'HAII' ............................. 0000ti001
(6) MOP
oooooooo
'5) •••••• AID
.,
Or
.100000101"
[""nil'hle External' Interrupt
·00010101 . 15 Disable External InterruN
11000101
~. (SS)+- 0
'"
. l'
11010101
05 (SS)f- 1
'11100101
£5 (OBO"+- 0············-······..·· ..···_·······
1
.'-- -T'
il110101"f5 (PBf) '+-1
'0111010175 EnableCiocf fAJt~fon:'To .- . .
1
01
'Ha', f ..···· ...... -..
............. _......................... .
00 no oprat ion
Converter Instruction
(6) ...... Other
-
TOSHIBA
TMP BO C4BAP / -6, TMP BO C3SAP / -6, TMP BO C4BAF / -6,
TMPBOC4BAT,TMPBOC3SAT
TMPBOC4BAP/TMPBOC3SAP/TMPBOC4BAF/TMPBOC4BAT/TMPBOC3SAT
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
SYMBOL I
ITEM
I
RATING
_V_c~c_____ lvcc Supply Voltage (with respect to GND (VSS)) I -O.SV to +7V
_V_I~N~A___ I I nR u t Vo 1 t a ge (E xc ep t EA)
I---O~.~S-V-to-V-C-C-+O---".S,.-VVI NB
I~In:..;;Jpl::..;u;;":t:-'-V~ol~t;;":a;..J;;ig:":;"e~(O~n;"::l"';;'y,6;..E=-A~)~---------1 -0. SV to l3V
=P=D=====IPower Dissipation (Ta=70 ·C)
1----2S--Qrn-W--TSOLDER ISoldering Temperature (Soldering Timer 10 sec)1
260·C
--~·~--~~·-_ T_S_T_G_ _ I Storage Temperature
-6S C to 150 C
I
~~~-~~~---------------I
TOPR
O·C to 70·C
I Operating Temperature
DC CHARACTERISTICS
TOPR=O·C to 70·C, VCC=+SV±lO%, VSS=OV, unless otherwise noted.
I SYMBOL I
PARAMETER
I TEST CONDITIONS I MIN. I TIP. I MAX. I UNIT I
IVIL
IInput Low Volt~Except
I
I-o.s I
I O.B I V I
I
I
I
I
I
I
IXTALl, XTAL2, RESET)
IVILI
IInput Low Volta~
1-0.5 I--I~I-v-I
I
I (XTALl, XTAL2, RESET)
I
I
I
I
I
IVIH
IInput High Vol~(E~ept
12:""21--IVcCI-v-1
1
IXTALl, XTAL2, RESET, PS)
1
1
1
1
I
IVIHI
IInput High Volt~ _
10":'71--IVcCI-v-1
I
1(XTALl, XTAL2, RESET, PS)
1 vcci
1
1
I
1VOL
10utput Low Voltage
IOL=1.6mA
1 - - 1 - - 1 0.4sl-v-1
1
1 (Except PlO-P17, P20-P27)
1
1
1
1
1
IVOL1
10utput Low Voltage
IOL=1.2mA
1 - - 1 - - 1 0.4sl-v-1
I
1 (PlO-P17, P20-P27)
1
1
1
1
1
IVOHll 10utput High Voltage
IOH=-1.6mA
I~I--I--I-v-I
I
I (Except P 10-P 17, P 20-P 27)
I
I
I
I
I
IVOH12 10utput High Voltage
IOH=~400~A
Ivcc- I----I----I-v-I
1
I (Except PlO-P17, P20-P27)
I O.BI
I
I
I
IVOH2l 10utput High Voltage
IIOH=-SO~A
I~I--I---I-v-I
I
1 (PlO-P17, P20-P27)
I
I
I
I
I
I
\VOH22 10utput High Voltage
IIOH=-2S~A
Ivcc- I----I----I--v--I
\
1(PlO-P17, P20-P27)
1
1 O.BI
1
1
1
1ILl
1Input Leak Current
IVSS.1_
I.n
1 __ ..3_
MCU48-56
TMP 80 C48AP /-6, TMP 80 C35 AP /-6, TMP 80 C48AF /-6,
TMP80C48AT ,TMP80C35AT
TOSHIBA
OUTLINE DRAWING (FLAT PACKAGE)
Unit in mm
o 35
0.8 pitch
--- -t - - f J
_ _-
-
I
~
~
t ~i ~I
Z:
4J
2:...
lEl
.l4
--'~
I
~
3.!l
I
I
36
I
I
:'-7
.a
16
1
16
41
15
"4.3
l'
'"'
l2
38
---~ 39
--'~
I
CO
0~//
II
I
iJ
~
J
0
+t
0
~
-'
......
0-
-.&>
.....
1.3
~
;7
i
+ ..
... ---+--+------"--
14.0±O.1
( 16.9)
MARK
J
fl
-C
- -
iJUUUUJ JUUUUU
- - - --
- --
><
<
1.45±o.3
,
:i
U"I
t"-
,
f\
o
N
--
.1
-
1N
0
~
lS.2:tO.3
0.85*0.3
MCU48-57
TMP 80C48AP /-6, TMP 80C35AP /-6, TMP 80C48AF /-6,
TMP80C48AT, TMP80C35AT
TOSHIBA
OUTLINE DRAWING (Plastic Leaded Chip Carrier)
unit
6
1
40
44
o
7
39
o
~
U"'\
r-
.....
17
29
28
17.52::0.12
I
_H·~l±O.1
I---
~
jl.27TYj
15.76 TYP.
MCU48-58
~
in
rom
TOSHIBA
TMP80C49AP /-6, TMP80C39AP /-6, TMP80 C49AF /-6,
TMP80C49AT,TMP80C39AT
8-BIT SINGLE-CHIP MICROCOMPUTER
TMP80C49AP /TMP80C49AP-6
TMP80C39AP /TMP80C39AP-6
TMP80C49AF/TMP80C49AF-6
TMP80C49AT/TMP80C39AT
GENERAL DESCRIPTION
The TMP80C49A is a single chip microcomputer fabricated in Silicon Gate CMOS
technology which provides internal 8-bit parallel architecture.
The following basic architectural functions of a computer have been included
in a single chip; an 8-bit CPU, 128 x 8 RAM data memory, 2K x 8 ROM program
memory, 27 I/O lines and an 8-bit timer/event counter.
The TMP80C49A is particularly efficient as a controller. It has extensive bit
handling capability as well as facilities for both binary and BCD arithmetic.
The TMP80C39A/-6 is the equivalent of a TMP80C49A/-6 without ROM program
memory on chip.
By using this device with external EPROM or RAM, software
debugging becomes easy.
The TMP80C49AP/-6 and TMP80C39AP/-6 are in a standard Dual Inline Package.
The TMP80C49AF/-6 is in a 44-pin Flat Package.
The TMP80C49AT and TMP80C39AT are packaged in the JEDEC standard type 44pin
PLCC (Plastic leaded Chip Carrier).
FEATURES
• TMP80C49AP/TMP80C39AP/TMP80C49AF/
TMP80C49AT/TMP80C39AT
1.36~s Instruction Cycle Time
O'C to 70'C, SV ± 10%
• TMP80 C49AP-6/TMP80C39AP -6/TMP80C49AF-6
2.S ~s Instruction Cycle Time
-40'C to 8S'C, SV ± 20%
• Software Upward Compatible with
TMP8049AP/TMP80C49P-6/INTEL's 8049
• HALT Instruction (Additional Instruction)
• 2K x 8 masked ROM
• 128 x 8 RAM
• 27 I/O lines
• Interval Timer/Event Counter
MCU48-59
• Low Power
lOrnA MAX. in Normal Operation
(VCC=SV, fXTAL=6MHz)
10~A Max. in Power Down
(VCC=SV, fXTAL: DC)
• Single Power Supply
• Power Down Mode (Stand-by Mode)
• Halt Mode (Idle Mode)
TMP80C49AP /-6 ,TMP80C39AP /-6 ,TMP80C49AF /-6,
TMP80C49AT,TMP80C39AT
TOSHIBA
PIN CONNECTIONS (TOP VIEW)
10
VCC(+SV)
XTALl
T)
~i~~f
P27
P26
P25
P2~
P)7
P 16
f 1S
Pl~
Pl :3
P12
Pll
SS
rnJ
E.A
1m
PSEN
lrn
ALE
DBC
DBl
DB2
DB3
DB"
DBS
DB6
DB,
~O
PROG
P23
P:n
P:21
VSS
P20
Flat Package
PLCC
r~
~~
0
~"''''
CI 0 0 N
N N
1I)a::><>f--c.c.c.
111) tI)«
\oJ f-- f--
oil'
'S' I...t
'4' .'3'
'1'J 4+
'l3 062 '11 40
.. LJ
. . . '2'
. .t ..
... ,""" , .. , .......
~
PROG
P23
P22
P21
P20
NC
P25
P:Z6
P27
Tl
Vec
TO'P VIEW
He
Vss
DB7
DB6
DB5
TO
XTALl
XTAL2
In'E1
n
D~
!NT r-.
EA ;.:
RD ;:
PSEN
~
:It:
~
P24
P17
P16
PIS
PH
--"
X
:l:i
NC !:::
~
'NC
ALE if
DBO ~
DBl 2::::
DBl iC
DB3 ~:
~
~
Pl3
. P12
Pll
PIO
~:
Ps
Wit
~
~
;;~~~~~~;::;~~g
c::Ic::Ic::Ic::I>
Ne: No Conuf'r \ J rm
MCU48-60
..
. . . . . . . . -'
TMP BOC49AP /-6, TMPBOC39AP / -6, TMPBOC49AF /-6,
TOSHIBA
TMPBOC49AT,TMPBOC39~T
BLOO< DIAGRAM
INSTRUCT ION REGIST EF/
DECODER
RA1.:
128x 6
ACC:J1fJLATOf\
Ell'
TEST
POWL,,\
SAVE
~
1-0
!Zto
'co
c: ....
>-3t""
tr..r
>-3
@
!l:
tz:
tr..
tz:
..;
.....
!Z
'1:
e:
>-3
tr..t>:'
torr.
'c>-l
t"";
";1?
~E
>-3!Z
..... t -
!Z!Z
e:[:I;:
e:
"0
>-3
t=:x ..; .....
6~
~
t"
::-
t=
~
t"
t=:
~~
~S1
to "0
"-::l:
68
tr::::
=tz:
C:l t=::t>
ccrr.
s:
...,
!:I:
tr..e
...,~
!l:>-l
0:>-
tr
[:I;:
tr..
~H~
!:I:"e
0»
tr!Z
[:I;:e
[:I;:
::r
0
tr
tz:
ttr.
Note 1)
Note 2)
The lower order 4 bit of port 2 output latch are used also
input/output operations with the I/O expander.
The output latch of port o is also used for address output.
MCU4B-61
for
TOSHIBA
PIN NAMES AND PIN DESCRIPTION
TMP80 C49AP /-6 t TMP 80C39AP /-6, TMP 80C49AF /-6,
TMP80C49AT t TMP80C39AT
VSS (p ower Supp ly)
Circuit GND potential
VCC (Power Supply)
+SV during operation
PS (Input)
The control signal for the power saving at the power down mode
Low)
(Active
PROG (Output)
Output strobe for the 1'MP82C43P I/O expander.
P 10 - P 17 (Input/Output) Port 1
8-bit quasi-bidirectional port (Internal Pullup
SOKn) .
P20 - P 27 (Input/Output) Port 2
8-bit quasi-bidirectional port (Internal Pullup
= SOKn) •
P20 - P23 contain the four high order program counter bits during an external
program memory fetch and serve as a 4-bit I/O expander bus for the
TMP8243P.
DBO - DB7 (Input/Output, Tri-State)
True bidirectional port which can be written or read synchronously using
the RO, WR strobes. The port can also be statically latched.
Contains
the 8 low order program counter bits during an external program memory
fetch, and receives the addressed instruction under the control of PSEN.
Also contains the address and data duri~ an external RAM data store instruction, under control of ALE, RO, and WR.
TO (Input/Output)
Input pin testable using the conditional transfer instructions JTO and
JNTO. TO can be designated as a clock output using ENTO CLK instruction.
TI (Input)
Input pin testable using the JTl and JNTI instruction. Can be designated
the event counter input using the timer/STRT CNT instruction.
INT (Input)
External interrupt input. Initiates an interrupt if interrupt is enabled.
Interrupt is disabled after a reset. Also testable with conditional jump
instruction. (Active low)
RD (Output)
Output strobe activated during a Bus read.
Can be used to enab Ie data
onto the Bus from an external device. Used as a Read Strobe to External
Data Memory (Active Low).
WR (Output)
Output strobe during a Bus write (Active Low).
External Data Memory.
MCU48-62
Used as a Write Strobe to
TOSHIBA
TMP80 C49AP /-6) TMP 80C39AP /-6) TMP80G49AF /-6)
TMP80C49AT,TMP80C39AT
RESET (Input)
Active Low signal which is used to initialize the Processor.
during the power down mode.
Also used
ALE (Oupput)
Address Latch Enable.
This signal occurs once during each cycle and is
useful as a clock output. The negative edge of ALE strobes address into
external data and program memory.
PSEN (Output)
Program Store Enable. This output occurs only during a fetch to external
program memory (Active Low).
SS
(Input)
Single step input can be used in conj unction wi th ALE to "single step"
processor through each instruction when SS is low the CPU is placed into a
wait state after it has completed the instruction being executed.
Also
used during the power down mode.
EA (Input)
External Access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug and essential for testing
and program verification. (Active High)
XTAL 1 (Input)
One side of crystal input for internal oscillator.
nal source.
XTAL 2 (Input)
Other side of crystal input.
MCU48-63
Also input for exter-
TLCS-~8
nes·18 LIST Of nlSTRltTlM (114)
~
•
~
I
Object Code
As...... er
Pfrn)nlc
.OD .. A '. Rr
::
:: ~r
rllnct Ion
(1st)
(2m)
=1
81n.
Flao eye Ie
1""0-7
(A).-(A)+(Rr)
~;::'::~:·~:~:f(Rrn:::~::·:~::.~::::~o,I..·.::.
II" r
ttl
r-:
. :. : .::".: .:' :. "
·(A)~·"·
c
OA
A
SW.,-A--·_
........
t
i
Rl _. A
o
J
01000111
11100111
41
£7
Ric -- . l ....·......·1Hlllfll
... 'Ft'
n
(A)<1:4> .... fA')'<3:0:; .. ·........··· .....
(A) .......
(A) .-(A)<1>
n=O-6
(A)·.-(A)' ............ ·· ........
;"
r···
(A) .-(C)
nsO-6
(A)<7> ..... (A)
·ARt _._. l"'''---' ''01100n1'' . . s1" ." (A)..
PlI .. 00001000 08·p
rs~~~=-~~B~in:~.=-~lIc~.x~.r.~~~______~~-rC~._AC~~
OIlTl .... Po. A 00111000 J8.0 (Po) .-(A)
P:1,2
2
...
,.
U
2
-r. ·
...
...
2
'f"
"1''''
...
.,
,.
1
1
1"
'r"
·f·. ··
2
~(Pp)/\ i
liiiiiii
ii
A 00000010
08
02
..'MS·...... ·if"; . 8~··00001000
P~l, 2
P,(2
···TA) ;:: (Sitc; 1
(BUS) ..... (ACl
I
1
,
p
r OIlTC::"SUS!
·:·T:::.
. ·..........·....·· ....·. ·..... f .... · . .,..
oI --- "."-" . . __ . . .-...-.-..--..-_.. .. . . . . . . - . . . . . . . _. . . _. . . . . . ._. . . . . . . . . . . . . . . . . . . . . . . .
f-:M--~!lfIJ.-
I
2
FIi19 ~Ie
runction
(1st)
HncllOnic
"'f'
.:·(A)<~·l>
(A)<1> .-(ClnzO-6
(A).:(PP) ......................... P~l. 2
Object Code
.... 1' ..
(C) .-(A)
t '''-- A....
AsseMbler
Ip
A'HC ......PIJ,.... I···· '10'Oll0'Pj) 98.0 "(Pri)
iii II iii
ii
NORC ........jiilr.... 10001000' 88.0
2
(C).-(A)
'011;'01'1'1' .......71'· ... (A) f-(PO)
~4"::'1
'2"
(A)<1:4> ..... 0
PIJ:..'A '(j(hhlol1 jC.p (Po) ':"(A)<3:'(»
0';4"::'1
2
AHLO···· Po. A·" 100111Po OC·p "(Pol ,-(PO)I\(A)<3:0> 0-=4':":'1
2
_~~LD""PP, Al00011pp_~..~l!..~I!~~P1Y.~~~~.1--:':-t-_-t-'2~
IHC
Rr
0OO11rrr lS.r (Rr) .-(Rr)·l
r=O ...... T
1
(1) IHC ..... @Rr
0001000r 10.r . ((Rr)) ..... (lRrll·,.r:O. t
1
t--~O£~t_..;.;.Rr'----1I--"~10~0='~r..".;rr:-+-=-c8.r (Rr) ..... (Rr)-l
1'=0...... 1
1
JHP
a
all00100 all'4 (PC)<10:0> f-a
2
aHl
(PC) f-(08f)
B ·jHp'P"" . _·@A . ·. ·........ ··1011ooff ....·. 83. (Pc)' ~(An2
r DJMf..·.. Rr .....-a ....· 11101rrr tS.r (Rr) .-(Rr)-l
. r-s0-7
2
II
aHl
if(Rr) *Othen(PC)<1:0' .....aHl
else no ooeration
n
c JC· . ··. a
11110110 F6 if(e)-1 then(PCl<1:0>;'aHl'"
f
aHI.
else no operation
h
'2
...
JMC ..·. ·....·a. ·. . ·· . . ·1l100110 . '[6 ... if(C}-=O then(PC).::·:aHC-·
Pp
m'io. . . ·.
Jr..·. . ·a· . . . ·. ·. . "11'00011'0
aHl
..jMl ....·.... a. . ·. . . ·. · 1001011'0
n ..
S
t
aHl
aHl
·)t,o·. . ·_. ·a. ·. · ·. ·. . . - 00110110
C6
.. 00
... 36'
else no operation
if(Al=O then(PCl;':aHl
else no oreration
If(A)*O then(PC)<7:0> t-:aHt
else no oooration
if f0:1 then(PCl<1:0>~::-:aH[
I
0\
H
~
00
o
n
>-'Iw
~'"
oof!d
0_
nl
~O\
"'~
;l>t-i
~>-'I ~
>-'100
~~
oo~
-
0'"
2
Z
-f'
n;l>
w"Ti
'"
:>1
>-'10\
TLCS-48 LIST or INSTRllCTJONS (414)
t-i
LI
I~
.
s
Assellbler
•
n
c
h
ft
s
1
,r
Object Code
runet Ion
(1st)
(2nd)
ftneIonlc
Flag Cycle
rcIe
In········a
;s
H
0
v
c
. 2 ..
2
n.
s
t
2
TC
io
IIU
t
i
en
rt
ir{A")<·b;;;;fTile·;I······
aHL
ft
CAll_.a_.
(PC)<1:0)--aHL
1t-0--1
aH10100 aJl'H [(SP)) --(PSW)<1:4>· (PC)
. aliL
. (SP) "":CSP)+l ......... .
(PC)<10: 0> --8
(PC)<11> 4-(D8f)
2·
0
r
else no operat ion
.2
Object Code
(1st)
(200)
Bin.
HOV
c
b6b100lo~·;2·
Hnellonlc
S
a
a Jib ·_·-i·"
Assembler
all
Bin.
Hex.
C AC
00100110
26 If TO"O thcn(PC)<7:0)--aHL
aHL
else no operat ion
jjC· I
·0"-010110·56 . if 11-1 then(PC)+:-aHC··
aHL
else no operation
0100011(f ... "4"S· if a-O· then(PC)·~aHC· ..
.INti a
aHl
. else noooerat ion ... .... .......
Jro· a
10110110·86 H FtF1 then(PC)+:::iiHC
aHL
else no operation
Jtf -.j .. -. . ··000'0"'0· ..
if H·l" then(Pc)4=aHr···
.___...__ ...._............ aHL
else no operation
JIITO
I
r
I
10111rrr
iiiiiiii
HOV······@·Rr·....· . 1011000r
iii iii i i
~'r··.. ·1. PSi,..·· 11000111
PSW.A
.
11010111
HOV
00101rrr
A. Rr
XCH
XCH .... A. lIRr···· 00 10000 r
XCIID A. flRr
0011000r
HOVX····· @Rr,A· 1001000r
...
HOVX A. flRr
1000000r
HOVp· ···"A,flA
10100011
HOVP"j"····A.@A
11100011
HOV
01000010
A.l
HOY
01100010
T.A
01010101
STRl T
STRI eNT
01000101
STOP TOfT
01100101
TCNT)
00100101
EN
TCHTI
00110101
DIS
Rr,' i
"ex.
88'r
ii
BO'r
ii
C1
07
2/1· r
20~r
30'r
90'r
80-r
A3
[j
42
I·· 62
... 55
45
65
25
3S
.................... .-...................
(5) ................... _....................
runet ion
flag
~I'
I
0
CJ)
::r:
H
t;Jj
:l>
C.AC
(Rr)--j
r:0 ..... 7
({ltr)j':':i
r"O.l
2
1
(A) --(PSWI
(PSW) --(AI
(A) -(Rr)
r O-1
(A) -r (Rr))
r .. O.l
(A) <3: 0> .... r (Rrl<3: 0> ) r"O.l
[XI[ (Rr)] t-(A)
!'z0. 1
(A) --[Xli (Rr))
r=0.1
(AI· --PROr (PCI ~ 'A) )
(A) ..... PROr (PC)· 011 • rA) 1
(A) --(TR)
(TR)--(A)
Start Titer·
Start counter
Stop Tilller/Counter
(nahle Tiller/Counter InterMlPt
Oisahle 'illl~!{~I_'!ter Interrupt
1
1
1
1
1
1
T
1
1
1
1
1
·1
,..,
1
1
~
I ~-
00
o
o
~
I
....
\0
~
--.......
I
...._..............................
·-f···'
""t-i
--[(SP)]<11 :0>
'RtiR-··_·_·_··,oo;OOlf .-··93· . (PC)
(SP ft: (SP) -,. ..................................
·rr· ·r····
o
fl) Rf,- ---1000001f -'83·· .
·(SP)··t::.·(~fpf-l··
................... I··
~
00
(PSW)<1:4> --((SP)]<15:12>
10010111
91 (C)--O
1
101(10111
A1··
.................................
T
10000101
85 (Fof...:o ........................................
,..
. FO . .
10010101
95 (FO)"...:NOt{tO)·· ...... . . ,
Fll0l00101
A5 (f1) --0
f
F1
10110101
B~
(F1) ·....HOT(F'f)'·· .... ..............................
1
A, Rr 11111rrr f8+r (A)--(Rr)
j'E0 ......1
1
A •'Rr 1111000rr~r··· (A)'::[ (Rrlr···············_········ r - O , l · 1 .
A.1i
~~mn
·~~(A) t.::1
. .. ............................. ........
.. 2 ..
CLR
C
CPL
C
(3)CLR .. ·ro···
CPL
ClR
CPl
f«JV
KJV
(I) KJV
(C)~Nontr·
C
o (i..-:::::.: . (: . :.:.·..:.. 100000101 .. OS·
n DIS
I
. 00010101
15
tS£l···· ···Ri«f····· 11000101 ... C!l
r SH"· R81
11010101
05
o SH···· HBO ·····11100101
E5
F5
I SH
H8111110101
ENT(f···· CLK
·01110101
75 .
t"Mble£xfernal·'ntcr·nirif
Disable [xterllr1l Interrort·
(BS)-- 0
(RS)-- 1
(nsr ) -- O·
(OBf)~ 1 .
(nableClock6Jtjij(ontO . ·:
·HAIr···················· . . . 00000001 ··of Ha I t
·:=:~tf~ 1'~~~~
·!tr :I~~rfi~·~~;~:~~~~::~:::::::~~:::=·~[:· . . . . . . . . }. ..
(2) _ ••• Stlbrout lne InstMlct ion
ft) ~ Instrvct Ion
(3) •••••• flag Instruct Ion
,
·--1
(PC) --[(SP)]
(6) HOP
OOOOOOOO
00
(5) ...... AID Converter Instruction
(6) ...... Other
0--.......
01
~""
\O~
;:p.t-i
~,.., ~
t-ioo
. 1
1
. . . -. ···r
~~
1
,
..
~\O
oo~
..
·--r
.,
..
no oprat ion
(')
t-iw
oo~
-
o \0
o >
w'TJ
\0 --.......
:l>1
,..,""
TOSHIBA
TMPSO C49AP /-6, TMPSOC39AP / -6, TMPSOC49AF /-6,
TMPSOC49AT,TMPSOC39AT
TMP80C49AP/TMPSOC39AP/TMPSOC49AF/TMPSOC49AT/TMPSOC39AT
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
ITEM
I
I SYMBOL I
Ivcc SUEEly Voltage (with resEect to GND (VSS»I
I VCC
IInEut Voltage (ExceEt EA)
I
I VINA
VINB
IInEut
Voltage (Onli': EA)
I
I
IPower DissiEation (Ta=70·C)
I
I PD
I TSOLDER ISoldering TemEerature (Soldering Timer 10 sec) I
IStorage Temperature
I
I TSTG
10Eerating TemEerature
I
I TOPR
RATING
-O.sV to +7V
-O.sV to VCC+O.sV
-O.sV to 13V
2s0mW
260 ·C
-65 ·C to 150' C
O·C to 70'C
DC CHARACTERISTICS
TOPR=O·C to 70·C, VCC=+sV±10%, VSS=OV, unless otherwise noted.
I SYMBOL I
PARAMETER
I TEST CONDITIONS I MIN. I TIP. I MAX. I UNIT
I VIL
IInput Low Vol t~Except I
1-0.5 I
I O.S I V
I
IXTAL1, XTAL2, RESET)
I
I
I
I
I
IVILI
IInput Low Volta~
1-0.5 1--I""D.6I-vI
I (XTALl, XTAL2, RESET)
I
I
I
I
IVIH
IInput High Vol!~.&~_JE!.£ept
12T1--IVCCI-vI
IXTALl, XTAL2, RESET, PS)
I
I
I
I
IVIHI
IInput High Volt~ _"
1~1--IVCCI-vI
I (XTALl, XTAL2, RESET, PS)
Ix vcci
I
I
I VOL
10utput Low Vol tage
IOL=l .6mA
1 - - 1 - - 1 0.4sl-vI
I (ExceEt PlO-P17, P20-P27)
I
I
I
I
IVOLI
10utput Low Voltage
IOL=l.2mA
1---1---1 0.4SI-vI
I (PIO-PI7, P20-P27)
I
I
I
I
IVOHll 10utput High Voltage
IOH=-1.6mA
12T1--I--I-vI
I (ExceEt P10-P17, P20-P27)
I
I
I
I
IVOH12 10utput High Voltage
IOH=-40011A
Jvcc- I - - - I - - - I - v I
I (Except PIO-PI7, P20-P27)
I o.SI
I
I
IVOH21 10utput High Voltage
IOH=-SOllA
12T1--I--I-vI
I (p 10-P 17, P 20-P 27)
I
I
I
I
VOH22 I Output High Voltage
IOH=-2s11A
Ivcc- I - - - I - - - I - v I (PIO-P17, P20-P27)
I o.sl
I
I
=IL-I~-IInput Leak Current
IVSS(VIN(VCC
1 - - 1 - - 1 ±10 I~
I (Tl, lNT, EA, PS)
I
=
=
I
I
I
I
-IL-I-I-II~ut Leak Current
IVSS~VIN~VCC
I--I--I-=Sol~
I (SS, RESET)
I
I
I
I
I
I VSS+O .45V~VIN~VCC 1--1--1-500 I~
-I-LI-2-1 Input Leak Current
_ _ I (PIO-PI7, P20-P27)
I
1_ _ 1_ _ 1_ _ 1_ _
ILO
10utput Leak Current(BUS,TO)lvss+0.4sV~VIN~Vccl I - I ±10 I llA I
_ _ _ I (High impedance condition) I
1_ _ 1_ _ 1_ _ 1_ _ 1
ICCI
I
I Normal
IVCC=SV,fXTAL=6MHzl
I
I 10 I
I
_ _ _ I VCC Supply
I oEeration I VIH=VCC-O .2V
I
I
I
I rnA I
ICCHI I
Current
I HALT Mode IVIL=0.2V
I---I---I-WI
I
~___ I
I
I
I
I
I
I
I
ICC2
I
I Normal
IVCC=5V,
1--1--1151--1
I vcc Supp ly
I oEeration I fXTAL=l1MHz
I
I
I
I mA 1
-I-CCH-2-1
Current
I HALT Mode IVIH=VCC-0.2V
I---I---I~I
I
I
I
I
I
I
I
I
I VI L=O .2V
MCU4S-66
TMPSO C49AP 1-6, TMP SO C39AP 1-6, TMP SO C49AF I -6,
TMPSOC49AT,TMPSOC39AT
TOSHIBA
TMP SOC49AP ITMPSOC39AP ITMPSOC49AF ITMP SOC49AT ITMPSOC39AT
AC CHARACTRISTICS
TOPR=O·C to 70·C, VCC=+5V±10%, VSS=OV, unless otherwise noted.
ITEST
I f(t)
11 MHz IUNIT
I SYMBOL I
PARAMETER
ICONDITION I
I
MAX. I
I
I
INote 2
I l/xtal fl
I t
I Clock Period
10001 ns
I tLL I ALE Pulse Width
I
13.5t-170 I
I ns
I tALI Ad d res sSe t up Time ( ALE )
I
I 2t-110 I
I ns
I CL=20 F
I
t-40 I
I tLA IAddress Hold Time (ALE)
I ns
7.5t-200
ns
I tCCl I Control Pulse Width
I
I (RD, WR)
I
I
I tCC2 IControl Pulse Width
I 6t-200 I 350
ns
I
I (p SEN)
I
I
I tDW IData Setup Time
ns
16.5t-200 I 390
I
I (WR)
I
I
I tWD IData Hold Time
I CL=20pF
ns
I
t-50 I 40
I
I
(WR)
I tDR IData Hold Time
I
I (RD, PSEN)
I tRDl IData Input Read Time
I
I
I
I
I CL=20pF
11 .5t-30
I
I
I
I
o
15.5t-120 I
(RD)
I tRD2 IData Input Read Time
I
I (PSEN)
I tAW IAddress Setup Time
I
I
I
4t-120 I
I
I
I
I
I (WR)
I tADI IAddress Setup Time
I (RD)
tAD2 IAddress Setup Time
I (PSEN)
tAFC11Address Float Time
I (RD, WR)
tAFC21Address Float Time
I (p SEN)
tLAFCIIALE to Control Time
I
I
I
I
10t-1701
I
I
I
7t-170 I
I
I
I CL=20pF
I
I
I CL=20pF
10.5t-40
I
I
I
I
I
2t-40
MCU 4S-67
375
ns
240
ns
ns
730
ns
460
ns
ns
I 140
I
3t-75
I
tLAFC21ALE to Control Time
I (PSEN)
tCAl IControl to ALE Time
I (RD, WR, PROG)
tCA2 I Control to ALE Time
I (PSEN)
t CP IPort Control Setup Time (PROG)
tPC IPort Control Hold Time (PROG)
tPR IPort 2 Input Data Setup Time
I (PROG)
tPF IPort 2 Input Data Hold Time
I (PROG)
tDP IPort 2 Output Data Setup Time
I (PROG)
tPD IPort 2 Output Data Hold Time
I (PROG)
ns
5t-150 I 300
I
I
(RD, WR)
110
10
ns
I 200
ns
I
Il.5t-75
I
60
ns
I
I
I
I 25
ns
t-65
I
I
I
4t-70
I
Il.St-SO
I 4t-260 I 100
Is .St-120 I
I
I
11.5t
I
I
I
I
ns
I 290
I
I 50
o
6t -290 I 250
I
I
11. St-90
I
I
I
40
650
ns
ns
ns
140
ns
ns
ns
TOSHIBA
TMP80C49AP /-6, TMP80C39AP / -6, TMP80C49AF /-6,
TMP80C49AT,TMP80C39AT
TMP80C49AP/TMP80C39AP/TMP80C49AF/TMP80C49AT/TMP80C39AT
AC CHARACTRISTICS (CONTINUE)
TOPR=O·C to 70·C, VCC=+SV±10%, VSS=OV, unless otherwise noted.
11 MHz
PARAMETER
ITEST
I SYMBOL I
I f(t)
I
I CONDITION I
I MIN. I MAX.
I
I
IlO.St-2501 700 I
I
I tPP IPROG Pulse Width
I 4t-200 I 160 I
I tPL IPort 2 I/O Data SetuE Time(ALE) I
10.St-30 I 15 I
I tLP IPort 2 I/O Data Hold Time (ALE) I
(ALE) I
14.5t+lOO 1
1 510
I tPV IPort OutEut Delay Time
I tOPRR ITO Clock Period
1 3t
1
I 270 I
1 1St
I
I 1.36115.0
I tCY IC:z:cle Time
IUNITI
I
I
I ns I
I ns I
I ns I
1 ns 1
I ns I
1 llS I
Note: 1. Control Output CL=80pF. BUS Output CL=lSOpF.
2. The f(t) assumes 50% duty cycle on XTAL1 and XTAL2.
The Max. Clock frequency is llMHz. and the Min. Clock frequency is
1MHz.
MCU48-68
TOSHIBA
TMPBOC49AP /-6, TMPBOC39AP /-6, TMPBOC49AF /-6,
TMPBOC49AT,TMPBOC39AT
TMPBOC49AP-6/TMPBOC39AP-6/TMPBOC49AF-6 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
ITEM
I
I SYMBOL I
(with
resEect to GND (VSS))I
VCC
Ivcc
SUEEly
Voltage
I
IInEut Voltage (ExceEt EA)
I
I VINA
I InEut· Vo 1 tage (Only EA)
I
I VINB
IPower DissiEation (Ta=85 . C)
I
I PD
I TSOLDER ISoldering TemEerature (SolderinB Timer 10 sec) I
IStorage TemEerature
I
I TSTG
10perating TemEerature
I
I TOPR
RATING
-0.5V to +7V
-0.5V to VCC+0.5V
-0.5V to 13V
250mW
260'C
-65 ·c to ISO'C
-40'C to BS'C
DC CHARACTERISTICS (I)
TOPR = -40'C to BS·C, VCC=+SV±IO%, VSS=OV, unless otherwise noted.
I SYMBOL I
PARAMETER
I TEST CONDITIONS I MIN. I TYP. I MAX. I UNIT I
IVIL
IInput Low Voltage
I
1-0.5 I
I O.B I V I
I
I
I
I
I
I
I
I
IVIH
IInput High Vol~&~_JE~ept I
1"""""2."21--IVCCI-v-1
I
IXTALI, XTAL2, RESET, PS)
I
I
I
I
I
I
IVIHI
IInput High Volt~ _
I
1~1--IVCCI-v-1
I
I (XTALI, XTAL2, RESET, PS)
I
Ix vcci
I
I
I
10utput Low Voltage
IIOL=1.6mA
1 - - 1 - - 1 0.4SI-v-1
I VOL
I
I (ExceEt P 10-P 17, P 20-P 27)
I
I
I
I
I
I
10utput Low Voltage
IIOL=l.2mA
1 - - 1 - - 1 0.451-v-1
IVOLI
I
I (PIO-P17, P20-P27)
I
I
I
I
I
I
IVOHll IOutput High Voltage
IIOH=-I.6mA
I~I--I--I-v-I
I
I(ExceEtPlO-PI7,P20-P27)
I
I
I
I
I
I
I VOHl2 10utput High Voltage
IIOH=-40011A
I VCC- I - - I - - I - v - I
I
I (ExceEt PIO-P17, P20-P27)
I
I o.BI
I
I
I
IVOH21 10utput High Voltage
I IOH=-SOllA
I~I--I--I-v-I
I
I (PIO-P17, P20-P27)
I
I
I
I
I
I
IVOH22 10utput High Voltage
I IOH=-2511A
Ivcc- I - - I - - I - v - I
I
I (PIO-PI7, P20-P27)
I
I o.BI
I
I
I
IILI
IInput Leak Current
IVSS<
<
.c:
N
~
20
%
~____________~5~1~.3~M~A~X~P__________________~
i
15.24
J
-
Note: 1.
2.
± 0.15
1.4 ± 0.15
0.5
± 0.25
'-
2.54 ±0.25
0-1:
This dimension is measured at the center of bending point of leads.
Each lead pi tch is 2 .S4mm, and all the leads are located within
±O.2Smm from their theoritical positions with respect to No.1 and
No.40 leads.
MCU48-80
TMP80 C49AP /-6, TMP80C39AP /-6, TMP80C49AF /-6,
TMP80C49AT, TMP80C39AT
TOSHIBA
OUTLINE DRAWING (FLAT PACKAGE)
o 35
0.8 pitch
I
,. ,.
,. ,. ,.
~
,.
..
I
~
I- l-
I... I-
~
34
~
I
36
~
~7
1-""(
38
---~ 39
~
~
I
I
IT
.0
41
L
3 1
,2
I
1.
~
CO
~
,'"
I
Ut;;::;;,:·"
7'
~
~ ~
H
~ ~
,- ",--t-
3:\ 3':~.i 3:' 2~
~
~
t:l :b
~6 2,. .i" c:.>
.
.
MARKING
{AREA
.I
.~
L.
..
1 2 3 • t
tIt- tl-
..
...... ......
1.0
..
..
,
...
~
.., 6 9 ]0 11
~
t:
~
I-
......
~
I
,)
3
I
a·
1P
16
1
16
P-4
0
+I
0
f
I
~
.-1
15
14
-.
0"
..I:)
P-4
l.'3
12
t-
I-
+.. . . ... .....
14.0:.t:O.l
(16.9)
.
>(
-.
C
~
U'\
e}
MARK
<
1. 4S±O. ,3
::E
C
\J'\
f'oN
-.
-N
15.2:0.3
0.85*°.3
MCU48-81
1
TMP 80C49AP /-6, TMP 80C39AP /-6, TMP80C49AF /-6,
TMP80C49AT,TMP80C39AT
TOSHIBA
OUTLINE DRAWING (Plastic Leaded Chip Carrier)
unit
6
I
44
40
o
7
39
N
c
~
LI"\
r-.....
29
17
28
17.52:0.12
r.#
16.6 TYP.
O.71:tO.1
----------------------\+-------------~iN
c
~
"'"
~
I
~.O~±O.l
~
~~ypt ~
15.7bTYP.---I
MCU48-82
in
mm
TOSHIBA
TMP80 CSOAP /-6, TMP 80 C40AP / -6, TMP80 CSOAF /-6,
TMP80CSOAT,TMP80C40AT
8-BIT SINGLE-CHIP MICROCOMPUTER
TMP80CSOAP /TMP80CSOAP-6
TMP80C40AP /TMP80C40AP-6
TMP80CSOAF/TMP80CSOAF-6
TMP80CSOAT/TMP80C40AT
GENERAL DESCRIPTION
The TMP80CSOA is a single chip microcomputer fabricated in Silicon Gate Q10S
technology which provides internal 8-bit parallel architecture.
The following basic architectural functions of a computer have been included
in a single chip; an 8-bit CPU, 2S6 x 8 RAM data memory, 4K x 8 ROM program
memory, 27 I/O lines and an 8-bit timer/event counter.
Tne TMP80CSOA is particularly efficient as a controller. It has extensive bit
TOSHIBAg capability as well as facilities for both binary and BCD arithmetic.
The TMP80C40A/-6 is the equivalent of a TMP80CSOA/-6 without ROM program
memory on chip.
By using this device with external EPROM or RAM, software
debugging becomes easy.
The TMP80CSOAP/-6 and TMP80C40AP/-6 are in a standerd Dual Inline Package.
The TMP80CSOAF/-6 is in a 44-pin Flat Package.
The TMP80CSOAT and TMP80C40AT are packaged in the JEDEC standard type 44pin
PLCC (Plastic Leaded Chip Carrier).
FEATURES
• TMP80CSOAP/TMP80C40AP/TMP80CSOAF/
TMP80CSOAT/TMP80C40AT
1.36~s Instruction Cycle Time
O'C to 70'C, SV ± 10%
• TMP 80 CSOAP -6/TMP 80 C40AP -6/TMP 80CSOAF-6
2.S ~s Instruction Cycle Time
-40'C to 8S'C, SV ± 20%
• Software Upward Compatible with
TMP8049AP/TMP80C49AP-6/INTEL's 8049.
• HALT Instruction (Additional Instruction)
• 4K x 8 masked ROM
• 256 x 8 RAM
• 27 I/O lines
• Interval Timer/Event Counter
MCU48-83
• Low Power
lOmA MAX. in Normal Operation
(VCC=SV, fXTAL=6MHz)
10~A Max. in Power Down Mode
(VCC=SV, fXTAL : DC)
• Single Power Supply
• Power Down Mode (Stand-by Mode)
• Halt Mode (Idle Mode)
TMP80 CSOAP / -6, TMP80 C40AP /-6, TMP 80CSOAF /-6,
TMP80CSOAT,TMP80C40AT
TOSHIBA
PIN CONNECTIONS (TOP VIEW)
TO
VCC (+5V)
11
4O
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
XrAL1
;i~~~
~
m
LA
1m
PSEt\
~
ALE
DBO
DBl
DB2
DB3
DB~
DBS
DB£>
DB,
VSS
P27
P26
P25
P 2 ..
P I7
P l6
Fl S
P1 ..
Pl 3
P12
Pll
~O
PROG
P~3
P22
P21
P20
Flat Package
PLCC
!oJ":!":!
r~
Ir.«
0
,..."'''''
~!oJf-<>f-<
zz
~
.... ~~
~~
~Z
c
~z
:>
l"l
~
."
~
0::0
t'"
E;
t:1
~
ALE F'S"£]T
OJ OJ
l"ll"l
.,,~
t"'~
SS
t'"
OJ "0
~::o
:::~
68
e::o
OJCJ
;;r::
~t:1
0::0
~
~
l"l:>
RD
WR
OJt:1
~:>
::::~
0:>
e
l"3
OJ
PROG
tr.l1."3
~><
~."
0:>
tl:lz
1."3t:1
1."3
::0
0
tr
l"l
th
OJ
Note 1)
Note 2)
The lower order 4 bit of port 2 output latch are used also
input/output operations with the I/O expander.
The output latch of port 0 is also used for address output.
MCU48-85
for
TOSHIBA
PIN NAMES AND PIN DESCRIPTION
TMP80CSOAP / -6, TMP 80C40AP /-6, TMP80 CSOAF /-6,
TMP80CSOAT,TMP80C40AT
VSS (Power Supply)
Circuit GND potential
VCC (p ower Supp ly)
+SV during operation
PS (Input)
The control signal for the power saving at the power down mode
Low)
(Active
PROG (Output)
Output strobe for the TMP 82 C43P I/O expander.
P 10 - P 17 (Input/Output) Port 1
8-bit quasi-bidirectional port (Internal Pullup
SOKr2) .
P20 - P27 (Input/Output) Port 2
8-bit quasi-bidirectional port (Internal Pullup
= SOKn) .
P20 - P23 contain the four high order program co~nter bits during an external
program memory fetch and serve as a 4-bit I/O expander bus for the
TMP8243P.
DBO - DB7 (Input/Output, Tri-State)
True bidirectional port which can be written or read synchronously using
the RD, WR strobes. The port can also be statically latched.
Contains
the 8 low order program counter bi ts during an external program memory
fetch, and receives the addressed instruction under the control of PSEN.
Also contains the address and data duri~ an external RAM data store instruction, under control of ALE, RD, and WR.
TO (Input/Output)
Input pin testable using the conditional transfer instructions JTO and
JNTO. TO can be designated as a clock output using ENTO CLK instruction.
T 1 (Input)
Input pin testable using the JTl and JNTl instruction. Can be designated
the event counter input using the timer/STRT CNT instruction.
INT (Input)
External interrupt input. Initiates an interrupt if interrupt is enabled.
Interrupt is disabled after a reset. Also testable with conditional jump
instruction. (Active low)
RD (Output)
Output strobe activated during a Bus read.
Can be used to enable data
onto the Bus from an external device. Used as a Read Strobe to External
Data Memory (Active Low).
WR (Output)
Output strobe during a Bus write (Active Low).
External Data Memory.
MCU48-86
Used as a Write Strobe to
TOSHIBA
TMP SO C50AP / -6, TMP SO C40AP / -6, TMP SO C50AF / -6,
TMPSOC50AT,TMPSOC40AT
RESET (Input)
Active Low signal which is used to initialize the Processor.
during the power down mode.
Also used
ALE (Oupput)
Address Latch Enable.
This signal occurs once during each cycle and is
useful as ·a clock output. The negative edge of ALE strobes address into
external data and program memory.
PSEN (Output)
Program Store Enable. This output occurs only during a fetch to external
program memory (Active Low).
SS (Input)
Single step input can be used in conjunction with ALE to "single step"
processor through each instruction when SS is low the CPU is placed into a
wait state after it has completed the instruction being executed.
Also
used during the power down mode.
EA (Input)
External Access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug and essential for testing
and program verification. (Active High)
.
XTAL 1 (Input)
One side of crystal input for internal oscillator.
nal source.
XTAL 2 (Input)
Other side of crystal input.
MCU4S-S7
Also input for exter-
TLCS-~8
Object Code
runct Ion
(1st)
1:
Bin.
Hex.
I
Flag Cycle
Ie
C.~C
.11
5
(2nd)
! tt . 1, ......
1
............._...................
t t 2
_DO _.. A •. Rr. 01101rrr 68"r (A)4-(A)"(Rr)
... 0-1
_00
A, ~Rr 0110000r 6Q.r •. (A}~(A)"[(Rrfr····"······""~o,f···
ADO· -.. ·A·,1i
00000011
03 ···(A)+-(A)+i
iiiiiiii
ii
·.iJOC·_··A-;··-Rr·· 01illrrr 1s+r(A}t.:fAFfRrF(Cr ··. ····~O::·7 ·11 . f
_DOC A ,'Rr 0111000r10->r (A)4-(A)+[(Rr)l .. (t)-····~O.l
·ff ··f
ADOC-·f·, fj"·- 0001001,· 13 (A)f-(A)"i"(C) .
t 12
iii ii Ii i
jI
"ANT· ·r:····Rr· ··01011rrr 58"r· "(Al;::(Af"·"(Rrr················r~o;;:r
.. f····
Ml-A·, '~r- ·0101000;;· 5~r· (A)~(A) .." [(Rr;r···..·_····· ';:';0:'··· .............. ····r···
Ml
A ,ti ... 0101001'53·· (A)4-(A}·i\1 ... ................
2
iii iii Ii
ii
ORr··-.--;-Rr·-· O;OO1irr·4/i.. r ··(Al;::lAr';TR·rr·············-··r;;~l.. .......... 1
ORt··- -A-,·'Rr·· 01()()O()Or 40";; .:(A)~.fAL.Y((Rrn:::·:::. :::~r=o!t.·:
ORl
A • ti _... 01000011" .. 4j (A}f-(A) vi
·f
iii Ii III
Ii
..
.:. . .: : ....,
·nl-·1-;·"'·ii·r-·· -fiOl1frr· 08·. r·( AY;:·(Ar·t;;(R·r r············~o;:;:r
XRl "A."!Rr····;;Ol000r· OO"r ··(A);::(Af'.tf(Rdr········.. ·r.;O.l ...
XRlA, tI
11010011
Ii i II iii
03·· (A)f-·(A)··vi
ii
..
··r····
···1· .
. . ·f·
Object Code
ASSeMbler
1
O£C-· ._-. A· ....... -._. 00000111
01 (A)..:.(A)-f·····.. ········· .............................
··f····
00100111 ... 21·
............................................ .
·f
ClR
A
00 11 011,· 31 (A) f-NOHAr:~·:·::·:··::::::::··::······::....·:··:· ..
CPl
A
1
.(.....
01010111
51 (A)f-(A)8CO
DA
A
..
01000111 .. 47 ··(A)<1:4> .... fAl<:Eo>· ....· · . ·········
"sw.·p-- A
Rl - A
11100111
£1. (A)··..:.(A)··
t"
(A) 4-(A)<7>
n=0-6
o RtC""'··;'_··-·· n1"1o'-1"f ····Ft (A) f-(A)···· ....
. ·t
(C)f-(A)<7>
ft
(A) f-(C)
~o-6
R~-· --- A . _·········011"1011"1 ······l1"· ... (A )<11>····;::·(A f f-(A)
ii1iC .-- l·_·-"-·OlroOfff ··-6'- . (AJ····.:·(A)·..·············..·······..·····
(e) f-(A)
(A)<7> f-(C)
~N
2
, .1"_._~_ •. P1J. 000010pp 08"p (A).~::JPpL...... __ ........_._..... _... P=1.2
(A)~O
.,,
r· . ·
FIiJ9 Cycle
funct ion
(1st)
(2nd)
HnelllOnic
8in.
lip-x.
OUTL ..... PP.A ..... 0011100p JIJ.p
C.AC
(Pot t-(A)
, .................._........ .
AHC····· . ·p·p·:..n··· ·,00110·00 M·p . (pp")
I
N
p
U
T
":'(Pp)/\ i
I i II Ii ii
I;
ORC····· . ·p·ii:lr ..... 10001000 88+0 . fpp)'::'(Pp)V i
II iii iii
ii
·"lNS·········r··;···8Iiifoooo1000 OS "TA);:(8i~f
·O.UTC:.::::Bi1i;·;A. 00000010 02 (BUS)t-(AC)
P~1.2·
2·
P,.(t··
2
·2
...... _ ..._ .._... _ .2 ..
I
o
2
U
T
p
U
ORr ·. ···"8"05:··'....
iiiiiiii
10001000
iiiiiiil
ii
88
Ii
·(B·~f;:'(8US)··
vi·
2
t-J
~
T
00
HOVO· . · · A·; Po 000011po ot·p . fAf 4-(Po) .
.TIIt-- A··-······ ... 000101,-,····· 11 ·. (A)·;::·(A·)·.r·········. ·····_···. ·. ········· . ···...···....
I . _- --..-.. . ----......._. . . -.. --.. .. . . . . . . -.........-.. .-.-.. _. . . . _. . . . -.........................................
o
LIST Of tNSTRttTlIJfS (214)
. p=4~7
··2··
(A)<1:b f-O
(Po) 4-(A)<3:0>
p=4·~1
2
ANLO···· PP.·· A.. ·· 10011100 !)(>p(Pp) f-(Po)/\(A)<3:0> 0,,4-1·
2
f-~~LO .... npp~ A· ·100011PP_~~_~Pl-=:.(~IUV(A)<3:Quc4"""'·
2
IHC
Rr
00011rrr lS*r (Rr) f-(Rr)"l
r=0 ...... 1
1
(1) IHC ..·····~Rr
oo01000r 10'r . [(Rr») 4-[(Rr)1 .. f
r=O.l·
1
DECRr·
11001rrr· CS·r (Rr) 4-(Rr)-1
1'=0-1
1
JHP
a
a1lOO100 all'~ (PC)<10:0> 4-a
2
aHl
(PC)<11> f-(D8f)
B JHP"j;······ . ·@A·········· ·101100'-' ···B3·(Pc)f-PRO[(PC)<11:8>~(An .....-- 1.2
r DJHf·_· Rr;···a·····ll11>1rrr Ts·r· (Rr)· 4-(Rr)-l
r=()-..1 -.2
a
aHL
i((Rr) =l:Othen(PC)<7:0>4-aHL
n
else no operation
c JC·········a···· .... ·HHoll0fS H(C)"l then(PC)<1:0>t:-aHL
f .
h
aHl
else no operation
JNC·. ···..··i...... ·······. ··· 1"1100110 ·"£6 ... if(C)=O then(PC)i-:aHL ....
2·
s
aHL
el se no operat ion
t ·JH-r·········-a··········-····· ·1001011(f ·!j6·It(A)=l:O then(PC)<7:0>·e..:affL .
···Z·
aHl
else no operation
JTCj""·········a····..·············OO110110 .. 36· if Tlp1 then(PC)<1:0>t:-aHC····Z-·
L--~r-r--_~""""""L.-,.=:-aHl
else ~ orer"!l~n-'-_ _- - ' L - - ' - _ - - '
OO\i"o········pp·:···A. ·· ·OO"ffHop 3C··0
.n ...... RI'fII~tpr
In~t"lrtlnn
o
()
VI
o
~
or
J"STRttlJONS (M4)
Assembler
Object Code
(1st)
TlCS-48 LIST
1
Object Code
(1st)
Function
Flag Cye Ie
~m
(2nd)
s
8in.
Hex.
C.AC
00100110
26 If TO.. O thcn(PC)<7:0>f-aHL
2
aHL
else no oooration
. '0"010110 "-56' if T1-1 then(PC)f-aHl'
J11
I
2
aHL
else no operation
·f·
0100011Cj"' '.6 . if n·o· then(PC)'~aHC" .
JNtl ...
aHt
. else no oooration . .
. 2
10110110
B6 if ro..l then(PC)<7:0>~aHr""
JFO
a
aHL
else no oooration
.. 2
6"1'11011()"" "'76 if Fl z l' then(PC);':ciHC·H
aHt
else no operation
Jfr-·a·-········- 'OOO10fl(f "16 if Tf.,fthen(PC)·;::itHC····
f'
aHt
else no operation
Jir--i"--' '-",00001'-0 '''86' "If INT ';0 then(Pc)';::aHC'
f'
aHl
else no operation
JlC10
8
r
I
n
c
h
n
s
1
r
•c
a
....
o Jib' -'-B'" ...-... '6bti1oo"1o 1).'2 . n "(Al(b>~f Hie·n······ .
(l)
HOV
H
o
aHl
(PC) <1: O>..--aHl
else no operation
bwO-7
aH~~~OO aH-ll . ~~~~.l~.fs~~~).~1...:4>... ~JP~) ........... ..
Rr •• i
HOv. · . ··liir·...r·
H(jii'l.psifH'
e
HOV .... PsW.A·
XCii
A.Rr··
XCii
A. lIRr....
XClID·.. ·A.(lRr·
tlJVX'" @Rr.A·
HOVX'" A,lIRr
HOVP .... A,(I" .
HOVP"3".... A.(lA
HOV
A.I
HOV
I.A
STRT T
STRT' eM,
STOP 1CHT
EN
lCHl1
DIS
lCH!L
I\..
s
t
Te
io
en
rt
o
r
~I.
n.v I
rUllCt ion
(2M)
V
IIU
i
HneIRonlc
~
a
t
n
"
Ie
Bin.
!lex.
10111rrr B8'r
iii i ii i i i i
1011000r 80-r
iii iii j i i i
11000111
C1
11010111
07
00101rrr 211~r
001 OOOOr 20~ r
0011000r 30-r
1001000r 90'r
1000000r 80>r
10100011
AJ
11100011
[j
01000010
42
01100010
62
01010101' 55
01000101" 45
01100101
65
00100101
2~
00110101
35
I
..
C.AC
(Rr)o-j
r.. 0....... 7
2
nRr)l~i
f
(A) "'IPSW)
IPSW) -(AI
(A) .... (Ilr)
r O....... 1
(A) .... (( Rr)]
r=O. 1
(A)<3:0> .... IIRr)<3:0>] r=O.l
[XTI(Rr)] o-(A)
. ""0.1
(A) ..--(XTl(Rr)] ..
1'=0.1
(A)' f-PROIIPC)<11:8> ;IA))
(A) ~PRO"PC)<11)· 011· (All
(AI -(1R)
(1R)..--(A)··
Start 1iller
Start counter
Stop TiJnCr/Counter
[nallle Ti"~r/Couoter Interrupt
Disable 1illcr/Couoter Interrupt
t
1
1
I~
11
I~
··1
~
I 1.
./ ~
-I ~ .
I
2
--I
(PC)<10:0> +-11
(PC)<11> 4-(DSr)
(5) .................................... .
(3\
M-' ----100000'11· "-'83' . (Sp)"'+:.·'S·P}-1·· . ·-..-....·. _.... ·................ ·· . ·..........··-f· .
~fR- ....·--··100loo·;f
CtR
t
10010111
CPr t
10100111
(3) ClR. FO
10000101
I CPl . FO .... ... 10010101
ClR
Fl
"'0100"01
CPl
f1
10110101
KJV
A. Rr 11111rrr
KJV 'A';Rr-- 1111000r'
U) KJV
•.• Ii ··..n~mn
(PC) +-[(SP)]
(SP)-·f.-(SP)-'·
............................... 'IT ..
(PC) +-[(SP))<11 :0>
(PSW) <1 :4> ..--[(SP)] <15 : 12>
91 (e)f-O
1
A7' (C)..--flOTCCr .. · ...... ········ .... ······ ........ H
'1'
85 no)' ~ ..... -..........:......:. ::::.:....:.::
1
9S (rO)H~NotHtif"'" .
1
A5 (rl) f-O
...............................................
·..1. ·
85' (f1) ·..:..:HolUfr·. ·. . ·........·. ·........ ····
1
F8·r (A)f-(Rr)
reO ...... 7
1
·"t~r . ··(A).::.[(RrJl..-.. ·_ ........ ·_.. ·_..·.. r-O.1 ."
.,.
-r . .
'-'''93'
~~
fA) +::j . .. .......... _................. ..... H..
..
(3) •••••• Flag Instruct Ion
....................................
c
0
n
t
r
..EN ....··
....
r
DHf"...
S[l ..."RM
RRl
SH
0
sEt
I
SEt
ENTCf........
. ·· elK
·2 .
fO'j-Rr':-i-- -1010frrr A8+r- ..(Rrr;:·(Ar-----·----..·-........~~l'·
,
KJV--'Rr" A "1010000'; A()4rl(Rrnf-fAT ..-·-....·-........ ·-.. ~o f· . · .............. ,....
(2) _ ••• SUbroutTne Instruct ion
fl) M!M InslMICt Ion
~
~
HBO
HBl
. -. I
...
I·00010101
00OOO1(n
11000101
11010101
11100101
.. 11110101
01110101
..
os
C!>
... D~
...
1
fnii'iile [xter·naf Interrupt'
15 Disable [xternal InterroN
(8S)..-- 0
(BSI(OSF)··4.-1 0·············· ..·.. ·· ...... _......... _..... -
E5 (DSr) '4- 1
.......-.....-..
F5
lnable
clockojtPi(o·j\
.. tO . .
75
~
1
1
1
l'
..... - -T··
1
·H'AIr................... -... 00000001 '''0'1' lIaI t " ' ,
(6)
HOP
OOOOOOOO
00 no oorat ion
1
(5) •••••• AID COnverter Instnlct ion -~(~.;.6)~
...-...-O~t.,....he-r---.l---L~-I
00
o
(')
~.j>-
~o
oo?tl
o ___
(')1
VI (3\
o~
~04
~~ ~
1-100
~~
00 VI
00
(,):J>
o ___
.j>-"%j
:J>I
~(3\
TOSHIBA
TMP SO C50AP /-6 t TMPSOC40AP /-6 t TMPSOC50AF /-6,
TMPSOC50AT t TMP80C40AT
TMP80C50AP/TMPSOC40AP/TMP80C50AF/TMPSOC50AT/TMP80C40AT
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
SYMBOL
,
ITEM
'RATING
_V~C~C_ _ 'VCC Supply Voltage (with respect to GND (VSS», -0.5V to +7V
_V_I_N_A_ _ I In put Vo I t a ge (Excep t EA)
'--0~.-=5~V~to-V~C~C~+7"O-=.5=-VVI NB
'-I-np~u-t-V"";;"o"";;"lt-a~g~e---+-(O-n~l-y~EA-')~---------' -0.5 V to l3V
=P:D====='Power Dissipation (Ta=70 ·C)
'----257"Om~W--TSOLDER 'Soldering Temperature (Soldering Timer 10 sec)'
260·c
, -~~-~~--_T
.......S_T_G_ _ , Storage Temperature
-65· C to 150· C
, ---~-~------------------------,.
TOPR
Operating Temperature
0 C to 70 C
.
DC CHARACTERISTICS
TOPR=O·C to 70·C, VCC=+5V±10%, VSS=OV t unless otherwise noted.
'SYMBOL'
PARAMETER
, TEST CONDITIONS , MIN., TYP., MAX., UNIT'
'VIL
'Input Low Volt~Except
'-0.5'
, O.S, V ,
,
, XT AL I t XT AL 2, RE SE T )
,
,
,
,
,
IVILI
IInput Low Volta~
1-0.5 '--I---0:-6,-v-,
I
, (XTALI, XTAL2, RESET)
,
,
I
I
I
'VIH
'Input High Vol~.s..~_JExcept
,---z:-2,--,VCC,-V-'
I
IXTALI, XTAL2, RESET, PS)
,
I
1
1
1
IVIHI
IInput High Volt~ _
'~I--IVCCI-v-1
1
1 (XTALI, XTAL2, RESET, PS)
I vcc 1
I
I
1
I VOL
IOutput Low Voltage
IOL=I .. 6mA
' - - 1 - - 1 0.451-v-1
,
1 (Except PlO-PI7 t P20-P27)
1
1
,
,
1
IVOLI
IOutput Low Voltage
IOL=I.2mA
' - - 1 - - 1 0.451-v-1
I
1 (PIO-PI7, P20-P27)
I
,
1
I
1
IOH=-l.6mA
12.41--I--I-v-1
IVOHll IOutput High Voltage
1
1 (Except PIO-PI7, P20-P27)
1
1
,
1
I
IVOHl2 Output High Voltage
IOH=-400],lA
Ivcc- I - - I - - ' - v - ,
I
(Except PIO-PI7, P20-P27)
'O.S,
1
1
1
1VOH21 Output High Vol tage
IOH=-50],lA
12.41--'--I-v-1
1
(PIO-PI7, P20-P27)
1
,
,
1
1
IVOH22 Output High Voltage
IOH=-25],lA
Ivcc- I - - ' - - I - v - I
I
(PlO-PI7, P20-P27)
I o.SI
I
I
I
'ILl
Input Leak Current
'VSS~VIN~VCC
, - - , - - , ±10 ,~
,
(T I, 1NT, EA, Ps)
I - 'I'
I
1ILl 1
I.!!E.ut Leak Current
I VSS~VIN~VCC
1---1--1-==50 I~
I
(SS, RESET)
I
I
I
I
1
IILI2
Input Leak Current
IVSS+0.45V(VIN(VCCI--I--1-500 I~
1
(PIO-PI7, P20-P27)
,
=
=
1
1
,
I
10utput Leak Current(BUS,TO)IVSS+0.45V~VIN~Vccl---I---I~I~
IILO
I
I (High impedance condition) I
1_ _ 1_ _ 1_ _ 1_ _
IICCI
I
I Normal
IVCC=5V,fXTAL=6MHzl
I
I 10 I
1
Ivcc Supply
I operation IVIH=VCC-0.2V
I
I
I
I mA
'ICCHI I
Current'
IVIL=0.2V
1--1--,"2:51
I
I
I HALT Mod e I
I
I
I
I
IVCC=5V,
1--I--I---r5I-IICC2 I
I Normal
I
I VCC Supply
I operation I fXTAL=l1MHz
I
I
I
I mA
IICCH2 I
Current
I HALT Mode IVIH=VCC-G.2V
I---I---I~I
I
I
I
IVI L=O .2 V
I
I
I
I
MCU48-90
TOSHIBA
TMPSOC50AP / -6, TMP SOC40AP /-6, TMP SO C50AF /-6,
TMP80C50AT,TMPSOC40AT
TMPSOC50AP/TMPSOC40AP/TMPSOC50AF/TMPSOC50AT/TMPSOC40AT
AC CHARACTRISTICS
TOPR=O'C to 70'C, VCC=+5V±10%, VSS=OV I
PARAMETER
I SYMBOL I
I
I
I Clock Period
I t
I tLL I ALE Pulse Width
I tAL IAddress SetuE Time (ALE)
I tLA IAddress Hold Time (ALE)
I tCC1 I Control Pulse Width
I (RD, WR)
I
I tCC2 I Control Pulse Width
I (PSEN)
I
I tDW IDa~ Setup Time
I (WR)
I
I 'tWD I Data Hold Time
I (WR)
I
I tDR IData Hold Time
I
I (RD, PSEN)
I tRD1 I Data Input Read Time
I (RD)
I
I tRD2 IData Input Read Time
I (p SEN)
I
I tAW IAddress Setup Time
I (WR)
/
I tAD1 IAddress Setup Time
I (RD)
I
I tAD2 IAddress Setup Time
I (PSEN)
I
I tAFC1/Address Float Time
I (RD, WR)
I
I tAFC21Address Float Time
I (PSEN)
I
ItLAFC11ALE to Control Time
I (RD, WR)
I
ItLAFC21ALE to Control Time
I
I (p SEN)
I tCA1 IControl to ALE Time
I (RD, WR, PROG)
I
tCA2 IControl to ALE Time
I (PSEN)
tCP IPort Control SetuE Time (PROG)
tPC IPort Control Hold Time (PROG)
tPR IPort 2 Input Data Setup Time
I (PROG)
tPF /Port 2 Input Data Hold Time
I (PROG)
tDP IPort 2 Output Data Setup Time
I (PROG)
tPD IPort 2 Output Data Hold Time
I (PROG)
unless otherwise noted.
TEST
11 MHz
IUNIT I
I f (t)
CONDITION I
I MIN. I MAX. I
I
Note 2
I l/xtal fl 90.91 10001 ns I
13.5t-170 I 150
I ns I
I 2t-110 I 70
I ns I
CL=20EF
I t-40 I 50
I ns I
17.5t-200 I 4S0
I ns I
I
I
I
I
I 6t-200 I 350
I ns I
I
I
I
I
16.5t-200 I 390
I ns I
I
I
I
I
CL=20pF
t-50 I 40
I
I ns I
I
I
I
I
I CL=20pF
11 .5t-30 I
110 I ns I
0
I
I
I
I
15.5t-120 I
375
ns I
I
I
I
I
I
240
ns I
I
I 4t-120 I
/
I
I
I
ns /
I
I 5t-150 I 300
/
I
I
/
730
ns I
I
I 10t-1701
I
I
I
I
ns I
460
I
I 7t-170 I
I
I
I
I
ns I
I CL=20pF
I 2t-40 I 140
I
I
I
I
ns I
I CL=20pF
10.5t-40 I 10
I
I
I
I
ns I
I
I 3t-75 I 200
I
I
I
ns I
11.5t-75
60
I
I
I
I
ns I
t-65
25
I
I
I
I
I
ns I
290
I
I 4t-70
I
/
/
ns I
11 .5t-SO
50
I
ns I
100
I
I 4t-260
ns I
Is .5t-120
650
I
I
I
I
ns /
140
11.5t
0
I
I
/
I
ns I
250
I 6t-290
I
I
I
I
ns I
40
11.5t-90
I
/
MCU4S-91
I
I
TOSHIBA
TMP 80 CSOAP / -6, TMP 80 C40AP / -6, TMP 80 CSOAF / -6,
TMP80CSOAT,TMP80C40AT
TMP80CSOAP/TMP80C40AP/TMP80CSOAF/TMP80CSOAT/TMP80C40AT
AC CHARACTRISTICS (CONTINUE)
TOPR=O'C to 70'C, VCC=+SV±10%, VSS=OV! unless otherwise noted.
PARAMETER
I SYMBOL I
ITEST
11 MHz
I f(t)
I CONDITION I
I
I
I MIN .1 MAX.
IIO.St-2Sol 700 I
I
I tPP IPROG Pu·lse Width
I 4t-200 I 160 I
I tPL IPort 2 I/O Data SetuE Time(ALE) I
10.St-30 I 15 I
I tLP IPort 2 I/O Data Hold Time (ALE) I
(ALE) 1
!4.St+l00 !
I tPV IPort Out ut Dela Time
1 510
3t
I tOPRRITO Clock Period
1
1 270 1
1 tCY I C;:tcle Time
1
1 1St
1 1.36115.0
IUNIT I
I
I
I ns I
I ns I
I ns I
1 ns 1
1 ns I
1 llS I
Note: 1. Control Output CL=80pF. BUS Output CL=IS0pF.
2. The f(t) assumes 50% duty cycle on XTALI and XTAL2.
The Max. Clock frequency is IIMHz. and the Min. Clock frequency is
IMHz.
MCU48-92
TOSHIBA
TMPBO CsOAP / -6, TMPBOC40AP / -6, TMPBOCsOAF /-6,
TMPBOCsOAT,TMPBOC40AT
TMPBOCsOAP-6/TMPBOC40AP-6/TMPBOCsOAF-6 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
I SYMBOL I
ITEM
I
RATING
, VCC
'VCC Supply Voltage (with respect to GND (VSS» I -O.sV to +7V
I VINA
I Input Voltage (Except EA)
1---o=-.-:s~V-to-V-C-C-+O~.s~VI VI NB
'-In-p~u-t-V"';;"'o"';;"'lt-a-"gi!...,;.e~(O-n.....;l-y""""--EA--:)~---------I -0.5 V to 13 V
'_P~D~___ '~Po~w.....;e~r_D...;;...i~ss~i~p~a_t_io_n~(_Ta_=_B~s_·~C~)_~_ _ _ _ _~I--~---2s~~~W--, TSOLDER 'Soldering Temp~rature (Soldering Timer 10 sec)'
260·C
, --~~----, TSTG
, Storage Temoerature
-6s·C to lsO·C
, TOP R
'-Op-e-r-a.....t'7i-n -g """'::T::-"'e-m-p-er-a-t-u-r-e- - - - - - - - - - - 1 -40· C to B5 . C
DC CHARACTERISTICS (1)
TOPR = -40·C to Bs·C, VCC=+sV±lO%, VSS=OV, unless otherwise noted.
I SYMBOL I
PARAMETER
I TEST CONDITIONS I MIN. I TYP. I MAX. I UNIT I
IY1L
IInput Low Voltage
I
1-0.5 I
I O.B I V I
I'
I
,
I
I
I
I
'VIH
IInput High Vol~(Except ,
12.21--IVCCI-v-1
I
IXTALl, XTAL2, RESET, PS)
,
I'
I
,
,
'VIHl
'Input High Volt~ _
I
,~,--,VCCI-v-1
I
,(XTALl, XTAL2, RESET, PS)
I
'x vcc I
I
,
,
'Output Low Voltage
,IOL=1.6mA
1 - - ' - - ' 0.4s,-V-'
I VOL
,
'(Except P 10-P 17, P 20-P 27)
,
I"
I
I
'Output Low Voltage
,IOL=l.2mA
r - - - I - - ' 0.4SI-v-,
IVOLl
I
I (PlO-P17, P 2 0 - P 2 7 ) '
I'
I
I
,
IVOHl! 10utput High Voltage
,IOH=-l.6mA
12.4'--I--,-v-1
,
'(Except PIO-PI7, P20-P27)
I
' I '
I
I
'VOH12 'Output High Voltage
I IOH=-40011A
Ivcc- ' - - - ' - - - I - v - ,
,
'(Except PIO-P17, P20-P27)
I
'o.BI
I
I
I
'IOH=-sOllA
12.4'--'--I-v-1
I VOH2l 'Output High Vol tage
,
I (p 10-P 17, P 20-P 27)
I
I'
I
I
,
VOH22 10utput High Voltage
'IOH=-2s11A
Ivcc- ' - - I - - ' - v - ,
I(PIO-P17, P 2 0 - P 2 7 ) '
,0.BI'
I
,
=IL""""':I=---'Input Leak Current
'VSS~VIN~VCC
1 - - ' - - ' ±lO ,~,
I (Tl, !NT, EA, pg)
,- '"
I
I
-IL-I-I-II!!E.ut Leak Current
IVSS~VIN~VCC
1--I--,--=SO'~1
I (SS, RESET)
I
I
I
I
I
I
-IL-I-2-IInput Leak Current
IVSS+0.4sV~VIN~Vccl--I--I-SOO I~I
_ _ I (PlO-PI7, P20-P27)
I
I
I
I
I
I
10utput Leak Current(BUS,TO) IVSS+0.4sV~VIN~VCC'---I---1 ±10 I~I
ILO
=-~_I(High impedance condition) I
1___ 1_ _ 1___ 1_ _ 1
ICCI
I
I Normal
IVCC=sV,fXTAL=6MHzl
I
'10 I
,
'VCC Supply
I operation IVIH=VCC-O.2V
I
I
,
I mA I
--IC-CH~l-1
Current
I HALT Mode' VIL=0.2V
I---'---'--W,
I
I
I
I
I
I
I
I
I
MCU4B-93
TOSHIBA
TMP80CSOAP /-6, TMP80C40AP /-6, TMP80CSOAF / -6,
TMP80CSOAT,TMP80C40AT
TMP80CSOAP-6/TMP80C40AP-6/TMP80CSOAF-6 ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (II)
TOPR=-40·C to 8S·C, VCC=+SV±20%, VSS=OV, unless otherwise noted.
I SYMBOL I
PARAMETER
I TEST CONDITIONS I MIN. I TIP. I MAX. I UNIT
IVIL
IInput Low Voltage
I
I-o.s I
10.lS I V
I
I
I
I
I
Ix vcci
IVIH
'Input High Vol~(E~ept ,
'O.S xl--IVCCI-vI
IXTALl, XTAL2, RESET, PS)
1
I~I _ _ I_ _ I_ _
IVIHI
IInput High Volt~ _
10.7 xl
I vcc I V
1
I (XTALl, XTAL2, RESET, PS)
I~I _ _ I_ _ ' _ _
I VOL
IOutput Low Voltage
IOL=l.6mA
1
I
I 0.4sl
V
I
I (Except PIO-P17, P20-P27)
1_ _ 1_ _ 1_ _ 1_ _
IVOLI
IOutput Low Voltage
IOL=l.2mA
I I 10.4SI V
I
I (PIO-P17, P20-P27)
1_ _ 1_ _ 1_ _ 1_ _
I ~OH12 IOutput High Vol tage
IOH=-400llA
IVCC- I
I
I V
I
I (Except PlO-P17, P20-P27)
I~I _ _ I_ _ I_ _
IVOH22 IOutpt,lt High Voltage
IOH=-2SllA
Ivcc- I
I
I V
I
I (PIO-P17, P20-P27)
I 0.81
I
I
ILl
I Input Leak Current
VSS~VIN~VCC
1 - - I - - I ± i " O IliA
~~I(Tl, ffi, EA, PS)
1_ _ 1_ _ 1_ _ 1_ _
ILl 1
I I~ut Leak Current
IVSS~VIN~VCC
,
I
I-vcc I llA
I(ss, RESET)
I
I
I
10.1 I
-IL-I-2-IInput Leak Current
Ivss+o .4SV~VIN~VCC I - - ' - - I - v c c IliA
I (PIO-P17, P20-P27)
I
I
I
I OJITI
-IL-O--IOutput Leak Current(BUS,TO)'VSS+0.4SV~VIN~VcCI---I-----1 ±10 I ~A
~~_I (High impedance condition) ,
1____ ' _ _ 1_ _ 1_ _
ICCI
,
I Normal·
IVCC=SV fXTAL=6MHz I
,
I 10'
_ _ _ Ivcc Supply
I Operation 'VIH=VCC-0.2V,
' _ _ ' _ _ ' _ _ 1 mA
I CCHI ,
Current' HALT Mode 'VIH=O 2V
I'
I 2. S,
I
I
I·
I
I
,
I
MCU48-94
TOSHIBA
TMP80CsOAP /-6, TMP80C40AP /-6, TMP80CsOAF /-6,
TMP80CsOAT,TMP80C40AT
TMP 80CSOAP- 6/TMP 80C40AP- 6/TMP 80 CSOAF-6
AC CHARACTRISTICS
TOPR=-40·C to 8s·C, VCC=+sV±20%, VSS=OV, unless otherwise noted.
6 MHz
ITEST
UNIT I
PARAMETER
I SYMBOL I
I f(t)
I
I CONDITION I
I MIN. I MAX.
I
I
I
INote 2
I Clock period
1 l/xtal f1166.61 1000 ns I
I t
ns I
13.St-170 I 410 I
I
I tLL IALE Pulse Width
ns I
I 2t-110 I 220 I
I tAL IAddress SetuE Time (ALE)
CL=20pF
120 I
ns I
I t-40
I tLA IAddress Hold Time (ALE)
ns I
17.st-200 1050 I
I tCCl I Control Pulse Width
I
I (RD, WR)
I
I
I
800 I
ns I
I tCC2 IControl Pulse Width
I 6t-200
I
I (p SEN)
I
I
I
880 I
16.St-200
ns I
I tDW IData Setup Time
I (WR)
I
I
I
I
CL=20pF
120 I
t-sO
ns I
I tWO IData Hold Time
I
I (WR)
I
I
I
tDR IData Hold Time
CL=20pF
ns I
11.St-30
0 I 220
I (RD, PSEN)
I
I
I
I
tRDl Data Input Read Time
5.5t-120 I
ns I
I 800
(RD)
I
I
I
tRD2 Data Input Read Time
ns I
4t-120 I
I 550
(PSEN)
I
I
tAW
Address Setup Time
ns
5t-150 I 680 I
(WR)
I
I
tADl Address Setup Time
ns
10t-1701
11500
(RD)
I
I
tAD2 Address Setup Time
ns
1000
7t-170 I
(p SEN)
I
tAFCl Address Float Time
CL=20pF
ns
2t-40 I 290
(RD, WR)
I
tAFC21Address Float Time
CL=20pF
ns
10.5t-40 I 40
I (p SEN)
I
/
/
ItLAFC11ALE to Control Time
ns
I 3t-75 I 420
I
I
/
I (RD, WR)
ns
ItLAFC21ALE to Control Time
11.5t-75 I 175
I
I
I (PSEN)
I
ns
t-65 I 100
I
I tCAl IControl to ALE Time
I
I (RD, WR, PROG)
I
I
ns
I tCA2 IControl to ALE Time
I 4t-70 I 590
I
I (PSEN)
I
I
ns
11 .5t-80 I 170
I tCP IPort Control SetuE Time (PROG)
ns
I tPC IPort Control Hold Time (PROG)
I 4t-260 I 400
ns
1290
18.5t-120 I
I tPR IPort 2 Input Data Setup Time
I
I
I (PROG)
I
250
ns
/1.5t
0
I tPF IPort 2 Input Data Hold Time
I
I
I (PROG)
I
I
ns
I tDP IPort 2 Output Data Setup Time
I 6t-290 I 710
I
I (PROG)
I
I
ns
Il.St-90 I 160
I tPD IPort 2 Output Data Hold Time
I
I (PROG)
I
I
MCU48-95
TOSHIBA
TMP80CsOAP /-6, TMP80C40AP /-6, TMP80CsOAF /-6,
TMP80CsOAT,TMP80C40AT
TMP80CsOAP-6/TMP80C40AP-6/TMP80CsOAF-6
AC CHARACTRISTICS (CONTINUE)
TOPR=-40·C to 8s·C, VCC=+5V±20%z VSS=OV z unless otherwise noted.
PARAMETER
ITEST
6 MHz
I SYMBOL I
I
I f(t)
I CONDITION I
I MIN. 1 MAX.
I
I
IIO.st-2s011s00 I
I
I tPP IPROG Pulse Width
1 4t-200 1 460 1
I tPL IPort 2 I/O Data SetuE Time (ALE) 1
10.st-30 1 130 1
I tLP IPort 2 I/O Data Hold Time (ALE) 1
(ALE) 1
14.st+l00 1
1 850
1 tPV IPort Out ut Dela Time
3t
1 tOPRRITO Clock Period
500 1
2.5 115.0
1 1St
1 tC'f IC:icle Time
IUNITI
I
I
I ns I
1 ns 1
I ns 1
1 ns 1
I ns 1
1 llS 1
Note: 1. Control Output CL=80pF. BUS Output CL=ls0pF.
2. The f(t) assumes 50% duty cycle on XTALI and XTAL2.
The Max. Clock frequency is 6MHz. and the Min. Clock frequency is
IMHz.
MCU48-96
TMP80CSOAP / -6, TMP80 C40AP /-6, TMP80 CSOAF /-6,
TMP80CSOAT,TMP80C40AT
TOSHIBA
TIMING WAVEFORM
A. Instruction Fetch from External Program Memory
ALE
PSEN
DBO-7
1 - - - tADZ
B. Read from External Data Memory
ALE
INPUT DATA
DBO-7
t------
tADI
MCU48-97
TMP 80 CSOAP / -6, TMP 80 C40AP / -6, TMP 80 CSOAF / -6,
TMP80CSOAT,TMP80C40AT
TOSHIBA
c.
Write into External Data Memory
tCAl
ALE
tcel
tDW
DBO-7
OUTPUT DATA
D. Timing of Port 2 during Expander Instruction Execution
ALE
tpv
PORTl,2
PORT 1.Z DATA
PORT
20-23 PORT ZO-Z3 DATA
PCH
PORT
20-23pORT 20-23 DATA
PCH
PRoe
MCU48-98
'CAl
NEW PORT 1.2
DATA
TMP 80 CSOAP /-6, TMP 80 C40AP /-6, TMP 80CSOAF /-6,
TMP80C50AT,TMP80C40AT
TOSHIBA
POWER DOWN MODE (I) ••••••••• Data Hold Mode in RAM
The operation of oscillation circuit is suspended by setting Ps terminal to
low level after RESET terminal has been set to low level.
Consequently, all
the data in RAM area can be held in low power consumption.
The minimum hold voltage of VCC in this mode is 2V.
P S terminal is se t to high leve 1 to re sume os ci llat ion after VCC has been
reset to SV, and then RESET terminal is set to high level, thus, the normal
mode is restarted from the initialize operation (address 0).
DC CHARACTERISTICS
TMP80CSOAP/40AP,TMP80CSOAF,TMP80CSOAT/40AT: TOPR=O'C to 70'C, VSS=OV
TMP80CSOAP-6/40AP-6,TMP80CSOAF-6
TOPR=-40'C to 8S'C, VSS=OV
1SYMBOL 1
PARAMETER
I
TEST CONDITION
1 MIN. 1 TYP. 1 MAX. 1 UNIT 1
'I
I
I
I
I
I
,
, VSBI 1 Standby Voltage(l) 1
1 2.0 1
1 6.0' V ,
"
I-vc-c-=~SV-,-V-IH-=-V-C-C-~0-.-2V-,--I--I--'--I--1
, ISBI 1 Standby Current(l) ,VIL=0.2V
1
1 0.5 1 10
1 UA
,
AC CHARACTERISTICS
TMP80C50AP /40AP, TMP80CSOAF, TMP80C50AT/40AT :TOPR=O' C to 70'C,VCC=5V±10%,VSS=OV
TMP80C50AP-6/40AP-6, TMP80CSOAF~6
: TOPR=-40'C to 8S'c,VCC=5V±20%,VSS=OV
PARAMETER
I SYMBOL 1
ITEST CONDITION' MIN.! TYP .1 MAX. 1 UNIT 1
I
I,
!
I,
1
I
1
,
, uS ,1
ItPSHR 'Power Save Hold Time (RESET)
10
1
,
,
,
,
,
1
I
I,
,
,
,
,
,
(RESET)
Save
SetuE Time
mS
'tPSSR 'Power
10
,
I
I
I,
I,
1
I,
, tVH
5
uS
'VCC Hold Time (PS)
,
,
,
,
,
I
!
, 5 I
,
, uS ,
'VCC SetuE Time (PS)
'tVS
Note: tCY=2.SUS (fXTAL=6MHz)
,
,
,
,
,
TIMING WAVEFORM
Oiiilr-
Vee
i~
\
"
'r
tVH
\
tvs
I
"
'.I
.
,...
r\~
"
tpSHR
MCU48-99
-'"
tpSSR
,
TMP80 C50AP /-6, TMP80C40AP / -6, TMP80CSOAF /-6,
TMP80CSOAT,TMP80C40AT
TOSHIBA
POWER DOWN MODE (II) .••..••.• ALL Data Hold Mode
The operation of.-£scillation circuit is suspended by setting Ps terminal to
low level after SS terminal has been set to low level. Consequently, all data
can be held in low power consumption.
The minimum hold voltage of VCC in this mode is 3V.
P S termina 1 is set to high leve 1 to resume os ci lla t ion after VCC has been
reset to SV, and then SS terminal is set to high level, thus, the normal mode
is restarted continuously from the state just before the power down mode (II).
DC CHARACTERISTICS
TMP80CSOAP/40AP,TMP80CSOAF,TMP80C50AT/40AT: TOPR=O·C to 70·C, VSS=OV
TMP80CSOAP-6/40AP-6,TMP80C50AF-6
TOPR=-40·C to 85 ·C, VSS=OV
I SYMBOL I
PARAMETER
I
TEST CONDITION
I MIN. I TYP. I MAX. I UNIT I
I
'I
I
I
I
,
I
, VSB2 , Standby Voltage(2) ,
, 3.0 ,
I 6.0' V I
"
'-VC-C-=~5V-,-V-IH-=-V-C-C--0-.-2V-,--,--,--,--,--,
I ISB2 , Standby Current(2) IVIL=0.2V
"
0.5 '10 'llA I
AC CHARACTERISTICS
TMP80CSOAP/40AP,TMP80CSOAF,TMP80C50AT/40AT:TOPR=0·C to 70·C,VSS=5V±10%,VSS=OV
: TOPR=-40~C to 8S·C,VCC=5V±20%,VSS=OV
TMP80CSOAP-6/40AP-6,TMP80C50AF-6
PARAMETER
TE'ST CONDITION' MIN., TYP.' MAX., UNIT'
'SYMBOL'
,
I
I,
,
,
,
'tPSHS 'Power Save Hold Time (SS)
,
I
'tPSSS 'Power Save SetuE Time (SS)
,
I
,'tVH
,'VCC
10
10
I 5
Hold Time (p S)
,
,
'VCC SetuE Time (PS)
'tVS
Note: tCY=2.511S (fXTAL=6MHz)
5
I
I,
,
,
,
,
I,
,
,
,
,
,
,
,
TIMING WAVEFORM
jt-
-~
Vee
r\
1"
"
tVH
55
PS
\
tV5
I
~
'r
...'
~
.,
1'L
t pSHS
NCU48-100
..
r-
tpSS5
I,
,
,
,
,
,
llS
mS
llS
I llS
,
,
,
,
,
,
,
,
TMP80C50AP /-6, TMP80C40AP /-6, TMP80C50AF /-6,
TMP80CSOAT,TMP80C40AT
TOSHIBA
HALT MODE
• 1 HALT INSTRUCTION
OP code is "OIH". HALT INSTRUCTION is an additional instruction to the
'standard 8048/8049 instruction set.
· 2 Entry to HALT MODE
On the
MODE.
execution of HALT
INSTRUCTION,
TMP80CSOA/TMP80C40A enter
HALT
· 3 Status in HALT MODE
The oscillator continues its operation,
internal logic values just prior to the
maintained. Power consumption in HALT
operation. The status of each pins are
however, the internal clocks and
execution of HALT INSTRUCTION are
MODE is less than 50% of normal
described in the following table.
• 4 Release from HALT MODE
HALT MODE is released by either of two signals (RESET,INT).
(1)
RESET Release Mode : An active RESET input signal causes the normal reset
function. TMP80C50A/TMP80C40A start· the program at address "000 H".
(2)
INT Release Mode : An active INT input signal causes the normal operation.
In case of interrupt enable mode (EI MODE), TMP80C50A/TMP80C40A execute
the interrupt service routine, after the execution of one instruction
which is located at the next address after HALT INSTRUCTION.
In case of interrupt disable mode (DI MODE), TMP80C50A/TMP80C40A execute
normal operation from the next address after HALT INSTRUCTION.
• 5 Supply Voltage Range in HALT MODE
The operating supply voltage range and the operating temperature range
are same as in normal operation.
MCU48-101
TMP80CSOAP / -6, TMP80C40AP /-6, TMP80CSOAF /-6,
TMP80CSOAT,TMP80C40AT
TOSHIBA
PIN STATUS IN POWER DOWN MODE (I) (II)
PIN NAME
DBO - DB7
PIO - Pl7
P 20 - P 27
TO
TI
XTALI
XTAL2
RESET, Ss
High impedance
Input disabled
High impedance, input disabled
Input di sab led
High impedance
Output "High" Level
Input disabled when oscillator is stopped.
Pull-up transistors turn off.
Input disabled when oscilltor is stopped.
INT, EA
-RD, -WR,
STATUS
ALE
High impedance
PROG, PSEN
PIN STATUS IN HALT MODE
PIN NAME
DBO - DB7
PIO - P17
P 20 - P 27
TO
Tl
XTALl, XTAL2
RESET, INT
SS, EA
STATUS
Values prior to the execution of HALT
INSTRUCTION are maintained.
Status prior to the execution of HALT
INSTRUCTION is. maintained.
Input disabled
Continue oscillation
Input enabled
Input disabled
RD, WR,
Output "High" leve 1
PROG, PSEN
ALE
Output "Low" level
MCU48-102
TMP 80 CSOAP / -6, TMP 80 C40AP / -6, TMP 80 CSOAF / -6,
TMP80CSOAT,TMP80C40AT
TOSHIBA
OSCILATOR
QUARTZ CRYSTAL
IMHz to 4MHz
f
f = 4MHz to IlMHz
Cl
Cl
C2
C2
30pF
20pF
CERAMIC RESONATOR
f
IMHz to 3MHz
f = 3MHz to IlMHz
Cl
Cl
C2
C2
100pF
30PF
.J;
= SV, Ta = 2S'C, unless otherwise noted.
TYPICAL CHARACTARISTICS: Vee
v CC
C2
- [MAX. TYPICAL CURVE
V OUT - IOL TYPICAL CURVE
VCC
IOL
(V)
(rnA)
6
40
...- .....-
30
5
~/
4
...
3
Icc
fXTAL -
V
10
.-'
10
5
20
15 fXTAL (MHz)
/
/~
I
V
2
4
3
VOUT - IOH TYPICAL CURVE
(PORT 1.2)
1
2
TYPICAL CURVE
ICC
3
5 VOUT(V)
4
(rnA)
-50
10
~.""
-150
V
.~
/
-"
.,.
15 fXTAL (MHz)
~
IOH
(uA)
V OUT - IOH TYPICAL CURVE
(DB .CONTROL)
CRESET - tRESET TYPICAL CURVE
1
2
3
4
(rns)
~/
..".
10
,~
6
3
2
-5
/'
30
-10
V
-15
~.
~"
~~
-20
o. ~J
0.020.03
0.0& 0.1
0.2 0.3 C
(uF) JlESlT
IOH
(mA)
MCU48-103
5 VOUT(V)
/
/
100
60
20
7
-200
10
5
RESET
-100
~
./
5
t
....
/v
......
~
~
V
/
TMP80CSOAP /-6, TMP 80 C40AP /-6, TMP80CSOAF /-6,
TMP80CSOAT,TMP80C40AT
TOSHIBA
OUTLINE DRAWING (DUAL INLINE PACKAGE)
Unit in mm
40
21
><
<
....
.::.
N
~
20
-
%
S1.3MAX
1 S.24
::E
± 0.25
J
I,
I,
if
-
Note: 1.
2.
0.5
± 0.1 S
1.4
± 0.15
2.S4 ±0.25
\
fl~
\
~ O.25~~:~5-+
0-
This dimension is measured at the center of bending point of leads.
Each lead pi t ch is 2. S4mm, and all the leads are located wi thin
±0.2Smm from their theoritica1 positions with respect to No.1 and
No.40 leads.
MCU48-104
TMP 80CSOAP / -6, TMP80C40AP /-6, TMP80CSOAF / -6,
TMP80CSOAT,TMP80C40AT
TOSHIBA
OUTLINE DRAWING (FLAT PACKAGE)
Unit in mm
o 35
0.8 pitch
~
~
•
34
I
3!1
I
I
--.l~
36
I
--IJ
';!.7
-----
38
39
.0
~
I
L
i-L
I
II
41
'2
~
U
CO
vf:::J;/
~
7'
~
t
~
~
"~
IT
I
~ ~
~
J
~ ~ ±
~~-f';~
i
MARKING_+
.
!AREA
L_
1
~
:3 •
-~
~
~
~
~
~
~
~
...
... ...
.
"7
~
~
~J
2:J
1P
lEi
1
16
I
--I
..J
......
..J
0
+I
.
-.:r
0
.-4
15
14
-.
0"
~
~
1.:3
12
S 9 ]011
.
1 . . . ..
i
14.0±0.1
(16.9)
.
-..
MARK
c
U"\
~
c\
J
_If\
- -
.
C
UUUUUJ JUUUUU
---- - - - --
><
<
~
1 45±0 ,3
t-
,
r\
N
r---
. -.....
c
U"\
~
15.2;10.3
0.85.0.3 I
MCU48-105
.
U"\
N
-
TMP 80CSOAP /-6, TMP80C40AP /-6, TMP80CSOAF /-6,
TMP80CSOAT,TMP80C40AT
TOSHIBA
OUTLINE DRAWING (Plastic Leaded Chip Carrier)
unit
6
1 44
40
o
7
39
...
N
17
29
28
17.52:0.12
~
16.6 TYP.
UO 1
Ir-+F
,
•
N
o
~
C""'I
I _. I~~~O.l
~
~
j;.Z7 TY]
~
N
o
OJ,....
N
15.7bTYP.
MCU48-106
in
mm
TMP8048PI, TMP 8035PI
TOSHIBA
8-BIT SINGLE-CHIP MI CROCOHPUTER
GENERAL DESCRIPTION
The TMP8048PI, from here on referred to as the TMP8048 , is a single chip
microcomputer fabricated in N-channel Silicon Gate MOS technology which
provides internal 8-bit parallel architecture.
The follo~ing basic architectural functions of a computer have been
included in a single chip; an 8-bit CPU, 64 x 8 RAH data memory, lK x 8 ROH
program memory, 27 I/O lines and an 8-bit timer/event counter.
The TMP8048 is particularly efficient as a controller.
It has extensive
bit handing capability as well as facilities for both binary and BCD
arithmetic.
The TMP8035PI is the equivalent of a TMP8048 without ROB program memory on
chip. By using this device with external EPROH or RA.t1, software debugging
becomes easy.
FEATURES
• 2.5 ~S Instruc:ion Cycle
· A!.l instruction 1 or 2 c:·c~es
Over 90 instruc:ions; 70~ single
• Easy expandable memory and I/O
• lK x 8 masked ROM
PIN
CONNEeTIO~S
• 0.:. x 8
R..!....~
· 17 I/O lines
r_. __ ...- _
.........·_ ....... c ...
• Single level interrupt
• Single 5V supply
-40·C to +8S·C Operation
(Tor View)
TO
XTALI
XTAL2
Vee (+SV)
Tl
~27
P26
RESET
"SS
INT
P 2S
P24
EA
P17
PI6
PIS
Pl4
Pl3
P1 2
PII
PIO
VDD(+SV)
PROG
P 23
RD
PSEN
WR
ALE
DBO
DBI
DB2
DB3
DB4
DBS
DB6
DB7
(OV)VSS
P22
P 21
P 20
MCU48-107
THP8048PI,TMP8035PI
TOSHIBA
BLOCK DIAGRAM
Oscilla tion
2
Mask ROM
IK
x
8
(Program
Area)
gister!
Decoder
1====::-1
Accumula tor
Bit Test
Circuit
Control and Timing Circuit
XTAL 2
XTAL 1
rnn
1-1
~
"'Cl
c:
"rn
0
~
TNT EA
1-11-4
c:l..t'!j
~
""I
r>
It
III
It
"'Cl"
Ol
"
""1
""I
1-4
~
't:l
If;
....
....
....
"0
""I
"'Cl
c:
"
c:
~
~
c:
M
~
III
rn
~
~
.... ....
~
r>
til
....
" OQ
"1
....
:<
tIl~
It!
SS
>
0.
"I
~
tI'l
M
~
't:l
ALE
t"'">
Ol 0.
PSEN
'---"""'
til
"0
"0.
"
""I
""I
0
rn
tIlrn
It!
r> ""I o
:rlt cr
"
0
""I
cr
~
WR
RD
OQ
"1
Ol
S
C1
III
!"t
Ol
tI'l
"
""I
0
0"'
PROG
tIlM
"x
o
""I't:l
tl
Note 1) The lower order 4 bits of
port 2 output latch are
used also for input/output
operations with the I/O
expander.
cr~
~o.
It!
""I
~
rn
MCU48-108
Note 2) The output latch of port 0
is also used for address
output.
TOSHIBA
TMP 8048PI, TMP 8035PI
PIN NAMES AND PIN· DESCRIPTION
VSS (Power Supply)
Circuit GND potential
VDD (Power Supply)
+SV during operation La,,' power standby pin for THP8048 RAM
vec (Hain Power Supply)
+SV during operation
PROG(Output)
Output strobe for the TMP8243P I/O expander
PIO-PI7 (Input/Output) Port 1
8-bit quasi -bidirectional port (Internal Pullup=SOkQ).
P20-P27 (Input/Output) Port 2
8-bit quasi-bidirectional port (Internal Pullup=SOkn).
P20-P23 Contain the four high order progr~ counter bits during an
external prog~a~ mecory fetch and serve as a 4-bit I/O expander bus for
the TMP8243P.
DBO-~B7
(Input/Output, 3 State)
Co:'!t ~i:1 S
the f: 10'.., order 1='r0 gra::-: counter bits curing a::. external progra::: merr.~
fetch, and receives the addressed instruction under the control of PSEN.
Also contains the address and data during an external RAM data store
instruction, under control of ALE, RD, and WR.
TO
(Input/Output)
Input pin testable using the conditional transfer instructions JTO and
J~~O.
TO can be designated as a clock output using ENTO CLK instruction.
TI
(Input)
Input pin testable using the JTI and JNTl instruction. Can be designated
the event counter input using the timer/STR! CN! instruction.
INT
(Input)
External interrupt input. Initiates an interrupt if interrupt is
enabled. Interrupt is disabled after a reset. Also testable with
conditional jump instruction. (Active Low)
RD
(Output)
Output strobe activated during a Bus read. Can be used to enable data
onto the Bus from an external device. Used as a Read Strobe to External
Data Memory (Active Low).
WR
(Output)
Output strobe during a Bus write (Active Low) Used as a Write Strobe to
External Data Memory.
MCU48-I09
TMP 8048P 1, TMP 80 35P I
TOSHIBA
RESET (Input)
Active Low signal which is used to initialize the Processor.
during Power down.
Also used
ALE
(Output)
Address Latch Enable. This signal occurs once during each ~ycle and is
useful as a clock output. The negative edge of ALE strobes address into
external data and program memory.
P SEN
(Outpu t)
Program Store Enable. This output occurs only during a fetch to external
program memo!y (Active Low).
SS (Input)
Single step input can be used in conjunc.£i.on with ALE to "single step"
processor through each instruction when S5 is low the CPU is placed into
a wait state after it has completed the instruction being excuted.
EA (Input)
External Access input which forces all program memory fetches to reference
exter:::a 1 meCOI:Y-. t' se ful fo:- 12=....1 1a t ion an:i debug and es sent ial for tes t i ng
and program verification. (Active High).
XTAL 1 (Input)
One 5id~ of crystal input fer
al sCI;;:-ce.
int~rnal
oscillator.
Also
~up~t
fer extern-
i..'"IAL 2 (Input)
Other side of crystal input.
FUNCTIO~AL
DESCRIPTION
1. System Configuration
The following system functions of the TMP8048 are described in detail.
(1)
Program Memory
(6) Stack (Stack Pointer)
(2) Data Memory
(7) Flag 0, Flag 1
(3)
I/O Port
(8) Program Status Word (PSW)
(4) Timer/Counter
(9) Reset
(5)
Interrupt Control Circuit
(10) Oscillator Circuit
(1) Program Memory
• The maximum memory that can be directly addressed
4096 bytes. The first 1024 bytes from location 0
internal resident mask ROt-1. The rest of the 3072
memory are external to the chip. The TMP8035 has
memory; all memory must be external.
MCU48-110
by the TMP8048 is
through 1023 can be
bytes of addressable
no internal resident
TMP 8048P I , THP 80 35P I
TOSHIBA
There are three locations 1n Program Memory of special importance.
Address
4095
}1emory Bank 1
2048
2047
1024
Memory Bank 0
1023
Program MemoD' Area
• Location 0
Activating the Reset line of the processor causes the first instruction to be fetched from Location O.
• Loea: :0:-. 3
~. . :;: i '\'" a: :. :1; t ~. e i:l t err u p ~ 1 i :: e c: the pro: c S S ~!'
causes a ju=? to
subrou~ine
define;: by ad:i::-ess
(:.:
h~lc
::"".. t
e :-ru?: e:1 a :: ! e:: )
in Location 3.
• Location 7
A timer/counter interrupt resulting from a timer/counter overflow
(if enabled) causes a jump to a subroutine defined by address held in
Location 7.
• Program address 0-2047 and 2048-4095 are called memory banks 0 and 1
respectively switching of memory banks is achieved by changing the
most significant bit of the program counter (PC) during execution of
an unconditional jump instruction or call instruction executed after
using SEL MBO or SEL MBl.
Reset operation automatically selects Bank O.
(2) Data Memory
Resident Data Memory (volatile RAM) is organized as 64 words by 8-bits
wide •
. The first 8 locations (0 -7) of the memory array are designated as
working registers and are directly addressable by several
instructions. By executing a Register Bank switch instruction (SEL
RBI) locations 24 - 31 are designated as the working registers in
place of 0 - 7.
MCU48-l11
TMP 804 8P I , TMP 80 35P I
TOSHIBA
Address~--------------~
63
Data Memory
32
31 Resister Bank 1
f------------
24
RE1
23----------8 Level Stack
8
("16 byte)
7 -R-;;i-;te~ -B~;k--O
o
REO
Internal Data Memory Area
• RAM locations 8 - 23 serve a dual role in that they contain the ~rogram
counter stack which is a stack 2 bytes wide by 8 levels deep. These
locations stora returning addresses fro= sub~outines. If the level of
subroutine nesting 15 less than the permitted 8, you free up 2 bytes of
~~ for general use for every level of nesting not utilized.
• A.:.L
~
Pointer
1:)ca::'c:15 a:--e in::irectl;" a:::::re5s.:::e thro-.;;l.... eit::er cf t .. c R..!_'::
"'-:--.i::' reside at RO and Rl of the Register array.
R~gisters
• The TX?5048 architecture
allo~s
extension of the Data Memory to 256 words.
(3)Input!Output Ports
• The TMP8048 has 27 I/O lines which can be used for either input or output.
These I/O lines are grouped into 3 ports each having 8 bidirectional lines
and 3 "test'; inputs which can alter program sequences when tested by conditional jump instructions.
• Ports 1 and 2 are each 8-bits wide and have identical characteristics.
Data written to these ports is statically latched and remains unchanged
until rewritten. As input ports these lines are non-latching, i.e •• inputs
must be present until read by an input instruction.
• All lines of Ports land 2 are called quasi-bidirectional because of a
special output circuit structure (illustrated in Figure 1). Each line is
continously pulled to a +5V level through a high impedance resistive device
(SOkn ) which is sufficient to provide the source current for a TTL high
level yet can be pulled low by a standard TTL gate thus allowing the same
p in to be used for both input and output. In order to speed up t he "0"
to "1" transition a low impedance de~ice (Sk<2 ) is switched in momentarily
whenever a "1" is written to line. When a "0" is written to line a low
impedance device overcomes the pullup and provides TTL current sinking
capabi 1 i ty.
MCU48-1l2
T~J' 8048P I , TMP 8035P I
M"L, ORL
+5V
+5V
SOkD
Internal Bus---..........--l D
Q
D-Type
Flip-Flop
CLK
50kr2 I/O pins
Port1 or 2
Q t-r------;
~rite Pulse---r-~----------------~
Inter Buffer
IN
Fig.1
Input/Output Circuit of Port 1, Port 2
· Reset initializes all lines to a high impedance "1" state.
• When external data memory area is not addressed during excution of an
internal prograc, Port 0 (DBO - DB;) beco~es a true bidirectional port
(bus) ~ith associated input and ou:put strobes. If bidirectional feature
n2t needed Bus can serve as either a statically latched output p~rt or
a non-latched input port. However, I/O lines of this port cannot b~
in termixed •
· As a static port data is written and latched using the OUTL instruction
and inputted using the INS instruction these two commands generate
pulses on the corresponding RD and WR strobe lines.
As a bidirectional port the MOVX instructions are used to read and write
the port which generate the RD and WR strobes.
• When not being written or read, the Bus lines are ln a high impedance
s ta te •
(4)Timer/Event Counter
• The 8-bit binary up counter can use either of the following frequency
inputs
(1) Internal clock (1/480 of OSC frequency)
••.••..••••• Timer mode
MCU48-113
TMr 8048PI ,TMP B035PI
TOSHIBA
(2) External input clock form T1 terminal
(minimum cycle time 3 x ALE cycle)
..........•.• Event Counter mode
The CQunter is presettable and readable with two MOV instructions
which transfer the content of the accumulator to the counter and vice
versa. The counter content is not affected by a Reset and is initialized
solely by the MOVT, A instruction. The counter is stopped by a Reset or
STOP TCNT instruction and remains stopped until started by START T
instruction or as an event
counter by a START CNT. Once started
the
counter v,ii 11 increment to its maximum count (FF) and overflow to Zero
continuing its count until stopped by a STOP TCNT instruction or RESET.
The increment from maximum count to Zero (overflow) results in the setting
of an overflow flag and the generation of an interrupt request. When
interrupt acknowledged a subroutine call to Location 7 will be initiated.
Location 7 should store the starting address of the timer or counter
service routine. The state of the overflow flag is testable with the
conditional JUM? (JTF). The flag is reset by excuting a JTF or by RESET.
Figure 2 illu~trates the concept of the timer circui~.
XTAL/IS
1/32
Pre-scaler
Cleared on Start Timer
JTF Instruction
8-Bit Timer!
Counter
Edge Detector
n
Read/Write Enable
Timer Interrupt
Request Flip-Flop
INT
Timer Interrupt Enable
Fig.2
Concept of Timer Circuit
MCU48-114
TOSHIBA
TMP8048PI.TMP803SPI
Conditional Jump Logic
S
JTF
Inst ruction
Timer
Flag F-F
R
Rese,t
Timer Overflow
Q1------1
- - - -.......~ S
Timer Interrupt
Execution------~~
Timer
OverflO1..·
R F-F
Reset
RETR
Instruction
I1\T pin
Interrupt
F-F
ALE
_-~-.... External interrur~ Reccg:-.izec
l-H-~------;
D
Timer interrupt
Recognized
Last cycle
of Instructl.on
r.~
-;
Ins~
ruet io:::
E~c~tion
of
I~~er
rU?t Call l:::struction
Reset-----L-+------------------~
DIS TCNTl
Instruction
Instruction
Fig.3
Concept of Interrupt Control Circuit
(S) Interrupt Control Circuit
. There are two distinct types of Interrupts in the TMPB048.
(1) External Interrupt from the INT terminal
(2) Timer Interrupt caused by timer overflow
MCU48-11S
TOSHIBA
THP8048PI, TMP8035PI
The interrupt system is single level in that once an interrupt is detected
all further interrupt requests are ignored until execution of an RETR
(which should occur at the end of an interrupt service routine) reenables
the interrupt input logic.
· An interrupt sequence is initiated by applying a low level "0" to the I1\T
pin. INT is level triggered and active low "'ihich allows "Wire Oring" of
sever~l interrupt sources.
The interrupt level is sampled every machine
cycle during ALE and when detected causes a "jump to subroutine" at Location 3. As in any call to subroutine, the Program Counter and Program
Status Word are saved in the stack.
· When an overflow occurs in the internal timer/event counter an interrupt
request is generated which is reserviced as outlined in previous paragraph
except that a jump to Location 7 is used instead of ~ If INT and times
overflow occur simultaneously then external request I~~ takes precedence.
• If an extra external interrupt is needed in addition to I~~ this can be
achieved by enabling the counter interrupt, loading FFH in the counter
(one less than the terminal count), and enabling the event counter mode.
A "I" to "0" transition on Tl will cause an interrupt vector to Location 7.
The
1:-.;5:
i~terru?t
service routine pointed to De
reside in oe=:ry be:"'::7:.
a
and
20~7,
ad~resses
i:€"
E~~:
~~
Location 5 or
O.
Figure 3 illustrates the concept of the interrupt control circuit.
(6) Stack (stack Pointer)
• An interrupt or Call to subroutine causes the contents of the program
counter to be stored in one of the 8 register pairs of the Program Counter
Stack. The pair to be used is determined by a 3-bit stack pointer which is
part of the Program Status Words (PSW explained in section (8». Data RA~
locations, 8 through 23 are available as stack registers and are used to
store the program counter and 4-bits of PSW as shown in the figure.
• The stack pointer when initialized points to RAM location 8 and 9. The
first subroutine jump or interrupt results in the program counter contents
being transferred to Locations 8 and 9. Then the stack pointer is incremented by one to point to Locations 10 and 11. Eight levels of subroutine
are obviously possible.
• At the end of a subroutine signalled by a RET or RETR causes the stack
pointer to be decremented by one and the contents of the resulting pair
to be transferred to the Program Counter.
MCU48-116
THP8048PI,TMP8035PI
TOSHIBA
23
7
22
21
6
20
19
5
18
17
4
16
15
3
2
I
I
14
I
I
13
I
I
12
I
11
I
1
I
I
10
I
PSI-'
I
PCS '\, 11
0 ~-------+--------PC4 '\, 7
I PCO'\, 3
0) Flag 0, Flag 1,
9
8
Stack
FA..~
Pointer
Address
(FO, Fl)
The Cl?8048 has t ..·o flags fJ a:1c F1 .... hic~ a:-e used fer conditio::al ju:,::?
....
..
tes:ec
\..,·ith the
conc!.tl~7:a.:.
Thes-e
flags ca~ be set, res:: and
instruction J:O.
FO is a part of the program status word (PSW) and is saved 1n the stack
area when a subroutine is called.
(8) Program Status Word (PSW)
An 8-bit status word which can be loaded to and from the accumlator exists
called the Program Status Word (PSW). The PSW is read by a MOV A, PSI': and
written to by a MOV PSW, A. The information available in the PSW is shown
in the diagram below.
MCU48-117
TOSHIBA
THP8048PI,TMP8035PI
Stack Pointer
/
I C I AC I FO I BS 11 I S2 151 150
MSB
I
II
1_ _ _ _ _ 11
Saved in stack area
at the time of Subroutine Call.
Bits 0 - 2
Bit 3
Bit 4
Spare ("1" during Read)
Stack Pointer Bits(SO, Sl, S2)
Not used ("1" level when read.)
Working Register Bank Switch Bit
(BS)
a
Bank a
Bank 1
1
Bit 5
Bit 6
Flag a (Fa)
Auxiliary Carry CAC) carry bi~ generated by a:; AJD
.'
.
instructio:l.
used by the decica: acj ust lns:ruc:1.c::
Q
DA,
Bit 7
LSB
• • ";'
A (J..C)
Carry (C) flag which indicates that the previous
operation has resulted in the accumulator.
( C)
(9) Reset
The reset input provides a means for initialization of the processor.
This Schmitt trigger input has an internal pullup registor which in
combination with an external l~F capacitor provides an internal reset
pulse
sufficient length to guarantee that all internal logic is
initialized.
r
lkn
--1-O----J\fV\r---~-----Q RESET
IllF
J.
MCU48-118
TOSHIBA
TMP 8048P I, TMP 80 35P I
If the pulse is generated externally the reset pin must be held at ground
(~0.5V)for at least 50mS after the power supply is within tolerance .
. Reset performs the following functions within the chip:
(i)
Sets PC to Zero.
Sets Stack Pointer to Zero.
( iii)
Selects Register Bank O.
(i v)
Selects Memory Bank O.
(v)
Sets BUS (DBO - DB 7) to high impedance state. (Except when EA
( vi)
S~ts Ports 1 and 2 to input mode.
(vii)
Disables interrupts Ctimer and external).
(viii) Stops Timer.
(ix)
Clears Timer Flag.
(x)
Clears FO and Fl.
(xi)
Disables clock output from TO.
( ii )
(10) Oscillator Circuit
TMP8048 can be operated by the external clock input
crystal oscillator as sho~~ below.
~n
additio~
+5V
,.......----~----..y
XTJ.~
1
XTAL 2
20 pF
----~~----~---v
J
2. Basic Operation and Timing
The following basic operations and timing are explained
(1) Instruction Cycle
(2) External Memory Access Timing
(3) Interface with I/O Expander TMP8243P
(4) Internal Program Verify (Read) Timing
(5) Single Step Operation Timing
(6) Low Power Stand-by Mode
NCU48-119
XTAL 2
to
5V)
TMP 8048P I, TMP 80 35P I
TOSHIBA
(1)
Instruction Cycle
· The instructions of TMP8048 are executed in one or two machine cycles,
and one machine cycle contents of five states.
· Fig.4 illustrates its relationship with the clock input to CPU.
el2 clock shown in Fig.4 is derived to outside by ENTO CLK instruction.
· ALE can be also used as the clock to indicate the machine cycle as well
as giving the external address latch timing.
(2) External Memory Access Timing
(i) Program Memory Access
. TIfP8048 programs are excuted in the following three modes.
(1) Execution of internal program only.
(2) Execution of both external and internal progracs.
(3) Executi;n of external prograc only.
The external program memory is accessed (instructions are fetched)
automatically when the internal RO~ address is exceeded in I!::>de (2)
c~ci fro= i~itial sta~: address 0 i~ m~de (3:.
· In the ex:ernal prog:-a::: m-emory access opera:ion, the follc\.:':':lg
~il:'
occur
· The contents of the l2-bit program counter will be output on BUS(DBO DB7) and the lower 4-bits of Port 2.
· Address Latch Enable (ALE) will indicate the time at which address is
valid. The trailing edge of ALE is used to latch the address
externa 11y •
Program Store Enable (PSEN) indicates that an external instruction
fetch is in progress and serves to enable the external memory device.
BUS (DBO - DB7) reverts to Input mode and the processor accepts its
8-bit contents as an Instruction Word.
• Figure 5 illustrates the timing.
(ii) Access of External Data Memory
. In the extended data memory access operation during READ/WRITE cycle the
following occurs
• The contents of RO Rl is output onto BUS (DBO - DB7).
· ALE indciates address is valid. The trailing edge of ALE is used to
latch the address externally.
A read RD or write WR pulse on the corresponding output pins indicates
the type of data memory access in progress. Output data valid at trailing edge of WR and input data must be valid at trailing edge of RD.
Data (8-bits) is transferred over BUS.
MCU48-l20
TOSHIBA
TMP8048PI,THP8035PI
XI/Il.l 1np\lt
(6HHz)
¢l
(2MHz)
Generated
internally ¢2
State
1
2
Instruction
Fetch
Decode
3
Execution
4
Execution
5
Execution
1
(500ns)
1 Statt?
(2.5lJ sec)
r
ALE
Next Address Latch Timing
(400KHz)
Fig.4
Address
P20 - P23
DBO -
Instruction Cycle Timing
Address
Address
DB7
ALE
L
Fig. 5
Timing of External Program Memory Access
MCU48-121
TOSHIBA
n1t' 8048PI, TMP 8035PI
Data Address
Program Address
Program Address
DBO - DB7
In~tructior
ALE
RD (WR)
PSEN
\
\
I
r
\
I
External Data Memory Access Instruction
Suggest we have diagrams
BUS
----~~~----~(
Data
\~---Fig.6
~
BUS
WR
-----~~
\'-------11
Timing of Accessing External Data Memory
MCU48-122
Data
~
TMP 8048P I, TMP 80 35P I
TOSHIBA
. Figure 6 illustrates the timing of accessing the external data memory
during execution of external program.
(3) Interface with I/O Expander (TMP8243P)
The TMP8048 I/O can be easily expanded using the TMP8243 I/O Expander.
THis device uses only the lower half 4-bits of Port 2 for commuication
with the T~W8048. The TMP8243 contains four 4-bit I/O ports which serve
as extensIons of one chip I/O and are addressed as Ports (4-7). All
cOlTID1unication takes place over the lower half of port 2 (P20 - P23) with
timing provided by an output pulse on the PROG pin. Each transfer consists
of two 4-bit nibbles the first containing the "OP Code" and port
address and the second containing the actual 4-bits of data.
+12V
EA
o~r---------------------------------------------------------
RESET 0\_1- - -_ _--!I(f~-~d
~
I)
ALE
DBO- DB7
P20, P2l
--------------~~
~,
Input of Internal
Address
Output of Internal
RO~ Data
RJ~
Input of Inte:-u.al
Fig.7
RO~~
Input of Internal
Address
RO~~
of Internal
Address
I~FU:
Accress
Ro!-1
Timing of Reading Internal Program Memory
5V
5V
10K
5V
F~
D
5
Q
55
74
T
R
Q
ALE
Fig.8
(a)
Single Step Circuit
MCU48-123
nlP 8048P I , TMP 80 35P 1
TOSHIBA
Reading of Internal Program Memory
• The processor is placed in the READ mode by applying +12V to the EA pin and
OV to the RESET pin. The address of the location to be read is
then
applied to BUS and the low order 2-bits of Port 2. The address is latched
by a 0 to 1 transition on RESET and the high level causes the contents of
program memory location addressed to appear on the eight lines of BUS.
· Figure 7 illustrates the timing diagram for·this operation.
(5) Single Step Operation.
· A single step feature useful for debug can be implemented by utilizing a
circuit shown in Figure 8 (a) combined with the SS-pin and ALE pin.
• A D-tL£e flip flop with set and reset is used to generate SSe In the run
mode S5 is held high by keeping the flip flop set. To enter single step,
set is removed allowing ALE to bring SS low via reset input. The next
instruction is started by clocking a "I" into the FF which will not appear
on SS unless ALE is high removing reset. In response to SS going high
the processor begins an instruction fetch which brings ALE low resetting
FF and causing.~~e processor to again enter the stopped state.
The tiffiing diagram in this case is as
show~
in Figure 8 (b). (EA
SV) •
• It-.e L:)\,,-er 'IX? S:.~S has been or ga:n Z'::Cl to a:'lo;,; po;,;er to be removed frow all
but the volatile, 64 x 8 data R&~ array. In power down mode the contents
of data RAM can be maintained while drawing typically 10 - 15% of normal
operating power requirements .
. vee
serves as the SV supply for the bulk of the TMP8048 while the VDD
supplies only the RAM array. In standby mode vce is reduced to OV but VDD
is kept at 5V. Applying a low level to reset inhibits any access to the
RAN by the processor and guarantees that RA.~ cannot be inadvertently
altered as power is removed from vce.
ss
/
P20 - P23
/
\
ALE
DBD - DB7
\
i
i
IL.. _ _ _ _ _ _ _ _ _ _ ..J
'For two
instruction
Instruction Input
Address (PC)
Address (PC)
>-0
X
<
Address (PC+l )
X
Address (PC+l)
Port20 -23
Data
Fig.8(b)
Single Step Operation Timing
MCU48-124
TOSHIBA
INSTRllCTION
ACCUt-1ULATOR INSTRUCTION
I Mnemonic
I
I Instruction Code
Operation
ID7ID6:D5iD4ID3!D2IDl IDOl
I
I ADD A,Rr
I 01 1 I 11 01 1 I rl rl rl (A)(-(A)+(Rr)
I
I
I
I
I
I
I
I
I
I r = 0-7
I ADD A,@Rr
I 01 1 I 1 I 01 01 01 01 r I (A) (- (A) + CCRr ) )
I
I
I
I
I r = 0, 1
I
I
I
I
I
IADD A,1=Data
o! 01 01 0: 01 01 1 I 11 (A)(-(A)+Data
1
! d7i d6! dsl d41 d3 i d21 dl I dO I
I
I ADDC A,Rr
01 1 I 1 I 1 ! 1 ! rl r; r i (A) <- (A)+ (Rr ) + CC)
I
I
I
I
I
I
I
I r = 0-7
I ADDC A ,@Rr
01 1 I 1 I 1 I 0: 01 0: rl (A)(-(A)+(CRr»+
ICc)
1
I
I
I
I
1 I
I
I
I
I
I
I
I
I
I
I r = 0, 1
I AD DCA, {I Da t a
O! O! 01 11 O! 01 11 11 (A) (-(A)-+Data+(C)
Id7Id6!d5!d4!d3!d2IdlldOI
I
IANL A,Rr
I 01 11 01 11 1 I rl rl r I (A) (- (A) and (Rr)
I
I
I
I
I
I
I
I
1 I r = o - 7
IANL A,@Rr
Rr»
I O! 11 0; 1 I ot 01 0: r I CA)(-(A)and
I
I
i I I ! r = 0, 1
I
I
/
I
I AN LA, 4= Dat a II 01 11 0] 11 01 0: 11 11 (A) (-(A) and Data
I
«
nrrS048PI,TMP8035PI
I
I Flag I
:BYtes ICy cles ICTAC I
I
I
I
I
I
I
I
1
1
I
I
I
I
I
1
I
I
I
1
'd7:o6'dS!d4!d3!d2!dl!dO~
/ORL A,Rr
I
/ ORL A,@Rr
I 01 11 61 01 11 rl rl r I (A) <-(A) or (Rr)
I
I
/
I
I
/
1
1 / r = 0-7
I
01 1 I 01 01 01 01 01 rICA)<-(A) or
Rr » I
/
I
!
!
1
: r = o~ 1
I
0' 1: 0' ot 0, 0; I! 1: (A)<-(A) or Data
i
I
I
i 0;':'
.!... ,
: }:F~~ 1-.,
=Dat a
K::-
I
I XRL A,@Rr
I
IXRL A, 4mat a
I
I INC A
IDEC A
1CLR A
/ CPL A
IDA A
1
1SWAP A
/
/
1
2
2
1
2
\
«
C! d6d5:d4'd3'd2'd1:ciO,
1: 0: I; I; ri rl r; (AJ <- (A) EOR (Rr)
I
I
I
I
I
I
I
I
I r = 0-7
I
I 11 1/ 01 1/ 01 01 01 rICA)(-(A) EOR«Rr» I
I
I
I
I
I
I
I
I
I r = 0, 1
I 11 1 I 01 11 01 oi 11 II(A)(-(A) EaR Data
Id7ld6ldsld4ld3!d2ldlldOI
I 01 01 01 11 01 11 1 I 11 (A)(-(A)+1
I 01 01 0/ 01 01 1 I 11 1/(A)<-(A)-1
1 01 01 11 01 01 11 11 II(A)(-O
01 11 11 01 11 11 1/ (A) <-NOT (A)
/ 01
1 01 11 01 11 01 11 1 I IIDecimal Adjust
I
1 1 1 I
I
I
1 I Accumu lat or
1/ 0/ 01 01 1/ 1/ 1/ (A4-7)->(AO-3)
/ 0/
(1 /
/
/
/
1 1 /
/
/
/
I
I I I / / I
MCU48-125
1
1
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
I
I
I
I
I
I
I
1
1
2
2
1
01
I
01
I
01
I
01
I
01
I
I
01
I
-I
I
/
-/ -I
I
2
/
/
1
/
1
1
!
2
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
/
I
2
1
I
I
1
1
2
2
/
I
1
1
1
1
1
1
1
1
1
1
1
1
/
I
I
/
/
1
1
I
1
01
I
01
I
o!
I
01
I
01
I
I
01
I
-I
I
!
I
-I -I
!
!
_I
I
-I
I
/
-I -I
!
:
-' I
-I
I
I
-I -I
/
I
-I -I
-! -I
-I -I
-I -I
01 -I
/
I
-I
-/ -I
1
1
/
/
/
I
TMP8048PI,THP803SPI
TOSHIBA
I
I
Mnemonic
I Instruction Code
I
ID71D6 DsID41D31D21DI1DOI
Operation
I
I
I Flagl
IBytes ICyclesl--cTAc1
1 I 0 I 0 I 1 I 1 I 1 I (An + 1 ) < - (An)
I
1
I
1
I - I - I
I
I
I
I
I In= 0 - 6
I
I
I
I
I
I I I I I (AO) <- (A 7)
I
I
I
I
1 I 1 I 0 I 1 I 1 I 1 I (An + 1 ) < - (An)
I
I
- I - I
I
I I
I I I I I In= 0 - 6
I
I
I
I
I
I
I
I
I
I I I I (C)<-(An
I
I
I I
I
I I
I
I I I I I (AO) <- (C)
I
I
I
I
IRR A
1011
1111011111 II(An)<-(An+l)
I
I
-I -I
I
I I
I
I
I
I
I
In= 0 - 6
I
I
I
I
I
I
I
I
I
I
I
I
I (An < - (AO )
I
I
I
I
IRRC A
1011 1101011111 II(An)<-(An+I)
I
I
-I -I
I
I
I
I
I
I I I In= 0 - 6
I
I
I
I
I
I I
I
I
I
I I I (C) <- (AO)
I
I
I
I
__________~I~I~~I__~I~1~1~1__~i(_A_7)_<_-_(C~)______~1____~I____~~I__ I
I RL A
I
I
I RL C A
I 1I 1
I
I
I
I
I 1I 1
~n?ut/output
.
l.'
•
I
•.neco:llC
lIN A,Pp
I
~ 0 ;.~r.... P;, ~ A
• ;.51. P? ~ ::.: a :. a
Instruction
I ·ins:ruction Code
1
IDiiD6:D5'D4!D3iD2:DliDOi
1
Operatio:!
. B-,tes
I -
I
01 OJ 01 01 11 01 pi P!{A)<-(Pp)
I
I
I
I
I
1 1 1 I P = 1, 2
I
! C' 0: 1 I 1 1 1:
p! p! (p p ) <- ( A)
I
: ? = 1, 2
I· _ G· 1: l' 0, _. ?' (?;:; <- (? P ) a ~:i Data'
I
;c; cE
1
0:
C),c~~c3:c2:cil
:dO' ?
=
I
I
2
I
2
I -I -I
I
I
I
I -I _I
"l
I
I
.:.
-!
-.
1, 2
IORL Pp,#Data I I! 0: O! 01 I! 01 pi pi (Pp)<-(Pp)or Data
I
Id7id6 i dSld41d31d21dlidOI P = 1, 2
IINS A,BUS
101010101 110101 O!(A)<-(BUS)
IOUTL BUS,A
1010101010101 11 O~(BUS)<-(A)
IANL BUS,#Datal 11 01 01 11 11 01 01 01 (BUS)<-(BUS) and
I
Id71d61dSld41d31d21dlidOI Data
IORL BUS,#Datal 11 01 01 01 11 01 01 01 (BUS)<-(BUS) or
1
Id7id6!dSld4Id3Id2IdlldO!Data
IMOVD A,Pp
101010101 11 11 pi pl(AO-3)<-CPp)
I
I
I
I
I
1 1 1 1 I(A4-7)<~0
I
I
I
I
I
1 I
I
IIp=4-7
IMOVD Pp,A
10101 11 11 11 11 pi pl(Pp)<-CAO-3)
I
I
I I I I I I IIp=4-7
IANLD Pp,A
I 11 01 01 11 11 11 pip I (Pp)<-(Pp)and
I
I
I
I
I
I
I
I
I
I (AO- 3)
I
I
I
I
I
I
I
I
IIp=4-7
I
IORLD Pp,A
1110101011111 pi pl(Pp)<-(Pp)or(AO-3)1
I
I
I
I
I
I
I
I
IIp=4-7
I
MCU48-126
!C '
I Flag I
i yc .. es i c;Aci
2
2
1
1
2
2
2
2
1
2
1
2
2
2
I -I -I
I
I
I
I -I -I
I
I -I - I
I -I -I
1
I
1
I -I -I
I
1
1
1 -I -I
1
1
1
1
1
1
1
I
1
1
1
I
1
1
1
2
2
-I -I
1
1
1
-I -I
-I
1
1
-I
1
TMP8048PI,THP803SPI
TOSHJBA
Register Instruction
I Mnemonic
I Instruction Code
I D 71 D 61 D S i D4 ! D 31 D 21 D 1 ! DO
I
I 01 0: 01 1 I 1 I rl rl r
I INC Rr
1
I
I
1 I
I
I
I
I
I INC @Rr
I 01 01 O! 1 1 01 01 01 r
I
I
I
I
I
I
I
I
I
DEC Rr
1 I 1 ! 0: 01 1 ! rl r[ r
I I 1 I I
I
I
Operation
I
I (Rr) <-- (Rr )+ 1
I r = 0-7
I ( (Rr ) ) (Rr )
! I I 1 I I I <1 1 I 1 I I I r =0 - 7
o! 01 1 I 01 01 01 o! rl (A)-->«Rr»
<-1 1 1 1 I 1 I
I
I r = 0, 1
1 1 1 I
0, 0; Ii 1 :
o. O· r, (AO-3)-> (CRrO-3»)
r
0:
I
MOVX A,@Rr
MOVX @Rr,A
MOVP A, @A
MOVP 3 A, @A
(
11
I
11
I
1I
I
11
I
01
I
01
I
01
I
1I
I
01
1
01
I
11
1
11
1
I
I
I
01
1
11
I
01
I
01
1
1
01
1
o!
I
01
I
01
1
I
IBytes
1
I
1
I
1
2
I
I
I
1Cycles
1
1
1
1
1
I
2
!
1
1
1
1
I
I
I
I
I
I
I
I
I
1
2
I
I
2
2
I
2
I
I
I
I
1
.
I
1
1
1
1
1
1
1
1 Flagl
ICTACI
1 -I -I
1 -I -I
1 -I _II
1 I
I
1 -I -I
I
1 I
I -! -I
I
I I
1 -I -I
I
I
I
I
I
,
I -I -I
I
I 1
I -I -I
I
I I
I -I -I
I -I -I
I -I -!
I
1
1 I
I -I -I
1 1 I
,
.1.
<-
r = 0, 1
01 o! r I (A) <-- ( (R r ) )
1 1 I r = 0, 1
01 01 r [ ( ( Rr ) ) <-- ( A)
I I I r = 0, 1
01 11 11 (PCO-7)<--(A)
I I I (A) <-- ( (p C) )
01 11 1 I CP CO - 7 ) <-- (A)
I I 1(PC8-11) <--OOll
1 I 1(A) <-- PC) )
«
MCU48-129
2
I -I -I
1 1 1
1 -I -I
I
I
I
I -I -I
2
I I I
I -I -I
2
2
1
1
1
I
1
1
TMP8048PI,TMP803SPI
TOSHIBA
Timer/Counter Instruction
Mnemon ic
IMOV A,T
I MOV T, A
STRT T
STRT CNT
STOP TCNT
EN TCNT 1
I
IDIS TCNTI
I
Instruction Code
D7 ID61 D5 ! D4 ! D3 ! D2 ID11 DO I
01 1 I 01 01 01 01 11 o I (A) <-- (T)
01 11 1 I 01 01 01 1 I o I (T) <-- ( A)
01 1 I 01 1 i 01 1 I 01 llCounting is
I I I I I I I Istarted in the
I I I I I I ! It imer mode
O! 1 I ot 01 Of 1 I ot 1 ! Count i ng is
I I I I I I I !started in the
I I I I I I I levent counter
I I I I I I I Imode
O! 11 1 I 01 O! 1 I 01 I!Stop both time
I ! I I I I laccumulation and
I I I I I I I levent counting
01 01 1 ! oJ 01 1 I 01 IITimer interrupt
I I I I I I I lis enabled
01 01 1 I 1 i 01 11 01 IITimer interrupt
lis disabled
IBytes
I
1
I
1
I
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I Cycles
I
1
I
1
I
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I Flagl
ICTAcI
I -I -I
I -I -I
I -I -I
I
I I
I I
I -I -!
I I I
I -I -I
I I
I - II -I
I
I I
I I I
I -I -I
I I I
I -I -I
I I I
Control Instruction
Mnemonic
Instruction Code
Operation
IBytes ICyclesl~1
I
I C AC!
D7 D6!DS:D4!D3:D2!Dl!DOI
I
1,
.
0' 0' 0' 0: I! O! 1 ! E>::erna 1 l:::€rrU?t!
1
I
I
! I I ' . enabled
0' 0: 0: 1: 01 1: 0: 1 :Exte~nal inte!"rupt:
1
1
I 1 I
I
I
i
1 1 I lis disabled
1
1 I - -I
1 I 1 I O!
I
I 01 11 01 11 (BS) <-- 0
1 I 1 I 01 11 01 1 1 01 II(BS)<-- 1
1
1 I - -I
1
1
1 1 - -I
1 I 11 1 : 01 01 11 01 11 (DBF)<-- 0
I
1
1 I
11 11 11 11 01 11 01 11 (DBF) <-- I
-I
I
1
1 I - -I
01 11 11 11 01 1 I 01 liTO is enabled to 1
I I I I 1 1 1 lact as the clock 1
1
1
1
I
1
1 1 1 I I 1 I loutput
1 I
01 01 01 01 01 01 01 O!No o:eerat ion
-I
I
1
E~
I
f','
'.)
:l~
DIS I
SEL REO
SEL RBI
SEL MBO
SEL MBI
ENTO CLK
NOP
;
O!
-
MCU48-130
TOSHIBA
TMP8048PI,TMP803SPI
ITMP8048PI/803SPI:
INDUSTRIAL SPECIFICATIONI
ABSOLUTE MAXIMUM RATTINGS
I SYMBOL I
ITEM
IVDD
IVDD SU plY Voltaee (with respect to GND (VSS»
Ivcc
Ivcc SupplY Voltage (with respect to GND (VSS»
IVINA
IInput Voltage (Except EA)
IVINB
IInput Voltage (Only EA)
IPD
!PO,,.:eT Dissipation (Ta = 70'C)
ITSOLDER !Solderin Temperature (Solderin Time 10 sec)
ITSTG
IStorage Temperature
ITOPR
10perating Temperature
I RATTING
I-O.SV to + 7V
-O.SV to + 7V
I-O.SV to + 7V
l-o.SV to + 13V
I
1 • S\-,l
I
260' C
-S5'C to IS0'C
1-40'C to 8S'C
DC CHARACTERISTICS
ITA=-iO' C to 8S' Ci, VCC=VDD=+SV±lO%, VSS=OV, Unless Otherwise Noted.
------:--~--:--
I SY!-1BOL
IVIL
I
IVILI
i
I
i(XrALI,XTAL2~RESET)
IVIH
I
IVIHI
IInput High Voltage
I(Except 11ALI,XTAL2,RESET)
IInput High Vo~
i ______
lVOL
!VOLI
I
IVOL2
IVOL3
I
IVOH
IVOHI
I
I VOH2
I
PARAMETER
!Input Law Voltage
I (Except XTALI ,XTAL2 ,RESET)
IInput Low.. Voltage
ITEST CONDITIONS ! H IN . ITYP . ! MAX. ! UN IT I
1-0.51 0.71 V
I
I
I
I
I
1-0.5! 0.6 V
I
I
I
I
2.21 VCC! V
I
I
I
I
3.8!
veci V
1
~:~(-)~-~,-;~-,.-1~,~-.~-~-.~-:~,-R-E-SE-:~:-~~~------~--------------~--~--~-------r!:
!Output Lo~ Vcl:e~e (BrS)
IOL
1.6 =-!.
. . --'
:0.':'5
~OutPut Lo~ Valts2e
V
IOL
1.6 mA
I (RD', ~~, PSEN, ALE)
I
I
I
I
/Output Low Voltage (PROG)
O.B rnA
I - 10.451 V
I IOL
"
~
!Output Low Voltage
!(For other output pins)
!Output High Voltage (BUS)
1.2 rnA
I IOL
I
I IOH =-280\.lA
I IOH =-BO\.lA
10utpu~Hi~oltage
I(RD, WR, PSEN, ALE)
IOutput High Vol tage
I(For other output pins)
I
I
I
I
I ILl
IInput Leak Current (Tl, INT)
I
I
Ivss
I
I
I
2.41
2.41
I
I 10H =-3011A
I
2.41
VIN
~
- I-
VCC
I
IVSS+O.45~VIN~VCCI
I
I
IVSS+0.4S~VIN~vccl
I
MCU48-131
-
I
~
IILII
I
I
-
I
I
IInput Leak Current
I (PlO-17, P20-P27, EA, S5)
IILO
10utput Leak Current (BUS, TO)
I
I(High impedance condition)
1100
I VDD S upp ly Current
IIDD+ICCITotal Supply Current
-
I
I
I
I
10.451
I
I
I
I
I - I
I
I
I - I
I
I
I
I
I ±Iol
-
I
V
V
V
V
uA
I
- I -
1-7001 uA
I
-
I
I
I ±Iol uA
-
I
I
I 201 rnA
I 14S1 rnA
-
I
I
I
I
-
TMP8048PI,TMP803sPI
TOSHIBA
AC
CHARACTE_RI_S_T_I_C~S____~~
ITA=-40·C to 8s·cl, VCC=VDD=+sV±10%, VSS=OV, Unless Otherwise Noted.
PARAMETER
ITEST CONDITIONS IMIN. ITYP • IMAX. I UN IT I
I SYMBOL I
2001 - I - I ns
I ALE P u 1 seW i d t h
I
I tLL
1201 - I - 1 ns
iAddress Setu2 Time (ALE )
I tAL
I
801 - I - 1 ns
IAddress Hold time (ALE )
1t LA
I
I
1
I
I
I
1
400! ICont'rol Pulse \'-"idth (PSEN ,RD ,\,'R) !
I - 1 ns
1t CC
I
I
1
I
I
1
420[ - 1 - 1 ns
IData SetuE Time (WR)
I tDW
I
I
1
1
I
I
1
1tWD
IData Hold Time (WR)
801 I - I ns
I
2.51 - 115.0 ! lJS
I Cve Ie Time
1tCY
I
1
1
I
1
1
1
ItDR
IData Hold Time (PSEN ,RD)
20 EF
01 - 1 2001 ns
I CL
I
I
1
I
1
1
I tRD
- ! - I 4001 ns
IData InEut Read Time (p SEN, RD) !
I
I
I
I
I
1
I tAW
IAddress SetuE Time (WR)
2301 - 1 - I ns
1
IAddress S~tuD Time (Data InEut) I
1tAD
I - I 600 ! ns
II
I
I
I
I
- -I tAFC
IAddress Float Time (RD z PSEN) I
-40 I
1 - I ns
1tCA
IInternal between Control Pulse 1
101
1 - I ns
I and ALE
I
I
1
I
I
: ~ C?
ns
iF crt C·~~tr~:" Se:tI:' Tit:;-== (F~X)
lIS!
;
I tPC
!Port CO:1tr:Jl H;:,:o Ti1:l7: (PEOG)
ns
65:
I
86:): ns
! tPR
jPort 2 Input Data Sct .,..,;_ ....
I
1(PROG)
I
I
I
I tDP
10utEut Data SetuE Time (PROG)
230 I I ns
ItPD
10utEut Data Hold Time (PROG)
251
I ns
ItPF
IPort 2 Input Data Hold Time
160 I ns
01 I (PROG)
1
I
1
ItPP
IPROG Pulse Width
- 1 ns
9201 ItPL
IPort 2 I/O Data SetuE Time
3001
I ns
It LP
IPort 2 I/O Data Hold Time
- I ns
1201 -
-
-
J.."LLlO;:
-
-
-
-
-
-
Note :tCY=2.slJs, Control Output:CL=80pF, BUS Output: CL=lSOpF, PORT20-23:
CL=80pF.
MCU48-132
TOSHIBA
TMP 8048P I , TMP 80 35P I
TIMING WAVEFORM
A. Instruction Fetch from External Program Memory
tcr
ALE
BUS
B. Read from External Data Memory
ALE
RD
B'CS
C.
~"ite
Data
into External Data Memory
BUS
MCU48-133
TOSHIBA
THP 8048PI, THF 8035PI
D. Timing of Port 2 during Expander Instruction Execution
ALE
PORT20
I
PORT23
(Output Data)
PORT20
PCH
I
PCH
PORT23
(Input Data)
Port
PROG
*
Input Enabled State
TYPICAl CHARACTERISTICS
1) BUS:I OH '" VOH
3) BUS. Pl. P2: 10L - VOL
VDIr VCc=5V
TA=25°C
-50
,.....,
1
'-'
-30
"-
0
-10
o
o
e
..,J
c
"'"r---................
==
0
,~
o
4
VDD-VCC=SV
-500
TA-25°C
-300
1-1
---.
",
o
VOH (V)
---
2
-
~
VOH (V)
MCU48-134
...
,,- ' /
10
-----
2
<::;1
'-'
30
1-1
2) Pl. P2:I OH -VOH
-
VDD=VCc=5V
TA=25°C
50
<
'-'
:::
1-1
-
2
4
TMP8048PI,TMP803SPI
TOSHIBA
TAPE FORMAT
TMP8048 programs are delivered in the form of paper tape with the following
format and it is required to attach the tape list,
The format of paper tape
is same as the Intel type object tape (hexadecimal tape output by Intel MDS
system, PROMPT 48 Development Tool, etc,)
PROGRA~
Tape Format
M )
Leader, 50 ">;L1.L" characten or more
Cor.:ne!1ts
COm::ient (Record mark":" is not included) }
(eR)
Option
I----=---l- - - - -
Record Mark
Record Le!1gth (2 hexadecimal digits)
Loading Address (4 hexadecimal digits)
"00"
Record Type (2 Digits)
Normal Record
"01""., End of File Record
Data
Check
s~
(2 hexadecimal digits)
(en
D-~. characters (RUB::)U!. BLANK) before and after "(CR) (LF)" are
(, -;-J
c~tiC'Clal.
t----=---l -- - --- Record ~:::-k (Re?eatec helo;;)
~
H
R)'
LF
]Trailer, 50 "NIlLL" characters or more
(2) Example of Tape List
TOSHIBA MICRO COMPUTER TLCS-48
:l00000000665C7D79CFSOF3F95lFED55A8FF16E570
:lOOOl00088884DDE67D31F5D8ABA6DF292Fl13F5Cl
:l00020004FFIFB5DFFDAA96A99CF7DF94A346B7C09
:l0003000197352F729F12F79AA9C057C5B851EED77
:l003COOOSDFDB5E556A67277F61A51C631CF9FOE80
:l003DOOOBD2F6F20E8BB1977E3FB5ADIF41FDAA7E2
:l003EOOOB53D42EOEC32546025B7308CDD52063DID
:l003FOOOB4BE9E9E345B6138060B20VC372BF60BD6
:OOOOOOOlFF
MCU48-135
TOSHIBA
TMP 8048P I, TMP 80 35P I
OUTLINE DRAWING
Unit in mm
2]
40
20
-;r
!
I
51.3 MAX
1 5. 24
± 0.25
I
z
0.5
± 0.15
1. 4
± O. 15
2.54 ±O.2S
Note: 1. This dimension is measured at the center of bending point of leads.
2. Each lead pitch is 2.54mm, and all the leads are located within
±0.2Smm from their theoritical positions with respect to No.1 and
No.40 leads.
MCU48-136
1
I
TOSHIBA
THP 804 9PI -6, TMP 8039P 1-6
8-BIT SINGLE-CHIP MI CROCOHPUTER
GENERAL DESCRIPTION
The TMP8049PI-6, from here on referred to as the TMP8049 , is a single chip
microcomputer fabricated in N-channel Silicon Gate MOS technology which
pr6vides internal 8-bit parallel architecture.
The following basic architectural functions of a computer have been
included in a single chip; an 8-bit CPU, 128 x 8 R.-\'~ data memory, 2K x 8 ROM
program memory, 27 I/O lines and an 8-bit timer/event counter.
The TMP8049 is particularly efficient as a controller.
It has extensive
bit handing capability as well as facilities for both binary and BCD
arithmetic.
The TMP8039PI is the equivalent of a TMP8049 without ROM program memory on
chip. By using this device wi th external EPROM Or RAM, software debugging
becomes easy.
FEATURES
•
•
·
•
·
2.S ~S Instruction Cycle
• 128 x 8 RA.11
All instruction 1 or 2 cycles
• 27 I/O lines
Over 90 instructions; 70% single byte • Interval Timer/Event Counter
Easy expandable memory and I/O
• Single level interrupt
2K x 8 masked ROM
• Single SV supply
-40'C to +8S'C Operation
PIN CONNECTIONS (Top View)
TO
XTALI
XTAL2
RESET
Vcc (+S\')
Tl
P27
P26
P2S
P24
P17
~
INT
EA
RD
PSEN
PI6
PIS
PI4
loJR
ALE
DBa
DBI
P13
P1 2
Pli
PIa
VlJD(+SV)
PROG
P23
P22
P 21
DB2
DB3
DB4
DBs
DB6
DB7
P 20
(OV)VSS
MCU48-137
TMP 8049PI -6, TMP 8039PI-6
TOSHIBA
BLOCK DIAGRAM
DBC-DB7
Oscilla tion
2
Frequency
l-f.ask ROM
lK
x
8
(Program
Area)
64 x 8
Decoder t====~
Accumula tor
Bit Test
Circuit
Control and Timing Circuit
XTAL
2
mET lifT
XTAL 1
H
0
:::0
""
n
til
~
til
,.,c: ~.....
til
It)
It)
rT
~
Ol
,.,
H
,..,0
""
=
,.,c:
HH
=
=
"",.,
c:
EA
O-t'!j
,.., :<
rT'"
It) rT
til It)
til ..,
C
enOl
It)
,..,
"0
rT
III
=
~
~
til>
n
0-
rTl
55
en
.....
=
OQ
~
til
en
rT
til
"0
ALE
r'">
Cl 0rTo-
PSEN RD Wit
CIl"'C:!
,..,rT "'"0
OQ
n
"'" o
:Tit)
0'"""
en
,..,rT
0
0'"
til
til
til
til
Ol
51
------
PROG
'='
tr.t'!1
Ol
en
o
Cl
rT
,..,rT
~~
Cl
0'"=0..,til
It)
0'0til"
CIl
MCU48-138
Note 1) The lower order 4 bits of
port 2 output latch are
used also for input/output
operations with the I/O
expander.
Note 2) The output latch of port 0
is also used for address
output.
TMP8049PI-6,T~~8039PI-6
TOSHIBA
PIN NAMES AND PIN DESCRIPTION
VSS (Power Supply)
Circuit GND potential
VDD (Power Supply)
+5V during operation Low power standby pin for TMP8049 RAM
VCC O·1ain PoV.'er Supply)
+SV during operation
PROG(Output)
Outpu t st robe for the TMP 8243P I/O expander
PIO-PI7 (Input/Output) Port 1
8-bit quasi -bidirectional port (Internal Pullup=50kn).
P20-P27 (Input/Output) Port 2
8-bit quasi-bidirectional port (Internal Pullup=50kn).
P20-P23 Contain the four high order program counter bits during an
external program memory fetch and serve as a 4-bit I/O expander bus for
the TM? 8243P :
DBO-DB7 (Input/Output, 3 State)
True bidirectional port which can be written or read synchronously using
the RD, ~~ strobes. The port can also be statically latched. Contains
the 8 lo~ order program counter bits during an external progr~~ mem~
fetch, and receives the addressed instruction under the control of PSEN.
Also contains the address and data during an external ~~ data store
instruction, under control of ALE, RD, and WR.
TO
(Input/Output)
Input pin testable using the conditional transfer instructions JTO and
JNTO. TO can be designated as a clock output using ENTO CLK instruction.
Tl
(Input)
Input pin testable using the JTl and JNTI instruction. Can be designated
the event counter input using the timer/STRT CN! instruction.
INT
(Input)
External interrupt input. Initiates an interrupt if interrupt is.
enabled. Interrupt is disabled after a reset. Also testable with
conditional jump instruction. (Active Low)
RD
(Output)
Output strobe activated during a Bus read. Can be used to enable data
onto the Bus from an external device. Used as a Read Strobe to External
Data Memory (Active Low).
WR
(Output)
Output strobe during a Bus write (Active Low) Used as a Write Strobe to
External Data Memory.
MCU48-l39
TMP8049PI-6,TMP8039PI-6
TOSHIBA
RESET (Input)
Active Low signal which is used to initialize the Processor.
during Power down.
Also used
ALE
(Output)
Address Latch Enable. This signal occurs once during each cycle and is
useful as a clock output. The negative edge of ALE strobes address into
external data and program memory.
PSEN
(Output)
Program Store Enable. This output occurs only during a fetch to external
program memory (Active Low).
55 (Input)
Single step input can be used in conjunction with ALE to "single step"
processor through each instruction when -55 is low the CPU is placed into
a wait state after it has completed the instruction being excuted.
EA (Input)
External Access input which forces all program memory fetches tn reference
external memory. Useful for emulation and debug and essential for testing
and program verification. (Active High).
XTAL 1 (I nput)
One side of crystal input for internal oscillator.
al source.
Also input for extern-
XTAL 2 (Input)
Other side of crystal input.
FUNCTIONAL DESCRIPTION
1. System Configuration
The following system functions of the TMP8049 are described in detail.
(1)
Program Memory
(6) Stack (Stack Pointer)
(2) Data Memory
(7) Flag 0, Flag 1
(3)
I/O Port
(8) Program Status Word (PSW)
(4) Timer/Counter
(9) Reset
(5)
Interrupt Control Circuit
(10) Oscillator Circuit
(1) Program Memory
• The maximum memory that can be directly addressed
4096 bytes. The first 2048 bytes from location 0
internal resident mask ROM. The rest of the 2048
memory are external to the chip. The TMPB039 has
memory; all memory must be external.
MCU4B-140
by the TMP8049 is
through 2047 can be
bytes of addressable
no internal resident
TMP 8049PI -6) TMP 8039PI-6
TOSHIBA
There are three locations 1n Program Memory of special importance.
Address
4095
Bank 1
2048
2047
Memory Bank 0
Program Me!:lor'Y Area
• Location 0
Activating the Reset line of the processor causes the first instruction to be fetched from Location O.
• Location 3
Activating the interrupt line of the processor (if interrupt enabled)
causes a jump to subroutine defined by address held in Location 3.
• Location 7
A timer/counter interrupt resulting from a timer/counter overflow
(if enabled) causes a jump to a subroutine defined by address held in
Location 7.
• Program address 0-2047 and 2048-4095 are called memory banks 0 and 1
respectively switching of memory banks is achieved by changing the
most significant bit of the program counter (PC) during execution of
an unconditional jump instruction or call instruction executed after
using SEL MBO or SEL MBI.
Reset operation automatically selects Bank O.
(2) Data Memory
Resident Data Memory (volatile RAM) is organized as 128 words by 8-bits
wide •
• The first 8 locations (0 -7) of the memory array are designated as
working registers and are directly addressable by several
instructions. By executing a Register Bank switch instruction (SEL
RBI) locations 24 - 31 are designated as the working registers in
place of 0 - 7.
MCU48-I4l
TMP8049PI-6,TMP8039PI-6
TOSHIBA
Addressr---------------~
127
Data Hemory
32
31 Resister Bank 1
f------------
24
RBI
23'----------8 Level Stack
8
(16 byte)
7 r-R~;i;t-e_; -B~;k-O-·
a
RBO
Internal Data Memory Area
•
~~
locations 8 - 23 serve a dual role in that they contain the program
counter stack which is a stack 2 bytes wide by 8 levels deep. These
locations store returning addresses from subroutines. If the level of
subroutine nesting is less than the permitted 8, you free up 2 bytes of
RAM for general use for every level of nesting not utilized.
• ALL 128 locations are indirectly addressable through either of two
Pointer Registers which reside at RO and Rl of the Register array.
~~
• The TMP8049 architecture allows extension of the Data Memory to 256 words.
(3)Input/Output Ports
· The TMP8049 has 27 I/O lines which can be used for elither input or output.
These I/O lines are grouped into 3 ports each having 8 bidirectional lines
and 3 "test" inputs which can alter program sequences when tested by conditional jump instructions.
• Ports 1 and 2 are each 8-bits wide and have identical characteristics.
Data written to these ports is statically latched and remains unchanged
until rewritten. As input ports these lines are non-latching, i.e., inputs
must be present until read by an input instruction.
• All lines of Ports 1 and 2 are called quasi-bidirectional because of a
special output circuit structure (illustrated in Figure 1). Each line is
continously pulled to a +5V level through a high impedance resistive device
(50kn ) which is sufficient to provide the source current for a TTL high
level yet can be pulled low by a standard TTL gate thus allowing the same
pin to be used for both input and output. In order to speed up the "0"
to "1" transition a low impedance device (5kn ) is switched in momentarily
whenever a "1" is written to line. When a "0" is written to line a low
impedance device overcomes the pullup and provides TTL current sinking
capability.
MCU48-142
TMP B049PI -6, TMP B039P 1-6
TOSHIBA
A\L. ORL
+5V
Interual
Bus--~--60-1
+SV
Q
D-Type
Flip-Flop
D
CLK
50kr2 1/0 pins
Portl or 2
Q 1--!-------1
~rite PuIs~-~--~------------~
Inter Buffer
IN
Fig.l
Input/Output Circuit of Port 1, Port 2
• Reset initializes all lines to a high impedance "1" state.
•
~hen
external data memory area is not addressed during excution of an
internal prograc, Port a (DBa - DB7) becomes a true bidirectional port
(bus) with associated input and output strobes. If bidirectional feature
not needed Bus can serve as either a statically latched output port or
a non-latched input port. However, 1/0 lines of this port cannot be
intermixed.
As a static port data is written and latched using the OUTL instruction
and inputted using the INS instruction these two commands generate
pulses on the corresponding RD and WR strobe lines.
As a bidirectional port the MOVX instructions are used to read and write
the port which generate the RD and WR strobes.
• When not being written or read, the Bus lines are in a high impedance
state.
(4)Timer/Event Counter
• The 8-bit binary up counter can use either of the following frequency
inputs
(1) Internal clock (1/480 of OSC frequency)
•..•.••••••• Timer mode
MCU48-143
TMP8049PI-6,TM?8039PI-6
TOSHIBA
(2) External input clock form Tl terminal
(minimum cycle time 3 x ALE cycle)
Event Counter mode
The counter is presettable and readable with two MOV instructions
which transfer the content of the accumulator to the counter and vice
versa. The counter content is not affected by a Reset and is initialized
solely by the MOVT, A instruction. The counter is stopped by a Reset or
STOP TCNT ins t ruct ion and rema ins stopped unt i 1 s ta rt ed by START T
instruction or as an event
counter by a START CNT.
Once started
the
counter will increment to its maximum count (FF) and overflow to Zero
continuing its count until stopped by a STOP TCNT instruction or RESET.
The increment from maximum count to Zero -(overflow) results in the setting
of an overflow flag and the generation of an interrupt request. When
interrupt acknowledged a subroutine call to Location 7 will be initiated.
Location 7 should store the starting address of the timer or counter
service routine. The state of the overflow flag is testable with the
conditional JUMP (JTF). The flag is reset by excuting a JTF or by RESET.
Figure 2 illus~rates the concept of the timer circuit.
Timer
XTAL/15
1/32
Pre-scaler
Cleared on Start Timer
JTF Instruction
8-Bit Timer/
Counter
Tl
Edge Detector
IT
Read/Write Enable
Timer Interrupt
Request Flip-Ylop
U.-rr
Timer Interrupt Enable
Fig.2
Concept of Timer Circuit
MCU48-l44
TM.P 8049PI -6, TMP 8039PI-6
TOSHIBA
Conditional Jump Logic
S
JTF
Inst ruet ion
Timer
Flag F-F
Re set ----:. ~-"
>--+---l R
Timer Overflov:
------------~~~s
Q~------~
Timer
Overflow
Timer Interrupt
.....
E>:ecution-----.:~
I
... c.:_
S S-~
R F-F
RETR
Reset
Instruction
~
~
~
.u
J.Q
tlC "t:
c: c.:
~
~
e,;
...... t::::;
-'
R c:
u
INT pin
InterALE
01-----1
Last cycle
of Inst ruct ~on
__--~~~E>:ternal interCLK
rupt Recognized
Q
}-II-+-..........---------i D
Timer interrupt
Recognized
CLR
E~;
I
Inst ruet ion
s
~
="'=c:,;
Q
~
~"""
a,:
~
... r.:
R ~ ~
IS..... Q
Instruction
~
i:
t.~~ TC~T
~
~
~
c.;
~ ..... ~
Rf:~d.
~
J..
Execution of Interrupt Call Instruction
Reset---~-+----------~
DIS TCNTI
Instruction
Instruction
Fig.3
Concept of Interrupt Control Circuit
(5) Interrupt Control Circuit
• There are two distinct types of Interrupts in the TMP8049.
(1) External Interrupt from the INT terminal
(2) Timer Interrupt caused by timer overflow
MCU48-145
TOSHIBA
TMP8049Pl-6,TMP8039Pl-6
The interrupt system is single level in that once an interrupt is detected
all further interrupt requests are ignored until execution of an RETR
(which should occur at the end of an interrupt service routine) reenables
the interrupt input logic.
· An interrupt sequence is initiated by applying a low level "0" to the INT
pin. un is level triggered and active low which allows "Wire Dring" of
several interrupt sources. The interrupt level is sampled every machine
cycle during ALE and when detected causes a "jump to subroutine" at Location 3. As in any call to subroutine, the Program Counter and Program
Status Word are saved in the stack.
• When an overflow occurs in the internal timer/event counter an interrupt
request is generated which is reserviced as outlined in previous paragraph
except that a jump to Location 7 is used instead of 3. If INT and times
overflow occur simultaneously then external request INT takes precedence.
• If an extra external interrupt is needed in addition to I~~ this can be
achieved by enabling the counter interrupt, loading FFH in the counter
(one less than the terminal count), and enabling the event counter mode.
A "1" to "0" transition on T1 will cause an interrupt vector to Location 7.
The interrupt service routine pointed to be addresses in Location 3 or 7
must reside in memory between 0 and 2047, i,e., Bank O.
Figure 3 illustrates the concept of the interrupt control circuit.
(6) Stack (stack Pointer)
• An interrupt or Call to subroutine causes the contents of the program
counter to be stored in one of the 8 register pairs of the Program Counter
Stack. The pair to be used is determined by a 3-bit stack pointer which is
part of the Program Status Words (PSW explained in section (8)). Data RAM
locations, 8 through 23 are available as stack registers and are used to
store the program counter and 4-bits of PSW as shown in the figure.
• The stack pointer when initialized points to RAM location 8 and 9. The
first subroutine jump or interrupt results in the program counter contents
being transferred to Locations 8 and 9. Then the stack pointer is incremented by one to point to LOcations 10 and 11. Eight levels of subroutine
are obviously possible.
• At the end of a subroutine signalled by a RET or RETR causes the stack
pointer to be decremented by one and the contents of the resulting pair
to be transferred to the Program Counter.
MCU48-146
TMP8049PI-6,TMPB039PI-6
TOSHIBA
23
7
22
21
6
20
19
5
18
17
4
16
15
3
14
13
2
12
I
11
1
10
PSI':'
0
(7) Flag 0, Flag 1,
PCB'\. 11
--------+--------PC4 '\. 7
: PCO '\. 3
Stack
Pointer
(FO, Fl)
9
8
R~X
Address
• The TMPB049 has two flags FO and Fl which are used for conditional jump.
These flags can be set, reset and
tested with the
conditional
jump
instruction JFO.
• FO is a part of the program status word (PSW) and is saved in the stack
area when a subroutine is called.
(B) Program Status Word (PSW)
• An 8-bit status word which can be loaded to and from the accumlator exists
called the Program Status Word (PSW). The PSW is read by a MOV A, PSW and
written to by a MOV PSW, A. The information available in the PSW is shown
in the diagram below.
MCU48-147
TOSHIBA
TMP8049PI-6,TMP8039PI-6
Stack Pointer
/
I C I AC I FO I BS 11 I S2 lSI I SO
MSB I
II
LSB
1_ _ _ _ _ 11
Saved in stack area
at the time of Subroutine Call.
Bits 0 - 2
Bit 3
Bit 4
Spare ("l" during Read)
Stack Pointer Bits(SO, Sl, S2)
Not used ("1" level when read.)
Working Register Bank Switch Bit
(BS)
o
Bank 0
Bank 1
1
Bit 5
Bit 6
Flag 0 (FO)
Auxiliary Carry (AC) carry bit generated by an ADD
instruction and used by the decimal adjust instruction
DA, A CAC)
Bit 7
Carry (C) flag which indicates that the previous
operation has resulted in the accumulator.
(C)
(9) Reset
The reset input provide s a means for ini t ial iza t ion of the proces sor.
This Schmitt trigger input has an internal pullup registor which in
combination with an external l~F capacitor provides an internal reset
pulse
sufficient length to guarantee that all internal logic is
initialized.
lkr2
r-L-o---'V\l\t---l-llF~JP-----a RESET
MCU48-148
TMP 8049P I -6, TMP 8039P 1-6
TOSHIBA
If the pulse is generated externally the reset pin must be held at ground
(~0.5V)for at least 50mS after the power supply is within tolerance •
• Reset performs the following functions within the chip:
(i)
Sets PC to Zero.
Sets Stack Pointer to Zero.
( iii)
Selects. Register Bank O.
(iv)
Selects Mer.;ory Bank O.
(v)
Sets BUS (DBO - DB 7) to high impedance state. (Except when EA
Sets Ports 1 and 2 to input mode.
(vi)
(vii) Disables interrupts (timer and external).
(viii) Stops Timer.
(ix)
Clears Timer Flag.
(x)
Clears FO and Fl.
(xi)
Disables clock output from TO.
(ii)
(10) Oscillator Circuit
TMP8049 can. be operated by the external clock input in addition to
crystal oscillator as shown below.
+5V
2
.----1---V
lOpF
XTAL 1
XTAL 1
XTAL 2
XTAL 2
J;
2. Basic Operation and Timing
The following basic operations and timing are explained
(1) Instruction Cycle
(2) External Memory Access Timing
(3) Interface with I/O Expander TMP8243P
(4) Internal Program Verify (Read) Timing
(5) Single Step Operation Timing
(6) Low Power Stand-by Mode
MCU48-149
5V)
TMP8049PI-6, T~1P8039PI-6
TOSHIBA
(1) Instruction Cycle
• The instructions of TMP8049 are executed in one or two machine cycles,
and one machine cycle contents of five states.
Fig.4 illustrates its relationship with the clock input to CPU.
· 62 clock shown in Fig.4 is derived to outside by ENTO eLK instruction.
• ALE can be also used as the clock to indicate the machine cycle as well
as giving the external address latch timing.
(2) External Memory Access Timing
(i) Program Memory Access
• TMP8049 programs are excuted 1n the following three modes.
(1) Execution of internal program only.
(2) Execution of both external and internal programs.
(3) Execution' of external program only.
The external program memory is accessed (instructions are fetched)
automatically when the internal ROM address is exceeded in mode (2)
and from initial start address 0 in mode (3).
• In the external program memory access operation, the following will occur
• The contents of the l2-bit program counter will be output on BUS(DBO DB7) and the lower 4-bits of Port 2.
• Address Latch Enable (ALE) will indicate the time at which address is
valid. The trailing edge of ALE is used to latch the address
externa lly •
Program Store Enable (PSEN) indicates that an external instruction
fetch is in progress and serves to enable the external memory device.
BUS (DBO - DB7) reverts to Input mode and the processor accepts its
8-bit contents as an Instruction Word.
• Figure 5 illustrates the timing.
(ii) Access of External Data Memory
• In the extended data memory access operation during READ/WRITE cycle the
following occurs
• The contents of RO Rl is output onto BUS (DBO - DB7).
• ALE indciates address is valid. The trailing edge of ALE is used to
latch the address externally.
• A read RD or write WR pulse on the corresponding output pins indicates
the type of data memory access in progress. Output data valid at trailing edge of WR and input data must be valid at trailing edge of RD.
Data (8-bits) is transferred over BUS.
MCU48-1S0
nIT' 80.49PI-6. H1F8039PI- 6
TOSHIBA
XTAU
Input
(6HHz)
H
(2HHz)
-enerated
nternally ¢,2
1
State
2
Instruction
Fetch
3
Execution
Decode
1 State
L
(400kHz)
~ext
Address Latch Timing
Instruction Cycle Timing
Address
Address
Address
P20 - P23
1
1 Cycle
ALE
Fig.4
5
Execution
4
Execution
DBO - DB7
Instruction
ALE
I
I
PSEN
~
\
Fig. 5
!I
\
II
Timing of External Program Memory Access
MCU48-1S1
L
TMP8049PI-6,TMP8039PI-6
TOSHIBA
Data Address
PrOF-ram Address
,....-----.....Program Address
DBO - DB 7
Instruction
Instruction
Input/Output Data
ALE
RD ~)
/
\
PSEN
r
\
\
External Data Mer:::-ry Access Instruction
Suggest we have diagrams
-.J\
Read
ALE
ALE
BUS
BUS
RD
\
Fig. 6
,-
n
Write
0-<
WR
Timing of Accessing External Data Memory
MCU48-152
\
Data
>J
TOSHIBA
TMP 804 9PI -6, T~.P 8039PI-6
Figure 6 illustrates the tlmlng of accessing the external data memory
during execution of external program.
(3) Interface with I/O Expander (TMP8243P)
The TMP8049 I/O can be easily expanded using the TMP8243 I/O Expander.
THis device uses onlY the lower half 4-bits of Port 2 for commuication
with the TMP8049. Th~ TMP8243 contains four 4-bit I/O ports which serve
as extensions of one chip I/O and are addressed as Ports (4-7). All
communication takes place over the lower half of port 2 (P20 - P23) with
timing provided by an output pulse on the PROG pin. Each transfer consists
of two 4-bit nibbles the first containing the "OP Code" and port
address and the second containing the actual 4-bits of data.
+12V~
oJ
EA
::ET
DBO - DB7
__________________________________________________________
------/-i':f-/__~
0\_7
Input of Internal
RO~: Address
PlO, P21
Input of Internal
Address
Output 0 f Internal
Rm~ Data
RO~~
Input of Internal
Input of Internal RON Address
Fig.7
ROH Address
Timing of Reading Internal Program Memory
5V
5V
10K
5S
R~
5V
F-.1
D
S
Q
SS
74
T
R
Q
ALE
Fig.S
(a) Single Step Circuit
MCU48-153
TMP 804 9P I -6, TMP 8039PI-6
TOSHIBA
Reading of Internal Program Memory
The processor is placed in the READ mode by applying +12V to the EA pin and
OV to the RESET pin. The address of the location to be read is then
applied to BUS and the low order 2-bits of Port 2. The address is latched
by a 0 to 1 transition on RESET and the high level causes the contents of
program memory location addressed to appear on the eight lines of BUS.
• Figure 7 illustrates the timing diagram for this operation.
(S)
Single Step Operation.
• A single step feature useful for debug can be implemented by utilizing a
circuit shown in Figure 8 (a) combined w.ith the SSpin and ALE pin.
• A D-t1Ee flip flop with set and reset is used to generate SS. In the run
mode SS is held high by keeping the flip flop set. To enter single step,
set is removed allowing ALE to bring SS low via reset input. The next
instruction is started by clocking a "1" into the FF which will not appear
on 55 unless ALE is high removing reset. In response to SS going high
the processor begins an instruction fetch which brings ALE low resetting
FF and causing the processor to again enter the stopped state.
• The timing diagram in this case is as shown in Figure 8 (b). (EA
5V).
(6) Lower Power Stand-by Mode.
• The Lower TMP8049 has been organized to allow power to be removed from all
but the volatile, 128 x 8 data RAM array. In power down mode the contents
of data RAM can be maintained while drawing typically 10 - 15% of normal
operating power requirements.
• vee serves as the 5V supply for the bulk of the TMP8049 while the VDD
supplies only the RAM array. In standby mode vee is reduced to ov but VDD
is kept at 5V. Applying a low level to reset inhibits any access to the
RAM by the processor and guarantees that RAM cannot be inadvertently
altered as power is removed from vee.
___I
\~----------------------------------\
ALE
/
Instruction Input
~----------~
;
: For two
instruction
~----------~
DBO - DB7 --A-d-d-r-e-s-s--(P-C-)-------~------~(~--A-d-d-r-e-s-s--(-P-e-~-l-)----------
P20 - P23
Address (PC)
)(
)(~__A_d_d_r_e_s_s__(_P_e+_l_)___________
Port 20 - 23
Data
Fig.8(b)
Single Step Operation Timing
MCU48-1S4
TOSHIBA
THPB049PI-6, H1?B039PI-6
INSTRUCTION
ACCUMULATOR INSTRUCTION
I
.
I Instruction Code
I
I
I
I~ I
I Mnemon1.c
ID7ID6ID5ID4/D31D2IDIIDOI
Operation
IBytes ICyclesl clAcl
IADD A,Rr
101 11 1101 11 rl rl rICA)<-(A)+(Rr)
I
1 10101
I
I I I I I I I I Ir= 0-7
I
I I I
I ADD A,@Rr
101111101010101 rl(A)<-(A)+«Rr»
1 I
10101
I
I I I I I I I I I r = 0, 1
I
I I I
IADD A,t:Data
010101010101 11 II(A)<-(A)+Data
2 I
2 10101
d7ld6ld5ld4ld3ld2ldlldO!
I
I I I
I
0\ 11 11 11 11 r\ rl rl(A)(-(A)+(Rr)+(C)
I
1 10101
I ADDC A,Rr
\ I I I \ I \ Ir= 0-7
I
I I I
I
0111111\ 0\ 01 01 rl(A)(-(A)+«Rr»+
I
1 10101
I ADDC A,@Rr
I I I I I I I I (C)
I
I I I
I
I
I I I
I I I I I I I I r = 0, 1
I
10101011101011\ II(A)<-(A)+Data+(C)
2 I
2 10101
Id7ld6;d5id4ld3ld2ldlldOI
I
I I I
101 1\ 01 11 11 rl rl rl(A)(-(A) and (Rr)
1 I
1 I -I -I
I I I I I I I I Ir= 0-7
I
I
I I I
101110111010101 rl(A)(-(A)and «Rr»1
1 I
1 I -I-I
I I I I I I I I I r = 0, 1
I
I
I I I
I 0 I 1 I 0 I 1 I 0 I 0 I 1 I 1 I (A) ( - (A ) an dD at a I
2 I
2 I -I -I
Id71d61d51d41d31d21dlidOI
I
I
II I
1 I
1 I -I -I
101 110101 11 rl rl rl(A)<-(A) or (Rr) I
I I I I I I I I I r= 0-7
I
I
I I I
101 110101010101 rl(A)<-(A) or «Rr»1
1 I
1 I -I -I
I I I I I I I I I r = 0, 1
I
I
I I I
2 I
2 I -I -I
I 01 11 01 01 01 01 11 11 (A)<-(A) or Data I
Id7Id6!d5!d4Id3Id2IdlldOI
I
I
I I I
1 I
1 I -I -I
I 11 1101 1 11 rl rl rl(A)<-(A) EOR (Rr) I
I I I I
I I I I r= 0-7
I
I
I I I
XRL A,@Rr
11111011 010101 rl(A)<-(A) EOR«Rr»I
1 I
1 I -I -I
I I I I
I I I I r = 0, 1
I
I
I I I
XRL A,~tData
2 I
2 I -I -I
I 11 11 01 1 01 01 11 11 (A)<-(A) EOR Data I
Id71d61d51d4 d31d21dlidOI
I
I
I I I
INC A
1010101 1 01 11 11 lICA)<-(A)+l
I
1 I
1 I -I -I
DEC A
10101010 01 11 11 11(A)<-(A)-1
I
1 I
1 I -I -I
CLR A
I 0 I 0 I 1 I 0 0 I 1 I 1 I 1 I (A) <-0
I
1 I
1 I -I - I
CPL A
10101111 011111 11 (A)<-NOT (A)
I
1 I
1 I -I-I
DA A
10111011 011111 I1Decima1 Adjust
I
1 I
1 101-1
I I I I
I I I I Accumulator
I
I
I 1 1
ISWAP A
I 01 11 01 0 01 11 11 11 (A4-7)->(AO-3)
1
1 I
1 1 -I -I
I
I I I I
I 1 I I
POO
/DO
P07
07
'V
'V
~ ~ P10
P17
A7
'V
/AO
'V
~ ~P 20
'V
-
'---
~
I-
"-
r.
PORT
2
/ A8
P27
A15
'V
I--
f-
TIMER
f+
8BIT 2CH !:::I(TlMER2/3)
i-
ROM
(8 KB)
r-
TlMER/ EVENT ~
COUNTER
l6BIT lCH 10(TlMER4)
-t--
;:: PORT
3
t--
~
r---p 35/RD
r---p 36/WR
-
P 37/WAIT
40
~P~RT~ >P/ A16
rL
Fig. 1
eLK
EA
..- t-- RESET
...... -
~
I-
'---
P81/INT1/TI4 - f - P82/INT2/TI5 - f - P83/T03/T04
~
--
.-
TIMER
8BIT 2CH
(TlMERO/l)
t-- VSS(GND)
LJl~
--
r-
....
....
..-. f - VCC
CPU
A
F
B
C
0
E
H
L
A'
F'
B' C '
E'
0'
H' L'
IX
IY
SP
PC
TMP90C840 Block Diagram
MPU90-2
'V
P43
A19
'V
TMP90C840
TOSHIBA
2.
PIN ARRANGEMENT AND FUNCTIONS
The arrangement
described below.
2.1
of
input/output
pins,
their
names
and
functions
are
Pin Arrangement
Fig. 2.1 shows where the input/output pins are located in the TMP90C840.
VREF
1
AGND
2
(ANO) p50
(ANI) PSI
(AN2) p52
3
(AN3) P53
(AN4) P54
(AN5) P55
(TOI/MOO) p60
(MOl) P61
(M02) P62
(M03) P63
Vee
62
P37 (WAIT)
P36 (WR)
5
60
P35 (RD)
P34 (CTS)
6
7
8
59
P33 (TxD)
9
10
56
P32 (TxD/RTS/SCLK)
P31 (RxD)
P30 (RxD)
4
11
EA
P43 (A19)
12
P42 (A18)
(T03/MIO) P70
(MIl) P71
(Ml2) P72
(Ml3) P73
(INTO) P80
13
14
P41 (Al7)
P40 (A16)
15
16
P27
(INTl/TI4) P81
(INT2/TIS) P82
18
(T03/T04) P83
NMI
RESET
CLK
(DO) POO
(Dl) POI
(D2) P02
(D3) P03
(D4) P04
(DS) P05
(D6) P06
(D7) P07
(GND) Vss
Fig. 2.1-(1)
55
(Al~)
P26 (A14)
P25 (A13)
P24 (A12)
17
P23 (All)
P22 (AIO)
P21 (A9)
P20 (AB)
19
20
21
22
PI7 (A7)
P16 (A6)
23
24
25
26
40
39
27
28
29
36
30
35
31
32
PIS (AS)
P14 (A4)
P13 (A3)
P12 (A2)
Pll (AI)
PIO (AO)
X2
Xl
Pin Arrangement (Shrink Dual Inline Package)
MPU90-3
H
oUl
::t:
H
~
b:I
>
)C
C
iiii
~~t:.e
£1
~I
»I~~
~~~
>-in
5 ~ 21~ EE
"O"O"O"O~:s<"O"O"O"O"O"O
1J11JI1JI1JI2t:ioww .... www
I'%j
.....
WNt"'OC"lO-./C7\VI.c.w N
O'Q
N
......
I
.r-.
N
....
P
'"d
~
c:
\0
o
I
.p-
>
11
11
III
p
O'Q
CO
S
CO
p
rt
.r-.
>z:I
......
III
rt
'"d
III
(AN41
(ANSI
(TOlmO)
(MOL)
(M02)
(MOl)
(TOl/MlO)
(1-111)
(Ml2)
(Mll)
(INTO)
(INT1/TI4)
(INT2/TIS)
(TOl/T04)
P3l (RxO)
P30 (RxOI
PS4
PS5
P60
PH
P62
P6l
P70
PH
EA
P43
P42
P41
P40
P27
P26
P2s
P24
P23
P22
PH
P20
P17
P16
P1S
p14
peo
pel
pe2
pe3
NMI
RESET
eLK
(DO) POO
(01) POL
(A19)
(A18)
(A17)
(A16)
(A1S)
(A14)
(All)
(A12)
(All)
(AlO)
(A9)
(A8)
(A7)
(A6)
(AS)
(M)
(')
l"
III
O'Q
CO
;g;g;g;g;g;g~~~~~~~
Nw.c.IJIC7\-./1II
Ot"'NW
22~&&~2
------2
;;;;;;;;
e!:~~
~
'"d
\0
o
()
00
.pO
TOSHIBA
2.2
TMP90C840
Pin Names and Functions
The names of input/ output
Table 2.2.
Table 2.2
pins
and
their
funct ions
are
summarized
~n
Pin Names and Functions
Function
Port 0:
8-bit I/O port that allows selection of input/output on byte basis
Data bus:
Also functions as 8-bit bidirectional data bus for external memory
Port 1: 8-bit I/O port that allows selection on byte basis
Address bus:
The lower 8 bits function as
address bus for external memory
Port 2:
8-bit I/O port that allows selection on bit basis
/
--------------------------------------------1
Address bus:
The upper 8 bits function as /
address bus for external memory
Port 30:
I-bit input port
1
Serial data receiving
Port 31:
I-bit input port
1
Serial data receiving
Port 32:
l-bit output port
/
/
/
/--------------------------------------------1
1
1
/
1--------------------------------------------/
1
1
1--------------------------------------------/
Serial data transmission
/
/--------------------------------------------/
/ Request serial data transmission
/--------------------------------------------/
/ Serial clock output
1 Port 33: I-bit output port
1
1--------------------------------------------1
1
1
1
Serial data transmission
/ Port 34:
l-bit input port
1
/
1
/--------------------------------------------1
Ca able of serial data transmission
/
Port 35:
I-bit output port
1
1--------------------------------------------1
1
1
1
1
Read:
Generates strobe signal for reading
external memory
Port 36:
l-bit output port
1
1
1
/--------------------------------------------1
1
1
1
Write: Generates strobe signal for writing
into external memory
Port 37:
l-bit input port
1
memory or peripheral LSI
1
1
1
1--------------------------------------------1
Wait:
Input pin for connecting slow accessl
1
1
MPU90-5
TOSHIBA
TMP90C840
I
I No. of
I/O
I
Pin
Name I
Function
1__
~____-+__p~1_'n~s__~~3__
st_a_t~e_s-+I________~~~__________________________
I P40 - P431
4
Output I Port 4: 4-bit output port that allows
I
I
I selection of port/address bus on bit basis I
--------------------------------------------
I/A16 - A191
I
I
I Address bus: Also functions as address busl
I
I
I for external memory (4 bits of bank
I
I__~__~~I__~--~--------~I--ad-d-r-e~s~s~)~~--~-----------------------1
Ipso - PSSI
6
Input
I Port 5: 6-bit input port
I
I
I
1--------------------------------------------1
llANO
AN51
I Analog input: 6 points for analog input
I
I
I to A/D converter
I~VR~E~F~---+I--~l~~---------+I~In~p~u~t~o~f~r~ef~e~r~e~n-c-e--vo~lt-a-g-e--t-o-A-/~D~--------
I________-+I______-+________-+I~co~n~v~e~r~t~e~r______~----------------------I~AG~N~D~--~I--~l~~----~--_+I~Gr~o~u~n~d~p~i~n-f~o~r~A~/~D~c~on~v~e~r~t~e~r________~---I P60 - P631
4
I/O
I Port 6: 4-bit I/O port that allows I/O
I
I
I selection on bit basis
I/MOO - M031
1-------------------------------------------I/T01
I
/Output I Stepping motor control port 0
I
1I
I
1-------------------------------------------Output of Timer 0 or 1
/Output I Timer output 1:
I--P-70-----P-7-3+1----4--~--~I/~0~--+I--Po-r-t~7~:--~4--b-1~·t~I~/~O--p~or-t--t~h-a-t~a~I-lo-w-s~I~/~O----
I
I
I/M10 - M131
/T03
I
1
I
1
/INTO
I
I
I selection on bit basis
1-------------------------------------------/Output I Stepping motor control port 1
1--------------------------------------------1
/Output 1 Timer output 3: Output of Timer 2 or 3
Input
I Port 80: I-bit input port
P81
I
I
1
Input
I
P80
/INT1
/T14
II
1-------------------------------------------I Interrupt request pin 0: interrupt request
I
/INT2
/T15
I
I
1-------------------------------------------1 Timer input 4: Counter/capture trigger
1
1
Input
1
I
signal for Timer 4
Port 82: I-bit input port
1-------------------------------------------I Interrupt request pin 2: rising edge in-
1-------------------------------------------I Timer input. 5: capture trigger signal for
1
1
Output
/T03/T04 1
NMI
I
I
1
Input
I
1
I terrupt request pin
I
I
I
P83
1-------------------------------------------I Interrupt request pin 1: interrupt request
I pin (Level/falling edge is programmable)
I
1
I
P82
I pin (Level/rising edge is programmable)
I Port 81: I-bit input port
I Timer 4
Port 83: I-bit output port
1
1-------------------------------------------I Timer output 3/4: Output of Timer 3/4
I Non-maskable interrupt request pin:
Falling edge interrupt request pin
1
MPU90-6
TOSHIBA
Pin Name
CLK
TMP90C840
No. of
pins
1
I/O
3 states
Output
1
Input
Xl/X2
2
Input
Input/
Output
Vcc
Vss(GND)
1
EA
RESET
1
Function
Clock output: Generates clock pulse at 1/4
frequency of clock oscillation. It is a
high-level while resetting.
External access: Connects with Vcc pin in
the TMP90C840 using internal ROM, and with
GND pin in the TMP90C841 with no internal
ROM.
Reset
Pin for quartz crystal oscillator
Power supply pin (+5V)
Ground pin (OV)
MPU90-7
TOSHIBA
3•
TMP90C840
OPERAT ION
This chapter describes the
TMP90C840 in every block.
3.1
functions
and
the basic
operations
of the
CPU
The
TMP90C840 incorporates a high-per formance 8-bi t CPU.
This CPU
its speed of processing, addressing and executing instructions
compared to the conventional 8-bit versions.
This section describes the CPU functions available to the programmer.
improve~
3.1.1
Memory map
The TMP90C840 supports a program memory of up to 64K bytes and a data
memory of maximum 1M bytes.
The program memory may be assigned to the address space from OOOOOH to
OFFFFH, while the data memory can be allocated to any address from
OOOOOH to FFFFFH.
(1)
Internal ROM
The TMP90C840 internally contains an 8K-byte ROM.
The address space
from OOOOH to lFFFH is provided to the ROM. The CPU starts executing
a program from OOOOH by resetting.
The addresses OOlOH to 007FH in this internal ROM area are used for
the entry area for the interrupt processing.
(2)
Internal RAM
The TMP90C840 also contains a 256 byte RAM, which is allocated to the
address space from FECOH to FFBFH.
The CPU allows the access to a
certain RAM area (FFOOH to FFBFH, 192 bytes) by a short operation code
(opcode) in a "direct addressing mode".
The addresses from FFlOH to FF7FH in this RAM area can be used as
parameter area for micro DMA processing (and for any other purposes
when the micro DMA function is not used).
(3)
Internal I/O
The TMP90C840 provides a 48-byte address space as an internal I/O
area, whose addresses range from FFCOH to FFEFH. This I/O area can be
accessed by the CPU using a short opcode in the "direct addressing
mode".
Fig. 3.1 (1) is a memory map indicating the areas accessible by the CPU
in the respective addressing mode.
MPU90-8
TOSHIBA
TMP90C840
OOOOOH
02000H
Program & Data Area
Data Area
External Memory
(56K byte)
(BC)
(IX)
(IY)
(IX+d)
(IY+d)
(DE)
(HL)
(SP)
(SP+d)
(HL+A)
(nn)
OFECOH
OFFOOH
I
OFFCOH
Direct Area
(n)
OFFFOH
External Memory
(16 byte)
lOOOOH
External Memory
(960K byte)
FFFFFH
~--------------~
Fig. 3.1 (1)
Memory Map
MPU90-9
TOSHIBA
3.1.2
TMP90C840
Registers
Fig. 3.1 (2) shows the configuration of registers.
7
0
I_ _~_ _-+-_ _~_ _ I
I
I
I
I
I
I
Main registers
Alternative
registers
3
0
15
0
Special purpose
registers
Fig. 3.1 (2)
Configuration of Registers
The TMP90C840 uses main registers, alternative registers and dedicated
registers.
The main registers and the alternative registers are
allowed to be exchanged of their contents by a register exchange
instruction.
(1)
Register A
This is an 8-bit register used mainly for 8-bit arithmetic and logic
operations.
(2)
Register F
This is an 8-bit register that stores the status of operation results.
Configuration of register F is shown in Fig. 3.1 (3).
7
6
5
4
3
2
1
o
MSB I S I Z IIFFI H I X Ip/vl N I C I LSB
Fig. 3.1 (3)
o
o
Configuration of Register F
Sign flag (S)
The sign flag is set to "1" when the arithmetic result is negative.
It stores the contents of the most significant bit (MSB) of the
arithmetic and logic unit (ALU).
Zero flag (Z)
Z flag is set to "I" when the all bits of the ALU after operation are
"0".
MPU90-10
TOSHIBA
TMP90C840
o
Parity/Overflow flag (P/V)
This flag has two funct ions.
One is to indicate the parity (p)
resulted from a logical opepration (AND, OR, or XOR).
It is set to
"I" when the result is even, and "0" for odd parity.
The other is to indicates the overflow (V) in an arithmetic operation
(ADD, ADC, SUB, SBC, or CP).
The flag is set to "I" when the result
cannot be expressed by a signed integral number.
The P/V flag selects either function according to the instruction.
o Carry. flag (C)
The flag is set to "I" if a carry or borrow has occurred on the MSB of
the ALU.
o Expansion carry flag (X)
Like the carry flag (C), it is set to "I" when the MSB of the ALU
involves a carry or borrow as a result of an operation except that it
applies to a wider range of instructions (e.g., INC rr).
o Half carry flag (H)
It is set to "1" when a carry or borrow has occurred on the 4th bit of
the lower side in the ALU.
o Addition/Subtraction flag (N)
This flag is set to "I" if the executed operation is a subtraction
(SUB, SBC, CP, or DEC).
o Interrupt enable flag (IFF)
A maskab Ie interrupt is enab led or disab led by this flag.
This flag
is set to "I" by an EI instruction and "0" by an DI instruction.
(Note) This flag is shared with the alternative register F'.
(3)
Registers B, C, D, E, Hand L
All these registers have an 8-bit configuration.
They function as
16-bit register pairs (concatenated BC, DE and HL) as well as
independent 8-bit register.
Registers B or register pair BC is also
used as a counter for the loop instruction (DJNZ).
Register pair HL
is used for 16-bit data processing including l6-bit arithmetic/logic
operations.
(4)
Registers A', F', B', C', D', E', H' and L'
These registers have the same structure as the main registers (A, F,
B, C, D, E, Hand L). They are called alternat ive registers.
There
is no instruction that directly accesses these alternative registers,
but its data can be processed by a register exchange instruction.
Following are examples of register· exchange insturctions that allow
the exchange of data between a main register and an alternative
register:
EX
AF,AF'
EXX
(5)
Registers IX, IY, BX and BY
IX and IY are 16-bit independent
and BY are 4-bit independent
registers.
These registers are used mainly
generate 20- bit addresses.
IX
16-bit additions.
registers called index registers.
BX
registers and referred to as bank
for specifying memory addresses,
and IY registers are also used
MPU90-11
and
for
TOSHIBA
TMP90C840
BX and BY registers are allocated to the memory addresses FFECH (BX
register) and FFEDH (BY register) in the internal I/O address spaces.
Only their lower four bits are effective, with the upper four bits
being undefined. These undefined .bits are always set to "1" when reat
out.
By resetting, the lower four bits of BX and BY registers are
initialized to "0".
BX
I - I - I - I - IBX3IBX2IBXlIBXOI
(FFECH) -------------------------------
R/W
BY
I - I - I - I - IBY31BY21BYliBYOI
(FFECH) -------------------------------
R/W
(6)
SP register
SP register is a l6-bit register called a stack pointer (SP), that
stores the start address of the memory stack area (Last in, first out
basis). It is decremented when a CALL or PUSH instruction is executed
or an interrupt is accepted.
It is incremented by execution of RET
instruction or a POP instruction.
(7)
PC register
This is a l6-bit register called a program counter, and stores the
memory address of the next instruction to be executed.
It is initialized to OOOOH when the RESET pin becomes low.
(8)
Other
By executing the data exchange instruction [EXX] between a main
register and an alternative register, the EXF bit (exchange flag: Bit
1 of memory address FFD2H) of the internal I/O register is inverted.
This is a read-only bit, and is not initialized by resetting.
3.1.3
Addressing modes
Eight addressing modes are available for the TMP90C840. They are used
in combination with various instructions to enhance the CPU's
processing capabilities.
They are: Register mode, immediate mode, register indirect mode, index
mode, register index mode, extend mode, direct mode and relative mode.
The
The first seven addressing modes are used most frequently.
relative addressing mode is only applicable to specific instructions.
(1)
Register addressing mode
In the register addressing mode, the operand represents a specified
register.
Example:
LD A, B
The contents of Register B are loaded into Register A.
(2)
Immediate addressing mode
In this mode, the operand is in the instruction.
Example:
LD A, 12H
Immediate data "12H" are loaded into Register A.
MPU90-l2
TOSHIBA
(3)
TMP90C840
Register indirect addressing mode
In the register indirect addressing mode, the operand is located in a
memory address indicated by a register pair (SC, DE, ilL, IX, IY or
SP).
Example:
LD A, (HL)
Memory
CPU
I
A
HL
"45H"
(4)
~n
12
0
45
1<-1-----1
1
1
45
2000H
I
o 1 1
0
1
the memory address 2000H is loaded into Register A.
Index addressing mode
In the index addressing mode, the operand is located in a memory
address specified by adding an 8-bit displacement value in the opcode
to the contents of a specified register pair (IX, IY or SP).
Example:
LD A, (SP+2)
Memory
CPU
I
A
1<-1------1
1
67
67
3002H
1
1
SP
1_3~_O__
O_O_1
1
--------------------1
"67H" in the memory address 3002H is loaded into Register A.
displacement value ranges from -128 to +127.
(5)
The
Register index addressing mode
In this mode, the operand is located in a memory address specified by
adding the displacement value of Register A to the contents of
register pair HL.
Exampl e:
LD B, (HL+A)
MPU90-13
TOSHIBA
TMP90C840
Memory
CPU
I
A
B
HL
12 0
1 1
1
89 1<-1------ 1
1
0 0
1
1
03
89
2003H
"89H" in the memory address 2003H is loaded into Register B. In this
mode, the data in Register A are considered as 8-bit signed number,
and the displacement value ranges from -128 to +127.
(6)
Extended addressing mode
In this mode, the operand is accessed by 2-byte (16-bit) data in the
opcode.
Example:
LD A, (2000H)
Memory
CPU
1
A
.-..,;.4.;;,...5_I <-1-----1
1
45
2000H
1
I
1
-------------------1
"45H" in the memory address 2000H is loaded into Register A.
(7)
Direct addressing mode
The operand in this mode is located in a memory address from FFOOH to
FFFFH specified by I-byte (8 bits) data in the opcode. Compared with
the extended addressing mode, it saves both program memory and
executing time.
This mode allows the access to 256-byte addresses
from FFOOH to FFFFH •
• or the TMP90C840, this direct area is divided into the internal RAM
(192 bytes from FFOOH to FFBFH) and the internal I/O area (48 bytes
from FFCOH to FFEFH).
MPU90-14
TOSHIBA
TMP90C840
Example:
LD
A, (FFIOH)
Memory
CPU
1
A
~5...;..6_I
<-1-----1
1
56
FFIOH
1
1
1
--------------------1
"56H" in the memory address FFlOH is loaded into Register A.
(8)
Relative addressing mode
In the relative addressing mode, the operand is found at the address
relat ive to the current inst ruction.
This mode is applicable to
instructions involving an 8-bit displacement value (JR and DJNZ) and a
16-bit displacement value (LDAR, JRL and CALR).
Example:
JR 2034H
Memory
C8
32
2000H
2001H
2002H
JR instruction
In this example, the program execut ion jumps to the address 2034H.
Since the program counter is already incremented by 2 at the time of
address computation, the displacement is obtained by the following
formula based on the "memory addres s of the JR inst ruc t ion + 2":
Destination address
(address of instruction being executed
+ 2)
In the example, the displacement "32H" is obtained by:
2034H
(2000H + 2)
In any other instructions using the relative addressing mode (DJNZ,
LDAR, JRL and CALR) , the displacement is always calculated based on
the "address of the current instruction + 2".
MPU90-15
TOSHIBA
(9)
TMP90C840
Addressing modes for extended data area
The TMP90C840 provides up to 1M bytes of data.
The addresses OOOOOH to OFFFFH can be accessed in a normal addressing
mode.
However, the addresses from IOOOOR to FFFFFH called an "extended data
area" require a special addressing mode for access.
Accessing the extended data area requires to select the addressing
mode which uses the index register IX or IY for obtaining the address
of the operand (the register indirect addressing mode or the index
addressing mode).
The following four special modes are available:
(IX)
(IY)
(IX+d)
( IY+d)
In these modes, the extended data area is accessed by using a 20-bit
address consisting of a 16-bit offset address (address bus AO to A15)
and a bank address (address bus A16 to A19).
The 16-bit offset address is obtained by the same way as in a normal
address computation. The 4-bit bank address is specified by the bank
register BX or BY.
The register pair BX is selected when the index
register IX is used, and BY is selected when IY is used.
LD
Example:
A, (IX)
Memory
CPU
A
45
1
1<-1-----1
1
45
1
1
BX
1
6
1
IX
I
2 0 0 0
11
---------------------------_1
"45H" in the address 62000H is loaded into Register A.
MPU90-l6
62000H
TOSHIBA
TMP90C840
In the index addressing mode, a carry resulted from calculating the
16- bit offset address is ignored; i. e., it is not added to the bank
address.
Example:
LD
A, (IY+23H)
Memory
CPU
A
45
1
1<-1-----1
1
60013H
45
1
1
BY
1
6
1
IY
1
F F F 0
11
---------------------------1
In this example, "45H" in the address 60013H is loaded into Register
A.
In any other addressing mode that accesses a non-extended data area
(the index register IX or IY is not used for address computing of the
operand), the 4-bit bank address (address bus A16 to A19) becomes "0",
indicating that the access range is from OOOOOH to OFFFFH.
(Note)
3.1.4
Given "FFECH" to the IX value of (BX address) an instruction "LD
(IX), x", the normal write cycle is not performed, making the
result indefinite.
Instructions
The TMP90C840 supports a rich variety of addressing modes as well as
powerful instruction sets.
There are 163 basic instructions as
categorized into the following nine groups:
o
o
o
o
o
o
o
o
o
8-bit transfer instruciton
16-bit transfer instruciton
Exchange, block transfer and search instructions
8-bit arithmetic and logical operation instruction
Special operation and CPU control instructions
16-bit arithmetic and logical operation instruciton
Rotate and shift instructions
Bit manipulation instruction
Jump, call and return instruction
Table 3.1 (1) lists the 163 basic instructions.
describes the mnemonics and their meaning.
(1)
Table
3.1.
(2)
8-bit transfer instruction
The 8-bit transfer instructions inclued those for transferring 8-bit
data between registers, register and immediate address, register and
memory, or memory and immediate address.
MPU90-17
TOSHIBA
TMP90C840
(2)
I6-bit transfer instruction
The I6-bit transfer instructions include those for transferring I6-bit
data between registers, register and immediate address, register and
memory, and memory and immediate address, PUSH and POP instructions
using the stack, and LDA (Load Address) instruction that calculates an
effective address and loads its value into a register.
(3)
Exchange, block transfer and search instructions
The data exchange instructions are executed to exchange 16-bit data
between registers, between memory and register, or between a main
register and an alternative register.
The block transfer instructions can transfer data in any memory block
to other memory area.
The block search instructions are executed to find out a particular
8-bit character in a given memory block.
LDIR, LDDR, CPIR and CPDR
included in the block transfer and search instructions read the
current instruction each time a I-byte memory is transferred or
compared, thus making it possible to acknowledge an interrupt before
reaching to the end of the block.
(4)
8-bit arithmetic and logical operation instruction
8-bit arithmetic and logical operation instructions perform 8-bit
arithmetic and logical operations between Register A and another
register, Register A and immediate address, Register A and memory,
register and immediate address, and memory and immediate address (ADD,
ADC, SUB, SBC, AND, OR XOR and CP), or increment/decrement the
contents of register or memory by 1 (INC, DEC, INCX and DECX).
The INCX (Increment if X) inst ruction increments the contents of a
memory specified by the operand if the X flag is "1", and does nothing
if not. The DECX instruction performs the same operation except that
it decrements the data. These instructions are executed to increment
or decrement the data with 20-bit width in the 20-bit address pointers
(registers BX and IX or BY and IY) mainly to access an extended data
area.
Examples:
INC IX
INCX (FFECH)
LD A, (IX)
Increment Register IX
Increment Register BX if X
Load contents of memory into Register A
MPU90-18
TOSHIBA
TMP90C840
Table 3.1 (1)
10
LD
10
10
LO
10
10
LO
10
LOW
PUSH
POP
LOA
EX
EX
EXX
r,r
r,n
r,mem
mem,r
mem,n
rr,rr.
rr,nn
rr,mem
mem,rr
mem,nn
qq
qq
rr,mem
DE,HL
AF,AF'
EX
mem,rr
101
10IR
100
LDDR
CPI
CPIR
CPD
CPDR
ADO
ADD
ADD
ADO
ADC
ADC
ADC
ADC
SUB
SUB
SUB
SUB
SBC
SBC
SBC
A,r
A,mem
r,n
mem,n
A,r
A,mem
r,n
mem,n
A,r
A,mem
r,n
mem,n
A,r
A,n
A,mem
TMP90C840 Basic Instructions (163 types)
SBC
SBC
AND
AND
ANO
AND
AND
OR
OR
OR
OR
OR
XOR
XOR
XOR
XOR
XOR
CP
CP
CP
CP
CP
INC
INC
DEC
DEC
INCX
OECX
OAA
CPL
NEG
LDAR
CCF
SCF
RCF
NOP
HALT
DI
EI
SWI
r,n
mem,n
A,r
A,n
A,mem
r,n
mem,n
A,r
A,n
A,mem
r,n
mem,n
A,r
A,n
A,mem
r,n
mem,n
A,r
A,n
A,mem
r,n
mem,n
r
mem
r
mem
(n)
(n)
A
A
A
HL,PC+dd
MUL
MUL
MU1
DIV
DIV
DIV
ADD
ADD
ADD
ADC
ADC
ADC
SUB
SUB
SUB
SBC
SBC
SBC
AND
AND
AND
OR
OR
OR
XOR
XOR
XOR
CP
CP
CP
ADD
ADD
ADD
INC
INCW
DEC
DECW
RLCA
RLC
RLC
MPU90-19
HL,r
HL,n
HL,mem
H1,r
HL,n
H1,mem
H1,rr
HL,nn
H1,mem
HL,rr
H1,nn
HL,mem
H1,rr
H1,nn
H1,mem
H1,rr
HL,nn
HL,mem
HL,rr
HL,nn
HL,mem
H1,rr
HL,nn
H1,mem
HL,rr
HL,nn
HL,mem
HL,rr
HL,nn
HL,mem
ix,rr
ix,nn
ix,mem
rr
mem
rr
mem
r
mem
RRCA
RRC r
RRC mem
RLA
r
RL
mem
RL
RRA
r
RR
RR
mem
SLAA
SLA r
SLA mem
SRAA
SRA r
SRA mem
SLLA
S11 r
SLL mem
SRLA
SRL r
SRL mem
R1D mem
RRD mem
BIT b,r
BIT b,mem
RES b,r
RES b,mem
SET/TSET b,r
SET/TSET b,mem
cC,mem
JP
JR
cc,PC+d
JRL PC+dd
CALL cC,mem
CALR PC+dd
OJNZ [BC, ]PC+d
RET cc
RETI
TOSHIBA
TMP90C840
Table 3.1 (2)
Mnemonic
LD
LDW
PUSH
POP
LDA
EX
I
I
I
I
I
I
EXX
I
Meaning
I
I
I
I
I
I
I
CPD
I
CPDR I
I
ADD
I
ADC
I
SUB
I
SBC
I
AND
I
OR
I
XOR
I
CP
I
INC
I
DEC
I
INCX I
DECX I
DAA
I
CPL
I
NEG
I
LDAR I
CCF
I
SCF
I
RCF
I
NOP
I
HALT I
DI
I
EI
I
SWI
I
LDI
LDIR
LDD
LDDR
CPI
CPIR
TMP90C840 Mnemonics and Their Meaning
Load
Load Word
Push
Pop
Load Addres s
Exchange
Exchange X
Load and Increment
Load, Increment and Repeat
Load and Decrement
Load, Decrement and Repeat
Compare and Increment
Compare, Increment and
Repeat
Compare and Decrement
Compare, Decrement and
Repeat
Add
Add with Carry
Subtract
Subtract with Carry
And
Or
Exclusive Or
Compare
Increment
Decrement
'Increment if X
Decrement if X
Decimal Adjust Accumulator
Complement
Negate
Load Address Relative
Complement Carry Flag
Set Carry Flag
Reset Carry Flag
No Operation
Halt
Disable Interrupt
Enable Interrupt
Software Interrupt
Mne- I
Meaning
monic I
MUL
Multiply
DIV
Divide
INCW
Increment Word
DECW
Decrement Word
RLCA
Rotate Left Circular
Accumulator
Rotate Left Circular
RLC
RRCA
Rotate Right Circular
Ac cumulator
Rotate Right Circular
RRC
Rotate Left Accumulator
RLA
Rotate Left
RL
Rotate Right Accumulator
RRA
Rotate Right
RR
Shift Left Arithmetic
SLAA
Accumulator
Shift Left Arithmetic
SLA
Shift Right Arithmetic
SRAA
Accumulator
Shift Right Arithmetic
SRA
Shift left Logical
SLLA
Accumulator
Shift Left Logical
SLL
Shift Right Logical
SRLA
Accumulator
SRL
Shift Right Logical
Rotate Left Digit
RLD
RRD
Rotate Right Digit
BIT
Bit Test
RES
Reset Bit
SET
Set Bit
TSET
Test and Set
JP
Jump
Jump Relative
JR
Jump Relative Long
JRL
CALL
Call
CALR
Call Relat ive
DJNZ
Decrement and Jump if Non
Zero
Return
RET
RETI
Return from Interrupt
MPU90-20
TOSHIBA
TMP90C840
(5)
Special operation and CPU control instruction
Special operations are used to control Register A (DAA, CPL and NEG),
load the data in a relative address into a register (LDAR), control
the carry flag (CCF, SCF and RCF) , mUltiply an 8-bit data by an 8-bit
data and convert the result into a 16-bit representation (MUL) , divide
a 16-bit data by an 8-bit divisor and obtain an 8-bit quotient with an
8-bit residual (DIV), and to nothing (NOP).
If a quotient cannot be represented by an 8-bit number (outside the
0-255. range) or if the divisor is a (e. g. , "divide 1, 000 by 0" or
"divide 5,000 by 0"), the overflow flag is set to "1".
CPU control instructions are executed to suspend the CPU operation
(HALT), enable/disable a maskable interrupt (El/DI), and to execute a
software interrupt (SWI).
(6)
16-bit arithmetic and logical operation instruction
The 16-bit arithmetic and logical operation instructions perform
16-bit arithmetic logical operations between the register pair HL and
another register pair, the register pair HL and immediate address, and
the register pair HL and memory (ADD, ADC, SUB, SBC, AND, OR, XOR and
CP), perform an addition between the index registers IX and IY or
Stack Pointer SP and a register pair, or immediate address and memory
(ADD), or increment/decrement the contents of a register pair or
memory by 1 (INC, INCW, DEC, and DECW).
Note that "ADD HL,rr", "ADD ix,gg", "INC rr" and "DEC rr" result in a
different flag status.
(7)
Rotate and shift instructions
The rotate and shift instructions use 8-bit data (RLC, RRC, RL, RR·,
SLA, 8RA, SLL and SRL) or binary-coded decimal (BCD) data (RLD and
RRD).
(8)
Bit manipulation instruction
The bit manipulation instructions perform testing,
setting and
resetting a particular bit in a register or memory (BIT, SET and RES).
A test and reset instruction (TSET) is als 0 avai lab Ie for execut ing
multiple tasks.
(9)
Jump, call and return instructions
A jump instruction can be used, in addition to the register indirect,
index, register index, and extended addressing modes, in the 8-bit and
16-bit relat ive addressing modes.
Note, however, that the 16-bit
relative addressing mode can be used only for an unconditional jump
instruction.
A call instruction uses the 16-bit relative addressing mode, as well
as the register indirect,
index,
register index,
and
extended
addressing modes.
Again, 16-bit relative addressing mode is only
applicable to an unconditional call instruction.
Return
instructions
contain
unconditional
return
instruction,
conditional return instruction and RETI instruction for return back
from the interrupt processing.
These instructions pop up the program counter PC and the register pair
AF from the stack.
16 condition codes and over 16 mnemonics are used
in these instructions, because certain flags have more than one
meaning (e.g. Z and EQ, NZ and NE, PE and OV, PO and NOV).
MPU90-21
TOSHIBA
TMP90C840
In addition to the above instructions, "DJNZ PC+d" and "DJNZ BC,PC+d"
may be used to control program loops.
"DJNZ PC+d" decrements the contents of the Register B (8-bit) each
time the instruction is executed, and executes a relative jump until
it becomes zero.
"DJNZ BC, PC+d" decrement s the contents of the
regis ter pair BC (16- bit), and executes a relat ive jump unt i 1 it
becomes zero.
Appendix A lists the TMP90C840 machine instructions.
The table
includes the instruction groups, mnemonics, codes, functions, flag
status and executing time.
The execut ing time can be ca lculated us ing the value in the "T"
column, which denotes the number of states.
Time for one state is
eq uiva lent to a time twice as long as the clock osci llat ion cycl e.
For example, if the clock oscillation frequency is 10MHz, the time for
one state is 200 ns.
Execut ing "LD A, r" at the clock frequency of lOMHz requires two
states, and thus takes 200ns x 2 = 400ns for the execution.
Appendix B contains code maps.
The TMP90C840 supports I-byte opcode
instructions and 2-byte opcode instructions.
The I-byte opcode
instruction is formatted as follows:
LD
A,B
Opcode
LD
A,n
Opcode
n
LD
HL,mn
Opcode
n
m
LD
(w) ,n
Opcode
w
n
LDW
(w),mn
Opcode
w
n
JR
PC+d
Opcode
d
CALL
ran
Opcode
n
MPU90-22
m
m
TOSHIBA
TMP90C840
As shown in the code format, a I-byte opcode instruction has an opcode
in the first byte and operand codes in the subsequent bytes. If there
are two I-byte operand codes, the lower operand is placed before the
upper operand.
If both a source and a destination are included as
operand codes, the destination is placed first.
A 2-byte opcode instruction begins with the first opcode, followed by
an operand code specified by the first opcode, then the second opcode
and its operand code. For example,
LO
B,C
I 1st °E Code I 2nd °E Code I
LO
B, (n)
11 st
°E
Codel
n
12nd
°E
Code!
LO
B,(IX+d) lIst
°E
Codel
d
12nd
°E
Code I
LO
B, (mn)
11 st
°E
Code!
n
ADO B,n
lIst
°E
Code 12nd
ADD (VW) ,n
11 st 0p Codel
°E
m
Code!
w
12nd
°E
Codel
n
v
12nd 0p Codel
n
In a 2-byte opcode instruction, the pos1t1on of the second opcode is
determined by the first opcode.
Basically, the first opcode in a
2-byte opcode instruction provides data to select the mode of
addressing the operand in the range of EOH to FER. The first operand
code that follows the first opcode serves to specify the memory
addressing mode.
The second operand code that follows the second
opcode specifies the immediate addressing mode.
Their roles can be
summarized as follows:
I
I
1st opcode 11 st operand codel 2nd opcode
I
I 1<
I addressing I
mode
I
2nd operand codel
I
>1 < Spec1. f y
>1< Specify imSpecify
memory
I instruction I mediate adaddressing
dress ing
MPU90-23
I
>1
I
TOSHIBA
3.2
TMP90C840
Basic Timing
Each instruction of the TMP90C840 is executed by combination of read,
write and dummy cycles.
These are basic cycles that synchronize with
the system clock. 1/2 of the frequency of the clock oscillation is used
as the sys tem clock; e. g., if the clock freq uency is 10 MHz, the
frequency of the system clock is 5 MHz. The system clock cycle is also
called a "state".
The TME90C840 bus operation are basically synchronous, and each of
memory read, memory write and dummy cycles is completed in two states,
unless they are not requested to wait.
The "CLK" pin generates a pulse at a frequency that further halves the
frequency of the system clock.
This CLK signal synchronizes with the
bus cycles with no wait request.
3.2.1
Read/Write cycles
Fig. 3.2.(1) is a t~m~ng chart of external memory read/write cycles.
The left side shows the bus operation timing with no wait request, and
on the right side shows that with a 2-state wait request.
Each wait consists of a mUltiple of two states, making a bus cycle
wait for two, four, six, eight states, etc •..•
State
E
~
Xl
CLK
A¢ - 19
Read
Cycle
RD
[ D¢ - 7_
WAIT
Fig. 3.2.(1)
Timing of External Memory Read/Write Cycles
MPU90-24
TOSHIBA
TMP90C840
The TMP90C840 CPU has a wait control register (WAITC) that controls
waits by using software. The configuration of this register is shown
in Fig. 3.2 (2).
7
P3CR
(FFC7H)
6
WAITC
5
4
RDE
ODE
3
2
1
TXDC
0
RXDC
I
I
0
0
0
1
1
0
1
1
2-state wait
Normal wait
No wait
Reserved
Fig. 3.2 (2)
I
See "3.5.4 Port 3".
Wait Control Register
This register is assigned to the bits 6 and 7 of the memory address
FFC7H in the internal I/O register area (the other bits are used for
controlling other functions).
It is reset. to "00", whereby the
register is placed in the 2-state wait mode.
In the "2-state wait mode", only the first wait in a bus cycle is
sampled, and all subsequent waits are ignored.
In the "normal wait mode", all wait requests are sampled.
The "no
wait mode" ignores all waits.
3.2.2
Dummy cycles
The timing of dummy cycles is shown in Fig. 3.2 (3). All through the
dummy cycles, the level of both the RD andWR signals remains at "1"
and wait requests are ignored, with the address bus being undefined.
A dummy cycle is also called an "internal operating cycle".
The bus
cycle becomes the dummy cycle when the CPU reads or write the data
from/to the internal memory or internal I/O area.
Xl
eLK
At/; - 19 ~'--~_"""_-+-_-I\_
RD
WR
D¢ - 7
WAIT
Fig. 3.2 (3)
Timing of Dummy Cycles
MPU90-25
TOSHIBA
TMP90C840
3.2.3
Interrupt Acknowledge Timing
Fig. 3.2 (4) shows the basic tlmlng of interrupts being acknowledged.
An interrupt request may be sampled by the CPU at the falling edge of
the CLK signal in the last bus cycle of each instruction.
Note,
however, that the sampling of a non-maskable interrupt (NMI) is
delayed a half the system clock cycle.
When an interrupt request is acknowledged, the CPU starts an interrupt
response sequence that proceeds as follows: 1) A read cycle (In this
cycle·, the read data is not used in the CPU because the pipel ine
processing prefetches instructions.
The pipeline processing is
described in "3.2.6 Bus Operation for Executing Instructions".), 2)
two dummy cycles (the CPU receives an interrupt vector from an
internal interrupt controller), 3) out put 0 f the interrupt vec tor
(OOOH for the upper address locations A8 to A19) and read out of the
dummy cycle, 4) one dummy cycle, 5) saving the contents of the program
counter PC and those of the register pair AF into the stack (four
write cycles), and 6) the CPU resets the interrupt enable flag IFF to
"0" (to disable interrupts) and jumps to the interrupt processing
routine.
If a "micro DMA processing" is specified as the interrupt, the CPU
follows the sequence to be described in "3.3.2 Micro Dt'1A processing".
Xl
-, Jl JlJl
A¢ - 19
~
I
CLK
-K
-
L.nIJlJlJl Jlir-1' Jlir-1' Jl'J
I
X
Last
RD
\
I
WR
\
J
I
\
~
Next + 1
\
\
Dummy
J
- --- ---- --- ~ .. -- ---- --- --- --
D¢ - 7
~
NMI
INT¢
(Level)
/ i\
INT¢·1·2
(Rising Edge)
Internal INT
C
I
Last Instructlon
Execution Cycle
Fig. 3.2 (4)
Interrupt Acknowledge
Sequence
Interrupt Acknoledge Timing
MPU90-26
TOSHIBA
3.2.4
TMP90C840
Reset
The basic timing of the reset operation is indicated in Fig. 3.2 (5).
In order to reset the TMP90C840, the RESET input must be maintained at
the "0" level for at least ten system clock cycles 00 states). When
a reset req uest is accepted, all I/O ports (Port 0/ da ta bu.s DO to 07,
Port l/address bus AO to A7, Port 2/address bus A8 to A15, Port 6 and
Port
function as input ports (high impedance state).
The RD, WR
and CLK pins that always function as output ports turn to the "1"
level, and the other input ports (P32, P33, Port 4/address bus A16 to
A19 and P83) turn to the "0" level. The dedicated input ports remain
unchanged.
The registers and external memory of the CPU also remain
unchanged.
Note, however, that the program counter PC, the interrupt
enable flag IFF and the bank registers BX and BY are cleared to "0".
Register A shows an undefined status.
When the reset is cleared, the CPU starts executing instructions from
the address OOOOH.
n
Xl
"'" Jl ...Jl Jl Jl Jl ...Jl ...Jl
I
eLK
A16 - 19
I
\
\
RESET
A¢ - 15
-~
{undefined I}---
-K
~Undef ined \
-
RD
~
/
WR
~
j
D¢ - 7
~
) - - - ~--
-
---
Fig. 3.2 (5)
Reset Timing
MPU90-27
TOSHIBA
3.2.5
TMP90C840
System flowchart
Fig. 3.2 (6) is a system flowchart of the TMP90C840.
A normal
operation repeats a loop between "Fetch instruction" and "Execute
instruction".
When an interrupt is acknowledged) the CPU proceeds to "Interrupt
processing".
Executing the return instruction RETI makes the CPU
return to the address that follows the address of the SWI instruction
in the same way as the SWI instruction is executed under software
control.
When a HALT instruction is executed, the CPU suspends the operation
until an interrupt is requested.
When the interrupt is acknowledged,
the CPU starts the interrupt processing.
However, when a maskab Ie
interrupt is requested with the interrupt enable flag at "0"
(interrupts are disabled), the CPU only releases the HALT state and
starts executing an instruction that follows the HALT instruction.
For det ails of the interrupt proces sing, refer to "3.3 Int errupt
Function".
The timing of releasing the HALT state is described in
"3.4 Standby Function".
By setting the RESET input level to "0", the CPU always returns to
"RESET" start position without regard to its current position in the
flowchart.
MPU90-28
TMP90C840
TOSHIBA
YES
PC +- OOOOH
IFF +- 0
BX,BY +- 0
I/O Initialize
PC +- PC-l
YES
Instruction
Fig. 3.2 (6)
Interrupt
TMP90C840 System Flowchart
MPU90-29
TOSHIBA
3.2.6
TMP90C840
Bus operation for executing instructions
The TMP90C840 adopts a pipeline processing method in which it executes
an instruction simultaneous with the next instruction fetch.
The
concept of this processing is illustrated in Fig. 3.2 (7).
Address
100
102
101
Fetch instruc- I Execute intion in address I struction in
100
I address 100
Fetch instruc- I Execute intion in addressl strcution in
101
I address 101
Fetch instruc- I
tion in address I
102
I
Fig. 3.2 (7)
Pipeline Processing
This pipeline processing allows the TMP90C840 to obtain a higher
executing speed than the conventional method that fetches the next
instruction after the previous instruction is executed.
The bus
operation for each instruction begins with "fetching a code in the
address that follows the first instruction code", and not with
"fetching the first instruction code". The first instruction code is
fetched when the CPU is execut ing the previous instruction.
An
example of this processing is shown in Fig. 3.2 (8).
Address I
INC A
CPU
I LD B,A
Execute
INC A
I ADD A,n
DEC H
Execute I Execute I Execute
LD B,A I internal I ADD A,n
I operation I
,
I
,
I ''<
Bus
Bus
operation operation
Fig. 3.2 (8)
n
Pipeline Processing
MPU90-30
ADD A,n
Bus operation
Execute
DEC H
>'<
,
and Bus Operation
>'
DEC H ,
Bus
operation
TOSHIBA
TMP90C840
Table 3.2 is a list of the bus operations for each instruction. Their
cycles (read, write or dummy) are indicated by symbols in the table.
Each bus cycle is represented by a single symbol (a character string
with one to three characters length) and delimited by a colon ":".
The bus operations should be read from the left to right.
A capital letter denotes an effective bus cycle, and a small letter (n
or d) denotes an invalid bus cycle. For example, data read out in the
read cycle of the "n" bus operation have no effect on the CPU
operation, and are ignored.
The symbol "d" represents an internal
operation cycle that involves no read or write of memory.
Table 3.2
Bus Operations for Executing Instructions
Meaning of symbols
Symbol
N
n
1
2
3
4
5
6
d
R
R+l
W
W+l
Data Bus
Next Code Read
Next Code Read (dummy)
1 st Code Read
2nd Code Read
3rd Code Read
4th Code Read
5th Code Read
6th Code Read
Dummy (No Read/Wri te)
1st Data Read
2nd Data Read
1 st Data Write
2nd Data Write
MPU90-31
Address Bus
Next Op Code Address
Next Op Code Address
Jump/Call/Return Address
Op Code Address+1
Op Code Address+2
Op Code Address+3
Op Code Address+4
Op Code Address+5
Undefined
1 st Data Address
2nd Data Address
1 st Data Address
2nd Data Address
TOSHIBA
TMP90C840
1. 8-BIT LOADS
I Mnemonic
: LD
A, r
I
I
Bus Operation
IN
I
r, A
N
I
r, g
2: N
i
I
................~.'..~ .................. ~.:.~ ............................... ,
I
A, (n)
r, (gg)
r,(ix+d)
r, (HL+A)
r, (mn)
r, (n)
2: d: R: N
2:R:N
2:d:3:R:N
2:d:d:d:d:R:N
2:3:4:R:N
2:3:R:N
I":~~;~;T ~::::':w'l
I
'
\
Ux+d), r
(HL+A)' r
(mn), r
12:d:3:N:W
I
12~d~d~d~d:N:W
.
I
1
I
(HL+A),mn 12:~:~~~:d:3:4:N:
,
PUSH
(vw),mn
(w),mn
QQ
POP
QQ
LOA
rr, ix+d
rr,HL+A
I
II
I
(Ix+d),n. 2:d:3:4:W:N
I
I
I
(HL+A).n 12:d:d:d:d:3:W:N ,
(vw), n
I 2: 3: 4: 5: W: N.
.
(w),n
2:d:3:W:N
I
I
I
Bus Operat ion
N:d
N:d
2: N: d
1
rr,(gg)
rr,(ix+d)
rr,(HL+A)
rr, (mn)
rr, (n)
I
'···· . ~~~i~~:····n-:·~·:::·~:~·~·i·····
(ix+d),rr '2:d:3:N:W:W+1
I
II
(H L+A) , r r I 2: d : d : d : d : N: W: W+ 11
!
(mn), rr
.
(n), r r
I
1
(gg),rr
(ix+d),rr
2:R:R+1:N
I
2:d:3:R:R+1:N
I
2:d:d:d:d:R:R+1:N!
12: 3: 4: R: R+ 1: N
2:3:R:R+l:N
I
. ~~~. . . . . . . . . . . . . . . .L~. . . . . . . . . . . . . . . . . . I
(HL+A)' rr
I
rr,gg
I
1··············~t·{~f······.l}n·:·R~·i":·ii············1
I
I
2:3:4:5:6:N:W:W+1
2:d:3:4:N:W:W+l
I N:d: (SP-1)~QQH:
(SP-2) ~QQL
n: QQL ~ (SP) :
QQHt- (SP+1):
d:N
12:d:3:N:d
12:d:d:d:d:N:d
3. EXCHANGES,
BLOCK TRANSFERS AND SEARCHES
Mnemonic
I Bus Operation
EX
DE. HL
N
I EX
AF,AF'
N
EX
2. 16-BlT LOADS
I Mnemonic
LD
HL,rr
1
rr,HL
I
12.3.4.N.W
1·······+~H·n········T~·+~·}····················
I
16-BIT LOADS(Continued)
I
Mnemonic
I Bus Operat ion \
i LDW
(gg),mn
12:3:4:N:W:WT1
\
(ix+d),mn 12:d:3:4:5:N:W:W+11
(mn), rr
(n),rr
LDI/LDD
LDIR/LDDR repeat
end
CPT/CPO
I CPIR/CPDR repeat
I
end
2:3:4:N:W:W+l
2 : 3: N: W: W+ 1
MPU90-32
2:R:R+1:
d: W: W+1: N
I
2:d:3:R:R+1:
I
d:W:W+1:N
2:d:d:d:d:R:R+1: I
d:W:W+1:N
2:3:4:R:R+1:
d:W:W+1:N
2:3:R:R+1:
d:W:W+1:N
2:n:R:W:d:d:N
2:n:R:W:d:d:d:d:1
2:n:R:W:d:d:N
2:n:R:d:d:d:N
12:n:R:d:d:d:d;d:1
2:n:R:d:d:d:N
I
TOSHIBA
TMP90C840
4. 8-BIT ARITHHETIC
5. SPECIAL FUNCTIONS
I
AND LOGIC OPERATIONS
Hnemonic
ADO/ ADC/SUB/SBC/ I
AN D/OR/XOR
1
A, g
A, n
A, (gg)
A, (ix+d)
A, (HL+A)
I
2: N
12: N
12:R:N
i 2:d:3:R:N
!2:d:d:d:d:R:N
I
NOP
I
II
I
I CP
A,
n
1
I
I
I
12:d:d:d:d:3:R:N:~
12:3:R:N:W
2:d:3:4:R:N:W
I
II
I
Nexi DEcx.
r
N
(gg)
(ix+d)
(Hl+A)
(mn)
2:R:N:W
2:d:3:R:N:W
2:d:d:d:d:R:N:W
2:3:4:R:N:W
i SW I
In: d : d : 1: d :
I
I
I (SP-2) -PCl:
I (SP-3) .-A:
I :SP-4J<-F:
I
!
I
HU L/ DI V HL. g
HL,n
HL. (gg)
I
HL,
2:d:R:N:W
HL.
Hl,
HL.
:
i i;!~~~ ~':'~':::'N:W'.......·········1
(n)
I
DIIEl
I
!1·······································1'·············
.......................... :
A,(gg)
A, (ix+d)
A, (Hl+A)
A, (mn)
A, (n)
.
·································· .. ···1· .... ···.. ·· .. ·····..................... j
g, n
12:3:N
(gg),n
2:3:R:N
(ix+d),n
2:d:3:4:R:N
(HL+A),n
2:d:d:d:d:3:R:N
(vw),n
2:3:4:5:R:N
2:3:4:R:N
(w),n
INC/DEC
Bus Operation
N:d
N
2:3:N:d
N
(SP-1) .-PCH:
2: 3: N
2: 3: 4: 5 : R: N: W
! 2:3:4:R:N:W
2: N
I 2:N
12:R:N
!2:d:3:R:N
12:d:d:d:d:R:N
! 2:3:4:R:N
I
12:d:R:N
I
N
N:d
iN
HALT
1······::·~~~J···u.:~:·:·:~:~····
g,n
(gg),n
(ix+d),n
(HL+A).n
( vw), n
(w), n
A, g
Hnemonic
DAA
A
CPL/NEG A
LDAR
HL,PC+cd
CCF/SCF/RCF
Bus Operation
MPU90-33
I
i 2: n: d: d: d: d: d: d: N'
2:d:d:d:d:d:d:N
2:R:d:d:d:
d:d:d:N
(ix+d), 2:d:3:R:d:d:d:
d: d: d:N
(HL+A),. 2:d:d:d:d:R:d:d:
d:d:d:d:N
(mn) ,I 2: 3: 4: R: d : d : d:
d:d:d:N
I
(n)
2:3:R:d:d:d:
I
I
d:d:d:N
OSHrBA
TMP90C840
6. 16-BIT ARITHHETIC
AND LOGIC OPERATIONS
I
Hnemonic
I Bus Operation
ADD/ADC/SUB/S~CI
AND/OR/XOR/CP
HL,gg
HL,mn
HL.(gg)
HL, (ix+d)
HL. (HL+A)
HL. (mn)
HL, (n)
ADD
iX,gg
iX,mn
ix, (gg)
ix, (jx+d)
ix, (H L+A)
ix, (mn)
iX,(n)
IINC/DEC
rr
2:N:d:d
2:3:N
2:R:R+1:N
12:d:3:R:R+1:N
I
2:d:d:d:d:R:R+1:NI
12:3:4:R:R+1:N
2:d:R:R+1:N
2:N:d:d
2:3:N
2:R:R+1:N
12:d:3:R:R+1:N
I
2: d: d: d: d: R: R+ 1: N
'
2:3:4:R:R+1:N
2:3:R:R+1:N
·N:d
'··IHc·w/D"E"C"w···fiiQ)······ ··2·~·R·:··R·~·i··:·····················1
1,
I
N: W: W+1
.
(ix+d) 2:d:3:R:R+1:
N:W:W+1
(HL+A) 2:d:d:d:d:R:R+1:
N:W:W+1
(mn)
2:3:4:R:R+1:
N:W:W+1
(n)
I 2: d: R: R+ 1:
IN: W: W+1
7. ROTATES AND SHIFTS
Hnemonic
Bus Ope rat ion
RLC/RRC/RlIRRI
SLA/SRA/SLL/SRL
A
N
2:N
9
(gg)
2:R:N:W
I
(ix+d) 2:d:3:R:N:W
I
(HL+A) 12:d:d:d:d:R:N:W
(mn)
2:3:4:R:N:W
(n)
2:3:R:N:W
(gg)
RLD/RRD
2:R:d:d:N:W
(i x+d) 2:d:3:R:d:d:N:W
(HL+A) 2:d:d:d:d:
R:d:d:N:W
I
(mn)
12:3:4:R:d:d:N:W
12:3:R:d:d:N:W
(n)
8. BIT OPERATIONS
Mnemonic
Bus Operation
I BIT
b,g
2:N
I
b, (gg)
2:R:N·
b, (ix+d) 2:d:3:R:N
b, (HL+A) 2:d:d:d:d:R:N
b, (mn)
\2:3:4:R:N
b, (n)
,2:d:R:N
SET/RES b,g
2:N
I
b, (gg)
2:R:N:d:W
I
b, (·i x+d) 2: d: 3: R: N: d: W
;
b, (HL+A) 2:d:d:d:d:
R:N:d:W
.
b, (mn)
12:3:4:R:N:d:W
b, (n)
12:d:R:N:d:W
b,g
2:N:d:d
i TSET
i
b, (gg) j 2:R:N:d:d:W
i
b, (ix+d) ,2:d:3:R:N:d:d:W
i
b, (HL+A) . 2:d:d:d:d:
I
R:N:d:d:W
I
b, (mn)
2:3:4:R:N:d:d:W
b, (n)
2:3:R:N:d:d:W
I
I
MPU90-34
TOSHIBA
TMP90C840
JUMPS, CALLS AND
Mnemonic
JP cC,gg true
false
ce. i x+d true
false
ec.HL+A true
false
ee,mn true
RETURNS
Bus Operation
2:n:d:1
2:N:d
2:d:3:n:d:1
2:d:3:N:d
2:d:d:d:d:n:d:l
2:d:d:d:d:N:d
2:3:4:n:d:l
2:3:4:N:d
-----------------------------!.~-!-~-~ .........................................
JR ee, PC+d true 2:n:d:l
2:N
---......... -...... -.--...... !.~-!.~.~ ............................................
JP mn
2:3:d:l
JRL PC+ed
2:3:d:d:l
CALL ee,gg truE 2:n:d:d:
(SP-l) +-PCH:
(SP-2) +-PCl:
1
false 2:N:d
ee ix+d truE 2:d:3:n:d:d:
(SP-1) +-PCH:
(S P-2) +- PC l :
1
fa ISE 2:d:3:N:d
ee,Hl+A true 2:d:d:d:d:n:d:d:
(SP-1) +-PCH:
(SP-2) +-PCl:
1
false 2:d:d:d:d:N:d
ce,mn true 2:3:4:n:d:d:
(SP-1)+-PCH:
(SP-2) +- PCl:
1
2:3:4:N:d
... --.......... --.-... --.... -!.~-!-~-~ .......................................
CALL mn
2:3:d:d:
(SP-1) (- PCH
(S?-2) - PCl
1
CAlR PCTed
2:3:d:d:d:
(~P-1) +- PCH
(SP-2) +- PCl
1
9.
t
Hnemonic
I Bus Operation
DJNI PC+d
tru~ 2:d:d:d:1
falstJ 2:d:d:d:N
BC, PC+d t ru ~ 2: d: d: d: 1
fals~ 2:d:d:d:N
RET
I n:
PCl+-(SP):
PCH +- (SP+ 1) :
d:1
RET ec
t ru~ 2: n: d:
PCl- (SP) :
PCH+- (SP+1):
I d: 1
false:
2:N:d
......................................... .........................................
n:
RET!
F+-(SP):
A+-(SP+1) :
PCl+- (SP+2):
PCH +- (SP+3) :
d: 1
I
I
I
MPU90-35
TOSHIBA
TMP90C840
10. INTERRUPT
HODE
I
Bus Operat ion
NORHAL INTERRUPT n+1:d:d:1:d:
(SP-1) +-PCH:
(S P- 2) +- PC l :
(SP-3) +-A:
(SP-4)+-F:
1
HICRO DHA
n+ 1: d: d: d:
DSTl+-(FFOOH+V+1):
DSTH+- (FFOOH+V+2):
SRCl +- (FFOOH+V+3) :
SRCH+-(FFOOH+V+4) :
CHD +-(FFOOH+V+5):
TEHP+- (SRC):
(OS1) +- TEHP:
TEHP+-(SRC+1) / d:
(OST+1) +-TEHP / d:
d:
d:
(FFOOH+V+4) +-SRCH':
(FFOOH+V+3) +-SRCl':
(FFOOH+V+2) +-OSTH':
(FFOOH+V+1) +-OSTL':
COUNT +- (FFOOH+V) :
d:
(FFOOH+V) +-COUNr:
N
.......................................................................................
if COUNT'=O
t hen execute
d:d:d:
(SP-1) +- PCH:
(SP-2)+-PCl:
(SP-3) +-A:
(SP-4)+-F:
1
MPU90-36
TOSHIBA
3.3
TMP90C840
Interrupt Functions
The TMP90C840 supports a general purpose interrupt processing mode to
acknowledge internal and external interrupt requests, as well as a micro
DMA processing mode that enables automatic data transfer by the cpu.
Immediately after the reset state is released, all interrupt requests
are processed in the general purpose interrupt processing mode.
However, they can be processed in the micro DMA processing mode by using
a DMA eoable register to be described later.
Fig. 3.3 (1) is a flowchart of the interrupt response sequence.
Interrupt Processing
Reading of Interrupt Vector 'V'
YES
General-Purpose
Interrupt Processing
Fig. 3.3 (1)
Micro-DMA
Processing
Interrupt Response Flowchart
When an interrupt is requested, the source of the interrupt transmits
the request to the CPU via an internal interrupt controller.
The CPU
starts processing the interrupt if it is a non-maskable or maskable
interrupt requested in the EI state.
However, a maskable interrupt
requested in the DI state is ignored and acknowledged.
Having acknowledged an interrupt, the CPU reads out the interrupt vector
from the internal interrupt controller to find out the interrupt source.
Then, the CPU checks if the interrupt requests the general purpose
interrupt processing or the micro DMA processing, and proceeds to each
processing ••
As the reading of an interrupt vecotors is performed in the internal
operating cycles, the bus cycle at that time results in dummy cycles.
3.3~1
Normal interrupt processing
A normal interrupt is processed as shown in Fig. 3.3. (2).
The CPU stores the contents of the program counter PC and the register
pair AF into the stack, and resets the interrupt enable flag IFF to
"0" (disable interrupts).
It then transfers the value of the
interrupt vector "v" to the program counter, and the processing jumps
to an interrupt processing program.
MPU90-37
TOSHIBA
TMP90C840
The overhead for the entire process from accepting an
jumping to an interrupt processing program is 20 states.
interrupt
to
General-Purpose
Interrupt Processing
(SP-l) + PCH
(SP-2) + peL
(SP-3) + A
(SP-4) + F
SP + SP-4
IFF + 0
Fig. 3.3 (2)
General Purpose Interrupt Processing Flowchart
An interrupt processing program ends with a RETI instruction.
When this instruction is executed, the data previously stacked from
the program counter PC and the register pair AF are restored.
After the CPU reads out the interrupt vector, the source of an
interrupt requested acknowledges that the CPU accepts the request, and
clears the request.
A non-maskable interrupt cannot be disabled by programming.
A
maskable interrupt, on the other hand, can be enabled or disabled by
programming. An interrupt enable flip flop (IFF) is provided on the
bit 5 of Register F in the cpu. The interrupt is enabled or dis,abled
by setting IFF to "1" by the EI instruction or to t'o" by the DI
instruction, respectively. IFF is reset to "0" by the reset operation
or the acceptance of any interrupt (including non-maskable interrupt).
The EI instruction is executed after the subsecuent instructions is
executed.
MPU90-38
TOSHIBA
TMP90C840
Table 3.3 (1) lists the possible interrupt sources.
Table 3.3 (1)
I
Interrupt Sources
I
IPriorityl
order
Type
Interrupt source
Non
SWI instruction
maskablelNMI(Input from NMI pin)
I INTWD (watchdog)
I INTO (Externa 1 input 0)
I INTTO (Timer 0)
I INTTI (Timer 1)
I INTT2 (Timer 2)
I INTAD (AID Converter)
Maskablel INTT3 (Timer 3)
I INTT4 (Timer 4)
I INTI (Externa 1 input 1)
I INTT5 (Timer 5)
I INT2 (External input 2)
I INTRX (End of serial
receiving)
I
I INTTX (End of serial
transmission)
I
1
2
3
4
5
6
7
7
8
9
10
11
12
13
14
(Note)
I Start ad-I Start adIVectorldress of Idress of
Ivalue Igeneral IMico DMA
I
I purpose Iprocessingl
I
I interrupt I parameter I
I
I
I process- I
I
I
I
I ing
I 10H I 001 OH I
I
I
I 18H I 0018H I
I
I 20H I 0020H I
I
I 28H I 0028H I FF28H
I
I 30H I 0030H I FF30H
I 38H I 0038H I FF38H
I
I
I 40H I 0040H I FF40H
I
I 40H I 0040H I FF40H
I
I 48H I 0048H I FF48H
I
I 50H I 0050H I FF50H
I
I 58H I 0058H I FF58H
I 60H I 0060H I FF60H
I
I 68H I 0068H I FF68H
I
I
I 70H I 0070H I FF70H
I
I
I
I
I
I 78H I 0078H I FF78H
i
I
I
I
Either INTT2 or INTAD is selected by software.
The "priority order" in the table is the order of the interrupt source
used by the CPU for accepting more than one interrupt requested at one
time.
If interrupt of fourth and fifth orders are requested simultaneously,
for example, an interrupt of the "5th" priority is acknowledged after
a "4th" priority interrupt processing has been completed by a RETI
instruction. However, a lower priority interrupt can be acknowledged
immediately by executing an EI instruction in a program that processes
a higher priority interrupt.
The internal interrupt controller merely determines the priority of
the sources of interrupts to be acknowledged by the CPU when more than
one interrupt are requested at a time.
It is, therefore, unable to
compare the priori ty of interrupt be ing executed with the one be ing
requested.
3.3.2
Micro DMA processing
Fig. 3.3 (3) is a flowchart of the micro DMA processing.
Parameters
(addresses of source and destination, and transfer mode) for the data
transfer between memories are loaded by the CPU from an address
modified by an interrupt vector value.
After the data transfer
between memories accroding to these parameter, these parameters are
MPU90-39
TOSHIBA
TMP90C840
updated and saved by the CPU into the original locations.
The CPU
then decrements the number of transfers, and completes the micro LMA
processing unless the result is "0".
If the number of transfer becomes "0", the CPU {7roceeds to the general
purpose interrupt handling described in the previous chapter.
Micro DMA Processing
Loading of Parameters
DST ~ (FFOOH+V+l)W
SRC ~ (FFOOH+V+3)W
CMD ~ (FFOOH+V+S)
Data Transfer between Memories
(DST) ~ (SRC)
DST ~ DST + 0/1/2
SRC ..-- SRC ±0/1/2
Saving of Update Parameters
(FFOOH+V+3)W ~ SRC
(FFOOH+V+l)W ~ DST
Decremen t of No. of Transfer
Count ~ (FFOOH+V)
Count ~ Count-l
(FFOH+V) ~ Count
Yes
General-purpose
Interrupt Processing
Fig. 3.3 (3)
Micro DMA Processing Flowchart
The micro DMA processing is performed by using only hardware to
process interrupts mostly completed by simple data transfer. The use
of hardware allows the micro DMA processing to handle the interrupt in
a higher speed than the conventional methods using software. The CPU
registers are not affected by the micro DMA processing.
Fig. 3.3.(4) shows the functions of parameters used in the micro DMA
processing.
MPU90-40
TOSHIBA
TMP90C840
FFOOH+V+O
I
Number of transfer
FFOOH+V+l
I
Destination address (Lower)
FFOOH+V+2
I
Destination address (Upper)
FFOOH+V+3
I
Source address (Lower)
FFOOH+V+4
Source address (Upper)
7
5
6
4
2
3
1
0
FFOOH+V+5
(Transfer mode)
x
I
x
I
x
I
x
I
x
I
I
I
I
I
I
I
I
I
I
I
I
0
1
(Note)
x
0
0
0
1
1
0
1
1
Fix current destination/source addresses
Increment destination
address
Increment source address
Decrement source address
I-byte transfer
2-byte transfer
don't care
Fig. 3.3 (4)
Parameters for Micro DMA Processing
Parameters for the micro DMA processing are located in the internal
RAM area (See Table 3.3 (1)
Interrupt Sources). The start address of
each parameter is "FFOOHH + interrupt vector value", from which a six
bytes' space is used for the parameter.
This space can be used for
any other memory purposes if the micro DMA processing is not used.
The parameters normally consist of the number of transfer, addresses
of destination and source, and transfer mode.
!he number of transfer
indicates the number of data transfer accepted in the micro DMA
processing.
The amount of data transferred by a single micro DMA processing is
limited to one or two bytes.
Both the destination and source
addresses are specified by 2-byte data.
The address space available
for the micro DMA processing ranges from OOOOH to FFFFH.
Bit s 0 and 1 of the transfer mode indicates the mode updat ing the
source and/or destination, and the bit 2 indicates the data length
(one byte or two bytes).
MPU90-41
TOSHIBA
TMP90C840
Table 3.3 (2) shows the relation between the transfer mode and the
result of updating the destination/source addresses.
Table 3.3 (2)
Addresses Updated by Micro DMA Processing
Transfer
mode
000
Function
I-byte transfer:
001
I-byte transfer:
010
I-byte transfer:
011
I-byte transfer:
100
2-byte transfer:
101
2-byte transfer:
110
2-byte transfer:
III
2-byte transfer:
\Destination\ Source \
\ address \ address \
Fix the current source/ \
0
\
0
destination addresses
\
\
Increment the destination\
+ 1
o
address
\
+ 1
Increment the source
o
\
address
\
o
Decrement the source
- 1
\
address
\
Fix the current source/ \
o
o
destination addresses
\
+ 2
Increment the destination\
o
address
\
Increment the source
o
+ 2
\
address
\
Decrement the source
o
- 2
\
address
\
In the 2-byte transfer mode, data are transferred as follows:
(Destination address)
(Destination address+l)
<<-
(Source address)
(Source address+l)
Similar data transfers are made in the modes that "decrement the
source address", but the updated results are different as shown in the
table 3.3 (2).
Fig. 3.3 (5) shows an example of the micro DMA processing that handles
data receiving of internal serial I/O.
This is an example of executing "an interrupt processing program after
serial data receiving" after receiving 7-frame data (Assume 1 frame =
1 byte for this example) and saving them into the memory addresses
from FFOOH to FF06H.
MPU90-42
TOSHIBA
TMP90C840
Initial setting for serial receiving
CALL
SET
SIOINIT
1,(FFE6H)
SET
1,(FFE8H)
LD
LDW
LDW
(FF70H),7
(FF71H) ,FFOOH
(FF73H) ,FFEBH
LD
(FF75H),1
Enable an interrupt for serial data
receiving.
Set the micro DMA processing mode for the
interrupt.
Set the number of transfer = 7
Set FFOOH for the destination address.
Set
FFEBH
for
the
source
(serial
receiving buffer) address.
Set the trans fer mode (I-byt e transfer:
Increment destination address).
EI
ORG
0070H
Interrupt processing program
after serial data receiving
REETI
Fig. 3.3 (5)
Example of Micro DMA Processing
The bus operation in the general purpose interrupt processing and the
micro DMA processing is included in "Table 3.2
Bus Operation for
Executing Instructions" in the previous section.
The micro DMA processing time (when the number of transfer is not
decremented to 0) is 46 states without regard to the I-byte/2-byte
transfer mode.
Figure 3.3 (6) shows the interrupt processing flowchart.
MPU90-43
TOSHIBA
TMP90C840
Reading of
Interrupt
Vector 'V'
YES
Data Transfer
for Micro-DMA
General-Purpose
Interrupt
Processing
PUSH PC
PUSH AF
IFF -+- 0
Micro-DMA Processin<
YES
Interrupt
Processing
Program
Instr.llction
of RETI
POP AF
POP PC
END
Fig. 3.3 (6)
Interrupt Processing Flowchart
MPU90-44
TOSHIBA
3.3.3
TMP90C840
Interrupt controller
Fig. 3.3 (8) outlines the interrupt circuit.
The left side of this
figure represents an interrupt controller, and the right side
comprises the CPU's interrupt request signal circuit arid HALT release
signal circuit (See "3.4 Standby Function" for the HALT operation).
The interrupt controller consists of Interrupt Request Flip-flops,
interrupt enable flags, and micro DMA enable flags allocated to each
of 14 channels.
The Interrupt Request Flip-flops serve to latch
inter~upt requests from peripherals.
Each flip-flop is reset to "0"
when a reset or interrupt is acknowledged by the CPU and the vector of
the interrupt channel is read into the CPU, or when the CPU executes
an instruction that clears a request to interrupt that channel (write
"vector divided by 8" into the memory address FFC3H). For example, by
executing
LD (FFC3H), s8Hi8,
the Interrupt Request Flip-flops for the interrupt channel "INTI"
whose vector is 58H is reset to "0".
The status of an Interrupt Request Flip-flops is found out by reading
the memory address FFC2H or FFC3H.
"0" denotes there is no interrupt
request, and "1" denotes that an interrupt is requested. Fig. 3.3 (7)
illustrates the bit configuration indicating the status of Interrupt
Request Flip-flops.
IRFL ____~/_IR~F~O~/~IR~F~T~O~I_IR~F_T~l~I____~E~XT
__~IP~I~C~R~1P~O~C__
R
(FFC2H)
I
I
See "3.5.2 Port 1".
I
I_R___> INTT 1 req ue s t flag
________
R___> INTTO request flag
______________R___> INTO request flag
IRFH IIRFT21IRFT31IRFT41IRFI /IRFT5IIRF2 I IRFRXI IRFTXI
(FFC3H)
I
I~> INTTX req uest flag
R > INTRX request flag
INT2 req uest flag
R
R > INTTS req uest flag
> INTI request flag
R
> INTT4 req uest flag
R
> INTT3 req uest flag
R
R > INTT2/INTAD request
> flag
(Caution)
Writing "vector divided by 8" into the memory address
clears the Flip-flop for the specified interrupt request.
Fig. 3.3 (7)
Configuration of Interrupt Request Flip-flops
MPU90-45
FFC3H
Interrupt Controller
Instruction
of sIn
~-1--~r-------::v:-:=::-:;-lnO;)H
CPU
NHI -..--+-----IJ.-_ _ _ _ _ _ _..;.v_=--=.1.;;.8H~
INTWD---4------~------~M~ic-r-o~DMA~--~V-=--2-0~H~
Enable Flag
Dn
3 Input OR
Non
Maskable
Interrupt
Request
Interrupt Enable
Flag of CPU
Interrupt
11 Input OR
Request
signal
Maskable
Interrupt
Request
Halt Release
Signal
DO
01
02
D3
D4
05
06
07
Read of
Interrupt
vector
Reset
TOSHIBA
TMP90C840
The interrupt enable flags provided for all interrupt request channels
are assigned to the memory address FFE7H or FFE8H.
Setting any of
these flags to "1" enables an interrupt of the respective channel.
These flags are initialized to "0" by resetting.
The micro DMA enable flag also provided for each interrupt request
channel is assigned to the memory address FFE6H or FFE7H.
The
interrupt request for each channel is placed in the micro DMA
processing mode by setting this flag to "I". This flag is initialized
to "O~' (general purpose interrupt processing mode) by resetting.
Fig. 3.3. (9) shows the bit configuration of the interrupt enable
flags and micro DMA enable flags.
Interrupt by Timer 2 (INTT2) and that by AID converter (INTAD) use a
common interrupt req uest channel.
The interrupt controller firs t
accepts INTT2 after a reset.
IN TAD can be used by setting the
"INTT2/INTAD selection bit" (ADIS: Bit 3 of memory address FFE7H) to
"I".
Attention should be paid to the following three modes having special
circuits:
I INTO Level mode
I
If INTO is not an edge-based interrupt, the
function of Interrupt Request Flip-flop is
cancelled. Therefore the interrupt request
signal must be held until the interrupt
request is acknowledged by the CPU. A change
in the mode (between edge and level) automatically clears the interrupt request flag.
1
1
1
1
1
1
1
1
1--------------------1-----------------------------------------------1
1
1
1
1
1
I
I
I
1
1
The Interrupt Req uest FI ip-flop can be cleared 1
only by resetting or reading the register thatl
stores AID conversion value, and cannot be
cleared by an instruction. A change in the
interrupt source (between INTAD and INTT2)
1
automatically clears the interrupt request
1
flag.
I
I
I
1
I
I channel receiving buffer, and not by an
1
1
I
1
INTAD' level mode
I
I
1
1
1--------------------1-----------------------------------------------1
INTRX level mode
The Interrupt Request Flip-flop is cleared
1
1 only by resetting or reading the serial
1
instruction.
MPU90"";47
I
I
TOSHIBA
TMP90C840
Interrupt enable flags
INTEL I IET2 IIET3 I IET4
(FFE6H)
lEI I lETS I lE2 I IERX I IETX
R/W
> INTTX
interrupt
enable flag
____ > INTRX interrupt
enable flag
______ > INT2 interrupt
enable flag
_________ > INTTS interrupt
enable flag
___________> INTI interrupt
enable flag
______________ > INTT4 interrupt
enable flag
________________> INTT3 interrupt
enable flag
___________________> INTT2 interrupt
enable flag
1__
Interrupt and micro DMA enable flags
INTER I "0" I DEO IDErO IDET1 I ADIS
(FFE7R)
lEO IIETO I lET 1 I R/W
1__
> INTTI interrupt
enable flag
interrupt
enable flag
_ _ _ _ _ _ ) INTO interrupt
enable flag
_ _ _ _ _ _ _ _ _ ) INTT2/INTAD selection
* I 0 I INTT2 I
I
I 1 I INTAD
_ _ _ _ _ _ _ _ _ _ _) INTTl DMA enable flag
_ _ _ _ _ _ _ _ _ _ _ _ _ _) INTTO 1l1A enable flag
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) INTO DMA enable flag
Write "0"
* indicates the initial)value after reset.
___ > INTTO
Micro DMA enable flags
DMAEH IDET2 IDET3 IDET4
(FFE8H)
DEI IDETS
DE2 IDERX IDETX
R/W
1--) INTTX DMA enable flag
---)
------)
----------)
----------------)
-----------------)
--------------------)
-------------------------)
INTRX
INT2
INTTS
INTI
INTT4
INTT3
INTT2
Fig. 3.3 (9) Interrupt/Micro DMA Enable Flags
MPU90-48
1l1A
DMA
DMA
DMA
DMA
DMA
DMA
enable
enable
enable
enable
enable
enable
enable
flag
flag
flag
flag
flag
flag
flag
TOSHIBA
3.4
TMP90C840
Standby Function
When a HALT instruction is executed, the TMP90C840 selects one of the
following modes as determined by the halt mode set register:
(1)
RUN
Suspends only the CPU operation.
remains unchanged.
(2)
IDLE.l
Sus pends
all
interna 1 circui t s
except
the
interna 1
osc illator.
In this mode, the power consumpt ion is les s
than 1/10 of that in the normal operation.
(3)
IDLE2
Operate only the internal oscillator and specific internal
I/O devices.
The power consumption is less than 1/ 3 of
that in the normal operation.
(4)
STOP
Suspends all internal
oscillator.
In this
considerably reduced.
The power
consump t ion
circuits including the internal
mode, the power consumption 1S
The HALT mode set register (HALTM) is assigned to the bits 2 and 3 of
the memory address FFD2H in the internal I/O register area (other bits
are used to control other functions).
The register is reset to "00"
(RUN mode) by resetting.
These HALT state can be released by resetting or requesting an
interrupt. Either a non-maskable or maskable interrupt is acknowledged
and processed if the CPU executes the EI (enable interrupt) instruction.
However the CPU executes the DI (disable interrupt) instruction, a
maskable interrupt may be accepted, and the CPU starts execut ing the
instruction following the HALT instruction.
7
6
5
4
WDTOUT
WDMOD IWDTE
I WARM
(FFD2H) I
I
See "3.10 Watchdog Timer"
3
HALTM
I
I
I
I
I
I
I
I
I
I
I
I
0
0
0
1
0
1
1
1
Fig. 3.4 (1)
2
1
0
EXF IDRVE
I
I
I
I- ) See "3.4.4 STOP mode II
I
Exchange flag
I
)
See "3.1.2 Registers"
RUN
STOP
IDLE 1
IDLE2
HALT Mode Set Register
MPU90-49
TMP90C840
TOSHIBA
3.4.1
RUN Mode
Fig. 3.4 (2) shows the timing for releasing the
interrupts in the RUN/IDLE 2 mode.
In the RUN mode, the system clock in the MCU continues
after a HALT instruction is executed.
Only the CPU
the instruction.
Until the HALT state is released,
dummy cycles. In the HALT state, an interrupt request
the r.is ing edge of the "CLK" signa 1.
Xl
...,
RD
V
-~
II
~
by
to operate even
stops executing
the CPU repeats
is sampled with
~I
V
1\
~
~
If
)I
~
Next
C
Next + 1
OC
"
I'
~
"
J'
J
I'r-
~
"
WR
D¢ - 7
state
L.r LrLr L.r L.rLrLn.1MJ1lJ1lJ1Lr Lr L.r U
eLK
A¢ - 19
HALT
I
- 1---- --- ---- ~ --- ---- -----1f---- - - - - - - --~
'c.
II
NMI
INT¢
(Level)
1----
~ r.-~
\
{~~
JI
INT¢'1'2
(Rising Edge)
(C,
H
Internal INT
"
11"
HALT 1nstruct10n
Execution Sequence
Fig. 3.4 (2)
Interrupt Acknowlec
Sequence
Timing Chart for Releasing the HALT State by
Interrupts in RUN/IDLE 2 Modes
MPU90-S0
TOSHIBA
3.4.2
TMP90C840
IDLE 1 mode
Fig. 3.4 (3) illus trates the t lmlng for releas ing the HALT stat e by
interrupts in the IDLE 1 mode.
In the IDLE 1 mode, only the internal osci llator and the watchdog
timer counter operate. The system clock in the MCU stops, and the CLK
signal is fixed at the "1" level.
In the HALT state, an instruction request is sampled asynchronously
with the system clock, however the HALT release (restart of operation)
is performed synchronously with it.
(Note)
Xl
"\
An interrupt requested by the watchdog timer
through the HALT period in this mode.
~IJlUl'JllJl Jl
is
prohibited
LnJhJllJl JlL.nUlJlU
J(
V
eLK
A¢ - 19
-_rJ...
~
)J
I
1\
V
\
r--
.(
JJ
~
Next
~
n
Next + 1
-
((
RD
J
((
WR
D¢ - 7
~
JI
j
\
JJ
--- 1 - - - ~----5f---- ~--- --- ---- r-::--,
~
--- ~-- --- --- ~ 1 - ~
tf
}/
NMI
INT¢
(Level)
j{
JJ
['¢·1·2
((
JJ
Lsing Edge)
m
HAL~
Instruct~on
Exeqution Sequence
Fig. 3.4 (3)
3.4.3
J\
Interrupt Acknowledge
Sequence
Timing Chart of HALT Released by
Interrupts in IDLEI Mode
IDLE 2 mode
Fig. 3.4 (2) shows the timing of HALT release caused by interupts in
the RUN/IDLE 2 mode.
MPU90-51
TOSHIBA
TMP90C840
In the IDLE2 mode, the HALT state is released by an interrupt with the
same timing as in the RUN mode, except the internal operation of the
MCU.
In the RUN mode, only the CPU stops executing the current
instruction, and the system clock is supplied to all internal devices.
In the IDLE 2 mode, however, the sys tem clock is suppl ied to only
specific internal I/O devices.
As a result, the HALT state in the
IDLE 2 mode requires only a 1/3 of the power consumed in the RUN mode.
In the IDLE 2 mode, the system clock is supplied to the following I/O
devices:
o
o
o
o
3.4.4
8-bit timer
16-bit timer
Serial interface
Watchdog timer
STOP mode
Fig. 3.4 (4) is a timing chart for releasing the HALT state by
interrupts in the STOP mode.
The STOP mode is selected to stop all internal circuits including the
internal oscillator.
In this mode, all pins except special ones are
put in the high-impedance state, independent of the internal operation
of the MCU. Table 3.4 summarizes the state of these pins in the STOP
mode.
Note, however, that the pre-halt state can be retained by
setting the internal I/O register DRVE (Drive enable: Bit 0 of memory
address FFD2H) to "1". The content of this register is initialized to
"0" by resetting.
When the CPU accepts an interrupt request, the internal oscillator is
restarted immediately.
However, to s tabil ize the oscillation, the
system clock starts its output after the time set by the warming up
counter WARM (Warming up: Bit 4 of . memory address FFD2H) ha1tfassed16
A warming-up time of either the clock oscillation time x 2
or 2
can be set by setting this bit to either "0" or "1".
This bit is
initialized to "0" by resetting.
MPU90-52
TOSHIBA
TMP90C840
Warming-up
Time
Xl
"""\
Jl .JllJl JlIJ
LrtnLI' LI'L!llJl~r-I~:Jl
,
V
CLK
Ar/; - 19
_OC
r~--H---'{
~
JJ
I~
I
"
,,- I J
Next
~--H--- Il
OC
((
RD
~
JJ
~-""'f---
I
~
Next + 1
OC
..I'
,
\
\
Jr--
t,
WR
Dr/; - 7
~-"5---
... 1 - - - --
~-
Ir:--\.
p
~--
--
'I
7)
~-~T--- ~J----
--
--- --
1 - - -~
~
--
If
.J)
NMI
\
rr
)J
I "
INTr/;
J)
(r..
(Level)
~
JJ
·1·2
ing Edge)
{G-
1/
HALT Instruct~on
Execution Sequence
Fig. 3.4 (4)
r
rr
J
Interrupt Acknowledge
Sequence
Timing Chart of HALT Released by
Interrupt in STOP 2 Mode
The internal oscillator can be also restarted by the input of the
RESET signal at "0" to the CPU. In this case, however, the warming-up
counter remains inactive because the power is turned on too quickly.
As a result, the normal clock operation may not be performed due to
the unstable clock supplied immediately after restarting the internal
oscillator. To avoid this, it is necessary to keep the RESET signal
at "a' long enough to release the HALT state in the STOP mode.
MPU90-53
TOSHIBA
TMP90C840
Table 3.4
State of Pins in STOP Mode
(DRVE bit is set to "0")
1
Pin Name
1
State
1
1--------------------1-------------------------1
POO - P07/DO - 7 1 High impedance
P10
P17 / AO - 7 1 High impedance
P27/A8 - 15 1 High impedance
P20
P30
P37
1 High impedance
P40
P43/A16 - 191 High impedance
P50
P55
1 High impedance
P60
P63
1 Pre-HALT state
Pre-HALT state
P70
P73
1
Ready for input
P80
1
High impedance (Note)
P81
1
High impedance (Note)
P82
1
High impedance
P83
1
Ready for input
NMI
1
High impedance
CLK
1
Ready for input
EA
1
Ready for input
RESET
1
High impedance
Xl
1
X2
"1"
1
(Note)
3.5
P81 and P82 are pulled up slightly in the zero-cross
detection mode.
Functions of Ports
The TMP90C840 contains total 54 bits input/output ports.
These ports
function not only for the general-purpose I/O but also for the
input/output of the internal CPU and I/O devices. Table 3.5 describes
the functions of these ports.
MPU90-54
TOSHIBA
TMP90C840
Table 3.5
Functions of Ports
Port I Pin name INa. ofl Direction IDirection set unitl
Pin name for
name I
I pins I
I
I internal function
Port 0 I POO - P071
8 I
I/O
I
Byte
I DO - D7
I
------1----------1------1-----------1------------------1-------------------1
Port 11 PIO - P171
8 I
I/O
I
Byte
I AO - A7
I
------1----------1------1-----------1------------------1-------------------1
Port 21 P20 - P271
8 1
I/O
1
Bit
1 A8 - AIS
1
------1----------1------1-----------1------------------1-------------------1
Port 31 P30
1
1 1
Input
1 RxD
1
1
I 1
Input
1 RxD
1
1 P31
1
1 1 Output
1 TxD/RTS/SCLK
1 P32
1
I 1 Output
1 TxD
1 P33
1 P34
1
1 1
Input
1 CTS
1 P3S
I
I lOut put
I RD
1 P36
I
I 1 Output
1 WR
I P37
1
1 1
Input
1 WAIT
------1----------1------1----------- ------------------1------------------1Port 41 P40 - P431
4 1
Output
1 A16 - Al9
1------1----------1------1----------- ------------------1------------------IPort SI PSO - PSSI
6 I
Input
I ANO - ANS
1------1----------1------1----------- ------------------1------------------1Port 61 P60 - P631
4 1
I/O
Bit
1 MOO - M03/T01
1------1----------1------1----------- ------------------1------------------1Port .71 P70 - P731
4 1
I/O
Bit
1 MIO - Ml3/T03
1------1----------1------1----------- ------------------1-------------------1
1Port 81 P80
1
I 1
Input
1 INTO
1
1
1 1
Input
1 INTI/TI4
1
1
1 P81
1
1 p82
1
1 1
Input
1 INT2/TIS
1
1
1 P83
1
I 1 Output
1 T03/T04
1
These port pins function as the general-purpose input/output ports by
reset t ing.
The port pins, for wh ich input or output is programmably
selectable, function as input ports by resetting. A separate program is
required to use them for an internal function.
The TMP90C841 functions in the same way as the TMP90C840 except:
a Port 0 always functions as a data bus (DO to D7).
a Port I always functions as Address bus (AO to A7).
a Port 2 always functions as Address bus (A8 to AlS).
a P3S, P36 and P37 of Port 3 always function as RD, WR and WAIT
pins, respectively.
3.S.1
Port 0 (POO - P07)
Port 0 is an 8-bit general-purpose I/O port (PO: memory address FFCOH)
whose I/O function is specified by the control register (POC: bit 0 of
memory address FFC2H) for each byte.
By resetting all bits of the
control register are initialized to "0", whereby Port 0 turns to the
input mode, and the contents of the output latch register are
undefined.
MPU90-SS
TOSHIBA
TMP90C840
In addition to the general-purpose I/O port function, it functions as
a data bus (DO - 07).
Access of an external memory makes it
automatically function as a data bus.
Reset
Write POCR
H
:::l
rT
ro
11
:::l
Port 0
(POO - P07)
~
o
PJ
~
Write PO
g'
Ul
Read PO
Fig. 3.5 (1)
3.5.2
Port
a
Port I (PIO - PI7)
Port 1 is an 8-bit general-purpose I/O port (PL: memory address FFCIH)
whose I/O function is specified by the control register (PIC: bit 1 of
memory address FFC2H) for each byte. All bits of the output latch and
the control register are initialized to "0" by resetting, whereby Port
I is put in the input mode.
In addition to the general-purpose I/O port function, it functions as
an address bus (AO - A7). The address bus function can be selected by
setting the external extension control register (EXT: bit 2 of memory
address FFC2H) to "1" regardless of the status of the above control
register (p IC) . The EXT register is reset to "0" whereby Port land
Port 2 turn to the general-purpose I/O mode.
The EXT register of the TMP90C841 is always set to "1" so that Port 1
functions as an address bus (AO - A7).
MPU90-56
TMP90C840
TOSHIBA
Reset
H
!:l
rt
CD
Ii
!:l
Port 1
~~--~
(P10 - P17)
o
llJ
rt
llJ
tI1
C
Ul
Read Pl
Fig. 3.5 (2)
MPU90-57
Port 1
TOSHIBA
TMP90C840
Port 0 Register
PO
1 P07 1 P06 1 POS 1 P04 1 P03 1 P02 1 POI 1 POO 1 R/W
(FFCOH)
Port 1 Register
PI
1 P17 1 P16 1 PIS 1 P14 1 P13 1 P12 1 Pll 1 PIO 1 R/W
(FFCIH)
Port 0/1 Control Register
POICR
(FFC2H)
1 ____
~I~I~RF_O~I~I=R_FT~O~I_I=R_FT_l~I~__~1_E_X_T~~P=l_C~_P_o_c_1
W
1__ > Set I/O of Port 0
R
See "3.3.3 Interrupt controller"./
*
1
1
/
/
/
1
1 1 / Output
/
W
____ > Set I/O of Port I
/
* /
/
0 / Input
/
/---/----------/
/
/ I / Output
/
/
1 0 1 Input
1---/----------/
/
W
/______ > Set
general-purpose
port/address bus of
Ports I and 2
* /
/
1
0 / General- /
1 purpose /
1 port
/
1---1----------1
/ I / Address
/
/ bus
*
Fig. 3.5 (3)
indicates initial
value after reset.
Registers for Ports 0 and I
MPU90-58
/
/
TOSHIBA
3.5.3
TMP90CB40
Port 2 (P20 - P27)
Port 2 is an B-bit general-purpose I/O port (P2: memory address FFC4H)
whose I/O functionsis specified by the control register (P2CR : bit 1
of memory address FFC5H) for each bit.
All bits of the output latch
and the control register are initialized to "0" by resetting , Whereby
Port 2 turns to the input mode.
In addition to the general-purpose I/O port function, it functions as
an address bus (AB - A15).
The address bus func t ion can be se lec ted
by setting the EXT register (EXT: bit 2 of memory address FFC2H,
shared with port 1) to "I" and set t ing the Port 2 control regis ter
(P2CR) to the output mode. When the Port 2 control register is set to
"0", Port 2 functions as an input port, regardless of the status of
the EXT register.
For the TMP90CB41, all bits of the EXT register and the control
register are always set to "1", and Port 2 functions as an address bus
(AB to A15).
Reset
H
~
rT
Write
p2CR
CD
ti
~
Port 2
(P20-P27)
Pl
.....
0
$lJ
rT
Pl
to
c
Write
P2
Ul
Read P2
Fig. 3.5 (4)
MPU90-59
Port 2
TMP90C840
TOSHIBA
Port 2 Register
P2
I P27 I P26 I P25 I P24 I P23 I P22 I P21 I P20 I R/W
(FFC4H)
Port 2 Control Register
P2CR Ip27C Ip26C Ip25C Ip24C Ip23C Ip22C Ip2lC Ip20C I W
(FFC5H)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
*
t
IEXI=OI
IEXI=ol
IEXT=ll
IEXT=ll
*
t
t
t
t
-t
t
-t
t
0 IInput IInput !Input IInput IInput IInput IInput IInput I
1 IOutputlOutputl Output I Output I OutputlOutputlOutputlOutp uti
0 I Input IInput IInput IInput IInput IInput IInput IInput I
1 I Al5
I Al4
I Al3
I Al2
I All
I AIO
indicates initial value after reset.
Fig. 3.5 (5)
Registers for Port 2
MPU90-60
I A9
I A8
I
TOSHIBA
3.5.4
TMP90C840
Port 3 (P30 - P37)
Port 3 is an 8-bit general-purpose I/O port (P3: memory address FFC6H)
with fixed I/O function.
All bits of the output latch are set to "1",
and "1" is generated to the output port.
In addition to the I/O port function, P30 - P34 have the I/O function
for the internal serial interface, while P35 - P37 have the external
memory control function.
The additional functions can be selected by
the control register (P3CR: memory address FFC7H).
All bits of the
control register are initialized to "0" by resetting, by which the
port turns to the general-purpose I/O port mode.
However, access of an external memorLmakes P35 _-_P37 automat ically
function as the memory control pins (RD, WR and WAIT), and access of
an internal memory makes them function as general-purpose I/O ports.
When an external memory is accessed , therefore, the output latch
regis ters P35 eRD) and P36 (WR) shou ld be kept at "1" which is the
initial value after the reset.
The bit 5 (RDE) of the control r~gister is intended for a pseudostatic
RAM.
When set to "1", it always functions as an RD pin.
It is set to
"0" by reading the internal I/O unit.
Reset
Port 3 Output
(P32, P33, P35, P36)
H
~
rT
CD
I'i
Write P3
~
llJ
I-'
0
llJ
rT
llJ
tJ:l
Read P3
C
Ul
Port 3 Input
(P30, P31, P34, P37)
t
Read P3
Fig. 3.5 (6)
MPU90-61
Port 3
TMP90C840
TOSHIBA
Port 3 Register
P3
(FFC6H)
1
P37
R
P36
R/W
P35
R/W
P34
R
P33
R/W
P32
R/W
P31
R
P30
R
Port 3 Control Register
P3CR
(FFC 7H)
1
WAITC
RDE
ODE
TXDC
RXDC
-----~----:....---:---~--.:....----.;..--
1_--:----
R/W
1
1
See "3.8 Serial Channel".
R/W
1 ______ >
Set port P33 to open drain output
1
1
* 1 0 1 CMOS
output
1
1---1----------------------------1
1 1 1 Open drain output
1
R/W
Set port P35 to fixed RD mode
----->
* 1 0 1 General-purpose I/O port 1
1---1----------------------------1
1 1 1 Fixed as an pin
1
R/W
_________>
WAIT control
*
1
001 2-state wait
1
1---1----------------------------1
* I
*
011 Normal wait
I
1---1----------------------------1
I 101 No wait
I
1---1----------------------------1
I 1 I Reserve
I
*
Fig. 3.5 (7)
indicates initial value after reset.
Register for Ports 3
MPU90-62
TOSHIBA
3.5.5
TMP90C840
Port 4 (P40 - P43)
Port 4 is a 4-bit port (P4: memory address FFC8H) intended only
the output.
All bits of the output latch are initialized to "0"
resetting, and "0" is generated from the port.
In addition to the output port function, it works as an address
(A16 - A19). The selection of the address bus function is made by
control register (P4CR: memory address FFC9H).
The output port
addre.ss bus function can be selected for each bit.
All bits of
contro 1 regis ter are init ial ized to "0" by reset t ing, by wh ich
port turns to the output mode.
H
Port 4
(P40 - P43)
~
lti .-----1
11
~
Pl
I-"
t:I
Write P4
Pl
rt
Pl
1l'1------<
c
t - - -...
Ul
Read P4
Fig. 3.5 (8)
MPU90-63
Port 4
for
by
bus
the
or
the
the
TMP90C840
TOSHIBA
Port 4 Register
P4
1
(FFC8H)
1 P43 1 P42 1 P41 I P40 I R/W
Port 4 Control Register
P4CR I
(FFC9H)
Ip43C Ip42C I P41C Ip40C I W
>
*
*
Set output port/
address bus
1 0 1 Output port 1
1---1-------------1
1 1 1 Address bus 1
indicates initial
value after reset.
Bank register BX
BX
1
(FFECH)
BX3
BX2
BXl
BXO I R/W
>
Address bus
A16 - A19
Bank register BY
BY
1
(FFEDH)
BY3
BY2
BYl
BYO 1 R/W
>
Fig. 3.5 (9)
Registers for Port 4
MPU90-64
Address bus
Al6 - Al9
TOSHIBA
TMP90C840
3.5.6
Port 5 (P50 - P55)
Port 5 is a 6-bit input port (P5: bit 0 - 5 of memory address FFCAH)
and also used as an analog input pin (ANO - AN5).
Writing data into Port 5 register is prohibited.
Port S
(PSO - PSS/ANO - ANS)
6 Channel
Analog
Multiplexer
Fig. 3.5 (10)
Port 5
Port 5 Register
P5
I
(FFCAH)
0
1
PS5 I P54 I P53 I PS2 I PSI I PSO I R
Fig. 3.5 (11)
Register for Port 5
MPU90-65
TOSHIBA
3.5.7
TMP90C840
Port 6 (P60 - P63)
Port 6 is a 4-bit general-purpose I/O port (P6: memory address FFCCH)
whose function is specified by the control register (P67CR: bits 0 - 3
of memory address FFCEH) for each bit.
The control register is
initialized to "0" by resetting, and Port 6 enters in the input mode.
This port is also serviceable as a stepping motor control port channel
o (MOO - M03) , so either the general-purpose I/O or the stepping motor
contrbl port can be selected by the control register (SMMOD: bits 0
and 1 of memory address FFCBH). This port is served as the generalpurpose I/O port by resetting.
Reset
r--
•
r-____________~------__--~~IDirectionl
LControl
~______~I
FunctionL,-
,r----------T----~
writ! P67CR
I Control
Write tMMOD
Shift...
H
~
rt
CD
•
r-----------~----------~I
output Ir---~----~--~~'
~ Latch
I
>--...---i
gPI
I--' 1 - - - - - 41
~
lJ
~
C
Ul
Output
Buffer
SA6
Shift Alternate
l Register
t_
L
r----
~-----------------.
Write P6
L,..-,-.
-
-----+
~\..._-J.... - - - - .
Read p6
Fig. 3.5 (12)
MPU90-66
Port 6
Port 6
(P60-p63
/MOO-M03)
TOSHIBA
3.5.8
TMP90C840
Port 7 (P70 - P73)
Port 7 is a 4-bit general-purpose I/O port (P7: memory address FFCDH)
whose I/O function is specified by the control register (P67CR: bits 4
- 7 of memory address FFCEH). The control register is initialized to
"a" by resetting, whereby Port 7 turns to the input mode.
This port is also serviceable as a stepping motor control port channel
I (MIa - MI3), so either the general-purpose I/O or the stepping motor
control port can be selected by the control register (SMMOD: bits 4
and 5 of memory address FFCBH).
It is served as the general-purpose
I/O port by resetting.
Reset
r-"'"
~____________4-__________+--1IDirectionl~________~~__~
IControl
,
r-______~IFunctionL-
I
writ! P67CR
I Control , -
t
Write SMMOD
l
Shift~
J Output I
r-.f Latch I
H
::l
rt
~
::l
PI
,w
I Shift
I-' t - - - - - I
o
~
tl1
C
Ul
SA7
Alternate
I Register
t~
________________~
1' . . . .
Output
Buffer
Port 7
(P70-P73
/MIO-M13)
TOSHIBA
TMP90C840
Port 6 Register
P6
ISA63 ISA62 ISA6l ISA60
(FFCCH)
1
W
P63
1 P62 1 P61 1 P60
R/W
Stepping motor
control port
Channel 0 shifter
alternate register
Port 6
Port 7 Register
P7
I SA73 I SA72 I SA7l I SA70
(FFCDH)
1
W
Stepping motor
control port
Channel 1 shifter
alternate register
P73 I P72 I P7l I P70
R/W
Port 7
Port 6 and 7 Register
P67CR Ip73C Ip72C Ip7lC Ip70C Ip63C Ip62C Ip6lC Ip60C
(FFCEH)
I________~--------~--------~--------w
________ )
Select input/output of
port 6
*
1
0
1
1
1
1
w
______________________________ )
Output
1
1
*
0
I
1
1
Input
1
Output
1
1----1-----------1
1
indicates initial
value after reset.
Registers for Ports 6 and 7
MPU90-68
1
Select input/output of
port 7
*
Fig. 3.5 (l4a)
Input
1----1-----------1
TOSHIBA
TMP90C840
Stepping motor mode register
SMMOD / SM7M
P70C
SM6M
P60C
(FFCBH) ------~------~----~-------
See "3.7 Stepping motor control
port".
/------~--~--~----~--~-/
/
/ R/W
/_->
P63
*
P62
Select function of Port 6.
(Port 6 Output Control)
P61
P60
/00/ IN/OUT / IN/OUT / IN/OUT / IN/OUT /
Shift
/
trigger /
/
/--1--------/--------/--------/--------/-----------/
/01/ IN/OUT / IN/OUT / IN/OUT / IN/TOl /
/
/--1--------1--------1--------1--------/-----------/
/10 /
/
/
/
/
/
/--/ IN/M03 / IN/M02 1 IN/MallIN/MOO 1 Timer 0,1 /
/11/
/
/
/
/
/
Shift trigger signal output timer for
stepping motor control
___ I
R/W
______________>
*
I P73
/
/
P72
Select function of Port 7.
(Port 7 Output Control)
P71
/
P70
/
I
/00/ IN/OUT / IN/OUT / IN/OUT / IN/OUT /
Shift
trigger /
/
/--/--------/--------1--------/--------/-----------/
1011 IN/OUT I IN/OUT I IN/OUT 1 IN/T03 I
I
1--1--------1--------1--------1--------1-----------1
110 I
1
1
1
1 Timer 2,3 1
1--1 IN/M13 / IN/M12 1 IN/Mll 1 IN/MIa 1-----------1
1111
I
I
I
I Timer 4
I
Shift trigger signal output timer for
stepping motor control
*
(Note)
indicates initial value after reset.
SM6M and SM7M are included in Fig. 3.7.
Fig. 3.5 (14b)
Register for Port 6 and 7
MPU90-69
TOSHIBA
3.5.9
TMP90C840
Port 8 (P8D - P83)
Port 8 is a 4-bit general-purpose I/O port (P8: memory address FFDOH),
with P80 to P82 intended only for the input and P83 only for the
output. The output latch of P83 is reset to "0", whereby the output
level turns to "L".
Port 8 also has the functions of interrupt request input, clock input
for a timer/event counter, and timer output.
(1) P80/INTO
P80 is a general-purpose input port, also used as the external
interrupt request input pin INTO. INTO allows the selection of either
an "H" level interrupt or rising edge interrupt by using the control
register (P8CR: Bit 0 of memory address FFDlH).
PSO/INTO
H
::l
rt
~
Read PS
::l
III
t-'
t::l
III
rt
III
tJj
~
en
PSCR
Fig. 3.5 (15)
Port P80/INTO
(2) P8l/INTl/TI4
P8l is a general-purpose input port, also used as the external
interrupt request input pin INTI and the clock input pin TI4 for the
timer/event counter.
This port incorporates a zero-eros s detec tion circuit, and enab les
zero-cross detection by connecting an external capacitor.
The zerocross detection can be disabled/enabled by using the control register
(P8CR: Bit 1 of memory address FFDIH). This control register is reset
to "0", making the zero-cross detection disabled.
(3)
P82/INT2/TI5
Like P8l, P82 is a general-purpose input port, als a used as the
external interrupt request input pin INT2 and the clock input pin TIS
for the timer/ event counter.
This port also contains a zero-cross
detection circuit, and disables/enables the zero-cross detection by
using the control register (P8CR: Bit 2 of memory address FFDIH).
When this control register is reset, the zero-cross detection is
disabled.
MPU90-70
TOSHIBA
TMP90C840
Capacitor
P81/I~4 f\f'\v
H
::l
rt
Control
I
INTO
Interrupt by "H"
I level detection
I
1---1-------------------1
I 1 I Interrupt
I
I
by ris- I
ind edge detection 1
w
P81/INTl/TI4 zero-cross
- - -> enable
*
1
(Zerp-Cross Enable P81)
0 I Disable
I
1---1-------------------1
I
1
I
Enable
1
w
P8Z/INTZ/TI5 zero-cross
- - - - -> enable
*
1
(Zerp-Cross Enable P8Z)
0 1 Disable
1
1---1-------------------1
1
liEnable
I
w
________> Select
*
1
FIG. 3.5 (18)
1
I
T03/T04
indicates initial value
after res et.
Registers for Port 8
MPU90-7Z
(P83 Output Control)
I P83
I
1---1-------------------1
1
*
0
P83 function
1
TMP90C840
TOSHIBA
3.6
Timers
The TMP90C840 incorporates four 8-bit timers and a 16-bit multi-function
timer/event counter.
The four 8-bit timers can operate independently,
two 16-bit timers through cascade connection.
operating modes are provided for the 8-bit timers:
o
o
o
o
8~bit
interval timer mode (4 timers)
l6-bit interval timer mode (2 timers)
possible arrangements: 8-bit x 2 and 16-bit x 1, or 16-bit x 2
8-bit programmable square wave (pulse) generation (pPG) mode (2
timers)
8-bit pulse width modulation (PWM) mode (2 timers)
The 16-bit multi-function
following six modes:
a
o
o
o
a
o
3.6.1
and also function as
The following four
timer/event
counter
can
operate
1n
the
16-bit interval timer mode
l6-bit event counter mode
16-bit programmable square wave (pulse) generation (pPG) mode
Frequency measurement mode
Pulse width measurement mode
Timer deviation measurement mode
8-bit timers
The TMP90C840 incorporates four
and 3), each of which can be
connection of Timer 0 and 1, or
as 16-bit internal timers.
Fig. 3.6 (1) is a block diagram
8-bit interval timers (Timers 0, 1, 2
operated independently.
The cascade
Timer 2 and 3 allows these timers used
of the 8-bit timers (Timer 0 and Timer
O.
Timer 2 and 3 have the same circuit configuration as Timer 0 and Timer
1 respectively.
Each interval timer is composed of an 8-bit up-counter, an 8-bit
comparator and an 8-bit timer/register, with a Timer Flip-flop
(TFF1/TFF3) provided to each pair of Timer 0 and Timer 1 and Timer 2
and Timer 3.
Internal clocks (~T1, ~T16 and ~T256), some of the input clock sources
for the interval timers, are generated by the 9-bit prescaler shown in
Fig. 3.6 (2).
Their operating modes of the 8-bit timers and flip-flops
are
controlled by four control registers (TCLK, TFFCR, TMOD and TRUN).
MPU90-73
TMP90C840
TOSHIBA
TFFCR3,2
set
reset
TRUNl
:'0:'
Trigger
TRUNO
r--Timer
I
I
¢Tl
I
I
¢T16
I
I
I
I
I
Match
I
I
I
I
: ¢Tl
: ¢T16
I¢T256
I
I
I
I
I
INTTOi
I
I
I
I
I
I
I
I
I
I
I
I
I
I
IL.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
I
~---------------Interrial Data Bus
Fig. 3.6 (1)
Block Diagram of 8-bit Timers (Timers 0 and 1)
MPU90-74
TOSHIBA
Select PWM 1 cycle
("Don't care" in non-PWM modes)
*
1001
I
1--1------------------------------1
6
lOll
2 -1
I
1--1------------------------------1
1101
27 - 1
I
1--1------------------------------1
8
I 11 I
2 - 1
I
R/W
____ > Set
*
operating mode of Timer
a
and 1.
1001 8-bit timer x 2
I
1--1------------------------------1
lOll 16-bit timer
I
1--1------------------------------1
1101 8-bit PPG output
I
1--1------------------------------1
1111 8-bit PWM output (Timer 1)
I
I I +8-bit timer (Timer 0)
I
R/W
________>
Select PWM 3 cycle
("Don I t care" in non-PWM modes)
*
1001
I
1--1------------------------------1
6
1011
2 - 1
I
1--1------------------------------1
7
110 I
2 - 1
I
1--1------------------------------1
8
III I
2
- 1
I
R/W
___________> Set
*
(Note)
operating mode of Timer 2 and 3.
1001 8-bit timer x 2
I
1--1------------------------------1
lOll 16-bit timer
I
1--1------------------------------1
1101 8-bit PPG output
I
1--1------------------------------1
1111 8-bit PWM output (Timer 3)
I
I I +8-bit timer (Timer 2)
I
* indicates initial value after reset.
R/W denotes that read or write is possible.
Fig. 3.5 (3) 8-bit Timer Mode register (TMOD)
MPU90-77
TMP90C840
TOSHIBA
Timer 3 Timer 2 Timer 1 Timer
I 7
6
I 5
4
I 3
2
I 1
a
a I
I
TCLK I T3CLK
T2CLK
TICLK
TOCLK
(F FD 8H ) I ___:...---.,;..._~-.;._--=--_~_
I
I
IR/w
I
I
I-> Timer a input clock
I
TMOD3,2 = 01
TMOD3,2
01
I I
I
I * 1001
Internal clock ~T1
1011 Internal clock 0T1
I
¢T16
~T16
1101
I
"
"
Not used
¢T256
1111
"
I
I
I
I R/W
I
> Timer 1 input clock
I
*
TMOD3,2 = 01
I
1001 Timer a comparator
I I outEut
1011 Internal clock ¢T1
q}T16
1101
"
q}T256
1111
"
TMOD3,2 = 01
Timer a overflow
output
R/W
>
Timer 2 input clock
TMOD7,6
01
I
1001
1011 Internal clock ~T1
¢T16
1101
"
q}T256
111\
"
I
*
TMOD7,6 = 01
Internal clock ¢T1
¢T16
"
Not used
R/W
>
*
(Note)
*
Timer 3 input clock
I
TMOD7,6 = 01
I
1001 Timer 2 comparator
I I outEut
1011 Internal clock ~T1
1101
"
¢T16
"
¢T256
1111
TMOD7,6 = 01
Timer 2 overflow
output
indicates initial value after reset.
Fig. 3.6 (4)
8-bit Timer Clock Control Register (TCLK)
MPU90-78
TOSHIBA
TMP90C840
7
1
TRUN 1
(F FD BH ) 1
16-bit timers
8-bit timers
5143210
6
BRATE
1
1
1
1
1
1
1
1PRRUNI T4RUNIT3RUNIT2RUNITIRUNITORUNI
1
1
1
1
1
1
1
--------~----~----~--~----~--~----
1
1
1
1
1 R/W
1__> Select Timer 0 operation
1
1
1
*
1 0 1 Stop and clear
1 1 1 Count
1
R/W
1_ _> Select Timer
1
*
operation
1 0 1 Stop and clear
1 1 1 Count
R/W
______> Select
*
Timer 2 operation
1 0 / Stop and clear
1 1 1 Count
R/W
_____________> Select
*
Timer 3 operat ion
1 0 / Stop and clear
/ 1 1 Count
R/W
______________ > Select
16-bit timer
(Timer 4) operation
*
1 0 1 Stop and clear
/ 1 / Count
R/W
____________________> Select
* /
prescaler operation
0 / Stop and clear
I 1 / Count
R/W
_________________ >
Select transfer speed of serial I/O
baud rate generator (fc=9.8304MHz)
*
(Note)
*
II
SC1,0=01
/00/ 300 baud
101/ 1200 baud
/101 4800 baud
111/19200
I
1 600 baud
12400 baud
/9600. baud
indicates initial value after reset.
R/W denotes that read or write is possible
Fig. 3.6 (5)
Timer/Serial Channel Control Registers (TRUN)
MPU90-79
SC 1,0=11
I 150 baud
TOSHIBA
TMP90C840
TFF3
7
I
I
TFFCR I
(FFD9H)I
I
TFFl
2
1
0 I
I 3
I
I
I
I
I
I
FFlC
IFF 1 IE I FF 1 IS I
IFF3IEIFF3IS1
I
I
I
I
I
I
I
I_-:--_1
I
6
5
FF3C
4
I
I
I
I
I
__________~------~----~~--~~I
1_ _ > Select inverse signal of timer flip-flop TFFI
*
00
I TMOD3,zl
I FFI IS
I
I
0
18-bit timer
I
Imode (Timer
I
1
18- bit timer
I
lmode (Timer
I
01
10
11
I
I
0) I
1)
I
I
I
I
I 16-bit timer modelPPG mode IpWM mode I
I (Timers 0 & 1)
I (Timer 1) I (Timer 1) I
R/W
___ > Invert
*
I
0
timer flip-flop TFFI
Disable
1--~1~--~-E-n-a~b-l-e-------------------------------------
W
________ > Control
00
01
10
11
timer flip-flop TFFI
Clear TFF1 to "0"
Set TFF1 to "1"
Invert value of TFFI (Software inversion)
Don't care (Always se t at "11" when re ad out)
R/W
_______ > Select
*
inverse signal of timer flip-flop TFF3
01
11
00
10
I TMOD7,61
I
I
I FF3IS
I
I
I
18-bit timer
0
I
I
I
Imode (Timer 2) I
I
I
18- bit timer
1
I 16-bit timer modelPPG mode I PWM mode I
I
Imode (Timer 3) I (Timers 2 & 3)
I (Timer 3) I (Timer 3) I
I
R/W
_ _ _ _ _ _ ) Invert timer flip-flop TFF3
o
1
Disable
Enable
W
_________ ) Control timer flip-flop TFF3
00
01
10
11
Fig. 3.6 (6)
Clear TFF3 to "0"
Set TFF3 to "1"
Invert value of.TFF3 (Software inversion)
Don't care (Always set at "11" when re ad out)
8-Bit Timer Flip-Flop Control Register (TFFCR)
MPU90-80
TOSHIBA
CD
TMP90C840
Timer registers
8-bi t regi s ter s are provided to se t
value of a timer register matches
signal of their comparators turn to
this signal becomes active when the
the interva I time.
When the se t
that of an up-counter, the match
the active mode. If "OOH" is set,
up-counter overflows.
®
Comparators
A comparator compares the values in an up-counter and a timer
register. When they matches, the comparator clears the up-counter to
"0", . and generates an interrupt signa I (INTTn) .
If the timer
flip-flop inversion is enabled by the Timer Flip-Flop control
register, the comparator inverts the Timer Flip-flop.
CD
Timer flip-flops (Timer F/Fs)
The status of the Timer Flip-flop 1.5 inverted by the match signal
(output by comparator).
Its status can be output to the timer output
pin TOI (also used as P60) and T03 (used as P70 or P80).
A Timer F/F is provided to each of the timer pairs Timer a - Timer 1
and Timern 2 - Timer 3, and is called TFFI and TFF3, respectively.
The status of TFFI is output to Tal, and that of TFF3 to T03. T03 has
2 pins (P70 and P83). P83 is selected only when the port 7 is used as
a stepping motor control port.
The Timer F/Fs are controlled by a timer flip-flop control register
(TFFCR) .
In the case of TFFI (timer F/F for the Timer a and Timer 1), the
flip-flop operation is described as follows:
TFFCRO (FFIIS) selects the signal for inversion of TFFI. In the 8-bit
timer mode, inversion is enabled by the match signal from Timer a if
this bit is set to "1", or by the signal from Timer 1 if set to "0".
In any other mode, FFIIS must be always set to "1". It is initialized
to "0" by resetting.
TFFCRI (FFIIE) controls the inversion of TFFI.
Setting this bit to
"1" enables the inversion and setting it to "0" disable.
FFIIE is initialized to "0" by resetting.
The bits TFFCR3 and TFFCR2 (FFIC) are used to set/reset TFFI or enable
its inversion by software. TFFI is reset by writing "00", set by "01"
and inverted by "10".
Similarly, TFF3 is controlled by TFFCR7 - 4.
The 8-bit timers operate as follows:
(1)
8-bit timer mode
The four interval timers 0, 1, 2 and 3 can operate independently as an
8-bit interval timer.
Only the operation of Timer 1 is described
because their operations are the same.
aD
Generating interrupts at specified intervals
Periodic interrup~s can be generated by using Timer 1 (INTT1) in the
following procedure:
Stop Timer 1, set the desired operating mode,
input clock and cycle time in, the registers TMOD, TCLK and TREGI
enable INTT1, and start the counting of Timer 1.
MPU90-81
TOSHIBA
TMP90CB40
Example:
To generate Timer 1 interrupt every 4.0us at fc=10 MHz, the
registers should be set as follows:
MSB
LSB
7 6 5 4 3 2 1 0
-
TRUN
TMOD
TCLK
<- - - <<- -
-
TREG1
INTER
IRUN
<- 0 0
<- <- - -
- - - - 1
- - - 1-
(Note)
x:
- - 0 -
Stop Timer 1, and clear it to "0".
Set the B-bit timer mode.
Select OT1 (O.Bus @fc=10 MHz) as the
input clock.
Set the timer register at 40us/Tl = 50.
Enable INTT l.
Start Timer 1.
0 0 x x
0 1
1 1 0 0 1 0
1
Don't care
No change
Use the following table for selecting the input clock:
Table 3.6 (1)
B-bit timer interrupt cycle and input clock
Interrupt cycle
O.Bus l2.Bus 204.Bus -
@fc=10 MHz
204us
3.264ms
52.429ms
Resolution
O.Bus
l2.Bus
204.Bus
Input clock
0Tl
~16
¢T256
Caution for using Timer 2
Interrupts generated by Timer 2 (INTT2) uses the same interrupt mask
flag (INTEL 7) as used for those of the AID converter (INTAD).
To
select either interrupt, another flag INTEH3 is provided.
Setting
this flag to "0" enables interrupts by Timer 2 and disables those by
the AID converter.
[2]
Generating pulse at 50% duty
The Timer Flip-flop is inverted at specified intervals, and its status
is output to a timer output pin (TOl or T03).
Example:
To output pulse from TOI at fc=10 MHz every 4.Bus, the
registers should be set as follows:
This example uses Timer I, but the same operation can be
effected by using Timer O.
7 6 543 2 1 0
TRUN
TMOD
TCLK
TREGI
TFFCR
<- - - - 0 <- 0 0 x x
<- - 0 1
<- 0 0 0 0 0 0 1 0
<- 0 0 1 1
SMMOD Tl
~Tl6
The timer (interrupt) cycle is selected by the lower eight bits set by
TREGO and the upper eight bits set in TREGl.
Note that TREGO must be
always set first (Writing data into TREGO disables the comparator
temporarily, which is restarted by writing data into TREGl).
Example:
To generate interrupts INTTl at fc=8MHz every 1 second,
timer registers TREGO and TREGl should be set as follows:
As ¢Tl6 (=16us @8MHz) is selected as the input clock,
1 sec/l6~s = 62500 = F424H
Therefore,
TREGl
F4H
TREGO
24H
the
The match signal is generated by Timer 0 comparator each time the
up-counter UCO matches TREGO. In this case, the up-counter UCO is not
cleared, and the interrupt INTTO is not generated.
Timer 1 comparator a Iso generates the match signa I each time the
up-counter UC I match TREGl.
When the match signal is generated
simultaneously from comparators of Timer a and Timer 1,
the
up-counters UCO and UCl are cleared to "0", and the interrupt INTTl is
generated.
If the Timer Flip-flop inversion is enabled by the Timer
Flip-flop control register, the timer flip-flop TFFl is inverted at
the same time.
MPU90-84
TMP90C840
TOSHIBA
Example:
Given TREGI
04H and TREGO
value of
Up-Counter
(UC1, UCO) OOOOH0080H
Timer 0
Comparator Match Signal
J
80H,
0180H
0280H
n
n
0380H
n
- - - - - ..._ _ _...... i . -_ _ _-'
Timer 1
Comparator Match
Signal
Interrupt INTTl
0400H
0480H
L
.nn
J~L---:
n----I
I
I
I
I
Timer Output TOl
________________________________~~rt Signal
Fig. 3.6 (9)
(3)
8-bit PPG (Programmable pulse generation) mode
Pulse can be generated at any frequency and duty rate by Timer I or
Timer 3. The output pulse may be either low- or high-active.
In this mode, Timers 0 and Timer 2 are not be used.
If Timer I is used, pulse is output to TOI (also used as P60), and the
use of Timer 3 results in the output to T03 (also used as P70/P83).
Following is the t1m1ng of Timer 1 (The operation is the same as when
Timer 3 is selected):
TREGO
= UCl
TREGl = UCl
TOl
TREGO
TREGl
In the 8-bit PPG mode, programmable pulse is generated by the
inversion of the timer output each time the 8-bit up-counter I (ucl)
matches the timer register TREGO or TREGI.
MPU90-85
TMP90C840
TOSHIBA
Note that the set value of TREGO must be smaller than that of TREGI.
In this mode, the up-counter UCO of Timer 0 is disabled (Set TRUN 0
0, and stop and clear Timer 0).
The PPG mode can be illustrated as follows:
¢Tl
¢T16
TFFCRl
= 1
TMOD3 , 2
=10
TCLK3, 2
f. 00
Internal Data Bus
Fig. 3.6 (10)
Example:
Block Diagram of8-bit PPG Mode
Generate pulse at 50kHz and 1/4 duty rate (@fc
8MHz)
.sL.JL---ILJ
W
t = 1/50
o
(ms)
Calculate the set values of the timer registers.
To obtain the frequency of 50kHz, the pulse cycle t should be:
1150kHz = 20lls.
Given oTl = Ills (@8MHz),
20lls/ Ills = 20
Conseq uent ly, the timer register 1 (TREGl) shou ld be set to 20
14H.
Given a 1/4 duty, t x 1/4 = 20 x 1/4 = 5 llS
5 llS / 1 llS = 5
As a result, the timer register 0 (TREGO) should be set to 5' = 05H.
MPU90-86
TOSHIBA
TMP90C840
TRUN
<--
TCLK
TMOD
TFFCR
<- <-
<-
- - - -
<- <- <-
(Note)
(4)
-
<- 0 0 0 0
<- 0 0 0 1
TREGO
TREGI
SMMOD
P67CR
TRUN
x:
Stop Timer 0 and Timer 1, and clear them
to "0".
0 1 x x
Select ~Tl as the input clock.
lOx x
Set 8-bit PPG mode.
0 0 1 1
Clear the output, and enable the inverI I
s ion by Timer 1.
Writing "01" provides negative logic pulse
0 I 0 1
Write "SH".
0 1 0 0
Write "14H".
x x 0 1
Select P60 as the TOI pin.
- - - 1
Start Timer 1.
1 0
- 0 0
1
Don't care
No change
8-bit PWM (pulse width modulation) mode
This mode is only available for Timer 1 and Timer 3, and generates two
types of 8-bit resolution PWM (PWMI and PWM3).
Pulse width modulation is output to TOI pin (also used as P60) when
us ing Timer 1, and to T03 p in (a Iso used as P70 or P83) when us ing
Timer 3.
Timer 0 and Timer 2 can be also used as 8-bit timers.
Following is the timing of Timer 1 (PWMl) (The operation is the same
as when Timer 3 is selected):
The inversion of the timer output occurs when the up-counter (UC!)
matches the set value of the timer register TREGl, as well as when an
overflow of 2n - 1 (n = 6, 7 or 8 selected by TMODI or TMODO) occurred
at the counter. The up-counter UCI is cleared by the occurrence of an
overflow of 2n - 1.
The following condition must be obtained in this PWM mode:
(Set value of timer register)
<
(set overflow value of 2
Match signal
from Comparator
2n _l
Overflow
TOI
I.
tpwM
.1
The PWM mode can be illustrated as follows:
MPU90-87
n
- 1 counter)
TMP90C840
TOSHIBA
TRUN5
TRUNl
Comparator Output
of Timer 0
,----'---..
¢Tl
¢T16
¢T256
Up-Counter UCl
Clear
TCLK3,2
TMOD3,2 = 11
TlI,OD1,0
(n
= 6,
7 or 8)
TOl
Internal Data Bus
Fig. 3.6 (11)
Example:
Block Diagram of 8-bit PWM Mode
Generate the following PWM to the T01 pin at fc=10MHz.
I..
50.4]15
...1
Assuming the PWM cycle is 50.4 ~s when ~Tl
10MHz,
6
50.4~s/0.8~s = 63 = 2 - 1
Consequently, n should be set at 6 (TMODl,O
Given the "H" level period of 36~s, setting
36us/0.8~s = 45 = 2DH
As a result, TREGI should be set at 2DH.
TRUN
TCLl<
TMOD
TFFCR
TREG1
SMMOD
P67CR
TRUN
(Note)
<-
- 0 -
<-<<<<<<-
x:
- 0 I
I 101
- - 0 0 1 1
0 0 I 0 1 101
x x 0
iJ
1
Don't care
1 -
0.8 us and @fc
= 01).
~Tl=0.8~s
results:
Stop Timer 1.
Select 0T~ as the input clock.
Set the 2 - 1 cycle in the PWM mode.
Set the initial output to 0 (ilL" level).
Write "2DH ".
Select P60 as the TOI pin.
Start Timer 1.
No change
MPU90-88
TOSHIBA
TMP90C840
Table 3.6 (3)
PWM Cycle and Selection of 2n_ 1 counter
PWM cycle (@fc
= 10MHz)
1
1
1 ¢Tl 1 ,T16 1 ¢T256 1
1--6----1---------1----------1----------1
1 2 - 1 1 50.4~s 1 806.4~s 1 l2.9ms 1
1--]----1---------1----------1----------1
1 2 - 1 1 101.6~s 1 1625.6~s 1 26.Oms 1
1-- ----1---------1----------1----------1
1 2 8- 1 1 204.0~s 1 3264.0~s 1 52.2ms 1
3.6.2
Multi-function 16-bit timer/event counter (Timer 4)
The TMP90C840 incorporates a multi-function 16-bit timer/event counter
that functions in the following operating modes:
o
o
o
o
o
o
16- bit time r
16-bit event counter
16-bit PPG mode
Frequency measurement
Pulse width measurement
Time deviation measurement
Fig. 3.6 (12) is a block diagram of the 16-bit timer/event counter.
In ternal Data Bus
'ITFl
1'14
TIS
INTl
Interrupt
IN1'2
Interrupt
Fig. 3.6 (12)
Block Diagram of l6-bit Timer/Event counter (Timer 4)
MPU90-89
TOSHIBA
TMP90C840
The timer/event counter is composed of a 16-bit up-counter, two 16-bit
timer registers, two 16-bit capture registers, two comparators, a
capture input control, a timer flip-flop and its control circuit.
The timer/event counter is controlled by four control registers
(T4MOD, T4FFCR, TRUN, and P8CR). The TRUN register also controls the
8-bit timers. For details, refer to Fig. 3.6 (5).
The P8CR register is the control register for the port P8.
7
T4MOD
(FFE4H)
6
4
5
I CAP IN I
I
I
I
I
3
CAPMM
a
1
2
CLEI
I
I
T4CLKK
I
I R/W
I- ) Timer 4 input clocks
*
1001
1011
1101
1111
Externa 1 clock (T14)
Internal clock ~Tl
Interna 1 clock ~T16
Not used
R/W
) Clear up-counter UC16
*
01 Clear disable
11 Clear if equal to TREGS
R/W
) Control capture/interrupt INTI
*
I I Capture control
1001 Cap ture disable
1011 CAP 1 at TI4 rise
I I CAP 2 at TIS rise
110 I CAP 1 at TI4 fall
I I CAP 2 at TIS fall
I
INTI
contra 1
I Interrupt occurs at
I rising edge of TI4
I input
I Interrupt occurs at
I falling edge of TI4
I I
I input
1111 CAP 1 at TFF1 risel Interrupt occurs at
I I CAP 2 at TFF1 falll falling edge of TI4
I I
I input
W
_________________ ) Trigger software capture
(Note)
*
indicates initial
value after reset.
* I
01 Capture up-counter value into CAP1
I I (Softwre capture)
I 11 Always set at "1" when read out
a R/W denotes either
reading or writing is possible.
Fig. 3.6 (13)
16-Bit Timer/Event counter (Timer 4) Control Mode registers
MPU90-90
TMP90CB40
TOSHIBA
7
S
6
4
3
2
1
T4FFCR
(FFE5H)
ICAP2TE:CAPITE:EQSTE :EQ4TE
1
o
T4FFC
1
1
W
1 ____
> Control
of Timer Flip-flop 4 (TFF4)
1 00 1 Clear TFF4 to "0"
1
1----1------------------------1
1 01 1 Se t TFF4 to "1"
1
1----1------------------------1
1 10 1 Invert TFF4 value
1
1
1 (software inversion) 1
1----1------------------------1
1 11 1 Don't care (Always set 1
1
1 at "11" when read out) 1
R/W
> Trigger
---
inversion of Timer Flipflop 4 (TFF4)
* 1
0 1 Disable trigger
1
1----1------------------------1
1
CAP2TE:
CAPITE:
EQSTE
EQ4TE :
Fig. 3.6 (14)
1
2
When
When
When
When
liEnable trigger
capturing up-counter value
capturing up-counter value
equalizing up-counter with
equalizing up-counter with
1
into CAP2
into CAPl
TREG5
TREG4
l6-bit Timer/Event Counter Timer Flip-Flop 4 Control Registers
Up-counter (UC16)
UC16 is a l6-bit binary counter that counts up by the input clock
specified by the register T4MOD (T4CLK) (bits 1 ans 0).
Its input clock is selected from the internal clocks ¢II and I1JT16
generated by the 9-bit prescaler (also used as the B-bit timer), or
the external clock from the T14 pin (also used as PBl/ INTI) .
By
resetting, the bits 0 and 1 of T4MOD are initialized to "00", whereby
T14 is selected as the input clock to this up-counter.
The Timer Control Register TRUN 4 (T4RUN) controls the counter to
start, stop or clear.
Clearing the up-counter UC 16 is controlled by the bi t 2 of T4MOD2
register (CLE). The up-counter UC16 is cleared to "0" when matching
the timer register TREG5.
Timer registers (TREG4 and TREGS)
Two 16-bit registers are provided to set the counter value. When the
values in these timer registers equal with the value of the up-counter
UC16, the match signal of the comparator becomes active.
MPU90-91
TOSHIBA
TMP90C840
Data for the timer registers TREG4 and TREGS are provided by a 2-byte
data load instruction or two I-byte data load instructions, from the
lower eight bits followed by the upper eight bits.
TREGS
TREG4
Upper a bits
Lower 8 bits
FFEIH
3
FFEOH
Upper a bits
FFE3H
FFE2H
Capture registers (CAPl and CAP2)
CAPI and CAP2 are 16-bit registers that hold the values of the
up-counter UCI6.
Data in the capture registers are read by a 2-byte data load
instruction or two I-byte data load instructions, from the lower eight
bits followed by the upper eight bits.
CAP 1
Upper a bits
FFDDH
4
Lower a bits
CAP2
Lower a bits
FFDCH
Upper a bits
FFDFH
Lower a bits
FFDEH
Capture input control circuit
This circuit controls the timing that the capture registers (CAPI and
CAP2) latch the UC16 up-counter value.
The latch timing is set by the register T4MOD4,3 (CAPM).
o
o
o
o
If T4MOD4,3 = 00,
The capture function is disabled.
Theese bits are initialized to
this mode by resetting.
If T4MOD4,3 = 01,
The up-counter value is latched into CAPI at the rising edge of the
TI4 (also used as pal/INTI) input, and into CAP2 at the rising edge
of TIS (also used as P82/INT2) input.
If T4MOD4,3 = 10,
The up-counter value is latched into CAPI at the rising edge of the
TI4 input, and by CAP2 at its falling edge. Only in this mode, the
interrupt INTI occurs at the falling edge.
If T4MOD4,3 = 11,
The up-counter value is latched into CAPI at the r1s1ng edge of the
timer flip-flop TFFl, and into CAP2 at its falling edge.
The up-counter value can be also latched into the capture registers by
using software. In this case, the current up-counter value is latched
into CAPI each time "a" is written into the T4MODS (CAPIN) register.
MPU90-92
T~P90C840
TOSHIBA
Comparators (CP4 and CPS)
The 16-bit comparators detect the match of the up-counter UC16 and the
timer register TREG4 or TREG5.
When the up-counter matches registers TREG4 or GREGS, the interrupt
INTT4 or INTT5 occurs, respectively.
The up-counter is cleared only
when it matches TREGS (the clear operation can be disabled if
neces sary) .
®
Timer Flip-flop (TFF4)
This Timer Flip-flop is inverted by the match signal from the
comparators (CP4 and CPS) and the latch signal to the capture
registers (CAPI and CAP2).
It is pos sib Ie to enab lei di sab Ie the invers ion for each of these
sources by using TRFFCR5-2.
Also TFF4 can be inverted, cleared to "0" and set to "1" under
software control.
Its value can be output to the timer output pin T04 also used as P83
or T03. Either pin function may be selected by the registers P8CR and
SMMOD. T04 is selected by setting P8CR3 = 1 and SMMODS,4 = 11.
(1)
16-bit timer mode
In this mode, the interval time is set in the timer register TREG5 to
generate the interrupt INTT5.
TRLJN <- a
INTEL <- - - a - 1
T4FFCR<- x x a a 0 0 1 I
T4MOD <- x x 1 0 0 1 * *
(**=01,10,11)
TREG5 <- **** **** **** ****
TRLJN <- 1 1
- -
-
(Note)
(2)
x:
--
Don't care
Stop Timer 4.
Enable INTT5 and disable INTT4.
Disable trigger.
Se 1ec t interna 1 clock for input, and
disable the capture function.
Set the interval time (16 bits).
Start Timer 4.
No change
16-bit event counter mode
This timer can be used as a 16-bit event counter by selecting the
external clock (TI4) as the input clock in the above timer mode (1).
The counter counts up at the rising edge of the TI4 input clock.
The TI4 pin is also used as P81 or INTI.
TRLJN
P8CR
<- - - - 0
<- - - - - - - * -
INTEL <- - - 0 0 1
T4FFCR
,-->
Keep counting (Free-running)
Count with oTl.
, I-I
-T4MOD <- x x I 0 I 00 1
, ,
T___________> Load
T4FFCR<- x x
aaaa
,
,
0
th~
a
'" T___ >
Clear TFF4 to "0".
> Disable
TFF4 inversion.
::0 :~ !*:~o~ ,:~,~~)}
,
INTEL Enable
TFF4 inversion when the up-counter
value matches TREG4 or 5.
Enable INTTS.
------
<- - - - -
INTEL
1 -
Setting of INTS
-T4FFCR<-
x x -
-
0 0
I I
T______ > Disable
INTEL
<- -
(Note)
x'
TFF4 inversion when the upcounter value matches TREG4 or 5.
Dis a b I e INTT 5 •
0 Don't care
No change
When no delay time is required, invert the TFF4 when the up-counter
value is loaded into CAPl, and set the CAPI value (c) plus the
one-shot pulse width (p) to TREGs when the interrupt INTI occurs. The
TFF4 inversion should be enabled when the up-counter (UC16) value
matches TREGs, and disabled when generating the interrupt INTTs.
Count Clock
(Internal Clock)
.JlJ11l.fUUL ___ JlJlJllL ___ ___ JlJlJ1Jl.fL
c+p
C
Input of TI4
(External
Tr igger Pulse)
Loading the up-counter
value into
INTi
./' INTTS
:\
: Loading the up-counter
I value into Capture
: Register 2 (CAP2)
-------------------~-------
Match with TREGS
Inversion
Enable
Timer output T04
Inversion Enable /
:.....~______~
(p)
Inversion Disable
Pulse width
Fig. 3.6 (17)
One-Shot Pulse Output (with no delay)
MPU90-96
TOSHIBA
@
TMP90C840
Freq uency measurement
The frequency of the external clock can be measured in this mode. The
clock is input through the TI4 pin, and its frequency is calculated by
using the 8-bit timers (Timer 0 and Timer 1) and the 16-bit
timer/event counter (Timer 4);
The frequency of the external clock ~s calculated by using the
frequency of the input clock to Timer 4 (TI4).
The value of the
up-counter is loaded into the capture register CAP1 at the rising edge
of the Timer Flip-flop TFF1 of 8-bit timers (Timer 0 and Timer 1), and
into CAP2 at its falling edge.
The frequency is calculated by using the number of input clock in a
certain period (the difference between the loaded values in CAPI and
CAP2 when the interrupt (INTTO or INTTl) is generated by either 8-bit
timer.
Count Clock
(Input of TI4)
-1lI11lJlJ1Jl__ _ ___ JUlJ1JL __ _
CI
C2
TFFI
Loading UCl6 into
CI
CI
CAPI--~~ ~--------------~--------------~~--------------~----Loading UCl6 into
CAP2--~~~--------------~
C2
INTTO/INTTI
Fig. 3.6 (18)
CD
Frequency Measurement
Pulse width measuremnt
This mode allows to measure the "H" level width of an external pulse.
While keeping the 16-bit timer/event counter counting (free-running)
with the internal clock input, the external pulse is input through the
TI4 pin.
Then the capture function is used to load the UC16 values
into CAPl and CAP2 at the rising edge and falling edge of the external
trigger pulse respec t ive ly.
The interrupt INTI occ urs at the fa 11 ing
edge of TI4.
The pulse width is obtained from the difference between the values of
CAPI and CAP2 and the internal clock cycle.
Count Clock
(Internal Clock)
JUlJUlll __
CI
--~-C2
TI4
(External Pulse)
Loading UCl6 into
CAP I
CI
CI
Loading UCl6 into
CAP2
c2
INTI
Fig. 3.6 (19)
Pulse Width Measurement
MPU90-97
TOSHIBA
TMP90C840
(Note)
The external interrupt INTI occurs at the falling edge of TI4 only
in this pulse width measurement mode (T4MOD4,3 = 10).
In any
other mode, the interrupt occurs at its rising edge.
The width of "L" level can be obtained from the difference between the
first C2 and the second CI when the second INTI interrupt is
generated.
QD
Time Qifference measurement
This mode is used to measure the difference in time between the rising
edges of external pulses input through TI4 and TIS.
Keep the I6-bit timer/event counter (Timer 4) counting (free-running)
with the internal clock, and load the UC16 value into CAP 1 at the
rising edge of the input pulse to TI4.
Then the interrupt INTI is
generated.
Similarly, the UC16 value is loaded into CAP2 at the rising edge of
the input pulse to TIS, generating the interrupt INT2.
The time difference between these pulses can be obtained from the
difference between the time loading the up-counter value into CAPI and
CAP2.
Count Clock
(Internal Clock)
JUlJlJlJL -Cl
-_JlllJlJllL __ _
(;2
Input TI4
Input TIS
Loading UC16 into
CAP 1
Loading UC16 into
CAP 2
INTl
INT2
Time Difference
Fig. 3.6 (20)
3.7
.'
Time Difference measurement
Stepping Motor control ports (P6 and
pn
The TMP90C840 has two 4-bit hardware stepping motor control ports (SMC
ports MO and Ml) that synchronize with the (8-bit/16-bit) timers. These
SMC ports MO and MI are also used as the I/O ports P6 and P7.
The channel 0 (MO) synchronizes with the trigger signal of the Timer
Flip-flop TFFI, and the channel I (Ml) is synchronous with that of the
Timer Flip-flop TFF3 or TFF4, for output.
MPU90-98
TOSHIBA
TMP90C840
The SMC ports are controlled by three control registers (P67CR, SMMOD,
and SMCR) , and allow the selection of driving method: 1) 4-phase
I-step/2-step excitation and 2) 4-phase 1-2 step excitation.
3.7.1
Control registers
(1)
Port 6 and Port 7 I/O selection register (P67CR)
This register specifies either input or output for each bit of the
4-bit I/O ports 6 and 7.
When all bits of P67CR are initialized to "0" by resetting, Ports 6
and 7 function as input ports.
P67CR is a write-only register (not for readout).
(2)
Stepping motor control port mode register (SMMOD)
Ports 6 and 7 also function as SMC Ports (MO and Ml) or Timer Output
Ports (TOI and T03), as selected by SMMODl, 0 or SMMODS, 4.
When Port 6 is used as SMC Port (MO), SMMODl, 0 should be set to 10 or
II.
When Port 7 is used as SMC Port (Ml), SMMODS, 4 should be set to 10 to
make it synchronize with the trigger pulse of the timer flip-flop TFF3
and set at 11 to make it synchronize with the trigger pulse of the
Timer Flip-flop TFF4. P83 (also used as T03 and T04) can function as
T03 only when SMMODS, 4 are set at 11.
SMMOD2 and SMMOD6 serve to select the excitation method. With "0" the
full-step Cl-step/2-step) excitation is selected and with "1" tht~
half-step (1-2 step) excitation is selected.
When
full-step
excitation is selected, the selection of either 1 or 2-step excitation
is determined by the initial output value.
SMMOD3 and SMMOD7 allow to set the number of phases.
(3)
Stepping motor control port rotating direction control register (SMCR)
This register controls the rotating direction.
The direction of the
channel 0 (MO) is set by SMCRO (CCW6) and that of the channel 1 (M1)
is set by SMCR4 (CCW7).
"a" denotes normal rotation and "I" denotes reverse rotation.
(4)
Port 6
This is a 4-bit I/O port allocated to the address FFCCH.
The lower four bits are assigned as Port 6, while the upper four bits
function as the shifter alternate register (SA6) for driving the
stepping motor with the half-step (1 - 2) excitation.
(5)
Port 7
This is a 4-bit I/O port allocated to the address FFCDH.
The lower four bits are assigned as Port 7, while the upper four bits
function as the shifter alternate register (SA7) for driving the
stepping motor with the half-step (1 - 2) excitation.
MPU90-99
TOSHIBA
TMP90C840
P7
1
7
6
P6
5
413
2
1
o
1
1
1
P67CR Ip73C:P72C:P71C:P70clp63C:P62C:P61C:P60cl
(FFCEH) 1
1
1
1
1
1
1
1
1_ _ _
W
1
>
*
1
1
1
Select Port 6 I/O
(On bit basis)
1 0 1 Input
1
1---1--------------------1
1 1 1 Output
1
1
w
1
1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
*
(Note)
*:
w:
Select Port 7 I/O
(On bit basis)
1 0 1 Input
1
1---1--------------------1
1 1 1 Output
1
initial value after reset.
write only.
Fig. 3.7 (1)
Ports 6 and 7 I/O Selection Registers
MPU90-100
TMP90C840
TOSHIBA
P7
7
6
P6
4
5
2
3
o
1
/
SMMOD /
(FFCBH) /
SM7M
SM6M
P70C
P60C
--------~------~~----~---R-/~W---
Select Port 6 function (On bit basis)
*
00
01
10
11
/ P63 / P62 / P61
P60
SMC
/
/Trigger signal/
/
/
/
/
/IN/OUT/IN/OUT/IN/OUT/IN/OUT/
/
/ IN/OUT / IN/OUT / IN/OUT / IN/TOI/
/
/ IN/M03/ IN/M02i IN/MOI/IN/MOO/TFFI (Timer 0 /
/
/
/
/
/ or Timer 1)
/
IN
Input port
Out
Output port
TOI
Timer output port
MOO-3: Stepping motor control port 0
R/W
_____ >
* I
Stepping motor control port 0 mode
(excitation)
0 / 1 or 2 excitation (Full-step)
/
.1 / 1-2 Excitation (Half-step)
/
/----/------------------------------------------/
/
R/W
--------->
* /
Stepping motor control port 0 mode
(Phase)
0 /
1
1 / 4-phase
/
1----/------------------------------------------/
1
Fig. 3.7 (2a)
Stepping Motor Control Port Mode Registers
MPU90-101
TMP90C840
TOSHIBA
P7
7
6
P6
5
4
2
3
o
1
I
SMMOD I
(FFCBH)I
SM7M
SM6M
P70C
P60C
R/W
I
1___ > Select Port 6 function (On bit basis)
*
SMC
P73 I P72 I P71 I P70 I P83
I
I Trigger signa 11
I
I
I
I
I
I
I
I
I 00 I IN/OUT I IN/OUT I IN/OUT I IN/OUT I
I
I 01 I IN/OUT I IN/OUT I IN/OUT I IN/T0310UT/T041
TFF3
I
I
I
I
I
I
I
I
I (Timer 2 and I
I 10 I IN / M13 I IN / M12 I IN / Mll I IN / Ml 0 I
I Timer 3
I
I
I
I
I
I
I
TFF4
IOUT/T031
I
I
I
I 11 I
I
I (Timer 4)
I
I
I
I
I
I
I
IN
Input port
OUT
Output port
T03,T04
Timer output port
MI0-3: Stepping motor control port 1
R/W
________>
*
I
Stepping motor control port 1 mode
(excitation)
0 I 1 or 2 excitation (Full-step)
I
I----I--------------------------~---------------I
I
1 I 1 - 2 excitation (Half-step)
I
R/W
__________ >
* I
0
Stepping motor control port 1 mode
(Phase)
I
I
I--~-I------------------------------------------I
I
Fig. 3.7 (2b)
1 I 4-phase
Stepping Motor Control Port Mode Registers
MPU90-102
I
TOSHIBA
TMP90C840
7
P7(Ml)
654
P6(MO)
2
3
1
o
1
1
1
1
1
SMCR 1
- 1CCW7 1
- 1CCW6 1
(FFCFH) 1_ _ _ _ _...:.1--,-----:..1_ _ _ _ _..;..1_ _ 1
1
R/W
1
Stepping motor control port 0 rotating
direction
1
1
1
*
1
1
1
1 0 1 Normal rotation
1
1---1--------------------------------------1
1 1 1 Reverse rotation
1
1
1
R/W
1_> Stepping motor control port 1 rotating
direction
*
Fig. 3.7 (3)
7
1 0 1 Normal rotation
1
1---1--------------------------------------1
1 1 1 Reverse rotation
1
Stepping Motor Control Port Rotating Direction Control Registers
6
5
4
3
2
1
o
1
1
1
1
1
P6
ISA63:SA62:SA61IsA601 P63: P62: P611 P601
( F FC CH ) 1
1
1
1
1
_R;;.,;;/:..,.W_ _> Port 6
W
--------------->
7
6
5
4
3
2
Shifter alternate register 0 for
stepping motor control
1
o
1
1
1
1
I
P7
ISA73:SA72:SA71IsA701 P73: P72: P711 P701
(FFCDH)1
1
1
1
1
R/W
------>
W
---------------->
Fig. 3.7 (4)
Port 7
Shifter alternate register 1 for
stepping motor control
Ports 6 and 7
MPU90-103
TOSHIBA
3.7.2
TMP90C840
4-phase I-step/2-step excitation
Figs. 3.7 (5) and (6) show the output waveforms of 4-phase I-step
excitation and 2-step excitation when Channel 0 is selected.
Sets circle by using TIMER-O or TIMER-l
n n n n n
Trigger of·TFFl ~
MOO (P60)
I
"---~
I
,IbO
b3
,
Ib2
Ibl
b3
lbl
bO
Ib2
~i
----------------~
I
MOl (P61)
~bl
M02(P62)
,,
Ibl
t
Initial Value
P6 + xxxx0100
(2)
Trigger of TFFl
I
bO
b3
(Note) "bn" is Internal Value
p6 + xxxxb3b2blbO .
Normal rotation
n n n n
,~
bl
Ib2
Ib3
bO
MOl (P6l)
l£L.Jb2
Ib3
bO
bl
M02(P62)
,ib2lb3
bO
bl
Ib2
bl
I b2
Ib3
MOO (P60)
IbO
I
I
,
I
M03 (P63)
'b3
I
r-
I bl
bO
b3
b2
~----------------~
~02
M03 (P63)
bO
LL
bO
t
n
LL
I
Initial Value p6 + xxxx0100
@
Fig. 3.7 (5)
Reverse rotation
Output Waveforms of 4-phase I-step Excitation
(Normal Rotation and Reverse Rotation)
MPU90-104
TMP90C840
TOSHIBA
Trigger of TFFI
n
~
I
MOO (P60)
~b3
MOl (P61)
I
Ibl
I
M02(P62)
n n n rL
n
b2
\bl
bO
bO
I b3
b2
Ibl
~bl
I
bO
Ib3
b2
b2
Ibl
bO
Ib3
L
I
I
M03 (P63)
;b3
t
Initial Value p6 -+- xxxxllOO
Fig. 3.7 (6)
Output Waveforms of 4-phase I-step Excitation
(Normal Rotation)
When Channel a is selected, for example, the stepping motor control
port is controlled as follows:
The output latch of MO (also used as P6) rotates at the rising edge of
the TFFl trigger pulse (that inverts the value of TFF!) and is out put
to the port.
The rotating direction is selected by SMCRO (CCW6). Setting SMCRO to
"0" selects the normal rotation (MOO -) Mal -) MOZ -) M03) , and
setting it to "1" results in the reverse rotation (MOO <- Mal <- MOZ
<- M03).
The 4-phase I-step excitation can be obtained by
initializing anyone bit of Port 6 to "1", and setting two succeeding
bits to "1" produces the 4-phase Z-step excitation.
Fig. 3.7 (7) is a block diagram of the two excitations.
Sifter Alternate
Register
Output Latch
M03(P63)
H
:l
.,b~----------------~~
M02(P62)
!:Jr-----------------~~
~
~--~--~
MOL (P61)
!:J
'""'1----.1
!C....:J
:l
U:I--_~
MOO (P60)
Jl is showing to shift
the signal at the
Rising-Edge of TFFl-tigger pulse
Fig. 3.7 (7)
Block Diagram of 4-phase l-step/Z-step Excitation
(Normal Rotation)
MPU90-10S
TOSHIBA
3.7.3
TMP90C840
4-phase 1-2 step excitation
Figs. 3.7 (8) shows the output waveforms
excitation when Channel 0 is selected.
n
Trigger of TFF1--II
I
MOO (P60)
b4
:bO
I
I
Ibl
MOl (P6l)
b5
I
M02 (P62)
M03 (P63)
/b2lb6
I
I
Ib3
b7
+
n
MOO (P60)
MOl (P6l)
M02 (P62)
M03 (P63)
I
I
IbO
I
n n n
1-2
L
b7
b2
Ib6
bl
bO
b4
Ib3
b7
b2
bl
b5
bO
b4
Ib3
b7
b2
Ib6
bl
b5
bO
b4
b5
l£L
(Note) The Ibn' is initial value.
p6 +- b7b6b5b4b3b2blbO.
(1)
J
4-phase
Ib3
Initial Value
P6 +- 10001100
Trigger of TFFl
of
Normal rotation
n n n n n
L
b5
bl
b6
fb2
b7
b3
l£L
b6
Ib2
b7
b3
Ib4
bO
b5
b7
b3
Ib4
bO
b5
bl
b6
twrb4
bO
b5
bl
Ib2
b7
I
I
Ibl
I
I
i
Ib2
I
t
Initial Value P6
+-
b6
10001100
~ Reverse rotation
Fig. 3.7 (8)
Output Waveforms of 4-phase 1-2 step Excitation
(Normal Rotation and Reverse Rotation)
MPU90-106
step
TOSHIBA
TMP90C840
The 4-phase 1-2 step excitation is obtained as follows:
Given the Port bits I b7 b6 b5 b4 b3 b2 bl
bO I initialially
arranged as I b3 b7 b2 b6 bl b5 bO b2 I, set three succeeding
bits to "1", and the other bits to "0" (Positive logic).
For example, initializing b3, b7 and b2 to "1" provides the initial
value "10001100", which produces the waveforms in Fig. 3.7 (8).
To obtain the negative logic output, the above initial value of Port 6
should be inverted.
That is, the waveforms in Fig. 3.7 (8) can be converted to the
negative logic output by initializing the P6 bits to "011110011".
When Channel 0 is selected, for example, the stepping morot control
port is controlled as follows:
The output latch of MO (also used as P6) and the stepping motor
control shifter alternate register (SA6) rotate at the rising edge of
the TFF 1 trigger pu lse and are output to the port.
The rot at ing
direction is selected by SMCRO (CCW6).
Fig. 3.7 (9) is a block diagram of this excitation.
output
Latch
Sifter Alternate
Register
b3
M03 (P63)
Jl..
SL
H
b2
M02(P62)
::l
rt
(i)
Ii
::l
III
SL
I-'
11
0
III
rt
III
bl
MOl (P61)
to
C
en
.fL
SL
bO
MOO(P60)
Jl
Fig. 3.7 (9)
Block Diagram of
(Normal Rotation)
4~phase
MPU90-107
1-2 step Excitation
TMP90C840
TOSHIBA
Example:
The registers should be set as follows to drive Channel 0
(MO) with the 4-phase 1-2 step excitation (normal rotation)
when Timer 0 is selected:
7 6 5 4 3 2 1 0
- 0
0 0 x x
- - 0 1
TRUN
TMOD
TCLK
TREGO
TFFCR
<<- <- <- * * *
<-
SMMOD
SMCR
P67CR
P6
TRUN
<- <<- <- 1 o
<- - -
(Note)
x:
-
--
* * * **
- 0 0
1 0
1 1 1 x
- - 0
- 1 1 1 1
0 0 1 1 0 0
1 - - - - 1
Don't care
Stop Timer 0, and clear it to "0".
Set the 8-bit timer mode.
Select ~T1 as the input clock.
Set the cycle in Timer register.
Clear TFFI to "0", and enable inversion
trigger- by Timer 0
Select 4-phase 1-2 step excitation mode.
Select normal rotation.
Set all P6 bits to the output mode.
Initialize the P6 bits.
Start Timer O.
No change
MPU90-108
TOSHIBA
3.8
TMP90C840
Serial Channel
The TMP90C840
incorporates a serial I/O channel
asynchronous transmission (UART) and I/O expansion.
The serial channel has the following operating modes:
for
full-duplex
o
I/O interface mode --- Mode 0:
Transmit/receive I/O data for
expand I/O and transmit its
synchronous signals (SCLK)
o
Asynchronous transmission (UART)
/
/
Mode 1
---------/-- Mode 2
/
Mode 3
mode
7-bit data
8-bit data
9-bit data
The Mode 1 and Mode 2 allow the addition of a parity bit.
The Mode 3
accommodates a wake-up function to start the slave controllers in a
controller serial link (multi-controller system).
Fig. 3.8 (1) shows the data format (I-frame data) in each mode.
· Mode 0 (I/O Interface Model
~
Transfer direction
• Mode 1
• Mode 2 (8-bit UART Mode)
• Mode
(Wake up)
\
I
When Bit 8
When Bit 8
= Address
=0
Fig. 3.8 (1)
(select code) is denoted.
Data.is denoted.
Data Formats
MPU90-109
TOSHIBA
TMP90C840
Data received and transmitted are stored temporarily into separate
buffer registers
to allow independent
tr an smis s ion and receiving
(Full-duplex).
In the I/O interface mode, however, the data transfer is half-duplex due
to the single SCLK (serial clock) pin is used for transmisison and
receiving.
Two pins are provided for receiving (RxD, also used as P30 and P3l) and
transmission (TxD, also used as P32 and P33), which allows two serial
transmi~ison/receiving
using the time-sharing technique.
The pin
function is selected by the P3CR registers.
For example, P30 can be
used as the RxD pin by setting P3CR1, 0 to 01.
The receiving buffer register has a double-buffer structure to prevent
overruns.
The one buffer receives the next frame data while the other
buffer store~he receive data is read by the CPU.
The use of CTS and RTS allows to halt the data transmission until the
CPU completes reading of the receive data for each frame (Hand-shake
function) .
In the UART mode, a check func t ion is added not to s tart the receiving
operation by error start bits due to noise.
The channel starts
receiving data only when the start bit is detected to be normal at least
twice in three samplings.
~nen an
request is issued to the CPU to transmit data after the
transmitting buffer becomes empty or to read data after the receiving
buffer completed to store data, the interrupt INTTX or INTRX occurs
respectively.
In receiving data, the occurrence of an overrun error,
parity error or framing error sets the flag (SCCR4, 3 or 2) accordingly.
MPU90-110
TOSHIBA
3.B.l
TMP90CB40
Control Registers
The ser ia 1 channe 1 is controlled by four contro 1 regis ters (SCMOD
SCCR, TRUN, and P3CR). The received/transmitted data are stored into
SCBUF.
l
SCMOD
7
6
5
TBB
a
RXE
3
4
2
WU
SM
a
1
SC
(FFE9H)
I R/W
I-> Serial transfer clock
*
I
I
UART mode
I I/O interface
1001 Timer 2 match
I
I I signa 1
I
1--1----------------------1
1011 Baud rate genetator I
fc/8
1--1----------------------1
1101 Internal clock 01
I
1--1----------------------1
1111 Bauda rate generator I
I I 1/2 clock
I
R/W
*
>
Serial transfer mode
I/O interface mode
1001
I
1011
I
I 7- bit data
1---------------1
1--1
1101 UART mode
I
I B-bit data
1---------------1
1--1
1111
I
I 9- bit data
R/W
>
Wake-up function
I
I
9-bit UART
Other modes
01 Interrupt if data
I
I I are received.
I
1--1----------------------1 don't care
I 11 Interrupt only if
I
* I
I
I
RBB = 1.
I
R/W
>
* I
Enable receiving data
Disable
Enable
01
I 11
R/W
>
Fig. 3.B (2)
Transmission data bit B
Serial Channel Mode Register
MPU90-111
TMP90CB40
TOSHIBA
7
S
6
3
4
o
I
2
I
I
I
I
I
I
I
I
seCR
IRBB I EVEN I PE IOERRlpERRIFERRI
(FFEAH) I
I
I
I
I
I
1/
I CTSE I
I
I
I R/W
I
I
I
I
I
I
I
I
1_ _
*
> Enable
hand-shake function
I 0 I Disable (always transmitt-I
I
I able)
I
1---1---------------------------1
I I I Enable
I R
1_ _
>
I
Framing error flag
R
R
Parity error flag
----->
Always
cleared to
"0" when
read out
Overrun error flag
------->
R/W
_______________________> Enable
*
parity addition
I 0 I Disable
I
I I I Enable
I
1---1---------------------------1
R/W
______________________________ > Add/check
*
even parity
I 0 I Odd parity
I
I I I Even parity
I
1---1---------------------------1
R
______________________________> Rec ei ving
(Caution)
Since all error flags are cleared after readout, avoid testing
for only one bit by using a bit-testing instruction.
Fig. 3.B (3)
7
6
S
4
Serial Channel Control Register
3
2
I
0
I
I
ITB7:TB6:TBS:TB4:TB3:TB2:TBI:TBOI
SCBUF
(FFEBH)
da t a bi t B (S RB )
I
(Transmisison)
I
7
6
S
4
3
2
I
0
I
I
I RB 7: RB6: RBS: RB4: RB3: RB2: RBI: RBO I
I
Fig. 3.B (4)
(Rece iving)
I
Serial Transmission/Receiving Buffer Registers
MPU90-II2
TOSHIBA
TMP90C840
7
TRUN
(FFDBH)
5
6
BRATE
4
3
o
1
2
I
I
I
I
I
I
I
I PRRUNI T4RUN/T3RUNIT2RUNITIRUNITORUNI
I
I
/
I
I
/
/
R/W
_ _ _ _ ) Timer 2 funct ion
* I 0 / St op & clear
1
1---1-------------------------1
I 1 I
Count
/
R/W
_ _ _ _ _ _ _ _ _ _ _ ) Prescaler function
*
I
0
I
1
1
Stop
&
clear
1
/---/-------------------------1
I
Count
/
R/W
---------------------)
Select transfer speed of serial
I/O baud rate generator
I
I
SCMODl,O=Ol
1
SCMODl,O=ll
I
1---1-----------/-------------/
* I 00/ 300 baud / 150 baud /
1---/-----------/-------------/
I all 1200 baud I
600 baud
/
1---1-----------1-------------/
~aud
/
1---1-----------/-------------1
I 11119200 baud / 9600 baud /
/ la/ 4800 baud / 2400
@fc = 9.8304MHz
(Note)
Also refer to Fig. 3.6 (5)
Fig. 3.8.(5)
Timer/Serial Channel Operation Control Register
MPU90-113
TOSHIBA
TMP90C840
7
P3CR
(FFC7H)
6
WAITC
5
4
RDE
ODE
2
3
TXDC
a
1
RXDC
I
I
I R/W
1__ > Select P30 and P31 functions
*
I
I
P31
I
P30
I
1---1--------------1--------------1
I
001 Input port
I
Input port
I
1---1--------------1--------------1
I
all Input port
I
RxD pin
I
1---1--------------1--------------1
I
101 RxD pin
I
Input port
I
1---1-------------- --------------1
I
11 I No t us e d
I
R/W
_ _ _ ) Select P32 and P33 functions
*
I
I
P33
I
P32
I
1---1--------------1--------------1
I
001 Output port I Output port I
1---1--------------1--------------1
I
all Output port I RxD pin
I
1---1--------------1--------------1
I
101 RxD pin
I
Output port I
1---1--------------1--------------1
1 111 TxD pin
I RTS/SCLK pin I
R/W
___ > Select
*
Fig. 3.8.(6)
P33 CMOS/Open-drain output
1 a I CMOS output
I
1---1----------------------------1
I 1 I Open-drain output
1
Port 3 Control Register
MPU90-114
TOSHIBA
3.8.2
TMP90C840
Architecture
Fig. 3.8 (7) is a block diagram of the serial channel.
r--
Se~ial
Clock Circuit--------------------j
I
I
I
TRUN7. 6 T02TRG (Timer2 Comparator Output) I
I
-
:
I
I
I ¢T4
¢T16
:
¢T64
:
'SIOCLK
I
I
I
I
I
I
01
:
I
I
I
I
I
~
I/O Interface
:
_____________________ l2.0~~ _____________ J
r ' P - - - - - G CTS
(P34)
RTS/O~----------~
SCLK
~~----~
(P32)
TxD
(P32)
TxD
(P33)
Internal Data Bus
Fig. 3.8 (7)
Block Diagram of Serial Channel
MPU90-115
TOSHIBA
Q)
TMP90C840
Baud-rate generator
The baud-rate generator comprises a circuit that generates a clock
pulse to determine the transfer speed for transmission/receiving in
the asynchronous communication (UART) mode.
The input clock to the baud-rate generator ~T4, ~T16, ~T64 or ~T256 is
generated by the 9-bit prescaler.
One of these input clocks is
selected by the timer/serial channel control register TRUN7, 6
(BRATE).
Also,. either no frequency division or 1/2 division can be selected by
the serial channel mode register SCMOD1, 0 (SC1, 0).
Tab Ie 3.8 (1) shows the baud-rate wh'en fc = 9.8304 MHz.
Table 3.8 (1)
Baud Rate Selection
1 BRATE 1 Input clock 1 No division(SC1,0=0l) 1 1/2 division(SCl,O=ll) 1
1---------1-------------1-----------------------1------------------------1
1 00 1
¢T256
1
300
bps
1
150 bps
1
1---------1-------------1-----------------------1------------------------1
1 01 1
¢T64
1
1200
bps
1
600 bps
1
1---------1-------------1"-----------------------1------------------------1
1 10 1
¢T16
1
4800
bps
\
2400 bps
1
\---------\-------------\-----------------------\------------------------1
\
11
\
¢T4
\
19200
bps
\
9600 bps
\
@fc = 9.8304 MHz
GO
Serial clock generating circuit
This circuit generates the basic clock for transmitting and receiving
data.
1) In case of I/O interface mode
It generates a clock at a 1/8 frequency of the system clock (fc).
This clock is output from the SCLK pin (also used as P32/RTS).
2) In case of asynchronous commumication (UART) mode
A basic clock is generated based on the above baud rate generator
clock, the internal clock 01, or the match signal from Timer 2, as
selected by bits 1 and 0 of SCMOD register (SC).
CD
Receiving counter
The receiving counter is a 4-bit binary counter used in the
asynchronous communication (UART) mode and is counted by using SIOCLK.
16 pulses of SIOCLK is used for receiving 1 bit data.
The data are
sampled three times at 7th, 8th and 9th pulses and evaluated by the
rule of majority.
For example, if data sampled at the 7th, 8th and
9th clock are "1", "0" and "1", the recieved data is evaluated as "1".
The sampled data "0", "0" and "1" is evaluated that the received data
is "0".
~
1)
Receiving control
In case of I/O interface mode
The RxD signa 1 is sampled on the rising edge of the shi ft
which is output to the SCLK pin.
MPU90-116
clock
TOSHIBA
TMP90CB40
2)
In case of asynchronous communication (UART) mode
The receiving control features a circuit for detecting the start bit
by the rule of majority. When two or more "0" are detected during 3
samples, it is recognized as normal start bit and the receiving
operation is started.
Data being received are also evaluated by the rule of majority.
CD
Receiving buffer
The receiving buffer has a double-buffer structure to prevent
overruns. Received data are stored into the Receiving buffer 1 (shift
register type) for each 1 bit.
When 7 or B bits data are stored in
the Receiving bufter 1, the stored data 1.S transferred to the
Receiving buffer 2 (SCBUF), and the interrupt INTRX occurs at the same
time. The CPU reads out the Receiving buffer 2 (SCBUF). Data may be
stored into the Receiving buffer 1 before the CPU reads out the
Receiving buffer 2 (SCBUF).
Note, however, that an overrun occurs
unle ss the CPU reads out the Rece iving buf fer 2 (SCBUF) be fore the
Receiving buffer 1 receives all bits of th~ next data.
When an
overrun occurred, the data in the buffer 2 and RBB are not lost,
however, that in the buffer 1 are lost.
SeCR7 (RBB) stores the parity bit in the case adding parity in the
B-bit UART mode and the MSB in the 9-bit UART mode.
In the 9-bit UART mode, setting SCMOD4 CWU) to "1" enables the wake-up
function of the slave controllers, and the interrupt INTRX occurs only
if RBB=1.
@
Transmission counter
This is a 4-bit binary counter used in the asynchronous communication
(UART) mode. Like the receiving counter, it counts based on SIOCLK to
generate a transmission clock TXDCLK for every 16 counts.
SIOCLK
15 16 'II
TXDCLK
CD
lJ
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 :1:
2
ill
Transmission control
I/O interface mode
Data in the transmission buffer are output to the TxD pin for each
bit at the rising edge of the shift clock output from the SCLK pin.
2) Asynchronous communication (UART) mode
When the CPU have written data into the transmission buffer,
transmission is started with the next rising edge of TxDCLK, and a
transmission shift clock TxDSFT is generated.
1)
Hand-shake function
The TMP90CB40 supports a hand-shake function,
by which the
connection of crs of one TMP90CB40 and RTS of the other TMP90CB40
allows receiving/transmitting data on a frame basis to prevent
overrun errors. This function is enabled or disabled by the control
register SCCRO (CTSE).
MPU90-117
TMP90C840
TOSHIBA
When the last bit (parity bit or MSB) of l-frame data is received by
the receiving unit, the RTS pin turns to the "H" level to request
the transmission unit to halt transmission.
When the CTS pin turned to the "H" level, the transmission unit
halts transmission, after completing the current data transmission,
until the pin turns to the "L" level.
At this time, the interrupt
INTTX is generated, to request the CPU to transfer data.
Then the
data is written into the transmission buffer, and the CPU is placed
in ~he standby mode.
When the received data are read by the receiving unit, the RTS pin
returns to the "L" leve 1 , req ue sting that the transmis s ion is
restarted.
TMP90C840
TMP90C840
\.J
\.J
TxD
RxD
--
--
CTS
RTS
Transmission unit
Receiving unit
Fig. 3.8 (8)
1
234
5
6
7
8
9
Hand-shake Function
10
11
12
13
14
15
16
1
2
SIOCLK
=><____________E_n_d__B_i_t______~~--~~--------------------------.J)(stoP bit
RxD
Sampling
Timing
IRFRX
RTS
(Note)
In case of 8-bit asynchronous communication (UART), the last bit
is the bit 7 in the non-parity mode, and the parity bit in the
parity-added mode ••
Fig. 3.8 (9)
Timing Chart of RTS (request to send) Signal
MPU90-118
TOSHIBA
TMP90C840
Data write timing
--fLs\
If
I
C""'"
~\
jStopped
Transmission
13
14
SIOCLK
T
TXDCLK
TxD
H
16
14
2
1
--.,
15
16
1
2
3
I
I
""""5
--.,]
n
\start bit
H
51
n
A bit
0
(Note) 1) Keep the CTS signal at the "H" level until data are written into
the transmission buffer (SCBUF).
A fa 11 of the CTS signa 1 halts the transmis ison 0 f the next
data.
2) The transmission is restarted from the first fall of TXDCLK
after a fall of the CTS signal.
Fig. 3.8 (10)
QD
GD
3.8.3
(1)
Hand-shake by CTS (clear to send) Signal
Transmission buffer
The transmission buffer (SCBUF) shifts out the data written by the CPU
from the LSB as based on the shift clock TXDSFT generated by the
transmission control unit.
When all bits are shifted out, the
transmission buffer becomes empty, generating the interrupt INTTX.
Parity control circuit
Setting the serial channel control register SCCRS (PE: Parity enable)
to "1" allows the addition of a parity bit in transmitting/receiving
data, only in the 7-bit DART or 8-bit DART mode.
Either even or odd
parity can be selected by the SCCR6 (EVEN) register.
In the transmission mode, the parity is automatically generated as
based on the data written into the transmission buffer (SCBUF),
storing into the 7th bit (TB7) of SCBUF in the 7-bit DART mode or into
TB8 in the 8-bit DART mode for transmission.
PE and EVEN should be
designated before writing data into the transmission buffer.
In the receiving mode, the parity is generated from data shifted into
the receiving buffer 1 and transferred to the receiving buffer 2
(SCBUF).
A parity error is detected and the PERR flag is set if the
parity status mismatches the 7th bit (RB7) of'SCBOF in the 7-bit DART
mode or RB8 in the 8-bit DART mode.
Operation
Mode 0 (I/O interface mode)
This mode is used to increase the number of I/O pins of the TMP90C840
for transmitting/receiving data and supplying a synchronous clock
(SCLK) to an external shift register.
MPU90-1l9
TOSHIBA
TMP90C840
Output Port Expansion
Input Port Expansion
Shift
A
Register
TMP90C840
Shift
Register
TMP90C840
B
TxD
SI
RxD
C
QH
SCK
E
SCI<"
~
CLOCK
Port
----.
S/I
F
F
Port
RCK
G
G
H
H
TC74HC595
TC74HC166
Fig. 3.8 (11)
CD
B
C
D
E
D
SCLl<
A
I/O Interface Mode
Transmission
Each time the CPU writes data into the transmisison buffer, 8-bit data
are output from TxD pin. When all data are output, IRFTX is set, and
the interrupt INTTX occurs.
234
4
1
4
CLK
':'X Data
;'lriting
Tir:ing
SCLK
TxD
I
-----x'
,-----'-i.
. . bit
bit
I
TXDSFT ----________________-u
IP2TX
bt±*:
____________________________________
@
I
bit 6
I
I
*=
-b-i-t-7~!
I
~____~!~
:
~{(
)JI-------------------...J
(INTTX Interrupt Flag)
Fig 3.8 (12)
I
I
I
1
Transmitting Operation (I/O Interface Mode)
Receiving
Each time the CPU reads the receiving data and clears the receiving
interrupt flag IRFRX, the next data are shifted into the receiving
buffer 1. When 8-bit data are received, the data are transferred to
the receiving buffer 2 (SCBUF), which sets IRFRX and generates
interrupt INTRX.
For rece~v~ng data, the receiving enable state is previously set
(RxE=l) .
MPU90-120
TOSHIBA
TMP90C840
I
I
~~
¢2
IRFRX
(INTRX
I
interrupt
SCLK
I
I
: \
I
:
I
-----b-i-t--O------)d~'-b-i-t--l-~tJk--b-it--6~)(~-b-i-t--7~jr~-----
RxD
I
Transfer timing to ____________________________________________________~~
receiving buffer 2
Fig 3.8 (13)
(2)
Receiving Operation (I/O Interface Mode)
Mode 1 (7-bit UART mode)
The 7-bit UART mode is obtained by setting the serial channel mode
register SCMOD3 2 (SM) to "01".
This mode allows the addition of a parity bit, which is enabled or
disabled by the serial channel control register SCCRS (PE). When PE =
1 (enable), even or odd parity can be selected by SCCR6 (EVEN).
Example:
When transmitting data with the following format,
control registers should be set as described below.
(Baud Rates
•
P3CR
SCMOD
TRUN
SCCR
INTEL
SCBUF
(Note)
2400 baud @fc
= 9.8304 MHz)
Transfer direction
- a1
<<- x a - x 0 1 1 1
<- I 0 1
<- x 1 1 x x x x 0
I
<<- * * * * * * * *
x:
Don't care
Select P32 as the TxD pin.
Set the transfer speed at 2,400 bps in
the 7-bit UART mode.
Add an even parity.
Enable INTTX interrupt.
Set data for transmission.
No change
MPU90-121
the
TOSHIBA
(3)
TMP90C840
Mode 2 (8-bit UART mode)
The 8-bit UART mode is obtained by setting SCMOD3 and SCMOD2 (SM) to
"10". This mode a Iso allows the addition of a parity bit, as enabled
or disabled by SCCRS (PE). When PE = 1 (enable), even or odd parity
can be selected by SCCR6 (EVEN).
Example:
When receiving data with the following format, the control
registers should be set as described below.
odd
(Baud Rates 9600 bps @fc = 9.8304 MHz)
~.~---------Transfer
direction
Main setting:
- P3CR
(SCCR (- x 0 1 x x x
TRUN (- 1 1 1 SCMOD (- - 0 1 x 1 0
INTEL (- - -
-
0 1
x 0
1 1
1 -
Select P30 as the RxD pin.
Add an odd parity.
Set the transfer speed at 9,600 bps in
the 8-bit UART mode.
Enable INTTX interrupt.
INTRX processing
I Ace
(- SCCR
00011100 Check errors.
I If Acc = a then erro
I_Acc
(- SCBUF
Read out the received data.
(Note)
(4)
x;
Don't care
No change
Mode 3 (9-bit UART mode)
The 9-bit UART mode is obtained by setting SCMOD3, 2 (SM) = "11". The
addition of a parity bit is disabled in this mode.
The MSB (9th bit) is written into TB8 for transmission, and into RB8
for receiving.
Writing into or reading from the buffer must begin
with the MSB followed by SCBUF.
Wake-up function
In the 9-bit UART mode, setting SCMOD4 (WU) to "1" allows the wake-up
operation of the slave controllers.
The interrupt INTRX occurs only
when RB8 = 1.
MPU90-122
TOSHIBA
TMP90C840
T
t
TxD
RxD
!
~
•
TxD
RxD
(P33)
!
j
TxD
RxD
(P33)
!
TxD
RxD
(P33)
Master
Slave 1
Slave 2
Slave 3
TMP90C840
TMP90C840
TMP90C840
TMP90C840
(Note)
For the wake-up operation, P33 should be always selected as the
TxD pin of the slave controllers, and put in the open drain
output mode.
Fig. 3.8 (14)
Serial Link Using Wake-up Function MPU90-137
IProtocoll
Select the 9-bit UART mode for the master and slave controllers.
Set the WU bit of each slave controller to "1" to enable data
receiving.
The master controller transmits I-frame data including the 8-bit
select code for the slave controllers. The MSB (bit 8) is set to "1".
select code of slave controller.
"1"
GU
Each slave controller receives the above frame, and clears the WU bit
to "0" if the above select code matches its own select code.
CD
The master controller transmits data to the specified slave controller
(whose WU bit is cleared to "0"). At the same time, the MSB (bit 8)
is clea~ed to "0".
Data
MPU90-123
"0"
TOSHIBA
®
TMP90CS40
The other slave controllers (with the WU bit remalnlng at "I ") ignore
the receiving data because their MSBs (bit S or RBS) are set to "0" to
disable the interrupt INTRX.
When the WU bit is cleared to "a", the interrupt INTRX occurs, making
it possible to read the receiving data.
Only when WU = 0, the slave controllers can transmit data to the
master controller, including those indicating the end of data
receiving.
Link two slave controllers serially with the master
controller, and use the internal clock 01 as the transfer
clock.
Example:
AA
t,
TxD
~
TxD
RxD
Haster
~
RxD
Slave 1
,~
TxD
~
RxD
Slave 2
Select Code Select Code
00000001
00001010
o
Set the master control
Main
P3CR <- 0 0 1
INTEL <- SCCR (- x x x x x x
SCMOD (- 1 0 1 a l l
SCBUF
<-
a 0 a a a 0
1 0
1 1
Select P32 as TxD and P31 as RxD.
Enable INTRX and INTTX.
Disable the hand-shake function.
Select 01 as the transfer clock in the
9-bit UART mode.
Set the select code for the slave controller 1.
x a
1 a
o
1
INTTX interrupt
I-SCMOD (- a
I_SCBUF <- *
o
Set TBS to "a".
Set data for transmission.
*******
Set the slave controller 2
Main
I-P3CR
<--
1 1
a
1
a
1 1
I INTEL Analog
*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
input channel select
ANO
000
001
010
011
100
101
110
ANI
AN2
AN3
AN4
ANS
Not used
IlTl
R/w
_____________ > AID
*
1
0
conversion start
1
1
1-----1---------------------------1
1 1 1 Start AID conversion
1
(Note) Always cleared to "0" when read out
R/w
______________>
AID conversion speed selection
* 1 0 1 95 states (1911s)
1
1-----1---------------------------1
1
(Note)
1
190 states (3811s)
1
Conversion speed calculated at fc=lOMHz
1
1
1
1
1 R
1_ _ _ _ _ _ _ _ _ _
1
1
>
AID conversion busy flag
* 1 0 1 AID conversion not busy 1
1-----1---------------------------1
1 1 1 AID conversion busy
1
1
1
1
1
1
l
R
------------------------->
*
Fig. 3.9 (2)
1
End of conversion flag
1
AID conversion not ended
1 0 1 nor started
1
1-----1---------------------------1
1 1 1 AID conversion ended
1
AID Converter Mode Register
MPU90-126
TOSHIBA
TMP90C840
MSB
7
LSB
6
5
4
3
2
o
ADREG
(FFEEH)
AID conversion result register (Read only)
Fig. 3.9 (3)
3.9.2
AID Conversion Result Register
Operation
(1)
Analog reference voltage
The high analog reference voltage is applied to the VREF pin, and the
low analog reference voltage is applied to the AGND pin.
The reference voltage between VREF and AGND is divided by 2S6 by
connecting ladder resistance, and compared with the analog input
voltage for AID conversion.
(2)
Analog input channels
For the AI D convers ion, one of the six ana log input channe Is (ANO
(PSO) to &~S (PSS» is selected by the register ADMOD2-0 (ADCH).
ADCH is initialized to "000" by resetting, whereby the ANO pin 18
selected.
The pins not used for the analog input can be used for ordinary input
(PS).
(3)
Selection of AID conversion speed
Normally, the AID converter is used in the high-speed conversion mode
that completes the operation in 95 states (19 ~s @fc=lOMHz).
When using an oscillation frequency of more than 10MHz, set the
register ADMOD4 (ADes) to "1" and obtain the conversion speed of 190
states (38 ~s, @fc=10MHz).
ADCS is initialized to "0" by resetting, by which the AID converter
turns to the high-speed conversion mode.
(4)
Starting AID conversion
The AID conversion is started by writing "1" into the register ADMOD3
(ADS). When the AID conversion is started, the ADMODS (ADBF) flag is
set to "1", indicating that the conversion is in progress.
(S)
AID conversion end and interrupt
When the AID conversion is completed, the ADMOD6 (EOCF) flag is set to
"1", indicating that the AID conversion is completed.
Then the ADBF
flag is cleared to "0" to generate the interrupt INTAD.
INTAD (interrupt by the AID converter) is controlled by the interrupt
enab Ie flag INTEL 7 (IET2), also used for INTT2 (interrupt by Timer
2). Either INTAD or INTT2 is selected by the INTER3 (ADIS) flag.
To
generate INTAD interrupt, both IET2 and ADIS should be set to "1".
Both INTAD and INTT2 jump to the same vector address (0040H), but can
be distinguished by the ADIS flag.
When IN TAD is latched, the INTAD status cannot be cleared by software.
MPU90-127
TOSHIBA
(6)
TMP90C840
Reading AID conversion results
The results of AID conversion are stored into the ADREG register.
By reading the contents of the ADREG register, EOCF flag is cleared to
"0".
When the contents of the ADREG register is read while the AID
conversion is performed, the AID conversion results become undefined.
AID conversion is stopped by a HALT instruction except in the RUN
mode, by which the AID conversion results also become undefined.
In th~ RUN mode, AID conversion is not stopped by a HALT instruction.
Example:
[1]
Analog input vo ltage to the AN3 pin is converted to a
digital value in the high-speed conversion mode (95
states), and the result is stored into the memory address
FFIOH by using AID interrupt IN TAD service routine.
Main setting
Set INTADE to "1".
Enable INTT2
Select AN3 as the analog input channel,
and start the AID conversion in the highspeed conversion mode.
INTEH (- 1
INTEL (- 1 - - - - ADMOD (- x x x a 1 0 1 1
AID interrupt service routine
I A
(I (FFIOH)
I
ADREG
A
(-
Example:
[2] Analog input voltage to the AN2 pin is converted to a
digital value in the high-speed conversion mode (95
states), and the result is loaded into the accumulator when
the end of conversion is detected by the EOCF flag.
ADMOD (- x x x 0 1 0 1 0
loop:
if EOCF
(Note)
3.10
Load the contents of ADREG into the ac-.
cumulator. Store the accumulator value
into the memory address FFIOH.
x·
o
then loop
else A (-
Don't care
Select AN2 as the analog input channel,
and start the AID conversion in the highspeed conversion mode.
ADREG
No change
Watchdog timers (Runaway detecting timer)
When the mulfunction (runaway) of the CPU occurs due to any cause such
as noise, the watchdog timer (WDT) detec ts it to return to the normal
sate.
When WDT has detected malfunction, a non-maskable interrupt is
generated to indicate it to the CPU.
MPU90-128
TOSHIBA
TMP90C840
3.10.1
Architecture
Fig. 3.10 (1) is a block diagram of the watchdog timer (WDT).
The watchdog timer consists of a 20-stage binary counter (input clock:
o @fc/2), a flip-flop that disables/enables the selector, a selector
that selects one of the four output clocks generated from the binary
counter, and two control registers.
INTWD Interrupt
Selector
¢
(fc/2)
enable
Twenty-stage Binary
Counter for Watch Dog
Timer
Reset
Under Execution --------~
of HALT Instruction
Write
(stop Mode)
'4EH'
Q
F/F
R
Reset
'-----'"-........:- WDTE
Watch Dog Timer
control Register
(WDCR)
Internal Data Bus
Fig. 3.10 (1)
3.10.2
Block Diagram of Watchdog Timer
Control Registers
WDT is controlled by two control registers (WDMOD and WDCR).
(1)
1
Watchdog timer mode register (WDMOD)
Set the detecting time of watchdog timer (WDTP)
The WDT interrupt period is set by this 2-bit flag.
WDTP is
i~!tialized to "00" by resetting, providing the initial set value of
2 /fc (sec.) (approx. 8,192 states).
MPU90--129
TOSHIBA
(i)
TMP90C840
WDT enable/ disable control (WDTE)
WDTE is initialized to "I" by resetting, which enables the watchdog
timer function.
To disab Ie the func t ion, the bi t shou ld be cleared to "a" and the
disable code "BlH" should be written into the WDCR register.
By
using this dual procedure, it becomes hard to disable the WDT even
if the malfunction occurs.
The disable state can be returned to the enable state by setting the
WOTE bit to "I".
MPU90-l30
TOSHIBA
TMP90C840
,
7
,
WDMOD ! WDTE!
,
(FFD2H)
6
5
WDTP
I
,
4
,
'WARM'
,
,
,
3
1
2
0
1
HALTM
1
EXFIDRVEI
,
I
I
1
I~>
See "3.4.4 STOP Mode".
R
1
1_ _
>
Invert at each EXX instruction execution.
R/W
_ _ _ _ _>
Se lee t standby mode by HALT
instruction (HALT mode)
RUN Mode
STOP Mode
IDLEI Mode
IDLE2 Mode
00
*
01
10
11
R/W
_ _ _ _ _ _ _ _ _>
*
,
Selec t warming-up time "("hen
returned from stop mode.
1
1
,1
,
0
1
214/fc (Approx. 1.6 !Ds)
1
1
1
,1
1
2
16
( Note)
/fc (Approx. 6.6 rns)
fc = 10 MHz
R/W
Select detecting period of
watchdog timer (WDTP).
>
* ,
1
1
I
1
,
I
I
I
I
I
I
00
,1
214/fc (Approx. 1.6 ms)
I
1
01 I
2
16
/fc (Approx. 6.6 ms)
I
I 18
10 I 2 /fc (Approx. 26.2 ms)
I
I 2O
11 I 2 /fc (Approx. 105 rns)
I
(Note)
fc = 10 MHz
R/W
____________ >
Watchdog timer enable/disable control
I 0 I Disable (Interac t ive with WDCR) I
1 I Enable
I
* I
(Note)
To disable the WDT func t ion, the disable code shou Id be writ ten
into the WDCR register.
Fig. 3.10 (2)
Watchdog Timer Mode Register
MPU90-131
TOSHIBA
(2)
TMP90C840
Watchdog timer control register (WDCR)
This register is used to disable the watchdog timer function and clear
the binary counters.
o Disable WDT
The watchdog timer can be disabled by, after clearing WDMOD7
(WDTE) to "0", writing the disable code (B1H) into this WDCR
register.
WPMOD
WDCR
o
<- O-----XX
<- 10110001
Clear WDTE to "0".
Write disable code (B1H).
Clear binary counter
The binary counter can be cleared and resume counting by writing
the clear code (4EH) into the WDCR register.
WDCR
7
6
<5
Write clear code (4EH).
01001110
4
3
2
1
o
WDCR
(FFD3H)
1
Iw
1_ _ _ _ _ _
>
Disable/clear watchdog timer.
B1H 1
4EH"1
Other I
Fig. 3.10 (3)
Disable code
Clear code
Watchdog Timer Control Register
MPU90-132
TOSHIBA
3.10.3
TMP90C840
Operation
The watchdog timer generates INTWD (watchdog timer interrupt) after a
time specified by the register WDMOD6, 5 (WDTP).
The binary counter
for the watchdog timer is cleared to "0" by software (instruction)
before the interrupt occurs.
If the CPU caused a malfunction
(runaway)
for reason such as noise and fails
to execute
the
instruction to clear the binary counter, the counter will overflow and
the watchdog timer interrupt INTWD occurs.
The CPU detects the
malfu~ction (runaway) by this interrupt.
The watchdog timer starts its operation as soon as the reset state is
cleared.
The watchdog timer stops its operation only in the STOP mode.
When
the STOP mode is released, the watchdog timer starts its operation
after a specified warming-up time.
In the other standby mode (IDLE 1, IDLE 2 or RUN modes), the watchdog
timer is enabled.
However, the function can be disabled before
selecting any of these modes.
Example: (1) Clear the binary counter.
WDCR <- 01001110
Write clear code (4ER)
16
(2) Set 2 /fc for the detecting time of watchdog timer.
WDMOD <- 101---XX
(3) Disable the watchdog timer.
WDMOD <- O-----XX
Clear WDTE to "0"
WDCR <- 10110001
Write disable code (BIR)
(4) Select the IDLE 2 mode.
WDMOD <- 0---11XX
Disable WDT and set IDLE 2 mode
WDCR <- 10110001
Select the standby mode
Execute HALT instruction
16
(5) Select the STOP mode (Warming-up time: 2 /fc)
WDMOD <- ---101XX
Select STOP mode
Execute HALT instruction
Select the standby mode
MPU90-133
TMP90C840
TOSHIBA
4.
ELECTRICAL CHARACTERISTICS
TMP90C840N/TMP90C840F/TMP90841N
4.1
Absolute maximum ratings
S~bol
I
VCC
I
VIN
I
PD
I
TSOLDERI
TSTG I
TOPR I
4.2
Parameter
Supply voltage
InEut voltage
Power dissi~ation (Ta=85' C)
Soldering temEerature
Storage temEerature
°Eerating temEerature
Rating
-0.5 - +7
-0.5 - Vcc +0.5
250
260
-65 - 150
-40 - 85
IUnitl
I V I
I V I
I mV I
I ·c I
I ·C I
I ·C I
DC characteristics
TA=-40 - 8S'C
Parameter
ISymbol I
I
I
I VIL I InEut Low Voltage (PO)
I VILI I Pl,P2,P3,P4,PS zP6,P7,P8
I VIL2 I/RESET,INTO,/NMI,xl,x2
I VIL3 IlEA
I VIH I InEut High Voltage (PO)
I VIRI I Pl,P2,P3~P4,PSzP6,P7,P8
I VIH2 I/RESET,INTO,/NMI,xl,x2
I VIH3 IlEA
I VOL 10utEut Low Voltage
I VOR 10utput High Voltage
I VORl I
I VOR2 I
I I DAR IDarlington Drive Current
1(81/0 Eins)
I
I ILL I Input Leakage Current
I
I
I ILO 10utput Leakage Current
I
I
I ICC 10perating Current (RUN)
Idle 1
I
I
Idle 2
I
I
STOP
I
I
I
I
Iv sTOplPower Down Voltage
I
I
IR REST I IRESET Pull UE Register
I CIO IPin Capacitance
I
I
I VIH I Schmitt width/RESET,/NMI,
I
I INTO
Vce=sV±lO%
Max.
Min.
IUnitl Test
I
I
I
I Condition I
I
I
10.2Vcc-0.ll V I
1-0.3
I
10.3Vce
1-0.3
I
I V I
10.2sVcc
1-0.3
I
I V I
1-0.3
10.3
I V I
I
10.2Vcc+l.lIVcc+0.3
I V I
I
I Vcc+0.3
IO.7Vce
I V I
I
IVcc+0.3
10.7sVcc
I
I V I
IVcc+0.3
I Vcc-O. 3
I
I V I
10.45
I
I V I IOL=1.6mA
I
12.4
I V I IOR=-400UA I
I
10.7sVcc
I V IIOH=-100UA I
I
10.9Vcc
I
I
I V I IOH=-20UA
1-5.0
1-1.0
I
I rnA IVEXT=1.SV
I REXT=I.lkn I
I
I
I
I±S
I UA 10.2RL
1--------1 2
lEX rr,rr lEX AF,AF'
109
IAF<-->AF'
1--------1 2
I
IEXX
lOA
IBC/DE/HL<->BC'/DE'/HL'
1--------1 2 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
EX (gg),rr
IEO+gg:50+rr
I (gg)W<-->rr
1--------114 I
EX (ix+d),rr
IFO+ix:d:50+rr l(ix+d)W<-->rr
1--------1 IB I
EX mem,rr EX (HL+A),rr
IF3:50+rr
1(HL+A)W<-->rr
1--------1 22 I
EX (mn),rr
IE3:n:m:50+rr I (mn)W<-->rr
1--------1 18 I
EX (n),rr
IE7:n:50+rr
1(n)W<-->rr
1--------116 1
----------- ---------------1--------------1-------------------------------1--------1-----1
LDI
LDI
IFE:5B
I (DE)<-(HL)
1---0-MO-114 I
I
I
I
I
IDE<-DE+l
I
I
I
I
IHL<-RL+l
I
I
I
I
IBC<-BC-l
----------- ---------------1--------------1-------------------------------1--------1-----1
LDIR
LDIR
IFE:59
I (DE)<-(RL)
1---0-00-118/141
I
IDE<-DE+l
I
I
I
I
IHL<-HL+l
I
I
I
I
I
I
I
I
IBC<-BC-l, Repeat until BC-O.
-----------1---------------1--------------1-------------------------------1--------1-----1
LDD
I LDD
IFE: 5A
I (DE )<- (HL)
I---O-MO-I 14 I
IDE<-DE-l
I
I
I
I
I
IHL<-RL-l
I
I
I
I
I
1
I
I
I
I
IBC<-BC-l
-----------1---------------1--------------1-------------------------------1--------1-----1
LDDR
ILDDR
IFE:5B
I (DE)<-(RL)
1---0-00-IIB/141
I
I
I
IDE<-DE-l
I
I
I
I
I
I
IHL<-HL-l
I
I
I
1
I
I
I
I
I
IBC<-BC-l, Repeat until BC=O.
1-----------1---------------1--------------1-------------------------------1--------1-----1
ICPI
ICPI
IFE:5C
IA-(HL)
I*N-**MI-1 14 I
IRL<-HL+l
I
I
I
I
I
I
I
I
I
I
I
I
IBC<-BC-l
1-----------1---------------1--------------1-------------------------------1--------1-----1
ICPIR
ICPIR
I FE: 5D
IA- (HL)
I*N-**MI-118/ 141
I
I
I
IRL<-HL+l
I
1
I
I
I
I
IBC<-BC-l
I
I
I
I
I
I
I
I
I
IRepeat until A=(RL) or BC=O.
1-----------1---------------1--------------1-------------------------------1--------1-----1
ICPD
ICPD
IFE:5E
IA-(RL)
I*N-**MI-1 14 I
I
I
I
I
I
I
IHL<-RL-l
I
I
I
I
I
I
IBC<-BC-l
1-----------1---------------1--------------1-------------------------------1--------1-----1
ICPDR
ICPDR
IFE:5F
IA-(RL)
I*N-**MI-IIB/141
I
I
I
IHL<-RL-l
I
I
I
I
I
I
IBC<-BC-l
I
I
I
I
I
I
I
I
I
I Repeat until A=(RL) or BC-O.
(Note)
Flag M:
Flag N:
If BC=O after execution, P/V flag is 0, and otherwise 1.
If A=(RL), Z flag is I, and otherwise o.
Appendix-2
<- repe
/no rep
<- repe
/no rep
<- repe
/no re~
<- repe
/no rep
TOSHIBA
Appendix A Table of Machine Instructions
Appendix A Table of Machine Instructions (3/11)
4.
8-bit arithmetic operation
I Instructionl
Mnemonic
Code
Function
ISZIHXVNCI T
I ADD A, r
I ADD A,g
I F8+g:60
I A <-A+g
I**-**VO*I 4 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I ADD A,n
IADD A,n
168:n
IA <-A+n
I**-**vo*! 4 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
IADD A,(gg)
IEO+gg:60
IA <-A+(gg)
1**-**vo*1 6 I
I
IADD A,(ix+d) IFO+ix:d:60
IA <-A+(ix+d)
1**-**vo*1 10 I
IA <-A+(HL+A)
1**-**vO*114 I
I ADD A,mem IADD .A,(HL+A) 1F3:60
I
IADD A,(mn)
IE3:n:m:60
IA <-A+(mn)
!**-**vo*1 10 I
I
IADD A,(n)
160:n
IA <-A+(n)
I**-**VO*I 8 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I ADD r,n
I ADD g,n
I FB+g:6B:n
I g <-g+n
I**-**VO* I 6 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
I ADD (gg) ,n
I EB+gg:68:n
I (gg)<- (gg)+n
1**-**vO*1 10 I
1**-**vo*1 14 I
I
IADD (ix+d) ,n I F4+ix:d:68:n I (ix+d)<-(ix+d)+n
IADD mem,n I ADD (HL+A),n IF7:68:n
I (HL+A)<-(HL+A)+n
1**-**vO*118 I
I
IADD (vw),n
IEB:w:v:68:n
I (vw)<-(vw)+n
I**-**VO* I 14 I
IEF:w:68:n
I (w)<-(w)+n
1**-**vo*1 12 I
I
I ADD (w),n
1-----------1---------------1--------------1-------------------------------1--------1-----1
IADC A,r
IADC A,g
IF8+g:6l
IA <-A+g+CY
I**-**VO*I 4 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I ADC A,n
I ADC A,n
169:n
IA <-A+n+CY
1**-**vO*1 4 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
IADC A,(gg)
IEO+gg:61
IA <-A+(gg)+CY
I**-**VO* I 6 I
I
IADC A,(ix+d) IFO+ix:d:61
IA <-A+(ix+d)+CY
1**-**vo*1 10 I
IADC A,mem IADC A, (HL+A) IF3:61
IA <-A+(HL+A)+CY
1**-**vo*1 14 I
IADC A,(mn)
IE3:n:m:61
IA <-A+(mn)+CY
1**-**vo*110 I
I
I
I ADD A, (n)
161:n
IA <-A+(n)+CY
1**-**vO*1 8 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
IADC r,n
IADC g,n
IF8+g:69:n
Ig <-g+n+CY
1**-**vo*1 6 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
IADC (gg),n
IEB+gg:69:n
!(gg)<-(gg)+n+CY
1**-**vo*1 10 I
IADC (ix+d) ,n I F4+ix:d:69':n I (ix+d)<-(ix+d)+n+CY
I**-**vO* I 14 I
I
IADC mem,n IADC (HL+A),n IF7:69:n
I (HL+A)<-(HL+A)+n+CY
1**-**vo*1 IB I
IADC (vw),n
IEB:w:v:69:n
l(vw)<-(vw)+n+CY
1**-**vo*114 I
I
I
IADC (w),n
IEF:w:69:n
I (w)<-(w)+n+CY
1**-**vo*112 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I SUB A,r
ISUB A,g
IFB+g:62
IA <-A-g
1**-**V1*1 4 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I SUB A,n
I SUB A,n
16A:n
IA <-A-n
1**-**Vl*1 4 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
I SUB A, (gg)
IEO+gg:62
IA <-A-(gg)
1**-**Vl*1 6 I
ISUB A,(ix+d) IFO+ix:d:62
IA <-A-(ix+d)
1**-**Vl*1 10 I
I
ISUBA,mem ISUB A,(HL+A) IF3:62
IA<-A-(HL+A)
1**-**Vl*114 I
I
ISUB A,(mn)
IE3:n:m:62
IA <-A-(mn)
1**-**Vl*110 I
I
ISUB A,(n)
162:n
IA <-A-(n)
1**-**Vl*1 8 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
ISUB r,n
ISUB g,n
IFB+g:6A:n
Ig <-g-n
1**-**Vl*1 6 I
I-----------I---------------I--------------I-~-----------------------------1--------1-----1
I
I SUB (gg),n
IEB+gg:6A:n
I (gg)<-(gg)-n
1**-**Vl*1 10 I
ISUB (ix+d),n IF4+ix:d:6A:n I (ix+d)<-(ix+d)-n
1**-**Vl*114 I
I
I SUB mem,n I SUB (HL+A),n IF7:6A:n
I (HL+A)<-(HL+A)-n
1**-**Vl*1 IB I
I
I SUB (vw) ,n
IEB :101: v:6A:n
I (vw )<-(vw)-n
I**-**Vl* I 14 I
IEF:w:6A:n
I (w)<-(w)-n
1**-**Vl*1 12 I
I
I SUB (101) ,n
1-----------1---------------1--------------1-------------------------------1--------1-----1
I SBC A,r
I SBC A,g
I FB+g:63
IA <-A-g-CY
1**-**Vl*1 4 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
ISBC A,n
ISBC A,n
16B:n
IA <-A-n-CY
1**-**vl*1 4 I
1-----------1---------------/--------------1-------------------------------1--------1-----1
I
I SBC A, (gg)
IEO+gg:63
IA <-A-(gg)-CY
1**-**Vl*1 6 I
I
I SBC A, (ix+d) IFO+ix:d:63
IA <-A-(ix+d)-CY
1**-**Vl*1 10 I
IA <-A-(HL+A)-CY
1**-**vl*1 14 I
I SBC A,mem I SBC A, (HL+A) IF3:63
IE3:n:m:63
IA <-A-(mn)-CY
I**-**V1* I 10 I
I
I SBC A, (1111)
I
I SBC A, (n)
163:n
IA <-A-(n)-CY
1**-**Vl*1 8 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
ISBC r,n
ISBC g,n
IFB+g:6B:n
Ig <-g-n-CY
1**-**Vl*1 6 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
I SBC (gg) ,n
I EB+gg:6B:n
I (gg)<-(gg)-n-CY
1**-**Vl*1 10 I
I
ISBC (ix+d) ,n I F4+ix:d:68:n I (ix+d)<-(ix+d)-n-CY
1**-**Vl*1 14 I
ISBC mem,n ISBC (HL+A),n IF7:6B:n
I (HL+A)<-(HL+A)-n-CY
1**-**Vl*1 IB I
I
ISBC (vw),n
IEB:w:v:6B:n
I(vw)<-(vw)-n-CY
I**-**V1* I 14 I
ISBC (w),n
IEF:w:6B:n
I (w)<-(w)-n-CY
1**-**Vl*112 I
I
Appendix-3
TOSHIBA
Appendix A Table of Machine Instructions
Appendix A Table of Machine Instructions (4/11)
I Instructionl
Mnemonic
Code
Function
\ SZIHXVNCI T
lAND A,r
lAND A,g
IFB+g:64
IA <-A AND g
\**-10POOI 4 I
1-----------1---------------1-------------- 1--------.-----------------------1-------- 1-----1
lAND A,n
lAND A,n
16C:n
IA <-A ,AND n
1**-10pool 4 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
lAND A,(gg)
IEO+gg:64
IA <-A AND (gg)
1**-10pool 6 I
IA <-A AND (ix+d)
1**-lOPOO I 10 I
I
I AND A, (ix+d) I FO+ix: d: 64
lAND A,mem lAND A,(HL+A) IF3:64
IA <-A AND (HL+A)
1**-10POOI 14 I
I
lAND A,(mn)
IE3:n:m:64
IA <-A AND (mn)
1**-10pool 10 I
I
lAND A,(n)
164:n
IA<-AAND(n)
1**-10pool B I
1-----------1---------------1--------------1-------------------------------1--------1-----1
lAND r,n
lAND g,n
IFB+g:6C:n
Ig <-g AND 0
1**-10pool 6 I
I-----------I---------------I----------~---I-------------------------------1--------1-----1
I
lAND (gg) ,n
I EB+gg:6C:n
I (gg)<-(gg) AND n
1**-10POOI 10 I
lAND (ix+d),n IF4+ix:d:6C:n I (ix+d)<-(ix+d) AND n
1**-10pool 14 I
I
lAND mem,n lAND (HL+A),n IF7:6C:n
I(HL+A)<-(HL+A) AND n
1**-10pool IB I
I
lAND (vw),n
IEB:w:v:6C:n
I(vw)<-(vw) AND n
1**-10pool 14 I
I
lAND (w),n
IEF:w:6C:n
I(w)<-(w) AND n
1**-10pooI12 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
lOR A,r
lOR
A,g
IF8+g:66
IA <-A OR g
I**-OOPOO I 4 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
lOR A,n
lOR
A,n
16E:n
IA <-A OR n
I**-OOPOO I 4 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
lOR
A,(gg)
I EO+gg: 66
IA<-AOR(gg)
I**-OOPOO I 6 I
I
lOR
A,(ix+d) IFO+ix:d:66
IA <-A OR (ix+d)
I**-oopool 10 I
lOR A,mem lOR
A,(HL+A) IF3:66
IA <-A OR (HL+A)
I**-OOPOOI 14 I
I
lOR A,(am)
IE3:n:m:66
IA <-A OR (mn)
I**-OOPOOI 10 I
lOR
A,(n)
166:n
IA <-A OR (n)
I**-oopool 8 I
I
1-----------1---------------1--------------1-------------------------------1--------1-----1
lOR r,o
lOR
g,n
IFB+g:6E:n
Ig <-g OR n
I**-OOPOOI 6 I
1-----------1---------------1--------------1-------------------------------\--------1-----1
I
lOR
(gg),n
I EB+gg: 6E:n
I (gg)<-(gg) OR n
\**-OOPOO I 10 \
I
lOR
(ix+d),n IF4+ix:d:6E:n I (ix+d)<-(ix+d) OR n
1**-oOPOOI14 I
lOR mem,n lOR
(HL+A),n IF7:6E:n
I (HL+A)<-(HL+A) OR n
I**-oopool 18 I
I
lOR
(vw),n
IEB:w:v:6E:n
l(vw)<-(vw)ORn
1**-00POOI14 I
lOR
(w),n
IEF:w:6E:n
I (w)<-(w) OR n
1**-00POOI12 I
I
1-----------1---------------1--------------1-------------------------------\--------1-----1
IXOR A,r
IXOR A,g
IFB+g:65
IA <-A XOR g
\**-OOPOOI 4 I
1-----------1---------------1--------------\-------------------------------\--------1-----1
IXORA,n
IXOR A,n
16D:n
IA<-AXORn
1**-00POOI4 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
IXOR A,(gg)
IEO+gg:65
IA <-A XOR (gg)
I**-oopool 6 I
I
IXOR A,(ix+d) IFO+ix:d:65
IA <-A XOR (ix+d)
1**-oOPOOI 10 I
IXOR A,mem IXOR A,(HL+A) IF3:65
\A <-A XOR (HL+A)
I**-OOPOOI 14 I
I
IXOR A,(mn)
\E3:n:m:65
IA <-A XOR (m)
1**-oOPOOI 10 I
IXOR A, (n)
165:n
IA <-A XOR (n)
I**-OOPOOI 8 I
I
1-----------1---------------1--------------1-------------------------------1--------\-----1
IXOR r,n
IXOR g,n
IFB+g:6D:n
\g <-g XOR n
1**-oOPOOI 6 I
1-----------1---------------1--------------\-------------------------------\--------\-----\
I
IXOR (gg),n
IE8+gg:6D:n
1(gg)<-(gg) XOR 0
1**-oOPOOI 10 \
I
IXOR (ix+d),n IF4+ix:d:6D:n \ (ix+d)<-(ix+d) XOR n
I**-oopool 14 I
IXOR mem,n IXOR (HL+A),n IF7:6D:n
\(HL+A)<-(HL+A) XOR n
\**-OOPOOI 18 1
I
IXOR (vw),n
\ EB:w:v:6D:n
\ (vw)<-(vw) XOR 0
\**-OOPOO I 14 \
1
IXOR (w) ,n
1EF:w:6D:n
1(w)<-(w) XOR 0
\**-OOPOOI 12 1
1-----------1---------------1--------------1-------------------------------\--------1-----1
Icp A,r
Icp
A,g
IF8+g:67
IA-g
\**-**vl*14 1
1-----------1---------------1--------------1-------------------------------1--------1-----1
Icp A,n
Icp
A,n
16F:n
IA-n
1**-**Vl*1 4 1
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
Icp
A,(gg)
IEO+gg:67
IA-(gg)
1**-**Vl*1 6 I
I
Icp
A,(ix+d) IFO+ix:d:67
IA-(ix+d)
1**-**Vl*110 I
A, (HL+A) IF3:67
IA-(HL+A)
I**-**Vl*\ 14 I
Icp A,mem Icp
A,(mn)
IE3:n:m:67
IA-(mn)
\**-**vl*1 10 I
I
Icp
A,(n)
167:n
IA-(n)
\**-**Vl*1 8 \
I
Icp
1-----------1---------------1--------------1-------------------------------1--------1-----1
Icp r,n
Icp
g,n
IFB+g:6F:n
Ig-n
\**-**vl*1 6 I
1-----------1---------------1--------------1-------------------------------\--------1-----1
I
Icp
(gg),n
IEB+gg:6F:n
I(gg)-n
1**-**Vl*1 8 \
I
Icp
(ix+d),n IF4+ix:d:6F:n I(ix+d)-n
1**-**Vl*112 I
Icp mem,n Icp
(HL+A),n IF7:6F:n
1(HL+A)-n
1**-**Vl*1 16 1
IEB:w:v:6F:n
I (vw)-n
\**-**Vl*112 I
I
Icp
(vw),n
I
Icp
(w),n
IEF:w:6F:n
I(w)-n
1**-**Vl*110 I
Appendix-4
Appendix A Table of Machine Instructions
TOSHIBA
Appendix A Table of Machine Instructions (Sill)
I Instructionl
Mnemonic
Code
I
Function
ISZIHXVNCI T I
I INC r
I INC r
IBO+r
I r (-r+l
I**-**vO-1 2 I
1----------- ---------------1--------------1-------------------------------1--------1-----1
INC (gg)
IEO+gg:B7
I (gg)<;-(gg)+l
I**-**vo-I B I
INC (ix+d)
IFO+ix:d:B7
I (ix+d)(-(ix+dhl
I**-**vo-I 12 I
INC mem
INC (HL+A)
IF3:B7
I (HL+A)<-(HL+A)+l
I**-**vo-I 16 I
IINC (mn)
IE3:n:m:B7
I (mn)(-(mn)+l
1**-**vO-112 I
IB7:n
I (n)<-(n)+1
I**-**vo-I 10 I
1
I INC (n)
I-----------I--~------------I--------------I-------------------------------1--------1-----
I DEC r
I DEC r
IBB+r
I r (-r-l
I**-**vI-1 2
1-----------1---------------1--------------1-------------------------------1--------1----I
IDEC (gg)
IEO+gg: BF
I (gg)(-(gg)-l
1**-**VI-1 B
I
DEC (ix+d)
IFO+ix:d:BF
I (ix+d)(-(ix+d)-1
1**-**VI-112
I DEC mem
DEC (HL+A)
I F3:BF
I (HL+A)(-(HL+A)-l
1**-**VI-1 16
DEC (mn)
IE3:n:m:BF
I (mn)<-(mn)-1
1**-**VI-1 12
DEC (n)
IBF:n
I (n)<-(n)-1
1**-**VI-1 10 I
----------- ---------------1--------------1-------------------------------1--------1-----1
INCX
INCX (n)
107:n
I If X=I, (n) (- (n)+1
I**-**vo-I 6/101 (- X=O/I
1----------- ---------------1--------------1-------------------------------1--------1-----1
IDECX
IDECX (n)
10F:n
I If X=I, (n) (- (n)-1
1**-**VI-1 6/101 <- X=O/I
(Note)
5.
If X=O in INCX and DECX instructions, all flags remain unchanged.
Special operation and CPU control
I Ins t ruc t ion I
Mnemonic
I
Code
I
Func t ion
I SZIHXVNC 1 T I
IA register IDAA A
lOB
IDecimal adjust accumulator
I**-**P-* I 4 I
110
IA
0 I -> I Cy I I**-OXPO*I 12 I
IRRC mem
IRRC (HL+A)
1F3:A1
I
-----------1**-OXPO*1 16 I
IRRC (mn)
IE3:n:m:A1
I
1**-OXPO*112 I
I
I
IRRC (n)
IE7:n:A1
I
1**-oxpo*110 I
-----------1---------------1--------------1-------------------------------1--------1-----1
RL
r
I RLA
I A2
I
I---ox-O* I 2 I
IRL g
IF8+g:A2
I
I**-OXPO*I 4 I
-----------1---------------1--------------1 I
I 1--------1-----1
I RL
(gg)
I EO+ gg: A2
I I
-----------I 1**-OXPO* I 8 I
IRL
(ix+d)
IFO+ix:d:A2
I --I Cy 1<--1 7 (-- 0 1-- I**-OXPO*I 12 I
RL mem
IRL
(HL+A)
IF3:A2
I
-----------1**-OXPo*1 16 I
IRL
(mn)
IE3:n:m:A2
I
I**-OXPO*I 12 I
IRL
(n)
IE7:n:A2
I
1**-OXPo*110 I
-----------1---------------1--------------1-------------------------------1--------1-----1
RR r
I RRA
I A3
I
I---ox-O* I 2 I
IRR g
IF8+g:A3
I
1**-OXPO*14 I
-----------1---------------1--------------1 I
1 1--------1-----1
IRR
(gg)
I EO+gg:A3
I I
-----------I 1**-oxpo*1 8 I
IRR
(ix+d)
IFO+ix:d:A3
I --I 7 -->
0 1-->1 CY 1-- I**-OXPO*I 12 I
RR mem
IRR
(HL+A)
IF3:A3
I
-----------1**-OXPo*1 16 I
IRR
(mn)
IE3:n:m:A3
I
I**-OXPO*I 12 I
I
IRR
(n)
IE7:n:A3
I
1**-oxpo*110 I
I
1-----------1---------------1--------------1-------------------------------1--------1-----1
ISLA r
I SLAA
I A4
I
I---ox-O*I 2 I
ISLA g
I F8+g:A4
I
1**-oXPO*1 4 I
1
1-----------1---------------1--------------1
1--------1-----1
I
ISLA (gg)
I EO+gg:A4
I
----------1**-oXPO*1 8 I
I
ISLA (ix+d)
I FO+ix:d:A4
I I Cy I (- I 7 (- 0 I <- 0 I**-OXPO*I 12 I
ISLA mem
ISLA (HL+A)
I F3:A4
I
----------1*.*-oXPO*1 16 I
ISLA (mn)
IE3:n:m:A4
I
I**-OXPO* I 12 I
I
ISLA (n)
I E7:n:A4
I
I**-OXPO*I 10 I
I
1-----------1---------------1--------------1-------------------------------1--------1-----1
ISRA r
ISRAA
lAS
I
I---ox-O*I 2 I
I F8+g:AS
I
1**-oxpo*1 4 I
I
I SRA g
1-----------1---------------1--------------1
1--------1-----1
I
ISRA (gg)
I EO+gg:AS
I
------------I **-OXPO* I 8 I
ISRA (ix+d)
IFO+ix:d:AS
I --I 7 -->
0 I --> I CY I 1**-oXPO*1 12 I
I
ISRA mem
ISRA (HL+A)
IF3:AS
I I
------------I **-OXPO* I 16 I
I E3: n:m:AS
I I
1**-oXPO*1 12 I
I
I SRA (mn)
I E7: n:A5
I
I**-oxpo* I 10 I
I
I SRA (n)
I-----------I--~------------I--------------I-------------------------------1--------1-----1
I SLL r
I SLLA
I A6
I
I
I RLL g
I F8+g: A6
I
1-----------1---------------1--------------1
I
I SLL (gg)
IEO+gg:A6
I
----------I
ISLL (ix+d)
IFO+ix:d:A6
I I Cy I (- I 7 <- 0 I <-0
I SLL (HL+A)
I F3: A6
I
----------I SLL mem
IE3:n:m:A6
I
I
1SLL (mn)
I
ISLL (n)
IE7:n:A6
1
Appendix-8
I---ox-O*I 2 I
I**-oxpo* I 4 I
1--------1-----1
1**-oxpo*1 8 I
1**-oxpo*112 I
I**-OXPO* I 16 I
1**-oXPO*1 12 I
1**-oxpo*110 1
Appendix A Table of Machine Instructions
TOSHIBA
Appendix A
Table of Machine Instructions (9/11)
I Instructionl
Mnemonic
I
Code
Function
ISZIIiXVNCI
T
I SRL r
I SRLA
I A7
I---ox-O* I 2
I
ISRL g
IF8+g:A7
I
1**-oXPO*1 4
I
1-----------1---------------1--------------1
1--------1-----1
I
SRL (gg)
IEO+gg:A7
I
------------I**-OXPO*I
8 I
I
SRL (ix+d)
IFO+ix:d:A7
10 -> 17
-->
0 1->1 CY I 1**-oxpo*1 12 I
ISRL mem
SRL (HL+A)
1F3:A7
1
------------I**-OXPO*I 16
I
SRL (mn)
IE3:n:m:A7
I
1**-oxpo*112 I
I
I
SRt (n)
IE7:n:A7
I
I**-OXPO*I 10 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
IRLD (gg)
IEO+gg:I0
I
Areg
memory
I**-OOPO-I 12 I
I
I RLD (ix+d)
I FO+ix: d: 10
I ________
I **-oopo-I 16 I
IRLD mem
IRLD (HL+A)
IF3:10
I
1**-oOPO-120 I
I
IRLD (mn)
IE3:n:m:10
117
413
01
17
413
01 1**-oopo-116 I
I
I RLD (n)
IE 7: n: 10
I ----------1----------- I **-oopo-I 14 I
I
I
I
I
tit
I
I
I
I
1-----------1---------------1--------------1----------=======----=====-----1--------1-----1
I
IRRD (gg)
IEO+gg:ll
I
Areg
memory
1**-OOPo-1 12 I
I
IRRD (ix+d)
IFO+ix:d:ll
I _______
l ___ 1**-oOPO-1 16 I
IRRD mem
IRRD (HL+A)
IF3:11
I
i
I**-oopo-I 20 I
I
IRRD (mu)
IE3:n:m:ll
117
413
01
17
413
01 I**-OOPO-I 16 I
IRRD (n)
IE7:n:ll
I ----------1----------- I**-oopo-I 14 I
I
__
1_ _ +
I
I
I
I
I
I
I
I
I
1
I
1
1
I
r_-__------_--__-_--__-_-l__
l_--_------_-_-_-_-_-_-__
t
8.
Bit manipulation
I Instructionl
Mnemonic
Code
I
Function
I SZIHXVNCI T I
IBIT b,r
IBIT b,g
IF8+g:A8+b
I Z (-"I.g.b
IX*-IXXO-1 4
I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
IBIT b,(gg)
IEO+gg:A8+b
I Z (-"I. (gg).b
IX*-1XXO-1
6 I
IBIT b,(ix+d)
IFO+ix:d:A8+b I Z (_"I. (ix+d).b
IX*-IXXo-110 I
I
IBIT b,mem IBIT b,(HL+A)
1F3+A8+b
I Z (-"I. (HL+A).b
IX*-IXXO-II4 I
IBIT b,(m)
IE3:n:m:A8+b
I Z (-"I. (m).b
IX*-1xxo-1 10 I
I
IBIT b,(n)
IA8+b:n
I Z (-"I. (n).b
IX*-IXXO-1 8 I
I
1-----------1---------------1--------------1-------------------------------1--------1-----1
ISET b,r
ISET b,g
IF8+g:B8+b
I g.b (- 1
1--------1 4 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
ISET b,(gg)
IEO+gg:B8+b
I(gg).b (- 1
1--------110 I
IFO+ix:d:B8+b ICix+d).b (- 1
1--------1 14 I
I
ISET b,(ix+d)
IF3+B8+b
I (HL+A).b (- 1
1--------1 18 I
ISET b,mem ISET b,(HL+A)
IE3:n:m:B8+b
I (un).b (- 1
1--------1 14 I
I
ISET b,(m[d
IB8+b:n
I(n).b (- 1
1--------112 I
I
ISET b,(n)
1-----------1---------------1--------------1-------------------------------1--------1-----1
IRES b,r
IRES b,g
IFB+g:BO+b
I g.b (- 0
1--------1 4 I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
IRES b,(gg)
IEo+gg:BO+b
I(gg).b (- 0
1--------1 10 I
IRES b,(ix+d)
IFO+ix:d:BO+b ICix+d).b (- 0
1--------1 14 I
I
I F3+BO+b
I (HL+A). b (- 0
1--------1 IB
I
I RES b, mem I RES b, (HL+A)
IRES b,(un)
IE3:n:m:BO+b
I(un).b (- 0
1--------1 14 I
I
IRES b,(n)
IBO+b:n
I(n).b <- 0
1--------112 I
I
1-----------1---------------1--------------1-------------------------------1--------1-----1
ITEST b,r
ITEST b,g
IFB+g:18+b
I ... (-"I. g.b
:g.b <-1
IX*-1xXO-1
B I
1-----------1---------------1--------------1-------------------------------1--------1-----1
I
ITEST b,(gg)
IEO+gg:IB+b
I Z (-"I. (gg).b : (gg).b (-I
IX*-IXXO-1 12 I
IFO+ix:d:18+b I Z (-"I. (ix+d).b:(ix+d).b (-I
IX*-IXXo-1 16 I
I
ITEST b,(ix+d)
ITEST b,mem ITEST b,(HL+A)
IF3+18+b
I Z (-"I. (HL+A).b:(HL+A).b (-I
IX*-1xXO-120 I
IE3:n:m:1B+b
I Z (-"I. (un).b :(un).b (-1
IX*-IXXO-116 I
I
ITEST b,(un)
IE7:n:18+b
I Z (-"I. (nLb
:(n).b <-1
IX*-IXXo-1 14 I
I
ITEST b,(n)
Appendix-9
TOSHIBA
Appendix A
9.
Appendix A Table of Machine Instructions
T~ble
of Machine Instructions (10/11)
Jump, call and return
I Instructionl
Mnemonic
I
Code
Function
ISZIHXVNCI T
I
IJP
cc,gg
IE8+gg:CO+cc
IIf ce, PC (- gg
1--------16/8 I (I
IJP
cc,ix+d
IF4+ix:d:CO+cc IIf cc, PC (- ix+d
1--------110/121
bit Symbol
->
->
Initial value after reset
Remarks
-> Read/Write
Appendix-16
TOSHIBA
,)
AEEendix C
Table of Special Function Registers
I/O Port
MSB
i~mbol'
PO
PI
P2
I
I
,
I
Port
0
'Address'
I
I
OFFCOH ,
7
P07
P26
P25
I
P37
P36
R/W
P3S
R/W
1
1
Port
3
OFFC6H I
4
I
I
IOFFC8H I
,
I
I
I
I
I
R
I Ine ut
Port
,
Port
5
I
10FFCAH
I
,
,I
I
I
p8
P27
OFFC4H
I
P7
PIS
2
,
P6
Pl6
Port
I
PS
Pl7
OFFCIH I
I
P4
I
I
I
I
Port
Port
Port
(Note)
5
P05
,
,I
,
Port
,
LSB
6
P06
,
,I
I
P3
Name
6
7
8
, OF~CCH
I
I
I
I
10FFCDH
I
I
I
IOFFDOH
I
,
,I
,I
I
I
I
I
I
I
,I
I
I
I
I
4
P04
3
P03
R/W
Ineut mode
Pl4
Pl3
R/W
Ineut mode
P24
P23
R/W
Ine ut mode
P34
P33
R/W
R
I
InEut
P43
2
P02
POI
0
POO
Pl2
Pll
PlO
P22
P21
P20
P32
R/W
I
P42
P31
P30
R
Ine ut
P40
1
R
Ine ut
P41
R/W
0
PSS
PS4
0
PS3
0
PS2
0
P51
0
PSO
R
Ineut onl~
: Shared with analog input pin (ANO - ANS)
SA60
SA61
W
Undefined
Stepping motor control POl't 0
shifter alternate reg.
SA73
SAll
SA70
SA72
W
Undefined
Stepping motor control Port
shifter alternate reg.
SA63
SA62
,
Read/Write
R/W
Either read or write is possible.
R
Only read is possible.
W
Only write is possible.
Appendix-I7
P63
P62
P61
P60
R/W
InEut mode
Shared with stepping motor
control e ort o (MO)
P73
P72
P70
P7l
R/W
Ineut mode
Shared with stepping motor
control e ort I (M!)
p80
P83
P82
P8l
R/W
R
R
R
0
Ine ut mode
Appendix C Table of Special Function Registers
TOSHIBA
(2)
I/O Port control
I Symbol!
Name
I Address
I
I
I
I POI CR I Port 0/1
IOFFC2H
I (IRFL) Control Reg.1
I
I
I
o
I
I
I
I
I
I
I
I
I
I Port 2
10FFCSH
I Control Reg.1
I
I
I
I
I
I
I
P3CR
5
4
IRFTO
IRFTl
0
o
R
3
Interrupt Request Flag
1. Interrupt being
requested
I
I
I
I
I
I
I
I
Ip2CR
I
I
I
I
I
I
6
IRFO
I
I
I
I Port 3
IOFFC7H
I Control Reg.1
I
I
I
I
I
I
I
I
P27C
P26C
P25C
P24C
P23C
o
2
EXT
PIC
POC
W
W
W
o
o
o
:P1
:PO
:PI-P2
:control :control :control
0: I/O
Port:
1:
0: In
0: In
Address: 1: Out
1: Out
bus
P21C
P20C
P22C
W
o
o
0: In
WAITC1
1: Out
WAITCO
o
R/W
o
o
0
o
0
(I/O selected bit by bit)
ROE
ODE
TXDC 1: TXDCO
R/W
R/W
R/W
o
0
:RD
:P33
Wait control
00: 2 state wait:control :control
01: normal wait :0: RD
:0: CMOS
10: non
wait: for only: 1: Open
11: reserved
: external:
drain:
:access
: 1: Al-
o
P33
OO:Out
01: Out
10: TxD
11:TxD
o
o
RXDCl
RXDCO
R/W
o
0
P32
Out
TxD
Out
P31
OO:In
01: In
10:RxD
o
P30
In
RxD
In
iTS/: 11:
SCLK: Not used
____~I----------_I~----~--------------~:~w~ay~s~R~D~------~--~~--~~~~~~~__~~~
I
I
I
P43C
P42C
P41C
P40C
W
Ip4CR I Port 4
IOFFC9H
o
I
I Control Reg. I
o
o
o
1____~I----------~I~----~~~--~~~~~~~--~~~--~~O~:~Ou~t~(~p~o~r~t~)~l~:~A~d~dr~e~s~s~o~u~tp~u~t~
I
I
I
P73C
P72C
P71C
P70C
P63C
P62C
P61C
P60C
W
Ip67CR I Port 6/7
10FFCEH
W
I
I Control Reg. I
0
0
o
0
0
0
0
1____~I----------~I~----~--~O~:~I~n~--------~I~:~O~u~t------~~~O~:~In~~~~--~~l~:~O~u~t~~~-I
I
I
P830C
ZCE2
ZCE1
EDGE
Ip8CR I Port 8
IOFFD1H
W
W
W
W
I
IControl Reg.1
0
0
0
0
I
I
I
:p83
: INT2/TI5: INTl/TI4: INTO
I
I
I
: contro 1 : contro 1 : contro 1 : cont ro 1
I
I
I
0: P83
1: ZCD : 1: ZCD :0: levell
I
I
I
1: T03/: enable: enable:1: I
I
1____~I__________~I______~____~______~______~______~__~TO~4~:______~______~__~ed~g~e~
Symbol in
denotes another name.
Appendix-18
TOSHIBA
{3)
Appendix C Table of Special Function Registers
Stepping motor control port control
4
3
2
1
0
I
IAddress I
7
Name
6
5
I Symbol I
SM6Ml
SM6MO
P60Cl
P60CO I
P70Cl
P70CO
I
I
I SM7MI : SM7MO
I
R/W______~____~~~--~~~-R~/~W~~--~~--~R~/~W~~--I
R/W
I
I
I____~~
I
0__~___O
0 __~~~
0 __~~~~~~
0
____~~O__~__~O~~~~O~__ I
I
I__~
I
I Stepping
:O:I-step: 00: IN/OUT
I
:O:l-step: 00: IN/OUT
IOFFCBH I
: SMMOD I Motor
: /2-step: 01: IN/OUT,T03
: /2-step: 01: IN/OUT,TOI I
I
I Mode Reg. I
I
: 0: 3: excita-: IX: IN/MO
I
10: IN/Ml
: excita-:
10: 3I
I
(Timer 2,
phase: tion
(Timer 0,
I
I
I
I phase : tion
Timer 3)
: 1: 4: 1: 1-2
Timer 1)
I
:1:1-2
11: 4I
I
step
11: " (Timer 4): phase
step
I
I
I
I phase
excita-:
excita-:
I
I
I
I
tion
tion
I
I
I
I
----~----------+-----~------~~~--~--------~C~~7~~------~~~~--------~C~~~6~1
I
I
I
R/w
R/w
I
I
I
I
o
0
I
I
I
I Stepping
:O:Normal:
:O:Normall
SMCR I Motor
IOFFCFH I
:rotation:
:rotation/
I Control Reg. I
I
: 1: Re: 1: Re- I
I
I
I
:verse
:verse
I
I
I
I
:rotation:
:rotationl
I
I
I
Also refer to P67CR, P6 and P7 registers.
:4)
Watchdog timer control
LSB
MSB
IAddressi
7
0
5
4
3
2
6
EXF
DRVE
WDTPI
WDTPO
WARM
HALTMI
HALTMO
I
I
I WDTE
R/W
R/W
R/W
R/W
R
I
I
I R/W
UnO
0
0
0
0
1
0
I
I
I
defined:
I Watchdog
I
I
WDMOD I Timer
: Invert : 1:
Detecting time : Warming-: Standby mode
IOFFD2H I
:up time : 00: RUN
mode :each
: to drive I
I Mode Reg. I
I
14
00: 2l6 /fc
I
I
I 1 : WDT
:
14
: 01: STOP mode :time EXX:pin in I
:0:2 /fc: 10: IDLEI mode : instruc-: STOP
I
I
I
I Enable: 01: 2IS/fc
16
:1:2 Ifc: 11 : IDLE2 mode :tion is :mode.
10: 220/ fc
I
I
I
I
:executed:
11: 2 /fc
I
I
I
I
WDCR I Watchdog
IOFFD3H I
I
W
I
I
I
I Timer
I Control Reg.1
I
I
BlH: WDT Disable code
4EH: WDT Clear code
I
I
I
I
51mboll
Name
Appendix-19
Appendix C Table of Special Function Registers
TOSHIBA
(5)
Timer/event counter control
I 51mbol
I
I TREGO
I
I
ITREGI
I
I
ITREG2
I
I
I TREG3
I
I
I
I
ITCLl(
I
I
I
I
I
I
I
ITFFCR
I
I
I
I
I
I
ITHOD
I
I
I
I
I
Name
I Address
8-bit Timer I
Register 0 IOFFD4H
I
8-bit Timer I
Register 1 IOFFD5H
I
8-bit Timer I
Register 2 IOFFD6H
I
8-bit Timer I
Register 3 IOFFD7H
I
I
I
8-bit Timer I
ISource cloc~loFFD8H
I Control Reg. I
I
I
I
I
I
I
I
I
I
I
I 8-bit Timer I
I Flip-Flop IOFFD9H
IControl Reg.1
I
I
I
I
8-bit Timerl
Mode Reg.
IOFFDAH
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
6
5
4
2
0
W
Undefined
W
Undefined
W
Undefined
W
Undefined
nCLKI : T3CLKO
T2CLKI : T2CLKO
TlCLKI : TlCLKO
TOCLKI : TOCLKO
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
8-bit
8-bit
00:
00:
T02TRG
00:
01:
00:
TOOTRG
01:
~Tl
~Tl
01:
10:
tiT 1
01:
10:
~Tl6
\fITl
~Tl6
10: .Tl6
11: .T256
10:
11: ~T256
t>Tl6
11: ~T256
:(8-bit mode onll):
11: ~T256
: (8- bi t mode onl:z
TFF3C 1 : TFF3CO
TFF3IE : TFFJIS
TFFIC 1 : TFFICO
TFFUE : TFFlIS
W
W
R/W
R/W
0
0
0
0
00: Clear TFF3 : 1: TFF3 :0:
00: Clear TFFl : 1: TFFI :0:
01: Set
TFFJ
Invert : Invert
01: Set
TFFl
Invert : Invert
10: Invert TFFJ
Enable : by 8-bit: 10: Invert TFFl
Enable :by 8-bi
11: Don't care
: timer 2
11: Don't care
:timer C
T23Ml : T23MO
TWM21
: PWM20
TI0Ml : TlOMO
PWMOI
PWMOC
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
00: 8-bit Timer
PWM Freq uency
00: 8-bit Timer
PWM Frequency
01: 16-bit Timer: 00:
01: 16-bit Timer: 00:
6
6
10: 8-bit PPG
2 -1
01:
10: 8-bit PPG
01:
2 -1
27 -1
11: 8-bit PWM
10: 27 -1
11: 8-bit PWM
10:
8
8
11: 2 -1
11: 2 -1
Appendix-20
Appendix C Table of Special Function Registers
TOSHIBA
I Symbol I
Name
I Address I
6
5
4
3
2
0
BRATEO
PRRUN
T4RUN
T3RUN
T2RUN
T1 RUN
TORU~
I
I
I
I BRATE1
I
18-bit Timer/I
I---~~-R~/W~~~~~~----~~--~~~--R~/~W~~----~~~--~~-I
1 TRUN
1
I
I
I
iCAPIL
1 Serial
1
1 Channel
IOFFDBH
1 Baud Rate 1
1Control Reg.1
1
1
116-bit Timerl
I/Event
IOFFDCH
1
1 Counter
Capture
1
0
0
0
0
0
0
0
0
1-0~0~:~3~0~0~/~15~0~b-a-ud~:~~P~r-es-c-a~l-e-r~&~T~i~m~e-r~Ru~n-/~S~t~o-p-C~o~n-t-r-o~1--~--~--~----
1 01:1200/600
1 10:4800/2400
1 11: 19200/9600
1
0:
1:
Stop & Clear
Run (Count up)
--------------------------------R-------------------------------
1I______~I--------------------------~Un~d~e~f~i~n~e~d--------------------------1_______________________________________________________________
CAPIH 1 Register
IOFFDDH I__________________________~~~R~~--------------------------1
1
I
Undefined
'16-bit Timerl
, _____________________________________________________________
CAP2L I/Event
I Counter
'Capture
IOFFDEH I__________________________~~~R~~--------------------------1I_______~,--------------------------~Un-d-e~f~i~n~e-d--------------------------, _____________________________________________________________
CAP2H 1 Regi s t er 2 1OFFDFH I___________________________~R~--------------------------1
1
1
Undefined
1
1
1
TREG4LI16-bit TimerlOFFEOH I----------------------------~W~---------------------------I/Event
1_____~I-------------------------~Un~d~e~f~i~n~e~d-------------------------1 Counter
1
I______________________________~-----------------------------TRE~HI Register 4 IOFFEIH I_________________________~~~W~~-----------------------1
1
1
Undefined
I
1
, _____________________________________________________
TREG5LI16-bit TimeriOFFE2H I__________________________~~~W~~-------------------------I/Event
11______~I--------------------------~U-nd-e~f~i~n~e~d--------------------------I Counter
1__________________________________________________________
TREG5HI Register
1
IOFFE3H I___________________________~~W~~-------------------------_
1
1
. Undefined
Appendix-21
Appendix C
TOSHIBA
I Symbo 11
Name
I Address
I
I
I
I
I
I T4MOD
I
I
I
I
I
I 16-bit Timer I
1/ Event
IOFFE4H
I Counter
I
I Mode Reg. I
I
I
I
I
I
I
I
I
I
I
I
I
I
7
I
I
I 16-bit Timer I
T4FFCRIFIip-Flop 4 IOFFE5H
I
IControl Reg.1
I
I
I
I
I
I
I
I
(6)
I
6
Table of Special Function Registers
5'
CAPlIN
W
4
CAPMl
3
CAPMO
R/W
0
0
Capture timing
2
CLE
R/W
0
1
T4CLKl
0
T4CLKO
R/W
0
0
Timer 4 source
clock
:0: Soft-: 00: Disable
1:
00: T14
: ware
01 : T14 t TI5
UC16
01: ..e-Tl
: Capture: 10: TI4 + T14 ~
Clear
10: .e-Tl6
: 1: Don't: 11: TFF! t TFF! ~ : Enable: 11:
care
CAPITE : EQ5TE
EQ4TE
TFF4Cl
TFF4CO
CAP2TE
W
R/W.
0
0
0
0
TFF 4 inversion trigger
0: Disable trigger
00: Clear TFF4
TFF4
01 : Set
1: Enab Ie trigger
10: Invert TFF4
11: Don't care
Serial channel control
IS~bol
Name
I
~
I
I
ISCMOD
SCCR
SCBUF
Serial
Channel
Mode Reg.
Serial
Channel
Control
Register
Serial
Channel
Buffer
Register
I Address I
7
6
5
4
3
0
2
: Fixed at: RXE
WU
SMI
SMO
SCI
SCO
I
I !BS
"0"
I
I
R/W
I
I
IUndefined
0
0
0
0
0
0
0
I
IOFFE9H ITrans: 1:
: 1:
00:1/0 interface: 00: T02TRG
U
Imission
Receive: Wake up: 01: UART 7-bit
01: BR
A
I
IBit-8
Enable
Enable
10: UART 8-bit
10: 01
R
I
11: UART 9-bit
I data in
11: BR 1/2
T
I
19-bit
I
IUART
I
EVEN
PE
OERR
PERR
FERR
CTSE
I
I RBS
R/W
R
R(Cleared to "0" bI reading)
R/W
I
I
10FFEAH I Undefined
0
0
0
0
0
0
I Receiv- : Parity : 1:
1: Error
: 1: CTS
I
ling Bit-: 0: Odd : Parity .----------------------------.
Enable
I
18 data
1 : Even: Enable
Overrun: ParitI : Flaming
I
RB6
RB5
RB4
RB3
RB2
RBI
RBO
I
I RB7
10FFEBH I TB7
TB4
TB6
TB5
TB3
TB2
IBl
IBO
R (Receiving)/W (Transmission)
I
I
Undefined
I
I
Also refer to P3CR, TRUN register.
(Note)
Appendix-22
BR:
Baud Rate Generator
TOSHIBA
.7)
Appendix C Table of Special Function Registers
AID Converter control
1
MSB
LSB
1Address 1 7
6
2
o
3
4
5
1
1______~__E~0~C_F__~~AD~B-F----~AD~C-S----~AD~S~----AD-C-H~2~--A~D~C~H~l----A~D-C~H~O-1
1
R
R/W
R/w
R/W
10FFEFH I------~--~O--~~-O----~~O~~--~O~--~~O~----~O~----~O~-1
1
1: END
1: Busy: 0: 95s :1: Start: Analog Input Channel
1
,
1:190s
Select
1
1
Symbol 1
Name
1
1 AID
ADMOD 1 Converter
1 Mode Reg.
, A/D Result 1
,
'OFFEEH I--------------------------R---------------------------------ADREG 1 Register
8)
1
Interrupt control
Symbol I
Name
1
INTEL 1 Interrupt
1 Enable
1 Mask Reg.
1
INTEH 1............
(DMA 1
EL)' Mic ro DMA
-----I Enable
DMAEH 1 Register
,
1
1
1
,
IRFL I
(P01-'
CR)I
,
,
I
IRFH
,
,
I
I
I
I
'I--~O---~O~--~O~---~O~---~O~--~O~--~O~----O~--
1
1: Enable
0: Disable
1________~I_R~FO_____IR~F~T~O____I_R_FT~l~__________E~XT~----~P~lC-R--~~P_O_C_R__
1
, _ _ _ _~_ _ _ _~R~______~____~__~W~~_____~W~_____
I'
0
0
0
0
0
0
IOFFC2H 1------~--I~n~t-e-r-ru~p-t~R-e-q-ue~s~t~F.;;.I-ag--~------~-P~l~.P~2--~P~1~--~-P~0~~
Interrupt 1
I
:Controls: Control: Controll
Request
1
1: Interrupt being re0:1/0
0: In
0: In 1
Flag 0:
I
quested
port: 1: Out
1: Out I
IRF'
1: Ad- :
,
Clear'
dress:'
I______+I__~--~__-=----~~----~~--~------~ b~u~s~~~----~--__--I
"IRFT2
IRFT3: IRFT4
IRFl
IRFT5
IRF2
IRFRX
IRFTX'
I'
R (Only IRF Clear code can be used to write.)
1
IOFFC3H 1 0
0
0
0
0
0
0
I
" 1 : Interrupt being requested (IRF is cleared to "0" by writing
I
IRF Clear code.)
,
"
1
I
__
Symbol in
9)
1Address 1
6
5
4
3
2
0
' __*_I~E~T~2~__I~E~T~3_____I~E_T~4_____I~E~1~~~I-ET~5~----IE~2~____I_E~RX
______I_E~T~X__
1
IOFFE6H I____________________________~R~/~W__~------~-----------------1
I__~O~__~~O~__~~O____~~O__~__~O__~~-O~--~~O~--~~O~-1______+I__________~l~:~E~na~b~l~e~~--~~~--~~O~:~D~i~s~a~b~le~----~~----~~-' 1 __________D_E~O__~~D~E-T~O-----D-E-T~l-----A-DI-S------IE-O--~~-IE-T~O_____I_E~T~l__
loFFE7H I____________~R~/~W____________~__~------~~R~/~W------------~
1
I_...;;O_~~~O-~-...;;O~~-:--~O~.--.;;-....;O~..,......;~_:O~--.;-....;O~-.:~-O~-, ______+1__~~1_:~En;.:.;a;;.;b~l~e----~~O~:~D~i~s~a~b.;;.le~~--=-~~l~:--.;;;E~n~ab~l~e----~~O~:~D.;;..is~a;;.;b~l~e~
I
1__~D~E~T~2__~D_E~T~3____~D~E_T_4_____D~E~1~~~D-ET.;;..5----~DE-2~____D_E~RX~~__D_E_T_X__
IOFFE8H'
R/W
) denotes another name.
*
Share with lEAD (If ADIS=l. use as INTAD Mask Reg.)
Bank register
Symbol 1
BX I
BY
I
I
I
I
I
Name
IAddress'
:::~ster
X \OFFECH
:::~ster
Y \OFFEDH
I
I
7
6
5
4
3
0
2
\=======~=======~=======~======~~=~B:X3~==~==:BX:2~=~R~/~W=B:X~l~==~==B:X:O~==
I
0
0
0
0
:=======================:==========~:3:======~~2:=~RZ/~W=B=Y;l======B~Y~O=~
I
0
Appendix-23
0
0
0
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:10:25 08:09:11-08:00 Modify Date : 2013:10:25 18:18:56-07:00 Metadata Date : 2013:10:25 18:18:56-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:97ac79a6-049b-4411-9722-b29592ac2363 Instance ID : uuid:2ebb3b83-3122-4df5-a8a8-a310b15d6b3a Page Layout : SinglePage Page Mode : UseNone Page Count : 364EXIF Metadata provided by EXIF.tools