1988_U71_8 Bit_Single_Chip_Microcomputer_Data_Book 1988 U71 8 Bit Single Chip Microcomputer Data Book
User Manual: 1988_U71_8-bit_Single_Chip_Microcomputer_Data_Book
Open the PDF directly: View PDF 
.
Page Count: 971
| Download | |
| Open PDF In Browser | View PDF |
8-BIT SINGLE CHIP
MICROCOMPUTER DATA BOOK
#U71
~HITACHI®
MEDICAL APPLICATIONS
Hitachi's products are not authorized for use in MEDICAL APPLICATIONS,
including, but not limited to, use in life support devices without the written
consent of the appropriate officer of Hitachi's sales company. Buyers of
Hitachi's products are requested to notify Hitachi's sales offices when planning
to use the products in MEDICAL APPLICATIONS.
When using this manual, the reader should keep the following in mind:
1. This manual may, wholly or partially, be subject to change without notice.
2.
All rights reserved: No one is permitted to reproduce or duplicate, in any
form, the whole or part of this manual without Hitachi's permission.
3. Hitachi will not be responsible for any damage to the user that may result
from accidents or any other reasons during operation of his unit according
to this manual.
4. This manual neither ensures the enforcement of any industrial properties
or other rights, nor sanctions the enforcement right thereof.
5.
Circuitry and other examples described herein are meant merely to indicate characteristics and performance of Hitachi semiconductor-applied
products. Hitachi assumes no responsibility for any patent infringements
or other problems resulting from applications based on the examples
described herein.
6.
No license is granted by implication or otherwise under any patents or
other rights of any third party or Hitachi, Ltd.
February 1988
©Copyright 1985, 1988, Hitachi America Ltd.
Printed in U.S.A.
CONTENTS
• GENERAL INFORMATION
•
•
•
•
•
•
Quick Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Introduction of Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Quality Assurance .....................................................................................
Reliability Test Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . ..
Design Procedure and Support Tools for 8-bit Single-chip Microcomputers . . . . . . . . . . . . . . . . . . . . . . . . . ..
7
17
26
32
38
DATA SHEETS
HD6801S0
HD6801Ss
HD6801VO
HD6801Vs
HD6803
HD6803·1
HD6805S1
HD6805S6
HD6805T2
HD6805U1
HD6805Vl
HD6805Wl
HD6301Vl
HD63AOIVI
HD63BOIVI
HD6301XO
HD63AOIXO
HD63B01XO
HD6301YO
HD63AOIYO
HD63BOIYO
HD6303R
HD63A03R
HD63B03R
HD6303X
HD63A03X
HD63B03X
HD6303Y
HD63A03Y
HD63B03Y
HD6305UO
HD63AOsUO
HD63B05UO
HD630sVO
HD63AOsVO
HD63BOsVO
HD6305XO
HD63AOsXO
HD63BOsXO
HD630sXl
HD63A05X1
HD63BOsX1
HD6305X2
HD63A05X2
HD63B05X2
HD6305YO
HD63A05YO
HD63B05YO
HD6305Yl
HD63A05Yl
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . .. 43
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 43
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 77
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 77
Micro Processing Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............. 111
Micro Processing Unit (NMOS) ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............. 111
Microcomputer Unit (NMOS) .................................................. 138
Microcomputer Unit (NMOS) .. '.' .............................................. 158
Microcomputer Unit with PLL Logic (NMOS) ........................................ 178
Microcomputer Unit (NMOS) .................................................. 209
Microcomputer Unit (NMOS) .................................................. 230
Microcomputer Unit (NMOS) .................................................. 251
Microcomputer Unit (CMOS) .................................................. 279
Microcomputer Unit (CMOS) . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . ................ 279
Microcomputer Unit (CMOS) .................................................. 279
Microcomputer Unit (CMOS) .................................................. 319
Microcomputer Unit (CMOS) .................................................. 319
Microcomputer Unit (CMOS) .................................................. 319
Microcomputer Unit (CMOS) .................................................. 358
Microcomputer Unit (CMOS) .................................................. 358
Microcomputer Unit (CMOS) .................................................. 358
Micro Processing Unit (CMOS) ................................................. 406
Micro Processing Unit (CMOS) ................................................. 406
Micro Processing Unit (CMOS) ................................................. 406
Micro Processing Unit (CMOS) ................................................. 440
Micro Processing Unit (CMOS) ................................................. 440
Micro Processing Unit (CMOS) ................................................. 440
Micro Processing Unit (CMOS) ................................................. 477
Micro Processing Unit (CMOS) ................................ . ................ 477
Micro Processing Unit (CMOS) ................................................. 477
Microcomputer Unit (CMOS) .................................................. 520
Microcomputer Unit (CMOS) .................................................. 520
Microcomputer Unit (CMOS) .................................................. 520
Microcomputer Unit (CMOS) .................................................. 546
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............. 546
Microcomputer Unit (CMOS) .................................................. 546
Microcomputer Unit (CMOS) .................................................. 572
Microcomputer Unit (CMOS) .................................................. 572
Microcomputer Unit (CMOS) ............................•..................... 572
Microcomputer Unit (CMOS) .................................................. 599
Microcomputer Unit (CMOS) .................................................. 599
Microcomputer Unit (CMOS) .................................................. 599
Microcomputer Unit (CMOS) .................................................. 599
Microcomputer Unit (CMOS) .................................................. 599
Microcomputer Unit (CMOS) .................................................. 599
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 628
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 628
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Microcomputer Unit (CMOS) .................................................. 655
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD63B05Yl
HD6305Y2
HD63A05Y2
HD63B05Y2
HD63L05Fl
HD63L05EO
HD68POIV07
HD68PO 1V07-1
HD68POIMO
HD68POIMO-l
HD68P05V07
HD68P05MO
HD68P05WO
HD63POIMI
HD63PAOIMI
HD63PBOlMl
HD63P05YO
HD63PA05YO
HD63PB05YO
HD63P05Yl
HD63PA05Yl
HD63PB05Yl
HD63701VO
HD637AOIVO
HD637BOIVO
HD63701XO
HD637AOIXO
HD637BOIXO
HD63705VO
HD637A05VO
HD637B05VO
•
•
Microcomputer Unit (CMOS) '" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Microcomputer Unit (CMOS) ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 655
Microcomputer Unit (CMOS) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Microcomputer Unit (CMOS) ..... . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
Evaluation Chip for HD63L05FI (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 715
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 717
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
Microcomputer Unit (NMOS) .......................................................... 756
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " 778
Microcomputer Unit (CMOS) ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 807
Microcomputer Unit (CMOS) ... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
Microcomputer Unit (CMOS) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Microcomputer Unit (CMOS) .......................................................... 950
INTRODUCTION OF THE RELATED DEVICES
• 8/16-bit Multi-chip Microcomputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• 4-bit Single-chip Microcomputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• IC Memory ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• LCD Driver Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• Gate Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• CODEC/Filter Combo LSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• Speech Synthesis LSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
955
957
961
964
966
968
968
HITACHI SALES OFFICE LOCATIONS . ................................................................. 969
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
GENERAL
INFORMATION
•
•
•
•
•
Quick Reference Guide
I ntroduction of Packages
Reliability and Quality Assurance
Reliability Test Data of Microcomputer
Design Procedure and Support Tools
for 8-bit Single-chip Microcomputer
QUICK REFERENCE GUIDE
• NMOS 8-BIT SINGLE-CHIP MICROCOMPUTER HD6801 SERIES
HD6801S0
HD6801S5
HD6801VO
HD6801V5
Bus Timing (MHz)
1.011.25
1.0/1.25
Supply Voltage (V)
5.0
5.0
5.0
0-+70
0-+70
0- +70
DP-40
DP-40
DP-40
2
4
-
128
128
128
Type No.
LSI
Characteristics
Operating Temperature * (oC)
Package
Memory
ROM (k byte)
RAM (byte)
Functions
1.0/1.25
29
29
13
External
2
2
2
Soft
1
1
1
Timer
3
3
3
1
1
I/O Port
Interrupt
HD6803
HD6803-1
Serial
• Free running counter
• Output compare register
• Input capture register
Timer
1
16-bit x 1
16-bit x 1
16-bit x 1
Full double step·stop type
SCI
External Memory Expansion
• Address/data non-multiple mode
(256 bytes)
• Address/data multiple mode
(65k bytes)
Clock Pulse Generator
• Address/data
multiple mode
(65k bytes)
Built-in (External clock useable)
Yes (64 bytes)
Built-in RAM Holding
EP ROM on the Package Type * *
HD68P01V07
HD68P01V07-1
Compatibil ity
MC68D1
MC6801·1
Reference Page
43
HD68P01V07
HD68P01V07-1
-
MC6803
MC6803-1
77
111
• Wide Temperature Range (-40 - +85°C) version is available .
•• HD68P01MO and HD68P01MO-1 are useable.
~HITACHI
Hitachi America Ltd_ • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
7
QUICK REFERENCE GUIDE - - - - - - - - - - - - - - - - - - - - - - - - - -
• NMOS 8-BIT SINGLE-CHIP MICROCOMPUTER HD6805 SERIES
Type No.
HD6805S1
HD6805S6
1.0
1.0
1.0
5.25
5.25
5.25
0-+70
0-+70
0-+70
DP-28
DP-28
DP-40
ROM (k byte)
1.1
1.8
2
RAM (byte)
64
64
96
Clock Frequency (MHz)
Supply Voltage (V)
LSI
Characteristics
Operating Temperature** (OC)
Package
Memory
I/O Port
I/O Port
Nesting
Interrupt
Functions
I
I
20
Input Port
20
-
6
I
I
20
20
-
HD6805Ul
32
I
I
6
6
External
1
1
1
Soft
1
1
1
Timer
1
1
1
24
8
Timer
• 8-bit timer with 7-bit prescaler
• Event counter
Clock Pulse Generator
• Resistor
• Crystal
Low-voltage Automatic Reset (LV I)
Self-check Mode
Yes
Yes
Yes
Available
Available
Available
-
-
HD68P05V07
MC6805P2
138
MC6805P6
158
209
Other Features
EPROM on the Package Type
Compatibility
Reference Page
-
* Preliminary
** Wide Temperature Range (-40 - +85°C) version is available.
8
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - Q U I C K REFERENCE GUIDE
HD6805V1
HD6805T2*
1.0
1.0
1.0
5.25
5.25
5.25
0-+70
0-+70
0-+70
DP-40
DP-28
DP-40
4
2.5
4
96
64
96
I
I
32
l
24
8
6
19
I
19
-
HD6805W1
29
l
l
6
12
1
1
2
1
1
1
1
1
4
23
6
• 8-bit timer
with 7-bit
prescaler
• Event counter
.8-bit
comparator
• Crystal
Yes
Yes
Yes
Available
Available
PLL logic
for RF
synthesizer
Available
HD68P05V07
-
230
-
MC6805T2
178
• 8-bit x
4-channel
internal
AID converter
.8 bytes of
standby RAM
HD68P05WO
251
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
9
QUICK REFERENCE GUIDE - - - - - - - - - - - - - - - - - - - - - - - - • CMOS 8·BIT SINGLE·CHIP MICROCOMPUTER HD6301 SERIES
Type No.
Bus Timing (MHz)
LSI
Characteristics
HD6301Vl
HD63A01Vl
HD63B01Vl
HD6301XO
HD63A01XO
HD63B01XO
1.0 (HD6301Vl)
1.5 (HD63A01V1)
2.0 (HD63B01Vl)
1.0 (HD6301XO)
1.5 (H D63AOl XO)
2.0 (HD63B01XO)
Supply Voltage (V)
5.0
Operating Temperature***(oC)
Package
DP-40, FP·54, CG-40
ROM (k byte)
Memory
RAM (byte)
Input Port
4
128
192
Functions
2
2
2
Timer
3
4
SCI
External Memory Expansion
10
3
1
1
16-bit xl
( Free running counter X l )
Output compare register x 1
I nput capture register xl
16·bit x 1
(Free running counter X l )
Output compare register x2
Input capture register xl
8-bit x 1
( 8-bit up counter X l )
Time constant register x 1
Asynchronous
Asynchronous/Synchronous
65k bytes
65k bytes
-Error detection
-Low power consumption
modes (sleep and standby)
-Error detection
-Low power consumption
modes (sleep and standby)
-Slow memory interface
-Halt
HD63P01Ml
HD63PA01Ml"
HD63PB01Ml"
H D63701 vot' •
HD637AOlVO t **
HD637BOl vot"
279
Reference Page
8
21
External
Timer
• Preliminary
•• Under development
tEPROM on-chip type
53
Soft
Serial
Other Features
24
29
29
Output Port
Interrupt
DP-64S, FP-80
4
I/O Port
I/O Port
EPROM on the Package Type
(EPROM On-Chip Type)
5.0
0-+70
0- +70
HD63701XOt *
HD637A01XOt"
HD637BOl XO t"
319
••• Wide Temperature Range (-40 - +85°C) version is available.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - Q U I C K REFERENCE GUIDE
HD6301YO
HD63A01YO
HD63B01YO
HD6303R
HD63A03R
HD63B03R
HD6303X
HD63A03X
HD63B03X
HD6303Y
HD63A03Y
HD63B03Y
1.0 (HD6301YO)
1.5 (HD63A01YO)
2.0 (HD63B01YO)
1.0 (HD6303R)
1.5 (HD63A03R)
2.0 (HD63B03R)
1.0 (HD6303X)
1.5 (HD63A03X)
2.0 (HD63B03XI
1.0 (HD6303Y)
1.5 (HD63A03Y)
2.0 (HD63B03Y)
5.0
0-+70
DP-64S
5.0
5.0
5.0
0-+70
0-+70
0-+70
DP-64S, FP-80
DP-64S
DP-40, FP-54, CG-40
16
-
-
-
256
128
192
256
-
16
13
48
53
-
13
5
24
8
24
-
24
-
-
-
3
2
3
3
2
2
2
2
4
3
4
4
1
1
1
1
16-bit xl
(Free running counter X l )
Output compare register x 2
I nput capture register x 1
8-bit xl
(8-bit up counter X l )
Time constant register x 1
16-bit x 1
Input capture register x 1
16-bit xl
(Free running counter X l )
Output compare register x 2
Input capture register x 1
8-bit xl
( 8-bit up counter X l )
Time constant register xl.
16-bit x 1
(Free running counter X l )
Output compare register x 2
Input capture register x 1
8-bit x 1
(8-bit up counter X l )
Time constant register x 1
Asynchronous/Synchronous
Asynchronous
Asynchronous/Synchronous
Asynchronous/Synchronous
65k bytes
65k bytes
65k bytes
65k bytes
eError detection
-Low power consumption
modes (sleep and standby)
-Slow memory interface
-Halt
eError detection
-Low power consumption
mode~ (sleep and standby)
eError detection
-Low power consumption
modes (sleep and standby)
-Slow memory interface
-Halt
eError detection
-Low power consumption
modes (sleep and standby)
-Slow memory interface
-Halt
440
417
358
1
("""unn;n.
roun'" x,
Output compare ~egister x 1
406
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
11
QUICK REFERENCE GUIDE - - - - - - - - - - - - - - - - - - - - - - - - - -
• CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER HD6305 SERIES
Type No.
Clock Frequency (MHz)
LSI
Characteristics
Supply Voltage
HD6305UO*
HD63A05UO*
HD63B05UO*
HD6305VO*
HD63A05VO*
HD63B05VO*
HD6305XO
HD63A05XO
HD63B05XO
1.0 (HD6305UO)
1.5 (HD63A05UO)
2.0 (HD63B05UO)
1.0 (HD6305VO)
1.5 (HD63A05VO)
2.0 (HD63B05VO)
1.0 (HD6305XO)
1.5 (HD63A05XO)
2.0 (HD63B05XO)
(V)
Operating Temperature *** (DC)
Package
5.0
5.0
S.O
0-+70
0-+70
0-+70
DP·40
DP·64S. Fp·64
DP·40
Memory
ROM
(k byte)
RAM
(byte)
2
4
4
128
192
128
31
I/O Port
Input Port
I/O Port
-
31
Interrupt
-
7
55
-
-
Output Port
32
31
31
16
External
2
2
Soft
1
1
1
Timer
2
2
2
Serial
1
1
1
-
-
-
2
Functions
Timer
SCI
External Memory Expansion
Other Features
H D63705VOt··
HD637A05VOt··
HD637BOSVOt· •
EPROM on the Package Type
(EPROM On·Chip Type)
Evaluation Ch ip
Reference Page
• Preliminary •• Under development
t EPROM on-chip type
12
-
-
520
546
HD63P05YO
HD63PA05YO
HD63PB05YO
572
••• Wide Temperature Range (-40 - +85 OCt version is available.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - QUICK REFERENCE GUIDE
HD6305X1
HD63A05X1
HD63B05X1
HD6305X2
HD63A05X2
HD63B05X2
HD6305YO
HD63A05YO
HD63B05YO
HD6305Y1
HD63A05Y1
HD63B05Y1
HD6305Y2
HD63A05Y2
HD63B05Y2
1.0 (H D6305X 1)
1.5 (HD63A05X1)
2.0 (HD63B05X1)
1.0 (HD6305X2)
1.5 (H D63A05X2)
2.0 (HD63B05X2)
1.0 (HD6305YO)
1.5 (HD63A05YO)
2.0 (HD63B05YO)
1.0 (HD6305Y1)
1.5 (HD63A05Y1)
2.0 (HD63B05Y1)
1.0 (HD6305Y2)
1.5 (HD63A05Y2)
2.0 (HD63B05Y2)
HD63L05F1
0.1
5.0
5.0
5.0
5.0
5.0
3.0
0-+70
0-+70
0-+70
0- +70
0-+70
-20- +75
DP-64S, FP-64
DP·64S, FP-64
DP-64S, FP-64
DP-64S, FP-64
DP-64S, FP-64
DP-64S, FP-80
4
-
8
8
-
4
128
128
256
256
256
96
24
7
31
24
31
7
-
32
55
24
31
7
-
7
24
-
20
-
-
16
20
7
31
(19)
2
2
2
2
2
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
1
1
e8-bit x 1 (with
7-bit prescaler)
- 8-bit x 1 (with 7 -bit prescaler)
- 15-bit x 1 (combined with SCI)
-
Synchronous
12k bytes
16k bytes
- Low power consumption modes
(Wait, stop and standby)
HD63P05Y1*
HD63PA05Y1 *
H D63PB05Y 1*
-
-
8 k bytes
-
16k bytes
-8-bit AID converter
-LCD driver
(6 x 7 segment)
e Low power consumption modes
(Standby and halt)
HD63P05YO
HD63PA05YO
HD63PB05YO
HD63P05Y1 *
HD63PA05Y1 *
HD63PB05Y1 *
-
-
-
-
-
-
599
599
628
655
655
HD63L05EO
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
684
13
QUICK REFERENCE G U I D E - - - - - - - - - - - - - - - - - - - - - - - - - • NMOS 8·BIT SINGLE·CHIP MICROCOMPUTER EPROM ON THE PACKAGE TYPE
HD68P01V07 HD68P01V07-1
Type No.
LSI
Characteristics
I Supply Voltage
IOperating Temperature
HD68P01MO-1
HD68P05V07
HD68P05MO
5.0
5.0
(oC)
0-+70
0- +70
I Package
DC-40P
DC-40P
HD6801S0
HD6801VO
Equivalent Device
Mount~ble
HD68P01MO
(V)
EPROM
Reference Page
,HD6801S5
HD6801V5
-
-
HD6805U1
HD6805V1
HN482732 A-30
HN482732A-30
HN482764-3
HN482764-3
HN482732A-30
717
717
717
717
756
HN482764-3
756
• CMOS 8·BIT SINGLE·CHIP MICROCOMPUTER EPROM ON THE PACKAGE TYPE
Type No.
HD63P01M1
l
Supply Voltage
LSI
Characteristics 10perating Temperature
HD63PA01M1· HD63PB01Ml· HD63P05YO
HD63PA05YO
(V)
5.0
(OC)
0-+70
0-+70
DC-40P
DC-64SP
IPackage
Equivalent Device
HD6301V1
Mountable EPROM
Reference Page
HD63PB05YO
5.0
HD63A01V1
HD63B01V1
HD6305XO
HD6305YO
HD63A05XO
HD63A05YO
HD63B05XO
HD63B05YO
HN482732 ... ·30
HN482784·3
HN27C84·30
HN482732 ... ·25
HN482784
HN27C84·25
HN482732 ... ·30
HN482784·3
HN27C84·30
HN482732 ... ·30
HN482784·3
HN27C84·30
HN482732 ... ·25
HN482764
HN27C84·25
HN482732 ... ·30
HN482784·3
HN27C84·30
807
807
807
847
847
847
• CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER EPROM ON-CHIP TYPE
HD6370lVO
Type No.
Clock Frequency (MHz)
LSI
Characteristics
Supply Voltage (V)
Package
Memory
1/0 Port
1/0 Port
Input Port
Output Port
Functions
Interrupt
29
1.0,1.5,2.0
5.0
5.0
5.0
DC-40
DC-64S
DP-64S
DC-40
4
4
4
192
192
192
I
I
j
29
-
53
-
I
I
I
24
8
21
I
I
I
3
2
2
1
Timer
3
4
2
External Memory
Expansion
Others
1
1
1
16 bit xl
16 bit xl
8 bit xl
8 bit xl
UART
UART
synchronous
EPROM
Programming
-
-
Synchronous
Possible (65k byte)
Possible (65k byte)
-
• Error detection
• Low power consumption modes (Sleep and
• Error detection
• Low power consumption modes (Sleep and
Standby)
• Slow memory interface
• Low power consumption modes
(Wait, Stop and Standby)
27C256, 27256
2732A
27C256, 27256
(Vpp = 12.5V)
High Performance Pro·
gramming algorithm
available
(Vpp = 21V)
(Vpp = 12.5V)
High Performance Programming algorithm
available
Standby)
Equivalent EPROM Type
31
2
2
Serial 1/0
Hitachi
(under development)
H67PWA01A
H67PWA01B
H35VSAOOA
H35VSAOOB
Data 1/0
-
HD63701 XO
(for 29A/29B)
HD63705V
(for 29A/29B)
904
904
• Preliminary
14
31
External
Serial
Reference Page
HD63705VO * *
Soft
Timer
Socket
Adapter
*
HD63701XO
1.0,1.5,2.0
EPROM (k byte)
RAM (byte)
**
1.0,1.5,2.0
904
•• Under development
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - QUICK REFERENCE GUIDE
HD68P05WO
5.0
0- +70
DC·40P
HD6805W1
HN482732A·30
HN482764·3
778
HD63P05Y1*,
H D63PA05Y1*
HD63PB05Y1*
5.0
0-+70
DC·64SP
HD6305X1
HD6305Y1
HD63B05X1
HD63A05X1
HD63B05Y1
HD63A05Y1
HN482732A·30 HN482732A·30 HN482732A·25
HN482764
HN482764·3
HN482764·3
HN27C64·25
HN27C64·30
HN27C64·30
874
874
874
·Preliminary
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
15
INTRODUCTION OF PACKAGES
Hitachi microcomputer devices are offered in a variety of
packages, to meet various user requirements.
1. Package Classification
When selecting suitable packaging, please refer to the
Package Classifications given in Fig. I for pin insertion, surface
mount, and multi-function types, in plastic and ceramic.
Standard Outline
Pin Insertion Type
Plastic DIP
Ceramic DIP
Shrink Outline
Shrink Type Plastic DIP
Shrink Type Ceramic DIP
Package Classification
Flat Package
FPP (Plastic)
Surface Mounting Type
Ch ip Carrier
Multi-function Type
SOP (Plastic)
EPROM on the
Package Type
PLCC (Plastic)
LCC
(Glass Sealed Ceramic)
DIP; DUAL IN LINE PACKAGE
S-DIP; SHRINK DUAL IN LINE PACKAGE
PGA: PIN GRID ARRAY
FLAT-DIP; FLAT DUAL IN LINE PACKAGE
FLAT-QUIP; FLAT QUAD IN LINE PACKAGE
CC: CHIP CARRIER
SOP; SMALL OUTLINE PACKAGE
FPP; FLAT PLASTIC PACKAGE
PLCC;PLASTIC LEADED CHIP CARRIER
LCC ; LEADLESS CHIP CARRIER
Fig. 1
Package Classification according to Material and Printed Circuit Board Mounting Type
$
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
17
INTRODUCTION OF PACKAGES - - - - - - - - - - - - - - - - - - - - - - - tified by code as follows, illustrated in the data sheet of each
device.
When ordering, please write the package code beside the type
number.
2. Type No. and Package Code Indication
Type No. of Hitachi single-chip microcomputer device is
followed by package material and outline specifications, as
shown below. The package type used for each device is idenType No. Indication
HDxxxxP
(Note)
The type No. of EPROM on the package type and
EPROM on-chip type microcomputers is described
as follows.
Package Classification
C : Ceramic DIP
P ; Plastic DIP
F
FPP
CG; LCC
EPROM on the package type: HDXXfXXXX
EPROM on-chip type
HDXX1XXXXC
Package Code Indication
DP-64S
D; DIP
C;CC
F ; FLAT
18
P ; Plastic
G ;Glass sealed
ceramic
C ;Ceramic
S; Shrink type
P; EPROM on the package type
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------INTRODUCTIONOFPACKAGES
3. Package Dimensional Outline
Hitachi single·chip microcomputer device employs the pack·
ages shown in Table I according to the mounting method on
the PCB.
Table 1 Package List
Package classification
Mounting method
Package material
Package code
Plastic
Dp·28
Dp·40
Ceramic
DC-40
Plastic
DP·64S
Ceramic
DC·64S
Plastic
Fp·54
Fp·64
Fp·80
FP·100
Standard outline (DIP)
Pin insertion type
Shrink outline (S·DIP)
Flat package (FPP)
Surface mounting type
Chip carrier (LCC)
EPROM on the package type
Multi·function type
Glass sealed ceramic
CG·40
Ceramic
DC·40P
DC·64SP
Plastic DIP
•
DP·28
~
0" -IS"
•
o S1mtn-~
5
k---\.o
8ma.~
2S'm,"
20_0 38
(Unit: mml
DP·40
(Unit: mm)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
19
INTRODUCTION OF PACKAGES
Ceramic DIP
• DC-40
0'""
1
!
'I--_----l~21_
_____L
A
~-.~
L_~
(Unit: mm)
Shrink Type Plastic DIP
•
DP·64S
o
17.0
5.1m.. 2.S4"""
(Unit:mml
20
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
INTRODUCTION OF PACKAGES
I
Shrink Type Ceramic DIP
• DC-64S
.
'0
lQJ
"
cu
~I
~
'
0.20-0.36
(Unit: mm)
Flat Package
•
FP·54
(Unit: mm)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
21
•
FP·64
(Unlt:mm)
• FP-80
f-
I
ij
~_._r-i
(Unit: mm)
• FP-100
25810.
:zo
.,
,-I
90
iI'so
,
31
~I
1
"'U
~I
1
"Xl
Xl
(Unit: mm)
22
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------INTRODUCTIONOFPACKAGES
I Leadless Chip Carrier I
• CG·40
12.19
D~
~II'I
~
0 0 00000000%1
§
~
(Unit: mm)
I EPROM on the Package Type I
• DC-40P
. ,.n
i
1!i24
!
(Unit: mm)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
23
INTRODUCTION OF PACKAGES
• DC·64SP
o
II
II
II
II
101
a
II
II
I
~I
i=
II
III
a
II
-a
a
a
a
a
III
a
II
II
(Unit:mm)
The temperature of the leads should be kept at 260°C
for 10 minutes or less.
(2) The temperature of the resin should be kept at 23SoC
for 10 minutes or less.
(3) Below is shown the temperature profile when soldering a
package by the reflowing method.
(1)
4. Mounting Method
Package lead pins are surface treated with solder coating or
plating to facilitate PCB mounting. The lead pins are connected
to the package by eutectic solder. Common connecting method
of leads and precautions are explained as follows:
4.1
Mounting Methods of Pin Insertion Type Package
Insert lead pins into the PCB through-holes (usually about
cPO.8mm). Soak leads in a wave solder tub.
Lead pins held by the through-holes enable handling of the
package through the sqldering process, and facilitate automated
soldering. When soldering leads in the wave solder tub, do not
get solder on the package.
4.2 Mounting Method of Surface Mount Type Package
Apply the specified quantity of solder paste to the pattern on
any printed board by the screen printing method, to temporarily
fix the package to the board. The solder paste melts when heated
in a reflowing furnace, and package leads and the pattern of the
printed board are fixed by the surface tension of the melted
solder and self alignment.
The size of the pattern where leads are attached should be 1.1
to 1.3 times the leads' width, depending on paste material or
furnace adjustment.
The temperature of the reflowing furnace is dependent on
packaging material and type. Fig. 2 lists the adjustment of the
reflowing furnace for FPP. Pre-heat the furnace to 150° C. Surface temperature of the resin should be kept at 235° C maximum
for lO minutes or less.
24
Time-
Fig.2 Reflowing Furnace Adjustment
for FPP
Employ adequate heating or temperature control equipment
to prevent damage to the plastic package epoxy-resin material.
When using an infrared heater, avoid long exposure at temperatures higher than the glass transition point of epoxy-resin (about
150° C), which may cause package damage and loss of reliability
characteristics. Equalize the temperature inside and outside of
packages by reducing the heat of the upper surface of the
packages.
FPP leads may easily bend in shipment or during handling,
and impact soldering onto the printed board. Heat the bent leads
again with a soldering iron to reshape them.
Use a rosin flux when soldering. Do not use chloric flux
because the chlorine in the flux has a tendency to remain on the
leads and reduce reliability. Use alcohol, chlorothene orfreon to
wash away rosin flux from packages. These solvents should not
remain on the packages for an excessive length of time, because
the package markings may disappear.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------INTRODUCTIONOFPACKAGES
5.
Package Marking
The Hitachi trademark and product type No. are printed on
packages, as shown in the following examples. Customer
marking can be added to single-chip devices upon request.
(b)
(a)
'.~~~
(e)B DB8DL1JSDB
(d)
~
DD
(e)
D~ B~ rsJ
Meaning of each mark
(a)
Hitachi Trademark
(b)
Lot Code
(c)
TYpe No.
(d)
(e)
.ROM Code
Japan Mark
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
25
QUALITY ASSURANCE
1. VIEWS ON QUALITY AND RELIABILITY
Basic views on quality at Hitachi are to meet the
individual uers' required quality level and maintain a
general quality level equal to or above that of the
general market. The quality required by the user may
be specified by contract, or may be indefinite. In either
case, efforts are made to assure reliable performance
in actual operating circumstances. Quality control
during the manufacturing process, and quality awareness from design through production lead to product
quality and customer satisfaction. Our quality assurance technique consists basically of the following
steps:
(1) Build in reliability at the design stage of new
product development.
(2) Build in quality at all steps in the manufacturing
process.
(3) Execute stringent inspection and reliability confirmation of final products.
(4) Enhance quality levels through field data feed
back.
(5) Cooperate with research laboratories for higher
quality and reliabili~y.
With the views and methods mentioned above,
utmost efforts are made to meet users' requirements.
design, device design, layout design, etc. Therefore, as long as standardized processing and
materials are used the reliability risk is extremely
small even in the case of new development
devices, with the exception of special requirements imposed by functional needs.
(2) Device Design
It is important for the device design to consider
total balance of process, structure, circuit, and
layout design, especially in the case where new
processes and/or new materials are employed.
Rigorous technical studies are conducted prior to
device development.
(3) Reliability Evaluation by Functional Test
Functional Testing is a useful method for design
and process reliability evaluation of IC's and LSI
devices which have complicated functions.
The objectives of Functional Test are:
• Determining the fundamental failure mode.
• Analysis of relation between failure mode and
manufacturing process.
• Analysis of failure mechanism.
• Establishment of QC points in manufacturing
process.
2. RELIABILITY DESIGN OF
SEMICONDUCTOR DEVICES
2.3' Design Review
2.1 Reliability Targets
The reliability target is an important factor in sales,
manufacturing, performance, and price. It is not adequate to set a reliabi Iity target based on a si ngle set of
common test conditions. The reliability target is set
based on many factors:
(1) End use of semiconductor device.
(2) End use of equipment in which device is used.
(3) Device manufacturing process.
(4) End user manufacturing techniques.
(5) Quality control and screening test methods.
(6) Reliability target of system.
2.2 Reliability Design
The following steps are taken to meet the reliability
targets:
(1) Design Standardization
As for design rules, critical items pertaining to
quality and reliability are always studied at circuit
26
Design Review is an organized method to confirm that
a design satisfies the performance required and
meets design specifications. In addition, design review
helps to insure quality and reliability of the finished
products. At Hitachi, design review is performed from
the planning stage to production for new products,
and also for design changes on existing products.
Items discussed and considered at design review are:
(1) Description of the products based on design
documents.
(2) From the standpoint of each participant, design
documents are studied, and for points needing
clarificatior'!, further investigation will be carried
out.
(3) Specify quaiity control and test methods based on
design documents and drawings.
(4) Check process and ability of manufacturing line to
achieve design goal.
(5) Preparation for production.
(6) Planning and execution of sub-programs for
design changes proposed by individual specialists,
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
QUALITY ASSURANCE
for test, experiments, and calculations to confirm
the design changes.
(7) Analysis of past failures with similar devices, discussion of methods to prevent them, and planning
and execution of test programs to confirm success.
design, as described in section 2. Our views on quality
approval are:
(1) A third party executes approval objectively from
the standpoint of the customer.
(2) Full consideration is given to past failures and
3. QUALITY ASSURANCE SYSTEM
information from the field.
(3) No design change or process change without QA
3.1 Activity of Quality Assurance
approval.
materials, and processes are closely
monitored.
(5) Control points are established in mass production
after studying the process abilities and variables.
General views of overall quality assurance in Hitachi
are as follows:
(1) Problems in each individual process should be
solved in ~he process. Therefore, at the finished
product stage the potential failure factors have
been removed.
(2) Feedback of information is used to insure a satisfactory level of ability process.
(4) Parts,
3.3 Quality and Reliability Control at Mass
Production
Quality control is accomplished through division ot
functions jn manufacturing, quality assurance, and
other related departments. The total function flow is
shown in Fig. 2. The main points are described below.
3.2 Quality Approval
To insure quality and reliability, quality approval is
carried out at the preproduction stage of device
Contents
Step
ISpecification
Target
I
I
I Design Review
i
II
Design
Trial
Production
Materials, Parts
Approval
II
IlCharacteristics Approval
II
ILQuality Approval (1)
II
II Qual ity. App
~
I~ass
Production
I
Purpose
Characteristics of Material and
Parts
Appearance
Dimension
Heat Resistance
Mechanical
Electrical
Others
Electrical
Characteristics
Function
Voltage
Current
Temperature
Others
Appel'lrance, Dimension
Confirmation of
Characteristics and
Reliability of Materials
and Parts
I Confirmation of Target
Spec. Mainly about
Electrical Characteristics
Reliability Test
Life Test
Thermal Stress
Moisture Resistance
Meehan ical Stress
Others
Confirmation of Quality
and Reliability in Design
Reliability Test
Process Check same as
Quality Approval (1)
Confirmation of Quality
and Reliability in Mass
Production
Figure 1 Flow Chart of Quality Approval
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
27
QUALITY ASSURANCE - - - - - - - - - - - - - - - - - - - - - -
Method
Quality Control
Process
Inspection on Material and
Parts for Semiconductor
Devices
Products
_ __ __ _
Lot Sampling,
Confirmation of
Quality Level
Manufacturing Equipment,
Environment, Sub-material,
Worker Control
Confirmation of
Quality Level
Inner Process
Quality Control
Lot Sampling,
Confirmation of
Quality Level
100% Inspection on
Appearance and Electrical
Characteristics
Testing,
Inspection
Sampling Inspection on
Appearance and Electrical
Characteristics
Lot Sampling
Reliability Test
Confirmation of
Quality Level, Lot
Sampling
r ---------------,
Feedback of
Information
:
Quality Information
I
Claim
:
Field Experience
General Quality
IL _______________
Information
__ oJI
I
I
I
Figure 2
28
Flow Chart of Qltality Control in Manufacturing Process
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
QUALITY ASSURANCE
3.3.1 Quality Control of Parts and Materials
As semiconductor devices tend towards higher performance and higher reliability, the importance of
quality control of parts and materials becomes paramount. Items such as crystals, lead frames, fine wire
for wire bonding, packages, and materials needed in
manufacturing processes such as masks and chemicals, are all subject to rigorous inspection and control.
Incoming inspection is performed based on the purchase specification and drawing. The sampling is executed based mainly on MIL-STD-105D.
The other activities of quality assurance are as
follows:
(1) Outside vendor technical information meeting.
(2) Approval and guidance of outside vendors.
(3) Chemical analysis and test.
The typical check points of parts and materials are
shown in Table 1.
Table 1 Quality Control Check Points of Material and Parts
(Example)
Material,
Parts
Important
Control Items
Appearance
Wafer
Mask
Fine
Wire for
Wire
Bonding
Frame
Ceramic
Package
Dimension
Sheet Resistance
Defect Density
Crystal Axis
Appearance
Dimension
Resistoration
Gradation
Appearance
Dimension
Purity
Elongation Ratio
Appearance
Dimension
Processing
Accuracy
Plating
Mounting
Characteristics
Appearance
Dimension
Leak Resistance
Plating
Mounting
Characteristics
Electrical
Characteristics
Mechanical
Strength
Composition
Plastic
Electrical
Characteristics
Thermal
Characteristics
Molding
Performance
Mounting
Characteristics
Point for Check
Damage and Contamina·
tion on Surface
Flatness
Resistance
Defect Numbers
Defect Numbers, Scratch
Dimension Level
3.3.2 Inner Process Quality Control
Inner Process Quality Control performs very important
functions in quality assurance of semiconductor
devices. The manufacturing Inner Process Quality
Control is shown in Fig. 3.
(1) Quality Control of Semi-final Products and Final
Products
Potential failure factors of semiconductor devices
are removed in the manufacturing process. To
achieve this, check points are set-up in each process and products which have potential failure
factors are not moved to the next process step.
Manufacturing lines are rigidly selected and tight
inner process quality controls are executed-rigid
checks in each process and each lot, 100% inspection to remove failure factors caused by manufacturing variables and high temperature aging and
temperature cycling. Elements of inner process
quality control are as follows:
• Condition control of equipment and workers
environment and random sampling of semifinal products.
• Suggestion system for improvement of work.
• Education of workers.
• Maintenance and improvement of yield.
• Determining quality problems, and implement·
ing countermeasures.
• Transfer of quality information.
Uniformity of Gradation
Contamination, Scratch,
Bend, Twist
Purity Level
Mechanical Strength
Contamination, Scratch
Dimension Level
Bondability, Solderability
Heat Resistance
Contamination, Scratch
Dimension Level
Airtightness
Bondability, Solderability
Heat Resistance
Mechanical Strength
(2) Quality Control of Manufacturing Facilities and
Measuring Equipment
Manufacturing equipment is improving as higher
performance devices are needed. At Hitachi, the
automation of manufacturing equipment is encouraged. Maintenance Systems maintain operation of high performance equipment. There are
daily inspections which are performed based on
related specifications. Inspection points are listed
in the specification and are checked one by one to
prevent any omission. As for adjustment and
maintenance of measuring equipment, specifications are checked one by one to maintain and
improve quality.
Characteristics of
Plastic Material
Molding Performance
Mounting Characteristics
(3) Quality Control of Manufacturing Circumstances
and Sub-Materials
The quality and reliability of semiconductor devices
are highly affected by the manufacturing process.
Therefore, controls of manufacturing circum-
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
29
QUALITY ASSURANCE - - - - - - - - - - - - - - - - - - - - - stances such as temperature, humidity and dust,
and the control of submaterials, like gas, and pure
water used in a manufacturing process, are intensively executed.
attention to buildings, facilities, air conditioning
systems, delivered materials, clothes, work environment. and periodic inspection of floating dust
concentration.
Dust control is essential to realize higher integration and higher reliability of devices. At Hitachi,
maintenance and improvement of cleanliness at
manufacturing sites is accomplished through
3.3.3 Final Product Inspection and Reliability
Assurance
(1) Final Product Inspection
Lot inspection is done by the quality assurance
Process
Control Point
Purpose of Control
Purchase of Material
wafer~
Wafer
, Surface Oxidation
Inspection on Surface
Oxidation
Photo Resist
Inspection on Photo Resist
o PQC Level Check
Diffusion
Appearance, Thickness of
Oxide Film
Inspection on Evaporation
o PQC Level Check
Wafer Inspection
Scratch, Removal of Crystal
Defect Wafer
Assurance of Resistance
Pinhole, Scratch
Photo
Resist
Dimension, Appearance
Diffusion
Inspection on Diffusion
o PQC Level Check
Evaporation
Characteristics, Appearance
Oxidation
Diffusion Depth, Sheet
Resistance
Gate Width
Characteristics of Oxide Film
Breakt:own Voltage
Evaporation
Thickness of Vapor Film.
Scratch, Contamination
Wafer
Thickness, VTH Characteristics
Electrical Characteristics
Dimension Level
Check of Photo Resist
Diffusion Status
Control of Basic Parameters
(VTH, etc.) Cleanness of surface,
Prior Check of VIH
Breakdown Voltage Check
Assurance of Standard
Thickness
Prevention of Crack,
Quality Assurance of Scribe
Inspection on Chip
Electrical Characteristics
Chip Scribe
Inspection on Chip
Appearance
o PQC Lot Judgement
Chip
Assembling
Assembling
Appearance after Chip
Bonding
Appearance after Wire
Bonding
Pull Strength, Compression
Width, Shear Strength
Appearance after Assembling
Quality Check of Chip
Bonding
Quality Check of Wire
Bonding
Prevention of Open and
Short
Sealing
Sealing
Guarantee of Appearance
and Dimension
o PQC Level Check
Final Electrical Inspection
o Failure Analysis
Marking
Appearance after Sealing
Outline, Dimension
Marking Strength
Analysis of Failures, Failure
Mode, Mechanism
Feedback of Analysis I nformati on
o PQC
Appearance of Chip
Level Check
Inspection after
Assembling
o PQC Lot Judgement
Appearance Inspection
Sampling Inspection on
Products
Receiving
Shipment
Figure 3 Example of Inner Process Quality Control
30
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
QUALITY ASSURANCE
department for products which were judged good
in 100% test ... the final process in manufacturing. Though 100% yield is expected, sampling
inspection is executed to prevent mixture of bad
product by mistake. The inspection is executed not
only to confirm that the products have met the
users' requirements but also to consider potential
Customer
Quality factors. Lot inspection is executed based
on MIL-STO-l050.
(2) Reliability Assurance Tests
To assure the reliability of semiconductor devices,
reliability tests and tests on individual manufacturing lots that are required by the user, are periodically performed.
I
Claim
(Failures, Information)
Sales Dept.
Sales Engineering Dept.
,----------------------------------1
1
L
I
Countermeasure
Execution of
Cou ntermeasu re
Design Dept.
Manufacturing Dept.
I
Failure Analysis
Quality Assurance Dept.
Report
Quality Assurance Dept.
I
IL ____________ _
~
Follow-up and Confirmation
of Countermeasure Execution
Report
--------------------~
Sales Engineering Dept.
Reply
Customer
Figure 4 Process Flow Chart of Field Failure
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
31
RELIABILITY TEST DATA
1. INTRODUCTION
2. PACKAGE AND CHIP STRUCTURE
2.1 Packaging
Microcomputers provide high reliability and quality to meet
the demands of increased functions, enlarging scale, and widening application. Hitachi has improved the quality .level of
microcomputer products by evaluating reliability, building
quality into the manufacturing process, strengthening inspection
techniques, and analyzing field data.
The following reliability and quality assurance data for
Hitachi 8-bit single-chip microcomputers indicates results from
test and failure analysis.
Production output and application of plastic packaging continues to increase, expanding to automobile measuring and control systems, and computer terminal equipment operating under
severe conditions. To meet this demand, Hitachi has significantly
improved moisture resistance and operational stability in the
plastic manufacturing process.
Plastic and side-brazed ceramic package structures are shown
in Figure I and Table I.
(1) Plastic DIP
(2\ Plastic Flat Package
Bonding wire
Figure 1 Package Structure
Table 1 Package Material and Properties
32
Plastic Flat Package
Plastic DIP
Item
Package
Epoxy
Epoxy
Solder plating Alloy 42
Lead
Solder dipping Alloy 420r Cu
Die bond
Au-Si or Ag paste
Au-Si or Ag paste
Wire bond
Thermo compression
Thermo compression
Wire
Au
Au
$
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - R E L I A B I L I T Y TEST DATA
2.2 Chip Structure
The HMCS6800 family is produced in NMOS E/ D technology or low power CMOS technology. Si-gate process is used
in both types to achieve high reliability and density. Chip structure and basic circuitry are shown in Figure 2.
Si-Gate N-channel E/D
Drain
Source
FET1
Drain
Si-Gate CMOS
SiO,
Source
Drain
Source
FET2
FET2
P-channel
EMOS
N-channel
DMOS
N-channel
EMOS
N·channel
EMOS
Figure 2 Chip Structure and Basic Circuit
3. QUALITY QUALIFICATION AND EVALUATION
3.1
Reliability Test Methods
Reliability test methods shown in Table 2 are used to qualify and evaluate new products and processes.
Table 2 Reliability Test Methods
Test Items
Test Condition
M IL-STO-883B Method No.
Operating Life Test
125°C,1000hr
1005,2
High Temp. Storage
Low Temp, Storage
Steady State Humidity
Steady State Humidity Biased
Tstg max, 1000hr
Tstg min, 1000hr
65°C 95%RH, 1000hr
85°C 85%RH, 1000hr
1008,1
T em peratu re Cycl ing
Temperature Cycling
Thermal Shock
Soldering Heat
Mechanical Shock
Vibration Fatigue
Variable Frequency
Constant Acceleration
Lead Integrity
-55°C'" 150°C, 10 cycles
-20°C'" 125°C:200 cycles
O°C'" 100°C, 100 cycles
260°C, 10 sec
1500G 0.5 msec, 3 times/X, Y, Z
60Hz 20G, 32hrs/X, Y, Z
20"'2000Hz 20G, 4 min/X, Y, Z
20000G,1 min/X, Y, Z
225gr, 90° 3 times
1010,4
1011,3
2002,2
2005,1
2007,1
2001,2
2004,3
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
33
RELIABI LlTY TEST D A T A - - - - - - - - - - - - - - - - - - - - - - - - - - 3.2 Reliability Test Results
Reliability Test Results of 8-bit single-chip microcomputer
devices are shown in Table 3 to Table 7.
Table 3 Dynamic Life Test
Sample Size
Component Hours
Failures
191 pes.
114
191000
114000
0
77
40
- - - - - - --2-2----------
77000
40000
- - - - - - - - 22000- - - - - - -
0
0
- - - - - -0- - - - - - -
32000
22000
0
0
Device Type
HD6801P
HD6805P
0
-----------r-----------------------------------------------182
182000
HD6301P
0
HD6305P
HD63L05P
---------HD68P01
HD63P01
HD68P05
32
22
Estimated Field Failure Rate
.. 0.01 S%/1 000 hrs at Ta" 7SoC for NMOS (HDS801P, HD680SP)
.. 0.037%/1000 Ius at Ta = 7SoC for CMOS (HDS301P, HDS3LOSP)
(Activation Energy 0.7eV, Confidence LeveISO%)
Table 4 High Temperature, High Humidity Test (Moisture Resistance Test)
(1) 85°C 85%RH Bias Test
Device Type
Vcc Bias
168 hrs
500 hrs
1000 hrs
HD6801P
HD6805P
HD6301P
HD6305P
5.5V
5.5V
5.5V
5.5V
0/22
0/22
0/176
0/22
0/22
0/22
0/131
0/22
0/22
0/22
0/131
0/22
Condition
168 hrs
500 hrs
1000 hrs
65°C 95%RH
65°C 95%RH
65°C 95%RH
85°C 95%RH
65°C 95%RH
65°C 95%RH
85°C 95%RH
0/45
0/45
0/603
0/234
0/112
0/160
0/160
(2) High Temperature-High Humidity Storage Life Test
Device Type
HD6801P
HD6805P
HD6301P
HD6301P
HD6305P
HD63L05P
HD63L05P
0/45
0/45
0/603
1 */234
0/112
0/160
1 */160
0/45
0/45
0/603
0/233
0/112
0/160
0/159
.. Aluminum corrosion
(3) Pressure Cooker Test
(Condition: 2 atm 121°C)
Device Type
40 hrs
60 hrs
100 hrs
HD6801P
HD6805P
HD6301P
HD6305P
HD63L05P
0/45
0/44
0/135
0/32
0/80
0/45
0/44
0/135
0/32
0/80
0/45
0/44
0/135
0/32
1*/80
200 hrs
0/45
0/44
0/135
0/32
2** /79
.. Leakage current
··Leakage current and Aluminum corrosion
34
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
,
- - - - - - - - - - - - - - - - - - - - - - - - - - - RELIABI LlTY TEST DATA
(4) MIL-STD-883B Moisture Resistance Test
(Condition; 65°C- _10°C, over 90%RH)
Device Type
10 cycles
20 cycles
40 cycles
HD6801P
HD6805P
HD6301P
HD63L05P
0/50
0/32
0/75
0/22
0/50
0/32
0/75
0/22
0/50
0/32
0/75
0/22
Table 5 Temperature Cycling Test
Device Type
10 cycles
100 cycles
200 cycles
HD6801P
HD6805P
HD6301P
HD6305P
0/102
0/442
0/258
0/45
0/102
0/45
0/258
0/45
0/102
0/45
0/258
0/45
HD63P01
HD68P05
0/45
0/68
0/44
0/45
0/19
0/44
0/45
0/19
f-------- -----------------------HD68P01
0/44
-------------- ---- - -- ---- ----
Table 6 High Temperature, Low Temperature Storage Life Test
Device Type
Ta
168hrs
500hrs
HD6801P
150°C
-55°C
0/22
0/22
0/22
0/22
-- - - - 0/44
0/22
- - - - - - - - - -- -
---
-
HD6805P
- - - -- - - -
-
--
--
- - -
-- --
-----------
- -- ----- - - - - -- - - -
0/44
0/22
-- - 0/22
0/22
f- - - - -
-55°C
- - -
-
--
-- - - -
- - - -- - - 0/22
0/22
--
- - -
- - -
-55°C
$
-
-
0/45- - - - - - - - - 0/45- - - - - - - - - 0145 - - - - 0/22
15~C
0/22
0/22
- - - - -- - -0/44
0/22
- - - - - - -- -0/22
0/22
- - - -- -
0/22
---------- ---------------------
HD6305P
-55°C
- - - - - - - - - - - - - - - 150°C- - - HD63L05P
--- -- - -
150°C
-55°C
150° C
HD6803P
-55°C
- - - - - - - - -- -- - - - - 150°C-- - - HD6301P
-
1000hrs
On2
On2
0/22
0/22
0/22 - - - - - - -
0/22
0/22
-oni - - - - - - - -
0/22
-----------
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
~~
0/22
-On2- - -- 0/22
35
RELIABILITY TEST D A T A - - - - - - - - - - - - - - - - - - - - - - - - - - Table 7 Mechanical and Environmental Test
Test Item
4.
Plastic DIP
Condition
Flat Plastic Package
Sample Size
Failure
Sample Size
Failure
Thermal Shock
O°C -100°C
10 cycles
110
0
100
0
Soldering Heat
260°C, 10 sec.
164
0
22
0
Salt Water Spray
35°C, NaCI 5%
24 hrs
110
0
22
0
Solderabil ity
230°C, 5 sec.
Rosin flux
159
0
34
0
Drop Test
75cm, maple board
3 times
110
0
22
0
Mechanical Shock
1500G, 0.5ms
3 times/X, Y, Z
110
0
22
0
Vibration Fatigue
60 Hz, 20G
32hrs/X, Y, Z
110
0
22
0
Vibration Variable Freq.
100 - 2000Hz
20G, 4 times/X, Y, Z
110
0
22
0
Lead Integrity
225g, 90°
Bonding 3 times
110
0
22
0
PRECAUTIONS
4.1 Storage
To prevent deterioration of electrical characteristics, solderability, appearance or structure, Hitachi recommends semiconductor devices be stored as follows:
(1) Store in ambient temperatures of 5 to 30° C, with a relative
humidity of 40 to 60%.
(2) Store in a clean, dust- and active gas-free environment.
(3) Store in conductive containers to prevent static electricity.
(4) Store without any physical load.
(5) When storing devices for an extended period, store in an
unfabricated form, to minimize corrosion of pre-formed
lead wires.
(6) Unsealed chips should be stored in a cool, dry, dark and
dust-free environment. Assembly should be performed
within 5 days of unpacking. Devices can be stored for up to
20 days in dry nitrogen gas with a dew point at -30° C or less.
(7) Prevent condensation during storage due to rapid temperature changes.
(2) To prevent device deterioration from clothing-induced static
electricity, workers should be properly grounded while handling devices. Use of a I M ohm resistor is recommended to
prevent electric shock.
(3) When transporting printed curcuit boards containing semiconductor devices, suitable preventive measures against
static electricity must be taken. Voltage build-up can be
avoided by shorting the card-edge terminals. When a belt
conveyor is used, apply some surface treatment to prevent
build-up of electrical charge.
(4) Minimize mechanical vibration and shock when transporting semiconductor devices or printed circuit boards.
4.3 Handling for Measurement
4.2 Transportation
General precautions for electronic components are applicable in transporting semiconductors, units incorporating semiconductors, and other similar systems. In addition, Hitachi
recommends the following:
(I) When transporting semiconductor devices or printed circuit
boards, minimize mechanical vibration and shock. Use containers or jigs which will not induce static electricity as a
result of vibration. Use of an electrically conductive container or aluminum foil is recommended.
36
Avoid static electricity, noise and voltage surge when measuring or mounting devices. Precaution should be taken against
current leakage through terminals and housings of curve tracers,
synchroscopes, pulse generators, and DC power sources.
When testing devices, prevent voltage surges from the tester,
attached clamping circuit, and any excessive voltage possible
through accidental contact.
In inspecting a printed circuit board, power should not be
applied if any solder bridges or foreign matter is present.
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - RELIABI LlTY TEST DATA
4.4 Soldering
Semiconductor devices should not be exposed to high
temperatures for excessive periods. Soldering must be performed
consistent with temperature conditions of 2600 C for 10 seconds,
3500 C for 3 seconds, and at a distance of I to 1.5mm from the end
of the device package.
A soldering iron with secondary voltage supplied through a
grounded transformer is recommended to protect against
leakage current. Use of alkali or acid flux, which may corrode the
leads, is not recommended.
4.5 Removing Residual Flux
Detergent or ultrasonic removal of residual flux from circuit
boards is necessary to ensure system reliability. Selection of
detergent type and cleaning conditions are important factors.
When chloric detergent is used for plastic packaged devices,
care must be taken against package corrosion. Extended
cleaning periods and excessive temperature conditions can cause
the chip coating to swell due to solvent permeation. Hitachi
recommends use of Lotus and Dyfron solvents. Trichloroethylene solvent is not suitable.
The following conditions are advisable for ultrasonic
cleaning:
•
Frequency: 28 to 29 k Hz (to avoid device resonation)
•
Ultrasonic output: 15W/f
•
Keep devices from making direct contact with power
generator
•
Cleaning time: Less than 30 seconds.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
37
DESIGN PROCEDURE AND SUPPORT TOOLS FOR
8-BIT SINGLE-CHIP MICROCOMPUTERS
The cross assmebler and hardware simulator using various
types of computers are prepared by Hitachi as supporting systems to develop user's programs.
User's programs are mask programmed into the ROM and
delivered as the LSI by the company.
Fig. I shows the typical program design procedure and Table
I shows the system development support tools for the 8-bit
single-chip microcomputer family used in these processes.
CD
®J
(3
Text Editor / CRT Editor
Evaluation Kit
H68SD5A
Intel MDS
PDP·11
VAX-11
IBM370
Cross Assembler
Evaluation Kit
H68SD5A
Intel MDS
PDP·11
VAX-11
IBM370
Evaluation Kit
Evaluation Board
H68SD5A
EPROM on the Package Type
Microcomputer
HD68P01V07
HD68P05V07
HD68P05WO
HD63P01M1
[ HD63P05YO
HD63P05Yl
EPROM on·chip Type
Microcomputer
HD63701VO
HD63701XO
[
HD63705VO
CD When the user programs the system, the predetermined functions are
aSSigned to the I/O pin and the RAM before the programming.
@A
flow chart is deSigned to achieve the predetermined functions and the flow
chart is coded by uSing the prenumeroc code.
@ The coded
flow chart is punched Into the card or the paper tape or written into
the floppy diSk, to generate a source program.
@
The source program IS assembled by the resident system (evaluation kitl or the
cross system, to generate the object program. In thiS case, errors during
the assembling are also detected.
® Hardware Simulation IS performed to confirm the program.
.
.'
The company provides four kinds of hardware, the H68SD5A, the evaluation kit,
the evaluation board and the EPROM on the package type microcomputer. The
consumers are able to choose the best suitable tool.
® The completed program IS sent to the company In the form
of EPROM or the
object tape.
(!) Options
such as ROM IS masked by the company, LSI IS testatively produced
and the sample IS handed In to the user. After the user has evaluated the
sample and confirmed that the program IS correct, mass production is
started.
Figure 1 Program Design Prnr"~'lre
38
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, ·CA 95131 • (408) 435-8300
DESIGN PROCEDURE AND SUPPORT TOOLS
- - - - - - - - - - - - - - - - - - - - F O R 8-BIT SINGLE-CHIP MICROCOMPUTER
Table 1 System Development Support Tools
Resident System
Type No.
Cross System
Evaluation Kit
Evaluation
Board
EPROM on
the Package
H68SD5A+Emulator Set
(Hardware + Software)
IBM370
HD6801S0
HD6801VO
H61EVT2 (Hardware)
+
S61MIX2-R (Software)
-
HD68P01V07
H68SD5A + H61MIX1
S31XSY1-T
HD6805S1
HD6805S6
H65EVT2 (Hardware)
-
-
HD6805U1
HD6805V1
HD6805W1
HD6301V1
+
S65MIX1-R (Software)
H65EVT3 (Hardware)
+
S65MIX1-R (Software)
H31EVT1 (Hardware)
+
S31MIX1-R (Software)
HD68P05V07
-
HD68P05WO
-
HD63P01M1
HD63701VO t ** H68SD5A+H31MIX1
HD6301XO
-
-
HD6301YO
HD6305UO·
HD6305VO*
-
**
-
-
-
HD6305XO
HD6305X1
HD6305YO
HD6305Y1
H35EVT1
(Hardware + Software)
HD63L05F1
H3L5EVT1 (Hardware)
+
H3L5EVOO
S3L5MIX1-R (Software
* Prel iminary
* * Under development
-
-
H68SD5A + H65MIX2
t*
HD63701XO
H68SD5A + H31MIX2
-
H68SD5A + H31MIX3
H68SD5A + H35MIX1
-
H68SD5A + H3L5MIX1
t EPROM On-chip Type
0
-
-
S31XSY1-T
HD63705VOt**
H68SD5A+ H35MIX3**
H D63705-V'OT*'*
HD63P05YO
HD63P05Y1 *
HD63P05YO
HD63P05Y1 *
S31MDS1-F
(ISIS-II)
S31MDS2-F
(CP/M)
S35MDS1-F I - - (ISIS-II)
S35MDS2-F r - - (CP/M)
-
H68SD5A + H65MIX1
-
Intel
PDP-11/
MDS2201230 VAX-11
S31MDS1-F
(ISIS-II)
S31MDS2-F
(CP/M)
-
0
I----
r--20
S35MDS1-F
(ISIS-II)
S35MDS2-F
(CP/M)
-
-
-
-
-
0 Available from Microtec.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
39
DESIGN PROCEDURE AND SUPPORT TOOLS
FOR 8-BIT SINGLE-CHIP M I C R O C O M P U T E R - - - - - - - - - - - - - - - - - - - System Configuration
• SINGLE-CHIP MICROCOMPUTER DEVELOPMENT
SYSTEM
H68SD5A is a completely integrated hardware and software
development system for Hitachi's 4-Bit and 8-Bit single-chip
microcomputers. It offers high-level functions such as operation
by CRT display, assembler (based on floppy disk), easy debugging (in-circuit emulator) and simulation.
H6BSD5A
FEATURES
• Upward version of the H6BSD5
• CRT Display, keyboard and two floppy disk drives
• Easy to debug user's prototype system by in-circuit emulators suited for each kind of MCU.
• The H6BSD5A can perform system development by CRT
editor, assembler, linkage editor, emulator and simulator.
• Parallel andlor serial interface ports are available for easy
printer interface.
• EPROM programmer interface software is provided. DATA
110's EPROM programmers (29A, 22A and 228) are applicable.
• User's program developped by using the H6BSD5 is usable.
• Emulators for the H6BSD5 are usable.
Emulator Module
(Option)
40
B-bit single-chip miCrO-]
computer family
HMCS40 series
HMCS400 series
I
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
DATA SHEETS
Preliminary data sheets herein contain information on new products. Specifications and information are subject to change without notice.
Advance Information data sheets herein contain information on a product
under development. Hitachi reserves the right to change or discontinue these
products without notice.
HD6801S0,HD6801S5-----MCU (Microcomputer Unit)
The HD6801S MCV is an 8-bit microcomputer unit which is
compatible with the HMCS6800 family of parts. The HD6801 S
MCV is object code compatible with the HD6800 with improved execution times of key instructions plus several new 16bit and 8-bit instructions including an 8x8 unsigned multiply
with l6-bit result. The HD6801S MCV can operate as a single
- chip microcomputer or be expanded to 65k bytes. The
HD6801S MCV is TTL compatible and requires one +5.0 volt
power supply. The HD680lS MCV has 2k bytes of ROM and
128 bytes of RAM on chip. Serial Communication interface
(S.C.I.), and parallel I/O as well as a three function 16-bit timer.
Features and Block diagram of the HD680 I S include the follow-
HD6801S0P
HD6801S5P
(DP-40)
.
~g:
•
•
•
FEATURES
Expanded HMCS6800 Instruction Set
•
•
8 x 8 Multiply
On-Chip Serial Communication Interface (S.C.I.)
•
Object Code Compatible With The HD6800 MPU
•
•
16-Bit Timer
Single Chip Or Expandable To 65k Bytes
•
•
2k Bytes Of ROM
128 Bytes Of RAM (64 Bytes Retainable On Power
Down)
PIN ARRANGEMENT
o
HD6801S
• 29 Parallel 1/0 Lines And 2 Handshake Control Lines
•
Internal Clock/Divided-By-Four Circuitry
• TTL Compatible Inputs And Outputs
•
Interrupt Capability
• Compatible with MC6801 and MC6801-1
P••
•
BLOCK DIAGRAM
p.?
......_ _ _ _ _ _...r- Vee Standby
(Top View)
•
TYPE OF PRODUCTS
P2.
MCU
p"
HD6801S0
1 MHz
HD6801S5
1.25 MHz
P2I
14-+-++-.--. ~~:
Bus Timing
PI.
PII
PI2
PI1
p"
P"
p"
PI7
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
43
HD6801S0,HD6801S5----------------------------------------------------•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Supply Voltage
Vee
Input Voltage
Yin
Operating Temperature
Topr
Tstg
Storage Temperature
•
Value
Unit
-0.3 - +7.0
V
-0.3 - +7.0
-+70
V
°c
- 55 -+150
°c
..
..
0
With respect to VSS (SYSTEM GND)
(NOTE] Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could aftect reliability of LSI.
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee =S.OV±S%, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)
Item
Input "High" Voltage
Symbol
RES
V 1H
Other Inputs*
Input "Low" Voltage
Allinputs*
Input Load Current
P4Q - P47
SCI
EXTAL
NMI, IRQI, RES
Output "High" Voltage
P30 - P37
P4Q - P47 , E, SCI, SC 2
Other Outputs
Input Capacitance
Vee Standby
Standby Current
-
-
P17
max
Unit
-
Vee
2.0
-
V
Vee
0.8
V
-
-
0.5
Ilinl
V in = 0 - 5.2SV
Ts
V in = 0.5 - 2.4V
-
I LOAD = -205 fJ.A
I LOAD = -145 fJ.A
2.4
2.4
I LOAD = -100 fJ.A
2.4
I LOAD = 1.6 mA
V out = 1.5V
-
-
0.5
V
1.0
-
10.0
mA
mW
P37
All Outputs
typ
-
Yin = 0- Vee
PIO - P17 , P30
Pzo - PZ4
Darlington Drive Current PIO
Power Dissipation
Yin = 0- 2.4V
lIinl
Input Leakage Current
min
4.0
-0.3
VIL
Three State (Offset)
Leakage Current
Output" Low" Voltage
Test Condition
II
"
V OH
VOL
-IOH
PD
-
0.8
0.8
mA
-
2.5
fJ.A
10
100
fJ.A
-
-
-
-
-
-
-
1200
-
-
12.5
V SBB
4.0
-
5.25
Operating
V SB
-
5.25
Powerdown
ISBB
4.75
-
-
8.0
P30 - P37 , P4Q - P47 , SCI
Other Inputs
Cin
Powerdown
Yin = OV, Ta = 25°C,
f = 1.0 MHz
V SBB = 4.0V
10.0
V
pF
V
mA
• Except Mode Programming Levels.
44
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------HD6801S0,HD6801S5
•
AC CHARACTERISTICS
BUS TIMING (Vee = 5.0V±5%, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)
Item
Symbol
Cycle Time
Test Condition
HD6801S0
typ
min
max
1
10
-
Address Strobe Pulse Width "High"*
tcyc
PW ASH
Address Strobe Rise Time
tAs r
200
5
Address Strobe Fall Time
Address Strobe Delay Time *
tASf
tASD
5
60
Enable Rise Time
tE r
tEf
PW EH
PW EL
5
5
Enable Fall Time
Enable Pulse Width "High" Time *
Enable Pulse Width "Low" Time *
Address Strobe to Enable,Delay Time*
Address Delay Time
Address Delay Time for Latch (f=1.0MHz)*
tASED
tAD
Fig. 1
tADL
Fig. 2
min
-
50
5
-
50
5
30
-
-
5
5
340
350
30
-
50
50
-
-
-
-
-
-
-
260
260
ns
ns
ns
ns
ns
ns
ns
-
-
0.8
50
50
-
450
450
60
-
-
-
-
-
-
-
Unit
150
-
-
HD6801S5
typ
max
10
p.s
-
ns
50
50
ns
ns
ns
-
-
260
270
-
-
Data Set-up Write Time
tDSW
225
-
-
115
-
-
ns
Data Set-up Read Time
tDSR
tHR
80
10
-
-
70
-
-
ns
-
-
-
20
60
-
-
-
ns
tHW
tASL
-
-
10
20
50
-
-
ns
tAHL
tAH
20
-
-
20
-
-
ns
20
-
-
20
-
-
ns
-
-
-
-
(610)
(600)
-
-
-
-
(420)
(420)
ns
Read
Data Hold Time
Write
Address Set-up Time for Latch*
Address Hold Time for Latch
I
I
Address Hold Time
Peripheral Read
Access Time
I
I
Non-Multiplexed Bus *
Multiplexed Bus*
Oscillator stabilization Time
(tACCN)
(tACCM)
tRC
tpcs
Processor Control Set-up Time
*These timings change in approximate proportion to tcyc. The figures
is minimum (; in the highest speed operation).
PERIPHERAL PORT TIMING (Vee
10
Fig. 10
100
-
-
Fig. 11
200
-
-
100
200
-
-
ms
ns
-
this characteristics represent those when tcyc
= 5.0V ±5%, Vss = OV, Ta =0 -
+70°C, unless otherwise noted.)
Symbol
Test Condition
min
typ
max
Unit
Peripheral Data Setup Time
Port 1,2,3,4
tposu
Fig. 3
200
Port 1, 2,3,4
tpOH
Fig. 3
200
-
ns
Peripheral Data Hold Time
-
Delay Time, Enable Positive Transition
to 0S3 Negative Transition
tOS01
Fig. 5
-
-
350
ns
Delay Time, Enable Positive Transition
to 0S3 Positive Transition
t05 0 2
Fig. 5
-
-
350
ns
Delay Time, Enable Negative
Transition to Peripheral Data
Valid
Port 1, 2*,3,4
tpwo
Fig.4
-
-
400
ns
Delay Time, Enable Negative
Transition to Peripheral
CMOS Data Valid
*
Port 2**, 4
tCMo S
Fig. 4
-
-
2.0
Ils
tpWIS
Fig. 6
200
-
port 3
tlH
Fig. 6
50
-
Input Data Set-up Time
Port 3
tiS
Fig. 6
20
-
-
ns
Input Data Hold Time
Item
Input Strobe Pulse Width
*Except P21
ns
ns
ns
**10kn pull up register required for Port 2
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
45
HD6801S0,HD6801S5----------------------------------------------------TIMER, SCI TIMING (Vee" 5.0V ±5%, Vss
=OV, Ta =0 -
Item
Symbol
Timer Input Pulse Width
tpwT
Delay Time, Enable Positive Transition to
Timer Out
tTOD
SCI Input Clock Cycle
tSCYC
SCI Input Clock Pulse Width
tpwsCK
MODE PROGRAMMING (Vee
o
+70 C, unless otherwise noted.)
=5.0V ±5%, Vss =OV, Ta =0 -
Test Condition
typ
max
-
-
ns
-
-
600
ns
1
-
-
tCYC
0.6
tScYc
Unit
min
2tcyc+200
Fig. 7
0.4
Unit
+70°C, unless otherwise noted.)
min
typ
max
Mode Programming Input "Low" Voltage
V MPL
-
1.7
V
Mode Programming Input "High" Voltage
V MPH
4.0
-
V
-
tcyc
-
tcyc
Symbol
Item
Mode Programming Set·up Time
Mode Programming
Hold Time
3.0
-
tMPs
2.0
-
tMPH
0
100
-
PW RSTL
RES "Low" Pulse Width
I FfES Rise Time ~ 1J.1s
I m Rise Time < 1J.1s
Test Condition
Fig. 8
ns
~--------------------t~----------------------~
Address Strobe
lAS)
2.2V
O.6V
Enable
IE)
R/Vii
Ar-A"
Isell' IPort4)
MCU Write
D.-D •• A.-A,
IPort 3)
MCU Read
0.-0,. A.-A,
IPort 3)
1-----ltACCM)-
Figure 1 Expanded Multiplexed Bus Timing
46
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
--------------HD6801S0,HD6801S5
I.
tcvc
-J-
2.4V
lEI
,
PWEL
I
0.5V";f\
-
-tAO-
2.2V
Aa--A,(Port4 )
R1N
~
j
(SC2)
(SCI)
....JrPWEH
~!'
Enable
-\
--
-tEr
-tEf
-tAH
r-
~
Address Valid
-,~
0.6V'r-t05w-
2.2V,r-
MCU Write
0.-0,
(Port3)
-
Data Valid
If'
0.6V\-
"1'-
.
-t05R-"
(tACcNI
I
-tHW
-lr~
-
-tHR
2.0V
MCU Read
0.-0, -------------------------------------------(1
O.BV
Data Vahd
(Port 3)
Figure 2 Expanded Non-Multiplexed Bus Timing
r-
rMCURead
Enable(E)
MCU Write
Enable(E)
=:::~}---_o,v"
P,O - PI'
p.o - p ••
-------""'\.
All Data
p.o-P.,
Inputs
Port Outputs _ _ _ _ _ _ _ __
~.~~
Data Valid
p.o-p"
Inputs·
·Port 3 Non·Latched Operation (LATCH ENABLE
=
(NOTE)
1. 10 kn Pullup resistor required for Port 2 to reach 0.7 VCC
0)
2. Not applicable to P 21
3. Port 4 cannot be pulled above Vce
Figure 3
Data Set-up and Hold Times
'(MCU Read)
Figure 4
Port Data Delay Timing
(MCU Write)
153
Address
Bus
2.0V
(S0006)
OS3 __________•..;,,\ rtOSD1
•
·Access matches Output Strobe Select (OSS
OSS = 1, a write)
Figure 5
=
....tI H ..
~
O.6V ~"'
_ _ _ _ _ _ _- - ' , ~.~v
2.0V
p •• - P"
Inputs
O.BV
0, a read;
Port 3 Output Strobe Timing
(Single Chip Mode)
Figure 6
Port 3 Latch Timing
(Single Chip Mode)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
47
HD6801S0,HD6801S5-----------------------------------------------------
Enable
(E)
Timer
Counler _ _ _ _ _ _---!~---
'____
I------~L VMPH
Mode InpulS _ _ _ _ _......"'<1
{P, •• p". P" I
VMPL
P"
Oulpul
Figure 8
Figure 7
Mode Programming Timing
Timer Output Timing
Vee
Test Point
0,......----1'
m
AL -2.2kO
Tesl Point
30pF
lS2074
®
or Equiv.
C
A
C • 90 pF for.P,. -p". p.. -p.,. E. SC,. SC,
=30 pF for P,. -p". PIO -p ..
A· 12 kn for p,.-p". p•• -P.,. E,SC , . SC,
• 24 kO for P,. -p". P IO -P,.
(a) CMOS Load
(b) TTL Load
Figure 9 Bus Timing Test Loads
L;nl
,nst,uctoon
_I
I~ I~ I
.,
Cycle
Internal
Add,", Bus-"'_-+'''-_-V·'--_''''"_.....J''-_-'''--_J'\._.......,'-_-'''__J,_ _''-_-'''__-'''_.......''-_--''....._ J \ ._ _
*----'"
~O"R02
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
-II-'Pes
. . . . v_---"'"-_,..-"'V'--v_-
Internal~~--"'V"-"'"""'~--v--"'V"-"'"""',..--v--"'"--"'"""'~-"""'---"'V"Oe.a Bus J \ ___"'-__- " ' - -__J\. _ _"'-_-"....._ - " ' _......" - _ - " ' - - _ - "_ _"'-_.....J"__......"-_--"......._J\._.....J"-_
'n,o,no'RIW
*IRQz .... I nternal
Interrupt \ ..._______________________________- - J1
Figure 10 Interrupt Sequence
E
Vee
~~\\\\\\\\\\\\\ ~\\\\\\\\\\\\\\\ ~ ~ rt..Il-fLr
~-::~:~
~ \)----------i~
'I
I's ..... ,..-----------'RC--------.-----·L 4;-'PCS
'~'
I
t .._o.;;.:;o._PCS
______
----------~~f~--------------------~1~
~ ~
u. S\\§\\\§\\'L\\\\§\\~ }sS\\§\\\\\\\S\\\\\S\\\\\\\v---V
~~
FFFE FFFE
'n,otno'Rffl \\\\\\\§\~ ~\\\\S\\\\\\\\\\\\\\\\\\\\\Y
~ pc::y-n<,
1-
'n ... nso'
Add,...
~:,':';~: M\\\\§\\\\\\\\\~ ,%\\\\\\\\\\\\\\\\\\\\\\\\S\'\1C!
=
PCB-PCIS PCO-PC7 F;'"
Instruction
pc::x:::x::
Figure 11 Reset Timing
48
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------~HD6801S0,HD6801S5
• SIGNAL DESCRIPTIONS
•
•
Vee and VSS
These two pins are used to supply power and ground to the
chip. The voltage supplied will be +5 volts ±5%.
• XTAL and EXTAL
These connections are for a parallel resonant fundamental
crystal, AT cut. Divide·byA circuitry is included with the
internal clock, so a 4 MHz crystal may be used to run the
system at 1 MHz. The divide-by-4 circuitry allows for use of the
inexpensive 3.58 MHz Color TV crystal for non-time critical
applications. Two 22pF capacitors are needed from the two
crystal pins to ground to insure reliable operation. An example
of the crystal interface is shown in Fig. 12. EXTAL may be
driven by an external clock source at a 4 MHz rate to run at
I MHz with 45% to 55% duty cycle. It is not restricted to 4
MHz, as it will divide by 4 any frequency less than or equal to 5
MHz. XTAL must be grounded if an external clock is used.
Nominal Crystal Parameter
~
4 MHz
5 MHz
Co
7 pF max.
4.7 pF max.
Rs
60n max.
30ntyp.
Item
XTAL 1---....- - - - - ,
CJ
EXTAL
~-.....---,
C L1
= C L2 = 22pF
± 20%
(3.2 - 5 MHz)
[Notel These are representative
AT cut parallel resonance
crystal parameters.
+r
CL1
tL2
Figure 12 Crystal Interface
• Vee Standby
This pin will supply +5 volts ±5% to the standby RAM on the
chip. The first 64 bytes of RAM will be maintained in the power
down mode with 8 rnA current max. The circuit of figure 13
can be utilized to assure that Vee Standby does not go below
V SBB during power down.
To retain information in the RAM during power down the
following procedure is necessary:
1) Write "0" into the RAM enable bit, RAME. RAME is bit
6 of the RAM Control Register at location $0014. This
disables the standby RAM, thereby protecting it at power
down.
2) Keep Vee Standby greater than VSBB.
Figure 13 Battery Backup for Vee Stl'lndbv
Reset (RES)
TIlls input is used to reset and start the MCU from a power
down condition, resulting from a power failure or an initial
startup of the processor. On power up, the reset must be held
"Low" for at least 100 ms. When reset during operation, RES
must be held "Low" at least 3 clock cycles.
When a "High" level is detected, the MCU does the following:
I) All the higher order address lines will be forced "High".
2) I/O Port 2 bits 2, I, and 0 are latched into programmed
control bits PC2, PCI and PeO.
3) The last two ($FFFE, $FFFF) locations in memory will
be used to load the program addressed by the program
counter.
4) The interrupt mask bit is set. Clear before the CPU can
recognize maskable interrupts.
• Enable (E)
This supplies the external clock for the rest of the system
when the internal oscillator is used. It is a single phase, TTL
compatible clock, and will be the divide-by-4 result of the
crystal oscillator frequency. It will drive one TTL load and
90 pF capacitance.
• Non-Maskable Interrupt (NMI)
A low-going edge on this input requests that a non-maskableinterrupt sequence be generated within the processor. As with
interrupt Request signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
has no effect on NMI.
In response to an NMI interrupt, the Index Register, Program
Counter, Accumulators, and Condition Code Register are stored
orl the stack. At the end of the sequence, a 16-bit address will
be loaded that points to a vectoring address located in memory
locations $FFFC and $FFFD. An address loaded at these locations causes the CPU to branch to a non-maskable interrupt
service routine in memory.
A 3.3 kn external resistor to Vee should be used for
wire-OR and optimum control of interrupts.
Inputs IRQ! and NMI are hardware interrupt lines that are
sampled during E and will start the interrupt routine on the
E following the completion of an instruction.
•
Interrupt Request (IRQ,)
This level sensitive input requests that an interrupt sequence
be generated within the machine. The processor will complete
the current instruction before it recognizes the request. At that
time, if the interrupt mask bit in the Condition Code Register is
not set, the machine will begin an interrupt sequence. The Index
Register, Program Counter, Accumulators, and Condition Code
Register are stored on the stack. Next the CPU will respond to
the interrupt request by setting the interrupt mask bit "High"
so that no further maskable interrupts may occur. At the end of
the cycle, a 16-bit address will be loaded that points to a vectoring address which is located in memory locations $FFF8 and
$FFF9. An address loaded at these locations causes the CPU
to branch to an interrupt routine in memory.
The IRQ! requires a 3.3 kn external resistor to Vee which
should be used for wire-OR and optimum control of inte~ts.
Internal Interrupts will use an internal interrupt line (IRQl)'
This interrupt will operate the same as IRQ. except that it will
use .the vector address of $FFFO through $FFF7. IRQ. will
have priority over IRQ2 if both occur at the same time. The
Interrupt Mask Bit in the condition code register masks both
interrupts (See Table 1).
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
49
HD6801S0,HD6801S5------------------------------------------------------Table 1 Interrupt Vector Location
Vector
MSB
Highest
Priority
Lowest
Priority
•
PORTS
There are four I/O ports on the HD6801 S MCV; three 8-bit
ports and one 5-bit port. There are two control lines associated
with one of the 8-bit ports. Each port has an associated write
only Data Direction Register which allows each I/O line to be
programmed to act as an input or an output*. A "1" in the
corresponding Data Direction Register bit will cause that I/O
line to be an output. A "0" in the corresponding Data Direction
Register bit will cause that I/O line to be an input. There are
four ports: Port 1, Port 2, Port 3, and Port 4. Their addresses
and the addresses of their Data Direction registers are given in
Table 2.
Interrupt
LSB
FFFE
FFFF
FFFC
FFFD
FFFA
FFFB
FFF8
FFF9
IRQ, (or IS3)
FFF6
FFF7
ICF (Input Capture)
FFF4
FFF5
OCF (Output Compare)
FFF2
FFF3
TOF (Timer Overflow)
FFFO
FFF1
SC, (RDRF + ORFE + TORE)
RES
NMI
Software Interrupt (SWi)
* The only exception is bit I of Port 2, which can either be data
input or Timer output.
Table 2 Port and Data Direction Register Addresses
The following pins are available in the Single Chip Mode, and
are associated with Port 3 only.
•
Input Strobe (lS3) (SCI)
This sets an interrupt for the processor when the IS3 Enable
bit is set. As shown in Figure 6 Input Strobe Timing, IS3 will
fall tiS minimum after data is valid on Port 3. If IS3 Enable is
set in the I/O Port 3 Control/Status Register, an interrupt will
occur. If the latch enable bit in the I/O Port 3 Control/Status
Register is set, this strobe will latch the input data from another
device when that device has indicated that it has valid data.
• Output Strobe (OS3) (SC 2 )
This signal is used by the processor to strobe an external
device, indicating valid data is on the I/O pins. The timing for
the Ou tpu t Strobe is shown in Figure 5. I/O Port 3 Con trol/
Status Register is discussed in the following section.
The following pins are available in the Expanded Modes.
• ReadlWrite (RM) (SC 2 )
This TTL compatible output signals the peripherals and
memory devices whether the CPU is in a Read ("High") or a
Write ("Low") state. The normal standby state of this signal is
Read ("High"). This output can drive one TTL load and 90 pF
capacitance.
•
I/O Strobe (IDS) (SCI)
In the expanded non-multiplexed mode of operation, lOS
internally decodes A9 through AI5 as "O"s and A8 as a "I".
This allows external access of the 256 locations from $0 I 00 to
$OIFF. The timing diagrams are shown as figure 2.
• Address Strobe (AS) (SCI)
In the expanded multiplexed mode of operation, address
strobe is output on this pin. This Signal is used to latch the 8
LSB's of address which are mUltiplexed with data on Port 3.
An 8-bit latch is utilized in conjunction with Address Strobe. as
shown in figure 19. So I/O Port 3 can become data bus during
the E pulse. The timing for this signal is shown in Figure I of
Bus Timing. This signal is also used to disable the address from
the multiplexed bus allowing a deselect time. tASD before the
data is enabled to the bus.
Ports
Port Address
Data Direction
Register Address
I/O Port 1
$0002
I/O Port 2
$0003
$0000
$0001
I/O Port 3
$0006
$0004
I/O Port 4
$0007
$0005
I/O Port 1
This is an 8-bit port whose individual bits may be defined as
inputs or outputs by the corresponding bit in its data direction
register. The 8 output buffers have three-state capability,
allowing them to enter a high impedance state when the
peripheral data lines are used as inputs. In order to be read
properly, the voltage on the input lines must be greater than 2.0
V for a logic "I" and less than 0.8 V for a logic "0". As outputs, these lines are TTL compatible and may also be used as
a source of up to 1 rnA at 1.5 V to directly drive a Darlington
base. After Reset, the I/O lines are configured as inputs. In all
three modes, Port I is always parallel I/O.
•
•
I/O Port 2
This port has five lines that may be defined as inputs or
outputs by its data direction register. The 5 output buffers have
three-state capability, allowing them to enter a high impedance
state when used as an input. In order to be read properly, the
voltage on the input lines must be greater than 2.0 V for a
logic "I" and less than 0.8 V for a logic "0". As outputs, this
port has no internal pullup resistors but will drive TTL inputs
directly. For driving CMOS inputs, external pullup resistors are
required. After Reset, the I/O lines are configured as inputs.
Three pins on Port 2 (pins 10, 9, and 8 of the chip) are used
to program the mode of operation during reset. The values of
these pins at reset are latched into the three MSB's (bits 7, 6,
and 5) of Port 2 which are read-only. This is explained in the
Mode Selection Section.
In all three modes, Port 2 can be configured as I/O and
provides access to the Serial Communications Interface and the
Timer. Bit I is the only pin restricted to data input or Timer
output.
• I/O Port 3
This is an 8-bit port that can be configured as I/O, a data bus,
or an address bus multiplexed with the data bus - depending on
the mode of operation hardware programmed by the user at
reset. As a data bus, Port 3 is bi-directional. As an input for
peripherals, it must be supplied regular TTL levels, that is,
greater than 2.0 V for a logic "I" and less than 0.8 V for a logic
"0"
50
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------HD6801S0,HD6801S5
Its TTL compatible three-state output buffers can drive one
TTL load and 90 pF capacitance. In the Expanded Modes, after
reset, the data direction register is inhibited and data flow depends on the state of~ R/W line. The input strobe (IS3)
and the output strobe (OS3) used for handshaking are explained
later_
In the three modes, Port 3 assumes the following characteristics:
Single Chip Mode: Parallel Inputs/Outputs as programmed by
its associated Data Direction Register. There are two control
lines associated with this port in this mode, an input strobe and
an output strobe, that can be used for handshaking. They are
controlled by the I/O Port 3 Control/Status Register explained
at the end of this section. Three options of Port 3 operations
are sumarized as follows: (1) Port 3 input data can be latched
using IS3 (SC I) as a control signal, (2) OS3 can be generated by
either an CPU read or write to Port 3's Data Register, and (3)
and IroJl interrupt can be enabled by an IS3 negative edge.
Port 3 latch and strobe timing is shown in Fig. 5 and Fig. 6.
Expanded Non-Multiplexed Mode: In this mode, Port 3
becomes the data bus (Do -D 7).
Expanded Multiplexed Mode: In this mode, Port 3 becomes
both the data bus (D o-D 7) and lower bits of the address bus
(Ao-A7)' An address strobe output is true when the address is
on the port.
load and 90 pF capacitance. After reset, the lines are configured
as inputs. To use the pins as addresses, therefore, they should
be programmed as outputs. In the three modes, Port 4 assumes
the following characteristics:
Single Chip Mode: Parallel Inputs/Outputs as programmed by
its associated Data Direction Register.
Expanded Non-Multiplexed Mode: Port 4 is configured as the
lower order address lines (Ao - A7) by writing "I"s to the data
direction register. When all eight address lines are not needed,
the remaining lines, starting with the most Significant bit, may
be used as I/O (inputs only).
Expanded Multiplexed Mode: Port 4 is configured as the
higher' order address lines (As - A1s ) by writing" 1"s to the data
direction register. When all eight address lines are not needed,
the remaining lines, starting with the most significant bit, may
be used as I/O (Inputs only).
•
OPERATION MODES
The operation modes that HD680lS will operate after
reset is determined by hardware that the user must wire on pins
to, 9, and '8 of the chip. These pins are the three LSB's (I/O 2,
I/O I, and I/O 0 respectively) of Port 2. They are latched into
programmed control bits PC2, PC I, and PCO when reset goes
high. I/O Port 2 Register is shown below.
PORT 2 DATA REGISTER
7
I/O PORT 3 CONTROL/STATUS REGISTER
153
$OOOF
Bit 0;
Bit I;
Bit 2;
Bit 3;
Bit 4;
Bit 5;
Bit 6;
Bit 7;
•
FLAG
6
5
4
TS"3
TFm\
ENABLE
X
055
o
LATCH
X
X
$0003
6
4
2
1
0
r--PC-2-TI-p-C-l~l-p-C-o-rI-I/-0-4-T1-I/-O-3-T1-1/-0-2~1-1-IO--1~1-1-10--0-'
X
ENABLE
Not used.
Not used.
Not used.
LATCH ENABLE. This controls the input latch for I/O
Port 3. If this bit is set "High" the input data will be
latched with the falling edge of the Input Strobe, IS3.
This bit is cleared by reset, and the latch is "re-opened"
with CPU read Port 3.
OSS. (Output Strobe Select) This bit will select if the
Output Strobe should be generated at OS3 (SC 2 ) by a
write to I/O Port 3 or a read of I/O Port 3. When this bit
is cleared the strobe is generated by a read Port 3. When
this bit is set the strobe is generated by a write to Port 3.
Not used.
IS3 IRQI ENABLE. When set, interrupt will be enabled
whenever IS3 FLAG is set; when clear, interrupt is
inhibited. This bit is cleared by reset.
IS3 FLAG. This is a read-only status bit that is set by
the falling edge of the input strobe, IS3 (SCd. It is
cleared by a read of the Control/Status Register followed by a read or write of I/O Port 3. Reset will clear
this bit.
I/O Port 4
This is an 8-bit port that can be configured as I/O or as
address output lines depending on the mode of operation. In
order to be read properly, the voltage on the input lines must be
greater than 2.0 V for a logic "1" and less than 0.8 V for a logic
An example of external hardware that could be used for
Mode Selection is shown in Fig. 14. The HDl4053B provides
the isolation between the peripheral device and MCU during
reset, which is necessary if data conflict can occur between
peripheral device and Mode generation circuit.
As bits 5, 6 and 7 of Port 2 are read-only, the mode cannot
be changed through software. The mode selections are shown in
Table 3.
The HD6801S can operate in three basic modes;
(1) Single Chip Mode, (2) Expanded Multiplexed Mode (compatible with HMCS6800 peripheral family) (3) Expanded NonMultiplexed Mode.
•
Single Chip Mode
In the Single Chip Mode the Ports are configured as I/O.
This is shown in Figure 16 the single Chip Mode. In this
mode, Port 3 will have two associated control lines, an input
strobe and an output strobe for handshaking data.
•
Expanded Non-Multiplexed Mode
In this mode the HD6801S will directly address HMCS6800
peripherals with no external logic. In this mode Port 3 becomes
the data bus. Port 4 becomes the A o-A 7 address bus or partial
address and I/O (inputs only). Port 2 can be parallel I/O, serial
I/O, Timer, or any combination of them. Port 1 is parallel I/O
only. In this mode the HD6801 S is expandable to 256 locations .
The eight address lines associated with Port 4 may be
substituted for I/O (inputs only) if a fewer number of address
lines will satisfy the application (See Figure 17).
"0"
As outputs, each line is TTL compatible and can drive 1 TTL
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
51
HD680'1S0,HD6801S5-------------------------Vee
(
~
~
R
R, R, R,
6
T
TT
A B
C
HD6801S
X.
Yo
X
~Zo
Y
P,o
X,
P"
Y,
P"
Z,
C
I
???
~
Mode
Control
Switch
RES
8
9
10
z
P,o (PCO)
P2
,
(PC1)
P" (PC2)
HD14053B
Inh
[NOTES]
Jr
1) Mode 7 as shown
2) RC"'Reset time constant
3) R , =10k!l
Figure 14 Recommended Circuit for Mode Selection
Truth Table
Control Input
On Switch
Inh
A
B
Binary to 1-of-2
Decoder with
Inhibit
C
xoo-----------------~~~-+~--,
X.o-------------------~~-+~--~
yoo-------------------~~~---.
y.O----------------------R~~--~
2ocr----------------------~~+-~
2.
Select
Inhibit
x
y
2
C B
A
HD14053B
0
0
0
Zo Yo Xu
0
0
0
1
Zo Yo X,
0
0
1
0
Zo Y, Xo
0
0
1
1
Zo Y, X,
0
1
0
0
Z, Yo Xo
0
1
0
1
Z, Yo X,
0
1
1
0
Z, Y, Xo
0
1
1
1
Z, Y, X,
1
X X X
0
-
Figure 15 HD14053B Multiplexers/Demultiplexers
Vee
Vee
40
2
Port 1
81/0 lines
Port 3
8 I/O Lines
Port 4
8 I/O Lines
Port 2
5 I/O Lines
Vss
SCI
Timer
Figure 16 HD6801S MCU Single-Chip Mode
52
Enable
Enable
Port 1
8 Parallel I/O
Port 3
8 Data Lines
Port 2
5 Parallel I/O
SCI
Timer
Port 4
To 8 Address
Lines or To
8 I/O Lines
(Inputs Only)
Figure 17 HD6801S MCU Expanded Non-Multiplexed Mode
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - H06801 SO,H06801S5
•
Expanded Multiplexed Mode
Vee
In this mode Port 4 becomes higher order address lines with
an alternative of substituting some of the address lines for I/O
(inputs only). Port 3 is the data bus multiplexed with the lower
order address lines differentiated by an output called Address
Strobe. Port 2 is 5 lines of Parallel I/O, SCI, Timer, or any
combination of them. Port 1 is 8 Parallel I/O lines. In this mode
it is expandable to 65k bytes. (See Figure 18).
•
Enable
Lower order Address Bus Latches
Port 1
81/0 Lines
Since the data bus is multiplexed with the lower order
address bus in Port 3, latches are required to latch those address
bits. The 74LS373 Transparent octal D-type latch can be used
with the HD6801S to latch the least significant address byte.
Figure 19 shows how to connect the latch to the HD6801S.
The output control to the 74LS373 may be connected to
ground.
8 Lines
Multiplexed
Data/Address
Port 2
5 I/O Lines
SCI
Timer
Port 4
To 8 Address
Lines or To
8 I/O Lines
(Inputs Only)
Vss
Figure 18 HD6801S MCU Expanded Multiplexed Mode
GND
AS
I
G OC
0,
Port 3
Address/Data
[
a,
1Add,~,
74LS373
D.
Function Table
Ao-A,
Output
Control
O.
L
L
L
1
H
Enable
Output
G
0
Q
H
H
L
X
H
L
X
X
H
L
a.
Z
0", 0 0 -0,
Figure 19 Latch Connection
•
Mode and Port Summary MCU Signal Description
This section gives a description of the MCU signals for the various modes. SCI and SC 2 are signals which vary with the mode
that the chip is in.
MODE
SINGLE CHIP
PORT 1
Eight Lines
PORT 2
Five Lines
I/O
PORT3
Eight Lines
PORT4
Eight Lines
SCI
SC 2
I/O
I/O
I/O
153 (I)
053(0)
ADDRESS BUS*
(As-A ls )
AS(O)
R/W(O)
ADDRESS BUS*
(Ao-A? )
105(0)
R!W(O)
EXPANDED MUX
I/O
I/O
ADDRESS BUS
(Ao-A?)
DATA BUS
(Do-O? )
EXPANDED NON-MUX
I/O
I/O
DATA BUS
(D o-D 7 )
*These lines can be substituted for I/O (Input Only) starting with the most significant address line.
I = Input
ISl.= Input Strobe
SC = Strobe Control
o = Output
OS3 = Output Strobe
AS = Address Strobe
A/W = Aead/Write
lOS = I/O Select
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
53
HD6801S0,HD6801S5------------------------------------------_____________
Table 3 Mode Selection Summary
Mode
P"
(PC2)
P21
(PCl)
P,.
(PCO)
ROM
RAM
7
6
H
H
H
I
I
H
H
L
I
I
I
I
MUX(6)
5
H
L
H
I
I
I
NMUX(6)
4
H
L
L
1(2)
I
I
3
L
H
H
E
E
E
MUX
2
L
H
L
E
I
E
MUX
Multiplexed/RAM
1
L
L
H
I
I
E
MUX
Multiplexed/RAM 8< ROM
0
L
L
L
I
I
1(3)
MUX
Multiplexed Test
LEGEND:
I -Internal
E - External
MUX - Multiplexed
NMUX - Non-Multiplexed
L - Logic "0"
H - Logic "1"
•
Interrupt
Vectors
1(1)
Operating
Mode
Single Chip
Multiplexed/Partial Decod~
Non-Multiplexed/Partial Decode
Single Chip Test
Multiplexed/No RAM 8< ROM
[NOTES)
11 Internal RAM is addressed at $XX80
2) Internal ROM is disabled
3) RES vector is external for 2 cycles after RES goes "High"
4) Addresses associated with Ports 3 and 4 are considered external in Modes 0,
1,2, and 3
5) Addresses associated with Port 3 are considered external in Modes 5 and 6
6) Port 4 default is user data input; address output is oPtional by writing to Port 4
Data Direction Register
MEMORY MAPS
•
The MCU can provide up to 65k bytes address space depending on the operating mode. A memory map for each operating
mode is shown in Figure 20. The rust 32 locations of each map
are reserved for the MCU's internal register area, as shown in
Table 4. With exceptions as indicated.
Table 4
Bus
Mode
I
INTERRUPT FLOWCHART
The Interrupt flow chart is depicted in Figure 24 and is common to every interrupt excluding reset.
Internal Register Area
Register
Port
Port
Port
Port
1
2
1
2
Data
Data
Data
Data
Direction Register···
Direction Register···
Register
Register
Port
Port
Port
Port
3
4
3
4
Data
Data
Data
Data
Direction Register···
Direction Register···
Register
Register
Address
00
01
02
03
04·
05··
06·
07· •
Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
Output Compare Register (High Byte)
08
09
OA
OB
Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Port 3 Control and Status Register
OC
00
OE
OF·
Rate and Mode Control Register
Transmit/Receive Control and Status Register
Receive Data Register
Transmit Data Register
10
11
12
13
RAM Control Register
Reserved
14
15-1F
• External address in MOde!..Q. 1, 2, 3, 5, 6; cannot be
accessed in Mode 5 (No. 105)
•• External addresses in Modes 0, 1,2,3
••• 1=Output, O=lnput.
54
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------HD680150,HD680155
HD6801S
Mode
o
HD6801S
Mode
1
Multiplexed/RAM & ROM
Multiplexed Test mode
$0000(1)
$0000(1)
Internal Registers
I nternal Registers
$001 F
$001F
External Memory Space
External Memory Space
$0080
$0080
Internal RAM
Internal RAM
$OOFF
$OOFF
External Memory Space
External Memory Space
$F800
Internal ROM
Internal ROM
$FFEF
$FFFO
I nternal Interrupt Vectors(2
(NOTESI
1) Excludes the following addresses which may
be used externally; $04, $05, $06, $07 and $OF.
2) Addresses $FFFE and $FFFF are considered
external if accessed within 2 cycles alter a
positive edge of RES and internal at all other
times.
3) After 2 CPU cycles, there must be no over·
lapping of internal and external memory
spaces to avoid driving the data bus with more
than one device.
4) This mode is the only mode which may be used
to examine the interrupt vectors in internal
ROM using an external Reset vector.
External Interrupt Vectors
$FFFF - - - - - ,
[NOTES]
1) EXCludes the following addresses which may
be used externally; $04, $05, $06, $07 and
$OF.
2) Internal ROM addresses $FFFO to $FFFF are
not usable.
Figure 20 HD6801S Memory Maps
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
55
HD6801S0,HD6801S5--------------------------------------------------____
HD6801S
Mode
2
HD6801S
Mode
Multiplexed/RAM
3
Multiplexed/No RAM or ROM
$0000(1)
$0000(1)
}
Internal Registers
Internal Registers
$OOlF
$OOlF
External Memory Space
$0080
Internal RAM
$OOFF
External Memory Space
External Memory Space
I-----I,}
$FFFO
$FFFF ' -_ _ _--'
External Interrupt Vectors
$FFFO~---~~
$FFFF ...._ _ _..... }
[NOTE]
[NOTE]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07, ~nd
$OF.
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and
$OF.
Figure 20
56
External Interrupt Vectors
HD6801S Memory Maps
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------HD6801S0,HD6801S5
HD6801S4
Mode
Single Chip Test
HD6801S
Mode
5
Non-Multiplexed/Partial Decode
$0000
Internal Registers
$001F
$0080
} Internal RAM
$OOFF
$0100
$01 FF '--_....-_....
} External Memory Space
(1)(4)
$F800
Internal ROM
$XX80
$XXFF
Internal RAM
} Internal Interrupt Vectors
[NOTES)
,) The internal ROM is disabled.
2) Mode 4 may be changed to Mode 5 without
having to assert RESET by writing a "'" into
the peo bit of Port 2 Data Register.
3) Addresses A. to A, 5 are treated as "don't
cares" to decode internal RAM.
4) Internal RAM will appear at $XX80 to $XXFF.
$FFFF
Internal Interrupt Vectors
[NOTES)
1) Excludes the following addresses which may
not be used externally": $04, $06, and $OF.
(No lOS)
2) This mode may be entered without going
through RES by using Mode 4 and subsequently writing a "1" into the peo bit of
Port 2 Data Register.
3) Address lines A. - A, wi II not contain addresses until the Data Direction Register for Port 4
has been written with '" 's" in the appropriate
bits. These address lines will assert ""s" until
made outputs by writing the Data Direction
Register.
Figure 20 HD6801S Memory Maps (Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
57
HD6801S0,HD6801S5~---------------------------------------------------
HD6801S
Mode
6
HD6801S7
Mode
Single Chip
Multiplexed/Partial Decode
$0000(1)
$001F
$OOOO~}
Internal Registers
Internal Registers
$001 F ~~~~(4
Unusable
$0080
External Memory Space
$0080
Internal RAM
$ooFF
$OOFF
External Memory Space
$F800
$F8oo
Internal ROM
Internal ROM
Internal Interrupt Vectors
Int.ernal Interrupt Vectors
$FFFF
[NOTES)
1) Excludes the following address which may be
used externally: $04, $06, $OF.
2) Address lines A.-A" will not contain
addresses until the Data Direction Register for
Port 4 has been written with "1's" in the
appropriate bits. These address lines will
assert "1's" until made outputs by writing the
Data Direction Register.
Figure 20 HD6801S Memory Maps (Continued)
58
~HITACftl
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - H D 6 8 0 1 SO,HD6801 55
•
PROGRAMMABLE TIMER
The HD6801S contains an on-chip 16-bit programmable
timer which may be used to perform measurements on an input
waveform while independently generating an output waveform.
Pulse widths for both input and output signals may vary from a
few microseconds to many seconds. The timer hardware consists
of
• an 8-bit control and status register,
• a 16-bit free running counter,
• a 16-bit output compare register, and
• a 16-bit input capture register
A block diagram of the timer registets is sh9wn in Figure 21.
•
Free Running Counter ($0009:$000A)
The key element in the programmable timer is a 16-bit free
running counter which is driven to increasing values by E (Enable). The counter value may be read by the CPU software at
any time. The counter is cleared to zero by reset and may be
considered a read-only register with one exception. Any CPU
write to the counter's address ($09) will always result in preset
value of $FFF8 being loaded into the counter regardless of the
value involved in the write. This preset figure is intended for
testing operation of the part, but may be of value in some
applications.
•
Output Compare Register ($OOOB:$OOOC)
The Output Compare Register is a 16-bit read/write register
which is used to control an output waveform. The contents of
this register are constantly compared with the current value of
the free running counter. When a match is found, a flag is set
(OCF) in the Timer Control and Status Register (TCSR) and the
current value of the Output Level bit (OLVL) in the TCSR is
clocked to the Output Level Register. Providing the Data
Direction Register for Port 2, Bit 1 contains a "1" (Output),
the output level register value will appear on the pin for Port 2
Bit 1. The values in the Output Compare Register and Output
level bit may then be changed to control the output level on the
next compare value. The Output Compare Register is set to
$FFFF during RES. The Compare function is inhibited for
one cycle following a write to the high byte of the Output
Compare Register to insure a valid 16-bit value is in the register
before a compare is made.
•
Input Capture Register ($OOOD:$OOOE)
The Input Capture Register is a 16·bit read-only register used
to store the current value of the free running counter when the
proper transition of an external input signal occurs. The input
transition change required to trigger the counter transfer is
controlled by the input Edge bit (IEDG) in the TCSR. The Data
Direction Register bit for Port 2 Bit 0, should* be clear (zero)
in order to gate in the external input signal to the edge detect
unit in the timer.
The input pulse width must be at least two E-cycles to ensure
an input capture under all conditions.
*
•
With Port 2 Bit 0 configured as an output and set to "1", the
external input will still be seen by the edge detect unit.
Timer Control and Status Register (TCSR) ($0008)
The Timer Control and Status Register consists of an 8-bit
register of which all 8 bits are readable but only the low order 5
bits may be written. The upper three bits contain read-only
timer status information and indicate the followings.
• a proper transition has taken place on the input pin with a
subsequent transfer of the current counter value to the
input capture register.
• a match has been found between the value in the free
running counter and the output compare register, and
• when $0000 is in the free running counter.
Each of the flags· may be enabled onto the HD6801 internal
bus (IRQ2) with an individual Enable bit in the TCSR. If the
HD6801 S Internal Bus
Output Input
Figure 21
Level
Edge
81t 1
Port 2
Sit 0
Port 2
~
Block Diagram of Programmable Timer
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
59
HD6801S0,HD6801S5----------------------------------------------------Timer Control and Status Register
5
6
ICF I OCF
4
1
0
TOF I EICI I EOCI I ETOIIIEDG I OLVLI $0008
I-bit in the HD6801S Condition Code Register has been cleared,
a priority vectored interrupt will occur corresponding to the flag
bit(s) set. A description for each bit follows:
Bit 0 OLVL Output Level - This value is clocked to the output
level register on a successful output compare. If
the DDR for Port 2 bit I is set, the value will
appear on the output pin.
Bit I IEDG Input Edge - This bit controls which transition of
an input will trigger a transfer of the counter to
the input capture register. The DDR for Port 2 Bit
o must be clear for this function to operate. IEDG
= 0 Transfer takes place on a negative edge
("High"-to-"Low" transition).
.
IEDG = I Transfer takes place on a positive edge
("Low"-to-"High" transition).
Bit 2 ETOI Enable Timer Overflow Interrupt - When set, this
bit enables IR0 2 to occur on the internal bus for a
TOF interrupt; when clear the interrupt is inhibited.
Bit 3 EOCI Enable Output Compare Interrupt - When set,
this bit enables IR0 2 to appear on the internal bus
for an output compare interrupt; when clear the
interrupt is inhibited.
Bit 4 EICI Enable Input Capture Interrupt- When set, this
bit enables IR0 2 to occur on the internal bus for
an input capture interrupt; when clear the interrupt is inhibited.
Bit 5 TOF Timer Overflow Flag - This read-only bit is set
when the counter contains $FFFF. It is cleared by
a read of the TCSR (with TOF set) followed by an
CPU read of the Counter ($09).
Bit 6 OCF Output Compare Flag - This read-only bit is set
when a match is found between the output
compare register and the free running counter. It is
cleared by a read of the TCSR (with OCF set)
followed by an CPU write to the output compare
register ($OB or $OC).
Bit 7 ICF
Input Capture Flag - This read-only status bit is
set by a proper transition on the input; it is~cleared
by a read of the TCSR (with ICF set) followed by
an CPU read of the Input Capture Register ($OD).
CPU via the data bus and with the outside world via pins 2, 3,
and 4 of Port 2. The hardware, software, and registers are explained in the following paragraphs.
• Wake-Up Feature
In a typical multi-processor application, the software
protocol will usually contain a destination address in the initial
byte(s) of the message. In order to permit non-selected MCU's
to ignore the remainder of the message, a wake-up feature is
included whereby all further interrupt processing may be
optionally inhibited until the beginning of the next message.
When the nex t message appears, the hardware re-enables (or
"wakes-up") the for the next message. The "wake-up" is
automatically triggered by a string of ten consecutive I's which
indicates an idle transmit line. The software protocol must
provide for the short idle period between any two consecutive
messages.
• Programmable Options
The following features of the HD680lS serial I/O section are
programmable:
· format - standard mark/space (NRZ)
• Clock - external or internal
• baud rate - one of 4 per given CPU ¢2 clock frequency or
external clock >-8 input
• wake-up feature - enabled or disabled
• Interrupt requests - enabled or masked individually for
transmitter and receiver data registers
• clock output - internal clock enabled or disabled to Port
2 (Bit 2)
• Port 2 (bits 3 and 4) - dedicated or not dedicated to serial
I/O individually for transmitter and receiver.
• Seri~1 Communication Hardware
The serial communication hardware is controlled by 4
registers as shown in Figure 22. The registers include:
• an 8-bit control and status register
• a 4-bit rate and mode control register (write-only)
• an 8-bit read-only receive data register and
• an 8-bit write-only transmit data register.
In addition to the four registers, the serial I/O section utilizes
bit 3 (serial input) and bit 4 (serial output) of Port 2. Bit 2 of
Port 2 is utilized if the internal-clock-out or external-clock-in
options are selected .
• SERIAL COMMUNICATION INTERFACE
The HD680lS contains a full-duplex asynchronous serial
communication interface (SCI) on chip. The controller
comprises a transmitter and a receiver which operate independently or each other but in the same data format and at the same
data rate. Both transmitter and receiver communicate with the
Transmit/Receive Control and Status (TRCS) Register
The TReS register consists of an 8-bit register of which all 8
bits may be read while only bits 0-4 may be written. The
register is initialized to $20 by reset. The bits in the TRCS
register are det1ned as follows:
Transmit/Receive Control and Status Register
7
6
5
4
3
0
1.R_D_R_ELI_o_R_F_E"'I_T_D_R_E...I.......
R_I_E_IL--R_E...&.I_T_IE-..I_T_E_L--W_u-..II
1
60
ADDR : $0011
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - H D 6 8 0 1 SO,HD6801S5
Bit 7
Rate and Mode Control Register
I
I I I I
CCl
CCO
SSl
Bit 0
SSO
1$10
Transmit/Receive Control and Status Register
Port 2
Receive Shift Register
Clock
10
Bit ....- " ' - - - - - - - - + 1
2
T.
Bit
4
j+----E
12
Transmit Data Register
Figure 22 Serial I/O Registers
writing a new byte into the transmit data register,
TDRE is initialized to I by reset.
Bit 6 ORFE Over-Run-Framing Error - set by hardware when
an overrun or framing error occurs (receive only).
An overrun is defined as a new byte received with
last byte still in Data Register/Buffer. A framing
error has occurred when the byte boundaries in bit
stream are not synchronized to bit counter. The
oRFE bit is cleared by reading the status register,
then reading the Receive Data Register, or by
reset.
Bit 7 RDRF Receiver Data Register Full - Set by hardware
when a transfer from the input shift register to the
receiver data register is made. The RDRF bit is
cleared by reading the status register, then reading
the Receive Data Register, or by reset.
Bit 0 WU
"Wake-up" on Next Message - set by HD6801S
software and cleared by hardware on receipt of
ten consecutive l's or reset of RE flag. It should
be noted that RE flag should be set in advance of
CPU set of WU flag.
Bit 1 TE
Transmit Enable - set by HD6801S to produce
preamble of nine consecutive l's and to enable
gating of transmitter output to Port 2, bit 4
regardless of the DDR value corresponding to this
bit; when clear, serial I/O has no effect on Port 2
bit 4.
TE set should be after at least one bit time of data
transmit rate from the set-up of transmit data
rate and mode.
Bit 2 TIE
Transmit Interrupt Enable - when set, will permit
an IRQ2 interrupt to occur when bit 5 (TDRE) is
set; when clear, the TDRE value is masked from
the bus.
Receiver Enable - when set, gates Port 2 bit 3 to
Bit 3 RE
input of receiver regardless of DDR value for this
bit; when clear, serial I/O has no effect on Port 2
bit 3.
Bit 4 RIE
Receiver Interrupt Enable - when set, will permit
an IRQ2 interrupt to occur when bit 7 (RDRF) or
bit 6 (ORFE) is set; when clear, the interrupt is
masked.
Bit 5 TORE Transmit Data Register Empty - set by hardware
when a transfer is made from the transmit data
register to the output shift register. The TDRE bit
is cleared by reading the status register, then
Rate and Mode Control Register
The Rate and Mode Control register controls the following
serial I/O variables:
• Baud rate
• format
• clocking source, and
• Port 2 bit 2 configuration
The register consists of 4 bits all of which are wri te-only and
cleared by reset. The 4 bits in the register may be considered as
a pair of 2-bit fields. The two low order bits control the bit rate
for internal clocking and the remaining two bits control the
format and clock select logic. The register definition is as
follows:
Rate and Mode Control Register
6
x
X
4
X
X
3
2
CC1
cco
I I I
0
SS1
SSO
ADDR : $0010
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
61
HD6801S0,HD6801S5----------------------------------------------------Bit 0 SSO} Speed Select - These bits select the Baud rate for
Bit 1 SS1 the internal clock. The four rates which may be
selected are a function of the CPU tP2 clock
frequency. Table 5 lists the available Baud rates.
Bit 2 CCO} Clock Control and Format Select - this 2·bit field
Bit 3 CC1 controls the format and clock select logic. Table 6
defines the bit field.
Table 5 SCI Bit Times and Rates
XTAL
2.4576 MHz
4.0 MHz
4.9152 MHz*
E
614.4 kHz
1.0 MHz
1.2288 MHz
SS1 : SSO
0
0
E+ 16
26 J.Ls/38,400 Baud
16 J.Ls/62,500 Baud
13 J.LsI76,800 Baud
0
1
E + 128
208 J.Ls/4,800 Baud
128 J.LsI7812.5 Baud
104.2 J.Ls/9,600 Baud
1
0
E + 1024
1.67 ms/600 Baud
1.024 ms/976.6 Baud
833.3 J.Ls/1 ,200 Baud
1
1
E + 4096
6.67 ms/150 Baud
4.096 ms/244.1 Baud
3.33 ms/300 Baud
* HD6801S5 Only
Table 6 SCI Format and Clock Source Control
Port 2 Bit 2
Port 2 Bit 3
Port 2 Bit 4
0
0
-
-
-
**
**
0
1
NRZ
Internal
Not Used
**
**
1
0
NRZ
Internal
Output*
**
**
1
NRZ
External
Input
**
**
CC1:CCO
1
•
Format
Clock Source
Clock output is available regardless of values for bits RE and TE.
Bit 3 is used for serial input if RE = "1" in TRCS; bit 4 is used for serial output if TE
Internally Generated Clock
If the user wishes for the serial I/O to furnish a clock, the
following requirements are applicable:
o the values of RE and TE are immaterial.
o CCl, CCO must be set to 10
o the maximum clock rate will be E + 16.
o the clock will be at Ix the bit rate and will have a rising
edge at mid·bit.
Externally Generated Clock
If the user wishes to provide an external clock for the serial
I/O, the following requirements are applicable:
o the CC 1, CCO, field in the Rate and Mode Control Register
must be set to 11,
o the external clock must be set to 8 times (x 8) the desired
baud rate and
o the maximum external clock frequency is 1.0 MHz.
• Serial Operations
The serial I/O hardware should be initialized by the
HD6801S software prior to operation. This sequence will
normally consist of;
o writing the desired operation control bits to the Rate and
Mode Control Register and
o writing the desired operational control bits in the Transmit/
Receive Control and Status Register.
The Transmitter Enable (TE) and Receiver Enable (RE) bits
may be left set for dedicated operations.
62
= "1" in TRCS.
Transmit Operations
The transmit operation is enabled by the TE bit in the
Transmit/Receive Control and Status Register. This bit when
set, gates the output of the serial transmit shift register to Port 2
Bit 4 and takes unconditional control over the Data Direction
Register value for Port 2, Bit 4.
Following a RES the user should configure both the Rate
and Mode Control Register and the Transmit/Receive Control
and Status Register for desired operation. Setting the TE bit
during this procedure initiates the serial output by first
transmitting a nine·bit preamble of 1's. Following the preamble,
internal synchronization is established and the transmitter
section is ready for operation.
At this point one of two situation exist:
I) if the Transmit Data Register is empty (TORE = 1), a
continuous string of ones will be sent indicating an idle
line, or,
2) if data has been loaded into the Transmit Data Register
(TORE = 0), the word is transferred to the output shift
register and transmission of the data word will begin.
During the data transmit, the 0 start bit is first transmitted.
Then the 8 data bits (beginning with bit 0) followed by the stop
bit, are transmitted. When the Transmitter Data Register has
been emptied, the hardware sets the TORE flag bit.
If the HD6801S fails to respond to the flag within the proper
time, (TORE is still set when the next normal transfer from th~
parallel data register to the serial output register should occur)
then a 1 will be sent (instead of a 0) at "Start" bit time,
followed by more I's until more data is supplied to the data
register. No O's will be sent while TORE remains a 1.
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------HD6801S0,HD6801S5
Receive Operation
The receive operation is enabled by the RE bit which gates in
the serial input through Port 2 Bit 3. The receiver section
operation is conditioned by the contents of the Transmit/
Receive Control and Status Register and the Rate and Mode
Control Register.
The receiver bit interval is divided into 8 sub-intervals for
internal synchronization. In the NRZ Mode, the received bit
stream is synchronized by the first 0 (space) encountered.
The approximate center of each bit time is strobed during
the next 10 bits. If the tenth bit is not a 1 (stop bit) a framing
error is assumed, and bit ORFE is set. If the tenth bit as a I, the
data is transferred to the Receive Data Register, and interrupt
flag RDRF is set. If RDRF is still set at the next tenth bit time,
ORFE will be set, indicating an over-run has occurred. When the
HD6801S responds to either flag (RDRF or ORFE) by reading
the status register followed by reading the Data Register, RDRF
(or ORFE) will be cleared.
• RAM CONTROL REGISTER
This register, which is addressed at $0014, gives status
information about the standby RAM. A "0" in the RAM enable
bit (RAM E) will disable the standby RAM, thereby protecting
it at power down if Vee Standby is held greater than VSBB
volts, as explained previously in the signal description for Vee
Standby.
• Condition code register manipulation instructions -- Table 10
• Instructions Execution times in machine cycles - Table
II
• Summary of cycle by cycle operation - Table 12
· Op codes Map - Table 13
• CPU Programming Model
The programming model for the HD6801S is shown in Figure
23. The double (D) accumulator is physically the same as the
Accumulator A concatenated with the Accumulator B so that
any operation using accumulator D will destroy information in
A and B.
8·Blt Accumulators A and B
Or 16·81t Double Accumulator D
115
X
01
Index Register (Xl
115
SP
01
Stack POinter (S?)
15
PC
01
Program Counter (PC)
1
Condition Code Register (eGR)
RAM Control Register
$0014
Carry IBorrow from MSB
OverflOW
~1__5_~_B_: ~I~R_A_M_E_~I_x__~I__x__L-_x__~_x__~_X ~_x~
__
Zero
Negative
__
Bit 0 Not used.
Bit 1 Not used.
Bit 2 Not used.
Bit 3 Not used.
Bit 4 Not used.
Bit 5 Not used.
Bit 6 RAME The RAM Enable control bit allows the user the
ability to disable the standby RAM. This bit is set
to a logic" 1" by RES which enables the standby
RAM and can be written to one or zero under program control. When the RAM is disabled, data is
read from external memory.
Big 7 STBY The Standby Power bit is cleared when the standPWR by voltage is removed. This bit is a read/write status flag that the user can read which indicates that
the standby RAM voltage has been applied, and
the data in the standby RAM is valid.
• GENERAL DESCRIPTION OF INSTRUCTION SET
The HD6801S is upward object code compatible with the
HD6800 as it implements the full HMCS6800 instruction set.
The execution times of key instructions have been reduced to
increase throughout. In addition, new instructions have been
added; these include 16-bit operations and a hardware multiply.
Included in the instruction set section are the following:
• CPU Programming Model (Figure 23)
• Addressing modes
• Accumulator and memory instructions - Table 7
• New instructions
• Index register and stack manipulations instructions - Table
8
• Jump and branch instructions - Table 9
Interrupt
Half Carry (F rom Sit 3)
Figure 23 CPU Programming Model
•
CPU Addressing Modes
The HD6801S eight-bit microcomputer unit has seven
address modes that can be used by a programmer, with the
addressing mode a function of both the type of instruction and
the coding within the instruction. A summary of the addressing
modes for a particular instruction can be found in Table 11
along with the associated instruction execution time that is
given in machine cycles. With a clock frequency of 4 MHz, these
times would be microseconds.
Accumulator (ACCX) Addressing
In accumulator only addressing, either accumulator A or
accumulator B is specified. These are one-byte instructions.
Immediate Addressing
In immediate addressing, the operand is contained in the
second byte of the instruction except LDS and LDX which have
the operand in the second and third bytes of the instruction.
The CPU addresses this location when it fetches the immediate
instruction for execution. These are two or three-byte instructions.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
63
HD6801S0,HD6801S5----------------------------------------------------Table 7 Accumulator & Memory Instructions
Condition Code
Addressing Modes
Mnemonic
Operations
IMMED.
OP
8B
INDEX
DIRECT
-
#
OP
2
2
9B
-
#
OP
3
2
AB
Register
EXTEND
IMPLIED
-
#
OP
-
#
4
2
BB
4
3
A + M-+A
OP
-
#
ADDA
ADDB
CB
2
2
DB
3
2
EB
4
2
FB
4
3
B+M-B
Add Double
ADDD
C3
4
3
03
5
2
['3
6
2
F3
6
3
A:B+M:M+l-A:B
Add Accumulators
ABA
Add With Carry
ADCA
89
2
2
99
3
2
A9
4
2
B9
4
3
A+M+C-A
ADCB
C9
2
2
09
3
2
E9
4
2
F9
4
3
B+M+C-B
ANDA
84
2
2
94
3
2
A4
4
2
B4
4
3
A'M-A
AN DB
C4
2
2
04
3
2
E4
4
2
F4
4
3
B·M- B
Bit Test
BIT A
85
2
2
95
3
2
A5
4
2
B5
4
3
A·M
BIT B
C5
2
2
05
3
2
E5
:4
2
F5
4
3
B'M
Clear
CLR
6F
6
2
7F
6
3
00- M
Compare
lB
2
1
4F
2
1
CLRB
5F
2
1 00 .... B
81
2
2
91
3
2
Al
4
2
Bl
4
3
A-M
CMPB
Cl
2
2
01
3 ,2
El
4
2
Fl
4
3
B-M
Compare
Accumulators
CBA
Complement, l's
COM
11
63
6
2
73
6
2
1
A-B
M .... M
3
COMA
43
2
1
A -A
COMB
53
2
1
B -B
40
2
1
OO-A-A
50
2
1
OO-B .... B
Decimal Adjust. A
DAA
19
2
1
Converts binary add of BCD
characters into BCD format
Decrement
DEC
4A
2
1
A -1- A
5A
2
1
B-1 - B
A@ M .... A
6
2
7A
6
6
3
DECB
Exclusive OR
Increment
EORA
88
2
2
98
3
2
A8
4
2
EORB
C8
2
2
08
3
2
E8
4
2
6C
6
2
INC
B8
4
3
F8
4
3
B @ M .... B
7C
6
3
M+1-M
INCA
4C
2
1
A + 1 .... A
INCB
5C
2
1
8 + 1 .... 8
LDAA
86
2
2
96
3
2
A6
4
2
86
4
3
M .... A
LDAB
C6
2
2
06
3
2
E6
4
2
F6
4
3
M .... 8
Load Double
Accumulator
LDD
CC
3
3
DC 4
2
EC
5
2
FC
5
3
Multiply Unsigned
MUL
OR, Inclusive
ORAA
8A
2
2
9A
3
2
AA 4
2
BA
4
3
ORAB
CA
2
2
DA 3
2
EA
2
FA
4
3
Load
Accumu lator
Push Data
4
PSHA
Pull Data
37
3
1
B .... Msp, SP - 1 .... SP
4
1
SP + 1 .... SP, Msp .... A
33
4
1
SP + 1 .... SP, Msp .... B
49
2
1
69
6
2
79
6
3
ROLB
..
ROR
59
66
6
2
76
6
2
1
3
RORA
46
2
1
RORB
56
2
1
~) l..o1
II
C b7
B
i I I I IIJ
bo
~l L:cH
II IIII
C b7
B
R
t
R
·•
R
S R R
R
S R R
R
S R R
t
t
t
t
t
t t
t
t
R
S
R
S
t
t
t
t
t
t
t
t
t
t
t
t @ •
t t
t
t
·· ··
·· ··
·· ··
·
· ··
·· ··
·· ·· ·
·· ·· ·
·· ··
··· ··· ···
··· ··· · · · ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
··· ···
·· ··
··
R S
(1)~
(L (2;
(f,
~,
t
@
t @ •
t
(4) •
t
R
R
@ •
(5) •
(5, •
R
R
t t
R
t
t
R
t t
t
t
t
6
6 I
I~
bO
t
I
I
6
I
I
I
6
I
R
I
I
I
6
t
t
6
I
(Continued)
The Condition Code Register notes are listed after Table 10 .
··
R
R
I
A .... Msp, SP - 1 .... SP
32
ROL
t
t
t
t
t
®
PULA
ROLA
Rotate Right
1
t
t
I
PSHB
PULB
Rotate Left
A x 8 .... A: B
8 + M- 8
3
t
t
t ~ ~
t ~ t
t t t
t ~ t
t t t
t t t
t
t t
t t
t t
t t
t t
A + M .... A
36
··
· ·•
··
·· ··
·· ··
·· ·•
··· ···
t
t
t
M + 1 .... 8, M .... A
3D 10 1
C
t
t
t
t
t
M-1 -M
3
DECA
0
V
t
NEGA
NEGB
6A
70
OO-M-M
NEG
2
1
N Z
t
(Negate)
6
2
I
t
Complement, 2's
60
3
H
t
00- A
CMPA
4
t
t
A+B- A
CLRA
5
t
t
Add
AND
64
Boolean/
Arithmetic Operation
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------HD6801S0,HD6801S5
Table 7 Accumulator & Memory Instructions
(Continued)
Condition Code
Register
Addressing Modes
Operations
Mnemonic
IMMED.
OP
Shift Left
Arithmetic
Double Shift
Left, Arithmetic
Shift Right
Arithmetic
Shift Right
Logical
Double Shift
Right Logical
-
#
INDEX
DIRECT
OP
-
#
ASL
EXTEND
OP
-
#
OP
-
#
68
6
2
78
6
3
OP
-
#
M}
_
[}+-{IIIII I I
48
2
1
ASLB
58
2
1
3
1 ~
05
ASLD
A
B
C
6
2
77
6
3
ASRA
47
2
1
ASRB
57
2
1
64
LSR
6
2
74
6
3
LSRA
44
2
1
LSRB
54
2
1
LSRD
04
3
1
~}
A~~ A7 A~~ II
Aq B7
--
3
2
A7
4
2
B7
4
3
07
3
2
E7
4
2
F7
4
3
Store Double
Accumulator
STD
DO 4
2
ED
5
Subtract
SUBA
80
2
2
90
3
2
AD
SUBB
CO
2
2
DO
3
2
EO
Double Subtract
SUBD
83
4
3 93
5
2
Subtract
Accumulators
SBA
SBCA
82
2
2
92
3
SBCB
C2
2
2
02
3
1_0
BQ
C?I IIIIII~
b7
bO
B
~}o~
B
b7
-
I IIIIIII~
bO
------+
97
1-0
bO
b7
A7
67
ASR
STAB
Subtract
With Carry
IMPLIED
ASLA
STAA
Store
Accumulator
Booleanl
Arithmetic Operation
0-01
ACC AI ACC B
A7
AO
B7
~
BO
A--- M
B ___ M
A ___ M
B ___ M+1
2
FD
5
3
4
2
BO
4
3
A-M---A
4
2
FO
4
3
B-M---B
A3
6
2
B3
6
3
A: B - M :M+1---A: B
2
A2
4
2
82
4
3
A-M-C---A
2
E2
4
2
F2
4
3
B-M-C---B
10
2
1
A-B---A
Transfer
Accumulators
TAB
16
2
1
A---B
TBA
17
2
1
B---A
Test Zero or
Minus
TST
60
6
2
70
6
M -00
3
TSTA
40
2
1
A-DO
TSTB
50
2
1
B - 00
. .
The Condition Code Re!llster notes are listed after Table 10 .
Direct Addressing
In direct addressing, the address of the operand is contained
~ the second byte of the instruction. Direct addressing allows
the user to directly address the lowest 256 bytes in the machine
i.e., locations zero through 255. Enhanced execution times are
achieved by storing data in these locations. In most configurations, it should be a random access memory. These are two-byte
instructions.
Extended Addressing
In extended addressing, the address contained in the second
byte of the instruction is used as the higher eight-bits of the
address of the operand. The third byte of the instruction is used
as the lower eight-bits of the address for the operand. This is an
absolute address in memory. These are three-byte instructions.
Indexed Addressing
In indexed addressing, the address contained in the second
byte of the instruction is added to the index register's lowest
5
4
3 2
1
0
H
I
N Z
V
C
··• ··•
· ··
··· ··
·· ·•
·• ··
·· ··
·
··· ··
·· ··
··· ···
·· ··
·· ··
t
t
t ®t
t @t
t
t
l®
t
t
t
®
®
®
®
t
t
t
t t
t t
R t
R t
R t
(§)
®
®
t
t
t
t
t
t
R
t
@ t
t
t
t
t
R
t
t
R
R
··
·
t
t
t
t
t
t
t
t
t
t
t
t t
.. r--
t
t
1
t
t t t
t R
t R
t
t
t
t
t
:
t
t
t
:
··
R R
t R R
t
R R
eight bits in the CPU. The carry is then added to the higher
order eight bits of the index register. This result is then used to
address memory. The modified address is held in a temporary
address register so there is no change to the index register. These
are two-byte instructions.
Implied Addressing
In the implied addressing mode the instruction gives the
address (i.e., stack pointer, index register, etc.). These are
one-byte instructions.
Relative Addressing
In relative addressing, the address contained in the second
byte of the instruction is added to the program counter's lowest
eight bits plus two. The carry or borrow is then added to the
high eight bits. This allows the user to address data within a
range of -126 to + 129 bytes of the present instruction. These
are two-byte instructions.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
65
HD6801S0,HD6801S5------------------------------------------------------•
New Instructions
In addition to the existing 6800 Instruction Set, the following new instructions are
incorporated in the HD6801S Microcomputer.
ABX
Adds the 8-bit unsigned accumulator B to the 16-bit X-Register taking into account
the possible carry out of the low order byte of the X-Register.
ADDD Adds the double precision ACCD* to the double precision value M:M+l and places
the results in ACCD.
ASLD Shifts all bits of ACCD one place to the left. Bit 0 is loaded with zero. The C bit is
loaded from the most significant 'bit of ACCD.
LDD
Loads the contents of double precision memory location into the double
accumulator A:B. The condition codes are set according to the data.
LSRD Shifts all bits of ACCD one place to the right. Bit 15 is loaded with zero. The C bit
is loaded from the least significant bit to ACCD.
MUL
Multiplies the 8 bits in accumulator A with the 8 bits in accumulator B to obtain a
16-bit unsigned number in A:B, ACCA contains MSB of result.
PSHX The contents of the index register is pushed onto the stack at the address contained
in the stack pointer. The stack pointer is decremented by 2.
PULX The index register is pulled from the stack' beginning at the current address
contained in the stack pointer +1. The stack pointer is incremented by 2 in total.
STD
Stores the contents {)f double accumulator A:B in memory. The contents of ACCD
remain unchanged.
SUBD Subtracts the contents of M:M + I from the contents of double accumulator AB
and places the result in ACCD.
BRN
Never branches. If effect, this instruction can be considered a two byte NOP (No
operation) requiring three cycles for execution.
CPX
Internal processing modified to permit its use with any conditional branch instruction.
*ACCD is the 16 bit register (A:B) formed by concatenating the A and B accumulators. The A-accumulator is the most significant byte.
Table 8 Index Register and Stack Manipulation Instructions
Condition Code
Register
Addressing Modes
Pointer Operations
Mnemonic
Compare Index Reg
CPX
Decrement I ndex Reg
DEX
Decrement Stack Pntr
Increment Index Reg
IMMED.
DIRECT
OP
-
#
OP
-
8C
4
3
9C
5
EXTND
INDEX
-
#
OP
2
AC 6
IMPLIED
#
OP
-
2 BC 6
#
OP
-
Booleanl
Arithmetic Operation
#
3
X-M: M+ 1
09
3
1
X-1-+X
DES
34
3
1
SP - 1 -+ SP
INX
08
3
1
X+1-+X
Increment Stack Pntr
INS
31
3
1
SP + 1 -+ SP
Load Index Reg
LOX
CE
3
3
Load Stack Pntr
LOS
8E
3
3
Store I ndex Reg
STX
Store Stack Pntr
STS
Index Reg -+ Stack Pntr
TXS
EE 5 2 FE
2 AE 5 2 BE
OF 4 2 EF 5 2 FF
9F 4 2 AF 5 2 BF
DE
4
9E
4
2
5
3
5
3
M-+ X H • (M+ 1)-+ XL
M-+ SP H . (M+1)-+SP L
5
3
X H -+ M. XL -+ (M + 1)
5
3
SP H -+ M. SP L -+ (M+ 1)
35
3
1
X-1-+SP
Stack Pntr -+ Index Reg
TSX
30
3
1
SP + 1-+ X
Add
ABX
3A
3
1
B+X-+X
Push Data
PSHX
3C
4
1
XL -+ M sP • SP - 1 -+ SP
XH-+ Msp. SP -1-+ SP
Pull Data
PULX
38
5
1
SP + 1 -+ SP. Msp -+ X H
SP + 1 -+ SP. MsP - XL
2
5
4
3
H
I
N Z
V
C
t
t
t
1 0
··· ··• ·· • ·• ·••
··• ·· ·• • ·• ••
·• • ··•
·• •• · · • ••
·· · ·· ·· ··• ·
· ·• · ·• • ·•
· ·
t
t
t
• 1(1)
t
R
.(j)t
R
.(j) t
1J t
R
R
The Condition Code Register notes are listed after Table 10.
66
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
i
- - - - - - - - - - - - - - - - - - - - - - - - - - - H D 6 8 0 1 SO,HD6801S5
Table 9 Jump and Branch Instructions
Condition Code
Register
Addressing Modes
Operations
Mnemonic
RELATIVE
OP
Branch Always
-
#
DIRECT
OP
-
#
INDEX
OP
-
IMPLIED
EXTND
#
OP
-
Branch Test
#
OP
-
#
20
Branch Never
BRN
21
3 2
None
Branch If Carry Clear
BCC
24
3
2
C=O
Branch If Carry Set
BCS
25
3
2
C=l
Branch If = Zero
BEQ
27
3
2
Z=1
Branch If ;> Zero
BGE
2C
3
2
N
> Zero
BGT
2E
3
2
Z + (N
Branch If Higher
BHI
22
3
2
C+Z=O
< Zero
BlE
2F
3
2
Z + (N
BlS
23
3
2
C+Z=1
Branch If
Branch If
Branch If lower Or
Same
< Zero
2
e V=O
e V) = 0
20
3
2
N
BMI
2B
3
2
N=1
Branch If
Branch If Not Equal
Zero
BNE
26
3
2
Z=O
Branch If Overflow
Clear
BVC
28
3
2
v=o
Branch If Overflow Set
BVS
29
3
2
V =1
Branch If Plus
BPl
2A
3
2
N=O
80
6
2
Branch To Subroutine
BSR
Jump
JMP
Jump To Subroutine
JSR
No Operation
NOP
01
Return From Interrupti
RTI
3B 10 1
Return From
Subroutine
RTS
39
Software Interrupt
SWI
3F 12 1
Wait for Interrupt
WAI
3E
6E
90
Table10
5
2
3
2
7E
3
3
AD 6
2
BD 6
3
2
5
9
1
e V) = 1
e V= 1
BlT
Branch If Minus
Advances Prog. Cntr.
Only
3
2
1
0
I
N Z
V
C
· ·· ·
·
·• ·• ·· ·· ·· ··
•
•
·· ··• ··• •• ··• ·••
·· ·• ·· ·• ·• ••
· ·• · ·• · •
·· · ·· · ·• ··
·• ·• • •• ·• •
·· ·· ··· ·· ·· ··•
·· ·· ·· ·· •• ••
·• ·• ·• ·· ·· ·•
·· · ·· • • ••
··
• •
•
-@-
1
S
· ®. · • •
1
Condition Code Register Manipulation Instructions
fA-ddressingModes
Operations
4
• •
• •
None
BRA
3
5
H
Mnemonic
Condition Code Register
Boolean Operation
IMPLIED
OP
-
OC
2
1
#
Clear Carry
ClC
Clear Interrupt Mask
Cli
OE
2
1
0-1
Clear Overflow
ClV
OA
2
1
O-V
Set Carry
SEC
00
2
1
l-C
Set Interrupt Mask
SEI
OF
2
1
Set Overflow
SEV
OB
2
1
1- I
I-V
Accumulator A - CCR
TAP
06
2
1
A- eCR
CCR - Accumulator A
TPA
07
2
1
CCR- A
O-C
5
4
3
2
1
H
I
N
Z
V
0
C
·• · ·• ·• •
•
• · · •
• •
• ·
·
·• · ·· ·• • ·•
• · • • • ·
• •
R
R
R
S
S
S
---@)---
Condition Code Register Notes: (Bit set it test is true and cleared otherwise)
CD
(Bit V)
@ (Bit C)
@ (Bit C)
@ (Bit V)
@ (Bit V)
@ (Bit V)
(J) (Bit N)
@ (All)
® (Bit I)
@) (All)
® (Bit C)
Test: Result = 10000000?
Test: Result" OOOOOOOO?
Test: Decimal value of most significant BCD Character greater than nine? (Not cleared if previously set)
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to.execution?
Test: Set equal to result of NE!:)C after shift has occurred.
Test: Result less than zero? (Bit 15 = 1)
load Condition Code Register from Stack. (See Special Operations)
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the wait state.
Set according to the contents of Accumulator A.
Set equal to result of Bit 7 (ACCB)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
67
H06801 SO,H06801 55
Table 11
ACCX
Immediate
Direct
Extended
Instruction Execution Times in Machine Cycles
Indexed
Implied
Aelative
ACCX
ABA
2
INX
ABX
3
JMP
ADC
ADD
2
Immediate
Direct
4
JSA
6
4
LOA
4
4
5
6
6
LDD
4
2
3
4
4
LOS
4
6
6
LOX
4
LSA
ASLD
ASR
6
2
Implied
MUL
BCS
NEG
5
5
5
6
6
6
6
10
NOP
~
BGE
ORA
BGT
PSH
4
4
PSHX
BHI
4
BIT
PUL
4
4
BlE
PULX
BlS
ROL
6
BlT
AOR
6
BMI
ATI
10
BNE
RTS
5
BPL
SBA
3
BAA
3
SEC
BSA
6
SEI
BVC
3
SEV
BVS
3
STA
2
2
4
CBA
STD
4
ClC
STS
4
STX
4
SUB
3
CLI
6
ClR
6
SUBD
elV
6
4
SBe
BAN
5
4
4
6
12
CMP
4
4
SWI
COM
6
6
TAB
2
6
6
TAP
2
6
6
TPA
4
CPX
5
TBA
DAA
DEC
Aelative
LSAD
6
BCC
BEQ
6
4
AND
2
Indexed
4
ADDD
ASL
Extended
2
DES
TST
DEX
TSX
6
EOR
4
4
TXS
3
INC
6
6
WAI
9
INS
68
~HITACHI
\ Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------HD6801S0,HD6801S5
•
Summary of Cycle by Cycle Operation
Table 12 provides a detailed description of the information
present on the Address Bus, Data Bus, and the Read/Write line
(R/W) during each cycle for each instruction.
This information is useful in comparing actual with expected
results during debug of both software and hardware as the
control program is executed. The information is categorized in
groups according to addressing mode and number of cycles per
instruction. (In general, instructions with the same addressing
mode and number of cycles execute in the same manner; exceptions are indicated in the table).
Table 12 Cycle by Cycle Operation
Address Mode &
Instructions
Address Bus
Data Bus
IMMEDIATE
2
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Operand Data
LDS
LDX
LDD
3
1
2
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
CPX
SUBD
ADDD
4
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus F F F F
1
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address of Operand
1
1
1
Op Code
Address of Operand
Operand Data
Op Code Address
Op Code Address + 1
Destination Address
1
1
0
Op Code
Destination Address
Data from Accumulator
Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand + 1
1
1
0
0
Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus F F F F
1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1
1
1
1
0
0
Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
3
1
2
3
4
DIRECT
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
3
1
2
3
STA
3
LOS
LOX
LDD
4
1
2
3
1
2
3
4
STS
STX
STD
4
1
2
3
4
CPX
SUBD
ADDD
5
1
2
3
4
5
JSR
5
1
2
3
4
5
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
69
HD6801S0,HD6801S5----------------------------------------------------Table 12 Cycle by Cycle Operation (Continued}
Address Mode &
Instructions
Data Bus
Address Bus
INDEXED
JMP
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
3
1
2
3
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Offset
Low Byte of Restart Vector
4
1
2
3
4
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
1
1
1
1
Op Code
Offset
Low Byte of Restart
Operand Data
1
2
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Regis,er Plus Offset
1
1
1
0
Op Code
Offset
Low Byte of Restart Vector
Operand Data
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
0
0
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus F F F F
Index Register Plus Offset
1
1
1
1
1
0
Op Code
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Add ress
Op Code Add ress + 1
Address Bus F F F F
Index Register + Offset
Index Register + Offset + 1
Address Bus F F F F
1
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Stack Pointer
Stack Pointer - 1
1
1
1
1
0
0
Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
4
STA
3
4
LDS
LDX
LDD
5
STS
STX
STD
5
ASL
ASR
CLR
COM
DEC
INC
1
2
3
4
5
1
2
3
4
5
LSR
NEG
ROL
ROR
TST*
6
1
2
3
4
5
6
CPX
SUBD
ADDD
6
JSR
6
1
2
3
4
5
6
1
2
3
4
5
6
*In the TST instruction, R/iii line of the sixth cycle is "1" level, and AB
70
= FFFF, DB = Low Byte of Reset Vector.
Vec~or
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------HD6801S0,HD6801S5
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
EXTENDED
3
JMP
1
2
3
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
STA
4
1
2
3
4
4
1
2
3
4
LDS
LDX
LDD
5
STS
STX
STD
5
ASL
ASR
CLR
COM
DEC
INC
1
2
3
4
5
1
2
3
4
5
LSR
NEG
ROL
ROR
TST*
6
1
2
3
4
5
6
CPX
SUBD
ADDD
6
JSR
6
1
2
3
4
5
6
1
2
3
4
5
6
I
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
1
1
1
1
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data
Op Code
Op Code
Op Code
Operand
1
1
1
Address
Address + 1
Address + 2
Destination Address
Op Code
I Destination
0
Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)
0
0
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address Bus F F F F
Address of Operand
1
0
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF
1
1
1
1
1
1
Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
1
1
1
1"
0
0
-I n the TST instruction, R/W line of the sixth cycle is "'" level, and AB=FF FF • DB=Low Byte of Reset Vector.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
(Continued)
71
HD6801S0,HD6801S5------------------------------------------------------Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Data Bus
Address Bus
IMPLIED
2
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Op Code of Next Instruction
ABX
3
1
2
3
Op Code Address
Op Code Address + 1
Address Bus F F F F
1
1
1
Op Code
Irrelevant Data
Low Byte of Restart Vector
ASLD
LSRD
3
1
2
Op Code Address
Op Code A.ddress + 1
Address Bus FFFF
1
1
1
Op Code
Irrelevant Data
Low Byte of Restart Vector
DES
INS
3
Op Code Address
Op Code Address + 1
Previous Register Contents
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
INX
DEX
3
OP Code Address
Op Code Address + 1
Address Bus F F F F
1
1
1
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
PSHA
PSHB
3
OP Code Address
Op Code Address + 1
Stack Pointer
1
1
0
Op Code
Op Code of Next Instruction
Accumulator Data
TSX
3
Op Code Address
Op Code Address + 1
Stack Pointer
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
TXS
3
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
PULA
PULB
4
Op Code Address
OP Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Operand Data from Stack
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
0
0
Op Code
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte)
3
4
5
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer.,. 1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
1
1
1
1
1
5
Stack Pointer + 2
1
Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
Op Code
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(High Order Byte)
Address of Next Instruction
(Low Order Byte)
1
2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
0
0
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA
SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
4
PSHX
4
1
2
3
4
PULX
RTS
WAI**
5
5
9
1
2
3
4
Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (H igh Order Byte)
(Continued)
72
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------HD6801S0,HD6801S5
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Cycles.
Cycle
#
5
6
7
WAI**
10
SWI
10
12
Pointer
Pointer
Pointer
Pointer
Pointer
-
2
3
4
5
6
Data Bus
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
10
Op Code Address
Op Code Address + 1
Address Bus FFFF
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
Address Bus F F F F
Address Bus F F F F
Address Bus FFFF
Address Bus F F F F
1
1
1
1
1
1
1
1
1
1
Op Code
Irrelevant
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
5
Stack Pointer + 2
1
6
Stack Pointer + 3
1
7
Stack Pointer + 4
1
8
Stack Pointer + 5
1
9
Stack Pointer + 6
1
10
Stack Pointer + 7
1
Op Code
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instruction Address from
Stack (Low Order Byte)
10
11
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Stack Pointer - 7
Vector Address FFFA (Hex)
1
1
0
0
0
0
0
0
0
1
1
12
Vector Address FFFB (Hex)
1
1
2
3
4
5
6
7
8
9
RTI
Stack
Stack
Stack
S!ack
Stack
R/W
Line
0
0
0
0
0
8
9
MUL
Address Bus
1
2
3
4
5
6
7
8
9
Data
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Op Code
Irrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index· Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
I rrelevant Data
Address of Subroutine
(High Order Byte)
Address of Su broutine
(Low Order Byte)
**While the MCU is in the "Wait" state, its bus state will appear as a series of MCU reads of an address which is seven locations less than the
original contents of the Stack Pointer. Contrary to the HD6800, none of the ports are driven to the high impedance state by a WAI instruction.
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
73
HD6801S0,HD6801S5----------------------------------------------------Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Data Bus
Address Bus
RELATIVE
BCC
BCS
BEQ
BGE
BGT
BRN
BHT
BLE
BLS
BLT
BMT
3
BNE
BPL
BRA
BVC
BVS
1
2
I
3
1
1
1
Op Code
Branch Offset
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
Op Code
Branch Offset
Low Byte of Restart Vector
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
-----
6
BSR
1
2
3
4
5
6
•
Op Code Address
Op Code Address + 1
Address Bus FFFF
0
0
When the op codes (4E, SE) are used to execute, the MCU
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the
LSI.
Summary of Undefined Instruction Operations
The HD680lS has 36 undefmed instructions. When these are
carried out, the contents of Register and Memory in MCU
change at random.
Table 13 Op codes Map
HD6801S
MICROCOMPUTER INSTRUCTIONS
OP
CODE
ACC
A
~
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0000
0001
----------- ----0
1
2
3
BRA
TSX
CBA
BRN
INS
~
BHI
PULA (+1)
BLS
PULB (+1)
BCC
DES
LSRD (+1) ~
ASLD (+1) ~
TAP
TAB
TBA
7
TPA
1000
S
INX (+1)
1001
9
DEX (+1)
1010
A
CLV
1011
B
1100
0011
SBA
NOP
0111
0010
BCS
TXS
BNE
PSHA
ACC IND
B
0100 0101 0110 0111
-----
4
5
6
RTS (+2)
BPL
ABX
SEV
ABA
BMI
RTI (+7)
C
CLC
~
BGE
PSHX (+1)
1101
0
SEC
BLT
MUl (+7)
1110
E
F
CLI
BGT
WAI (+6)
[NOTES]
2/3
1/3
I
I
0
E
I
0
.
SBC
1
SUBD (+2)
.:
2
ADDD (+2)
~
~
STA
STA
EOR
7
ROL
ADC
DEC
ORA
A
.
.
JMP (-3)
CLR
1/2
2/6
CPX (+2)
BSRJ
J+41
TST
** ---
ADD
JSR (+2)
LOS (+1)
:- (+111
3/6
2/2
STS (+1)
I 2/3 I 2/4 I 3/4
*
.
B
LDD (+1)
(+1~
*
* (+111
2/2
STD (+1)
LOX (+1)
STX(+1)
I 2/3 I 2/4 I 3/4
) indicate that the number in parenthesis must be added to the cycle count for that instruction.
3) The instructions shown below are all 3 bytes and are marked with ......
Immediate addressing mode of SUBD, CPX, lOS, ADDD, LDD and LOX instructions, and undefined op codes
(SF, CD, CF).
4) The Op codes (4E, 5E) are 1 byte/ oo cycles instructions, and are marked with ......
74
3
4
S
9
1) Undefined Op codes are marked with ~ .
2) (
F
CMP
----1/2
C
SUB
INC
-
B
5
BVS
1/2
I
6
DAA
1/2
A
BIT
-----
BYTE/CYCLE
I
I EXT
LOA
~
SWI (+9)
9
liND
ROR
ASL
BlE
I
------==-:
ASR
~
S
1DIR
1100111011111011111
AND
PSHB
/
7
IMM
LSR
PULX (+2)
SEI
AceB or X
1 DIR liND 1 EXT
1000110011101011011
COM
BEQ
1111
IMM
NEG
BVC
V
ACCA orSP
EXT
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
C
0
E
F
I
s=
o
2:
»
3
~
o·
S»
~
•
I\)
~
o
o
c}
°A
rov
~l:
.CD
-~
• :J>
(1)(')
~
J:
~
oen
CD
()
»
co
01
~
*SCI = TIE-TORE + RIE-(RORF + ORFE)
•
Condition Code Register
ii'
~
,
,
i
i
Vector -> PC
o
$
e
NMI
FFFC FFFO
SWI
FFFA FFFB
FFF8 FFF9
FFF6 FFF7
FFF4 FFF5
FFF2 FFF3
FFFO FFFl
TRIT;
01
Co
(,)
ICF
OCF
TOF
SCI
o
o
Non-Maskahle Interrupt
Software Interrupt
Maskable Interrupt Request 1
Input Capture Interrupt
Output Compare Interrupt
Timer Overflow Interrupt
SCI Interrupt (TORE + RORF + ORFE)
:::r
o
0>
CO
o.....
en
p
:::r
o
0>
CO
o.....
""'-I
VI
Figure 24 Interrupt Flowchart
en
(11
HD6801S0,HD6801S5------------------------------------------------------Vee
Vee
Enable
Enable
NMI
Port 3
8 Transfer
Lines
Port 1
81/0
Lines
POrt 4
81/0 Line.
Port 1
81/0 LInes
,-...,ra----,.----"-""
Port 2
Port 2
51/0 L,nes
SCI
51/0 L,nes '-~"L
SCI
Port 4
81/0 Lines
__,........_...J
16 Bit T,mer
Vss
Figure 25
Vss
HD6801 S MCU Single-Chip Dual Processor Configuration
HD6801S
MCU
Address
Bus
Data
Bus
Figure 26 HD6801 S MCU Expanded Non-Multiplexed Mode
Address Bus
Data Bus
Figure 27 HD6801 S MCU Expanded Multiplexed Mode
•
Caution for the HD6801 Family SCI, TIMER Status Flag
The flags shown in Table 14 are cleared by reading/writing
(flag reset condition 2) the data register corresponding to each
flag after reading the status register (flag reset condition 1).
To clear the flag correctly, take the following procedure:
1. Read the status register
2. Test the flag
3. Read the data register
Table 14 Status Flag Reset Conditions
ICF
Flag Reset
Condition 1
(Status Register)
When each flag is
OCF
"1",
TOF
TRCSR/Read
RDRF
When each flag is
"1",
Status
Flag
f----
TIMER
SCI
f-----
~
Flag Reset Condition 2
(Data Register)
ICR/Read
OCRIWrite
TC/Read
RD~
Read
~
TDRE
76
TRCSR/Read
TDR/Write
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6801VO,HD6801V5
MCU (Microcomputer Unit)
The HD6801 V MCV is an 8·bit microcomputer unit which
is compatible with the HD680lS except the ROM size. The
HD6801V MCV is object code compatible with the HD6800
with improved execution times of key instructions plus several
new 16·bit and 8·bit instructions including an 8x8 unsigned
multiply with l6·bit result. The HD680lV MCV can operate as
a single chip microcomputer or be expanded to 65k bytes. The
HD6801V MCV is TTL compatible and requires one +5.0 volt
power supply. The HD680 I V MCV has 4k bytes of ROM and
128 bytes of RAM on chip. Serial Communications Interface
(SCI), and parallel I/O as well as a three function l6·bit timer.
Features and Block diagram of the HD6801 V include the
following:
HD6801VOP
HD6801V5P
(DP·40)
•
•
FEATURES
Expanded HMCS6800 Instruction Set
•
•
8 x 8 Multiply
On·Chip Serial Communication Interface (SCI)
•
Object Code Compatible With The HD6800 MPU
•
•
16·Bit Timer
Single Chip Or Expandable To 65k Bytes
•
•
4k Bytes Of ROM
128 Bytes Of RAM (64 Bytes Retainable On Power
Down)
•
•
29 Parallel I/O Lines And 2 Handshake Control Lines
Internal Clock/Divided·By·Four Circuitry
•
TIL Compatible Inputs And Outputs
P"
•
Interrupt Capability
P"
•
Compatible with MC6801 (except ROM size)
P"
P Il
P"
•
BLOCK DIAGRAM
P"
p ..
•
PIN ARRANGEMENT
o
sc,
sc,
P"
P"
P"
P"
HD6801V
P"
P"
P"
p ..
P.,
(Top View)
•
TYPE OF PRODUCTS
MCU
Bus Timing
HD6801VO
1 MHz
HD6801V5
1.25 MHz
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
n
HD6801VO,HD6801V5------------------------------------------------------• ABSOLUTE MAXIMUM RATINGS
Item
Vee
V in
Input Voltage
Operating Temperature
Value
Unit
-0.3 - +7.0
V
-0.3 - +7.0
V
0
Topr
Tstg
Storage Temperature
*
..
Symbol
Supply Voltage
°c
-+70
°c
- 55 --+150
With respect to VSS (SYSTEM GND)
[NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliabilitv of LSI.
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee =5.0V±5%, Vss
Item
Input "High" Voltage
Input "Low" Voltage
=OV, Ta =0- +70°C. unless otherwise noted.)
Symbol
RES
Other Inputs·
V IL
Other Inputs*
Ilinl
Input Leakage Current
NMI. IRQI. RES
Ilinl
Three State (Offset)
Leakage Current
PIO - P17 • P30 - P37
P20 - P24
PJO - P37
P40 - P47 • E, SCI. SC 2
Other Outputs
Output "High" Voltage
Output "Low" Voltage
Input Capacitance
Vee Standby
Standby Current
-
max
Vee
-0.3
0.6
-0.3
-
0.8
-
-
0.5
0.8
1.2
mA
-
2.5
10
J.LA
Vin = 0- 2.4V
-
II TS "
V in = 0.5 - 2.4V
-
V OH
I LOAD = -205 J.LA
ILOAD = -145 J.LA
2.4
2.4
I LOAD = -100 J.LA
2.4
' LOAD = 1.6 mA
V out = 1.5V
-
VOL
PI7
PJO - P37 • P40
Other Inputs
typ
-
V in = 0- Vee
All Outputs
Darlington Drive Current PIO
Power Dissipation
min
4.0
2.0
EXTAL
P40 - P47
SCI
EXTAL
Input Load Current
Test Condition
V1H
-IOH
V in = 0 - 5.25V
Po
-
P47 • SCI
Cin
V in = OV, Ta = 25°C,
f = 1.0 MHz
1.0
-
Powerdown
V SBB
4.0
Operating
V SB
4.75
Powerdown
ISBB
V SBB = 4.0 V
-
Unit
V
Vee
V
-
100
-
-
-
-
-
0.5
V
10.0
mA
-
1200
mW
-
12.5
-
10.0
-
J.LA
V
-
5.25
5.25
8.0
pF
V
mA
-Except Mode Programming Levels.
78
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
--------~---------------------------------------------HD6801VO,HD6801V5
• AC CHARACTERISTICS
BUS TIMING (Vee = 5.0V±5%, Vss -= OV, Ta - 0 - +70°C, unless otherwise noted.)
Symbol
Item
Cycle Time
Address Strobe Pulse Width "High"
Test Condition
tCYC
PW ASH
*
min
HD6801VO
typ
max
min
HD6801V5
typ
max
Unit
1
-
10
0.8
-
10
ps
200
-
-
150
-
-
ns
Address Strobe Rise Time
tASr
5
-
50
5
-
50
ns
Address Strobe Fall Time
tASf
tAso
5
60
-
50
-
50
-
-
5
30
-
-
ns
ns
tEr
tEf
PW EH
PW EL
5
5
-
5
5
-
-
50
50
-
50
50
-
Address Strobe Delay Time
*
Enable Rise Time
Enable Fall Time
Enable Pulse Width "High" Time
*
Enable Pulse Width "Low" Time *
Address Strobe to Enable Delay Time
Address Delay Time
Address Delay Time for Latch
Data Set-up Write Time
*
tASEO
tAD
*
tAOL
ns
ns
ns
450
450
-
-
340
350
-
-
-
-
60
-
-
30
-
-
260
270
-
-
-
-
260
260
ns
ns
ns
ns
Fig. 1
Fig. 2
-
-
-
-
tosw
225
-
-
115
-
-
ns
Data Set-up Read Time
Read
Data Hold Time
Write
tOSR
tHR
-
-
BO
-
-
ns
-
-
-
-
-
-
10
20
-
-
Address Set-up Time for Latch *
Address Hold Time for Latch
tASL
tAHL
80
10
20
60
Address Hold Time
tAH
I
I
Peripheral Read
Access Time
I
I
tHW
Non-Multiplexed Bus*
(tACCN)
Multiplexed Bus*
(tACCM)
Oscillator stabilization Time
Fig. 10
tRC
tpcs,
Processor Control Set-up Time
Fig. 11
ns
-
-
50
-
-
ns
20
-
-
20
-
-
ns
20
-
-
20
-
-
-
-
-
-
(410)
-
-
(610)
(600)
-
-
(410)
100
200
-
-
100
-
-
ms
-
200
-
-
ns
ns
ns
*These timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc is
minimum (=in the highest speed operation).
PERIPHERAL PORT TIMING (Vee = 5.0V ±5%, Vss
=OV, Ta = 0 -
+70~C, unless o.therwise noted.)
Symbol
Test Condition
min
typ
max
Peripheral Data Setup Time
Port 1, 2, 3,4
t posu
Fig.3
200
-
-
ns
Peripheral Data Hold Time
Port 1,2,3,4
tpOH
Fig.3
200
-
-
ns
Delay Time, Enable Positive Transition
to 0S3 Negative Transition
tOS01
Fig. 5
-
-
350
ns
Delay Time, Enable Positive Transition
to 0S3 Positive Transition
tOS02
Fig. 5
-
-
350
ns
Delay Time, Enable Negative
Transition to Peripheral Data
Valid
Port 1, 2*,3,4
tpwo
Fig.4
-
-
400
ns
Delay Time, Enable Negative
Transition to Peripheral
CMOS Data Valid
*
Port 2**, 4
tCMOS
Fig.4
-
-
2.0
J.!s
-
ns
Item
tPWIS
Fig. 6
200
-
Input Data Hold Time
port 3
tlH
Fig. 6
50
Input Data Set-up Time
Port 3
tiS
Fig. 6
20
-
Input Strobe Pulse Width
*Except Pl.
Unit
ns
ns
.... 10kn. pull up register required for Port 2
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
79
HD6801VO,HD6801V5 - - - - - - - - - - - - - - - - - - - - - - - - - - TIMER, SCI TIMING (Vee = 5.0V ±5%, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)
Item
Symbol
Timer Input Pulse Width
tpWT
Delay Time, Enable Positive Transition to
Timer Out
tTOD
SCI Input Clock Cycle
tSCYC
SCI Input Clock Pulse Width
tpWSCK
Test Condition
typ
max
-
-
ns
-
-
600
ns
1
-
-
tCYC
0.4
-
0.6
tScyc
Unit
min
2t cyc +200
Fig.7
Unit
MODE PROGRAMMING (Vee = 5.0V ±5%, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)
min
typ
max
Mode Programming Input "Low" Voltage
V MPL
-
-
1.7
V
Mode Programming Input "High" Voltage
V MPH
4.0
-
-
V
3.0
-
-
tcyc
-
-
Symbol
Item
PW RSTL
RES "Low" Pulse Width
Mode Programming Set-up Time
Mode Programming
Hold Time
I RES
Rise Time
2
1J.Ls
I RES Rise Time < 1J.Ls
Test Condition
Fig.8
t MPS
2.0
tMPH
0
100
-
tcyc
ns
~--------------------t~----------------------~
Address Strobe
(AS)
2.2V
PWASH
Enable
(E)
R/W, Ar-A'6
(Sell (Port4)
MCU Write
Do-D,.Ao-A,
(Port 3)
MCU Read
0.-0,. A.-A,
(Port 3)
Figure 1 Expanded Multiplexed Bus Timing
80
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------HD6801VQ,HD6801V5
I
teye
PWEL
O.SV
1\
i---
Rfiii
ISC,)
(SC,)
PWEH
I
~
'AD
1\
-
I.-tE,
---00
2.2V
Ao-A~Port4 )
iOS
-..-
f-
2.4V
Enable
IE)
J
1-00
1\
f-
-.
"'-'HW
2.2V
MCUWri te
~
Oa,a Valid
°0- 0 ,
~
D.6:}
(Port3)
-t05RItACCN)
2.0V
MCU R\!ad
0.-0,
I+-'AH
Address Valid
D.6~
-'05\1\1-
(Port 3)
kI-tEf
------------------------------------~
O.BV
-
+- tHR
oa,a Vahd
,'-------..11
Figure 2 Expanded Non-Multiplexed Bus Timing
r-MCU Write
r-MCURead
Enable(E)~
O.SV
Enable(E)
'CMOSi}
'pwo
P,. - P 17
p •• - p,.
"
P40 - P47
All oa,a
Port Outputs _ _ _ _ _ _ _...J
Inputs
p)O -
P)'7
- - - - 0.7 VCC
~.~~
oa,a Valid
2.0V
Inputs-
D.SV
(Note)
1. 10
'Port 3 Non-Latched Operation (LATCH ENABLE = 0)
Figure 3
r
kn Pullup resistor required for Port 2 to reach 0.7 Vee
2. Not applicable to P 21
3. Port 4 cannot be pulled above Vee
Data Set-up and Hold Times;
(MCU Read)
Figure 4
Port Data Delay Timing
(MCU Write)
MCU access of Port 3 *
Enable(E)
Add,",
Bu,
053------
P,. - PI'
Inputs
~~~--------~~~-----
• Access matches Output Strobe Select (OSS = 0 a read'
OSS = 1, a wrtte)
,
,
Figure 5
Port 3 Output Strobe Timing
(Single Chip Mode)
Figure 6
Port 3 Latch Timing
(Single Chip Mode)
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
81
HD6801VO,HD6801V5------------------------------------------------------
Enable
(E)
Timer
Counter ----.J'---t=~-:-J
v-------s..
'-____
VMPH
tTOO~ 2.2V
P"
,...::O,;.:.6;.,;V_ _ __
Output
Figure 8
Figure 7
Mode Programming Timing
Timer Output Timing
Vee
Test Point
0..-----.1 _,
m
AL.2.2k(}
Test Point
152074
®
Or EQuiv
C
(a) CMOS Load
A
(b) TTL Load
Figure 9 Bus Timing Test Loads
NMi Of
IROz
xs- X 15
\~
InlPtnalR/W
.. IRQ 2
--
ACea
ACCA
eeA
Irr~ll!Vanl
Vector
Vector
Data
MSB
LS8
____________________________-JI
First Inst. at
Interrupt Routme
Internal Interrupt
Figure 10 Interrupt Sequence
'nlo,"al
Address Bus
'nto,nol
\\\\\\\\\\\\\\\\\\\\\~ ~\\\\\\\\\\S\\\\\\\\\\\\\\\y---V~
~
~
FFFE FfFE
RIW \\\\\\\\\\\\\\\\\'{
/\\\\\\\\\\\\\\\\\\\\\\\\\\\1
~;,':';~: ~\\\\\\\\\\\\\\\\\\\\1,tz\\\\\\\\\\\\\\\\\\\\\S\\\\\\SX:::
=
pes-pelS PCO-PC7
First
'< ~
pc:::x:::x::
Instruction
Figure 11 Reset Timing
82
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------HD6801VO,HD6801V5
•
• SIGNAL DESCRIPTIONS
Vee and Vss
These two pins are used to supply power and ground to the
chip. The voltage supplied will be +5 volts ±5%.
• XT AL and EXT AL
These connections are for a parallel resonant fundamental
crystal, AT cut. Divide-by-4 circuitry is included with the
internal clock, so a 4 MHz crystal may be used to run the
syltem at 1 MHz. The divide·by·4 circuitry allows for use of the
lIlexpensive 3.58 MHz Color TV crystal for non-time critical
applications. Two 22pF capacitors are needed from the two
crystal pins to ground to insure reliable operation. An example
of the crystal interface is shown in Fig. 12. EXT AL may be
driven by an external TTL compatible clock source with a 45%
to 55% duty cycle. It will divide by 4 any frequency less than or
equal to 5 MHz. XT AL must be grounded if an external clock is
used.
Nominal Crystal Parameter
•
~
4 MHz
5 MHz
Co
7 pF max.
4.7 pF max.
Rs
60n max.
30n typo
Item
XTAL~--
__------~
CJ
EXT A L
~--
__--,
CL1
= C L2 = 22pF
± 20%
(3.2 - 5 MHz)
[Note] These are representative
AT cut parallel resonance
crystal perameters.
Figure 12 Crystal Interface
• Vee Standby
This pin will supply +5 volts ±5% to the standby RAM on the
chip. The first 64 bytes of RAM will be maintained in th~ power
down mode with 8 rnA current max. The circuit of figure 13
can be utilized to assure that Vee Standby does not go below
V SBB during power down.
To retain information in the RAM during power down the
following procedure is necessary:
1) Write "0" into the RAM enable bit, RAME. RAME is bit
6 of the RAM Control Register at location $0014. This
disables the standby RAM, thereby protecting it at power
down.
2) Keep Vee Standby greater than VSBB.
VCCS'".b,
T
P"""LI~
Figure 13 Battery Backup for Vee Standby
Reset (RES)
This input is used to reset and start the CPU from a power
down condition, resulting from a power failure or an initial
startuo of the processor. On power up, the reset must be held
"Low" for at least 100 ms. When reset during operation, RES
must be held "Low" at least 3 clock cycles.
When a "High" level is detected, the MCU does the follow·
ing:
1) All the higher order address lines will be forced "High".
2) I/O Port 2 bits 2, 1, and 0 are latched into programmed
control bitsPC2, PCI and PCD.
3) The last two ($FFFE, $FFFF) locations in memory will
be used to load the program addressed by the program
counter.
4) The interrupt mask bit is set. Clear before the CPU can
recognize maskable interrupts.
• Enable (E)
This supplies the external clock for the rest of the system
when the internal oscillator is used. It is a single phase, TTL
compatible clock, and will be the divide·by-4 result of the crystal
oscillator frequency. It will drive one TTL load and 90 pF
capacitance.
•
Non-Maskable Interrupt (NMI)
A low-going edge on this input requests that a non-maskableinterrupt sequence be generated within the processor. As with
interrupt Request signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
has no effect on NMI.
In response to an NMI interrupt, the Index Register, Program
Counter, Accumulators, and Condition Code Register are stored
on the stack. At the end of the sequence, a 16-bit address will
be loaded that points to a vectoring address located in memory
locations $FFFC and $FFFD. An address loaded at these locations causes the CPU to branch to a non-maskable interrupt
service routine in memory.
A 3.3 kn external resistor to Vee should be used for
wire-OR and optimum control of interrupts.
Inputs IRQl and NMI are hardware interrupt lines that are
sampled during E and will start the interrupt routine on the
E following the completion of an instruction .
•
Interrupt Request (I RO l )
This level sensitiv~ input requests that an interrupt sequence
be generated within the machine. The processor will complete
the current instruction before it recognizes the request. At that
time, if the interrupt mask bit in the Condition Code Register
is not set, the machine will begin an interrupt sequence. The
Index Register, Program Counter, Accumulators, and Condition
Code Register are stored on the stack. Next the CPU will respond to the interrupt request by setting the interrupt mask bit
"High" so that no further maskable interrupts may occur. At
the end of the cycle, a 16-bit address will be loaded that points
to a vectoring address which is located in memory locations
$FFF8 and $FFF9. An address loaded at these locations causes
the CPU to branch to an interrupt routine in memory.
The IRQ\ requires a 3.3 kn external resistor to Vee which
should be used for wire-OR and optimum control of interrupts.
Internal Interrupts will use an internal interrupt line (IRQ2).
This interrupt will operate the same as IRQ 1 except that it will
use the vector address of $FFFO through $FFF7. IRQl will
have priority over IRQ2 if both occur at the same time. The
Interrupt Mask Bit in the condition code register masks both
interrupts (See Table I).
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
83
HD6801VQ,HD6801V5----------------------------------------------------Table 1 Interrupt Vector Location
Vector
Highest
Priority
Lowest
Priority
• PORTS
There are four I/O ports on the HD6801V MCU; three 8-bit
ports and one 5-bit port. There are two control lines associated
with one of the 8-bit ports. Each port has an associated write
only Data Direction Register which allows each I/O line to be
programmed to act as an input or an output*. A "1" in the
corresponding Data Direction Register bit will cause that I/O
line to be an output. A "0" in the corresponding Data Direction
Register bit will cause that I/O line to be an input. There are
four ports: Port 1, Port 2, Port 3, and Port 4. Their addresses
and the addresses of their Data Direction registers are given in
Table 2.
Interrupt
MSB
LSB
FFFE
FFFF
RES
FFFC
FFFD
NMI
FFFA
FFFB
FFF8
FFF9
IRQ, (or IS3)
FFF6
FFF7
ICF (Input Capture)
OCF (Output Compare)
Software Interrupt (SWI)
FFF4
FFF5
FFF2
FFF3
TOF (Timer Overflow)
FFFO
FFF1
SCI (RDRF + ORFE + TORE)
*
The only exception is bit I of Port 2, which ·can either be data
input or Timer output.
Table 2 Port and Data Direction Register Addresses
The following pins are available in the Single Chip Mode, and
are associated with Port 3 only.
• Input Strobe (lS3) (SCI)
The tunction of the IS3 signal depends on the I/O Port 3
Control/Status Register. If IS3 Enable bit is set, an interrupt
will occur by the fall of the IS3 signal. If the latch enable bit is
set, the data in the I/O Port 3 will be latched at the I/O Port 3
Data Register. The timing condition of the IS3 signal that is
necessary to be latched the input data normally is shown in
Figure 6.
• Output Strobe (OS3) (SC 2 )
This signal is used by the processor to strobe an external
device, indicating valid data is on the I/O pins. The timing for
the Output Strobe is shown in Figure 5. I/O Port 3 Control!
Status Register is discussed in the following section.
The following pins are available in the Expanded Modes.
•
ReadIWrite (R/W) (SC 2 )
This TTL compatible output signals the peripherals and
memory devices whether the CPU is in a Read ("High") or a
Write ("Low") state. The normal standby state of this signal is
Read ("High"). This output can drive one TTL load and 90 pF
capacitance.
•
I/O Strobe (lOS) (SCI)
In the expanded non-multiplexed mode of operation, lOS
internally decodes A9 through A 15 as zero's and As as a one.
This allows external access of the 256 locations from $0100 to
$01 FF. The timing diagrams are shown as figure 2.
• Address Strobe (AS) (SCI)
In the expanded multiplexed mode of operation, address
strobe is output on this pin. This signal is used to latch the 8
LSB's of address which are multiplexed with data on Port 3. An
8-bit l~tch is utilized in conjunction with Address Strobe, as
shown In figure 19. So I/O port 3 can become data bus during
the E pulse. The timing for this signal is shown in Figure 1 of
Bus Timing. This signal is also used to disable the address from
the multiplexed bus allowing a deselect time, tASD before the
data is enabled to the bus.
Data Direction
Register Address
Ports
Port Address
I/O Port 1
$0002
$0000
I/O Port 2
$0003
$0001
I/O Port 3
$0006
$0004
I/O Port 4
$0007
$0005
•
I/O Port 1
This is an 8-bit port whose individual bits may be defined as
inputs or outputs by the corresponding bit in its data direction
register. The 8 output buffers have three-state capability,
allowing them to enter a high impedance state when the
peripheral data lines are used as inputs. In order to be read
properly, the voltage on the input lines must be greater than 2.0
V for a logic "1" and less than 0.8 V for a logic "0". As outputs these lines are TTL compatible and may also be used as.
a source of up to 1 rnA at 1.5 V to directly drive a Darlington
base. After Reset, the I/O lines are configured as inputs. In all
three modes, Port I is always parallel I/O.
• I/O Port 2
This port has five lines that may be defined as inputs or
outputs by its data direction register. The 5 output buffers have
three-state capability, allowing them to enter a high impedance
state when used as an input. In order to be read properly, the
voltage on the input lines must be greater than 2.0 V for a
logic "1" and less than 0.8 V for a logic "0". As outputs, this
port has no internal pullup resistors but will drive TTL inputs
directly. For driving CMOS inputs, external pullup resistors are
required. After Reset, the I/O lines are configured as inputs.
Three pins on Port 2 (pins 10, 9, and 8 of the chip) are used
to program the mode of operation during reset. The values of
these pins at reset are latched into the three MSB's (bits 7 6
and 5) of Port 2 which are read only. This is explained in ~h~
Mode Selection Section.
In all three modes, Port 2 can be configured as I/O and
provides access to the Serial Communications Interface and the
Timer. Bit 1 is the only pin restricted to data input or Timer
output.
• I/O Port 3
This is an 8-bit port that can be configured as I/O, a data bus,
or an address bus multiplexed with the data bus - depending on
the mode of operation hardware programmed by the user at
reset. As a data bus, Port 3 is bi-directional. As an input for
peripherals, it must be supplied regular TTL levels, that is,
greater than 2.0 V for a logiC "1" and less than 0.8 V for a logic
"0"
84
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------HD6801VO,HD6801V5
Its TTL compatible three-state output buffers can drive
one TTL load and 90 pF capacitance. In the Expanded Modes,
after reset, the data direction register is inhibited and data flow
depends on the state of the R/W line. The input strobe (lS3)
and the output strobe (OS3) used for handshaking are explained
later.
In the three modes, Port 3 assumes the following characteristics:
Single Chip Mode: Parallel Inputs/Outputs as programmed by
its associated Data Direction Register. There are two control
lines associated with this port in this mode, an input strobe and
an output strobe, that can be used for handshaking. They are
controlled by the I/O Port 3 Control/Status Register explained
at the end of this section. Three options of Port 3 operations
are sumarized as follows: (I) Port 3 input data can be latched
using IS3 (SC 1) as a cOfltrol signal, (2) OS3 can be generated by
either an CPU read or write to Port 3's Data Register, and (3)
and IRQl interrupt can be enabled by an IS3 negative edge.
Port 3 latch and strobe timing is shown in Fig. 5 and Fig. 6.
Expanded Non-Multiplexed Mode: In this mode, Port 3
becomes the data bus (Do -D7)'
Expanded Multiplexed Mode: In this mode, Port 3 becomes
both the data bus (D o -D 7) and lower bits of the address bus
(Ao-A7)' An address strobe output is true when the address is
on the port.
As outputs, each line is TTL compatible and can drive I TTL
load and 90 pF capacitance. After reset, the lines are configured
as inputs. To use the pins as addresses, therefore, they should be
programmed as outputs. In the three modes, Port 4 assumes the
following characteristics:
Single Chip Mode: Parallel Inputs/Outputs as programmed by
its associated Data Direction Register.
Expanded Non-Multiplexed Mode: Port 4 is configured as
the lower order address lines (Ao - A7) by writing "I "s to the
data direction register. When all eight address lines are not needed, the remaining lines, starting with the most significant bit,
may be used as I/O (inputs only).
Expanded MUltiplexed Mode: Port 4 is configured as the
higher order address lines (As - Aid by writing "I"s to the
data direction register. When all eight address lines are not
needed, the remaining lines, starting with the most Significant
bit, may be used as I/O (inputs only).
•
OPERATION MODES
The operation modes that HD6801 V will operate after Reset
is determined by hardware that the user must wire on pins 10,
9, and 8 of the chip. These pins are the three LSB's (I/O 2, I/O
1, and I/O 0 respectively) of Port 2. They are latched into
programmed control bits PC2, PC 1, and PCO when reset goes
high. I/O Port 2 Register is shown below.
PORT 2 DATA REGISTER
I/O PORT 3 CONTROL/STATUS REGISTER
6
IS3
IS3
$OOOF
Bit 0;
Bit I;
Bit 2;
Bit 3;
Bit 4;
Bit 5;
Bit 6;
Bit 7;
•
FLAG
a
4
X
OSS
LATCH
X
X
2
4
6
o
$0003
PC2
X
PCl
I
pca
1
1/04
11/0311/0211/01 1110
a
IRQl
ENABLE
ENABLE
Not used.
Not used.
Not used.
LATCH ENABLE. This controls the input latch for I/O
Port 3. If this bit is set "High" the input data will be
latched with the falling edge of the Input Strobe, IS3.
This bit is cleared by reset, and the latch is "re-opened"
with CPU read Port 3.
OSS. (Output Strobe Select) This bit wJ!L.select if the
Output Strobe should be generated at OS3 (SC 2 ) by a
write to I/O Port 3 or a read of I/O Port 3. When this bit
is cleared the strobe is generated by a read Port 3. When
this bit is set the strobe is generated by a write to Port 3.
Not used.
IS3 IRQI ENABLE. When set, interrupt will be enabled
whenever IS3 FLAG is set; when clear, interrupt is
inhibited. This bit is cleared by reset.
IS3 FLAG. This is a read-only status bit that is set by
the falling edge of the input strobe, IS3 (SC 1)' It is
cleared by a read of the Control/Status Register followed by a read or write of I/O Port 3. Reset will clear
this bit.
I/O Port 4
This is an 8-bit port that can be configured as I/O or as
address output lines depending on the mode of operation. In
order to be read properly, the voltage on the input lines must
be greater than 2.0 V for a logic" I" and less than 0.8 V for a
logic "0".
An example of external hardware that could be used for
Mode Seiection is shown in Fig 14. The HDI4053B provides
the isolation between the peripheral device and MCU during
reset. which is necessary if data conflict can occur between
peripheral device and Mode generation circuit.
As bits 5, 6 and 7 of Port :2 are read-only, the mode cannot
be changed through software. The mode selections are shown in
Table 3.
The HD680 IV can operate three basic modes; (I) Single Chip
Mode, (2) Expanded Multiplexed Mode (compatible with
HMCS6800 peripheral family) (3) Expanded Non-Multiplexed
Mode.
•
Single Chip Mode
In the Single Chip Mode the Ports are configured as I/O.
This is shown in Figure 16 the single Chip Mode. In this
mode, Port 3 will have two associated, control lines, an input
strobe and an output strobe for handshaking data.
•
Expanded Non-Multiplexed Mode
In this mode the HD680lV will directly address HMCS6800
peripherals with no external logic. In this mode Port 3 becomes
the data bus. Port 4 becomes the Ao-A 7 address bus or partial
address and I/O (inputs only). Port 2 can be parallel I/O, serial
I/O, Timer, or any combination of them. Port I is parallel I/O
only. In this mode the HD6801V is expandable to 256 locations. The eight address lines associated with Port 4 may be
substituted for I/O (inputs only) if a fewer number of address
lines will satisfy the application (See Figure 17).
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
85
HD6801VO,HD6801V5----------------------------------------------------Vee
(
.>
R
RI RI RI
6
TT T
A
Xo
~
B C
RES
HD6801V
Yo
X
Zo
Y
XI
Z
8
9
10
Poo (PCO)
P2I (PC1)
Pl1 (PC2)
YI
ZI
C
6 0
I..
1
~,
???
~
Mode
Control
Switch
HD14053B
Inh
J;
1) Mode 7 as shown
2) RC"'Reset time constant
3) R I =10kn
[NOTES)
Figure 14 Recommended Circuit for Mode Selection
Truth Table
Control Input
On Switch
Inh
Binary to 1-of-2
Decoder with
Inhibit
A
B
C
Xo~----------------4C~+-~~--~
Xl~-------------------R~~4-+-~
yocr--------------------~~4-+-~
ylc.r----------------------~~~~
Zo~----------------------~~+-~
Zl~------------------------~C*~
Select
Inhibit
C B A
x
y
z
HD14053B
0
0
0
0
Zo Yo Xo
0
0
0
1
Zo Y. XI
0
0
1 0
Zo VI Xo
0
0
1
1
Zo VI XI
0
1 0
0
ZI Vo Xo
0
1
0
1
ZI Vo XI
0
1
1 0
ZI VI Xo
0
1
1
ZI VI XI
1
X X X
1
-
Figure 15 HD14053B Multiplexers/Demultiplexers
Vee
Vee
40
2
Port 1
8 I/O Lines
Port 3
8 I/O Lines
Port 4
8 I/O Lines
Port 2
5 I/O Lines
Vss
SCI
Timer
Figure 16 HD6801V MCU Single-Chip Mode
86
Enable
Enable
Port 1
8 Parallel I/O
Port 3
8 Data Lines
Port 2
5 Parallel I/O
SCI
Timer
Vss
Port 4
To 8 Address
Lines or To
8 I/O Lines
(Inputs Only)
Figure 17 HD6801V MCU Expanded Non-Multiplexed Mode
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------~'HD6801VO,HD6801V5
•
Expanded Multiplexed Mode
Vee
In this mode Port 4 becomes higher order address lines with
an alternative of substituting some of the address lines for I/O
(inputs only). Port 3 is the data bus multiplexed with the lower
order address lines differentiated by an output called Address
Strobe. Port 2 is 5 lines of Parallel I/O, SCI, Timer, or any
combination of them. Port 1 is 8 Parallel I/O lines. In this mode
it is expandable to 65k bytes. (See Figure 18).
•
Enable
Lower order Address Bus Latches
8 Lines
Multiplexed
Data/Address
Port 1
8 I/O Lines
Since the data bus is mUltiplexed with the lower order
address bus in Port 3, latches are required to latch those address
bits. The 74LS373 Transparent octal D·type latch can be used
with the HD6801V to latch the least significant address byte.
Figure 19 shows how to connect the latch to the HD680 1V.
The output control to the 74LS373 may be connected to
ground.
Port 2
5 I/O Lines
SCI
Timer
Port 4
To 8 Address
Lines or To
8 I/O Lines
(Inputs Only)
Vss
Figure 18 HD6801V MCU Expanded Multiplexed Mode
GND
AS
I
0
Port 3
Address/Data
[
1
G OC
01
1Add,~,
74LS373
D.
Function Table
A. -A,
a.
1
Output
Control
G
Enable
0
a
L
L
L
H
H
H
L
X
H
L
X
X
H
L
00
Output
Z
0", 0.-0,
Figure 19 Latch Can nection
•
Mode and Port Summary MCU Signal Description
This section gives a description of the MCU signals for the various modes. SCI and SC 2 are signals which vary with the mode
that the chip is in.
MODE
SINGLE CHIP
PORT3
Eight Lines
PORT4
Eight Lines
SCI
SC 2
I/O
I/O
I/O
IS3 (I)
OS3 (0)
ADDRESS BUS*
(A8~Als )
AS(O)
R/W(O)
ADDRESS BUS*
(Ao~A7 )
10S(0)
R!W(O)
PORT 1
Eight Lines
PORT 2
Five Lines
I/O
EXPANDED MUX
I/O
I/O
ADDRESS BUS
(Ao~A7 )
DATA BUS
(Do~D7 )
EXPANDED NON·MUX
I/O
I/O
DATA BUS
(Do~D7 )
·These lines can be substituted for I/O (Input Only) starting with the most significant address line.
I = Input
iS3 = Input Strobe
SC = Strobe Control
o = Output
OS3 = Output Strobe
AS = Address Strobe
R/W = Read/Write
lOS = I/O Select
$HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
87
HD6801VO,HD6801V5-----------------------------------------------------Table 3 Mode Selection Summary
PH
(PC2)
Pl1
(PC1)
PlO
(PCO)
ROM
RAM
7
H
H
H
I
I
6
H
H
L
I
I
I
I
MUX(6)
5
H
L
H
I
I
I
NMUX(6)
4
H
L
L
1(2)
1(1)
I
I
3
L
H
H
E
E
E
MUX
2
L
H
L
E
I
E
MUX
Multiplexed/RAM
1
L
L
H
I
I
E
MUX
Multiplexed/RAM & ROM
0
L
L
L
I
I
1(3)
MUX
Multiplexed Test
LEGEND:
I - Internal
E - External
MUX - Multiplexed
NMUX - Non-Multiplexed
L - Logic "0"
H - Logic "1"
•
Interrupt
Vectors
Operating
Mode
Mode
I
Single Chip
Multiplexed/Partial Decode
Non·Multiplexed/Partial Decode
Single Chip Test
Multiplexed/No RAM & ROM
[NOTES)
1)
2)
3)
4)
Internal RAM is addressed at $XX80
I nternal ROM is disabled
RES vector is external for 2 cycles after RES goes "High"
Addresses associated with Ports 3 and 4 are considered external in Modes 0,
1,2, and 3
5) Addresses associated with Port 3 are considered external in Modes 5 and 6
6) Port 4 default is user data input; address output is optional by writing to Port 4
Data Direction Register
MEMORY MAPS
•
The MeV can provide up to 65k bytes address space depending on the operating mode. A memory map for each operating
mode is shown in Figure 20. The ftrst 32 locations of each map
are reserved for the MeU's internal register area, as shown in
Table 4. With exceptions as indicated.
Table 4
Bus
Mode
INTERRUPT FLOWCHART
The Interrupt flowchart is depicted in Figure 24 and is common to every interrupt excluding reset.
Internal Register Area
Register
Address
Port
Port
Port
Port
1
2
1
2
Data
Data
Data
Data
Direction Register*'"
Direction Register***
Register
Register
00
01
02
03
Port
Port
Port
Port
3
4
3
4
Data
Data
Data
Data
Direction Register * * *
Direction Register***
Register
Register
04*
05*'
06*
07**
Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
Output Compare Register (High Byte)
08
Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Port 3 Control and Status Register
OC
00
OE
OF'
Rate and Mode Control Register
Transmit/Receive Control and Status Register
Receive Data Register
Transmit Data Register
10
11
12
13
RAM Control Register
Reserved
09
OA
OB
14
1S-1F
• External address in Mode~ 1, 2, 3, 5, 6; cannot be
accessed in Mode 5 (No. lOS)
** External addresses in Modes 0, 1,2,3
*** 1=Output, O=lnput'
88
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------HD6801VO,HD6801V5
HD6801V
Mode
o
1
Multiplexed/RAM & ROM
Multiplexed Test mode
$0000(1)
$0000(1 )
}
Internal Registers
Internal Registers
$001F
$001 F
}
External Memory Space
)
Internal RAM
External Memory Space
$0080
$0080
$OOFF
HD6801V
Mode
Internal RAM
$OOFF
External Memory Space
External Memory Space
$FOOO
$FOOO
Internal ROM
Internal ROM
$FFEF
$FFFO
$FFFF(2)
Internal Interrupt Vectors(2
[NOTES]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and $OF.
2) Addresses $FFFE and $FFFF are considered
external if accessed within 2 cycles alter a
positive edge of RES and internal at all other
times.
3) After 2 CPU cycles, there must be no over·
lapping of internal and external memory
spaces to avoid driving the data bus with more
than one device.
4) This mode is the only mode which may be used
to examine the interrupt vectors in internal
ROM using an external Reset vector.
External Interrupt Vectors
$FFFF '----.....I
[NOTES]
1) Excludes the following addresses which may
be used externally; $04, $05, $06, $07 and
$OF.
2) Internal ROM addresses $FFFO to $FFFF are
not usable.
Figure 20 HD6801V Memory Maps
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
89
HD6801VO HD6801V5-----------------------------------------------------
HD6801V
Mode
2
HD6801V3
Mode
Multiplexed/RAM
Multiplexed/No RAM or ROM
$0000(1)
$0000(1)
}
Internal Registers
Internal Registers
$001F
$001F
External Memory Space
$0080
Internal RAM
$OOFF
External Memory Space
External Memory Space
$FFFO ......- - - - t '}
$FFFF L-_ _ _....
External I nterrupt Vectors
$FFFO ......- - - - t
.
$FFFF L-_ _ _.... }
External Interrupt Vectors
[NOTE)
[NOTE)
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07, and
$OF.
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and
$OF.
Figure 20 HD6801V Memory Maps (Continued)
90
$HITACtt l
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------HD6801VO,HD6801V5
HD6801V
Mode
4
Single Chip Test
HD6801V
Mode
5
Non-Multiplexed/Partial Decode
$0000(1)
$0000
Internal Registers
} Internal Registers
$001 F
$OOlF
$0080
} Internal RAM
$OOFF
$0100
} External Memory Space
$01FF
U
1)(4)
$FOOO
Internal ROM
$XX80
$XXFF
Internal RAM
Internal Interrupt Vectors
[NOTES]
1) The internal ROM is disabled.
2) Mode 4 may be changed to Mode 5 without
having to assert RESET by writing a "1" into
the peo bit of Port 2 Data Register.
3) Addresses As to AI 5 are treated as "don't
cares" to decode internal RAM.
4) Internal RAM will appear at $XX80 to $XXFF.
$FFFF
Internal Interrupt Vectors
[NOTES]
1) Excludes the following addresses which may
not be used externally: $04, $06, and $OF.
(No lOS)
2) This mode may be entered without going
through RES by using Mode 4 and subsequently writing ,a "1" into the peo bit of
Port 2 Data Register.
3) Address lines Ao -A 7 will not contain addresses until the Data Direction Register for Port 4
has been written with "l's" in the appropriate
bits. These address lines will assert "l's" until
made outputs by writing the Data Direction
Register.
Figure 20 HD6801 V Memory Maps (Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
91
HD6801VO,HD6801V5-----------------------------------------------------
HD6801V7
Mode
HD6801V6
Mode
Single Chip
Multiplexed/Partial Decode
$0000(1)
$001F
Internal Registers
$0000
} Internal Registers
$001F
External Memory Space
$0080
$0080
Internal RAM
Internal RAM
$ooFF
$OOFF
External Memory Space
$FOOO
Internal ROM
Internal ROM
Internal Interrupt Vectors
Internal Interrupt Vectors
$FFFF
[NOTES)
1) Excludes the following address which may be
used externally: $04, $06, $OF.
2) Address lines A.-A .. will not contain
addresses until the Data Direction Register for
Port 4 has been written with "1's" in the
appropriate bits. These address lines will
assert "1's" until made outputs by writing the
Data Direction Register.
Figure 20 HD6801V Memory Maps (Continued)
92
~HITACHI
Hitachi America Ltd.- 2210 O'Toole Ave. - San Jose, CA 95131 - (408) 435-8300
------------------------------------------------------HD6801VO,HD6801V5
•
PROGRAMMABLE TIMER
The HD680 1V contains an on-chip 16-bit programmable
timer which may be used to perform measurements on 1ft input
waveform while independently generating an output waveform.
Pulse widths for both input and output signals may vary from a
few microseconds to many seconds. The timer hardware consists
of
• an 8-bit control and status register,
• a 16-bit free running counter,
• a 16-bit output compare register, and
• a 16-bit input capture register
A block diagram of the timer registers is shown in Figure 21.
•
Free Running Counter ($0009:$000A)
The key element in the programmable timer is a 16-bit free
running counter which is driven to increasing values by E (Enable). The counter value may be read by the CPU software at
any time. The counter is cleared to zero by reset and may be
considered a read-only register with one exception. Any CPU
write to the counter's address ($09) will always result in preset
value of $FFF8 being loaded into the counter regardless of the
value involved in the write. This preset figure is intended for
testing operation of the part, but may be of value in some
applications.
•
Output Compare Register ($OOOB:$OOOC)
The Output Compare Register is a 16-bit read/write register
which is used to control an output waveform. The contents of
this register are constantly compared with the current value of
the free running counter. When a match is found, a flag is set
(OCF) in the Timer Control an~ Status Register (TCSR) and the
current value of the Output Level bit (OLVL) in the TCSR is
clocked to the Output Level Register. Providing the Data
Direction Register for Port 2, Bit 1 contains a "1" (Output),
the output level register value will appear on the pin for Port 2
IRa,
Bit 1. The values in the Output Compare Register and Output
level bit may then be changed to control the output level on the
next compare value. The Output Compare Register is set to
$FFFF during reset. The Compare function is inhibited for
one cycle following a write to the high byte of the Output
Compare Register to insure a valid 16-bit value is in the register
before a compare is made.
•
Input Capture Register ($OOOD:$OOOE)
The Input Capture Register is a 16-bit read-only register used
to store the current value of the free running counter when the
proper transition of an external input signal occurs. The input
transition change required to trigger the counter transfer is
controlled by the input Edge bit (IEDG) in the TCSR. The Data
Direction Register bit for Port 2 Bit 0, should· be clear (zero)
in order to gate in the external input signal to the edge detect.
unit in the timer.
The input pulse width must be at least two E-cycles to ensure
an input capture under all conditions.
*
•
With Port 2 Bit 0 configured as an output and set to "1", the
external input will still be seen by the edge detect unit.
Timer Control and Status Register (TCSR) ($0008)
The Timer Control and Status Register consists of an 8-bit
register of which all 8 bits are readable but only the low order 5
bits may be written. The upper three bits contain read-only
timer status information and indicate the followings:
• a proper transition has taken place on the input pin with a
subsequent transfer of the current counter value to the
input capture register.
• a match has been found between the value in the free
running counter and the output compare register, and
• when $0000 is in the free running counter.
Each of the flags may be enabled onto the HD680 1V internal
bus (IRQ2) with an individual Enable bit in the TCSR. If the
HD6801V Internal Bus
Output Input
Figure 21
Level
Bit 1
Edge
Bit 0
Port 2
Port 2
Block Diagram of Programmable Timer
~HITACHI
\ Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
93
HD6801VO,HD6801V5-----------------------------------------------------Timer Control and Status Register
7
5
6
IICF I OCF
4
3
2
1
0
TOF I EICI I EOCI I ETOIIIEOG I OLVLI $0008
I-bit in the HD680 I V Condition Code Register has been cleared,
a priority vectored interrupt will occur corresponding to the flag
bites) set. A description for each bit follows:
Bit 0 OLVL Output Level - This value is clocked to the output
level register on a successful output compare. If
the DDR for Port 2 bit I is set, the value will
appear on the outpu't pin.
Bit 1 IEDG Input Edge - This bit controls which transition of
an input will trigger a transfer of the counter to
the input capture register. The DDR for Port 2 Bit
o must be clear for this function to operate. IEDG
= 0 Transfer takes place on a negative edge
("High" -to-"Low" transition).
IEDG = I Transfer takes place on a positive edge
("Low"-to-"High" transition).
Bit 2 ETOI Enable Timer Overflow Interrupt - When set, this
bit enables IR0 2 to occur on the internal bus for a
rOF interrupt; when clear the interrupt is inhibited.
Bit 3 EOCI Enable Output Compare Interrupt - When set,
this bit enables IR0 2 to appear on the internal bus
for an output compare interrupt; when clear the
interrupt is inhibited.
Bit 4 EICI Enable Input Capture Interrupt - When set, this
bit enables IR0 2 to occur on the internal bus for
an input capture interrupt; when clear the interrupt is inhibited.
Bit 5 TOF Timer Overflow Flag - This read-only bit is set
when the counter contains $FFFF.1t is cleared by
a read of the TCSR (with TOF set) followed by an
CPU read of the Counter ($09).
Bit 6 OCF Output Compare Flag - This read-only bit is set
when a match is found between the output
compare register and the free running counter. It is
cleared by a read of the TCSR (with OCF set)
followed by an CPU write to the output compare
register ($OB or $OC).
Bit 7 ICF
Input Capture Flag - This read-only status bit is
set by a proper transition on the input; it is cleared
by a read of the TCSR (with ICF set) followed by
an CPU read of the Input Capture Register ($OD).
CPU via the data bus and with the outside world via pins 2, 3,
and 4 of Port 2. The hardware, software, and registers are explained in the following paragraphs.
• Wake-Up Feature
In a typical multi-processor application, the software
protocol will usually contain a destination address in the initial
byte(s) of the message. In order to permit non-selected MCU's
to ignore the remainder of the message, a wake-up feature is
included whereby all further interrupt processing may be
optionally inhibited until the beginning of the next message.
When the next message appears, the hardware re-enables (or
''wakes-up'') for the next message. The "wake-up" is automatically triggered by a string of ten consecutive I's which
indicates an idle transmit line. The software protocol must
provide for the short idle period between any two consecutive
messages.
• Programmable Options
The follOwing features of the HD680 I V serial I/O section are
programmable:
· format - standard mark/space (NRZ)
• Clock - external or internal
• baud rate - one of 4 per given CPU CP2 clock frequency or
external clock x8 input
• wake-up feature - enabled or disabled
• Interrupt requests - enabled or masked individually for
transmitter and receiver data registers
• clock output - internal clock enabled or disabled to Port
2 (Bit 2)
• Port 2 (bits 3 and 4) - dedicated or not dedicated to serial
I/O individually for transmitter and receiver.
• Serial Communication Hardware
The serial communication hardware is controlled by 4 registers as shown in Figure 22. The registers include:
• an 8-bit control and status register
• a 4-bit rate and mode control register (write only)
• an 8-bit read only receive data register and
• an 8-bit write only transmit data register.
In addition to the four registers, the serial I/O section utilizes
bit 3 (serial input) and bit 4 (serial output) of Port 2. Bit 2 of
Port 2 is utilized if the internal-clock-out or external-clock-in
options are selected .
• SERIAL COMMUNICATION INTERFACE
The HD680 I V contains a full-duplex asynchronous serial
communication interface (SCI) on chip. The controller comprises a transmitter and a receiver which operate independently
or each other but in the same data format and at the same data
rate. Both transmitter and receiver communicate with the
Transmit/Receive Control and Status (TRCS) Register
The TRCS register consists of an 8-bit register of which all 8
bits may be read while only bits O~4 may be written. The
register is initialized to $20 by reset. The bits in the TRCS
register are defined as follows:
Transmit/Receive Control and Status Register
76543210
I ROREI ORFE I TORE I RIE I
94
RE
I TIE I
TE
I
wu
I
AODR : $0011
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------HD6801VO,HD6801V5
Bit 7
Rate and Mode Control Register
I
I I I I
CCl
CCO
SSl
Bit 0
SSO 1$10
Transmit/Receive Control and Status Register
$12
Port 2
Receive Shift Register
Clock
Bit
2
Tx
Bit
10
I+----E
~----'-.::.......-----~
12
4
Figure 22 Serial I/O Registers
Bit 0 WU
"Wake-up" on Next Message - set by HD6801V
software and cleared by hardware on receipt of
ten consecutive 1's or reset of RE flag. It should
be noted that RE flag should be set in advance of
CPU set of WU flag.
Bit 1 TE
Transmit Enable - set by HD6801V to produce
pre am ble of nine consecutive I's and to enable
gating of transmitter output to Port 2, bit 4
regardless of the DDR value corresponding to this
bit; when clear, serial I/O has no effect on Port 2
bit 4.
TE set should be after at least one bit time of data
transmit rate from the set·up of transmit data
rate and mode.
Transmit Interrupt Enable - when set, will permit
Bit 2 TIE
an IRQ2 interrupt to occur when bit 5 (TDRE) is
set; when clear, the TDRE value is masked from
the bus.
Bit 3 RE
Receiver Enable - when set, gates Port 2 bit 3 to
input of receiver regardless of DDR value for this
bit; when clear, serial I/O has no effect on Port 2
bit 3.
Bit 4 RIE
Receiver Interrupt Enable - when set, will permit
an IRQ2 interrupt to occur when bit 7 (RDRF) or
bit 6 (ORFE) is set; when clear, the interrupt is
masked.
Bit 5 TORE Transmit Data Register Empty - set by hardware
when a transfer is made from the transmit data
register to the output shift register. The TDRE bit
is cleared by reading the status register, then
writing a new byte into the transmit data register,
TDRE is initialized to 1 by reset.
Bit 6 ORFE Over-Run-Framing Error - set by hardware when
an overrun or framing error occurs (receive only).
An overrun is defined as a new byte received with
last byte still in Data Register/Buffer. A ~raming
error has occurred when the byte boundaries in bit
stream are not synchronized to bit counter. If WU
flag is set, the ORFE bit will not be set. The
ORFE bit is cleared by reading the status register,
then reading the Receive Data Register, or by
reset.
Bit 7 RORF Receiver Data Register Full - set by hardware
when a transfer from the input shift register to the
receiver data register is made. If WU flag is set,
the RDRF bit will not be set. The RDRF bit is
cleared by reading the status register, then reading
the Receive Data Register, or by reset.
Rate and Mode Control Register
The Rate and Mode Control register controls the follOWing
serial I/O variables:
• Baud rate
• format
• clocking source, and
• Port 2 bit 2 configuration
The register consists of 4 bits all of which are write-only and
cleared by reset. The 4 bits in the register may be considered as
a pair of 2-bit fields. The two low order bits control the bit rate
for internal clocking and the remaining two bits control the
format and clock select logic. The register definition is as
follows:
Rate and Mode Control Register
X
6
5
4
X
X
X
3
2
I I I I eel I eeo I
0
551
550
AD DR : $0010
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
95
HD6801VO,HD6801V5----------------------------------------------------Bit 0 SSO} Speed Select - These bits select the Baud rate for
Bit 1 551 the internal clock. The four rates which may be
selected are a function of the CPU Zero
BGT
2E
3
2
Z + (N @ V) =0
Branch If Higher
BHI
22
3
2
C+Z=O
Branch If.;; Zero
BlE
2F
3
2
Z+ (N@ V) = 1
Branch If lower Or
Same
BlS
23
3
2
C+Z=1
N@V=1
Branch If
< Zero
BlT
2D
3
2
Branch If Minus
BMI
2B
3
2
N=1
Branch If Not Equal
Zero
BNE
26
3
2
Z=O
Branch If Overflow
Clear
BVC
28
3
2
V=O
Branch If Overflow Set
BVS
29
3
2
V =1
Branch If Plus
BPl
2A
3
2
N=O
Branch To Subroutine
BSR
8D
6
2
Jump
JMP
Jump To Subroutine
JSR
No Operation
NOP
01
Return From InterruptI
RTI
3B 10 1
Return From
Subroutine
RTS
39
Software Interrupt
SWI
3F 12 1
Wait for Interrupt
WAI
3E
3
2
7E
3
3
AD 6
2
BD 6
3
6E
9D
Table10
5
2
2
5
9
1
Advances Prog. Cntr.
Only
3
2
1
0
I
N Z
V
C
·· · · ·· ··
·• ·· · ·· ·• ··
·· ·· ·· ·• ·· ··
·· ··• ··• •• ·• ··•
·• · ·• •
···
• · ··• ·
·• ·• · · ·• ••
··
• ··• • ·
·· ·· •• ·· ·· ••
·· ·· ·· ·• ·•• ··
• ··· ·
··· · • ·
• · ·• • ·
·· ®.• •• ·· ••
-@-
1
S
1
Condition Code Register Manipulation Instructions
IAddressingModes
Operations
4
• • •
•
•
None
Branch If Carry Clear
Branch If
5
H
Mnemonic
Condition Code Register
Boolean Operation
IMPLIED
OP
-
#
OC
2
1
Clear Carry
ClC
Clear Interrupt Mask
CLI
OE
2
1
0-+1
Clear Overflow
ClV
OA
2
1
O-+V
Set Carry
SEC
OD
2
1
1 -+ C
Set Interrupt Mask
SEI
OF
2
1
1-+1
Set Overflow
SEV
OB
2
1
l-+V
Accumulator A -+ CCR
TAP
06
2
1
A-+ CCR
CCR -+ Accumulator A
TPA
07
2
1
CCR -+ A
O-+C
5
4
3
2
1
H
I
N
Z
V
·· · ·•
·· ·· •·
•
•
·• · •
··
R
S
0
C
·· ·· •
··· ·· ·•
· •
···
R
R
S
S
---@---
Condition Code Register Notes: (Bit set it test is true and cleared otherwise)
CD
(Bit V)
(Bit C)
(Bit C)
(Bit V)
(Bit V)
(Bit V)
(BitN)
® (All)
® (Bit I)
if§> (All)
® (Bit C)
@
@
@
@
@
(J)
Test: Result = 1oo0oo00?
Test: Result lr OOOOOOOO?
Test: Decimal value of most significant BCD Character greater than nine? (Not cleared if previously set)
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to result to N <±> C after shift has occurred.
Test: Result less than zero? (Bit15=1)
load Condition Code Register from Stack. (See Special Operations)
Set when interrupt occurs. If previously set, a Non-Maskable I nterrupt is required to exit the wait state.
Set according to the contents of Accumulator A.
Set equal to result of Bit 7 (ACCB)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
101
HD6801VO,HD6801V5
Table 11
ACCX
ABA
ABX
ADC
•
•
•
ADDD
•
Direct
3
4
3
5
2
3
ASL
•
ASLD
Extended
Indexed
•
2
ADD
AND
Immediate
ASA
BCC
BCS
•
•
•
•
Instruction Execution Times in Machine Cycle
Implied
Relative
2
INX
3
JMP
4
4
4
JSR
4
LDA
6
4
6
6
4
6
LDD
6
6
LDS
LSR
5
2
3
•
3
4
4
4
•
2
Indexed
Implied
3
3
•
6
4
5
5
5
6
6
4
5
5
5
6
Extended
•
MUL
NEG
2
6
6
4
4
BHI
•
•
BIT
3
4
•
3
ORA
3
PSH
3
PSHX
PUL
4
•
3
•
•
•
•
•
6
6
6
6
•
5
ROL
2
ROR
2
RTI
10
BNE
3
RTS
5
•
•
BRN
•
BVC
•
BVS
6
3
3
•
2
CBA
CLC
•
•
CLI
6
CLR
COM
2
•
2
4
CPX
5
•
DEC
DES
INC
INS
2
3
4
4
STD
4
5
STS
4
5
5
5
STX
4
•
TAP
2
TBA
4
•
6
6
•
3
5
•
•
4
6
TST
•
4
6
•
2
•
6
2
TSX
TXS
•
•
12
TPA
3
3
4
4
SUBD
TAB
3
2
STA
6
6
DEX
EOR
2
SEV
6
6
6
4
SEI
SWI
6
4
2
4
•
3
SEC
4
DAA
•
SUB
6
eLV
CMP
2
SBA
SBC
•
4
3
BSA
•
10
BMI
BRA
•
•
4
PULX
BLS
BPL
Relative
2
NOP
BGT
102
Direct
LSRD
BGE
BLT
Immediate
LDX
BEQ
BLE
ACCX
WAI
•
•
6
3
3
9
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
•
•
•
------------------------------------------------------HD6801VO,HD6801V5
• Summary of Cycle by Cycle Operation
Table 12 provides a detailed description of the information
present on the Address Bus, Data Bus, and the Read/Write line
(R/W) during each cycle for each instruction.
This information is useful in comparing actual with expected
results during debug of both software and hardware as the
control program is executed. The information is categorized in
groups according to addressing mode and number of cycles per
instruction. (In general, instructions with the same addressing
mode and number of cycles execute in the same manner; exceptions are indicated in the table).
Table 12 Cycle by Cycle Operation
Address Mode &
Instructions
Address Bus
Data Bus
IMMEDIATE
2
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Operand Data
LOS
LOX
LDD
3
1
2
3
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
CPX
SUBD
ADDD
4
1
2
3
4
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus F F F F
1
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
3
1
2
3
Op Code Address
Op Code Address + 1
Address of Operand
1
1
1
Op Code
Address of Operand
Operand Data
STA
3
1
2
3
Op Code Address
Op Code Address + 1
Destination Address
1
1
0
Op Code
Destination Address
Data from Accumulator
LOS
LOX
LDD
4
1
2
3
4
Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
STS
STX
STD
4
1
2
3
4
Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand + 1
1
1
0
0
Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)
CPX
SUBD
ADDD
5
1
2
3
4
5
Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus F F F F
1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
JSR
5
1
2
3
4
5
Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1
1
1
1
0
0
Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
DIRECT
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
103
HD6801VO,HD6801V5-----------------------------------------------------Table 12 Cycle by Cycle Operation (Continueo/
Address Mode &
Instructions
Address Bus
Data Bus
INDEXED
3
1
2
3
Op Code Address
Op Code Address + 1
Address Bus F F F F
1
1
1
Op Code
Offset
Low Byte of Restart Vector
4
1
2
3
4
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data
STA
4
1
2
3
4
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
1
1
1
0
Op Code
Offset
Low Byte of Restart Vector
Operand Data
LOS
LOX
LDD
5
1
2
3
Or CodE! Address
4
5
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
1
1
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
5
1
2
3
4
5
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
0
0
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset
1
1
1
1
1
0
Op Code
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data
CPX
SUBD
ADDD
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Index Register + Offset + 1
Address Bus F F F F
1
1
1
1
1
1"
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
JSR
6
1
2
3
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Stack Pointer
Stack Pointer - 1
1
1
1
1
0
0
Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
JMP
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
STS
STX
STD
ASL
ASR
CLR
COM
DEC
INC
LSR
NEG
ROL
ROR
TST*
4
5
6
*
104
Op Cede
In the TST instruction, R/W line of the sixth cycle is"1" level, and AB=FFFF, DB=Low Byte of Reset Vector.
(Continued)
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------HD6801VO,HD6801V5
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Data Bus
Address Bus
EXTENDED
3
JMP
1
2
3
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
STA
4
1
2
3
4
4
1
2
3
4
5
LDS
LDX
LDD
1
2
3
4
5
5
STS
STX
STD
1
2
3
4
5
ASL
ASR
CLR
COM
DEC
INC
LSR
NEG
ROL
ROR
TST*
CPX
SUBD
ADDD
6
1
2
3
4
5
6
6
1
2
3
4
5
6
JSR
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
1
1
1
1
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data
Op Code
Op Code
Op Code
Operand
1
1
1
0
Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)
Address
Address + 1
Address + 2
Destination Address
0
0
Op Code Address
Op Code Addtess + 1
Op Code Address + 2
Address of Operand
Address Bus F F F F
Address of Operand
0
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF
1
1
1
1
1
1
Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
1
1
1
1
1
0
0
* In the TST instruction, R/W line of the sixth cycle is "1" level, and AB = FFFF, DB = Low Byte of Reset Vector.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
(Continuedl
105
HD6801VO,HD6801V5-----------------------------------------------------Table 12 Cycle by Cycle Operation (Continued)
Address Mode, &
Instructions
Data Bus
Address Bus
IMPLIED
ABA
ASL
ASR
CSA
CLC
CLI
CLR
CLV
COM
DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA
ABX
SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Op Code of Next Instruction
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Irrelevant Data
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Irrelevant Data
Low Byte of Restart Vector
Op Code /\ddrcss
1
'-'tJ vvu't;;
Op Code Address + 1
Previous Register Contents
1
1
Op Code of Next Instruction
Irrelevant Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Stack Pointer
1
1
a
Op Code
Op Code of Next Instruction
Accumulator Data
Op Code Address
Op Code Address + 1
Stack Pointer
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Operand Data from Stack
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
a
a
Op Code
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte)
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
1
1
1
1
1
5
Stack Pointer + 2
1
Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
Op Code
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(High Order Byte)
Address of Next Instruction
(Low Order Byte)
1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
1
2
3
1
2
3
ASLD
LSRD
3
DES
3
INS
1
2
3
1
2
3
INX
DEX
3
PSHA
PSHB
3
TSX
3
TXS
3
PULA
PULB
4
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
4
PSHX
4
1
2
3
4
PULX
5
1
2
3
4
5
RTS
5
1
2
3
WAI**
9
2
3
4
106
~HITACHI
a
a
("'\1"'Ior" ..... .....a,."
..
_...
Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High .order Byte)
(Contmued)
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------HD6801VO,HD6801V5
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Cycles
Cycle
#
5
6
7
WAI**
8
9
MUL
10
SWI
10
12
Stack
Stack
Stack
Stack
Stack
Pointer
Pointer
Pointer
Pointer
Pointer
-
2
3
4
5
6
R/W
Line
0
0
0
0
0
Data Bus
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
10
Op Code Address
Op Code Address + 1
Address Bus FFFF
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
1
1
1
1
1
1
1
1
1
1
Op Code
Irrelevant Data
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
5
Stack Pointer + 2
1
6
Stack Pointer + 3
1
7
Stack Pointer + 4
1
8
Stack Pointer + 5
1
9
Stack Pointer + 6
1
10
Stack Pointer + 7
1
Op Code
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next I nstruction Address from
Stack (Low Order Byte)
10
11
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Stack Pointer - 7
Vector Address FFFA (Hex)
1
1
0
0
0
0
0
0
0
1
1
12
Vector Address FFFB (Hex)
1
1
2
3
4
5
6
7
8
9
RTI
Address Bus
1
2
3
4
5
6
7
8
9
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Op Code
Irrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index·Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)
**While the MCU is in the "Wait" state, its bus state will appear as a series of MCU reads of an address which is seven locations less than the
original contents of the Stack Pointer. Contrary to the HD6800, none of the ports are driven to the high impedance state by a WAI instruction.
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
107
HD6801VO,HD6801V5-----------------------------------------------------Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instruction
Data Bus
Address Bus
RELATIVE
Bce
BCS
BEQ
BGE
BGT
BRN
BHT
BLE
BLS
BL T
BMT
BNE
BPL
BRA
BVC
BVS
BSR
3
1
2
3
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Branch Offset
Low Byte of Restart Vector
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
Op Code
Branch Offset
Low Byte of Restart Vector
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
~
Summai"; uf Uiidefined liiiti"iJctiuii Operations
The HD6801 V has 36 undefmed instructions. When these are
carried out, the contents of Register and Memory in MCU
change at random.
0
0
When the op codes (4E, SE) are used to execute, the MCU
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the
LSI.
Table 13 Op codes Map
HD6801 V MICROCOMPUTER INSTRUCTIONS
OP
CODE
ACC
A
~
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0000
0001
1
0
---
0011
2
3
SBA
BRA
TSX
CBA
BRN
INS
----------- --NOP
0010
~
BHI
PULA (+1)
BLS
PULB (+1)
~~
BCC
DES
ASLD (+1)
~
BCS
TXS
TAP
TAB
BNE
PSHA
LSRD (+1)
0111
7
TPA
TBA
BEQ
PSHB
1000
8
INX (+1)
PULX (+2)
1001
9
DEX (+1)
---
BVC
DAA
BVS
RTS (+2)
1010
A
CLV
~
BPL
ABX
1011
B
SEV
ABA
BMI
RTI (+7)
1100
C
CLC
~
BGE
PSHX (+1)
1101
D
SEC
BLT
MUL (+7)
1110
E
CLI
BGT
WAI (+6)
1111
F
SEI
~
BLE
SWI (+9)
1/2
1/2
2/3
1/3
BYTE/CYCLE
[NOTES]
/
/
ACC IND
B
0100 0101
ACCA or SP
EXT
0110 0111
----------
4
5
6
IMM
100011001J 1010] 1011
7
8
IMM
I DIR
liND
I EXT
1100111011111011111
1 9 1 AlB
NEG
C
1 DIE 1
F
0
SUB
CMP
SBC
COM
*
: SUBD (+2)
*
:
ADDD (+2)
AND
BIT
5
ROR
LDA
6
/1
//
STA
STA
EOR
8
ROL
ADC
9
DEC
ORA
A
INC
*
TST
BSR/
JMP (-3)
--- ** ---CLR
1/2
2/6
J+41
*
CPX (+2)
JSR (+2)
LDS (+1)
::. (+1)1
3/6
B
ADD
2/2 \ 2/3
STS (+1)
I 2/4 I 3/4
LDD (+1)
*
* (+1)/
LDX (+1)
*
* (+1)1
2/2
STD (+1)
STX (+1)
I 2/3 I 2/4 I 3/4
) indicate that the number in parenthesis must be added to the cycle count for that instruction.
3) The instructions shown below are all 3 bytes and are marked with "*".
Immediate addressing mode of SUBD, CPX, LDS, ADDD, LDD and LDX instructions, and undefined op codes
(8F, CD, CF).
4) The Op codes (4E, 5E) are 1 byte/ oo cycles instructions, and are marked with "**,,
108
7
ASL
1) Undefined Op codes are marked with ~ .
2) (
3
4
LSR
ASR
1/2
ACCB or X
I DIR liND I EXT
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
C
0
E
F
I
s:
(')
=»
3
~
o·
D)
c:
?-
•
I\)
~
o
o
~
~~
_
~:I
CD
.
~
• l>
00(')
~ :I
~
o
en
_CD
()
»
<0
01
~
*SCI
•
= TIE·TORE + RIE'(RORF + ORFE)
~
o
$
Vector
-+
PC
~
fJMI
FFFC FFFO
01
SWI
FFFA FFFB
Software Interrupt
00
IRQ,
FFF8FFF9
o
o
ICF
OCF
TOF
SCI
FFF6
FFF4
FFF2
FFFO
Maskable Interrupt Request 1
Input Capture Interrupt
Output Compare Interrupt
Timer Overflow Interrupt
UJ
W
FFF7
FFF5
FFF3
FFFl
Non-Maskable Interrupt
SCI Interrupt (TORE + RORF + ORFE)
:::I:
CJ
0)
CO
o.....
<
P
:::I:
CJ
0)
CO
o
-<>
Figure 24 Interrupt Flowchart
o
.....
<
01
HD6801VO,HD6801V5-----------------------------------------------------Vee
Enable
Enable
NMI
Vee Standby
Port 3
8 Transfer
RES
Lines
Port 1
81/0
Lines
Port 1
8 I/O Lines
'--_. . . . _......J.,........,.
Port 4
81/0 Lines
Port 2
51/0 Lines
SCI
16 Bit Timer
Port 4
81/0 Lines
Port 2
51/0 Lines
SCI
Vss
Figure 25
HD6801 V MCU Single-Chip Dual Processor Configuration
~
MCU
~
MCU
Address
Bus
Data
Bus
Figure 26 HD6801 V MCU Expanded Non-Multiplexed Mode
Data Bus
Address Bus
Figure 27 HD6801 V MCU Expanded Multiplexed Mode
•
Caution for the HD6801 Family SCI, TIMER Status Flag
The flags shown in Table 14 are cleared by reading/writing
(flag reset condition 2) the data register corresponding to each
flag after reading the status register (flag reset condition I).
To clear the flag correctly, take the following procedure:
1. Read the status register
2. Test the flag
3. Read the data register
Table 14 Status Flag Reset Conditions
Status
Flag
ICF
TIMER
f--
OCF
f--
TOF
RDRF
SCI
f--
ORFE
f--
TORE
110
Flag Reset
Condition 1
(Status Register)
When each flag is
"1",
TRCSR/Read
When each flag is
"1",
TRCSR/Read
Flag Reset Condition 2
(Data Register)
ICR/Read
OCRlWrite
TC/Read
RDR/
Read
TOR/Write
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6803, HD6803-1---M PU (Micro Processing Unit)
The HD6803 MPU is an 8-bit micro processing unit which
is compatible with the HMCS6800 family of parts. The HD6803
MPU is object code compatible with the HD6800 with improved
execution times of key instructions plus several new 16-bit and
8-bit instruction including an 8 x 8 unsigned multiply with
16-bit result. The HD6803 MPU can be expanded to 65k bytes.
The HD6803 MPU is TTL compatible and requires one +0.5
volt power supply. The HD6803 MPU has 128 bytes of RAM,
Serial Communications Interface (S.C.I.), and parallel I/O as
well as a three function 16-bit timer. Features and Block
Diagram of the HD6803 include the following:
HD6803P
HD6803p·,
(DP·40)
•
•
FEATURES
Expanded HMCS6800 Instruction Set
•
•
8 x 8 Multiply
On-Chip Serial Communications Interface (S.C. I. )
•
Object Code Compatible with The HD6800 MPU
•
•
•
•
16-Bit Timer
Expandable to 65k Bytes
Multiplexed Address and Data
128 Bytes of RAM (64 Bytes Retainable On Power
Down)
•
•
•
13 Parallel I/O Lines
Internal Clock/Divided-By-Four
TTL Compatible Inputs and Outputs
•
•
Interrupt Capability
Compatible with MC6803 and MC6803-1
•
PIN ARRANGEMENT
o
AS
RM
°u/Ao
°IIA I
RES
02/ A 2
OJ/Aj
o,/A,
P ln
05/ A S
P"
P"
BLOCK DIAGRAM
•
IRa,
HD6803
1 06/ A b
P"
O,iA7
P"
A.
p,.
A.
POI
A, •
P"
All
POl
A"
P"
A"
A"
P'5
PI.
Standby
Do/A.
D,/A,
D,/A,
D,/A,
D./A.
D./A.
D./A.
D,/A,
R/W
(Top View)
....+---il-+--P,.
ioo+-.......>-+-_P"
~+-..---P22
1oo-I-.j.....4.
___ P"
~+-+-+--.--P"
AS
A.
A.
----P,O
Au
::...-:=--:=--:=- ~::
A"
t-----PI.
PH
----P"
A,.
A"
t-----~::
All
All
•
TYPE OF PRODUCTS
Type No.
Bus Timing
HD6803
1.0MHz
HD6803-1
1.25MHz
Vee Standby
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
111
HD6803,HD6803-1----------------------------------------------__________
•
ABSOLUTE MAXIMUM RATINGS
Item
Input Voltage
Vee *
V in *
Operating Temperature
Topr
Storage Temperature
Tm
•
Value
Unit
-0.3 - +7.0
V
Symbol
Supply Voltage
V
-0.3 - +7.0
0
°c
-+70
°c
- 55 - +150
With respect to VSS (SYSTEM GNO)
[NOTE] Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI.
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee =5.0V±5%, Vss = OV, Ta = O-+70°C, unless otherwise noted.)
Item
Input "High" Voltage
Symbol
RES
Other Inputs*
Test Condition
V IH
Input "Low" Voltage
All Inputs*
V IL
Input Load Current
EXTAL
Ilinl
Input Leakage Current
NMI, IRQI, RES
Ilinl
= 0 - Vee
V in = 0 - 5.25V
\ITS"
V in
Three State (Offset)
PIO - PI7 , Do/Ao- D7/ A 7
Leakage Current
P20
Output "High" Voltage
As - ~IS, E, R/W, AS
-
P24
Do/Ao - D7/ A 7
V OH
Other Outputs
Output "Low" Voltage
All Outputs
Darlington Drive Current P IO
Power Dissipation
I nput Capacitance
Vee Standby
Standby Current
-
P 17
Do/Ao - D7 /A 7
Other Inputs
VOL
-IOH
PD
Cin
V in
= 0.5 - 2.4V
min
typ
max
4.0
-
Vee
2.0
-
-0.3
-
Vee
0.8
-
-
0.8
mA
-
-
2.5
p,A
-
-
10
-
100
Unit
V
V
p,A
I LOAD
2.4
-
-
I LOAD
2.4
-
-
2.4
-
-
-
-
0.5
V
1.0
10.0
mA
-
-
1200
mW
-
-
12.5
= -205p,A
= -145p,A
I LOAD = -100p,A
I LOAD = 1.6 mA
V out = 1.5V
V in
f
= OV, Ta = 25°C,
= 1.0 MHz
-
10.0
Powerdown
V SBB
4.0
-
5.25
Operating
V SB
4.75
-
5.25
Powerdown
ISBB
-
-
8.0
VSBB
= 4.0V
V
pF
V
mA
• Except Mode Programming Levels.
112
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - H06803,H06803-1
•
AC CHARACTERISTICS
BUS TIMING (Vee = 5.0V ± 5%, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)
Item
Symbol
Cycle Time
Address Strobe Pulse Width "High" *
tCYC
PW ASH
Address Strobe Rise Time
t ASr
Test
Condition
HD6803
min
HD6803-1
typ
max
1
-
200
-
-
5
-
50
10
min
typ
0.8
-
150
-
5
max
10
Unit
ps
-
ns
-
50
ns
50
ns
-
ns
50
ns
50
ns
-
ns
-
ns
-
ns
Address Strobe Fall Time
t ASf
5
-
50
Address Strobe Delay Time *
t ASO
60
-
-
Enable Rise Time
t Er
5
-
50
5·
Enable Fall Time
5
-
50
5
Enable Pulse Width "High" Time *
tEf
PWEH
450
-
-
340
Enable Pulse Width "Low" Time *
PW EL
450
-
-
350
-
Address Strobe to Enable Delay Time *
t ASEO
60
-
-
30
-
Address Delay Time
tAD
t AOL
-
-
260
-
-
260
ns
Address Delay Time for Latch *
-
270
-
-
260
ns
Data Set-up Write Time
tosw
225
Data Set-up Read Time
tOSR
80
Fig. 1
5
30
Read
tHR
10
Write
20
Address Set-up Time for Latch *
tHW
t ASL
-
60
-
-
Address Hold Time for Latch
tAHL
20
-
-
Address Hold Time
20
-
-
Oscillator stabilization Time
tAH
(t ACCM )
t RC
Fig.8
100
-
-
100
Processor Control Set-up Time
tpcs
Fig. 7,8
200
-
-
200
Data Hold Time
I
I
Peripheral Read Access Time (Multiplexed Bus)*
-
(600)
115
-
-
ns
70
-
-
ns
10
-
-
20
-
-
50
-
-
ns
20
-
-
ns
-
ns
20
-
-
-
(420)
-
ns
ns
ms
ns
*These timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc is minimum
(= in the highest speed operation).
PERIPHERAL PORT TIMING (Vee = 5.0V ± 5%, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)
Item
Symbol
Test Condition
min
typ
max
Unit
Peripheral Data Setup Time
Port 1,2
tposu
Fig.2
200
-
-
ns
Peripheral Data Hold Time
Port 1, 2
tpOH
Fig.2
200
-
-
ns
Delay Time, Enable Negative
Transition to Peripheral Data
Valid
Port 1, 2*
t pwo
Fig.3
-
-
400
ns
* Except P21
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
113
H06803,H06803-1--------------------------------------__________________
TIMER, SCI TIMING (Vee
= S.OV ±So/cr, Vss = OV, Ta = 0 -
Item
+70°C, unless otherwise noted.)
Symbol
Timer Input Pulse Width
tPWT
Delay Time, Enable Positive Transition to
Timer Out
t TOD
min
2t cyc +200
-
Fig.4
SCI Input Clock Cycle
tSCYC
SCI Input Clock Pulse Width
tpwSCK
MODE PROGRAMMING (Vee
Test Condition
= S.OV ±S%, Vss = OV, Ta = 0 -
typ
max
-
-
ns
-
600
ns
Unit
1
-
-
tcyc
0.4
-
0.6
tScyc
+10°C, unless otherwise noted.)
min
typ
max
Unit
Mode Programming Input "Low" Vo1tage
V MPL
-
-
1.7
V
Mode Programming Input "High" Voltage
V MPH
4.0
-
-
V
3.0
-
-
tcyc
Item
Symbol
PW RSTL
RES " Low" Pulse Width
Mode Programming Set-up Time
Mode Programming
Hold Time
Test Condition
Rise Time ~ 1J,Ls
RES Rise Time
1J,Ls
L RES
j
<
Fig.5
tMPs
2.0
-
tMPH
0
100
-
tcyc
ns
~---------------------tcyc----------------------~
Address Strobe
(AS)
2.2V
O.6V
Enable
(E)
R/W
A,-A ..
IHIII/
MPU Wrote
Do/A" - D,/A,
(Port 3)
MPU Read
D"/A,, - O;/A,
(Port 3)
1----(tACCM)----
Figure 1 Expanded Multiplexed Bus Timing
114
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave .• San Jose, CA 95131 • (408) 435-8300
---------------------------H06803,H06803-1
r
r-MPU Read
MPUWrite
Enable (E)
Enable (E)
\
*
O.5V
/
!::=tPWDXl----
All Data
2.2V
Port O u t p u t s O . 6 V Data Valid
• Not appl icable to P"
Figure 2
Data Set-up and Hold Times
(MPU Read)
Figure 3 Port Data Delay Timing
(MPU Write)
Enable (E)
RES
Timer
Counter _ _ _ _....J
Mode Inputs _ _ _ _ _..-;;:.:.;...:.~
(P,., P", P,,)
Pl i
Output
Figure 5 Mode Programming Timing
Figure 4
Timer Output Timing
Vee
Rl =2.2kO
Test POint
m
1S2074
rH'
or EQurv
C
R
TTL Load
Figure 6 Bus Timing Test Load
~HITACHI
Hitachi America Ltd_ • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
115
HD6803,HD6803-1----------------------------------------__________________
Last In.truction
-1
Cycle
#1
Enable lEI
Internal
Address Bu • .J\--J"...._.....,'-_...J'-_...J'__...J1\.-_J,_ _J'\. _ _J\. _ _, ' - _......~_~"__...J'__...r._ _J\. _ _A.._ _
......
Internal""'\.~-""".---~--..,.--..,.-""""~--.~-"""--~--"'V"--"V"--..,.--"""--"V"--..,.-
v_-
Data Bu • ...I1.......--"--"'-O-p-Cod---'e"-OP-Co-d....."P-C-O--P-C"7'-pc-a---PC-15''----I''--...J''---''-A-CC-a-'''--"'''''-lr-re-leY-a-nt-''-Y-ec-to-r"'---"-Fi-rs-tl-nsJt."'o-'\~
Internal RtW
*
Enable IE)
Vee
IRQ~ ; Internal interrupt
_\\~\\\\\~
_
_______________-JI
5.25Y
\
1i+--
§\\\\\\\\\\\\\\\
~
I
n n
L.J
L.J
n n n n n n
~...
~
L.J
LJ
LJ
L....J
(~(===t-RC~~~~~--'~~ ~tPCS
I nterrupt Routine
=
fUl..J1J
~. I
~. ~tPCS
~l-------------~S ~4.6v
Adl;r~:n:~.
S\\\\\\\\\\\\\\\\\\\\~ }\$\\\\\\\\\S\\\\\\\\\\\\\\sw--Y
•
~ FFFE
RtW
MSB
Figure 7 Interrupt Sequence
4 7 5Y
. _ __ _ _
RES _ _ _ _ _ _ _..,.
Internal
Data
\\\\\\\t\\\\\\\&\\\~ ~\S\S\\\\\\\\\\\\\\\\\S\\S\Y
6~t~r;~! $\\\\\%\\\\\\\\~~ ,%S\S\\\\\\\\S\SSSS\S\SS\\SSSX:::
~NotYalid
=
FFFE
FFFE
.l~p;:.::.o.;::.av~----FFFF
r-v--v--v~E
New PC
"< ~
pc:::::x:::::x=
PCB-PC15 PCQ-PC7 Forst
Instruction
Figure 8 Reset Timing
• SIGNAL DESCRIPTIONS
•
Nominal Crystal Parameter
VCC and VSS
These two pins are used to supply power and ground to the
chip. The voltage supplied will be +5 volts ±5%.
•
XTAL and EXTAL
These connections are for a parallel resonant fundamental
crystal, AT cut. Devide·byA circuitry is included with the
internal clock, so a 4 MHz crystal may be used to run the
system at I MHz. The devide·byA circuitry allows for use of the
inexpensive 3.58 MHz Color TV crystal for non-time critical
applications. Two 22pF capacitors are needed from the two
crystal pins to ground to insure reliable operation. An example
of the crystal interface is shown in Fig. 9. EXT AL may be
driven by an external TTL compatible source with a 45% to
55% duty cycle. It will devided by 4 any frequency less than
or equal to 5 MHz. XT AL must be grounded if an external
clock is used.
116
Item
~
4 MHz
5 MHz
Co
7pF max.
4.7pF max.
RS
60n max.
30n typo
XTALr---~------,
CJ
C L1
= C L2 = 22pF ± 20%
(3.2 - 5 MHz)
EXT A L r-----e--,
[NOTE] AT cut parallel
resonance parameters
Figure 9 Crystal Interface
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6803,HD6803-1
E following the completion of an
• vee Standby
This pin will supply +5 volts ±5% to the standby RAM on the
chip. The first 64 bytes of RAM will be maintained in the power
down mode with 8 mA current max. The circuit of figure 13
can be utilized to assure that Vee Standby does not go below
V SBB during power down.
To retain information in the RAM during power down the
following procedure is necessary:
I) Write "0" into the RAM enable bit, RAME. RAME is bit
6 of the RAM Control Register at location $0014. This
disables the standby RAM, thereby protecting it at power
down.
2) Keep Vee Standby greater than VSBB.
Figure 10 Battery Backup for Vee Standby
•
Reset (RES)
This input is used to reset and start the MPU from a power
down condition, resulting from a power failure or an initial
startup of the processor. On power up, the reset must be held
"Low" for at least 100 ms. When reset during operation, RES
must be held "Low" at least 3 clock cycles.
When a "High" level is detected, the CPU does the following;
I) All the higher order address lines will be forced "High".
2) I/O Port 2 bits, 2, I, and 0 are latched into programmed
control bits PC2, PC I and PeO.
3) The last two ($FFFE, $FFFF) locations in memory will
be used to load the program addressed by the program
counter.
4) The interrupt mask bit is set. Clear before the CPU can
recognize maskable interrupts.
• Enable (E)
This supplies the external clock for the rest of the system
when the internal oscillator is used. It is a single phase, TTL
compatible clock, and will be the divide- by- 4 result of the
crystal oscillator frequency. It will drive one TTL load and 90
pF capacitance.
• Non-Maskable Interrupt (NMI)
When the falling edge of the input signal is detected at this
pin, the CPU begins non-maskable interrupt sequence internally.
As with interrupt Request signal, the processor will complete
the current instruction that is being executed before it recognizes
the NMI signa\. The interrupt mask bit in the Condition Code
Register has no effect on NMI.
In response to an NMI interrupt, the Index Register, Program
Counter, Accumulators, and Condition Code Register are stored
on the stack. At the end of the sequence, a l6-bit address will
be loaded that points to a vectoring address located in memory
locations $FFFC and $FFFO. An address loaded at these locations causes the CPU to branch to a non-maskable interrupt
service routine in memory.
A 3.3 kS1 external resistor to Vee should be used for
wire-OR and optimum control of interrupts.
Inputs IRQ I and NMI are hardware interrupt lines that are
sampled during E and will start the interrupt routine on the
instruction.
•
Interrupt Request (lRQI)
This level sensitive input requests that an interrupt sequence
be generated within the machine. The processor will complete
the current instruction before it recognizes the request. At
that time, if the interrupt mask bit in the Condition Code
Register is not set, the machine will begin an interrupt sequence. The Index Register, Program Counter, Accumulators,
and Condition Code Register are stored on the stack. Next the
CPU will respond to the interrupt request by setting the interrupt mask bit "High" so that no further maskable interrupts
may occur. At the end of the cycle, a 16-bit address will be
loaded that points to a vectoring address which is located
in memory locations $FFF8 and $FFF9. An address loaded
at these locations causes the CPU to branch to an interrupt
routine in memory.
The IRQI requires a 3.3 kS1 external resistor to Vee which
should be used for wire-OR and optimum control of inte~ts.
Internal Interrupts will use an internal interrupt line (lRQ2)'
This interrupt will operate the same as IRQ I except that it will
use the vector address of $FFFO through $FFF7. IRQI will
have priority to IRQ2 if both occur at the same time. The
Interrupt Mask Bit in the condition code register masks both
interrupts (See Table I).
Table 1 Interrupt Vector Location
Vector
Highest
Priority
Lowest
Priority
Interrupt
MSB
LSB
FFFE
FFFF
RES
FFFC
FFFO
NMI
Software Interrupt (SWI)
FFFA
FFFB
FFF8
FFF9
IRQ I
FFF6
FFF7
ICF (Input Capture)
FFF4
FFF5
OCF (Output Compare)
FFF2
FFF3
TOF (Timer Overflow)
FFFO
FFFl
SCI (RORF + ORFE + TORE)
•
ReadlWrite (RiW)
This TTL compatible output signals the peripherals and
memory devices whether the CPU is in a Read ("High") or a
Write ("Low") state. The normal standby state of this signal is
Read ("High"). This output can drive one TTL load and 90pF
capacitance.
• Address Strobe (AS)
In the expanded multiplexed mode of operation, address
strobe is output on this pin. This signal is used to latch the 8
LSB's of address which are multiplexed with data on Do / Ao
to 0 7/ A 7 . An 8-bit latch is utilized in conjunction with Address
Strobe, as shown in figure II. So Do / Ao to 0 7/ A7 can become
data bus during the E pUlse. The timing for this signal is shown
in Figure I of Bus Timing. This signal is also used to disable the
address from the multiplexed bus allowing a deselect time, tASD
before the data is enabled to the bus.
• PORTS
There are two I/O ports on the HD6803 MPU; one 8·bit
port and one 5·bit port. Each pori has an associated write
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
117
H06803,H06803-1-------------------------------------------------------only Data Direction Register which allows each I/O line to be
programmed to act as an input or an output *. A "1" in the
corresponding Data Direction Register bit will cause that I/O
line to be an output. A "0" in the corresponding Data Direction
Register bit will cause that I/O line to be an input. There are
two ports: Port I, Port 2. Their addresses and the addresses of
their Data Direction registers are given in Table 2.
* The only exception is bit 1 of Port 2, which can either be data
input or Timer output.
Table 2 Port and Data Direction Register Addresses
Ports
Data Direction
Register Address
Port Address
1/0 Port 1
$0002
$0000
1/0 Port 2
$0003
$0001
state when used as an input. In order to be read properly, the
voltage on the input lines must be greater than 2.0 V for a
logic "I" and less than 0.8 V for a logic "0". As outputs, this
port has no internal pullup resistors but will drive TTL inputs
directly. For driving CMOS inputs, external pullup resistors are
required. After reset, the I/O lines are configured as inputs.
Three pins on Port 2 (pin 8, 9 and 10 of the chip) are requested
to set following values (Table 3) during reset. The values of
above three pins during reset are latched into the three MSBs
(Bit 5, 6 and 7) of Port 2 which are read only.
Port 2 can be configured as I/O and provides access to the
Serial Communications Interface and the Timer. Bit I is the
only pin restricted to data input or Timer output.
Table 3 The Values of three pins
I/O Port 1
This is an 8-bit port whose individual bits may be defined as
inputs or outputs by the corresponding bit in its data direction
Pin Number
8
Value
9
H
10
L
•
ron;,..+n...
H,,&o.>L'.d...
'1"" ..........
0
...... ~ ... _ .....
L ... C'C'... __
1 1\...
U
VUlPUL
UUllC:J.~
.I.
L_ •• _
lldVC
.LL ___ _ . L _ . l . _
1°'°.
lJlict::-~lalt::
(,,;apaUUJLY,
allowing them to enter a high impedance state when the
peripheral data lines are used as inputs. In order to be read
properly, the voltage on the input lines must be greater than 2.0
V for a logic "I" and less than 0.8 V for a logic "0". As outputs,
these lines are TTL compatible and may also be used as a source
of up to I rnA at 1.5 V to directly drive a Darlington base. After
reset, the I/O lines are configured as inputs.
•
[NOTES]
I/O Port 2
This port has five lines that may be defined as inputs or
outputs by its data direction register. The 5 output buffers have
three-state capability, allowing them to enter a high impedance
L
L; Logical "0"
u. ....
l~i"'''31''1''
",
..,~..........
.
• BUS
•
Data/Address Lines (Do/Ao ~ D7/A7)
Since the data bus is multiplexed with the lower order
address bus in Data/Address, latches are required to latch those
address bits. The 74LS373 Transparent Octal D-type latch can
be used with the HD6803 to latch the least Significant address
byte. Figure II shows how to connect the latch to the HD6803 .
The output control to the 74LS373 may be connected to
ground.
•
Address Lines (A8 ~ A15)
Each line is TTL compatible and can drive one TTL load and
90 pF. After reset, these pins become output for upper order
address lines (A8 to A15 ).
GND
•
AS
INTERRUPT FLOWCHART
The Interrupt flowchart is depicted in Figure 16 and is common to every interrupt excluding reset.
I
G OC
D,
D'''/Add''. [
a,
74LS373
D,
Function Table
Address: Ao -A,
Output
Control
a,
L
L
L
H
Enable
Output
G
D
a
H
H
H
H
L
L
L
O.
x
x
x
Figure 11 Latch Connection
118
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
Z
---------------------------------------------------------H06803,H06803-1
•
MEMORY MAP
• PROGRAMMABLE TIMER
The MPU can provide up to 65k byte address space. A
memory map is shown in Figure 12. The first 32 locations are
reserved for the MPU's internal register area, as shown in Table
4 with exceptions as indicated.
Table 4
Internal Register Area
Register
Port
Port
Port
Port
1
2
1
2
Data
Data
Data
Data
Not
Not
Not
Not
Used
Used
Used
Used
Address
Direction Register""
Direction Register""
Register
Register
00
01
02
03
04"
05"
06"
07"
Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
Output Compare Register (High Byte)
08
09
OA
OB
Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Not Used
OC
OD
OE
OF"
Rate and Mode Control Register
Transmit/Receive Control and Status Register
Receive Data Register
Transmit Data Register
10
11
12
13
RAM Control Register
Reserved
14
15-1F
" External Address
"" 1; Output, 0; Input
Multiplexed/RAM
$0000
The HD6803 contains an on-chip 16-bit programmable timer
which may be used to measure an input waveform while independently generating an output waveform. Pulse widths for
both input and output signals may vary from a few microseconds to many seconds. The timer hardware consists of
• an 8-bit control and status register,
a 16-bit free running counter,
• a 16-bit output compare register,
a 16-bit input capture register
A block diagram of the timer registers is shown in Figure 13.
•
Free Running Counter ($0009:$OOOA)
The key element in the programmable timer is a 16-bit free
running counter which is driven to increasing values by E (Enable). The counter value may be read by the CPU software at
any time. The counter is cleared to zero by reset and may be
considered a read-only register with one exception. Any CPU
write to the counter's address ($09) will always result in preset
value of $FFF8 being loaded into the counter regardless of the
value involved in the write. This preset figure is intended for
testing operation of the part, but may be of value in some
applications.
•
Output Compare Register ($OOOB:$OOOC)
The Output Compare Register is a 16-bit read/write register
which is used to control an output waveform. The contents of
this register are constantly compared with the current value of
the free running counter. When a match is found, a flag is set
(OCF) in the Timer Control and Status Register (TCSR) and the
current value of the Output Level bit (OLVL) in the TCSR is
clocked to the Output Level Register. Providing the Data
Direction Register for Port 2, Bit 1 contains a "1" (Output),
the output level register value will appear on the pin for Port 2
Bit I. The values in the Output Compare Register and Output
Level bit may then be changed to control the output level on
the next compare value. The Output Compare Register is set to
$FFFF during reset. The Compare function is inhibited for
one cycle following a write to the high byte of the Output
Compare Register to insure a valid 16-bit value is in the register
before a compare is made.
•
Internal Registers
$001 F
External Memory Space
$0080
I nternal RAM
$OOFF
Input Capture Register ($OOOD:$OOOE)
The Input Capture Register is a 16-bit read-only register used
to store the current value of the free running counter when the
proper transition of an external input signal occurs. The input
transition change required to trigger the counter transfer is
controlled by the input Edge bit (IEDG) in the TCSR. The Data
Direction Register bit for Port 2 Bit 0, should * be clear (zero)
in order to gate in the external input signal to the edge detect
unit in the timer.
The input pulse width must be at least two E-cycles to
ensure an input capture under all conditions.
External Memory Space
* With Port 2 Bit 0 configured as an output and set to "1", the
external input will still be seen by the edge detect unit.
$FFFO
....-----4,
$FFFF~_ _ _~
} External Interrupt Vectors
[NOTE)
Excludes the following addresses which may
be used externally: $04, $05, $06, $07, and
$OF.
Figure 12 HD6803 Memory Map
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
119
H06803,H06803-1------------------------------------------------------__
HD6803 Internal Bus
Bit 1
Port 2
OOR
r-l
Lj--J Output Compare Pulse
IIRo,
Output
Level
elt
1
Port 2
Input
Edge
elt
0
Port 2
Figure 13 Block Diagram of Programmable Timer
Timer Control and Status Register
7
6
ICF I OCF
•
5
4
TOF I EICI
Timer Control and Status Register (TCSR) ($0008)
The Timer Control and Status Register consists of an 8-bit
register of which all 8 bits are readable but only the low order 5
bits may be written. The upper three bits contain read-only
timer status information and indicate the followings:
• a proper transition has taken place on the input pin with a
'subsequent transfer of the current counter value to the
input capture register .
• a match has been found between the value in the free
running counter and the output compare register, and
when $0000 is in the free running counter.
Each of the flags may be enabled onto the HD6803 internal
bus (IRQ2) with an individual Enable bit in the TCSR. If the
I-bit in the HD6803 Condition Code register has been cleared, a
prior vectored interrupt will occur corresponding to the flag
bit(s) set. A description for each bit follows:
Bit 0 OL VL Output Level - This value is clocked to the output
level register on a successful output compare. If
the DDR for Port 2 bit I is set. the value will
appear on the output pin.
Bit 1 IEDG Input Edge - This bit controls which transition of
an input will trigger a transfer of the counter to
the input capture register. The DDR for Port 2 Bit
o must be clear for this function to operate. IEDG
= 0 Transfer takes place on a negative edge
("High"-to-"Low" transition).
lEDG = 1 Transfer takes place on a positive edge
120
I
2
1
EOCI I ETOIIIEDG
I
0
OLVL\ $0008
("Low" -to-"High" transition).
Bit 2 ETOI Enable Timer Overflow Interrupt - When set, this
bit enables IRQ2 to occur on the internal bus for a
TOF interrupt; when clear the interrupt is inhibited .
Bit 3 EOCI Enable Output Compare Interrupt - When set,
this bit enables IRQ2 to appear on the internal 'bus
for an output compare interrupt; when clear the
in terrupt is inhibited.
Bit 4 EICI Enable input Capture Interrupt - When set, this
bit enables IRQ2 to occur on the internal bus for
an input capture interrupt; when clear the interrupt is inhibited.
Bit 5 TOF Timer Overflow Flag - This read-only bit is set
when the counter contains $FFFF. It is cleared by
a read of the TCSR (with TOF set) followed by an
CPU read of the Counter ($09).
Bit 6 OCF Output Compare Flag - This read-only bit is set
when a match is found between the output
compare register and the free running counter. It is
cleared by a read of the TCSR (with OCF set)
followed by an CPU write to the output compare
register (SOB or SOC).
Bit 7 ICF
Input Capture Flag - This read-only status bit is
set by a proper transition on the input; it is cleared
by a read of the TCSR (with ICF set) followed by
an CPU read of the Input Capture Register ($OD).
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave_ • San Jose, CA 95131 • (408) 435-8300
-----------------------------HD6803,HD6803-1
• SERIAL COMMUNICATIONS INTERFACE
The H06803 contains a full-duplex asynchronous serial
communications interface (SCI) on chip. The controller
comprises a transmitter and a receiver which operate independently or each other but in the same data format and at the same
data rate. Both transmitter and receiver communicate with the
CPU via the data bus and with the outside world via pins 2, 3,
and 4 of Port 2. The hardware, software, and registers are explained in the following paragraphs.
Bit 7
I
Rate and Mode Control Register
I I I I
CCI
CCO
S5 I
Bit 0
5S0
1$10
Transmit/Receive Control and Status Register
Port 2
• Wake-Up Feature
In a typical multi-processor application, the software
protocol will usually contain a destination address in the initial
byte(s) of the message. In order to permit non-selected MPU's
to ignore the remainder of the message, a wake-up feature is
included whereby all further interrupt processing may be
optionally inhibited until the beginning of the next message.
When the next message appears, the hardware re-enables (or
"wakes-up") for the next message. The "wake-up" is automatically triggered by a string of ten consecutive I's which
indicates an idle transmit line. The software protocol must
provide for the short idle period between any two consecutive
messages.
Receive Shift Register
Clock
B.t
2
Tx
I+----E
12
BIt
4
Programmable Options
The following features of the H06803 serial I/O section are
programmable:
· format - standard mark/space (NRZ)
• Clock - external or internal
• baud rate - one of 4 per given CPU 4>2 clock frequency or
external clock x8 input
• wake-up feature - enabled or disabled
• Interrupt reque~ts - enabled or masked individually for
transmitter and receiver data registers
• clock output - internal clock enabled or disabled to Port
2 (Bit 2)
• Port 2 (bits 3 and 4) - dedicated or not dedicated to serial
I/O individually for transmitter and receiver.
• Serial Communications Hardware
The serial communications hardware is controlled by 4
registers as shown in Figure 14. The registers include:
• an 8-bit control and status register
• a 4-bit rate and mode control register (write only)
• an 8-bit read only receive data register and
• an 8-bit write only transmit data register.
In addition to the four registers, the serial I/O section utilizes
bit 3 (serial input) and bit 4 (serial output) of Port 2. Bit 2 of
Port :2 is utilized if the internal-clock-out or external-clack-in
options are selected.
10
I+-----''''-------~
•
Transmit Data Register
Figure 14 Serial I/O Registers
Bit 0 WU
"Wake-up" on Next Message - set by H06803
software and cleared by hardware on receipt of
ten consecutive I's or reset of RE flag. It should
be noted that RE flag should be set in advance of
CPU set of WU flag.
Transmit Enable - set by HD6803 to produce
pream ble of nine consecutive I's and to enable
gating of transmitter output to Port 2, bit 4
regardless of the DDR value corresponding to this
bit; when clear, serial I/O has no effect on Port 2
bit 4.
TE set should be after at least one bit time of data
transmit rate from the set-up of transmit data
rate and mode.
Transmit Interrupt Enable - when set, will pennit
an IRQ2 interrupt to occur when bit 5 (TORE) is
set: when clear, the TDRE value is masked from
the bus.
Receiver Enable - when set, gates Port :2 bit 3 to
input of receiver regardless of DDR value for this
bit: when clear, serial I/O has no effect on Port 2
bit 3.
Receiver Interrupt Enable - when set, wiU permit
an IRQ2 interrupt to occur when bit 7 (RDRF) or
bit 6 (ORFE) is set; when clear, the interrupt is
masked.
Bit I TE
Bit :2 TIE
Bit 3 RE
Transmit/Receive Control and Status (TRCS) Register
TIle TRCS register consists of an 8-bit register of which all 8
bits may be read while only bits 0~4 may be written. The
register IS initialized to $20 by reset. The bits in the TRCS
register are defined as follows:
Bit 4 RIE
Transmit/Receive ContrOl and Status Register
7654321
IRDR~ORFEITDREI
RIE I
RE
I I I
TIE
TE
WU
\ADDR
$0011
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
121
H06803,H06803-1-------------------------------------------------------Bit 5 TORE Transmit Data Register Empty - set by hardware
when a transfer is made from the transmit data
register to the output shift register. The TDRE bit
is cleared by reading the status register, then
writing a new byte into the transmit data register,
TDRE is initialized to I by reset.
Bit 6 ORFE Over-Run-Framing Error - set by hardware when
an overrun or framing error occurs (receive only).
Rate and Mode Control Register
6
I
x
X
I
3
CC1
I
o
2
CCO
SS1
SSO
AD DR : $00'0
An overrun is defined as a new byte received with
last byte still in Data Register/Buffer. A framing
error has occured when the byte boundaries in bit
stream are not synchronized to bit counter. If
WU-f1ag is set, the ORFE bit will not be set. The
ORFE bit is cleard by reading the status register,
then reading the Receive Data Register, or by
reset.
Bit 7 RDRF Receiver Data Register Full-set by hardware when
a transfer from the input shift register to the
receiver data register is made. If WU-f1ag is set, the
RDRF bit will not be set. The RDRF bit is cleared
by reacting the status register, then reading the
Receive Data Register, or by reset.
Rate and Mode Control Register (RMCR)
The Rate and Mode Control register controls the following
serial I/O variables:
• Baud rate
• format
• clocking source,
• Port 2 bit 2 configuration
The register consists of 4 bits all of which are wri te-only and
cleared by reset. The 4 bits in the register may be considered as
a pair of 2-bit fields. The two low order bits control the bit rate
for Internal clocking and the remaining twq bits control the
format and clock select logic. The register definition is as
follows:
Bit 0 SSO} Speed Select - These bits select the Baud rate fo'r
Bit I SSl the internal clock. The four rates which may be
selected are a function of the CPU
CO
2
2
DO
3
2
EO
4
2
FO
4
3
Double Subtract
SUBD
83
4
3
93
5
2
A3
6
2
B3
6
3
Subtract
Arcumulators
SBA
Subtract.
With Carry
SBCA
82
2
2
92
3
2
A2
4
2
B2
4
3
A-M-C-+A
SBCB
C2
2
2
D2
3
2
E2
4
2
F2
4
3
B-M-C-+B
2
1
A-B-+A
Transfer
Accu'mulators
TAB
16
2
1
A-+B
TBA
17
2
1
B-+A
Test Zero or
Minus
TST
TSTA
4D
2
1
A - 00
TSTB
5D
2
1
B - 00
2
7D
6
Direct Ar1dressing
In direct addr('ssin~. the address of the operand is contained
in the second bvte of the instruction. Direct addressing allows
the user to dire~tly address the lowest 256 bytes in the machine
i.e .• locations zero through 255. Enhanced execution times are
achieved by storing data in these locations. In most configurations. it should be a random access memory. These are two-byte
instructions.
EX1.mded Addressing
In extended addressing, the address contained in the second
hvte of !he instruction i; used as the higher g-bits of the address
of the operand. The third hyte of the instruction is used as the
lower g-hits of the address for the operand, This is an absolute
"ddress in memory. These are three-byte inst ructions.
Indexed Addressing
In indexed addressing, the address contained in the second
hyte of the instruction 'is added to the index register's lowest
~
BO
A: B-M :M+l-+A: B
10
6
1__ 0
BQ
--
A .... M
B-+M+l
6D
II
B7
Y"ll II II I I f-oQ
b7
bO
B
A
B
bO
A~~ A7 A~~
M}
3
LSRA
Store Double
Accumulator
A
B
,A7
M -00
3
The Condition Corle Re!llster notes ilre listed after Table 10.
126
D-lllllillf-o
2
58
4
2
1
0
I N Z
V
C
·· ···
•
_
48
ASR
5
H
:<
ASLB
LSRB
Double Shift
Right l.ogical
IMPLIED
OP
ASLA
ASRB
Shift Right
Booleanl
Arithmetic Operation
·•
··• ··•
• •
·· ··
· ·•
·· ·
··
··· ···
·•
··· ···
·· ··
·· ··
3
t t ® t
t t ([I t
t t .&t
t t @ t
t t @
t t @
t t @
R t 19)
R t @
R t @
R
t
t
t
t
t
t
t @ t
t t
t t
R
t t
R
R
··
·
t t t t
t t t t
t t t I
t t t t
t
t
t
t
t t t t
t t R •
t t R
·
t
t
R R
t
t
R R
I
t
R R
8-bits in the CPU. The carry is then added to the higher
order 8-bits of the index register. This result is then used to
address memory, The modified address is held in a temporary
address register so there is no change to the index register. These
are two-byte instructions.
Implied Addressing
In the implied addressing mode the instruction gives the
address (i.e., stack pointer, index register, etc.), These are
one-byte instructions.
Relative Addressing
In relative addressing, the address contained in the second
byte of the instruction is added to the program counter's lowest
8-bits plus two. The carry or borrow is then added to the high
8-bits. This allows the user to address data within a range of
-126 to + 129 hytes of the present instruction. These are twobyte inst ructions.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------HD6803,HD6803-1
•
New Instructions
In addition to the existing 6800 Instruction Set, the following new instructions are
incorporated in the HD6803 Microcomputer.
Adds the 8·bit unsigned accumulator B to the 16·bit X·Register taking into account
the possible carry out of the low order byte of the X·Register.
ADDD Adds the double precision ACCD * to the double precision value M: M+ I and places
the results in ACCD.
ASlD Shifts all bits of ACCD one place to the left. Bit 0 is loaded with zero. The C bit is
loaded from the most significant bit of ACCD.
LDD
Loads the contents of double preciSion memory location into the double
accumulator A:B. The condition codes are set according to the data.
LSRD Shifts all bits of ACCD one place to the right. Bit 15 is loaded with zero. The C bit
is loaded from the least significant bit to ACCD.
MUL
Multiplies the 8 bits in accumulator A with the 8 bits in accumulator B to obtain a
16·bit unsigned number in A: B, ACCA contains MSB of result.
PSHX The contents of the index register is pushed onto the stack at the address contained
in the stack pointer. The stack pointer is decremented by 2.
PULX The index register is pulled from the stack beginning at the current address
contained in the stack pointer +1. The stack pointer is incremented by 2 in total.
STD
Stores the contents of double accumulator A:B in memory. The contents of ACCD
remain unchanged.
SUBD Subtracts the contents of M:M + I from the contents of double accumulator AB
and places the result in ACCD.
BRN
Never branches. If effect, this instruction can be considered a two byte NOP (No
operation) requiring three cycles for execution.
CPX
Internal processing modified to permit its use with any conditional branch in·
struction.
ABX
*ACCD' is the 16 bit register (A: B) formed by concatenating the A and B accumulators. The A-accumulator is the most significant byte.
Table 8 Index Register and Stack Manipulation Instructions
Condition Code
Register
Addressing Modes
Pointer Operations
Mnemonic
IMMED.
DIRECT
INDEX
EXTND
IMPLIED
OP
-
t
OP
- ..
OP
-
t
OP
-
:r
8C
4
3
9C
5
2
AC
6
2
BC
6
3
Boolean!
Arithmetic Operation
OP
-
t
09
3
1
X -1
SP - 1 ~ SP
X-M:M+l
Compare Index Reg
CPX
Decrement Index Reg
DEX
Decrement Stack Pntr
DES
34
3
1
Increment Index Reg
INX
08
3
1
X + 1~ X
Increment Stack Pntr
INS
31
3
1
SP + 1
~
~
Load Index Reg
LOX
CE
3
3
DE
4
2
EE
5
2
FE
5
3
M~XH.(M+l)-XL
LOS
8E
3
3
9E
4
2
AE
5
2
BE
5
3
M- SP H . (M+ll~SPL
Store Index Reg
STX
OF
4
2
EF
5
2
FF
5
3
XH ~ M. XL - (M + 1)
Store Stack Pntr
STS
9F
4
2
AF
5
2
BF
5
3
SP H ~ \1. SP L - (M + 11
Index Reg - Stack Pntr
TXS
35
Stack Pntr'''' Index Reg
TSX
Add
ABX
Push Data
PSHX
3
1
SP + 1 ~ X
3A
3
1
B +
3C
4
1
XL - Msp. SP - 1 -
X
SP
X H - Msp. SP - 1 - SP
-
Pull Data
X-I - SP
X~
PULX
38
5
1
N
2 1 0
Z V C
··· ··· ·· · ·· ··
··· ··· ·· · ·· ··
··· ···
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
· · · · ·i·
1
!
1
!
Load Stack Pntr
30
3
I
!
SP
1
4
!
X
3
5
H
SP + 1 - SP. Msp -
XH
SP + 1 - SP. Msp -
XL
(i) 1
R:.
• !J)
.(f)
!
R
t
R
• '0
t
R
The Condition Code Register notes are listed after Table 10.
'~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
127
H 0 6 8 0 3 , H 0 6 8 0 3 - 1 - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ __
Table 9 Jump and Branch Instructions
Condition Code
Register
Addressing Modes
Mnemonic
Operations
RELATIVE
OP
Branch Always
BRA
20
Branch Never
BRN
Branch If Carry Clear
BCC
Branch If Carry Set
Branch If = Zero
Branch If ;;. Zero
-
#
DIRECT
OP
-
#
INDEX
OP
-
#
OP
-
Branch Test
IMPLIED
EXTND
#
-
OP
#
2
21
3
2
None
24
3
2
C=O
BCS
25
3
2
BEQ
27
3
2
C =1
Z =1
BGE
2C
3
2
N
BGT
2E
3
2
Z + (N
Branch If Higher
BHI
22
3
2
C+Z=O
Branch If '" Zero
BlE
2F
3
2
Z + (N
Branch If lower Or
Same
BlS
23
3
2
C+Z=1
BlT
20
3
2
N
<±J
Branch If Minus
BMI
2B
3
2
N
z
Branch If Not Equal
Zero
BNE
26
3
2
Z=O
Branch If Overflow
Clear
BVC
28
3
2
V=O
Branch If Overflow Set
BVS
29
3
2
V =1
Branch If Plus
BPl
2A
3
2
N=O
80
6
2
Branch If
Branch If
>
Zero
< Zero
Branch To Subroutine
BSR
Jump
JMP
Jump To Subroutine
JSR
No Operation
NOP
01
2
Return From Interrupt
RTI
3B
10 1
Return From
Subroutine
RTS
39
5
Software Interrupt
SWI
3F
12 1
Wait for Interrupt
WAI
3E
9
6E
90
Tablel0
5
2
3
2
7E
3
3
AD 6
2
BD
6
3
1
<±J
<±J
V) = 0
V) = 1
V= 1
Clear Carry
1
V
Advances Prog. Cntr.
Only
OP
-
#
OC
2
1
•
•
•
•
•
Clear Interrupt Mask
CLI
OE
2
1
0-1
Clear Overflow
ClV
OA
2
1
O-V
Set Carry
SEC
oq
2
1
1 .... C
Set Interrupt Mask
SEI
OF
2
1
1 .... 1
Set Overflow
SEV
OB
2
1
l .... V
Accumulator A .... CCR
TAP
06
2
1
A .... CCR
CCR - Accumulator A
TPA
07
2
1
CCR-A
S
~
1
5
4
3
2
1
H
I
N
Z
V
0
C
·· · ·•• ·• ·• •
·· ·· • ·· ·• ·•
·· · ·· ·· ·
R
R
R
S
S
S
--~---
·····•
Condition Code Register Notes: (Bit set it test is true and cleared otherwise)
1 (Bit V)
(Bit C)
(Bit C)
(Bit V)
(Bit V)
(Bit V)
(Bit N)
(All)
(Bit I)
(All)
(Bit C)
128
•
•
•
•
· · ·
· ·· ··
·
·
·· ·• ·•• ·•• ·•• ·•
·• ·· · · · ··
·• · ·· ·· ·· ·•
· .· · ·
Condition Code Register
O-C
C
-@-
1
Boolean Operation
IMPLIED
0
•
•
•
•
•
•
•
•
Condition Code Register Manipulation Instructions
Mnemonic
ClC
2
N Z
·
1
~ddressingModes
Operations
3
I
·••
·
· · · · ••
•
·· ••
·· · ··
V =0
<±J
4
H
• • • •
• • •
•
• • •
• • • •
• • • •
• • •
• • •
•
• • • •
• • • •
• • •
• • • •
• •
• • •
• •
None
3
5
Test: Result = 10oo00oo?
Test: Result .. OOOOOOOO?
Test: Decimal value of most significant BCD Character greater than nine' (Not cleared if previously set)
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to result of N <±J C after shift has occurred.
Test: Result less than zero? (Bit 15 = 1)
load Condition Code Register from Stack. (See Special Operations)
Set when interrupt occurs. If previously set, a Non·Maskable Interrupt is required to exit the wait state.
Set according to the contents of Accumulator A.
Set equal to result of Bit 7 (ACCB)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435~8300
HD6803,HD6803-1
Table 11
ExACCX Immediate Direct tended
ABA
ABX
ADC
ADD
ADDD
AND
ASL
ASLD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BIT
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BSR
BVC
BVS
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS
Instruction Execution Times in Machine Cycle
ImIndexed plied
2
3
2
4
4
2
4
4
4
6
4
6
4
6
6
•
6
2
4
4
•
6
4
6
4
4
6
6
6
6
6
6
4
4
6
6
•
InExACCX Immediate Direct tended dexed
Relative
INX
JMP
JSR
LDA
LDD
LDS
LDX
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI
•
•
•
•
6
4
6
4
4
5
5
5
5
5
4
Relative
3
•
3
5
4
Implied
6
6
•
10
6
6
4
4
4
•
4
5
6
6
6
6
10
•
5
•
4
4
4
4
4
4
5
5
5
5
•
4
3
4
4
6
6
12
2
2
6
6
~HITACHI
Hitachi America Ltd_ • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
3
9
129
H06803,H06803-1---------------------------•
Summary of Cycle by Cycle Operation
control program is executed. The information is categorized in
groups according to addressing mode and number of cycles per
instruction. (In general. instructions with the same addressing
mode and number of cycles execute in the same manner: exceptions are indicated in the table).
Table 12 provides a detailed description of the information
present on the Address Bus. Data Bus, and the Read/Write line
(R/W) during each cycle for each instruction.
This information is useful in comparing actual with expected
results during debug of both software and hardware as the
Table 12 Cycle by Cycle Operation
Address Mode &
Instructions
Address Bus
Data Bus
IMMEDIATE
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
2
[
LOS
LOX
LOD
3
CPX
SUBD
ADDD
4
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Operand Data
1
2
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus F F F F
1
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address of Operand
1
1
1
Op Code
Address of Operand
Operand Data
Op Code Address
Op Code Address + 1
Destination Address
1
1
0
Op Code
Destination Address
Data from Accumulator
Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand + 1
1
1
0
0
Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus F F F F
1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1
1
1
1
0
0
Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
3
1
2
3
4
DIRECT
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
3
1
2
3
STA
3
LOS
LOX
LDD
4
STS
STX
STD
4
CPX
SUBD
ADDD
5
JSR
5
1
2
3
1
2
3
4
1
2
3
4
1
2
3
4
5
1
2
3
4
5
(Continued)
130
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
I
---------------------------------------------------------H06803,H06803-1
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
INDEXED
JMP
3
1
2
3
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
4
4
STA
1
2
3
4
1
2
3
4
LDS
LDX
LDD
LDD
5
STS
STX
STD
5
ASL
ASR
CLR
COM
DEC
INC
1
2
3
4
5
1
2
3
4
5
LSR
NEG
ROL
ROR
TST*
6
1
2
3
4
5
6
CPX
SUBD
ADDD
6
JSR
6
1
2
3
4
5
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
1
1
1
0
Op Code
Offset
Low Byte of Restart Vector
Operand Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
0
0
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset
0
Op Code
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Index Register + Offset + 1
Address Bus F F F F
1
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Stack Pointer
Stack Pointer - 1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
1
1
1
1
1
0
0
• In the TST Instruction, R/W line of the sixth cycle is "'" level, and AB = FFFF, DB = Low Byte of Reset Vector.
$HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
(Continued)
131
H06803,H06803-1-------------------------------------------------------Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
EXTENDED
JMP
3
1
2
3
AOC
AOD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
4
1
2
3
4
4
STA
1
2
3
4
LOS
LOX
LOD
5
STS
STX
STD
5
ASL
ASR
CLR
COM
DEC
INC
1
2
3
4
5
1
2
3
4
5
LSR
NEG
ROL
ROR
TST*
6
1
2
3
4
5
6
CPX
SUBD
ADDD
6
JSR
6
1
2
3
4
5
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
1
1
1
1
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data
Op Code
Op Code
Op Code
Operand
1
1
1
Address
Address + 1
Address + 2
Destination Address
0
Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
(High Ortier Byte)
(Low Order Byte)
Order Byte)
Order Byte)
0
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address Bus FFFF
Address of Operand
1
1
1
1
1
0
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF
1
1
1
1
1
1
Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
0
0
0
-
• In the TST instruction, R/W line of the sixth cycle is "'" level, and AB = FFFF, DB = Low Byte of Reset Vector.
132
(Continued)
~HITACHI
\ Hitachi America Ltd, • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------H06803,H06803-1
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
IMPLIED
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA
ABX
SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST
2
3
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Op Code of Next Instruction
1
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Irrelevant Data
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Irrelevant Data
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Previous Register Contents
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Stack Pointer
1
1
0
Op Code
Op Code of Next Instruction
Accumulator Data
Op Code Address
Op Code Address + 1
Stack Pointer
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Operand Data from Stack
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
0
0
Op Code
Irrelevant Data
Index Register (Low Order Byte)
Index Regl ster (H igh Order Byte)
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
1
1
1
1
1
5
Stack Pointer + 2
1
Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
Op Code
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(High Order Byte)
Address of Next Instruction
(Low Order Byte)
1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
2
3
ASLD
LSRD
3
DES
INS
3
INX
DEX
3
PSHA
PSHB
3
TSX
3
TXS
3
PULA
PULB
4
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
4
PSHX
4
1
2
3
4
PULX
5
1
2
3
4
5
RTS
5
1
2
3
WAI**
9
2
3
4
0
0
Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
(Cont Inued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
133
H06803,H06803-1-------------------------------------------------------Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Cycles
Cycle
:;=
10
10
Op Code Address
Op Code Address + 1
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus F F F F
1
1
1
1
1
1
1
1
1
1
Op Code
Irrelevant
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
5
Stack Pointer + 2
1
6
Stack Pointer + 3
1
7
Stack Pointer + 4
1
8
Stack Pointer + 5
1
9
Stack Pointer + 6
1
10
Stack Pointer + 7
1
OpCode
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instruction Address from
Stack (Low Order Byte)
10
11
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Stack Pointer - 7
Vector Address FFFA (Hex)
1
1
0
0
0
0
0
0
0
1
1
12
Vector Address FFFB (Hex)
1
1
2
3
4
5
6
7
8
9
RTI
SWI
10
12
1
2
3
4
5
6
7
8
9
"
Pointer
Pointer
Pointer
Pointer
Pointer
-
2
3
4
5
6
Data Bus
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
9
MUL
Stack
Stack
Stack
Stack
Stack
R/W
Line
0
0
0
0
0
5
6
7
8
WAI**
Address Bus
Data
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Op Code
Irrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
I rrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)
(Continued)
•• While the MPU is in the "Wait" state, its bus state will appear as a series of MPU reads of an address which IS seven locations less than the
original contents of the Stack Pointer. Contrary to the HD6800, none of the ports are driven to the high impedance state by a WAI
instruction.
134
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------------HD6803,HD6803-1
Table 12 Cycle by Cycle Operation (Continued)
RELATIVE
Address Mode &
Instructions
BCC
BCS
BEQ
BGE
BGT
BRN
BHT
BlE
BlS
Bl T
BMT
Cycle
Cycles
BNE
BPl
BRA
BVC
BVS
BSR
R/W
line
Address Bus
#
3
1
2
3
Op Code Address
Op Code Address + 1
Address Bus FFFF
6
1
2
3
4
Op Code Address
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
5
6
• Summary of Undefined Instruction Operations
The HD6803 has 36 underfined instructions. When these are
carried out, the contents of Register and Memory in MPU
change at random.
Data Bus
1
1
1
Op Code
Branch Offset
low Byte of Restart Vector
1
1
1
1
0
0
Op Code
Branch Offset
low Byte of Restart Vector
Op Code of Next Instruction
Return Address (low Order Byte)
Return Address (High Order Byte)
When the op codes (4E, SE) are used to execute. the MPU
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the
LSI.
Table 13 Op codes Map
HD6803 MICROPROCESSOR INSTRUCTIONS
ACC
A
OP
CODE
~
LO
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0000
-----
0001
0010
0011
1
2
3
BRA
TSX
CBA
BRN
INS
~
BHI
PULA (+1)
~
BLS
PULB (+1)
LSRD (+1) ~
ASLD (+1) ~
BCC
DES
NOP
-----
4
BCS
TXS
TAB
BNE
PSHA
0111
7
TPA
TBA
BEQ
PSHB
1000
S
INX (+1)
~
BVC
PULX (+2)
1001
9
OEX (+1)
OAA
BVS
RTS (+2)
1010
A
CLV
~
BPL
ABX
10.11
B
SEV
ABA
BMI
RTI (+7)
1100
C
CLC
~
BGE
PSHX (+1)
1101
0
SEC
BLT
MUL (+7)
1110
E
CLI
BGT
WAI (+6)
1111
F
SEI
~
BLE
SWI (+9)
1/2
1/2
2/3
1/3
BYTE/CYCLE
[NOTES]
/'
ACCA or SP
EXT
IMM
0110 0111
5
6
I DIR
liND
ACCB or X
I EXT
1000 110011101011011
7
S
I
9
I
A
I
NEG
TAP
/
----
0100 0101
SBA
0
ACC IND
B
-----
liND I EXT
B
C
I
D
rEI
F
0
CMP
1
SBC
2
SUBD (+2)
ADDD (+2)
3
4
LSR
AND
BIT
5
ROR
LOA
6
Ll
ASR
ASL
/1
STA
STA
EOR
7
S
ROL
ADC
9
DEC
ORA
A
BSR
(+4)
TST
---
.
JMP (-3)
CLR
1/2
2/6
B
ADD
INC
1/2
I DIR
1100111011111011111
SUB
COM
...--"
IMM
;
3/6
I
CPX (+2)
JSR (+2)
I;
(+1~
•
(+1~
STS (+1)
I 2/3 I
2/4
STO (+1)
LOX (+1)
LOS (+1)
(+1)1
2/2
LDO(+1)
I 3/4
2/2
STX (+1)
C
0
E
F
I 2/3 I 2/4 I 3/4
1) Undefined Op codes are marked with ~.
2)
) indicate that the number in parenthesis must be added to the cycle count for that instruction.
3) The instructions shown below are all 3 bytes and are marked with ......
Immediate addressing mode of SUBO. CPX. LDS. AOOO. LOD and LOX instructions. and undefined opcodes
(SF. CD. CF).
4) The Op codes (4E. 5E) are 1
byte/~
cycles instructions. and are marked with ......
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
135
:I:
o
0)
W
0-
00
o
~
:I:
o
0)
00
o
~
~
s-o
2:
»
3
~
o·
$l)
!:
P.
•
I\)
~
o
o
~
~~
~:I
.CD
-~
• :J>
(f)()
§
:I
c....
oen
CD
()
»
'SCI; TIE·TORE + RIE·(RORF + ORFE)
Condition Code Register
,
,
i
i. i
~
co
~
~
Vector
NMI
SWI
IRQ,
ICF
OCF
TOF
SCI
•
~
$
~
w
(J1
Co
w
A
o
o
Figure 16 Interrupt Flowchart
-+
PC
FFFC FFFO
FFFA FFFB
FFF8 FFF9
FFF6 FFF7
FFF4 FFF5
FFF2 FFF3
FFFO FFFl
Non·Maskable Interrupt
Software Interrupt
Maskable Interrupt Request 1
Input Capture Interrupt
Output Compare Interrupt
Timer Overflow Interrupt
SCI Interrupt (TORE + RORF + ORFE)
----------------------------H06803,H06803-1
Data Bus
Address Bus
Fi;lure 17 HD6803 MPU Expanded Multiplexed Bus
• Caution for the HD6803 Family SCI, TIMER Status Flag
The flags shown in Table 14 are cleared by reading/writing
(flag reset condition 2) the data register corresponding to each
flag after reading the status register (flag reset condition 1).
Table 14
Status Flag
To clear the flag correctly, take the following procedure:
1. Read the status register.
2. Test the flag.
3. Read the data register.
Status Flag Reset Conditions
Flag Reset Condition 1
(Status Register)
Flag Reset Condition 2
(Data Register)
ICR/Read
ICF
When each flag is "1",
TIMER
OCR/Write
OCF
TRCSR/Read
TC/Read
TOF
RDRF
When each flag is "1",
SCI
RDR/Read
ORFE
TRCSR/Read
TDRlWrite
TDRE
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
137
HD6805S1-------------MCU
(Microcomputer Unit)
The HD6805S1 is the 8-bit Microcomputer Unit (MCU)
which contains a CPU, on-chip clock,' ROM, RAM, I/O and
timer. It is designed for the user who needs an economical
microcomputer with the proven capabilities of the HD
6800-based instruction set.
The following are some of the hardware and software
highlights of the M CU.
•
HARDWARE FEATURES
•
8-Bit Architecture
•
•
64 Bytes of RAM
Memory Mapped I/O
•
•
•
1100 Bytes of User ROM
Internal 8-Bit Timer with l·Bit Prescaler
Vectored Interrupts - External and Timer
•
20 TTL/CMOS Compatible I/O Lines; FI Lines LED
HD6805S1P
(DP-28)
PIN ARRANGEMENT
•
~
Compatible
INT
•
On·Chip Clock Circuit
•
Self-Check Mode
EXTAL
• Master Reset
• Low Voltage Inhibit
• Easy for System Development and Debugging
•
A,
Vce
A.
A,
4
A.
NUM
A,
TIMER
5 Vdc Single Supply
A,
HD6805S1
A,
•
Compatible with MC6805P2
Co
•
SOFTWARE FEATURES
C,
A.
•
•
Similar to HD6800
Byte Efficient Instruction Set
C,
B,
C,
•
Easy to Program
B.
•
True Bit Manipulation
•
Bit Test and Branch Instructions
•
•
Versatile Interrupt Function
Powerful Indexed Addressing for Tables
•
Full Set of Conditional Branches
B,
B.
B,
B,
(Top View)
•
•
Memory Usable as Registers/Flags
•
•
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
•
•
All Addressing Modes Apply to ROM, RAM and I/O
Compatible with MC6805P2
BLOCK DIAGRAM
RES
TIMER
Accumulator
CPU
ConlrOI
Indelt
Reg , s1e'
POri
A
11O
Lines
A,
A,
A,
A,
A.
A,
A.
A,
Condition
Port
A
R.g
Cod.
Data
0"
5
Register
CC
Rog
Slack
POinter
SP
Program
Counter
"HuJh" PCH
Program
Counter
'Low"
peL
1100 .. 8
ROM
Sell check
ROM
138
B,
B,
B, POrt
B
B,
B. 11O
B, Lines
B.
B,
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
C,
C,
C,
C,
Port
C
11O
L,""
----------------------------------------------------------------HD680551
• ABSOLUTE MAXIMUM RATINGS
Vee *
Input Voltage (EXCEPT TIMER)
V in *
Input Voltage (TIMER)
•
Operating Temperature
T opr
Storage Temperature
T stg
Unit
Value
Symbol
Item
Supply Voltage
-0.3 - +7.0
V
-0.3 - +7.0
V
V
-0.3 - +12.0
o
°c
°c
-+70
-55-+150
With respect to Vss (SYSTEM GND)
(NOTE)
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (VCC=5.25V ± 0.5V, VSS=GND, Ta=o-+70°C, unless otherwise noted)
Item
Input "High" Voltage
Symbol
min typ
-
Vee
V
INT
3.0
-
Vee
V
V IH
2.0
-
Vee
V
Timer Mode
2.0
-
Vee
V
Self-Check Mode
9.0
-
11.0
V
-0.3
-
0.8
V
RES
INT
Input "Low" Voltage
EXTAL(Crystal Mode)
V IL
All Other
-0.3
-
0.8
V
-0.3
-
0.6
V
-0.3
-
0.8
-
700
4.75
V
-
V
Po
-
Low Voltage Recover
LVR
-
-
Low Voltage Inhibit
LVI
-
4.0
Power Dissipation
TIMER
INT
I nput Leak Current
max Unit
4.0
All Other
Input "High" Voltage(Timer)
Test Condition
RES
IlL
V in =0.4V-V ee
EXTAL(Crystal Mode)
V
mW
-20
-
20
IlA
-50
-
50
IlA
0
IlA
-1200 -
• AC CHARACTERISTICS (Vcc=5.25V ± 0.5V, Vss=GND, Ta=O - +70°C, unless otherwise noted.)
Item
Symbol
Test Condition
min
typ
max Unit
Clock Frequency
f cl
0.4
Cycle Time
t cve
1.0
-
Oscillation Frequency (External Resistor Mode)
f EXT
-
3.4
TNT Pulse Width
t lWL
t evc +
250
-
-
ns
RES Pulse Width
t RwL
t eve +
250
-
-
ns
TIMER Pulse Width
tTwL
t eve +
250
-
-
ns
Oscillation Start·up Time (Crystal Mode)
tose
C L=22pF±20%,
Rs=60D. max.
-
-
100
ms
Delay Time Reset
tRHL
External Cap. = 2.2 IlF
100
-
-
ms
-
-
30
pF
-
-
10
pF
Input Capacitance
I
I
XTAL
All Other
C in
R ep =15.0kSl±1%
Vin=OV
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
4.0
MHz
10
IlS
-
MHz
139
HD6805S1---------------------------------------------------------------• PORT ELECTRICAL CHARACTERISTICS (Vee
= S.2SV ± O.SV, Vss = GND, Ta = 0"" +70°C, unless otherwise noted.)
Port B
VOH
Port C
Port A and C
Output "Low" Voltage
VOL
Port B
Input "High" Voltage
Input "Low" Voltage
typ
max
Unit
3.S
-
V
2.4
-
2.4
-
1.S
-
-
Port A, B, C
2.4
-
Yin
IlL
Yin
V
0.4
V
1.0
V
V
-300
-
-
-0.3
Port B, C
V
0.4
Vee
V IL
= O.BV
= 2V
= O.4V"" Vee
V
V
-
2.0
Yin
V
-
VIH
Port A
Input Leak Current
min
= -lo~A
IOH = -100~A
IOH = -200~A
IOH = -1 mA
IOH = -100~A
IOL = 1.6 mA
IOL = 3.2 mA
IOL = 10mA
IOH
Port A
Output "High" Voltage
Test Condition
Symbol
Item
-SOO
20
O.B
V
-
~A
~A
20
~A
TTL Equiv. (Port A and C)
TTL Equiv. (Port B)
~
Vee
vee
~2.4kn.
1.2kn.
li=3.2mA
Ii = 1.6 mA ;>
Test Point
Test Point
(>
O-·~~1
=
Vi
Vi
40 pF
30 pF
12 kn.
24 kn.
-rrr
(NOTE)
1. Load capacitance includes the floating capacitance
2. All diodes are lS2074 C8> or equivalent.
of the probe and the jig etc.
Figure 1 Bus Timing Test Loads
•
•
SIGNAL DESCRIPTION
•
VCC and Vss
Power is supplied to the MCU using these two pins. VCC is
•
RES
•
NUM
+5.25 V ±O.s V. VSS is the ground connection.
•
TIMER·
This pin allows an external input to be used to decrement the
internal timer circuitry. Refer to TIMER for additional information about the timer circuitry.
The input and output signals for the MCU, shown in PIN
ARRANGEMENT, are described in the following paragraphs.
INT
This pin provides the capability for asynchronously applying
an external interrupt to the MCU. Refer to INTERRUPTS for
additional information.
•
XTAL and EXTAL
These pins provide connections for the on-chip clock circuit.
A crystal (AT cut, 4 MHz maximum), a resistor or an external
signal can be connected to these pins to provide a system clock
with various stability/cost tradeoffs. Refer to INTERNAL OSCILLATOR OPTIONS for recommendations about these inputs.
140
This.pin allows resetting of the MCU at times other than the
automatic resetting capability already in the MCU. Refer to
RESETS for additional information.
This pin is not for user application and should be connected
to Vss.
•
Input/Output Lines (Ao ,.., A 7 , 8 0
-
B7 , Co ,.., C 3 )
.These 20 lines are arranged into two 8-bit ports (A and B)
and one 4-bit port (C). All lines are programmable as either
inputs or outputs under software control of the Data Direction
Registers (DDR). Refer to INPUT/OUTPUT for additional
information.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------------------HD6805S1
• MEMORY
The MCU memory is configured as shown in Figure 2. During
the processing of an interrupt, the contents of the CPU registers
are pushed onto the stack in the order shown in Figure 3. Since
the stack pointer decrements during pushes, the low order byte
(PeL) of the program counter is stacked first; then the high
order three bits (PCH) are stacked. This ensures that the
program counter is loaded correctly as the stack pointer
increments when it pulls data from the stack: A subroutine call
will cause only the program counter (PCH, PeL) contents to be
pushed onto the stack.
Cau tion: - Self Test ROM Address Area
Self test ROM locations can not be used for a user program.
If the user's program is in this location, it will be removed when
manufacturing mask for production.
o
7
000
127
128
255
256
Not Used
ROM
(704 Bytes)
959
960
1923
1924
1
Port B
1
1
1
1
o
2
$000
$001
I
Port C
$002
~o
3
Not Used
$003
4
Port A DDR
$004*
$0 F
$100
5
Port B DDR
$005*
$783
$784
I
Not Used
$006*
Port C DDR
Not Used
$007
8
Timer Data Reg
$008
9
Timer CT R L Reg
$009
7
$3BF
$3CO
Self Check
ROM
(116 Bytes)
2039
2040
Port A
6
Main
ROM
(964 Bytes)
3
4
0
2
$07F
Page Zero
ROM
(128 Bytes)
5
6
$000
I/O Ports
Timer
RAM
(128 Bytes)
$OOA
10
Not Used (54 Bytes)
$7F7
$7F8
Interrupt
Vectors
ROM
(8 Bytes)
63
64
12~
$07F
*Write-only registers
$7FF
2047
$03F
$040
RAM (64 Bytes)
Stack
t
Figure 2 MCU Memory Configuration
6
n-4
1
5
1
4
11
Pu II
Condition
Code Register
Accumulator
0
X
n+2
Accumu lator
n-3
A
n +1
n-2
n-1
n+3
Index Register
1
1
1
1
1\
PCH*
PC
10
n+4
1
PCl'
0
I
I
I
Index Register
0
10
1
n+5
0
1
0
1 11
I
5 4
11
Program Counter
0
SP
Stack Pointer
Condition Code Register
Push
* For subroutine calls, only PCH and PCL are stacked
Carry/Borrow
Figure 3 Interrupt Stacking Order
Zero
Negative
Interrupt Mask
Half Carry
Figure 4 Programming Model
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
141
HD6805S1-------------------------------------------------------------•
REGISTERS
The CPU has five registers available to the programmer.
They are shown in Figure 4 and are explained in the following
paragraphs.
• Accumulator (A)
The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.
• Index Register (X)
The index register is an 8-bit register used for the indexed
addressing mode. It contains an 8-bit address that may be added
to an offset value to create an effective address. The index
register can also be used for lim ited calculations and data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
• Program Counter (PC)
The program counter is an II-bit register that contains the
address of the next instruction to be executed.
• Stack Pointer (SP)
The stack pointer is an II-bit register that contains the
address of the next free location on the stack. Initially, the
stack pointer is set to location $07F and is decremented as data
is being pushed onto the stack and incremented as data is being
pulled from the stack. The six most significant bits of the stack
pointer are permanently set to 000011. During a MCU reset or
the reset stack pointer (RSP) instruction, the stack pointer is set
to location $07F. Subroutines and interrupts may be nested
down to location $061 which allows the programmer to use up
to 15 levels of subroutine calls.
• Condition Code Register (CC)
The condition code register is a 5-bit register in which each
bit is used to indicate or flag the results of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each
individual condition code register bit is explained in the
follOWing paragraphs.
Half Carry (H)
Used during arithmetic operations (ADD and ADC) to
indicate that a carry occurred between bits 3 and 4.
I nterrupt (I)
This bit is set to mask the timer and external interrupt (I NT).
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.
Negative (N)
Used to indicate that the result of the last arithmetic, logical
or data manipulation was negative (bit 7 in result equal to a
logical one).
I
Zero (Z)
Used to indicate that the result of the last arithmetic, logical
or data manipulation was zero.
Carry/Borrow (C)
Used to indicate that a carry or borrow out of the arithmetic
logic unit (ALU) occurred during the last arithmetic operation.
This bit is also affected during bit test and branch instructions,
shifts, and rotates.
• TIMER
The MCU timer circuitry is shown in Figure 5. The 8-bit
counter, the Timer Data Register (TDR), is loaded under program control and counts down toward zero as soon as the clock
input is applied. When the timer reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register (TCR) is
set. the CPU responds to this interrupt by saving the present
CPU state on the stack, fetching the timer interrupt vector from
locations $7F8 and $7F9 and executing the interrupt routine.
The timer interrupt can be masked by setting the timer interrupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in the
Condition Code Register also prevents a time interrupt from
being processed.
The clock input to the timer can be from an external source
applied to the TIMER input pin or it can be the internal rp2
signal. When the internal rp2 signal is selected as the input
source, the node a is connected to b (see Fig. 5).
In case of the external source, the node b connects with c.
.------
_._.-
--
----
x
BRCLR
x
.-
---~-
--~-~--
x
BSET
x
BSR
CLC
x
CLI
x
x
._------+
x
x
x
x
x
x
x
x
x
x
x
JMP
x
JSR
x
x
x
x
x
x
CPX
x
EaR
x
LDA
x
LDX
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
- - ~-
x
x
x
x
x
x
x
x
CMP
INC
x
>.----
BRSET
DEC
•
•
•
x
x
BRA
BRN
COM
•
-~r----.
BPL
CLR
•
•
••
•
•
•
•
x
x
BCC
x
x
x
x
x
x
x
x
x
x
x
x
--I------
x
x
x
x
x
x
x
x
x
x
x
x
x
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
I
N
Z
• II II
• II II
• II II
• II II
• II II
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• II II
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
a • •
C
II
II
•
II
II
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
II
II
•
•
a
•
•
• a
1
II
II
II
II
II
1
•
•
• II II II
• II II •
• II II •
• II 1\ •
• • • •
• • • •
• II II •
• 1\ II •
(to be continued)
C
1\
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
155
HD6805S1-----------------------------------------------------------------Table 7 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
LSL
x
x
LSR
x
x
NEG
x
x
NOP
x
x
ROL
x
x
x
ROR
x
x
RSP
x
RT!
x
RTS
x
ORA
x
SBC
SEC
SEI
x
Relative
x
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
STA
x
x
x
x
x
x
x
x
x
x
STX
x
x
x
x
x
SWI
Bit
Setl
Clear
x
x
x
SUB
x
x
x
TAX
x
TST
x
TXA
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
I nterrupt Mask
N
Negative (Sign Bit)
Z
Zero
156
Direct
Extended
x
C
1\
Bit
Test &
Branch
I
N
• •
• •
1\
1\
1\
0
1\
1\
H
Z
C
•
•
•
•
•
•
• 1\ 1\ 1\
• • • •
• 1\ 1\ •
• 1\ 1\ 1\
•
1\
?
?
?
1\
1\
• • • •
?
?
• • • • •
• • 1\ 1\ 1\
• • • • 1
• 1 • • •
• • 1\ 1\ •
• • 1\ 1\ •
• • 1\ 1\ 1\
• 1 • • •
• • • • •
• • 1\ 1\ •
• • • • •
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD6805S1
Table 8
Bit Manipulation
Opcode Map
Read/Modify NJ rite
Branch
Test &
Branch
Set/
Clear
Rei
DIR
0
1
2
3
0
BRSETO
BSETO
BRA
I
A
I
4
I
X
I
5
I
,X1
I
6
Control
I
IMP
IMP
IMM
I
DIR
I
7
8
9
A
RTI*
-
I
B
NEG
1
BRCLRO
BClRO
BRN
-
2
BRSET1
BSET1
BHI
-
Register/Memory
,XO
RTS*
-
3
BRCLR1
BClR1
BlS
COM
4
BRSET2
BSET2
BCC
lSR
SWI*
-
I EXT I
I
C
I
,X2
I
,X1
I
,XO
D
I
E
I
F
SUB
<--
HIGH
0
-
CMP
1
-
SSC
2
-
CPX
3
l
-
AND
4
a
5
BRClR2
BClR2
BCS
-
-
-
BIT
5 W
6
BRSET3
BSET3
BNE
ROR
-
-
LDA
6
7
BAClA3
BClR3
BEQ
ASA
-
TAX
8
BASET4
BSET4
BHCC
lSLlASl
-
ClC
-
I
STA(+1)
7
EOR
8
9
BAClR4
BClR4
BHCS
ROl
-
SEC
ADC
9
A
BASET5
BSET5
BPl
DEC
-
CLI
ORA
A
B
BACLR5
BClR5
BMI
-
-
SEI
C
BASET6
BSET6
BMC
INC
-
ASP
0
BAClA6
BClR6
BMS
TST
-
Nap
E
BASET7
BSET7
Bil
-
-
F
BACLA7
BClR7
BIH
ClR
-
3/10
(NOTE)
2/7
2/4
2/6
I
1/4
I
1/4
I
2/7
I
1/6
1/*
I
BSR* I
-
TXA
1/2
-
2/2
I
I
2/4
I
3/5
I
ADD
B
JMP(-1)
C
JSR(+3)
0
lDX
E
STX(+1)
F
3/6
I
2/5
I
1/4
1. Undefine.d opcodes are marked with "_".
2. The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles).
Mnemonics followed by a "." require a different number of cycles as follows:
RTI
9
RTS
6
SWI
11
BSR
8
3. (
indicate that the number in parenthesis must be added to the cycle count for that instruction.
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
157
HD6805S6-------------MCU (Microcomputer
Unit)
The HD680SS6 is the 8-bit Microcomputer Unit (MCU)
which contains a CPU, on-chip clock, ROM, RAM, I/O and
timer. It is designed for the user who needs an economical
microcomputer with the proven capabilities of the HD
6800-based instruction set.
The foUowing are some of the hardware and software
highlights of the M CU.
• HARDWARE FEATURES
• B-Bit Architecture
• 64 Bytes of RAM
• Memory Mapped I/O
• 1804 Bytes of User ROM
• Internal B-Bit Timer with 7-Bit Prescaler
•
HD6805S6P
(DP·28)
•
20 TTL/CMOS Compatible I/O Lines;
8 Lines LED Compatible
•
On-Chip Clock Circuit
•
•
•
•
Self-Check Mode
Master Reset
Low Voltage Inhibit
Easy for System Development and Debugging
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
5 Vdc Single Supply
Compatible with MC6805P6
SOFTWARE FEATURES
Similar to HD6800
Byte E~icient Instruction Set
Easy to 'Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Function
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible with MC6805P6
PIN ARRANGEMENT
A,
A,
A,
A.
A,
A,
A.
B,
C,
B,
B.
B,
B,
B.
B,
B,
(Top View)
•
BLOCK DIAGRAM
TIMER
B.
Accumulator
A
CPu
Control
A,
A,
POrt
A,
A
110
A,
A,
Line"
AI
Condition
Port
Data
A
Reg
Olr
Reg
~
5
Register CC
CPU
Stack
A.
A,
5
Pomter
SP
Program
Counter
3
.. H ..... PCH
ALU
Program
Counter
"Low" pel
18()11xB
ROM
",xl
Self check
ROM
158
8,
8, Pan
8
8,
8, I/O
8, L' ....
8,
8,
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
C. Po ..
C,
C
C, 1/0
C. L, ....
HD6805S6
• ABSOLUTE MAXIMUM RATINGS
Item
Input Voltage (EXCEPT TIMER)
Input Voltage (TIMER)
•
Value
Symbol
Supply Voltage
Unit
Vee *
-0.3 - +7.0
V in *
-0.3 - +7.0
V
-0.3 -+12.0
V
°c
°c
Operating Temperature
T opr
o -+70
Storage Temperature
T stg
- 55 - +150
V
With respect to Vss (SYSTEM GND)
(NOTE)
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation shouid be under
recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc=5.25V ± O.5V. Vss=GND. Ta=Q-+70°C. unless otherwise noted.)
Item
Input "High" Voltage
Symbol
min typ
-
Vee
V
INT
3.0
-
Vee
V
V IH
2.0
-
Vee
V
Timer Mode
2.0
-
Vee
V
Self-Check Mode
9.0
-
11.0
V
-0.3
-
0.8
V
RES
INT
Input "Low" Voltage
max Unit
4.0
All Other
Input "High" Voltage (Timer)
Test Condition
RES
EXTAL(Crystal Mode)
V IL
All Other
-0.3
-
0.8
V
-0.3
-
0.6
V
-0.3
-
0.8
-
700
V
Po
-
Low Voltage Recover
LVR
-
-
4.75
V
Low Voltage Inhibit
LVI
-
4.0
-
V
-20
-
20
J.l.A
-50
-
50
J.l.A
0
J.l.A
Power Dissipation
TIMER
INT
I nput Leak Current
IlL
V in =O.4V-V ee
-1200 -
EXTAL(Crystal Mode)
mW
• AC CHARACTERISTICS (Vcc=5.25V ± O.5V. Vss=GND. Ta=O - +70°C. unless otherwise noted.)
Item
Symbol
min
Test Condition
typ
max Unit
Clock Frequency
f cl
0.4
-
4.0
Cycle Time
tcyc
1.0
-
10
J.l.s
Oscillation Frequency (External Resistor Mode)
fEXT
3.4
-
MHz
TNT Pulse Width
t lWL
-
-
ns
-
-
ns
t Cyc +
250
-
-
ns
-
-
100
ms
100
-
-
ms
-
-
-
-
35
10
pF
RES Pulse Width
tRWL
TIMER Pulse Width
t TWL
Oscillation Start-up Time (Crystal Mode)
Delay Time Reset
I nput Capacitance
tose
tRHL
I
XTAL
I
All Other
C ,n
-
Rep=15.0k~al%
tCYC t
250
tcyc t
250
C L=22pF±20%,
Rs=60Q max.
External Cap. = 2.2 J.l.F
Vin=OV
i
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
MHz
pF
159
HD6805S6
_ PORT ELECTRICAL CHARACTERISTICS (Vee = 5.25V
Output "Low" Voltage
typ
max
Unit
3.5
-
-
V
IOH = -100~A
2.4
2.4
IOH = -1 mA
1.5
-
V
IOH = -200~A
-
V
Port C
IOH = -100~A
2.4
V
IOL = 1.6 mA
-
-
-
Port A and C
0.4
V
-
0.4
V
-
1.0
V
-
Vee
V
O.S
V
Port B
VOH
VOL
Port B
IOL = 3.2 mA
VIH
2.0
VIL
-0.3
Port A, B, C
Port A
Input Leak Current
Test Condition
IOL = 10mA
Input "High" Voltage
Input "Low" Voltage
=GND, Ta =0 -- +70°C, unless otherwise noted)
min
Symbol
PortA
Output "High" Voltage
± 0.5V, Vss
IOH =-10~A
Item
IlL
Port B, C
Yin = O.SV
-500
~A
-300
-
-
Yin = 2V
-
~A
Yin = O.4V"" Vee
- 20
-
20
~A
TTL Equiv. (port B)
TTL Equiv. (Port A and C)
Vee
Vee
li=3.2mA
Test Point
40pF
V
1.2kn
Ii = 1.6
Test Point
30 pF
12 kn
mA
2.4kn
24 kn
(NOTE) 1. Load capacitance includes the floating capacitance of the probe and the jig etc.
2. All diodes are 152074 (£!l or equivalent.
Figure 1 Bus Timing Test Loads
• SIGNAL DESCRIPTION
- TIMER
The input and output signals for the MCU, shown in PIN
ARRANGEMENT, are described in the following paragraphs.
This pin allows an external input to be used to decrement
the internal timer circuitry. Refer to TIMER for additional
information about the timer circuitry.
- VCC and VSS
Power is supplied to the MCU using these two pins. VCC is
+5.25 V ± 0.5 V. VSS is the ground connection.
-INT
This pin provides the capability for asynchronously appiying
an external interrupt to the MCU. Refer to INTERRUPTS for
additional information.
- XTAL and EXTAL
These pins provide connections for the on-chip clock circuit.
A crystal (AT cut, 4 MHz maximum), a resistor or an external
signal can be connected to these pins to provide a system clock
with various stability/cost tradeoffs. Refer to INTERNAL
OSCILLATOR OPTIONS for recommendations about these
inputs.
160
- RES
This pin allows resetting of the MCU at times other than the
automatic resetting capability already in the MCU. Refer to
RESETS for additional information.
-NUM
This pin is' not tor user application and should be connected
to VSS.
_ Input/Output Lines (Ao ,." A7, Bo ,." 87, Co ,." C3)
These 20 lines are arranged into two 8-bit ports (A and B)
and one 4-bit port (C). All lines are programmable as either
inputs or outputs under software control of the data direction
registers. Refer to INPUT/OUTPUT for' additional information.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300 .
HD6805S6
• MEMORY
order three bits (PCH) are stacked. This ensures that the
program counter is loaded correctly as the stack pointer
increments when it pulls data from the stack: A subroutine call
will cause only the program counter (pCH, PeL) contents to be
pushed onto the stack.
The MCU memory is configured as shown in Figure 2. During
the processing of an interrupt, the contents of the CPU registers
are pushed onto the stack in the order shown in Figure 3. Since
the stack pointer decrements during pushes, the low order byte
(PCL) of the program counter is stacked first; then the high
Cau tion: - Self Test ROM Address Area
Self test ROM locations can not be used for a user program.
If the user's program is in this location, it will be removed when
manufacturing mask for production.
o
7
000
7
$000
I/O Ports
Timer
RAM
(128 Bytes)
127
128
1\80
Page Zero
ROM
(128 Bytes)
255
256
Port B
$OFF
$100
Self Check
ROM
(116 Bytes)
2039
2040
1
$001
I
$002
PortC
3
Not Used
$003
Port A DDR
$004*
5
Main
ROM
(1668 Bytes)
$783
$784
1
4
Port B DDR
$005*
I
$006*
Not Used
6
1923
1924
1
0
$000
1
1
2
3
Port A
2
$07F
4
5
6
0
Port C DDR
7
Not Used
$007
8
Timer Data Reg
$008
9
Timer CTR L Reg
$009
$OOA
10
Not Used (54 Bytes)
$7F7
$7F8
Interrupt
Vectors
ROM
(8 Bytes)
63
64
12~
$07F
t
*Write-only registers
$7FF
2047
$03F
$040
RAM (64 Bytes)
Stack (31 Bytes Maximum)
Figure 2 MCU Memory Configuration
6
n-4
1
5
1 1\
Condition
Code Register
n-3
Accumulator
n-2
Index Register
n-1
0
4
o
1 Accumulator
Pull
L..._ _ _ _ _A
_ _ _ _....
n+l
o
L..._ _ _ _ _X_ _ _ _....llndex
n+2
10
1 1 1 1 11
peL"
I
I
n+3
PCH*
8 7
PCH
10
n+4
0 1 0 1 0 10 1
Register
0
I Program Counter
PCL
5 4
111
1
0
SP
1 Stack Pointer
n+5
Condition Code Register
Push
* For subroutine calls, only PCH and PCL are stacked.
Carry/Borrow
Figure 3 Interrupt Stacking Order
Zero
Negative
Interrupt Mask
Half Carry
Figure 4 Programming Model
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
161
HD6805S6---------------------------------------------------------------•
REGISTERS
The CPU has five registers available to the programmer.
They are shown in Figure 4 and are explained in the following
paragraphs.
• Accumulator (A)
The accumulator is a general purpose 8-bit register used to
hold op~rands and results of arithmetic calculations or data
manipulations.
• Index Register (X)
The index register is an 8-bit register used for the indexed
addressing mode. It contains an 8-bit address that may be added
to an offset value to create an effective address. The index
register can also be used for lim ited calculations and data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
• Program Counter (PC)
The program counter is an II-bit register that contains the
address of the next instruction to be executed.
• Stack Pointer (SP)
The stack pointer is an II-bit register that contains the
address of the next free location on the stack. Initially, the
stack pointer is set to location $07F and is decremented as data
is being pushed onto the stack and incremented as data is being
pulled from the stack. The six most significant bits of the stack
pointer are permanently set to 000011. During a MCU reset or
the reset stack pointer (RSP) instruction, the stack pointer is set
to location $07F. Subroutines and interrupts may be nested
down to location $061 which allows the programmer to use up
to 15 levels of subroutine calls.
• Condition Code Register (CC)
The condition code register is a 5-bit register in which each
bit is used to indicate or flag the results of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each
individual condition code register bit is explained in the
following paragraphs.
Half Carry (H)
Used during arithmetic operations (ADD and ADC) to
indicate that a carry occurred between bits 3 and 4.
I nterru pt (I)
This bit is set to mask the timer and external interrupt (INT).
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.
Negative (N)
Used to indicate that the result of the last arithmetic, logical
or data manipulation was negative (bit 7 in result equal to a
logical one).
Zero (Z)
Used to indicate that the result of the last arithmetic, logical
or data manipulation was zero.
Carry/Borrow (C)
Used to indicate that a carry or borrow out of the arithmetic
logic unit (ALU) occurred during the last arithmetic operation.
This bit is also affected during bit test and branch instructions,
shifts, and rotates.
•
TIMER
The MCU timer circuitry is shown in Figure 5. The 8-bit
counter, the Timer Data Register (TOR), is loaded under program control and counts down toward zero as soon as the clock
input is applied. When the timer reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register (TCR), is
set. The CPU responds to this interrupt by saving the present
CPU state on the stack, fetching the timer interrupt vector from
locations $7F8 and $7F9 and executing the interrupt routine.
The timer interrupt can be masked by setting the timer interrupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in the
Condition Code Register also prevents a timer interrupt from
being processed.
The clock input to the timer can be from an external source
applied to the TIMER input pin or it can be the internal 1/>2
signal. When the internal ¢!2 signal is selected as the input
source, the node a is connected to b (see Fig. 5).
<1>2
(Internal)
TI R; Timer Interrupt Request
TIM; Timer Interrupt Mask
,.
I
Timer
Input
Pin
I
I
r-----'
I
I
I
I
I
I
_____ .JI
IL
L,---;-i-i -i-i--&- r-J
,
TIR TIM
Clock
Input
NOT USED
Manufactu ring
'I.1ask Options
Write
Read
Write
Read
Figure 5 Timer Block Diagram
162
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------------------HD6805S6
In case of the external source, the node b connects with c.
When the q)2 signal is used as the source, the clock signal is input
to the prescaler while the TIMER input is "High".
The source of the clock input is one of the options that has
to be specified before manufacture of the MCU. A prescaler option can be applied to the clock input that extends the timing
interval up to a maximum of 128 counts before decrementing
the counter (TDR). The timer continues to count past zero, falling through to $FF from zero, and then continuing the count.
Thus, the counter can be read at any time by reading the TDR.
This allows a program to determine the length of time since a
timer interrupt has occurred and not disturb the counting process.
At power-up or reset, the prescaler and counter are initialized
with all logical ones; the timer interrupt request bit (bit 7) is
cleared, and the timer interrupt mask bit (bit 6) is set.
(NOTE) If the MCU Timer is not used, the TIMER input pin
must be grounded.
2
'---
• SELF CHECK
The self-check capability of the MCU provides an internal
check to determine if the part is functional. Connect the MCU
as shown in Figure 6 and monitor the output of port C bit 3
for an oscillation of approximately 3Hz. ROM, RAM, TIMER,
Interrupts, I/O of Port A, Band C are checked by this capability.
• RESETS
The MCU can be reset three ways: by initial power-up, by
the external reset input (RES) and by an optional internal low
voltage detect circuit, see Figure 7. All the I/O port are initialized to Input mode (DDR's are cleared) during RESET.
During power-up, a minimum of 100 milliseconds is needed
before allowing the RES input to go "High".
This time allows the internal crystal oscillator to stabilize.
Connecting a capacitor to the RES input, as shown in Figure 8,
typically provides sufficient delay.
A, 27
INT
A, 26
28
-
RES
As 25
XTAL
A, 23
:::;:: 2.21' F
-Trr
A'2i--
C
A, 22
A, 21
EXTAL
+9V
7
~
V ee
330
n
JooA
13fff
r.:;
'C Q
J~O n r.:.'!01
330n
Y;;\f
~~
~
Ao~
TIMER
HD6805S6
(Resistor option)'
B,~
NUM
B,
18
Bs
17
B, 16
8
Co
B,~
9
C,
B,
14
10 C,
B,
13
11 C,
B" 12
V ee = Pin 3
V Ss =Pin1
• Refer to Figure 9
about crystal option
Figure 6 Self Check Connections
Vee
OV----------------J
RES
Pin
-----------------------~
Internal
Reset
Figure 7 Power Up and RES Timing
$
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
163
HD6805S6-------------------------------------------------------------• INTERNAL OSCILLATOR OPTIONS
The internal oscillator circuit is designed to require a minimum of external components. A crystal, a resistor, a jumper
wire, or an external signal may be used to generate a system
clock with various stability/cost tradeoff. A manufacturing
mask option is required to select either the crystal oscillator
or the RC oscillator circuit. The different connection methods
are shown in Figure 9. Crystal specifications are given in Figure
10. A resistor selection graph is given in Figure II.
Part of
HD6805S6
MCU
Figure 8 Power Up Reset Delay Circuit
5 XTAL
5 XTAL
M HZ
4 ma x
c=J
4
EXTAL
HD6805S6
MCU
4 EXTAL
HD6805S6
MCU
22 P F±20%=;:t:;:
Crystal
Approximately 25% Accuracy
tcyc = 1.25 IlS typo
External Jumper
Vee
XTAL
~"\.,,
XTAL
r----I
R
External
Clock
Input
4 EXTAL
HD6805S6
MCU
4
EXTAL
HD6805S6
MCU
No
Connection
External Clock
Approximately 15% Accuracy
External Resistor
CRYSTAL OPTIONS
RESISTOR OPTIONS
Figure 9 Internal Oscillator Options
C,
XTAL~~
5
~~
\
EXTAL
4
I -'-
\
4
Vee = 5.25V
TA = 25°C -
1\
>
'"" ""
u
c
Q)
:l
AT Co =
f = 4
RS =
Cut Parallel Resonance Crystal
7 pF max.
MHz (C, =22pF±20%)
60n max.
~
u..
Figure 10 Crystal Parameters
o
10
15
"" --
20
25
30
Resistance (kn)
.............
..............
35
40
45
Figure 11 Typical Resistor Selection Graph
164
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
50
----------------------------------------------------------------HD6805S6
1-1
$7F -SP
o -DDR's
CLR iN'f Logic
$FF - TOR
$7F _ Prescaler
$7F _ TCR
Y
INT
Y
TIMER
Stack
PC, X, A, CC
Load PC From
Reset:$7FE,$7FF
Load PC From
SWI: $7FC,$7FD
INT: $7FA, $7FB
TIMER: $7F8,$7F9
Fetch
Instruction
SWI
Y
Execute
Instruction
Figure 12 Interrupt Processing Flowchart
Data
Direction
Register
Bit
Output
Data Bit
o
Output
State
Input to
MCU
o
o
3·State
Pin
1
Figure 13 Typical Port I/O Circuitry
o
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
165
HD6805S6----------------------------------------------------------------•
•
INTERRUPTS
The CPU can be interrupted three different ways: through
the external interrupt (INT) input pin, the internal timer
interrupt request, and a software interrupt instruction (SWI).
When any interrupt occurs, processing is suspended, the present
CPU state is pushed onto the stack, the interrupt bit (I) in the
Condition Code Register is set, the address of the interrupt
routine is obtained from the appropriate interrupt vector
address, and the interrupt routine is executed. Stacking the
CPU registers, setting the I bit, and vector fetching requires
11 cycles. The interrupt service routines normally end with a
return from interrupt (RT!) instruction which allows the CPU
to resume processing of the program prior to the interrupt.
Table 1 provides a listing of the· interrupts, their priority, and
the vector address that contain-the starting address of the appropriate interrupt routine.
A flowchart of the interrupt processing sequence is given in
Figure 12.
Table 1 Interrupt Priorities
Vector Address
Priority
Interrupt
$7FE and $7FF
$7FC and $7FD
$7FA and $7FB
$7F8 and $7F9
RES
SWI
2
INT
TIMER
4
3
Port A
INPUT/OUTPUT
There are 20 input/output pins. All pins are programmable
as either inputs or outputs under software control of the corresponding data direction register (DDR). When programmed as
outputs, the latched output data is readable as input data,
regardless of the logic levels at the output pin due to output
loading (see Figure 13). When port B is programmed for outpu ts, it is capable of sinking 10 rnA on each pin (VOL = 1V
max). All input/output lines are TTL compatible as both inputs
and outputs. Port A are CMOS compatible as outputs, and
Port Band C are CMOS compatible as inputs. Figure 14 provides some examples of port connections.
•
BIT MANIPULATION
The MCU has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 15
illustrates the usefulness of the bit manipulation and test
instructions. Assume that bit 0 of port A is connected to a zero
crossing detector circuit and that bit 1 of port A is connected to
the trigger of a TRIAC which powers the controlled hardware.
This program, which uses only seven ROM locations,
provides turn-on of the TRIAC within 14 microseconds of the
zero crossing. The timer could also be incorporated to provide
turn-on at some later time which would pennit pulse-width
modulation of the controlled power.
Port B
Port A Programmed as output(s), driving CMOS and TTL Load directly.
Port B Programmed as output(sl. driving Darlington base directly.
(a)
(b)
+v
+v
R
Port B
CMOS Inverter
Port C
C3
Port B Programmed as output(s), driving LED(s) directly.
(c)
Port C Programmed as output(s), driving CMOS loads, using external
pull-up resistors.
(d)
Figure 14 Typical Port Connections
166
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------------HD6805S6
•
SELF 1
Bit Set/Clear
Refer to Figure 23. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.
BRClR 0, PORT A, SELF 1
BSET 1, PORT A
BClR 1, PORT A
•
Bit Test and Branch
The CPU has ten addressing modes available for use by the
programmer. They are explained and illustrated briefly in the
following paragraphs.
Refer to Figure 24. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
($OO-$FF) and branch to any location relative to the PC. The
byte to be tested is addressed by the byte following the opcode.
The individual bit within that byte to be tested is addressed by
the lower three bits of the opcode. The third byte is the relative
address to be added to the program counter if the branch condition is met. These instructions are three bytes long. The value of
the bit tested is written to the carry bit in the condition code
register.
•
•
Figure 15 Bit Manipulation Example
• ADDRESSING MODES
Immediate
Refer to Figure 16. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
•
Direct
Refer to Figure 17. In direct addressing, the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.
•
Extended
Refer to Figure 18. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instructions are three bytes long.
•
Relative
Refer to Figure 19. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA=(pC)+2+Rel. Rei is the contents
of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to somewhere within the
range of + 129 bytes to -127 of the present instruction. These
instructions are two bytes long.
•
Indexed (No Offset)
Refer to Figure 20. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and "their EA is the contents of the index register.
•
Indexed (8-bit Offset)
•
•
Register/Memory Instructions
Most of these instructions use two operands. One operand is
either the accumulator or the index register. The other operand
is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR)
instructions have no register operand. Refer to Table 2.
•
Read/Modify/Write Instructions
These instructions read a memory location or a register,
modify or test its contents, and write the modified value back
to memory or to the register. The test for negative or zero
(TST) instruction is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
3.
•
Branch Instructions
The branch instructions cause a branch from the program
when a certain condition is met. Refer to Table 4.
•
Bit Manipulation Instructions
These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 5.
•
•
•
Indexed (16-bit Offset)
INSTRUCTION SET
The MCV has a set of 59 basic instructions. They can be
divided into five different types: register/memory, read/modify/
write, branch, bit manipulation, and control. The following
paragraphs briefly explain each type. All the instructions within
a given type are presented in individual tables.
Refer to Figure 21. The EA is calculated by adding the
contents of the byte following the opcode to the contents of
the index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.
Refer to Figure 22. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.
Implied
Refer to Figure 25. The implied mode of addressing has no
EA. All the information necessary to execute an instruction is
contained in the opcode. Direct operations on the accumulator
and the index register are included in this mode of addreSSing.
In addition, control instructions such as SWI, RTI belong to this
group. All implied addressing instructions are one byte long.
Control Instructions
The control instructions control the MCV operations during
program execution. Refer to Table 6.
Alphabetical Listing
The complete instruction set is given in alphabetical order in
Table 7.
• Opcode Map
Table 8 is an opcode map for the instructions used on the
MCV.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
167
HD6805S6--------------------------------------------------------------
Memory
I
8
A
Indr-:H
Stack Point
I
PROG LOA #$F8 05BE
A6
Prog Count
I-------f
05BF
05CO
F8
CC
I
I
§
I
I
I
Figure 16 Immediate Addressing Example
1EA
t
Memory
i
I
I
i
i
i
i
i
I
,
i
I
CAT
FCB
32
LDA
CA T
I
004B
/'
1
Adder
'"
,
A
ooto
20
004B
~l
052D
B6
052E
4B
20
Index Reg
I
I
I
PROG
I
Stack Point
I
I
I
Prog Count
052F
CC
I
~
I
I
I
I
I
I
Figure 17 Direct Addressing Exall'l'lle
168
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
1
------------------------------------------------------------------HD6805S6
,,,
,
Memory
I
8
I
PROG
LOA
CAT
06
040B
E5
I
FCB
64
A
I
M~~ J
040A
,
CAT
0000
40
Index Reg
Stack Point
I
I
Prog Count
40
06E5
040C
CC
Figure 18 Extended Addressing Example
Memory
iI
§
PROG
BEQ
PROG2
04A7
27
04A8
18
A
Index Reg
Stack Point
I
I
0000
§
,I
I
Figure 19
Relative Addressing Example
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
169
HD6805S6--------------------------------------------------------------
Memory
A
TAB L
FCC
t LIt ooB8
4C
4C
49
Index Reg
B8
I
PROG
LOA
. I
Stack Point
05F4~
X
Prog Count
05F5
CC
§
Figure 20 Indexed (No Offset) Addressing Example
1
t
EA
Memory
I
I
I
I
I
TABL
I
I
FCB
#BF
0089
BF
FCB
#86
oo8A
86
FCB
#OB
008B
DB
FCB
#CF
008C
CF
I
I
/
I
oo8C
t
Adder
~
A
1
I
CF
I
Index Reg
I
I
I
03
I
Stack Point
PROG
LOA
TABL. X 075B
E6
075C
89
I
I
I
I
0750
CC
I
§
Figure 21
170
I
Prog Count
Indexed (8-Bit Offset) Addressing Example
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
I
------------------------------------------------------------------HD6805S6
lEA
Melory
i
i
I
i
~
~
I
LDA
TAB L. X 0692
0693
0694
/
Adder
t
J
~
I
I
I
077E
BF
#86
077F
86
FCB
#DB
0780
DB
FCB
#CF
0781
CF
Figure 22
I
02
I
I
I
I
Prog Count
0695
CC
I
#BF
DB
Stack Point
07
FCB
A
Index Reg
7E
FCB
,
-,
I
I
TABL
0780
I
I
PROG
I
I
I
Indexed (16·Bit Offset) Addressing Example
Memory
PORT B
EQU
BF
0001
A
0000
Index Reg
PROG BeLR 6. PORT B
058F
0590
1D
~------4
Stack Point
01
Prog Count
0591
I
I
~
cc
I
I
I
Figure 23 Bit Set/Clear Addressing Example
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
171
HD6805S6-------------------------------------------------------------
PORT C
EQU
A
FO
0002
2
Index Reg
0000
Stack Point
PROG BRCLR 2. PORT C. PROG 2
0574
0575
05
.....-----~
02
0576
10
I
Prog Count
0000
cc
T
I
~
I
0594
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
Figure 24 Bit Test and Branch Addressing Example
I
I
I
I
~
A
E5
Index Reg
I
I
I
PROG
TAX
E5
I
05BA~
Prog Count
058B
CC
I
I
I
I
~
Figure 25
172
Implied Addressing Example
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------------------HD6805S6
Table 2
Register/Memory Instruction s
Addressing Modes
Function
Immediate
Mnemonic
Op
Op
Op
#
#
#
#
Code Bytes Cycles Code Bytes Cycles Code
Indexed
(8-Bit Offset)
Indexed
(No Offset)
Extended
Direct
Op
#
#
Bytes Cycles Code
#
Op
#
Bytes Cycles Code
Indexed
(16-Bit Offset)
Op
#
#
Bytes Cycles Code
#
#
Bytes Cycles
Load A from Memory
LOA
A6
2
2
B6
2
4
C6
3
5
F6
1
4
E6
2
5
06
3
Load X from Memory
LOX
AE
2
2
BE
2
4
CE
3
5
FE
1
4
EE
2
5
DE
3
6
Store A in Memory
STA
-
-
-
B7
2
5
C7
3
6
F7
1
5
E7
2
6
07
3
7
Store X in Memory
STX
-
-
-
BF
2
5
CF
3
6
FF
1
5
EF
2
6
OF
3
7
Add M"mory to A
ADD
AB
2
2
BB
2
4
CB
3
5
FB
1
4
EB
2
5
DB
3
6
6
Add Memory and
Carry to A
AOC
A9
2
2
B9
2
4
C9
3
5
F9
1
4
E9
2
5
09
3
6
Subtract Memory
SUB
AD
2
2
80
2
4
CO
3
5
FO
1
4
EO
2
5
DO
3
6
Subtract Memory from
A with Borrow
SBC
A2
2
'2
B2
2
4
C2
3
Ii
F2
1
4
E2
2
5
02
3
6
AND Memory to A
AND
A4
2
2
B4
2
4
C4
3
5
F4
1
4
E4
2
5
04
3
6
OR Memory with A
ORA
AA
2
2
BA
2
4
CA
3
5
FA
1
4
EA
2
5
OA
3
6
Exclusive OR Memory
with A
EOR
A8
2
2
B8
2
4
C8
3
5
F8
1
4
E8
2
5
08
3
6
Arithmetic Compare A
with Memory
CMP
Al
2
2
Bl
2
4
Cl
3
5
Fl
1
4
El
2
5
01
3
6
Arithmetic Compare X
with Memory
2
2
B3
2
4
C3
3
5
F3
1
4
E3
2
5
03
3
6
6
CPX
A3
Bit Test Memory with A
(Logical Compare)
BIT
A5
2
2
B5
2
4
C5
3
5
F5
1
4
E5
2
5
05
3
Jump Unconditional
JMP
BC
2
3
CC
3
4
FC
1
3
EC
2
4
DC
3
5
JSR
-
-
Jump to Subroutine
-
-
BO
2
7
CD
3
8
FD
1
7
ED
2
8
DO
3
9
Table 3
Read/ModifylWrite Instructions
Addressing Modes
Function
Implied (X)
Implied (A)
Mnemonic
Op
Code
Op
#
#
Bytes Cycles Code
Indexed
(No Offset)
Direct
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
#
#
Bytes Cycles
Increment
INC
4C
1
4
5C
1
4
3C
2
6
7C
1
6
6C
2
7
Decrement
DEC
4A
1
4
5A
1
4
3A
2
6
7A
1
6
6A
2
7
Clear
CLR
4F
1
4
5F
1
4
3F
2
6
7F
1
6
6F
2
7
Complement
COM
43
1
4
53
1
4
33
2
6
73
1
6
63
2
7
Negate
(2's Complement)
NEG
40
1
4
50
1
4
30
2
6
70
1
6
60
2
7
Rotate Left Thru Carry
ROL
49
1
4
59
1
4
39
2
6
79
1
6
69
2
7
Rotate Right Thru Carry
ROR
46
1
4
56
1
4
36
2
6
76
1
6
66
2
7
Logical Shift Left
LSL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
Logical Shift Right
LSR
44
1
4
54
1
4
34
2
6
74
1
6
64
2
7
Arithmetic Shift Right
ASR
47
1
4
57
1
4
37
2
6
77
1
6
67
2
7
Arithmetic Shift Left
ASL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
Test for Negative or
Zero
TST
40
1
4
50
1
4
3D
2
6
7D
1
6
60
2
7
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
173
HD6805S6----------------------------------------------------------------Table 4 Branch Instructions
Relative Addressing Mode
Mnemonic
Function
Op
Code
#
#
Bytes
Cycles
Branch Always
BRA
20
2
4
Branch Never
BRN
21
2
4
Branch IF Higher
BHI
22
2
4
Branch I F lower or Same
BlS
23
2
4
Branch I F Carry Clear
BCC
24
2
4
(Branch IF Higher or Same)
(BHS)
24
2
4
Branch I F Carry Set
BCS
25
2
4
(Branch IF lower)
(BlO)
25
2
4
BNE
26
2
4
Branch I F Equal
BEQ
27
2
4
Branch I F Half Carry Clear
BHCC
28
2
4
Branch I F Half Carry Set
BHCS
29
2
4
4
Branch I F Not Equal
Branch I F Plus
BPl
2A
2
Branch I F Minus
BMI
2B
2
4
Branch I F I nterrupt Mask Bit is Clear
BMC
2C
2
4
Branch I F Interrupt Mask Bit is Set
BMS
2D
2
4
Branch I F Interrupt Line is low
Bil
2E
2
4
Branch IF Interrupt Line is High
BIH
2F
2
4
Branch to Subroutine
BSR
AD
2
8
Table 5 Bit Manipulation Instructions
Addressing Modes
Bit Set/Clear
Mnemonic
Function
Op
Code
Bit Test and Branch
#
#
Bytes
Cycles
Op
Code
#
#
Bytes
Cycles
Branch I F Bit n is set
BRSET n (n=O ..... 7)
-
-
-
2-n
3
10
Branch I F Bit n is clear
BRClR n (n=O .... .7)
-
-
-
01+2-n
3
10
-
-
Set Bit n
BSET n (n=O ..... 7)
10+2-n
2
7
-
Clear bit n
BClR n (n=O ..... 7)
11+2-n
2
7
-
-
Table 6 Control Instructions
Implied
Function
174
Mnemonic
Op
Code
#
#
Bytes
Cycles
Transfer A to X
TAX
97
1
2
Transfer X to A
TXA
9F
1
2
Set Carry Bit
SEC
99
1
2
Clear Carry Bit
ClC
98
1
2
Set Interrupt Mask Bit
SEI
9B
1
2
Clear Interrupt Mask Bit
CLI
9A
1
2
Software Interrupt
SWI
83
1
11
Return from Subroutine
RTS
81
1
6
Return from Interrupt
RTI
80
1
9
2
2
Reset Stack Pointer
RSP
9C
1
No-Operation
NOP
90
1
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
---------------------------------------------------------------HD6805S6
Table 7 I nstruction Set
Condition Code
Addressing Modes
Mnemonic
Implied
Immediate
Direct
Extended
Relative
Indexed
Indexed
(No
(8 Bits)
Offset)
Indexed
(16 Bits)
ADC
x
x
x
x
x
x
ADD
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
AND
ASL
x
x
ASR
x
x
Bit
Set/
Clear
x
BCC
x
BCLR
BCS
x
BEQ
x
BHCC
x
BHCS
BHI
x
x
BHS
x
BIH
x
BIL
x
x
BIT
x
x
x
x
x
x
x
x
BLO
BLS
BMC
BMI
x
BMS
BNE
x
x
BPL
x
BRA
x
BRN
x
x
x
BRCLR
BRSET
x
BSET
x
BSR
CLC
x
CLI
x
CLR
x
DEC
x
x
x
x
x
x
x
x
x
x
x
EOR
x
x
x
CPX
x
x
x
CMP
COM
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
JMP
x
x
x
x
JSR
x
x
x
x
x
x
x
x
x
x
x
x
x
INC
Bit
Test &
Branch
LDA
x
x
x
LDX
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
x
H
I
N
Z
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
•
1\
1\
1\
1\
1\
•
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
C
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
1\
1\
•
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • 1\
• • 1\
• • •
• • •
• • 0
0 • • •
• 0 1 •
• 1\ 1\ 1\
• 1\ 1\ 1
• 1\ 1\ 1\
• 1\ 1\ •
•
•
•
•
•
•
•
•
•
•
•
•
• 1\ 1\ •
• 1\ 1\ •
• • • •
• • • •
• 1\ 1\ •
•
1\
1\
•
(to be continued)
C
1\
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
175
HD6805S6--------------------------------------------------------------Table 7 Instruction Set
Condition Code
Addressing Modes
Mnemonic
Implied
Immediate
Extended
Relative
LSL
x
x
x
LSR
x
x
NEG
x
x
x
x
NOP
x
x
ORA
x
Setl
Clear
x
x
x
x
x
x
x
x
x
x
x
x
Bit
x
Bit
Test &
Branch
I
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
1
•
•
•
1
•
•
•
1\
1\
1\
0
1\
1\
1\
1\
1\
RSP
RTI
x
?
RTS
x
•
•
•
•
•
•
•
•
•
•
•
ROR
x
SBC
SEC
SEI
x
STA
x
x
STX
x
x
x
x
x
SUB
TAX
x
x
TST
x
TXA
x
SWI
x
x
x
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
I nterrupt Mask
N
Negative (Sign Bit)
Z
Zero
x
C
1\
x
x
x
x
x
x
x
x
x
x
x
Z
H
x
x
x
ROL
176
Direct
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
C
• • •
1\ 1\ •
1\
1\
1\
1\
1\
1\
• • •
?
?
?
• • •
1\
1\
1\
• • 1
• • •
1\ 1\ •
1\ 1\ •
1\ 1\ 1\
• • •
• • •
1\ 1\ •
• • •
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave .• San Jose, CA 95131 • (408) 435·8300
---------------------------------------------------------------HD6805S6
Table 8
Bit Manipulation
Branch
Opcode Map
Control
Read/Modify /Write
I ,XO
I 7
Register/Memory
I
I
I EXT I ,X2 I Xl I ,XO
I C I D I E I F
Test &
Branch
Set/
Clear
Rei
DIR
0
1
2
3
0
BRSETO
BSETO
BRA
NEG
RTI"
-
1
BRCLRO
BCLRO
BRN
-
CMP
1
BRSETl
BSETl
BHI
-
RTS'
2
-
SBC
2
I
I
A
4
I
I
X
5
I
I
,Xl
6
IMP
8
-
IMP
IMM
9
A
DIR
B
SUB
<-
HIGH
0
3
BRCLRl
BCLR1
BLS
COM
CPX
3
L
4
BRSET2
BSET2
BCC
LSR
-
-
AND
4
o
-
-
-
BIT
5 W
-
-
LDA
6
STA(+l)
7
CLC
EOR
8
SEC
ADC
9
CLI
ORA
A
ADD
B
5
BRCLR2
BCLR2
BCS
6
BRSET3
BSET3
BNE
ROR
7
BRCLR3
BCLR3
BEQ
ASR
SWI"
TAX
-
8
BRSET4
BSET4
BHCC
LSL/ASL
9
BRCLR4
BCLR4
BHCS
ROL
A
BRSET5
BSET5
BPL
DEC
B BRCLR5
~CLR5
BMI
-
-
SEI
C BRSET6
BSET6
BMC
INC
-
RSP
D BRCLR6
BCLR6
BMS
TST
NOP
E BRSET7
BSET7
BIL
-
-
BRCLR7
BCLR7
BIH
CLR
-
TXA
-
1/2
2/2
F
3/10
(NOTE)
2/7
2/4
2/6
I 1/4
I 1/4
I 2/7
11/6
1/'
I
-
I
BSR'I
I
I
2/4
I 3/5
JMP(-l)
C
JSR(+3)
D
LDX
E
STX(+1)
F
I 3/6
I 2/5
I 1/4
1. Undefined opcodes are marked with "-".
2. The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles).
Mnemonics followed by a ..... require a different number of cycles as follows:
RTI
9
RTS
6
SWill
BSR
8
3. (
indicate that the number in parenthesis must be added to the cycle count for that instruction.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
177
HD6805T2--------------MCU (Microcomputer
Unit with PLL Logic)
-PRELIMINARY-
The HD6805T2 is an 8-bit Microcomputer Unit (MCU)
which contains a CPU, on-chip clock, ROM, RAM, I/O, Timer,
and the PLL Logic for an RF synthesizer. It meets the needs of
users who needs economical single chip microcomputer with the
proven abilities of MPU instruction set of HD6800.
The Principal characteristics of the hardware and software of
the MCU are listed below.
• HARDWARE FEATURES
• 8-bit Architecture
• 64 Bytes of RAM
• Memory Mapped I/O
• 2508 Bytes of User ROM
• Internal 8-bit Timer with 7 -bit Prescaler
• Timer Start/Stop and Source Select
• Vectored Interrupts - External and Timer
• 19 TTL/CMOS Compatible I/O Lines; 8 Lines are LED Compatible
• On-Chip Clock Circuit
• Self-Check Mode
• Master Reset
• Low Voltage Inhibit
• 14-Bit Binary Variable Divider
• 1O-Stage Mask-Programmable Reference Divider
• Three-State Phase and Frequency Comparator
• Suitable for TV Frequency Synthesizers
• 5Vdc Single Supply
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SOFTWARE FEATURES
Resembles HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM, and I/O
Compatible with MC6805T2
178
HD6805T2P
(DP-28)
•
PIN ARRANGEMENT
VSS
INT
A7
VCC
A6
EXTAL
As
XTAL
A4
NUM
A3
ct>COMP
HD6805T2
A2
Co/TIMER
AI
C1
Ao
C2
B7
fin
B6
Bo
Bs
BI
B4
B2
Bs
(Top View)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
•
,...Dl
o(')
'"
~
C
~
:;
»
:lJ
:r.
C)
»
s:
3
~
o·
SD
r
ii
•
RES
I\)
I\)
INT
Ao
a
A,
CPU
Control
NUM
o
cj
ALU
CPU
EXTAL
XTAL
Oscillator
~
~:I
A,
Data
Dir.
Reg.
A.
A.
A,
A.
A7
CD
.~
Accumulator
(8)
• :J>
mel
!
'~
oen
Condition Code
Register
(5)
Index Register
Stack Pointer
(8)
(5)
Program
Counter "High"
Bo
(4)
Program
Counter "Low"
(8)
B,
B,
Data
Dir.
Reg.
CD
B.
B.
B,
B.
o
B7
»
fin
<0
~
~
Data
Dir .
•
Reg.
Co/TIMER
C,
C,
~
o
~
..Jlo.
Cal
UI
m
Cal
o
o
:::I:
C
0>
00
o01
'"
'<)
-i
N
HD6805T2----------------------------------------------------------------•
ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
Symbol
Value
Unit
Vee·
-0.3 to +7.0
V
-0.3 to +7.0
V
Input Voltage (Except cpCOMP)
Vin·
Input Voltage (cpCOMP)
Operating Temperature
Topr
Storage Temperature
Tstg
-0.3 to + 12.0
o to
V
+70
°C
-55 to + 150
°C
• With respect to Vss (SYSTEM GND).
(Note) When the maximum ratings are exceeded. the LSI may be irreparably damaged. Recommended operating conditions should be adhered to.
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee
= 5.25V ±
O.5V. Vss
Item
Input "High" Voltage
min.
typo
max.
Unit
RES
4.0
-
Vee
V
INT·
3.0
-
Vee
V
Test Condition
2.0
-
Vee
V
Normal Mode
2.0
-
Vcc
V
Self-Check Mode··
9.0
11.0
V
All Other Except fin
Input "High" Voltage
cpCOMP
= GND. Ta = 0 to + 70°C. unless otherwise noted.)
Symbol
V IH
RES
-0.3
-
0.8
V
INT·
-0.3
-
0.8
V
-0.3
-
0.6
V
-0.3
-
0.8
V
-
-
850
mW
V ACP -P
Input "Low" Voltage
V IL
EXTAL
All Other Except fin
Power Dissipation
Not Port
Loading
Po
AC Coupled Input Voltage Swing
fin
V FIP
0.5
-
2.4
Input Leak Current
fin
IIIL I
-
-
40
p.A
Output "Low" Current
cpCOMP
ICML
-
-
300
p.A
Output "High" Current
cpCOMP
ICMH
-
p.A
cpCOMP
IIIL I
-
-
200
Input Leak Current
1.0
p.A
LVR
-
-
4.75
V
Low Voltage Recover
Low Voltage Inhibit
VOL
V OH
1.0V
= Vce
-
lV
LVI
INT
Input Leak Current
=
EXTAL
RES
IIIL
I
Vin
= 0.4V
Vin = 0.8V
-
4.0
-
-
50
p.A
-
-
1600
p.A
4.0
-
50
p.A
-
V
• Internal biasing makes the input float to approximately 2.0V when unused .
•• In self-check mode. q,COMP may be connected to V1H through 10 kfl register.
180
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------------HD6805T2
•
AC CHARACTERISTICS (Vee = 5.25V ± O.5V. Vss = GND. Ta = 0 to
Item
Symbol
unless otherwise noted.)
min.
typo
max.
Unit
0.4
-
4.2
MHz
Cycle Time
tcyc
0.95
-
10
JLs
INT Pulse Width
t lwL
t cyc +
250
-
-
ns
RES Pulse Width
t RWL
t cyc +
250
-
-
ns
TIMER Pulse Width
t TwL
t cyc +
250
-
-
ns
Delay Time Reset
tRHL
-
100
-
ms
Clock Frequency
fcl
External Cap.
= 1.0JLF
Input Frequency
fin
1
-
16
MHz
Input Frequency Rise Time at fin
tinr
-
-
20
ns
tinf
-
-
20
ns
-
40
-
60
%
terr
-
70
-
ns
-
35
pF
-
10
pF
Input Frequency Fall Time at fin
Duty Cycle of fin and External Input on EXT Al
Injection Pulse Active Time
Input Capacitance
•
+ 70°C.
Test Condition
I
XTAl
I
All Other
Vin = OV
Cin
PORT elECTRICAL CHARACTERISTICS (Vee = 5.25V ± O.5V. Vss = GND. Ta = 0 to
Symbol
min.
typo
max.
Unit
IOH = -100JLA
2.4
-
V
IOH = -10JLA
3.5
-
-
V
IOH = -100JLA
2.4
-
-
V
Port B
IOH = -200JLA
2.4
-
-
V
Port C
IOH
Port A with CMOS
Drive Enable
Port A with CMOS
Drive Disable
V OH
Port A
Output "low" Voltage
Port B
=
2.4
-
-
V
IOL = 1.6mA
-
-
0.4
V
IOL = 3.2mA
-
-
0.4
V
-
1.0
V
-
0.4
V
-100JLA
VOL
IOL = 10mA
Port C
Input "High" Voltage
Port A. B. C
Input "low" Voltage
IOL = 1.6mA
V IH
2.0
-
Vee
V
V IL
-0.3
-
0.8
V
300
JLA
-
500
JLA
-
-
20
JLA
-
-
20
JLA
-
20
iJ.A
Vin = 2.0V
Port A with CMOS
Drive Enable
Input leak Current
unless otherwise noted.)
Test Condition
Item
Output "High" Voltage
+ 70°C.
Port A with CMOS
Drive Disable
Vin
IIlL I
Port B
Port C
= 0.8V
-
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
181
HD6805T2---------------------------------------------------------------CMOS Equiv. (Port A)
TTL Equiv. (Port B)
TTL Equiv. (Port A and C)
5.0V
2.4kn
1.2kn
Test Point
0------------'1
Test Point
Test POint
r'F
5.0V
40pF
30pF
12kn
24kn
(Note) 1. Load capacitance contains the floating capacitance of the probe, the jig, etc.
2. All diodes are 152074
or the similar.
®
Figure 1 Bus Timing Test Loads
•
• Vee. Vss
The MCU is supplied power through these pins. Vee is S.2SV
± 0.5V. Vss is grounded.
•
INT
This pin provides an external interrupt to the MCU. For more
details, see INTERRUPTS.
•
XTAL.EXTAl
These are control input pins for the internal clock circuit.
Connection of these pins to a crystal (AT cut, 4.2 M Hz maximum) or to an external input provides the internal oscillator with
varying degrees of stability. For suggestions pertaining to these
pins, see INTERNAL OSCILLATOR OPTIONS.
• fin
This fin pin is a high frequency digital input to the variable divider portion of the on-chip frequency synthesizer. The reference
frequency for the phase lock loop is divided down from internal
clock CPz. The frequency synthesizer features are explained in
PHASE LOCK LOOP.
• cpCOMP
This is a three-state output signal. The state varies according
to the result of the comparison between the internal reference
frequency and the variable divided signal. See PLL for details.
cpCOMP is raised to 9V through 10 kfl in self-check mode.
•
RES
Besides the resetting capability which the MCU already has,
this pin also makes resetting of the MCU possible. See RESETS
for more details.
•
NUM
This pin should be grounded as it is not applicable to users.
182
INPUT/OUTPUT Lines lAo to A 7 • Bo to 8 7 , Co to C z)
These 19 lines form two 8-bit ports (Port A, Port B) and one
3-bit port (Port C). By software control of the data direction registers, these lines can be programmed to be either inputs or outputs. See INPUTS/OUTPUTS for more information. The
Co/TIMER pin also can be programmed as an external input to
the internal timer. For information on the timer modes, see
TIMER.
•
SIGNAL DESCRIPTION
The following describes the input and output signals of
H06805T2.
•
MEMORY
The MCU memory diagram is indicated in Figure 2. The
MCU, with its program counter, can address 4096 bytes of
memory and I/O registers. The MCU has implemented 2698 of
the 4096 memory locations, 2508 bytes user ROM, 116 bytes
self-check ROM, 64 bytes of user RAM, 6 bytes of port I/O, 2
timer registers, and 2 PLL registers. The user ROM is divided
into four areas. The first area (begins at $080) provides users
with access to ROM locations by using the direct and table lookup indexed addressing mode. The second and third user ROM
areas begin at memory location $100 and $040 respectively. The
last eight-byte user ROM which begins at $FF8 is for the interrupt vectors.
The first 16 memory locations of the MCU are reserved for 1/
o features and 10 of them have been implemented. These locations are used for the ports, the port OORs, the timer, and the
PLL registers.
The MCU has 64 bytes of user RAM. 31 bytes out of the 64
bytes are shared with the stack area. Careful utilization of the
stack is necessary when data shares the stack area.
While interrupt and subroutine calls are processed to save the
processor state, the shared stack area is occupied.
The register contents are saved in the stack as indicated in
Figure 3. The low order byte (PCL) of the program counter is
stacked first as the stack pointer decrements during saving. Next,
the high order four bits (PCH) are stacked. This ensures that the
program counter is loaded correctly after pulls from the stack. as
the stack pointer increments when it fetches data from the stack.
Only when a subroutine call is made, the program counter (PCH,
PCL) contents are saved onto the stack, and the remaining CPU
registers are not saved.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD6805T2
7
6
I
I
5
I
4
I
3
I
I
1
I
0
Port A Register
$00
Port 8 Register
$01
I
Not used
$02
$03
Not used
$04
Port A DDR Register
Port C Register
Port 8 DDR Register
$05
I
Not used
$06
Port C DDR Register
Not used
$07
$08
Timer Data Register
$09
Timer Control Register
Variable Divider" Low"
$OA
$08
2
Not used
I
Variable Divider "High"
10
Direct
Addressing
Mode Enable
11
12
SOC
Not used
(52 bytes)
$03F
63
64
$040
User RAM
(64 bytes)
$07F
127
$080
128
I
(128 bytes)
I
$OFF
$100
I
I
I
I
---
User ROM
--------------------
I
255
256
I
I
(1792 bytes)
I
I
I
I
$7FF
2047
$800
2048
Not used
(1344 bytes)
$D3F
3391
$040
3392
I
I
I
User ROM
I
(580 bytes)
I
I
I
I
I
I
3971
$F83
$F84
3972
I
I
I
I
I
I
Self-check ROM
(116 bytes)
I
I
I
I
I
I
$FF7
4087
$FF8
4088
Interrupt Vector ROM
(8 bytes)
4095
$FFF
Figure 2 MCU Memory Configuration
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
183
HD6805T2--------------------------------------------------------------Return
Interrupt
7
6
I
K-4
1
J
1
5
:
I
3
4
2
1
0
I
1
I
I
CCR
Interrupt
-------K+1
K-3
A
K+2
Call
K-2
X
K+3
]
K~
Subroutine
-----
I
1
I
1
:
I
Return
Subroutine
I
1
:
______
1
I
PCH
I
PCl
Only PCH and PCl are saved for subroutine calls.
Figure 3
•
Interrupt Stacking Order
levels of subroutine calls.
REGISTERS
The MCU provides five registers for the programmer which
are indicated in Figure 4. These registers are explained in the following.
•
Accumulator (A)
The accumulator is an 8-bit general purpose register. It holds
operands and results of arithmetic calculations or data manipulations.
•
Condition Code Register (CC)
The condition code register is a 5-bit register. In the register,
the results of the instruction just executed is indicated or flagged
by each bit. These bits can be individually program tested specific
action taken as a result of their state. The following paragraphs
explain each individual code register bit.
Half Carry (H)
•
Index Register (X)
The index register is an 8-bit register for the indexed addressing mode. It has an 8-bit address which can be added to an offset
value to make an effective address. When using read/modify/
write instructions, it may also be used for data manipulation and
limited calculations. When not required by the code sequence
being executed, it can be a temporary storage area.
•
Interrupt (J)
This bit is set to mask external interrupt (INT) and the timer.
If an interrupt takes place while this bit is set, it is latched and
will not be processed until the interrupt bit is reset.
Negative (N)
Program Counter (PC)
The program counter is an 12-bit register. It contains the address that decides which instruction is to be executed next.
•
Indicates that a carry occurred between bits 3 and 4 during an
arithmetic operation (ADD and ADC).
Indicates that the result of the last data, arithmetic, or logical
manipulation was negative (bit 7 in result equal to a logic
"one").
Stack Pointer (SP)
The stack pointer is a 12-bit register. It contains the address of
the next free location in the stack. Firstly, the stack pointer is set
to location $07F. Then it is decremented as data is being pushed
onto the stack and incremented as data is being pulled from the
stack. The seven most crucial bits of the stack pointer are set to
0000011 permanently. The stack pointer is set to location $07F
during and MCU reset or the reset stack pointer (RSP) instruction. Subroutines and interrupts can be nested down to location
$061 which enables the programmer to use a maximum of 15
184
Zero (Z)
It indicates that the result of the last data, arithmetic, or logical manipulation was zero.
Carry/Borrow (C)
During the last arithmetic operation, it indicates that a carry
or borrow out of the arithmetic unit (ALU) occurred. During
branch instructions, rotates, bit test, and shifts, this bit is also
affected.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------------------HD6805T2
A (8)
x (8)
PCL (8)
PCH (4)
o
o
o
o
o
SP (5)
H
C:
Z:
N:
I :
H:
N
z
C
(CCR)
Carry/Borrow
Zero
Negative
Interrupt Mask
Half Carry
Figure 4 Programming Model
•
TIMER
The MCU timer circuitry is indicated in Figure 5. Program
control enables the 8-bit counter to be loaded and the clock input
(prescaler output) decrements the counter toward zero. When
the timer reaches zero, the timer interrupt request bit (bit 7) in
the Timer Control Register (TCR) is set. The timer interrupt
mask bit (bit 6) in the TCR enables the timer interrupt to be
masked (disabled). The timer also becomes inhibited by the interrupt bit (I-bit) in the Condition Code Register. When the
MCU responds to the interrupt requirement, it maintains the
present CPU state in the stack, fetches the timer interrupt vectors from locations $FF8 and $FF9, and executes the interrupt
routine. See INTERRUPT for more details.
The timer clock input is established by way of bit 5 (TCR 5)
in the Timer Control Register. When this bit is set to a logic
"one" (external mode), the Co/TIMER pin is the time clock
source. In this mode, a mask option selects either the gated rP2
with Co or the positive transition on Co/TIM ER as timer clock
source. This makes pulse widths or pulse counts easily measured.
The timer clock source is the internal rP2 when TCR 5 is set to a
logic "zero". When bit 4 in the Timer Control Register is set to
a logic "one", the time clock source is disabled.
The timer continues to count past zero, falling through to $FF
from zero, and then continuing to count. The counter can be
monitored by reading the Timer Data Register (TOR). This
allows a program to determine the length of time since a timer
interrupt has occurred without disturbing the counting process.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
185
HD6805T2--------------------------------------------------------------Data Bus
Timer Control Reg.
(TCR)
Timer Data Reg.
(TOR)
and
8-bit Counter
o
o~--------------
Timer
Interrupt
Mask
Prescaler
Mask
Option
Figure 5 Timer Block Diagram
6
TCR7
TCR6
o
4
TCR5
TCR4
TCR3
TCR2
TCR1
TCRO
TCR7 - - Timer Interrupt Request Status Bit;
Set when TOR "0"; cleared to "0" during reset.
TCR6 --Timer Interrupt Mask Bit;
When "1", timer interrupt is masked (disabled). Set to "1"
during reset.
TCR5 - - External Timer Source;
External when set to "1" and internal when set to "0".
Cleared to "0" during reset.
TCR4 - - Disable Timer;
Timer source is disconnected when set to "1" and timer input
enabled when set to "0". Cleared to "0" during reset.
TCR bits 3,2, 1 and 0; set to all "1" 's (not used).
186
$HITACtt·
Hitachi America Ltd. •
2210
O'Toole Ave. • San Jose, CA 95131
• (408) 435-8300
---------------------------------------------------------------HD6805T2
•
SELF-CHECK
The MCV has a self-check capability which allows an internal
check to see whether a port is functional or not. Connect the
MCV as indicated in Figure 6 and monitor the output of Port C
bit 2 for an oscillation of approximately 7 Hz. Pin 7, a 9 volt
level on the ct>COMP input, energizes the ROM-based self-check
feature. The self-check program exercises the timer, interrupts, II
o ports, RAM, and ROM.
•
RESETS
There are three ways to reset the MCV; initial power up, the
external reset input RES), and by an internal low voltage detect
circuit. See Figure 7 for details. All the I/O ports are initialized to
Input Mode (DDR's are cleared) during RESET.
A delay of tRHL is essential upon power up before allowing
the reset input to go "High".
27
~
This time allows the internal crystal oscillator to stabilize. Sufficient delay can be provided by connecting a capacitor to the
RES input as shown in Figure 8.
•
INTERNAL OSCILLATOR
The design of the internal oscillator circuit aims at the requirement of minimum of external components. A crystal or an external signal can be used to drive the internal oscillator. Figures 9
and 10 show different connection methods. Figure 11 indicates
the crystal specifications.
The crystal oscillator startup time changes according to many
variables: crystal parameters (especially R s ), oscillator load capacitances, IC parameters, ambient temperature, and supply capacitances. To ensure rapid oscillator startup, neither the load capacitance nor the crystal characteristics should exceed the recommended value.
28
i
RES
A7
26
--
I - - A.
INT
2
r---
10 F
. .u
25
I - - As
r-
24
...AAA
9V
6
23
~
10kO
7
COMP
A.
t-
NUM
A3
L..
22
'---
A2
~ A,
Co/TIMER
HD6805T2
18
B7
r--
B.
17
f--
Bs
16
-
15
14
'---
-
13
12
C2
fin
y
A
3300 x 3
~
5
XTAL
.L
0
EXTAL
B2
Bo
A
VV
jQ,,J
'U'
4
B,
rJ
11
B.
B3
~
'U'.
10
Vce
.A
'<7
C,
Ao
-
,J
~
9
20
19
8
3
I
i
Vce
VSS
4MHz
22pF
1"\
1
VCC
1"'
L.:
Figure 6 Self Check Connections
Hitachi America Ltd. •
2210
~HITACHI
O'Toole Ave. • San Jose, CA 95131
187
• (408) 435-8300
HD6805T2---------------------------------------------------------------
RES
Pin
-----------r
Internal
Reset------------'
Figure 7 Power Up and RES Timing
220k.!1
28
VCC-JVVV---+----,
RES
--;J; 1.01'F
5 XTAl
4 MHzCJ
max
4 EXTAL
Part of
HD6805T2
MCU
HD~~JT2
CL =22P F±20%;J;
Figure 9 Crystal
Figure 8 Power Up Reset Delay Circuit
External
Clock
l_n_p_ut_ _ _4~ EXT A L
5 XTAL
HD6805T2
MCU
AT - Cut Parallel Resonance Crystal
Co = 7pF max.
f 4 MHz (CL =22pF±20%)
RS=60.!1 max.
&
Figure 11
Figure 10 External Clock
•
INTERRUPTS
The MCU can be interrupted three ways as follows: CD
through the external interrupt (INT) input pin,
the internal
timer interrupt request, Q) the software interrupt instruction
(SWI). If any interrupt occurs, processing is in pending, the current CPU state is saved in the stack, the interrupt bit (1) in the
condition Code Register is set, the address of the interrupt
routine is received from the proper interrupt vector address, and
finally the interrupt routine is carried out. The complete stacking
the CPU registers, setting the I-bit, and vector fetching, a total of
II tcyc periods are required.
Figure 12 illustrates a flowchart of the interrupt sequence.
When a return from interrupt (RTI) instruction is issued, the interrupt servic~ routine must b..; terminated to caus~ til..; :ViC L., to
resume processing of the program held by the interrupt (by popping off the previous CPU state). Table I lists the interrupts,
their priority, and the address of the vector containing the start
address of the proper interrupt service routine. The interrupt
priority applies to those suspended when the CPU is ready for a
a:>
188
Crystal Parameters
new interrupt. Though RES is listed in Table I in that it is occasionally regarded as an interrupt, it is not normally used as such.
When the interrupt mask bit in the Condition Code Register is
set, the interrupt is latched for executing a later interrupt.
The external interrupt is internally synchronized and then
latched onto the negative edge of INT, which can be driven by a
digital signal at a maximum period of tIWL'
Table 1
Interrupt
Priority
RES
SWI
1
2"
INT
TIMER
3
4
Vector Address
$FFE
$FFC
$FFA
$FF8
and
and
and
and
$FFF
$FFD
$FFB
$FF9
• Priority 2 applies when the I-bit in the condition Code Register is set.
When I = O. SWI has priority 4. like any other instruction. Therefore.
INT has priority 2 and the timer has priority 3.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD6805T2
y
I-bit (in CCR)
: set
INT logic
: Clear
DDR, A, B,C
: all clear
SP
: 07F
Prescaler
: 7F
TDR
: FF
TCR
: 4F
I-bit (in CCR)
set
TNT
N
INT logic
Clear
INT Pin
N
(TCR6)·(TCR7)
y
TIMER
SWI
y
PC ~ PC + 1
load PCH/PCl from
FFE/FFF
STACK
PCH, PCl, A, X, CCR
load PCH/PCl from
TIMER
INT
:
SWI
:
Figure 12
FF8/FF9
FFA/FFB
FFC/FFD
Interrupt Processing Flowchart
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
189
HD6805T2------------------------------•
INPUT/OUTPUT
The HD6805T2 is provided with 19 I/O pins (00 is also an
input pin but is used only as an interrupt). The Data Direction
Register (DDR) of each pin defines whether it is an input or an
output (" 1" is an output; "0" is an input).
To Timer
for Co/TIMER Pin
Input
Port A, B, C
Register
Bit
Output
Pin
Port A, B, C
DDR
Bit
Port A, B, C
DDR Bit
1
1
0
Port A, B, C
Register Bit
0
1
0/1
Output State
0
1
3-State*
0
1
Pin
Input to MCU
* Except Port A (CMOS drive enable option)
Figure 13 Port A, B, C Block Diagram
190
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------------HD6805T2
The DDR is initialized to all "O'''s by resetting and all pins
become input. The output registers, not initialized by resetting,
can be set before programming the DDR to prevent undefined
level. Fig. 13 shows the latched output data may be read as input
data in the case programmed as an output regardless of the logic
levels at the output pin due to output loading. If programmed as
an output, port B can sink 10 mA (VOL max = 1V) and source
I rnA on each pin.
80
Port 8
Port A
8,
A,
(b)
(a)
Port A: Drives CMOS and TTL loads directly when programmed as an
output. Internal pull-up devices are included for CMOS drivability. For more details, refer to ELECTRICAL CHARACTERISTICS.
Port 8: Drives Darlington base directly when programmed as an output.
+v
+v
R
80
C./TIMERf--_ _ _......._
Port B
··
Port C
CMOS Inverter
C2
10 mA max
8,
(c)
(d)
Port 8: Drives LED(s) directly when programmed as an output.
Port C: Drives CMOS by external pull-up resistors when programmed as
an output.
Figure 14 Typical Port Connections
All 110 lines, either for inputs or outputs, are TTL compatible. Both ports Band C as inputs are CMOS compatible; port A
as outputs is CMOS compatible by mask option. Some of the
port connections are shown in Fig. 14. Fig. 2 shows the data register and the DDR's address.
Caution
The DDR's corresponding to ports A, Band C (at $004, $005
and $006) are provided for write operation only; the read operation is not defined. BSET and BCLR for read/modify/write opera-
tions don't set or clear DDRs, but unaffected bits can be set, so
it is recommended to use a single-store instruction to write into
DDR's.
The latched output data can be written as shown in Fig. 13.
When writing to a port, any data can be written even in its DDR
"input" mode. This initializes the data registers to prevent any
uncertain output. But read/modify/write instructions should be
handled carefully because read data depends on the I/O level of
the pin with the DDR in the input (0) mode and on the latched
output data with the DDR in the output (I) mode.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131
191
• (408) 435-8300
HD6805T2---------------------------------------------------------------•
PHASE LOCK LOOP (PLL)
The HD6805T2 has a Phase Lock Loop (PLL) which consists
of a 14-bit binary variable divider, a 10-phase reference divider, a
frequency and phase comparator which has a three-state output,
and the circuits which prevent "backlash" in phase lock states.
-
LPF
Fig. 15 gives an easily established frequency synthesizer system driven by a voltage-controlled oscillator when connecting an
adequate high-frequency prescaler and an active integrator. The
equations controlling the PLL is shown in Fig. 16.
r----
VCO
Prescaler
(+ P)
~
COMP
fin
Phase
Comparator
14-bit Variable
Divider
(+ N)
I.-.--
r--
fREF
Reference
Divider
(+ R)
/\
fVAR
J
HD6805T2
CPU
<1>.
<1>.
Divider
(1/4)
<1>1
YDtFigure 15 Phase Lock Loop as R F Frequency Synthesizer
192
~HITACHI
Hitachi America Ltd_ • 2210 O'Toole Ave_ • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------------HD6805T2
For a system in lock: fVAR = fREF
since fin = fVAR'N, fVCO = tin'P ( P = Prescaler diving ratio),
fVCO = fREF,P'N
Minimum frequency step =
M~~O
= fREF'P
e.g.: tCl ~ 4.00 MHz, R .. 2 '0 (R=the reference dividing ratio), P=64
f),f~;O
= 62.5 kHz, fREF = 976.5 Hz
Figure 16 Principal PLL Equations
•
VARIABLE DIVIDER
The variable devider, a 14-bit binary down counter, sends/receives data to/from the CPU through read/write registers which
are located at $OOA in the case of the Least Significant (LS) byte
and $008 in that of the Most Significant (MS) byte. "1" is
always read from the high-order two bits of the $OOB register.
The variable divider counting zero will generate a preset pulse
fvAR . Fig. 17 provides a PLL block diagram where the 14-bit
latch is reloaded to the variable divider.
When the $OOA register is being written into, data is transferred from $OOA and $OOB registers to the latch, outside the preset
time. Assume that 6-bit data is transferred to $OOB register. The
data is transferred to the variable divider only when $OA register
is next written into. An errorless data transfer in the fine tuning
operation is shown in Fig. 18.
The 14-bit latch is activated synchronously with the communication between the CPU and the variable divider, which are
asynchronous devices.
When switching on, the PLL registers and the variable divider
are fixed to "1".
The variable frequency input pin, fin, is self biased requiring
an ac coupled signal with a normal swing of 1.2V. As the input
frequency of fin varies with the appropriate prescaler, the whole
TV frequency spectrum may be included.
•
REFERENCE DIVIDER
A reference frequency, fREF , is made by the lO-phase binary
counter and is compared with the variable divider output. This
reference divider is mask optional and the user can select any
frequency as shown in Fig. 17.
fin
CPU
Data Bus
1
2"iO
Reference
Divider
1
2'
8
\
Variable
Divider
(14 bits)
Register
($OOA)
latch
(14 bits)
6
Mask
Option
Register
($OOB)
6
MSB
fVAR
load
Synchronize
Write $OOA
Figure 17 PLL Block Diagram
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
193
HD6805T2--------------------------------------------------------------CTD
CTD1
CTU
CTU1
TST
BNE
DEC
DEC
PLLA
CTD1
PLLB
PLLA
LDA
INCA
BNE
INC
INC
CTU1
PLLB
PLLA
•
Check if Low byte = "00"
If not decrement only Low byte
Decrement High byte
Decrement Low byte
PHASE COMPARATOR
Both the frequency and phase of fVAR and fREF are compared
by the phase comparator, whose relation will generate c/>COMP, a
three-level output, shown in Figs. 19 and 20. c/>COMP is combined, amplified and the dc voltage is supplied to the voltage control oscillator.
.
Internal transfer delays will prevent linear features in the stable area. Non-linear characteristics are shown by the phase comparators and this leads to a "backlash" effect which will cause
sideband and FM distortion. Insertion of a very short pulse into
the device will prevent this. On insertion, the loop tries to cancel
the pulse to carry the phase comparator to the linear area shown
in Fig. 21.
PLLA
Check if Low byte = "FF"
If not increment only Low byte
Increment High byte
I ncrement Low byte
Figure 18 Typical Fine Tune Example
COMP
Output
Phase Comparator
Input
Low
Level
HighImpedance
High
Level
Figure 19 State Diagram (Phase Comparator)
194
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD6805T2
L
I
I
I
I
------'IIrTlL-_____
tvAR-----'nl'-------'fil'------IH1"-"--_ _
High-
I
I
I
I
I
--,I r
II
II
tL
n
'--U=
I
I
n
I
r i s e injection
2
signal. When the internal <1>2 signal is selected as the input
source, the node a is connected to b (see Fig. 5). In case of the
external source, the node b connects with c. When the <1>2 Signal
is used as the source, the clock signal is input to the prescaler
while the TIMER input is "High". The source of the clock input
is one of the options that has to be specified before manufac-
<1>,
(Internal)
Timer
Input
Pin
,.-----.,
I
I
I
I
I
I
I _____ .JI
L.
Manufacturing
Mask Options
Wrtte
Read
Write
Read
Figure 5 Timer Block Diagram
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
213
HD6805U1------------------------------------------------------------•
ture of the MCU. A prescaler option can be applied to the clock
input that extends the timing interval up to a maximum of 128
counts before decrementing the counter (TDR). The timer continues to count past zero, falling through to $FF from zero and
then continuing the count. Thus, the counter (TDR) can be read
at any time by reading the TDR. This allows a program to determine the length of time since a timer interrupt has occurred and
not disturb the counting process.
The TDR is 8-bit Read/Write Register in location $008.
At power-up or reset, the TDR and the prescaler are initialized
with all logical ones.
The Timer Interrupt Request bit (bit 7 of the TCR) is set
by hardware when timer count reaches zero, and is cleared by
program or by hardware reset. The bit 6 of the TCR is writable
by program. Both of those bits can be read by CPU.
(NOTE) If the MCU Timer is not used, the TIMER input pin
must be grounded.
2-
INT
2
RES
SELF CHECK
The self-check capability of the MCU provides an internal
check to determine if the part is functional. Connect the MCU
as shown in Figure 6 and monitor the output of port C bit 3 for
an oscillation of approximately 3Hz. ROM, RAM, TIMER,
Interrupts, I/O of Port A, Band C are checked by this capability .
•
RESETS
The MCU can be reset three ways; by initial power-up, by
the external reset input (RES) and by an optional internal
low voltage inhibit circuit, see Figure 7. All the I/O port are
initialized to input mode (DDRs are cleared) during reset.
During power-up, a minimum of 100 milliseconds is needed
before allowing the RES input to go "High".
This time allows the internal crystal oscillator to stabilize.
Connecting a capacitor to the l{ES input, as shown in Figure 8,
typically provides sufficient delay.
A, 40
A, 39
T
2 .21'F
A, 38
A4~
6 XTAL
C
+9V
A, 36
A, 35
EXTAL
A,
An
HD6805Ul *
8
34
~
TIMER (Resistor option)
B,~
~
V CC
J30n
r.:::J
9
J.3,? 11 'C blO
~31n r.:::JU 11
3,?J! ~ ~ 12
.WY..~:!
;Okn
v
10kn
~A
v v
10k n
~-,.::
JO}v~
vv
V cc =
vss =
RES Pin
NUM
B,
31
B, 30
B, 29
Co
BJ~
C,
B, 27
C,
B, 26
C,
B" 25
I!!Y 13
C.
14 C,
15 C.
16
C,
Pin 4
Pin 1
Refer to F ,gure 9 about crystal option
Figure 6 Self Check Connections
----------f"
Internal
Reset
Figure 7 Power Up and RES Timing
214
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------------HD6805U1
•
INTERNAL OSCILLATOR OPTIONS
The internal oscillator circuit is designed to require a minimum of external components. A crystal, a resistor, a jumper
wire, or an external signal may be used to generate a system
clock with various stability/cost tradeoff. A manufacturing
mask option is required to select either the crystal oscillator or
the RC oscillator circuit. The different connection methods are
shown in Figure 9. Crystal specifications are given in Figure 10.
A resistor selection graph is given in Figure 11.
2
RES
T ...
22"F
Part of
HD6805U1
MCU
Figure 8 Power Up Reset Delay Circuit
6
6 XTAL
XTAL
4 MHz c::::::J
max
EXTAL
EXTAL
HD6805U1
MCU
HD6805U1
MCU
Approximately 25% Accuracy
tcyc ~ 1.251Js typo
External Jumper
\""r__6....
XTAL
XTAL
R
External
Clock
Input
EXTAL
HD6805U1
MCU
EXTAL
Ex ternal Clock
ApprOXimately 15% Accuracy
Ex ternal ReSistor
CRYSTAL OPTIONS
RESISTOR OPTIONS
Figure 9
Internal OSCillator Options
C,
f\
XTAL~~EXTAL
~C~
6
AT
C.,
f
~
~
Cut Parallel Resonance Crystal
~
7 pF max.
4 MHz
HD6805U1
MCU
No
Connection
5
I I
\
vee ~ 5.25V
T A ~ 25'C
-
1\
>
'"
~
l.I..
RS~60llmax
~
~
~~
J'-..... r--
Figure 10 Crystal Parameters
10
15
20
25
30
35
40
45
50
ReSistance Ik!ll
Figure 11 TYPical ReSistor Selection Graph
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
21.5
HD6805U1--------------------------------------------------------------
1
7F
~I
~SP
O~DDR's
Stack
PC, X,A,CC
INT
CLR I NT Logic
FF ~ TOR
7F ~ Prescaler
7F ~ TCR
y
TIMER
Load PC From
Reset :$FFE, $FFF
Load PC From
SWI :$FFC, $FFD
INT:$FFA, $FFB
TIMER :$FF8,$FF9
Fetch
Instruction
Y
SWI
Execute
Instruction
Figure 12 Interrupt Processing Flowchart
Data
Direction
Register
Bit
Output
Data Bit
Output
State
Input to
MCU
0
0
0
3-State
Pin
1
Figure 13 Typical Port liD Circuitry
216
0
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------------------HD6805U1
•
INTERRUPTS
The CPU can be interrupted three different ways: through
the external interrupt (INT) input pin, the internal timer interrupt request, and a software interrupt instruction (SWI). When
any interrupt occurs, processing is suspended, the present CPU
state is pushed onto the stack, the interrupt bit (I) in the Condition Code Register is set, the address of the interrupt routine is
obtained from the appropriate interrupt vector address, and the
interrupt routine is executed. Stacking the CPU registers, setting
the I bit, and vector fetching requires 11 cycles. The interrupt
service routines normally end with a return from interrupt
(RTI) instruction which allows the CPU to resume processing of
the program prior to the interrupt. Table I provides a listing of
the interrupts, their priority, and the vector address that contain
the starting address of the appropriate interrupt routine.
A flowchart of the interrupt processing sequence is given
in Fig. 12.
Table 1 Interrupt Priorities
Priority
Vector Address
$FFE and $FFF
SWI
1
2
fNT
3
$FFA and $FFB
TIMER
4
$FF8 and $FF9
Interrupt
RES
$FFC and $FFD
outputs. Port A is CMOS compatible as outputs, and Port Band
C lines are CMOS compatible as inputs. Figure 14 provides some
examples of port connections.
•
INPUT
Port D can be used as either 8 TTL compatible inputs or
threshold input and 7 analog inputs pins. Fig. 15 (a) shows the
construction of port D. The Port D register at location $003
stores TTL compatible inputs, and those in location $007 store
the result of comparison Do to D6 inputs with D7 threshold
input. Port D has not only the conventional function as inputs
but also voltage-comparison function. Applying the latter, can
easily check that 7 analog input electric potential max. exceeds
the limit with the construction shown in Fig. 15 (b). Also, using
one output pin of MCU, after external capacity is discharged
at the preset state, charge the CR circuit of long enough time
constant, apply the charging curve to the D7 pin. The construction described above is shown in Fig. 15 (c). The compared
result of Do to D6 is regularly monitored, which gives the
analog input electric potential applied to Do to D6 pins from
inverted time. This method enables 7 inputs to be converted
from analog to digital. Furthermore, combination of two functions gives 3 level voltages from Do to D6. Fig. 15 (d) provides
the example when VTH is set to 3.5V.
•
•
INPUT/OUTPUT
There are 24 input/output pins. All pins are programmable
as either inputs or outputs under software control of the corresponding Data Direction Register (DDR). When programmed
as outputs, the latched output data is readable as iriput data,
regardless of the logic levels at the output pin due to output
loading (see Fig. 13). When Port B is programmed for outputs,
it is capable of sinking lOrnA on each pin (VOL = 1V max).
All input/output lines are TTL compatible as both inputs and
Port A
BIT MANIPULATION
The MCU has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 16
illustrates the usefulness of the bit manipulation and test
Port B
Port A Programmed as output(s) ,driving CMOS and TT L Load directly.
Port B Programmed as output(s),driving Darlington base directly.
(b)
(a)
+V
+V
R
CMOS Inverter
Port C
Port B
10 mA max
C7
Port B Programmed as output(s),d"vlng LED(s) directly.
(e)
Port C Programmed as output(s), driving CMOS loads, using
external pull-up
Id)
Figure 14 Typical Port Connections
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
217
HD6805U1---------------------------------------------------------------vides turn-on of the TRIAC within 14 microseconds of the zero
crossing. The timer could also be incorporated to provide turnon at some later time which would permit pulse-width modulation of the controlled power.
instructions. Assume that bit 0 of port A is connected to a zero
crossing detector circuit and that bit I of port A is connected to
the trigger of a TRIAC which power the controlled hardware.
This program, which uses only seven ROM locations, pro-
$003 Read
Input Port
(0 0 - D 6 )
Internal Bus
(BitO - Bit6)
+
$003 Read
Internal Bus
(Bit 7)
(a) The logic configuration of Port D
Port
Co
C
I-D,,;,7_ _ _ Reference Level
D
r-_.- - - Analog Input 6
D,
Port
D
Port
D
D.
t---:--Analog Input 6
Do
I-----Analog Input 0
Analog Input 0
(b) Seven analog inputs and a reference level input of Port D
D,
3 Levels Input 6
l
D
Do
~
o,~
(c) Application to AID convertor
V TH (; 3.5V)
O.
Port
Co
Input
Voltage
($003)
($007)
OV - 0.8V
0
0
2.0V - 3.3V
1
0
3.7V - Vee
1
1
3 Levels Input 0
(d) Application to 3 levels input
Figure 15 Configuration and Appl ication of Port D
218
_HITACftl
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------------HD6805U1
SELF 1
BRClR 0, PORT A, SELF 1
BSET 1, PORT A
BClR 1, PORT A
Figure 16 Bit Manipulation Example
• ADDRESSING MODES
The CPV has ten addressing modes available for use by the
programmer. They are explained and .illustrated briefly in the
following paragraphs.
• Immediate
Refer to Figure 17. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
• Direct
Refer to Figure 18. In direct addressing, the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.
• Extended
Refer to Figure 19. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instructions are three bytes long.
• Relative
Refer to Figure 20. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA=(pC)+2+Rel. Rei is the contents
of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to somewhere within the
range of +129 bytes to -127 of the present instruction. These
instructions are two bytes long.
• Indexed (No Offset)
Refer to Figure 21. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and their EA is the contents of the index register.
• Indexed (8-bit Offsetl
Refer to Figure 22. The EA is calculated by adding the
contents of the byte following the opcode to the contents of
the index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.
• Indexed (16-bit Offset)
Refer to Figure 23. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.
• Bit Set/Clear
Refer to Figure 24. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.
• Bit Test and Branch
Refer to Figure 25. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
($OO-$FF) and branch to any location relative to the Pc. The
byte to be tested is addressed by the byte following the opcode.
The individual bit within that byte to be tested is addressed by
the lower three bits of the opcode. The third byte is the relative
address to be added to the program counter if the branch condition is met. These instructions are three bytes long. The value of
the bit tested is written to the carry bit in the condition code
register.
• Implied
Refer to Figure 26. The implied mode of addressing has no
EA. All the information necessary to execute an instruction is
contained in the opcode. Direct operations on the accumulator
and the index register are included in this mode of addressing.
In addition, control instructions such as SWI, RTI belong to this
group. All implied addressing instructions are one byte long.
•
INSTRUCTION SET
The MCV has a set of 59 basic instructions. They can be
divided into five different types: register/memory, read/modify/
write, branch, bit manipulation, and control. The following
paragraphs briefly explain each type. All the instructions within
a given type are presented in individual tables.
• Register/Memory Instructions
Most of these instructions use two operands. One operand is
either the accumulator or the index register. The other operand
is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR)
instructions have no register operand. Refer to Table 2.
• Read/Modity/Write Instructions
These instructions read a memory location or a register,
modify or test its contents, and write the modified value back
to memory or to the register. The test for negative or zero
(TST) instruction is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
3.
• Branch Instructions
The branch instructions cause a branch from the program
when a certain condition is met. Refer to Table 4.
• Bit Manipulation Instructions
These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 5.
• Control Instructions
The control instructions control the MCV operations during
program execution. Refer to Table 6.
• Alphabetical Listing
The complete instruction set is given in alphabetical order in
Table 7.
• Opcode Map
Table 8 is an opcade map for the instructions used on the
MeV.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
219
HD6805U1-------------------------------------------------------------
i
I
I
~
I
A
F8
Index
I
eq
Stack Point
I
I
PROG LOA #$F8 05BE
A6
~------t
05BF
F8
Prog Count
05CO
CC
I
I
§
I
I
I
Figure 17
t
lEA
Memory
I
i
I
I
I
I
I
FCB
32
004B
l
004B
/
Adder
I
I
I
I
CAT
Immediate Addressing Example
I
t
I
~
A
ooto
20
J
L
20
I
Index Reg
I
PROG
LOA
CA T
I
I
0520
B6
052E
4B
Stack Point
I
I
Prog Count
I
052F
CC
~
II
I
I
I'
'
I
I
Figure 18 Direct Addressing Example
220
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
I
I
I
---------------------------------------------------------------HD6805U1
Memory
i
I
I
§
PROG
LOA
CAT
0000
A
::§J--------'
I
I
CAT
FCB
40
64
06E5
Index Reg
Stack Point
I
I
Prog Count
.....------4
40
040C
CC
Figure 19
Extended Addressing Example
Memory
§
A
Index Reg
Stack Point
I
I
PROG
BEQ
PROG2
04A7
27
04A8
18
0000
§
I
I
I
Figure 20
Relative Addressing Example
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
221
HD6805U1--------------------------------------------------------------
A
TABL
FCC
t Lit 00B8
4C
4C
49
Index Reg
B8
I
PROG
LOA
I
Stack Point
05F4~
X
Prog Count
05F5
CC
§
Figure 21
Indexed (No Offset) Addressing Example
t
lEA
Memory
i
i
I
i
i
I
TABL
FCB
#BF
0089
BF
FCB
#86
008A
86
FCB
#OB
008B
DB
FCB
#CF
008C
CF
i
I
/
I
008C
t
Adder
~
A
1
I
I
I
I
I
CF
I
Index Reg
03
I
Stack Point
PROG
LOA
TAB L X 075B
E6
075C
89
I
I
I
0750
CC
I
§
,I
Figure 22
222
I
Prog Count
Indexed (8·Bit Offset) Addressing Example
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
I
-----------------------------------------------------------------HD6805U1
1
EA
I
Melory
i
I
I
I
I
i
~
~
I
PROG
lDA TAB L. X 0692
0693
0694
t
Adder
~
A
I
f
077E
BF
#86
077F
86
FCB
#DB
0780
DB
FCB
#CF
0781
CF
Figure 23
I
I
Prog Count
I
I
I
0695
CC
i
#BF
02
I
I
07
FCB
I
Stack Point
7E
FCB
DB
Index Reg
I
i
TABl
/
I
0780
I
Indexed (16-Bit Offset) Addressing Example
Memory
PORT B
EQU
BF
0001
A
I
I
0000
Index Reg
PROG BClR 6. PORT B
058F
1D
0590
01
Stack Point
Prog Count
0591
I
I
CC
~
I
I
I
Figure 24
Bit Set/Clear Addressing Example
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
223
HD6805U1---------------------------------------------------------------lEA
Memlry
i
I
i
i
i
PORT C
EQU
0002
t
I
Fa
0002
2
I
'/
Adder
J
'"
f
Bit
2
0000
,
I
i
i
PROG BRCLR 2. PORT C. PROG 2
0574
I
02
0576
1D
,
---f
Index Reg
I
I
Stack POint
I
I
0000
0594
J
CC
~
OR
i
~ '"
I
I
I
Prog Count
05
0575
A
~
j
I
I
Adder
I
C
/
i
Figure 25 Bit Test and Branch Addressing Example
Memory
i
I
I
I
~
i
i
i
I
,
PROG
TAX
05BA
A
E5
Index Reg
E5
i
8
Prog Count
05B8
CC
i
I
~
Figure 26 Implied Addressing Example
224
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
J
-----------------------------------------------------------------HD6805U1
Table 2
Register/Memory Instructions
Addressing Modes
Function
Mnemonic
Immediate
Indexed
(No Offset)
Extended
Direct
Op
#
#
Bytes Cycles Code
Op
Op
#
#
Op
#
#
Code Bytes Cycles Code Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
Indexed
(16-Bit Offset)
#
Op
#
Bytes Cycles Code
#
#
Bytes Cycles
Load A from Memory
LOA
A6
2
2
B6
2
4
C6
3
5
F6
1
4
E6
2
5
06
3
6
Load X from Memory
LOX
AE
2
2
BE
2
4
CE
3
5
FE
1
4
EE
2
5
DE
3
6
7
Store A in Memory
STA
-
B7
2
5
C7
3
6
F7
1
5
E7
2
6
07
3
STX
-
-
• Store X in Memory
-
-
BF
2
5
CF
3
6
FF
1
5
EF
2
6
OF
3
7
Add Mdmory to A
ADD
AB
2
2
BB
2
4
CB
3
5
FB
1
4
EB
2
5
DB
3
6
Add Memory and
Carry to A
AOC
A9
2
2
B9
2
4
C9
3
5
F9
1
4
E9
2
5
09
3
6
4
EO
6
Subtract Memory
SUB
AO
2
2
BO
2
4
CO
3
5
FO
1
2
5
DO
3
Subtract Memory from
A with Borrow
SBC
A2
2
2
82
2
4
C2
3
5
F2
1
4
E2
2
5
02
3
6
AND Memory to A
AND
A4
2
2
84
2
4
C4
3
5
F4
1
4
E4
2
5
04
3
6
OR Memory with A
ORA
AA
2
2
BA
2
4
CA
3
5
FA
1
4
EA
2
5
OA
3
6
Exclusive OR Memory
with A
EOR
A8
2
2
B8
2
4
C8
3
5
FB
1
4
EB
2
5
DB
3
6
Arith".,etic Compare A
with Memory
CMP
Al
2
2
Bl
2
4
Cl
3
5
Fl
1
4
El
2
5
01
3
6
Arithmetic Compare X
with Memory
2
2
B3
2
4
C3
3
5
F3
1
4
E3
2
5
03
3
6
6
CPX
A3
Bit Test Memory with A
(Logical Compare)
BIT
AS
2
2
B5
2
4
C5
3
5
F5
1
4
E5
2
5
05
3
Jump Unconditional
JMP
-
2
3
CC
3
4
FC
1
3
EC
2
4
DC
3
5
JSR
-
-
BC
Jump to Subroutine
-
BO
2
7
CD
3
B
FO
1
7
ED
2
B
DO
3
9
Table 3
Read/ModifylWrite Instructions
Addressing Modes
Function
Implied (A)
Mnemonic
Op
Code
#
Implied (X)
#
Op
Bytes Cycles Code
Direct
Op
#
#
Bytes Cycles Code
#
#
Indexed
Indexed
(No Offset)
(8-Bit Offset)
Op
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
#
#
Bytes Cycles
Increment
INC
4C
1
4
5C
1
4
3C
2
6
7C
1
6
6C
2
Decrement
DEC
4A
1
4
5A
1
4
3A
2
6
7A
1
6
6A
2
7
Clear
CLR
4F
1
4
5F
1
4
3F
2
6
7F
1
6
6F
2
7
Complement
COM
43
1
4
53
1
4
33
2
6
73
1
6
63
2
7
Negate
(2's Complement)
NEG
40
1
4
50
1
4
30
2
6
70
1
6
60
2
7
7
7
Rotate Left Thru Carry
ROL
49
1
4
59
1
4
39
2
6
79
1
6
69
2
Rotate Right Thru Carry
ROR
46
1
4
56
1
4
36
2
6
76
1
6
66
2
7
Logical Shift Left
LSL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
Logical Shift Right
LSR
44
1
4
54
1
4
34
2
6
74
1
6
64
2
7
Arithmetic Shift Right
ASR
47
1
4
57
1
4
37
2
6
77
1
6
67
2
7
Arithmetic Shift Left
ASL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
4D
1
50
1
3D
2
70
1
6
60
2
7
Test for Negative or
Zero
TST
4
4
6
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
225
HD6805Ul------------------------------------------------_____________
Table 4 Branch Instructions
Relative Addressing Mode
Function
Mnemonic
Op
Code
#
#
Bytes
Cycles
4
Branch Always
BRA
20
2
Branch Never
BRN
21
2
4
Branch IF Higher
BHI
22
2
4
Branch I F lower or Same
BlS
23
2
4
BCC
(BHS)
24
2
4
24
2
4
Branch I F Carry Set
BCS
25
2
4
(Branch IF lower)
(BlO)
25
2
4
Branch I F Carry Clear
(Branch IF Higher or Same)
Branch I F Not Equal
BNE
26
2
4
Branch I F Equal
BEQ
27
2
4
Branch I F Half Carry Clear
BHCC
28
2
4
Branch I F Half Carry Set
BHCS
29
2
4
Branch IF Plus
BPl
2A
2
4
Branch IF Minus
BMI
2B
2
4
Branch I F Interrupt Mask Bit is Clear
BMC
2C
2
4
Branch I F Interrupt Mask Bit is Set
BMS
20
2
4
Branch I F Interrupt Line is low
Bil
2E
2
4
Branch IF Interrupt Line is High
BIH
2F
2
4
Branch to Subroutine
BSR
AO
2
8
Table 5 Bit Manipulation Instructions
Addressing Modes
Function
Mnemonic
Bit Set/Clear
Op
Code
Bit Test and Branch
#
#
Bytes
Branch IF Bit n is set
BRSET n (n=O ..... 7)
-
-
Branch I F Bit n is clear
BRClR n (n=O .... .7)
-
-
#
#
Cycles
Op
Code
Bytes
Cycles
-
2-n
3
10
01+2-n
3
10
Set Bit n
BSET n (n=O ..... 7)
10+2-n
2
7
-
-
-
Clear bit n
BClR n (n=O ..... 7)
11+2-n
2
7
-
-
-
Table 6 Control Instructions
Implied
Function
226
Mnemonic
Op
Code
#
#
Bytes
Cycles
Transfer A to X
TAX
97
1
2
Transfer X to A
TXA
9F
1
2
Set Carry Bit
SEC
99
1
2
Clear Carry Bit
ClC
98
1
2
Set Interrupt Mask Bit
SEI
9B
1
2
Clear Interrupt Mask Bit
CLI
9A
1
2
Software Interrupt
SWI
83
1
11
Return from Subroutine
RTS
81
1
6
Return from Interrupt
RTI
80
1
9
Reset Stack Pointer
RSP
9C
1
2
No·Operation
NOP
90
1
2
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------HD6805U1
Table 7 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
Direct
Extended
Relative
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
Setl
Clear
Bit
Test &
Branch
H
I
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
ADC
x
x
x
ADD
x
x
x
x
x
x
1\
AND
x
x
x
x
x
x
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ASl
x
x
x
x
ASR
x
x
x
x
x
BCC
x
BClR
-
Bit
BCS
x
BEQ
x
BHCC
x
BHCS
x
BHI
x
BHS
x
BIH
x
Bil
x
x
BIT
x
x
x
BlO
x
BlS
x
BMC
x
BMI
x
BMS
x
BNE
x
BPl
x
BRA
x
BRN
x
x
x
BRClR
x
BRSET
x
x
BSET
x
BSR
CLC
x
CLI
x
ClR
x
CMP
COM
DEC
x
x
x
x
x
CPX
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
EOR
x
x
x
x
x
x
x
x
x
JMP
x
x
x
x
x
JSR
x
x
x
x
x
x
x
x
x
x
x
x
x
x
INC
lDA
lDX
x
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
x
Z
C
1\
1\
1\
1\
1\
1\
1\
1\
•
1\
1\
1\
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1\
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• 1\
• 1\
• •
• •
• 0
• •
1 •
N
0
1\
1\
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1
•
•
1\ 1\ •
• • • •
• • • •
• 1\ 1\ •
• 1\ 1\ •
•
•
(to be continued)
C
1\
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
227
HD6805U1-------------------------------------------------------------Table 7 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
Relative
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
LSL
x
x
x
x
LSR
x
x
x
x
NEG
x
x
x
x
NOP
x
x
ORA
ROL
ROR
x
x
RSP
x
RTI
x
RTS
x
x
SBC
SEC
SEI
x
x
x
x
x
x
x
x
x
x
x
Bit
Setl
Clear
x
x
x
x
x
x
x
x
STA
x
x
x
x
STX
x
x
x
x
x
x
x
x
x
x
x
x
SUB
SWI
x
TAX
x
TST
x
TXA
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I'. Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
228
Direct
Extended
x
x
C
/\
•
?
Bit
Test &,
Branch
H
I
N
Z
C
•
•
•
•
•
•
•
•
•
/\
/\
/\
?
?
• 0 /\ /\
• /\ /\ /\
• • • •
• /\ /\ •
• /\ /\ /\
• /\ /\ /\
• • • •
?
?
?
• • • • •
• • /\ /\ /\
• • • • 1
• 1 • • •
• • /\ /\ •
• • /\ /\ •
•
•
•
•
•
• /\ /\ /\
1 • • •
• • • •
• /\ /\ •
• • • •
CarrY/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
\ Hitachi America Ltd_ • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD6805U1
Table 8
Bit Manipulation
Test &
Branch
Setl
Clear
0
1
2
BRSETO
BSETO
BAA
Control
Aead/Modify/Write
Branch
Ael
Opcode Map
DIA
3
I
A
I
X
I
4
I
5
I
I
,Xl
6
I
I
IMP
IMP
IMM
I
DIA
7
8
9
A
I
B
5
BRCLR2
BCLR2
BCS
6
BRSET3
BSET3
BNE
ROR
-
-
7
BRCLR3
BCLR3
BEQ
ASR
-
TAX
8 BRSET4
BSET4
BHCC
LSL/ASL
-
CLC
0
NEG
1
BRCLRO
BCLRO
BRN
-
2
BRSETl
BSETl
BHI
-
Register /Memory
,XO
ATI'
RTS'
-
3
BRCLRl
BCLRl
BLS
COM
4
BRSET2
BSET2
BCC
LSR
SWI'
-
-
I EXT I ,X2 I Xl I ,XO
I
C
I
0
I
E
I
F
SUB
-
I
+-
CMP
1
SBC
2
CPX
3
L
AND
4
o
BIT
5 W
LOA
6
STA(+l)
7
EOR
8
9
BRCLR4
BCLR4
BHCS
ROL
-
SEC
AOC
9
A
BRSET5
BSET5
BPL
DEC
CLI
ORA
A
B BRCLR5
BCLR5
BMI
-
-
SEI
C BRSET6
BSET6
BMC
INC
-
RSP
D BRCLR6
BCLR6
BMS
TST
-
NOP
E BRSET7
BSET7
BIL
-
-
F BRCLR7
BCLR7
BIH
-
TXA
-
1/'
1/2
2/2
3/10
(NOTE)
2/7
2/4
CLR
2/6
I 1/4
I 1/4
I 2/7
I 1/6
-
1
BSR'I
,
T 2/4
AOD
B
JMP(-l)
C
JSR(+3)
D
LOX
E
F
STX(+l)
, 3/5
HIGH
0
I 3/6
I 2/5
I 1/4
1. Undefined opcodes are marked with "-".
2. The number at the bottom of each column denote the number of bytes and the number of cycles required (Bytes/Cycles).
Mnemonics followed by a "," require a different number of cycles as follows:
RTI
9
RTS
6
SWill
BSR
8
3. (
indicate that the number in parenthesis must be added to the cycle count for that instruction.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
229
HD6805V1-------------MCU (Microcomputer
Unit)
The HD6805Vl is the 8-bit Microcomputer Unit (MCU)
which contains a CPU, on-chip clock, ROM, RAM, I/O and
timer. It is designed for the user who needs an economical
microcomputer with the proven capabilities of the HD6800based instruction set.
The following are some of the hardware and software highlights of the MCU.
HD6805V1P
•
•
•
•
•
•
•
•
HARDWARE FEATURES
8·Bit Architecture
96 Bytes of RAM
Memory Mapped I/O
3848 Bytes of User ROM
Internal 8-Bit Timer with 7·Bit Prescaler
Vectored Interrupts - External and Timer
24 I/O Ports + 8 Input Port
(8 Lines LED Compatible; 7 Bits Comparator Inputs)
• On-Chip Clock Circuit
• Self·Check Mode.
• Master Reset
• Low Voltage Inhibit
• Easy for System Development and Debugging
• 5 Vdc Single Supply
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Function
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible Instruction Set with MC6805P2
•
BLOCK DIAGRAM
(DP-40)
•
PIN ARRANGEMENT
0
A,
A,
As
A.
A,
A,
A,
Ao
B,
HD6805Vl
c,
B.
C.
Cs
C,
C,
Bo
D,
D,
Ds
CPU
Indell
Register
A.
A,
Port
A,
I/O
Lmes
A.
As
A
A,
::
ContrOl
Data
Dir.
Pon
B
Reg
Reg
D.
Condition
POri
A
Data
Dir
Reg
Reg
Cod.
S
(Top View)
Register
c.
g:
Po.t
~~
1:0
Cs
Lines
C.
C,
D.
D,
D,
D.
0
D.
Input
Os
Lmes
b.
D~ 'VTIot
230
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------------------HD6805V1
• ABSOLUTE MAXIMUM RATINGS
Vee *
Input Voltage (EXCEPT TIMER)
V in *
Input Voltage (TIMER)
Operating Temperature
•
With respect to
(NOTE)
-0.3 - +7.0
V
-0.3 - +7.0
V
V
-0.3 - +12.0
o
T cpr
T stg
Storage Temperature
Unit
Value
Symbol
Item
Supply Voltage
°c
°c
-+70
- 55 - +150
Vss (SYSTEM GND)
Permanent LSI damage may occur If maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc=5.25V ± O.5V. Vss=GND. Ta=o-+70°C. unless otherwise noted.)
Item
Input "High" Voltage
Symbol
min typ
-
Vee
V
INT
3.0
-
Vee
V
2.0
-
Vee
V
2.0
-
Vee
V
9.0
-
11.0
V
-0.3
-
0.8
V
V ,H
Timer Mode
Self·Check Mode
RES
INT
Input "Low" Voltage
max Unit
4.0
All Other
Input "High" Voltage (Timer)
Test Condition
RES
V ,L
EXTAL(Crystal Mode)
All Other
-0.3
-
0.8
V
-0.3
-
0.6
V
-0.3
-
0.8
-
700
V
PD
-
Low Voltage Recover
LVR
-
-
4.75
V
Low Voltage Inhibit
LVI
-
4.0
-
V
Power Dissipation
TIMER
INT
I nput Leak Current
I'L
V,n=0.4V-Vee
XTAL(Crystal Mode)
mW
-20
-
20
-50
-
50
J.lA
0
J.lA
-1200 -
J.lA
• AC CHARACTERISTICS (Vcc=5.25V ± O.5V. Vss=GND. Ta=O - +70°C. unless otherwise noted.)
Item
Symbol
Test Condition
min
typ
max Unit
Clock Frequency
f el
0.4
-
4.0
Cycle Time
t eve
1.0
-
10
J.ls
Oscillation Frequency (External Resistor Mode)
tEXT
3.4
-
MHz
TNT Pulse Width
t,wL
t eve t
250
-
-
ns
RES Pulse Width
tRWL
t eve +
250
-
-
ns
TIMER Pulse Width
t TWL
t eve +
250
-
-
ns
-
-
100
ms
100
-
-
ms
-
-
35
pF
-
-
10
pF
Oscillation Start-up Time (Crystal Mode)
Delay Time Reset
Input Capacitance
I
I
XTAL
All Other
tose
-
Rep= 15.0kSl±1 %
C L=22pF±20%.
Rs=60S2 max.
tRHL
External Cap. = 2.2).iF
C in
V,n=OV
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
MHz
231
HD6805V1--------------------------------------------------------------_
• PORT ELECTRICAL CHARACTERISTICS (Vee
Item
= 5.25V ± 0.5V, VSS = GND
Port B
max
Unit
= -10J,LA
IOH = -100J,LA
IOH = -200J,LA
IOH = -1 mA
IOH = -100J,LA
IOL = 1.6. mA
---=,
IOL = 3.2mA
IOL = 10 mA
3.5
-
-
V
-
-
0.4
V
-
0.4
V
-
-
1.0
V
VIH
2.0
Vee
V
VIL
-0.3
IOH
VOH
Port A and C
Input "High" Voltage
Input "Low" Voltage
Port B
Port A, B, C,
and D*
VOL
IlL
Port B, C,
and D
2.4
2.4
1.5
2.4
-500
Yin
= 0.8V
= 2V
-300
-
Yin
= O.4V '" Vee
- 20
-
-
V:rH+0.2
VTH-0.2
Yin
Port A
Input Leak Current
Input "High" Voltage
Port D**
(Do'" D 6 )
Input "Low" Voltage
Port D**
(Do'" D 6 )
VIL
-
Port D**(D7)
VTH
0
Threshold Voltage
..
* Port D as digital Input
** Port D as analog input
VIH
-
V
V
V
V
0.8
V
-
J,LA
-
J,LA
20
J,LA
-
V
-
V
0.8 xVec
V
TTL Equiv. (Port A and C)
TTL Equiv. (Port B)
Ii
unless otherwise noted.)
typ
Port C
Output "Low" Voltage
= 0 '" +70°C
min
Port A
Output "High" Voltage
Ta
Test Condition
Symbol
Vee
= 3.2 mA
li=
Test Point
Test Pomt
1.6mA
2.4kH
Vi
Vi
40 pF
(NOTE)
30 pF
12 kl!
24 k!!
1. Load capacItance includes the floating capacitance of H,e probe and the jig etc.
2. All diodes are 152074(/3) or equivalent.
Figure 1 Bus Timing Test Loads
•
SIGNAL DESCRIPTION
The input and output signals for the MCU, shown in PIN
ARRANGEMENT, are described in the following paragraphs.
•
Vee and Vss
Power is supplied to the MeU using these two pins. Vee
is +S.2SY ±O.SV. Vss is the ground connection.
•
INT
This pin provides the capability for asynchronously applying
an external interrupt to the MCU. Refer to INTERRUPTS for
additional information.
• XT AL and EXT AL
These pins provide connections for the on-chip clock circuit.
A crystal (AT cut, 4 MHz maximum), a resistor or an external
signal can be connected to these pins to provide a system clock
with various stability/cost tradeoffs. Refer to INTERNAL OSCILLATOR OPTIONS for recommendations about these inputs.
232
•
TIMER
This pin allows an external input to be used to decrement
the internal timer circuitry. Refer to TIMER for additional
information about the timer circuitry.
• RES
This pin allows resetting of the MeU at times other than
the automatic resetting capability already in the MeU. Refer
to RESETS for additional information.
•
NUM
This pin is not for user application and should be connected
to VSS.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------------HD6805Vl
•
• MEMORY
The MCU memory is configured as shown in Figure 2. During
the processing of an interrupt, the contents of the CPU regi·
sters are pushed onto the stack in the order shown in Figure 3.
Since the stack pointer decrements during pushes, the low order
byte (PCL) of the program counter is stacked first; then the
high order four bits (PCH) are stacked. This ensures that the
program counter is loaded correctly as the stack pointer in·
crements when it pulls data from the stack. A subroutine call
will cause only the program counter (pCH, PCL) contents to
be pushed onto the stack.
Input/Output Lines (Ao - A 7 , Bo - B 7 , Co - C 7 )
These 24 lines are arranged into three 8·bit ports (A, Band
C). All lines are programmable as either inputs or outputs under
software control of the Data Direction Register (DDR). Refer to
INPUT/OUTPUT for additional information.
•
Input Lines (Do - 0 7 )
These are 8·bit input lines, which has two functions. Firstly,
these are TTL compatible inputs, in location $003. The other
function is 7 bits comparator in location $007. Refer to INPUT
for more details.
Caution: - Self Test ROM Address Area
Self test ROM locations can not be used for a user program.
If the user's program is in this location, it will be removed when
manufacturing mask for production.
o
765432
000
$000
I/O Ports Timer
RAM (128 Bytes)
$07F
$080
127
128
ROM
1
Port B
$001
2
Port C
S002
$F7F
$F80
S003**
3
Port D (digital)
4
Port A DDR
$004*
5
Port B DDR
S005*
S006*
Port C DDR
$007**
Port D (analog)
7
3967
3968
$000
Port A
6
(3840 Bytes)
0
0
8
Timer Data Reg.
$008
9
Timer eTR L Reg.
S009
$OOA
10
Not Used (22 Bytes)
Self·test
4087
4088
31
32
$FF7
$FFS
Interrupt
Vectors
(S Bytes)
Figure 2
n-4
n-3
5
1 1 11
4
Accumu lator
MCU Memory Configuration
0
0
Condition
Code Register
$07F
Write only registers
•• Read only register
$FFF
6
Star
.
12'A
4095
Pu II
n+
I Accumulator
A
1
0
I
X
n+2
11
n-2
n-1
I ndex Register
1 1 1 11
PCL'
PCH'
SOl F
SO 20
RAM (96 Bytes)
n+3
PC
11
n+4
Index Register
0
5 4
0 0 0 0 0
1 1 1 1 1 1 11 11
I
I
Program Counter
0
SP
n+5
Stack POinter
Condition Code Register
Push
, For subroutine calls, only PCH and PCl are stacked.
Carry/Borrow
Figure 3 Interrupt Stacking Order
Zero
Negative
Interrupt Mask
Half Carry
Figure 4
Programming Model
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
233
HD6805V1-------------------------------------------------------------•
REGISTERS
The CPU has five registers available to the programmer.
They are shown in Figure 4 and are explained in the following
paragraphs.
• Accumulator (A)
The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.
• Index Register (X)
The index register is an 8-bit register used for the indexed
addressing mode. It contains an 8-bit address that may be added
to an offset 'value to create an effective address. The index
register can also be used for limited calculations and data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
• Program Counter (PC)
The program counter is a 12-bit register that contains the
address of the next instruction to be executed.
• Stack Pointer (SP)
The stack pointer is a 12-bit register that contains the address
of the next free location on the stack. Initially, the stack pointer is set to location $07F and is decremented as data is being
pushed onto the stack and incremented as data is being pulled
from the stack. The six most significant bits of the stack pointer
are permanently set to 0000011. During an MCU reset or the
reset stack pointer (RSP) instruction, the stack pointer is set
to location $07F. Subroutines and interrupts may be nested
down to location $061 which allows the programmer to use up
to 15 levels of subroutine calls.
• Condition Code Register (CC)
The condition code register is a S-bit register in which each
bit is used to indicate or flag the r~sults of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each individual condition code register bit is explained in the following
paragraphs.
Half Carry (H)
Used during arithmetic operations (ADD and AOC) to
indicate that a carry occurred between bits 3 and 4.
Interrupt (I)
This bit is set to mask the timer and external interrupt (INT).
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.
Negative (N)
Used to indicate that the result of the last arithmetic, logical
or data manipulation was negative (bit 7 in result equal to a
logical one).
Zero (Z)
Used to indicate that the result of the last arithmetic, logical
or data manipulation was zero.
Carry/Borrow (C)
Used to indicate that a carry or borrow out of the arithmetic
logic unit (ALU) occurred during the last arithmetic operation.
This bit is also affected during bit test and branch instructions,
shifts, and rotates.
• TIMER
The MCU timer circuitry is shown in Figure S. The 8-bit
counter, the Timer Data Register (TDR), is loaded under program control and counts down toward zero as soon as the clock
input is applied. When the timer reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register (TCR) is
set. The CPU responds to this interrupt by saving the present
CPU state on the stack, fetching the timer interrupt vector from
locations $FF8 and $FF9 and executing the interrupt routine.
The timer interrupt can be masked by setting the timer interrupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in the
Condition Code Register also prevents a timer interrupt from
being processed.
The clock input to the timer can be from an external source
applied to the TIMER input pin or it can be the internal cP"
signal. When the internal CP2 signal is selected as the input
source, the node a is connected to b (see Fig. 5). In case of the
external source, the node b connects with c. When the CP2 signal
is used as the source, the clock signal is input to the prescaler
while the TIMER input is "High". The source of the clock input
is one of the options that has to be speCified before manufacture of the MCU. A prescaler option can be applied to the clock
input that extends the timing interval up to a maximum of 128
"',
(Internal)
Timer
Input
Pin
,.-----,
I
I
I
I
I
I
IL _____ JI
Manufactu ring
Mask Options
Write
Read
Figure 5 Timer Block 0 iagram
234
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------------HD6805V1
counts before decrementing the counter (TDR). The timer continues to count past zero, falling through to $FF from zero and
then continuing the count. Thus, the counter (TDR) can be read
at any time by reading the TDR. This allows a program to determine the length of time since a timer interrupt has occurred and
not disturb the counting process.
The TDR is 8-bit Read/Write Register in location $008.
At power-up or reset, the TDR and the prescaler are initialized
with all logical ones.
The Timer Interrupt Request bit (bit 7 of the TCR) is set by
hardware when timer count reaches zero, and is cleared by program or by hardware reset. The bit 6 of the TCR is writable by
program. Both of those bits can be read by CPU.
(NOTE) If the MCU Timer is not used, the TIMER input pin
must be grounded.
2-
INT
2
RES
•
SELF CHECK
The self-check capability of the MCU provides an internal
check to determine if the part is functional. Connect the MCU
as shown in Figure 6 and monitor the output of port C bit 3 for
an oscillation of approximately 3Hz. ROM, RAM, TIMER,
Interrupts, I/O of Port A, Band C are checked by this capability.
• RESETS
The MCU can be reset three ways; by initial power-up, by
the external reset input (RES) and by an optional internal
low voltage inhibit circuit, see Figure 7. All the I/O port are
initialized to input mode (DDRs are cleared) during reset.
During power-up, a minimum of 100 milliseconds is needed
before allowing th.e RES input to go "High".
This time allows the internal crystal oscillator to stabilize.
Connecting a capacitor to the RES input, as shown in Figure 8,
typically provides sufficient delay.
A, 40
A, 39
T
A, 38
A.~
2 2IJF
.
C
XTAL
EXTAL
+9V
8
A., 36
A,
3S
A,
34
An
HD6805V1.
~
TIMER (Resistor option)
B,~
7 NUM
~
vcc
330n
...A A
r.:
9
.J..3~~1 ~ CJ\10
_pin
Co
B.,~
C,
B, 27
B, 26
B" 25
13
10kn
14
c.
c,
~o:n\l
15
Jo:r/
C,
16
C,
v
• Refer to F, gure 9
P,n 4
V cc
=
vss
= Pin 1
RES Pin
B. 29
C,
';~k~
A
31
B, 30
r.: ~11 c,
j30~1 ~ Ie, 12
'IV v
\!:!I
A
B.
about crystal option
Figure 6 Self Check Connections
--------------~
Internal
Reset
Figure 7 Power Up and RES Timing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
235
HD6805V1---------------------------------------------------------------•
INTERNAL OSCILLATOR OPTIONS
The internal oscillator circuit is designed to require a minimum of external components. A crystal, a resistor, a jumper
wire, or an external signal may be used to generate a system
clock with various stability/cost tradeoff. A manufacturing
mask option is required to select either the crystal oscillator or
the RC oscillator circuit. The different connection methods are
shown in Figure 9. Crystal specifications are given in Figure 10.
A resistor selection graph is given in Figure 11.
2
Part of
HD6805V1
MCU
Figure 8 Power Up Reset Delay Circuit
6 XTAL
6 XTAL
4 MHz
max
c:J
HD6805V1
5 EXTAL
5 EXTAL
HD6805V1
Crystal
Approximately 25% Accuracy
tcyc = 1.25 /olS typo
External Jumper
XTAL
6 XTAL
R
External
Clock
Input
MCU
MCU
EXTAL
HD6805V1
5 EXTAL
MCU
HD6805V1
MCU
No
Connection
External Clock
Approximately 15% Accuracy
External Resistor
CRYSTAL OPTIONS
RESISTOR OPTIONS
Figure 9 Internal Oscillator Options
5
,
f\
C,
XTAL~~EXTAL
6
~C~
4
\
5
C
Q>
:l
C" = 7 pF max.
1= 4 MHz
~
u.
i"-.
Rs = 60l! max
Figure 10 Crystal Parameters
o
10
15
20
'"
25
~ I'-....
30
i'--. t'35
40
Resistance (kl1)
Figure 11 Typical Resistor Selection Graph
236
_I
1\
'\
>
u
AT - Cut Parallel Resonance Crystal
1
Vee = 5.25V
T A = 25°C -
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
45
50
----------------------------------------------------------------HD6805V1
1 -> I
7F ->SP
Stack
PC,X,A,CC
o ->DDR's
CLR TNT Logic
FF ->TDR
7 F -> Prescaler
7F -> TCR
Y
TIMER
Load PC From
SWI :$FFC, $FFD
il'iff:$FFA, $FFB
TIMER :$FF8,$FF9
Load PC From
Reset: $FFE, $FFF
Fetch
Instruction
Y
SWI
Execute
Instruction
Figure 12 Interrupt Processing Flowchart
Data
Direction
Register
Bit
Output
Data Bit
Output
State
Input to
MCU
o
o
o
3·State
Pin
1
Figure 13 Typical Port I/O Circuitry
o
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
237
HD6805V1--------------------------------------------------------------•
INTERRUPTS
The CPU can be interrupted three different ways: through
the external interrupt (INT) input pin, the internal timer interrupt request. and a software interrupt instruction (SWI). When
any interrupt occurs, processing is suspended, the present CPU
state is pushed onto the stack, the interrupt bit (I) in the Condition Code Register is set, the address of the interrupt routine is
obtained from the appropriate interrupt vector address, and the
interrupt routine is executed. Stacking the CPU registers, setting
the I bit, and vector fetching requires 11 cycles. The Interrupt
service routines normally end with a return from interrupt
(RTf) instruction which allows the CPU to resume processing of
the program prior to the interrupt. Table 1 provides a listing of
the interrupts, their priority, and the vector address that contain
the starting address of the appropriate interrupt routine.
A flowchart of the interrupt processing sequence is given
in Fig. 12.
Table 1 Interrupt Priorities
Priority
Vector Address
1
$FFE and $FFF
SWI
2
$FFC and $FFD
fNT
3
$FFA and $FFB
TIMER
4
$FF8 and $FF9
Interrupt
RES
outputs. Port A is CMOS compatible as outputs, and Port Band
C lines are CMOS compatible as inputs. Figure 14 provides some
examples of port connections.
•
•
•
INPUT/OUTPUT
There are 24 input/output pins. All pins are programmable
as either inputs or outputs under software control of the corresponding Data Direction Register (DDR). When programmed
as outputs, the latched output data is readable as input data,
regardless of the logic levels at the output pin due to output
loading (see Fig. 13). When Port B is programmed for outputs
it is capable of sinking lOrnA on each pin (VOL = I V max).
All input/output lines are TTL compatible as both inputs and
Port A
INPUT
Port D can be used as either 8 TTL compatible inputs or 1
threshold input and 7 analog inputs pins. Fig. 15 (a) shows the
construction of port D. The Port D register at location $003
stores TTL compatible inputs, and those in location $007 store
the result of comparison Do to D6 inputs with D7 threshold
input. Port D has not only the conventional function as inputs
but also voltage-comparison function. Applying the latter, can
easily check that 7 analog input electric potential max. exceeds
the limit with the construction shown in Fig. 15 (b). Also, using
one output pin of MCU, after external capacity is discharged
at the preset state, charge the CR circuit of long enough time
constant, apply the charging curve to the D7 pin. The construction described above is shown in Fig. 15 (c). The compared
result of Do to D6 is regularly monitored, which gives the
analog input electric potential applied ·to Do to D6 pins from
inverted time. This method enables 7 inputs to be converted
from analog to digital. Furthermore, combination of two functions gives 3 level voltages from Do to D6. Fig. 15 (d) provides
the example when VTH is set to 3.5V.
BIT MANIPULATION
The MCV has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 16
illustrates the usefulness of the bit manipulation and test
Port B
Port A Programmed as output(s), driving CMOS and TTL Load directly.
Port B Programmed as output(s). driving Darlington base directly.
(a)
(b)
+V
+V
R
R
Port B
Port C
Port B Programmed as output(s), driving LED(s) directly.
(c)
t - - - -....~ CMOS Inverter
Port C Programmed as output(s). driving CMOS loads. using external pull-I
resistors.
(d)
Fiaure 14 Typical Port Connections
238
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------------HD6805V1
vides turn-on of the TRIAC within 14 microseconds of the zero
crossing. The timer could also be incorporated to provide turnon at some later time which would permit pulse-width modulation of the controlled power.
instructions. Assume that bit 0 of port A is connected to a zero
crossing detector circuit and that bit 1 of port A is connected to
the trigger of a TRIAC which power the controlled hardware.
This program, which uses only seven ROM locations, pro-
$003 Read
Internal Bus
(BitO - Bit6)
Internal Bus
(Bit 7)
(a) The logic configuration of Port 0
Port
Co
C
07
~-'---
Reference Level
~D-,._ _ _
Analog Input 6
07
Port
o
Port
o
Do
D.
\--":"""--Analog Input 6
Do
1 - - ' : - - - Analog Input 0
Analog Input 0
(c) Application to AID convertor
(b) Seven analog inputs and a reference level input of Port 0
07
VTH (; 3.5V)
D.
3 Levels Input 6
Port
0
)
Do
Input
Voltage
($003)
($007)
OV - 0.8V
0
0
2.0V - 3.3V
1
0
3.7V - Vee
1
1
3 Levels Input 0
(d) Application to 3 levels input
Figure 15 Configuration and Application of Port 0
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
239
HD6805V1----------------------------------------------------------______
··
SELF 1
•
BRCLR 0, PORT A, SELF 1
BSET 1, PORT A
BCLR 1, PORT A
Figure 16 Bit Manipulation Example
• ADDRESSING MODES
The CPU has ten addressing modes available for use by the
programmer. They are explained and illustrated briefly in the
following paragraphs.
• Immediate
Refer to Figure 17. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
• Direct
Refer to Figure 18. In direct addressing, the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.
• Extended
Refer to Figure 19. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instructions are three bytes long.
• Relative
Refer to Figure 20. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA=(pC)+2+Rel. Rei is the contents
of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to somewhere within the
range of + 129 bytes to -127 of the present instruction. These
instructions are two bytes long.
• Indexed (No Offset)
Refer to Figure 21. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and their EA is the contents of the index register.
• Indexed (a-bit Offset)
Refer to Figure 22. The EA is calculated by adding the
contents of the byte following the opcode to the contents of
the index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.
• Indexed (16-bit Offset)
Refer to Figure 23. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.
240
Bit Set/Clear
Refer to Figure 24. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.
• Bit Test and Branch
Refer to Figure 25. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
($OO-$FF) and branch to any location relative to the PC. The
byte to be tested is addressed by the byte following the opcode.
The individual bit within that byte to be tested is addressed by
the lower three bits of the opcode. The third byte is the relative
address to be added to the program counter if the branch condition is met. These instructions are three bytes long. The value of
the bit tested is written to the carry bit in the condition code
register.
• Implied
Refer to Figure 26. The implied mode of addressing has no
EA. All the information necessary to execute an instruction is
contained in the opcode. Direct operations on the accumulator
and the index register are included in this mode of addressing.
In addition, control instructions such as SWI, RTI belong to this
group. All implied addressing instructions are one byte long.
•
INSTRUCTION SET
The MCU has a set of 59 basic instructions. They can be
divided into five different types: register/memory, read/modify/
write, branch, bit manipulation, and control. The following
paragraphs briefly explain each type. All the instructions within
a given type are presented in individual tables.
• Register/Memory Instructions
Most of these instructions use two operands. One operand is
either the accumulator or the index register. The other operand
is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR)
instructions have no register operand. Refer to Table 2.
• Read/Modity/Write Instructions
These instructions read a memory location or a register,
modify or test its contents, and write the modified value back
to memory or to the register. The test for negative or zero
(TST) instruction is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
3.
• Branch Instructions
The branch instructions cause a branch from the program
when a certain condition is met. Refer to Table 4.
• Bit Manipulation Instructions
These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 5.
• Control Instructions
The control instructions control the Mev operations during
program execution. Refer to Table 6.
• Alphabetical Listing
The complete instruction set is given in alphabetical order in
Table 7.
• Opcode Map
Table 8 is an opcode map for the instructions used on the
MCV.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD6805V1-
I
8
A
Ind
05BF
F8
Stack Point
I
PROG LOA #$F8 05BE
LQ
I
I
Prog Count
A6
I------~
F8
05CO
CC
I
I
~
I
I
I
Figure 17 Immediate Addressing Example
,
I
I
,
I
FCB
32
EA
I
,,
I
I
I
I
CAT
1
t
Memorv
I
/
t
Adder
20
OO4B
I
004B
~
ol
A
I
I
20
1
Index Reg
I
I
PROG
LOA
CAT
0520
B6
052E
4B
I
I
Stack Point
I
I
I
Prog Count
I
052F
I
CC
~
I
I
I
I
I
I
:
I
I
Figure 18 Direct Addressing Example
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
241
HD6805V1-------------------------------------------------------------EA
Memory
,
I
I
I
I
~
PROG
LOA
M~§
CAT
040A
06
040B
E5
FeB
40
Index Reg
J
Stack Point
Prog Count
040C
40
06E5
64
A
I
I
I
I
CAT
0000
CC
Figure 19 Extended Addressing Example
Memory
:
I
§
A
Index Reg
Stack Point
I
I
PROG
BEQ
PROG2
04A7
27
04A8
18
0000
§
I
,
I
,
Figure 20 Relative Addressing Example
242
¢i)HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD6805V1
Memory
A
TABL
FCC
t Lit OOBB
4C
4C
49
Index Reg
B8
I
PROG
LOA
X
I
Stack Point
05F4~
Prog Count
05F5
CC
§
Figure 21
Indexed (No Offset) Addressing Example
lEA
Melory
i
I
i
i
FCB
#BF
0089
BF
FCB
#86
008A
86
FCB
#OB
008B
DB
FCB
#CF
008C
CF
i
I
PROG
LOA
008C
/
Adder
I
I
TABL
I
t
I
~
A
...i
I
I
I
i
I
TAB L. X 075B
E6
075C
89
I
03
I
Stack Point
I
I
I
Prog Count
I
i
CF
Index Reg
0750
CC
I
I
§
I
,
I
,
Figure 22
Indexed (B·Bit Offset) Addressing Example
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
243
HD6805V1--------------------------------------------------------------
Memory
i
I
§
A
DB
Index Reg
I
PROG
LOA
TABl. X 0692
0693
0694
02
I
~6
07
7E
Stack Point
r-------~
Prog Count
0695
I
TABl
CC
I
FCB
#BF
077E
BF
FCB
#86
077F
86
FCB
#DB
0780 ~--~O~B--_t------------------l
FeB
#CF
0781
CF
Figure 23
Indexed (16-Bit Offset) Addressing Example
Memory
PORT B EQU
BF
0001
A
0000
Index Reg
PROG BClR 6 PORT B 058F
0590
10
1-------4
01
Stack Point
Prog Count
0591
I
I
cc
§
I
I
,
I
Figure 24 Bit Set/Clear Addressing Example
244
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------------HD6805V1
PORT C
EQU
A
0002
2
Index Reg
Stack Point
PROG 8RCLR 2. PORT C. PROG 2
0574
Prog Count
05
J-.-------t
0575
02
0576
10
I
0000
0594
CC
I
~
T
L -____________________________________
~
Figure 25 Bit Test and Branch Addressing Example
Memory
I
I
I
I
~
PROG
TAX
058A
I
I
I
I
I
I
E5
Index Reg
E5
8
Prog Count
0588
cc
I
I
~
Figure 26
Implied Addressing Example
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
245
HD6805V1---------------------------------------------------------------Table 2 Register/Memory Instructions
Addressing Modes
Function
Mnemonic
Indexed
(No Offset)
Extended
Direct
Immediate
Op
#
#
Bytes Cycles Code
Op
Op
Op
#
#
#
#
Code Bytes Cycles Code Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
Indexed
(16-Bit Offset)
#
Op
#
Bytes Cycles Code
#
#
Bytes Cycles
Load A from Memory
LOA
A6
2
2
B6
2
4
C6
3
5
F6
1
4
E6
2
5
06
3
6
Load X from Memory
LOX
AE
2
2
BE
2
4
CE
3
5
FE
1
4
EE
2
5
DE
3
6
Store A in Memory
STA
-
-
-
B7
2
5
C7
3
6
F7
1
5
E7
2
6
07
3
7
Store X in Memory
STX
-
-
-
BF
2
5
CF
3
6
FF
1
5
EF
2
6
OF
3
7
Add Memory to A
ADD
AB
2
2
BB
2
4
CB
3
5
FB
1
4
EB
2
5
DB
3
6
Add Memory and
Carry to A
AOC
A9
2
2
B9
2
4
C9
3
5
F9
1
4
E9
2
5
09
3
6
Subtract Memory
SUB
AO
2
2
BO
2
4
CO
3
5
FO
1
4
EO
2
5
DO
3
6
Subtract Memory from
Awith Borrow
SBC
A2
2
2
B2
2
4
C2
3
5
F2
1
4
E2
2
5
02
3
6
AND Memory to A
AND
A4
2
2
B4
2
4
C4
3
5
F4
1
4
E4
2
5
04
3
6
OR Memory with A
ORA
AA
2
2
BA
2
4
CA
3
5
FA
1
4
EA
2
5
OA
3
6
Exclusive OR Memory
with A
EOR
A8
2
2
B8
2
4
C8
3
5
F8
1
4
E8
2
5
08
3
6
Arithmetic Compare A
with Memory
CMP
A1
2
2
B1
2
4
C1
3
5
F1
1
4
E1
2
5
01
3
6
Arithmetic Compare X
with Memory
2
2
B3
2
4
C3
3
5
F3
1
4
E3
2
5
03
3
6
6
I
CPX
A3
Bit Test Memory with A
(LOIJiCiI Compare)
BIT
A5
2
2
B5
2
4
C5
3
5
F5
1
4
E5
2
5
05
3
Jump Unconditional
JMP
-
-
-
BC
2
3
CC
3
4
FC
1
3
EC
2
4
DC
3
5
Jump to Subroutine
JSR
-
-
-
BO
2
7
CO
3
8
FO
1
7
ED
2
8
DO
3
9
Table 3 Read/ModifylWrite Instructions
Addressing Modes
Function
Implied (A)
Mnemonic
Op
Code
#
Op
Bytes Cycles Code
#
Direct
#
#
Op
Bytes Cycles Code
#
Indexed
Indexed
(No Offset)
(8-Bit Offset)
Op
Bytes Cycles Code
#
#
Op
Bytes Cycles Code
#
#
Bytes Cycles
Increment
INC
4C
1
4
5C
1
4
3C
2
6
7C
1
6
6C
2
Decrement
DEC
4A
1
4
5A
1
4
3A
2
6
7A
1
6
6A
2
7
Clear
CLR
4F
1
4
5F
1
4
3F
2
6
7F
1
6
6F
2
7
Complement
COM
43
1
4
53
1
4
33
2
6
73
1
6
63
2
7
Negate
(2's Complement)
NEG
40
1
4
50
1
4
30
2
6
70
1
6
60
2
7
Rotate Left Thru Carry
ROL
49
1
4
59
1
4
39
2
6
79
1
6
69
2
7
Rotate Right Thru Carry
ROR
46
1
4
56
1
4
36
2
6
76
1
6
66
2
7
Logical Shift Left
LSL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
Logical Shift Right
LSR
44
1
4
54
1
4
34
2
6
74
1
6
64
2
7
Arithmetic Shift Right
ASR
47
1
4
57
1
4
37
2
6
77
1
6
67
2
7
Arithmetic Shift Left
ASL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
TST
40
1
4
50
1
4
3D
2
6
70
1
6
60
2
7
Test for Negative or
Zero
246
#
Implied (X)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
7
----------------------------------------------------------------HD6805V1
Table 4 Branch Instructions
Relative Addressing Mode
Mnemonic
Function
Op
Code
#
#
Bytes
Cycles
4
Branch Always
BRA
20
Branch Never
BRN
21
Branch IF Higher
BHI
22
2
2
2
Branch I F lower or Same
BlS
23
2
4
BCC
(BHS)
24
2
4
24
4
Branch IF Carry Set
BCS
25
(Branch IF lower)
(BlO)
25
2
2
2
BNE
26
2
4
4
4
Branch I F Carry Clear
(Branch IF Higher or Same)
Branch I F Not Equal
Branch I F Equal
BEQ
27
Branch I F Half Carry Clear
BHCC
28
Branch I F Half Carry Set
BHCS
29
Branch I F Plus
BPl
2A
2
2
2
2
4
4
4
4
4
4
Branch I F Minus
BMI
2B
2
4
Branch I F Interrupt Mask Bit is Clear
BMC
2C
2
4
Branch I F Interrupt Mask Bit is Set
BMS
20
4
Branch I F Interrupt Line is low
Bil
2E
Branch IF Interrupt line is High
BIH
2F
Branch to Subroutine
BSR
AD
2
2
2
2
4
4
8
Table 5 Bit Manipulation Instructions
Addressing Modes
Function
Bit Set/Clear
Mnemonic
Op
Code
Bit Test and Branch
#
#
Cycles
Op
Code
Bytes
Cycles
-
2'n
3
10
01+2'n
3
10
-
#
#
Bytes
Branch I F Bit n is set
BRSET n (n=O ..... 7)
-
-
Branch IF Bit n is clear
BRClR n (n=O ..... 7)
-
-
Set Bit n
BSET n (n=O ..... 7)
10+2'n
2
7
-
-
Clear bit n
BClR n (n=O ..... 7)
11+2'n
2
7
-
-
Table 6 Control Instructions
Implied
Function
Mnemonic
Op
Code
#
#
Bytes
Cycles
Transfer A to X
TAX
97
1
2
Transfer X to A
TXA
9F
1
2
Set Carry Bit
SEC
99
1
2
Clear Carry Bit
ClC
98
1
2
Set Interrupt Mask Bit
SEI
9B
1
2
Clear Interrupt Mask Bit
CLI
9A
1
2
Software Interrupt
SWI
83
1
11
Return from Subroutine
RTS
81
1
6
Return from Interrupt
RTI
80
1
9
Reset Stack Pointer
RSP
9C
1
2
No·Operation
NOP
90
1
2
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
247
HD6805V1---------------------------------------------------------------Table 7 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
Direct
Extended
Relative
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
Setl
Clear
Bit
Test &
Branch
H
I
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
•
ADC
x
x
x
x
x
x
/\
ADD
x
x
x
x
x
x
/\
x
x
x
•
•
•
•
•
•
•
•
•
•
•
•
•
x
x
ASl
x
x
x
x
ASR
x
x
x
x
x
AND
x
BCe
x
BClR
BCS
x
BEQ
x
BHCC
x
BHCS
x
BHI
x
BHS
x
BIH
x
Bil
x
x
BIT
x
x
x
BlO
x
BlS
x
BMC
x
BMI
BMS
x
x
BNE
x
BPL
x
BRA
x
BRN
x
x
•
•
x
•
•
•
•
•
•
•
BRCLR
x
BRSET
x
x
BSET
ClC
x
CLI
x
CLR
x
COM
x
x
CPX
DEC
x
x
x
x
x
x
x
x
EaR
x
x
x
x
x
x
x
x
CMP
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
JSR
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
LDA
LDX
x
•
•
JMP
INC
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
•
•
•
•
•
x
BSR
248
Bit
•
•
•
•
•
•
•
•
•
•
•
N
Z
C
/\
/\
/\
/\
/\
/\
/\
/\
/\
•
/\
/\
/\
/\
/\
•
•
•
•
•
•
•
•
•
•
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1\
1\
•
•
0
•
•
0
1
1\
/\
/\
/\
1
1\
1\
1\
1\
•
•
1\ 1\ •
• • •
• • •
/\ 1\ •
/\ /\ •
1\
1\
1\
1\
(to be continued)
C
/\
Carry Borrow
Test and Set if True. Cleared Otherwise
Not Affected
~HITACHI
Hitachi America Ltd_ • 2210 O'Toole Ave_ • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD6805V1
Table 7 Instruction Set
Addressing Modes
Condition Code
----,-
Mnemonic
Implied
Immediate
Direct
Extended
Relative
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
LSL
x
x
x
x
LSR
x
x
x
x
NEG
x
x
x
x
NOP
x
x
x
x
x
x
x
x
x
ROR
x
x
x
x
RSP
x
RTI
x
RTS
x
ORA
ROL
x
x
x
x
x
x
x
STA
x
x
x
x
STX
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SBC
SEC
x
SEI
x
x
SUB
SWI
Bit
Set!
Clear
x
TAX
x
TST
x
TXA
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
x
C
1\
•
7
Bit
Test &
Branch
H
I
N
Z
C
• 1\ 1\ 1\
• 0 1\ 1\
• 1\ 1\ 1\
• • • •
• 1\ 1\ •
• 1\ 1\ 1\
• 1\ 1\ 1\
• • • •
?
? ? ?
• • • •
• 1\ 1\ 1\
• • • 1
1 • • •
• 1\ 1\ •
• 1\ 1\ •
• 1\ 1\ 1\
1
• • •
• • • •
• • 1\ 1\ •
• • • • •
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
249
HD6805V1------------------------------------------------------------Table 8
Bit Manipulation
Test &
Branch
Clear
0
0
BRSETO
1
2
Setl
Branch
Opcode Map
Control
Read/Modify/Write
Register IMemory
,XO
IMP
IMP
IMM
I
DIR
7
8
9
A
B
NEG
RTI·
-
I
I
I
-
RTS*
-
CMP
1
BHI
SBC
2
SWI*
-
CPX
3
l
-
AND
4
o
BIT
5 W
Rei
DIR
1
2
3
BSETO
BRA
BRCLRO
BCLRO
BRN
BRSET1
BSET1
I
I
A
4
I
I
X
5
3
BRCLR1
BClR1
BlS
COM
4
BRSET2
BSET2
BCC
lSR
5
BRCLR2
BClR2
BCS
-
6
BRSET3
BSET3
BNE
ROR
7
BRCLR3
BClR3
BEQ
ASR
I
I
,X1
6
I
I
-
EXT j,X2
C
I
0
I
,X1
T
I
E
T
,XO
F
SUB
+-
8
BRSET4
BSET4
BHCC
lSl/ASl
-
ClC
EOR
9
BRCLR4
BClR4
BHCS
ROl
-
SEC
ADC
9
A
BRSET5
BSET5
BPl
DEC
-
CLI
ORA
A
B BRCLR5
BClR5
BMI
-
-
SEI
ADD
B
C BRSET6
BSET6
BMC
INC
-
RSP
BRCLR6
BClR6
BMS
TST
NOP
TAX
E BRSET7
BSET7
Bil
-
-
F BRCLR7
BClR7
BIH
ClR
-
TXA
1/·
1/2
0
3/10
(NOTE)
250
217
2/4
2/6
I 1/4
I 1/4
I 2/7
I 1/6
-
-
I
I
BSR·I
212
J
I
2/4
I 3/5
I
lOA
6
STA(+1)
7
8
JMP(-1)
C
JSR(+3)
0
LOX
E
STX(+1)
F
3/6
HIGH
0
I
2/5
I 1/4
1. Undefined opcodes are marked with "-".
2. The number at the bottom of each column denote the number of bytes and the number of cycles reQuired (Bytes/Cycles).
Mnemonics followed by a ..... reQuire a different number of cycles as follows:
RTI
9
RTS
6
SWI
11
BSR
8
3. (
indicate that the number in parenthesis must be added to the cycle count for that instruction.
$HITACfll
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6805W1
MCU
(Microcomputer Unit)
The HD6805Wl is an 8-bit microcomputer unit (MCU)
which contains a CPU, on-chip clock, ROM, RAM, standby
RAM, an A/D Converter, I/O and two timers. It is a member of
the HD6805 family which is designed for user who needs an
economical microcomputer with proven capabilities of the
HD6800-based instruction set.
The following are some of the hardware and software highlights of the MCU.
•
•
•
•
•
•
•
•
•
•
HARDWARE FEATURES
8-Bit Architecture
96 Bytes of RAM
(8 bytes are standby RAM functions)
Memory Mapped I/O
3848 Bytes of User ROM
Internal 8-Bit Timer (Timer 1) with 7-Bit Prescaler
Internal8-Bit Programmable Timer (Timer 2)
Interrupts - 2 External and 4 Timers
23 TTL/CMOS compatible I/O Lines; 8 Lines Directly
Drive LEOs.
On-Chip 8-Bit, 4-Channel A/D Converter
On-Chip Clock Circuit
Self-Check Mode
Master Reset
Low Voltage Inhibit
Easy for System Development and Debugging
5 Vdc Single Supply
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versati Ie Interrupt Function
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible with MC6805P2, HD6805S1 and HD6805V1
•
•
•
•
•
•
HD6805W1P
(DP-40)
•
PIN ARRANGEMENT
0
Vss
AT
A.
A,
A.
A,
A,
A,
Ao
BT
B.
B,
B.
RAME/RES
INT,
Vee
EXTAL
XTAL
NUM
TIMER
Co
C,
C,
C,
C.
IC/C,
OC/C.
7
HD6805Wl
B,
B,
B,
Bo
INT, /Do
ANo/D,
AN, /D,
AN,/D,
AN,/D.
21
AVec
AVss
VRH/D,
Vee Standby
(Top View)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
251
HD6805W1-------------------------------------------------------------• BLOCK DIAGRAM
TIMER
8
Port B
I/O Lines
TlMER-2
Prescaler 2
Timer Data
8 Register 2
Timer
8 Status Register 2
Output Compare
8 Register
I nput Capture
8 Register
(lC)
Timer Control
8 Register 2
PortA
I/O Lines
A.
A,
A,
A,
A.
A,
A,
A,
.,
.~
0::
«
~
'B
CPU Control
...
a:
O~
(O.!e
III
00::
Q.
10~
X
Condition Code
Register
CC
5
.~
.~
Index Register
8
~
0
A
8
Prescaler Control
8 Register 2
(DC)
e:
Accumulator
5
CPU
Port C
I/O Lines
Stack Point
6
SP
4
Program Counter
"High"
PCH
Bo
B,
B,
B,
B.
Bs
e:
0
.;;
al
c5!
ALU
ca·~
Program Counter
"Low"
8
PCL
~~
00::
~
.~
0::
U
5
Q.
e:
Co
C,
C,
C,
C.
C S (IC)
C, (DC)
Port D
Input lines
.2
.:~ ...
Do
D,
D,
D,
D.
Ds
O~
m·!!!
;~
00::
(RAME) Vee Standby
(lNT,)
(AN o )
(AN,)
(AN,)
(AN,)
(VRH)
ADC lines
AVee
AVSS
(VRH)
(AN o)
(AN,)
(AN,)
(AN,)
A/D Control
Status Register
8
AID Result
Register
8
(NOTE)
252
$
The contents of ( ) items can be changed by software.
HITACHI
Hitachi America Ltd_ • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------------HD6805W1
•
ABSOLUTE MAXIMUM RATINGS
Vee
Input Voltage (EXCEPT TIMER)
V in
Input Voltage (TIMER)
Operating Temperature
T opr
Storage Temperature
T stg
(NOTE)
Value
Symbol
Item
Supply Voltage
Unit
-0.3
~
+7.0
V
-0.3
~
+7.0
V
-0.3 - +12.0
o
V
°c
~+70
°c
-55 - +150
This device has an input protection circuit for high quiescent voltage and field, however, be careful not
to impress a high input voltage than the insulation maximum value to the high input impedance circuit.
To insure normal operation. the following are recommended for V in and V out :
VSS ~ (V in or Vout ) ~ Vee
•
ElECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee = 5.25V ±0.5V, Vss = GND, Ta = 0 -+70°C, unless otherwise noted.)
Symbol
Item
Input "High" Voltage
min
typ
max
Unit
RES
4.0
-
Vee
V
INTJ.INT2
3.0
-
Vee
V
2.0
-
Vee
V
2.0
-
V
V IH
All Others
Input "High" Voltage (Timer)
Test Condition
Timer Mode
Self-Check Mode
RES
INT I. INT2
EXTAL(Crystal Mode)
All Others
Input "Low" Voltage
Power Dissipation
V IL
-
-0.3
-
0.8
V
-0.3
-
0.8
V
-0.3
-0.3
-
0.6
0.8
V
V
-
V
Po
LVR
-
-
750
mW
Low Voltage Recover
-
-
4.75
V
Low Voltage Inhibit
LVI
-
4.0
-
V
-20
-
20
p.A
-50
-
50
p.A
-
0
p.A
TIMER
Input Leak Current
Standby Voltage
V in =O.4V:--V ee
INTI.INT2
EXTAL(Crystal Mode)
IlL
Nonoperation Mode
V SBB
4.0
-
Vee
Operation Mode
V SB
4.75
-
Vee
-
3
typ
max
Unit
4.0
MHz
Nonoperation Mode
Standby Current
•
9.0
Vee
11.0
-1200
ISBB
VSBB=4.0V
-
V
mA
AC CHARACTERISTICS (Vee = 5.25V ±O.5V, Vss = GND. Ta = 0 -+70°C, unless otherwise noted.)
Item
Symbol
Clock Frequency
Test Condition
min
0.4
tel
-
1.0
-
10
/..I.s
-
3.4
-
MHz
tlWL
t Cyc +
250
-
-
ns
tRWL
t Cyc +
250
-
-
ns
TIMER Pulse Width
t TWL
t Cyc +
250
-
-
ns
Oscillation Start-up Time (Crystal Mode)
tose
C L =22pF±20%
Rs=60Q max.
-
-
100
ms
Delay Time Reset
tRHL
External Cap. = 2.2 p.F
100
Cycle Time
tCYC
Oscillation Frequency (External Resistor Mode)
texT
TNii Pulse Width
RES Pulse Width
I nput Capacitance
I
I
XTAL. VRH/Ds
All Others
C in
R ep =15.0kQ±1%
Vin=OV
-
-
-
-
35
pF
-
-
10
pF
~HITACHI
\ Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
ms
-----
253
HD6805W1--------------------------------------------------------------•
PORT ELECTRICAL CHARACTERISTICS (Vee = 5.25V ±O.5V. Vss = GND. Ta = 0 - +70°C. unless otherwise noted.1
Item
Test Condition
Symbol
min
typ
max
Unit
IOH = -10~A
3.5
-
V
IOH = -100~A
2.4
-
V
IOH = -200~A
2.4
-
-
V
IOH=-1mA
1.5
-
-
V
Port C
IOH = -100 ~A
2.4
V
IOL = 1.6 mA
-
0.5
V
IOL = 3.2 mA
-
-
-
Ports A and C
0.5
V
IOL = 10 mA
-
-
1.0
V
Vee
O.S
V
-
~A
Port A
Output "High" Voltage
Output "Low" Voltage
Input "High" Voltage
Input "Low" Voltage
Input Leak Current
V OH
Port B
VOL
Port B
Ports A. B. C
and 0
V IH
2.0
-
V IL
-0.3
-
Vin = O.SV
-500
Vin = 2V
-300
-
Port A
IlL
Ports B. C and 0
•
-20
Vin = O.4V-V ee
V
-
~A
20
~A
AID CONVERTER ELECTRICAL CHARACTERISTICS (Vee = 5.25V±O.5V. Vss = AVss = GMD. Ta = 0 - +70°C. unless
otherwise noted.1
Item
Symbol
Analog Power Supply
Voltage
AVee
Analog Input Voltage
AV in
Reference Voltage
V RH
Test Condition
Unit
5.75
V
0
V RH
V
V
-
< Vee ~ 5.75V
4.0
-
Vee
5.25
-
-
7.5
pF
5.25V
at 4MHz
Input Channels
254
max
4.0
Resolution Power
Absolute Accuracy
typ
5.25
4.75V ~ Vee ~ 5.25V
Analog Multiplexer Input
Capacitance
Conversion Time
min
4.75
Ta = 25°C
$
V
-
8
-
76
76
76
Bit
tCYC
4
4
4
Channel
-
-
±1.5
LSB
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------------------HD6805W1
TTL Equiv. (Ports A, C and D)
TTL Equiv. (Port B)
Vee
Ii = 3.2 mA
1.4kn
Ii = 1.6 mA
Test Point
Test Point
Vi
2.4kH
Vi
40 pF
(NOTE)
30 pF
12 kn
24 kl1
1. Load capacitance includes the floating capacitance of the probe and the iig etc.
2. All diodes are 1S2074(j3) or equivalent.
Figure 1 Bus Timing Test Loads
•
al information.
SIGNAL DESCRIPTION
The input and output signals for the MCU, shown in PIN
ARRANGEMENT, are described in the following paragraphs.
•
Vee and Vss
Voltage is supplied to the MCU using these two pins. Vee is
S.2SV ±O.SV. Vss is the ground connection.
•
INT./INT 2
This pin provides the capability for asynchronously applying
an external interrupt to the MCU. Refer to INTERRUPTS
for additional information.
•
XTAL and EXTAL
These pins provide connections for the on-chip clock circuit.
A crystal (AT cut, 4 MHz maximum), a resistor or an external
signal can be connected to these pins to provide a system clock
with various stability/cost tradeoffs. Refer to INTERNAL OSCILLATOR OPTIONS for recommendations about these inputs.
•
TIMER
•
RES
This pin allows an external input to be used to count for the
internal timer circuitry. Refer to TIMER 1 and TIMER 2 for
additional information about the timer circuitry. When this pin
isn't used, it must be grounded.
• Vee Standby
Vee Standby provides power to the standby portion of the
RAM and the STBY PWR and RAME bits of the RAM Control
Register. Voltage requirements depend on whether the MeU
is in a powerup or powerdown state. In the powerup state, the
power supply should provide Vee and must reach V SB before
RES reaches 4.0V. During powerdown, Vee standby must
remain above V SBB (min) to sustain the standby RAM and
STBY PWR bit. While in powerdown operation, the standby
current will not exceed ISBB.
It is typical to power both Vee and Vee Standby from the
same source during normal operation. A diode must be used
between them to prevent supplying power to Vee during
powerdown operation shown Figure 2.
To sustain the standby RAM during powerdown, the following software or hardware are needed.
(1) Software
When clearing the RAM Enable bit (RAME) which is bit 6
of the RAM Control Register at location $OOlF, the RAM
is disabled.
Vee Standby must remain above V SBB (min).
(2) Hardware
When RAME pin is "Low" before powerdown, the RAM is
disabled. Vee Standby must remain above VS BB (min).
This pin allows resetting of the MCU at times other than the
automatic resetting capability already in the MCU. Refer to
RESETS for additional information.
•
NUM
•
I/O Lines (Ao ~ A 7 , 8 0 ~ 8 7 , Co ~ C6
Vee S"odbV
T
Po~,
Uo,
This pin is not for user application and should be connected
to VSS'
)
There 23 lines are arranged into three ports (A, B and C). All
lines are programmable as either inputs or outputs under software control of the Data Direction Register (DDR). Refer to
INPUT/OUTPUT for additional information.
•
Input Lines (Do ~ Os)
These are TTL compatible input lines, in location $003.
These also allow analog inputs to be used for an A/D converter
and interrupt. Refer to INPUT and A/D converter for addition-
Figure 2 Battery Backup for Vee Standby
•
RAME
This pin is used for the external control of the RAM. When
it is "Low" before powerdown, the RAM is disabled. If Vee
Standby remains above VSBB (min), the standby RAM is
sustained.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
255
HD6805W1--------------------------------------------------------------•
AVec
This pin is used for the power supply of the AID converter.
When high accuracy is required, a different power source from
Vee should be impressed.
Connect to Vee for all other cases. AVss corresponds to
AVee as a GND terminal.
•
ANo -AN 3
These pins allow analog inputs to be used for an AID converter. These inputs are switched by the intemal multiplexer
and selected by bit 0 and 1 of the AID Control Status Register
(ADCSR: $OOE).
VRH and AVSS
The input terminal reference voltage for the AID converter is
"High" (VRH)or "Low" (AV ss ). AVss is fIXed at OV.
•
Input Capture (lC)
This pin is used for input of Timer 2 control, in this case,
Port C s should be configured as input. Refer to TIMER 2
for more details.
Compare Register is matched with the Timer Data Register
2. In this case, Port C6 should be configured as an output.
Refer to TIMER 2 for more details.
• MEMORY
The MCV memory is configured as shown in Figure 3. During
the interrupt processing, the contents of the CPU registers are
pushed onto the stack in the order shown in Figure 4. Since
the stack pointer decrements during pushes. the low order byte
(PCL) of the program counter is stacked first; then the high
order three bits (PCH) are stacked. This ensures that the program counter is loaded correctly as the stack pointer increments
when it pulls data from the stack. A subroutine call will cause
only the program counter (PCH, PCl) contents to be pushed
onto the stack.
•
• Output Compare (OC)
This pin is used for output of Timer 2 when the Output
000
sooo
I/OPom
Caution: - Self Test ROM Address Area
Self test ROM locations can not be used for a user program.
If the user's program is in this location, it will be removed when
manufacturing mask for production.
~-P~O'~'A~-------_4SOOO
Por,8
TII,.r
$01F
$020
031
032
RAM
s001
~-----------~
~--p~O'~'C~-----_4~2
~-:~::~:~=-O-O-R-----4=:·
196 81
127
128
$07F
$080
1005'
~----------~
POri C OOR
$006"
~------------~
~-----------_4_7
ROM
138~
81
~
Tlm,r 0.1. Reg 1
$008
Tim" CTRL Reg 1
SOO9
M.s.c,tI.neou' Reg
SOOA
_______________ SOOB
~_________________
~
SOOC
__________________ 0
AID CTAL Status Reg
SOOE
AID R.sul1 Reg
SOOF ••
~_ _ _ _ _ _ _ _ _ _ _ _ _ _---,"$O10
~______________---,"SOl1
SO'2
~-----------------,"
1-______________
~SOI3
I-______________
..
1-_____________~SOIS
1-_____________~SO'6
~SO
SO 17
~------------1-____________
~SOI8
P"IC.I., CTRL Reg '1
$019
Tlm,r St'.IUS Ret '1
SOl A"
TIm" CTRL Reg '1
S018
Tim" 0,1' Reg '1
SO I C
Output Comp", R.g
SOlO
:;1----------1 :::~
Stlf·t,t' ROM 112081
::; I----------l:::;
l"tttr~lI:tlVK10rl
·Wrlt.Reg
409S~
_ _ _ _ _ _ _...JIFFF
"RtIdRt9
•• 'SI,ndby RAM
u,,' 'If" 8 by'"
of RAM
Figure 3 MCU Memory Structure
256
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------~----------------------------------HD6805W1
5
n-4
1
4
Pu II
Condition
1
11 Code Register
n +1
n-3
Accumu lator
n+2
n-2
Index Register
n+3
n-1
1
1
1
1
11
PCH*
PC l '
n +4
n+S
Pu sh
Figure 4
Interrupt Stacking Order
Condition Code Register (CC)
The condition code register is a 5-bit register in which each
bit is used to indicate or flag the results of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each individual condition code register bit is explained below.
REGISTERS
The CPU has five registers available to the programmer,
as shown in Figure 5 and explained below.
0
I
A
I ndex Reg ister
X
The half carry bit is used during arithmetic operations (ADD
or ADC) to indicate that a carry occurred between bits 3 and 4.
This bit is set to mask everything. If an interrupt occurs
while this bit is set. it is latched and will be processed as soon as
the interrupt bit is reset.
Negative (N)
PC
Program Counter
11
0
Half Carry (H)
Interrupt (I)
Accu mu lator
11
I
Stack Pointer (SP)
The stack pointer is a 12-bit register that contains the address
of the next free location on the stack. Initially, the stack point·
er is set to location $07F and is decremented as data is being
pushed onto the stack and incremented while data is being
pulled from the stack. The six most significant bits of the stack
pointer are permanently set to 00000 I. During an MCU reset
or reset stack pointer (RSP) instruction. the stack pointer is
set to location $07F. Subroutines and interrupts may be nested
down to location $041 which allows the programmer to use up
to 3 I levels of subroutine calls.
•
• For subroutine calls. only PCH and PCl are stacked
•
•
0
10 I
10 1
0
I
11
SP
I
Stack Pointer
The negative bit is used to indicate that the result of the last
arithmetic. logical or data manipulation was negative (bit 7 in
a result equal to a logical one).
Zero (Z)
Condition Code Register
Carry/Borrow
Zero
Negative
Interrupt Mask
Zero is used to indicate that the result of the I"st arithmetic,
logical or data manipulation was zero.
Carry/Borrow (C)
Carry /borrow is used to indicate that a carry or borrow au t
of the arithmetic logic unit (ALU) occurred during the last
arithmetic operation. This bit is also affected during bit test and
branch instructions, shifts and rotates.
Half Carry
•
Figure 5 Programming Model
•
Accumulator (A)
The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.
•
Index Register (X)
The index register is an 8-bit register used for the indexed
addressing mode and con tains an 8-bit address that may be
added to an offset value to aeate an effective address. The
index register can also be used for limited calculations or data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
•
Program Counter (PC)
The program counter is a 12-bit register that contains the
address of the next instruction to be executed.
TIMER 1
The MCU timer circuitry is shown in Figure 6. The 8-bit
counter, Timer Data Register 1 (TORI), is loaded under program control and counts down toward zero as soon as the clock
input is applied. When the TORI reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register I (TCRI)
is set. The CPU responds to this interrupt by saving the present
CPU state in the stack, fetching the timer I interrupt vector
from locations $FF8 and $FF9 and executing the interrupt
routine. The timer 1 interrupt can be masked by setting the
timer interrupt mask bit (bit 6) in the TCRI. The interrupt
bit (I bit) in the Condition Code Register also prevents a timer I
interrupt from being processed.
The clock input to the timer I can be from an external
source applied to the TIMER input pin or it can be the internal
2 is used as the source, it can be gated by an
input applied to the TIMER input pin allowing the user to
easily perform pulse·width measurements. When the TIMER
input pin doesn't control the Zero
DIRECT
OP Branch Always
Brlnch If - Zero
Brlnch If ;;. Zero
RELATIVE
#
#
#
C
3
2
Z + (N
Z- 1
N
0 v-o
0 V)
Brlnch If Higher
22
3
2
C+Z-O
Brlnch If .. Zero
BlE
2F
3
2
Z + (N
Branch If lower Or
Seme
BlS
23
3
2
BlT
20
BMI
2B
3 2
3 2
N - 1
Branch If NOI Equal
Zero
BNE
26
3 2
Zoo
Brlnch If Overflow
Clelr
BVC
2B
3 2
V-o
Brlnch If Overflow Sel
BVS
29
3 2
V-I
Brlnch If Plus
BPl
2A
Brlnch To Subroutine
Jump
BSR
JMP
80
Jump To Subrouline
JSR
90
5
2
6E
7E
AD
80
V) - 1
· ... ..
No Operltion
NOP
01
RTI
3B 10 1
RTS
39
Sofewere Interrupt
SWI
WAI
SLP
3F 12 1
Sleep
0
- 0
N-O
Return From Inlerrupt
Return From
Subroutine
Weit for Interrupt-
3E
lA
1 1
5
9
4
Advlnces Prog. Cntr.
Only
1
1
1
Note) ·WAI puts R/W hogh;Address Bus goes to F F F F; Data Bus goes to the three state.
CondItIon Code RegIster \/11111 be explained in Note of Table 11.
302
=1
2
3 2
3 2
BGT
BHI
Branch If < Zero
Brlnch If Minus
543210
HINZVC
--1)
--
·· • .• .• • •
S
·
:!> •
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HI?6301 V1 ,HD63A01 V1 ,HD63B01 V1
Table 11
Condition Code Register Manipulation Instructions
!AddressingModel
Oper.tion,
CIe.r Carry
Condition Code Aeg"ter
IMPLIED
Mnemonic
ClC
Boolean Operation
OP
-
It
OC
I
I
O-C
CLI
OE
I
I
0-1
CI.ar Overflow
ClV
OA
I
I
o-v
Set Carry
SEC
00
I
Set Intarrupt Ma,k
SEI
OF
I
,
1- C
1-1
Set Overflow
SEV
OB
1
1
I-V
Accumulator A - CCR
TAP
06
I
I
A- CCA
CCR - Accumulator A
TPA
07
I
I
CCR- A
[NOTE
11
Condition
CD (Bit
@
(Bit
@
(Bit
@
(Bit
@
(Bit
® (Bit
iJ)
(Bit
®
(All
® (Bit
@l
@
Code
V)
C)
C)
V)
V)
V)
N)
Bit)
t)
(All Bit)
(Bit C)
4
3
2
1
H
I
N
Z
V
0
C
··· ·· ··· ··· ·· ··
··· ·· ··· ··· ·· ··
······
A
Claar Intarrupt Ma,k
I
5
A
A
S
S
S
- - - Itt - - -
Register Notes: (Bit set if test is true and cleared otherwise)
Test: Result = 1OO00000?
Test: Result \ 00000000?
Test: BCD Character of high~rder byte greater than 9? (Not cleared if previously set)
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to NmC=1 after the execution of instructions
Test: Result less than zero? (Bit 15=1)
Load Condition Code Register from Stack.
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the wait
state.
Set according to the contents of Accumulator A.
Result of Multiplication Bit 7= 1 of ACCS?
[NOTE 2] CLI instructions and interrupt.
_ _ __
If interrupt mask-bit is set (1 ="1") and interrupt is requested (lRO, = "0" or IR0 2 = "0"),.
and then CLI instruction is executed, the CPU responds as follows.
1 the next instruction of CLI is one-machine cycle instruction.
Subsequent two instructions are executed before the interrupt is responded.
That is, the next and the next of the next instruction are executed.
2 the next instruction of CLI is two-machine cycle (or more) instruction.
Only the next instruction is executed and then the CPU jump to the interrupt routine.
Even if TAP instruction is used, instead of CLI, the same thing occurs.
Table 12 OP-Code Map
OP
ACC
ACC
CODE
A
B
0011
0100
0101
0110
3
4
~
6
~
LO
0000
0000
0001
0
I
O~
NOP
SBA
2
BRA
CBA
BRN
INS
BHI
PULA
BLS
PULB
0001
I
0010
~ ~
3 ~ ~
4 LSRD ~
5 ASLo ~
0011
0100
0101
0110
0111
2
TSX
BCC
DES
BCS
TXS
6
7
TAP
TAB
BNE
PSHA
TPA
TBA
BEQ
PSHB
XGoX BVC
PULX
oAA
RTS
8
INX
1001
1010
1000
0010
9
oEX
A
ClV
SlP
BPl
ABX
1011
B
SEV
ABA
BMI
RTI
1100
C
CLC
~
BGE
PSHX
1101
D
SEC
./'"""
BlT
MUl
1110
E
CLI
BGT
WAI
1111
F
SEI
~
~
,
SWI
0
1
BVS
BlE
3
INo
1%
ACCA or SP
olR
I
i
INo
1000
1001
8 ,
9
I
1010
I
I
I
A
I
I
0111
7
ACCB or X
DIR
IMM
IMM
1011
1100
I
1101
B
C
J
o
:.:::--
----
---
AIM
CMP
OIM
SBC
COM
I
EXT
1110
I
1111
E
j
F
0
I
2
SUBo
3
AND
4
BIT
ElM
5
lOA
ROR
./'""" -I
ASR
EOR
ROl
AoC
DEC
TIM
INC
6
~I
STA
ASl
STA
9
QRA
A
ADD
B
JMP
7
8
,
I
D
lOX
~l
STS
9
C
STo
lOS
~
6
Loo
./'""" I
JSR
BSR I
7
8
CPX
TST
ClR
5
liND
I
J
Aooo
lSR
~~
4
olR
SUB
NEG
------
I
EXT
A
I
B
C
I
E
STX
o
1
E
F
J
F
UNDEFINED OP CODE ~
• Only for instructions of AIM, OIM, ElM, TIM
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
303
HD6301V1,HD63A01V1,HD63B01V1--------------------------------------------•
Instruction Execution Cycles
In the HMCS6800 series, the execution cycle of each instruction is the number of cycles between the start of the
current instruction fetch and just before the start of the subsequent instruction fetch.
The HD6301 VI uses a mechanism of the pipeline control for the instruction fetch and the subsequent instruction
fetch is performed during the current instruction being exe-
cuted.
Therefore, the method to count instruction cycles used in
the HMCS6800 series cannot be applied to the instruction cycles such as MULT, PULL, DAA and XGDX in the HD6301VI.
Table 13 provides the information about the rel~onship
among each data on the Address Bus, Data Bus, and R/W status
in cycle·by-cycle basis during the execution of each instruction.
Table 13 Cycle-by-Cycle Operation
Address Mode &
Instructions
IMMEDIATE
ADC
ADD
AND
BIT
EOR
CMP
LOA
ORA
SBC
SUB
ADDD CPX
LDD
LOS
LOX
SUBD
DIRECT
ADC
AND
CMP
LOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
Address Bus
CPX
LOS
SUBD
STD
STX
STS
1
2
Op Code Address+ 1
Op Code Address+2
1
1
Operand Data
Next Op Code
1
2
3
Op Code Address+ 1
Op Code Address + 2
Op Code Address + 3
1
1
1
Operand Data (MSB)
Operand Data (LSE:')
Next Op Code
1
2
Op Code Address + 1
Address of Operand
Op Code Address+2
1
1
1
Address of Operand (LSB)
Operand Data
Next Op Code
1
Destination Address
Accumulator Data
Next Op Code
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
2
3
3
3
ADDD
LDD
LOX
4
3
1
2
3
1
12
3
4
4
JSR
5
1
2
3
4
1
2
3
4
5
TIM
4
1
2
3
4
AIM
OIM
Data Bus
ElM
6
1
2
3
4
5
6
Op Code Address+ 1
Destination Address
Op Code Address+2
Op Code Address+ 1
Address of Operand
Address of Operand + 1
Op Code Address+2
Op Code Address + 1
Destination Address
Destination Address+ 1
Op Code Address+2
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-l
Jump Address
Op Code Address+ 1
Op Code Address+2
Address of Operand
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
, Address of Operand
'FFFF
Address of Operand
Op Code Address+3
0
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
- Continued -
304
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave_ • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - HD6301 V1,HD63A01 V1,HD63B01 V1
Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
INDEXED
JMP
3
ADC
AND
CMP
LOA
SBC
TST
STA
ADD
BIT
EOR
ORA
SUB
4
4
1
2
3
1
2
3
4
1
2
3
4
ADDD
CPX
LOS
SUBD
STD
STX
LDD
LOX
5
1
2
3
4
5
STS
5
1
2
3
4
5
JS~
1
2
5
3
4
5
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
4
5
6
1
2
TIM
5
CLR
5
AIM
OIM
1
2
3
ElM
7
3
4
5
1
2
3
4
5
1
2
3
4
5
6
7
Data Bus
Op Code Address+ 1
FFFF
Jump Address
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address+2
1
1
1
1
1
1
1
Offset
Restart Address (LSB)
First Op Code of Jump Routine
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Op Code Address + 1
FFFF
IX + Offset
Op Code Address+2
Op Code Address + 1
FFFF
IX + Offset
IX + Offset+ 1
Op Code Address+2
Op Code Address + 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address+2
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-l
IX + Offset
Op Code Address + 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address + 2
Op Code Address + 1
Op Code Address+2
FFFF
IX+Offset
Op Code Address + 3
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset
Op Code Address+2
Op Code Address + 1
Op Code Address + 2
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address + 3
1
1
Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
00
1
1
1
1
1
1
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
0
1
- Continued -
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
305
HD6301Vl,HD63A01Vl,HD63B01Vl----------------------Table 13 Cycle-by.cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
EXTEND
JMP
3
ADC
AND
CMP
lOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
TST
4
4
ADDD
CPX
lOS
SUBD
lDD
lOX
5
1
2
3
1
2
3
4
Op Code Address + 1
Op Code Address + 2
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
Op Code Address+3
1
1
1
1
1
1
1
Jump Address (MSB)
Jump Address (lSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data
Next Op Code
1
2
3
4
1
2
3
4
Op Code Address + 1
Op Code Address+2
Destination Address
Op Code Address+3
Op Code Address+ 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
Op Code Address + 3
Op Code Address + 1
Op Code Address+2
Destination Address
Destination Address + 1
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Address of Operand
Address of Operand
O~ Code Address+3
1
1
Destination Address (MSB)
Destination Address (lSB)
Accumulator Data
Next Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data (MSB)
Operand Data (lSB)
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (MSB)
Jump Address (lSB)
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
5
STD
STX
STS
5
1
2
3
4
5
JSR
6
1
2
3
4
5
6
ASl
COM
INC
NEG
ROR
ASR
DEC
lSR
ROL
6
1
2
3
4
5
6
ClR
5
Data Bus
1
2
3
4
5
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
0
00
1
Next Op Code
- Continued -
306
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301V1,HD63A01V1,HD63B01V1
Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions
IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
PULA
ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
LSR
ROL
NOP
SEC
SEV
TAP
TPA
TSX
XGDX
Address Bus
1
Op Code Address + 1
1
Next Op Code
Op Code Address + 1
FFFF
Op Code Address + 1
FFFF
Stack Pointer + 1
Op Code Address + 1
FFFF
Stack Pointer
Op Code Address+ 1
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Op Code Address +. 1
FFFF
Stack Pointer
Stack Pointer - 1
Op Code Address + 1
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Return Address
Op Code Address + 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
1
1
1
1
1
1
1
Next Op Code
Restart Address (LSB)
Next Op Code
Restart Address (LSB)
Data from Stack
Next Op Code
Restart Address (LSB)
Accumulator Data
Next Op Code
Next Op Code
Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSB)
Next Op Code
Restart Address (LSB)
Index Register (LSB)
Index Register (MSB)
Next Op Code
Next Op Code
Restart Address (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
- Continued -
I
1
2
PULB
3
1
2
1
2
3
..
PSHA
Data Bus
PSHB
4
PULX
4
PSHX
1
2
3
4
1
2
3
4
1
2
5
RTS
3
4
5
1
2
5
MUL
3
4
5
1
2
7
3
4
5
6
7
$
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
307
HD6301V1,HD63A01V1,HD63B01V1--------------------------------------------Table 13 Cycle-by·Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
IMPLIED
WAI
9
1
2
3
4
5
6
7
8
9
RTI
1
2
3
10
4
5
6
7
8
9
SWI
12
SLP
4
10
1
2
3
4
5
6
7
8
9
10
11
12
1
2
I
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer - 5
Stack Pointer-6
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4
Stack Pointer + 5
Stack Pointer + 6
Stack Pointer + 7
Return Address
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address + 1
FFFF
FFFF
Sleep
1
3
4
FFFF
Op Code Address + 1
Data Bus
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
Next Op Code
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
Index Register (lSB)
Index Register (MSB)
Accumulato~ A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (lSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (lSB)
Return Address. (MSB)
Return Address (lSB)
First Op Code of Return Routine
Next Op Code
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
Index Register (lSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (LSB)
First Op Code of SWI Routine
Next Op Code
Restart Address (LSB)
High Impedance· Non MPX Mode
Address Bus ·MPX Mode
1
Restart Address (LSB)
Next Op Code
- Continued -
308
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301Vl,HD63A01Vl,HD63B01Vl
Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions
RELATIVE
BCC
BEQ
BGT
BlE
BlT
BNE
BRA
BVC
BSR
BCS
BGE
BHI
BlS
BMT
BPl
BRN
BVS
Address Bus
3
1
2
3
5
1
2
3
4
5
Op Code Address+ 1
FFFF
1Branch Address···· .. Test=·1 ..
Op Gode Address+1···Test=·O"
1
1
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Branch Address
1
1
0
0
1
• LOW POWER CONSUMPTION MODE
The HD630I VI has two low power consumption modes; sleep
and standby mode.
•
Data Bus
Branch Offset
Restart Address (lSB)
First op Code of Branch Routine
Next Op Code
1
Offset
Restart Address (lSB)
Return Address (LSB)
Return Address (MSB)
First op Code of Subroutine
CPU.
This sleep mode is available to reduce an average power
consumption in the applications of the HD630lVI which may
not be always running .
SleepMode
On execution of SLP instruction, the MCU is brought to the
sleep mode. In the sleep mode, the CPU sleeps (the CPU clock
becomes inactive), but the contents of the registers in the CPU
are retained. In this mode, the peripherals of CPU will remain
active. So the operations such as transmit and receive of the
SCI data and counter may keep in operation. In this mode,
the power consumption is reduced to about 1/6 the value of
a normal operation.
The escape from this mode can be done by interrupt, RES,
STBY. The RES resets the MCU and the STBY brings it into the
standby mode (This will be mentioned later). When interrupt is
requested to the CPU and accepted, the sleep mode is released,
then the CPU is brought in the operation mode and jumps to
the interrupt routine. When the CPU has masked the interrupt,
after recovering from the sleep mode, the next instruction of
SLP starts to execute. However, in such a case that the timer
interrupt is inhibited on the timer side, the sleep mode cannot
be released due to the absence of the interrupt request to the
• Standby Mode
Bringing STBY "Low", the CPU becomes reset and all
clocks of the HD630 I V I become inactive. It goes into the
standby mode. This mode remarkably reduces the power consumptions of the HD6301 Vi.
In the standby mode, if the HD6301VI is continuously
supplied with power, the contents of RAM is retained. The
standby mode should escape by the reset start. The following
is the typical application of this mode.
First, NMI routine stacks the MCU's internal information and
the contents of SP in RAM, disables RAME bit of RAM control
register, sets the Standby bit, and then goes into the standby
mode. If the Standby bit keeps set on reset start, it means
that the power has been kept during standby mode and the
contents of RAM is normally guaranteed. The system recovery
may be possible by returning SP and bringing into the condition
before the standby mode has started. The timing relation for
each line in this application is shown in Figure 24.
Vee
~--------~I\!------~r-
HD6301Vl
STBY
I
~-------41~
I
~
Stack registers
RAM control
register set
I
I
~
Oscillator I
stabilizing
time
~
restart
Figure 24 Standby Mode Timing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
309
HD6301V1,HD63A01Vl,HD63B01Vl--------------------------------------------•
ERROR PROCESSING
Table 14 Address Error
When the HD630IVI fetches an undefined instruction or
fetches an instruction from unusable memory area, it generates
the highest priority internal interrupt, that may protect from
system upset due to noise or a program error.
Mode
I
I
I
Address $OOIF $OOIF $OOIF
• Op-Cocle Error
Fetching an undefined op-code, the HD630 1V 1 will stack the
CPU register as in the case of a normal interrupt and vector to
the TRAP (SFFEE, SFFEF), that has a second highest priority
(RES is the highest).
5
6
$0000
$0000
I
I-
$OO7F $OOIF
S0200
7
$0000
I
SOO7F
$0100
I
I
$EFFF
$EFFF
System Flow chart of HD6301 VI is shown in Fig. 25.
• Addres. Error
When an instruction is fetched from other than a resident
ROM, RAM, or an external memory area, the CPU starts the
same interrupt as op-code error. In the case which the instruction is fetched from external memory area and that area is not
usable, the address error cannot be detected.
The addresses which cause address error in particular mode
are shown in Table 14.
This feature is applicable only to the instruction fetch, not to
normal read/write of data accessing.
310
2,4
0
1
$0000 $0000 $0000
Transitions among the active mode, sleep mode, standby
mode and reset are shown in Fig. 26.
Figures 27, 28, 29 and 30 shows a system configuration.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - H D 6 3 0 1 V1 ,HD63A01 V1 ,HD6 3 B01 V1
PCl
~
~
PCH
MSP
MSP-l
IXl -- MSP-2
IXH
~MSP-3
ACCA
- MSP-4
ACCB
• MSP-S
CCR -. MSP-6
Figure 25
HD6301V1 System Flow Chart
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
311
HD6301V1,HD63A01V1,HD63B01V1-----------------------
Figure 26 Transitions among Active Mode, Standby Mode,
Sleep Mode, and Reset
vee
Vee
c:::J
Enable
Enable
NMI
NMI
IRQ I
iRa,
Port 3
8 Transfer
RES
LInes
Port 1
PorI 1
81/0 Lones
81/0
L,,~es
Port 2
5110 L,nes
Port 4
8110 Lones
SCI
16 Bol Tomer
312
81/0 Lones
SCI
vss
VSS
Figure 27
Port 4
PorI 2
5110 Lones
HD6301Vl MCU Single-Chip Dual Processor Configuration
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - H D 6 3 0 1 V1 ,HD63A01 V1 ,HD63 801 V1
HD6301Vl
=
MCU
Address
Bus
Figure 28
Data
Bus
Address Bus
HD6301 V1 MCU Expanded Non-Multiplexed Mode
(Mode 5)
Figure 29
HD6301Vl MCU
16
Addre .. Bus
Figure 30
Data Bus
HD6301 V1 MCU Expanded Multiplexed Mode
Enable
8
Data Bus
HD6301V1 MCU Expanded Non-Multiplexed Mode (Mode 1)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
313
HD6301V1,HD63A01V1,HD63B01V1-------------------------------------------• PRECAUTION TO THE BOARD DESIGN OF OSCILLATION CIRCUIT
As shown in Fig. 31, there is a case that the cross talk dis-
k-20mm max---J
I
I
~ Avoid signal lines
~~~~~~~~~~~~_~:::~i:n this area.
turbs the nonnal oscillation if signal lines are put near the
oscillation circuit. When designing a board, pay attention to
this. Crystal and CL must be put as near the HD6301 VI as
possible.
j j
1i
~
co
i
iii iii
I
~"""-~EXTAL
30------'
HD630'V'
HD630'V1
Do not use this kind of print board design.
FiQtJre 31
Precaution to the boad design of
oscillation circuit
(Top view)
Figure 32 Example of Oscillation Circuits in Board Design
Table 15 Pin Condition in Sleep Mode
~
Port'
PIO-PI?
Port 2
PZO -P Z4
Port 3
P30 -Pn
Port 4
P4C)-P4 ?
314
,
0
Pin
2.4
5
6
7
<-
<-
<-
<-
<-
+-
<-
+-
+-
<-
<-
Function
I/O Port
Lower AddreH Bus
1/0 Port
Condition
Keep the condition
just before sleep
Output "1"
Keep the condition
just before sleep
Function
I/O Port
+-
+-
Condition
Keep the condition
just before sleep
<-
+-
<-
Function
E: Lower Address
Bus
E: Data Bus
Condition
E: Output "1"
E: High Impedance
Function
Upper Address
<-
Condition
Output "'"
Se2
Output "1"
IRead Conditionl
SCI
Output AddreH
Strobe
Data Bus
E: Lower Address
Bus
E: Data Bus
Data B.Js
E: Lower AddreH
Bus
E: Data Bus
High Impedance
E: Output "'"
E: High Impedance
High Impedance
E: Output "1"
Keep the condition
E: High Impedance just before sleep
<-
Lower Address Bus
or Input Port
Upper Address Bus
or Input Port
+-
+-
Address Bus: Output "'"
Port: Keep the condition just before
sleep
+-
<-
<-
+-
<-
Output "'"
+-
+-
Output Address
Strobe
1/0 Port
1/0 Port
Keep the condition
just before sleep
Output "'"
Input Pin
$HITAC,HI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - HD6301 V1 ,HD63A01 V1 ,HD63B01 V1
Table 16 Pin Condition during RESET
~
0
Pin
5
2,4
1
P IO
Port 1
~ P I7
high impedance (input)
..
..
..
.
P20
Port 2
~ P24
high impedance (input)
..
..
..
..
Port 3
E":
P30
~
P37
Port 4
P40 ~ P47
"1" output
E: "1" output INa'el
(high impedance)
high impedance
(input)
SC 2
"1" output (READ)
SCI
E: "1" output
E: high impedance
[Note]
E: "1" output
high impedance
..
(Note)
E: "1" output
(high impedance)
..
.
..
..
..
.
.
"1" output
E :"1" output
E: "1" output'INa,.,
(high impedance)
.
..
E: "1" output
E: high impedance
.
.
high impedance
(input)
•
"1" output
high impedance
(input)
In mode 0, 2, 4, 6, port 3 is set to "1" output state during E ~ "1" and it causes the conflict with the output of external memory, Following 1 and 2 should be done to avoid the conflict;
(1) Construct the system that disables the external memory during reset,
(2) Add 4,7kn pull-down resistance to the SC, pin (AS) to make SCI pin "0" level during E ~ "1",
This operation makes port 3 high impedance state.
• PIN CONDITIONS AT SLEEP AND STANDBY STATE
• Sleep State
The conditions of power supply pins, clock pins, input pins
and E clock pin are the same as those of operation. Refer to
Table 15 for the other pin conditions.
• Standby State
Only power supply pins and STBY pin are active. As for the
clock pin EXTAL, its input is fixed internally so the MCU is
not influenced by the pin conditions. XTAL is in "I" output.
All the other pins are in high impedance.
•
DIFFERENCE BETWEEN HD6301VO and HD6301V1
The HD630lVI is an upgraded version of the HD630IVO.
The difference between HD630 I VO and HD630 I V I is shown
in Table 17.
Table 17 Difference between HD6301VO and HD6301V1
Item
HD6301VO
Operating
Mode
Mode 2: Not defined
The electrical characterElectrical
istics of 2MHz version
Character(B version) are not speciistics
fied.
Timer
high impedance
7
6
Has problem in output
compare function.
(Can be avoided by software.)
•
APPLICATION NOTE FOR HIGH SPEED SYSTEM
DESIGN USING THE HD6301V1
This note describes the solutions of the potential problem
caused by noise generation in the system using the HD6301 VI.
The CMOS ICs and LSIs featured by low power consumption
and high noise immunity are generally considered to be enough
with simply designed power source and the GND line.
But this does not apply to the applications configured of
high speed system or of high speed parts. Such high speed system may have a chance to work incorrectly because of the
twise by the transient current generated during switching.
The noise generation owing to the over current (Sometimes
it may be several hundreds rnA for peak level.) during switching
may cause data write error.
This noise problem may be observed only at the Expanded
Mode (Mode I, 2, 4, 5 and 6) of the HD630lVI. The Single
Chip Mode (Mode 7) of the HD6301 V I has no such a problem_
HD6301V1
Mode 2: Expanded
Multiplexed Mode
(Equivalent to Mode 4)
Some characteristics
are improved.
The 2MHz version is
guaranteed.
The problem is solved.
Assuming the HD630 I V I is used as CPU in a system.
I. Noise Occurrence
If the HD630lVI is connected to high speed RAM, a write
error may occur. As shown in Fig. 33, the noise is generated in
address bus during write cycle and data is written into an unexpected address from the HD630 I VL This phenomenon causes
random failures in systems whose data bus load capacitance
exceeds the specification value (90 pF max.) and/or the impedance of the GND line is high.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
315
HD6301V1 ,HD63A01V1 ,HD63B01 V 1 - - - - - - - - - - - - - - - - - - - - - -
E
I
\
/
AS
RfW
\
I
\
\
(SC 2 )
I
X
A,-A l5
(Port 4)
----X
(
0 0 -0,
(Port 3)
X
A"--- Noise
)--
Fig. 33 Noise Occurrence in address bus during write cycle
If the data bus Do - D7 changes from "FF" to "00", extremely large transient current flows through the GND line.
Then the noise is generated on the LSI's V'§, pins proportioning
to the transient current and to the impedance [Zg] of the GND
line.
Oo-......-df-<
Zg
N
Vn: Noise Voltage Zg: GNO Impedance
Cd: Data bus load capacitance
N: Number of data bus lines switching from H to L
Fig. 35 Dependency of the noise voltage on each parameter
Fig. 34 Noise Source
This noise level, Vn , appears on all output pins on the LSI
including the address bus.
Fig. 35 shows the dependency of the noise voltage on the
each parameter.
II. Noise Protection
To avoid the noise on the address bus during the system
operation mentioned before, there are two solutions as follows:
The one method is to isolate the HD630 1V 1 from peripheral
devices so that peripherals are not affected by the noise. The
other is to reduce noise level to the extent of not affecting peripherals using analog method.
1. Noise Isolation
Addresses should be latched at the negative edge of the
AS signal or at the positive edge of the E signal. The 74LS373
is often used in this case.
316
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------HD6301V1,HD63A01V1,HD63B01V1
trolling those analog parameters.
(a) Transient Current Reduction
(I) Reduce the data bus load capacitance. If large load
capacitance is expected, a bus buffer should be inserted.
(2) Lower the power supply voltage V cc within specification.
(3) Increase a time constant at transient state by inserting a resistor (loa ~ 200n) to Data Buses in series
to keep noise level down .
Table 18 shows the relationship between a series
resistors and noise level or a resistor and DC/ AC
characteristics.
, - - - - - - . . - -.. Do - 0,
P 30 -
P37
1+---4"'---1
Ao - A,
HD6301V1
......- - _ A . -AI5
AS
' " Additional Latch
(74LS373 for
R
Di~~~---~------r--------r_---·
noise isolation)
2. Noise Reduction
As the noise level depends on each parameter such Cd, Vee,
Zg, the noise level can be reduced to the allowable level by con-
HD6301V1
Table 18.
No
lOOn
1.6mA
1.6mA
Item
Noise Voltage Level
DC Characteristics
See Fig. 36
IOL
f = 1 MHz
AC
Characteristics
f = 2 MHz
tADL
190 ns
190 ns
210 ns
tACCM
395 ns
395 ns
375 ns
tADL
160 ns
180 ns
200 ns
tASL
20 ns
20 ns
o ns
270 ns
250 ns
230 ns
t ACCM
Fig. 36 shows an example of the dependency of the noise
voltage on the load capacitance of the data bus. *
1.5
c
>
i
:
W
~
Vcc = 5.0V
Ta = 25°C
Zg = 0
N=8
Cd = 90 pF
~
08
5:
"Note: The value of series resistor should be carefully selected because it
heavily depends on each parameter of actual application system.
Maximum allowed )
load capacitance of
the HD6301V1
specification
f'O _L___~
______ :____
o
>
Fig 37 shows the typical wave form of the noise.
R=O
E pin
R=100n
~R=200n
'0
2
1.0mA
No change
f = 1.5 MHz
collditions
200n
0.5
~~ng
;
V~
I
I
A. pin
R Series Resistor
OL--------.------~,_------
50
100
__
Cd (pF)
Fig. 37
Data bus load capacitance
Fig. 36
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
317
H 06301 V1 ,H063A01 V1 ,H 063801 V 1 - - - - - - - - - - - - - - - - - - - - - - (3) Insert a bypass capacitor between the Vee line and the
GND of the HD630IVl. A tantalum capacitor (about
O.IJ.lF) is effective on the reduction.
(b) Reduction of GND line impedance
(1) Widen the GND line width on the PC board.
(2) Place theHD630I VI close by power source.
~~-------T--------r_------~--~r_____
Power
Source
~~~------~--------~------~----~~
(Recommended)
Power
Source
~-,---------~------~--------~~
Fig. 38 Layout of the HD6301 V1 on the PC board
• RECEIVE MARGIN OF THE Set
Table 19
Receive margin of the SCI contained in the HD630lVI is
shown in Table 19.
Note: SCI = Serial Communication Interface
START
3
Bit distortion tolerance
(t-to) Ito
Character distortion tolerance
(T -To) ITo
±37.5%
+3.75%
-2.5%
6
4
8
STOP
Ideal Waveform
Bit length j--to-.j
1
I - 0 0 1 - - - - - - - - - - Character length To - - - - - - - - - - - . . 1
Real Waveform
1 + - - - -_ _
318
T_~t~
_ _
__+l.1
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6301 XO ,HD63A01 XO , - - HD63B01XO
CMOS MCU (Microcomputer Unit)
The HD630IXO is a CMOS single-chip microcomputer unit
(MCU) which includes a CPU compatible with the HD6301VI,
4k bytes of ROM, 192 bytes of RAM, 53 parallel I/O pins, a
Serial Communication Interface (SCI) and two timers on chip.
•
•
•
•
•
•
•
HD6301XOP, HD63A01XOP,
HD63B01XOP
FEATURES
I nstruction Set Compati ble with the H D630 1V 1
Abundant On-chip Functions
4k Bytes of ROM, 192 Bytes of RAM
53 Parallel I/O Ports
16-Bit Programmable Timer
a-Bit Reloadable Timer
Serial Communication Interface
Memory Re,ady
Halt
Error-Detection (Address Trap, Op Code Trap)
Interrupts ... 3 External, 7 Internal
Operation Mode
Mode 1 ... Expanded (Internal ROM Inhibited)
Mode 2 ... Expanded (Internal ROM Valid)
Mode 3 ... Single-chip Mode
Low Power Dissipation Mode
Sleep
Standby
Wide Range of Operation
Vee = 3 - 6V (f = 0.1 - 0.5MHz).
Vee = 5V±10%( f = 0.1 - 1.0MHz; HD6301XO )
f = 0.1 - 1.5MHz; HD63A01XO
f = 0.1 - 2.0MHz; HD63BOl XO
(DP·64S1
HD6301XOF, HD63AOl XOF,
HD63B01XOF
(FP-80)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
319
HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------• PIN ARRANGEMENT
•
HD6301XOP, HD63A01XOP, HD63B01XOP
a
Vat!
XTAl
•
HD6301XOF, HD63A01XOF, HD63B01XOF
0
;:.
EXTAl;
....
MP.
MP,
lIES
STay
7
NMi~
Pzo •
P"
Paz
,
p..
p,.
p,.
p,.
P"
p..
p.,
P"
p..
PM
p..
PH
, P..,
P"
PIO
'41
'"
'42
POI
p..
Po
p..
p..
PM
PI.
p..
PH
'.7
P,, _ _ _ _ _ _--i..- Vee
(Top View)
(Top View)
• BLOCK DIAGRAM
v.. _ __
.. !
v.--_
..:
! !
I I
P.,(Tin)
p,,(T.... ')--~~
p""iffi
P"fSCLK) ---t-I~
P'tlWi'
Pu(Rx)
P"tRlR
PU(TK)
Pl'.J/CTR
PHfT....2)--.H+++-I
P'.. /SA
'.,(T0ut3)-H+~+-f
PuITCLK)-f"iY+l+H-4
'..,.IIIl:r.)
',,/IIIlli)
Pu(MR)
P,oIRArTl
p..
p.,
P"
P"
p..
p.
p.
.I
RAM
ROM
112 B....
4k B....
P"
320
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 - +7.0
V
Input Voltage
Yin
-0.3 - Vee+0.3
Operating Temperature
Topr
V
°c
Storage Temperature
Tstg
(NOTE)
0-+70
°c
-55 - +150
This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection
circuits. To assure the normal operation. we recommend Vin • Vout : Vss;::; (V in or Vout ) ;::; Vee.
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee
= 5.0V±10%, Vss = OV, Ta = 0 -
Item
+70°C, unless otherwise noted.)
Test Condition
Symbol
RES, STay
Input "High" Voltage
EXTAL
V 1H
Other Inputs
Input "Low" Voltage
All Inputs
V 1L
I nput Leakage Current
NMI, RES, STBY,
MP o , MP 1 , Port 5
Ilinl
Three State (off·state)
Leakage Current
Ports 1,2,3,4,6,7
IITsl1
Output "High" Voltage
All Outputs
V OH
Output "Low" Voltage
All Outputs
Darlington Drive
Current
min
typ
Vee- 0 .5
-
Vee xO .7
2.0
-
max
Unit
Vee
+0.3
V
-0.3
-
0.8
V
Yin = 0.5-V ee -0.5V
-
-
1.0
p.A
Yin = 0.5-V ee -0.5V
-
-
1.0
p.A
-
V
IOH = -200J..LA
2.4
-
IOH=-10p.A
Vee- 0.7
VOL
IOL = 1.6mA
-
-
0.4
V
Ports 2, 6
-loH
Vout = 1.5V
1.0
-
10.0
mA
Input Capacitance
All Inputs
Cin
Yin = OV, f = lMHz,
Ta = 25°C
-
-
12.5
pF
Standby Current
Non Operation
-
3.0
15.0
p.A
ISTB
= lMHz**)
= 1.5MHz**)
Sleeping (f = 2MHz**)
Operating (f = lMHz**)
Operating (f = 1.5MHz**)
Sleeping (f
I SLP
Current Dissipation *
lee
Sleeping (f
Operating (f = 2MHz**)
RAM Standby Voltage
V RAM
2.0
V
1.5
3.0
mA
2.3
4.5
mA
3.0
6.0
mA
7.0
10.0
mA
10.5
15.0
mA
14.0
20.0
mA
-
-
V
* VIH min = Vee-1.OV. VIL max = O.8V (All output terminals are at no load.)
** Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max.
values about Current Dissipations at x MHz operation are decided according to the following formula;
typo value (f = x MHz) = typo value (f = 1 MHz) x x
max. value (f = x MHz) = max. value (f = 1MHz) x x
(both the sleeping and operating)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
321
HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------•
AC CHARACTERISTICS (Vee
= 5.0V±10%, Vss = OV, Ta = O-+70°C, unless otherwise noted.)
BUS TIMING
Item
Symbol
Test
Condition
HD6301XO
HD63A01XO
min
typ
max
min
typ
10
0.666
25
Cycle Time
tCYC
1
Enable Rise Time
tEr
-
Enable Fall Time
-
25
-
Enable Pulse Width "High" Level*
tEf
PW EH
-
450
-
-
300
-
Enable Pulse Width "Low" Level*
PWEL
450
-
-
300
Address, RiWDelay Time-
tAO
-
-
250
toow
-
200
80
-
-
tHW
80
tHR
I Write
I Read
Data Delay Time
HD63B01XO
max
min
typ
10
0.5
25
-
max
Unit
25
-
-
220
-
-
-
220
-
-
-
190
ns
160
-
160
-
-
120
ns
-
ns
10
25
JJ.s
ns
25
ns
-
ns
ns
-
70
-
-
50
-
70
35
-
-
50
-
-
40
0
-
-
0
-
-
0
PWRW
450
-
-
300
-
-
220
-
ns
RD, WR Delay Time
tRWO
-
40
-
-
40
ns
tHRw
30
-
ns
200
-
-
25
tOLR
30
160
-
LTR" Delay Time
-
-
40
RD, WR Hold Time
-
-
120
ns
ITR Hold Time
tHLR
10
-
-
10
-
10
-
-
ns
MR Set-up Time*
tSMR
-
ns
MR Hold Time*
tHMR
E Clock Pulse Width at MR
PWEMR
Processor Control Set-up Time
tpcs
Data Set-up Time
Address, R!W Hold TimeWrite*
Data Hold Time
Read
RD, WR Pulse Width*
I
I
tOSR
tAH
Processor'Control Rise Time
tpcr
Processor Control Fall Time
tpcf
BA Delay Time
tSA
Oscillator Stabilization Time
tRC
PW RST
Reset Pulse Width
Fig. 1
80
ns
ns
ns
400
-
-
280
-
-
90
-
40
-
ns
9
-
-
9
-
-
0
-
-
-
230
-
9
JJ.S
200
-
-
200
-
-
200
-
-
ns
-
-
100
-
-
100
-
ns
-
100
-
100
-
100
ns
Fig.3
-
-
250
-
-
190
-
-
100
-
160
ns
Fig. 11
20
-
20
-
-
20
-
-
3
-
-
3
-
-
ms
3
-
Fig.2
Fig. 3,
10,11
Fig. 2,3
tcyc
• These timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc is
minimum (= in the highest speed operation).
PERIPHERAL PORT TIMING
Item
Symbol
HD6301XO
HD63A01XO
HD63B01XO
Test
Condition
min
typ
max
min
typ
max
min
typ
max
Unit
Peripheral Data
Set-up Time
Ports 2,3,5,6
tposu
Fig.5
200
-
-
200
-
-
200
-
-
ns
Peripheral Data
Hold Time
Ports 2, 3, 5, 6
tpOH
Fig.5
200
-
-
200
-
-
200
-
-
ns
3 4 6'7 ' tpwo
'"
Fig.6
-
-
300
-
-
300
-
-
300
ns
Del.yT;me IE~~ble
Negative Transition to
Peripheral Data Valid)
322
I
Porn 1 2
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300 ,
-----------------------HD6301XO,HD63A01XO,HD63B01XO
TIMER, SCI TIMING
Item
Timer 1 Input Pulse Width
Delay Time (Enable Positive
Transition to Timer Output)
SCI Input
Clock Cycle
II
HD63A01XO
typ
max
Test
Condition
min
typ
max
min
tPWT
Fig.8
2.0
-
-
2.0
-
-
tTOD
Fig. 7
-
-
400
-
-
Fig.8
1.0
-
2.0
-
1.0
Fig. 4, 8
-
2.0
-
-
200
-
290
-
-
Async. Mode
Clock Sync.
HD6301XO
Symbol
tscyc
Unit
tvp
max
2.0
-
-
400
-
-
400
ns
-
1.0
-
tcyc
-
-
2.0
-
-
-
200
-
-
200
ns
290
-
-
290
-
-
ns
-
-
100
-
-
ns
SCI Transmit Data Delay
Time (Clock Sync. Mode)
tTXD
SCI Receive Data Set-up
Time (Clock Sync. Mode)
tSRX
SCI Receive Data Hold Time
(Clock Sync. Mode)
tHRX
100
-
-
100
SCI Input Clock Pulse Width
Fig.4
HD63B01XO
min
tcyc
tcyc
tPWSCK
0.4
-
0.6
0.4
-
0.6
0.4
-
0.6
tscyc
Timer 2 Input Clock Cycle
ttCYC
2.0
-
-
2.0
-
-
2.0
-
-
tcyC
Timer 2 Input Clock Pulse
Width
tpwTCK
200
-
-
200
-
-
200
-
-
ns
Timer 1·2, SCI Input Clock
Rise Time
tCKr
-
-
100
-
-
100
-
-
100
ns
Timer 1·2, SCI Input Clock
Fall Time
tCKf
-
-
100
-
-
100
-
-
100
ns
Fig.8
$HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
323
HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------I-----------tcyc-----------<
~---PWEL---~
~---PWEH-----<-I
2.4V
O.SV
RO,WR
MCU Write
00-07
MCU Read
00-07
LlR
Figure 1 Mode 1, Mode 2 Bus Timing
I--------PWEMR------l
,,
E
\
'-----
O.SV
MR
Figure 2 Memory Ready and E Clock Timing
324
Hitachi America Ltd. •
2210
~HITACHI
O'Toole Ave. • San Jose, CA 95131
• (408) 435-8300
-----------------------HD6301XO,HD63A01XO,HD63B01XO
Last Instruction
Execution Cycle
Instruction Execution
Cycle
HALT Cycle
I
tBAI---1'---!I----;.......:...:.-...:...;...;.,;..--.....,
2.4V
BA
Figure 3 HALT and 8A Timing
Synchronous Clock
Transmit Data
Receive Data
---<"---
* 2.0V is high level when clock input.
2.4V is high level when clock output.
Figure 4 SCI Clocked Synchronous Timing
I
E
E
MCUWrite
----
P10-P17, P 2 0 - P 2 7 - - - - - - - - " ~-.,.,...,.....-
P30-P37, P40-P47
PSO-PS7, P70-P74------~ ~~~--
P30-P37
(Inputs)
(Outputs)
Figure 5 Port Data Set-up and Hold Times (MCU Read)
Figure 6 Port Data Delay Times (MCU Write)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
325
HD6301XO,HD63A01XO,HD63B01XO----------------------------------------------
E
Timer 1 - - - - " ' " r....,.~~~""""'r---
FRC
P21 , P25
- - - - - - . . . : . . -....
Outputs _ _ _ _ _ _ _ _...J
~=~---
(a) Timer 1 Output Timing
(b) Timer 2 Output Timing
Figure 7
Timer Output Timing
Vcc
h-----'l{
**
C
tCKf
* Timer 2; ttcyc
SCI
; tscyc
1rl
RL =2.2kQ
Test Point
R
1 S2074(ij)
or Equiv.
C =90pF for Port 1, Port 3, Port 4, E
=30pF for Port 2, Port 6, Port 7
R = 12kQ for Port 1 - Port 4, Port 6, Port 7, E
** Timer 1; tPWT
Timer 2; tPWTCK
SCI
; tPWSCK
Figure 9 Bus Timing Test Loads (TTL Load)
Figure 8 Timer 1·2, SCI Input Clock Timing
Interrupt
Test
Internal
Address Bus _ _" ....
-+-_'--_,,'-__'--_"'-_..J'--_J'-_..J'-_"'-_ _'--_"'-_ _'--_"-_...n"___"-_-"....
NMI. imr..
IR(h.IR so it provides an enable bit to
Bit 0 and 1 of the RAM port 5 control register at $0014. Refer
to "RAM/PORT 5 CONTROL REGISTER" for the details.
When one of the internal interrupts, ICI, OCI, TOI, CMI or
SIO is generated, the CPU produces internal interrupt signal
(IRQ3). IRQ3 functions just the same as IRQ! or IRQ2 except
for its vector address. Fig. 13 shows the block diagram of the
interrupt circuit.
Table 1 Interrupt Vector Memory Map
Priority
Highest
Lowest
328 \
Vector
Interrupt
MSB
LSB
FFFE
FFFF
RES
FFEE
FFEF
TRAP
FFFC
FFFD
NMI
FFFA
FFFB
SWI (Software Interrupt)
FFF8
FFF9
IRQ!
FFF6
FFF7
ICI (Timer 1 Input Capture)
FFF4
FFF5
OCI (Timer 1 Output Compare 1, 2)
FFF2
FFF3
TOI (Timer 1 Overflow)
FFEC
FFED
FFEA
FFEB
CMI (Timer 2 Counter Match)
IRQ2
FFFO
FFFl
SIO (RDRF+ORFE+TDRE)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
Each Register's Interrupt
Enable Flag
"1 "; Enable, "0"; Disable
IRQ,
IRQ2
ICF
--
OCFl
-0-
OCF2
--0-
TOF
...-...
IRQ3
CMF
RDRF
--
---0ORFE
TORE
---0-
ICI
Condition
Code
Register
I-MASK
"O";Enable
"1" ;Disable
~
~
TOI
CMI
~
Interrupt
Request
Signal
~
-)
Edge
Detective
Circuit
Sleep
Cancel
Signal
[ Address Error
TRAP
Op Code Error
Detective Circuit
SWI
Figure 13 Interrupt Circuit Block Diagram
•
Mode Program (MP o , MPd
This signal, usually be in read state ("High"), shows whether
the CPU is in read ("High") or write ("Low") state to the
peripheral or memory devices. This can drive one TTL load
and 30pF capacitance.
CPU to interface with low-speed memories (See Fig. 2). Up to
9p.s can be stretched.
During internal address space access or nonvalid memory
access, MR is prohibited internally to prevent decrease of operation speed. Even in the halt state, MR can also stretch "High"
period of system clock to allow peripheral devices to access
low-speed memories. As this signal is used also as P 52 , an enable
bit is provided at bit 2 of the RAM/port 5 control register at
$0014. Refer to "RAM/PORT 5 CONTROL REGISTER" for
more details .
•
•
•
This is an input control signal to stop instruction execution
and to release buses. When this signal switches to "Low", the
CPU stops to enter into the halt state after having executed
the present instruction. When entering into the halt state, it
makes BA (P 74 ) "High" and also an address bus, data bus, RD,
WR, R/W high impedance. When an interrupt is generated
in the halt state, the CPU uses the interrupt handler after the
halt is cancelled.
(Note)
Please don't switch the HALT signal to "Low" when the
CPU executes the WAI instruction and is in the interrupt wait
state to avoid the trouble of the CPU's operation after the halt
is cancelled.
These two pins decide the operation mode_ Refer to "MODE
SELECTION" for mode details.
The following signal descriptions are applicable only for the
expanded mode.
•
Read/Write (RM; P 72 )
RD, WR (P?I). P71 )
These signals show active low outputs when the CPU is
reading/writing to the peripherals or memories. This enables
the CPU easy to access the peripheral LSI with RD and WR
input pins. These pins can drive one TTL load and 30pF capacitance.
load Instruction Register (UR; P 73 )
This signal shows the instruction opecode being on data
bus (active low). This pin can drive one TTL load and 30pF
capacitance.
•
Memory Ready (MR; PS2 )
This is the input control signal which stretches the system
clock's "High" period to access low-speed memories. During
this signal is in "High", the system clock operates in normal
sequence. But this signal in "Low", the "High" period of the
system clock will be stretched depending on its "Low" level
duration in integral multiples of the cycle time. This allows the
•
Halt (HALT; P 53 )
Bus Available (SA; P74)
This is an output control Signal which is normally "Low"
but "High" when the CPU accepts HALT and releases the buses.
The HD6800 and HD6802 make BA "High" and release the
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
329
HD6301XO,HD63A01XO,HD63B01XO-------------------------------------------buses at WAI execution, while the HD6301XO doesn't make
BA "High" under the same condition. But if the HALT becomes
"Low" when the CPU is in the interrupt wait state after having
executed the WAI, the CPU makes BA "High" and releases the
buses. And when the HALT becomes "High", the CPU returns
to the interrupt wait state.
• PORT
The HD6301XO provides seven I/O ports (six 8-bit ports and
a 5-bit port). Table 2 gives the address of ports and the data
direction register and Fig. 14 the block diagrams of each port.
Table 2 Port and Data Direction Register Address
Port
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port Address
$0002
$0003
$0006
$0007
$0015
$0017
$0018
Data Direction Register
$0001
$0004
to port 1. When a write operation is made to port 1, the high
impedance state shifts to the output state and the written data
will be output. Once port I gets in the output state, it operates
as an output till reset occurs. The CPU can also read the value of
the Port 1 data register, thus enables the CPU to use bit manipulation.
In mode 1 and 2, port 1 acts as lower address buses. This
port can drive one TTL load and 90pF capacitance .
• Port 2
An 8-bit input/output port. The data direction register
(DDR) of port 2 controls the I/O state. It provides two bits; bit
o decides the I/O direction of P20 and bit 1 the I/O direction of
P21 to P27 ("0" for input, "I" for output).
Port 2 is also used as an I/O pin for the timers and the
SCI. When used as an I/O pin for the timers and the SCI, port
2 except P20 automatically becomes an input or an output
depending on their functions regardless of the data direction
register's value.
Port 2 Data Direction Register
$0016
-
• Port 1
An 8-bit port for output only. In mode 3, port 1 goes to high
impedance during reset and keeps the state even after accepting
reset cancellation. It continues till a write operation is made
A reset clears the DDR of port 2 and configures port 2 as an
input port. This port can drive one TTL and 30pF capacitance.
In addition, it can produce ImA current when Vout = 1.5V to
drive directly the base of Darlington transistors.
Port Write Signal
Data Bus
Data Bus
~~eb~~:~;-t-+------'
Port Read Signal
Tri-state
Control
...l....
Mode 1,2
Address Bus,
Control Signal
...L
Port 1, Port 4, Port 7
Port 2
Port Write Signal
Data Bus
CPU Internal Bus _ _ _ _ _---.J
Port 3
Data Bus
Figure 14 Port Block Diagram
330
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301XO,HD63A01XO,HD63B01XO
•
Port3
An 8-bit I/O port. The DDR of port 3 controls the I/O state.
It provides only one bit which decides I/O state by the byte
("0" for input and "I" for output). It is cleared during reset.
Port 3 can drive one TTL load and 90pF capacitance.
Port 3 Data Direction Register
o
4
1•
-- I
I-
Port 4
regardless of the value of this bit and P S2 can be used as the
I/O port. This bit becomes "1" during reset.
Bit 3 Halt Enable bit (HL TE)
When using P 53 as an input for Halt signal, write "1" in this
bit. When "0", the halt function is prohibited. In mode 3, the
halt function is prohibited regardless of the value of this bit and
P S3 can be used as the I/O port. This bit becomes "1" during
reset.
(Note)
When using P S2 and P S3 as the input ports in mode I and 2,
MRE and HLTE bit should be cleared just after the reset. Notice
that memory ready and halt function is enable till MRE and
HL TE bit is cleared.
An 8-bit port for output only like Port 1. In mode 1 and 2,
"High" address will be produced.
Bit 4, Bit 5 Not Used.
•
Bit 6 RAM Enable (RAME)
Port 5
An 8-bit port for input only. The lower four bits are also
usable as input pins for interrupt, MR and HALT.
•
Port 6
An 8-bit I/O port. This port provides an 8-bit DDR corresponding to each bit and can specify input or output by the
bit ("0" for input, "}" for output). This port can drive one
TTL load and 30pF capacitance. A reset clears the DDR of port
6. In addition, it can produce ImA current when Vout
I.SV to drive directly the base of Darlington transistors.
•
Port 7
A 5-bit port for output only. In mode 3, port 7 goes to high
impedance during reset and keeps the state even after accepting
reset cancellation. It continues till a write operation is made to
port 7. When a write operation is made to port 7, the high
impedance state shifts to the output state and the written data
will be output. Once port 7 gets in the output state, it operates
as an output till reset occurs. Port 7 can also read the value of
the data register, thus enables the CPU to use the bit manipulation instruction. In this case b 7 ~ bs are" I ".
In mode 1 and 2, port 7 acts as outputs for control signals
(RD, WR, R/W, LlR and BA). This port can drive one TTL
load and 30pF capacitance.
•
On-chip RAM can be disabled by this control bit. By resetting the MCU, "1" is set to this bit, and on-chip RAM is enabled.
This bit can be written "I" or "0" by software. When RAM is
in disable condition (=logic "0"), on-chip RAM is invalid and
the CPU can read data from external memory. This bit should
be "0" before getting into the standby mode to protect onchip RAM data.
Bit 7 Standby Power Bit (STBY PWR)
When Vee is not provided in standby mode, this bit is
cleared. This is a flag for both read/write by software. If this bit
is set before standby mode, and remains set even after returning
from standby mode, Vee voltage is provided during standby
mode and the on-chip RAM data is valid.
•
MODE SELECTION
Mode program pins, MP o and MP I determine the operation
mode of the HD6301 XO as Table 3 gives.
•
Mode 1 (Expanded Mode)
In this mode, port 3 is data bus and port 1 lower address bus
and port 4 upper address bus to interface directly with the
HMCS6800 buses. A control signal such as R/W is produced at
port 7. In mode I, on-chip ROM is disabled and 6Sk bytes of
address space are externally expandable (refer to Fig. IS) .
RAM/PORT 5 CONTROL REGISTER
The control register located at $0014 controls on-chip
RAM and port S.
RAM/Port 5 Control Register
•
Mode 2 (Expanded Mode)
This mode is also expandable as well as mode 1. But in this
mode, on-chip ROM is enabled and the expandable address
space is 61k bytes (refer to Fig. 16).
•
76543210
Mode 3 (Single-chip Mode)
In this mode, all ports are available (refer to Fig. 17).
Table 3 Mode Selection
Bit 0, Bit 1 IRO I , IR0 2 Enable Bit (IROIE, IR0 2 E)
When using P so and PSI as interrupt pins, write "I" in
these bits. When "0", the CPU doesn't accept an external
interrupt or a sleep cancellation by the external interrupt.
These bits become "0" during reset.
Bit 2 Memory Ready Enable Bit (MRE)
When using P S2 as an input for Memory ReadY'signal, write
"1" in this bit. When "0", the memory ready function is prohibited. In mode 3, the memory ready function is prohibited
Mode MP I
MP o
ROM RAM
Interrupt
Vector
Operation Mode
1
"L"
"H"
E
1*
E
Expanded Mode
2
"H"
"L"
I
1*
I
Expanded Mode
3
"H"
"H"
I
I
I
Single-chip Mode
"L" = Logic "a", "H" = Logic "1", I; Internal, E; External.
• The addressing RAM area can be external by clearing RAME bit at
$0014.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
331
HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------Vee
Vee
E
AD
RD
WR
R/W
iJR
HD6301 XO
8
MR. HALT
Port 6
Port 4
8 Address Bus
81/0 Lines
BA
Port 3
8 Data Bus
Timer 1, 2 SCI
Port 5
8 ~t Lines
IRQ" fRQ2
MR. HALT
Port 6
8 I/O Lines
Port 1
8 Address Bus
~~ ~;r6~
HD6301XO
NMI
Port 2
8 1/0 Lines
Port 3
8 Data Bus
Timer 1,2
SCI
Port 5
R/Vii
LlR
RES
SfBY
BA
MCU
Port 2
81/0 Lines
WR
CJ
Port 1
8 Address Bus
Port 4
8 Address Bus
Figure 16 Mode 2
Figure 15 Mode 1
Vee
Port 7
5 Output Lines
CJ
Port 3
8 I/O Lines
Port 2
8 I/O Lines
Timer 1, 2 SCI
Port 5
8 Input Lines
ilm1.
Port 1
8 Output Lines
fRQ2
Port 6
8 I/O Lines
Port 4
8 Output Lines
Figure 17 Mode 3
•
Mode and Port
Table 4 shows MeV signals in each mode.
Table 4 MCU Signals in Each Mode
Port
~
Port 1
332
Mode 1
Mode 2
Address Bus (Ao~A7)
Mode 3
Address Bus (Ao ~ A7)
Output Port
I/O Port
Port 2
I/O Port
I/O Port
Port 3
Data Bus (Do ~D7)
Data Bus (Do ~D7)
I/O Port
Port 4
Address Bus (As ~AlS)
Address Bus (As ~ A 1S )
Port 5
Input Port
Input Port
Output Port
Input Port
Port 6
I/O Port
I/O Port
I/O Port
Port 7
RD, WR, R/W, LlR, BA
RD, WR, R/W, LlR, BA
Output Port
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301XO,HD63A01XO,HD63B01XO
•
MEMORY MAP
The MeV can address up to 65k bytes depending on its
mode. 32 internal registers use addresses from "00" as shown in
Table 5.
operation mode. Fig. 18 gives memory maps in each operation
Table 5 Internal Register
Address
Registers
00
-
R/W***
-
Initialize at RESET
W
$FC
-
01
02*
Port 2 Data Direction Register
Port 1
R/W
Undefined
03
04*
Port 2
R/W
Undefined
W
-
$FE
Port 3
Port 4
R/W
R/W
Undefined
Undefined
Timer Control/Status Register 1
Free Running Counter ("High")
R/W
$00
R/W
$00
OA
Free Running Counter ("Low")
R/W
$00
OB
Output Compare Register 1 ("High")
R/W
$FF
DC
Output Compare Register 1 ("Low")
R/W
$FF
OD
Input Capture Register ("High")
R
$00
DE
Input Capture Register ("Low")
R
$00
OF
Timer Control/Status Register 2
R/W
$10
10
Rate, Mode Control Register
R/W
$00
11
Tx/Rx Control Status Register
R/W
$20
12
Receive Data Register
R
$00
13
Transmit Data Reg,ister
W
14
RAM/Port 5 Control Register
05
06*
07*
08
09
Port 3 Data Direction Register
-
R/W
-
$00
$7C or $FC
-
15
Port 5
R
16
Port 6 Data Direction Register
W
$00
17
18*
Port 6
R/W
Undefined
Port 7
R/W
Undefined
19
Output Compare Register 2 ("High")
R/W
$FF
1A
Output Compare Register 2 ("Low")
R/W
$FF
1B
Timer Control/Status Register 3
R/W
$20
1C
Time Constant Register
W
$FF
1D
Timer 2 Up Counter
R/W
$00
1E
1F**
Test Register
-
-
-
-
• External Address in Mode 1,2.
** Test Register. Do not access to this register .
• ** R : Read Only Register
W : Write Only Register
R/W: Read/Write Register
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
333
HD6301XO,HD63A01XO,HD63B01XO------------------------------------------HD6301XO
Expanded Mode
HD6301XO
Expanded Mode
Mode 1
Internal"
Registers
External
Memory
Space
$0040
Mode 2
Register
External
Memory
Space
Internal
RAM
I'""'"'"
Internal
RAM
$OOFF
HD6301XO
Single-chip Mode
Mode 3
$0000~1Inte~nal
$001 F
Register
$0040
Internal
RAM
$OOFF
External
Memory
Space
External
Memory
Space
$FOOO
$FOOO
Internal
ROM
$FFFF
$FFFF
Internal
ROM
$FFFF
* Excludes the following addresses
• Excludes the following addresses
which may be used externally:
$02. $04. $06. $07. $18.
which may be used externally:
$02. $04. $06. $07. $18.
Figure 18 HD6301 XO Memory Map
•
•
TIMER 1
The HD630IXO provides a I6-bit programmable timer which
can simultaneously measure an input waveform and generate
two independent output waveforms. The pulse widths of both
input/output waveforms vary from microseconds to seconds.
Timer 1 is configurated as follows (refer to Fig. 20).
• Control/Status Register 1 (8 bit)
• Control/Status Register 2 (7 bit)
• Free Running Counter (I6 bit)
• Output Compare Register 1 (16 bit)
• Output Compare Register 2 (16 bit)
• Input Capture Register ( 16 bit)
•
Free-Running Counter (FRC) ($0009 : OOOA)
The key timer element is a I6-bit free-running counter driven
and incremented by system clock. The counter value is readable
by software without affecting the counter. The counter is
cleared by reset.
When writing to the upper byte ($09), the CPU wntes the
preset value ($FFF8) into the counter (address $09, $OA)
regardless of the write data value. But when writing to the
lower. byte ($OA) after the upper byte writing, the CPU writes
not only the lower byte data into lower 8 bit, but also the upper
byte data into higher 8 bit of the FRC.
The counter will be as follows when the CPU writes to it by
double store instructions (STD, STX etc.).
$09 Write
Counter value
$OA Write
$FFF8
$5AF3
In the case of the CPU write ($5AF3) to the FRC
Output Compare Register (OCR)
($0008, $OOOC; OCR1) ($0019, $001A ;OCR2)
The output compare register is a 16-bit read/write register
which can control an output waveform. The data of OCR is
always compared with the FRC.
When the data matches, output compare flag (OCF) in the
timer control/status register (TCSR) is set. If an output enable
bit (OE) in the TCSR2 is "1", an output level bit (OLVL) in the
TCSR will be output to bit 1 (Tout 1) and bit 5 (Tout 2) of
port 2. To control the output level again by the next compare,
the value of OCR and OLVL should be changed. The OCR is set
to $FFFF at reset. The compare function is inhibited for a cycle
just after a write to the OCR or to the upper byte of the FRC.
This is to begin the comparison after setting the I6-bit value
valid in the register and to inhibit the compare function at this
cycle, because the CPU writes the upper byte to the FRC, and
at the next cycle the counter is set to $FFF8.
* For data write to the FRC or the OCR, 2-byte transfer instruction (such as STX etc.) should be used.
•
Input Capture Register (lCR) ($0000: OOOE)
The input capture register is a 16-bit read only register which
stores the FRC's value when external input signal transition
generates an input capture pulse. Such transition is controlled
by input edge bit (IEDG) in the TCSRI.
In order to input the external input signal to the edge detecter, a bit of the DDR corresponding to bit 0 of port 2 should be
cleared ("0"). When an input capture pulse occurs by the external input signal transition at the next cycle of CPU's highbyte read of the ICR, the input capture pulse will be delayed by
one cycle. In order to ensure the input capture operation, a
CPU read of the ICR needs 2-byte transfer instruction. The
input pulse width should be at least 2 system cycles. This register is cleared ($0000) during reset.
Figure 19 Counter Write Timing
334
Hitachi America Ltd. •
2210
~HITACHI
O'Toole Ave. • San Jose, CA 95131
• (408) 435-8300
-----------------------HD6301XO,HD63A01XO,HD63B01XO
•
Timer Control/Status Register 1 (TCSR1) ($0008)
The timer control/status register 1 is an 8·bit register. All bits
are readable and the lower 5 bits are also writable. The upper 3
bits are read·only which indicate the following timer status.
Bit 5 The counter value reached to $0000 as a result of
counting·up (TOF).
Bit 6 A match has occured between the FRC and the OCR 1
(OCFl).
Bit 7 Defined transition of the timer input signal causes the
counter to transfer its data to the ICR (ICF).
The followings are each bit descriptions.
•
Timer Control/Status Register 2 (TCSR2) ($OOOF)
The timer control/status register 2 is a 7 ·bit register. All bits
are readable and the lower 4 bits are also writable. But the
upper 3 bits are read-only which indicate the following timer
status.
Bit 5 A match has occured between the FRC and the OCR2
(OCF2).
Bit 6 The same status flag as the OCFI flag of the TCSR I,
bit 6.
Bit 7 The same status flag as the ICF flag of the TCSRI , bit 7.
The followings are the each bit descriptions.
Timer Control/Status Register 1
Timer Control/Status Register 2
6
76543210
ICF 1OCF,I OCF21 - IEOCI2f LVL21OE21 O~ $OOOF
Bit 0
Bitl
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
OL VL 1 Output Levell
OLVLl is transferred to port 2, bit I when a match
occurs between the counter and the OCRI. If bit 0 of
the TCSR2 (OEI) is set to "I", OLVLl will appear at
bit I of port 2.
IEDG InputEdge
This bit determines which edge, rising or falling of
input signal of port 2, bit 0 will trigger data transfer
from the counter to the ICR. For this function, the
DDR corresponding to port 2, bit 0 should be cleared
beforehand.
IEDG=oO, triggered on a falling edge
("High" to "Low")
IEDG=oI, triggered on a rising edge
("Low" to "High")
ETOI
Enable Timer Overflow Interrupt
When this bit is set, an internal interrupt (IRQ3) by
TO! interrupt is enabled. When cleared, the interrupt is
inhibited.
EOCll
Enable Output Compare Interrupt 1
When this bit is set, an internal interrupt (IRQ3) by
OCI1 interrupt is enabled. When cleared, the interrupt
is inhibited.
EICI
Enable Input Capture Interrupt
When this bit is set, an internal interrupt (IRQ3) by
ICI interrupt is enabled. When cleared, the interrupt is
inhibited.
TOF
Timer Overflow Flag
This read·only bit is set when the counter incre·
ments from SFFFF by I. Cleared when the counter's
the upper byte (S0009) is read by the CPU after the
TCSRI read.
OCFl Output Compare Flag 1
This read·only bit is set when a match occurs be·
tween the OCRI and the FRC. Cleared when writing to
the OCRI (SOOOB or SOOOC) after the TCSRI or
TCSR2 read.
ICF
Input Capture Flag
This read·only bit is set when an input signal of
port 2. bit 0 makes a transition as defined by IEDG
and the FRC is transferred to the ICR. Cleared when
reading the upper byte (SOOOD) of the ICR after the
TCSR I or TCSR2 read.
Bit 0
OEl Output Enable 1
This bit enables the OLVLl to appear at port 2, bit
I when a match has occurred between the counter and
the output compare register I. When this bit is cleared,
bit I of port 2 will be an I/O port. When set, it will be
an output ofOLVLl automatically.
Bit 1 OE2 Output Enable 2
This bit enables the OLVL2 to appear at port 2, bit
5 when a match has occurred between the counter and
the output compare register 2. When this bit is cleared,
port 2, bit 5 will be an I/O port. When set, it will be an
output of OLVL2 automatically.
Bit 2 OLVL2 Output Level 2
OLVL2 is transferred to port 2, bit 5 when a match
has occurred between the counter and the OCR2. If
bit 5 of the TCSR2 (OE2) is set to "I", OLVL2 will
appear at port 2, bit 5.
Bit 3 EOCI2 Enable Output Compare Interrupt 2
When this bit is set, an internal interrupt (IRQ3) by
OCI2 interrupt is enabled. When cleared, the interrupt
is inhibited.
Bit 4 Not Used
Bit 5 OCF2 Output Compare Flag 2
This read-only bit is set when a match has occurred
between the counter and the OCR2. Cleared when
writing to the OCR2 (SOOI9 or SOOIA) after the
TCSR2 read.
Bit 6 OCFl Output Compare Flag 1
Bit 7 ICF Input Capture Flag
OCF 1 and ICF addresses are partially decoded.
The CPU read of the TCSRI/TCSR2 makes it possible
to read OCFI and ICF into bit 6 and bit 7.
Both the TCSRI and TCSR2 will be cleared during reset.
(Note)
If OEI or OE2 is set to "I" before the first output compare
match occurs after reset restart, bit I or bit 5 of port 2 will
produce "0" respectively.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
335
HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------
Figure 20 Timer 1 Block Diagram
•
•
TIMER2
In addition to the timer 1, the HD630 I XO provides an 8-bit
reloadable timer, which is capable of counting the external
event. This timer 2 contains a timer output, so the MCU can
generate three independent waveforms. (Refer to Fig. 21.)
The timer 2 is configured as follows:
Control/Status Register 3 (7 bit)
8-bit Up Counter
Time Constant Register (8 bit)
•
Time Constant Register (TCONR) ($001C)
The time constant register is an 8-bit write only register. It
is always compared with the counter.
When a match has occurred, counter match flag (CMF) of
the timer control status register 3 (TCSR3) is set and the value
selected by TOSO and TOSI of the TCSR3 will appear at port 2,
bit 6. When CMF is set, the counter will be cleared simultaneously and then start counting from $00. This enables regular
interrupts and waveform outputs without any software support.
The TCONR is set to "$FF" during reset.
Timer 2 Up Counter (T2CNT) ($0010)
This is an 8-bit up counter which operates with the clock
decided by CKSO and CKSI of the TCSR3. The CPU can read
the value of the counter without affecting the counter. In addition, any value can be written to the counter by software even
during counting.
The counter is cleared when a match occurs between the
counter and the TCONR or during reset.
If a write operation is made by software to the counter at the
cycle of counter clear, it does not reset the counter but put the
write data to the counter.
336
•
Timer Control/Status Register 3 (TCSR3) ($0018)
The timer control/status register 3 is a 7-bit register. All bits
are readable and 6 bits except for CMF can be written.
The followings are each pin descriptions.
Timer Control/Status Register 3
76543210
I CMF IECMII - I T2E ITOS11TosoICKS11CKSoI $0018
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------HD6301XO,H063A01XO,HD63B01XO
r----- Timer1
FRC
....---+-- Port 2
Bit 7
~+---~------+~~Port2
BitS
IRQ3
Figure 21
Bit 0
Bit 1
CKSO
C,KS1
Timer 2 Block Diagram
Input Clock Select 0
Input Clock Select 1
Table 7 Timer 2 Output Select
Input clock to the counter is selected as shown in
Table 6 depending on these two bits. When an external
clock is selected, bit 7 of port 2 will be a clock input
automatically. Timer 2 detects the rising edge of the
external clock and increments the counter. The external
clock is countable up to half the frequency of the
system clock.
Table 6 Input Clock Select
CKS1
CKSO
0
0
E clock
0
1
E clock/8*
1
0
E clock/128*
1
1
External clock
Input Clock to the Counter
TOS1
TOSO
0
0
Timer Output
Timer Output Inhibited
0
1
Toggle Output*
1
0
Output "0"
1
1
Output "1"
• When a match occurs between the counter and the TeONR, timer 2
output level is reversed. This leads to production of a square wave with
50% duty to the external without any software support,
Bit 4
T2E
Timer 2 Enable Bit
When this bit is cleared, a clock input to the up
counter is prohibited and the up counter stops. When set
to "1 ", a clock selected by CKSI and CKSO (Table 6) is
input to the up counter.
(Note)
• These clocks come from the FRC of the timer 1. If one of these clocks
is selected as an input clock to the up counter, the CPU should not
write to the FRC of the timer 1.
P26 outputs "0" when T2E bit cleared and timer 2. set in
output enable condition by TOSI or TOSO. It also outputs "0"
when T2E bit set" 1" and timer 2 set in output enable condition before the first counter match occurs.
Bit 2
Bit 3
Bit 5
Bit 6
TOSO
TOS1
Timer Output Select 0
Timer Output Select 1
When a match occurs between the counter and the
TCONR timer 2 outputs shown in Table 7 will appear at
port 2, bit 6 depending on these two bits. When both
TOSO and TOSI are "0", bit 6 of port 2 will be an I/O
port.
Hitachi America Ltd. •
2210
Not Used
ECMI Enable Counter Match Interrupt
When this bit is set, an internal interrupt (IRQ3) by
CMI is enabled. When cleared, the interrupt is inhibited.
Bit 7
CMF
Counter Match Flag
This read-only bit is set when a match occurs between
the up counter and the TCONR. Cleared by writing
"0" by software (unable to write "1" by software).
Each bit of the TCSR3 is cleared during reset.
~HITACHI
O'Toole Ave. • San Jose, CA 95131
337
• (408) 435-8300
HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------• SERIAL COMMUNICATION INTERFACE (SCI)
The HD6301XO SCI contains two operation modes; one is an
asynchronous mode by the NRZ format and the other is a
clocked synchronous mode which transfers data synchronizing
with the serial clock.
The SCI consists of the following registers as shown in Fig.
22 Block Diagram:
• Control/Status Register (TRCSR)
• Rate/Mode Control Register (RMCR)
• Receive Data Register (RDR)
• Receive Data Shift Register (RDSR)
• Transmit Data Register (TDR)
• Transmit Data Shift Register (TDSR)
The serial I/O hardware requires an initialization by software
for operation. The procedure is usually as follows:
/'i) Write a desirable operation mode into each corresponding control bit of the RMCR.
2) Write a desirable operation mode into each corresponding control bit of the TRCSR.
When using bit 3 and 4 of port 2 for serial I/O only, there is
no problem even if TE and RE bit are set. But when setting the
baud rate and operation mode, TE and RE should be "0". When
clearing TE and RE bit and setting them again, more than I bit
cycle of the current baud rate is necessary. If set in less than I
bit cycle, there may be a case that the internal transmit/receive
initialization fails.
•
Asynchronous Mode
An asynchronous mode contains the following two data
formats:
I Start Bit + 8 Bit Data + I Stop Bit
I Start Bit + 9 Bit Data + I Stop Bit
In addition, if the 9th bit is set to " 1" when making 9
bit data format, the format of
1 Start bit + 8 Bit Data + 2 Stop Bit
is also transferred.
Data transmission is enabled by setting TE bit of the TRCSR,
then port 2, bit 4 will become a serial output independently of
the corresponding DDR.
For data transmit, both the RMCR and TRCSR should be
set under the desirable operating conditions. When TE bit is
set during this process, 10 bit preamble will be sent in 8-bit data
format and 11 bit in 9-bit data format. When the preamble is
produced, the internal synchronization will become stable and
the transmitter is ready to act.
The conditions at this stage are as follows.
1) If the TDR is empty (TORE=I), consecutive I's are
produced to indicate the idle state.
338
Hitachi America Ltd. •
2210
2) If the TDR contains data (TDRE=O), data is sent to the
transmit data shift register and data transmit starts.
During data transmit, a start bit of "0" is transmitted first.
Then 8-bit or 9-bit data (starts from bit 0) and a stop bit "1"
are transmitted.
When the TOR is "empty", hardware sets TORE flag bit. If
the CPU doesn't respond to the flag in proper timing (the TDRE
is in set condition till the next normal data transfer starts from
the transmit data register to the transmit sift register), "I" is
transferred instead of the start bit "0" and continues to be
transferred till data is provided to the data register. While the
TDRE is "I ", "0" is not transferred
Data receive is possible by setting RE bit. This makes port 2,
bit 3 a serial input. The operation mode of data receive is
decided by the contents of the TRCSR and RMCR. The first
"0" (space) synchronizes the receive bit flow. Each bit of the
following data will be strobed in the middle. If a stop bit is not
"I", a framing error assumed and ORFE is set.
When a framing error occurs, receive data is transferred to
the receive data register and the CPU can read error-generating
data. This makes it possible to detect a line break.
If the stop bit is "1", data is transftmed to the receive data
register and an interrupt flag RORF is set. If RDRF is still
set when receiving the stop bit of the next data, ORFE is set to
indicate overrun generation.
When the CPU read the receive data register as a response to
RDRF flag or ORFE flag after having read TRCS, RORF or
ORFE is cleared.
(Note) Clock Source in Asynchronous Mode
If CCI: CCO = 10, the internal bit rate clock is provided at
P22 regardless of the values for TE or RE. Maximum clock rate
is E -7 16.
If both CCI and CCO are set, an external TTL compatible
clock must be connected to P 22 at sixteen times (16x) the
desired bit rate, but not greater than E.
•
Clocked Synchronous Mode
In the clocked synchronous mode, data transmit is
synchronized with the clock pulse. The HD630lXO SCI
provides functionally independent transmitter and receiver
which makes full duplex operation possible in the asynchronous
mode. But in the clocked synchronous mode an SCI clock I/O
pin is only P 22 , so the simultaneous receive and transmit
operation is not available. In this mode, TE and RE should
not be in set condition (" I") simultaneously. Fig. 23 gives a
synchronous clock and a data format in the clocked synchronousmode.
~HITACHI
O'Toole Ave. • San Jose, CA 95131
• (408) 435-8300
----------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
Timerl FRC,
Timer2
Up Counter
Figure 22 Serial Communication Interface Block Diagram
Data transmit is realized by setting TE bit in the TRCSR.
Port 2, bit 4 becomes an output unconditionally independent
of the value. of the corresponding DDR.
Both the RMCR and TRCSR should be set in the desirable
operating condition for data transmit.
When an external clock input is selected, data transmit is
performed under the TDRE flag "0" from port 2, bit 4, synchronizing with 8 clock pulses input from external to port 2,
bit 2.
Data is transmitted from bit 0 and the TDRE is set when the
transmit data shift register is "empty". More than 9th clock
pulse of external are ignored.
Transmit Direction
Synchronous
clock
Data
~NotValid
• Transmit data is produced from a falling edge of a synchronous clock to the next falling edge .
• Receive data is latched at the rising edge.
Figure 23 Clocked Synchronous Mode Format
When data transmit is selected to the clock output, the MCU
produces transmit data and synchronous clock at TDRE flag
clear.
Data receive is enabled by setting RE bit. Port 2, bit 3 will
be a serial input. The operating mode of data receive is decided
by the TRCSR and the RMCR.
If the external clock input is selected, RE bit should be set
when P22 is "High". Then 8 external clock pulses and the
synchronized receive data are input to port 2, bit 2 and bit
3 respectively. The MCU put receive data into the receive
data shift register by this clock and set the RDRF flag at the
termination of 8 bit data receive. More than 9th clock pulse of
external input are ignored. When RDRF is cleared by reading
the receive data register, the MCU starts receiving the next data.
So RDRF should be cleared with P22 "High"
When data receive is selected to the clock output, 8 synchronous clocks are output to the external by setting RE bit. So receive data should be input from external, synchronously with
this clock. When the first byte data is received, the RDRF flag
is set. After the second byte, receive operation is performed and
output the synchronous clock to the external by clearing the
RDRF bit.
• Transmit/Receive Control Status Register (TRCSR) ($0011)
The TRCSR is composed of 8 bits which are all readable. Bits
o to 4 are also writable. This register is initialized to $20 during
reset. Each bit functions as follows.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
339
HD6301XO,HD63A01XO,HD63B01XO---------------------------------------------Transmit/Receive Control Status Register
76543
10
IRDRFIORFEITDREI RIE I RE I TIE I TE I WU
Bit 0
/ $0011
WU Wake-up
In a typical multi-processor configuration, the
software protocol provides the destination address at
the first byte of the message. In order to make uninterested MCV ignore the remaining message, a wake-up
function is available. By this, uninterested MCV can inhibit all further receive processing till the next message
starts.
Then wake-up function is triggered by consecutive
1's with 1 frame length (10 bits for 8-bit data, 11 for
9-bit). The software protocol should provide the idle
time between messages.
By setting this bit, the MCV stops data receive till the
next message. The receive of consecutive" 1" with one
frame length wakes up and clears this bit and then the
MeV restarts receive operation. However, the RE flag
should be already set before setting this bit. In the
clocked synchronous mode WU is not available, so this
bit should not be set.
Bit 1 TE Transmit Enable
When this bit is set, transmit data will appear at port
2, bit 4 after one frame preamble in asynchronous mode,
while in clocked synchronous mode it appears immediately. This is executed regardless of the value of the
corresponding DDR. When TE is cleared; the serial I/O
doesn't affect port 2, bit 4.
Bit 2 TIE Transmit Interrupt Enable
When this bit is set, an internal interrupt (IRQ3) is
enabled when TDRE (bit 5) is set. When cleared, the
interrupt is inhibited.
Bit 3 RE Receive Enable
When set, a signal is input to the receiver from port
2, bit 3 regardless of the value of the DDR. When RE
is cleared, the serial I/O doesn't affect port 2, bit 3.
Bit 4 RIE Receive Interrupt Enable
When this bit is set, an internal interrupt, IRQ3 is
enabled when RDRF (bit 7) or ORFE (bit 6) is set.
When cleared, the interrupt is inhibited.
Bit 5 TORE Transmit Data Register Empty
TDRE is set when the TDR is transferred to the
transmit data shift register in the asynchronous mode,
while in clocked synchronous mode when the TDSR is
"empty". This bit is reset by reading the TRCSR and
writing new transmit data to the transmit data register.
TDRE is set to "1" during reset.
(Note)
TDRE should be cleared in the transmittable state after the
TEset.
Bit 6 ORFE Overrun Framing Error
ORFE is set by hardware when an overrun or a framing error is generated (during data-receive only). An
overrun error occurs when new receive data is ready to
340
be transferred to the RDR during RDRF still being set.
A framing error occurs when a stop bit is "0". But in
clocked synchronous mode, this bit is not affected. This
bit is cleared when reading the TRCSR, then the RDR,
or during reset.
Bit 7 RDRF Receive Data Register Full
RDRF is set by hardware when the RDSR is transferred to the RDR. Cleared when reading the TRCSR,
then the RDR, or during reset.
(Note) When a few bits are set between bit 5 to bit 7 in the
TRCSR, a read of the TRCSR is sufficient for: clearing
those bits. It is not necessary to read the TRCSR everytime to clear each bit.
• Transmit Rate/Mode Control Register (RMCR)
The RMCR controls the following serial I/O:
• Baud Rate
• Clock Source
• Data Format
• Port 2, Bit 2 Function
In addition, if 9-bit data format is set in the asynchronous
mode, the 9th bit is put in this register. All bits are readable and
writable except bit 7 (read only). This register is set to $00
during reset.
Transfer Rate/Mode Control Register
76543210
1
RDa/ TOa/ SS21 CC21 CCl
Bit 0
Sit 1
Bit 5
SSO}
SSl
SS2
1 CCO / SSl
I
SSO 1$0010
Speed Select
These bits control the baud rate used for the SCI. Table
8 lists the available baud rates. The timer 1 FRC (SS2=O) and
the timer 2 up counter (SS2=1) provide the internal clock to the
SCI. When selecting the timer 2 as a baud rate source, it functions as a baud rate generator. The timer 2 generates the baud
rate listed in Table 9 depending on the value of the TCONR.
(Note) When operating the SCI with internal clock, do not
perform write operation to the timer/counter which is
the clock source of the SCI.
Bit 2
Bit 3
Bit 4
CCO}
CCl
CC2
Clock Control/Format Select*
These bits control the data format and the clock source
(refer to Table 10).
* ceo, CC1 and CC2 are cleared during reset and the MCV
goes to the clocked synchronous mode of the external
clock operation. Then the MCV sets port 2, bit 2 into the
clock input state. When using port 2, bit 2 as an output
port, the DDR of port 2 should be set to "1" and CCI
and CCO to "0" and "1" respectively.
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------HD6301XO,HD63A01XO,HD63B01XO
Table 8 SCI Bit Times and Transfer Rates
(1) Asynchronous Mode
SS2
SS1
SSO
0
0
0
0
0
0
1
XTAL
2.4576MHz
4.0MHz
E
614.4kHz
1.0MHz
4.9152MHz
1.2288MHz
13j.Lsj76800Baud
E-716
26j.Ls/38400Baud
16j.Ls/62500Baud
1
E-7128
208j.Ls/4800Baud
128j.Ls/7812.5Baud
104.2 j.Ls/9600Baud
0
E-71024
1.67ms/600Baud
1.024ms/976.6Baud
833.3j.Ls/1200Baud
3.333ms/300Baud
0
1
1
E-74096
6.67ms/150Baud
4.096ms/244.1 Baud
1
-
-
-
*
*
*
* When SS2 is "1", Timer 2 provides SCI clocks. The baud rate is shown as follows with the
f
32 (N+l)
Baud Rate
(
TCONR as N.
f: input clock frequency to the)
timer 2 counter
N =0 - 255
(2) Clocked Synchronous Mode *
XTAL
4.0MHz
6.0MHz
8.0MHz
E
1.0MHz
1.5MHz
2.0MHz
SS2
SS1
SSO
0
0
0
E-72
0
0
1
E-716
0
1
0
0
1
1
1
-
-
-
2j.Ls/bit
1.33j.Ls/bit
1j.Ls/bit
16j.Ls/bit
10.7j.Ls/bit
8j.Ls/bit
E-7128
128j.Ls/bit
85.3j.Ls/bit
64j.Ls/bit
E-7512
512j.Ls/bit
341 j.Ls/bit
256j.Ls/bit
**
**
**
* Bit rates in the case of internal clock operation. In the case of external clock operation, the external clock is
operatable up to DC - 1/2 system clock.
** The bit rate is shown as follows with the TCONR as N.
Bit Rate
(~s/bit) = 4 (~+ 1)
(
f: input clock frequency to the)
timer 2 counter
N = 0 - 255
Table 9 Baud Rate and Time Constant Register Example
~L
2.4576MHz
3.6864MHz
4.0MHz
4.9152MHz
8.0MHz
110
150
300
600
1200
2400
4800
9600
19200
38400
21"
127
63
31
15
7
3
1
0
-
32"
191
95
47
23
11
5
2
35"
207
103
51
25
12
70"
51"
207
103
51
25
12
-
-
-
-
43"
255
127
63
31
15
7
3
1
0
Baud Rate (Baud
-
-
-
* E/8 clock is input to the timer 2 up counter and E clock otherwise.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
341
HD6301XO,HD63A01XO,HD63B01XO----------------------Table 10 SCI Format and Clock Source Control
CC2
0
0
cel
0
1
1
a
a
a
1
1
1
1
CCO
0
1
0
1
Format
8-bit data
8-bit data
8-bit data
a
a
a
1
1
a
B-bit data
B-bit data
9-bit data
9-bit data
1
9-bit data
1
Mode
Clocked Synchronous
Asynchronous
Clock Source
External
Internal
Port 2, Bit 2
Input
Not Used* *
Asynchronous
Asynchronous
Internal
External
Output*
Clocked Synchronous
Asynchronous
Internal
Internal
Asynchronous
Asynchronous
Internal
External
Output
Not Used**
Output*
Input
Input
Port 2, Bit 3
I
Port 2, Bit 4
When the TRCSR, RE bit is "1",
bit 3 is used as a serial input.
When the TRCSR, TE bit is ''1'',
bit 4 is used as a serial output.
* Clock output regardless of the TRCSR, bit RE and TE.
** Not used for the SCI.
Bit 6
Bit 7
T08 Transmit Data Bit 8
When selecting 9-bit data format in the asynchronou's mode, this bit is transmitted as the 9th data. In
transmitting 9-bit data, write the 9th data into this bit
then write data to the receive data register.
ROB Receive Data Bit B
When selecting 9-bit data format in the asynchronous
mode, this bit stores the 9th bit data. In receiving 9-bit
data, read this bit then the receive data register.
• TIMER, SCI STATUS FLAG
Table 11 shows the set and reset conditions of each status
flag in the timer !, timer 2 and SCI.
As for Timer! and Timer 2 status flag, if the set and reset
condition occur simultaneously, the set condition is prior to the
reset condition. But in case of SCI control status flag, the reset
condition has priority. Especially as for OCFI and OCF2 of
Timer I, the set signal is generated periodically whenever FRC
matches OCR after the set, and which can cause the unclear of
the flag. To clear surely, the method is necessary to avoid the
occurence of the set Signal between TCSR read and OCR write.
For example, match the OCR value to FRC first, and next read
TCSR, and then write OCR at once.
Table 11 Timer 1, Timer 2 and SCI Status Flag
Timer
1
Timer
2
Set Condition
ICR by edge input to P20 •
ICF
FRC
OCFl
OCR1=FRC
2.
1.
OCF2
OCR2=FRC
2.
1.
TOF
FRC=$FFFF+1 cycle
CMF
T2CNT=TCON R
RORF
Receive Shift Register
ORFE
1.
2.
SCI
TORE
1.
2.
3.
-+
-+
1.
2.
1.
2.
1.
2.
1.
2.
1.
2.
RDR
Framing Error (Asynchronous Mode)
Stop Bit = a
Overrun Error (Asynchronous Mode)
Receive Shift Register -+ ROR when
RORF=l
Asynchronous Mode
TOR -+ Transmit Shift Register
Clocked Synchronous Mode
Transmit Shift Register is "empty"
~=O
Reset Condition
Read the TCSR 1 or TCSR2 then ICRH,
when ICF=l
~=O
Read the TCSR 1 or TCSR2 then write to the
OCRl H or OCRl L, when OCFl =1
RES=O
Read the TCSR2 then write to the OCR2H or
OCR2L, when OCF2=1
RES=O
ReadtheTCSRl then FRCH,whenTOF=l
RES=O
Write "0" to CM F, when CM F = 1
~=O
Read the TRCSR then RDR, when RDRF= 1
FfES=o
Read the TRCSR then RDR, when ORFE=l
RES=O
Read the TRCSR then write to the TOR,
when TORE= 1
(Note) TORE should be reset
after the TE set.
(Note) 1. ~; transfer
2. For example; "ICRH" means High byte of ICR.
342
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
•
for a system with no need of the HD630IXO's consecutive
operation.
LOW POWER DISSIPATION MODE
The HD630lXO provides two low power dissipation modes;
sleep and standby.
• Standby Mode
The HD6301XO stops all the clocks and goes to the reset
state with STBY "low. In this mode, the power diSsipation is
reduced conspicuously. All pins except for the power supply,
the STBY and XT AL are detached from the MCU internally
and go to the high impedance state.
In this mode the power is supplied to the HD6301XO, so
the contents of RAM is retained_ The MCU returns from this
mode during reset. The follOWings are typical usage of this
mode.
Save the CPU information and SP contents on RAM by NMI.
Then disable the RAME bit of the RAM control register and set
the STBY PWR bit to go to the standby mode. If the STBY
PWR bit is still set at reset start, that indicates the power is
supplied to the MCU and RAM contents are retained properly.
So system can restore itself by returning their pre-standby informations to the SP and the CPU. Fig. 24 depicts the timing at
each pin with this example.
• SleepMode
The MCU goes to the sleep mode by SLP instruction execution. In the sleep mode, the CPU stops its operation, while the
registers' contents are retained. In this mode, the peripherals
except the CPU such as timers, SCI etc. continue their functions. The power dissipation of sleep-condition is one fifth that
of operating condition.
__
The MCU returns from· this mode by an interrupt, RES or
STBY; it goes to the reset state by RES and the standby mode
by STBY. When the CPU acknowledges an interrupt request, it
cancels the sleep mode, returns to the operation mode and
branches to the interrupt routine. When the CPU masks this
interrupt, it cancels the sleep mode and executes the next
instruction. However, for example if the timer I or 2 prohibits
a timer interrupt, the CPU doesn't cancel the sleep mode because of no interrupt request.
This sleep mode is effective to reduce the power dissipation
Vee
~~
®NMII
®
NMI
HD6301XO
@ RES
IIIIII
STBY
I
H
I
®
I
I
I
I
I
®
STBY
J~
IIIIII
I
I
I
I
I
I
1---1
~
o Oscillator
Start Time
o Save Registers
o RAM/Port 5 Control
Register Set
~
Aestart
Figure 24 Standby Mode Timing
•
TRAP FUNCTION
The CPU generates an interrupt with the highest priority
(TRAP) when fetching an undefmed instruction or an instruction from non-memory space. The TRAP prevents the systemburst caused by noise or a program error.
•
memory area. Table 12 provides addresses where an address
error occurs to each mode.
This function is available only for an instruction fetch and
is not applicable to the access of normal data read/write.
Table 12 Addresses Applicable to Address Errors
Op Code Error
When fetching an undefmed op code, the CPU saves CPU
registers as well as a normal interrupt and branches to the TRAP
(SFFEE, SFFEF). This has the priority next to reset.
• Addre. Error
When an instruction fetch is made excluding internal ROM,
RAM and external memory area, the MCU generates an interrupt as well as an op code error. But on the system with no
memory in its external memory area, this function is not
applicable if an instruction fetch is made from the external non-
Mode
Address
1
2
$0000
$0000
3
$0000
1
1
1
$OOlF
$oolF
$003F
$0100
1
$EFFF
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
343
HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------(Note) The TRAP interrupt provides a retry function differently from other interrupts. This is a program flow return
to the address where the TRAP occurs when a sequence
returns to a main routine from the TRAP interrupt
routine by RTI. The retry can prevent the system burst
caused by noise etc.
However, if another TRAP occurs, the program repeats
the TRAP interrupt forever, so the consideration is
necessary in programming.
•
INSTRUCTION SET
The HD630lXO provides object code upward compatible
with the HD6801 to utilize all instruction set of the
HMCS6800. It also reduces the execution times of key instructions for throughput improvement.
Bit manipulation instruction, change instruction of the
index register and accumulator and sleep instruction are also
added.
The followings are explained here.
CPU Programming Model (refer to Fig. 25)
Addressing Mode
Accumulator and Memory Manipulation Instruction
(refer to Table 13)
New Instruction
• Index Register and Stack Manipulation Instruction
(refer to Table 14)
• Jump and Branch Instruction (refer to Table 15)
• Condition Code Register Manipulation
(refer to Table 16)
• Op Code Map (refer to Table 17)
B is selected. This is a one-byte instruction.
Immediate Addressing
This addressing locates a data in the second byte of an
instruction. However, LDS and LDX locate a data in the second
and third byte exceptionally. This addressing is a 2 or 3-byte
instruction.
Direct Addressing
In this addressing mode, the second byte of an instruction shows the address where a data is stored. 256 bytes ($0
through $255) can be addressed directly. Execution times
can be reduced by storing data in this area so it is reconunended
to make it RAM for users' data area in configurating a system.
This is a 2-byte instruction, while 3·byte with regard to AIM,
aIM, ElM and TIM.
Extended Addressing
In this mode, the second byte shows the upper 8 bit of the
data stored address and the third byte the lower 8 bit. This
indicates the absolute address of 3-byte instruction in the
memory.
Indexed Addressing
The second byte of an instruction .and the lower 8 bit of the
index register are added in this mode. As for AIM, OIM, ElM
and TIM, the third byte of an instruction and the lower 8 bits
of the index register are added.
This carry is added to the upper 8 bit of the index register
and the result is used for addressing the memory. The modified
address is retained in the temporary address register, so the contents of the index register doesn't change. This is a 2-byte
instruction except AIM, aIM, ElM and TIM (3-byte instruction).
Implied Addressing
•
Programming Model
Fig. 25 depicts the HD630lXO programming model. The
double accumulator D consists of accumulator A and B, so
when using the accumulator D, the contents of A and Bare
destroyed.
E
15-- -
A
-- -
0:U 7
-
-
0
-
j
8
-
-
-
-
-
-
-
1,5
1,5
SP
1'5
PC
D.
01
Inck.
A",m""o .. A .nd
8
16·B'IOOubl~Accumulal010
R~g'Sler
(XI
01
01
7
8·8"
~
'
An instruction itself specifies the address. That is, the
instruction addresses a stack pointer, index register etc. This is a
one-byte instruction.
Relative Addressing
The second byte of an instruction and the lower 8 bits of
the program counter are added. The carry or borrow is added to
the upper 8 bit. So addressing from -126 to + 129 byte of the
current instruction is enabled. This is a 2-byte instruction.
(Note) CLI, SEI Instructions and Interrupt Operation
When accepting the IRQ at a preset timing with the CLI and
SEI instructions, more than 2 cycles are necessary between the
eLi and SEI instructions. For example, the following program
(a) (b) don't accept the IRQ but (c) accepts it.
Progr.rnCountl"' (PCI
0
~
H
IN
Z
V
C
Cond,tlonCodeRtg.Sll",(CCRJ
c..-,yIBoHo .... t'omMSB
Ovedlow
eLi
Zero
N"9il1,ve
Inte"'JpI
eLi
Hal! Carry (From 8,t 3)
SEI
CLI
Nap
SEI
Nap
Nap
SEI
(a)
(b)
(c)
Figure 25 CPU Programming Model
•
CPU Addressing Mode
The HD630 I XO provides 7 addressing modes. The addressing
mode is decided by an instruction type and code. Table 13
through 17 show addressing modes of each instruction with
the execution times counted by the machine cycle.
When the clock frequency is 4 MHz, the machine cycle time
becomes microseconds directly.
Accumulator (ACGX) Addressing
The same thing can be said to the TAP instruction
instead of the eLi and SEI instructions.
Only an accumulator is addressed and the accumulator A or
344
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------'----------------HD6301XO,HD63A01XO,HD63B01XO
Table 13 Accumulator, Memory Manipulation Instructions
Condition Code
Addressing Modes
Operations
Mnemonic
IMMED
DIRECT
INDEX
Register
EXTEND
Boolean/
IMPLIED
Arithmetic Operation
OP
-
#
OP
-
#
OP
-
#
OP
-
#
ADDA
BB
2
2
9B
3
2
AB
4
2
BB
4
3
A +
ADDB
CB
2
2
DB
3
2
EB
4
2
FB
4
3
B+M~B
Add Double
ADDD
C3
3
3
03
4
2
E3
5
2
F3
5
3
A
Add Accumulators
ABA
Add With Carry
ADCA
B9
2
2 99
3
2
A9
4
2
B9
4
3
A+M+C~A
ADCB
C9
2
2
09
3
2
E9
4
2
F9
4
3
B+M+C~B
ANDA
B4
2
2
94
3
2
A4
4
2
B4
4
3
A·M-A
AN DB
C4
2
2
04
3
2
E4
4
2
F4
4
3'
B·M~
BITA
B5
2
2
95
3
2
A5
4
2
B5
4
3
A·M
BIT B
C5
2
2
05
3
2
E5
4
2
F5
4
3
B·M
6F
5
2
7F
5
3
OO~
Add
AND
Bit Test
Clear
lB
CLR
CLRA
CLRB
Compare
5F
1
1
00 - B
2
Bl
4
3
A-M
CMPB
C1
2
2
01
3
2
El
4
2
Fl
4
3
B-M
63
6
2
73
6
3
43
COMB
53
60
6
2
70
6
1
1
1
1
A-B
1
A -A
1
B
~B
6
3
2
A8
4
2
B8
4
3
A@M-A
3
2
E8
4
2
F8
4
3
B @ M~ B
6C
6
2
7C
6
3
M + 1
~M
~
A
4C
1
1
A + 1
5C
1
1
B + 1~ B
2
A6
4
2
B6
4
3
M~A
4
2
F6
4
3
M
M + 1 ~ B. M- A
06
3
2
Load Double
Accumulator
LDD
CC
3
3
DC 4
2
EC
5
2
FC
5
3
Multiply Unsigned
MUL
OR. Inclusive
ORAA
8A
2
2
9A
3
2
AA 4
2
BA
4
3
ORAB
CA
2
2
DA 3
2
EA
4
2
FA
4
3
3D
PSHA
7
1
~B
AxB~A:8
B +M- B
4
1
A - Msp. SP - 1 ~ SP
~
Msp. SP - 1
~
SP
PSHB
37
4
1
B
PULA
32
3
1
SP + 1 ~ SP, Msp
PULB
33
3 1 SP + 1 ~ SP. Msp ~ B
49
1
1
59
1
1
ROL
69
6
2
79
6
3
ROLA
ROLB
ROR
66
6
2
76
6
3
RORA
46
1
1
RORB
56
1
1
(Note) Condition Code Register will be explained in Note of Table 16.
t
t
t
t
t
t
t
t
t
R
t
t
R
t
t
t
t
R
R
S R
R
S
R
S R
t
!
t
R
R
R R
R
t
t
t
t
t
t
t
t
t
t
t
t
t
!
t
t
R
S
R
S
R
S
~)~I
B
C b7
~
A
11111
~)blill
C b7
B
t @
R
®.
!
t
R
!
!
R
!
I R
I
!
!
R
I
R
• @
A+M~A
36
:
t
®•
3
08
2
t
t
t
!
98
2
2
t
t
t
t
t
2
2
C6
t
t
R
2
C8
LDA8
t
t
t
t
t
88
EORB
E6
t
t
t
t
A
EORA
3
t
t
B-l~B
96
t
@•
@.
A -1
1
2
t
··
· ··
··
·· ·· ··
·· ·· ··
·· ··
··· ···
·· ··
·· ··
·· ··
·· ··
··· ···
·· ·· ··
·· ·· ®.
·· ·· ·
·· ·· ··
·· ·· · · ·
·· ·· · · · ··
··· ··· ··· ··· ··· ···
·· ··
··
fJ · ·
·· ··
t
t
1
1
2
t
t
t
t
1
86
t
~
4A
5A
LDAA
t
t @ •
A
DECB
INCB
t
t
A~
DECA
INC
C
t
t
OO-B~B
7A
0
t
00 -
1
2
1
V
~M
1
1
6
3
M -1
1
50
6A
2
N Z
t
40
2 1
I
Converts binary add of BCD
characters into BCD format
NEGA
NEGB
19
H
t I@~
t @@
t @@
OO-M~M
3
4
t
M-M
COMA
INCA
Rotate Right
00- A
4
DEC
Rotate Left
1
Al
Decrement
Pull Data
1
2
NEG
B
4F
11
A
M
3
DAA
Push Data
B~
91
Decimal Adjust. A
Load
Accumulator
A +
2
COM
Increment
1
A
B + M: M+l-A:B
2
CBA
Exclusive OR
1
M~
81
Complement, "s
(Negate)
- 1#
CMPA
Compare
Accumulators
Complement.2·s
OP
5
IbO~
III
bO
I
t
I
I
I
I
I @ I
II(§) I
II(§) I
I @ t
I @I
I @I
(continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
345
HD6301XO,HD63A01XO,HD63B01XO-------------------------------------------Table 13 Accumulator, Memory Manipulation Instructions
Condition Code
Register
Addressing Modes
Operations
Mnemonic
IMMED
OP
Shift Left
Arithmetic
-
DIRECT
#
OP
-
EXTEND
INDEX
#
ASL
OP
68
-
#
OP
-
#
6
2
78
6
3
OP
-
#
M)
_
o-l I I III I I 1+ 0
48
58
1
ASLB
Double Shift
Left. Arithmetic
ASLD
05
1 1 ~
Shift Right
Arithmetic
ASR
AS LA
6
2
71
6
3
47
1
1
57
1 1
44
1
1
LSRB
54
1
1
LSRD
04
1 1
ASR8
LSR
64
6
2
74
6
3
LSRA
Double Shift
Right Logical
1
1 1
A
8
C
b7
b7
Mj
ACC A/ ACC 8
A,7
AO
87
BO
07
3
2
E7
4
2
F7
4
3
2
ED 5
2
FD 5
3
A_M
B -'+ M+ 1
Subtract
SUBA
80
2
2
90
3
2
AO
4
2
BO
4
3
A-M -A
SUBB
CO
2
2
DO
3
2
EO
4
2
FO
4
3
Double Subtract
SUBO
83
3
3
93
4
2
A3
5
2
B3
5
3
B - M - B
A: B-M :M+l-A:B
Subtract
Accumulators
SBA
SBCA
82
2
2
92
3
2
A2
4
2
B2
4
3
SBCB
C2
2
2
02
3
2
E2
4
2
F2
4
3
Subtract
With CarrV
Transfer
Accumulators
TAB
Test Zero or
Minus
TST
A7
4
2
10
B-M-C-B
17
60
4
2
70
4
A - B- A
A-M-C-A
16
TBA
1 1
1
1
1
A-B
1
B-A
M -00
3
A -00
TSTA
40
1
1
TSTB
50
1
1 B - 00
And Immediate
AIM
71
6
3
61
7
3
M·IMM-M
OR Immediate
DIM
72
6
3 62
7
3
M+IMM-M
EOR Immediate
ElM
75
6
3 65
7
3
M!:iIMM-M
Test Immediate
TIM
7B
4
3 68
3
M·IMM
5
(Note) Condition Code Register will be explained in Note of Table 16.
$
3 2
1 0
V
C
·· ·· ••
·· ··
·· ·· •• •
·· ·· • •*
·· ·· * @*
·· ·· • •* ·
·· ·· ··
·· ·· •
·· ·· •
··· ··· ·•
·· ·· ·
·· ·· • •
*
*
* ®*
* ' SP - 1 - SP
SP + 1 - SP, M., - XL
ACCD··IX
5
(j)
(j)
(j)
(j)
l
l
l
l
A
A
A
A
••••••
(Note) Condition Code Register will be explained in Note of Table 16.
Hitachi America Ltd. •
2210
~HITACHI
O'Toole Ave. • San Jose, CA 95131
347
• (408) 435-8300
HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------Table 15 Jump, Branch Instruction
Condition Code
Register
Addressing Modes
Operations
Mnemonic
RELATIVE
OP
Branch AlwlYs
BRA
20
-
#
3
2
OIRECT
OP
-
#
INDEX
OP
-
#
EXTEND
IMPLIED
OP
OP
-
#
-
Branch Test
#
None
Branch Never
BRN
21
3
2
None
Brlnch If Carry CI.r
BCC
24
3
2
c=o
Branch If Carry Set
BCS
25
3
2
Br.nch If - Zero
BEQ
27
3
2
C=1
Z c 1
Branch If .. Zero
BGE
2C
3
2
N <±> V-O
> Zero
BGT
2E
3
2
Z + (N <±> V)· 0
Branch If Higher
BHI
22
3
2
C+Z=O
Branch If .. Zero
BlE
2F
3
2
Z + (N <±> V) - 1
Branch If lower Or
Seme
BlS
23
3
2
C+Z = 1
BlT
20
3
2
N <±> V = 1
BMI
2B
3
2
N -I
Br.nch If Not Equ.'
Zero
BNE
26
3
2
ZeO
Branch If OverflOW
Crear
BVC
28
3
2
V-O
Branch If Overflow Set
8VS
29
3
2
V -I
Branch If Plus
BPl
2A
3
2
N-O
80
5 2
Branch If
Branch If
< Zero
Branch If Minus
Branch To Subroutine
BSR
Jump
JMP
Jump To Subroutine
JSR
No Operation
NOP
01
Return From Interrupti
RT!
3B 10 1
Return From
Subroutine
RTS
39
3
2
7E
3
3
AD 5
2
BD 6
3
6E
90
5
2
1
5
1
1
5of_re Interrupt
SWI
3F 12 1
W.it for Interrupt·
Sleep
WAI
SLP
3E
9
1A 4
Advances Prog. Cntr.
Only
1
1
5
4
3
H
I
N Z
2
1 0
V
C
··· ··· ··· ··· ··· ···
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
··· ··· ··· ··· ······
··· ··· ··· ··· ··· ···
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
··· ···
·· · ·· ·· ·· ··
·• • • ·• ·• •·
--@
--
S
®.
(Note) • WAI puts R/W high; Address Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of Table 16.
348
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave . • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
Table 16 Condition Code Register Manipulation Instructions
jAddressingModes
Operations
Condition Code Register
IMPLIED
Mnemonic
OP
-
Boolean Operation
#
Clear Carry
ClC
OC
1
1
O .... C
Clear Interrupt Mask
CLI
OE
1
1
0 .... 1
1
0"" V
l .... C
I .... V
3
2
1
I
N
Z
V
0
C
·· · ·· ·· ·· ·
·· ·· ·· ·· · ·
·· · ·· ·· · ··
······
R
Clear Overflow
ClVo
OA
1
1
SEC
OD
1
SEI
OF
1
,
Set Overflow
SEV
08
1
1
Accumulator A .... CCR
TAP
06
1
1
A .... CCR
CCR .... Accumulator A
TPA
07
1
1
CCR .... A
R
S
1 .... 1
S
®
---
S
---
CONDITION CODE SYMBOLS
H
Half-carry from bit 3 to bit 4
I
Interrupt mask
N
Negative (sign bit)
Z
Zero (byte)
Overflow, 2's complement
V
C
Carry/Borrow from/to bit 7
R
Reset Always
S
Set Always
t Set if true after test or clear
Not Affected
OP
Operation Code (Hexadecimal)
Number of MCU Cycles
Msp Contents of memory location pointed to by Stack Pointer
#
Number of Program Bytes
+
Arithmetic Plus
Arithmetic Minus
•
Boolean AND
+
Boolean Inclusive OR
e Boolean Exclusive OR
M Complement of M
Transfer into
OBit = Zero
00 Byte = Zero
(Note)
4
R
Set Carry
Set Interrupt Mask
LEGEND
5
H
Condition Code Register Notes: (Bit set if test is true and cleared otherwise)
CD
(Bit V)
Test: Result = 10000000?
@
@
@
(Bit C)
Test: Result ~ OOOOOOOO?
(Bit C)
(Bit V)
(Bit V)
Test: BCD Character of high-order byte greater than 10?
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
(Bit V)
(Bit N)
Test: Set equal to NEll C = 1 after the execution of instructions
Test: Result less than zero? (Bit 15=1)
®
®
o
®
®
@
@
(Not cleared if previously set)
(All Bit)
Load Condition Code Register from Stack.
(Bit I)
(All Bit)
(Bit C)
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the wait state.
Set according to the contents of Accumulator A.
Result of Multiplication Bit 7=1? (ACCB)
Table 17 OP-Code Map
OP
ACC
ACC
CODE
A
B
0100
0101
~
LO
0000
0001
0010
0
1
2
0011
0000
0
~ SBA
BRA
3
TSX
0001
1
NOP
BRN
INS
0010
2
BHI
PULA
0011
3
4
~ ~
~ ~
lSRD ~
BLS
PULB
BCC
DES
0100
CBA
0101
5
ASLD
~
BCS
TXS
0110
6
TAP
TAB
BNE
PSHA
0111
7
TPA
TBA
BEQ
PSHB
1000
8
lNX
XGDX BVC
PUlX
1001
9
DEX
DAA
BVS
RTS
1010
A
ClV
SLP
BPL
ABX
1011
B
SEV
ABA
BMI
RTI
1100
C
CLC
~
~
~
~
BGE
PSHX
1101
0
SEC
1110
E
CLl
1111
F
SEI
0
1
UNDEFINED OP CODE
BLT
MUL
BGT
WAI
BlE
SWI
2
3
-------4
IND
lfof
0110
0111
1000
6
7
8
5
----
DIR'
1001
9
I
I
1010
A
EXT
IMM
1011
1100
B
C
I
I
I
~CCB
DIR
1101
o
or X
liND
I
I
1110
E
I
I
I
EXT
1111
F
SUB
0
AIM
CMP
1
OIM
SBC
2
COM
ADDD
SUBD
.-
LSR
3
AND
ElM
ROR
~l
ASR
4
BIT
5
lDA
6
~I
STA
STA
7
8
ASL
EOR
ROL
ADC
9
DEC
ORA
A
ADD
TIM
INC
B
LDD
CPX
TST
BSR
I
7
8
I
STD
~l
STS
9
I
C
0
LOX
LOS
~l
6
~j
JSR
JMP
CLR
5
I
I
I
I
I
NEG
~~
4
ACCA or SP
liND
!IMMIDIR
A
I
B
C
I
E
STX
o
I
E
F
J
- ._-
F
l:2::l
• Only each instructions of AIM, OIM, ElM, TIM
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
349
HD6301XO,HD63A01XO,HD63B01XO----------~---------------------------------
• CPU OPERATION
• CPU Instruction Flow
When operating, the CPU fetches an instruction from a
memory and executes the required function. This sequence
starts with RES cancel and repeats itself limitlessly if not
affected by a special instruction or a control signal. SWI, RTI,
WAI and SLP instructions change this operation, while NMI,
IRQ1, IRQ2, IRQ3, HALT and STBY control it. Fig. 26 gives
the CPU mode transition and Fig. 27 the CPU system flow
chart. Table 18 shows CPU operating states and port states.
•
Operation at Each Instruction Cycle
Table 19 shows the operation at each instruction cycle.
By the pipeline control of the HD6301XO, MULT, PUL, DAA
and XGDX instructions etc. prefetch the next instruction.
So attention is necessary to the counting of the instruction
cycles because it is different from the usual one ..... op code
fetch to the next instruction of code.
Table 18 CPU Operation State and Port State
Figure 26 CPU Operation Mode Transition
Mode
Reset
Mode 1.2
H
Mode 3
T
Port
Port 1
(Ao -A , )
Port 2
Mode 1,2
Mode 3
T
Port 3
(Do - 0,)
Mode 1,2
Port 4
(A. -A IS )
Mode 1.2
H
Mode 3
T
Port 5
Port 6
Port 7
Mode 3
Mode 1,2
Mode 3
Mode 1.2
Mode 3
Mode 1,2
Mode 3
H; High,
STBY****
T
T
T
T
T
T
T
T
T
*
T
T
L; Low, T; High Impedance
* RD,WR,R/W.LlR=H,BA=L
RD, WR, R/W=T, LlR. BA=H
HALT is unacceptable in mode 3.
E pin goes to high impedance state.
350
HALT***
T
-------Keep
-----T
T
-T
Keep
Sleep
H
Keep
Keep
T
Keep
H
Keep
T
.=------
Keep
----
*
Keep
**
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
I
s:
(")
~
»
3
~
o·
$l)
r-
ei
•
I\)
~
(Note)
0
0
oi
1. The program sequence will come to the RES start from
any place of the flow during RES. When STBY=O, the
sequence will go into the standby mode regardless of the CPU
condition.
2. Refer to "FUNCTIONAL PIN DESCRIPTION" for more
details of interrupts.
~~
~:I
·
(I) .~
~
enC')
~ :I
c.....
0
en
~(I)
()
»
(0
I
01
o
~
Q)
w
o
•
><
~
9
0
&
I
TN
~
o
W
Q)
w
01
cD
~
o
W
0
0
><
9
I
o
Q)
W
III
w
VI
Figure 27
HD6301XOSystem Flow Chart
o
o><
HD6301XO,HD63A01XO,HD63B01XO-------------------------------------------Table 19 Cycle-by-Cycle Operation
Address Mode &
Instructions
Address Bus
Data Bus
IMMEDIATE
ADC
AND
CMP
LDA
SBC
ADDD
LDD
LDX
ADD
BIT
EOR
ORA
SUB
CPX
LDS
SUBD
1
1
2
Op Code Address + 1
Op Code Address + 2
1
1
0
0
1
1
1
3
Op Code Address+ 1
Op Code Address + 2
Op Code Address + 3
1
1
1
0
0
0
1
1
1
0
1
2
3
Op Code Address + 1
Address of Operand
Op Code Address+2
1
1
1
0
0
0
1
1
1
0
1
2
3
1
2
3
Op Code Address+ 1
Destination Address
Op Code Address'" 2
Op Code Address+ 1
Address of Operand
Address of Operand + 1
Op Code Address+2
Op Code Address+ 1
Destination Address
Destination Address + 1
Op Code Address + 2
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
Op Code Address+3
Op Code Address + 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
Op Code Address+3
0
Operand Data
Next Op Code
2
3
2
1
1
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
DIRECT
ADC
AND
CMP
LDA
SBC
STA
ADD
BIT
EOR
ORA
SUB
3
3
ADDD
LDD
LDX
CPX
LDS
SUBD
STD
STX
STS
4
4
4
1
2
3
4
JSR
5
1
2
3
4
5
1
TIM
4
2
3
4
AIM
OIM
ElM
6
1
2
3
4
5
6
1
0
/1
0
1
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
0
1
1
0
1
1
1
1
1
1
0
1
0
Address of Operand (LSB)
Operand Data
Next Op Code
Destination Address
Accumulator Data
Next Op Code
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
(Continued)
352
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301XO,HD63A01XO,HD63B01XO
Address Mode &
Instructions
Address Bus
Data IJus
INDEXED
JMP
3
ADC
AND
CMP
LOA
SBC
TST
STA
ADD
BIT
EOR
ORA
SUB
4
4
1
2
3
1
2
3
4
1
2
3
4
ADDD
CPX
LOS
SUBD
LDD
LOX
5
1
2
3
4
5
STD
STX
STS
5
1
2
3
4
5
1
2
JSR
5
;3
4
5
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
TIM
5
1
2
3
4
5
6
1
2
3
4
5
CLR
5
1
2
3
4
5
AIM
OIM
1
2
3
ElM
7
4
5
6
7
Op Code Address+ 1
FFFF
Jump Address
Op Code Address+ 1
H:FF
IX + Offset
Op Code Address + 2
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address + 2
Op Code Address+ 1
FFFF
IX + Offset
IX+Offset+ 1
Op Code Address+2
Op Code Address+ 1
FFFF
IX + Offset
IX+Offset+ 1
Op Code Address+2
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
IX + Offset
Op Code Address+ 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+ 2
Op Code Address+ 1
Op Code Address + 2
FFFF
IX+Offset
Op Code Address+3
Op Code Address+ 1
FFFF
IX + Offset
IX+Offset
Op Code Address + 2
Op Code Address+ 1
Op Code Address+2
FFFF
IX+Offset
FFFF
IX+Offset
Op Code Address+3
1
1
1
1
1
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
1
0
0
1
0
0
1
1
0
0
1
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
0
1
0
1
0
Offset
Restart Address (LSB)
First Op Code of Jump Routine
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data
00
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
353
HD6301XO,HD63A01XO,HD63B01XO----------------------Address Mode &
Instructions
Address Bus
EXTEND
JMP
3
ADC
AND
CMP
LOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
TST
4
1
2
3
1
2
3
4
4
1
2
3
4
ADDD
CPX
LOS
SUBD
STD
STX
LDD
LOX
5
1
2
3
4
5
STS
5
1
2
3
4
5
JSR
6
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
CLR
5
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
Data Bus
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
1
1
1
FFFF
1
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address+ 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
Op Code Address+3
Op Code Address + 1
Op Code Address+2
Address of Operand
Address of Operand
Op Code Address+3
0
0
1
1
Op Code Address+ 1
Op Code Address + 2
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Op Code Address + 3
Op Code Address+ 1
Op Code Address+2
Destination Address
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Address of Operand
Address of Operand + 1
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Destination Address
Destination Address + 1
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
1
1
0
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
0
Jump Address (MSB)
Jump Address (LSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Accumulator Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (MSB)
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
1
1
1
1
0
0
0
0
1
1
1
0
1
0
0
0
0
1
1
1
1
0
0
1
0
1
00
1
0
1
0
Next Op Code
0
1
1
1
1
1
1
1
1
1
1
1
(Continued)
354
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
Address Mode &
Instructions
IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
LSR
ROL
Nap
SEC
SEV
TAP
TPA
TSX
XGDX
PULA
PULB
PSHA
PSHB
Address Bus
Data Bus
1
Op Code Address+ 1
1
0
1
0
1
2
1
2
Op Code Address+ 1
FFFF
Op Code Address+ 1
FFFF
Stack Pointer + 1
Op Code Address+ 1
FFFF
Stack Pointer
Op Code Address+ 1
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Op Code Address+ 1
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Return Address
Op Code Address + 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
Next Op Code
1
2
3
3
4
PULX
4
1
2
3
4
1
2
3
4
1
2
PSHX
5
3
4
5
1
2
RTS
5
3
4
5
1
2
MUL
7
3
4
5
6
7
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
0
0
1
0
0
0
1
1
1
0
0
1
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
1
1
1
Next Op Code
Restart Address (LSB)
Next Op Code
Restart Address (LSB)
Data from Stack
Next Op Code
Restart Address (LSB)
Accumulator Data
Next Op Code
Next Op Code
Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSB)
Next Op Code
Restart Address (LSB)
Index Register (LSB)
Index Register (MSB)
Next Op Code
Next Op Code
Restart Address (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
355
HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------Address Mode &
Instructions
Address Bus
IMPLIED
WAI
9
1
2
3
4
5
6
7
8
9
RTI
10
1
2
3
4
5
6
7
8
9
SWI
12
10
1
2
3
4
5
6
7
8
9
10
11
12
1
2
SLP
4
BCS
BGE
BHI
BLS
BMT
BPL
BRN
BVS
3
r
356
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
I I I I
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (LSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
I!lext Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (LSB)
First Op Code of SWI Routine
Next Op Code
Restart Address (LSB)
I
1
0
1
1
1
0
Restart Address (LSB)
Next Op Code
Op Code Address+ 1
FFFF
Branch Address'"'' Test="1"
Op Code Address +1···Test="0··
1
1
0
1
1
1
1
1
1
0
1
0
Branch Offset
Restart Address (LSB)
First Op Code of Branch Routine
Next Op Code
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-1
Branch Address
1
1
0
0
1
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
FFFF
Op Code Address+ 1
1
2
1
2
3
4
5
1
1
0
0
0
0
1
1
3
4
3
5
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer-3
Stack Pointer-4
Stack Pointer-5
Stack Pointer-6
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer+3
Stack Pointer+4
Stack Pointer + 5
Stack Pointer+6
Stack Pointer + 7
Return Address
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-1
Stack Pointer - 2
Stack Pointer-3
Stack Pointer-4
Stack Pointer - 5
Stack Pointer-6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address+ 1
FFFF
Sleep
I
RELATIVE
BCC
BEQ
BGT
BLE
BLT
BNE
BRA
BVC
BSR
Data Bus
I
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Op Code of Subroutine
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H D6301 XO, H 063A01 XO, H 063801 XO
•
PRECAUTION TO THE BOARD DESIGN OF OSCILLATION CI RCUIT
As shown in Fig. 28, there is a case that the cross talk disturbs the normal oscillation if signal lines are put near the
oscillation circuit. When designing a board, pay attention to
this. Crystal and CL must be put as near the HD630IXO as
possible.
XTAL
EXTAL
HD6301XO
HD6301XO
!OP-64S)
Do not use this kind of print board design.
Figure 28
(Top view)
Precaution to the boad design
of oscillation circuit
Figure 29
Example of Oscillation Circuits in Board Design
•
RECEIVE MARGIN OF THE SCI
Receive margin of the SCI contained in the HD630 1 XO is
shown in Table 20.
Note: SCI = Serial Communication Interface
Table 20
Bit distortion tolerance
(t-to) Ito
Character distortion tolerance
(T-Tol ITo
±4.37%
±43.7%
START
3
6
4
Ideal Waveform
Bit length \--to
I
8
STOP
-1
I-o.o-----------Character length To - - - - - - - - - - - 1
Real Waveform
1 4 - - -_ _
T_~t~
_ _ _______.j.1
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
357
HD6301 YO,HD63A01 YO,--HD63B01YO
CMOS MCU (Microcomputer Unit)
The HD6301YO is a CMOS 8-bit single-chip microcomputer
unit which contains a CPU compatible with the CMOS 8-bit
microcomputer HD6301V, 16k bytes of ROM, 256 bytes of RAM,
53 parallel I/O pins, Serial Communication Interface (SCI) and two
timers.
•
•
•
•
•
•
•
•
•
•
FEATURES
Instruction Set Compatible with the HD6301 V 1
16k Bytes of ROM, 256 Bytes of RAM
53 Parallel I/O Pins
(48 I/O Pins, 5 Output Pins)
Parallel Handshake Interface (Port 6)
Darlington Transistor Drive (Port 2, 6)
16-Bit Programmable Timer
Input Capture Register x 1
Free Running Counter x 1
Output Compare Register x 2
8-Bit Reloadable Timer
External Event Counter
Square Wave Generation
Serial Communication Interface (SCI)
Asynchronous Mode (8 Transmit Formats, Hardware Parity)
Clocked Synchronous Mode
HD6301YOP, HD63A01YOP,
HD63B01YOP
(DP-64S)
•
PIN ARRANGEMENT
Vss , 0
Memory Ready
3 Kinds of Memory Ready
Halt
Error Detection
(Address Error, Op-code Error)
• Interrupt - External 3, Internal 7
• Operation Mode
Mode 1; Expanded Mode
!Internal ROM Inhibited)
Mode 2; Expanded Mode
(Internal ROM Valid)
Mode 3; Single Chip Mode
• Maximum 65K Bytes Address Space
• Low Power Dissipation Mode
Sleep Mode
Standby Mode (Hardware Standby, Software Standby)
• Minimum Instruction Execution Time - O.5/-ts (f = 2M Hz)
• Wide Range of Operation
V cc =3 to 5.5V
(f =0.1 to O.5MHz)
XTAL
EXTAL
3
STBY
7
2
•
•
V cc =5V±10%
HD6301YO
f =0.1 to 1 .0MHz : HD630 1YO }
f=O.1 to 1.5MHz: HD63A01YO
{ f =0.1 to 2.0MHz : HD63BOl YO
(Top View)
358
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301YO,HD63A01YO,HD63B01YO
•
BLOCK DIAGRAM
Vcc_
VSS
VSS
-
)----..r-TI
P2o(Tin
P2,(Tout,J---_fool
P22(SCLK) ---...+fool N
P2J( Rx ) ----1'#fool Ia:
P24(Tx
) ---H-#fool o
0..
P2S(TOUt2) -_++++~
P2s(ToutJ) -'"1'"i++#fool
P27(TCLK)
P70/RD
P71/WR
P72/R!W
P7J/i:m
P74/BA
-,ttttlttL--1_J
PJO/Oo
PJ,fO,
PJ2/02
PJJ/OJ
PJ4/04
PJS/OS
PJS/OS
PJ7/0,
PlO/Ao
P l1 /A,
P,2iA2
P'J/AJ
P'4/A4
P's/As
P's/As
P17/A,
-----.r-TI
Pso(rnn-, )
PS,(iRQ2 )-----~
PS2(MR ) -----~ It)
IPSJ( HAIT) -----~ a:
PS4(fS
) -----~ o
0..
Pss(~
P4o/Aa
P4,fAg
P42/AlO
P4J/Al1
P44/A'2
P4s/A'J
P46/A'4
)-----~
PS6
PS7
Pso
Ps'
PS2
PSJ
PS4
PSS
P66
PS7
P4';A,~
<0
I-
a:
o
0..
16kBytes
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
359
HD6301YO,HD63A01YO,HD63B01YO----------------------•
ABSOLUTE MAXIMUM RATINGS
Symbol
Item
Value
Unit
Supply Voltage
Vee
-0.3-+ 7.0
Input Voltage
V in
-0.3- Vee+ 0 .3
Operating Temperature
Topr
0-+70
°C
Storage Temperature
T stg
-55-+150
°C
V
V
(NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits. To assure the normal
operation, we recommend Vin, Vaut : Vss ;:;; (Vin or Vaut ) ;:;; Vce.
•
•
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee = 5.0V± 1 0%. Vss = OV. Ta = 0- + 70°C. unless otherwise noted.'
Item
Symbol
Test Condition
RES.STBY
Input "High" Voltage
EXTAL
V 1H
Other Inputs
min
typ
Vee- 0 .5
-
Vee XO .7
max
Unit
Vee
+0.3
V
2.0
-
-0.3
-
0.8
V
Input "Low" Voltage
All Inputs
V 1L
Input Leakage Current
NMI. RES, STBY,
MP o• MP,
Il in I
V in
= 0.5-Vee -0.5V
-
-
1.0
/-LA
Three State
Leakage Current
P rt 1,2,3,4
o s 5,6.7
IITSII
V in = 0.5-Vee- 0 .5V
-
-
1.0
/-LA
2.4
-
-
V
Vee- 0 .7
-
-
V
Output "High" Voltage
All Outputs
V OH
= -200/-LA
IOH = -10/-LA
IOH
Output "low" Voltage
All Outputs
VOL
IOL = 1.6mA
-
-
0.4
V
Darlington Drive
Current
Ports 2, 6
-IOH
V out = 1.5V
1.0
-
10.0
mA
Input Capacitance
All Inputs
Cin
V in = OV, f = 1MHz,
Ta
25°C
-
-
12.5
pF
Standby current
Non Operation
-
3.0
15.0
/-LA
=
ISTB
ISLP
Current Dissipation·
Icc
Sleeping (f = 1MHz··)
-
1.5
3.0
rnA
Sleeping (f = 1.5MHz··'
2.3
4.5
mA
Sleeping (f = 2MHz··'
-
3.0
6.0
mA
Operating (f= 1MHz··'
-
7.0
10.0
mA
Operating (f = 1.5MHz··'
-
10.5
15.0
mA
14.0
20.0
mA
2.0
-
-
V
Operating (f = 2MHz··'
RAM Standby Voltage
V RAM
V1H min = Vee - 1.0V, V1L max = O.8V (All output terminals are at no 10adJ
Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max. values about Current
Dissipations at X MHz operation are decided according to the following formula:
typo value (f X MHz) = typo value (f = 1MHz) x X
max. value (f = X MHz) = max. value (f = 1MHz) x X
(both the sleeping and operating)
=
360
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301YO,HD63A01YO,HD63B01YO
• AC CHARACTERISTICS IV cc
BUS TIMING
= 5.0V ± 1 0%, V ss = OV, T = 0 - + 70°C, unless otherwise noted.)
8
Item
Test
Condition
Symbol
HD6301YO
min
typ
HD63A01YO
HD63B01YO
min
typ
max
min
typ
max
10
fJ-S
25
ns
Cycle Time
tcyc
1
10
0.666
0.5
-
25
-
-
10
tEr
-
-
Enable Rise Time
25
Enable Fall Time
tEt
-
-
25
-
-
25
-
-
Enable Pulse Width "High" Level'
PWEH
450
-
-
300
-
-
220
-
Enable Pulse Width "Low" Level'
PWEL
450
-
-
300
220
tAD
-
250
-
190
200
-
160
-
tOSR
80
-
-
-
to ow
-
-
-
Address, R/W Delay Time'
70
80
-
50
-
40
80
-
50
-
-
tHW
40
0
-
300
40
-
-
-
60
tAH
-
-
Data Delay Time
Data Set-up Time
I Write
I Read
Address, R/WHold Time'
Data Hold Time
I Write'
I Read
Fig. 1
0
tHR
RD, WR Pulse Width'
PWRW
RD, WR Delay Time
tRWO
RD, WR Hold Time
tHRW
450
LlR Delay Time
tOLR
-
Lm" Hold Time
tHLR
10
MR Set-up Time'
tSMR
400
MR Hold Time'
tHMR
E Clock Pulse Width at MR
PWEMR
Processor Control Set-up Time
tpcs
Fig. 2
Fig. 3,
13,14
10
280
160
-
-
10
-
230
70
9
-
20
-
9
-
200
-
-
200
-
-
200
100
-
-
100
-
teA
Fig.3
tRC
Fig. 14
20
Reset Pulse Width
PW RST
Fig. 2, 3
-
40
100
Oscillator Stabilization Time
tpCt
200
220
-
BA Delay Time
tpcr
Processor Control Fall Time
20
0
-
-
-
Processor Control Rise Time
3
-
Unit
max
100
250
-
20
3
100
190
-
20
3
25
ns
-
ns
160
ns
120
ns
-
ns
ns
ns
ns
ns
ns
40
ns
20
ns
120
ns
-
ns
-
ns
50
ns
9
fJ-S
-
-
ns
-
100
ns
100
ns
160
ns
-
ms
tCYC
• These timings change in approximate proportion to teye. The figures in this characteristics represent those when teye is minimum (= in the highest speed
operation).
PERIPHERAL PORT TIMING
Item
Symbol
Peripheral Data
Set UpTime
Port 1, 2, 3,
4,5,6
t pDSU
Peripheral Data
Hold Time
Port 1. 2. 3.
4.5.6
tpDH
Delay Time (From
Enable Fall Edge to
Peripheral Output)
Port 1. 2. 3.
4.5.6,7
tpWD
Input Data Hold Time
Port 6
tlH
Input Data Set-Up Time
Port 6
tiS
Input Strobe Pulse
Width
Output Strobe Delay Time
Test
Condition
HD6301YO
HD63A01YO
HD63B01YO
Unit
min
typ
max
min
typ
max
min
typ
max
200
-
-
200
-
-
200
-
-
ns
200
-
-
200
-
-
200
-
-
ns
-
-
300
-
-
300
-
-
300
ns
200
-
-
200
-
-
200
-
-
ns
150
-
-
150
-
-
150
-
ns
100
-
-
100
-
-
100
-
-
ns
-
-
200
-
-
200
-
-
200
ns
Fig. 5
Fig. 6
t pWIS
Fig. 10
tOSDl
Fig. 11
tOSD2
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
361
HD6301YO,HD63A01YO,HD63B01YO---------------------TIMER. SCI TIMING
Item
Symbol
HD6301YO
HD63A01YO
min
typ
max
min
typ
max
min
typ
-
2.0
-
-
2.0
-
-
tcyc
400
-
400
-
400
ns
1.0
-
1.0
-
-
2.0
-
-
220
-
-
220
ns
-
260
-
-
ns
Timer 1 Input Pulse Width
tpWT
Fig. 9
2.0
Delay Time (Enable Positive
Transition to Timer Output)
tTOD
Fig. 7. 8
-
-
Fig. 9
1.0
-
Fig.4
2.0
-
2.0
-
-
220
-
-
260
-
-
260
-
SCI Input
Clock Cycle
I Async. Mode
I Clock Sync.
tSCYC
HD63B01YO
Test
Condition
max
Unit
tCYC
tCYC
SCI Transmit Data Delay
Time (Clock Sync. Mode)
tTxD
SCI Receive Data Set-up
Time (Clock Sync. Mode)
tSRX
SCI Receive Data Hold Time
(Clock Sync. Mode)
tHRX
100
-
-
100
-
-
100
-
-
ns
SCI Input Clock Pulse Width
tpWSCK
0.4
-
0.6
0.4
-
0.6
0.4
-
0.6
ts cvc
Timer 2 Input Clock Cycle
Fig. 4
ttcyc
2.0
2.0
2.0
tcyc
tpWTCK
-
-
200
-
-
200
-
-
200
-
-
Timer 2 Input Clock Pulse
Width
-
ns
Timer 1 ·2. SCI Input Clock
Rise Time
tCKr
-
-
100
-
-
100
-
-
100
ns
Timer 1 • 2. SCI Input Clock
Fall Time
tCKf
-
-
100
-
-
100
-
-
100
ns
362
Fig. 9
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301YO,HD63A01YO,HD63B01YO
~---------tcvc----------l
~---PWEL-----<-l
f------PWEH----'O~
2.4V
O.8V
MCU Write
00-07
----------------------------+-------~
MCU Read
00-07
----------------------------+---------~
LlR
Figure 1
Mode 1, Mode 2 Bus Timing
f-------PWEMR - - - - - - i
\
\
\
'-----
O.8V
MR
Figure 2
Memory Ready and E Clock Timing,
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
363
HD6301YO,HD63A01YO,HD63B01YO---------------------------------------------Last Instruction
,Execution Cycle,
Instruction Execution
Cycle
HALT Cycle
E
HALT
tBAI----t,.---(I-----.....;..;........;---_
BA
Figure 3
HALT and BA Timing
Synchronous Clock
Transmit Data
Receive Data
·2.0V is high level when clock input.
2.4V is high level when clock output.
Figure 4
SCI Clocked Synchronous Timing
jMCU Write
jMCU Read
E
E
PlO- P'7, P20"": P27,
P30-P37, P40-P47,------""" r~~-
Pso- PS7, P60- P67,
P70- P74
(Outputs)
P30- P37
(Inputs)
Figure 5
364
Port Data Set-up and Hold Times (MCU Read)
Figure 6
Port Data Delay Times (MCU Write)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301YO,HD63A01YO,HD63B01YO
E
E
T2CNT
Timer
FRC
P21,
P26
Output
P25
Outputs --------~ 1"-=.::.---Figure 7
Timer
••
Timer 2 Output Timing
tCKf
'Timer 2 ; ttcyc
SCI
; tScyc
Figure 9
(TCONR=N)
Figure 8
Output Timing
"Timer 1 ; tPWT
Timer 2; tPWTCK
SCI
; tPWSCK
PORT6
Data
(Input)
Timer 1 ·2, SCI Input Clock Timing
Figure 10
Port 6 Input Latch Timing
Vcc
Test Point
MCU access of
PORT6
:p:i
C
E
R
RL=2.2kQ
1 S2074(8)
or Equiv.
C = 90pF for Port 1, Port 3, Port 4, E
=30pF for Port 2, Port 5, Port 6, Port 7
R=12kQ for Port 1 - Port 7, E
Figure 11
Figure 12
Output Strobe Timing
Bus Timing Test Loads (TTL Load)
Interrupt
Test
Internal
Address Bus
-_J'--!-..J'--_J\.._..J'-_.A._...J'-_.A._...J'-_A._-"'--_"-_..J'o.....-.J"-_A_-''-_J\...
NMI. iRQ,.
IR02.IRO,
Internal
Data Bus _ _J'-_..J'-_J\.._..J''--_A._-'''-_.A._...J'-_A._..J'o_ _''-_.J'\_-.J''-_A._-'''--_.AOp
Operand Irrelevant pca - PCB IXO IXB ACCA
ACCB
CCR
Vector Vector First Inst of
Code Op Code Data
PC7
PC 15
IX7
IX 15
MSB
LSB
Interrupt Routine
Internal
Read
Internal
Write
\
- _____.....1
\
Figure 13
Interrupt Sequence
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
365
HD6301YO,HD63A01YO,HD63B01YO----------------------
Vee
fi~j---_s,s~v----------~------~--------------~i~!~
/I---'-'-=-'------·AC------1
~___..;f___+_+____----;
IllS _ _ ...
, ___________ .)...---..11
VC
C
-O.
5V
t'C~
tpes
vee -O.5V
O.SV
- - . . . . , j j -_ _ _ _ _ _ _ __
-=X::X:=
~~~,.ss&l)\\\\\\\\\\\\\\\\\\\\C:X=~ ___
FFFF
FFFF FFFF
FFFF
FFFf FFFE
FFFF New PC
FFFF
FFFF
I~>-------III-r_ _ _ _ _ _ __
w,",naI8\l)\\\_\\\\\\\\\\\\
w·,"al"~\\\\\\\\\\\\\\\\\\\\\'
RtW
BI"'Wmlml"m.-IIII'lIIItllll'r----1t-----------------------,~~f
lID
B\\t~MM\i\\\\\\I'
WI!
~~\\»\\\\\\\\\\\\\\\\\\.
,~~,......,....."
f~~IJ-J- - - -
g:a BI'l)llltll\1li••illll\1I••ijllill~------------:;:O-O--O-:~I----{.'f-f-----PCB PC 15
Figure 14
•
FUNCTIONAL PIN DESCRIPTION
•
• Vee, Vss
Vee and Vss provide power to the MCU with 5V ± 10% supply.
In the case of low speed operation (fmax = 500kHz), the MCU can
operate with 3 to 5.5 volts. Two Vss pins should be tied to ground.
•
XTAL, EXTAL
These two pins interface with an AT-cut parallel resonant crystal.
Divide-by-four circuit is on chip, so if 4MHz crystal oscillator is
used, the system clock is IMHz for example.
EXTAL pin can be drived by the external clock with 45% to 55%
duty. The system clock which is one fourth frequency of the external clock is generated in the LSI. The external clock frequency
should be less than four times of the maximum operating frequency. When using the external clock, XTAL pin should be open. Fig.
15 shows examples of connection circuit. The crystal and CLl, CL2
should be mounted as close as possible to XTAL and EXTAL pins.
Any line must not cross the line between the crystal oscillator and
XTAL, EXTAL.
AT Cut Parallel Resonant Crystal Oscillator
Co=7pF max
Rs=60Q max
XTALI------.-----.
CJ
Cll =Cl2
= 10pF-22pF±20%
EXTALI---.--.....
PCO PC7
FIr.t
Instruction
Reset Timing
STBY
This pin makes the MCU standby mode. In "Low" level, the
oscillation stops and the internal clock is stabilized to make reset
condition. To retain the contents of RAM at standby mode, "0"
should be written into RAM enable bit (RAME). RAME is the bit
6 of the RAM/port 5 control register at $0014. RAM is disabled by
this operation and its contents is sustained.
Refer to "LOW POWER DISSIPATION MODE" for the
standby mode.
• Reset (RES)
This pin resets the MCU from power OFF state and provides a
startup procedure. During power-on, RES pin must be held "Low"
level for at least 20ms.
The CPU registers (accumulator, index register, stack pointer,
condition code register except for interrupt mask bit), RAM and
the data register of ports are not initialized during reset, so their
contents are undefined in this procedure.
To reset the MCU during operation, RES should be held "Low"
for at least 3 system-clock cycles. At the 3rd cycle d~ "Low"
level, all the address buses become "High". When RES remains
"Low", the address buses keep "High". If RES becomes "High",
the MCU starts the next operation.
(1) Latch the value of the mode program pins; MPo and MP!.
(2) Initialize each internal register (Refer to Table 6).
(3) Set the interrupt mask bit. For the CPU to recognize the
maskable interrupts IRQ!> IRQ2 and IRQ3' this bit should be
cleared in advance.
(4) Put the contents (=start address) of the last two addresses
(SFFFE, SFFFF) into the program counter and start the
program from this address. (Refer to Table 1).
(3.2-8MHz)
•
Enable (E)
•
Non-Maskable Interrupt (NMI)
This pin provides a TTL-compatible system clock to external circuits. Its frequency is one fourth that of the crystal oscillator or
external clock. This pin can drive one TIL load and 90pF capacitance.
Figure 15
366
Connection Circuit
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------HD6301YO,HD63A01YO,HD63B01YO
When the falling edge of the input signal is detected at this pin,
the CPU begins non-maskable interrupt sequence internally. As
well as the IRQ mentioned below, the instruction being executed at
NMI signal detection will proceed to its compeletion. The interrupt
mask bit of the condition code register doesn't affect non-maskable
interrupt at all.
In response to an NMI interrupt, the contents of the program
counter, index register, accumulators and condition code register
will be saved onto the stack. Upon completion of this sequence, a
vector is fetched from $FFFC and $FFFD to transfer their contents
into the program counter and branch to the non-maskable interrupt
service routine.
(Note) At reset start, the stack pointer should be initialized on
an appropriate memory area and then the falling edge
be input to NMI pin.
•
Interrupt Request
CfRQ1, 1RQ2)
These are level-sensitive pins which request an internal interrupt
sequence to the CPU. At interrupt request, the CPU will complete
the current instruction before the acceptance of the request. Unless
the interrupt mask in the condition code register is set, the CPU
starts an interrupt sequence; if set, the interrupt request will be ignored. When the sequence starts, the contents of the program
counter, index register, accumulators and condition code register
will be saved onto the stack, then the CPU sets the interrupt mask
bit and will not acknowledge the mask able request. During the last
cycle, the CPU fetches vectors depicted in Table 1 and transfers
their contents to the program counter and branches to the service
routine.
The CPU uses the external interrupt pins (IRQ! and IRQ2) also
as port pins P50 and P51, so it provides an enable bit to Bit 0 and 1 of
the RAM port 5 control register at $0014. Refer to "RAM/PORT 5
CONTROL REGISTER" for the details.
When one of the internal interrupts, ICI, OCI, TOI, CMI or SIO
is generated, the CPU produces internal interrupt signal (IRQa).
IRQa functions just the same as IRQ! or IRQ2 except for its vector
address. Fig. 16 shows the block diagram of the interrupt circuit.
Each Status Register's Interrupt
Enable Flag
"'" ; Enable "0'" Disable
.~-o-
ISF
IRQt
~
IRQ2
~~
ICF
OCF1
-0-
OCF2
-0-
-""
TOF
IRQ3
CMF
RORF
PER
ORFE
TORE
n
..-;:..
:J
-I
""-0-0-
ICI
Condition
Code
Register
I MASK
"0"; Enable
'" " ; Disable
~~
TOI
CMI
~ignal
---~
-J
Edge
Detective
Circuit
Address Error
Op Code Error
DetectIve CIrcuit
Interrupt
~ Request
Sleep
Cancel
Signal
TRAP
SWI
Figure'6
Interrupt Circuit Block Diagram
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
367
HD6301YO,HD63A01YO,HD63B01YO--------------_ _ _ _ _ _ __
Table 1 Interrupt Vector Memory Map
Priority
Highest
Lowest
•
Vector
MSB
low-speed memories (See Fig. 2). Up to 9ILs can be stretched.
During internal address space access or non valid memory
access, MR is prohibited internally to prevent decrease of operation
speed. Even in the halt state, MR can also stretch "High" period of
system clock to allow peripheral devices to access low-speed memories. Refer to "RAM/PORT 5 CONTROL REGISTER" for more
details.
Interrupt
LSB
FFFE
FFFF
RES
FFEE
FFEF
TRAP
FFFC
FFFD
NMI
•
FFFA
FFFB
SWI
(Software Interrupt)
FFF8
FFF9
IRQ,. ISF (port 6 Input Strobe)
FFF6
FFF7
ICI
(Timer 1 Input Capture)
FFF4
FFF5
OCI
(Timer 1 Output Compare 1. 2)
FFF2
FFF3
TOI
(Timer 1 Overflow)
This is an input control signal to stop instruction execution and
to release b~ses. When this signal switches to "Low", the CPU
stops to enter into the halt state after having executed the present
instruction. When entering into the halt stat~ makes BA (P74 )
"High" and also an address bus, data bus, RD, WR, R/W high
impedance. When an interrupt is generated in the halt state, the
CPU uses the interrupt handler after the halt is cancelled.
(Note) Please don't switch the HALT signal to "Low" when
the CPU executes the WAI instruction and is in the interrupt wait state to avoid the trouble of the CPU's operation after the halt is cancelled.
FFEC
FFED
CMI
(Timer 2 Counter Match)
•
FFEA
FFEB
IRQ2
FFFO
FFF1
SIO
(RDRF + OR FE + TORE + PER)
Mode Program (MPo, MP,)
The following signal descriptions are applicable only for the
expanded mode.
Read/Write (R/VV; P72)
This signal, usually be in read state ("High"), shows whether
the CPU is in read ("High") or write ("Low") state to the
peripheral or memory devices. This can drive one TTL load and
30pF capacitance.
•
Table 2
Load Instruction Register (LlR; P73)
This signal shows the instruction opecode being on data bus
(active low). this pin can drive one TTL load and 30pF capacitance.
•
Memory Ready (MR; P62)
This is the input control signal which stretches the system
clock's "High"period to access low-speed memories. HD630lYO can
select three kinds of low-speed memory access method by RAM/
Port 5 Control Register's MRE bit and AMRE bit. In the case that
CPU accesses low-speed memories by the external MR signal
(MRE="I", AMRE="O"), the system clock operates in normal
sequence when this signal is in "High".
But this signal in "Low", the "High" period of the system clock
will be stretched depending on its "Low" level duration in integral
multiples of the cycle time. This allows the CPU to interface with
368
PORT
The HD6301 YO provides seven I/O ports. Port 1, 2, 3, 4, 5, and
6 are 8-bit I/O ports. Each port provides Data Direction
Register(DDR). Port 1 and port 3 select the I/O state by the byte
and port 2, 4, 5 and 6 the I/O state by the bit. Port 7 is a 5-bit output-only port. In the expanded mode (mode 1, mode 2), port 3
becomes data buses, port 1 and port 4 address buses and port 7 control signal pins.
• RD, WR (P 7 o, P71)
These signals show active low outputs when the CPU is readingl
writing to the peripherals or memories. This enables the CPU easy
to access the peripheral LSI with RD and'WR input pins. These pins
can drive one TTL load and 30pF capacitance.
•
Bus Available (BA; P7,.)
This is an output control signal whicb is normally "Low" but
"High" when the CPU accepts HALT and releases the buses. The
HD6800 and HD6802 make BA "High" and release the buses at
WAI execution, while the HD6301YO doesn't make BA "High"
under the same condition.
These two pins decide the operation mode. Refer to "MODE
SELECTION" for more details.
•
Halt (HALT; P63)
•
Port and Data Direction Register Address
Port
Port Address
Data Direction Register
Port 1
$0002
$0000
Port 2
$0003
$0001
Port 3
$0006
$0004
Port 4
$0007
$0005
Port 5
$0015
$0020
Port 6
$0017
$0016
Port 7
$0018
Port 1
An 8-bit 110 port. The DDR of port 1 (PlODR) controls the 1/0
state. It provides a bit which select the I/O state by the byte ("0" for
input and "1" for output).
As it is cleared during reset, port 1 is an input port.
In the expanded mode (mode 1, mode 2), port 1 functions as a
lower address buses (Ao to A7)' Port 1 can drive one TTL load and
90pF capacitance.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301YO,HD63A01YO,HD63B01YO
WP1D
Mode 1
Mode 2
RES
reset
I I I -I I -I -I I~: Ir~~t~~~~,~~goO)
MSB
....._--..1.._ - - ' ._ _....._---I..._ - - ' ._ _L.._--L.._--l.
~~~!~red dUring
Port 1 ($0002)
P
17
I P
1s
1 P
1S
\
P
14
\
P
13
\
P
12
\
Pll
I P :;~l~~:i~~
lO
\
can produce 1rnA when Vout = 1.5V to drive directly the base of
Darlington transistor.
• Port2
An 8-bit I/O port. Port 2 DDR (P2DDR) controls the I/O state.
This port provides DDR corresponding to each bit and can define
input or output by the bit ("0" for input, "1" for output).
As Port 2 DDR is cleared during reset, it will be an input port.
Port 2 is also used as an I/O pin for timer 1, Timer 2 and the SCI.
Pins for Timers and the SCI set or reset each DDR depending on
their functions and become I/O pins. When port 2 functions as an 1/
o port after used as I/O pins of the timers or the SCI, the I/O direction of the pins remain as it is used as the I/O pin of timer and SCI.
Port 2 can drive one TTL load and 30pF capacitance. This port
P20 (Tin)
P20 is also used as an external input pin for the input-capture.
This pin is an I/O port which is an input or output as defined by the
Data Direction Register (P 2o DDR) ("0" for an input and "1" for
an output). Then either a signal to or from P20 ("to" for an output
port, "from" for an input port) is always input to the Timer 1 input
capture.
RES
~-----~ Q
R
WP4
-L-
CJ)
CJ)
Q)
Q;
c.
c.
C
Mode 1
Mode 2
aJ
WP4D : DDR Write signal
WP4 : Port Write signal
RP4
: Port Read signal
* Priority: set> reset
PORT4 DDR ($0005)
(Write only, $00
during reset.)
PORT4 ($0007)
(R/W, not initialized during
reset.)
• Port5
An 8-bit I/O port. The DDR of port 5 controls I/O state. Each bit
of port 5 has a DDR which defines I/O state ("0" for input and" 1"
for output).
During reset, the DDR of port 5 is cleared and port 5 becomes
an input port.
Port 5 is also usable as IRQ!> IRQ, HALT, MR and the strobed
signal of port 6 for handshake
It is set to input or output
automatically if it is used as these control signal pins (except PS4 ,
IS). Since the DDR of port 5, as is port 2, is set or reset by the control signal, I/O directions of the I/O ports are retained after the control signal is disabled. Port 5 can drive one TTL load and 90pF
capacitance.
as, ®.
372
Pso and PSI are also usable as interrupt pins. The RAM/port 5
control registers of IRQ I and IRQ2 have enable bits OQIE, IQ2E).
When these bits are set to "1", Pso and PSI will automatically be
interrupt input pins.
P62 (MR), P63 (HALT)
PS2 and PS3 are also usable as MR and HALT inputs. MR and
HALT have enable bits (MRE, HLTE) in the RAM/Port 5 Control
Register as IRQI and IRQ2' In the single chip mode (Mode 3), PS2
and PS3 are usable as I/O ports regardless of the value of the enable
bits. In the expanded mode (Mode 1 or Mode 2), since MRE is
cleared during reset, PS2 is usable as an I/O port. Since HLTE is set
during reset, the DDR of PS3 will be automatically reset to be a
HALT input pin. HLTE of the RAM/Port 5 Control Register has to
be cleared to use PS3 as an I/O port.
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301YO,HD63A01YO,HD63B01YO
RES
R1
R2
~--------_40
D~--~-'
PS n DDR
C
WP5D
~-------IO
DI----4----4~
Q;
PS n DATA
C
RP5
~
E
WP5
--L
WP5D : DDR Write signal
WP5 : Port Write signal
RP5
: Port Read sig·nal
L..--+------4II---IRAM/PORT
5 Control
Register
___________+-______
iRa 1
_ - -___.iRa2
MR
~~
HALT
* Initializing
IRQ1E
value during reset;
= "0",
IRQ2E
= "0",
MRE
= "0"**,
** P52 and P53 can be used as I a ports
HLTE
= "1"**
in spite of the value of this register in Mode 3.
P54(lS)
P54 is also usable as the input strobe (IS) for port 6 handshake
interface. This pin, as is P20 , is always an I/O port. If P54 is used as
an output port (set the DDR of P54 to "1"), an output signal from
P54 will be the input to IS.
RES
R
.---------10
D ~--.....
P S4 DDR
C
CJl
:l
co
WP5D
!:!
ro
D 1----1 0
1------10
PS4
ro
DATA
c
Q;
C
RP5
C
WP5
-L
>--=15=------------+---...
P 55 (OS)
po.; is also usable as the output strobe (OS) for port 6 handshake
interface. It will be an I/O port during reset, and an as output pin
Port 6 Control Status Register
by setting the OS enable register (OSE) of the port 6 Control Status
Register (P6CSR).
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
373
HD6301YO,HD63A01YO,HD63B01YO---------------------RES
Ul
:::I
III
0
C
~
co
0
WP5D
i6
Pss DDR
E
2l
.::
Q
D
PssDATA
Port 6 Control/Status Register
C
r---- - ----I
WP5
I
~TT~_+------------_+-----+--OS
OSE (1 : OS output
)
o : OS output disable
PS8. PS7
PS6 and PS7 are 110 ports.
RES
R
D
PS n DDR
Q
C
Ul
:::I
III
WP5D
~
co
Q
D
PS n DATA
c
WP5
0
i6
E
2l
.::
PORTS DDR ($0020)
(Write only, $00
during reset.)
• Port6
8-bit 110 port. Port 6 DDR controls 110 state. Each bit of port 6
has a DDR and designates input or output ("0" for input, "1" for
output). During reset, Port 6 DDR is cleared and port 6 becomes an
input port.
374
Port 6 controls parallel handshake interface besides functions as
an 110 port. Therefore, it provides DDRs to control and IS LATCH
to latch the input data.
Port 6 can drive one TTL load and 30pF capacitance. It can drive
directly the base of Darlington transistor as port 2.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------HD6301YO,HD63A01YO,HD63B01YO
RES
R
r--------iQ
'"
Dt-----i~
!9
PSn DDR
C
~
WP6D
(ij
E
D ~--....... ~
PSn DATA
r------I Q
C
WP6
R5
RP6
D
WP6D : DDR Write signal
WP6 : Port Write signal
RP6
: Port Read signal
--...L
R
Q
IS LATCH
C
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ Port 6
Control/Status Register
LSB
PORT6 DDR ($0016)
(Write only. $00
during reset.)
L-_-'-_-'-_...1..._....I-_....I-_-L-_-L-_--I
I I
Pe7
Peel p e5
j Pe41
P631 Pe21 Pel
I I
PeD
PORT6 ($0017)
(RIW. not initialized during
reset.)
as an output port. CPU 7 can also read the Port 7 data register to execute bit manipulation instruction. In the expanded mode (Mode 1,
Mode 2), Port 7 is an output pin for control signals (RD, WR, RI
W, UR, BA) from the CPU.
Port 7 can drive one TIL load and 30pF capacitance ..
• Port 7
A 5-bit output vort. In single-chip mode (Mode 3), port 7 goes
to a high impedance state during reset. By a write to Port 7, Port 7
goes to the output state from the high impedance ~tate, and it outputs the written data. Once it becomes output state, Port 7 functions
RES
R
WP7
5,
Mode 1.Mode 2
Q
,-5_2_*_ _-'
!9
III
D...-_ _-+.... O
Q
P7n
DATA
C
WP7
(ij
E
~
WP7: Port Write signal
RP7 : Port Read signal
Mode 1
Mode 2
-L
'------------+--1--- CPU
* Priority: S2 > R. SI
Control Signal
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
375
HD6301YO,HD63A01YO,HD63B01YO---------------------•
RAM/PORT 6 CONTROL REGISTER
Bit 3 Halt Enable Bit (HLTE)
The control register located at $0014 controls on-chip RAM and
port 5.
RAM/Port 5 Control Register (RP5CR)
(Note)
$0014
Bit 0, Bit 1
When using P53 as an input pin of the HALT signal, write" 1" in
this bit. When this bit is set, P53 DDR is automatically cleared and
becomes the Halt input pin. If the bit is "0", the Halt function is
inhibited and P53 is used as an 110 port. The bit is set to "1" during
reset. However, in Mode 3, Halt function is inhibited regardless of
the bit.
When using P52 and P53 as the input ports in mode 1
and 2, MRE and HLTE bit should be cleared just after
the reset.
Bit 4 Auto Memory Ready Enable Bit (AMRE)
TR01, IRQ2 Enable Bit (lRO,E, IR02E)
When using P50 and P51 as interrupt pins, write "1" in these bits.
When the bit is set to "1", the DDRs correspo~g to P 50 and
P51 are cleared and become IRQ; input pin and
2 input pin.
When IRQIE and IRQ2E are set, P50 and P51 cannot be used as an
output ports. When "0", the CPU doesn't accept an external interrupt or a sleep cancellation by the external interrupt. These bits are
cleared during reset.
. When the bit is set and the CPU accesses the external address,
"memory ready" operates automatically and stretches the E clock's
"High" duration for one system clock. When MRE bit of bit 2 is
cleared and when the CPU accesses the external address space, the
function operates. When MRE bit is set and then the CPU accesses
the external address space with P52 (MR) pin in "low", "memory
ready" operates automatically. In Mode 3, regardless of the bit
value, the "auto memory ready" function is inhibited. (See Table 3
and Fig. 17.)
Bit 2 Memory Ready Enable Bit (MRE)
When using P52 as an input pin of the "memory ready" signal,
write "1" in this bit. When set, P52 DDR is automatically cleared
and becomes the MR input pin. In Mode 3, however, the "memory
ready" is inhibited regardless of the bit. The bit is cleared during
reset.
Table 3
Since this bit is set to "1" during reset, clear the bit
at the beginning of the program when auto memory
ready doesn't have to operate.
"Memory Ready" Function
MRE
AMRE
0
0
"Memory ready" inhibited.
0
1
When the CPU accesses the external address, "High" duration of E clock automatically becomes one-cycle
longer. This state is retained during reset.
1
0
"Memory ready" operates by P52 (MR) pin. The function is the same as that of the HD6301 XO.
1
1
When the CPU accesses the external address space with the P52 (MR) pin in "low", the "auto memory
ready" operates. This function is effective if it has both "high-speed memory" and "slow memory"
outside. Input CS signal of "slow memory" to MR pin.
Function
Bit 6 Standby Flag (STBV FLAG)
By clearing this flag, HD6301YO gets into the standby mode by
software. This ~is set to "1" during reset, so the standby mode is
canceled with RES pin in "low". The RES pin should be in "low"
until oscillation becomes stable (min. 2Oms.).lfthe STBY pin in is
in "low", the standby mode can not be canceled with the RES pin
in "low".
Bit 6 RAM Enable (RAM E)
On-chip RAM can be disabled by this control bit. By resetting
the MCU, "1" is set to this bit, and on-chip RAM is enabled.
376
(Note)
When this bit is cleared (=logic "0") on-chip RAM is invalid and
the CPU can read data from external memory. This bit should be
"0" before getting into the standby mode to protect on-chip RAM
data.
Bit 7 Standby Power Bit (STBY PWR)
When Vee is not provided in standby mode, this bit is cleared.
This is a flag for read/write and can be read by software. If this bit is'
set before standyby mode, and remains set even after returning
from standby mode, Vee voltage is provided during standby mode
and the on-chip RAM data is valid.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301YO,HD63A01YO,HD63B01YO
(a) MRE=O, AMRE=1
E
Address
,
,
,
external add ress
external address
Bus
internal address
(b) MRE= 1, AMRE= 1
E
Address
external address
Bus
external address
MR
(CS pin of "slow memory")
(e) MRE= 1,AMRE=O (HD6301XO Compatible Mode)
E
Address
Bus
MR
Figure 17
•
Memory Ready Timing
Port 6 Control/Status Register
This is the Control/Status Register for parallel handshake interface using Port 6. The functions are as follows;
1) Latches input data to Port 6 at the IS (PM) falling edge.
2) Outputs a strobe signal OS (P55 ) outward by reading or writing to port 6.
3) When IS FLAG is set at the IS falling edge, an interrupt
occurs.
The following shows Port 6 Control/Status Register (P6CSR).
the input latch remains canceled and this bit functions as a usual
I/O port. This bit is cleared during reset.
Bit 4: OSS Output Strobe Select
This register initiates an output strobe (OS) from P55 by reading
or writing to port 6. When cleared, OS occurs by reading Port 6.
When set, OS occurs by writing to Port 6. This bit is cleared during
reset.
Bit 5: OSE Output Strobe Enable
$0021
This register decides the enabling or disabling of the output
strobe. When cleared, P55 functions as an I/O port. When set, P55
functions as an OS output pin. (P55 DDR is set by OSE.) This bit is
cleared during reset.
Bit 6: IS IRQ, Enable Input Strobe Interrupt Enable
BitO
Bit 1
Bit2
"Bit 7 is Read-Only bit
Not used.
When set, an IRQ! interrupt to the CPU occurs by setting IS
FLAG of bit 7. When cleared, the interrupt does not occur. This bit
is cleared during reset.
Bit 3: Latch Enable
Bit 7: IS Flag Input Strobe Flag
This register controls the input latch for Port 6 (ISLATCH).
When this bit is set to "1", the input data to port 6 will be latched
inward at the IS (P 54 ) falling edge. An input latch will be canceled
by reading Port 6, which enables to latch the next data. If cleared,
This flag is set at the IS (PS4 ) falling edge. This flag is for readonly. When set, the flag is cleared by reading or writing to Port 6
after reading the Port 6 Control Status Register. This bit is cleared
during reset.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
377
HD6301YO,HD63A01YO,HD63B01YO-----------------------
HD6301YO
Port 6 Control/Status Register
) - - - -...iRQ,
Figure 18
•
Input Strobe Interrupt block Diagram
address externally can be used as the input port
MODE SELECTION
Mode program pins, MPa and MP} determine the operation
mode of the HD6301 YO as Table 4 shows.
•
•
Mode 3 (Single-chip Mode)
In this mode, all ports are available (refer to Fig. 21).
Mode 1 (Expanded Mode)
In this mode, port 3 is data bus and port 1 "Lower" address bus
and port 4 "Upper" address bus to interface directly with the
HMCS6800 buses. A control signal such as R/W is produced at port
7. In mode 1, on-chip ROM is disabled and 65k bytes of address
space are externally expandable (refer to Fig. 19).
Table 4
Mode
MP,
MP o
ROM
RAM
Interrupt
Vector
1
"L"
"H"
E
I'
E
Expanded
Mode
2
"H"
"L"
I
I'
I
Expanded
Mode
3
"H"
"H"
I
I
I
Single-chip
Mode
• Mode 2 (Expanded Mode)
This mode is also expandable as well as mode I. But in this
mode, on-chip ROM is enabled and the expandable address space is
48k bytes (refer to Fig. 20).
In Mode 2, port 4 is available as an input port during reset, and
so the upper address is not output outwards. After reset starts, set
the P4DDR corresponding to the external address output. By setting the DDR, the upper address is output. When a small external
memory space is provided, the pin not required to output the
•
Mode Selection
=
Operation
Mode
=
"L"
Logic "0", "H"
Logic "''',1; Internal, E; External.
• The addressing RAM area can be external by clearing RAME bit $00'4.
Mode and Port
Table 5 shows MCV signals in each mode.
Table 5
~
Mode 1
Port
378
MCU Signals in Each Mode
Mode 2
Mode 3
Port 1
Address Bus (A o -A7)
Address Bus (A o --A 7)
I/O Port
Port 2
110 Port
I/O Port
I/O Port
Port 3
Data Bus (00-07)
Data Bus (00-07)
I/O Port
Port 4
Address Bus (As-A,5)
110 Port or Address Bus (A s -A,5)
I/O Port
Port 5
110 Port
I/O Port
I/O Port
Port 6
I/O Port
I/O Port
I/O Port
Port 7
RO, WR. R/W, LlR. BA
RO, WR, R/W, LlR, BA
Output Port
$
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
~~~~~~~~~~~~~~~~~~~~~~~HD6301YO.HD63A01YO.HD63B01YO
RES
STBY
NMI
PORT2
HD6301YO
MCU
(~~er1.2)
PORT5
(W~)
PORT6
Figure 19
E
E
RD
AD
WR
WR
R/W
LIR
RjW
ill
BA
BA
PORT3
Data Bus
PORT3
Data Bus
PORTl
Address Bus
PORTl
Address Bus
PORT4
Address Bus
PORT4
Address Bus
or Input Ports
Figure 20
Mode 1
Mode 2
E
PORT7
HD6301YO
PORT3
MCU
PORT1
PORT5
(~RQ')
PORT4
Figure 21
Mode 3
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
379
HD6301YO,HD63A01YO,HD63B01YO---------------------Table 6 Internal Register
Address
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
20
21
22
23
24
25
26
27
•
380
Register
Abbreviation
P1DDR
P2DDR
PORT1
PORT2
P3DDR
P4DDR
PORT3
PORT4
TCSR1
FRCH
FRCL
OCR1H
OCR1L
ICRH
ICRL
TCSR2
RMCR
TRCSR1
RDR
TOR
RP5CR
PORT5
P6DDR
PORT6
PORT7
OCR2H
OCR2L
TCSR3
TCONR
T2CNT
TRCSR2
TSTREG
P5DDR
P6CSR
Port 1 DDR (Data Direction Register)
Port 2 DDR
Port 1
Port 2
Port 3 DDR
Port 4 DDR
Port 3
Port 4
Timer Control/Status Register 1
Free Running Counter (MSB)
Free Running Counter (LSB)
Output Compare Register 1 (MSB)
Output Compare Register 1 (LSB)
Input Capture Register (MSB)
Input Capture Register (LSB)
Timer Control/Status Register 2
Rate/Mode Control Register
Tx/Rx Control Status Register 1
Receive Data Register
Transmit Data Register
RAM/Port 5 Control Register
Port 5
Port 6 DDR
POrl6
Port 7
Output Compare Register 2 (MSB)
Output Compare Register 2 (LSB)
Timer Control/Status Register 3
Time Constant Register
Timer 2 Up Counter
Tx/Rx Control Status Register 2
Test Register"
PORT 5 DDR
PORT 6 Control/Status Register
-
-
Reserved
-
R/W""
W
W
R/W
R/W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R
W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
W
R/W
-
-
-
Initialized value
during reset"""
$FE
$00
indefinite
indefinite
$FE
$00
indefinite
indefinite
$00
$00
$00
$FF
$FF
$00
$00
$10
$CO
$20
$00
indefinite
$F8or$78
indefinite
$00
indefinite
indefinite
$FF
$FF
$20
$FF
$00
$28
$00
$07
-
-
Register for test. Don't access this register.
R: Read-only register, W: Write-only register, R/W: Read/Write register.
When empty bit is in the register, it is set to "'"
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------HD6301YO,HD63A01YO,HD63B01YO
$0000
r------------~
$0027
r----;::-Ex'7
te:":rn:":a';""l':":'Me:":m:":o--ry-----1
Space
Internal *
Register
$0027
Mode 3
Mode 2
Mode I
$0000r-----------------~
Internal
**
Register
External Memory
Space
$0040
$0000
$0040
$0040
Internal RAM
256 Bytes
Internal RAM
256 Bytes
Internal RAM
256 Bytes
$0 13F I------------------l
Internal
$0027 ......_ _ _ _R_e_g_is_te_r_ _ _--'
$0 13F ~-----------l
$0 13F L..-_ _ _ _ _ _ _ _ _...J
External
Memory
Space
External
Memory
Space
$COOO
$COOO
Internal ROM
16k Bytes
$FFFFL-________________~
$FFFF~
_ _ _ _ _ _ _ _~ $FFFFL..-_ _ _ _ _ _ _ _ _~
** Mode
* Mode
2 does not
include the addresses:
I does not
include the addresses:
$00, $02, $04, $06,
$00, $02, $04, $05,
$06, $07 or $18 which
and $18 which can be
used externally.
can be used externally.
Figure 22
•
H D630 1 YO Memory Map
TIMER 1
The HD630IYO provides a 16-bit programmable timer which
can simultaneously measure an input waveform and generate two
independent output waveforms. The pulse widths of both input/
output waveforms vary from microseconds to seconds.
Timer 1 is configured as follows (refer to Fig. 24).
Control/Status Register 1 (8 bit)
Control/Status Register 2 (7 bit)
Free Running Counter (16 bit)
Output Compare Register 1 (16 bit)
Output Compare Register 2 (16 bit)
Input Capture Register (16 bit)
•
Free-Running Counter (FRC)($0009:000A)
The key timer element is a 16-bit free-running counter driven
and incremented by system clock. The counter value is readable by
software without affecting the counter. The counter is cleared during reset.
When writing to the upper byte ($09), the CPU writes the preset
value ($FFF8) into the counter (address $09, $OA) regardless of
the write data value. But when writing to the lower byte ($OA) after
the upper byte writing, the CPU writes not only the lower byte data
into lower 8 bit, but also the upper byte data into higher 8 bit of the
FRC.
The counter will be as follows when the CPU writes to it by double store instructions (STD, STX, etc.)
Counter value
• Output Compare Register (OCR)
($0008, $OOOC; OCR1) ($0019, $001A: OCR2)
The output compare register is a 16-bit read/write register which
can control an output waveform. The data of OCR is always compared with the FRC.
When the data matches, output compare flag (OCF) in the timer
control/status register (TCSR) is set. If an output enable bit (OE) in
the TCSR2 is "I", an output level bit(OLVL) in the TCSR will be
output to bit 1 (OCR 1) and bit 5 (OCR 2) of port 2. To control the
output level again by the next compare, the value of OCR and
OL VL should be changed. The OCR is set to $FFFF at reset. The
compare function is inhibited for a cycle just after a write to the
upper byte of the OCR or FRC. This is to begin the comparison
after setting the 16 bit value in the register and to inhibit the compare function at this cycle, because the CPU writes the upper byte to
the FRC, and at the next cycle the counter is set to $FFF8.
* For data write to the FRC or the OCR, 2-byte transfer
instruction (such as STX, etc.) should be used.
•
Input Capture Register nCR) ($0000 : OOOE)
The input capture register is a 16-bit read-only register which
stores the FRC's value when external input signal transition generates an input capture pulse. Such transition is controled by input
edge bit (IEDG) in the TCSR 1.
In order to input the external input signal to the edge detector, a
bit of the DDR corresponding to bit 0 of port 2 should be cleared
("0"). When an input capture pulse occurs by external input signal
transition at the next cycle of CPU's high-byte read of the ICR, the
input capture pulse will be delayed by one cycle. In order to ensure
the input capture operation, a CPU read of the ICR needs 2-byte
transfer instruction. The input pulse width should be at least 2 system cycles. This register is cleared ($0000) during reset.
$FFF8
In the case of the CPU write ($ 5AF3) to the FRC
Figure 23
Internal ROM
16k Bytes
Counter Write Timing
•
Timer Control/Status Register 1 (TCSR1) ($0008)
The timer control/status register 1 is an !l-hit register. All bits are
readable and the lower 5 bits are also writahle. The upper 3 bits are
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
381
HD6301YO,HD63A01YO,HD63B01YO---------------------read-only which indicate the following timer status.
Bit 5
The counter value reached to $0000 as a result of counting-up (TOF).
Bit 6
A match has occurred between the FRC and the OCR 1
(OCFO.
.
Bit 7
Defined transition of the timer input signal causes the
counter to transfer its data to the ICR (ICF).
The followings are the each bit descriptions.
Timer Control/Status Register 1
the ICR after the TCSR 1 or TCSR2 read at ICF = 1.
• Timer Control/Status Register 2 (TCSR2) ($OOOF)
The timer control/status register 2 is a 7-bit register. All bits are
readable and the lower 4 bits are also writable. But the upper 3 bits
are read-only which indicate the following timer status.
Bit 5
A match has occurred between the FRC and the OCR2
(OCF2).
Bit 6
The same status flag as the OCFl flag ofthe TCSR 1, bit 6.
Bit 7
The same status flag as the ICF flag of the TCSR 1, bit 7.
The followings are the each bit descriptions.
Timer Control/Status Register 2
$0008
7654321
OLVL 1 Output Level 1
OLVLl is transferred to port 2, bit 1 when a match occurs between the counter and the OCR1.lfbit 0 ofthe TCSR2 (OEO is
set to "I", OLVLl will appear at bit 1 of port 2.
Bit 1
IEDG Input Edge
This bit determines which edge, rising or falling, of input signal of bit 0 of port 2 will trigger data transfer from the counter to
the ICR. For this function, the DDR corresponding to port 2, bit
oshould be cleared beforehand.
IEDG=O, triggered on a falling edge
("High" to "Low")
IEDG = 1, triggered on a rising edge
("Low" to "High")
Bit 2
ETOI Enable Timer Overflow Interrupt
When this bit is set, an internal interrupt (IRQa) by TO! interrupt is enabled. When cleared, the interrupt is inhibited.
EOCI1 Enable Output Compare Interrupt 1
Bit 3
When this bit is set, an internal interrupt (IRQa) by OCIl
interrupt is enabled. When cleared, the interrupt is inhibited.
Bit 4
ElCI Enable Input Capture Interrupt
When this bit is set, an internal interrupt (IRQa) by ICI interrupt is enabled. When cleared, the interrupt is inhibited.
TOF Timer Overflow Flag
Bit 6
This read-only bit is set when the counter increments from
$FFFF by 1. Cleared when the counter's MSB byte ($0009) is
read by the CPU after the TCSRI read at TOF=l.
Bit 6
OCF1 Output Compare Flag 1
This read-only bit is set when a match occurs between the
OCRI and the FRC. Cleared when writing to the OCRI ($OOOB
or $OOOC) after the TCSR 1 or TCSR2 read at OCF = 1.
Bit 7
ICF Input Capture Flag
This read-only bit is set when an input signal of port 2, bit 0
makes a transition as defined by IEDG and the FRC is transferred to the ICR. Cleared when reading the upper byte ($OOOD) of
ICF
Bit 0
382
I
OCF11 OCF21 -
I
0
EOCI2f LVL2 1OE21 OEl
I
$OOOF
Bit 0
OE1 Output Enable 1
This bit enables the OLVLl to appear at port 2, bit 1 when a
match has ocCurred between the counter and the output compare register 1. When this bit is cleared, bit 1 of port 2 will be an
I/O port. When set, it will be an output ofOLVLl automatically.
Bit 1
OE2 Output Enable 2
This bit enables the OLVL2 to appear at port 2, bit 5 when a
match has occurred between the counter and the output compare register 2. When this bit is cleared, port 2, bit 5 will be an 1/
o port. When set, it will be an output ofOLVL2 automatically.
Bit 2
OL VL2 Output Level 2
OLVL2 is transferred to port 2, bit 5 when a match has occurred between the counter and the OCR2. If bit 5 of the TCSR2
(OE2) is set to "1", OLVL2 will appear at port 2, bit 5.
EOCI2 Enable Output Compare Interrupt 2
Bit 3
When this bit is set, an internal interrupt (IRQ3) by OCI2
interrupt is enabled. When cleared, the interrupt is inhibited.
Bit 4
Not used
Bit 6
OCF2 Output Compare Flag 2
This read-only bit is set when a match has occurred between
the counter and the OCR2. Cleared when writing to the OCR2
($0019 or $001 A) after the TCSR2 read at OCF2 = 1.
Bit 6
OCF1 Output Compare Flag 1
Bit 7
ICF Input Capture Flag
OCFl and ICF are dual addressed. If which register, TCSRI
or TCSR2, CPU reads, it can read OCFl and ICF to bit 6 and bit
7.
Both the TCSRI and TCSR2 will be cleared during reset.
(Note) If OEI or OE2 is set to "1" before the first output compare match occurs after reset restart, bit 1 or bit 5 of port 2
will produce ·"0" respectively.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------HD6301YO,HD63A01YO,HD63B01YO
Figure 24
•
Timer 1 Block Diagram
TIMER2
In addition to the timer 1, the HD630IYO provides an 8-bit
reloadable timer, which is capable of counting the external event.
The timer 2 contains a timer output, so the MCU can generate
three independent waveforms. (Refer to Fig. 25.)
The timer 2 is configured as follows:
Control/Status Register 3 (7 bits)
8-bit Up Counter
. Time Constant Register (8 bits)
•
selected by TOSO and TOSI of the TCSR3 will appear at port 2, bit
6. When CMF is set, the counter will be cleared simultaneously and
then start counting from $00. This enables regular interrupts and
waveform outputs without any software support. The TCONR is set
to "$FF" during reset.
•
Timer Control/Status Register 3 (TCSR3) ($001 B)
The timer control/status register 3 is a 7-bit register. All bits are
readable and 6 bits except for CMF can be written.
The followings are each pin descriptions.
Timer 2 Up Counter (T2CNT) ($001 0)
This is an 8-bit up counter which operates with the clock decided
by CKSO and CKS 1 of the TCSR3. The CPU can read the value of
the counter without affecting the counter. In addition, any value
can be written to the counter by software even during counting.
The counter is cleared when a match occurs between the counter
and the TCONR or during reset.
If the write operation is made by software to the counter at the
cycle of counter clear, it does not reset the counter but put the write
data to the counter.
Timer Control/Status Register 3
7
6
ICMF' ECMI'
Bit 0
Bit 1
• Time Constant Register (TCONR) ($001 C)
The time constant register is an 8-bit write only register. It is
always compared with the counter.
When a match has occurred, the counter match flag (eMF) of
the timer control status register 3 (TCSR3) is set and the value
5
-
432
1
°
, T2E' TOS1' TOSO'CKS1/ CKSO/
$0018
CKSO Input Clock Select Q
CKS1 Input Clock Select 1
Input clock to the counter is selected as shown in Table 7
depending on these two bits. When an external clock is selected,
bit 7 of port 2 will be a clock input automatically. Timer 2 detects
the rising edge of the external clock and increments the counter.
The external clock is countable up to half the frequency of the
system clock.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
383
HD6301YO,HD63A01YO,HD63B01YO----------------------
.------ Timer1 FRC
Port 2
Bit 7
Port 2
Bit 6
IRQ3
Figure 25
Timer 2 Block Diagram
Bit 4
Table 7 Input Clock Sele,ct
CKS1
CKSO
0
0
Input Clock to the Counter
E clock
0
1
E clock/S"
1
0
E clock/12S"
1
1
External clock
• These clocks come from the FRC of the timer 1. If one of these clocks is
selected as an input clock to the up counter, the CPU should not write to
the FRC of the timer 1.
Bit 2
Bit 3
TOSO Timer Output Select 0
TOS1 Timer Output Select 1
When a match occurs between the counter and the TCONR
timer 2 outputs shown in Table 8 will appear at port 2, bit 6
depending on these two bits. When both TOSO and TOS I are
"0", bit 6 of port 2 will be an I/O port.
Table S Timer 2 Output Select
Timer Output
TOS1
TOSO
0
0
0
Timer Output Inhibited
1
Toggle Output"
1
0
Output "0"
1
1
Output "'"
" When a match occurs between the counter and the TCONR, timer 2
output level is reversed. This leads to production of a square wave with
50% duty to the extemal without any software support.
384
T2E Timer 2 Enable Bit
When this bit is cleared, a clock input to the up counter is
inhibited and the up counter stops. When set to "I", a clock
selected by CKSI and CKSO (Table 7) is input to the up counter.
(Note) P26 outputs "0" when T2E bit cleared and timer 2 set in
output enable condition by TOSI or TOSO. It also outputs
"0" when T2E bit set "I" and timer 2 set in output enable condition before the first counter match occurs.
Bit 5
Not Used.
ECMI Enable Counter Match Interrupt
Bit 6
When this bit is set, an internal interrupt ORQ3) by CMI is
enabled. When cleared, the interrupt is inhibited.
Bit 7
CMF Counter Match Flag
This read-only bit is set when a match occurs between the up
counter and the TCONR. Cleared by writing "0" at CMF = I by
software (unable to write "I" by software).
Each bit of the TCSR3 is cleared during reset.
• SERIAL COMMUNICATION INTERFACE (SCI)
The Serial Communication Interface (SCI) in the HD630lYO
contains the following two operating modes: asynchronous mode by
the NRZ format, and clocked synchronous mode which transfers
data synchronously with the clock. In the asynchronous mode, data
length, parity bits and number of stop bits can be selected, and eight
transfer formats are provided.
The SCI consists of the following registers as shown in Fig. 26
Block Diagram.
Transmit/Receive Control Status Register I (TRCSRJ)
Rate/Mode Control Register (RMCR)
Transmit/Receive Control Status Register 2 (TRCSR2)
Receive Data Register (RDR)
Recevie Shift Register
Transmit Data Register (TDR)
Transmit Shift Register
To operate the SCI, initialize the RMCR and TRCSR2, after
selecting the desirable operating mode and transfer format. Next,
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301YO,HD63A01YO,HD63B01YO
set the enable bit (TE or RE) of the TRCSR 1. Operating mode and
transfer format should be changed when the enable bit (TE, RE) is
cleared. When setting the TE or RE again after changing the ope rat-
P22
~--------------------------------------------~
Figure 26
•
ing mode or transfer format, interval of more than a I-bit cycle of
the baud rate or bit rate is necessary. If a I-bit cycle or more is not
allowed, the SCI block may not be initialized.
SCI Block Diagram
Asynchronous Mode
Asynchronous mode contains 8 transfer formats as shown in
Fig. 27.
Data transmission is enabled by setting TE bit of the TRCSRI,
then port 2, bit 4 will unconditionally become a serial output independently of the corresponding DDR.
To transmit data, set the desirable transmit format with RMCR
and TRCSR2. When the TE bit is set, the data can be transmitted
after transmitting the one frame of preamble (" 1").
The conditions at this stage are as follows.
1) If the TDR is empty (TDRE=l), consecutive I's are produced to indicate the idle state.
2) If the TDR contains data (TDRE=O), data is sent to the
Transmit Shift Register and data transmit starts.
During data transmit, a start bit of "0" is transmitted first. Then
7-bit or 8-bit data (starts from bit 0) is transmitted. With PEN = 1,
the parity bit, even or odd, selected by EOP bit is added, lastly the
stop bit (1 bit or 2 bis) is sent.
When the TDR is "empty", hardware sets TDRE flag bit. If the
CPU doesn't respond to the flag in proper timing (the TDRE is in
set condition till the next normal data transfer starts from the
transmit data register to the transmit sift register), "1" is transferred instead of the start bit "0" and continues to be transferred till
data is provided to the data register. While the TDRE is "1", "0" is
not transferred.
Data receive is possible by setting RE bit. This makes port 2, bit
3 a serial input. The operation mode of data receive is decided by
the contents of the TRCSR2 and RMCR at first, and set RE bit of
TRCSRl. The first "0" (space) synchronizes the receive bit flow.
Each bit of the following data will be strobed in the middle. If a stop
bit is not "1", a framing error assumed and ORFE is set.
When a framing error occurs, receive data is transferred to the
Receive Data Register and the CPU can read the error-generating
data. This makes it possible to detect a line break.
When PEN bit is set, the parity check is done. If the parity bit
does not match the EOP bit, a parity error occurs and the PER bit is
set, not the· RDRF bit. Also, when the parity error occurs the
receive data can be read just like in the case of the framing error.
The RDRF flag is set when the data is received without a framing error and a parity error.
If RDRF is still set when receiving the stop bit of the next data,
ORFE is set to indicate the overrun generation. CPU can get the
receive data by reading RDR. When 7 bit data format is selected,
the 8th bit of RDR is "0".
W~en the CPU read the receive Data Register as a response to
RDRF flag or ORFE flag after having read TRCSR, RDRF or
ORFE is cleared.
(Note) Clock Source in Asynchronous Mode
If CCI:CCO= 10, the internal bit rate clock is provided at P22
regardless of the values for TE or RE. Maximum clock rate is
E+16.
If both eel and eeo are set, an external TTL compatible clock
must be connected to P22 at sixteen times (I6x ) the desired bit
rate, but not greater than E.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
385
H 0630 1YO, H 063A01 YO, H 063BO 1YO
(1) ISTARTI
7Bit Data
(2) I START!
7Bit Data
2 STOP
(3) ISTART!
7Bit Data
! PARITY I STOP!
(4) I STARTI
7Bit Data
!PARITY!
(5)
I START!
BBit Data
(6)
ISTART!
BBit Data
2 STOP
(7)
I
START!
BBit Data
IPARIT3 STOP I
(8)
I STARTI
BBit Data
!PARITyl
Figure 27
•
I STOP I
! STOP I
2 STOP
Asynchronous Mode Transfer Format.
pulse of external are ignored.
When data transmit is selected to the clock output, the MCV
produces transmit data and synchronous clock at TDRE flag clear.
2) Data receive
Data receive is enabled by setting RE bit. Port 2, bit 3 will be a
serial input. The operating mode of data receive is decided by the
TRCSRI and the RMCR.
If the external clock input is selected, 8 external clock pulses and
the synchronized receive data are input to port 2, bit 2 and bit 3
respectively. The MCV put receive data into the receive data shift
register by this clock and set the RDRF flag at the termination of 8
bit data receive. More than 9th clock pulse of external input are
ignored. When RDRF is cleared, the MCV starts receiving the next
data instantly. So, RDRF should be cleared with P22 "High" .
When data receive is selected with the clock output, 8 synchronous clocks are output to the external by setting RE bit. So
receive data should be input from external synchronously with this
clock. When the first byte data is received, the RDRF flag is set.
After the second byte, receive operation is performed by sending
the synchronous clock to the external after clearing the RDRF bit.
Clocked Synchronous Mode
In the clocked synchronous mode, data transmit is synchronized
with the clock pulse. The HD6301 YO SCI provides functionally
independent transmitter and receiver which makes full duplex
operation possible in the asynchronous mode. But in the clocked
synchronous mode an SCI clock 110 pin is only P22 , so the
simultaneous receive and transmit operation is not available. In this
mode, TE and RE should not be in set condition ("1")
simultaneously. Fig. 28 gives a synchronous clock and a data format
in the clocked synchronous mode.
1) Data transmit
Data transmit is realized by setting TE bit in the TRCSRI. Port
2, bit 4 becomes an output unconditionally independent of the
value of the corresponding DDR.
. Both the RMCR and TRCSR should be set in the desirable
operating condition for data transmit.
When an external clock input is selected and the TDRE flag is
"0", data transmit is performed from port 2, bit 4, synchronizing
with 8 clock pulses input from external to port 2, bit 2.
Data is transmitted from bit 0 and the TDRE is set when the
Transmit Shift Register (TSR) is "empty". More than 9th clock
<=====::J1
2 STOP
Transmit Direction
Synchronous
clock
Data
~NotValid
• Transmit data is produced from a falling edge of a synchronous clock to the next falling edge .
• Receive data is latched at the rising edge.
Figure 28
•
Clocked Synchronous Mode Format
Transmit/Receive Control Status Register (TRCSR1)
($0011)
The TRCSRI is composed of8 bits which are all readable. Bits 0
to 4 are also writable. This register is initialized to $20 during reset.
Each bit functions are as follows.
386
Transmit/Receive Control Status Register
7
I I
6
5
432
RDRF ORFEI TDREI RIE I RE I TIE
I
1
0
TE I WU I
$0011
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------HD6301YO,HD63A01YO,HD63B01YO
Bit 0
WU Wake-up
In a typical multi-processor configuration, the software protocol provides the destination address at the first byte of the
message. In order to make uninterested MCU ignore the
remaining message, a wake-up function is available. By this,
uninterested MCU can inhibit all further receive processing till
the next message starts.
Then wake-up function is triggered by consecutive 1's with I
frame length. The software protocol should provide the idle time
between messages.
By setting this bit, the MCU stops data receive till the next
message. The receive of consecutive "1" with one frame length
wakes up and ·clears this bit by hardware and then the MCU
restarts receive operation. However, the RE flag should be
already set before setting this bit. In the clocked synchronous
mode WU is not available, so this bit should not be set.
Bit 1
TE Transmit Enable
When this bit is set, transmit data will appear at port 2, bit 4
after one frame preamble in asynchronous mode, while in
clocked synchronous mode it appears immediately. This is
executed regardless of the value of the corresponding DDR.
When TE is cleared, the serial 110 doesn't affect port 2, bit 4.
Bit 2
TIE Transmit Interrupt Enable
When this bit is set, an internal interrupt (IRQ3) is enabled
when TDRE (bit 5) is set. When cleared, the interrupt is
inhibited.
Bit 3
TORE Transmit Data Register Empty
TDRE is set by hardware when the TDR is transferred to the
Transmit Shift Register in the asynchronous mode, while in
clocked synchronous mode when the TDSR is "empty". This
bit is cleared by reading the TRCSRI or TRCSR2 and writing
new transmit data to the TDR when TDRE= 1. TDRE is set to
"1" during reset.
(Note) TDRE should be cleared in the transmittable state after
the TE set.
Bit 6
RDRF Receive Data Register Full
RDRF is set by hardware when data is received normally and
transferred from the Receive Shift Register (RSR) to the RDR.
This bit is cleared by reading TRCSR I or TRCSR2, and the
RDR, when RDRF = I. This bit is cleared during reset.
•
Bit2
Bit3
Bit4
CCO}
CC1
CC2
Clock Control/Format Select·
These bits control the data format and the clock source (refer to
Table II).
• CCO, CCI and CC2 are cleared during reset and the MCU
goes to the clocked synchronous mode of the external clock
operation. Then the MCU automatically set port 2, bit 2 into
the clock input state. When using port 2, bit 2 as an output
port, the DDR of port 2 should be set to "1" and CCI and
CCO to "0" and" 1" respectively.
Bit 6
Bit 7
Not Used.
Not Used
Transmit/Receive Control Status Register 2 (TRCSR2)
The TRCSR2 is a 7-bit register which can select a data format in
the asynchronous mode. The upper 3 bits are the same address as
the TRCSRI. Therefore, the RDRF, ORFE and TDRE can be read
by either the TRCSRI or TRCSR2. Bits 0 to 2 of the TRCSR2 are
used for read/write. Bits 4 to 7 are used only for read.
Transmit/Receive Control Status Register 2
7
6
5
432
1
0
IRDRFIORFEITDREI PER 1 -.1 PEN 1Eopi 5Bli $001E
ORFE Overrun Framing Error
_. ORFE is set by hardware when an overrun or a framing error
is generated (during data-receive only). An overrun error occurs
when new receive data is ready to be transferred to the RDR
during RDRF still being set. A framing error occurs when a stop
bit is "0". But in clocked synchronous mode, this bit is not
affected. This bit is cleared by reading the TRCSRI or TRCSR2,
and the RDR, when RDRF=l. ORFE is cleared during reset.
Bit 7
Speed Select
These bits control the baud rate used for the SCI. Table 9 lists
the available baud rates. The timer 1 FRC (SS2 =0) and the timer 2
up counter (SS2 = I) provide the internal clock to the SCI. When
selecting the timer 2 as a baud rate clock source, it functions as a
baud rate generator. The timer 2 generates the baud rate listed in
Table 10 depending on the value of the TCONR.
(Note) When operating the SCI with internal clock, do not perform write operation to the timer/counter which is the
clock source of the SCI.
•
RIE Receive Interrupt Enable
When this bit is set, an internal interrupt (IRQ3) is enabled
when RDRF (bit 7) or ORFE (bit 6) is set. When cleared, the
interrupt is inhibited.
Bit 5
SSO}
SS1
SS2
RE Receive Enable
When set, a signal is input to the receiver from port 2, bit 3
regardless of the value of the DDR. When RE is cleared, the
serial 110 doesn't aflfect port 2, bit 3.
Bit 4
BitO
Bit 1
BitS
Transmit Rate/Mode Control Register (RMCR)
The RMCR controls the following serial 110:
· Baud Rate
Data Format
· Clock source
. Port 2, Bit 2 Function
· Operation Mode
All bits are readable/writable. Bit 0 to 5 of the RMCR are cleared
during reset.
Bit 0
SBl Stop Bit length
This bit selects the stop bit length in the asynchronous mode.
If this bit is "0", the stop bit is I-bit. If" 1", the stop bit is 2-bit.
This bit is cleared during reset.
Bit 1
EOP Even/Odd Parity
This bit selects the parity generated and checked when the
PEN is "1". If this bit is "0", the parity is even. If" 1", it is odd.
This bit is cleared during reset.
Bit 2
PEN Parity Enable
This bit decides whether the parity bit should be generated
and checked in the asynchronous mode or not. If this bit is "0",
the parity bit is neither generated nor checked. If "1", it is
generated and checked. This bit is cleared during reset.
The 3 bits above do not affect the SCI opertion in the clocked
synchronous mode.
Bit 3
Not Used
Transfer Rate/Mode Control Register
6
543
2
1
0
I - 1552 1CC21 CC1 ICcol 55115501 $0010
_HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
387
HD6301YO,HD63A01YO,HD63B01YO---------------------Table 9 SCI Bit Times and Transfer Rates
(1) Asynchronous Mode
XTAL
SS2 SSI
0
0
0
0
1
0
1
0
1
-
SSO
0
1
0
1
E
E716
E7128
E-:-l024
E74096
-
-
2.4576MHz
614.4kHz
26;IS/38400Baud
208'IS/4800Baud
1.67ms/600Baud
6.67ms/150Baud
4.0MHz
1.0MHz
16,us/62500Baud
128 1Is/7812.5Baud
1.024ms/976.6Baud
4096ms/244.1 Baud
4.9152MHz
12288MHz
13"s/76800Baud
104.21Is/9600Baud
833.3,us/1200Baud
3.333ms/300Baud
*
*
*
* When SS2 is "I", Timer 2 provides SCI docks.
Baud Rate =
fhe baud rate is shown as follows with the TCONR as N.
f
32'(N+I)
(
f: input clock frequency to the)
timer 2 counter
N = 0 - 255
(2) Clocked Synchronous Mode'
XTAL
SS2 SSI
0
0
0
0
0
0
SSO
0
1
0
E
E72
E716
E7128
E7512
40MHz
1.0MHz
21lS/bit
16,us/bit
128,us/bit
512 11s/bit
6.0MHz
1.5MHz
1.33,us/bit
107,us/bit
85.3,us/bit
341 lIs/bit
8.0MHz
2.0MHz
l,us/bit
8,us/bit
64.u s/bit
256,us/bit
**
**
**
* Bit rates in the case of internal clock operation. In the case of external clock operation, the external clack is
operatable up to DC - 1/2 system clock.
** The bit rate is shown as follows with the TCONR as N.
.
.
4(N+I)
Bit Rate (loiS/bit) = - - f (
f: i~put clock frequency to the)
timer 2 counter
N = 0 - 255
Table 10 Baud Rate and Time Constant Register Example
~L
Baud Rate (Baud
110
150
300
600
1200
2400
4800
9600
19200
38400
2.4576MHz
36864MHz
4.0MHz
4.9152MHz
8.0MHz
21'
127
63
31
15
7
3
1
0
32'
191
95
47
23
11
5
2
35'
207
103
51
25
12
70'
51'
207
103
51
25
12
-
-
43'
255
127
63
31
15
7
3
1
0
-
-
-
• E/8 clock is input to the timer 2 up counter and E clock otherwise.
Table 11
CC2
0
0
0
0
1
1
1
I
CCI
0
0
1
1
0
0
I
1
CCO
Format
0
1
0
I
B-bit data
B-bit data
0
I
0
I
8-bit data
8-bit data
8-bit data
7-bit data
7-bit data
7-bit data
SCI Format and Clock Source Control
Mode
Clocked Synchronous
Clock Source
Port 2, Bit 2
External
Internal
Asynchronous
Asynchronous
Internal
Input
Not Used"
Output'
External
Input
Clocked Synchronous
Asynchronous
Internal
Internal
Output
Not Used"
Asynchronous
Internal
Output'
Asynchronous
External
Input
Asynchronous
Port 2, Bit 3
I
Port 2, Bit 4
When the TRCSR I, RE bit is "1",
bit 3 is used as a serial input.
When the TRCSRI, TE bit is "1",
bit 4 is used as a serial output.
* Clock output regardless of the TRCSRI, bit RE and TE_
** Not used for the SCI.
388
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave, • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301YO,HD63A01YO,HD63B01YO
Bit 4
Bit7
PER Parity Error
BitS
RORF
Receive Data Register Full
This bit is set when the PEN is "1" and a parity error occurs.
It is cleared by reading the RDR after reading the TRCSR2,
when PER = 1.
* Each flag of the TDRE, ORFE, and RDRF can be read from
either the TRCSRI or TRCSR2.
TORE
Transmit Data Register Empty
Bit6
•
ORFE
TIMER, SCI STATUS FLAG
Table 12 shows the set and reset conditions of each status flag in
the timer 1, timer 2 and SCI.
Overrun/Framing Error
Table 12 Timer 1, Timer 2 and SCI Status Flag
Set Condition
P6CSR
Falling edge input to PS4 (is)
ICF
FRC -+ ICR by Rising or Falling edge input to
P20·
(Selecting with the IEDG bit)
2.
RES = 0
OCFl
OCRl = FRC
1.
Read the TCSR 1 or TCSR2 then write to
the OCRl H or OCRl L, when OCFl = 1
2.
RES = 0
1.
Read the TCSR2 then write to the OCR2H
or OCR2L, when OCF2 = 1
2.
RES = 0
1.
Read the TCSR 1 then FRCH, when
TOF = 1
Timer
1
OCF2
TOF
Timer
2
OCR2 = FRC
FRC = $FFFF + 1 cycle
1.
Read the P6CSRthen read or write the
PORT6, when IS FLAG = 1
2.
RES = 0
1.
Read the TCSR 1 or TCSR2 then ICRH,
when ICF = 1
2.
RES = 0
1.
Write "0" to CMF, when CMF = 1
2.
RES
1.
Read the TRCSAl or TRCSR2 then RDA,
when RDRF = 1
CMF
T2CNT = TCONR
RDRF
Receive Shift Register -+ RDR
2.
RES = 0
ORFE
1.
Framing Error (Asynchronous Mode)
Stop Bit = 0
1.
Read the TRCSAl or TRCSR2 then RDA, when
ORFE = 1
2.
Overrun Error (Asynchronous Mode)
Receive Shift Register -+ RDR when
RDRF = 1
2.
RES = 0
1.
Asynchronous Mode
TOR -+ Transmit Shift Register
Read the TRCSRl or TRCSR2 then write to the
2.
Clocked Synchronous Mode
Transmit Shift Register is "empty"
3.
RES = 0
SCI
TORE
PER
(Note) -
Clear Condition
IS FLAG
; Transfer
= ; equal
Parity when PEN = 1
ICRH; Upper byte of ICR
OCR 1H; Upper byte of OCR 1
OCR2H; Upper byte of OCR2
=0
TOR, when TORE = 1
Note)
1.
2.
TORE should be reset after the TE set.
Read the TRCSR2 then RDR, when PER = 1
RES=O
OCR1 L; Lower byte of OCR1
OCR2L; Lower byte of OCR2
FRCH; Upper byte of FRC
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
389
HD6301YO,HD63A01YO,HD63B01YO---------------------•
LOW POWER DISSIPATION MODE
This sleep mode is effective to reduce the power dissipation for a
system with no need of the HD6301YO's consecutive operation.
The HD6301YO provides two low power dissipation modes;
sleep and standby.
•
• Standby Mode
The MCV goes to the standby mode with the STBY "Low" or
Sleep Mode
The Meu goes to the sleep mode by SLP instruction execution.
In the sleep mode, the CPU stops its operation, while the registers'
contents are retained. In this mode, the peripherals except the CPU
such as timers, SCI, etc. continue their functions. The power dissipation of sleep-condition is one fifth that of operating condition.
The MeU returns from this mode by an interrupt, RES or
STBY; it goes to the reset state by RES and the standby mode by
STBY. When the CPU acknowledges an interrupt request, it cancels
the sleep mode, returns to the operation mode and branches to the
interrupt routine. When the CPU masks this interrupt, it cancels
the sleep mode and executes the next instruction. However, for
example, if the timer 1 or 2 prohibits a timer interrupt, the CPU
doesn't cancel the sleep mode because of no interrupt request.
by clearing the STBY flag. In this mode, the HD6301 YO stops all
the clocks and goes to the reset state. In this mode, the power dissipation is reduced to several /LA. During standby, all pins, except
the power supply (Vee, Vss ), the STBY, RES and XTAL (which
outputs "0"), go to the high impedance state. In this mode, power
(Vee) is supplied to the HD6301 YO, and the contents of RAM is
retained. The MCV returns from this mode during reset. When the
MCV goes to the standby mode with STBY "Low", it wi\l restart at
the timing shown in Fig. 29(a). When the MCV goes to the standby
mode by clearing the STBY flag, it wi\l restart only by keeping the
RES "Low" for longer than the oscillating stabilization time.
(Fig. 29(b»
Vee
HD6301YO
I
------!I
r-:~:
---Holl.
fWU-11111
:
I
I
I~:IIIII- - - - - i f
I
I
:
I· IIVss
Vss
Standby Mode
o Save Registers
o RAM/Port 5 Control Re\lister Set
I
-,..
.,
o ~::~Iatorl
Time
r---.
Restart
(a) Standby Mode by STBY
Vee
HD6301YO
•'.
'~
I
Vss
I
I
I
I
OSTBY
Clear
I
I
I
I
I
I
I
I
I
I
III'..
Standby Mode
FLAG
!
.,1
i
o Oscillator:
Start
Time
~
: Restart
Vss
(b) Standby Mode by the STBY Flag
Figure 29. Standby Mode Timing
390
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------'--------------HD6301YO,HD63A01YO,HD63B01YO
•
F,
TRAP FUNCTION
The CPU generates an interrupt with the highest priority
(TRAP) when fetching an undefined instruction or an instruction
from non-memory space. The TRAP prevents the system-burst
caused by noise or a program error.
•
Op Code Error
When fetching an undefined op code, the CPU saves registers as
well as a normal interrupt and branches to the TRAP ($FFEE,
$FFEF). This has the priority next to reset.
..
0:U 7
8
1,5
01
Inde-Regllter (XI
1,5
,
11
-
-
-
-
-
0 -
-
-
Table 13 Addresses Applicable to Address Errors
1
2
3
$0000
$0000
$0000
I
I
I
$0027
$0027
$003F
Mode
Address
$0140
I
$BFFF
- -
-
-
-
SP
1,5
PC
7
Address Error
When an instruction fetch is made excluding internal ROM,
RAM and external memory area, the MeU generates an interrupt
as well as an op code error. But on the system with no memory in its
external memory area, this function is not applicable if an instruction fetch is made from the external non-memory area. Table 13
pfOvides addresses where an address error occurs to each mode.
This function is available only for an instruction fetch and is not
applicable to the access of normal data read/write.
8·8" Aceumula,.... A and 8
Or 16-811 Double Accumulator 0
-
Figure 30
•
01
Stack Po,nt., (SP)
01
Progr.m Counter (PCI
0
H
•
3
~
15- -
I
N Z
V C
Condition Code
A~'II" leeR)
C.,,,/BoHOW 'rom MSB
Ovefflow
Z.ro
N.I' .....
Interrupt
Half CArry IF rom 811 31
CPU Programming Model
CPU Addressfng Mode
The HD6301 YO provides 7 addressing modes. The addressing
mode is determined by an instruction type and code. Tables 14
through 18 show addressing modes of each instrution with the
execution times counted by the machine cycle.
When the clock frequency is 4MHz, the machine cycle time
becomes microseconds directly.
Accumulator (ACCX) Addressing
Only an accumulator is addressed and the accumulator A or B is
selected. This is a one-byte instruction.
Immediate Addressing
This addressing locates a data in the second byte of an instruction. However, LDS and LDX locate a data in the second and third
byte exceptionally. This addressing is a 2 or 3-byte instruction.
Direct Addressing
(Note)
The TRAP interrupt provides a retry function differently
from other interrupts. This is a program flow return to the
address where the TRAP occurs when a sequence returns
to a main routine from the TRAP interrupt routine by
RTI. The retry can prevent the system burst caused by
noise, etc.
However, if another TRAP occurs, the program repeats
the TRAP interrupt forever, so the consideration is
necessary in programming.
In this addressing mode, the second byte of an instruction shows
the address where 'a data is stored. 256 bytes ($0 through $255) can
be addressed directly. Execution times can be reduced by storing
data in this area so it is recommended to make it RAM for users'
data area in configurating a system. This is a 2-byte instruction,
while 3 byte with regard to AIM, OIM, ElM and TIM.
Extended Addressing
In this mode, the second byte shows the upper 8 bit of the data
stored address and the third byte the lower 8 bit. This indicates the
absolute address of 3 byte instruction in the memory.
Indexed Addressing
•
INSTRUCTION SET
The HD6301YO provides object code upward compatible with
the HD6801 to utilize all instruction set of the HMCS6800. It also
reduces the execution times of key instructions for throughput
improvement.
Bit manipulation instruction, change instruction of the index
register and accumulator and sleep instruction are also added.
The followings are explained here.
CPU Programming Model (refer to Fig. 30)
Addressing Mode
Accumulator and Memory Manipulation Instruction (refer to
Table 14)
New Instruction
Index Register and Stack Manipulation Instruction (refer to
Table 15)
Jump and Branch Instruction (refer to Table 16)
Condition Code Register Manipulation (refer to Table 17)
Op Code Map (refer to Table 18)
•
Programming Model
Fig. 30 depicts the HD6301 YO programming model. The double
accumulator D consists of accumulator A and B, so when using the
accumulator D, the contents of A and B are destroyed.
The second byte of an instruction and the lower 8 bit of the
index register are added in this mode. As for AIM, OIM, ElM and
TIM, the third byte of an instruction and the lower 8 bits of the
index register are added.
This carry is added to the upper 8 bit of the index register and
the result is used for addressing the memory. The modified address
is retained in the temporary address register, so the contents of the
index register doesn't change. This is a 2-byte instruction except
AIM, OIM, ElM and TIM (3-byte instruction).
Implied Addressing
An instruction itself specifies the address. This is, the instruction
addresses a stack pointer, index register, etc. This is a one-byte
instruction.
Relative Addressing
The second byte of an instruction and the lower 8 bits of the
program counter are added. The carry or borrow is added to the
upper 8 bit. So addressing from -126 to + 129 byte of the current
instruction is enabled. This is a 2-byte instruction.
(Note) CLI, SEI Instructions and Interrupt Operation
When accepting the IRQ at a preset timing with the
eLi and SEI instructions, more than 2 cycles are necessary between the eLi and SEt instructions. For examole, the following program (a) (b) don't accept the IRQ
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
391
HD6301YO,HD63A01YO,HD63B01YO---------------------but (c) accepts it.
eLI
eLI
eLI
SEI
NOP
SEI
NOP
NOP
SEI
(a)
(b)
(c)
The same thing can be said to the TAP instruction instead
of the eLI and SEI instructions.
392
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301YO,HD63A01YO,HD63B01YO
Table 14 Accumulator, Memory Manipulation Instructions
Condition Cod~
Addressing Modes
Operations
Mnemonic
IMMED
DIRECT
OP
-
#
OP
ADDA
BB
2
2
ADDB
CB
2
2
Add Double
ADDD
C3
Add Accumulators
ABA
Add
Add With Carry
ADCA
Register
EXTEND
INDEX
-
#
OP
9B
3
2
AB
4
2
BB
4
3
A+M- A
DB
3
2
EB
4
2
FB
4
3
B+M-B
3 3 03 4
2
E3
5
2
F3
5
3
-
#
OP /-
#
OP
2
2
99
3
-
#
A
lB
89
Boolean/
Arithmetic Operation
IMPLIED
1
1
B+M
2
A9
4
2
B9
3
A+M+C-A
4
2
F9
4
3
B+M+C-B
4
2
B4
4
3
A·M-A
ADCB
C9
2
2
09
3
2
AND
ANDA
B4
2
2
94
3
2
A4
ANDB
C4
2
2
04
3
2
E4
4
2
F4
4
3
B·M- B
Bit Test
BITA
85
2
2
95
3
2
A5
4
2
B5
4
3
A·M
BIT B
C5
2
2
05
3
2
E5
4
2
F5
4
3
Clear
CLR
6F
5
2
7F
5 3
Compare
Compare
Accumulators
Complement, l's
B·M
00- M
CLRA
4F
1
1
00 - A
CLRB
5F
1
1
00 - B
CMPA
81
2
2
91
3
2
Al
4
2
Bl
4
3
A-M
CMPB
Cl
2
2
01
3
2
El
4
2
Fl
4
3
B-M
11
1
COMA
43
1 1 A -A
COMB
53
1
CBA
COM
63
6
2
73
1
B -B
OO-M-M
NEG
(Negatel
NEGA
NEGB
40
1
1 OO-A-A
50
1
1 oo-B-B
Decimal Adjust. A
DAA
19
2 1 characters ,ntO BCD format
Decrement
DEC
Exclusive OR
Increment
6A
6
6
2
2
7A
6
A-B
M-M
3
6
3
Converts binary add of BCD
DECA
4A
1
1
A-I - A
DECB
5A
1
1
B-l-B
88
2
2
98
3
2
A8
4
2
BB
4
3
AC!> M-A
EORB
C8
2
2
08
3
2
E8
4
2
F8
4
3
B C!> M- B
6C
6
2
7C
6
3
M+l-M
INCA
4C
1 1
A +1 - A
INCB
5C
1
1
B + 1- B
LDAA
86
2
2
96
3
2
A6
4
2
B6
4
3
M-A
LDAB
C6
2
2
06
3
2
E6
4
2
F6
4
3
M -B
Load Double
Accumulator
LDD
CC
3
3
DC 4
2
EC
5
2
FC
5
3
M + 1 - B. M - A
Multiply Unsigned
MUL
Load
Accumulator
OR, Inclusive
Push Deta
Pull Data
Rotete Left
3D
ORAA
8A
2
2
9A
3
2
AA 4
2
BA 4
3
A+M- A
CA
2
2
DA 3
2
EA 4
2
FA
4
3
B +M- B
PSHA
36
PSHB
37
PULA
32
PULB
33
3 1 SP + 1 - SP, MoP - A
3 1 SP + 1 - SP, MoP - B
49
1
1
1
1
ROL
69
6
2
79
6
59
ROLB
ROR
66
6
2
76
6
4
4
1
A - MoP, SP - 1 - SP
1
B - Msp. SP - 1 - SP
3
ROLA
Rotete Rillht
7 1 AxB-A:B
ORAB
3
RORA
46
1
1
RORB
56
1
1
(Note) Condition Code Register wi)) be explained in Note of Table 17
:j~111111
B
C b7
:jb
B
C
3
2
N Z
1
0
V C
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
:
I
I
I
I
I
I
I
I
I
I
R
I
I
R
I
I
R
R
I
I
R
S R R
R
S R R
R
S R R
I
I
I
I
I
I
I
I
I
I
I
I
I
I
R
S
I
R
S
I
I
R
S
I
I
(j)~
I
I
(j)~
I
I
(j)~
I
I
I ~
I
EORA
INC
I
I
@ •
I I @ •
I I @ •
M -1-M
3
H
·
·
· ··
··
··· ··· ···
·· ·· ·
··· ···
·· ··
··· ···
·· ··
·· ··
·· ··
·· ·· ·
·· ·· .·.
··· ··· ·.
·· ·· ··
·· ·· · · ·
··· ··· ·· ·· ·· ···
·· ·· ·· ·· ·· ··
··· ···
iJ · ·
·· ··
COI'npiement,2's
60
70
6
1
4
M+l-A:B
A +B- A
4
E9
5
,IJ
be
I1III11
b7
be
I
I
I
I
I
R
I
I
~
I
I
I
I
~
R
~
I
I
R
I
I
R
I
I
R
I
I
R
I
I
R
I
I
I
Zero
BGT
2E
3
2
Z + IN
Branch If Higher
BHI
22
3 2
< Zero
BlE
2F
3
2
Z + IN
BlS
23
3
2
C+Z =1
BlT
20
3
2
N
BMI
2B
3
2
N = 1
Branch If Not Equal
Zero
BNE
26
3
2
Z=O
Branch If Overflow
Cle.,
BVC
2B
3
2
V-O
Branch If Overflow Set
BVS
29
3
2
V = 1
Branch If Plus
BPl
2A
3
2
N=O
Branch To Subroutine
BSR
BO
5 2
Jump
JMP
Jump To Subroutine
JSR
No Operation
NOP
Branch If
Branch If
Branch If lower Or
Seme
Branch If
< Zero
Branch If Minus
V ~ 0
<±l
VI = 0
C+Z=O
6E
90
5
2
3
2
7E
3
3
AD 5
2
BD 6
3
01
1 1
Return From Interrupt
RT!
3B 10 1
Aetum From
Subroutine
RTS
39
5 1
Software Interrupt
SWI
3F
12 1
Weit for Interrupt"
WAI
SLP
3E
1
Sleep.
<±l
9
lA 4
-
<±l
<±l
VI = 1
V = 1
Advances Prog. Cntr.
Only
1
5
4
3
H
I
N Z
2
1 0
V
C
·· ·· ·· ·· ·· ··
··· ··· ··· ··· ··· ···
·· ·· ·· ·· ·· ··
··· ··· ··· ··· ··· ···
·· ·· ·· ·· ·· ··
·· · ·· ·
··· ··· ··· ··· ··· ···
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
···• ·• ··• ···• •··· •···
--00 - S
.J; •
{Notel • WAI puts R/W high; Address Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of Table 17.
396
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301YO,HD63A01YO,HD63B01YO
Table 17 Condition Code Register Manipulation Instructions
iAddressingMode!
Oper.tions
-
OP
CI ••r terry
CLC
CI•• r Int.rrupt M.sk
Clnr Overflow
CLI
CLV
SEC
Set terry
Set Int.rrupt Mesk
Set Overflow
Accumul.tor A- CCR
eCR - Accumul.tor A
Condition Code Register
IMPLIED
Mnemonic
,
,
,
,
,
,
,
00
SEI
SEV
TAP
TPA
#
1
OC
OE
OA
OF
08
06
07
Boolean Operation
,
O-C
0-1
1
O-V
l-C
, -I
,
1-V
A- CCR
1
,
,
1
,
3
2
1
0
I
N
Z
V
C
R
A
R
S
S
S
---@ - - -
CONDITION CODE SYMBOLS
OP
Operation Code (Hexadecimal)
Number of MCU Cycles
Msp Contents of memory location pointed by Stack Pointer
#
Number of Program Bytes
+
Arithmetic Plus
Arithmetic Minus
•
Boolean AND
+ Boolean Inclusive OR
~.
Boolean Exclusive OR
M Complement of M
Transfer into
OBit = Zero
00 Byte = Zero
(Note)
4
H
·· · ·· ·· ·· ·
·· ·· ·· ·· · ·
·· · ·· ·· · ··
······
CCR - A
LEGEND
5
H
I
N
Z
V
C
R
S
Half-carry from bit 3 to bit 4
Interrupt mask
Negative (sign bit)
Zero (byte)
Overflow, 2's co,)"plement
Carry/Borrow from/to bit 7
Reset Always
Set Always
Set if true after test or clear
Not Affected
t
Condition Code Register Notes: (Bit set if test is true and cleared otherwise)
CD
(Bit V)
Test: Result = 10000000?
@
@
@
(Bit C)
Test: Result \ 00000000?
(Bit C)
Test: BCD Character of high-order byte greater than 10?
(Bit V)
Test: Operand = 10000000 prior to execution?
(Not cleared if previously set)
®
®
(Bit V)
Test: Operand = 01111111 prior to execution?
(Bit V)
Test: Set equal to N~ C = 1 after the execution of instructions
(j)
(Bit N)
Test: Result less than zero? (Bit 15=1)
®
®
(All Bit)
Load Condition Code Register from Stack.
(Bit I)
Set when interrupt occurs. If previously set, a Non·Maskable Interrupt is required to exit the wait state.
@;
(All Bit)
Set according to the contents of Accumulator A_
®
(Bit C)
Result of Multiplication Bit 7=1? (ACCB)
Table 18 OP-Code Map
OP
ACC
ACC
CODE
A
B
~o _______
0000
LO
0001
0010
0011
0100
0101
4
5
0
1
SBA
2
BRA
3
TSX
1
NOP
CBA
BAN
INS
2
3
4
~ ~
~ ~
BHl
PULA
BLS
PULB
LSAD
~
BCC
DES
0101
5
ASLO
~
BCS
TXS
OliO
6
7
TAP
TAB
TPA
TBA
BNE
BEO
PSHA
0111
1000
0000
0001
0010
0011
0100
PSHB
8
INX
XGOX BVC
PULX
1001
9
DEX
OAA
BVS
ATS
1010
A
CLV
SLP
BPL
ABX
lOll
B
SEV
ABA
BMI
ATI
1100
e
CLC
~
BGE
PSHX
~
~
~
BLT
MUL
BGT
WAI
BLE
SWI
2
3
1101
0
1110
E
SEC
CLI
1111
F
SEI
0
1
lINOEFltiED OP CODE
--------
IND
OliO
~
01 II
1000
7
8
6
J
I
IMM lOlA liND
9
I
A
1100
B
G
I 1101 I
I o I
1110
E
I EXT
I 1111
I F
SUB
0
AIM
CMP
OIM
SBC
1
2
ADDD
SUBD
LSA
AND
ElM
BIT
AOA
~l
ASL
...-------1
STA
3
4
5
LOA
ASA
STA
EOA
6
7
8
AOL
AOC
9
DEC
ORA
A
TIM
ADD
B
CPX
INC
TST
BSA
1
...--------1
7
8
I
~
STS
9
j
STO
LOX
LOS
~l
6
LOO
JSR
JMP
CLR
5
1 1001
COM
----
ACCB or X
1 EXT
1 1010 1 lOll
IMM lOlA liND
NEG
~~
4
ACCA or SP
DIA
A
j
B
C
STX
1 ,:>_1 ._~._.LF .-
C
0
E
F
---
c;;;;:::::::J
• Only each instructions of AIM, OIM, ElM, TIM
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
397
HD6301YO,HD63A01YO,HD63B01YO---------------------•
•
and port states.
CPU OPERATION
CPU Instruction Flow
When operating, the CPU fetches an instrution from a memory
and executes the required function. This sequence starts with RES
cancel and repeats itself limitlessly if not affected by a special
instruction or a control signal. SWI, RTI, WAI and SLP instructions
change this operation, while NMI, ~ IRQ;, IRQ3, HALT and
STBY control it. Fig. 31 gives the CPU mode transition and Fig. 32
the CPU system flow chart. Table 19 shows CPU operating states
Figure 31
• Operation at Each Instruction Cycle
Table 20 shows the operation at each instruction cycle. By the
pipeline control of the HD6301YO, MULT, PUL, DAA and XODX
instructions, etc. prefetch the next instruction. So attention is
necessary to the counting of the instruction cycles because it is
different from the usual one-from op code fetch to the next
instruction op code.
CPU Operation Mode Transition
Table 19 CPU Operation State and Port State
Port
Port 1
(AOtoA7)
Mode
Reset
Mode 1, 2
H
Mode 3
T
Mode 1,2
Port 2
Mode 3
Mode 1,2
Port 3
(DO to 07)
Mode 3
Mode 1
Port 4
(AB to A15)
Mode 2
Mode 3
Mode 1, 2
Port 5
Mode 3
Mode 1, 2
Port 6
Mode 3
STBy····
T
T
T
T
H
Mode 3
T
T
T
T
T
T
Mode 1, 2
Port7
T
T
T
H; High, L; Low, T; High Impedance
Keep;
The output port is retained. and the input port goes to the high impedance state.
=
• RD, WR, R/w' LlR
H. BA
RD, WR, R/IN T, LlR, BA
=
=L
=H
HALT···
---------------------T
Keep
T
T
Keep
Keep
..
Sleep
H
Keep
Keep
T
Keep
H
.....
Keep
Keep
Keep
Keep
HALT is unacceptable in mode 3.
E pin goes to high impedance state.
Address output pin
H
Input port = T
=
398
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
I
s:
(')
2:
»
3
I
FFFE.FFFF
I
STACK
~
Cr
I»
!:
~
•
(Note)
I\)
~
0
0
i}
1. The program sequence will come to the RES start from
any place of the flow during RES. When STBY=O, the
sequence will go into the standby mode regardless of the CPU
condition.
2. Refer to "FUNCTIONAL PIN DESCRIPTION" for more
details of interrupts.
~~
~:I
.CD
-~
• l>
CJ)(')
~ :I
c:...0
en
SD
()
»
CO
C1l
:::I:
~
o
m
w
•
o......
p-<
~
0
~
IN
:::r:
o
w
~
W
m
C1l
»
CD
w
o......
-<
0
0
P
:::I:
o
m
w
Figure 32
W
-0
-0
HD6301 YO System Flow Chart
to
o......
o-<
Table 20
Address Mode 8&
Instructions
Cycle-by-Cycle Operation
Data Bus
Address Bus
IMMEDIATE
ADC
AND
CMP
LOA
SBC
AD DO
LDD
LOX
DIRECT
ADC
AND
CMP
LOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
CPX
LOS
SUBD
ADD
BIT
EOR
ORA
SUB
CPX
LOS
SUBD
Op Code Address + 1
Op Code Address + 2
1
1
0
0
1
1
1
2
3
Op Code Address+ 1
Op Code Address+2
Op Code Address+3
1
1
1
0
0
0
1
1
1
1
2
3
Op Code Address+ 1
Address of Operand
Op Code Address+2
1
1
1
0
0
0
1
1
1
1
2
3
1
2
3
Op Code Address+ 1
Destination Address
Op Code Address+2
Op Code Address + 1
Address of Operand
Address of Operand + 1
Op Code Address+2
Op Code Address+ 1
Destination Address
Destination Address+ 1
Op Code Address+2
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address+ 1
Op Code Address+2
Address of Operand
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
Op Code Address+3
3
3
4
4
STD
STX
STS
4
1
2
3
4
JSR
5
1
2
3
4
5
TIM
4
1
2
3
4
AIM
DIM
1
0
Operand Data
Next Op Code
2
3
ADDD
LDD
LOX
1
2
ElM
6
1
2
3
4
5
6
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
1.
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
1
0
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Address of Operand (LSB)
Operand Data
Next Op Code
Destination Address
Accumulator Data
Next O'p Code
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
(Continued)
400
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------HD6301YO,HD63A01YO,HD63B01YO
Address Mode &
Instructions
Address Bus
INDEXED
JMP
3
ADC
AND
CMP
LOA
SBC
TST
STA
ADD
BIT
EOR
ORA
SUB
4
4
ADDD
CPX
LOS
SUBD
LDD
LOX
5
1
2
3
1
2
3
4
Op Code Address + 1
FFFF
Jump Address
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address+2
1
1
1
1
1
1
1
0
1
2
3
4
1
2
3
4
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address+2
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset+ 1
Op Code Address+2
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address+2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
IX + Offset
Op Code Address + 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address + 2
Op Code Address + 1
Op Code Address + 2
FFFF
IX + Offset
Op Code Address + 3
Op Code Address + 1
FFFF
IX + Offset
IX + Offset
Op Code Address + 2
Op Code Address + 1
Op Code Address + 2
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address + 3
1
1
0
5
STD
STX
STS
5
1
2
3
4
5
JSR
5
1
2
3
4
5
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
1
2
3
4
5
6
TIM
5
1
2
3
4
5
CLR
5
AIM
OIM
1
2
3
4
5
1
ElM
7
Data Bus
2
3
4
5
6
7
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
i
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
1
0
0
0
1
0
0
0
1
0
1
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
0
Offset
Restart Address (LSB)
First Op Code of Jump Routine
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operlilnd Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
NextOp Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data
00
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
401
HD6301YO,HD63A01YO,HD63B01YO----------------------Address Mode &
Instructions
Address Bus
EXTEND
JMP
3
ADC
AND
CMP
LOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
TST
4
1
2
3
1
2
3
4
4
1
2
3
4
ADDD
CPX
LOS
SUBD
STD
STX
LDD
LOX
5
1
2
3
4
5
STS
5
1
2
3
4
5
JSR
6
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
CLR
5
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
Data Bus
Op Code Address + 1
Op Code Address+2
Jump Address
Op Code Address+ 1
Op Code Address + 2
Address of Operand
Op Code Address+3
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
Jump Address (MSB)
Jump Address (LSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Next Op Code
Op Code Address+ 1
Op Code Address+2
Destination Address
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Address of Operand
Address of Operand + 1
Op Code Address+3
Op Code Address+ 1
Op Code Address + 2
Destination Address
Destination Address + 1
Op Code Address+3
Op Code Address + 1
Op Code Address + 2
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
qP Code Address+ 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand
Op Code Address + 3
1
1
0
1
1
1
1
1
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0
1
0
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
Destination Address (MSB)
Destination Address (LSB)
Accumulator Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (MSB)
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
00
Next Op Code
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
0
1
(Continued)
402
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301YO,HD63A01YO,HD63B01YO
Address Mode &
Instructions
IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
PULA
ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
LSR
ROL
NOP
SEC
SEV
TAP
TPA
TSX
XGDX
Address Bus
1
Op Code Address+ 1
1
0
1
0
Next Op Code
1
2
1
2
Op Code Address+ 1
FFFF
Op Code Address+ 1
FFFF
Stack Pointer + 1
Op Code Address + 1
FFFF
Stack Pointer
Op Code Address + 1
Op Code Address+ 1
FFFF
Stack Pointer+ 1
Stack Pointer+2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-1
Op Code Address+ 1
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Return Address
Op Code Address + 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
Next Op Code
Restart Address (LSB)
Next Op Code
Restart Address (LSB)
Data from Stack
Next Op Code
Restart Address (LSB)
Accumulator Data
Next Op Code
Next Op Code
Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSB)
Next Op Code
Restart Address (LSB)
Index Register (LSB)
Index Register (MSB)
Next Op Code
Next Op Code
Restart Address (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
1
2
PULB
3
3
PSHA
Data Bus
PSHB
4
PULX
4
1
2
3
4
1
2
3
4
1
2
PSHX
5
3
4
5
1
2
RTS
5
3
4
5
1
2
MUL
7
3
4
5
6
7
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
0
0
1
0
0
0
1
1
1
0
0
1
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
403
HD6301YO,HD63A01YO,HD63B01YO----------,-------------Address Mode &
Instructions
Address Bus
IMPLIED
WAI
9
1
2
3
4
5
6
7
8
9
RTI
10
1
2
3
4
5
6
7
8
9
SWI
12
10
1
2
3
4
5
6
7
8
9
10
11
12
1
2
SLP
4
I
BCS
BGE
BHI
BLS
BMT
BPl
BRN
BVS
3
404
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
j
j
j
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (LSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (LSB)
Return Address (MSB)
Return Address (LSB)
First OpCode of Return Routine
Next Op Code
Restart Address (LSB)
Return Address (lSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (LSB)
First Op Code of SWI Routine
Next Op Code
Restart Address (lSB)
3
4
FFFF
Op Code Address+ 1
1
1
1
0
1
1
1
0
Restart Address (lSB)
Next Op Code
1
2
Op Code Address + 1
FFFF
1Branch Address·· .. ··Test=·'1"
Op Code Address +1.. ·Test="O"
1
1
0
1
1
1
1
1
1
0
1
0
Branch Offset
Restart Address (lSB)
First Op Code of Branch Routine
Next Op Code
1
1
0
0
1
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
3
5
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer-5
Stack Pointer - 6
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer+4
Stack Pointer + 5
Stack Pointer + 6
Stack Pointer + 7
Return Address
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer-3
Stack Pointer-4
Stack Pointer - 5
Stack Pointer-6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address+ 1
FFFF
Sleep
1
RELATIVE
BCC
BEQ
BGT
BLE
BlT
BNE
BRA
BVC
BSR
Data Bus
1
2
3
4
5
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Branch Address
Offset
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
First Op Code of Subroutine
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6301YO,HD63A01YO,HD63B01YO
•
r
PRECAUTION TO THE BOARD DESIGN OF OSCILLATION
CIRCUIT
As shown in Fig. 33, there is a case that the cross talk disturbs the normal oscillation if signal lines are put near the oscillation circuit. When designing a board, pay attention to this.
Crystal and C L must be put as near the HD6301 YO as possible.
20mm
max---1
HD6301YO
HD6301YO
Do not use this kind of print board design
Figure 33
Precaution to the boad design
of oscillation circuit
(Top view)
Example of Oscillation Circuits in Board Design
Figure 34
• RECEIVE MARGIN OF THE SCI
Receive margin of the SCI contained in the HD6301 YO
is shown in Table 21.
Note: SCI = Serial Communication Interface.
Table 21
Bit distortion tolerance
(t-to) Ito
Character distortion tolerance
(T - Tol ITo
±43.7%
±4.37%
6
4
START
Ideal Waveform
Bit length
r
to
8
STOP
--1
I""'.>-----------Character length To - - - - - - - - - - - . j
Real Waveform
f + - - - - -_ _
T_~t~
_ _
_____+i.1
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
405
HD6303R,HD63A03R,---HD63B03R
CMOS MPU (Micro Processing Unit)
The HD6303R is an 8-bit CMOS micro processing unit
which has the completely compatible instruction set with the
HD630lVl. 128 bytes RAM, Serial Communication Interface
(SCI), parallel I/O ports and multi function timer are incorpora·
ted in the HD6303R. It is bus compatible with HMCS6800 and
can be expanded up to 65k bytes. Like the HMCS6800 family,
I/O level is TTL compatible with +5.0V single power supply.
As the HD6303R is CMOS MPU, power dissipation is extremely
low. And also HD6303R has Sleep Mode and Stand·by Mode
as lower power dissipation mode. Therefore, flexible low power
consumption application is possible.
•
•
•
•
•
•
•
•
•
•
•
FEATURES
Object Code Upward Compatible with the HD6800, HD6801,
HD6802
Multiplexed Bus (Do/Ao-D7/A7As-A,s)' Non Multiplexed
Bus (00-D 7 , Ao-A,s)
Abundant On·Chip Functions Compatible with the
HD6301Vl; 128 Bytes RAM, 13 Parallel I/O Lines, 16-bit
Timer, Serial Communication Interface (SCI)
Low Power Consumption Mode; Sleep Mode, Stand· By Mode
Minimum Instruction Execution Time
lJ.ls (f=lMHz), 0.67/-Ls (f=1.5MHz), 0.5/-Ls (f=2.0MHz)
Bit Manipulation, Bit Test Instruction
Error Detecting Function; Address Trap, Op Code Trap
Up to 65k Bytes Address Space
Wide Operation Range
Vcc =3t06V (f=0.1-0.5MHz)
f = 0.1 to 2.0 MHz (V cc = 5V ± 10%)
HD6303RP, HD63A03RP,
HD63B03RP
(DP-40)
HD6303RF, HD63A03RF,
HD63B03RF
(FP-54)
H D6303RCG, H D63A03RCG,
HD63B03RCG
TYPE OF PRODUCTS
Bus Timing
Type No.
HD6303R
HD63A03R
HD63B03R
1.0 MHz
1.6 MHz
2.0 MHz
(CG-40)
406
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6303R,HD63A03R,HD63B03R
• PIN ARRANGEMENT
•
•
HD6303RP, HD63A03RP,
HD63B03RP
o
HD6303RF, HD63A03RF,
HD63B03RF
•
AS
HD6303RCG, HD63A03RCG,
HD63B03RCG
L~J L;J L8J ~BJ ~~J ~~ L~J L~J ~~J ~~J
Rm
D,/A, f~
00/.0. 0
O,/A,
0,1"',
m
0,1"',
S1"BY
Dc/A ..
Os/As
0,/.0.,
0,/.0..
0,1.0.,
A.
!J
3J
•
A,.
[~O A,/P17
[I.? A./P,.
D:8 As/P,s
[17 A./p,.
NMI
n
IRQ,
~J
[1~
A,.
~.oi r~l r~1
fo.l i~l r=~ r~j rf?l r:!i r~1
A"
I~ I~ f
rf: cf .f f- ~ ~ ~
~
en
(Top View)
(Top View)
[2~
[~1 Vee
Vss
EXTAl ~J
~--------------~
A'3
t2_2 A,s
XTAL
Vee
A"
~~
r-
Dc/A ..
0.1.0..
fis
"--
0,1.0.,
0,/.0.,
A3/P13
< .;,
(Top View)
BLOCK DIAGRAM
..J
..Je:(
~~~~ 1~10l~
»xwwz~la:
.......---+-1---
P20
h+--.-....I--- P21
~-+-~~- P 22
Address/
~-+--+-4
Data
Buffers
___- P23
P2•
k - - - - _ P1o /Ao
k----_Pll/A 1
t - - - - - P12/A2
....- - - - P13/A3
k - - - - - Pl./A.
PIS/As
t - - - - - PIs/As
P17 /A7
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
407
• ABSOLUTE MAXIMUM RATINGS
Input Voltage
Operating Temperature
Storage Temperature
(NOTE)
Value
Symbol
Item
Supply Voltage
Unit
Vee
V in
-0.3 -+7.0
V
-0.3 -
Topr
T sts
0- +70
V
°c
-55 -+150
°c
Vee+0.3
This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection
circuits. To assure the normal oPeration, we recommend Yin, V out : VSS ;:a;; (V in or V out ) ;:a;; Vee.
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee
= 5.0V±10%, Vss = OV, Ta = O-+70°C, unless otherwise noted.)
Item
Symbol
Test Condition
min
typ
max
Unit
Vee
+0.3
V
Input "Low" Voltage
All Inputs
V 1L
-0.3
-
0.8
V
Input Leakage Current
NMI, IRQ!, RES, STBY
Il in I
V in =0.5-Vee -0.5V
-
-
1.0
iJ,A
Three State (off'state)
Leakage Current
Do-D 7 ,A s -A!5
IITsl1
V in =0.5-Vee -0.5V
-
-
1.0
iJ,A
Output "High" Voltage
All Outputs
V OH
2.4
-
-
V
Vee- O.7
-
V
Output "Low" Voltage
All Outputs
VOL
IOL = 1.6mA
-
-
0.55
V
Cin
Vin=OV, f= 1.0MHz,
Ta = 25°C
-
-
12.5
pF
iJ,A
mA
RES, STBY
Input "High" Voltage
EXTAL
Vee-0.5
Vee xO .7
V 1H
Other Inputs
Input Capacitance
Standby Current
PIO- P 17, P20 -P 24 ,
All Inputs
Non Operation
2.0
IOH = -10iJ,A
-
2.0
15.0
Operating (f=l MHz* *)
-
6.0
Sleeping (f=l MHz**)
-
1.0
10.0
2.0
lee
Current Dissipation *
lee
RAM Stand·By Voltage
V RAM
• V1H min = Vee-1.OV, VIL max
IOH = -200iJ,A
2.0
-
-
V
= O.8V
•• Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max.
values about Current Dissipations at f = x MHz operation are decided according to the following formula;
typo value (f
max. value (f
408
= xMHz) = typo value
(f = 1 MHz) x x
value (f = 1 MHz) x x
(both the sleeping and operating)
= xMHz) = max.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
•
AC CHARACTERISTICS (Vee
= 5.0V±10%, Vss = OV, Ta = 0~+70°C, unless otherwise
noted.)
BUS TIMING
Item
Symbol
Test
Condition
HD6303R
min
typ
HD63A03R
max min
1
-
PW ASH
220
-
Address Strobe Rise Time
tASr
-
-
20
Address Strobe Fall Time
tASf
-
-
Address Strobe Delay Time *
tASD
60
-
20
-
Enable Rise Time
tEr
Enable Fall Time
tEf
450
-
-
60
-
-
-
-
-
-
250
250
250
-
Cycle Time
tcyc
Address Strobe Pulse Width *
"High"
Enable Pulse Width "High" Level* PWEH
Enable Pulse Width "Low" Level* PWEL
Address Strobe to Enable Delay*
t ASED
Time
Address Delay Time
450
tAD'
f-Fig. 1
tAD2
Fig. 2
tADL
typ
10 0.666 -
-
20
20
-
150
-
40 300 300 -
-
20
-
Address Set-up Time for Latch *
tASL
60
40
-
Address Hold Time for Latch
tAHL
30
-
-
20
-
Addr~ss
tAH
20
tASM
200
-
-
-
-
-
-
tpcs
Fig.9
200
-
ns
ns
-
20
Processor Control Set-up Time
-
-
tHW
-
ns
ns
ns
-
Write
20
160
160
160
-
-
Fig.8
ns
-
-
tRC
-
-
0
Oscillator stabilization Time
ns
-
20
220
20
tHR
*
Multiplexed Bus (tACCM)
-
-
190
190
190
Read
I
20
-
80
Access Time
220
20
-
tDSR
INon-Multiplexed* (tACCN)
Peripheral Read Bus
-
-
-
Read
Ao ~ A7 Set-up Time Before E *
20
-
-
-
I1S
-
-
-
Hold Time
20
10
Unit
110
-
230
Data Hold Time
-
max
-
40
t Dsw
Data Set-up Time
10 0.5
-
Write
Address Delay Time for Latch*
HD63B03R
max min typ
ns
20
ns
20
ns
-
ns
20
ns
20
ns
-
ns
100
110 -
-
650
-
-
395
-
-
270
650
-
-
395 -
-
270
ns
20
-
-
ms
200
-
-
-
ns
60 0 -
150
-
-
20
50
0
20
20
20
20
60
200 20
ns
ns
ns
ns
ns
ns
ns
*These timings change in approximate proportion to tcyco The figures in this characteristics represent those when tcyc is minimum
(= in the highest speed operation).
PERIPI:IERAL PORT TIMING
Item
Symbol
Test
Condition
min
typ
HD63B03R
HD63A03R
HD6303R
max min
typ
max min typ
max
Unit
Peripheral Data
Set-up Time
Port 1,2
tpDSU
Fig. 3
200
-
-
200
-
-
200
-
-
ns
Peripheral Data
Hold Time
Port 1,2
t pDH
Fig. 3
200
-
-
200
-
-
200
-
-
ns
tpWD
Fig.4
-
-
300
-
-
-
-
D.,.V Tim., En.b'. N"o-I Port
1
tive Transition to Peri2*
'
pheral Data Valid
300
300
ns
• Except P"
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
409
HD6303R,HD63A03R,HD63B03R~~~~~~~~~~~~~~~~~~~~~~~
TIMER, SCI TIMING
Item
Symbol
Test
Condition
HD63A03R
HD6303R
min
typ
max min
-
typ
HD63B03R
max min
typ
-
2.0
-
-
-
-
-
2.0
-
-
2.0
-
0.6
0.4
-
max
-
tpWT
2_0
-
Delay Time, Enable Positive
Transition to Timer Out
tTO D
-
-
SCI Input Clock Cycle
t ScyC
2.0
-
-
SCI Input Clock Pulse Width
tPWSCK
0.4
-
0.6
Test
Symbol Condition
min
typ
max min
typ
max min
typ
max
3
-
-
3
3
-
-
-
2
-
-
2
-
2
-
-
150
-
-
150
-
-
150
-
-
Timer Input Pulse Width
Fig. 5
400
0.4
400
2.0
400
Unit
tCYC
ns
-
tcyC
0.6
tScyc
MODE PROGRAMMING
Item
RES "low" Pulse Width
PW RSTL
Mode Programming Set-up Time
tMPs
Mode Programming Hold Time
tMPH
Fig.6
HD63B03R
HD63A03R
HD6303R
Unit
tCYC
tcyC
ns
I+-----------------------t~c------------------------I
2.4V
Address Strobe
(AS)
2.4V
Enable
(E)
MPU Write
Do-D"A.-A,
MPU Read
0.-0,. A.-A,
Figure 1 Multiplexed Bus Timing
410
~
NotValid
_HITACHI
Hitachi America Ltd_ • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435.8300
teve
Enable
lEI
2.4V
O.BV
MPUW,ite
0.-0,
MPU Read
0.-0,
------+---------+-----------~
------~--------4---------------------~1
2.4V
O.6V
Figure 2
IZ?ZI
Non-Multiplexed Bus Timing
r
r M P U Read
Not Valid
MPUWri.e
~
I-'PWD-l
P,o - p.,
p •• - p,.
Inputs
All D...
2.4V D••• V.lid
Port Ou.puts _____________.J I\..:;,.O.:;,.8V:.......___
Note) Port 2: Except P2 I
Figure 3 Port Data Set-up and Hold Times
(MPU Read)
Figure 4
Port Data Delay Times
(MPU Write)
Timer
Counter _______.J '----t-------' ' - - - - -
Mode Inputs ------....:;;.:.;.{l
(P20. P2l . Pu I
P"
Output
Figure 5 Timer Output Timing
Figure 6 Mode Programming Timing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
411
Vee
RL
= 2.2kn
(4.0kn for E)
e=90pF for AS, R/W, Do/AD ~ D,/A 7 , and AS
=30pF for P20 ~ P2 • and Ao/P ,o - A7 /P 17
=40pF for E
R=12kQ
Test Point
1S2074 (8)
or Equiv.
e
Figure 7 Bus Timing Test Loads (TTL Load)
Interrupt
Test
Internal
Address Bus --"-+-~~~'.:-~"-"==,~""""::,~,,-=::-:-J\..~-::J'~~"-:o~..J\.":<"::,,,~~;"l;""0-::=...I'~~':':"'~~r'---"-.
NMI.IRQ,
Internal
Data Bus _ _"-_...A_..J\.-_"-_-"_..J'\.,..._J\.._..J'...,.._,...,.."..,..,J\..,...,....~~,.,....~=~""""~'-",.,....~.--~
Internal
Read
Internal
Write
______-'1
Figure 8 Interrupt Sequence
\~---------------
:~~.... _)\\\\\\\\\\\\\\\\\\\\\~~~~Ii-----FFFF FFFE
:;'ternll _
)\\\\\\\\\\\\\\\\\\\\\\
~t.rnll _
~\\\\\\\\\\\\\\\\\\\\\\\
FFFF New PC
I~
!~~.~\----------
RNi_~\\\\\\\\\\\\\\\\\\\\Wl
~:".:t\\\\\\\\\\\\\"'\\\\\\\\\\\\\\\\\,---------~I:~~f-I- - - - Figure 9 Reset Timing
•
FUNCTIONAL PIN DESCRIPTION
• Vee'Vss
These two pins are used for power supply and GND.
Recommended power supply voltage is 5V ± 10%. 3 to 6V can
be used for low speed operation (l00 - 500 kHz).
•
mental crystal, AT cut. For instance, in order to obtain the
system clock lMHz, a 4MHz resonant fundamental crystal is
used because the devide-byA circuitry is included. An example
of the crystal interface is shown in Fig. 10. EXTAL accepts
an external clock input of duty 45% to 55% to drive. For
external clock, XTAL pin should be open. The crystal and
capacitors should be mounted as close as possible to the pins.
XTAL, EXTAL
These two pins are connected with parallel resonant fun Zero
BGT
2E
3
2
Z + (N
BHI
22
3
2
C+Z=O
Branch If
Branch If Higher
<±l
V· 0
<±l
<±l
V)· 0
Branch If <: Zero
BlE
2F
3
2
Z + (N
Branch If lower Or
Same
BlS
23
3
2
C+Z=1
N@V-l
< Zero
BlT
20
3
2
Branch If Minus
BMI
2B
3
2
N·l
Branch If Not Equal
Zero
BNE
26
3
2
z=o
Branch If Overflow
Clear
BVC
28
3
2
V-O
Branch If Overflow Set
BVS
29
3
2
V -I
Branch If Plus
BPl
2A
3
2
Branch To Subroutine
BSR
80
5
2
Jump
JMP
Jump To Subroutine
JSR
No Operation
NOP
01
Return From Interrupti
RTI
3B 10 1
Return From
Subroutine
RTS
39
Bra nch If
N-O
BE
90
3
2
7E
3
3
5 2 AD 5 2 BD 6 3
1
1
Advances Prog, entr.
Only
5 1
Software Interrupt
SWI
3F 12 1
Wait for Interrupt"
Sleep
WAI
3E
9
SLP
'"
4
1
1
Note) *WAI ~~ts R/W high; ,Addre~s Bus goes .to F~FF; Data Bus goes to the three state,
Condition Code Register Will be explained In Note of Table 10.
Hitachi America Ltd. •
2210
V)· 1
~HITACHI
O'Toole Ave. • San Jose, CA 95131
5
4
3
H
I
N Z
2
1 0
V
C
·· ·· ·· ·· ·· ··
··· ··· ··· ··· ··· ···
··· ··· ··· ··· ··· ···
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·
·· ·· ·· ·· ·· ··
··· ··· ··· ··· ··· ···
·· ·· ·· ·· ·· ··
·· · ·· ·· ·· ··
·• • • ·• ·• ·•
a
--@
--
S
@.
425
• (408) 435-8300
HD6303R,HD63A03R,HD63B03R----------------------------------------------Table 10 Condition Code Register Manipulation Instructions
CondItion Code Register
iAddressingModet
Operations
OC
-1
Cli
OE
1
ClV
OA
1
Set Carry
SEC
Set Interrupt Mask
SEI
00
OF
Set Overflow
SEV
08
Accumulator A - CCR
TAP
CCR - Accumulator A
TPA
OP
Claar Carry
ClC
Clear Interrupl Mask
ClnrOverfiow
[NOTE
11
@)
21
3
2
1
I
N
Z
V
1
e
R
0-1
,
O-V
,
1
l-C
1
1- I
06
1
1
A- CCR
07
1
,
,
R
S
S
S
I-V
1
C
R
O-C
1
0
---@---
CCR-A
Condition Code
CD (Bit V)
@
(Bit C)
@
(Bit C)
@
(Bit V)
@
(Bit V)
® (Bit V)
(j)
(Bit N)
@
(All Bit)
@
(Bit II
®
[NOTE
4
H
·· · ·· ·· ··
·· ·· ·· ·· · ·
·· · ·· ·· · ··
······
If
1
5
Boolean OperatIon
IMPLIED
MnemonIC
Register Notes: (Bit set if test is true and cleared otherwise)
Test: Result = 1000oooo?
Test: Result, Oooooooo?
Test: BCD Character of high-<>rder byte greater than 9? (Not cleared if previously set)
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to N
f'O
E pin
"0
>.,
'0
z
0.5
A. pin
ns
OL--------.------~._-------.
50
100
Fig. 32
Data bus load capacitance Cd [pFJ
Fig. 31
438
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - HD6303R,HD63A03R,HD63B03R
(3) Insert a bypass capacitor between the Vee line and the
GND of the HD6303R. A tantalum capacitor (about
O.l,uF) is effective on the reduction.
(b) Reduction of GND line impedance
(1) Widen the GND line width on the PC board.
(2) Place the HD6303R close by power source.
~~~------~-------r------~--~~
Power
Source
~~~------~--------~------~~--~~
IRecommended)
Power
Source
~~--------~--------~------~~
Fig. 33 Layout of the HD6303R on the PC board
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
439
HD6303X,HD63A03X,---HD63B03X
CMOS MPU (Micro Processing Unit)
The HD6303X is a CMOS 8-bit micro processing unit (MPU)
which includes a CPU compatible with the HD630IVl, 192
bytes of RAM, 24 parallel I/O pins, a Serial Communication
Interface (SCI) and two timers on chip.
HD6303XP. HD63A03XP.
HD63B03XP
•
•
•
•
FEATURES
Instruction Set Compatible with the HD6301Vl
192 Bytes of RAM
24 Parallel I/O Pins
16 I/O Pins-Port 2. 6
8 Input Pins-Port 5
• Darlington Transistor Drive (Port 2. 6)
• 16-Bit Programmable Timer
(DP-64S)
Input Capture Register x 1
Free Running Counter x 1
H D6303X F. H D63A03X F.
Output Compare Register x 2
HD63B03XF
• 8-Bit Reloadable Timer
External Event Counter Square Wave Generation
• Serial Communication Interface
• Memory Ready
• Halt
• Error-Detection (Address Trap. Op-Code Trap)
• Interrupts ... 3 External. 7 Internal
• Up to 6Sk Bytes Address Space
• Low Power Dissipation Mode
Sleep Mode
(FP-80)
Standby Mode
• Minimum Instruction Execution Time -O.5#LS
• PIN ARRANGEMENT
(f = 2.0 MHz)
• HD6303XP. HD63A03XP.
• HD6303XF. HD63A03XF. HD63B03XF
• Wide Range of Operation
HD63B03XP
Vcc = 3 - 6V (f = 0.1 - O.S MHz).
f = 0.1 - 1.0 MHz; HD6303X
V. 1
E
oJ
Vcc = SV±10% f = 0.1 - 1.5 MHz; HD63A03X XTAL~ 0
IfIj"
[
~~w~li~~I~~Q
f = 0.1 - 2.0 MHz; HD63B03X EXTAL J
Wrf
MP. ~
MP, 5
1
R/W
iJ"A"
RES 6
BA
SfBY~
D.
D,
D,
D,
NMI B
P:lO 9
P"
P"
~
i!:I
D.
D,
D.
1 D,
P u 12
P'14 1
P:as
1
Pu
1
P:n
1
A.
A,
A.
A,
A.
A,
Pso 1
PSI '
Pn
1
P"
p ..
1
P"
p ..
.
A.
A,
Vo
1 A•
A,
J A,.
P"
p••
P.l 2
p.. 7
P"
p..
p.,
p..
A"
1 An
P"
(Top View)
440
.., Ne
A"
A ..
An
Vee
1
(Top View)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
~~~~~~~~~~~~~~~~~~~~~~~~HD6303X,HD63A03X,HD63B03X
•
BLOCK DIAGRAM
vcc
rD1I j Ii
vss
vss
o
...J
a:
~
NO
P2o(Tin)
Q..
0
~
P22!SCLK)
t 0
o 0
X
P2,(Tout1)
Na:
1L...
N
P23(Rx)
...J
<
r-
IIII
I
~
Ia: r3: I~ <
a:3:~...JaJ
X
w
6l,/oa:
I~
a:a:a:::::!:J:
CPU
RD
~
I~
0
P24(Tx)
n
Q..
~
~
A
P25(Tout2)
WR
R/W
LlR
BA
P26(Tout3)
P27(TclK)
\I
I-------
L.--
l-.
'---
A
\
V
-V
Ci;
E
~
:J
en I------/
III
:J
~
~
I-----
en
10
0
"----
V
1\
U
Vl
L.--
A
,...--
V
~
aJ'"::l
£ f-----
1"0
iii
I----
N
Ci;
V
E
:J
~
III
~
en
0
A
:J
en
1\
~
\I
~
aJ'"::l
..---
J
V
'"'"
Pso(i"R'Q,,)
III
III
C1l
-C
"'C
«
P51(iR02'
2)
~
L...--
<
..---
"0
PS3(~
LT)
Ln
P54
Q..
~
III
f.----
:J
en
P 57
'"
L.--
V
A
::l
~
"'C
"'C
«
P 60 P 61 -
a:
P62It)
0
0
0
V
~
~
:J
P 56
P 66 -
~
f---
f---
£
en
P 64 - -
f.----
~
0
P 55
P 6S - -
f.----
Q)
P52(M R)
P63-
I--I---
I-----
~
I------I-------
£
-------<
~
~
f-----
f--I----
L.....-
It)
Q..
ce
RAM
192 Bytes
P 67 -
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
441
HD6303X,HD63A03X,HD63B03X----------------------------------------------•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Supply Voltage
Input Voltage
Vee
V in
Operating Temperature
Topr
Storage Temperature
Tstg
Value
Unit
-0.3 - +7.0
V
-0.3 - Vee+0.3
V
°c
0-+70
°c
-55 - +150
(NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection
circuits. To assure the normal operation, we recommend Vin , Vout : VSS ;£ (Vin or Vout ) ;£ Vee.
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc = 5.0V±10%, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)
Item
Symbol
Test Condition
RES, STBY
Input "High" Voltage
EXTAL
V 1H
Input Leakage Current
Three State (off-state)
Leakage Current
Output "High" Voltage
All Inputs
NMI, RES, STBY,
MP o , MP 1 , Port 5
Ao-A 1 5,0 0 -0 7 , RD,
WR, R/W,Port 2,Port 6
All Outputs
typ
-0.3
-
0.8
V
-
-
1.0
p.A
Vee xO . 7
Other Inputs
Input "low" Voltage
min
Vee- 0 .5
2.0
V 1L
liinl
V in = 0.5-V ee -0.5V
IiTsl1
V in = 0.5-V ee -0.5V
V OH
IOH = -200p.A
max
Unit
Vee
+0.3
V
-
-
1.0
p.A
2.4
-
Vee- 0 .7
-
V
V
Output "Low" Voltage
All Outputs
VOL
IOL = 1.6mA
-
-
0.4
V
Darlington Drive
Current
Ports 2, 6
-loH
Vout = 1.5V
1.0
-
10.0
mA
I nput Capacitance
All Inputs
C in
V in = OV, f = 1MHz,
Ta = 25°C
-
-
12.5
pF
Standby Current
Non Operation
ISTB
-
3.0
15.0
p.A
mA
IOH = -10p.A
Sleeping (f = 1 MHz* *)
IsLP
Sleeping (f = 1.5MHz**)
Sleeping (f = 2MHz**)
Current Dissipation *
Operating (f = 1MHz**)
Icc
Operating (f = 1.5MHz**)
Operating (f = 2MHz**)
RAM Standby Voltage
V RAM
2.0
1.5
3.0
2.3
4.5
mA
3.0
6.0
mA
7.0
10.0
mA
10.5
15.0
mA
14.0
20.0
mA
-
-
V
·V 1H min = Vcc-1.OV, VIL max = O.8V ,All output terminals are at no load.
··Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max.
values about Current Dissipations at x MHz operation are decided according to the following formula;
typo value (f = x MHz) = typo value (f = 1 MHz) x x
max. value If = x MHz) = max. value (f = 1MHz) x x
(both the sleeping and operating)
442
$HITACfu
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------~----------------------------------HD6303X,HD63A03X,HD63B03X
•
AC CHARACTERISTICS (Vee
= 5.0V±10%, Vss =OV, Ta =0 ~ +70°C, unless otherwise noted.)
BUS TIMING
Item
Symbol
Test
Condition
HD63A03X
HD6303X
min
typ
max
min
typ
HD63B03X
Unit
max
min
typ
max
10
Ils
25
ns
25
ns
ns
Cycle Time
tcyc
1
-
10
0.666
-
10
0.5
Enable Rise Time
tEr
-
25
-
-
25
-
Enable Fall Time
-
25
-
-
25
-
-
Enable Pulse Width "High" Level*
tEf
PW EH
450
-
-
300
-
-
220
-
-
Enable Pulse Width "Low" Level*
PWEL
450
-
-
300
-
-
220
-
-
ns
Address, RIW Delay Time*
tAD
-
-
250
200
-
ns
120
ns
tOSR
80
-
-
160
-
-
190
to ow
-
-
70
-
70
-
-
ns
tAH
80
-
50
-
35
-
-
ns
tHW
80
-
-
-
50
-
-
40
-
-
ns
0
-
0
ns
-
220
40
ns
I Write
I Read
Data Delay Time
Data Set-up Time
Address, RIW Hold Time*
I Write*
Data Hold Time
I Read
Fig. 1
160
-
-
300
-
-
-
40
-
-
40
-
-
tHRW
-
-
30
-
-
30
-
-
25
ns
LI R Delay Time
tOLR
-
200
-
-
160
-
-
120
ns
-
ns
-
ns
0
-
RD, WR Pulse Width*
tHR
PW RW
450
RD, WR Delay Time
tRwo
RD, WR Hold Time
LlR Hold Time
tHLR
10
-
-
10
-
-
10
MR Set-up Time*
tSMR
400
-
-
280
-
230
M R Hold Time *
tHMR
-
90
-
40
E Clock Pulse Width at MR
PWEMR
-
9
-
-
9
-
Processor Control Set-up Time
tpcs
Processor Control Rise Time
tpcr
Processor Control Fall Time
tpCf
SA Delay Time
teA
Oscillator Stabilization Time
tRC
Reset Pulse Width
PWRS T
Fig.2
Fig. 3,
10,11
ns
0
ns
9
IlS
200
-
-
200
-
-
200
-
-
ns
-
-
100
-
-
100
-
100
ns
-
-
100
-
100
ns
250
-
-
190
-
160
ns
Fig. 11
20
-
100
Fig.3
-
-
-
-
20
-
-
ms
-
-
20
3
-
3
-
-
tcyc
Fig. 2, 3
3
• These timings change in approximate proportion to tcyc- The figures in this characteristics represent those when tcyc is minimum
(= in the highest speed operation)_
PERIPHERAL PORT TIMING
Item
Symbol
HD6303X
HD63A03X
HD63B03X
Test
Condition
min
typ
max
min
typ
max
min
typ
max
Unit
Peripheral Data
Set-up Time
Ports 2, 5, 6
tposu
Fig.5
200
-
-
200
-
-
200
-
-
ns
Peripheral Data
Hold Time
Ports 2, 5, 6
tpOH
Fig.5
200
-
-
200
-
-
200
-
-
ns
tpwo
Fig.6
-
-
300
-
-
300
-
-
300
ns
D.,.y T;m. (En.bl, I
Negative Transition to
Peripheral Data Valid)
Ports 2, 6
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
443
HD6303X,HD63A03X,HD63B03X----------------------------------------------TIMER SCI TIMING
Item
Timer 1 Input Pulse Width
Delay Time (Enable Positive
Transition to Timer Output)
SCI Input
Clock Cycle
lr Async. Mode
Clock Sync.
Test
Condition
min
tPWT
Fig.8
2.0
tTOD
Fig.7
-
Fig.8
1.0
-
Fig. 4, 8
2.0
-
-
tScyC
HD63A03X
HD6303X
Symbol
typ
typ
HD63B03X
Unit
max
min
tvp
-
-
2.0
-
-
tcyc
-
400
-
-
400
ns
-
1.0
-
-
2.0
-
-
tcyc
-
200
-
-
200
ns
290
-
-
290
-
-
ns
max
min
-
-
2.0
-
400
-
-
1.0
-
-
2.0
-
-
200
-
290
-
-
max
t<;yc
SCI Transmit Data Delay
Time (Clock Sync. Mode)
tTXD
SCI Receive Data Set-up
Time (Clock Sync. Mode)
tSRX
SCI Receive Data Hold Time
(Clock Sync. Mode)
tHRX
100
-
-
100
-
-
100
-
-
ns
SCI I nput Clock Pu Ise Width
tPWSCK
0.4
-
0.6
0.4
-
0.6
0.4
-
0.6
tscyc
Timer 2 Input Clock Cycle
ttCyc
2.0
-
-
2.0
-
-
2.0-
-
-
tcyc
Timer 2 Input Clock Pulse
Width
tpwTCK
200
-
-
200
-
-
200
-
-
ns
Timer l' 2, SCI Input Clock
Rise Time
tCKr
-
-
100
-
-
100
-
-
100
ns
Timer l' 2, SCI Input Clock
Fall Time
tCKf
-
-
100
-
-
100
-
-
100
ns
444
Fig. 4
Fig.8
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------HD6303X,HD63A03X,HD63B03X
t-----------tCyC------------l
I-----PWEL---~
2.4V
O.8V
RO,WR
MPU Write
00-07
MPU Read
00-07
LlR
Figure 1 Bus Timing
t-------PWEMR------I
\
E
\
\
'-----
O.8V
MR
Figure 2 Memory Ready and E Clock Timing
~HITACHI
\ Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
445
HD6303X,HD63A03X,HD63B03X----------------------------------------------Last Instruction
Execution Cycle
Instruction EXtlcution
Cycle
HALT Cycle
I
tBA~~r----~'----------~----------~
BA
Figure 3 HALT and BA Timing
Synchronous Clock
Transmit Data
Receive Data
-<~__~~~~_~__t_"~~____
• 2.0V is high level when clock input.
2.4V is high level when clock output.
Figure 4 SCI Clocked Synchronous Timing
I
jMPU Read
MPU Write
E
P20-P27
Pso- PS7 _ _ _ _ _ _- - J
1\-=0=";---
(Outputs)
Figure 5 Port Data Set-up and Hold Times (MPU Read)
446
Figure 6 Port Data Delay Times (MPU Write)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------HD6303X,HD63A03X,HD63B03X
E
E
Timer 1 - - - -.....
FRC
P21 , P2S
r-,~~::-::-:........
,---T2CNT
-------.:..--
Outputs-------------_-J
p,.Output _ _ _ _-'
~~_ _ __
TCONR
(a) Timer 1 Output Timing
=N
(b) Timer 2 Output Timing
Figure 7
Timer Output Timing
vcc
m
RL =2.2kQ
Test Point
C
**
tCKf
* Timer 2; ttcyc
SCI
; tscyc
R
1S2074(fl)
or Equiv.
C=90pF for Do~D7' Ao-A ls , E
=30pF for Port 2, Port 6, RD, WR, R/W, BA,
R=12kn
** Timer 1; tPWT
Timer 2; tPWTCK
SCI
; tPWSCK
DR
Figure 9 Bus Timing Test Loads (TTL Load)
Figure 8 Timer "2, SCI Input Clock Timing
Interrupt
Test
Internal
Address Bus ____" .....-+-...J.'--__"'-__...J''--__'''-__-''--__J'-__- ' ' - -__J'-_...J''--_'''-__...J''--__,'-__...r..__~''-__...r.._
NMI.IRQ1.
IRQ2.IRQ3
Internal
DataBus ____J~__-"'____J ....._...J'~_J.....__...J'____J'-__-J'___J~__...J·'____" ....._...J·'___I~__~,_
Op
Operand Irrelevant pca Code Op Code Data
PC 7
Internal
Read
Internal
Write
\~
PCB PC 15
Ixa IX 7
Ixa IX 15
ACCA
ACCB
CCR
_J' ~_ _~,_
Vector Vector First Inst. of
MSB
LSB
Interrupt Routine
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ J
______...J'
\~----------------Figure 10 Interrupt Sequence
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
447
HD6303X,HD63A03X,HD63B03X-----------------------------------------------
~Ir- \S.S~\-_=_V -'_AC~--i'r--~======'~~
,.=-l~,...J
'PCS
AE ~ _ _ _ _ _ _... >-_-J'
·cc
V CC -O·5v
08\1
~f'r-------
~~~,essi\\\\\ll"\\\\\\\\\\\\\\\\\\mc:x=~---r--"~
FFFF
~,e'nal
FFFF FFFF FFFF
FFFF FFFE
''-F1FF
FFFF N.wPC
1\\\\1 )\\\\\\\\"""\\\\\\\\\
FFFF FFFF
I~>-------I~(
-----
~'e,",' BBN\\\\\\\\\\\\\\\\\\\\\\\
I~'r----II-(_ _ _ __
~ at~§fu\\\\\\\\\\\\\\\\"
WR
1R'~\\M\\\\§§\\\\\\~\.
g~:' .l)\~m~~m'mm~mlltl~\1Il\11#1Iilli11'11~--------:;cro-o:l~~i-(-----PC8- PCO- First
PC 15 PC7
Instruction
Figure 11 Reset Timing
•
FUNCTIONAL PIN DESCRIPTION
• Vee, Vss
Vee and Vss provide power to the MPU with 5V±1O%supply. In the case of low speed operation (fmax = 500kHz), the
MPU can operate with three through six volts. Two Vss pins
should be tied to ground.
•
XTAL, EXTAL
These two pins interface with an AT-cut parallel resonant
crystal. Divide-by-four circuit is on chip, so if 4MHz crystal
oscillator is used, the system clock is IMHz for example.
AT Cut Parallel Resonant Crystal Oscillator
Co=7pF max
Rs=60Q max
CL1 =CL2
= 1OpF - 22pF 20%
+
(3.2 -BMHz)
EXTALr--+--,
-1- Jr
CL2
CL
1
Figure 12 Crystal Interface
EXT AL pin can be drived by the external clock of 45 to
55% duty, and one fourth frequency of the external clock
is produced in the LSI. The external clock frequency should
be less than four times of the maximum operable frequency.
When using the external clock, XTAL pin should be open.
Fig. 12 shows an example of the crystal interface. The crystal
and CLl, CL2 should be mounted as close as possible to XT AL
448
•
STBY
This pin makes the MPU standby mode. In "Low" level, the
oscillation stops and the internal clock is stabilized to make
reset condition. To retain the contents of RAM at standby
mode, "0" should be written into RAM enable bit (RAME).
RAME is the bit 6 of the RAM/port 5 control register at $0014.
RAM is disabled by this operation and its contents is sustained.
Refer to "LOW POWER DISSIPATION MODE" for the
standby mode.
•
XTAL t---...------,
c:J
and EXT AL pins. Any line must not cross the line between the
crystal oscillator and XT AL, EXT AL.
Reset (RES)
This pin resets the MPU from power OFF state and provides a startup procedure. During power-on, RES pin must
be held "Low" level for at least 20ms.
The CPU registers (accumulator, index register, stack pointer,
condition code register except for interrupt mask bit), RAM
and the data register of a port are not initialized during reset,
so their contents are unknown in this procedure.
To reset the MPU during operation, RES should be held
"Low" for at least 3 system-clock cycles. At the 3rd cycle
during "Low" level, all the address buses become "High". When
RES remains "Low", the address buses keep "High". If RES
becomes "High", the MPU starts the next operation .
. (l) Latch the value of the mode program pins; MP 0 and MP I .
(2) Initialize each internal register (Refer to Table 3).
(3) Set the interrupt mask bit. For the CPU to recognize the
maskable interrupts IRQI , IRQ2 and IRQ3, this bit should
be cleared in advance.
(4) Put the contents (= start address) of the last two addresses
($FFFE, $FFFF) into the program counter and start the
program from this address. (Refer to Table 1).
*The MPU is usable to accept a reset input until the clock
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------HD6303X,HD63A03X,HD63B03X
becomes normal oscillation after power on (max. 20ms). During
this transient time, the MPU and I/O pins are undefined. Please
be aware of this for system designing.
•
Enable (E)
This pin provides a TTL-compatible system clock to external
circuits. Its frequency is one fourth that of the crystal oscillator
or external clock. This pin can drive one TTL load and 90pF
capacitance.
•
Non-Maskable Interrupt (NMI)
When the falling edge of the input signal is detected at this
pin, the CPU begins non-maskable interrupt sequence internally.
As well as the IRQ mentioned below, the instruction being
executed at NMI signal detection will proceed to its completion.
The interrupt mask bit of the condition code register doesn't
affect non-maskable interrupt at all.
When starting the acknowledge to the NMI, the contents of
the program counter, index register, accumulators and condition
code register will be saved onto the stack. Upon completion
of this sequence, a vector is fetched from $FFFC and $FFFD
to transfer their contents into the program counter and branch
to the non-maskable interrupt service routine.
(Note) After reset start, the stack pointer should be initialized
on an appropreate memory area and then the falling edge
should be input to NMI pin.
•
Interrupt Request (lRG" IRQ2)
These are level-sensitive pins which request an internal
interrupt sequence to the CPU. At interrupt request, the CPU
will complete the current instruction before its request acknowledgement. Unless the interrupt mask in the condition code
register is set, the CPU starts an interrupt sequence; if set, the
interrupt request will be ignored. When the sequence starts, the
contents of the program counter, index register, accumulators
and condition code register will be saved onto the stack, then
the CPU sets the interrupt mask bit and will· not acknowledge
the maskable request. During the last cycle, the CPU fetches
vectors depicted in Table I and transfers their contents to the
program counter and branches to the service routine.
The CPU uses the external interrupt pins, IRQ, and IRQ2,
also as port pins P so and PSI, so it provides an enable bit to
Bit 0 and 1 of the RAM port 5 control register at $0014. Refer
to "RAM/PORT 5 CONTROL REGISTER" for the details.
When one of the internal interrupts, ICI, OCI, TOI, CMI or
SIO is generated, the CPU produces internal interrupt signal
(IRQ3)' IRQ3 functions just the same as IRQ, or IRQ2 except
for its vector address. Fig. 13 shows the block diagram of the
interrupt circuit.
Table 1 Interrupt Vector Memory Map
Priority
Highest
Lowest
Vector
MSB
Interrupt
LSB
FFFE
FFFF
RES
FFEE
FFEF
TRAP
FFFC
FFFD
NMI
FFFA
FFFB
SWI (Software Interrupt)
FFF8
FFF9
IRQ,
FFF6
FFF7
ICI
FFF4
FFF5
OCI (Timer 1 Output Compare 1, 2)
(Timer 1 Input Capture)
FFF2
FFF3
TOI (Timer 1 Overflow)
FFEC
FFED
CMI (Timer 2 Counter Match)
FFEA
FFEB
IRQ 2
FFFO
FFFl
SIO (RDRF+ORFE+TDRE)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
449
HD6303X,HD63A03X,HD63B03X----------------------------------------------Each Register's Interrupt
Enable Flag
","; Enable, "0"; Disable
IRO,
IR02
ICF
OCF'
OCF2
Interrupt
Request
Signal
TOF
IRQ3
CMF
RDRF
ORFE
TDRE
Sleep
Cancel
Signal
TRAP
SWI
Figure 13 Interrupt Circuit Block 0 iagram
•
access, MR is prohibited internally to prevent decrease of operation speed. Even in the halt state, MR can also stretch "High"
period of system clock to allow peripheral devices to access
low-speed memories. As this signal is used also as P 52 , an enable
bit is provided at bit 2 of the RAM/port 5 control register at
$0014. Refer to "RAM/PORT 5 CONTROL REGISTER" for
more details.
Mode Program (MP o , MPd
To operate MPU, MP o pin -should be connected to "High"
level and MP 1 should be connected to "Low" level (refer to
Fig. 15).
•
Read/Write (R/VV)
This signal, usually be in read state ("High"), shows whether
the CPU is in read ("High") or write ("Low") state to the
peripheral or memory devices. This can drive one TTL load
and 30pF capacitance.
•
•
RD,WR
These signals show active low outputs when the CPU is
reading/writing to the peripherals or memories. This enables
the CPU easy to access the peripheral LSI with RD and WR
input pins. These pins can drive one TTL load and 30pF capacitance.
•
Load Instruction Register (LIR)
This signal shows the instruction opecode being on data
bus (active low). This pin can drive one TTL load and 30pF
capacitance.
•
•
Memory Ready (MR; Pd
This is the input control signal which stretches the system
clock's "High" period to access low-speed memories. During
this signal is in "High", the system clock operates in normal
sequence. But this signal in "Low", the "High" period of the
system clock will be stretched depending on its "Low" level
duration in integral multiples of the cycle time. This allows the
CPU to interface with low-speed memories (see Fig. 2). Up to
9 ps can be stretched.
During internal address space access or nonvalid memory
450
Halt (HALT; P 53 )
This is an input control signal to stop instruction execution
and to release buses. When this signal switches to "Low", the
CPU stops to enter into the halt state after having executed
the present instruction. When entering into the halt state, it
makes BA (P 74 ) "High" and also an address bus, data bus, RD,
WR, R/W high impedance. When an interrupt is generated
in the halt state, the CPU uses the interrupt handler after the
halt is cancelled.
(Note) Please don't switch the HALT signal to "Low" when
the CPU executes the WAI instruction and is in the
interrupt wait state to avoid the trouble of the CPU's
operation after the halt is cancelled.
Bus Available (BA)
This is an output control signal which is normally "Low"
but "High" when the CPU accepts HALT and releases the buses.
The H06800 and H06802 make BA "High" and release the
buses at WAI execution, while the H06303X doesn't make
BA "High" under the same condition. But if the HALT becomes
"Low" when the CPU is in the interrupt wait state after having
executed the WAI, the CPU makes BA "High" and releases the
buses. And when the HALT becomes "High", the CPU returns
to the interrupt wait state.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------HD6303X,HD63A03X,HD63B03X
•
PORT
The HD6303X provides three I/O ports. Table 2 gives the
address of ports and the data direction register and Fig. 14
the block diagrams of each port.
Table 2 Port and Data Direction Register Address
Port
Port Address
Data Direction Register
Port 2
$0003
$0015
$0017
$0001
$0016
Port 5
Port 6
•
Port 2 is also used as an I/O pin for the timers and the
SCI. When used as an I/O pin for the timers and the SCI, port
2 except P 20 automatically becomes an input or an output
depending on their functions regardless of the data direction
register's value.
Port 2 Data Direction Register
4
Port 2
An 8-bit input/output port. The data direction register
(DDR) of port 2 controls the I/O state. It provides two bits;
bit 0 decides the I/O direction of P20 and bit 1 the I/O direction ofP 21 to P27 ("0" for input, "I" for output).
A reset clears the DDR of port 2 and configures port 2 as an
input port. This port can drive one TTL and 30pF capacitance. In addition, it can produce ImA current when Vout
1 .5V to drive directly the base of Darlington transistors.
Port Write Signal
Data Bus
Timer 1, 2,;--t-_ _ _..J
SCI Output
Port Read Signal
Tri·state
Control
....L
~~'r~~~~t,---------<
Port 2
Data Bus
Figure 14 Port Block Diagram
•
RAM and port 5.
Port 5
An 8-bit port for input only. The lower four bits are also
usable as input pins for interrupt, MR and HALT.
•
7
Port 6
An 8-bit I/O port. This port provides an 8-bit DDR corresponding to each bit and can specify input or output by the
bit ("0" for input, "1" for output). This port can drive one
TTL load and 30pF capacitance. A reset clears the DDR of port
6. In addition, it can produce ImA current when Vout = I.5V
to drive directly the base of Darlington transistors.
•
RAM/Port 5 Control Register
BUS
•
0 0 -0 7
These pins are data bus and can drive one TTL load and
90pF capacitance respectively.
6
5
4
321
0
Bit 0, Bit 1 IRO I , IR0 2 Enable Bit (IROIE, IR0 2 E)
When using P so and PSI as interrupt pins, write "1" in
these bits. When "0", the CPU doesn't accept an external
interrupt or a sleep cancellation by the external interrupt.
These bits become "0" during reset.
Bit 2 Memory Ready Enable Bit (MRE)
Ao-A ls
These pins are address bus and can drive one TTL load and
90pF capacitance respectively.
When using P S2 as an input for Memory Ready signal, write
"1" in this bit. When "0". the memory ready function is prohibited andPs2 can be used as I/O port. This bit becomes
"1" during reset.
•
RAM/PORT 5 CONTROL REGISTER
Bit 3 Halt Enable bit (HL TEl
•
The control register located at $0014 controls on-chip
When using P S3 as an input for lIalt
si~nal.
451
$HITACHI
Hitachi America Ltd. •
2210
O'Toole Ave. • San Jose, CA 95131
write "I" in this
• (408) 435-8300
HD6303X,HD63A03X,HD63B03X----------------------------------------------bit. When "0", the halt function is prohibited and PS3 can be
used as I/O port. This bit becomes "1" during reset.
(Note) When using PS2 and PS3 as the input ports in mode 1
and 2, MRE and HLTE bit should be cleared just after
the reset.
Notice that memory ready and halt function is enable
till MRE and HLTE bit is cleared.
Vee
AD
WR
CJ
R/N
LiR
BA
Bit 4, Bit 5 Not Used.
Port 2
81/0 lines
Timer 1, 2
SCI
Port,5
Bit 6 RAM Enable (RAMEl
On-chip RAM can be disabled by this control bit. By resetting the MPU, "1" is set to this bit, and on-chip RAM is
enabled. This bit can be written "I" or "0" by software. When
RAM is in disable condition (= logic "0"), on-chip RAM is
invalid and the CPU can read data from external memory.
This bit should be "0" before getting into the standby mode to
protect on-chip RAM data.
8 Data Bus
81Rff,~~
16 Address
Bus
MAo RAIf
Port 6
81/0 lines
Bit 7 Standby Power Bit (STBY PWRI
When Vee is not provided in standby mode, this bit is
Figure 15 Operation Mode
cleared. This is a flag for both read/write by software. If this bit
is set before standby mode, and remains set even after returning
from standby mode, Vee voltage is provided during standby
mode and the on·chip RAM data is valid.
•
MEMORY MAP
The MPU can address up to 65k bytes. Fig. 16 gives memory
map of HD6303X. 32 internal registers use addresses from "00"
as shown in Table 3.
Table 3 Internal Register
Address
Registers
R/W***
00
-
-
01
Port 2 Data Direction Register
03
-
-
02*
W
Port 2
R/W
Initialize at RESET
$FC
Undefined
04*
-
-
-
05
06*
-
-
-
07*
-
-
-
08
Timer Control/Status Register 1
RIW
$00
09
Free Running Counter ("High")
RIW
$00
OA
Free Running Counter ("Low")
RIW
$00
OB
Output Compare Register 1 ("High")
RIW
$FF
OC
Output Compare Register 1 ("Low")
R/W
$FF
00
Input Capture Register ("High")
R
$00
OE
Input Capture Register ("Low")
R
$00
OF
Timer Control/Status Register 2
RIW
$10
10
Rate, Mode Control Register
R/W
$00
11
Tx/Rx Control Status Register
RIW
$20
$00
12
Receive Data Register
R
13
Transmit Data Register
W
14
RAM/Port 5 Control Register
15
Port 5
R
16
Port 6 Data Direction Register
W
RIW
$00
$7C or $FC
$00
(continued)
452
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
~~~~~~~~~~~~~~~~~~~~~~~~HD6303X,HD63A03X,HD63B03X
Table 3 Internal Register
R/W***
Initialize at RESET
R/W
-
Undefined
Output Compare Register 2 ("High")
R/W
$FF
Registers
Address
17
Port 6
-
18*
19
-
1A
Output Compare Register 2 ("Low")
R/W
$FF
18
Timer Control/Status Register 3
R/W
$20
1C
Time Constant Register
W
$FF
10
Timer 2 Up Counter
R/W
$00
1E
1F**
-
-
Test Register
-
* External Address.
** Test Register. Do not access to this· register.
* •• R
: Read Only Register
W : Write Only Register
R/W: Read/Write Register
and incremented by system clock. The counter value is readable
by software without affecting the counter. The counter is
cleared by reset.
When writing to the upper byte ($09), the CPU writes the
preset value ($FFF8) into the counter (address $09, $OA)
regardless of the write data value. But when writing to the
lower byte ($OA) after the upper byte writing, the CPU writes
not only the lower byte data into lower 8 bit, but also the
upper byte data into higher 8 bit of the FRC.
The counter will be as follows when the CPU writes to it
by double store instructions (STD, STX etc.).
HD6303X
Expanded Mode
Internal"
Registers
External
,,"~'77~~ ~ ~;a~~ry
Internal
RAM
$OOFF F""'~~'""'I ~
$09 Write
External
Memory
Space
Counter value
$OA Write
$FFF8
$5AF3
In t·he case of the CPU write ($5AF3) to the FRC
Figure 17 Counter Write Timing
$FFFFIo...-_ _ _..J,
" Excludes the following addresses
which may be used externally:
$02, $04, $06, $07, $18.
Figure 16 HD6303X Memory Map
•
TIMER 1
The HD6303X provides a l6-bit programmable timer which
can simultaneously measure an input waveform and generate
two independent output waveforms. The pulse widths of both
input/output waveforms vary from microseconds to seconds.
Timer I is configurated as follows (refer to Fig. 18).
• Control/Status Register I (8 bit)
Control/Status Register 2 (7 bit)
Free Running Counter (16 bit)
Output Compare Register I ( 16 bit)
Output Compare Register 2 (16 bit)
Input Capture Register (16 bit)
• Output Compare Register (OCR)
($0008, $OOOC; OCR1) ($0019, $001A ; OCR2)
The output compare register is a 16-bit read/write register
which can control an output waveform. The data of OCR is
always compared with the FRC.
When the data matches, output compare flag (OCF) in the
timer control/status register (TCSR) is set. If an output enable
bit (OE) in the TCSR2 is "I", an output level bit (OLVL) in
the TCSR will be output to bit I (Tout I) and bit 5 (Tout 2)
of port 2. To control the output level again by the next compare, the value of OCR and OLVL should be changed. The
OCR is set to $FFFF at reset. The compare function is inhibited
for a cycle just after a write to the OCR or to the upper byte
of the FRC. This is to begin the comparison after setting the
16-bit value valid in the register and to inhibit the compare
function at this cycle, because the CPU writes the upper byte
to the FRC, and at the next cycle the counter is set to $FFF8.
* For data write to the FRC or the OCR, 2-byte transfer
instruction (such as STX etc.) should be used.
•
•
Free-Running Counter (FRC) ($0009 : OOOA)
The key timer element is a 16-bit free-running counter driven
Input Capture Register (lCR) ($0000: OOOE)
The input capture register is a 16·hit read only register which
stores the FRC's value when external inpli t signal transition
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
453
HD6303X,HD63A03X,HD63B03X·,----------------------------------------------generates an input capture pUlse. Such transition is controlled
by input edge bit (IEDG) in the TCSRI.
In order to input the external input signal to the edge
detecter, a bit of the DDR corresponding to bit 0 of port 2
should be cleared ("0"). When an input capture pulse occurs
by the external input signal transition at the next cycle of CPU's
high-byte read of the ICR, the input capture pulse will be delayed by one cycle. In order to ensure the input capture operation, a CPU read of the ICR needs 2-byte transfer instruction.
The input pulse width should be at least 2 system cycles. This
register is cleared ($0000) during reset.
• Timer Control/Status Register 1 (TCSR 1) ($0008)
The timer control/status register 1 is an 8-bit register. All bits
are readable and the lower 5 bits are also writable. The upper 3
bits are read only which indicate the following timer status.
Bit 5 The counter value reached to $0000 as a result of
counting-up (TOF).
Bit 6 A match has occured between the FRC and the OCR 1
(OCFI).
Bit 7 Defined transition of the timer input signal causes the
counter to transfer its data to the ICR (ICF).
The followings are each bit descriptions.
Timer Control/Status Register 1
Bit 7
to the OCRI ($0008 or $OOOC) after the TCSRI or
TCSR2 read.
ICF
Input Capture Flag
This read-only bit is set when an input signal of
port 2, bit 0 makes a transition as defined by IEDG and
the FRC is transferred to the (CR. Cleared when reading
the upper byte ($OOOD) of the ICR following the
TCSRI or TCSR2 read.
• Timer Control/Status Register 2 (TCSR2) ($OOOF)
The timer control/status register 2 is a 7-bit register. All bits
are readable and the lower 4 bits are also writable. But the
upper 3 bits are read-only which indicate the following timer
status.
Bit 5 A match has occured between the FRC and the OCR2
(OCF2).
Bit 6 The same status flag as the OCFI flag of the TCSRl,
bit 6.
Bit 7 The same status flag as the ICF flag of the TCSR 1 , bit 7.
The followings are the each bit descriptions.
Timer Control/Status Register 2
76543210
ICF I OCF11 OCF21 -
IEOCI2~LVL21 OE21 O~ $OOOF
Bit 0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
OLVL 1 Output Levell
OLVLI is transferred to port 2, bit 1 when a match
occurs between the counter and the OCRl. If bit 0 of
the TCSR2 (OEI) is set to "I", OLVLl will appear at
bit 1 of port 2.
IEDG Input Edge
This bit determines which edge, rising or falling, of
input signal of port 2, bit 0 will trigger data transfer
from the counter to the ICR. For this function, the
DDR corresponding to port 2, bit 0 should be cleared
beforehand.
IEDG=O, triggered on a falling edge
("High" to "Low")
IEDG=I, triggered on a rising edge
("Low" to "High")
ETOI
Enable Timer Overflow Interrupt
When this bit is set, an internal interrupt (IRQ3) by
TO! interrupt is enabled. When cleared, the interrupt is
inhibited.
EOCll
Enable Output Compare Interrupt 1
When this bit is set, an internal interrupt (IRQ3) by
DC! I interrupt is enabled. When cleared, the interrupt
is inhibited.
EICI
Enable Input Capture Interrupt
When this bit is set, an internal interrupt (lRQ3) by
ICI interrupt is enabled. When cleared, the interrupt is
inhibited.
TOF Timer Overflow Flag
This read-only bit is set when the counter increments from $FFFF by I. Cleared when the counter's
upper byte ($0009) is ready by the CPU after the
TCSRI read.
OCFl
Output Compare Flag 1
This read-only bit is set when a match occurs between the OCRI and the FRC. Cleared when writing
454
Hitachi America Ltd. •
2210
OEl Output Enable 1
This bit enables the OLVLl to appear at port 2, bit
1 when a match has occurred between the counter and
the output compare register 1. When this bit is cleared,
bit 1 of port 2 will be an I/O port. When set, it will be
an output of OLVLI automatically.
Bit 1 OE2 Output Enable 2
This bit enables the OLVL2 to appear at port 2, bit
5 when a match has occurred between the counter and
the output compare register 2. When this bit is cleared,
port 2, bit 5 will be an I/O port. When set, it will be an
output of OLVL2 automatically.
Bit 2 OLVL2 Output Level 2
OLVL2 is transferred to port 2, bit 5 when a match
has occurred between the counter and the OCR2. If
bit 5 of the TCSR2 (OE2) is set to "1", OLVL2 will
appear at port 2, bit 5.
Bit 3 EOCI2 Enable Output Compare Interrupt 2
When this bit is set, an internal interrupt (IRQ3) by
OCI2 interrupt is enabled. When cleared, the interrupt
is inhibited.
Bit 4 Not Used
Bit 5 OCF2 Output Compare Flag 2
This read-only bit is set when a match has occurred
between the counter and the OCR2. Cleared when
writing to the OCR2 ($0019 or $OOIA) after the TCSR2
read.
Bit 6 ,OCFl Output Compare Flag 1
Bit 7 ICF Input Capture Flag
OCFI and ICF addresses are partially decoded.
The CPU read of the TCSRl/TCSR2 makes it possible
to read OCFI and ICF into bit 6 and bit 7.
Both the TCSRI and TCSR2 will be cleared during reset.
(Note) If OEI or OE2 is set to "1" before the first output
compare match occurs after reset restart, bit 1 or bit 5
of port 2 will produce "0" respectively.
~HITACHI
O'Toole Ave. • San Jose, CA 95131
• (408) 435-8300
-----------------------------------------------HD6303X,HD63A03X,HD63B03X
, Figure 18 Timer 1 Block Diagram
•
•
TIMER 2
In addition to the timer 1, the HD6303X provides an 8-bit
reloadable timer, which is capable of counting the external
event. This timer 2 contains a timer output, so the MPU can
generate three independen t waveforms (refer to Fig. 19).
The timer 2 is configured as follows:
Control/Status Register 3 (7 bit)
8-bit Up Counter
Time Constant Register (8 bit)
•
Time Constant Register (TCONR) ($001C)
The time constant register is an 8-bit write only register. It
is always compared with the counter.
When a match has occurred, counter match flag (CMF) of
the timer control status register 3 (TCSR3) is set and the value
selected by TOSO and TOSI of the TCSR3 will appear at port 2,
bit 6. When CMF is set, the counter wi\l be cleared simultane·
ously and then start counting from $00. This enables regular
interrupts and waveform outputs without any software support.
The TCONR is set to "$FF" during reset.
Timer 2 Up Counter (T2CNT) ($0010)
This is an 8-bit up counter which operates with the clock
decided by CKSO and CKS 1 of the TCSR3. The CPU can read
the value of the counter without affecting the counter. In ad·
dition, any value can be written to the counter by software
even during counting.
The counter is cleared when a match occurs between the
counter and the TCONR or during reset.
If a write operation is made by software to the counter at the
cycle of counter clear, it does not reset the counter but put the
write data to the counter.
•
Timer Control/Status Register 3 (TCSR3) ($0018)
The timer control/status register 3 is a 7-bit register. All bits
are readable and 6 bits except for eMF can be written.
The followings are each pin descriptions.
Timer Control/Status Register 3
76543210
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
455
HD6303X,HD63A03X.HD63B03X-----------------------------------------------
r - - - - Timer1 FRC
....----+-- Port 2
Bit 7
t-+----t------+-- Port 2
Bit6
Figure 19 Timer 2 Block Diagram
Bit 0
Bit 1
CKSO Input Clock Select 0
CKS1 Input Clock Select 1
Input clock to the counter is selected as shown in
Table 4 depending on these two bits. When an external
clock is selected, bit 7 of port 2 will be a clock input
automatically. Timer 2 detects the rising edge of the
external clock and increments the counter. The external
clock is countable up to half the frequency of the
system clock.
Table 4 Input Clock Select
CKS1
0
0
1
1
CKSO
0
1
0
1
456
TOS1
TOSO
0
0
1
1
0
1
0
1
Timer Output
Timer Output Inhibited
Toggle Output*
Output "0"
Output "1"
• When a match occurs between the counter and the TCONR, timer 2
output level is reversed. This leads to production of a square wave with
50% duty to the external without any software support.
Bit 4
Input Clock to the Counter
E clock
E clock/8*
E clock/128*
External clock
• These clocks come from the FRC of the timer 1. If one of these clocks
is selected as an input clock to the up counter, the CPU should not
write to the FRC of the timer 1.
Bit 2
Bit 3
Table 5 Timer 2 Output Select
TOSO Timer Output Select 0
TOSl Timer Output Select 1
When a match occurs between the counter and the
TCONR timer 2 outputs shown in Table 5 will appear at
port 2, bit 6 depending on these two bits. When both
TOSO and TOS 1 are "0", bit 6 of port 2 will be an I/O
port.
T2E Timer 2 Enable Bit
When this bit is cleared, a clock input to the up
counter is prohibited and the up counter stops. When set
to "I", a clock selected by CKS I and CKSO (Table 4)
is input to the up counter.
(Note) P26 outputs "0" when T2E bit cleared and timer 2 set
in output enable condition by TOSI or TOSO. It also
outputs "0" when T2E bit set "I" and timer 2 set in
output enable condition before the first counter match
occurs.
Bit 5 Not Used
Bit 6 ECMI Enable Counter Match Interrupt
When this bit is set, an internal interrupt (lRQ3) by
CMI is enabled. When cleared, the interrupt is inhibited.
Bit 7 CMF Counter Match Flag
This read-only bit is set when a match occurs between
the up counter and the TCONR. Cleared by writing
"0" by software write (unable to write ''l'' by software).
Each bit of the. TCSR3 is cleared during reset.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------HD6303X,HD63A03X,HD63B03X
•
SERIAL COMMUNICATION INTERFACE (SCI)
The HD6303X SCI contains two operation modes; one is an
asynchronous mode by the NRZ format and the other is a
clocked synchronous mode which transfers data synchronizing
with the serial clock.
The SCI consists of the following registers as shown in
Fig. 20 Block Diagram:
• Control/Status Register (TRCSR)
• Rate/Mode Control Register (RMCR)
• Receive Data Register (RDR)
• Receive Data Shift Register (RDSR)
• Transmit Data Register (TDR)
• Transmit Data Shift Register (TDSR)
The serial I/O hardware requires an initialization by software
for operation. The procedure is usually as follows:
1) Write a desirable operation mode into each corresponding control bit of the RMCR.
2) Write a desirable operation mode into each corresponding control bit of the TRCSR.
When using bit 3 and 4 of port 2 for serial I/O only, there is
no problem even if TE and RE bit are set. But when setting the
baud rate and operation mode, TE and RE should be "0". When
clearing TE and RE bit and setting them again, more than 1 bit
cycle of the current baud rate is necessary. If set in less than 1
bit cycle, there may be a case that the internal transmit/receive
initialization fails.
•
Asynchronous Mode
An asynchronous mode contains the following two data
formats:
I Start Bit + 8 Bit Data + I Stop Bit
1 Start Bit + 9 Bit Data + 1 Stop Bit
In addition, if the 9th bit is set to "1" when making 9
bit data format, the format of
1 Start bit + 8 Bit Data + 2 Stop Bit
is also transferred.
Data transmission is enabled by setting TE bit of the TRCSR,
then port 2, bit 4 will become a serial output independently of
the corresponding DDR.
For data transmit, both the RMCR and TRCSR should be
set under the desirable operating conditions. When TE bit is
set during this process, 10 bit preamble will be sent in 8-bit data
format and 11 bit in 9-bit data format. When the preamble is
produced, the internal synchronization will become stable and
the transmitter is ready to act.
The conditions at this stage are as follows.
1) If the TDR is empty (TDRE=I), consecutive l's are
produced to indicate the idle state.
2)
If the TDR contains data (TDRE=O), data is sent to the
transmit data shift register and data transmit starts.
During data transmit, a start bit of "0" is transmitted first.
Then 8-bit or 9-bit data (starts from bit 0) and a stop bit' "1"
are transmitted.
When the TDR is "empty", hardware sets TDRE flag bit. If
the CPU doesn't respond to the flag in proper timing (the TDRE
is in set condition till the next normal data transfer starts from
the transmit data register to the transmit sift register), "1" is
transferred instead of the start bit "0" and continues to be
transferred till data is provided to the data register. While the
TDRE is "1", "0" is not transferred.
Data receive is possible by setting RE bit. This makes port 2,
bit 3 be a serial input. The operation mode of data receive is
decided by the contents of the TRCSR and RMCR. The first
"0" (space) synchronizes the receive bit flow. Each bit of the
following data will be strobed in the middle. If a stop bit is not
"1", a framing error assumed and ORFE is set,
When a framing error occurs, receive data is transferred to
the receive data register and the CPU can read error-generating
data. This makes it possible to detect a line break.
If the stop bit is "1", data is transferred to the receive data
register and an interrupt flag RDRF is set. If RDRF is still
set when receiving the stop bit of the next data, ORFE is set to
indicate overrun generation.
When the CPU read the receive data register as a response to
RDRF flag or ORFE flag after having read TRCS, RDRF or
ORFE is cleared.
(Note) Clock Source in Asynchronous Mode
If CCI : CCO = 10, the internal bit rate clock is provided
at P22 regardless of the values for TE or RE. Maximum
clock rate is E-;.- 16.
If both CCI and CCO are set, an external TTL compatible clock must be connected to P 22 at sixteen times
(l6x) the desired bit rate, but not greater than E.
•
Clocked Synchronous Mode
In the clocked synchronous mode, data transmit is
synchronized with the clock pulse. The HD6303X SCI
provides functionally independent transmitter and receiver
which makes full duplex operation possible in the asynchronous
mode. But in the clocked synchronous mode an SCI clock I/O
pin is only P22, so the simultaneous receive and transmit
operation is not available. In this mode, TE and RE should
not be in set condition (" I") simultaneously. Fig. 21 gives a
synchronous clock and a data format in the clocked synchronous mode.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
457
HD6303X,HD63A03X,HD63B03X-----------------------------------------------
HD6303X Internal Data Bus
Transmit/Receive Control and Status Register
Tlmer1 FRC,
Tlmer2
Up Counter
Figure 20 Serial Communication Interface Block Diagram
Data transmit is realized by setting TE bit in the TRCSR.
Port 2, bit 4 becomes an output unconditionally independent
of the value of the corresponding DDR.
Both the RMCR and TRCSR should be set in the desirable
operating condition for data transmit.
When an external clock input is selected, data transmit is
<:==:===::::J
performed under the TORE flag "0" from port 2, bit 4, synchronizing with 8 clock pulses input from external to port 2,
bit 2.
Oata is transmitted from bit 0 and the TORE is set when the
transmit data shift register is "empty". More than 9th clock
pulse of external are ignored.
Transmit Direction
Synchronous
clock
Data
~NotValid
• Transmit data is output from a falling edge of a synchronous clock to the next falling edge .
• Receive data is latched at the rising edge.
Figure 21
Clocked Synchronous Mode Format
When data transmit is selected to the clock output, the MPU
produces transmit data and synchronous clock at TORE flag
clear.
Data receive is enabled by setting RE bit. Port 2, bit 3 will
be a serial input. The operating mode of data receive is decided
by the TRCSR and the RMCR.
If the external clock input is selected, RE bit should be
set when P22 is "High". Then 8 external clock pulses and
the synchronized receive data are input to port 2, bit 2
and bit 3 respectively. The MPU put receive data into the
receive data shift register by this clock and set the RDRF
flag at the termination of 8 bit data receive. More than 9th
clock pulse of external input are ignored. When RDRF is
cleared by reading the receive data register, the MPU starts
458
receiving the next data. So RORF should be cleared with P 22
"High"
When data receive is selected to the clock output, 8 synchronous clocks are output to the external by setting RE bit. So receive data should be input from external, synchronously with
this clock. When the first byte data is received, the RORF flag
is set. After the second byte, receive operation is performed and
output the synchronous clock to the external by clearing the
RDRF bit.
• Transmit/Receive Control Status Register (TRCSR) ($0011)
The TRCSR is composed of 8 bits which are all readable. Bits
o to 4 are also writable. This register is initialized to $20 during
reset. Each bit functions as follows.
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------HD6303X,HD63A03X,HD63B03X
Transmit/Receive Control Status Register
7
6
5
4
o
3
TE
Bit
°
1 wu 1$001 1
WU Wake-up
In a typical multi-processor configuration, the
software protocol provides the destination address at
the first byte of the message. In order to make uninterested MPU ignore the remaining message, a wake-up
function is available. By this, uninterested MPU can inhibit all further receive processing till the next message
starts.
Then wake-up function is triggered by consecutive
1 's with 1 frame length (10 bits for 8-bit data, 11 for
9-bit). The software protocol should provide the idle
time between messages.
By setting this bit, the MPU stops data receive till the
next message. The receive of consecutive "1" with one
frame length wakes up and clears this bit and then the
MPU restarts receive operation. However, the RE flag
should be already set before setting this bit. In the
clocked synchronous mode WU is not available, so this
bit should not be set.
Bit 1 TE Transmit Enable
When this bit is set, transmit data will appear at port
2, bit 4 after one frame preamble in asynchronous mode,
while in clocked synchronous mode it appears immediately. This is executed regardless of the value of
the corresponding DDR. When TE is cleared, the serial
I/O doesn't affect port 2, bit 4.
Bit 2 TIE Transmit Interrupt Enable
When this bit is set, an internal interrupt (lRQ3) is
enabled when TDRE (bit 5) is set. When cleared, the
interrupt is inhibited.
Bit 3 RE Receive Enable
When set, a signal is input to the receiver from port
2, bit 3 regardless of the value of the DDR. When RE
is cleared, the serial I/O doesn't affect port 2, bit 3.
Bit 4 RIE Receive Interrupt Enable
When this bit is set, an internal interrupt, IRQ3 is
enabled when RDRF (bit 7) or ORFE (bit 6) is set.
When cleared, the interrupt is inhibited.
Bit 5 TORE Transmit Data Register Empty
TDRE is set when the TDR is transferred to the
transmit data shift register in the asynchronous mode,
while in clocked synchronous mode when the TDSR is
"empty". This bit is reset by reading the TRCSR and
writing new transmit data to the transmit data register.
TDRE is set to "1" during reset.
(Note) TDRE should be cleared in the transmittable state after
the TE set.
Bit 6 ORFE Overrun Framing Error
ORFE is set by hardware when an overrun or a framing error is generated (during data receive only). An
overrun error occurs when new receive data is ready to
be transferred to the RDR during RDRF still being set.
A framing error occurs when a stop bit is "0". But in
clocked synchronous mode, this bit is not affected. This
bit is cleared when reading the TRCSR, then the RDR,
or during reset.
Bit 7 RDRF Receive Data Register Full
RDRF is set by hardware when the RDSR is transferred to the RDR. Cleared when reading the TRCSR, then
the RDR, or during reset.
(Note) When a few bits are set between bit 5 to bit 7 in the
TRCSR, a read of the TRCSR is sufficient for clearing
those bits. It is not necessary to read the TRCSR everytime to clear each bit.
• Transmit Rate/Mode Control Register (RMeR)
The RMCR controls the following serial I/O:
• Baud Rate
• Clock Source
• Data Format
• Port 2, Bit 2 Function
In addition, if 9-bit data format is set in the asynchronous
mode, the 9th bit is put in this register. All bits are readable and
writable except bit 7 (read only). This register is set to $OC
during reset.
Transfer Rate/Mode Control Register
76543210
IROsl TOsl SS21 ee21 eel Iceo ISS1 1sso 1$0010
°
Bit
Bit 1
Bit 5
SSG}
SSl
SS2
Speed Select
These bits control the baud rate used for the SCI. Table
6 lists the available baud rates. The timer 1 FRC (SS2=0) and
the timer 2 up counter (SS2= I) provide the internal clock to the
SCI. When selecting the timer 2 as a baud rate source, it functions as a baud rate generator. The timer 2 generates the baud
rate listed in Table 7 depending on the value of the TCONR.
(Note) When operating the SCI with internal clock, do not
perform write operation 10 the timer/counter which is
the clock source of the SCI.
Bit 2
Bit 3
Bit 4
CCO}
CCl
CC2
Clock Control/Format Select*
These bits control the data format and the clock source
(refer to Table 8).
* CCO, CC I and CC2 are cleared during reset and the MPU
goes to the clocked synchronous mode of the external
clock operation. Then the MPU sets port 2, bit 2 into
the clock input state. When using port 2, bit 2 as an
output port, the DDR of port 2 should be set to "I" and
CC 1 and CCO to "0" and "1" respectively.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
459
HD6303X,HD63A03X,HD63B03X----------------------------------------------Table 6 SCI Bit Times and Transfer Rates
(1) Asynchronous Mode
SS2
SS1
SSO
0
0
0
0
0
0
1
XTAL
2.4576MHz
4.0MHz
E
614.4kHz
1.0MHz
4.9152MHz
1.2288MHz
E-';-16
26.us/38400Baud
16.us/62500Baud
13.us/76800Baud
1
E-';-128
208.u s/4800Baud
128.us/7812.5Baud
104.2.us/9600Baud
0
E-';-1024
1.67ms/600Baud
1.024ms/976.6Baud
833.3.us/1200Baud
3.333ms/300Baud
0
1
1
E-';-4096
6.67ms/150Baud
4.096ms/244.1 Baud
1
-
-
-
*
*
*
* When SS2 is "1", Timer 2 provides SCI clocks. The baud rate is shown as follows with the
f
32 (N+l)
Baud Rate
(
TCONR as N.
f: i~put clock frequency to the)
timer 2 counter
N = 0 - 255
(2) Clocked Synchronous Mode *
XTAL
S52
S51
SSO
0
0
0
E
E-.;-2
0
0
1
E-';-16
0
1
0
0
1
1
1
-
4.0MHz
6.0MHz
8.0MHz
1.0MHz
1.5MHz
2.0MHz
2.u s/ bit
16.us/bit
1.33.u s/ bit
10.7.u s / bit
E-';-128
128.us/bit
E-';-512
5 12.us/bit
85.3.u s / bit
341.u s / bit
256.us/bit
**
**
**
-
-
1.us/bit
8.u s/ bit
64,us/bit
* Bit rates in the case of internal clock operation. In the case of external clock operation, the external clock is
operatable up to DC - 1/2 system clock.
** The bit rate is shown as follows with the TCONR as N.
Bit Rate (JIs/bit) = 4
(~+ 1)
(
f: i~put clock frequency to the)
timer 2 counter
N=O-255
Table 7 Baud Rate and Time Constant Register Example
:~L
2.4576MHz
3.6864MHz
4.0MHz
4.9152MHz
80MHz
110
150
300
600
1200
2400
4800
9600
19200
38400
21"
127
63
31
15
7
3
1
0
-
32"
191
95
47
23
11
5
2
35"
207
103
51
25
12
70"
51"
207
103
51
25
12
-
-
-
-
43"
255
127
63
31
15
7
3
1
0
Baud Rate (Baud
* E/8 clock
460
-
-
-
-
is input to the timer 2 up counter and E clock otherwise.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------HD6303X,HD63A03X,HD63B03X
Table 8
SCI Format and Clock Source Control
CC2
CCl
CCO
Format
Mode
Clock Source
Port 2, Bit 2
0
0
0
0
0
0
0
8-bit data
Clocked Synchronous
External
Input
1
8-bit data
Asynchronous
Internal
Not Used**
1
0
8-bit data
Asynchronous
Internal
Output*
1
1
8-bit data
Asynchronous
External
Input
1
0
8-bit data
Clocked Synchronous
Internal
Output
1
0
0
1
9-bit data
Asynchronous
Internal
Not Used**
1
1
0
9-bit data
Asynchronous
Internal
Output*
1
1
1
9-bit data
Asynchronous
External
Input
Port 2, Bit 3
I
Port 2, Bit 4
When the TRCSR, RE bit is "1",
bit 3 is used as a serial input.
When the TRCSR, TE bit is "1",
bit 4 is used as a serial output.
* Clock output regardless of the TRCSR, bit RE and TE.
** Not used for the SCI.
Bit 6
TD8
Transmit Data Bit 8
When selecting 9-bit data format in the asynchronoU's mode, this bit is transmitted as the 9th data. In
transmitting 9-bit data, write the 9th data into this bit
then write data to the receive data register.
Bit 7
RD8
Receive Data Bit 8
When selecting 9-bit data format in the asynchronous
mode, this bit stores the 9th bit data. In receiving 9-bit
data, read this bit then the receive data register.
• TIMER, SCI STATUS FLAG
flag in the timer 1, timer 2 and SCI.
As for Timer 1 and Timer 2 status flag, if the set and reset
condition occur simultaneously, the set condition is prior to
the reset condition. But in case of SCI control status flag,
the reset condition has priority. Especially as for OCFl and
OCF2 of Timer 1, the set signal is generated periodically whenever FRC matches OCR after the set, and which can cause the
unclear of the flag. To clear surely, the method is necessary to
avoid the occurence of the set signal between TCSR Read and
OCR write. For example, match the OCR value to FRC first,
and next read TCSR, and then write OCR at once .
Table 9 shows the, set and reset conditions of each status
Table 9
Timer 1, Timer 2 and SCI Status Flag
Set Condition
Timer
1
Timer
2
Reset Condition
ICF
FRC -+ ICR by edge input to P 20 •
OCFl
OCR1=FRC
OCF2
OCR2=FRC
2.
Read the TCSR2 then write to the OCR2H or
OCR2L, when OCF2=1
RES=O
TOF
FRC=$FFFF+l cycle
1.
2.
Read the TCSRl then FRCH, when TOF-l
RES=O
CMF
T2CNT=TCON R
1.
2.
Write "a" to CMF, when CMF=l
RES =a
RDRF
Receive Shift Register -+ RDR
1.
Read the TCSRl or TCSR2 then ICRH,
when ICF= 1
2.
RES =0
1.
Read the TCSRl or TCSR2 then write to the
OCR1H orOCR1L,when OCF1=1
RES=O
2.
ORFE
1.
2.
SCI
TDRE
1.
2.
3.
1.
1.
Read the TRCSR then RDR, when RDRF-l
2.
RES =a
Framing Error (Asynchronous Mode)
Stop Bit = 0
Overrun Error (Asynchronous Mode)
Receive Shift Register -+ RDR when
RDRF=l
1.
2.
Read theTRCSR then RDR,when ORFE-l
RES=O
Asynchronous Mode
TDR -+ Transmit Shift Register
Clocked Synchronous Mode
Transmit Shift Register is "empty"
RES = a
Read the TRCSR then write to the TDR,
when TDRE= 1
(Note) TD R E shou Id be reset after the TE set.
(Note) 1. -+ ; transfer
2. For example; "ICRH" means High byte of ICR.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
461
HD6303X,HD63A03X,HD63B03X----------------------------------------------•
for a system with no need of the HD6303X's consecutive
operation.
LOW POWER DISSIPATION MODE
The HD6303X provides two low power dissipation modes;
sleep and standby.
•
•
The MPU goes to the sleep mode by SLP instruction execution. In the sleep lJlode, the CPU stops its operation, while the
registers' contents are retained. In this mode, the peripherals
except the CPU such as timers, SCI etc. continue their functions. The power dissipation of sleep-condition is one fifth that
of operating condition.
The MPU returns from this mode by an interrupt, RES or
STBY; it goes to the reset state by RES and the standby mode
by STBY. When the CPU acknowledges an interrupt request, it
cancels the sleep mode, returns to the operation mode and
branches to the interrupt routine. When the CPU masks this
interrupt, it cancels the sleep mode and executes the next
instruction. However, for example if the timer 1 or 2 prohibits
a timer interrupt, the CPU doesn't cancel the sleep mode because of no interrupt request.
This sleep mode is effective to reduce the power dissipation
Vee
~NMIII-
Standby Mode
The HD6303X stops all the clocks and goes to the reset
state with STBY"Low". In this mode, the power dissipation is
reduced conspicuously. All pins except for the power supply,
the STBY and XT AL are detached from the MPU internally
and go to the high impedance state.
In this mode the power is supplied to the HD6303X, so
the contents of RAM is retained. The MPU returns from this
mode during reset. The followings are typical usage of this
mode.
Save the CPU information and SP contents on RAM by NMI.
Then disable the RAME bit of the RAM control register and set
the STBY PWR bit to go to the standby mode. If the STBY
PWR bit is still set at reset start, that indicates the power is
supplied to the MPU and RAM contents are retained properly.
So system can restore itself by returning their pre-standby informations to the SP and the CPU. Fig. 22 depicts the timing 'at
each pin with this example.
Sleep Mode
_____
""",,~~
I
OJ NMI
I
I
HD6303X
I
flUl'-llIIl
-~j \---~----il
I
I
I
r:-:
(
~I~------------~J~
111111
I
I
I
~
Save registers
RAM/Port 5 Control
Register Set
Figure 22
•
TRAP FUNCTION
Op Code Error
When fetching an undefined op code, the CPU saves CPU
registers as well as a normal interrupt and branches to the TRAP
($FFEE, $FFEF). This has the priority next to reset.
• Address Error
When an instruction fetch is made from internal register
($0000-5001 F), the MPU generates an interrupt as well as an
op code error. But on the system with no memory in its external memory area, this function is not applicable if an instruction fetch is made from the external non-memory area.
462
' Oscillator
Start Time
~
Restart
Standby Mode Timing
The CPU generates an interrupt with the highest priority
(TRAP) when fetching an undefined instruction or an instruction from non-memory space. The TRAP prevents the systemburst caused by noise or a program error.
•
I
~
This function is available only for an instruction fetch and
is not applicable to the access of normal data read/write.
(Note) The TRAP interrupt provides a retry function differently from other interrupts. This is a program flow return
to the address where the TRAP occurs when a sequence
returns to a main routine from the TRAP interrupt
routine by RTf. The retry can prevent the system burst
caused by noise etc.
However, if another TRAP occurs, the program repeats
the TRAP interrupt forever, so the consideration is
necessary in programming .
•
INSTRUCTION SET
The HD6303X provides object code upward compatible
with the HD680 I to utilize all instruction' set of the
HMCS6800. It also reduces the execution times of key instruc-
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------HD6303X,HD63A03X,HD63B03X
tions for throughput improvement.
Bit manipulation instruction, change instruction of the
index register and accumulator and sleep instruction are also
added.
The followings are explained here.
CPU Programming Model (refer to Fig. 23)
Addressing Mode
Accumulator and Memory Manipulation Instruction
(refer to Table 10)
• New Instruction
• Index Register and Stack Manipulation Instruction
(refer to Table II)
• Jump and Branch Instruction (refer to Table 12)
• Condition Code Register Manipulation
(refer to Table 13)
• Op Code Map (refer to Table 14)
•
Programming Model
Fig. 23 depicts the HD6303X programming model. The
double accumulator D consists of accumulator A and B, so
when using the accumulator D, the contents of A and Bare
destroyed.
r----A- ___o~g
1S
8·8"A«umul ..... A.nd8
D o O r 16·8" Double Accumulator 0
01
,
11
SP
01
Stack POinter ISPI
ol
Program Count •• (PCI
L.115_ _ _ _ _ _ _ _ _ _ _.....
1
lrodn Reglstet' DO
0
H
I
PI.!
Z
V C
CondItIO'" Code Reg,Uef ICCRI
C.ry/BOHOYV from MS9
Overflow
Z.ro
Negative
Interrupt
Half Carry IFrom 8.t 31
In this addressing mode, the second byte of an instruction shows the address where a data is stored. 256 bytes ($0
through $255) can be addressed directly. Execution times
can be reduced by storing data in this area so it is recommended
to make it RAM for users' data area in configurating a system.
This is a 2-byte instruction, while 3-byte with regard to AIM,
OIM, ElM and TIM.
Extended Addressing
In this mode, the second byte shows the upper 8 bit of the
data stored address and the third byte the lower 8 bit. This
indicates the absolute address of 3-byte instruction in the
memory.
Indexed Addressing
The second byte of an instruction and the lower 8 bit of the
index register are added in this mode. As for AIM, OIM, ElM
and TIM, the third byte of an instruction and the lower 8 bits
of the index register are added.
This carry is added to the upper 8 bit of the index register
and the result is used for addressing the memory. The modified
address is retained in the temporary address register, so the contents of the index register doesn't change. This is a 2-byte
instruction except AIM, aIM, ElM and TIM (3-byte instruction).
Implied Addressing
An instruction itself specifies the address. That is, the
instruction addresses a stack pointer, index register etc. This is a
one-byte instruction.
Relative Addressing
The second byte of an instruction and the lower 8 bits of
the program counter are added. The carry or borrow is added to
the upper 8 bit. So addressing from -126 to + 129 byte of the
current instruction is enabled. This is a 2-byte instruction.
(Note) CLI, SEI Instructions and Interrupt Operation
When accepting the IRQ at a preset timing with CLI
and SEI instructions, more than 2 cycles are necessary between the CLI and SEI instructions. For example,
the following program (a) (b) don't accept the IRQ but
(c) accepts it.
Figure 23 CPU Programming Model
•
CPU Addressing Mode
The HD6303X provides 7 addressing modes. The addressing
mode is decided by an instruction type and code. Table 10
through 14 show addressing modes of each instruction with
the execution times counted by the machine cycle.
When the clock frequency is 4 MHz, the machine cycle time
becomes microsecond~ directly.
Accumulator (ACCX) Addressing
Only an accumulator is addressed and the accumulator A or
B is selected. This is a one-byte instruction.
Immediate Addressing
This addressing locates a data in the second byte of an
instruction. However, LDS and LDX locate a data in the second
and third byte exceptionally. This addressing is a 2 or 3-byte
instruction.
Direct Addressing
CLI
SEI
CLI
NOP
SEI
CLI
Nap
Nap
SEI
(a)
(b)
(c)
The same thing can be said to the TAP instruction
instead of the CLI and SEI instructions.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
463
HD6303X,HD63A03X,HD63B03X----------------------------------------------Table 10 Accumulator, Memory Manipulation Instructions
Condition Code
Addressing Modes
Mnemonic
Operations
DIRECT
IMMED
Register
EXTEND
INDEX
IMPLIED
-
#
OP
-
#
OP
-
#
OP
-
#
ADDA
8B
2
2
9B
3
2
AB
4
2
BB
4
3
A +M-A
ADDB
CB
2
2
DB
3
2
EB
4
2
FB
4
3
B+M-B
Add Double
AOOO
C3
3
3
03
4
2
E3
5
2
F3
5
3
A: B + M: M+l-A:B
Add Accumulators
ABA
Add With Carry
AOCA
OP
lB
89
2
2
99
3
2
A9
4
2
B9
4
3
-
Arithmetic Operation
OP
Add
1
#
1
A + B- A
A+M+C-A
ADCB
C9
2
2
09
3
2
E9
4
2
F9
4
3
B+M+C-B
AND
ANOA
84
2
2
94
3
2
A4
4
2
B4
4
3
A·M-A
ANDB
C4
2
2
04
3
2
E4
4
2
F4
4
3
B·M-B
Bit Test
BIT A
85
2
2
95
3
2
A5
4
2
B5
4
3
A·M
BIT B
C5
2
2
05
3
2
E5
4
2
F5
4
3
B·M
6F
5
2
7F
5
3
CLR
Clear
Compare
1
1 00 - A
CLRB
5F
1
1 00 - B
81
2
2
91
3
2
Al
4
2
Bl
4
3
A-M
CMP8
Cl
2
2
01
3
2
El
4
2
Fl
4
3
8-M
63
6
2
73
6
3
C8A
Complement, l's
COM
INegatel
1
1
A -A
53
1
1
B -8
60
NEG
6
2
70
6
19
6
4
2
B8
4
3
EORB
CB
2
2
08
3
2
E8
4
2
F8
4
3
B G M- B
3
M+l-M
Pull Data
Rotate Left
2
4
3
M-A
LDAA
86
2
2
96
3
2
LDAB
C6
2
2
06
3
2
E6
4
2
F6
4
3
M - B
LDD
CC
3
3
DC
4
2
EC
5
2
FC
5
3
M + 1 - B, M- A
8A
2
2
9A
3
2
AA 4
2
BA
4
3
A+M-A
2
FA
4
3
B +M- B
ORAB
Push Data
CA
2
2
DA 3
2
EA
4
7 1 AxB-A:B
PSHA
36
4
1
A - Msp, SP - 1 - SP
PSHB
37
4
1
B - Msp. SP - 1 - SP
PULA
32
3
1
SP + 1 - SP, Msp - A
PULB
33
3
1
SP + 1 - SP, Msp - B
49
1
1
ROL
69
6
2
79
6
3
ROLA
59
1
1
RORA
46
1
1
RORB
56
1
1
ROLB
Rotate Right
A +1- A
B + 1- B
B6
A6
3D
ROR
66
6
2
76
6
3
(Note) Condition Code Register will be explained in Note of Table 13,
I
I
I
I
I
I
I
I
R
I
I
R
I
I
R
R
S R R
R
S
R R
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
R
5
R
5
I
I
I
R
5
I
(!)~
R
A8
ORAA
I
I
2
MUL
I
I
3
OR, InclUSIve
:
Ii) •
98
Multiply Unsigned
I
I
I
2
1
I
I
AG M-A
2
1
I
I
88
1
I
I
EORA
1
I
I
I
A-I - A
4C
I
I
B-1 - B
5C
I
Ii) •
1
4
I
I
I
I
1
INCB
I
I
I
1
6
I
I
I
1
7C
I
I
··
· ··
··
·· ·· ··
·· ·· ··
··· ···
·· ··
··· ···
··· ···
·· ··
·· ··
··· ··· ··
·· ··
·· ·· ·
·· ·· ··
·· ·· · · ·
·· ·· · · · ··
··· ··· ··· ··· ··· ···
··· ···
IJ · ·
·· ··
I
4A
2
I
I
M -1-M
5A
6
I
(!)~
DECB
6C
0
(!)rll
DECA
INCA
Accumulator
2 1
3
1
V C
I
1 oo-B-B
7A
2
I
1 OO-A-A
1
2
3
N Z
I
1
6
I
I
40
50
6A
H
Converts bonary add of BCD
characters into BCD format
NEGA
INC
Load Double
OO-M-M
3
NEGB
DAA
Accumulator
A-8
M-M
43
DEC
Load
1
COMB
Decimal Adjust, A
Increment
1
COMA
Decrement
Exclusive OR
11
4
I R
R S R R
00- M
4F
CMPA
5
I
CLRA
Compare
Accumulators
Complement,2's
464
Boolean/
IIIII I ~
~) l;[};i
I
C b1
IIIIII
B
C
b1
R
I
I
I
I
I
I
I
I
A
I
I
R
(5) •
(5) •
G> •
R
• (i)
:l~'
B
(j) •
I
I
a>
bO
bO
I
I
R
I
I
R
I
I
I
I
I
~
I
I
I
I
I
I
I
I
- X H
SP + 1- SP,MIP - XL
Exchange
XGDX
18
2
1
ACCD· ·IX
3
M- XH.IM+ 1)- Xl_
M- SP H ,IM+1)-SP l
X H - M, Xl - 1M + 1)
SP H - M, SP l - 1M + 11
5 4
3 2
1 0
H
N Z
V
:
:
I
C
l
·· ··· · ·
··· ··· ··· ·· ······
l
l
l
··· ···
··· ·· ·· ·· ·· ···
·· ·· ·· ·· ·· ··
·• · · · · ·•
.ct>
.ct>
.ct>
'0
l
l
l
l
R
R
R
R
••••
(Note) Condition Code Register will be explained in Note of Table 13.
466
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------HD6303X,HD63A03X,HD63B03X
Table 12 Jump, Branch Instructions
Condition Code
Register
Addressing Modes
Operations
Mnemonic
RELATIVE
DIRECT
IMPLIED
OP
OP
-
Branch Test
-
#
20
3
2
None
3
2
None
3
2
C=O
3
2
C=1
3
2
#
OP
-
EXTEND
OP
OP
-
INDEX
#
#
-
H
#
Branch Always
BRA
Branch Never
BRN
21
Branch If Carry Clear
BCC
24
Branch If Carry Set
BCS
25
Branch If = Zero
BEQ
27
Branch If ;. Zero
BGE
2C
N
> Zero
BGT
2E
Z + (N
Branch If Higher
BHI
22
C+Z=O
Branch If " Zero
BlE
2F
3
2
Z + (N
Branch If lower Or
Same
BlS
23
3
2
C+Z =1
Branch If
< Zero
<±l
ill
ill
C
V) = 1
20
3
2
NGlV=1
2B
3
2
N = 1
Branch If Not Equal
Zero
BNE
26
3
2
Z=O
Branch If Overflow
Clear
BVC
2B
3
2
Branch If Overflow Set
BVS
29
3
V-I
Branch If Plus
BPL
2A
3
N=O
Branch To Subroutine
BSR
80
5 2
Jump
JMP
Jump To Subroutine
JSR
No Operation
NOP
01
Return From Interrupt
RT!
3B 10 1
RTS
39
5
Software Interrupt
SWI
3F
12 1
Wait for Interrupt-
WAI
SLP
3E
9
lA
4
::>Ieep
V
V) = 0
BMI
Retum From
N Z
V =0
BlT
Subroutine
I
Z =1
Branch If Minus
Branch If
543210
V=O
3
2
7E
3
3
AD 5
2
BD
6
3
6E
90
5
2
1 1
Advances Prog. Cntr.
Only
-(j)-
1
•
5 ••
••••••
(Note) • WAI puts R/W high; Address Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of Table 13.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
467
HD6303X,HD63A03X,HD63B03X-----------------------Table 13 Condition Code Register Manipulation Instructions
IAddressingModl!!
Operations
Condition Code Aegister
Boolean Operation
IMPLIED
Mnemonic
OP
-
#
ClC
OC
1
1
CI •• r Interrupt Mask
CLI
OE
1
1
0 .... 1
CI•• r Overflow
ClV
OA
1
1
Set Carry
SEC
00
1
1
0"" V
1 .... C
Set Interrupt M.sk
SEI
OF
1
1
1 .... 1
Set Owrflow
SEV
OB
1
Accumulator A .... CCA
TAP
06
1
1
A .... CCA
CCA .... Accumulator A
TPA
07
1
1
CCA .... A
CI •• r Carry
N
2
Z
0
1
V
C
A
A
S
S
S
---@---
CONDITION CODE SYMBOLS
OP
Operation Code (Hexadecimal)
Number of MCU Cycles
MSp Contents of memory location pointed to by Stack Pointer
#
Number of Program Bytes
Arithmetic Plus
Arithmetic Minus
Boolean AND
+ Boolean Inclusive OR
t»
Boolean Exclusive OR
M Complement of M
Transfer into
OBit = Zero
00 Byte = Zero
(Note)
3
I
A
I .... V
LEGEND
4
H
··· ·· ··· ··· ·· ··
··· ·· ··· ··· ·· ··
······
O .... C
1
5
H
I
N
Z
V
C
R
S
Half-carry from bit 3 to bit 4
Interrupt mask
Negative (sign bid
Zero (byte)
Overflow, 2's complement
Carry/Borrow from/to bit 7
Reset Always
Set Always
Set if true after test or clear
Not Affected
t
•
Condition Code Register Notes: (Bit set if test is true and cleared otherwise)
(j)
(2'\
(3)
(.I)
'5'
(Bit V)
(Bit C)
Test: Result = 100oo000?
Test: Result ~ OOOOOOOO?
(Bit C)
(Bit V)
(Bit V)
Test:
Test:
Test:
Test:
(Bit V)
(Bit N)
6'
7,
(8)
(9;
(iO)
(i1)
BCD Character of high-order byte greater than 10? (Not cleared if previously set)
Operand = 10000000 prior to execution?
Operand = 01111111 prior to execution?
Set equal to N~ C = 1 after the execution of instructions
(All Bid
(Bit I)
Test: Result less than zero? (Bit 15=1)
Load Condition Code Register from Stack.
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the wait state.
(All Sit)
(Sit C)
Set according to the contents of Accumulator A.
Result of Multiplication Bit 7=1? (ACCS)
Table 14 OP-Code Map
OP
ACC
ACC
CODE
A
B
~ --00000
LO
0000
0
0001
1
0010
2
0011
S
4
NOP
0001
f-1
0010
2
0011
3
SBA
BRA
TSX
CBA
BRN
INS
BHl
PULA
BLS
PULB
BCC
DES
0101
5
BCS
TXS
0110
6
-----~
---------------..----------TAP
TAB
BNE
PSHA
0111
7
TPA
TBA
BEQ
PSHB
1000
8
INX
XGDX
BVC
PULX
0100
LSRD
ASLD
1001
9
DEX
DAA
BVS
RTS
1010
A
CLV
SLP
BPL
ABX
1011
B
SEV
ABA
BMI
RTI
1100
C
CLC
~
BGE
PSHX
1101
0
SEC
1110
E
CLI
1111
F
SEI
0
~
-----1
------
'UNDEFINED OP CODE
BLT
MUL
BGT
WAI
BLE
SWI
2
3
0100
4
-
DIR
0110
0101
---~
6
5
-------
I
l%~tl00l
I
ACCA or SP
IND
IMM
DIR
0111
1-----
7
8
4
A
IMM
I .1011
I B
1100
C
I
I
I
DIR
1101
0
liND
I
I
1110
E
I EXT
I 1111
I F
0
AIM
CMP
1
OIM
SBC
2
ADDD
SUBD
LSR
ElM
AND
3
4
BIT
5
______ I
LOA
ROR
~l
ASR
6
STA
STA
7
ASL
EOR
ROL
ADC.
9
DEC
ORA
A
TIM
8
ADD
B
CPX
INC
TST
BSR
I
~I
7
8
I
I
0
LOX
~
STS
9
C
STD
LOS
~I
6
LDD
JSR
JMP
CLR
5
I
9
EXT
SUB
~
------
1010
ACCB or X
I
NEG
COM
-------
liND
A
I
B
C
I
E
STX
0
I
E
F
I
F
~
• Only each instructions of AIM, OIM, ElM, TIM
468
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
~~~~~~~~~~~~~~~~~~~~~~~~-HD6303X,HD63A03X,HD63B03X
• CPU OPERATION
• CPU Instruction Flow
When operating, the CPU fetches an instruction from a
memory and executes the required function. This sequence
starts with RES cancel and repeats itself limitlessly if not
affected by a special instruction or a control signal. SWI, RTI,
WAI and SLP instructions change this operation, while NMI,
IRQ1, IRQ2, IRQ3, HALT and STBY control it. Fig. 24 gives
the CPU mode transition and Fig. 25 the CPU system flow
chart. Table 15 shows CPU operating states and port states.
•
Operation at Each Instruction Cycle
Table 16 shows the operation at each instruction cycle.
By the pipeline control of the HD6303X, MULT, PUL, DAA
and XGDX instructions etc. pre fetch the next instruction. So
attention is necessary to the counting of the instruction cycles
because it is different from the usual one ------ op code fetch
to the next instruction op code.
Table 15 CPU Operation State and Port State
Port
Reset
STBY***
HALT
Ao -A 7
H
T
T
H
Port 2
T
T
Keep
Keep
Do - D7
As -A 15
T
T
T
T
H
T
T
H
Port 5
T
T
T
T
Port 6
T
T
Keep
Keep
Control
Signal
*
T
**
*
H ; High,
L; Low,
Sleep
Figure 24 CPU Operation Mode Transition
T; High Impedance
• RD, WR, R/W, DR = H, SA
RD, WR, R/iN = T, DR, SA
=L
=H
••• E pin goes to high impedance state.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
469
~
o
I
o
a>
~
eN
X
J:
oa>
eN
»
o
I
s:
eN
(')
X
=:l:-
"':::t:
o
3
a>
~
eN
CD
o·
(Note)
III
r
p:
•
2. Refer to "FUNCTIONAL PIN DESCRIPTION" for more
details of interrupts.
I\)
I\)
<5
o
oi
~~
~:I
.CD
-
~
• :J>
CJ)C')
~
:I
C"-
oen
~
()
:l:<0
~
~
•
~
o
$
~
(J.)
(J1
00
(J.)
o
o
1. The program sequence will com~o the RES start from
any place of the flow during RES. When STBY=O, the
sequence will go into the standby mode regardless of the CPU
condition.
Figure 25 HD6303X System Flow Chart
o
eN
X
------------------------HD6303X,HD63A03X,HD63B03X
Table 16 Cycle-by-Cycle Operation
Address Mode &
Instructions
IMMEDIATE
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
ADDD CPX
LDD
LOS
LOX
SUBD
DIRECT
ADC
AND
CMP
LOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
Address Bus
CPX
LOS
SUBD
STD
STX
STS
1
2
Op Code Address + 1
Op Code Address + 2
1
1
0
0
1
1
1
2
3
Op Code Address+ 1
Op Code Address + 2
Op Code Address + 3
1
1
1
0
0
0
1
1
1
0
1
Op Code Address + 1
Address of Operand
Op Code Address+ 2
1
1
1
0
0
0
1
1
1
0
3
2
3
4
3
1
2
3
1
2
3
4
4
1
2
3
4
JSR
5
1
2
3
4
5
TIM
4
AIM
OIM
1
0
Operand Data
Next Op Code
2
3
ADDD
LDD
LOX
Data Bus
1
2
3
4
1
ElM
6
2
3
4
5
6
Op Code Address + 1
Destination Address
Op Code Address + 2
Op Code Address+ 1
Address of Operand
Address of Operand + 1
Op Code Address+2
Op Code Address + 1
Destination Address
Destination Address+ 1
Op Code Address + 2
Op Code Address+ 1
FFFF
Stack POinter
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Op Code Address + 3
Op Code Address+ 1
Op Code Address + 2
Address of Operand
FFFF
Address of Operand
Op Code Address + 3
1
0
1
0
1
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
0
1
1
0
1
1
1
1
1
1
0
1
0
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Address of Operand (LSB)
Operand Data
Next Op Code
Destination Address
Accumulator Data
Next Op Code
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
471
Address Mode &
Instructions
Address Bus
INDEXED
JMP
3
ADC
AND
CMP
LOA
SBC
TST
STA
ADD
BIT
EOR
ORA
SUB
4
4
1
2
3
1
2
3
4
1
2
3
4
ADDD
CPX
LOS
SUBD
STD
STX
LDD
LOX
5
1
2
3
4
5
STS
5
1
2
3
4
5
JSR
5
1
2
3
4
5
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
TIM
5
1
2
3
4
5
6
1
2
3
4
5
CLR
5
1
2
3
4
5
AIM
OIM
ElM
1
2
3
7
4
5
6
7
Data Bus
Op Code Address+ 1
FFFF
Jump Address
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address + 2
1
1
1
1
1
1
1
0
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address + 2
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address+2
Op Code Address+ 1
FFFF
IX+Offset
IX + Offset + 1
Op Code Address+2
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
IX + Offset
Op Code Address+ 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+ 2
Op Code Address+ 1
Op Code Address+2
FFFF
IX + Offset
Op Code Address+3
Op Code Address + 1
FFFF
IX + Offset
IX + Offset
Op Code Address+2
Op Code Address+ 1
Op Code Address+2
FFFF
IX+Offset
FFFF
IX + Offset
Op Code Address+3
1
1
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
1
0
0
1
0
0
1
1
0
0
1
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
0
1
0
1
0
Offset
Restart Address (LSB)
First Op Code of Jump Routine
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data
00
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operal'\d'l>ata
Next Op Code
(Continued)
472
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
~~~~~~~~~~~~~~~~~~~~~~~~-HD6303X,HD63A03X,HD63B03X
Address Mode &
Instructions
Address Bus
Data Bus
EXTEND
JMP
3
ADC
AND
CMP
lOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
TST
4
1
2
3
1
2
3
4
4
1
2
3
4
ADDD
CPX
lOS
SUBD
lDD
lOX
5
1
2
3
4
5
STD
STX
STS
5
1
2
3
4
5
JSR
6
1
2
3
4
5
6
ASl
COM
INC
NEG
ROR
ASR
DEC
lSR
ROl
6
1
2
3
4
5
6
ClR
5
1
2
3
4
5
Op Code Address+ 1
Op Code Address+2
Jump Address
Op Code Address+ 1
Op Code Address + 2
Address of Operand
Op Code Address + 3
Op Code Address + 1
Op Code Add, ess + 2
Destination Address
Op Code Address + 3
Op Code Address+ 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Destination Address
Destination Address+ 1
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
FFFF
Stack Pointer
Stack Pointer-l
Jump Address
Op Code Address+ 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
pp Code Address+3
Op Code Address+ 1
Op Code Address+2
Address of Operand
Address of Operand
Op Code Address+3
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
0
Jump Address (MSB)
Jump Address (lSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data
Next Op Code
Destination Address (MSB)
Destination Address (lSB)
Accumulator Data
Next Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data (MSB)
Operand Data (lSB)
Next Op Code
Destination Address (MSB)
Destination Address (lSB)
Register Data (MSB)
Register Data (lSB)
Next Op Code
Jump Address (MSB)
Jump Address (lSB)
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data
Restart Address (lSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data
00
Next Op Code
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
473
Address Mode &
Instructions
IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
PULA
ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
LSR
R(!)L
NOP
SEC
SEV
TAP
TPA
TSX
XGDX
Address Bus
1
Op Code Address + 1
1
0
1
0
Next Op Code
1
2
1
2
Op Code Address + 1
FFFF
Op Code Address+ 1
FFFF
Stack Pointer + 1
Op Code Address+ 1
FFFF
Stack Pointer
Op Code Address+ 1
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Op Code Address + 1
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Return Address
Op Code Address + 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
Next Op Code
Restart Address (LSB)
Next Op Code
Restart Address (LSB)
Data from Stack
Next Op Code
Restart Address (LSB)
Accumulator Data
Next Op Code
Next Op Code
Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSB)
Next Op Code
Restart Address (LSB)
Index Register (LSB)
Index Register (MSB)
Next Op Code
Next Op Code
Restart Address (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
1
2
PULB
3
3
PSHA
Data Bus
PSHB
4
PULX
4
1
2
3
4
1
2
3
4
1
2
PSHX
5
3
4
5
1
2
RTS
5
MUL
3
4
5
1
2
7
3
4
5
6
7
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
0
0
1
0
0
0
1
1
1
0
0
1
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
0
u
1
1
1
1
1
1
(Continued)
474
_HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
Address Mode &
Instructions
Data Bus
Address Bus
IMPLIED
WAI
9
1
2
3
4
5
6
7
8
9
RTI
10
1
2
3
4
5
6
7
8
9
SWI
12
10
1
2
3
4
5
6
7
8
9
10
11
12
1
2
SlP
4
Op Code Address+ 1
FFFF
Stack Pointer
Star.k Pointer-1
Stack Pointer - 2
Stack Pointer-3
Stack Pointer-4
Stack Pointer-5
Stack Pointer-6
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer+2
Stack Pointer+3
Stack Pointer+4
Stack Pointer + 5
Stack Pointer + 6
Stack Pointer + 7
Return Address
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer-5
Stack Pointer - 6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address+ 1
FFFF
1
j
Sleep
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
I I I I
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (lSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (lSB)
Return Address (MSB)
Return Address (lSB)
First Op Code of Return Routine
Next Op Code
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
Index Register (lSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (LSB)
First Op Code of SWI Routine
Next Op Code
Restart Address (lSB)
I
1
1
1
0
1
1
1
0
Restart Address (lSB)
Next Op Code
Op Code Address+ 1
FFFF
I Branch Address Test='''''
lOp Code Address + '-Test="O"
1
1
0
1
1
1
1
1
1
0
1
0
Branch Offset
Restart Address (lSB)
First Op Code of Branch Routine
Next Op Code
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Branch Address
1
1
0
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
3
4
FFFF
Op Code Address+ 1
1
2
RELATIVE
BCC
BEQ
BGT
BlE
BlT
BNE
BRA
BVC
BSR
BCS
BGE
BHI
BlS
BMT
BPL
BRN
BVS
3
3
5
1
2
3
4
5
0
1
Offset
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
First Op Code of Subroutine
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
475
HD6303X,HD63A03X,HD63B03X-----------------------------------------------• PRECAUTION TO THE BOARD DESIGN OF OSCILLA·
TlON CIRCUIT
As shown in Fig. 26, there is a case that the cross talk dis·
turbs the normal oscillation if signal lines are put near the
oscillation circuit. When designing a board, pay attention to
this. Crystal and CL must be put as near the HD6303X as
possible.
XTAL
EXTAL
H06303X
H06303X
(OP·64S)
Do not use this kind of print board design.
Figure 26
Precaution to the boad design
of oscillation circuit
(Top View)
Figure 27 Example of Oscillation Circuits in Board Design
•
RECEIVE MARGIN OF THE SCI
Receive margin of the SCI contained in the HD6303X is
shown in Table 17.
Note: SCI = Serial Communication Interface
Table 17
HD6303X
START
2
3
6
4
Bit distortion
tolerance
(t-to) Ito
Character
distortion tolerance
(T -To) ITo
±43.7%
±4.37%
8
STOP
Ideal Waveform
Real Waveform
~
476
_ _
T_~t~
_ _
----+t.1
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6303Y ,HD63A03Y ,
HD63B03Y
CMOS MPU (Micro Processing Unit)
The HD6303Y is a CMOS 8-bit single-chip microprocessing unit
which contains a CPU compatible with the CMOS 8-bit microcomputer HD6301V, 256 bytes of RAM, 24 parallel I/O pins, Serial
Communication Interface (SCI) and two timers.
FEATURES
Instruction Set Compatible with the HD6301 V 1
256 Bytes of RAM
24 Parallel 1/0 Pins
Parallel Handshake Interface (Port 6)
Darlington Transistor Drive (Port 2, 6)
1 6-Bit Programmable Timer
Input Capture Register x 1
Free Running Counter X 1
Output Compare Register X 2
• S-Bit Reloadable Timer
Extemal Event Counter
Square Wave Generation
• Serial Communication Interface (SCI)
Asynchronous Mode (S Transmit Formats, Hardware Parity)
Clocked Synchronous Mode
• Memory Ready
3 Kinds of Memory Ready
HD6303YP, HD63A03YP,
HD63B03YP
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(DP-64S)
• PIN ARRANGEMENT
Halt
Error Detection
(Address Error, Op-code Error)
Interrupt - Extemal 3, Internal 7
Maximum 65k Bytes Address Space
Low Power Dissipation Mode
Sleep Mode
Standby Mode (Hardware Standby, Software Standby)
Minimum Instruction Execution Time - 0.5~s (f = 2MHz)
Wide Range of Operation
Vcc=3 to 5.5V (f=O.l to 0.5MHz)
f=O.l to 1.0MHz : HD6303Y )
V cc= 5V± 10% f= 0.1 to 1.5MHz : HD63A03Y
f=O.l to 2.0MHz: HD63B03Y
0
AD
6
WR
1 RtW
MP,
OR
RES
SA
STBY
5 Do
AMi
70,
O2
5
03
4 D.
5 D.
HD6303Y
A3
1
(Top View)
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
477
HD6303Y,HD63A03Y,HD63B03Y----------------------------------------------• BLOCK DIAGRAM
vccvss vss P20(Tin )
P21(Toutd
P22(SCLK)
P23(Rx )
)
P24(Tx
P2S(TOUt2)
P26(ToutJ)
P 27 (TCLK)
Pso(iRo 1 )
pSl(iRch )
PS2(MR )
PS3(HALn
Ps 4(fS
)
Pss«)S )
PS6
PS7
P60
P61
P62
P63
P64
P6S
P66
P67
...J
a:
N
....
a:
0
0
...J
....<{x.., ~X
OW
!:!:
~RD
CPU
WR
RjW
em
0
Q..
SA
Do
01
02
03
04
Os
06
07
Ao
Al
A2
A3
A4
As
A6
A7
~
....I.t'I
(Q
0
a:
0
a..
As
Ag
Alo
All
Au
A13
A14
A15
(0
....
a:
0
a..
RAM
256Bytes
478
Hitachi America Ltd. •
2210
~HITACHI
O'Toole Ave. • San Jose, CA 95131
• (408) 435-8300
-------------------------------------------------HD6303Y,HD63A03Y,HD63B03Y
•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Unit
Value
Supply Voltage
Vee
-0.3-+7.0
Input Voltage
V in
-0.3-Vee+ 0 .3
V
Operating Temperature
Topr
0-+70
°C
Storage Temperature
T stg
-55-+150
°C
V
(NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits. To assure the normal
operation, we recommend V in , V out : V ss ~ (V in or Vout ) ~ V cc.
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee = 5.0V± 10%, Vss = OV, Ta = 0-+ 70°C, unless otherwise noted.)
Symbol
Item
Test Condition
RES,STBY
Input "High" Voltage
EXTAL
V IH
Other Inputs
min
typ
Vee- 0 .5
-
Vee XO .7
-
2.0
-
-0.3
max
Unit
Vee
+0.3
V
-
0.8
V
Input "Low" Voltage
All Inputs
V IL
Input Leakage Current
NMI, RES, STBY,
MPo,MP,
Il in I
V in = 0.5-Vee- 0 .5V
-
-
1.0
p.A
Three State
Leakage Current
Ao-A?#. 0 0 -0 7 , RD,
WR, R , Ports 2,5,6
IllS11
V in = 0.5-Vee- 0 .5V
-
1.0
p.A
Output "High" Voltage
All Outputs
V OH
2.4
-
-
V
Vee- 0 .7
-
-
V
-
0.4
V
10.0
mA
IOH = - 200p.A
IOH = -10p.A
Output "Low" Voltage
All Outputs
VOL
IOL = 1.6mA
-
Darlington Drive
Current
Ports 2, 6
-I OH
V out = 1.5V
1.0
Input Capacitance
All Inputs
Cin
V in = OV, f = lMHz,
Ta = 25°C
-
-
12.5
pF
Standby Current
Non Operation
-
3.0
15.0
p.A
1.5
3.0
mA
-
2.3
4.5
mA
3.0
6.0
mA
ISlB
Sleeping (f= 1 MHz··)
ISLP
Sleeping (f= 1.5MHz··)
Sleeping (f= 2MHz··)
Current Dissipation·
Operating (f= 1MHz··)
lee
Operating (f= 1.5MHz··)
Operating (f= 2MHz··)
V RAM
RAM Standby Voltage
-
7.0
10.0
mA
10.5
15.0
mA
14.0
20.0
mA
2.0
-
-
V
V1H min = Vcc - 1.0V, V 1L max = O.8V (All output terminals are at no load.)
Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max. values about Current
Dissipations at X MHz operation are decided according to the following formula:
typo value (f
X MHz)
typo value (f = 1MHz) x X
max. value (f = X MHz) = max. value (f = 1MHz) x X
(both the sleeping and operating)
=
=
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
479
HD6303Y,HD63A03Y,HD63B03Y-----------------------------------------------• AC CHARACTERISTICS IV cc
BUS TIMING
= 6.0V± 1 0%. V ss = OV. T. = 0- + 70°C. unless otherwise noted.)
Item
Test
Condition
Symbol
HD6303Y
min
typ
1
-
Cycle Time
tcyC
Enable Rise Time
tEr
Enable Fall Time
tEf
Enable Pulse Width "High" level·
PW EH
450
Enable Pulse Width "low" level·
PWEl
450
Address. RiW Delay Time·
tAo
-
toow
-
tOSR
80
Data Delay Time
Data Set-up Time
IWrite
I Read
Address. RiW Hold Time·
Data Hold Time
I Write·
I Read
Fig. 1
tAH
80
tHW
70
t/"iR
0
R15. WR Pulse Width·
1m."WR Delay Time
t RWO
RD. WR Hold Time
tHRW
DR Delay Time
ITA Hold Time
tOlR
tHlR
10
MR Set-up Time·
tSMR
400
MR Hold Time·
tHMR
E Clock Pulse Width at MR
PWEMR
Processor Control Set-up Time
tpcs
PWRW
450
Fig. 2
-
Fig. 3.
13.14
200
Fig. 2. 3
-
Processor Control Rise Time
tpcr
Processor Control Fall Time
tpCf
BA Delay Time
tBA
Fig. 3
-
Oscillator Stabilization Time
t RC
Fig. 14
20
Reset Pulse Width
PW RST
3
HD63A03Y
max
min
typ
-
10
0.666
-
25
-
25
-
-
-
300
250
-
300
200
-
70
50
50
0
300
-
40
20
200
-
10
280
9
-
-
200
100
-
100
100
250
-
20
3
HD63B03Y
max
min
typ
10
0.5
25
-
- 10
- , 25
- 25
- 160
- 120
- 40
- 20
25
-
220
190
-
220
160
-
60
40
40
0
220
160
-
-
230
40
20
10
max
Unit
!LS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
120
ns
-
-
ns
-
50
ns
-
9
!LS
ns
9
-
-
200
-
-
ns
100
-
100
ns
100
ns
20
-
3
-
70
100
190
-
160
ns
-
ms
-
tcyC
• These timings change in approximate proportion to tcyc' The figures in this characteristics represent those when lcyc is minimum (= in the highest speed
operation).
Peripheral Port Timing
Item
Symbol
Peripheral Data
Set Up Time
Port 2.5.6
Peripheral Data
Hold Time
Port 2. 5. 6
tpOH
Delay Time (From
Enable Fall Edge to
Peripheral Output)
Port 2. 5, 6
t pwo
tposu
HD6303Y
HD63A03Y
HD63B03Y
Unit
min
typ
max
min
typ
max
min
typ
max
200
-
-
200
-
-
200
-
-
ns
200
-
-
200
-
-
200
-
-
ns
-
-
300
-
-
300
-
-
300
ns
200
-
200
-
-
150
-
ns
100
-
-
-
-
200
-
-
200
-
150
100
-
200
-
-
200
ns
Fig. 5
Input Strobe Pulse Width
Port 6
Input Data Set-Up Time
Port 6
Output Strobe Delay Time
Fig. 6
t pWIS
Input Data Hold Time
~H
Fig. 10
tiS
toso,
toso2
480
Test
Condition
Fig. 11
150
100
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
ns
ns
TIMER, SCI TIMING
Item
Symbol
HD6303Y
HD63A03Y
HD63B03Y
Test
Condition
min
typ
max
min
typ
max
min
typ
max
-
2.0
-
-
2.0
-
tCYC
400
-
-
400
-
-
400
ns
-
1.0
-
-
1.0
-
2.0
-
-
2.0
-
-
tcvc
-
-
tCYC
-
-
220
-
-
220
ns
Unit
Timer 1 Input Pulse Width
tpWT
Fig. 9
2.0
Delay Time (Enable Positive
Transition to Timer Output)
tTOD
Fig. 7, 8
-
Fig. 9
1.0
Fig. 4
2.0
-
-
-
220
260
-
-
260
-
-
260
-
-
ns
-
-
100
-
ns
0.6
tSCYC
SCI Input
Clock Cycle
IAsync. Mode
rClock Sync.
tSCYC
SCI Transmit Data Delay
Time (Clock Sync. Mode)
tTXD
SCI Receive Data Set-up
Time (Clock Sync. Mode)
tSRX
SCI Receive Data Hold Time
(Clock Sync. Mode)
tHRX
100
-
-
100
SCI Input Clock Pulse Width
tpWS CK
0.4
0.6
0.4
-
0.6
0.4
Timer 2 Input Clock Cycle
ttCYC
2.0
tpWTCK
-
-
200
-
2.0
200
-
2.0
Timer 2 Input Clock Pulse
Width
-
-
200
-
-
Timer 1'2, SCI Input Clock
Rise Time
tCKr
-
-
100
-
-
100
-
-
100
ns
Timer 1'2, SCI Input Clock
Fall Time
tCKf
-
-
100
-
-
100
-
-
100
ns
Fig. 4
Fig. 9
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
tcyc
ns
481
I----------tcvc----------I
E
!-----PWEL----I
I-----PWEH-----I
tEf __- _ t A H
tEr
Ao-A,5.
R/W
2.4V
O.SV
________________________~~!:-_r-----PW--~~-I
2.4V
RD,WR
MPU Write
0 0 -0 7
MPU Read
0 0-0 7
O.SV
----------------------------~----~
----------------------------+---------~
Figure 1 Bus Timing
I---------PWEMR------l
\
E
\
\
'-----
O.SV
MR
Figure 2 Memory Ready and E Clock Timing
482
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
I
-----------------------------------------------HD6303Y,HD63A03Y,HD63B03Y
Last Instruction
IExecution Cycle
Instruction Execution
Cycle
HALT Cycle
l
E
tB ... f--V-__-~i-----.....;...;........;.---~
2.4V
BA
Figure 3
HALT and SA Timing
Synchronous Clock
Transmit Data
Receive Data
*2.0V is high level when clock input.
2.4V is high level when clock output.
Figure 4
SCI Clocked Synchronous Timing
r-MPUWrite
E
Figure 5 Port Data Set-up and Hold Times (MPU Read)
Figure 6 Port Data Delay Times (MPU Write)
$
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
483
HD6303Y,HD63A03Y,HD63B03Y----------------------------------------------E
E
T2CNT
Timer 1 - - - -.... ,.-.,,..L:::~::=.:--.. - - - FRC
P25------.....:-~
1-..,.,..,....---
Outputs _ _ _ _ _ _ _ _--J
~O.:.;:-----
P21,
Figure 7
(TCONR=N)
Figure 8
Timer 1 Output Timing
**
h
tCKf
"Timer 2 ; ttcyc
SCI
; tScyc
Figure 9
P26
Output
Timer 2 Output Timing
**
""Timer 1 ; tPWT
Timer 2 ; tPWTCK
SCI
; tPWSCK
PORT6
Data
(Input)
Timer 1·2, SCI Input Clock Timing
Figure 10
Port 6 Input Latch Timing
Vcc
Test Point
MPU access of
PORT6
Ji
C
E
R
RL=2.2kQ
1S2074®
or Equiv.
C = 90pF for 0 0 -0 7 , Ao-A 15 • E
= 30pF for Port 2. Port 5. Port 6, RD.
WFi. RIW. BA.1JIf
R = 12kO
Figure 11
Figure 12
Output Strobe Timing
Bus Timing Test Loads (TTL Load)
Interrupt
Test
Internal
Address Bus _ _.r...-+-_'--_"'-_..J''--_''-_.J''--_''-_.J''--_''-_J'o_......
''-_J\_-''-_A_-'\-_''''-
NMI. iRQ..
i1i02.IRQ3
Internal
Data Bus _ _.J'\._..J'--_J\._..J''--_'''-_.J'~_'''-_-'"\-_'''-_..J'< __''-_J'o_....J~_.A._-'"\-_''''Vector Vector First Inst. of
IXOIXBOp Operand Irrelevant PCOIXIS
MSB
LSB
Interrupt Routina
IX7
Code OP Code Data
PC7
Inlarnal
Read
Intarnal
Writa
\~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
Figure 13
484
,
______..J'
Interrupt Sequence
$
HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
~~~~~~~~~~~~~~~~~~~~~~~~HD6303Y.HD63A03Y.HD63B03Y
--s.sv
A--=4:..:.S:..:V_ _ _
i---~
~~
I~c_____
\'-Vo\CIC--O-.-~V------iI-----+-I"'-----------;,.CS~
II£S
_""I______,,...._...J
fl:5V
~~I~j-------
Vee -0 5V
~t'·ss1a)\\\\\\\\\\\\\\\\\\\\\uc.:x=:::x=r~_=cx=
FFFF
FFFF FFFF FFFF FFFF FFFf FFFF N...., PC
FFFF FFFF
I~>-------II~(- - - - - -
~'.'n.' ,,)\\\\\\\\\\\\\\1\\\\\\\
l;J"n.' "~\\U\\\\\\\\\\\\\\l\\\\\
--4...---------::;:::x::r~f
RtW . . 1." . ' , - -
l1li
ms'~\\\\\\\\\.\\\
WI!
l\\\\\\\t~\\\\\\\\\\§§\\\,,\\\\.
'~tTD_H-r-I~J- - f~~J
~.IIIr:l)I~I.lfiWlI141-1-1I1I"I;~------~~JIIIIIIH~~f----------_
pce - PCO- First
PCIS
PC7
Instruction
Figure 14 Reset Timing
•
•
FUNCTIONAL PIN DESCRIPTION
Vee. Vss .
•
XTAL.EXTAL
• STBY
Vee and Vss provide power to the MPU with 5V± 10% supply.
In the case oflow speed operation (fmax=500kHz), the MPU can
operate with 3 to 5.5 volts. Two Vss pins should'be tied to ground.
These two pins interface with an AT-cut parallel resonant crystal.
Divide-by-four circuit is on chip, so if 4MHz crystal oscillator is
used, the system clock is IMHz for example.
EXTAL pin can be drived by the external clock with 45% to 55%
duty. The system clock which is one fourth frequency of the external clock is generated in the LSI. The external clock frequency
should be less than four times of the maximum operating frequency. When using the external clock, XTAL pin should be open. Fig.
15 shows examples of connection circuit. The crystal and CLl , C L2
should be mounted as close as possible to XTAL and EXTAL pins.
Any line must not cross the line between the crystal oscillator and
XTAL, EXTAL.
AT Cut Parallel Resonant Crystal Oscillator
Co=7pF max
Rs=60Q max
XTAL~--~----~
CJ
CLl =CL2
= 10pF-22pF±20%
EXTAL~--~....,
(3.2-SMHz)
This pin makes the MPU standby mode. In "Low" level, the oscillation stops and the internal clock is stabilized to make reset condition. To retain the contents of RAM at standby mode, "0"
should be written into RAM enable bit (RAME). RAME is the bit
6 of the RAM/port 5 control register at $0014. RAM is disabled by
this operation and its contents is sustained .
Refer to "LOW POWER DISSIPATION MODE" for the
standby mode.
• Reset (RES)
This pin resets the MPU from power OFF state and provides a
startup procedure. During power-on, RES pin must be held "Low"
level for at least 2Oms.
The CPU registers (accumulator, index register, stack pointer,
condition code register except for interrupt mask bit), RAM and
the data register of ports are not initialized during reset, so their
contents are undefined in this procedure.
To reset the MPU during operation, RES should be held "Low"
for at least 3 system-clock cycles. At the 3rd cycle during "Low"
level, all the address buses become "High". When RES remains
"Low", the address buses keep "High". If RES becomes "High",
the MPU starts the next operation.
(1)
Latch the value of the mode program pins; MPo and MP 1 •
(2) Initialize each internal register (Refer to Table 4).
(3) Set the interrupt mask bit. For the CPU to recognize the
maskable interrupts IRQI' IROz and IRQ3' this bit should be
cleared in advance.
(4) Put the contents (=start address) of the last two addresses
($FFFE, $FFFF) into the program counter and start the program from this address. (Refer to Table 1).
• Enable IE)
This pin provides a TTL-compatible system clock to external circuits. Its frequency is one fourth that of the crystal oscillator or external clock. This pin can drive one TTL load and 90pF capacitance.
• Non-Maskable Interrupt INMIl
Figure 1 5 Connection Circuit
When the falling edge of the input signal is detected at this pin,
the CPU begins non-maskable interrupt sequence internally. As
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
485
well as the IRQ mentioned below, the instruction being executed at
Nm signal detection will proceed to its compeletion. The interrupt
mask bit of the condition code register doesn't affect non-maskable
interrupt at all.
In response to an NMI interrupt, the contents of the program
counter, index register, accumulators and condition code register
will be saved onto the stack. Upon completion of this sequence, a
vector is fetched from $FFFC and $FFFD to transfer their contents
into the program counter and branch to the non-maskable interrupt
service routine.
(Note) At reset start, the stack pointer should be initialized on
an appropriate memory area and then the falling edge
be input to NMI pin.
• Interrupt Request
(jJ{Q,. TFRl2 )
These are level-sensitive pins whiCh request an internal interrupt
sequence to the CPU. At interrupt request, the CPU will complete
the current instruction before the acceptance of the request. Unless
the interrupt mask in the condition code register is set, the CPU
starts an interrupt sequence; if set, the interrupt request will be ignored. When the sequence starts, the contents of the program
counter, index register, accumulators and condition code register
will be saved onto the stack, then the CPU sets the interrupt mask
bit and will not acknowledge the maskable request. During the last
cycle, the CPU fetches vectors depicted in Table 1 and transfers
their contents to the program counter and branches to the service
routine.
The CPU uses the external interrupt pins (IRQI and IRQ2) also
as port pins Pso and PSI' so it provides an enable bit to Bit 0 and 1 of
the RAM port 5 control register at $0014. Refer to "RAM/PORT 5
CONTROL REGISTER" for the details.
When one of the internal interrupts, ICI, OCI, TOI, CMI or SIO
is generated, the CPU produces internal interrupt signal (IRQa)'
IRQa functions just the same as IRQI or IRQ2 except for its vector
address. Fig. 16 shows the block diagram of the interrupt circuit.
Each Status Register's Interrupt
Enable Flag
"'" ; Enable, "0" ; Disable
ISF
Condition
Code
---+-O-~ O-f---~ Register
I MASK
ICF
;
----+-o~o-+-.-,...;..;;;.;..___I"O" Enable
"1"; Disable
OCFl
OCF2 - - - f - O ' "
Interrupt
Request
Signal
TOF
CMF
RDRF
PER
ORFE
TORE
Sleep
Cancel
Signal
TRAP
SWI
Figure'6
486
Interrupt Circuit Block Diagram
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
ries. Refer to "RAM/PORT 5 CONTROL REGISTER" for more
details.
Table 1 Interrupt Vector Memory Map
Priority
Highest
Vector
FFEE
FFEF
TRAP
FFFC
FFFD
NMI
FFFA
FFFB
SWI
(Software Interrupt)
FFF8
FFF9
lRQ,. ISF (port 6 Input Strobe)
FFF6
FFF7
ICI
(Timer 1 Input Capture)
FFF4
FFF5
OCI
(Timer 1 Output Compare 1. 2)
FFF2
FFF3
TOI
(Timer 1 Overflow)
•
FFEC
FFED
CMI
(Timer 2 Counter Match)
FFEA
FFEB
IRQ2
FFFO
FFF1
FFFE
Lowest
• Halt (HALT; P63 )
Interrupt
This is an input control signal to stop instruction execution and
to release buses. When this signal switches to "Low", the CPU
stops to enter into the halt state after having executed the present
instruction. When entering into the halt state, it makes BA "High"
and also an address bus, data bus, RD, WR, RiW high impedance.
When an interrupt is generated in the halt state, the CPU uses the
interrupt handler after the halt is cancelled. When halted during the
sleep state, the CPU keeps the sleep state, while BA is "High" and
releases the buses. Then the CPU returns to the previous sleep
state when the HALT signal becomes "High".
(Note) Please don't switch the HALT signal to "Low" when
the CPU executes the WAI instruction and is in the interrupt wait state to avoid the trouble of the CPU's operation after the halt is cancelled.
MSB
LSB
FFFF
•
Mode Program (MP o' MP,)
•
Read/Write (R/W)
RES
510
(RDRF
+ ORFE + TORE + PER)
Bus Available (BA)
This is an output control signal which is normally "Low" but
"High" when the CPU accepts HALT and releases the buses. The'
HD6800 and HD6802 make BA "High" and release the buses at
WAI execution, while the HD6303Y doesn't make BA "High"
under the same condition.
• PORT
The HD6303Y provides three 8-bit I/O ports. Each port provides Data Direction Register (DDR) which controls the I/O state
by the bit.
Set MPo "High" and MP1 "Low".
Table 2 Port and Data Direction Register Address
This signal, usually be in read state ("High"), shows whether
the CPU is in read ("High") or write ("Low") state to the peripheral or memory devices. This can drive one TTL load and 30pF capacitance.
•
RD, WR
These signals show active low outputs when the CPU is reading/
writing to the peripherals or memories. This enables the CPU easy
to access the peripheral LSI with Rl) and WR input pins. These pins
can drive one TTL load and 30pF capacitance.
•
Load Instruction Register (LlR)
This signal shows the instruction opecode being on data bus
(active low). This pin can drive one TTL load and 30pF capacitance.
•
Memory Ready (MR; P&2)
This is the input control signal which stretches the system
clock's "High" period to access low-speed memories. HD6303Y
can select three kinds of low-speed memory access method by
RAM/Port 5 Control Register's MRE bit and AMRE bit. In the
case that CPU accesses low-speed memories by the external MR
signal (MRE="I", AMRE="O"), the system clock operates in
normal sequence when this signal is in "High".
But this signal in "Low", the "High" period of the system clock
will be stretched depending on its "Low" level duration in integral
multiples of the cycle time. This allows the CPU to interface with
low-speed memories (See Fig. 2). Up to 9ILs can be stretched.
During internal address space access or non valid memory access, MR is prohibited internally to prevent decrease of operation
speed. Even in the halt state, MR can also stretch "High" period of
system clock to allow peripheral devices to access low-speed memo-
•
Port
Port Address
Port 2
$0003
$0001
Port 5
$0015
$0020
Port 6
$0017
$0016
Data Direction Register
Port 2
An 8-bit I/O port. Port 2 DDR (P2DDR) controls the I/O state.
This port provides DDR corresponding to each bit and can define
input or output by the bit ("0" for input, "I" for output).
As Port 2 DDR is cleared during reset, it will be an input port.
Port 2 is also used as an I/O pin for timer 1, Timer 2 and the SCI.
Pins for Timers and the SCI set or reset each DDR depending on
their functions and become I/O pins. When port 2 functions as an 1/
o port after used as I/O pins of the timers or the SCI, the I/O direction of the pins remain as it is used as the I/O pin of timer and SCI.
Port 2 can drive one TTL load and 30pF capacitance. This port
can produce 1rnA when Vout= 1.5V to drive directly the base of
Darlington transistor.
Pzo (Tin)
P20 is also used as an external input pin for the input-capture.
This pin is an I/O port which is an input or output as defined by the
Data Direction Register (P2o DDR) ("0" for an input and "1" for
an output). Then either a signal to or from P20 ("to" for an output
port, "from" for an input port) is always input to the Timer 1 input
capture.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
487
HD6303Y,HD63A03Y,HD63B03Y----------------------------------------------RES
-----~ Q
R
'"
C
~
ol-----+cil
P20 OOR
~
WP20
iii
E
01------1~
1-------1 Q
P20 DATA
RP2
WP2D : DDR Write Signal
WP2 : Port Write Signal
RP2
: Port Read Signal
WP2
.....L
Timer 1
Input Capture Input
>---------------1.
P21 (Tout 1), P24 (Tx), P 26 (Tout 2), P26 (Tout 3)
These four pins can be also used as output pins for Timer 1,
Timer 2 and a transmit output of the SCI. Timer 1, and the SCI
have a register which enables output. By setting these registers,
they automatically will be output pins of timer or the SCI.
r--------4~ Q S
R 01-----+ '"
P2" OOR
cil
C
WP20
~
co
0
iii
01-----+ ~
P2" DATA
C
Q
.E
'_
.Ii!n~~ ~ Ti~,:r
}_ and SCI
t
t
WP2
yl----------+---~--
Output Data
--------+----i-- Output Enable Signal
I...-......
RP2
----L-
488
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------HD6303Y,HD63A03Y,HD63B03Y
P22 (SelK)
P22 is also used as a clock 110 pin for the SCI. It is selected as a
clock input or output pin by the operating mode of the SCI. It is usa-
ble as an 110 port when the SCI has no clock input or output (as an
output port ifP22 DDR=I, as an input port ifP22 DDR=O).
RES
S R, R2
~---------4-4Q
D~--4-~
P22 DDR
C
WP2D
~
C1l
.---..........---..
r--r--.
D 1---+....... 0
Q
SCI
r----------
P22 DATA
(ij
C
Q)
I
~
I
I
WP2
E
I
1..--1-_ _ _+--_ _
Clock Input Enable signal
L--...r-rL.....l---------I----..:--- Output Clock
I..-~---------+-------
RP2
.--...!..--II~
-L
P 23 (Rx). P 27 (TClK)
P23 and P27 are also used as received data input pins for the SCI
and external clock input pins for Timer 2. The SCI and Timer 2
have registers which enable input. If the registers are set, the DDR
(P23 DDR, P27 DDR) are cleared and P23 and P27 will be input
pins for Rx and TCLK.
Clock Output Enable signal
Input Clock
Since the SCI will be a clocked synchronous mode by an external
clock-input during reset, the DDR of P22 is cleared automatically
and P22 is an input port. Set the SCI to a mode where P22 is not used
(CCO or CCI of the RMC Register is "0" or "1" respectively) and
write "1" to the P22 DDR to make P22 an output port.
RES
R2
III
DI---+---4cil
P2n DDR
~
L-~C__~
C
WP2D
(ij
I------~ Q
E
Q)
DI----+~ ~
P2n DATA
C
WP2
SCI, Timer 2
r---------Input Enable signal
r---t--" Timer
SCI Receive Data,
2 External Clock
PORT2 DDR ($0001)
(Write only, $00
during reset.)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
489
HD6303Y,HD63A03Y,HD63B03Y----------------------------------------------• Port 5
An 8"'bit I/O port. The DDR of port 5 controls I/O state. Each bit
of port 5 has a DDR which defines I/O state ("0" for input and "1"
for output).
During reset, the DDR of port 5 is cleared and port 5 becomes
an input port.
Port 5 is also usable as IRQI,!R~ HALT, MR and the strobed
signal of port 6 for handshake (IS, OS). It is set to input or output
automatically if it is used as these control signal pins (except PS4 '
ID. Since the DDR of port 5, as is port 2, is set or reset by the control signal, I/O directions of the I/O ports are retained after the control signal is disabled. Port 5 can drive one TTL load and 90pF capacitance.
P so (IRQ,). P s, (IRQ2)
Pso and P61 are also usable as interrupt pins. The RAM/port 5
control registers ofmQl and IRQ; have enable bits (IQIE, IQ2E).
When these bits are set to "1", P50 and P61 will automatically be interrupt input pins.
PS2 (MR). P&3 (HALT)
~ and P53 are also
usable as MR and HALT inputs. MR and
HALT have enable bits (MRE, HLTE) in the RAM/Port 5 Control
Register as lRQl and mQz. Since MRE is cleared during reset, P5Z is
usable as an I/O port, and HLTE is set during reset, the DDR ofP s3
will be automatically reset to be a HALT input pin. HLTE of the
RAM/Port 5 Control Register has to be cleared to use P53 as an I/O
port.
RES
Rl
R2
r---------~Q
D~--~-.
PS n DDR
C
III
:;,
III
WP5D
!II
1U
o
D I----+----t Iii
PS n DATA
E
t-----------iQ
!!!
C
WP5D: DDR Write signal
WP5 : Port Write signal
RP5
: Port Read signal
c::
WP5
L.--+----~..--iRAM/PORT
5 Control
Register
mol
l------I~ i1m2
~------------------+-------~~
~
• Initializing value during reset;
IRQ'E= "0", IRQ2E= "O",MRE= "O",HLTE= "'"
PS4 (is)
output port (set the DDR of P54 to "1 "), an output signal from PS4
will be the input to IS.
_
P54 is also usable as the input strobe (IS) for port 6 handshake
interface. This pin, as is Pzo , is always an I/O port. IfP 54 is used as an
RES
R
r-----------tQ
D
PS4 DDR
C
1-------.
III
:;,
III
WP5D
!9
!II
D 1-_ _-+ 0
t----------i Q
~
PS4 DATA
2i
C
RP5
.EO
WP5
-L
-+___... Port 6
>---,:=-_ _ _ _ _ _ _ _
Control Status Register
is
490
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
by setting the OS enable register (OSE) of the port 6 Control Status
Register (P6CSR).
Pss (OS)
P55 is also usable as the output strobe (OS) for port 6 handshake
interface. It will be an I/O port during reset, and an OS output pin
RES
WP5D
D
'-~-'L-_r~~~Q
PssDATA
Port 6 Control/Status Register
C
r---------I
WP5
~+__------+_--+-
as
OSE (1 : as output
o : as
RP5
.....J.-
)
output disable
P S6 ' P 57
P 56 and P57 are 110 ports.
RES
R
Q
D
PS n DDR
C
co'"
:J
WP5D
Q
D
PS n DATA
c
~
ctI
C
coc:
03
]
WP5
PORT5 DDR ($0020)
(Write only. $00
during reset.)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
491
HD6303Y,HD63A03Y,HD63B03Y------------------------------------------------•
Port 6 controls parallel handshake interface besides functions as
an 110 port. Therefore, it provides DDRs to control and IS LATCH
to latch the input data.
Port 6 can drive one TIL load and 30pF capacitance. It can drive
directly the base of Darlington transistor as port 2.
Port 6
8-bit 110 port. Port 6 DDR controls 110 state. Each bit of port 6
has a DDR and designates input or output ("0" for input, "1" for
output). During reset, Port 6 DDR is cleared and port 6 becomes an
input port.
AES
A
.---------iQ
----~IRQl
Figure 18
Input Strobe Interrupt block Diagram
AD
Vim
RIS
A!W
Wf
BA
Data Bus
Address Bus
Address Bus
POAT6
Figure 19 HD6303Y Operating Function
494
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------HD6303Y,HD63A03Y,HD63B03Y
Table 4 Internal Register
00·
01
02·
03
04·
05·
06·
07·
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1 F····
20
21
22
23
24
25
26
27
•
••
•••
••••
Abbreviation
Register
Address
P1DDR
P2DDR
PORT1
PORT2
P3DDR
P4DDR
PORT3
PORT4
TCSR1
FRCH
FRCl
OCR1H
OCR1l
ICRH
ICRl
TCSR2
RMCR
TRCSR1
RDR
TDR
RP5CR
PORT5
P6DDR
PORT6
PORT1
OCR2H
OCR2l
TCSR3
TCONR
T2CNT
TRCSR2
TSTREG
P5DDR
P6CSR
Port 1 DDR (Data Direction Register)
Port 2 DDR
Port 1
Port 2
Port 3 DDR
Port 4 DDR
Port 3
Port 4
Timer Control/Status Register 1
Free Running Counter (MSB)
Free Running Counter (lSB)
Output Compare Register 1 (MSB)
Output Compare Register 1 (lSB)
Input Capture Register (MSB)
Input Capture Register (lSB)
Timer Control/Status Register 2
Rate/Mode Control Register
Tx/Rx Control Status Register 1
Receive Data Register
Transmit Data Register
RAM/Port 5 Control Register
Port 5
Port 6 DDR
Port 6
Port 7
Output Compare Register 2 (MSB)
Output Compare Register 2 (lSB)
Timer Control/Status Register 3
Time Constant Register
Timer 2 Up Counter
Tx/Rx Control Status Register 2
Test Register·
PORT 5 DDR
PORT 6 Control/Status Register
-
Reserved
-
-
R/W··
Initialized value
during reset···
W
W
R/W
R/W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R
W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
$FE
$00
indefinite
indefinite
$FE
$00
indefinite
indefinite
$00
$00
$00
$FF
$FF
$00
$00
$10
$CO
$20
$00
indefinite
$F8or$78
indefinite
$00
indefinite
indefinite
$FF
$FF
$20
$FF
$00
$28
W
R/W
$00
$07
-
-
-
-
External address .
R: Read-only register, W: Write-only register, RIW: ReadlWrite register.
When empty bit is in the register, it is set to "1".
Register for test. Don't access this register.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
495
• Output Compare Register (OCR)
($OOOB. $OOOC; OCR1) ($0019. $001A: OCR2)
$0000
Internal'
Register
$0027
The output compare register is a 16-bit read/write register which
can control an output waveform. The data of OCR is always compared with the FRC.
When the data matches, output compare flag (OCF) in the timer
control/status register (TCSR) is set. Ifan output enable bit (OE) in
the TCSR2 is "1", an output level bit(OLVL) in the TCSR will be
output to bit 1 (OCR 1) and bit 5 (OCR 2) of port 2. To control the
output level again by the next compare, the value of OCR and
OL VL should be changed. The OCR is set to $FFFF at reset. The
compare function is inhibited for a cycle just after a write to the upper byte of the OCR or FRC. This is to set the 16-bit value valid in
the counter register for compare. In addition, it is because counter
is to set $FFF8 at the next cycle of the CPU's upper byte write to
the FRC.
• For data write to the FRC or the OCR, 2-byte transfer instruction (such as STX, etc.) should be used.
External Memory
Space
$0040
Internal RAM
256 Bytes
$013F
External
Memory
Space
•
Input Capture Register (lCR) ($OOOD : OOOE)
The input capture register is a 16-bit read-only register which
stores the FRC's value when external input signal transition generates an input capture pulse. Such transition is controled by input
edge bit (IEDG) in the TCSRl.
In order to input the external input signal to the edge detector, a
bit of the DDR corresponding to bit 0 of port 2 should be cleared
("0"). When an input capture pulse occl,lrs by external input signal
transition at the next cycle of CPU's high-byte read of the ICR, the
input capture pulse will be delayed by one cycle. In order to ensure
the input capture operation, a CPU read of the ICR needs 2-byte
transfer instruction. The input pulse width should be at least 2 system cycles. This register is cleared ($0000) during reset.
$FFFF
·This mode does not
include the addresses:
$00. $02. $04. $05.
$06. $07 or $18 which
can be used externally.
Figure 20 HD6303Y Memory Map
• TIMER 1
• Timer Control/Status Register 1 (TCSR1) ($0008)
The HD6303Y provides a 16-bit programmable timer which can
simultaneously measure an input waveform and generate two independent output waveforms. The pulse widths of both input/output
waveforms vary from microseconds to seconds.
Timer 1 is configured as follows (refer to Fig. 22).
Control/Status Register 1 (8 bit)
Control/Status Register 2 (7 bit)
Free Running Counter (16 bit)
Output Compare Register 1 (16 bit)
Output Compare Register 2 (16 bit)
Input Capture Register (16 bit)
The timer control/status register 1 is an 8-bit register. All bits are
readable and the lower 5 bits are also writable: The upper 3 bits are
read-only which indicate the following timer status.
Bit 5
The counter value reached to $0000 as a result of counting-up (TOF).
Bit 6
A match has occurred between the FRC and the OCR 1
(OCF1).
Bit 7
Defined transition of the timer input signal causes the
counter to transfer its data to the ICR (ICF).
The followings are the each bit descriptions.
•
Timer Control/Status Register 1
Free-Running Counter (FRC)($0009:000A)
The key timer element is a 16-bit free-running counter driven
and incremented by system clock. The counter value is readable by
software without affecting the counter. The counter is cleared during reset.
When writing to the upper byte ($09), the CPU writes the preset
value ($FFF8) into the counter (address $09, $OA) regardless of
the write data value. But when writing to the lower byte ($OA) after
the upper byte writing, the CPU writes not only lower byte data into
lower 8 bit, but also upper byte data into higher 8 bit of the FRC.
The counter will be as follows when the CPU writes to it by double store instructions (STD, STX, etc.)
Bit 0
OLVL 1 Output Level 1
OLVLl is transferred to port 2, bit 1 when a match occurs between the counter and the OCRl. If bit 0 of the TCSR2 (OED,
is set to "1", OLVLl will appear at bit 1 of port 2.
Bit 1
IEDG Input Edge
This bit determines which edge, rising or falling, of input signal of bit 0 of port 2 will trigger data transfer from the counter to
the ICR. For this function, the DDR corresponding to port 2, bit
o should be cleared beforehand.
IEDG= 0, triggered on a falling edge
("High" to "Low")
IEDG= I, triggered on a rising edge
("Low" to "High")
$FFFB
Counter value
In the case of the CPU write ($ 5AF3) to the FRC
Figure 21
496
$0008
Counter Write Timing
Bit 2
ETOI Enable Timer Overflow Interrupt
When this bit is set, an internal interrupt (IRQa) by TOI interrupt is enabled. When cleared, the interrupt is inhibited.
Bit 3
EOCI1 Enable Output Compare Interrupt 1
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
When this bit is set, an internal interrupt (IRQa) by OCIl interrupt is enabled. When cleared, the interrupt is inhibited.
Bit 4
EICI Enable Input Capture Interrupt
When this bit is set, an internal interrupt (IRQa) by ICI interrupt is enabled. When cleared, the interrupt is inhibited.
Bit 5
Timer Control/Status Register 2 (TCSR2) ($OOOF)
The timer control/status register 2 is a 7-bit register. All bits are
readable and the lower 4 bits are also writable. But the upper 3 bits
are read-only which indicate the following timer status.
Bit 5
A match has occurred between the FRC and the OCR2
(OCF2).
Bit 6
Timer Control/Status Register 2
6
543
ICF IOCFtl DCF21 -
2
1
0
I EDCI2F LVL2 1DE21 DE1 I $OOOF
OE 1 Output Enable 1
This bit enables the OLVLI to appear at port 2, bit 1 when a
match has occurred between the counter and the output compare register 1. When this bit is cleared, bit 1 of port 2 will be an
I/O port. When set, it will be an output ofOLVLI automatically.
Bit 1
OE2 Output Enable 2
This bit enables the OLVL2 to appear at port 2, bit 5 when a
match has occurred between the counter and the output compare register 2. When this bit is cleared, port 2, bit 5 will be an 1/
o port. When set, it will be an output ofOLVL2 automatically.
OCF1 Output Compare Flag 1
This read-only bit is set when a match occurs between the
OCRI and the FRC. Cleared when writing to the OCRI ($OOOB
or $OOOC) after the TCSRI or TCSR2 read at OCF= 1.
Bit 7
ICF Input Capture Flag
This read-only bit is set when an input signal of port 2, bit 0
makes a transition as defined by IEDG and the FRC is transferred to the ICR. Cleared when reading the upper byte ($OOOD) of
the ICR after the TCSRI or TCSR2 read at ICF= 1.
•
Bit 0
TOF Timer Overflow Flag
This read-only bit' is set when the counter increments from
$FFFF by 1. Cleared when the counter's MSB byte ($0009) is
read by the CPU after the TCSRI read at TOF= 1.
Bit 6
Bit 7
The same status flag as the ICF flag of the TCSRI, bit 7.
The followings are the each bit descriptions.
Bit 2
OLVL2 Output Level 2
OLVL2 is transferred to port 2, bit 5 when a match has occurred between the counter and the OCR2. If bit 5 of the TCSR2
(OE2), is set to "I", OLVL2 will appear at port 2, bit 5.
Bit 3
EOCI2 Enable Output Compare Interrullt 2
When this bit is set, an internal interrupt (IRQa) by OCI2 interrupt is enabled. When cleared, the interrupt is inhibited.
Bit 4
Not used
Bit 5
OCF2 Output Compare Flag 2
This read-only bit is set when a match has occurred between
the counter and the OCR2. Cleared when writing to the OCR2
($0019 or $OOIA) after the TCSR2 read at OCF2= 1.
Bit 6
Bit 7
OCF1 Output Compare Flag 1
ICF Input Capture Flag
OCFI and ICF are dual addressed. If which register, TCSRI
or TCSR2, CPU reads, it can read OCFI and ICF to bit 6 and bit
7.
Both the TCSRI and TCSR2 will be cleared during reset.
(Note) If OEI or OE2 is set to "I" before the first output compare match occurs after reset restart, bit 1 or bit 5 of port 2
will produce "0" respectively.
Figure 22 Timer 1 Block Diagram
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
497
HD6303Y,HD63A03Y,HD63B03Y-----------------------------------------------• TIMER 2
In addition to the timer 1, the HD6303Y provides an 8-bit reloadable timer, which is capable of counting the external event. The
timer 2 contains a timer output, so the MPU can generate three independent waveforms. (Refer to Fig. 23.)
The timer 2 is configured as follows:
Control/Status Register 3 (7 bits)
. 8-bit Up Counter
. Time Constant Register (8 bits)
• Timer 2 Up Counter (T2CNT) ($001 D)
This is an 8-bit up counter which operates with the clock decided
by CKSO and CKS1 of the TCSR3. The CPU can read the value of
the counter without affecting the counter. In addition, any value
can be written to the counter by software even during counting.
The counter is cleared when a match occurs between the counter
and the TCONR or during reset.
If the write operation is made by software to the counter at the
cycle ofcounter clear, it does not reset the counter but put the write
data to the counter.
• Time Constant Register (TCONR) ($001C)
The time constant register is an 8-bit write only register. The
data of register is always compared with the counter.
When a match has occurred, the counter match flag (CMF) of
the timer control status register 3 (TCSR3) is set and the value
selected by TOSO and TOS1 of the TCSR3 will appear at port 2, bit
6. When CMF is set, the counter will be cleared simultaneously and
then start counting from $00. This enables regular interrupts and
waveform outputs without any software support. The TCONR is set
to "$FF" during reset.
• Timer Control/Status Register 3 (TCSR3) ($001 B)
The timer control/status register 3 is a 7-bit register. All bits are
readable and 6 bits except for CMF can be written.
The followings are each pin descriptions.
Timer Control/Status Register 3
7
6
5
432
1
0
ICMFIECMII-I T2EITOS1ITOSoICKS1ICKsol $0018
Bit 0
Bit 1
CKSO Input Clock Select 0
CKS1 Input Clock Select 1
Input clock to the counter is selected as shown in Table 5 depending on these two bits. When an external clock is selected,
bit 7 of port 2 will be a clock input automatically. Timer 2 detects
the rising edge of the external clock and increments the counter.
The external clock is countable up to half the frequency of the
system clock.
....---- Timer' FRC
Port 2
Bit 7
Port 2
Bit 6
Figure 23 Timer 2 Block Diagram
498
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------HD6303Y,HD63A03Y,HD63B03Y
Table 5 Input Clock Select
CKS1
CKSO
0
0
E clock
0
1
E clock/S"
1
0
E clock/12S"
1
1
External clock
Input Clock to the Counter
" These clocks come from the FRC of the timer 1. If one of these clocks is
selected as an input clock to the up counter, the CPU should not write to
the FRC of the timer 1.
Bit 2
Bit 3
TOSO Timer Output Select 0
TOS 1 Timer Output Select 1
When a match occurs between the counter and the TCONR
timer 2 outputs shown in Table 6 will appear at port 2, bit 6 depending on these two bits. When both TOSO and TOSI are "0",
bit 6 of port 2 will be an I/O port.
Table 6 Timer 2 Output Select
TOS1
TOSO
0
0
Timer Output
Timer Output Inhibited
0
1
Toggle Output"
1
0
Output "0"
1
1
Output "1"
" When a match occurs between the counter and the TCONR, timer 2
output level is reversed. This leads to production of a square wave with
50% duty to the external without any software support.
Bit 4
T2E Timer 2 Enable Bit
When this bit is cleared, a clock input to the up counter is
inhibited and the up counter stops. When set to "I", a clock
P22
selected by CKSI and CKSO (Table 5) is input to the up counter.
(Note) P26 outputs "0" when T2E bit cleared and timer 2 set in
output enable condition by TOS 1 or TOSO. It also outputs
"0" when T2E bit set" 1" and timer 2 set in output enable condition before the first counter match occurs.
Bit 6
Not Used.
Bit 6
ECMI Enable Counter Match Interrupt
When this bit is set, an internal interrupt (IRQa) by CMI is
enabled. When cleared, the interrupt is inhibited.
Bit 7
CMF Counter Match Flag
'This read-only bit is set when a match occurs between the up
counter and the TCONR. Cleared by writing "0" at CMF= 1 by
software (unable to write "1" by software).
Each bit of the TCSR3 is cleared during reset.
• SERIAL COMMUNICATION INTERFACE (SCI)
The Serial Communication Interface (SCI) in the HD6303Y
contains the following two operating modes: asynchronous mode by
the NRZ format, and clocked synchronous mode which transfers
data synchronously with the clock. In the asynchronous mode, data
length, parity bits and number of stop bits can be selected, and eigtit
transfer formats are provided.
The SCI consists of the following registers as shown in Fig. 24
Block Diagram.
Transmit/Receive Control Status Register 1 (TRCSRl)
Rate/Mode Control Register (RMCR)
Transmit/Receive Control Status Register 2 (TRCSR2)
Receive Data Register (RDR)
Recevie Shift Register
Transmit Data Register (TDR)
Transmit Shift Register
To operate the SCI, initialize the RMCR and TRCSR2, after
selecting the desirable operating mode and transfer format. Next,
set the enable bit (TE or RE) ofthe TRCSRI. Operating mode and
transfer format should be changed when the enable bit (TE, RE) is
cleared. When setting the TE or RE again after changing the operating mode or transfer format, interval of more than a I-bit cycle of
the baud rate or bit rate is necessary. If a I-bit cycle or more is not
allowed, the SCI block may not be initialized.
~----------------------------------------------~
Figure 24 SCI Block Diagram
$
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
499
HD6303Y,HD63A03Y,HD63B03Y------------------------------------------------• Asynchronous Mode
Asynchronous mode contains 8 transfer formats as shown in
Fig. 25.
Data transmission is enabled by setting TE bit of the TRCSRl,
then port 2, bit 4 will unconditionally become a serial output independently of the corresponding DDR.
To transmit data, set the desirable transmit format with RMCR
and TRCSR2. When the TE bit is set, the data can be transmitted
after transmitting the one frame of preamble ("1 ").
The conditions at this stage are as follows.
1) Ifthe TDR is empty (TDRE= 1), consecutive 1's are produced to indicate the idle state.
2) If the TDR contains data (TDRE=O), data is sent to the
Transmit Shift Register and data transmit starts.
During data transmit, a start bit of "0" is transmitted first. Then
7-bit or 8-bit data (starts from bit 0) is transmitted. With PEN= 1,
the parity bit, even or odd, selected by EOP bit is added, lastly the
stop bit (1 bit or 2 bis) is sent.
When the TDR is "empty", hardware sets TDRE flag bit. If the
CPU doesn't respond to the flag in proper timing (the TDRE is in
set condition till the next normal data transfer starts from the transmit data register to the transmit sift register), "1" is transferred instead of the start bit "0" and continues to be transferred till data is
provided to the data register. While the TDRE is "I", "0" is not
transferred.
Data receive is possible by setting RE bit. This makes port 2,
bit 3 a serial input. The operation mode of data receive is decided by
the contents of the TRCSR2 and RMCR at first, and set RE bit of
TRCSRI. The first "0" (space) synchronizes the receive bit flow.
Each bit of the following data will be strobed in the middle. If a stop
bit is not" 1", a framing error assumed and ORFE is set.
When a framing error occurs, receive data is transferred to the
Receive Data Register and the CPU can read the error-generating
data. This makes it possible to detect a line break.
When PEN bit is set, the parity check is done. If the parity bit
does not match the EOP bit, a parity error occurs and the PER bit is
set, not the RDRF bit. Also, when the parity error occurs the receive data can be read just like in the case of the framing error.
The RDRF flag is set when the data is received without a framing error and a parity error.
If RDRF is still set when receiving the stop bit of the next data,
ORFE is set to indicate the overrun generation. CPU can get the receive data by reading RDR. When 7 bit data format is selected, the
8th bit of RDR is "0".
When the CPU read the receive Data Register as a response to
RDRF flag or OR FE flag after having read TRCSR, RDRF or
ORFE is cleared.
(Note) Clock Source in Asynchronous Mode
If CCl:CCO= 10, the internal bit rate clock is provided at P22
regardless of the values for TE or RE. Maximum clock rate is
E+16.
If both CCI and CCO are set, an external TTL compatible clock
must be connected to P22 at sixteen times (16X) the desired bit
rate, but not greater than E.
I STOP I
(1) ISTARTI
7Bit Data
(2) !START!
7Bit Data
2 STOP
(3) !START!
7Bit Data
IPARITY ISTOP I
(4) , STARTI
7Bit Data
IPARITY I
(5)
I START I
BBit Data
(6)
'START I
BBit Data
(7)
ISTARTI
BBit Data
(8)
, STARTI
BBit Data
2 STOP
I STOP I
2 STOP
Figure 25 Asynchronous Mode Transfer Format
• Clocked Synchronous Mode
In the clocked synchronous mode, data transmit is synchronized
with the clock pulse. The HD6303Y SCI provides functionally independent transmitter and receiver which makes full duplex operation
possible in the asynchronous mode. But in the clocked synchronous
mode an SCI clock I/O pin is only P22 , so the simultaneous receive
and transmit operation is not available. In this mode, TE and RE
should not be in set condition ("1") simultaneously. Fig. 26 gives a
synchronous clock and a data format in the clocked synchronous
mode.
I) Data transmit
Data transmit is realized by setting TE bit in the TRCSRI. Port
2, bit 4 becomes an output unconditionally independent of the
value of the corresponding DDR.
Both the RMCR and TRCSR should be set in the desirable operating condition for data transmit.
500
When an external clock input is selected and the TDRE flag is
"0", data transmit is performed from port 2, bit 4, synchronizing
with 8 clock pulses input from external to port 2, bit 2.
Data is transmitted from bit 0 and the TDRE is set when the
Transmit Shift Register (TSR) is "empty". More than 9th clock
pulse of external are ignored.
When data transmit is selected to the clock output, the MPU
produces transmit data and synchronous clock at TDRE flag clear.
2) Data receive
Data receive is enabled by setting RE bit. Port 2, bit 3 will be a
serial input. The operating mode of data receive is decided by the
TRCSRI and the RMCR.
If the external clock input is selected, 8 external clock pulses and
the synchronized receive data are input to port 2, bit 2 and bit 3 respectively. The MPU put receive data into the receive data shift register by this clock and set the RDRF flag at the termination of 8 bit
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
~~~~~~~~~~~~~~~~~~~~~~~~HD6303Y.HD63A03Y.HD63B03Y
data receive. More than 9th clock pulse of external input are ignored. When RDRF is cleared, the MPU starts receiving the next
data instantly. So, RDRF should be cleared with P22 "High".
When data receive is selected with the clock output, 8 synchronous clocks are output to the external by setting RE bit. So re-
ceive data should be input from external synchronously with this
clock. When the first byte data is received, the RDRF flag is set.
After the second byte, receive operation is performed by sending
the synchronous clock to the external after clearing the RDRF bit.
<~====:::JI Transmit Direction
Synchronous
clock
Data
~NotValid
• Transmit data is produced from a failing edge of a synchronous clock to the next falling edge .
• Receive data is latched at the rising edge.
Figure 26 Clocked Synchronous Mode Format
• Transmit/Receive Control Status Register (TRCSR1)
($0011)
Bit 5
The TRCSRI is composed of8 bits which are all readable. Bits 0
to 4 are also writable. This register is initialized to $20 during reset.
Each bit functions are as follows.
Transmit/Receive Control Status Register
7
6
5
1RDRF 1ORFE 1TOREI
Bit 0
4
RIE
3
2
1
Bit 6
0
1 RE 1 TIE 1 TE 1WU 1 $0011
WU Wake-up
In a typical multi-processor configuration, the software protocol provides the destination address at the first byte of the
message. In order to make uninterested MPU ignore the remaining message, a wake-up function is available. By this, uninterested MPU can inhibit all further receive processing till the
next message starts.
Then wake-up function is triggered by consecutive l's with 1
frame length. The software protocol should provide the idle time
between messages.
By setting this bit, the MPU stops data receive till the next
message. The receive of consecutive" 1" with one frame length
wakes up and clears this bit by hardware and then the MPU restarts receive operation. However, the RE flag should be already
set before setting this bit. In the clocked synchronous mode WU
is not available, so this bit should not be set.
Bit 1
• Transmit Rate/Mode Control Register (RMCR)
The RMCR controls the following serial 110:
Baud Rate
Data Format
. Clock source
. Port 2, Bit 2 Function
. Operation Mode
All bits are readable/writable. Bit 0 to 5 of the RMCR are cleared
during reset.
Transfer Rate/Mode Control Register
TE Transmit Enable
TIE Transmit Interrupt Enable
When this bit is set, an internal interrupt (IRQ3) is enabled
when TDRE (bit 5) is set. When cleared, the interrupt is
inhibited.
Bit 3
RE Receive Enable
When set, a signal is input to the receiver from port 2, bit 3
regardless of the value of the. DDR. When RE is cleared, the
serial 110 doesn't atlfect port 2, bit 3.
Bit 4
ORFE Overrun Framing Error
ORFE is set by hardware when an overrun or a framing error
is generated (during data-receive only). An overrun error occurs
when new receive data is ready to be transferred to the RDR
during RDRF still being set. A framing error occurs when a stop
bit is "0". But in clocked synchronous mode, this bit is not affected. This bit is cleared by reading the TRCSRI or TRCSR2,
and the RDR, when RDRF= I. ORFE is cleared during reset.
Bit 7
RORF Receive Data Register Full
RDRF is set by hardware when data is received normally and
transferred from the Receive Shift Register (RSR) to the RDR.
This bit is .cleared by reading TRCSRI or TRCSR2, and the
RDR, when RDRF= 1. This bit is cleared during reset.
When this bit is set, transmit data will appear at port 2, bit 4
after one frame preamble in asynchronous mode, while in
clocked synchronous mode it appears immediately. This is executed regardless of the value of the corresponding DDR. When
TE is cleared, the serial I/O doesn't affect port 2, bit 4.
Bit 2
TORE Transmit Data Register Empty
TDRE is set by hardware when the TDR is transferred to the
Transmit Shift Register in the asynchronous mode, while in
clocked synchronous mode when the TDSR is "empty". This
bit is cleared by reading the TRCSRI or TRCSR2 and writing
new transmit data to the TDR when TDRE= I TDRE is set to
"I" during reset.
RIE Receive Interrupt Enable
When this bit is set, an internal interrupt (IRQ) is enabled
when RDRF (bit 7) or ORFE (bit 6) is set. When cleared, the
interrupt is inhibited.
6
5
432
1
0
I - ISS21 ee21 cell eeol SS1 I Ssol
Bit 0
Bit 1
Bit 5
SSO
SS1
SS2
$0010
Speed Select
These bits control the baud rate used for the SCI. Table 7 lists
the available baud rates. The timer 1 FRC (SS2= 0) and the timer 2
up counter (SS2= 1) provide the internal clock to the SCI. When
selecting the timer 2 as a baud rate clock source, it functions as a
baud rate generator. The timer 2 generates the baud rate listed in
Table 8 depending on the value of the TCONR.
(Note) When operating the SCI with internal clock, do not perform write operation to the timer/counter which is the
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
501
HD6303Y,HD63A03Y,HD63B03Y-----------------------Table 7 SCI Bit Times and Transfer Rates
(1) Asynchronous Mode
XTAL
SS2
SSI
SSO
0
0
0
0
1
0
1
0
2.4576MHz
4.0MHz
614.4kHz
1.0MHz
4.9152MHz
1.2288MHz
E
E';-16
26:,s/384008aud
16"s/62500Baud
131,s/768008aud
E';- 128
2081,s/48008aud
0
E';-1024
1.67ms/6008aud
128"s/7812.5Baud
1.024ms/976.68aud
6.67ms/1508aud
4096ms12441 Baud
0
1
1
E-7·4096
I
-
-
-
..
..
104.2 I lS/9600Baud
833.3"s/1200Baud
3333ms/300Baud
..
.. When SS2 is "I", Timer 2 provides SC'I cio~ks. fhe haud rate is shown as follows with the TCONR as N.
Baud Rate =
f
32 (N+ I)
(
f: i~put clock frequency to the)
"mer 2 counter
N = 0 - 255
(2) Clocked Synchronous Mode·
4.0MHz
6.0MHz
8.0MHz
1.0MHz
1.5MHz
2,OMHz
0
E
E';-2
2lls/bit
1.33"slbit
1"slbit
I
E';-16
16"s/bit
10.7"s/bit
0
E';-128
128"s/bit
512Jls/bit
85.3"slblt
8"s/bit
64.us/bit
341 "s/bit
256"s/bit
X TAL
SS2
SS1
SSO
0
0
0
0
0
E';-512
0
....
....
.. ..
.. Bit rates in the case of internal clock operation. In the case of external clock operation, the external clock is
operatable up to DC - 1/2 system clock .
.... The bit rate is shown as follows with the TCONR as N.
Bit Rate (loiS/bit) = 4
(~+ I)
(
f: input clock frequency to the)
timer 2 counter
N = 0 - 255
Table 8 Baud Rate and Time Constant Register Example
~L
Baud Rate (Bau
110
150
300
600
1200
2400
4800
9600
19200
38400
2.4576MHz
3.6864MHz
4.0MHz
4.9152MHz
8.0MHz
21'
127
63
31
15
7
32'
191
95
47
23
11
5
2
35'
207
103
51
25
12
43'
255
127
63
31
15
7
70'
51'
207
103
51
25
12
-
-
3
-
1
0
3
1
0
-
-
-
-
.. E/B clock is input to the timer 2 up counter and E clock otherwise.
502
~HITACHI
Hitachi America Ltd, • 2210 O'Toole Ave, • San Jose, CA 95131 • (408) 435-8300
~~~~~~~~~~~~~~~~~~~~~~~~HD6303Y.HD63A03Y.HD63B03Y
clock source of the SCI.
Bit 2
Bit 3
Bit 4
CCO
CC1
CC2
Bit 0
Clock Control/Format Select·
Bit 1
These bits control the data format and the clock source (refer to
Table 9).
• CCO, CCI and CC2 are cleared during reset and the MPU
goes to the clocked synchronous mode of the external clock
operation. Then the MPU automatically set port 2, bit 2 into
the clock input state. When using port 2, bit 2 as an output
port, the DDR of port 2 should be set to "1" and CCI and
CCO to "0" and "1" respectively.
Bit 6
Bit 7
Not Used.
Not Used
Bit 2
Bit 5
5
432
1
TORE
Transmit Data Register Empty
Bit 6
ORFE
Overrun/Framing Error
Bit 7
6
PER Parity Error
This bit is set when the PEN is "1" and a parity error occurs.
It is cleared by reading the RDR after reading the TRCSR2,
when PER=l.
RORF
Receive Data Register Full
* Each flag of the TDRE, ORFE, and RDRF can be read from
either the TRCSRI or TRCSR2.
Transmit/Receive Control Status Register 2
7
PEN Parity Enable
This bit decides whether the parity bit should be generated
and checked in the asynchronous mode or not. If this bit is "0",
the parity bit is neither generated nor checked. If" 1", it is generated and checked. This bit is cleared during reset.
The 3 bits above do not affect the SCI opertion in the clocked
synchronous mode.
Bit 3
Not Used
• Transmit/Receive Control Status Register 2 (TRCSR2)
The TRCSR2 is a 7-bit register which can select a data format in
the asynchronous mode. The upper 3 bits are the same address as
the TRCSRI. Therefore, the RDRF, ORFE and TDRE can be read
by either the TRCSRI or TRCSR2. Bits 0 to 2 of the TRCSR2 are
used for read/write. Bits 4 to 7 are used only for read.
EOP Even/Odd Parity
This bit selects the parity generated and checked when the
PEN is "1". If this bit is "0", the parity is even. If"I", it is odd.
This bit is cleared during reset.
Bit 4
'RDRF'ORFE'TDRE' PER'
SBl Stop Bit length
This bit selects the stop bit length in the asynchronous mode.
If this bit is "0", the stop bit is I-bit. If "1", the stop bit is 2-bit.
This bit is cleared during reset.
0
- , PEN' EOP' SBll
$OOlE
•
TIMER. SCI STATUS FLAG
Table 10 shows the set and reset conditions of each status flag in
the timer 1, timer 2 and SCI.
Table 9 SCI Format and Clock Source Control
CC2
CCl
CCO
Format
Mode
Clock Source
Port 2, Bit 2
0
0
0
0
1
1
0
0
1
1
0
0
a-bit data
a·bit data
External
Internal
Input
Not Used"
a-bit data
Clocked SynChronous
Asynchronous
Asynchronous
Internal
Output'
a-bit data
Asynchronous
External
Input
a·bit data
7-bit data
Clocked Synchronous
Internal
Asynchronous
Internal
Output
Not Used"
1
1
0
1
0
1
0
1
0
7-bit data
Asynchronous
Internal
Output"
1
1
7-bit data
Asynchronous
External
Input
,
Port 2, Bit 3
I
Port 2, Bit 4
When the TRCSR1, RE bit is "1",
bit 3 is used as a serial input.
When the TRCSR 1, TE bit is ",",
bit 4 is used as a serial output.
• Clock output regardless of the TRCSR 1, bit RE and TE .
•• Not used for the SCI.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
503
HD6303Y,HD63A03Y,HD63B03Y----------------------------------------------Table 10 Timer 1, Timer 2 and SCI Status Flag
Clear Condition
Set Condition
P6CSR
IS FLAG
Falling edge input to PS4 (is)
ICF
FRC -- ICR by Rising or Falling edge input to
P20
(Selecting with the IEDG bit)
OCRl = FRC
OCFl
Timer
1
Timer
2
OCF2
OCR2 = FRC
TOF
FRC = $FFFF+ 1 cycle
CMF
T2CNT = TCONR
Read the P6CSR then read or write the
PORT6, when IS FLAG = 1
2.
RES = 0
1.
Read the TCSR 1 or TCSR2 then ICRH,
when ICF = 1
2.
RES = 0
1.
Read the TCSRl or TCSR2 then write to
the OCRl H or OCRl L, when OCFl = 1
2.
RES=O
1.
Read the TCSR2 then write to the OCR2H
or OCR2L, when OCF2 = 1
2.
RES = 0
1.
Read the TCSRl then FRCH, when
TOF= 1
2.
m=O
1.
Write "0" to CMF, when CMF = 1
2.
RES = 0
1.
Read the TRCSRl or TRCSR2 then RDR,
when RDRF = 1
RDRF
Receive Shift Register -- RDR
2.
RES= 0
ORFE
1.
Framing Error (Asynchronous Mode)
Stop Bit = 0
1.
Read the TRCSR 1 or TRCSR2 then RDR, when
ORFE = 1
2.
Overrun Error (Asynchronous Mode)
Receive Shift Register -- RDR when
RDRF = 1
2.
~=O
1.
Asynchronous Mode
TOR --+ Transmit Shift Register
Read the TRCSR 1 or TRCSR2 then write to the
TOR, when TORE = 1
2.
Clocked Synchronous Mode
Transmit Shift Register is "empty"
3.
"RES" =
SCI
TORE
PER
(Note) - ; Transfer = ; equal
504
1.
0
Parity when PEN= 1
1.
2.
ICRH; Upper byte of ICR
OCR1H; Upper byte of OCR1
OCR2H; Upper byte of OCR2
Read the TRCSR2 then RDR, when PER= 1
m=O
OCR 1L; Lower byte of OCR 1
OCR2L; Lower byte of OCR2
FRCH; Upper byte of FRC
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
This sleep mode is effective to reduce the power dissipation for a
system with no need of the HD6303Y's consecutive operation.
• LOW POWER DISSIPATION MODE
The HD6303Y provides two low power dissipation modes; sleep
and standby.
•. Standby Mode
The MPU goes to the standby mode with the""STBY "Low" or
by clearing the STBY flag. In this mode, the HD6303Y stops all the
clocks and goes to the reset state. In this mode, the power dissipation is reduced to several p.A. During standby, all pins, except the
power supply (Vee, Vss ), the STBY, RES and XTAL (which outputs "0"), go to the high impedance state. In this mode, power
(Vee) is supplied to the HD6303Y, and the contents of RAM is retained. The MPU returns from this mode during reset. When the
MPU goes to the standby mode with STBY "Low", it will restart at
the timing shown in Fig. 27(a). When the MPU goes to the standby
mode by clearing the STBY flag, it will restart only by keeping the
RES "Low" for longer than the oscillating stabilization time. (Fig.
27(b»
• Sleep Mode
The MPU goes to the sleep mode by SLP instruction execution.
In the sleep mode, the CPU stops its operation, while the registers'
contents are retained. In this mode, the peripherals except the CPU
such as timers, SCI, etc. continue their functions. The power dissipation of sleep-condition is one fourth that of operating condition.
The MPU returns from this mode by an interrupt, RES or
STBY; it goes to the reset state by RES and the standby mode by
STBY. When the CPU acknowledges an interrupt request, it cancels
the sleep mode, returns to the operation mode and branches to the
interrupt routine. When the CPU masks this interrupt, it cancels
the sleep mode and executes the next instruction. However, for example, if the timer 1 or 2 prohibits a timer interrupt, the CPU
doesn't cancel the sleep mode because of no interrupt request.
Vee
I'
NMI
HD6303Y
I~~---41
3 RES
111111
STBY
-1
I
I
I
Jr:-
I
2
STBY
IIIIII
~:
I
RES
Ivss
I
1
vss
-I-
Standby Mode
a Save Registers
o RAM/Port 5 Control Register Set
I
~I-
~I
Time
r-.
Restart
(a) Standby Mode by STBY
Vee
HD6303Y
'LS
•
I
I
I
I
I
Standby Mode
OSTBY FLAG
Clear
Vss
I
I
I
I
I
:-
,
I
I
.,'..
:
I
I
"I:
o Oscillator:
Start
~
Time
:
Restart
Vss
(b) Standby Mode by the STBY Flag
Figure 27 Standby Mode Timing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
505
HD6303Y,HD63A03Y,HD63B03Y----------------------------------------------•
TRAP FUNCTION
The CPU generates an interrupt with the highest priority
(TRAP) when fetching an undefined instruction or an instruction
from non-memory space. The TRAP prevents the system-burst
caused by noise or a program error.
• Op Code Error
When fetching an undefined op code, the CPU saves registers as
well as a normal interrupt and branches to the TRAP ($FFEE,
$FFEF). This has the priority next to reset.
f A . °U 7
1&- -
-
-
-
-
-
-
0 -
•
-
-
- -
15
INSTRUCTION SET
The HD6303Y provides object code upward compatible with the
HD6801 to utilize all instruction set of the HMCS6800. It also reduces the execution times of key instructions for throughput improvement.
Bit manipulation instruction, change instruction of the index
register and accumulator and sleep instruction are also added.
The followings are explained here.
CPU Programming Model (refer to Fig. 28)
Addressing Mode
Accumulator and Memory Manipulation Instruction (refer to
Table II)
New Instruction
Index Register and Stack Manipulation Instruction (refer to
Table 12)
Jump and Branch Instruction (refer to Table 13)
Condition Code Register Manipulation (refer to Table 14)
Op Code Map (refer to Table 15)
• Programming Model
Fig. 28 depicts the HD6303Y programming model. The double
accumulator D consists of accumulator A and B, so when using the
accumulator D, the contents of A and B are destroyed.
-
38·'"
fL
,
11
SP
1. 5
PC
7
A
Aceumu'.'''' .nd ,
0, 16·BU Doubte Accumul'IOf' 0
IndtaR-.ister IX)
01
SttckPoint.,ISPI
01
Program Count., fPCI
0
H
•
-
01
1
1. 5
• Address Error
When an instruction fetch is made from the address of internal
register, the MPU generaters an interrupt as well as an op code
error. But on the system with no memory in its external memory
area, this function is not applicable if an instruction fetch is made
from the external non-memory area. Addresses where an address
error occurs are from $0000 to $0027.
This function is available only for an instruction fetch and is not
applicable to the access of normal data read/write.
(Note) The TRAP interrupt provides a retry function differently
from other interrupts. This is a program flow return to the
address where the TRAP occurs when a sequence returns
to a main routine from the TRAP interrupt routine by
RTI. The retry can prevent the system burst caused by
noise, etc.
However, if another TRAP occurs, the program repeats
the TRAP interrupt forever, so the consideration is necessary in programming.
-
I
N Z
V C
Condition Cock R-V i" ... feCR)
Clrry/Bor,ow from MSB
Owrllow
Z.ro
N",li.,.
Interrupt
H.1t CAtry (From Bil3)
Figure 28 CPU Programming Model
the address where a data is stored. 256 bytes ($0 through $255) can
be addressed directly. Execution times can be reduced by storing
data in this area so it is recommended to make it RAM for users'
data .area in configurating a system. This is a 2-byte instruction,
while 3 byte with regard to AIM, OIM, ElM and TIM.
Extended Addressing
In this mode, the second byte shows the upper 8 bit of the data
stored address and the third byte the lower 8 bit. This indicates the
absolute address of 3 byte instruction in the memory.
Indexed Addressing
The second byte of an instruction and the lower 8 bit of the index register are added in this mode. As for AIM, OIM, ElM and
TIM, the third byte of an instruction and the lower 8 bits of the index register are added.
This carry is added to the upper 8 bit of the index register and
the result is used for addressing the memory. The modified address
is retained in the temporary address register, so the contents of the
index register doesn't change. This is a 2-byte instruction except
AIM, OIM, ElM and TIM (3-byte instruction).
Implied Addressing
An instruction itself specifies the address. This is, the instruction
addresses a stack pointer, index register, etc. This is a one-byte instruction.
Relative Addressing
The second byte of an instruction and the lower 8 bits of the program counter are added. The carry or borrow is added to the upper
8 bit. So addressing from -126 to + 129 byte ofthe current instruction is enabled. This is a 2-byte instruction.
(Note) CLI, SEI Instructions and Interrupt Operation
When accepting the IRQ at a preset timing with CLI and
SEI instructions, more than 2 cycles are necessary between the CLI and SEI instructions. For example, the following program (a)(b) don't accept the IRQ but (c) accepts it.
• CPU Addressing Mode
The HD6303Y provides 7 addressing modes. The addressing
mode is determined by an instruction type and code. Tables 11
through 15 show addressing modes of each instruction with the execution times counted by the machine cycle.
When the clock frequency is 4MHz, the machine cycle time becomes microseconds directly.
CLI
SEI
CLI
NOP
SEI
CLI
NOP
NOP
SEI
(a)
(b)
(c)
Accumulator (ACCX) Addressing
Only an accumulator is addressed and the accumulator A or B is
selected. This is a one-byte instruction.
Immediate Addressing
This addressing locates a data in the second byte of an instruction. However, LDS and LDX locate a data in the second and third
byte exceptionally. This addressing is a 2 or 3-byte instruction.
The same thing can be said to the TAP instruction instead
of the CLI and SEI instructions.
Direct Addressing
In this addressing mode, the second byte of an instruction shows
506
$HITACfll
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
Table 11
Accumulator, Memory Manipulation Instructions
Condition Codlt
Addressing Modes
Operations
Add
Mnemonic
IMMED
DIRECT
INDEX
Register
EXTEND
OP
-
#
OP
-
ADDA
BB
2
2
9B
ADDB
CB
2
2
C3
3 3 03 4 2 E3 5 2 F3 5 3
Add Double
ADDD
Add Accumulators
ABA
Add With Carry
ADCA
-
-
IMPLIED
OP
3
2
AB
4
2
BB
4
3
A+M- A
DB 3
2
EB
4
2
FB
4
3
B+M-B
#
OP
-
#
#
OP
Boolean/
Arithmetic Operation
A
lB
A9
4
2
2
E9
4
3 2
A4
4
B9
2
2 99
3
2
3
#
1
1
4
3
2
F9
4
3
B+M+C-B
2
B4
4
3
A·M-A
C9
2
2
B4
2
2 94
ANDB
C4
2
2
04
3
2
E4
4
2
F4
4
3
B·M-B
Bit Test
BIT A
85
2
2 95
3
2
A5
4
2
B5
4
3
A·M
BIT B
C5
2
2
05
3
2
E5
4
2
F5
4
3
6F
5
2
7F
5
3
Clear
Compare
09
CLR
B·M
00 - M
CLRA
4F
1
1 00 - A
CLRB
5F
1
1 00 - B
CMPA
81
CMPB
Cl
Compere
Accumulators
CBA
Complement.l·s
COM
2
'2
2 91
3
2
AI
4
2
Bl
4
3
A-M
01
3
2
El
4
2
Fl
4
3
B-M
63
6
2
73
6
3
60
6
2
70
6
3
2
11
COMA
COMB
1
1
1
1
1 B -B
B
I
S
oo-M-M
Complement.2·s
NEG
(Negate I
NEGA
NEGB
40
1
1 OD-A-A
50
1
1 oo-B-B
Decimal Adjust. A
oAA
19
2 1 characters ,nto BCD format
Decrement
DEC
oECA
4A
1
1
oECB
5A
1
1 B-l-B
Exclusive OR
Increment
SA
6
2
7A
6
Converts b,nary add of BCD
M -1-M
3
A-I - A
A@M-A
EORA
88
2
2 98
3 2
AS 4
2
BB
4
3
EORB
C8
2
2
3
E8
4
2
F8
4
3
B @M- B
6C
6
2
7C
6
3
M+l-M
08
2
INC
,
INCA
4C
1
INCB
5C
1 1 B + 1- B
A +1- A
LDAA
86
2
2 96
3
2
A6
4
2
B6
4
3
M-A
LoAB
C6
2
2
06
3
2
E6
4
2
F6
4
3
M-B
Loed Double
Accumulator
Loo
CC
3
3
DC 4
2
EC
5
2
FC
5
3
M + 1 - B. M- A
Multiply Unsigned
MUL
OR. Inclusive
ORAA
Loed
Accumulator
ORAB
Push Data
Pull Data
Rotate Left
3D
8A
CA
2
2
2
2
9A
3
DA 3
2
AA 4
2
EA 4
BA 4
3
A+M- A
2
FA 4
3
B +M- B
PSHA
36
37
4
4
1
PSHB
PULA
32
3
1 SP + 1 - SP. Mill - A
PULB
33
3 1 SP + 1 - SP. Mill - B
49
1
ROL
69
6
2
79
6
1
59
1 1
RORA
46
1
1
RORB
56
1
1
ROR
66
6
2
76
6
3
(Note) Condition Code Register will be explained in Note of Table 14.
$
A - Mill. SP - 1 - SP
1 B - Mill. SP - 1 - SP
3
ROLB
Rotate Right
7 1 AxB-A:B
2
ROLA
~l~"""
8
C
1 0
··
· ··
··
·· ·· ··
··· ··· ··
··· ···
··· ···
·· ··
·· ··
·· ··
·· ·· .
·· ·· ·
·· ·· ·
··· ··· ·
·· ·· ··
·· ·· · · ·
·· ·· · · · ··
··· ··· ··· ··· ··· ···
n4l · ·
·· ··
~ ··
·· ··
I
I
S I
S I
S S
: I
I S
I I
I I
I I
I S
I
S
S
I S
S S
S S
I
S S
R
R
R
R
R
S R R
R
S R R
I
S I
A -A
1
2
I
A-B
43
3
N Z V C
R S R R
M-M
53
I
S
A+M+C-A
B9
ANDA
H
I
B+M:M+l-A
ADCB
4
I
A + B- A
AND
5
b7
:}
I.o--i
I
8
C b7
I
I
S
S S I
I
S
I
S
S
I
S
S R S
I R S
S R S
I
S
I IIIII
bO
s . SP - 1 - SP
XH - Mil>. SP - 1 ... SP
4 1 SP+ 1- SP. M",- X H
Exchange
XGDX
18
2
Add
Push Data
SP+l-SP.M.. -X L
1 ACeD··IX
Condition Code
Register
5 4 3 2 1 0
H I N Z V C
1 I t I
··· ··· ·· ··· ··
·· ·· ·· ··· ··
·· · ··
·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
······
I
I
CI,
I
R
I
I
• "L
• 17 I
R
R
• CD
R
••••••
(Note) Condition Code Register will be explained in Note of Table 14.
~HITACHI
\ Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
509
HD6303Y,HD63A03Y,HD63B03Y
~~~~~~~~~~~~~~~~~~~~~~~
Table 13 Jump, Branch Instruction
Addressing Modes
Mnemonic
Operttions
RELATIVE
OP
DIRECT
INDEX
EXTEND
IMPLIED
OP
OP
-
Branch Test
-
#
3
2
Non.
3
2
C-O
3 2
C- 1
3 2
3 2
Z- 1
N (±) V- 0
Z + IN (±) VI- 0
OP
-
#
OP
-
#
#
-
#
Brench Alweys
BRA
Brench N.wr
BRN
20
21
Brench If Cerry CI.r
BCC
24
Branch If Cerry Set
BCS
BEQ
25
27
Brench If > Z.ro
BGE
BGT
2C
2E
Br.nch If Higher
BHI
Brench If .. Z.ro
BLE
22
2F
3 2
Z + IN (±) VI- 1
Brench If Lo_r Or
Sem.
BLS
23
3 2
C+Z - 1
Branch If < Zero
BLT
20
3
2
N (±) V-I
Brench If Minus
BMI
2B
3
2
N- 1
Branch If Not EQuel
Z.ro
BNE
26
3
2
z-o
Branch If Overflow
Brench If - Zero
Br.nch If .. Zero
3 2
3
None
2
C+Z-O
3 2
BVC
2B
3
2
V-O
Branch If Owrflow Set
BVS
29
3 2
V -I
Branch If Plus
BPL
2A
3
N-O
Brench To Subroutine
BSR
80
5 2
Jump
JMP
Jump To Subroutln.
JSR
CIe"
2
90 5
6E 3
2 AD 5
2 7E 3 3
2 BD 6 3
1 1
No Operation
NOP
01
Return From Interrupt
RTI
3B 10 1
R.tum From
Subroutine
5of_e Interrupt
RTS
39
SWI
WAI
SLP
3F 12 1
3E 9 1
lA 4 1
Weh for Int.rrupt"
. SIMP
5
-
Advtnctl Prog. Cntr.
Only
1
Condition Code
R-Sist.r
5 4 3 2 1 0
H I N Z V C
···· ·· ·· ·· ··
··· ··· ······ ······
·· ·· ·· ·· ·· ··
··· ··· ··· ··· ······
·· ·· ·· ·· ·· ··
· · ··· ·
·· ·· ·· ·· ·· ··
·· ·· ·· ···· ··
··· ··· ··· ··· ··· ···
··· ·· ·· ·· ··
•· • • •· •·•·
--@--
S
.j) •
(Note) • WAI puts RIW high; Address Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of Table 14.
510
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
Table 14 Condition Code Register Manipulation Instructions
r'ddressingModes
Operations
Mnemonic
Condition Code Register
Boolean Operation
IMPLIED
-
OP
#
Clear Carry
CLC
OC
1
1
O .... C
Clear Interrupt Mask
CLI
Clear Overflow
3
2
1
I
N
Z
V
0
C
·· · ·· ·· ·· ·
·· ·· ·· ·· · ·
· · ·· ·· · ··
······
R
OE
1
1
0-1
CLV
OA
1
1
O-V
SEC
00
1
1
1 -C
Set Interrupt Mask
SEI
OF
1
1
1-1
Set Overflow
SEV
OB
1
1
1 -V
Accumulator A .... CCR
TAP
06
1
1
A- CCR
CCR .... Accumulator A
TPA
07
1
1
CCR- A
R
S
e
S
S
---
il}---
CONDITION CODE SYMBOLS
OP
Operation Code (Hexadecimal!
Number of MCU Cycles
MSp Contents of memory location pointed by Stack Pointer
#
Number of Program Bytes
Arithmetic Plus
Arithmetic Minus
•
Boolean AND
+
Boolean Inclusive OR
e Boolean Ex~lusive OR
M Complement of M
Transfer into
OBit = Zero
00 Byte = Zero
(Note)
4
H
R
Set Carry
LEGEND
5
H
I
N
Z
V
C
R
5
Half-carry from bit 3 to bit 4
Interrupt mask
Negative (sign bit!
Zero (byte)
Overflow, 2's complement
Carry/Borrow from/to bit 7
Reset Always
Set Always
Set if true after test or clear
Not Affected
t
•
Condition Code Register Notes: (Bit set if test is true and cleared otherwise)
(Bit V)
Test: Result = 10000000?
(i)
(Bit C)
Test: Result ~ 00000000?
®
(Bit
(Bit
(Bit
(Bit
(Bit
(All
Test:
Test:
Test:
Test:
Test:
Load
(9)
@)
@
(Bit I)
(All Bit)
(Bit C)
@
@
@
®
®
(J)
C)
V)
V)
V)
N)
Bit!
BCD Character of high-order byte greater than 10? (Not cleared if previously set)
Operand = 10000000 prior to execution?
Operand = 01111111 prior to execution?
Set equal to N~ C = 1 after the execution of instructions
Result less than zero? (Bit 15=1)
Condition Code Register from Stack.
Set when interrupt occurs. If previously set. a Non-Maskable Interrupt is required to exit the wait state.
Set according to the contents of Accumulator A.
Result of Multiplication Bit 7=1? (ACCB)
Table 15 OP-Code Map
OP
ACC
ACC
CODE
A
B
0011
0100
0101
0110
3
4
5
6
~
lO
0000
0001
0
1
0010
0000
0
~
SBA
2
BRA
0001
1
NOP
CBA
BRN
INS
0010
2
BHI
PULA
BlS
PUlB
BCC
DES
0011
0100
~ ~
3 ~ ~
4 lSRD ~
5 ASlO ~
TSX
BCS
TXS
6
TAP
TAB
BNE
PSHA
0111
7
TPA
TBA
BEQ
PSHB
1000
8
INX
XGOX BVC
PUlX
0101
0110
1001
9
DEX
OAA
BVS
RTS
1010
A
ClV
SlP
BPl
ABX
1011
B
SEV
ABA
BMI
RTI
1100
C
ClC
~
~
~
BGE
PSHX
~
1101
0
SEC
1110
E
ClI
1111
F
SEI
0
I
UNDEFINED OP CODE
BlT
MUl
BGT
WAI
BlE
SWI
2
3
------------
---
INO
I~
0111
1000
I
1001
I
1010
I
1011
1100
I
I
7
8
1
9
1
A
1
B
C
1
IMM 1 OIR
IMM
OIR
1101
o
or X
liND 1 EXT
1 1110 1 1111
I
E
1
F
SUB
0
AIM
CMP
1
OIM
SBC
2
COM
AD DO
SUBO
3
AND
lSR
ElM
ROR
~I
ASR
4
BIT
5
lOA
6
~·I
STA
7
STA
ASl
EOR
ROl
ADC
9
DEC
ORA
A
TIM
8
ADD
INC
B
CPX
TST
BSR
I
~l
JSR
~I
6
lOD
7
8
1
I
0
lOX
--------I
STS
9
C
STO
lOS
JMP
ClR
5
liND 1 EXT
NEG
~ ~
4
Aces
ACCA or SP
OIR
A
I
B
C
1
E
STX
o
I
E
F
I
F
c::2::l
• Only each instructions of AIM, OIM. ElM, TIM
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
511
HD6303Y,HD63A03Y,HD63B03Y----------------------------------------------and port states.
• CPU OPERATION
• CPU Instruction Flow
When operating, the CPU fetches an instrution from a memory
and executes the required function. This sequence starts with RES
cancel and repeats itself limitlessly if not affected by a special instruction or a control signal. SWI, RTI, WAI and SLP instructions
change this operation, while NMI, IRQl, IRQ2, IRQs, HArT and
STBY control it. Fig. 29 gives the CPU mode transition and Fig. 30
the CPU system flow chart. Table 16 shows CPU operating states
• Operation at Each Instruction Cycle
Table 17 shows the operation at each instruction cycle. By the
pipeline control of the HD6303Y, MULT, PUL, DAA and XGDX
instructions, etc. prefetch the next instruction. So attention is necessary to the counting of the instruction cycles because it is different
from the usual one-from op code fetch to the next instruction op
code.
Figure 29 CPU Operation Mode Transition
Table 16 CPU Operation State and Port, Bus, Control Signal State
Reset
STBY'3
HALT
Ao-A7
H
T
T
H
Port 2
T
T
Keep
Keep
Do - 0 7
T
T
T
T
As -A'5
Port 5
H
T
T
H
T
T
Keep
Keep
Port 6
T
T
Keep
Keep
Control Signal
·1
T
·2
·1
Port
·1
·2
·3
512
Sleep
RD, WR, R/W, DR = H, SA = L
Mi, WR, RiW = T, ITIf. SA = H
E pin goes to high impedance state.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
~
;!;
s-o
:2':
»
3
~
~
o·
$l)
II
STACK
PC. IX
ACC...
r
~
•
INote)
I\)
~
0
0
c}
1. The program sequence will come to the RES start from
any place of the flow during RES. When STBY=O. the
sequence will go into the standby mode regardless of the CPU
condition.
2. Refer to "FUNCTIONAL PIN DESCRIPTION" for more
details of interrupts.
~~
~:I
.CD
-~
• )Ii
CJ)(")
~ 1:
c...
0
en
51>
()
»
<0
01
~
::c
c
•
~
0)
CAl
0
ow
IN
$
~
:<
eN
::c
c
01
00
0)
eN
0
0
CAl
»
o
CAl
:<
::c
c
0)
Figure 30 HD6303Y System Flow Chart
1II
Co)
CAl
OJ
o
CAl
-<
Table 17 Cycle-by-Cycle Operation
Address Mode &
Instructions
IMMEDIATE
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SUB
SBC
ADDD CPX
LDD
LOS
LOX
SUBD
DIRECT
ADC
AND
CMP
LOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
CPX
LOS
SUBD
STD
STX
STS
1
2
Op Code Address + 1
Op Code Address + 2
1
1
0
0
1
1
1
0
Operand Data
Next Op Code
1
2
3
Op Code Address + 1
Op Code Address+2
Op Code Address + 3
1
1
1
0
0
0
1
1
1
1
1
0
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
1
2
3
Op Code Address+ 1
Address of Operand
Op Code Address+ 2
1
1
1
0
0
0
1
1
1
1
1
0
Address of Operand (LSB)
Operand Data
Next Op Code
1
2
3
1
2
3
4
1
2
3
4
1
2
3
4
Op Code Address+ 1
Destination Address
Op Code Address + 2
Op Code Address + 1
Address of Operand
Address of Operand + 1
Op Code Address + 2
Op Code Address+ 1
Destination Address
Destination Address+ 1
Op Code Address + 2
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Op Code Address+3
Op Code Address + 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
Op Code Address+3
1
0
1
1
1
1.
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
1,
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
Destination Address
Accumulator Data
Next Op Code
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (LSB)
Restart Address (LSB)
Return Addrf!ss (LSB)
Return Address (MSB)
First Subroutine Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
2
3
3
3
ADDD
LDD
LOX
4
4
JSR
5
5
TIM
4
AIM
OIM
Data Bus
Address Bus
ElM
6
1
2
3
4
1
2
3
4
5
6
1
1
1
0
1
1
1
1
1
0
(Continued)
514
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
,
Address Mode &
Instructions
Address Bus
INDEXED
JMP
3
ADC
AND
CMP
LOA
SBC
TST
STA
ADD
BIT
EOR
ORA
SUB
4
4
1
2
3
1
2
3
4
1
2
3
4
ADDD
CPX
LOS
SUBD
STD
STX
LDD
LOX
5
1
2
3
4
5
STS
5
1
2
3
4
5
1
2
JSR
5
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
3
4
5
1
2
3
4
5
6
TIM
5
1
2
3
4
5
CLR
5
AIM
OIM
1
2
3
4
5
1
ElM
2
3
7
4
5
6
7
Data Bus
Op Code Address+ 1
FFFF
Jump Address
Op Code Address + 1
FFFF
IX-+: Offset
Op Code Address+2
1
1
1
1
1
1
1
0
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address+2
Op Code Address + 1
FFFF
IX + Offset
IX+Offset+ 1
Op Code Address+2
Op Code Address + 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address+2
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-1
IX+Offset
Op Code Address + 1
FFFF
IX + Offset
FFFF
IX + Offset
OP Code Address + 2
Op Code Address + 1
Op Code Address+2
FFFF
IX + Offset
Op Code Address+3
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset
Op Code Address+2
Op Code Address+ 1
Op Code Address+2
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+3
1
1
0
0
1
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
0
0
1
0
1
1
0
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
0
1
0
1
0
Offset
Restart Address (LSB)
First Op Code of Jump Routine
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Immediate Data
Offset
Restart Address (LSBj
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data
00
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
515
Address Mode &
Instructions
Data Bus
Address Bus
EXTEND
JMP
3
ADC
AND
CMP
LOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
TST
4
1
2
3
1
2
3
4
4
1
2
3
4
ADDD
CPX
LOS
SUBD
STD
STX
LDD
LOX
5
1
2
3
4
5
STS
5
1
2
3
4
5
JSR
6
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
CLR
5
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
Op Code Address + 1
Op Code Address + 2
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
Op Code Address+3
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Op Code Address + 1
Op Code Address+2
Destination Address
Op Code Address+3
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
Op Code Address + 3
Op Code Address + 1
Op Code Address+2
Destination Address
Destination Address + 1
Op Code Address + 3
Op Code Address + 1
Op Code Address+2
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
FFFF
Address of Operand
Op Code Address + 3
Op Code Address+ 1
Op Code Address+2
Address of Operand
Address of Operand
Op Code Address + 3
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
0
0
1
1
1
1
f
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
0
Jump Address (MSB)
Jump Address (LSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Accumulator Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (MSB)
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
00
Next Op Code
(Continued)
516
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
Address Mode &
Instructions
IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
PULA
ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
LSR
ROL
NOP
SEC
SEV
TAP
TPA
TSX
XGDX
Address Bus
1
Op Code Address+ 1
1
a
1
a
Next Op Code
1
2
1
2
Op Code Address + 1
a
Stack Pointer + 1
Op Code Address+ 1
1
1
1
1
1
1
1
a
3
1
1
1
1
1
1
1
Next Op Code
Restart Address (LSB)
Next Op Code
Restart Address (LSB)
Data from Stack
Next Op Code
Restart Address (LSB)
Accumulator Data
Next Op Code
Next Op Code
Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSB)
Next Op Code
Restart Address (LSB)
Index Register (LSB)
Index Register (MSB)
Next Op Code
Next Op Code
Restart Address (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
1
2
PULB
3
PSHA
Data Bus
PSHB
4
PULX
4
1
2
3
4
1
2
3
4
1
2
PSHX
5
3
4
5
1
2
RTS
5
3
4
5
1
2
MUL
7
3
4
5
6
7
FFFF
Op Code Address + 1
FFFF
FFFF
Stack Pointer
Op Code Address+ 1
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Op Code Address+ 1
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Return Address
Op Code Address + 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
a
1
1
1
1
1
1
1
a
a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
a
1
a
a
1
1
a
a
1
a
a
a
1
1
1
a
a
1
a
a
a
a
1
1
1
1
1
1
a
1
a
1
1
1
1
1
1
1
1
1
1
1
1
a
a
1
1
1
1
1
1
1
1
1
1
1
1
1
a
a
a
1
1
1
1
1
1
1
1
1
1
1
a
0
1
1
1
1
1
1
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
517
Address Mode &
Instructions
Address Bus
Data Bus
IMPLIED
WAI
9
1
2
3
4
5
6
7
8
9
RTI
10
1
2
3
4
5
6
7
8
9
10
SWI
1
12
2
3
4
5
6
7
8
9
10
11
12
1
2
SLP
4
1
1
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer-5
Stack Pointer - 6
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer+3
Stack Pointer +4
Stack Pointer + 5
Stack Pointer+6
Stack Pointer + 7
Return Address
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer - 5
Stack Pointer-6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address + 1
FFFF
Sleep
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
j
j
j
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
~
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accu,mulator A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (LSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (LSB)
First Op Code of SWI Routine
Next Op Code
Restart Address (LSB)
3
4
FFFF
Op Code Address + 1
1
1
1
0
1
1
0
Restart Address (LSB)
Next Op Code
1
2
Op Code Address + 1
FFFF
1Branch Address··· .. ·Test=·.,..
Op Code Address +l .. ·Test="Q"
1
1
0
1
1
1
1
1
1
0
1
0
Branch Offset
Restart Address (LSB)
First Op Code of Branch Routine
Next Op Code
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Branch Address
1
1
0
0
1
0
1
1
1
1
0
0
1
1
1
1
1
0
RELATIVE
BCC
BEQ
BGT
BLE
BlT
BNE
BRA
BVC
BSR
BCS
BGE
BHI
BLS
BMT
BPL
BRN
BVS
3
3
5
518
1
2
3
4
5
1
0
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Op Code of Subroutine
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6303Y,HD63A03Y,HD63B03Y
•
PRECAUTION TO THE BOARD DESIGN OF OSCILLATION CIRCUIT
As shown in Fig. 31, there is a case that the cross talk disturbs the normal oscillation if signal lines are put near the
oscillation circuit. When designing a board, pay attention to
this. Crystal and CL must be put as near the HD6303Y as
possible.
x
E
E
E
o
N
-.L
64
XTAL
EXTAL
HD6303Y
HD6303Y
Do not use this kind of print board design.
Figure 31
(Top View)
Precaution to the boad design
of oscillation circuit
Figure 32 Example of Oscillation Circuits in Board Design
•
RECEIVE MARGIN OF THE SCI
Receive margin of the SCI contained in the HD6303Y is
shown in Table 18.
Note: SCI = Serial Communication Interface
Table 18
HD6303Y
4
START
6
Bit distortion
tolerance
(t-to) Ito
Character
distortion tolerance
(T-To) ITo
±43.7%
±4.37%
8
STOP
Ideal Waveform
Bit length r-to--j
1
I 0 0 . _ - - - - - - - - - Character length To - - - - - - - - - Real Waveform
1 4 - - - -_ _
T-~t-i--~.1
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
519
HD6305UO ,HD63A05UO , - - HD63B05UO
CMOS MCU (Microcomputer Unit)
-PRELIMINARYThe HD6305VO is a CMOS 8-bit single-chip MCV which is
similar to the HD6305X MCV family. This version is upward
compatible with the HD6805 family in respect to instructions. A
CPU, a clock generator, a 2k-byte ROM, a 128-byte RAM, 31 1/
o terminals, two timers, and a serial communication interface
(SCI) are incorporated in the HD6305UO. As a result of CMOS
technology, the HD6305UO consumes much less power than
NMOS counterparts. In addition, three low power dissipation
modes (stop, wait and standby) which further decreases power
consumption, are included in the HD6305UO.
Other notable features include enhanced instruction cycle of
the main instructions and the use of three additional instructions
to improve system throughput.
HD630SUOP, HD63AOSUOP,
HD63BOSUOP
(DP-40)
• HARDWARE FEATURES
• CMOS 8-bit single-chip MCU
• 2048 bytes of ROM
• 1 28 bytes of RAM
• 31 bidirectional I/O terminals
• Two timers
8-bit timer with a 7 -bit prescaler (programmable prescaler; event counter)
1 S-bit timer (commonly used with the SCI clock divider)
• On-Chip serial interface circuit (synchronized with clock)
• Six interrupts (two external, two timer, one serial and one
software)
• Low power dissipation modes
- Wait ....... In this mode, the clock oscillator is on and
the CPU halts but the timer/serial/interrupt
function is operatable. Also, all registers are
held, except the I bit in the condition code
register is cleared.
- Stop ....... In this mode, the clock stops but the RAM
data, I/O status and registers are held. Except the timer control register (bits 6 and 7)
and the I bit of the condition code register.
- Standby .... In this mode, the clock stops, the RAM data
is held, and the other internal condition is reset.
• Minimum instruction cycle time
HD630SUO ...... 1 IJ-s (f = 1 MHz)
- HD63AOSUO ..... 0.67 IJ-s (f = 1.S MHz)
- HD63BOSUO ..... O.S IJ-s (f = 2 MHz)
• Wide operating range
Vee = 3 to 6V (f = 0.1 to O.S MHz)
HD630SUO ...... f = 0.1 to 1 MHz
(Vee = 5V ± 100/0)
HD63AOSUO ..... f = 0.1 to 1.S MHz
(Vee = SV ± 10%)
... f = 0.1 to 2 MHz
HD63BOSUO
(Vee = SV ± 10%)
• System development fully supported by an emulator
•
PIN ARRANGEMENT
Vee
EXTAL
XTAL
7 TIMER
STiiY
0./INT2
o,/ff
O./Rx
O./T.
02
0,
Do
eo
c,
C2
C.
c.
Cs
c.
1 C,
(Top View)
• SOFTWARE FEATURES
• Similar to HD6800
• Byte efficient instruction set
• Powerful bit manipulation instructions (Bit Set, Bit Clear, and
Bit Test and Branch usable for all RAM bits and all I/O terminals)
520
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - HD6305UO,HD63A05UO,HD63B05UO
•
•
•
•
•
A variety of interrupt operations
Index addressing mode useful for table processing
A variety of conditional branch instructions
Ten powerful addressing modes
All addressing modes adaptable to RAM. and I/O instructions
•
BLOCK DIAGRAM
•
•
•
Three new instructions. StoP. Wait and DAA, added to the
HD6805 family instruction set
Instructions that are upward compatible with those of Motorola's MC6805P2 and MC 146805G2
Compatible instruction set with HD6305X
XTAl EXTAl RES NUM
INT
STBY
TIMER
Index
Register
Port A
I/O
Terminals
CPU
Control
X
Condition Code
Register
CCR
Stack
Pointer SP
0,
D.
Do
CPU
Program
Counter
"High"PCH
Program
Counter
"low" PCl
Port B
I/O
Terminals
D./lNT,
D,/CK
D./Rx
D,/Tx
Port 0
I/O
Terminals
AlU
Serial
Status
Register
Serial
Data
Register
Port C
I/O
Terminals
• ABSOLUTE MAXIMUM RATINGS
Item
Supply voltage
I nput voltage
Symbol
Value
Unit
VCC
-0.3-+7.0
V
-0.3 -
V in
Vcc
+ 0.3
V
Operating temperature
Topr
0-+70
°c
Storage temperature
T stg
-55 - +150
°c
[NOTE]
These products have a protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding,
be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normal
operation. we recommended Vin. V out ; Vss ~ (V in or V out ) ~ Vee.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
521
H D6305UO, H D63A05UO, H D63B05UO
• ELECTRICAL CHARACTERISTICS
• DC Characteristics (Vee
=5.0V ± 10%, VSS =GND and Ta = 0 '""" +70°C unless otherwise specified)
Input
voltage
"High"
Test
condition
Symbol
Item
RES.STBY
EXTAL
VIH
Others
Input volt·
age "Low"
VIL
All Inputs
Operating
Current *
dissipation
Wait
f = 1MHz**
lee
Stop
Standby
Input
leakage
current
TIMER,
INT,
SfBY
Threestate
current
Ao '""" A 7 ,
Bo '""" B 7 ,
Co'""" C 7 ,
Do'""" D6
IITSII
Input
capacity
All
terminals
Cin
IIILI
Item
typ
max
Unit
V
Vee- 0 .5
-
Vee+ 0.3
Vee x 0.7
-
Vee+ 0.3
V
2.0
-
Vee+ 0.3
V
-0.3
-
0.8
V
-
5
10
mA
2
5
mA
-
2
10
/lA
-
2
10
/lA
-
-
1
/lA
-
-
1
Il A
-
-
12
pF
Yin = 0,5 '"""
Vee - 0.5V
f = 1MHz,
Yin =OV
* V 1H min ~ Vee-1.0V, VIL max ~ 0,8 V
"The value at f = xMHz can be calculated by the following equation: ICC
• AC Characteristics (Vee
min
(f
= xMHz) = ICC If = 1MHz) multiplied by x
=5.0V ± 10%, Vss = GND and Ta = 0 '""" +70°C unless otherwise specified)
Symbol
Test
condition
HD6305UO
min
typ
HD63A05UO
max
min
typ
HD63B05UO
max
min
typ
max
Unit
Clock
frequency
fcl
0.4
-
4
0.4
-
6
0.4
-
8
MHz
Cycle time
tcyc
1.0
-
10
0.666
-
10
0.5
-
10
/ls
INT pulse
width
tlWL
tc~c
+2 0
-
-
tcyc
+200
-
-
tcyc
+200
-
-
ns
INT2 pulse
width
tlwL2
tcyc
+250
-
-
tc~c
+ 00
-
-
tCyc
+200
-
-
ns
RES pulse
width
tRwL
5
-
-
5
-
-
5
-
-
tcyc
TIMER pulse
width
tTWL
tcyc
+250
-
-
tcyc
+200
-
-
tcyc
+200
-
-
ns
Oscillation
start time
(crystal)
tose
-
-
20
-
-
20
-
-
20
ms
Reset delay
time
tRH L
80
-
-
80
-
-
80
-
-
ms
522
CL
= 22pF ±
20%
Rs = 60n
max
External cap.
2.2/lF
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - HD6305UO,HD63A05UO,HD63B05UO
• Port Electrical Characteristics (Vee
=5.0V ± 10%, VSS =GND and Ta = 0 -
Item
min
typ
2.4
-
-
V
Vee - 0.7
-
-
V
IOL = 1.6mA
-
-
VIH
2.0
-
Vee + 0.3
V
VIL
- 0.3
-
0.8
V
-
-
1
IlA
VOL
Input voltage "Low"
Ports A,
B,C,D
Input leakage current
Yin
III LI
SCI Timing (Vee
Symbol
Clock Cycle
tScyc
Data Output Delay Time
tTXD
Data Set-up Time
tSRX
Data Hold Time
tHRX
=0.5Vee - 0.5V
= 5.0V±10%, Vss =GND and Ta = 0 -
Item
Unit
IOH = -2OOIlA
Ports A,
B,C,D
Input voltage "High"
max
IOH = -101lA
VOH
Output voltage "Low"
•
Test
condition
Symbol
Output volt·
age "High"
+70°C unless otherwise specified)
Test
Condition
Fig. 1
Fig.2
0.55
V
+70°C unless otherwise specified)
HD6305UO
min
typ
max
HD63A05UO
typ
min
max
1
-
-
-
250
-
200
-
-
200
100
-
-
100
-
32768 0.67
HD63B05UO
min
typ
max
Unit
21845
0.5
-
16384
IlS
250
-
-
250
ns
-
200
-
100
-
-
ns
ns
Vee
Clock Output
TTL Load
(Port)
Test point
terminal
C,ICK
Data Output
IOL= 1 .6mA
2.4kQ
o---~t-----'----foII--.
D,/T.
40pF
12kQ
Data Input
D./Rx
Figure 1 SCI Timing (Internal Clock)
[NOTES 1 1. The load capacitance includes stray capacitance caused
by the probe, etc.
2. All diodes are 152074
Clock Input
Data Output
D,/Tx
®.
o BV
OI/CK
Ir-::-c::-:--++-----..... r---~I---
Figure 3 Test Load
~~-++-----~~---~.I---
•
Dat8 Input
20V
O./Rx
o BV
•
Figure 2
SCI Timing (External Clock)
DESCRIPTION OF TERMINAL FUNCTIONS
The input and output signals of the HD630SUO are described
here.
Vee. Vss
Voltage is applied to the HD6305UO through these two terminals. Vee is S.OV ± 10%, while Vss is grounded .
•
INT,INT 2
External interrupt request inputs to the HD6305UO. For details, refer to "INTERRUPTS". The INT2 terminal is also used
as the port D6 terminal.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
523
HD6305UO,HD63A05UO,HD63B05UO - - - - - - - - - - - - - - - - - - - - - •
o
XTAL,EXTAL
These terminals provide input to the on-chip clock circuit. A
crystal oscillator (AT cut, 2.0 to 8.0 M Hz) or ceramic filter is
connected to the terminal. Refer to "INTERNAL OSCILLATOR" for using these input terminals.
•
TIMER
This is an input terminal for event counter.
"TIMER" for details.
127
128
Refer to
Ir
$007F
RAM
(128Bytes)
Stack
255
256
ao
$gOFF
$ 100
\
Not Used
•
RES
•
NUM
This terminal is not intended for user applications. It must be
grounded to V 5S'
•
InputlOutput Terminals (Ao - 0 6)
A 7 , Bo -
B 7 , Co -
ROM
(2,048Bytes)
C 7 ' Do
8180
These 31 terminals consist of three 8-bit 110 ports (A, Band
C) and a 7-bit 110 port D. Each of these can be used as an input
or output terminal on a bit basis through program control of the
data direction register (DDR). For details, refer to "1/0
PORTS."
Since port D6 is also used for the INT~ input, in order to use
port D6 as an 110 port, the INT~ interrupt mask bit in the
miscellaneous register should be set to "I" to disable the INT~
input.
•
Vectors
A
B
C
0
PORT A DDR
PORT B DDR
PORT C DDR
PORT D DDR
Timer Data Reg
Timer CTRL Reg
Mlsc Reg
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$OA
16
17
18
$lFFF
$2000
SCI CTRL Reg
SCI STS Reg
SCI Data Reg
$10
$11
$12
Not Used
Not Used
$7F
127
$3FFF
16383
STBY
Figure 4 Memory Map of HD6305UO MCU
543 2 1 o
1
Condition
n-4 1 1
n+l
Code Register
7
CK (05)
•
Rx (D.)
•
Tx (0 3 )
Accumulator
n+2
n-2
Index Register
n+3
pcw
n+4
n-1 0 01
Used to receive serial data.
n
Used to transmit serial data.
PCl·
Pull
n+5
Push
MEMORY MAP
• In a subroutine call, only PCL and PCH are stacked.
The memory map of the HD6305UO MCU is shown in Fig. 4.
During interrupt processing, the contents of the MCU registers
are saved into the stack in the sequence shown in Fig. 5. This
saving begins with the lower byte (PCL) of the program counter.
Then the value of the stack pointer is decremented and the higher byte (PCH) of the program counter, index register (X), accumulator (A) and condition code register (CCR) are stacked in
that order. In a subroutine call, only the contents of the program
counter (PCH and PCL) are stacked.
524
I
6
n-3
Used to input or output clocks for serial operation.
•
PORT
PORT
PORT
PORT
Not Used
---------$lFF4
Interrupt
819 1
8192
This terminal is used to place the MCU into the standby
mode. With STBY at "Low" level, the oscillation stops and the
internal condition is reset. For details, refer to "STANDBY
MODE."
The terminals described in the following are 110 pins for serial
communication interface (SCI). They are also used as ports D:1,
D, and D.,. For details, refer to "SERIAL COMMUNICATION
INTERFACE."
•
$17FF
$1800
6143
6144
Used to reset the MCU. Refer to "RESET" for details.
0
1
2
3
4
5
6
7
8
9
10
$0000
I/O Ports
Timer
SCI
Figure 5 Sequence of Interrupt Stacking
•
REGISTERS
There are five registers which the programmer can operate.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6305UO,HD63A05UO,HD63B05UO
o
7
.....________
--11 Accumulator
A
1
7
o
index
.....
1 _ _ _ _X_ _ _ _---' Register
I
~
Zero (Z):
o
13
1
13
Negative (N):
__________________
PC
IProgram
~.Counter
6 5
0
Carry/
Borrow (C):
~1°-Llo~lo~l~o~lo~l_ol~1~1~1~1_____
sp____~I~~~~r
•
~~m;"
Zero
' - - - - - - Negative
'------Interrupt
Mask
l..------Half
Carry
Figure 6
•
Programming Model
Accumulator (A)
This accumulator is a general purpose 8-bit register which
holds operands or the result of arithmetic operation or data
processing.
•
Inden Register (X)
Table 1 Priority of Interrupts
Priority
Program Counter (PC)
The program counter is a 14-bit register that contains the address of the next instruction to be executed.
•
Interrupt
Vector Address
1
RES
$1FFE,
$lFFF
2
SWI
$lFFC,
$1FFD
3
INT
$1FFA,
$lFFB
4
TIMER/INT2
$lFF8,
$lFF9
5
TIMER (WAIT)
$1FF6.
$lFF7
6
SCI/TIMER2
$1FF4,
$lFF5
Stack Pointer (SP)
The stack pointer is a 14-bit register that indicates the address
of the next stacking space. Just after reset, the stack pointer is set
at 'address $OOFF. It is decremented when data is pushed, and incremented when pulled. The upper 8 bits of the stack pointer are
fixed to 00000011. During the MCU being reset or during a reset
stack pointer (RSP) instruction, the pointer is set to address
$OOFF. Since a subroutine or interrupt can use space up to address $OOCI for stacking, the subroutine can be used up to 31
levels and the interrupt up to 12 levels.
•
INTERRUPT
There are six different types of interrupt: external interrupts
(INT, INT,), internal timer interrupts (TIMER, TIMER.,), serial
interrupt (SCI) and interrupt by an instruction (SWI).
Of these six interrupts, the INTl and TIMER or the SCI and
TIMER:! generate the same vector address, respectively. Although, a different vector address is generated for a timer interrupt during the wait mode, as shown in Table 1.
When an interrupt occurs, the program in progress stops and
then the CPU status is saved onto the stack. And then, the interrupt mask bit (I) of the condition code register is set and the
start address of the interrupt processing routine is obtained from
a particular interrupt vector address. Then the interrupt routine
starts from the start address. System can exit from the interrupt
routine by a RTI instruction. When this instruction is executed,
the CPU status before the interrupt (saved onto the stack) is
pulled and the CPU restarts the sequence with the instruction
next to the one at which the interrupt occurred. Table 1 lists the
priority of interrupts and their vector addresses.
The index register is an 8-bit register, and is used for index
addressing mode. Each of the addresses contained in the register
consists of 8 bits which, combined with an offset value, provides
an effective address.
In the case of a read/modify/write instruction, the index register can be used like an accumulator to hold operation data or the
result of operation.
If not used in the index addressing mode, the register can be
used to store data temporarily.
•
lowing the CLI has been executed.)
Used to indicate that the result of the most recent arithmetic operation, logical operation or
data processing is negative (bit 7 is logic" I ").
Used to indicate that the result of the most recent arithmetic operation, logical operation or
data processing is zero.
Represents a carry or borrow that occurred in
the most recent arithmetic operation. This bit is
also affected by the Bit Test and Branch instruction, a shift instruction and a Rotate instruction .
Condition Code Register (CCR)
The condition code register is a 5-bit register, each bit indicating the result of the instruction just executed. The bits can be individually tested by conditional branch instructions. The CCR
bits are as follows:
Half Carry (H): Used to indicate that a carry occurred between
bits 3 and 4 during an arithmetic operation
(ADD, ADC),
Setting this bit causes all interrupts, except a
Interrupt (I):
software interrupt, to be masked. If an interrupt
occurs with the bit I set, it is latched, It will be
processed the instant the interrupt mask bit is
reset. (More specifically, it will enter the interrupt processing routine after the instruction fol-
A flowchart of the interrupt sequence is shown in Fig. 7. A
block diagram of the interrupt request source is shown in Fig. 8.
In the block diagram of Fig. 8, the external interrupt INT. is a
falling edge trigger input, whereas, the external interrupt
can
be configured as a falling edge trigger input or a combination of
falling edge and low level trigger input, depending on the status
of bit 5 in the miscellaneous register (MR). When an interrupt
request is detected at the INT., or INT inputs, an interrupt request is generated and latched.-The INT interrupt request is automatically cleared if jumping is made to the INT processing
routine. Meanwhile, the INT., request is cleared if "0" is written
in bit 7 of the miscellaneous register.
For the external interrupts (INT, I NT.,) , internal timer interrupts (TIMER, TIMER.') and serial interrupt (SCI), each interrupt request is held, bui not processed, if the I bit of the condition code register is set. Immediately after the I bit is cleared, the
corresponding interrupt processing starts according to the priority.
The INT:! interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by setting bit 6 of
the timer control register; the SCI interrupt by setting bit 5 of the
serial status register; and the TIMER:! interrupt by setting bit 4 of
the serial status register.
The status of the INT terminal can be tested by a BIL or BIH
instruction. The INT falling edge and falling edge/low level detec-
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
fiiit
525
HD6305UO,HD63A05UO,HD63B05UO
y
INT
Clear
iNT
INT,
Fetch
Instruction
1 .... 1 Bit
$FF .... SP
TIMER
o .... ODRs
Clear INT Logic
$FO-+TDR
$7F -+ Timer Prescaler
$50-+TCR
$3F -+SSR
SOD -+SCR
$5F -+MR
y
SCI
N
CLI
y
SEI
Load PC From
SWI : $1 FFC. $1 FFD
INT: $1FFA. $1FFB
TIMER: $1FF8. $1FF9
INT,: $1FF8. $1FF9
TIMER (WAIT): $1FF6.
$1 FF7
SCI: $1 FF4. $1 FF5
TIMER,: $1 FF4. $1 FF5
Figure 7
Interrupt Flowchart
tor circuit and its latching circuit are independent of testin~
these instructions. This is also true with the status of the INT"
terminal.
•
Miscellaneous Register IMR; $OOOA)
The external interrupt INT" and the TIMER interrupt have
identical interrupt vector addresses, as shown in Table I. For this
reason, bits 6 and 7 of a special register called the miscellaneous
register (M R: $OOOA) are available to control the [NT" interrupt.
Moreover, bit 5 of the MR controls the sensing mode for the
INT interrupt detector (falling edge detector or falling edge/low
level detector>.
Bit 7 of the MR is the IN~terrupt request flag. When a
falling edge is detected at the INTz terminal, bit 7 is set to "I"
526
Then the interrupt routine software (vector addresses: $lFFS,
$lFF9) checks bit 7 to see if an INT z interrupt occurred. Bit 7
can be reset by software.
Miscellaneous Register 1M R; $OOOA)
L -_ _ _ _ _ _ _ _ _ _ _
L -_ _ _ _ _ _ _ _ _ _ _ _ _
INT, Interrupt Mask
INT 2 Interrupt Request Flag
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H D6305UO, H D63A05UO, H D63B05UO
Bit 6 is the INT, interrupt mask bit. If this bit is set to "1",
then the INT, interrupt is disabled. Both read and write are possible with bit --', but" 1" cannot be written in this bit by software.
In other words, an INT, interrupt request by software is not possible.
Bit 5 is the control bit for INT interrupt detection. If this bit is
reset to "0", the detection logic will detect a falling edge. When
this bit is set to "1", the detection logic will detect a falling edge
or a low level.
When reset, bit 7 is cleared to "0", bit 6 is set to "1" and bit
5 is cleared to "0".
•
TIMER
Figure 9 shows an MCU timer block diagram. The timer data
register is loaded by software and, upon receipt of a clock input,
begins to count down. When the timer data register (TDR) becomes "0", the timer interrupt request bit (bit 7) in the timer
control register is set. In response to the interrupt request, the
MCU saves its status into the stack and fetches the timer interrupt routine addresses $lFF8 and $lFF9 (or $lFF6 and $lFF7
when the timer interrupt occures during the wait mode) and ex-
ecutes the interrupt routine. The timer interrupt can be masked
by setting the timer interrupt mask bit (bit 6) in the timer control register. The mask bit (I) in the condition code register can
also mask the timer interrupt.
The source clock to the timer can be either an external signal
from the timer input terminal or the internal E signal (the oscillator clock divided by 4). If the E signal is used as the source,
the clock input can be gated by the input to the timer input terminal.
Once the timer count has reached 0, it starts counting down
with "FF". The count can be monitored whenever desired by
reading the timer data register. This permits the program to know
the length of time having passed after the occurrence of a timer
interrupt, without disturbing the contents of the counter.
When the MCU is reset or placed in the stop mode, the timer
data register (TDR) is initialized to $FO. The timer interrupt request bit (bit 7) then is cleared and the timer interrupt mask bit
(bit 6) is set.
To clear the timer interrupt request bit (bit 7), it is necessary
to write "0" in that bit.
Condition Code
Register (CCR)
BIH. BIL Test
Falling
Edge
Detector
iNT
Interrupt
Latch
INT
Falling Edge Detector
Vector Address Generated:
$1FFB. $1FF9
TIMER
($1 FF6. $1 FF7 for
~':":":::----------+---------"" TIMER interrupt during
the WAIT mode)
SCIITIMER ,
} - - - - - - ' - - - - - - - - - _ Vector Address Generated:
$1 FF4. $1 FF5
Figure 8
Interrupt Request Generation Circuitry
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
527
HD6305UO,HD63A05UO,HD63B05UO
Table 2
TCR7
Timer interrupt request
o
Absent
Clock Source Selection
TCR
Clock input source
Bit 5
Bit 4
0
0
Internal clock E
Present
•
TCR6
Timer interrupt mask
0
1
E under TIME R terminal control
o
Enabled
1
0
No clock input (counting stopped)
Disabled
1
1
Event input from TIMER terminal
Timer Control Register ITCR; $0009)
Selection of a clock source, selection of a prescaler frequency
division ratio, and a timer interrupt can be controlled by the
timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four modes
(see Table 2) can be selected by bits 5 and 4 of the timer control
register (TCR).
A prescaler division ratio is selected by the combination of
three bits (bits 0, I and 2) of the timer control register (see
Table 3). There are eight different division ratios: + 1, + 2, + 4,
+ 8, + 16, + 32, + 64 and + 128. After reset, the TCR is set to
the + 1 mode.
Table 3
Timer Control Register (TCR; $0009)
TCR
Bit 2
L -_ _ _ _ _ _ _ _ _ _ _
Prescaler Division Ratio Selection
Bit 1
Bit 0
Prescaler division ratio
0
71
0
1
72
1
0
74
0
0
0
0
Timer interrupt mask
L--_ _ _ _ _ _ _ _ _ _ _ _ _ Timer interrupt request
After reset, the TCR is initialized to "E under timer terminal
control" (bit 5 = 0, bit 4 = \). If the timer terminal is "I", the
counter starts counting down with "$FO" immediately after reset.
When "I" is written in bit 3, the prescaler is initialized to
"$7F". This bit always shows "0" when read.
0
1
1
78
1
0
0
716
1
0
1
732
1
1
0
764
1
1
1
7128
Initialize
(Internal
Clock)
E
--1---1
Timer Data
Register
L..._ _-.-_ _ _ _.....-_ _--I Timer Interrupt
Write
Figure 9
Read
Timer Block Diagram
A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "I". When a timer inter-
528
rupt occurs, "I" is set in the timer interrupt request bit. This bit
can be cleared by writing "0" in that bit.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6305UO,HD63A05UO,HD63B05UO
•
ister and data transfer.
SERIAL COMMUNICATION INTERFACE (SCII
This interface is used for serial transmission or reception of 8bit data. Sixteen transfer rates are available in the range from 1
iJ.s to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one eighth counter and
one prescaler. (See Fig. 10.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 3, 4
and 5 of port D. Described below are the operations of each reg-
•
SCI Control Register (SCR; $0010)
SCI Control Registers (SCR; 0010)
E
_
li --,
~"""'"""""""""1r--'
r--
Ds(CK) :
Transfer
Clock
Generator
I
I
I
I
I
I
Initialize
I
I
D4 (Rx) :
-----.
D3 (Tx) :
:.-..--....J
I
L
______ ..J
SCI Status Register
(SSR :$0011)
SCI/TIMER2
Figure 10 SCI Block Diagram
Bit 7 (SCR7)
When this bit is set, the DDR corresponding to the D" becomes" 1" and this terminal serves for output of SCI data. After
reset, the bit is cleared to "0".
D3 terminal
SCR7
o
Used as I/O terminal (by DDR)
Serial data output (DDR output)
SCR6
Bit 6 (SCR6)
When this bit is set, the DDR corresponding to the D~ becomes "0" and this terminal serves for input of SCI data. After
reset, the bit is cleared to "0".
D4 terminal
o
Used as I/O terminal (by DDR)
Bits 5 and 4 (SCR5, SCR4)
These bits are used to select a clock source. After reset, the
bits are cleared to "0".
Serial data input (DDR input)
SCR5 SCR4
Clock source
0
0
-
0
1
-
1
0
Internal
1
1
External
Ds terminal
Bits 3 - 0 (SCR3 - SCRO)
These bits are used to select a transfer clock rate. After reset,
the bits are cleared to "0".
Used as I/O terminal (by
DDR)
Clock output (DDR output)
I Clock input (DDR input)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
529
HD6305UO,HD63A05UO,HD63B05UO
SCR3
SCR2
SCR1
SCRO
Bit 4 (SSR4)
Bit 4 is the TIMER., interrupt mask bit which can be set or
cleared by software. When the bit is "I", the TIMER2 interrupt
(SSR6) is masked. When reset, it is set to "1".
Transfer clock rate
4.00 MHz
4.194 MHz
0
0
0
0
1 /ols
0.95 /ols
0
0
0
1
2/ols
1.91/ols
0
0
1
0
4/ols
3.82/ols
0
0
1
1
8/ols
7.64 /ols
1
I
I
I
I
1
1
1
1
1
32768/ols
1/32 s
Bit 3 (SSR3)
W!1en "1" is written in this bit, the prescaler of the transfer
clock generator is initialized. When read, the bit always is "0".
Bits 2 - 0
Not used.
•
•
SCI Data Register (SDR; $0012)
A serial-parallel conversion register that is used for transfer of
data.
•
SCI Status Register (SSR; $0011)
76543210
Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon completion of transmitting or receiving 8-bit data. It is cleared when
reset or data is written to or read from the SCI data register with
the SCR5 = "1". The bit can also be cleared by writing "0" in
it.
Data Transmission
By writing the desired control bits into the SCI control registers, a transfer rate and a source of transfer clock are determined
and bits 3 and 5 of port D are set at the serial data output terminal and the serial clock terminal, respectively. The transmit data
should be stored from the accumulator or index register into the
SCI data register. The data written in the SCI data register is output from the D,/Tx terminal, starting with the LSB, synchronously with the falling edge of the serial clock. (See Fig. 11.)
When 8 bits of data have been transmitted, the interrupt request
bit is set in bit 7 of the SCI status register. This request can be
masked by setting bit 5 of the SCI status register. Once the data
has been sent, the 8th bit data (MSB) stays at the D'/Tx terminal. If an external clock source has been selected, the transfer
rate determined by bits 0 - 3 of the SCI control register is ignored, and the D/CK terminal is set as input. If the internal
clock has been selected, the DiCK terminal is set as output and
clocks are output at the transfer rate selected by bits 0 - 3 of the
SCI control register.
Bit 6 (SSR6)
Bit 6 is the T1ME~ interrupt request bit. TIME~ is used
commonly with the serial clock generator, and SSR6 is set each
time the internal transfer clock falls. When reset, the bit is
cleared. It also be cleared by writing "0" in it. (For details, see
T1MER2 .)
Bit 5 (SSR5)
Bit 5 is the SCI interrupt mask bit which can be set or cleared
by software. When it is "I", the SCI interrupt (SSR7) is masked.
When reset, it is set to "1".
SSR7
SCI interrupt request
o
Absent
Present
SSR6
TIMER z interrupt request
o
Absent
Present
SSR5
o
SCI interrupt mask
Enabled
Disabled
SSR4
o
TIMER z interrupt mask
Enabled
Disabled
530
Figure 11
•
SCI Timing Chart
Data Reception
By writing the desired control bits into the SCI control register, a transfer rate and a source of transfer clock are determined
and bits 4 and 5 of Port D are set at the serial data input terminal and the serial clock terminal, respectively. Then dummy-writing or -reading the SCI data register, the system is ready for receiving data. (This procedure is not needed for the second and
subsequent data receptions. It must be taken only after resetting.)
The data from the D/Rx terminal is input to the SCI data
register synchronously with the leading edge of the serial clock
(see Fig. 10. When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI status register. This request can be masked by setting bit 5 of the SCI status register. If
an external clock source have been selected, the transfer rate determined by bits 0 - 3 of the SCI control register is ignored and
the data is received synchronously with the clock from the DJ
CK terminal. If the internal clock has been selected, the D:,fcK
terminal is set as output and clocks are output at the transfer rate
selected by bits 0 - 3 of the SCI control register.
•
TIMER2
The SCI transfer clock generator can be used as a timer. The
clock selected by bits 3 - 0 of the SCI control register (4 IJ-s approx. 32 ms (for oscillation at 4 MHz» is input to bit 6 of the
SCI status register and the T1MER2 interrupt request bit is set at
each falling edge of the clock. Since interrupt requests occur periodically, TIMER2 can be used as a reload counter or clock.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - HD6305UO,HD63A05UO,HD63B05UO
®®
L
CG
: Transfer
clock generator is reset and mask bit (bit 4
of SCI status register) is clea red.
Cli.@ : TIMER2
®. ® :TIMER2
interrupt request
interrupt request bit cleared
TIMER., is commonly used with the SCI transfer clock generator. If wanting to use TIMER:! independently of the SCI, specify
"External" (SCR5 = I, SCR4 = J) as the SCI clock source.
If "Internal" is selected as the clock source, reading or writing
the SDR causes the prescaler of the transfer clock generator to
be initialized.
I/O PORTS
There are 31 input/output terminals (ports A, B, C, D). Each
110 terminal can be selected for either input or output by the
data direction register. More specifically, an I/O port will be input
if "0" is written in the data direction register, and output if "I"
is written in the data direction register. Port A, B, C or Dreads
latched data if it has been programmed as output, even with the
output level being fluctuated by the output load. (See Fig. 12.)
When reset, the data direction register goes "0" and all the
input/output terminals are used as input.
All input/output terminals are TTL compatible and CMOS
compatible in respect of both input and output.
If 110 ports are not used, they should be connected to Vss via
resistors. With none connected to these terminals, there is the
possibility of power being consumed despite that they are not
used.
•
RESET
The MCV can be reset either by external reset input (RES) or
power-on reset. (See Fig. 13.) On power up, the reset input must
be held "Low" for at least tose to assure that the internal oscillator is stabilized. A sufficient time of delay can be obtained by
connecting a capacitance to the RES input as shown in Fig. 14.
5V
Vcc
OV
•
RES
Terminal
/~
/"
VIH
---------4"'"
-
tRHL
-
RES
r----
Internal _ _ _ _ _ _ _ _ _ _ _....J
Reset
Figure 13
Power On and Reset Timing
l00kn typ
HD6305UO
MCU
Bit of data
direction
register
Bit of
output
data
1
0
0
0
1
1
1
1
0
X
Figure 12
Status of
output
Input to
CPU
Figure 14
Input Reset Delay Circuit
•
3-state
Pin
Input/Output Port (Ports A, B, C and D) Diagram
INTERNAL OSCILLATOR
The internal oscillator circuit is designed to meet the requirement for minimum external configurations. It can be driven by
connecting a crystal (AT cut 2.0 - 8.0 MHz) or ceramic oscillator between pins 38 and 39 depending on the required oscillation
frequency stability.
Three different terminal connections are shown in Fig. 15.
Figs. 16 and 17 illustrate the specifications and typical arrangement of the crystal, respectively.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
531
HD6305UO,HD63A05UO,HD63B05UO--------------------------------------------• LOW POWER DISSIPATION MODE
The HD6305UO has three low power dissipation modes: wait,
stop and standby.
1---._3_9-t EXTAL
JO-.:.0"H>=38 XTAl
HD6305UO
MCU
•
Wait Mode
When WAIT instruction being executed, the MCU enters into
the wait mode. In this mode, the oscillator stays active but the
internal clock stops. The CPU stops but the peripheral functions
- the· timer and the serial communication interface - stay
active. (NOTE: Once the system has entered the wait mode, the
serial communication interface can no longer be retriggered.) In
the wait mode, the registers (except the I bit of the condition
code register which is cleared), RAM and I/O terminals hold
their condition just before entering into the wait mode.
The e~e from this mode c~e done by interrupt (INT,
TIMERIINT., or SCI/TIMER.,), RES or STBY. The RES resets
the MCU an-d the STBY brings it into the standby mode. (This
will be mentioned later.)
When interrupt is requested to the CPU and accepted, the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt. routine. If an interrupt other
than the INT (i.e., TIMER/INT2 or SCIITIMER2) is masked by
the timer control register, miscellaneous register or serial status
register, there is no interrupt request to the CPU, so the wait
mode cannot be released.
Fig. 18 shows a flowchart for the wait function .
10-22pF±20%
Crystal Oscillator
External
Ceramic Oscillator
Clock
Input39 EXTAL
NC38 XTAL HD6305UO
MCU
•
When STOP instruction being executed, MCU enters into the
stop mode. In this mode, the oscillator stops and the CPU and
peripheral functions become inactive, but the RAM, registers
(except bits 6 and 7 of the timer control register and the I bit of
the condition code register) and I/O terminals hold their condition just before entering the stop mode. Bits 6 and 7 of the timer
control register are initialized to "1" and "0", bits 7, 6, 5 and 4
of SCI status register are initialized "0", "0", "1", "1", respectively, and the I bit of the condition code register is cleared.
The escape from this mode can be done by an external interrupt (INT or INT2 ), RES or STBY. The RES resets the MCU
and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted, the
stop mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the INT2 interrupt
is masked by the miscellaneous register, there is no interrupt request to the MCU, so the stop mode cannot be released.
Fig. 19 shows a flowchart for the stop function. Fig. 20 shows
a timing chart of return to the operation mode from the stop
mode.
For releasing from the stop mode by an interrupt, oscillation
starts upon input of the interrupt and, after the internal delay
time for stabilized oscillation, the CPU becomes active. For restarting by RES, oscillation starts when the RES goes "0" and
the CPU restarts when the RES goes" 1". The duration of RES
= "0" must exceed tose to assure stabilized oscillation.
External Clock Drive
Figure 15
Internal Oscillator Circuit
C,
AT Cut
Parallel
Resonance
Co=7pF max.
EXTAL
f=2.0-8.0MHz
39
Rs=600 max.
C~
s
XTAL
38
Co
Figure 16
Parameters of Crystal
•
l NOTE I
Use as short wirings as possible for connection of the crystal
with the EXT AL and XTAL terminals. Do not allow these
wirings to cross others.
Figure 17
532
Typical Crystal Arrangement
Stop Mode
Standby Mode
The MCU enters into the standby mode when the STBY terminal goes "Low". In this mode, all operations stop and the internal condition is reset but the contents of the RAM are hold.
The I/O terminals turn to high-impedance state. The standby
mode should escape by bringing STBY "High". The CPU must
be restarted by reset. The timing of input signals at the RES and
STBY terminals is shown in Fig. 21.
Table 4 lists the status of each parts of the MCU in each low
power dissipation modes. Transitions between each mode are
shown in Fig. 22.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------HD6305UO,HD63A05UO,HD63B05UO
Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop
Clear I bit
Initialize
CPU, TIMER, SCI,
1/0 and All
Other Functions
No
No
Restart
Processor Clocks
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 18
Wait Mode Flowchart
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
533
HD6305UO,HD63A05UO,HD63B05UO--------------------------------------------
Stop Oscillator
and All Clocks
Clear I bit
TCR7 +- 0
TCR6 +- 1
SSR7 +- 0
SSR6 +- 0
SSR5 +- 1
SSR4 +- 1
No
Turn on Oscillator
Wait for Time Delay
to Stabilize
Turn on Oscillator
Wait for Time Delay
to Stabilize
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 19 Stop Mode Flowchart
534
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------HD6305UO,HD63A05UO,HD63B05UO
1111111111111111111111111111
Oscillator
4111111111111111111111111111111111111111111111111111111111
(
~Il---+----I
E
I
stabilized (built-in delay time)
Interrupt
STOP instruction
executed
restart
(a) Restart by Interrupt
11111111111111111111111111111
Oscillator
E
~l---+--~
Time required for oscillation to become
STOP instruction
executed
stabilized (tose!
Reset
start
RES
(b) Restart by Reset
Figure 20
Timing Chart of Releasing from Stop Mode
-~I
\'-----JlJr-RES
i
I
I
I
I
,
I
I
~-~--~--~~--------\~---------+--------~
tosc
Figure 21
Table 4
Restart
Timing Chart of Releasing from Standby Mode
Status of Each Part of MCU in Low Power Dissipation Modes
Condition
Mode
Start
WAIT
Software
STOP
Standby
Hardware
CPU
Timer,
Serial
WAIT instruction
Active
Stop
Active
Keep
Keep
Keep
STOP instruction
Stop
Stop
Stop
Keep
Keep
Keep
STBY="Low"
Stop
Stop
Stop
Reset
Keep
High impedance
• Register in the CPU (except I bit
In
Register*
RAM
Escape
1/0
Oscillator
terminal
STBY, RES, INT, INT 2 ,
each interrupt request of
TIMER, TIMER 2 , SCI
---
-- ----
STBY, RES, INT, INT2
STBY="High"
-<
the CCR)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
535
HD6305UO,HD63A05UO,HD63B05UO-------------------------------------------See Fig. 25. In the direct addressing mode, the address of the
operand is contained in the 2nd byte of the instruction. The user
can gain direct access to memory up to the lower 255th address.
All RAM and I/O registers are on page 0 of address space so that
the direct addressing mode may be utilized.
•
Extended
See Fig. 26. the extended addressing is used for referencing to
all addresses of memory. The EA is the contents of the 2 bytes
that follow the operation code. An extended addressing instruction requires a length of 3 bytes.
•
Relative
See Fig. 27. The relative addressing mode is used with branch
instructions only. When a branch occurs, the program counter is
loaded with the contents of the byte following the operation code.
EA = (PC) + 2 + ReI., where ReI. indicates a signed 8-bit data
following the operation code. If no branch occurs, ReI. = O.
When a branch occurs, the program jumps to any byte in the
range + 129 to -127. A branch instruction requires a length of 2
bytes.
•
Indexed (No Offset)
See Fig. 28. The indexed addressing mode allows access up to
the lower 255th address of memory. In this mode, an instruction
requires a length of one byte. The EA is the contents of the index register.
Figure 22 Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset
•
•
BIT MANIPULATION
The HD630SVO MCV can use a single instruction (BSET or
BCLR) to set or clear one bit of the RAM or an I/O port. Every
bit of memory or I/O within page 0 ($00 - $FF) can be tested
by the BRSET or BRCLR instruction; depending on the result of
the test, the program can branch .to required destinations. Since
bits in the RAM, or I/O can be manipulated, the user may use a
bit within the RAM as a flag or handle a single I/O bit as an independent 1/0 terminal. Fig. 23 shows an example of bit
manipulation and the validity of test instructions. In the example,
the program is configured assuming that bit 0 of port A is connected to a zero cross detector circuit and bit I of the same port
to the trigger of a triac.
The program shown can activate the triac within a time of
lOllS from zero-crossing through the use of only 7 bytes on the
ROM. The on-chip timer provides a required time of delay and
pulse width modulation of power is also possible.
•
Figure 23
BRCLR 0, PORT A, SELF 1
BSET 1, PORT A
BCLR 1, PORT A
Exa~lple of Bit Manipulation
•
ADDRESSING MODES
Ten different addressing
HD630SVO MCV.
•
modes
are
available
to
the
•
Bit Set/Clear
See Fig. 31. This addressing mode is applied to the BSET and
BCLR instructions that can set or clear any bit on page O. The
lower 3 bits of the operation code specify the bit to be set or
cleared. The byte that follows the operation code indicates an address within page O.
Bit Test and Branch
See Fig. 32. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0 and
can be branched in the relative addressing mode. The byte to be
tested is addressed depending on the contents of the byte following the operation code. Individual bits within the byte to be
tested are specified by the lower 3 bits of the operation code. The
3rd byte represents a relative value which will be added to the
program counter when a branch condition is established. Each of
these instructions should be 3 bytes long. The result of the test is
written in the carry bit of the condition code register. (Set if true,
cleared otherwise,)
Immediate
See Fig. 24. The immediate addressing mode provides access
to a constant which does not vary during execution of the program.
This access requires an instruction length of 2 bytes. The effective address (EA) is PC and the operand is fetched from the
byte that follows the operation code.
•
Indexed (16-bit Offset)
See Fig. 30. The contents of the 2 bytes following the operation code are added to content of the index register to compute
the value of EA. In this mode, the complete memory can be accessed. When used in the indexed addressing mode 06-bit offset), an instruction must be 3 bytes long.
•
SE L F 1.
Indexed (S-bit Offset)
See Fig. 29. The EA is the contents of the byte following the
operation code, plus the contents of the index register. This
mode allows access up to the lower 51lth address of memory.
Each instruction when used in the index addressing mode (8-bit
offset) requires a length of 2 bytes.
Direct
536
•
Implied
See Fig. 33. This mode involves no EA. All information
needed for execution of an instruction is contained in the operation code. Direct manipulation on the accumulator and index register is included in the implied addressing mode. Other instructions such as SWI and RTI are also used in this mode. All instructions used in the implied addressing mode should have a
length of one byte.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------HD6305UO,HD63A05UO,HD63B05UO
I
A
::
~
I
Memory
~_-----cA~
r-FB
Index Reg
I
Stack Point
PROG LOA :: $FB
05BEt-:~~::::jf_--------.J
Prog Count
05BF'"
OS CO
CC
~
I
I
Figure 24
Example of Immediate Addressing
Memory
A
CATFCB32004B~~L:::r_--1_---~~------~~2g0~J
Index
eg
I
Stack t:Po~in::-t- _....
PROG LOA CAT 0520
052E
1=j]t:=1~--J
Prog lount
OS2F
CC
§
:
:
:
:
Figure 25
Example of Direct Addressing
Memory
0000
A
40
Index Reg
PROG LOA CAT 0409..-......;;~--IL
~:~~t---':'-::----f
I
Stack Point
CATFCB6406E5~:J@:::l_-------J
Prog Count
040C
CC
Figure 26
Example of Extended Addressing
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
537
HD6305UO,HD63A05UO,HD63B05UO-------------------------------------------Memory
A
Index Reg
I
Stack Point
PROG BEQ PROG2 04A7
04AB I-~=-----t
~
;
:
Figure 27
Example of Relative Addressing
Memory
A
TABLFCC LI
00BBt:~~::i---~~~------1-----------~~4fC~:J
BB
Stack POint
Prog Count
05F5
CC
Figure 28
Example of Indexed (No Offset) Addressing
Memory
00B9
OOBA
(JOSB
OOSC
BF
B6
DB
CF
PROG LOA TABL X 075B
075C
E6
TABL FCB
FCB
FCB
FCB
.BF
$B6
IWB
!!,CF
A
CF
Index Reg
03
Stack POIOt
89
I
Prog Count
0750
cc
I
~
Figure 29 Example of Indexed (8·bit Offset) Addressing
538
$HITACtil
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------HD6305UO,HD63A05UO,HD63B05UO
Memory
PROG lOA TABl X 0692
0693
0694
~
A
DB
Index Reg
02
Stack POIOt
I
Prog Count
0695
CC
TABl FCB
FCB
FCB
FCB
IIBF
1186
IIDB
IICF
I
BF
86
08
CF
077E
077F
0780
0781
Figure 30 Example of Indexed (16-bit Offset) Addressing
PORT 8 EQU 1 00011---";:::""_-fI
A
Index Reg
I
PROG 8elR 6. PORT B 05BF
t::J2t=l------.J
0590
Prog Count
0591
CC
~
,I
Stack POint
,•
Figure 31
Example of Bit Set/Clear Addressing
PORT C EQU 2 0002 )-""";";:""'--1
PROG BRClR 2,PORT C PROG 2 0574
05 7 51---"';'~--I
0576
I--......;.:;...-~I
In this example bit C of the CC
becomes "0",
Figure 32
Example of Bit Test and Branch Addressing
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
539
HD6305UO,HD63A05UO,HD63B05UO--------------------------------------------
Memory
~
'"00'" """
~A
~
~
I
I
I
I
I
I
I
,
Figure 33
Example of Implied Addressing
• INSTRUCTION SET
There are 62 basic instructions available to the HD6305VO
MCV. They can be classified into five categories: register/memory, read/modify/write, branch, bit manipulation, and control. The
details of each instruction are described in Tables 5 through 11.
•
Register/Memory Instructions
Most of these instructions use two operands. One operand is
either an accumulator or index register. The other is derived
from memory using one of the addressing modes used on the
HD6305VO MeV. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump instruction (JSR). See Table 5.
•
Read/Modify/Write Instructions
These instructions read a memory or register, then modify or
test its contents, and write the modifieq value into the memory
or register. Zero test instruction (TST) does not write data, and
is handled as an exception in the read/modify/write group. See
Table 6.
540
•
Branch Instructions
A branch instruction branches from the program sequence in
progress if a particular condition is established. See Table 7.
•
Bit Manipulation Instructions
These instructions can be used with any bit located up to the
lower 255th address of memory. Two groups are available; one
for setting or clearing and the other for bit testing and branching.
See Table 8.
•
Control Instructions
The control instructions control the operation of the MeV
which is executing a program. See Table 9.
• List of Instructions in Alphabetical Order
Table 10 lists all the instructions used on the HD6305VO
MeV in the alphabetical order.
•
Operation Code Map
Table II shows the operation code map for the instructions
used on the MCV.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H D6305UO, H D63A05UO, H D63B05UO
Table 5
Register/Memory Instructions
Addressing Modes
Indexed
Operations
Mnemonic
Immediate
Extended
Direct
OP II
-
OP II
- OP
Load A from Memory
LOA
A6
2
2
B6
2
3 C6 3
2
II
Indexed
- OP
II
-
OP II
-
OP II
-
F6
1
3
E6
2
4 06 3
5
3
EE
2
4 DE 3
5
M-X
4
E7
2
4 07 3
5
A-M
OF
4
H
2
3 CE 3
4
FE
1
2
3 C7
3
4
F7
1
BF
2
3
CF
3
4
FF
1
4
EF
2
4
3
5
X-M
2
BB
2
3 CB 3
4
FB
1
3
EB
2
4 DB 3
5
A+M-·A
2
2
B9
2
3 C9 3
4
F9
1
3 E9
2
4 09 3
5
A+M+C~A
AO 2
2
BO 2
3 CO 3
4
FO
1
3 EO 2
4 DO 3
5
A-M~A
2
2
B2
2
3 C2
3
4
F2
1
3 E2
2
4
02 3
5
A-M-C~A
AND
A4 2
2
B4
2
3 C4 3
4
F4
1
3 E4
2
4
04 3
5
A·
ORA
AA 2
2 BA 2
3 CA 3
4
FA
1
3 EA 2
4 DA 3
5
A+M~A
EOR
A8 2
2
B8
2
3 C8 3
4
FS
1
3
E8
2
4 08 3
5
CMP
A1
2
2
Bl
2
3 C1
3
4
Fl
1
3 El
2
4 01
3
CPX
A3
2
2
B3
2
3 C3 3
4
F3
1
3 E3
2
4 03 3
2
4
AE
2
STA
Store X in Memory
STX
-
- - -
Add Memory to A
ADD
AB 2
to A
ADC
A9
Subtract Memory
SUB
A with Borrow
SBC
A2
AND Memory to A
OR Memory with A
Add Memory and Carry
"-
"-
1\
1\
•
A+M~A
• •
"
1\
•
5
A-M
• •
" "
5
X-M
• •
A·M
• •
• •
•
··"" ·
Bit Test Memory with
A (Logical Compare)
BIT
A5
2
B5
2
3 C5
F5
1
3 E5
2
4 05 3
5
Jump Unconditional
JMP
BC
2
2 CC 3
3 FC
1
2 EC
2
3 DC 3
4
Jump to Subroutine
JSR
- - - - -
BD 2
5 CD 3
6 FD
1
5 ED 2
5 DO 3
6
1\
1\
"
1\
.. ."• ·•
· ·
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
Table 6
"
""
M~A
Arithmetic Compare X
3
" ••
"
"" ••
1\
·
Arithmetic Compare A
with Memory
C
• •
• •
Exclusive OR Memory
with Memory
Z
"• • " " ""
"
Subtract Memory from
with A
N
·
·
BE
LOX
I
• • "
•
• • /\"
• /\
1\ •
"
M-A
B7
Load X from Memory
Store A in Memory
Condition
Code
Boolean/
Arithmetic
Operation
Indexed
(No Offset) (S·Bit Offset) (16·8itOffset)
1\
Read/Modify/Write Instructions
Addressing Modes
Indexed
Operations
Mnemonic
Implled(A)
OP II
-
OP II
Increment
INC
4C
1
2
5C
1
-
2 3C
OP II
2
Indexed
(No Offset) (8· Bit Offset)
Direct
Implled(X)
-
OP II
5 7C
1
-
OP II
5 6C
Condition
Code
Boolean/Arithmetic Operation
-
2
6
A+1
~A
or X+1
~X
or M+1
~M
~A
or X-1
~X
or M-1
~M
H
I
•
•
•
•
• "- " •
• " II •
• 0 1 •
• 1\ 1\ 1
N
Z
Decrement
DEC
4A
1
2 5A
1
2 3A 2
5
7A
1
5 6A 2
6
A-I
Clear
CLR
4F
1
2
5F
1
2
3F
2
5
7F
1
5
6F
2
6
OO-A or OO-X or OO-M
Complement
COM
43
1
2
53
1
2 33
2
5
73
1
5 63
2
6
A~A or'X~X or M~M
(2's Complement)
NEG
40
1
2
50
1
2
30
2
5
70
1
5 60 2
6
or OO-M ··M
ROL
49
1
2
59
1
2
39
2
5
79
1
5 69
2
6
bo~
L5t I I I I I I I
•
• •
1\
Rotate Left Thru Carry
Rotate Right Thru Carry
ROR
46
1
2
56
1
2 36
2
5
76
1
5 66
2
6
L0=t I I·H ..:MI Ibo~
• •
1\ "-
OO-A-A or
Negate
Logical Shift Left
LSL
48
1
2
58
1
2 38
2
5
78
1
5 68
2
6
Logical Shift Right
LSR
44
1
2
54
1
2
34
2
5
74
1
5 64
2
6
OO-X~X
AOf_cwlll
C
c
b,
·
0
---
:II·H":MII
bo
C
bo
C
~
Arithmetic Shift Right
ASR
47
1
2
57
1
2
37
2
5
77
1
5 67
2
6
Arithmetic Shift Left
ASL
48
1
2
58
1
2
38
2
5
78
1
5 68
2
6
Equal to LSL
TST
40 1
2 50
1
2 3D 2
4
70
1
4 60 2
5
A-OO or X-OO or M-OO
• •
• •
1\
0
1\
• •
"
"
1\
0\
1\
0\ 1\
"-
""
1\
"-
Test for Negative
or Zero
" ""-
1\
bo
D-I I ~,,:xr~ I I 1-- • •
b,
0-1 I I·H ..:MI I 1-0 • •
[?b'
1\
C
•
Symbols: Op = OperatIon
# = Number of bytes
= Number of cycles
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
541
HD6305UO,HD63A05UO,H D63B05UO - - - - - - - - - - - - - - - - - - - - - Table 7 Branch Instructions
Addressing Modes
Operations
Mnemonic
Relative
OP
~
-
Branch Always
BRA
20
2
3
None
Branch Never
BRN
21
2
3
None
Branch IF Higher
BHI
22
2
3
C+Z=O
Branch IF lower or· Same
BlS
23
2
3
C+Z=1
Branch IF Carry Clear
BCC
24
2
3
C=O
(BHS)
24
2
3
C=O
BCS
25
2
3
C=1
(Branch IF Higher or Same)
Branch IF Carry Set
(Branch IF lower)
Branch IF Not Equal
(BlO)
25
2
3
C=1
BNE
26
2
3
z=o
BEQ
27
2
3
Z=1
Branch IF Half Carry Clear
BHCC
28
2
3
H=O
Branch IF Half Carry Set
BHCS
29
2
3
H=1
Branch IF Plus
BPl
2A
2
3
N=O
Branch IF Minus
BMI
2B
2
3
N=1
BMC
2C
2
3
1=0
BMS
20
2
3
1=1
Bil
2E
2
3
INT=O
Branch IF Equal
Condition Code
Branch Test
Branch IF Interrupt Line
is low
BIH
2F
2
3
INT=1
Branch to Subroutine
BSR
AD
2
5
--
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • •
• • •
• • •
• • •
• • • •
• • • •
•
•
•
Branch IF Interrupt Line
is High
N
•
•
•
•
•
•
•
•
•
Branch IF Interrupt Mask
Bit is Set
I
•
•
Branch IF Interrupt Mask
Bit is Clear
H
= Operation
= Number of bytes
- = Number of cycles
Symbols: Op
#
Table 8 Bit Manipulation Instructions
Operations
Addressing Modes
Booleanl
Bit Set/Clear
Bit Test and Branch Arithmetic
Operation
OP
#
OP
::
BRSET n(n =0· .. 7)
2·n
3 5
BRCLR n(n=O··· 7)
- - 01 +2·n 3 5
BSET n(n=0···7)
10+2·n 2 5
- - 1-+Mn
BCLR n(n ::;::0···7)
11 +2·n 2 5
- - O-+Mn
Mnemonic
Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear Bit n
-
-
-
Symbols: Op· Operation
# • Number of bytes
- • Number of cycles
542
-
Branch
Test
Condition Code
H
Mn=1
Mn=O
-
-
I
• •
• •
• •
• •
N
Z
• •
• •
C
1\
1\
• • •
• • •
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6305UO,HD63A05UO,HD63B05UO
Table 9
Control Instructions
Addressing Modes
Mnemonic
Operations
Transfer A to X
TAX
97
#
1
Transfer X to A
TXA
9F
1
2
2
H
X--+A
Set Carry Bit
SEC
99
1
1
1--+C
CLC
98
1
1
O--+C
Set Interrupt Mask Bit
SEI
9B
1
2
1--+1
Clear Interrupt Mask Bit
CLI
9A
1
2
0--+1
Software Interrupt
SWI
83
1
10
Return from Subroutine
RTS
81
1
5
Return from Interrupt
RTI
80
1
8
Reset Stack Pointer
RSP
9C
1
2
1
2
4
4
No-Operation
NOP
90
1
DAA
80
1
Stop
STOP
8E
1
Wait
WAIT
8F
1
Symbols: Op= Operation
# = Number of bytes
- = Number of cycles
I
Z
C
•
•
•
•
•
•
•
• • • •
? ? ?
• • • •
• • • •
• • 1\
• 00 • •
• • •
•
•1
?
$FF--+SP
Advance Prog. Cntr. Only
Converts binary add of BCD charcters Into
1\
BCD format
Indexed
Mnemonic
Extended Relative (No Offset)
Immediate
Direct
ADC
X
x
X
ADD
x
x
X
x
x
ASl
X
x
x
ASR
x
X
x
x
X
x
x
Indexed
Set!
Test &
(8-Bit)
(16-Bit)
Clear
Branch
H
I
N
Z
X
X
1\
1\
1\
1\
x
x
x
x
x
x
"-
•
"-
1\
1\
1\
1\
•
1\
1\
1\
1\
1\
1\
x
BClR
x
x
x
x
x
x
x
x
BCS
BEQ
BHCC
BHCS
BHI
(BHS)
BIH
Bil
x
X
x
x
x
x
x
(BlO)
BlS
BMC
BMI
X
BMS
x
x
x
x
BNE
BPL
BRA
Bit
Indexed
x
BCC
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
•
•
•
1\*
Condition Code
Bit
BIT
?
•
Instruction Set (in Alphabetical Order)
Addressing Modes
AND
0
•
•
•
•
• Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.>
Table 10
Implied
N
• • •
• • •
• • •
• •1 •
•
•
• 01 •
• •
A--+X
Clear Carry Bit
Decimal Adjust A
Condition Code
Boolean Operation
Implied
OP
X
x
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
C
• • •
• • •
•
•
•
•
•
•
•
•
"•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
"•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(to be continued)
C
1\
•
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
load CC Register From Stack
~HITAOHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
543
H D6305UO,HD63A05UO,H D63B05UO - - - - - - - - - - - - - - - - - - - - - Table 10
Instruction Set (in Alphabetical Order)
Addressing Modes
Condition Code
Bit
Mnemonic
Implied
Immediate
Direct
Extended Relative
Indexed
Indexed
Indexed
Set!
Test &
(No Offset)
(8-Bit)
(16-Bit)
Clear
Branch
x
BRN
x
x
BRCLR
BRSH
x
BSET
x
BSR
CLC
CLI
CLR
x
x
x
x
x
CPX
DAA
DEC
x
x
x
x
x
x
x
x
x
x
x
x
x
EOR
INC
x
x
x
x
x
CMP
COM
x
JMP
JSR
x
x
LOA
LDX
LSL
LSR
NEG
NOP
x
x
x
x
x
ORA
ROL
ROR
RSP
RTI
RTS
SEI
x
x
x
x
x
x
x
x
x
SBC
SEC
x
SUB
TAX
TST
TXA
WAIT
x
x
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
544
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
STX
SWI
x
x
x
x
x
x
x
STA
STOP
Bit
x
C
f\
•
N
Z
• • •
• • •
• • •
• • •
• • •
• •0 •
• •
• • 0
• • "
• • 1\
• • 1\
• • 1\
• • 1\
• • 1\
• • 1\
• • •
• • •
• • 1\
• • "
• • 1\0
• •
• • 1\
• • •
•
•
•
•
•
•
•1
H
•
•
•
•?
•
•
•
•
•
•
•
•
•
•
•
•
•
I
•
•
•
•?
•
•
•1
•
0
•
•1
•
•
•
0
/'I
1\
C
•
1\
"•
•0
•
•
1\
1\
1
1\
1\
1\
1\
•
•
/'I •
• •
• •
1\ •
1\
/'I
1\
•
1\
1\
1\
1\
1\
1\
• •
/'I •
1\
/'I
" ""
1\
•? •? •?
• • •
/'I
• "• 1
• • •
"• "• ••
1\
1\
•
• • •
• • •
1\ 1\ •
• • •
• • •
1\
Carry Borrow
Test and Set if True. Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
Hitaohi. America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
"
1\
1\
- - - - - - - - - - - - - - - - - - - - - - HD6305UO,HD63A05UO,HD63B05UO
Table 11
Bit Manipulation
Branch
Operation Code Map
Control
Read/Modify IWrite
Test &
Set/
Branch
Clear
Rei
DIR
A
X
,X1
,XO
IMP
0
1
2
3
4
5
6
7
8
9
0
BRSETO
BSETO
BRA
NEG
RTI'
-
1
BRCLRO
BCLRO
BRN
-
RTS'
2
BRSET1
BSET1
BHI
-
-
3
BRCLR1
BCLR1
BLS
COM
SWI'
4
BRSET2
BSET2
BCC
LSR
5
BRCLR2
BCLR2
BCS
-
-
IMP IMM
BNE
ROR
-
ASR
-
TAX'
8
9
BRSET4
BSET4
BHCC
LSLASL
BRCLR4
BCLR4
BHCS
ROL
-
A
BRSET5
BSET5
BPL
DEC
-
B
BRCLR5
BCLR5
BMI
-
C
BRSET6
BSET6
BMC
INC
-
D
BRCLR6
BCLR6
BMS
E
BRSET7
BSET7
BIL
-
F
BRCLR7
BCLR7
BIH
CLR
3/5
2/5
2/3
(NOTES)
1
SBC
2
6
STA(+ll 7
CLC
EOR
SEC
ADC
8
9
Cll*
ORA
A
SEI*
ADD
RSP'
-
DAA' NOP BSR'
1/'
CMP
LDA
-
JSR(+2)
1/1
2/2
2/3
JSR(+ 1)
JSR(+21 D
E
STX
STX(+lI F
3/5
W
C
LDX
3/4
L
o
B
JMP(-1)
-
HIGH
0
STA
WAIT' TXA'
1/5
+-
5
BEQ
2/6
F
SUB
BIT
BSET3
1/2
,XO
E
3
BCLR3
1/2
,X1
D
4
BRSET3
2/5
,X2
C
CPX
BRCLR3
STOP'
EXT
B
AND
6
TST(-1)
DIR
-
7
TST
A
-
TST(-lI
Register /Memory
2/4
1/3
1. "-" is an undefined operation code.
2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).
The number of cycles for the mnemonics asterisked (0) is as follows:
RTI
8
TAX
2
RTS
5
RSP
2
SWI
10
TXA
2
DAA
2
BSR
5
STOP
4
ell
2
WAIT
4
SEI
2
3. The parenthesized numbers must be added to the cycle count of the particular instruction.
•
Additional Instructions
The following new instructions are used on the HD6305VO:
DAA Converts the contents of the accumulator into BCD code.
WAIT Causes the MCV to enter the wait mode. For this mode,
see the topic, Wait Mode.
STOP Causes the MCV to enter the stop mode. For this mode,
see the topic, Stop Mode.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
545
HD6305VO,HD63A05VO, - - HD63B05VO
CMOS MCU(Microcomputer Unit)
-PRELIMINARYThe HD6305VO is a CMOS 8-bit single-chip MCU which is
similar to the HD6305X MCU family. This version is upward
compatible with the HD6805 family in respect to instructions. A
CPU, a clock generator, a 4k-byte ROM, a 192-byte RAM, 31 II
o terminals, two timers, and a serial communication interface
(SCI) are incorporated in the HD6305VO. As a result of CMOS
technology, the HD6305VO consumes much less power than
NMOS counterparts. In addition, three low power dissipation
modes (stop, wait and standby) which further decreases power
consumption, are included in the HD6305VO.
Other notable features include enhanced instruction cycle of
the main instructions and the use of three additional instructions
to improve system throughput.
•
•
•
•
•
•
•
•
•
•
•
•
HARDWARE FEATURES
CMOS a-bit single-chip MCU
4096 bytes of ROM
192 bytes of RAM
31 bidirectional I/O terminals
Two timers
8-bit timer with a 7-bit prescaler (programmable prescaler; event counter)
1 5-bit timer (commonly used with the SCI clock divider)
On-chip serial interface circuit (synchronized with clock)
Six interrupts (two external. two timer. one serial and one
software)
Low power dissipation modes
- Wait ....... In this mode. the clock oscillator is on and
the CPU halts but the timer/serial/interrupt
function is operatable. Also. all registers are
held. except the I bit in the condition code
register is cleared.
- Stop ....... In this mode. the clock stops but the RAM
data. I/O status and registers are held. Except the timer control register (bits 6 and 7)
and the I bit of the condition code register.
- Standby .... In this mode. the clock stops. the RAM data
is held. and the other internal condition is reset.
Minimum instruction cycle time
HD6305VO ....... 1 JLs (f = 1 MHz)
- HD63A05VO ..... 0.67 JLs (f = 1.5 MHz)
- HD63B05VO ...... 0.5 JLs (f = 2 MHz)
Wide operating range
Vee = 3 to 6V (f = 0.1 to 0.5 MHz)
HD6305VO ....... f = 0.1 to 1 MHz
(Vee = 5V ± 10%)
HD63A05 VO
.. f = 0.1 to 1.5 MHz
(Vee = 5V ± 10%)
HD63B05VO. .
. f = 0.1 to 2 MHz
(Vee = 5V ± 10%)
System development fully supported by an emulator
HD6305VOP. HD63A05VOP.
HD63B05VOP
(DP-40)
•
PIN ARRANGEMENT
Vcc
EXTAL
XTAL
7 TIMER
S'i'iiY
D./T'ATi
D./CK
33 D./Rx
D3ITx
02
0,
Do
(Top View)
• SOFTWARE FEATURES
• Similar to HD6800
• Byte efficient instruction set
• Powerful bit manipulation instructions (Bit Set. Bit Clear. and
Bit Test and Branch usable for all RAM bits and all I/O terminals)
546
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300 ,
HD6305VO,HD63A05VO,HD63B05VO
•
•
•
•
•
•
A variety of interrupt operations
Index addressing mode useful for table processing
A variety of conditional branch instructions
Ten powerful addressing modes
All addressing modes adaptable to RAM, and I/O instructions
•
•
•
Three new instructions, Stop, Wait and DAA, added to the
HD6805 family instruction set
Instructions that are upward compatible with those of Motorola's MC6805P2 and MC146805G2
Compatible instruction set with HD6305X
BLOCK DIAGRAM
XTAL EXTAL RES NUM
INT
STBY
TIMER
CPU
Control
Port A
I/O
Terminals
D.IINT 2
D5/CK
D./Rx
D3/Tx
O2
D.
CPU
Port 0
I/O
Terminals
Do
ALU
Port B
I/O
Terminals
Serial
Status
Register
Serial
Data
Register
Port C
I/O
Terminals
• ABSOLUTE MAXIMUM RATINGS
Item
Supply voltage
I nput voltage
Symbol
Value
Unit
VCC
-0.3 - +7.0
V
V
Vin
-0.3 - Vcc + 0.3
Operating temperature
Topr
0-+70
°c
Storage temperature
T stg
-55 - +150
°c
[NOTE)
These products have a protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding,
be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normal
operation, we recommended Vin, V out ; Vss ~ (V in or V out ) ~ Vee.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
547
HD6305VO,HD63A05VO,HD63B05VO - - - - - - - - - - - - - - - - - - - - - • ELECTRICAL CHARACTERISTICS
.DC Characteristics (Vee
=5.0V ± 10%, Vss =GND and T. = 0 -
Item
Input
voltage
"High"
+70°C unless otherwise specified)
Test
condition
Symbol
Current *
dissipation
Input
leakage
current
Threestate
current
Input
capacity
typ
max
Unit
Vee- 0.5
-
Vee+ 0.3
V
VIH
Vee x 0.7
-
Vee+ 0.3
V
2.0
-
Vee+ 0.3
V
VIL
-0.3
-
0.8
V
Operating
-
5
10
mA
Wait
-
2
5
mA
Stop
-
2
10
p,A
Standby
-
2
10
p,A
-
-
1
fJ,A
-
-
1
p,A
-
-
12
pF
FIES. S'fBY
EXTAL
Others
Input voltage "Low"
min
All Inputs
f = 1MHz**
Icc
TIMER.
INT.
IIILI
mv
V in
Ao - A 7 ,
Bo - B 7 ,
Co -C 7 •
ilTSl1
All
terminals
Cin
=0.5-
Vee - O.5V
Do -0,
=
f lMHz.
Vin = OV
*V1Hmin; Vcc-1.ov. VIL max; 0.8 V
nThe value at f = xMHz can be calculated by the following equation: IcC If
• AC Characteristics (Vee = 5.0V
Item
Symbol
± 10%. Vss
Test
condition
=GND and T. = 0 -
=
xMHz) ; Icc (f
typ
1MHz) multiplied by x
+70°C unless otherwise specified)
HD6305VO
min
R
HD63A05VO
max
min
typ
HD63B05VO
min
typ
0.4
-
8
MHz
Clock
frequency
fel
0.4
-
4
0.4
-
6
Cycle time
teyc
1.0
-
10
0.666
10
+ 00
te~e
-
0.5
-
10
fJ,S
-
-
-
ns
-
-
teye
+200
-
-
ns
5
-
-
5
-
-
teye
-
teye.
+200
-
-
teye
+200
-
-
ns
-
20
-
-
20
-
-
20
ms
-
-
80
-
-
80
-
-
ms
tlWL
+2 0
te~c
-
-
INT2 pulse
width
tlWL2
teye
+250
-
-
+ 00
te~e
RES pulse
width
tRWL
5
-
-
TIMER pulse
width
tTWL
!eye
+250
-
Oscillation
start time
(crystal)
tose
-
Reset delay
time
tRHL
80
548
Rs
=22pF ±
20%
= 60n
max
teye
+200
INT pulse
width
CL
Unit
max
max
External cap.
2.2p,F
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435~8300
H D6305VO, HD63A05VO, H D63B05VO
• Port Electrical Characteristics (Vee = 5.0V ± 10%, VSS = GND and Ta = 0 - +70°C unless otherwise specified)
Item
min
typ
max
Unit
2.4
-
-
V
Vee - 0.7
-
-
V
-
-
VIH
2.0
-
Vee + 0.3
V
Vil
- 0.3
-
0.8
V
-
-
1
J.lA
=-200J.lA
IOH =-10J.lA
IOH
Output volt·
age "High"
VOH
Ports A,
B,C,D
Output voltage "Low"
Val
Input voltage "High"
Input voltage "Low"
Ports A,
B,C,D
Input leakage current
•
Test
condition
Symbol
IOl
Vin
III LI
= 1.6mA
=0.5Vee - O.5V
0.55
V
SCI Timing (Vee = 5.0V±10"k, Vss = GND and Ta = 0 - +70°C unless otherwise specified)
Item
Symbol
Clock Cycle
tScyc
Data Output Delay Time
tTXD
Data Set-up Time
tSRX
Data Hold Time
tHRX
Test
Condition
Fig. 1
Fig.2
HD6305VO
HD63A05VO
typ
min
max
min
typ
1
32768 0.67
200
-
100
-
-
max
HD63B05VO
typ
min
max
Unit
-
21845
0.5
-
16384
J.ls
250
-
-
250
ns
200
-
-
-
ns
-
-
200
100
100
-
-
ns
250
-
-
Vcc
Clock Output
TTL load
(Port)
Test point
terminal
Ds/CK
Data Output
10L=
1.6mA
2.4kQ
o---~'---""'-----i'It--.
O,lTx
40pF
12kQ
Data Input
D./Ax
Figure 1 SCI Timing (Internal Clock)
[NOTES 1 1. The load capacitance includes stray capacitance caused
by the probe, etc.
2. All diodes are 152074 ® .
Clock Input
Cs/CK
o 8V
lr::-~-+-i-----....... r---~'I-----
!'-'-;,,;,...-+-i-----...J
•
tSRX
Data Input
2.0V
D./Rx
o 8V
Figure 3 Test Load
'----~l____
DESCRIPTION OF TERMINAL FUNCTIONS
The input and output signals of the HD6305VO are described
here.
•
Figure 2 SCI Timing (External Clock)
V cc , Vss
Voltage is applied to the HD6305VO through these two terminals. Vee is S.OV ± 10%, while Vss is grounded .
•
INT,INT 2
External interrupt request inputs to the H D6305VO. For details, refer to "INTERRUPTS". The 'iN'[" terminal is also used
as the port D6 terminal.
.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
549
HD6305VO,H D63A05VO,H D63B05VO - - - - - - - - - - - - - - - - - - - - - •
XT AL, EXT AL
These terminals provide input to the on-chip clock circuit. A
crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic filter is
connected to the terminal. Refer to "INTERNAL OSCILLATOR" for using these input terminals.
• TIMER
This is an input terminal for event counter. Refer to
"TIMER" for details.
•
o
63
64
RAM
(192Bytes)
Stack
255
256
-
A 7 , Bo -
B7 , Co - C 7 ' Do
0 6)
These 31 terminals consist of three 8-bit 110 ports (A, Band
C) and a 7-bit I/O port D. Each of these can be used as an input
or output terminal on a bit basis through program control of the
data direction register (DDR). For details, refer to "110
PORTS."
Since port D6 is also used for the INTz input, in order to use
port D6 as an 110 port, the INTz interrupt mask bit in the
miscellaneous register should be set to "1" to disable the INTz
input.
• STBY
This terminal is used to place the MCU into the standby
mode. With STBY at "Low" level, the oscillation stops and the
internal condition is reset. For details, refer to "STANDBY
MODE."
The terminals described in the following are 110 pins for serial
communication interface (SCI). They are also used as ports D;j'
D4 and Dr,. For details, refer to "SERIAL COMMUNICA nON
INTERFACE. "
•
~OFF
\
$OFFF
$1000
4095
4096
NUM
This terminal is not intended for user applications. It must be
grounded to Vss.
Input/Output Terminals (Ao -
$003F
$0040
Not Used
RES
Used to reset the MCU. Refer to "RESET" for details.
0
1
2
3
4
5
6
7
8
9
10
$ 100
•
•
$0000
I/O Ports
Timer
SCI
ROM
(4,096Bytes)
Vectors
A
B
C
0
PORT A DDR
PORT BOOR
PORT C DDR
PORT DOOR
Timer Data Reg
Timer CTRL Reg
Misc Reg
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$OA
Not Used
1----------$lFF4
Interrupt
8180
819 1
8192
PORT
PORT
PORT
PORT
16
17
18
$lFFF
$2000
SCI CTRLReg
SCI STS Reg
SCI Data Reg
$10
$11
$12
Not Used
Not Used
$3F
63
16383
$3FFF
Memory Map of HD6305VO MCU
Figure 4
7 6 543 2 1 0
Condition
n-4 1 1 1
n+l
Code Register
I
CK (05)
n-3
Accumulator
n+2
n-2
Index Register
n+3
Pull
Used to input or output clocks for serial operation.
•
•
Rx (0 4 )
Used to receive serial data.
n-l
Tx (0 3 )
Used to transmit serial data.
n
PCW
PCl"
n+4
n+5
Push
• MEMORY MAP
The memory map of the HD6305VO MCU is shown in Fig. 4.
During interrupt processing, the contents of the MCU registers
are saved into the stack in the sequence shown in Fig. 5. This
saving begins with the lower byte (PCL) of the program counter.
Then the value of the stack pointer is decremented and the higher byte (PCH) of the program counter, index register (X), accumulator (A) and condition code register (CCR) are stacked in
that order. In a subroutine call, only the contents of the program
counter (PCH and PCL) are stacked.
550
0 01
• In a subroutine call, only PCl and PCH are stacked.
Figure 5 Sequence of Interrupt Stacking
• REGISTERS
There are five registers which the programmer can operate.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H D6305VO, HD63A05VO, H D63B05VO
a
7
1
A
1.-_ _ _ _ _ _ _ _
---1 Accumulator
a
7
1
index
IRegister
X
1.-_ _ _ _ _ _ _ _---1
13
a
PC_ _ _ _ _ _ _ IProgram
1 ________
13
6 5
a
~1_o~lo~l_ol~o~lo~I_OLI1~IL1~1_____sP____~I~~~~r
~
~.Counter
r--r---.,...--r---r......., Con d iti 0 n
L...,....L....,...J'-,.--L-.,.....L..,....J
Code
Reg iste r
~g~~~(..
Zero
L -_ _ _ Negative
'-------Interrupt
Mask
' - - - - - - - - Half
Carry
Figure 6
•
Programming Model
Accumulator (A)
This accumulator is a general purpose 8-bit register which
holds operands or the result of arithmetic operation or data
processing.
•
Negative (N):
Index Register (X)
Zero (Z):
Carry/
Borrow (C):
•
Table 1 Priority of Interrupts
Priority
Program Counter (PC)
The program counter is a 14-bit register that contains the address of the next instruction to be executed.
•
Interrupt
Vector Address
1
RES
$1FFE,
$1FFF
2
SWI
$1FFC,
$1FFD
3
INT
$1FFA,
$1FFB
4
TIMER/INT2
$1FF8,
$1FF9
5
TIMER (WAIT)
$1 FF6,
$1FF7
6
SCI/TIMER2
$1FF4,
$1FF5
Stack Pointer (SP)
The stack pointer is a 14-bit register that indicates the address
of the next stacking space. Just after reset, the stack pointer is set
at address $OOFF. It is decremented when data is pushed, and incremented when pulled. The upper 8 bits of the stack pointer are
fixed to 00000011. During the MCU being reset or during a reset
stack pointer (RSP) instruction, the pointer is set to address
$OOFF. Since a subroutine or interrupt can use space up to address $OOCI for stacking, the subroutine can be used up to 31
levels and the interrupt up to 12 levels.
•
INTERRUPT
There are six different types of interrupt: external interrupts
(INT, INT), internal timer interrupts (TIMER, TIMER 2), serial
interrupt (SCI) and interrupt by an instruction (SwC.
Of these six interrupts, the INT2 and TIMER or the SCI and
TIMER2 generate the same vector address, respectively. Although, a different vector address is generated for a timer interrupt during the wait mode, as shown in Table 1.
When an interrupt occurs, the program in progress stops and
then the CPU status is saved onto the stack. And then, the interrupt mask bit (I) of the condition code register is set and the
start address of the interrupt processing routine is obtained from
a particular interrupt vector address. Then the interrupt routine
starts from the start address. System can exit from the interrupt
routine by a RTI instruction. When this instruction is executed,
the CPU status before the interrupt (saved onto the stack) is
pulled and the CPU restarts the sequence with the instruction
next to the one at which the interrupt occurred. Table 1 lists the
priority of interrupts and their vector addresses.
The index register is an 8-bit register, and is used for index
addressing mode. Each of the addresses contained in the register
consists of 8 bits which, combined with an offset value, provides
an effective address.
In the case of a read/modify/write instruction, the index register can be used like an accumulator to hold operation data or the
result of operation.
If not used in the index addressing mode, the register can be
used to store data temporarily.
•
lowing the CLI has been executed')
Used to indicate that the result of the most recent arithmetic operation, logical operation or
data processing is negative (bit 7 is logic" 1").
Used to indicate that the result of the most recent arithmetic operation, logical operation or
data processing is zero.
Represents a carry or borrow that occurred in
the most recent arithmetic operation. This bit is
also affected by the Bit Test and Branch instruction, a shift instruction and a Rotate instruction .
Condition Code Register (CCR)
The condition code register is a S-bit register, each bit indicating the result of the instruction just executed. The bits can be individually tested by conditional branch instructions. The CCR
bits are as follows:
Half Carry (H): Used to indicate that a carry occurred between
bits 3 and 4 during an arithmetic operaJion
(ADD, ADC).
Setting this bit causes all interrupts, except a
Interrupt 0):
software interrupt, to be masked. If an interrupt
occurs with the bit I set, it is latched. It will be
processed the instant the interrupt mask bit is
reset. (More specifically, it will enter the interrupt processing routine after the instruction fol-
A flowchart of the interrupt sequence is shown in Fig. 7. A
block diagram of the interrupt request source is shown in Fig. 8.
In the block diagram of Fig. 8, the external interrupt INT2 is a
falling edge trigger input, whereas, the external interrupt INT can
be configured as a falling edge trigger input or a combination of
falling edge and low level trigger input, depending on the status
of bit 5 in the miscellaneous register (MR). When an interrupt
request is detected at the INT2 or INT inputs, an interrupt request is generated and latched. The INT interrupt request is automatically cleared if jumping is made to the INT processing
routine. Meanwhile, the INT2 request is cleared if "0" is written
in bit 7 of the miscellaneous register.
For the external interrupts ONT, INT), internal timer interrupts (TIMER, TIMER 2) and serial interrupt (SCI), each interrupt request is held, but not processed, if the I bit of the condition code register is set. Immediately after the I bit is cleared, the
corresponding interrupt processing starts according to the priority.
The INT2 interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by setting bit 6 of
the timer control register; the SCI interrupt by setting bit 5 of the
serial status register; and the TIMER2 interrupt hy selling bit 4 of
the serial status register.
The status of the INT terminal can hL' tL'~tL'd hy a BIL or BIH
instruction. The INT falling edge and l'allll\l( l"lll(c/low level detec-
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
551
HD6305VO,HD63A05VO,HD63B05VO - - - - - - - - - - - - - - - - - - - - - -
y
fNf
Fetch
Instruction
1 -+ I Bit
$FF -+ SP
O-+DDRs
Cleer INT Logic
$FO-+TDR
$7F -+ Timer Presceler
$50-+TCR
$3F -+SSR
$OO-+SCR
$SF -+MR
TIMER
y
SCI
N
Load PC From
SWI : $1 FFC, $1 FFD
INT: $1 FFA, $1 FFB
TIMER: $1 FF8, $1 FF9
INT,: $1 FF8, $1 FF9
TIMER (WAIT): $1FF6,
$1FF7
SCI: $1FF4, $lFF5
TIMER, : $1 FF4, $1 FF5
Figure 7 Interrupt Flowchart
tor circuit and its latching circuit are independeni 01 testing by
these instructions. This is also true with the status of the INT.,
terminal.
•
Miscellaneous Register (MR; $OOOA)
Miscellaneous Register (MR; $OOOA)
The external interrupt INT2 and the TIMER interrupt have
identical interrupt vector addresses, as shown in Table 1. For this
reason, bits 6 and 7 of a special register called the miscellaneous
register (MR: $OOOA) are available to control the INT2 interrupt.
Moreover, bit 5 of the MR controls the sensing mode for the
INT interrupt detector (falling edge detector or falling edge/low
level detector).
Bit 7 of the MR is the IN~terrupt request flag. When a
falling edge is detected at the INT2 terminal, bit 7 is set to "1"
552
Then the interrupt routine software (vector addresses: $lFFS,
$lFF9) checks bit 7 to see if an INT2 interrupt occurred. Bit 7
can be reset by software .
L -_ _ _ _ _ _ _ _ _ _ _
INT, Interrupt Mask
' - - - - - - - - - - - - - - INT, Interrupt Request Flag
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6305VO,HD63A05VO,HD63B05VO
Bit 6 is the INT2 interrupt mask bit. If this bit is set to "I",
then the INT2 interrupt is disabled. Both read and write are possible with bit 7, but" I" cannot be written in this bit by software.
In other words, an INT2 interrupt request by software is not possible.
Bit 5 is the control bit for INT interrupt detection. If this bit is
reset to "0", the detection logic will detect a falling edge. When
this bit is set to "I", the detection logic will detect a falling edge
or a low level.
When reset, bit 7 is cleared to "0", bit 6 is set to "I" and bit
5 is cleared to "0".
• TIMER
Figure 9 shows an Mev timer block diagram. The timer data
register is loaded by software and, upon receipt of a clock input,
begins to count down. When the timer data register (TDR) becomes "0", the timer interrupt request bit (bit 7) in the timer
control register is set. In response to the interrupt request, the
MeU saves its status into the stack and fetches the timer interrupt routine addresses $IFF8 and $IFF9 (or $IFF6 and $IFF7
when the timer interrupt occures during the wait mode) and ex-
ecutes the interrupt routine. The timer interrupt can be masked
by setting the timer interrupt mask bit (bit 6) in the timer control register. The mask bit (I) in the condition code register can
also mask the timer interrupt.
The source clock to the timer can be either an external signal
from the timer input terminal or the internal E signal (the oscillator clock divided by 4). If the E signal is used as the source,
the clock input can be gated by the input to the timer input terminal.
Once the timer count has reached 0, -it starts counting down
with "FF". The count can be monitored whenever desired by
reading the timer data register. This permits the program to know
the length of time having passed after the occurrence of a timer
interrupt, without disturbing the contents of the counter.
When the Mev is reset or placed in the stop mode, the timer
data register (TDR) is initialized to $FO. The timer interrupt request bit (bit 7) then is cleared and the timer interrupt mask bit
(bit 6) is set.
To clear the timer interrupt request bit (bit 7), it is necessary
to write "0" in that bit.
Condition Code
Register ICCR)
BIH. Bil Test
Falling
Edge
Detector
rnT
Interrupt
latch
INT
Falling Edge Detector
r---.......--t---------.
Vector Address Generated:
$1FF8. $1FF9
TIMER
1$1 FF6. $1 FF7 for
1..------1
--'~~:-::----------+---------.... i~~~~I~~~~~)t during
SCI/TIMER.
} - - - - - - 6 - - - - - - - - -..
Figure 8
Vector Address Generated:
$1 FF4. $1 FF5
Interrupt Request Generation Circuitry
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
553
H D6305VO,H D63A05VO,H D63B05VO - - - - - - - - - - - - - - - - - - - - - - Table 2
TCR7
Timer interrupt request
a
Absent
Clock Source Selection
TCR
Bit 5
Bit 4
Clock input,source
Pre.sent
TCR6
0
0
Internal clock E
Timer interrupt mask
0
1
E under TIMER terminal control
Enabled
1
0
No clock input (counting stopped)
Disabled
1
1
Event input from TIMER terminal
a
•
Timer Control Register ITCR; $0009)
Selection of a clock source, selection of a prescaler frequency
division ratio, and a timer interrupt can be controlled by the
timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four modes
(see Table 2) can be selected by bits 5 and 4 of the timer control
register (TCR).
A prescaler division ratio is selected by the combination of
three bits (bits 0, 1 and 2) of the timer control register (see
Table 3). There are eight different division ratios: + 1, + 2, + 4,
+ 8, + 16, + 32, + 64 and + 128. After reset, the TCR is set to
the + 1 mode.
Table 3
Timer Control Register (TCR; $0009)
L -_ _ _ _ _ _ _ _ _ _ _
Prescaler Division Ratio Selection
TCR
Bit 2
Bit 1
Timer interrupt mask
Timer interrupt request
L -_ _ _ _ _ _ _ _ _ _ _ _ _
After reset, the TCR is initialized to "E under timer terminal
control" (bit 5 = 0, bit 4 = 1). If the timer terminal is "1", the
counter starts counting down with "$FO" immediately after reset.
When "1" is written in bit 3, the prescaler is initialized to
"$7F". This bit always shows "0" when read.
Bit 0
Prescaler division ratio
0
0
0
+1
0
0
1
+2
0
1
0
+4
0
1
1
+8
1
0
0
+16
1
0
1
+32
1
1
0
+64
1
1
1
+128
Initialize
(Internal
Clock)
E -----1f----i
Timer Data
Register
~----~-------r----~
Write
Figure 9
Read
Timer Block Diagram
A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "1". When a timer inter-
554
Timer Interrupt
rupt occurs, "1" is set in the timer interrupt request bit. This bit
can be cleared by writing "0" in that bit.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H D6305VO, H D63A05VO, H D63B05VO
•
ister and data transfer.
SERIAL COMMUNICATION INTERFACE (SCI)
This interface is used for serial transmission or reception of 8bit data. Sixteen transfer rates are available in the range from 1
ILs to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one eighth counter and
one prescaler. (See Fig. 10.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 3, 4
and 5 of port D. Described below are the operations of each reg-
•
SCI Control Register (SCR; $0010)
SCI Control Registers (SCR; 0010)
E
_
Di--,
'--.,............
---.~
r--
Ds(CK) :
Transfer
Clock
Generator
I
I
I
I
I
I
I
Initialize
I
D 4 (Rx) :
----.
D 3 (Tx) :
:-.---...J
L ______ .J
I
SCI Status Register
(SSR :$0011 )
SCI/TIMER2
Figure 10 SCI Block Diagram
Bit 7 (SCR7)
When this bit is set, the DOR corresponding to the Oa becomes" 1" and this terminal serves for output of SCI data. After
reset, the bit is cleared to "0".
D3 terminal
SCR7
o
Used as I/O terminal (by DDR)
Serial data output (DDR output)
Bit 6 (SCR6)
When this bit is set, the OOR corresponding to the 0 4 becomes "0" and this terminal serves for input of SCI data. After
reset, the bit is cleared to "0".
D4 terminal
SCR6
o
Used as I/O terminal (by DDR)
Bits 5 and 4 (SCR5, SCR4)
These bits are used to select a clock source. After reset, the
bits are cleared to "0".
Serial data input (DDR input)
SCR5 SCR4
Clock source
Ds terminal
0
0
-
0
1
-
1
0
Internal
Clock output (DDR output)
1
1
External
Clock input (DDR input)
Bits 3 - 0 (SCR3 - SCRO)
These bits are used to select a transfer clock rate. After reset,
the bits are cleared to "0".
Used as I/O terminal (by
DDR)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
555
HD6305VO,H D63A05VO,H D63B05VO - - - - - - - - - - - - - - - - - - - - - -
SCR3
SCR2
SCR1
SCRO
Transfer clock rate
4.00 MHz
4.194MHz
1 J.Ls
0.95J.Ls
2 J.LS
1.91 J.Ls
0
0
0
0
0
0
0
1
0
0
1
0
4J.Ls
3.82 J.LS
0
0
1
1
8J.Ls
7.64J.Ls
I
I
I
I
I
I
1
1
1
1
32768 J.LS
1/32 s
Bit 4 (SSR4)
Bit 4 is the TIMERz interrupt mask bit which can be set or
cleared by software. When the bit is "I", the TIMERz interrupt
(SSR6) is masked. When reset, it is set to "1".
Bit 3 (SSR3)
When "1" is written in this bit, the prescaler of the transfer
clock generator is initialized. When read, the bit always is "0".
Bits 2 - 0
Not used.
•
•
SCI Data Register (SDR; $0012)
A serial-parallel conversion register that is used for transfer of
data.
•
SCI Status Register (SSR; $0011)
76543210
Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon completion of transmitting or receiving 8-bit data. It is cleared when
reset or data is written to or read from the SCI data register with
the SCR5 = "I". The bit can also be cleared by writing "0" in
it.
Data Transmission
By writing the desired control bits into the SCI control registers, a transfer rate and a source of transfer clock are determined
and bits 3 and 5 of port D are set at the serial data output terminal and the serial clock terminal, respectively. The transmit data
should be stored from the accumulator or index register into the
SCI data register. The data written in the SCI data register is output from the D3/Tx terminal, starting with the LSB, synchronously with the falling edge of the serial clock. (See Fig. 11.)
When 8 bits of data have been transmitted, the interrupt request
bit is set in bit 7 of the SCI status register. This request can be
masked by setting bit 5 of the SCI status register. Once the data
has been sent, the 8th bit data (MSB) stays at the D/Tx terminal. If an external clock source has been selected, the transfer
rate determined by bits 0 - 3 of the SCI control register is ignored, and the D/CK termina~ set as input. If the internal
clock has been selected, the D/CK terminal is set as output and
clocks are output at the transfer rate selected by bits 0 - 3 of the
SCI control register.
Bit 6 (SSR6)
Bit 6 is the TIMERz interrupt request bit. TIMERz is used
commonly with the serial clock generator, and SSR6 is set each
time the internal transfer clock falls. When reset, the bit is
cleared. It also be cleared by writing "0" in it. (For details, see
TIME~.)
Bit 5 (SSRS)
Bit 5 is the SCI interrupt mask bit which can be set or cleared
by software. When it is "I", the SCI interrupt (SSR 7) is masked.
When reset, it is set to "I".
SSR7
o
SCI interrupt request
Absent
Present
SSR6
a
TIMER2 interrupt request
Absent
Present
SSR5
o
SCI interrupt mask
Enabled
Figure 11
•
SCI Timing Chart
Data Reception
By writing the desired control bits into the SCI control register, a transfer rate and a source of transfer clock are determined
and bits 4 and 5 of Port D are set at the serial data input terminal and the serial clock terminal, respectively. Then dummy-writing or -reading the SCI data register, the system is ready for receiving data. (This procedure is not needed for the second and
subsequent data receptions. It must be taken only after resetting.)
The data from the D/Rx terminal is input to the SCI data
register synchronously with the leading edge of the serial clock
(see Fig. 11). When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI status register. This request can be masked by setting bit S of the SCI status register. If
an external clock source have been selected, the transfer rate determined by bits 0 - 3 of the SCI control register is ignored and
the data is received synchronously with the clock from the D-I
CK terminal. If the internal clock has been selected, the D-icK
terminal is set as output and clocks are output at the transfer' rate
selected by bits 0 - 3 of the SCI control register.
Disabled
•
SSA4
a
TIMER2 interrupt mask
Enabled
Disabled
556
TIMER2
The SCI transfer clock generator can be used as a timer. The
clock selected by bits 3 - 0 of the SCI control register (4 ILs approx. 32 ms (for oscillation at 4 MHz» is input to bit 6 of the
SCI status register and the TIMERz interrupt request bit is set at
each falling edge of the clock. Since interrupt requests occur periodically, TIMERz can be used as a reload counter or clock.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - HD6305VO,HD63A05VO,HD63B05VO
---g>1
~
CD
_ _..J
: Transfe r
clock generator is reset and mask bit (bit 4
of SCI status register) is cleared.
interrupt request
@.@ : TIMER2 interrupt request bit cleared
®. ® : TlMER2
TIMER2 is commonly used with the SCI transfer clock generator. If wanting to use TIMER 2 . independently of the SCI, specify
"External" (SCR5 = 1, SCR4 = 1) as the SCI clock source.
If "Internal" is selected as the clock source, reading or writing
the SDR causes the prescaler of the transfer clock generator to
be initialized.
•
All input/output terminals are TTL compatible and CMOS
compatible in respect of both input and output.
I[ I/O ports are not used, they should be connected to VSS
via resistors. With none connected to these terminals, there is
the possibility of power being consumed despite that they are
not used.
•
RESET
The MCV can be reset either by external reset input (RES) or
power-on reset. (See Fig. 13.) On power up, the reset input must
be held "Low" for at least tose to assure that the internal oscillator is stabilized. A sufficient time of delay can be obtained by
connecting a capacitan~e to the RES input as shown in Fig. 14.
5V
Vcc
OV
I/O PORTS
There are 31 input/output terminals (ports A, B, C, D). Each
110 terminal can be selected for either input or output by the
data direction register. More specifically, an 110 port will be input
if "0" is written in the data direction register, and output if "1"
is written in the data direction register. Port A, B, C or Dreads
latched data if it has been programmed as output, even with the
output level being fluctuated by the output load. (See Fig. 12.)
When reset, the data direction register goes "0" and all the
input/output terminals are used as input.
V
RES
Terminal --------~
-
tRHL
~VIH RES
f-----
Internal _ _ _ _ _ _ _ _ _ _ _.....J
Reset
Figure 13
Power On and Reset Timing
l00k!l typ
,*22.IIF
HD6305VO
MCU
Bit of data
direction
register
Bit of
output
data
1
0
1
1
0
X
Status of
output
Input to
CPU
Figure 14
•
0
1
3-state
0
1
Pin
Figur.e 12 Input/Output Port (Ports A, B, C and D) Diagram
Input Reset Delay Circuit
INTERNAL OSCILLATOR
The internal oscillator circuit is designed to meet the requirement for minimum external configurations. It can be driven by
connecting a crystal (AT cut 2.0 - 8.0 MHz) or ceramic oscillator between pins 38 and 39 depending on the required oscillation
frequency stability.
Three different terminal connections are shown in Fig. 15.
Figs. 16 and 17 illustrate the specifications and typical arrangement of the crystal, respectively.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
557
HD6305VO,HD63A05VO,HD63B05VO
•
iO-~.OMH>=38 XTAl
HD6305VO
MCU
10-22pF±20%
•
Wait Mode
When WAIT instruction being executed, the MCU enters into
the wait mode. In this mode, the oscillator stays active but the
internal clock stops. The CPU stops but the peripheral functions
- the timer and the serial communication interface - stay
active. (NOTE: Once the system has entered the wait mode, the
serial communication interface can no longer be retriggered.) In
the wait mode, the registers (except the I bit of the condition
code register which is cleared), RAM and I/O terminals hold
their condition just before entering into the wait mode.
The escape from this mode c~e done by interrupt (INT,
TIMERIINT2 or SCI/TIMER 2), RES or STBY. The RES resets
the MCU and the STBY brings it into the standby mode. (This
will be mentioned later.)
When interrupt is requested to the CPU and accepted, the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If an interrupt other
than the INT (i.e., TIMER/INT2 or SCIITIMER2) is masked by
the timer control register, miscellaneous register or serial status
register, there is no interrupt request to the CPU, so the wait
mode cannot be released.
Fig. 18 shows a flowchart for the wait function .
Crystal Oscillator
HD6305VO
MCU
External
Ceramic Oscillator
Clock
Input39 EXTAL
NC38 XTAL HD6305VO
MCU
•
External Clock Drive
Figure 15
Internal Oscillator Circuit
C,
s
AT Cut
Parallel
Resonance
Co=7pF max.
EXTAL
f=2.0-8.0MHz
39
Rs=6OQ max.
C~
XTAL
38
Co
Figure 16
Parameters of Crystal
Use as short wirings as possible for connection of the crystal
with the EXT AL and XTAL terminals. Do not allow these
wirings to cross others.
Figure 17
558
Typical Crystal Arrangement
Stop Mode
When STOP instruction being executed, MCU enters into the
stop mode. In this mode, the oscillator stops and the CPU and
peripheral functions become inactive, but the RAM, registers
(except bits 6 and 7 of the timer control register and the I bit of
the condition code register) and I/O terminals hold their condition just before entering the stop mode. Bits 6 and 7 of the timer
control register are initialized to "1" and "0", bits 7, 6, 5 and 4
of SCI status register are initialized "0", "0", "1", "1", respectively, and the I bit of the condition code register is cleared.
The escape from this mode can be done by an external interrupt (INT or INT2), RES or STBY. The RES resets the MCU
and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted, the
stop mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the INT2 interrupt
is masked by the miscellaneous register, there is no interrupt request to the MCU, so the stop mode cannot be released.
Fig. 19 shows a flowchart for the stop function. Fig. 20 shows
a timing chart of return to the operation mode from the stop
mode.
For releasing from the stop mode by an interrupt, oscillation
starts upon input of the interrupt and, after the internal delay
time for stabilized oscillation, the CPU becomes active. For restarting by RES, oscillation starts when the RES goes "0" and
the CPU restarts when the RES goes" 1". The duration of RES
= "0" must exceed tose to assure stabilized oscillation.
•
[NOTE J
lOW POWER DISSIPATION MODE
The HD6305VO has three low power dissipation modes: wait,
stop and standby.
f-----.>-3_9~ EXTAL
Standby Mode
The MCU enters into the standby mode when the STBY terminal goes "Low". In this mode, all operations stop and the internal condition is reset but the contents of the RAM are hold.
The I/O terminals turn to high-impedance state. The standby
mode should escape by bringing STBY "High". The CPU must
be restarted by reset. The timing of input signals at the RES and
STBY terminals is shown in Fig. 2l.
Table 4 lists the status of each parts of the MCU in each low
power dissipation modes. Transitions between each mode are
shown in Fig. 22.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - HD6305VO,HD63A05VO,HD63B05VO
Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop
Clear I bit
Initialize
CPU, TIMER. SCI,
1/0 and All
Other Functions
No
No
Restart
Processor Clocks
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 18
Wait Mode Flowchart
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
559
HD6305VO,H D63A05VO,HD63B05VO - - - - - - - - - - - - - - - - - - - - - -
Stop Oscillator
and All Clocks
Clear I bit
TCR7 <- 0
TCR6 <- 1
SSR7 <- 0
SSR6 <- 0
SSR5 <- 1
SSR4 <- 1
No
Turn on Oscillator
Wait for Time Delay
to Stabilize
Turn on Oscillator
Wait for Time Delay
to Stabilize
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
, Figure 19 Stop Mode Flowchart
560
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - HD6305VO,HD63A05VO,HD63B05VO
Oscillator
1111111111111111111111111111
a111111111111111111111111111111111111111111111111111111111111
II
(
~'l----+-----'
E
I
stabilized (built-in delay time)
Interrupt
STOP instruction
executed
restart
(a) Restart by Interrupt
Oscillator
1111II111I11111111111111111 II
~~-+__~
E
Time required for oscillation to become
STOP instruction
executed
stabil ized (toscl
RES
(b) Restart by Reset
Figure 20
Timing Chart of Releasing from Stop Mode
i
I
I
I
I
~_~
_ _I
~
I
__I
~L~
________
~~
__________
~
________
~
tosc
Figure 21
Table 4
Restart
Timing Chart of Releasing from Standby Mode
Status of Each Part of MCU in Low Power Dissipation Modes
Condition
Start
Mode
WAIT
-
Software
STOP
Standby
Hardware
• RegISter
In
Oscillator
CPU
Timer,
Serial
WAIT instruction
Active
Stop
Active
STOP instruction
Stop
Stop
STBY="Low"
Stop
Stop
the CPU (except
..
I bit In the CCR
Escape
RAM
I/O
terminal
Keep
Keep
Keep
STBY, RES, INT, INT 2 ,
each interrupt request of
TIMER, TIMER 2 , SCI
Stop
Keep
Keep
Keep
STBY, RES, INT, INT2
Stop
Reset
Keep
High im·
pedancc
Register*
STBy,="High"
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
561
HD6305VO,HD63A05VO,HD63B05VO
See Fig. 25. In the direct addressing mode, the address of the
operand is contained in the 2nd byte of the instruction. The user
can gain direct access to memory up to the lower 255th address.
All RAM and I/O registers are on page 0 of address space so that
the direct addressing mode may be utilized.
•
Extended
See Fig. 26. the extended addressing is used for referencing to
all addresses of memory. The EA is the contents of the 2 bytes
that follow. the operation code. An extended addressing instruction requires a length of 3 bytes.
•
Relative
See Fig. 27. The relative addressing mode is used with branch
instructions only. When a branch occurs, the program counter is
loaded with the contents of the byte following the operation code.
EA = (PC) + 2 + ReI., where ReI. indicates a signed 8-bit data
following the operation code. If no branch occurs, ReI. = O.
When a branch occurs, the program jumps to any byte in the
range + 129 to -127. A branch instruction requires a length of 2
bytes.
•
Indexed (No Offset)
See Fig. 28. The indexed addressing mode allows access up to
the lower 255th address of memory. In this mode, an instruction
requires a length of one byte. The EA is the contents of the index register.
Figure 22 Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset
•
•
BIT MANIPULATION
The HD6305VO MCV can use a single instruction (BSET or
BCLR) to set or clear one bit of the RAM or an 110 port. Every
bit of memory or I/O within page 0 ($00 - $FF) can be tested
by the BRSET or BRCLR instruction; depending on the result of
the test, the program can branch to required destinations. Since
bits in the RAM, or 110 can be manipulated, the user may use a
bit within the RAM as a flag or handle a single 110 bit as an independent I/O terminal. Fig. 23 shows an example of bit
manipulation and the validity of test instructions. In the example,
the program is configured assuming that bit 0 of port A is connected to a zero cross detector circuit and bit I of the same port
to the trigger of a triac.
The program shown can activate the triac within a time of
lOp.s from zero-crossing through the use of only 7 bytes on the
ROM. The on-chip timer provides a required time of delay and
pulse width modulation of power is also possible.
•
Figure 23
•
BRClR 0, PORT A, SELF 1
BSET 1, PORT A
BClR 1, PORT A
Exa~ple of Bit Manipulation
ADDRESSING MODES
Ten different addressing
HD6305VO MCV.
•
modes
are
available
to
the
•
Bit Set/Clear
See Fig. 31. This addressing mode is applied to the BSET and
BCLR instructions that can set or clear any bit on page O. The
lower 3 bits of the operation code specify the bit to be set or
cleared. The byte that follows the operation code indicates an address within page O.
Bit Test and Branch
See Fig. 32. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0 and
can be branched in the relative addressing mode. The byte to be
tested is addressed depending on the contents of the byte following the operation code. Individual bits within the byte to be
tested are specified by the lower 3 bits of the operation code. The
3rd byte represents a relative value which will be added to the
program counter when a branch condition is established. Each of
these instructions should be 3 bytes long. The result of the test is
written in the carry bit of the condition code register. (Set if true,
cleared otherwise.)
Immediate
See Fig. 24. The immediate addressing mode provides access
to a constant which does not vary during execution of the program.
This access requires an instruction length of 2 bytes. The effective address (EA) is PC and the operand is fetched from the
byte that follows the operation code.
•
Indexed (16-bit Offset)
See Fig. 30. The contents of the 2 bytes following the operation code are added to content of the index register to compute
the value of EA. In this mode, the complete memory can be accessed. When used in the indexed addressing mode (I6-bit offset), an instruction must be 3 bytes long.
•
SE l F 1.
Indexed (S-bit Offset)
See Fig. 29. The EA is the contents of the byte following the
operation code, plus the contents of the index register. This
mode allows access up to the lower 51Ith address of memory.
Each instruction when used in the index addressing mode (8-bit
offset) requires a length of 2 bytes.
Direct
562
•
Implied
See Fig. 33. This mode involves no EA. All information
needed for execution of an instruction is contained in the operation code. Direct manipulation on the accumulator and index register is included in the implied addressing mode. Other instructions such as SWI and RTI are also used in this mode. All instructions used in the implied addressing mode should have a
length of one byte.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - HD6305VO,HD63A05VO,HD63B05VO
j
A
~
=
I
Memory
j
I---::::~
_ _-tA:::Ec::::J
FB
Index Reg
I
Stack Point
PROG LDA lI$FB
05BEt-:~~~f-_----~
Prog Count
05CO
CC
05BF'"
t-~;""--I
Figure 24
Example of Immediate Addressing
Memory
A
CATFCB32004B~~L:~~--~---~~------E::12[0::J
Index Reg
Stack Point
PROG LDA CAT 052D 1-~:""---1
Prog !ount
052F
CC
052E I-"';';~--f
Figure 25
Example of Direct Addressing
Memory
~
:
PROG LDA CAT
0000
A
:
40
Index Reg
04091-~=-_L
I
040AI--:;;;;.....~
040BI-""'::::""'----li
Stack Point
CATFCB6406E5~~£:::t-------_J
Figure 26
Prog Count
040C
CC
Example of Extended Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
563
H D6305VO, H D63A05VO, H D63B05VO
PROG BEQ PROG2 04A 7
04A81--"";;';---I
Figure 27
Example of Relative Addressing
Memory
A
TABLFCC LI
00B8~~~::1---~~~-------t----------~~4~C:::J
B8
Stack POint
Prog Count
05F5
CC
Figure 28
Example of Indexed (No Offset) Addressing
Memory
TA8L FCB
FCB
FCB
FCB
.8F
#86
#DB
If.CF
BF
86
DB
CF
0089
008A
008B
008C
PROG LOA TABl.X 075B
075C
A
CF
Index Reg
03
Stack POint
E6
89
I
Prog Count
075D
CC
~
I
I
I
Figure 29 Example of Indexed (8-bit Offset) Addressing
564
~HITACHI
Hitachi America Ltd_ • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6305VO,HD63A05VO,HD63B05VO
Memory
~
PROG lDA TABL.X 0692
0693
0694
A
DB
Index Reg
02
Stack Point
I
Prog count
0695
CC
TABl FCB
FCB
FCB
FCB
I
II BF 077E
1186 077F
II DB 0780
IICF
DB
CF
0781
Figure 30 Example of Indexed (16-bit Offset) Addressing
Memory
PORT B EQU 1 0001 t-----'B;;:.-F_~I
Index Reg
I
PROG BClR 6 PORT B 058F
0590
1D
Stack POint
l:~O~lt:j----~
Prog Count
0591
CC
~
I
,
t
,
Figure 31
Example of Bit Set/Clear Addressing
PORT C EQU 2 0002 I--~FO~---I
Index Reg
I
PROG BRClR 2.PORT CPROG 2 0574
05
05751--'::'0::"2- - I
05761-----::'1D;'----I
In this example bit C of the CC
becomes "0",
Figure 32
Example of Bit Test and Branch Addressing
~HITACHI
Hitachi America Ltd_ • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
565
HD6305VO,HD63A05VO,HD63B05VO
Memory
,"00'" 0'"
~
~
~
,
,
,
I
I
,
I
I
Figure 33
•
Example of Implied Addressing
INSTRUCTION SET
•
There are 62 basic instructions available to the HD630SVO
MeU. They can be classified into five categories: register/memory, read/modify/write, branch, bit manipulation, and control. The
details of each instruction are described in Tables S through 11.
•
Register/Memory Instructions
Most of these instructions use two operands. One operand is
either an accumulator or index register. The other is derived
from memory using one of the addressing modes used on the
HD630SVO MeU. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump instruction (JSR). See Table S.
•
566
A branch instruction branches from the program sequence in
progress if a particular condition is established. See Table 7.
•
Bit Manipulation Instructions
These instructions can be used with any bit located up to the
lower 2SSth address of memory. Two groups are available; one
for setting or clearing and the other for bit testing and branching.
See Table 8.
•
Control Instructions
The control instructions control the operation of the MeU
which is executing a program. See Table 9.
•
Read/Modify/Write Instructions
These instructions read a memory or register, then modify or
test its contents, and write the modified value into the memory
or register. Zero test instruction (TST) does not write data, and
is handled as an exception in the read/modify/write group. See
Table 6.
Branch Instructions
List of Instructions in Alphabetical Order
Table 10 lists all the instructions used on the HD630SVO
MeU in the alphabetical order.
•
Operation Code Map
Table 11 shows the operation code map for the instructions
used on the MeU.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H D6305VO, H D63A05VO, H D63B05VO
Table 5
Register/Memory Instructions
Addressing Modes
Indexed
Operations
Mnemonic
Immediate
Direct
Extended
Indexed
OP II
- OP
II
- OP
II
- OP
II
- OP
II
- OP
II
-
Load A from Memory
LDA
A6
2
2
2
3
C6
3
4
F6
1
3
E6
2
4
D6 3
5
Load X from Memory
LDX
AE
2
2
BE
2
3
CE
3
4
FE
1
3
EE
2
4
DE
3
5
M~X
Store A in Memory
STA
- - -
B7
2
3 C7
3
4
F7
1
4
E7
2
4 D7
3
5
A~M
B6
H
STX
-
- -
BF
2
3
CF
3
4
FF
1
4
EF
2
4
DF
3
5
X~M
ADD
AB
2
BB
2
3
CB
3
4
FB
1
3
EB
2
4
DB 3
5
A+M-·A
C9
ADC
A9
2
2
B9
2
3
3
4
F9
1
3
E9
2
4
D9 3
5
A+M+C-A
Subtract Memory
SUB
AO
2
2
BO
2
3 CO 3
4
FO
1
3
EO
2
4
DO 3
5
A-M~A
A with Borrow
SBC
A2
2
2
B2
2
3 C2
3
4
F2
1
3
E2
2
4
D2 3
5
A-M-C-A
AND Memory to A
AND
A4
2
2
84
2
3 C4
3
4
F4
1
3
E4
2
4 D4 3
5
A·
OR Memory with A
ORA
AA
2
2
BA
2
3 CA 3
4
FA
1
3
EA
2
4 DA 3
5
A+M~A
EOR
A8
2
2
B8
2
3 C8
3
4
F8
1
3
E8
2
4
D8 3
5
A+M~A
CMP
A1
2
2
B1
2
3 C1
3
4
F1
1
3
E1
2
4
D1
3
5
A-M
CPX
A3
2
2
B3
2
3 C3
3
4
F3
1
3
E3
2
4 D3
3
5
X-M
2
A·M
2
B5
2
3 C5
3
4
F5
1
3
E5
2
4 D5
3
5
- - -
BC
2
2 CC
3
3
FC
1
2
EC
2
3 DC 3
4
Jump to Subroutine
JSR
- -
BD
2
5 CD 3
6
FD
1
5 ED 2
5 DD 3
6
-
1\
1\
1\
1\
1\
t\
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
Table 6
" "•
"•
1\
Bit Test Memory with
A5
/\
/\
Arithmetic Compare X
BIT
1\
··"
·• ·• " ·
"
··" "
··• ··• .." .• ·•
·
Arithmetic Compare A
JMP
C
"
• •
• •
M~A
Exclusive OR Memory
A (Logical Compare)
1\
1\
Subtract Memory from
Jump Unconditional
1\
/\
Add Memory and Carry
with Memory
Z
1\
1\
to A
with Memory
N
1\
/\
Store X in Memory
with A
I
·· ·· ··•
·• ·• " •
·" "
" · " ""
· ·"
M~A
Add Memory to A
2
Condition
Code
Booleanl
Arithmetic
Operation
Indexed
(No Offset) (8-Bit Offset) (16-811 Offset)
Read/Modify/Write Instructions
Addressing Modes
Operations
Indexed
Mnemonic
Implied(A)
Imploed(X)
Indexed
(No Offset) (8-BII Offset)
Direct
OP
II
-
OP II
-
OP II
-
OP
II
- OP
II
-
Increment
INC
4C
1
2
5C
1
2
3C
2
5
7C
1
5
6C
2
6
A+1-A or X+1-X or M+l-M
H
Decrement
DEC
4A
1
2
5A
1
2
3A
2
5
7A
1
5
6A
2
6
A - 1 -A or X - 1 -X or M - 1 -M
Clear
CLR
4F
1
2
5F
1
2
3F
2
5
7F
1
5
6F
2
6
OO~A
Complement
COM
43
1
2
53
1
2
33
2
5
73 1
5
63
2
6
or
or
A~A
OO~X
X~X
or
OO~M
Or M-M
I
• •
OO-M~M
NEG
40
1
2
50
1
2
30
2
5
70
1
5
60
2
6
or
ROL
49
1
2
59
1
2
39
2
5
79
1
5
69
2
6
L6t I I I I I I Ib'iJ • •
Rotate Right Thru Carry
ROR
46
1
2
56
1
2
36
2
5
76
1
5
66
2
6
Lci=t I H'~":MI
Logical Shift Left
Logical Shift Right
lSL
LSR
48
44
1
1
2
2
58
54
1
1
2
2
38
34
2
2
5
5
78
74
1
1
5
5
68
64
2
2
6
6
e
b,
I ~"':xH
b,
[]-I
0-1 I
H'~"':MI
M
Ibo~
I I 1- 0
b,
bo
C
b,
e
I HJ
ASR
47
1
2
57
1
2
37
2
5
77
1
5
67
2
6
Arithmetic Shift Left
ASL
48
1
2
58
1
2
38
2
5
78
1
5
68
2
6
Equal to LSL
TST
4D
1
2
5D
1
2
4
7D
1
4
6D 2
5
A-OO or X-OO or M-OO
Test for Negative
2
3D
Symbols: Op = Operatton
# = Number of bytes
- = Number of cycles
""
" "
• "
"
""
""
•
""
·
·• ·
[(b'I H··HMI I 1-0 •
Arithmetic Shift Right
or Zero
C
·
·
·· ·
Rotate Left Thru Carry
C
Z
II
(2's Complement)
Aor Xor
N
• • "
• " " •
1
0
•
• t\ 1
II
OO-A-A or OO-X-X
Negate
COndition
Code
Booleanl Arithmetic Operation
·
1\
1\
II
/\
0
/\
• •
1\
·•
/\
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
" "
" •
567
HD6305VO,HD63A05VO,HD63B05VO
Table 7 Branch Instructions
Addressing Modes
Mnemonic
Operations
Relative
OP
#
-
Branch Always
BRA
20
2
3
None
Branch Never
BRN
21
2
3
None
Branch IF Higher
BHI
22
2
3
C+Z=O
Branch IF Lower or Same
BlS
23
2
3
C+Z=1
Branch IF Carry Clear
BCC
24
2
3
C=O
(BHS)
24
2
3
C=O
BCS
25
2
3
C=1
(BlO)
25
2
3
C=1
BNE
26
2
3
Z=O
(Branch IF Higher or Same)
Branch IF Carry Set
(Branch IF Lower)
Branch IF Not Equal
Condition Code
Branch Test
H
I
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • •
• • •
• • •
• • •
• • •
• • •
• • •
•
BEQ
27
2
3
Z=1
Branch IF Half Carry Clear
BHCC
28
2
3
H=O
Branch IF Half Carry Set
BHCS
29
2
3
H=1
Branch IF Plus
BPl
2A
2
3
N=O
Branch IF Minus
BMI
2B
2
3
N=1
BMC
2C
2
3
1=0
• •
BMS
20
2
3
1=1
Bil
2E
2
3
INT=O
•
•
•
•
Branch IF Equal
Branch IF Interrupt Mask
Bit is Clear
Branch IF Interrupt Mask
Bit is Set
Branch IF Interrupt Line
is low
Branch IF Interrupt Line
is High
BIH
2F
2
3
INT=1
Branch to Subroutine
BSR
AD
2
5
--
Symbols: Op
#
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
=Operation
= Number of bytes
- =Number of cycles
Table 8 Bit Manipulation Instructions
Operations
Mnemonic
Addressing Modes
Boolean/
Bit Test and Branch Arithmetic
Bit Set/Clear
Operation
op
op
;;
# -
-
Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear Bit n
BRSET n(n=0···7)
BRClR n(n=0···7)
BSET n(n=0···7)
10+2·n 2
BClR n(n=0···7)
11 +2·n 2
-
5
5
2·n
01+2·n
3
3
-
-
--
-
-
-
Symbols: Op c Operation
# = Number of bytes
a Number of cycles
568
5
5
-
1--->Mn
O--->Mn
Branch
Test
Mn=1
Mn=O
-
Condition Code
Z
C
H
I
•
•
•
•
• • •
• • •
• • • •
• • • •
N
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H D6305VO, H D63A05VO, H D63B05VO
Table 9
Control Instructions
Addressing Modes
Operations
Mnemonic
Transfer A to X
TAX
Implied
Condition Code
Boolean Operation
OP
#
-
97
1
Transfer X to A
TXA
9F
1
2
2
Set Carry Bit
SEC
99
1
1
1-C
Clear Carry Bit
CLC
9B
1
1
O-C
Set Interrupt Mask Bit
SEI
9B
1
2
1-1
Clear Interrupt Mask Bit
CLI
9A
1
2
0-1
10
A-X
X-A
Software Interrupt
SWI
B3
1
Return from Subroutine
RTS
B1
1
5
Return from Interrupt
RTI
BO
1
B
Reset Stack Pointer
RSP
9C
1
2
$FF-SP
No-Operation
NOP
9D
1
1
Advance Prog. Cntr. Only
Decimal Adjust A
DAA
BD
1
Converts binary add of BCD charcters Into
STOP
BE
1
WAIT
BF
1
2
4
4
Stop
Wait
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
H
I
•
•
•
•
•
• •
• •
• •
•1 •
•
0
1\
•
Mnemonic
•
•
•
•
?
•
•
•
•
1\*
Condition Code
Indexed
Indexed
Extended Relative (No Offset) (B-Bit)
Immediate'
Direct
ADC
X
X
X
ADD
X
X
AND
X
X
Indexed
(16-Bit)
X
X
X
X
X
X
X
X
X
X
X
ASl
X
X
X
X
ASR
BCC
X
X
X
X
Bit
Bit
Set/
Clear
Test &
Branch
BClR
X
X
BEQ
X
BHCC
X
BHCS
X
BHI
(BHS)
X
BIH
X
X
X
X
X
X
X
X
BlS
X
BMC
X
BMI
X
BMS
X
BNE
X
BPl
BRA
X
X
X
X
H
I
N
Z
C
1\
•
1\
1\
1\
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
1\
X
BCS
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
1\
0
Instruction Set (in Alphabetical Order)
Addressing Modes
Bil
BIT
(BlO)
C
• Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.)
Table 10
Implied
Z
• •
• •1
•
•
•
•
•
1
• •
• • •
? ? ?
• • •
• • •
•
0 • •
0 • •
•
•
•
?
•
•
•
•
BCD format
N
1\
1\
1\
1\
1\
•
/,
1\
1\
1\
1\
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
1\
•
•
•
•
•
•
•
•
•
•
1\
•
•
•
•
•
•
•
•
•
•
•
• •
• •
• •
• • • • •
• • • • •
• • • • •
• • • • •
(to be continued)
C
1\
•?
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
load CC Register From Stack
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
569
HD6305VO,HD63A05VO,HD63B05VO
Table 10 Instruction Set (in Alphabetical Order)
Addressing Modes
Condition Code
Bit
Mnemonic
Implied
Immediate
Direct
Extended Relative
Indexed
Indexed
Indexed
Set!
Test &
(No Offset)
(8-Bit)
(16-Bit)
Clear
Branch
x
BRN
x
x
BRCLR
BRSET
x
BSET
x
BSR
x
x
x
CLC
CLI
CLR
x
x
x
x
x
CMP
x
COM
x
CPX
x
x
DAA
DEC
x
x
x
x
x
x
x
x
x
x
x
EOR
x
INC
JMP
JSR
I
x
x
LOA
LOX
x
x
x
x
LSL
LSR
NEG
NOP
x
ORA
ROL
ROR
I
RSP
RTI
RTS
I
SBC
,
SEC
I
SEI
x
x
x
x
x
x
x
x
x
x
STX
TAX
TST
TXA
WAIT
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
X
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
H
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
x
x
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
570
x
x
x
x
x
x
SUB
SWI
x
x
x
STA
STOP
Bit
x
C
1\
•?
x
x
•
•
•
•
I
N
Z
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•1
•
0
•
•1
•
•
•
•
•
•
•
•
•
•0
•
•
•
•
•
•
•
1\
/\
1\
1\
1
1\
1\
1\
1\
0
1
1\
/\
1\
1\
1\
/\
C
•
/\
1\
•
•
0
•
•
1\
•
•
/\ •
• • •
• • •
1\
1\
/\
1\
1\
•
•
/\
1\
1\
0
1\
1\
1\
1\
1\
• • •
1\ 1\ •
1\
/\
1\
1\
/\
1\
•
?
•
1\
•
•
1\
•
• •
? ?
• •
1\
1\
•
•
1\
•
•
Carry Borrow
Test and Set if True. Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACftl
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
1\
1\
•
1
• •
1\ •
• •
1\ •
1\ 1\
• •
• •
1\ •
• •
• •
H D6305VO, H D63A05VO, H D63B05VO
Table 11 Operation Code Map
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Bit Manipulation
Test &
Set/
Branch
Clear
0
1
BRSETO
BSETO
BRClRO
BCLRO
BRSETl
BSETl
BClRl
BRCLRl
BRSET2
BSET2
BRClR2
BCLR2
BRSET3
BSET3
BRClR3
BCLR3
BRSET4
BSET4
BRClR4
BClR4
BRSET5
BSET5
BRClR5
BClR5
BRSET6
BSET6
BRClR6
BCLR6
BRSET7
BSET7
BRClR7
BClR7
2/5
3/5
(NOTES)
Branch
Read/Modify /Write
Rei
DIR A
X ,Xl ,XC
4
5
6
7
2
3
BRA
NEG
BRN
BHI
BlS
COM
BCC
lSR
BCS
ROR
BNE
BEQ
ASR
BHCC
LSL!ASL
BHCS
ROl
DEC
BPl
BMI
INC
BMC
TST
TST(-l)
BMS TSTI-lI
BIL
BIH
CLR
2/3
2/5 1/2 1/2 2/6 1/5
Control
Register /Memory
IMP IMP IMM DIR EXT ,X2 ,Xl ,XC
A
B
C
D
E
F +- HIGH
8
9
RTI' SUB
0
RTS' CMP
1
SBC
2
SWI' CPX
3 L
o
AND
4 W
BIT
5
lDA
6
TAX' STA
STAI+ll 7
CLC
EOR
8
--ADC
SEC
9
ORA
A
Cll*
ADD
B
SEI*
RSP' JMP(-l)
C
DAA' NOP BSR' JSR(+2) JSR(+l) JSRI+21 D
STOP' lDX
E
WAIT' TXA' STXI+ll F
STX
1./' 1/1 2/2 2/3 3/4 3/5 2/4 1/3
-
1. "-" is an undefined operation code.
2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).
The number of cycles for the mnemonics asterisked (-) is as follows:
RTI
8
TAX
2
RTS
5
RSP
2
SWI
10
TXA
2
DAA
2
BSR
5
STOP
4
ell
2
WAIT
4
SEI
2
3. The parenthesized numbers must be added to the cycle count of the particular instruction.
•
Additional Instructions
The following new instructions are used on the HD6305VO:
DAA Converts the contents of the accumulator into BCD code.
WAIT Causes the MCU to enter the wait mode. For this mode,
see the topic, Wait Mode.
STOP Causes the MCU to enter the stop mode. For this mode,
see the topic, Stop Mode.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
571
HD6305XO,HD63A05XO,--HD63B05XO
CMOS MCU(Microcomputer Unit)
The HD6305XO is a CMOS 8-bit single-chip microcomputer.
The CMOS unit is upward compatible with the HD6805 family
in respect to instructions. On the chip of the HD6305XO, a
CPU, a clock generator, a 4kB ROM, a 128-byte RAM, 55 I/O
terminals, two timers and a serial communication interface
(SCI) are built in. Because of the CMOS process, the HD6305XO
consumes less power than the NMOS. In addition, three low
power dissipation modes (stop, wait, and standby) support the
low power operating.
Other distinguished features include enhanced instruction
cycle of the main instructions and the use of three additional
instructions to obtain more improved system throughput.
• HARDWARE FEATURES
.8-bit based MCU
.4096-bytes of ROM
• 128-bytes of RAM
.A total of 55 terminals, including 32 I/O's, 7 inputs and 16
outputs
.Two timers
- 8-bit timer with a 7-bit prescaler (programmable prescaler;
event counter)
- 15-bit timer (commonly used with the SCI clock divider)
• On-chip serial interface circuit (synchronized with clock)
• Six interrupts (two external, two timer, one serial and one
software)
• Low power dissipation. modes
- Wait. . .. I n this mode, the clock oscillator is on and the
CPU halts but the timer/serial/interrupt function is operatable.
- Stop. . .. In th is mode, the clock stops but the RAM
data, I/O status and registers are held.
- Standby.. In th is mode, the clock stops, the RAM data
is held, and the other internal condition is
reset.
• Minimum instruction cycle time
HD6305XO ..... 1p.s (f = 1 MHz)
- HD63A05XO .... 0.67 p.s (f = 1.5 MHz)
- HD63B05XO .... 0.5p.s (f 2 MHz)
• Wide operating range
VCC = 3 to 6V (f = 0.1 to 0.5 MHz)
HD6305XO ..... f = 0.1 to 1 MHz (VCC = 5V ± 10%)
HD63A05XO .... f
0.1 to 1.5 MHz (VCC 5V ± 10%)
HD63B05XO .... f = 0.1 to 2 MHz (VCC = 5V ± 100/0)
.System development fully supported by an evaluation kit
=
=
572
HD6305XOP, HD63A05XOP,
HD63B05XOP
(DP-64S)
HD6305XOF, HD63A05XOF,
HD63B05XOF
(FP-64)
• SOFTWARE FEATURES
.Similar to HD6800
• Byte efficient instruction set
• Powerful bit manipulation instructions (Bit Set, Bit Clear, and
Bit Test and Branch usable for all RAM bits and all I/O terminals)
• A variety of interrupt.operations
.1 ndex addressing mode useful for table processing
• A variety of conditional branch instructions
• Ten powerful addressing modes
• All addressing modes adaptable to RAM, and I/O instructions
• Three new instructions, STOP, WAIT and DAA, added to the
HD6805 family instruction set
• I nstructions that are upward compatible with those of Motorola's MC6805P2 and MC146805G2
=
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------HD6305XO,HD63A05XO,HD63B05XO
• PIN ARRANGEMENT
• HD6305XOP, HD63A05XOP, HD63B05XOP
o
•
HD6305XOF, HD63A05XOF, HD63B05XOF
Go
G,
G2
G3
G.
Gs
EXTAL
NUM
TIMER
A7
Ge
G7
F7
Fe
Fs
F.
F3
F2
F,
Fo
E7
Ee
Ae
As
A.
A3 l
A2
A,
Ao
B7
Be
Bs
B6
B5
B4
B3
B2
Es
B.
B3
B2
E.
B,
C7/Tx
E,
Eo
07
C,/Rx
oe/ii'ii'f;
ClICK
Os
O.
E3
E2
Bo
C.
C3
C2
C,
03
02
0,
Co
Vee
B,
Bo
C7/Tx
Cs/Rx
I ~uuuuu..;;oo 000
~
'It
M
N
_
0
(J
.....
N
U
(Top View)
(Top View)
• BLOCK DIAGRAM
XTAl
EXTAl
RES
TIMER
Accumulator
8
PortA
110
A
CPU
Control
Index
8
Register
x
D,
D,,1Ii'r,
D.
g:
Terminals
0,
CPU
D,
Port 0
Input
Terminals
Eo
110
E,
E,
Terminals
::
Port B
E.
Port E
OutpUt
Terminals
E,
E,
F.
F,
F,
::
F,
F,
F,
Port F
OutpUt
Terminals
PortG
110
Terminal.
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
573
H D6305XO,H D63A05XO,HD63B05XO - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Supply voltage
Vee
-0.3- +7.0
V
Input voltage
Vin
-0.3 - Vee + 0.3
V
Operating temperature
Topr
0-+70
°c
Storage temperature
T stg
-55 - +150
°c
[NOTE]
These prod'Jcts have a protection circuit in their input tarminals against high electrostatic voltage or high electric fields. Notwithstanding,
be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normal
operation, we recommended Vln. Vout ; Vss ~ (V ln or Vout ) ~ Vee .
• ELECTRICAL CHARACTERISTICS
• DC Characteristics (Vee
=5.0V ± 10%, Vss =GND and T.· 0"" +70°C unless otherwise specified)
Item
Input
voltage
"High"
Symbol
Test
condition
ReS.mv
EXTAL
VIH
Others
Input voltage "Low"
Wait
lee
Stop
TIMER,
INT,
f
= 1MHz**
JlILI
~'li~P7'
Threestate
current
Ao -A 7,
Bo"" B7,
Co - C7 ,
Go"" G 7,
Eo - E7~**
Fo-F7***
Input
capacity
All
terminals
*VIHmin'" vcc-1.OV. VIL max
Vin
JlTSJi
Unit
Vee- 0.5
-
Vee+ 0.3
V
Vee x 0.7
-
Vee+ 0.3
V
Vee+ 0.3
V
O.B
V
5
10
mA
Cin
-
2
5
mA
-
2
10
p.A
-
2
10
p.A
-
-
1
p.A
-
-
1
p.A
-
-
12
pF
=0.5-
Vee - 0.5V
= 1MHz,
Vin =OV
f
=0.8 V
nThe value at f - xMHz can be calculated by the following equation:
... At standby mode
574
max
-0.3
VIL
All Inputs
Standby
Input
leakage
current
typ
2.0
Operating
Current *
dissipation
min
ICC (f = xMHz) .. IcC (f '" lMHz) multiplied by x
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - H D6305XO,H D63A05XO,H D63B05XO
• AC Characteristics (Vee
Item
=5.0V ± 10%, Vss =GND and T. =0 typ
max
min
typ
min
typ
0.4
-
8
MHz
fel
0.4
-
4
0.4
-
6
Cycle time
-
10
0.666
-
10
t
c2c
+ 00
-
+ 00
t~c
teye
1.0
INT pulse
width
tlwL
te~e
+2 0
-
-
INT2 pulse
width
tlWL2
teyc
+250
-
-
RES pulse
width
tRWL
5
-
-
TIMER pulse
width
tTWL
tcyc
+250
-
-
Oscillation
start time
(crystal)
tose
-
-
20
Reset delay
time
tRHL
80
-
-
CL
=22pF ±
Rs
= 60n
20%
Unit
max
Clock
frequency
max
0.5
-
10
Ils
-
tcyc
+200
-
-
ns
-
-
tcyc
+200
-
-
ns
5
-
-
5
-
-
tcye
tcyc
+200
-
-
tcyc
+200
-
-
ns
-
-
20
-
-
20
ms
80
-
-
80
-
-
ms
max
External cap.
2.21lF
• Port Electrical Characteristics (Vee
=5.0V ± 10%, Vss =GND and Ta =0 -
Item
Output volt·
age "High"
typ
min
max
2.4
-
-
V
IOH = -1 01lA
Vee - 0.7
-
-
V
IOL = 1.6mA
-
-
VIH
2.0
-
Vee + 0.3
V
V IL
-0.3
-
0.8
V
-1
-
1
IlA
VOL
Ports A,
B,C, D,
G
Input leak·
age current
Unit
10 H = - 2OOIlA
VO H
Input volt·
age "High"
Input volt·
age "Low"
+70°C unless otherwise specified)
Test
condition
Symbol
Ports A,
B,C,G,
E,F
Output volt·
age "Low"
•
min
HD63B05XO
HD63A05XO
HD6305XO
Test
condition
Symbol
+70°C unless otherwise specified)
Yin = 0.5-
III
Vee - 0.5V
0.55
V
SCI Timing (Vee = 5.0V±10"IO, Vss = OV and Ta = 0 - +70°C unless otherwise specified)
Item
Symbol
Clock Cycle
tScyc
Data Output Delay Time
tTxD
Data Set·up Time
tSRX
Data Hold Time
tHRX
Test
Condition
Fig. 1
Fig. 2
HD6305XO
min
typ
1
200
-
100
-
-
max
HD63A05XO
typ
max
min
HD63B05XO
min
typ
max
Unit
-
21845
0.5
-
16384
IlS
250
-
-
250
-
250
ns
-
200
-
-
200
-
-
ns
-
100
-
-
100
-
-
ns
32768 0.67
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
575
H D6305XO, H D63A05XO, H D63B05XO
-XTAL, EXTAL
These terminals provide input to the on-chip clock circuit.
A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic
fllter is connected to the terminal. Refer to "INTERNAL
OSCILLATOR" for using these input terminals.
Clock Output
C,!CK
Data Output
C,!TX
-TIMER
This is an input terminal for event counter. Refer to
"TIMER" for details.
Dat8 Input
C./AX
-RES
Used to reset the MCU. Refer to "RESET" for details.
Figure 1 SCI Timing (Internal Clock)
.NUM
This terminal is not intended for user applications. It should
be grounded to Vss.
Clock Input
C./CK
• Input/Output Terminals (Ao '" A7, Bo - B7, Co '" C7 , Go -
G·d
Data Output
These 32 terminals consist of four 8-bit I/O ports (A, B, C,
G). Each of them can be used as an input or output terminal
on a bit through program control of the data direction register.
For details, refer to "I/O PORTS".
C,'TX
tSRX
Data Input
CelAX
2.0V
______JrO~.8~V__________~~·~--~~
• Input Terminals (01 '" 07)
These seven input-only terminals are TTL or CMOS compatible. Of the port D's, D6 is also used as INTl. 1£ D6 is
used as a port, the INT2 interrupt mask bit of the miscellaneous register must be set to "1" to prevent an INT2 interrupt
from being aCCidentally accepted.
Figure 2 SCI Timing (External Clock)
Vee
TTL Load
(Port)
Test point
terminal
IOL= 1.6mA
2.4kQ
• Output Terminals (Eo'" E7, Fo '" F7)
These 16 output-only terminals are TTL or CMOS compatible.
......---~-_.
o-----~....----
12kQ
40pF
.STBY
This terminal is used to place the MCU into the standby
mode. With STBY at "Low" level, the oscillation stops and
the internal condition is reset. For details, refer to "Standby
Mode".
[NOTES 1 1. The load capacitance includes stray capacitance causad
by the probe, etc.
2. All diodes ar.e 152074
®.
Figure 3 Test Load
The terminals described in the following are I/O pins for
serial communication interface (SCI). The)' are also used as
ports Cs , C6 and C7 • For details, refer to "SERIAL COMMUNICATION INTERFACE."
.CK (Cs)
Used to input or output clocks for serial operation .
• Tx (C7)
• DESCRIPTION OF TERMINAL FUNCTIONS
The input and output signals of the HD6305XO are described
here.
Used to transmit serial data.
.Rx
eVee, Vss
(C6)
Used to receive serial data.
Voltage is applied to MCU through these two terminals.
Vee is 5.0V ± 10%, while Vss is grounded.
-INT, INT2
External interrupt request inputs to MCU. For details, refer
to "INTERRUPTS". The 1Nf2 terminal is also used as the
port D6 terminal.
576
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - H D6305XO, HD63A05XO,HD63B05XO
-REGISTERS
-MEMORY MAP
There are five registers which the programmer can operate.
The memory map of the HD6305XO MCU is shown in
Fig. 4. During interrupt processing, the contents of the CPU
registers are saved into the stack in the sequence shown in
Fig. 5. This saving begins with the lower byte (PCL) of the
program counter. Then the value of the stack pointer is
decremented and the higher byte (pC H) of the program
counter, index register (X), accumulator (A) and condition
code register (CC) are stacked in that order. In a subroutine
call, only the contents of the program counter (pCH and PCL)
are stacked.
7
127
128
255
256
$007F
RAM
(128Bytes)
Stack
~OO80
$QOFF
$0100
\
Not Used
4095
4096
8182
8191
8192
PORT A
0
1 PORT B
2
PORT C
3
PORT D
4 PORT A DDR
5 PORT B DDR
6 PORT C DDR
7 PORT G DDR
8 Timer Data Reg
9 Timer CTRL Reg
10 Mlsc Reg
11
PORT E
12 PORT F
13 PORT G
$0000
I/O Ports
Timer
SCI
ROM
(4,096Bytes)
-------_ ....
Interrupt
Vectors
$OFFF
S1000
0
PC
I
6 5
0
r--"T""-r--,-T"'""-'
"""""""""r-'-..,..-I-r"-T...J
Condition
Code
Re g iste r
~g~~~~
Zero
L----Negative
L-..----Interrupt
Mask
' - - - - - - - - - Half
Carry
sor
Figure 6 Programming Model
• Accumulator (A)
This accumulator is an ordinary 8-bit register which holds
operands or the result of arithmetic operation or data processing.
• Index Register (X)
Not Used
Not Used
127
16383
I
Program
....J.Counter
L.._ _ _ _ _ _ _ _ _ _ _ _ _ _
$08
$09
$OA
SOB
SOC
SOD
Not Used
S1 FFF
$2000
I
Index
--JReglster
L.._ _ _ _ _ _ _ _
$00
$01
$02
S03-$04"
S05$06-
16 SCI CTRL Reg $10
17 SCI STS Reg $11
18 SCI Data Reg $12
$1FF6
X
I
13
13
o
0
L..I____
A_ _ _----'I Accumulator
7
0
$3FFF
$7F
*
Write only regis ter
** Read only regis ter
Figure 4 Memory Map of HD6305XO MCU
The index register is an 8-bit register, and is used for index
addressing mode. Each of the addresses contained in the
register consists of 8 bits which, combined with an offset
value, provides an effective address.
In the case of a read/modify/write instruction, the index
register can be used like an accumulator to hold operation
data or the result of operation.
If not used in the index addressing mode, the register can
be used to store data temporarily.
• Program Counter (PC)
The program counter is a 14-bit register that contains the
address of the next instruction to be executed.
7 6 543 2 1 0
Condition
n-4 1 1 1
n+1
Code Register
I
n-3
Accumulator
n+2
n-2
Index Register
n+3
n-1
n
0 01
PCW
PCl-
Pull
• Stack Pointer (SP)
The stack pointer is a 14-bit register that indicates the address of the next stacking space. Just after reset, the stack
pointer is set at address $OOFF. It is decremented when data
is pushed, and incremented when pulled. The upper 8 bits
of the stack pointer are fixed to 00000011. During the MCU
being reset or during a reset stack pointer (RSP) instruction,
the pointer is set to address $OOFF. Since a subroutine or
interrupt can use space up to address $OOCI for stacking, the
subroutine can be used up to 31 levels and the interrupt up
to 12 levels.
n+4
n+5
Push
* In a subroutine call, only pel and PCH are stacked.
Figure 5 Sequence of Interrupt Stacking
• Condition Code Register (CC)
The condition code register is a 5 ·bit register. each bit
indicating the result of the instruction just executed. The
bits can be individually tested hy conditional branch instruc-
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
577
HD6305XO,HD63A05XO,HD63B05XO
tions. The CC bits are as follows:
Half Carry (H): Used to indicate that a carry occurred between bits 3 and 4 during an arithmetic operation (ADD, ADC).
Interrupt (I): Setting this bit causes all interrupts, except
a software interrupt, to be masked. If an
interrupt occurs with the bit I set, it is
latched. It will be processed the instant
the interrupt mask bit is reset. (More specifically, it will enter the interrupt processing
routine after the instruction following the
CLI has been executed.)
Negative (N): Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is negative (bit 7 is logic
"1 ").
Zero (Z):
Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is zero.
Carry/
Represents a carry or borrow th3t occurred
Borrow (C): in the most recent arithmetic operation. This
bit is also affected by the Bit Test and Branch
instruction and a Rotate instruction.
-INTERRUPT
There~e
six different types of interrupt: external interrupts (lNT,. IN.Tz), internal timer interrupts (TIMER,
TIMERz), senal mterrupt (S.CI) and interrupt by an instruction (SWI).
Of these six interrupts, the INTz and TIMER or the SCI
and TIMER2 generate the same vector address, respectively.
When an interrupt occurs, the program in progress stops
and the then CPU status is saved onto the stack. And then,
the interrupt mask bit (I) of the condition code register is
set and the start address of the interrupt processing routine
is obtained from a particular interrupt vector address. Then
the interrupt routine starts from the start address. System
can exit from the interrupt routine by an RTI instruction.
When this instruction is executed, the CPU status before
the interrupt (saved onto the stack) is pulled and the CPU
restarts the sequence with the instruction next to the one at
which the interrupt occurred. Table 1 lists the priority of
interrupts and their vector addresses.
Table 1
Interrupt
Priority of Interrupts
Priority
RES
1
SWI
INT
Vector Address
$1FFE,
$1FFF
2
$1FFC,
$lFFD
3
$lFFA,
$lFFB
TIMER/INT2
4
$lFFS,
$lFF9
SCI/TIMER2
5
$lFF6,
$lFF7
A flowchart of the interrupt sequence is shown in Fig. 7.
A block diagram of the interrupt request source is shown in
Fig. 8.
r-------,
JNr
y
!NT;"
y
1--1
$FF--SP
O--DDR'S
CLR INT Logic
SFF--TDR
$7F--Timer Prescaler
$SO--TCR
$3F--SSR
$OO--SCR
$7F ...... MR
TIMER
Y
Figure 7
578
y
SCI
Interrupt Flowchart
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - H D6305XO, H D63A05XO, H D63B05XO
In the block diagram, both the external interrupts INT and
are edge trigger inputs. At the falling edge of each input,
an interrupt request is generated and latched. The INT interrupt request is automatically cleared if jumping is made to
the INT processing routine. Meanwhile, the INT2 request is
cleareu . ~ "0" is written in bit 7 of the miscellaneous register.
For the external interrupts {lNT, INT2), internal timer
interrupts (TIMER, TIMER2) and serial interrupt (SCI), each
interrupt request is held, but not processed, if the I bit of the
condition code register is set. Immediately after the I bit is
cleared, the corresponding interrupt processing starts according to th!.£!!ority.
The INT2 interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by setting bit 6
of the timer control register; the SCI interrupt by setting bit
5 of the serial status register; and the TIMER2 interrupt by
setting bit 4 of the serial status register.
The status of the INT terminal can be tested by a BIL or
BIH instruction. The INT falling edge detector circuit and
its latching circuit are independent of testing by these instructions. This is also true with the status of the INT2 terminal.
iNT2
• Miscellaneous Register (MR; $OOOA)
The interrupt vector address for the external interrupt
INT2 is the same as that for the TIMER interrupt, as shown
in Table 1. For this reason, a special register called the miscellaneous register (MR; $OOOA) is available to control the
iNTi interrupts.
Bit 7 of this register is the INT2 interrupt request flag.
When the falling edge is detected at the INT2 terminal, "1"
is set in bit 7. Then the software in the interrupt routine
(vector addresses: $IFF8, $lFF9) checks bit 7 to see if it
is INT2 interrupt. Bit 7 can be reset by software.
Miscellaneous Register (MR;$OOOA)
76543210
IMR7IMR61Z1Z1Z1Z1Z1Zl
f
r
INT2
L-.._ _ _ _ _ _ _ _ _ _ _
Interrupt Mask
INT2 Interrupt Request Flag
Miscellaneous Register (MR; $OOOA)
Bit 6 is the INT2 interrupt mask bit. If this bit is set to "1",
then the INT2 interrupt is disabled. Both read and write are
possible with bit 7 but "1" cannot be written in this bit by
software. This means that an interrupt request by software
is impossible .
When reset, bit 7 is cleared to "0" and bit 6 is set to "1".
-TIMER
Figure 9 shows an MCU timer block diagram. The timer
data register is loaded by software and, upon receipt of a
clock input, begins to count down. When the timer data
Vectoring generated
$1FFA.$1FFB
BIH/Bll Test
Condition Code Register (CC)
iNf Interrupt latch
,
INT
Falling Edge Detector
l
}-_~I-----
Vectoring generated
$1 FF8. $1 FF9
TIMER
Serial Status
Register (SSR)
SCI/TIMER2
......- - -
>--~
Figure 8
Vectoring generated
$1FF6.$lFF7
Interrupt Request Generation Circuitry
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
579
HD6305XO,HD63A05XO,HD63B05XO - - - - - - - - - - - - - - - - - - - - - register (TDR) becomes "0", the timer interrupt request
bit (bit 7) in the timer control register is set. In response to
the interrupt request, the MCU saves its status into the stack
and fetches timer interrupt routine address from addresses
$IFF8 and $IFF9 and execute the interrupt routine. The
timer interrupt can be masked by setting the timer interrupt
mask bit (bit 6) in the timer control register. The mask bit
(I) in the condition code register can also mask the timer
interrupt.
The source clock to the timer can be either an external
signal from the timer input terminal or the internal E signal
(the oscillator clock divided by 4). If the E signal is used as
the source, the clock input can be gated by the input to the
timer input terminal.
Once the timer count has reached "0", it starts counting
down with "$FF". The count can be monitored whenever
desired by reading the timer data register. This permits the
program to know the length of time having passed after the
occurrence of a timer interrupt, without disturbing the contents of the counter.
When the MCU is reset, both the prescaler and counter are
initialized to logic "I". The timer interrupt request bit
(bit 7) then is cleared and the timer interrupt mask bit (bit
6) is set.
To clear the timer interrupt request bit (bit 7), it is necessary to write "0" in that bit.
• Timer Control Register (TCR; $0009)
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
Timer Control Register (TCR; $0009)
L-_ _ _ _ _ _ _ _ _ _ Timer interrupt mask
L - - - - - - - - - - - - - - T i m e r interrupt request
After reset, the TCR is initialized to "E under timer terminal control" (bit 5 = 0, bit 4 = I). If the timer terminal is
"I", the counter starts counting down with "$FF" immediately after reset.
When "1" is written in bit 3, the prescaler is initialized.
This bit always shows "0" when read.
Table 2
TCRl
Timer interrupt request
a
Absent
TCR
Clock input source
Bit 5
Bit 4
0
0
I nternal clock E
0
1
E under timer terminal control
1
0
No clock input (counting stopped)
1
1
Event input from timer terminal
Present
Timer interrupt mask
TCR6
Clock Source Selection
a
Disabled
Initialize
(Internal
Clock)
E --+---l
Timer Data
Register
L-_ _-.-_ _ _--,._ _- . J Timer Interrupt
Write
Read
Figure 9 Timer Block Diagram
580
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - HD6305XO,HD63A05XO,HD63B05XO
A prescaler division ratio is selected by the combination of
three bits (bits 0, 1 and 2) of the timer control register (see
Table 3). There are eight different division ratios: -H, +2, +4,
+8, +16, +32, +64 and +128. After reset, the TCR is set to the
+1 mode.
A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "1". When a timer
interrupt occurs, "1" is set in the timer interrupt request bit.
This bit can be cleared by writing "0" in that bit.
-SERIAL COMMUNICATION INTERFACE (SCI)
Table 3
Prescaler Division Ratio Selection
TCR
Bit 2
Bit 1
Bit 0
Prescaler division ratio
0
0
0
+1
0
0
1
+2
0
1
0
+4
0
1
1
+8
1
0
0
+16
1
0
1
+32
1
1
0
+64
1
1
1
+128
This interface is used for serial transmission or reception
of 8-bit data. Sixteen transfer rates are available in the range
from 1 J-LS to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one eighth counter and
one prescaler. (See Fig. 10.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 5,
6 and 7 of port C. Described below. are the operations of
each register and data transfer.
eSCI Control Register (SCR; $001 0)
SCI Control Registers (SCR; 0010)
E
Transfer
Clock
Generator
L-__....L.---...--l
,- __li __,
C5(CK) :
I
I
I
I
I
I
Initialize
I
----.l
C6(Rx)
I
C7(Tx)
L------~~---==r~~~~~~~~~~~~;;~~~~~~~~~~--~
SCI Status Registers
(SSR :$0011 )
Not Used
SCI TIMER2
Figure 10 SCI Block Diagram
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
581
HD6305XO,HD63A05XO,HD63B05XO
Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completion of transmitting or receiving 8-bit data. It is
cleared when reset or data is written to or read from the
SCI data register with the SCRS=" 1". The bit can also be
cleared by writing "0" in it.
C7 terminal
SCR7
o
Used as I/O terminal (by DDR).
Serial data output (DDR output)
Bit 6 (SSR6)
Bit 6 is the TIMER2 interrupt request bit. TIMER2 is used
commonly with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When reset, the
bit is cleared. It also be cleared by writing "0" in it. (For
details, see TIMER2.)
C6 terminal
SCRS
o
Used as I/O terminal (by DDR).
Serial data input (DDR input)
SCR5 SCR4
Clock source
Cs terminal
0
0
-
0
1
-
1
0
Internal
Clock output (DDR output)
1
1
External
Clock input (DDR input)
Bit 5 (SSRS)
Bit 5 is the SCI interrupt mask bit which can be set or
cleared by software. When it is "1", the SCI interrupt (SSR7)
is masked. When reset, it is set to "1".
Used as I/O terminal (by
DDR).
Bit 4 (SSR4)
Bit 4 is the TIMER2 interrupt mask bit which can be set
or cleared by software. When the bit is "1", the TIMER2
interrupt (SSR6) is masked. When reset, it is set to "1".
Bit 7 (SCR7)
When this bit is set, the DDR <:orresponding to the C7
becomes "I" and this terminal serves for output of SCI data.
After reset, the bit is cleared to "0".
Bit 6 (SCR6)
When this bit is set, the DDR corresponding to the C6
becomes "0" and this terminal serves for input of SCI data.
After reset, the bit is cleared to "0".
Bits 5 and 4 (SCRS, SCR4)
These bits are used to select a clock source. After reset,
the bits are cleared to "0".
Bits 3 - 0 (SCR3 - SCRO)
These bits are used to select a transfer clock rate. Mter
reset, the bits are cleared to "0".
SCR3
0
SCR2
0
SCRl
0
SCRO
0
Bit 3 (SSR3)
When "1" is written in this bit, the prescaler of the transfer
clock generator is initialized. When read, the bit always is "0".
Bits 2 - 0
Not used.
SSR7
o
Absent
Present
SSR6
TIMER2 interrupt request
o
Absent
Present
Transfer clock rate
4.00 MHz
4.194 MHz
SSR5
0.95J.1s
o
1 J.ls
0
0
0
1
2p.s
1.91p.s
0
1
0
4p.s
3.82p.s
0
0
1
1
8p.s
7.64p.s
SSR4
l
I
l
I
l
l
o
1
1
1
1
32768p.s
1/32 s
76543210
Enabled
TIMER2 interrupt mask
Enabled
Disabled
eSCI Data Register (SOR; $0012)
A serial·parallel conversion register that is used for transfer
of data.
eSCI Status Register (SSR; $0011)
SCI interrupt mask
Disabled
0
582
SCI interrupt request
• Data Transmission
By writing the desired control bits into the SCI control
registers, a transfer rate and a source of transfer clock are
determined and bits 7 and 5 of port C are set at the serial
data output terminal and the serial clock terminal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data
written in the SCI data register is output from the C7 fTx
terminal, starting with the LSB, synchronously with the
falling edge of the serial clock. (See Fig.11.) When 8 bits of
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - HD6305XO,HD63A05XO,HD63B05XO
data have been transmitted, the interrupt request bit is set in
bit 7 of the SCI status register with the rising edge of the
last serial clock. This request can be masked by setting bit
5 of the SCI status register. Once the data has been sent, the
8th bit data (MSB) stays at the C7/Tx terminal. If an external
clock source has been selected, the transfer rate determined by
bits 0 - 3 of the SCI control register is ignored, and the Cs /
CK terminal is set as input. If the internal clock has been
selected, the Cs /CK terminal is set as output and clocks are
output at the transfer rate selected by bits 0 - 3 of the SCI
<;ontrol register.
Figure 11
SCI Timing Chart
• Data Reception
By writing the desired control bits into the SCI control
register, a transfer rate and a source of transfer clock are determined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock terminal, respectively.
Then dummy-writing or -reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed after reading subseqent received data. It must be taken
after reset and after not reading subsequent received data.)
The data from the C6 /Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig.II). When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bit 5
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0 - 3 of the SCI
control register is ignored and the data is received synchronously with the clock from the Cs /CK terminal. If the internal
clock has been selected, the Cs/CK terminal is set as output
and clocks are output at the transfer rate selected by bits 0 3 of the SCI control register.
TIMERz is commonly used with the SCI transfer clock
generator. If wanting to use TIMERz independently of the
SCI, specify "External" (SCRS = I, SCR4 = I) as the SCI
clock source.
If "Internal" is selected as the clock source, reading or
writing the SDR causes the prescaler of the transfer clock
generator to be initialized.
-I/O PORTS
There are 32 input/output terminals (ports A, B, C, G).
Each I/O terminal can be selected for either input or output
by the data direction register. More specifically, an I/O port
will be input if "0" is written in the data direction register,
and output if "I" is written in the data direction register.
Port A, B or C reads latched data if it has been programmed
as output, even with the output level being fluctuated by the
output load. (See Fig. 12-a.) For port G, in such a case, the
level of the pin is always read when it is read. (See Fig. 12-b.)
This implies that, even when "I" is being output, port G may
read "0" if the load condition causes the output voltage to
decrease to below 2 .OV .
When reset, the data direction register and data register go
to "0" and all the input/output terminals are used as input.
.TIMERz
The SCI transfer clock generator can be used as a timer.
The clock selected by bits 3 - 0 of the SCI control register
(4 p.s - approx. 32 ms (for oscillation at 4 MHz)) is input to
bit 6 of the SCI status register and the TIMERz interrupt
request bit is set at each falling edge of the clock. Since interrupt requests occur periodically, TIMERz can be used as a
reload counter or clock.
Bit of data
direction
register
Bit of
output
data
Status of
output
Input to
CPU
1
0
0
0
1
1
1
1
0
X
3-state
Pin
a. Ports A, Band C
---~l
'-----'
CD
: Transfer
clock generator is reset and mask bit (bit 4
of SCI status register) is clea red.
b. Port G
®. (fl : TIMERz interrupt request
@.® :TIMERz interrupt request bit cleared
Figure 12
Input/Output Port Diagram
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
583
H D6305XO, H D63A05XO,H D63B05XO - - - - - - - - - - - - - - - - - - - - - There are 16 output-only terminals (ports E and F). Each
of them can also read. In this case, latched data is read even
with the output terminal level being fluctuated by the output
load (as with ports A, B and C).
When reset, "Low" level is output from each output terminal.
Seven input-only terminals are available (port D). Writing
to an input terminal is invalid.
All input/output terminals, output terminals and input
terminals are TTL compatible and CMOS compatible in respect of both input and output.
If I/O ports or input ports are not used, they should be
connected to VSS via resistors. With none connected to these
terminals, there is the possibility of power being consumed
despite that they are not used.
1-----41.....---1
JO-~iOM><>=
EXTAL
XTAL
HD6305XO
MCU
10-22pF±20%
Crystal Oscillator
HD6305XO
MCU
-RESET
The MCU can be reset either by external reset input (RES)
or power-on reset. (See Fig. 13.) On power up, the reset
input must be held "Low" for at least tose to assure that the
internal oscillator is stabilized. A sufficient time of delay can
be obtained by connecting a capacitance to the RES input as
shown in Fig. 14.
External_---C-e-ra-m-i-c-O-s-c-ill-a-to...r
Clock
Input
EXTAL
NC
XTAL HD6305XO
MCU
5V
Vcc
OV
External Clock Drive
RES
Terminal
/1-<'"" -
./
---------r"
-
~::;al
VIH RES
Figure 15
Cl
_ _ _ _ _ _ _ _ _ _~
Figure 13
Internal Oscillator Circuit
tRHLf--
~~
XTAL~~EXTAL
Power On and Reset Timing
AT Cut
Parallel
Resonance
Co=7pF max.
f=2.0-S.0MHz
Rs=600 max.
Figure 16 Parameters of Crystal
100k!l typ
Vcc:--~vv--4---~
-:;r;2.2.II F
HD6305XO
MCU
Figure 14
Input Reset Delay Circuit
-INTERNAL OSCILLATOR
The internal oscillator circuit is designed to meet the
requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 - 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the required oscillation frequency stability.
Three different terminal connections are shown in Fig. 15.
Figs. 16 and 17 illustrate the specifications and typical arrangement of the crystal, respectively.
584
[NOTE) Use as short wirings as possible for connection of the crystal
with the EXT AL and XTAL terminals. Do not allow these
wirings to cross others.
Figure 17 Typical Crystal Arrangement
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - H D6305XO, HD63A05XO,H D63B05XO
-LOW POWER DISSIPATION MODE
The HD6305XO has three low power dissipation modes:
wait, stop and standby.
.Wait Mode
When WAIT instruction being executed, tht: MCU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication interface - stay active. (NOTE: Once the system has entered the
wait mode, the serial communication interface can no longer
be retriggered.) In the wait mode, the registers, RAM and I/O
termmals hold their condition just before entering into the
wait mode.
The escape from this mode can be done by interrupt (INT,
TIMER/INT2 or SCI/TIMER2), RES or STBY. The RES
resets the MCU and the STBY brings it into the standby
mode. (This will be mentioned later.)
When interrupt is requested to the CPU and accepted, the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit of the condition code register, after releasing from the wait mode the MCU executes the instruction
next to the WAIT. If an interrupt other than the INT (Le.,
TIMER/INT2 or SCI/TIMER2) is masked by the timer control
register, miscellaneous register or serial status register, there
is no interrupt request to the CPU, so the wait mode cannot
be released.
Fig. 18 shows a flowchart for the wait function.
• Stop Mode
When STOP instruction being executed, MCU enters into
the stop mode. In this mode, the oscillator stops and the CPU
and peripheral functions become inactive but the RAM,
registers and I/O terminals hold their condition just before
entering into the stop mode.
The escape from this mode can be done by an external
interrupt (INT or INT2), RES or STBY. The RES resets the
MCU and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted,
the stop mode escapes, then the CPU is brought to the operation mode and vectors to the interrupt routine. If the interrupt is masked by the I bit of the condition code register,
after releasing from the stop mode, the MCU executes the
instruction next to the STOP. If the INT2 interrupt is masked
by the miscellaneous register, there is no interrupt request to
the MCU, so the stop mode cannot be released.
Fig. 19 shows a flowchart for the stop function. Fig. 20
shows a timing chart of return to the operation mode from
the stop mode.
For releasing from the stop mode by an interrupt, oscillation starts upon input of the interrupt and, after the internal
delay time for stabilized oscillation, the CPU becomes active.
For restarting by RES, oscillation starts when the RES goes
"0" and the CPU restarts when the RES goes "1". The duration of RES="O" must exceed tose to assure stabilized oscillation.
• Standby Mode
The MCU enters into the standby mode when the STBY
terminal goes "Low". In this mode, all operations stop and
the internal condition is reset but the contents of the RAM are
hold. The I/O terminals turn to high-impedance state. The
standby mode should escape by bringing STBY "High". The
CPU must be restarted by reset. The timing of input signals
at the RES and STBY terminals is shown in Fig. 21 .
Table 4 lists the status of each parts of the MCU in each
low power dissipation modes. Transitions between each mode
are shown in Fig. 22.
(Note)
When I bit of condition code register is "1" and interrupt
(INT, TIMER/INT 2, SCI/TIMER2 ) is held, MCU does not
enter WAIT mode by the execution of WAIT instruction.
In that case, after the 4 dummy cycles MCU executes the
next instruction.
In the same way, when external interrupts (INT, INT 2) are
held at the bit I set, MCU does not enter STOP mode by the
execution of STOP instruction. In that case, also, MCU executes
the next instruction after the 4 dummy cycles.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
585
H06305XO,H 063A05XO,H063B05XO - - - - - - - - - - - - - - - - - - - - - -
Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop
Initialize
CPU, TIMER, SCI,
1/0 and All
Other Functions
No
No
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 18
586
Wait Mode Flowchart
¢Z)HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - H D6305XO, H D63A05XO, H D63B05XO
Oscillator and
All Clocks Stop.
No
Turn on Oscillator
Wait for Time Delay
to Stabilize
Turn on Oscillator
Wait for Time Delay
to Stabilize
1=0
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 19
Stop Mode Flowchart
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
587
H D6305XO,HD63A05XO,H D63B05XO - - - - - - - - - - - - - - - - - - - - - -
om":~'~:~~~\~~~~
!
Time required for oscillation to become
stabilized (built·in delay time)
Interrupt
STOP instruction
executed
restart
(a) Restart by Interrupt
Oscillator II1111111111111111111111111 II
~r-----+-------'
Time required for oscillation to become
STOP instruction
executed
stabilized (tos e)
RES
(b) Restart by Reset
Figure 20
Timing Chart of Releasing from Stop Mode
\L--------Ill}-RES
_----'I
i
,
I
I
,
,
L_~
,
I
__~ __ ~~~~~~~~~~~~~~~~~~-J
tosc
Figure 21
Table 4
Restart
Timing Chart of Releasing from Standby Mode
Status of Each Part of MCU in Low Power Dissipation Modes
Condition
Mode
Start
WAIT
Soft·
ware
STOP
Stand·
by
588
Hard·
ware
1/0
Escape
Oscil·
lator
CPU
Timer,
Serial
Register
RAM
WAIT in·
struction
Active
Stop
Active
Keep
Keep
Keep
STBY, RES, INT, INT 2 ,
each interrupt request of
TIMER, TIMER 2 , SCI
STOP in·
struction
Stop
Stop
Stop
Keep
Keep
Keep
STBY, RES, INT, INT2
STBY="Low"
Stop
Stop
Stop
Reset
Keep
High im·
pedance
terminal
STBY="High"
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - HD6305XO,H D63A05XO,HD63B05XO
Figure 22 Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset
-BIT MANIPULATION
The HD6305XO MCU can use a single instruction (BSET
or BCLR) to set or clear one bit of the RAM or an I/O port
(except the write-only registers such as the data direction
register). Every bit of memory or I/O within page 0 ($00 $FF) can be tested by the BRSET or BRCLR instruction;
depending on the result of the test, the program can branch to
required destinations. Since bits in the RAM, or I/O can be
manipulated, the user may use a bit within the RAM as a flag
or handle a single I/O bit as an independent I/O terminal.
Fig. 23 shows an example of bit manipulation and the validity
of test instructions. In the example, the program is configured
assuming that bit 0 of port A is connected to a zero cross
detector circuit and bit 1 of the same port to the trigger of a
triac.
The program shown can activate the triac within a time of
IOj1.s from zero-crossing through the use of only 7 bytes on
the ROM. The on-chip timer provides a required time of
delay and pulse width modulation of power is also possible.
the program.
This access requires an instruction length of 2 bytes. The
effective address (EA) is PC and the operand is fetched from
the byte that follows the operation code.
• Direct
See Fig. 25. In the direct addressing mode, the address of
the operand is contained in the 2nd byte of the instruction.
The user can gain direct access to memory up to the lower
255th address. All RAM and I/O registers are on page 0 of address space so that the direct addressing mode may be utilized.
• Extended
See Fig. 26. The extended addressing is used for referencing to all addresses of memory. The EA is the contents of
the 2 bytes that follow the operation code. An extended
addressing instruction requires a length of 3 bytes.
• Relative
SELF 1.
See Fig. 27. The relative addressing mode is used with
branch instructions only. When a branch occurs, the program
counter is loaded with the contents of the byte following the
operation code. EA = (PC) + 2 + ReI., where ReI. indicates a
signed 8-bit data following the operation code. If no branch
occurs, ReI. = O. When a branch occurs, the program jumps
to any byte in the range + 129 to -127. A branch instruction
requires a length of 2 bytes.
BRClR 0, PORT A, SELF 1
BSET 1, PORT A
BClR 1, PORT A
Figure 23 Example of Bit Manipulation
-ADDRESSING MODES
Ten different addressing modes are available to the
HD6305XO MCU.
• Indexed (No Offset)
• Immediate
See Fig. 24. The immediate addressing mode provides
access to a constant which does not vary during execution of
See Fig. 28. The indexed addressing mode allows access
up to the lower 255th address of memory. In this mode, an
instruction requires a length of onc bytc. The EA is the
contents of the index register.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
589
H D6305XO,H D63A05XO,HD63B05XO - - - - - - - - - - - - - - - - - - - - - elndexed (8·bit Offset)
See Fig. 29. The EA is the contents of the byte follow·
ing the operation code, plus the contents of the index register.
This mode allows access up to the lower 511 th address of
memory. Each instruction when used in the index addressing
mode (8·bit offset) requires a length of 2 bytes.
elndexed (16·bit Offset)
See Fig. 30. The contents of the 2 bytes following the
operation code are added to content of the index register
to compute the value of EA. In this mode, the complete
memory can be accessed. When used in the indexed address·
ing mode (16·bit offset), an instruction must be 3 bytes long.
e Bit Set/Clear
See Fig. 31. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
O. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte that follows the operation code
indicates an address within page O.
e Bit Test and Branch
See Fig. 32. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. Individual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relative value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code register.
elmplied
See Fig. 33. This mode involves no EA. All information
needed for execution of an instruction is contained in the
operation code. Direct manipulation on the accumulator
and index register is included in the implied addressing mode.
Other instructions such as SWI and RTI are also used in this
mode. All instructions used in the implied addressing mode
should have a length of one byte.
~-=~____~A~~
I
Memory
I
FB
Index Reg
I
Stack Point
PROG LOA:: $FB
05BE~~~~f---------.J
Prog Count
05CO
CC
05BF
~
I
I
I
Figure 24
Example of Immediate Addressing
Memory
A
CATFCB32004B~~c:~~--1_---~~-----1~~20~;J
Index Reg
Stack Point
PROG LOA CAT 0520 ~""':;:;::""---1
Prog Count
052F
CC
052E t---';;'----1
Figure 25
590
Example of Direct Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H 0 6305XO, H 0 63A05XO, H D63B05XO
Memory
~
A
:
:
40
Index Reg
PROG LDA CAT ~:~!t-~~--"L
I
040Bt---=.:.....~1
Stack Point
CAT FCB 64 06E5t::32:::}---------------J
Figure 26
Prog Count
040C
CC
Example of Extended Addressing
PROG BEQ PROG2 04A7
04A81-~~-I
Figure 27
Example of Relative Addressing
Memory
A
TA8LFCC LI
00B8t:~~::j---~~~-------r----------i:~4~C~~
B8
Stack Point
Prog Count
05F5
CC
Figure 28
Example of Indexed (No Offset) Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
591
H D6305XO,H D63A05XO,H D63B05XO - - - - - - - - - - - - - - - - - - - - - - -
Memory
TABL FCB :: BF
00B9t---.,.,BF,..---t
:~~ ~~~ gg~~t--....".,~:,.......--t
A
FCB ::CF OOBCt:1CtF=:l----f--J
Index Reg
CF
03
Stack Point
PROG LOA TABL.X 075B t=jE~6=:j_ _ _J
075C
B9
Prog Count
0750
CC
Figure 29
Example of Index (S-bit Offset) Addressing
~
.
A
D8
Index Reg
'
02
PROG LDA TABU g~~~t-~~-I
0694
Stack
oint
Prog Count
1--;;"'--1
0695
CC
:~~ :~ g~~~ ~::i~~==-i:t----------.J
TABL FCB
FCB
DB 07801CF 0781
t--"""';;''----I
Figure 30
PORT B EQU 1 0001
Example of Index (16-bit Offset) Addressing
t-"""';;''---f''l
A
Index Reg
PROG BCLR 6. PORT B 058F
0590
r-::~l~Dt:=l----...J
I-
I
Stack Point
01
Prog Count
0591
CC
Figure 31
592
Example of Bit Set/Clear Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H D6305XO,H D63A05XO, H D63B05XO
PORT C EQU 2 0002 I---';';~---I
PROG BRCLR 2.PORT CPROG 2 0574
05 751----;:~--I
0576
I--":'::"-'~
Figure 32
Example of Bit Test and Branch Addressing
Memory
Figure 33
Example of Implied Addressing
• Branch Instructions
-INSTRUCTION SET
There are 62 basic instructions available to the HD6305XO
MeU. They can be classified into five categories: register/
memory, read/modify/write, branch, bit manipulation, and
control. The details of each instruction are described in
Tables 5 through II.
• Register/Memory Instructions
Most of these instructions use two operands. One operand
is either an accumulator or index register. The other is derived
from memory using one of the addressing modes used on the
HD6305XO MeU. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump
instruction (JSR). See Table 5.
• Read/Modify/Write Instructions
These instructions read a memory or register, then modify
or test its contents, and write the modified value into the
memory or register. Zero test instruction (TST) does not
write data, and is handled as an exception in the read/modify/
write group. See Table 6.
A branch instruction branches from the program sequence
in progress if a particular condition is established. See Table 7.
• Bit Manipulation Instructions
These instructions can be used with any bit located up to
the lower 255th address of memory. Two groups are available;
one for setting or clearing and the other for bit testing and
branching. See Table 8.
• Control Instructions
The control instructions control the operation of the MeU
which is executing a program. See Table 9.
• list of Instructions in Alphabetical Order
Table 10 lists all -the instructions used on the HD6305XO
MeU in the alphabetical order.
• Operation Code Map
Table 11 shows the operation code map for the instructions
used on the MeU.
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
593
HD6305XO,HD63A05XO,HD63B05XO
Table 5
Register/Memory Instructions
Addressing Modes
Indexed
Indexed
Operations
Mnemonic
Immediate
Direct
OP Ii
- OP Ii
-
OP Ii
-
OP Ii
-
OP II
-
OP Ii
-
Load A from Memory
LOA
A6
2
2
3
C6 3
4
F6
1
3
E6
2
4
06 3
5
Load X from Memory
LOX
AE
2
2
BE
2
3
CE
3
4
FE
1
3
EE
2
4
DE 3
5
M~X
Store A in Memory
STA
-
-
-
B7
2
3 C7
3
4
F7
1
4
E7
2
4
07 3
5
A~M
Store X in Memory
STX
-
-
-
BF
2
3
CF
3
4
FF
1
4
EF
2
4
OF 3
5
X~M
Add Memory to A
ADD
AB
2
2
BB
2
3 CB 3
4
FB
1
3
EB
2
4
DB 3
5
A+M-.A
to A
ADC
A9
2
2
B9
2
3 C9
3
4
F9
1
3
E9
2
4
09 3
5
A+M+C--A
Subtract Memory
SUB
AO
2
2
BO
2
3 CO 3
4
FO
1
3
EO
2
4
DO 3
5
A-M~A
A with Borrow
SBC
A2
2
2
B2
2
3 C2
3
4
F2
1
3
E2
2
4
02 3
5
A-M-C~A
AND Memory to A
AND
A4
2
2
B4
2
3 C4 3
4
F4
1
3
E4
2
4
04 3
5
A·
OR Memory with A
ORA
AA 2
2
BA 2
3 CA 3
4
FA
1
3
EA
2
4 DA 3
5
A+M~A
EOR
AS
2
2
BS
2
3 C8
3
4
F8
1
3
E8
2
4
08 3
5
A(±>M~A
CMP
A1
2
2
B1
2
3 C1
3
4
Fl
1
3
El
2
4
01
3
5
A-M
CPX
A3
2
2
B3
2
3 C3
3
4
F3
1
3
E3
2
4
03 3
5
X-M
A5
2
2 B5 2
3 C5
A,M
-----
B6
2
Condition
Code
Booleanl
Arithmetic
Operation
Indexed
(No Offset) (S-Bit Offset) (IS-Bit Offset)
Extended
• •
•
• •
•
Subtract Memory from
M~A
Exclusive OR Memory
Arithmetic Compare A
with Memory
Arithmetic Compare X
with Memory
Bit Test Memory with
A (L09ical Compare)
BIT
3
4
F5
1
3
E5
2
4
05 3
5
Jump Unconditional
JMP
BC
2
2 CC 3
3
FC
1
2
EC
2
3 DC 3
4
Jump to Subroutine
JSR
BD 2
5 CD 3
6
FD
1
5 ED
2
5 DO 3
6
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
Table 6
N
Z
C
1\
1\
•
1\
(,
1\
1\
· ••
·· ·
• ·•
• •
• •
·•
• •
• ·
·
• •
·•
• •
•
• • • • •
··• • •
Add Memory and Carry
with A
I
H
M~A
1\
1\
1\
1\
t
(
1\
1\
I
1\
/\
I,
(,
1\
1\
1\
t,
1\
1\
1\
1\
t,
1\
1\
/\
1\
I
t,
1\
t
Read/Modify/Write Instructions
Addressing Modes
Indexed
Indexed
Operations
Mnemonic
Implied(A)
Implied(X)
Direct
Condition
Code
Booleanl Arithmetic Operation
(No Offset) IS-Bit Offset}
OP II
-
OP II
-
OP
II
-
OP II
-
OP II
-
Increment
INC
4C
1
2
5C
1
2
3C
2
5
7C
1
5
6C
2
6
A+ l-·A or X+ 1 ~X or M+ 1 ~M
Decrement
DEC
4A
1
2 5A
1
2 3A 2
5
7A
1
5 6A 2
6
A-I
H
~A
or
or X-I
OO·~X
~X
or
or M-l
Clear
CLR
4F
1
2
5F
1
2
3F
2
5
7F
1
5
6F
2
6
OO·~A
Complement
COM
43
1
2
53
1
2
33
2
5
73
1
5
63
2
6
"A.A or X~X or M~M
OO-A -A or
Negate
(2's Complement)
Rotate Left Thru Carry
NEG
ROL
40
49
1
1
2
2
50
59
1
1
2
2
30
2
39.2
5
5
70
79
1
1
5
5
60
69
2
2
~M
OO~M
or
6
L5t I I I I I I IbO~
ROR
46
1
2
56
1
2
36
2
5
76
1
5
66
2
6
Logical Shift Left
LSL
48
1
2
58
1
2
38
2
5
78
1
5
68
2
6
·
OO-M~M
AorX or
iii
• •
• •
lciH I I'+~O':MI
Ibo~ • •
c
D-l I ~OI:xr~ I I 1- • •
b,
C
• •
0-1 I IAHor:MI I 1-0
[(b'I H,H"'I I KJ • •
Equal to LSL
• •
b
'
c
b,
N
Z
/\
(\
1\
1\
C
•
•
•
0
1
1\
r
1
/\
1\
1\
"-
1\
.\
/\
/\
"-
/\
0
/\
t,
1\
r
1\
1\
1\
1\
1\
•
OO-X~X
6
Rotate Right Thru Carry
I
• •
•
• •
• •
(\
bo
0
1\
---bo
Logical Shift Right
LSR
44
1
2
54
1
2
34
2
5
74
1
5
64
2
6
Arithmetic Shift Right
ASR
47
1
2
57
1
2
37
2
5
77
1
5
67
2
6
ArithmetiC Shift Left
ASL
48
1
2
58
1
2
38
2
5
78
1
5
68
2
6
TST
40
1
2
50
1
2 3D
2
4
70
1
4
60 2
5
bo
C
Te.t for Negilive
or Zero
A-OO or X-OO or M-OO
• •
Symbols: Op - Operation
# - Number of bytes
- - Number of cycles
594
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H D6305XO, H D63A05XO, H D63B05XO
Table 7 Branch Instructions
Addressing Modes
Operations
Mnemonic
Relative
OP
:If
-
20
2
2
3
3
3
3
2
3
Branch Always
BRA
Branch Never
BRN
21
2
Branch IF Higher
BHI
22
2
Branch IF lower or Same
BlS
23
Branch IF Carry Clear
BCC
24
(Branch IF Higher or Same)
Condition Code
Branch Test
None
None
C+Z=O
C+Z=1
C=O
H
I
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(BHS)
24
2
3
C=O
BCS
25
2
3
C=1
(BlO)
25
2
3
C=1
Branch IF Not Equal
BNE
26
2
BEQ
27
2
Branch IF Half Carry Clear
BHCC
28
2
Branch IF Half Carry Set
BHCS
29
2
Branch IF Plus
BPl
2A
2
Branch IF Minus
BMI
2B
2
3
3
3
3
3
3
z=o
Branch IF Equal
BMC
2C
2
3
1=0
BMS
2D
2
3
1=1
Bil
2E
2
3
INT=O
•
•
•
Branch IF Carry Set
(Branch IF lower)
Z=1
H=O
H=1
N=O
N=1
Branch IF Interrupt Mask
Bit is Clear
Branch IF Interrupt Mask
Bit is Set
Branch IF Interrupt Line
is low
Branch IF Interrupt Line
is High
BIH
2F
2
3
INT=1
Branch to Subroutine
BSR
AD
2
5
--
•
•
•
•
•
•
•
•
•
•
N
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
• •
• •
• •
• •
• •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Symbols: Op : Operation
# : Number of bytes
- : Number of cycles
Table 8 Bit Manipulation Instructions
Operations
Addressing Modes
Boolean/
Branch
Bit Test and Branch Arithmetic
Bit Set/Clear
Test
OP
OP
# - Operation
#
-BRSET n(n =0··· 7)
3 5
Mn=1
2'n
BRClR n(n=0···7)
Mn=O
01 +2·n 3 5
BSET n(n=0···7)
10+2·n 2 5
1--Mn
BCLR n(n=0···7)
11 +2·n 2 5
O--Mn
Mnemonic
-
Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear Bit n
-
-
Condition Code
Z
C
• • • •
1\
H
I
N
• • • •
• • • • •
• • • • •
1\
Symbols: Op: Operation
# : Number of bytes
- : Number of cycles
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
595
H D6305XO, H D63A05XO, H D63B05XO
Table 9
Operations
Mnemonic
Transfer A to X
TAX
Control Instructions
Addressing Modes
Implied
#
-
97
1
X-+A
H
Transfer X to A
TXA
9F
1
2
2
Set Carry Bit
SEC
99
1
1
1-+C
Clear Carry Bit
Set Interrupt Mask Bit
CLC
98
9B
1
1
O-+C
SEI
1
1-+1
Clear Interrupt Mask Bit
CLI
9A
1
Software Interrupt
SWI
83
1
10
Return from Subroutine
RTS
81
1
5
Return from Interrupt
RTI
80
1
Reset Stack Pointer
No-Operation
RSP
9C
90
1
NOP
8
2
1
2
4
4
Decimal Adjust A
Stop
Wait
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
DAA
80
1
STOP
8E
1
WAIT
8F
1
I
N
Z
C
• • • • •
A-+X
2
2
1
Condition Code
Boolean Operation
OP
• • • •
• • • •
• •1 • •
• 0 • •
• 1 • •
•
• •
• • • •
? ? ? ?
• • • •
• • • •
• •
• • • •
• • • •
0-+1
$FF-+SP
Advance Prog. Cntr. Only
Converts binary add of BCD charcters into
BCD format
/\
/\
* Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.l
•1
0
•
•
•
•
?
•
•
•
•
/\*
Table 10 Instruction Set (in Alphabetical Order)
Addressing Modes
Condition Code
Bit
Mnemonic
Indexed
Implied
Indexed
Indexed
Set!
Test &
(8-Bit)
(16-Bit)
Clear
Branch
X
X
X
!\
X
X
X
X
!\
X
X
X
X
Immediate
Direct
ADC
X
X
X
ADD
X
X
AND
X
X
Extended Relative (No Offset)
ASl
X
X
X
X
ASR
X
X
X
X
BCC
X
BClR
X
BCS
X
BEQ
X
BHCC
X
BHCS
X
BHI
X
(BHS)
X
BIH
X
Bil
X
BIT
X
X
X
(BlO)
X
BlS
X
BMC
X
BMI
X
BMS
X
BNE
X
BPl
X
BRA
X
Condition Code Symbols:
H
Half Carry (From Bit 3)
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
596
X
Bit
X
X
H
I
•
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
N
Z
C
!\
!\
!\
!\
!\
!\
!\
!\
•
/,
!\
!\
!\
!\
!\
•
•
•
•
•
•
•
•
•
•
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
•
• •
• •
• •
• •
• •
• •
• •
• •
/\
•
•
•
•
•
•
•
!\
(to be continued)
C
!\
•?
Carry IBorrow
Test and Set if True, Cleared Otherwise
Not Affected
load CC Register From Stack
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H D6305XO,H D63A05XO, H D63B05XO
Table 10 Instruction Set (in Alphabetical Order)
Addressing Modes
Condition Code
Bit
Mnemonic
Implied
Immediate
Extended Relative
Direct
BRN
Bit
Indexed
Indexed
Indexed
Set!
Test &
(No Offset)
(S-Bit)
(16-Bit)
Clear
Branch
X
BRCLR
X
BRSET
X
BSET
X
BSR
X
CLC
X
CLI
X
CLR
X
COM
x
x
X
x
X
x
x
X
CPX
DAA
X
DEC
X
EOR
INC
x
x
x
x
CMP
x
X
JMP
JSR
x
x
LDA
LDX
LSL
LSR
NEG
NOP
x
x
x
x
x
ORA
ROL
ROR
RSP
RTI
RTS
x
x
x
x
x
x
SBC
SEC
X
SEI
x
STA
STOP
STX
TAX
TST
TXA
WAIT
X
X
x
x
X
X
X
X
X
X
X
X
x
x
x
X
X
X
x
x
x
X
X
x
x
X
X
x
x
X
X
x
x
X
X
X
X
X
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
X
X
X
x
x
x
x
x
SUB
SWI
x
x
x
x
x
x
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
x
!
C
f\
•?
H
I
N
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•0
•
•
•
•
•
•
•1
•
1\
1\
1\
1\
1
1\
1\
1\
1\
1\
1\
.,•
1\
1\
•
•
0
•
•
1\
•
•
•
• • • •
• • • •
•
•
•
•
• 0
•
•
• • • •
•
•
•
•
• • • •
? ? ? ?
• • • •
•
•1 • • 1
• • •
•
•
• • • •
•
•
•1
• • •
• • • •
•
•
• • • •
• • • •
1\
f\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
(\
1\
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
597
HD6305XO,HD63A05XO,HD63B05XO - - - - - - - - - - - - - - - - - - - - - Table 11
Bit Manipulatior\
Operation Code Map
Read/Modify/Write
Control
Test &
Set/
Branch
Clear
Rei
DIR
A
X
,Xl
,XO
IMP
0
1
2
3
4
5
6
7
8
0
BRSETO
BSETO
BRA
1
BRCLRO
BCLRO
BRN
-
2
BRSETl
BSETl
BHI
-
3
BRCLRl
BCLRl
BLS
COM
BRSET2
BSET2
BCC
LSR
5
BRCLR2
BCLR2
BCS
6
BRSET3
BSET3
BNE
Register/Memory
IMP IMM
9
RTI'
NEG
4
RTS'
-
SWI'
-
A
DIR
EXT
,X2
,Xl
,XO
B
C
D
E
F
+-H IGH
0
-
SUB
--
CMP
1
~
SBC
2
-
CPX
3
-
AND
4
-
-
BIT
5
ROR
--
-
LDA
6
5TA(+I) 7
-
7
BRCLR3
BCLR3
BEQ
ASR
-
TAX'
8
9
BRSET4
BSET4
BHCC
LSL/ASL
-
CLC
STA
EOR
BRCLR4
BCLR4
BHCS
ROL
-
SEC
ADC
8
9
A
BRSET5
BSET5
BPL
DEC
-
CLI*
ORA
A
B
BRCLR5
BCLR5
BMI
--
-
ADD
C
BRSET6
BSET6
BMC
INC
SEI*
RSP'
D
BRCLR6
BCLR6
BMS
E
BRSET7
BSET7
BIL
F
BRCLR7
BCLR7
BIH
3/5
2/5
2/3
(NOTES)
•
Branch
T5T(-I)
--
TST(-l)
TST
2/5
1/2
1/2
2/6
1/*
1/1
JSR(+l)
C
JSR(+2) D
LDX
2/2
2/3
STX
3/4 3/5
E
5TX(+1) F
2/4
1/3
1. "-" is an undefined operation code.
2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).
The number of cycles for the mnemonics asterisked (·1 is as follows:
ATI
8
TAX
2
ATS
5
ASP
2
SWI
10
TXA
2
DAA
2
BSA
5
STOP
4
eLi
2
WAIT
4
SEI
2
3. The parenthesized numbers must be added to the cycle count of the particular instruction.
WAIT Causes the MCV to enter the wait mode. For this mode,
Additionallnstructions
The following new instructions are used on the HD630SXO:
DAA Converts the contents of the accumulator into BCD
code.
598
1/5
JSR(+2)
-
WAIT" TXA'
CLR
B
JMP(-l)
--
DAA' NOP BSW
STOP'
-
--
L
o
W
see the topic, Wait Mode.
STOP Causes the MCV to enter the stop mode. For this mode,
see the topic, Stop Mode.
~HITACHI
Hitachi America Ltd. • 2210 OToole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6305X1 ,HD63A05X1 ,HD63B05X1
HD6305X2,HD63A05X2,HD63B05X2
CMOS MCU (Microcomputer Unit)
The HD6305XI and the HD6305X2 are memory expandable versions of the HD6305XO, which is CMOS 8-bit single chip
microcomputer. A CPU, a clock generator, a 128-byte RAM,
I/O terminals, two timers and a serial communication interface
(SCI) are built in both chip of the HD6305XI and the HD
6305X2. Their memory spaces are expandable to 16k bytes
externally.
The HD6305XI and the HD6305X2 have the same functions
as the HD6305XO's except for the number of I/O terminals.
The HD6305X I has a 4k byte ROM and its memory space is
expandable to 12k bytes externally. The HD6305X2 is a microcomputer unit which includes no ROM and its memory space
is expandable to 16k bytes ex ternally.
• HARDWARE FEATURES
• 8-bit based MCU
.4k-bytes of internal ROM (HD6305Xl)
No internal ROM (HD6305X2)
• 128-bytes of RAM
• A total of 31 terminals, including 24 I/O's, 7 inputs
.Two timers
8-bit timer with a 7-bit prescaler (programmable prescaler;
event counter)
15-bit timer (commonly used with tne SCI clock divider)
• On-chip serial interface circuit (synchronized with clock)
.Six interrupts (two external, two timer, one serial and one
software)
• Low power dissipation modes
- Wait .... In this mode, the clock oscillator is on and the
CPU halts but the timer/serial/interrupt func·
tion is operatable.
- Stop .... In this mode, the clock stops but the RAM
data, I/O status and registers are held.
- Standby.. In this mode, the clock stops, the RAM data
is held, and the other internal conditiOA is
reset.
• Minimum instruction cycle time
HD6305Xl/X2 .. 11ls (f = 1 MHz)
- HD63A05Xl/X2 .. 0.671ls (f = 1.5 MHz)
- HD63B05Xl/X2 .. 0.51ls (f = 2 MHz)
• Wide operating range
VCC =3 to 6V (f =0.1 to 0.5 MHz)
- HD6305Xl/X2 .. f =0.1 to 1 MHz (VCC =5V ± 10%)
- HD63A05Xl/X2 .. f = 0.1 to 1.5 MHz (VCC = 5V ± 100/0)
- HD63B05Xl/X2 .. f =0.1 to 2 MHz (VCC =5V ± 100;6)
• System development fully supported by an evaluation kit
HD6305X1P, HD63A05X1P,
HD63B05X1P, HD6305X2P,
H D63A05X2P, H D63B05X2P
H D6305X 1 F, H D63A05X 1 F,
HD63B05Xl F, HD6305X2F,
HD63A05X2F, HD63B05X2F
(FP-64)
• SOFTWARE FEATURES
.Similar to HD6800
• Byte efficient instruction set
• Powerful bit manipulation instructions (Bit Set, Bit Clear, and
Bit Test and Branch usable for all RAM bits and all I/O terminals)
• A variety of interrupt operations
• Index addressing mode useful for table processing
• A variety of conditional branch instructions
• Ten powerful addressing modes
-All addressing modes adaptable to RAM, and I/O instructions
• Three new instructions, STOP, WAIT and DAA, added to the
H06805 family instruction set
• Instructions that are upward compatible with those of Motorola's MC6805P2 and MC146805G2
~HITACHI
Hitachi America Ltd. - 2210 O'Toole Ave. - San Jose, CA 95131 - (408) 435-8300
599
HD6305X1,HD6305X2
• PIN ARRANGEMENT
• HD6305X1P, HD63A05X1P, HD63B05X1P, HD6305X2P,
HD63A05X2P,HD63B05X2P
vss.b
RES·C
IN"fC
STBVD
XTAlO
EXTAl
NUM
TIMER
•
HD6305X1F, HD63A05X1F, HD63B05X1F, HD6305X2F,
HD63A05X2F,HD63B05X2F
DATAo
DATA,
DATA 2
DATA 3
DATA.
DATAl
DATAe
DATA,
E
0
Ei
A,
A,
AI
A.
A3
A2
51
DATA 7
E
R'~
A/W
ADR13
ADR12
ADR"
ADA13
ADAI2
ADA"
ADR~
ADA,o
ADR,
ADR,
ADR,
ADR,
ADRI
ADR.
ADR 3
ADR2
ADR,
ADRo
0,
D,Im;=;
01
0_
03
Dz
A,
Ao
B,
B,
Bs
B.
B3
B2
B,
Bo
C,/Tx
C,I Rx
ClICK
C.
C3
Cz
C,
ADA g
ADAa
ADA7
ADA6
ADA~
ADA.
ADA)
ADA2
ADA,
ADAo
07
0,
~
Co - L -_ _ _ _ _ _.-J- Vee
u
-u u u
u
u
u
0
u
>
a
0
• BLOCK DIAGRAM
., I~
0 o
~
0
(Top View)
(Top View)
XTAl EXTAl
TIMER
Port A
I/O
Terminals
8
Index
Register
0,
CPU
Control
x
1/'-_ _--1 0
!i
~I
Condition Code
Aegister
CPU
O.;iNT2
D.
0"
Port 0
~~ ~':,~~naIS
Slack
6
Pointer
sp
Program
Counter
Port B
I/O
Terminals
6
"High" PCH
"OR I l
AOR 12
ADR"
ADR,o
AOR.
AOR.
ADRJ
ADR.
ADR,
AOR"
AOR,
ADRl
ADR,
ADRo
• No internal ROM in HD6305X2
DATA 1
DATA.
DATA,
DATA.
DATA,
DATAJ
DATA,
OAT",
600
DATAs
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H 0 6305X 1, H D6305X2
• ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 - +7.0
V
Input Voltage
Vin
-0.3 - Vee + 0.3
V
Operating Temperature
Topr
0-+70
°c
Storage Temperature
T stg
-55 - +150
°c
Item
[NOTE)
These products have a protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding,
be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normal
operation, we recommended Vin, Vout ; Vss ~ (Vin or Vout ) ~ Vee·
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee
= 5.0V±10%, Vss = GND, Ta '" 0 ~ +70o C, unless otherwise noted.)
Item
Symbol
Test Condition
RES, STBY
Input "High" Voltage
EXTAL
V 1H
min
typ
max
Vee-0 .5
-
Vee+0 .3
Vee xO . 7
-
Vee+0 . 3
2.0
-
Vee+ 0 .3
-0.3
0.8
V
V
Other Inputs
Input "Low" Voltage
All Inputs
V OH
Output "Low" Voltage
All Outputs
VOL
Input Leakage Current
TIMER,INT,
D1 - 0 7 , STBY
Illd
Three-state Current
Ao -- A 7 , Bo - B7 ,
Co -- C 7 , ADRo '" ADR13*'
DATAo""" DATA?, E*,R/W*
2.4
-
IOH '" -10J..LA
V ee -O.7
-
-
IOL'" 1.6mA
-
-
0.55
V
-
-
1.0
J..LA
-
-
1.0
J..LA
-
5
10
mA
2
5
mA
2
10
J..LA
2
10
J..LA
-
12
pF
Vin
= 0.5 -
Vec-0.5
IITs"
Operating
Current Dissipation * *
Wait
f
Icc
Stop
= lMHz***
Standby
Input Capacitance
All Terminals
f
Cin
V
IOH - -200J..LA
V 1L
Output "High" Voltage All Outputs
Unit
= 1MHz, Vin = OV
• Only at standby
.. VIH min = Vee-1.OV, VIL max = O.BV
* .. The value at f = xMHz is given by using
IcC (f =xMHz) = ICC If = 1MHz) x x
•
AC CHARACTERISTICS (Vee
Item
= 5.0V±10%, Vss =GND, Ta = 0"" +70°C, unless otherwise noted.)
Symbol
Test
Condition
H D6305X 1/X2
min
typ
HD63A05X 1/X2
max
min
typ
HD63B05X1/X2
max
min
typ
max
Unit
Cycle Time
tcyC
1
-
10
0.666
-
10
0.5
-
10
J..Ls
Enable Rise Time
tEr
-
20
ns
20
20
-
20
ns
Enable Pulse Width("High" Level)
PWEH
450
-
-
300
-
220
PW EL
450
-
-
300
-
220
-
ns
Enable Pulse Width("Low" Level)
Address Delay Time
tAO
-
-
250
-
190
-
Address Hold Time
tAH
40
-
-
30
-
20
-
20
-
Data Delay Time
tow
-
-
200
-
160
-
-
Data Hold Time (Write)
tHW
40
-
-
30
-
20
._- ..-
Data Set-up Time (Read)
tOSR
80
-
60
-
50
Data Hold Time (Read)
tHR
0
-
-
-
-
tEf
-
20
Enable Fall Time
-
0
-
--
C
Fig. 1
---
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
ns
180
ns
-
ns
120
ns
--.--
------
--
---
._ ..ns
--- .-
--
--
ns
--
ns
601
HD6305X1,HD6305X2
•
PORT TIMING (Vee
= 5.0V±10%, Vss =GND, Ta = 0 -
Item
•
Symbol
Port Data Set·up Time
(Port A, B, C, D)
tpDS
Port Data Hold Time
(Port A, B, C, D)
tpDH
Port Data Delay Time
(Port A, B, C)
tpDW
H D6305X 1/X2
H D63A05X 1/X2
HD63B05Xl/X2
Unit
min
typ
max
min
typ
max
min
typ
max
200
-
-
200
-
-
200
-
-
ns
200
-
-
200
-
-
200
-
-
ns
-
-
300
-
-
300
-
-
300
ns
Fig.2
CONTROL SIGNAL TIMING (Vee
Item
Test
Condition
+70°C, unless otherwise noted.)
Fig.3
= 5.0V±10%, Vss =GND, Ta = 0 -
Symbol
Test
Condition
+70°C, unless otherwise noted.)
HD6305Xl/X2
HD63A05Xl/X2
typ
max
min
typ
max
min
-
-
-
-
tcyc
+200
tcyc
+200
INTPulse Width
tlWL
tcyc
+250
INT2 Pulse Width
tlWL2
tcyc
+250
-
-
tcyc
+200
tcyC
+200
-
-
RES Pulse Width
t RWL
5
-
-
5
-
-
Control Set·up Time
tes
250
-
-
250
-
-
Fig.5
Tim~r Pulse Width
t TwL
Oscillation Start Time (Crystal)
tose
Fig.5,Fig.20'
Reset Delay Time
tRHL
Fig. 19
H D63B05X 1/X2
min
Unit
typ
max
-
-
ns·
-
-
ns
5
-
-
tCyc
250
-
-
ns
-
-
tcyc
+200
-
-
ns
20
tcyc
+200
-
-
20
-
-
20
ms
-
80
-
-
80
-
-
ms
tcyc
+250
-
-
-
-
80
-
I
* CL = 22pF ±20%, Rs = 60Q max .
•
SCI TIMING (Vee = 5.0V±10%, Vss= GND, Ta
Item
Symbol
Clock Cycle
tscyc
Data Output Delay Time
tTXD
Data Set·up Time
tSRX
Data Hold Time
tHRX
602
=0 -
+70°C, unless otherwise noted.)
Test
Condition
Fig.6,
Fig.7
HD6305Xl/X2
min
typ
1
-
-
-
200
100
max
HD63A05Xl/X2
min
HD63BG5Xl/X2
max
min
typ
max
16384
-
ns
-
ns
-
21845
0.5
250
-
-
250
-
-
200
-
200
-
100
-
-
-
100
-
32768 0.67
Unit
typ
250
$HITACftl
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
J1S
ns
HD6305X1,HD6305X2
Port
Port
AB,C,D
A,B,C
2.4V
O.6V
Data
Valid
Figure 3 Port Data Delay Time (MCU Write)
Figure 2 Port Data Set-up and Hold Times
(MCU Read)
Interrupt
Test
E
Address
Bus
INT,INT2
Vector Vector New PC
MSB
LSB
Address
Address Address
Op Code Op Code 1FFF
Address Address + 1
~\~._ - - - - I/
PCoPC7
Data Bus
R/IN
Op
Operand Irrelevant
Code
Op Code Oa.a
PCaPC13
IX
CC
Vector
Vector
~::'ess~~~ress
First Inst. of
Interrupt Routine
\\-______--J/
Figure 4
I nterrupt Sequence
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
603
HD6305X',HD6305X2
E
Vee
Address
Bus
's~-I/IllllIllllll
R/W
__
Data Bus
_ _ _,-,----------i~~--f)I/I//!I///h----
Figure5 Reset Timing
tscyC
Clock Output
2.4V
C5/CK
O.6V
Data Output
C7/TX
tSRX
tHRX----
Data Input
2.0V
C6/RX
O.8V
Figure6 SCI Timing (Internal Clock)
tscyC
2.0V
Clock Input
C5/CK
O.8V
trxD
Data Output
2.4V
C7/TX
O.6V
tSRX
Data Input
2.0V
C6/RX
O.8V
Figure7 SCI Timing(External Clock)
604
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------HD6305X1,HD6305X2
Vcc
TTL Load
(Port)
IOL=1.6mA
2.4kQ
• Address Bus (ADR o - ADR 13)
Each terminal is TTL compatible and can drive one TTL
load and 90pF.
Test point
terminal
n-------<_--~>---_jl.....-~
90pF
• Data Bus (DATA o - OATA 7)
This TTL compatible three-state buffer can drive one TTL
load and 90pF.
12kQ
• Input/Output Terminals (Ao - A7, Bo - B7, Co - C 7 )
These 24 terminals consist of three 8-bit I/O ports (A, B, C).
Each of them can be used as an input or output terminal on
a bit through program control of the data direction register.
For details, refer to "I/O PORTS."
[NOTES 1 1. The load capacitance in eludes stray capacitance caused
by the probe. etc.
2. All diodes are 152074
®.
Figure 8 Test Load
- DESCRIPTION OF TERMINAL FUNCTIONS
The input and output signals of the MCU are described
here.
.Vee, Vss
Voltage is applied to the MCU through these two terminals.
Vee is S.OV ± 10%, while Vss is grounded.
.INT, INT2
External interrupt· request inputs to the MCU. For details,
refer to "INTERRUPT". The INT2 terminal is also used as
the port 0 6 terminal.
• Input Terminals (01 - D7)
These seven input-only terminals are TTL or CMOS compatible. Of the port D's, 06 is also used as INT2. If 06 is
used as a port, the INT2 interrupt mask bit of the miscellaneous register must be set to "1" to prevent an INT2 interrupt
from being accidentally accepted.
.STBY
This terminal is used to place the MCU into the standby
mode. With STBY at "Low" level, the oscillation stops and
the internal condition is reset. For details, refer to "Standby Mode."
The terminals described in the following are I/O pins for
serial communication interface (SCI). They are also used as
ports C 5 , C6 and C7 • For details, refer to "SERIAL COMMUNICATION INTERFACE."
.CK (Cs)
Used to input or output clocks for serial operation .
• XT AL, EXT AL
These terminals provide input to the on-chip clock circuit.
A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic
fIlter is connected to the terminal. Refer to "INTERNAL
OSCILLATOR" for using these input terminals.
• TIMER
This is an input terminal for event counter. Refer to
"TIMER" for details.
.RES
Used to reset the MCU. Refer to "RESET" for details.
.NUM
This terminal is not for user application. In case of the
HD630SX1, this terminal should be connected to Vee
through 10k51 resistance. In case of the HD6305X2, this
terminal should be connected to Vs s .
• Enable (E)
This output terminal supplies E clock. Output is a singlephase, TTL compatible and 1/4 crystal oscillation frequency
or 1/4 external clock frequency. It can drive one TTL load
and a 90pF condenser.
• Rx (C6)
Used to receive serial data.
.Tx (C7)
Used to transmit serial data .
-MEMORY MAP
The memory map of the MCU is shown in Fig. 9. $1000$1 FFF of the HD630SX2 are external addresses. However,
care should be taken to assign vector addresses to $1 FF6 $1 FFF. During interrupt processing, the contents of the CPU
registers are saved into the stack in the sequence shown in
Fig. 10. This saving begins with the lower byte (PCL) of the
program counter. Then the value of the stack pointer is
decremented and the higher byte (PCH) of the program
counter, index register (X), accumulator (A) and condition
code register (CC) are stacked in that order. In a subroutine
call, only the contents of the program counter (PCH and PCL)
are stacked.
• Read/Write (R/W)
This TTL compatible output signal indicates to peripheral
and memory devices whether MCU is in Read ("High"), or
in Write ("Low"). The normal standby state is Read ("High").
Its output can drive one TTL load and a 90pF condenser.
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
605
HD6305X1,HD6305X2
o
127
128
255
256
PORT A
PORT B
PORT C
PORT D
PORT A DDR
PORT BOOR
PORT C DDR
Not Used
8 Timer Data Reg
9 Timer CTRL Reg
10 Misc Reg
0
1
2
3
4
5
6
1$0000
I/O Ports
Timer
SCI
'$007F
RAM
(128Bytes)
Stack
~0080
$gOFF
External
Memory Space
$ \0
$00
$01
$02
$03"
$04"
$05$06$08
$09
$OA
-REGISTERS
There are five registers which the programmer can operate,
o
7
L..._ _ _ _A_ _ _ _~I Accumulator
1
o
7
Iindex
X _ _ _ _...1 Register
' - -_ _ _ _
1
o
13
I:rogram
PC
L..._ _ _ _ _ _ _
_ _ _ _ _ _ _--I. Counter
1
13
6 5
0
I 0-,-1o..&..lo......l_olL..0.J...10......1_1..&..1_1L..I_ _S_p_----II ~~~~fer
L.
4095
4096
$OFFF
ROM·
(4,096Bytes)
---------
8182 , Interrupt·
819 1 Vector;;
8192
S'00~6
Not Used
r -......~-r--_....,
L..;,;...L..,....L..,....JL....,...L..,..J
SCI CTRL Reg $10
17 SCI STS Reg $11
18 SCI Data Reg $12
$1FF6
$1 FFF
$2000
~gg~~
Zero
' - - - - - Negative
Not Used
$lF
31
32 External
$20
Memory Space
$7F
External
Memory Space
16383
Condition
Code
Register
'-------Interrupt
Mask
Half
Carry
12J~
$3FFF
L--_ _ _ _ _
Figure 11 Programming Model
* Write only reg ister
* * Read only reg'Ister
* ROM area ($1000 - $1 FFF) in the HD6305X2
is changed into External Memory Space.
• Accumulator (A)
This accumulator is an ordinary 8-bit register which holds
operands or the result of arithmetic operation or data processing.
Figure 9 Memory Map of MCU
7 6 5 4 3 2 1 o
n-4 1 1 11 Condition
n+1
Code Register
n-3
Accumulator
n+2
n-2
Index Register
n+3
PCW
n+4
n-1
n
0 01
PCL-
Pull
n+5
Push
* In a subroutine call, only PCl and PCH are stacked.
Figure 10 Sequence of Interrupt Stacking
• Index Register (X)
The index register is an 8-bit register, and is used for index
addressing mode. Each of the addresses contained in the
register consists of 8 bits which, combined with an offset
value, provides an effective address.
In the case of a read/modify/write instruction, the index
register can be used like an accumulator to hold operation
data or the result of operation,
If not used in the index addressing mode, the register can
be used to store data temporarily.
• Program Counter (PC)
The program counter is a 14-bit register that contains the
address of the next instruction to be executed.
• Stack Pointer (SP)
The stack pointer is a 14-bit register that indicates the address of the next stacking space. Just after reset, the stack
pointer is set at address $OOFF. It is decremented when data
is pushed, and incremented when pulled. The upper 8 bits
of the stack pointer are fixed to 00000011. During the MCV
being reset or during a reset stack pointer (RSP) instruction,
the pointer is set to address $OOFF. Since a subroutine or
interrupt can use space up to address $OOCI for stacking, the
subroutine can be used up to 31 levels and the interrupt up
to 12 levels .
• Condition Code Register (CC)
The condition code register is a 5-bit register, each bit
indicating the result of the instruction just executed. The
bits can be individually tested by conditional branch instruc-
606
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - HD6305Xl,HD6305X2
tions. The CC bits are as follows:
Half Carry (H): Used to indicate that a carry occurred between bits 3 and 4 during an arithmetic operation (ADD, ADC).
Setting this bit causes all interrupts, except
Interrupt (I):
a software interrupt, to be masked. If an
interrupt occurs with the bit I set, it is
latched. It will be processed the instant
the interrupt mask bit is reset. (More specifically, it will enter the interrupt processing
routine after the instruction following the
CLI has been executed.)
Negative (N): Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is negative (bit 7 is logic
"1 ").
Used to indicate that the result of the most
Zero (Z):
recent arithmetic operation, logical operation
or data processing is zero.
Represents a carry or borrow that occurred
Carry/
Borrow (C): in the most recent arithmetic operation. This
bit is also affected by the Bit Test and Branch
instruction and a Rotate instruction.
Of these six interrupts, the INT2 and TIMER or the SCI
and TIMER2 generate the same vector address, respectively.
When an interrupt occurs, the program in progress stops
and the then CPU status is saved onto the stack. And then,
the interrupt mask bit (I) of the condition code register is
set and the start address of the interrupt processing routine
is obtained from a particular interrupt vector address. Then
the interrupt routine starts from the start address. System
can exit from the interrupt routine by an RTI instruction.
When this instruction is executed, the CPU status before
the interrupt (saved onto the stack) is pulled and the CPU
restarts the sequence with the instruction next to the one at
which the interrupt occurred. Table 1 lists the priority of
interrupts and their vector addresses.
Table 1
Interrupt
-INTERRUPT
There~e six different types of interrupt: external.interrupts (INT, INT2), internal timer interrupts (TIMER,
TIMER2), serial interrupt (SCI) and interrupt by an instruction (SWI).
Priority of Interrupts
Priority
Vector Address
RES
1
$lFFE,
$lFFF
SWI
2
$lFFC,
$lFFD
INT
3
$lFFA,
$lFFB
TIMER/INT2
4
$lFF8,
$lFF9
SCI/TIMER2
5
$lFF6,
$lFF7
A flowchart of the interrupt sequence is shown in Fig. 12.
A block diagram of the interrupt request source is shown in
Fig. 13.
,---------,
y
TNT
y
fN'f;"
y
1~1
$FF~SP
TIMER
O~DDR's
CLR INT Logic
Y
SCI
$FF~TDR
$7F~ Timer
Prescaler
$50~TCR
$3F~SSR
$OO~SCR
$7F~MR
Figure 12 Interrupt Flow Chart
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
607
H D 6305X 1, H D 6305X2
Bit 7 of this register is the INT2 interrupt request flag.
When the falling edge is detected at the INT2 terminal, "1"
is set in bit 7. Then the software in the interrupt routine
(vector addresses: $lFF8, $IFF9) checks bit 7 to see if it
is INT2 interrupt. Bit 7 can be reset by software.
In the block diagram, both the external interrupts INT and
INT2 are edge trigger inputs. At the falling edge of each input,
an interrupt request is generated and latched. The INT interrupt request is automatically cleared if jumping is made to
the INT processing routine. Meanwhile, the INT2 request is
cleared if "0" is written in bit 7 of the miscellaneous register.
For the external interrupts (INT, INT2), internal timer
interrupts (TIMER, TIMER2) and serial interrupt (SCI), each
interrupt request is held, but not processed, if the I bit of the
condition code register is set. Immediately after the I bit is
cleared, the corresponding interrupt processing starts according to th!.E!!0rity.
The INT2 interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by setting bit 6
of the timer control register; the SCI interrupt by setting bit
5 of the serial status register; and the TIMER2 interrupt by
setting bit 4 of the serial status register.
The status of the INT terminal can be tested by a BIL or
BIH instruction. The INT falling edge detector circuit and
its latching circuit are independent of testing by these instructions. This is also true with the status of the INT2 terminal.
7
Miscellaneous Register (MR;$OOOA)
S
543210
IMR7IMRslzvv\ZVIZI
t
f
L __________
~-----------
INT2 Interrupt Mask
INT2 Interrupt Request Flag
Miscellaneous Register (MR; $OOOA)
Bit 6 is the [NT2 interrupt mask bit. If this bit is set to "1",
then the INT2 interrupt is disabled. Both read and write are
possible with bit 7 but "1" cannot be written in this bit by
software. This means that an interrupt request by software
is impossible.
When reset, bit 7 is cleared to "0" and bit 6 is set to "1"
eMiscelianeous Register (MR; $OOOA)
The interrupt vector address for the external interrupt
INT2 is the same as that for the TIMER interrupt, as shown
in Table 1. For this reason, a special register called the miscellaneous register (MR; $OOOA) is available to control the
INT2 interrupts.
-TIMER
Figure 14 shows a MCV timer block diagram. The timer
data register is loaded by software and, upon receipt of a
clock input, begins to count down. When the timer data
Vectoring generated
$1FFA,$1FFB
BIH/BIL Test
Condition Code Register (CC)
INT Interrupt Latch
INT
Fa"ing Edge Detector
")-_~t------
Vectoring generated
$1 FFB, $1 FF9
TIMER
Serial Status
Register (SSR)
SCI TlMER2
} - - - - - < - - - - Vectoring generated
$1FF6.$1FF7
~ igure
608
13 I nterrupt Request Generation Ci rcu itry
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6305X1,HD6305X2
register (TDR) becomes "0", the timer interrupt request
bit (bit 7) in the timer control register is set. In response to
the interrupt request, the CPU saves its status into 'the stack
and fetches timer interrupt routine address from addresses
$1 FF8 and $1 FF9 and execute the interrupt routine. The
timer interrupt can be masked by setting the timer interrupt
mask bit (bit 6) in the timer control register. The mask bit
(I) in the condition code register can also mask the timer
interrupt.
The source clock to the timer can be either an external
signal from the timer input terminal or the internal E signal
(the oscillator clock divided by 4). If the E signal is used as
the source, the clock input can be gated by the input to the
timer input terminal.
Once the timer count has reached "0", it starts counting
down with "$FF". The count can be monitored whenever
desired by reading the timer data register. This permits the
program to know the length of time having passed after the
occurrence of a timer interrupt, without disturbing the contents of the counter.
When the MCU is reset, both the prescaler and counter are
initialized to logic "I". The timer interrupt request bit
(bit 7) then is cleared and the timer interrupt mask bit (bit
6) is set.
To clear tl)e timer interrupt request bit (bit 7), it is necessary to write "0" in that bit.
• Timer Control Register (TCR; $0009)
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
Timer Control Register (TeR; $0009)
L.._ _ _ _ _ _ _ _ _ _
After reset, the TCR is initialized to "E under timer terminal control" (bit 5 = 0, bit 4 = 1). If the timer terminal is
"1", the counter starts counting down with "$FF" immediately after reset.
When "1" is written in bit 3, the prescaler is initialized.
This bit always shows "0" when read.
Table 2
TCR7
Timer interrupt request
o
Absent
TCR
Clock input source
Bit 4
0
0
I nternal clock E
0
1
E under timer terminal control
Enabled
1
0
No clock input (counting stopped)
Disabled
1
1
Event input from timer terminal
Timer interrupt mask
o
Clock Source Selection
Bit 5
Present
TCRS
Timer interrupt mask
' - - - - - - - - - - - - - - - Timer interrupt request
Initialize
!Internal
Clock)
E --I---l
Timer Data
Register
L....--"T""---...,.-----' Timer Interrupt
Write
Read
Figure 14 Timer Block Diagram
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
609
HD6305X1,HD6305X2 - - - - - - - - - - - - - - - - - - - - - - - - - _
A prescaler division ratio is selected by the combination of
three bits (bits 0, 1 and 2) of the timer control register (see
Table 3). There are eight different division ratios; +1, +2, +4,
+8, +16, +32, +64 and +128. After reset, the TCR is set to the
+1 mode.
A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "1". When a timer
interrupt occurs, "1" is set -in the timer interrupt request bit.
This bit can be cleared by writing "0" in that bit.
-SERIAL COMMUNICATION INTERFACE (SCI)
Table 3
This interface is used for serial transmission or reception
of 8-bit data. Sixteen transfer rates are available in the range
from 1 J.l.s to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one eighth counter and
one prescaier. (See Fig. 15.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 5,
6 and 7 of port C. Described below are the operations of
each register and data transfer.
Prescaler Division Ratio Selection
TCR
Bit 2
Bit 1
Bit 0
Prescaler division ratio
0
0
0
+1
0
0
1
+2
0
1
0
+4
0
1
1
+8
1
0
0
+16
1
0
1
+32
1
1
0
+64
1
1
1
+128
eSCI Control Register (SCR; $0010)
SCI Control Registers (SCR; 0010)
E
Transfer
Clock
Generator
SCI Data Registers ..........,r"----'
(SOR: $0012)
.-------1
Initialize
SCI Status Registers
(SSR :$0011)
Not Used
SCI/TIMER2
Figure 15 SCI Block Diagram
61.0
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
I
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6305X1 ,HD6305X2
Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completion of transmitting or receiving 8-bit data. It is
cleared when reset or data is written to or read from the
SCI data register with the SCRS=" 1". The bit can also be
cleared by writing "0" in it.
C 7 terminal
SCR7
o
Used as I/O terminal (by DDR).
Serial data output (DDR output)
Bit 6 (SSR6)
Bit 6 is the TIMER2 interrupt request bit. TIMER2 is used
commonly with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When reset, the
bit is cleared. It also be cleared by writing "0" in it. (For
details, see TIMER2')
C6 terminal
SCR6
o
Used as I/O terminal (by DDR).
Serial data input (DDR input)
SCR5 SCR4
Clock source
C s terminal
0
0
-
0
1
-
1
0
Internal
Clock output (DDR output)
1
1
External
Clock input (DDR input)
Used as I/O terminal (by
DDR).
Bit 7 (SCR7)
When this bit is set, the DDR corresponding to the C 7
becomes "1" and this tenninal serves for output of SCI data.
After reset, the bit is cleared to "0".
Bit 6 (SCR6)
When this' bit is set, the DDR corresponding to the C6
becomes "0" and this tenninal serves for input of SCI data.
After reset, the bit is cleared to "0".
Bit 5 (SSRS)
Bit 5 is the SCI interrupt mask bit which can be set or
cleared by software. When it is "1 ", the SCI interrupt (SSR7)
is masked. When reset, it is set to "1".
Bit 4 (SSR4)
Bit 4 is the TIMER2 interrupt mask bit which can be set
or cleared by software. When the bit is "1", the TIMER2
interrupt (SSR6) is masked. When reset, it is set to "1".
Bit 3 (SSR3)
When "1" is written in this bit, the prescaler of the transfer
clock generator is initialized. When read, the bit always is "0".
Bits 2 '" 0
Not used.
Bits 5 and 4 (SCRS, SCR4)
These bits are used to select a clock source. After reset,
the bits are cleared to "0".
SCRl
SCRO
SCR2
0
0
0
0
0
0
0
0
0
SCI interrupt request
o
Absent
Present
SSR6
Bits 3,.., 0 (SCR3 "" SCRO)
These bits are used to select a transfer clock rate. After
reset, the bits are cleared to "0".
SCR3
SSR7
o
Absent
Present
Transfer clock rate
4.00 MHz
4.194 MHz
SSR5
1 /-lS
0.95/-ls
o
1
2/-ls
1.91/-ls
1
0
4/-ls
3.82/-ls
0
0
1
1
8/-ls
7.64 /-ls
SSR4
l
I
l
I
I
l
o
1
1
1
1
32768/-ls
1/32
SCI interrupt mask
Enabled
Disabled
S
-SCI Data Register (SDR; $0012)
A serial-parallel conversion register that is used for transfer
of data.
-SCI Status Register (SSR; $0011)
TIMER2 interrupt request
TIMER2 interrupt mask
Enabled
Disabled
• Data Transmission
By writing the desired control bits into the SCI control
registers, a transfer rate and a source of transfer clock are
detennined and bits 7 and 5 of port C are set at the serial
data output tenninal and the serial clock tenninal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data
written in the SCI data register is output frOIl1 till' C 7/Tx
tenninal, starting with the LSB. synchronollsly with the
falling edge of the serial clock. (See hg. I I,.) When H hit of
~ HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
611
HD6305X1,HD6305X2
data have been transmitted, the interrupt request bit is set in
bit 7 of the SCI status register with the rising edge of the last
serial clock. This request can be masked by setting bit 5 of the
SCI status register. Once the data has been sent, the 8th bit
data (MSB) stays at the C7/Tx terminal. If an external clock
source has been selected, the transfer rate determined by
bits 0 '" 3 of the SCI control register is ignored, and the Cs /
CK terminal is set as input. If the internal clock has been
selected, the Cs /CK terminal is set as output and clocks are
output at the transfer rate selected by bits 0 '" 3 of the SCI
control register.
Figure 16 SCI Timing Chart
• Data Reception
By writing the desired control bits into the SCI control
register, a transfer rate and a source of transfer clock are determined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock terminal, respectively.
Then dummy-writing or -reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed after reading subsequent received data. It must be taken
after reset and after not reading subsequent received data.
The data from the C6 /Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig. 16). When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bit 5
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0 ..... 3 of the SCI
control register is ignored and the data is received synchronously with the clock from the C s /CK terminal. If the internal
clock has been selected, the Cs/CK terminal is set as output
and clocks are output at the transfer rate selected by bits 0 .....
3 of the SCI control register.
TIMER2 is commonly used with the SCI transfer clock
generator. If wanting to use TIMER2 independently of the
SCI, specify "External" (SCRS = 1, SCR4 = 1) as the SCI
clock source.
If "Internal" is selected as the clock source, reading or
writing the SDR causes the' prescaler of the transfer clock
generator to be initialized.
-I/O PORTS
There are 24 input/output terminals (ports A, B, C). Each
I/O terminal can be selected for either input or output by the
data direction register. More specifically, an I/O port will
be input if "0" is written in the data direction register, and
output if "1" is written in the data direction register. Port A,
B or C reads latched data if it has been programmed as output,
even with the output level being fluctuated by the output
load. (See Fig. 17.)
When reset, the data direction register and data register go
to "0" and all the input/output terminals are used as input.
Bit of data
direction
register
Bit of
output
data
Status of
output
Input to
CPU
1
0
0
0
1
1
0
X
Figure 17
.TIMER2
The SCI transfer clock generator can be used as a timer.
The clock selected by bits 3 ..... 0 of the SCI control register
(4 p.s ..... approx. 32 ms (for oscillation at 4 MHz» is input to
bit 6 of the SCI status register and the TIMER2 interrupt
request bit is set at each falling edge of the clock. Since interrupt requests occur periodically, TIMER2 can be used as a
reload counter or clock.
@@
L
CD
: Transfer
clock generator is reset and mask bit (bit 4
of SCI status register) is elea red.
00. C!) : TIMER2
®.@ : TIMER2
612
interrupt request
interrupt request bit cleared
1
3·state
1
Pin
I nputlOutput Port Diagram
Seven input-only terminals are available (port D). Writing
to an input terminal is invalid.
All input/output terminals and input terminals are TTL
compatible and CMOS compatible in respect of both input and
output.
If I/O ports or input ports are not used, they should be
connected to Vss via resistors. With none connected to these
terminals, there is the possibility of power being consumed
despite that they are not used.
-RESET
The MCU can be reset either by external reset input (RES)
or power-on reset. (See Fig. 18.) On power up, the reset
input must be held "Low" for at least tose to assure that the
internal oscillator is stabilized. A sufficient time of delay can
be obtained by connecting a capacitance to the RES input as
shown in Fig. 19.
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6305X1,HD6305X2
requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 - 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the required oscillation frequency stability.
Three different terminal connections are shown in Fig. 20.
Figs. 21 and 22 illustrate the specifications and typical arrangement of the crystal, respectively.
5V
Vcc
OV--------------
RES
Terminal
---------1""
AT Cut
Parallel
Resonance
Co=7pF max.
XTAL~WEXTAL f=2.0-S.0MHz
Rs=600 max.
Cl
~:;~al-----------~
Figure 18 Power On and Reset Timing
~~
Figure 21
Parameters of Crystal
100kS1 typ
V CC~, AJ"~--4--~
(a)
HD6305X
MCU
Figure 19
Input Reset Delay Circuit
-INTERNAL OSCILLATOR
The internal oscillator circuit is designed to meet the
[NOTE]
Use as short wirings as possible for connection of the crystal
with the EXTAL and XTAL terminals. Do not allow these
wirings to cross others.
1-----4....--l EXTAL
lO+MH>=
XTAL
Figure 22
HD6305X
MCU
10-22pF±20%
-LOW POWER DISSIPATION MODE
The HD6305X has three low power dissipation modes:
wait, stop and standby.
Crystal Oscillator
HD6305X
MCU
External,....._ _. :C..:e.:. ,:ra:..:.;m.,;;i..:.c. ,;O;..,;S..:.ci_lI_at_O.,r
Clock
Input
EXTAL
NC
XTAL HD6305X
MCU
External Clock Drive
Figure 20
Typical Crystal Arrangement
Internal Oscillator Circuit
• Wait Mode
When WAIT instruction being executed, the MCU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication interface - stay active. (NOTE: Once the system has entered the
wait mode, the serial communication interface can no longer
be retriggered.) In the wait mode, the registers, RAM and I/O
terminals hold their condition just before entering into the
wait mode.
The escape from this mode can be done by interrupt (INT,
TIMER/!NT2 or SCI/TIMER2), RES or STBY. The RES
resets the MCU and the STBY brings it into the standby
mode. (This will be mentioned later.)
When interrupt is requested to the CPU and accepted, the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit of the condition code register, after releasing from the wait mode the MCU executes the instruction
next to the WAIT. If an interrupt other than the fNT (i.e.,
TTMER/INT2 or SCI/TIMER2) is masked by the timer control
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
613
HD6305X1,HD6305X2 - - - - - - - - - - - - - - - - - - - - - - - - - register, miscellaneous register or serial status register, there
is no interrupt request' to the CPU, so the wait mode cannot
be released.
Fig. 23 shows a flowchart for the wait function.
• Stop Mode
When STOP instruction being executed, MCU enters into
the stop mode. In this mode, the oscillator stops and the CPU
and peripheral functions become inactive but the RAM,
registers and 1/0 terminals hold their condition just before
entering into the stop mode.
The escape from this mode can be done by an external
interrupt (I"'N'f or INTi), RES or STBY. The RES resets the
MCU and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted,
the stop mode escapes, then the CPU is brought to the opera·
tion mode and vectors to the interrupt routine. If the inter·
rupt is masked by the I bit of the condition code register,
after releasing from the stop mode, the MCU executes the
instruction !\ext to the STOP. lethe INT2 interrupt is masked
by the miscellaneous register, there is no interrupt request to
the MCU, so the stop mode cannot be released.
Fig. 24 shows a flowchart for the stop function. Fig. 25
shows a timing chart of return to the operation mode from
the stop mode.
For releasing from the stop mode by an interrupt, oscilla·
tion starts upon input of the interrupt and, after the internal
delay time for stabilized oscillation, the CPU becomes active .
For restarting by RES, oscillation starts when the RES goes
"0" and the CPU restarts when the RES goes" I". The dura·
tion of RES="O" must exceed tosc to assure stabilized oscil·
lation.
• Standby Mode
The Meu enters into the standby mode when the STBY
terminal goes "Low". In this mode, all operations stop and
the internal condition is reset but the contents of the RAM are
hold. The 1/0 terminals turn to high-impedance state. The
standby mode should escape by bringing STBY "High". The
CPU must be restarted by reset. The timing of input Signals
at the RES and STBY terminals is shown in Fig. 26.
Table 4 lists the status of each parts of the MeU in each
low power dissipation modes. Transitions between each mode
are shown in Fig. 27.
(Note)
~en I bit of condition code register is "I" and interrupt
(INT, TIMER/INT 2 , SCI/TIMER2) is held, MeU does not enter
WAIT mode by the execution of WAIT instruction.
In that case, after the 4 dummy cycles MeU executes the
next instruction.
In the same way, when external interrupts (INT, INT 2) are
held at the bit I set, MeU does not enter STOP mode by the
execution of STOP instruction. In that case, also, MeU executes
the next instruction after the 4 dummy cycles.
614
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6305X1,HD6305X2
Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop
Initialize
CPU, TIMER, SCI,
I/O and All
Other Functions
No
No
1=1
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 23 Wait Mode Flow Chart
@jHITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
615
HD6305X1,HD6305X2
Stop Oscillator
and All Clocks
No
Turn on Oscillator
Wait for Time Delay
to Stabilize
Turn on Oscillator
Wait for Time Delay
to Stabilize
1=0
1=1
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 24 Stop Mode Flow Chart
616
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------- HD6305X1,HD6305X2
"1111" Ill" 111111111111111
Osci lIator
E
aerrTlllllllllllllllllllllllllllllllllllllllllllllIIlllll1IIII
(
~'l----+----'
I
stabilized (built-in delay time)
Interrupt
STOP instruction
executed
restart
(a) Restart by Interrupt
Oscillator
11111111111111111111111111111
E
Time required for oscillation to become
STOP instruction
executed
stabilized (tos c)
(b) Restart by Reset
Figure 25
Timing Chart of Releasing from Stop Mode
'-------I~l)O_-----J1
;,
,
,
,
,
I
~-~-~--~~--------~r-------------~------------~
tosc
Figure 26
Table 4
Restart
Timing Chart of Releasing from Standby Mode
Status of Each Part of MCU in Low Power Dissipation Modes
Condition
Mode
Start
WAIT
Software
STOP
Standby
Hardware
Oscillator
WAIT instruction
Escap€
1/0
CPU
Timer,
Serial
Register
RAM
Active
Stop
Active
Keep
Keep
Keep
STBY, RES, INT, INT 2 ,
each interrupt request of
TIMER, TIMER 2 , SCI
STOP instruction
Stop
Stop
Stop
Keep
Keep
Keep
STBY, RES, INT, INT2
STBY="Low"
Stop
Stop
Stop
Reset
Keep
High impedance
terminal
STBy,:"High"
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
617
HD6305Xl,HD6305X2
Figure 27
Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset
-BIT MANIPULATION
The MCU can use a single instruction (BSET or BCLR) to
set or clear one bit of the RAM or an I/O port (except the
write-only registers such as the data direction register). Every
bit of memory or I/O within page 0 ($00 ~ $FF) can be tested
by the BRSET or BRCLR instruction; depending on the result
of the test, the program can branch to required destinations.
Since bits in the RAM, or I/O can be manipulated, the user
may use a bit within the RAM as a flag or handle a single I/O
bit as an independent I/O terminal. Fig. 28 shows an example
of bit manipulation and the validity of test instructions. In
the example, the program is configured assuming that bit 0
of port A is connected to a zero cross detector circuit and
bit 1 of the same port to the trigger of a triac.
The program shown can activate the triac within a time of
lOllS from zero-crossing through the use of only 7 bytes on
the ROM. The on-chip timer provides a required time of
delay and pulse width modulation of power is also possible.
SE LF 1.
Figure 28
BRCLR 0, PORT A, SELF 1
BSET 1, PORT A
BCLR 1. PORT A
Example of Bit Manipulation
the byte that follows the operation code.
• Direct
See Fig. 30. In the direct addressing mode, the address of
the operand is contained in the 2nd byte of the instruction.
The user can gain direct access to memory up to the lower
255th address. All RAM and I/O registers are on page 0 of ad·
dress space so that the direct addressing mode may be utilized.
• Extended
See Fig. 31. The extended addressing is used for referencing to all addresses of memory. The EA is the contents of
the 2 bytes that follow the operation code. An extended
addressing instruction requires a length of 3 bytes.
• Relative
See Fig. 32. The relative addressing mode is used with
branch instructions only. When a branch occurs, the program
counter is loaded with the contents of the byte following the
operation code. EA = (PC) + 2 + ReI., where ReI. indicates a
signed 8-bit data following the operation code. If no branch
occurs, ReI. = O. When a branch occurs, the program jumps
to any byte in the range + 129 to -127. A branch instruction
requires a length of 2 bytes.
-ADDRESSING MODES
• Indexed (No Offset)
Ten different addressing modes are available to the MCU.
• Immediate
See Fig. 29. The immediate addressing mode provides
access tv a constant which docs not vary during execution of
the program.
This access requires an instruction length of 2 bytes. The
effective address (LA) is PC and the operand is fetched from
618
See Fig. 33. The indexed addressing mode allows access
up to the lower 255th address of memory. In this mode, an
instruction requires a length of one byte. The EA is the
contents of the index register.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6305Xl,HD6305X2
e Indexed (8-bit Offset)
See Fig. 34. The EA is the contents of the byte following the operation code, plus the contents of the index register.
This mode allows access up to the lower 511 th address of
memory. Each instruction when used in the index addressing
mode (8-bit offset) requires a length of 2 bytes.
elndexed (16-bit Offset)
See Fig. 35. The contents of the 2 bytes following the
operation code are added to content of the index register
to compute the value of EA. In this mode, the complete
memory can be accessed. When used in the indexed addressing mode (l6-bit offset), an instruction must be 3 bytes long.
e Bit Set/Clear
See Fig. 36. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
O. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte that follows the operation code
indicates an address within page O.
e Bit Test and Branch
See Fig. 37. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. Individual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relative value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code register.
elmplied
See Fig. 38. This mode involves no EA. All information
needed for execution of an instruction is contained in the
operation code. Direct manipulation on the accumulator
and index register is included in the implied addressing mode.
Other instructions such as SWI and RTI are also used in this
mode. All instructions used in the implied addressing mode
should have a length of one byte.
EA
Memory
A
F8
Index Reg
I
Stack Point
PROG LOA :I$F8
058Et-:=4.~~------~
Prog Count
05CO
CC
05BFI-
1--'-;";;--1
~
I
I
Figure 29
Example of Immediate Addressing
Memory
A
CAT FCB 32 004B
t::JSc::1---t----~~----_C~2~0::J
Index eg
Stack !I:-'o""'in"'"t---'
PROG LOA CAT
~~~~r7.~-;__-.--J
Figure 30
Prog !ount
052F
CC
Example of Direct Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
619
HD6305Xl,HD6305X2
Memory
~
:
0000
A
:
40
PROG LOA CAT 0409t--~;-----lL
040A ..........;;.;:;....--I
040B ...........;;.;:;....--I;
Index Reg
I
Stack Point
Prog Count
CATFCB6406E5~~~__~--------------~
040C
CC
Figure 31
Example of Extended Addressing
PROG BEQ PROG2 04A 7
04ASI----".,.....--t
~
;
;
Figure 32
Example of Relative Addressing
A
TABLFCC LI
00BSt::J~::j-----~~--------t---------~~~4~C~~
BS
Stack POint
Prog Count
05F5
CC
Figure::l3
620
Example of Indexed (No Offset) Addressing
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6305X1,HD6305X2
Memory
BF
86
DB
CF
8F
0089
008A
008B
008C
86
DB
CF
PROG LOA TABL.X 075B
075C
E6
89
TABL FCB
FCB
FCB
FCB
A
CF
Index Reg
03
Stack Point
I
Prog Count
0750
CC
I
~
I
I
Figure 34
Example of Index (8-bit Offset) Addressing
Memory
@
.
TABL FCB
FCB
FCB
FCB
BF
DB
Index Re9
.
02
Stack
PROG LOA TABLX g::~I-~~--1
0694
A
oint
Prog Count
1--";';;""--1
0695
CC
077E 1---";;'.,,---1
'":~~=:t---------_-.J
86
077F
DB 0780\CF 0781
1--""';;'---1
Figure 35
PORT B EQU 1 0001
Example of Index (16-bit Offset) Addressing
t---"''---fi
A
Index Reg
PROG BCLR 6. PORT B 058F t-::jl~D=::t-_ _ _ _.J
0590101
I
Stack Pomt
Prog Count
0591
CC
~
.
,
Figure 36
Example of Bit Set/Clear Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
621
H D6305X 1, H D6305X2
PORT C EOU 2 0002 t-.....;.;~~
PROG BRCLR 2.PORT CPROG 2 0574
t::~~:::~
05 75
0576'-
t-.....;.;~~I
Figure 37
Ex~mple of Bit Test and Branch Addressing
Memory
i
I
~
,"OG,., 0". ~
~
,,
,,
,
,,,
Figure 38
Example of Implied Addressing
-INSTRUCTION SET
There are 62 basic instructions available to the HD6305X
MeV. They can be classified into five categories: register/
memory, read/modify/write, branch, bit manipulation, and
control. The details of each instruction are described in
Tables 5 through 11.
• Register/Memory Instructions
Most of these instructions use two operands. One operand
is either an accumulator or index register. The other is derived
from memory using one of the addressing modes used on the
HD6305X MeV. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump
instruction (JSR). See Table 5.
• Re.d/ModifylWrite Instructions
These instructions read a memory or register, then modify
or test its contents, and write the modified value into the
memory or register. Zero test instruction (TST) does not
write data, and is handled as an exception in the read/modify/
write group. See Table 6.
622
• Branch Instructions
A branch instruction branches from the program sequence
in progress if a particular condition is established. See Table 7.
• Bit Manipulation Instructions
These instructions can be used with any bit located up to
the lower 255th address of memory. Two groups are available;
one for setting or clearing and the other for bit testing and
branching. See Table 8.
• Control Instructions
The control instructions control the operation of the Mev
which is executing a program. See Table 9.
• List of Instructions in Alphabetical Order
Table 10 lists all the instructions used on the HD6305X MeV in the alphabetical order.
• Operation Code Map
Table 11 shows the operation code map for the instructions
used on the MeV.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6305X1,HD6305X2
Table 5 Register/Memory Instructions
Addressing Modes
Indexed
MnemoniC
Operations
Immediate
Extended
Direct
Indexed
OP II
-
OP II
-
-
OP II
-
OP II
OP II
-
Load A from Memory
LOA
A6 2
2
B6
2
3 C6
3
4
F6
1
3
E6
2
4 06 3
5
Load X from Memory
LOX
AE
2
2
BE
2
3 CE
3
4
FE
1
3
EE
2
4
DE 3
5
M-X
Store A in Memory
STA
--
-
B7
2
3 C7
3
4
F7
1
4
E7
2
4 07 3
5
A-M
Store X in Memory
STX
-
-
-
BF
2
3
CF
3
4
fF
1
4
EF
2
4 OF 3
5
X-M
Add Memory to A
ADD
AB
2
2 BB
2
3 CB 3
4
FB
I
3
EB
2
4 DB 3
5
A+M-·A
to A
ADC
A9
2
2
B9
2
3 C9
3
4
F9
1
3
E9
2
4 09 3
5
A+M+C-A
Subtract Memory
SUB
AO
2
2 BO
2
3 CO 3
4
FO
1
3
EO
2
4 DO 3
5
A-M-A
A with Borrow
SBC
A2
2
2 B2
2
3 C2
3
4
F2
1
3
E2
2
4 02 3
5
A-M-C-A
AND Memory to A
AND
A4
2
2 B4
2
3 C4 3
4
F4
1
3
E4
2
4 04 3
5
A·M-A
OR Memory with A
ORA
AA 2
2 BA 2
3 CA 3
4
FA
1
3
EA 2
4 DA 3
5
A+M-A
EOR
A8
2
2 B8
2
3 C8
3
4
F8
I
3
E8
2
4 08 3
5
AEBM-A
CMP
Al
2
2
Bl
2
3 Cl
3
4
Fl
I
3
El
2
4
01
3
5
A-M
CPX
A3
2
2 B3
2
3 C3 3
4
F3
I
3
E3
2
4 03 3
5
A (L09ical Compare)
BIT
AS
2
2
B5
2
3 C5
3
4
F5
I
3
E5
2
4 05 3
5
Jump Unconditional
JMP
BC
2
2 CC 3
3
FC
I
2 EC
2
3 DC 3
4
Jump to Subroutine
JSR
BO 2
5 CD 3
6 FD
I
5 ED 2
5 DO 3
6
OP II
-
Condition
Code
Boole8n/
Arithmetic
Operation
Indexed
(No Offset) (8-BitOffset) (16-BitOffset)
N
Z
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
I,
1\
f,
1\
1\
1\
f,
1\
1\
1\
,f,
1\
•
1\
1\
• •
1\
f
•
• •
1\
1\
/\
X-M
• •
1\
f,
1\
A·M
• • " •
• • • •
• • • • •
M-A
H
I
•
•
•
•
•
•
•
•
•
1\
Add Memory and Carry
•
• •
1\
C
•
•
•
•
Subtract Memory from
• •
• •
• •
Exclusive OR Memory
with A
·
Arithmetic Compare A
with Memory
Arithmetic Compare X
with Memory
Bit Test Memory with
·
1\
Symbols: OJ) = Operation
# = Number of bytes
- = Number of cycles
Table 6 Read/Modify/Write Instructions
Addressing Modes
Operations
I Mnemonic
I
Indexed
Implied(A)
Implied(X)
Direct
Indexed
(No Offset) (8-Blt Offset)
OP II
-
OP II
-
-
OP II
Increment
INC
4C
I
2
5C
I
2 3C
2
5
7C
I
5 6C
2
6
OP II
-
OP II
A + I -A or X + I -X or M + I -M
Decrement
DEC
4A
1
2 SA
I
2
3A
2
5
7A
1
5 6A 2
6
A-I -A or X-l-X or M-l-M
Clear
CLR
4F
1
2
5F
I
2
3F
2
5
7F
I
5
6F
2
6
OO-A or OO-X or OO-M
Complement
COM
43
I
2
53
I
2
33
2
5
73
I
5 63
2
6
A-A or X-X or M-M
H
I
•
•
•
•
•
•
•
•
N
Z
1\
1\
1\
0
C
•
"I •
•
1\
1\
1
1\
1\
1\
1\
,~
1\
1\
1\
I,
1\
1\
1\
0
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
•
OO-A-A or OO-X-X
Negate
NEG
40
I
2
Rotate Left Thru Carry
ROL
49
1
2 59
I
2
39
2
Rotate Right Thru Carry
ROR
46
I
2
I
2
36
2
(2'5, Complement)
Condition
Code
Boolean/Arithmetic Operation
50
56
I
2
30
2
• •
• •
70
I
5 60
2
6
or OO-M-M
5
79
I
5 69
2
6
l5t I I I I I I IboiJ
5
76
I
5
2
6
LEHb.
e
I I"H"':MI I~~ • •
5
66
Logical Shift Left
LSL
48
I
2
58
1
2
38
2
5
78
I
5 68
2
6
Logical Shift Right
LSR
44
1
2 54
I
2
34
2
5
74
1
5
64
2
6
AorXOfM
e
o.
bo
D-I I ~,,:xH I I 1-- 0 • •
0., b.I H'~":MI I...HJe • •
[fb.
:II"H~MI
110
e
I~ • •
• •
Arithmetic Shift Right
ASR
47
I
2
57
1
2
37
2
5
77
I
5
67
2
6
Arithmetic Shift Left
ASL
48
I
2
58
1
2
38
2
5
78
I
5
68
2
6
Equal to LSL
TST
40
I
2 50
I
2 3D 2
4
70
I
4 60 2
5
A-OO or X-OO or M-OO
Test for Negative
or Zero
• •
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
623
HD6305Xl,HD6305X2
Table 7 Branch Instructions
Addressing Modes
Operations
Mnemonic
Relative
OP
#
-
Branch Always
BRA
20
2
3
Branch Never
BRN
21
2
3
None
Branch IF Higher
BHI
22
2
3
C+Z=O
None
Branch IF lower or Same
BlS
23
2
3
C+Z=l
Branch IF Carry Clear
BCC
24
2
3
C=O
(Branch IF Higher or Same)
(BHS)
24
2
3
C=O
BCS
25
2
3
C=l
(BlO)
25
2
3
C=l
BNE
26
2
3
z=o
Z=l
Branch IF Carry Set
(Branch IF lower)
Branch IF Not Equal
Branch IF Equal
BEQ
27
2
3
Branch IF Half Carry Clear
BHCC
28
2
3
H=O
Branch IF Half Carry Set
BHCS
29
2
3
H=l
Branch IF Plus
BPl
2A
2
3
N=O
Branch IF Minus
BMI
2B
2
3
N=l
BMC
2C
2
3
1=0
BMS
2D
2
3
1=1
Bil
2E
2
3
INT=O
Branch IF Interrupt Mask
Bit is Set
Branch IF Interrupt Line
is low
Branch IF Interrupt Line
is High
BIH
2F
2
3
INT=l
Branch to Subroutine
BSR
AD
2
5
--
H
I
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
•
•
•
•
•
•
Branch IF Interrupt Mask
Bit is Clear
Condition Code
Branch Test
•
•
•
•
•
•
Z
C
Symbols: Op = Operation
# = Number of bytes
- =Number of cycles
Table 8 Bit Manipulation Instructions
Operations
Addressing Modes
Bit Test and
Bit Set/Clear
OP
OP
#
- BRSET n(n =0···7)
2·n
BRCLR n(n=0···7)
- - 01 +2·n
BSET n(n=0···7)
10+2·n 2 5
BClR n(n =0···7)
11 +2·n 2 5
Mnemonic
-
Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear Bit n
Boolean/
Branch
Branch Arithmetic
Test
Operation
;;
3 5
Mn=l
3 5
Mn=O
l-.Mn
- - O-.Mn
-
-
Condition Code
H
I
N
•
•
•
•
•
•
•
•
• •
• •
• • •
• • •
Symbols: Op· Operation
# • Number of bytes
- • Number of cycles
624
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
Z
C
1\
1\
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6305X1 ,HD6305X2
Table 9
Mnemonic
Operations
Control Instructions
Addressing Modes
Implied
1*
-
Transfer A to X
TAX
97
1
Transfer X to A
TXA
9F
1
2
2
OP
A-X
X-A
Set Carry Bit
SEC
99
1
1
1-C
Clear Carry Bit
Set Interrupt Mask Bit
CLC
98
1
1
O-C
SEI
98
1
1-1
Clear Interrupt Mask Bit
CLI
9A
1
Software Interrupt
SWI
83
1
Return from Subroutine
RTS
81
1
Return from Interrupt
RTI
80
1
Reset Stack Pointer
RSP
9C
1
No-Operation
NOP
90
1
2
2
10
5
8
2
1
Decimal Adjust A
Stop
Wait
Symbols: Op = Operation
# = Number of bytes
= Number of cycles
DAA
80
1
STOP
8E
1
WAIT
8F
1
2
4
4
Condition Code
Boolean Operation
0-1
$FF-SP
Advance Prog. Cnu. Only
Converts binary add of BCD charcters Into
BCD format
H
I
N
Z
C
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•1
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•1
0
1
•
?
•
•
•
•
•
A
0
•
•
•
•
?
•
•
•
•
A*
A
• Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.)
Table 10 Instruction Set (in Alphabetical Order)
Addressing Modes
Condition Code
Bit
Mnemonic
Indexed
Implied
Immediate
Direct
x
x
x
x
x
x
x
x
ADC
ADD
AND
ASl
ASR
x
x
Extended Relative (No Offset)
x
x
x
x
x
x
x
x
Indexed
Indexed
Set!
Test &
(S-Bit)
(16-Bit)
Clear
Branch
N
Z
C
x
x
x
x
x
X
1\
1\
1\
1\
X
1\
1\
1\
1\
1\
1\
•
1\
1\
1\
1\
1\
1\
x
x
BClR
x
x
x
x
x
x
x
x
BCS
BEQ
BHCC
BHCS
BHI
(BHS)
BIH
Bil
x
BIT
x
BlS
BMC
BMI
BMS
BNE
BPl
BRA
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
x
x
x
x
x
x
x
x
x
x
(BlO)
x
x
H
I
•
•
• •
x
BCC
Bit
• •
• •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
1\
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
•
• •
• •
• •
• •
• •
• •
• •
1\
•
..
(to be continued)
C
!\
•?
Carry /Borrow
Test and Set if True, Cleared Otherwise
Not Affected
load CC Register From Stack
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
625
HD6305X-1,HD6305X2
Table 10 Instruction Set (in Alphabetical Order)
Condition Code
Addressing Modes
Bit
Mnemonic
Implied
Immediate
Direct
Extended Relative
Indexed
Indexed
Indexed
Set!
Test.
(No Offset)
(8-Bit)
(16-Bit)
Clear
Branch
x
BRN
x
x
BRCLR
BRSET
x
BSET
x
BSR
CLC
CLI
CLR
x
x
x
x
x
CPX
DAA
DEC
x
x
x
x
x
x
x
x
x
x
x
x
x
EOR
INC
x
x
x
x
x
CMP
COM
x
JMP
JSR
x
x
LOA
LOX
LSL
LSR
NEG
NOP
x
x
x
x
x
ORA
RSP
x
x
x
RTI
X
RTS
x
ROL
ROR
SEI
x
x
x
x
SBC
SEC
x
x
SUB
TAX
TST
TXA
WAIT
x
x
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
626
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
STX
SWI
x
x
x
STA
STOP
Bit
x
C
/\
•
x
x
H
I
N
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•0
•
•
•
•
•
•
•0
•
•
•
•
•
•
•1
•
/\
/\
/\
/\
1
/\
/\
/\
/\
f\
/\
•
•
•
•
•
•
•
•
/\
/\
•
•0
•
•
/\
•
•
•
• • • •
• • • •
• 1\ •
•
•
/\
1\
/\
f\
/\
/\
1\
f\
1\
•
•
•
/\
/\
/\
0
1\
1\
1\
f\
1\
• •
•
•
•
• •
? ?
• •
•
•1 •
•
•
• •
•
•1
•
• •
•
• •
• •
/\
• •
•
1\
1\
/\
1\
/\
/\
1\
•
?
•
•
•
•
•
?
•
./\
/\
/\
1\
/\
1\
1\
1\
1\
Carry Borrow
Test and Set if True. Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
•
•
•
1\
•
f\
1
•
•
•
•
•
•
•
•
•
1\
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6305X1 ,HD6305X2
Table 11 Operation Code Map
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Bit Manipulation
Test &
Set/
Branch
Clear
1
0
BRSETO
BSETO
BClRO
BRClRO
BRSET1
BSET1
BRClR1
BClR1
BRSET2
BSET2
BRClR2
BClR2
BRSET3
BSET3
BRClR3
BClR3
BRSET4
BSET4
BRClR4
BClR4
BRSET5
BSET5
BRClR5
BClR5
BRSET6
BSET6
BRClR6
BClR6
BRSET7
BSET7
BRClR7
BClR7
3/5
2/5
INOTES)
Branch
Rei
2
BRA
BRN
BHI
BlS
BCC
BCS
BNE
BEQ
BHCC
BHCS
BPl
BMI
BMC
BMS
Bil
BIH
2/3
Read/Modify /Write
DIR
3
TST{-1)
2/5
Control
Register /Memory
.XO IMP IMP IMM DIR EXT .X2 .X1 .XO
7
A
D
B
E
8
9
C
F
RTI" SUB
RTS' CMP
SBC
SWI* CPX
COM
lSR
AND
BIT
ROR
lDA
TAX' ASR
STA(+l)
STA
lSl/ASl
EOR
ClC
ROl
SEC
ADC
CLI*
DEC
ORA
SEI*
ADD
RSP" .INC
JMP(-1)
TST
TST(-1) DAA" NOP BSR" JSR(+2) JSR(+1) JSR(+2)
STOP' lDX
WAIT' TXA' .STX(+l)
ClR
STX
1/2 1/2 2/6 1/5 1/* 1/1 2/2 2/3 3/4 3/5 2/4 1/3
A
4
X .X1
5
6
NEG
+--H IGH
0
1
2
3
l
o
4 W
5
6
7
8
9
A
B
C
D
E
F
1. "-" is an undefined operation c6de.
2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).
The number of cycles for the mnemonics asterisked (.) is as follows:
RTI
8
TAX
2
RTS
5
RSP
2
SWI
10
TXA
2
DAA
2
BSR
5
STOP
4
eLI
2
WAIT
4
SEI
2
3. The parenthesized numbers must be added to the cycle count of the particular instruction.
•
Additional Instructions
The follOWing new instructions are used on the HD6305X:
DAA Converts the contents of the accumulator into BCD
code.
WAIT Causes the MCV to enter the wait mode. For this mode,
see the topic, Wait Mode.
STOP Causes the MCV to enter the stop mode. For this mode,
see the topic, Stop Mode.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
627
HD6305YO,HD63A05YO,---
HD63B05YO
CMOS MCU (Microcomputer
HD6305YO is a CMOS 8-bit single-chip microcomputer
which includes a CPU upward compatible with the HD6305XO.
On the chip of the HD6305YO, 7872 byte ROM, 256 byte RAM,
55 I/O terminals, two timers and a serial communication interface (SCI) are built in. And three low power dissipation modes
(stop, wait and standby) support the low power operating.
Instruction set is upward compatible with the HD6805 family.
Unit)
HD6305YOP, HD63A05YOP,
HD63B05YOP
• HARDWARE FEATURES
.8·bit based MCU
• 7872 bytes of ROM
.256 bytes of RAM
.A total of 55 terminals, including 32 I/O's, 7 inputs and 16
outputs
• Two timers
- 8·bit timer with a 7-bit presealer (programmable presealer;
event counter)
- 15·bit timer (commonly used with the SCI clock divider)
• On-chip serial interface circuit (synchronized with clock)
.Six interrupts (two external, two timer, one serial and one
software)
• Low power dissipation_ modes
- Wait ... _ In this mode, the clock oseillator is on and the
CPU halts but the timer/serial/interrupt function is operatable.
- Stop .... In this mode, the clock stops but the RAM
data, I/O status and registers are held.
- Standby .. In this mode, the clock stops, the RAM data
is held, and the other internal condition is
reset .
• Minimum instruction cycle time
HD6305YO .... 11ls (f = 1 MHz)
- HD63A05YO .... 0.671ls (f = 1.5 MHz)
- HD63B05YO . . .. 0.51ls (f =2 MHz)
• Wide operating range
VCC 3 to 6V (f 0.1 to 0.5 MHz)
HD6305YO .... f =0.1 to 1 MHz (VCC =5V ± 10%)
- HD63A05YO .... f 0.1 to 1.5 MHz (VCC =5V ± 10%)
- HD63B05YO .... f =0.1 to 2 MHz (VCC =5V ± l()o~)
.System development fully supported by an evaluation kit
=
(DP·64S)
HD6305YOF, HD63A05YOF,
HD63B05YOF
(FP-64)
=
=
• SOFTWARE FEATURES
• Similar to HD6800
• Byte efficient instruction set
• Powerful bit manipulation instructions (Bit Set, Bit Clear, and
Bit Test and Branch usable for 192 byte RAM bits within page
o and all I/O terminals)
• A variety of interrupt operations
• Index addressing mode useful for table processing
• A variety of conditional branch instructions
• Ten powerful addressing modes
• All addressing modes adaptable to RAM, and I/O instructions
• Three new instructions, STOP, WAIT and DAA, added to the
HD6805 family instruction set
• Instructions that are upward compatible with those of Motorola's MC6805P2 and MC146805G2
628
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------HD6305YO,HD63A05YO,HD63B05YO
• PIN ARRANGEMENT
•
•
HD6305YOP, HD63A05YOP, HD63B05YOP
Vss
HD6305YOF, HD63A05YOF, HD63B05YOF
Go
0
G,
G2
GJ
G.
RES
INT
STBY
XTAL
EXTAL
NUM
TIMER
A7
Ae
As
Gs
Ga
G7
F7
Fa
Fs
F.
F3
F2
A2
A,
Ao
F,
Fo
E7
Ee
Es
Bs
B.
B3
B2
B,
Bo
CdTx
Ce/ Rx
B5
B4
B3
B2
E.
E3
E2
E,
Eo
B,
Bo
07
Oe /lNT 2
Cs/CK
Os
C.
C3
C2
C,
Co
O.
C7/Tx
Ce/Rx
03
02
uuuc3~ooooo~
0,
Vee
(Top View)
(Top View)
is
• BLOCK DIAGRAM
XTAL
EXTAl
Re'S
Accumulator
A
PortA
I/O
Terminals
Index
8
Register
x
Condition Code
Register cc
CPU
Control
0,
DI/~
~:
Port 0
03
O2
0,
Terminals
Input
Stack
SP
E,
E,
Port B
I/O
Terminals
E,
::
Es
E.
E,
Port E
Output
Terminals
Port F
Output
Terminals
Go
G,
G,
Port G
G,
G..
Go
Go
Termlnll,·
1/0
G,
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
629
HD6305YO,HD63A05YO,HD63B05YO - - - - - - - - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Supply voltage
Vee
-0.3 - +7.0
V
Input voltage
Vin
-0.3 - Vee + 0.3
V
Operating temperature
Topr
0-+70
°c
Storage temperature
Tstg
-55 - +150
°c
-
[NOTE)
These products have a protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding,
be careful not to apply any voltage higher than the absolute maximum rating to these high inpl.,lt impedance circuits. To assure normal
operation, we recommended Vln, Vout; Vss ~ (Vln or Vout ) ~ Vee .
• ELECTRICAL CHARACTERISTICS
.CC Characteristics (Vee = 5.0V ± 10%, VSS = GND and T. = 0 -+70°C unless otherwise specified)
Symbol
Item
Input
voltage
"High"
Test
condition
An,mv
EXTAL
VIH
All Input
Input
leakage
current
~D?,
Threestate
current
Ao- A7,
8 0 - B7,
Co - C7,
Go -G 7,
Eo-E7**
Fo - F7**
Input
capacity
All
terminals
Vee- 0.5
-
Vee+ 0.3
V
Vee+ 0.3
V
Vee+ 0.3
V
0.8
V
6
10
mA
-0.3
Icc
-
f = 1MHz*
Standby
TIMER,
TfJT,
Unit
VIL
Wait
Stop
'max
2.0
Operating
Current
dissipation
typ
Vee x 0.7
Others
Input voltage "Low"
min
IIILI
2
5
mA
2
10
p.A
2
10
p.A
-
-
1
p.A
-
-
1
p.A
-
-
12
pF
Vin = 0.5IITSII
Cin
Vee - 0.5V
=1MHz,
Vin =OV
f
• The value It f - xMHz can be calculated by the following equation:
standby mode
ICC (f • xMHz) .. ICC (f • 1MHz) multiplied by x
.. A t
630
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------HD6305YO,HD63A05YO,HD63B05YO
• AC Characteristics (Vee = 5.0V ± 10%, Vss = GND and T.
Item
HD6305YO
Test
condition
Symbol
= 0 - +70o C unless otherwise specified)
min
typ
-
Clock
frequency
fel
0.4
Cycle time
HD63A05YO
HD63B05YO
max
min
typ
4
0.4
10
0.666
-
-
tcyc
+200
max
min
typ
6
0.4
-
Unit
max
8
MHz
10
Ils
-
ns
teye
1.0
INT pulse
width
tlWL
+2 0
tc~c
-
-
teye
+200
INT2 pulse
width
tlWL2
teye
+250
-
-
tcye
+200
-
-
teye
+200
-
-
ns
RES pulse
width
tRwL
5
-
-
5
-
-
5
-
-
tcyc
teye
+200
-
-
teye
+200
-
-
ns
-
-
20
-
-
20
ms
80
-
-
80
-
-
ms
TIMER pulse
width
tTWL
Oscillation
start time
(crystal)
tose
Reset delay
time
tRHL
tcyc
+250
-
-
CL = 22pF ±
200/6
Rs = 60n
max
-
-
20
External cap.
2.21lF
80
-
-
• Port Electrical Characteristics (Vee
=5.0V ± 10%, VSS =GND and Ta =0 -
Item
Symbol
Output volt·
age "Low"
Ports A,
B,C, D,
G
-
-
V
-
-
0.55
V
VIH
2.0
-
Vee + 0.3
V
VIL
- 0.3
-
0.8
V
-1
-
1
IlA
Symbol
Clock Cycle
tScyc
Data Output Delay Time
tTXD
Data Set·up Time
tSRX
Data Hold Time
tHRx
Unit
-
IOL
= 1.6mA
Vin = 0.5Vee - 0.5V
= 5.0V±10%, Vss =GND and Ta = 0 -
Item
max
2.4
IlL
(Vee
typ
Vee - 0.7
VOL
Input leak·
age current
• SCI Timing
=-2OOIlA
IOH = -101lA
Input volt·
age "High"
Input volt·
age "Low"
min
VOH
Ports A,
B,C,G,
E,F
0.5
+70°C unless otherwise specified)
Test
condition
IOH
Output volt·
age "High"
10
Test
Condition
Fig. 1,
Fig. 2
V
+70°C unless otherwise specified)
HD63A05YO
HD6305YO
min
typ
1
-
32768 0.67
200
-
100
-
-
max
250
HD63B05YO
Unit
typ
max
min
typ
max
21845
0.5
Ils
-
250
ns
-
200
-
16384
250
200
-
100
-
-
100
-
-
ns
ns
min
-
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
631
HD6305YO,HD63A05YO,HD63B05YO - - - - - - - - - - - - - - - - - - - - - -INT,INT2
External interrupt request inputs to the HD6305YO. For
details, refer to "INTERRUPTS". The INT2 terminal is also
used as the port D6 tenninal.
Clock Output
Co/CK
Data Output
- XTAL, EXTAL
These terminals provide input to the on-chip clock circuit.
A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic
fdter is connected to the terminal. Refer to "INTERNAL
OSCILLATOR" for using these input terminals.
C7/TX
Oat8 Input
C./RX
-TIMER
This is an input terminal for event counter. Refer to
"TIMER" for details.
Figure 1 SCI Timing (Internal Clock)
Clock Input
-RES
Used to reset the MCU. Refer to "RESET" for details.
o.sv
CO/CK
~~++----------\r_----~~
Data Output
C7/TX
~~++---------J~----~'~
tSAX
2.0V
Data Input
C"RX
______JPO~.SV~________~~r~----~~
Figure2 SCI Timing(External Clock)
Vcc
TTL Load
(Portl
~~~r,:~to-
IOL= 1.6mA
-Input/Output Terminal. (Ao - A7, Bo - B7, Co - C7, Go G'd
These 32 terminals consist of four 8-bit I/O ports (A, B, C,
G). Each of them can be used as an input or output terminal
on a bit through program control of the data direction register.
For details, refer to "I/O PORTS."
-Input Terminals (01 - 07)
These seven input-only terminals are TTL or CMOS compatible. Of the port D's, D, is also used as INT2. If D, is
used as a port, the INT2 interrupt mask bit of the miscellaneous register must be set to ~'I" to prevent an INT2 interrupt
fro'm being accidentally accepted.
2.4kQ
____-.____~~--~~~
12kQ
40pF
-NUM
This terminal is not intended for user applications. It must
be grounded to Vss.
- Output Terminal. (Eo - E7, Fo - F7)
These 16 output-only terminals are TTL or CMOS com·
patible .
[NOTES 1 1. Tha load capacitance in cludes stray capecitanca caused
by the probe. etc.
2. All diodes are 1S2074
®.
Figure 3 Test Load
• DESCRIPTION OF TERMINAL FUNCTIONS
The input and output signals of the HD630SYO are described
here.
eVee, Vss
Voltage is applied to the HD6305YO through these two
terminals. Vee is 5.0V ± 10%, while Vss is grounded.
• STBV
This terminal is used to place the MCU into the standby
mode. With STBY at "Low" level, the oscillation stops and
the internal condition is reset. For details, refer to "Standby
Mode."
The terminals described in the following are I/O pins for
serial communication interface (SCI). They are also used as
ports Cs , C6 and C7 • For details, refer to "SERIAL COM·
MUNICATION INTERFACE."
-CK (Cs)
Used to input or output clocks for serial operation.
- Rx (C,)
Used to receive serial data.
-Tx (C7)
Used to transmit serial data.
632
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - HD6305YO,HD63A05YO,HD63B05YO
-REGISTERS
-MEMORY MAP
There are five registers which the programmer can operate.
The memory map of the HD6305YO MCU is shown in
Fig. 4. During interrupt processing, the contents of the MCU
registers are saved into the stack in the sequence shown in
Fig. 5. This saving begins with the lower byte (PCL) of the
program counter. Then the value of the stack pointer is
decremented and the higher byte (pC H) of the program
counter, index register (X), accumulator (A) and condition
code register (CC) are stacked in that order. In a subroutine
call, only the contents of the program counter (pCH and PCL)
are stacked.
o
7
A _ _ _ _....1Accumulator
......_ _ _ _
I
7
o
Index
I......_ _ _ _X _ _ _ _....IReglster
13
o
Program
PC_ _ _ _ _ _ _.... Counter
'--_ _ _ _ _ _ _
13
6 5
0
I
I
_--""I ~~~;;~r
1L,.0__1L,.0. .&. 01......1__
01L,.0.L.10......1_1...&..1_1L,.I_ _S_P
o
63
64
0
1
2
3
4
5
6
7
B
9
10
11
12
13
$0000
I/O Ports
Timer
SCI
$003F
$0040
RAM
(192Bytes)
Stack
255
$gOFF
256
$ 100
RAM
(64Bytes)
$013F
319
$0140
320
\
ROM
(7,872Bytes)
PORT A
PORT B
PORT C
PORT 0
PORT A DDR
PORT BOOR
PORT C DDR
PORT G DDR
Timer Data Reg
Timer CTRL Reg
MISC Reg
PORT E
PORT F
PORT G
$00
$01
$02
$03""
$04"
$05"
$06"
'-----Negative
'------Interrupt
Mask
'-------Half
Carry
Figure 6
Programming Model
• Accumulator (A)
This accumulator is an ordinary 8-bit register which holds
operands or the result of arithmetic operation or data processing.
• Index Register (X)
Not Used
$3F
63
$3FFF
Figure 4
~gg~"
Zero
sor
Not Used
16383
Code
L..r-L..,,"","-r""L-r..a....,...J Register
$08
$09
$OA
SOB
SOC
$00
Not Used
16 SCI CTRL Reg $10
17 SCI STS Reg $11
18 SCI Data Reg $12
8182 ~---------Interrupt $1FF6
Vectors
$1FFF
8191
8192
$2000
r--r--r--,r---r--, Condition
* Write only regis ter
** Read only regis ter
Memory Map of H06305YO MCU
The index register is an 8-bit register, and is used for index
addressing mode. Each of the addresses contained in the
register consists of 8 bits which, combined with an offset
value, provides an effective address.
In the case of a read/modify/write instruction, the index
register can be used like an accumulator to hold operation
data or the result of operation.
If not used in the index addressing mode, the register can
be used to store data temporarily.
• Program Counter (PC)
The program counter is a 14-bit register that contains the
address of the next instruction to be executed.
I
7 6 543 2 1 0
Condition
n-4 1 1 1
n+1
Code Register
n-3
Accumulator
n+2
n-2
Index Register
n+3
n-1
n
o oj
PCW
PCl"
Pull
• Stack Pointer (SP)
The stack pointer is a 14-bit register that indicates the address of the next stacking space. Just after reset, the stack
pointer is set at address $OOFF. It is decremented when data
is pushed, and incremented when pulled. The upper 8 bits
of the stack pointer are fIXed to 00000o 11. During the MCU
being reset or during a reset stack pointer (RSP) instruction,
the pointer is set to address $OOFF. Since a subroutine or
interrupt can use space up to address $OOCI for stacking, the
subroutine can be used up to 31 levels and the interrupt up
to 12 levels.
n+4
n+5
Push
* In a subroutine call, only PCL and PCH are stacked.
Figure 5 Sequence of Interrupt Stacking
• Condition Code Register (CC)
The condition code register is a 5-blt register, each bit
indicating the result of the instruction just executed. The
bits can be indiVidually tested by conditional branch instruc-
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
633
HD6305YO,HD63A05YO,HD63B05YO - - - - - - - - - - - - - - - - - - - - tions. The CC bits are as follows:
Half Carry (H): Used to indicate that a carry occurred between bits 3 and 4 during an arithmetic operation (ADD, ADC).
Interrupt (I): Setting this bit causes all interrupts, except
a software interrupt, to be masked. If an
interrupt occurs with the bit I set, it is
latched. It will be processed the instant
the interrupt mask bit is reset. (More specifically, it will enter the interrupt processing
routine after the instruction following the
CLI has been executed.)
Negative (N): Used to indicate that the result of the most
recent arithmetic operation, logical operation
or: data processing is negative (bit 7 is logic
"I").
Used to indicate that the result of the most
Zero (Z):
recent arithmetic operation, logical operation
or data processing is zero.
Represents a carry or borrow that occurred
Carry!
Borrow (C): in the most recent arithmetic operation. This
bit is also affected by the Bit Test and Branch
instruction and a Rotate instruction.
-INTERRUPT
There are six different types of interrupt: external interrupts (INT, INTi), internal timer interrupts (TIMER,
TIMER2), seridl interrupt (SCI) and interrupt by an instruction (SWI).
Of these six interrupts, the INT2 and TIMER' or the SCI
and TIMER2 generate the same vector address, respectively.
When an interrupt occurs, the program in progress stops
and the then CPU status is saved onto the stack. And then,
the interrupt mask bit (I) of the condition code register is
set and the start address of the interrupt processing routine
is obtained from a particular interrupt vector address. Then
the interrupt routine starts from the start address. System
can exit from the interrupt routine by an RTI instruction.
When this instruction is executed, the CPU status before
the interrupt (saved onto the staCk) is pulled and the CPU
restarts the sequence with the instruction next to the one at
which the interrupt occurred. Table 1 lists the priority of
interrupts and their vector addresses.
Table 1
Interrupt
Priority
Vector Address
m
1
$lFFE,
$lFFF
SWI
2
$lFFC,
$lFFD
INT
3
$lFFA,
$lFFB
TIMER/INT2
4
$lFFS,
$lFF9
SCI/TIMER2
5
$lFF6,
$lFF7
A flowchart of the interrupt sequence is shown in Fig. 7.
A block diagram of the interrupt request source is shown in
Fig. 8.
y
/NT
y
iNf2
y
1-1
$FF-SP
O-OOR'S
CLR iN'f Logic
SFF-TOR
$7F-Timer Prescaler
$50-TCR
S3F-SSR
$OO-SCR
S7F-+MR
TIMER
y
Figure 7
634
Priority of Interrupts
SCI
Interrupt Flowchart
_HITACf!1
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - HD6305YO,HD63A05YO,HD63B05YO
In the block diagram, both the external interrupts INT and
INn are edge trigger inputs. At the falling edge of each input,
an interrupt request is generated and latched. The INT interrupt request is automatically cleared if jumping is made to
the INT processing routine. Meanwhile, the INT2 request is
cleared if "0" is written in bit 7 of the miscellaneous register.
For the external interrupts (INT, INT2), internal timer
interrupts (TIMER, TIMER2) and serial interrupt (SCI), each
interrupt request is held, but not processed, if the I bit of the
condition code register is set. Immediately after the I bit is
cleared, the corresponding interrupt processing starts according to th~ority.
The INT2 interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by setting bit 6
of the timer control register; the SCI interrupt by setting bit
5 of the serial status register; and the TIMER2 interrupt by
setting bit 4 of the serial status register.
The status of the INT terminal can be tested by a BIL or
BIH instruction. The INT falling edge detector circuit and
its latching circuit are independent of testing by these instructions. This is also true with the status of the INT2 terminal.
Bit 7 of this register is the INT2 interrupt request flag.
When the falling edge is detected at the INT2 terminal, "I"
is set in bit 7. Then the software in the interrupt routine
(vector addresses: $lFF8, $lFF9) checks bit 7 to see if it
is INT2 interrupt. Bit 7 can be reset by software.
Miscellaneous Register (MR;$OOOA)
7
S
fI
f
543210
IMR71MRsIZIZIZIZVIZI
-
INT2 Interrupt Mask
' - - - - - - - - - - - - - INT2 Interrupt Request Flag
Bit 6 is the INT2 interrupt mask bit. If this bit is set to "I",
then the INT2 interrupt is disabled. Both read and write are
possible with bit 7 but "1" cannot be written in this bit by
software. This means that an interrupt request by software
is impossible .
When reset, bit 7 is cleared to "0" and bit 6 is set to "1".
• Miscellaneous Register (MR; $OOOA)
The interrupt vector address for the external interrupt
INT2 is the same as that for the TIMER interrupt, as shown
in Table 1. For this reason, a special register called the miscellaneous register (MR; $OOOA) is available to control the
INTi interrupts.
-TIMER
Figure 9 shows an MCU timer block diagram. The timer
data register is loaded by software and, upon receipt of a
clock input, begins to count down. When the timer data
Vectoring generated
$1 FFA. $1 FFB
BIH/BIL Test
Condition Code Register ICC)
TNT Interrupt Latch
INT
I
Falling Edge Detector
1
"}---4......-r----
Vectoring generated
$lFF8. $lFF9
TIMER
Serial Status
Register (SSR)
SCI/TIMER2
>----<......- - - Vectoring generated
$lFF6. $lFF7
Figure 8
Interrupt Request Generation Circuitry
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
635
HD6305YO,HD63A05YO,HD63B05YO - - - - - - - - - - - - - - - - - - - - - register (TDR) becomes "0", the timer interrupt request
bit (bit 7) in the timer control register is set. In response to
the interrupt request, the MCV saves its status into the stack
and fetches timer interrupt routine address from addresses
$1 FF8 and $1 FF9 and execute the interrupt routine. The
timer interrupt can be masked by setting the timer interrupt
mask bit (bit 6) in the timer control register. The mask bit
(I) in the condition code register can also mask the timer
interrupt.
The source clock to the timer can be either an external
signal from the timer input terminal or the internal E signal
(the oscillator clock divided by 4). If the E signal is used as
the source, the clock input can be gated by the input to the
timer input terminal.
Once the timer count has reached "0", it starts counting
down with "$FF". The count can be monitored whenever
desired by reading the timer data register. This permits the
program to know the length of time having passed after the
occurrence of a timer interrupt, without disturbing the contents of the counter.
When the MCV is reset, both the prescaler and counter are
initialized to logic "1". The timer interrupt request bit
(bit 7) then is cleared and the timer interrupt mask bit (bit
6) is set.
To clear the timer interrupt request bit (bit 7), it is necessary to write "0" in that bit.
• Timer Control Register (TCR, $0009)
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
Timer Control Register (TCR; $0009)
4
3
' - - - - - - - - - - - - Timer interrupt mask
' - - - - - - - - - - - - - - - Timer interrupt request
After reset, the TCR is initialized to "E under timer terminal control" (bit 5 = 0, bit 4 = 1). If the timer terminal is
"I", the counter starts counting down with "$FF" immediately after reset.
When "1" is written in bit 3, the prescaler is initialized.
This bit always shows "0" when read.
Table 2
TCRl
Timer interrupt request
o
Absent
o
TCR
Clock Source Selection
Clock input source
Bit 5
Bit 4
0
0
I nternal clock E
0
1
E under timer terminal control
Enabled
1
0
No clock input (counting stopped)
Disabled
1
1
Event input from timer terminal
Present
Timer interrupt mask
TCR6
o
Initialize
(Internal
Clock)
E ----"1---1
Timer Data
Register
------r-----.,.----J
Write
Figure 9
636
Timer Interrupt
Read
Timer Block Diagram
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - H D6305YO,HD63A05YO,HD63B05YO
A prescaler division ratio is selected by the combination of
three bits (bits 0, 1 and 2) of the timer control register (see
Table 3). There are eight different division ratios: +1, +2,74,
+8, +16, +32, +64 and +128. After reset, the TCR is set to the
+1 mode.
A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "1". When a timer
interrupt occurs, "1" is set in the timer interrupt request bit.
This bit can be cleared by writing "0" in that bit.
-SERIAL COMMUNICATION INTERFACE (SCII
Table 3
This interface is used for serial transmission or reception
of 8-bit data. Sixteen transfer rates are available in the range
from 1 p.s to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one eighth counter and
one prescaler. (See Fig. 10.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 5,
6 and 7 of port C. Described below are the operations of
each register and data transfer.
Prescaler Division Ratio Selection
TCR
Bit 2
Bit 0
Bit 1
Prescaler division ratio
0
0
0
+1
0
0
1
+2
0
1
0
+4
a
1
1
+8
1
0
0
+16
1
0
1
+32
1
1
0
+64
1
1
1
-;.-128
-SCI Control Register (SCR; $0010)
SCI Control Registers (SCR; $0010)
E
I"u{f--,
L-....-...J...........~
Transfer
Clock
Generator
Cs(CK) :
I
I
I
I
I
I
Initialize
I
I
C6(Rx)
---.:
I
C7~
L _____ _
I
SCI Status Registers
(SSR :$0011)
Not Used
SCI TIMER2
Figure 10
SCI Block Diagram
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
637
HD6305YO,HD63A05YO,HD63B05YO - - - - - - - - - - - - - - - - - - - - Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completion of transmitting or receiving 8-bit data. It is
cleared when reset or data is written to or read from the
SCI data register with the SCRS=" I". The bit can also be
cleared by writing "0" in it.
C7 terminal
SCR7
o
Used as I/O terminal (by DOR).
Serial data output (OOR output)
C6 terminal
SCR6
o
Bit 6 (SSR6)
Bit 6 is the TIMER2 interrupt request bit. TIMER2 is used
commonly with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When reset, the
bit is cleared. It also be cleared by writing "0" in it. (For
details, see TIMER2')
Used as I/O terminal (by DDR).
Serial data input (DDR input)
SCR5 SCR4
Clock source
Cs terminal
-
0
0
0
1
1
0
Internal
Clock output (DDR output)
1
1
External
Clock input (DDR input)
Bit S (SSRS)
Bit S is the SCI interrupt mask bit which can be set or
cleared by software. When it is "1", the SCI interrupt (SSR7)
is masked. When reset, it is set to "1".
Used as I/O terminal (by
DDR).
Bit 4 (SSR4)
Bit 4 is the TIMER2 interrupt mask bit which can be set
or cleared by 'software. When the bit is "1", the TIMER,
interrupt (SSR6) is masked. When reset, it is set to "1"
Bit 7 (SCR7)
When this bit is set, the DDRcorresponding to the C7
becomes "1" and this terminal serves for output of SCI data.
After reset, the bit is cleared to "0".
Bit 6 (SCR6)
When this bit is set, the DDR corresponding to the C6
becomes "0" and this terminal serves for input of SCI data.
After reset, the bit is cleared to "0" .
Bits 5 and 4 (SCRS, SCR4)
These bits are used to select a clock source. After reset,
the bits are cleared to "0".
Bits 3 - 0 (SCR3 .... SCRO)
These bits are used to select a transfer clock rate. After
reset, the bits are cleared to "0".
Transfer clock rate
4.00 MHz
4.194 MHz
Bit 3 (SSR3)
When "I" is written in this bit, the prescaler of the transfer
clock generator is initialized. When read, the bit always is "0".
Bits 2 .... 0
Not used.
SSR7
o
SSR6
o
SCR1
SCRO
0
0
0
0
11-'s
0.951-'5
0
0
0
1
21-'5
1.911-'5
0
0
1
0
41-'s
3.821-'5
0
0
1
1
81-'5
7.641-'5
SSR4
I
I
I
I
I
I
o
1
1
1
1
327681-'5
1/32 s
SSR5
o
Absent
SCI interrupt mask
Enabled
Disabled
TIMER2 interrupt mask
Enabled
Disabled
eSCI DltII RIIIStlir 'SDR;$OO12)
A _rial-parallel conversion register that is used for transfer
638
TIMER, interrupt request
Present
SCR2
eSCI Satus Attlltlr 'SSA; $0011)
Absent
Present
SCR3
ofd.ta.
SCI interrupt request
• Data Transmission
By writing the desired control bits into the SCI control
registers, a transfer rate and a source of transfer clock are
determined and bits 7 and S of port C are set at the serial
data output terminal and the serial clock terminal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data
written in the SCI data register is output from the C7 /Tx
terminal, starting with the LSB, synchronously with the
falling edge of the serial clock. (See Fig. 11.) When 8 bits of
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD6305YO,HD63A05YO,HD63B05YO
data have been transmitted, the interrupt request bit is set in
bit 7 of the SCI status register with the rising edge of the
last serial clock. This request can be masked by setting bit 5
of the SCI status register. Once the data has been sent, the 8th
bit data (MSB) stays at the C7/Tx terminal. If an external
clock source has been selected, the transfer rate determined by
bits 0 - 3 of the SCI control register is ignored, and the Cs /
CK terminal is set as input. If the internal clock has been
selected, the Cs /CK terminal is set as output and clocks are
output at the transfer rate selected by bits 0 - 3 of the SCI
con trol register.
Figure 11 SCI Timing Chart
• Data Reception
By writing the desired control bits into the SCI control
register, a transfer rate and a source of transfer clock are determined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock terminal, respectively.
Then dummy-writing or -reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed after reading subsequent received data_ It must be taken
after reset and after not reading subsequent received data_)
The data from the C6 /Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig. 11). When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bit 5
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0 -- 3 of the SCI
control register is ignored and the data is received synchronously with the clock from the C s /CK terminal. If the internal
clock has been selected, the Cs/CK terminal is set as output
and clocks are output at the transfer rate selected by bits 0 -3 of the SCI control register.
TIMER2 is commonly used with the SCI transfer clock
generator. If wanting to use TIMER2 independently of the
SCI, specify "External" (SCRS = 1, SCR4 = 1) as the SCI
clock source.
If "Internal" is selected as the clock source, reading or
writing the SDR causes the prescaler of the transfer clock
generator to be initialized.
-I/O PORTS
There are 32 input/output terminals (ports A, B, C, G).
Each I/O terminal can be selected for either input or output
by the data direction register. More specifically, an I/O port
will be input if "0" is written in the data direction register,
and output if "1" is written in the data direction register.
Port A, B or C reads latched data if it has been programmed
as output, even with the output level being fluctuated by the
output load. (See Fig. 12-a.) For port G, in such a case, the
level of the pin is always read when it is read. (See Fig. 12-b.)
This implies that, even when "1" is being output, port G may
read "0" if the load condition causes the output voltage to
decrease to below 2 .OV .
When reset, the data direction register and data register go
to "0" and all the input/output terminals are used as input.
.TIMER2
The SCI transfer clock generator can be used as a timer.
The clock selected by bits 3 -- 0 of the SCI control register
(4 JJ.S - approx. 32 ms (for oscillation at 4 MHz)) is input to
bit 6 of the SCI status register and the TIMER2 interrupt
request bit is set at each falling edge of the clock. Since interrupt requests occur periodically, TIMER2 can be used as a
reload counter or clock_
CD
Bit of
output
data
Status of
output
Input to
CPU
1
0
0
0
1
1
0
X
1
3-state
1
Pin
a. Ports A, Band C
®@...--__@;:;;,4@
----'
-----LJ.-----~t
CD
Bit of data
direction
register
L
:Transfer
clock generator is reset and mask bit (bit 4
of SCI status register! is clea red.
®.@ : TIMER2 interrupt request
®.@ : T1MER2 interrupt request bit cleared
b. Port G
Figure 12
Input/Output Port Diagram
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
639
HD6305YO,HD63A05YO,HD63B05YO - - - - - - - - - - - - - - - - - - - - - There are 16 output-only terminals (ports E and F). Each
of them can also read. In this case, latched data is read even
with the output terminal level being fluctuated by the output
load (as with ports A, B and C).
When reset, "Low" level is output from each output terminal.
Seven input-only terminals are available (port D). Writing
to an input terminal is invalid.
All input/output terminals, output terminals and input
terminals are TTL compatible and CMOS compatible in respect of both input and output.
If I/O ports or input ports are not used, they should be
connected to VSS via resistors. With none connected to these
terminals, there is the possibility of power being consumed
despite that they are not used.
I--~_-l EXTAL
JO~8:0MHz=
XTAl H06305YO
MCU
10-22pF±20%
Crystal Oscillator
HD6305YO
-RESET
The MCU can be reset either by external reset input (RES)
or power-on reset. (See Fig. 13.) On power up, the reset
input must be held "Low" for at least 30 ms to assure that the
internal oscillator is stabilized. A sufficient time of delay can
be obtained by connecting a capacitance to the RES input as
shown in Fig. 14.
MCU
External
Ceramic Oscillator
Clock
Input
EXTAL
NC
XTAL HD6305YO
MCU
5V
Vcc
OV-------'
External Clock Drive
An
Terminal
~::~81
---------1""
__________
Figure 13
Figure 15
C,
~
~~
Power On and Reset Timing
XTAL~~EXTAL
Figure 16
100kO typ
HD6305YO
Parameters of Crystal
Input Reset Delay Circuit
-INTERNAL OSCILLATOR
The internal oscillator circuit is designed to meet the
requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 - 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the required oscillation frequency stability.
Three different terminal connections are shown in Fig. 15.
Figs. 16 and 17 illustrate the specifications and typical arrangement of the crystal, respectively.
640
AT Cut
Parallel
Resonance
Co=7pF max.
f=2.0-S.0MHz
Rs=600 max.
(a)
MCU
Figure 14
Internal Oscillator Circuit
[NOTE 1 Use as short wirings as possible for connection of the crystal
with the EXT AL and XTAL terminals. Do not allow these
wirings to cross others.
Figure 17
Typical Crystal Arrangement
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - HD6305YO,HD63A05YO,HD63B05YO
-LOW POWER DISSIPATION MODE
The HD6305YO has three low power dissipation modes:
wait, stop and standby.
.Wait Mode
When WAlI instruction being executed, the MCU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication interface - stay active. (NOTE: Once the system has entered the
wait mode, the serial communication interface can no longer
be retriggered.) In the wait mode, the registers, RAM and I/O
terminals hold their condition just before entering into the
wait mode.
The escape from this mode can be done by interrupt (INT,
TIMER/INT2 or SCI/TIMER2), RES or STBY. The RES
resets the MCU and the STBY brings it into the standby
mode. (This will be mentioned later.)
When interrupt is requested to the CPU and accepted. the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit of the condition code register, after releasing from the wait mode the MCU executes the instruction
next to the WAIT. If an interrupt other than the INT (Le.,
TIMER/INT2 or SCI/TIMER2) is masked by the timer control
register, miscellaneous register or serial status register, there
is no interrupt request to the CPU, so the wait mode cannot
be released.
Fig. 18 shows a flowchart for the wait function.
• Stop Mode
When STOP instruction being executed, MCU enters into
the stop mode. In this mode, the oscillator stops and the CPU
and peripheral functions become inactive but the RAM,
registers and I/O terminals hold their condition just before
entering into the stop mode.
The escape from this mode can be done by an external
interrupt (INT or INT2), RES or STBY. The RES resets the
MCU and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted,
the stop mode escapes, then the CPU is brought to the operation mode and vectors to the interrupt routine. If the interrupt is masked by the I bit of the condition code register,
after releasing from the stop mode, the MCU executes the
instruction next t~ the STOP. If the INT2 interrupt is masked
by the miscellaneous register, there is no interrupt request to
the MCU, so the stop mode cannot be released.
Fig. 19 shows a flowchart for the stop function. Fig. 20
shows a timing chart of return to the operation mode from
the stop mode.
For releasing from the stop mode by an interrupt, oscillation starts upon input of the interrupt and, after the internal
delay time for stabilized oscillation, the CPU becomes active.
For restarting by RES, oscillation starts when the RES goes
"0" and the CPU restarts when the RES goes "1". The duration of RES="O" must exceed 30 ms to assure stabilized oscillation.
• Standby Mode
The MCV enters into the standby mode when the STBY
terminal goes "Low". In this mode, all operations stop and
the internal condition is reset but the contents of the RAM are
hold. The I/O terminals turn to high-impedance state. The
standby mode should escape by bringing STBY "High". The
CPU must be restarted by reset. The timing of input signals
at the RES and STBY terminals is shown in Fig. 21 .
Table 4 lists the status of each parts of the MCU in each
low power diSSipation modes. Transitions between each mode
are shown in Fig. 22.
(Note)
When I bit of condition code register is "1" and interrupt
(INT, TIMER/INT 2, SCI/TIMER 2) is held, MCU does not enter
WAIT mode by the execution of WAIT instruction.
In that case, after the 4 dummy cycles MCU executes the
next instruction.
In the same way, when external interrupts (INT, INT 2) are
held at the bit I set, MCU does not enter STOP mode by the
execution of STOP instruction. In that case, also, MCU executes
the next instruction after the 4 dummy cycles.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
641
HD6305YO,HD63A05YO,HD63B05YO - - - - - - - - - - - -_ _ _ _ _ _ _ _ __
Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop
Initialize
CPU, TIMER, SCI.
I/O and All
Other Functions
No
No
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 18
642
Wait Mode Flow Chart
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - ' - - - - - - - - - - - - - - HD6305YO, H D63A05YO,HD63B05YO
Oscillator and
All Clocks Stop.
No
Turn on Oscillator
Wait for Time Delay
to Stabilize
Turn on Oscillator
Wait for Time Delay
to Stabilize
1=0
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 19
Stop Mode Flow Chart
$HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
643
HD6305YO,HD63A05YO,HD63B05YO - - - - - - - - - - - - - - . . , - - - - - - - - -
om":to.~,:~~~\~~~~
I
Time required for oscillation to become
stabilized (built-in delay time)
Interrupt
STOP instruction
executed
restart
(a) Restart by Interrupt
Oscillator
E
III111111111111111111111111 II
~,}----+_--'
t
Time required for oscillation to become
stabilized (tos e )
STOP instruction
executed
Reset
start
(b) Restart by Reset
Figure 20
Timing Chart of Releasing from Stop Mode
\
I
H
,
RES
I
I
I
I
I
I
I
'-_.&_-'---
\
tosc
Figure 21
Table 4
Restart
Timing Chart of Releasing from Standby Mode
Status of Each Part of MCU in Low Power Dissipation Modes
Condition
Mode
WAIT
-
Start
Soft·
ware
STOP
Stand·
by
644
Hard·
ware
Escape
CPU
Timer,
Serial
Register
RAM
1/0
terminal
Active
Stop
Active
Keep
Keep
Keep
STBY, RES, INT, INi l ,
each interrupt request of
TIMER, TIMER 2 , SCI
STOP in·
struction
Stop
Stop
Stop
Keep
Keep
Keep
STBY, RES, INT, INTl
STBY="Low"
Stop
Stop
Stop
Reset
Keep
High impedance
Oscillator
WAIT instruction
STBY="High"
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - H D6305YO,H D63A05YO,H D63B05YO
Figure 22
Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset
-BIT MANIPULATION
The HD6305YO MCV can use a single instruction (BSET
or BCLR) to set or clear one bit of the RAM within page 0 or
an I/O port (except the write-only registers such as the data
direction register). Every bit of memory or I/O within page 0
(SOO ,.." SFF) can be tested by the BRSET or BRCLR instruction; depending on the result of the test, the program can
branch to required destinations. Since bits in the RAM on page
0, or I/O can be manipulated, the user may use a bit within the
RAM on page 0 as a flag or handle a single I/O bit as an
independent I/O terminal. Fig. 23 shows an example of bit
manipulation and the validity of test instructions. In the
example, the program is configured assuming that bit 0 of port
A is connected to a zero cross detector circuit and bit I of the
same port to the trigger of a triac.
The program shown can activate the triac within a time of
lOllS from zero-crossing through the use of only 7 bytes on
the ROM. The on-chip timer provides a required time of
delay and pulse width mudulation of power is also possible.
j
SELF 1.
Figure 23
BRCLR 0, PORT A, SELF 1
BSET 1, PORT A
BClR 1, PORT A
Example of Bit Manipulation
-ADDRESSING MODES
Ten different addressing modes are available to the
HD6305YO MCV.
elmmediate
See Fig. 24. The immediate addressing mode provides
access to a constant which does not vary during execution of
the program.
This access requires an instruction length of 2 bytes. The
effective address (EA) is PC and the operand is fetched from
the byte that follows the operation code.
e Direct
See Fig. 25. In the direct addressing mode, the address of
the operand is contained in the 2nd byte of the instruction.
The user can gain direct access to memory up to the lower
255th address. 192 byte RAM and I/O registers are on page 0
of address space so that the direct addressing mode may be
utilized.
eExtended
See Fig. 26. The extended addressing is used for referencing to all addresses of memory. The EA is the contents of
the 2 bytes that follow the operation code. An extended
addressing instruction requires a length of 3 bytes.
e Relative
See Fig. 27. The relative addressing mode is used with
branch instructions only. When a branch occurs, the program
counter is loaded with the contents of the byte following the
operation code. EA = (PC) + 2 + ReI., where ReI. indicates a
signed 8-bit data following the operation code. If no branch
occurs, ReI. = O. When a branch occurs, the program jumps
to any byte in the range + 129 to -127. A branch instruction
requires a length of 2 bytes.
elndexed (No Offset)
See Fig. 28. The indexed addressing mode allows access
up to the lower 255th address of memory. In this mode, an
instruction requires a length of one hyte. The EA is the
contents of the index register.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
645
HD6305YO,HD63A05YO,HD63B05YO - - - - - - - - - - - - - - - - - - - - - elndexed (8-bit Offset!
See Fig. 29. The EA is the contents of the byte following the operation code, plus the contents of the index register.
This mode allows access up to the lower 511 th address of
memory: Each instruction when used in the index addressing
mode (8-bit offset) requires a length of2 bytes.
elndexed (1S-bit Offset!
See Fig. 30. The contents of the 2 bytes following the
operation code are added to content of the index register
to compute the value of EA. In this mode, the complete
memory can be accessed. When used in the indexed addressing mode (16-bit offset), an instruction must be 3 bytes long.
e Bit Set/Clear
See Fig. 31. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
o. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte that follows the operation code
indicates an address within page O.
e Bit Test and Branch
See Fig. 32. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. Individual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relative value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code register.
elmplied
See Fig. 33. This mode involves no EA. All information
needed for execution of an instruction is contained in the
operation code. Direct manipulation on the accumulator
and index register is included in th.e implied addressing mode.
Other instructions such as SWI and RTI are also used in this
mode. All instructions used in the implied addressing mode
should have a length of one byte.
~~~__~tA~~
/
Memory
I
Fa
Index Reg
I
Stack Point
PROG LOA II SFa
05aEl=~~:::t------.-J
05BF
Prog Count
05CO
CC
'-"';';~-4
~
I
I
Figure 24
Example of Immediate Addressing
Memory
CAT FCB 32 004B
t::J1c::i---t----QQf~---~iA~~2~O~J
Index eg
Stack
PROG LOA CAT 052D~::!!t::::I--.-I
052E ..
.
8
!.
.
cc
!.
Figure 25
646
""~o,...'n,..,.t--...
Prog lount
052F
Example of Direct Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - HD6305YO,HD63A05YO,HD63B05YO
Memory
,
~
0000
A
40
PROG LOA CAT ~:~!I-~;--L
Index Reg
I
040BI-....;;"-_r
Stack Point
Prog Count
CAT FCB 64 06E5t-.....::~_-t-------~
Figure 26
040C
CC
Example of Extended Addressing
Memory
A
PROG BEQ PROG2 ~:~~~--:;":~-I
Figure 27
Example of Relative Addressing
Memory
TABLFCC LI
00B8t::~:::i--~~-----~--------t~~4~C~~
n ex e
.
' " " CO, , " "
.
~
B8
Stack POint
Prog Count
05F5
CC
§
.
Figure 28
;
Example of Indexed (No Offset) Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
647
HD6305YO,HD63A05YO,HD63B05YO - - - - - - - - - - - - - - - - - - - - - -
Memory
TABl FCB II BF 00B9
FCB IIB6 008A
FCB IIDB 008B
FCB IICF 008C
BF
86
DB
CF
PROG lDA TABl.X 075B
075C
E6
89
A
CF
Index Reg
03
Stack Point
I
Prog Count
0750
CC
I
~
I
•
Figure 29
Example of Index (S·bit Offset) Addressing
Memory
A
DB
eg
02
Stack oont
Index
PROG lDA TABl.X ~~~~~~;;"""--1
0694
Prog Count
0695
CC
~----1
TABl FCB II BF 077E ~~:'---1
FCB 1186
FCB
IIDB 077Ft=~=j---------.-J
0780
FCB IICF 0781
............;;;...........
Figure 30
PORT B EQU 1 0001
Example of Index (16·bit Offset) Addressing
~-------f"1
A
Index Reg
I
PROG BClR 6. PORT B 058F
1D
0590 [ : = ! O U 1 = j - - - - - J
Figure 31
648
~ount
Prog
0591
CC
~
I,
Stack Point
:,
Example of Bit Set/Clear Addressing
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - HD6305YO,HD63A05YO,HD63B05YO
POAT C EQU 2 0002 ~....:..;FO:""'''''{l.L_ _.;I
PAOG BACLA 2.POAT CPAOG 2 0574
0575
0576
05
02
10
Figure 32
Example of Bit Test and Branch Addressing
Memory
'"06 ,., " ' "
~
~
~.
··
•
I
Figure 33
Example of Implied Addressing
-INSTRUCTION SET
There are 62 basic instructions available to the HD630SYO
MeU. They can be classified into five categories: register/
memory, read/modify/write, branch, bit manipulation, and
control. The details of each instruction are described in
Tables 5 through 11.
• Register/Memory Instructions
Most of these instructions use two operands. One operand
is either an accumulator or index register. The other is derived
from memory using one of the addressing modes used on the
HD630SYO MeU. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump
instruction (JSR). See Table S.
• Read/Modify/Write Instructions
These instructions read a memory or register, then modify
or test its contents, and write the modified value into the
memory or register. Zero test instruction (TST) does not
write data, and is handled as an exception in the read/modify/
write group. See Table 6.
• Branch Instructions
A branch instruction branches from the program sequence
in progress if a particular condition is established. See Table 7.
• Bit Manipulation Instructions
These instructions can be used with any bit located up to
the lower 2SSth address of memory. Two groups are available;
one for setting or clearing and the other for bit testing and
branching. See Table 8.
• Control Instructions
The control instructions control the operation of the MeV
which is executing a program. See Table 9.
• List of Instru.ctions in Alphabetical Order
Table 10 lists all the instructions used on the HD630SYO
MeV in the alphabetical order.
• Operation Code Map
Table 11 shows the operation code map for the instructions
used on the Mev.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
649
HD6305YO,HD63A05YO,HD63B05YO
Table 5 Register/Memory Instructions
Addressing Modes
Indexed
Operations
Mnemonic
Immediate
Extended
Direct
-
Indexed
Condition
Code
Booleanl
Arithmetic
Operation
Indexed
(No Offset) (S-Bit Offset) (16-BitOffset)
OP #
-
OP #
-
OP #
-
OP #
-
load A from Memory
lOA
A6
2 B6 2
3 C6 3
4
F6
1
3 E6
2
4 06 3
5
load X from Memory
lOX
AE 2
2 BE 2
3 CE 3
4
FE
1
3
EE
2
4 DE 3
5
M~X
Store A in Memory
STA
-
-
-
B7
2
3- C7 3
4
F7
1
4
E7
2
4 07 3
5
A~M
Store X in Memory
STX
-
- -
BF
2
3 CF 3
4
FF
1
4
EF
2
4
OF 3
5
X~M
Add Memory to A
ADD
AB 2
2 BB 2
3 CB 3
4
FB
1
3 EB
2
4 DB 3
5
A+M-·A
A
to A
AoC
A9 2
2 B9 2
3 C9 3
4
F9
1
3 E9
2
4 09 3
5
A+M+C~A
Subtract Memory
SUB
AO 2
2 BO 2
3 CO 3
4
FO
1
3 EO 2
4 DO 3
5
A-M~A
•
• •
A with Borrow
SBC
A2
2 B2
2
3 C2 3
4
F2
1
3 E2
2
4 02 3
5
A-M-C~A
AND Memory to A
AND
A4 2
2 B4 2
3 C4 3
4
F4
1
3
E4
2
4 04 3
5
A·
OR Memory with A
ORA
AA
2
2 BA 2
3 CA 3
4
FA
1
3 EA 2
4 OA 3
5
A+M~A
EOR
AB 2
2 B8
2
3 C8 3
4
F8
1
3 E8
2
4 08 3
5
A,+)M~A
CMP
A1
2 B1
2
3 C1
3
4
F1
1
3 E1
2
4 01
3
5
CPX
A3 2
2 B3 2
3 C3 3
4
F3
1
3 E3
2
4 03 3
A (logical Compare)
BIT
A5 2
2 B5
2
3 C5 3
4
F5
1
3 E5
2
Jump Unconditional
JMP
-
-
-
BC 2
2 CC 3
3 FC
1
2 EC
2
Jump to Subroutine
JSR
-
-
-
BO 2
5 CD 3
6 Fo
1
5 ED 2
2
OP #
OP #
-
M~A
H
I
•
•
•
•
•
•
•
•
•
A
~
A
r
A
/\
1\
r,
A
r
A
t,
A
"-
A
• •
A
A
·•
A-M
• •
A
A
~
5
X-M
• •
A
r
A
4 05 3
5
A·M
3 DC 3
4
5 DO 3
6
• •
•
• • • • •
• • • • •
A
• •
• •
• •
M~A
Arithmetic Compare X
with Memory
A
A
Arithmetic Compare A
2
A
C
•
•
•
•
A
Exclusive OR Memory
with Memory
A
A
Subtract Memory from
with A
Z
A
A
Add Memory and Carry
2
N
Bit Test Memory with
A
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
"
•
A
Table 6 Read/Modify/Write I~structions
Addressing Modes
Operations
Mnemonic
Indexed
Implied(A)
-
Implied(X)
-
Ind81Ced
(No Offset) (8-Bit Offset)
Direct
- OP #
- OP #
-
Increment
INC
4C
1
2 5C
1
2 3C 2
5 7C
1
5 6C 2
6
A+1~A
or
X+1~X
or
M+1~M
or
X-1~X
or
M-1~M
OP #
OP #
OP l!
Decrement
DEC
4A
1
2 5A 1
2 3A 2
5 7A
1
5 6A 2
6
A-1~A
Clear
ClR
4F
1
2
5F
1
2
3F
2
5
7F
1
5 6F
2
6
OO~A
Complement
COM
43
1
2 53
1
2 33
2
5
73
1
5 63
2
6
A~A
or
or
(2's Complement)
NEG
40
1
2 50
1
2 30 2
5
70
1
5 60 2
6
Rotate Left Thru Carry
ROl
49
1
2 59
1
2 39 2
5
79
1
5 69
2
6
Rotate Right Thru Carry
ROR
46
1
2 56
1
2 36
5
76
1
5 66 2
6
2
OO~X
X~X
oo-A~A
Negate
Condition
Code
Booleanl Arithmetic Operation
or
or
oo~M
M~M
H
I
•
•
•
•
•
•
•
•
N
Z
A
A
A
A
C
•
•
•
0
1
A
A
1
A
A
A
A
/\
A
A
A
r
A
A
A
0
A
A
A
A
A
A
1\
A
1\
1\
•
oo-X~X
or
• •
A",
i"'
III
~~
Lb-t I I I II I • •
I IAH"':"'I Ibo~ • •
c b,
too
[}-1 I ~",:xr~ I I 1-- 0 • •
oroo-M~M
L0=t
C
logical Shift left
lSl
48
1
2 58
1
2 38
2
5 78
1
5 68 2
6
logical Shift Right
lSR
44
1
2 54
1
2 34 2
5 74
1
5 64 2
6
Arithmetic Shift Right
ASR
47
1
2 57
1
2 37
2
5
77
1
5 67
2
6
Arithmetic Shift left
ASl
48
1
2 58
1
2 38
2
5
78
1
5 68 2
6
TST
40 1
4 70 1
4 60 2
5
Tnt tor Negative
or Zero
2 50 1
2 3D 2
b,
---110
c
01 1 IAH"':"'I 1 I-D • •
[(b'
110
c
I 1-0 • •
Equal to lSl
• •
A-oo or X-oo or M-oo
• •
:1
H'~~MI
Symbols: Op - Operation
# - Number of bytes
- - Number of cycles
650
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - HD6305YO,HD63A05YO,HD63B05YO
Table 7 Branch Instructions
Addressing Modes
Operations
Mnemonic
Relative
BRA
20
:1*
2
-
Branch Always
3
None
Branch Never
BRN
21
2
3
None
Branch IF Higher
BHI
22
2
3
C+Z=O
OP
Branch IF Lower or Same
BLS
23
2
3
C+Z=1
Branch IF Carry Clear
BCC
24
2
3
C=O
(BHS)
24
2
3
C=O
(Branch IF Higher or Same)
BCS
25
2
3
C=1
(BLO)
25
2
3
C=1
Branch IF Not Equal
BNE
26
2
3
z=o
Branch IF Equal
BEQ
27
2
3
Z=1
Branch IF Half Carry Clear
BHCC
28
2
3
H=O
Branch IF Half Carry Set
BHCS
29
2
3
H=1
Branch IF Plus
BPL
2A
2
3
N=O
Branch IF Minus
BMI
2B
2
3
N=1
BMC
2C
2
3
1=0
BMS
20
2
3
1=1
BIL
2E
2
3
INT=O
Branch IF Carry Set
(Branch IF Lower)
Condition Code
Branch Test
Branch IF Interrupt Line
is Low
Branch IF Interrupt Line
is High
BIH
2F
2
3
INT=1
Branch to Subroutine
BSR
AD
2
5
--
N
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Branch IF Interrupt Mask
Bit is Set
I
•
•
Branch IF Interrupt Mask
Bit is Clear
H
•
•
• •
• •
• •
• •
C
• •
•
•
•
•
•
•
•
•
•
•
•
•
• •
• •
• •
• •
• •
• •
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
Table 8 Bit Manipulation Instructions
Operations
Mnemonic
Addressing Modes
Boolean/
Bit Test and Branch Arithmetic
Bit Set/Clear
Operation
OP
OP
:1*
:1*
3 5
2·n
-
Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear Bit n
BRSET n(n=0···7)
BRCLR n(n=0 .. ·7)
BSH n(n=0 .. ·7)
10+2·n 2
BClR n(n=0 .. ·7)
11 +2·n 2
- 01 +2·n 3
5
5
-
Branch
Test
H
Mn=1
5
-
Mn=O
-
1-+Mn
O-+Mn
-
-
Condition Code
I
N
Z
C
• • • •
• • • •
• • • • •
• • • • •
1\
1\
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
651
H D6305YO, H o 63A05YO, H D63B05YO
Table 9
Control Instructions
Addressing Modes
Implied
Mnemonic
Operations
#
-
Transfer A to X
TAX
97
1
2
A--X
Transfer X to A
TXA
9F
1
2
X--A
Set Carry Bit
SEC
99
1
1
1--C
Clear Carry Bit
CLC
98
1
1
O---+C
Set Interrupt Mask Bit
Clear Interrupt Mask Bit
SEI
9B
1
1---+1
CLI
9A
1
Software Interrupt
SWI
83
1
Return from Subroutine
RTS
81
1
2
2
10
5
8
2
1
2
4
4
Return from Interrupt
RTI
80
1
Reset Stack Pointer
RSP
9C
1
No-Operation
NOP
1
Decimal Adjust A
OAA
90
80
Stop
STOP
8E
1
WAIT
8F
1
Wait
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
1
Condition Code
Boolean Operation
OP
0--1
$FF---+SP
Advance Prog. Cntr. Only
Converts binary add of BCD charcters into
BCD format
H
I
N
Z
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•1
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
•
0
1
•
?
•
•
•
•
•
1\
1\
C
•
•1
0
•
•
•
•?
•
•
•
•
1\*
• Are BCD characters of upper byte 10 or more? (They are not cleared if set in edvance.)
Table 10 Instruction Set (in Alphabetical Order)
Condition Code
Addressing Modes
Bit
Mnemonic
Implied
Immediate
Direct
x
x
x
x
x
x
x
x
ADC
ADD
AND
ASl
ASR
x
x
Extended Relative
x
x
x
Indexed
Indexed
Indexed
Set!
Test 8t
(No Offset)
(8-Bit)
(16-8it)
Clear
Branch
x
x
x
x
x
x
x
x
x
x
X
/\
X
/\
x
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
x
BCC
x
BClR
x
x
x
x
x
x
x
x
BCS
BEQ
BHCC
BHCS
BHI
(BHS)
BIH
Bil
x
BIT
x
BlS
BMC
BMI
BMS
BNE
BPl
BRA
Condition Cod. Symbols:
H
Half Carry (From Bit 3)
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
652
x
x
x
x
x
x
x
x
x
x
(BlO)
Bit
x
x
H
I
N
•
•
•
•
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
•
• •
• •
• •
• •
• •
• •
• •
• •
Z
C
/\
/\
/\
/\
/\
/\
•
/\
/\
/\
II
II
II
/\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
/\
II
II
•
•
(to be continued)
C
/\
•?
Carry /Borrow
Test and Set if True. Cleared Otherwise
Not Affected
load CC Register From Stack
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H D6305YO, H D63A05YO, H D63B05YO
Table 10 Instruction Set (in Alphabetical Order)
Addressing Modes
Condition Code
Bit
Inaexed
Mnemonic
Implied
Immediate
Direct
Extended Relative (No Offset)
BRN
Indexed
Indexed
Set!
Test &
(S-Bit)
(16-Bit)
Clear
Branch
X
BRCLR
X
BRSET
X
BSET
X
BSR
X
CLC
X
CLI
X
CLR
X
CMP
COM
X
X
X
X
X
DAA
X
DEC
X
EOR
X
X
X
CPX
INC
X
X
X
X
X
X
X
JMP
JSR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
LOX
X
X
X
X
X
X
X
X
X
X
LSR
X
X
X
X
NEG
X
X
X
X
NOP
x
ORA
X
X
ROL
X
x
X
X
ROR
X
X
X
X
RSP
X
RTI
X
RTS
X
X
X
SBC
X
X
SEC
X
SEI
X
STA
X
X
x
X
x
X
x
x
SUB
SWI
x
TAX
X
TST
X
TXA
x
x
X
X
X
Condition Code Symbols:
H
Half Carry (From Bit 3)
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
X
X
X
X
X
X
X
X
X
C
/\
•?
x
X
C
•
/\
/\
•
•
0
•
•
/\
/\
/\
/\
1
/\
/\
/\
/\
/\
/\
/\
/\
/\
/\
X
X
Z
•
•
•
•
•
•
•1
/\
X
STX
WAIT
X
N
H
1\
X
LSL
I
• • •
• • •
• • •
• • •
• • •
• •0 •
• •
• • 0
• •
• •
• •
• •
• •
• •
• •
• • •
• • •
• •
• •
• •
• • 0
• •
• • •
• •
• •
• •
• • •
? ? ?
• • •
• •
• •1 •
• •
• •
• • •
• •
• •1
• •
• • •
• •
• • •
• • •
/\
LOA
STOP
Bit
/\
/\
•
•
•
• •
• •
•
•
1\
/\
/\
/\
/\
/\
/\
/\
/\
/\
/\
• •
•
/\
/\
/\
/\
/\
/\
•
?
•
•
•
•
•
?
•
/\
/\
/\
/\
/\
1\
/\
/\
1\
•
•
•
•
/\
/\
/\
1
•
•
•
•
•
•
•
•
•
/\
Carry/Borrow
Test and Set if True. Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
653
H D6305YO,HD63A05YO,HD,63B05YO - - - - - - - - - - - - - - - - - - - - - - Table 11
Bit Manipulation
Test &
Branch
Operation Code Map
Control
Aead/Modify /Write
Branch
Set/
Clear
Ael
DIA
A
X
,X1
,XC
IMP
0
1
2
3
4
5
6
7
B
0
BASETO
BSETO
BAA
,XC
E
F
<--
CMP
1
SBC
2
-
3
BRCLR1
BCLR1
BLS
COM
4
BASET2
BSET2
BCC
LSR
BCS
,X1
D
--
-
BHI
BNE
,X2
C
--
BRN
BSET1
BCLA2
EXT
B
RTS"
BCLAO
BSET3
DIA
SUB
BASET1
BACLR2
A
-
BACLAO
BASET3
9
ATI"
1
5
IMP IMM
NEG
2
6
Register /Memory
-
SWI*
-
ROR
-
-
CPX
3
-
AND
4
-
BIT
5
-
LDA
6
7
BACLA3
BCLA3
BEQ
ASA
--
TAX"
STA
5TAI+11 7
8
BASET4
BSET4
BHCC
LSL/ASL
--
CLC
EOR
8
9
A
BACLA4
BCLA4
BHCS
ROL
SEC
ADC
9
BASET5
BSET5
BPL
DEC
CLI*
ORA
A
B
BACLA5
BCLA5
BMI
C
BRSET6
BSET6
BMC
0
BACLA6
BCLA6
BMS
E
BRSET7
BSET7
Bil
F
BACLR7
BCLA7
BIH
3/5
2/5
2/3
(NOTES)
~
-
-
--
INC
T5TI-11
--
TST(-1)
TST
1/2
1/2
2/6
1/5
1/*
JSR(+2)
1/1
JSA(+1)
lDX
2/2
STX
2/3
3/4
3/5
l
o
W
B
JMP(-1)
-
WAIT' TXA*
CLA
2/5
ADD
-
DAA" NOP BSA"
STOP'
-
SEI*
ASP"
-
HIGH
0
2/4
C
JSRI+21 D
E
5TXI+11 F
1/3
1. "-" is an undefined operation code.
2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).
The 'number of cycles for the mnemonics asterisked (.) is as follows:
ATI
8
TAX
2
ATS
5
RSP
2
SWI
10
TXA
2
DAA
2
BSR
5
STOP
4
eLi
2
WAIT
4
SEI
2
3. The parenthesized numbers must be added to the cycle count of the particular instruction.
•
Additionallnstructions
The following new instructions are used on the HD630SYO:
DAA Converts the contents of the accumulator into BCD
code.
654
WAIT Causes
see the
STOP Causes
see the
the MCU to enter the wait mode. For this mode,
topic, Wait Mode.
the MCU to enter the stop mode. For this mode,
topic, Stop Mode.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
HD6305V1 ,HD63A05V1 ,HD63B05V1-HD6305V2, HD63A05V2, HD63B05V2
CMOS MCU (Microcomputer Unit)
The HD630SYI and the HD6305Y2 are CMOS 8-bit single
chip microcomputers. A CPU, a clock generator, a 256 byte
RAM, I/O terminals, two timers and a serial communication
interface (SCI) are built in both chip of the HD6305YI and
the HD6305Y2. Their memory spaces are expandable to 16k
bytes externally.
The HD6305Y I and the HD6305Y2 have the same functions
as the HD630SYO's except for the number of I/O terminals.
The HD6305YI has 7872 byte ROM and its memory space is
expandable to 8k bytes externally. The HD6305Y2 is a microcomputer unit which includes no ROM and its memory space
is expandable to 16k bytes ex tern ally .
HD6305Y1P, HD63A05Y1P,
HD63B05Y1P, HD6305Y2P,
HD63A05Y2P, HD63B05Y2P
• HARDWARE FEATURES
• S-bit based MCU
.7872 bytes of internal ROM (HD6305Y1)
No internal ROM (HD6305Y2)
.256 bytes of RAM
-A total of 31 terminals, including 24 110's, 7 inputs
.Two timers
8·bit timer with a 7-bit prescaler (programmable prescaler;
event counter)
15·bit timer (commonly used with the SCI clock divider)
• On-chip serial interface circuit (synchronized with clock)
.Six interrupts (two external, two timer, one serial and one
software)
• Low power dissipation modes
- Wait .... In this mode, the clock oscillator is on and the
CPU halts but the timer/serial/interrupt func·
tion is operatable.
Stop .... In this mode, the clock stops but the RAM
data, I/O status and registers are held.
Standby .. In this mode, the clock stops, the RAM data
is held, and the other internal condition is
reset.
• Minimum instruction cycle time
HD6305Y1/Y2 .. 1p.s (f = 1 MHz)
- HD63A05Y1!Y2 .. 0.67p.s (f = 1.5 MHz)
- HD63B05Y1/Y2 .. 0.5p.s (f = 2 MHz)
• Wide operating range
VCC = 3 to 6V (f = 0.1 to 0.5 MHz)
HD6305Y1/Y2 .. f 0.1 to 1 MHz (VCC 5V ± 100!O)
HD63A05Y1/Y2 .. f
0.1 to 1.5 MHz (VCC 5V ± 100!O)
HD63B05Y1/Y2 .. f 0.1 to 2 MHz (Vce 5V ± 10%)
.System development fully supported by an evaluation kit
=
=
=
=
=
HD6305Y1 F, HD63A05Y1 F,
HD63B05Y1 F, HD6305Y2F,
HD63A05Y2F, HD63B05Y2F
(FP-64)
• All addressing modes adaptable to RAM, and I/O instructions
• Three new instructions, STOP, WAIT and DAA, added to the
HD6805 family instruction set
• I nstructions that are upward compatible with those of Motorola's MC6805P2 and MC146805G2
=
• SOFTWARE FEATURES
.Similar to HD6S00
• Byte efficient instruction set
• Powerful bit manipulation instructions (Bit Set, Bit Clear, and
Bit Test and Branch usable for 192 byte RAM bits within page
o and all I/O terminals)
• A variety of interrupt operations
• Index addressing mode useful for table processing
• A variety of conditional branch instructions
• Ten powerful addressing modes
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
655
HD6305Y1,HD6305Y2-------------------------------------------------------• PIN ARRANGEMENT
• HD6305Y1P, HD63A05Y1P, HD63B05Y1P,
HD6305Y2P, HD63A05Y2P, HD63B05Y2P
Vss
RES
INT
STBY
XTAL
EXTAL
NUM
TIMER
A7
As
A5
A,
A3
A2
A,
Ao
B7
Bs
Bs
B,
B3
B2
B,
•
HD6305Y1F, HD63A05Y1F, HD63B05Y1F,
HD6305Y2F, HD63A05Y2F, HD63B05Y2F
< .J.
~ DATA,
DATA2
DATAo
0
.{
I-
I- I-
o
<{
<{
0
0
<{
DATA3
DATA4
DATA 5
DATAs
DATA7
E
R/iii
ADR13
ADR12
ADRn
ADR,o
ADA,
ADR,
ADR7
ADR.
ADR.
ADR4
ADR3
ADR z
ADR,
ADRo
07
80
C7/Tx
C./Rx
D,ITm'i
C7/Tx
D.
0,
03
C./CK
C,
C3
C2
C,
Co
02
0,
Vee
c5
odo
(Top View)
(Top View)
E
• BLOCK DIAGRAM
RtW
TIMER
I/O
CPU
I"del(
Port A
8
Register
Control
X
Terminals
Register
CPU
Stack
Pointer
0,
oe/iNTz
0,
04
03
Condition Code
6
.------,_ I
~~
PortO
Input
Terminals
Sp
Program
Counter
Port B
6
"High" PCH
'/0
Terminlls
• No internal ROM in H06305Y2
DATA,
o"'TA,
DATA,
O...T....
DATA,
DATA,
DATA,
OAT....
656
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
------------------------------------------------------HD6305Y1,HD6305Y2
• ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
Input Voltage
Symbol
Value
Unit
Vee
-0.3 - +7.0
V
Vin
-0.3 - Vee + 0.3
V
Operating Temperature
Topr
0-+70
°c
Storage Temperature
T stg
-55- +150
°c
[NOTE)
These products heve e protection circuit in their input terminals against high electrostatic \/oltage or high electric fields. Notwithstanding,
be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normal
operation, we recommanded Vln, Vout ; Vss ~ (V ln or Vout ) ~ Vee .
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee = 5.0V±10%, Vss = GND, Ta = 0 - +70 C, unless otherwise noted.)
0
Item
Symbol
Test Condition
RES, STBY
Input "High" Voltage
V IH
EXTAL
min
typ
max
Vee- 0 .5
-
Vee+ 0 .3
Vee xO .7
-
Vee+ 0 .3
2.0
-
Vee+0 .3
Other Inputs
Input "Low" Voltage
Output "High" Voltage
All Inputs
V OH
-0.3
-
0.8
V
2.4
-
IOH = -10J..LA
Vee- O.7
-
-
V
-
-
0.55
V
-
-
1.0
J..LA
-
-
1.0
J..LA
Operating
-
5
10
mA
Wait
-
2
5
mA
2
10
J..LA
2
10
J..LA
-
12
pF
Output "Low" Voltage
All Outputs
VOL
I nput Leakage Current
TIMER,INT,
D1 - D 7 , STBY
Illd
Three-state Current
Ao - A 7 , Bo - B 7 ,
Co - C7 , ADRo - ADR13*'
DATA o- DATA7.E", R/W"
IITSd
Current Dissipation**
IOL = 1.6mA
Vin = 0.5 - Vee-0.5
f=1MHz***
Icc
Stop
Standby
Input Capacitance
V
IOH - -200J..LA
V IL
All Outputs
Unit
All Terminals
f = 1MHz, Vin = OV
Cin
• Only at standby
•• VIH min = Vee-1.OV, VIL max = O.BV
... The value at f = xMHz is given by uSing.
lee (f =xMHz) = lee (f = 1MHz) x x
•
AC CHARACTERISTICS (Vee = 5.0V±10%, Vss = GND, Ta
Item
Symbol
Test
Condition
=0 -
+70°C, unless otherwise noted.)
H D6305Y 1/Y2
HD63A05Y1/Y2
min
typ
max
min
typ
0.666
-
Cycle Time
tCYC
1
Enable Rise Time
tEr
-
-
10
-
20
Enable Fall Time
tEf
-
-
-
20
-
Enable Pulse Width("High" Level)
PWEH
450
-
300
450
-
250
-
Enable Pulse Width("Low" Level)
PW EL
Address Delay Time
tAD
Fig. 1
-
300
-
H D63B05Y 1/Y2
min
10
0.5
-
10
J..LS
20
-
20
ns
20
ns
-
220
-
-
ns
20
-
220
190
-
typ
-
20
160
-
-
-
20
-
50
-
-
0
-
Address Hold Time
tAH
40
-
-
30
Data Delay Time
tow
-
200
-
Data Hold Time (Write)
tHW
40
-
-
tOSA
80
-
60
Data Hold Time (Read)
tHA
0
-
-
30
Data Set-up Time (Read)
0
Unit
max
max
-
ns
180
ns
-
ns
120
ns
-
-
ns
-
-
ns
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
ns
657
HD6305Y1,HD6305Y2-------------------------------------------------------•
PORT TIMING (Vee = 5.0V±10%, Vss = GND, Ta = 0 - +70°C, unless otherwise noted.)
Item
•
Symbol
Port Data Set·up Time
(Port A, B, C, D}
tpDS
Port Data Hold Time
(Port A, B, C, D)
tpDH
Port Data Delay Time
(Port A, B, C)
tpDW
Test
Condition
HD6305Y1/Y2
min
typ
max
min
typ
max
min
typ
max
200
-
-
200
-
-
200
-
-
ns
200
-
-
200
-
-
200
-
-
ns
-
-
300
-
-
300
-
-
300
ns
HD63A05Y1/Y2
HD63B05Y1/Y2
Unit
Fig.2
Fig. 3
CONTROL SIGNAL TIMING (Vee = 5.0V±10%, Vss = GND, Ta = 0 - +70°C, unless otherwise noted.)
Item
Symbol
Test
Condition
HD6305Y1/Y2
HD63A05Y1/Y2
HD63B05Y1/Y2
Unit
min
typ
max
min
typ
max
min
typ
max
-
-
-
-
tcyc
+200
tcyc
+200
-
-
ns
-
-
ns
5
250
-
-
tCYc
ns
INTPulse Width
t'WL
tcyC
+250
INT2 Pulse Width
t'WL2
tcyc
+250
-
-
tcyc
+200
tcyc
+200
-
-
RES Pulse Width
tRWL
5
-
-
5
-
Control Set-up Time
tcs
250
-
-
250
-
-
Timer Pulse Width
tTwL
tcyc
+250
-
-
tcyc
+200
-
-
tcyc
+200
-
-
ns
Oscillation Start Time (Crystal)
tosc
Fig.5, F ig.20·
-
-
20
-
-
20
-
-
20
ms
Reset Delay Time
tRHL
Fig, 19
80
-
-
80
-
-
80
-
-
ms
* CL
Fig. 5
= 22pF ±20%, Rs = 600 max .
• SCI TIMING (Vee = 5.0V±10%, Vss= GND, T8 = 0 - +70°C, unless otherwise noted.)
Item
Symbol
Clock Cycle
tscyc
Data Output Delay Time
tTXD
Data Set-up Time
tSRX
Data Hold Time
tHRX
658
Test
Condition
Fig,6,
Fig, 7
H D6305Y 1/Y2
min
typ
1
-
200
100
max
HD63A05Y1/Y2
min
H D63B05Y 1/Y2
typ
max
min
typ
max
-
21845
0,5
250
-
-
16384
-
200
-
-
-
200
-
100
100
-
-
32768 0.67
250
-
-
250
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
Unit
IlS
ns
ns
ns
--------------------------------------------------------HD6305Y1,HD6305Y2
~---------tcYC---------~
E
\ ...I----PWEL--~~
2.4V
Ao-A13
R/W
O.6V
tow
MCU Write
DATAo - DATA7
MCU Read
DATAo - DATA7
Figure 1 Bus Timing
E
2.4V
E
Port
A,B,C,D
Port
A,B,C
2.4V
O.6V
Data
Valid
Figure 3 Port Data Delay Time (MCU Write)
Figure 2 Port Data Set-up and Hold Times
(MCU Read)
Interrupt
Test
E
Address
Bus
INT,INT2
\ \ -_ _...1
Vector Vector New PC
MSB
LSB
Address
AddressAddress
PCoPC7
Data Bus
Vector Vector
~:d~ess;~~ress
RiW
First Inst. of
Interrupt Routine
\\------_-1'
Figure 4 Interrupt Sequence
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave .• San Jose, CA 95131 • (408) 435-8300
659
HD6305Y1,HD6305Y2 - - - - - - - - - - - - - - - - - - - - - - - - - - -
=:=u-t
5~
,
E
4.SV
Vee
tosc
STBY
- -------.....-----i4---.....,
90pF
• Data Bus (DATAo - DATA,)
• Address Bus (ADR o - ADR 13 )
Each terminal is TTL compatible and can drive one TTL
load and 90pF.
12kQ
• Input/Output Terminals (Ao '"" A7, Bo - B7, Co - C,)
These 24 tenninals consist of three 8-bit I/O ports (A, B, C).
Each of them can be used as an input or output terminal on
a bit through program control of the data direction register.
For details, refer to "I/O PORTS."
[NOTES I 1. The load capacitance includes stray capacitance caused
by the probe, etc.
2. All diodes are 152074
®
• Input Terminals (01 ..... 07)
These seven input-only terminals are TTL or CMOS compatible. Of the port D's, D6 is also used as INT2. If D6 is
used as a port, the INT2 interrupt mask bit of the miscellaneous register must be set to "1" to preve~t an INT2 interrupt
from being accidentally accepted.
Figure 8 Test Load
- DESCRIPTION OF TERMINAL FUNCTIONS
The input and output signals of the MCU are described
here.
.STBY
This tenninal is used to place the Mev into the standby
mode. With STBY at "Low" level, the oscillation stops and
the internal condition is reset. For details, refer to "Standby Mode."
.Vee, Vss
Voltage is applied to the MCU through these two terminals.
Vee is 5.0V ± 10%, while Vss is grounded.
The terminals described in the following are I/O pins for
serial communication interface (SCI). They are also used as
ports Cs , C6 and C7 • For details, refer to "SERIAL COMMUNICATION INTERFACE."
.INT,INT2
External interrupt request inputs to the MCU. For details,
refer to "INTERRUPT". The INT 2 terminal is also used as
the port D6 tenninal.
• XT AL, EXTAL
These tenninals provide input to the on-chip clock circuit.
A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic
fIlter is connected to the terminal. Refer to "INTERNAL
OSCILLATOR" for using these input tenninals.
.CK (Cs)
Used to input or output clocks for serial operation.
• Rx (C6)
Used to receive serial data.
.Tx (C,)
Used to transmit serial data .
• TIMER
This is an input terminal for event counter. Refer to
"TIMER" for details.
-MEMORY MAP
.RES
Used to reset the MCV. Refer to "RESET" for details.
.NUM
This terminal is not for user application. In case of the
HD6305Y I this tenninal should be connected to Vee
through lOkn resistance. In case of the HD6305Y2, this
terminal should be connected to Vss·
• Enable (E)
This output tenninal supplies E clock. Output is a singlephase, TTL compatible and 1/4 crystal oscillation frequency
or 1/4 external clock frequency. It can drive one TIL load
and a 90pF condenser.
The memory map of the MCU is shown in Fig. 9. $0140$IFFF of the HD6305Y2 are external addresses. However,
care should be taken to assign vector addresses to $1 FF6 $IFFF. During interrupt processing, the contents of the CPU
registers are saved into the stack in the sequence shown in
Fig. 10. This saving begins with the lower byte (PCL) of the
program counter. Then the value of the stack pointer is
decremented and the higher byte (PCH) of the program
counter, index register (X), accumulator (A) and condition
code register (CC) are stacked in that order. In a subroutine
call, only the contents of the program counter (PCH and PCL)
are stacked.
• RelldlWrite (R/W)
This TTL compatible output signal indicates to peripheral
and memory devices whether MCV is in Read ("High"), or
in Write ("Low"). The normal standby state is Read ("High").
Its output can drive one TTL load and a 90pF condenser.
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
661
HD6305Y1,HD6305Y2
-REGISTERS
o
63
64
255
256
319
320
$0000
I/O Ports
Timer
SCI
0
1
2
3
4
5
6
$003F
RAM
(192Bytes)
Stack
RAM
(64Bytes)
~_O040
$8
\
$013F
PORT
PORT
PORT
PORT
A
B
C
D
PORT A DDR
PORT BOOR
PORT C DDR
$00
$01
$02
$03""
$04"
$05"
$06"
Not Used
OFF
$ 100
8
Timer Data Reg
9 Timer CTRL Reg
10
Mise Reg
$08
$09
$OA
$0140
ROM·
There are five registers which the programmer can operate.
7
0
I
-'I Accumulator
A_ _ _ _
L._ _ _ _
7
0
X
I
Iindex
-..JReglster
L.._ _ _ _ _ _ _ _
13
0
PC
I Program
....
I _ _ _ _ _ _ _ _ _ _ _ _ _ _--'. Counter
6 5
13
0
1 I"--__
1,-0...lI,-o~10-,,1...101.....0.1-10...L1_1~I...1
s_p_---'I ~b~~t'er
Not Used
r--.....--............,,........-... Condition
(7.872Bytes)
Code
4....L.................""'-T-""""-' Register
8182
8191
8192
---------
16
17
18
$1FF6
1'I7~~~~~~t • $1FFF
$2000
31
3~\
•External
Memory Space
16383
63
$3FFF
SCI CTRL Reg
SCI STS Reg
SCI Data Reg
Not Used
External
Memory Space
$10
$11
$12
~gg~~
Zero
'-----Negative
'------Interrupt
Mask
'-------Half
Carry
$1F
$20
$3F
Figure 11 Programming Model
* Write only reg ister
* * Read only regi ster
• Accumulator (A)
* ROM area ($0140 - $1 FFF) in the HD6305Y2
is changed into External Memory Space.
This accumulator is an ordinary 8-bit register which holds
operands or the result of arithmetic operation or data processing.
Figure 9 Memory Map of MCU
• Index Register (X)
I
76543210
Condition
n-4 1 1 1 Code
Register n+'1
n-3
Accumulator
n+2
n-2
Index Register
n+3
n-1 0
01
n+4
n
PCW
Pull
The index register is an 8-bit register, and is used for index
addressing mode. Each of the addresses contained in the
register consists of 8 bits which, combined with an offset
value, provides an effective address.
In the case of a read/modify/write instruction, the index
register can be used like an accumulator to hold operation
data or the result of operation.
If not used in the index addressing mode, the register can
be used to store data temporarily.
• Program Counter (PC)
PCL"
n+5
Push
* In a subroutine call, only PCL and PCH are stacked.
Figure 10 Sequence of Interrupt Stacking
The program counter is a 14-bit register that contains the
address of the next instruction to be executed.
• Stack Pointer (SP)
The stack pointer is a 14-bit register that indicates the address of the next stacking space. Just after reset, the· stack
pointer is set at address $OOFF. It is decremented when data
is pushed, and incremented when pulled. The upper 8 bits
of the stack pointer are fIXed to 00000011. During the MCU
being reset or during a reset stack pointer (RSP) instruction,
the pointer is set to address $OOFF. Since a subroutine or
interrupt can use space up to address $OOCI for stacking, the
subroutine can be used up to 31 levels and the interrupt up
to 12 levels.
• Condition Code Register (CC)
The condition code register is a S-bit register, each bit
indicating the result of the instruction just executed. The
bits can be individually tested by conditional branch instruc-
662
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------HD6305Y1,HD6305Y2
tions. The CC bits are as follows:
Half Carry (H): Used to indicate that a carry occurred between bits 3 and 4 during an arithmetic operation (ADD, ADC).
Interrupt (I): Setting this bit causes all interrupts, except
a software interrupt, to be masked. If an
interrupt occurs with the bit I set, it is
latched. It will be processed the instant
the interrupt mask bit is reset. (More specifically, it will enter the interrupt processing
routine after the instruction following the
CLI has been executed.)
Negative (N): Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is negative (bit 7 is logic
"I ").
Zero (Z):
Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is zero.
Carry/
Represents a carry or borrow. that occurred
Borrow (C): in the most recent arithmetic operation. This
bit is also affected by the Bit Test and Branch
instruction and a Rotate instruction.
Of these six interrupts, the INT2 and TIMER or the SCI
and TIMERz generate the same vector address, respectively.
When an interrupt occurs, the program in progress stops
and the then CPU status is saved onto the stack. And then,
the interrupt mask bit (I) of the condition code register is
set and the start address of the interrupt processing routine
is obtained from a particular interrupt vector address. Then
the interrupt routine starts from the start address. System
can exit from the interrupt routine by an RTI instruction.
When this instruction is executed, the CPU status before
the interrupt (saved onto the stack) is pulled and the CPU
restarts the sequence with the instruction next to the one at
which the interrupt occurred. Table 1 lists the priority of
interrupts and their vector addresses.
Table 1
Interrupt
-INTERRUPT
There~e six different types of interrupt: external interrupts (INT,. I~T2), internal timer interrupts (TIMER,
TIMER2), senal mterrupt (SCI) and interrupt by an instruction (SWI).
Priority of Interrupts
Priority
Vector Address
RES
1
$1FFE,
$1FFF
SWI
2
$1FFC,
$1FFD
INT
3
$1FFA,
$1FFB
TIMER/INTz
4
$1FF8,
$1FF9
SCI/TIMER2
5
$1FF6,
$1FF7
A flowchart of the interrupt sequence is shown in Fig. 12.
A block diagram of the interrupt request source is shown in
Fig. 13 .
.-------~
y
fNT
y
fN'f;"
y
1~1
$FF~SP
TIMER
O~DDR's
CLR INT Logic
Y
SCI
$FF~TDR
$7F~ Timer Prescaler
$50~TCR
$3F~SSR
$OO~SCR
$7F~MR
Figure 12 Interrupt Flow Chart
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
663
HD6305Y1,HD6305Y2 - - - - - - - - - - - - - - - - - - - - - - - - - - In the block diagram, both the external interrupts INT and
INT2 are edge trigger inputs. At the falling edge of each input,
an interrupt request is generated and latched. The INT interrupt request is automatically cleared if jumping is made to
the INT processing routine. Meanwhile, the INT2 request is
cleared if "0" is written in bit 7 of the miscellaneous register.
For the external interrupts (INT, INT2), internal timer
interrupts (TIMER, TIMER2) and serial interrupt (SCI), each
interrupt request is held, but not processed, if the I bit of the
condition code register is set. Immediately after the I bit is
cleared, the corresponding interrupt processing starts according to th~ority.
The INT2 interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by setting bit 6
of the timer control register; the SCI interrupt by setting bit
5 of the serial status register; and the TIMER2 interrupt by
setting bit 4 Of the serial status register.
The status of the INT terminal can be tested by a BIL or
BIH instruction. The INT falling edge detector circuit and
its latching circuit are independent of testing by these instructions. This is also true with the status of the INT2 terminal.
eMiscelianeous Register (MR; $OOOA)
The interrupt vector address for the external interrupt
INT2 is the same as that for the TIMER interrupt, as shown
in Table I. For this reason, a special register called the miscellaneous register (MR; $OOOA) is available to control the
INT2 interrupts.
Bit 7 of this register is the INT2 interrupt request flag.
When the falling edge is detected at the INT2 terminal, "1"
is set in bit 7. Then the software in the interrupt routine
(vector addresses: $lFF8, $lFF9) checks bit 7 to see if it
is INT2 interrupt. Bit 7 can be reset by software,
Miscellaneous Register (MR;$OOOA)
76543210
IMR7IMR61=IZI
!
t
-INT-2 Interrupt Mask
Interrupt Request Flag
' - - - - - - - - - - - - iNf2
Bit 6 is the INT2 interrupt mask bit. If this bit is set to "I",
then the INT2 interrupt is disabled. Both read and write are
possible with bit 7 but "I" cannot be written in this bit by
software. This means that an interrupt request by software
is impossible.
.
When reset, bit 7 is cleared to "0" and bit 6 is set to "I".
-TIMER
Figure 14 shows a MCV timer block diagram. The timer
data register is loaded by software and, upon receipt of a
clock input, begins to count down. When the timer data
Vectoring generated
$1FFA,$1FFB
BIH/BIL Test
Condition Code Register (CC)
1liIT Interrupt Latch
INT
Falling Edge Detector
I
~--4~+---- Vectoring generated
$1 FF8, $1 FF9
TIMER
Serial Status
Register (SSR)
SCI/TIMER2
~--.....- - - Vectoring generated
$1FF6,$1FF7
Figure 13 Interrupt Request Generation Circuitry
664
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------HD6305Y1,HD6305Y2
• Timer Control Register (TCR; $0009)
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
register (TOR) becomes "0", the timer interrupt request
bit (bit 7) in the timer control register is set. In response to
the interrupt request, the CPU saves its status into 'the stack
and fetches timer interrupt routine address from addresses
$1 FF8 and $1 FF9 and execute the interrupt routine. The
timer interrupt can be masked by setting the timer interrupt
mask bit (bit 6) in the timer control register. The mask bit
(I) in the condition code register can also mask the timer
interrupt.
The source clock to the timer can be either an external
Signal from the timer input terminal or the internal E signal
(the oscillator clock divided by 4). If the E signal is used as
the source, the clock input can be gated by the input to the
timer input terminal.
Once the timer count has reached "0", it starts counting
down with "$FF". The count can be monitored whenever
desired by reading the timer data register. This permits the
program to know the length of time having passed after the
occurrence of a timer interrupt, without disturbing the contents of the counter.
When the MCU is reset, both the prescaler and counter are
initialized to logic "1". The timer interrupt request bit
(bit 7) then is cleared and the timer interrupt mask bit (bit
6) is set.
To clear the timer interrupt request bit (bit 7), it is necessary to write "0" in that bit.
Timer Control Register (TCR; $0009)
' - - - - - - - - - - - - Timer interrupt mask
' - - - - - - - - - - - - - - T i m e r interrupt request
After reset, the TCR is initialized to "E under timer terminal control" (bit 5 = 0, bit 4 = 1). If the timer terminal is
"1", the counter starts counting down with "$FF" immediately after reset.
When "1" is written in bit 3, the prescaler is initialized.
This bit always shows "0" when read.
Table 2
TCR7
Timer interrupt request
o
Absent
TCR
Bit 5
Bit 4
Present
TCR6
o
Clock Source Selection
Clock input source
0
0
I nternal clock E
Timer interrupt mask
0
1
E under timer terminal control
Enabled
1
0
No clock input (counting stopped)
Disabled
1
1
Event input from timer terminal
Initialize
(Internal
Clock)
E ----11---1
~
____
~
______
Write
~
____- J
Timer Interrupt
Read
Figure 14 Timer Block Diagram
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
665
HD6305Y1,HD6305Y2
A prescaler division ratio is selected by the combination of
three bits (bits 0, 1 and 2) of the timer control register (see
Table 3). There are eight different division ratios; -:-1, -:-2,-:-4,
-:-8, -:-16, -:-32, -:-64 and -:-128. After reset, the TCR is set to the
-:-1 mode.
Table 3
-SERIAL COMMUNICATION INTERFACE (SCI)
This interface is used for serial transmission or reception
of 8-bit data. Sixteen transfer rates are available in the range
from 1 J.!s to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one eighth counter and
one prescaler. (See Fig. 15.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 5,
6 and 7 of port C. Described below are the operations of
each register and data transfer.
Prescaler Division Ratio Selection
TCR
Bit 0
Prescaler division ratio
Bit 2
Bit 1
0
0
0
+1
0
0
1
-:-2
0
1
0
H
0
1
1
-:-8
1
0
0
-:-16
1
0
1
-:-32
1
1
0
-:-64
1
1
1
-:-128
A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "1". When a timer
interrupt occurs, "I" is set in the timer interrupt request bit.
This bit can be cleared by writing "0" in that bit.
eSCI Control Register (SCR; $0010)
SCI Control Registers (SCR;$0010)
E
_ ,. __£f__,
C5(CK)
'--,.......-'---r-..1
Transfer
Clock
Generator
:
I
I
I
I
SCI Data Registers
(SDR: $0012)
L-...L,~.....J
.-._ _ _ _ _-1
I
I
Initialize
I
-----.l
C6(Rx)
I
C7(Tx)
L______ }--~=r~~~~~~~~~~~~~~~~~~~~~~~-~
SCI Status Registers
(SSR :$0011)
Not Used
SCI/TlMER2
Figure 15 SCI Block Diagram
666
_HITACftl
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------HD6305Yl,HD6305Y2
SCR7
Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completion of transmitting or receiving 8-bit data. It is
cleared when reset or data is written to or read from the
SCI data register with the SCRS=" 1". The bit can also be
cleared by writing "0" in it.
C7 terminal
o
Used as I/O terminal (by DDR).
Serial data output (DDR output)
SCR6
Bit 6 (SSR6)
Bit 6 is the TIMER z interrupt request bit. TIMER z is used
commonly with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When reset, the
bit is cleared. It also be cleared by writing "0" in it. (For
details, see TIMERz .)
C6 terminal
o
Used as I/O terminal (by DDR).
Serial data input (DDR input)
SCR5 SCR4
Clock source
C5 terminal
a
a
-
a
1
-
1
a
Internal
Clock output CDDR output)
1
1
External
Clock input (DDR input)
Used as I/O terminal (by
DDR).
Bit 7 (SCR7)
When this bit is set, the DDR corresponding to the C 7
becomes "1" and this terminal serves for output of SCI data.
After reset, the bit is cleared to "0".
Bit 6 (SCR6)
When this bit is set, the DDR corresponding to the C6
becomes "0" and this terminal serves for input of SCI data.
After reset, the bit is cleared to "0".
Bit S (SSRS)
Bit S is the SCI interrupt mask bit which can be set or
cleared by software. When it is "1", the SCI interrupt (SSR7)
is masked. When reset, it is set to "1"
Bit 4 (SSR4)
Bit 4 is the TIMER z interrupt mask bit which can be set
or cleared by software. When the bit is "1", the TIMERz
interrupt (SSR6) is masked. When reset, it is set to "1 ".
Bit 3 (SSR3)
When "1" is written in this bit, the prescaler of the transfer
clock generator is initialized. When read, the bit always is "0".
Bits 2,.., 0
Not used.
SSR7
o
Bits S and 4 (SCRS, SCR4)
These bits are used to select a clock source. After reset,
the bits are cleared to "0".
a
SCR2
a
SCRl
a
SCRa
a
SSR6
o
SSR5
o
0.95p.s
a
0
1
2 p.s
1.91 p.s
a
a
1
a
4 p.s
3.82 p.s
a
a
1
1
8 p.s
7.64p.s
SSR4
1
1
1
1
1
1
a
1
1
1
1
32768 p.s
1/32 s
-SCI Status Register (SSR; $0011)
Absent
SCI interrupt mask
Enabled
Disabled
a
-SCI Data Register (SDR; $0012)
A serial-parallel conversion register that is used for transfer
of data.
TIMER z interrupt request
Present
Transfer clock rate
4.00 MHz
4.194 MHz
1 J..Ls
Absent
Present
Bits 3,.., 0 (SCR3 ,.., SCRO)
These bits are used to select a transfer clock rate. After
reset, the bits are cleared to "0".
SCR3
SCI interrupt request
TIMER z interrupt mask
Enabled
Disabled
• Data Transmission
By writing the desired control bits into the SCI control
registers, a transfer rate and a source of transfer clock are
determined and bits 7 and S of port C are set at the serial
data output terminal and the serial clock terminal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data
written in the SCI data register is output from the C 7 /Tx
terminal, starting with the LSB, synchronously with the
falling edge of the serial clock. (See Fig. 16.) When 8 bit of
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
667
HD6305Y1,HD6305Y2-----------------------------------------------------data have been transmitted, the interrupt request bit is set in
bit 7 of the SCI status register with the rising edge of the last
serial clock. This request can be masked by setting bit 5 of the
SCI status register. Once the data has been sent, the 8th bit
data (MSB) stays at the C7/Tx terminal. If an external clock
source has been selected, the transfer rate determined by
bits 0 "'" 3 of the SCI control register is ignored, and the Cs /
terminal is set as input. If the internal clock has been
selected, the C5/CK terminal is set as output and clocks are
output at the transfer rate selected by bits 0 "'" 3 of the SCI
control register.
ex
Figure 16 SCI Timing Chart
• Data Reception
By writing the desired control bits into the SCI control
register, a transfer rate and a source of transfer clock are determined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock terminal, respectively.
Then dummy-writing or -reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed after reading subseC[uent received data. It must be taken
after reset and after not reading subsequent received data.)
The data from the C6 /Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig. 16). When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bit 5
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0 "'" 3 of the SCI
control register is ignored and the data is received synchronously with the clock from the Cs /CKterminal. If the internal
clock has been selected, the Cs/CK terminal is set as output
and clocks are output at the transfer rate selected by bits 0 "'"
3 of the SCI control register.
TIMERz is commonly used with the SCI transfer clock
generator. If wanting to use TIMERz independently of the
SCI, specify "External" (SCR5 = 1, SCR4 = I) as the SCI
clock source.
If "Internal" is selected as the clock source, reading or
writing the SDR causes the prescaler of the t,ansfer clock
generator to be initialized.
-I/O PORTS
There are 24 input/output terminals (ports A, B, C). Each
I/O terminal can be selected for either input or output by the
data direction register. More specifically, an I/O port will
be input if "0" is written in the data direction register, and
output if "1" is written in the data direction register. Port A,
B or C reads latched data if it has been programmed as output,
even with the output level being fluctuated by the output
load. (See Fig. 17.)
When reset, the data direction register and data register go
to "0" and all the input/output terminals are used as input.
Bit of data
direction
register
Bit of
output
data
Status of
output
Input to
CPU
1
0
0
0
1
1
1
0
X
3-state
Figure 17
.TIMERz
The SCI transfer clock generator can be used as a timer.
The clock selected by bits 3 "'" 0 of the SCI control register
(4 IJ,S "'" approx. 32 ms (for oscillation at 4 MHz» is input to
bit 6 0[" the SCI status register and the TIMERz interrupt
request bit is set at each falling edge of the clock. Since interrupt requests occur periodically, TIMERz can be used as a
reload counter or clock.
---~1
' - -_ _...J
CD
: Transfer
clock generator is reset and mask bit (bit 4
of SCI Itatus register) is cleared.
00. @ : TIMERl interrupt request
@.@ : TIMEAz interrupt request bit cleared
668
1
Pin
InputlOutput Port Diagram
Seven input-only terminals are available (port D). Writing
to an input terminal is invalid.
All input/output terminals and input tenninals are TTL
compatible and CMOS compatible in respect of both input and
output.
If I/O ports or input ports are not used, they should be
connected to VSS via resistors. With none connected to these
terminals, there is the possibility of power being consumed
despite that they are not used.
-RESET
The MCU can be reset either by external reset input (RES)
or power~n reset. (See Fig. 18.) On power up, the reset
input must be held "Low" for at least tose to assure that the
internal oscillator is stabilized. A sufficient time of delay can
be obtained by connecting a capacitance to the RES input as
shown in Fig. 19.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------HD6305Y1,HD6305Y2
requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 - 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the required oscillation frequency stability.
Three different terminal connections are shown in Fig. 20.
Figs. 21 and 22 illustrate the specifications and typical arrangement of the crystal, respectively.
5V
Vee
OV
I ........ j..-'"
V
RES
Terminal
-
~::;;al
VIH
----------1"'"
tRHL
--
RES
f---
Cl
___________________~
Figure 18
~~
XTAL~~EXTAL
Power On and Reset Timing
Figure 21
AT Cut
Parallel
Resonance
Co=7pF max.
f=2.0-8.0MHz
Rs=600 max.
Parameters of Crystal
100kn typ
(a)
HD6305Y
MCU
Figure 19
Input Reset Delay Circuit
-INTERNAL OSCILLATOR
The internal oscillator circuit is designed to meet the
[NOTE] Use as short wirings as possible for connection of the crystal
with the EXTAL and XTAL terminals. Do not allow these
wirings to cross others.
II--~~-l EXTAL
lo-a:OMH=
XTAL
Figure 22
Typical Crystal Arrangement
HD6305Y
MCU
-LOW POWER DISSIPATION MODE
10-22pF±20%
The HD630SY has three low power dissipation modes:
wait, stop and standby.
Crystal Oscillator
• Wait Mode
When WAIT instruction being executed, the MCU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication interface - stay active. (NOTE: Once the system has entered the
wait mode, the serial communication interface can no longer
be retriggered.) In the wait mode, the registers, RAM and I/O
terminals hold their condition just before entering into the
wait mode.
The escape from this mode can be done by interrupt (INT,
TIMER/INT2 or SCI/TIMER2), RES or STBY. The RES
resets the MCU and the STBY brings it into the standby
mode. (This will be mentioned later.)
When interrupt is requested to the CPU and accepted, the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit of the condition code register, after releasing from the wait mode the MCU executes the instruction
next to the WAIT. If an interrupt other than the iNT (i.e.,
TIMER/INT2 or SCI/TIMER2) is masked by the timer control
HD6305Y
MCU
Ex ternal..-_ _..,:C..,:e_ra_m_i_c_O_S_c_ilI_a_to..,r
Clock
Input
EXTAL
NC
XTAL HD6305Y
MCU
External Clock Drive
Figure 20
I nternal Oscillator Circu it
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
669
HD6305Y1,HD6305Y2------------------------------------------------------register, miscellaneous register or serial status register, there
is no interrupt request to the CPU, so the wait mode cannot
be released.
Fig. 23 shows a flowchart for the wait function.
• Stop Mode
When STOP instruction being executed, MCU enters into
the stop mode. In this mode, the oscillator stops and the CPU
and peripheral functions become inactive but the RAM,
registers and I/O terminals hold their condition just before
entering into the stop mode.
The escape from this mode can be done by an external
interrupt (INT or INT2), RES or STBY. The RES resets the
MCU and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted,
the stop mode escapes, then the CPU is brought to the opera·
tion mode and vectors to the interrupt routine. If the inter·
rupt is masked by the J. bit of the condition code register,
after releasing from the stop mode, the MCU executes the
instruction next to the STOP. If the INT2 interrupt is masked
by the miscellaneous register, there is no interrupt request to
the MCU, so the stop mode cannot be released.
Fig. 24 shows a flowchart for the stop function. Fig. 25
shows a timing chart of return to the operation mode from
the stop mode.
For releasing from the stop mode by an interrupt, oscilla·
tion starts upon input of the interrupt and, after the internal
delay time for stabilized oscillation, the CPU becomes active .
For restarting by RES, oscillation starts when the RES goes
"0" and~ CPU restarts when the RES goes "I". The duration of RES="O" must exceed 30 ms to assure stabilized ascii·
lation.
• Standby Mode
The MCU enters into the standby mode when tk STBY
terminal goes "Low". In this mode. all operations stop and
the internal condition is reset but the contents of the RAM are
hold. The I/O terminals turn to high-impedance state. The
standby mode should escape by bringing STBY "High". The
CPU must be restarted by reset. The timing of input signals
at the RES and STBY terminals is shown in Fig. 26.
Table 4 lists the status of each parts of the MCU in each
low power dissipation modes. Transitions between each mode
are shown in Fig. 27.
(Note)
When I bit of condition code register is "I" and interrupt
(INT, TIMER/INT 2, SCI/TIMER 2) is held, MCU does not
enter WAIT mode by the execution of WAIT instruction.
In that case, after the 4 dummy r.ycles MCU executes the next
instruction.
In the same way, when external interrupts (INT, INT 2) are
held at the bit I set, MCU does not enter STOP mode by the
execution of STOP instruction. In that case, also, MCU executes
the next instruction after the 4 dummy cycles.
670
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6305Y1 ,HD6305Y2
Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop
Initialize
CPU, TIMER, SCI,
1/0 C!nd All
Other Functions
No
No
1=1
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 23 Wait Mode Flow Chart
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
671
HD6305Y1,HD6305Y2------------------------------------------------------
Stop Oscillator
and All Clocks
No
Turn on Oscillator
Wait for Time Delay
to Stabilize
Turn on Oscillator
Wait for Time Delay
to Stabilize
1=0
1=1
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 24 Stop Mode Flow Chart
672
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------HD6305Yl,HD6305Y2
O,dll"",
E
1111111111111111111111111111
II
(~
~r-\---+1-. . . .~
I
Time required for oscillation to become
stabilized (built·in delay time)
Interrupt
STOP instruction
executed
Instructions
restart
(a) Restart by Interrupt
Oscillator
E
111111111111111111111111111 II
~~~~
Time required for oscillation to become
STOP instruction
executed
stabilized (tos c )
Reset
start
RES
(b) Restart by Reset
Figure 25
Timing Chart of Releasing from Stop Mode
'---------lHl-
_--.J!
;
I
I
I
~_~
__I __II
~
~~
____________
~~
_______________-+____________- - J
tosc
Figure 26
Table 4
Restart
Timing Chart of Releasing from Standby Mode
Status of Each Part of MCU in Low Power Dissipation Modes
Condition
Mode
WAIT
-
Start
Software
STOP
Standby
Hardware
Escape
1/0
Oscil·
lator
CPU
Timer.
Serial
Register
RAM
WAIT in·
struction
Active
Stop
Active
Keep
Keep
Keep
STBY, RES, INT.INT2.
each interrupt request of
TIMER. TIMER 2 • SCI
STOP instruction
Stop
Stop
Stop
Keep
Keep
Keep
STBY. RES. INT, INT2
STBY="Low"
Stop
Stop
Stop
Reset
Keep
High impedance
terminal
STSY="High"
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
673
HD6305Y1,HD6305Y2------------------------------------------------------
Figure 27
Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset
-BIT MANIPULATION
The MeU can use a single instruction (BSET or BCLR) to
set or clear one bit of the RAM within page 0 or an I/O port
(except the write-only registers such as the data direction
register). Every bit of memory or I/O within page 0 ($00 $FF) can be tested by the BRSET or BRCLR instruction;
depending on the result of the test, the program can branch to
required destinations. Since bits in the RAM on page 0, or I/O
can be manipulated, the user may use a bit within the RAM on
page 0 as a flag or handle a single I/O bit as an independent
I/O terminal. Fig. 28 shows an example of bit manipulation
and the validity of test instructions. In the example, the program is configured assuming that bit 0 of port A is connected
to a,zero cross detector circuit and bit I of the same port to
the trigger of a triac.
The program shown can activate the triac within a time of
lOJ..ls from zero-crossing through the use of only 7 bytes on
the ROM. The on-chip timer provides a required time of
delay and pulse width modulation of power is also possible.
SE l F 1.
Figure 28
BRClR 0, PORT A, SELF 1
BSET 1 , PORT A
BClR 1, PORT A
Exa.:nple of Bit Manipulation
-ADDRESSING MODES
Ten different addressing modes are available to the MCU.
• Immediate
See Fig. 29. The immediate addressing mode provides
access to a constant which does not vary during execution of
the program.
This access requires an instruction length of 2 bytes. The
674
effective address (EA) is PC and the operand is fetched from
the byte that follows the operation code.
• Direct
, See Fig. 30. In the direct addressing mode, the address of
the operand is contained in the 2nd byte of the instruction.
The user can gain direct access to memory up to the lower
255th address. 192 byte RAM and I/O registers are on page 0
of address space so that the direct addressing mode may be
utilized.
• Extended
See Fig. 31. The extended addressing is used for referencing to all addresses of memory. The EA is the contents of
the 2 bytes that follow the operation code. An extended
addressing instruction requires a length of 3 bytes.
• Relative
See Fig. 32. The relative addressing mode is used with
branch instructions only. When a branch occurs, the program
counter is loaded with the contents of the byte following the
operation code. EA = (PC) + 2 + ReI., where ReI. indicates a
signed 8-bit data following the operation code. If no branch
occurs, ReI. = O. When a branch occurs, the program jumps
to any byte in the range + 129 to -127. A branch instruction
requires a length of 2 bytes.
• Indexed (No Offset)
See Fig. 33. The indexed addressing mode allows access
up to the lower 255th address of memory. In this mode, an
instruction requires a length of one byte. The EA is the
contents of the index register.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
I
------------------------------------------------------HD6305Y1,HD6305Y2
e Indexed (S-bit Offset)
See Fig. 34. The EA is the contents of the byte following the operation code, plus the contents of the index register.
This mode allows access up to the lower 511 th address of
memory. Each instruction when used in the index addressing
mode (8-bit offset) requires a length of2 bytes.
elndexed 06-bit Offset)
See Fig. 35. The contents of the 2 bytes following the
operation code are added to content of the index register
to compute the value of EA. In this mode, the complete
memory can be accessed. When used in the indexed addressing mode (I6-bit offset), an instruction must be 3 bytes long.
e Bit Set/Clear
See Fig. 36. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
O. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte that follows the operation code
indicates an address within page O.
I
If $F8
~
=
A
1
~
PROG LOA
elmplied
See Fig. 38. This mode involves no EA. All information
needed for execution of an instruction is contained in the
operation code. Direct manipulation on the accumulator
and index register is included in the implied addressing mode.
Other instructions such as SWI and RTI are also used in this
mode. All instructions used in the implied addressing mode
should have a length of one byte.
~I
Memory
.
e Bit Test and Branch
See Fig. 37. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. Individual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relative value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code register.
1::CJ
I~_~c:A
F8
Index Reg
I
Stack Point
058[t:~~~~_ _ _ _ _---.J
Prog Count
058F'"
05CO
CC
I---';";;~-f
~
,
,
Figure 29
Example of Immediate Addressing
Memory
A
CATFC8320048~~c:~~--1_---~~-----1~~20~;J
Index
Stack
PROG LOA CAT 0520
052E t-~:---t
eg
!;-:~o:"!":in: -t- - " ,
Prog !ount
052F
cc
~
,
,
1
!
Figure 30
$
Example of Direct Addressing
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
675
HD6305Y1 ,HD6305Y2 - - - - - - - - - - - - - - - - - - - - - - - - - - -
Memory
0000
A
40
Index Reg
I
Stack POint
CAT FCB 64 06E5~......::~-.r---------'
-Figure 31
Prog Count
040C
CC
Example of Extended Addressing
A
PROG BEQ PROG2 04A 7
04A81----:;,;----4
Figure 32
Example of Relative Addressing
TABL FCC LI 00B8
4C
B8
Stack POint
Prog Count
05F5
CC
Figure 33
676
Example of Indexed (No Offset) Addressing
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6305Y1 ,HD6305Y2
TABL FCB
FCB
FCB
FCB
BF
86
DB
CF
0089
008A
008B
008C
CF
Index Reg
03
Stack POint
E6
89
PROG LOA TABL X 0758
075C
Prog Count
075D
CC
Figure 34
Example of Index (8-bit Offset) Addressing
~
DB
Index Reg
02
PROG LOA TABL X 0 6 9
02
6§
'
'
I
0693
07
~
0694
7E
TABL
.
.
:~: :~ ~~~~ ~==i;[::-i:t----------~
FCB
FCB
Stack POint
Prog Count
0695
CC
DB 07801CF 0781 ~....;;.:.....-~
Figure 35
PORT B EQU 1 0001
Example of Index 06-bit Offset) Addressing
t-....;;.~--r-,
Index Reg
I
PROG BCLR 6 PORT B 058F
0590
t=j1~0=j-_ _ _ _J
Stack POint
01
Prog Count
0591
CC
~
,
,
Figure 36
Example of Bit Set/Clear Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
677
HD6305Y1,HD6305Y2------------------------------------------------------
PORT C EQU 2.00021-...;.;;;....--1
Index Reg
I
Stack POint
PROG BRCLR 2.PORT C.PROG 2 0574
05 751---;~-~ I
0576
Prog
~:::j~dt
Figure 37
,
,"OG ' ' " 0'"
bount
0594
CC
Example of Bit Test and Branch Addressing
Memory
~
~
§
I
I
I
I
I
I
I
I
Figure 38
Example of Implied Addressing
-INSTRUCTION SET
There are 62 basic instructions available to the HD6305Y
MeU. They can be classified into five categories: register/
memory, read/modify/write, branch, bit manipulation, and
control. The details of each instruction are described in
Tables 5 through II.
• Register/Memory Instructions
Most of these instructions use two operands. One operand
is either an accumulator or index register. The other is derived
from memory using one of the addressing modes used on the
HD6305Y MeU. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump
instruction (JSR). See Table 5.
• Read/Modify/Write Instructions
These instructions read a memory or register, then modify
or test its contents, and write the modified value into the
memory or register. Zero test instruction (TST) does not
write data, and is handled as an exception in the read/modify/
write group. See Table 6.
678
• Branch Instructions
A branch instruction branches from the program sequence
in progress if a particular condition is established. See Table 7.
• Bit Manipulation Instructions
These instructions can be used with any bit located up to
the lower 255th address of memory. Two groups are available;
one for setting or clearing and the other for bit testing and
branching. See Table 8.
• Control Instructions
The control instructions control the operation of the MeU
which is executing a program. See Table 9.
• list of Instructions in Alphabetical Order
Table 10 lists all the instructions used on the HD6305Y '"
MeU in the alphabetical order.
• Operation Code Map
Table 11 shows the operation code map for the instructions
used on the MeU.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------HD6305Yl,HD6305Y2
Table 5
Register/Memory Instructions
Addressing Modes
Indexed
Operations
Mnemonic
Immediate
Extended
Direct
Indexed
OP #
-
OP #
- OP
#
-
OP #
-
OP #
Load A from Memory
LOA
A6 2
2 B6 2
3 C6
3
4
F6
I
3
E6
2
4
Load X from Memory
LOX
AE
2
2
BE
2
3
CE
3
4
FE
I
3
EE
2
4
DE
3
5
M~X
Store A in Memory
STA
-
-
-
B7
2
3 C7
3
4
F7
I
4
E7
2
4
07
3
5
A~M
-
-
-
OF
#
-
06 3
5
- OP
Condition
Code
Booleanl
Arithmetic
Operation
Indexed
(No Offset) (S-Bit Offset) 116-Bit Offset)
H
·
I
•
• •
•
• •
•
M~A
N
Z
1\
/\
/\
/\
/\
C
•
•
•
•
Store X in Memory
STX
BF
2
3
CF
3
4
FF
I
4
EF
2
4
3
5
X~M
·
/\
/\
/\
Add Memory to A
ADO
AB 2
2 BB
2
3
CB 3
4
FB
I
3
EB
2
4 DB 3
5
A+M-·A
1\
/\
.'
to A
AOC
A9
2
2
B9
2
3 C9
3
4
F9
1
3
E9
2
4
09 3
5
A+M+C-A
/\
1\
1\
/\
Subtract Memory
SUB
AO 2
2
BO
2
3 CO 3
4
FO
1
3
EO
2
4
DO 3
5
A-M~A
/\
1\
t,
A with Borrow
SBC
A2
2
2
B2
2
3 C2
AND Memory to A
AND
A4 2
2
B4
2
3
OR Memory with A
ORA
AA 2
EOR
A8
CMP
1\
Add Memory and Carry
•
• •
Subtract Memory from
3
4
F2
1
3
E2
2
4
02
3
5
A-M-C-A
C4 3
4
F4
I
3
E4
2
4
04 3
5
A
2 BA 2
3 CA 3
4
FA
I
3
EA
2
4 OA 3
5
A+M~A
2
2
B8
2
3 C8 3
4
F8
I
3
E8
2
4
08 3
5
A-t-M~A
Al
2
2
Bl
2
3 Cl
3
4
Fl
I
3
El
2
4
01
3
5
A-M
CPX
A3
2
2
B3
2
3 C3
3
4
F3
I
3
E3
2
4
03 3
5
X-M
A (L091cal Compare)
BIT
AS
2
2
85
2
3 C5
3
4
F5
I
3
E5
2
4
05 :!
5
A ·M
Jump Unconditional
JMP
8C
2
2 CC 3
3
FC
I
2
EC
2
3 DC 3
4
Jump to Subroutine
JSR
BO 2
5 CD 3
6
FO
I
5 ED 2
5 DO 3
6
• •
• •
• •
·M~A
1\
1\
t,
f'
1\
1\
• •
/\
f'
• •
f'.
t
.~
1\
f'.
/\
1\
•
•
Exclusive OR Memory
with A
·
Arithmetic Compare A
with Memory
Arithmetic Compare X
with Memory
·•
Bit Test Memory with
• •
•
• • • • •
• • • • •
1\
1\
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
Table 6
Read/Modify/Write Instructions
Addressing Modes
Indexed
Operations
Mnemonic
Imphed(A)
Imphed(X)
Oorect
Booleanl Arithmetic Operation
OP #
-
OP
:I
- OP
#
- OP
II
- OP
II
-
Increment
INC
4C
I
2
5C
1
2
3C
2
5
7C
I
5
6C
2
6
A + 1 ~A or X + I
or M + I
~M
~X
or M -1
~M
Decrement
DEC
4A
1
2 5A 1
2
3A 2
5
7A
1
5
6A
2
6
A-I
CLR
4F
1
2
SF
1
2
3F
2
5
7F
1
5
6F
2
6
OO~A
Complement
COM
43
I
2
53
I
2 33 2
5
73
I
5
63
2
6
A~A or X~X or M~M
~A
or X-I
~X
Clear
or
OO-A~A
Negate
(2's Complement)
NEG
40
I
2
50
1
2
2
5
70
I
5
60
2
6
Rotate Left Thru Carry
ROL
49
I
2
59
1
2 39 2
5
79
1
5
69
2
6
Rotate Right Thru Carry
ROR
46
I
2 56 1
2
5
76
I
5
66
2
6
30
36
2
Condition
Code
Indexed
(No Offset) IS-Bit Offset)
or
OO~X
or
or
OO~M
H
I
•
•
•
•
•
•
•
•
N
Z
1\
/\
/,
t
0
I
C
•
•
•
I
1\
OO-X~X
OO-M~M
AOfjOfM
L5t I II
boiJ
II I
• •
• •
LriHb' I H'3"':"1 Ibo~ • •
b,
bo
c
•
[]-I I ~Of:Xr~ I I t-0
b,
0., I H·3~MI I KJ • •
bo
[fb'
:1 H'Hul I 1-0 • •
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
/\
/\
0
1\
1\
C
Logical Shift Left
Logical Shift Right
LSL
LSR
48
44
I
I
2 58 I
2
54
I
2
2
38
34
2
2
5
5
78
74
I
I
5
68
2
6
boo
5
64
2
6
C
·
C
Arithmetic Shift Right
ASR
47
I
2
57
1
2
2
5
77
I
5
67
2
6
Arithmetic Shift Left
ASL
48
I
2
58
I
2 38 2
5
78
I
5
68
2
6
Equal to LSL
TST
40
I
2 50
I
2 3D 2
4
70
I
4
60 2
5
A-OO '" X-OO or M-OO
37
/\
1\
II.
• •
II.
II.
II.
• •
II.
II.
•
Test for Negative
or Zero
Symbols: Op = Operation
# = Number of bytes
= Number of cycles
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
679
HD6305Yl,HD6305Y2-----------------------------------------------------Table 7 Branch Instructions
Addressing Modes
Mnemonic
Operations
Relative
OP
#
-
Branch Always
BRA
20
2
3
None
Branch Never
BRN
21
2
3
None
Branch IF Higher
BHI
22
2
3
C+Z=O
Branch IF Lower or Same
BLS
23
2
3
C+Z=l
Branch IF Carry Clear
BCC
24
2
3
C=O
(BHS)
24
2
3
C=O
C=l
(Branch IF Lower)
Branch IF Not Equal
I
N
• •
• •
• •
• •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
H
(Branch IF Higher or Same)
Branch IF Carry Set
Condition Code
Branch Test
BCS
25
2
3
(BlO)
25
2
3
C=l
BNE
26
2
3
Z=O
•
•
•
•
•
•
BEQ
27
2
3
Z=l
Branch IF Half Carry Clear
BHCC
28
2
3
H=O
Branch IF Half Carry Set
BHCS
29
2
3
H=l
Branch IF Plus
BPl
2A
2
3
N=O
Branch IF Minus
BMI
2B
2
3
N=l
BMC
2C
2
3
1=0
BMS
20
2
3
1=1
Bil
2E
2
3
INT=O
•
•
•
Branch IF Equal
•
•
•
•
•
•
Branch IF Interrupt Mask
Bit is Clear
Branch IF Interrupt Mask
Bit is Set
Branch IF Interrupt Line
is low
Branch IF Interrupt Line
is High
BIH
2F
2
3
INT=l
Branch to Subroutine
BSR
AD
2
5
--
Z
C
•
•
•
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• • •
• • •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
Table 8 Bit Manipulation Instructions
Operations
Addressing Modes
Boolean/
Branch
Bit Test and Branch Arithmetic
Bit Set/Clear
Test
Operation
OP
OP
~
~
BRSET n(n=0···7)
- Mn=1
2·n
3 5
BRClR n(n =0···7)
- - 01+2·n 3 5
Mn=Q
BSET n(n =0···7)
- 1--Mn
10+2·n 2 5
BClR n(n=0···7)
11 +2·n 2 5
O--Mn
Mnemonic
-
Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear Bit n
-
Condition Code
H
I
N
Symbol.: Op· Operation
# • Number of byte.
- • Number of cycle.
680
Z
C
• • • •
• • • •
• • • • •
• • • • •
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
/\
f\
------------------------------------------------------HD6305Y1,HD6305Y2
Table 9
Control Instructions
Addressing Modes
Operations
Mnemonic
Transfer A to X
TAX
Implied
Condition Code
Boolean Operation
OP
#
-
97
1
Transfer X to A
TXA
9F
1
2
2
Set Carry Bit
SEC
99
1
1
1-+C
Clear Carry Bit
CLC
98
1
1
Set Interrupt Mask Bit
SEI
9B
1
Clear Interrupt Mask Bit
CLI
9A
1
2
2
O-+C
1-+1
Software Interrupt
SWI
83
1
10
Return from Subroutine
RTS
81
1
5
Return from Interrupt
RTI
80
1
8
A-+X
X-+A
0-+1
Reset Stack Pointer
RSP
9C
1
2
$FF->SP
No-Operation
NOP
90
1
1
Advance Prog. Cntr. Only
2
4
4
Converts binary add of BCD charcters onlo
BCD format
Decimal Adjust A
Stop
Wait
SymbOls: Op = Operation
# = Number of bytes
a Number of cycles
OAA
80
1
STOP
8E
1
WAIT
SF
1
H
I
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•1
N
•
•
•
•
•
0
•
1
•
• •
? ?
• •
• •
•
• •
• •
A
Z
C
• •
•
•
•
•
•
•
•
?
•1
0
•
•
•
•?
• •
• •
• •
• •
A
A*
• Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.)
Table 10 Instruction Set (in Alphabetical Order)
Addressing Modes
Condition Code
Bit
Mnemonic
Implied
Immediate
Direct
x
x
x
x
x
x
x
x
ADC
ADD
AND
ASl
ASR
x
x
Extended Relative
x
x
x
Indexed
Indexed
Indexed
Set!
Test &
(No Offset)
(B-Bit)
(16-Bit)
Clear
Branch
x
x
x
x
x
x
x
x
x
x
X
x
(BHS)
x
x
x
x
x
x
BIH
x
BCS
BEQ
BHCC
BHCS
BHI
x
Bil
BIT
x
x
x
x
x
x
(BlO)
Bl'S
x
x
BMC
BMI
BMS
x
BNE
BPl
x
x
BRA
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
x
x
I
N
Z
•
/\
/\
/\
/\
/\
/\
/\
x
BClR
H
A
•
• •
X
x
BCC
Bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
C
•
•
•
• • • •
• • • •
• • • •
/\
(\
/\
/\
/\
1\
/\
/\
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
•
•
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
1\
1\
(to be continued)
C
A
•?
Carry i Borrow
Test and Set if True, Cleared Otherwise
Not Affected
load CC Register From Stack
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
681
HD6305Yl,HD6305Y2------------------------------------------------------Table 10 Instruction Set (in Alphabetical Order)
Condition Code
Addressing Modes
Bit
Mnemonic
Implied
Immediate
Direct
Extended Relative
Indexed
Indexed
Indexed
Set
Test &
(No Offset)
(8-Bit)
(16-Bit)
Clear
Branch
x
BRN
x
x
BRCLR
BRSET
x
BSET
x
BSR
CLC
CLI
CLR
x
x
x
DEC
x
x
EOR
INC
x
x
x
x
CPX
DAA
x
x
x
x
x
x
CMP
COM
x
x
x
JMP
x
JSR
LDA
x
x
LDX
x
LSL
x
x
x
LSR
NEG
x
x
x
x
NOP
x
x
ORA
ROR
x
x
RSP
x
RTI
x
x
ROL
RTS
SEI
x
TST
TXA
WAIT
x
x
x
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
Interrupt Mask
Negative (Sign Bit)
N
Z
Zero
682
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SUB
TAX
x
x
x
x
x
x
x
STX
SWI
x
x
x
x
x
H
I
N
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•1
/\
/\
/\
f\
1\
1
1\
"-
/\
7
STA
STOP
x
x
x
x
SBC
SEC
Bit
x
C
1\
•
7
/\
/\
•
•0
•
•
A
1\
1\
1\
1\
f\
A-
•
•
'\ •
• • •
• • •
f\
•
•
1\
f\
1\
1\
1\
1\
f\
0
f\
1\
f\
f\
1\
• • •
1\
'\
•
/\
1\
1\
1\
f\
f\
• • •
7
7
7
• • • •
• 1\ 1\ f\
• • • 1
1
• • •
• f\
• •
• 1\
•
1
•
• •
• 1\
• •
• •
1\
Carry Borrow
Test and Set If True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
1\ •
• •
f\ •
1\ 1\
• •
• •
1\ •
• •
• •
- - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6305Y1 ,HD6305Y2
Table 11 Operation Code Map
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Bit Manipulation
Test &
Set/
Branch
Clear
1
0
BRSETO
BSETO
BRClRO
BClRO
BRSETl
BSETl
BRClRl
BClRl
BRSET2
BSET2
BRClR2
BClR2
BRSET3
BSET3
BRClR3
BClR3
BSET4
BRSET4
BRClR4
BClR4
BSET5
BRSET5
BRClR5
BClR5
BRSET6
BSET6
BRClR6
BClR6
BRSET7
BSET7
BRClR7
BClR7
3/5
2/5
(NOTES)
Read,Modify /Write
Branch
Rei
2
BRA
BRN
BHI
BlS
BCC
BCS
BNE
BEQ
BHCC
BHCS
BPl
BMI
BMC
BMS
Bil
BIH
2/3
DIR
3
TST(-11
2/5
Control
Register !Memory
,XC IMP IMP IMM DIR EXT ,X2 ,Xl
7
A
8
9
C
D
E
B
RTI' SUB
RTS' CMP
SBC
SWI' COM
CPX
AND
lSR
BIT
ROR
lDA
-- TAX' ASR
STA
EOR
lSl/ASl
ClC
ADC
ROl
SEC
ClI*
ORA
DEC
SEI*
ADD
RSP' JMP(-l)
INC
TST
TST(-l) DAA' NOP BSR' JSR(+2) JSR(+l)
lDX
STOP' WAIT' TXA' ClR
STX
1/2 1/2 2/6 1/5 1/' 1/1 2/2 2/3 3/4 3/5 2/4
A
4
X ,Xl
5
6
NEG
,XC
F
-- HIGH
0
1
2
3
STA(+1)
l
o
4 W
5
6
7
8
9
JSR(+21
A
B
C
D
E
STX(+1) F
1/3
1. "-" is an undefined operation code.
2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).
The number of cycles for the mnemonics asterisked (0) is as follows:
RTI
8
TAX
2
RTS
5
RSP
2
SWI
10
TXA
2
DAA
2
BSR
5
STOP
4
ell
2
WAIT
4
SEI
2
3. The parenthesized numbers must be added to the cycle count of the particular instruction.
• Additional Instructions
The following new instructions are used on the HD6305Y:
DAA Converts the contents of the accumulator into BCD
code.
WAIT Causes the MCV to enter the wait mode. For this mode,
see the topic, Wait Mode.
STOP Causes the MCV to enter the stop mode. For this mode,
see the topic, Stop Mode.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
683
HD63L05F1------CMOS MCU (Microcomputer Unit)
The HD63LOSFI is a CMOS single·chip microcomputer suit·
able for low-voltage and low·current operation. Having CPU
functions similar to those of the HMCS6800 family, the
HD63LOSFI is equipped with a 4k bytes ROM, 96 bytes RAM,
I/O, timer, 8 bits A/D, and LCD (7 X 7 segments max.) drivers,
all on one chip.
• HARDWARE FEATURES
• 3V Power Supply
• 8·Bit Architecture
• Built·in 4k Bytes ROM (Mask ROM)
• Built·in 96 Bytes RAM
• 20 Parallel 1/0 Ports
• Built·in 7 x 7 Segments LCD Driver Capability
• Built·in 8·Bit Timer
• Built·in 8·Bit AID Converter
• Program Halt Function for Low Power Dissipation
• Stand·by Input Terminal for Data Holding
•
•
•
•
HD63L05F1F
SOFTWARE FEATURES
An Instruction Set Similar to That of The HMCS6800
Family (Compatible with The HD6805S)
HMCS6800 Family Software Development System is Appli·
cable
PIN ARRANGEMENT (Top View)
XOUT
NUM
TIMER 3
VRH 4
VRL
CC I
CC 2
NC
E
V CH 1
CHI 11
V I /CH 7 /0 19
SEG I7 /CH 2 1
SEG 16 /CH 3 1
V 2/CH s/O IS 1
SEG 15 /CH 4 1
NC
SEG I4 /CH s 1
SEG 13 /CH 6 1
SEG 12 2
SEG II 21
SEG lo 2
SEG 9 2
SEG s
SEG 7 2
SEG 6 2
SEG s
SEG.
SEG 3
SEG 2
SEG I 31
NC 3
684
1
HD63L05F1P
37
XIN
Vee
SB
INT
RES
Vss
EXTAL
XTAL
NC
A7
A6
As
A4
A3
A2
AI
Ao
B7
B6
Bs
B4
B3
B2
BI
Bo
C3
C2
CI
Co
COM 3
COM 2
COMI
(FP·80)
.i..J«.(.{.i.'i.(.c'itiicOrDcOrDrD
~~~:::f!.~!::::~;.
::::;:~
...
NC
NC
NC
Vss
RES
iNT
58
NC
Vcc
HD63L05F1F
XIN
NC
NC
VRH
VRL
CC,
cc,
NC
.1
VCH
~~~~~g;;;~~~~~~
Q5
£"1
(!l
_ U
i
~
(!l
~5 ui
r:
:
U
(!l
(!l
M
i
u
~:
-
~
~
-.
(!l (!l (!l (!l (!l
G ~~~~~;?~~~~~~~~~
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
SEG.
-------------------------------------------------------------HD63L05F1
• BLOCK DIAGRAM
Common
Driver
Output
COM,
COM.
COM.
Data
Latch
LCD1
SEG,
SEG.
LCD2
SEG.
SEG.
8
9:l
LCo3
XIN
SEG s
SEG.
SEG 7
SEG •
;
8
0
.~
XOUT
c5
LCD4
SEG9
SEGIO
E
CD
E
CII
LCo5
SEG"
SEGu
Jl
SEG 13
SEG,.
SEG ..
SEG u
SEG"
LCo6
NUM
LCD7
Le08
TIMER
4
e
8
0
.~
!!
CD ..
1;0
Accumulator
0
u
A
8
«~
~ '5,
Q..~
e
0
'z ...
U
Condition
Code Reg.
~t;
~a:
0
System
8 Cont. Reg.
X
8
"CD
o 'g>
>
e
0
Index
Register
Ao
A,
A.
A3
A.
As
A.
A7
~CD
CCR
5
o~
<~u
<
-CH,
(CH,I
(CH.I
(CH.I
(CHsI
(CH.I
(CH 71
(CH.I
CPU
Stack
Pointer
0
5
SP
4
Program
Counter
"High" PCH
8
Program
Counter
"Low" PCL
e
0
';::
ALU
~
e!
Ill!!
;a:
Q..~
i5'~
~ 's,
0
Bo
B,
B.
B.
B.
Bs
B.
B7
e
0
';:
~
~!
i5'~
~a::
0
U!!
~'&
Q..~
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
Co
C,
C.
C.
685
HD63L05F1
•
ABSOLUTE MAXIMUM RATINGS
Unit
Value
Symbol
Item
Supply Voltage
Vee
-0.3-+5.5
V
Input Voltage
Yin
-0.3 - Vee+0.3
V
Output Voltage
V out
-0.3 - Vee+0.3
V
Operating Temparature
Topr
-20 - +75
Storage Temparature
Tstg
-55 - +125
°c
°c
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded.
Normal operation should be under recommended operating conditions.
If these conditions are exceeded, it could affect reliability of LSI.
•
ELECTRICAL CHARACTERISTICS (Vee = 3.0V ±O.SV, Vss
unless otherwise noted.)
•
DC CHARACTERISTICS
Item
Connect C L - 0.5J.LF to
V eH
= 3.0V,
min
typ
max
Unit
V ee -O·3
-
Vee
V
-
Vee
V
TIMER
O.SVee
-
Vee
V
NUM (Normal Mode)
Vee-0 .2
-
Vee
V
Vee- 2 . 1
-
Vee- 1.S
V
Vss
-
0. 2V ee
V
Vss
0. 2V ee
0.2
V
Vss
-
0.5V ee-0.2
-
0.5Vee+0 .2
V
3
15
30
J.LA
-
-
1.0
J.LA
-
100
200
J.LA
-
40
SO
J.LA
2
5
J.LA
-
200
600
J.LA
-
120
200
J.LA
-
60**
100**
J.LA
-
2
5
J.LA
-
220
600
J.LA
-
-
0.3
V
V IH
= 0.5J.LF to
Connect C L
V eH
RES, INT, S8
V IL
TIMER
NUM (Test Mode)
Self Check Input
Voltage
NUM (Self Check Mode)
VIM
Input Pull-Up
Current
RES (lNT: Mask Option)
NUM
-IR1
Vee
Input Leakage
Current
TIMER, S8
IIINI
Yin
Crystal*
Oscillation
Current Dissipar--tion
RC*
Oscilla·
tion
During
System
Operation
At Halt
lee1
At Standby
At AID
Operation
During
System
Operation
At Halt
~---
E
= 3.0V,
= OV -
Yin
= OV
Vee
f = 400kHz
No load.
Tested after setting
up the internal status
by self check.
R = 100kS1
No load.
lee2
At Standby
At AID
Operation
Output "Low"
Level Voltage
+75°C, typ means typical value at Vee
0.5V ee +0.9
RES, INT, S8
XTAL, XIN
Input "Low"
Level Voltage
Test Condition
Symbol
XTAL, XIN
Input "High"
Level Voltage
= OV, Ta = -20 -
VOL
Tested after setting
up the internal status
by self check.
IOL
= 30J.LA
• Depends on the mask-option .
•• 60$£A -+ 30$£A and 100$£A -+ 60$£A when OSC1 is stopped by Halt.
686
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
V
---------------------------------------------------------------HD63L05F1
•
AC CHARACTERISTICS
Item
Symbol
Operating Clock Frequency
Cycle Time
fel
teye
Oscillation Frequency *
(Resistor Option)
fOSCR
External Clock Duty
Duty
Oscillation Start Time *
(Crystal Option)
Test Condition
R
= 100kil ±1%
= 10pF ±20%, Rs = lkil max
min
typ
max
Unit
100
400
500
kHz
8
10
40
p.s
300
400
500
kHz
45
50
55
%
tOSCf
Co
-
-
150
ms
Oscillation Start Time *
(Resistor Option)
tOSCR
R = 100kil±1%,
Connect C L = 0.5p.F to V CH
-
-
2
ms
Oscillation Start Time (32kHz) *
tOSC1
Cc3 = 10pF ±20%, Rs = 20kil max
-
-
1
s
-
10
pF
-
10
-
0
-
1
s
200
-
ms
t eye + 1
-
Test Condition
min
typ
max
CMOS Output, IOH = -100p.A
Key Load CMOS Output
IOH = -10p.A
IOL = 100p.A
Vcc-O.3
-
-
V
V cc "'{)·3
-
-
V
-
-
0.3
V
Vcc
V
Vss
-
0.2Vcc
V
-
-
1.0
p.A
4
20
40
p.A
I nternal Capacitance
of Oscillator
I
EXTAL
I
XOUT
Delay Time of Oscillation Delay
Time *
CD
tOLY
Selected by mask option
Reset Delay Time
tRLH
External Capacitance
RES Pulse Width*
tRWL
INT Pulse Width *
t,wL
TIMER Pulse Width
tTWL
= 2.2p.F
With 32kHz OSC
Without 32kHz OSC
When OSCl is not stopped by Halt
When OSCl is stopped by Halt
I n the case of counter
48
1.5tcyc + 1
t eye + 1
32
pF
p.s
p.s
p.s
p.s
p.s
* Depends on mask-option.
•
PORT CHARACTERISTICS
Item
Symbol
Port A, B, C
Output "High" Level Voltage *
Port A, B, C
V OH
Output "Low" Level Voltage
Port A. B. C
VOL
Input "High" Level Voltage
Port A, B, C
Input "Low" Level Voltage
Port A, B, C
V'H
V IL
Input t..eakage Current
Port A, B, C
Input Pull-Up Current *
Port A, B, C
IIINI
-IR2
0.8Vcc
Yin =
OV - VCC
Vcc = 3.0V,
Yin =
OV
Unit
* Depends on mask-option.
~HITACHI
Hitachi America Ltd. • 2210 OToole Ave. • San Jose, CA 95131 • (408) 435-8300
687
HD63L05Fl
•
LCD DRIVER OUTPUT CHARACTERISTICS (Vee
Item
= 3.0V, Vss = OV, Ta = -20 -
V OH1
Output "High" Level Voltage
Output "Low" Level Voltage
VI
typ
max
Unit
2.8
-
1.8
-
-
V
V
V OH2
V OH3
0.8
-
-
V
-
-
2.2
V
Segment
Vou
V OL2
-
-
1.2
V
-
0.2
V
-
V
1.8
-
V
0.8
-
-
-
-
2.2
V
-
1.2
V
-
-
0.2
V
45
90
180
kn
Vcc-0.3
-
-
V
-
-
0.3
V
VI
V OH1
Common
VI
V OH2
V OH3
Output "Low" Level Voltage
= 1.00V, V 2 = 2.00V
IOH = -lilA
min
Segment
V OL3
Output "High" Level Voltage
+7SoC, unless otherwise noted.)
Test Condition
Symbol
Vou
V OL2
Common
VI
V OL3
Dividing Resistor
R LCD
Output "High" Level Voltage * Segment
V OH
Output "Low" Level Voltage*
VOL
Segment
= 1.00V, V 2 = 2.00V
IOL = lilA
= 1.OOV, V 2 = 2.00V
IOH = -51lA
= 1.00V, V 2 = 2.00V
IOL = 51lA
Tested between V I and V 2
In the case of Output Port,
IOH = -301lA
In the case of Output Port,
IOL = 30llA
2.8
V
* Depends on mask-option.
Vee
VOH1
O.I"F
V2
VOH2
VI
VOH3
vss
Output Level of SEG and COM
688
Power Supply Circuit for LCD Display
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63L05F1
•
AID CONVERTER CHARACTERISTICS
(Vee
= 3.0V, Vss = OV, Ta = _20°C -
Symbol
Item
+7SoC, unless otherwise noted.)
Test Condition
min
typ
max
-
8
bit
+2
LSB
Vcc
V
-
V
V AH
V
Unit
V OYN
0.2
-
Vcc- 1.O
V
Ladder Resistor (V AH - VAd
RHL
40
80
160
kn
Conversion Time
tCNV
2
-
4
ms
-4
+4
LSB
-
-
60
p.s
Conversion Accuracy
Reference Voltage
I nput Voltage Range
Programmable
Voltage Comparison
O.2V
Vss
Resolution
Absolute Accuracy
-2
"High" Side
V AH
-
"Low" Side
VAL
Vss
V AH - VAL
6.V AEF
1.8
Input Range
V 1N
V RL
Input Dynamic Range
Judge Error
VAL = 0.2V2 or <7>32k)) at "'"
COUNTER (External clock) at "0"
- - - - - - - - - - - - - - <7>2 (frequency is 1/4 of OSC,) at "1"
<7>32k (frequency is '/12 of OSC, or 32.768 kHz) at "0"
Figure 6
Timer Control Register Configuration
Vee
-1V'"
R'S T"m'oo'_
1_
~VIL
-
1
V1H
"
-----
~--------~I
Built-in Reset
Figure 7
HD63L05F1
MCU
Figure 8
Input Reset Delay Circuit
Application of Power and Reset Timing
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
693
HD63L05F1
•
capability also provides the internal state of the MCV to measure the LSI current. After a system reset, the MCV goes into
each current measurement mode by the combination of the
control switches. The LSI current can be measured when the
NUM is returned to Vee after setting of the current mode.
SELF CHECK
The self check capability of the MCV provides an internal
check to detennine if the port is functional. Connect the MCV
as shown in. Figure 9 and monitor the output of port C bit 3
for an oscillation of approximately O.5Hz. This self check
+3V
Vee
LED
1l2Vee~ s.
-The connection of OSC1 and OSC2
depend on their mask option.
5,
Selection of 5witch
LSI Function
During
operation
LSI
Current
50
5,
5,
5,
5.
S,
S.
S,
X
X
X
X
X
X
(!)
0
0
X
X
X
O"'X
X
(,) ... m
X
X
Halt
0
0
0
X
O"'X
X
'1)"'0
AID
0
0
X
X
O"'X
X
1D~0
X
Standby
0
0
0
X
O"'X
X~
1D~0
X
X: OFF
o
... : Change the state
:ON
Figure 9 Self Check Connections
•
INTERNAL OSCILLATOR OPTIONS
The MCU incorporates two oscillators: Oscillator I for system clock supply and Oscillator 2 for peripheral modules such
as time base, AID converter, LCD drivers, etc ..
•
crystal or resistor depending on the stability. A manufacturing
mask option is available to provide better matching between
the external components and the internal oscillator. The oscillator 1 can stop when power is applied in Standby mode. Figure
10 shows the connection. A resistor selection graph is given in
Figure 11 .
Oscillator 1 (OSC1; XTAL, EXTAL)
The internal oscillator circuit can be driven by an external
694
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD63L05F1
• Oscillator 2 (OSC2; XIN, XOUT)
Clocks for time base, LCD drivers, an A/D converter and a
timer are supplied by the OSC2 (32.768kHz crystal). In Halt
mode, OSC2 and frequency divider operate and permit the
operation of the peripheral modules with low power consumption. In Standby mode, the frequency divider is in reset state
but only OSC2 keeps on running to control the delay time
required when the MCV is released from Standby mode. Figure
12 shows the connection and the relation between oscillator 1
and oscillator 2 is shown Figure 13 and Table 1.
When OSC2 is not available in an user system, clocks for
time base, LCD drivers, a A/D converter and a timer are supplied by the OSCI through frequency divider. When OSC2
is not available or crystal option is selected for OSC I, OSC 1
can not be stopped in Halt mode.
Only when CR option is selected for OSC 1 and OSC2 is available in an user system, OSCI can be stopped in Halt mode.
(Note)
The accuracy of the time base (1 sec, 1/16 sec) is kept only
when OSC2 is 32.768kHz crystal oscillator.
Vee
10pF
EXTAL
Rs ; 1kn
c:::J
XTAL
HD63L05Fl
MCU
100kn
HD63L05Fl
MCU
RC Oscillator
Crystal Oscillator
EXTAL
EXTAL
Ext. Clock
Input
XTAL
Ext. Clock
Input
HD63L05Fl
MCU
HD63L05Fl
MCU
XTAL
Ext. Clock
Ext. Clock
Crystal Option
Resistor OPtion
Figure 10 Mask Option for Oscillator 1
500
400
~
300
I
\
\
Vee; 3.0V
Ta; 25°C
~
~
;
~
!
200
~
100
o
100
200
300
~
t--- r--
400
500
I--.
600
~
700
Resistance (kn)
Figure 11
Typical Resistor Selection Graph
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
695
HD63L05F1
XOUT
Rs
= 20kn c:J
HD63L05F1
MCU
XIN
10pF
CPU
Clock~
4
veeT
HALT---....I
Crystal Oscillator
STANDBY
Time base
Interrupt
XOUT
(Open)
XIN
Vee
HD63L05F1
MCU
Figure 13 Relation between Oscillator 1 and Oscillator 2
Not Used
Figure 12 Connection of Oscillator 2
Table 1 Oscillator 2 Mask-option and System Operation
When OSC 1 is Crystal
Mask Option
OSC2
Not Available
State
~
,.
During System
Operation
At Halt
At Standby
(NOTE)
0 ..... run
OSCl
0
0
X
CPU Peripheral OSCl
0
X
X
When OSCl is RC
OSC2
Available
0
CPU Peripheral OSCl
0
0
X
OSC2
Not Available
0
X
X
0
X
0
0
X
0
0
X
OSC2
Available
CPU Peripheral OSCl
0
X
X
CPU Peripheral
0
0
0
0
0
X
OorX
X
X
0
X
(m •• koption)
X
x ..... stop
Table 2 Mask-options of Oscillation Circuits and the Delay Time
Type of OSCl
Use of OSC2
Used
Used
Standby mode
Not used
Crystal Option
Not used
Used
CR Option
Not used
Delay Time of Restart (second)
Condition
Used
Standby mode
Not used
Oscillation
of OSCl
at HALT
Oscillation
of OSCl
at HALT
Stop
Continue
Stop
Continue
0
X
0
X
0
0
0
X
0
1/16
1/2
1
X
0
X
0
X
0
X
0
0
0
0
0
X
0
X
0
0
0
0
0
X
0
X
0
Note) Combinations of the mask-option indicated X is not available.
• STANDBY
When the STANDBY (SB) terminal becomes "High" level,
the MCV goes into standby mode at its instruction fetch cycle.
On standby mode, only 32 kHz oscillator (OSC2) keeps on
running while the others are stopped with holding the current
data except A/D converter, timer, and time base. Restarting
696
of the MeV from standby mode is controlled by the Delay Time
which is available by counting the OSC2 oscillation or 1/12
frequency of the aSCI in frequency divider after the STANDBY terminal turned to "Low" level. Therefore, the CPU restarts
operation from the previous state after the Delay Time (0 sec,
1/16 sec, 1/2 sec, or 1 sec), and the accuracy of the Delay Time
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD63L05F1
is kept when OSC2 is 32.768 kHz crystal oscillator. When 1/12
frequency of aSCI is provided to the frequency divider, the
Delay Time depends on the stability of aSCI after restarting
from standby mode and is not acculate.
HARDWARE RESET
"1"'-'1
$7F .... SP
•
"0" -+ DDRs
Delay Time
CLR iNT Logic
SFF -+ Tim.r Data Reg.
Since aSCI stops in standby mode, it is needed to inhibit
restarting of CPU untill the aSCI oscillation is stabilized after
the STANDBY terminal has turned to "Low" level. To take
this stabilizing time of aSCI, user can select the Delay Time
out of 0 sec, 1/16 sec, 1/2 sec or 1 sec by mask-option depending on a combination in the Table 2. STANDBY terminal has to
be kept at "Low" when resetting the MCU and has to be kept
at "Low" during the Delay Time. Starting of the MCU by reset
is also controlled by the Delay Time.
•
$7F -+ Timer Prescaler
$7F -+ Timer Control Reg.
$48 .... AID Control Reg.
$63 -+ System Control Aeg.
"0" .... LCD!. LCD2. LCD3 Reg.
INTERRUPTS
There are six different interrupts to the MCU: external
interrupt via external interrupt terminal (INT), internal timer
interrupt, interrupt by termination of A/D conversion, time
base interrupt, and software interrupt by an instruction (SM).
When any interrupt occurs, processing is suspended, the present MCU state is pushed onto the stack, the interrupt bit (I) in
the condition code register is set, the address of the interrupt
routine is obtained from the appropriate interrupt vector
address, and the interrupt routine is executed. The interrupt (
service routines normally end with a return from interrupt
instruction (RTI) which allows the MCU to resume processing
L----r-.J
of the program prior to the interrupt. Table 3 provides a listing
of the interrupts, their priority, and the vector address that
contains the starting address of the appropriate interrupt
routine.
Figure 14 shows the system operation flow, in which the
portion surrounded with dot-dash lined contains interruption
execution sequence.
(Note)
A clear interrupt bit instruction (CLI) allows to suspend the
processing of the program by an interruption after execution
of the next instruction while a set interrupt bit instruction
(SEI) inhibits any interrupts before execution of the next
instruction. When a mask bit of a control register is cleared by
an instruction, interruption is allowed before execution of the
next instruction.
Standby
Operation
Sequence
Figure 14 System Operation Flowchart
Table 3
Interruption Priority
•
Interruption
Priority
Vector Address
Acknowledging an I NT in Halt mode
In HALT mode, the CPU is not operating but the peripherals
are operating. When an interruption is acknowledged, the CPU
is activated and executes interruption service matching the
interruption condition by means of vectoring.
RES
SWI
1
$FFE,$FFF
2
INT
3
$FFC,$EFD
$FFA, $FFB
TIMER
4
$FF8,$FF9
•
AID
S
$FF6,$FF7
TIME BASE
6
$FF4,$FFS
In Standby mode, the system is not operating with power
supplied to it, therefore, any interruption request (including
RES) is not acknowledged.
Acknowledging an INT in Standby mode
~HITACHI
Hitachi America Ltd, • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
697
HD63L05Fl
•
INPUT/OUTPUT
There are 20 input/output terminals, which are program
controlled by data direction registers for use as either input or
output. If an I/O port has been programmed as an output and
is read, then the latched logical level data is read even though
the output level changes due to the output load.
If a port is to be used as an input terminal, lhe user must
specify whether or not it will be equipped with a pull-up PMOS.
Figure 15 shows the port I/O circuit.
Bits of
Data
Direction
Register
Bit of Output Data
Output
State
Input to
CPU
0
0
0
3-State
Pin
Figure 15 Port I/O Circuit
0
•
Configuration of Port
Figure 16 shows the configuration of I/O ports. As the
output is on/off controlled by a data direction register. an I/O
port may directly be applied as an input terminal. No problem
is involved with the input if both "High" and "Low" levels
are applied', For only one level. the user must specify the use
of a pull-up PMOS for "Open/Low" input application.
Pull-up PMOS available
Pull-up PMOS not available
I[
Jli
--{>---o-
tv~
rVss~
:
I
r
•
-----L __ '-----' __
~
VSS
Vss
Vss
Figure 16 Selection of Input Configuration for I/O Port
698
$HITACfll
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD63L05F1
•
Only logical "0" can be written into this bit by software.
A/D CONVERTER
The MCU incorporates an 8 bits AID converter based on the
resistor ladder system. Figure 17 shows its block diagram.
The "High" side of reference voltage is applied to V RH ,
while the "Low" side of reference voltage is applied to V RL'
The reference voltage is divided by resistors into voltages matching each bit, which is compared with analog input voltage for
AID conversion. As the analog input voltage is applied to the
MOS gate of the comparator through the analog multiplexer,
this voltage comparison system achieves high input impedance.
The AID Data Register stores the results of an AID conversion or can be set 8 bit data for programmed comparator.
These functions are controlled by software-controlled AID
CTRL Register. The result of AID conversion is not assured
if the conversion is interrupted by STANDBY. Figure 18 shows
the configuration of the AID control register.
•
A/D Interrupt Request Flag (AID INT)
The AID INT bit is set to logical "I" after completion of
AID conversion and is cleared by program or by system reset.
•
A/D Interrupt Mask (A/D MASK)
If this bit is set, interrupt from the AID converter is not
acknowledged. This bit can be written by program.
•
A/D Conversion Flag (CNV)
To start auto AID conversion, set this bit to logical "I".
During conversion, data of this bit stays at "I". The bit is
automatically reset to "0" when the auto AID conversion ends.
In auto AID conversion, supply voltage is applied to the comparator only when CNV = "I". The digital data which is obtained by the AID conversion is held in the AID Data Register.
This data is reset when the CNY is set to "I" again.
•
A/D Operation Mode Select Bit (Auto/Program)
Used to select either auto-run 8 bits AID conversion or
8 bit programmed comparator operation (Auto 8 bits AID
conversion at ''0'').
Offset Compo Capacitor
Analog Input
CHI
(CH1)}
(CH,)
(CH.) MASK OPTION
(Cr')
(CHI)
( ) indicates that these channels are
shared the terminal with segment.
Reference
Input
MPX
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Data Bus
Channel
000
CHI
001
(CH , )
010
(CH,)
011
(CH.)
100
(CH.)
101
(CH.)
110
(CH,)
111
(CHI)
Figure 17 8 Bits A/D Converter Block Diagram
Figure 18 AID Control Register Configuration
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
699
HD63L05F1
•
Comparator Output (COMP OUT)
The result of comparator operation under program control
can be read from this bit (Logical "1" means that input voltage
is higher than programmed reference voltage).
•
Analog Input Channel Select Bits (MPX)
Used to select 8-channel analog inputs. The multiplexer is
an analog switch based on CMOS. Note that the analog inputs
from CH 2 to CHs are mask option while CHI is exclusive.
When 1/3 bias - 1/3 duty or static LCD is used, CH 7 and
CHs are not available because these two terminals are used for
LCD power supply as V I and V2 .
•
LCD CIRCUIT
The system configuration of the LCD circuits is shown in
Figure 19. Segment data for display are stored in data registers
LCDI to LCD8. Since the circuits are connected to the output
terminals via pin location block, the user may specify a combination of data to be multiplexed to the segment output terminals.
The bit data of the LCD register is combined with the timing
clock (4)1 , 4>2 or 4>3) and three combined bit data are gathered to
make a segment output data for 1/3 bias - 1/3 duty driving in
the pin location block. 10 case of static LCD drive or output
port, timing is always fIXed at 4>1 (always "High") and one bit
data of the LCD register is transferred for an output terminal.
Note that the output terminals from SEG 13 to SEG 17 are
mask option while the others (SEG 1 to SEG I2 ) are always available when the Duty bits are "a I " or "11".
When the form of output port is selected by Duty bit ("00"),
4>WRITE can be got every time data is written into LCDI
register in the case that EXT bit is "1". As LCDI register has
8 bits latches, it is easy to transfer the internal 8 bits data to
external devices via output por~s, with automatiCally generated
write clock 4>WRITE. The cycle clock pulse can be also available
as an internal data source for the output terminal when output
port is selected as 1/4 aSCI.
Assignment of segment terminals to the bits of the LCD
data register, including the case where they are used as output
terminals, is to be specified .by the user when he orders masks.
In case of static LCD or output ports, only LCD1, LCD2, and
LCD3 are allowed to be used. These registers are initialized at
"a" by system resetting.
•
LlaUID CRYSTAL DRIVER WAVEFORMS
The LCD circuit is based on 1/3 bias .:... 1/3 duty driving.
Figure 20 shows the common electrode output signal waveforms
(COM 1, COM 2 , COM 3 ), segment Signal waveforms (SEG I to
SEG I7 ) and LCD bias waveforms (between COM and SEGMENT).
SEG,
SEG,
Pin Location
Block
SEG.
SEG.
SEG.
SEG.
SEG,
SEG.
SEG.
SEG ..
SEGII
SEG ..
SEG ..
SEG ..
SEG"
SEG"
SEG"
SEG"-SEG,,
Mask Option
System
Cant.
Duty
Contents of
SEG, -SEG'7
00
OUTPUT PORT
01
STATIC LCD
10
---
11
1/3 Bias
1/3 Duty LCD
Data Reg.
COM,
COM,
COM,
SVS CTAL Reg.
Note)
Both of mask-option and software
control are needed to specify the
contents of SEG, - SEG'7.
Figure 19 LCD Circuit System Configuration
700
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD63L05Fl
Vee
2/3V e e- 1/3Vcc· =
--.-
COMMON 1
GNO'COMMON 2
COMMON 3
SEGMENT
11.2.31
COM1-SEGMENT
COM! -SEGMENT
COMI-SEGMENT
OUTPUT PORT
Vee
.Fb::
"1"
GND
STATIC LCD
Output levels
"0" mat~hlng Data in
Figure 20
•
~z
,..--,
J U U L
Register
>
Vee
Vss
LCD Driving Waveforms
BIT MANIPULATION
The MCU has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR)_ Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines.
(Note)
It is needed to pay attention to the system control register,
the timer control register, and AID control register when
BSET, BCLR, or Read/Modify/Write instructions are applied
to them. If own interrupt request occured onto the interrupt
request bit (bit 7) of the control register between read cycle and
write cycle of these instructions, the bit 7 might be cleared in
the write cycle and not acknowledged by CPU.
The instruction used for that purpose has a length of 2 bytes .
The effective address (EA) is PC. The operand is fetched from
the byte that follows the OP code.
•
Direct
See Figure 22. In direct addressing mode, the address of the
operand is contained in the second byte of the instruction.
The user can gain direct access to the LSB 256 of memory. All
RAM bytes, I/O registers. and 128 bytes of ROM are located
on page 0 in order to utilize this useful addressing mode.
•
Extended
See Figure 23. The extended addressing mode is used for
referencing to all addresses of memory. The EA consists of
the contents of the two bytes that follow the OP code. The
instruction used for extended addressing has a length of 3
bytes.
•
•
ADDRESSING MODE
There are 10 addressing modes available to the MCU for
programming_ Familiarize yourself with these modes by reading
the information and referring to the diagrams that follow.
•
Immediate
See Figure 21. In immediate addressing mode, constants
that will not change during execution of a program are accessed.
Relative
See Figure 24. Only Branch instructions are used in relative
addressing mode. When a branching takes place, the contents
of the byte next to the OP code are added to the program
counter. EA = (PC) + 2 + ReI., wh~re ReI. indicates signed 8 bits
data at the address following the OP code. When no branching
takes place, ReI. = O. When a branching occurs. the program
jumps to any byte of +129 to -127 of the current instruction.
The length of the Branch instruction is 2 hytes.
~HITACHI
\ Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
701
HD63l05F1
•
Indexed (without Offset)
See Figure 25. In this addressing mode, the lower 256 bytes
of memory are accessed. The length of the instruction used
for this mode is one byte. The EA consists of the contents of
the index register.
•
Indexed (8 Bits Offset)
See Figure 26. The EA consists of the contents of the byte
following the OP code, and the content~ of the index register.
In this mode, the lower addresses of memory up to 511 can be
accessed. Two bytes are required for the instruction.
•
Indexed (16 Bits Offset)
See Figure 27. The EA consists of the contents of the two
bytes following the OP code. and the contents of the index
register. In this mode. the whole of the memory can be accessed. The instruction using this addressing mode has a length of
3 bytes.
• Bit Set/Clear
See Figure 28. This addressing mode can be applied to any
instruction that permits'any bit on page 0 to be set or cleared.
The byte following the OP code indicates an address within
page O.
• Bit Test. Branch
See Figure 29. This addressing mode can be applied to instructions that test bits at the first 256 addresses ($00 to $FF)
and are branched by relative qualification. The byte to be tested
is addressed by the contents of the address next to the OP code.
The individual bits of the byte to be tested are designated by
the lower 3 bits of the OP code. The third byte indicates a
relative value that is to be added to the program counter when
a branch condition is satisfied. The instruction has a length
of 3 bytes. The value of the bit that has been tested is written
at the carry bit of the condition code register.
•
Implied
See Figure 30. There is no EA for this mode. All information
needed for execution of instructions is contained in the OP
code. Operations that are carried out directly on the accumulator and index register are included in the implied addressing
mode. In addition, the SWI and RTI instructions are also included in the group of this operation. The instruction using
this addressing has a length of one byte.
I
8
I
PROG LDA # $F8 05BE
05BF
A
,
,
Prog Count
AS
t-------t
05CO
F8
CC
I
,
~
,
I
I
Figure 21
702
Example of Immediate Addressing
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD63L05F1
~
lEA
Memory
i
i
I
i
I
i
i
i
I
i
I
i
I
oo4B
/
Adder
t
~
~
A
0000
20
CAT FCB 32 004B
1
I
I
PROG LOA CAT 0520
B6
052E
4B
-.
I
I
I
20
I
I
I
Stack Point
I
I
I
Index Reg.
Prog Count
052F
CC
@@
i
I
i
i
i
I
Figure 22 Example of Direct Addressing
Memory
i
I
I
@@
I
PROG
LOA CAT 0409
040A
040B
0000
A
I
~6 J____---'
40
Index Reg
.
06
E5
Stack Point
I
Prog Count
I
040C
40
CA T FCB 64 06E5
I------~
CC
Figure 23 Example of Extended Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
703
HD63L05F1
Memory
i
I
§
A
Index Reg
Stack Point
I
I
0000
PROG BEQ PROG2 04A7
27
04A8
18
§
I
I
,
,
Figure 24 Example of Relative Addressing
Memory
A
TABL FCC/LI/ 00B8
4C
4C
49
Index.Reg
B8
I
PROG
I
Stack Point
LDAX05F4~
Prog Count
05F5
CC
~
Figure 25 Example of Indexed (without Offset) Addressing
704
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------HD63L05F1
lEA
,,
Melorv
i
,
BF
FCB # 86 008A
86
FCB # DB 008B
DB
FCB # CF 008C
CF
,
f
/
Adder
I
,
I
I
oose
I
I
TABL FCB # BF 0089
I
'"
I
A
J
I
CF
I
Index Reg
I
I
I
03
Stack Point
PROG LOA TABl.X 075B
E6
075C
89
I
I
Prog Count
I
I
I
0750
CC
I
§
Figure 26 Example of Indexed (8 Bits Offset) Addressing
EA
,
Memorv
I
§
I
PROG LOA TABl.X 0692
A
DB
Index Reg
I
02
~6
0693
07
0694
7E
Stack Point
1-------'
Prog Count
0695
I
TABL FCB # BF 077E
FCB # 86 077F
FCB # DB 0780
FCB # CF 0781
CC
,
BF
86
I-__O::B~_--J-----------------'
CF
Figure 27 Example of Indexed (16 Bits Offset) Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
705
HD63L05F1---------------------------------------------------------
Memory
PORT B EOU 1 0001
BF
A
0000
Index Reg
PROG BCLR 6. PORT B 058F
10
0590
01
Stack Point
Prog Count
0591
I
I
CC
~
I
I
I
I
Figure 28 Example of Bit Set/Clear Addressing
A
PORT C EOU 2 0002
Index Reg
Stack Point
PROG BRCLR 2. PORT C. PROG 2 0574
0575
05
t------~
02
0576
10
Prog Count
0594
CC
C
I
I
~
I
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
Figure 29 Example of Bit Test and Branch Addressing
706
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
I
---------------------------------------------------------------HD63L05Fl
,
Memory
I
I
I
I
~
PROG TAX 058A
8
I
I
I
I
I
I
A
E5
Index Reg
E5
Prog Count
0588
CC
I
I
~
Figure 30 Example of Implied Addressing
•
INSTRUCTION SET
•
There arc 59 instructions available to the MCU. They can
be divided into five groups: Register/Memory, Read/Modify/
Write, Branch, Bit Processing, and Control. All of these instructions arc explained below according to the groups, and are
summarized in individual tables.
•
Register/Memory
Branch
A Branch instruction will branch from the program sequence
in progress if the specific branch condition is satisfied. See
Table 6.
•
Bit Processing
This instruction can be used for any bit of the first 256
bytes of memory. One group is used for setting or clearing,
while the other is used for bit testing and branching. See Table 7.
Most of these instructions use two operands. One operand
is either the accumulator or index register, while the other is
acquired from memory using one of the addressing modes.
No operand of register is available in the unconditional Jump
(JMP) and Subroutine Jump (JSR) instructions. See Table 4.
• Control
•
• A List of Instructions Arranged in Alphabetical Order
Read/ModifylWrite
These instructions read a memory address or register, modify
or test its contents, and writes a new value into the memory or
register. Negative or Zero instructions (TST) do not provide
writing, and are exceptions for the Read/Modify/Write. See
Table 5.
$
The Control instruction controls the operation of the MCU
for which a program is being executed. See Table 8.
All instructions are listed in Table 9 in the alphabetical
order.
• OP Code Map
Table 10 shows an OP code map of the instructions used
with the MeV.
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
707
HD63L05F1------------------------------------------------------------Table 4
Register/Memory Instructions
Addressing Mode
Immediate
Operation
Mnemonic
Op
Code
Direct
#
Op
#
Bytes Cycles Code
Indexed
(No Offset)
Extended
#
#
Op
Bytes Cycles Code
#
#
Op
Bytes Cycles Code
Indexed
(8-8itOffset)
Op
#
#
Bytes Cycles Code
Indexed
(16-BitOffset)
Op
#
#
Bytes Cycles Code
#
#
Bytes Cycles
Load A from Memory
LOA
A6
2
2
B6
2
3
C6
3
4
F6
1
2
E6
2
4
06
3
Load X from Memory
LOX
AE
2
2
BE
2
3
CE
3
4
FE
1
2
EE
2
4
DE
3
5
Store A in Memory
STA
-
2
4
C7
3
5
F7
1
3
E7
2
5
07
3
6
STX
-
B7
Store X in Memory
-
BF
2
4
CF
3
5
FF
1
3
EF
2
5
OF
3
6
Add Memory to A
ADD
AB
2
2
BB
2
3
CB
3
4
FB
1
2
EB
2
4
DB
3
5
5
Add Memory and
Carry to A
AOC
A9
2
2
B9
2
3
C9
3
4
F9
1
2
E9
2
4
09
3
5
Subtract Memory
SUB
AO
2
2
BO
2
3
CO
3
4
FO
1
2
EO
2
4
DO
3
5
Subtract Memory from
A with Borrow
SBC
A2
2
2
B2
2
3
C2
3
4
F2
1
2
E2
2
4
02
3
5
AND Memory to A
AND
A4
2
2
B4
2
3
C4
3
4
F4
1
2
E4
2
4
04
3
5
OR Memory with A
ORA
AA
2
2
BA
2
3
CA
3
4
FA
1
2
EA
2
4
OA
3
5
Exclusive OR Memory
with A
EOR
A8
2
2
B8
2
3
C8
3
4
F8
1
2
E8
2
4
08
3
5
Arithmetic Compare A
with Memory
CMP
Al
2
2
Bl
2
3
Cl
3
4
Fl
1
2
El
2
4
01
3
5
Arithmetic Compare X
with Memory
CPX
A3
2
2
B3
2
3
C3
3
4
F3
1
2
E3
2
4
03
3
5
Bit Test Memory with
A (Logical Compare)
BIT
A5
2
2
B5
2
3
C5
3
4
F5
1
2
E5
2
4
05
3
5
Jump Unconditional
JMP
-
-
BC
2
2
CC
3
3
FC
1
1
EC
2
3
DC
3
4
Jump to Subroutine
JSR
-
-
-
BO
2
4
CD
3
5
FD
1
3
ED
2
4
DO
3
5
Symbols: op· Operation
# .. Instruction
Table 5 Read/Modify/Write Instructions
Addressing Mode
Implied (A)
Implied (X)
Indexed
(No Offset)
Direct
Indexed
(8-Bit Offset)
Mnemonic
Op
Code
#
#
#
#
#
#
Bytes
Cycles
Bytes
Cycles
Op
Code
#
Cycles
Op
Code
#
Bytes
Op
Code
#
Cycles
Op
Code
#
Bytes
Bytes
Cycles
INC
4C
1
1
5C
1
1
3C
2
4
7C
1
3
6C
2
5
Decrement
DEC
4A
1
1
5A
1
1
3A
2
4
7A
1
3
6A
2
5
Clear
CLR
4F
1
1
5F
1
1
3F
2
4
7F
1
3
6F
2
5
Operation
Increment
Complement
COM
43
1
1
53
1
1
33
2
4
73
1
3
63
2
5
Negate
(2's Complement)
NEG
40
1
1
50
1
1
30
2
4
70
1
3
60
2
5
Rotate Left Thru Carry
ROL
49
1
1
59
1
1
39
2
4
79
1
3
69
2
5
Rotate Right Thru Carry
ROR
46
1
1
56
1
1
36
2
4
76
1
3
66
2
5
Logical Shift Left
LSL
48
1
1
58
1
1
38
2
4
78
1
3
68
2
5
Logical Shift Right
LSR
44
1
1
54
1
1
34
2
4
74
1
3
64
2
5
Arithmetic Shift Right
ASR
47
1
1
57
1
1
37
2
4
77
1
3
67
2
5
----_.-.-
Arithmetic Shift Left
ASL
48
1
1
58
1
1
38
2
4
78
1
3
68
2
5
Test for Negative or
Zero
TST
40
1
1
50
1
1
3D
2
4
70
1
3
60
2
5
Symbols:
708
Qp"
Operation
#
= Instruction
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------------HD63L05F1
Table 6 Branch Instructions
Relative Addressing Mode
Operation
Op
Code
Mnemonic
Branch Always
BRA
20
Branch Never
BRN
21
Branch IF Higher
BHI
22
Branch I F Lower or Same
BLS
23
BCC
24
(BHS)
24
#
#
Bytes
Cycles
Branch IF Minus
BMI
2B
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Branch IF Interrupt Mask Bit is Clear
BMC
2C
2
Branch IF Interrupt Mask Bit is Set
BMS
20
2
2 or 3 *
Branch IF Interrupt Line is Low
BIL
2E
2
2 or 3 *
Branch IF Interrupt Line is High
BIH
2F
2
2 or 3 *
Branch to Subroutine
BSR
AD
2
Branch I F Carry Clear
(Branch IF Higher or Same)
Branch IF Carry Set
BCS
25
(BLO)
25
Branch I F Not Equal
BNE
26
Branch IF Equal
BEQ
27
Branch IF Half Carry Clear
BHCC
28
Branch IF Half Carry Set
BHCS
29
Branch IF Plus
BPL
2A
(Branch IF Lower)
3
2 or 3 *
2 or 3 *
2 or 3 *
2 or 3 *
2 or 3 *
2 or 3 *
2 or 3 *
2 or 3 *
2 or 3 *
2 or 3 *
2 or 3 *
2 or 3 *
2 or 3 *
2 or 3 *
4
Symbol: Op = Operation
# = Instruction
* If branched, each instruction will be a 3-cycle instruction.
Table 7 Bit Processing InstA1ctior.s
Addressing Mode
Bit Set/Clear
Bit Test and Branch
Mnemonic
Op
Code
#
#
Bytes
Cycles
Branch IF Bit n is Set
BRSET n (n = 0 ..... 7)
-
-
-
2· n
Branch IF Bit n is Clear
BRCLR n (n = 0 ..... 7)
-
-
01 + 2· n
3
3
Set Bit n
BSET n In = 0 ..... 7)
2
4
-
-
-
Clear Bit n
BCLRn(n=D ..... 7)
10 + 2, n
11 + 2, n
2
4
-
-
-
Operations
Op
Code
#
#
Bytes
Cycles
4 or 5 *
4 or 5 *
Symbol: Op = Operation
# = Instruction
• If Branched, each instruction will be a 5-cycle instruction.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
709
HD63L05F1------------------------------------------------------------Table 8 Control Instructions
Implied
#
#
Mnemonic
Op
Code
Transfer A to X
TAX
97
1
1
Transfer X to A
TXA
9F
1
1
Set Carry Bit
SEC
99
1
1
Clear Carry Bit
ClC
98
1
1
Operation
Bytes Cycles
Set Interrupt Mask Bit
SEI
9B
1
1
Clear I nterrupt Mask Bit
CLI
9A
1
1
Software Interrupt
SWI
83
1
9
Return from Subroutine
RTS
81
1
4
Return from Interrupt
RT!
80
1
7
Reset Stack Pointer
RSP
9C
1
1
No-Operation
NOP
90
1
1
Symbol: Op = Operation
# = Instruction
Table 9 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
Direct
Extended
Relative
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
Setl
Clear
Bit
Test &
Branch
H
I
N
Z
C
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1\
1\
1\
1\
1\
1\
1\
•
1\
/\
1\
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ADC
x
x
x
ADD
x
x
x
x
x
x
1\
AND
x
x
x
x
x
x
•
ASl
x
x
x
x
ASR
x
x
x
x
x
BCC
x
BClR
BCS
x
BEQ
x
BHCC
x
BHCS
x
BHI
x
BHS
x
BIH
x
Bil
x
BIT
x
x
x
x
BlO
x
BlS
x
BMC
x
BMI
x
BMS
x
BNE
x
BPl
x
BRA
x
Symbols for condition code:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
710
Bit
x
x
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1\
1\
1\
• •
• •
• •
• •
•
•
•
•
•
•
•
•
1\
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(Continued)
C
1\
Carry/Borrow
Test and Set if True. Cleared Otherwise
Not Affected
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------------HD63L05F1
Table 9
Instruction Set (Continued)
Addressing Modes
Mnemonic
Implied
Immediate
Direct
Extended
Relative
Condition Code
Indexed
Indexed Indexed
(No
(B Bits) (16 Bits)
Offset)
Bit
Setl
Clear
Bit
Test &
Branch
x
BRN
BRCLR
x
BRSET
x
x
BSET
BSR
x
CLC
x
CLI
x
CLR
x
COM
x
LSR
x
x
x
NEG
NOP
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
ROR
x
x
x
RSP
x
RTI
x
RTS
x
x
SBC
SI;:C
x
SEI
x
STA
STX
x
SUB
SWI
x
TAX
x
TST
x
TXA
x
Symbols for condition code:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
x
x
ROL
ORA
x
x
x
JSR
LOX
x
x
x
x
x
LSL
x
x
JMP
LOA
x
x
x
x
x
INC
x
x
x
x
EOR
x
x
x
CPX
DEC
x
x
CMP
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
C
1\
•
}
x
x
x
x
x
H
I
N
Z
C
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
A
A
•
•
0
•
•
0
1
A
A
A
1\
1
A
1\
A
•
•
1\
A
A
1\
A
A
A
•
• • •
• • •
A 1\ •
A 1\ •
A
1\
A
0
A
A
A
A
A
• • •
A
A
•
A
A
1\
• • 1\ 1\ 1\
• • • • •
x
x
x
x
x
?
?
?
?
•
•
•
•
•
•
•
•
•
•
•
• • •
• 1\ 1\
• • •
1 • •
• 1\ 1\
• 1\ 1\
• 1\ 1\
1 • •
• • •
• 1\ 1\
• • •
•
?
1\
1
•
•
•
1\
•
•
•
•
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
711
HD63L05F1------------------------------------------------------------Table 10 OP Code Map
Bit Manipulation
Branch
Register /Memory
Control
Read/Modify /Write
I OIR I EXT I ,X2 I Xl I ,XO
I B I C I 0 I E J F ... HIGH
Test &
Branch
Set/
Clear
Rei
OIR
0
1
2
3
0
BRSETO
BSETO
BRA
NEG
RTI*
-
1
BRClRO
BClRO
BRN
RTS*
-
CMP
1
2
BRSETl
BSETl
BHI
-
-
SBC
2
SWI*
I
I
A
4
I
I
X
5
3
BRClRl
BClRl
BlS
COM
4
BRSET2
BSET2
BCC
lSR
I
I
,Xl
6
I
I
,XO
7
IMP
8
-
5
BRClR2
BClR2
BCS
-
6
BRSET3
BSET3
BNE
ROR
7
BRClR3
BClR3
BEQ
ASR
-
8
IMP
IMM
9
A
SUB
0
-
CPX
3
l
-
AND
4
o
-
BIT
5 W
TAX
-
I
lOA
6
STA (+1)
7
BRSET4
BSET4
BHCC
lSl/ASl
-
ClC
EOR
9 BRClR4
A BRSET5
BClR4
BHCS
ROl
-
SEC
AOC
8
9
BSET5
BPl
DEC
-
CLI
ORA
A
B BRClR5
BClR5
BMI
-
SEI
ADD
B
C BRSET6
BSET6
BMC
INC
JMP(-l)
C
BRClR6
BClR6
BMS
TST
-
E BRSET7
BSET7
Bil
-
-
-
F BRClR7
BClR7
BIH
ClR
-
TXA
0
3/4 or 5
(NOTES)
712
2/4
2/20r3
2/4
I
1/1
I
1/1
I 2/5 I 1/3
1/-
RSP
NOP
1/1
-
1
BSR*1
JSR(+l)
T
JSR
IJSR(+l
-
I
2/21
STX(+l)
2/3
I
3/4
r 3/5 I
0
E
lOX
F
2/4
I
1/2
1. "-" is an undefined operation code.
2. The figure in the lowest row of each column gives the number of bytes and the cycles needed for the instruction.
The number of cycles for the asterisked (*) mnemonics is a follows:
RTI
7
RTS
4
SWI
9
BSR
4
3. The parenthesized figure must be added to the cycle count of the associated instruction.
4. If the instruction is branched, the cycle count is the larger figure.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------------HD63L05F1
DATE OF ORDER
CUSTOMER
DEPT.
ACCEPTED BY
ROM CODE ID.
LSI TYPE NO.
HD63L05F
MASK OPTION LIST
* Select one type for each item and check •.
HD63L05F
(1) OSC OPTION
Type
of
OSCl
Use
of
OSC2
0
STANDBY
mode
Used
XTAL
Option
Not used
Used
CR
Option
Delay Time of
Restart (sec.)
1/16
1/2
Condition
Not Used
STANDBY
mode
Oscillation
of OSCl
at HALT
Oscillation
of OSCl
at HALT
Used
Not Used
Used
Not Used
Stop
Continue
Stop
Continue
***
***
***
***
* Specify a type of
OSC option.
1
* Crystal option of OSC,
is not allowed to stop
at HALT.
* If OSC2 is not used,
the Delay Time is not
acculate.
***
***
***
***
***
***
***
(2) I/O OPTION
Mask Option
Port
A
C
B
Pin
D
INT
Ao
Al
A2
A3
A4
As
A6
A7
Bo
Bl
82
83
84
85
86
87
Co
Cl
C2
C3
A
B
C
D
E
F
G
H
K
Mask Option
E 1 F
I
Pin
SEG13/CH6
SEG14/CHs
SEGlS/CH4
SEG16/CH3
SEG17/CH2
01s/CHs/V2
019/CH7/Vl
G
Mask option
K
H
***
*'**
***
***
***
CMOS output without input pull·up PMOS
CMOS output with input pull·up PMOS
CMOS output for key scanning
NMOS open-drain output
Input without pull·up PMOS
Input with pull·up PMOS
A/D Input
Segment output
Terminals for LCD display
* Specify an I/O option for each terminal.
(3) LCD DRIVER
L
Segment
Mask Option
I S I P
I
I
Mask options indicated as *** are not available.
L
S
P
, /3 bias·' /3 duty LCD
Static LCD
Output port
, * Specify a type of LCD driver.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
713
HD63L05F1------------------------------------------------------------(4)
LCD PIN LOCATION
LCD
Regilt.
?
'Segment Output Terminal
Timing
t COM, COM, COM, SEG, SEG, SEG, SEG. SEG. SEG, SEG, SEG, SEG, SEG" SEG" SEG" SEG" SEG .. SEG" SEG,. SEG"
Outpu~
011
0 ..
,
LCO' 0
2
3
4
5
6
7
,
LC02 0
--
2
3
4
5
6
7
,
LC03 0
2
3
4
5
6
LC04 0
,
2
3
4
5
6
LC05 0
,
2
3
4
5
6
LC060
1
2
3
4
5
6
LC07 0
1
2
3
4
5
6
LC08 0
1
2
3
I/JWRITE
114
•
•
•
•
•
714
ascI
0
0
Specify the multiplex timing and segment terminal for each bit of LCD1 to LCOS.
When static or output port is selected, the Multiplex timing is fixed at COM,.
If there are unspecified bits, Hitachi specifies them as dummy.
4>WRITE is generated when data is written into the LC01.
1/4 OSC1 is a quarter of the OSC1 clock speed. When the MCU is in standby mode, it becomes "Low".
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD63L05EO,-------------Evaluation Chip for HD63L05F 1
HD63LOSE is a CMOS evaluation chip for the HD63LOSF.
Connecting an external EPROM (HN462732) to the chip, it
can be operated as a single chip microcomputer HD63LOSF.
Interface signals are 12 bit Address Bus (Eo"'" E 7 , Fo ,.." F 3),8
bit Data Bus (Do ,.." 0 7 ) and Chip Enable (C'E).
It is easy to debug the HD63LOSF user program with this
evaluation chip.
•
•
•
•
•
•
•
•
•
•
•
FEATURES
3V Power Supply
96 Bytes RAM
EPROM (HN462732) Interface
LCD Driver
a-bit Programmable Timer with 7-bit Prescaler
a-bit A/D Converter
20 parallel I/O Port
Same Instruction Set as HD63L05F
NMOS Open-drain Output
100 Pin Flat Package (FP-l00)
•
TERMINALS
Ao ,.." A7
I/O Port
Bo ,.." B7
I/O Port
Co ,.." C3
I/O Port
Do ,.." D7
Data Bus (Input)
Eo ,.." E7
Lower a bit Address Bus (Output)
Fo ,.." F3
Upper 4 bit Address Bus (Output)
U/M
Test Terminal
CE/WR
Chip Enable, Read/Write
Instruction Fetch Signal
ADCLK
E Clock
HA[T
External clock control signal
M'SET
Connected to V cc
HD63L05EO
(FP-100)
•
PIN ARRANGEMENT
m
HD63L05EO
51
Co
NC: No Connection
(Top View)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
715
HD63L05EO------------------~--
_______________________________________
• BLOCK DIAGRAM
COMMON
DRIVER
OUTPUT
HALTJ
LIR------.
~DCLK~
CEo WR
DATA
LATCH
LCD1
8
LCD2
8
SEG.
SEG,
SEG 3
SEG 4
MSET
SEG s
SEG 6
XOUT
I
SEG 7
SEG s
SEG.
SEG,o
U/M
TIMER
INT
(SEG I1
)
(SEG 12 )
ACCUMULATOR
A
8
INDEX REGISTER
8
IX
CPU
CONTROL
8
SYS CTRL
STACK POINTER
SP
PROGRAM
COUNTER
HIGH PCH
4
PROGRAM
COUNTER
LOW PCL
)
)
)
(SEG'6)
L...._ _ _.L--'-_ _ (SEG )
17
r:::-r""1.___ CHI
~
<
0
CONDITION CODE
REG.
CCR
5
(SEG 13
(SEG. 4
(SEG IS
k----(CH.)
k----(CH3)
....---(CH4)
k----(CHs)
5
....---(CH6)
ALU
k----(CH7)
L_...L~---(CH' )
....---Bo
14----B•
....---B.
a-.---B 3
a-.---B4
....---Bs
....- - - B 6
'-----B7
L--L-r--oI
c3c3uu
716
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD68P01 V07 ,HD68P01 V07-1HD68P01 MO ,HD68P01 MO-1
MCU (Microcomputer
The HD68POI is an 8-bit single chip microcomputer unit
(MCU) which significantly enhances the capabilities of the
HMCS6800 family of parts. It can be used in production systems to allow for easy firmware changes with minimum delay or
it can be used to emulate the HD6801 for software development.
If includes 128 bytes of RAM, Serial Communications Interface
(SCI), parallel I/O and a three function Programmable Timer on
chip, and 2048 bytes, 4096 bytes or 8192 bytes of EPROM on
package. It includes an upgrade HD6800 microprocessing unit
(MPU) while retaining upward source and object code compatibility_ Execution times of key instructions have been improved and several new instructions have been added including
an unsigned 8 by 8 multiply with 16-bit result. The HD68POI
can function as a monolithic microcomputer or can be expanded to a 65k byte address space. It is TTL compatible and
requires one +5 volt power supply. A summary of HD68POI
features includes:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
FEATURES
Expanded HMCS6800 I nstruction Set
8 x 8 Multiply Instruction
Serial Communications Interface (SCI)
Upward Source and Object Code Compatible with HD6800
16-bit Three-function Programmable Timer
Applicable to All Type of EPROM
4096 bytes; HN482732A
8192 bytes; HN482764
128 Bytes of RAM (64 bytes Retainable on Powerdown)
29 Parallel 1/0 and Two Handshake Control Line
Internal Clock Generator with Divide-by-Four Output
Full TTL Compatibility
Full Interrupt Capability
Single-Chip or Expandable to 65k Bytes Address Space
Bus compatible with HMCS6800 Family
•
TYPE OF PRODUCTS
Type No.
Bus Timing
HD68P01V07. HD68P01V07-1.HD68P01MO. HD68P01 MO-1
•
EPROM Type No.
PIN ARRANGEMENT (Top View)
HD68P01V07. HD68P01V07-1
HD68P01MO, HD68P01MO-1
H N482732A-30
HD68P01V07
1 MHz
HD68P01V07-1
1.25MHz
HN482732A-30
HD68P01MO
1 MHz
1.25MHz
HN482764-3
H D68POl MO-1
Unit)
HN482764-3
Note) EPROM is not attached to the MCU.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
717
HD68P01V07,HD68P01V07-1,HD68P01 MO,HD68P01 M-1
•
BLOCK DIAGRAM
.....--"~+-+
P20
k-+-..,--~>-+.. P21
Ie++-.-~ P22
14+--+-+--t-+ P23
14+-+-t--i-.+ P24
Address
Output
EPROM
(HN482732AI
lHN482764 )
00
01
02
0,
04
Data
Input
O~
O~
I
07 I
I
L __________
718
-.J
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-l
•
ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
Symbol
Vee *
-0.3 - +7.0
V
V in *
-0.3 -+7.0
V
Input Voltage
Operating Temperature
Top.
Storage Temperature
Tst9
Value
Unit
-+70
°c
-55 -+150
°c
0
" With respect to VSS (SYSTEM GND)
[NOTE] Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded. it could affect reliability of LSI.
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee =5.0V±5%, Vss = OV, Ta = 0 - +70°C; unless otherwise noted.)
Item
Input "High" Voltage
Symbol
RES
All Inputs*
Input Load Current
P40 - P4 ?
SCI
EXTAL
Ilinl
Input Leakage Current
NMI, IRQ~, RES
P IO
-
PI?, P 30
P 20
-
P 24
P 30
P40
-
P 3?
P4 ?, E, SCI, SC 2
,-
Ilinl
P 37
All Outputs
Darlington Drive Current P IO
Power Dissipation
Input Capacitance
Vee Standby
Standby Current
P 30
-
Vee
2.0
-0.3
-
Vee
0.8
-
-
0.5
-
-
0.8
1.2
mA
Vin = 0- Vee
--
Vin = 0 - 5.25V
-
-
2.5
JJ.A
-
-
10
100
JJ.A
IITSII
V OH
I LOAD = -205 JJ.A
I LOAD = -145JJ.A
2.4
2.4
I LOAD = -100 JJ.A
2.4
I LOAD = 1.6 mA
Vout = 1.5V
-
VOL
-IOH
PI?
Vin = 0 - 2.4V
Vin = 0.5 - 2.4V
Other Outputs
Output "Low" Volta.ge
max
-
VIL
Three State (Offset)
Leakage Current
Output "High".Voltage
typ
V1H
Other Inputs*
Input "Low" Voltage
min
4.0
Test Condition
Po
-
P 37 , P40
-
P4 ?, SCI
Cin
Vin = OV, Ta = 25°C,
f = 1.0 MHz
-
-
-
-
1.0
-
-
V
V
10.0
mA
-
1200
mW
-
-
12.5
-
12.5
5.25
8.0
Powerdown
VSBB
4.0
Operating
VSB
4.75
Powerdown
ISBB
-
-
VSBB = 4.0V
V
V
0.5
-
Other Inputs
Unit
5.25
pF
V
mA
"Except Mode Programming Levels: See Figure 8.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
719
HD68P01 V07,HD68P01 V07-1 ,HD68P01 MO,HD68P01 M-1
• AC CHARACTERISTICS
BUS TIMING (Vee = 5.0V±5%, Vss
= OV, Ta = 0 -
+70°C, unless otherwise noted.)
Symbol
Item
Test Condition
H D6SPOl V07/MO
min
min
typ
max
10
O.S
-
10
-
150
-
-
ns
5
-
50
ns
50
ns
-
ns
50
ns
Data Set·up Write Time
tDsw
225
Data Set·up Read Time
toSR
SO
Read
tHR
10
Write
tHW
20
-
Address Set-up Time for Latch *
tASL
60
Address Hold Time for Latch
tAHL
20
-
Address Hold Time
tAH
20
-
-
-
Cycle Time
Address Strobe Pulse width "High'"
PWASH
Address Strobe Rise Time
tASr
1
200
5
Address Strobe Fall Time
tASt
5
Address Strobe Delay Time *
tASD
60
Enable RiseTime
Enable Fall Time
t Er
tEt
Enable Pulse Width "High" Time *
PWEH
450
Enable Pulse Width "Low" Time *
PWEL
450
Address Strobe to Enable Delay Time *
tASED
60
Address Delay Time
tAD
Fig. 1
tADL
Fig. 2
Address Delay Time for Latch (f
Data Hold Time
Peripheral Read
Access Time
I
I
= 1.0MHz) *
I Non-Multiplexed Bus *
I
Multiplexed Bus"
Oscillator stabilization Time
Processor Control Set-up Time
PERIPHERAL PORT TIMING (Vee
5
5
hACCN)
(tACCM)
tRC
Fig. 11
100
tpcs
Fig. 12
200
= 5.0V ±5%, Vss =OV, Ta = 0 -
Item
-
50
50
5
50
5
50
5
-
50
ns
-
340
-
ns
350
260
70
-
-
10
-
-
20
-
-
50
-
-
ns
20
-
ns
270
30
30
-
115
(610)
-
20
(600)
-
-
100
200
ns
ns
-
ns
-
ns
(420)
(420)
-
Symbol
Test Condition
min
typ
max
Unit
tposu
Fig. 3
200
-
ns
Peripheral Data Hold Time
Port 1, 2, 3,4
tpOH
Fig. 3
200
-
-
Delay Time, Enable Positive Transition
to OS3 Negative Transition
tOS01
Fig. 5
-
-
350
ns
Delay Ti",!e, Enable Positive Transition
to OS3 Positive Transition
tOSD2
Fig. 5
-
-
350
ns
Delay Time, Enable Negative
Transition to Peripheral Data
Valid
Port 1, 2*,3,4
tpWD
Fig_ 4
-
-
400
ns
Delay Time, Enable Negative
Transition to Peripheral
CMOS Data Valid
*
Port 2**, 4
t CMOS
Fig.4
-
-
2.0
JlS
-
-
ns
-
ns
tPWIS
Fig.6
200
tlH
Fig.6
50
Input Data Set-up Time
Port 3
tiS
Fig.6
20
"Except P"
720
ns
260
Port 1, 2, 3,4
port 3
ns
260
+70°C, unless otherwise noted.)
Input Data Hold Time
Jls
-
-
Peripheral Data Setup Time
Input Strobe Pulse Width
Unit
max
-
tcyc
HD6SP01V07·1/MO·l
typ
ns
ns
""10kfl pull up register required for Port 2
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
os
ns
ns
ms
ns
---------------HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-1
TIMER, SCI TIMING (Vee
= 5.0V ±5%
Vss
=OV
=0 -
Ta
+70°C unless otherwise noted.)
Symbol
Item
Timer Input Pulse Width
tpwT
Delay Time, Enable Positive Transition to
Timer Out
tTOD
typ
max
-
-
ns
-
600
ns
-
Fig. 7
SCI Input Clock Cycle
tSCYC
SCI Input Clock Pulse Width
tpwSCK
= 5.0V ±5%, Vss = OV. Ta = 0 -
MODE PROGRAMMING (Vee
min
2 tcyc+2OO
Test Condition
Unit
1
-
-
tCyc
0.4
-
0.6
tScyC
+70°C, unless otherwise noted.)
min
typ
max
Unit
Mode Programming Input "Low" Voltage
V MPL
-
-
1.7
V
Mode Programming Input "High" Voltage
V MPH
4.0
-
-
V
3.0
-
-
tcyc
2.0
-
-
tcyc
0
-
100
-
-
ns
Symbol
Item
PW RSTL
RES "Low" Pulse Width
Mode Programming Set-up Time
I
Mode Programming
Hold Time
RES Rise Time ~ 11lS
tMPH
RES Rise Time < l~s
I
teye
.J~
2,2V..,
V
- --
I--PWASH-
Q,6V..,,...
-tASt
-tASr
tASD
Enable
(EI
\.
~~
-- -
J
2, 4V~
Fig.8
tMPs
I
Address Strobe
(AS)
Test Condition
ASEO
-'t-
V'
PW EL
Q,5V -'~
~(
PWEH
J
-4
-tAD-
R/W ,Ar-Au
(SCi
Address Val,d
"'
D.-D"A.-A,
(Port 3)
I--
1-
I-tMiL
) ~;~ess .l~
) QValId
k(
6V
tos w ----..
)":22V
)
~
ValId
Q 6V
r\
"
Data Vaild
-'
1-
-tHA
.. ~
jit- 2 ,QV
.,11
-tf4N
~'f-
Q 6V
-tCSA-
!;d.ess -l
-
Data ValId
~
-tADLMCU Read
0.-0,. A.-A,
(Port 3)
-tAH
V.
Q 6V
tASL-
MCUWrote
-tEt
-l
)~2 2V
(Port4)
1\
-
-tEr
Q,SV
.,11
(tACCM)
Figure 1 Expanded Multiplexed Bus Timing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
721
HD68P01V07,HD68P01 V07-1 ,HD68P01 MO,HD68P01 M-1
.
--,
~
2.4V"""a-Enable
(E)
O.SV
.
tcyc
,-f'\
PWEL
-:-~
PWEH
~(
-"~
J
--+
-tEr
Acr-AlIPort4 )
Rm (SC2)
iDS (SCI)
I--tEf
--+
~tAO-
1-
22V)~
-tAH
-'1\
Address Valod
"1~
O.6V\-tOSIIII-
-tHIll/
--+
MCU Write
22V}~
0.-0,
(Port3)
06V\'"
-'~
Data Valid
.
-,'f-
I-tOSR-
(tACCN)
MCU Read
0.-0,
(Port 3)
--+
Data Valod
------------------------------------~I
O.8V 1 ' - - - - - - - - " 1
Figure 2
Expanded Non-Multiplexed Bus Timing
r-
r-MCURead
MCUWrite
CMOS
t
-}
_tPIII/O_
P,. - P"
,
P 2. - PH
p •• - P.,
Inputs
p,. -
-tHR
2.0V
All Data
Port Outputs
_ _ _ _ _ _ _ _ _ _ _ _ _ _- J
... ---O. 7V CC
2.2V
O.SV Data Valid.
P"
Inputs"
(NOTE)
·Port 3 Non-Latched Operation (LATCH ENABLE: 0)
Figure 3
1. 10 kn Pullup resistor required for Port 2 to reach 0.7 VCC
2. Not applicable to P"
3. Port 4 cannot be pulled above Vec
Data Set-up and Hold Times
Figure 4
Port Data Delay Timing
(MCU Write)
(MCU Read)
Address
BUI
053 - - - - - - - - - -
• Access matches Output Strobe Select (055 : 0, a read;
055· I, a write)
Figure 5
722
Figure 6
Port 3 Output Strobe Timing
(Single Chip Mode)
Port 3 Latch Timing
(Single Chip Mode)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-1
RES
Timer
Counter
(p~~d;2:~P~2t:) ------.;..~rl
I'-----.....JI'!'
P"
Output
Figure 7 Timer Output Timing
Test POInt
Figure 8
Mode Programming Timing
o~----l" 30pF
C = 90 pF for p,.-p" ,p.o-p", E,SC" SC,
=30pFforP,o-P",p,.-p,.
R= 12knforP •• -P".P .. -P".E,SC"SC,
= 24 kn for p,. -P", P,n -p,.
(a) CMOS Load
(b) TTL Load
Figure 9
•
Bus Timing Test Loads
INTRODUCTION
The HD68POI is an 8-bit monolithic microcomputer which
can be configured to function in a wide variety of applications, The facility which provides this extraordinary flexibility
is its ability to be hardware programmed into eight different
operating modes. The operating mode controls the configuration of' 18 of the MCU's 40 pins, available on-chip resources,
memory map, location (internal or external) of interrupt
vectors, and type of external bus_ The configuration of the remaining 22 pins is not dependent on the operating mode.
Twenty-nine pins are organized as three 8-bit ports and one
5-bit port. Each port consists of at least a Data Register and a
write-only Data Direction Register. The Data Direction Register
is used to define whether corresponding bits in the Data Register are configured as an input (clear) or output (set).
The term "port", by itself, refers to all of its associated hardware, When the port is used as a "data port" or "I/O port", it is
controlled by its Data Direction Register and the programmer
has direct access to its pins using the port's Data Register. Port
pins are labled as Pij where i identifies one of four ports and j
indicates the particular bit.
The Microprocessor Unit (MPU) is an enhanced HD6800
MPU with additional capabilities and greater throughput. It is
upward source and object code compatible with the HD6800,
The programming model is depicted in Figure 10 where Accumulator D is a concatenation of Accumulators A and B, A
list of new operations added to the HMCS6800 instruction set
are shown in Table 8.
The basic difference between the HD6801 and the HD68POI
is that the HD6801 has an on-chip ROM while the HD68POI has
an on the package EPROM. The HD68PO 1 is pin and code com·
patible with the HD6801 and can be used to emulate the
HD6801, allowing easy software development using the onpackage EPROM. Software developed using the HD68POI can
then be masked into the HD6801 ROM.
~,75- ~
iJD ~ -
- - A____0
- -
~-
-
8-Bit Accumulators
- :0 A and B
~ Or '6-Bit Double
Accumulator D
1'..._5_______X_ _ _ _ _ _--'01
Index Register (X)
L..1'_5_______S_P_ _ _ _ _ _. . .I01
Stack Pointer (SP)
1'.._5_______P_C_ _ _ _ _ _......
ol
Program Counter (PC)
Condition Code
Register (CCR)
Carry/Borrow from MSB
Overflow
Zero
Negative
Interrupt
Half Carry (From Bit 3)
Figure 10
HD68POl Programming Model
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
723
HD68P01 V07,HD68P01 V07-1 ,HD68P01 MO,HD68P01 M-1
•
INTERRUPTS
The MCV supports two types of interrupt requests: maskable
and non-maskable. A Non-Maskable Interrupt (NMI) is always
recosnized and acted upon at the completion of the current
instruction. Maskable interrupts are controlled by the Condition
Code Register's I-bit and by individual enable bits. The I-bit
controls all maskable interrupts. Of the maskable interrupts,
there are two types: IRQ) and IRQ2 . The Programmable Timer
and Serial Communications Interface use an internal IRQ2 interrupt line, as shown in BLOCK DIAGRAM. External devices
(and IS3) use IRQ) . An IRQ) interrupt is serviced before IRQ2
if both are pending.
All IlUh interrupts use hardware prioritized vectors. The
single SCI interrupt and three timer interrupts are serviced in a
prioritized order where each is vectored to a separate location.
All MCV interrupt vector locations are shown in Table I.
The Interrupt flowchart is depicted in Figure 13 and is com·
mon to every MCU interrupt excluding Reset. The Program
Counter, Index Register, A Accumulator, B Accumulator, and
Condition Code Register are pushed to the stack. The I-bit is
L." Inst,uctlon
_I
set to inhibit maskable interrupts and a vector is fetched corresponding to the current highest priority interrupt. The vector
is transferred to the Program Counter and instruction execution
is resumed. Interrupt and RES timing is illustrated in Figure 11
and 12.
Table 1
.,
Interrupt Vector Locations
MSB
LSB
FFFE
FFFF
RES
FFFC
FFFO
NMI
FFFA
FFFB
Software Interrupt (SWI)
FFF8
FFF9
I RQ) (or IS3)
FFF6
FFF7
ICF (Input Capture)
FFF4
FFF5
OCF (Output Compare)
FFF2
FFF3
TOF (Timer Overflow)
FFFO
FFF1
SCI (RORF + ORFE + TORE)
Interrupt
Cvcle
.s
I
1
.g
.'0
1
I
."
I
I
m
Internal
Address Bus """,,_-+"-_-+,''-_-'
*-----
NMlo,~
\~
'~_"'''
_ _''-_---'''-_ _ _ _ _
'~_'''
'-_---"'-_ _ - . _ . " , _ _
,'-_....J"-_-"'~_
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
-II+-'pcs
Internal....,.,~-....,--~-_ _-~~-"'"---'\r-'-'\.--_r--"""---....,--'\r--....,---'\r-~.---""",..--
0.1a Bus -"--"'------'''O-P-C-od-.''-O-P-Cod-."-Pc-o-,P-C"7\..PC-S-'p-C....
, s""""X-o-,X-7"'-X-S---X'-5"-A-C-C-A-"-A-C-C-S"'---""""Ir-,.-'.Y-.n-'-"-V-.-c,-o'--"-V-.c-,o-,-"-F-,,-st-,n......" o - ' Data
MSB
LSB
Interrupt Rou .. ne
\~------------------------------~I
Internal RfW'
• IRQ,; Internal Interrupt
Figure 11
LS1J"1~J1S1..fLJ
1-.
-5.25V
475V
Va
Interrupt Sequence
n
I,
'Re
I
!t
~
- - - - · L -'pcs
H1 - - - - - - - - - - - - - - - - - s S ~ 4.0V
RES
I-,pcs
""\ 1...;O~,8_V_ _ _ _ __
A;,::,n:~, \\\\\\\\\\\\\\\\\\\\\~ M\\\\\\\\\\\\\\\\\\\\S\~
~ t::x:::x:::x::
~~
FFFEFFFE
In",nol Rfli
\\\\\\\\\\\\\\\\\\\~ ~\S\\\\\\\\\\\\\\\\\\\\\\\\Y
~~
~;,':';~: fu\\\\\\\\\\\\\\\\%1,\\\\\\\\\\\\\\\\\\\\\\\~ ~~
PCS-PC15 PCO-PC7 Forst
Instruction
~NOIV'lld
Figure 12
724
Reset Timing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
I
~
~
»
3
~
o·
Dl
C;
?-
•
tv
~
o
o
~
~~
~l:
CD
.~
:I:
C
ex>
• l>
C)
wO
~ l:
."
o
~
C-
o<
o
C/)
CD
,""-J
:I:
()
»
C
C)
<.0
01
ex>
."
~
o
~
o<
Condition Code Register
,
•
,
,-"
~
o
$
Vector
NMI
SWI
IRO
ICF
OCF
TOF
SCI
~
(,.)
01
CD
(,.)
o
o
--
PC
FFFC:FFFO
FFFA:FFFB
FFF8:FFF9
FFF6:FFF7
FFF4:FFF5
FFF2:FFF3
FFFO:FFFl
~
A
";-'
~
Non·Maskable Interrupt
Software Interrupt
Maskable Interrupt Request 1
Input Capture Interrupt
Output Compare Interrupt
Timer Overflow Interrupt
SCI Interrupt (TORE + RORF + ORFE)
:I:
C
C)
ex>
."
o
~
~
.0
:I:
C
C)
ex>
."
'..j
'"
1I1
Figure 13
Interrupt Flowchart
o
~
~
HD68P01 V07,HD68P01 V07-1 ,HD68P01 MO,HD68P01 M-1
•
FUNCTIONAL PIN DESCRIPTIONS
• Vee and Vss
Vee and V ss provide power to a large portion of the Meu.
The power supply should provide +5 volts (±5%) to Vee, and
VSS should be tied to ground. Total power dissipation (including Vee Standby), will not exceed PD milliwatts.
• Vee Standby
Vee Standby provides power to the standby portion (S80
through SBF) of the RAM and the STBY PWR and RAME bits
of the RAM Control Register. Voltage requirements depend on
whether the MCU is in a powerup or powerdown state. In the
powerup state, the power supply should provide +5 volts (±5%)
and must reach VSB volts before RES reaches 4.0 volts. During
powerdown, Vee Standby must remain above VSBB (min) to
sustain the standby RAM and STBY PWR bit. While in powerdown operation, the standby current will not exceed ISBB.
It is typical to power both Vee and Vee Stand by from the
same source during normal operation. A diode must be used
between them to prevent supplying power to Vee during
powerdown operation. Vee Standby should be tied to either
ground or Vee in Mode 3.
Figure 14
Battery Backup for Vee Standby
•
patible clock to the MCU's internal clock generator. Divide-byfour circuitry is included which allows use of the inexpensive
3.58 MHz Color Burst TV crystals. A 22 pF capacitor is required from each crystal pin to ground to ensure reliable startup and
operation. Alternatively, EXT AL may be driven with an external TTL compatible clock with a duty cycle of 45% - 55%
with XT AL connected to ground.
The internal oscillator is designed to interface with an AT-cut
quartz crystal resonator or a ceramic resonator operated in parallel resonance mode in the frequency range specified for 3.2 4 MHz. The crystal should be mounted as close as possible to
the input pins to minimize output distortion and startup stabilization time. The MCU is compatible with most commercially
available crystals and ceramic resonators and nominal crystal
parameters are shown in Figure 15.
•
RES
This input is used to reset the MCU's internal state and provide an orderly startup procedure. During powerup, RES must
be held below 0.8 volts: (J) at least tRe after Vee reaches 4.75
volts in order to provide sufficient time for the clock generator
to stabilize, and (2) until Vee Standby reaches 4.75 volts. RES
must be held low at least three E-cycles if asserted during powerup operation.
When a "High" level is detected, the MCU does the following:
I) All the higher order address lines will be forced "High".
2) I/O Port 2 bits, 2, I, and 0 are latched into programmed
control bits PC2, PCI and PCO.
3) The last two (SFFFE, SFFFF) locations in memory will
be used to load the program addressed by the program
counter.
4) The interrupt mask bit is set; must be cleared before the
CPU can recognize maskable interrupts.
RAM Control Register ($14)
The RAM Control Register includes two bits which can be
used to control RAM accesses and determine the adequacy of
the standby power source during powerdown operation. It is
intended that RAME be cleared and STBY PWR be set as part
of a powerdown procedure.
•
RAM Control Register
•
6
Bit 0- 5 Not Used
Bit 6 RAME
Bit 7 STBY PWR
•
5
4
3
2
x
x
x
x
o
x
x
RAM Enable. This Read/Write bit can be
used to remove the entire RAM from the
internal memory map. RAME is set (enabled) during Reset provided standby
~er is available on the positive edge of
RES. If RAME is clear, any access to a
RAM address is external. If RAME is set
and not in Mode 3. the RAM is included
in the internal map.
Standby Power. This bit is a Read/Write
status bit which is cleared whenever Vee
Standby decreases below VS BB (min). It
can be set ~ by software and is not
affected by RES.
XTAL and EXTAL
These two input pins interface either a crystal or TTL com-
726
E (Enable)
This is an output clock used primarily for bus synchronization. It is TTL compatible and is the slightly skewed divide-byfour result of the MCU input frequency. It will drive one
Schottky TTL load and 90 pF, and all data given in cycles is referenced to this clock unless otherwise noted.
NM" (Noll-Maskable Interrupt)
An NMI negative edge request an CPU interrupt sequence,
but the current instruction will be completed before it responds
to the request. The CPU will then begin an interrupt sequence.
Finally, a vector is fetched from SFFFC and SFFFD, transferred to the Program Counter and instruction execution resumes. NMI typically requires a 3.3 kD (nominal) resistor to
Vee. There is no internal NMI pullup resistor. NMI must be
held low for at least one E-cycle to be recognized under all
conditions.
•
I ROl (Maskable I nterrupt Request 1)
IRQ. is a level-sensitive input which can be used to request
an interrupt sequence. The CPU will complete the current instruction before it responds to the request. If the interrupt mask
bit (I-bit) in the Condition Code Register is clear, the CPU will
begin an interrupt sequence. Finally, a vector is fetched from
SFFF8 and SFFF9, transferred to the Program Counter, and
instruction execution is resumed.
IRQ. typically requires an external 3.3 kn (nominal) resistor to V cc for wire-OR application. IRQ. has no internal
pullup resistor.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-1
• SC, and SC2 (Strobe Control 1 and 2)
The function of SCI and SC 2 depends on the operating
mode. SCI is configured as an output in all modes except
single chip mode, whereas SC 2 is always an output. SC I and
SC 2 can drive one Schottky load and 90 pF.
SC, and SC2 in Single Chip Mode
In Single Chip Modes, SCI and SC 2 are configured as an input and output, respectively, and both function as Port 3 control lines. SC I functions as IS3 and can be used to indicate that
Port 3 input data is ready or output data has been accepted.
Three options associated with IS3 are controlled hy Port 3's
Control and Status Register and are discussed in Port 3's description. If unused, IS3 can remain unconnected.
SC 2 is configured as OS3 and can be used to strobe output
data or acknowledge input data. It is controlled by Output
Strobe Select (OSS) in Port 3's Control and Status Register. The
strobe is generated by a read (OSS= 0) or write (OSS = I) to
Port 3's Data Register. OS3 timing is shown in Figure 5.
SC, and SC2 in Expanded Non-Multiplexed Mode
In the Expanded Non-Multiplexed Mode, both SCI and SC 2
are configured as outputs. SC I functions as Input/Output Select
(lOS) and is asserted only when $0100 through $OIFF is sensed
on the internal address bus.
SC 2 is configured as Read/Write and is used to control the
direction of data bus transfers_ An CPU read is enabled when
Read/Write and E are high.
SC, and SC2 in Expanded Multiplexed Mode
In the Expanded Multiplexed Modes, both SCI and SC 2 are
configured as outputs. SCI functions as Address Strobe and can
be used to demultiplex the eight least significant addresses and
the data bus. A latch controlled by Address Strobe captures address on the negative edge, as shown in Figure 20.
SC 2 is configured as Read/Write and is used to control the
direction of data bus transfers. An CPU. read is enabled when
Read/Write and E are high.
Nominal Crystal Parameter
.~
4 MHz
5 MHz
Co
7 pF max.
4.7 pF max.
Rs
son max.
30n typo
------------
Item
----------~ID~I
XTAL ~--~~------~
CL1
= CL2 = 22pF ±20%
(3.2
~
5 MHz)
Co
Equivalent Circuit
EXTAL
~--~~...,
(Note) These are representative
AT cut parallel resonance
crystal parameters.
(al Nominal Recommended Crystal Parameters
U-4-.7~5-V----------~JfC------------------------------Vee
REs
--------------------~--------------~
~-----tAe------~
Oscillator
Stabilization
Time, tAe
(bl Oscillator Stabilization Time hRC)
Figure 15
Oscillator Characteristics
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
727
HD68P01V07,HD68P01V07-1 ,HD68P01 MO,HD68P01 M-1
• PORTS
There are four I/O ports on the MCU; three 8-bit ports and
one S-bit port. There are two control Jines associated with one
of the 8-bit ports. Each port has an associated write only Data
Direction Register which allows each I/O line to be programmed
to act as an input or an output. A "\" in the corresponding
Data Direction Register bit will cause that I/O line to be an output. A "0" in the corresponding Data Direction Register bit will
cause the I/O line to be an input. There are four ports: Port I .
Port 2, Port 3, and Port 4. Their addresses and the addresses of
their Data Direction registers are given in Table 2.
two lines, IS3 and OS3, which can be used to control Port 3
data transfers.
Three Port J options are wntrolled by the Port 3 Control
and Status Register and available only in Single-Chip Mode: (1)
Port 3 input data can be latched using IS3 as a control signal,
(2) OS3 can be generated by either an CPU read or write to
Port 3's Data Register. and (3) an I ROt interrupt can be enabled by an IS3- negative edge. Port 3 latch timing is shown in
Figure 6.
Port 3 Control and Status Register
Table 2 Port and Data Direction Register Addresses
Ports
I/O
I/O
I/O
I/O
Port 1
Port 2
Port 3
Port 4
Port Address
Data Direction
Register Address
$0002
$0003
$0006
$0007
$0000
$0001
$0004
$0005
$OOOF
Bit 0-2
Bit 3
•
P10-P17 (Port 1)
Port 1 is a mode independent 8-bit I/O port where each line
is an input or output as defined by its Data Direction Register.
The TTL compatible three-state output buffers can drive one
Schottky TTL load and 30 pF, Darlington transistors, or CMOS
devices using external pullup resistors. It is configured as a data
input port by RES. Unused lines can remain unconnected.
• P20-P24 (Port 2)
Port 2 is a mode independent S-bit I/O port where each line
is configured by its Data Direction Register. DUring .RES, all
lines are configured as inputs. The TTL compatible three-state
output buffers can drive one Schottky TTL load and 30 pF or
CMOS devices using external pullup resistors. P 20 , P2t and P 22
must always be connected to provide the operating mode. If
lines P23 and P24 are unused, they can remain unconnected.
P 20, P 2t, and P22 provide the operating mode which is
latched into the Program Control Register on the positive edge
of RES. The mode may be read from Port 2 Data Register as
shown where pe2 is latched from pin 10.
Port 2 also provides an interface for the Serial Communications Interface and Timer. Bit 1, if configured as an output, is
dedicated to the timer's Output Compare function and cannot
be used to provide output from Port 2 Data Register.
7
6
I
543
PCO \ P24
2
1
0
P22
P21
P20
I I I I
P23
Bit 5
Bit 6
Bit 7
Port 3 in Expanded Non-Multiplexed Mode
Port 3 is configured as a bidirectional data bus (Do - 0,) in
the Expanded Non-Multiplexed Mode. The direction of data
transfers is controlled by Read/Write (SC 2 ) and clocked by E
(Enable).
Port 3 in Expanded Multiplexed Mode
Port 3 is configured as a time multiplexed address (Ao - A,)
and data bus (Do - 0 7 ) in Expanded Multiplexed Mode where
Address Strobe (AS) can be used to demultiplex the two buses.
Port 3 is held in a high impedance state between valid address
and data to prevent potential bus conflicts.
Port 2 Data Register
\ PC2\ PCl
Bit 4
Not used.
LATCH ENABLE. This bit controls the input latch for Port 3. If set, input data is
latched by an IS3 negative edge. The latch
is transparent after a read of Port 3's Data
~ster. LATCH ENABLE is cleared by
RES.
OSS (Output Strobe Select). This bit determines whether OS3 will be generated by a
read or write of Port 3's Data Register.
When clear, the strobe is generated by a
read; when set, i~enerated by a write.
OSS is cleared by RES.
Not used.
IS3 IRO t ENABLE. When set, an IRO t
interrupt will be enabled whenever IS3
FLAG is set; when clear, the interrupt is
inhibited. This bit is cleared by RES.
IS3 FLAG. This read-only status bit is set
by an IS3 negative edge. It is cleared by a
read of the Port 3 Control and Status
Register (with IS3 FLAG set) followed by
a read or write to Port 3's Data Register or
by RES.
$0003
• P30-P37 (Port 3)
Port 3 can be configured as an I/O port, a bidirectional 8-bit
data bus, or a multiplexed address/data bus depending on the
operating mode. The TTL compatible three-state output buffers
can drive one Schottky TTL load and 90 pF. Unused lines can
remain unconnected.
• P40-P47 (Port 4)
Port 4 is configured as an 8·bit I/O port, address outputs, or
data inputs depending on the operating mode. Port 4 can drive
one Schottky TTL load and 90 pF and is the only port with
internal pullup resistors. Unused lines can remain unconnected.
Port 3 in Single-Chip Mode
Port 3 is an 8-bit I/O port in Single-Chip Mode where each
line is configured by its Data Direction Register. There are also
Port 4 in Single Chip Mode
In Single Chip Mode, Port 4 functions as an 8·bit I/O port
where each line is configured by its Data Direction Register.
728
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD68P01 V07,HD68P01V07-1 ,HD68P01 MO,HD68P01 M-1
Internal pullup resistors allow the port to directly interface with
CMOS at 5 volt levels. External pullup resistors to more than 5
volts, however, cannot be used.
Port 4 in Expanded Non-Multi~ed Mode
Port 4 is configured from RES as an 8-bit input port where
its Data Direction Register can be written to provide any or all
of address lines, Ao to A 7 • Internal pullup resistors are intended to pull the lines high until its Data Direction Register is
configured.
Port 4 in Expanded Multiplexed Mode
In all Expanded Multiplexed modes except Mode 6, Port ~
functions as half of the address bus a~rovides As to A IS • In
Mode 6, the port is configured from RES as an 8-bit parallel input port where its Data Direction Register can be written to
provide any or all of address lines, As to A is . Internal pullup
resistors are intended to pull the lines high until. its Data Direction Register is configured where bit 0 controls As.
• OPERATING MODES
The MCV provides eight different operating modes which are
selectable by hardware programming and referred to as Mode 0
through Mode 7. The operating mode controls the memory
map, configuration of Port 3, Port 4, SC I , SC 2, and the physical
location of interrupt vectors.
•
Fundamental Modes
The MCV's eight modes can be grouped into three fundamental modes which refer to the type of bus it supports: Single
Chip, Expanded Non-Multiplexed, and Expanded Multiplexed.
Single chip modes include 4 and 7, Expanded Non-Multiplexed
is Mode 5 and the remaining five are Expanded Multiplexed
modes. Table 3 summarizes the characteristics of the operating
modes.
Single Chip Modes (4, 71
In Single-Chip Mode, the MCV's four ports are configured as
parallel input/output data ports, as shown in Figure 16. The
MCV functions as a monolithic microcomputer in these two
modes without external address or data buses. A maximum of
29 I/O lines and two Port 3 control lines are provided. In addition to other peripherals, another MCV can be interfaced to
Port 3 in a loosely coupled dual processor configuration, as
shown in Figure 17.
In Single-Chip Test Mode (4), the RAM responds to $XX80
through $XXFF and the ROM is removed from the internal address map. A test program must first be loaded into the RAM
using modes 0, I, 2, or 6. If the MCV is Reset and then programmed into Mode 4, execution will begin at $XXFE: XXFF.
Mode 5 can be irreversibly entered from Mode 4 without going
through Reset by setting bit 5 of Port 2's Data Register. This
mode is used primarily to test Ports 3 and 4 in the Single-Chip
and Non-Multiplexed Modes.
Expanded Non-Multiplexed Mode (51
A modest amount of external memory space is provided in
the Expanded Non-Multiplexed Mode while retaining significant on-chip resources. Port 3 functions as an 8-bit bidirectional
data bus and Port 4 is configured as an input data port. Any
combination of the eight least-significant address lines may be
obtained by writing to Port 4's Data Direction Register. Stated
alternatively, any combination of Ao to A7 may be provided
whil~ retaining the remainder as input data lines. Internal pull-
up resistors are intended to pull Port 4's lines high until it is
configured.
Figure 18 illustrates a typical system configuration in the
Expanded Non-Multiplexed Mode. The MCV interfaces directly
with HMCS6800 family parts and can access 256 bytes of
external address space at $100 through $1 FF. lOS provides an
address decode of external memory ($100-$1 FF) and can
be used similarly to an address or chip select line.
Table 3 Summary of HD6800 Operating Modes
Common to all Modes:
Reserved Register Area
Port 1
Port 2
Programmable Timer
Serial Communication Interface
Single Chip Mode 7
128 bytes of RAM; 2048 bytes of ROM
Port 3 is a parallel I/O port with two control lines
Port 4 is a parallel I/O port
SCI is Input Strobe 3 (lS3)
SC2 is Output Strobe 3 (OS3)
Expanded Non-Multiplexed Mode 5
128 bytes of RAM; 2048 bytes of ROM
256 bytes of external memory space
Port 3 is an 8-bit data bus
Port 4 is an input port/address bus
SCI is Input/Output Select (lOS)
SC2 is read/write (R/W)
Expanded Multiplexed Modes 1, 2, 3, 6
Four memory space options (65k address space):
(1) No internal RAM or ROM (Mode 3)
(2) Internal RAM, no ROM (Mode 2)
(3) Internal RAM and ROM (Mode 1)
(4) Internal RAM, ROM with partial address bus (Mode 6)
Port 3 is a multiplexed address/data bus
Port 4 is an address bus (inputs/address in Mode 6)
SCI is Address Strobe (AS)
SC2 is Read/Write (RtWI
Test Modes 0 and 4
Expanded Multiplexed Test Mode 0
May be used to test RAM and ROM
Single Chip and Non·Multiplexed Test Mode 4
(1) May be changed to Mode 5 without going thr')ugh Reset
(2) May be used to test Ports 3 and 4 as I/O ports
Expanded-Multiplexed Modes (0,1, 2,3,61
In the Expanded-Multiplexed Modes, the MCV has the ability
to access a 65k bytes memory space. Port 3 functions as a time
multiplexed address/data bus with address valid on the negative
edge of Address Strobe (AS) and the data bus valid while E is
high. In Modes 0 to 3, Port 4 provides address line~ to Al s.
In Mode 6, however, Port 4 is configured during RES as data
port inputs and the Data Direction Register can be changed to
provide any combination of address lines, As to A is . Stated
alternatively, any subset of As to A is can be provided while
retaining the remainder as input data lines. Internal pullup
resistors are intended to pull Port 4's lines high until software
configures the port.
Figure 19 depicts a typical configuration for the ExpandedMultiplexed Modes. Address Strobe can be used to control a
transparent D-type latch to capture addresses Ao to A7 , as
shown in Figure 20. This allows Port 3 to function as a Data Bus
when E is high.
In Mode 0, the Reset vector is external for the first two Ecycles after the positive edge of RES and internal thereafter. In
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
729
HD68P01 V07,HD68P01V07-1 ,HD68P01 MO,HD68P01 M-1
addition, the internal and external data buses are connected and
there must be no memory map overlap to avoid potential bus
conflicts. Mode 0 is used primarily to verify the ROM pattern
and monitor the internal data bus with the automated test
equipment.
Vee
Vee
Vee
XTAL
Port 1
8110 lines
Port 3
81/0 Lines
Port 4
81/0 Lines
Port 2
5110 lines
Serial 1/0
16-Bit Timer
XTAL
f'ort 1
81/0
Lines
Vss
Port 2
5110 Lines
SCI
16-Bit Timer
Vss
Figure 16
Lines
16-Bit Timer
Single Chip Mode
Figure 17
Vee
Single Chip Dual Processor Configuration
Vee
Port 3
808t8 lines
Port 1
81/0 Lines
Port 1
81/0
Port 2
5110
Port 2
5110
SCI
Port 4
T08
Timer
Vss
Vss
Figure 18
Expanded Non-Multiplexed Configuration
Vee
Vee
XTAL
C=::J
~~~--~-.4-------,-~------r+--___ ~::~~~~S
16
R/W
HD68POI ~~------~~-----.~+-----~ti----+R/W
Port 1
81/0 Lines
Port 1
81/0
Port 2
5110 Lines
!leri.IIIO
1I1-BII Timer
Port 4
8 Lines
Address Bus
Port 2
5110
SCI
Timer
Vss
VSS
Figure 19
730
Expanded Multiplexed Configuration
$HITACftl
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - H D68P01 V07, H D68P01 V07-1, H D68P01 MO, H D68P01 M-1
GND
AS
I
G OC
0)
D)
74LS373
(Typical)
Port 3
[
Address/Data
08
Addre~
)
Function Table
A, - A,
Output
Control
G
0
0
L
L
L
H
H
H
L
X
H
L
X
X
H
L
Ob
Enable
Output
00
Z
) 0", 0, -0,
Figure 20
•
Typical Latch Arrangement
Programming The Mode
The operating mode is programmed by the levels asserted on
P22 , P2l , and P 20 which are latched into PC2, PCI, and pca of
the program control register on the positive edge of RES. The
operating mode may be read from Port 2 Data Register as
shown below, and programming levels and timing must be met
as shown in Figure 8. A brief outline of the operating modes is
shown in Table 4.
Circuitry to provide the programming levels is dependent
primarily on the normal system usage of the three pins. If configured as outputs, the circuit shown in Figure 21 may be used;
otherwise, three-state buffers can be used to provide isolation
while programming the mode.
Port 2 Data Register
7
6
5
4
321
PC2\ PCl \ PCO \ P241 P23\ P22\ P2l
0
P20
$0003
Table 4 Mode Selection Summary
Mode
P22
(PC2)
P2 )
(PC1)
P20
(PCO)
ROM
RAM
Interrupt
Vectors
Bus
Mode
7
H
H
H
I
I
I
I
6
H
H
L
I
I
I
MUXIS,6)
Operating Mode
Single Chip
Multiplexed/Partial Decode
5
H
L
H
I
NMUXIS,6)
H
L
L
112)
I
Ill)
I
4
I
3
2
L
H
H
E
E
E
I
MUX(4)
Multiplexed /No RAM or ROM
L
H
L
E
I
E
MUX(4)
Multiplexed /RAM
1
L
L
H
I
I
E
MUX(4)
Multiplexed/RAM & ROM
0
L
L
L
I
I
1(3)
MUX(4)
Multiplexed Test
Legend:
I - Internal
E - External
MUX - Multiplexed
NMUX - Non-MUltiplexed
L - Logic "0"
H - Logic "'"
Non·Multiplexed/Partial Decode
Single Chip Test
Notes:
(1) Internal RAM is addressed at $XX80
(2) Internal ROM is disabled
(3) RES vector is external for 2 cycles aher RES goes high
(4) Addresses associated with Ports 3 and 4 are considered external in Modes 0, I, 2, and 3
(5) Addresses associated with Port ~ are considered external in Modes 5 and 6
(6) Port 4 default is user data input; address output is optional by writing to Port 4 Dlltll Direction Aegilter
~HITACHI
Hitachi America Ltd, • 2210 O'Toole Ave, • San Jose, CA 95131 • (408) 435-8300
731
HD68P01V07,HD68P01V07-1 ,HD68P01 MO,HD68P01 M-1
Vee
(
:
R
~
RI RIC RI
6
111
A B C
HD68P01
Xo
r---
Yo
X
Zo
Y
XI
Z
RES
8
9
10
P20 (PCO)
P21 (PC1)
P22 (PC2)
YI
ZI
I
C
1
(
???
~
Mode
ContrOl
Switch
Figure 21
Inh
HD14053B
1) Mode 7 as shown
2) RC::::: Reset time constant
3) RI = 10kn
(NOTES)
~
Recommended Circuit for Mode Selection
Truth Table
Control Input
Inh
A
B
C
Inhibit
XoO------------------K~-r+-r1---,
X
XI
YO
YIo---------------------~~r1--~
Y
Zoo-----------------------~~r--,
ZI~-------------------------K~~
Figure 22
732
On Switch
Select
Binary to 1-of-2
Decoder with
Inhibit
Z
C B
A
0
0
0
0
Zo
YO
Xo
0
0
0
1
Zo
Yo
XI
0
0
1
0
Zo
YI
Xo
0
0
Zo
YI
XI
0
1 0
0
ZI
Yo
Xo
0
1
0
1
ZI
Yo
XI
0
1
1
0
ZI
YI
Xo
ZI
YI
XI
,,
0
, ,
1
X X X
1
HD14053B
-
HD14053B Multiplexers/Demultiplexers
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-1
• MEMORY MAPS
The MCV can provide up to 65k bytes address space depending on the operating mode. The HD68POI provides 8k bytes address space for EPROM, but the maps differ in EPROM types as
follows.
1) HN482732A (a 4k-byte EPROM)
In order to support the HD6801VO, EPROM of the
HD68POIV07jHD68POIV07-1 must be located at $FOOO$FFFF.
2) HN482764 (a 8k-byte EPROM)
The HD68POIMOjHD68POIMO-1 can provide up to
8k bytes address space using HN482764 instead of
HN482732A. In this case, EPROM of the HD68POIMOj
HD68POIMO-l is located at $EOOO-$FFFF.
A memory map for each operating mode is shown in Figure
23. The first 32 locations of each map are reserved for the
MCV's internal register area, as shown in Table 5, with exceptions as indicated.
Refer to "Precaution when emulating the HD6801 Family".
Table 5 Internal Register Area
Register
Port
Port
Port
Port
Address
1
2
1
2
Data
Data
Data
Data
Direction Register* *Direction Register* **
Register
Register
00
01
02
03
Port 3
Port 4
Port 3
Port 4
Data
Data
Data
Data
Direction Register***
Direction Register* *Register
Register
04*
05**
0607**
Timer Control and Status Register
Counter (High 8yte)
Counter (Low Byte)
Output Compare Register (High Byte)
08
09
OA
OB
Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Port 3 control and Status Register
OC
00
OE
OF*
Rate and Mode Control Register
Transmit/Receive Control and Status Register
Receive Data Register
Transmit Data Register
10
11
12
13
RAM Control Register
Reserved
14
15·1F
* External address in Modes 0, 1, 2, 3, 5,6; cannot be accessed in
Mode 5 (No lOS)
* - External addresses in Modes 0, 1, 2,3
* * * 1 "Output, 0 .. Input
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
733
HD68P01V07,HD68P01 V07-1 ,HD68P01 MO,HD68P01 M-1
HD68P01
Mode
o
HD68P01
Mode
Multiplexed Test mode
1
Multiplexed/RAM & EPROM
$0000(1)
$0000(1)
Internal Registers
Internal Registers
$OOlF
$OOlF
External Memory Space
External Memory Space
$0080
$0080
Internal RAM
Internal RAM
$,oOFF
$OOFF
External Memory Space
External Memory Space
$EOOO
$EOOO
EPROM
$FFEF
EPROM
$FFFF(2)
Internal Interrupt Vectors(2
(NOTESI
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and $OF.
2) Addresses $FFFE and $FFFF are considered
external if accessed within 2 cycles alter a
positive edge of RES and internal at all other
times.
3) After 2 CPU cycles, there must be no overlapping of internal and external memory
spaces to avoid driving the data bus with more
than one device.
4) This mode is the only mode which may be used
to examine the interrupt vectors in EPROM
using an external Reset vector.
Figure 23
734
$FFFO
$FFFF ....._ _ _J'
External Interrupt Vectors
[NOTESI
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and
$OF.
2) EPROM addresses $FFFO to $FFFF are
not usable.
HD68P01 Memory Maps
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - HD68POl V07,HD68POl V07-1 ,HD68POl MO,H D68POl M-l
2
HD68P01
Mode
HD68P01
Mode
Multiplexed/RAM
3
Multiplexed/No RAM or EPROM
$0000(1'
$0000(1'
} Internal Registers
Internal Registers
$oolF
$OOlF
External Memory Space
$0080
Internal RAM
$OOFF
External Memory Space
External Memory Space
$FFFO I - - - - - t ,
$F FF F '--_ _ _... }
$FF FO
External Interrupt Vectors
'-----I
$FFFF '--_ _ _.... }
l'
[NOTE]
Excludes the following addresses which may
be used externally: $04, $05, $06, $07, and
$OF.
Figure 23
External Interrupt Vectors
[NOTE]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and
$OF.
HD68P01 Memory Maps (Continued)
~HITACHI
Hitachi America Ltd, • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
735
HD68P01V07,HD68P01V07-1 ,HD68POl MO,HD68P01 M-1
HD6BP01
Mode
HD6BP014
Mode
Single Chip Test
5
Non-Multiplexed/Partial Decode
$0000(1)
$0000
Internal Registers
} Internal Registers
$001F
$001F
$0080
} Internal RAM
$ooFF
$0100
} External Memory Space
$01FF
U
1)(4)
$EOOO
EPROM
$XX80
$XXFF
Internal RAM
Internal Interrupt Vectors
[NOTES)
1) The internal ROM is disabled.
2) Mode 4 may be changed to Mode 5 without
having to assert RESET by writing a "1" into
the PCO bit of Port 2 Data Register.
3) Addresses A. to A,. are treated as "don't
cares" to decode internal RAM.
4) Internal RAM will appear at $XX80 to $XXFF.
Figure 23
736
$FFFF
Internal Interrupt Vectors
[NOTES)
1) Excludes the following addresses which may
not be used externally: $04, $06, and $OF.
(No lOS)
2) This mode may be entered without going
through RESET by using Mode 4 and subsequently writing a "1" into the PCO bit of
Port 2 Data Register.
3) Address lines A. - A. will not contain addresses until the Data Direction Register for Port 4
has been written with "1's" in the appropriate
bits. These address lines will assert "1's" until
made outputs by writing the Data Direction
Register.
HD6BP01 Memory Maps (Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - HD68POl V07,H D68POl V07-1, HD68POl MO,H D68POl M-l
HD68P01
Mode
6
HD68P01
Mode
7
Single Chip
Multiplexed/Partial Decode
$0000(1)
Internal Registers
Internal Registers
$OOlF
External MelT,ory Space
$0080
$0080
Internal RAM
} Internal RAM
$OOFF
$OOFF
External Memory Space
$EOOO
EPROM
$FFFF
EPROM
)
Internal Interrupt Vectors
Internal Interrupt Vectors
$FFFF
[NOTES)
1) Excludes the following address which may be
used externally: $04, $06, $OF.
2) Address lines A.-A" will not contain
addresses until the Data Direction Register for
Port 4 has been written with "l's" in the
appropriate bits. These address lines will
assert "l's" until made outputs by writing the
Data Direction Register.
Figure 23 HD68P01 Memory Maps (Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
737
HD68P01V07,HD68P01V07-1 ,HD68P01 MO,HD68P01 M-1
• PROGRAMMABLE TIME
The Programmable Timer can be used to perform input waveform measurements while independently generating an output
waveform_ Pulse widths can vary from several microseconds to
many seconds. A block diagram of the Timer is shown in Figure
24.
• Counter ($09:0A)
The key timer element is a 16-bit free-running counter which
is incremented by E (Enable). It is cleared during RES and is
read-only with one exception: a write to the counter ($09) will
preset it to $FFF8. This feature, intended for testing, can disturb serial operations because the counter provides the SCI's
internal bit rate clock. TOF is set whenever the counter contains
alii's.
• Output Compare Register ($OB:OC)
The Output Compare Register is a 16-bit Read/Write register
used to control an output waveform or provide an arbitrary
timeout flag. It is compared with the free-running counter on
each E-cyde. When a match is found, OCF is set and OLVL is
clocked to an output level register. If Port 2, bit 1, is configured
as an output, OLVL will appear at P 21 and the Output Compare
Register and OLVL can then be changed for the next compare.
The function is inhibited for one cycle after a write to its high
byte of the Compare Resister ($OB) to ensure a valid compare.
The Output Compare Register is set to $FFFF by RES.
•
Input Capture Register ($00: OE)
The Input Capture Register is a 16-bit read-only register used
to store the free-running counter when a "proper" input transition occurs as defined by IEDG. Port 2, bit 0 should be configured as an input, but the edge detect circuit always senses P 20
even when configured as an output. An input capture can occur
independently of ICF: the register always contains the most current value. Counter transfer is inhibited, however, between accesses of a double byte CPU read. The input pulse width must
be at least two E-cycles to ensure an input capture under all
conditions.
• Timer Control and Status Register ($08)
The Timer Control and Status Register (TCSR) is an 8-bit
register of which all bits are readable while bits 0--4 can be
written. The three most significant bits provide the timer's
status and indicate if:
a proper level transition has been dtected,
a match has been found between the free-running counter
and the output compare register, and
the free-running counter has overflowed.
Each of the three events can generate an IRQ2 interrupt and
is controlled by an individual enable bit in the TCSR.
HD68POl Internal Bus
Timer b~7~~~~r-~__r-~~~~1
Control
I
And
I,--'-r--&..,-.....L...,.....~.....L..,..-l--......~
Status
Register
Bit 1
Port 2
DDR
$08
.---I
_____ : Output Input
Level Edge
BitO
Bit 1
Port 2 Port 2
Figure 24
738
Block Diagram of Programmable Timer
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-1
clock: external or internal bit rate clock
Baud (or bit rate): one of 4 per E-c1ock frequency, or external bit rate (X8) input
wake-up feature: enabled or disabled
interrupt requests: enabled individually for transmitter
and receiver
clock output: internal bit rate clock enabled or disabled
to P22
Port 2 (bit 3,4): dedicated or not dedicated to serial I/O
individually for transmitter and receiver.
Timer Control and Status Register (TCSR)
7
6
Bit 0 OLVL
Bit 1 IEDG
Bit 2 ETOI
Bit 3 EOCI
Bit 4 EICI
Bit 5 TOF
Bit 6 OFC
Bit 7 ICF
•
543
2
1
0
Output level. OLVL is clocked to the output
level register by a successful output compare and
will appear at P21 if Bit 1 of Port 2's Data Direction Register is set. It is cleared by RES.
Input Edge. IEDG is cleared by RES and controls
which level transition will trigger a counter transfer to the Input Capture Register:
IEDG =0 Transfer on a negative-edge
IEDG = 1 Transfer on a positive-edge.
Enable Timer Overflow Interrupt. When set, an
IRQ2 interrupt is enabled for a timer overflow;
when clear, the interrupt is inhibited. It is cleared
by RES.
Enable Output Compare Interrupt. When set, an
IRQ2 interrupt is enabled for an output compare; when clear, the interrupt is inhibited. It is
cleared by RES.
Enable Input Capture Interrupt. When set, an
IRQ2 interrupt is enabled for an input capture;
when clear, the interrupt is inhibited. It is
cleared by RES.
Timer Overflow Flag. TOF is set when the
counter contains $FFFF. It is cleared by reading
the TCSR (with TOF set) followed by the
counter's high byte ($09), or by RES.
Output Compare Flag. OCF is set when the Output Compare Register matches the free-running
counter. It is cleared by reading the TCSR(with
OCF set) and then writing to the Output Compare Register ($OB or SOC), or by RES.
Input Capture Flag. ICF is set to indicate a
proper level transition; it is cleared by reading
the TCSR (with ICF set) and then the Input
Capture Register High Byte ($00), or by RES.
SERIAL COMMUNICATIONS INTERFACE (SCI)
A full-duplex asynchronous Serial Communications Interface
(SCI) is provided with a data format and a variety of rates. The
SCI transmitter and receiver are functionally independent, but
use the same data format and bit rate. Serial data format is
standard mark/space (NRZ) and provides one start bit, eight
data bits, and one stop bit. "Baud" and "bit rate" are used
synonymously in the following description.
•
The Serial Communications Interface includes four addressable registers as depicted in Figure 25. It is controlled by the
Rate and Mode Control Register and the Transmit/Receive Control and Status Register. Data is transmitted and received utilizing a write-only Transmit Register and a read-only Receive
Register. The shift registers are not accessible to software.
Bit 7
Rate and Mode Control Register
I I I I I Icco I I
X
X
X
X
Bit 0
551 550 1$10
CCI
Transmit/Receive Control and Status Register
Port 2
Receive Shift Register
C~~kle-~l~O_ _ _ _ _ _...-.I
....- - - E
2
Tx
Bit .....--.:'=-.2_ _ _ _ _ _ _ __
4
Transmit Data Register
Figure 25
SCI Registers
Wake-Up Feature
In a typical serial loop multi-processor configuration, the
software protocol will usually identify the addresse(s) at the
beginning of the message. In order to permit uninterested MCU's
to ignore the remainder of the message, a wake-up feature is
included whereby all further SCI receiver flag (and interrupt)
processing can be inhibited until its data line goes idle. An SCI
receiver is re-enabled by an idle string of ten consecutive l's or
by RES. Software must provide for the required idle string
between consecutive messages and prevent it within messages.
•
• Serial Communications Registers
Rate and Mode Control Register (RMCR) ($10)
The Rate and Mode Control Register controls the SCI bit
rate, format, clock source, and under certain conditions, the
configuration of P 22 . The ~ster consists of four write-only
bits which are cleared by RES. The two least significant bits
control the bit rate of the internal clock and the remaining two
bits control the format and clock source.
Rate and Mode Control Register (RMCR)
6543210
Programmable Options
The following features of the SCI are programmable:
format: Standard mark/space (NRZ)
I I I I I I I I I
X
X
X
X
ee1
eeo
551
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
5SO
$0010
739
HD68P01V07,HD68P01 V07-1 ,HD68P01MO,HD68P01 M-1
Bit 1: Bit 0
SSl: SSO Speed Select. These two bits select the
Baud when using the internal clock. Four rates
may be selected which are a function of the MCV
input frequency. Table 6 lists bit time and rates
for three selected MCV frequencies.
CCI :CCO Clock Control Select. These two bits
Bit 3: Bit 2
select the serial clock source. If CCI is set, the
DDR value for Pu is forced to the complement
of CCO and cannot be altered until CC I is
cleared. If CCI is cleared after haVing been set,
its DDR value is unchanged. Table 7 defines the
clock source, and use ofP 22 .
If both eCI and CCO are set, an external TTL compatible
clock must be connected to P 22 at eight times (8X) the desired
bit rate, but not greater than E, with a duty cycle of 50% (±
10%). IfCCI:CCO = 10, the internal bit rate clock is provided at
P 22 regardless of the values for TE or RE.
Bit 2 TIE
Bit 3 RE
Bit 4 RIE
Bit 5 TDRE
(Note) The source of SCI internal bit rate clock is the timer's free run·
ning counter. An CPU write to the counter can disturb serial
operations.
Transmit/Receive Control and Status Register (TRCSR) ($11)
The Transmit/Receive Control and Status Register controls
the transmitter, receiver, wake-up feature, and two individual
interrupts and monitors the status of serial operations. All eight
bits are readable while bits 0 to 4 are also writable. The register
is initialized to $20 by RES.
Bit 60RFE
Transmit/Receive Control and Status Register (TRCSR)
7
6
5
4
3
2
1
IRDRfRFEITDREI RIE I RE I TIE I TE
0
Iwu I
$0011
"Wake-up" on Idle Line. When set, WV enables
the wake-up function; it is cleared by ten con·
secutive 1's or by RES. WV will not set if the line
is idle.
Transmit Enable. When set, P 24 DDR bit is set,
cannot be changed, and will remain set if TE is
subsequently cleared. When TE is changed from
clear to set, the transmitter is connected to P 24
BitOWU
Bit 1 TE
Bit 7 RDRF
and a preamble of nine consecutive l's is transmitted. TE is cleared by RES.
Transmit Interrupt Enable. When set, an IRQ2
interrupt is enabled when TDRE is set; when
clear, the interrupt is inhibited. TE is cleared by
RES.
Receive Enable. When set, P23 's DDR bit is
cleared, cannot be changed, and will remain clear
if RE is subsequently cleared. While RE is set,
~SCI receiver is enabled. RE is cleared by
RES.
Receiver Interrupt Enable. When set, an IRQ 2
interrupt is enabled when RDRF and/or ORFE is
set; when clear, the interrupt is inhibited. RIE is
cleared by RES.
Transmit Data Register Empty. TDRE is set
when the Transmit Data Register is transferred to
the output serial shift register or by RES. It is
cleared by reading the TRCSR (with TDRE set)
and then writing to the Transmit Data Register.
Additional data will be transmitted only if TDRE
has been cleared.
Overrun Framing Error. If set, ORFE indicates
either an overrun or framing error. An overrun is
a new byte ready to transfer to the Receiver Data
Register with RDRF still set. A receiver framing
error has occurred when the byte boundaries of
the bit stream are not synchronized to the bit
counter. An overrun can be distinguished from a
framing error by the value of RDRF: if RDRF is
set, then an overrun has occurred; otherwise a
framing error has been detected. Data is not
transferred to the Receive Data Register in an
overrun or framing error condition. ORFE is
cleared by reading the TRCSR (with ORFE set)
then the Receive Data Register, or by RES.
Receive Data Register Full. RDRF is set when
the input serial shift register is transferred to the
Receive Data Register. It is cleared by reading
the TRCSR (with RDRF set), and then the Receive Data Register, or by RES.
Table 6 SCI Bit Times and Rates
SSl
0
0
1
1
:
XTAL
E
E 716
E 7128
E 71024
E 7 4096
SSO
0
1
0
1
2.4576 MHz
614.4 kHz
26 /15/38,400 Baud
20Blls/4,800 Baud
1.67ms/600 Baud
6.67ms/150 Baud
4.0 MHz
1.0 MHz
16 /15/62,500 Baud
128/15/7812.5 Baud
1.024ms/976.6 Baud
4.096ms/244.1 Baud
4.9152 MHz*
1.2288 MHz
13/15/76,800 Baud
104.2115/9,600 Baud
833.3/15/1,200 Baud
3.33 ms/300 Baud
* HD68P01V07·1, HD68P01MO-l only
Table 7 SCI Format and Clock Source Control
CC1: CCO
0
0
1
0
1
0
1
1
Format
Clock Source
Port 2 Bit 2
Port 2 Bit 3
-
-
-
Port 2 Bit 4
NRZ
NRZ
Internal
Not Used
Output*
**
**
**
**
NRZ
Internal
External
• Clock output is available regardless of values for bits RE and TE .
•• Bit 3 is used for serial input if RE = "'" in TRCS; bit 4 is used for serial output if TE
740
**
**
Input
= "1"
-
in TRCS.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-1
•
Internally Generated Clcok
If the user wishes for the serial I/O to furnish a clock, the follOwing requirements are applicable:
• the values of RE and TE are immaterial.
CCI, CCO must be set to 10
the maximum clock rate will be E 7 16.
• the clock will be at 1X the bit rate and will have a rising
edge at mid-bit.
Externally Generated Clock
If the user wishes to provide an external clock for the serial
I/O, the following requirements are applicable:
the CCl, CCO, field in the Rate and Mode Control Register must be set to 11,
• the external clock must be set to 8 times (X8) the desired
baud rate and
• the maximum external clock frequency is 1.0 MHz.
Then the 8 data bits (beginning with bit 0) followed by the stop
bit (1), are transmitted. When the Transmitter Data Register has
been emptied, the TDRE flag bit is set.
If the MCV fails to respond to the flag within the proper time, (TDRE is still set when the next normal transfer from
the parallel data register to the serial output register should
occur) then a 1 will be sent (instead of a 0) at "Start" bit time,
followed by more l's until more data is supplied to the data
register. No D's will be sent while TDRE remains a 1.
•
•
Serial Operations
The SCI is initialized by writing control bytes first to the
Rate and Mode Control Register and then to the Transmit/Receive Control and Status Register.
The Transmitter Enable (TE) and Receiver Enable (RE) bits
may be left set for dedicated operations.
Transmit operations
The transmit operation is enabled by TE in the Transmit/Receive Control and Status Register. When TE is set, the output of
the transmit serial shift register is connected to P24 and the
serial output by first transmitting to a ten-bit preamble of I's.
Following the preamble, internal synchronization is established
and the transmitter section is ready for operation.
At this point one of two situation exist:
I) if the Transmit Data Register is empty (TDRE = I ), a continuous string of ones will be sent indicating an idle line,
or,
2) if a byte has been written to the Transmit Data Register
(TDRE = 0), it is transferred to the output serial shift register and transmission will begin.
During the transfer itself. the start bit (0) is first transmitted.
Receive Operations
The receive operation is enabled by RE which configures
P23 . The receive operation is controled by the contents of the
Transmit/Receive Control and Status Register and the Rate and
Mode Control Register.
The receiver bit interval is divided into 8 sub-intervals for
internal synchronization. In the NRZ Mode, the received bit
stream is synchronized by the first 0 (space) encountered.
The approximate center of each bit time is strobed during
the next 10 bits. If the tenth bit is not a 1 (stop bit) a framing
error is assumed, and ORFE is set. If the tenth bit is aI, the
data is transferred to the Receive Data Register, and interrupt
flag RDRF is set. If RDRF is still set at the next tenth bit time,
ORFE will be set, indicating an over-run has occurred. When the
MCV responds to either flag (RDRF or ORFE) by reading
the status register followed by reading the Data Register, RDRF
(or ORFE) will be cieared.
•
INSTRUCTION SET
The HD68POI is upward source and object code compatible
with the HD6800. Execution times of key instructions have
been reduced and several new instructions have been added,
including hardware multiply. A list of new operations added to
the HD6800 instruction set is shown in Table 8.
In addition, two new special opcodes, 4E and SE, are provided for test purposes. These opcodes force the Program Counter
to increment like a l6-bit counter, causing address lines used
in the expanded modes to increment until the device is reset.
These opcodes have no mnemonics.
Table 8 New Instructions
Instruction
Description
ABX
ADDD
ASLD
BRN
LDD
LSRD
MUL
PSHX
PULX
STD
SUBD
Unsigned addition of Accumulator B to Index Register
Adds (without carry) the double accumulator to memory and leaves the sum in the double accumulator
Shifts the double accumulator left (towards MSB) one bit; the LSB is cleared and the MSB is shifted into the C-bit
Branch Never
Loads double accumulator from memory
Shifts the double accumulator right (towards LSB) one bit; the MSB is cleared and the LSB is shifted into the C-bit
Unsigned multiply; multiplies the two accumulators and leaves the product in the double accumulator
Pushes the Index Register to stack
Pulls the Index Register from stack
Stores the double accumulator to memory
Subtracts memory from the double accumulator and leaves the difference in the double accumulator
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
741
HD68P01V07,HD68P01V07-1 ,HD68P01 MO,HD68P01 M-1
• Programming Model
A programming model for the HD68POl is shown in Figure
10. Accumulator A can be concatenated with accumulator B
and jointly referred to as accumulator D where A is the most
significant byte. Any operation which modifies the double
accumulator will also modify accumulator A and/or B. Other
registers are defined as follows:
• Addressing Modes
The CPU provides six addressing modes which can be used
to reference memory. A summary of addressing modes for all
instructions is presented in Table 9, 10, 11, and 12 where execution times are provided in E-cycles. Instruction execution times
are summarized in Table 13. With an input frequency of 4 MHz,
E-cycles are equivalent to microseconds. A cycle-by-cycle
description of bus activity for each instruction is provided in
Table 14 and a description of selected instructions is shown in
Figure 26.
Program Counter
The program counter is a 16-bit register which always points
to the next instruction.
Immediate Addressing
The operand or "immediate byte(s)" is contained in the following byte(s) of the instruction where the number of bytes
matches the size of the register. These are two or three byte
instructions.
Stack Pointer
The stack pointer is a 16-bit register which contains the address of the next available location in a pushdown/pullup
(LIFO) queue. The stack resides in random access memory at a
location defined by the programmer.
Direct AddreSSing
The least significant byte of the operand address is contained
in the second byte of the instruction and the most Significant
byte is assumed to be $00. Direct addressing allows the user to
access $00 through $FF using two·byte instructions and execution time is reduced by eliminating the additional memory access. In most applications, the 2S6-byte area is reserved for
frequently referenced data.
Index Register
The Index Register is a 16-bit register which can be used to
store data or provide an address for the indexed mode of
addressing.
Accumulators
The CPU contains two 8-bit accumulators, A and S, which
are used to store operands and results from the arithmetic logic
unit (ALU). They can also be concatenated and referred to as
the D (double) accumulator.
Extended Addressing
The second and third bytes of the instruction contain the absolute address of the operand. These are three byte instructions.
Condition Code Registers
The condition code register indicates the results of an instruction and includes the following five condition bits: Negative (N), Zero (Z), Overflow (V), Carry/Borrow from MSB (C),
and Half Carry from bit 3 (H). These bits are testable by the
conditional branch instruction. Bit 4 is the interrupt mask
(I-bit) and inhibits all maskable interrupts when set. The two
unused bits, b6 and b7 are read as ones.
Indexed Addressing
The unsigned offset contained in the second byte of the instruction is added with carry to the Index Register and used to
reference memory without changing the Index Register. These
are two byte instructions.
Table 9 Index Register and Stack Manipulation Instructions
Pointer Operations
Compare Index Reg
Mnemonic
CPX
Immed
Direct
OP
-
#
OP
8C
4
-
3
9C
5
Extend
Index
-
#
OP
2
AC 6
#
OP
2
BC
6
Implied
#
OP
-
Boolean/
Arithmetic Operation
#
3
X - M: M+ 1
Decrement Index Reg
DEX
09
3
1
X-1-X
Decrement Stack Pntr
DES
34
3
1
SP -1 - SP
X + 1- X
Increment Index Reg
INX
08
3
1
Increment Stack Pntr
INS
31
3
1
Load Index Reg
LDX
CE
3
3
DE
Load Stack Pntr
LDS
8E
3
3
9E
Store Index Reg
STX
DF
Store Stack Pntr
STS
9F
4
Indell Reg - Stack Pntr
TXS
35
3
1
X-1-SP
StIck Pntr .... Index Reg
TSX
30
3
1
SP+1-X
SP + 1- SP
2
FE
5
3
M- X H • (M+ 1)- XL
5
2
BE
5
3
5
2
FF
5
3
M- SP H • (M+1)-SP L
XH - M. XL - 1M + 1)
2
BF
5
3
2
EE
4
2
AE
4
2
EF
2
AF
5
4
5
SPH - M. SP L - IM+1)
Add
ABX
3A
3
1
B + X- X
PUlh Data
PSHX
3C
4
1
XL - MSp. SP -1 - SP
Pull Data
PULX
38
5
1
SP + 1- SP. MSp- X H
SP + 1- SP. MSp- XL
Condo Code Reg.
5
4
3
H
I
N Z
2
C
• • t t t t
• • t • •
• • • • • •
t •
•
• • • •
t t R •
• • t t R •
• • t t R •
• • t t R •
• • • • • •
• • • • • •
• • • • • •
• • • • •
·
·· ·· ·· ·
·
XH - Msp. SP -1 - SP
• • • • • •
The Condition Code Register notes are listed after Table 12.
742
1 0
V
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-1
Implied Addressing
The operand(s) are registers and no memory reference is
required. These are single byte instructions.
the branch condition is true, the Program Counter is overwritten
with the sum of a signed single byte displacement in the second
byte of the instruction and the current Program Counter. This
provides a branch range of - 126 to 129 bytes from the first
byte of the instruction. These are two byte instructions.
Relative Addressing
Relative addressing is used only for branch instructions. If
Table 10 Accumulator and Memory Instructions
Accumulator and
Memory Operations
Mnemonic
Immed
OP
-
Direct
#
OP
-
Extend
Index
#
OP
-
#
OP
-
Implied
#
OP
-
#
lB
2
1
3A
3
1
Condo Code Reg.
Boolean Expression
H
I
A+B-+A
~
B + X-+X
•
• ~ ~ ~ ~
• • • • •
• ~ ~ ~ ~
• ~ ~ ~ ~
• ~ ~ ~ ~
• ~ ~ ~ ~
• ~ ~ ~ ~
• ~ ~ R •
• ~ ~ R •
• ~ ~ ~ ~
• ~ ~ ~ ~
• ~ ~ ~ ~
• ~ ~ ~ ~
• ~ ~ ~ ~
• ~ ~ ~ ~
• ~ ~ ~ ~
• ~ ~ R •
• ~ ~ R •
• ~ ~ ~ ~
• R S R R
Add Acmltrs
ABA
Add B to X
ABX
Add with Carry
ADCA
89
2
2
99
3
2
A9
4
2
B9
4
3
A+M+C-+A
~
ADCB
C9
2
2
09
3
2
E9
4
2
F9
4
3
B+M+C-+8
~
ADDA
8B
2
2
9B
3
2
AB 4
2
BB
4
3
A + M-+A
ADDB
CB
2
2
DB 3
2
EB
4
2
FB
4
3
B + M-+A
~
~
Add
Add Double
ADDD
C3
4
3
03
5
2
E3
6
2
F3
6
3
0+ M:M + 1-..0
And
ANDA
84
2
2
94
3
2
A4 4
2
B4
4
3
A • M-+A
ANDB
C4
2
2
04
3
2
E4
4
2
F4
4
3
B'M-+B
68
6
2
78
6
3
Shift left, Arithmetic
ASl
ASlA
48
2
1
ASlB
58
2
1
05
3
1
ASRA
47
2
1
ASRB
57
2
1
Shift left Obi
ASlD
Shift Right. Arithmetic
ASR
Bit Test
,
2
77
6
3
85
2
2
95
3
2
A5
4
2
B5
4
3
BITB
C5
2
2
05
3
2
~5
4
2
F5
4
3
CBA
Clear
ClR
l's Complement
6
BITA
Compare Acmltrs
Compare
67
6F
6
2
7F
6
1
3
A-B
OO-+M
4F
2
1
00 -+A
5F
2
1
OO-+B
CMPA
81
2
2
91
3
2
Al
4
2
Bl
4
3
A-M
CMPB
Cl
2
2
01
3
2
El
4
2
Fl
4
3
B- M
63
6
2
73
6
3
COM
M-+M
COMA
43
2
1
A-+A
COMB
53
2
1
B-+B
19
2
1
DAA
DEC
6A
6
2
7A 6
DECB
EORA
88
2
2
98
3
2
EORB
C8
2
2
08
3
2
INC
4
4A
2
1
A-l-+A
5A
2
1
B-l-+B
2
3
E8
4
2
F8
4
3
B (f) M-..B
6C
6
2
7C
6
3
M + 1 -+M
INCA
4C
2
1
A + l-+A
INCB
5C
2
1
B + 1 -+B
86
2
2
96
3
2
A6 4
2
B6
4
3
lDAB
C6
2
2
06
3
2
E6
4
2
F6
4
3
M-+B
load Double
lDD
CC
3
3
DC 4
2
EC
5
2
FC
5
3
M:M+l-+D
logical Shift. left
lSl
68
6
2
78
6
3
Shift Right, logical
lSlA
48
2
1
lSlB
58
2
1
lSlD
05
3
1
44
2
1
lSR
64
6
2
74
lSRA
6
·
·
3
lSRB
54
2
1
lSRD
04
3
1
•
•
•
•
•
•
•
•
•
•
• •
• •
•
• •
• •
• •
• •
•
• •
• •
•
• •
• •
.. _- •
• •
•
M-+A
lDAA
·•
----_._.
·
Z V C
R
S R R
R
S R R
~
~
t t t
~
~ R S
~
R
S
t
~ R S
~ t t
~
~
~
~
~
~
t
~
~
~ R
t
t
~ R
~ ~
~
!
~
~
~
t t
·
Ai±)M-..A
4
A8
B8
Adj binary sum to BCD
M-l-+M
3
DECA
load Acmltrs
2
ClRA
Decimal Adj. A
Increment
B'M
11
ClRB
Decrement
Exclusive OR
A·M
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
•
•
•
•
•
•
~ t t
t ~ t
~ t R
~ t R
t t R
~ t t t
~
~
~
~
~
~
~
t
~
~
R
R
R
R
~
t t
t t
f ~ f
f f f
f f f
(Continued I
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
743
HD68P01V07,HD68P01V07-1 ,HD68POl MO,HD68POl M-l
Table 10 Accumulator and Memory Instructions (Continued)
Accumulator and
Memory Operations
Mnemonic
Multiply
MUL
2's Complement
(Negate)
NEG
Immed
OP
-
Direct
#
OP
-
Index
#
OP
-
Extend
#
OP
-
Implied
#
OP
-
#
3D 10 1
60
6
2
70
6
Boolean Expression
AXB-+D
OO-M-+M
3
NEGA
40
2
1
NEGB
50
2
1
OO-A-+A
OO-B-+B
No Operation
NOP
01
2
1
PC + 1 -+PC
Inclusive OR
OAAA
8A 2
2
9A 3
2
AA 4
2
BA 4
3
OAAB
CA 2
2
DA 3
2
EA 4
2
FA 4
3
A + M-+A
B+M-+B
Push Data
PSHA
36
PSHB
37
3
1
B -+ Stack
Pull Data
PULA
32
4
1
Stack -+A
33
4
1
Stack -+ B
49
2
1
59
2
1
AOAA
46
2
1
AORB
56
2
1
10
2
1
PULB
Aotate Left
AOL
69
6
2
79
6
AOLB
AOA
66
6
2
76
6
1
A -+Stack
3
AOLA
Aotate Aight
3
3
A-B-+A
Subtract Acmltr
SBA
Subtract with Carry
SBCA
82
2
2
92
3
2
A2 4
2
B2
4
3
A-M-C-+A
SBCB
C2
2
2
02 3
2
E2
4
2
F2
4
3
B-M-C-+B
Store Acmltrs
Subtract
STAA
97
3
2
A7
4
2
B7
4
3
A-+M
STAB
07 3
2
E7
4
2
F7
4
3
B-+M
STD
DO 4
2
ED 5
2
FD 5
3
O-+M:M + 1
3
2
AO 4
2
BO
4
3
A - M-+A
B-M-+B
SUBA
80
2
2
90
SUBB
CO
2
2
00 3
2
EO
4
2
FO
4
3
Subtract Double
SUBD
83
4
3
93
2
A3 6
2
B3
6
3
Transfer Acmltr
TAB
16
2
1
A-+B
TBA
17
2
1
B-+A
TSTA
40
2
1
A -00
TSTB
50
2
1
B - 00
Test, Zero or Minus
TST
5
60
6
2
70
6
D-M:M+1-+D
3
M -00
The Condition Code Aegister notes are listed after Table 12.
744
Condo Code Reg.
H
I
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•• • •
·•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
·
N Z V
C
t
t t ~ t
t t t t
t t ~ ~
• • • •
t t A •
t t A •
• • • •
• • • •
• • • •
• • • •
t t t
t t t
t t t
t t t
t t ~
t
t
t
t
t
t t ~ t
t t t t
t t t t
t t t t
t t R •
t t A •
t t A •
t t t t
t t t t
t t t t
t t A •
t t A •
t t A R
t t A A
t t A A
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-1
Table 11
Operations
Mnemonic
Direct
OP
-
Jump and Branch Instructions
Relative
# OP
-
#
Index
OP
-
Extend
#
OP
-
Condo Code Reg.
Implied
#
-
OP
Branch Test
#
Branch Always
BRA
20
3
2
None
Branch Never
BRN
21
3
2
None
Branch If Carry Clear
BCC
24
3
2
C=O
Branch If Carry Set
BCS
25
3
2
C=1
Branch If • Zero
BEQ
27
3
2
Z=1
Branch If ~ Zero
BGE
2C
3
2
N (±) V =0
> Zero
BGT
2E
3
2
Z + (N
BHI
22
3
2
C+Z=O
Branch If Higher or Same
BHS
24
3
2
C=O
Branch If ~ Zero
BlE
2F
3
2
Z + (N
Branch If Carry Set
BlO
25
3
2
C=1
Branch If
Branch If Higher
<±l
<±l
Branch If lower Or Same
BlS
23
3
2
C+Z=1
< Zero
BlT
20 3
2
N
Branch If Minus
BMI
2B
3
2
N=1
Branch If Not Equal Zero
BNE
26
3
2
N=O
Branch If Overflow Clear
BVC
2B
3
2
V=O
Branch If
<±l
Branch If Overflow Set
BVS
29
3
2
V =1
Branch If Plus
BPl
2A 3
2
N=O
Branch To Subroutine
BSR
80 6
2
Jump
JMP
Jump To Subroutine
JSR
3
2
7E
3
3
AD 6
2
&0 6
3
6E
90
5
2
No Operation
NOP
01
Return From Interrupt
RTI
3B 10 1
Return From Subroutine
RTS
39
2
5
V) = 1
V =1
1
Software Interrupt
SWI
3F 12 1
WAI
3E
4
3
H
I
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
~
2 1 0
Z V C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
·• ·• •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
~
~
~
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
~
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
~
• • • • • •
• S • • • •
• • • • • •
1
Wait For Interrupt
9
V) = 0
5
1
The Condition Code Register notes are listed after Table 12.
Table 12 Condition Code Register Manipulation tnstructions
Clear Carry
Condo Code Reg.
Implied
Operations
Mnemonic
OP
ClC
OC
2
Boolean Operation
#
O .... C
1
5
4
3
2
1
0
H
I
N
Z
V
C
• • •
• R •
• • •
• •
• S •
• • •
• • R
• • •
Clear Interrupt Mask
CLI
OE
2
1
0·- I
Clear Overflow
ClV
OA
2
1
Set Carry
SEC
00
2
1
0"" V
1 .... C
Set Interrupt Mask
SEI
OF
2
1
1 .... 1
Set Overflow
SEV
OB
2
1
1-V
Accumulator A- CCR
TAP
06
2
1
A- CCR
~
CCR - Accumulator A
TPA
07
2
1
CCR - A
• • • • • •
LEGEND
OP Operation Code (Hexadecimal)
- Number of MPU Cycles
Msp Contents of memory location pointed to by Stack Pointer
# Number of Program Bytes
+ Arithmetic Plus
- Arithmetic Minus
• Boolean AND
X Arithmetic Multiply
+ Boolean Inclusive OR
<±l Boolean Exclusive OR
M Complement of M
-+ Transfer Into
OBit .. Zero
00 Byte" Zero
·
~
~
·• • ·
• • •
· •
R
S
S
~
~
~
CONDITION CODE SYMBOLS
H Half-carry from bit 3
I Interrupt mask
N Negative (sign bit)
Z Zero (byte)
V Overflow, 2's complement
C Carry/Borrow from MSB
R Reset Always
S Set Always
~ Affected
• Not Affected
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
745
HD68P01V07,HD68P01 V07-1 ,HD68P01 MO,HD68P01 M-1
Table 13 Instruction Execution Times in E·Cycles
Addressing Mode
Addressing Mode
a
:c
III
746
-c
CII
.E
is
•
•2
•
•3
•
•4
•
•4
2
4
2
3
5
4
6
4
6
4
6
4
6
•6
•6
•
•
•
•
•
•
•4
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•6
E
ABA
ABX
ADC
ADD
ADDD
AND
ASl
ASlD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BHS
BIT
BlE
BlO
BlS
BlT
BMI
BNE
BPl
BRA
BRN
BSR
BVC
BVS
CBA
ClC
CLI
ClR
ClV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS
-c
CII
-c
c::
l!l
x
w
CII
•
•
•
•
•
•
•
•
•
•2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•2
•4
•
•
•
•2
•
•
t)
~
3
•
•
•
•
•
•
•
•
•
•3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•3
•5
•
•
•
•3
•
•
•
•
•
•
•
•
•4
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•6
•4
6
6
x
CII
a.
a;
.E
a:
2
3
•
•
•
•
•
•
•
•
•4
6
6
•6
•
•4
6
6
•
•
•
•
•
•
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•2
2
2
•2
•
2
•2
•3
3
•
•3
•3
3
3
3
3
3
3
•3
3
3
3
3
3
3
3
3
6
3
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
E
~
CII
C1I
-c
...
C1I
CII
>
'+=0
.:
•6
•
•4
•
-c
,!!!
a
:c
INX
JMP
JSR
LOA
LDD
LOS
LOX
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STO
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI
U
i-c
c::
ax
-c
CII
x
CII
-c
-c
,!!!
a.
CII
>
'+=0
III
a;
.E
is
w
.:
.E
a:
•
•
•2
•
•3
•3
3
3
4
4
4
6
4
5
5
5
6
6
4
5
5
5
6
•
•
•
•
•
•
•
•
•
3
3
3
•
•
•
•
•
2
•
•
•
•
•
•
•
•
•2
•
•
•
•
•
•
•2
4
•
•
•
•
•
•
•
•
•
•5
•
•
•
•
•3
•
•
•
•
•
•
•
•
•3
•
•
•
•
•
•
•
•
•
•
•
3
4
4
4
3
5
•
•
•6
•
•
•
•6
•
•6
•
4
•
•
•
•6
6
6
•
•
•4
•
•
•
•
•
•4
•
•
•
•
•6
•
•
•
•
•
•
•6
•
•
•
4
•
4
5
5
5
4
6
•
•
•
•
4
5
5
5
4
6
•
•
•
•
•
•
•3
10
•2
•
•4
•5
•
•
10
5
2
•2
2
2
•
•
•
•
•
•12
2
2
2
2
•3
3
9
~HITACHI
Hitachi America Ltd, • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
----------------HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-1
• SUMMARY OF CYCLE BY CYCLE OPERATION
Table 14 provides a detailed description of the information
present on the Address Bus, Data Bus, and the Read/Write
(R/W) line during each cycle of each instruction.
The information is useful in comparing actual with expected
results during debug to both software and hardware as the
program is executed. The information is categorized in groups
according to addressing mode and number of cycles per instruc-
tion. In general, instructions with the same addressing mode
and number of cycles execute in the same manner. Exceptions
are indicated in the table.
Note that during MeV reads of internal locations, the resultant value will not appear on the external Data Bus except in
Mode o. "High order" byte refers to the most Significant byte
ofa 16-bitvalue.
Table 14 Cycle by Cycle Operation
Address Mode &
Instructions
Address Bus
Data Bus
IMMEDIATE
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
2
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Operand Data
LOS
LOX
LDD
3
1
2
3
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
CPX
SUBD
ADDD
4
2
3
Op Code Address
Op Code Address + ,
Op Code Address + 2
Address Bus F F F F
,
4
DIRECT
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
STA
3
,
2
3
3
,
2
3
LOS
LOX
LDD
4
STS·
STX
STD
4
,
2
3
4
,
2
3
,
4
CPX
SUBD
AoDD
5
2
3
4
5
JSR
5
1
2
3
4
5
Op Code Address
Op Code Address + ,
Address of Operand
Op Code Address
Op Code Address + ,
Destination Address
Op Code Address
Op Code Address + ,
Address of Operand
Operand Address + ,
,
,,
,,
,,,
,,
,,,
,
,,
,
0
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code
Address of Operand
Operand Data
Op Code
Destination Address
Data from Accumulator
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + ,
Address of Operand
Address of Operand + ,
0
0
Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)
Op Code Address
Op Code Address + ,
Operand Address
Operand Address + 1
Address Bus F F F F
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand olta (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stick Pointer + 1
1
1
1
0
0
Op Code
Irrelevlnt Oltl
First Subroutine Op Code
Return Addr... (Low Order Byte)
Return Addr... (High Order Byte)
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
747
HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-1 - - - - - - - - - - - - - - - Table 14 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
EXTENDED
3
JMP
1
2
3
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
4
3
4
4
STA
1
2
1
2
3
4
LOS
LDX
LDD
5
STS
STX
STD
5
ASL
ASR
CLR
COM
DEC
INC
1
2
3
4
5
1
2
3
4
5
lSR
6
NEG
3
4
5
6
ROL
ROR
TST*
CPX
SUBD
ADDD
1
2
6
1
2
3
4
5
6
JSR
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)
Op Code Address
Op Code Address + 1
9p Code Address + 2
Address of Operand
1
1
1
1
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data
Op Code
Op Code
Op Code
Operand
1
1
1
0
Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
0
0
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address Bus F F F F
Address of Operand
1
1
1
1
1
0
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus F F F F
1
1
1
1
1
1
Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
0
Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Address
Address + 1
Address + 2
Destination Address
0
• In the TST instruction, the line condition of the sixth cycle does the following: R/Vii = "High", AB = FFFF, DB = Low Byte of Reset Vector.
(Continued)
748
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-1
Table 14 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
INDEXED
3
1
2
3
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Offset
Low Byte of Restart Vector
4
1
2
3
4
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data
STA
4
1
2
3
4
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
1
1
1
0
Op Code
Offset
Low Byte of Restart Vector
Operand Data
LOS
LOX
LDD
5
1
2
5
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
1
2
3
4
5
Op Code Add ress
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Index Register ~Ius Offset + 1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Address Bus F F F F
Index Register Plus Offset
0
Op Code
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data
6
1
2
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Index Register + Offset + 1
Address Bus F F F F
1
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Stack Pointer
Stack Pointer - 1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
JMP
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
3
4
5
STS
STX
STD
ASL
ASR
CLR
COM
DEC
INC
LSR
NEG
ROL
ROR
TST *
CPX
SUBD
ADDD
3
4
5
6
JSR
6
1
2
3
4
5
6
0
0
1
1
1
1
1
0
0
• In the TST instruction, the line condition of the sixth cycle does the following: R/VV = "High", AB = FFFF, DB = Low Byte of Reset Vector.
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
749
HD68P01 V07,H D68P01 V07-1 ,HD68P01 MO,H D68P01 M-1 - - - - - - - - - - - - Table 14 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Data Bus
Address Bus
IMPLIED
ABA
ASl
ASR
CBA
CLC
Cli
CLR
ClV
COM
DAA
DEC
INC
lSR
NEG
NOP
ROL
ROR
SBA
ABX
SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Op Code of Next Instruction
Op Code Address
Op Code Address + 1
Address Bus F F F F
1
1
1
Op Code
Irrelevant Data
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Irrelevant Data
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Previous Register Contents
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code Address
Op Code Address + 1
Address Bus F F F F
1
1
1
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Stack Pointer
1
1
0
Op Code
Op Code of Next Instruction
Accumulator Data
Op Code Address
Op Code Address + 1
Stack Pointer
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code Address
Op Code Address + 1
Address Bus F F F F
1
1
1
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Operand Data from Stack
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
0
Op Code
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte)
3
4
5
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer"
Stack Pointer + 1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
1
1
1
1
1
5
Stack Pointer + 2
1
1
2
3
1
2
3
ASLD
lSRD
3
DES
INS
3
INX
DEX
3
PSHA
PSHB
3
TSX
3
TXS
3
PULA
PULB
4
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
4
PSHX
4
1
2
3
4
PUlX
RTS
5
5
1
2
0
Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
Op Code
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(High Order Byte)
Address of Next Instruction
(Low Order Byte)
(Continued)
750
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD68P01V07,HD68P01V07-1 ,HD68POl MO,HD68POl M-l
Table 14 Cycle by Cycle Operation (Continued)
Address Mode &
Instruction
WAI
**
Cycles
9
Cycle
#
Address Bus
R/W
Line
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Sta<;k Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
1
1
0
0
0
0
0
0
0
Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
10
Op Code Address
Op Code Address + 1
Address Bus F F F F
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus F F F F
1
1
1
1
1
1
1
1
1
1
Op Code
Irrelevant
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
5
Stack Pointer + 2
1
6
Stack Pointer + 3
1
7
Stack Pointer + 4
1
8
Stack Pointer + 5
1
9
Stack Pointer + 6
1
10
Stack Pointer + 7
1
Op Code
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instruction Address from
Stack (Low Order Byte)
10
11
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Stack Pointer - 7
Vector Address FFFA (Hex)
1
1
0
0
0
0
0
0
0
1
1
12
Vector Address FFFB (Hex)
1
1
2
3
4
5
6
7
8
9
MUL
10
1
2
3
4
5
6
7
8
9
RTI
SWI
10
12
1
2
3
4
5
6
7
8
9
Data Bus
Data
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Op Code
Irrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)
•• While the MCU is in the "Wait" state, its bus state will appear as a series of the MCU reads of an address which is seven locations
less than the original contents of the Stack Pointer. Contrary to the HD6800, none of the ports are driven to the high impedance
state by a WAI instruction.
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
751
HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-1 - - - - - - - - - - - - - - - Table 14 Cycle by Cycle Operation (Continued)
Address Mode &
Instruction
Address Bus
Data Bus
RELATIVE
BCC
BCS
BEQ
BGE
BGT
3
BHT BNE
BlE BPl
BlS BRA BRN
BlT BVC
BMT BVS
1
2
3
6
BSR
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Branch Offset
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
Op Code
Branch Offset
Low Byte of Restart Vector
Op Code of Next Instruction
Return Address (low Order Byte)
Return Address (High Order Byte)
a
a
When the op codes (4E, SE) are used to execute, the MCU
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the
LSI.
•
SUMMARY OF UNDEFINED INSTRUCTIONS OPERA·
TION
The MeU has 36 undefined instructions. When these are
carried out, the contents of Register and Memory in MCU
change at random.
Table 15 Op Codes Map
HD68POl MICROCOMPUTER INSTRUCTIONS
OP
CODE
ACC
A
~
LO
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
6
0110
0000
0001 0010
0110
0111
4
5
6
7
2
3
-----
BRA
TSX
CBA
BRN
INS
-----
LSRD (+1)
BHI PULA (+1)
BLS PULB (+1)
/
BCC
DES
ASLD (+1)
,/
BCS
TXS
TAP
TAB
BNE
PSHA
PSHB
0111
7
TPA
TBA
BEC
1000
8
INX (+1)
,/"
BVC PULX (+2)
1001
9
DEX (+1)
DAA
BVS
RTS (+2)
1010
A
CLV
/
BPL
ABX
1011
B
SEV
BMI
RTI (+7)
1100
C
CLC
1101
D
SEC
1110
E
CLI
1111
F
SEI
BYTE/CYCLE
1/2
ABA
/
BGE PSHX (+1)
V
/
/
1/2
------0101
1
-=-------
EXT
0100
SBA
/
/
IND
0011
0
NOP
ACC
B
BLT
MUL (+7)
BGT
WAI (+6)
BLE
SWI (+9)
2/3
1/3
ACCA or SP
IMM
1000 /1001 /1010 /1011
1100 /1101 /1110 /1111
I
8
9
I
Al
B
C
SBC
I
SUBD (+2)
LSR
AND
ROR
LDA
---
D
I
E
I
0
1
.
2
:
ADDD (+2)
BIT
~I
~/
STA
ASL
STA
3
4
5
6
7
S
EOR
ROL
ADC
9
DEC
ORA
A
- .. ---
I
JMP (-3)
.
• (+1
CLR
2/6
I
3/6
LDD (+1)
CPX (+2)
C
JSR (+2)
C (+11J
D
LDS (+1)
I
LDX(+1)
E
I-I
.
STD (+1)
I
I
STS (+1)
• (+11/
STX (+1)
F
BSR
(+4)
TST
1/2
B
ADD
INC
2/2
I 2/3 I 2/4 I 3/4
2/2
1 2/3 1 2/4 1 3/4
(NOTES) 1. Undefined Op codes are marked with ~.
2. (
) indicate that the nlumber in parenthesis must be added to the cycle count for that instruction.
3. The instructions shown below are all 3 bytes and are marked with ......
Immediate addressing mode of SUBD, CPX, LDS, ADDD, LDD and LDX instructions, and undefined op codes
(SF, CD, CFl.
4. The Op codes (4E, 5E) are 1 byte/~ cycles instructions, and are marked with .......
752
F
CMP
COM
ASR
I
liND I EXT
SUB
NEG
1/2
ACCB or X
1 DIR
IMM I DIR I INDI EXT
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave . • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-1
•
PRECAUTIONS WHEN EMULATING
THE HD6801 FAMILY
The HD68P01 series has 8k-byte EPROM space internally in
location $EOOO to $FFFF. Note the following when emulating
the HD6801S0 (2k-byte ROM on-chip) and the HD6801VO
(4k-byte ROM on-chip) with the HD68P01 series.
(Note 1) In Table 16, the following addresses are external like the ROM
on-chip type:
$FFFO to $FFFF in Mode 1
$FFFE and $FFFF (reset vector) just after releasing reset in
Mode 0
(Note 2) In Mode 0, data will not appear at Port 3 if accessing the
EPROM addresses. It is different from the ROM on-chip type.
1) Mode 0, 1,6
Table 16 shows the address which may be used for the internal ROM space.
2) Mode 5, 7
Table 18 shows the addresses which may be used for the
internal ROM space without any limitations.
Table 18
Table 16
HD6801SO
$F800 to $FFFF (2k bytes)
HD6801S0
$F800 to $FFFF (2k bytes)
HD6801VO
$FOOO to $FFFF (4k bytes)
HD6801VO
$FOOO to $FFFF (4k bytes)
Mode 0, 1 and 6 are expanded modes. When emulating the
HD6801S0 and the HD6801VO, the addresses shown in Table
17 should not be used externally because they are the internal
space in the EPROM on the package type. (See Fig. 26)
3) Mode 2,3,4
In these modes, the internal ROM is disable. The EPROM
on the package type may be used equivalently as the ROM onchip type.
Table 17
HD6801S0
$EOOO to $F7FF (6k bytes)
HD6801VO
$EOOO to $EFFF (4k bytes)
(Example)
IROM On-chip Type I
I EPROM on the Package Type I
External
Memory Space
(Internal Addresses)
®
4k·Byte EPROM Space
$F7F
$F800
Internal
Addresses
}
Figure 26
Internal Addresses
Corresponding to the
ROM On-chip Type
Memory Map Example when Emulating the HD6801S0
with the HD68P01 MO and the 4k ·Byte EPROM
Figure 26 shows an address map example when emulating the
HD6801S0 with the HD68P01MO and the 4k-byte EPROM in
mode 0, 1 and 6. In the emulation of expanded modes, the
addresses for memories and peripherals may be used externally
in space A, but not in space Band C which are internal ad-
dresses in the EPROM on the package type.
Figure 27 and 28 show the memory maps when emulating
the HD6801S0 and HD680lVO with the EPROM on the pack·
age type and the EPROM.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
753
H068P01V07,H068P01V07-1,H068P01MO,H068P01M-1 - - - - - - - - - - - - - - EPROM on the Package Type
H D68P01 V07/-1
EPROM
HN482732A
MCU
Address
Memory Map
lC!]
External
Address
ir------,
@
:
~
_____
~
EPROM
Address
HD68P01MO/-1
HN482732A
MCU
Address
EPROM
Address
MCU
Address
l
$ELC!J
$EOOO
HN482764
EPROM
Address
!
®
$ECIO(l:::::::::j $0000
I
Unusable
1";::::::::::;::;:1
Address
:i!iUffi!!Uiii
$FO()OCT9 $000
'$7FF
$800
$17FF
$1800
$FFF
$1FFF
Internal
ROM Address
Figure 27 Memory Map When Emulating the HD6801S0
EPROM on the Package Type
EPROM
HN482732A
EPROM
Address
MCU
Address
Memory Map
External
Address
+~
$EOOO
}
ir-------~
@
:
i. -- - - -. ~
1"'::,::::::::::'::1
HH(t)iHH
HD68P01MO/-1
HD68P01V07/-1
HN482732A
EPROM
Address
MCU
Address
~[!]
HN482764
MCU
Address
~
$EOOOI
I
I
EPROM
Address
~
®
$0000
I
I
I
Unusable
Address
@
:@
$FOOO
$000
$FFFF
$FFF
$EFFF
$FOOO
Internal
ROM Address
Figure 28 Memory Map When Emulating the HD6801VO
754
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
$1FFF
- - - - - - - - - - - - - - - - HD68P01V07,HD68P01V07-1,HD68P01MO,HD68P01M-1
PRECAUTION TO USE EPROM ON THE PACKAGE 8-BIT
SINGLE-CHIP MICROCOMPUTER
As this microcomputer takes a special packaging type with
pin sockets on its surface, pay attention to the followings;
(1) Do not apply higher electro-static voltage or serge voltage
etc_ than maximum rating, or it may cause permanent
damage to the device.
(2) There are 28 pin sockets on its surface. When using 32k
Table 19 Status Flag Reset Conditions
•
Let the index-side four pins open.
When using 24 pin EPROM. match
its index and insert it into lower
24 pin sockets.
ICF
Flag Reset
Condition 1
(Status Register)
When each flag is
OCF
"1"
Status
Flag
f---
TIMER
f---
SCI
TOF
TRCSR/Read
RDRF
When each flag is
-ORFE
-TDRE
Flag Reset Condition 2
(Data Register)
"1"
TRCSR/Read
ICR/Read
OCR/Write
TC/Read
RDR/
Read
TDR/Write
EPROM (24 pins), let the index-side four pins open.
(3) When assembling this LSI into user's system products as
well as the mask ROM type 8-bit single-chip microcomputer, pay attention to the followings to keep the good ohmic
contact between EPROM pins and pin sockets.
(a). When soldering on a printed circuit board, etc., keep its
condition under 250°C within 10 seconds. Over-time/
temperature may cause the bonding solder 'of socket
pins to meet and the sockets may drop.
(b) Keep out detergent or coater from the pin sockets at
aft-solder flux removal or board coating. The flux or
coater may make pin socket contactivity worse.
(c) Avoid the permanent use of this LSI under the evervibratory place and system.
(d) Repeating insertion/removal of EPROMs may damage
the contactivity of the pin sockets, so it is recommended to assemble new ones to your system products.
(4) In order to perform the normal operation at 1.25 MHz, it
is recommended to use the EPROM whose access time is
less than 300 ns.
Ask our sales agent about anything unclear.
•
PRECAUTION FOR HD68P01 FAMILY
SCI, TIMER STATUS FLAGS
The flags shown in Table 19 are cleared by read/write (flag
reset condition 2) the data register corresponding to each flag
after reading the status register (flag reset condition I). To
clear the flag correctly, take the following procedure:
I. Read the status register
2. Test the flag
3. Read/Write the data register
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • /(408) 435-8300
755
HD68P05V07,HD68P05MOi_MCU(Microcomputer Unit)
The HD68POS is the 8-bit Microcomputer Unit (MCU) which
contains a CPU, on-chip clock, RAM, I/O and timer. It is designed for the user who needs an economical microcomputer with
the proven capabilities of the HD6800-based instruction set.
Setting EPROM on the package, this MCU has the equivalent
function as the HD680SU and HD680SV.
•
•
•
•
•
•
HARDWARE FEATURES
8-Bit Architecture
96 Bytes of RAM
Memory Mapped I/O
Internal 8-Bit Timer with 7-Bit Prescaler
Vectored Interrupts - External, Timer and Software
• 24 I/O Ports + 8 Input Port
(8 Lines Directly Drive LEOs; 7 Bits Comparator Inputs)
• On-Chip Clock Circuit
• Master Reset
• Easy for System Development and debugging
• 5 Vdc Single Supply
•
PIN ARRANGEMENT
HD68P05V07
• SOFTWARE FEATURES
• Similar to HD6800
• Byte Efficient Instruction Set
• Easy to Program
• True Bit Manipulation
• Bit Test and Branch Instructions
• Versatile Interrupt Function
• Powerful Indexed Addressing for Tables
• Full Set of Conditional Branches
• Memory Usable as Registers/Flags
• Single Instruction Memory Examine/Change
• 10 Powerful Addressing Modes
•
•
All Addressing Modes Apply to ROM, RAM and liD
Compatible Instruction Set with HD6805
Note) EPROM is not attached to the MCU,
•
TYPE OF PRODUCTS
HD68P05MO
Type No.
Bus Timing
HD68P05V07
1 MHz
HN482732A·30
HD68P05MO
1 MHz
HN482764·3
EPROM Type No.
(Top View)
756
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H D68P05V07,HD68P05MO
•
BLOCK DIAGRAM
TIMER
Port B
I/O Lines
Accumulator
Port A
I/O lines
A
8
Index
Register
A.
PortA
Reg
Condition
Code
Register
Data
Dir
Reg
'5
CPU Control
X
cc
Data
Dir
Reg
CPU
Port C
I/O Lines
Stack
Pointer
SP
Program
Counter
"High" PCH
Program
Counter
"Low" PCL
Port B
Reg
ALU
Data
Dir
Reg
Data
Input
Port C
Reg
Port D
Input lines
Buffer
•
Port D
Reg
Address
Output lines
•
EPROM
HN482732AJ
[ HN482764
~~:~I
ADR,
ADR,
ADR'I
ADR,.
Address
Output 1 - - - - - 4 t - - - - - - - - - l
Buffer
:g:,.
'I
I
•
Address
Output Lines
Address
Output
Buffer
I
•
I
L
_______________ II
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
757
HD68P05V07,HD68P05MO---------------------------------------------------• ABSOLUTE MAXIMUM RATINGS
Item
Vee *
Input Voltage (EXCEPT TIMER)
Yin *
Input Voltage (TIMER)
Operating Temperature
T opr
T stg
Storage Temperature
•
V
-0.3-+7.0
V
-0.3 - +12.0
V
o -+70
°c
- 55 - +150
°c
Permanent LSI damage may occur if maximum rating~ are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (VCC=5.25V ± 0.5V, VSS=GND, Ta=0-+10°C, unless otherwise noted.)
Item
Symbol
Test Condition
RES
Input "High" Voltage
INT
Input "Low" Voltage
typ
max
-
Vee
V
Vee
V
Unit
-0.3
-
Vee
0.8
V
RES
INT
-0.3
-
0.8
V
-0.3
-
0.6
V
-0.3
-
0.8
V
-
-
700
mW
-
-
4.75
2.0
XTAL (Crystal Mode)
V IL
All Other
Power Dissipation
PD
Low Voltage Recover
LVR
-20
TIMER
Input Leak Current
min
4.0
3.0
V IH
All Other
INT
IlL
V in =0.4 V-V cc
XTAL (Crystal Mode)
•
Unit
-0.3- +7.0
With respect to Vss (SYSTEM GND)
(NOTE)
•
•
Value
Symbol
Supply Voltage
-
-50
-1200
V
V
20
p.A
50
p.A
0
p.A
Unit
AC CHARACTERISTICS (VCC=5.25V ± 0.5V, VSS=GND, Ta=0-+70°C, unless otherwise noted.)
min
typ
max
Clock frequency
Item
fcl
0.4
4.0
MHz
Cycle Time
tcyc
1.0
-
10
p.s
INT Pulse Width
t lWL
t cvc +
250
-
-
ns
RES Pulse Width
t RWL
t cvc +
250
-
-
ns
TIMER Pulse Width
t TWL
t cvc +
250
-
-
ns
Oscillation Start·up Time (Crystal Mode)
tosc
CL =22pF±20%,
Rs=60n max.
-
-
100
ms
Delay Time Reset
tRHL
Ex ternal Cap. = 2. 2p. F
100
-
-
ms
Vin=OV
-
-
35
pF
10
pF
Input Capacitance
I
I
EXTAL
All Other
Symbol
Cin
Test Condition
~HITACHI
758
Hitachi America
Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - HD68P05V07,HD68P05MO
• PORT ELECTRICAL CHARACTERISTICS (Vee
= S.2SV ± O.SV, Vss = GNO, Ta = 0 -- +70°C, unless otherwise noted.)
Symbol
Item
Port
VOH
B
Port C
Input "High" Voltage
Input "Low" Voltage
Input Leak Current
Port
VOL
B
Port A,
and 0*
Input "Low" Voltage
..
V
IOH = -100 lolA
2.4
IOH = -200 lolA
2.4
-
IOH = -1 mA
1.S
-
IOH = -100 lolA
2.4
-
-
-
0.4
V
-
0.4
V
1.0
V
Vee
V
-
IOL = 10mA
Yin = O.SV
-Soo
-
Yin = 2V
-300
Yin = O.4V -- Vee
-
VIH
B, C.
2.0
-0.3
VIL
Port A
IlL
Port 0**
Port 0**
(Do"" 0 6 )
20
V
V
V
V
O.S
V
-
lolA
-
-
lolA
-
20
lolA
-
VTH+0.2
-
V
V IL
-
VTwO.2
-
V
VTH
0
-
O.SxVee
V
V IH
(Do"" 0 6 )
Port 0**(0,)
Threshold Voltage
Unit
-
~=3.2mA
Port B. C,
and 0
Input "High" Voltage
max
-
~_=1.6mA
Port A and C
Output "Low" Voltage
typ
3.S
Test Condition
Port A
Output "High" Voltage
min
IOH =-10IoLA
* Port 0 as digital Input
**
Port 0 as analog input
TTL Equiv. (Port A and C)
TTL Equiv. (Port B)
Vee
Vee
2.4kH
1.2kn
Ii
Test Point
= 3.2 rnA
Test
Ii = 1.6 rnA
POIOt
Vi
Vi
40 pF
(NOTE)
30 pF
12 kn
24 k!2
1. Load capacitance includes the floating capacitance of tt,e? probe and the jig etc.
2. All diodes are 152074 @or equivalent.
Figure 1 Bus Timing Test Loads
•
inputs,
SIGNAL DESCRIPTION
The input and output signals for the MCV, shown in PIN
ARRANGEMENT, are described in the following paragraphs.
•
Vee and Vss
•
INT
Power is supplied to the MCV using these two pins. Vee
is +S.2SV ±O.5V. V ss is the ground connection.
This pin provides the capability for asynchronously applying
an external interrupt to the MCV. Refer to INTERRUPTS
for additional information.
•
•
TIMER
This pin allows an external input to be used to decrement
the internal timer circuitry. Refer to TIMER for additional
information C!bout the timer circuitry.
•
RES
This pin allows resetting of the MCV. Refer to RESETS
for additional information.
XTAL and EXTAL
These pins provide connections for the on-chip clock circuit.
A crystal (AT cut, 4 MHz maximum) can be connected to these
pins to provide a system clock with various stability. Refer to
INTERNAL OSCILLATOR for recommendations about these
•
NUM
This pin is not for user application and should be connected
to VSS.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave . • San Jose, CA 95131 • (408) 435-8300
759
HD68P05V07,HD68P05MO--------------------------------------------------•
InpUt/Output Lines (Ao - A" Bo - B7 , Co - C 7 )
These 24 lines are arranged into three 8-bit ports (A, Band
C). All lines are programmable as either inputs or outputs under
software control of the Data Direction Register (DDR). Refer to
INPUT/OUTPUT for additional information.
•
Input Lines (Do - 0 7 )
These are 80bit input lines, which has two functions. Firstly,
these are TIL compatible inputs, in location $003. The other
func,tion of them is 7 bits comparator in location $007. Refer to
INPUT for more detail.
•
REGISTERS
The MCU has five registers available to the programmer.
They are shown in Figure 2 and are explained in the following
paragraphs,
L...-_ _ _ _ _~I
Accumulator
°
~llndex
"L-_ _ _ _ _ _pc____---J1°
L...-_ _ _ _ _
Register
Program Counter
I D..,II_o-'l_o....l_o-'l_o.....I_,. I_,
. ....I___sp_---J1°
"
5 4
L
~
I
Figure 2
Stack Pointer
N
Z
C
Condition Code Register
Carry/Borrow
Zero
Negative
• Stack Pointer (SP)
The stack pointer is a 13-bit register that contains the address
of the next free location on the stack. Initially, the stack pointer is set to location $007F and is decremented as data is being
pushed onto the stack and incremented as data is being pulled
from the stack. The six most significant bits of the stack pointer
are permanently set to 00000011. During an MCU reset or the
reset stack pointer (RSP) instruction, the stack pointer is set
to location $007F. Subroutines and interrupts may be nested
down to location $0061 which allows the programmer to use up
to 15 levels of subroutine callS:
• Condition Code Register (CC)
The condition code register is a S-bit register in which each
bit is used to indicate or flag the r~sults of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each individual condition code register bit is explained in the following
paragraphs.
Half Carry (H)
Used during arithmetic operations (ADD and ADC) to
indicate that a carry occurred between bits 3 and 4.
Interrupt (I)
This bit is set to mask the timer and external interrupt (iNT) •.
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.
Negative (N)
Used to indicate that the result of the last arithmetic, logical
or data manipulation was negative (bit 7 in result equal to a
logical one).
Zero (Z)
Interrupt Malk
Halt Carry
Programming Model
• Accumulator (A)
The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.
• Index Register (X)
The index register is an 80bit register used for the indexed
addressing mode. It contains an 8-bit address that may be added
to an offset value to create an effective address. The index
register can also be used for limited calculations and data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
• Program Counter (PC)
The program counter is a 13-bit register that contains the
address of the next instruction to be executed.
Used to indicate that the result of the last arithmetic, logical
or data manipulation was zero.
Carry/Borrow (C)
Used to indicate that a carry or borrow out of the arithmetic
logic unit (ALU) occurred during the last arithmetic operation.
This bit is also affected during bit test and branch instructions,
shifts. and rotates.
• TIMER
The MCU timer circuitry is shown in Figure 3. The 8-bit
counter, the Timer Data Register (TDR), is loaded under program control and counts down toward zero as soon as the clock
input is applied. When the timer reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register (TCR) is
set. The MCV responds to this interrpt by saving the present
CPU state on the stack, fetching the timer interrupt vector from
locations $OFF8 and $OFF9 and executing the interrupt rou·
tine. The timer interrupt can be masked by setting the timer
TIMER Input Pin
TCR bit 4
Timer Control Register
(TCR)
11>2 (lnternall-----\"-......
TCR bit 5
Prescaler
} Address Bits
Clock Input
a·bit Counter
Timer Data Register (TOR)
Timer Interrupt Req.
Timer Interrupt Mask
Clock Input
} Source Option
Figure 3
760
Hitachi America
Timer Block Diagram
~HITACHI
Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------HD68P05V07,HD68P05MO
interrupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in
the Condition Code Register also prevents a timer interrupt
from being processed.
The clock input to the timer can be from an external source
applied to the TIMER input pin or it can be the internal rjn
signal. When the rjn signal is used as the source, it can be gated
by an input applied to the TIMER input pin allowing the
user to easily perform pulse-width measurements. A prescaler
option can be applied to the clock input that extends the timing
interval up to a maximum of 128 counts before decrementing
the counter (TDR). The timer continues to count past zero,
falling through to $FF from zero and then continuing the
count. Thus, the counter (TDR) can be read at any time by
reading the TDR. This allows a program to determine the length
of time since a time interrupt has occurred and not disturb
the counting process.
The TDR is 8-bit read/write register in location $008. At
power-up or reset, the TDR and the prescaler are initialize with
all logical ones.
The timer interrupt request bit (bit 7 of the TCR) is set by
hardware when timer count reaches zero, and is cleared by program or by hardware reset. The bit 6 of the TCR is writable by
program. Both of those bits can be read by MPV.
The bit 5 and bit 4 of the TCR select a clock input source.
The selections are shown in Table 1. Bit 3 is not used. Bit 2, bil
1 and bit 0 are used to select the prescaler dividing ratio, shown
in Table 2. At reset, an internal clock by the TIMER input pin
is selected as clock source and "";- 1 mode" is selected as the
prescaler dividing ratio.
(NOTE) If the MCV Timer is not used, the TIMER input pin
must be grounded.
•
Vee
OV--------------J
RES Pin --------~
Internal
-----------------~
Reset
Figure 4
Timer Control
Part of
HD68P05
MCU
Figure
------Clock Input Source
Bit 5
Bit 4
0
0
0
1
0
1
1
1
¢2
Controlled by TIMER Input
(Note)
Power and RES Timing
2
Table 1 Selection of Clock Input Source
Register (TCR)
RESETS
The MCV can be reset two ways; by initial power-up and
by the external reset input (m), see Figure 4. All the I/O
ports are initialized to input mode (DDRs are cleared) during
reset.
During power-up, a minimum 100 milliseconds is needed
before allowing the RES input to go "High".
This time allows the internal crystal oscillator to stabilize.
Connecting a capacitor to the RES input, as shown in Figure
5, typically provides su fficient delay.
•
5
Power Up Reset Delay Circuit
INTERNAL OSCILLATOR
The internal oscillator circuit is designed to require a minimum of external components. The use of a crystal (AT cut,
4 MHz max) is sufficient to drive the internal oscillator with
various stability ~ The different connection methods are shown
in Figure 6. Crystal specifications are given in Figure 7.
Event Input from TIMER
(NOTE) 1. 0.0 and 1.0 are not usable In mask option of 6805
2. The TIMER input pin must be tied to Vee. for
uncontrolled q,2 clock.
6 XTAL
4 MHz c::J
max
EXTAL HD68P05
MCU
22pF' 20%
Table 2 Selection of Prescaler Dividing Ratio
Timer Control
T
Prescaler Dividing Ratio
Register (TCR)
Bit 2
8it 1
Bit 0
0
0
0
0
0
0
0
Prescaler ..;- 1
1
Prescaler -;- 2
1
1
0
Prescaler -;- 4
1
1
Prescaler -'- 8
0
0
0
Prescaler -;- 16
1
1
Prescaler -:- 32
1
1
0
Prescaler -'- 64
1
1
1
Prescaler -;- 128
6 XTAL
External
Clock
Inpul
~HITACHI
Figure 6
5 EXTAL
HD68P05
MCU
Internal Oscillator
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
761
HD68P05V07,HD68P05MO--------------------------------------------------onto the stack. This interrupt' bit (I) in the condition code register is set, the address of the interrupt routine is obtained from
the appropriate interrupt vector address, and the interrupt routine is executed. Stacking the CPU registers, setting the 1 bit,
and vector fetching requires 11 cycles. The interrupt service
routines normally end with a return from interrupt (RTI) instruction which allows the MCU to resume processing of the
program prior to the interrupt. Table 3 provides a listing of the
interrupts, their priority, and the vector address that contain the
starting address of the appropriate interrupt routine.
A flowchart of the interrupt processing sequence is given in
Fig. 9.
C,
XTAl~~EXTAl
~~
6
5
AT - Cut Parallel Hesonance Crvstal
Co = 7 pF max.
1= 4 MHz
RS = 60n max.
Figure 7 Crystal Parameters
•
6
INTERRUPTS
The MeV can be interrupted three different ways: through
the external interrupt (INT) input pin, the internal timer interrupt request, and a software interrupt instruction (SWI). When
any interrupt occurs, processing is suspended, the present CPU
state is pushed onto the stack in the order shown in Fig. 8, the
interrupt bit (I) in the Condition Code Register is set, the address of the interrupt routine is obtained from the appropriate
interrupt vector address, and the interrupt routine is executed.
Since the stack pointer decrements during pushes, the low order
byte (PCL) of the program counter is stacked first; then the
high order five bits (pCH) are stacked. This ensures that the program counter is loaded correctly as the stack pointer increments
when it pulls data from the stack. A subroutine call will canse
only the prqgram counter (pCH, PCL) contents to be pushed
n-4
1
5
1
4
11
0
Condition
Code Reg'ster
Pull
n+1
n-3
Accumulator
n+2
n-2
Index Register
n+3
1
n+4
n-1
1
1
11
PCW
PCl"
n+5
Push
" For subroutine calls, onlv PCH and PCl are stacked.
Figure 8
Table 3
Interrupt
Priority
1
Interrupt Priorities
Vector Address
HD6BP05V07
HD6BP05MO
$OFFE, $OFFF
$lFFE,$1FFF
2
$OFFC, $OFFD
$1 FFC, $1 FFD
3
$OFFA, $OFFB
$1 FFA, $1 FFB
4
$OFFB, $OFF9
$1 FFB, $1 FF9
SWI
TIMER
Interrupt Stacking Order
1-1
7F -sP
o ... DDR·s
ClR
TNT Logic
FF -+TOR
7F ... Pleseale.
50 _ TCR
$1 FFe, $1 FFO
$OFFA, $OFFB
SOFFB, $OFF9
$IFFA. $IFFB
$1 F Fa. $1 FF9
SWI
Figure 9 Interrupt Processing Flowchart
762
$HITACtU
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
•
INPUT/OUTPUT
There are 24 input/output pins. All pins are programmable
as either inputs or outputs under software control of the corresponding Data Direction Register (DDR). When programmed
as outputs, the latched output data is readable as input data,
regardless of the logic levels at the output pin due to output
loading (see Fig. 10). When Port B is programmed for outputs,
it is capable of sinking lOrnA on each pin (VOL = IV max).
All input/output lines are TTL compatible as both inputs and
outputs. Port A is CMOS compatible as outputs, and Port Band
C are CMOS compatible as inputs. Figure 11 provides some
examples of port connections.
Data
Direction
Register
Bit
---8
Output
State
Output
Data Bit
0
1
1
0
1
0
Figure 10
Input to
MCU
0
1
1
3·State
Pin
Typical Port I/O Circuitry
Port A
Port B
Port A Programmed as output(s), driving CMOS and TTL Load directly.
Port B Programmed as output(s), driving Darlington base directly.
(a)
(b)
+v
+v
R
R
Bo
CMOS Inverter
Port C
Port B
10 rnA max
C,
B,
Port B Programmed as output(s), driving LED(s) directly.
(e)
Port C Programmed as output(s), driving CMOS loads, using external
pull·up resistors.
(d)
Figure 11 Typical Port Connections
•
INPUT
Port D can be used as either 8 TTL compatible inputs or I
threshold input and 7 analog inputs pins. Fig. 12 (a) shows the
construction of port D. The Port D register at location S003
stores TTL compatible inputs, and those in location S007 store
the result of comparison Do to D6 inputs with D7 threshold
input. Port D has not only the conventional function as inputs
but also voltage-comparison function. Applying the latter, can
easily check that 7 analog input electric potential max. exceeds
the limit with the construction shown in Fig. 12 (b). Also, using
one output pin of MCU, after external capacity is discharged
at the preset state, charge the CR circuit of long enough time
constant. apply the charging curve to the 07 pin. The construction described above is shown in Fig. 12 (c). The compared
result of Do to 06 is regularly monitored, which gives the
analog input electric potential applied to Do to 06 pins from
inverted time. This method enables 7 inputs to be converted
from analog to digital. Furthermore. combination of two functions gives 3 level voltages from Do to D6, Fig. 12 <1Lprovides
the example when V TH is set to 3.5V .
•
BIT MANIPULATION
The MCU has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to haye individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 13
illustrates the usefulness of the bit manipulation and test
instructions. Assume that bit a of port A is connecte'd to a zero
crossing detector circuit and that bit 1 of port A is connected to
the trigger ofa TRIAC which power the controlled hardware.
This program, which uses only seven ROM locations, .provides turn-on of the TRIAC within 14 microseconds of the zero
crossing. The timer could also be Incorporated to provide twnon at some later time which would permll pulse·width modulation of the controlled power.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
763
HD68P05V07,HD68P05MO--------------------------------------------------$003 Read
Input Port
(00- 0 6 )
Internal Bus
(BitO - BitS)
$003 Read
Input Port (0,)
Internal Bus
(Bit 7)
(a) The logic configuration of Port 0
~
Port
..
Co
C
0
1-....;'_ _ _ Reference Level
0
t -..:..'- - Analog Input 6
0,
Port
o
Port
o
Do
D.
/-----Analoq Input 6
Do
1 - - - - - Analog Input 0
Analog Input 0
(el Application to AID convertor
(b) Seven analog inputs and a reference level input of Port 0
0,
VTH (; 3.5V)
d.
3 Levels Input S
Port
0
\
O.
Input
Voltage
($003)
($007)
OV - 0.8V
0
0
2.0V - 3.3V
1
0
3.7V - Vee
1
1
3 Levels Input 0
Id) Application to 3 levels input
Figure 12 Configuration and Application of Port 0
764
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - HD68P05V07,HD68P05MO
SELF 1
··
··
•
BRClR 0, PORT A, SELF 1
BSET 1, PORT A
BClR 1, PORT A
Figure 13 Bit Manipulation Example
•
ADDRESSING MODES
The MCV has ten addressing modes available for use by the
programmer. They are explained and illustrated briefly in the
following paragraphs.
• Immediate
Refer to Figure 14. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
• Direct
Refer to Figure 15. In direct addressing, the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, 1/0 registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.
• Extended
Refer to Figure 16. Extended addressing is used to referem:e
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instructions are three bytes long.
• Relative
Refer to Figure 17. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA=(pC)+2+Rel. Rei is the contents
of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to somewhere within the
range of +129 bytes to -127 of the present instruction. These
instructions are two bytes long.
• Indexed (No Offset)
Refer to Figure 18. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and their EA is the contents of the index register.
• Indexed (a-bit Offset)
Refer to Figure 19. The EA is calculated by adding the
contents of the byte fullowing the opcode to the contents of
the index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.
• Indexed (16-bit Offset)
Refer to Figure 20. This addressing mode calculates the fA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.
Bit Set/Clear
Refer to Figure 21. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.
• Bit Test and Branch
Refer to Figure 22. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
($OO-$FF) and branch to any location relative to the PC. The
byte to be tested is addressed by the byte following the opcode.
The individual bit within that byte to be tested is addressed by
the lower three bits of the opcode. The third byte is the relative
address to be added to the program counter if the branch condition is met. These instructions are three bytes long. The value of
the bit tested is written to the carry bit in the condition code
register.
• Implied
Refer to Figure 23. The implied mode of addressing has no
EA. All the information necessary to execute an instruction is
contained in the opcode. Direct operations on the accumulator
and the index register are included in this mode of addressing.
In addition, control instructions such as SWI, RTI belong to this
group. All implied addressing instructions are one byte long.
•
INSTRUCTION SET
The MCV has a set of 59 basic instructions. They can be
divided into five different types: register/memory, read/modify/
write. branch, bit manipulation, and control. The following
paragraphs briefly explain each type. All the instructions within
a given type are presented in individual tables.
• Register/Memory Instructions
Most of these instructions use two operands. One operand is
either the accumulator or the index register. The other operand
is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR)
instructions have no register operand. Refer to Table 4.
• Read/Modify/Write Instructions
These instructions read a memory location or a register,
modify or test its contents, and write the modified value back
to memory or to the register. The test for negative or zero
(TST) instruction is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
5.
• Branch Instructions
The branch instructions cause a branch from the program
when a certain condition is met. Refer to Table 6.
• Bit Manipulation Instructions
These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 7.
• Control Instructions
The control instructions control the MCU operations during
program execution. Refer to Table 8.
• Alphabetical Listing
The complete instruction set is given in alphabetical order in
Table 9.
• Opcode Map
Table lOis an opcode map for the instructions used on the
MCU.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
765
HD68P05V07,HD68P05MO---------------------------------------------------
Memory
i
I
I
I
I
~
A
F8
Index
e9
I
Stack Point
I
PROG LOA #$F8 058E
A6
Prog Count
F8
05CO
1-------1
058F
CC
I
I
§
I
I
I
Figure 14
t
lEA
[
Memory
I
I
I
I
i
I
I
I
I
I
I
I
CAT
FCB
32
LOA
CA T
1
0048
~
/
Adder
'"
A
ooto
20
0048
1
0520
86
052E
48
20
I
Stack Point
I
I
I
I
Prog Count
I
052F
CC
~
I
I
I
I
Figure 15 Direct Addressing Example
766
1
Index Reg
I
I
PROG
Immediate Addressing Example
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
I
- - - - - - - - - - - - - - - - - - - - - - - - - - HD68P05V07,HD68P05MO
Memory
I
I
I
@
PROG
CAT
LOA
FCB
CAT
64
0000
A
::~J-----'
06ES
I
I
I
I
40
Index Reg
Stack Point
Prog Count
40
040C
t-------t
CC
Figure 16 Extended Addressing Example
Memory
:
I
§
A
Index Reg
Stack Point
I
I
PROG
BEQ
PROG2
04A 7
04A8
0000
27
t-------I
18
§
I
I
Figure 17
Relative Addressing Example
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
767
H D68PQ5V07. H D68P05MO
Memory
A
TABL
FCC
t Lit 00B8
4C
4C
49
Index Reg
B8
I
PROG
LOA
I
Stack Point
05F4~
X
Prog Count
05F5
CC
§
Figure 18 Indexed (No Offset) Addressing Example
i
lEA
Memory
i
i
I
i
I
I
TABL
FCB
;rBF
0089
BF
FCB
#86
008A
86
FCB
",DB
008B
DB
FCB
;,CF
008C
CF
I
r
I
008C
t
/
Adder
~
A
J
I
I
r
I
I
I
CF
I
Index Reg
03
I
Stack Po,nt
PROG
LOA
TABL. X 075B
E6
075C
89
I
I
I
I
Prog Count
0750
CC
I
§
,I
Figure 19 Indexed (8-Bit Offset) Addressing Example
768
$
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
I
I
--------------------------~------------------------HD68P05V07.HD68P05MO
i
i
:
I
§
PROG
LOA TABl. X 0692
I
0780
I
Adder
A
I
I
~'
06
0693
0694
DB
I
07
7E
02
I
Stack Point
I
1--------'
I
Prog Count
I
0695
I
TABL
I
Index Reg
CC
I
I
I
FCB
#BF
077E
BF
FCB
#86
077F
86
FCB
FCB
#OB
#CF
0780 ~--O~B~-__1r------------------l
0781
CF
Figure 20 Indexed (16-Bit Offset) Addressing Example
Memory
PORT B EOU
BF
0001
A
0000
Index Reg
PROG BCLR 6. PORT B 058F
10
0590 t---01--~
Stack Point
Prog Count
0591
I
I
cc
~
I
I
I
I
Figure 21
Bit Set/Clear Addressing Example
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
769
HD68P05V07,HD68P05MO--------------------------------------------_______
PORT C
EOU
A
0002
2
Index Reg
Stack Point
PROG BRCLR 2. PORT C. PROG 2
0575
0574
05
t------~
02
0576
1D
I
Prog Count
0000
CC
T
I
~
.,
0594
~------------------------------------~
Figure 22 Bit Test and Branch Addressing Example
Memory
I
I
I
I
~
PROG
TAX
A
E5
05BA§
I
I
I
I
Index Reg
E5
Prog Count
05BB
CC
I
I
I
I
§
I
I
I
I
I,
Figure 23
770
Implied Addressing Example
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------HD68P05V07,HD68P05MO
Table 4
Register/Memory Instructions
Addressing Modes
~-
Function
Mnemonic
Immediate
Direct
Indexed
(No Offset)
Extended
Op
Op
#
Op
#
#
#
Code Bytes Cycles Code Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(S·Bit Offset)
#
Op
#
Bytes Cycles Code
Indexed
(16·Bit Offset)
#
Op
#
Bytes Cycles Code
#
#
Bytes Cycles
load A from Memory
LOA
A6
2
2
B6
2
4
C6
3
5
F6
1
4
E6
2
5
06
3
6
load X from Memory
LOX
AE
2
2
BE
2
4
CE
3
5
FE
1
4
EE
2
5
DE
3
6
Store A in Memory
STA
-
2
5
C7
3
6
F7
1
5
E7
2
6
07
3
7
STX
-
-
B7
Store X in Memory
-
BF
2
5
CF
3
6
FF
1
5
EF
2
6
OF
3
7
ADD
AB
2
2
BB
2
4
CB
3
5
FB
1
4
EB
2
5
DB
3
6
Add Memory and
Carry to A
AOC
A9
2
2
B9
2
4
C9
3
5
F9
1
4
E9
2
5
09
3
6
Subtract Memory
SUB
AD
2
2
BO
2
4
CO
3
5
FO
1
4
EO
2
5
DO
3
6
Subtract Memory from
A with Borrow
SBC
A2
2
2
B2
2
4
C2
3
5
F2
1
4
E2
2
5
02
3
6
6
Add
M~mory
to A
AND Memory to A
AND
A4
2
2
B4
2
4
C4
3
5
F4
1
4
E4
2
5
04
3
OR Memory with A
ORA
AA
2
2
BA
2
4
CA
3
5
FA
1
4
EA
2
5
OA
3
6
Exclusive OR Memory
with A
EOR
A8
2
2
B8
2
4
CII
3
5
F8
1
4
E8
2
5
08
3
6
Arithmetic Compare A
with Memory
CMP
Al
2
2
Bl
2
4
Cl
3
5
Fl
1
4
El
2
5
01
3
6
Arithmetic Compare X
with Memory
CPX
A3
2
2
B3
2
4
C3
3
5
F3
1
4
E3
2
5
03
3
6
Bit Test Memory with A
(logical Compare)
BIT
A5
2
2
85
2
4
C5
3
5
F5
1
4
E5
2
5
05
3
6
. Jump Unconditional
JMP
-
-
BC
2
3
CC
3
4
FC
1
3
EC
2
4
DC
3
5
Jump to Subroutine
JSR
-
-
-
BO
2
7
CD
3
8
FO
1
7
ED
2
8
DO
3
9
Table 5
Read/ModifylWrite Instructions
Addressing Modes
1--- - - - - - - r
Function
Implied (XI
Implied (AI
Mnemonic
Op
Code
Op
#
#
Bytes Cycles Code
Indexed
(No Offset I
Direct
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bvtes Cycles Code
#
#
Bytes Cycles
Increment
INC
4C
1
4
5C
1
4
3C
2
6
7C
1
6
6C
2
7
Decrement
DEC
4A
1
4
5A
1
4
3A
2
6
7A
1
6
6A
2
7
Clear
CLR
4F
1
4
5F
1
4
3F
2
6
7F
1
6
6F
2
7
Complement
COM
43
1
4
53
1
4
33
2
6
73
1
6
63
2
7
Negate
(2'$ Complement)
NEG
40
1
4
50
1
4
30
2
6
70
1
6
60
2
7
Rotate Left Thru Carry
ROL
49
1
4
59
1
4
39
2
6
79
1
6
69
2
7
Rotate Right Thru Carry
ROR
46
1
4
56
1
4
36
2
6
76
1
6
66
2
7
Logical Shift Left
LSL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
7
Logical Shift Right
LSR
44
1
4
54
1
4
34
2
6
74
1
6
64
2
Arithmetic Shift Right
ASR
47
1
4
57
1
4
37
2
6
77
1
6
67
2
7
Arithmetic Shift Left
ASL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
TST
40
1
4
50
1
4
3D
2
6
70
1
8
80
2
7
Test for Negative or
Z.O
_HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
771
HD68P05V07,HD68P05MO---------------------------------------------------Table 6 Branch Instructions
Relative Addressing Mode
Mnemonic
Function
#
#
Op
Code
Bytes
Cycles
Branch Always
BRA
20
2
4
Branch Never
BRN
21
2
4
Branch IF Higher
BHI
22
2
4
Branch I F lower or Same
BlS
23
2
4
Branch I F Carry Clear
BCC
24
2
4
(Branch IF Higher or Same)
(BHS)
24
2
4
Branch I F Carry Set
BCS
25
2
4
(Branch IF lower)
(BlO)
25
2
4
Branch I F Not Equal
BNE
26
2
4
Branch IF Equal
BEQ
27
2
4
Branch I F Half Carry Clear
BHCC
28
2
4
Branch I F Half Carry Set
BHCS
29
~
4
Branch I F Plus
BPl
2A
2
4
Branch IF Minus
BMI
2B
2
4
Branch I F Interrupt Mask Bit is Clear
BMC
2C
2
4
Branch IF Interrupt Mask Bit is Set
BMS
20
2
4
Branch IF Interrupt Line is low
Bil
2E
2
4
Branch IF Interrupt Line is High
BIH
2F
2
4
Branch to Subroutine
BSR
AO
2
8
Table 7 Bit Manipulation Instructions
Addressing Modes
Function
Bit Set/Clear
Mnemonic
Op
Code
Bit Test and Branch
#
#
Bytes
Cycles
Op
Code
-
Branch I F Bit n is set
BRSET n (n=O ..... 7)
-
-
Branch I F Bit n is clear
BRClR n (n=O ..... 7)
-
-
Se-t Bit n
BSET n (n=O ..... 7)
10+2-n
2
7
Clear bit n
BClR n (n=O ..... 7)
11+2-n
2
7
#
#
Bytes
Cycles
01+2-n
3
3
10
-
-
-
2-n
10
-
Table 8 Control Instructions
Implied
Function
772
Mnemonic
Op
Code
#
#
Bytes
Cycles
Transfer A to X
TAX
97
1
2
Transfer X to A
TXA
9F
1
2
Set Carry Bit
SEC
99
1
2
Clear Carry Bit
ClC
98
1
2
2
Set Interrupt Mask Bit
SEI
9B
1
Clear Interrupt Mask Bit
CLI
9A
1
2
Software Interrupt
SWI
83
1
11
Return from Subroutine
RTS
81
1
6
Return from Interrupt
RTI
80
1
9
Reset Stack Pointer
RSP
9C
1
2
No·Operation
NOP
90
1
2
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------HD68P05V07,HD68P05MO
Table 9 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
Direct
Extended
Relative
Indexed
Indexed
(No
(8 Bits)
Offset)
Condition Code
Indexed
(16 Bits)
Bit
Set/
Clear
Bit
Test &
Branch
H
I
N
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
•
1\
1\
1\
1\
1\
1\
1\
1\
•
ADC
x
x
x
x
x
x
1\
ADD
x
x
x
x
x
x
1\
AND
x
x
x
x
x
x
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ASL
x
x
x
x
ASR
x
x
x
x
x
BCC
x
BCLR
BCS
x
BEQ
x
BHCC
x
BHCS
x
BHI
x
x
x
BHS
BIH
x
BIL
x
BIT
x
x
x
BLO
x
BLS
x
BMC
BMI
x
x
BMS
x
BNE
x
BPL
x
BRA
x
BRN
x
x
x
BRCLR
x
BRSET
x
x
BSET
x
BSR
CLC
CLI
CLR
x
x
x
CMP
COM
INC
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
J$R
LDX
x
x
x
x
x
x
JMP
LDA
x
x
x
x
EOR
x
x
x
x
CPX
DEC
x
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
x
x
x
1\
1\
1\
1\
1\
•
•
•
•
•
•
•
• •
• •
• •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1\
1\
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• 1\
• 1\
• •
• •
• 0
• •
0
1
•
1\
1\
1\
1\
1\
1
1\
1\
1\
1\
1\
1\
1\
•
•
1\ •
• • •
• • •
1\ 1\ •
1\
1\
1\
•
(to be continued)
C
1\
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
773
HD68P05V07,HD68P05MO--------------------------------------------------Table 9 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
lSL
x
x
LSR
x
NEG
x
x
x
NOP
x
x
ORA
ROL
ROR
RSP
RT!
RTS
SEC
SEI
x
STX
x
SUB
TAX
TST
TXA
x
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
x
x
x
x
x
Bit
Set/
Clear
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Condition Code Svmbols:
H
Half Carry (From Bit 31
I
Interrupt Mask
N
Negative (Sign Bitl
Z
Zero
x
x
C
/\
•
?
Bit
Test &
Branch
I
N
• •
/\
/\
/\
0
/\
/\
/\
/\
/\
H
•
•
•
•
•
x
x
STA
SWI
x
Relative
x
x
x
x
x
x
x
SBC
774
Direct
Extended
x
•
•
•
•
•
•
•
?
•
•
•
1
•
•
•
Z
C
• • •
/\
/\
/\
/\
/\ /\
•
• •
•
?
?
?
•
•
•
/\ /\
•
•
• •
•
• •
/\ /\
•
/\
/\
•
/\ /\
•
• 1 • •
• • • •
• • /\ /\
• • • •
Carry {Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
•
/\
/\
•
?
•
/\
1
•
•
•
/\
•
•
•
•
------------------------------------------------------HD68P05V07,HD68P05MO
Table 10
Bit Manipulation
Test &
Set/
Branch
Clear
0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
0
BRSETO
BRClRO
BRSET1
BRClR1
BRSET2
BRClR2
BRSET3
BRClR3
BRSET4
BRClR4
BRSET5
BRClR5
BRSET6
BRClR6
BRSET7
BRClR7
3/10
(NOTE)
•
1
BSETO
BClRO
BSET1
BClR1
BSET2
BClR2
BSET3
BClR3
BSEH
BClR4
BSET5
~ClR5
BSET6
BClR6
BSET7
BClR7
2/7
Rei
OIR
2
BRA
BRN
3
f
I
A
4
I
I
X
5
NEG
f
I
,X1
6
f
I
.XO
IMP
IMP
7
8
RTI·
RTS·
9
-
BHI
-
BlS
BCC
BCS
BNE
BEQ
COM
lSR
-
2/6
, 1/4
-
-
-
Nap
-
-
-
TXA
1/2
-
, 1/6
1/·
1
B
1
C
I
I
)(2
0
I
)(1
I
E
I·xo
I
F
SUB
CMP
TAX
ClC
SEC
CLI
SEI
RSP
-
A
f EXT
-
-
-
IMM f OIR
-
SWI·
ROR
ASR
lSLlASl
ROl
DEC
INC
TST
ClR
, 1/4 , 2/7
Register/Memory
Control
Read/Modify /Write
Branch
BHCC
BHCS
BPl
BMI
BMC
BMS
Bil
BIH
2/4
Opcode Map
-
-
I
I
BSR·'
-
T
2/2
, 2/4
HIGH
SBC
CPX
AND
BIT
lOA
STA(+1)
5 W
6
7
EOA
ADC
ORA
ADD
JMP(-lI
JSR(+3)
8
9
A
B
C
0
E
lOX
STX(+1)
, 3/5
~
0
1
2
3 l
4 a
'3/6
, 2/5
F
I
1/4
1. Undefined opcodes are marked with "-".
2. The number at the bottom of each column denote the number of bytes and the number of cycles reQuired (Bytes/Cycles).
Mnemonics followed by a ..... require a different number of cycles as follows:
RTI
9
RTS
6
SWI
11
BSR
8
3. (
indicate that the number in parenthesis must be added to the cycle count for that instruction.
HD68P05 USED AS ROM-ON-CHIP HD6805UIV
When using the HD68P05 for the HD6805U (2k ROM) or
the HD6805V (4k ROM), take the memory configuration
shown in Figure 25 (a) or (b). "Not Used" or "Self Test"
($F80 to $FF7) locations can be used in the HD68P05. Note
that these locations cannot be used for a user program when
making the program in mask ROM version. The HD6805U or
HD6805V takes mask option method for internal oscillation,
low voltage inhibit circuit or timer. The HD68P05 takes crystal
option for oscillation without low voltage inhibit circuits. The
HD68P05 should specify timer part by software, so it is required to set bit 0 to bit 5 of the Timer Control Register after reset
and select the prescaler dividing ratio and the clock input
source. Figure 24 shows a program example where external
clock is selected as an input source at 128 dividing ratio.
When the program emulated by the EPROM on package type
(the HD68P05) is built in the ROM-on-chip type, the instructions operating these bits are ignored because the HD6805U/V
doesn't have the TCR bit 0 to 5.
Bit 4 and 5 of the TCR should be specified to be "CP2 controlled by TIMER Input" or "Event Input from TIMER".
The HD6805U/V has the self test program in locations
$F80 to $FF7 as shown in Fig. 25. The HD68P05 can use this
area. But a user program written in this area cannot be built in
the ROM-on-chip type. (See Table 3.) The vector address of
the HD68P05MO is $IFF8 to $IFFF differently from the
HD6805U/V.
Pay attention to the above statements when debugging the
program for the ROM-on-chip type.
lOA #$77
STA TCR ($009)
·••••
Figure 24 Example to initialize timer control register (TCR)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
ns
HD68P05V07,HD68P05MO---------------------------------------------------o
7
000
12 7
128
76543210
$000
I/O Ports
Timer
RAM
(128 Bytes)
$07F
$080
0
Port A
$000
1
Port B
$001
2
Port C
$002
3
Port D (digital)
$003"
4
Port A DDR
$004"
5
Port B DDR
$005"
6
Port C DDR
$006"
7
Port D (analog)
8
Timer Data Reg
$008
9
Timer CTR L Reg
$009
10
Not Used
$OOA
(22 Bytes)
$01 F
ROM
(128 Bytes)
$OFF
$100
255
256
Not Used
2047
2048
$7FF
$800
ROM
31
32
3967
3968
4087
4088
4095
Self-Test
Interrupt Vectors
$020
RAM (96 Bytes)
1~~
(1920 Bytes)
$007"
St~ck
$07F
• Write-Only Register
., Read-Only Register
$F7F
$F80
$FF7
$FF8
$FFF
(a) HD6805U Configuration
o
7
000
127
128
76543210
$000
I/O Ports
Timer
RAM
(128 Bytes)
$07F
$080
0
Port A
$000
1
Port B
$001
2
Port C
$002
3
Port D (digital)
$003"
4
Port A DDR
$004'
5
Port B DDR
$005'
6
Port C DDR
$006'
7
Port D (analog)
$007"
ROM
8
Timer Data Reg
$008
(3840 Bytes)
9
Timer CTR L Reg
$009
10
31
32
1:~
3967
3968
4087
4088
4095
Self-Test
Interrupt Vectors
$F7F
$F80
$FF7
$FF8
$FFF
Not Used
(22 Bytes)
RAM (96 Bytes)
$OOA
$OlF
$020
Sta{k
$07F
..
• Write-Only Register
Read-Only Register
(b) HD6805V Configuration
Figure 25
776
MCU Memory Configuration
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------HD68P05V07,HD68P05MO
• PRECAUTION TO USE EPROM ON THE PACKAGE 8-BIT
SINGLE-CHIP MICROCOMPUTER
As this microcomputer takes a special packaging type with
pin sockets on its surface, pay attention to the followings;
(1) Do not apply higher electro-static voltage or serge voltage
etc. than maximum rating, or it may cause permanent
damage to the device.
(2) There are 28 pin sockets on its surface. When using 32k
Let the index-side four pins open.
When using 24 pin EPROM, match
its index and insert it into lower
24 pin sockets.
EPROM (24 pins), let the index-side four pins open.
(3) When assembling this LSI into user's system products as
well as the mask ROM type 8-bit single-chip microcomputer, pay attention to the followings to keep the good ohmic
contact between EPROM pins and pin sockets.
(a) When soldering on a printed circuit board, etc., keep its
condition under 250°C within 10 seconds. Over-time/
temperature may cause the bonding solder of socket
pins to meet and the sockets may drop.
(b) Keep out detergent or coater from the pin sockets at
aft-solder flux removal or board coating. The flux or
coater may make pin socket contactivity worse.
(c) Avoid the permanent use of this LSI under the evervibratory place and system.
(d) Repeating insertion/removal of EPROMs may damage
the contactivity of the pin sockets, so it is recommended to assemble new ones to your system products.
Ask our sales agent about anything unclear.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
777
HD68P05WO------------MCU (Microcomputer Unit)
The HD68P05WO is the 8-bit Microcomputer Unit (MCU)
which contains a CPU, on-chip clock, RAM, an AID converter,
I/O and two timers. It is designed for the user who needs an
economical microcomputer with the proven capabilities of the
HD6800-based instruction set. Setting EPROM on the package,
this MCU has the same function as the HD6805Wl which has
on-chip ROM. It is useful not only for a means of debugging
and evaluating the HD6805WI but also for small-scale-production.
The following EPROMs are available.
4k byte: HN482732A
8k byte : HN482764
•
•
•
•
•
•
•
•
•
•
•
HARDWARE FEATURES
8-Bit Architecture
96 Bytes of RAM
Memory Mapped 1/0
Internal8-Bit Timer with 7-Bit Prescaler
Internal 8-bit Programmable Timer (Timer2) with 7-bit
Prescaler
Vectored interrupts; External, Timer and Software
23 I/O Ports + 6 Input Ports
(8 Lines Directly Drive LEOs.)
On-chip 8 bits A/D Converter
On-chip Clock Generator
Master Reset
Easy for System Development and Debugging
5 Vdc Single Supply
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SOFTWARE FEATURES
Similar to HD6800 Family
Byte Efficient Instruction Set
Easy to Program
Ture Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Function
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/F lags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible Instruction Set with HD6805
•
TYPE OF PRODUCTS
•
•
Type No.
Bus Timing
HD68P05WO
1 MHz
• PIN ARRANGEMENT
A,
IC/C,
OC/C.
OVee
OA12
OA7
OAe
OAs
OA.
OA3
OA2
OA,
OAo
000
00,
002
OVss
Vee 0
Vee 0
Vee 0
As 0
As 0
A" 0
VssO
A,oO
CEO
070
08 0
05 0
O. 0
03 0
(Top View)
EPROM Type No.
HN482732A-30
HN482764-3
(NOTE) EPROM is not attached to the MCU.
778
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------HD68P05WO
• BLOCK DIAGRAM
TIMER
8
Port B
I/O lines
TlMER-2
Timer Data
8 Register 2
Timer
8 Status Register 2
(OC)
IIC)
0
Output Compare
8 Register
.~
0$
Index Register
ca·!!
1Q~
X
Condition Code
Register
CC
5
oa:
~
.~
a:
al
(;
CI..
Program Counter
"High"
PCH
Timer Control
8 Register 2
c
"Low"
~
0
.~
.~
QJ
.!: ....
AlU
0$
Program Counter
8
B.
Bs
B6
B7
Port C
I/O Lines
SP
6
B.
B2
B3
CPU
Stack Point
Input Capture
8 Register
PortA
I/O Lines
CPU Control
8
-
.~
A
8
Prescaler Control
8 Register 2
Bo
c:
Accumulator
Prescaler 2
ca·!!
u
Oa:
CI..
1Ui'
PCl
a:
(;
Co
C.
C2
C.
C.
C s liC)
C6 (OC)
Port 0
Input Lines
Do IINT2 )
D. (AN o )
O2 (AN,)
D. (AN 2 )
O. (AN.)
(RAME) Vee Standby
.- _ ~~a.:..k~e _
I
I
I
I
I
I
05 (VRH)
I
00
0,
02
03
O.
AOC lines
, - - - - - - - AVee
,..-----AVSS
I
I
(VRH)
(AN o )
(AN,)
(AN 2 )
(AN.)
O.
Oe
07
A/O Control
Status Register
I
8
I
AID Result
Register
I
I
I
1
I
I
I
I
I
I
I
8
ADRa
ADR9
ADR,o
ADR"
ADR"
CE
(NOTE)
The contents of ( ) items can be changed by software.
Address
Output 1-_ _ _ _ _ _ _ _ _ _---'
Buffer
L _______ .-J
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
779
HD68P05WO----------------------------------------------------------•
ABSOLUTE MAXIMUM RATINGS
Symbol
Item
Supply Voltage
Vee
Input Voltage (EXCEPT TIMER)
Yin
Input Voltage (TIMER)
Value
Unit
-0.3 - +7.0
V
-0.3 - +7.0
V
-0.3 - +15.0
V
°c
°c
Operating Temperature
Topr
o -+70
Storage Temperature
Tstg
-55 - +150
(NOTE) This device has an input protection circuit for high quiescent voltage and field, however, be careful not
to impress a high input voltage than the insulation maximum value to the high input impedance circuit.
To insure normal operation, the following are recommended for V in and Vout :
VSS ~ (V in or Vout ) ~ Vee
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee = 5.25V ±0.5V, Vss = GND, Ta = 0-+70°C, unless otherwise noted.)
min
typ
max
Unit
RES
4.0
Vee
V
INT 1 ,INT 2
3.0
Vee
V
2.0
-
Vee
V
2.0
-
-0.3
-
Vee
0.8
V
Item
Symbol
Input "High" Voltage
All Others
Test Condition
V IH
Timer
RES
INT 1 ,INT 2
Input "Low" Voltage
EXTAL
All Others
Power Dissipation
-0.3
-0.3
-0.3
V IL
-
Po
LVR
Low Voltage Recover
-
TIMER
Input Leak Current
INT 1 ,INT 2
-20
IlL
V in =O.4V-V ee
Standby Voltage
Standby Current
•
-50
-1200
EXTAL
Nonoperation Mode
V SBB
4.0
Operation Mode
V SB
4.75
Nonoperation Mode
ISBB
VSBB=4.0V
-
V
0.8
0.6
0.8
V
V
V
mW
750
4.75
V
20
J..I.A
50
J..I.A
0
J..I.A
Vee
V
Vee
3
mA
AC CHARACTERISTICS (Vee = 5.25V ±0.5V, Vss = GND, Ta = 0 -+70°C, unless otherwise noted.)
Item
Symbol
Clock Frequency
min
typ
max
Unit
0.4
-
4.0
MHz
Cycle Time
teye
10
J..I.s
INT Pulse Width
tl WL
t eye+
250
-
-
ns
RES Pulse Width
tRWL
tcye+
250
-
-
ns
TIMER Pulse Width
tTWL
t eye+
250
-
-
ns
Oscillation Start-lip Time (Crystal Mode)
tose
C L =22pF±20%
Rs=60n max.
-
-
100
ms
tRHL
External Cap. = 2.2 J..I.F
100
-
ms
-
-
35
pF
-
-
10
pF
Delay Time Reset
I nput Capacitance
780
Test Condition
fel
I
I
XTAL, VRH/OS
All Others
C in
1.0
Vin=OV
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------HD68P05WO
•
PORT ELECTRICAL CHARACTERISTICS (Vee = 5.25V ±0.5V, Vss = GND, Ta = 0 - +70°C, unless otherwise noted.)
Item
Symbol
Port A
Output "High" Voltage
Output "Low" Voltage
Input "High" Voltage
Input "Low" Voltage
V OH
Port B
Test Condition
typ
max
Unit
3.5
2.4
IOH = -200~A
2.4
-
-
V
IOH = -100 ~A
-
V
V
IOH =-1 mA
1.5
-
-
V
Port C
IOH = -100 ~A
2.4
-
-
V
Ports A and C
IOL = 1.6 mA
-
0.5
V
IOL = 3.2 mA
-
-
0.5
V
IOL = 10mA
-
1.0
V
Vee
0.8
V
~A
J.lA
VOL
Port B
Ports A, B, C
and D*
V IH
2.0
-
V IL
-0.3
-
V in = 0.8V
-500
-
V in = 2V
-300
-
-
-20
-
20
Port A
Input Leak Current
min
IOH =-10~A
IlL
Ports B, C and 0*
V in = O.4V-V ee
V
~A
* Port 0 as digital mput
•
AID CONVERTER ELECTRICAL CHARACTERISTICS (Vee = 5.25V±O.5V, Vss = AVss = GMD, Ta = 0 - +70°C, unless
otherwise noted.)
Item
min
typ
AVee
4.75
AV in
0
Symbol
Analog Power Supply
Voltage
Analog Input Voltage
Reference "High" Voltage
VRH
Test Condition
4.75V ~ V ee ~ 5.25V
4.0
< Vee ~ 5.75V
4.0
5.25V
max
Unit
5.25
5.75
V
-
V RH
V
Vee
5.25
V
V
Analog Multiplexer Input
Capacitance
-
-
7.5
pF
Resolution Power
-
8
-
Conversion Time
76
76
76
Bit
tcyc
4
4
4
Channel
-
-
±1.5
LSB
Input Channels
Ta = 25°C
Absolute Accuracy
TTL Equiv. (Ports A,C)
TTL Equiv. (Port B)
Vee
Vee
Ii
= 3.2 rnA
1.2kn
Ii = 1.6 rnA
Test Point
Test Point
Vi
2.4kn
Vi
40 pF
(NOTE)
30 pF
1.2kn
24 kn
1. Load capacitance includes the floatin!;! capacitance of the probe and the jig etc.
2. All diodes are 1S2074(fj) or equivalent.
Figure 1 Bus Timing Test Loads
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
781
HD68P05WO-----------------------------------------------------------• SIGNAL DESCRIPTION
The input and output signals for the MCU, shown in PIN
ARRANGEMENT, are described in the following paragraphs.
Vee and Vss
Voltage is supplied to the MCU using these two pins. Vee is
S.2SV ±O.SV. Vss is the ground connection.
•
•
disabled.
Vee Standby must remain above VSBB (min).
(2) Hardware
When RAME pin is "Low" before powerdown, the RAM is
disabled. Vee Standby must remain above VSBB (min).
INT 1 /INT 2
This pin provides the capability for asynchronously applying
an external interrupt to the MCU. Refer to INTERRUPTS for
additional information.
XTAL and EXTAL
These pins provide connections for the on-chip clock circuit.
A crystal (AT cut, 4MHz maximum) or an external signal can be
connected to these pins to provide the internal oscillator with
varying degrees of stability. Refer to INTERNAL OSCILLATOR for recommendations about these inputs.
•
• TIMER
This pin allows an external input to be used to count for the
internal timer circuitry. Refer to TIMER 1 and TIMER 2 for
additional information about the timer circuitry.
•
RES
This pin allows resetting of the MCU. Refer to RESETS for
additional information.
•
NUM
This pin is not for user application and should be connected
to Vss·
I/O Lines (Ao - A 7 • Bo - B 7 • Co - C6 I
These 23 lines are arranged into three ports (A, B and C). All
lines are programmable as either inputs or outputs under software control of the Data Direction Registers. Refer to INPUT I
OUTPUT for additional information.
•
Input Lines (Do - 05 I
These are TTL compatible input lines,' in location $0003.
These also allow analog inputs to be used for an AID converter.
Refer to INPUT for additional information.
Figure 2
•
Battery Backup for Vee Standby
RAME
This pin is used for the external control of the RAM. When
it is "Low" before powerdown, the RAM is disabled. If Vee
Standby remains above VSBB (min), the standby RAM is
sustained.
•
AVee
•
ANo - AN3
This pin is used for the power supply of the AID converter.
When high accuracy is required, a different power source from
Vee should be impressed.
Connect to Vee for all other cases. AVss corresponds to
A Vccas a GND terminal.
These pins allow analog inputs to be used for an AID converter. These inputs arll switched by the internal multiplexer
and selected by bit 0 and 1 of the AID Control Status Register
(ADCSR: $OOOE).
•
VRH and AVss
The input terminal reference voltage for the AID converter is
"High" (VRH) or "Low" (AVss). AVss is ftxed at OV.
•
Vee Standby
Vee Standby provides power to the standby portion of the
RAM and the STBY PWR and RAME bits of the RAM Control
Register. Voltage requirements depend on whether the MCU
is in a powerup or powerdown state. In the powerup state, the
power supply should provide Vee and must reach VSB before
RES reaches 4.0V. During powerdown, Vee Standby must
remain above VSBB (min) to sustain the standby RAM and
STBY PWR bit. While in powerdown operation, the standby
current will not exceed ISBB'
It is typical to power both Vee and Vee Standby from the
same source during nomal operation. A diode must be used
between them to prevent supplying power to Vee during powerdown operation shown Figure 2.
To sustain the standby RAM during powerdown, the following software or hardware are needed.
(1) Software
When clearing the RAM Enable bit (RAME) which is bit 6
of the RAM Control Register at location $OOlF, the RAM is
•
782
*
•
Input Capture (lC)
This pin is used for input of Timer2 control. in this case,
Port Cs should be conftgured as input. Refer to TIMER 2 for
more details.
•
Output Compare (Oel
This pin is used for output of Timer2 when the Output
Compare Register is matched with the rimer Data Register 2.
In this case, Port C6 should be conftgured as an output. Refer to
TIMER 2 for more details.
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------HD68P05WO
•
REGISTERS
The CPU has five registers available to the programmer,
as shown in Figure 3 and explained below.
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each individual condition code register bit is explained below.
Half Carry (H)
The half carry bit is used during arithmetic operations (ADD
or ADC) to indicate that a carry occurred between bits 3 and 4.
°
'--_ _ _ _
A_ _ _ _.....II Accumulator
°
'--____x____
.....Illndex Register
(2
°1
12
6 5
°
Lolo.....I....0.....lI_o.......l_o.....jIL,...0.......I_o.....jlL,...l.....jIL...-_ _s_p_-....J1
_ _ _ _ _ _ _ _ _P_C_ _ _ _ _ _....J Program Counter
Stack Pointer
Condition Code
Register
Carry/Borrow
Zero
Negative
Interrupt Mask
' - - - - - - - - Half Carry
Interrupt (I)
This bit is set to mask everything. If an interrupt occurs
while this bit is set, it is latched and will be processed as soon as
the interrupt bit is reset.
Negative (N)
The negative bit is used to indicate that the result of the last
arithmetic, logical or data manipulation was negative (bit 7 in
a result equal to a logical one).
Zero (Z)
Zero is used to indicate that the result of the last arithmetic,
logical or data manipulation was zero.
Carry/Borrow (C)
Carry/borrow is used to indicate that a carry or borrow out
of the arithmetic logic unit (ALU) occurred during the last
arithmetic operation. This bit is also affected during bit test and
branch instructions, shifts and rotates.
Figure 3 Programming Model
• TIMER 1
• Accumulator (A)
The accumulator is a general purpose 8-bit register used to
hold operands and results' of arithmetic calculations or data
manipulations.
•
Index Register (X)
The index register is an 8-bit register used for the indexed
addressing mode and contains an 8-bit address that may be
added to an offset value to create an effective address. The
index register can also be used for limited calculations or data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
• Program Counter (PC)
The program counter is a 13-bit register that contains the
address of the next instruction to be executed.
• Stack Pointer (SP)
The stack pointer is a 13-bit register that contains the address
of the next free location on the stack. Initially, the stack pointer is set to location $007F and is decremented as data is being
pushed onto the stack and incremented while data is being
pulled from the stack. The seven most Significant bits of the
stack pointer are permanently set to 0000001. During an MCU
reset or reset stack pointer (RSP) instruction, the stack pointer
is set to location $007F. Subroutines and interrupts may be
nested down to location $0041 which allows the programmer to
use up to 31 levels of subroutine calls.
The MCU timer circuitry is shown in Figure 4. The 8-bit
counter, Timer Data Register 1 (TDR1), is loaded under pro·
gram control and counts down toward zero as soon as the clock
input is applied. When the TDRI reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register 1 (TCR1)
is set. The MCU responds to this interrupt by saving the present
CPU state in the stack, fetching the timer 1 interrupt vector
from locations $OFF8 and $OFF9 and executing the interrupt
routine. The timer 1 interrupt can be masked by setting the
timer interrupt mask bit (bit 6) in the TCR 1. The interrupt bit
(I bit) in the Condition Code Register also prevents a timer 1
interrupt from being processed.
The clock input to the timer 1 can be from an external
source applied to the TIMER input pin 01: it can be the internal
1/>2 signal. When 1/>2 is used as the source, it can be gated by an
input applied to the TIMER input pin allowing the user to
easily perform pulse-width measurements. The timer 1 continues to count past zero, falling through to $FF from zero and
then continuing the count. Thus, the counter (TDR1) can be
read at any time by reading the TDRI. This allows a program
to determine the length of time since a timer interrupt has
occurred and not disturb the counting process.
At power-up or reset, the prescaier and counter are initialized
with all logical ones; the timer 1 interrupt request bit (bit 7) is
cleared and the timer 1 interrupt mask bit (bit 6) is set. In
order to release the timer 1 interrupt, bit 7 of the TCR 1 must
be cleared by software.
• Condition Code Register (CC)
The condition code register is a 5-bit register in which each
bit is used to indicate or flag the results of the instruction just
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
783
HD68P05WO-----------------------------------------------------------
3
Write
Read
Fig'Ure 4 Timer Clock
• Timer Control Register 1 (TCR1: $0009)
The Timer Control Register I (TCRI: $0009) can control
selection of clock input source and prescaler dividing ratio and
timer interrupt.
Timer Control Register 1 (TCR1: $0009)
6
5
4
3
2
I
0
TlF I TIM IIS1 I ISO V1MS21 MS11 MSO
~
.
I
TCRl
Bit 5
0
0
1
1
Bit4
0
1
0
1
Clock Input Source
---
Internal Clock cf>2 *
cf>2 Controlled by TIMER Input
Event Input From TIMER
* The TIMER input pin must be tied to Vee, for uncontrolled
clock input.
Table 2 Selection of Prescaler Dividing Ratio
L"nml" o;,'d'o, R.",
Clock Input Source
Timer Interrupt Mask
L - - - - - - - - - - T i m e r Interrupt Request Flag
As shown in Table I, the selection of the clock input source
e
is ISO and lSI in the TCRI (bit 4 and bit 5) and 3 kinds of
input are selectable. At reset, internal clock cf>2 controlled by
the TIMER input (bit 4 = I, bit 5 =0) is selected.
The prescaler dividing ratio is selected by MSO, MS I, and
MS2 in the TCRI (bit 0, bit I, bit 2) as shown in Table 2. The
dividing ratio is selectable from eight ways (+ I, +2, +4, +8, + 16,
+32, +64, +128). At reset, + 1 mode is selected. The prescaler
is initialized by writing in the TDRI.
Timer 1 interrupt mask bit (TIM) allows the Timer 1 into
interrupt at "0" and masks at "1". Timer 1 interrupt causes
Timer 1 interrupt request bit (TIF) to be set. TIF must be
cleared by software.
(NOTE) If the MCV Timerl and Timer2 are not used, the
TIMER input pin must be grounded.
784
Table 1 Selection of Clock Input Source
Bit 2
0
0
0
0
1
1
1
1
TCRl
Bit 1
0
0
1
1
0
0
1
1
Bit 0
0
1
Q
1
0
1
0
1
Prescaler Dividing Ratio
+1
+2
+4
+8
+16
+32
+64
+ 128
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
~2
-----------------------------------------------------------HD68P05WO
• TIMER 2
The HD68P05WO includes an 8-bit programmable timer
(Timer 2) which can not only measure the input waveform
but also generate the output waveform. The pulse width for
both input and output waveform can be varied from several
microseconds to several seconds.
(NOTE) If the MCV Timerl and Timer2 are not used, the
TIMER input pin must be grounded.
Timer 2 hardware consists of the followings.
• 8·bit Control Register 2
• 8-bit Status Register 2
• 8-bit Timer Data Register 2
• 8-bit Output Compare Register
• 8-bit Input Capture Register
• 5-bit Prescaler Control Register
• 7-bit Prescaler 2
Block Diagram of Timer 2 is shown in Fig. 5.
8
Read/Write
Output Compare Register
(OCR: $0010)
8 bit Register
8
I--_ _.......:._ _..J ReadlWrite
Input Capture Register (lCR: S001 E)
8 bit Register
8
Read
Timer Control Register 2
(TCR2: $0018)
ICI
OCI TOI
Internal Interrupts Request Signal
Figure 5 Block Diagram of Timer 2
•
Timer Data Register 2 (TOR2; $OO1C)
The main part of the Timer 2 is the 8-bit Timer Data Register
2 (TDR2) as free-running counter, which is driven by internal
clock tP2 or the TIMER input and increments the value. The
values in the counter is always readable by software.
The Timer Data Register 2 is Read/Write register and is
cleared at reset.
output level bit (OLVL) in the TCR2 is transferred to Port C6
(OC).
If Port C6 's Data Direction Register (DDR) is "1" (output),
this value will appear at Port C6 (OC). Then the values of OCF
and OLVL can be changed for the next compare. The OCR is
set to $FF at reset.
•
• Output Compare Register (OCR; $0010)
The Output Compare Register (OCR) is an 8-bit read/write
register used to control an output waveform. The contents of
this register are always compared with those of the TDR2.
When these two contents conform to each other, the flag (OCF)
in the Timer Status Register 2 (TSR2) is set and the value of the
Input Capture Register (lCR; $001E)
The Input Capture Register (ICR) is an 8-bit read-only
register used to store the value of the TDR2 when Port Cs
(IC) input transition occurs as defined by the input edge bit
(IEDG) of the TCR2.
In order to apply Port Cs (IC) input to the edge detect
circuit, the DDR of Port Cs should be cleared ("0").*
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
785
HD68P05WO------------------------------------------------------------Bit 5 TOF Timer Overflow Flag
To ensure an input capture under all condition, Port Cs
(Ie) input pulse width should be 2 Enable-cycles at least.
This read-only bit is set when the TDR2 contains $00. It
is cleared by reading the TSR2 followed by reading of the
TDR2 .
*The edge detect circuit always senses Port Cs (IC) even if the DDR
is set with Port Cs output.
•
Timer Control Register 2 (TCR2; $001B)
Bit 6 OCF Output Compare Flag
The Timer Control Register 2 (TCR2) consists of an 5-bit
register of which all bits can be read and written.
This read-only bit is set when a match is found between the
OCR and the TDR2. It is cleared by reading the TSR2 and then
writing to the OCR.
Timer Control Register 2 (TCR2: $001 B)
6
5
4
I 2 1 Z I Z I ICIM
3
2
1 OCIM 1 TOIM
Bit 7 ICF Input Capture Flag
This read-only bit is set to indicate a proper level transition
and cleared by reading the TSR2 and then reading the TCR2.
0
IIEDG
1 OLVL 1
User can write into port C6 by software.
Accordingly, after port C6 has output by hardware and is
immediately write into by software, simultaneous cyclic pulse
control with a short width is easy .
•
Bit 0 OL VL Output Level
Prescaler Control Register 2 (PCR2: $0019)
The selections of clock input source and prescaler dividing
ratio are performed by the Prescaler Control Register 2 (peR2:
$0019).
This bit will appear at Port C6 when the value in the TDR2
equals the value in the OCR, if the DDR of Port C6 is set. It
is cleared by reset.
Bit 1 I EDG Input Edge
This bit determines which level transition of Port C5 (IC)
input will trigger a data store to ICR from the TDR2. When
this function is used, it is necessary to clear DDR of Port C5 •
When IEDG = 0, the negative edge triggers ("High" to "Low"
transition). When IEDG = I, the positive edge triggers ("Low"
to "High" transition). It is cleared by reset.
Prescaler Control Register 2 (PCR2: $0019)
6
5
151
I21Z1
4
ISO
3
0
o
2
MS2
Bit 2 TOIM Timer Overflow Interrupt Mask
.
MSl
M50
t
When this bit is cleared, internal interrupt (TOI) is enabled
by TOF interrupt but when set, interrupt is inhibited.
Prescaler Dividing Ratio
L -_ _ _ _ _ _
Bit 3 OCIM Output Compare Interrupt Mask
Clock Input Source
When this bit is cleared, internal interrupt (OCI) by OCF
interrupt occurs. When set, interrupt is inhibited.
Bit 4 ICIM Input Capture Interrupt Mask
When this bit is cleared, internal interrupt (lCI) by ICF
interrupt occurs. When set, interrupt is inhibited.
•
Timer Status Register 2 (TSR2: $001A)
The Timer Status Register 2 (TSR2) is an 8-bit read-only
register which indicates that:
(1) A proper leveltransition has been detected on the input
pin with a subsequent transfer of the TDR2 value to the
ICR (lCF).
(2) A match has been found between the TDR2 and the OCR
(OCF).
(3) The TDR2 is zero (TOF).
Each of the event can generate 3 kinds of internal interrupt
request and is controlled by an individual inhibit bits in the
TCR2. If the I bit in the Condition Code Register is cleared,
priority vectors are generated in response to clearing each
interrupt mask bit. Each bit is described below.
ICF
786
OCF
5
4
3
2
Table 3 Selection of Clock Input Source
PCR2
Bit 5
Bit4
0
0
0
1
1
0
1
1
Clock Input Source
Internal Clock
CD
~
Table 8
oC1I
Register/Memory Instructions
~
Addressing Modes
;;.
~
f---------.
Function
Mnemonic
Immediate
Indexed
(No Offset)
Extended
Direct
~
»
Op
Op
Op
#
#
#
#
Code Bytes Cycles Code Bytes Cycles Code
3
~
Op
#
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
Indexed
(16-Bit Offset)
Op
#
#
Bytes Cycles Code
#
#
Bytes Cycles
c:r
Load A from Memory
LOA
A6
2
2
B6
2
4
C6
3.
5
F6
1
4
E6
2
5
06
3
6
!::
p..
Load X from Memory
LOX
AE
2
2
BE
2
4
CE
3
5
FE
1
4
EE
2
5
DE
3
6
Store A in Memory
STA
-
-
-
B7
2
5
C7
3
6
F7
1
5
E7
2
6
07
3
7
Store X in Memory
STX
-
-
-
BF
2
5
CF
3
6
FF
1
5
EF
2
6
OF
3
7
Add Memory to A
ADD
AB
2
2
BB
2
4
CB
3
5
FB
1
4
EB
2
5
DB
3
6
Add Memory and
Carry to A
ADC
A9
2
2
B9
2
4
C9
3
5
F9
1
4
E9
2
5
09
3
6
Subtract Memory
SUB
AO
2
2
BO
2
4
CO
3
5
FO
1
4
EO
2
5
DO
3
6
Subtract Memory from
A with Borrow
SBC
A2
2
2
B2
2
4
C2
3
5
F2
1
4
E2
2
5
02
3
6
~
•
I\)
I\)
o
o
c}
~~
~:t
.CD
·
-~
- - - _ .. -
AND Memory to A
AND
A4
2
2
B4
2
4
C4
3
5
F4
1
4
E4
2
5
04
3
6
OR Memory with A
ORA
AA
2
2
BA
2
4
CA
3
5
FA
1
4
EA
2
5
DA
3
6
Exclusive OR Memory
with A
EOR
A8
2
2
B8
2
4
C8
3
5
F8
1
4
E8
2
5
08
3
6
()
Arithmetic Compare A
with Memory
CMP
A1
2
2
B1
2
4
Cl
3
5
Fl
1
4
El
2
5
01
3
6
co
~
~
Arithmetic Compare X
with Memory
CPX
A3
2
2
B3
2
4
C3
3
5
F3
1
4
E3
2
5
03
3
6
Bit Test Memory with A
(Logical Compare)
BIT
A5
2
2
B5
2
4
C5
3
5
F5
1
4
E5
2
5
05
3
6
Jump Unconditional
JMP
-
-
-
BC
2
3
CC
3
4
FC
1
3
EC
2
4
DC
3
5
Jump to Subroutine
JSR
-
-
-
BD
2
7
CD
3
8
FD
1
7
ED
2
8
DO
3
9
~
CJ)()
:t
c...~
oen
~
»
•
~
o
$
~
(J.)
CJ1
Co
(J.)
8
Symbols:
Op: Operation Abbreviation
# : Instruction Statement
:J:
~
~
»
3
Table 9
~
0"
Read/ModifyIWrite Instructions
$l)
r-
Addressing Modes
ei
•
Function
Implied (A)
Mnemonic
Indexed
(No Offset)
Direct
Implied (X)
I\)
~
o
Op
Code
o
oi
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
#
#
Bytes Cycles
Increment
INC
4C
1
4
5C
1
4
3C
2
6
7C
1
6
6C
2
7
~~
Decrement
DEC
4A
1
4
5A
1
4
3A
2
6
7A
1
6
6A
2
7
(1)
_
~:I
Clear
CLR
4F
1
4
5F
1
4
3F
2
6
7F
1
6
6F
2
7
"~
Complement
COM
43
1
4
53
1
4
33
2
6
73
1
6
63
2
7
• )Ii
:I
c.....-
Negate
(2's Complement)
NEG
40
1
4
50
1
4
30
2
6
70
1
6
60
2
7
Rotate Left Thru Carry
ROL
49
1
4
59
1
4
39
2
6
79
1
6
69
2
7
(1)
Rotate Right Thru Carry
ROR
46
1
4
56
1
4
36
2
6
76
1
6
66
2
7
()
Logical Shift Left
LSL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
00(")
~
o
en
»
CO
~
~
•
~
o
$
~
Logical Shift Right
LSR
44
1
4
54
1
4
34
2
6
74
1
6
64
2
7
Arithmetic Shift Right
ASR
47
1
4
57
1
4
37
2
6
77
1
6
67
2
7
Arithmetic Shift Left
ASL
48
1
4
58
1
4
38
2
6
78
1
6
68
2
7
Test for Negative or
Zero
TST
4D
1
4
5D
1
4
3D
2
6
7D
1
6
6D
2
7
Symbols:
Op: Operation Abbreviation
# : Instruction Statement
Co)
01
00
Co)
o
o
:::L
o
CJ)
CD
"tI
o
00
~
01
~
HD68P05WO------------------------------------------------------------Table 10 Branch Instructions
Relative Addressing Mode
Function
Mnemonic
Op
Code
#
#
Bytes
Cycles
Branch Always
BRA
20
2
4
Branch Never
BRN
21
2
4
Branch IF Higher
BHI
22
2
4
Branch I F Lower or Same
BLS
23
2
4
Branch I F Carry Clear
BCC
24
2
4
(Branch IF Higher or Same)
(BHS)
24
2
4
Branch I F Carry Set
BCS
25
2
4
(Branch IF Lower)
(BLO)
25
2
4
Branch I F Not Equal
BNE
26
2
4
Branch I F Equal
BEQ
27
2
4
Branch IF Half Carry Clear
BHCC
28
2
4
Branch I F Half Carry Set
BHCS
29
2
4
Branch I F Plus
BPL
2A
2
4
Branch IF Minus
BMI
2B
2
4
Branch IF Interrupt Mask Bit is Clear
BMC
2C
2
4
Branch I F I nterrupt Mask Bit is Set
BMS
20
2
4
Branch I F Interrupt Line is Low
BIL
2E
2
4
Bra nch I F I nterru pt Li ne isH igh
BIH
2F
2
4
Branch to Subroutine
BSR
AD
2
8
Symbols: Op: Operation Abbreviation
#: Instruction Statement
Table 11
Bit Manipulation Instructions
Addressing Modes
Bit Test and Branch
Bit Set/Clear
Mnemonic
Function
Op
Code
#
#
Bytes
Cycles
Op
Code
#
#
Bytes
Cycles
Branch IF Bit n is set
B RSET n (n=O ..... 7)
-
-
-
2·n
3
10
Branch IF Bit n is clear
BRCLR n (n=O .... .7)
-
-
-
01+2·n
3
10
Set Bit n
BSET n (n=O ..... 7)
10+2·n
2
7
-
-
-
Clear bit n
BCLR n (n=O ..... 7)
11+2·n
2
7
-
-
-
Symbols: Op: Operation Abbreviation
#: Instruction Statement
Table 12 Control Instructions
Implied
Function
Op
Code
#
#
Bytes
Cycles
Transfer A to X
TAX
97
1
2
Transfer X to A
TXA
9F
1
2
Set Carry Bit
SEC
99
1
2
Clear Carry Bit
CLC
98
1
2
Set Interrupt Mask Bit
SEI
9B
1
2
Clear Interrupt Mask Bit
CLI
9A
1
2
Software Interrupt
SWI
83
1
11
Return from Subroutine
RTS
81
1
6
Return from Interrupt
RTI
80
1
9
Reset Stack Pointer
RSP
9C
1
2
No·Operation
NOP
90
1
2
Symbols: Op: Operation AbbreViation
802
Mnemonic
#: I nstructlon Statement
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------HD68P05WO
Table 13 Instruction Set
Mnemonic
Implied
ADC
ADD
AND
ASL
ASR
BCC
BCLR
BCS
BEQ
Immediate
Direct
x
x
x
x
x
x
x
x
x
x
Extended
x
x
x
Condition Code
Bit
Set/
Clear
Bit
Test &
Branch
/\
•
•
•
•
I
x
x
x
x
x
x
x
x
x
x
•
•
•
•
•
•
•
•
I
x
x
x
•
•
•
x
x
•
•
•
•
x
x
x
x
x
x
x
x
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
•
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
C
/\
H
/\
x
BMS
BNE
JSR
LOA
LOX
Relative
x
BHCC
BHCS
BHI
BHS
BIH
BIL
BIT
BLO
BLS
BMC
BMI
CLC
CLI
CLR
CMP
COM
CPX
DEC
EOR
INC
JMP
Addressing Modes
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
I
N
Z
C
• /\ /\ /\
• /\ /\ /\
• /\ /\ •
• /\ /\ /\
• /\ /\ /\
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• /\ /\ •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• •
• •
• •
• •
• •
• •
• •
• •
• 0
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
•
•
•
/\
/\
•
•
0
•
0
1
•
/\
/\
/\
/\
/\
1
/\
/\
/\
/\
/\
/\
/\
•
•
• • /\ /\ •
• • • • •
• • • • •
• •
• •
/\
/\
/\
/\
•
•
(to bl! continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
803
HD68P05WO------------------------------------------------------------Table 13 Instruction Set
Addressing Modes
Implied
Mnemonic
Immediate
Relative
Extended
Direct
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
LSL
x
x
x
x
LSR
x
x
x
x
NEG
x
x
x
x
NOP
x
x
x
x
ORA
x
x
x
x
x
Bit
Setl
Clear
Bit
Test &
Branch
I
N
• •
• •
• •
1\
1\
1\
0
1\
1\
1\
1\
1\
?
H
x
x
x
ROR
x
x
RSP
x
RTI
x
?
RTS
x
•
•
•
•
•
•
•
•
x
x
x
x
x
x
STA
x
x
x
x
x
x
x
x
x
x
x
x
x
STX
x
x
x
SEC
x
SEI
x
x
SUB
SWI
x
TAX
x
TST
x
TXA
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
I nterrupt Mask
N
Negative (Sign Bit)
Z
Zero
C
C
• • • • •
• • 1\ 1\ •
• • 1\ 1\ 1\
• • 1\ 1\ 1\
• • • • •
ROL
SBC
Z
?
?
?
• • • •
• 1\ 1\ 1\
• • • 1
1 • • •
• 1\ 1\ •
• 1\ 1\ •
• 1\ 1\ 1\
1 • • •
• • • • •
• • 1\ 1\ •
• ·1 • • •
x
x
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
1\
•
?
Table 14 Opcode Map
Bit Manipulation
0
Setl
Test &
Branch
Clear
0
BRSETO
Brnch
Rei
DIR
1
2
3
BSETO
BRA
I
A
I
x
4
I
5
6
I
,XO
IMP
IMP
IMM
I
DIR
I
7
8
9
A
I
B
NEQ
-
I EXT I
1
C
1
,X2
D
I
Xl
1
E
1 ,xo
]
F
~
RTI"
-
RTS"
-
CMP
1
2
SUB
BCLRO
2
BRSETl
BSETl
BHI
-
3
4
BRCLRl
BCLRl
BLS
COM
BRSET2
BSET2
BCC
LSR
5
BRCLR2
BCLR2
B(;~
-
6
BRSET3
BSET3
BNE
ROR
-
7
BRCLR3
BCLR3
BEQ
ASR
-
TAX
8
8RSET4
BSET4
BHCC
LSLlASL
-
CLC
BRCLR4
BCLR4
BHCS
ROL
-
SEC
ADC
9
BRSET5
BSET5
BPL
DEC
-
CLI
ORA
A
B~L_R5
BMI
-
BSET6
BMC
2
A
BRCLRO
t-
-
~ ~RCLI3~
C
BRSET6
--E.
BRCLR6
F
BRCLR7
f--'
3/10
INOTE)
2/7
2/4
2/6
I
1/4
I
SBC
CPX
3
-
-
AND
4
-
-
BIT
5
LDA
6
-
-
RSP
NOP
CLR
-
TXA
-
1/2
2/2
1/4
I
2/7
I
1/6
1/"
I
STA(+l1
7
EOR
8
ADD
-
TST
BIH
-
-
~ I--~EI_
INC
BCLR6 BMS
t-------'--- f--------'--- f - - - - t--E BRSET7
BSET7
BIL
BCLR7
SWI"
-
1
BSR"I
-
-r
2/41 3/5
c
JSR(+31
D
LDX
E
i 3/6
o
w
B
JMP(-ll
STX(+l1
I
HIGH
0
BRN
1
804
i
I
,Xl
Register/Memory
Control
Read/Modify/Write
-r
F
2/5
I 1/4
1, Undefined opcodes are marked with "-",
2, The number at the bottom of each column denotes the number of bytes and the number of cycles required (Bytes/Cycles).
Mnemonics followed by a " .... require a different number of cycles as follows:
RTI
9
RTS
6
SWill
BSR
8
3. (
I indicates that the number in parenthesis must be added to the cycle count for that instruction.
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD68P05WO
•
HD68P05WO USED FOR HD6805W1
The HD680SWI provides mask option of the internal oscillator and low voltage inhibit, while the HD68POSWO provides
only crystal option and without low voltage inhibit function.
The address from $OF7 A to $OFF 1 cannot be used for user
program because the self test program of the HD680SWl (on-
chip ROM version) is located at these addresses.
In order to be pin compatible with the HD680SW 1, the
address of the HD68POSWO's ROM must be located at $0080 $OFFF. Memory addresses $1000 to $1 FFF should not be
usable.
$0000
$0001
RAM
$0001
$0002
$0002
$0003··
$0003--
SO Zero
2
Z + (N (±) VI- 0
BGT
2E
3
Branch If Higher
BHI
22
3 2
Branch If .. Zero
BlE
2F
3
2
Z + (N (±) VI- 1
Branch If lower Or
Seme
BlS
23
3
2
C+Z-l
Branch If
< Zero
C+Z=O
N (±) V-I
BlT
20
3 2
Branch If Minus
BMI
2B
3
2
N -I
Branch If Not Equal
Zero
BNE
26
3
2
Z-O
Branch If Owrflow
Clear
BVC
2B
3
2
V-O
Branch If Owrflow Set
BVS
29
3 2
V-I
Branch If Plus
BPl
2A
3
2
N-O
BD
5
2
Branch To Subroutine
BSR
Jump
JMP
Jump To SUbroutine
JSR
No Operation
NOP
01
Return From Interrupti
RTI
3B 10 1
Retum From
Subroutine
RTS
39
6E
3
2
7E
3
3
90 5 2 AD 5 2 BO 6 3
1 1
Advances Prog. Cntr.
Onlv
5 1
Sof_relnterrupt
SWI
3F 12 1
Weit for Interrupt"
Sleep
WAI
SlP
3E
5
H
#
BRA
9 1
lA 4 1
Note) ·WAI puts R/W high; Address Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of Table 11.
4
3 2 1 0
I N Z V C
·· ·· ·· ·· ·· ·
··· ··· ··· ··· ··· ···
·· ·· ·· ·· ·· ··
··· ··· ··· ··· ··· ···
·· ·· ·· · ·· ··
······
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
······
·· · ·· ·· ·· ··
·• • • ·• ·• ·•
e
e
--@--
S
@.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
831
HD63P01M1,HD63PA01M1,HD63PB01M1-------------------Table 11
Condition Code Register Manipulation Instructions
f/'ddreHingModft
OptrMions
Mnemonic
Condition Code Aegister
Boolean Operation
IMPLIED
OP
-
#
1
1
O .... C
ClC
OC
Clear Interrupt Mesk
Cli
OE
1
1
0 .... 1
C..... Overflow
ClV
OA
1
1
1
1
1
1
0 .... V
1
CCA .... A
SEC
00
SEI
OF
Set Overflow
SEV
OB
Accumulator A .... CCA
TAP
06
CCA .... Accumulator A
TPA
07
1
1
1
1
1
4
3
2
1
H
I
N
Z
V
0
C
·· · ·· ·· ·· ·
·· ·· ·· ·· · ·
·· · ·· ·· · ··
······
A
C..... c.rry
Set Cerry
Set Interrupt Mesk
5
A
R
I .... C
S
1 .... 1
S
I .... V
S
--@---
A .... CCA
[NOTE 11 Condition Code
CD (Bit V)
@
(Bit C)
@
(Bit C)
@
(Bit V)
® (Bit VI
@
(Bit V)
CD (Bit NI
@
(All Bit)
® (Bit I)
[NOTE
Register Notes: (Bit set if test is true and cleared otherwise)
Test: Result = looooooo?
Test: Result It. 00000000?
Test: BCD Character of high-order byte greater than 9? (Not cleared if previously set!
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to N&>C=1 after the execution of instructions
Test: Result less than zero? (Bit 15=1)
load Condition Code Register from Stack.
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the wait
state.
@)
(All Bit) Set according to the contents of Accumulator A.
® (Bit C) Result of Multiplication Bit 7= 1 of ACCB?
CLI instructions and interrupt.
If interrupt mask-bit is set (1="1"1 and interrupt is requested (iRa. = "0" or IRQ, = "0"1,.
and then CLI instruction is executed, the CPU responds as follows.
1 the next instruction of Cli is one-machine cycle instruction.
Subsequent two instructions are executed before the interrupt is responded.
That is, the next and the next of the next instruction are executed.
the next instruction of CLI is two-machine cycle (or morel instruction.
Only the next instruction is executed and then the CPU jump to the interrupt routine.
Even if TAP instruction is used, instead of CLI, the same thing occurs.
21
Table 12 OP-Code Map
OP
ACC
ACC
CODE
A
B
~O~
0000
0
LO
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
NOP
2 ~
3 ~
0001
1
0010
2
0011
3
SBA
BRA
TSX
CBA
BAN
INS
/""
BHI
PULA
~ 8LS
LSRO ~ BCC
PULB
ASLD
,.,.-
BCS
TXS
TAP
TAB
BNE
PSHA
TPA
TBA
BEQ
PSHB
INX
XGOX BVC
PULX
9
DEX
OM
BVS
RTS
A
CLV
SLP
BPL
A8X
4
5
6
7
8
DES
B
SEV
ABA
8MI
RTI
C
CLC
/""
8GE
PSHX
0
SEC
E
CLI
F
SEI
~ 8LT
~ 8GT
~ 8LE
0
1
2
MUL
WAI
SWI
3
--
0100
4
0101
5
--5
OIA
0110
0111
7
6
ACCB or X
ACCA or SP
1 EXT
1000 1 1001 1 1010 1 1011
8 1 9 1 A 1 B
IMM lOlA
liND
NEG
1 EXT
1 1101 1 1110 1 1111
1 0 1 E 1 F
IMM lOlA liND
1100
C
SUB
AIM
0
1
2
3
CMP
OIM
SBC
COM
SUBD
AOOD
LSA
ElM
ROA
AND
4
BIT
5
6
7
8
LOA
~I
ASA
~.I
STA
STA
ASL
EOR
ROL
AOC
9
DEC
ORA
ADD
A
TIM
INC
B
CPX
TST
BSR
~~
4
Vo;i
INO
1
"/-1
JSA
JMP
7
8
1
1 A
0
LOX
~
STS
9
C
STO
LOS
/"I
CLR
6
LOO
1
B
C
I
E
STX
o
I
E
F
I
F
UNDEFINED OP CODE ~
• Only for instructions of AIM, OIM, ElM, TIM
832
~HITACHI
Hitachi America Ltd_ • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63P01M1,HD63PA01M1,HD63PB01M1
•
Instruction Execution Cycles
In the HMCS6800 series, the execution cycle of each instruction is the number of cycles between the start of the current
instruction fetch and just before the start of the subsequent
instruction fetch.
The HD63POIMl uses a mechanism of the ~peline control for the instruction fetch and the subsequent instruction
fetch is performed during the current instruction being exe-
cuted.
Therefore, the method to count instruction cycles used in
the HMCS6800 series cannot be applied to the instruction cycles such as MULT, PULL, DAA and XGDXin the HD63POIMl.
Table 13 provides the information about the rell!!.!onship
among each data on the Address Bus, Data Bus, and R/W status
in cycle-by-cycle basis during the execution of each instruction.
Table 13 Cycle-by-Cycle Operation
Address Mode &
Instructions
IMMEDIATE
ADC
ADD
BIT
AND
CMP
EOR
LDA
ORA
SBC
SUB
ADDD CPX
LDD
LDS
LDX
SUBD
DIRECT
ADC
AND
CMP
LDA
SBC
STA
ADD
BIT
EOR
ORA
SUB
Address Bus
CPX
LDS
SUBD
STD
STX
STS
1
2
Op Code Address+ 1
Op Code Address+2
1
1
Operand Data
Next Op Code
1
2
3
Op Code Address + 1
Op Code Address+2
Op Code Address+3
1
1
1
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
1
2
3
Op Code Address+ 1
Address of Operand
Op Code Address+2
1
1
1
Address of Operand (LSB)
Operand Data
Next Op Code
1
2
3
1
2
3
Op Code Address+ 1
Destination Address
Op Code Address+2
Op Code Address+ 1
Address of Operand
Address of Operand + 1
Op Code Address+2
Op Code Address+ 1
Destination Address
Destination Address + 1
Op Code Address+2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer- 1
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
Op Code Address+3
Op Code Address + 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
Op Code Address+3
1
Destination Address
Accumulator Data
Next Op Code
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
2
3
3
3
ADDD
LDD
LDX
4
4
4
1
2
3
4
JSR
5
1
2
3
4
5
TIM
4
1
2
3
4
AIM
OIM
Data Bus
ElM
6
1
2
3
4
5
6
0
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
- Continued -
~HITACHI
Hitachi America Ltd_ • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
833
HD63P01Ml,HD63PA01Ml,HD63PB01Ml--------------------Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions
INDEXED
JMP
3
1
2
3
ADC
AND
CMP
LOA
SBC
TST
STA
ADD
BIT
EOR
ORA
SUB
4
4
ADDD
CPX
LOS
SUBD
LDD
LOX
5
1
2
3
4
1
2
3
4
1
2
3
4
5
STD
STX
STS
5
1
2
3
4
5
JSR
5
1
2
3
4
5
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
1
2
3
4
5
6
TIM
5
1
2
3
4
5
CLR
5
1
2
3
4
5
AIM
OIM
Data Bus
Address Bus
ElM
7
1
2
3
4
5
6
7
Op Code Address+ 1
FFFF
Jump Address
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address+2
1
1
1
1
1
1
1
Offset
Restart Address (LSB)
First Op Code of Jump Routine
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address+2
Op Code Address + 1
FFFF
IX + Offset
IX+Offset+ 1
Op Code Address+2
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset+ 1
Op Code Address+2
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-l
IX + Offset
Op Code Address+ 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address + 2
Op Code Address+ 1
Op Code Address+2
FFFF
IX+Offset
Op Code Address+3
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset
Op Code Address+2
Op Code Address+ 1
Op Code Address + 2
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+3
1
1
Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Immediate Data
Offset
Restar:t Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
00
1
1
1
1
1
1
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
0
1
- Continued -
834
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300 ,
--------------------HD63P01M1,HD63PA01M1,HD63PB01M1
Table 13 Cvcle-bv-Cvcle Operation (Continued)
Address Mode &
Instructions
Address Bus
EXTEND
JMP
3
ADC
AND
CMP
lOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
TST
4
1
2
3
1
2
3
4
4
1
2
3
4
ADDD
CPX
lOS
SUBD
STD
STX
lDD
lOX
5
1
2
3
4
5
STS
5
1
2
3
4
5
JSR
6
ASl
COM
INC
NEG
ROR
ASR
DEC
lSR
ROl
6
1
2
3
4
5
6
1
2
3
4
5
6
1
2
ClR
5
3
4
5
Data Bus
Op Code Address+ 1
Op Code Address + 2
Jump Address
Op Code Address+ 1
Op Code Address + 2
Address of Operand
Op Code Address + 3
1
1
1
1
1
1
1
Jump Address (MSB)
Jump Address (lSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data
Next Op Code
Op Code Address+ 1
Op Code Address+2
Destination Address
Op Code Address + 3
Op Code Address+ 1
Op Code Address+2
Address of Operand
Address of Operand + 1
Op Code Address+3
Op Code Address + 1
Op Code Address+2
Destination Address
Destination Address + 1
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
FFFF
Stack Pointer
Stack Pointer-1
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
Op Code Address+3
Op Code Address+ 1
Op Code Address + 2
Address of Operand
Address of Operand
Op Code Address+3
1
1
Destination Address (MSB)
Destination Address (lSB)
Accumulator Data
Next Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data (MSB)
Operand Data (lSB)
Next Op Code
Destination Address (MSB)
Destination Address (lSB)
Register Data (MSB)
Register Data (lSB)
Next Op Code
Jump Address (MSB)
Jump Address (lSB)
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data
Restart Address (lSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
0
00
1
Next Op Code
- Continued -
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
835
HD63P01M1,HD63PA01M1,HD63PB01M1--------------------
Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions
IMPLIED
ABA
ASl
ASR
ClC
ClR
COM
DES
INC
INX
lSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
PULA
ABX
ASlD
CBA
Cli
ClV
DEC
DEX
INS
lSR
ROl
NOP
SEC
SEV
TAP
TPA
TSX
XGDX
Address Bus
Op Code Address+ 1
1
Op Code Address+ 1
FFFF
Op Code Address+ 1
FFFF
Stack Pointer+ 1
Op Code Address+ 1
FFFF
Stack Pointer
Op Code Address+ 1
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-1
Op Code Address+ 1
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer+2
Return Address
Op Code Address + 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
2
PUlB
PSHB
4
2
1
2
3
1
2
3
4
PUlX
4
1
2
3
4
PSHX
5
1
2
3
4
5
RTS
5
1
2
3
4
5
MUl
1
2
3
7
836
1
Next Op Code
1
Next Op Code
Restart Address (lSB)
Next Op Code
Restart Address (lSB)
Data from Stack
Next Op Code
Restart Address (lSB)
Accumulator Data
Next Op Code
Next Op Code
Restart Address (lSB)
Data from Stack (MSB)
Data from Stack (lSB)
Next Op Code
Restart Address (lSB)
Index Register (lSB)
Index Register (MSB)
Next Op Code
Next Op Code
Restart Address (lSB)
Return Address (MSB)
Return Address (lSB)
First Op Code of Return Routine
Next Op Code
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
- Continued -
1
3
PSHA
1
Data Bus
4
5
6
7
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63P01Ml,HD63PA01Ml,HD63PB01Ml
Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
IMPLIED
WAI
9
1
2
3
4
5
6
7
8
9
RTI
10
1
2
3,
4
5
6
7
8
9
SWI
12
10
1
2
3
4
5
6
7
8
9
10
11
12
1
2
SLP
4
r
1
3
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer-3
Stack Pointer-4
Stack Pointer-5
Stack Pointer-6
Op Code Address+ 1
FFFF
Stack Pointer+ 1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4
Stack Pointer + 5
Stack Pointer + 6
Stack Pointer + 7
Return Address
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address+ 1
FFFF
FFFF
Sleep
4
FFFF
Op Code Address + 1
Data Bus
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator. A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (LSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (LSB)
First Op Code of SWI Routine
Next Op Code
Restart Address (LSB)
High Impedance-Non MPX Mod
Address Bus -MPX Mode
1
Restart Address (LSB)
Next Op Code
- Continued -
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
837
HD63P01M1,HD63PA01M1,HD63PB01M1-----------------------------------------
Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &.
Instructions
Address Bus
Data Bus
RELATIVE
BCC
BEQ
BGT
BLE
BLT
BNE
BRA
BVC
BSR
BCS
BGE
BHI
BLS
BMT
BPL
BRN
BVS
1
3
2
3
,
2
5
3
4
5
Op Code Address+ 1
FFFF
{BranCh Address······Test=·'"
Op Code Address+'··Test=·O"
1
1
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-1
Branch Address
1
1
• LOW POWER CONSUMPTION MODE
The HD63POIMI has two low power consumption modes;
sleep and standby mode.
Branch Offset
Restart Address (LSB)
First Op Code of Branch Routine
Next Op Code
1
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Op Code of Subroutine
0
0
1
CPU.
This sleep mode is available to reduce an average power
consumption in the applications of the HD63PO 1M 1 which may
not be always running .
• SleepMode
On execution of SLP instruction, the MCU is brought to the
sleep mode. In the sleep mode, the CPU sleeps (the CPU clock
becomes inactive), but the contents of the registers in the CPU
are retained. In this mode, the peripherals of CPU will remain
active. So the operations such as transmit and receive of the
SCI data and counter may keep in operation. In this mode,
the power consumption is reduced to about 1/6 the value of
a normal operation.
The escape from this mode can be done by interrupt, RES,
STBY. The RES resets the MCU and the STBY brings it into the
standby mode (This will be mentioned later). When interrupt is
requested to the CPU and accepted, the sleep mode is released,
then the CPU is brought in the operation mode and jumps to
the interrupt routine. When the CPU has masked the interrupt
after recovering from the sleep mode, the next instruction of
SLP starts to execute. However, in such a case that the timer
interrupt is inhibited on the timer side, the sleep mode cannot
be released due to the absence of the interrupt request to the
Standby Mode
Bringing "ST1JY "Low", the CPU becomes reset and all
clocks of the HD63POIMI become inactive. It goes into the
standby mode. This mode remarkably reduces the power consumptions of the HD63POIMl.
In the standby mode, if the HD63POIMI is continuously
supplied with power, the contents of RAM is retained. The
standby mode should escape by the reset start. The follOWing
is the typical application of this mode.
First, NM1 routine stacks the MCU's internal information and
the contents of SP in RAM, disables RAME bit of RAM control
register, sets the Standby bit, and then goes into the standby
mode. If the Standby bit keeps set on reset start, it means
that the power has been kept during standby mode and the
contents of RAM is normally guaranteed. The system recovery
may be possible by returning SP and bringing into the condition
before the standby mode has started. The timing relation for
each line in this application is shown in Figure 24.
•
Vee
~------~II~j----~r-
HD63P01M1
STay
I
I
r:-
-----11 ~:
L---I
I
~
I
I
~
o Stack registers
OsciUator I
o RAM control
:~~~lng
register set
~
restart
Figure 24 Standby Mode Timing
838
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - HD63P01M1,HD63PA01M1,HD63PB01M1
•
ERROR PROCESSING
When the HD63POlMI fetches an undefined instruction or
fetches an instruction from unusable memory area, it generates
the highest priority internal interrupt, that may protect from
system upset due to noise or a program error.
• Op-Code Error
Fetching an undefined op-code, the HD63POIM I will stack the
CPU register as in the case of a normal interrupt and vector to
the TRAP ($FFEE. $FFEF). that has a second highest priority
(RES is the highest).
•
Address Error
When an instruction is fetched from other than a resident
ROM, RAM, or an external memory area, the CPU starts the
same interrupt as op-code error. In the case which the instruction is fetched from external memory area and that area is not
usable, the address error cannot be detected.
The addresses which cause address error in particular mode
are shown in Table 14.
This feature is applicable only to the instruction fetch, not to
normal read/write of data accessing.
$
Table 14 Address Error
Mode
0
SOOOO
1
SOOOO
2,4
5
6
7
SOOOO
SOOOO
SOOOO
$0000
\
\
\
\
\
\
Address SOOIF SOOIF SOOIF S007F SOOIF S007F
S0200
SOIOO
\
\
$OFFF
$OFFF
System Flow chart ofHD63POIMI is shown in Fig. 25.
Transitions among the active mode, sleep mode, standby
mode and reset are shown in Fig. 26.
Figures 27, 28, 29 and 30 shows a system configuration.
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
839
HD63P01M1,HD63PA01M1,HD63PB01M1-----------------------------------------
PCl
~MSP
PCH"- MSP-1
IXL
~
MSP-2
IXH
~
MSP-3
ACCA -MSP-4
Aces -MSP-5
CCR
~
MSP-6
Figure 25 HD63P01M1 System Flow Chart
840
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - HD63P01M1,HD63PA01M1,HD63PB01M1
Figure 26 Transitions among Active Mode, Standby Mode,
Sleep Mode, and Reset
Vce
Vee
c:J
Enable
Enable
NMI
NMI·
IRO,
iRQ,
Port 3
8 Transfer
Lines
Port 1
81/0
Lines
Port 1
8110 Lines
Port 2
51/0 Lines
SCI
16 Bit Timer
Port 4
81/0 Lines
vss
VSS
Figure 27
Port 4
8110 Lines
Port 2
51/0 Lines
SCI
HD63P01 M1 MCU Single-Chip Dual Processor Configuration
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
841
HD63P01M1,HD63PA01M1,HD63PB01M1--------------------
HD63P01Ml
Enable
MCU
8
Address
Bus
Data
Bus
Address Bus
Figure 28 HD63P01 M1 MCU Expanded Non-Multiplexed Mode
(Mode 5)
Data Bus
Figure 29 HD63P01M1 MCU Expanded Multiplexed Mode
(Modes 2, 4 and 6)
HD63POl Ml MCU
16
Address Bus
Data Bus
Figure 30 HD63P01M1 MCU Expanded Non-Multiplexed Mode (Mode 1)
842
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63P01Ml,HD63PA01M1,HD63PB01M1
• PIN CONDITIONS AT SLEEP AND STANDBY STATE
• PRECAUTION TO THE BOARD DESIGN OF OSCILLATION CIRCUIT
As shown in Fig. 31, there is a case that the cross talk dis-
• Sleep State
The conditions of power supply pins (pins 1 and 21), clock
pins (pins 2 and 3), input pins (pins 4, 5, 6 and 7) and E clock
pin (pin 40) are the same as those of operation. Refer to Table
15 for the other pin conditions. Both address (Ao - A 12 ) and
chip enable (CE) for the EPROM are in "1" state.
• Standby State
__
Only power supply pins (pins 1 and 21) and STBY pin (pin 7)
are active. As for the clock pin EXTAL(pin3), its input is fIXed
internally so the MCV is not influenced by the pin conditions.
XTAL (pin 2) is in "1" output. All the other pins are in high
impedance. Both address (Ao - Ad and chip enable (CE) for
the EPROM are in "1" output.
turbs the nonnal oscillation if signal lines are put near the
oscillation circuit. When designing a board, pay attention to
this. Crystal and CL must be put as near the HD63P01M1
as possible.
HD63P01M1
Do not use this kind of print board design.
Figure 31
Precaution to the boad design of
oscillation circuit
Table 15 Pin Condition in Sleep Mode
~
Function
0
Pin
2,4
1
5
I/O Port
Lower Address Bus
I/O Port
+-
Keep the condition
just before sleep
Output "1"
Keep the condition
just before sleep
+-
7
6
...
...
...
...
+-
Port 1
P IO -P 17
Condition
Function
I/O Port
+-
+-
+-
Port 2
P20 -P 24
Condition
Keep the condition
just before sleep
+-
+-
+-
Function
E: Lower Address
Bus
E: Data Bus
Data Bus
E: Lower Address
Bus
E: Data Bus
Data Bus
E: Lower Address
Bus
E: Data Bus
Condition
E: Output "1"
E: High Impedance
High Impedance
E: Output "1"
E: High Impedance
High Impedance
Keep the condition
E: Output "1"
E: High Impedance just before sleep
Function
Upper Address
+-
Lower Address Bus
or Input Port
Upper Address Bus
or Input Port
...
Keep the condition
just before sleep
...
Output "1"
Port 3
P3o -P 37
Port 4
P40 -P 47
+-
Output "1"
+-
+-
Address Bus: Out·
put "1"
Port: Keep the condition just before
sleep
SC.
Output "1"
(Read Condition)
+-
+-
+-
SCI
Output Address
Strobe
+-
+-
Condition
Output "1"
Output Address
Strobe
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
+++-
I/O Port
I/O Port
Input Pin
843
HD63P01M1,HD63PA01M1,HD63PB01M1-----------------------------------------Table '6 Pin Condition during Reset
~
,
0
Pin
2,4
5
6
7
Port'
P iO - P17
high impedance (input)
•
•
•
•
•
Port 2
P20 - P24
high impedance (input)
•
•
•
•
•
Port 3
P30
-
P37
Port 4
P40 - P47
E: "'" output
E: "'" outputlN01el
(high impedance)
E:
high impedance
E:"l" output
E: "'" output INotel
(high impedance)
•
•
•
•
SC 2
"'" output (READ)
·
•
·•
·
·
SCI
E: "'" output
E: high impedance
•
•
•
"'" output
high impedance
(input)
•
"'" output
E: "'" output
E: high impedance
•
high impedance
(input)
•
In mode 0, 2, 4, 6, port 3 is set to "'" output state during E = "'" and it causes the conflict with the output of external memory. Following , and 2 should be done to avoid the conflict;
(,) Construct the system that disables the external memory during reset.
(2) Add 4.7kfl. pull-down resistance to the SC, pin (AS) to make SC, pin "0" level during E = "'''.
This operation makes port 3 high impedance state.
2_ Mode 6 (Expanded Multiplexed Mode)
Use 4k bytes of EPROM address space located from $FOOO
through $FFFF _ But do not use 4k bytes from $EOOO
through $EFFF because these addresses are internal for the
HD63POIM1, while these are external for the HD6301Vl.
3. Mode 1,2,4
No need to be careful, since ROM address is external in
these cases.
• PRECAUTION TO EMULATE THE HD6301V1 BY
HD63P01M1
The internal EPROM of the HD63POIMl provides 8k bytes
address space located from $EOOO through $FFFF _The followings should be noted to emulate the HD6301 VI (4k bytes
internal ROM) with the HD63POIMI.
1. Mode 5 (Expanded Non-multiplexed Mode) and Mode 7
(Single Chip Mode)
Use 4k bytes of EPROM address space located from $FOOO
through $FFFF.
HD63PO'M'
HD630'V'
$EOOO
$EOOO
Address
(EPROM)
$FFFF
}'""'""
Figure 32
844
high impedance
high impedance
(input)
Ao -A12 , CE "'" output
[Notel
"'''output
E: "'" output INotel
(high impedance)
$
l., " ,'
Add".
Internal Address
Address Map of Mode 6
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------HD63P01M1,HD63PA01M1,HD63PB01M1
•
PRECAUTION TO USE THE EPROM ON-PACKAGE
8 BIT SINGLE CHIP MICROCOMPUTER
Please pay attention to the followings, since this MeV has
special structure with pin socket on the package.
(l) Don't apply high static voltage or surge voltage over MAXIMUM RATINGS to the socket pins as well as the LSI pins.
If not, that may cause permanent damage to the device.
(2) When using 32k EPROM (24 pin), insert it on the mark side
and let the four above pins open.
•
PRECAUTION TO THE BOARD DESIGN OF OSCILLATION CIRCUIT
As shown in Fig. 33, there is a case that the cross talk disturbs the normal oscillation if signal lines are put near the oscillation circuit. When designing a board, pay attention to this.
Crystal and CL must be put as near the HD63POIMI as possible.
XTAL
4 Pins (On index side) open.
EXTAL
24 Pin EPROM should be inserted
on the mark side with 4 above open.
HD63P01M1
Do not use this kind of print board design.
Figure 33 Precaution to the boad design of
oscillation circuit
(3) When using this in production like mask ROM type single
chip microcomputer, pay attention to the followings to
keep the good contact between the EPROM pins and socket
pins.
(a) When soldering the LSI on a print circuit board, the
recommended condition is
Temperature: lower than 250°C
Time
' : within 10 sec.
(b) Note that the detergent or coating will not get in the
socket during flux washing or board coating alter
soldering, because that may cause bad effect on socket
contact.
(c) Avoid permanent application of this under the condition of vibratory place and system.
(d) The socket, inserted and pulled repeate<1ly lOses Its
contactability. It is recommended to use new one
when applied in production.
Ask our sales agent about anything unclear.
HD63P01M1
(Top view)
Figure 34
Example of Oscillation Circuits in Board Design
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
845
HD63P01M1,HD63PA01M1,HD63PB01M1----------------------------------------•
Table 17
RECEIVE MARGIN OF THE SCI
Receive margin of the SCI contained in the HD63P01M1
is shown in Table 17.
Note: SCI =Serial Communication Interface
START
1
2
3
4
Bit distortion tolerance
(t-tol Ito
Character distortion tolerance
(T-Tol ITo
±25%
±3.75%
5
6
8
STOP
Ideal Waveform
I.
Bit length r-to--j
Character length To
Real Waveform
I.
846
~t~
T
.1
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
HD63P05YO,HD63PA05YO,-HD63PB05YO
CMOS MCU (Microcomputer Unit)
The HD63POSYO is an CMOS 8-bit single-chip microcomputer unit which has a 4k-byte or 8k-byte EPROM on the
package. It is compatible with the HD630SYO except for ROM
which is not included in the HD63POSYO. It can be used not
only for debugging and evaluating the internal program of
HD630SXO or HD630SYO, but also for small-sized production
preceding mask ROM.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
FEATURES
Pin compatible with HD6305XO and HD6305YO
256-byte of RAM
A total of 55 terminals, including 32 110's, 7 inputs and 16
outputs.
Two timers
- B-bit timer with a 7-bit prescaler (programmable prescaler;
event counter)
- 15-bit timer (commonly used with the SCI clock divider)
On-chip serial interface circuit (synchronized with clock)
Six interrupts (two external, two timer, one serial and one
software)
Low power dissipation modes - Wait, Stop and Standby
Mode
Minimum instruction cycle time
HD63P05YO ...... 1 p.s (f = 1 MHz)
HD63PA05YO .... 0.67 p.s (f = 1.5 MHz)
HD63PB05YO ..... 0.5 p.s (f = 2 MHz)
Similar to HD6BOO instruction set
Bit manipulation
Bit test and branch
Versatile interrupt handling
Full set of conditional branches
New instructions - STOP, WAIT, DAA
Applicable to 4k or Bk bytes of EPROM
4k bytes; HN4B2732A
Bk bytes; HN4B2764, HN27C64
HD63P05YO, HD63PA05YO,
HD63PB05YO
(DC-64SP)
• PIN ARRANGEMENT
• TYPE OF PRODUCTS
Vss
r; 0
3
Bus Timing
Applied EPROM
HD63P05YO
1 MHz
HN4B2732A-30, HN4B2764-3, HN27C64-30
HD63PA05YO
1.5 MHz
HN4B2732A-30, HN4B2764-3, HN27C64-30
HD63PB05YO
2 MHz
HN4B2732A-25, HN4B2764, HN27C64-25
(Note)
EPROM is not attached to the MCU.
G2
1 G3
STBY 4
XTAL 5
EXTAL
NUM
G.
Gs
~
7
TIMER ~
o Vee
A7 ~
G6
G,
VeeO
F,
A6 ~
VeeO
As :;;
A. 12
Vee 0
OAs
As 0
A21
OAs
Ag 0
A"
F6
Fs
F.
F3
1 F2
F,
OA.
A" 0
B, 1
OA3
VssO
Fo
E,
B6 1
OA2
A,oO
E6
OA,
CEO
OAo
0,0
000
060
E2
E,
00,
05 0
1 Eo
Ao 1
Type No.
Go
G,
m~
iNl
Bs 1
B.
B3 21
B2 2
B, 2
Bo
C,/Tx
C6/Rx 26
Cs/c:K
7
002
O. 0
OVss
03 0
C. 8
C3
Es
E.
E3
D,
D6/TNTi
Os
7
D.
03
02
0,
C, ~
Co_~~__________~ Vee
(Top View)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
847
H D63P05YO,HD63PA05YO,HD63PB05YO----------------_ _ _ __
• BLOCK DIAGRAM
XTAl
EXTAl
RES
NUM
iN'f
S'i'iY
TIMER
Accumulator
8
A
Index
Register
Port A
1/0
Terminals
CPU
Control
x
~:
Condition Code
Register cc
0,
0,
0,
CPU
Stack
Pointer Sp
Program
Counter
"High" PCH
Program
Counter
Port B
1/0
Terminals
"Low"
0,
DeliNT,'"
AlU
PCl
Port D
Input
Terminals
Eo
E,
E,
E,
E.
E,
Port E
Output
Terminals
E.
E,
Port C
Fo
F,
1/0
Terminals
F,
F,
F.
F,
F.
F,
Serial
Data
Register
Go
G,
G,
G,
Serial
Status
Register
G.
Go
Port G
1/0
Terminals
Go
On Package
r----------.,
1
Port F
Output
Terminals
G,
1
Aol
All
AZI
::1
Asl
Aol
:;1
EPROM
HN482732Aj
HN482764
[ HN27C64
At l
Alol
Alii
AUI
"0£1
I
I
I
001
011
Ozl
031
0,1
Data
Input
Osl
001
I
L-______~--~:~~____~
IL _____ _
848
_...J
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63P05YO,HD63PA05YO,HD63PB05YO
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Supply voltage
Vee
-0.3 - +7.0
V
Input voltage
Yin
-0.3 - Vee + 0.3
V
Operating temperature
Storage temperature
[NOTE]
Topr
0-+70
°c
T stg
-55 - +150
°c
These products have a protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding,
be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normal
operation. we recommended Vln. Vout ; Vss ~ (Vin or Vout ) ~ Vee .
• ELECTRICAL CHARACTERISTICS
• DC Characteristics (Vee
=5.OV ± 10%, Vss =GND and Ta = 0 -
+70°C unless otherwise specified)
Test
condition
min
typ
max
Unit
Vee- 0.5
-
Vee+ 0.3
V
Vee x 0.7
-
Vee+ 0.3
V
2.0
-
Vee+ 0.3
V
-0.3
-
0.8
V
Operating
-
5
10
mA
Wait
-
2
5
mA
Stop
-
2
10
p.A
Standby
-
2
10
p.A
-
-
1
p.A
-
-
1
p.A
-
-
15
pF
Item
Symbol
RES.S'fBY
Input
voltage
"High"
EXTAL
VIH
Others
Input volt·
age "Low"
Current •••
dissipation
Input
leakage
current
All Input
VIL
lee
f
=1MHz*
TIMER.
TNT.
~D7'
Three·
state
current
Ao -A 7 ,
Bo - B 7 ,
Co -C 7 ,
Go -G 7 ,
Eo - E 7 ·*
Fo - F7**
Input
capacity
All
terminals
IIILI
Yin = 0.5-
IITSII
Cin
Vee - 0.5V
f = 1MHz,
Yin =OV
* The value at f = xMHz can be calculated by the following equation:
lec (f= xMHz) = lee (f= 1MHz) multiplied by x
•• At standby mode
••• All output and RES terminals are open (VIH min = Vee-1.OV. VIL max = O.8V). and ICC of EPROM is not included.
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
849
HD63P05YO,HD63PA05YO,HD63PB05YO---------------------• AC Characteristics (Vee
=5.0V ± 10%, VSS =GND and T. =0"" +70°C unless otherwise specified)
min
typ
HD63PA05YO
HD63PB05YO
max
min
typ
6
0.4
-
tcyc
+200
-
max
min
typ
-
10
0.5
Clock
frequency
fel
0.4
-
4
0.4
Cycle time
teye
1.0
-
10
0.666
Unit
max
8
MHz
10
IlS
-
ns
INT pulse
width
tlWL
te~e
+2 0
-
-
teye
+200
INT2 pulse
width
tlWL2
teye
+250
-
-
tcye
+200
-
-
tcye
+200
-
-
ns
RES pulse
width
tRWL
5
-
-
5
-
-
5
-
-
tcyc
TIMER pulse
width
tTWL
tcyc
+250
-
-
tcyc
+200
-
-
tcyc
+200
-
-
ns
Oscillation
start time
(crystal)
tose
-
-
20
-
-
20
-
-
20
ms
Reset delay
time
tRHL
80
-
-
80
-
-
80
-
-
ms
CL
= 22pF ±
200;6
Rs = 60n
max
External cap.
2.21lF
• Port Electrical Characteristics (Vee
=5.0V ± 10%, Vss =GND and Ta =0 -
Item
Symbol
Test
condition
=- 2OOIlA
IOH =-101lA
Ports A,
B,C,D,
G
Input volt·
age "Low"
Input leak·
age current
typ
max
Unit
2.4
-
-
V
-
-
V
-
-
0.55
V
VIH
2.0
-
Vee + 0.3
V
VIL
-0.3
-
0.8
V
-
-
1
IlA
IOL
VOL
Input volt·
age "High"
min
Vee - 0.7
VOH
Ports A,
B,C,G,
E, F
Output volt·
age "Low"
= 1.6mA
Vin =0.5Vee - 0.5V
IIILI
(Vee = 5.0V±10%, Vss =GND and Ta = 0 - +70°C unless otherwise specified)
SCI Timing
Item
Symbol
Clock cycle
tScye
Data output delay time
tTXD
Data set·up time
tSRX
Data hold time
tHRX
850
+70°C unless otherwise specified)
IOH
Output volt·
age "High"
•
HD63P05YO
Test
condition
Symbol
Item
Test
condition
Fig. 1,
Fig. 2
HD63P05YO
min
typ
1
-
-
-
200
100
HD63PA05YO
max
min
HD63PB05YO
typ
max
min
typ
max
-
16384
0.5
-
-
21845
250
250
-
-
-
200
-
-
200
-
-
100
-
-
100
32768 0.67
Unit
250
Ils
ns
-
ns
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
ns
- - - - - - - - - - - - - - - - - - - - - H D63P05YO,HD63PA05YO,HD63PB05YO
nected to these pins. For instance, in order to obtain the
system clock 1 MHz, a 4 MHz resonant fundamental crystal is
useful because the divide-by-4 circuitry is included. EXTAL
accepts an external clock input of duty 50% (±10%) to drive,
then the internal clock is a quarter the frequency of the
external clock. External drive frequency will be 4 or less times
the maximum internal clock. For external driving, no XTAL
should be connected. Refer to "INTERNAL OSCILLATOR"
for using these input pins.
Clock Output
C,/CK
Data Output
C,/TX
Data Input
Co/RX
eTIMER
Is an external input pin to control the internal Timer. For
details, see "TIMER".
Figure 1 SCI Timing (Internal Clock)
f-----
tscvc
----I
eRES
20V
Clock Input
Is used for resetting MCU. For details, see "RESET".
°av
C5/CK
eNUM
Data Output
24V
C,/Tx
Is not for user application. It must be grounded to Vss.
1I-'0:...:6:..:,.V-++-_ _ _ _....J ' -_ _ _- I I - - - -
t:-~X
Dat.lnput
CO/RX
tHRX.~
20V
r--
~OV
-----1l:.>!-.Q....,av'--____
°av
eINPUT/OUTPUT PINS (Ao-A?, Bo-B7, CO-C7, GO-G7)
32 pins consist of four 8-bit I/O ports (A, B, C, G). Each of
them is used as input or output pin, through program control
of the data direction register. For details, see "I/O PORTS".
I-----
elNPUT PINS (01 - 07)
Figure2 SCI Timing(External Clock)
Are 7 input-only pins compatible with the TTL and CMOS.
D6 is used as INT2. When the D6 is used as the port, set the
INT2 interrupt mask bit of the miscellaneous register to "1"
to prevent an INT2 from accidental interruption.
Vcc
TTL Load
(Port) .
IOL=1.6mA
2.4kQ
::,:itt o-----4I~--......--*--.
eOUTPUT PINS(Eo-f7,Fo-F7)
Are 16 output-only pins compatible with the TTL and
CMOS.
12kQ
40pF
eSTBY
[NOTES)
Used for bringing the MCU into the standby mode. With
STBY at "Low" level, the oscillation stops and internal situation is reset. Fore details, see "STANDBY MODE". The
following are I/O pins for serial communication interface
(SCI), and used as ports C5, C6, and C7. For details, see
"SERIAL COMMUNICATION INTERFACE".
1. The load capacitance includes stray capacitance caused
by the probe, etc.
2. All diodes are 152074
®.
eCK (Cs)
Used to input or output clocks when receiving or transmitting serial data.
Figure 3 Test Load
-DESCRIPTION ON PIN FUNCTIONS
Here is the description of HD63P05YO MCU input and
output signals.
eRx (C6)
eVee. Vss
Power is supplied to the MCU using these two pins. When
the operating voltage of the EPROM is 5.0V ± 5%, change Vee
according to that of EPROM.
eTx (C7)
eINT.INT2
Used for requesting an external interrupt to the MCU. For
details, see "INTERRUPT". The INT2 is used as the port D6
pin.
eXTAL, EXTAL
Are input pins to the internal clock circuit. A crystal
oscillator (AT cut, 2.0 to 8.0 MHz)or ceramic oscillator is con-
$
Used to receive serial data.
Used to transmit serial data.
-MEMORY MAP
The memory map of the HD63P05YO MCU is shown in
Fig. 4. During interrupt, the contents of the registers are saved
in the stack as shown in Fig. 5. The saving begins with the
lower byte (PCL) of the program counter. Then the stack
pointer value is decremented, and the higher byte (pC H)
of the program counter, index register (X), accumulator (A)
and condition code register (CC) are stacked in this order.
In subroutine calls, only the contents of the program counter
(pCH and PCL) are stacked.
HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
851
HD63P05YO,HD63PA05YO,HD63PB05YO---------------------
o
63
64
255
256
$0000
I/O Ports
Timer
SCI
$003F
~OO40
RAM
(192Bytes)
Stack
$gOFF
$ 100
RAM
(64Bytes)
\
$013F
319
320
$0140
PORT A
0
1
PORT B
2
PORT C
3
PORT D
4 PORT A DDR
5 PORT BOOR
6 PORT C DDR
7 PORT G DDR
8 Timer Data Reg
9 Timer CTRL Reg
10 Misc Reg
11
PORT E
12
PORT F
13 PORT G
EPROM
(7,872Bytes)
8182
819 1
8192
--------Interrupt
SOO
SOl
S02
$03'·
S04·
S05·
$06·
7
o
7
o
A
--11 Accumulator
I'--________
index
X
--1IRegister
I'--________
o
13
Program
I'--_ _ _ _ _ _ _PC_ _ _ _ _ _ _--'.ICounter
sor
13
$08
$09
$OA
SOB
SOC
SOD
6 5
~g~~~~
Not Used
$lFF6
Vectors
SlFFF
$2000
Zero
16 SCI CTRL Reg $10
17 SCI STS Reg $11
18 SCI Data Reg $12
'-----Negative
'------Interrupt
Mask
' - - - - - - - - Half
Carry
Not Used
Figure 6
Not Used
$3F
63
16383
$3FFF
I
76543210
Condition
Code Register
e Stack Pointer (SP)
The stack pointer is a 14-bit register which indicates the
address of the next free location in the stack. Initially, the
stack pointer is set to $OOFF. It is decremented as data is
pushed in, and incremented as it is pulled out. The upper 8
bits of the stack pointer are fixed to 00000011.
During an MCU reset or when the reset stack pointer (RSP)
instruction is executed, the pointer is set to the location
$OOFF. A subroutine or interrupt may be nested down to
location $OOC 1 which allows programmers to use up to 31
levels of subroutine call or 12 levels of interrupt response.
Pull
n+l
n-3
Accumulator
n+2
n-2
Index Register
n+3
n-1 0
01
n
PCW
n+4
eCondition Code Register (CC)
PCl-
Push
The condition code register is a 5-bit register. Each bit
indicates the result of the executed instruction. These bits
can be individually tested by conditional branch instructions .
The CC bits are as follows.
n+5
• In a subroutine call, only PCl and PCH are stacked.
Figure 5
Sequence of Interrupt Stacking
-REGISTERS
There are five registers which the programmers can handle.
e Accumulator (A)
The accumulator is a general purpose 8-bit register which
holds operands, the results of arithmetic operations or data
processing.
elndex Register (X)
The index register is an 8-bit register used for the index
addressing mode. It contains an 8-bit value to be added to an
instruction value to create an effective address. The index
register can also be used for data manipulations using the readmodify-write instruction. The index register may also be used
as a temporary storage area.
eProgram Counter (PC)
852
Programming Model
The program counter is a 14-bit register which contains the
address of the next instruction to be executed.
- Write only regi ster
- - Read only regis ter
Figure 4 Memory Map of HD63P05YO MCU
n-4 1 1 1
0
l~o~l~o~lo~l~ol~o~lo~l_l~l_l~1__S_p_~I~~~~r
Half Carry (H): Used to indicate a carry occurring between
bits 3 and 4 during an arithmetic operation
(ADD, ADC).
Interrupt (I): Setting this bit causes all interrupts to be
masked except for software ones. If an interrupt occurs while the bit I is set, the interrupt
is latched, and processed as soon as the
interru pt mask bit (I) is reset. (Exactly, the
interrupt enters the processing routine after
the instruction next to the CLI is executed.)
Negative (N): Used to indicate that the result of the latest
arithmetic operation, logical operation or data
processing is negative (Bit 7 is logical" 1").
Zero (Z):
Used to indicate that the result of the latest
arithmetic operation, logical operation or data
processing is zero.
Carry /Borrow Shows a carry or borrow occurring in the
(C):
latest arithmetic operation. This bit is also
affected by the Bit Test and Branch, Shift and
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - H D63P05YO,HD63PA05YO,HD63PB05YO
Rotate instructions.
Table 1
-INTERRUPT
Interrupt
There are six different types of interrupt: external interrupt (INT, INT2), internal timer interrupts (TIMER, TIMER
2), serial interrupt (SCI) and interrupt by an instruction (SWI).
Of these six interrupts, the INT2 and TIMER, and SCI and
TIMER 2 respectively generate the same vector address. When
an interrupt occurs, the program in execution stops and CPU
state at the interrupt is saved onto the stack. In addition, the
interrupt causes the interrupt mask bit (I) in the condition
code register to be set and obtains the start address of the
interrupt routine from an assigned interrupt vector address
before the interrupt routine starts frofu the state address. The
system exits from the interrupt routine by RTI instruction.
When the RTI instruction is executed, the CPU state before
the interrupt (saved in the stack) is pulled and the CPU starts
the program again from the next step to the interrupted one.
Table 1. lists the priority of interrupts and their vector
addresses.
m
Priority of Interrupts
Priority
Vector Address
1
$1FFE,
SWI
2
$1FFC,
$1FFD
INT
3
$1FFA,
$1FFB
$1FFF
TIMER/INT2
4
$1FF8,
$1FF9
SCI/TlMER2
5
$1FF6,
$1FF7
A flow chart of the interrupt is shown in Fig. 7. Also a
block diagram of the interrupt request source is shown in
~ 8. In the block diagram, both the external interrupts
INT and INT2 are edge trigger inputs. At the falling edge
of the input, an interrupt request is generated and latched.
The INT interrupt request is automatically cleared if a
program jumps to the INT routine. In the case of INT2, the
y
l1iIT
y
iNf2
y
1--+1
SFF--+SP
O--+DDR'S
CLR iNT Logic
SFF--+TDR
S7F--+Timer Prescaler
S50--+TCR
S3F ..... SSR
SOO--+SCR
S7F ..... MR
TIMER
Y
Figure 7
SCI
Interrupt Flowchart
interrupt request is cleared when "0" is written in bit 7 of
the miscellaneous register. For external interrupts(INT,INT2),
internal timer interrupts (TIMER, TIMER2) and serial interrupt (SCI), these interrupt requests are held, but not operated,
while bit I of the condition code register is set. Immediately
after the bit I is cleared, the corresponding interrupt is
activated.
The INT2 interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by bit 6 of the
timer control register, the SCI interrupt by bit 5 of the serial
status register and the TIMER2 interrupt by bit 4 of the serial
'
status register.
The state of the INT pin is tested by BIL or BIH instructions. The INT falling edge detector circuit and its latch circuit
are independent of tests by these instructions. The state of
INT2 pin is also independent.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
853
HD63P05YO,HD63PA05YO,HD63PB05YO--------------------Vectoring generated
$1 FFA. $1 FFB
BIH/BIL Test
Condition Code Register (CC)
INT Interrupt Latch
INT
I
Falling Edge Detector
I
Miscellaneous
Register (MR)
}-----4~I-----
Vectoring generated
$1 FF8. $1 FF9
TIMER
Serial Status
Register (SSR)
SCI/TIMER2
)--~----
Figure 8
•
Interrupt Request Generation Circuitry
Miscellaneous Register (MR: $OOOA)
The interrupt vector address for external interrupt INT2 is
the same as that for the TIMER interrupt, as shown in Table
1. For this reason, a special register called a miscellaneous
register (MR: $OOOA) is available for INT2 interrupt control.
Bit 7 of the miscellaneous register is of INT2 interrupt request
flag. When the falling edge is detected at the INT 2 pin, "1" is
set in bit 7. The software in the interrupt routine (vector
address: $IFF8, $IFF9) checks to see if it is INT2 interrupt.
Bit 7 is reset by software. Bit 6 is the INT2 interrupt mask
bit. If the bit is set to "1", the INT2 interrupt is disabled.
Miscellaneous Register (MR;$OOOAl
76543210
IMR71 MRS
IZlZlZlZlZlZJ
tt
L ----------
L......_ _ _ _ _ _ _ _ _ _ _
Vectoring generated
$1FF6.$1FF7
INT2 Interrupt Mask
INT2 Interrupt Request Flag
Both "READ" and "WRITE" are possible with bit 7, but
"1" can not be written to in this bit by software. Therefore,
interrupt requests by software are not possible. By resetting,
bit 7 is cleared and bit 6 is entered "1 ".
timer interrupt routine address from address $IFF8 and
$IFF9. The timer interrupt can be masked by setting the
timer interrupt mask bit (bit 6) in the timer control register.
The mask bit (I) in the condition code register can also disable
the timer interrupt. The source clock for the timer can be
either an external signal from the timer input pin or the
internal E signal (oscillator clock divided by 4). If the E
signal is selected as the source, the clock input can be gated
by the input to the timer input pin.
When the timer counter reaches "0", it starts counting
down from $FF. The count can be monitored at any time by
reading the timer data register. This function allows knowledge
of the length of time after a timer interrupt with a program,
without destroying the contents of the counter.
When the MCU is reset, both the prescaler and counter
return to the initial state of logical "1". At the same time,
the timer interrupt request bit (bit 7) is cleared and the timer
interrupt mask bit (bit 6) is set. Write "0" in the timer interrupt request bit (bit 7) to clear it.
TCR7
o
Timer interrupt request
Absent
Present
• TIMER
The MCU timer block diagram is shown in Fig. 9. The 8bit counter is loaded under program control and is decremented by the clock input. When the timer data register
(TOR) reaches 0, the timer interrupt request bit (bit 7) in the
timer control register is set. The MCU responds to this interrupt by saving the present CPU state in the stack, fetching the
854
TCR6
Timer interrupt mask
o
Enabled
Disabled
~HITACHI
Hitachi America Ltd_ • 2210 O'Toole Ave . • San Jose, CA 95131 • (408) 435-8300
---------------------HD63P05YO,HD63PA05YO,HD63PB05YO
After resetting, the TCR is initialized to "E under timer
terminal control" (bit 5 = 0, bit 4 = 1). If the timer terminal
is "1 ", the counter starts counting down with "$FF"
immediately after the reset.
• Timer Control Register (TCR; $0009)
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
Table 2
TCR
Timer Control Register (TCR; $0009)
4
3
2
0
L Prescaler division ratio selection
Prescaler initialize
L-_ _ _ _ _ _ _ _ Clock input source
L--_ _ _ _ _ _ _ _ _ _ Timer interrupt mask
L..-_ _ _ _ _ _ _ _ _ _ _ _ _ Timer interrupt request
Clock Source Selection
Clock input source
Bit 5
Bit 4
0
0
Internal clock E
0
1
E under timer terminal control
1
0
No clock input (counting stopped)
1
1
Event input from timer terminal
Initialize
(Internal
Clock)
E --+---1
Timer Data
Register
......_ _...,...._ _ _--._ _---J
Write
Figure 9
Table 3
Prescaler Division Ratio Selection
TCR
Prescaler division ratio
Bit 2
Bit 1
0
0
0
0
1
+2
0
1
0
+4
0
1
1
+8
1
0
0
+16
1
0
1
+32
1
1
0
+64
1
1
1
+128
Bit 0
0
+1
Timer Interrupt
Read
Timer Block Diagram
The prescaler is initialized by writing "1" in bit 3. The bit is
always "0", when "READ". A prescaler division ratio is
selected by a combination of the three bits (bits 0, 1 and 2)
of the timer control register (See Table 3). There are eight
division ratios; +1, +2, +4, +8, +16, +32, +64 and +128.
After resetting, the TCR returns to the + 1 mode. The timer
interrupt is enabled when the timer interrupt mask bit is "0",
and disabled when the bit is "1". When a timer interrupt
occurs, "1" is set in the timer interrupt request bit. The bit is
cleared by writing "0" into it.
-SERIAL COMMUNICATION INTERFACE (SCI)
Used for 8-bit data communication. Transfer rate ranges
from IllS to about 32 ms (when oscillated at 4 MHz), and there
are sixteen selections.
The SCI consists of three registers, one octal counter and
one prescaler. (See Fig. 10) The SCI communicates with the
CPU through the data bus, and with peripherals through bits
5, 6 and 7 of port C. Operations of the registers and data
transfer are described below.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
855
HD63P05YO,HD63PA05YO,HD63PB05YO--------------------SCI Control Registers (SCR; $0010)
E
_ ,. __li __,
Cs(CK)
.....-r-----..--"
Transfer
Clock
Generator
:
I
I
I
I
I
I
I
Initialize
I
Ce(Rx)
l
C7(Tx)
:
I _____ _
L
---.
I
SCI Status Registers
(SSR :$0011)
SCI/TlMER2
Figure 10
SCI Block Diagram
eSCI Control Register (SCR; $0010)
Bit 7 (SCR7)
When this bit is set, the DDR corresponding to the C 7
becomes "1" and this terminal serves for output of SCI data.
After resetting the bit is cleared to "0".
C7 terminal
SCR7
Bit 6 (SCR6)
When this bit is set, the DDR corresponding to the C6
becomes "0" and this terminal serves for input of SCI data.
After resetting the bit is cleared to "0".
Used as I/O terminal (by DDR).
o
Serial data output (DDR output)
C6 terminal
SCR6
o
Used as I/O terminal (by DDR).
Bits 5 and 4 (SCRS, SCR4)
These bits are used to select a clock source. After resetting
the bits are cleared to "0".
Bits 3 - 0 (SCR3 - SCRO)
These bits are used to select a transfer clock rate. After
resetting the bits are cleared to "0".
Serial data input (DDR input)
SCR5 SCR4
0
0
0
1
Clock source
-
C 5 terminal
Used as I/O terminal (by
DDR).
1
0
Internal
Clock output (DDR output)
1
1
External
Clock input (DDR input)
856
Transfer clock rate
SCR3
SCR2
0
0
0
0
1116
0
0
0
1
21l s
1.91 IlS
0
0
1
0
41l s
3.B21ls
0
0
1
1
Blls
7.641ls
I
I
I
I
I
I
1
1
1
1
3276BIls
1/32 s
SCR1
SCRO
4.00 MHz
4.194 MHz
0.95 1ls
~HITACHI
Hitachi America Ltd. • 2210 OToole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------HD63P05YO,HD63PA05YO,HD63PB05YO
eSCI Data R.gi.ter (SDR; $0012)
A serial-parallel conversion register that is used for transfer
of data.
• Data Transmission
By writing the desired control bits into the SCI control
registers, a transfer rate and a transfer clock source are determined and bits 7 and 5 of port C are set at the serial data
output terminal and the serial clock terminal, respectively.
The transmit data should be stored from the accumulator
or index register into the SCI data register. The data written
in the SCI data register is output from the C7/Tx terminal,
starting with the LSB, synchronously with the falling edge
of the serial clock (See Fig. 11). When 8 bits of data have been
transmitted, the interrupt request bit is set in bit 7 of the SCI
status register with the rising edge of the last serial clock. This
request can be masked by setting bit 5 of the SCI status register. Once the data has been sent, the 8th bit data (MSB)
stays at the C7/Tx terminal. If an external clock source has
been selected, the transfer rate determined by bits 0 to 3 of
the SCI control register is ignored, and the CS ICK terminal
is set as input. If the internal clock has been selected, the Cs I
CK terminal is set as output and clocks are output at the
transfer rate selected by bits 0 to 3 of the SCI control register.
eSCI Statu. R.gi.ter (SSR;$OO11)
Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set on completion of transmitting or receiving 8-bit data. It is cleared
when reset or data is written to or read from the SCI data
register with the SCRS=" 1". The bit can be cleared by writing
"0" into it.
Bit 6 (SSR6)
Bit 6 is the TIMER2 interrupt request bit. TIMER2 is commonly used with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When resetting, the
bit is cleared. It can also be cleared by writing "0" into it.
(For details, see TIMER2).
Bit 5 (SSRS)
Bit 5 is the SCI interrupt mask bit which can be set or
cleared by software. When it is "I", the SCI interrupt (SSR7)
is masked. When resetting, it is set to "1".
Bit 4 (SSR4)
Bit 4 is the TIMER2 interrupt mask bit which can be set
or cleared by software. When the bit is "1", the TIMER2
interrupt (SSR6) is masked. When resetting, it is set to "I".
Figure 11 SCI Timing Chart
• Data Reception
By writing the desired control bits into the SCI control
register, a transfer rate and a transfer clock source are determined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock terminal, respectively.
Then dummy-writing or -reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed after reading subsequent received data. It must be taken
after reset and after not reading subsequent received data.)
The data from the C6 /Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig. II). When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bit 5
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0 - 3 of the SCI
control register is ignored, and the data is received synchronously with the clock from the CS ICK terminal. If the internal
clock has been selected, the Cs/CK terminal is set as output
and clocks are output at the transfer rate selected by bits 0 3 of the SCI control register.
Bit 3 (SSR3)
When "I" is written into this bit, the prescaler of the transfer clock generator is initialized. When "READ", the bit is
always "0".
Bits 2 - 0
Not used.
SSR7
o
SCI interrupt request
Absent
Present
SSR6
TIMER2 interrupt request
o
Absent
Present
.TIMER2
SSR5
SCI interrupt mask
o
Enabled
Disabled
SSR4
o
TIMER2 interrupt mask
The SCI transfer clock generator can be used as a timer.
The clock selected by bits 3 to 0 of the SCI control register
(4 fJ.S to approx. 32 ms (when oscillated at 4 MHz» is input to
bit 6 of the SCI status register and the TIMER2 interrupt
request bit is set at each falling edge of the clock. Since interrupt requests occur periodically, TIMER2 can be used as a
reload counter or clock.
Enabled
Disabled
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
857
HD63P05YO,HD63PA05YO,HD63PB05YO - - - - - - - - - - - - - - - - - - - - ®@
L
CD
: Transfer
clock generator is reset and mask bit (bit 4
of SCI status register) is clea red.
interrupt request
@.@ : TIMER2 interrupt request bit cleared
c:
c:
~-..--.:......n5
(XTAU
"'-'-'--'--<16 (EXTAU
HD63P05YO
Figure 23 Precaution to the board design of
oscillation circuit
• PRECAUTION TO USE THE EPROM ON-PACKAGE 8-BIT
SINGLE-CHIP MICROCOMPUTER
Please be careful of the following, since this MCV has a
special structure with pin socket on the package.
(1) Don't apply high static voltage or surge voltage over
MAXIMUM RATINGS to the socket pins as well as the
LSI pins. If so, that may cause permanent damage to the
device.
(2) When using 32k EPROM (24-pin), insert it leaving the
four pins above open.
(3) When inserting this into system products like mask ROM
type single chip microcomputer, be careful of the following to give effective contact between the EPROM pins and
socket pins.
(a) When soldering the LSI onto a printed circuit board,
the recommended condition is
Temperature: lower than 250°C
Time:
within 10 sec.
(b) Be careful that detergent or coating does not get into
the socket during flux washing or board coating after
soldering, because that may cause bad effect on
socket contact.
(c) Avoid permanent application of this under conditions
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
863
HD63P05YO,HD63PA05YO,HD63PB05YO--------------------of continuous vibration.
(d) The socket, repeatedly inserted and removed, loses
its contactability. It is recommended to use new one
when used in production.
-BIT MANIPULATION
The HD63P05YO MCU can use a single instruction (BSET
or BCLR) to set or clear one bit of the RAM within page 0 or
an I/O port (except the write-only registers such as the data
direction register). Every bit of memory or I/O within page 0
(SOO ,.", $FF) can be tested by the BRSET or BRCLR instruction; depending on the result of the test, the program can
branch to required destinations. Since bits in the RAM on page
0, or I/O can be manipulated, the user may use a bit within the
RAM on page 0 as a flag or handle a single I/O bit as an
independent I/O terminal. Fig. 24 shows an example of bit
manipulation and the validity of test instructions. In the
example, the program is configured assuming that bit 0 of port
A is connected to a zero cross detector circuit and bit I of the
same port to the trigger of a triac.
The program shown can activate the triac within a time of
lOlls from zero-crossing through the use of only 7 bytes on
the memory. The on-chip timer provides a required time of
delay and pulse width mudulation of power is also possible.
SE IF 1.
Figure 24
BRClR 0, PORT A, SELF 1
BSET 1 , PORT A
BClR " PORT A
• Indexed (No Offset)
See Fig. 29. The indexed addressing mode allows access
up to the lower 255th address of memory. In this mode, an
instruction requires a length of one byte. The EA is the
contents of the index register.
• Indexed (8-bit Offset)
See Fig. 30. The EA is the contents of the byte following the operation code, plus the contents of the index register.
This mode allows access up to the lower 5 11 th address of
memory. Each instruction when used in the index addressing
mode (8-bit offset) requires a length of 2 bytes.
• Indexed (16-bit Offset)
See Fig. 31. The contents of the 2 bytes following the
operation code are added to content of the index register
to compute the value of EA. In this mode, the complete
memory can be accessed. When used in the indexed addressing mode (16-bit offset), an instruction must be 3 bytes long.
Example of Bit Manipulation
-ADDRESSING MODES
Ten different addressing modes are available to the
HD63P05YO MCU.
• Immediate
See Fig. 25. The immediate addressing mode provides
access to a constant which does not vary during execution of
the program.
This access requires an instruction length of 2 bytes. The
effective address (EA) is PC and the operand is fetched from
the byte that follows the operation code.
• Direct
See Fig. 26. In the direct addressing mode, the address of
the operand is contained in the 2nd byte of the instruction.
The user can gain direct access to memory up to the lower
255th address. 192 byte RAM and I/O registers are on page 0
of address space so that the direct addressing mode may be
utilized.
• Extended
See Fig. 27. The extended addressing is used for referencing to all addresses of memory. The EA is the contents of
the 2 bytes that follow the operation code. An extended
addressing instruction requires a length of 3 bytes.
864
• Relative
See Fig. 28. The relative addressing mode is used with
branch instructions only. When a branch occurs, the program
counter is loaded with the contents of the byte following the
operation code. EA = (PC) + 2 + ReI., where ReI. indicates a
Signed 8-bit data following the operation code. If no branch
occurs, ReI. = O. When a branch occurs, the program jumps
to any byte in the range + 129 to -127. A branch instruction
requires a length of 2 bytes.
• Bit Set/Clear
See Fig. 32. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
O. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte that follows the operation code
indicates an address within page O.
• Bit Test and Branch
See Fig. 33. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. Individual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relative value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code register.
• Implied
See Fig. 34. This mode involves no EA. All information
needed for execution of an instruction is contained in the
operation code. Direct manipulation on the accumulator
and index register is included in the implied addressing mode.
Other instructions such as SWI and RTI are also used in this
mode. All instructions used in the implied addressing mode
should have a length of one byte.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63P05YO,HD63PA05YO,HD63PB05YO
I
LE
=
A
I~
Memorv
I~_---lCA~
F8
Index Reg
I
Stack Point
PROG LOA lISF8 05BEt-:~~:::l~---------.J
Prog Count
05BF'"
05CO
t---:":~-f
CC
~
.
I
I
Figure 26
Example of Immediate Addressing
A
CATFCB32004B~:EL:~~----1_------~~---------1E;~20~;J
n ex
PROG LOA CAT
t-----.. .
06201-~~-t
062£
I
I
S
I
I
I
I
I
19
Stick 'ko:!':In:':"!- - - '
prog tun!
052F
cc
~
Figure 26
Example of Direct Addressing
Memory
0000
A
40
PROG LOA CAT
0409'-~;---"L
Index Reg
~:~:'--+'~-4
I
Stack Pomt
CATFCB6406E5t::J~::}_-------J
Prog Count
040C
CC
Figure 27
Example of Extended Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
865
HD63P05YO,HD63PA05YO,HD63PB05YO-----------_ _ _ _ _ _ _ _ __
A
PROG BEQ PROG2 04A 7 ...........".,,.......~
04AB
1--"":';;:"'---1
§
:
;
Figure 28
Example of Relative Addressing
Memory
A
TABLFCC
LlOOB8~:J4~C:::j----~~--------~---------{~34~C:::J
49
.
.
''''''' '"' , "" ~
B8
Stack POint
Prog Count
05F5
CC
~
,
Figure 29
,,
Example of Indexed (No Offset) Addressing
MeJorv
,
BF
86
DB
CF
TABL FCB II BF 0089
FCB .86 008A
FCB II DB 008B
FCB #CF OOSC
lEA
008C
,
I
/~
-r----"
I
:
:
E6
89
PROG LDA TABL X 075B
075C
L
I
I
I
I
A
CF
Inde< Reg
03
Stack POint
I
I
I
I
0750
I
Prog Count
cc
~
,
Figure 30
866
,
Example of index (8-bit Offset) Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • -(408) 435-8300
- - - - - - - - - - - - - - - - - - - - - H D 6 3 P 0 5 Y O , H D63PA05YO,HD63PB05YO
Memory
~.
.
PROG LOA TABL.X g:~;t---::~---t
0694
TABL
Prog <.;ount
0695
CC
1----1
:~: ::~ g;;~ ~::i:~~:::t-----------1
FCB II DB 0780.,.
DB
FCB IiCF 0781 ......___
CF___
Figure 31
Example of Index (lS·bit Offset) Addressing
Memory
i
U
I
I
pORTBeOU10001~1
BF
aa
I
BIt
6
0000
Inde. Reg
•
PROG BClR 6 PORT B 05BF
0590
I
I
10
01
prog Count
0591
CC
~
I,
:,
Figure 32
Example of Bit Set/Clear Addressing
PORT C EOU 2 0002 1 - - - - - 1
. . . .--t
PROG BRCLR 2.PORT C PROG 2 g~;:I-~
05761-~~-1
Figure 33
Example of Bit Test and Branch Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
867
H D63P05YO,HD63PA05YO,HD63PB05YO - - - - - - - - - - - - - - - - - - - - -
,
'"00 . ., " "
Memory
~
~
~
I
I
:
I
I
:
Figure 34
Example of Implied Addressing
-INSTRUCTION SET
There are 62 basic instructions available to the HD63P05YO
MeV. They can be classified into five categories: register/
memory, read/modify/write, branch, bit manipulation, and
control. The details of each instruction are described in
Tables 5 through II.
• Register/Memory Instructions
Most of these instructions use two operands. One operand
is either an accumulator or index register. The other is derived
from memory using one of the addressing modes used on the
MeV. There is no register operand in the unconditional jump
instruction (JMP) and the subroutine jump instruction (JSR).
See Table 5.
• Read/Modify/Write Instructions
These instructions read a memory or register, then modify
or test its contents, and write the modified value into the
memory or register. Zero test instruction (TST) does not
write data, and is handled as an exception in the read/modify/
write group. See Table 6.
868
• Branch Instructions
A branch instruction branches from the program sequence
in progress if a particular condition is established. See Table 7.
• Bit Manipulation Instructions
These instructions can be used with any bit located up to
the lower 255th address of memory. Two groups are available;
one for setting or clearing and the other for bit testing and
branching. See Table 8.
• Control Instructions
The control instructions control the operation of the MeV
which is executing a program. See Table 9.
• List of Instructions in Alphabetical Order
Table 10 lists all the instructions used on the MeV in the
alphabetical order.
• Operation Code Map
Table 11 shows the operation code map for the instructions
used on the MeV.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------HD63P05YO,HD63PA05YO,HD63PB05YO
Table 5
Register/Memory Instructions
Addressing Modes
Indexed
Mnemonic
Operations
Immediate
Extended
Direct
Indexed
OP II
- OP
II
- OP
II
-
OP II
-
OP II
-
OP II
-
Load A from Memory
LOA
A6
2
2
B6
2
3 C6 3
4
F6
1
3
E6
2
4
06 3
5
M~A
Load X from Memory
LOX
AE
2
2
BE
2
3 CE
3
4
FE
1
3
EE
2
4
DE 3
5
M-X
Store A in Memory
STA
B7
2
3- C7
3
4
F7
1
4
E7
2
4
07
3
5
A~M
Store X in Memory
STX
BF
2
3
CF
3
4
FF
1
4
EF
2
4
OF
3
5
X·-M
Add Memory to A
ADD
4
FB
1
3
EB
2
4 DB 3
5
A+M-·A
Add Memory and Carry
AB
2
2 BB 2 3 CB 3
- - - - t---
-- r-- .-
Condition
Code
Booleanl
Arithmetic
Operation
Indexed
(No Offset) (8·Bit OIIset) (16·Bit Offset)
H
/\
to A
AoC
A9
2
2
B9
2
3 C9
3
4
F9
1
3
E9
2
4
09 3
5
A+M+C~A
Subtract Memory
SUB
AO
2
2
BO
2
3 CO 3
4
FO
1
3
EO
2
4
DO 3
5
A-M~A
A with Borrow
SBC
A2
2
2
B2
2
3 C2
3
4
F2
1
3
E2
2
4
02 3
5
A-M-C-A
AND Memory to A
AND
A4
2
2
B4
2
3 C4 3
4
F4
1
3
E4
2
4 04 3
5
A·M~A
OR Memory with A
ORA
AA 2
2
BA 2
3 CA 3
4
FA
1
3
EA
2
4 oA 3
5
A+M-A
EOR
A8
2
2
BB
2
3 CB
3
4
F8
1
3
EB
2
4 DB 3
5
AGlM~A
CMP
Al
2
2
Bl
2
3 Cl
3
4
Fl
1 .3
El
2
4
01
3
5
A-M
CPX
A3
2
2
B3
2
3 C3 3
4
F3
1
3
E3
2
4
03 3
5
X-M
A (Logical Compare)
BIT
A5
2
2
B5
2
3 C5
3
4
F5
1
3
E5
2
4
05 3
5
A·M
Jump Unconditional
JMP
BC
2
2 CC
3
3
FC
1
2 EC
2
3 DC 3
4
Jump to Subroutine
JSR
Bo 2
5 CD 3
6
Fo
1
5 ED
2
5 DO 3
6
•
• •
/\
Subtract Memory from
·· ·••
·
··
Exclusive OR Memory
with A
Arithmetic Compare A
with Memory
N
Z
1\
1\
1\
/\
1\
1\
1\
/\
1\
/\
C
e
•
•
•
/\
/\
/\
1\
1\
1\
1\
1\
1\
/I
1\
1\
1\
/\
1\
•
•
•
··
·•
• •
•
•
•
·• ·• • • ·•
Arithmetic Compare X
with Memory
I
• ·•
• ·
• ·
•
e
Bit Test Memory with
1\
1\
1\
/\
1\
1\
1\
Symbols: Op = Operation
.# = Number of bytes
- = Number of cycles
Table 6
Read/Modify/Write Instructions
Addressing Modes
Indexed
Operations
Mnemonic
Increment
Imphed(A)
Implied(X)
OP II
OP II
INC
4C
1
2
5C
1
Direct
3C
Booleanl Arithmetic Operation
OP
II
-
OP II
-
2
5
7C
1
5
6C
2
6
A+l -A or X+l
OP II
2
Condition
Code
Indexed
(No Offset) (8·Bit Offset)
~X
or M+
I~M
or M-l
-~
Decrement
DEC
4A
1
2
5A
1
2
3A
2·
5
7A
1
5
6A
2
6
A-I -A or X-I
~X
Clear
CLR
4F
1
2
5F
1
2
3F
2
5
7F
1
5
6F
2
6
OO~A
or
Complement
COM
43
1
2
53
1
2
33
2
5
73
1
5
63
2
6
A-A or X-X or M~M
Negate
or
OO~X
OO-A -A or
(2·s Complement)
NEG
40
1
2
50
1
2
30
2
5
70
1
5
60 2
6
Rotate left Thru Carry
ROL
49
1
2
59
1
2
39
2
5
79
1
5
69
2
6
Rotate Right Thru Carry
ROR
46
1
2
56
1
2
36
2
5
76
1
5
66
2
6
~M
OO~M
I
•
•
•
•
•
•
•
•
Lb=t 11I I 1I I
L0=t I IAH",:ul Ibe~
AOf Xor
bo~
U
• •
• •
e
C
logical Shift Left
LSL
48
1
2
58
1
2
38
2
5
78
1
5
68
2
6
c
b,
bo
0
---bo
Logical Shift Right
LSR
44
1
2
54
1
2
34
2
5
74
1
5
64
2
6
Arithmetic Shift Right
ASR
47
1
2
57
1
2
37
2
5
77
1
5
67
2
6
Arithmetic Shift Left
ASL
48
1
2
58
1
2
38
2
5
78
1
5
68
2
6
Equal to LSL
TST
40
1
2
50
1
2 3D 2
4
70
1
4
60 2
5
A-OO or X-OO or M-OO
bo
C
C
:IIAH"':MI
I KJ
Test for Negative
or Zero
•
··
·
D-i 1~"':"r~ I 1 t0., b,1 H·~"':ul 1 1-0 •
lfb'
N
Z
C
/\
r-
1\
1\
•
•
•
0
1
/\
/\
1
r-
OO-X~X
OO-M~M
or
H
•
• •
e
• •
/\
1\
/\
/\
/\
A.
/\
"
/\
0
1\
/\
1\
1\
1\
1\
1\
1\
1\
1\
•
Symbols: Op - Operatton
# - Number of bytes
- - Number of cycles
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
869
HD63P05YO,HD63PA05YO,HD63PB05YO--------------------Table 7 Branch Instructions
Addressing Modes
Mnemonic
Operations
Relative
OP
~
-
Branch Always
BRA
20
2
3
None
Branch Never
BRN
21
2
3
None
Branch IF Higher
BHI
22
2
3
C+Z=O
Branch IF lower or Same
BlS
23
2
3
C+Z=1
Branch IF Carry Clear
BCC
24
2
3
C=O
(Branch IF Higher or Same)
(BHS)
24
2
3
C=O
BCS
25
2
3
C=1
Branch IF Carry Set
(BlO)
25
2
3
C=1
Branch IF Not Equal
BNE
26
2
3
Z=O
Branch IF Equal
BEQ
27
2
3
Z=1
Branch IF Half Carry Clear
BHCC
2B
2
3
H=O
Branch IF Half Carry Set
BHCS
29
2
3
H=1
Branch IF Plus
BPl
2A
2
3
N=O
Branch IF Minus
BMI
2B
2
3
N=1
BMC
2C
2
3
1=0
BMS
20
2
3
1=1
Bil
2E
2
3
INT=O
(Branch IF l------+t---'
90pF
12kQ
elnput Pins (01 '" 07)
Are 7 input-only pins compatible with the TTL and CMOS.
D6 is used as INT2. When the D6 is used as the port, set the
INT2 interrupt mask bit of the miscellaneous register to "1"
to prevent an INT2 from accidental interruption.
eEnable (E)
Supplies E clock. Output is a single-phase, TTL compatible
and 1/4 crystal oscillation frequency or 1/4 external clock
frequency. It can drive one TTL load and a 90pF condenser.
e Read/Write (RM)
[NOTES)
1. The load capacitance includes stray capacitance caused
by the probe. etc.
2. All diodes are 152074
®
Is an output pin compatible with the TTL. This indicates
to peripheral and memory devices whether MCU is in Read
("High"), or in Write ("Low"). The normal standby state is
Read ("High"). Its output can drive one TTL load and a
90pF condenser.
Figure 8 Test Load
eData Bus (DATAo '" DATA7)
Are three-state buffers compatible with the TTL. Each of
them can drive one TTL load and 90pF.
-DESCRIPTION ON PIN FUNCTIONS
Here is the description of HD63P05Yl MCU input and
output signals.
eVee, Vss
Power is supplied to the MCU using these two pins. When
the operating voltage of the EPROM is 5.0V ± 5%, change Vee
according to that of EPROM.
.
eINT,INT2
Used for requesting an external interrupt to the MCU. For
details, see "INTERRUPT". The INT2 is used as the port D6
pin.
eAddress Bus (ADRo '" ADRI3)
Are compatible with the TTL and can drive one TTL load
and 90pF.
eSTBY
Used for bringing the MCU into the standby mode. With
STBY at "Low" level, the oscillation stops and internal situation is reset. For details, see "STANDBY MODE". The following are I/O pins for serial communication interface (SCI), and
used as ports Cs, C6, and C7. For details, see "SERIAL
COMMUNICATION INTERFACE".
eCK (Cs)
eXTAL, EXTAL
Are input pins to the internal clock circuit. A crystal
oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic oscillator is connected to these pins. For instance, in order to obtain the
system clock 1 MHz, a 4 MHz resonant fundamental crystal is
useful because the divide-by-4 circuitry is included. EXT AL
accepts an external clock input of duty 50% (±1O%) to drive,
then the internal clock is a quarter the frequency of the
external clock. External drive frequency will be 4 or less times
the maximum internal clock. For external driving, no XTAL
should be connected. Refer to "INTERNAL OSCILLATOR"
for using these input pins.
eTiMER
Is an external input pin to control the internal Timer. For
details, see "TIMER".
eRES
Is used for resetting MCU. For details, see "RESET".
Used to input or output clocks when receiving or transmitting serial data.
eRx (C6)
Used to receive serial data.
eTx (C7)
Used to transmit serial data.
-MEMORY MAP
The memory map of the HD63P05Yl MCU is shown in
Fig. 9. During interrupt, the contents of the registers are saved
in the stack as shown in Fig. 10. The saving begins with the
lower byte (PCL) of the program counter. Then the stack
pointer value is decremented, and the higher byte (PCH)
of the program counter, index register (X), accumulator (A)
and condition code register (CC) are stacked in this order.
In subroutine calls, only the contents of the program counter
(pCH and PCL) are stacked.
eNUM
Is not for user application. It must be connected to Vee
through 1kn resistance.
elnput/Output Pins (Ao '" A7, Bo '" B7, Co '" C7)
24 pins consist of three 8-bit I/O ports (A, B, C). Each of
them is used as input or output pin, through program control
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
881
HD63P05Y1,HD63PA05Y1,HD63PB05Y1----------------------
o
63
64
255
256
319
320
$0000
1/0 Ports
Timer
SCI
$003F
RAM
(192Bytes)
~OO40
Stack
SgOFF
$ 100
RAM
(64Bytes)
\
$013F
0
1
2
PORT
PORT
PORT
PORT
3
4
5
6
A
B
C
D
PORT A DDR
PORT BOOR
PORT C DDR
I
Timer Data Reg
Timer CTRL Reg
Misc Reg
IAccumulator
A
7
I
X
13
I
Not Used
8
9
10
0
7
$00
$01
$02
$03"
$04"
$05"
$06"
I
PC
13
$08
$09
$OA
0
Iindex
Register
0
Program
Counter
0
Stack
Pomter
6 5
SP
10101010101011 111
$0140
EPROM
Not Used
~gm~~
(7,872Bytes)
8182
819 1
8192
I
--------Interrupt
$1FF6
$lFFF
$2000
Vector!::
16
17
18
SCI CTRL Reg
SCI STS Reg
SCI Data Reg
Not Used
31
3i
External
Memory Space
63
16383
External
Memory Space
Zero
$10
$11
$12
~---Negative
~-----Interrupt
Mask
l...------Half
Carry
$lF
$20
Figure 11
$3F
The program counter is a 14-bit register which contains the
address of the next instruction to be executed .
• Write only regis ter
•• Read only regis ter
$3FFF
• Stack Pointer (SP)
The stack pointer is a 14-bit register which indicates the
address of the next free location in the stack. Initially, the
stack pointer is set to $OOFF. It is decremented as data is
pushed in, and incremented as it is pulled out. The upper 8
bits of the stack pointer are fixed to 00000011.
During an MCU reset or when the reset stack pointer (RSP)
instruction is executed, the pointer is set to the location
$OOFF. A subroutine or interrupt may be nested down to
location $OOC 1 which allows programmers to use up to 31
levels of subroutine call or 12 levels of interrupt response.
Figure 9 Memory Map of HD63P05Yl MCU
7 6
I
5 4
n-4 1 1 1
3
2
Condition
Code Register
o
Pull
n+l
n-3
Accumulator
n+2
n-2
Index Register
n+3
PCW
n+4
n-l
0 01
Programming Model
.Condition Code Register (CC)
n
PCl"
n+5
The condition code register is a S-bit register. Each bit
indicates the result of the executed instruction. These bits
can be individually tested by conditional branch instructions .
The CC bits are as follows.
Push
• In a subroutine call, only PCl and PCH are stacked.
Figure 10 Sequence of Interrupt Stacking
• REGISTERS
There are five registers which the programmers can handle.
• Accumulator (A)
The accumulator is a general purpose 8-bit register which
holds operands, the results of arithmetic operations or data
processing.
.Index Register (X)
The index register is an 8-bit register used for the index
addressing mode. It contains an 8-bit value to be added to an
instruction value to create an effective address. The index
register can also be used for data manipulations using the read- .
modify-write instruction. The index register may also be used
as a temporary storage area.
• Program Counter (PC)
882
Half Carry (H): Used to indicate a carry occurring between
bits 3 and 4 during an arithmetic operation
(ADD, ADC).
Interrupt (I): Setting this bit causes all interrupts to be
masked except for software ones. If an interrupt occurs while the bit I is set, the interrupt
is latched, and processed as soon as the
interrupt mask bit (I) is reset. (Exactly, the
interrupt enters the processing routine after
the instruction next to the CLI is executed.)
Negative (N): Used to indicate that the result of the latest
arithmetic operation, logical operation or data
processing is negative (Bit 7 is logical "I ").
Zero (Z):
Used to indicate that the result of the latest
arithmetic operation, logical operation or data
processing is zero.
Carry /Borrow Shows a carry or borrow occurring in the
(C):
latest arithmetic operation. This bit is also
affected by the Bit Test and Branch, Shift and
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - H D63P05Yl ,HD63PA05Yl ,HD63PB05Yl
Rotate instructions.
Table 1
-INTERRUPT
There are six different types of interrupt: external interrupt (INT, INT2), internal timer interrupts (TIMER, TIMER
2), serial interrupt (SCI) and interrupt by an instruction (SWI).
Of these six interrupts, the INT2 and TIMER, and SCI and
TIMER 2 respectively generate the same vector address. When
an interrupt occurs, the program in execution stops and CPU
state at the interrupt is saved onto the stack. In addition, the
interrupt causes the interrupt mask bit (I) in the condition
code register to be set and obtains the start address of the
interrupt routine from an assigned interrupt vector address
before the interrupt routine starts from the state address. The
system exits from the interrupt routine by RTI instruction.
When the RTI instruction is executed, the CPU state before
the interrupt (saved in the stack) is pulled and the CPU starts
the program again from the next step to the interrupted one.
Table I. lists the priority of interrupts and their vector
addresses.
Interrupt
RES
Priority of Interrupts
Priority
Vector Address
1
$1FFE,
$1FFF
SWI
2
$1FFC,
$1FFD
INT
3
$1FFA,
$1FFB
TIMER/INT2
4
$1FF8,
$1FF9
SCI/TIMER2
5
$1FF6,
$1FF7
A flow chart of the interrupt is shown in Fig. 12. Also a
block diagram of the interrupt request source is shown in
Fig. 13. I~e block diagram, both the external interrupts
INT and INT2 are edge trigger inputs. At the falling edge
of the input, an interrupt request is generated and latched.
The INT interrupt request is automatically cleared if a
program jumps to the INT routine. In the case of INT2, the
y
TNT
y
1..... 1
$FF ..... SP
TIMER
O..... DDR·S
CLR INT Logic
SFF ..... TDR
S7F .....Timer Prescaler
S50 ..... TCR
S3F ..... SSR
Y
SCI
SOO .....SCR
S7F ..... MR
Figure 12 Interrupt Flowchart
interrupt request is cleared when "0" is written in bit 7 of
the miscellaneous register. For external interrupts(INT,INT2),
internal timer interrupts (TIMER, TIMER2) and serial interrupt (SCI), these interrupt requests are held, but not operated,
while bit I of the condition code register is set. Immediately
after the bit I is cleared, the corresponding interrupt is
activated.
The INT2 interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by bit 6 of the
timer control register, the SCI interrupt by bit 5 of the serial
status register and the TIMER2 interrupt by bit 4 of the serial
status register.
~
The state of the INT pin is tested by BIL or BIH instructions. The INT falling edge detec~or circuit and its latch circuit
are independent of tests by thesl! instructions. The state of
INT2 pin is also independent.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
883
HD63P05Y1,HD63PA05Y1,HD63PB05Y1---------------------Vectoring generated
$1 FFA. $1 FFB
BIH/BIL Test
Condition Code Register (CC)
INT Interrupt Latch
INT
Falling Edge Detector
I
"\---4~I-----
Vectoring generated
$1FFB.$1FF9
TIMER
Serial Status
Register (SSR)
)---~---
Vectoring generated
$1 FF6. $1 FF7
Figure 13 I nterrupt Request Generation Circu itry
•
Miscellaneous Register (MR: $OOOA)
The interrupt vector address for external interrupt INT2 is
the same as that for the TIMER interrupt, as shown in Table
I. For this reason, a special register called a miscellaneous
register (MR: $OOOA) is available for INT2 interrupt control.
Bit 7 of the miscellaneous register is of INT2 interrupt request
flag. When the falling edge is detected at the INT 2 pin, "I" is
set in bit 7. The software in the interrupt routine (vector
address: $IFF8, $IFF9) checks to see if it is INT2 interrupt.
Bit 7 is reset by software. Bit 6 is the INT2 interrupt mask
bit. If the bit is set to "I", the INT2 interrupt is disabled.
Miscellaneous Register (MR;$OOOAI
76543210
IMR7lMR61ZIZIZVVJZI
f
-
.
INT2
t~----------INT2
Interrupt Mask
Interrupt Request Flag
Both "READ" and "WRITE" are possible with bit 7, but
"I" can not be written to in this bit by software. Therefore,
interrupt requests by software are not possible. By resetting,
bit 7 is cleared and bit 6 is entered "I".
timer interrupt routine address ·from address $IFF8 and
$1 FF9. The timer interrupt can be masked by setting the
timer interrupt mask bit (bit 6) in the timer control register.
The mask bit (I) in the condition code register can also disable
the timer interrupt. The source clock for the timer can be
either an external signal from the timer input pin or the
internal E signal (oscillator clock divided by 4). If the E
signal is selected as the source, the clock input can be gated
by the input to the timer input pin.
When the timer counter reaches "0", it starts counting
down from $FF. The count can be monitored at any time by
reading the timer data register. This function allows knowledge
of the length of time after a timer interrupt with a program,
without destroying the contents of the counter.
When the MeU is reset, both the prescaler and counter
return to the initial state of logical "I". At the same time,
the timer interrupt request bit (bit 7) is cleared and the timer
interrupt mask bit (bit 6) is set. Write "0" in the timer interrupt request bit (bit 7) to clear it.
TCR7
o
Absent
Present
• TIMER
The MCU timer block diagram is shown in Fig. 14. The 8bit counter is loaded under program control and is decremented by the clock input. When the timer data register
(TOR) reaches 0, the timer interrupt request bit (bit 7) in the
timer control register is set. The MCU responds to this interrupt by saving the present CPU state in the stack, fetching the
884
Timer interrupt request
TCA6
o
Timer interrupt mask
Enabled
Disabled
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - HD63P05Y1 ,H D63PA05Y1 ,H D63PB05Y1
After resetting, the TCR is initialized to "E under timer
terminal control" (bit 5 = 0, bit 4 = 1). If the timer terminal
is "1", the counter starts counting down with "$FF"
immediately after the reset.
• Timer Control Register (TCR; $0009)
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
Table 2
TCR
Timer Control Register (TCR; $0009)
L -_ _ _ _ _ _ _ _ _ _
Bit 5
Bit 4
0
0
Clock Source Selection
Clock input source
Internal clock E
0
1
E under timer terminal control
1
0
No clock input (counting stopped)
1
1
Event input from timer terminal
Timer interrupt mask
' - - - - - - - - - - - - - - - Timer interrupt request
Initialize
(Internal
Clock)
E --+---1
Timer Data
Register
L-_ _...,...._ _ _......,._ _......J
Write
Timer Interrupt
Read
Figure 14 Timer Block Diagram
Table 3
The prescaler is initialized by writing" 1" in bit 3. The bit is
always "0", when "READ". A prescaler division ratio is
selected by a combination of the three bits (bits 0, 1 and 2)
of the timer control register (See Table 3). There are eight
division ratios; +1, +2, +4, +8, + 16, +32, +64 and + 128.
After resetting, the TCR returns to the + 1 mode. The timer
interrupt is enabled when the timer interrupt mask bit is "0",
and disabled when the bit is "1". When a timer interrupt
occurs, "1" is set in the timer interrupt request bit. The bit is
cleared by writing "0" into it.
.
Prescaler Division Ratio Selection
TCR
Bit 2
Bit 1
0
0
0
0
BitO
Prescaler division ratio
0
+1
0
1
+2
1
0
+4
0
1
1
+8
1
0
0
+16
1
0
1
+32
1
1
0
+64
1
1
1
+128
-SERIAL COMMUNICATION INTERFACE (SCI)
Used for 8-bit data communication. Transfer rate ranges
from Ip.s to about 32 ms (when oscillated at 4 MHz), and there
are sixteen selections.
The SCI consists of three registers, one octal counter and
one prescaler. (See Fig. 15) The SCI communicates with the
CPU through the data bus, and with peripherals through bits
5, 6 and 7 of port C. OperatiollS of thc rCl(istcrs and data
transfer are described below.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
885
HD63P05Yl,HD63PA05Yl,HD63PB05Yl--------------------SCI Control Registers (SCR; $0010)
E
'--.,....-'---.--'
Transfer
Clock
Generator
Initialize
SCI Status Registers
(SSR :$0011)
SCI/TlMER2
Figure 15 SCI Block Diagram
-SCI Control Register (SCR; $0010)
Bit 7 (SCR7)
When this bit is set, the DDR corresponding to the C7
becomes "I" and this terminal serves for output of SCI data.
After resetting the bit is cleared to "0".
C 7 terminal
SCR7
Bit 6 (SCR6)
When this bit is set, the DDR corresponding to the C6
becomes "0" and this terminal serves for input of SCI data.
After resetting the bit is cleared to "0".
Used as I/O terminal (by DDR).
o
Serial data output (DDR output)
SCR6
C6 terminal
o
Used as 1/0 terminal (by DDR).
Bits 5 and 4 (SCRS, SCR4)
These bits are used to select a clock source. After resetting
the bits are cleared to "0".
Bits 3 -- 0 (SCR3 -- SCRO)
These bits are used to select a transfer clock rate. After
resetting the bits are cleared to "0".
Serial data input (DDR input)
SCR5 SCR4
0
0
0
1
Clock source
-
C s terminal
Used as I/O terminal (by
DDR).
1
0
Internal
Clock output (DDR output)
1
1
External
Clock input (DDR input)
886
SCR3
SCR2
a
a
a
a
a
a
SCRl
SCRa
Transfer clock rate
4.aaMHz
4.194 MHz
a
lps
a.95ps
a
1
2ps
1.91ps
0
1
0
4ps
3.82ps
0
0
1
1
8ps
7.64ps
I
I
I
I
I
I
1
1
1
1
32768ps
1/325
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - H D63P05Y1,H D63PA05Y1,H D63PB05Y1
eSCI Dati Regi.ter (SDR; $0012)
A serial-parallel conversion register that is used for transfer
of data.
eSCI Stltu. Regi.ter (SSR; $0011)
Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set on completion of transmitting or receiving 8-bit data. It is cleared
when reset or data is written to or read from the SCI data
register with the SCRS=" 1". The bit can be cleared by writing
"0" into it.
Bit 6 (SSR6)
Bit 6 is the TIMER2 interrupt request bit. TIMER2 is commonly used with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When resetting, the
bit is cleared. It can also be cleared by writing "0" into it.
(For details, see TIMER2).
• Data Transmission
By writing the desired control bits into the SCI control
registers, a transfer rate and a transfer clock source are determined and bits 7 and S of port C are set at the serial data
output terminal and the serial clock terminal, respectively.
The transmit data should be stored from the accumulator
or index register into the SCI data register. The data written
in the SCI data register is output from the C7/Tx terminal,
starting with the LSB, synchronously with the faIling edge
of the serial clock (See Fig. 16). When 8 bits of data have been
transmitted, the interrupt request bit is set in bit 7 of the SCI
status register with the rising edge of the last serial clock. This
request can be masked by setting bit S of the SCI status register. Once the data has been sent, the 8th bit data (MSB)
stays at the C7/Tx terminal. If an external clock source has
been selected, the transfer rate determined by bits 0 to 3 of
the SCI control register is ignored, and the Cs/CK terminal
is set as input. If the internal clock has been selected, the Cs /
CK terminal is set as output and clocks are output at the
transfer rate selected by bits 0 to 3 of the SCI control register.
Bit S (SSRS)
Bit S is the SCI interrupt mask bit which can be set or
cleared by software. When it is "I", the SCI interrupt (SSR7)
is masked. When resetting, it is set to "1".
Bit 4 (SSR4)
Bit 4 is the TIMER2 interrupt mask bit which can be set
or cleared by software. When the bit is "1", the TIMER2
interrupt (SSR6) is masked. When resetting, it is set to "1":
Bit 3 (SSR3)
When "1" is written into this bit, the prescaler of the transfer clock generator is initialized. When "READ", the bit is
always "0".
Bits 2 - 0
Not used.
SSR7
o
SCI interrupt request
Absent
Present
SSR6
TIMER2 interrupt request
o
Absent
Present
SSR5
o
SCI interrupt mask
Enabled
Disabled
SSR4
o
TIMER2 interrupt mask
Figure 16 SCI Timing Chart
• Data Reception
By writing the desired control bits into the SCI control
register, a transfer rate and a transfer clock source are determined and bit 6 and S of port C are set at the serial data
input terminal and the serial clock terminal, respectively.
Then dummy-writing or -reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed after reading subsequent received data. It must be taken
after reset and after not reading subsequent received data.)
The data from the C6 /Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig. 16). When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bit S
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0 - 3 of the SCI
control register is ignored, and the data is received synchronously with the clock from the Cs/CK terminal. If the internal
clock has been selected, the CS ICK terminal is set as output
and clocks are output at the transfer rate selected by bits 0 3 of the SCI control register .
• TIMER2
The SCI transfer clock generator can be used as a timer.
The clock selected by bits 3 to 0 of the SCI control register
(4 fJ.s to approx. 32 ms (when oscillated at 4 MHz» is input to
bit 6 of the SCI status register and the TIMER2 interrupt
request bit is set at each falling edge of the clock. Since interrupt requests occur periodically, TIMER2 can be used as a
reload counter or clock.
Enabled
Disabled
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
887
HD63P05Y1,HD63PA05Y1,HD63PB05Y1----------------------
CD
®@..---__@;;:;,4@
-----LJ~~t
--J
CD
input must be held "Low" for at least tosc to assure that the
internal oscillator is stabilized. A sufficient delay time can
be obtained by connecting a capacitance to the RES input as
shown in Fig. 19.
L
: Transfer
clock generator is reset and mask bit (bit 4
of SCI status register) is clea red.
®.@ : TIMER2 interrupt request
@.@ : TIMER2 interrupt request bit cleared
5V
Vcc
OV
TIMER2 is commonly used with the SCI transfer clock
generator. If wanting to use TIMER2 independently of the
SCI, specify "External" (SCRS = 1, SCR4 = 1) as the SCI
clock source.
If "Internal" is selected as the clock source, reading or
writing the SDR causes the prescaler of the transfer clock
generator to be initialized.
RES
Terminal
---------f"V""'VIH RES
---
tRHl
I---
Internal
Reset - - - -_ _ _ _ _ _.....J
Figure 18
Power On and Reset Timing
-I/O PORTS
There are 24 input/output terminals (ports A, B, C). Each
I/O terminal can be selected for either input or output by the
data direction register. Specifically, an I/O port will be input
if "0" is written in the data direction register, and output if
"1" is written in the data direction register. Port A, B or C
reads latched data if it has been programmed as output, even
with the output load, the output level fluctuating. (See Fig.
17).
When resetting the data direction register and data register
go to "0" and all input/output terminals are used as input.
Seven input-only terminals are available (port D). Writing
to these ones is invalid.
All input/output terminals and input terminals are TTL
compatible and CMOS compatible in respect of both input
and output.
If I/O ports or input ports are not used, they should be
connected to VSS via resistors. With none connected to these
terminals, there is the possibility of power being consumed
despite their not being used.
HD63P05Y1
MCU
Figure 19
Input Reset Delay Circuit
-INTERNAL OSCILLATOR
The internal oscillator circuit is designed to meet the
1-----4.....-6~ EXTAL
JO-':OMH<= 5 XTAL
HD63P05Y1
MCU
10-22pF!20%
Crystal Oscillator
HD63P05Y1
MCU
Bit of data
direction
register
Bit of
output
data
Status of
output
Input to
MCU
1
0
0
0
1
1
1
1
0
X
Figure 17
3·state
External
Ceramic Oscillator
Clock
Input 6 EXTAL
NC 5 XTAL
Pin
MCU
Input/Output Port Diagram
-RESET
The MCV can be reset either by external reset input (RES)
or power-on reset. (See Fig. 18). On power up, the reset
888
HD63P05Y1
External Clock Drive
Figure 20
Internal Oscillator Circuit
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - HD63P05Y1 ,HD63PA05Y1 ,HD63PB05Y1
requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 - 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the required oscillation frequency stability.
Three different terminal connections are shown in Fig. 20.
Figs. 21 and 22 illustrate the specifications and typical arrangement of the crystal.
C,
s
C~
XTAl
EXTAl
~
5
Figure 21
6
AT Cut
Parallel
Resonance
Co=7pF max.
f=2.0-S.0MHz
Rs=600 max.
Parameters of Crystal
(a)
[NOTE I Use as short wirings as possible for connection of the crvstal
with the EXTAL and XTAL terminals. Do not allow these
wirings to cross others.
Figure 22
Typical Crystal Arrangement
-LOW POWER DISSIPATION MODE
The HD63P05Yl has three low power dissipation modes:
wait, stop and standby.
.Wait Mode
When a WAIT instruction being executed, the MCU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication interface - stay active. (NOTE: Once the system has entered the
wait mode, the serial communication interface can no longer
be retriggered.) In the wait mode, the registers, RAM and I/O
terminals hold the condition just before entering the wait
mode. Both address (Ao - Au) and chip enable (CE) for the
EPROM are in "1" state.
Release from this mode can be done by interrupt (lNT,
TIMER/INTl or SCI/TIMER2), RES or STBY. The RES
resets the MCU and the STBY brings it into the standby
mode. (This will be mentioned later.)
When interrupt is requested to the CPU and accepted. the
wait mode is released and the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit of the condition code register, after release
from the wait mode the MCU executes the instruction following WAIT. If an interrupt other than the INT (i.e., TIMER/
INT2 or SCI/TIMER2) is masked by the tiPlpr ~ontrol re-
gister, miscellaneous register or serial status register, there
is no interrupt request to the CPU, so the wait mode cannot
be released.
Fig. 23 shows a flowchart of the wait function.
• Stop Mode
When STOP instruction is being executed, the MCU enters
the stop mode. In this mode, the oscillator stops and the CPU
and peripheral functions become inactive but the RAM,
register and I/O terminals hold the condition they had just
before entering the stop mode. Both address (Ao - A12) and
chip enable (CE) for the EPROM are in "1" state.
Release from this mode can be done by an external interrupt (INT or INT2), RES or STBY. The RES resets the MCU
and the STBY brings it into the standby mode.
When an interrupt is requested and accepted by the CPU,
the stop mode is released and the CPU is brought in the operation mode and vectors to the interrupt routine. If the interrupt is masked by the I bit of the condition corle register,
after release from the stop mode, the MCU executes the
instruction following STOP. If the INT2 interrupt is masked
by the miscellaneous register, there is no interrupt request to
the MeU, so the stop mode cannot be released.
Fig. 24 shows the flowchart of the stop function. Fig. 25
shows a timing chart of the return to the operation mode
from the stop mode.
For releasing from the stop mode by an interrupt, oscillation starts upon input of the interrupt and, after the internal
delay time for stabilized oscillation, the CPU becomes active.
For restarting by RES, oscillation starts when the RES goes
"0" and the CPU restarts when the RES goes" 1" .. The duration of RES="O" must exceed tosc to assure stabilized oscillation.
• Standby Mode
__
The MCU enters the standby mode when the STBY terminal
goes "Low". In this mode, all operations stop and the internal
condition is reset but the contents of the RAM are held. The
I/O terminals turn to high-impedance state. Both address (Ao
- A12) and chip enable (CE) for the EPROM are in "1"
state. The standby mode should be released by bringing
STBY "High". The CPU must be restarted by resetting. The
timing of input signals at the RES and STBY terminals is
shown in Fig. 26.
Table 4 lists the status of each parts of the MCU in each
low power dissipation modes. Transitions between each mode
are shown in Fig. 27.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
889
H D63P05Y1, H D63PA05Y1,H D63PB05Y1 - - - - - - - - - - - - - - - - - - - - -
Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop
Initialize
CPU, TIMER. SCI,
I '0 and All
Other Functions
No
No
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 23
890
Wait Mode Flow Chart
$HITACfll
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - H D63P05Yl ,HD63PA05Yl,H D63PB05Yl
Oscillator and
All Clocks Stop.
No
Turn on Oscillator
Wait for Time Delay
to Stabilize
Turn on Oscillator
Wait for Time Delay
to Stabilize
1=0
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 24
Stop Mode Flow Chart
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
891
HD63P05Y1,HD63PA05Y1,HD63PB05Y1---------------------
O.:.'~.~:~~~~~~~
!
t
STOP instruction
executed
Interrupt
Time required for oscillation to become
stabilized (built-in delay time)
restart
(a) Restart by Interrupt
Oscillator 11111111111111111111111111111
E
~~-+__~
Time required for oscillation to become
stabilized (toscl
STOP instruction
executed
RES
(b) Restart by Reset
Figure 25
Timing Chart of ReleaSing from Stop Mode
\L...------.,H}--_~I
i
I
I
I
I
I
~-~
__IL __ I
~~
___
~~
___
~~
___
~
_________4-____________. J
tosc
Figure 26
Table 4
Restart
Timing Chart of Releasing from Standby Mode
Status of Each Part of MCU in Low Power Dissipation Modes
Condition
Mode
Start
WAIT
Software
STOP
Standby
892
Hardware
Escape
Oscillator
CPU
Timer,
Serial
Register
RAM
I/O
terminal
WAIT instruction
Active
Stop
Active
Hold
Hold
Hold
STBY, RES, INT, IN1 2 ,
each interrupt request of
TIMER, TIMER~, SCI
STOP instruction
Stop
Stop
Stop
Hold
Hold
Hold
STBY, RES, INT, INT2
STBY:::"Low"
Stop
Stop
Stop
Reset
Hold
High impedance
STBY="High"
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - HD63P05Y1 ,HD63PA05Y1 ,HD63PB05Y1
Figure 27
Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset
• PRECAUTION TO THE BOARD DESIGN OF OSCILLATION CIRCUIT
As shown in Fig.28, the cross talk may disturb normal
oscillation ifsign.al lines are set near the oscillation circuit.
When designing a board, be careful of this. Crystal and C
L
must be put near XTAL and EXTAL pins as possible.
c:
4 Pins IOn index side) open.
24 Pin EPROM should be inserted
on the mark side with 4 above open .
..
c:
~ v;~
v;
H>-..---:"'~5 (XTAU
~>--'----'-~ 6 (EXTALI
HD63P05Y1
Figure 28 Precaution to the board design of
oscillation circuit
• PRECAUTION TO USE THE EPROM ON-PACKAGE 8-BIT
SINGLE-CHIP MICROCOMPUTER
Please be careful of the following, since this MCV has a
special structure with pin socket on the package.
(1) Don't apply high static voltage or surge voltage over
MAXIMUM RATINGS to the socket pins as well as the
LSI pins. If so, that may cause permanent damage to the
device.
(2) When using 32k EPROM (24-pin), insert it leaving the
four pins above open.
(3) When inserting this into system products like mask ROM
type single chip microcomputer, be careful of the following to give effective contact between the EPROM pins and
socket pins.
(a) When soldering the LSI onto a printed circuit board,
the recommended condition is
Temperature: lower than 250°C
Time:
within 10 sec.
(b) Be careful that detergent or coating does not get into
the socket during flux washing or board coating after
soldering, because that lIlay cause had effect on
socket contact.
(c) Avoid permanent appiIrallllll III 11m IIndt'l rlllllltiiolls
~HITACHI
Hitachi America Ltd, • 2210 O'Toole Ave, • San Jose, CA 95131 • (408) 435-8300
893
HD63P05Y1,H D63PA05Y1 ,HD63PB05Y1 - - - - - - - - - - - - - - - - - - - - • Relative
See Fig. 33. The relative addressing mode is used with
branch instructions only. When a branch occurs, the program
counter is loaded with the contents of the byte following the
operation code. EA = (PC) + 2 + ReI., where ReI. indicates a
signed 8-bit data following the operation code. If no branch
occurs, ReI. = O. When a branch occurs, the program jumps
to any byte in the range + 129 to -127. A branch instruction
requires a length of 2 bytes.
of continuous vibration.
(d) The socket, repeatedly inserted and removed, loses
its contactability. It is recommended to use new one
when used in production.
-BIT MANIPULATION
The HD63P05Yl MCV can use a single instruction (BSET
or BCLR) to set or clear one bit of the RAM within page 0 or
an I/O port (except the write-only registers such as the data
direction register). Every bit of memory or I/O within page 0
(SOO "'" SFF) can be tested by the BRSET or BRCLR instruction; depending on the result of the test, the program can
branch to required destinations. Since bits in the RAM on page
0, or I/O can be manipulated, the user may use a bit within the
RAM on page 0 as a flag or handle a single I/O bit as an
independent I/O terminal. Fig. 29 shows an example of bit
manipulation and the validity of test instructions. In the
example, the program is configured assuming that bit 0 of port
A is connected to a zero cross detector circuit and bit I of the
same port to the trigger of a triac.
The program shown can activate the triac within a time of
10/oLs from zero-crossing through the use of only 7 bytes on
the memory. The on-chip timer provides a required time of
delay and pulse width mudulation of power is also possible.
• Indexed (No Off.et)
See Fig. 34. The indexed addressing mode allows access
up to the lower 255th address of memory. In this mode, an
instruction requires a length of one byte. The EA is the
contents of the index register.
• IndeKed (8-bit Offset)
See Fig. 35. The EA is the contents of the byte following the operation code, plus the contents of the index register.
This mode allows access up to the lower 511 th address of
memory. Each instruction when used in the index addressing
mode (8·bit offset) requires a length of 2 bytes.
.lndeKed (16·bit Offset)
See Fig. 36. The contents of the 2 bytes following the
operation code are added to content of the index register
to compute the value of EA. In this mode, the complete
memory can be accessed. When used in the indexed address·
ing mode (16·bit offset), an instruction must be 3 bytes long.
I
SE LF 1.
Figure 29
BRCLR 0, PORT A, SELF 1
BSET 1 , PORT A
BCLR 1, PORT A
EKample of Bit Manipulation
• Bit Set/Cle.r
See Fig. 37. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
O. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte that follows the operation code
indicates an address within page O.
-ADDRESSING MODES
Ten different addressing modes are available to the
HD63P05Yl MCV.
• Immediate
See Fig. 30. The immediate addressing mode provides
access to a constant which does not vary during execution of
the program.
This access requires an instruction length of 2 bytes. The
effective address (EA) is PC and the operand is fetched from
the byte that follows the operation code.
• Bit Test and Branch
See Fig. 38. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. Individual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relative value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code register.
• Direct
See Fig.31. In the direct addressing mode, the address of
the operand is contained in the 2nd byte of the instruction.
The user can gain direct access to memory up to the lower
255th address. 192 byte RAM and I/O registers are on page 0
of address space so that the direct addressing mode may be
utilized.
• Extended
See Fig. 32. The extended addressing is used for referencing to all addresses of memory. The EA is the contents of
the 2 bytes that follow the operation code. An extended
addressing instruction requires a length of 3 bytes.
894
• Implied
See Fig. 39. This mode involves no EA. All information
needed for execution of an instruction is contained in the
operation code. Direct manipulation on the accumulator
and index register is included in the implied addressing mode.
Other instructions such as SWI and RTI are also used in this
mode. All instructions used in the implied addressing mode
should have a length of one byte.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - HD63P05Yl ,HD63PA05Yl ,H D63PB05Yl
I
LE
=
A
I
Memory
I~_~t;:A~
F8
Index Reg
I
Stack Point
PROG LOA
II SF8
OSBEt:~~:::j~-------.J
OSBF
Prog Count
OSCO
CC
I-....;..:~-I
~
.
I
Figure 30
Example of Immediate Addressing
Memory
A
CATFCB32004Bt:~L:~~----i_----~~-----1t:~20~~
Index eg
\ir.to~ln~t- _...
Stack
PROG LOA CAT
~~~~ ...........;:~--i
Figure 31
Prog lount
OS2F
CC
Example of Direct Addressing
Memorv
0000
A
40
Index Reg
PROG LOA CAT 0409...--.....::;-~L
I
~:~:t-~:---f
Stack Pomt
CATFCB64 0 6 E S t : : 3 £ : : : } - - - - - - - - - - J
Figure 32
Prog Count
040C
CC
Example of Extended Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
895
HD63P05Y1 ,HD63PA05Y1 , H D 6 3 P B 0 5 Y 1 - - - - - - - - - - - - - - - - - - - - -
PROG BEQ PROG2 g::~I-"':;'~--1
FigurB 33
Example of Relative Addressing
Memorv
TABL FCC LI 00B8t=~=:::t--~iQQ.----t_-----t:;~4~C;;:J
n ex e
B8
,"OG LO"
0'"
§
Slick POlnl
Prog tunl
05F5CC
§
I
Figure 34
•
Example of Indexed (No Offset) Addressing
Memory
TABL FCB ~ BF
00B91-....;;,BF".....--I
:~: :~: ~g::~t::~~:t::~l__--_+-~I-+----~A~~C~F:;::J
FCB I CF
OOBC
CF
Index Reg
03
Stack POint
PROG LOA TABL X 075B
"::jE~6=::l_ _-..--J
075C~
B9
Prog Count
0750
cc
~
.
Figure 35 Example of Indexed (8·bit Offset) Addressing
896
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - H D63P05Y1,H D63PA05Y1,H D63PB05Y1
Memorv
PROG LOA TABL X 0692
0693
0694
~
A
DB
Index Reg
02
Stack omt
I
Prog Count
0695
CC
I
BF
B6
DB
CF
TABL FCB ~BF 077E
FCB IIB6 077F
FCB 1I0B 07BO
FCB IICF 0781
Figure 36 Example of Indexed (16-bit Offset) Addressing
PORT 8 EQU I 0001 ~.....::::....-.r-,
Index Reg
I
t:::ltt:=t-------.J
Stack POint
PROG BCLR 6 PORT 8 058F
0590 ...
Prog Count
0591
CC
~
I
I
,I
,I
Figure 37
Example of Bit Set/Clear Addressing
PORT C EQU 2 00021--.....;..;FO:.-~ 1'--...--'
A
In.dex Reg
I
PROG BRCLR 2.PORT C PROG 2 g~~:I-"";:~~;---1
Prog bount
0594
10
05761-...:..:
:""'-1
Figure 38
Example of Bit Test and Branch Addressing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
897
HD63P05Y1,HD63PA05Y1,HD63PB05Y1---------------------
Memory
,"OG'" 0'"
~
~
~
•
I
I
•
Figure 39
Example of Implied Addressing
-INSTRUCTION SET
There are 62 basic instructions available to the HD63P05Yl
MeU. They can be classified into five categories: register/
memory, read/modify/write, branch, bit manipulation, and
control. The details of each instruction are described in
Tables 5 through 11.
• Branch Instructions
A branch instruction branches from the program sequence
in progress if a particular condition is established. See Table 7.
• Register/Memory Instructions
Most of these instructions use two operands. One operand
is either an accumulator or index register. The other is derived
from memory using one of the addressing modes used on the
MeU. There is no register operand in the unconditional jump
instruction (JMP) and the subroutine jump instruction (JSR).
See Table 5.
• Read/Modify/Write Instructions
These instructions read a memory or register, then modify
or test its contents, and write the modified value into the
memory or register. Zero test instruction (TST) does not
write data, and is handled as an exception in the read/modify/
write group. See Table 6.
898
• Bit Manipulation Instructions
These instructions can be used with any bit located up to
the lower 255th address of memory. Two groups are available;
one for setting or clearing and the other for bit testing and
branching. See Table 8.
• Control Instructions
The control instructions control the operation of the MeU
which is executing a program. See Table 9.
• List of Instructions in Alphabetical Order
Table 10 lists all the instructions used on the MeU in the
alphabetical order.
• Operation Code Map
Table 11 shows the operation code map for the instructions
used on the MeU.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - H D63P05Y1 ,HD63PA05Y1 ,HD63PB05Y1
Table 5
Register/Memory Instructions
Addressing Modes
Indexed
Indexed
Operations
Mnemonic
Immediate
Extended
Direct
OP #
-
OP
#
-
-
OP
#
- OP
#
- OP
#
-
Load A from Memory
LOA
A6
2
2
B6
2
3 C6
3
4
F6
1
3
E6
2
4
06 3
5
M-A
Load X from Memory
LOX
AE
2
2
BE
2
3
CE
3
4
FE
1
3
EE
2
4
DE
3
5
M-X
Store A In Memory
STA
B7
2
3 C7
3
4
F7
1
4
E7
2
4
07
3
5
A-M
Store X In Memory
STX
BF
2
3
CF
3
4
FF
1
4
EF
2
4
OF
3
5
X-M
Add Memory to A
ADD
AB
2
2
BB
2
3 CB
3
4
FB
1
3
EB
2
4
DB 3
5
A+M-A
to A
AOC
A9
2
2
B9
2
3 C9
3
4
F9
1
3
E9
2
4
09 3
5
A+M+C-A
Subtract Memory
SUB
AO
2
2
BO
2
3 CO 3
4
FO
1
3
EO
2
4
DO 3
5
A-M-A
A with Borrow
SBC
A2
2
2
B2
2
3 C2
3
4
F2
1
3
E2
2
4
02
3
5
A-M-C-A
AND Memory 10 A
AND
A4
2
2
B4
2
3 C4
3
4
F4
1
3
E4
2
4
04 3
5
A· M-A
OR Memory wllh A
ORA
AA
2
2
BA 2
3 CA 3
4
FA
1
3
EA
2
4 DA 3
5
A+M-A
EOR
AB
2
2
B8
2
3 C8
3
4
FB
1
3
E8
2
4
08 3
5
A$M-A
CMP
Al
2
2
Bl
2
3 Cl
3
4
Fl
1
3
El
2
4
01
3
5
A-M
CPX
A3
2
2
B3
2
3 C3
3
4
F3
1
3
E3
2
4
03 3
5
X-M
A5
2
2
05
A·M
OP #
Condition
Code
Booleanl
Arithmetic
Operation
Indexed
(No Offset) (8·80t Offset) (16·80t Offset)
H
e
Arithmetic Compare X
BIT
B5
2
3 C5
3
4
F5
1
3
E5
2
4
3
5
JMP
BC
2
2 CC
3
3
FC
1
2
EC
2
3 DC 3
4
Jump to Subroutine
JSR
BO 2
5 CD 3
6
FO
1
5 ED
2
5 DO 3
6
1\
1\
A
A
A
C
A
1\
A
A
A
A
A
A
1\
1\
A
II
1\
A
1\
1\
1\
1\
1\
1\
1\
1\
e
•
.
.
•
·· •
• •
•
• •
1\
Symbols: Op = Operation
# = Number of bytes
- = Number of cycles
Table 6
1\
·•
Bit Test Memory with
A (Logical Compare)
A
/\
e
Arithmetic Compare A
Jump Unconditional
A
A
Exclusive OR Memory
with Memory
Z
/\
1\
Subtract Memory from
with Memory
N
··• ••
· ·• ··
•
• ·
• •
• •
•
·
• ·
·
• •
Add Memory and Carry
with A
I
•
•
1\
e
Read/Modify/Write Instructions
Addressing Modes
Operations
Indexed
Mnemonic
Imphed(A)
Imphed(X)
OP #
OP
#
Increment
INC
4C
1
2
5C
1
OP
#
-
OP #
5
7C
1
5
6C
OP #
2
3C
2
2
6
Boolean/Arithmetic Operation
A + 1 -A or X + 1 -X or M + 1 -M
Decrement
DEC
4A
1
2
5A
1
2
3A
2
5
7A
1
5
6A
2
6
A-I -A or X -1-X or M - 1 -M
Clear
CLR
4F
1
2
5F
1
2
3F
2
5
7F
1
5
6F
2
6
OO-A or OO-X or OO-M
Complement
COM
43
1
2
53
1
2
33
2
5
73
1
5
63
2
6
A-A or X-X or M-M
Negate
oo-A-A or OO-X-X
(2·$ Complement)
NEG
40
1
2
50
1
2
39
2
5
79
1
5
69
2
36
2
5
76
1
5
66
Rotate Left Thru Carry
ROL
49
1
2
59
1
Rotate Right Thru Carry
ROR
46
1
2
56
1
2
30
2
5
70
1
5
60
6
or oo-M-M
2
6
Lb--t I I I I I I Ib'~
2
6
LriHb' 1 H'~Of:MI
2
Aor)(orll
Logical Shift Right
LSL
LSR
48
44
1
1
2
2
58
54
1
1
2
2
38
34
2
2
5
5
78
74
1
1
5
5
68
64
2
2
6
6
Arithmetic Shift Right
ASR
47
1
2
57
1
2 37
2
5
77
1
5
67
2
6
Arithmetic Shift Left
ASL
4B
1
2
58
1
2
2
5
7B
1
5
6B
2
6
TST
40
1
2 50
1
2 3D 2
4
70
1
4
60 2
5
38
T..t for Negative
or Zero
c
b,
H
I
•
•
•
•
•
•
•
•
· ·•
·
1bo~ • •
C
Logical Shift Left
Condition
Code
Indexed
(No Offsetl (8·80t Offset)
Direct
N
Z
1\
1\
1\
1\
C
•
•
•
0
1
A
A
1
1\
1\
1\
1\
1\
1\
A
1\
1\
1\
1\
1\
0
1\
1\
1\
1\
A.
1\
1\
1\
1\
1\
•
bo
D-l I ~,,:xr~ 1 I ~o • •
b,
c
0-1 I I·H ..:MI 1 1-0 • •
[(b'
:1 H'~~MI 1 1-0 • •
Equal to LSL
• •
bo
bo
A-oo or X-oo or M-OO
C
• •
Symbols: Op· Operation
# • Number of bytes
- • Number of cycles
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
899
HD63P05Y1 ,HD63PA05Y1,H D 6 3 P B 0 5 Y 1 - - - - - - - - - - - - - - - - - - - - - Table 7 Branch Instructions
Addressing Modes
Mnemonic
Operations
Relative
OP
~
-
20
2
3
H
Branch Always
Branch Never
BRN
21
2
3
None
Branch IF Higher
BHI
22
2
3
C+Z=O
Branch IF lower or Same
BlS
23
2
3
C+Z=l
Branch IF Carry Clear
BCC
24
2
3
C=O
(BHS)
24
2
3
C=O
BCS
25
2
3
C=l
(BlO)
25
2
3
C=l
BNE
26
2
3
z=o
Z=l
Branch IF Carry Set
(Branch IF lower)
Branch IF Not Equal
BEQ
27
2
3
Branch IF Half Carry Clear
BHCC
28
2
3
H=O
Branch IF Half Carry Set
BHCS
29
2
3
H=l
Branch IF Plus
BPl
2A
2
3
N=O
Branch IF Minus
BMI
2B
2
3
N=l
BMC
2C
2
3
1=0
BMS
20
2
3
1=1
Bil
2E
2
3
INT=O
Branch IF Equal
Branch IF Interrupt Mask
Bit is Set
Branch IF Interrupt line
is low
Branch IF Interrupt line
is High
BIH
2F
2
3
INT=l
Branch to Subroutine
BSR
AD
2
5
--
Symbols: OP
#
-
N
• • •
• • •
• • •
• • •
• • •
• • •
Branch IF Interrupt Mask
Bit is Clear
I
Z
C
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
None
BRA
(Branch IF Higher or Same)
Condition Code
Branch Test
•
•
•
•
•
•
•
•
•
•
•
•
= Operation
= Number of bytes
= Number of cycles
Table 8 Bit Manipulation Instructions
Addressing Modes
Operations
Mnemonic
Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear Bit n
Bit Set/Clear
Boolean/
Bit Test and Branch Arithmetic
Operation
OP
#
OP
#
-
BRSET n(n = 0···7)
-
-
-
2·n
BRClR n(n=0···7)
-
-
-
01 +2·n
10+2·n
11 +2·n
2
5
5
BSET n(n =0···7)
BClR n(n=0···7)
2
-
-
Branch
Test
3
3
5
5
-
Mn=l
-
-
1..... Mn
-
-
-
O..... Mn
-
Symbols: Op Operation
1# • Number of bytes
- • Number of cycles
Mn=O
Condition Code
H
I
•
•
•
•
• • •
• • •
• • • •
• • • •
N
Z
E
900
~HITACHI
\ Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
C
/\
/\
- - - - - - - - - - - - - - - - - - - - - HD63P05Yl ,H D63PA05Yl ,HD63PB05Yl
Table 9
Control Instructions
Addressing Modes
Operations
Mnemonic
Implied
OP
Transfer A to X
TAX
97
Condition Code
Boolean Operation
#
1
2
A-+X
H
Transfer X to A
TXA
9F
1
SEC
99
1
2
1
X-+A
Set Carry Bit
Clear Carry Bit
CLC
98
1
1
O-+C
0-+1
Set Interrupt Mask Bit
SEI
9B
1
CLI
9A
1
2
2
Software Interrupt
SWI
83
1
10
Return from Subroutine
RTS
81
1
5
Return from Interrupt
RTI
80
1
B
Reset Stack Pointer
RSP
9C
1
2
1
$FF-+SP
Converts blnarv add of BCD charcters Into
BCD format
NOP
90
1
Decimal Adjust A
OAA
80
1
Stop
STOP
8E
1
2
4
WAIT
8F
1
4
Wait
Symbols; Op = Operation
# = Number of bytes
= Number of cycles
1-+1
?
Advance Prog Cntr. Only
1\
Mnemonic
Indexed
Immediate
Direct
x
x
x
x
x
x
x
x
ADD
ASL
ASR
x
x
Extended Relative (No Offset)
x
x
x
x
x
x
x
x
Indexed
Set/
Test &
(B-Bit)
(16-Bit)
Clear
Branch
x
x
x
x
x
X
1\
X
1\
x
..
BHCS
BHI
(BHS)
BIH
BIL
x
x
x
x
BPL
x
x
x
x
x
x
x
BRA
x
(BLO)
BLS
BMC
BMI
BMS
BNE
I
•
•
•
•
?
•
•
•
•
1\*
N
Z
C
1\
1\
1\
1\
" •"
"
• "•
• •
• •
• •
• •
• •
• •
• •
• •
• •
" •
• •
• •
• •
• •
• •
• •
• •
• •
1\
1\
• • 1\
• • •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • •
• • •
x
x
x
x
x
x
x
x
BEQ
BHCC
H
•
•
• •
• •
x
BCLR
BCS
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
1
0
Bit
Indexed
x
BCC
BIT
•e"
Condition Code
Bit
AND
1\
C
Instruction Set (in Alphabetical Order)
Addressing Modes
ADC
Z
• Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.>
Table 10
Implied
N
•
•
•
•
•
•
• • •
• • • •
? ? ?
• • • •
• • • •
• •
• • • •
e
• • •
l-+C
Clear Interrupt Mask Bit
No-Operation
I
• • •
• • •
• • •
• •1 •
• 0 •
• 1 •
x
x
• • •
• • •
• •
• • •
• • •
1\
• • •
• • •
• • •
• • •
• • •
• • •
1\
1\
1\
(to be continued)
C
1\
•
Carry /Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
901
HD63P05Y1, HD63PA05Y1, H D 6 3 P B 0 5 Y 1 - - - - - - - - - - - - - - - - - - - - Table 10 Instruction Set (in Alphabetical Order)
Condition Code
Addressing Modes
Bit
Mnemonic
Implieci
Immediate
Direct
Extended
Relative
Indexed
Indexed
Indexed
Set!
Test &
(No Offset)
(S-Bit)
(16-Bit)
Clear
Branch
H
x
x
•
•
•
•
x
BRN
BRCLR
BRSET
x
BSET
x
BSR
CLC
x
CLI
x
x
CLR
CMP
COM
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
CPX
DAA
x
DEC
x
EOR
INC
x
x
x
x
JSR
x
x
LDA
LSL
x
x
x
LSR
x
x
NEG
x
x
x
LDX
x
ORA
ROR
x
x
RSP
x
ROL
RTI
x
RTS
x
x
x
x
SEI
x
STA
STOP
x
SUB
SWI
x
TAX
x
TST
x
x
x
WAIT
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
902
x
x
x
x
x
x
x
x
x
x
x
x
x
x
STX
TXA
x
x
x
SBC
SEC
x
x
JMP
NOP
Bit
C
/\
•?
x
x
I
•
•
•
•
• •
• •0
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
? ?
• •
• •
• •1
•
• •
• •
• •
• •
• 1
• •
• •
• •
• •
Z
N
C
• • •
• •
• •
• • •
• • •
• • 0
• • •
0 1
1\
1\
•
/\
1\
1\
1\
1
1\
1\
1\
1\
1\
1\
1\
1\
/\
1\
1\
•
•
•
• • •
• • •
•
•
/\
1\
1\
1\
1\
1\
1\
1\
1\
0
1\
1\
1\
1\
1\
• • •
•
/\
1\
1\
1\
1\
1\
/\
1\
•
?
•
•
•
•
•? •?
• •
• 1
• •
•
• •
1\
1\
1\
1\
1\
1\
1\
1\
• •
• •
1\
1\
• •
• •
Carry IBorrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
~HITACHI
Hitachi America Ltd, • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
/\
•
•
•
•
•
•
/\
----------------------HD63P05Y1,HD63PA05Y1,HD63PB05Y1
Table 11 Operation Code Map
0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
Bit Manipulation
Test &
Set!
Branch
Clear
1
0
BRSETO
BSETO
BRCLRO
BCLRO
BRSETl
BSETl
BRCLRl
BCLRl
BRSET2
BSET2
BRCLR2
BCLR2
BRSET3
BSET3
BRCLR3
BCLR3
BRSET4
BSET4
BRCLR4
BCLR4
BRSET5
BSET5
BRCLR5
BCLR5
BRSET6
BSET6
BRCLR6
BCLR6
BRSET7
BSET7
BRCLR7
BCLR7
3/5
2/5
(NOTES)
Branch
Rei
2
BRA
BRN
BHI
BLS
BCC
BCS
BNE
BEQ
BHCC
BHCS
BPL
BMI
BMC
BMS
BIL
BIH
2/3
Read/Modify/Write
DIR
3
TST(-1)
2/5
A
4
X
5
NEG
Control
Register/Memory
.XO IMP IMP IMM DIR EXT .X2 .Xl .XO
A
7
B
8
0
E
F
C
9
RTI'
SUB
RTS'
CMP
SBC
SWI'
COM
CPX
LSR
AND
BIT
ROR
LOA
ASR
TAX'
STA{+!)
STA
LSL/ASL
CLC
EaR
ROL
SEC
AOC
DEC
CLI*
ORA
AOD
SEI*
INC
RSP'
JMP(-l)
TST
TST(-l) DAA' NOP BSW JSR(+2) JSR(+l) JSR(+2)
STOP' LOX
CLR
WAIT" TXA'
STX(+!)
STX
1/2 1/2 2/6 1/5 1/' 1/1 2/2 2/3 3/4 3/5 2/4 1/3
.Xl
6
+--
HIGH
0
1
2
3
4
5
6
7
L
o
W
8
9
A
B
C
0
E
F
1. "-" is an undefined operation code.
2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).
The number of cycles for the mnemonics asterisked (0) is as follows:
RTI
8
TAX
2
RTS
5
RSP
2
SWI
10
TXA
2
BSR
5
DAA
2
STOP
4
eLi
2
WAIT
4
SEI
2
3. The parenthesized numbers must be added to the cycle count of the particular instruction.
• Additional Instructions
The following new instructions are used on the HD63P05YI:
DAA Converts the contents of the accumulator into BCD
code.
WAIT Causes the MeV to enter the wait mode. For this mode,
see the topic, Wait Mode.
STOP Causes the MCV to enter the stop mode. For this mode,
see the topic, Stop Mode.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
903
HD63701 VO,HD637 A01 VO,-HD637B01VO
CMOS MCU (Microcomputer Unit)
-ADVANCE INFORMATIONThe HD63701 VO is an 8-bit CMOS single-chip microcomputer
unit, pin compatible with the HD6301V. 4kB EPROM, 192 bytes
RAM, Serial Communication Interface (SCI), parallel I/O ports
and multi function timer are incorporated in the HD63701VO. It is
bus compatible with HMCS6800. Execution time of key instructions are improved and several new instructions are added to increase system throughput. The HD63701 VO can be expanded up to
65k words. Like the HMCS6800 family, I/O level is TTL compatible with + 5.0V single power supply. As HD6370lVO is fabricated
by the advanced CMOS process technology, power dissipation is extremely reduced. In addition to that, HD63701 VO has Sleep Mode
and Standby Mode at lower power dissipation mode. Therefore
flexible low power consumption application is possible.
HD63701VOC, HD637A01VOC, HD637B01VOC
On chip EPROM can be programmed by the same procedure
as that of 27C256 or 27256.
•
•
•
•
•
•
•
•
•
•
FEATURES
Instruction Set Compatible with HD6301 Family
Abundant On-Chip Functions
4kB EPROM, 192 Bytes RAM, 29 Parallel 1/0 Lines, 2 Lines of
Data Strobe, 1 6-bit Timer, Serial Communication Interface
Low Power Consumption Mode: Sleep Mode, Standby Mode
Minimum Instruction Execution Time
1p..s (f= 1MHz), 0.67 p..s (f= 1.5MHzl. O.5p..s (f= 2MHz)
Bit Manipulation, Bit Test Instruction
Protection from System Upset Address Trap, Op-Code Trap
Up to 65k Words Address Space
Wide Operation Range
Vcc=5V±10%(f=O.1 t02.0MHz)
(DC-40)
•
PIN ARRANGEMENT
Vss
XTAL
EXTAL
NMI 4
IRQ, 5
RES 6
STBY
P 20
P2 ,
P 22
P 23
P 24
TYPE OF PRODUCTS
Type No.
HD63701VO
HD637A01VO
HD637B01VO
Bus Timing
9
11
P lO
P"
1.0MHz
1.5 MHz
2.0 MHz
P'2
P'3
P'4
P,s
P'6
P 17
20
(Top View)
904
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
H D 6370 1va H D 637 AO 1va H D 63 7 BO 1va
I
•
I
BLOCK DIAGRAM
>
...J
...J«
0)0.. ••- - -_ _
0..
«
;..~
EPROM MODE
~ ~~~~ I~bffi
/CJ»> Xww zjg:lC2
--~~P20
~~--4-~
P21
~-+--,..----........
P22
~-+-I-+-.......-
P23
P24
- - - - - - P10/A
O
- - - - - - P 1 i/ A '
......----P'2/A 2
......- - - - P 13 /A 3
......- - - - P14/ A4
P1s /A S
......- - - - P1S /A S
P17/A 7
EPROM MODE
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
905
HD63701 XO,HD637 A01 XO,-HD637B01XO
CMOS MCU(Microcomputer Unit)
-PRElIMINARY-
The HD63701XO is a high performance 8-bit CMOS single
chip microcomputer unit (MCU) which, including 4k bytes of
EPROM, is pin compatible with the HD6301XO.
The HD63701XO contains 4k bytes of EPROM, 192 bytes of
RAM, serial communication interface and 53 parallel I/O pins in
addition to CPU. It includes functions of halt, memory ready,
low speed access and releasing external bus at system expansion.
The HD63701XO is available in a hermetically sealed 64-pin
shrunk ceramic package which includes a window that allows for
EPROM erasure and in a 64-pin shrunk plastic package which is
one-time-programmable type. It can be programmed in the same
method as 2732A type EPROM.
• FEATURES
• Instruction Set Compatible with the HD6301 XO
• 4k Bytes of EPROM (compatible with 2732A type)
• 192 Bytes of RAM
• 53 Parallel I/O Pins
24 I/O Common Pins (Port 2, 3, 6)
21 Output Pins (Port1, 4, 7)
8 Input Pins (Port 5)
• Driving Darlington Transistor (Port 2, 6)
• 16-bit Programmable Timer
Input Capture Register x 1
Free Running Counter x 1
Output Compare Register x 2
• 8-bit Reloadable Timer
External Event Count
Square Wave Occurrence
• Serial Communication Interface (SCI)
Asynchronous Mode/Clock Synchronous Mode
3 Transfer Formats (Asynchronous Mode)
6 Clock Sources
• Memory Ready for Low Speed Memory Access
• Halt
• Error-Detection (Address Error, Op-code Error)
• Interrupts - 3 External, 7 Internal
• Operation Mode
Mode 1 - Expanded
(Internal ROM Inhibited)
MCU Mode [ Mode 2 _ Expanded (Internal ROM Valid)
Mode 3 - Single-chip Mode
EPROM Mode
• Up to 65k Bytes of Address Space
• Low Power Dissipation Mode
Sleep
Standby
• Minimum Instruction Execution Time - 0.5p.s (f=2.0MHz)
• Wide Operation Range
f=0.1 to 1.0MH:z; HD63701XO
V cc =5V±10% f=0.1 to 1.5MHz; HD637A01XO
[ f=0.1 to 2.0MHz; HD637B01XO
HD63701XOC,HD637A01XOC,
HD637B01XOC
(DC-64S)
HD63701XOP,HD637A01XOP,
HD637B01XOP
(DP-64S)
• PIN ARRANGEMENT
(Top View)
906
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
------------------------------------------HD63701XO,HD637A01XO,HD637B01XO
• BLOCK DIAGRAM
"
."
..
Vee
Vss
0
~
~
11.
~
j
~
1ff31~1:E
II: (I) Z
w
rD~ 111111-,rr-----.
0
II:
fu
,;:
11.0
~
_II:
P21(Tout1)
P22(SCLK)
P'3(Rx)
N~
P'4(Tx)
11.
CPU
-y
"
~
~ ~
:IE
:IE
~
:IE
0
II:
fu
-1+.j-j...1+-_ P70/Jm
P71 ;WR
P72/R/w
P73/ OR
P7A/BA
o
P,5(Tout2)
P,s(Tout3)
P27(TCLK)
~ ~
1 11
II:
~o
P,o(Tin)
..,
-
- P 3 0 / Do/EOo
..,
.f
- P 3 ' / D,/EO,
- P 3 ' / D,/E02
P33/D3/E03
f--- P3A/DA/EOA
P30/D./EO.
P3e/De/EOe
f--- P37/D7/E07
r--r---
~
r--P,oiAo/EAo
-P,,/A,/EA,
..
,.
~
.f
-P12/A2/EA2
-P13/A3/EA3
-P'A/AA/EA.
-P,o/Ao/EA.
-P,s/As/EAe
Pso(IRQ,)
Ps,(IRQ,)
Ps,(MR)
Ps3(HALT)---.....
P S 4 - - -.....
o
11.
P s s - - -.....
Pss----t
CE/
b
Ps,---~
-
PsoPs,Ps,PS3PS4PssPss-
.
II:
co
0
11.
0
0
co
0
11.
~
-
u
RAM
192 Bytes
EPROM
4k Bytes
......-----vpp/lrE'
Ps,-
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
907
HD63701XO,HD637A01XO,HD637B01XO--------------------•
ABSOLUTE MAXIMUM RATINGS
Value
Unit
-0.3- +7.0
V
Program Voltage
Vee
Vpp
-0.3- 22
V
I nput Voltage
Yin
-0.3- Vee+0.3
V
Operating Temperature
Topr
0-+70
°c
Storage Temperature
Tstg
-55 -+125
°c
Item
Symbol
Supply Voltage
(Note) This product has protection circuits in input terminal from high static electricity voltage and high electric field. But be careful not to apply
overvoltage more than maximum ratings to these high input impedance protection circuits. To assure the normal operation, we recommend
Vin, Vout : VSS~ (Vin or Vout)~ Vee·
•
•
MCU ELECTRICAL CHARACTERISTICS
o
DC CHARACTERISTICS (Vee =5V±10%, Vss = Vpp =OV, Ta= 0 - +70 C, unless otherwise noted.)
Symbol
Item
Test Condition
RES,STBY,MPo,MPl
Input "High" Voltage
EXTAL
P22 (SCLK)***
min
typ
Vee- 0 .5
-0.3
-
Vee xO .7
VIH
2.4
Other Inputs
2.2
max
Unit
Vee+O· 3
V
Input "Low" Voltage
All Inputs
V IL
0.8
V
Input Leakage Current
NMI, RES, STBY,
MPo MPI Port 5
Ilinl
Vin=0.5 - Vee-0.5V
-
-
1.0
fJ.A
Three State (off-state)
Leakage Current
Ports 1,2,3,4,6,7
IITSd
Vin=0.5 - Vee-0.5V
-
-
1.0
fJ.A
Output "High" Voltage
All Outputs
VO H
IOH=- 2OOfJ. A
2.4
Vee- 0 .7
-
-
V
IOH=-10fJ.A
IOL =1.6mA
-
0.5
V
VOL
-
V
V out =1.5V
1.0
-
0.4
-IOH
10.0
mA
Cin
Vin=OV, f=1MHz,
Ta=25°C
-
-
12.5
pF
-
-
25
pF
3.0
15.0
fJ.A
-
1.5
3.0
mA
Sleeping (f=1.5MHz**J
2.3
4.5
mA
Sleeping (f=2MHz**)
-
3.0
6.0
mA
Operating (f=1 MHz* *)
-
7.0
10.0
mA
Operating (f=1.5MHz**)
-
10.5
15.0
mA
Operating (f=2MHz**)
-
14.0
20.0
mA
2.0
-
-
V
Output "Low" Voltage
Ports 2, 6
Other Outputs
Darlington Drive Current Ports 2, 6
All Inputs (Except
Vpp/OE)
Input Capacitance
Vp p /O'E
Non Operation
Standby Current
ISTB
Sleeping (f=1MHz**)
ISLP
Cu(:'ent Dissipation *
Icc
RAM Standby Voltage
VRAM
V
·VIH min = Vee-1.OV, VIL max = O.8V (All output terminals are at no load.)
"Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max. values about Current
Dissipations at x MHz operation are decided according to the following formula;
typo value If = x MHz) = typo value (f = 1MHz) x x
max. value (f = x MHz) = max. value (f = 1MHz) x x
••• Synchronous clock input use only.
908
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------HD63701XO,HD637A01XO,HD637B01XO
•
AC CHARACTERISTICS (Vcc =5V±10%, Vss=Vpp=OV, Ta=O "-' +70°C, unless otherwise noted.)
BUS TIMING
Item
Symbol
Test
Condition
HD63701XO
min
typ
HD637A01XO
max
min
typ
HD637B01XO
max
min
typ
max
Unit
Cycle Time
tcyc
1
-
10
0.666
-
10
0.5
-
10
Enable Rise Time
tEr
-
-
25
-
-
25
-
-
25
ns
Enable Fall Time
-
-
-
25
-
ns
-
300
-
-
220
-
25
450
-
25
Enable Pulse Width "High" Level*
tEf
PW EH
-
ns
Enable Pulse Width "Low" Level*
PWEL
450
-
-
300
-
-
220
-
-
ns
Address, R/WDelay Time*
tAO
-
-
250
-
-
190
-
160
ns
J.l.S
Data Delay Time
1Write
toow
-
-
200
-
-
160
-
-
120
ns
Data Set-up Time
I Read
tOSR
80
-
70
-
-
70
-
-
ns
tAH
70
-
45
-
-
30
-
-
ns
tHW
70
-
-
50
-
-
35
-
-
ns
0
-
-
0
-
-
0
ns
450
-
-
300
-
-
220
-
-
RD, WR Pulse Width*
tHR
PW RW
-
ns
RD, WR Delay Time
tRWO
-
-
40
-
-
40
-
-
40
ns
RD, WR Hold Time
tHRW
-
30
200
160
-
-
ns
-
-
25
tOLR
-
30
LI R Delay Time
-
120
ns
Address, R/W Hold Time*
Write*
Data Hold Time
I Read
I
em Hold Time
Fig. 1
tHLR
10
-
-
10
-
-
10
-
-
ns
MR Set-up Time*
tSMR
400
-
-
280
-
-
230
-
-
ns
MR Hold Time*
tHMR
-
-
90
-
-
40
-
-
0
ns
E Clock Pulse Width at MR
PWEMR
-
-
9
-
-
9
-
-
9
J.l.S
Processor Control Set-up Time
tpcs
200
-
-
200
-
-
200
-
-
ns
-
-
100
-
-
100
-
-
100
ns
-
-
100
-
-
100
-
-
100
ns
-
-
250
-
-
190
-
-
160
ns
20
-
-
20
-
-
20
-
ms
3
-
-
3
-
-
3
-
-
Processor' Control Rise Time
tpcr
Processor Control Fall Time
tpCf
BA Delay Time
tSA
Oscillator Stabilization Time
tRC
PW RST
Reset Pulse Width
Fig.2
Fig. 3,
10,11
Fig. 2, 3
Fig.3
Fig.11
tcyc
• These timings change in approximate proportion to t cyc ' The figures in this characteristics represent those when tcye is
minimum (~in the highest speed operation),
PERIPHERAL PORT TIMING
Item
Symbol
HD63701XO
typ
max
Test
Condition
min
HD637B01XO
HD637A01XO
min
typ
max
min
typ
max
Unit
Peripheral Data
Set-up Time
Ports 2, 3, 5, 6
tposu
Fig.5
200
-
-
200
-
-
200
-
-
ns
Peripheral Data
Hold Time
Ports 2,3,5,6
tpOH
Fig.5
200
-
-
200
-
-
200
-
-
ns
tPWEO
Fig.6
-
-
800
-
-
630
-
-
550
ns
D.,.y Tim. IEo,bl.
positive TranSition to
Peripheral Data Valid)
IPo,"
1 2
3
6 '7 '
4
""
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
909
HD63701XO,HD637A01XO,HD637B01XO--------------------TIMER, SCI TIMING
Item
HD637A01XO
HD63701XO
Symbol
Test
Condition
min
typ
max
min
typ
HD637B01XO
max
min
typ
max
Unit
Timer 1 Input Pulse Width
tPWT
Fig.8
2.0
-
-
2.0
-
-
2.0
-
-
tcyc
Delay Time (Enable Positive
Transition to Timer Output)
tTOD
Fig.7
-
-
400
-
-
400
-
-
400
ns
[
I
Fig.8
1.0
-
-
tscyc
1.0
-
-
-
tcyc
2.0
-
-
2.0
-
_.
1.0
Fig. 4, 8
2.0
-
-
tcyc
-
-
200
-
-
200
-
-
200
ns
290
-
-
290
-
-
290
-
-
ns
SCI Input
Clock Cycle
Async. Mode
Clock Sync.
SCI Transmit Data Delay
Time (Clock Sync. Mode)
tTXD
SCI Receive Data Set·up
Time (Clock Sync. Mode)
tSRX
SCI Receive Data Hold Time
(Clock Sync. Mode)
tHRX
100
-
-
100
-
-
100
-
-
ns
SCI Input Clock Pulse Width
tpwSCK
0.4
-
0.6
0.4
-
0.6
0.4
-
0.6
tscyC
Timer 2 Input Clock Cycle
ttCyc
2.0
-
-
2.0
-
-
2.0
-
-
tcyc
Timer 2 Input Clock Pulse
Width
tpwTCK
200
-
-
200
-
-
200
-
-
ns
Timer 1'2, SCI Input Clock
Rise Time
tCKr
-
-
100
-
-
100
-
-
100
ns
Timer 1'2, SCI Input Clock
Fall Time
tCKf
-
-
100
-
-
100
-
-
100
ns
Fig.4
Fig.8
AD-A".
RW
RD.WR
MCU Write
00- 0,
MCU Read
00-0,
lIR
Figure 1 Mode 1, Mode 2 Bus Timing
910
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63701XO,HD637A01XO,HD637B01XO
!------PWEMR------I
\
E
\
\
'-----
O.BV
-I---+-- tHMR
MR
Figure 2 Memory Ready and E Clock Timing
Last Instruction
Execution Cycle
HALT Cycle
I
Instruction Execution
Cycle
E
tBAt---1r---{!-----....;..;.-..:....---_
2.4V
BA
Figure 3 HALT and BA Timing
Synchronous Clock
(I nput/Output)
Transmit Data
Receive Data
Figure 4 SCI Clocked Synchronous Timing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
911
HD63701XO,HD637A01XO,HD637B01XO----------------....;....----,
MCUWrite
E
tPWED
P'O-P17, P20-P27--------,. p..".......- PaO-P37, P40-P47
2.4V Data Valid
PSO-P67, P70-P74------- ~O;.;.,l.8""V:......-(Outputs)
Pao-Pa7
(Inputs)
Figure 6 Port Data Delay Times (MCU Writel
Figure 5 Port Data Set-up and Hold Times (MCU Read)
E
Timer 1 - - - - - , . -~=.;=:......
FRC
----
P21 , P2S
Outputs - - - - - - - - ~~--(b) Timer 2 Output Timing
(a) Timer 1 Output Timing
Figure 7
o~
tCK,
Timer Output Timing
Vee
••
tCKf
..
lS2074~
C
• Timer 2; ttcyc •• Timer 1; tPWT
SCI
; tscyc
Timer 2; tPWTCK
SCI
;tPWSCK
Figure 8 Timer 1-2, SCI Input Cloek Timing
912
m
RL =2.2kQ
Test Point
R
or Equiv.
C=90pF for Port 1, Port 3, Port 4, E
=30pF for Port 2, Port 6, Port 7
R=12kQ for Port 1-Port4, Port 6, Port 7, E
Figure 9 Bus Timing Test Loads (TTL Load)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - H063701 XO,H 0637 A01 XO,H0637B01 XO
Inlerrupl
Tesl
Inlernel
Address Bus _ _"'--\-...J'-_"'-_...J'-_"'-_..J\-_J\._..J\-_A_..J'\-_A_JI.-_"-_J\_--,"-_J\_
NMI.
iimi.
nm;.
IRa.
Inlernll
Det.Bus _ _~_-J'-_J\._..J\-_J\._..J\-_A_-J\-_.A._..J~_A_J\-_~_J\_-J~_J\_
IXOIX7
,
Internll
Reed
IX8IX15
ACCA
- _____~I
Internal
Write
ACC8
CCR
VeClor Vector Firslinsl. of
MS8
LS8
Inlerrupt Routine
\
Figure 10 Interrupt Sequence
--s.sv
~--------.~----+-----------~
/1....=-=----·AC-----I
m _ _ _- - -_ _., .....-....JI
Vee -o.c,v
~~' ... i\\\\I~\\\\\\\\\\\\\\\\\\\\\\\CX=~-----r-~
FFFF
FFFF FFFF FFFF r:r:fF FFFE FFFF Nh'IIPC
.
"'--F'f!FF
FFFf FFFF
\~~I!----_~.tn., . .~\\\\\\\\\\\\\\\\\\\\\\\
R!VV
:~~II-(
____--
I~~(
1a~\\\\\\\\\\\.\I\W
Ill!
-:~\\\\\\\\\\\\\\\\\\\\\\\f
I~~~j-j----
WI1
Dl~%§§§\§\\\\\\\\\\\t
II
~~:. _,1\\\\\\8\\\\\\\\\\\\\\\\\\\,
f~~J-j---
(}-{}--O;"I-----I}-(
--pca First
pca
PC 15
PC 7
Instruction
Figure 11 Reset Timing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
913
HD63701XO,HD637A01XO,HD637B01XO-----------------------------------------•
•
EPROM PROGRAMMING ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (V cc=5V±10%, Vpp=21V±O.5V, VSS=OV, Ta=25°C±5°C, unless otherwise noted.)
Item
•
Symbol
Test Condition
min
typ
max
20.5
21
21.5
V
-
-
30
mA
-
10
JJ,A
-
0.6
V
Unit
Program Voltage
Vpp
Program Current
Ipp
Vpp=21V
Input Leakage Current
III
Vin=5.25V/0.4V
-
Input "Low" Voltage
V IL
-0.1
Input "High" Voltage
VIH
2.2
-
Vcc+ 1 .O
V
Output "Low" Voltage
VOL
IOL =1.6mA
-
-
0.4
V
Output "High" Voltage
VOH
IOH=-200JJ,A
2.4
-
-
V
AC CHARACTERISTICS (V cc=5V±10%, Vpp=21V±O.5V, VSS=OV, Ta=25°C±5~C, unless otherwise noted.)
Item
Symbol
Address Set-up Time
Test Condition
min
typ
max
Unit
-
-
JJ,s
tAS
2
Address Hold Time
tAH
0
-
-
JJ,s
OE Set·up Time
DE Hold Time
tOES
2
-
-
JJ,s
tOEH
2
-
-
JJ,s
tos
2
-
-
JJ,s
JJ,s
Data Set·up Time
Data Hold Time
tOH
2
-
-
Output Disable Delay Time
tOF
0
-
130
ns
-
-
1
JJ,s
ms
Data Valid from
CE
tov
CE=VIL, OE=VIL
cr Pulse Width
tpw
45
50
55
OE Pulse Rise Time
tpRT
50
-
-
ns
V pp Recovery Time
tVR
2
-
-
JJ,s
(Notel tOF is defined when output becomes open because output level can not be refered.
EAo-EAl1
EOo-EO,
Vpp
OE
Figure 12 EPROM Programming Timing
914
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63701XO,HD637A01XO,HD637B01XO
•
FUNCTIONAL PIN DESCRIPTION
• v cc- vss
Vee and Vss provide power to the MCU with 5V±10% supply. Vss pin should be tied to ground.
•
XTAL.EXTAL
These two pins interface a crystal (an AT-cut type). Divideby-four circuit is on chip. When 4MHz crystal is used, the system
clock is IMHz for example.
EXT AL pin may be driven with an external clock of 45 to
55% duty, and one fourth frequency of the external clock is produced in the LSI. The external clock frequency should be less
AT Cut Parallel Resonant Crystal Oscillator
Co=7pF max
Rs=60Q max
•
CL 1 =CL2
= 10pF - 22pF±20%
(3.2 -8MHz)
EXTALI----~~
(a) Crystal Interface
XTAL~N.C.
External Clock
(b) External Clock
•
than four times of the maximum frequency. When using the external clock, XT AL pin should be open. Fig. 13 shows an example of connection circuit. The crystal and C Ll , C L2 should be
mounted as close as possible to XT AL and EXT AL pins. Any
line must not cross the line between the crystal and XTAL, EXTAL.
• S'fBY
This pin is used for standby mode or EPROM mode.
In standby mode, the oscillation may be stopped. To retain
the contents of RAM at standby, "0" should be written into
RAM enable bit (RAMW). RAME is the bit 6 of the RAM/port
5 control register at $0014. RAM is disabled by this operation
and its contents is sustained. Refer to "LOW POWER DISSIPATION MODE" for standby mode.
When this pin and Mode Program pins, MPo and MP 1 , are
"Low" level, the MCU is in EPROM mode. Refer to "PROGRAMMING THE EPROM" for details.
Interrupt Request URQ,. 1RQ2)
These are level-sensitive pins which request an internal interrupt sequence. At interrupt request, the CPU will complete the
current instruction before it responds to the request. If the interrupt mask in the condition code register is clear, the CPU will
begin an interrupt sequence; if set, the interrupt request will be
ignored. When the sequence starts, the contents of the program
counter, the index register, the accumulators and the condition
code register will be pushed onto the stack, then the interrupt
mask bit will be set and inhibits all maskable interrupt. Finally, a
vector is fetched from an address depicted in Table 1 and transferred to the program counter, and instruction execution is resumed.
The external interrupt pins, IRQI and IRQ2 are also used for
port pins Pso and PSI' so it is controlled by Bit 0 and 1 of the
RAM/port 5 control register at $0014. Refer to "RAM/PORT 5
CONTROL REGISTER" for details.
One of the internal interrupts, ICI, OCI, TOI, CMI or SIO
can generate an internal interrupt (IRQa). IRQa function is just
the same as IRQI or IRQ2 except the vector address. Fig. 14
shows the block diagram of the interrupt circuit.
•
Reset (RES)
This pin is used to reset the MCU's internal state and provide
a startup procedure. During power up, RES pin must be held
below "Low" level for more than 20 ms.
The CPU registers (accumulator, index register, stack pointer,
condition code register except for interrupt mask bit), RAM and
data registers of ports are not initialized during reset, so their
contents are unknown in a startup procedure.
To reset the MCU during operation, RES should be held
"Low" for at least 3 system-clock cycles. At the 3rd cycle, all the
address buses become "High". When RES remains "Low", the
Non-Maskable Interrupt (NMI)
When the negative edge of the input signal is detected at this
pin, the CPU will begin a non-maskable interrupt sequence. But
the current instruction will be completed before it responds to
the request. The interrupt mask bit of the condition code register
doesn't affect non-maskable interrupt at all.
When the interrupt occurs, the contents of the program counter, the index register, the accumulators and the condition code
register will be pushed onto the stack. Upon completion of this
sequence, a vector is fetched from $FFFC and $FFFD, transferred their contents to the program counter and the non-maskable
interrupt service routine starts. After reset, the stack pointer
should be initialized on an appropriate memory area before NMI
input.
•
Figure 13 Connection Circuit
•
Enable (E)
This pin provides a TTL-compatible clock used for bus synchronization. Its frequency is one fourth that of the internal oscillator or external clock. This pin can drive one TTL load and
90pF capacitance.
XTAL~--~------
EXTAL
address buses keep "High". If RES turns "High", the MCU restart sequence is:
(1) Latch the value of the mode program pins: MPo and MP I .
(2) Initialize each internal register (refer to Table 5).
(3) Set the interrupt mask bit. For the CPU to recognize the
maskable interrupts ~, IRQ; and IRQa, this bit should be
cleared in advance.
(4) Put the contents (=start address) of the last two addresses
($FFFE, $FFFF) into the program counter and start the
program from this address. (Refer to Table 1).
* The MCU is unable to accept a reset input until the clock becomes normal oscillation after power on (max. 20ms). During
this transient time, the MCU and I/O pins are undefined. Please
be aware of this for system designing.
Mode Program (MP o' MP 1)
These two pins decide the operation mode. Refer to "MODE
SELECTION" for more details.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
915
HD63701XO,HD637A01XO,HD637B01XO'---------------------Table 1 Interrupt Vector Memory Map
Priority
Highest
Lowest
Vector
Interrupt
MSB
LSB
FFFE
FFFF
RES
FFEE
FFEF
TRAP
FFFC
FFFD
NMI
FFFA
FFFB
SWI (Software Interrupt)
FFF8
FFF9
IRO t
FFF6
FFF7
ICI
FFF4
FFF5
OCI (Timer 1 Output Compare 1, 2)
FFF2
FFF3
TOI (Timer 1 Overflow)
FFEC
FFED
CMI (Timer 2 Counter Match)
FFEA
FFEB
IR0 2
FFFO
FFF1
SIO (RDRF+ORFE+TDRE)
(Timer 1 Input Capture)
Each Status Register's Interrupt
Enable Flag
"1"; Enable, "0"; Disable
--
IRQ,
IRQ2
ICF
...-...
OCF1
-0-
OCF2
_""-0-
-"
TOF
IRQJ
~
CMF
RDRF
""-0-
ORFE
TORE
""-0-
I
ICI
Condition
Code
Register
I-MASK
"O";Enable
"l",Disable
~ KY'"O
TOI
CMI
Interrupt
Request
~ Signal
~
---J
Edge
Detective
Circuit
Sleep
Cancel
Signal
TRAP
Address Error
Op Code Error
Detective Circuit
SWI
Figure 14 Interrupt Circuit Block Diagram
916
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63701XO,HD637A01XO,HD637B01XO
The following signal descriptions are applied only for expanded mode.
•
Read/Write (R/W; P 72 )
This signal, usually in read state ("High"), shows whether
the MCU is in read ("High") or write ("Low") state. This can
drive one TTL load and 30pF capacitance.
•
RD, WR (P 70 , P 71 )
Port 4 (EAo to EAIl ). In verification, the EPROM data is output
from Port 3 (EO o to E0 7 ) when this pin is "Low" level. In
"High" level, Port 3 will be high-impedance. In MCU mode, this
pin should be connected to Vss.
•
PORT
The HD63701XO has six 8-bit ports and a S-bit port. Table 2
gives the address of ports and the data direction register and Fig.
IS the block diagrams of each port.
These outputs will turn "Low" when the CPU read/write operation is completed. This enables the CPU easy to access the peripheral LSI with RD and WR input pins. These pins can drive
one TTL load and 30pF capacitance.
Port
Port Address
Data Direction Register
!DR;
Port 1
$0002
$0003
$0006
$0007
$0015
$0017
$0018
$0001
$0004
•
Load Instruction Register
Table 2 Port and Data Direction Register Address
P 73 )
Port 2
This is output for the instruction opecode on data bus (active
low). This pin can drive one TTL load and 30pF capacitance.
•
Port 4
This input is used to stretch the system clock's "High" period
in order to access low-speed memories. During this signal being
in "High", the system clock operates in normal sequence. But in
"Low", the "High" period of the system clock will be stretched
in integral multiples of the cycle time. This allows the CPU to interface with low-speed memories (See Fig. 2). Up to 9f.LS can be
stretched.
During internal address access or non valid memory access,
MR is prohibited internally to prevent decrease of operation
speed. Even in the halt state, MR can also stretch "High" period
of system clock to allow peripheral devices to access low-speed
memories. As this pin is used also for P52 , an enable bit is provided at bit 2 of the RAM/port S control register at $0014. Refer
to "RAM/PORT S CONTROL REGISTER" for more details.
•
Halt (HALT; P 53)
This input is used to stop instruction execution or to release
buses free. When this signal turns "Low", the CPU will be in
the halt state after completing the current instruction. During the
halt state, BA (P.H! is in "High", and an address bus, data bus,
RD, WR and R/W are high impedance. When an interrupt is requested in the halt state, the CPU responds to the interrupt request after the halt is cancelled.
(Note) When the CPU is interrupt wait state in WAI instruction
execution, HALT should be held "High". If HALT turns
"Low", the CPU may malfunction after releasing the halt
state. Refer to "APPLICATION NOTES" for details.
•
Port 3
Memory Ready (MR; P 52)
Port 5
Port 6
Port 7
•
-
Port 1
•
Port 2
An 8-bit input/output port. Its I/O state depends on the data
direction register (DDR) of port 2 which provides two bits; bit 0
decides the I/O direction of P20 and bit I the I/O direction of P21
to P27 ("0" for input, "I" for output).
Port 2 is also used for the timers and the SCI. When used for
the timers and the SCI, P21 to P27 are decided I/O regardless of
the DDR (except for P20 ).
Port 2 Data Direction Register
Bus Available (BA; P 74 )
The following pin functions are applied only in EPROM
mode. Refer to "THE EPROM PROGRAMMING" for details
of EPROM mode.
6
4
1
0
The DDR of port 2 is cleared at reset and port 2 is configured
as an input. This port can drive one TIL and 30pF. In addition,
it is capable of sinking ImA current at Vout= I.SV to drive directly the base of Darlington transistors.
Chip Enable (CE; P 57)
This pin is input for programming and verifying the EPROM.
When this pin is "Low" level, EPROM will be enable.
The EPROM can not be programmed or verified in "High"
level.
•
-
$0016
In MCU mode, port I is used for an 8-bit output port. In
mode 3, port 1 is high impedance during reset, and keeps the
state even after reset is released. When the CPU writes on the
port 1 data register, the written data will appear at Port 1. Once
port 1 gets in the output state, it operates as an outpllt till reset.
The CPU can read the Port 1 data register for the bit manipulation instruction.
In mode 1 and 2, port I is used for lower address buses. This
port can drive one TTL load and 90pF capacitance.
In EPROM mode, port 1 is lower address bus (EAo to EA 7 )
for the EPROM.
This output is normally "Low" but "High" when the CPU
accepts HALT and releases the buses. The HD6800 and HD6802
make BA "High" and release the buses at WAI execution, while
the HD6370lXO doesn't make BA "High" under the same condition.
•
-
Program Voltage/Output Enable (Vpp/OE)
This pin is used for program voltage and data output control
in verification.
Data from Port 3 (EO o to E07 ) can be programmed into the
EPROM when applying 2IV±0.SV to Vpp and holding CE in
"Low" level. The EPROM address is provided to Port 1 and
• Port 3
An 8-bit I/O port. I/O state depends on the DDR of Port 3
which has only one bit ("0" for input and "I" for output). It is
cleared at reset. In mode I and 2, port 3 is used for data bus.
This port can drive one TTL load and 90pF capacitance.
Port 3 is used for data bus (EO o to E07 ) of EPROM in
EPROM mode. In this case, I/O state of Port 3 is selected by OE
but not the DDR.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
917
HD63701XO,HD637A01XO,HD637B01XO---------------------
Port Write Signal
Port Write Signal
Data Bus
Data Bus
Mode 1.2
Address Bus.
Control Signal
-L
Address Bus.
Control Signal
Mode 1. 2
....L
Port 4 (Bit 4 to 7), Port 7
EPROM
Address Bus
Port 1, Port 4 (Bit 0 to 3)
Data Bus
Port 5
Data Bus
Data Bus ------'~'---
CPU Internal Bus
_-----...J
EPROM Mode
-L
EPROM
Data Bus
Port 5 (Bit 7)
Port 3
Port Write Signal
Data Bus
Timer 1. 2.,,--i-_ _ _....J
SCI Output
Port Read Signal
-L
~~~~~~~~.----------<
Port 6, Port 2 (Bit 0)
Port 2
Figure 15 Port Block Diagram
918
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63701XO,HD637A01XO,HD637B01XO
Port
3 Data Direction Register
4
6
is set at reset.
o
3
Port 4
In MCU mode, port 4 is used for an 8-bit output port like
Port 1. In mode 1 and 2, it is used for upper address bus.
In EPROM mode, P40 to P43 are used for upper address bus
(EAs to EA Il ) of EPROM.
•
Port 5
An 8-bit input port. The lower 4 bits are used for interrupt,
for the EPROM control.
MR, HArT, and P57 is
cr
(Note) When using P52 and PS3 for port in mode 1 and 2, MRE
and MLTE must be cleared after reset. If PS2 or P53 turns
"Low" before MRE and HL TE are cleared, the memory
ready function or the halt function will not be prohibited.
Bit 4. Bit 5
Bit 6
•
Port 6
An 8-bit I/O port. This port is programmable as either input
or output under software control of the corresponding the DDR
("0" for input, "1" for output). This port can drive one TTL
load and 30pF. The DDR of port 6 is cleared at reset. In addition, it is capable to sinking ImA current at Vout= 1.5V to drive
directly the base of Darlington transistors.
•
Port 7
A 5-bit output port. In mode 3, port 7 is high impedance during reset and keeps the state even after reset is released. When
the CPU writes on the port 7 data register, the written data will
appear at Port 7. Once port 7 gets in the output state, it operates
as an output till reset. The CPU can read the data register for the
bit manipulation instruction. In this case b7 to b5 are "1".
In mode 1 and 2, port 7 is used for control signals (RD, WR,
R/W", m and BA). This port can drive one TTL load and 30pF.
•
RAM/PORT 5 CONTROL REGISTER
The control register located at $0014 controls on-chip RAM
and port 5.
RAM/Port 5 Control Register
7
6
4
3
2
1
0
o. Bit 1
Bit 7
IRQ,. IRQ 2 Enable Bit ORQ,E. IRQ2E)
•
MODE SELECTION
The HD63701XO provides two fundamental modes, MCU
mode and EPROM mode. MCU mode is grouped into three; two
expanded modes (mode 1, mode 2) and a single chip mode
(mode 3).
These operating modes are selectable by mode program pins,
MPo and MP1 , and standby pin, STBY as shown in Table 3.
•
Mode 1 (Expanded Mode)
In this mode, Port 3 is data bus, Port 1 is lower address bus
and Port 4 is upper address bus to interface with the HMCS6800
buses. Port 7 is used for control signal such as R/W. In mode 1,
the EPROM is disable and external address space are expandable
up to 65k bytes (refer to Fig. 16).
•
Mode 2 (Expanded Mode)
for Memory Ready signal, write
the memory ready function is
In mode 3, the memory ready
of the value of this bit. This bit
Mode 3 (Single-chip Model
In this mode, all ports are available (refer to Fig. 18).
•
Memory Ready Enable Bit (MRE)
When using P52 for an input
"1" in this bit. When "0",
prohibited and PS2 is for port.
function is prohibited regardless
Standby Power Bit (STBY PWR)
This bit is cleared whenever Vee decreases below VRAM
(min). This is a read/write status bit by software. If this bit is set
before standby mode, it indicates that Vee is applied and the
RAM is valid.
This mode is also expanded mode. But in mode 2, address
space is expandable up to 61k bytes and the EPROM is enable
(refer to Fig. 17).
When using P50 and P51 for interrupt pins, write "1" in these
bits. When "0", the CPU doesn't accept an external interrupt or
a sleep cancellation by the external interrupt. These bits are
cleared at reset.
Bit 2
Not Used.
RAM Enable (RAM E)
The RAM is controlled by this bit. It is set at reset and the
RAM is enabled. This bit is programmable by software. When
the RAM is disabled (=Iogic "0"), the CPU can access an external memory. This bit should be cleared at the beginning of
standby mode to protect the RAM data.
•
Bit
Halt Enable Bit (HL TEl
When using PS3 for an input for Halt signal, write "1" in this
bit. When "0", the halt function is prohibited. In mode 3, the
halt function is prohibited regardless of the value of this bit. This
bit is set at reset.
1•
Bit 3
EPROM Mode
In this mode, the EPROM can be programmed. Refer to
"PROGRAMMING THE EPROM" for details.
•
Mode and Ports
Table 4 shows the MCU signals in each mode.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
919
HD63701XO,HD637A01XO,HD637B01XO--------------------Table 3 Mode Selection
MPI
MPo
STBY
EPROM
1
"L"
"H"
*
E
RAM
I (Note 1)
2
"H"
"L"
I
I (Note
I
I
Mode
MCU Mode
3
EPROM Mode
"H"
"H"
*
*
"L"
"L"
"L"
Interrupt Vector
E
1)
Operation Mode
Expanded Mode
I
Expanded Mode
I
I
Single-chip Mode
*
*
EPROM Programming Mode
"L"=Logic "0" "H"=Logic "1" I· Internal E· External *. Don't care
(Note 1) The RAM address area'will be ext~rn~1 by clea;ing RAME bit at $0014.
Table 4 MCU Signals in Each Mode
~
MCU Mode
Mode 1
Port
EPROM Mode
Mode 3
Port 1
Address Bus (Ao - A7)
Address Bus (A'o - A7)
Output Port
Port 2
I/O Port
I/O Port
I/O Port
Address Bus (EAo - EA7)
No use (Note 3)
Port 3
Data Bus (Do -07)
Data Bus (Do - 07)
I/O Port
Data Bus (EOo ,..., E07)
Port 4
Address Bus (As - A1s )
Address Bus (As - AIS )
Output Port
Port 5
Input Port
Input Port
Input Port
Address Bus (EAs -EAll)
CE (PS7) (Note 2)
Port 6
I/O Port
I/O Port
I/O Port
No use
(Note 3)
Output Port
No use
(Note 3)
Port 7
(Note 1)
(Note 2)
(Note 3)
920
Mode 2
RD, WR, RIW, UR, BA
RD, WR, R/W, UR, BA
(Note 1)
Use only 4 pins P4G to p.,. p .. to p. 7 are not used.
7 pins PSG to P56 are not used.
Unused ports should be connected to VSS.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63701XO,HD637A01XO,HD637B01XO
Vee
Vee
E
E
lID
1m
WR
CJ
R/JV
RES
BA
Port 1
8 Address Bus
MR. HAIi
Port 4
8 Address Bus
Port S
81/0 Lines
BA
NMi
Port 3
8 Data 8us
81R&;~~
R/W
lIR
RrS
STBY
OR
STBY
NMI
Port 2
81/0 Lines
Timer 1,2
SCI
Port 5
WR
0
Figure 16 MCU Mode; Mode 1
Port 2
8 I/O Lines
Timer 1, 2 SCI
Port 5
8!..!!2!!t Lines
IRQ" i1m2
MR, HALl
PortS
81/0 Lines
Port 3
8 Data Bus
Port 1
8 Address Bus
Port 4
8 Address Bus
Figure 17 MCU Mode; Mode 2
Vee
Vee
MPo
MP,
CI
Port 2
8 I/O Lines
Timer 1,2 SCI
Port 5
8 Input Lines
Port 7
5 Output Lines
Port 3
81/0 Lines
STBY
HD63701XO
MCU
Port 1
8 Output Lines
Port 1
8 Address Bus
nm;: i1m2
PortS
8 1/0 Lines
Port 4
8 Output Lines
Figure 18 MCU Mode; Mode 3
Port 3
8 Data Bus
Port 4
4 Address Bus
Figure 19 EPROM Mode
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
921
HD63701 XO,HD637 A01 XO,HD637B01 X O - - - - - - - - - - - - - - - - - - - - •
ing mode is shown in Fig. 20. The first 32 locations of each map
are reserved for the MCV's internal register area, as shown in
Table 5.
MEMORY MAP
The MCV has ability to access a 65k byte memory space depending on the operating mode. A memory map for each operat-
Table 5 Internal Register
Address
R/W***
Registers
-
00
-
Port 2 Data Direction Register
-
W
$FC
Port 1
RIW
Undefined
Port 2
R/W
Undefined
W
$FE
01
02*
03
04*
Port 3 Data Direction Register
05
06*
Initialize at RESET
-
-
-
Port 3
RIW
Undefined
07*
Port 4
RIW
Undefined
08
Timer Control/Status Register 1
RIW
$00
09
Free Running Counter ("High")
RIW
$00
OA
Free Running Counter ("Low")
RIW
$00
OB
Output Compare Register 1 ("High")
RIW
$FF
OC
Output Compare Register 1 ("Low")
R/W
$FF
00
Input Capture Register ("High")
R
$00
OE
Input Capture Register ("Low")
R
$00
OF
Timer Control/Status Register 2
RIW
$10
10
Rate, Mode Control Register
R/W
$00
11
Tx/Rx Control Status Register
RIW
$20
12
Receive Data Register
R
$00
13
Transmit Data Register
W
14
RAM/Port 5 Control Register
15
Port 5
R
16
Port 6 Data Direction Register
W
$00
17
Port 6
RIW
Undefined
18*
Port 7
RIW
Undefined
19
Output Compare Register 2 ("High")
RIW
$FF
1A
Output Compare Register 2 ("Low")
RIW
$FF
1B
Timer Control/Status Register 3
RIW
$20
1C
Time Constant Register
10
Timer 2 Up Counter
1E
1F**
Test Register
-
RIW
$00
$7C or $FC
-
W
$FF
RIW
$00
-
-
-
• External Address in Mode 1, 2 .
•• Test Register. Do not access to this register.
••• R : Read Only Register
W : Write Only Register
R/W: Read/Write Register
922
$HITACttl
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63701XO,HD637A01XO,HD637B01XO
EPROM Mode
MCU Mode
HD63701XO
Expanded Mode
SOOOO
$001F
HD63701XO
Expanded Mode
Mode 1
Internal'
Register
External
Memory
Mode 2
~::..::.o:;~~ ]
Internal'
Register
External
HD63701XO
Single-chip Mode
Mode 3
HD63701XO
SOOOO_J Inte~nal
SOO 1F
Register
SOI)4CII2:;~~~~i ~;:~ry
S OO401~~~~11 Space
Internal
RAM
Internal
RAM
Internal
~~~~;
$OOFF ~
SOOFF
RAM
External
Memory
Space
External
Memory
Space
Internal
EPROM
$FFFF ~:;.c..::~~.. )
$FOOO~~~~1
$FFFF
~~~~JJ
$FOOO
Internal
EPROM
II}
$FFFF
$000
Internal
EPROM
$FFF
• Excludes the following addresses
which may be used externally:
$02, $04, $06, $07, $IB.
• Excludes the following addresses
which may be used externally:
$02, $04, $06, $07, $IB.
Figure 20 HD63701XO Memory Map
• THE EPROM PROGRAMMING
The HD63701XO does not operate as the MCU in EPROM
mode, which allows to be programmable as equivalent EPROM
2732A type. When three pins, MPo, MP1 and STIJY should be
held low, the MCU will be in EPROM mode as shown in Table
3. In this mode, P30 to P37 are used for data bus, P IO to P17 al}d
P40 to P43 for address bus, and PS7 for CE input shown Fig, 19.
Refer to "APPLICATION NOTES" for the EPROM.
•
Programming/Verification
When CE pin is held low after the program voltage (V pp) is
applied to ~/OE pin, the data byte can be applied to Port 3.
When Vpp/OE pin and CE pin are held low after programming,
the programmed data is output from Port 3 and user can verify
the data. 110 timing of these signals are referred to Fig. 12.
When CE pin is returned to high, Port 3 will be tri-state and
EPROM programming/verification will be inhibited.
Table 6 shows the condition of the each pin is EPROM mode.
Unused pins should be connected to GND in EPROM mode.
•
Erasure (applied only for the ceramic package with a window)
Erasure of EPROM begins to occur when the LSI is exposed
to ultraviolet light (wavelength: 2537A, an integrated does of at
least: 1.5W·sec/cm). Exposing the LSI to an ultraviolet lamp of
1,200 p.. W/cm2 rating for 20 to 30 minutes, at a distance of about
1 inch, should be sufficient.
(Note) If the window is stained, erasure tin1e will be extended.
Remove stains from the window with a solvent which
has no influence on the package like alcohol. Don't rub
the window hard but wipe out softly.
(Note for the plastic package)
It is impossible to erase the programmed EPROM of
the plastic molded HD63701XO. Refer to "APPLICATION NOTES" for the plastic package.
Table 6 Pin Condition in EPROM mode
~
Vcc
Vss
Vpp/OE
CE
P30 to P37
PlOtOP17
P40 to P43
MPo, MPI , STBY
33
1
42
24
51 to 58
43 to 50
38 to 41
4,5,7
Programming
+5
GND
Vpp
"L"
Data input
Address input
+5
GND
"L"
"L"
Data output
Address input
"L"
"L"
GND
Verification
"H"
High
impedance
Don't care
"L"
GND
No,
Mode
Inhibition of
programm ing/verification
+5
GND
Don't care
Other pins
GND
"H"; VIH level, "L": VIL level
• TIMER 1
The HD63701XO has a 16-bit programmable timer which can
simultaneously measure an input waveform and generate two
independent output waveforms. The pulse width can vary from
several microseconds to many seconds.
Timer 1 is configura ted as follows (refcr to Fi~. 22).
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
923
HD63701XO,HD637A01XO,HD637B01XO-----------------------------------------Control/Status Register 1 (8 bit)
Control/Status Register 2 (7 bit)
Free Running Counter (16 bit)
Output Compare Register 1 (16 bit)
Output Compare Register 2 (16 bit)
Input Capture Register (16 bit)
•
Timer Control/Status Register 1
Bit 0
Free-Running Counter (FRC) ($0009 : OOOA)
The key timer element is a 16-bit Free-Running Counter
which is incremented by system clock (E). The counter value is
readable by software without affecting the FRC. It is cleared by
reset.
A write to the high byte of the FRC ($09) will preset the high
and low byte of the FRC to $FFF8 . A continuous write to the
high and low byte FRC, however, will set them to the write data.
The FRC write timing will be as follows when double store instructions (STD, STX etc.) execute.
Bit 1
$5AF3
Bit 4
•
Counter Write Timing
Bit 5
EOCll
Enable Output Compare Interrupt 1
EICI
Enable Input Capture Interrupt
TOF
Timer Overflow Flag
This read only bit is set when the FCR contains all
1'so It is cleared by reading the TCSRI followed by the
FCR's high byte ($0009).
Output Compare Register (OCR)
($0008, $OOOC; OCR1) ($0019, $001A; OCR2)
Input Capture Register nCR) ($0000 : OOOE)
The Input Capture Register is a 16-bit read only register used
to store the FRC when an external input transition occures defmed by input edge bit (IEDG) in the TCSRI.
In order to input the external signal to the edge detective circuit, Port 20 should be configured as an input. When an input
capture occures at the next cycle of a read the high-byte of the
ICR, the input capture will delay one cycle. In order to ensure
the input capture, a read to the ICR needs 2-byte transfer instruction, and the input pulse width should be at least 2 system
cycles. This register is cleared ($0000) at reset.
•
Enable Timer Overflow Interrupt
When this bit is set, an internal interrupt ORQa) is
enabled for leI. When cleared, the interrupt is inhibited.
The Output Compare Register is a 16-bit read/write register
used to control an output waveform. It is always compared with
the FRC on each E-cycle.
When a match is found, Output Compare Flag (OCF) in the
Timer Control/Status Register (TCSR) is set. If an output enable
bit (OE) in the TCSR2 is "1", an output level bit (OLVL) in the
TCSR will appear at Port 21 (Tout 1) or Port 25 (Tout 2).
The OCR and OL VL can then be changed for the next compare. The OCR is set to $FFFF at reset. The compare function is
inhibited for a cycle after a write to the OCR or to the high byte
of the FRC. This is to set the 16-bit value valid in the register for
compare. In addition, it is because $FFF8 is set at the next cycle
of a write to the high byte of the FRC.
• For a write to the FRC or the OCR, 2-byte transfer instruction (such as STX etc.) should be used.
•
ETOI
When this bit is set, an internal interrupt ORQa) is
enabled for OCIL When cleared, the interrupt is
inhibited.
In the case of a write ($5AF3) to the FRC.
Figure 21
Input Edge
When this bit is set, an internal interrupt ORQa) is
enabled for TOL When cleared, the interrupt is inhibited.
$OA Write
$FFF8
IEDG
This bit controls which level transition will trigger the
FCR transfer to the ICR. For this function, the DDR
corresponding to Port 20 should be cleared.
IEDG=O, transferred on a negative edge
IEDG= 1, transferred on a positive edge
Bit 3
Counter value
Output Level 1
When a match is found between the FCR and the
OCRI, OLVLl will appear at Port 21 if OEl, bit 0 of the
TCSR2, is set.
Bit 2
$09 Write
OL VL 1
Bit 6
OCFl
Output Compare Flag 1
This read only bit is set when a match is found between the OCRI and the FRC. It is cleared by writing to
the OCR I ($OOOB or $OOOC) followed by reading the
TCSR 1 or TCSR2.
Bit 7
ICF
Input Capture Flag
This read only bit is set to indicate a level transition
defined by IEDG. It is cleared by reading the high byte
($OOOD) of the ICR followed by the TCSRI or TCSR2.
•
Timer Control/Status Register 2 (TCSR2) ($OOOF)
The Timer Control/Status Register 2 is a 7-bit register. All
bits are readable while the lower 4 bits can be written. The upper
3 bits indicate the following timer's status.
Bit 5 A match has been found between the FRC and the
OCR2 (OCF2).
Bit 6 The same flag as the OCFI of the TCSRI.
Bit 7 The same flag as the ICF of the TCSRI.
The followings are each bit descriptions.
Timer Control/Status Register 2
76543210
ICF \ OCF1\ OCF21
-
IEOCI2fLVL2\ OE2\ OE 1 \ $OOOF
Timer Control/Status Register 1 (TCSR1) ($0008)
The Timer Control/Status Register 1 is an 8-bit register of
which all bits are readable while the lower 5 bits can be written.
The upper 3 bits indicate the following timer's status.
Bit 5 The FCR has overflowed. (TOF).
Bit 6 A match has been found between the FCR and the OCR
I (OCFt).
Bit 7 A level transition of the timer input has been detected
(ICF).
The followings are each bit descriptions.
924
Bit 0
OE 1
Output Enable 1
If this bit is set, the OLVLl wi\1 appear at Port 21
when a match is found between the FCR and the OCR 1.
When it is cleared, Port 21 will be I/O port. When set, it
will be an output of OLVLl automatically.
Bit 1
OE2
Output Enable 2
If this bit is set, the OL VL2 wi\1 appear at Port 25
when a match between the FCR and the OCR2. When
this bit is cleared, Port 25 will be I/O port. When set, it
will be an output of OL VL2 automatically.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63701XO,HD637A01XO,HD637B01XO
Bit 2
OL VL2
Bit 6
Bit 7
Output Level 2
OL VL2 is transferred to Port 25 when a match is
found between the FCR and the OCR2. If OE2, bit 5 of
the TCSR2, is set, OL VL2 will appear at Port 25.
Bit 3
EOCI2
OCFI and ICF addresses are partially decoded. CPU
read of the TCSRlITCSR2 makes it possible to read
OCFI and ICF into bit 6 and bit 7.
Both the TCSRI and TCSR2 will be cleared by reset.
Enable Output Compare Interrupt 2
When this bit is set, an internal interrupt (IRQa) is
enabled for OCI2. When cleared, the interrupt is
inhibited.
Bit 4
Bit 5
OCFl
Output Compare Flag 1
ICF Input Capture Flag
(Note) If OEI or OE2 is set before the first output compare
match is found after reset, Port 21 and Port 25 will output "0" respectively.
(Note) Because the set condition of ICF precedes its reset condition, ICF is not cleared when the set condition and the
reset condition occur simultaneously. The same phenomenon applies to OCFI, OCF2 or TOF respectively.
Not Used
OCF2
Output Compare Flag 2
This read-only bit is set when a match is found between the FCR and the OCR2. It is cleared by writing to
the OCR2 ($0019 or $OOIA) followed by reading the
TCSR2.
Figure 22 Timer 1 Block Diagram
•
put the data to it.
TIMER 2
In addition to the timer I, the HD6370lXO provides an 8-bit
reloadable timer, which is capable of counting the external event.
This timer 2 contains a timer output, so the MCU can generate
three independent waveforms. (Refer to Fig. 23.)
The timer 2 is configured as follows:
Control/Status Register 3 (7 bit)
8-bit Up Counter
Time Constant Register (8 bit)
•
Timer 2 Up Counter (T2CNT) ($0010)
This is an 8-bit up counter which is incremented by the clock
controlled by CKSO and CKSI of the TCSR3. The T2CNT is
always readable without affecting itself. In addition, any value can
be written to the T2CNT by software even during counting.
The counter is cleared when a match is found between the
T2CNT and the TCONR or by reset.
A write to the T2CNT at the clear cycle does not reset it but
•
Time Constant Register (TCONR) ($OOl'C)
The Timer Constant Register is an 8-bit write only register. It
is always compared with the T2CNT.
When a match has been found, counter match flag (CMF) of
the Timer Control/Status Register 3 (TCSR3) is set and the
value selected by TOSO and TOSI of the TCSR3 will appear at
Port 26. When CMF is set, the FCR will be cleared simultaneously and then a counting starts from $00. This enables regular interrupts and waveform outputs without any software support. The TCONR is set to "$FF" by reset.
•
Timer Control/Status Register 3 (TCSR3) ($001 B)
The Timer Control/Status Register 3 is a 7-bit register. All
bits are readable while 6 bits except for CMF can be written.
~HITACHI
\ Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
925
HD63701XO,HD637A01XO,HD637B01XO---------------------
...----- Timer1 FRC
...- - - - - Port 2
Bit 7
.--+---I-----~- Port 2
Bit 6
Figure 23 Timer 2 Block Diagram
The followings are each bit descriptions.
Bit 2
Bit 3
TOSO
TOS 1
Timer Output Select 0
Timer Output Select 1
When a match is found between the T2CNT and the
TCONR, timer 2 output selected by these bits shown in
Table 8 will appear at Port 26. When both TOSO and
TOS 1 are cleared, Port 26 will be an I/O port.
Timer Control/Status Register 3
16543210
ICMF IECMII -I T2E ITOSllTosolCKSllCKSol $0018
Table B Timer 2 Output Select
Bit 0
Bit 1
CKSO
CKS 1
Input Clock Select 0
Input Clock Select 1
TOS1
TOSO
0
0
Timer Output Inhibited
0
1
Toggle Output·
1
0
Output "0"
1
1
Output "1"
An input clock to the T2CNT is selected by these bits
as shown in Table 7. When an external clock is selected,
Port 27 will be an input automatically. The positive edge
of the external clock increments the T2CNT. The maximum external clock is half of the system clock frequency.
Table 7 Input Clock Select
• When a match is found between the T2CNT and the TCONA, timer 2
output level is reversed. This leads to production of a square wave with
50% duty to the external without any software support.
Input Clock to the Counter
CKSl
CKSO
0
0
1
0
E clock
1
E clock/B*
0
E clock/12B*
1
1
External clock
• These clocks come from the FAC of the timer 1. If one of these clocks
il selected 81 8n input clock to the up counter, a write to the FAC of
the timer 1 should be inhibited.
Bit 4
T2E
Timer 2 Enable Bit
When this bit is cleared, the T2CNT will stop. When
set, a clock selected by CKSI and CKSO (Table 7) provides to the T2CNT.
(Note) P26 is "0" when T2E is cleared and P26 is configured as
an output by TOSI or TOSO. It also is "0" when T2E is
set and P26 is configured as an output before the first
counter match.
Bit 5
Bit 6
926
Timer Output
Not Used
ECMI Enable Counter Match Interrupt
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63701XO,HD637A01XO,HD637B01XO
When this bit is set, an internal interrupt (IRQa) is
enabled for CM!. When cleared, the interrupt is inhibited.
Bit 7
CMF
Counter Match Flag
This read only bit is set when a match is found between the T2CNT and the TCONR. It is cleared by writing "0". (It cannot be written "1" by software).
Each bit of the TCSR3 is cleared by reset.
•
SERIAL COMMUNICATION INTERFACE (SCI)
The HD63701XO SCI provides two operation modes; one is
an asynchronous mode by the NRZ format and the other is a
clocked synchronous mode to transfer data synchronizing with
the serial clock.
The serial interface is configured as follows:
Transmit/Receive Control and Status Register (TRCSR)
Rate/Mode Control Register (RMCR)
Receive Data Register (RDR)
Receive Data Shift Register (RDSR)
Transmit Data Register (TDR)
Transmit Data Shift Register (TDSR)
The SCI is initialized by software. The procedure is usually as
follows:
1) Write a operation mode into each corresponding control
bit of the RMCR.
2) Write a operation mode into each corresponding control
bit of the TRCSR.
When setting the baud rate and operation mode, TE and RE
should be "0". When TE and RE is set again, more than 1 bit
cycle of the current baud rate is necessary. If set in less than 1 bit
cycle, the SCI cannot be initialized occasionally.
•
Asynchronous Mode
An asynchronous mode contains the following two data formats:
1 Start Bit + 8 Bit Data + 1 Stop Bit; 8 Bit Data Format
1 Start Bit + 9 Bit Data + 1 Stop Bit; 9 Bit Data Format
In 9 Bit Data Format, if the 9th bit is "1", the format of
1 Start Bit + 8 Bit Data + 2 Stop Bit
The SCI is initialized by writing desirable control bytes to the
RMCR and then to the TRCSR.
The transmit operation is enabled by TE in the TRCSR.
W~en T~ is set, the output of the TDSR is connected to P24
which will be configured as an output regardless of the DDR,
and then the serial output is initiated by transmitting to a 10-bit
preamble of "1" in the 8 Bit Data Format or an ll-bit preamble
of "1" in the 9 Bit Data Format. Following the preamble, the internal synchronization is established and the transmitter section
is ready for operation.
At this point one of two situation exist:
1) If the TDR is empty (TDRE= I), a continuous string of
ones will be sent indicating an idle line.
2) If a byte has been written to the TDR (TDRE=O), it is
transferred to the TDSR, TDRE will be set and transmission will begin.
During the transfer itself, the start bit (0) is first transmitted.
Then the 8 data bits or the 9 data bits (beginning with bit 0) followed by the stop bit (1) are transmitted. When the TDR has
been emptied, TDRE is set.
If the MCV fails to respond to the flag within the proper time,
(TDRE is still set when the next normal transfer from the TDR
to the TDSR should occure) then a "1" will be sent (instead of a
"0") at start bit time, followed by more 1's until more data is
supplied to the TDR. No O's will be sent while TDRE remains as
"1".
The receive operation 'is enabled by RE which configures P2a .
The receive operation is controlled by the contents of the
TRCSR and the RMCR. The receiver bit interval is divided into
8 sub-intervals for internal synchronization. The received bit
stream is synchronized by the first "0" (space) encountered. The
approximate center of each bit time is strobed during the next 10
bits.
If the tenth bit is not a "1" (stop bit), a framing error is assumed and ORFE is set. If the tenth bit is a "1", the data is
transferred to the RDR and interrupt flag RDRF is set. If RDRF
is still set at the next tenth bit time, ORFE will be set, indicating
an over-run has occurred. When the CPU responds to either flag
HD63701XO Internal Data Bus
Transmit/Receive Control and Status Register
(TRCSRI
Tlmerl FRC
Tlmer2
Up Counter
Figure 24 Serial Communication Interface Block Diagram
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
927
HD63701XO,HD637A01XO,HD637B01~0---------------------
(RDRF or ORFE) by reading the TRCSR followed by reading
the RDR, RDRF (or ORFE) will be cleared.
(Note) Clock Source in Asynchronous Mode
When using an internal clock for the SCI, the following
requirements are applicable:
Set CC1 and CCO to "1" and "0" respectively.
A clock is generated regardless of the value of TE,
RE.
The maximum clock rate is E+ 16.
The output clock is the same as the bit rate.
When using an external clock for the SCI, the following
requirements are applicable:
Set CC1 and CCO in the RMCR to "1" and "1" respectively.
The external clock should be set 16 times the desired
baud rate.
the maximum clock frequency is the same as the system clock.
•
Clocked Synchronous Mode
In the clocked synchronous mode, the transmit operation is
synchronized with the clock pulse. In the clocked synchronous
mode an SCI clock 110 pin is only P22 , so the receive and transmit operation cannot be simultaneously enabled. Therefore, TE
and RE should not be set simultaneously. Fig. 25 gives a synchronous clock and a data format in the clocked synchronous
mode.
The transmit operation is enabled by TE in the TRCSR. P24 is
configured as an output regardless of the value of the corresponding OOR.
Both the RMCR and TRCSR should be set in the desirable
operating conditions for data transmit.
If the user wishes to provide an external clock, the data bits
(beginning with bit 0) are transmitted from Pw synchronizing
with 8 clock pulses supplied to P22 , when TORE is "0". TDRE is
set when the TOSR is "empty". More the 9th clock pulse is ignored.
Transmit Direction
Synchronous
clock
Data
~NotValid
• Transmit data is sent between the negative edge of a synchronous clock and the next negative edge .
• Receive data is latched at the positive edge.
Figure 25 Clocked Synchronous Mode Format
available. By this, uninterested MCU can inhibit all
further receive processing till the next message starts.
Then wake-up function is triggered by consecutive 1's
with 1 frame length 00 bits for the 8-bit data format, or
11 bits for the 9-bit data format). The software protocol
should provide the idle time between messages.
By setting this bit, the MCU stops data receive till the
next message. The receive of consecutive "1" with one
frame length wakes up and clears this bit and then the
MCU restarts the receive operation. However, the RE
flag should be set before setting this bit. In the clocked
synchronous mode WU is not available, so this bit should
not be set.
The receive operation is enabled by RE. P22 is configured as
an input for the 8 bit external clock and P23 is configured as an
input for the receive data. The operating mode of data receive is
decided by the TRCSR and the RMCR.
If the external clock is provided, RE should be set when P22 is
"High". The receive data is transferred to the ROSR by this
clock, and RDRF is set. More the 9th clock pulse are ignored.
When RORF is cleared by reading the ROR, the MCU starts receiving the next data.
RDRF, therefore, should be cleared with P22 "High". When
the first byte data is received, RDRF is set. After the second
byte, the recejye operation is enabled by clearing RORF.
•
Bit 1
Transmit/Receive Control and Status Register (TRCSR)
($0011)
The TRCSR is an 8 bit register which is readable. Bits 0 to 4
are also writable. This register i$ initialized to $20 by reset. Each
bit functions as follows.
Transmit/Receive Control Status R.egister
6
4
TE
Bit 0
WU
I
wu 1$0011
Wake-up
Transmit Enable
When this bit is set, transmit data will appear at P24
after one frame preamble in asynchronous mode, while in
clocked synchronous mode appear immediately. This is
executed regardless of the value of the corresponding
OOR. When TE is cleared, the serial 110 doesn't affect
P24 ·
TIE
Transmit Interrupt Enable
When this bit is set, an internal interrupt (IRQa) is
enabled when TORE (bit 5) is set. When cleared, the interrupt is inhibited.
o
In a typical multi-processor configuration, the software
protocol will usually identify the address at the beginning
of the message. In order to permit uninterested MCU's
to ignore the remaining message, a wake-up function is
928
Bit 2
TE
Bit 3
Bit 4
RE
Receive Enable
When set, P2a is configured as an input for the receive
operation regardless of the value of the OOR. When RE
is cleared, the serial I/O doesn't affect P2a .
RIE
Receive Interrupt Enable
When this bit is set, an internal interrupt, IRQa is
enabled when RORF (bit 7) or ORFE (bit 6) is set.
When cleared, the interrupt is inhibited.
Bit 5
TORE
Transmit Data Register Empty
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63701XO,HD637A01XO,HD637B01XO
TDRE is set when the TDR is transferred to the
TDSR in the asynchronous mode, while it is set when
the TDSR is "empty" in clocked synchronous mode.
This bit is cleared by reading the TRCSR and writing the
new transmit data to the TDR. TDRE is set by reset.
(Note) TE should be set before clearing TDRE.
Bit 6
OR FE
Rate/Mode Control Register
RDRF
Receive Data Register Full
RDRF is set when the RDSR is transferred to the
RDR. Cleared when reading the TRCSR, then the RDR,
or by reset.
(Note) When a few bits are set between bit 5 to bit 7 in the
TRCSR, a read of the TRCSR is sufficient for clearing
those bits. It is not necessary to read the TRCSR everytime to clear each bit.
•
6
TOsl
5
4'
3
2
1
0
SS21 CC21 CCl 1cco 1SSl 1SSO 1$0010
Overrun Framing Error
ORFE is set when an overrun or a framing error is occured (during data receive only). An overrun error occurs
when a new receive data is ready to be transferred to the
RDR with RDRF still set. A framing error occurs when a
stop bit is "0". But in clocked synchronous mode, this
bit is not affected. This bit is cleared when reading the
TRCSR, then the RDR, or by reset.
Bit 7
7
ADS
I I
°
Bit
Bit 1
Bit 5
In addition, if 9-bit data format is set in the asynchronous
mode, the 9th bit is put in this register. All bits are readable and
writable except bit 7 (read only). This register is cleared by reset.
These bits select the baud rate when using the internal clock.
Table 9 lists the available bit times and baud rates. The timer 1's
FRC (SS2=0) and the timer 2's up counter (SS2;= 1) provide
Speed Select
the internal clock for the SCI. When the source of the SCI internal clock is the timer 2's up counter, the desired baud rates may
be selected by the TCONR shown in Table 10.
(Note) When operating the SCI with internal clock, do not write
to the counter which is the source of the SCI clock.
Rate/Mode Control Register (RMCR)
The RMCR controls the followings:
. Baud Rate
. Data Format
. Clock Source
. p 22 Function
SSO}
SSl
SS2
Bit 2
Bit 3
CCO}
CCl
Bit 4
CC2
Clock Control/Format Select-
These bits select the data format and the clock source (refer
to Table 11).
• CCO, CCI and CC2 are cleared and the MCV will be in
the clocked synchronous mode (the external clock operation) by reset. Then P22 is forced to be configured as an
input for the clock. If using P22 for an output, the DDR of
port 2 should be set to "I" and eCl, CCO must be set to
"01".
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
929
HD63701XO,HD637A01XO,HD637B01XO-----------------------------------------Table 9 SCI Bit Times and Rates
( 1) Asynchronous Mode
XTAL
2.4576MHz
4.0MHz
E
614.4kHz
1.0MHz
4.9152MHz
1 2288MHz
SS2
SS1
SSO
0
0
0
E-;-16
26 ~s/38400Baud
16Jis/62500Baud
0
0
1
E-;-128
208 Jis/4800Baud
128"s/7812.5Baud
104.21,S/9600Baud
0
1
0
E';-1024
1.67ms/600Baud
1.024ms/976.6Baud
833.3Jis/1200Baud
3.333ms/300Baud
0
1
1
E-;-4096
6.67ms/150Baud
4.096ms/244.1 Baud
1
-
-
-
*
*
131,s/76800Baud
*
* When SS2 is "I", Timer 2 provides SCI ciocks. fhe baud rate is shown as follows with the
Baud Rate
f
32 (N+l)
(
TCONR as N.
f: input clock frequency to the)
timer 2 counter
=0 -
N
255
(2) Clocked Synchronous Mode *
4.0MHz
6.0MHz
8.0MHz
1.0MHz
1.5MHz
20MHz
0
E
E..;-2
2 1,s/bit
1.33I's/bit
1Jis/bit
0
1
E-;-16
16Jis/bit
1071's/bit
8 Ji s/bit
0
1
0
E";-128
64l's/bit
1
1
E";-512
128 s/bit
"
512Jis/bit
85.3Jis/bit
0
341"s/bit
1
-
256 Ji s/bit
-
**
**
**
XTAL
SS2
SSl
SSO
0
0
0
-
* Bit rates in the case of internal clock operation. In the case of external clock operation, the external clock is
operatable up to DC - 1/2 system clock.
** The bit rate is shown as follows with the TCONR as N.
.
.
BIt Rate (lls/ b1t )
(N+l)
= -4 f(
f: i~put clock frequency to the)
hmer 2 counter
N
=0 -
255
Table10 Baud Rate and Time Constant Register Example
~L
Baud Rate (Baud
110
150
300
600
1200
2400
4800
9600
19200
38400
2.4576MHz
3.6864MHz
4.0MHz
4.9152MHz
8.0MHz
21"
127
63
31
15
7
3
1
0
32"
191
95
47
23
11
5
2
35"
207
103
51
25
12
70"
51"
207
103
51
25
12
-
-
43"
255
127
63
31
15
7
3
1
0
~-
-
-
-
·Eta clock is provided to the timer 2'5 up counter.
930
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
I
---------------------HD63701XO,HD637A01XO,HD637B01XO
Table 11 SCI Format and Clock Source Control
CC2
CCl
CCO
Format
Mode
Clock Source
Port 2, Bit 2
0
0
0
a-bit data
Clocked Synchronous
External
Input
0
0
1
a-bit data
Asynchronous
Internal
Not Used**
0
1
0
a-bit data
Asynchronous
Internal
Output*
0
1
1
8-bit data
Asynchronous
External
Input
1
0
0
8-bit data
Clocked Synchronous
Internal
Output
1
0
1
9-bit data
Asynchronous
Internal
Not Used**
1
1
0
9-bit data
Asynchronous
Internal
Output*
1
1
1
9-bit data
Asynchronous
External
Input
Port 2, Bit 3
I
Port 2, Bit 4
When R E is "1", bit 3 is used for
a serial input.
When TE is "1", bit 4 is used for
a serial output.
• Clock output regardless of RE or TE in the TRCSR .
•• Not used for the SCI.
Bit 6
Bit 7
TOa Transmit Data Bit a
When selecting the 9-bit data format in the
asynchronous mode, this bit is transmitted as the 9th
data.
ROa Receive Data Bit a
When selecting the 9-bit data format in the
asynchronous mode, this bit stores the 9th bit data.
• TIMER, SCI STATUS FLAG
Table 12 shows set and clear conditions of each status flag in
the timer 1, the timer 2 and the SCI.
If the flag set and clear conditions occur at the same time, the
flag of the Timer 1 and the Timer 2 will be set, and the SCI
cleared. Therefore the OCFl and OCF2 of the Timer 1 may not
be cleared correctly because set signal is generated periodically
whenever the OCR matches the FRC. In order to clear these
flags correctly, the match should be prohibited during the period
between reading the TSCR and writing the OCR. For instance,
these flags will be cleared correctly if the TCSR is read and the
OCR is written continuously soon after matching the value of the
OCR and the FCR .
Table 12 Timer 1, Timer 2 and SCI Status Flag
Set Condition
Timer
1
Timer
2
Reset Condition
ICF
FRC -+ ICR by edge input to P20 •
OCF1
OCR1=FRC
OCF2
OCR2=FRC
2.
Read the TCSR2 then write to the OCR2H or
OCR2L, when OCF2=1
RES=O
TOF
FRC=$FFFF+1 cycle
1.
2.
Read the TCSR1 then FRCH, when TOF=1
m=O
CMF
T2CNT=TCON R
1.
2.
Write "0" to CM F, when CM F = 1
RES =0
RDRF
Receive Shift Register -+ RDR
OR FE
1.
1.
2.
1.
2.
Read the TRCSR then RDR, when RDRF= 1
R'ES=O
Read the TRCSR then RDR, when ORFE=l
RES=O
1.
Read the TCSR 1 or TCSR2 then ICRH,
when ICF=1
2.
"FfES=0
1.
Read the TCSR 1 or TCSR2 then write to the
OCR1H orOCR1L,when OCF1=1
"FfES=0
2.
2.
SCI
TDRE
1.
2.
3.
1.
Framing Error (Asynchronous Mode)
Stop Bit = 0
Overrun Error (Asynchronous Mode)
Receive Shift Register -+ RDR when
RDRF=1
Asynchronous Mode
TDR -+ Transmit Shift Register
Clocked Synchronous Mode
Transmit Shift Register is "empty"
RE'S=O
Read the TRCSR then write to the TDR,
when TORE=l
(Note) Clear TD RE after setting TE.
(Note) 1. -+ ; transfer
2. For example; "leAH" means High byte of ICA.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
931
HD63701XO,HD637A01XO,HD637B01XO--------------------•
eration.
LOW POWER DISSIPATION MODE
The HD63701XO provides two low power dissipation modes;
sleep and standby.
•
•
Standby Mode
In MCU mode, the HD63701XO stops and reset with STBY
"low". In this mode, the power dissipation is reduced conspicuously. All pins except for the power supply, STIJY and
XT AL are detached from the MCU internally and will be the
high impedance state.
While the contents of RAM is retained. The MCU returns
from this mode by reset. The followings are typical usage of this
mode.
Save the CPU information and SP contents on RAM by NMT.
Then disable the RAME bit of the RAM control register and set
the STBY PWR bit to go to the standby mode. If the STBY
PWR bit is still set at reset, that indicates the power is supplied
to the MCU and RAM contents are retained properly. So system
can restore itself by returning their pre-standby informations to
the SP and the CPU. Fig. 26 depicts the timing at each pin with
this example.
Sleep Mode
The MCU will be in the sleep mode when SLP instruction is
executed. In the sleep mode, the CPU stops and the registers'
contents are retained. While the peripherals such as timers, SCI
etc. continue their functions. The power dissipation of the sleepcondition is one fifth that of the operating condition.
The MCU returns from this mode by an interrupt, RES or
ST'BY; it will be reset by ~ and the standby mode by smY.
When the CPU responds to an interrupt request, it cancels the
sleep mode, returns to the operation mode and branches to the
interrupt routine. When the CPU masks this interrupt, it cancels
the sleep mode and executes the next instruction. However, for
example if the timer 1 or 2 prohibits a timer interrupt, the CPU
doesn't cancel the sleep mode because of no interrupt request.
This sleep mode is effective to reduce the power dissipation
for a system with no need of the HD63701XO's consecutive op-
(r---I
Vee
CDNMII
CD
NMI
HD63701XO
@ RES
IIIIII
STBY
I
H
I
I
I
I
I
, SP - 1 .... SP
PSHB
37
4
1
B - MS!>, SP - 1 .... SP
PULA
32
3
1
SP + 1 - SP, Msp .... A
PULB
33
3
1
SP + 1 - SP, Msp .... B
49
1
:} L.[J4l1 I I I I I
59
,
1
46
1
1
Rotate Left
ROL
6
2
79
6
ROLB
ROR
66
6
2
76
I
I
I
l
l
I
l
l
I
I
l
6
A+M- A
B+M- B
1
3
RORA
RORB
56
1
1
(Notel Condition Code Register will be explained in Note of Table 17.
8
C
1>7
:}
t;Q;f
I
B
C 1>7
··
· ·· , , ,
·· ,
·· ·· , ··
·· ·· , ··
·· ··
··· ··• ,
·· ·· ,
·· ·· ,,
·· ·· ,
·· ·· ,
··· ··· ,, ,,
·· ·· ··
··· ···
·· ·· ··
·· ·· · ·: · ·
··· ··· · · · ···
·· ·· ·· ·· ·· ··
·· ·· · ·, · ·,
··· ··· ,, ,
·· ··
R
l
l
R
R
R
R 5
R R
R 5
R R
R
5 R R
l
I
l
I
l
I
I
l
I
I
I
I
I
I
I
R
S
I
I
R
S
R
S
(j)~
I (i)~
I (1)<2>
I
, @
I
@ •
I
I
I
I
I
I
I R
I R
I @ •
I @.
I @ •
l R
I R
I
R
II])
7 1 A.B-A:B
3
ROLA
Rotate Right
M + 1 - B, M- A
3D
69
I
I
l
@ •
LDAA
Pull Data
I
I
I
I
l
I
l
l
I
l
3
I @ •
LDAB
Load
Accumulator
C
I
I
4
I
Converts binary add of BCD
characters into BCD format
DECA
INC
Increment
6
2
6
oo-M .... M
NEG
6
70
M'~
I Negatel
60
0
V
l
l
I
00 .... M
Complement,2's
E .clusive 0 R
934
A:B+M:M+' .... A:B
BIT B
COM
,
I N Z
5
#
BITA
CLR
2
H
Registe,
EXTEND
INDEX
Booleanl
Arithmetic Operation
1141
be
IIIIII
IJ
be
I
I
I
I
I
I
I @
I
I
R
R
@ ,
I
l
@/'
I
@ I
@l'
@ ,
(continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63701XO,HD637A01XO,HD637B01XO
Table 14 Accumulator, Memory Manipulation Instructions
Condition Cod.
Aegister
Addressing Modes
Operations
Mnemonic
IMMED
OP
Shift Left
Arithmetic
Doubla Shift
Laft. Arithmetic
Shift Aight
Arithmetic
-
DIAECT
#
OP
-
#
ASL
EXTEND
INDEX
OP
-
#
OP
-
#
68
6
2
78
6
3
Double Shift
Aight Logical
Store
Accumulator
Store Doubl.
Accumulator
Subtreet
OP
-
#
M}
_
~ 1111111 ~O
C .,
bO
ASLA
48
1
1
ASLB
58
1
1
05
1 1 ~
ASLD
ASA
67
6
2
77
6
47
ASAA
57
LSA
64
6
2
74
6
A
8
ACC AI ACC 8
A7
3
ASAB
Shift Aillht
Logical
Booleanl
Arithmetic Operation
IMPLIED
1 1
1
1
AO 87
~,11Iii
:}
8.
'
M}
3
LSAA
44
1
LSRB
54
1 1
1
LSAD
04
1 1
o~
bO
ACC AI ACC 8
A1
AO
3
2
A7
4
2
B7
4
3
A-M
STAB
07
3
2
E7
4
2
F7
4
3
B-M
STD
00 4
2
EO 5
2
FD 5
3
A_M
B .... M+ 1
SUBA
80
2
2 90
3
2
AO
4
2
BO
4
3
A-M _A
SUBB
CO
2
2
00
3
2
EO
4
2
FO
4
3
B - M .... B
83
3 3 93
4
2 A3
5
2
B3
5 3
87
A: B-M ; M+ 1 .... A; B
Double Subtract
SUBD
Subtreet
Accumulators
SBA
Subtract
With CIIrry
SBCA
82
2
2
92
3
2
A2
4
2
B2
4
3
A-M-C .... A
SBCB
C2
2
2
02
3
2
E2
4
2
F2
4
3
B-M-C .... B
10
Transfar
Accumulators
TAB
16
TBA
17
Test Zero or
Minus
TST
2
70
4
1 1
A - B .... A
1 1 A .... B
1 1 B .... A
M -00
3
TSTA
40
1 1 A -00
TSTB
50
1
And Immediate
AIM
71
6
3
61
7
OR Immediate
OIM
72
6
3 62
EOR Immediate
ElM
75
6
3 65
Test Immediate
TIM
7B
4
3 6B
1 B - 00
M·IMM-M
7
3
3
7
3
MEBIMM-M
5
3
M·IMM
(Note) Condition Code Register will be explained in Note of Table 17.
f-+{]
90
M+IMM-M
3
H
N Z
I
·· ··
·· ·
··· ·
·· ··
··
·· ··
·· ··
·· ··
··· ···
·· ··
·· ··
··• ··•
(l
2
1 0
V
C
t t ®t
t t ~t
t t §.It
a
t t @t
a
t t
t t
t t
a
C
bO
Ao+llllllll~
8.'
97
4
1 f.cJ
_
STAA
60
1+-0
80
5 4
••
••
•
6
6
6
t
t
t
:§ t
t@t
R t
R
R I
6
t
A
l~l
I
I
I
I
A
I
I
R
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
A
I
R
I
I
I
R A
t
t
t
t
t
t
t
t
A
··
·
I
I
I
··
R
A
R
A
R
•
•
•
R
R
· ·
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
R
935
HD63701XO,HD637A01XO,HD637B01XO-----------------------------------------•
TIM. . . . . . . . .. (M)' (IMM)
Additional Instruction
In addition to the HD6801 instruction set, the HD63701XO
prepares the following new instructions.
AIM .......... (M)·(IMM)
--+
Executes "AND" operation to immediate data and
changes the relative flag of the condition code register.
(M)
These area 3-byte instructions; the first byte is op code, the
second immediate data and the third address modifier.
Executes "AND" operation to immediate data and the
memory contents and stores its result in the memory.
OIM . . . . . . . . .. (M)
+
XGDX ........ (ACCD) ...... (IX)
(IMM)
--+
(M)
Exchanges the contents of accumulator and the Index register.
Executes "OR" operation to immediate data and the
memory contents and stores its result in the memory.
ElM. . . . . . . . .. (M) Etl (IMM)
--+
SLP
Goes to the sleep mode. Refer to "LOW POWER DISSIP ATION MODE" for more details of the sleep mode.
(M)
Executes "EOR" operation to immediate data and the
memory contents and stores its result in the memory.
Table 15 Index Register, Stack Manipulation Instructions
Addr, ..in; Modll
Point... Operltioni
Mnemonic
Complre Inde. Reg
Decrement Inde. Reg
CPX
Decrement Stick Pntr
Increment Inde. Reg
DES
INX
Increment Stick Pntr
INS
IMMED.
DIRECT
OP
OP
8C 3 3 9C 4 2
-"
-"
-" -" - "
,
,
DEX
Load Inde. Reg
LOX
CE
3
3
DE 4
2
LOid Stack Pntr
Store Index Reg
LOS
STX
8E
3
3 9E
OF
4
2
4
2
Store Stick Pntr
STS
l'XS
9F
4
2
Index Reg - Stack Pntr
Boolllnl
Arithmetic Operltion
INDEX
EXTEND IMPLIED
OP
OP
OP
AC 5 2 BC 5 3
X-M:M+l
09 1 1 X- 1 - X
34
1 SP- 1 - SP
1 X + 1- X
08
31 1 1 SP+1-SP
5
AE 5
EF 5
AF 5
EE
2
FE
5
3
M-X H.(M+1)-X L
2
5
5
3
3
M- SP H . (M+ll-SP L
2
BE
FF
2
8F
5
3
XH - M. XL - (M + 1)
,
SP H - M. SP L - (M+ 1)
30
3A
,
,
3C
5 1 XL - M..,. SP - 1 - SP
PULX
38
4
XH - Mil>' SP - 1 - SP
1 SP + 1 - SP, Mil> - XH
SP+ 1- SP,M..,- XL
XGDX
18
2
1 ACCD· ·IX
Stick Pntr - Index Reg
Add
Push Dlta
TSX
Pull Dltl
Exchange
35
ABX
PSHX
1
X-I - SP
1 SP + 1- X
1 B + X- X
Condition Cod,
Reglat,r
!'i 4 3 2 1 0
H I N Z V C
·· ·· · ··
·· ·· ·· · ·· ··
·· ·· ·· · ··
··· ··· ···
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
· · ····
: t : t
t
t
(t· t
::u t
T t
'7 t
R
R
R
R
••••••
(Note) Condition Code Register will be explained in Note of Table 17,
936
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63701XO,HD637A01XO,HD637B01XO
Table 16 Jump, Branch Instruction
Condition Code
Register
Addressing Modes
()perations
Mnemonic
RELATIVE
OP
Branch Alwavs
Branch Never
BRA
BRN
-
#
DIRECT
OP
-
#
INDEX
OP
-
#
EXTEND
IMPLIED
OP
OP
-
#
-
Branch Test
#
None
20
BCC
24
3
2
C=O
BCS
25
3
2
C=1
2
BEQ
27
3
Branch If .. Zero
BGE
2C
3
N
> Zero
BGT
2E
3
Z + IN
Branch If Higher
BHI
22
3
2
Branch If " Zero
BlE
2F
3
2
Z + IN
Branch II lower Or
Same
BlS
23
3
2
C+Z =1
< Zero
<±l
<±l
BlT
20
3
2
N
2B
3
2
N = 1
Branch If Not Equal
Zero
BNE
26
3
2
Z=O
Branch If Overflow
Clear
BVC
28
3
2
V-O
Branch If Overflow Set
BVS
29
3
Branch If Plus
BPl
2A
3
Branch To Subroutine
BSR
80
5
1
0
V
C
V =0
<±l
VI = 0
<±l
VI = 1
V =1
V = 1
···· ·.
N=O
2
6E
3
3
5 2 AD 5 2 BD 6
3
JMP
Jump To Subroutine
JSR
No Operation
NOP
Return From Interrupt
RTI
3B 10 1
Retum From
Subroutine
RTS
39
5
Sohwere Interrupt
SWI
3F
12 1
Wait for Interrupt-
WAI
SLP
3E
9
lA
4
90
3
2
7E
Jump
Sleep
2
N Z
C+Z=O
BMI
Branch If
Branch If Minus
3
I
Z =1
Branch If = Zero
Branch If
4
H
·····.
None
21
Branch If CarrV Clear
Branch If Carry Set
5
01
1 1
Advances Prog. Cntr.
Onlv
1
,
1
--(!
--
·•· • ·• ··• • •
S
~g;
•
(Note) • WAI puts R/W high; Address Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of Table 17.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
937
HD63701XO,HD637A01XO,HD637B01XO--------------------Table 17 Condition Code Register Manipulation Instructions
jAddressingModes
Operations
Mnemonic
IMPLIED
-
OP
Clear Carry
ClC
CLI
ClV
Clear Interrupt Mask
Clear Overflow
Set eerry
Set Interrupt Mask
Set Overflow
Accumulator A- CCR
CCR -+ Accumulator A
SEC
SEI
SEV
TAP
TPA
1
1
1
OA
00
OF
OB
1
1
1
1
,
1
06
1
1
1
1
1
07
O-+C
0-1
O-+V
1
1- C
1-+1
I-V
A- CCR
CCR - A
LEGEND
CONDITION CODE SYMBOLS
OP
Operation Code (Hexadecimal)
Number of MCU Cycles
Msp Contents of memory location pointed to by Stack Pointer
#
Number of Program Bytes
Arithmetic P.lus
Arithmetic Minus
•
Boolean AND
+ Boolean Inclusive OR
e Boolean Exclusive OR
iiii Complement of M
Transfer into
OBit = Zero
00 Byte = Zero
(Note)
··· ·· ··· ··· ·· ··
··· ·· ··· ··· ·· ··
······
#
1
OC
OE
Condition Code Register
4
5
J
1
2
0
H
N
Z
I
V
C
R
R
R
S
S
S
--@---
Boolean Operation
H
I
N
Z
V
C
R
S
Half-carry from bit 3 to bit 4
Interrupt mask
Negative (sign bit)
Zero (byte)
Overflow, 2's complement
Carry/Borrow from/to bit 7
Reset Always
Set Always
Set if true after test or clear
Not Affected
t
•
Condition Code Register Notes: (Bit set if test is true and cleared otherwise)
CD
(Bit V)
Test: Result = 10000000?
(])
(Bit C)
Test: Result ~ OOOOOOOO?
@
@)
(Bit C)
Test: BCD Character of high-order byte greater than 10?
(Bit V)
Test: Operand = 10000000 prior to execution?
®
®
(Bit V)
Test: Operand = 01111111 prior to execution?
(Bit V)
Test: Set equal to NEll C = 1 after the execution of instructions
(i)
(Bit N)
Test: Result less than zero? (Bit 15=1)
(Not cleared if previously sed
®
(All Bid
Load Condition Code Register from Stack.
(9)
@)
(Bit I)
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exist the wait state.
(All Bit)
Set according to the contents of Accumulator A.
®
(Bit C)
Result of Multiplication Bit 7=1? (ACCB)
Table 18 OP-Code Map
OP
ACC
ACC
CODE
A
B
0100
0101
0110
4
5
6
~
LO
0000
0
0001
0000
0
~
1
SBA
0001
1
NOP
CBA
0010
0101
~ ~
3 ~ ~
4 LSRO ~
5 ASLD ~
0110
6
0011
0100
2
01ft
7
TAP
TPA
1000
8
INX
TAB
0010
0011
2
BRA
3
TSX
BRN
INS
BHI
PULA
BLS
PULB
BCC
DES
BCS
TXS
fo
IMM
0111
1000
8
7
ACCB or X
ACCA or SP
OIR
I
I
I
OIR liND
I
I
1001
9
1010
A
1 EXT
I
l
1011
1100
B
C
NEG
I
1 1110 I
I E I
IMMl OIR liND
I
J
ftOI
o
EXT
1111
F
SUB
0
AIM
CMP
1
OIM
SBC
2
3
COM
AOOO
SUBO
LSR
AND
~
ElM
4
BIT
5
LOA
6
PSHA
ROR
TBA
BNE
BEQ
PSHB
ASR
XGDX BVC
PUlX
ASL
L.-::::::::l
EOR
RTS
ABX
ROL
ADC.
9
DEC
ORA
A
1001
9
DEX
DAA
1010
A
CLV
SLP
BVS
BPL
1011
B
SEV
ABA
BMI
RT!
1100
C
CLC
BGE
PSHX
1101
1110
0
BLT
E
SEC
ClI
~
~
MUL
WAI
1111
F
SEI
0
---
INO
~ BGT
~ BLE
1
UNDEFINED OP CODE
2
----
TIM
5
STA
ADD
TST
BSR
I
B
~J
JSR
JMP
LOS
~
6
7
8
CPX
ClR
4
STA
INC
~~
SWI
3
~·I
7
8
I
~
STS
9
I
A
1
B
C
I
LDO
C
STD
LOX
E
0
STX
o
I
E
F
I
F
~
• Only each instructions of AIM, OIM. ElM. TIM
938
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435·8300
----------------------HD63701XO,HD637A01XO,HD637B01XO
• CPU OPERATION
•
CPU Instruction Flow
When operating, the CPU fetches an instruction from a
memory and executes the required functions. This sequence
starts after the reset release and repeats itself limitlessly if not affected by a special instruction or a control signal. SWI, RTI, WAI
and SLP instructions are to change this operation, while NMI,
tR:Q"1, mQz, IRQ3' HALT and STBY are to control it. Fig. 28
gives the CPU mode shift and Fig. 29 the CPU system flowchart. Table 19 shows the CPU operating states and port states.
•
Operation at Each Instruction Cycle
Table 20 provides the oj?eration at each instruction cycle. By
the pipeline control of the HD63701XO, MULT, PUL, DAA and
XGDX instructions etc. prefetch the next instruction. So attention is necessary to the counting of the instruction cycles because
it is different from the existent one - - - - - op code fetch to the
next instruction op code.
Table 19 CPU Operation State and Port State
Port
Mode
Reset
Port 1
(A. -A,)
Mode 1,2
H
Mode 3
T
Mode 1,2
Port 2
Mode 3
Port 3
(D. -0,)
Port 4
(A. -A,,)
Port 5
Port 6
Port 7
Mode 1,2
Mode 3
T
T
Mode 1,2
H
Mode 3
T
Mode 1,2
Mode 3
Mode 1,2
Mode 3
Mode 1,2
Mode 3
T
STBY****
T
T
T
T
T
T
T
*
T
T
H; High, L; Low, T; High Impedance
* RD, WR, RtW, LlR=H, BA=L
RD, WR, R/W=T, LlR, BA=H
HALT is unacceptable in mode 3.
E pin goes to high impedance state.
HAL T***
---------T
Keep
T
----T
T
Keep
--**
Sleep
H
Keep
Figure 28 CPU Operation Mode Transition
Keep
T
Keep
H
Keep
T
Keep
*
Keep
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
939
-0
::I:
~
o
0)
W
--.J
o
X
P
::I:
o
0)
w
I
~
......
:=:
~
»
o
~
P
~
3
X
o·
III
(Note)
!:
a.
•
1. The program sequence will come to the RES start from
any place of the flow during RES. When STBY=O. the
sequence will go into the standby mode regardless of the CPU
condition.
2. Refer to "FUNCTIONAL PIN DESCRIPTION" for more
details of interrupts.
I\:)
~
o
o
oi
~~
~:I
.CD
-
~
• :J>
000
~
:I
C-
o
C/)
~
(")
»
<0
~
~
IN
•
~
0
$
~
W
(J'1
~
W
0
0
Figure 29 HD63701XO System Flow Chart
::I:
C
0)
W
--.J
tl:J
o
~
X
o
---------------------HD63701XO,HD637A01XO,HD637B01XO
Table 20 Cycle-by-Cycle Operation
Address Mode &
Address Bus
Instructions
Data Bus
IMMEDIATE
ADC
AND
CMP
LOA
SBC
ADDD
LOD
LOX
DIRECT
ADC
AND
CMP
LOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
CPX
LOS
SUBD
ADD
BIT
EOR
ORA
SUB
3
3
3
ADDD
LDD
LOX
CPX
LOS
SUBD
STD
STX
STS
4
4
JSR
5
TIM
4
AIM
OIM
1
2
Op Code Address + 1
Op Code Address + 2
1
1
0
0
1
1
1
0
Operand Data
Next Op Code
1
2
3
Op Code Address + 1
Op Code Address ~ 2
Op Code Address i 3
1
1
1
0
0
0
1
1
1
1
1
0
Ope>rand Data (MSB)
Operand Data (LSB)
Next Op Code
1
2
3
Op Code Address + 1
Address of O~JP.rand
Op Code Address + 2
1
1
1
0
0
0
1
1
1
1
1
0
Address of Operand (LSB)
Operand Data
Next Op Code
1
2
3
1
2
3
4
1
2
3
4
1
2
3
4
5
1
2
3
4
1
2
3
4
Op Code Address '- 1
Destination Address
Op Code Address '- 2
Op Code Address i- 1
Address of Operand
Address of Operand ~ 1
Op Code Address~ 2
Op Code Address+ 1
Destination Address
Destination Address + 1
Op Code Address + 2
Op Code Address + 1
FFFF
Stack Pointer
Stack POinter - 1
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Address of Operand
FFFF
Address of Operand
Op Code Address + 3
1
0
1
1
1
1
1
0
1
0
0
0
0
0
0
2
ElM
6
5
6
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
0
Destination Address
Accumulator Data
Next Op Code
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
(Continued)
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
941
HD63701XO,HD637A01XO,HD637B01XO------------------------------------------Address Mode &
Instructions
Address Bus
INDEXED
JMP
3
ADC
AND
CMP
LOA
SBC
TST
STA
ADD
BIT
EOR
ORA
SUB
4
4
1
2
3
1
2
3
4
1
2
3
4
ADDD
CPX
LOS
SUBD
LDD
LOX
5
1
2
3
4
5
STD
STX
STS
5
1
2
3
4
5
JSR
5
1
2
3
4
5
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
1
2
3
4
5
6
TIM
5
1
2
3
4
5
CLR
5
1
2
3
4
5
AIM
OIM
ElM
1
2
3
7
4
5
6
7
Data Bus
Op Code Address+ 1
FFFF
Jump Address
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address t 2
1
1
1
1
1
1
1
0
Op Code Address + 1
FFFF
IX + Offset
Op Code Address+2
Op Code Address + 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address + 2
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address + 2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
IX +Offset
Op Code Address + 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+ 1
Op Code Address+ 1
Op Code Address + 2
FFFF
IX + Offset
Op Code Address + 3
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset
Op Code Address + 2
Op Code Address + 1
Op Code Address + 2
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+3
1
1
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
l
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
0
1
0
1
0
Offset
Restart Address (LSB)
First Op Code of Jump Routine
Offset
Restart· Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
RegIster Data (MSB)
RegIster Data ILSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data
00
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
(Continued)
942
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-S300
---------------------HD63701XO,HD637A01XO,HD637B01XO
Address Mode &
Instructions
Address Bus
Data Bus
EXTEND
JMP
3
ADC
AND
CMP
LOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
TST
4
1
2
3
1
2
3
4
4
1
2
3
4
ADDD
CPX
LOS
SUBD
LDD
LOX
5
1
2
3
4
5
STD
STX
STS
5
1
2
3
4
5
JSR
6
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
CLR
5
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
Op Code Address+ 1
Op Code Address + 2
Jump Address
Op Code Address+ 1
Op Code Address + 2
Address of Operand
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Destination Address
Op Code Address + 3
Op Code Address+ 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Destination Address
Destination Address + 1
Op Code Address+3
Op Code Address + 1
Op Code Address + 2
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
FFFF
Address of Operand
Op Code Address + 3
Op Code Address+ 1
Op Code Address + 2
Address of Operand
Address of Operand
Op Code Addtess+3
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
0
Jump Address (MSB)
Jump Address (LSB)
Next Op Code
Address of Operand (MSB)
~ddress of Operand (LSB)
Operand Data
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Accumulator Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (MSB)
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
00
Next Op Code
(Continued)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
943
HD63701XO,HD637A01XO,HD637B01XO-----------------------------------------Address Mode &
Instructions
Address Bus
Data Bus
IMPLIED
ABA
ASl
ASR
CLC
ClR
COM
DES
INC
INX
lSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
ABX
ASLD
CBA
CLI
ClV
DEC
DEX
INS
LSR
ROl
NOP
SEC
SEV
TAP
TPA
TSX
PULA
PUlB
PSHA
PSHB
XGDX
1
Op Code Address+ 1
1
0
1
0
Next Op Code
1
2
1
2
Op Code Address + 1
FFFF
Op Code Address + 1
FFFF
Stack Pointer + 1
Op Code Address + 1
FFFF
Stack Pointer
Op Code Address+ 1
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Op Code Address + 1
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Return Address
Op Code Address + 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
Next Op Code
Restart Address (lSB)
Next Op Code
Restart Address (lSB)
Data from Stack
Next Op Code
Restart Address (lSB)
Accumulator Data
Next Op Code
Next Op Code
Restart Address (lSB)
Data from Stack (MSB)
Data from Stack (LSB)
Next Op Code
Restart Address (LSB)
Index Register (LSB)
Index Register (MSB)
Next Op Code
Next Op Code
Restart Address (lSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Restart Address (LSB)
Restart Address (lSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
1
2
3
3
4
PUlX
4
PSHX
1
2
3
4
1
2
3
4
1
2
5
RTS
3
4
5
1
2
5
MUL
3
4
5
1
2
7
3
4
5
6
7
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
0
0
1
0
0
0
1
1
1
0
0
1
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
1
1
1
(Continued)
944
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63701XO,HD637A01XO,HD637B01XO
Address Mode &
Instructions
Data Bus
Address Bus
IMPLIED
WAI
9
1
2
3
4
5
6
7
B
9
RTI
10
1
2
3
4
5
6
7
8
9
SWI
12
10
1
2
3
4
5
6
7
B
9
10
11
12
1
2
SLP
Op Code Address+ 1
FFFF
Stack Pointer
Star.k Pointer- 1
Stack Pointer - 2
Stack Pointer-3
Stack POinter - 4
Stack Pointer - 5
Stack Pointer - 6
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Stack POinter + 3
Stack Pointer+4
Stack Pointer + 5
Stack Pointer + 6
Stack Pointer + 7
Return Address
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address+ 1
FFFF
1
4
SI~ep
1
3
4
FFFF
Op Code Address+ 1
1
2
Op Code Address + 1
FFFF
Branch Address - --Test =" 1..
Op Code Address +1-Test="0--
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
I I I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (LSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (LSB)
First Op Code of SWI Routine
Next Op Code
Restart Address (LSB)
I
1
1
1
0
1
1
1
0
Restart Address (LSB)
Next Op Code
1
1
0
1
1
1
1
1
1
0
1
0
Branch Offset
Restart Address (LSB)
First Op Code of Branch Routine
Next Op Code
1
1
0
1
1
0
0
1
1
1
1
1
0
RELATIVE
BCC
BEQ
BGT
BLE
BLT
BNE
BRA
BVC
eSR
BCS
BGE
BHI
BLS
BMT
BPL
BRN
BVS
3
3
1
2
5
3
4
5
j
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Branch Address
0
0
1
• APPLICATION NOTES
1
1
1
0
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Op Code of Subroutine
The memory cell will be discharged by;
to ultraviolet light; discharged by photo emitting electrons (erasure principle)
~ Heat; discharged by thermal emitting electrons
(j) Applied with high voltage; discharged by high electric
field. Charge loss from the normal cell by case ~ or (j)
is negligible. But if there are some defects at the Si02 , the
cell will be rapidly discharged through the defects. Such a
defective part is rejected by manufacturing screenings.
The erased, or discharged, cell is a "I".
CD Exposure
• The EPROM Programming and Maintenance
(1) The EPROM Programming and Data Retention
An EPROM memory cell is programmed by hot electrons
injected to the floating gate with applying high voltage at the
control gate and the drain. The electrons have been trapped
by the potential barrier at the polysilicon-oxide (Si02 ) by
which the floating gate is completely sorrounded. The programmed cell becomes a "0".
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
945
HD63701XO,HD637A01XO,HD637B01XO--------------------Si0
2
\1
~co.ntrol gate
• /
Floating gate
see~-~-::::-:eee::::-:Qy=::-r
Source \
~
Vpp overshoot of an EPROM programmer should 1
checked .
Negative-noise to device pins may cause a parasitic tra]
sistor effect and reduce the breakdown voltage.
1
N+
l
J
/Drain
N+
(3) Precaution for using the MCU in the ceramic package with
window
Static charge on the window surface may adversely affe
the function of the MCU. The charge will be caused by rul
bing the window with plastics or dry cloths, or touching
charged body on it. They can be discharged by exposure 1
ultraviolet light for a short time. It is recommended to pre
gram the memory cell again after exposure, since the ele
trons trapped at the floating gate will reduce. The metho(
to prevent static charge on the window are follows.
connect the body of an operator to the ground.
2 Do not rub the window with plastics or dry cloths.
Do not use coolant sprays which contain some ions.
4 Use a conductive opaque label.
The data stored in EPROM may be losed or the MCI
may malfunction by photocurrent if the MCU is exposed t
strong light like a fluorescent lamp or the sunlight. Then
fore, it is recommended to cover tl\e window with an opaqu
label.
\
The programmed cell ("0")
~
The erased cell ("1")
Figure 30 Cross-section of An EPROM Memory Cell
(2) Precaution of the EPROM Programming
The EPROM memory cell should be programmed with
the specified voltage and timing. The higher program voltage
Vpp or the longer program pulse width tpw is applied, ~he
more will be the quantity of electrons injected to the floating
gate. However, a p-n junction will be broken permanently if
Vpp is applied to more than maximum ratings. Especially
(4) Screening procedure of the MCU in the plastic package
In general, any standard manufacturing screening (
semiconductor devices will make initial failures rejected an
improve reliability. The bake procedure for EPROM devic~
accelerates any electron leakage at the floating gate. Th
manufacturer tests the CPU, RAM, I/O and other logi
functions in the EPROM on-chip MCU in the plastic pad
age at wafer sort and final test, and rejects any devices whic
do not pass the tests. It is impossible, however, to reject EF
ROM defects at final test, since the EPROM memory pOI
tion cannot be completely tested after molding in the plasti
package. Therefore, it is recommended that the screenin
procedure shown Fig. 31 after programming EPROM pOI
tion.
Failure
Baking (Vee and Vpp not applied)
150o C± 10°C, 48 hrs!.& hrs'
Ae-verify at Vce = 4.5V and 5.5V
* Baking time should be
measured after oven
temperature reaching at 150°C.
Figure 31
Recommended Screening Procedure of the MCU in The Plastic Package
(Caution) If the user experiences several consecutive programming failures, from same EPROM programmer, after
following the recommended screening procedure, then
call Hitachi.
'
946
(5) EPROM programmers and socket adapters
EPROM programmers and socket adapters which are rec
om mended for the HD63701XO are shown Table 21.
A socket adapter is a tool to convert from 64-pin socke
to standard 24-pin socket.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------HD63701XO,HD637A01XO,HD637B01XO
Table 21
EPROM Programmers and Socket Adapters for the HD63701XO
EPROM Programmer
Maker
Socket Adapter
Type No.
121A/1218
29A/298
DATA I/O (U.S.A.)
Maker
Type No.
Hitachi Ltd.
H67PWA01A
Data I/O
HD63701XO
(for 29A/298)
AVAL CORP. (JAPAN)
PKW-1000
PKW-7000
Hitachi Ltd.
H67PWA01A
Minato Electronics Inc.
(JAPAN)
M1863
M1866
7GU-2700
Hitachi Ltd.
H67PWA018
When a write-only register such as the DDR of the port is
read by the MPU, "$FF" always appears on the data bus. Note
that when an instruction which reads the memory contents and
does some arithmetic operation on the contents of the write-only
register, it always gets $FF as the arithmetic and logical results.
AIM, OIM and ElM instructions are unable to apply especially
for the bit manipulation of the DDR of the I/O port.
After performing BSR instruction, the branch destination address is output on an address bus to fetch the first op-code of a
subroutine. If $0001 is output as an address by some mistake the
HD63701XO decodes it inside and generates a trap interrupL
When RTf instruction is performed in this trap interrupt servicing routine, the HD63701XO will set $0001 in PC and start
from this address, which causes a trap interrupt again and repeat
this endless-loop_
•
•
•
Write only Register
Trap Interrupt
When execution an RTf instruction at the end of the interrupt
routine, trap interrupt different from other interrupts returns to
the address where the trap interrupt was generated. Attention is
necessary when using several trap interrupts in the program. See
Fig_ 32 and 33 for details.
FF01
OPn
FF02
Operand
FF03
Undefinition
FF04
OPn+1
Precaution for using W AI instruction
If HAI:T turns "Low" in WAI execution, a CPU upset may
occur since the correct vector will not be fetched after the halt
state has been released. It is recommended to use BRA instruction etc. for software interrupt before HAIT turns "Low" shown
Fig. 35.
1
WAI
lr
Waiting
Interrupt
Accept interrupt
Uncorrect vector (MSB)
Fetch vectors
Uncorrect vector (LSB)
C
Execute interrupt routine
A CPU upset
Figure 32 Fetching an Undefined Op-code
Figure 34 A CPU Upset after HALT Input in WAI Execution
After executing OPn instruction, the HD63701XO fetches and
decodes and undefined op-code inside to generate a trap interrupt. When RTI instruction is executed in this trap interrupt
servicing routine, the HD63701XO will set $FF03 in PC, fetch
the undefined code again, generate a trap interrupt and repeat
ABC endless-loop.
CLI
Loop 1-_ _ _B_R_A_ _ _---1
FF02
BSR
FF03
01
FF04
OPn
Loop
Waiting interrupt
Figure 35 A Recommended Example
Figure 33 Fetching Erroneously
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
947
HD63701XO,HD637A01XO,HD637B01XO--------------------•
* Just after power-on, the MPU doesn't enter reset state until
Power-on Reset
At power-on it is necessary to hold RES "low" to reset the
internal state of the device and to provide sufficient time for the
oscillator to stabilize. Pay attention to the following.
the oscillation starts. This is because the reset signal is input
internally, with the clocked synchronization as shown below.
Internal reset signal
RESpin
Inside the LSI
Figure 36 Reset Circuit
•
Thus, just after power-on the LSI state (IIO port, mode condition etc.) is unstable until the oscillation starts. If it is necessary
to inform the LSI state to the external devices during this period,
it needs to be done by the external circuits.
Board Design of Oscillation Circuits
Keep the following in mind when connecting a crystal resonator to XTAL and EXTAL pins of the HD6~701XO.
641------
HD63701XO
(1)
A crystal resonator and
load capacitors should be
as close as possible to the
LSI.
(2)
Keep the lines from XT AL
and E pins as far as possible.
(Avoid parallel wiring.)
0
External noise to XTAL and)
EXTAL pins will disturb the
( normal oscillation.
(
Avoid these lines.
Signal C
E signal will go into the
XTAL pin to disturb the
normal oscillation.
~
aJ
~
~
t: :
----'---....,.------1- - - - - -
HD630701XO
Signal lines or power supply lines near the oscillation circuit will
disturb normal oscillation by their induction (see the right figurel.
So pay attention not to do that. In addition. keep the resistance
between XTAL and its nearest pin, and between EXTAL and its
nearest pin more than 10MU.
Figure 37 Precaution on Board Design of Oscillation Circuits
948
@>HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - H 063701 XO,H0637 A01 XO,H 0637801 XO
HD63701XO
(Top view)
Figure 38 Example of Oscillation Circuits in Board Design
• Receive Margin of the SCI
Table 22
Receive margin of the SCI contained in the HD63701XO
is shown in Table 22.
Note: SCI = Serial Communication Interface.
START
2
3
4
Bit distortion tolerance
(t-to) I to
Character distortion tolerance
(T-To) ITo
±43.7%
±4.37%
5
6
8
STOP
Ideal Waveform
I
Bit length /--t o --]
....> - - - - - - - - - - C h a r a c t e r length To --------~~
Real Waveform
1 + - - -_ _
T_~t~
_ _
___+j.1
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
949
HD63705VO,HD637 A05VO,-HD637B05VO
CMOS MCU (Microcomputer Unit)
-ADVANCE INFORMATIONThe HD63705VO is an 8-bit CMOS single chip microcomputer
unit (MeU) which, including 4k bytes of EPROM, is object code
compatible with the HD6305VO.
The HD63705VO contains 4k bytes of EPROM, 192 bytes of
RAM, serial communication interface and 31 parallel I/O pins in
addition to CPU.
The HD63705VO is available in a hermetically sealed 40-pin
ceramic pa~kage which includes a glass window that allows for
programming and EPROM erasure in the same way as 27256
type EPROM.
HD63705VOC,HD637A05VOC,
HD637B05VOC
, • FEATURES
•
•
•
•
•
•
•
•
•
•
•
Instruction Set compatible with the HD6305VO
4k Bytes of EPROM (compatible with 27256 type)
192 Bytes of RAM
A total of 31 terminals
Twotimers
8-bit timer with a 7 -bit prescaler (programmable prescaler; event counter)
- 15-bit timer (commonly used with the SCI clock divider)
On-chip serial interface circuit (synchronized with clock)
Six interrupts (two external, two timer, one serial and one
software)
Low power dissipation modes - Wait, Stop and Standby
Mode
Operation Mode
MCU Mode (Single-chip Mode)
EPROM Mode
Minimum Instruction Cycle Time
HD63705VO ....... 1 P.s (f= 1MHz)
HD637 A05VO ...... 0.67 P.s (f= 1 .5MHz)
HD637B05VO ...... 0.5 P.s (f= 2MHz)
Wide Operating Range
HD63705VO ....... f=0.1 to 1MHz..(Vcc=5V± 10%)
HD637A05VO ...... f=0.1 to 1.5MHz (VCC=5V± 10%)
HD637B05VO ...... f=0.1 to 2MHz (Vcc=5V±10%)
(DC-40)
• PIN ARRANGEMENT
• SOFrwAREFEATURES
•
•
•
•
•
•
•
•
•
•
Similar to HD6800 Instruction Set
Byte Efficient Instruction Set
Bit Manipulation
Bit Test and Branch
Versatile Interrupt Handling
Powerful Indexed Addressing for Tables
Fu II Set of Conditional Branches
10 Powerful Addressing Modes
New Instructions - STOP, WAIT, DAA
Compatible with HD6805 Family
950
(Top View)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
---------------------HD63705VO,HD637A05VO,HD637B05VO
•
BLOCK DIAGRAM
MCU Mode
i
,
~
EPROMM7
VppfTlME R
7
l
EOolAo
EO,/A,
EO,lA.
EOy'A.
EO.tA,
EO .... A.
EO.tA.
EO ,lA,
B.
~I p
8
CD.! is~~
5.!1 caa:.2'
D-~
a:
-
Qi
r----;;IIJ
J~![
a:
8
Hdu"
I
uS
5 ·i
D-a:
6
~
OJ
o.g
c:
caa:
~,§
Index
Register
,
~
Miscellaneous
Register
r
'--- lRTl
~
CPU
Stack
POinter
SP
Program
Counter
"I:!igh" PCH
Program
Counter
"low" PCl
AlU
~
j
I
II
4096X8
EPROM
~~
CPU
Control
X
Condition Code
Register
CC
5
6
EA./B,
EAoIC o
EA,IC,
EA,IC.
EAy'C.
EA.tC,
EA ....C.
EAe/C.
EA,/C,
li
A
8
~,§
-
0.,"0t~
fBY
EA.
Accumulat~
D- ~ sa:
a:
B.
B.
JI
rW
Timer Control
-<.
5.!1
Bo
B,
EAII/B,
EA,oIB.
Prescaler
dr
T ' lAC R~ NUM
l
,
Timerl
8 Counter
11
I
I
192x8
RAM
Oe/lRT.
o"CR
~~
f-~
is .~ oS
5·!! ... I*Sa:
0,1
~
0,8
0,1
C5E"
ca
c:
D-l ~ ~
j.
Serial
Control
Register
Serial
Status
Register
...
O.tRx
Oy'Tx
00
Serial
Data
Register
MCUMode
I
EPROMM ode
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
951
INTRODUCTION OF
THE RELATED
DEVICES
•
•
•
•
•
•
•
8116-bit Multi-chip Microcomputer
4-bit Single-chip Microcomputer
IC Memory
LCD Driver Series
Gate Array
CODEC/Filter Combo LSI
Speech Synthesis LSI
8/16-BIT MULTI-CHIP MICROCOMPUTER
•
8·BIT MULTI·CHIP MICROCOMPUTER
LSI Characteristics
Division
Type No.
Process
10Id Type No.
MPU
iii
~
!
J
:.
HD6803
HD6803-1
HD6303R
HD63A03R
HD63B03R
HD6303X
HD63A03X
HD63B03X
HD6303Y
HD63A03Y
HD63B03Y
HD6305X2
HD63A05X2
HD63B05X2
HD6305Y2
HD63A05Y2
HD63B05Y2
HD6800
HD68AOO
HD68BOO
HD6802
HD6802W
HD6809
HD68A09
HD68B09
CMOS
1.0
us-
Supply
Voltage
IV)
Operating
...
Temperature
0-+70
5.0
-0-+70
~ 5.0
2.0
CMOS
~
DP-40
Compatibility
Microprocessor +128 Bytes of RAM
MC6803
MC6803-1
Microprocessor +128 Bytes of RAM
------
01'-40
FP-54
CG-40
0-+70
DP-64S
FP-80
Microprocessor +192 Bytes of RAM
0-+70
DP-64S
Microprocessor +256 Bytes of RAM
5.0
0-+70
DP-64S
FP-64
Microprocessor +12B Bytes of RAM
~
~ 5.0
0-+70
DP-64S
FP-64
Microprocessor +256 Bytes of RAM
5.0
-20 - +75
DP-40
Microprocessor
5.0
5.0
-20 - +75
-20 - +75
DP-40
DP-40
Microprocessor+Clock+256 Bytes of RAM
5.0
-20 - +75
DP-40
High-End 8-Bit Microprocessor
5.0
-20- +75
DP-40
High-End 8-Bit Microprocessor
r¥o-
5.0
-20 - +75
DP-40
High-End 8-Bit Microprocessor
IExternal Clock Type)
~
3.0
5.0
-20 - +75
DP-40
High-End B-Bit Microprocessor
IExternal Clock Type)
~ 5.0
2.0
~
CMOS
Function
Package t
1°C)
~
~ 5.0
2.0
CMOS
CMOS
~
~
2.0
2.0
HD46800D
HD468AOO
HD468BOO
HD46802
NMOS
NMOS
NMOS
NMOS
.J4--~
2.0
1.0
1.0
*-
MC6800
MC68AOO
MC68BOO
Microprocessor+Clock+ 128 Bytes of RAM MC6802
~
HD6309··
CMOS
~
2.5
HD6809E
HD68A09E
HD68B09E
NMOS
.J4---
HD6309E·
CMOS
HD6821
HD68A21
HD68B21
PIA
HD6321·
HD63A21·
HD63B21'
HD6840
HD68A40
HD68B40
PTM
HD6340·
HD63A40'
HD63840'
HD6843
FDC
HD68A43
HD6844
DMAC
HD68A44
HD68B44
HD6845
HD68A45
HD68B45
CRTC
HD6845S
HD68A45S
HD68B45S
COMBO HD6846
HD6850
HD6SA50
ACIA
HD6350
HD63A50
HD63B50
HDB852
SSDA
HDB8A52
HD4850S
HD485OB·1
ADU
HD4850SA
HD4650SA-l
ATC
NMOS
Clock
Frequency
IMHz)
HD46821
HD468A21
HD468B21
r-!Jl.-r-LL-2.0
5.0
-20- +75
DP-40
Peripheral I nterface Adapter
CMOS
.J4-r-LL-2.0
5.0
-20 - +75
DP-40
FP-54
Peripheral I nterface Adapter
5.0
-20 - +75
DP-28
Programmable Timer Module
5.0
-20- +75
DP-28
Programmable Timer Module
CMOS
HD46852
HD468A52
HDI46818
r1J!--
NMOS
NMOS
HD46503S
HD46503S-1
HD46504
HD46504-1
HD46504-2
HD46505R
HD46505R-l
HD46505A·2
HD46505S
HD46505S-1
HD46505S-2
HD46846
HD46850
HD468A50
~
~
J..42.0
r-!Jl.--
~
2.0
NMOS
~
1.5
5.0
0-+75
DP-40
Floppy Disk Controller
NMOS
r-14-------J..42.0
5.0
-20 - +75
DP-40
Direct Memory Access Controller
5.0
-20 - +75
DP-40
5.0
-20- +75
DP-40
5.0
-20 - +75
DP-40
NMOS
~
NMOS
r-14--------
NMOS
~
2.0
~
2.0
1.0
CRT Controller
13.0MHz High-speed Display)
CMOS
~
~
2.0
5.0
-20- +75
DP-24
Asynchronous Communications
Interface Adapter
NMOS
~
1.5
5.0
-20 - +75
DP-24
Synchronous Serial Data Adapter
5.0
-20- +75
DP-40
Analog Data Acquisition Unit
5.0
0-+70
DP-24
FP-24
Aeal Time Clock Plus RAM
~
1.0
MC6B44
MC68A44
MC68B44
MC6845
MC68A45
MC68B45
MC6846
MC6850
MC68A50
DP-24
.J4--1.5
MC6843
-----
-20 - +75
CMOS
MC6840
MC68A40
MC68B40
(3.7MHz High-speed Display)
5.0
~
MC6821
MC68A21
MC68B21
Combination ROM I/O Timer
Asynchronous Communications
Interface Adapter
~
NMOS
MC6809E
MC68A09E
MC68B09E
CRT Controller
NMOS
1.5
MC6809
MC68A09
MC68B09
----MC6852
MC68A52
----
f--------- ----
MC146H1H
• Preliminarv •• Under development ••• Wide Temperature Aange (-40 - +S5°C) version is available.
t DP; Plestic DIP, FP; Plastic Flat Package, CG: Glass-sealed Ceramic Leadless Chip Carrier
~HITACHI
Hitachi America Ltd_
•
2210 O'Toole Ave.
•
San Jose, CA 95131
955
•
(408) 435-8300
8i16-BIT MULTI-CHIP MICROCOMPUTER
•
16-BIT MULTI-CHIP MICROCOMPUTER
LSI Characteristics
Division
MPU
DMAC
iii
Type No.
Process
Clock
Frequency
(MHz)
HD68000-6
6
HD68000-8
8
HD68000-10
10
HD68000-12
HD68000Y6
12.5
6
HD68000Y8
NMOS
8
HD68000Y10
10
HD68000Y12
12.5
HD68000P6
6
HD68000P8
8
HD68000PS6
6
HD68000PS8
8
HD68450-4
4
HD68450-6
6
HD68450-8
8
HD68450-10
10
HD68450Y4
NMOS
4
HD68450Y6
6
HD68450Y8
8
.t:
HD68450Y10
10
CI>
HD63463-4**
4
...J
0;
4;
.g-
0..
HDC
ACRTC
HD63463-6*·
CMOS
6
H D63463-8 * *
8
HD63484-4*
4
HD63484-6*
6
CMOS
HD63484-8*
* Preliminary
956
** Under developmerit
Supply
Voltage
(V)
Operating
Temperature
(oC)
t
Package
Function
MC68000L6
MC68000L8
DC-64
MC68000L10
MC68000L 12
MC68000R6
5.0
0- +70
PGA-68
Microprocessor
MC68000R8
MC68000R10
MC68000R12
MC68000G6
DP-64
. MC68000G8
-
DP-64S
-
MC68450L4
MC68450L6
DC-64
5.0
MC68450L8
Direct Memory
0-+70
Access Controller
MC68450L10
-
PGA-68
-
5.0
0-+70
DC-48
Hard Disk Controller
-
5.0
0-+70
DC-64
Advanced CRT Controller
8
t
Compatibility
-
DP; Plastic DIP, DC; Ceramic DIP, PGA; Pin Grid Array
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
4-BIT SINGLE-CHIP MICROCOMPUTER
•
PMOS 4-BIT SINGLE-CHIP MICROCOMPUTER HMCS40 SERIES
Family Name
(Type Name)
r; Supply Voltage
0=
Power Dissipation (typ.)
-10
-10
-10
100
100
150
150
250
-50
-50
-50
-50
-50
-20 to+75
-20 to +75
-20 to +75
-20 to +75
-20 to +75
DP-28, DP-28S
DP-42, DP-42S
DP-42, DP-42S
FP-54, DP-64S
FP-54,DP-64S
1,024 x 10
64 x 10·'
2,048 x 10
128 X 10·'
2,048 x 10
128 X 10·'
4,096 x 10
.s:.
-10
ROM
(bits)
512 x 10
32x 10·'
RAM
(bits)
32 x 4
80 x 4
160x4
160x4
256 x 4
4
6
8
6
6
Registers
Stack Registers
2
4
3
4
4
4-Bit Data Input.
4x1
4x1
-
-
4-Bit Data Output
4x2
4x2
-
4)(1
Discrete Output
22
1x6
32
1 x 12
32
44
-
~
4-Bit Data Input/Output
°flc:
-
4x1
4x4
4)(6
Discrete Input/Output
1x4
1x4
1 x 16
1)( 16
0
:s
"-
HMCS47A
(HD38870)
Wg33a?1~'
-10
u Package
I/O Ports
HMCS45A
~~~=,
(V)
(V)
Operating Temperature Range ., (oC)
Memory
HMCS44A
Wg3~815SS'
(mW)
Ui "i Max. I/O Terminal Voltage
~~
..H~~_~_3_
HMCS42
(HD38702)
4x1
44
4x6
1 x 16
2
Timer/Counter
-
1
1
1
1
Number of Instructions
(I's)
Cycle Time
51
10
71
10
71
10
71
10
71
10
Power on Reset
Yes
Yes
Yes
Yes
Yes
Battery Back-up
-
RAM Hold
RAM Hold
RAM Hold
RAM Hold
HD38750E
HD44850E
HD44857E
HD38750E
HD44850E
HD44857E
HD44850E
HD44857E
HD44850E
HD44857E
HD44857E
Interrupts
Instructions
External
2
Built-in Clock Pulse Generator
Evaluation Chip
2
2
Yes
·1 Wide Temperature Range (-40to+85°C) version is available.
·2 Pattem Memory
~HITACHI
\ Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
957
4-BIT SINGLE-CHIP MICROCOMPUTER - - - - - - - - - - - - - - - - - - - - - • CMOS 4-BIT SINGLE-CHIP MICROCOMPUTER HMCS40 SERIES
Family Name
(Type Name)
HMCS42CL
(HD44708)
HMCS42C
(HD44700)
HMCS43CL
(HD44758)
HMCS43C
(HD44750)
HMCS44CL
(HD44808)
HMCS44C
(HD44801)
rl Supply Voltage
(V)
3/5
3/5
3/5
:~
Power Dissipation (typ.)
(mW)
0.23/1.5
0.24/1.5
0.32/2
Max. I/O Terminal Voltage
(V)
Vcc+0.3
Vcc+0.3
Vcc+0.3
(oC)
-20to+75
-20 to+75
-20 to+75
DP·28, DP·28S
DP·42, DP-42S
DP-42,DP·42S
ROM
(bits)
512 x 10
32 x 10.2
1,024 x 10
64x10· 2
2,048 x 10
128x10·2
RAM
(bits)
32x 4
80 x4
160 x 4
4
6
8
~t
..JIV
~ Operating Temperature Range·'
() Package
Memory
Registers
Stack Registers
3
2
4
c:
'"
4·8it Data Input
4x1
4x1
1:> I/O Ports
c:
4-Bit Data Output
4x2
4x2
.2
Discrete Output
::l
LL.
Instructions
1 x 12
32
-
4x 1
Discrete Input/Output
1x4
1x4
32
4x4
1 x 16
2
Timer/Counter
-
1
1
Number of Instructions
51
71
71
Cycle Time
20/10
20/10
20/10
External
Interrupts
1x6
22
4-Bit Data Input/Output
-
V-ts)
2
Yes
Built·in Clock Pulse Generator
Power on Reset
No/Yes
No/Yes
No/Yes
Battery Back-up
Halt
RAM Hold
Halt
HD44850E
HD44857E
HD44850E
HD44857E
HD44850E
HD44857E
Evaluation Chip
·1 Wide Temperature Range (-40 to +B5°C) version is available.
·2 Pattern Memory
·3 LCD DRIVE FUNCTION
LCD
Drive
Common
Segment
Duty
4
32
Static, 1/2, 1/3, 1/4
Bias
112, 1/3
Display Capability
4x32 Matrix (1/4 Duty)
Expandable using the LCD Driver HD44100H.
958
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
4-BIT SINGLE-CHIP MICROCOMPUTER
HMCS45CL
(HD44828)
HMCS45C
(HD44820)
HMCS46CL
(HD44848)
HMCS46C
(HD44840)
HMCS47CL
(HD44868)
HMCS47C
(HD44860)
LCD-.DI·
(HD44795,
HD44790)
LCD-IV·
(HD613901)
3/5
3/5
3/5
3/5
3/5
0.32/2
0.32/4
0.32/4
0.36/2.4
0.9/5.0
Vcc+ 0•3
Vcc+0.3
Vcc+0•3
Vcc+ 0.3
-20to+75
-20to+75
-20 to +75
-20to +75
Vcc+ 0.3
-20tO+75
3
3
FP-54, DP-64S
DP-42, DP-42S
FP-54, DP-64S
FP-BO
FP-80
2,048 x 10
128xl0· 2
4,096 x 10
4,096 x 10
2,048 x 10
128 X 10. 2
4,096 x 10
160 X 4
256 x 4
256x 4
160x 4
256 x 4
6
8
6
6
6
4
4
4
4
-
-
4 xl
4xl
4xl
-
4x1
4xl
4 xl
-
44
4
-
-
32
2
-
32
4x2
1 x 16
1 x 16
1 x 16
2
2
-
32
4x2
4x6
1x 16
1 x 16
2
-
44
4x4
4x6
2
1
1
1
1
1
71
71
71
71
71
20/10
20/5
20/5
20/10
20/5
Yes
No/Yes
No/Yes
No/Yes
Yes
No
Halt
Halt
Halt
Halt
Halt
HD44850E
HD44857E
HD44857E
HD44857E
HD44797E
HD44797E
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
959
4-BIT SINGLE-CHIP MICROCOMPUTER - - - - - - - - - - - - - - - - - - - - - • CMOS 4·BIT SINGLE·CHIP MICROCOMPUTER HMCS400 SERIES
Family Name (Type Name)
(V)
(max,) (mW)
:; Power Dissipation
Ci)~ Max. I/O Terminal Voltage
.J1:;
~ Operating Temperature Range
18
9
4 to 6
12
(V)
VCC-40
VCC-40
VCC-40
VCC-40
-20 to +75
-20 to +75
-20 to +75
-20 to +75
FP-64, DP-64S
FP-64, DP-64S
FP-64, DP-64S
DP-42
ROM
(bits)
4096 x 10
4096 x 10
4096 x 10
2048 x 10
RAM
(bits)
160 x 4
256 x 4
256 x 4
256 x 4
7
7
7
7
Stack Registers
16
16
16
16
4-Bit Input
4x 1
2x 1
4 x 1
2x 1
4x 1
2x 1
4-Bit Output
4x4
4x4
4x4
!0
I/O Ports
Interrupts
Instructions
58
58
58
1 x1
36
4 x 1
4-Bit Input/Output
4x5
4x5
4x5
4x4
1-Bit Input/Output
1 x 16
1 x 16
1 x 16
1 x 15
External
2
2
2
Timer/Counter
2
2
2
1
Serial Interface
1
1
1
-
99
99
99
98
2
1.33
4
2
Number of Instructions
Cycle Time
U£s)
Built-in Clock Pulse Generator
2
Yes (External drive is possible)
Others
Low Power Dissipation Mode (Stop mode, Stand-by mode)
Family Name (Type Name)
(V)
Ui~
.J.., Max. I/O Terminal Voltage
~ Operating Temperature Range
(V)
("C)
6 Package
Memory
4.5 to 5.5
4.5 to 5.5
(max.) (mW)
:; Power Dissipation
HD614P1SO**t
HD614POSOSt
rl Supply Voltage
..
27
Registers
"fi
c
:::J
u.
Wt89~Jfio*)*
2.7 to 6.0
("C)
6 Package
Memory
rHMD'ii~1.~r
4.5 to 6.0
~rt8ma:Jr
(HD614042)
4to 6
rl Supply Voltage
27
27
VCC-40
-20 to +75
VCC- 4O
-20 to +75
DC-64SP
ROM
(bits)
RAM
(bits)
DC-42
o4,096-word x 10-bit
with standard
EPROM 2764
° 4,096-word x 10-bit
with standard
EPROM 2764
o8,192-word x 10-bit
with standard
EPROM 27128
°8,192-word x 10-bit
with standard
EPROM 27128
576 x 4
576x4
Registers
7
7
Stack Registers
16
16
c
.2
4-Bit Input
c
:::J
u.
4-Bit Output
1:;
I/O Ports
4-Bit Input/Output
1-8it Input/Output
Interrupts
Instructions
58
4x1
2x 1
1x 1
4x4
4 x 1
4x5
1 x 16
36
4x4
1 x 15
External
2
Timer/Counter
2
1
Serial Interface
1
-
Number of Instructions
Cycle Time
Built-in Clock Pul. Generator
U£s)
2
99
98
1.33
2
Yes (External drive is possible)
Low Power Dissipation Mode
(Stop mode, Stand-by mode)
Others
*
Preliminary
* * Under development
t EPROM on the P8Ckage Type
960
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
Ie MEMORY
HM6116A/L Series
120 - 200ns
HM611 7/L Series
150 - 200ns
HM6167H/L Series
45 - 55ns
HM6267 Series
35 - 45ns
HM6264A/L Series
120 - 200n5
HM66202/L Series
150 - 200ns
HM4864A Series
120 - 200ns
HM50465 Series
120 - 200ns
HM~025 7
120 -
Series
200ns
HM51 258 Series
100 - 150ns
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
961
Ie MEMORY---------------------------------------------------------------HN61364
250ns
HN61365
250ns
HN61366
250ns
HN613128
250ns
HN61256
3.5 J.Ls
HN613256
250ns
HN62201
3.5 J.Ls
HN62101
3.5 J.Ls
HN62301/A
350ns/250ns
HN482732A Series
200 - 300ns
HN482764
200 - 300ns
HN27C64 Series
150 - 300ns
HN4827128 Series
250 - 450ns
HN27256 Series
250 - 300ns
HN27C256 Series
200 - 300ns
HN482764P-3
300ns
HN4827128P-30
300ns
HN58064P Series
250 - 300ns
962
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------IC
MEMORY
• BIPOLAR RAM
HM10414-1
8ns
HM10422-7
7ns
HM2112 Series
8 - 10ns
HM2142
10ns
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
963
[LCD
•
DRIVER SERIES
LCD DRIVER SERIES CHARACTERISTICS
Use
Item
"
General
Segment Display
Type Number
HD44100H
HD61100A
HD61200
HD61602
HD61603
Process
CMOS
CMOS
CMOS
CMOS
CMOS
(V)
5*1
5*1
5*1
3 - 5*1
3 - 5*1
(oC)
-20 - +75*'
-20 - +75
-20 - +75
-20 - +75
-20 - +75
FP-60
FP·l00
Fp·l00
FP-SO
FP·SO
(mW)
5.0
5.0
5.0
0.5 (5V)
0.5 (5V)
ROM
(bits)
-
-
-
-
-
RAM
(bits)
-
-
-
51 x 4
64 xl
Interface (CPU)
S
8
8
14
10
Interface (Driver I C)
2
2
2
-
-
Interface
(External ROM, RAM)
-
-
-
-
-
-
-
-
4
4
40
SO
80
Free (N)
.~
.~
ti Supply Voltage
~u
Ui
...J
Operating Temperature
Package
Power Dissipation
Memory
c
e
j
1/0
Number of Instruction
Common
LCD Driver
Segment
Duty
U
Ui
...J
Static, 1/2,
1/3,1/4
Static
Free (N)
N x SO
Matrix
(liN Duty)
SR type
SR type
Type Number
HD44102CH
HD44103CH
HD4410SH
HD61102
HD61202
Process
CMOS
CMOS
CMOS
CMOS
CMOS
5*'
N x 80
Matrix
(l/N Duty)
204
Segment
(1/4 Duty)
64 Segment
SR type
Use
Item
j
64
Free (N)
Comment
"
1
51
N x 40
Matrix
(liN Duty)
Display Capability
"=
"i
4
Graphic Display
Supply Voltage
(V)
5*1
5*1
5*'
5*1
Operating Temperature
(oC)
-20 - +75
-20 - +75
-20 - +75
-20 - +75
-20 - +75
FP·SO
FP-60
FP-60
Fp·l00
Fp·l00
2.5
Package
(mW)
2.5
4.0
4.0
3.0
ROM
(bits)
-
-
-
-
-
RAM
(bits)
200 xS
-
-
512 x S
512 x 8
21
Power Dissipation
Memory
c
1/0
0
j
Interface (CPU)
21
6
6
21
Interface (Driver IC)
-
5
5
-
-
Interface
(External ROM, RAM)
-
-
-
-
-
6
-
-
Common
-
20
32
7
-
Segment
50
-
-
64
64
Duty
liS, 1/12, 1/16,
1/24,1/32
1/S,l/12,l/16,
1/24,1/32
1/64
1/64
32 x 50
Dots
(1/32 Duty)
-
64 x 64
Dots
(1/64 duty)
64 x 64
Dot.
(1/64 duty)
Number of Instruction
LCD Driver
Display Capability
1/S,l/12,l/16,l/24,
1/32, 1/4S, 1/64
Suitable common
Comment
*1:
*2:
*3:
964
driver is HD44105H
or HD44103CH
-
Suitable common
driver is H 0611 03A
7
Suitable common
driver is HD61203
Except Power Supply for LCD.
-40 - +8SoC (Special Request). Please contact Hitachi Agents.
CG; Character Generator.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - L C D DRIVER SERIES
Character Display
HD44780
(LCD-II)
HD43160AH
CMOS
CMOS
5*'
5*'
-20 - +75*'
-20 - +75
FP-80
FP-54
1.75
10.0
7200
(CG)*'
6240
(CG)*'
80 x 8/64
x 8(CG)*'
80 x 8
11
21
4
5
-
18
11
6
16
-
40
1/8,1/11,
1/16
16 Digits
(5 x7 Dots
1/16 Duty)
1/8,1/12,
1/16
-
Expandable
to 80 Digits
using
HD44100H
Display to
80 Digits
using
HD44100H
HD61103A
HD61203
HD61830
HD61830B
CMOS
CMOS
CMOS
CMOS
5*'
5"
5*'
5"
-20 - +75
-20 - +75
-20 - +75
-20 - +75
FP-l00
Fp·100
FP~O
Fp·60
5.0
5.0
30.0
30.0
7360
(CG)*'
7360
ICG)"
(external
65536 x 8)
(external
65536 x
13
13
Graphic Display
6
9
64
64
1/48,1/64
1/96,1/128
1/48, 1164,
1/96,1/128
33
33
12
12
1/1 - 1/128
Static
1/1 -1/128
Display to
524288
Dots using
HD44100H or HD61100A.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
965
I GATE ARRAY
CMOS Gate Array HD61J/HD61K/HD61L/HD61MM Series
•
•
FEATURES
Fast operation
Internal gate (2-input NAND, FO=3, Al=3mm) .. 3.5ns typ
Input buffer (FO=3, Al = 3mm) . . . . . . . . . . . . . 9ns typ
Output buffer (CL =50pF). . . . . . . . . . . . . . . .. 20ns typ
Memory access time (HD61MM) ............... 60ns typ
low power dissipation
At 10MHz operation (Internal gate) ...... 130J..LW/gate typ
Abundant input and output configuration
Allocation of all pins except power supply pins to input/
output/input-output
Output can be CMOS/open drain/3-state
•
•
•
•
•
•
•
•
Memory on-chip (HD61MM)
Flexibility of memory capacity and word organization
Selection of single port/dual port memory
Wide operation temperature range
-20 to +75°C
Wide package selection
Especially plastic packages with high pin
count . . . . . . . . . . DllP64/FPP100
Powerful design support
User-Defined-Macro
Test pattern evaluation with fault simulator
Design support at local Design Center
Quick turn around time and reasonable development cost
LINE UP
HD61J
504
50
Gate count
I/O pin count
RAM on chip
Package
HD61K
1080
68
HD61l
1584
68
HD61MM
2496
104
available
-
-
-
DP28
0
0
DP40
DP42
DP64
FP54
FP80
FP100
DC28
DC40
PGA72
PGA120
*
*
0
-
0
0
0
0
0
0
0
-
-
-
0
0
0
0
-
-
-
0
0
0
0
*
*
*
-
0
-
-
Power supply pin
4
*
-
0
-
-
*
4
8*
·Under development
Bi-CMOS Gate Array HD27K/HD27l/HD27P/HD27Q Series
•
•
•
FEATURES
High speed with super low power dissipation
• Internal gate: 4.0ns (Fan out=3)
@0.05mW
• Input buffer: 5_0ns (Fan out=3)
@2_6mW
• Output buffer: 8.0ns (CL =15pF)
@2.6mW
lS TTL compatible input/output _ ...... _ ..... _ .... .
• Selectable totem-pole/3-state/open collector output
• IOL =8mA: Capable of driving 20 lS TTL's
•
•
•
•
•
966
Output buffer can construct logic functions_
• Saves gate stages.
A variety of macrocell library
• Internal gate: 44
• Output buffer: 9
A variety of reliable package
• Plastic DIP 16 to 64 pins
• Plastic FP 60 to 100 pins (under development)
A variety of DA 'system support
• Only logic diagrams and test patterns needed as an interface
with the user.
Short development time
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave_ • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------GATE ARRAY
Number of gates
Number
of Vee
and GND
pins
Package
Internal gate
(2-input NAND)
Input
buffer
Output
buffer
HD27K
200
18
18
2
16,20,28,
40 pins
HD27L
528
30
30
4
28,42,64
pins
60 pins
60,80,100
pins
60,80,100
pins
DIP
(Plastic)
HD27P
966
40
40
4
28,42,64
pins
HD27Q
1530
50
50
4
28,42,64
pins
FP*
(Plastic)
-
·Under development
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
967
CODEC/F I LTER COMBO LSI
CLOCK
SERIES
44230
44230C
44240C
TYPE
COMPo
LAW
HD44231B
A
HD44232B
/J.
HD44233B
A
HD44234B
/J.
HD44235
A
HD44236
/J.
HD44237
A
HD44238
/J.
POWER
(Typ.)
60mW
INTERNAL
CLOCK
SYNCIASYNC
OPERATION
OUTPUT AMP
PCMBIT
CLOCK RATE
DEVIDER
SYNC.
15361
INCLUDED
ONLY
15441
ADJUST-
2048kHz
SYNC.
64-
-
INCLUDED
ONLY
2048kHz
0
A
DEVIDER
SYNC.
15361
INCLUDED
ONLY
15441
A
A
PLL
SYNC.
64-
-
INCLUDED
ONLY
2048kHz
0
A
HD44247C
A
HD44248C
/J.
600 n
UNCOMMOP-AMP
BOTH
/J.
/J.
1.2 kn
ITED
2048kHz
60mW
HD44236C
HD44238C
ENDED
FULLY
-
HD44235C
HD44237C
RESIST
-
/J.
/J.
3kn
ABLE
0
BOTH
HD44232C
HD44233C
MIN
LOAD
SINGLE
2
PLL
HD44231C
HD44234C
TYPE
USING
BOTH
50mW
INPUT
AMP
DECODER
SHIFT
-
0
BOTH
PLL
80mW
INCLUDED
BOTH
64-
-
2048kHz
0
SAME AS
ABOVE
PUSHPULL
SPEECH SYNTHESIS LSI
Type
,
CMOS 1-chip System
Device
H 1;)6188517 (Speech Synthesizer)
HD44881 (128k-bit Expanding ROM)
System
PARCOR
Voice channel model
10 steps digital filter
Sampling frequency
10 kHz
Bit rate (b/s)
1250 ~ 9900
Frame period (ms)
10/20
Variable speaking speed
Speaking time
968
-25%, 0, +25%
10
~
20 sec (internal ROM)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408) 435-8300
600n
HITACHI AMERICA, LTD.
SEMICONDUCTOR AND IC DIVISION
HEADQUARTERS
Hitachi, Ltd.
New Marunouchi Bldg., 5-1,
Marunouchi 1-chome
Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 212-1111
Telex: J22395, J22432, J24491,
J26375 (HITACHY)
Cable: HITACHY TOKYO
REGIONAL OFFICES
MID-ATLANTIC REGION
U.S. SALES OFFICE
Hitachi America, Ltd.
Semiconductor and IC Division
2210 O'Toole Avenue
San Jose, CA 95131
Tel: 408-435-8300
Telex: 17-1581
Twx: 910-338-2103
Fax: 408-435-2748
Fax: 408-435-2749
Fax: 408-435-2782
DISTRICT OFFICES
•
Hitachi America, Ltd.
3800 W. 80th Street, Suite 1050
Bloomington, MN 55431
612/896-3444
•
Hitachi America, Ltd.
80 Washington St., Suite 302
Poughkeepsie, NY 12601
914/485-3400
•
Hitachi America, Ltd.
6 Parklane Blvd., #558
Dearborn, MI 48126
313/271-4410
•
Hitachi America, Ltd.
6161 Savoy Dr., Suite 850
Houston, TX 77036
713/974-0534
•
Hitachi (Canadian) Ltd.
2625 Queensview Dr.
Ottawa, Ontario, Canada K2A 3Y4
613/596-2777
•
Hitachi America, Ltd.
401 Harrison Oaks Blvd., Suite #317
Cary, NC 27513
919/481-3908
Hitachi America, Ltd.
1700 Galloping Hill Rd.
Kenilworth, NJ 07033
201/245-6400
NORTHEAST REGION
Hitachi America, Ltd.
5 Burlington Woods Drive
Burlington, MA 01803
617/229-2150
SOUTH CENTRAL REGION
Hitachi America, Ltd.
Two Lincoln Centre, Suite 865
5420 LBJ Freeway
Dallas, TX 75240
214/991-4510
NORTH CENTRAL REGION
Hitachi America, Ltd.
500 Park Blvd., Suite 415
Itasca, IL 60143
312/773-4864
NORTHWEST REGION
Hitachi America, Ltd.
2210 O'Toole Avenue
San Jose, CA 95131
408/435-2200
SOUTHWEST REGION
Hitachi America, Ltd.
18300 Von Karman Avenue, Suite 730
Irvine, CA 92715
714/553-8500
SOUTHEAST REGION
Hitachi America, Ltd.
4901 N.W. 17th Way, Suite 302
Fort Lauderdale, FL 33309
305/491-6154
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:10:20 18:09:58-08:00 Modify Date : 2013:10:20 22:19:18-07:00 Metadata Date : 2013:10:20 22:19:18-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:78ca78ec-ab26-854e-9eb8-beee98699e85 Instance ID : uuid:86d12f98-1809-c844-b8fe-02e1a1e2b298 Page Layout : SinglePage Page Mode : UseNone Page Count : 971EXIF Metadata provided by EXIF.tools