1988_VTI_ASIC 1988 VTI ASIC

User Manual: 1988_VTI_ASIC

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VLSI TECHNOLOGY, INC.

APPLICATION
SPECIFIC LOGIC
PRODUCTS
DATA BOOK

1988

Application Specific
Logic Products Division

$10.00

VLSI TECHNOLOGY, INC.

APPLICATION
SPECIFIC LOGIC
PRODUCTS
DATA BOOK

1988

Application Specific
Logic Products Division

The Information contained in this document has been carefully checked and is believed to be reliable; however, VLSI shall not be responsible for any loss or damage
of whatever nature resulting from the use of, or reliance upon, the information contained in this document. VLSI makes no guarantee or warranty conceming the
accuracy of such information, and this document does not in any way extend VLSrs warranty on any product beyond that set forth in VLSl's standard terms and
conditions of sale. VLSI does not guarantee that the use of any information contained herein will not infringe upon the patent or other rights of third parties, and no
patent or other license is implied hereby. VLSI reserves the right to make changes in the products without notification which would render the information contained in
this document obsolete or inaccurate. Please contact VLSI for the latest information conceming these products.
e 1988 VLSI Technology, Inc. Printed in U.SA.

VLSI TECHNOLOGY, INC
CONTENTS
PAGE
NUMBER

INTRODUCTION
Data book ..................................................................•..................
General ..........•............................................................................
Megacell-Based Design Rationale ................................................................. .
Current Family of Megacells ...................................................................... .
Designing a Circuit Using Megacells ................................................................ .
Using VTltest During the Design Phase ............................................................. .
Additional Logic for Test Simplification ...........................................•...................
Using VTltest Software to Help Create Test Programs ................................................. .
Defining the Test Program Flow ................................................................... .
Simulation and Test Program Generation ........................................................... .
Completing the Design .................................................•..............•...........
Summary .................................................................................... .

1
1
1
2
2
2
2
2
4

4
4
5

ORDERING AND PACKAGING INFORMATION
General. ... ....... ................................................................. ...... .....
Package Considerations ............................................. '.' . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual-In-Une Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Small-Outline Integrated Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Carrier. . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip-On-Board Mounting. . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Grid Array...................' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flatpack... ........................................................................ ............
System Considerations ............................................................... . . . . . . . . . . . .
Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18-Pin Ceramic Side-Brazed Dualln-Une Package (DIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18-Pin Plastic Dualln-Une Package (DIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-Pin Ceramic Side-Brazed Dualln-Une Package (DIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-Pin Plastic Dualln-Une Package (DIP). . . . . . . . . . . . . . . . . . . . . . . .. ...................................
24-Pin 0.3" Wide Plastic Dualln-Une Package ("Skinny" DIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24-Pin Plastic Dual In-Une Package (DIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-Pin Ceramic Side-Brazed Dualln-Une Package (DIP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .......
28-Pin Plastic Dualln-Une Package (DIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-Pin Plastic Leaded Chip Carrier (PLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40-Pin Ceramic Side-Brazed Dualln-Une Package (DIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40-Pin Plastic Dualln-Une Package (DIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44-Pin Plastic Leaded Chip Carrier (PLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48-Pin Ceramic Side-Brazed Dual In-Une Package (DIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48-Pin Plastic Dualln-Une Package (DIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64-Pin Ceramic Side-Brazed Dualln-Une Package (DIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64-Pin Plastic Dualln-Une Package (DIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S8-Pin Plastic Leaded Chip Carrier (PLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S8-Pin Leadless Chip Carrier (LCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84-Pin Plastic Leaded Chip Carrier (PLCC) ................... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84-Pin Leadless Chip Carrier (LCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100-Pin Plastic Leaded Flatpack (CJQFP) . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
149-Pin Ceramic Pin Grid Array (PGA) ................................................... . . .. . . . . . . . .

iii

7
8
8
8
8
9
9
9
9
10
10
11
11
11
12
12
13
14
14
15
15
16
16
17
17
18
18
19
19
20
21
22
23
24

VLSI TECHNOLOGY, INC.
CONTENTS
PAGE
NUMBER

HIGH INTEGRATION COMPUTER PRODUCTS
PC/AT-Compatible Devices
VL82C100 CMOS PC/AT-Compatible Peripheral Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL82C101A CMOS PC/AT-Compatible System Controller. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .
VL82C102A CMOS PC/AT-Compatible Memory Controller. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .
VL82C103 CMOS PC/AT-Compatible Address Buffer. . . .. . . . . .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . .
VL82C104 CMOS PC/AT-Compatible Data Buffer. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . .. .

505
506
507
508
509

PS/2-Compatible Devices
VL82C031 CMOS PS/2 Model30-Compatible System Controller ....................... ;. . . . . . . . . . . . . . . .. .
VL82C032 CMOS PS/2 Model 30-Compatible I/O Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL82C033 CMOS PS/2 Model 30-Compatible Floppy Disk Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL82C037 CMOS PS/2-Compatible VGA Video Graphics Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

501
502
503
504

PROCESORSANDCOPROCESORS
VL65NC02 CMOS 8-Bit Microprocessor ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL65C816 CMOS 16-Bit Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL82C389 Message-Passing Coprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . ..
VL86C010IVL86C110NL86C310NL86C410 CMOS 32-Bit Reduced Instruction Set Computer Family. ...........

225
257
533
619

PERIPHERALS
VL 16160 "RASTER OP" GraphicslBoolean Operation ALU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
VL 1772-025 1/4-inch Floppy Disk ControllerlFormatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . .
VL2793 • VL2797 Floppy Disk Formatter/Controller Family •......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL4500A Dynamic RAM Controlle r. . . . . . . . . . . . . . . . . . . . . • • • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL4502 Dynamic RAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL53C80 SCSI Interface (CMOS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . .
VL6522 • VL65C22 • VL65C22V Parallel InterfacelTimer ................................................
VL6765 Double-Density Floppy Disk Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL68C45R1S CMOS CRT Controller. . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL82C37A CMOS Direct Memory Access (DMA) Controller. . .. . . . . .. • . . . . .. . . . . . .. . . . . . . . . . • . .. . . • . . .. . .
VLB2C59A CMOS Programmable Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL82C284 '286 Clock Generator and Driver (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •
VL82C28B '28B Bus Controller (CMOS) ............................................................•
VL82C612 CMOS PC/AT-Compatible Memory Mapper. . . . . . .. . .. . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . . . . . . .
VL83C11 SCSI Buffer (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . .

25
105
153
177
191
205
239
2B1
307
513
547
511
512
563
565

SIGNAL PROCESSING PRODUCTS
VL2010 16 X 16 Parallel Multiplier/Accumulator. .. .. . . . . . .. . . . • . .. . . . . .. . . . . . .. . . . • . .. . . . . .. . • . . . .. . . .

145

DATA COMMUNICATIONS PRODUCTS
VL 16C450 • VL82C50A • VL82C50 CMOS Asynchronous Communications Elements. . . . . . . . . . . . . . . . . . • . . . . . .
VL 16C451 CMOS Asynchronous Communications Element With Parallel Port. . . . . . . . . . . • . . . . . . . . . . . . . . . . . . .
VL 16C452 CMOS Dual Asynchronous Communications Element With Parallel Port. . . . . . . . . . . . . . . . . . . . . . . . . . .
VL 16C550 CMOS Asynchronous Communications Element With FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL 1935 Synchronous Data Line Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . .
VL8530 Serial Communications Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . .
VLB5C30 Enhanced Serial Communications Controller (CMOS) ....................•....... " . . . . . . . . . . . . .

35
59
81
103
127
573
595

TELECOMMUNICATIONS PRODUCTS
VL7C212A CMOS 300/1200 Bit-Per-Second Modem ......•.••........................•.. " . . . • . . . . . . . . .
VL7C213 CMOS Parallel Bus Modem Controler. •. .. . . . .. . . . • . .. . . . . . .. . . . . .. . . . . . .. . . . . . .. . . . . • . . . . . . .
VL7C214 CMOS Stand-Alone Modem Interface Controller.. . . . . . . . . . . . . . . . . . . .. . . . . •. . . . . . . . . . . . . .. . . . ..
VL7C215 CMOS High Speed Parallel Bus Modem Controller............................... ~ . . . . . . . . . . . . ..
VL7C224A 2400 Bit-Per-Second Analog Peripheral. . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . ..
VL7C225 • VL7C235 • VL7C245 CMOS 2400 Bit-Per-Second Modem Advanced Coprocessor Family . . . . . . . . . . . ..
VL7C312 CMOS 300/1200 Bit-Per-Second Modem With Pin Programmable Receiver Gain. . . . . . . . . . . . . . . . . . . . ..
VL7C412 CMOS 300/1200 Bit-Per-Second Modem (Single 5-Volt Power Supply) .............. " . . . . . . . . . .. . ..
VL7C413 CMOS High Speed Parallel Bus Modem Controller (Automatic Modem Power Down Control). . . . . . . . . . . ..
VL7C414 CMOS Stand-Alone Modem Interface Controller (Automatic Modem Power Down Control). . . . . . .. . . . . ..
VLBOC75 T1 Interface (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

321
331
349
359
377
407
439
451
463
481
491

SALES OFFICES, DESIGN CENTERS, AND DISTRIBUTORS. . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

623

VLSI TECHNOLOGY, INC.
CONTENTS

DEVICE
NUMBER

DESCRIPTION

VL16160
VL16C450
VL16C451
VL16C452
VL16C550
VL1772-02
VL1935
VL2010
VL2793
VL2797
VL4500A
VL4502
VL53C80
VL65NC02
VL6522
VL65C22
VL65C22V
VL65C816
VL6765
VL68C45R1S
VL7C212A
VL7C213
VL7C214
VL7C215
VL7C224A
VL7C225
VL7C235
VL7C245
VL7C312
VL7C412
VL7C413
VL7C414
VL80C75
VL82C031
VL82C032
VL82C033
VL82C037
VL82C100
VL82C101A
VL82C102A
VL82C103
VL82C104
VL82C284
VL82C288
VL82C37A
VL82C389
VL82C50
VL82C50A
VL82C59A
VL82C612
VL83C11
VL8530
VL85C30
VL86C010
VL86C110
VL86C310
VL86C410

"RASTER OP" Graphics/Boolean Operation ALU. . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . .
CMOS Asynchronous Communications Elements ........................................
CMOS Asynchronous Communications Element With Parallel Port. . . . . . . . . . . . . . • . . . . . . . . . . . .
CMOS Dual Asynchronous Communications Element With Parallel Port. . . . . . . . . . . . . . . . . . . . . . .
CMOS Asynchronous Communications Element With FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5 1/4-inch Floppy Disk Controller/Formatter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Synchronous Data Line Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
16 X 16 Multiplier/Accumulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Floppy Disk Formatter/Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Floppy Disk Formatter/Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Dynamic RAM Controller. . . . . .. . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Dynamic RAM Controller.............................................................
SCSI Interface (CMOS) ................. " .......•................. " .. . . . . . . . . . . . ..
CMOS 8-Bit Microprocessor. . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . ..
ParaliellnterfacefTimer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ParaliellnterfacefTimer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ParaliellnterfacefTimer. . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS 16-Bit Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Double-Density Floppy Disk Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS CRT Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS 300/1200 Bit-Per-Second Modem. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . ..
CMOS Parallel Bus Modem Controller. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . .. . . . . . . . ..
CMOS Stand-Alone Modem Interface Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS High Speed Parallel Bus Modem Controller .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2400 Bit-Per-Second Analog Peripheral. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS 2400 Bit-Per-Second Modem Advanced Coprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS 2400 Bit-Per-Second Modem Advanced Coprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS 2400 Bit-Per-Second Modem Advanced Coprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS 300/1200 Bit-Per-Second Modem With Pin Programmable Receiver Gain. . . . . . . . . . . . . . ..
CMOS 300/1200 Bit-Per-Second Modem (Single 5 Volt Power Supply). . . . . . . . . . .. . . . . . . . . . . ..
CMOS High Speed Parallel Bus Modem Controller (Automatic Modem Power Down Control). . . . ..
CMOS Stand-Alone Modem Interface Controller (Automatic Modem Power Down Control). . .. . . . ..
T1 Interface (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS PS/2 Model 30-Compatible System Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMOS PS/2 Model 30-Compatible I/O Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS PS/2 Model 30-Compatible Floppy Disk Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS PS/2-Compatible VGA Video Graphics Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS PC/AT-Compatible Peripheral Controller. . . . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . ..
CMOS PC/AT-Compatible System Controller. .. . . .. . . . . . . . . . . . .. .......................
CMOS PC/AT-Compatible Memory Controller ............... , ............ , ...•......... ,
CMOS PC/AT-Compatible Address Buffer .'. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . • . . . . . . . . •.
CMOS PC/AT-Compatible Data Buffer...................... ... .... .......•...........
'286 Clock Generator and Driver (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
'286 Bus Controller (CMOS) ................ , ............ , ...............•.......... ,
CMOS Direct Memory Access (DMA) Controller. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . . .
Message-Passing Coprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMOS Asynchronous Communications Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMOS Asynchronous Communications Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMOS Programmable Interrupt Controller •............................................ ,
CMOS PC/AT-Compatible Memory Mapper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCSI Buffer (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Communications Controller. . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . .. . .. . . . . . .. .
Enhanced Serial Communications Controller (CMOS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMOS RISC MPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . .
CMOS RISC Memory Management Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS RISC Video Controller........ " . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . .
CMOS RISC I/O Controller........................ : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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VLSI TECHNOLOGY, INC.

VLSI TECHNOLOGY, INC.
INTRODUCTION

DATA BOOK

megacells and VLSI's design tools,
manufacturers can have a custom IC
design capability without all of the
normal custom development costs.

sible for the manufacture and marketing
of a diverse logic-based product line
that encompasses both innovative and
proven, well established catalog
devices. This line includes microprocessors and coprocessors, peripheral
circuits, and products for data communications and telecommunications
applications.

This data book presents a complete
technical description of the VLSI
Technology, Inc. Application Specific
Logic Products Division product line.
Where devices have been fully characterized, either by VLSI Technology or by
one of its partners, specific Information
Is presented in the form of data sheets.
Information on partially characterized
devices, devices currently under
development, or devices that have their
own Users Manuals containing data
sheets, is in the form of product briefs.
More complete data can be obtained on
any device from the Logic Products
Division Applications Department.

The VLSI Technology family of megacells represents commonly used
peripherals that are good candidates for
integration as parts of customer-driven
designs, which can be either customerspecific or market-specific. In customer-specific designs, it is possible, for
example, to combine these integration
elements with other megacells and logic
to become single-chip equivalents of
computer systems that are already in
production. This increased level of
integration provides cost and space
reduction that can keep the system
designs competitive. In a marketspecific design, upward-compatible
enhancements that meet the needs of
many customers can be added and the
device offered as a new standard
product.

Unlike other suppliers of such devices,
however, VLSI is also a recognized
leader in ASICs. As such, it not only
possesses the design, process, and
fabrication capabilities necessary to
produce the highest-quality off-the-shelf
components, but is also able to treat its
logic products as an integral part of a
complete solution. One of the primary
vehicles for accomplishing this is the
megacell; the functions represented by
individual devices can be implemented
as megacells in VLSI's software
libraries and used for semi custom
circuit design and functions developed
as megacells for specific applications
can be turned into catalog products.

In order to facilitate computer generL
tion of this data book, overbars (I.e. CS)
have been replaced by a preceding
minus sign (I.e. -CS) on all new or
recently revised data sheets. Older data
sheets will retain their overbars until a
major revision is performed.

GENERAL
The primary business objective of VLSI
Technology, Inc., (VLSI) is to provide
systems designers with total application-specific integrated circuit (ASIC)
solutions. To accomplish this, it has
created a unique blend of expert design
tools, leading-edge process technologies, state-of-the-art fabrication
facilities, and a wide range of products,
including a variety of "catalog" devices.

VLSI's megacells are designed to have
a fixed height and variable widths,
offering the best trade-off between
unusable internal space and placement
ease. As shown in Figure 1, they can
be configured to make a very dense
final design with a minimum of wasted
silicon real estate.

MEGACELLS
The megacell is a relatively new
concept in the world of Ie and system
design. As such ASIC companies as
VLSI offer better tools for IC design,
simulation, and testing, it becomes
necessary for systems manufacturers to
design custom ICs to keep up with their
competition. Megacells help decrease
design time by providing large building
blocks that are equivalents of standard
off-the-shelf products. By using

The Application Specific Logic Products
Division of VLSI Technology is respon-

Of equal importance with the physical
layout format of the cells is the structure
of the interconnect bus. This bus mUst
be generic enough to allow a wide
variety of functions to be connected

FIGURE 1. VLSI TECHNOLOGY MEGACELLS ARE OF A FIXED HEIGHT, WITH VARIABLE WIDTHS

VSS

•

STe
CELLS

MILS
MEGACELL

MEGACELL

IIIII
vee

•

• •
, III .

I•

I I I I I

.. "YLSI BUS DAIAUNES,

II ITII/

I/O INTERCONNECT

VLSI TECHNOLOGY, INC.

uniformly and efficiently, and must be
fast enough to not itself become a
limiting factor as system performance
increases.
The internal structure of the bus created
by VLSI for use with its megacells
contains an m-bit data bus and an n-bit
address bus, both of which are expandable in width to accommodate changes
in system requirements. The bus
operates synchronously at a rate of 3
million transfers a second, which is
equivalent to the performance of a 10
MHz 8086 or 12 MHz 68000 microprocessor. The bus definition allows for
internal access times of 50 ns and cycle
times in the 200 ns range. With standard
pad drivers, external loads can be driven
while supporting a 3 MHz bus frequency;
faster speeds can be obtained by using
faster pad drivers. To create a standard
product from a megacell, an interface
circuit is incorporated that exactly
matches the slower timing of the external
bus to the internal bus.
MEGACELL-BASED DESIGN RATIONALE
There are many reasons why megacells
make sense for new designs, including
reduced board space, lower power,
increased reliability and reduced design
times.
Typical applications that can benefit from
the use of megacells are those that
contain three or four LSI components
and a handful of "glue" components. All
of these components can be combined
into a single component if the functions
can be partitioned into logical groups
with a reasonable number of 110 pins. In
this type of application, the total pin
count might be reduced from 300 pins for
a discrete solution to less than 100 pins,
and the circuit board area reduced from
approximately 20 square inches to 2
square inches.
The power consumption of megacell
designs can be very small in comparison
with the HMOS designs they replace,
since all of the VLSI Technology
megacell family is implemented in high
speed, low power, two-micron CMOS
technology. In addition, because several
functions can be put on one piece of
silicon, the interconnect capacitance and
inductances are minimized, thereby
reducing the power to a fraction of what

INTRODUCTION
was needed in previous designs.
The reliability of a megacell-based
design is typically better than the
collection of discrete components it
replaces because there are fewer pins,
fewer bonding wires and lower total
power consumption. In most systems,
the largest contributor to reliability
problems is IC pin connections, with
such other factors as die temperature
and die size being secondary. The more
functional blocks that can be combined
on a single piece of silicon, the fewer the
number of interconnections that have to
be bonded to package pins, resulting in
higher overall reliability of the component
and system using it.
Since megacells can be used as high
level building blocks, overall design
times can be reduced significantly by
taking existing designs using standard
products and integrating additional
support logic directly onto the chip. An
example of this technique would be the
integration of a VL68C45 CRT controller
with a memory interface and video shift
registers to form a single-chip video
adapter. An additional option might be to
include character ROMs or RAM arrays,
although the addition of these commodity
components is not always cost effective.
CURRENT FAMILY OF MEGACELLS
Megacells are designed by very carefully
studying the data sheets and systems
implementations of the original part
vendors, but an important part of
validating a megacell design is to subject
it to many different hardware and
software environments. Only after a part
has been tested in several applications
can a vendor feel confident that the
megacell exactly emulates the original
function, including all of the undocumented "features". The VLSI Technology philosophy is to offer members of
the megacell family as standard products
as well as cells so that this validation can
take place very quickly after the introduction of the standard product. Since
customer-specific design times typically
take from two to four months, megacell
designs can be started before the
standard product validation has been
done. This lead time allows customers
to get a head start introducing designs.

DESIGNING A CIRCUIT USING
MEGACELLS
The design process is started by using a
megacell schematic "icon" as part of the
schematic entry of the user's design.
Provided with the megacell icon is a data
sheet detailing the internal timing
requirements of the megacell. The
designer works from this data sheet as if
using an off-the-shelf standard product,
except that the logic and timing of the
bus are somewhat easier to use.
USING VTltest DURING THE DESIGN
PHASE
When the schematic entry of the design
is complete, the designer uses a test
language assistance program (VTltest)
to capture a set of simulation vectors that
can be used to test the design after
silicon has arrived. Once the designer is
satisfied that the vector set is sufficient to
cover all possible stuck faults, a final test
program can be compiled through this
program. The output from this program
is a test program containing SETF
statements that can be easily moved
onto an industry-standard tester, such as
a Sentry tester system.
ADDITIONAL LOGIC FOR TEST
SIMPLIFICATION
In all cases, some additional logic will be
necessary to facilitate testing the
megacells. This additional logic consists
of multiplexers on pins to allow all of the
connections of the megacell to be
accessed from the periphery of the
circuit. This dictates that all designs be
contained in packages having at least as
many pins as the most pin-intensive
megacell used internally. To enable the
test mode, an illegal condition on the
interface is often used, such as Read
Strobe and Write Strobe being asserted
together while the chip is selected. This
would normally never occur in an
application, so it is a safe combination to
use. When enabled, the 110 pads of a
specific megacell are connected to the
110 pins of the component, and the
standard product test program run to
verify the functionality of the core.
USING VTltest SOFTWARE TO HELP
CREATE TEST PROGRAMS
VTltest is a software package that eliminates the need for the design engineer to
be an expert In testers and testing. The
designer works in a test language called

VLSI TECHNOLOGY, INC.
INTRODUCTION

VLSI Test Language (VTL), which allows
simultaneous development of the circuit
design and test program, providing
notification early in the design stages of
when tester-specific details affect the
testability of the design. Through the
test language, designers can create a file
describing the physical characteristics,
timing, stimulus patterns and expected
responses of a circuit under development (Figure 2). The remaining software
translates the description into commands
that run the simulation, verify the
expected response, and store requested
response values predicted from a
simulator. Finally, VTltest generates a
complete test program that includes all
specifications for the timing generators,
strobes, and registers, all pattern
loading, requested dc parametric and
summary test routines, and the test
vectors needed to test the circuit
functionality.

Besides identifying tester limitations
associated with the test program, the
software suggests ways to work around
them. In that way, design engineers can
become familiar with tester limitations
and make the optimum design-vs-testing
trade-off. When the testability of a circuit
becomes a problem, the design engineer
can add additional circuitry to help out.
Common practice is to break up long
counter strings to reduce the number of
states required to exercise each individual stage.
The test vectors generated by the
software have a one-to-one correspondence with the vectors used during the
simulation, so the information normally
lost during post-processing is retained.
Another benefit is that, since a tester is
not needed to develop the test program
and initially debug it, the test system is
available for production time and work
can be done during normal hours.

To interface with specific testers, the
software needs routines that contain
tester-specific information. these
routines also identify portions of the test
or simulation language description that
can not be executed by the tester,
simplifying the task of making portable
test software. Interface routines are
currently written in Xidak's Mainsail
language for both VLSl's simulator and
the Sentry Series 7, 10, and 20 testers.
When defining an IC, designers can
define the stimuli and the expected
responses through the test language,
creating modules that describe aspects
of the circuit's functions or dc test
conditions. The resulting circuit description contains a complete set of
operational parameters, all information
necessary to create a data sheet is
present. Since that information actually
drives the simulator and develops the
test program, it always remains up-todate.

FIGURE 2. THE STRUCTUE OF THE VLSI TECHNOLOGY TEST LANGUAGE MAKES TEST PROGRAM GENERATION
SIMPLE AND STRAIGHT·FORWARD
TEST LANGUAGE DESCRIPTION

CORRECTION
--'"

EXPECTED RESPONSES

STIMULUS PATTERNS
SIMULATOR
LIMITATIONS

+
TRANSLATION INTO SIMULATOR
COMMANDS

J
SIMULATION

t
SIMULATION RESPONSES

COMPARISON AND COMBINATION

TESTER
LIMITATIONS

t
TRANSLATION INTO TEST PROGRAM

PRODUCTION TEST PROGRAM

TESTER
CHARACTERISTICS

VLSI TECHNOLOGY, INC.

DEFINING THE TEST PROGRAM
FLOW
Several types of software modules are
required to create a complete test
description. Designers use the first
module, MAIN, both to describe the
overall flow of the test and to initialize the
test software for execution. The contents of the MAIN module declare the
duration of a test, select the required
parameter modules, and specify their
order of execution. The MAIN module
partitions the testing into a number of
steps that can be easily understood from
a high level.
The DURATION statement determines
the length of the tester cycle, and
normal-time selects the timing parameter
module of that name. The WRITE
commands place remarks in the test
program file for documentation purposes.
The physical characteristics of the IC
and defined through the pin definition
(PINDEF) module, which contains a
declaration of the number of circuit pins
and statements that the test software
uses to identify pins during testing.
Those pin definition statements also
define pin type (input, output, bidirectional, power, etc.). In addition, the
module may define the device type and
state whether it is static or dynamic.
Labels for each element of the pin list
can specify such pin types as input,
output, bidirectional, power ground,
three-state, open-drain, open-source, or
no connection.
Minimum, nominal, and maximum timing
parameters are defined in the TIMEPARAM module. Designers can test the
circuit under different timing conditions
by defining multiple modules and
assigning each module its own identifier.
An additional module, EDGETIME,
creates transition edges using the
parameters defined by TIMEPARAM.
These edges determine when the
stimulus values are placed on the input
pins and when the response values are
measured during each test cycle,
indicating such timing points as when
outputs should be sampled and when
inputs should be changed. For example,
to create a clock that remains low for 80
ns, high for 100 ns, and repeats every
200 ns would require the definition of
four edges. The first edge would be at 0
ns, the second at 80 ns, the third at 180

INTRODUCTION
ns, and the fourth at 200 ns. The last
edge defines the period of the cycle and
is also used for the duration declaration.
For each test cycle, the CYCLE module
describes the stimulus for input pins and
the response for output pins. If parameter values are included within parentheses in the module heading, a variety of
values can be placed on the input pins.
Each time the module is called, the
appropriate values are passed to it. This
module takes transition edges from the
EDGETIME module and determines
when to apply stimulus values to the I/O
pins and when to measure outputs
during each test cycle. CYCLE statements in the modules specify whether a
specific pin is to be stimulated or
measured. A transition edge at a pin
may be specified by "@" time. If not
specified, the stimulus values are placed
on the pin at the beginning of the cycle
and the responses are measured at the
end of the cycle.
With FUNCTIONTEST modules, the
designer partitions the test into functional
blocks or initialization procedures,
particularly if the sections are to be used
more than one. The first DCPARAM
statement sets the minimum and
maximum measurement values as well
as the source that creates them (current
or voltage). Defaults are provided if
exact values have not been selected. An
important attribute of this module is that
some portions can be used more than
once. These modules are executed
when called by the MAIN routine or other
FUNCTIONTEST routines. They may
contain WH ILE and other looping
constructs to provide a means of
conditionally executing statements.
SIMULATION AND TEST PROGRAM
GENERATION
As the software generates the test
program, it draws on the stimulus and
response values to select each pin's
timing generators and strobes on the
basis of the value of the pin before the
cycle starts, the number of transitions
occurring on the pin during the cycle,
and if the pin is to be an input or output
during the cycle.
The selection of mask register is
determined by the state of the registers
at the start of the cycle and the pins that
have been activated during the cycle.
The appropriate values are inserted into

a test vector, which is stored in a vector
file with the register set or enabling
commands. Before storing the test
vector, the software attempts to take
advantage of any vector compaction
capability of the tester.
After the test language is used to create
the modules, the resulting description file
is loaded into VLSltest, which parsing,
the software creates a data base from
the physical characteristics described in
the PINDEF module and from the
identifiers used throughout the circuit
description. After the program is
properly compiled, testing may begin.
The test language itself possesses all
the power and flexibility needed to
efficiently develop test programs. All
variables and constants are 32-bit values
that may be manipulated on a bit-by-bit
basis by a variety of familiar operators,
such as AND, OR, and XOR. Additionally, the language's looping constructs
present a compact means of conditionally executing a series of tests.
COMPLETING THE DESIGN
Test engineering effort is still required
when using this process, but the time
spent can be a matter of only a few
weeks, rather than the several-week
period traditionally associated with
creating a test program for a new
product.
When simulation is complete and the
design works satisfactorily, the layout
process can begin. In most cases,
designers are interested in minimizing
design time and associated costs, so
they pick standard cells for the additional
blocks of logic that will surround the
megacell cores. Cells are individually
compiled, placed and routed to create
blocks of logic until the entire nonmegacell portion of the design is
complete. For the best layout efficiency,
the additional logic is either put into a
block having the same height as a
megacell, or it is put around the megace lis to fill in the voids. When each
portion of the design is completed, these
blocks can be placed and interconnected
using a tool call VLSICOMPOSE, which
is a top level composition editor. This
editor assists in interconnecting blocks of
cells and optimizing both the placement
and interconnection of cells. The overall
goal of placing blocks to form the chip is
to get the ratio of the X and Y dimen-

VLSI TECHNOLOGY, INC.
INTRODUCTION

sions (the aspect ratio) as close to 1:1 as
possible. The resulting square die gives
the packaging engineer the most
flexibility in package selection.
When the entire layout process is
complete, a netlist of interconnections is
extracted from the physical data base to
allow comparison of what was intended
to be with what actually was implemented. Once the extraction is complete
and the net list comparison between
schematic and layout is successful, the
device can be resimulated in software
with more accuracy, since values of
expected capacitance are extracted
along with the connectivity information.

Finally, the layout is checked for design
rule violations using the design rule
checker (ORe) program.
When all of this has been successfully
completed, the data base is sent to a
design center, where the actual physical
layout of the megacells is included in the
data base. When everything checks out
properly, a mask set i~ created and
silicon is started. From this point, the
fabrication time typically takes 8 weeks
for the first pass prototypes.

SUMMARY
Megacells offer a way to quickly design
chips that replace today's board level

function, while at the same time offering
competitive costs, increased reliability,
increased performance and reduced
board space. The design process
requires a wide range of design tools,
including standard cells, cell compilers,
simulators, routers, test program
generators, and libraries of designs.
VLSI Technology, Inc. specializes in
offering these kinds of tools in addition to
complete wafer services to provide a
total solution to systems designers.

VLSI TECHNOLOGY, INC.

VLSI TECHNOLOGY, INC.
ORDERING • PACKAGING

GENERAL
VLSI Technology, Inc., Logic Products devices are available in a variety of plastic and ceramic packages - including flatpacks,
chip carriers, and pin grid arrays - and in different temperature ranges. Specific information on the packages and temperature
ranges for particular devices is coded into the part number portion of the order information included in each data sheet.
This information is organized as:
VL

9999999

aa9999
Special Number Code

Environmental Grade Code
Temperature Code
Package Type Code
Bin Code (product-specific)
Base Part Number (up to seven digits; may include dash character)
SPECIAL NUMBER CODE

RC9999 is a ROM code number.
SL9999 is a special lead number
SM9999 is a special marketing number.
SS9999 is a special specification number.

ST9999 is a special test number.
ENVIRONMENTAL GRADE CODE

Blank (no entry) a information is not applicable.
I =a 48-hour dynamic burn-in.

TEMPERATURE CODE

C = O°C to +70°C (commerical operating temperature range).
I = --40°C to +85°C (industrial operating temperature range).
M = -55°C to + 125°C (military operating temperature range).

PACKAGE TYPE CODE

C = ceramic side-brazed dual in-line package (ceramic DIP).
D = cerdip.
F = flatpack.
G = ceramic pin grid array (PGA).
L = JEDEC type-B lead less chip carrier (LCC).
P = plastic dual in-line package (plastic DIP).
Q = plastic leaded chip carrier (PLCC).
The package forms indicated" by the codes are illustrated in the
outline drawings contained within this section.

PART NUMBER EXAMPLE

The part number VL68C45R-23PC SS0001 would indicate a
CMOS revision R version of the 6845 CRT controller having a
2 MHz bus clock and a 3 MHz character clock, housed in a
plastic DIP, operating over the commercial temperature range,
and tested to a special specification (#0001).

VLSI TECHNOLOGY, INC.
ORDERING • PACKAGING

PACKAGE CONSIDERATIONS
DUAL IN-LINE PACKAGES
The dual in-line package (DIP) has
been in high-volume production for
nearly twenty years, and is estimated
to have been the package of choice
for over 80% of all integrated circuits
shipped in 1985. Some 1986 usage
estimates are as high as 18 billion
units worldwide. Generally, devices
in DIPs can be purchased in two
types of ceramic (cerdip and sidebrazed) and in the very-familiar
molded plastic package. Over 85%
of all DIPs, or over 12 billion, sold
worldwide in 1985 were plastic.

The ceramic side-brazed package is
relatively expensive and is frequently
imported. It has excellent mechanical characteristics, including the
ability to survive extreme temperatures, salt water, and corrosive
atmospheres. However, as the cost
of the integrated circuit it houses
becomes less and less expensive,
the relative cost of the ceramic DIP
becomes a major concern. In a large
number of applications, this package
is several times more expensive than
the chip within it. As would be
expected, this package is very
popular in military electronics and in
other potentially harsh mechanical
environments. The side-brazed
package, while representing less
than 2% of all DIP packages shipped in 1985, represents a higher
percentage of DIP revenue, due to
its comparatively high average
selling price (ASP).
The cerdip is a "sandwich" of two
ceramic parts that are joined
together by a cement-like epoxy. The
die itself is mounted on a lead
frame, and enjoys many of the cost
economies associated with this
approach. The cerdip has some of
the mechanical advantages of the
side-brazed ceramic at a lower cost.
The cerdip represented about 14%
of all DIP shipments in 1985.
The plastic DIP has been the catalyst for the computer revolution. The
dramatic reduction in the cost of
microprocessors, microprocessor
peripherals, communications
devices, and memories has been
passed along to the manufacturers
and the final users because plastic

packaging has remained extremely
inexpensive. In addition, reliable
automated 16-pin and 14-pin DIP
insertion equipment has dramatically
reduced manual "board stuffing"
costs of DIPs. The plastic DIP itself
is easy to manufacture. The die is
mounted on a copper-alloy lead
frame and the plastic material is
molded around it. It is usually
branded by a printing method with
an epoxy-based ink but, recently,
laser-scribing the number into the
plastic body is gaining popularity,
reducing costs even further.
Mechanically, the DIP has proven to
be an extremely utilitarian package
in most applications. Its short, stiff
leads on 2.54 mm (0.1 inch, or
100 mil) centers allow reasonably
easy insertion for both test and
production by both manual and
automatic techniques. While more
expensive DIPs are placed in
sockets, the overwhelming majority
are soldered directly into the printed
circuit board. The 64-pin DIP, the
largest DIP in high-volume production, is used to house VLSI's VL2010
and VL2044 Multiplier/Accumulators.
DIP configurations with higher pin
counts tend to exhibit unacceptable
mechanical problems, such as
extremely high insertion and extraction forces.
DIPs are available, in even-pin-count
steps, in packages as low as two
pins. A variation of the DIP that has
gained some acceptance is the SIP,
or single in-line package. The SIP,
mounted lying on its edge, uses very
little printed circuit board space and
frequently contains a number of
memory die in high-density memory
applications. However, as desirable
as the SIP may seem, it is not the
major evolutionary path of the DIP.
The SIP allows little air circulation for
cooling, is hard to handle, and is not
generally accepted as a standard.
The DIP evolution lies in surface
mounting the device.
SMALL-OUTLINE
INTEGRATED CIRCUITS
The small-outline integrated circuit
(SOIC) is a descendant of the DIP.
Sometimes called the "Swiss" outline integrated circuit in honor of its

country of origin, this package solves
many of the problems of the DIP.
while retaining many of its advantages. The gull-wing lead rests on
top of the printed circuit board rather
than going through it. For most
types, its leads are exactly half the
length that the DIP's are, and it
maintains the same basic rectangular package aspect ratio of the
DIP. This, however, becomes a
disadvantage in high-pin-count
applications. For more than 28 pins,
many designers prefer the square
aspect of the plastic leaded chip
carrier (PLCC) to the SOIC. The
small package mass of the SOIC
does not allow the same thermal
diSSipation that can be expected in
a standard DIP, which becomes a
minor problem as more chips are
made in the generally lower power
consuming CMOS process. Most
importantly, the SOIC consumes
only about 30% of the real estate
consumed by the standard DIP. It is
estimated that nearly 1.5 billion
SOIC units will be shipped in 1986.
CHIP CARRIERS
Chip carriers have been around for
several years in various forms, and
are just now coming into widespread
usage. Generally, the terminal
spacing of chip carriers is 1.27 mm
(50 mils), but several special types
have 1.0 mm (40 mil) spacing for use
by companies engaged in the pocket
pager bUSiness. Some variations are
available in 0.64 mm (25 mils) also.
The ceramic versions of chip carriers
have become very popular in military
applications for the same reason the
ceramic side-brazed DIP has: their
mechanical ruggedness. Frequently,
ceramic leadless chip carriers
(LCCs) are soldered in; others use
connectors, while still others have
their own leads and are inserted as
a leaded device. Due to the
dissimilar coefficient of expansion of
materials (package alumina and
printed circuit board fiberglass) and
the lack of pins on the leadless
versions to provide flexibility or
compliance, the ceramic leadless
chip carriers should be soldered to a
material that has the same thermal
expansion characteristics as they
have. This has become very popular

VLSI TECHNOLOGY, INC.
ORDERING • PACKAGING

in military applications where weight
and space are at a premium and,
generally, cost is not the primary
consideration.
The plastic leaded chip carrier
(PLCC) has very quickly become the
most popular of all the chip carriers.
The PLCC represented about 61 %
of the chip carriers shipped in 1985
(approximately 400 million units).
Although there is debate on the
issue of board space consumption,
the PLCC and SOIC consume about
the same amount of board space in
the 24- to 28-pin configurations. In
lower pin count applications, the
SOIC seems to be more spaceeffective; when over 24 pins or so,
the PLCC seems to have the edge in
most applications. In applications
over 28 pins, the PLCC is the surfacemount package of choice. Its square
aspect ratio allows many chip
placements that the highly rectangular package of the SOIC does not.
In addition, there are rectangular
PLCCs to accommodate such rectangular die, such as memories.
CHIP-ON-BOARD MOUNTING
The ultimate in low-cost chip
mounting is achieved by the chip-onboard (COB) technology, in which no
discrete package is actually
employed. The die is soldered onto a
copper pad on a printed circuit
board. Bonding wires connect the
die to smaller bonding pads around
the die. The die and wires are then
covered by a dollop of epoxy. This
technique, while inexpensive, is not

generally accepted in industrial or
business equipment. It has been
extensively employed in video game
cartridges, and seems to work quite
well there.

mounted, "socketed," or suspended
through a cut-out hole in the printed
circuit board.

PIN GRID ARRAY
The pin grid array (PGA), or "bed of
nails, " has only been around for ten
years, but had a usage of about
5 million in 1985, and its popularity
is growing rapidly. This major
package variation allows very high
pin counts in relatively small spaces
with excellent mechanical and
thermal characteristics. The 149-pin
VL82C389 Message Passing Coprocessor (MPC) for Multibus® II
systems is a prime example of PGA
high-density trends. The major disadvantage of the PGA is its high cost.
Virtually all of the 5 million PGA
units shipped in 1985 were ceramic.
Plastic pin grid arrays are well along
in development, and will provide
reliable, inexpensive packaging for
the many high-pin-count ASIC,
memory, and other circuits coming
into wide usage.

SYSTEM CONSIDERATIONS
In the extremely competitive computer market that now exists, every
repetitive cost, no matter how small,
comes under close scrutiny. Drilling
a hole in a printed circuit board
costs about $0.001, a fairly small
amount until it is multiplied by the
thousands of holes that frequently
occur in each board. This becomes a
significant consideration at the
system level. Even though re-tooling
costs are high, many companies are
converting (some at least partially) to
surface-mounting equipment. Surface mounting allows more chips in
a much smaller area, but not all
functions are yet available in
surface-mount packages. Some companies have solved this problem by
designing both through-the-board
and surface-mount devices onto the
same board. Others continue to use
the older technology until they can
re-tool for 100% surface mount.

FLATPACK
The flatpack holds less than 1% of
the IC package market. True to its
name, it is flat, small, and has flat
leads usually in the same plane as
the package body. It is generally
harder to handle and test than the
other package types, but provides a
~urface mounting alternative to the
pin grid array in very-high-pin-count
applications. It is usually surface

Application-specific integrated
circuits (ASICs) and their support
devices are requiring packages with
ever-increasing pin counts. The pin
count domain diagram graphically
depicts the typical domain of pin
counts for five basic package types.
While there is a good deal of overlap,
chip carriers and pin grid arrays will
become the package of choice in
future systems containing devices of
high pin count. Since the PGA device

PIN COUNT DOMAIN

PIN GRID ARRAY

FLAT PACK

CHIP CARRIER

I""

DIP

11111111111111111111111111111111111111111
o

100
NUMBER OF PINS

®Multibus is a registered trademark of Intel Corporation.

125

150

175

200

VLSI TECHNOLOGY, INC
ORDERING • PACKAGING

does not support surface-mount
technology, chip carriers or flatpack
technology will have to be implemented as pin counts exceed 170
using surface-mount systems.

Table 1 examines some of the
characteristics of packages that will
probably occupy the overwhelming
majority of printed circuit boards in
the future. Leadless chip carriers will
be especially popular in military and
harsh industrial applications. The
DIP, with many billions already in
use, will not disappear, but its
percentage of market will decrease
steadily. Pin grid arrays will remain

CONCLUSION
There will be no panacea package
that will exclude the use of all others
in the future. While there are several
criteria for the system designer,

and increase in popularity as very
large devices become more popular
and plastic PGAs become readily
available. Surface mounting is
definitely a wave of the future for
many systems. SOIC packaging will
increase rapidly for devices of
28 terminals and under, while the
mid-range and higher terminal count
devices will be housed in PLCCs or
flatpacks.

1. While few designs subject devices to extreme cold, such conditions may
cause the devices to operate outside of their normal specified ranges.
Therefore, the minimum operating temperature specification must be
observed as well as the maximum operating temperature.

THERMAL CONSIDERATIONS
The devices in this data book have
undergone thorough evaluation and
characterization to ensure their
operation over the specified temperature ranges. While safety margins
are used for all parametric tests over
the temperature range, the designer
should not exceed the temperature
limits, even for extremely short
intervals. The following notes are
presented to ensure a reliable, longlived system using VLSI's products:

2. The ambient temperature (TA) specification refers to the air on the surface
of the device. The printed circuit board design should be open enough to
permit free air flow around the devices.
3. Avoid layouts that place NMOS, HMOS, or CMOS devices near such heat
sources as power regulators and devices requiring heat sinks. If the design
demands such proximity, ensure that the specified temperature range is not
exceeded.
4. Ensure that the power supply voltage is within the specified range. Both low
and high voltages beyond the specified limits may cause device
overheating.

TABLE 1. PACKAGE CHARACTERISTICS
JEDEC Leadless Chip Carriers

DIP

Ceramic

Plastic

SOIC

PLCC

Uses Socket or Connector

Yes

Directly Solderable

Yes

Feature

PGA

Minimum Usual Terminal Count

Maximum Usual Terminal Count

156

225

Pin Spacing

1.27
(50)

2.5
(100)

1.27/1.0
(50/40)

2.5
(100)

mm
(mils)

Relative Cost (1 = Most Costly)

VLSI TECHNOLOGY, INC
ORDERING • PACKAGING

PACKAGE OUTLINES
18·PIN CERAMIC SIDE·BRAZED DUAL IN·L1NE PACKAGE (DIP)

.175 (4.445)
.105 (2.667)

.930 (23.622)
.880 (22.352)

.325 (8.255)
.290 (7.366)

-1

I
.010 MIN
(.254)

-r-:--"i"====-.....,----L~~

.055 (1.397)
.025 (.635)
.065 (1.651)
.030 (.762)

L~.lIII_·~

060

(1.52~1

J~.038 (.96~

.021 (.533)
.015 (.381)

PLANE BASE

SEATING PLANE
.175 (4.445)
.125 (3.175)

.012 (.305)
.008 (.203)

_IIr-

.100 (2.54)
TYP

NOTES: UNLESS OTHERWISE SPECIFIED.
1. ALL METRIC DIMENSIONS ARE IN PARENTHESES (
2. TOLERANCE TO BE t.005 (0.127).
3. LEAD MATERIAL: ALLOY 42 (OR EQUIVALENT).
4. LEAD FINISH: GOLD PLATE OVER NICKEL.

18·PIN PLASTIC DUAL IN·LINE PACKAGE (DIP)

]

270 (6.858)
.230 (5.842)

~Tr'M""r'T't":I"1:'7Tr'M""rr.

. . "..., I~:~:.::;:::--I f.

.120 (3.048)

MAX

.320 (8.128)

'015~~11
u
=t;::~:'~::)PLANE
I- ~ti~~~4~ I

MIN
.060 (1.524)
MAX

TYP

.023 (.584)
.015 (.381)

200 (5.080)
MAX

.115 (2.921)

.015 (.381)
.008 (.203)

--tJ 105~
~I

.350T~p890)

.100 (2.540)
TYP

NOTES: UNLESS OTHERWISE SPECIFIED.
1. LEAD FINISH: MATTE TIN PLATE OR LEAD/TIN SOLDER.
2. LEAD MATERIAL: ALLOY 42 OR COPPER.
3. PACKAGE LENGTH DOES NOT INCLUDE END FLASH BURR, WHICH IS .010 (0.254)
MAX. AT EACH END.
4. TOLERANCE TO BE t.005 (0.127) UNLESS OTHERWISE NOTED.
5. METRIC DIMENSIONS ARE IN PARENTHESES (
).
6. PIN 1 INDEX MARK MAY VARY IN SIZE AND SHAPE.

VLSI TECHNOLOGY, INC.
ORDERING • PACKAGING

PACKAGE OUTLINES
20·PIN CERAMIC SIDE·BRAZED DUAL IN·L1NE PACKAGE (DIP)

I~~O]~::::

.10~(~N667)

1.030(26.162)
.980 (24.892)

I-I

MIN

~--~======~~~--1
.055 (1.397)

.325 (8.255)
.290 (7.366)

.010 (.254)

----.

BASE PLANE

t
--f

SEATING
PLANE

.025(0.635)_
__
IIL~60(1'~1
.065(1.651) _~38(.9~
.030 (.762) .021 (.533)
.100 (2.540)
.015 (.381)
TYP

.175(4.445)
.125(3.175)

.012 (.305)
.008 (.203)

-11__

NOTES: UNLESS OTHERWISE SPECIFIED.
1. ALL METRIC DIMENSIONS ARE IN PARENTHESES.

2. TOLERANCE TO BE ± .005 (0.127).
3. LEAD MATERIAL: ALLOY 42 (OR EQUIVALENT).
4. LEAD FINISH: GOLD PLATE OVER NICKEL.

20·PIN PLASTIC DUAL IN·L1NE PACKAGE (DIP)

c:::::::IJ:;::::~
.900 (22.860)

.2°'Ui~80)

REF

I
--l

.320 (8.128)

_1.05~~~.670)__

~
.015 (0.381)
MIN _

MAX

==f.125 (3.175)

~I
~
-+
l JIIL060i~:24) IL

.075 (1.905)

MAX

.155(3.937)

-J C.

.023 (0.584)
.015 (0.381)

~ (2.540)

SEATING
PLANE

.140(3.556)
.120 (3.048)

_~:'~

'" 10''''

.008 (0.203)

90'

.350 (8.890)
TYP

TYP

NOTES: UNLESS OTHERWISE SPECIFIED.
1. LEAD FINISH: MATTE TIN PLATE OR LEADITIN SOLDER.
2. LEAD MATERIAL: ALLOY 42 OR COPPER.
3. PACKAGE LENGTH DOES NOT INCLUDE END FLASH BURR, WHICH IS .010 (0.254) MAX
AT EACH END.
4. TOLERANCE TO BE ± .005 (0.127).
5. ALL METRIC DIMENSIONS ARE IN PARENTHESES.
6. PIN 1 INDEX MARK MAY VARY IN SIZE AND SHAPE.

VLSI TECHNOLOGY, INC.
ORDERING • PACKAGING

[ : : : : : : : : : I~~,:;:t j~~H,'w,
II ..,"'.'.""REF--/
~:;~~ :~;:;~~~

.200 (5.080)
.150(3.810)

.155 (3.937)
.125 (3.175)
~

~~~
~ I l==r:g~~G

.070(1.778)
.015 (0.381)

.085 (2.159)
.040 (1.016) -

~ .060 (1.524) _

.140(3.556)
.120 (3.048)

TYP
.100 (2.540)
.023 (0.584)
TYP
.015 (0.381)

NOTES: UNLESS OTH~~~\~Epi~~~I~~~EADITIN SOLDER.
1. LEAD FINISH: MAT
Y 42 OR COPPER.

~.4' PACKAGE
~i~DM~:~~t~~E~~~gNS
AREI~~t~~~~~~E~C;SH BURR, WHICH IS .010 (0.254)
LENGTH DOES NOT
• MAX AT EACH END.
5. TOLERANCE TO BE ± .005 (0.127).

VLSI TECHNOLOGY, INC.
ORDERING • PACKAGING

PACKAGE OUTLINES
24·PIN PLASTIC DUAL IN·LlNE PACKAGE (DIP)

~:::::::::]s:::~:
1 L-1.100 (27.940)-1
MAX

.165(4.191)
.135 (3.429)

til

.620 (15.748)

1.280 (32.512)

1---

MAX

- - - , .015(0.361)

~MIN
--.l SEATING

.200(5.080)
MAX

II ~11~'060(1'524) I
TYP

4---+-......-

.100 (2.540)
TYP

----.

PLANE

.140(3.656)
.120(3.048)

MAX

lOS·
90.

1_.650 (16.510)
TYP

.023 (0.584)
.015(0.381)

~
L·015 (0.381)
.008 (0.203)

NOTES: UNLESS OTHERWISE SPECIFIED.
1. LEAD FINISH: MATTE TIN PLATE OR LEAD/TIN SOLDER.
2. LEAD MATERIAL: ALLOY 42 OR COPPER.
•
3. PACKAGE LENGTH DOES NOT INCLUDE END FLASH BURR, WHICH IS .010 (0.254) MAX
AT EACH END.
4. TOLERANCE TO BE ± .005 (0.127).
5. ALL METRIC DIMENSIONS ARE IN PARENTHESES.
6. PIN 1 INDEX MARK MAY VARY IN SIZE AND SHAPE.

28·PIN CERAMIC SIDE·BRAZED DUAL IN·LINE PACKAGE (DIP)

I: ~I~~~~ ]~~:]5::~~:
I' "2 -

14
-"1.430(36.322) _ _ _1_3_• 1
1.360(35.052)
I
.010(.254)

r---

MIN

r,~~~~~~~~~~

·
t

625 (15.875)j
.595(15.113)
.600 (15.240)
TYP

r===1

.012(.305)_L
.008(.203)

NOTES: UNLESS OTHERWISE SPECIFIED.
1. ALL METRIC DIMENSIONS ARE IN PARENTHESES.
2. TOLERANCE TO BE ± .005 (0.127).
3. LEAD MATERIAL: ALLOY 42 (OR EQUIVALENT).
4. LEAD FINISH: GOLD PLATE OVER NICKEL.

VLSI TECHNOLOGY, INC.
ORDERING • PACKAGING

PACKAGE OUTLINES
28·PIN PLASTIC DUAL IN·LlNE PACKAGE (DIP)

[::::::::::]s:&~t,

1.300 (33.020)
REF

.165(4.191)
.135 (3.429)

.620 (15.748)

1.470 (37.338)
MAX

1.015 (0.381)

~.IN
-.! SEATING

":~X"· II

~11~'060(1'S24) I .140:~~NE
TY P

.100(2.540)
TY P

.023(0Ts4)

MAX

0~ j_~~~_381)
90'

.120 (3.048)

:015 (0.381)

'_.650(16.510)
TYP

.008 (0.203)

NOTES: UNLESS OTHERWISE SPECIFIED.
1. LEAD FINISH: MATTE TIN PLATE OR LEADITIN SOLDER.
2. LEAD MATERIAL: ALLOY 42 OR COPPER.
3. PACKAGE LENGTH DOES NOT INCLUDE END FLASH BURR WHICH IS .010 (0.254) MAX. AT EACH END.
4. TOLERANCE TO BE ± .005 (0.12n UNLESS OTHERWISE NOTED.
5. ALL METRIC DIMENSIONS ARE IN PARENTHESES.
6. PIN 1 INDEX MARK MAY VARY IN SIZE AND SHAPE.

28·PIN PLASTIC LEADED CHIP CARRIER (PLCC)

-[ R"{'"
o 0

.460 (11.664)

~~"".~ 1-1
MAX

4'AlLS~

... , . .,,'

07~Lti]
LL

.020
MAX

Jt.032 (0.812)
.050 (1.270)
TYP

.185(4.699)
MAX

.021 (.533)
.013 (.330)

NOTES: UNlESS OTHERWISE SPECIFIED.
1. TOLERANCE 10 BE ± .005 (0.127).
2. LEADFRAME MATERIAL: COPPER.
3. LEAD FNSH: MATTE TfoI PLATE OR SOLDER DIP.
4. SPACING 10 BE MAINTAINED BETWEEN FORMED LEAD AND MOLDED PLASTIC ALONG
FULL LENGTH OF LEAD.
S. MOLDED PLASTIC DIMENSION DOES NOT INCUJOE SI)E FLASH BURR, WHICH IS .enO
(0.254) MAX ON FOUR SIDES.
6. ALL METRIC DIMENSIONS ARE IN PARENTHESES.

VLSI TECHNOLOGY, INC.

~,;.

,,~

.'\"::'f'~.:.""

ORDERING • PACKAGING

PACKAGE OUTLINES
40-PIN CERAMIC SIDE-BRAZED DUAL IN-LINE PACKAGE (DIP)

.190 (4.826)

1.980 (50.292)

iN. )

010 254

.085 (2.159)

[600

~~~240)_1

,ro~~II~I~
=r:;;:HIL
L ir
L
(1.5~4)

.020 (.508)

.065 (1.651)
.030 (.762)

060
-038 ( 965)
__
•.
.023 (.584)
.015(.381)

.175 (4.445)
.125 (3.175)

.100(2.540)
TYP

.-.012(.305)
.008 (.203)

NOTES: UNLESS OTHERWISE SPECIFIED.
1. ALL METRIC DIMENSIONS ARE IN PARENTHESES.
2. TOLERANCE TO BE ± .005 (0.127).
3. LEAD MATERIAL: ALLOY 42 (OR EQUIVALENT).
4. LEAD FINISH: GOLD PLATE OVER NICKEL.

40-PIN PLASTIC DUAL IN-LINE PACKAGE (DIP)

[:::::::::::::::::: Is:::~
'
rH II ~11~'060(1'524) I :~:~:~::::
i
I

1.900 (48.280) REF

.165(4.191)
.135 (3.429)

1.015 (0.381)

2.080 (52.832) MAX

~M'N
-.1 SEATING

... , " " .

PlANE

MAX

----.

4--

.100 (2.540)
TYP

.023 (0.584)
.015(0.381)

TYP---+.090 (2.286)
MAX

NOTES: UNLESS OTHERWISE SPECIFIED.
1. LEAD FlMSH: MATTE TIN PLATE OR LEAD/TIN SOLDER.
2. LEAD MATERIAL: ALLOY 42 OR COPPER.
3. PACKAGE LENGTH DOES NOT INCLUDE END FlASH BURR, WHICH IS .010 (0.254) MAX
AT EACH END.
4. TOLERANCE TO BE ± .005 (0.127).
5. ALL METRIC DIMENSIONS ARE IN PARENTHESES.
6. PIN 1 INDEX MARK MAY VARY IN SIZE AND SHAPE.

.620 (15.748)
MAX

blOC;

_\-'015(0'381)

90.

1_.650 (16.510)
TYP

.008 (0.203)

VLSI TECHNOLOGY, INC
ORDERING • PACKAGING

PACKAGE OUTLINES
44·PIN PLASTIC LEADED CHIP CARRIER (PLCC)

-Iq"f
.660 (18.784)

MAX

_ -_ _ .695Jl~653)

.185 (4.699)

MAX

NOTES: UNLESS OTHERWISE SPECIAED.
1. TOLERANCE TO BE ± .005 (0.127).
2. LEADFRAME MATERIAL: COPPER.
3. LEAD FINISH: MATTE TIN PlATE OR SOLDER DIP.
4. SPACING TO BE MAINTAINED BETWEEN FORMED LEAD AND MOLDED PlASTIC ALONG
FULL LENGTH OF LEAD.
5. MOLDED PlASTIC DIMENSION DOES NOT INCLUDE SIDE FLASH BURR, WHICH IS .010
(0.254) MAX ON FOUR SIDES.
6. ALL METRIC DIMENSIONS ARE IN PARENTHESES.

4..PIN CERAMIC SIDE·BRAZED DUAL IN·LlNE PACKAGE (DIP)

[: : :: I::: 1::::::::]j::::
,

/•

28/

2.430 (61.722)
2.380 (60.452)

•
.010(.254)

r:::-~:::-::::-=:-::::,-:::-::-:::-==-=-=-=-=::-::=-=-=-=-=::-::=-=-=-~~~N

.100(2.540)
TYP

_1/1_

.060(1.524)
.038(.965) _ _
.023(.534)
.015(.381)

NOTES: UNLESS OTHERWISE SPECIFIED.
1. ALL MeTRIC DIMENSIONS ARE IN PARENTHESES.
2. TOLERANCE TO BE ± .005 (0.127).
3. LEAD MATERIAL: ALLOY 42 (OR EQUIVALENT).
4. LEAD FINISH: GOLD PlATE OVER NICKEL.

BASE PLANE

'tLSEATING
PLANE
.175(4.445)
.125(3.175)

-t

.625(15.875)

A
I

.595(15.113) --

L·

.012(.305)
008 (.203)

-IL
I

.600 TYP-

VLSI TECHNOLOGY, INC.
ORDERING • PACKAGING

PACKAGE OUTLINES
48·PIN PLASTIC DUAL IN·LINE PACKAGE (DIP)

[:::::::::::::::::::::: Is : : : :
I

2.300 (58.420)
REF

:!.!.5 (4.445)
.145 (3.683)

tB- " "
i
2.450 (62.230)
MAX

.200 (5.080)

MAX

I ij II ij

- - l I I L .060(15.240)
TYP

----+..--

.100 (2.540)
TYP

'1.015 (0.381)

--.

4----

SEATING
PLANE

:!~Q~5~)

.120 (3.048)

----.

.023 (0.584)
:010 (0.254)

.075 (1.905)
MAX

.620 (15.748)
MAX

~1:
~
goo -\--

1_.650 (16.510)
TYP

.()15 (0.381)
.008 (0.203)

NOTES: UNLESS OTHERWISE SPECIAED.
1. LEAD ANISH: MATTE TIN PLATE OR LEAD/TIN SOLDER.
2. LEAD MATERIAL: ALLOY 42 OR COPPER.
3. PACKAGE LENGTH DOES NOT INCLUDE END FLASH BURR, WHICH IS .010 (0.254) MAX
AT EACH END.
4. TOLERANCE TO BE ± .005 (0.127) UNLESS OTHERWISE NOTED.
5. METRIC DIMENSIONS ARE IN PARENTHESES.
6. PIN 1 INDEX MARK MAY VARY IN SIZE AND SHAPE.

64·PIN CERAMIC SIDE·BRAZED DUAL IN·LINE PACKAGE (DIP)

6463

3433

1..-

1 2 3

11----------

3.240(82.296)
MAX

.914(23.216)
.884(22.454)

3132

720 (18.288)--1
0 MAX

1
010( 254)
.~

.190(4.826)MAX

~.=---rBASEPLANE ~

.070(1.~1 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ I~I ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~~~~!~~G ~

.020(.50~

.065(1.651)
.030(.762)

--l L
.100(2.540)
TYP

--lIIL.060(1.524)
.038(.965)

.Q;(.;;)
.015(.381)

NOTES: UNLESS OTHERWISE SPECIFIED.
1. ALL METRIC DIMENSIONS ARE IN PARENTHESES.
2. TOLERANCE TO BE ± .005 (0.127).
3. LEAD MATERIAL: ALLOY 42 (OR EQUIVALENT).
4. LEAD ANISH: GOLD PLATE OVER NICKEL.

.175(4.445)
.125(3.175)

.930(23.622)
900 (22.860) ~
"---"

---IL·012(.305)
.008(.203)

~
~

VLSI TECHNOLOGY, INC
ORDERING • PACKAGING

PACKAGE OUTLINES
64·PIN PLASTIC DUAL IN·LlNE PACKAGE (DIP)

[:::::::::::::::::::::::::::::::I~:

PIN 1 /

3.100 (78.740)
REF

NOTES: UNLESS OTHERWISE SPECIFIED.
1. LEAD FINISH: MATTE TIN PLATE OR LEAD/TIN SOLDER.

2. LEAD MATERIAL: ALLOY 42 OR COPPER.
3. PACKAGE LENGTH DOES NOT INCLUDE END FLASH BURR, WHICH IS .010 (0.254) MAX
AT EACH END.
4. TOLERANCE TO BE ± .005 (0.127).
5. METRIC DIMENSIONS ARE IN PARENTHESES.
6. PIN 1 INDEX MARK MAY VARY IN SIZE AND SHAPE.

S8·PIN PLASTIC LEADED CHIP CARRIER (PLCC)
--.045 (1.143)

PIN 1 INDEX
MAY VARY IN
SIZE AND
LOCATION

1-_ _ _ _ _ .995 ~iSX273)---------i

NOTES: UNLESS OTHERWISE SPECIFIED.
1. TOLERANCE TO BE ± .005 (0.127).
2. LEADFRAME MATERIAL: COPPER.
3. LEAD FINISH: MATTE TIN PLATE OR SOLDER DIP.
4. SPACING TO BE MAINTAINED BETWEEN FORMED LEAD AND MOLDED PLASTIC ALONG
FULL LENGTH OF LEAD.
5. MOLDED PlASTIC DIMENSION DOES NOT INCLUDE SIDE flASH BURR, WHICH IS .010
(0.254) MAX ON FOUR SIDES.
6. ALL METRIC DIMENSIONS ARE IN PARENTHESES.

VLSI TECHNOLOGY, INC

ORDERING • PACKAGING

PACKAGE OUTLINES
58·PIN LEADLESS CHIP CARRIER (LCC)

SEATING PLANE;
ELECTRICALLY
ACTIVE PLANE
ON THIS SIDE

,.....".~---PIN1

-L

.093 (2.362)
.077 (1.955)
LEAD 1 ONLY

.072 (1.829)
- - .058 (1.473)

NOTES: UNLESS OTHERWISE SPECIFIED.
1. TOLERANCE: ± .005 (0.127).
EAS' GOLD-PLATED (60 MICROINCHES MIN.
2. THICKNESS)
ALL EXPOSED
MICROINCHES
MIN., 350 MICROINCHES MAX.)
OVER NICKEL
ON.
OVER REFRACTORY METALUZATI
3. MATERIAL: AL2 O,
ECTIC

METALUZED(~~

~~LS~~~I~~~~~~I~~S ARE iN PARENTHESES.

040 (1.016) x 45

UJJJ..Q..QJ:U:IJJJ.J..~LJJ..u.:lJ.j,..w.~~II-T- CHAMFER INDEX CORNER

.083 (2.108)
....069 (1.753)

METRIC DIMENSIONS ARE IN

MILUMETERS.
~. JEDEC TYPE B PACKAGE.

( .595 (15.113)

MT'·

If==:

.800 (20.320)
4PLS

~.940(23.876)

.965 (24.511)

__ I

.965 (24.511 )
---I
.940
(23.876

•

VLSI TECHNOLOGY, INC.
.

ORDERING • PACKAGING

PACKAGE OUTLINES
84-PIN PLASTIC LEADED CHIP CARRIER (PLCC)

PIN 1 INDEX
MAY VARY IN
SIZE AND
LOCATION

1.160 (29.454)
MAX

0000000

1...--------

1.195 (30.353) _ _ _ _ _ _ _1
MAX

C-__________~--~'~'j'
I .050
(1.270)
~~ .032 (.812)
ITYP
.025 (.635)

.185M~X699)

.015 (.361)
UNLESS
1.

OTHERWISEN~g~~I!~~

IN PARENTHESES.

~~~~~T~II~E~~~NS ARE IN MILLIMETERS.

2. TOLERANCE

~~:iRI~~.0~6~~~~:

~: SPACING
t~~gF~~~~:
MATTE TIN PLA~~~;E~~L~5~:~~' LEAD AND MOLDED PLASTIC
TO BE MAINTAINED
I

5. ALONG FULL LENGTH OF LEAD
NOT INCLUDE SIDE FLASH BURR, WHICH S
riOES
6 MOLDED PLASTIC DIMENSION DES
.. 010 (0.254) MAX. ON FOUR SI
.

VLSI TECHNOLOGY, INC.
ORDERING • PACKAGING

PACKAGE OUTLINES
84-PIN LEADLESS CHIP CARRIER (LCC)

1.010 (25.654)
.099 (25.146)
4 PLS

.676 (17.170)
.664 (16.855)
1.161 (29.469)
1.139 (28.930)

=tj

II I! III! II I! I! I! I! I! I! I! I! I! I! I! I!

ill!

I! I! I! I

ELECTRICALLY ACTIVE PLANE ON THIS SIDE

~N;~~~~:~I~R~~iN~~;~~~~~ IN PAREEN~~ESES .
. METRIC DIMENSIONS ARE IN MILLIMET

.050TQp270)
.077 (1.956)
.063 (1.600)

SEATING PLANE

.066 (1.676)
.054 (1.372)

~7CROINCHES

2 TOLERANCE TO BE f·005 (0.127).
ALL BE GOLD.PLATED (60 MICROINCHES
3: ALL EXPOSED METALLIZED AREAS
MIN., 350 MICROINCHES
MIN THICKNESS) OVER NICKEL (50
MAX.) OVER REFRACTORY METALLIZATION.
4 MATERIAL: AI,O,.
5: JEDEC TYPE B PACKAGE.

VLSI TECHNOLOGY, INC.
ORDERING • PACKAGING

PACKAGE OUTLINES
100·PIN PLASTIC FLATPACK (CJQFP)

PIN 1

0.793 (20.1S)
0.782 (19.8S)

1.031 (26.20)
0.984 (2S.00)

0.023 (0.S8) TYP
0.120 (3.0S)

.026 (0.6S)

L
--1-0.100 (2.ss)

I ,.126

__ . .-....
~ ...._ _ _'\

0.008 (0.20)
O.OOS (0.13)

-i--

0.130 (3.30)
0.100 (2.SS)

-t

SOTYP

0.D16 (0.40)
0.008 (0.20)

DIMENSIOEN;J~~~~D

4: LEADFRAME: ALLOY

HITACHI CHE EN.4000, KASEl EPINAR 4110

~~L~~~~~~~J~~~tMITOMO 6300, KASEl CEl 4000

0.083 (2.10)
0.043 (1.10)

0.010 (0.2S)

NOTES: UNLESS OTHERWISE ~P~~J~'WNL Y FOR PROTOTYPE BUILDS.
1 THE CJOFP ARE CURRENTL
PARENTHESES.
2: ALL METRIC
AND EPOXY SEALED.
3 CJOFP ARE EPOXY 01

(3.20t~

.094 (2.40)

VLSI TECHNOLOGY, INC.
ORDERING • PACKAGING

PACKAGE OUTLINES
149·PIN CERAMIC PIN GRID ARRAY (PGA)

.050 (1.270)
DIA STAND OFF
4 PLS

.070 (1.778)
DIA TYP

000000 000000
--~~J00000000000000
~~~~0000000~~~~
0

.O~O U~2)
3 PLS
CHAMFER

~
.158 (4.013)J

D=q
CH~':~~R

~~~~

1.412 (35.865)
1.388 (35.255)

~~~0

c=:=,~~:,~~~~)

00000000000000~

-----'----t1~)000000000000
.100

'" "''')
~

1~)

.099 (2.514)

:~:: :::~~~:
lJ!,r_U lflf
lrlflflflflflfnnf
i
UUU U

.190 (4.826)

"I r-

.020 (.508)
.016 (.406)

.05~ ~U70)

~N;~iSM~~~~~~II~i::r~~I~I!~~

IN PARENTHESES .
. METRIC DIMENSIONS ARE IN MILLIMETERS.
2. TOLERANCE TO BE ± .005 (0.127).
3. MATERIAL: AI,03.
4. LEAD MATERIAL: KOVAR.
5.

000
000
000
000
000
000
000
0000

00000000000000~

.075 (1.905)

PIN 1 INDEX

000
000
000
000
000
000

ING (60 MICROINCHES MIN. THICKNESS) OVER

~~t~E~I~I~~ ~~C~~~~~~~TNOMINAL THICKNESS).

.170 (4.318)

:::: :::::::
REF

(2i~~0)

VLSI TECHNOLOGY, INC
VL16160
RASTER OP ALU

FEATURES

DESCRIPTION

• Provides hardware assist for bitmapped graphics operations. Includes
32-bit barrel shifter

The VL 16160 Raster Op ALU (RALU)
provides hardware-assisted performance enhancements for bit manipulation
operations used in bit-mapped graphics
displays. These operations, called bit
block translation (BITBL
allow bitmapped images to be combined and
manipulated by logical operators.
These operators include AND, OR, and
XOR, and can be used on source,
destination, and pattern data. Additionally, support for masking with multiple
mask registers for clipping is included.

• Performance increase over software
implementations:
-Monochrome - 4 x Software
-COlor - 4 x (Planes) x Software
• Supports both CRT displays and such
hardcopy devices as laser printers
• Compatible with both monochrome and
color displays
• Implements all 256 possible raster
operations on source, destination,
and pattern data

• 28- pin package; 5 V supply

The BITBLT operation is general
purpose enough to be used in a wide
range of graphics operations, including
text display using arbitrary fonts,

PIN DIAGRAM

BLOCK DIAGRAM

attributes, and enhancements. Successive applications of BITBLT can perform
such operations as scaling, filling,
rotations, and texturing.
In a typical application, the RALU
operates on display data in 16-bit words
that are latched into its input buffers by
external hardware. Once source,
destination, pattern, shift, and masking
data are loaded into the RALU, the
source data is bit-aligned with the
destination data, and the logical
operation specified in the function
register takes place. The results are
stored in the ALU Output Register,
which can be output onto the bus by a
single strobe signal.

VL16160
AO

vee

A1
A2.

-AD

A3
-CS
DO

01
D2
03
D4
OS
C6
07

GNO

-WR
-LooTB
-LSSTB
-AOSTB
015
014
013
012
011
010

PATTERN
DD-..I.z1.;.;;5;....._ _ _ _~
S.u-~__
D_ES_T_IN_A_T_IO_N__~

09
DB

ORDER INFORMATION
Part
Number

Package

Vl16160PC
VL16160CC
Vl16160aC

Plastic DIP
Ceramic DIP
Plastic Leaded Chip Carrier (PLCC)

Note: Operating temperature range is O°C to +70°C.

VLSI TECHNOLOGY, INC
VL16160

PIN DIAGRAM
VL16160-QC

-CS
DO

01
02
03
04
05

432 1282726
5
6
7
8
9
10
11

•

24
23
22

21
20

-LOSTB
-LSSTB
-AOSTB
015
014
013
012

12 13 14 15 16 17 18

SIGNAL DESCRIPTIONS
Signal
Name

Signal

Number

Description

00-015

6-15

Bidirectional data lines; input enabled by -eS and -WR. Input data to Destination
Register must be stable relative to the trailing edge of -LDSTB. Output enabled by -eS,
-RD, and AO-A3 or -AOSTB.

-CS

Chip Select; Must be active to write to or read from internal registers.

-RD

Read Enable; Input used to strobe any internal register data to the data bus pins. Must
be active in conjunction with -eS.

-WR

Write Enable; Input used to "mobe data on data bus pins into the selected register. Must
be active in conjunction with -eS.

AO-A3

1-4

-AOSTB

ALU Output Strobe; Input used to enable the output of the function decoder onto the data
bus pins. Cannot be active when -eS and -RD or -WR are active.

-LDSTB

Load Destination Register Strobe; Input used to strobe the value (address) on the data
bus pins into the Destination Register. Value on AO-A3 need not be valid when -LDSTB
is used to load the Destination Register. The -LDSTB pin also decrements the op
counter each time it is pulsed.

-LSSTB

Load Source Register Strobe; Input used to strobe the value on the data bus into the
Source Register specified by the Direction Bit. The other Source Register is loaded with
the previous contents of the Source Register being loaded.

GND

Ground

VCC

+5V±5%

VLSI TECHNOLOGY, INC.
VL16160

FUNCTIONAL
DESCRIPTION
The Vl16160 consists of four basic
blocks: Source Shifter, Function
Decoder, Op Counter, and the Register
set. The internal data bus is 16 bits
wjQe, enabling all internal registers to
be accessed easily from the 1/0 bus for
context saving and restoring. In
operation, the Source Shifter extracts
data from the Source Registers and
shifts the data to be aligned with the
data in the Destination and Pattern
Registers. The Function Decoder then
performs a 16-bit Boolean operation as
specified by the Function Register with
the data extracted from the Source
Registers and the data in the Destination and Pattern Registers. The result of
the Boolean operation is available on
the external 1/0 bus when the -AOSTB
signal is strobed and can easily be
written back into display memory. The
Op counter and associated registers
provide the support for clipping
operations as required by the application.

SOURCE SHIFTER
The Source Shifter performs bit
alignment on the concatenated 32 bits
of data in the Source 1 and Source 2
Registers. The amount of bit alignment
performed is based upon the value in
the Shift Value Register. When -lSSTB
is strobed, the Source Shifter extracts
16 contiguous bits from the 32 bits of
data in the Source 1 and Source 2
registers as follows:
1. If the low order four bits of the Shift
Value Register have a non-zero
value, that value specifies the shift
count by which the 16-bit field to be
extracted is offset from bit 0 of the
concatenated source registers, as
shown in Figure 1. The result is
passed on to the Function Decoder.
2. If the low-order four bits of the Shift
Value Register is 0, the contents of
either Source 1 or Source 2 are
passed directly to the Function
Decoder and no shifting occurs. The
direction bit indicates which source
register is used in the operation, as
shown in Figure 1.

FUNCTION DECODER
The Function Decoder performs a
Boolean operation on the contents of
the Destination Register, Pattern
Register, and the output of Source
Shifter. The Boolean operation is
specified by the Function Register. With
the three operands, 256 different
Boolean operations are possible. The
result of the operation is available on the
1/0 bus when the -AOSTB control signal
is active. -AOSTB signal cannot be
active at the same time that -CS and
-RD or -WR are active. The result of
the Boolean operation is also available
by reading the AlU Output Register.
To understand how the Function
Decoder performs the desired Boolean
operation, note again that with three
operands, (data in the Source, Pattern
and Destination Registers), a total of
256 different boolean operations is
possible. Out of these 256 possible
operations, the application defines
which are needed to perform the desired
task.
For example (see Figure 2), to "paint" a
new image over an existing image
requires the source data (image) to be
ORed with the destination data (image).
This means "Source Register OR the
Destination Register". For each bit,
there are four possible results of this
operation between these two registers.
However, since the Pattern Register is
always included, even when it is a "don't
care," a total of eight different possible
results of this one Boolean operation is
possible. These eight combinations
define the "function code" for the overlay
operation. Thus, the function code is
really defined as the result (and the only
result possible) of a Boolean combination of the Source, Destination, and
Pattern Registers. In using the
Vl16160, the application defines which
of the 256 possible Boolean combinations of the Source, Destination and
Pattern Registers define those "functions" required of the application, and
when that "function" is required, the
corresponding function code is loaded
into the Function Register.
In principal, the Function Decoder
operates on a bit-by-bit basis as a 1-of-8
data selector with each data bit in the

Source, Destination, and Pattern
Registers selecting one of eight bits of
data from the Function Register.
The function codes required of an
application are determined ahead of
time by the user and stored in memory
to be used as needed. The determination of the correct function code is a
matter of simply applying the definitions
stated above (see Figure 2), in a simple
method. The truth table for Pattern,
Source, and Destination bits is written,
with the desired output. This desired
output is read as the desired value of
the Function Register, with the least
significant b~ as shown in Figure 2.
Using this method, the software
engineer can easily define a pattern to
suit each specific need.

OP COUNTER
The Op Counter, in conjunction with the
Width and Mask Registers, provides for
masking of selected bits in the Destination Register. This masking prevents the
Vl 16160 from modifying selected areas
of display memory when performing
BITBlTs. For example, clipping may be
required at the edges of a window. The
function of the Op Counter is to keep
track of the beginning and end of each
row, so that the mask registers can
handle this clipping automatically,
without additional processor intervention.
The Op Counter must be correctly
initialized prior to the beginning of a
raster operation. The enabling of
masking is internally clocked by the
-lDSTB signal. For this reason, after
loading the Op counter with an initial
value, -lDSTB must be pulsed before
the -LSSTB of the first operation. Since
this -lDSTB will decrement the Op
Counter, it is necessary to increment the
Op Counter to be one more than the
intended value, so that this "dummy"
-lDSTB starts out the BITBlT with the
correct Op Counter value. This "dummy"
-lDSTB does have to be repeated
between scan lines, as the masking
remains enabled. If context switching is
utilized, however, reinitialization (with
the loading of Op Counter and subsequent -lDSTB) is necessary before
leaving a context, or upon re-entering
one, in the middle of a BITBlT.

VLSI TECHNOLOGY, INC.
VL16160

REGISTER DESCRIPTION
As shown in the block diagram, the
RALU consists of a number of registers,
each connected to the internal 16-bit
data path. Of these registers, three are
used very often and are directly accessible from the data bus by the assertion
. of strobe signals.

DIRISHIFT
This register controls the direction of the
raster operation (Ieft-to-right or right-toleft). In addition, it specifies the number
of bits to shift to align the source with
the destination fields.
MASK 1 and2
These registers are used to define the
left and right boundaries of the area on
the screen that is manipulated. (The
direction bit affects which register
corresponds to left vs. right). A bit set
in these registers allows the corresponding bit in the Destination Register
to pass through unaltered. When the Op
Counter is equal to the Width Register
(usually for the first raster operation on
each scan line), the Mask 1 Register
selects bits to be included in the
operation. Masking is disabled until the
Op Counter is zero (usually for the last
operation on a scan line); at that time,
the Mask 2 register is used.

SOURCE
The Source 'Register holds a 16-bit word
of data to be modified by a raster
operation. It is loaded from the data bus
by the assertion of the -LSSTB signal.
DESTINATION
The Destination Register holds a word
of data from the bit-mapped display that
is modified by the source data and
raster operation. It is loaded from the
data bus when -LDSTB is asserted.
ALUOUTPUT
The ALU Output Register holds the
result of the raster operation to be
written back to memory. The contents
may be put onto the data bus by the
assertion of the -AOSTB signal.

PAlTERN
This register contains data to be
combined with the output of the bitshifted source register. This is commonly used for enhancing an image
with a background pattern.

The remainder of the registers are
typically set up for a series of operations
and are not changed until the end of a
scan line.

FUNCTION
This register contains the operator that
is used to combine the source, destination, and pattern data.
OPCOUNTER
The Op Counter Register specifies the
current count of the operation in
progress. The Op Counter is decremented each time -lDSTB is brought
active. After the Op counter goes to
zero, the next -LDSTB causes the Op
counter to be reloaded with the value of
the Width register prior to the next
operation. The Op counter can be set to
the value of the Width Register at the
start of a raster operation by beginning
an operation with a "dummy" -LDSTB.
This loads the Op counter in preparation
for the first scan line.
WIDTH
The Width Register specifies the width
of the line (in 16-bit words) on which
raster operations will take place.
FLAG REGISTER
The Flag Register is uncommitted and
can be used to temporarily store context
information for multi-tasking implementations.

FIGURE 1. SHIFTING AND DIRECTION

D15

D8 D7
UNUSED

IDIRI

DO
SHIFT VALUE

DIRECTION I SHIFT VALUE REGISTER

(DATA BUS)

4
-1

SOURCE 2

SOURCE 1

H
H

SOURCE 1

DIRECTION

SOURCE 2

DIRECTION

VLSI TECHNOLOGY, INC.
VL16160

TABLE 1. REGISTER MAP

Destination Register

Source 1 Register

Source 2 Register

Pattern Register

Mask 1 Register

Mask 2 Register

Shift Value Register

Function Register

Width Register

Operation Count
Register

ALU Output Register

Reserved

Flag Register

VLSI TECHNOLOGY, INC.
VL16160

FIGURE 2. RASTER OPERATIONS EXAMPLE

Source Memory

Destination (new)
Function = "OR" Operation
(Pattern not used)

Pattern
Destination (old)
FIGURE 2a. SOURCE XOR DESTINATION (6616>

.---------,

Pattern

0
0
0
0
1
1
1
1

Source

0
0
1
1
0
0
1
1

Funct.

0
1
0
1

0
1
1
0
0
1
1

MSB

LSB

0
1
0
1

FIGURE 2d. SOURCE XOR DESTINATION OR PAT. (6F16>

Example

Dest.

Pattern

0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

Dest.

Funct.

0
1
0
1
0
1
0
1

0
1
1
1
0
1
1
1

Example

Source

0
0

0
1
1

0
1
1
1
1

0
1
1

Dest.

Funct.

0
1
0
1
0
1
0
1

0
0
1
1

1
1
1
1

Pattern

MSB

0
0

0
0
1
1
1
1

LSB

0
1
1

Funct.

0
1
0
1
0
1
0
1

0
1
1
0
1
1
1
1

Example
MSB

~-Pattem

LSB

Source

0
0
1
1
0
0
1
1

Dest.

Funct.

0
1
0
1

0
1
1
1
1
1
1
1

0
1

Example
MSB

~-Pattefn

LSB

FIGURE 2f. SOURCE OVERLAY DEST. OR PAT. (1F16)

FIGURE 2c. SOURCE OVERLAY DESTINATION (3316)
Pattern

0
1

Dest.

FIGURE 29. SOURCE OR DESTINATION OR PAT. (7F16)

,,---,,:~------,

Source

0
0

FIGURE 2b. SOURCE OR DESTINATION (7716>
Pattern

Source

Example

Pattern

0
0
0
0
1

0
1
1

1
1

MSB

1
LSB

Dest.

Funct.

0
0

1
1

0
1
0

0
0
0

Source

0
0
1

MSB

0
1

1
1

ImmS8 - Paltern

LSB

VLSI TECHNOLOGY, INC.
VL16160

ABSOLUTE MAXIMUM RATINGS
Supply Voltage
-0.5 V to +7.0 V
Input Voltage
-0.5 V to +7.0 V
Output Voltage
-0.5 V to +7.0 V
Operating Temperature O°C to +70°C
Storage Temperature -65°C to +150°C
Lead Temperature (10 s.)
300°C
Junction Temperature
175°C

DC CHARACTERISTICS

Stresses above those listed under
"Absolute Maximum Ratings" may
cause permanent damage to the
device. These are stress ratings only.
Functional operation of this device

under these or any other conditions
above those listed in this specification
is not Implied. Exposure to absolute
maximum ratings conditions for
extended periods may affect device

TA- O°C to +70°C, VCC- 5 V ±O 25 V

Symbol

Parameter

Min

VIH

High-Level Input Voltage

2.4

VIL

Low-Level Input Voltage

VOH

High-Level Output Voltage

VOL

Low-Level Output Voltage

IOH

Hiah-Level Outout Current

-400

10L

Low-Level Output Current

4.4

ilL

Input Leakage Current

11/0

110 Leakage Current

Typ

0.6

Conditions

2.4
0.3

0.45

VCC ... Min; 10Ha -400 JlA

VCC.. Min; 10L.,. 4.4 mA

JlA

VI- 0.45 V

20
JlA
100

0.4 V < Va < Vee
Power Supply Current at DC

CAPACITANCE

Unit
V

0.7 V < Vo < Vee

ICC

Max

120

VCC. Max

TA= O°C to +70°C

Symbol

Parameter

CliO

110 Capacitance

Input Capacitance

Min

Typ

Max

Unit

Conditions

VLSI TECHNOLOGY, INC.
VL16160

AC TIMING CHARACTERISTICS

TA =O°C to +70°C, VCC 5 V ± 0.25 V
Max

Symbol

Parameter

Min

tCSH

-CS, AO-A3 Hold After -WR Active

tRWW

-WR, -RD Signal Width

tCSS

-CS, AO-A3 Setup to -WR Inactive

CSV

Data Valid After -CS Active

120

tRDV

Data Valid After -RD Active

120

tRDH

Data Valid After -RD, -CS Inactive

tWRS

Unit

Data Setup to -WR Inactive

tWRH

Data Hold After -WR Inactive

tLSW

-LSSTB Pulse Width

tNLS

Time Between -LSSTB Pulses

tSDV

-LSSTB Inactive to Valid Data

LSF

-LSSTB Inactive to AOstb Active

tLDV

-LSSTB Active to Valid Data

tLDW

-LDSTB Pulse Width

tNLD

Time Between -LDSTB Pulses

tLDF

120
30

ns
ns

170

150

-LDSTB Inactive to -AOSTB Active

tLSS

Data Setup to -LSSTB Inactive

tLSH

Data Hold after -LSSTB Inactive

tLDS

Data Setup to -LDSTB Inactive

tLDH

Data Hold After -LDSTB Inactive

tFOV

Data Valid After -AOSTB Active

tDDV

Data Valid After Valid -LDSTB Data

tFDV

Bus High-Impedence After -AOSTB Inactive

140

Conditions

VLSI TECHNOLOGY, INC.
VL16160

FIGURE 3. REGISTER READIWRITE TIMING

AO-A3,-CS

VALID

-RO
tROH

-WR

tCSV~

tROV~

00-07

VALID

FIGURE 4. SOURCE REGISTER AND ALU OUTPUT CONTROL SIGNAL TIMING

~-------------tNLS

-LSSTB

~~------------tSOV

_ _~t------ tLSF

•
•

4 - - - f - - . f . - - tNLO - - - - - - -.... 1

-lOSTB

-AOSTB

tLSH~

tLSS~

00-07

SOURCE
VALID

VLSI TECHNOLOGY, INC.
VL16160

FIGURE 5. TYPICAL APPUCATION

SHIFT REG
LS
ADDR DECODE
OR
STATE MACHINE

_11

_ T

.....
.

.......
..
.......

VL16160

1I
T

ADDRESS BUS

I I

\.. .....

~....r.;:

DISPLAY
MEMORY

r--

6845CRTC

•

SYSTEM
MEMORY

(' RASTER
OPERATION
abcdefghijklmn

RALU

DATA RUS

TI CPU

VLSI TECHNOLOGY, INC
VL 16C450 • VL82C50A • VL82C50
ASYNCHRONOUS COMMUNICATIONS ELEMENT

FEATURES

DESCRIPTIONS

• Full double buffering

The VL 16C450 is an asynchronous
communications element (ACE) that is
functionally equivalent to the
VL82C50A. but is an improved specification version of that part. The
improved specifications provide
ensured compatibility with state-of-theart CPUs.

the CPU. The complete status of the
ACE can be read at any time during
functional operation by the CPU. The
information obtained includes the type
and condition of the transfer operations
being performed. and error conditions
involving parity. overrun. framing. or
break interrupt.

The VL 16C450. VL82C50A. and
VL82C50 ACEs serve as serial data
input/output interface in microcomputer
systems. They perform serial-toparallel conversion on data characters
received from peripheral devices or
modems. and parallel-to-serial conversion on data characters transmitted by

A programmable baud rate generation
is included that can divide the timing
reference clock inftut by a divisor
between 1 and (2 6_ 1).

• Independent control of transmit.
receive. line status and data set
interrupts
• Modem control signals include -CTS.
-RTS. -DSR. -DTR. -RI and -OCD
• Programmable serial interface
characteristics :
- 5-. 6-. 7- or 8-bit characters
- Even-. odd-. or no-parity bit
generation and detection
- 1-. 1 1/2- or 2-stop bit generation
- Baud rate generation (dc to 56K
baud)
• Full status reporting capabilities

The VLSI family of ACEs is available
packaged in plastic leaded chip carrier
as well as a plastic and ceramic DIP.

• Three-state TTL drive capabilities for
bidirectional data bus and control bus
-OeD·

PIN DIAGRAMS
VL16C450
VL82CSOA
VL82C50
DO
D1
D2
D3
D4
D5
D6
D7
RCLK

SIN
SOUT
CSO
CS1

-CS2
-BAUDOUT
XTAL1

XTAL2
-DOSTR
DOSTR
VSS

VL16C4S0
VL82C50A
VL82CSO
VCC

-AI
-DCD"
-DSR

-OUTl
-DTR

07
RClK
SIN
N.C.
SOUT

37
36
35
34

33
32
31

CS1
-CS2
-BAUDOUT

cso

-CTS

MR
-Oun
-OTA
-RTS
-OUT2
N.C.
INTRPT
N.C
AO
A1

-ATS
-OUT2
INTRPT
N.C.

XTAl2

·On the VL82C50. Pin 38 (Pin 42 on
the PLCC package) is also called
-RLSD.

CSOUT

-OISTR

DOSTR

A1
A2
-ADS
CSOUT
DDIS
DISTR
-DISTR

N.C.

-OOSTR

OISTR

ORDER INFORMATION
Part
Number

Clock
Frequency

Package

VL 16C450-PC
VL 16C450-CC
VL 16C450-OC

3.1 MHz

Plastic DIP
Ceramic DIP
Plastic Leaded Chip Carrier (PLCC)

VL82C50A-PC
VL82C50A-CC
VL82C50A-OC

3.1 MHz

Plastic DIP
Ceramic DIP
Plastic Leaded Chip Carrier (PLCC)

VL82C50-PC
VL82C50-CC
VL82C50-QC

3.1 MHz

Plastic DIP
Ceramic DIP
Plastic Leaded Chip Carrier (PLCC)

Note: Operating temperature range is O°C to + 70°C.

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

Do-D7

SIN

RCLK

A2
-BAUOOUT

csa
CSl
-CS2
-ADS
MR

SELECT
&
CONTROL
LOGIC
SOUT

-RTS
-CTS
DDIS
-DTR
-DSR
XTAL1
-DCD
XTAl2

(40)
POWER

(20)
SUPPLY

..
•

-RI
-CUTl

+5V
-CUT2
GND

(30)
INTRPT

Note: A pplca
I, ble p'ln numbers (DIP) are included within parentheses,

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number (DIP)

Signal
Type

Signal
Description

00-07

1-8

1/0

Data Bits 0 through 7 - The Data Bus provides eight, three-state 1/0 lines
for the transfer of data, control and status information between the ACE
and the CPU. These lines are normally in a high-impedance state except
during read operations. DO is the least significant bit (LSB) and is the first
serial data bit to be received or transmitted.

RCLK

Receive Clock Input - The external clock input to the UART baud rate
divisor.

SIN

Serial Data Input - The serial data input moves information from the
communication line or modem to the ACE receiver circuits. A mark (1) is
high, and a space (0) is low. Data on serial data input is disabled when
operating in the Loop Mode.

SOUT

CSO, CS1,
CS2

12-14

-BAUDOUT

XTAL1

Crystal Input Pin 1 - Input for external timing reference input or pin of
crystal (See Basic Configuration).

XTAL2

Crystal Input Pin 2 - Input for pin of crystal (See Basic Configuration).

-DOSTR

Input/Output Write Strobe - This is an active low input which causes data
from the data bus (00-07) to be input to the UART.

DOSTR

Input/Output Write Strobe - Same as -DOSTR, but uses an active high
input.

Serial Data Output - This line is the serial data output from the UARTs
transmitter circuitry. A mark (1) is a logic "one" (high) and space (0) is a
logic "zero" (low). SOUT is held in the mark condition when the transmitter
is disabled, Reset is true, the Transmitter Register is empty, or when in the
Loop Mode.
Chip Selects - The Chip Select inputs act as an enable for the device.
When --CS2 is low and CSO and CS1 are both high, the chip is selected.

Baud Rate Output - This output signal for the transmitter section is equal to
the internal reference frequency, divided by the selected divisor.

VSS

Ground (0 V).

-DISTR

Input/Output Read Strobe - This is an active low input which causes the
serial channel to output data to the data bus (DBO-DB7).

DISTR

Input/Output Read Strobe - Same as -DISTR, but uses an active high
input.

DDiS

Driver Disable - This pin goes low whenever the microprocessor is reading
data from the ACE. This signal may be used to disable an external transceiver.

CSOUT

Chip Select Out - A high on this pin indicates that the chip has been
selected by the chip select input pins.

-ADS

Address Strobe Input - When this pin is low, the state of the Register Select
and Chip Select pins is latched internally.

AO-A2

28-26

Address Lines AO-A2 - The address lines select the internal registers
during CPU bus operations.

INTRPT

No Connection.

Interrupt Output - This pin goes high (when enabled by the Interrupt
Enable Register) whenever a Receiver Error Flag, Received Data Available, Transmitter Holding Register Empty, or Modem Status condition is
detected.

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number (DIP)

Signal
Type

Signal
Description

-OUT2

Output 2 - User defined output that can be set to an active low by programming bit 3 of the Modem Control Register to a high level.

-RTS

Request to Send - The -RTS signal is an output on the UART used to
enable the modem. The -RTS pin is set low by writing a logic 1 to MCR bit
1 of the UART's Modem Control Register. The -RTS pin is reset high by
Reset. A low on the -RTS pin indicates to the ACE that the UART has
data ready to transmit.

-DTR

Data Terminal Ready - The DTR pin can be set (low) by writing a logic 1 to
MCR, Modem Control Register bit 0 of the UART. This signal is cleared
(high) by writing a logic 0 to the DTR bit (MCR) or whenever a reset occurs.
When active (low), the DTR pin indicates to the ACE that the UART is
ready to receive data.

-OUT1

Output 1 - User defined output that can be set to an active low by programming bit 2 of the Modem Control Register to a high level.

Master Reset - When high, the reset input forces the ACE into an idle
mode in which all data activities are suspended. The Modem Control
Register (MCR) along with its output, is cleared. The Line Status Register
(lSR) is cleared except for the THRE and TEMT bits, which are set. All
functions of the device remain in an idle state until programmed to resume
activities.

-CTS

Clear to Send - The logical state of the -CTS pin is reflected in the CTS bit
of the (MSR) Modem Status Register [CTS is bit 4 of the MSR, written
MSR(4)] of the UART. A change of state of the -CTS pin, since the
previous reading of the MSR causes the setting of DCTS in the Modem
Status Register. When the -CTS pin is low, the modem is indicating that
data on SOUTcan be transmitted.

-DSR

Data Set Ready - The logical state of the -DSR pin is reflected in MSR(5)
of the Modem Status Register. DDSR MSR(1) indicates whether the -DSR
pin has changed state since the previous reading of the MSR. When the
-DSR pin is low, the modem is indicating that it is ready to exchange data
with the UART.

-DCD (-RLSD)

Data Carrier Detect (Receive Line Signal Detect) - When low, the -DCD
(-RlSD) indicates that the data carrier has been detected by the modem or
data set. -DCD (-RlSD) is a modem input whose condition can be tested
by the CPU by reading MSR(7) (DCD or RlSD) of the Modem Status
Register. MSR(3) (DDCD or DRlSD) of the Modem Status Register
indicates whether the -DCD (-RlSD) input has changed since the previous reading of the MSR. -DCD (-RlSD) has no effect on the receiver. If
the -DCD (-AlSD) changes state with the modem status interrupt enabled, an interrupt occurs.

-RI

Ring Indicator Input - When low, -RI indicates that a telephone ringing
signal has been received by the modem or data set. The -RI signal is a
modem control input whose condition is tested bOy reading MSR(6) (RI) of
the UART. The Modem Status Register output TERI MSR(2) indicates
whether the RI input has changed from high to low since the previous
reading of the MSR. If the interrupt is enabled IER(3) == 1 and -RI changes
from a high to low, an interrupt is generated.

VCC

Power Supply - The power supply requirement is 5 V ±S%.

VLSI TECHNOLOGY, INC
VL 16C450 • VL82C50A • VL82C50

REGISTERS
Three types of internal registers are used
in the serial channel of each ACE. They
are used in the operation of the device,
and are the control, status, and data
registers. The control registers are the
Bit Rate Select Register Dll (Divisor
latch lSB) and DlM (Divisor latch
MSB), Line Control Register, Interrupt
Enable Register, and the Modem Control
registers, while the status registers are
the Line Status Registers and the
Modem Status Register. The data
registers are the Receiver Buffer
Register and the Transmitter Holding
Register. The Address, Read, and Write
inputs are used in conjunction with the
Divisor latch Access Bit in the Line
Control Register [lCR(7)] to select the
register to be written or read (see Table
1). Individual bits within these registers
are referred to by the register mnemonic
and the bit number in parenthesis. As
an example, lCR(7) refers to Line
Control Register Bit 7.
The Transmitter Buffer Register and
Receiver Buffer Register are data
registers that hold from five to eight bits
of data. If less than eight data bits are
transmitted, data is right justified to the

lSB. Bit 0 of a data word is always the
first serial data bit received and transmitted. The ACE data registers are doublebuffered so that read and write operations may be performed when the UART
is performing the parallel-to-serial or
serial-to-parallel conversion.
The format of the data character is
controlled by the Line Control Register.
The contents of the lCR may be read,
eliminating the need for separate storage
of the line characteristics in system
memory. The contents of the lCR are
described below:
lCR (0) Word length Select Bit 0
(WlSO)
lCR (1) Word length Select Bit 1
(WlS1)
lCR (2) Stop Bit Select (STB)
lCR (3) Parity Enable (PEN)
lCR (4) Even Parity Select (EPS)
lCR (5) Stick Parity
lCR (G) Set Break
lCR (7) Divisor latch Access Bit (DLAB)
lCR(O) and lCR(1) word length select
bit 1: The number of bits in each serial
character is programmed as shown in
Table 2.

TABLE 1. SERIAL CHANNEL INTERNAL REGISTERS

DLAB A2

RBR

Receiver Buffer Register (read only)

THR

Transmitter Holding Register (write only)

IER

Interrupt Enable Register

IIR

Interrupt Identification Register (read only)

lCR

Line Control Register

MCR

Modem Control Register

lSR

Line Status Register

MSR

Modem Status Register

Mnemonic

SCR

Scratch Register

Dll

Divisor latch (lSB)

DlM

Divisor latch (MSB)

= "Don't Care"

0= logic low

TABLE 2. WORD LENGTH
SELECT
lCR(1)

LCR(O)

0
1
1

1
0

Word Length
5 Bits
G Bits
7 Bits
8 Bits

lCR(2) Stop Bit Select: lCR(2) specifies the number of stop bits in each
transmitted character. If lCR(2) is a
logic 1 when a 5-bit word length is
selected, 1.S stop bits are generated. If
lCR(2) is a logic 1 when either a G-, 7-,
or a-bit word length is selected, two stop
bits are generated. The receiver checks
for two stop bits if programmed to do so.
lCR(3) Parity Enable: When lCR(3) is
high, a parity bit between the last data
word bit and stop bit is generated and
checked.
lCR(4) Even Parity Select: When parity
is enabled [lCR(3) = 1], lCR(4)-O
selects odd parity, and lCR(4) = 1
selects even parity.
lCR(S) Stick Parity: When parity is
enabled [lCR(3}-1], ClR(S) ... 1 causes
the transmission and reception of a
parity bit to be in the opposite state from
that indicated by lCR(4). This allows
forced parity to a known state and the
receiver to check the parity bit in a
known state.
lCR(G) Break Control: When lCR(G) is
set to a logic "1", the serial output
(SOUT) is forced to the spacing (logic 0)
state. The break is disabled by setting
lCR(G) to a logic "0". The Break Control
bit acts only on SOUT and does not
effect on the transmitter logic. Break
Control enables the CPU to alert a
terminal in a computer communications
system. If the following sequence is
used, no invalid characters will be transmitted because of the break.
1. load all lOons pad character in
response to THRE.

1 = logic High

2. Set the break in response to the next
THRE.

Note: The serial channel is accessed when -eSO is low.

3. Wait for the transmitter to be idle
(TEMT = 1), then clear the break
when the normal transmission has to
be restored.

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

FIGURE 1. LINE CONTROL REGISTER

o
Word
1----' Length
Select

0 1
1 0
1 1

'--_ _ _ _~Stop
0
Bit Select 1

5 Data Bits
6 Data Bits
7 Data Bits
8 Data Bits

= 1 Stop Bit
= 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected

'--_ _ _ _ _ _~Parity
Enable
1..-_ _ _ _ _ _ _ _- '

Even
Parity

o = Parity Disabled
1 = Parity Enabled
o = Odd Parity
1 = Even Parity

Select

L..-------------4~ Stick

Parity

1..-_ _ _ _ _ _ _ _ _ _ _ _"

o = Stick Parity Disabled
1 = Stick Parity Enabled

Break
Control

o = Break Disabled
1 = Break Enabled

Divisor
Latch

o = Access Receiver Buffer
1 = Access Divisor Latches

I..-----------------~Access

Bit
LCR(7) Divisor Latch Access Bit (DLAB);
LCR(7) must be set high (logic "1") to
access the Divisor Latches DLL and
DLM of the Baud Rate Generator during
a read or write operation. LCR(7) must
be input low to access the Receiver
Buffer, the Transmitter Holding, or the
Interrupt Enable Registers.
The Line Status Register (LSR) is a
single register that provides status
indications. The LSR is usually the first
register read by the CPU to determine
the cause of an interrupt or to poll the
status the serial channel of the ACE.
Three error flags OE, FE, and PE
provide the status of any error conditions
detected in the receiver circuitry. During
reception of the stop bits, the error flags
are set high by an error condition. The
error flags are not reset by the absence
of an error condition in the next received
character. The flags reflect the last
character only if no overrun occurred.
The Overrun Error character in the

Receiver Buffer Register has been
overwritten by a character from the
Receiver Shift Register before being
read by the CPU. The character is
thereby lost. Framing Error (FE)
indicates that the last character received
contained incorrect (low) stop bits. This
is caused by the absence of the required
stop bit or by a stop bit too short to be
detected. Parity Error (PE) indicates that
the last character received had a parity
error based on the programmed and
calculated parity of the received character.
The Break Interrupt (BI) status bit
indicates that the last character received
was a break character. A break character is an invalid data character. However, it is an entire character, including
parity and stop bits.
The Transmitter Holding Register Empty
(THRE) bit indicates that the THR
register is empty and may receive
another character. The Transmission

Shift Register Empty (TEMT) bit indicates that the Transmitter Shift Register
is empty, and the serial channel has
completed transmission of the last
character to be sent. If the interrupt is
enabled [IER(1 )]. an active THRE
causes an interrupt (INTRPT).
The Data Ready (DR) bit indicates that
the RBR has been loaded with a
received character (including Break) and
that the CPU may access this data.
Reading the LSR clears LSR(1 )-LSR(4).
(OE. PE, FE. and BI.)
The Line Status Register shown in Table
3 is described below:
LSR(O) Data Ready (DR): Data Ready is
set high when an incoming character has
been received and transferred into the
Receiver Buffer Register. LSR(O) is
reset low by a CPU read of the data in
the Receiver Buffer Register.
LSR(1) Overrun Error (OE): Overrun
Error indicates that data in the Receiver

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

TABLE 3. LINE STATUS REGISTER BITS
reset low by a CPU read of the LSR.
LSR BITS

Logic 1

Logic 0

LSR(O) Data Ready (DR)

Ready

Not Ready

LSR(1) Overrun Error (OE)

Error

No Error

LSR(2) Parity Error (PE)

Error

No Error

LSR(3) Framing Error (FE)

Error

No Error

LSR(4) Break Interrupt (BI)

Break

No Break

LSR(5) Transmitter Holding Register Empty (THRE)

Empty

Not Empty

LSR(6) Transmitter Empty (TEMT)

Empty

Not Empty

LSR(7) Not Used
Buffer Register was not read by the CPU
before the next character was transferred into the Receiver Buffer Register.
overwriting the previous character. The
OE indicator is reset whenever the CPU
reads the contents of the Line Status
Register.
LSR(2) Parity Error (PE): Parity Error
indicates that the received data character does not have the correct even or
odd parity. as selected by the Even
Parity Select bit LCR(4). The PE bit is
set high upon detection of a parity error.
and is reset low when the CPU reads the
contents of the LSR.
LSR(3) Framing Error (FE): Framing
Error indicates that the received character did not have a valid stop bit. LSR(3)
is set high when the stop bit following the
last data bit or parity bit is detected as a
zero bit (spacing level). The FE indicator
is reset low when the CPU reads the
contents of the LSR.
LSR(4) Break Interrupt (BI): Break
Interrupt is set high when the received
data input is held in the spacing (logic 0)
state for longer than a full word transmission time (start bit + data bits + parity +
stop bits). The BI indicator is reset when
the CPU reads the contents of the Line
Status Register.
LSR(l) - LSR(4) are the error conditions
that produce a Receiver Line Status
interrupt (priority 1 interrupt in the
Interrupt Identification Register (IIR»
when any of the conditions are detected.
This interrupt is enabled by setting
IER(2) .. 1 in the Interrupt Enable Register.

LSR(5) Transmitter Holding Register
Empty (THRE): THRE indicates that the
ACE is ready to accept a new character
for transmission. The THRE bit is set
high when a character is transferred from
the Transmitter Holding Register into the
Transmitter Shift Register. LSR(5) is
reset low by the loading the Transmitter
Holding Register by the CPU. LSR(5) is
reset low by the loading of the Transmitter Holding Register by the CPU. LSR(5)
is not reset by a CPU read of the LSR.
When the THRE interrupt is enabled
IER(l). THRE causes a priority 3
interrupt in the IIR. If THRE is the
interrupt source indicated in IIR. INTRPT
is cleared by a read of the IIR.
LSR(6) Transmitter Empty (TEMT):
TEMT is set high when the Transmitter
Holding Register (THR) and the Transmitter Shift Register (TSR) are both
empty. LSR(6) is reset low when a
character is loaded into the THR and
remains low until the character is
transferred out of SOUT. TEMT is not

LSR(7): This bit is always O.
The Modem Control Register (MCR)
controls the interface with the modem or
data set as described in Table 4 and
Figure 2. MCR can be written and read.
The -RTS and -OTR outputs are directly
controlled by their control bits in this
register. A high input asserts a low (true)
at the output pins. MCR Bits O. 1. 3. and
4 are shown below:
MCR(O): When MCR(O) is set high. the
-OTR output is forced low. When
MCR(O) is reset low. the -OTR output is
forced high. The -OTR output of the
serial channel may be input into an
inverting line driver in order to obtain the
proper polarity input at the modem or
data set.
MCR(l): When MCR(l) is set high. the
RTS output is forced low. When MCR(l)
is reset low. the -RTS output is forced
high.
MCR(2): The -RTS output of the serial
channel may be input into an inverting
line driver in order to obtain the proper
polarity input at the modem or data set.
MCR(3): When MCR(3) is set high. the
-OUT1 or -OUT2 output is forced high.
MCR(4): MCR(4) provides a local
loopback feature for diagnostic testing of
the channel. When MCR(4) is set high.
Serial Output (SOUT) is set to the
marking (logic "1") state. and the receiver
data input Serial Input (SIN) is disconnected. The output of the Transmitter
Shift Register is looped back into the
Receiver Shift Register input. The three

TABLE 4. MODEM CONTROL REGISTER BITS
Logic 1

MCRBits

Logic 0

MCR(O) Data Terminal Ready (OTR)

-OTR Output Low

-OTR Output High

MCR(1) Request to Send (RTS)

-RTS Output Low

-RTS Output High

MCR(2) OUT1

-OUT1 Output Low

-OUT1 Output High

MCR(3)OUT2

-OUT2 Output Low

-OUT2 Output High

MCR(4) LOOP

Loop Enabled

Loop Disabled

MCR(5) 0
MCR(6) 0
MCR(7) 0

VLSI TECHNOLOGY, INC
VL 16C450 • VL82C50A • VL82C50

FIGURE 2. MODEM CONTROL REGISTER

'--__+
'-----~...

L...-_ _ _ _ _ _, .

Data
Terminal
Ready

0 = -OTR Output High (Inactive)
1 = -OTR Output Low (Active)

Request
To Send

0 = -RTS Output High (Inactive)
1 = -RTS Output Low (Active)

No Connection

INT

0 = INT Disabled
1 = INT Enabled

' - - - - - - - - -... LOOP

0 =
1 =

LOOP Disabled
LOOP Enabled

"'-------------+ Bits are Set to Logic "0".
modem control inputs (-CTS, -OSR, and
-RI) are disconnected. The modem
control outputs (-DTR and -RTS) are
internally connected to the four modem
control inputs. The modem control
output pins are forced to their inactive
state (high).

bits in the IIR register, and an interrupt
(INTRPT) is generated. The MSR is a
priority 4 interrupt. The contents of the
Modem Status Register are described in
Table 5. Note that the state (high or low)
of the status bits are inverted versions of
the actual input pins.

In the diagnostic mode, data transmitted
is immediately received. This allows the
processor to verify the transmit and
receive data paths of the selected serial
channel. Bits MCR(5) - MCR(7) are
permanently set to logic o.

MSR(O) Delta Clear to Send (DCTS):
DCTS displays that the -CTS input to
the serial channel has changed state
since it was read last by the CPU.

The MSR provides the CPU with status
of the modem input lines from the
modem or peripheral devices. The MSR
allows the CPU to read the serial
channel modem signal inputs by
accessing the data bus interface of the
ACE in addition to the current status
information, four bits of the MSR indicate
whether the modem inputs have
changed since the last reading of the
MSR. The delta status bits are set high
when a control input from the modem
changes state, and reset low when the
CPU reads the MSR.
The modem input lines for the channel
are -CTS, -DSR, -RI, and -RLSD.
MSR(4) - MSR(7) are status indications
of these lines. The status indications
follow the status of the input lines. If the
modem status interrupt in the Interrupt
Enable Register is enabled [IER(3)], a
change of state in a modem input signals
will be reflected by the modem status

MSR(1) Delta Data Set Ready (DDSR):
DDSR indicates that the -DSR input to
the serial channel has changed state
since the last time it was read by the
CPU.
MSR(2) Trailing Edge of Ring Indicator
(TERI): TERI indicates that the -RI input
to the serial channel has changed state
from high to low since the last time it was
read by the CPU. Low to high transitions
on -RI do not activate TERI.

MSR(3) Delta Data Carrier Detect
(DRSLD): DRSLD indicates that the
-RSLD input to the serial channel has
changed state since the last time it was
read by the CPU.
MSR(4) Clear to Send (CTS): Clear to
Send (CTS) is the status of the -CTS
input from the modem indicating to the
serial channel that the modem is ready
to receive data from the serial channel's
transmitter output (SOUT). If the serial
channel is in loop mode[(MSR(4) = 1],
MSR(4) is equivalent to -RTS in the
MCR.
MSR(5) Data Set Ready (DSR): Data
Set Ready (DSR) is a status of the -DSR
input from the modem to the serial
channel which indicates that the modem
is ready to provide received data to the
serial channel receiver circuitry. If the
channel is in the loop mode [MCR(4) =
1], MSR(5) is equivalent to the DTR in
the MCR.

TABLE 5. MODEM STATUS REGISTER BITS
MSR Bit

Mnemonic

MSR(O)
MSR(1)
MSR(2)
MSR(3)

DCTS
DDSR
TERI
DRLSD
-CTS
-DSR

MSR(4)
MSR(5)
MSR(6)
MSR(7)

-RI
-RLSD

Description
Delta Clear To Send
Delta Data Set Ready
Trailing Edge of Ring Indicator
Delta Data Carrier Detect
Clear To Send
Data Set Ready
Ring Indicator
Receiver Line Signal Detect

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

MSR(6) Ring Indicator (RI): Indicates
the status of the RI input (pin 39). If the
channel is in the loop mode (MCR(4) =
1), (6) is not connected in the MCR.
MSR(7) Receive Line Signal Detect
(RLSD): Receive Line Signal Detect
indicates the status of the Receive Line
Signal Detect (-RLSD) input. If the
channel is in the loop mode (MCR(4)-1),
MSR(4) is equivalent to OUT2 of the
MCR.
The modem status inputs (-RI, -RLSD,
-DSR, and -CTS) reflect the modem
input lines with any change of status.
Reading the MSR register will clear the
delta modem status indications but has
no effect on the status bits. The status
bits reflect the state of the input pins
regardless of the mask control signals. If
a DCTS, DDSR, TERI, or DRLSD are
true, and a state change occurs during a
read operation (-DISTR), the state
change is not indicated in the MSR. If
DCTS, DDSR, TERI, or DRLSD are
false, and a state change occurs during
a read operation, the state change is
indicated after the read operation.
For LSR and MSR, the setting of status
bits is inhibited during status register
read -DISTR operations. If a status
condition is generated during a read
-DISTR operation, the status bit is not
set until the trailing edge of the read
-DISTR.
If a status bit is set during a read
-DISTR operation, and the same status
condition occurs, that status bit will be
cleared at the trailing edge of the read
-DISTR instead of being set again.

words of less than a bits, the data is right
justified to the least significant bit LSB =
Data Bit 0 [RBR(O)]. Data Bit 0 of a data
word [RBR(O)] is the first data bit reo
ceived. The unused bits in a character
less than a bits are output low to the
parallel output by the serial channel.
Received data at the SIN input pin is
shifted into the Receiver Shift Register
by the 16X clock provided at the CLK
input. This clock is synchronized to the
incoming data based on the position of
the start bit. When a complete character
is shifted into the Receiver Shift Regis·
ter, the assembled data bits are parallel
loaded into the Receiver Buffer Register.
The DR flag in the LSR register is set.
Double buffering of the received data
permits continuous reception of data
without losing received data. While the
Receiver Shift Register is shifting a new
character into the serial channel, the
Receiver Buffer Register is holding a
previously received character for the
CPU to read. Failure to read the data in
the RBR before complete reception of
the next character result in the low of the
data in the Receiver Register. The OE
flag in the LSR register indicates the
overrun condition.
RBR Bits 0 through 7:

THR(O)
THR(1)
THR(2)
THR(3)
THR(4)
THR(5)
THR(6)
THR(7)

Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7

Scratchpad Register is an 8-bit Read/
Write register that has no effect on either
channel in the ACE. It is intended to be
used by the programmer to hold data
temporarily.
SCR Bits 0 through 7:
SCR~)

D~aBhO

SCR(1)
SCR(2)

Data Bit 1
Data Bit 2

SCR~)
SCR~)

D~aBh3
D~aBh4

SCR~)

D~aBh5

SCR~)

D~aBh6

SCR(7)

Data Bit 7

INTERRUPTS
The Interrupt Identification Register (IIR)
in the serial channel of the ACE has
interrupt capability of interfacing to
current microprocessors. In order to
minimize software overhead during data
character transfers, the serial channel
prioritizes interrupts into four levels. The
four levels of interrupt conditions are as
follows:

RBR~)

D~aBhO

RBR(1)
RBR(2)

Data Bit 1
Data Bit 2

1. Receiver Line Status (priority 1)

RBR~)

D~aBh3

RBR~)

D~aBh4

RBR~)

D~aBh5

RBR(6)
RBR(7)

Data Bit 6
Data Bit 7

The ACE serial channel contains a
programmable Baud Rate Generator
(BRG) that divides the clock (DC to 3.1
MHz) by any divisor from 1 to 216•1 (see
also BRG description). The output
frequency of the Baud Generator is 16X
the data rate [divisor # = clock + (baud
rate x 16)]. Two a·bit divisor latch
registers store the divisor in a 16·bit
binary format. These Divisor Latch
registers must be loaded during initializa·
tion. Upon loading either of the Divisor
Latches, a 16·bit baud counter is
immediately loaded. This prevents long
counts on initial load.

The Transmitter Holding Register (THR)
holds parallel data from the data bus
(DO·D7) until the Transmitter Shift
Register is empty and ready to accept a
new character for transmission. The
transmitter and receiver word length and
number of stop bits are the same. If the
character is less than eight bits, unused
bits at the microprocessor data bus are
ignored by the transmitter.

The receiver circuitry in the serial
channel of the ACE is programmable for
5, 6, 7, or a data bits per character. For

THR Bits 0 through 7:

Data Bit 0 (THR(O)) is the first serial data
bit transmitted. The THRE flag (LSR(5))
reflect the status of the THR. The TEMT
flag (LSR(5)) indicates if both the THR
and TSR are empty.

Received Data Ready (priority 2)

3. Transmitter Holding Register Empty
(priority 3)
4. Modem Status (priority 4)
Information indicating that a prioritized
interrupt is pending and the type of
interrupt is stored in the Interrupt
Identification Register (IIR). When
addressed during chip select time, the
IIR indicates the highest priority interrupt
pending. No other interrupts are
acknowledged until the interrupt is
serviced by the CPU. The contents of
the IlR are indicated in Table 6 and are
described below:
IIR(O): IIR(O) can be used in either a
hard-wired prioritized or polled environment to indicate whether an interrupt is
pending. When IIR(O) is low, an interrupt
is pending, and IIR contents may be
used as a pointer to the appropriate

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

TABLE 6. INTERRUPT IDENTIFICATION REGISTER
Interrupt Set And Reset Functions

Interrupt Identification
Bit 2

Bit 1

Bit 0

Priority
Level

Interrupt
Flag

Interrupt
Source

None

Interrupt
Reset Control

First

Receiver
Line Status

OE, PE
FE, or BI

LSR Read

Second

Received Data
Available

RBR Read

Third

THRE

IIR Read if THRE is the
Interrupt Source or THR Write

Fourth

Modem Status

-CTS,-DSR
-RI,-RSLD

MSR Read

X = Not Defined.

VLSI TECHNOLOGY, INC
VL 16C450 • VL82C50A • VL82C50

TABLE 7. SERIAL CHANNEL ACCESSIBLE REGISTERS
Register Bit Number
Register
Mnemonic

Blt7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RBR
(Read Only)

Data
Bit 7
(MSB)

Data
Bit 6

Data
Bit 5

Data
Bit 4

Data
Bit3

Data
Bit 2

Data
Bit 1

Data
Bit 0
(LSB)*

THR
(Write Only)

Data
Bit 7

Data
Bit 6

Data
Bit 5

Data
Bit 4

Data
Bit 3

Data
Bit 2

Data
Bit 1

Data
BitO

DLL

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DLM

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

BitS

IER

(EDSSI)
Enable
Modem
Status
Interrupt

(ELSI)
Enable
Receiver
Line
Status
Interrupt

(ETBEI)
Enable
Transmitter
Holding
Register
Empty
Interrupt

(ERBFI)
Enable
Received
Data
Available
Interrupt

IIR
(Read Only)

Interrupt

Bit (1)

Bit (0)

"0" 1F
Interrupt
Pending

LCR

(DLAB)
Divisor
Latch
Access
Bit

Set
Break

Stick
Parity

(EPS)
Even
Parity
Select

(PEN)
Parity
Enable

(STB)
Number
of Stop
Bits

(WLSB1)
Word
Length
Select
Bit 1

(WLSBO)
Word
Length
Select
BitO

MCR

Loop

Out2

Out 1

(RTS)
Request
To
Send

(DTR)
Data
Terminal
Ready

LSR

(TEMT)
Transmitter
Empty

(THRE)
Transmitter
Holding
Register
Empty

(BI)
Break
Interrupt

(FE)
Framing
Error

(PE)
Parity
Error

(OE)
Overrun
Error

(DR)
Data
Ready

MSR

(DCD)
Data
Carrier
Detect

(RI)
Ring
Indicator

(DSR)
Data
Ready
Set

(CTS)
Clear
to
Send

(DRSLD)
Delta
Receive
Line Signal
Detect

(TERI)
Trailing
Edge
Ring
Indicator

(DDSR)
Delta
Data
Set
Ready

(DCTS)
Delta
Clear
to
Send

SCR

Bit 7

Bit 6

Bit5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

*LSB Data Bit 0 is the first bit transmitted or received.

"VLSI TECHNOLOGY. INC.
VL 16C450 • VL82C50A • VL82C50
interrupt service routine. When IIR(O) is
high. no interrupt is pending.
IIR(1) and IIR(2) are used to identify the
highest priority interrupt pending as
indicated in Table 6.
IIR(3) -IIR(7): These five bits of the IIR
are logic O.
The Interrupt Enable Register (IER) is a
Write register used to independently
enable the four serial channel interrupts
which activate the interrupt (INTRPT)
output. All interrupts are disabled by
resetting IER(O) - IER(3) of the Interrupt
Enable Register. Interrupts are enabled
by setting the appropriate bits of the IER
high. Disabling the interrupt system
inhibits the Interrupt Identification
Register and the active (high) INTRPT
output. All other system functions
operate in their normal manner. including
the setting of the Line Status and Modem
Status Registers. The contents of the
Interrupt Enable Register is described in
Table 7 and below:
IER(O): When programmed high IER(O)
= logic 1). IER(1) enables the Received
Data Available interrupt.
IER(1): When programmed high (IER(1)
... logic 1). IER(1) enables the Transmitter Holding Register Empty interrupt.
IER(2): When programmed high (IER(2)
.. logic 1). IER(2) enables the Receiver
Line Status interrupt.
IER(3): When programmed high (IER(3)
.. logic 1). IER(3) enables the Modem
Status Interrupt.
IER(4) - IER(7): These four bits of the
IER are logic O.
TRANSMlnER
The serial transmitter section consists of
a Transmitter Holding Register (THR).
Transmitter Shift Register (TSR). and
associated oontrollogic. The Transmitter Holding Register Empty (THRE) and
Transmitter Shift Register Empty (TEMT)
are two bits in the Line Status Register
which indicate the status of THR and
TSR. To transmit a 5- to 8-bit word. the
word is written through DO-D7 to the
THR. The microprocessor should
perform a write operation only if THRE is
high. The THRE is set high when the
word is automatically transferred from
the THR to the TSR during the transmission of the start bit.

When the transmitter is idle. THRE and
TEMT are high. The first word written
causes THRE to be reset to O. After the
transfer. THRE returns high. TEMT
remains low for at least the duration of
the transmission of the data word. If a
second character is transmitted to the
THR. the THRE is reset low. Since the
data word cannot be transferred from the
THR to the TSR until the TSR is empty.
THRE remains low until the TSR has
completed sending the word. When the
last word has been transmitted out of the
TSR. TEMT is set high. THRE is set
high one THR to TSR transfer time later.
RECEIVER
Serial asynchronous data is input into
the SIN pin. The idle state of the line
providing the input into SIN is high. A
start bit detect circuit continually
searches for a high to low transition from
the idle state. When the transition is
detected. a counter is reset. and counts
the 16X clock to 71/2. which is the
center of the start bit. The start bit is
valid if the SIN is still low at the mid-bit
sample of the start bit. Verifying the start
bit prevents the receiver from assembling a false data character due to a low
going noise spike on the SIN input.
The Line Control Register determines
the number of data bits in a character
(lCR(O). lCR(1 number of stop bits
lCR(2). if parity is used lCR(3). and the
polarity of parity lCR(4). Status for the
receiver is provided in the Line Status
Register to the Receiver Buffer Register..,
the Data Received indication in LSR(O) is
set high. The CPU reads the Receiver
Buffer Register through DO-07. This
read resets LSR(O). If 00-07 are not
read prior to a new character transfer
from the RSR to the RBR. the overrun
error status indication is set in LSR(1).
The parity check tests for even or odd
parity on the parity bit. which precedes
the first stop bit. If there is a parity error.
the parity error is set in lSR(2). There is
circuitry which tests whether the stop bit
is high. If it is not. a framing error
indication is generated in lSR(3).

».

The center of the start bit is defined as
clock count 7 112. If the data into SIN is
symmetrical square wave. the center of
the data cells will occur within ±3.12S%
of the actual center. providing an error
margin of 46.875%. The start bit can

begin as much as one 16X clock cycle
prior to being detected.
BAUD RATE GENERATOR (BRG)
The BRG generates the clocking for the
UART function. providing standard ANSI!
cCln bit rates. The oscillator driving
the BRG is provided by an external clock
into ClK.
The data rate is determined by the
Divisor latch registers DlL and DlM
and the external frequency. The bit rate
is selected by programming the two
divisor latches. Divisor latch Most
Significant Byte and Divisor latch least
Significant Byte. Setting Dll = 1 and
DlM ... 0 selects the divisor to divide by 1
(divide by 1 gives maximum baud rate
for a given input frequency at the ClK
input).
The BRG can use any of three different
popular frequencies to provide standard
baud rates. These frequencies are
1.8432 MHz, 2.4576 MHz, and 3.072
MHz. With these frequencies. standard
bit rates from 50 to 38.Sk bps are
available. Tables 8. 9. and 10 illustrate
the divisors needed to obtain standard
rates using these three crystal frequencies .
MASTER RESET
After power uP. the ACE MR input
should be held high for one microsecond
to reset the ACE circuits to an idle mode
until initialization. A high on MR causes
the following:
1. Initializes the transmitter and receiver
internal clock counters.
2. Clears the Line Status Register
(lSR). except for Transmitter Shift
Register Empty (TEMT) and Transmit
Holding Register Empty (THRE).
which are set. The Modem Control
Register (MCR) is also cleared. All of
the discrete lines. memory elements
and miscellaneous logic associated
with these register bits are also
cleared or turned off. The Line
Control Register (lCR). Divisor
latches. Receiver Buffer Register.
Transmitter Buffer Register are not
effected.
Following removal of the reset condition
(Reset low). the ACE remains in the idle
mode until programmed.

VLSI TECHNOLOGY, INC
VL 16C450 • VL82C50A • VL82C50

A hardware reset of the ACE sets the
THRE and TEMT status bit in the LSR.
When interrupts are subsequently
enabled, and interrupt occurs due to
THRE.
A summary of the effect of a reset on the
ACE is given in Table 11.
PROGRAMMING
The serial channel of the ACE is programmed by the control register LCR,
IER, DLL and DLM, and MCR. These
control words define the character
length, number of stop bits, parity, baud
rate, and modem interface.

While the control register can be written
in any order, the IER should be written to
last because it controls the interrupt
enables. Once the serial channel is
programmed and operational, these
registers can be updated any time the
ACE serial channel is not transmitting or
receiving data.
The control signals required to access
each serial channel's internal registers
are shown below.
SOFTWARE RESET
A software reset of the serial channel is
a useful method for returning to a

TABLE 8. BAUD RATES (1.8432 MHz CLOCK)
Desired
Baud Rate

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000

Divisor Used

2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6

3
2

Percent Error
Difference Between
Desired and Actual

0.026
0.058

0.69

2.86

completely known state without a system
reset. Such a reset consists of writing to
the LCR, Divisor Latches, and MCR
registers. The LSR and RBR registers
should be read prior to enabling interrupts in order to clear out any residual
data or status bits which may be invalid
for subsequent operation.

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

TABLE 9. BAUD RATES (2.4576 MHz CLOCK)
Desired
Baud Rate

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

Divisor Used

3072
2048
1396
1142
1024
512
256
128
85
77

64
43
32
21
16

Percent Error
Difference Between
Desired and Actual

0.026
0.0007

0.392
0.260
0.775

1.587

8
4

TAB LE 10. BAUD RATES (3.072 MHz CLOCK)
Desired
Baud Rate

75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

Divisor Used

3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5

Percent Error
Difference Between
Desired and Actual

0.026
0.034

0.312
0.628
1.23

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

TABLE 11. MASTER RESET
Register/Signal

Reset Control

Interrupt Enable Register
Interrupt Identification
Register
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register

Reset
Reset

SOUT
Intrpt (RCVR Errs)
Intrpt (RCVR Data Ready)
Intrpt (THRE)
Intrpt (Modem Status Changes)
-out2
-RTS
-DTR
-out1

Reset
Read LSRlReset
Read RBRlReset
Read "RlWrite THRlReset
Read MSRlReset
Reset
Reset
Reset
Reset

Reset
Reset
Reset
Reset

Reset
All Bits Low (0-3 forced and 4-7 permanent)
Bit 0 is High, Bits 1 and 2 Low
Bits 3-7 are Permanently Low
All Bits Low
All Bits Low
All Bits Low, Except Bits 5 and 6 are High
Bits 0-3 Low
Bits 4-7 Input Signal
High
Low
Low
Low
Low
High
High
High
High

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

AC CHARACTERISTICS :

= aoe to +70 oe, vee = 5 V ±5% (Note 1)
VL16C450

Min

Units

Conditions

Address Strobe Width

tAS

Address Setup Time

tAH

Address Hold Time

tCS

Chip Select Setup Time

tCH

Chip Select Hold Time

tDIW

-OISTRIDISTR Strobe Width

125

175

tRC

Read Cycle Delay

175

500

Read Cycle
+tRC

360

755

tDD

-OISTRIDISTR to Drive
Disable Delay

100 pF Load
Note 3

tODD

Delay from -OISTR/DISTR
to Data

125

175

100 pF Load

tHz

-OISTRIDISTR to Floating
Data Delay

100 pF Load
Note 3

tDOW

-OOSTRIDOSTR Strobe
Width

tWC

Write Cycle Delay

Write Cycle
+tWC

tDS
tDH
tCSC·

Chip Select Output Delay
from Select

tRA·

Address Hold Time from
-OISTRlDlSTR

tRCS·

Chip Select Hold Time from
-OISTRIDISTR

tAR·

-OISTRIDISTR Delay from
Address

tCSR·

100

175

200

500

360

755

Data Setup Time

Data Hold Time

=tAW· + tDOW

100

Max

tAW

Min

VL82C50

Parameter

=tAR(1) + t DIW

Max

VL82C50A

Symbol

100 pFLoad

Note 2

-OISTRIDISTR Delay from
Chip Select

Note 2

tWA·

Address Hold Time from
-OOSTRIDOSTR

Note 2

tWCS·

Chip Select Hold Time from
-OOSTRIDOSTR

Note 2

tAW

-OOSTRIDOSTR Delay
from Address

Note 2

tCSW

-OOSTRIDOSTR Delay frorr
Select

Note 2

100

125

tMRW

Master Reset Pulse Width

tXH

Duration of Clock High Pulse

140

tXL

Duration of Clock Low Pulse

140

Notes: 1. All timings are referenced to valid 0 and valid 1. (See AC TEST POINTS.)
2. Applicable only when ADS is tied low.
3. Charge and discharge time is determined by VOL, VOH and the external loading.

External Clock
(3.1 MHz Max)

VLSI TECHNOLOGY, INC
VL 16C450 • VL82C50A • VL82C50

AC CHARACTERISTICS (Cont.):

=O°C to + 70°C, VCC =5 V ±5% (Note 1)

VL16C450
Symbol

Parameter

Min

Max

VLB2C50A
Min

Max

VL82C50
Min

Max

Units

Conditions

Transmitter
tHR1

Delay from Rising Edge of
-DOSTR/DOSTR (WR THR)
to Reset Interrupt

175

1000

N/A

100 pF Load

tHR2

Delay from Falling Edge of
-DOSTR/DOSTR (WR THR)
to Reset Interrupt

N/A

1000

100 pF Load

tlRS

Delay from InitiallNTR
Reset Interrupt

-BAUDOUT
CYCLES

tSI

Delay from Initial Write to
Interrupt

-BAUDOUT
CYCLES

tSS

Delay from Stop to Next
Start

tSTI

tlR

100

Delay from Start Bit Low to
Interrupt (THRE) High

-BAUDOUT
CYCLES

Delay from -DISTR/DISTR
(RD IIR) to Reset Interrupt
(THRE)

250

1000

100 pF Load

Modem Control
tMDO

Delay from -DOSTR/DOSTR
(WR MCR) to Output

250

1000

100 pF Load

tSIM

Delay to Set Interrupt from
MODEM Input

250

1000

100 pF Load

tRIM

Delay to Reset Interrupt from
-DISTR/DISTR (RS MSR)

250

1000

100 pF Load

Baud Generator
216_1

2 16_1

Baud Divisor

tBLD

Baud Output Negative
Edge Delay

125

250

100 pF Load

tBHD

Baud Output Positive
Edge Delay

125

250

100 pF Load

tLW

Baud Output Down Time

425

fX .. 2 MHz, +2,
100 pF Load

tHW

Baud Output Up Time

330

fX - 2 MHz, +2,
100 pF Load

Receiver
tSCD

Delay from RCLK to
Sample Time

tSINT

Delay from Stop to Set
Interrupt

100 pF Load

tRINT

Delay from -DISTR/DISTR
(AD RBA/RDLSA) to Reset
Interrupt

100 pF Load

Note: 1. All timings are referenced to valid 0 and valid 1. (See AC TEST POINTS.)

VLSI TECHNOLOGY, INC.

VL 16C450 • VL82C50A • VL82C50

TIMING DIAGRAMS
READCVCLE

-ADS

A2., A1, AO

-CS2, eS1, esa

eSOUT

-DISTRIDISTR

_ _ _ _ _ __

-OOSTRJDOSTR

DDIS

DATA
1XH)7

BAUDOUT

XTAL1

~ j.-tHW .
-BAUD OUT
(+1 )

-BAUD OUT
(+2)

-BAUD OUT
(+3)

.-.J j.- tBLD..aIl4-tBHD
-11-BAUD OUT ---,
(+N, N>3)

= (N - 2) XTAL1 CYCLES
~
rL---~.ltHW

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

n..-

RECEIVER

RCLKIJ-~- - - - - ~ tSCD

ClK
SAMPLE

SAMPLE
ClK

~ ~

8ClKS

-----------------n..-

JL--L--L-~rl---L----1--=j_i:=~I;:~-«
~
ffil~
~
"

(DATAINTERRUPT
READYOR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

------------------...,X

-DISTRIDISTR
(NOTE
2) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ •
(READ
REC
DATA BUFFER
OR RDLSR)

tAINT

~_ _ __

RCVR ERR)

~CTIVE

•

\...,_ _ __

TRANSMITTER
TART

SERIAL
OUT (SOUT)

'>C)'STOP (1-2)
L-_ _ _ _ _ PARITY
~

"-Ll
______
~
tSTi

{
-----~\

INTERRUPT
(THRE)

rc:'-'~

(WRTHA)
-DOSTR/OOSTR
(NOTE 1)

tlR

-DISTRIDISTA _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
(ADIIA)
(NOTE 2)

Notes: 1. See WRITE Timing ~iagram.
2. See READ Timing Diagram.

VLSI TECHNOLOGY, INC. VL 16C450 • VL82C50A • VL82C50

WRITE CYCLE

-ADS

A2, A1, AO

-CS2, CS1, CSO

CSOUT

- - -

---

------ ------ ------

~------~--~--~-WC------------~
-DOSTR/DOSTR

ACTIVE
'-------,(t--- •
OR

----------------------------------~~~~--~~-A-CT-IV-E

-OISTRIDISTR

tDS

DATA

I. .-r -I

tDH

- - - - - - - - - -_ _----,( VALID DATA)\...._ _ _ _ _ _ _ _ _ _ _ __

DO-D7

MODEM CONTROLS

=f
____t

-DOST(~~O~~~) _______
J
-RTS, -OTR
-OUT1, -OUT2

/WDo=tf

tMDO

-CTS, -OSA, -oeD

INTERRUPT

-------t---

-0 ISTRID ISTR
(RD MSR) _ _ _ _ _ _ _ _ __

~I----------------------,
~---------

VLSI TECHNOLOGY, INC.
VL 16C450 • VL82C50A • VL82C50

AC TESTING INPUT/OUTPUT WAVEFORMS
EXTERNAL CLOCK INPUT (3.1 MHz MAXIMUM)

.....

AC TEST POINTS

tXH

.tXL"

Note:

All timings are referenced to valid 0 and valid 1.

TEST CIRCUIT

2.54 V

Device Under Test
680n

• Includes Scope and Jig 82 pF·

Capacitance

VLSI TECHNOLOGY, INC VL16C450 • VL82C50A • VL82C50

BASIC CONFIGURATION
VL16C450,VL82CSOA,VL82CSO

SOUT
SIN 1 4 - _ - 1

EIA
DRIVERS

-RTS

-DSR
VL16C450
VL82C50A
VL82C50

-DCD

-CTS

-RI

-ADS

TO RS232
INTERFACE

XTAL1

DOSTR
DISTR
-CS2

XTAL2

CS1
-BAUD

CSO

-OUT
RCLK

TYPICAL COMPONENT VALUES
Crystal
3.072 MHz

RP
1 Mn.

I
I

RX2
1.S Kn.

10·30 pF I 40·90 pF

C2I

IC1

VLSI TECHNOLOGY, INC
VL 16C450 • VL82C50A • VL82C50

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

-10°C to + 70°C

Storage Temperature -65°C to + 150°C
Supply Voltage to
Ground Potential -0.5 V to VCC + 0.3 V
Applied Output
Voltage

Stresses above those listed may cause
permanent damage to the device. These
are stress ratings only, functional
operation of this device at these or any
other conditions above those indicated in

this data sheet is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect device
reliability.

-0.5 V to VCC + 0.3 V

Applied Input
Voltage

-0.5 Vto + 7.0 V

Power Dissipation

500 mV

DC CHARACTERISTICS: TA =0° to +70°C, vee = 5 V ± 5%
VL16C450

VL82C50A

VL82C50

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Units

VILX

Clock Input Low Voltage

-0.5

0.8

-0.5

0.8

-0.5

0.8

VIHX

Clock Input High Voltage

2.0

VCC

2.0

VCC

2.0

VCC

VIL

Input Low Voltage

-0.5

0.8

-0.5

0.8

-0.5

0.8

VIH

Input High Voltage

2.0

VCC

2.0

VCC

2.0

VCC

VOL

Output Low Voltage

0.4

VOH

Output High Voltage

0.4
2.4

2.4

Conditions

10L 1.6 mA on All
10H =-1.0 mA

ICC
(Ave)

Average Power Supply
Current (VCC)

VCC =5.25 V, No
Loads on SIN, -DSR
-RLSD, -CTS, -DCD.
-RI = 2.0 V. All Other
Inputs ... 0.8 V. Baud
Rate Generator at
4MHz. Baud Rate at
56K.

ilL

Input Leakage

±10

(lA

VCC= 5.25 V
VSS ... 0 V
All Other Pins Floating

ICL

Clock Leakage

±10

(lA

VIN = 0 V, 5.25 V

10Z

Three-State Leakage
±20

±20

(lA

0.8

VILMR

MR Schmitt VIL

VIHMR

MR Schmitt VIH

0.8
2.0

2.0

VCC = 5.25 V
VSS ... 0 V
VOUT ... 0 V, 5.25 V
1~ Chip Deselected
2 Chip and Write
Mode selected

Note: -IN IT, -AFD, -STB, and -SUN are collector output pins that each have an internal pull-up resista (2.5K Q - 3.5K Q) to
VCC. This will generate a maximum of 2.0 mA of internallOL. In addition to this internal current, each pin will sink at
least 10 mA, while maintaining the VOL specification of 0.4 V Max.

VLSI TECHNOLOGY, INC.

VL16C450 • VL82C50A • VL82C50

VLSI TECHNOLOGY, INC.
VL16C451
PARALLEL/ASYNCHRONOUS
COMMUNICATIONS ELEMENT

FEATURES

DESCRIPTION

• IBM PC/AT-compatible

The VL 16C451 is an enhanced version
of the popular VL 16C450 asynchronous
communications element (ACE). The
serial channel performs serial-to-parallel
conversion on data characters received
from peripheral devices or modems, and
parallel-to-serial conversion on data
characters transmitted by the CPU. The
complete status of the Parallel/Asynchronous Communications Element
(P/ACE) can be read at any time during
functional operation by the CPU. The
information obtained includes the type
and condition of the transfer operations
being performed, and error conditions. It
is fully pin- and upward-compatible with
the dual serial channel VL 16C452. The
second serial channel of the VL 16C452
occupies pins that are VCC, GND, or
N.C. (not connected) on the VL 16C451.

• VL 16C450 with on-board Centronix
printer interface
• Completely pin- and upward-compatible with the dual serial channel
VL16C452.
• Independent control of transmit,
receive, line status and data set
interrupts
• Individual modem control signals
• Programmable serial interface
characteristics:
- 5-,6-,7- or 8-bit characters
- Even-, odd- or no-parity bit
generation and detection
- 1, 1 112 or 2 stop bit generation
• Three-state TTL drive for the data and
control bus

PIN DIAGRAM

The VL16C451 also provides the user
with a fully bidirectional parallel data port
that fully supports the parallel Centronics
type printer. This port allows information
received from either serial communication port to be printed from the PlACE.
The parallel port, together with the serial
port, provide IBM PC/AT-compatible
computers with a single device to serve
the two system ports.
A programmable baud rate generator is
included that can divide the timing
reference clock input by a divisor
between 1 and (2 16 -1).
The VL 16C451 is housed in a
68-pin plastic leaded chip carrier.

BLOCK DIAGRAM
VL16C451

GND
GND

GND

CLK

GND

2
N.C.
N.C.

-ACK BUSY

vec

I GND I GND I vee I-lPTOE I PE I SLCT I

GND

-ERR

I GND

-<)TSO
-DSRO
-RLSDO
-RIO
SINO

1 68 67 66 65 64 63 62 61

•

N.C.

1NT2

N.C.

-SUN

-<)SO

GND

-lNIT

OBO ·OB7

DBO

-NO

-8TB
GND

DB3

PDO

AO-A2.

PD1

~ow

DB-4

TOP

VIEW

DB5

PD2

DBS

PD3

DB7

PO ..

GND

PD5

vee

PD6

8 "

DB1
DB2

~
....:.........

~OR

SELECT
AND

- - t CONTROL
-RESET - - t
LOGIC
CLK - - t

BOO

,~8
8 '"

-RTSO

P07

-DTRO

INTO

SOUTO

BOO

-RTSO
-DTRO
SOUTO
INTO

UART

-ERR
SLCT
BUSY
PE

PARAllEL
PORT

-ACK

PDO-P07
~NIT

-AFD
-STB
-SUN
INT2

~TOE

-CS2

ORDER INFORMATION
Maximum
Clock Frequency

Part
Number
VL 16C451-QC

3.1 MHz

Package
Plastic Leaded Chip Carrier (PLCC)

Note: Operating temperature range is O°C to +70°C.

VLSI TECHNOLOGY, INC
VL16C451

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

$Ignal
Description

-lOR

Input/Output Read Strobe - This is an active low input which causes the serial channel to
output data to the data bus (OBO-OB7). The data output depends upon the register
selected by the address inputs AO, A1, A2. Chip Select 0 (-CSO) selects the UART and
Chip Select 2 (-CS2) selects the line printer port.

-lOW

Input/Output Write Strobe - This is an active low input which causes data from the data
bus (OBO-OB7) to be input to the UART or to the parallel port. The data input depends
upon the register selected by the address inputs AO, A1, A2. The chip select inputs
(-eSO and -CS2) enable the UART and the parallel port (respectively).

OBO-OB7

14-21

Data Bits OBO-OB7 - The Data Bus provides eight, three-state 110 lines for the transfer of
data, control and status information between the VL16C451 and the CPU. These lines are
normally in a high-impedance state except during read operations. DO is the least significant bit (lSB) and is the first serial data bit to be received or transmitted.

AO, A1, A2

35,34,33

Address Lines AO-A2 - The address lines select the internal registers during CPU bus
operations. See Table 1 for the decode of the serial channels, Table 11 for the decode of
the parallel line printer port.

ClK

Clock Input - The external clock input to the UART baud rate divisor

SOUTO,

Serial Data Output - This line is the serial data output from the UARTs transmitter
circuitry. A mark (1) is a logic "one" (high) and space (0) is a logic "zero" (low). SOUTO is
held in the mark condition when the transmitter is disabled, Reset is true, the Transmiter
Register is empty, or when in the loop Mode.

-CTSO

Clear to Send Input - The logical state of the -CTS pin is reflected in the CTS bit of the
(MSR) Modem Status Register [CTS is bit 4 of the MSR, written MSR (4)] of the UART. A
change of state of the -CTS pin, since the previous reading of the MSR causes the
setting of OCTS [MSR(O)] of the Modem Status Register. When the -CTS pin is low, the
modem is indicating that data on SOUTO can be transmitted.

OSRO

Data Set Ready Input - The logical state of the OSRO pin is reflected in MSR(5) of the
Modem Status Register. OOSR [MSR(1)] indicates whether the OSRO pin has changed
state since the previous reading of the MSR. When the OSRO pin is low, the modem is
indicating that it is ready to exchange data with the UART.

OTRO

Data Terminal Ready Output - The OTRO pin can be set (low) by writing a logic 1 to
MCR(O), Modem Control Register bit 0 of the UART. This signal is cleared (high) by
writing a logic 0 to the OTR bit [MCR(O)] or whenever a reset occurs. When active (low),
the DTRO pin indicates to the OCE that the UART is ready to receive data.

-RTSO

Request to Send Output - The -RTSO signal is an output on the UART used to enable the
modem. The -RTSO pin is set low by writing a logic 1 to MCR(1) bit 1 of the UARTs
Modem Control Register. The -RTSO pin is reset high by Reset. A low on the -RTSO pin
indicates to the DCE that the UART has data ready to transmit. In haH duplex operations,
-RTSO is used to control the direction of the line.

-RIO

Ring Indicator Input - When low, -RIO indicates that a telephone ringing signal has been
received by the modem or data set. The -RIO signal is a modem control input whose
condition is tested by reading MSR(6) (RI) of the UART. The Modem Status Register
output TERI [MSR(2)] indicates whether the RI input has changed from high to low since
the previous reading of the MSR. Hthe interrupt is enabled [IER(3)-1] and -RIO changes
from a high to low, an interrupt is generated.

-lPTOE

SINO

Parallel Data Output Enable - When low, this signal enables the Write Data Register to
the POO - P07 lines. A high puts the POO - PD7 lines in the high-impedence state
allowing them to be used as inputs. -lPTOE is usually tied low for line printer operation.
41

Serial Data Input - The serial data input moves information from the communication line
or modem to the Vl16C451 receiver circuits. A mark (1) is high, and a space (0) is low.
Data on serial data inputs is disabled when operating in the loop mode.

VLSI TECHNOLOGY, INC.
VL16C451

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Desalptlon

-RLSOO.

Receive Line Signal Oetect - When low. the -RLSO output indicates that the data carrier
has been detected by the modem or data set. -RLSO is a modem input whose condition
can be tested by the CPU by reading MSR(7) (RLSO) of the Modem Status Register.
MSR(3) (ORLSO) of the Modem Status Register indicates whether the -RLSO input has
changed since the previous reading of the MSR. -RLSO has no effect on the receiver. If
the -ALSO changes state with the modem status interrupt enabled. an interrupt occurs.

-RESET

Reset - When low. the reset input forces the VL 16C451 into an idle mode in which all
serial data activities are suspended. The Modem Control Register (MCR) along with its
output is cleared. The Line Status Register (LSR) is cleared except for the THRE and
TEMT bits. which are set. All functions of the device remain in an idle state until programmed to resume serial data activities.

INTO

Serial Channel Interrupt Output - This three-state output is enabled by the MCR bit 2.
The serial channel interrupt goes active (high) when one of the following interrupts has
an active (high) condition and is enabled by the Interrupt Enable Register of the serial
channel: Receiver Error flag. Received Oata Available. Transmitter Holding Register
Empty. and Modem Status. The interrupt is reset low upon appropriate service or a reset.

-CSO.-CS2

32.38

Chip Selects - Each Chip Select input acts as an enable for the write and read signals
for its channel. -eSO enables the serial port. while -CS2 enables the the signals to the
line printer port.

BOO

Bus Buffer Output - This active high output is asserted when this serial channel or the
parallel port is read. This output can be used to control the system bus driver device
(74LS245).

POO-P07

53-46

Parallel Oata Bits (0-7) - These eight lines provide a byte-wide input or output port to the
system. The eight lines are held in a high-impedance state when -LPTOE is held in the
high state.

-STB

Line Printer Strobe - This open-drain line provides communication between the
VL 16C451 and the line printer. When it is active low. it provides the line printer with a
signal to latch the data currently on the parallel port.

-AFO

Line Printer Autofeed - This open-drain line provides the line printer with an active low
signal when continuous form paper is to be autofed to the printer.

-IN IT

Line Printer Initialize: This open-drain line provides the line printer with a signal that
allows the line printer initialization routine to be started.

-SUN

Line Printer Select: This open-drain line selects the printer when it is active low.

INT2

Printer Port Interrupt - This signal is an active high. three-state output. generated by the
positive transition of -ACK. It is enabled by bit 4 of the Write Control Register.

-ERROR

Line Printer Error - This is an input line from the line printer. The line printer reports an
error by holding this line low during the error condition.

SLCT

Line Printer Selected - This is an input line from the line printer that goes high when the
line printer has been selected.

BUSY

Line Printer Busy - This is an input line from the line printer that goes high when the line
printer is not ready to accept data.

Line Printer Paper Empty - This is an input line from the line printer that goes high when
the printer runs out of paper.

-ACK

Line Printer Acknowledge - This input goes low to indicate a successful data transfer has
taken place. It generates a printer port interrupt during its positive transition.

VCC

3.23.40.64

Power Supply - The power supply requirement is 5 V ±5%.

GNO

2.5-9. 13.22.27. Ground (0 V) - All pins must be tied to ground for proper operation.
42.43.54.61.62

VLSI TECHNOLOGY, INC.
VL16C451

FUNCTIONAL
DESCRIPTION:
SERIAL CHANNEL REGISTERS
Three types of internal registers are
used in the serial channel of the
VL 16C451. They are used in the
operation of the device, and are the
control, status, and data registers. The
control registers are the Bit Rate Select
Register DLL (Divisor Latch LSB) and
DLM (Divisor Latch MSB), Line Control
Register, Interrupt Enable Register, and
the Modem Control registers, while the
status registers are the Line Status
Registers and the Modem Status
Register. The data registers are the
Receiver Buffer Register and the
Transmitter Holding Register. The
Address, Read, and Write inputs are
used in conjunction with the Divisor
Latch Access Bit in the Line Control
Register [LCR(7)] to select the register
to be written or read (see Table 1).
Individual bits within these registers are
referred to by the register mnemonic
and the b~ number in parenthesis. An
example, LCR(7) refers to Line Control
Register Bit 7.
The Transmitter Buffer Register and
Receiver Buffer Register are data
registers holding from five to eight bits
of data. If less than eight data bits are
transmitted, data is right justified to the

LSB. Bit 0 of a data word is always the
first serial data bit received and
transmitted. The VL 16C451 data
registers are double-buffered so that
read and write operations can be
performed at the same time the UART
is performing the parallel-to-serial and
serial-to-parallel conversion.
The format of the data character is
controlled by the Line Control Register.
The contents of the LCR may be read,
eliminating the need for separate
storage of the line characteristics in
system memory. The contents of the
LCR are described below:
LCR (0) Word Length Select Bit 0
(WLSO)
LCR (1) Word Length Select Bit 1
(WLS1)
LCR (2) Stop Bit Select (STB)
LCR (3) Parity Enable (PEN)
LCR (4) Even Parity Select (EPS)
LCR (S) Stick Parity
LCR (6) Set Break
LCR (7) Divisor Latch Access Bit
(OLAB)
LCR (0) and LCR(1) word length select
bit 1: The number of bits in each serial
character is programmed as shown in
the following chart:

TABLE 1.SERIAL CHANNEL INTERNAL REGISTERS
DLAB

RBR

Receiver Buffer Register (read only)

THR

Transmitter Holding Register (write only)

IER

Interrupt Enable Register

IIR

Interrupt Identification Register (read only)

LCR

Line Control Register

X
X

MCR

Modem Control Register

LSR

Line Status Register

MSR

Modem Status Register

SCR

Scratch Register

DLL

Divisor Latch (LSB)

DLM

Divisor Latch (MSB)

X • "Don't Care"

Mnemonic

O. Logic Low

LCR(1)
0
0
1
1

LCR(O)

0
1
0

Word Length
S Bits
6 Bits
7 Bits
a Bits

LCR(2) Stop Bit Select: LCR(2)
specifies the number of stop bits in each
transmitted character. If LCR(2) is a
logic 0, one stop bit is generated in the
transmitted data. If LCR(2) is a logic 1
when a S-bit word length is selected, 1.S
stop bits are generated. HLCR(2) is a
logic 1 when either a 6-, 7-, or a-bit word
length is selected, two stop bits are
generated. The receiver checks for two
stop bits if programmed.
LCR(3) Parity Enable: When LCR(3) is
high, a parity bit between the last data
word bit and stop bit is generated and
checked.
LCR(4) Even Parity Select: When parity
is enabled [LCR(3) .. 1], LCR(4)-0 selects
odd parity, and LCR(4) .. 1 selects even
parity.
LCR(S) Stick Parity: When parity is
enabled [LCR(3)-1], CLR(S)=1 causes
the transmission and reception of a
parity bit to be in the opposite state from
that indicated by LCR(4). This allows
the user to force parity to a known state
and for the receiver to check the parity
bit in a known state.
LCR(6) Break Control: When LCR(6) is
set to a logic "1", the serial output
(SOUT) is forced to the spacing (logic 0)
state. The break is disabled by setting
LCR(6) to a logic "0". The Break Control
bit acts only on SOUT and has no effect
on the transmitter logic. Break Control
enables the CPU to alert a terminal in a
computer communications system. If
the following sequence is used, no
erroneous or extraneous characters will
be transmi1ted because of the break.
1. Load an all "O"s pad character in
response to THRE.
2. Set break in response to the next
THRE.
3. Wait for the transmitter to be idle
(TEMT... 1), and clear break when
normal transmission has to be
restored.

1 .. Logic High

Note: The serial channel is accessed when -CSO is low.

VLSI TECHNOLOGY, INC.
VL 16C451

FIGURE 1. UNE CONTROL REGISTER

L...-_-.

Word
Length
Select

0 1
1 0
1 1

5 Data Bits
6 Data Bits
7 Data Bits
8 Data Bits

Stop
o = 1 Stop Bit
Bit Select 1 = 1.5 Stop Bits If 5 Data Bits Selected
2 Stop Bits if 6,7,8 Data Bits Selected
L..-_ _ _ _ _ _.Parity
o = Parity Disabled
1 = Parity Enabled
Enable
L..-_ _ _ _....

L..-_ _ _ _ _ _ _.....

Even
Parity
Select

1..-_ _ _ _ _ _ _ _ _

Parity
Stick

Odd Parity
1 = Even Parity

o=
1

1..-_ _ _ _ _ _ _ _ _ _ _

Break
Control

1..-_ _ _ _ _ _ _ _ _ _ _ _" " , Divisor
Latch

Stick Parity Disabled
Stick Parity Enabled

Break Disabled
1 = Break Enabled

o = Access Receiver Buffer
1 = Access Divisor Latches

Access
Bit
LCR(7) Divisor Latch Access Bit
(DLAB): LCR(7) must be set high (logic
"1") to access the Divisor Latches DLL
and DLM of the Baud Rate Generator
during a read or write operation.
LCR(7) must be input low to access the
Receiver Buffer, the Transmitter
Holding, or the Interrupt Enable
Registers.
The Line Status Register (LSR) is a
single register that provides status
indications. The LSR is usually the first
register read by the CPU to determine
the cause of an interrupt or to poll the
status the serial channel of the
VL16C451.
Three error flags OE, FE, and PE
provide the status of any error condi·
tions detected in the receiver circuitry.
During reception of the stop bits, the
error flags are set high by an error
condition. The error flags are not reset
by the absence of an error condition in
the next received character. The flags
reflect the last character only if no
overrun occurred. The Overrun Error

character in the Receiver Buffer
Register has been overwritten by a
character from the Receiver Shift
Register before being read by the CPU.
The character is thereby lost. Framing
Error (FE) indicates that the last
character received contained incorrect
(low) stop bits. This is caused by the
absense of the required stop bit or by a
stop bit too short to be detected. Parity
Error (PE) indicates that the last
character received had a parity error
based on the programmed and calculated parity of the received character.
The Break Interrupt (BI) status bit
indicates that the last character
received was a break character. A
break character is an invalid data
character. However, it is an entire
character, including parity and stop bits.
The Transmitter Holding Register
Empty (THRE) bit indicates that theTHR
register is empty and may receive
another character. The Transmission
Shift Register Empty (TEMn bit

indicates that the Transmitter Shift
Register is empty, and the serial
channel has completed transmission of
the last character to be sent. If the
interrupt is enabled [IER(1 )], an active
THRE causes an interrupt (INTRPT).
The Data Ready (DR) bit indicates that
the RBR has been loaded with a
received character (including Break)
and that the CPU may access this data.
Reading the LSR clears LSR(1)·
LSR(4). (OE, PE, FE, and BI.)
The contents of the Line Status
Register shown in Table 2 are de·
scribed below:
LSR(O) Data Ready (DR): Data Ready
is set high when an incoming character
has been received and transferred into
the Receiver Buffer Register. LSR(O) is
reset low by a CPU read of the data in
the Reciever Buffer Register.
LSR(1) Overrun Error (OE): Overrun
Error indicates that data in the Receiver
Buffer Register was not read by the
CPU before the next character was

VLSI TECHNOLOGY, INC.
VL16C451

TABLE 2. LINE STATUS REGISTER BITS
LSR BITS

Logic 1

logic 0

LSR (O) Data Ready (DR)

Ready

Not Ready

LSR (1) Overrun Error (OE)

Error

No Error

LSR(2) Parity Error (PE)

Error

No Error

LSR (3) Framing Error (FE)

Error

No Error

LSR (4) Break Interrupt (BI)

Break

No Break

LSR(5) Transmitter Holding Register Empty (THRE)

Empty

Not Empty

LSR(6) Transmitter Empty (TEMT)

Empty

Not Empty

LSR(7) Not Used

transferred into the Receiver Buffer
Register, overwriting the previous
character. The OE indicator is reset
whenever the CPU reads the contents
of the Line Status Register.
LSR(2) Parity Error (PE): Parity Error
indicates that the received data
character does not have the correct
even or odd parity, as selected by the
Even Parity Select bit (LCR(4)). The
PE bit is set high upon detection of a
parity error, and is reset low when the
CPU reads the contents of the LSR.
LSR(3) Framing Error (FE): Framing
Error indicates that the received
character did not have a valid stop bit.
LSR(3) is set high when the stop bit
following the last data bit or parity bit is
detected as a zero bit (spacing level).
The FE indicator is reset low when the
CPU reads the contents of the LSR.
LSR(4) Break Interrupt (BI): Break
Interrupt is set high when the received
data input is held in the spacing (logic
0) state for longer than a full word
transmission time (start bit + data bits +
pairty + stop bits). The BI indicator is
reset when the CPU reads the contents
of the Line Status Register.
LSR(1) - LSR(4) are the error conditions that produce a Reciever Line
Status interrupt (priority 1 interrupt in
the Interrupt Identification Register
(IIR)) when any of the conditions are
detected. This interrupt is enabled by
setting IER(2)=1 in the Interrupt Enable
Register.
LSR(5) Transmitter Holding Register
Empty (THRE): THRE indicates that
the VL82C50A is ready to accept a new
character for transmission. The THRE

bit is set high when a character is
transferred from the Transmitter
Holding Register into the Transmitter
Shift Register. LSR(5) is reset low by
the loading of the Transmitter Holding
Register by the CPU. LSR(5) is not
reset by a CPU read of the LSR.
When the THRE interrupt is enabled
(IER{1 )=1). THRE causes a priority 3
interrupt in the IIR. If THRE is the
interrupt source indicated in IIR,
INTRPT is cleared by a read of the IIR.
LSR(6) Transmitter Empty (TEMT):
TEMT is set high when the Transmitter
Holding Register (THR) and the
Transmitter Shift Register (TSR) are
both empty. LSR(6) is reset low when
a character is loaded into the THR and
remains low until the character is
transferred out of SOUTo TEMT is not
reset low by a CPU read of the LSR.
LSR(7): This bit is always

The Modem Control Register (MCR)
controls the interface with the modem
or data set as described in Table 3.

MCR can be written and read. The
-RTS and -DTR outputs are directly
controlled by their control bits in this
register. A high input asserts a low
(true) at the output pins. MCR Bits 0, 1,
3, and 4 are shown below:
MCR(O): When MCR(O) is set high, the
-DTR output is forced low. When
MCR{O) is reset low, the -DTR output is
forced high. The -DTR output of the
serial channel may be input into an
inverting line driver in order to obtain
the proper polarity input at the modem
or data set.
MCR(1): When MCR(1) is set high, the
RTS output is forced low. Whe MCR(1)
is reset low, the -RTS output is forced
high. The -RTS output of the serial
channel may be input into an inverting
line driver in order to obtain the proper
polarity input at the modem or data set.
MCR(3): When MCR(3) is set high, the
INT output is enabled.
MCR(4): MCR(4) provides a local
loopback feature for diagnostic testing
of the channel. When MCR(4) is set
high, Serial Output (SOUT) is set to the
marking (logic "1") state, and the
receiver data input Serial Input (SIN) is
disconnected. The output of the
Transmitter Shift Register is looped
back into the Receiver Shift Register
input. The three modem control inputs
(-CTS, -DSR, and -RI) are disconnected. The modem control outputs
(-DTR and -RTS) are internally connected to the four modem control
inputs. The modem control output pins
are forced to their inactive state (high).

TABLE 3. MODEM CONTROL REGISTER BITS
Logic 1

MeR BITS

Logic 0

MCR (O) DataTerminal Ready (DTR)

-DTR Output Low

-DTR Output High

MCR (1) Request to Send (RTS)

-RTS Output Low

-RTS OutputHigh

MCR (2) 0
MCR (3) Interrupt (INT) Enable
MeR (4) LOOP
MCR (5) 0
MeR (6) 0
MeS (7) 0

INT Enabled

INT Disabled

Loop Enabled

Loop Disabled

VLSI TECHNOLOGY, INC
VL 16C451

FIGURE 2. MODEM CONTROL REGISTER
Modem Control Register (MeR)

L -_ _~

Data
Terminal
Ready

0 ... -DTR Output High (Inactive)
1 ... -DTR Output Low (Active)

Request
To Send

I-----~NC

Not Connected

o ...

~------------~ INT

INT Disabled
1 = INT Enabled

~-------~ LOOP
L.-_ _ _ _ _ _ _ _ _ _ _~

In the diagnostic mode, data transmit·
ted is immediately received. This
allows the processor to verify the
transmit and receive data paths of the
selected serial channel. Bits MCR(5) •
MCR(7) are permanently set to logic O.
The MSR provides the CPU with status
of the modem input lines from the
modem or peripheral devices. The MSR
allows the CPU to read the serial
channel modem signal inputs by
accessing the data bus interface of the
VL 16C451. In addition to the current
status information, four bits of the MSR
indicate whether the modem inputs have
changed since the last reading of the
MSR. The delta status bits are set high
when a control input from the modem
changes state, and reset low when the
CPU reads the MSR.
The modem input lines for the channel
are -CTS, -DSR, -RI, and -RLSD.
MSR(4) - MSR(7) are status indications
of these lines. The status indications
follow the status of the input lines. If the
modem status interrupt in the Interrupt
Enable Register is enabled [IER(3)], a
change of state in a modem input
signals will be reflected by the modem
status bits in the IIR register, and an
interrupt (INTRPT) is generated. The
MSR is a priority 4 interrupt. The
contents of the Modem Status Register
are described in Table 4. Note that the
state (high or low) of the status bits are

-RTS Output High (Inactive)
1 = -RTS Output Low (Active)

0...

1...

LOOP Disabled
LOOP Enabled

These Bits are Permanently Set to Logic "0".

inverted versions of the actual input
pins.
MSR(O) Delta Clear to Send (DCTS):
DCTS indicates that the -CTS input to
the serial channel has changed state
since the last time it was read by the
CPU.
MSR(1) Delta Data Set Ready (DDSR):
DDSR indicates that the -DSR input to
the serial channel has changed state
since the last time it was read by the
CPU.
MSR(2) Trailing Edge of Ring Indicator
(TERI): TERI indicates that the -RI
input to the serial channel has changed
state from high to low since the last
time it was read by the CPU. Low to
high transitions on -RIO do not activate
TERI.
MSR(3) Delta Data Carrier Detect
(DRSLD): DRSLD indicates that the

-RSLD input to the serial channel has
changed state since the last time it was
read by the CPU.
MSR(4) Clear to Send (CTS): Clear to
Send (CTS) is the status of the -CTS
input from the modem indicating to the
serial channel that the modem is ready
to receive data from the serial channel's
transmitter output (SOUn. If the serial
channel is in loop mode [MSR(4)=1],
MSR(4) is equivalent to -RTS in the
MCR.
MSR(5) Data Set Ready (DSR): Data
Set Ready (DSR) is a status of the
-DSR input from the modem to the
serial channel which indicates that the
modem is ready to provide received
data to the serial channel receiver
circuitry. Hthe channel is in the loop
mode [MCR(4)=1], MSR(5) is equivalent to the DTR in the MCR.

TABLE 4. MODEM STATUS REGISTER BITS
MSRBIt
MSR
MSR
MSR
MSR
MSR
MSR
MSR
MSR

(1)
(2)
(0)
(3)
(4)
(5)
(6)
(7)

Mnemonic
DDSR
TERI
DCTS
DRLSD
-CTS
·DSR
-RI
·RLSD

Description
Delta Data Set Ready
Trailing Edge of Ring Indicator
Delta Clear to Send
Delta Data Carrier Detect
Clear To Send
Data Set Ready
Ring Indicator
Receiver Line Signal Detect

VLSI TECHNOLOGY, INC
VL 16C451

MSR(S) Ring Indicator: Indicates the
status fo the RI input (pin 39). If the
channel is in the loop mode
[MCR(4)=1], MSR(S) is not connected
in the MCR.
MSR(7) Receive Line Signal Detect :
Receive Line Signal Detect indicates
the status of the Receive Line Signal
Detect (-RLSD) input. If the channel is
in the loop mode [MCR(4)-1], MSR(4) is
equivalent to OUT2 of the MCR.
The modem status inputs (-RI, -RLSD,
-DSR, and -CTS) reflect the modem
input lines with any change of status.
Reading the MSR register will clear the
delta modem status indications but has
no effect on the status bits. The status
bits reflect the state of the input pins
regardless of the mask control signals.
If a DCTS, DDSR, TERI, or DRLSD are
true, and a state change occurs during
a read operation (-lOR), the state
change is not indicated in the MSR. If
DCTS, DDSR, TERI, or DRLSD are
false, and a state change occurs during
a read operation, the state change is
indicated after the read operation.
For LSR and MSR, the setting of status
bits is inhibited during status register
read -lOR operations. If a status
condition is generated during a read
-lOR operation, the status bit is not set
until the trailing edge of the read
-lOR.
If a status bit is set during a read
-lOR operation, and the same status
condition occurs, that status bit will be
cleared at the trailing edge of the read
-lOR instead of being set again.
The VL 1SC451 serial channel contains
a programmable Baud Rate Generator
(BRG) that divides the clock (DC to
3.1 MHz) by any divisor from 1 to 2 16-1
(see also BRG description). The output
frequency of the Baud Generator is 1SX
the data rate [divisor # .. clock + (baud
rate x 1S)]. Two a-bit divisor latch
registers store the divisor in a 1S-bit
binary format. These Divisor Latch
registers must be loaded during
initialization. Upon loading either of the
Divisor latches, a 1S-bit baud counter is
immediately loaded. This prevents long
counts on initial load.
The receiver circuitry in the serial
channel of the VL 1SC451 is programmable for 5, S, 7, or a data bits per

character. For words of less than a
bits, the data is right justified to the
least significant bit LSB .. Data Bit 0
[RBR(O)]. Data Bit 0 of a data word
[RBR(O)] is the first data bit received.
The unused bits in a character less than
a bits are output low to the parallel
output by the serial channel.
Received data at the SIN input pin is
shifted into the Receiver Shift Register
by the 1SX clock provided at the RCLK
input. This clock is synchronized to the
incoming data based on the position of
the start bit. When a complete character is shifted into the Receiver Shift
Register, the assembled data bits are
parallel loaded into the Receiver Buffer
Register. The DR flag in the LSR
register is set.
Double buffering of the received data
permits continuous reception of data
without losing received data. While the
Receiver Shift Register is shifting a new
character into the serial channel, the
Receiver Buffer Register is holding a
previously received character for the
CPU to read. Failure to read the data in
the RBR before complete reception of
the next character result in the low of
the data in the Receiver Register. The
OE flag in the LSR register indicates
the overrun condition.
RBR Bits 0 thru 7:
RBR(O)
RBR(1)
RBR(2)
RBR(3)
RBR(4)
RBR(5)
RBR(S)
RBR(7)

Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit S
Data Bit 7

THR Bits 0 thru 7
THR(O)
THR(1)
THR(2)
THR(3)
THR(4)
THR(5)
THR(S)
THR(7)

Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit S
Data Bit 7

Scratch pad Register is an a-bit Read!
Write register that has no effect on
either channel in the VL 1SC451. It is
intended to be used by the programmer to hold data termporarily.
SCR Bits 0 thru 7
SCR(O)
SCR(1)
SCR(2)
SCR(3)
SCR(4)
SCR(5)
SCR(S)
SCR(7)

Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7

INTERRUPTS
The Interrupt Identification Register
(IIR) in the serial channel of the
VL 1SC451 has interrupt capability for
interfacing to current microprocessors.
In order to minimize software overhead
during data character transfers, the
serial channel prioritizes interrupts into
four levels. The four levels of interrupt
conditions are as follows:
1. Receiver Line Status (priority 1)
2. Received Data Ready (priority 2)
3. Transmitter Holding Register Empty
(priority 3)
4. Modem Status (priority 4)

The Transmitter Holding Register (THR)
holds parallel data from the data bus
(DO-D7) until the Transmitter Shift
Register is empty and ready to accept a
new character for transmission. The
transmitter and receiver word length
and number of stop bits are the same.
If the character is less than eight bits,
unused bits at the microprocessor data
bus are ignored by the transmitter.

Information indicating that a prioritized
interrupt is pending and the type of
interrupt is stored in the Interrupt
Identification Register (IIR). When
addressed during chip select time, the
IIR indicates the highest priority
interrupt pending. No other interrupts
are acknowledged until the interrupt is
serviced by the CPU. The logic equivalent of the interrupt control circuit is
shown in Figure 3. The contents of the
IIR are indicated in Table 5 and are
described below.

Data Bit 0 [THR(O)] is the first serial
data bit transmitted. The THRE flag
[LSR(5)] reflect the status of the THR.
The TEMT flag [LSR(5)] indicates if
both the THR and TSR are empty.

IIR(O): IIR(O) can be used in either a
hard-wired prioritized or polled environment to indicate whether an interrupt is
pending. When IIR(O) is low, an
interrupt is pending, and IIR contents

VLSI TECHNOLOGY, INC.
VL16C451

TABLE 5. INTERRUPT IDENTIFICATION REGISTER
INTERRUPT IDENTIFICATION

INTERRUPT SET AND RESET FUNCTIONS
Interrupt
Flag

Interrupt
Source

None

First

Receiver
line Status

OE,PE
FE, or BI

LSR Read

Second

Received Data
Available

RBR Read

Third

THRE

IIR Read if THRE is the
Interrupt Source or THR Write

Fourth

Modem Status

-CTS,-DSR
-RI,-RSLD

MSR Read

Bit 2

Bit 1

Bit 0

0
0

Priority
Level

X = Not Defined.

FIGURE 3. INTERRUPT CONTROL LOGIC

DR (LSR BIT O)I---------lr----.........
ERBFI (IER BIT 0J-------I

THRE (LSR BIT 5 r - - - - - - - - - - l
ETBEI (IER BIT 1~------t
OE (LSR BIT 1)
PE (LSR BIT 2)
FE (LSR BIT 3)
BI (LSR BIT 4)
ELSI (IER BIT 1)

-----I

DCTS (MSR BIT 0
DDSR (MSR BIT 1
TERI (MSR BIT 2)
DDCD (MSR BIT 3
EDSSI (IER BIT 3 ) - - - -......
Interrupt Enable (MCR BIT 3)

-----------------1

Interrupt
Reset Control

VLSI TECHNOLOGY, INC.
VL16C451

TABLE 6. SERIAL CHANNEL ACCESSIBLE REGISTERS
Register
Mnemonic

Bit 6

Bit 5

Blt4

Bit 3

Bit 2

Bit 1

Bit 0

RBR
(Read Only)

Data
Bit 7
(MSB)

Data
Bit 6

Data
BitS

Data
Bit 4

Data
Bit 3

Data
Bit 2

Data
Bit 1

Data
Bit 0
(LSB)*

THR
(Write Only)

Data
Bit 7

Data
Bit 6

Data
BitS

Data
Bit 4

Data
Bit 3

Data
Bit 2

Data
Bit 1

Data
Bit 0

DLL

Bit 7

Bit 6

BitS

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DLM

Bit1S

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

BitS

IER

(EDSSI)
Enable
Modem
Status
Interrupt

(ELSI)
Enable
Receiver
Line
Status
Interrupt

(ETBEI)
Enable
Transmitter
Holding
Register
Empty
Interrupt

(ERBFI)
Enable
Received
Data
Available
Interrupt

IIR
(Read Only)

Interrupt

Bit (1)

Bit (0)

"0" 1F
Interrupt
Pending

LCR

(DLAB)
Divisor
Latch
Access
Bit

Set
Break

Stick
Parity

(EPS)
EVen
Parity
Select

(PEN)
Parity
Enable

(STB)
Number
of Stop
Bits

(WLSB1)
Word
Length
Select
Bit 1

(WLSBO)
Word
Length
Select
Bit 0

MCR

Loop

Out 2

Out 1

(RTS)
Request
To
Send

(DTR)
Data
Terminal
Ready

LSR

(TEMT)
Transmitter
Empty

(THRE)
Transmitter
Holding
Register
Empty

(BI)
Break
Interrupt

(FE)
Framing
Error

(PE)
Parity
Error

(OE)
Overrun
Error

(DR)
Data
Ready

MSR

(DCD)
Data
Carrier
Detect

(RI)
Ring
Indicator

(DSR)
Data
Ready
Set

(CTS)
Clear
to
Send

(DRSLD)
Delta
Receive
Line Signal
Detect

(TERI)
Trailing
Edge
Ring
Indicator

(DDSR)
Delta
Data
Set
Ready

(DCTS)
Delta
Clear
to
Send

SCR

Bit 7

Bit 6

BitS

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

*LSB Data Bit 0 is the first bit transmitted or received.

VLSI TECHNOLOGY, INC
VL 16C451

may be used as a pointer to the appropriate interrupt service routine. When
IIR(O) is high, no interrupt is pending.
IIR(1) and IIR(2) are used to identify the
highest priority interrupt pending as
indicated in Table 2.
IIR(3) - IIR(7): These five bits of the IIR
are logic o.
The Interrupt Enable Register (IER) is a
Write register used to independently
enable the four serial channel interrupts
which activate the interrupt (INTRPT)
output. All interrupts are disabled by
resetting IER(O) - IER(3) of the Interrupt
Enable Register. Interrupts are enabled
by setting the appropriate bits of the IER
high. Disabling the interrupt system
inhibits the Interrupt Identification
Register and the active (high) INTRPT
output. All other system functions
operate in their normal manner, including the setting of the Line Status and
Modem Status Registers. The contents
of the Interrupt Enable Register is described in Table 3 and below:
IER(O): When programmed high
[IER(O)=Logic 1], IER(O) enables
Received Data Available interrupt.
IER(1): When programmed high
[IER(1 )=Logic 1], IER(1) enables the
Transmitter Holding Register Empty
interrupt.
IER(2): When programmed high
[IER(2)=Logic 1], IER(2) enables the
Receiver line Status interrupt.
IER(3): When programmed high
[IER(3)=Logic 1], IER(3) enables the
Modem Status Interrupt.
IER(4) - IER(7): These four bits of the
IER are logic o.
TRANSMITTER
The serial transmitter section consists of
a Transmitter Holding Register (THR),
Transmitter Shift Register (TSR), and
associated control logic. The Transmitter Holding Register Empty (THRE) and
Transmitter Shift Register Empty
(TEMT) are two bits in the Line Status
Register which indicate the status of
THR and TSR. To transmit a 5- to 8-bit
word, the word is written through DO-D7
to the THR. The microprocessor should
perform a write operation only if THRE is
high. The THRE is set high when the
word is automatically transferred from

the THR to the TSR during the transmission of the start bit.
When the transmitter is idle, THRE and
TEMT are high. The first word written
causes THRE to be reset to o. After the
transfer, THRE returns high. TEMT
remains low for at least the duration of
the transmission of the data word. If a
second character is transmitted to the
THR, the THRE is reset low. Since the
data word cannot be transferred from the
THR to the TSR until the TSR is empty,
THRE remains low until the TSR has
completed sending the word. When the
last word has been transmitted out of the
TSR, TEMT is set high. THRE is set
high one THR to TSR transfer time later.
RECEIVER
Serial asynchronous data is input into
the SIN pin. The idle state of the line
providing the input into SIN is high. A
start bit detect circuit continually
searches for a high to low transition from
the idle state. When the transition is
detected, a counter is reset, and counts
the 16X clock to 71/2, which is the
center of the start bit. The start bit is
valid if the SIN is still low at the mid-bit
sample of the start bit. Verifying the
start bit prevents the receiver from
assembling a false data character due to
a low going noise spike on the SIN input.
The Line Control Register determines
the number of data bits in a character
(LCR(O), LCR(1)), number of stop bits
LCR(2), if parity is used LCR(3), and the
polarity of parity LCR(4). Status for the
receiver is provided in the Line Status
Register to the Receiver Buffer Register,
the Data Received indication in LSR(O)
is set high. The CPU reads the Receiver
Buffer Register through DO-D7. This
read resets LSR(O). If DO-D7 are not
read prior to a new character transfer
from the RSR to the RBA. the overrun
error status indication is set in LSR(1).
The parity check tests for even or odd
parity on the parity bit, which precedes
the first stop bit. If there is a parity error,
the parity error is set in LSR(2). There is
circuitry which tests whether the stop bit
is high. If it is not, a framing error
indication is generated in LSR(3).
The center of the start bit is defined as
clock count 7 1/2. If the data into SIN is
symmetrical square wave, the center of
the data cells will occur within

± 3.125% of the actual center, providing
an error margin of 46.875%. The start
bit can begin as much as one 16X clock
cycle prior to being detected.
BAUD RATE GENERATOR (BRG)
The BRG generates the clocking for the
UART function, providing standard
ANSI/CCln bit rates. The oscillator
driving the BRG is provided by an
external clock into CLK.
The data rate is determined by the
Divisor Latch registers DLL and DLM
and the external frequency. The bit rate
is selected by programming the two
divisor latches, Divisor Latch Most
Significant Byte and Divisor Latch Least
Significant Byte. Setting DLL=1 and
DLM=O selects the divisor to divide by 1
(divide by 1 gives maximum baud rate
for a given input frequency at the CLK
input).
The BRG can use any of three different
popular frequencies to provide standard
baud rates. These frequencies are
1.8432 MHz, 2.4576 MHz, and 3.072
MHz. With these frequencies, standard
bit rates from 50 to 38.5 kbps are
available. Tables 7, 8, and 9 illustrate
the divisors needed to obtain standard
rates using these three crystal frequencies.
RESET
After power up, the VL 16C451 -RESET
input should be held low for 500 ns to
reset the VL 16C451 circuits to an idle
mode until initialization. A low on
-RESETcauses the following:
1. Initializes the transmitter and
receiver internal clock counters.
2. Clears the Line Status Register
(LSR), except for Transmitter Shift
Register Empty (TEMT) and
Transmit Holding Register Empty
(THRE), which are set. The Modem
Control Register (MCR) is also
cleared. All of the discrete lines,
memory elements and miscellane
ous logic associated with these
register bits are also cleared or
turned off. The Line Control
Register (LCR), Divisor Latches,
Receiver Buffer Register, Transmit
ter Buffer Register are not effected.
Following removal of the reset condition
(Reset high), the VL 16C451 remains in
the idle mode until programmed.

VLSI TECHNOLOGY, INC.
VL 16C451

A hardware reset of the VL16C451 sets
the THRE and TEMT status bit in the
LSR. When interrupts are subsequently
enabled, an interrupt occurs due to
THRE.

A summary of the effect of a reset on
the VL 16C451 is given in Table 10.
PROGRAMMING
Each serial channel of the VL 16C451 is
programmed by the control registers
LCR, IER, DLL and DLM, and MCR.
These control words define the character length, number of stop bits, parity,
baud rate, and modem interface.

While the control register can be written
in any order, the IER should be written
to last because it controls the interrupt
enables. Once the serial channel is
programmed and operational, these
registers can be updated any time the
VL 16C451 serial channel is not
transmitting or receiving data.
The control signals required to access
each serial channel's internal registers
are shown below.
SOFlWARE RESET
A software reset of the serial channel is
a useful method for returning to a

completely known state without a
system reset. Such a reset consists of
writing to the LCR, Divisor Latches, and
MCR registers. The LSR and RBR
registers should be read prior to
enabling interrupts in order to clear out
any residual data or status bits which
may be invalid for subsequent
operation.
CLOCK INPUT OPERATION
The maximum input frequency of the
external clock of the VL 16C451 is
3.1 MHz.

TABLE 7. BAUD RATES (1.8432 MHz CLOCK)

Desired
Baud Rate

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000

Divisor Used

2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2

Percent Error
Difference Between
Desired and Actual

0.026
0.058

0.69

2.86

VLSI TECHNOLOGY, INC
VL16C451

TABLE 8. BAUD RATES (2.4576 MHz CLOCK)
Desired
Baud Rate

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

Divisor Used

3072
2048
1396
1142
1024
512
256
128
85
77

64
43
32
21
16

Percent Error
Difference Between
Desired and Actual

0.026
0.0007

0.392
0.260
0.775

1.587

TABLE 9. BAUD RATES (3.072 MHz CLOCK)
Desired
Baud Rate

75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

Divisor Used

3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5

Percent Error
Difference Between
Desired and Actual

0.026
0.034

0.312
0.628
1.23

VLSI TECHNOLOGY, INC.
VL16C451

TABLE 10. RESET
Register/Signal
Interrupt Enable Register
Interrupt Identification
Register
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register
SOUT
Intrpt (RCVR Errs)
Intrpt (RCVR Data Ready)
Intrpt (THRE)
Intrpt (Modem Status Changes)
·-Out2
-RTS
-DTR
-Out1

Reset

Reset Control
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Read LSRlReset
Read RBRlReset
Read IIR1Write THRlReset
Read MSRlReset
Reset
Reset
Reset
Reset

All Bits Low (0-3 forced and 4-7 permanent)
Bit 0 is High, Bits 1 and 2 Low
Bits 3-7 are Permanently Low
All Bits Low
All Bits Low
All Bits Low, Except Bits 5 and 6 are High
Bits 0-3 Low
Bits 4-7 Input Signal
High
Low
Low
Low
Low
High
High
High
High

DEVICE APPLICATION

VL16C451

SERIAL
DATA
BUS

CHANNEL 0
BUFFERS

9-PIN
"0"

CONN

ADDR
BUS
CTL
BUS

UARTAND
PRINTER
PORT

PARALLEL
PORT
RIC NET

25-PIN
"0"

CONN

VLSI TECHNOLOGY, INC.
VL 16C451

FUNCTIONAL
DESCRIPTION
PARALLEL PORT REGISTERS
The VL 16C4S1 's parallel port interfaces
the device to a Centronics-style printer.
When Chip Select 2 (-CS2) is low, the
parallel port is selected. Table 11
shows the registers associated with this
parallel port. The read or write function
of the register is controlled by the state
of the read (-lOR) and write
(-lOW) pin as shown. The Read Data
Register allows the microprocessor to
read the information on the parallel bus.

The Read Status Register allows the
microprocessor to read the status of the
printer in the five most significant bits.
The status bits are Printer Busy
(-BUSY), Acknowledge (-ACK) which
is a handshake function, Paper Empty
(PE), Printer Selected (SLCT), and
Error
(-ERROR). The Read Control Register
allows the state of the control lines to
be read. The Write Control Register
sets the state of the control lines.

They are Interrupt Enable (IRQ ENB),
Select In (SUN), Initialize the Printer
(-IN IT), Autofeed the Paper (AUTOFD),
Strobe (STROBE), which informs the
printer of the presence of a valid byte
on the parallel bus. The Write Data
Register allows the microprocessor to
write a byte to the para"el bus.
The para"el port is completely compatible with the para"el port implementation used in the IBM SeriallPara"el
Adaptor.

TABLE 11. PARALLEL PORT REGISTERS
Register

Bit 6

BitS

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PDO

Read Status

-BUSY

-ACK

SLCT

-ERROR

Read Control

IRQ ENB

SLIN

-INIT

PD7

PD6

PD5

PD4

PD3

PD2

IRQ ENB

SLIN

-INIT

Read Data

Write Data
Write Control

TABLE 12. PARALLEL PORT REGISTER SELECT
Control Pins

-lOR -lOW -CS2
0
1
0

0
0

1
1

1
0

0
0
0

A1
0

AO
0

0
1

1
0

Read Status
Read Control

1
0
0

Read Data

0
0

Invalid
Write Data
Invalid

Write Control

Invalid

1
1

AUTOFD STROBE
PD1

PD~

AUTOFD STROBE

VLSI TECHNOLOGY, INC.
VL16C451

AC CHARACTERISTICS TA= aoe to +7o oe, vee= 5 V ±SOlo (Notes 1, 5)
Symbol

Parameter

tDlW

-lOR Strobe Width

125

Read Cyle

360

tDDD

Delay from -lOR to Data

125

100 pF Load

tHZ

-lOR to Floating Data Delay

100

100 pF Load, Note 4

tDOW

-lOW Strobe Width

100

Write Cycle

360

tDS

Data Setup Time

tDH

Data Hold Time

tRA

Address Hold Time from -lOR

Note 2

tRCS

Chip Select Hold Time from -lOR

Note 2

tAR

-lOR Delay from Address

Note 2

tCSR

-lOR Delay from Chip Select

Note 2

tWA

Address Hold Time from-lOW

Note 2

tWCS

Chip Select Hold Time from -lOW

Note 2

tAW

-lOW Delay from Address

Note 2

tCSW

-lOW Delay from Select

Note 2

tRW

Reset Pulse Width

tXH

Duration of Clock High Pulse

140

External Clock

tXL

Duration of Clock Low Pulse

140

External Clock

Min

Max

Units

Conditions

ns
ns

Notes:
1.
2.
3.
4.
5.

All timing specifications apply to pins on both serial channels (e.g. RI refers to both RIO and RI1).
The internal address strobe is always active.
RCLK = tXH and tXL.
Charge and discharge time is determined by VOL, VOH and the external loading.
All timings are referenced to valid 0 and valid 1.
(see AC TEST POINTS).

VLSI TECHNOLOGY, INC.
VL16C451

AC CHARACTERISTICS
Symbol

(Cont.) TA= O°C to +70°C, VCC= 5 V ±5% (Notes 1, 5)

Parameter

Conditions

Transmitter
tHR1

Delay from Rising Edge of -lOW
(WR THR) To Reset Interrupt

tlRS

Delay from InitiallNTR Reset to Transmit Start

tSI

Delay from Initial Write to Interrupt

tSTI

Delay from Stop to Interrupt (THRE)

tlR

Delay from -lOR (RD IIR)
to Reset Interrupt (THRE)

175

100 pF load

ClK
Cycles

Note 3

ClK
Cycles

Note 3

ClK
Cycles

250

100 pF load

Note 3

Modem Control
tMDO

Delay from -lOW
(WR MCR) to Output

250

100 pF load

tSIM

Delay to Set Interrupt from MODEM Input

250

100 pF load

tRIM

Delay to Reset Interrupt from
-lOR (RS MSR)

250

100 pF load

ClK
Cycles

Receiver
tSINT

Delay from Stop to Set Interrupt

tRINT

Delay from -lOR
(RD RBR/RDlSR) to Reset Interruot

Jls

Note 3
100 pF load

Parallel Port
tOT

Data Time

tSB

Strobe Time

tAD

Acknowledge Delay (Busy Start to Acknowledge)

JlS

Defined by Printer

tAKD

Acknowledge Delay (Busy End to Acknowledge)

Jls

Defined by Printer

tAK

Acknowledge Duration Time

JlS

Defined by Printer

tBSY

Busy Duration Time

JlS

Defined by Printer

tBSD

Busy Delay Time

JlS

Defined by Printer

Jls
500

Jls

Notes:
1. All timing specifications apply to pins on both serial channels (e.g. RI refers to both RIO and RI1).
2. The internal address strobe is always active.
3. RClK ... tXH and tXL.
4. Charge and discharge time is determined by VOL, VOH and the external loading.
5. All timings are referenced to valid 0 and valid 1 (see AC TEST POINTS).

VLSI TECHNOLOGY, INC.
VL16C451

WRITE CYCLE TIMING
A2 A1 AO

------------~VA~L7rID~--------:

VALID

-CS

tCSW.

-----------1~~

tA_W~~~~~~~:+t-----,-~------~)(~----~ACTIVE

______

~OW

-------------t-------(~~--~~ACTIVE

-lOR
tDS

DATA
00-07

I .. tDH~

------------~\VALID DATA }L----------

READ CYCLE TIMING
A2 A1 AO

VALID

-CS

VALID

"tRCS"

RC-------PJ~

tCSR.

tAR----4~---~~~_ _ _~)~~~---~_ACTIVE
..

-lOR -----------~

-lOW

---------+----l-----U~---------,VCTIVE

tODD
DATA
DO-D7

~~_ VALID
-

------------~

DATA

tHZ

~'--_ __

VLSI TECHNOLOGY, INC.
VL16C451

RECEIVER TIMING

SIN\

START ~TA BITS (5-8)

(RECEIVER
INPUT
DATA)

CLK
SAMPLE

~
JL--.l-~-~~L--L--..L-:t--==~~=----

INTERRUPT
(DATA READY OR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
RCVR ERR)

- - - - - - - - - - - - - - - - - - - - - - . \ ACTIVE
-lOR
,

ttR4-

TRANSMITTER TIMING
START _ _ _ _ _ __
SERIAL
OUT (SOUT)

DATA (5-8)
PARITY
+-tSTI

INTERRUPT
(THRE)
-lOW
(WRTHR) ___

~~~ ~
__

__________________________________•

-lOR
(RDIIR)

MODEM TIMING
-lOW

..JL

\-----~--

(WR MCR) ___

-CTS,-DSA,-RLSD

............

-RTS, -DTR

-+I~

\ ff
tMDO~

tMDO

-----+-_...J

-INTERRUPT _ _ _ _

-lOR
(RD MSR)

-RI

VLSI TECHNOLOGY. INC.
VL16C451

PARALLEL PORTTIMING
DATA

iDT~DT1=

-M

STROBE

-ACK
•

tAD - - - - - - 1

BUSY

AC TESTING INPUT/OUTPUT WAVEFORMS
EXTERNAL CLOCK INPUT
....

AC TEST POINTS

tXH

.tXL.

TEST CIRCUIT
2.54 V

Output Under Test

6800

• Includes Scope and Jig 82 pF"

Capacitance

VLSI TECHNOLOGY. INC.
VL16C451

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

-10°C to +?O°C

Storage Temperature -65°C to + 150°C
Supply Voltage to
Ground Potential -0.5 V to VCC + 0.3 V
Applied Output
Voltage
Applied Input
Voltage

-0.5

Vto + ?OV
500mW

DC CHARACTERISTICS:

=0 to +70°C, VCC =5 V ± 5%

Parameter

Min

Max

Units

VILX

Clock Input Low Voltage

-0.5

0.8

VIHX

Clock Input High Voltage

2.0

VCC

VIL

Input Low Voltage

-0.5

0.8

VIH

Input High Voltage

2.0

VCC

VOL

VOH

those indicated in this data sheet is not
implied. Exposure to absolute maximum
rating conditions for extended periods
may affect device reliability.

-0.5 V to VCC + 0.3 V

Power Dissipation

Symbol

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only, functional
operation of this device at these or any
other conditions above

Output Low Voltage

Output High Voltage

ICC

Power Supply Current

ilL

Input Leakage

ICL

Clock Leakage

IOZ

3-State Leakage

VIL(RES)

Reset Schmitt VIL

VIH(RES)

Reset Schmitt VIH

0.4

2.4

Conditions

IOL .. 4.0 mA on DBO - DB?
IOL .. 12 mA on PDO - PO?
IOL .. 10 mA on -NIT, -AFD, -STB,
and -SUN (see Note 1)
IOL.. 2.0 mA on all other outputs

IOH .. -0.4 mA on
IOH .. -2.0 mA on
IOH = -0.2 mA on
and -SUN
IOH .. -0.2 mA on

DBO - DB?
PDO - PO?
-IN IT, -AFD, -STB,
all other outputs

VCC = 5.25 V, No loads on SINO;
-DSRO; -RLSDO; -CTSO.
-RIO ... 2.0 V. Other inputs .. 0.8 V. Baud
rate generator = 4 MHz. Baud rate = 56K

±10

VCC = 5.25 V, GND .. 0 V.
All other pins floating.

±10

VIN .. 0 V, 5.25 V

VCC .. 5.25 V, GND = 0 V.
VOUT .. 0 V, 5.25 V
1) Chip deselected
2) Chip and write mode selected

±20

0.8
2.0

V
V

Note 1. -INIT, -AFD, -STB, and -SUN are open collector output pins that each have an internal pull-up resistor (2.5 kn - 3.5 kQ)
to VCC. This will generate a maximum of 2.0 mA of internallOL. In addition to this internal current, each pin will sink at least
10 mA, while maintaining the VOL specification of 0.4 V Max.

VLSI TECHNOLOGY, INC.

;,,\

VLSI TECHNOLOGY, INC.
VL16C452
DUAL ASVNCHRONOUS
COMMUNICATIONS ELEMENT

FEATURES

DESCRIPTION

• IBM PC/AT-compatible

The VL 16C452 is an enhanced dualchannel version of the popular
VL 16C450 asynchronous communications element (ACE). The device
serves two serial inpuVoutput interfaces
simultaneously in microcomputer- or
microprocessor-based systems. Each
channel performs serial·to-parallel
conversion on data characters received
from peripheral devices or modems, and
parallel-to-serial conversion on data
characters transmitted by the CPU. The
complete status of each channel of the
dual ACE can be read at any time during
functional operation by the CPU. The
information obtained includes the type
and condition of the transfer operations
being performed, and error conditions.

• Dual-channel version of VL 16C450
• Centronix printer interface
• Independent control of transmit,
receive, line status and data set
interrupts on each channel
• Individual modem control signals for
each channel
• Programmable serial interface
characteristics for each channel:
- 5-,6-,7- or a-bit characters
- Even-, odd- or no-parity bit
generation and detection
-1, 1 1/2 or 2 stop bit generation
• Three-state TTL drive for the data and
control bus on each channel

PIN DIAGRAM

A programmable baud rate generator is
included that can divide the timing
reference clock input by a divisor
between 1 and (2 16 -1).
The VL 16C452 is housed in a
6a-terminal plastic leaded chip carrier.

BLOCK DIAGRAM
VL16C452

-ASLDI -All

In addition to its dual communications
interface capabilities, the VL 16C452
provides the user with a fully bidirectional parallel data port that fully
supports the parallel Centronics type
printer. This port allows information
received from either serial communication port to be printed from the dual
ACE. The parallel port, together with the
two serial ports, provide IBM PC/ATcompatible computers with a single
device to serve the three system ports.

CLK

GND

-ACK BUSY

vee

-CTSO
-OSRO
-ALSDO
-RIO
SINO
-eso

SINl

SOUTI
-DTRI

INTI
INT2 OBO· OB7

-AlSl

-ATSO
-OTRO
SOUTO
INTO

UART
#1

-SUN

-CTSI

B,V

-INIT

oeo

-MO

OBI

-5TB

OB2

GND

OB3

POO

DB4

POI

DBS

P02

OB6

P03

OB7

P04

GNO

PDS

vee

PD6

-AlSO

P07

-DTRO

INTO

SOUTO

BOO

vee

AO-A2
SELECT
-lOW
AND
-lOR
CONTROL
-AESET ---'-+ lOGIC
ClK ---'-+

::::

....
BOO

/'B
B/

-..
-eRR
SLCT
BUSY

PARALLEL
PORT

-ACK
-LPTOE
-eS2

GNO

-RTSI
-OrR 1
SOUT1
INT1

UART

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 4243

-CS2

-CTSI
-OSRI
-ALSOI
-Rll
SINl
-CSI

PDO·P07
-lNIT

-/\FO

-STB
-SUN
INT2

ORDER INFORMATION
Part
Number

Maximum
Clock Frequency

VL 16C452-QC

3.1 MHz

Package
Plastic Leaded Chip Carrier (PLCC)

Note: Operating temperature range is O°C to +70°C.

VLSI TECHNOLOGY, INC.
VL16C452

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Description

-lOR

Input/Output Read Strobe - This is an active low input which causes the selected channel
to output data to the data bus (OBO-OB7). The data output depends upon the register
selected by the address inputs AO, A 1, A2. Chip Select 0 (-CSO) selects UART #1, Chip
Select 1 (-CS1) selects UART #2, and Chip Select 2 (-CS2) selects the line printer port.

-lOW

Input/Output Write Strobe - This is an active low input which causes data from the data
bus (OBO-OB7) to be input to either UART or to the parallel port. The data input depends
upon the register selected by the address inputs AO, A 1, A2. The chip select inputs
(-CSO, -CS1, and -CS2) enable UART#1, UART #2, and the parallel port (respectively).

OBO-OB7

14-21

Data Bits OBO-OB7 - The Data Bus provides eight, three-state I/O lines for the transfer of
data, control and status information between the Vl16C452 and the CPU. These lines are
normally in a high-impedance state except during read operations. DO is the least
significant bit (lSB) and is the first serial data bit to be received or transmitted.

AO, A1, A2

35,34,33

ClK

Clock Input: The external clock input to the baud rate divisor of each UART.

SOUTO,
SOUT1

26,10

Serial Data Outputs - These lines are the serial data outputs from the UARTs' transmitter
circuitry. A mark (1) is a logic "one" (high) and space (0) is a logic "zero" (low). Each
SOUT is held in the mark condition when the transmitter is disabled, Reset is true, the
Transmiter Register is empty, or when in the loop Mode.

-CTSO, -CTS1

28, 13

Clear to Send Inputs - The logical state of each -CTS pin is reflected in the CTS bit of the
(MSR) Modem Status Register [CTS is bit 4 of the MSR, written MSR (4)] of each UART.
A change of state in either -CTS pin since the previous reading of the associated MSR
causes the setting of OCTS [MSR(O)] of each Modem Status Register. When a -CTS pin
is low, the modem is indicating that data on the associated SOUT can be transmitted.

OSRO,OSR1

31,5

Data Set Ready Inputs - The logical state of the OSR pins is reflected in MSR(5) of its
associated Modem Status Register. OOSR [MSR(1)] indicates whether the associated
OSR pin has changed state since the previous reading of the MSR. When a OSR pin is
low, its modem is indicating that it is ready to exchange data with the associated UART.

OTRO,OTR1

25,11

Data Terminal Ready Lines - Each OTR pin can be set (low) by writing a logic 1 to
MCR(O), Modem Control Register bit 0 of its associated UART. This signal is cleared
(high) by writing a logic 0 to the OTR bit [MCR(O)] or whenever a reset occurs. When
active (low), the OTR pin indicates to the OCE that its UART is ready to receive data.

-RTSO, -RTS1

24, 12

Request to Send Outputs - The -RTS signal is an output on each UART used to enable
the modem. An -RTS pin is set low by writing a logic 1 to MCR(1) bit 1 of its UARTs
Modem Control Register. Both -RTS pins are reset high by Reset. A low on the -RTS
pin indicates to the OCE that its UART has data ready to transmit. In half duplex
operations, -RTS is used to control the direction of the line.

-RIO, -R11

30,6

Ring Indicator Inputs - When low, -RI indicates that a telephone ringing signal has been
received by the modem or data set. The -RI signal is a modem control input whose
condition is tested by reading MSR(6) (RI) of each UART. The Modem Status Register
output TERI [MSR(2)] indicates whether the RI input has changed from high to low since
the previous reading of the MSR. If the interrupt is enabled [IER(3)-1] and RI changes
from a high to low, an interrupt is generated.

-lPTOE

Parallel Data Output Enable - When low, this signal enables the Write Data Register to
the POO - P07 lines. A high puts the POO - P07 lines in the high-impedence state allowing
them to be used as inputs. -lPTOE is usually tied low for line printer operation.

VCC

23,40,64

Power Supply - The power supply requirement is 5 V ±5%.

GNO

2, 7, 9, 22, 27,
42,43,54,61

Ground (0 V) - All pins must be tied to ground for proper operation.

VLSI TECHNOLOGY, INC.
VL16C452

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Desalptlon

-RLSOO,
-RLS01

29,8

Receive Line Signal Detect - When low, the -RLSO output indicates that the data carrier
has been detected by the modem or data set. -RLSO is a modem input whose condition
can be tested by the CPU by reading MSR(7) (RLSO) of the Modem Status Registers.
MSR(3) (ORLSO) of the Modem Status Register indicates whether the -RLSO input has
changed since the previous reading of the MSR. -RLSO has no effect on the receiver. If
the -ALSO changes state with the modem status interrupt enabled, an interrupt occurs.

-RESET

Reset - When low, the reset input forces the VL 16C452 into an idle mode in which all
serial data activities are suspended. The Modem Control Register (MCR) along with its
associated outputs are cleared. The Line Status Register (LSR) is cleared except for the
THRE and TEMT bits, which are set. All functions of the device remain in an idle state
until programmed to resume serial data activities.

INTO,INT1

45,60

Serial Channel Interrupts - Each three-state, serial channel interrupt output (enabled by
bit 3 of the MCR) goes active (high) when one of the following interrupts has an active
(high) condition and is enabled by the Interrupt Enable Register of its associated channel:
Receiver Error flag, Received Data Available, Transmitter Holding Register Empty, and
Modem Status. The interrupt is reset low upon appropriate service or a reset operation.

SINO, SIN1

41,62

Serial Data Inputs - The serial data inputs move information from the communication line
or modem to the VL 16C452 receiver circuits. A mark (1) is high, and a space (0) is low.
Data on serial data inputs is disabled when operating in the loop mode.

-CSO,-CS1,
-CS2

32,3,38

Chip Selects - Each Chip Select input acts as an enable for the write and read signals
for the serial channels 0 (-CSO) and 1 (-CS1). -CS2 enables the the signals to the line
printer port.

BOO

Bus Buffer Output - This active high output is asserted when either serial channel or the
parallel port is read. This output can be used to control the system bus driver device
(74LS245).

POO-P07

53-46

Parallel Data Bits (0-7) - These eight lines provide a byte-wide input or output port to the
system. The eight lines are held in a high-impedance state when -LPTOE is held in the
high state.

-STB

Line Printer Strobe - This open-drain line provides communication between the
VL 16C452 and the line printer. When it is active low, it provides the line printer with a
signal to latch the data currently on the parallel port.

-AFO

Line Printer Autofeed - This open-drain line provides the line printer with an active low
signal when continuous form paper is to be autofed to the printer.

-INIT

Line Printer Initialize: This open-drain line provides the line printer with a signal that
allows the line printer initialization routine to be started.

-SUN

Line Printer Select: This open-drain line selects the printer when it is active low.

INT2

Printer Port Interrupt - This signal is an active high, three-state output, generated by the
positive transition of -ACK. It is enabled by bit 4 of the Write Control Register.

-ERROR

Line Printer Error - This is an input line from the line printer. The line printer reports an
error by holding this line low during the error condition.

SLCT

Line Printer Selected - This is an input line from the line printer that goes high when the
line printer has been selected.

BUSY

Line Printer Busy - This is an input line from the line printer that goes high when the line
printer is not ready to accept data.

Line Printer Paper Empty - This is an input line from the line printer that goes high when
the printer runs out of paper.

-ACK

Line Printer Acknowledge - This input goes low to indicate a successful data transfer has
taken place. It generates a printer port interrupt during its pos~ive transition.

"VLSI TECHNOLOGY, INC.
VL16C452
FUNCTIONAL
DESCRIPTION:
SERIAL CHANNEL REGISTERS
Three types of internal registers are
used in each serial channel of the
Vl16C452. They are used in the
operation of the device, and are the
control, status, and data registers. The
control registers are the Bit Rate Select
Register Dll (Divisor latch lSB) and
DlM (Divisor latch MSB), Line Control
Register, Interrupt Enable Register, and
the Modem Control registers, while the
status registers are the Line Status
Registers and the Modem Status
Register. The data registers are the
Receiver Buffer Register and the
Transmitter Holding Register. The
Address, Read, and Write inputs are
used in conjunction with the Divisor
latch Access Bit in the Line Control
Register [LCR(7)] to select the register
to be written or read (see Table 1).
Individual bits within these registers are
referred to by the register mnemonic
and the b~ number in parenthesis. An
example, LCR(7) refers to Line Control
Register Bit 7.
The Transmitter Buffer Register and
Receiver Buffer Register are data
registers holding from five to eight bits
of data. If less than eight data bits are
transmitted, data is right justified to the

lSB. Bit 0 of a data word is always the
first serial data bit received and
transmitted. The Vl 16C452 data
registers are double-buffered so that
read and write operations can be
performed at the same time the UART
is performing the parallel-to-serial and
serial-to-par,allel conversion.
The format of the data character is
controlled by the Line Control Register.
The contents of the lCR may be read,
eliminating the need for separate
storage of the line characteristics in
system memory. The contents of the
lCR are described below:
lCR (0) Word length Select Bit 0
(WlSO)
lCR (1) Word length Select Bit 1
(WlS1)
lCR (2) Stop Bit Select (STB)
lCR (3) Parity Enable (PEN)
lCR (4) Even Parity Select (EPS)
lCR (5) Stick Parity
lCR (6) Set Break
lCR (7) Divisor latch Access Bit
(DLAB)
lCR (0) and lCR(1) word length select
bit 1: The number of bits in each serial
character is programmed as shown in
the following chart:

TABLE 1.SERIAL CHANNEL INTERNAL REGISTERS
DLAB

Mnemonic

RBR

Receiver Buffer Register (read only)

THR

Transmitter Holding Register (write only)

IER

Interrupt Enable Register

IIR

Interrupt Identification Register (read only)

lCR

Line Control Register

X
X
X

MCR

Modem Control Register

lSR

Line Status Register

MSR

Modem Status Register

SCR

Scratch Register

Dll

Divisor latch (lSB)

DlM

Divisor latch (MSB)

LCR(1)

LCR(O)

o
o

0
1

1
1

0
1

Word Length
5
6
7
a

Bits
Bits
Bits
Bits

lCR(2) Stop Bit Select: lCR(2)
specifies the number of stop bits in each
transmitted character. If lCR(2) is a
logic 0, one stop bit is generated in the
transmitted data. If lCR(2) is a logic 1
when a 5-bi1 word length is selected, 1.5
stop bits are generated. If lCR(2) is a
logic 1 when either a 6-, 7-, or a-bit word
length is selected, two stop bits are
generated. The receiver checks for two
stop bits if programmed.
lCR(3) Parity Enable: When lCR(3) is
high, a parity bit between the last data
word bit and stop bit is generated and
checked.
lCR(4) Even Parity Select: When parity
is enabled [lCR(3)=1], lCR(4)-0 selects
odd parity, and LCR(4)-1 selects even
parity.
lCR(5) Stick Parity: When parity is
enabled [lCR(3)-1], ClR(5)",1 causes
the transmission and reception of a
parity bit to be in the opposite state from
that indicated by LCR(4). This allows
the user to force parity to a known state
and for the receiver to check the parity
bit in a known state.
lCR(6) Break Control: When lCR(6) is
set to a logic "1 ", the serial output
(SOUT) is forced to the spacing (logic 0)
state .. The break is disabled by setting
LCR(6) to a logic "0". The Break Control
bit acts only on SOUT and has no effect
on the transmitter logic. Break Control
enables the CPU to alert a terminal in a
computer communications system. If
the following sequence is used, no
erroneous or extraneous characters will
be transmitted because of the break.
1. Load an all "O"s pad character in
response to THRE.
2. Set break in response to the next
THRE.

X - "Don't Care"
0 .. logic low
1 .. logic High
Note: Serial Channel 0 is accessed when -CSO is low; Serial Channel 1 is accessed
when -CS1 is low. Selecting both channels simultaneously is an invalid condition.

3. Wait for the transmitter to be idle
(TEMT-1), and dear break when
normal transmission has to be
restored.

VLSI TECHNOLOGY, INC.
VL16C452

FIGURE 1. UNE CONTROL REGISTER

Word
L . . - _ " , Length
Select

o
o

0
5 Data Bits
1 = 6 Data Bits
1 0 = 7 Data Bits
1 1
8 Data Bits

_ _ _--4~Stop
o = 1 Stop Bit
Bit Select 1 = 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits If 6, 7, 8 Data Bits Selected
"-_ _ _ _ _ _• Parity
o = Parity Disabled
Enable
1 = Parity Enabled
~

"-_ _ _ _ _ _ _... Even
Parity
Select
Stick
' - - - - - - - - - - -... Parity

Break
" - - - - - - - - - - - -... Control

Divisor
'---------------------·Lat~

o = Odd Parity
1 = Even Parity

Stick Parity Disabled
1 = Stick Parity Enabled

o = Break Disabled
1 = Break Enabled

o ==

Access Receiver Buffer
1 = Access Divisor Latches

Access
Bit
LCR(7) Divisor Latch Access Bit
(DLAB): LCR(7) must be set high (logic
"1") to access the Divisor Latches DLL
and DLM of the Baud Rate Generator
during a read or write operation.
LCR(7) must be input low to access the
Receiver Buffer, the Transmitter
Holding, or the Interrupt Enable
Registers.
The Line Status Register (LSR) is a
single register that provides status
indications. The LSR is usually the first
register read by the CPU to determine
the cause of an interrupt or to poll the
status of each serial channel of the
VL16C452.
Three error flags OE, FE, and PE
provide the status of any error conditions detected in the receiver circuitry.
During reception of the stop bits, the
error flags are set high by an error
condition. The error flags are not reset
by the absence of an error condition in
the next received character. The flags
reflect the iast character only if no
overrun occurred. The Overrun Error

indicates that the Transmitter Shift
Register is empty, and the serial
channel has completed transmission of
the last character to be sent. If the
interrupt is enabled [IER(1)], an active
THRE causes an interrupt (INTRPn.
The Data Ready (DR) bit indicates that
the RBR has been loaded with a
received character (including Break)
and that the CPU may access this data.
Reading the LSR clears LSR(1)LSR(4). (OE, PE, FE, and BI.)
The contents of the Line Status
Register shown in Table 2 are described below:
LSR(O) Data Ready (DR): Data Ready
is set high when an incoming character
has been received and transferred into
the Receiver Buffer Register. lSR(O) is
reset low by a CPU read of the data in
the Reciever Buffer Register.
lSR(1) Overrun Error (OE): Overrun
Error indicates that data in the Receiver
Buffer Register was not read by the
CPU before the next character was

VLSI TECHNOLOGY, INC.
VL16C452

TABLE 2. LINE STATUS REGISTER BITS
LSRBITS

Logic 1

logic 0

LSR(O) Data Ready (DR)

Ready

Not Ready

LSR (1) Overrun Error (OE)

Error

No Error

LSR (2) Parity Error (PE)

Error

No Error

LSR (3) Framing Error (FE)

Error

No Error

LSR (4) Break Interrupt (BI)

Break

No Break

LSR (5) Transmitter Holding Register Empty (THRE)
LSR (6)

Transm~ter

Empty (TEMT)

Empty "

Not Empty

Empty

Not Empty

LSR(7) Not Used

transferred into the Receiver Buffer
Register, overwriting the previous
character. The OE indicator is reset
whenever the CPU reads the contents
of the Line Status Register.
LSR(2) Parity Error (PE): Parity Error
indicates that the received data
character"does not have the correct
even or odd par~y, as selected by the
Even Parity Select bit (LCR(4)). The
PE bit is set high upon detection of a
parity error, and is reset low when the
CPU reads the contents of the LSR.
LSR(3) Framing Error (FE): Framing
Error indicates that the received
character did not have a valid stop b~.
LSR(3) is set high when the stop bit
following the last data b~ or parity b~ is
detected as a zero bit (spacing level).
The FE indicator is reset low when the
CPU reads the contents of the LSR.
LSR(4) Break Interrupt (BI): Break
Interrupt is set high when the received
data input is held in the spacing (logic
0) state for longer than a full word
transmission time (start b~ + data b~s +
pairty + stop b~s). The BI indicator is
reset when the CPU reads the contents
of the Line Status Register.
LSR(1) - LSR(4) are the error conditions that produce a Reciever Line
Status interrupt (priority 1 interrupt in
the Interrupt Identification Register
(IIR)) when any of the conditions are
detected. This interrupt is enabled by
setting IER(2)=1 in the Interrupt Enable
Register.
LSR(5) Transmitter Holding Register
Empty (THRE): THRE indicates that
the VL82C50A is ready to accept a new
character for transmission. The THRE

MCR(1): When MCR(1) is set high, the
RTS output is forced low. Whe MCR(1)
is reset low, the -RTS output is forced
high. The -RTS output of the serial
channel may be input into an inverting
line driver in order to obtain the proper
polarity input at the modem or data set.

When the THRE interrupt is enabled
(IER(1 )-1). THRE causes a prior~y 3
interrupt in the IIR. If THRE is the
interrupt source indicated in IIR,
INTRPT is cleared by a read of the IIR.

MCR(3): When MCR(3) is set high, the
INT output is enabled.

LSR(6) Transmitter Empty (TEMT):
TEMT is set high when the Transmitter
Holding Register (THR) and the
Transmitter Shift Register (TSR) are
both empty. LSR(6) is reset low when
a character is loaded into the THR and
remains low until the character is
transferred out of SOUTo TEMT is not
reset low by a CPU read of the LSR.
LSR(7): This b~ is always O.
The Modem Control Register (MCR)
controls the interface with the modem
or data set as described in Table 3.

MCR(4): MCR(4) provides a local
loopback feature for diagnostic testing
of the channel. When MCR(4) is set
high, Serial Output (SOUT) is set to the
marking (logic "1") state, and the
receiver data input Serial Input (SIN) is
disconnected. The output of the
Transm~ter Shift Register is looped
back into the Receiver Shift Register
input. The three modem control inputs
(--CTS, -DSR, and -RI) are disconnected. The modem control outputs
(-DTR and -RTS) are internally connected to the four modem control
inputs. The modem control output pins
are forced to their inactive state (high).

TABLE 3. MODEM CONTROL REGISTER BITS
MeR BITS

Logic 1

Logic 0

MCR (0) DataTerminal Ready (DTR)

-DTR Output Low

-DTR Output High

MCR (1) Request to Send (RTS)

-RTS Output Low

-RTS OutputHigh

INT Enabled

INT Disabled

Loop Enabled

Loop Disabled

MCR (2) 0
MCR (3) Interrupt (INT) Enable
MCR (4) LOOP
MCR (5) 0
MCR (6) 0
MCS (7) 0

VLSI TECHNOLOGY, INC.
VL16C452

FIGURE 2. MODEM CONTROL REGISTER
Modem Control Register (MCR)

Data
Terminal
Ready

0
1

= -oTR Output High (Inactive)

Request
' - - - -.... To Send

= -ATS Output High (Inactive)
= -ATS Output Low (Active)

'------'~

= -oTR Output Low (Active)

Not Connected

o = INT Disabled

~------------~ INT

o=
1 =

~--------. LOOP

INT Enabled
LOOP Disabled
LOOP Enabled

' - - - - - - - - - - - - - - - - . These Bits are Permanently Set to Logic "0".
In the diagnostic mode, data transmitted is immediately received. This
allows the processor to verify the
transmit and receive data paths of the
selected serial channel. Bits MCR(S) MCR(7) are permanently set to logic O.
The MSR provides the CPU with status
of the modem input lines from the
modem or peripheral devices. The MSR
allows the CPU to read each of the
serial channel modem signal inputs by
accessing the data bus interface of the
VL 16C4S2. In addition to the current
status information, four bits of the MSR
indicate whether the modem inputs have
changed since the last reading of the
MSR. The delta status bits are set high
when a control input from the modem
changes state, and reset low when the
CPU reads the MSR.
The modem input lines for each channel
are -CTS, -DSR, -RI, and -ALSO.
MSR(4) - MSR(7) are status indications
of these lines. The status indications
follow the status of the input lines. If the
modem status interrupt in the Interrupt
Enable Register is enabled [IER(3»), a
change of state in a modem input
signals will be reflected by the modem
status bits in the IIR register, and an
interrupt (INTRPT) is generated. The
MSR is a priority 4 interrupt. The
contents of the Modem Status Register
are described in Table 4. Note that the
state (high or low) of the status bits are

inverted versions of the actual input
pins.
MSR(O) Delta Clear to Send (DCTS):
DCTS indicates that the -CTS input to
the serial channel has changed state
since the last time it was read by the
CPU.
MSR(1) Delta Data Set Ready (DDSR):
DDSR indicates that the -DSR input to
the serial channel has changed state
since the last time it was read by the
CPU.
MSR(2) Trailing Edge of Ring Indicator
(TERI): TERI indicates that the -RI
input to the serial channel has changed
state from high to low since the last
time it was read by the CPU. Low to
high transitions on -AI do not activate
TERI.
MSR(3) Delta Data Carrier Detect
(DRSLD): DRSLD indicates that the

-RSLD input to the serial channel has
changed state since the last time it was
read by the CPU.
MSR(4) Clear to Send (CTS): Clear to
Send (CTS) is the status of the -CTS
input from the modem indicating to the
serial channel that the modem is ready
to receive data from the serial channel's--i
transmitter output (SOUT). If the serial
channel is in loop mode [MSR(4)-1].
MSR(4) is equivalent to -ATS in the
MCR.
MSR(S) Data Set Ready (DSR): Data
Set Ready (DSR) is a status of the
-DSR input from the modem to the
serial channel which indicates that the
modem is ready to provide received
data to the serial channel receiver
circuitry. If the channel is in the loop
mode [MCR(4)-1]. MSR(S) is equivalent to the DTR in the MCR.

TABLE 4. MODEM STATUS REGISTER BITS
MSR Bit
MSR
MSR
MSR
MSR
MSR
MSR
MSR
MSR

(1)
(2)
(0)
(3)
(4)
(S)
(6)
(7)

Mnemonic
DDSR
TERI
DCTS
DRLSD
-CTS
-DSR
-RI
-RLSD

Description
Delta Data Set Ready
Trailing Edge of Ring Indicator
Delta Clearto Send
Delta Data Carrier Detect
Clear To Send
Data Set Ready
Ring Indicator
Receiver Line Signal Detect

·_

VLSI TECHNOLOGY, INC.
VL16C452

MSR(S) Ring Indicator: Indicates the
status fo the RI input (pin 39). If the
channel is in the loop mode
[MCR(4)=1], MSR(S) is not connected
in the MCR.
MSR(7) Receive Line Signal Detect :
Receive Line Signal Detect indicates
the status of the Receive Line Signal
Detect (-RLSD) input. If the channel is
in t~e loop mode [MCR(4)-1], MSR(4) is
equivalent to OUT2 of the MCR.
The modem status inputs (-RI, -RLSD,
-DSR, and -CTS) reflect the modem
input lines with any change of status.
Reading the MSR register will clear the
delta modem status indications but has
no effect on the status bits. The status
bits reflect the state of the input pins
regardless of the mask control signals.
If a DCTS, DDSR, TERI, or DRLSD are
true, and a state change occurs during
a read operation (-lOR), the state
change is not indicated in the MSR. H
DCTS, DDSR, TERI, or DRLSD are
false, and a state change occurs during
a read operation, the state change is
indicated after the read operation.
For LSR and MSR, the setting of status
bits is inhibited during status register
read -lOR operations. If a status
condition is generated during a read
-lOR operation, the status bit is not set
until the trailing edge of the read
-lOR.
If a status bitis set during a read
-lOR operation, and the same status
conditionoccurs, that status bit will be
cleared at the trailing edge of the read
-lOR instead of being set again.
Each VL 16C452 serial channel contains
a programmable Baud Rate Generator
(BRG) that divides the clock (DC to
3.1 MHz) by any divisor from 1 to 2 IS-I
(see also BRG description). The output
frequency of the Baud Generator is 1SX
the data rate [divisor # = clock + (baud
rate x 1S)]. Two 8-bit divisor latch
registers store the divisor in a 1S-bit
binary format. These Divisor Latch
~e.g.is~ers. must be loaded during
Initialization. Upon loading either of the
Divisor latches, a 1S-bit baud counter is
immediately loaded. This prevents long
counts on initial load.
The receiver circuitry in each serial
channel ofthe VL 16C452 is programmable for 5, S, 7, or 8 data bits per

character. For words of less than 8
bits, the data is right justified to the
least significant bit LSB .. Data Bit 0
[RBR(O)]. Data Bit 0 of a data word
[RBR(O)] is the first data bit received.
The unused bits in a character less than
8 bits are output low to the parallel
output by the serial channel.
Received data at the SIN input pin is
shifted into the Receiver Shift Register
by the 1SX clock provided at the RCLK
input. This clock is synchronized to the
incoming data based on the position of
the start bit. When a complete character is shifted into the Receiver Shift
Register, the assembled data bits are
parallel loaded into the Receiver Buffer
Register. The DR flag in the LSR
register is set.
Double buffering of the received data
permits continuous reception of data
without losing received data. While the
Receiver Shift Register is shifting a new
character into the serial channel the
Receiver Buffer Register is holdi'ng a
previously received character for the
CPU to read. Failure to read the data in
the RBR before complete reception of
the next character result in the low of
the data in the Receiver Register. The
OE flag in the LSR register indicates
the overrun condition.
RBR Bits 0 thru 7:
RBR(O)
RBR(1)
RBR(2)
RBR(3)
RBR(4)
RBR(5)
RBR(S)
RBR(7)

Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7

The Transmitter Holding Register (THR)
holds parallel data from the data bus
(00-07) until the Transmitter Shift
Register is empty and ready to accept a
new character for transmission. The
transmitter and receiver word length
and number of stop bits are the same.
If the character is less than eight bits,
unused bits at the microprocessor data
bus are ignored by the transmitter.
Data Bit 0 [THR(O)] is the first serial
data bit transmitted. The THRE flag
[LSR(5)] reflect the status of the THR.
The TEMT flag [LSR(5)] indicates if
both the THR and TSR are empty.

THR Bits 0 thru 7
THR(O)
THR(1)
THR(2)
THR(3)
THR(4)
THR(5)
THR(S)
THR(7)

Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7

Scratch pad Register is an 8-bit Read!
Write re~ister that has no effect on any
channel In the VL 1SC452. It is intended
to be used by the programmer to hold
data termporarily.
SCR Bits 0 thru 7
SCR(O)
SCR(1)
SCR(2)
SCR(3)
SCR(4)
SCR(5)
SCR(S)
SCR(7)

Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7

INTERRUPTS
The Interrupt Identification Register
(IIR) of each serial channel of the
~L 1S~2 has interrupt capability for
Interfacing to current microprocessors.
In order to minimize software overhead
during data character transfers the
serial channel prioritizes interr~pts into
four levels. The four levels of interrupt
conditions are as follows:
1. Rece~ver Line Status (priority 1)
2. Received Data Ready (priority 2)
3. Transmitter Holding Register Empty
(priority 3)
4. Modem Status (priority 4)
Information indicating that a prioritized
interrupt is pending and the type of
interrupt is stored in the Interrupt
Identification Register (IIR). When
addressed during chip select time the
~IR indicates the highest priority ,
Interrupt pending. No other interrupts
are acknowledged until the interrupt is
serviced by the CPU. The logic equivalent of the interrupt control circuit is
shown in Figure 3. The contents of the
IIR are indicated in Table 5 and are
described below.
IIR(O): IIR(O) can be used in either a
hard-wi~ed prioritized or polled environment to indicate whether an interrupt is
pending. When IIR(O) is low, an
interrupt is pending, and IIR contents

VLSI TECHNOLOGY, INC.
VL16C452

TABLE 5. INTERRUPT IDENTIFICATION REGISTER
INTERRUPT IDENTIFICATION

INTERRUPT SET AND RESET FUNCTIONS

Priority
Level

Interrupt
Flag

Interrupt
Source

None

First

Receiver
Line Status

OE,PE
FE, or BI

LSR Read

Second

Received Data
Available

RBR Read

Third

THRE

IIR Read if THRE is the
Interrupt Source or THR Wr~e

Fourth

Modem Status

-CTS,-DSR
-RI,-RSLD

MSR Read

Bit 2

Bit 1

Bit 0

X - Not Defined.

FIGURE 3. INTERRUPT CONTROL LOGIC

DR (LSR BIT o)-------r--~
ERBFI (IER BIT 0)-----...1

THRE (LSR BIT 51--_ _ _ _~
ETBEI (IER BIT 1 ' 1 - - - - - - - - 1
OE (LSR BIT 1)
PE (LSR BIT 2)
FE (LSR BIT 3)
BI (LSR BIT 4)
ELSI (IER BIT 1)

----...I

DCTS (MSR BIT 0
DDSR (MSR BIT 1
TERI (MSR BIT 2)
DDCD (MSR BIT 3
EDSSI (IER BIT 3 ) - - - - . . . 1
Interrupt Enable (MCR BIT 3) _ _ _ _ _ _ _ _ _ _ _ _ _ _--01

Interrupt
Reset Control

VLSI TECHNOLOGY, INC.
VL16C452

TABLE 6. SERIAL CHANNEL ACCESSIBLE REGISTERS
Register
Mnemonic

Bit 6

Blt5

Blt4

Bit 3

Bit 2

Bit 1

Bit 0

RBR
(Read Only)

Data
Bit?
(MSB)

Data
Bit 6

Data
BitS

Data
Bit 4

Data
Bit 3

Data
Bit 2

Data
Bit 1

Data
Bit 0
(LSB)*

THR
(Write Only)

Data
Bit?

Data
Bit 6

Data
BitS

Data
Bit 4

Data
Bit 3

Data
Bit 2

Data
Bit 1

Data
Bit 0

DLL

Bit?

Bit 6

BitS

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DLM

Bit 1S

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

BitS

IER

(EDSSI)
Enable
Modem
Status
Interrupt

(ELSI)
Enable
Receiver
Line
Status
Interrupt

(ETBEI)
Enable
Transmitter
Holding
Register
Empty
Interrupt

(ERBFI)
Enable
Received
Data
Available
Interrupt

IIR
(Read Only)

Interrupt

Bit (1)

Bit (0)

"OR 1F
Interrupt
Pending

LCR

(DLAB)
Divisor
Latch
Access
Bit

Set
Break

Stick
Parity

(EPS)
Even
Parity
Select

(PEN)
Parity
Enable

(STB)
Number
of Stop
Bits

(WLSB1)
Word
Length
Select
Bit 1

(WLSBO)
Word
Length
Select
Bit 0

MCR

Loop

Out 2

Out 1

(RTS)
Request
To
Send

(DTR)
Data
Terminal
Ready

LSR

(TEMT)
Transmitter
Empty

(THRE)
Transmitter
Holding
Register
Empty

(BI)
Break
Interrupt

(FE)
Framing
Error

(PE)
Parity
Error

(OE)
Overrun
Error

(DR)
Data
Ready

MSR

(DCD)
Data
Carrier
Detect

(RI)
Ring
Indicator

(DSR)
Data
Ready
Set

(CTS)
Clear
to
Send

(DRSLD)
Delta
Receive
Line Signal
Detect

(TERI)
Trailing
Edge
Ring
Indicator

(DDSR)
Delta
Data
Set
Ready

(DCTS)
Delta
Clear
·to
Send

SCR

Bit 7

Bit 6

BitS

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

*LSB Data Bit 0 is the first bit transmitted or received.

VLSI TECHNOLOGY, INC.

may be used as a pointer to the appropriate interrupt service routine. When
IIR(O) is high, no interrupt is pending.
IIR(1) and IIR(2) are used to identify the
highest priority interrupt pending as
indicated in Table 2.
IIR(3) - IIR(7): These five bits of the IIR
are logic O.
The Interrupt Enable Register (IER) is a
Write register used to independently
enable the four serial channel interrupts
which activate the interrupt (INTRPT)
output. All interrupts are disabled by
resetting IER(O) - IER(3) of the Interrupt
Enable Register. Interrupts are enabled
by setting the appropriate bits of the IER
high. Disabling the interrupt system
inhibits the Interrupt Identification
Register and the active (high) INTRPT
output. All other system functions
operate in their normal manner, including the setting of the Line Status and
Modem Status Registers. The contents
of the Interrupt Enable Register is described in Table 3 and below:
IER(O): When programmed high
[IER(O} ... Logic 1], IER(O} enables
Received Data Available interrupt.
IER(1}: When programmed high
[IER(1)=Logic 1], IER(1) enables the
Transmitter Holding Register Empty
interrupt.
IER(2): When programmed high
[IER(2}=Logic 1], IER(2) enables the
Receiver line Status interrupt.
IER(3): When programmed high
[IER(3) .. Logic 1], IER(3) enables the
Modem Status Interrupt.
IER(4) - IER(7): These four bits of the
IER are logic O.
TRANSMIITER
The serial transmitter section consists of
a Transmitter Holding Register (THR),
Transmitter Shift Register (TSR), and
associated control logic. The Transmitter Holding Register Empty (THRE) and
Transmitter Shift Register Empty
(TEMT) are two bits in the Line Status
Register which indicate the status of
THR and TSR. To transmit a 5- to 8-bit
word, the word is written through 00-07
to the THR. The microprocessor should
perform a write operation only if TJiRE is
high. The THRE is set high when the
word is automatically transferred from

VL16C452
the THR to the TSR during the transmission of the start bit.
When the transmitter is idle, THRE and
TEMT are high. The first word written
causes THRE to be reset to O. After the
transfer, THRE returns high. TEMT
remains low for at least the duration of
the transmission of the data word. H a
second character is transmitted to the
THR, the THRE is reset low. Since the
data word cannot be transferred from the
THR to the TSR until the TSR is empty,
THRE remains low until the TSR has
completed sending the word. When the
last word has been transmitted out of the
TSR, TEMT is set high. THRE is set
high one THR to TSR transfer time later.
RECEIVER
Serial asynchronous data is input into
the SIN pin. The idle state of the line
providing the input into SIN is high. A
start bit detect circuit continually
searches for a high to low transiticm from
the idle state. When the transition is
.
detected, a counter is reset, and counts
the 16X clock to 7 1/2, which is the
center of the start bit. The start bit is
valid if the SIN is still low at the mid-bit
sample of the start bit. Verifying the
start bit prevents the receiver from
assembling a false data character due to
a low going noise spike on the SIN input.
The Line Control Register determines
the number of data bits in a character
(LCR(O), LCR(1», number of stop bits
LCR(2}, if parity is used LCR(3), and the
polarity of parity LCR(4). Status for the
receiver is provided in the Line Status
Register to the Receiver Buffer Register,
the Data Received indication in LSR(O)
is set high. The CPU reads the Receiver
Buffer Register through 00-07. This
read resets LSR(O}. If 00-07 are not
read prior to a new character transfer
from the RSR to the RBR, the overrun
error status indication is set in LSR(1).
The parity check tests for even or odd
parity on the parity bit, which precedes
the first stop bit. Hthere is a parity error,
the parity error is set in LSR(2). There is
circuitry which tests whether the stop bit
is high. Hit is not, a framing error
indication is generated in LSR(3}.
The center of the start bit is defined as
clock count 7112. If the data into SIN is
symmetrical square wave, the center of
the data cells will occur within

+/- 3.125% of the actual center,
providing an error margin of 46.875%.
The start bit can begin as much as one
16X clock cycle prior to being detected.
BAUD RATE GENERATOR (BRG)
The BRG generates the clocking for the
UART function, providing standard
ANSI/CCITT bit rates. The oscillator
driving the BRG is provided by an
external clock into CLK.
The data rate is determined by the
Divisor Latch registers DLL and DLM
and the external frequency. The bit rate
is selected by programming the two
divisor latches, Divisor Latch Most
Significant Byte and Divisor Latch Least
Significant Byte. Setting DLL=1 and
DLM .. O selects the divisor to divide by 1
(divide by 1 gives maximum baud rate
for a given input frequency at the CLK
input).
The BRG can use any of three different
popular frequencies to provide standard
baud rates. These frequencies are
1.8432 MHz, 2.4576 MHz, and 3.072
MHz. With these frequencies, standard
bit rates from 50 to 38.5 kbps are
available. Tables 7, 8, and 9 illustrate
the divisors needed to obtain standard
rates using these three crystal frequencies.
RESET
After power up, the VL 16C452 -RESET
input should be held low for 500 ns to
reset the VL 16C452 circuits to an idle
mode until in~ialization. A low on
-RESETcauses the following:
1. Initializes the transmitter and
receiver internal clock counters.
2. Clears the Line Status Register
(LSR), except for Transmitter Shift
Register Empty (TEMT) and
Transmit Holding Register Empty
(THRE), which are set. The Modem
Control Register (MCR) is also
cleared. All of the discrete lines,
memory elements and miscellane
ous logic associated with these
register bits are also cleared or
turned off. The Line Control
Register (LCR), Divisor Latches,
Receiver Buffer Register, Transmit
ter Buffer Register are not effected.
Following removal of the reset condition
(Reset high), the VL 16C452 remains in
the idle mode until programmed.

VLSI TECHNOLOGY, INC.
VL16C452

A hardware reset of the VL16C452 sets
the THRE and TEMT status bit in the
LSR. When interrupts are subsequently
enabled, an interrupt occurs due to
THRE.

A summary of the effect of a reset on
the VL 16C452 is given in Table 10.
PROGRAMMING
Each serial channel of the VL 16C452 is
programmed by the control registers
LCR, IER, DLL and DLM, and MCR.
These control words define the character length, number of stop bits, parity,
baud rate, and modem interface.

While the control register can be written
in any order, the IER should be written
to last because it controls the interrupt
enables. Once a serial channel is
programmed and operational, these
registers can be updated any time the
VL 16C452 serial channel is not
transmitting or receiving data.
The control signals required to access
each serial channel's internal registers
are shown below.
SOFlWARE RESET

A software reset of the serial channel is

completely known state without a
system reset. Such a reset consists of
writing to the LCR, Divisor Latches, and
MCR registers. The LSR and RBR
registers should be read prior to
enabling interrupts in order to clear out
any residual data or status bits which
may be invalid for subsequent
operation.
CLOCK INPUT OPERATION
The maximum input frequency of the
external clock of the VL 16C452 is 3.1
MHz.

a useful method for returning to a

TABLE 7. BAUD RATES (1.8432 MHz CLOCK)

DesIred
Baud Rate

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000

DIvIsor Used

2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6

Percent Error
DIfference Between
DesIred and Actual

0.026
0.058

0.69

3
2

2.86

VLSI TECHNOLOGY, INC
VL16C452

TABLE 8. BAUD RATES (2.4576 MHz CLOCK)
DesIred
Baud Rate

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

DIvIsor Used

3072
2048
1396
1142
1024
512
256
128
85
77

Percent Error
DIfference Between
DesIred and Actual

0.026
0.0007

0.392
0.260

64
43

0.775

32
21
16

1.587

8
4

TABLE 9. BAUD RATES (3.072 MHz CLOCK)
DesIred
Baud Rate

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

DIvIsor Used

3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5

Percent Error
DIfference Between
DesIred and Actual

0.026
0.034

0.312
0.628
1.23

VLSI TECHNOLOGY, INC
VL16C452

TABLE 10. RESET
Register/Signal

Reset

Reset Control

Interrupt Enable Register
Interrupt Identification
Register
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register

Reset
Reset

SOUT
Intrpt (RCVR Errs)
Intrpt (RCVR Data Ready)
Intrpt (THRE)
Intrpt (Modem Status Changes)
-Out2
-RTS
-DTR
-Out1

Reset
Read LSRlReset
Read RBRlReset
Read IIRlWrite THRlReset
Read MSRlReset
Reset
Reset
Reset
Reset

Reset
Reset
Reset
Reset

DEVICE APPLICATION
VL16C452

SERIAL
DATA
BUS

ADDR
BUS

CTL
BUS

DUAL
UARTAND
PRINTER
PORT

CHANNEL 0

9--PIN
"0"

BUFFERS

CONN

SERIAL

9--PIN

CHANNEL 1

CONN

BUFFERS

PARALLEL
PORT

RIC NET 1----11.

25-PIN

"D"

CONN

VLSI TECHNOLOGY, INC.
VL16C452

FUNCTIONAL
DESCRIPTION
PARALLEL PORT REGISTERS
The VL 16C4S2's parallel port interfaces
the device to a Centronics-style printer.
When Chip Select 2 (-CS2) is low. the
parallel port is selected. Table 11
shows the registers associated with this
parallel port. The read or write function
of the register is controlled by the state
of the read (-lOR) and write
(-lOW) pin as shown. The Read Data
Register allows the microprocessor to
read the information on the parallel bus.

The Read Status Register allows the
microprocessor to read the status of the
printer in the five most significant bits.
The status bits are Printer Busy
(-BUSY). Acknowledge (-ACK) which
is a handshake function. Paper Empty
(PE). Printer Selected (SLCT). and
Error
(-ERROR). The Read Control Register
allows the state of the control lines to
be read. The Write Control Register
sets the state of the control lines.

They are Interrupt Enable (IRQ ENB).
Select In (SLlN). Initialize the Printer
(-INIT). Autofeed the Paper (AUTOFD).
Strobe (STROBE). which informs the
printer of the presence of a valid byte
on the parallel bus. The Write Data
Register allows the microprocessor to
write a byte to the parallel bus.
The parallel port is completely compatible with the parallel port implementation used in the IBM SeriallParaliel
Adaptor.

TABLE 11. PARALLEL PORT REGISTERS
Register

Bit 6

BitS

Bit 4

Bit3

Bit 1

Bit 0

PD4

PD3

PD2

PD1

PD~

PD?

PD6

PD5

Read Status

-BUSY

-ACK

SLCT

-ERROR

Read Control

IRQENB

SUN

-INIT

PD?

PD6

PD5

PD4

PD3

PD2

IRQENB

SUN

-INIT

Read Data

Write Data
Write Control

TABLE 12. PARALLEL PORT REGISTER SELECT
Control Pins

-lOR -lOW -CS2
0
0
1

A1
0

AO
0

Read Status
Read Control

1
0
0

1
0
1

Invalid
Write Data
Invalid

Read Data

0
0

1
1

0
1
1

0
0

0
0
0
0
0

Write Control

Invalid

AUTOFD STROBE
PD1

PDO

AUTOFD STROBE

VLSI TECHNOLOGY, INC
VL16C452

AC CHARACTERISTICS TA= O°C to +70°C, VCC= 5 V ±50/0 (Notes 1,5)
Symbol

Parameter

tOlW

-lOR Strobe Width

125

Read Cyle

360

Min

Max

tODD

Delay from -lOR to Data

tHZ

-lOR to Floating Data Delay

tOow

-lOW Strobe Width

100
360

Conditions

Units

125

100 pF Load

100

100 pF Load, Note 4

Write Cycle

tOs

Data Setup Time

tOH

Data Hold Time

tRA

Address Hold Time from -lOR

Note 2

tRCS

Chip Select Hold Time from -lOR

Note 2

tAR

-lOR Delay from Address

Note 2

tCSR

-lOR Delay from Chip Select

Note 2

tWA

Address Hold Time from-lOW

Note 2

tWCS

Chip Select Hold Time from -lOW

Note 2

tAW

-lOW Delay from Address

Note 2

tCSW

-lOW Delay from Select

Note 2

tRW

Reset Pulse Width

JlS

tXH

Duration of Clock High Pulse

140

External Clock

tXL

Duration of Clock Low Pulse

140

External Clock

Notes:
1.
2.
3.
4.
5.

All timing specifications apply to pins on both serial channels (e.g. RI refers to both RIO and RI1).
The internal address strobe is always active.
RCLK =tXH and tXL.
Charge and discharge time is determined by VOL, VOH and the external loading.
All timings are referenced to valid 0 and valid 1.
(see AC TEST POINTS).
6. RCLK is internally derived from the internal-BAUDOUT signal.

VLSI TECHNOLOGY, INC
VL16C452

AC CHARACTERISTICS (Cant.) TA= O°C to +70°C, VCC= 5 V ±5% (Notes 1, 5)
Symbol

Conditions

Parameter

Transmitter
tHR1

Delay from Rising Edge of -lOW
(WR THR) To Reset Interrupt

tlRS

Delay from Initial INTR Reset to Transmit Start

tSI

Delay from Initial Write to Interrupt

tSTI

Delay from Stop to Interrupt (THRE)

tJR

Delay from -lOR (RD IIR)
to Reset Interrupt (THRE)

100 pF load

175

ClK
Cycles

Note 3

ClK
Cycles

Note 3

ClK
Cycles

250

100 pF load

Note 3

Modem Control
tMDO

Delay from -lOW
(WR MCR) to Output

250

100 pF load

tSIM

Delay to Set Interrupt from MODEM Input

250

100 pF load

tRIM

Delay to Reset Interrupt from
-lOR (RS MSR)

250

100 pF load

ClK
Cycles

Receiver
tSINT

Delay from Stop to Set Interrupt

tRINT

Delay from -lOR
(RD RBR/RDlSR) to Reset Interrupt

Ils

500

Note 3
100 pF load

Parallel Port
tOT

Data Time

Ils

tSB

Strobe Time

Ils

tAD

Acknowledge Delay (Busy Start to Acknowledge)

Ils

Defined by Printer

tAKD

Acknowledge Delay (Busy End to Acknowledge)

JlS

Defined by Printer

tAK

Acknowledge Duration Time

IlS

Defined by Printer

tBSY

Busy Duration Time

IlS

Defined by Printer

tBSD

Busy Delay Time

JlS

Defined by Printer

Notes:
1. All timing specifications apply to pins on both serial channels (e.g. RI refers to both RIO and RI1).
2. The internal address strobe is always active.
3. RClK - tXH and tXL.
4. Charge and discharge time is determined by Val, VOH and the external loading.
5. All timings are referenced to valid 0 and valid 1 (see AC TEST POINTS).

VLSI TECHNOLOGY, INC
VL16C452

WRITE CYCLE TIMING
-------------vA~L~ID~--------:

A2 A1 AD

VALID

-CS

tCSW

•

tA_W_-_-_-_-_-_-_-:~------I~________~)(~l..-------

WC------------~~

__________
-lOW

ACTIVE

•

-------------t-----{~---~ACTIVE

-lOR

DATA 00-07

"tDH~

tDS
_______________~\VALID DATA

)L________________

READ CYCLE TIMING
VALID

A2 A1 AD

tRA
VALID

-cs

"tRCS

tCSR
tAR

•

-lOR

-lOW

iACT,VE

•

VCTIVE

tODD

~~• VALID
-

DATA ------------------------'""1 DATA
00-07

1HZ

~\....______

VLSI TECHNOLOGY, INC.
VL16C452

RECEIVER TIMING

SIN\

START ~TA BITS (5-8)

(RECEIVER
INPUT
DATA)

t =t

INTERRUPT
(DATA READY OR
RCVR ERR)

tAINT

-lOR -

\ ACTIVE

TRANSMITTER TIMING
SERIAL
OUT (SOUT)

DATA (5-8)

INTERRUPT
(THRE)

-lOW

(WRTHR)~ ~~~~~
__

________________________________ •

-lOR

(RD IIR)

MODEM TIMING
-lOW

..JL

\_--~-.:..-...t.

(WR MCR) _ _
-RTS. -DTR

~I~

!MOO

-CTS.-DSA.-RLSD _____..oJ

-INTERRUPT _ _ _--11--_
-lOR
(RD MSR)

-RI

f) VLSI TECHNOLOGY, INC.
VL16C452
PARALLEL PORT TIMING
DATA

-=fDTt-tDT}

-M-

STROBE

-ACK
•

tAD--~

BUSY

AC TESTING INPUT/OUTPUT WAVEFORMS
EXTERNAL CLOCK INPUT
~

AC TEST POINTS

tXH

.tXL"

TEST CIRCUIT
2.54 V

Output Under Test

6800

'Indudes Scope and Jig 82 pF"
Capacitance

100

VLSI TECHNOLOGY, INC.
VL16C452

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

-10°C to +70°C

Storage Temperature -65°C to + 150°C
Supply Vo~age to
Ground Potential -0.5 V to VCC + 0.3 V
Applied Output
Voltage

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only, functional
operation of this device at these or any
other conditions above

those indicated in this data sheet is not
implied. Exposure to absolute maximum
rating conditions for extended periods
may affect device reliability.

-0.5 V to vce + 0.3 V

Applied Input
Vo~age

-0.5 V to + 7.0V

Power Dissipation

500mW

DC CHARACTERISTICS:

TA=Oto+70°C, VCC=5V±50/0

Symbol

Parameter

Min

VILX

Clock Input low Voltage

-0.5

0.8

Max

Units

VIHX

Clock Input High Voltage

2.0

vec

Vil

Input low Voltage

-0.5

0.8

VIH

Input High Voltage

2.0

VCC

VOL

Output low Voltage

VOH

Output High Voltage

ICC

Power Supply Current

III

Input leakage

lel

Clock Leakage

IOZ

3-State Leakage

Vll(RES)

Reset Schmitt VIL

VIH(RES)

Reset Schmitt VIH

0.4

2.4

Conditions

IOl ... 4.0 mA on DBO - DB7
IOl -12 mA on PDO - PD7
IOl ... 10 mA on -NIT, -AFD, -STB,
and -SUN (see Note 1)
IOl ... 2.0 mA on all other outputs

IOH • -0.4 mA on DBO - DB7
IOH .. -2.0 mA on PDO - PD7
IOH • -0.2 mA on -IN IT, -AFD, -STB,
and -SUN
IOH • -0.2 mA on all other outputs

VCC • 5.25 V, No loads on SINO,1;
-DSRO,1; -RlSDO,1 ; -CTSO, 1. -RIO,
-R11 • 2.0 V. Other inputs. 0.8 V. Baud
rate generator. 4 MHz. Baud rate. 56K

±10

VCC. 5.25 V, GND • 0 V.
All other pins floating.

±10

VIN • 0 V, 5.25 V

VCC • 5.25 V, GND • 0 V.
VOUT • 0 V, 5.25 V
1) Chip deselected
2) Chip and wr~e mode selected

±20

0.8
2.0

V
V

Nota 1. -INIT, -AFD, -STB, and -SUN are open collector output pins that each have an internal pull-up resistor (2.5 kn - 3.5 kn)
to VCC. This will generate a maximum of 2.0 mA of internal IOL. In addition to this internal current, each pin will sink at least 10
mA, while maintaining the VOL specification of 0.4 V Max.

101

VLSI TECHNOLOGY, INC

102

VLSI TECHNOLOGY, INC.
VL16C550
ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFOs

FEATURES

DESCRIPTIONS

• Fully compatible with VL 16C450 ACE

The VL 16C550 is an asynchronous
communications element (ACE) that is
functionally equivalent to the
VL 16C450, and additionally incorporates a 16 byte FIFO. The FIFOs are
available on both the transmitter and
receiver, and can be activated by
placing the device in the FIFO mode.
After a reset, the registers of the
VL 16C550 are identical to those of the
VL16C450.

• 16 byte FIFO reduces CPU interrupts
• Full double buffering
• Modem control signals include -CTS,
-RTS, -DSR, -DTR, -RI and -DCD
• Programmable serial characteristics:
- 5-, 6-, 7- or a-bit characters
- Even-, odd-, or no-parity bit generation and detection
- 1-, 1 1/2- or 2-stop bit generation
- Baud rate generation (dc to 56K
baud)
• Independent control of transmit,
receive, line status, data set interrupts,
FIFOs
• Full status reporting capabilities
• Three-state, TIL drive capabilities for
bidirectional data bus and control bus

characters transmitted by the CPU. In
the FIFO Mode, FIFOs are enabled
permitting 16 bytes to be stored in both
transmit and receive mode. The FIFOs
also provide three bits per byte of error
data in the receiver FIFO. The complete status of the ACE can be read at
any time during functional operation by
the CPU. The information obtained
includes the type and condition of the
transfer operations being performed,
and error conditions involving parity,
overrun, framing, or break interrupt.

Improved VL 16C550 specifications
provide compatibility with most newer
state-of-the-art CPUs. The VL 16C550
serves as a serial data input/output
interface in microcomputer systems. It
performs serial-to-parallel conversion
on data characters received from
peripheral devices or modems, and
parallel-to-serial conversion on data

A programmable baud rate generator is
included that can divide the timing
reference clock input by a divisor
between 1 and (2 16_1).
The VL 16C550 ACE with FIFOs is
available in both plastic and ceramic
DIP as well as a PLCC.

VL16C550

PIN DIAGRAMS

-OeD
03

VL16C550

DO
01

02
03

04
05

06
07
RClK
SIN
SOUT

CSO
CS1
-CS2
-BAUDOUT
XTAL1
XTAL2
-DOSTA
DOSTA
VSS

VCC
-RI
-DCD
-DSR
-CTS
MR
-oUT1
-DTR
-RTS
-oUT2
INTRPT
RXRDY

I 02 I

N.C. -AI I-OSR
00 vcc
~TS

•

05
06
07
RCLK

MR
-OUT 1
-OTR
-ATS
-OUT2
N.C.
INTRPT
RXROY
AO
A1

38
37

36
35
34
33
32
31

SIN
N.C.
SOUT
csa
CS1
-CS2
-BAUDOUT
18 1920 21 22 23 24 25 26 2728

AO
A1
A2
-ADS
TXADY
DDIS
DISTA
-DISTA

XTAL1

XTAL2

vssNt

-Oosm

-DOSTR

OOIS I-AOS

-0 Ism

TXROY

olsm

ORDER INFORMATION
Part
Number
Vl16C550-PC
Vl16C550-CC
VL 16C550-QC

External
Clock
Frequency
3.1 MHz

Package
Plastic DIP
Ceramic DIP
Plastic leaded Chip Carrier (PLCC)

Note: Operating temperature range is 0 C to + 70 C.

103

VLSI TECHNOLOGY, INC

104

VLSI TECHNOLOGY, INC.
VL1772-02
FLOPPY DISK CONTROLLER/FORMATIER

FEATURES
• BUilt-in data separator
• Built-in write precompensation
• Single and double density
• Motor control
• 128,256,512, or 1024 sector lengths

The VL 1772-02 is an MOSILSI device
that performs the functions of a floppy
disk controller/formatter. It replaces the

The VL 1772-02 is implemented in
NMOS silicon-gate technology and is
available in a 28-pin dual in-line
package. It is a low-cost version of the
WD179X Floppy Disk Controller/
Formatter and is compatible with generic
179X types. It also has a built-in digital
data separator and write precompensation circuits. A single read (RD) line (pin
19) is the only input required to recover
serial FM or MFM data from the disk
drive. The device has been specifically
.designed for control of floppy disk drives

PIN DIAGRAM

BLOCK DIAGRAM

• TTL compatible
• 8-bit bidirectional data bus
• Fast step rates
• 28-pin DIP
• Single 5 V power supply

DESCRIPTION

with data rates of 125K bps (single
density) and 250K bps (double density).
In addition, it can write a precompensation that is125 ns from nominal, and can
be enabled at any point through simple
software commands. Another programmable feature, Motor On, has been
incorporated to automatically enable
the spindle motor prior to operating a
selected drive. The VL 1772-02 offers
stepping rates of 2, 3, 6, and 12 ms.

older 1770-type device. The drive side
of the interface needs no additional logic
except for buffers/receivers. Designed
for single- or double-density operation,
the device contains a programmable
Motor On signal.

The processor interface consists of an
8-bit bidirectional bus for transfer of the
status information, data, and commands. All host communication with
the drive occurs through these data
lines. They are capable of driving one
standard TTL load or three LS loads.

DAL

VL1n2·02
8

INTRa

RIW

ORO

DDEN

WPRT

DALO

DAL1

TROO

DAL2
DAL3

WG
MO

DAL5

RD
CLK

DAL7

DIRC

STEP

GND

,
I I • I 1•

COMMAND
REGISTER

DATA
REGISTER

...

IAM DETECTOR I

I+-{

CRO LOGIC

•

ry -l

TRACK
REGISTER

F=11

STATUS
REGISTER

~
PRECOM

,SEPARATOR
WD

'-----I

ORO

INTRa
MR
CS

RJiIT
AO
A1
CLK(8MHz)
DO EN

I
I

BUS

•

DATAOUT
BUFFERS

...,

SECTOR
REGISTER

H g~I~~•

INTERNAL

DAL4

DAL6

0-8.t. 8

•
COMPUTER
INTERFACE
CONTROL

CONTROL

PLA
CONTROL
(240 X 19)

CONTROL

VCC

ORDER INFORMATION
Part
Number

Package

VL1772-02PC
VL 1772-020C
VL 1772-02CC

Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
Ceramic DIP

Note: Operating temperature range is O°C to +70°C.
105

WJm

'III'

DISK

TROO

INTERFACE

STEP
OIRO
MO

CONTROL

VLSI TECHNOLOGY, INC.
VL1772-02

SIGNAL
DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Description
Chip Select - A logic low on this input selects the chip and enables host communication
with the device.

AO,A1

ReadlWrite - A logic high on this input controls the placement of data on the 00-07 lines
from a selected register, while a logic low causes a write operation to a selected register.

3,4

Address 0, 1 - These two inputs select a register to read or write data:

CS
0
0
0

A1
0
0
1
1

AO
0
1
0
1

RiW-1
Status Register
Track Register
Sector Register
Data Reaister

RiW=o
Command Register
Track Register
Sector Register
Data Reaister

DALO - DAL7

5 - 12

Data Access Lines 0 through 7 - Eight-bit bidirectional bus used for transfer of data,
pontrol, or status. This bus is enabled by CS and RIW. Each line drives one TTL load.

Master Reset - A logic low pulse on this line resets the device and initializes the status
register (internal pull-up).

GND

Ground - Ground

VCC

Power Supply - +5 V ±5% power supply input.

STEP

Step - The Step output contains a pulse for each step of the drive's
pulse to the disk drive.

DIRC

Direction - The Direction output is high when stepping in towards the center of the
diskette, and low when stepping out.

CLK

Clock - This input requires a free-running 50% duty cycle clock (for internal timing) at 8
MHz ±1%.

Read Data - This active-low input is the raw data line containing both clock and data
pulses from the drive.

Motor On - Active high output used to enable the spindle motor prior to read, write, or
stepping operations.

Write Gate - This output is made valid prior to writing on the diskette.

Write Data - FM or MFM clock and data pulses are placed on this line to be written on
the diskette.

TROO

Track 00 - This active-low input informs the VL 1772-02 that the drive's RIW heads are
positioned over Track zero (internal pull-up).

Index Pulse - This active-low input informs the VL 1772-02 when the physical index hole
has been encountered on the diskette (internal pull-up).

WPRT

Write Protect - This input is sampled whenever a Write Command is received. A logic
low on this line prevents any Write Command from executing (internal pull-up).

[)'5"EN

Double Density Enable - This input pin selects either single (FM) or double (MFM)
density. When DO EN == 0, double density is selected (internal pull-up).

ORa

Data Request - This active-high output indicates that the Data Register is full (on a
Read) or empty (on a Write) operation.

INTRa

Interrupt Request - This active-high output is set at the completion of any command or a
read of the Status Register.

106

RiW head. This is a

VLSI TECHNOLOGY, INC.
VL1772-02

ARCHITECTURE
TheVL 1772-02 Floppy Disk Controllerl
Formatter block diagram is illustrated on
the front page. The primary sections
include the parallel processor interface
and the floppy disk interface.
Data Shift Register - This a-bit register
assembles serial data from the Read
Data input (RD) during read operations
and transfers serial data to the Write
Data output during write operations.
Data Register - This a-bit register is
used as a holding register during disk
read and write operations. In disk read
operations, the assembled data byte is
transferred in parallel to the Data
Register from the Data Shift Register. In
disk write operations, information is
transferred in parallel from the Data
Register to the Data Shift Register.
When executing the Seek command, the
Data Register holds the address of the
desired track position. This register is
loaded from the Data Access Lines
(DAL) and gated onto the DAL under
processor control.
Track Register - This a-bit register holds
the track number of the current readl
write head position. It is incremented by
one every time the head is stepped in
and decremented by one every time the
head is stepped out (towards Track 00).
The contents of the register are com-

pared with the recorded track number in
the ID field during disk read, write, and
verify operations. The Track Register
can be loaded from or transferred to the
DAL. This register should not be loaded
when the device is busy.
Sector Register (SR) - This a-bit register
holds the address of the desired sector
position. The contents of the register
are compared with the recorded sector
number in the ID field during disk read
or write operations. The Sector Register
contents can be loaded from or transferred to the DAL. This register should
not be loaded when the device is busy.
Command Register (CR) - This a-bit
register holds the command presently
being executed. This register should not
be loaded when the device is busy,
unless the new command is a forced
interrupt. The Command Register can
be loaded from the DAL but not read
onto the DAL.
Status Register (STR) - This a-bit
register holds device status information.
The meaning of the status bits is a
function of the type of command
previously executed. This register can
be read onto the DAL but not loaded
from the DAL.
CRC Logic - This logic is used to check
or to generate the 16-bit cyclic redun-

dancy check (CRC). The polynomial is:
G(x)

x16 + X12 + x5 + 1

The CRC includes all information
starting with the address mark and up to
the CRC characters. The CRC register
is preset to ones prior to data being
shifted through the circuit.
Arithmetic/logic Unit (ALU) - The ALU is
a serial comparator, incrementer, and
decrementer and is used for register
modification and comparisons with the
disk-recorded ID field.
Timing and Control - All computer and
floppy disk interface controls are
generated through this logic. The
internal device timing is generated from
an external crystal clock. The VL 177202 has two different modes of operation
according to the state of DDEN: When
~ ... 0, double density (MFM) is
enabled. When DDEN ... 1, single
density is enabled.
Address Mark Detector - The AM
detector detects ID, data, and index
address marks during read and write
operations.
Data Separator - A digital data separator, consisting of a ring shift register and
data window detection logic, provides
read data and a recovery clock to the
AM detector.

FIGURE 1. SYSTEM BLOCK DIAGRAM

WG
ClK

HOST
INTERFACE

WD
RD

~
AO
A1

CS
RtW

.
..
..

51/41NCH
VL1n2-02

TJ5
TROO

W"PRi

MO
DIRC

ORO
INTRa
5V

-:l:-BDEN

STEP
GND VCC

J107

FLOPPY
DRIVE

VLSI TECHNOLOGY, INC.
VL1772-02

FUNCTIONAL
DESCRIPTION
PROCESSOR INTERFACE
The interface to the processor is
accomplished through the eight data
access lines (DALs) and associated
control signals. The DALs are used to
transfer data, status, and control words
out of, or into the VL 1n2-02. The DALs
are three-state buffers that are enabled
as output drivers when Chip Select (CS)
= 0 and ANI = 1 are active, or act as
input receivers when CS and RiW = 0
are active.
When transfer of data with the Floppy
Disk Controller is required by the host
processor, the device address is
decoded and CS is made low. The
address bits A 1 and AO, combined with
the signal R7W during a read or write
operation, are interpreted as selecting
the following registers:
A1 - AO READ (RIW = 1)
0 Status Register
0
1 Track Register
0
1
0 Sector Register
1
1 Data Register

sector is reached.
On disk write operations, the Data
Request is activated when the Data
Register transfers its contents to the
Data Shift Register, and requires a new
data byte. It is reset when the Data
Register is loaded with new data by the
processor. If new data is not loaded at
the time the next serial byte is required
by the floppy disk, a byte of zeros is
written on the diskette and the Lost Data
bit is set in the Status Register.
At the completion of every command an
INTRa is generated; it is reset by either
reading the status register or by loading
the command register with a new
command. In addition, INTRa is
generated if a Force Interrupt command
condition is met.

WRITE (RIW = 0)
Command Register
Track Register
Sector Register
Data Register

After any register is written to, the same
register cannot be read from until 16 J.ls
in MFM or 32 J.ls in FM have elapsed.
During direct memory access (DMA)
types of data transfers between the
Data Register of the VL 1n2-02 and the
processor, the Data Request (ORO)
output is used in data transfer control.
This signal also appears as status bit 1
during read and write operations.
On disk read operations, the Data
Request is activated (set high) when an
assembled serial input byte is transferred in parallel to the Data Register.
This bit is cleared when the Data
Register is read by the processor. If the
Data Register is read after one or more
characters are lost, by having new data
transferred into the register prior to
processor readout, the Lost Data bit is
set in the Status Register. The read
operation continues until the end of

The VL 1n2-02 has two modes of
operation, according to the state of
DDEN. When DDEN = 1, single density
is selected. In either case, the CLK
input is at 8 MHz.
GENERAL DISK READ OPERATIONS
Sector lengths of 128,256,512, or 1024
bytes are obtainable in either FM or
MFM formats. For FM, '[)"I)"E"j\J should be
placed to logical "1". For MFM formats,
DDEN should be placed to a logical "0".
Sector lengths are determined at format
time by the fourth byte in the "10" field.
SECTOR LENGTH TABLE
SECTOR LENGTH
NUMBER OF BYTES
FIELD (HEX)
IN SECTOR (DECIMAL)

128
256
512
1024

01
02
03

108

There are from 0 to 244 sectors per
track for the VL 1n2-02, and from 0 to
244 tracks.
GENERAL DISK WRITE OPERATION
When writing is to take place on the
disk the Write Gate (WG) output is
activated, allowing current to flow into
the readlwrite head. As a precaution to
erroneous writing, the first data byte
must be loaded into the Data Register
in response to a Data Request from the
device before the Write Gate signal can
be activated.
Writing is inhibited when the Write
Protect input is a logic low, in which
case any Write command is immediately terminated, an interrupt is generated, and the Write Protect status bit is
set.
For write operations, the VL 1n2-02
provides Write Gate to enable a write
condition, and Write Data which
consists of a s.eries of active-high
pulses. These pulses contain both
clock and data information in FM and
MFM. Write Data provides the unique
missing clock patterns for recording
address marks.
The Precompensation Enable bit in
Write commands allow automatic write
precompensation to take place. The
outgoing write data stream is delayed or
advanced from nominal by 187ns
according to the following table:
PATTERN
1
1
0
1
o 0 0
1
0 0

0
1

X
X

1
0

MFM
Early
Late
Early
Late

FM
N/A
N/A
N/A
N/A

Next Bit to be sent
Current Bit sendmg
' - - - - - - Previous Bits sent

Precompensation is typically enabled
on the innermost tracks where bit shifts
usually occur and bit density is at its
maximum.

VLSI TECHNOLOGY, INC.
VL1772-02

COMMANDS
The VL 1772-02 accepts eleven commands. Command words should only be
loaded in the Command Register when
the Busy Status Bit is off (Status Bit 0).
The one exception is the Force Interrupt
command. Whenever a command is
being executed, the Busy Status Bit is
set. When a command is completed, an
interrupt is generated and the Busy
status bit is reset. The Status Register
indicates whether the completed
command encountered an error or was
fault-free. For ease of discussion,
commands are divided into four types
and are summarized in
Table 1.

mined by the direction output. The chip
will step the drive in the same direction it
last stepped unless the command
changes the direction.
The Direction signal is active-high when
stepping in and low when stepping out.
The Direction signal is valid 24 ~s before
the first stepping pulse is generated.

redundancy check (CRC) is correct, the
verify operation is complete and an
INTRQ is generated with no errors. If
there is a match but not a valid CRC, the
CRC Error Status Bit is set (Status Bit
3), and the next encountered ID field is
read from the disk for the verification
operation.

After the last directional step, an
additional 30 ms of head settling time
takes place if the Verify flag is set in
Type I commands. There is also a 30
ms head settling time if the E flag is set
in any Type II or III command.
When a Seek, Step, or Restore command is executed, an optional verification of read/write head position can be
performed by setting bit 2 (V = 1) in the
command word to logic 1. The verification operation begins at the end of the
30 ms settling time after the head is
loaded against the media. The track
number from the first encountered ID
Field is compared against the contents
of the Track Register. If the track
numbers compare and the ID Field cyclic

The Type I Commands (see Figure 2)
include the Restore, Seek, Step, Step-in,
and Step-out commands. Each of the
Type I Commands contains a rate field
(rO, r1), which determines the stepping
motor rate.
A 4 ~ (MFM) or 8 ~s (FM) pulse is
provided as an output to the drive. For
every step pulse issued, the drive moves
one track location in a direction deter-

The VL 1772-02 must find an ID field
with correct track number and correct
CRC within five revolutions of the media,
otherwise, the seek error is set and an
INTRQ is generated. If V lOS 0, no
verification is performed.
All commands, except the Force
Interrupt command, may be programmed via the h Flag to delay for
spindle motor start up time. If the h Flag
is not set and the Motor On line is low
when a command is received, the
VL 1772-02 will force Motor On to a logic
1 and waits six revolutions before
executing the command. At 300 RPM,
this guarantees a one-second spindle
start-up time. If, after finishing the

TABLE 1. COMMAND SUMMARY
TYPE II & III COMMANDS

BITS
TYPE COMMAND 7
I Restore
0
I Seek
0
I Step
0
I Step-In
0
I Step-out
0
II Read Sector 1
II Write Sector 1
III Read
Address
III Read Track
III Write Track
IV Force
Interrupt

0
0
0
1
1
0
0

5
0
0
1
0
1
0
1

0
1
u
u
u
m
m

0
1
1

0
0
1

0
ro
ro
ro
ro
ro
0

h
h
h
h
h
h
h

2
V
V
V
V
V
E
E

r1
r1
r1
r1
r
0
P

h
h
h

E
E
E

0
0
P

0
0
0

m = Multiple Sector Flag (Bit 4)
m = 0, Single Sector
m = 1, Multiple Sector
H
Motor On Flag (Bit 3)
H
0, Enable Spin Up Sequence
H
1, Disable Spin Up Sequence

=
=

ao = Data Address Mark (Bit 0)
= Write Normal Data Mark
= 1, Write Deleted Data Mark
E = 15ms Settling Delay (Bit 2)
E = 0, No Delay
E = 1, Add 15ms Delay
P = Write Precompensatlon (Bit 1)
P
O,Enable Write Precomp
P = 1,Disable Write Precomp

ao
ao

FLAG SUMMARY

TYPE I COMMANDS
h
Moto, On Flag (Bit 3)
h
0, Enable Spln·up Sequence
1, Disable Spin-up Sequence
h
V
Verify Flag (Bit 2)
V
0, No Verify
1, Verify on Destination Track
V
'1' ro
Stepping Rate (Bits 1,0)
1772-02
r1
'0
0
0
6 ms
0
1
12 ms
1
0
2 ms
1
1
3 ms
u
Update Flag (Bit 4)
u
0, No Update
u
1, Update Track Register

=
=
=
=
=
=

TYPE IV COMMANDS
13-1 0 Interrupt Condition (Bits 3-0)

10 = 1, Not Used
11 = 1, Not Used
12 = 1, Interrupt on Index Pulse
13 = 1, Immediate Interrupt
13-10
0, Terminate without interrupt

=
=
=

109

VLSI TECHNOLOGY, INC.
VL1772-02

command, the device remains idle for
ten revolutions, the Motor On line goes
If a command is
back to a logic
issued while Motor On is high, the
command executes immediately, defeating the six-revolution start up. This
feature allows consecutive read or write
commands without waiting for each
motor start-up; the VL 1n2-02 assumes
the spindle motor is up to speed.

RESTORE (SEEK TRACK 0)
Upo..!!..!!!£eipt of this command, the Track
00 (TROO) input is sampled. If TROO is
active-low indicating the read/write head
is positioned over Track 00, the Track
Register is loaded with z~nd an
interrupt is generated. If TROO is not
active-low, stepping pulses (pin 16) at a
rate specified b~ the r1, rO field are
issued until the TROO input is activated.

At this time, the Track Register is loaded
with zeros and an interrupt is generated.
If the TROD input does not go active-low
after 255 stepping pulses, the VL 1n202 terminates operation, interrupts, and
sets the Seek Error Status Bit, providing
the V flag is set. A verification operation
also takes place if the V flag is set. The
h bit allows the Motor On option at the
start of command.

FIGURE 2. TYPE I COMMAND FLOWCHART

SET DIRECTION

-1 TOTR

OTOTR

110

VLSI TECHNOLOGY, INC.
VL1772-02
FIGURE 3. TYPE II COMMAND FLOWCHART

FIGURE 2. TYPE I COMMAND FLOWCHART (Cent.)

VERIFY
SEQUENCE

SETMO
WAIT
61NDEX PULSES

seT
CRC
ERROR

INTRa
REseT BUSY

INTRa. RESET BUSY
SET WRITE PROTECT

111

VLSI TECHNOLOGY, INC.
VL1772-02

SEEK
This command assumes that the Track
Register contains the track number of
the current position of the read/write
head and the Data Register contains the
desired track number. The VL 1772-02
will update the Track Register and issue
stepping pulses in the appropriate
direction until the contents of the Track
Register are equal to the contents of the
Data Register (the desired track
location). A verification operation takes
place if the V flag is on. The h bit allows
the Motor On option at the start of the
command. An interrupt is generated at
the completion of the command. ( Note:
When using multiple drives, the track
register must be updated for the drive
selected before seeks are issued.)
STEP
Upon receipt of this command, the
VL 1772-02 issues one stepping pulse to
the disk drive. The stepping motor
direction is the same as in the previous
step command. After a delay determined by the r1, rO field, a verification
takes place if the V flag is on. If the U
flag is on, the Track Register is updated.
The h bit allows the Motor On option at
the start of the command. An interrupt
is generated at the completion of the
command.
STEP-IN
Upon receipt of this command, the
VL 1772-02 issues one stepping pulse in
the direction towards track 76. If the U
flag is on, the Track Register is incremented by one. After a delay is
determined by the r1, rO field, a verification takes place if the V flag is on. The h
bit allows the Motor On option at the
start of the command. An interrupt is
generated at the completion of the
command.
STEP-OUT
Upon receipt of this command, the
VL 1772-02 issues one stepping pulse in
the direction towards track O. If the U
flag is on, the Track Register is decremented by one. After a delay determined by the r1, rO field, a verification
takes place if the V flag is on. The h bit
allows the Motor On option at the start of
the command. An interrupt is generated
at the completion of the command.
TYPE II COMMANDS
The Type II Commands (see Figure 3)

are the Read Sector and Write Sector
commands. Prior to loading the Type II
Command into the Command Register,
the computer must load the Sector
Register with the desired sector number.
Upon receipt of the Type II command,
the busy status bit is set. If the E flag =
1, the command executes after a 15 ms
delay.
When an ID field is located on the disk,
the VL 1772-02 compares the track
number on the ID field with the Track
Register. If there is not a match, the
next encountered ID field is read and a
comparison is again made. If there was
a match, the sector number of the ID
field is compared with the Sector
Register. If there is not a sector match,
the next encountered ID field is read off
the disk and comparisons again made.
If the 10 field CRC is correct, the data
field is then located and is either written
into or read from depending upon the
command. The VL 1772-02 must find an
ID field with a track number, sector
number, and CRC within four revolutions
of the disk; otherwise, the Record Not
Found Status Bit is set (Status Bit 4) and
the command is terminated with an
interrupt (INTRa).
Each of the Type II Commands contains
an m flag that determines if multiple
records (sectors) are to be read or
written, depending upon the command.
If m = 0, a single sector is read or written
and an interrupt is generated at the
completion of the command. If m = 1,
multiple records are read or written with
the sector register internally updated so
that an address ve,rification can occur on
the next record. The VL 1772-02
continues to read or write multiple
records and update the sector register in
numerical ascending sequence until the
sector register exceeds the number of
sectors on the track or until the Force
Interrupt command is loaded into the
Command Register, which terminates
the command and generates an
interrupt.
For example: if the VL 1772-02 is
instructed to read sector 27 and there
are only 26 sectors on the track, the
sector register exceeds the number
available. The VL 1772-02 will search
for five disk revolutions, interrupt out,
reset busy, and set the Record Not
Found Status Bit.

112

READ SECTOR
Upon receipt of the Read Sector
command, the Busy status bit is set, and
when an ID field is encountered that has
the correct track number, correct sector
number, and correct CRC, the data field
is presented to the computer. The data
address mark (DAM) of the data field
must be found within 30 bytes in single
density and 43 bytes in double density
of the last ID field CRC byte; if not, the
ID field is searched for and verified
again followed by the data address mark
search. If, after five revolutions the
DAM cannot be found, the Record Not
Found StatusBit is set and the operation
is terminated. When the first character
or byte of the data field has been shifted
through the DSR, it is transferred to the
DR, and DRa is generated. If the
computer has not read the previous
contents of the DR before a new
character is transferred, that character is
lost and the Lost Data Status bit is set.
This sequence continues until the
complete data field has been input to the
computer. If there is a CRC error at the
end of the data field, the CRC Error
Status Bit is set, and the command is
terminated (even if it is a multiple record
command).
At the end of the read operation, the
type of data address mark encountered
in the data field is recorded in the Status
Register (Bit 5) as shown:
STATUS BIT 5

Deleted Data Mark
Data Mark

WRITE SECTOR
Upon receipt of the Write Sector
command, the Busy status bit is set.
When an ID field is encountered that
has the correct track number, correct
sector number, and correct CRe, a ORO
is generated. The VL1772-02 counts off
11 bytes in single density and 22 bytes
in double density from the eRe field and
the Write Gate (WG) output is made
active if the DRa is serviced (i.e., the
DR has been loaded by the computer).
If ORO has not been serviced, the
command is terminated and the Lost
Data status bit is set. If the DRa has
been serviced, the WG is made active
and six bytes of zeros in single density
and 12 bytes in double density are then
written on the disk. At this time, the data

VLSI TECHNOLOGY, INC.
VL1772-02

FIGURE 3. TYPE II COMMAND FLOWCHART (Cont.)

INTRa. RESET BUSY
SET RECORD·NOT FOUND

SET CRC
STATUS ERROR

READ

113

VLSI TECHNOLOGY, INC.
VL1772-02

FIGURE 3. TYPE II COMMAND FLOWCHART (Cont.)

READ SECTOR
SEQUENCE

SET DATA
LOST

114

VLSI TECHNOLOGY, INC.
VL1772-02

FIGURE 3. TYPE II COMMAND FLOWCHART (Cant.)

WRITE
SEQUENCE

SET DATA LOST
WRITE BYTE
OF ZEROES

115

VLSI TECHNOLOGY, INC.
VL1772-02

address mark is then written on the disk
as determ ined by the aO field of the
command as shown below:
80

DATA ADDRESS MARK (BIT 0)

Deleted Data Mark
Data Mark

so that a comparison can be made by
the user. At the end of the operation an
interrupt is generated and the Busy
status is reset.
Read Track - Upon receipt of the READ
track command, the head is loaded and
the Busy status bit is set. Reading
starts with the leading edge of the first
encountered index pulse and continues
until the next index pulse. All gap,
header, and data bytes are assembled
and transferred to the Data Register and
DROs are generated for each byte. The
accumulation of bytes is synchronized to
each address mark encountered. An
interrupt is generated at the completion
of the command.

The VL 1772-02 then writes the data field
and generates DROs to the computer. If
the ORO is not serviced in time for
continuous writing, the Lost Data Status
Bit is set and a byte of zeros is written
on the disk. The command is not
terminated. After the last data byte has
been written on the disk, the two-byte
CRC is computed internally and written
on the disk followed by one byte of logic
ones in FM or in FMF. The WG output
is then deactivated. INTRa will set 24
J.l.s (MFM) after the last CRC byte is
written. For partial sector writing, the
proper method is to write data and fill
the balance with zeros.

This command has several characteristics that make it suitable for diagnostic
purposes. They are: no CRC checking
is performed; gap information is included
in the data stream; and the address
mark detector is on for the duration of
the command. Because the AM detector
is always on, write splices or noise may
cause the chip to look for an AM.

TYPE III COMMANDS
Read Address - Upon receipt of the
Read Address command, the Busy
Status Bit is set. The next-encountered
10 field is then read in from the disk; and
six data bytes of the 10 field are assembled and transferred to the DR, and
a ORO is generated for each byte. The
six bytes of the 10 field are shown
below:
TRACK
ADDR

The 10 AM, 10 Field, 10 CRC Bytes,
DAM, Data and Data CRC Bytes for
each sector will be correct. The Gap
Bytes
may be read incorrectly during writesplice time because of synchronization.
CRC

2
6

Although the CRC characters are
transferred to the computer, the
VL 1772-02 checks for validity and the
CRC Error Status Bit is set if there is a
CRC error. The track address of the 10
field is written into the Sector Register

WRITE TRACK FORMATTING
THE DISK
Data and gap information are provided
at the computer interface. Formatting
the disk is accomplished by positioning

the RMI head over the desired track
number and issuing the Write Track
command.
Upon receipt of the Write Track command, the Busy Status Bit is set.
Writing starts with the leading edge of
the first encountered index pulse and
continues until the next index pulse, at
which time the interrupt is activated.
The Data Request is activated immediately upon receiving the command, but
writing will not start until after the first
byte has been loaded into the Data
Register. If the DR has not been loaded
within three byte times, the operation is
terminated, making the device Not Busy,
the Lost Data Status Bit is set, and the
interrupt is activated. If a byte is not
present in the DR when needed, a byte
of zeros is substituted.
This sequence continues from one index
mark to the next index mark. Normally,
whatever data pattern appears in the
data register is written on the disk with a
normal clock pattern. However, if the
VL 1772-02 detects a data pattern of F5
through FE in the data register, this is
interpreted as a data address mark with
missing clocks or CRC generation.
The CRC generator is initialized when
any data byte from F8 to FE is about to
be transferred from the DR to the DSR
in FM or by receipt of F5 in MFM. An F7
pattern generates two CRC characters
in FM or MFM. As a consequence, the
patterns F5 through FE must not appear
in the gaps, data fields, or 10 fields.
Also, CRCs must be generated by an F7
pattern.
Disks may be formatted in IBM 3740 or
System 34 formats with sector lengths of
128, 256, 512, or 1024 bytes.

TABLE 2. DATA PATTERN DECODE
DATA PATTERN
IN DR (HEX)

00 thru F4
F5
F6

F7
F9 thru FB
FC
FD
FE
FF

IN FM (DDEN

Write 00 thru F4 with ClK = FF
Not Allowed
Not Allowed
Generate 2 CRC bytes
Write Fa thru FB, ClK = C7, Preset
CRC
Write FC with ClK = 07
Write FD with ClK = FF
Write FE, ClK = C7, Preset CRC
Write FF with ClK = FF

IN MFM (DDEN

Write 00 thru F4, In MFM
Write A1* In MFM, Present CRC
Write C2** In MFM
Generate 2 CRC bytes
Write
Write
Write
Write
Write

*Mlsslng clock transition between bits 4 and 5.
**Mlsslng clock transition between bits 3 and 4.

116

Fa thru FB, In MFM
FC In MFM
FD In MFM
FE In MFM
FF In MFM

VLSI TECHNOLOGY, INC.
VL1772-02

TYPE IV COMMANDS
The Forced Interrupt Command is
generally used to terminate a multiple
sector read or write command or to
ensure Type I status in the status
register. This command can be loaded
into the command register at any time.
If there is a current command under
execution (Busy Status Bit set) the
command is terminated and the Busy
Status Bit reset.
The lower four bits of the command
determine the conditional interrupt as
follows:
10 =
11 =
12 ..
13 =

Don't Care
Don't Care
Every Index Pulse
Immediate Interrupt

The conditional interrupt is enabled
when the corresponding bit positions of
the command (13-10) are set to a 1.
Then, when the condition for interrupt is
met, the INTRa line goes high signifying
that the condition specified has occurred. If 13-10 are all set to zero (HEX
DO), no interrupt occurs but any command presently under execution is
immediately terminated. When using
the immediate interrupt condition (13 = 1)
an interrupt immediately is generated
and the current command terminated.
Reading the Status or writing to the
Command Register does not automatically clear the interrupt. The HEX DO is
the only command that enables the
immediate interrupt (HEX 08) to clear
on a subsequent load command register
or read status register operation. Follow
a HEX 08 with DO command.
Wait 16 Ils (double density) or 321ls
(single density) before issuing a new
command after issuing a forced interrupt. Loading a new command sooner
than this nullifies the forced interrupt.

when there is a current command under
execution, the Busy status bit is reset,
and the rest of the status bits are
unchanged. If the Force Interrupt
command is received when there is not
a current command under execution, the
Busy Status Bit is reset and the rest of
the status bits are updated or cleared.
In this case, Status reflects the Type I
commands.
The user has the option of reading the
status register through program control
or using the ORO line with DMA or
interrupt methods. When the Data
Register is read the ORO bit in the
Status Register and the ORO line are
automatically reset. A write to the Data
Register also causes both ORa's to
reset.

HEX VALUE OF BYTE WRITTEN
FF (or 00)

00
FE (10 Address Mark)
Track Number
Side Number (00 or 01)
Sector Number (1 thru 1A)
00 (Sector Length)
F7 (2 CRC's written)
FF (or 00)
00
FB (Data Address Mark)
Data (IBM uses E5)
F7 (2 CRC's written)
FF (or 00)
FF (or 00)

to be written, there is one Data Request.
**Continue writing until VL 1772-02
interrupts out. Approximately 369 bytes.

256 BYTES/SECTOR
Shown below is the recommended dualdensity format with 256 bytes/sector. In
order to format a diskette the user must
issue the Write Track comand and load
the data register with the following
values. For every byte to be written,
there is one data request.

The Busy Bit in the status may be
monitored with a user program to
determine when a command is complete, in lieu of using the INTRa line.
When using the INTRa, a Busy status
check is not recommended because a
read of the Status Register to determine
the condition of busy resets the INTRa
line.

NUMBER

The format of the Status Register is
shown below:
(BITS)

a
S1

NUMBER

OF BYTES
40
6
1
1
1
1
1
1
11
6
1
128
1
10
369**

Because of internal synchronization
cycles, certain time delays are observed
when operating under program 110 as
shown.

OF BYTES
60
12
3
1
1
1
1
1
1
22
12
3
1
256
1
24
668**

HEX VALUE OF BYTE WRITTEN

4E
00

F5 (Writes A1)
FE (10 Address Mark)
Track Number (0 thru 4C)
Side Number (0 or 1)
Sector Number (1 thru 1A)
01 (Sector Length)
F7 (2 CRC's written)
4E
00

F5 (Writes A1)
FB (Data Address Mark)
DATA
F7 (0 aa
t Add ress Mark)
4E
4E

Delay Req'd. I
Next Operation
FM
MFM
Write to
Read Busy Bit 48Jlsec 24Jlsec
Command Reg. (Status Bit 0)
Write to
Read Status
64",sec
32J.Lsec ** Continue writing until VL 1772-02
Force Interrupt Command stops any
Command Reg. Bits 1-7
16
interrupts out. Approximately 668 bytes.
command at the end of an internal micro
Write
Read Same
32J.Lsec
Jlsec
instruction and generates INTRa when
Register
Register
Non-Standard Formats - Variations in
the specified condition is met. Force
the recommended formats are pOSSible
Interrupt waits until ALU operations in
to a limited extent, if the following
progress are complete (CRC calculaRECOMMENDED ·126 BYTES/
requirements are met:
tions, compares, etc.).
SECTOR
1) Sector size must be 126,256,512 or
Shown below is the recommended
Status Register - Upon receipt of any
1024 bytes.
single-density
format
with
128
bytes/
command, except the Force Interrupt
sector. In order to format a diskette, the
2) Gap 2 cannot be varied from the
command, the Busy Status Bit is set and
user must issue the Write Track
recommend format.
the rest of the status bits are updated or
command, and load the data register
cleared for the new command. If the
3)
Three bytes of A1 must be used in
with the following values. For every byte
Force Interrupt Command is received
MFM.
Operation

117

VLSI TECHNOLOGY. INC.
VL1772-02

In addition, the Index Address Mark is
not required for operation by the
VL 1772-02. Gap 1, 3, and 4 lengths can
be as short as two bytes for VL 1772-02
operation; however, PLL lock up time,
motor speed variation, write-splice area,
etc. add more bytes to each gap to
achieve proper operation. For highest
system reliability, use the recommended
format.

Gap I
Gap II
Gap 111**
Gap IV

FM
16 bytes FF
11 bytes FF
6 bytes 00

10 bytes FF
4 bytes 00
16 bytes FF

MFM
32 bytes 4E
22 bytes 4E
12 bytes 00
3 bytes A1
24 bytes 4E

8 bytes 00
3 bytes A1
16 bytes 4E

* Byte counts must be exact.
.
**Byte counts are minimum, except exactly 3 bytes
of A1 must be written.

TABLE 3. STATUS REGISTER

BIT NAME

MEANING

S7 MOTOR ON
S6. WRITE PROTECT

This bit reflects the status of the Motor On output.
On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates
a Write Protect. This bit is reset when updated.
When set, this bit indicates that the Motor Spin-Up sequence has completed
(5 revolutions) on Type I commands. Type 2 & 3 commands, this bit indicates record
Type. 0 = Data Mark. 1 = Deleted Data Mark.
When set, it indicates that the desired track, sector, or side were not found. This
bit is reset when updated.
If S4 is set, an error is found in one or more 10 fields; otherwise it indicates
error data field. This bit is reset when updated.
When set, it indicates the computer did not respond to ORO in one byte time.
This bit is reset to zero when updated. On Type I commands, this bit reflects the
status of the TROO signal.
This bit is a copy of the ORO output. When set, it indicates the DR is full on a
Read Operation or the DR is empty on a Write operation. This bit is reset to zero
when updated. On Type 1 commands, this bit indicates the status of the IP
signal.
When set, command is under execution. When reset, no command is under
execution.

S5 RECORD
TYPElSPIN-UP
S4 RECORD NOT
FOUND (RNF)
S3 CRC ERROR
S2 LOST OATAi
BYTE
S1 DATA REOUEST
INDEX

SO BUSY

118

VLSI TECHNOLOGY, INC.
VL1772-02

FIGURE 4. TYPE III COMMAND WRITE TRACK FLOWCHART

-----.....

DELAY 6
INDEX PULSES

SETINTRQ
LOST DATA
RESET BUSY

119

VLSI TECHNOLOGY, INC.
VL1772-02

FIGURE 4. TYPE III COMMAND WRITE TRACK FLOWCHART (Cont.)

WRITE 2 CRC
CHARS. ClK
FF

WRITE FC
ClK
07

WRITE FO, FE OR
FB·F9, ClK
C7
INITIALIZE CRC

WRITE
BYTE OF ZEROES
SET DATA lOST

WRITE Al IN MFM
WITH MISSING
CLOCK INITIALIZE
CRC

WRITE C2 IN MFM
WITH MISSING
CLOCK

WRITE 2 CRC
CHARS.

120

VLSI TECHNOLOGY, INC.
VL1772-02

TABLE 4. READ DATA TIMING
CHARACTERISTIC

MIN

Raw Read Pulse Width

TYP

.200
.400
3

Raw Read Cycle Time

MAX

UNITS

CONDITIONS

3
3

JAsec

MFM
FM

JAsec

TABLE 5. READ ENABLE TIMING
READ ENABLE TIMING - RE such that: RJW
SYMBOL
tRE
tORR
tov
tOOH

CHARACTERISTIC

= 1, CS = O.
MIN

RE Pulse Width of CS
ORO Reset from RE
Data Valid from RE
Data Hold from RE
INTRa Reset from RE

TYP

MAX

UNITS

CONDITIONS
C L = 50 pf

300
200
150
8

nsec
nsec
nsec
nsec
JAsec

200
200
100
20

C L = 50 pf
C L = 50pf

Note: Worst case service time for ORO is 23.5 JAsec for MFM and 47.5 JAsec for FM.

FIGURE 5. READ ENABLE TIMING

OALS

0-7

----r--F'~DV-1

VALID
X___
r-'DDH--1

A/W _ _------J/~I----------'"\I\~-Cs

---~I't4-\-tAE·-~1

....41I-------tDAA-------l~~1
DAQ--------------------------~

\'----

121

VLSI TECHNOLOGY, INC.
VL1772-02

TABLE 6. WRITE ENABLE TIMING
WRITE ENABLE TIMING - WE such that: R/W
SYMBOL
t AS
tSET
tAH
t HLO
tWE
tORW
tos
tOH

= 0, CS = O.

CHARACTERISTIC

TYP

MIN

MAX

Setup ADDR to CS
Setup RIW to CS
Hold ADDR from CS
Hold RtW from CS
WE Pulse Width
DRO Reset from WE
Data Setup to WE
Data Hold from WE
INTRa Reset from WE

200
100

200

150

UNITS

CONDITIONS

nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
J.lsec

FIGURE 6. WRITE ENABLE TIMING

~~LS - - - -________________________--J)(

'SET~ ~

______~_L_ID

~'OS

_ _
R/W

*"_'OH--I
_
~ ~_tHLO

,\~_ _~Y

AO,Al

ORO

)(~_______

___________

~----tORW----~~

122

________________________

VLSI TECHNOLOGY. INC
VL1772-02

TABLE 7. WRITE DATA TIMING
SYMBOL

CHARACTERISTIC

MIN

TYP

Write Gate to Write Data

4
2
4,6,8
4
2
820
690
570
1.38

Write Data Cycle Time
Write Gate off from WD
twp

Write Data Pulse Width

FIGURE 7. WRITE DATA TIMING

123

MAX

UNITS

CONDITIONS

",sec
",sec
",sec
",sec
",sec
nsec
nsec
nsec
",sec

FM
MFM
FM
MFM
Early MFM
Nominal MFM
Late MFM
FM

VLSI TECHNOLOGY, INC.
VL1772-02

TABLE 8. MISCELLANOUS TIMING
SYMBOL

CHARACTERISTIC

tC01
tC02
t STP

Clock Duty (low)
CLock Duty (high)
Step Pulse Output

tOIA

Dir Setup to Step

tMR
tiP

Master Reset Pulse Width
Index Pulse Width

MIN

TYP

50
50

67
67
4
8
24
48

50
20

MAX

UNITS

nsec
nsec
",sec
iJsec

CONDITIONS

MFM
FM
MFM
FM

",sec
",sec

FIGURE 8. MISCELLANOUS TIMING

t - - - - - - - -.....1 1 ---------"""$

iP ...

VIH

~tIP~
MR

I I -----------i$

~Ir--------.....

~tMR---1

_______1

S~...---_ _

STEP IN

DIRC

STEP

124

VIH

VLSI TECHNOLOGY, INC.
VL1772-02

FIGURE 9. FORMATS
INDEX

~~~

~----
I-

WRITE GATE-.-J

SINGLE DENSITY FORMAT

INDEX

.---,

L - _____ _

~LSE----1

I-

L __ _

WRITEGATE~
DOUBLE DENSITY FORMAT

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

-10°C to +SO°C

Storage Temperature

-65°C to + 140°C

Supply Voltage to
Ground Potential

-0.5 V to +7.0 V

Applied Output
Voltage

-0.5 V to +7.0 V

Applied Input
Voltage

-0.5 V to +7.0 V

Power Dissipation

operational sections of this specification
is not implied and exposure to absolute
maximum rating conditions for extended
periods may affect device reliability.

Stresses above those listed under
"Absolute Maximum Ratings" may cause
permanent damage to the device. These
are stress ratings only. Functional
operation of this device at these or other
conditions above those indicated in the

SOOmW

DC CHARACTERISTICS

TA - O°C to 70°CI VCC - 5 V ± 5%

Symbol

Parameter

Min

VOH

Output High Voltage

2.4

VOL

Output Low Voltage

VIH

Input High voltage

VIL

Input Low Voltage

O.S

Typ

Max

0.4
2.0

Unit

Conditions

10 - -100 ~

10 -1.6 mA

ilL

Input Leakage Current

VIN -VCC

10L

Output Leakage Current

VOUT .. VCC

RPU

Internal Pull-up

1700

VIN=OV

ICC

Operating Supply Current

100
75
7S0

Power Dissipation

125

150

mA
mW

VLSI TECHNOLOGY, INC.
VL1772-02

APPLICATION INFORMATION
VL 1772-02: AN IMPROVED
VERSION
OF THE 1770-00
The 177X family of flexible disk controllers has attracted a great deal of interest
from system designers. Allowing
compactness and superior performance,
this family of advanced ICs has proven
to be a success in the marketplace. The
original 1770-00 won much approval
with its 28-pin package. Its digital data
separator allowed consistent operation
over temperature, but more was
required. The error rate of this data
recovery circuit was too high, and a
reliable data separator with lower error
rates was seen as an important need for
computer systems of all types. In
addition, a small change of step rate

selections could ensure faster throughput, while maintaining compatibility with
existing designs.
Thus began the design of a.new concept
in flexible disk controllers. An important
need was to maintain compatibility with
existing designs using the 1770-00,
while extending the capabilities of the
177X family to include higher-performance drives. These criteria have been
satisfied with the VL 1772-02.

IMPROVING THE DATA
SEPARATOR
The improvement of the data separator,
or data recovery circuit, as it is called, is
an important enhancement to the
reliability of the VL 1772-02. The

FIGURE 10. WINDOWING READ DATA

operation of this part of the circuit,
although critical to system reliability, is
simple to understand. Figure 10 shows
a train of read data pulses coming from
a floppy drive. The clock and data
pulses are both in this signal, combined
in a simple encoding format. In each bit
cell, the data separator chooses a time
period within which pulses are recognized as data pulses. The better the
resolution for defining this window for
the data pulses, the greater the jitter in
the signal can be before ones and zeros
are incorrectly recognized. This
incorrect recognition, and the resultant
soft errors, are the basic limiting factor in
floppy drive error rates. The VL 1772-02,
with a wider data window, has a lower
chance of incorrect recognition, resulting
in lower error rates. This effect will be
particularly evident as the user's media
degrades with use and jitter increases.
This increased reliability of the VL 177202 can result in fewer returns and
greater user satisfaction.

Clock

STEP RATES

I
I
I
I
I

L_..1

TAB LE 9. STEP RATE SELECTION: 1770-00
AND VL1772-02
Step Rate Select Bits
r1
rO

Step Rate (ms)
1nO-OO

VL1n2-02

With a different selection of step rates
than the 1770-00 (see table 9), the
VL 1772-02 allows the use of drives with
minimum settle times up to 12 ms. At
the same time, performance is enhanced to take advantage of floppy
drives that require only 2 or 3 ms of
delay. H a design is currently using
head settle times of 6 or 12 ms (as most
are), no modifications are required to
use the VL 1772-02 in the 1770-00
socket. H the current choice of r1 and rO
calls for 20 or 30 ms of delay, use of the
VL 1772-02 requires:
- the selection of drives that have
head settle time under 12 ms, and
modified software to allow correct r1, rO
choice, or
- implementation of head settle time in
hardware, with an external interrupt.
Fortunately, almost all modern flexible
disk drives have head settle times well
under 12 ms, and current 1770 applications have taken this into account, using
6 or 12 ms as the head settle time.
Where this change is required, it will
mean less waiting for the drives to finish
each seek. This will certainly produce
higher user satisfaction with the system,
as well as appreciably higher performance against most benchmarks.

126

VLSI TECHNOLOGY, INC
VL1935
SYNCHRONOUS DATA LINE CONTROLLER

FEATURES
• HDLC, SDLC, ADCCP and CCITT
X.25 Compatible
• SDLC Loop Data Link Capability
• Full or Half Duplex Operation
• DC to 2.0 Mbits/Sec Data Rate
• Programmable/Automatic FCS (CRC)
Generation and Checking
• Programmable NRZI EncodelDecode
• Full Set of Modem Control Signals
• Digital Phase Locked Loop
• Fully Compatible with Most CPU's
• Error Detection: CRC, Underrun,
Overrun, Aborted or Invalid Frame
Errors
• Straight Forward CPU Interrupts
• Programmable Modem Control
Interrupts
• Double Buffering of Data
• Variable Character Length (5, 6, 7 or 8
Bits)
• Residual Character Capability

• Global Address Recognition
• Extendable Address Field
• Extendable Control Field
• Automatic Zero Insertion and Deletion
• Maintenance Mode for Self-Testing
• Pin-Compatible Replacement for WD
1933 and WD1935

DESCRIPTION
The VL1935 is a MOSILSI microcomputer peripheral device which performs
the functioning of interfacing a parallel
digital system to a synchronous serial
data communication channel employing
ISO's HDLC, IBM's SDLC or ANSI's
ADCCP line protocol. These protocols
are referred to as Bit-Oriented Protocols
(BOP).
The chip is fabricated in N-channel
depletion load MOS technology and is
TTL compatible on all inputs and
outputs. This controller requires a
minimum of CPU software by supporting a comprehensive frame-level
instruction set and by hardware

implementation of the low level tasks
associated with frame assemblyl
disassembly and data integrity. It can
be programmed to encode/decode
NRZI data. The internal clock is then
derived from the NRZI data using a
digital phase locked loop.
The receiver and transmitter logic
operates as two total independent
sections with a minimum of common
logic. The frames are automatically
checked for errors during reception by
verifying correct Frame Check Sequence (FCS). In transmit mode, the
FCS is automatically generated by this
controller and sent before the final Flag.
It also continuously checks for other
errors. In case of an error, the CPU is
interrupted.
The controller recognizes and can
generate Flag, Abort, Idle and GA
characters. VL 1935 can be used in an
SOLC Loop configuration. An End of
Block option is supplied to minimize
CPU time. A full set of modem control
signals are supplied to minimize
external hardware.

• Address Compare

PIN DIAGRAM
VL1935

REOM
EOB

RE
es
Mise OUT
INTRO

ORDER INFORMATION
Part
Number

Clock
Frequency Package

VL1935-1 OPC
VL 1935-1 OQC
VL1935-1 OCC

0.5 MHz

Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
Ceramic DIP

VL1935-11 PC
VL 1935-11QC
VL1935-11 CC

1.0 MHz

Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
Ceramic DIP

VL 1935-12PC
VL 1935-12QC
VL 1935-12CC

1.5 MHz

Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
Ceramic DIP

02
03

04
05

Os
07
MR

OTR
OROO
DR01

VL 1935-13PC
VL 1935-13QC

2.0 MHz

Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
Ceramic DIP

VL 1935-13CC

GND

Note: Operating temperature range is O°C to +70°C.

127

VLSI TECHNOLOGY, INC.
VL1935

PIN DESCRIPTION

PIN
NUMBER

MNEMONIC

FUNCTION

SIGNAL NAME

REOM

Received End
of Message

Received End of Message with no Errors. This output signal is
the inverse of IR7, bit 7 of the Interrupt Register.

EOB

End of Block

This input, when low, function as an FCS command. Is independent
of CS.

Read Enable

This input, when low (and CS is active), gates the content of addressed register onto the Data bus.

Chip Select

This input, when low, selects the VL 1935 for a read or write operation
to/from the Data bus.

MISC OUT

Misc Output

This output is an extra programmable output signal for the convenience of the user. Is controlled by the CR10 bit.

INTRa

Interrupt
Request

This output is high whenever any of the interrupt register bits IR7-IR3
are set. TC must be asserted to assert INTRa.

Write Enable

This input when low (and CS is active), gates the content of the Data
bus into the addressed register.

DO-D7

Data Bus

Bidirectional three-state Data Bus. Bit 7 is MSB.

Master Reset

This input, when low, initializes all the registers, and forces the
VL 1935 into an idle state. The VL 1935 will remain idle until a command is issued by the CPU:

DTR

Data Terminal
Ready

Modem Control Signal. This output, when low, indicates to the Data
Communication Equipment (DCE) that the VL 1935 is ready to transmit or receive data.

DRaO

Data Request
Output

This output, when high, indicates that the Transmitter Holding Register
(THR) is empty and ready to receive a data character from the Data
bus for a transmit operation.

DRal

Data Request
Input

This output, when high, indicates that Receiver Holding Register
(RHR) contains a newly received data character, available to be read
onto the Data bus.

Vss

VSS

Ground

A2,AO,A1

ADDRESS

These inputs are used to address the CPU interface registers for read/
write operations.

MISC IN

Misc Input

This input is an extra input signal for the convenience of the user. The
state is shown by the SR4 bit.

Transmitted Data

This output transmits the serial data to the Data Communications
Equipment/Channel.

Receive Clock

This input is used to synchronize the received data.

Received Data

This input receives the serial data from the Data Communication
Equipment/Channel.

8 thru 15

21 thru 23

NRZI

This input, when low, sets the VL 1935 in NRZI mode.

CTS

Clear to Send

Modem Control Signal. This input when low, indicates that the DCE is
ready to accept data from the VL 1935.

1XJ32X

DPLL Select

This input controls the internal clock. When high (1 X clock), the external clock has the same frequency as the internal clock. When low
(32X clock), the external clock is 32 times faster than the internal clock
and the DPLL Logic is enabled.

Transmit Clock

This input is used to synchronize the transmitted data, as well as generating either Receive or Transmit INTRa's.

128

VLSI TECHNOLOGY, INC.
VL1935

PIN DESCRIPTION (continued)
PIN
NUMBER

SIGNAL NAME

MNEMONIC

FUNCTION

RTS

Request to Send

Modem Control Signal. This output, when low, indicates to the DCE
that the VL 1935 is ready to transmit data.

DSR

Data Set Ready

Modem Control Signal. This input, when low, indicates that the DCE
is ready to receive or transmit data.

Ring Indicator

Modem Control Signal. This input, when low, indicates a ringing signal
being received on the communication channel.

35
36

RIT,

Ring Indicator
Interrupt Control

These inputs are used to program Ring Indicator interrupts.

37
38

CD1, COO

Carrier Detect
Interrupt Control

These inputs are used to program Carrier Detect Interrupts.

Carrier Detect

Modem Control Signal. This input, when low, indicates there is a carrier signal received by the local DCE from a distant DCE.

Vee

+5VDC

TABLE 1.

RIO

VL 1935 GLOSSARY

TERM

DEFINITION/DESCRIPTION

BOP

Bit-oriented protocols: SDLC, HDLC, and ADCCP

ABORT

11111111 (seven or more contiguous 1's)

Go-ahead pattern. 01111111 (O(LSB) followed by seven 1's)

LSB

First transmitted bit and first received bit. (Least significant bit)

MSB

Last transmitted bit and last received bit. (Most significant bit)

IDLE

11111111 11111111 (15 or more contiguous 1's)

FLAG

01111110. Starts and ends a Frame.

A-FIELD

Address-field in the Frame. Consists of one or more 8-bit characters. Defines the address
of a particular station.

C-FIELD

Control field in the Frame. Consists of one or two 8-bit characters.

I-FIELD

Information field in the Frame. Consists of any number of bits.

FCS

Frame Check Sequence. A 16-bit error checking field sequence.

FRAME

A communication element, consisting of a minimum of 32 bits, and delimited by FLAGS.

GLOBAL ADDRESS

An A-field character of eight 1'so When this is compared and matched in the Address comparator, the DRQI will be set, indicating a valid address

RESIDUAL
CHARACTER

The last I-field character, consisting of a lesser amount of bits than the other I-field characters in the Frame.

DATA SET

Data Communication Equipment {DC E). May be a modem.

BIT TIME

Length in time of a serial data bit.

APPLICATIONS
COMPUTER COMMUNICATIONS

PACKET SWITCHING

TERMINAL COMMUNICATIONS

MULTIPLEXING SYSTEMS

COMPUTER TO MODEM INTERFACING

DATA CONCENTRATOR SYSTEMS

LINE CONTROLLERS

SDLC LOOP DATA LINK SYSTEMS

FRONT END COMMUNICATIONS

DMA APPLICATIONS

NETWORK PROCESSORS

COMMUNICATION TEST EQUIPMENT

TELECOMMUNICATION SWITCHING NETWORKS

LOCAL NETWORKS

MESSAGE SWITCHING

MULTIDROP LINE SYSTEMS

129

VLSI TECHNOLOGY, INC.
VL1935

FIGURE 1.

VL 1935 BLOCK DIAGRAM

~K[I~I~ISI§I§FoI5

A BRIEF DESCRIPTION OF HDLC, SDLC AND
ADCCP PROTOCOLS
The VL 1935 is compatible with HDLC, SDLC and ADCCP
standard communication Link Protocols. These are bit-oriented, code independent, and ideal for full duplex communication. A single communication element is called a FRAME,
which can be used for both link control and data transfer purposes.
The elements of a frame are the beginning eight bit FLAG
(F) consisting of one logical" 0 " six 1's and a 0, an eight bit
ADDRESS-FIELD(A), an eight bit CONTROL-FIELD (C), a
variable (N bits) INFORMATION-FIELD, a sixteen bit FRAMECHECK-SEQUENCE (FCS), and an eight bit end FLAG (F),
having the same bit-pattern as the beginning flag.
In HDLC, the address (A) and control (C) characters are
extendable (more than one character). An .important characteristic of a frame is that its contents are made code transparent by use of a zero bit insertion and deletion technique.
Thus, the user can adapt any format or code suitable for his
system. The frame is bit-oriented, meaning that, bits not
Figure 2.

VL 1935 TYPICAL SYSTEM INTERFACE
50·07

DTA
DSA
ATS

cs
MA
COMPUTER

SDLC

TO
AD

VL1935

FIGURE 3.

VL 1935 SDLC/HDLC/ADCCP
FRAME FORMAT

Where:
FLAG = 01111110
Address field-One or more 8-bit characters defining the
particular station
Control field-One or two 8-bit characters
Information field-Any number of bits (may be zero bits)
Frame Check Sequence-16-bit error checking field

characters in each field have ~pecific meanings. The Frame
Check Sequence (FCS) is an error detection scheme similar
to the Cyclic Redundancy Checkword (CRC) widely used in
magnetic disk storage devices. The frame format is shown
in Figure 3.

The following features are also part of these protocols.
MODEM

ZERO INSERTION/ZERO DELETION-Zero insertion/deletion is performed within the 2 Flags of a frame. If there are
more than five 1's in a row, a 0 is automatically inserted after
the fifth 1 and it is deleted upon reception by the receiver.
FRAME CHECK SEQUENCE (FCS)-A 16 bit cyclic redundancy check (CRC) calculation is performed during transmission of the data in between the 2 flags of the frame. The
CRC is then transmitted after the I-field and before the final
FLAG. Upon reception the receiver also performs a CRC
calculation on the incoming data. If there were no transmission error, the Receiver CRC equals FO B8 (hex).

130

"VLSI TECHNOLOGY, INC.
VL1935
HARDWARE ORGANIZATION
The VL 1935 block diagram is illustrated in Figure 1 and
described below.
CPU Interface Registers
All of these registers are addressable and to be read from
and/or written into by the CPU via the Data bus. These are
8-bit registers and have to be enabled via Chip Select (CS)
before any data transfer can be done.
CONTROL REGISTER 1,2,3 (CR1, 2, 3) Operations are
initiated by writing the appropriate commands into these registers. CR1 should be programmed last.
RECEIVER HOLDING REGISTER (RHR) When Data
Request Input is set (DROI= 1), contains received assembled character.
ADDRESS REGISTER (AR) Contains the address of the
accessed VL 1935, which is to be compared to the received
address character (A-field).
INTERRUPT REGISTER (IR) Contains the cause of the
current interrupt request.
TRANSMITTER HOLDING REGISTER (THR) Is to be
loaded with the next in line character to be transmitted, when
Data Request Output is set (DROO=1).
STATUS REGISTER (SR) Contains the overall status of
the VL 1935 plus some information of the last received
frame.
Non-Addressable, Internal Registers
These registers are transparent to the user, but is mentioned in these data sheets to help the understanding of the
VL 1935.
TRANSMITTER REGISTER (TR) This 8-bit register
functions as a buffer between the THR and the TD output.
It is loaded from the THR (if Data Command) with the next
character to be transmitted. A FLAG character may also be
loaded into this register under program control. This
character is automatically shifted out to the Transmit Data
output. When the last bit of the current transmitted character has left the TR register, a new character will be loaded
into this register, setting DROO (Data command) or INTRO
(Abort, Flag or FSC command). If at the time when only one
bit remains left in the TR register, and the THR is not loaded
or a new command is not programmed (Data command), an
underrun error will occur.
RECEIVER REGISTER (RR) The received data is, via
the Zero-Deletion logic shifted into this a-bit register. The
data is here assembled to a 5, 6, 7 or 8-bit character length
and then, under the right conditions, parallel transferred to
the RHR register.
FCS RECEIVE REGISTER AND FCS XMIT REGISTER
The VL 1935 contains a 16-bit CRC check register (FCS
REC. REG.) and a 16-bit CRC generation register (FCS XMIT
REG.). The generating polynomial is:
G(X) = X16

+ X12 + X5 + 1

The transmitter and receiver initialize the remainder value
to all ones before CRC accumulation starts. The data is
multiplied by X16 and is divided by G(X). Inserted o's are not
included in the accumulation. Under program control, the
complement called the frame check sequence (FCS) is sent
with high order bit first.

Various Internal Circuits
ADDRESS COMPARATOR This 8-bit comparator is used
to compare the contents of the Address Register with the first
address character of the incoming frame. This feature is enabled by a bit in the Command Register. If enabled and there
is a match, the received frame is valid and DROls are generated for every character received (including the A-field). If
enabled and there is not a match or there is no Global Address, the received frame is discarded. If not enabled, all received frames are valid and DROls are generated.
ZERO INSERTION The transmitted data stream is
continuously monitored by this logic. A zero is automatically
inserted following five contiguous 1 bits anywhere between
the beginning FLAG and the ending FLAG of a frame. The
insertion of the zero bit thus applies to the contents of the
Address, Control, Information Data, and the FCS field.
ZERO DELETION The received data stream is continuously monitored by this logic. Upon receiving five contiguous
1 bits, the sixth bit is inspected. If the sixth bit is a 0, it is
automatically deleted from the data stream. If the sixth bit is
a 1, the seventh bit inspected; if it is a 0, a FLAG is recognized; if it is a 1 an ABORT or GO AHEAD is recognized.
DATA BUS (D7-DO) This is an inverted 8-bit bidirectional data bus.
SDLC LOOP-MODE CONTROL This logic supervises
the VL 1935 running in SDLC Loop mode. It monitors the
received data for a GO-AHEAD pattern in the case when
SDLC LOOP MODE bit ((;R22) and ACT TRAN bit (CR16) are
set. When GO-AHEAD pattern is received, this logic suspends the repeater function and initiates the transmitter function. For more details, see functional description of SDLC
Loop Mode.
NRZI ENCODER/DECODER When this mode is selected, the NRZI Encoder encodes the "normal" transmitted
data to NRZI formatted data and the NRZI Decoder decodes
the received NRZI data to "normal" data.
A binary 1 for "normal data" is TD = high.
A binary 1 for NRZI data is TD = no change.
A binary 0 for "normal data" is TD

low.

A binary 0 for NRZI data is TD = change of state.
COMPUTER INTERFACE CONTROL This logic interfaces the CPU, to the VL 1935. It supervises the read and
write functions to the addressable registers, generates data
requests and interrupts, decodes and initiates commands,
monitors the status of VL 1935, etc.
MODEM INTERFACE CONTROL This logic interfaces
and supervises the modem control signals to/from the
VL 1935. It provides both dedicated (EIA Standard) and user
defined control functions.
CLOCK CONTROL This logic interfaces the transmit
and receive clocks to the VL 1935 . It converts the external
clocks to the necessary internal clocks.

FUNCTIONAL DESCRIPTION
SDLC Loop Mode
The diagram below shows an SOLC Loop Data Link System. VL 1935 can be used in any of these stations.

131

VLSI TECHNOLOGY, INC.
VL1935

FIGURE 4.

VL 1935 SDLC LOOP DATA LINK

Each secondary station is normally a repeater in Receive
mode (ACT REC bit on). The primary station is the loop controller. Signals sent out on the loop by the primary station are
relayed from station to station, then back to the Primary. Any
secondary station finding its address in the A-field captures
the frame for action at that station. All received frames are
relayed to the next station on the loop.
If a secondary station wants to transmit a message, it sets
the ACT TRAN bit (CTS must be low) and waits for a GO
AHEAD (GA) pattern. The ACT REC bit must be asserted for
detection of the GA and other existing patterns. Until the GA
pattern is received, this secondary station continues operating as a repeater. The primary station has the responsibility to
generate the first GA pattern which can be accomplished by a
flag followed by continuous 1'so The primary station must
continue to send 1's until the GA has circulated through the
entire loop. The first secondary station with its ACT TRAN bit
set detects the GA and changes the last 1 bit of the GA pattern to a 0, thus generating the start flag of the frame it wants
to transmit and preventing the GA pattern from propagating
down the loop. The repeater function is then suspended by
this secondary station and it goes into the transmit mode.
When this secondary station completes its transmission
frames, it resets the ACT TRAN bit and reverts back to the
repeater mode. It repeats the 1's generated by the primary
station to form another GA pattern from the final 0 of its end-

ing flag. The GA pattern propagates through the loop until a
secondary station down the loop, that wants to transmit (ACT
TRAN bit is set), intercepts the GA pattern and starts to transmit as described, or until the primary station receives the
idles (continuous 1's), indicating that the GA pattern has circulated through the entire loop. The primary station then generates another GA pattern or terminates its final data frame
with continuous 1'so
Repeaters (Secondary stations) delay the received data
by 4 bits (NRZ1 = 5 bits) before transmission.
The RC and TC clocks must be tied together. The internal
DPLL will not function in the loop mode.
1XJ32X Clock Option
When ·1 X clock is selected, the data rate equals tHe external clock (receiver and transmitter).
When 32X clock is selected, the external clock rate is 32
times faster than the data rate.
Dig ital Phase Locked Loop (DPLL)
This feature is particularly useful in NRZI mode and/or
when asynchronous modem is used. The purpose of the
DPLL is to synchronize the internal1X clock to the received
data, thus insuring that this data is sampled in the middle
of the incoming serial data bit. DPLL is automatically in operation when 32X clock is selected.
The DPLL Logic is initiated at the first received data
transition in a frame. Corrections, if needed, are then made
for each received data transition. A 32-counter is used for
this operation. At the beginning of each frame and at the
first received data transition, this 32 counter is reset. From
this time on, the counter increments with one count for
each external clock pulse. At count 16 the internal1X clock
is forced to change state to high (this transition
sampling time). At count 32, the counter resets itself. This
forces the internal 1X clock again to change state back to
low.

FIGURE 5. VL 1935 DPLL TIMING DIAGRAM

TC
(32X)

--I
RD

~5TC

------~~I--------------

(DATA)

NOTE 3

NOTE.

____________________~

~~R:;~~~~:~~ 1)

INTERNAL CLOCK

SAMPLE
DATA

NOTE 1. FIRST DATA TRANSITION (FIRST FLAG) SETS THE DPLL COUNTER TO 01.
NOTE 2. DATA TRANSITION IN BETWEEN HERE, OR NO DATA TRANSITION AT ALL, CAUSES NO CORRECTION OF THE
DPLL COUNTER.
NOTE 3. DATA TRANSITION IN BETWEEN HERE, WILL INCREMENT ONE COUNT TO THE DPLL COUNTER (ADD 01 TO
WHAT IS SHOWN).
NOTE 4. DATA TRANSITION IN BETWEEN HERE, WILL DECREMENT ONE COUNT TO THE DPLL COUNTER (SUBTRACT 01
TO WHAT IS SHOWN).

132

VLSI TECHNOLOGY, INC.
VL1935

At each received data transition, if the internal clock and
the received data is out of synchronization, a correction is
automatically made by :!: 1 external clock period. See DPLL
Timing Diagram in Figure 5.

will configure the VL 1935 for the user's specific data communication environment. These registers should be loaded
during power-on initialization and after a reset operation.
They can be changed at any time that the respective transmitter or receiver is deactivated. The CR1-3 dictate what the
transmitter will send: the type of character (DATA, 'ABORT,
FLAG or FCS), the number of bits per character, and the number of bits in the residual character. Similarly, they tell the
receiver the types of frames to look for: the number of bits per
I-field character, whether to perform an address compare,
and whether to watch for an extended address. The Control
Register also control Data Terminal Ready (DTR), Misc Out
and the activation of both the transmitter and the receiver. For
more detailed information, see Register Formats.

End Of Block CEOB)
This is an FCS command. The main purpose of EOB is to
allow the user to initiate FCS and FLAG without the need of
using extra computer time. This is particularly p;actical in
DMA applications. At the end of a frame, when the last information data character has already been loaded into the
THR and once again DRaO is set, either a regular FCS command is written into CR1 Register, or EOB is to be activated.
At the end of FCS, when INTRa is set (XMIT OPCOM), the
EOB if activated is to be reset again.

Monitoring Operation
Monitoring is done by uSE'! of the Interrupt Register (IR) and
Status Register (SR). The IR register indicates when a frame
is completed (transmitted or received), if there was an error
and if there is a Data Set Change. It also monitors the states
of INTRa, DRao and DRal.
The SR register indicates if an error is recognized by IR,
what type of error. It also monitors the modem control
signals; Ring Indicator (RI), Carrier Detect (CD), Data Set
Ready (DSR) and Misc in.
Furthermore, the SR register monitors if the Receiver is
idle, and also if in receive mode if the user has programmed
the Receiver Character Length to be 8 bits per character, this
register indicates the number of residual bits received. For
more detailed information, see Register Formats.

Serial Data Synchronization
The serial data is synchronized by the externally supplied Transmit Clock (iq and Receive Clock (RC). When 1X
clock is selected, the falling edge of TC generates new
transmitted data and the rising edge of RC is used to sample the received data. When 32X clock is selected, a 32counter (in th'e DPLL LogiC) is used to synchronize the internal clock. At time 0, when the counter is reset to 0, the
new transmitted data is generated. At time 16 (counter =
16) the received data is sampled, insuring that sampling is
done in the middle of the received serial data bit. At count
32, the counter is reset to 0 again.
Self Test (Diagnostic) Mode
This feature is a programmable Loop back of data, enabling the user to make a complete test of the VL 1935 with a
minimum of external circuitry. In this mode, transmitted data
to' the TD pin, is internally routed to the received data input
circuitry, thus allowing a CPU to send a message to itself to
verify proper operation of the VL 1935. The modem control
Signals DTR and RTS are deactivated (off) to insure no interference to/from the Data Communication Equipment (DCE).
DSR and CTS are internally activated for proper input conditions. TC and RC should be supplied by the sarne source if 1X
clock is selected.

PROGRAMMING

Read/Write Control Of CPU Interface Registers
These registers are directly accessible from the CPU bus
(D7-DO) by a read and/or write operation by the CPU.
The CPU must set up the VL 1935 register address (A2AO), Chip Select (CS), Write Enable (WE) or Read Enable
(RE) before each data bus transfer operation.
During a write operation, the falling edge of WE will initiate
a VL 1935 write cycle. The addressed register will then be
loaded with the content of the Data Bus (D7-DO). During a
read operation, the falling edge of RE will initiate a VL 1935
read cycle. The addressed register will then place its content
onto the Data Bus (D7-DO). The read/write operation is completed, when CS or RE/WE is brought high.
See Read/Write Timing diagram for more detailed information.
For read and write operation, the CR1-3 registers normally need no external clock. After reset of CR1-3, TC clock is
required. The AR and THR registers need no external clock,
and can only be written into. The RHR, IR and SR registers
need Transmit Clock (TC) or Receive Clock (RC) to set
various bits, and are read-only.
All these registers will get initialized by a Master Reset. A
read operation of RHR resets the DRal. A write operation
to THR, resets the DRaO. A read operation of IR, resets IR
bits 0 and 3-7. A read operation of SR, resets SR bits 0-2.
For addreSSing and external clocks needed, see TABLE 2.

Controlling Operation
Prior to initiating data transmission or reception, CONTROL REGISTER 1-3 (CR1-3) must be loaded with control
information from the CPU. The contents of these registers

A more detailed description is shown in Figure 6 of each bit
location. It should be known, that because the Data Bus
Lines (D7-DO) have inverted logic, a logic 1, asserted means
low state. Also, a modem control signal which is inverted
(example DTR), is in on-state (asserted) when low

Auto Flag
If this is selected and Data Command is executed, continuous Flags will be sent between frames. This eliminates the
need to execute the Flag Command. In DMA applications in
particular, this is very practical.
Extended Addressing
This type of addreSSing means, that there is more than one
address character in the A-field. In receive mode, the first
address character is compared in the Address Comparator of
the VL 1935. The other address character/s is to be compared by the CPU. The last address character is recognized
by the fact that the LSB (bit 2°) is a 1.

133

VLSI TECHNOLOGY, INC.
VL1935

TABLE 2.

DEVICE ADDRESS CODES

Read

Write

External Clock

l
L
L
L
L
L
H

H
H
H
H
L
L
X

H
H
L
L
H
H
X

H
L
H
L
H
L
X

CR1
CR2
CR3
RHR
IR
SR
X

CR1
CR2
CR3
AR
THR

None"
None"

L
H
X

"2.5 TC clock cycles are required
after a Master Reset to be able to
read and write.

10
CR1

= VIL at pins
= VIH at pins
= Don't care

Non~

RHR=RC. AR=None
IR='fC. THR=None
SRO-3=RC. SR4 -7=None.

DTR Command (CR11) This bit controls the data Terminal Ready (DTR) Signal to the data set. When CR11 is a
logical 0, DTR is off. When CR11 is a logical 1, DTR is on.
When the Self-Test mode is selected, DTR signal is forced
to an off state.
Transmitter Character length (CR13, 12) These bits
control the transmitted I-field data character lenQth. The
data character may be 5, 6, 7 or 8 bits long.

CR2

TABLE 3.
37

CR3

RHR

'1
XMIT
XMIT
REOM IRE,?M OPCOM OPCOM DSC
WI
WI
WINOlrRORS
~RROR
NO
UNDER
ERROR RUN

ORal

DRQO

INTRa
IR

THR

FIGURE~.

TRANSMITTER CHARACTER LENGTH

Vl1935 BIT ASSIGNMENTS

Control Register 1 (CR1)
When initiating a transmit/receive operation, this should be
the last register programmed.
Miscellaneous Output (CR10) This bit controls the Miscellaneous Output signal to the data set. When CR10 is a
logical 0, Misc Out is off, when it is a logical 1, Misc Out
is on.

CR13 (TCL1)

CR12 (TClO)

0
0
1

0
1
0
1

Bits Per
Character

8
7
6
5

Transmitter Commands (CR15, 14) These bits control
the transmission of DATA (A-field, C-field and I-field), ABORT,
FLAG, and FCS (FCS plus FLAG). When these commands
are programmed, the previous command currently still !n
progress, will complete the transmission of its character.
When this is done, a new character generated by this new
command, will be transmitted.
CR 14, 15 can be programmed as follows:
A. If DATA is programmed, the new character to be transmitted will be the character loaded (or still to be loaded) in the
THR REGISTER.
B. If ABORT is programmed, the new character will be eight
logical1's.
C. If FLAG is programmed, the new character will be
01111110.
D. If FCS is programmed, the new character which will be
transmitted consists of the residual byte (which was automatically transferred to the XMIT REGISTER, provided
that CR30-32 and are set correctly), followed by the 16-bit
content of the FCS XMIT REGISTER and the FLAG.
One serial bit ahead of this new character (for FCS command the FLAG Character), the CPU is signalled by DRaa or
INTRa that the VL 1935 is again ready to receive a new command. DRaa is asserted by a DATA command and INTRa
(XMIT OPCOM) is asserted by an ABORT, FLAG or FCS command.

134

VLSI TECHNOLOGY, INC
VL1935

TABLE 4.

TRANSMITTER COMMANDS

CR15 (TC1)

CR14 (TCO)

o
o

Command
DATA
ABORT
FLAG
FCS

In the case of the DATA command the user has two
choices; 1. Change the command. 2. Keep the DATA command and load a new character into the THR register. For
more information, please see the Transmission Timing diagram, Figure 7. See Table 4 for programming information.
Activate Transmitter (CR 16) This bit when set, enables
the transmitter and sets RTS signal. If in SOLC Loop Mode
(CR22 = set), the transmitter waits for a Go-Ahead pattern
before the transmitter is enabled.
Activate Receiver (CR 17) This bit when set activates
the receiver, which begins shifting in frames one character
at a time into RR register for inspection.
CONTROL REGISTER 2 (CR2)
Auto Flag (CR20) When set, Flags (without INTROs) will
be continuously transmitted in between frames, when otherwise the transmitter would be in idle state.
Self-Test Mode (CR21) When set, the Transmitter Data
Output is internally connected to the Receiver Data input
circuitry. The, modem control output signals are deactivated
(off state). The modem control input signals are internally
activated. This mode allows off-line diagnostic.
SDLC Loop Mode (CR22) When set, the VL 1935 is
cond itioned to operate in an SOLC Loop Data Link system
(see SOLC Loop Mode).
Receiver Character Length (CR24, 23) These bits indicate to the receiver how many bits per character there are
to assemble for the I-field. The I-field characters may be 5,
6, 7 or 8 bits long. The ,unused bits read from RHR will be
10gical0.
TABLE 5.

RECEIVER CHARACTER LENGTH

CR24
(RCL1)

CR23
(RCLO)

Bits Per
Character

0
0

0
1
0
1

8
7
6
5

TABLE 6.

Character/s Transmitted

Signal to CPU

Content of THR
1111 1111
0111 1110
FCS + 01111110

OROO
INTRO
INTRO
INTRO

Extended Address (CR25) When set, this bit indicates
to the receiver that there is more than one address character
in the A-field. The receiver will expect another address character if the LSB in the current address character is a logical O.
The purpose of this bit: If a non-8-bit field character length is
expected, the OROls will get out of synchronization i.f the
VL 1935 does not know exactly when the I-field will start. Not
used in transmit mode.
Address Compare (CR26) When set, the first address
character will be inspected in the Address Comparator. If
there is a match with the AR register, or if the address compared is a Global Address (eight 1's) the frame is considered
valid, causing OROls to be generated. Otherwise, the receiver does not react, and will continue comparing for a new
valid address. If not set, all frames are considered valid.
Extended Control (CR27) When set, indicates that
there are two control characters per name. If not set, there is
only one control character per frame. The purpose of this bit:
If a non-8-bit I-field character length is to be received, the
DROls will get out of synchronization if the VL 1935 does not
know when the I-field win start. Not used in transmit mode.
CONTROL REGISTER (CR3)
Transmit Residual Character Length (CR32, 31, 30)
(Table 6) These bits inform the transmitter what bit-length the
residual character will be. If no residual character is to be
sent, these bits must be set to logical O. (See Transmitter
Commands).
Unused (CA33-37) These bits are not used, and are
always a logical O.
INTERRUPT REGISTER (IR)
This register contains the information why an interrupt
INTRO was generated. An IR register read operation, will
reset bits 0, and 3-7. The Transmitter clock must be active to
generate an interrupt.
Loading the THR register, will reset OROO (bit 1). Reading
the RHR register, will reset OROI (bit 2). A new interrupt will
occur if one is pending.

TRANSMITTER RESIDUAL COMMANDS
CR32
(TRES 2)

CR31
(TRES 1)

CR30
(TRES 0)

Residual Char. Length

0
0
0
0
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

No residual char. sent
1 bit
2 bits
3 bits
4 bits
5 bits
6 bits
7 bits

135

VLSI TECHNOLOGY, INC.

TABLE 7.
CD1
LO
LO
HI
HI

VL1935
DATA SET CHANGE PROGRAMMING
COO
LO
HI
LO
HI

Interrupting edge of CD
Rising and falling
Falling
Rising
None

If a new interrupt is generated while the CPU is reading
the IR register, this new interrupt will set the respective bit
in the IR register one bit time later (this to avoid losing any
interrupt). The status of bits 3-7 will accumulate until the IR
register is read by CPU.

RIT

RiO

Interrupting edge ofRi

LO
LO
HI
HI

LO
HI
LO
HI

Rising and falling
Falling
Rising
None

If REOM WITH ERROR (IR 6) is set, these bits indicate the
type of error that occurred (Table 9).
TABLES.

INTRa (IRO) When set, indicates an interrupt and that
there are one or more bits set in positions 3 through 7 of this
register. This bit is a mirror image of INTRa signal (pin 6).
When pin 6 (INTRa) is not used for pending interrupts
information and only the IR register is read to obtain the
status of the interrupt bits (polling method), a minimum of
two (2) bits times must be allowed between IR registers
"read's" to insure an orderly flow of pending interrupts.

CHAR.
LENGTH
8
Bits/Char.

DRaO (IR1) When set, indicates a Data request output.
This bit is a mirror image of DRaO signal (pin 18).
7
Bits/Char.

ORal (IR2) When set, indicates a Data Request input.
This bit is a mirror image of ORal signal (pin 19).
Data Set Change (IR3) When set, indicates a change of
state of the Data Set (Data Communication Equipment). This
is a change of state ofDSR, CD orWThe type of change of
CD andRi that this bit will react to, is programmed by use of
input signals CD1/CDO and R11/R10 (Table 7).

6
Bits/Char.

XMIT Operation Complete with Underrun Error
(IR4) When set, indicates that the transmitter command
has been completed and there was an Underrun error. An
Underrun error occurs when the Data Request Output
(DRaO) is set, but THR register is not loaded in time.
XMIT Operation with No Error (IRS) When set, indicates that the transmitter command has been completed and
there was no error.
Received End of Message With Errors (IR6) When set,
indicates that a Received End of Message is detected, and
there was an error. Errors include CRC, Overrun, Invalid
Frame and Aborted Frame.
The SR Register bits 0-2 will indicate the exact type of
error.
Received End of Message With No Error (IR7) When
set, indicates that a Received End of Message is detected,
and there was no error. ThelR7 bit is the inverse of the
REOM output signal.
STATUS REGISTER (SR)
This register contains the status of the receiver and some
modem control signals. It also indicates (if REOM w/Errors)
exactly what type of errors. If the Receiver Character Length
is 8 bits, this register indicates the amount of Residual bits
that was received. A read operation will reset bits 0-2.
Received Error/Received Residual Character Length
(SR 2-0) If REOM wiNO ERROR (IR7) is set, these bits (SR 20), indicate the number of residual bits received (Table 8).

5
Bits/Char.

RES.
BITS

0
1
2
3
4
5
6
7
0
1
2
3
4
5
6

0
1
2
3
4
5
0
1
2
3
4

S
R
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
1
1
1
0
0
0
0
0
0
1
1

S
R
1

0
0
1
1
0
0
1
1
1
1

0
0
1
1
0
0
0
1

0
1
1
0
1
1

0
0

S
R
2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
1
0
1

TABLE 9.
Bit Set

Error

SRO
SR1
SR2

CRC
Overrun
Aborted or
Invalid frame

Receiver Idle (SR 3) When set, indicates that the receiver is currently IDLE.
Miscellaneous Input (SR4) This is a mirror image of
MISC IN signal. When this signal is set, SR4 bit is set.
Data Set Ready (SRS) This is mirror image of DSR signal. When this signal is set, SR5 bit is set.
Carrier Detect (SR6) This is a mirror image of CD signal.
When this signal is set, SR6 bit is set.

136

VLSI TECHNOLOGY, INC.
VL1935

Ring Indicator (SR7) This is the inverse of the Ai signal.
When SR? bit is set, a ringing signal has been received on
the communication channel.
TRANSMITTER OPERATION
Prior to this operation, the programmable inputs and the
transmit mode related register bits need to be programmed
according to the user's specific data communications environment. The last bit to be set is always the ACT TRAN
(CR16) bit.

Also, the ACT TRAN bit should be kept set in between
frames. Every time DRaO gets set, the user must load the
THR register before the last loaded character only has 1.5
bits left to be transmitted. In other words, when DRaO gets
set, the user may wait (if a-bit characters) up to 7.5 serial
data bits before loading the THR. If THR is not loaded within
this time, an Underrun error will occur.
If Auto Flag is not selected (CR20 = logical 0) the sequence
will be a little different than described below. When the first
DRaO is set, and after the Address character is loaded into
THR, a Flag command is also programmed (CR15, 14 = 10).
This will set an interrupt (INTRQ), which indicates that the
IR register must be read. Now, the Data Command is reprogrammed (CR15, 14 =00).
For more information, see Transmission Timing diagram.

Before this, the INTRa has to be cleared, which can be
done by reading the IR register. For more detailed information
how to program the VL 1935 see Programming.
As an example of how to program the VL 1935 let's
assume a 24-bit information is to be transmitted. The I-field
would then consist of three a-bit characters with no residual
bits. CR3 should then be 00 (Hex).
Bits CR23-CR27 are for reception only (see Receiver
Operation). The last register to be programmed is CR1. If
MISC OUT is not used, this may be ignored. If a modem is
used, DTR (CR11) is to be set. CR13 and CR12 should be
logical a's (8-bit char. length). CR15 and CR14 should be
logical a's (Data Command). ACT TRAN (CR16) bit is to be
set. The ACT REC (CR17) is for reception only.
The DTR bit, when set, activates the DTR signal, indicating to the modem to prepare for communication. When the
modem is ready, it sends back a Data Set Ready (DSR) to the
VL 1935 . This causes the DSC (IR3) bit to set, which in turn
activates INTRa. The IR register is now read. Simultaneously, when the ACTTRAN (CR16) bit is set, this activates the
Request to Send (RTS) signal, instructing the modem to enter
into transmit mode. When the modem is ready to transmit
data, it responds by activating the Clear to Send (CTS) signal.
The VL 1935 is now conditioned to transmit. Now DRaO
gets, set, indicating to the CPU (or DMA) to load the first character (Address) into the THR. When this is done, DRaO will
reset. As soon as the VL 1935 is ready to be loaded with the
next character to be transmitted, DRaO is again set. When
the THR register is again loaded with a character, DRaO will
again reset.
This same sequence continues until the last I-field character to be transmitted is loaded into the THR. If CRC checking is to be used, the next time when DRaO is set, an FCS
command has to be programmed. This is accomplished bv
either setting CR15, 14 to both logical1's or by activating the
EOB signal.
At the end of the FCS being transmitted, INTRa will set
indicating XMIT Operation Complete. The IR register is to be
read to find out whether the frame was sent with or without
error. Also the FCS Command which was used as described
above has to be changed. If CR15, 14 were set, these have
to be reset (to Data Command), or if EOB was activated, this
signal has to be deactivated. At this same time, the ACT
TRAN bit is allowed to be reset, causing the TO output to go
idle after the end Flag is sent. If the ACT TRAN bit is kept
set, continuous Flags will be sent following the FCS.
If a new frame is to be sent right after this first frame, only
one Flag is needed in between frames, meaning the frames
have one common Flag character. In this case, the second
frame Address character may be loaded at the same time
the FCS command is programmed during the first frame.

ABORT CONDITIONS
The function of prematurely terminating a data ·Iink is
called an "Abort." The transmitting station aborts by sending eight consecutive 1's. Unintentional Abort caused by
1's in the A-C- or I-field is prevented by zero insertion. Intentional Abort may be sent by programming an Abort command. Abort will also be sent in the case where THR is not
loaded in time or FCS command is not programmed in time
(= underrun). This means that after the DRaO is set, to
avoid Abort; THR must be loaded, EOB activated or FCS
command programmed before there is only 1.5 bits left of
the last character to be transmitted.
If this is not done, INTRa (XMIT OPCOM w/underrun) is
set and Aborts are transmitted until, either the command is
changed or the THR is loaded. If in this same case, Auto
Flag was programmed, one Abort (with INTRa) would be
generated, and thereafter continuous Flags (with no INTRas)
will be sent.
RECEIVER OPERATION
Prior to this operation, the programmable inputs and the
receive mode related register bits have to be programmed
according to the user's specific data communication environment. Also, the INTRa has to be cleared. The last bit to be
set is always the ACT REC (CR17) bit.
For more detailed information how to program the VL 1935
see Programming. As an example, let's assume a 26-bit information is to be received, and the I-field is made up by a-bit
characters. The CR3 register is only for transmit mode, and
may be ignored here. CR20 and CR 12-16 bits are also for
transmit mode only, and therefore may also be ignored. CR21
and CR22 are to be logical as (no Self-Test and no SDLC
Loop Mode). CR24, 23 are to be logical a's (a-bit character Ifield). If only one A-field and one C-field character is
expected, and this VL 1935 has a specific address, CR25
should be a logical a, CR26 should be a 1, and CR27 should
be a O. The address to which the A-field should compare
should be loaded into the AR register.
The status of the modem is monitored by the SR register,
and it may be useful to read it at this time. CR1 is loaded as
the last register. CR10 (Misc In) bit is optionable to the user.
CR11 (DTR) is to be set if modem is used. CR17 (ACT REC)
is now set, starting the input of frame characters into the
Receiver Register (RR). When Flag is detected, the next

137

VLSI TECHNOLOGY, INC.
VL1935

8-bit character (address-character), when received, is compared to the character in the AR register. If these match, or
if the received character is a Global address, this frame is
valid, and the DROI gets set. If the Address Comparator
(CR26) bit is not set, all frames would be considered valid
and generate DROls. When the RHR register is read, DROI
will be reset. All characters in a valid frame which are input
into the RR register will set DROI, and every time RHR is
read by the CPU, DROI will be reset.
During reception, the receiver also performs a CRC calculation on the incoming data. When the end Flag is received, INTRa will get set, indicating Received End of
Message. If the reception is completed with no error, IR7
(REaM wino Error) bit will be set. When 8-bit characters are
received SR 0-2 bits indicate the number of residual bits, in
this case two. If IR6 (REaM wlError) was set, SR 0-2 bits
indicate the type of errors (see Receiver Error Indication).
When all characters including the A-field and the FCSfield are read, and when the REaM interrupt is recognized,
it is up to the user to disassemble these mentioned characters from the received data. If non-8-bit characters are received, the amount of residual bits have to be calculated by
the CPU after masking out the part of the ending Flag
showing up in the last read character.
After end of frame, the receiver begins searching for a
new frame.

CRC Error (SRO) If the CRC calculation performed on
the incoming data does not equal to FOBS (HEX); this bit will
be set.
Overrun Error (SR1) After DROI is set, if the RHR is not
read within one character minus one bit time, this bit will be
set.
.
Aborted or Invalid Frame Error (SR2) If the frame is
aborted or if in a frame the number of bits between flags are
less than the required minimum (see Table 10), this bit will be
set.
NOTES
1. TCcommand-1f two or more contiguous ABORTS or
FLAGS are executed, the ACT TRAN (CR16) bit has. to be
reset before DATA-command can be executed.
2. Master Reset (MR)-Needs no clock during activation of
MR. However, 2.5 clock cycles are required to reset the
VL 1935 after the falling edge of MR.
3. IR-register-Immediately when IR register is read, bit 0
will reset. Bits 3-7 are reset one bit time later.
4. SR-register-Bits 0-2 are reset one bit time after SR register is read.
5. SDLC Loop mode-Go-ahead pattern may be sent by
either sending IDLE or ABORT after Flag.
6. TC and RC clocks are completely independent of each
other.

(For more information, see Figure 8.)
RECEIVER ERROR INDICATION
When a frame is received, and REaM w/Error (IR6) is set,
the type of error is indicated by the SR bits 0-2.

7. It is recommended to verify that the INTRa Signal (pin 6)
is set prior to reading the IR register.
8. End Of Block (EOB) - Minimum activated time must be
one (1) character time. It can be activated indefinitely
using IDDLE or AUTO FLAG (CR20).

TABLE 10.
Valid Frame For VL 1935
Receiver Programmed for

7 bit char

8 bit char

6 bit char

5 bit char

1 address, 1 control

~25

bits

~23

bits

~21

bits

~19

bits

2 addresses, 1 control
1 address, 2 controls

~25

bits

~24

bits

~23

bits

~22

bits

3 addresses, 1 control
2 addresses, 2 controls

~25

bits

~25

bits

~25

bits

~25

bits

138

VLSI TECHNOLOGY, INC
VL1935

FIGURE 7.

VL 1935 TRANSMISSION TIMING DIAGRAM

TC
(lX CLOCK)

PATASITS

DROO

I~I

-1

1-1 DATA
BIT

THA
LOADED

D~~A

r
--~----------------------~~____________________~r---l~_____
IA
READ

SITS

INTRa

t -L

~:- ...~

::f w

0 0

fEE-

ljl
>~a:

tO~

~~~

'" a:","
@ ~9Q

-L -L
S
<5
~~a:
o.e~

~~~
~9Q

~offi

~~~
~~~

~95

t
w

E ~~

~§
... ~~

aa:
l:

NOTE 1. CR3 = OOH, CR2 = 01H, CR1 = 02H (FQB THIS EXAMPLE ONLY)
NOTE 2. WRITE FCS COMMAND, OR ACTIVATE mB.
NOTE 3. INF. DATA MAY CONSIST OF ANY NUMBER OF BITS.

FIGURE 8.

VL 1935 RECEPTION TIMING DIAGRAM

------fFCS

IDLE

D;TArBITS
DAOI

---i
INTRa

r
-:-

u
a:

-L -L

-L

--.

~~~
o5t u

~~~

~~~~

SNCC

a:a:u

~~Q

it~

--.
ljl

~~~
l:wl:

<5
o a: a:

gu~

l
~

a:a:u

o~~~

~"'~
o~~

NOTE 1. AR = 19H. CR2 = 40H, CRl = 02H (FOR THIS EXAMPLE ONLY)
NOTE 2. INF. DATA (I·FIELD) MAY CONSIST OF ANY AMOUNT OF BITS.
NOTE 3. CPU DOES NOT KNOW UNTIL RECEIVED END OF MESSAGE (REOM) THAT THIS IS AN FCS CHARACTER.

139

IIL

t
!!:~

a:!5.

LIR
AEAD

VLSI TECHNOLOGY, INC.
VL1935

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Storage Temperature
Storage Temperature
Voltage on any pin
with respect to GND (Vss)
Power Dissipation
DC Characteristics
TA = O°Cto +70°

-55°C to +125°C (plastic package)
-65°C to +150°C (ceramic package)
-0.3 to +7.0 V
1W
VSS=OV,VCC=+5±0.25V

TABLE 11. VL 1935 DC CHARACTERISTICS
Symbol
III
ILO
VIH
VIL
VOH
VOL
ICC

Parameter

Max

Units

2.4
0.8
2.4
0.4
210

Conditions

/-I A
/-I A

VIN = VCC
VCC or VSS
VOUT

V
V
V
V
rna

All Inputs
-1oo/-lA
10
10 = 1.6mA

10
10

Input Leakage
Output Leakage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Supply Current

AC Characteristics
TA = O°C to +70°

Typ

Min

VSS=OV, VCC=+5±0.25V

TABLE 12. VL 1935 AC CHARACTERISTICS
-10
Symbol

Parameter

Min

TAS
TAH
TCSS
TCSH

READ & WRITE (Fig. 9, 10)
Address Set·Up
Address Hold
Chip Select Set·up
Chip Select Hold

TRED
TDV
TDRQIR
TINTRQF
TRE

READ (Fig. 9)
Data Delay from RE Asserted
Date Valid from RE Deasserted
0
DRQI Reset Delay
INTRQ Reset Delay
RE Pulse width
325

WRITE (Fig. 10)
DataSet·up
TDS
Data Hold
TDH
TDRQOF DRQO Reset Delay
WE Pulse width
TWE

-12

-11
Max

20
20
20
20

Min

Max

Min

290
0

Max

140
280
280

Min

Max

20
20
20
20

20
20
20
20
315
140
280
280

-13

ns
ns
ns
ns

20
20
20
265
140
280
280

300

275

250

180
20

160
20

140

Units Conditions

240
140
280
280

ns
ns ,
ns
ns
ns

330

ns
ns
ns

125

ns
ns
ns

1.0

1.5

2.0

1.0

1.5

2.0

2.5

20
~

20
20

200
20

330

20
330

200

180

160

140

TRDS
TRDH
TTDO

TRANSMIT& RECEIVE (Fig.11)
Receive DataSet Up
150
Receive Data Hold
150
Transmit Data Out Delay

150
150

125

1xFc

CLOCK
1X Clock

32xFc

32XCIock

TR
TF

RISE & FALL (Fig. 12)
RiseTime
Fall Time

NOTE: All A.C. Timing Measurements made at 0.8 V and 2.0 V.

140

MHz at 50% duty
cycle
MHz at 50% duty
cycle
ns
ns

See figure 1

VLSI TECHNOLOGY, INC.
VL1935

FIGURE 9.

VL 1935 READ TIMING DIAGRAM

HIGH IMP. STATE

~--------------~
NOTE 1)

~ ---~

HIGH IMP

07·00

STATE

VALID

~ (NOTE 1)

AO. A1, A2

1'~-----I~-

RE-----""_~

VL 1935 WRITE TIMING DIAGRAM

_To v

;., 1-

TCSS-4
DROI ___

VALID

r---------- -y ____ _
TRE

~==x-

FIGURE 10.

¥r-

TOROOR

DRaa

T_OR_O_IR_ _ _......

INTRo-----t----..t''''"'"
NOTE 1. TREO and TOV starts from where bQth
CS and ltE' are active.

FIGURE 11.

RECEIVER AND TRANSMITTER TIMING

FIGURE 12. VL1935 RISE AND FALL TIMING DIAGRAM

141

VLSI TECHNOLOGY, INC

FIGURE 13.

VL1935
VL 1935 TRANSMITTER FLOW CHART

SOlCRIEPEATER

MODE

~~IT SEETN~~~~~E~~A~.S::6RT OR IDLE
~Ee; C~:~~gZ ;~~N~E,,~ 2F~~UNTS I
81TCOUNTEROEFAUtTS TO

EIGHT 81T CHAFIACTERS

142

BITS

VLSI TECHNOLOGY, INC.
VL1935

FIGURE 14.

VL 1935 RECEIVER FLOW CHART
MASTER
RESET

NOTE: STATE 0 IS WHERE WE SEARCH fOR OR
HAVE FOUND THE OPENING FLAG AND SYNC
THE fRAME TO IT. AfTER THE OPENING flAG
HAS BEEN DETECTED WE GO TO STATE 1.

RECEIVE BIT COUNTER - MODULO COUNTER
USED TO PROGRAM THE NUMBER OF
BITS PER CHARACTER & CALCULATE THE
NUMBER OF RESIDUAL BITS.

(START fRAME,

NOTE: IN STATE 1 WE ARE IN SYNC
WITH THE INCOMING DATA AND WE
INCREMENT BY CHARACTER UNTIL THE
FRAME ENOS OR IS ABORTED
(lNTRO)

(1- FRAME)

ICR2')
RCL 1

o
o

(CR23)
RCLO

BITS PER
CHAR

143

VLSI TECHNOLOGY, INC.

144

VLSI TECHNOLOGY, INC.
VL2010
16 X 16 PARALLEL MULTIPLIER·ACCUMULATOR

FEATURES

DESCRIPTION

• 16 x 16 parallel multiplication and
product accumulation

The VL2010 is a 16 x 16 parallel multiplier-accumulator (MAC) that offers
ultra-low power consumption and very
high performance. High performance is
achieved through the use of the
efficient Booth's algorithm and
advanced VLSI processing technology.

• High-speed multiply-accumulate time
-65 ns, typical
-90 ns, max
• CMOS silicon-gate technology
• Single 5 V supply
• Low power
-0.2 W typical
• Standard TIL-compatible 1/0 levels
• Performs double-precision subtraction, addition, and multiplication,
including rounding control
• Pin-far-pin functional replacement for
VVTL1010, VVTL2010,
TDC1010J, LMA1010, and
AMD29510
• 64-pin ceramic and plastic DIP
• 6a-terminal plastic leaded chip
carrier (PLCC)

The VL201 0, under control of the ACC
input, performs either the multiply only,
or the multiply-accumulate function. In
either mode, input data X and Y can
be specified as two's complement or
unsigned magnitude. Input data
representation is selectable via the
input control line, TC. In the multiplyonly mode, extended product (XTP)
data is sign-extended or set to zero for
two's complement and unsignedmagnitude arithmetic, respectively. An
RND control is available for rounding
up the most significant product (MSP)
and extended product (XTP) data. In
the multiply-accumulate mode, the
double-precision accumulated answer
is rounded back to single-precision or
single-precision plus XTP bits.

BLOCK DIAGRAM

The VL2010 architecture includes input
and output data registers, as well as
three-state output data buses with independent, non-registered control.
Time-multiplexing is used for the
common least significant product (LSP)
and Input Data raJ/O lines. Input lines
TSX, TSM, and TSL, respectively,
control the outputs of the XTP, MSP,
and LSP registers.
In the multiply-accumulate mode (ACC
active), output data can be added to or
subtracted from the last product. When
SUB is also active, subtraction occurs.
Otherwise, addition is performed.
The VL2010 can be efficiently applied
in a variety of digital signal processing
functions, including digital filtering
(recursive, non-recursive, wave) and
FFT processing (complex multiplication, butterfly computation). In addition,
the VL2010 can be employed effectively in upgrading the computational
capability of mini- and microcomputer
systems.

ORDER INFORMATION
Multlplyl

YtLSP .
Part

Number

Accumulate
Time
Package

VL2010-90CC
VL2010-90PC 90 ns
VL2010-90aC

Ceramic DIP
Plastic DIP
PLCC

Note: Operating temperature range is
O°C to +70°C.

elK

PREL~~=:t::==+=:::;:::=1;::::=t==::;-4
TSX---+-...J
TSM--~-~---~~

TSL---r--+---~--+-----+~

XTP

MSP

lSP

145

VLSI TECHNOLOGY, INC.
VL2010

PIN DIAGRAM

VL2010-QC

X4
X5

TSL 1
Y2,P2

RND

Y3,P3

CLKX 1
CLKY 1

Y6,P6

Y7,P7
GND
5

GND
Y8,P8

Y10,P10
Y11,P11

Y13,P13
4

Y14,P14
Y15,P15

146

VLSI TECHNOLOGY, INC.
VL2010
PIN DIAGRAM

PIN DESCRIPTIONS
X
Data Input
X is a 16-bit input. Data bits are loaded
on the rising edge of CLKX.
Y/LSP
Datalnputl
Data Output
These pins share functions between Y
(16-bit data input) and LSP (least
significant product output). Input data
bits are loaded on the rising edge of
CLKY. Output LSP data bits are
available following the rising edge of
CLKP.
MSP
Data Output
The 16-bit most-significant product
output. MSP data is available following
CLKX,CLKY
Input Clocks
These X and Y data input register
clocks are active on their rising edges.
ACC
Accumulate
A HIGH level input permits the
contents of the LSP. MSP. and XTP
registers to be added to the multiplier
output. A LOW level input allows
multiplication only. The ACC signal is
loaded on the rising edge of either
CLKX or CLKY. and must be valid for
the entire duration of input data.
SUB
Subtract
When ACC and SUB are both HIGH.
the contents of the output register are
subtracted from the last product
generated. and the difference is stored
back into the output registers at the
rising edge of the next CLKP. When
ACC is HIGH and SUB is LOW.
addition instead of subtraction is
performed. The SUB signal is loaded
into the SUB register at the rising edge
of either CLKX or CLKY.
The SUB signal must be valid over the
same period that the input data is
valid. When ACC is LOW. SUB is a
"Don't Care" pin.

RND
Round
A HIGH-level input causes a "1" to be
added to the most significant bit of the
LSP to round up MSP and XTP data.
RND is loaded on the rising edge of
either CLKX or CLKY and must be
valid for the duration of the input data.

VL2010-PC,CC.
X6
X5
X4
X3
X2
X1
XO
YO.PO
Y1.P1
Y2.P2
Y3.P3
Y4.P4
Y5.P5
Y6.P6
Y7.P7
GND
Y8.P8
Y9.P9
Y10.P10
Y11.P11
Y12.P12
Y13.P13
Y14.P14
Y15.P15
P16
P17
P18
P19
P20
P21
P22
P23

TC
Two'sComplementl Unsigned Magnltude
A HIGH-level input defines X and Yas
two's complement data. while a LOW
level defines the input data as unsigned magnitude. As with ACC. SUB.
and RND. TC is loaded at the rising
edge of either CLKX or CLKY and
must be valid for the duration of the
input data.
TSX,TSM,TSL
3-state Output Controls
The LSP. MSP. or XTP output buffers
are at high-impedance~tput
disabled) when TSL. TSM. or~.
respectively. is HIGH. These are
direct. nonregistered control signals.
The output drivers are enabled when
TSL. 1mil. or TSX is LOW.

1
2

X7
X8
X9

X10
X11
X12
X13
X14
X15

5
6

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

TSL
RND
SUB
ACC
CLKX
CLKY
VCC
TC
TSX
PREL
TSM
CLKP
P34
P33
P32
P31
P30
P29
P28
P27
P26
P25
P24

PRELOAD TRUTH TABLE
PREL
0

TSX
0

TSM
0

TSL
0
1
0
1

0
0
0
0
0

1
1

1
1
1
1

0
0

1
1

1
1
1
1
1
1
1
1

0
0
0
0

1
1
1
1

0
1
1
0

0
1
1

1
1
1

0
1
0
1

0
1

XTP
Q
Q
Q
Q
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PL
PL
PL
PL

MSP
Q
Q
Hi-Z
Hi-Z
Q
Q
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PL
PL
Hi-Z
Hi-Z
PL
PL

LSP
Q
Hi-Z
Q
Hi-Z
Q
Hi-Z
Q
Hi-Z
Hi-Z
PL
Hi-Z
PL
Hi-Z
PL
Hi-Z
PL

Notes:
Hi-Z - Output buffers at high impedance (Output disabled).
Q ... Output buffers at low impedance. Contents of output registers will be transferred
to output pins.
PL- Output buffers at high impedance. or output disabled. Preload data supplied
externally will be loaded into the output register at the rising edge of CLKP.
147

VLSI TECHNOLOGY, INC.
VL2010

DATA FORMATS
FRACTIONAL TWO'S COMPLEMENT
BIT

VALUE

15
SGN

14
2-1

13
2-2

INPUT

BIT
VALUE
BIT

XTP
VALUE
OUTPUT

MSP

BIT
VALUE
BIT

LSP
VALUE

15
SGN
34
_24
31
21

14
2-1
33
23
30

2- 3

32
22
29

2-15

2- 16

2- 17

\,1

\2-12

2- 13

2-14

2-15

~
)

2-13

2-14

2-15

13
2-2

2-1

2°

r\
~

7 P

,.,

(

2-11

2-18 \ .

Notes:
1. The value of the input sign bits is -2°.

-------------18

2- 12

2-13

2-14

2-28

2-30

2. The format shown uses a two's complement fractional notation. Note that the location of the binary point signifying the
separation of the integer and fractional fields is just after the sign, between the sign (_2°) and and the next most significant bit
for the multiplier inputs (-2 1). This scheme is carried over to the output format, except that an extended significance to the
integer field is provided to extend the utility of the accumulator. Consistent with the input notation, the output binary point is
located between the -2° and the _21 bit positions.
The location of the binary point is arbitrary, as long as one is consistent with both input and output formats. One can consider
the number field entirely integer, i.e., with the binary point just to the right of the least significant bit for input, product, and
accumulated sum.
3. When nonaccumulating, all first four bits (P34 to P31) will indicate the sign of the product. The P30 term will also indicate
the sign, except for the one exceptional case when multiplying -1 X -1. Note that, with the additional significant bits available
on this muttiplier, -1 X -1 is a valid operation yielding +1 product.
4. Whether accumulating the sum of products or doing single products, there is no change in format. However, the three
additional most significant bits (the guard bits) are provided to allow valid summation beyond that available for a single
multiplication product. For further clarification, no difference exists between this organization and one which would have the
product accumul;ation off-chip in a separate 18-bit adder. Taking the sign at the ost siginificant bit position guarantees that the
largest number field will be used. In operation, the sign will be extended into the lesser significant bit positions when the
accumulated sum only occupies a right-hand portrion of the accumulator. As an example, when the sum only occupies the
least three bit positions, then the sign will be extended through the 16 most significant positions.
INTEGER MAGNITUDE
BIT

VALUE

15
2 15

14
214

INPUT

BIT
VALUE
BIT

15
2 15
34

14
214

2 13

VALUE
MSP

BIT
VALUE

LSP

BIT
VALUE

2 34
31
2 31
15
2 15

233

232
29

30
2 30

2 29

14
214

13
2 13

148

2°

~
)

12~

XTP

OUTPUT

\,1

I\.

2 13

212

7 ?

~
212 \ .

2 19
\3

2°

--------18

217

2 16

2°

2 18

VLSI TECHNOLOGY, INC.
VL2010

AC CHARACTERISTICS
Symbol

Parameter

=0 °e to 70 °e, vee =5 V ± .25 V
Typ

Max

Unit

Conditions

Output Delay

Load 1 (Figure 3)

tENA

Output Enable Delay

Load 2 (Figure 4)

tDIS

Output Disable Delay

Load 2 (Figure 4)

tMA

Multiply-Accumulate Time

tPW

Clock Pulse Width

Input Register Setup Time

Input Register Hold Time

Min

TIMING DIAGRAM
X,Y,TC,
RND, ACC, SUB

CONTROL AND
DATA IN

+-tPW--~

CLKX, CLKY
PRELOAD TIMING

LOAD TIMING
CLKP
PREL

TSL, TsM,TSx
~tDIS

PRELOAD IN
DATA

OUTPUT PINS
HIGH IMPEDANCE

149

VLSI TECHNOLOGY, INC
VL2010

FIGURE 1. INPUT EQUIVALENT CIRCUIT

FIGURE 4. TEST LOAD FOR 3-STATE DELAY

soon

FROM

OUTPUT

o---~-

40PF

FIGURE 2. OUTPUT CIRCUIT

OV.

2.6V

FIGURE 5. SUPPLY CURRENT VS OPERATING
FREQUENCY
100

--r------------,

VCC

T =·55

T =25

75
ICC

. - - - - - OUTPUT

(mA)

o
o

8 10 12 14 16 18 20
Frequency (MHz)

Note:

Temperature (T) Is measured In degrees Centigrade.

FIGURE 3. TEST LOAD FOR DELAY MEASUREMENT

FIGURE 6. MULTIPLY-ACCUMULATE TIME VS AMBIENT
TEMPERATURE
105 - , - - - - - - - - - - - - - . . . ,

95
FROM

OUTPUT

tMA
(ns)

o----+-~~--.

40pF
55
45-+--~-~--~--r--~

TA (degrees Centigrade)

150

VLSI TECHNOLOGY, INC.
VL2010

ABSOLUTE MAXIMUM RATINGS
Supply Voltage
-0.5 to 7.0 V
Input Voltage
-0.5 to 7.0 V
Output Voltage
-0.5 to 7.0 V
0 °C to 70°C
Operating Temperature
Storage Temperature -65 C to 150 C
Lead Temperature (10 Sec.)
300 C
MaximumJunction Temp.
175 C

DC CHARACTERISTICS

those listed on the operational sections
of this specification is not implied and
exposure to absolute maximum ratings
conditions for extended periods may
affect device reliability.

Stresses above those listed under
"Absolute Maximum Ratings" may
cause permanent damage to the
device. These are stress ratings only.
Functional operation of this device at
these or any other conditions above

=0 °C to

70°C,

vce =5 V

± .25 V

Symbol

Parameter

VIH

High-level Input Voltage

VIL

Low·levellnput Voltage

0.8

VOH

High-level Output Voltage

2.4

3.0

VCC.. Min; IOH-o.4 mA

VOL

low·level Output Voltage

0.3

0.4

VCC.. Min; IOl-4.0 mA

IIH

High-level Input Current

VCC.Max; VIH ..2.4 V

III

Low· Leve I Input Current

VCC.Max; Vll-0.4 V

10H

High·level Output Current

-0.4

10l

Low·level Output Current

4.0

ICC

Supply Current at DC

ICC/F

Supply Current IncreaselMHz

CAPACITANCE

Min

Max

2.0

Unit

Conditions

V
V

mA
8.0

mA
mA

mAl
MHz

VCC=Max; DC Condo
VCC-Max

TA = 0 °C to 70°C

Symbol

Parameter

Input Capacitance

Min

I
I

Typ

Clocks, Unlatched Controls
Data, latched Controls

Output Capacitance

151

Max

Unit

20
10

Conditions

VLSI TECHNOLOGY, INC.

152

VLSI TECHNOLOGY, INC.
VL2793 • VL2797
FLOPPY DISK FORMATTER!
CONTROLLER FAMILY

FEATURES

DESCRIPTION

• On-chip PLL data separator

• Soft sector format compatibility

The VL279X are N-Channel Silicon
Gate MOS LSI devices which perform
the functions of a Floppy Disk Formatter/Controller in a single chip implementation. The VL279X, which can be
considered the end result of both the
FD1771 and FD179X designs, is IBM
3740 compatible in single density mode
(FM) and System 34 compatible in
Double Density Mode (MFM). The
VL279X contains all the features of its
predecessor the FD179X plus a high
performance Phase-Lock-Loop Data
Separator as well as Write Precompensation Logic. In Double Density mode,
Write Precompensation is automatically
engaged to a value programmed via an
external potentiometer. In order to
maintain compatibility, the FD1771,
FD179X and VL279X designs were

PIN DIAGRAM

ORDER INFORMATION

• On-chip write precompensation logic
• Single +5 V supply
• Accommodates single and double
density formats
IBM 3740 (FM)
IBM 34 (MFM)
• Automatic seek with verify
• Multiple sector read/write
• TIL compatible
• Programmable control
-Selectable track-to-track access
-Head load timing
• Software compatible with the FD179X
series

VL2793
VL2797

ENP

HLT
INTRa
DRa

FiE

~~~~
iP

AO
Al

DALO
DALl

READY
WD

Format

Package
Plastic DIP
Ceramic DIP

VL2797-PC
VL2797-CC

DoubleSided

Plastic DIP
Ceramic DIP

Note: Operating temperature range is O°C to +70°C.

TG43
HLD
RAWRD
VCO

SSO/EN'M'F
CLK
PUMP

GND

TEST
~"""-----'

The 279317 has a side select output for
controlling double sided drives.

SingleSided

'DIRC
~8
RPW

The VL279X is TTL compatible on all
inputs and outputs. The outputs will
drive one TTL load or three LS loads.
The VL2793 is identical to the 2791
except the DAllines are TRUE for
systems that utilize true data busses.

VL2793-PC
VL2793-CC

WPW

DAL3
DAL4
DAL5
DAL6
DAL7
STEP

The processor interface consists of an
8-bit bidirectional bus for data, status,
and control word transfers. The
VL279X is set up to operate on a
multiplexed bus with other bus-oriented
devices.

Part
Number

TROO

DAL2

made as close as possible with the
computer interface, instruction set, and
110 registers being identical. Also, head
load control is identical. In each case,
the actual pin assignments vary by only
a few pins from anyone to another.

VCC

153

VLSI TECHNOWGY, INC.
VL2793 • VL2797

PIN DESCRIPTION
PIN NUMBER

PIN NAME

SYMBOL

FUNCTION

ENABLE PRECOMP

ENP

A Logic high on this input enables write precompensation to be performed on double density Write Data
output only.
A logic low (50 microseconds min.) on this input
resets the device and loads HEX 03 into the command register. The Not Ready (Status Bit 7) is reset
during MR ACTIVE. When MR is brought to a logic
high a RESTORE Command is executed, regardless
of the state of the Ready signal from the drive. Also,
HEX 01 is loaded into sector register.

VSS

Ground

VCC

+5V ±5%

MASTER RESET

POWER SUPPLIES

21
COMPUTER INTERFACE:
2

WRITE ENABLE

A logic low on this input gates data on the DAL into
the selected register when CS is low.
A logic low on this input selects the chip and enables
computer communication with the device.

3
4

5,6

7-14

READ ENABLE

A logic low on this input controls the placement of
data from a selected register on the DAL when CS is
low.

These inputs select the register to receive/transfer
data on the DAL lines under RE and WE control:
CS

0
0
0
0

0
0
1
1

0
1
0
1

Status Reg
Track Reg
Sector Reg
Data Reg

WE
Command Reg
Track Reg
Sector Reg
Data Reg

DATA ACCESS LINES

DALO-DAL7

Eight bit bi-directional bus used for transfer of commands, status, and data These lines are inverted
(active low) on VL279X.

CLOCK

CLK

This input requires a free-running 50% duty cycle
square wave clock for internal timing reference, 2
MHz ± 1% for 8" drives, 1 MHz ± 1% for minifloppies.

DATA REQUEST

DRQ

This output indicates that the Data Register contains
assembled data in Read operations, or the DR is
empty in Write operations. This signal is reset when
serviced by the computer through reading or loading
the DR.

INTERRUPT REQUEST

INTRQ

This output is set at the completion of any command
and is reset when the Status register is read or the
Command register is written to.

FLOPPY DISK INTERFACE:
15

STEP

The step output contains a pulse for each step.

DIRECTION

DIRC

Direction Output is active high when stepping in,
active low when stepping out.

5114," 8" SELECT

Si8

This input selects the internal VCO frequency for use
with 5114" drives or 8" drives.

READ PULSE WIDTH

RPW

TEST

An external potentiometer tied to this input controls
the phase comparator within the data separator.
A logic low on this input allows adjustment of external resistors by enabling Internal signals to appear on
selected pins.

154

VLSI TECHNOLOGY, INC.
VL2793 • VL2797

PIN DESCRIPTION (Continued)
PIN NUMBER

PIN NAME

SYMBOL

FUNCTION

PUMP

High·lmpedance output signal which is forced high
or low to increase/decrease the VCO frequency.

ENABLE MINI·FLOPPY
(2793)

SIDE SELECT OUTPUT
(2797)

SSO

The logic level of the Side Select Output is directly
controlled by the'S' flag in Type II or III commands.
When U = 1, SSO is set to a logic 1. When U = 0,
SSO is set to a logic O. The SSO is compared with the
side information in the Sector 1.0. Field. If they do not
compare Status Bit 4 (RNF) is set. The Side Select
Output is only updated at the beginning of a Type II or
III command. It is forced to a logic 0 upon a MASTER
RESET condition.

VOLTAG E·CONTROLLED
OSCILLATOR

VCO

An external capacitor tied to this pin adjusts the VCO
center frequency.

RAW READ

The data input signal directly from the drive. This
input shall be a negative pulse for each recorded flux
transition.

HEAD LOAD

HLD

The HLD output controls the loading of the Read·
Write head against the media

TRACK GREATER
THAN 43

TG43

This output informs the drive that the ReadlWrite
head is positioned between tracks 44·76. This output
is valid only during Read and Write Commands.

WRITE GATE

This output is made valid before writing is to be
performed on the diskette.

WRITE DATA

MFM or FM output pulse per flux transition. WD
contains the unique Address marks as well as data
and clock in both FM and MFM formats.

READY

This input indicates disk readiness and is sampled
for a logic high before Read or Write commands are
performed. If Ready is low the Read or Write
operation is not performed and an interrupt is
generated. Type I operations are performed regard·
less of the state of Ready. The Ready input appears in
inverted format as Status Register bit 7.

WRITE PRECOMP
WIDTH

WPW

An external potentiometer tied to this input controls
the amount of delay in Write precompensation mode.

TRACK 00

TROO

This input informs the VL279X that the ReadlWrite
head is positioned over Track 00.

INDEX PULSE

WRITE PROTECT

WPRT

This input informs the VL279X when the index hole
is encountered on the diskette.
This input is sampled whenever a Write Command is
received. A logic low terminates the command and
sets the Write Protect Status bit.

DOUBLE DENSITY

DDEN

This input pin selects either single or double density.
operation. When DDEN
0, double density is
selected. When DO EN = 1, single density is
selected.

HEAD LOAD TIMING

HLT

When a logic high is found on the HLT input the head
is assumed to be engaged. It is typically derived from
a 1 shot triggered by HLD.

A logic low on this input enables an internal -:- 2 of
the Master Clock. This allows both 5 1/4" and 8" drive
operation with a single 2 MHz clock. For a 1 MHz
clock on Pin 24, this line must be left open or tied to a
Logic 1.

155

VLSI TECHNOWGY, INC.
VL2793 • VL2797

Figure 1.

HOST
PROCESSOR

Data Shift Register - This 8-bit register assembles serial
data from the Read Data input (RAW READ) during Read
operations and transfers serial data to the Write Data
output during Write operations.

8'"

OAl'

g:~!

WPAT

1 + - - - - - - - g~TVKE

Data Register - This 8-bit register is used as a holding
register during Disk Read and Write operations in Disk
Read operations the assembled data byte is transferred in
parallel to the Data Register from the Data Shift Register. In
Disk Write operations information is transferred in parallel
from the Data Register to the Data Shift Register:

DAl6
OAl7

APPLICATIONS
8" FLOPPY AND 5114" MINI FLOPPY CONTROLLER
SINGLE OR DOUBLE DENSITY
CONTROLLE~FORMATTER

The VL279X Family are MOS/LSI devices which perform
the functions of a Floppy Disk Controller/Formatter. Soft·
ware compatible with its predecessor, the FD179X, the
device also contains a high performance Phase-Lock·Loop
Data Separator as well as Write Precompensation Logic.
When operating in Double Density mode, Write Precompensation may be enabled, its value predetermined by an
external potentiometer. An on-chip VCO and phase
comparator allows adjustable frequency range for 51f4" or
8" Floppy Disk interfacing.
The VL279X is fabricated in NMOS silicon gate technology
and available in a 40 pin dual-in-line package.

FEATURES
Single Density (FM)
Double Density (MFM)
True Data Bus
Inverted Data Bus
Side Select Out
Internal CLK Divide

2793

2797

X
X
X

X
X
X
X

ORGANIZATION
The Floppy Disk Formatter block diagram is illustrated on
page 5. The primary sections include the parallel processor
interface and the Floppy Disk interface.

When executing the Seek command the Data Register
holds the address of the desired Track position. This
register is loaded from the DAL and gated onto the DAL
under processor control.
Track Register - This 8-bit register holds the track number
of the current ReadlWrite head position. It is incremented
by one every time the head is stepped in (towards track 76)
and decremented by one when the head is stepped out
(towards track (0). The contents of the register are compared with the recorded track number in the ID field during
disk Read, Write and Verify operations. The Track Register
can be loaded from or transferred to the DAL. This Register
should not be loaded when the device is busy.
Sector Register (SR) - This 8-bit register holds the address
of the desired sector position. The contents of the register
are compared with the recorded sector number in the ID
field during disk Read or Write operations. The Sector
Register contents can be loaded from or transferred to the
DAL. This register should not be loaded when the device is
busy.
Command Register (CR) - This 8-bit register holds the
command presently being executed. This register should
not be loaded when the device is busy unless tile new
command is a force interrupt. The command register can
be loaded from the DAL, but not read onto the DAL.
Status Register (STR) - This 8-bit register holds device
Status information. The meaning of the Status bits is a
function of the type of command previously executed. This
register can be read onto the DAL, but not loaded from the
DAL.
CRC Logic - This logic is used to check or to generate the
16-bit Cyclic Redundancy Check (CRC). The polynomial is:
G(x)
x 16 + x 12 + x5 + 1.

The CRC includes all information starting with the address
mark and up to the CRC characters. The CRC register is
preset to ones prior to data being shifted through the
circuit.
Arithmetic/Logic Unit (ALU) - The ALU is a serial comparator, incrementer, and decrementer and is used for register
modification and comparisons with the disk recorded ID
field.
Timing and Control - All computer and Floppy Disk interface controls are generated through this logic. The internal device timing is generated from an external crystal
clock.
AM Detector - The address mark detector detects ID, data
and index address marks during read and write operations.
Write Precompensation - enables write precompensation
to be performed on the Write Data output.

156

VLSI TECHNOLOGY, INC
VL2793 • VL2797

VL279X BLOCK DIAGRAM

=fL=J
r - - - ' - - , . o - - RPW

WRITE OArA

(TCOISKI

5i8

veo
PUMP

PLA
COJr\jTROL
(230 X 11)

CO",",PUTER
I~TERFACE

COJr\jTROl

DISK
t~TERFA:E

CQIlfTR(.,:

_._STEP

~----.

Data Separator - a high performance Phase-Lock-Loop
Data Separator with on-chip VCO and phase comparator
allows adjustable frequency range for 51/4" or 8" Floppy
Disk interfacing.

During Direct Memory Access (DMA) types of data transfers between the Data Register of the VL279X and the
processor, the Data Request (ORa) output is used in Data
Transfer control. This signal also appears as status bit 1
during Read and Write operations.

PROCESSOR INTERFACE
The interface to the processor is accomplished through the
eight Data Access Lines (DAL) and associated control
signals. The DAL are used to transfer Data, Status, and
Control words out of, or into the VL279X. The DAL are
three state buffers that are enabled as output drivers when
Chip Select (CS) and Read Enable (RE) are active (low logic
state) or act as input receivers when CS and Write Enable
(WE) are active.

On Disk Read operations the Data Request is activated (set
high) when an assembled serial input byte is transferred in
parallel to the Data Register. This bit is cleared when the
Data Register is read by the processor. If the Data Register
is read after one or more characters are lost, by having new
data transferred into the register prior to processor readout,
the Lost Data bit is set in the Status Register. The Read
operation continues until the end of sector is reached.

When transfer of data with the Floppy Disk Controller is
required by the host processor, the device address is
decoded and CS is made low. The address bits A1 and AO,
combined with the signals RE during a Read operation or
WE during a Write operation are interpreted as selecting
the following registers:
A1 0
0
1
1

READ (RE)

WRITE (WE)

0
1
0
1

Status Register
Track Register
Sector Register
Data Register

Command Register
Track Register
Sector Register
Data Register

On Disk Write operations the data Request is activated
when the Data Register transfers its contents to the Data
Shift Register, and requires a new data byte. It is reset when
the Data Register is loaded with new data by the processor.
If new data is not loaded at the time the next serial byte is
required by the Floppy Disk, a byte of zeroes is written on
the diskette and the Lost Data bit is set in the Status
Register.
At the completion of every command an INTRa is
generated. INTRa is reset by either reading the status
register or by loading the command register with a new
command. In addition, INTRa is generated if a Force Interrupt command condition is met.

157

VLSI TECHNOLOGY, INC.
VL2793 • VL2797

The 279X has two modes of operation according to the
1, Single Density
state of DDEN (Pin 37). When DDEN
(FM) is selected. When DDEN = 0, Double Density (MFM)
is selected. In either case, the CLK input (Pin 24) is set at 2
MHzfor8" drivesor1 MHzfor51/4" drives.

On the 2791/2793, the ENMF input (Pin 25) can be used for
controlling both 51/4" and 8" drives with a single 2 MHz
clock. When ENMF = 0, an internal -:- 2 of the CLK is
performed. When ENMF = 1, no divide takes place. This
allows the use of a 2 MHz clock for both 51/4" and 8"
configurations.
The internal VCO frequency must also be set to the proper
value. The 5i8 input (Pin 17) is used to select data separator
operation by internally dividing the Read Clock. When 5/8
= 0, 5114" data separation is selected; when 5/8 = 1, 8"
drive data separation is selected.
CLOCK (24)
2MHz
2MHz
1 MHz

ENMF(25)

5/8 (17)

DRIVE

1
0
1

1
0
0

8"
5114 "
51/4"

FUNCTIONAL DESCRIPTION
The VL279X is software compatible with the FD179X series
of Floppy Disk Controllers. Commands, status, and data
transfers are performed in the same way. Software generated
for the 179X can be transferred to a 279X system without
modification.
In addition to the 179X, the 279X contains an internal Data
Separator and Write precompensation circuit. The TEST
(Pin 22) line is used to adjust both data separator and precompensation. When TEST
0, the WD (Pin 31) line is
internally connected to the output of the write precomp
one-shot. Adjustment of the WPW (Pin 33) line can then be
accomplished. A second one-shot tracks the precomp setting at approximately 3:1 to insure adequate Write Data
pulse widths to meet drive specifications.

Similarly, Data separation is also adjusted with TEST = O.
The TG43 (Pin 29) line is internally connected to the output
of the read data one-shot, which is adjusted via the RPW
(Pin 18) line. The DIRC (Pin 16) line contains the Read Clock
output (.5 MHz for 8" drives). The VCO Trimming capacitor
(Pin 26) is adjusted for center frequency.
Internal timing signals are used to generate pulses during
the adjustment mode so that these adjustments can be
made while the device is in-circuit. The TEST line also
contains a pull-up resistor, so adjustments can be performed simply by grounding the TEST pin, overriding the
pull-up. The TEST pin cannot be used to disable stepping
rates during operation as its function is quite different from
the 179X.
Other pins on the device also include pull-up resistors and
may be left open to satisfy a Logic 1 condition. These are:
ENP, 5/8, ENMF, WPRT, DDEN, HLT, TEST, and MR.
GENERAL DISK READ OPERATIONS
Sector lengths of 128, 256, 512 or 1024 are obtainable in
either FM or MFM formats. For FM, DDEN should be
placed to logical "1." For MFM formats, DDEN should be

Sector Length Table"
Sector Length
Field (hex)

00
01
02
03

Numberof Bytes
in Sector(decimal)
128
256
512
1024

*2793/97 may vary - see command summary.

placed to a logical "0." Sector lengths are determined at
format time by the fourth byte in the "10" field.
The VL279X recognizes tracks and sectors numbered 00FFX. However, due to programming restrictions, only tracks
and sectors 00 thru F4 can be formatted.

GENERAL DISK WRITE OPERATION
When writing is to take place on the diskette the Write Gate
(WG) output is activated, allowing current to flow into the
ReadlWrite head. As a precaution to erroneous writing the
first data byte must be loaded into the Data Register in
response to a Data Request from the 279X before the Write
Gate signal can be activated.
Writing is inhibited when the -W-r"'-it-e-=P-ro-t-e-'ct input is a logic
low, in which case any Write command is immediately
terminated, an interrupt is generated and the Write Protect
status bit is set.
For write operations, the 279X provides Write Gate (Pin 30)
and Write Data (Pin 31) outputs. Write data consists of a
series of pulses set to a width approximately three times
greater than the precomp adjustment. Write Data provides
the unique address marks in both formats.

READY
Whenever a Read or Write command (Type II or III) is
received the 279X samples the Ready input. If this input is
logic low the command is not executed and an interrupt is
generated. All Type I commands are performed regardless
of the state of the Ready input. Also, whenever a Type II or
III command is received, the TG43 signal output is updated.
TG43 may be tied to ENP to enable write precompensation
on tracks 44-76.
COMMAND DESCRIPTION
The VL279X will accept eleven commands. Command
words should only be loaded in the Command Register
when the Busy status bit is off (Status bit 0). The one exception is the Force interrupt command. Whenever a
command is being executed, the Busy status bit is set.
When a command is completed, an interrupt is generated
and the Busy status bit is reset. The Status Register indicates whether the completed command encountered an
error or was fault free. For ease of discussion, commands
are divided into four types. Commands and types are
summarized in Table 1.

158

VLSI TECHNOLOGY, INC.
VL2793 • VL2797

TABLE 1. COMMAND SUMMARY
A. Commands for Model 2793

B. Commands for Model 2797
Bits

Type
I
I
I
I
I
II
II
III

Command
Restore
Seek
Step
Step-in
Step-out
Read Sector
Write Sector
Read Address
III Read Track
III Write Track
IV Force Interrupt

TABLE 2.
Command
Type

5
0
0
1
0
1
0
1
0
1
1
0

'6
0
0
0
1
1
0
0
1
1
1
1

7
0
0
0
0
0
1
1
1
1
1
1

0
1
T
T
T
m
m
0
0
1
1

Bits
3
h
h
h
h
h
S
S
0
0
0
13

2
V
V
V
V
V
E
E
E
E
E
12

r1
r1
r1
r1
r1
C
C
0
0
0
11

0
rO
rO
ro
rO
rO
0

ao
0
0
0
10

7
0
0
0
0
0
1
1
1
1
1
1

6
0
0
0
1
1
0
0
1
1
1
1

5
0
0
1
0
1
0
1
0
1
1
0

0
1
T
T
T
m
m
0
0
1
1

3
h
h
h
h
h
L
L
0
0
0
13

2
V
V
V
V
V
E
E
E
E
E
12

r1
r1
r1
r1
r1
U
U
U
U
U
11

FLAG SUMMARY

Bit
No(s)
0,1

=Track Number Verify Flag

= Head Load Flag

=Track Update Flag

11&111

=Side Compare Flag

11&111

=Update SSO

11&111

= 15 MS Delay

=Side Compare Flag

=Sector Length Flag

0.3

Description

r1 rO Stepping Motor Rate
See Table 3 for Rate Summary

= Data Address Mark

LSB's Sector Length in 10 Field
01
00
512
256
L
0
128
256
L
1

=
=
m =0, Single record
m = 1, Multiple records

=Multiple Record Flag

Ix
10
11
12
13
13·IC

=0, No verify
= 1, Verify on destination track
h = 0, Unload head at beginnipg
h = 1, Load head at beginning
T =0, No update
T = 1, Update track register
aO =0, FB (DAM)
aO = 1, F8 (delet~d DAM)
C =0, Disable side compare
C = 1, Enable side compare
U =0, Update SSO to 0
U = 1, UpdateSSO to 1
E = 0, No. 15 MS delay
E = 1,15MSdelay(30MSfor1 MHz)
S =0, Compare for side 0
S = 1, Compare for side 1
V
V

= Interrupt Condition Flags
= 1 Not Ready To Ready Transition
= 1 Ready To Not Ready Transition
= 1 Index Pulse
= 1 Immediate Interrupt, Requires A Reset= 0 Terminate With No Interrupt (INTRC)

- NOTE: See Type IV Command Description for further information.

159

10
1024
512

11
128
1024

0
ro
ro
ro
rO

ro
0

ao
0
0
0
10

VLSI TECHNOLOGY, INC

Write Precompensation
When operating in Double Density mode (DDEN = 0), the
279X has the capability of providing a user-defined
precompensation value for Write Data. An external
potentiometer(10K) tied to the WPW signal (Pin 33) allows a
setting of 100 to 300 ns from nominal.
Setting the Write precomp value is accomplished by forcing the TEST line (Pin 22) to a logic O. A stream of pulses
can then be seen on the Write Data (Pin 31) line. Adjust the
WPW Potentiometer for the desired pulse width. This
adjustment may be performed in-circuit since Write Gate
(Pin 30) is inactive while TEST = O.

VL2793 • VL2797
must be accomplished between the two conditions to
inhibit over-responsiveness to jitter and to prevent an
extremely wide lock-up response, leading to PUMP runaway. The filter affects these two reactions in (Tlutually
opposite directions.
The following Filter Circuit is recommended for 8"
FM/MFM:
PUMP
(PIN 23)

~
.1/-Af

1 K Q P IN914

Data Separation
The 279X can operate with either an external data separator
or its own internal recovery circuits. The condition of the
TEST line (Pin 22) in conjunction with MR (Pin 19) will select
internal or external mode.
To program the 279X for external VCO, a MR pulse must be
applied while TEST = O. A clock equivalent to eight times
the data rate (e.g., 4.0 MHz for 8" Double Density) is applied
to the VCO input (Pin 26). The feedback reference voltage is
available on the Pump output (Pin 23) for external integration to control the VCO. TEST is returned to a logiC 1
for normal operation. Note: To maintain this mode, TEST
must be held low whenever MR is applied.
For internal VCO operation, the TEST line must be high
during the MR pulse, then set to a logic 0 for the adjustment procedure.
A 50K Potentiometer tied to the RPW input (Pin 18) is used
to set the internal Read Data pulse for proper phasing. With
a scope on Pin 29 (TG43), adjust the RPW pulse for 1/8 of
the data rate (250 ns for 8" Double Density). An external
variable capacitor of 5-60 pf is tied to the VCO input (Pin 26)
for adjusting center frequency. With a frequency counter
on Pin 16 (DIRC) adjust the trimmer cap to yield the appropriate Data Rate (500 KHz for 8" Double Density). The
I)'[j§ij line must be low while the 518 line is held high or the
adjustment times above will be doubled.
After adjustments have been made, the TEST pin is
returned to a Logic 1 and the device is ready for operation.
Adjustments may be made in-circuit since the DIRC and
TG43 lines may toggle without affecting the drive.
The PUMP output (Pin 23) consists of posi\ive and negative
pulses, which their duration is equivalent to the phase
difference of incoming Data vs. VCO frequency. This signal
:is internally connected to the VCO input, but a Filter is
needed to connect these pulses to a slow moving DC
:voltage.
'The internal phase-detector is unsymmetrical for a random
'distribution of data pulses by a factor of two, in favor of a
:PUMP UP condition. Therefore, it is desirable to have a
:PUMP DOWN twice as responsive to prevent run-away
during a lock attempt.
A first order lag-lead filter can be used at the PUMP output
(Pin 23). This filter controls the instantaneous response of
the VCO to bit-shifted data (jitter) as well as the response to
normal freauency shift, i.e., the lock-up time. A balance

Since 5V4" Drives operate at exactly one-half the data rate
(250 Kb/sec) the above capacitor should be doubled to .2 or
.2~f.

TYPE I COMMANDS
The Type I Commands include the Restore, Seek, Step,
Step-in, and Step-Out commands. Each of the Type I
Commands contains a rate field (ra r1), which determines
the stepping motor rate as defined in Table 3.
A ~s (MFM) or 4 "'s (FM) pulse Is provided as an output to
the drive. For every step pulse issued, the drive moves one
track location in a direction determined by the direction
output. The chip will step the drive in the same direction it
last stepped unless the command changes the direction.
The Direction signal is active high when stepping in and
low when stepping out. The Direction signal is valid before
the first stepping pulse is generated.
The rates (shown in Table 3) can be applied to a StepDirection Motor through the device interface.
TABLE 3. STEPPING RATES
R1

2MHz
TEST
1

1 MHz
TEST
1

0
0
1
1

0
1
0
1

3ms
6ms
10ms
15ms

6ms
12ms
20ms
30ms

ClK

After the last directional step an additional 15 milliseconds
of head settling time takes place if the Verify flag is set in
Type I commands. Note that this time doubles to 30 ms for
a 1 MHz clock. There is also a 15 ms head settling time if
the E flag is set in any Type II or III command.
When a Seek, Step or Restore command is executed an
optional verification of Read·Write head position can be
performed by setting bit 2 (V = 1) in the command word to
a logic 1. The verification operation begins at the end of the
15 millisecond settling time after the head is loaded against
the media. The track number from the first encountered 10

160

VLSI TECHNOLOGY, INC
VL2793 • VL2797

Field is compared against the contents of the Track
Register: If the track numbers compare and the 10 Field
Cyclic Redundancy Check (CRG) is correct, the verify
operation is complete and an INTRQ is generated with no
errors. If there is a match but not a valid CRC, the CRC error
status bit is set (Status bit 3), and the next encountered 10
field is read from the disk for the verification operation.
The VL279X must find an 10 field with correct track
number and correct CRC within 5 revolutions of the media;
otherwise the seek error is set and an INTRQ is generated.
If V = 0, no verification is performed.
The Head Load (HLD) output controls the movement of the
read/write head against the media. HLD is activated at the
beginning of a Type I command if the h flag is set (h = 1), at
1), or
the end of the Type I command if the verify flag (V
upon receipt of any Type II or III command. Once HLO is
active it remains active until either a Type I command is
received with (h = 0 and V = 0); or if the 279X is in an idle
state (non-busy) and 15 index pulses have occurred.

Head Load timing (HLT) is an input to the 279X which is
used for the head engage time. When HLT = 1, the 279X
assumes the head is completely engaged. The head
engage time is typically 30 to 100 ms depending on drive.
The low to high transition on HLD is typically used to fire a
one shot. The output of the one shot is then used for HLT
and supplied as an input to the 279X.

active low, stepping pulses at a rate specified by the r1 ro
field are issued until the TROD Input Is activated. At this
time the Track Register is loaded with zeroes and an interrupt Is generated. If the fROO input does not go active
low after 255 stepping pulses, the 279X terminates
operation, interrupts, and sets the Seek error status bit. A
verification operation takes place if the V flag Is set. The h
bit allows the head to be loaded at the start of command.
Note that the Restore command Is executed when MR
goes from an active to an Inactive state.

SEEK
This command assumes that the Track Register contains
the track number of the current position of the Read-Write
head and the Data Register contains the desired track
number. The VL279X will update the Track register and
issue stepping pulses in the appropriate direction until the

TYPE I COMMAND FLOW

HEAD LOAD TIMING

HLOr----1I
f----",";

!
Hl T (FROM ONE SHOT)

When both HLD and HLT are true, the 279X will then read
from or write to the media. The "and" of HLD and HLT appears as status Bit 5 in Type I status.
In summary for the Type I commands: if h = 0 and V = 0,
HLD is reset. If h = 1 and V = 0, HLD is set at the
beginning of the command and HLT is not sampled nor is
there an internal 15 ms delay. If h = 0 and V = 1, HLD is set
near the end of the command, an internal 15 ms occurs,
and the 279X waits for HLT to be true. If h
1 and V
1,
HLD is set at the beginning of the command. Near the end
of the command, after all the steps have been issued, an
internal 15 ms delay occurs and the 279X then waits for HLT
to occur.

For Type II and III commands with E flag off, HLD is made
active and HLT is sampled until true. With E flag on, HLD is
made active~ an internal 15 ms delay occurs and then HLT is
sampled until true.

RESTORE (SEEK TRACK 0)
Upon receipt of this command the Track 00 (TROO) input is
sampled. If TROO is active low indicating the Read-Write
head is positioned over track 0, the Track Register is loaded
with zeroes and an interrupt is generated. If TROO is not

161

VLSI TECHNOLOGY, INC

TYPE I COMMAND FLOW

VL2793 • VL2797
TYPE I COMMAND FLOW
VERIFY
SEQUENCE

NOTE

contents of the Track register are equal to the contents of
the Data Register (the desired track location). A verification
operation takes place if the V flag is on. The h bit allows the
head to be loaded at the start of the command. An interrupt
is generated at the completion of the command. Note:
When using multiple drives, the track register must be
updated for the drive selected before seeks are issued.

STEP
Upon receipt of this command, the 279X issues one
stepping pulse to the disk drive. The stepping motor
direction is the same as in the previous step command.
After a delay determined by the r1 rO field, a verification
takes place if the V flag is on. If the T flag is on, the Track
Register is updated. The h bit allows the head to be loaded
at the start of the command. An interrupt is generated at
the completion of the command.

1 UHl THERE Ie; A. 10M.., 0(1 AY

delay determined by the r1 rO field, a verification takes place
if the V flag is on. The h bit allows the head to be loaded at
the start of the command. An interrupt is generated at the
completion of the command.

STEP·OUT
Upon receipt of this command, the 279X issues one
stepping pulse in the direction towards track O. If the T flag
is on, the Track Register is decremented by one. After a
delay determined by the r1 rO field, a verification takes place
if the V flag is on. The h bit allows the head to be loaded at
the start of the command. An interrupt is generated at the
completion of the command.

EXCEPTIONS
On the 2797 device, the SSO output is not affected during
Type I commands, and an internal side compare does not
take place when the M Verify Flag is on.

STEP·IN

TYPE II COMMANDS

Upon receipt of this command, the 279X issues one
stepping pulse in the direction towards track 76. If the T
flAg is on, the Track Register is incremented by one. After a

The Type II Commands are the Read Sector and Write
Sector commands. Prior to loading the Type II Command
into the Command Register, the computer must load the

162

VLSI TECHNOLOGY, INC.
VL2793 • VL2797

Sector Register with the desired sector number. Upon
receipt of the Type II command, the busy status Bit is set. If
the E flag
1 (this is the normal case) HLO is made active
and HLT is sampled after a 15 msec delay. If the E flag is 0,
the head is loaded and HLT sampled with no 15 msec delay.

TYPE II COMMAND

When an 10 field is located on the disk, the 279X compares
the Track Number on the 10 field with the Track Register. If
there is not a match, the next encountered 10 field is read
and a comparison is again made. If there was a match, the
Sector Number of the 10 field is compared with the Sector
Register. If there is not a Sector match, the next encountered 10 field is read off the disk and comparisons
again made. If the 10 field CRC is correct, the data field is
then located and will be either written into, or read from
TYPE II COMMAND

dependinp upon the command. The 279X must find an 10
field with a Track number, Sector number, side number, and
CRC within 5 revolutions of the disk; otherwise, the Record
not found status bit is set (Status bit 4) and the command is
terminated with an interrupt.
Each of the Type II Commands contains an (m) flag which
determines if multiple records (sectors) are to be read or
written, depending upon the command. If m
0, a single
sector is read or written and an interrupt is generated at the
completion of the command. If m
1, multiple records are
read or written with the sector register internally updated
so that an address verification can occur on the next
record. The 279X will continue to read or write multiple
records and update the sector register in numerical
ascending sequence until the sector register exceeds the
number of sectors on the track or until the Force Interrupt
command is loaded into the Command Register, which
terminates the command and generates an interrupt.

For example: If the 279X is instructed to read sector 27 and
there are only 26 on the track, the sector register exceeds

163

VLSI TECHNOLOGY, INC
VL2793 • VL2797

TYPE II COMMAND

TYPE II COMMAND
READ SECTOR
SEQUENCE

WRITE SECTOR
SEQUENCE

'NTRO, RESET BUSY
SET eRe ERROR

the number available. The 279X will search for 5 disk
revolutions, interrupt out, reset busy, and set the record not
found status bit.
The Type II commands for the 2793 also contain side select
compare flags. When C
0 (Bit 1) no side comparison is
made. When C = -1, the LSB of the side number is read off
the 10 Field of the disk and compared with the contents of
the (S) flag (Bit 3). If the S flag compares with the side
number recorded in the 10 field, the 279X continues with
the 10 search. If a comparison is not made within 5 index
pulses, the i.nterrupt line is made active and the RecordNot-Found status bit is set.

The Type II and III commands for the 2797 contain a side
select flag (Bit 1). When U = 0, SSO is updated to O.
Similarly, U = 1 updates SSO to 1. The chip compares the
SSO to the 10 field. If they do not compare within 5
revolutions the interrupt line is made active and the RNF
status bit is set.

mands include a 'L' flag. The 'L' flag, in conjunction with
the sector length byte of the 10 Field, allows different byte
lengths to be implemented in each sector. For IBM com·
patibility, the 'L' flag should be set to a one.
READ SECTOR
Upon receipt of the Read Sector command, the head is
loaded, the Busy status bit set, and when an 10 field is
encountered that has the correct track number, correct
sector number, correct side number, and correct CRC, the
data field is presented to the computer. The Data Address
·Mark of the data field must be found within 30 bytes in
Single density and 43 bytes in double density of the last 10
field CRC byte; if not, the 10 field search is repeated.

When the first character or byte of the data field has been
shifted through the OSR, it is transferred to the DR, and
ORO is generated. When the next byte is accumulated in
the OSR, it is transferred to the DR and another ORO is
generated. If the Computer has not read the previous
contents of the DR before a new character is transferred

The 2797 READ SECTOR and WRITE SECTOR com·

164

VLSI TECHNOLOGY. INC.
VL2793 • VL2797

that character is lost and the Lost Data Status bit is set.
This sequence continues until the complete data field has
been inputted to the computer. If there is a CRC error at the
end of the data field, the CRC error status bit is set, and the
command is terminated (even if it is a multiple sector
command).

TRACK
ADDR
1

Deleted Data Mark
Data Mark

WRITE SECTOR
Upon receipt of the Write Sector command, the head is
loaded (HLD active) and the Busy status bit is set. When an
ID field is encountered that has the correct track number,
correct sector number, correct side number, and correct
CRC, a DRO is generated. The 279X counts off 11 bytes in
single density and 22 bytes in double density from the CRC
field and the Write Gate (WG) output is made active if the
DRO is serviced (Le., the DR has been loaded by the
computer). If DRO has not been serviced, the command is
terminated and the Lost Data status bit is set. If the DRO
has been serviced, the WG is made active and six bytes of
zeroes in single density and 12 bytes in double density are
then written on the disk. At this time the Data Address
Mark is then written on the disk as determined by the
field of the command as shown below:

This command has several characteristics which make it
suitable for diagnostic purposes. They are: no CRC
checking is performed; gap information is included in the
data stream; the internal side compare is not performed;
and the address mark detector is on for the duration of the
command. Because the AM. detector is always on, write
splices or noise may cause the chip to look for an AM. If an
address mark does not appear on schedule with the Lost
Data status flag being set.

CRC CRC
1
2

computer, the 279X checks for validity and the CRC error
status bit is set if there is a CRC error. The Track Address of
the ID field is written into the sector register so that a
comparison can be made by the host. At the end of the
operation an interrupt is generated and the Busy Status is
reset.
READ TRACK
Upon receipt of the READ track command, the head is
loaded, and the Busy Status bit is set. Reading starts with
the leading edge of the first encountered index pulse and
continues until the next index pulse. All Gap, Header, 'and
data bytes are assembled and transferred to the data
register and DRO's are generated for each byte. The ac·
cumulation of bytes is synchronized to each address mark
encountered. An interrupt is generated at the completion of
the command.

STATUS
BIT5
1

SECTOR
LENGTH

Although the CRC characters are transferred to the

At the end of the Read operation, the type of Data Address
Mark encountered in the data field is recorded in the Status
Register(Bit 5) as shown:

SIDE
SECTOR
NUMBER ADDRESS

Data Address Mark (Bit 0)
Deleted Data Mark
Data Mark

The 10 AM., 10 field, 10 CRC bytes, DAM, Data and Data
CRC Bytes for each sector will be correct. The Gap Bytes
may be read incorrectly during write-splice time because of
synchronization.

The 279X then writes the data field and generates DRO's to
the. computer. If the DRO is not serviced in time for con·
tinuous writing the Lost Data Status Bit is set and a byte of
zeroes is written on the disk. The command is not ter·
minated. After the last data byte has been written on the
disk, the two-byte CRC is computed internally and written
on the disk followed by one bye of FE in FM or in MFM. The
WG output is then deactivated. For a 2 MHz clock the
INTRa will set 8 to 12 IAsec after the last CRC byte is
written. For partial sector writing, the proper method is to
write the data and fill the balance with zeroes. By letting the
chip fill the zeroes, errors may be masked by the lost data
status and improper CRC Bytes.

WRITE TRACK FORMATIING THE DISK

(Refer to section on Type III commands for flow diagrams.)
Formatting the disk is a relatively simple task when operat·
ing programmed 1/0 or when operating under DMA with a
large amount of memory. Data and gap information must be
provided at the computer interface. Formatting the disk is
accomplished by positioning the RIW head over the desired track number and issuing the Write Track command.
Upon receipt of the Write Track command, the head is
loaded and the Busy Status bit is set. Writing starts with
the leading edge of the first encountered index pulse and
continues until the next index pulse, at which time the
interrupt is activated. The Data Request is activated im·
mediately upon receiving the command, but writing will not
start until after the first byte has been loaded into the Data
Register. If the DR has not been loaded by the time the
index pulse is encountered the operation is terminated
making the device Not Busy, the Lost Data Status Bit is set,
and the interrupt is activated. If a byte is not present in the
DR when needed, a byte of zeroes is substituted.

TYPES III COMMANDS
READ ADDRESS
Upon receipt of the Read Address command, the head is
loaded and the Busy Status Bit is set. The next en·
countered ID field is then read in from the disk, and the six
data bytes of the ID field are assembled and transferred to
the DR, and a DRO is generated for each byte. The six bytes
of the 10 field are shown below:

165

VLSI TECHNOLOGY, INC.
VL2793 • VL2797

TYPE III COMMAND WRITE TRACK

TYPE III COMMAND Read Track/Address
READ ADDRESS
SEQUENCE

INTRa
)
RESET BUSY

·30 MS IF CLOCK
= 1 MHz

166

VLSI TECHNOLOGY, INC.
VL2793 VL2797
0

This sequence continues from one index mark to the next
index mark. Normally, whatever data pattern appears in the
data register is written on the disk with a normal clock
pattern. However, if the 279X detects a data pattern of F5
thru FE in the data register, this is interpreted as data address inarks with missing clocks or CRC generation.

TYPE III COMMAND WRITE TRACK

The CRC generator is initialized when any data byte from
Fa to FE is about to be transferred from the DR to the DSR

CONTROL BYTES FOR INITIALIZATION
DATA PATTERN
IN DR (HEX)

Vl279X INTERPRETATION
IN FM (DDEN = 1)

Vl279X INTERPRETATION
IN MFM (DDEN = OJ

00 thru F4
F5
F6
F7
Fa thru FB
FC
FD
FE
FF

Write 00 thru F4 with ClK = FF
Not Allowed
Not Allowed
Generate 2 CRC bytes
Write Fa thru FB, Clk = C7, Preset CRC
07
Write FC with Clk
Write FD with Clk = FF
Write FE, Clk = C7, Preset CRC
Write FF with Clk = FF

WriteOOthru F4, in MFM
Write A 1 * in MFM, Preset CRC
Write C2* * in MFM
Generate 2 CRC bytes
Write Fa thru FB, in MFM
Write FC in MFM
Write FD in MFM
Write FE in MFM
Write FF in MFM

* Missing clock transition between bits 4 and 5

* * Missing clock transition between bits 3 and 4

167

VLSI TECHNOLOGY, INC.

or by receipt of F5 In MFM. An F7 pattern will generate two
CRC characters in FM or MFM. As a consequence, the
patterns F5 thru FE must not appear in the gaps, data
fields, or 10 fields. Also, CRC's must be generated by an F7
pattern.
Disks may be formatted in IBM 3740 or System 34 formats
with sector lengths of 128, 256, 512, or 1024 bytes.
TYPE IV COMMANDS
The Forced Interrupt command is generally used to ter·
mlnate a multiple sector read or write command or to in·
sure Type I status in the status register. This command can
be loaded into the command register at any time. If there is
a current command under execution (busy status bit set)
TYPE III COMMAND Read Track/Address

VL2793 • VL2797
the command will be terminated and the busy status bit
reset.
The lower four bits of the command determine the condl·
tional interrupt as follows:
10
Not·Ready to Ready Transition
11
Ready to Not·ReadyTransition
12
Every Index Pulse
13
Immediate Interrupt
The conditional interrupt is enabled when the correspond·
ing bit positions of the command (13 . 10) are set to a 1.
Then, when the condition for Interrupt is met, the INTRQ
line will go high signifying that the condition specified has
occurred. If 13· 10 are all set to zero (HEX DO), no interrupt
will occur but any command presently under execution will
be immediately terminated. When using the immediate

=
=
=
=

READ TRACK
SEQUENCE

yes

168

VLSI TECHNOLOGY, INC.

interrupt condition 13 = 1), an interrupt will be immediately
generated and the current command terminated. Reading
the status or writing to the command regiSter will not automatically clear the interrupt. The HEX DO is the only com·
mand that will enable the immediate interrupt (HEX 08) to'
clear on a subsequent load command register or read sta·
tus register operation. Follow a HEX 08 with DO command.
Wait 8 micro sec (double density) or 16 micro sec (single
density) before issuing a new command after issuing a
forced interrupt (times double when clock = 1 MHz).
Loading a new command sooner than this will nullify the
forced interrupt.

VL2793 • VL2797
STATUS REGISTER
Upon receipt of any command, except the Force Interrupt
command, the Busy Status bit is set and the rest of the
status bits are updated or cleared for the new command. If
the Force Interrupt Command is received when there is a
current command under execution, the Busy status bit is
reset, and the rest of the status bits are unchanged .. If the
Force Interrupt command is received when there is not a
current command under execution, the Busy Status bit is
reset and the rest of the status bits are updated or cleared.
In this case, Status reflects the Type I commands.

Forced interrupt stops any command at the end of an in·
ternal micro-instruction and generates INTRa when the
specified condition is met. Forced interrupt will wait until
ALU operations in progress are complete (CRC
calculations, compares, etc.)

The user has the option of reading the status register
through program control or using the ORO line with DMA or
interrupt methods. When the Data register is read the ORO
bit in the status register and the ORO line are automatically
reset. A write to the Data register also causes both ORa's
to reset.
.

More than one condition may be set at a time. If for
example, the READY TO NOT·READY condition (11 = 1)
and the Every Index Pulse (12 = 1) are both set, the
resultant command would be HEX "DA." The "OR'" func·
tion is performed so that either a READY TO NOT·READY
or the next Index Pulse will cause an interrupt condition.

The busy bit in the status may be monitored with a user
program to determine when a command is complete, in lieu
of using the INTRa line. When using the INTRa, a busy
status check is not recommended because a read of the
status register to determine the condition of busy will reset
the INTRa line.
The format of the Status Register is shown below:
(BITS)

o
so

Status varies according to the type of command executed
as shown in Table 4.
Because of internal sync cycles, certain time delays must
be observed when operating under programmed I/O. They
1 MHz)
are: (times double when clock

Delay Req'd.
I
FM
MFM
I

Operation

Next Operation

Write to
Command Reg.

Read Busy Bit
(Status Bit 0)

1~s

Write to
Command Reg.

Read Status
Bits 1·7

2~s

Write Any
Register

Read From Ditt.
Register

I
I
I

6,.cs
1~s

I
I

IBM 3740 FORMAT - 128 BYTESISECTOR
Shown below is the IBM single-density format with 128
bytes/sector. In order to format a diskette, the user must
issue the Write Track command, and load the data register
with the following values. For every byte to be written, there
is one Data Request.

169

VLSI TECHNOLOGY, INC.

NUMBER
OF BYTES
40

6
1
26

6
1
1
1
1
1
1
11

6
1
128
1
27
2472

VL2793 • VL2797
HEX VALUE OF
BYTE WRITTEN
FF (or 00)3
00
FC (Index Mark)
FF(oroo)
00
FE (ID Address Mark)
Track Number
Side Number (00 or 01)
Sector Number (1 thru 1A)
00 (Sector Length)
F7 (2 CRC's written)
FF (or 00)
00
FB (Data Address Mark)
Data (IBM uses E5)
F7 (2 CRC's written)
FF(orOO)
FF (or 00)

1. Write bracketed field 26 times
2. Continue writing until 279X interrupts out.
Approx. 247 bytes.
3. A '00' option is allowed.
IBM SYSTEM 34 FORMAT·
256 BYTES/SECTOR
Shown below is the IBM dual·density format with 256
bytes/sector. In order for format a diskette the user must
issue the Write Track command and load the data register
with the following values. For every byte to be written, there
is one data request.

NUMBER
OF BYTES
80
12

3
1
*50
12

3
1

1
1

1
22
12

3
1
256

1
54
598**

HEX VALUE OF
BYTE WRITTEN
4E
00
F6 (Writes C2)
FC (Index Mark)
4E
00
F5 (Writes A 1)
FE (ID Address Mark)
Track Number (0 thru 4C)
Side Number (0 or 1)
Sector Number (1 thru 1A)
01 (Sector Length)
F7 (2 CRCs written)
4E
00
F5 (Writes A 1)
FB (Data Address Mark)
DATA
F7 (2 CRCs written)
4E
4E

* Write bracketed field 26 times
* * Continue writing until 279X interrupts out.
Approx. 598 bytes.

IBM TRACK FORMAT

' ...... ' ... ONlY IO .......... DO .. T...... M
ARE PRECEOED8Y THREE BYTES OF
A' WITH CI OCII fRANSITtOfrt BETW(£N

BITS."NOSM,SStNG

•• ... 'SSl ...GCLOCII.TA .. N$ITrO".

BETWHN8"SlANOt

_Wf'ITlTU"NO"'OfIIUItOATi
OfII",,[vIO\l&OA'A'"l0

170

VLSI TECHNOLOGY, INC.
VL2793 • VL2797

1. NON·IBM FORMATS
Variations in the IBM formats are possible to a limited ex·
tent if the following requirements are met:

MFM

Gap I
Gap II

16 bytes FF
11 bytes FF
6 bytes 00

Gap 111**

10 bytes FF
4 bytes 00

Gap IV

16 bytes FF

32 bytes 4E
22 bytes4E
12 bytes 00
3 bytes A1
24 bytes4E
8 bytes 00
3 bytes A1
16 bytes 4E

GAP

1) Sector size must be 128, 256, 512 of 1024 bytes.
2) Gap 2 cannot be varied from the IBM format.
3) 3 bytes of A 1 must be used in MFM.
In addition, the Index Address Mark is not required for
operation by the 279X. Gap 1,3, and 4 lengths can be as
short as 2 bytes for 279X operation, however PLL lock up
time, motor speed variation, write splice area, etc. will add
more bytes to each gap to achieve proper operation. It is
recommended that the IBM format be used for highest
system reliability.

ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Voltage to any input with
respect to Vss = + 7 to - 0.5V
Operating temperature = O°C to 70°C
Storage temperature = - 55°C to + 125°C

OPERATING CHARACTERISTICS(DC) TA
SYMBOL

CHARACTERISTIC

IlL
10L
VIH
VIL
VOH
VOL
VOHP
VOLP
Po
RpU
ICC

Input Leakage
Output Leakage
Input High Voltage
Input Low Voltage
Output High Voltaqe
Output Low Voltage
Output High PUMP
Output Low PUMP
Power Dissipation
Internal Pull-up*
Supply Current

* Byte counts must be exact.
* * Byte counts are minimum, except exactly 3 bytes of A 1
must be written.

NOTE: Maximum limits indicate where permanent device
damage occurs. Continuous operation at these limits is not
intended and should be limited to those conditions
specified in the DC Electrical characteristics.

= O°C to 70°C, Vss = OV, VCC = + 5V ± .25V
MIN

TYP

MAX

UNITS

10
10

2.0
0.8
2.4
0.45

2.2

100
70

0.2
.75
1700
150

* Internal Pull-up resistors on PINS 1, 17, 19, 22, 36, 37 and 40. Also pin 25 on 2793.

171

V
V
V
V
V
V
W
~A

rnA

CONDITIONS
VIN = VCC
VOUT = VCC

10 = -l00~A
10 = 1.6mA
lOp = -1.0mA
lOp = +1.0mA
All Outputs Open
VIN = OV
All Outputs Open

VLSI TECHNOLOGY, INC
VL2793 • VL2797

TIMING CHARACTERISTICS TA

= O°C to 70°C, VSS = OV, VCC = + 5V ± .25V

READ ENABLE TIMING
SYMBOL

CHARACTERISTIC

TSET
THLO
TRE
TORR
TIRR
TOACC
TOOH

Setup AOOR & CS to RE
Hold AOOR & CS from RE
RE Pulse Width
ORa Reset from RE
INTRa Reset from RE
Oata Valid from RE
Oata Hold From RE

TYP

MIN

MAX

UNITS

50
10

200
100

500
100
20

200
3000
200
150

CONDITIONS

nsec
nsec
nsec
nsec
nsec
nsec
nsec

See Note
CL
50pf
CL
50pf

UNITS

CONDITIONS

= 50pf
=
=

WRITE ENABLE TIMING
SYMBOL

CHARACTERISTIC

TSET
THLO
TWE
TORR
TIRR
TOS
TOH

Setup AOOR & CS to WE
Hold AOOR & CS from WE
WE Pulse Width
ORa Reset from WE
INTRa Reset from WE
Oata Setup to WE
Oata Hold from WE

TYP

MIN

MAX

50
10

nsec
nsec
nsec
nsec
nsec
nsec
nsec

200
100

500

200
3000

150
50

READ ENABLE TIMING

See Note

WRITE ENABLE TIMING
'6' OR 32' u S - - - - - - t

VOH

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __J~l

TIAR'~
'''TRO

IOAlI

f---:----;I---------,

---+--,

-----t---i
~---il--...J

JiIIOTE

cs MAV BE PERMANENlL y TIED lOW IF DESIRED
'T'hle OOUBlES WHEN CLOCK

'CS MAV BE PERIoIANENTl V TIED LOW 'F DESIRED
2 WHEN WRITING OAT A INTO SECTOR TIIACI< OR DATA
REGISTER USER CANNOT READ THIS REGISTER UNT ...
AT LEAST • ~SEC IN MFM AFTER THE RISING EDGE Of' WE
WHEN WRITING INTO THE c:oo....AND REGISTER STATUS
t SERVICE IWORST CASEI
IS NOT VALID UNTIL SOME 28 ~SEC IN FM. ,. ~SEC N MFM
'fM 235 uS
, ..... ,
LATER THESE T_S ARE DOUeLED WHEN CLK
'MFM
11 SuS
"TIME DOUeLES WHEN CLOCK
, .....z
NOTE

1 SERVICE (WORST CASEI

'FM
'MFM

275 uS
135 uS

ORO RISING EDGE" INDICATES THAT THE DATA REGISTER HAS ASSEMBLED
OATA

ORO FALLING EOGE: INDICATES THAT THE DATA REGISTER WAS READ
INTRO RISING EDGE· OCCURS AT END OF COMMAND
INTAQ fALLING EDGE INDICATES THAT THE STATUS REGISTER WAS REAO

OlIO RISING EDGE. INDICATES THAT THE DATA REGISTER IS EMPTV
OAQ FALLING EDGE: INOtCATES THAT THE OATA REGISTER IS lOAOEO
INTAQ RISING EDGE, INDICATE THE END Of' A COMMAND
INTAQ FALLING EDGE INDICATES THAT THE COMMAND REGISTER
IS WAlnEH TO

172

VLSI TECHNOLOGY, INC.
VL2793 • VL2797

INPUT DATA TIMING
SYMBOL

CHARACTERISTIC

TPW
TSC

Raw Read Pulse Width
Raw Read Cycle Time

WRITE DATA TIMING: (All TIMES DOUBLE WHEN ClK

MIN
100
1500

TYP

MAX

UNITS

CONDITIONS

nsec
nsec

200
2000

= 1 MHz) (NO WRITE PRECOMPENSATION)

SYMBOL

CHARACTERISTIC

MIN

TYP

MAX

UNITS

CONDITIONS

TWp

Write Data Pulse Width

400
200

600
300

TWG

Write Gate to Write Data

TWF

Write Gate off from WD

500
250
2
1
2
1

nsec
nsec
IAsec
IAsec
IAsec
IAsec

FM
MFM
FM
MFM
FM
MFM

MISCELLANEOUS TIMING:
SYMBOL

CHARACTERISTIC

MIN

TYP

MAX

UNITS

CONDITIONS

tCD1
tCD2
tSTP
tDIR
tMR
tiP
RWP

Clock Duty (low)
Clock Duty (high)
Step Pulse Output
Dir Setup to Step
Master Reset Pulse Width
Index Pulse Width
Read Window Pulse Width

230
230
2 or4

250
250

20000
20000

nsec
nsec
IAsec
IAsec
IAsec
IAsec

See Note
± ClKERROR

WPW

Precomp Adjust.
Write Data Pulse Width

WPW

Write Data Pulse Width

VCO

Free Run Voltage Controlled
Oscillator. Adjustable by ext.
capacitor on Pin 26
Pump Up + 25%

VCO

VCO
Cext
RClK

PUIDON
flOCK*

50
10
120
240
100

nsec
nsec
nsec

200

300

400

nsec

600
6.0

900

1200

nsec
MHz
MHz

4.0

MHz

5.0

Pump Down - 25%
5% Change VCC
TA
75°C
Adjustable external capacitor

700
1400
300

3.B
3.5
20

3.0

MHz

4.2

MHz
MHz
pf

100

Derived read clock
VCO -;- B,16,32

PUIPD time on
(pulse width)
Data Separator Capture Range

237.5

*The flOCK specification is guaranteed from 10° C to 40° C.

173

500

KHz

250

KHz

250

KHz

125

KHz

250

250
500
262.5

ns
ns
kbits/sec

See Note
Input0-5V
MFM
FM ± 15%
MFM
Precomp
100 nsec
MFM
Precomp
300 nsec
FM
0
Cext
35 pf
Cext

=
=
=
=
PU = 2.2V
Cext = 35 pf
PO = 0.2V
Cext = 35 pf
Cext = 35pf
Cext = 35 pf
VCO = 4.0MHz
nom
VCO = 4.0MHz
DDEN = 0
5/B = 1
DDEN = 0
5/B = 0
DDEN = 1
5/B = 1
DDEN = 1
5/B = 0
MFM
FM
5/8 .~ 0

VLSI TECHNOLOGY, INC.
VL2793 • VL2797

MISCELLANEOUS TIMING
iP j~_ _----,

WRITE DATA TIMING

--.J

WO~---~

r--TIP_-I

'---1----\j

--.;

VlH

r--I------\$

: . -TWG

WG~

I----T w, --1

~TWp

--.:
l+- TWF
----~

VIH

READ DATA TIMING
T"R--l

I 1----TBC----i..~1
1-oII
..

REAO-U
OATA
~ TPW

-+I

OIRe

VOH
VOL

STEP IN
_

R,Ro' _

~
I- -I 1--

'-----

NOTES:

I~r-----IL
TOIR -1TS . . I-----IT5TP\--

TOIR

1. Times double when clock = 1 MHz.
2. Output timing readings are at VOL
2.0v.

TSTP

= 0.8v and VOH

• FROM STEP RATE TABLE
TABLE 4. STATUS REGISTER SUMMARY
BIT
S7
S6
S5
S4
S3
S2
S1
SO

ALL TYPE I
COMMANDS

READ
ADDRESS

READ
SECTOR

READ
TRACK

WRITE
SECTOR

WRITE
TRACK

NOT READY
WRITE
PROTECT
HEAD LOADED
SEEK ERROR
CRC ERROR
TRACK 0
INDEX PULSE
BUSY

NOT READY
0

0
RNF
CRC ERROR
LOST DATA
ORO
BUSY

RECORD TYPE
RNF
CRC ERROR
LOST DATA
DRO
BUSY

0
0
0
LOST DATA
ORO
BUSY

NOT READY
WRITE
PROTECT
0
RNF
CRC ERROR
LOST DATA
DRO
BUSY

NOT READY
WRITE
PROTECT
0
0
0
LOST DATA
DRO
BUSY

STATUS FOR TYPE I COMMANDS
BIT NAME

MEANING

S7 NOT READY

This bit when set indicates the drive is not ready. When reset it indicates that the drive is ready.
This bit is an inverted copy of the Ready input and logically 'ored' with MR.

S6 PROTECTED

When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT input.

S5 HEAD LOADED

When set,it indicates the head is loaded and engaged. This bit is a logical "and" of HLD and HLT
signals.

S4 SEEK ERROR

When set, the desired track was not verified. This bit Is reset to 0 when updated.

S3 CRC ERROR

CRC encountered in ID field.

S2TRACKOO

When set, indicates Read/Write head is pOSitioned to Track O. This bit Is an inverted copy of the
TROO input.

S11NDEX

When set, indicates index mark detected from drive. This bit is an Inverted copy of the IP Input.

SO BUSY

When set command is in progress. When reset no command is In progress.

174

VLSI TECHNOLOGY, INC.
VL2793 • VL2797

STATUS FOR TYPE II AND III COMMANDS
BIT NAME

MEANING

S7 NOT READY

This bit when set indicates the drive is not ready. When reset, it indicates that the drive is ready.
This bit is an inverted copy of the Ready input and 'ored' with MR. The Type II and III Commands
will not execute unless the drive is ready.

S6 WRITE PROTECT

On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a Write Protect.
This bit is reset when updated.

S5 RECORD TYPE

On Read Record: It indicates the record-type code from data field address mark. 1 = Deleted
Data Mark. 0 = Data Mark. On any Write: Forced to a Zero.

S4 RECORD NOT
FOUND (RNF)

When set, it indicates that the desired track, sector, or side were not found. This bit is reset when
updated.

S3 CRC ERROR

If S4 is set, an error is found in one or more 10 fields; otherwise it indicates error in data field. This
bit is reset when updated.

S2 LOST DATA

When set, it indicates the computer did not respond to DRQ in one byte time. This bit is reset to
zero when updated.

S1 DATA REQUEST

This bit is a copy of the DRQ output. When set, it indicates the DR is full on a Read Operation or
the DR is empty on a Write operation. This bit is reset to zero when updated.

SO BUSY

When set, command is under execution. When reset, no command is under execution.

SUMMARY OF ADJUSTMENT PROCEDURE
WRITE PRECOMPENSATION
1)
2)
3)
4)
5)
6)

Set TEST (Pin 22) to a logic high.
Strobe MR (Pin 19).
Set TEST (Pin 22) to a logic low.
Observe pulse width on WD (Pin 31).
Adjust WPW (Pin 33) for desired pulse width (Precomp Value).
Set TEST (Pin 22) to a logic high.

DATA SEPARATOR
1)
2)
3)
4
5)
6)
7)
8)

Set TEST (Pin 22) to a logic high.
Strobe MR (Pin 19). Insure that 5i8, and DDEN are set properly.
Set TEST (Pin 22) to a logic low.
Observe Pulse Width on TG43 (Pin 29).
Adjust RPW (Pin 18) for 1/8 of the read clock (250ns for 8" DO, 500ns for 5114" DO, etc.).
Observe Frequency on DIRC (Pin 16).
Adjust variable capacitor on VCO pin for Data Rate (500 KHz for 8" 00,250 KHz for 5 1/4" DO, etc.).
Set TEST (Pin 22) to a logic high.

NOTE: To maintain internal VCO operation, insure that TEST = 1 whenever a master reset pulse is applied.

175

VLSI TECHNOLOGY, INC

176

VLSI TECHNOLOGY, INC.
VL4500A
DYNAMIC RAM CONTROLLER

FEATURES
• Controls operation of 8K116K132K164K
dynamic RAMs

• Three-state outputs allow multipart
memory configuration

• Creates static RAM appearance

• Performance ranges of 150 ns/200
nsl250 ns

• One package contains address
multiplexer, refresh control and timing
control
• Directly addresses and drives up to
256K bytes of memory without external
drivers
• Operates from microprocessor clock
• Refresh may be internally or externally
initiated
• Strap-selected wait state generation
for microprocessor/memory speed
matching

• Compatible with TI TMS 4500A

DESCRIPTION
The VL4500A is a monolithic DRAM
system controller designed to provide
address multiplexing, timing, control,
and refresh/access arbitration functions to simplify the interface of
dynamic RAMs to microprocessor
systems.
The controller contains a 16-bit
multiplexer that generates the address

lines for the memory device from the 16
system address bits and provides the
strobe signals required by the memory to
decode the address. An 8-bit refresh
counter generates the 256-row addresses required to refresh.
A refresh timer is provided that generates the necessary timing to refresh the
dynamic memories and assure data
retention.
The VL4500A also contains refresh/
access arbitration circuitry to resolve
conflicts between memory access
requests and memory refresh cycles.
The VL4500A is offered in a 40-pin 600mil dual-in-line plastic package and is
guaranteed for operation from O°C to
70°C.

BLOCK DIAGRAM

PIN DIAGRAM
VL4500A

RAO-RA7

--r---+I
8

CLK

ROY
REN1
-CS
ALE

-RASO
-RAS1
-ACR
-ACW

-CAS
RAO
CAO
MAO
MA1
CA1
RA1

RA2
CA2.
MA2.

GNO

I - - r - - ' MAO-MA7

VCC

-REFREQ

CArJ-CA7

--r---+I

TWST

FSO
FS1
RA7
CA7
MA7
MA6
CA6
RA6
RAS
CAS
MAS
RA4

MM
RA3
CA3
MA3

AlE - - - - - - 4 1 1 - - -..

-cs ---tor:~:;-l
. - - - - + -RASO
REN1 ---~_ _ _~~-----_j

----------------t

-ACR
-ACW --------r======;I~
-REFREQ _ _ _ _ _ _ _ _

1 - - - - - + -RAS1

.----+-CAS

roST _ _ _ _ _ _ _-+~~~~
________
F~

c~------_J==~====~~
ORDER INFORMATION
Part
Number

. - - - - + ROY

FS1 _ _ _ _ _ _ _ _

Access
Time

Package

VL4500-15PC
VL4500-15CC

150 ns

Plastic DIP
Ceramic DIP

VL4500-20PC
VL4500-20CC

200 ns

Plastic DIP
Ceramic DIP

Note: Operating temperature range is O°C to +70°C.

177

____J

VLSI TECHNOLOGY, INC.
VL4500A

PIN DESCRIPTIONS
RAO-RA7

Input

Row Address - Used to generate the row address for the multiplexer.

CAO-CA7

Input

Column Address - Used to generate the column address for the multiplexer.

MAO-MA7

Output

Memory Address - 3-state outputs designed to drive the addresses of the
Dynamic RAM array.

ALE

Input

Address latch Enable - Used to latch the 16 address inputs, CS and REN1. This also
initiates an access cycle if Chip Select is valid. The rising edge (lOW-to-HIGH level) of
ALE returns RAS to HIGH.

Input

Chip Select - A lOW on this input enables an access cycle. The trailing edge of ALE
latches the Chip Select input.

REN1

Input

RAS Enable 1 - Used to select one of two banks of RAM via the RASO and RAS1
outputs when chip select is present. When lOW, RASO is selected; when HIGH, RAS1 is
selected.

ACR, ACW

Input

Access Control, Read; Access Control, Write - A lOW on either of these inputs causes
the column address to appear on MAO-MA7 and the Column Address Strobe to pulse
active lOW. The risi~dge of ACR or ACW terminates the cycle by ending RAS and
CAS strobes. When ACR and ACW are both lOW, MAO-MA7, RASO, RAS1, and CAS go
into a high-impedance (floating) state.

ClK

Input

System Clock - Provides the master timing to generate refresh cycle timings and refresh
rate. Refresh rate is determined by the TWST, FS1, FSO inputs.

REFREQ

Input/
Output

Refresh Request - (This input should be driven by an open-collector output.) On
input, a lOW-going edge initiates a refresh cycle and will cause the internal refresh timer
to be reset on the next falling edge of the ClK. As an output, a lOW-going edge signals
an internal refresh request and that the refresh timer will be reset on the next lOW-going
edge of ClK. REFREQ will remain lOW until the refresh cycle is in progress and the
current refresh address is present on MAO-MA7. (Note: REFREQ contains an internal
pull-up resistor with a nominal resistance of 10 k!1.)

RASO, RAS1 Output

Row Address Strobe - 3-state outputs used to latch the row address into the bank of
DRAMs selected by REN1. On refresh both signals are driven.

CAS

Output

Column Address Strobe - 3-state output used to latch the column address into the
DRAM array.

ROY

Output

Ready - Totem-pole output used to synchronize memories that are too slow to
guarantee microprocessor access time requirements. This output is also used to inhibit
access cycles during refresh when in cycle-steal mode.

TWST

Input

Timing/Wait Strap - A HIGH on this input indicates a wait state should be added to each
memory cycle. In addition, it is used in conjunction with FSO and FS1 to determine
refresh rate and timing.

FSO, FS1

Inputs

Frequency Select 0; Frequency Select 1 - Strap inputs used to select Mode and
Frequency of operation as shown in Table 1.

178

VLSI TECHNOLOGY, INC.
VL4500A

TABLE 1:

STRAP CONFIGURATION

TWST

FS1

FSO

Walt
Stales
For
Memory
Access

L
L
L
L

L
L
H
H

L (1)
H
L
H

a
a
a
a

External
Clk +31
Clk + 46
Clk + 61

1.984
2.944
3.904

Refreq.
64-95 (2)
64-85 (2)
64-82 (3)

4
3
3
4

L
L

H
H

L
H
L
H

1
1
1
1

Clk + 46
Clk + 61
Clk + 76
Clk+91

2.944
3.904
4.864
5.824

64-85
64-80
64-77
64-88

(2)
(2)
(2)
(4)

3
4
4
4

Strap Input Modes

Refresh
Rate

Minimum
Clk Freq
1M Hz)

Refresh
Freq (kHz)

Clock
Cycles
For Each
Refresh

Noles:
1. This strap configuration resets the Refresh Timer circuitry.
2. Upper figure in refresh frequency is the frequency produced if the minimum CLK frequency of the next select stale is used.
3. Refresh frequency if CLK frequency is 5 MHz.
4. Refresh frequency if CLK frequency is 8 MHz.

FUNCTIONAL DESCRIPTION
VL4500A consists of six basic
blocks; address and select latches,
refresh rate generator, refresh
counter, the multiplexer, the arbiter,
and the timing and control block.

ADDRESS AND SELECT
LATCHES
The address and select latches
allow the DRAM controller to be
used in systems that multiplex
address and data on the same lines
without external latches. The row
address latches are transparent,
meaning that while ALE is HIGH,
the output at MAO-MA7 follows the
inputs RAO-RA7.

REFRESH RATE GENERATOR

MULTIPLEXER
Upon power-up it is necessary to
provide a reset signal by driving all
three straps to the controller LOW
to initialize internal counters. A
system's LOW-active, power-on
reset (RESET) can be used to
accomplish this by connecting it to
those straps that are desired HIGH
during operation. During this reset
period, at least four clock cycles
should occur.

REFRESH COUNTER
The refresh counter contains the
address of the row to be refreshed.
The counter is decremented after
each refresh cycle. IA LOW-toHIGH transition on TWST sets the
refresh counter to FF16 (25510).1

The refresh rate generator is a
counter that indicates to the arbiter
that it is time for a refresh cycle. The
counter divides the clock frequency
according to the configuration
straps as shown in Table 1. The
counter is reset when a refresh
cycle is requested or when TWST,
FS1 and FSO are LOW. The
configuration straps allow the
matching of memories to the system
access ti me.

The multiplexer provides the
DRAM array with row, column,
and refresh addresses at the
proper times. Its inputs are the
address latches and the refresh
counter. The outputs provide up
to 16 multiplexed addresses on
eight lines.

ARBITER
The arbiter provides two operational
cycles; access and refresh. The
arbiter resolves conflicts between
cycle requests and cycles in
execution, and schedules the
inhibited cycle when used in cyclesteal mode.

TIMING AND
CONTROL BLOCK
The timing and control block
executes the operational cycle at
the request of the arbiter. It provides
the DRAM array with RAS and CAS
signals. It provides the CPU with a
ROY signal. It controls the
multiplexer during all cycles. It
resets the refresh rate generator and
decrements the refresh counter
during refresh cycles.

179

VLSI TECHNOLOGY, INC.
VL4500A

ABSOLUTE MAXIMUM RATINGS
Operating Ambient
O°C to +70°C
Temperature Range
Storage Temperature
-65°C to +150°C
Range
Supply Voltage
Range, Vee, Note 1
-1.5 to +7 V
Input Voltage Range
(any input), Note 1
-1.5 to +7 V
Continuous Power
1.2W
Dissipation

Stresses above those listed under
"Absolute Maximum Ratings" may
cause permanent damage to the
device. These are stress ratings only.
Functional operation of this device
at these or any other conditions

above those listed on the
operational sections of this
specification is not implied and
exposure to absolute maximum
rating conditions for extended
periods may affect device reliability.

DC CHARACTERISTICS: T A = O°C to +70°C
Symbol

Parameter

Vil (except REFREQ)

Input LOW Voltage

-1.0 (2)

Vil (REFREQ)

Input LOW Voltage

-1.0 (2)

0.8

VIH

Input HIGH Voltage

2.4

6.0

Val

'Output LOW Voltage

0.4

Min

MAO-MA7, ROY

2.4

RASO, RAS 1, CAS

2.7

REFREQ

2.4

VOH

Output HIGH
Voltage

IIH

Input HIGH
Current
All pins except REFREQ

III

Input LOW
Curren·t

loz

Output Off-State Current

lee

Operating Supply Current

Typ (3)

Max

Unit

0.8

Conditions

10l = 4 mA

Vee = 4.5 V

10H = -1 mA

Vee =4.5 V

10H = -100 p,AVee = 4.5 V
p,A

VI = 5.5 V

REFREQ

-1.25

All others

-10

p,A

100

VI=OV

±50

p,A

Va = 0 to 4.5 V Vee = 5.5 V

140

TA = O°C

Vee=5.5V

CAPACITANCE: TA = 25°C, f = 1.0 MHz
Symbol Parameter

Min

Typ (3)

Max

Unit

Conditions

I nput Capacitance

VI=OV

f = 1 MHz

Output Capacitance

Va = OV

f = 1 MHz

Notes:
1. Voltage values are with respect to the ground terminal.
2. The algebraic convention, where the more negative limit is designated as minimum, is used in this data sheet for logic voltage levels only.
3. All typical values are at Vcc = 5 V, TA = 25° C except where otherwise noted.

180

VLSI TECHNOLOGY, INC.
VL4500A

AC CHARACTERISTICS: TA = O°C to +70°C, Vee = 5 V ± 10%
VL4S00A-1S

VL4S00A-20

VL4S00A-25

Symbol

Parameter

Min

tC(C)

CLK Cycle Time

100

tW(CH)

CLK HIGH Pulse Width

tW(CU

CLK LOW Pulse Width

Max

Min

Max

120

Min

Transition Time, All Inputs

tAEL-CL

Time Delay, ALE LOW to
CLK Starting LOW, Note 1

tCL-AEL

Time Delay, CLK LOW to
ALE Starting LOW, Note 1

tCL-AEH

Time Delay, CLK LOW to
ALE Starting HIGH, Note 2

tW(AEH)

Pulse Width ALE HIGH

tAV-AEL

Time Delay, Address, REN1,
CS Valid to ALE LOW

tAEL-AX

Time Delay, ALE LOW to
Address Not Valid

tAEL-ACL

Time Delay, ALE LOW to
ACX LOW, Notes 3, 4, 5, 6

th(RA) + 30

th(RA) + 40

th(RA) + 50

tACH-ci

Time Delay, ACX HIGH to
CLK LOW, Notes 3, 7

tACL-CH

Time Delay, ACX LOW to
CLK Starting HIGH (to
remove RDY)

tRQL-CL

Time Delay, REFREQ LOW
to CLK Starting LOW, Note 8

tW(RQU

Pulse Width, REFREQ LOW

Max

Unit

140

Notes:
1. Coincidence of the trailing edge of ClK and the trailing edge of ALE should be avoided, as the refresh/access occurs on the trailing ClK
edge. A trailing edge of CLK should occur during the interval from ACX HIGH to ALE lOW.
2. If ALE rises before ACX and a refresh request is present, the falling edge of ClK after tCL-AEH will output the refresh address to MAD-MA7
and initiate a refresh cycle.
3. These specifications relate to system timing and do not directly reflect device performance.
4. On the access grant cycle following refresh, the occurrence of CAS lOW depends on the relative occurrence of ALE lOW to ACX lOW. If
ACX occurs prior to or coincident with ALE then CAS is timed from the ClK HIGH transition that causes RAS lOW. If ACX occurs 20 ns or
more after ALE then CAS is timed from the ClK lOW transition following the ClK HIGH transition causing RAS lOW.
5. For maximum speed access (internal delays on both access and access grant cycles), ACX should occur prior to or coincident with ALE.
6. thcRA) is the dynamic memory row address hold time. ACX should follow ALE by tAEL-CEL in systems where the required thcRA) is greater than
tREL-MAX minimum.
7. Minimum of 20 ns is specified to ensure arbitration will occur on falling ClK edge. tACH-CL also affects precharge time such that the
minimum tACH-CL should be equal or greater than: twcRH)-twcCll + 30 ns (for cycle where ACX HIGH occurs prior to ALE HIGH) where twcRHI
is the DRAM RAS precharge time.
8. This parameter is necessary only if refresh arbitration is to occur on this falling edge of ClK (jn systems where refresh is synchronized to
external events).

181

VLSI TECHNOLOGY, INC
VL4500A

AC CHARACTERISTICS: TA = O°C to +70°C, Vee = 5 V ± 10%
Symbol

Parameter

tAEL-REL

Time Delay, ALE lOW to RAS Starting lOW

VL4500A-15
Min
Max
35

VL4500A-20
Min
Max
40

VL4500A-25
Min
Max

RAS Fall Time

Time Delay, Row Address Valid to
Memory Address Valid

tAEH-MAV

Time Delay, ALE HIGH to Valid
Memory Address

tAEL-RYL

Time Delay, ALE to ROY Starting lOW
(TWST = 1 or Refresh in Progress)

tAEL-CEL

Time Delay, ALE lOW to CAS Starting
lOW, Note 9

tAEH-REH

Time Delay, ALE HIGH to RAS Starting
HIGH

tt(MAV)

Address Transition Time

tACL-MAX

Row Address Hold from ACX lOW

tMAV-CEL

Time Delay, Memory Address Valid to
CAS Starting lOW

tt !RELI
tRAv-MAV

tt (CEll
tACL-CEL

150
30

200

20
25

15
100

20
45

130

250

Time Delay, ACX to RAS Starting HIGH

RAS Rise Time

tACH-CEH

Time Delay, ACX HIGH to CAS Starting
HIGH

20
40

tt (CEHI
tACH-MAX

CAS Rise Time

tCH-RYH

Time Delay, ClK HIGH to ROY Starting
HIGH (After ACX lOW), Note 10

tRFL-RFL

Time Delay, REFREQ External Until
Supported by REFREQ Internal

tCH-RFL

Time Delay, ClK HIGH Until REFREQ
Internal Starting lOW

tCL-MAV

Time Delay, ClK lOW Until Refresh
Address Valid

100

125

tCH-RRL

Time Delay, ClK HIGH Until Refresh
RAS Starting lOW

tMAV-RRL

Time Delay, Refresh Address Valid
Until Refresh RAS lOW

tCL-RFH

Time Delay, ClK lOW to REFREQ
Starting HIGH (3-cycle Refresh)

tCH-RFH

Time Delay, ClK HIGH to REFREQ
Starting HIGH (4-cycle Refresh)

tCH-RRH

Time Delay, ClK HIGH to Refresh RAS
Starting HIGH

tCH-MAX

Time Delay, Refresh Address Hold
After ClK HIGH

Column Address Hold from ACX HIGH

30
10

50
45

35
15

CL = 320 pF

165

tt (REHI

CL=160pF

25
50

tACH-REH

CL = 40 pF

Conditions
CL=160pF

CAS Fall Time
Time Delay, ACX lOW to CAS Starting
lOW, Note 9

Unit

CL=160pF
ns
CL = 320 pF
CL=160pF

CL = 40 pF

10
20

CL=160pF

Notes:
9. The falling edge of CAS occurs as soon as both tAEL-CEL and tACL-CEL have elapsed. If ACX goes LOW prior to (tAEL-CEU - (tACL-CEL) after
ALE. the CAS timing is determined by tAEL-CEL. Otherwise. the access time increases, and the falling edge of CAS is measured from the
falling edge of ACX instead of ALE (tACL-CEL determines CAS timing!.
10. ROY returns HIGH on the rising edge of ClK. If TWST = O. then on an access grant cycle ROY goes HIGH on the same edge that causes
access RAS lOW. If TWST = 1. then ROY goes to the HIGH level on the first rising ClK edge after ACX goes lOW on access cycles and on
the next rising edge after the edge that causes access RAS lOW on access grant cycles (assuming ACX LOW>.

182

VLSI TECHNOLOGY, INC.
VL4500A

AC CHARACTERISTICS: TA= O°C to+70°C, Vcc= 5 V± 10%
VL4500A-15
Min
Max

VL4500A-20
Min
Max

Time Delay, ClK HIGH Until Access RAS
Starting lOW

tCl-CEl

Time Delay, ClK lOW to Access CAS
Starting lOW, Note 11

125

140

185

tCl-MAX

Row Address Hold After ClK lOW

tW(ACLl

ACX lOW Width, Note 12

110

140

175

tREL-MAX

Row Address Hold From RAS lOW

tt(RYLl

ROY Fall Time

tt(RYH)

ROY Rise Time

tdis

Output Disable Time (3-state Outputs)

tAEH-MAX

Column Address Hold From ALE HIGH

ten

Output Enable Time (3-state Outputs)

tCAV-CEl

Column Address Setup to CAS After
Refresh

tCH-CEl

Time Delay, ClK HIGH to Access
CAS Starting lOW, Note 11

tACl-Cl

ACX lOW to ClK Starting lOW, Note 13

tACl-RYH

ACX lOW to ROY Starting HIGH, Note 13

tCl-ACl

ClK lOW to ACX Starting lOW, Note 13

Symbol

Parameter

tCH-REl

100

125

Cl = 40 pF

105

Cl=160pF

235
45

0
200

Cl=160pF

165

80
0

180

Conditions

Unit

VL4500A-25
Min
Max

Cl = 40 pF

Notes:
11. On the access grant cycle following refresh, the occurrence of CAS lOW depends on the relative occurrence of ALE lOW to ACX lOW.
If ACX occurs prior to or coincident with ALE then CAS is timed from the ClK HIGH transition that causes RAS lOW. If ACX occurs 20
ns or more after ALE then CAS is timed from the ClK lOW transition following the ClK HIGH transition causing RAS lOW.
12. The specification of tw (ACL) is designed to allow a CAS pulse. This assures normal operation of the device in testing and system
operation.
13. For RDY HIGH transition (during normal access) to be timed from the rising edge of ClK, ACX must occur tCL-ACL after the falling edge
of ClK. For ACX prior to the falling edge of ClK by tACL-CL, the RDY HIGH transition will be tACL-RYH. Note that tACL-CL is a limiting
parameter for control of RDY to be dependent on ACX lOW. During the interval for tACL-CL < MINIMUM to tCL-ACL > MINIMUM, the
control of RDY may vary between the rising clock edge or falling edge of ACX.

AC TESTING INPUT, OUTPUT WAVEFORM

LOAD CIRCUIT

vee

3.0 V

TEST POINTS

1150 II

UND~~~~~i-----"""'----""'"
2400 II

·CL INCLUDES JIG CAPACITANCE

INPUT

OUTPUT

Cl = 160 pF'

AC testing inputs are driven at 3.0 V for a logic "1" and
0.0 V for a logic "0". Timing measurements are made at
2.2 V for a logic "1" and 0.6 V for a logic "0" at the
outputs. The inputs are measured at 2.4 V for a logic "1"
and 0.8 V for a logic "0".
183

VLSI TECHNOLOGY, INC.
VL4500A

TIMING DIAGRAMS
ACCESS CYCLE TIMING

ClK

ALE

ROW RENT

COl,CS

COLUMN ADDRESS

tt(CEl)

tAEl-RYl

ROY
tt(RYH)

tt(RYl)
1_ _ _ _ _ _ _ _ _

tAEL-CEl

REFRESH REQUEST TIMING
ClK

~
(EXTERNAL)

\~-

REFREQ
(INTERNAL)

184

VLSI TECHNOLOGY, INC.
VL4500A

TIMING DIAGRAMS (ConU
OUTPUT 3-STATE TIMING

REFRESH CYCLE TIMING (3-CYCLE)

CLK

tCl-RFH

-I--j

1- MAO-MA7

Jr-

/
V
I--

tCl-MAV

REFRESH ADDRESS

tCH-RRl

I--

RAS

1--

tCH-MAX

tCl_MAX!

ROW ADDRESS

1
tCH-RRH

- ! - tCH -REL

tCAV·CEL

1--

V
I-- tCl·CEL t -

~tMAV.RRl------'

i\tCH·CEL!

REFRESH CYCLE TIMING (4-CYCLE)

"The voltage levels (on a RAS or CAS pin) used for testing tOIS and ten are at 10% and 90% of the VOH-VOL range for that pin.
tan the access grant cycle following refresh, the occurrence of CAS lOW depends on the relative occurrence of ALE lOW to ACX lOW. If
ACX occurs prior.to or coincident with ALE then CAS is timed from the ClK HIGH transition that causes RAS lOW. If ACX occurs 20 ns or
more after ALE then CAS is timed from the ClK lOW transition following the ClK HIGH transition causing RAS LOW.

185

VLSI TECHNOLOGY, INC
VL4500A

TIMING DIAGRAMS (Cont.)
TYPICAL ACCESS/REFRESH/ACCESS CYCLE (3-CYCLE, TWST = 0)
ACCESS
2

REFRESH/ACCESS GRANT
W,
W2
2

ACCESS
2

TYPICAL ACCESS/REFRESH/ACCESS CYCLE (4-CYCLE, TWST = 0)
ACCESS

REFRESH/ACCESS GRANT
W

ClK

ALE

MAX

ROY

186

VLSI TECHNOLOGY, INC.
VL4500A

TIMING DIAGRAMS (ContJ
TYPICAL ACCESS/REFRESH/ACCESS CYCLE (3-CYCLE, TWST
ACCESS

= 1)
REFRESH/ACCESS GRANT

ClK

ALE

MAX

ROY

TYPICAL ACCESS/REFRESH/ACCESS CYCLE (4-CYCLE, TWST

= 1)

187

VLSI TECHNOLOGY. INC.
VL4500A

READY (ROY) SIGNAL TIMING (WAIT STATE OPERATION, TWST

ClK

ALE

ROY

RDY starting HIGH is timed from ACX LOW (tACL-RYH) for the condition ACX going LOW while CLK HIGH.
ClK

ALE

tCL-ACL-+-~_

tCH-RYH

ROY

RDY starting HIGH is timed from CLK HIGH (tCH-RYH) for the condition ACX going LOW while CLK LOW.

188

VLSI TECHNOLOGY, INC
VL4500A

TYPICAL APPLICATIONS
68000 CPU TO VL4S00A 128K

x 16 MEMORY INTERFACE

MC68000

-------------------------------,ClK
VL4S00A

" ' - - - - - -... AlE

ClK L
AlB
A17

Al·A16

...._ _ _--![>

L[============~~~~~_-_-_-_-_-_-_--1
L----------------v L~~....::.:;.:::;:...:.:.;~..;;.;;rir_..

OTAcKt==~~~=====t~~~=l~L-_f=t::::::::::::::~-t_l
RIW

lOS L _ _ _ _ ____

00·07

OB·15

808SA CPU INTERFACE TO VL4S00A CONTROLLER

BOBSA

CONFIGURATION
STRAPS

'See section 5.1. p. 12.

189

VLSI TECHNOLOGY, INC.

190

VLSI TECHNOLOGY, INC.
VL4502
DYNAMIC RAM CONTROLLER

FEATURES
• Inputs are TTL voltage compatible
• Controls operation of 64K and
256K dynamic RAMs
• Creates static RAM appearance
• One package contains address
multiplexer, refresh control and
timing control
• Directly addresses and drives up to
2 megabytes of memory without
external drivers
• Operates from microprocessor
clock
-No crystals, delay lines, or RC
networks
-Eliminates arbitration delays

DESCRIPTION
• High performance CMOS
technology

The VL4502 is a monolithic DRAM
system controller providing address
multiplexing, timing, control and
refresh/access arbitration functions
to simplify the interface of dynamic
RAMs to microprocessor systems.

• Strap-selected wait state
generation for microprocessor/
memory speed matching
• Ability to synchronize or interleave
controller with the microprocessor
system (including multiple
controllers)

The controller contains an 18-bit
multiplexer that generates the
address lines for the memory device
from the 18 system address bits and
provides the strobe signals required
by the memory to decode the
address. A 9-bit refresh counter
generates up to 512 row addresses
required to refresh.

• 3-state outputs allow multi port
memory configuration
• Performance ranges of
150 ns/200 ns
• Compatible with VLSI VL4500A
and TI TMS4500A, THCT4502

A refresh timer is provided that
generates the necessary timing to
refresh the dynamic memories and
assure data retention.

• Refresh may be internally or
externally initiated

PIN DIAGRAMS
HC
~

MAO
~

RAO
~

~
~
ALE
RENI
HC
~
~
~
~
~

VL4502 DIP

MA5
HC

RA5
CAS

CAl
RAI

GHD
MAl

CA7
MA 7

FSI

TWST
FSO

HC
HC

ORDER INFORMATION
Part
Number

Access
Time

Package

VL4502-15PC
VL4502-15CC
VL4502-15QC

150 ns

Plastic DIP
Ceramic DIP
Plastic Leaded Chip Carrier (PLCC)

VL4502-20PC
VL4502-20CC
VL4502-20QC

200 ns

Plastic DIP
Ceramic DIP
Plastic Leaded Chip Carrier (PLCC)

Note:
Operating temperature range: O°C to + 70°C.

191

ViSI TECHNOLOGY, INC.
VL4502

BLOCK DIAGRAM

RAG-RA8

CAG-CA8

MAG-MAS

AlE-----

CS
REN1
REN2
ACR
ACW
REFREQ

TWST
FSO
FS1

'iJ

fiEii

'iJ

fiA§i

'iJ

nMING
'iJ
AND
CONTROL

fim

'iJ

CA§j

'iJ

CUi
ROY

ClK
RESET-

192

VLSI TECHNOLOGY, INC.
VL4502

PIN DESCRIPTIONS
Pin
Name

Pin
Number,
Note 1

Description

RAO-RAS

3, S, 9, 15, Row Address-These address inputs are used to generate the row address for the multiplexer.
1S, 21,22,
27,32

CAO-CAS

4,7,10,
Column Address-These address inputs are used to generate the column address forthe
14, 17,20, multiplexer.
23,26,33

MAO-MAS

5,6, 11,
Memory Address-These three-state outputs are designed to drive the addresses of the
13,16,19, Dynamic RAM array.
24,25,34

ALE

Address latch Enable-This input is used to latch the 1S address inputs, CS and REN1 and
REN2. This also initiates an access cycle if chip select is valid. The rising edge (lOW level to
HIGH level) of ALE returns RAS to the HIGH level.

Chip Select-A lOW on this input enables an access cycle. The trailing edge of ALE latches the
chip select input.

REN1, REN2 43,36

RAS Enable 1 and 2-These inputs are used to select one of four banks of RAM. When REN2 is
lOW, the lower banks are enabled via CASO, RASO, and RAS1. When REN2 is HIGH, the higher
banks are enabled via CAS1, RAS2, and RAS3. REN1 selects RASO, RAS2 or RAS1, RAS3
when chip select is present.

ACR, ACW

4S, 1

Access Control, Read; Access Control, Write-A lOW on either of these inputs causes the column addresses to appear on MAO-MAS and the column address strobe. The rising edge of ACR
or ACW terminates the cycle by ending RAS and CAS .strobes. When ACR and ACW are both
lOW, MAO-MAS, RASO, RAS1, RAS2, RAS3, CASO, and CAS1 go into a HIGH impedance
(floating) state.

ClK

System Clock-This input provides the master timing to generate refresh cycle timings and
refresh rate. Refresh rate is determined by the TWST, FS1, FSO inputs.

REFREQ

Refresh Request-(This input is driven by an open-collector output.) On input, a lOW-going edge
initiates a refresh cycle and will cause the internal refresh timer to be reset on the next falling
edge of the ClK. As an output, a lOW-going edge signals an internal refresh request and that
the refresh timer will be reset on the next lOW-going edge of ClK. REFREQ will remain lOW
until the refresh cycle is in progress and the current refresh address is present on MAO-MAS.
(Note: REFREQ contains an internal pull-up resistor with a nominal resistance of 10 kilohms.)

RASO,RAS146,47
RAS2,RAS339,40

Row Address Strobe-These three-state outputs are used to latch the row address into the bank
of DRAMs selected by REN1 and REN2. On refresh, all RAS signals are active.

CASO,CAS1 2,3S

Column Address Strobe-these three-state outputs are used to latch the column address into
the DRAM array.

ROY

Ready-This totem-pole output synchronizes memories that are too slow to guarantee
microprocessor access time requirements. This output is also used to inhibit access cycles
during refresh when in cycle-steal mode.

TWST

Timing/Wait Strap-A HIGH on this input indicates a wait state should be added to each
memory cycle. In addition it is used in conjunction with FSO and FS1 to determine refresh
rate and timing.

FSO,FS1

29,2S

Frequency Select 0; Frequency Select 1-These are strap inputs to select Mode and Frequency
of operation as shown in Table 1.

(PlCC
only)

RESET-Active lOW input to initialize the controller asynChronously. Refresh Address is set to
1FFH, internal refresh requests, synchronizer, and frequency divider are cleared. This input is
driven by an open collector driver.
RESET contains an internal pull-up with a nominal resistance of 100 K!l. This allows the pin to be
left open, if desired.

Note:
1. Pin numbers are for dual in-line package only.

193

VLSI TECHNOLOGY, INC.
VL4502

TABLE 1: STRAP CONFIGURATION
Strap Input Modes, Note 1
TWST

FS1

FSO

Memory
Access
Wait
States

L
L
L
L

L
L
H
H

L(3)
H
L
H

0
0
0
0

External
External
Clk-;.-61
Clk-;.-91

H
H
H
H

L
L
H
H

L
H
L
H

1
1
1
1

Clk-;.-61
Clk-;.-91
Clk-;.-106
Clk-;.-121

Refresh
Rate, Note 2

Refresh
Clock
Cycles

4
3

3
4
3

4
4
4

TABLE 2: OUTPUT STROBE SELECTION
Control

Input

REN2

REN1

RASO

Selected Output
RAS1

RAS2

RAS3

CASO

CAS1

X
X

Notes:
1. If the strap configuration is changed, the device should be reset in order to insure normal refresh operation.
2. The maximum refresh rate is a function of the applicable maximum clock frequency (see AC Characteristics).
3. This strap configuration resets the refresh timer circuitry.

FUNCTIONAL DESCRIPTION

ARBITER

Vl4502 consists of six basic blocks;
address and select latches, refresh
rate generator, refresh counter, the
multiplexer, the arbiter, and the timing and control block.

driving all three strap inputs lOW, or
by driving RESET lOW. During this
reset period, at least four clock cycles
should occur. (See RESET, below.)

ADDRESS AND SELECT
LATCHES

The refresh counter contains the address of the row to be refreshed. The
counter is decremented after each
refresh cycle. (A lOW-to-HIGH transition on TWST sets the refresh
counter to 1FF16 (51110).

The address and select latches allow
the DRAM controller to be used in
systems that multiplex address and
data on the same lines without externallatches. The row address latches
are transparent, meaning that while
ALE is HIGH, the output at MAO-MA8
follows the inputs RAO-RA8 ..

REFRESH RATE GENERATOR
The refresh rate generator is a
counter that indicates to the arbiter
that it is time for a refresh cycle. The
counter divides the clock frequency
according to the configuration straps
as shown in Table 1. The counter is
reset when a refresh cycle is requested or when TWST, FS1 and FSO
are lOW. The configuration straps allow the matching of memories to the
system access time. Upon Power-Up,
a reset may be accomplished by

REFRESH COUNTER

MULTIPLEXER
The multiplexer provides the DRAM
array with row, column, and refresh
addresses at the proper times. Its
inputs are the address latches and
the refresh counter. The outputs provide up to 18 multiplexed addresses
on nine lines.

STATIC OPERATION
The Vl4502 is designed for static operation. As a result, the user can use
a ClK frequency as low as needed,
as long as maximum transition times
are not exceeded. As the ClK rate is
changed, the refresh rate will change
accordingly, in keeping with the frequency-divider specifications above.

194

The arbiter provides two operational
cycles; access and refresh. The arbiter resolves conflicts between cycle
requests and cycles in execution, and
schedules the inhibited cycle when
used in cycle-steal mode.

TIMING AND CONTROL
BLOCK
The timing and control block executes
the operational cycle at the request
of the arbiter. It provides the DRAM
array with RAS and CAS signals. It
provides the CPU with a ROY signal.
It controls the multiplexer during all
cycles. It resets the refresh rate generator and decrements the refresh
counter during refresh cycles.

RESET
The Vl4502 is reset by bringing the
timing straps TWST, FS1, and FSO
lOW. The refresh address is set to
1FF, internal refresh requests are
synchronized, and the frequency
divider is cleared. This reset can
occur asynchronously with respect
to ClK and control signals. In the
PlCC package, the Vl4502 can
be reset with the RESET signal. In
either case, at least four clock cycles
should occur during the reset period.

VLSI TECHNOLOGY, INC.
VL4502

ABSOLUTE MAXIMUM RATINGS
Ambient Temperature
- 10°C to + 80°C
Under Bias
Storage Temperature
Range
- 65°C to + 140°C
Supply Voltage
Range, vee, Note 1 - 0.5 to + 7.0 V
Input Voltage Range
(any input), Note 1 - 0.5 to + 7.0 V
Continuous Power
Dissipation
1.2 W

DC CHARACTERISTICS:

Stresses above those listed under
"Absolute Maximum Ratings" may
cause permanent damage to the
device. These are stress ratings
only. Functional operation of this
device at these or any other

conditions above those indicated on
the operational sections of this
specification is not implied and
exposure to absolute maximum
rating conditions for extended
periods may affect device reliability.

= O°Cto +70°C, VCC = 5V ±10%
Typ(3)

Symbol

Parameter

Min

VIH

Input HIGH Voltage

2.4

VIL (except REFREQ)

Input LOW Voltage

VSS-0.5

O.S

VIL (REFREQ)

Input LOW Voltage

VSS-0.5

1.2

MAD-MASRDY

2.4

RASX,CASX

2.7

REFREQ

2.4

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

ilL

Input LOW Current

IOZ

Off-state Output Current

ICC(4)

Operating Supply Current DC

Max

Unit

Conditions

IOH

= -100 J.LA
= 4mA

-1 mA

VCC

= 4.5V

V
0.4

REFREQ

100

All Others

REFREQ,RESET
All others

V
J.LA

-1.25

-10

J.LA

IOL
VI

= 5.5V

= OV

±50

J.LA

Input Capacitance

Output Capacitance

= Ot04.5V

= O°C
VI = OV
VO = OV

VCC = 4.5V
vce = 4.5V

= 5.5V
= 5.5V
f = 1 MHz
f = 1 MHz

VCC

GRAPH 1
100

IC~ v~ c~oc~ FRIEQ~EN~Y
VS LOAD

CL = 360 pF CASO, CAS1, MAO-MAB
1BO pF RASO:-ifAS3

V
/v

ITOTAL

V
/

o
o

/
NO LOAD

ICLK(MHz)

Notes:
1. Voltage values are with respect to the ground terminal.
2. The algebraic convention, where the more negative limit is designated as minimum, is used in this data sheet for logic voltage levels only.
3. All typical values are at vce = 5 V. TA = 25°C except where otherwise noted.
4. Refer to Graph 1 for AC Power Consumption Guarantee. In testing, all inputs except CLK are held LOW.

195

VLSI TECHNOLOGY, INC.
VL4502

AC CHARACTERISTICS:

= ooe to +70oe, vee = 5 V ±

10%
VL4502-15

Symbol

Parameter

Min

tC(C)

ClK Cycle Time

100

VL4502-20
Max

Min

tW(CH)

ClK HIGH Pulse Width

tW(CL)

ClK lOW Pulse Width

Transition Time, All Inputs

tAEL-Cl

Time Delay, ALE lOW to
ClK Starting lOW, Note 1

tCl-AEl

Time Delay, ClK lOW to
ALE Starting lOW, Note 1

tCl-AEH

Time Delay, ClK lOW to
ALE Starting HIGH, Note 1

tW(AEH)

Pulse Width ALE HIGH
Time Delay, Address, REN1,2
CS Valid to ALE lOW

tAEl-AX

Time Delay, ALE lOW to
Address Not Valid

tAEl-ACl

Time Delay, ALE lOW to
ACX lOW, Notes 3, 4, 5, 6

tACH-Cl

Time Delay, ACX HIGH to
ClK lOW, Notes 3,7

tACl-CH

Time Delay, ACX lOW to
ClK Starting HIGH (to
remove ROY)

tRQl-Cl

Time Delay, REFREQ lOW
to ClK Starting lOW, Note 8

tW(RQl)

Input Pulse Width, REFREQ lOW

+ 30

Unit

tAV-AEl

th(RA)

Max

100

th(RA)

+ 40

Notes:
1. Coincidence of the trailing edge of ClK and the trailing edge of ALE should be avoided as the refresh/access occurs during the interval from
ACX HIGH to ALE lOW.
2. If ALE rises before ACX and a refresh request is present, the falling edge of ClK after tCl-AEH will output the refresh address to MAO-MA8
and initiate a refresh cycle.
3. These specifications relate to system timing and do not directly reflect device performance.
4. On the access grant cycle following refresh, the occurrence of CAS lOW depends on the relative occurrence of ALE lOW to ACX lOW.
If ACX occurs prior to or coincident with ALE then CAS is timed from the ClK HIGH transition that causes RAS lOW. If ACX occurs 20 ns or
more after ALE then CAS is timed from the ClK lOW transition following the ClK HIGH transition causing RAS lOW.
5. For maximum speed access (internal delays on both access and access grant cycles), ACX should occur prior to or coincident with ALE.
6. th(RA) is the dynamic memory row address hold time. ACX should follow ALE by tAEl-CEl in systems where the required th(RA) is greater
than tREl-MAX minimum.
7. Minimum of 20 ns is specified to ensure arbitration will occur on falling ClK edge. tACH-Cl also affects precharge time such that the
minimum tACH-Cl should be equal or greater than: tW(RH) - tW(Cl) + 30 ns (for cycle where ACX HIGH occurs prior to ALE HIGH) where
tW(RH) is the DRAM RAS precharge time.
8. This parameter is necessary only if refresh arbitration is to occur on this lOW-going ClK edge (in systems where refresh is synchronized to
external events).

196

VLSI TECHNOLOGY, INC.
VL4502

AC CHARACTERISTICS:

= O"Cto +70"C, VCC = 5V ±

10%
VL4502·20

VL4502·15
Min

Max

Min

Max

Symbol

Parameter

tAEl·REl

Time Delay, ALE lOW to RAS Starting lOW

tt(REl)

RASFallTime

tRAV-MAV

Time Delay, Row Address Valid to Memory
Address Valid

tAEH-MAV

Time Delay, ALE HIGH to Valid
Memory Address

tAEl-RYl

Time Delay, ALE to RDY Starting lOW
(TWST = 1 or Refresh in Progress)

tAEl-CEl

Time Delay, ALE lOW to CAS Starting lOW

tAEH-REH

Time Delay, ALE HIGH to RAS Starting HIGH

tt(MAV)

Address Transition Time

tACl-MAX

Row Address Hold from ACX lOW

tMAV-CEl

Time Delay, Memory Address Valid to CAS
Starting lOW

tt(CEl)

CAS Fall Time

tACl-CEl

Time Delay, ACX lOW to CAS Starting lOW

150

20
20

0
15
90

tACH-REH

Time Delay, ACX to RAS Starting HIGH

tt(REH)

RAS Rise Time

tACH-CEH

Time Delay, ACX HIGH to CAS Starting HIGH

tt(CEH)

CAS Rise Time

20
65

130
40
20

30
15

200
35

Column Address Hold from ACX HIGH

tCH-RYH

Time Delay, ClK HIGH to RDY Starting
HIGH (After ACX LOW), Note 9

tRFl-RFl

Time Delay, REFREO External Until
Supported by REFREO Internal

tCH-RFl

Time Delay, ClK HIGH Until REFREO
Internal Starting lOW

tCl-MAV

Time Delay, ClK lOW Until Refresh
Address Valid

100

tCH-RRl

Time Delay, ClK HIGH Until Refresh
RAS Starting lOW

tMAV-RRl

Time Delay, Refresh Address Valid
Until Refresh RAS lOW

tCl-RFH

Time Delay, ClK lOW to REFREO Starting
HIGH (3 Cycle Refresh)

tCH-RFH

Time Delay, ClK HIGH to REFREO Starting
HIGH (4 Cycle Refresh)

tCH-RRH

Time Delay, ClK HIGH to Refresh RAS
Starting HIGH

tCH-MAX

Time Delay, Refresh Address Hold
After ClK HIGH

5
15

tACH-MAX

Unit

Note:
9. RDY returns HIGH on the rising edge of ClK. If TWST = 0, then on an access grant cycle RDY goes HIGH on the same edge that causes
access RAS lOW. If TWST = 1, then RDY goes to the HIGH level on the first rising ClK edge after A~oes lOW on access cycles and on
the next rising edge after the edge that causes access RAS lOW on access grant cycles (assuming ACX lOW).

197

VLSI TECHNOLOGY, INC.
V·L4502

AC CHARACTERISTICS:

= one to + 70"e, vee = 5 V ±

10%
VL4502-15

Min

Symbol

Parameter

tCH-REl

Time Delay, ClK HIGH Until Access RAS
Starting lOW

tCl-CEl

Time Delay, ClK lOW to Access CAS
Starting lOW, Note 10 .

VL4502-20

Max

Min

Max

125

140

tCl-MAX

Row Address Hold After ClK lOW

tW(ACl)

ACX lOW Width

120

tREl-MAX

Row Address Hold From RAS lOW

tt(RYl)

ROY Fall Time

tt(RYH)

ROY Rise Time

tdis

Output Disable time (3-State Outputs)

tAEH-MAX

Column Address Hold From ALE HIGH

Unit

100

125
15

ten

Output Enable Time (3-State Outputs)

tCAV-CEl

Column Address Setup to CAS After
Refresh

tCH-CEl

Time Delay, ClK HIGH to Access
CAS Starting lOW, Note 9

140

t RESET

Power Up RESET

Four (4) Clock Cycles

0
180

Notes:
10. On the access grant cycle following refresh, the occurrence of CAS lOW depends on the relative occurrrence of ALE lOW to ACX lOW. If
ACX occurs prior to or coincident with ALE then CAS is timed from the ClK lOW transition that causes RAS lOW. If ACX occurs 20 ns or
more after ALE then CAS is timed from the ClK lOW transition following the ClK HIGH transition causing RAS lOW.

OUTPUT LOAD CONDITIONS:

vee

= 5.0 V

AC TESTING INPUT, OUTPUT WAVEFORM

VCC

3'00VV=X~~'4V
TEST POINTS

RASO·RAS3-__- - - -.......__-

ROY

_
880

720

r'80 PF

40PF
r

-=VCC

VCC

REFREQ
360pF
r

'020

40PF
r

MA~MA8--~----~~.--

720

r360PF

198

INPUT

0.8V
OUTPUT

AC TESTING INPUTS ARE DRIVEN AT 3.0 V FOR A LOGIC "'" AND 0.0 V
FOR A LOGIC "0". TIMING MEASUREMENTS ARE MADE AT 2.4 V FOR A
LOGIC "'" AND 0.8 V FOR A LOGIC "0" AT THE OUTPUTS.

VLSI TECHNOLOGY, INC
VL4502

TIMING DIAGRAMS
ACCESS CYCLE TIMING

REFRESH REQUEST TIMING

elK

iiEFifEQ
(EXTERNAL)

\~----

mREQ
(INTERNAL)

199

VLSI TECHNOLOGY, INC.

VL4502

TIMING DIAGRAMS (Cont.)
OUTPUT 3-STATE TIMING

1-.,,_u- _t_,":~
,

OUTPUTS

REFRESH CYCLE TIMING (3-CYCLE)

elK

ICL-RFH

-1---

---

MAo-MAe

I - -ICH-MAX

-1c:L-MAY

REFRESH ADDRESS

-ICH-RRL

K
1 - -1c:H-RRH

4----IMAV_ARL ~

1--

ICL-MAX f

ROW ADDRESS

----

-I-'CH-REL

-ICAY-CEL

I--1c:L-CELf -

1\
1c:H-CELf

REFRESH CYCLE TIMING (4-CYCLE)

ON THE ACCESS GRANT CYCLE FOllOWING REFRESH, THE OCCURRENCE OF CAS lOW
DEPENDS ON THE RELATIVE OCCURRENCE OF ALE lOW TO ACX lOW. IF ACX OCCURS
PRIOR TO OR COINCIDENT WITH ALE THEN CAS IS TIMED FROM THE ClK HIGH
TRANsmON THAT CAUSES RlS lOW. IF ACX OCCURS 20 NS OR MORE AFTER ALE THEN
~:N~\\~tl':,~ THE ClK lOW TRANsmON FOllOWING THE ClK HIGH TRANsmON

200

VLSI TECHNOLOGY, INC
VL4502

TIMING DIAGRAMS (Cont.)
TYPICAL ACCESS/REFRESH/ACCESS CYCLE (3-CYCLE, TWST
ACCESS

= 0)

REFRESH/ACCESS GRANT

ACCESS

TYPICAL ACCESS/REFRESH/ACCESS CYCLE (4-CYCLE, TWST = 0)
ACCESS

REFRESH/ACCESS GRANT

ClK

ALE

MAX

ROY

201

VLSI TECHNOLOGY, INC.
VL4502

TIMING DIAGRAMS (Cont.)
TYPICAL ACCESS/REFRESH/ACCESS CYCLE (3-CYCLE, TWST
ACCESS

= 1)
REFRESH/ACCESS GRANT

TYPICAL ACCESS/REFRESH/ACCESS CYCLE (4-CYCLE, TWST

= 1)
REFRESH/ACCESS GRANT

ClK

ALE

COLUMN

MAX

ROY

202

VLSI TECHNOLOGY, INC
VL4502

READY (ROY) SIGNAL TIMING (WAIT STATE OPERATION, TWST

elK

ALE

'CH.RYH

ROY

ROY starting HIGH is timed from elK HIGH (tCH-RYH)

203

VLSI TECHNOLOGY, INC

204

VLSI TECHNOLOGY, INC.
VL53C80
SMALL COMPUTER SYSTEM INTERFACE (SCSI)

FEATURES

DESCRIPTION

SCSI INTERFACE
• Interface to 1.5M bps (asynchronous)

The VLSI Technology VL53C80 SCSI
device is a 40-pin CMOS device
designed to accommodate the Small
Computer Systems Interface (SCSI)
as defined by the ANSI X3T9.2
committee. The VL53C80 operates as
both the initiator and the target and
can therefore be used in host adapter,
host port, and formatter designs. This
device supports arbitration, including
reselection. Special high-current opencollector output drivers, capable of
sinking 48 mA at 0.5 V, connect
directly to the SCSI bus.

• Supports initiator and target roles
• Parity generation with optional checking
• Arbitration support
• Direct control of all bus signals
• High current outputs drive SCSI bus
MPU INTERFACE
• Memory or liD mapped interface
• DMA of programmed liD

The device is controlled by reading and
writing several internal registers which
are addressed as standard or memory
mapped 1/0. DMA transfers require little
CPU support because the VL53C80
controls the necessary handshake
signals. The VL53C80 interrupts the
MPU when it detects a bus condition
requiring service. Normal and block
mode DMA is also available to match
several popular DMA controllers.
The VL53C80 is available in a 40-pin
plastic or ceramic DIP as well as a 44pin plastic leaded chip carrier.

The VL53C80 interfaces with the system microprocessor as a peripheral.

• Normal or block mode DMA
• Optional MPU interrupts

PIN DIAGRAM

BLOCK DIAGRAM
READY

ORO

VL53C80
00
-087
-086
-085
-084
-OB3
-OB2
-OB1
-OBO
-OBP
GNO

-SEL

02
03
04
05
06
07
A2
A1
VOO

AO
-lOW

-8SY

-RESET

-ACK

-MSG

-EOP
-OACK
REAOY
-lOR
IRO
ORO

-REO

-CS

-ATN
-RST
-1/0
-C/O

-A N

-CID

-RST

-ACK

-ItO

-REa

-MSG
SCSI BUS INTERFACE

ORDER INFORMATION
Part
Number

Package

VL53C80-PC
VL53C80-CC
VL53C80-QC

Plastic DIP
Ceramic DIP
Plastic Leaded Chip Carrier (PLCC)

Note: Operating temperature range is O°C to +70°C.

205

-DBP

DBO-DB7

VLSI TECHNOLOGY, INC
VL53C80

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Type

Signal
Description

00-07

1,40-34

,1/0*

Three-state microprocessor data bus lines. Active high when an output.

AO-A2

30,32,33

These signals are used with -CS, -lOR, or -lOW to address the internal
registers.

-RESET

I-

Reset - Clears all registers. It does not force the SCSI signal-RST to the
active state. -RESET is active low.

-EOP

I-

End Of Process - Used to terminate a DMA transfer. If asserted during a
DMA cycle, the current byte will be transferred but no additional bytes will
be requested.

-lOR

I/O Read - Used to read an internal register selected by -CS and AO-A2. It
also selects the Input Data Register when used with -DACK. -lOR is
active low.

-lOW

I/O Write - Used to write an internal register selected by CS and AO-A2.
When used with -DACK it selects the Output Data Register. -lOW is
active low.

-CS

I-

Chip Select - An active low signal that enables a read or write of the
internal register selected by address lines AO-A2.

-DACK

DMA Acknowledge - This active low signal resets ORO and selects the
data register for input or output of data transfers.

IRO

Interrupt Request - Informs the microprocessor of an error condition or an
event completion.

ORO

DMA Request - Indicates that the data register is ready to be read or
written. ORO occurs only if DMA mode is true in the Command Register.
It is cleared by -DACK.

READY

Ready - Can be used to control the speed of block mode DMA transfers. It
goes active to indicate the chip is ready to sendlreceive data and remains
false after a transfer until the last byte is sent or until the DMA Mode bit is
reset.

VDD

+5V.

GND

Ground.

-All pins interface directely with the microprocessor.

206

VLSI TECHNOLOGY, INC.
VL53C80

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Type

Signal
Description

-ACK

110·

Acknowledge - Driven by an initiator, -ACK shows an acknowledgment for
a REO/ACK data transfer handshake. In the target role, -ACK is received
as a response to the -REO signal.

-ATN

I/O·

Attention - Driven by an initiator, -ATN indicates an attention condition.
This signal is received in the target role.

-BSY

110·

Busy - Indicates that the SCSI bus is being used and can be driven by both
the initiator and the target device.

-C/O

110·

Control or Data - Driven by the target, -C/O indicates Control or Data
information is on the data bus. It is received by the initiator.

-DBO--DB7,
-DBP

9-2,10

110·

Data Bus - These eight data bits (-DBO- -DB7), plus a parity bit (-DBP)
form the data bus. -DB7 is the most significant bit and has the highest
priority during the Arbitration phase. Data parity is odd. Parity is always
generated and optionally checked. Parity is not valid during arbitration.

-110

110·

Input/Output - Driven by a target which controls the direction of data
movement on the SCSI bus. True (low) indicates input to the initiator. It is
also used to distinguish between Selection and Reselection phases.

-MSG

110·

Message - Received by the initiator, and driven by the target during the
Message phase.

-REO

110·

Request - Driven by a target, -REO indicates a request for a REO/ACK
data transfer handshake. It is received by the initiator.

-RST

110·

Reset - Indicates an SCSI bus reset condition.

-SEL

I/O·

Select - Used by an initiator to select a target or by a target to reselect an
initiator.

"Bidirectional, active low, open collector signals with 48 mA sink capability. All pins interface directly with the SCSI bus.

207

VLSI TECHNOLOGY, INC
VL53C80

FUNCTIONAL DESCRIPTION

TABLE 1. REGISTER SUMMARY

The VL53C80 Small Computer Systems
Interface (SCSI) device is seen as a set
eight registers to the controlling MPU.
By reading and writing the correct
registers, the MPU may start any SCSI
Bus function or may sample and assert
any signal on the SCSI Bus. This
permits the user to use all or portions of
the SCSI protocol in software. These
. registers are read (written) by activating
-CS with an address on AO-A2, and
then issuing an -lOR (-lOW) pulse.
The following section will describe the
operation of the internal registers.

Address

SCSI signal names are used to define
" the contents of the internal registers.
Even though the bus is active low, a
one (1) is used to indicate signal
assertion and a zero (0) is used to
indicate the inactive state. Se'e Table 1.
DATA REGISTERS
The data registers are used for the
transfer of SCSI commands, data,
status, and message bytes between the
microprocessor Data Bus and the SCSI
Bus. The VL53C80 does not hanqle
any information that passes through the
data registers. The data registers
consist of the transparent Current SCSI
Data Register, the Output Data Register, and the Input D.ata Register.
Current SCSI Data Register
Address 0 (Read Only) - The Current
SCSI Data Register is a read only
register which permits the microprocessor to read the active SCSI Data Bus.
This is done by activating -CS with an
address on A2-AO of 000, and issuing
an -lOR pulse. If parity checking is
enabled, the SCSI Bus parity is
checked at the beginning of the read
cycle. This register is active during a
programmed 110 data read, or during
Arbitration to inspect for higher priority
arbitrating devices, Parity is not
assured valid during Arbitration.
7

432

-OB7 -OB6 -OB5 -084 -OB3 -OB2 -OB1 -OBO

Output Data Register
Address 0 (Write Only) - The Output
Data Register is a write only register
that is used to send data to the SCSI
Bus. This done by either using a

RIW

Current SCSI Data

Output Data

RNI

Initiator Command

RNI

Mode

RNI

Target Command

Current SCSI Bus Status

Select Enable

Bus and Status

Start DMA Send

Input Data

Start DMA Target Receive

Reset Parity/Interrupts

Start DMA Initiator Receive

normal MPU write, or under DMA
control, by using -lOW and -DACK.
This register is further used to assert
the correct ID bits on the SCSI Bus
during the Arbitration and Selection
phases.
7

-OB7 -OB6 -OB5 -OB4 -OB3 -OB2 -OB1 -OBO

Input Data Register
Address 6 (Read Only) - The Input Data
Register is a read only register that is
used to read latched data from the
SCSI Bus. Data is latched either during
a DMA Target receive operation as
-ACK goes active, or during a DMA
Initiator receive when -REO goes
active. The DMA Mode bit (port 2, bit
1) is to be set before data can be
latched in the Input Data Register. This
register may be read under DMA control
using -lOR and -DACK. Parity may be
checked when the Input Data Register
is loaded, if desired.
7

Initiator Command Register
Address 1 (ReadlWrite) - The Initiator
Command Register is a read/write
register that is used to assert some
SCSI Bus signals, to monitor those
signals, and to monitor the progress of
bus arbitration. Many of these bits are
significant only when being used as an
Initiator. However, most can be used
during Target role operation. Values for
the Read and Write registers are shown
below, respectively.
7

ASRT AlP
-RST

ASRT ASRT ASRT ASRT ASRT
-ACK -BSY -SEL -ATN DATA
BUS

543

ASRT TEST DIFF ASRT ASRT ASRT ASRT ASRT
-RST MODE ENBL -ACK -BSY -SEL -ATN DATA
BUS

The following is a description of the
operation of all bits in the Initiator
Command Register.

-OB7 -OB6 -OB5 -084 -DB3 -DB2 -OB1 -OBO

208

Bit 7 - Assert -RST - Whenever a one
(1) is written to bit 7 of the Initiator
Command Register, the -RST signal is

VLSI TECHNOLOGY, INC.
VL53C80

asserted on the SCSI Bus. The -RST
signal stays asserted until this bit is
reset or an external-RESET occurs.
After this bit is set (1), IRQ goes active.
Then, all internal logic and control
registers are reset (except for the
interrupt latch and the Assert -RST bit).
Writing a zero (0) to bit 7 of the Initiator
Command Register releases the -RST
signal. Reading this register shows the
status of this bit.
Bit 6 - AlP (Arbitration in Progress)
(Read Bit) - This bit is used to determine if arbitration is in progress. For
this bit to be active, the Arbitrate bit
(port 2, bit 0) must have been previously set. It indicates that a "bus free"
condition has been detected, that the
chip has asserted -BSY, and the
contents of the Output Data Register
(port 0) onto the SCSI Bus. AlP will
remain active until the Arbitrate bit is
reset.
Bit 6 - Test Mode (Write Bit) - This bit
may be written during a test environment to disable all output drivers,
thereby removing the VL53C80 from
the circuit. Resetting this bit returns the
device to normal operation.
Bit 5 - LA (Lost Arbitration) (Read Bit) This bit, when active, indicates that t~e
VL53C80 has found a bus free condition, arbitrated for use of the bus by asserting -BSY and its ID on the Data
Bus and lost Arbitration due to -SEL
bein'g asserted by another bus device.
For this bit to be active, the Arbitrate bit
(port 2, bit 0) must be active.
Bit 5 - DIFF ENBL (Differential Enable)
(Write Bit) - This bit must be written with
a zero (0) for proper operation.
Bit 4 - Assert -ACK - This bit is used by
the bus initiator to assert -ACK on the
SCSI Bus. To assert -ACK, the Target
Mode bit (port 2, bit 6) must be false.
Writing a zero (0) to this bit resets
-ACK on the SCSI Bus. Reading this
register simply reflects the status of this
bit.
Bit 3 - Assert -BSY - Writing a one (1)
into this bit position asserts -BSY onto
the SCSI Bus. Conversely, a zero (0)
resets the -BSY signal. Asserting
-BSY indicates a successful selection
or reselection and resetting this bit
creates a bus disconnect condition.

Reading this ~egister simply reflects the
status of this bit.
Bit 2 - Assert -SEL - Writing a one (1)
into this bit position asserts -SEL onto
the SCSI Bus. -SEL is normally
asserted after Arbitration has been
correctly completed. -SEL may be
released by resetting this bit to a zero
(0). A read of this register shows the
status of this bit.
Bit 1 - Assert -ATN - -ATN may be
asserted on the SCSI Bus by setting
this bit to a one (1) if the Target Mode
bit (port 2, bit 6) is false. -ATN is
normally asserted, by the initiator, to
request a Message Out bus phase.
Note that since Assert -SEL and Assert
-ATN are in the same register, a select
with -ATN may be implemented with
one MPU write. -ATN may not be
asserted by resetting this bit to zero (0).
A read of this register simply reflects the
status of this bit.
Bit 0 - Assert Data Bus - The Assert
Data Bus bit, when set, allows the
contents of the Output Data Register to
be enabled as chip outputs on the
signals -DBO through -DB7. Parity is
generated and asserted on -DBP also.
Connected as an Initiator, the outputs
are only enabled if the Target Mode bit
(port 2, bit 6) is false, the received
signal-I/O is false, and the phase
signals (-C/D, -110, and -MSG) match
the contents of the Assert -C/D, Assert
-I/O, and Assert -MSG in the Target
Command Register.
This bit should also be set during DMA
send operations.
Mode Register Address 2 (Readl
Write)
The Mode Register is used to control
the operation of the chip. This register
decides whether the VL53C80 operates
as an Initiator or a Target, whether DMA
transfers are being used, whether parity
is checked, and whether interrupts ~re
generated on various external conditions. This register may be read to
inspect the value of these internal
control bits. The operation of these
control bits are shown below.
.
7

320

I
BlK TAR- EN
EN
EN MONI- DMA ARB
MODE GET PAR PAR EOP TOR MOOE
DMA MOOECHKG INT INT BSY

209

Bit 7 - Block Mode DMA - The Block
Mode DMA bit controls the characteristics of the DMA DRQ/-DACK handshake. When this bit is reset (0), and
the DMA Mode bit is active (1), the
DMA handshake uses the normal
interlocked handshake. The rising edge
of -DACK shows the end of each byte
being transferred. In block mo~e
operations, Block Mode DMA bit set (1)
and DMA Mode bit set (1), the end of
-lOR or -lOW signifies the end of each
byte transferred and -DACK is allowed
to remain active throughout the DMA
operation. READY can then be used to
request the next transfer.
Bit 6 - Target Mode - The Target Mode
bit allows the VL53C80 to operate as
either an SCSI Bus Initiator, bit reset
(0), or as an SCSI bus Target device,
bit set (1). In order for the signals -A TN
and -ACK to be asserted on the SCSI
Bus, the Target Mode bit must be reset
(0). In order for the signals -DC, -I/O,
-MSG, and -REQ to be asserted on the
SCSI Bus, the Target Mode bit should
be set (1).
Bit 5 - Enable Parity Checking - The
Enable Parity Checking bit decides
whether parity errors will be ignore~ or.
saved in the parity error latch. If thiS bit
is reset (0), parity will be ignored; if this
bit is set (1), parity errors will be saved.
Bit 4 - Enable Parity Interrupt - The
Enable Parity Interrupt bit, when set (1).
will cause an interrupt (IRQ) to occur if
a parity error is detected. A par.ity
interrupt will only be generated If the
Enable Parity Checking bit (bit 5) is also
enabled (1).
Bit 3 - Enable EOP Interrupt - The
Enable EOP Interrupt, when set (1),
causes an interrupt to occur when an
-EOP (End of Process) signal is
.
received from the DMA controller logiC.
Bit 2 - Monitor Busy - The Monitor Busy
bit, when true (1) causes an interrupt to
be generated for an unplanned loss of
-BSY. When the interrupt is generated
due to loss of -BSY, the lower six bits
of the Initiator Command Register are
reset (0) and all signals are removed
from the SCSI Bus.
Bit 1 - DMA Mode - The DMA Mode bit
is normally used to enable a DMA
transfer and must be set (1) prior to

VLSI TECHNOLOGY, INC.
VL53C80

writing ports 5 through 7. Ports 5
through 7 are used to initiate DMA
transfers. The Target Mode bit (port 2,
bit 6) must be consistent with writes to
port 6 and 7 (Le., set (1) for a write to
port 6 and reset (0) for a write to port 7).
The control bit Assert Data Bus (port 1,
bit 0) must be true (1) for all DMA send
operations. In the DMA mode, -REO
and -ACK are controlled automatically.
The DMA Mode bit is not reset when
the receipt of an -EOP signal occurs.
Any DMA transfer may be stopped by
writing a zero (0) into this bit. Care must
be taken not to cause -CS and -DACK
to become active simultaneously.
-BSY must be active to set the DMA
Mode bit.
Bit 0 - Arbitrate - The Arbitrate bit is set
(1) to start the Arbitration process. Prior
to setting this bit, the Output Data
Register should contain the proper
SCSI device 10 value. Only one data
bit should be active for SCSI Bus
arbitration. The VL53C80 will wait for a
bus free condition befor~ entering the
arbitration phase. The results of the
arbitration phase are determined by
reading the status bits LA and AlP (port
1, bits 5 and 6, respectively).
Target Command Register
Address 3 (ReadlWrite) - When
connected as a target device, the
Target Command Register allows the
MPU to control the SCSI Bus Information Transfer phase and also to assert
-REO simply by writing this register.
The Target Mode bit (port 2, bit 6) must
be true (1) for bus assertion to occur.
The SCSI Bus phases are described in
Table 2 •.

TABLE 2. SCSI INFORMATION TRANSFER PHASES
Assert
-I/O

Bus Phase

765

320

Unspecified

Command

Message Out

Data In

Unspecified

Status

Message In

The VL53C80 uses bit 7 of this register
to determine when the last byte of DMA
transfer is sent to the SCSI Bus. This
flag is needed since the End of DMA bit
in the Bus and Status Register only
display when the last byte was received
from the DMA.
Current SCSI Bus Status Register
Address 4 (Read Only) - The Current
SCSI Bus Status Register is a read only.
register which is used to monitor seven
SCSI Bus control signals plus the Data
Bus parity bit. An Initiator device can
use this register to determine the
current bus phase and poll -REO for
pending data transfers. This register
may also be used to determine why a
certain interrupt occurred. Values for
the Current SCSI Bus Status Register
are shown below.
654

-eto

-VO -SEl -DBP

Select Enable Register
Address 4 (Write Only) - The Select
Enable Register is a write only register
which is used as a mask to monitor a
signal 10 during a selection attempt.
The simultaneous occurrence of the
correct 10 bit, -BSY false, and -SEL
true will cause an interrupt. This
interrupt can be disabled by resetting all
bits in this register. If the Enable Parity
Checking bit (port 2, bit 5) is active (1),
parity will be examined during selection.
7

543

I
ASRT ASRT ASRT ASRT
-REO -MSG -eto

-vo

Assert
-MSG

Data Out

-RST -BSY -REO -MSG

When connected as an Initiator with
DMA Mode true and if the phase lines
(-110, -C/O, and -MSG) do not match
the phase bits in the Target Command
Register, a phase mismatch interrupt is
caused when -REO goes active. In
order to send data as an Initiator, the
Assert -I/O, Assert -C/O, and Assert
-MSG bits must match the corresponding bits in the Current SCSI Bus Status
Register (port 4). The Assert -REO bit
(bit 3) has no meaning when operating
as an Initiator.

Assert

-c/o

-DB7 -DBS -OB5 -DB4 -OB3 -DB2 -DBl -DBO

210

Bus and Status Register
Address 5 (Read Only) - The Bus and
Status Register is a read only register
which may be used to monitor the remaining SCSI control signals not found
in the Current SCSI Bus Status Register
(-ATN and -ACK), and six other status
bits. Below is a description of each bit
of the Bus and Status Register.
5

END OMA PAR INT
0
BSY -ATN -ACK
OF ROST ERR ROST MCH ERR
OMA
ACT

Bit 7 - End of DMA Transfer - The End
of DMA Transfer bit is set if -EOP,
-DACK, and either -lOR or -lOW are
both active for at least 100 ns. Since
the -EOP signal can occur during the
last byte sent to the Output Data
Register (port 0), the -REO and -ACK
signals must be monitored to insure that
the last byte has been transferred. This
bit is reset when the DMA Mode bit is
reset (0) in the Mode Regi~ter (port 2).
Bit 6 - DMA Request - The DMA
Request bit permits the MPU to sample
the output pin ORO. ORO can be
cleared by asserting -DACK or by
resetting the DMA Mode bit (bit 1) in the
Mode Register (port 2). The ORO
signal does not reset when a phase
mismatch interrupt occurs.
Bit 5 - Parity Error - This bit is set if a
parity error occurs during a data receive
or a device selection. The Parity Error
bit can only be set (1) if the Enable

VLSI TECHNOLOGY, INC.
VL53C80

Parity Check bit (port 2, bit 5) is active
(1). This bit may be cleared by reading
the Reset Paritylfnterrupt Register (port

7).
Bit 4 - Interrupt Request Active - This bit
is set if an enabled interrupt condition
occurs. It reflects the current state of
the IRQ output and can be cleared by
reading the Reset Parity/Interrupt
Register (port 7).
Bit 3 - Phase Match - The SCSI signals,
-MSG, -C/O, and -I/O, represent the
current information transfer phase. The
Phase Match bit indicates whether the
current SCSI Bus phase matches the
lower three bits of the Target Command
Register. Phase Match is continuously
updated and is only significant when
operating as a bus initiator. A phase
match is required for data transfers to
occur on the SCSI Bus.
Bit 2 - Busy Error - The Busy Error bit is
active if an unexpected loss of the
-BSY signal has occurred. This latch is
set whenever the Monitor Busy bit (port
2, bit 2) is true and -BSY is false. An
unexpected loss of -BSY will disable
any SCSI outputs and will reset the
DMA Mode bit (port 2, bit 1).
Bit 1 - ATN - This bit reflects the
condition of the SCSI Bus control signal
-ATN. This signal is normally monitored by the Target device.
Bit 0 - ACK - This bit reflects the
condition of the SCSI Bus control signal
-ACK. This signal is normally monitored by the Target device.
DMA REGISTERS
Three write only registers are used to
initiate all DMA activity. They are Start
DMA Send (port 5), Start DMA Target
Receive (port 6) and Start DMA Initiator
Receive (port 7). Simply writing these
registers starts the DMA transfers.
Data presented to the VL53C80 on
signals DO through 07 during the
register write is meaningless and has
no effect on the operation. Prior to
writing these registers, the Block Mode
DMA bit (bit 7), the DMA Mode bit (bit 1)
and the Target Mode Bit (bit 6) in the
Mode Register (port 2) must be
appropriately set. The individual
registers are briefly described as
follows.

Start DMA Send
Address 5 (Write Only) - This register is
written to initiate a DMA send, from the
DMA to the SCSI Bus, for either initiator
or target role operations. The DMA
Mode bit (port 2, bit 1) must be set prior
to writing this register.
Start DMA Target Receive
Address 6 (Write Only) - This register is
written to initiate a DMA receive, from
the SCSI Bus to the DMA, for Target
operation only. The DMA Mode bit (bit
1) and the Target Mode bit (bit 6) in the
Mode Register (port 2) must both be set
(1) prior to writing this register.
Start DMA Initiator Receive
Address 7 (Write Only) - This register is
written to initiate a DMA receive, from
the SCSI Bus to the DMA, for initiator
operation only. The DMA Mode bit (bit
6) must be false (0) in the Mode
Register (port 2) prior to writing this
register.
Reset Parltyllnterrupt
Address 7 (Read Only) - Reading this
register resets the Parity Error bit (bit 5),
the Interrupt Request bit (bit 4), and the
Busy Error bit (bit 2) in the Bus and
Status Register (port 5).
ON-CHIP SCSI HARDWARE supPORT
The device allows direct control and
monitoring of the SCSI Bus by providing
a latch for each signal. Portions of the
protocol define timings which are much
too quick for traditional microprocessors
to control. Therefore, hardware support
has been provided for DMA transfers,
bus arbitration, phase change monitoring, bus disconnection, bus reset, parity
generation, parity checking, and device
selection/reselection.
Arbitration is performed using a bus free
filter to continuously inspect -BSY. If
-BSY stays inactive for at least 400 ns,
then the SCSI Bus is free, and arbitration may begin. Arbitration starts if the
bus is free, -SEL is inactive, and the
Arbitration bit (port 2, bit 0) is active.
Once arbitration has started (-BSY asserted), an arbitration delay of 2.2 Ils
should elapse before the Data Bus can
be examined to determine if arbitration
has been won. This delay is implemented in the control software driver.

211

The VL53C80 is a clockwise device.
Delays such as bus free delay, bus set
delay, and bus-settle delay are implemented using gate delays. These
delays may differ between devices
because of inherent process variations,
but are well,within the proposed ANSI
X3T9.2 specification (Revision 17).
INTERRUPTS
The VL53C80 provides an interrupt
output (IRQ) to display a task completion or an unusual bus event. The use
of interrupts is optional. They may be
disabled by resetting the assigned bits
in the Mode Register (port 2) or the
Select Enable Register (port 4).
When an interrupt occurs, the Bus and
Status Register and the Current SCSI
Bus Status Register should be read to
determine which condition caused the
interrupt. IRQ can be reset simply by
reading the Reset Paritylfnterrupt
Register (port 7) or by an external chip
reset (-RESET active for 200 ns).
When the VL53C80 has been correctly
initialized, an interrupt will be generated
if the chip is selected or reselected, if an
-EOP signal occurs during a DMA
transfer, if an SCSI Bus reset occurs, if
a parity error occurs during a data
transfer, if a bus phase mismatch
occurs, or nan SCSI Bus disconnection
takes place.
Selectlon/Reselectlon
The VL53C80 can generate a select
interrupt if -SEL is true (1), its device 10
is true (1), and -BSY is false for at least
one bus-settle delay (400 ns). If -I/O is
active, this should be considered a
reselect interrupt. The correct 10 bit is
determined by a match in the Select
Enable Register (port 4). Only a single
bit match is necessary to generate an
interrupt. This interrupt may be
disabled by writing zeros (O's) into all
bits of the Select Enable Register.

If parity is supported, parity should also
be good during the selection phase.
Therefore, if the Enable Parity bit (port
2, bit 5) is active then the Parity Error bit
should be checked to ensure that a
proper selection has occurred. The
Enable Parity Interrupt bit need not be
set for this interrupt to be generated.

VLSI TECHNOLOGY, INC.
VL53C80

The proposed SCSI specification also
requires that no more than two device
IDs be active during the selection
processor. To ensure this, the Current
SCSI Data Register (port 0) should be
read.

and the new data appears in the Input
Data Register. Since a phase mismatch interrupt will not occur, -REO
and -ACK must be sampled to determine that the Target is attempting to
send more data.

Values for the Bus and Status Register
(port 5) and the Current SCSI Bus
Status Register (port 4) are displayed
below, respectively.

For send operations, the End Of DMA
bit is set when the DMA completes its
transfer, but the SCSI transfer may still
be in progress. If connected as a
Target, -REO and -ACK should be
sampled until both are false. If connected as an Initiator, a phase change
interrupt can be used to signal the
completion of the previous phase. It is
possible for the Target to request more
data for the same phase. Then, a
phase change will not occur and both
-REO and -ACK must be sampled to
determine when the last byte was
transferred.

101010111xlolxlo
END DMA PAR INT
0
BSY -ATN -ACK
OF ROST ERR ROST MCH ERR
DMA
ACT

o ololxlxlx
-RST -BSY -REO -MSG -CID

-va

1 xl
-5EL -DBP

End of Process (EOP) Interrupt
An End of Process signal (-EOP) which
occurs during a DMA transfer (DMA
Mode true) will set the End Of DMA
Status bit (port 5, bit 7) and may
generate an interrupt if Enable EOP
Interrupt bit (port 2, bit 3) is true. The
-EOP pulse will not be recognized (End
of DMA bit set) unless -EOP, -DACK,
and either -lOR or -lOW are simultaneously active for at least 100 ns. DMA
transfers can still occur if -EOP was
asserted at the correct time. This
interrupt can be disabled by resetting
the Enable EOP Interrupt bit.
Values for the Bus and Status Register
(port 5) and the Current SCSI Bus
Status Register (port 4) for this interrupt
are shown below, respectively.
765

END DMA PAR INT
0
BSY -ATN -ACK
OF ROST ERR ROST MCH ERR
DMA
ACT

-va

lolxlol11xlolxlx
END DMA PAR INT
0
BSY -ATN -ACK
OF ROST ERR ROST MCH ERR
DMA
ACT

xlxlxlxlolxl

-RST -BSY -REO -MSG -ctD

Values for the Bus and Status Register
(port 5) and the Current SCSI Bus
Status Register (port 4) are displayed
below, respectively.
7

11101011101010

1011

SCSI Bus Reset
The VL53C80 generates an interrupt
when the -RST signal changes to true.
The device releases all bus signals
within a bus clear delay (800 ns) of this
transition. This interrupt also occurs
after setting the Assert -RST bit (port 1,
bit 7). This interrupt cannot be disabled. (Note: -RST is not latched in bit
7 of the Current SCSI Bus Status
Register and may not be active when
this port is read. For this case, the Bus
Reset interrupt may be determined by
default.)

1x I x I x I x I x I x I x I X

-5EL -DBP

-RST -BSY -REO-MSG -ctD -1/0 -5EL -DBP

The End Of DMA bit is used to determine when a block transfer is complete.
Receive operations are complete when
there is no data left in the chip and no
additional handshakes occurring. The
only exception to this is receiving data
as an Initiator and the Target opts to
send additional data for the same
phase. In this case, -REO goes active

Parity Error
An interrupt is generated for a received
parity error if the Enable Parity Check
(bit 5) and the Enable Parity Interrupt
(bit 4) bits are set (1) in the Mode
Register (port 2). Parity is checked
while reading the Current SCSI Data
Register (port 0) and during a DMA
receive operation. A parity error can be

212

detected without generating an interrupt
by disabling the Enable Parity Interrupt
bit and checking the Parity Error flag
(port 5, bit 5).
Values for the Bus and Status Register
(port 5) and the Current SCSI Bus
Status Register (port 4) are displayed
below, respectively.
7

10lxl1111110lxlx
END DMA PAR INT
0
BSY -ATN -ACK
OF ROST ERR ROST MCH ERR
DMA
ACT

654

1011111xlxlxlolx
-RST -BSY -REO-MSG -CID

-va

-5EL -DBP

Bus Phase Mismatch
The SCSI phase lines contain the
signals -110, -C/D, and -MSG. These
signals are compared with the corresponding bits in the Target Command
Register: Assert -110 (bit 0), Assert -C/
D (bit 1), and Assert -MSG (bit 2). The
comparison continually occurs, and is
reflected in the Phase Match bit (bit 3)
of the Bus and Status Register (port 5).
An interrupt (IRO) is generated if the
DMA Mode bit (port 2, bit 1) is active
and a phase mismatch occurs when
-REO transitions from false to true.
A phase mismatch prevents the
recognition of -REO and also removes
the chip from the bus during an Initiator
send operation. -DBO through -DB7,
and -DBP will not be driven even
though the Assert Data Bus bit (port 1,
bit 0) is active. This interrupt is only
active when connected as an Initiator
and may be disabled by resetting the
DMA Mode bit. (Note: It is possible for
this interrupt to occur when connected
as a Target if another device is driving
the phase lines to a different state.)
Values for the Bus and Status Register
(port 5) and the Current SCSI Bus
Status Register (port 4) are displayed
below, respectively.
7

654

321

10lolol11ololxlo
END DMA PAR INT
0
BSY -ATN -ACK
OF ROST ERR ROST MCH ERR
DMA
ACT

lol11xlxlxlxlolx
-RST -BSY -flEO -MSG -ctD

-va

-5EL -OBP

VLSI TECHNOLOGY, INC.
VL53C80

Loss of -BSY
When the Monitor Busy bit (bit 2) in the
Mode Register (port 2) is active, an
interrupt will be generated if the -BSY
signal goes false for at least one bussettle delay (400 ns). This interrupt
may be disabled by resetting the
Monitor Busy bit. Values are displayed
below for the Bus and Status Register
and Current SCSI Bus Status Register,
respective Iy.
7

I I I I IxI I I
0

END DMA PAR INT
0
BSY -ATN -ACK
OF RQST ERR RQST MCH ERR
DMA
ACT

lolololxlxlxlolo
-RST -BSY -REQ-MSG

-c/O

-I/O -SEL -DBP

RESET CONDITIONS
There are three reset situations that
apply to the VL53C80:
Hardware Chip Reset
When the signal-RST is active for at
least 200 ns, the VL53C80 device is reinitialized and all internal logic and
control registers are cleared. This is
only a chip reset, and does not cause
and SCSI Bus reset condition.
SCSI Bus Reset (-RST) Received
When an SCSI-RST signal is detected,
an IRO interrupt is generated and a chip
reset occurs. All internal logic and
registers are cleared, except for the IRO
interrupt latch and the Assert -RST bit
(bit 7) in the Initiator Command Register
(port 1). (Note: The -RST signal may
be sampled by reading the Current
SCSI Bus Status Register (port 4). This
signal is not latched and may not be
present when this port is read.)
SCSI Bus Reset (-RST) Issued
If the MPU sets the Assert -RST bit (bit
7) in the Initiator Command Register
(port 1), the -RST signal goes active on
the SCSI Bus and an internal reset
occurs. All internal logic and registers
are cleared except for the IRO interrupt
latch and the Assert -RST bit (bit 7) in
the Initiator Command Register (port 1).
The -RST signal continues to be active
until the Assert -RST bit is reset or until
a hardware reset occurs.

DATA TRANSFERS
Data may be transferred between SCSI
Bus devices in one of four modes:
1) Programmed 1/0
2) Normal OMA
3) Block Mode OMA
4) Pseudo OMA.
The following sections describe these
modes in detail. (Note: For all data
transfer operations -DACK and -CS
can never b~ active at the same time).

Block Mode DMA
Popular DMA controllers such as the
9517A provide a Block Mode DMA
transfer. This type of transfer allows the
DMA controller to transfer blocks of
data without giving up the use of the
Data Bus to the MPU after each byte is
transferred. This way, faster transfer
rates are achieved by eliminating the repetitive access and release of the MPU
Bus.

Programmed 110 Transfers
Programmed 1/0 is the most basic form
of data transfer. The -REO and -ACK
handshake signals are individually
examined and asserted by reading and
writing the appropriate register bits.
This type of transfer is usually used
when transferring small blocks of data
(e.g. command blocks or message and
status bytes).

If the Block Mode DMA bit (port 2, bit 7)
is active, the VL53C80 begins the
transfer by asserting DRO. The DMA
controller then asserts -DACK for the
duration of the block transfer. ORO becomes inactive for the remainder of the
transfer. The READY output can be
used to control the transfer rate.

An initiator send operation will begin by
setting the -CIO, -1/0, and -MSG bits
in the Target Command Register to the
correct state so that a phase match
exists. In addition to the phase match
condition, it is necessary for the Assert
Data Bus bit (port 1, bit 0) to be true
and the received 1/0 signal to be false
for the VL53C80 to send data.
For every transfer, the data is loaded to
the Output Data Register (port 0). The
MPU then waits for the -REO bit (port
4, bit 5) to become active. Once -REO
goes active, the Phase Match bit (port
5, bit 3) is checked and the Assert
-ACK bit (port 1, bit 4) is set. The
-REO bit is sampled until it becomes
false and the MPU resets the Assert
-ACK bit to complete the transfer.
Normal DMA Mode
DMA transfers are usually used for
large block transfers. The SCSI chip
outputs a DMA request (DRO) whenever it is ready for a byte transfer.
External DMA logic uses this DRO
signal to generate -DACK and an -lOR
or an -lOW pulse to the VL53C80.
ORO becomes inactive when -DACK is
asserted and -DACK goes inactive
some time after the minimum read or
write pulse width. This process is
repeated for every byte. In this mode,
-DACK should not be allowed to cycle
unless a transfer is occuring.

213

Non-block mode DMA transfers
terminate when -OACK goes false,
whereas Block Mode transfers end
when -lOR or -lOW becomes inactive.
OMA transfers may be started sooner in
a Block Mode transfer.
To obtain the best performance in Block
Mode operation, the OMA logic should
use the normal DMA mode interlocking
handshake. READY is available to
throttle the DMA transfer, but DRO is 30
to 40 ns faster than READY, and may
be used to start the cycle sooner.
The methods described under "Halting
a DMA Operation" apply for all DMA
operations.
Pseudo DMA Mode
In order to avoid monitoring and
asserting the request/acknowledge
handshake signals for programmed 1/0
transfers, the system may be designed
to implement a pseudo DMA mode.
This mode initiated by programming the
VL53C80 to operating in the DMA
mode, by using the MPU to emulate the
DMA handshake. DRO may be
detected by polling the OMA Request
bit (bit 6) in the Bus and Status Register
(port 5), by sampling the signal through
an external port or by using it to cause a
MPU interrupt. Once ORO is detected,
the MPU can perform a read or write
data transfer. This MPU readlwrite is
externally decoded to generate the
correct -DACK and -lOR or -lOW
signals.

VLSI TECHNOLOGY, INC

Frequently, external decoding logic is
needed to generate the VL53C80 -CS
signal. This same logic may be used to
generate -DACK at no extra system
cost and provide an increased performance in programmed 110 transfers.

Halting a DMA Operation
The -EOP signal is one way to halt a
DMA transfer. A bus phase mismatch
or a reset of the DMA Mode bit (port 2,
bit 1) can also end a DMA cycle for the
current bus phase.
Using the -EOP Signal - If -EOP is
used, it should be asserted for at least
100 ns while -DACK and -lOR or -lOW
are both active. If either-lOR or -lOW
are not active, an interrupt will be generated, but the DMA activity will
continue. The -EOP signal does not
reset the DMA Mode bit. The -EOP
signal can occur during the last byte
sent to the Output Data Register (port
0). The -REO and -ACK signals should
be monitored to ensure that the last
byte has transferred.

VL53C80
Bus Phase Mismatch Interrupt - A bus
phase mismatch interrupt may be used
to halt the transfer if operating as an
Initiator. Using this method frees the
host from maintaining a data length
counter and frees the DMA logic from
providing the -EOP signal. If performing an Initiator send operation, the
VL53C80 requires -DACK to cycle
before -ACK goes inactive. Since
phase changes cannot occur if -ACK is
active, either -DACK must be cycled
after the last byte is sent or the DMA
Mode bit must be reset in order to
receive the phase mismatch interrupt.
Resetting the DMA Mode Bit - A DMA
operation may be stopped at any time
simply by resetting the DMA Mode bit.
It is recommended that the DMA Mode
bit be reset after receiving an -EOP or
bus phase mismatch interrupt. The
DMA Mode bit must then be set before
writing any of the start DMA register for
later bus phases.

214

If resetting the DMA Mode bit is used
instead of -EOP for Target role
operation, then care must be exercised
to reset this bit at the proper time.
When receiving data as a Target
device, the DMA Mode bit must be reset
once the last DRO is received and
before -DACK is asserted to prevent an
additional -REO from taking place. Resetting this bit causes DRO to go
inactive. The last byte received
remains in the Input Data Register and
may be obtained either by performing a
normal MPU read or by cycling -DACK
or -lOR. Frequently, -EOP is easier to
use when operating as a Target device.

VLSI TECHNOLOGY, INC
VL53C80

SWITCHING TEST CIRCUIT

'--------VT

50 pF

S~ITCHING

TEST WAVEFORM

2.4

0.4

<:":x_

x:":>

215

VLSI TECHNOLOGY, INC.
VL53C80

SWITCHING CHARACTERISTICS/WAVEFORMS
CPU WRITE
Min

Max

Units

Condition

Symbol

Description

Address Setup to Write Enable

Write Enable Occurs When -lOW and -CS

Address Hold from End Write Enable

Write Enable Occurs When -lOW and -CS

Write Enable Width

Write Enable Occurs When -lOW and -CS

Chip Select Hold from End of -lOW

Data Setup to End of Write Enable

Data Hold Time from End of -lOW

Write Enable Occurs When -lOW and -CS

AO-A2~______________________________________________________________________
---------

~t11~.------t2-----~~

-CS
~------------t3------------~~---

-lOW

.*14__-----t6----~~~

__ ~~~----------t5----------__

____

DO-D7....-------------..~

CPU READ
Symbol

Description

Address Setup to Read Enable

Read Enable Occurs When -lOR and -CS

Address Hold from End Read Enable

Read Enable Occurs When -lOR and -CS

Chip Select Hold from End of -lOR

Data Access Time from Read Enable

Data Hold Time from End of -lOR

Min

Max

130

Units

Condition

Read Enable Occurs When -lOR and -CS

AO-A2~_________________________________________________________________~
---------

~ t1

1,....
.......- - -

-CS

-lOR

216

------PI

VLSI TECHNOLOGY, INC.
VL53C80

SWITCHING CHARACTERISTICS/WAVEFORMS (Cont.)
DMA WRITE (NON-BLOCK MODE) TARGET SEND
Min

Max

Units

Symbol

Description

DRO False from -DACK True

-DACK False to DRO True

Write Enable Width

100

DACK Hold from End of -lOW

Data Setup to End of Write Enable

Data Hold Time from End of -lOW

130

Write Enable Occurs When -lOW and -DACK

Width of -EOP Pulse (Note)

100

-ACK True to -REO False

125

-REO from End of -DACK
(-ACK False)

150

t10

-ACK True to DRO True (Target)

110

t11

-REO from End of -ACK
(-DACK False)

150

t12

Data Hold from Write Enable

Data Setup to -REO True (Target)

t13

Condition

Note: -EOP, -lOW, and -DACK must be concurrently true for at least t7 for proper recognition of the -EOP pulse.

DRO
-DACK

-lOW

DO - D7
-EOP

-REO
-ACK

-DBO --DB7,
BYTE N-1
-DBP
------------------------------

217

VLSI TECHNOWGY, INC
VL53C80

SWITCHING CHARACTERISTICS/WAVEFORMS (Cont.)
DMA WRITE (NON-BLOCK MODE) INITIATOR SEND
Symbol

Description

Min

Max

Units

130

DRO False from -DACK True

-DACK False to DRO True

Write Enable Width

100

-DACK Hold from End of -lOW

Data Setup to End of Write Enable

Data Hold Time from End of -lOW

Width of -EOP Pulse (Note)

100

-REO True to -ACK True

-REO False to DRO True

t10

-DACK False to -ACK False

t11

-lOW False to Valid SCSI Data

t12

Data Hold from Write Enable

160

110

150

100

Condition

Write Enable Occurs When -lOW and -DACK

Note: -EOP, -lOW, and -DACK must be concurrently true for at least t7 for proper recognition of the -EOP pulse.

DRO
-DACK

-lOW

DO - D7
-EOP
-REO
t9
-ACK

2~ ~~ ~~------------------------

________________________t1__
-DBO--DB7,
BYTEN-1
~
-DBP
-----------------------------------------------

218

BYTEN

VLSI TECHNOLOGY, INC
VL53C80

SWITCHING CHARACTERISTICS/WAVEFORMS (Cont.)
DMA READ (NON-BLOCK MODE) TARGET RECEIVE
Symbol

Description

ORO False from -DACK True

-DACK False to ORO True

-DACK Hold Time from End of -lOR

Data Access Time from Read Enable

Min

Max
130

Units

Condition

ns
ns

ns
115

Data Hold Time from End of -lOR

Width of -EOP Pulse (Note)

100

-ACK True to ORO True

110

-DACK False to -REO True
(-ACK False)

150

-ACK True to -REO False

125

t10

-ACK False to -REO True
(-DACK False)

150

Read Enable Occurs When -lOR and -DACK

ns
ns

t11

Data Setup Time to -ACK

t12

Data Hold Time from -ACK

Note: -EOP, -lOR, and -DACK must be concurrently true for at least t6 for proper recognition of the -EOP pulse.

ORO
-DACK

-lOR

DO - 07
-EOP
-REO
1 4 - - - - t10 ----t~ " ' - - - - - - - -

-ACK

-DBO - DB7,
-DBP

219

VLSI TECHNOLOGY, INC.
VL53C80

SWITCHING CHARACTERISTICS/WAVEFORMS (Cant.)
DMA READ (NON-BLOCK MODE) INITIATOR RECEIVE
Symbol

Description

ORO False from -OACK True

-OACK False to ORO True

Min

Max
130

-OACK Hold Time from End of -lOR

Data Access Time from Read Enable

Data Hold Time from End of -lOR

Units

ns
115

Read Enable Occurs When -lOR and -OACK

Width of -EOP Pulse (Note)

100

-REO True to ORO True

150

-OACK False to -ACK False
(-REO False)

160

-REO True to -ACK True

160

t10

-REO False to -ACK False
(-OACK False)

140

t11

Data Setup Time to -REO

Data Hold Time from -REO

t12

Condition

Note: -EOP. -lOR. and -OACK must be concurrently true for at least t6 for proper recognition of the -EOP pulse.

ORO
-OACK

-lOR

~O-

-EOP
-REO

-ACK

-OBO --OB7.
-OBP

220

VLSI TECHNOLOGY, INC
VL53C80

SWITCHING CHARACTERISTICS/WAVEFORMS (Cont.)
DMA WRITE (BLOCK MODE) TARGET SEND
Symbol

Description

DRO False from -DACK True

Min

Max
130

Units

Condition

Write Enable Width

100

Write Recovery Time

120

Data Setup to End of Write Enable

Data Hold Time from End of -lOW

Width of -EOP Pulse (Note)

100

-ACK True to -REO False

125

-REO from End of -ACK
(-ACK False)

180

-REO from End of -ACK
(-lOW False)

170

t10

140

Write Enable Occurs When -lOW and -DACK

-ACK True to READY True

t11

READY True to -lOW False

t12

-lOW False to READY False

t13

Data Hold from -ACK True

t14

Data Setup to -REO True

ns
140

Note: -EOP, -lOW, and -DACK must be concurrently true for at least t6 for proper recognition of the -EOP pulse.

ORO
-DACK

----'/

tl~---

-lOW

DO - 07
-EOP

-REO
-ACK
---4~~----t11------~~~-----t12------~~

READY

=g~~ --DB7,---------B-YT--E-N-_1-------~...~·,. .- - -----:...t-14-----B:Y-T-E:!~N-------221

VLSI TECHNOLOGY, INC.
VL53C80

SWITCHING CHARACTERISTICS/WAVEFORMS(Cont.)
DMA READ (BLOCK MODE) TARGET RECEIVE
Symbol

Description

Min

DRO False from -DACK True

-lOR Recovery Time

Data Access Time from Read Enable

Max
130

Units
ns
ns

120
110

Data Hold Time from End of -lOR

Width of -EOP Pulse (Note)

100

-lOR False to -REO True
(-ACK False)

190

-ACK True to -REO False

125

-ACK False to -REO True
(-lOR False)

170

-ACK True to READY True

140

t10

READY true to Valid Data

140

t11

-lOR False to READY False

t12

Data Setup Time to -ACK

t13

Data Hold Time from -ACK

Condition

Read Enable Occurs When -lOR and -DACK

Note: -EOP, -lOR, and -DACK must be concurrently true for at least t5 for proper recognition of the -EOP pulse.

DRO

tt={

-------'/

-DACK

-lOR

DO - D7
-EOP
-REO

-ACK
~---

READY

-DBO--DB~

-DBP

~"2

m
BYTE N

222

t11

----t~

VLSI TECHNOLOGY, INC.
VL53C80

SWITCHING CHARACTERISTICS/WAVEFORMS (Cant.)
RESET
Symbol

Description

Min

Minimum Width of Reset

200

Max

t___t1_t

-RESET

Units

Condition

ARBITRATION
Symbol

Description

Bus Clear from -SEL True

Arbitrate Start from -BSY False

Bus Clear from -BSY False

Min

1200

Max

Units

600

2200

1100

Condition

-RST

-SEL

___--J/

-BSY

-OBO - -OB7, ~WW'@~
-OBP

ARB

-BSY (IN)

________________;=-t3-------

223

VLSI TECHNOLOGY, INC
VL53C80

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

O°C to +70°C

Storage Temperature -65°C to + 150°C
Supply Voltage to
Ground Potential
Applied Input
Voltage

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only, functional
operation of this device at these or any
other conditions above those indicated

in this data sheet is not implied.
Exposure to absolute maximum rating
conditions for extended periods may
affect device reliability.

+6 V

-0.6 V to VCC +0.6 V

Power Dissipation

0.8W

DC CHARACTERISTICS: TA = O°C to +70°C, VCC = 5 V ±5%
Symbol

Parameter

VIH

Min

Max

Units

High Level Input Voltage

2.0

5.25

VIL

Low Level Input Voltage

-0.3

0.8

IIH

High Level Input Current on:

ilL

SCSI Bus Pins

JlA

All Other Pins

JlA

Low Level Input Current on:
SCSI Bus Pins

-50

!lA

All Other Pins

-10

JlA

VOH

High Level Output Voltage

VOL

Low Level Output Voltage on:

2.4

Condition

VIH

= 5.25 V, VIL = 0

VIH

= 5.25 V, VIL = 0

VDD

= 4.75 V,

= 4.75 V, IOL =48.0 mA
= 4.75 V, IOL = 7.0 mA

SCSI Bus Pins

0.5

VDD

All Other Pins

0.5

VDD

224

=-3.0 mA

IOH

VLSI TECHNOLOGY, INC
VL65NC02
CMOS a-BIT MICROPROCESSOR

FEATURES

DESCRIPTION

• CMOS silicon-gate technology

The VL65NC02 is an a-bit microprocessor device produced using CMOS
silicon-gate technology. This device
provides advanced system architecture
for enhancements in system performance, speed, and value over its NMOS
counterparts, the 65XX family of
microprocessor devices. The VL65NC02
is the CMOS equivalent of the NMOS
6502, and contains some enha;,cements. This CMOS type may exhibit
different intermediate cycle information
from that resident in the NMOS 6502.
Intermediate cycle information is not
specified, and should not be used.

• Low power
-1.1 mA/MHz
• Software compatible with the NMOS
6502
• Single 5 V power supply required
• a-bit parallel processing
• True indexing capability
• Programmable stack pointer
• Interrupt capability
• Non-maskable interrupt
• a-bit bidirectional data bus

The VL65NC02 provides 64K bytes of
addressable memory and an interrupt
input, as well as options for on-chip
oscillators and drivers. It is bus and
software compatible with the 65XX CPU
family.

• Addressable memory range of up to
64K bytes
• Ready input
• Direct memory access (DMA)
capability

CLOCK GENERATOR
The clock generator develops all internal
clock signals and (where applicable)
external clock signals associated with
the device. It is the clock generator that
drives the timing control unit and the
external timing for slave mode
operations.

• Clock speeds up to 4 MHz
• Pipelined architecture
• On-chip clock options:
-External single-input clock
-On-board clock, single external
crystal

PIN DIAGRAM

ROY
01 (OUT)

-IRQ
N.C.
-NMI
SYNC
VCC

PROGRAM COUNTER
The 16-bit program counter provides the
addresses that step the microprocessor
through sequential instructions in a
program.
Each time the microprocessor fetches
an instruction from program memory,
the lower byte of the program counter
(PCL) is placed on the low-order bits of
the address bus and the higher byte of
the program counter (PCH) is placed on
the high-order a bits. The counter is
incremented each time an instruction or
data is fetched from program memory.

ORDER INFORMATION
•Part
Number

VL65NC02
VSS

TIMING CONTROL
The timing control unit keeps track of
the instruction cycle being monitored.
The unit is set to zero each time an
instruction fetch is executed and is
advanced at the beginning of each
phase-one clock pulse for as many
cycles as are required to complete the
instruction. Each data transfer that
takes place between the registers
depends upon decoding the contents of
both the instruction register and the
timing control unit.

-RES
02 (OUT)

1 MHz

S.O.

2MHz
VL65NC02-03PC

VL65NC02-03CC

05
06

A7
NJ

A15
A14
A13
A12
VSS

A9
A10
A11

Ceramic DIP

VL65NC02-02CC

Plastic DIP

VL65NC02-02PC

Ceramic DIP

VL65NC02-01 CC

00,(IN)
N.C.
N.C.
RJ-W

M
AS
A6

Package
Plastic DIP

VL65NC02-01 PC

01
02

Clock
Frequency

Plastic DIP
3 MHz
Ceramic DIP
Plastic DIP

VL65NC02-04PC
4 MHz

VL65NC02-04CC

Ceramic DIP

Note: Operating temperature range is O°C to +70°C.

225

VLSI TECHNOLOGY, INC
VL65NC02

BLOCK DIAGRAM
INTERNAL ARCHITECTURE
REGISTER SECTION

CONTROL SECTION
r-'I

---,

•
•

ABl

I
~

,.......,

~
1....01

I""'"

.II

AS . .

ACCUMULATOR
A

A11.

A12.

1"1

.L
"'I

A1S.
L-.-

....... .......

.....

~
-

P IT

S
14
~

TIMING

CONTROL

~~.

"It

~>-

r GENERATOR
CLOCK

PROCESSOR
STATUS
REGISTER P

DATA BUS
BUFFER

~
.....
.......
.4~

0O,(IN)

- 1

--...

....

l ~~l~~ II~~~t~ l

--..
--..
...
...
...
...
......
..

DO
01
02
03
04
05
06
07

. -

226

I-

01,OUT
02, OUT

INSTRUCTION
REGISTER

S BIT LINE
1 BIT LINE

SYN C

INSTRUCTION
DECODE

INPUT DATA I ..
LATCH (Dl)

lEGEND:

...

ROY

I
~

N-v

PCH

~1~l l~~~~.

<:=

.... + +

.....
.......

A14.

L-

lOGIC

~
-

PCl

ABH'l

A13.

INTERRUPT

l-"

A10.

ALU

---.

A9.

~
..

I .....

A7.~

ADDRESS
BUS

STACK
POINT
REGISTER (S)

L.....;.

I""'"

-IRQ NMI

INDEX
REGISTER
Y

INDEX
REGISTER
X

•
•

-R~S ~·l

OATA
BUS

R/-W

VLSI TECHNOLOGY, INC.
VL65NC02

TABLE 1. HARDWARE ENHANCEMENTS
The VL65NC02 microprocessor has
been designed with several hardware
and software enhancements over the
NMOS 6502 device, while maintaining
software compatability. In addition to the
increased speed and lower power
consumption inherent in CMOS technology, the VL65NC02 has the following
characteristics:

VL65NC02 Enhancements
Pin compatible with NMOS 6502
64K addressable bytes of memory
-IRQ interrupt
TTL-level single phase clock input

• Two new addressing modes

RC time base clock input

• Seven software/operational
enhancements

Crystal time base clock input
Two-phase output clock

• Two hardware enhancements:

SYNC and ROY signals

- Eight new instructions, 64 total
- 27 new opcodes, 178 total

-NMI interrupt signal

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Description

00 (IN),
01 (OUT),
02 (OUT)

37,
3,39

Clock Signals - The VL65NC02 requires an external 00 clock. 00 is a TTL-level input
that is used to generate the internal clocks of the VL65NC02. Two full-level output
clocks are generated by the VL65NC02. The 02 clock is in phase with 00. The 01
clock output is 1800 out of phase with 00. When 00 is stopped, the CPU is in the
standby mode.

-IRQ

Interrupt Request - This TTL-compatible input requests that an interrupt sequence begin
within the microprocessor. The -IRQ is sampled during 02 operation; if the interrupt flag
in the processor status register is zero, the current instruction is completed and the
interrupt sequence begins during 01. The program counter and processor status
register are stored in the stack. The microprocessor then sets the interrupt mask flag
high so that no further -IRQs may occur. At the end of this cycle, the program counter
low byte is loaded from address FFFE, and program counter high byte from location
FFFF, thus transferring program control to the memory vector located at these addresses. The ROY signal must be in the high state for any interrupt to be recognized. A
3 kn external resistor should be used for proper wire-OR operation.

-NMI

Non-Maskable Interrupt - A negative-going edge on this input requests that a non-maskable interrupt sequence be generated within the microprocessor. The -NMI is sampled
during 02; the current instruction is completed and the interrupt sequence begins during
01. The program counter is loaded with the interrupt vector from locations FFFA (low
byte) and FFFB (high byte), thereby transferring program control to the non-maskable
interrupt routine. Since this interrupt is non-maskable, another -NMI can occur before
the first is finished. Care should be taken when using -NMI to avoid this.

227

VLSI TECHNOLOGY, INC
VL65NC02

SIGNAL DESCRIPTIONS (Cant.)
Signal
Name

Pin
Number

Signal
Description

ROY

Ready - This input allows the user to single-cycle the microprocessor on all cycles,
including wr~e cycles. A negative transition to the low state, during or coincident with
01, halts the microprocessor with the output address lines reflecting the current address
being fetched. This condition remains through a subsequent 02 in which the ready
signal is low. This feature allows microprocessor interfacing with low-speed memory as
well as direct memory access (DMA).

R/-W

ReadlWrite - This signal is normally in the high state, indicating that the microprocessor
is reading data from memory or 110 bus. In the low state, the data bus has valid data
from the microprocessor to be stored at the addressed memory location.

-SO

Set Overflow - A negative transition on this line sets the overflow bit (V) in the processor
status register. The signal is sampled prior to the leading edge of 02 by the processor
control time (tRWS).

-RES

Reset - This input resets the microprocessor. Reset must be held low for at least two
clock cycles after VCC reaches operating voltage from a power-down. A positive transition on this pin causes an initialization sequence to begin. Likewise, after the system
has been operating, a Iowan this line of at least two cycles ceases microprocessing
activity, followed by initialization after the positive edge on -RES.
When a pos~ive edge is detected, there is an initialization sequence lasting six clock
cycles. Then, the interrupt mask flag is set, the decimal mode is cleared, and the
program counter is loaded with the restart vector from locations FFFC (low byte) and
FFFD (high byte). This is the start location for program control. This input should be
high in normal operation.

SYNC

Synchronize - This output line identifies those cycles during which the microprocessor is
fetching the instruction operation code (op code). The SYNC line goes high during 01 of
an opcode fetch and stays high for the remainder of that cycle. If the ROY line is pulled
low during the 01 clock pulse in which SYNC went high, the processor stops in its
current state and remains in the state until the ROY line goes high. In this manner, the
SYNC signal can be used to control ROY to cause single instruction execution.

AO - A15

9 - 25

Address Bus - AO-A 15 forms a 16-bit address bus for memory and 110 exchanges on the
data bus. The output of each address line is TIL-compatible, capable of driving one
standard TIL load and 130 pF.

00- 07

33 -26

Data Bus - The data lines const~ute an 8-b~ bidirectional data bus used for data exchanges to and from the device and peripherals. The outputs are three-state buffers
capable of driving one TIL load and 130 pF.

VCC

5 V ± 5% power supply

VSS

1,21

Digital ground

228

VLSI TECHNOLOGY, INC.
VL65NC02

INSTRUCTION AND
REGISTER DECODE
Instructions fetched from memory are
gated onto the internal data bus. These
instructions are latched into the instruction register, then decoded, along with
timing and interrupt signals, to generate
control signals for the various registers.
ARITHMETIC/LOGIC UNIT
All arithmetic and logic operations take
place in the ALU, including incrementing
and decrementing internal registers
(except the program counter). The ALU
has no internal memory and is used only
to perform logical and transient numerical operations.
ACCUMULATOR
The accumulator is a general-purpose 8bit register that stores the results of
most arithmetic and logic operations. In
addition, the accumulator usually
contains one of the two data words used
in these operations.
INDEX REGISTER
There are two 8-bit index registers (X
and Y) that may be used to count
program steps or to provide an index
value to be used in generating an
effective address.

When executing an instruction that
specifies indexed addressing, the CPU
fetches the op code and the base
address, and modifies the address by
adding the index register to it prior to
performing the desired operation. Preor post-indexing of indirect addresses is
possible (see addressing modes).
STACK POINTER
The stack pointer is an 8-bit register
used to control the addressing of the
variable-length stack on page one. The
stack pointer is automatically incremented and decremented under control
of the microprocessor to perform stack
manipulations under direction of either
the program or interrupts (-NMI and
-IRQ). The stack allows simple implementation of nested sub-routines and
mulitple-Ievel interrupts. The stack
pointer should be initialized before any
interrupts or stack operations occur.
PROCESSOR STATUS REGISTER
The 8-bit processor status register contains seven status flags. Some of the
flags are controlled by the program,
others may be controlled by the program
and the CPU. The VL65NC02 instruc-

tion set contains a number of conditional
branch instructions that are designed to
allow testing of these flags.
HARDWARE ENHANCEMENTS
The VL65NC02 microprocessor
incorporates several hardware enhancements over its NMOS counterpart,
the 6502. These hardware enhancements are:
• The NMOS device would ignore the
assertion of a Ready (ROY) during a
write operation. The CMOS family
stops the processor during 02 clock
if ROY is asserted during a write
operation.
• On the NMOS device, unused inputonly pins (-IRQ, -NMI, ROY, -RES,
and -SO) must be connected to a low
impedance signal to avoid noise
problems. These unused pins on the
CMOS devices are internally connected by a high-impedance to
VCC (approximately 250 1Ul).
OPERATIONAL ENHANCEMENTS
Tables 1 lists the operational enhancements that have been added to the
VL65NC02 device.

TABLE 2. NO OPERATION (NOP) TIMING FOR UNDEFINED OPCODES
Opcode

Number of Bytes Expected
(Total- Including Opcode):

Number of
Cycles:

X2
X3
X7
XB
XF

1
1
1
1

44
54

2
2
2
2
3
3
3

3
4
4
4
8
4
4

D4
F4
5C
DC
FC

Note: "X" indicates a "Don't Care".

229

VLSI TECHNOLOGY, INC.
VL65NC02

TABLE 3. INSTRUCTION SET SUMMARY
IMMEDIATE
MNEMONIC
ADC
AND
ASL
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRA
BRK
BVC
BVS
CLC
CLD
CLI
CLV
CMP
CPX
CPY
DEC
DEX
DEY
EOR
INC
INX
INY
JMP
JSR
LDA
LDX
LDY
LSR
NOP
ORA
PHA
PHP
PHX
PHY
PLA
PLP
PLX
PLY
ROL
ROR
RTI
RTS
SBC
SEC
SED
SEI
STA
STP
STX
STY
STZ
TAX
TAY
TRB
TSB
TSX
TXA
TXS
TYA
WAI

OPERATION
A+M+C-A (3)
AI\M-A
C - U=::JjJ -0
BRANCH IF C=O (2)
BRANCH IF C=1 (2)
BRANCH IF Z=1 (2)
AI\M
(5)
BRANCH IF N=1 (2)
BRANCH IF Z=O (2)
BRANCH IF N=O (2)
BRANCH ALWAYS(2)
BREAK
BRANCH IF v=o (2)
BRANCH IF V=1 (2)
O-C
0-0
0-1
O-V
A-M
X-M
YoM
DECREMENT
X-l- X
Y-1- Y
A'Q'M -A
INCREMENT
X+1- X
Y+1- Y
JUMP TO NEW LOC
JUMP SUB
M-A
M-X
M-Y
0NO OPERATION
AVM-A
A-Ms S-I-S
P-Ms S-I-S
X-Ms S-I-S
Y-Ms S-I-S
S+I-S Ms-A
S+I-S Ms-P
S+l-S Ms-X
S+I-S M~-Y
L
CJ

r:z==:Ql-c

cr:::::=:::DJ -

LC-~ .J

RTRNINT
RTRN SUB
A-M-C-A
,.- C
l-D
1-1
A-M
STOP (1-1/>2)
X-M
Y-M
00- M
A-X
A-Y
AI\M-M
AVM-M
S-X
X-A
X-S
V-A
O-RDY

(3)

(6)
(6)

ABSOLUTE

(4)
(1)
ZERO
PAGE IMPLIED (IND. X) (IND). Y

ZPG.X

OP n # OP n # OP n # OP n # OP n # OP n # OP n #
6922 60 4 3 6~ 32
61 62 71 5 2 7542
2922 20 43 2~ 32
21 62 31 5 2 3542
OE 6 3 O€ 5 2 OA 2 1
1662

89 2 2 2C 43

(1)
ABS.X

RELA(1)
ABS.Y TlVE(2)

n # OP n # OP n #
43 7943
4 3 3943
6 3
9022
BO 2 2
FO 2 2
34 4 2 3C 4 3
3022
DO 2 2
1022
8022

24 3 2

OP
7D
30
lE

00 7 1
5022
7022
18 2
08 2
58 2
B82
C9 22 CD 4
EO 2 2 EC 4
CO 22 CC 4
CE 6

3
3
3
3

4922 4D 43
EE 63

C5
E4
C4
C6

3
3
3
5

2
2
2
2 3A
CA
88
4532
E6 5 2 lA
E8
C8

1
1
1
1
Cl 6 2 01 52 05 42 DO 43 09 43

2 1
2 1
2 1

D6 62 DE 6 3

41 6 2

51 52

2 1
2 1
2 1

4C 3 3
2063
A9 22 AD 4 3 A5 3 2
A2 2 2 AE 4 3 A632
AO 2 2 AC 4 3 A4 3 2
4E 63 4652 4A 2
EA 2
0922 OD 4 3 0532
48 3
083
DA 3
SA 3
68 4
284
FA 4
7A 4
2E 63 2652 2A 2
6E 6 3 66 5 2 6A 2
40 6
606
E9 2 2 ED 4 3 ES 3 2
38 2
F8 2
78 2
8D 4 3 8532
DB 3
8E 4 3 8632
8C 43 8432
9C 4 3 6432
AA 2
A82
lC 63 1452
OC 63 0452
BA 2
8A 2
9A 2
98 2
CB 3

5542 5D 4 3
F6 6 2 FE 6 3

5943

INDIRECT

PROCESSOR
ZPG.Y STATUS CODE
7643210 MNEOP n # OP n # N VB 0 I ZC MONIC
N V • • • Z C ADC
7252
N. • •• Z •
3252
AND
N. • •• Z C
ASL
BCC
BCS
BEQ
M,M.· • • Z •
BIT
BMI
BNE
BPL
BRA
1 0 1 ••
BRK
BVC
BVS
CLC
• • • 0
• 0 •••
CLD
CLI
• 0 ••
CLV
• 0 •
N. • •• Z C CMP
0252
N •• • • Z C
CPX
N· • • • Z C CPY
N. • •• z •
DEC
N •• • • z •
DEX
N. • •• Z •
DEY
N •• • • z •
5252
EOR
N. • •• z •
INC
N ••
INX
N. • •• z •
INY
6C 6 3
JMP
JSR
N •• • • z •
B2 5 2
lOA
2
N
•
•
B64
• • z • LDX
N. • •• Z •
LDY
o • • •• Z C
LSR
NOP
N •• • • Z •
1252
ORA
PHA
PHP
PHX
PHY
N· • • • z •
PLA
NVI DIZC
PLP
N· •
PLX
PLY
N • • • • z•
N. • • • Z C ROL
N • • • • Z C ROR
NV1DIZC
RTI
RTS
N V • • • Z C SBC
F2 5 2
• • • • 1 SEC
1 •••
SED
• • 1 ••
SEI
9252
STA
STP
964 2 • • •
STX
STY
STZ
N ••
TAX
N •• • • Z •
TAY
• • z • TRB
• • z • TSB
N. • •• Z •
TSX
N· • •• z •
TXA
TXS
N.
TYA
WAI

··.. ·· ....
...
·.. ·....
·....
...
··..
·
.
·
...
··.... · ...
··.. · ....
. · ....
···...
· .. ·...

••z•

7C 6 3
Al 6 2 Bl 5 2 B5 4 2 BD 43 B943
BE 43
B4 4 2 BC 4 3
1
5662 5E 63
1
01 62 11 5 2 1542 lD 4 3 1943
1
1
1
1
1
1
1
1
1
3662 3E 6 3
1
7662 7E 6 3
1
1
El 6 2 Fl 5 2 F5 4 2 FD 43 F943
1
1
1
81 62 91 62 9542 9D 53 9953
1
9442
7442 9E 5 3
1
1

1
1
1
1
1

· ...
··... · ....

·.. ·...
...
·..... ··...
··.. ·· ....
....
• • z·

·.. · ...
···....
··... · ....
··...
...

· ....
··.. · ....
• • z.
··....

· . ·• ....
•• z •

·.. ·...

230

"VLSI TECHNOLOGY, INC
VL65NC02
TABLE 4. INSTRUCTION SET SUMMARY ABBREVIATIONS
X
Y
A
M
Ms
+

Index X
Index Y
Accumulator
Memory per Effective Address
Memory per stack Pointer
Add
Subtract

And
V
Or
lJ. Exclusive Or
n Number of Cycles
# Number of Bytes
M6 Memory Bit 6
M7 Memorv Bit 7

Add 1 to "n" if decimal mode, if page
boundary is crossed (except STA and
STZ), or if branch on same page (add 2
if page different). Accumulator address
os included in implied address. "N" and
"V" flags are unchanged in immediate
mode. "Z" flag includes N'M
result (same as BIT instruction).

ADDRESSING MODES
The VL65NC02 CPU has 15 addressing
modes (two more than the NMOSequivalent family). In the following
discussion of these addressing modes,
a bracketed expression follows the title
of the mode. This expression is the
term used in the Instruction Set Opcode
Matrix, Table 8, to make it easier to
identify the actual addressing mode
used by the instruction.
ACCUMULATOR ADDRESSING
[Accum]- This form of addressing is
represented by a one-byte instruction,
implying an operation on the accumulator.
IMMEDIATE ADDRESSING
[IMM] - In immediate addressing, the
second byte of the instruction contains
the operand, with no further memory
addressing required.
ABSOLUTE ADDRESSING
[Absolute] - In absolute addressing, the
second byte of the instruction specifies
the eight low-order bits of the effective
address, while the third byte specifies
the eight high-order bits. Thus, the
absolute addressing mode allows
access to the entire 64K bytes of
addressable memory.
ZERO PAGE ADDRESSING
[ZP] - The zero page instructions allow
for shorter code and execution times by
fetching only the second byte of the
instruction and assuming a zero high
address byte. Careful use of the zeropage can result in a significant increase
in code efficiency.
INDEXED ZERO PAGED ADDRESSING
[ZP, X, or y] - (X, Y Indexing) - This
form of addressing is used with the
index register and is referred to as
"zero-page, X" or "zero-page, V". The
effective address is calculated by adding
the second byte to the contents of the
index register. Since this is a form of
"zero-page" addressing, the content of

the second byte references a location in
page zero. Additionally, due to the
"zero-page" addressing nature of this
mode, no carry is added to the highorder eight bits of memory and crossing
of page boundaries does not occur.
INDEXED ABSOLUTE ADDRESSING
[ABS, X, or y] - (X, Y Indexing) - This
form of addressing is used in conjunction with X and Y index register and is
referred to as "absolute, X" and
"absolute, Y". The effective address is
formed by adding the contents of X or Y
to the address contained in the second
and third bytes of the instruction. This
mode allows the index register to
contain the index or count value and the
instruction to contain the base address.
This type of indexing allows any location
referencing and the index to modify
multiple fields, resulting in reduced
coding and execution time.
INDEXED ABSOLUTE INDIRECT
[(INO), X] - (JMP (IN D), X) - The
contents of the second and third
instruction bytes are added to the X
register. The 16-bit result is a memory
address containing the effective
address.
IMPLIED ADDRESSING
[Implied] - In the implied addressing
mode, the address containing the
operand is implicity stated in the
operation code of the instruction.
RELATIVEADDRESSING
[Relative] - Relative addressing is used
only with branch instructions and
establishes a destination for the
conditional branch.
The second byte of the instruction
becomes the operand, which is an
"offset" added to the contents of the
lower eight bits of the program counter
when the counter is set at the next
instruction. The 8-bit offset provides a
branching range of -128 to +127 bytes
from the next instruction.

231

INDEXED INDIRECT ADDRESSING
[(INO, X)] - In indexed indirect addressing, referred to as indirect, X, the
second byte of the instruction is added
to the contents of the X index register,
discarding the carry. The result of this
addition points to a memory location on
page zero whose contents are the loworder eight bits of the effective address.
The next memory location in page zero
contains the high-order eight bits of the
effective address. Both memory
locations specifying the high-and loworder bytes of the effective address
must be in page zero.
INDIRECT INDEXED ADDRESSING
[(INO), Y] - In indirect indexed addressing, referred to as indirect, Y, the
second byte of the instruction points to a
memory location in page zero. The
contents of this memory location are
added to the contents of the Y index
register, the result being the low-order
eight bits of the effective address. The
carry from this addition is added to the
contents of the next page zero memory
location, the result being the high-order
eight bits of the effective address.
ABSOLUTE INDIRECT
[Indirect] - The second byte of the
instruction contains the low-order eight
bits of a memory location. The highorder eight bits of that memory location
are contained in the third byte of the
instruction. The contents of the fully
specified memory location are the loworder byte of the effective address. The
next memory location contains the highorder byte of the effective address,
which is loaded into the 16 bits of the
program counter, (JMP (INO) only).
INDIRECT
[(INO)] - The second byte of the
instruction contains a zero page address
serving as the indirect pointer. This is
not available on the NMOS 6500 family.

0) VLSI TECHNOLOGY, INC
VL65NC02
INSTRUCTION SET
Table 5 lists the instruction set for the CMOS CPU family in alphabetic order according to mnemonic. Table 6 lists the hexadecimal
codes for each of the instructions that are new to the CMOS family and were not available in the NMOS 6502 device family. Table
7 lists those instructions that were available on the NMOS family, but have been assigned new addressing modes in the CMOS
CPU family.

TABLE 5. INSTRUCTION SET LISTING (ALPHABETIC)
Mnemonic
(2)
(2)

ADC
AND
ASL

(1)(3) BBR
(1 )(3) BBS
BCC
BCS
BEQ
(2)
BIT
BMI
BNE
BPL
(1 )
BRA
BRK
BVC
BVS

Function
Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)
Branch on Bit Reset
Branch on Bit Set
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Branch Atways
Force Break
Branch on Overflow Clear
Branch on Overflow Set

CLC
CLD
CLI
CLV
CMP
CPX
CPY

Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory and Index Y

(2)

DEC
DEX
DEY

Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One

(2)

EOR

"Exclusive-OR" Memory with Accumulator

(2)

INC
INX
INY

Increment Memory by One
Increment Index X by One
Increment Index Y by One

(2)

JMP
JSR

Jump to New Location
Jump to New Location Saving Return Address

(2)

LOA
LOX
LOY
LSR

Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or Accumulator)

(2)

Mnemonic

(2)

(1)
(1)

Function

NOP

No Operation

ORA

"OR" Memory with Accumulator

PHA
PHP
PHX
PHY
PLA
PLP
PLX
PLY

Push Accumulator on Stack
Push Processor Status on Stack
Push X Register on Stack
Push Y Register on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack
Pull X Register from Stack
Pull Y Register from Stack

(1)(3) RMB
ROL
ROR
RTI
RTS

Reset Memory Bit
Rotate One Bit Left (Memory or Accumulator)
Rotate One Bit Right (Memory or Accumulator)
Return from Interrupt
Return from Subroutine

(2)

Subtract Memory from Accumulator with Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
Store Zero

SBC
SEC
SED
SEI
(1)(3) 5MB
(2)
STA
STX
STY
(1)
STZ

(1)
(1)

TAX
TAY
TRB
TSB
TSX

TXA
TXS
TVA

Transfer Accumulator to Index X
Transfer Accumulator to Index Y
Test and Reset Bits
Test and Set Bits
Transfer Stack Pointer to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Register
Transfer Index Y to Accumulator

Notes:
1. CMOS instruction not available on NMOS Family.
2. Previous NMOS instruction with additional addressing mode(s) added to the CMOS family.
3. 65C02 instruction not available on VL65NC02.

232

VLSI TECHNOLOGY, INC.
VL65NC02

TABLE 6. HEXADECIMAL CODES (NEW CMOS FAMILY INSTRUCTIONS)
Hex
80

3A
1A
DA
SA
FA
7A
9C

9E
64

74
1C
14

OC
04

89
OF-7F(1)
8F-FF(1 )
07-77(1)
87-F7(1)

Mnemonic
BRA
DEC
INC
PHX
PHY
PLX
PLY
STZ
STZ
STZ
STZ
TRB
TRB
TSB
TSB
BIT
BBR
BBS
RMB
5MB

Description
Branch Relative Always (Relative)
Decrement Accumulator (Accum)
Increment Accumulator (Accum)
Push X on Stack (Implied)
Push Yon Stack (Implied)
Pull X from Stack (Implied)
Pull Y from Stack (Implied)
Store Zero (Absolute)
Store Zero (ABS, X)
Store Zero (ZP)
Store Zero (ZP, X)
Test and Reset Memory Bits with Ao:umulator (Absolute)
Test and Reset Memory Bits with Ao:umulator (ZP)
Test and Set Memory Bits with Accumulator (Absolute)
Test and Set Memory Bits with Accumulator (ZP)
Test Immediate with Accumulator (IMM)
Branch on Bit Reset (Bit Manipulation, ZP)
Branch on Bit Set (Bit Manipulation, ZP)
Reset Memory Bit (Bit Manipulatiol\ ZP)
Set Memory Bit (Bit Manipulation, ZP)

Note:
1. Most significant digit change only. Instruction not available on 65C02.

TABLE 7. HEXADECIMAL CODES
(INSTRUCTIONS WITH NEW CMOS ADDRESSING MODES)
Hex

32
3C
34

02
52

Mnemonic
ADC
AND
BIT
BIT
CMP
EOR
JMP

LOA

ORA
SBC
STA

Description
Add Memory to Accumulator with Carry [(ZP)]
AND Memory with Accumulator [{ZP)]
Test Memory Bits with Accumulator [ABS, X]
Test Memory Bits with Accumulator [ZP, X]
Compare Memory and Accumulatol [(ZP)]
Exclusive-OR Memory with Accumulator [(ZP)]
Jump (New addressing mode) [(IND),X]
Load Accumulator with Memory [(ZP)]
OR Memory with Accumulator [{ZP)]
Subtract Memory from Accumulator with Borrow [(ZP)]
Store Accumulator in Memory [(ZP)]

233

VLSI TECHNOLOGY, INC
VL65NC02

TABLE 8. INSTRUCTION SET OPCODE MATRIX
The following matrix shows the 210 op codes associated with the VL65NC02 microprocessor. The matrix identifies the hexadecimal code, the addressing mode, and the number of machine cycles associated with each op code.

LSD 0

JSR
AB~

RTI
EOR
Implied (IND. X)
1 6
2 6

BVC
EOR
Relative (IND). Y
2 2"
2 5'
RTS
Implied
1 6

BRA
STA
Relative (IND. X)
2 6
2 3'

BCC
STA
Relative (IND). Y
2 2"
2 6

o
E

RMBO
ZP
2 5

PHP
Implied
1 3

ORA
IMM
2 2

ASL
Accum
1 2

TSB
ABS
3 6

ORA
ABS
3 4

ASL
ABS
3 6

BBRO
ZP
3 5"

TRB
ZP
2 5

ORA
ZP.X
2 4

ASL
Zp.X
2 6

RMBl
ZP
2 5

CLC
Implied
1 2

ORA
ABS. Y
3 4'

INC
Accum
1 2

TRB
ABS
3 6

ORA
ABS. X
3 4'

ASL
ABS.X
3 7

BIT
ZP
2 3

AND
ZP
2 3

ROL
ZP
2 5

RMB2
ZP
2 5

PLP
Implied
1 4

AND
IMM
2 2

ROL
Accum
1 2

BIT
ABS
3 4

AND
ABS
3 4

ROL
ABS
3 6

BIT
ZP. X
2 4

AND
ZP.X
2 4

ROL
Zp.X
2 6

RMB3
ZP
2 5

SEC
Implied
1 2

AND
ABS. Y
3 4'

DEC
Accum
1 2

BIT
ABS.X
3 4'

AND
ABS.X
3 4'

ROL
ABS.X
3 7

EOR
ZP
2 3

LSR
ZP
2 5

RMB4
ZP
2 5

PHA
Implied
1 3

EOR
IMM
2 2

LSR
Accum
1 2

JMP
ABS
3 3

EOR
ABS
3 4

LSR
ABS
3 6

EOR
ZP. X
2 4

LSR
ZP. X
2 6

RMB5
ZP
2 5

Cli
Implied
1 2

EOR
ABS.Y
3 4'

PHY
Implied
1 3

EOR
ABS.X
3 4'

LSR
ABS. X
3 7

STZ
ZP
2 3

ADC
ZP
2 3t

ROR
ZP
2 5

RMB6
ZP
2 5

PLA
Implied
1 4

ADC
IMM
2 2t

ROR
Accum
1 2

JMP
(ABS)
3 6

ADC
ABS
3 4t

ROR
ABS
3 6

STZ
Zp.X
2 4

ADC
ZP. X
2 4t

ROR
Zp.X
2 6

RMB7
ZP
2 5

SEI
Implied
1 2

ADC
ABS. Y
3 4't

PLY
Implied
1 4·

JMP
ABS.X
3 6

ADC
ABS.X
3 4't

ROR
ABS. X
3 7

STY
ZP
2 3

STA
ZP
2 3

STX
ZP
2 3

5MBO
ZP
2 5

DEY
Implied
1 2

BIT
IMM
2 2

TXA
Implied
1 2

STY
ABS
3 4

STA
ABS
3 4

STX
ABS
3 4

BBSO
ZP
3 5"

STA
(IND)
2 5

STY
ZP.X
2 4

STA
ZP.X
2 4

STX
ZP.Y
2 4

5MBl
ZP
2 5

TYA
Implied
1 2

STA
ABS.Y
3 5

TXS
Implied
1 2

STZ
ABS
3 4

STA
ABS.X
3 5

STZ
ABS. X
3 5

BBSl
ZP
3 5"

LOY
IMM
2 2

LOX
IMM
2 2

LOY
ZP
2 3

LOA
ZP
2 3

LOX
ZP
2 3

5MB2
ZP
2 5

TAY
Implied
1 2

LOA
IMM
2 2

TAX
Implied
1 2

LOY
ABS
3 4

LOA
ABS
3 4

LOX
ABS
3 4

BBS2
ZP
3 5"

LOA
(INO)
2 5

LOY
ZP. X
2 4

LOA
ZP.X
2 4

LOX
ZP.Y
2 4

5MB3
ZP
2 5

CLV
Implied
1 2

LOA
ABS.Y
3 4'

TSX
Implied
1 2

LOY
ABS.X
3 4'

LOA
ABS.X
3 4'

LOX
ABS.Y
3 4'

BBS3
ZP
3 5"

LOA
(IND. X)
2 6

BCS
LOA
Relative (INO). Y
2 2"
2 5'
CPY
IMM
2 2

CPY
ZP
2 3

·CMP
ZP
2 3

DEC
ZP
2 5

5MB4
ZP
2 5

INY
Implied
1 2

CMP
IMM
2 2

OEX
Implied
1 2

CPY
ABS
3 4

CMP
ABS
3 4

DEC
ABS
3 6

BBS4
ZP
5"

CMP
ZP. X
2 4

DEC
Zp.X
2 6

5MB5
ZP
2 5

CLO
Implied
1 2

CMP
ABS. Y
3 4'

PHX
Implied
1 3

CMP
ABS. X
3 4'

DEC
ABS. X
3 7

BBS5
ZP
3 5"

sac
ZP
2 3t

INC
ZP
2 5

5MB6
ZP
2 5

INX
Implied
1 2

SBC
IMM
2 2t

NOP
Implied
1 2

SBC
ABS
3 4t

INC
ABS
3 6

BBSS
ZP
5"

sac
ZP. X
2 4t

INC
Zp.X
2 6

5MB7
ZP
2 5

SED
Implied
1 2

SBC
ABS.Y
3 4't

PLX
Implied
1 4

SBC
ABS.X
3 4't

INC
AaS. X
3 7

BBS7
ZP
3 5"

EOR
(IND)
2 5

ADC
(IND)
2 5t

CMP
(INO)
2 5
CPX
ZP
2 3

SBC
(IND. X)
2 6t

BEQ
SBC
Relative (INO). Y
2 2"
2 5't

AND
(IND)
2 5

CMP
(IND. X)
2 6

BNE
CMP
Relative (INO). Y
2 2"
2 5'
CPX
IMM
2 2

ORA
(IND)
2 5

ADC
(IND. X)
2 6t

BVS
ADC
Relative (IND). Y
2 2" 2 5't

6
ASL
ZP
2 5

AND
(IND. X)
2 6

BMI
AND
Relative (IND). Y
2 2"
2 5'

5
ORA
ZP
2 3

BRK
ORA
Implied (IND. X)
1 7
2 6
BPL
ORA
Relative (IND). Y
2 2"
2 5'

4
TSB
ZP
2 5

sac
(INO)
2 5t

D--~

BRK
Implied
1 7

-op Code
-Addressing Mode
-Instruction Bytes; Machine Cycles

CPX
ABS
3 4

tAdd
'Add
"Add
Add

Note: All of the op codes in column 7 and column F are interpreted as a NOP in the 65NC02.

234

1 to
1 to
1 to
2 to

N
N
N
N

BBRl
ZP
5"

BBR2
ZP
3 5"

BBR3
ZP
5"

BBR4
ZP
3 5"
BBR5
ZP
5"

BBR6
ZP
3 5"
BBR7
ZP
5"

if in decimal mode.
if page boundary is crossed.
if branch occurs to same page;
if branch occurs to different page.

VLSI TECHNOLOGY, INC.
VL65NC02

CRYSTAUCLOCK CONSIDERATIONS
Figure 1 shows a time base generation scheme for 4 MHz operation of the VL65NC02 that has been tested and proven reliable for
normal environments. As with any clock oscillator circuit, stray capacitance due to board layout can cause unpredictable results
requiring "fine tuning" of the circuit. Figure 2 shows a possible external clock scheme for standby mode. Table 9 identifies nominal
crystal parameters for five crystal frequencies.

Frequency (MHz)
Parameter

3.58

4.0

6.0

8.0

10.0

Units

30-50

20-40

10·30

3.5

6.5

4-6

3·5

0.15

0.025

0.01-0.02

0.01·0.02

740K

730K

720K

Note: AT-cut ?rystal parameters only. Others may be used.

FIGURE 1. TIME BASE GENERATOR
1.5

3.0

7404

7404
00 (IN)
VL65NC02

02 (OUT) 39

XTAL*

Note: CTS Knights MP Series or equivalent.
FIGURE 2. STANDBY MODE

00 (IN)
STOP
L=STANOBY
H=ACTIVE

SYNC

10
74HC74

CPU
02(OUT)~

TIME
BASE

y
+5V
STOPPING THE CLOCK·STANDBY MODE
Caution must be exercised when configuring the VL65NC02 in the standby mode (Le., 00 (IN) clock stopped). The input clock
can be held in the high state indefinitely; however, if the input clock is held in the low state longer than five Jls, internal register
and data status can be lost. Figure 2 shows a circuit that stops the 00 (IN) clock in the high state during standby mode.

VLSI TECHNOLOGY, INC
VL65NC02

FIGURE 3. TIMING DIAGRAM

00(IN) _ _ _"":::I

..---=---~-i~
=:::jr=
- 1>f--

tSK2

01(OUT) _ _ _ _~I. .- - tCl
02 (OUT)

.....-IR

tCYC
tAOS, tRWS, tSYS

tCH

--------J

D~D7

(READ) _ _ _ _ __

D~D7 -=============~~~~~~~~~-------t4

(WRITE) _

ROY ACTIVE

RDY,~RQ

~MI.:: ---

tiS

C==_~IR~Q~'~~~M~I'~-~RE=S~A~C~TI~VE~~i-_ _ _ _~='~ ~=H~~___

~b.-------"':""'------

Note: All timing .IS referenced from a high
. level of 2.4 volts and a low level of 0.5 volts.

VLSI TECHNOLOGY, INC.
VL65NC02

AC CHARACTERISTICS:

= O°C to +70°C, VCC = S V ±SOfo

CLOCK TIMING
1 MHz
Symbol

Parameter

2MHz

3 MHz

4 MHz

Min

Max

Min

Max

Min

Max

Min

Max

tCYC

02 Cycle Time

1000

Note(1)

500

Note(1)

333

Note(1)

250

Note(1)

Units
ns

tCl

02 Low Pulse Width

430

5000

210

5000

150

5000

100

5000

tCH

02 High Pulse Width

450

220

160

110

tSK2

00 to 02 Low Skew

tSK1

02 LOW to 01 High Skew

- 20

tR, tF

Clock Rise and Fall Times

READIWRITE TIMING
1 MHz
Symbol

Parameter

2 MHz

3 MHz

4 MHz

Min

Max

Min

Max

Min

Max

Min

Max

125

100

Units

tRWS

R/-W Setup Time

tHRW

R/-W Hold Time

215

160

40
10

tAOS

Address Setup Time

125

100

tHA

Address Hold Time

tACC

Read Access Time

775

Read Data Setup Time

100

340

tDSU
tHR

Read Data Hold Time

tMDS

Write Data Delay Time

200

110

tHW

Write Data Hold Time

Min

Max

Min

Max

Min

Max

Min

Max

125

100

200

110

150

100

ns
ns
ns

CONTROL SIGNAL TIMING
1 MHz
Symbol
tSYS
tRDS
tSOS
tiS
tNMI

Parameter
SYNC Delay
ROY Setup Time
-SO Setup Time
-IRQ,-RES Setup Time
-NMI Setup Time

75
200
200

2MHz

3 MHz

4 MHz
Units
ns
ns
ns
ns
ns

Notes:
1. VL65NC02 minimum operating frequency is limited by 02 low pulse width. The processor can be stopped with 02 held high.

237

VLSI TECHNOLOGY, INC
VL65NC02

ABSOLUTE MAXIMUM RATINGS
Ambient Operating Temperature:
O°C to +70°C
- Commercial
- Industrial
-40°C to +85°C
Storage Temperature
Supply Voltage to
Ground Potential

-65°C to +150°C

-0.3 to +7.0 V

Applied Output
Voltage

-0.3 to VCC + 0.3 V

Applied Input
Voltage

-0.3 to VCC + 0.3 V

DC CHARACTERISTICS:
Symbol

=O°C to +70°C, VCC =+50 V ± 5% (Notes 1, 2, 3)

Parameter
00 (IN)

VIH

VIL

operational sections of this specification
is not implied and exposure to absolute
maximum rating conditions for extended
periods may affect device reliability.

Min

Typ

Max

Units

2.4

VCC+ 0.3

+ 0.4

+ 0.8

1.0

-50

Input High Voltage
All Other Inputs

2.0

00 (IN)

-0.3

All Other Inputs

-0.3

Input Low Voltage
00 (IN)

Test Conditions

VIN ... 0 Vto +5.25 V
VCC .. 0 V

liN

Input Leakage
CUrrent

ITSI

Three-State (Off-State) Input Current
07 - DO

VIN = 0.4 V to +2.4 V
VCC-+5.25 V

VOH

Output High Voltage
SYNC. 07-00. A15-AO. RI-W. 01. 02

2.4

VCC =+4.75 V
ILOAO .. -100 ~

VOL

Output Low Voltage
SYNC. 07-00. A15-AO. RI-W. 01. 02

+0.4

VCC -+4.75 V
ILOAO -1.6 ~

2.0

VCC =+5.0 V

Active (5)

2.6

rnA/MHz

Active (6)

Low Power

1.1

rnA/MHz

-NMI. -IRQ. ROY.
-RES.-SO

Standby (4)
ICC

Supply Current

....NMI.-IRQ.-SO. ROY
CIN

Input Capacitance
00 (IN)

CIO

110 Capacitance - 07-00. 01.02

COUT

Output Capacitance - A 15-AOPJ-W. SYNC

Notes:
(1) All units are direct current (DC).
(2) A negative sign indicates outward current flow. positive indicates inward flow.
(3) -IRQ and -NMI require an external pull-up resistor.
(4) Typical values are shown for VCC ... +5.0 V and TA .. +25°C.
(5) Typical value for power estimation only; dependent on frequency of operation.
(6) Maximum value for power consumption; independent of frequency of operation.

238

ROY - 0 V
VCC = +5.0 V.
VIN =0 V.
f .. 1 MHz.
TA _ 25°C

VLSI TECHNOLOGY, INC.
VL6522 • VL65C22 • VL65C22V
PARALLEL INTERFACEITIMER

FEATURES

DESCRIPTION

• Low power consuming CMOS
parallel interface/timer
-VL65C22 has active pull-ups on
Port "8"
-VL65C22V has resistive pull-ups
on Port "8"

• Programmable Data Direction
Registers

The VL65221VL65C221VL65C22V are
flexible I/O devices for use with the
65XX family of processors. The
VL65C221VL65C22V are CMOS
implementations of the VL6522 device.
All include functions for programmed
control of up to two peripheral devices
(Ports A and B). Two program-controlled a-bit bidirectional peripheral I/O
ports allow direct interfacing between
the microprocessor and selected
peripheral devices. Two programmable
Data Direction Registers (A and B)
allow selection of data direction (input
versus output) on an individualline-by-

PIN DIAGRAM

BLOCKDIAGRAM

• Low cost HMOS parallel interface/
timer (VL6522)
• Two a-bit bidirectional I/O ports
• Two 16-bit timer/counters
• Serial bidirectional peripheral I/O port

line basis. Also provided are two programmable 16-bit counter/timers with
latches. Timer 1 may be operated in a
one-shot interrupt mode with interrupts
on each count-to-zero, or in a freerunning mode with a series of evenly
spaced interrupts. Timer 2 functions
both as an interval and pulse counter.
Serial data transfers are provided by a
shift register. Application versatility is
further increased by various control
registers, including an interrupt flag
register, an interrupt enable register,
and two function control registers.

r-------____-------..

-IRQ

PORTA
REGISTERS

VL6522
VL65C22
VL65C22V

PORTA

GND
PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
CB1
CB2
VCC

CA1
CA2
RSO
RS1
RS2
RS3
-RES

DATA

BUS

r--::-:-1+------ CAl

1 + - - - - - + CA2

-IRES

01
02
03

RI-W

02
CSl
-CS2
RSO
RSl

RS2

RS3

PORTB

02
CS1
-CS2

R/-W
-IRO

ORDER INFORMATION
Part
Number

Technology

Clock
Frequency

Package

Plastic DIP
VL6522-01 PC
HMOS
1 MHz
Plastic Leaded
VL6522-010C
HMOS
Plastic DIP
VL6522-02PC
HMOS
Plastic DIP
VL65C22-02PC
CMOS
Plastic DIP
VL65C22V -02PC CMOS
2MHz
VL6522-020C
Plastic Leaded
HMOS
Plastic Leaded
VL65C22-020C
CMOS
Plastic Leaded
VL65C22V-020C CMOS
Plastic DIP
VL65C22-04PC
CMOS
Plastic DIP
VL65C22V-04PC CMOS
4MHz
Plastic Leaded
VL65C22-040C
CMOS
Plastic Leaded
VL65C22V-040C CMOS
Note: Operating temperature range IS O°C to +70°C

Chip Carrier (PLCC)

Chip Carrier (PLCC)
Chip Carrier (PLCC)
Chio Carrier (PLCC)

Chip Carrier (PLCC)
Chip Carrier (PLCC)

VLSI TECHNOLOGY, INC.
VL6522 • VL65C22 • VL65C22V

PIN DIAGRAM
VL6522
VL65C22
VL65C22V

PAS
PA6
PA7
PBO

RS3

N.C.

N.C.
PB1
PB2
PB3
PB4
PB5
PB6

37
36
35
34

-RES

N.C.

32
31
30

03
04
05

DO
01
02

18 19 20 21 22 23 24 25 26 27 28

FIGURE 1. MICROPROCESSOR AND PERIPHERAL INTERFACE

DO-D7

PAo-PA7

02 - - - + I
Rl-W _ _- . .

MICROPROCESSOR
BUS INTERFACE
RSo-RS3 ------+I

VL6522
VL65C22
VL65C22V

1+--'" CA1
1+-_'" CA2
14---+

PERIPHERAL
INTERFACE

CB1

. . . - _. . . CB2

-RES ------+I
-IRQ

+----f

PBo-PB7

FUNCTIONAL DIFFERENCES AMONG VL6522, VL65C22, AND VL65C22V
Function

VL6522

VL65C22

VL65C22V

Are Decoded During -02

Are Decoded During -02
Only if -CS2 is an Active Low

CB1

Must Not Change During Last
100 ns of-02

Can Change Anytime, But is
Sampled Only During -02

Port B (PBO - PB7,
CB1, CB2)

Has Active (Transistor)
Internal Pull-ups

Has Passive (Resistor, Approx.
6 kohms) Internal Pull-ups

Port B (PBO - PB7,
CB1, CB2)

Each pin represents one Standard TTL load either as an input
or as an output

Each pin represents two Standard TTL loads either as an
input or as an output

Each pin represents one Standard TTL load either as an input
or as an output

VLSI TECHNOLOGY, INC.
VL6522 • VL65C22 • VL65C22V

SIGNAL
DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Description

-RES

AA low reset (-RES) input clears all VL65(C)22(V) internal registers to logic 0 (except T1
and T2 latches and counters and the Shift Register). This places all peripheral interface
lines in the input state; disables the timers, shift register, and interrupting from the chip.

The input clock is the system 02 clock and triggers all data transfers between processor
bus and the VL65(C)22(V).

RJ-W

The direction of the data transfers between the VL65(C)22(V) and the system processor
is controlled by the RJ-W line and the CS1 and --CS2 inputs. When RJ-W is low, (write
operation) and the VL65(C)22(V) is selected, data is transferred from the processor bus
into the selected VL65(C)22(V) register. When RJ-W is high, (read) and the chip is
selected, and data is transferred from the selected VL65(C)22(V) register to the CPU.

00-07

33-26

The eight bidirectional data bus lines transfer data between the VL65(C)22(V) and the
system processor bus. During ready cycles, the contents of the selected VL65(C)22(V)
register are placed on the data bus lines. During write cycles, these lines are highimpedance inputs and data is transferred from the processor bus into the selected
register. When the VL65(C)22(V) is not selected, the data bus lines are high-impedance.

CS1, -CS2

24,23

The two chip select inputs are normally connected to processor address lines either
directly or through decoding. The selected VL65(C)22(V) register is accessed when CS1
is high and --CS2 is low.

RSO, RS1, RS2,
RS3

38 -35

The coding of the four Register Select inputs selects one of the 16 internal registers of
the VL65(C)22(V), as shown in Table 2.

-IRQ

The Interrupt Request output goes low whenever an internal interrupt flag is set and the
corresponding interrupt enable bit is a logic 1. This output is open-drain to allow the
interrupt request signal to be wire-or'd with other equivalent signals in the system.

PAO - PA7

2-9

Port A consists of eight lines which can be individually programmed to act as inputs or
outputs under control of Data Direction Register A. The polarity of output pins is controlled by an Output Register and input data may be latched into an internal register
under control of CA 1 line. All modes of operation are controlled by the system processor
through the internal control registers. These lines, as inputs represent one standard
TTL load in the input mode and will drive one standard TTL load in the output mode.

PBO - PB7

10 - 17

Peripheral Data Port B is an 8-line, bidirectional bus, controlled by an Output Register,
Input Register and Data Direction Register similar to Data Port A. The output signal on
line PB7 may be controlled by Timer 1 while Timer 2 may be programmed to count
pulses on PB6 line. VL6522 and VL65C22 Port B lines are also capable of sourcing 3.0
mA at 1.5 VDC in the output mode. This allows the outputs to directly drive Darlington
transistor circuits. VL65C22V Port B lines have internal pull-up resistors (3 kn) to VCC.

CA1, CA2

40,39

Control Lines CA 1 and CA2 serve as interrupt inputs or handshake outputs for Peripheral Data Port A. Each line controls an internal Interrupt Flag with a corresponding
Interrupt Enable bit. CA 1 also controls the latching of Input Data on Port A. CA 1 is a
high impedance input, while CA2 represents one standard TTL load in the input mode.
In the output mode, CA2 will drive one standard TTL load.

CB1, CB2

18,19

Control lines CB1 and CB2 are interrupt inputs or handshake outputs for Peripheral Data
Port B. Like Port A, these two lines control an internal Interrupt Flag with a corresponding Interrupt Enable bit. These lines are also a serial data port under control of the Shift
Register (SR). Each control line represents two standard TTL loads in the input mode
(one TTL load on the VL65C22V) and can drive two TTL loads in the output mode (one
TTL load for the VL65C22V). CB1 and CB2 cannot drive Darlington transistor circuits.

VCC

+5 Volts

GND

Ground

VLSI TECHNOLOGY, INC.
VL6522 • VL65C22 • VL65C22V

FUNCTIONAL
DESCRIPTION
PERIPHERAL DATA PORTS
(PORT A, PORT B)
Each Peripheral Data Port operates in
conjunction with a Data Direction
Register (DORA or DORB). Under
program control, the Data Direction
Registers specify which lines within the
port bus are to be designated as inputs
or outputs. A logic 0 in any bit position
?f th.e register will cause the correspondIng line to serve as an input, while a
logic 1 will cause the line to serve as an
output.
When a line is programmed as an
?utP~t,. it is controlled by a correspondIng bit In the Output Register (ORA or
O~B). A logic 1 in the Output Register
Will cause the corresponding output line
to go high, while a logic 0 will cause the
line to go low. Under program control
d~ta is.~ritten into the Output Registe~
bit positions corresponding to the output
lines which have been programmed as
outputs. Should data be written into bit
positions corresponding to lines which
have been programmed as inputs, the
output lines will be unaffected.
When reading a Peripheral Data Port
the contents of the corresponding Input
Register (IRA or IRB) are transferred
onto the Data Bus. When the input
latching feature is disabled, Input
Register A (IRA) will reflect the logic
levels present on the Port A bus lines.
However, with input latching enabled
and the selected active transition on
CA 1 having occurred, Input Register A
will contain the data present on the Port
A bus lines at the time of the transition
In this case, once Input Register A has'
been read, it will appear transparent
reflecting the current state of the Port A
bus lines until the next CA1 latching
transition.
With respect to Input Register B, it
operates similar to Input Register A
except that for those Port B bus lines
which have been programmed as
outputs, there is a difference. When
reading Input Register A, the logic level
on the bus line determines whether a
log~ 1 or 0 is sensed. However, when
reading the Input Register B, the logic
level stored in Output Register B (ORB)
is the logic level sensed. For this
reason, those outputs which have large
loading effects may cause the reading of

Input Register A to result in the reading
of logic 0 when a 1 was actually
programmed, and reading a logic 1
when a 0 was programmed. However,
when reading Input Register B, the logic
level read will be correct, regardless of
loading on the particular bus line.
For information on formats and
operation of the Peripheral Data Port
registers, refer to Figures 14, 15, 16,
and 17. It should be noted that the
input latching modes are controlled by
the Auxiliary Control Register.
DATA TRANSFER· HANDSHAKE
CONTROL
~ ~we~.ul feature of the Vl65(C)22(V)
IS its ability to provide absolute control
over data transfers between the
microprocessor and peripheral devices.
This control is accomplished by way of
Rhandshake Rlines. Port A lines (CA 1,
CA2) handshake data transfers on both
~ead and Write operations, while Port B
lines (CB1, C82) handshake data on
Write operations only.
READ HANDSHAKE CONTROL
Read Handshaking provides effective
control of data transfers from a peripheral device to the microprocessor. To
accomplish the Read Handshake the
peripheral device generates a Data
Ready signal to the Vl65(C)22(V) which
indicates valid data is present on the
Peripheral Data Port bus. In most
cases, this Data Ready signal will
interrupt the microprocessor, which will
then read the data and generate a Data
Taken signal. Once the peripheral
s~nses the Data Taken signal, new data
Will be placed on the bus. This process
continues until the data transfer is
complete.
Automatic Read Handshaking applies to
Peripheral Data Port A only. The Data
Ready signal is transmitted by the
~eriphe~al device over the CA1 interrupt
line, while the Data Taken signal is
generated and transmitted to the
peripheral device over the CA2 line.
When the Data Ready signal is received, it sets an internal flag in the
Interrupt Flag Register (IFR). This flag
may interrupt the microprocessor or it
may be polled under program control.
As an option, the Data Taken signal
may be either a pulse or a level. In

either case, it is set low (logic 0) by the
microprocessor and is cleared by the
next Data Ready signal. Refer to
Figures 2 and 3 for Read Handshake
timing and operating sequence.
WRITE HANDSHAKE CONTROL
The Write Handshake operation is
similar to Read Handshaking. For Write
Handshaking, however, the
Vl65(C)22(V) generates the Data
Ready signal and the peripheral device
must generate the Data Taken return
signal. Note that Write Handshaking
may occur on both Data Ports (A and
B). For a Write Handshake, CA2 or
CB2 serve as the Data Ready output
and can operate in either the Handshake Mode or the Pulse Mode. The
Data Taken signal is received by CA1
or CB1. The Data Taken signal sets a
flag in the Interrupt Flag Register and
clears the Data Ready output signal.
Note that the selection of Read or Write
Handshake operating modes (CA 1,
CA2, C81, and C82) is accomplished
by the Peripheral Control Register
(PCR).
INTERRUPT OPERATION
There are three basic operations
including: setting the flag within the
Interrupt Flag Register (IFR), enabling
the interrupt by way of a corresponding
bit in the Interrupt Enable Register
(IER), and signaling the microprocessor
with an Interrupt Request (IRO). An
Interrupt Flag can be set by conditions
Internal to the chip or by inputs to the
chip from external sources. Normally,
an Interrupt Flag remains set until the
interrupt is serviced. To determine the
source of an interrupt, the microprocessor must examine each flag in
order, from highest to lowest priority.
This is accomplished by reading the
contents of the Interrupt Flag Register
into the microprocessor accumulator
shifting the contents either left or right
and then using conditional branch
instructions to detect an active interrupt.
Each Interrupt Flag has a corresponding Interrupt Enable bit in the Interrupt
Enable Register. The enable bits are
controlled by the microprocessor (set or
reset). If an Interrupt Flag is high (logic
1), and the corresponding Interrupt
Enable bit is high (logic 1), the Interrupt
Request (IRO) will go low (logic O).

VLSI TECHNOLOGY, INC.
VL6522 • VL65C22 • VL65C22V

FUNCTIONAL
DESCRIPTION

(Cant.)

IRQ is an open-collector output which
can be wire-or'd with other devices
within the system.
All Interrupt Flags are contained within
a single Interrupt Flag Register. Bit 7 of
this register will be high (Logic 1)
whenever an Interrupt Flag is set, thus
allowing convenient polling of several
devices within a system to determine
the source of the interrupt.
The Interrupt Flag Register (IFR) and
Interrupt Enable Register (IER) format
and operation is shown in Figures 28
and .29 respectively. The Interrupt Flag
R~glster may be read directly by the
mlcrprocessor, and individual flag bits
may be cleared by Writing a "1" into the
appropriate bit of the IFA. Bit 7 of the
IFR indicates the status of the Interrupt
Request (IRQ) output. Bit 7 corresponds to the following logic function:
IRQ .. IFR6 x IER6 + IFR5 x IER5 +
IFR4 x IER4 + IFR3 x IER3 + IFR2 x
IER2 + IFR1 x IER1 + IFRO x IERO.
Note x .. LogicAND, + = LogicOR.
Bit 7 is not a flag. For this reason bit 7
is not directly cleared by writing a '"1 "
into its bit position. It can be cleared
however, by clearing all the flags within
the register, or by disabling all active
interrupts in the next section.
TIMER OPERATION
Timer 1 Operation - Interval Timer T1
consists of two 8-bit latches and a 16-bit
counter. The latches serve to store
data which is to be loaded into the
counter. Once the counter is loaded
under program control, it decrements at
a Phase 2 (02) clock rate. Upon
reac~ing zero, an Interrupt Flag is set,
causing Interrupt Request (IRQ) to go
low (Logic 0) if the corresponding
Interrupt Enable bit is set. Once the
Timer reaches a count of zero, it will
either disable any further interrupts
(provided it has been programmed to do
so), or it will automatically transfer the
contents of the latches into the counter
and proceed to decrement again. The
counter may be programmed to invert
the output signal on PB7 each time it
reaches a count of zero. Additional
control bits are provided in the Auxiliary
Control Register (bits 6 and 7) to allow
selection of Timer 1 operating modes.

It should be noted that the microprocessor does not write directly il1to the loworder counter (T1 Col). Instead, this half
of the counter is loaded automatically
from the low-order register when the
microprocessor writes into the highorder register and counter. In fact, it
may not be necessary to write to the
low-order register in some applications
since the timing operation is triggered
by writing to the high-order register and
counter.
Timer 1 One-Shot Mode - Interval Timer
T1 may operate in the One-Shot Mode
which allows the generation of a single
Interrupt Flag each time the Timer is
loaded. The Timer can also be programmed to produce a single negative
pulse on Data Port Line PB7.
To generate a single interrupt, it is
required that bits 6 and 7 of the
Auxiliary Control Register be low (Logic
0). The low-order 11 counter (11 Col)
or the low-order T1 latch (T1 L-L) must
then be loaded with the low-order count
value. Note that a load to 11 Col is
effectively a load to T1 L-L Next, the
high-order count value must be loaded
into t~e hi.gh-order T1 counter (11 C-H),
at which time the value is simultaneously loaded into high-order 11 latch
(T1 L-H). During this load sequence, the
contents of T1 L-L is transferred to 11 CL The counter will start counting down
on the next 02 clock following the load
sequence into T1 C-H, and will decrement at the 02 clock rate. Once the T1
counter reaches a zero count, the
Interrupt Flag is set. To generate a
negative pulse on Data Port line PB7
the sequence is identical to the abov~
except bit 7 of the Auxiliary Control
Register must be high (Logic 1). Data
Port line PB7 will then go low (Logic 0)
following the load to T1 C-H, and will go
high (Logic 1) again when the counter
reaches a zero count. Once set, the T1
Interrupt Flag is reset by either loading
T1 C-H, which starts a new count, or by
reading T1 CoL.
Timer 1 Free-Run Mode - An important
advantage within the VL65C22 is the
ability of the latches associated with the
T1 counter to provide a continuous
series of evenly spaced interrupts or a
square wave on Data Port line PB7. It

243

should also be noted that the continuous series of interrupts and square
waves are not affected by variations in
the microprocessor interrupt response
time. These advantages are all
produced in the Free-Run Mode~. When
operating in the Free-Run Mode, the
Interrupt Flag is set and the signal on
PB7 is inverted each time the counter
reaches a count of zero. In the FreeRun Mode., however, the counter does
not continue to decrement after
reaching a zero count. Instead, the
counter automatically transfers the
contents of the latch into the counter
(16 bits) and then decrements from the
new count value. As can be seen, it is
not necessary to reload the timer in
order to set the Interrupt Flag on the
next count of zero. When set, the
Interrupt Flag can be cleared by either
reading T1 Col, by writing directly into
the Interrupt Fig Register (IFR) as will
be discussed later, or by a load into
11 C-H when a new count value is
desired.
Since the interval timers are all ret riggerable, reloading the counter will
always reinitialize the time-out period.
Should the microprocessor continue to
reload the counter before it reaches
zero, counter time-out can be prevented. Timer 1 is able to operate in
this manner provided the microprocessor writes into the high-order counter
(T1 C-H). By loading the latches only,
the microprocessor can access the
timer during each count-down operation
without affecting the time-out in
progress. In this way, data loaded into
the latches will determine the length of
the next subsequent time-out period.
This capability is of value in the FreeRun Mode with the output enabled. In
the Free-Run Mode, the signal on Data
Port line PB7 is inverted and the
Interrupt Flag is set with each counter
time-out. When the microprocessor
responds to the interrupts with new data
for the latches, it can determine the
period of the next half-cycle during each
half-cycle of the output signal on line
PB7. In this way, complex waveforms
can be generated.
Timer 2 Operation - Timer 2 operates in
the One-Shot Mode only (as an interval
timer), or as a pulse counter for

VLSI TECHNOLOGY, INC.
VL6522 • VL65C22 • VL65C22V

FUNCTIONAL
DESCRIPTION (Cant.)
counting negative pulses on Data Port
line PBS. A single control bit within the
Auxiliary Control Register is used to
select between these two modes. Timer
2 is made up of a write-only low-order
latch (T2L-L), a read-only low-order
counter (T2C-L), and a readlwrite highorder counter (T2C-H). This 1G-bit
counter decrements at a 02 clock rate.
Timer 2 One-Shot Mode - Operation of
Timer 2 in the One-Shot Mode is similar
to Timer 1. That is, for each load T2C-H
operation, Timer 2 sets the Interrupt
Flag for each countdown to zero.
However, after a time-out, the T2
counters roll over to all 1's (FFF1G) and
continue to decrement. This two's
complement decrement allows the user
to determine how long the T2 Interrupt
Flag has been set. Since the Interrupt
Flag logic is disabled after the initial
interrupt set (zero count), further
interrupts cannot be set by a subsequent count to zero. To enable the
Interrupt Flag logic, the microprocessor
must reload T2C-H. The Interrupt Flag
is cleared by either reading T2C-L or by
loading T2C-H.
Timer 2 Pulse Counting Mode-In the
Pulse Counting Mode, Timer 2 counts a
predetermined number of negativegoing pulses on Data Port line PBS. To
accomplish this, a count number is
loaded into T2C-H, which clears the
Interrupt Flag logic and starts the
counter to decrement each time a
negative pulse is applied to Data Port
line PBG. When the T2 counter reaches
a count of zero, the Interrupt Flag is set
and the counter continues to decrement
with each pulse on PBS. To enable the
Interrupt Flag for subsequent countdowns, it is necessary to reload T2C-H.
The decrement pulse on line PBG must
be low (Logic 0) during the leading edge
of the 02 clock.
SHIFT REGISTER OPERATION AND
MODES
Shift Register Operation - The Shift
Register performs bidirectional serial
data transfers on line CB2. These
transfers are controlled by an internal
modul0-8 counter. Shift pulses can be
applied to the CB 1 line for controlling
external devices. Each Shift Register

operating mode is controlled by control
bits within the Auxiliary Control Register.
Shift Register Input Modes - Shift
Register Disabled (000) - In the 000
mode, the Shift Register is disabled from
all operation. the microprocessor can
read or write the Shift Register, but
shifting is disabled and both CB1 and
CB2 are controlled by bits in the
Peripheral Control Register (PCR). The
Shift Register Interrupt Flag is held low
(disabled).
Shift In - Counter T2 Control (001) - In
this mode, the shifting rate is controlled
by the low order eight bits of counter T2.
Shift pulses are generated on the CB1
line to control shifting in external
devices. The time between transitions
of the CB1 output clock is determined by
the 02 clock period and the contents of
the low-order T2 latch (N). Shifting
occurs by writing or reading the Shift
Register. Data is shifted into the loworder bit first, and is then shifted into the
next higher order bit on the negativegoing edge of each clock pulse. Input
data should change before the positivegoing edge of the CB1 clock pulse. This
data is then shifted into the Shift
Register during the 02 clock cycle
following the positive-going edge of the
CB1 clock pulse. After eight CB1 clock
pulses, the Shift Register Interrupt Flag
will set the IRQ will go low (Logic 0).
Shift In - 02 Clock Control (010) - In this
mode, the shift rate is controlled by the
02 clock frequency. Shift pulses are
generated on the CB1 line to control
shifting in external devices. Timer 2
operates as an independent interval
timer and has no influence on the Shift
Register. Shifting occurs by reading or
writing the Shift Register. Data is shifted
into the low order bit first, and is then
shifted into the next higher order bit on
the trailing edge of the 02 clock pulse.
After eight clock pulses, the Shift
Register Interrupt Flag will be set and
output clock pulses on the CB1 line will
stop.
Shift In - External CB1 Clock Control
(011) - In this mode, CB1 serves as an
input to the Shift Register. In this way,
an external device can load the Shift
Register at its own pace. The Shift
Register counter will interrupt the

244

microprocessor after each eight bits
have been shifted in. The Shift
Register counter does not stop the
shifting operation. Its function is simply
that of a pulse counter. Reading or
writing the Shift Register resets the
Interrupt Flag and initializes the counter
to count another eight pUlses. Note that
data is shifted during the first 02 clock
cycle following the positive-going edge
of the CB1 shift pulse. For this reason,
data must be held stable during the first
full cycle following CB1 going high.
Shift Out - Free Running at T2 Rate
(100) -This mode is similar to mode 101
in which the shifting rate is determined
by T2. However, in mode 100 the Shift
Register Counter does not stop the
shifting operation. Since Shift Register
bit 7 (SR7) is recirculated back into bit
0, the eight bits loaded into the Shift
Register will be clocked onto the CR2
line repetitively. In this mode, the Shift
Register Counter is disabled and IRQ is
never set.
Shift Out - T2 Control (101) - In this
mode, the shift rate is controlled by T2
(as in mode 100). However, with each
read or write of the Shift Register, the
Shift Register Counter is reset and eight
bits are shifted onto the CB2 line. At
the same time, eight shift pulses are
placed on the CB1 line to control
shifting in external devices. After the
eight shift pulses, the shifting is
disabled, the Interrupt Flag is set, and
CB2 will remain at the last data level.
Shift Out - 02 Clock Control (110) - In
this mode, the shift rate is controlled by
the system 02 Clock.
Shift Out - External CB1 Clock Control
(111) - In this mode, shifting is controlled by external pulses applied to the
CB1 line. The Shift Register Counter
sets the Interrupt Flag for each eightpulse count, but does not disable the
shifting function. Each time the
microprocessor reads or writes to the
Shift Register, the Interrupt Flag is reset
and the counter is initialized to begin
counting the next eight pulses on the
CB1 line. After eight shift pulses, the
Interrupt Flag is set. The microprocessor can then load the Shift Register with
the next eight bits of data.

VLSI TECHNOLOGY, INC.
VL6522 • VL65C22 • VL65C22V

TABLE 1. PERIPHERAL INTERFACE CHARACTERISTICS
Symbol
tR,tF

Parameter
Rise and Fall Time for CA 1, CB 1, CA2 and CB2 Input Signals

tCA2

Delay Time, Clock Negative Transition to CA2 Negative

TA=O°Cto70°C,VCC=5V±5%

Min

Typ

Max

Unit

1.0

2.0

Il s

0.05

1.0

0.20

1.5

1.0

2.0

Transition (Read Handshake or Pulse Mode)
tRS1

Delay Time, Clock Negative Transition to CA2 Positive
Transition JPulse Model

tRS2

Delay Time, CA 1 Active Transition to CA2 Positive Transition
(Handshake Mode)

tWHS

Delay Time, Clock Positive Transition to CA2 or CB2 Negative
Transition (Write Handshake)

tDS

Delay Time, Peripheral Data Valid to CB2 Negative Transition

tRS3

Delay Time, Clock Positive Transition to CA2 or CB2 Positive
Transition (Pulse Mode)

tRS4

Delay Time, CA1 or CB1 Active Transition to CA2 or CB2
Positive Transition (Handshake Mode)

t21

Delay Time Required from CA2 Output to CA 1 Active

400

300

Transition (Handshake Mode)
tiL

Set-up Time, Peripheral Data Valid to CA1 or CB1 Active
Transition (Input Latching)

tSR1

Shift-Out Delay Time - Time from 02 Falling Edge to CB2

300

Data Out
tSR2

Shift-In Set-up Time - Time from CB2 Data In to 02 Rising Edge

300*

tSR3

External Shift Clock (CB1) Set-up Time Relative to 02

100

ns
tCYC

Trailing Edge
tlPW

Pulse Width - PB6 Input Pulse

2 x tCYC

tlCW

Pulse Width - CB1 Input Clock

2x tCYC

tiPS

Pulse Spacing - PB6 Input Pulse

2 xtCYC

tiCS

Pulse Spacing - CB1 Input Pulse

2 xtCYC

tAL

CA 1, CB1 Set Up Prior to Transition to Arm Latch

300

tPDH

Peripheral Data Hold After CA 1, CB 1 Transition

150

*Note: This specification is "0" (zero) on the VL65C22V.

245

VLSI TECHNOLOGY, INC.
VL6522 • VL65C22- • VL65C22V

FIGURE 2. TIMING FOR READ HANDSHAKE, PULSE MODE

CA2
"DATA TAKEN"

tCA2

tRS1

FIGURE 3. TIMING FOR READ HANDSHAKE, HANDSHAKE MODE

--------------~,~/-----------------CA2
"DATA TAKEN"
tCA2

J'-O-.S-V------7';~/~------)1-----tR-:-:~

CA1
--------------------------------------~;:~-----"DATA READY"
~ __
--------------------------------------~;

20'.OSVV

~~~---ACTIVE
TRANSITION

FIGURE 4. TIMING FOR WRITE HANDSHAKE, PULSE MODE

"'------t "'------t
Wi

WRITE ORA,ORB
OPERATION
,,----------------...

CA2,CB2
"DATA READY"

tWHS

,,'---

tRS3

o.SV
tDS - - - - - -.....

PA, PB - - - - - - - - - - - - - - - - - _
P
ERIPHERAL2
DATA
' . O V__________________________________
~._~O~.S~V

246

VLSI TECHNOLOGY, INC.
VL6522 • VL65C22 • VL65C22V

FIGURE 5. TIMING FOR WRITE HANDSHAKE, HANDSHAKE MODE

02
WRITE ORA, ORB
OPERATION

CA2
"DATA READY"
tOs ---i"
PA,PB
PERIPHERAL
DATA
- - - - - - - - - - - - - - - - - - - ,~~----------~~~~~------------+--

;~12 (IN)

Phase 2 In Clock

RES

Reset

4>1 (OUT)

Phase 1 Out Clock

RIW

Read/Write

4>2 (OUT)

Phase 2 Out Clock

Set Overflow

00-07

Data Bus

SYNC

Synchronize

DO/BAO-D7IBA7

Data Bus, Multiplexed

VDA

Valid Data Address

Emulation Select

Vector Pull

IRQ

Interrupt Request

VPA

Valid Program Address

Memory Lock

Voo

Positive Power Supply (+5 Volts)

M/X

Mode Select (PM or Px)

Vss

Internal Logic Ground

262

VLSI TECHNOLOGY, INC.
VL65C816

TABLE 1. COMPATIBILITY ISSUES
65C816

65C02

NMOS 6502

1. S (Stack)

Always page 1 (E = 1),8 bits
16 bits when (E = 0).

Always page I, 8 bits

2. X (X Index Register)

Indexed page zero always in
page 0 (E = I),
Cross page (E = 0).

Always page 0

Indexed page zero always in
page 0 (E = I),
Cross page (E = 0).

Always page 0

4. A (Accumulator)

8 bits (M = I), 16 bits (M'= 0)

8 bits

5. P (Flag Registor)

N, V, and Z flags valid in
decimal mode.
o = 0 after reset or interrupt.

N, V, and Z flags valid in
decimal mode.
o = 0 after reset and
interrupt.

N, V, and Z flags invalid
in decimal mode.
o = unknown after reset.
o not modified after interrupt

7 cycles

6 cycles

7 cycles

5 cycles

6 cycles

5 cycles and invalid page
crossing

4 cycles (E = 1)
3 cycles (E = 0)

4 cycles

No additional cycle

Add 1 cycle

OOFFFE,F (E = I~K bit = 0
on stack if IRQ, NMI, ABORT.
00FFE6, 7 (E = 0) X = X on
Stack always.

F~FJill..K

3. Y (Y Index Register)

6. Timing
A. ABS, X ASL, LSR, ROL,
ROR With No Page Crossing
B. Jump Indirect
Operand = XXFF
C. Branch Across Page
D. Decimal Mode
7. BRK Vector

No additional cycle
bit = 0 on stack

iflRQ,NMI.

FffE.FJill.K bit = 0 on stack
iflRQ,NMI.

8. Interrupt or Break
Bank Address

PBR not pushed (E = 1)
RTI PBR not pulled (E = 1)
PBR pushed (E = 0)
RTI PBR pulled (E = 0)

Not available

9. Memory Lock (ML)

ML = 0 during Read, Modify and
Write cycles.

ML = 0 during Modify and Write.

Not available

10. Indexed Across Page
Boundary (d),y; a,x; a,y

Extra read of invalid address.

Extra read of last instruction
fetch.

Extra read of invalid address.

11. ROY Pulled During Write
Cycle.

Processor stops

Ignored

12. WAI and STP Instructions.

Available

Not available

13. Unused OP Codes

One reserved OP Code specified
as WDM will be used in future
systems. The 65C816 performs
a no-operation.

No operation

Unknown and some "hang
up" processor.

14. Bank Address Handling

PBR = 00 after reset or interrupts.

Not available

15. R/W During Read-ModifyWrite Instructions

E = I, R/W = 0 during Modify and

R/W = 0 only during Write cycle

R/W = 0 during Modify and
Write cycles.

Writecy~s.

E = 0, R/W = 0 only during
Write cycle.
16. Pin 7

VPA

SYNC

17. COP Instruction
Signatures 00-7F user defined
Signatures 80-FF reserved

Available

Not available

263

VLSI TECHNOLOGY, INC.
VL65C816

TABLE 2. INSTRUCTION SET - ALPHABETICAL SEQUENCE
ADC
AND
ASL
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRA
BRK
BRL
BVC
BVS
CLC
CLD
CLI
CLV
CMP
COP
CPX
CPY
DEC
DEX
DEY
EOR
INC
INX
INY
JML
JMP
JSL
JSR
LDA
LDX
LDY
LSR
MVN
MVP
NOP
ORA
PEA
PEl
PER

Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift One Bit Left, Memory or Accumulator
Branch on Carry Clear (Pc =0)
Branch on Carry Set (Pc = 1)
Branch if Equal (pz = 1)
Bit Test
Branch if Result Minus (PN = 1)
Branch if Not Equal (pz = 0)
Branch if Result Plus (PN = 0)
Branch Always
Force Break
Branch Always Long
Branch on Overflow Clear (Pv = 0)
Branch on Overflow Set (Pv =1)
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Coprocessor
Compare Memory and Index X
Compare Memory and Index Y
Decrement Memory or Accumulator by One
Decrement Index X by One
Decrement Index Y by One
"Exclusive OR" Memory with Accumulator
Increment Memory or Accumulator by One
Increment Index X by One
Increment Index Y by One
Jump Long
Jump to New Location
Jump Subroutine Long
Jump to New Location Saving Return Address
Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or Accumulator)
Block Move Negative
Block Move Positive
No Operation
"OR" Memory with Accumulator
Push Effective Absolute Address on Stack (or Push Immediate
Data on Stack)
Push Effective Indirect Address on Stack (or Push Direct
Data on Stack)
Push Effective Program Counter Relative Address on Stack

PHA
PHB
PHD
PHK
PHP
PHX
PHY
PLA
PLB
PLD
PLP
PLX
PLY
REP
ROL
ROR
RTI
RTL
RTS
SBC
SEC
SED
SEI
SEP
STA
STP
STX
STY
STZ
TAX
TAY
TCD
TCS
TDC
TRB
TSB
TSC
TSX
TXA
TXS
TXY
TYA
TYX
WAI
WDM
XBA
XCE

Push Accumulator on Stack
Push Data Bank Register on Stack
Push Direct Register on Stack
Push Program Bank Register on Stack
Push Processor Status on Stack
Push Index X on Stack
Push Index Y on Stack
Pull Accumulator from Stack
Pull Data Bank Register from Stack
Pull Direct Register from Stack
Pull Processor Status from Stack
Pull Index X from Stack
Pull Index Y form Stack
Reset Status Bits
Rotate One Bit Left (Memory or Accumulator)
Rotate One Bit Right (Memory or Accumulator)
Return from Interrupt
Return f.rom Subroutine Long
Return from Subroutine
Subtract Memory from Accumulator with Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Processor Status Bite
Store Accumulator in Memory
Stop the Clock
Store Index X in Memory
Store Index Y in Memory
Store Zero in Memory
Transfer Accumulator to Index X
Transfer Accumulator to Index Y
Transfer C Accumulator to Direct Register
Transfer C Accumulator to Stack Pointer Register
Transfer Direct Register to C Accumulator
Test and Reset Bit
Test and Set Bit
Transfer Stack Pointer Register to C Accumulator
Transfer Stack Pointer Register to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Pointer Register
Transfer Index X to Index Y
Transfer Index Y to Accumulator
Transfer Index Y to Index X
Wait for Interrupt
Reserved for Future Use
Exchange B and A Accumulator
Exchange Carry and Emulation Bits

For alternate mnemonics, see Table 7.

TABLE 3. VECTOR LOCATIONS
E=1

E=Q

OOFFFE,F -IRQ/BRK
OOFFFC,D-RESET
OOFFFA,B -NMI
OOFFF8,9 -ABORT
OOFFF6,7 -(Reserved)
OOFFF4,5 -COP

Hardware/Software
Hardware
Hardware
Hardware
Software

OOFFEE,F -IRQ

Hardware

OOFFEC,D-~erved)

OOFFEA,B-NMI
OOFFE8,9 -ABORT
OOFFE6,7 -BRK
OOFFE4,5 -COP

The VP output is low during the two cycles used for vector location access.
When an interrupt is executed, D = 0 and I =1 in Status Register P.

264

Hardware
Hardware
Software
Software

VLSI TECHNOLOGY, INC.
VL65C816

TABLE 4. OPCODE MATRIX
M
S
0

M
S
0

loSD

BRKs
2 8

ORA (d,x)
2 6

COPs
2 *8

ORA d,s
2*4

TSBd
2-5

ORAd
2 3

ASLd
2 5

ORA[d]
2*6

PHPs
1 3

ORA#
2 2

BPLr
2 2

ORA (d},Y ORA (d) OR:~d7S},Y
2-5
2 5

TRBd
2-5

AND (d,x)
2 6

BITd
2 3

JSRa
2
3 6

JSLal
4* 8

AND d,s
2*4

ORAd,x ASL d,x
2 4
2 6
ANDd
2 3

ROLd
2 5

BMlr
2 2

AND (d},Y AND (d) AN~ ~d7S},Y
2-5
2 5

RTI s
1 7

EOR (d,x)
2 6

BVCr
2 2

EOR (d},y
2 5

RTSs
6
1 6

ADC (d,x)
2 6

BVSr
7
2 2

ADC (d},y ADC (d) AD~ ~d7S},y STZ d,x ADCd,x ROR d,x
2-5
2-4
2 5
2 4
2 6

BRAr
2-2

STA (d,x)
2 6

BCCr
9
2 2

STA (d},y
2 6

LDY#
A
2 2

LDA (d,x)
2 6

BCSr
2 2

LDA (d},y
2 5

CPY#
2 2

CMP (d,x)
2 6

WDM
2 *2

EOR d,s
2*4

BRLrl
3*3

ADCd,s
2*4

STAd,s
2*4

STA (d) ST~ ~;},y
2-5
LDX#
2 2

LDAd,s
2*4

LDA (d) LD~~7S},y
2-5
REP#
2*3

CMPd,s
2*4

BNEr
D
2 2

CMP (d},y CMP(d) CM: ~d7S},y
2-5
2 5

CPX#
E
2 2

SBC (d,x)
2 6

BEQr
2 2

SBC (d},y
2 5

symbol
#
A
r
rl
i

s
d
d,x
d,y
(d)
(d,x)
(d},y

SEP#
2*3

SBCd,s
2*4

SBC (d) SB~ ~d7S},y
2-5
2

TSBa
3-6

ORAa
3 4

ASLa
3 6

ORAal
4* 5

O~A.J~]'Y CLCi ORAa,y INCA TCSi

TRBa
3-6

ORA a,x ASL a,x ORA al,)
3 4
3 7
4*5

MVP xyc
3*7

EORd
2 3

LSRd
2 5

STZd
2-3

ADCd
2 3

STYd
2 3

STAd
2 3

RORd
2 5

STXd
2 3

STY d,x STAd,x STX d,Y
2 4
2 4
2 4
LDYd
2 3

LDAd
2 3

LDXd
2 3

LDY d,x LDAd,x LDX d,y
2 4
2 4
2 4
CPYd
2 3
PEl s
2*6
CPXd
2 3
PEAs
3* 5

CMPd
2 3

DECd
2 5

CMPd,x DEC d,x
2 4
2 6
SBCd
2 3

INCd
2 5

SBCd,x INCd,x
2 6
2 4

AND [d]
2*6

PLPs
1 4

BIT a
ROLA PLD s
1 2 1*5 . 3 4

LSRA PHKs
1 2 1*3

JMPa
3 3

E~R.J~)'Y

CLli
1 2

EOR a,Y PHYs TCDi
1 -3 1*2
3 4

JMPal
4*4

ADC[d)
2*6

PLA s
1 4

RORA RTLs
1 2 1 *6

JMP(a}
3 5

A~C.J~]'Y

SEI i
1 2

STAId]
2*6

DEYi
1 2

BIT#
2-2

S~AJ~'Y

TYAi
1 2

STAa,y
3 5

LDA[d]
2*6

TAYi
1 2

LDA#
2 2

L~AJ~'y

CLVi
1 2

LDAa,y
3 4

TSXi
1 2

CMP[d)
2*6

INYi
1 2

CMP#
2 2

DEXi WAli
1 2 1- 3

CPYa
3 4

CLDi CMPa,y PHXs STPi
1 2
3 4
1- 3 1- 3

JML (a)
3*6

NOPi XBAi
1 2 1*3

CPXa
3 4

C~P.J~)'y
SBC[d)
2 *6

SB2C.J~)'y
7

INXi
1 2

addressing mode
direct indirect long
direct indirect long indexed
absolute
absolute indexed (with x)
absolute indexed (with y)
absolute long
absolute long indexed
stack relative
stack relative indirect indexed
absolute indirect
absolute indexed indirect
block move

Op Code Matrix Legend
ADDRESSING
MODE
BASE
NO. CYCLES

265

EOR#
2 2

ADC#
2 2

ANDa
3 4

ANDal
4*5

AND a,x ROLa,x ANDal,)
3 7
3 4
4 *5

EORa
3 4

ROLa
3 6

LSR a
3 6

EORal
4* 5

EOR a,x LSR a,x EOR al,)
4*5
3 4
3 7
ADCa
3 4

RORa
3 6

ADCal
4*5

ADC a,Y PLY s TDCI JMP (a,x) ADC a,x RORa,x ADCal,)
3-6
4 *5
3 4
3 7
3 4
1 - 4 1 *2

SBC#
2 2

TXAi PHBs
1 2 1 *3

STY a
3 4

TXSi
1 2

TXYi
1 *2

STZa
3-4

TAXi PLB s
1 2 1*4

LDYa
3 4

TYXi
1 *2

LDYa,x
3 4

SEDi SBCa,y PLX s XCEi JSR (a,x)
3*6
1 2
3 4
1 - 4 1*2

[d)
[d),y
a
a,x
a,y
al
al,x
d,s
(d,s},y
(a)
(a,x)
xyc

BASE
NO. BYTES

1 *2

PHAs
1 3

symbol

65C8160pcodes
• = New 65C02 Opcoaes
Blank =NMOS 6502 Opcodes

AND#
2 2

1- 2

EOR [d)
2*6

immediate
accumulator
program counter relative
program counter relative long
implied
stack
direct
direct indexed (with x)
direct indexed (with y)
direct indirect
direct indexed indirect
direct indirect indexed

* =New

BITa,x
3 -4

addressing mode

INSTRUCTION
MNEMONIC

SECi AND a,Y DECA TSCi
1 -2 1 *2
3 4
1 2

BITd,x ANDd,x ROL d,x AN2D.J~).Y
2-4
2 4
2 6

EOR (d) EO~~d7S},Y MVN xyc EOR d,x LSR d,x
2 -5
3*7
2 4
2 6
PER s
3 *6

ASLA PHDs
1 2 1* 4

STAa
3 4

STXa
3 4.

STAal
4*5

STAa,x STZa,x STAal,x
3-5
4*5
3 5
LDAa
3 4

LDXa
3 4

LDAal
4*5

4
5
6
7
8

9
A

LDAa,x LDX a,y LDAal,x
4*5
3 4
3 4

CMPa
3 4

DEC a
3 6

CMPal
4*5

CMPa,x DECa,x CMPal,)
3 7
4*5
3 4
SBCa
3 4

INCa
3 6

SBCal
4*5

SBCa,x INCa,x SBCal,x
4*5
3 4
3 7

D
E

VLSI TECHNOLOGY, INC.
VL65C816
PROCESSOR
STATUS CODE
7 6 5 4 3 2 1 0

TABLES.
..

OPERATION

A+M+C-A
AIIM - A

BEQ
BIT
BMI
BNE
BPL

BRANCH IF Z = 1
MM (NOTE 1)
BRANCH IF N = 1
BRANCH IF Z = 0
BRANCH IF N = 0

BRA
BRK
BRL
BVC
BVS

BRANCH ALWAYS
BREAK (NOTE 2)
BRANCH LONG ALWAYS
BRANCH IF V = 0
BRANCH IF V =1

CLC
CLO
CLI
CLV
CMP
COP
CPX
CPY
DEC
OEX
DEY
EOR
INC
INX
INY

O-C

JML
JMP
JSL
JSR
LOA

JUMP LONG TO NEW LOC.
JUMP TO NEW LOC.
JUMP LONG TO SUB.
JUMPTO SUB.
M-A

4C 5C
22
20
A9 AD AF AS

LOX
LOY
LSR
MVN
MVP

M-X
M -Y

A2 AE
AO AC
4E

NOP
ORA
PEA

NO OPERATION
AVM - A
Mpc + 1, Mpc + 2- Ms-1, Ms

PEl

~RAN~Ui;~~1d
BRANCH IF C = 1

-0

[w't-:-:-Ji]-c

7
71
31

77 61
37 21

75
35
16

15 16 17 18

7D 7F 79
3D 3F 39
1E

19 20 21

72 67
32 27

89 2C

A - Ms, S-1 - S
OBR - Ms, S - 1 - S
0- Ms, Ms -1, S - 2 - S
PBR - Ms, S - 1 - S
P- Ms, S -1 - S

PHX
PHY
PLA
PLB
PLO

X - Ms, S -1 - S
Y - Ms, S -1 - S
S + 1 - S, Ms- A
S + 1 - S, Ms - OBR
S + 2 - S, Ms - 1, Ms - 0
S + 1- S, Ms- P
S + 1 - S, Ms- X
~+ 1-S, Ms- Y
MflP-P

SEC
SED
SEI
SEP
STA

DO OF 09

01 07 C1 05

C9 CD CF C5

02 C7

C3 D3

E4
C4
C6 3A

55
F6

50 SF 59
FE

N
N
N
N

CA
51

57 41

52 47

43 53

E8
C8
DC
6C

AVM-M
S-C
S-X
X-A
X-S

TXY
TYA
TYX
WAI
WOM

X-V
V-A
V-X
0- RDY
NO OPERATION (RESERVED)
B--A
C-E

Z C
Z C

Z
Z
Z

N
N
N
N
N

88
49 40 4F 45
EE
E6 1A

Z
Z
Z

7C
FC
B2 A7

B4
56

BO BF B9
BE
BC
5E

10 1F 19

12 07

B1 B7 A1 B5
B6

A6
A4
46 4A

A3 B3
N
N
54
44

Z
Z
Z C

EA
11

09 00 OF 05

17 01

F4
04
62

IDA
SA
68
AB
2B

N
N
N
N V M X 0
N

I~~
7A

~VM

C2
2E

26 2A

66 6A

~ V MX

40
6B
60
F1

E9 ED EF E5

F7 E1

FO FF F9

F2 E7

E3 F3

97 81

90 9F 99

Z C

ROR
RTI
RTL
RTS
SBC

~C*

SEC
SED
SEI
SEP
STA

83 93

STP
STX
STY
STZ
TAX
N
N
N

**
*

Z
Z

•

3B
BA
8A
9A

N
N
N

Z
Z
Z

9B
98
BB
CB
42

N
N
N

Z
Z
Z

EB
FB

Z .

*
*•
*

266

PER

PHX
PHY
PLA
PLB
PLO
PLP
PLX
PLY
REP
ROL

Z
Z
Z
Z C

A8
5B
1B
7B

A-Y
C-O
C-S
O-C

LOX
LOY
LSR
MVN
MVP
NOP
ORA
PEA

96
94
74

JML
JMP
JSL
JSR
LOA

PHA
PHB
PHD
PHK
PHP

DB
86
84

DEY
EOR
INC
INX
INY

PEl

8E
8C
9C

COP
CPX
CPY
DEC
DEX

*
*
*

38 '
F8
78
80 8F 85

BRA
BRK
BRL
BVC
BVS
CLC
CLD
CLI
CLV
CMP

Z C

02
EO EC
CO CC
CE

1-1

TSB
TSC
TSX
TXA
TXS

XBA
XCE

.01

50
70

1-C
1-0
MVP-P
A-M

BEQ
BIT
BMI
BNE
BPL

18
081
58
B8

tlliE:tP
RTRN FROM INT.

STOP (1- 4>2)
X-M
Y-M
00- M
A-X

AOC
AND
ASL
BCC
BCS

M,M.

Lc -

STP
STX
STY
STZ
TAX
TAY
TCO
TCS
TOC
TRB

Z C
Z.
Z C

~-C:J

RTRN FROM SUB. LONG
RTRN SUBROUTINE
A-M-C-A

MNEMONIC

Z C E= 0
Z C E= 1

30
DO
10

M(d), M(d + 1) - Ms - 1, Ms

PHA
PHB
PHD
PHK
PHP

N V
N
N

S -2 - S
Mpc + rl, Mpc + rl + 1 - Ms - 1, Ms
S-2-S

I
I

S -2 - S

ROR
RTI
RTL
RTS
SBC

63 73
23 33

M - M BACKWARD
M - MFORWARO

PER

PLP
PLX
PLY
REP
ROL

22 23 24

N V M X 0
N V 1 B 0

BO
FO

0-0
0-1
O-V
A-M
CO-PROCESSOR
X-M
Y-M
DECREMENT
X-1-X
Y-1 -Y
AVM-A
INCREMENTS
X +1-X
Y +1-Y

69 60 6F 65
29 20 2F 25
OE
06 OA

AOC
AND
ASL
BCC
BCS

't:

TAY
TCD
TCS
TOC
TRB
TSB
TSC
TSX
TXA
TXS
TXY
TYA
TYX
WAI
WOM
XBA
XCE

VLSI TECHNOLOGY, INC
VL65C816

TABLE 6. DETAILED INSTRUCTION OPERATION
CYCLE

ADDRESS MODE
1. Immediate It
(LDY,CPY,CPX,LDX,DRA,
AND,EOR,ADC,BIT,LDA, (1)(8)
CMP,SBC REP,SEP)
(14 Op Codes)
(2 and 3 byles)
12 and 3 cycles)

2a. Absolute I
IBIT,STY,STZ,LDY,
CPY,CPX,STX,LDX,
ORA,AND,EOR,ADC,
STA,LDA,CMP,SBC)
(18 Op Codes)
(3 bytes)
(4 and 5 cycles)
2b. Absolute (R-M-W)

(I)

IASL,ROL,LSR,ROR
DEC,INC,TSB,TRB)
(6 Op Codes)
(3 bytes)
(6 and 8 cycles)

(1)
(3)

II)

1
2.
2a

VP. iiL, YDA, YPA
I

1.
2.
3.
4.
4a.

I
I
I

I.
2.

I
I

3.
4.
4a.
5
6a.

I
I

o
o
I

2d. Absolute (Jump to
subroutine) _
(JSR)
(1 Op Code)
(3 bytes)
(6 cycles)
(different order from N6502)
*3a. Absolute Long al
(ORA,AND,EOR,ADC
STA,LDA,CMP,SBC)
(8 Op Codes)
(4 bytes)
(5 and 6 cycles)

I
I
I
I

2.
3
I.

I
I

3.
4.
5.
6.
I.

I
I

5.
Sa

I.
2.

3
4.

4b Direct IR-M-W) d
(ASL,ROL,LSR,ROR
DEC,INC,TSB,TRB)
16 Op Codes)
(2 bytes)
(5.6.7 and 8 cycles)

5.
6

(2)
(I)

8.
I.
I.
2.
2a.
3
3a

I
I

(2)
II)
(3)

I
I
I

I
I
I
I

4.
4a.
5.
Sa.

I
I

I.
2
2a.
3

I
I

I
I
I

4.
5.

I
I
I

Op Code
NEW PCL
NEWPCH
NEWBR
Op Code

PBR.PC
PBR,PC'1

I
I
I

I
I
I
I

PBR,PC
PBR,PC'1
PBR,PC'2
PBR,PC'3
NEW PBR,PC

I
I

I
2.
3.

2a.
3.

Op Code
AAL
AAH
AAB

I
I

PBR,PC
PBR,PC'1
PBR,PC'2
PBR,PC'3
AAB,AA
AAB,AA'1

1.
2.

I
I

I
I
I

Op Code
NEWPCL
NEWPCH
10
PCH
PCL
NextOpCode

0
0
0

I.
2

PBR,PC
PBR,PC'1
PBR,PC'2
PBR,PC'2
O,S
0,S-1
PBR,NEWPC

I
I
I

Sa.

8. Direct Indirect
Indexed Long [d)"
(ORA,AND,EOR,ADC,
STA,LDA,CMP,SBC)
18 Op Codes)
(2 bytes)
(6,7 and 8 cycles)

PBR,PC
PBR.PC·l
PBR,PC'1
0,0'00
0,0'00'1

PBR,PC
PBR,PC'1

PBR,PC
PBR,PC"
PBR,PC'1

Data Low

Data High

Op Code
NEWPCL
NEW PCH
PBR
10
NEWPBR
PCH
PCL
NextOp Code
Op Code
DO
10

(2)

9. Direct Indexed Indirect Id,.)
10RA,AND,EOR,ADC,
STA,LDA,CMP,SBC)
(2)
18 Op Codes)
(2 bytes)
16,7 and 8 cycles)
(I)
1/0
1/0

lOb. Direct,X(R-M-W) d,'
(ASL,ROL,LSR,ROR,
DEC,INC)
(6 Op Codes)
(2 bytes)
(6,7,8 and 9 cycles)

I 1. Direct, Y d"
(STX,LDX)
(2 Op Codes)
(2 bytes)
(4,5 and 6 cycles)
1/0

Data High

110

Op Code
10

(4)

(I)

lOa Direct,X d,'
IBIT,STZ,STY,LDY,
ORA,AND,EOR.ADC,
STA,LDA,CMP,SBC)
(II Op Codes)
(2 bytes)
(4,5 and 6 cycles)

12b. Absolute,X(R-M-W) a,x
(ASL,ROL,LSR,ROR,
DEC,INC)
(6 Op Codes)
(3 bytes)
(7 and 9 cycles)

* I 3. Absolute Long,X al,.
(ORA,AND,EOR,ADC,
STA,LDA,CMP,SBC)
(8 Op Codes)
(4 bytes)
(5 and 6 cycles)

Op Code
10

14. Absolute,Y I,Y
(LDX,ORA,AND,EOR,ADC,
STA,LDA,CMP,SBC)
(9 Op Codes)
(3 bytes)
(4,5 and 6 cycles)

Op Code
10
10

15. Relative r
(BPL,BMI,BYC,BYS,BCC,
BCS,BNE,BEQ,BRA)
(9 Op Codes)
12 bytes)
(2,3 and 4 cycles)

267

6
6a
I.
2
2a.
3.
4
5.

6
6a.
I
2.

(2)

(1)

4.
4a.

I
I
I

I
I
I
I

I
I

I
I
I
I

4.
4a.
5.
6a.
6.

2a.

3.
(I)
(3)
(I)

o
o
o

2.
(2)

I
I

2.
(2)

2a.
3.

2a
3.

I
I
I
I

(1)

4a.

(4)

3.
3a.

12a. Absolute,X .,.

(BIT,LDY,STZ,
ORA,AND,EOR,ADC,
STA,LDA,CMP,SBC)
(I I Op Codes)
(3 bytes)
(4,5 and 6 cycles)

3.
lc
Ib
la.
I.

I.
2.
(2)

(I)

Data Low

Op Code
DO
10
Data Low
Data High
10
Data High
Data Low

RES'1

m,O

4.
(I)

4a.

I.
2.
3.
4.

(I)
(3)
II)

5.
Sa.

I
I

I
I
I
I
I

I
I
I
,
0

o
0
0

I.
2.
3

5.
Sa.
I.
2.

(I)

(5)
(6)

I.
2
2a.
2b.

I
I
I
I
I

I
I
I

I
I

I
I
I
I
I

OpCod.
10
10
IRQ(BRK)

PBR,PC
PBR,PC'I
PBR,PC'1
PBR.PC·I
PBR,PC'I
PBR,PC'I
PBR,PC'I

Op Cod.
10
10
RES(BRK)
AES(BRK)
AESIBRK)
BEGIN

PBR,PC
PBR,PC'1
PBR,PC'1
0,0'00
0,0'00'1
DBR,AAH,AAL'
DBR.AA+Y
DBR,AA'Y+l

Op Cod.
DO
10
AAL
AAH
YL 10
Data Low
Data High

PBR,PC
PBR,PC'1
PBR,PC'1
0,0'00
0,0'00'1
0,0+00'2
AAB,AA'Y
AAB,AA'Y'1

Op Code
DO
10
AAL
AAH
AAB
Data Low
Data High

PBR,PC
PBR,PC'1
PBR,PC'I
PBR.PC.l
O,D'DO+X
O,D'DO+X'I
DBR,AA
DBR,AA+l

Op Code
DO
10
10
AAL
AAH
Data Low
Data High

1'0
1'0

PBR,PC
PBR,PC'1
PBR,PC'I
PBR,PC'1
O,D'DO+X
0,D+DO+X'1

Op Code
DO
10
10
Data Low
Data High

1/0
1/0

PBR,PC
PBR,PC'1
PBR,PC+l
PBR,PC+l
O,D'DO'X
D,D+OO+X+l
0,D'DO,X'1
0,D+DO'X'1
O,D'DO+X

Op Code
DO
10
10
Data Low
Data High
10
Dala High
Data Low

PBR,PC
PBR,PC+l
PBR,PC'1
PBR,PC+I
O,D'DO'Y
O,D'DO'Y+l

Op Code
DO
10
10
Data Low
Data High

1'0
1'0

Op Code
AAL
AAH
XL 10
Data Low
Dala High

1'0
1'0

PBR,PC
PBR,PC'1
PBR,PC'2
PBR,PC'3
AAB,AA'X
AAB,AA.X.t

Op Code
AAL
AAH
AAB
Data Low
Data High

I
I
I
I
I

PBR,PC
PBR,PC'1
PBR,PC'1
PBR,PC'1
PBR,PC'Offset

I
I
1/0
110

I
1/0

1'0

PBR,PC
Op Code
AAL
PBR,PC'1
PBR,PC+2
AAH
DBR,AAH,AAL'XL 10
DBR,AA'X
Data Low
DBR,AA'X'1
Data High
DBR.AA'X'1
10
DBR,AA'X'1
Data High
DBR,AA+X
Data Low

PBR,PC
Op Code
PBR,PC'1
AAL
PBR,PC+2
AAH
DBR,AAH,AAL'YL 10
DBR,AA'Y
Data Low
DBR,AA'Y'1
Data High

AiW

PBR,PC
PBR,PC'I
PBR.PC·I
PBR,PC'1

PBR,PC
PBR,PC'1
PBR.PC'2
DBR,AAH,AAL'
DBR,AA'X
DBR,AA'X+l

I
I

3.
3a.
4
4a.

(4)

7a.
7.

4.
(I)

I
I

ADDRESS IUS DATA IUS

Op Code
NEWPCL
NEWPCH
Op Code

I
I
I
I
I

I
I
I
I

PBR,PC
PBR,PC'1
PBR,PC'2
PBR, NEWPC

2a.
3.
3a.

IRQ,WiI

I
I
I
I

7. Direct Indirect Indexed Id)"
(ORA,AND,EOR,ADC,
STA,LDA,CMP,SBC)
(8 Op Codes)
(2 bytes)
(5,6,7 and 8 Cycles)

I
I
I
I
I

I
2.

3
I

RES'O
RES'1
See 21. Stack
(Hardware Interrupt)

110
1/0

Vii, iii. VDA, VPA

(9)

Op Code
AAL
AAH
Data Low
Data High
10
Data High
Data Low

I
I
I
I
I
I

I
I
I

.6d Stop-The-Clock
(STP)
(1 Op Code)
(I byte)
(3 cycles)

CYCLE

PBR,PC
PBR,PC'1
PBR,PC'2
DBR,AA
DBR,AA'1
DBR,AA'1
DBR,AA'1
DBR,AA

I
I
I
I
I
I

I
I
I

ADDRESS MODE
• 6c Walt For Interrupt
(WAI)
(lOp Code)
(I byte)
(3 cycles)

Op Code
AAL
AAH
Data Low
Data High

PBR,PC
PBR.PC·1
PBR,PC'2
O,S
O,S
PBR,PC'3
0,S-1
0,S-2
NEW PBR,PC

R/Vi

Op Code
IDL
IDH

PBR.PC
PBR,PC'1
PBR,PC'2
DBR,AA
DBR,AA'1

PBR,PC
PBR,PC'1
PBR,PC'1
0,0'00
0,0'00'1
0,0·00'1
0,0'00'1
0,0'00

1.
2.

5. Accumulator A
(ASL,INC,ROL,DEC,LSR,ROR)
16 Op Codes)
(I byte)
12 cycles)

*6b. Implied'
(XBA)
(lOp Code)
(I byte)
(3 cycles)

I
I
I
I
I

II)

6a. Implied I
(DEY, INY, INX, DEX, NOP,
XCE, TYA, TAY,TXA, TXS,
TAX,TSX,TCS,TSC,TCD,
TDC,TXY,TYX,CLC,SEC,
CLI,SEI,CLY,CLD,SED)
(25 Op Codes)
II byte)
(2 cycles)

I
I
I

4a. Direct d
IBIT,STZ,STY,LDY,
CPY,CPX,STX,LDX,
ORA,AND,EOR,ADC,
STA,LDA,CMP,SBC)
(18 Op Codes)
(2 bytes)
(3,4 and 5 cycles)

I
I
I
I

*3c. Absolute Long (Jump to
Subroutine Long) ••
(JSL)
(lOp Code)
(4 bytes)
17 cycles)

I
I

(1)

*3b. Absolute Long (JUMP) "'
(JMP)
(lOp Code)
(4 bytes)
(4 cycles)

o
o

I
I
I

ADDRESS BUS DATA BUS
PBR,PC
PBR,PC+I
PBR,PC+2

I
I

6
2c. Absolute IJUMP)
(JMP)(4C)
II Op Code)
(3 bytes)
13 cycles)

Op Code
Offset
10
10
Op Code

I
1/0

1'0

I
1/0
1/0

8VLSI TECHNOLOGY, INC.
VL65C816
TABLE 6. DETAILED INSTRUCTION OPERATION (CONT.)
ADDRESS MODE

CYCLE

*16. Aelalive Long rt
(BAL)
(1 Op Code)
(3 bytes)
(4 cycles)

1.
2.
3.
4.
1.

17a. Absolute Indirect (_)
(JMP)
(1 Op Code)
(3 bytes)
(5 cycles)

1.
2
3.
4.
5
1.
1.
2.
3.
4.
5
6.

*17b. Absolute Indirect (_)
(JML)
(1 Op Code)
(3 bytes)
(6 cycles)
• 18. Direct Indirect (d)
(OAA,AND,EOA,ADC,
STA,LDA,CMP,SBC)
(8 Op Codes)
(2 byles)
(5,6 and 7 cycles)

(2)

(1)
*19. Direct Indirect Long [d]
(OAA,AND,EOA,ADC
STA,LDA,CMP,SBC)
(8 Op Codes)
(2 bytes)
(6,7 and 8 cycles)

(2)

(1)
20a. Absolute Indexed Indirect (_,x)
(JMP)
(lOp Code)
(3 byles)
(6 cycles)

*20b. Absolute Indexed Indirect
(Jump to Subroullne Indexed
Indirect) (_,x)
(JSA)
(lOp Code)
(3 bytes)
(8 cycles)

21a. Stack (Hardware
Interrupts) I
(IAO.NMI,ABOAT,AES)

(3)
(7)

(4 hardware interrupts)

(0 bytes)
(7 and 8 cycles)

21b. Stack (Software
Interrupts) I
(BAK,COP)
(2 Op Codes)
(2 bytes)
(7 and 8 cycles)

(3)
(7)

1
2.
2a
3.

1.
2
2a.
3.
4.
5
6

VP. iii, VDA, VPA
1
1
1
1
1

1
1
1
1

RIW

1
1

1
1
1

PBA,PC
PBR,PC'1
PBA,PC'1
0,0'00
0,0·00·1
0,0'00'2
AAB,AA
AAB,AA'I

OpCode
DO
10
AAL
AAH
AAB
Data Low
Data High

PBA.PC
PBA.PC·1
PBA,PC'2
PBA.PC·2
PBA.AA·X
PBA,AA'X'1
PBA. NEWPC

OpCode
AAL
AAH
10
NEW PCL
NEW PCH
OpCode

PBA.PC
PBA,PC'1
0,5
0,5-1
PBA,PC'2
PBA,PC'2
PBR.AA·X
PBA,AA'X'1
PBA,NEWPC

Op Code
AAL
PCH
PCL
AAH
10
NEWPCL
NEWPCH
Next Op Code 1

PBA.PC
PBA,PC
0,5
0,5-1
0.5-2
0,5-3
O,VA
O.VA'1
O.AAV

10
10
PBR
PCH
PCL
P
AAVL
AAVH
Next Op Code

1.
2
3
4.
5.
6
7.
8
1.

1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1

1.
2
3.
4.
5
6
7
8.

1
1
1
1
1

1
1
1
1
1
1
0
0
1

1
1
1
1

1
1
1
1
1

1
21c. Stack (Aeturn from
Interrupt) •
2
(ATI)
(3) 3.
4
(1 Op Code)
(1 byte)
5.
(6 and 7 cycles)
6
(different order from N6502) (7) 7.
1

, ,

21d Stack (Return from
Subroutine) I
(ATS)
(1 Op Code)
(1 byte)
(6 cycles)

1.
2
3
4.
5
6.

1
1
1
1
1

*21e Stack (Return tram
Subroutine Long) •
(ATL)
(1 Op Code)
(1 byte)
(6 cycles)

1.
2
3
4
5
6.

1
1
0
0
0
0
1

PBA,PC
PBR,PC'1
PBR,PC'1
0.5'1
0.5'2
0.5'2
PBA,PC

Op Code
10
10
PCL
PCH
10
Op Code

PBA.PC
PBA,PC"
PBA,PC',
0.5'1
0,5'2
0.5'3
NEW PBA.PC

Op Code
10
10
NEW PCL
NEW PCH
NEWPBA
Next Op Code I

,,
,

1
1
1
1
1

PBA,PC
PBA,PC'1
PBA,PC'1
0,5'1
0,5'2

OpCode
10
10
Aeglster Low
Register High

1.
2.
2a
3
4
5.
6

PBA,PC
PBA,PC'1
PBA,PC'1
0,0'00
0,0'00'1
0,5
0,5-1

Op Code
DO
10
AAL
AAH
AAH
AAL

*211 Stack (Push EffectIVe
Absolute Address) I
(PEA)
(lOp Code)
(3 bytes)
(5 cycles)

1
2
3.
4.
5

PBA,PC
PBA,PC'1
PBA,PC'2
0,5
0,5-1

OpCode
AAL
AAH
AAH
AAL

*211 Stack (Push EllectlVe
Program Counter Relallve
Address) I
(PEA)
(1 Op Code)
(3 bytes)
(6 cycles)

1.
2.
3

1
1

PBA,PC
PBA,PC'1
PBA,PC'2
PBA,PC'2
0,5

*22. Stack Aelallve d,l
(OAA.AND,EOA,ADL.
STA.LDA.CMP,SDC)
(8 Op Codes)
(2 bytes)
(4 and 5 cycles)

(1)

(2)

0,5-1

Op Code
Offset Low
Offset High
10
PCH·OFF.
CAAAY
PCL .OFFSET 0

1
2.
3

1
1

(1)

PBA,PC
PBA,PC'1
PBA,PC'1
0.5'50
0.5'50'1

Op Code
SO
10
Data Low
Data High

1/0
1/0

1
1
1

(1)

1.
2.
3.
4.
5.
6.
7.
7a

1
1
1

1
I
1

PBA,PC
PBA,PC'1
PBR,PC'1
0,5'50
0,5'50'1
0,5'50'1
DBA,AA'Y
DBA.AA·Y·1

Op Code
SO
10
AAL
AAH
10
Data Low
Data High

1
1
1
1
110
'/0

1
1
1

I
1
1

1
1
1

PBR,PC
PBR,PC'1
PBA,PC'2
SBA,X
DBA,Y
DBA,Y
DBA,Y
PBA,PC
PBA.PC·1
PBA.PC·2
SBA,X-l
DBA,Y-l
DBA,Y-I
DBA,Y-l

Op Code
DBA
SBA
Source Data
Dest. Data
10
10
Op Code
DBA
SBA
Source Data
Dest. Data
10
10

PBA.PC
PBR,PC'I
PBA.PC·2
SBA,X-2
DBA.Y-2
DBA,Y-2
DBA,Y-2
PBA,PC'3

OpCode
DBA
SBA
Source Data
Dest. Data
10
10
NextOpCode

PBA,PC
PBA.PC·'
PBA,PC'2
SBA,X
DBA.Y
DBA,Y
DBA,Y

Op Code
DBA
SBA
Source Data
Dest. Data
10
10

PBR,PC
PBA,PC"
PBA,PC'2
SBA,X"
DBA,Y'1
DBA,Y"
DBA,Y"

Op Code
DBA
SBA
Source Data
Dest. Data
10
10

PBA.PC
PBR,PC'1
PBA,PC'2
SBA,X'2
DBA,Y'2
DBA.Y·2
DBA,Y'2
PBA,PC'3

Op Code
DBA
SBA
Source Data
Dest. Data
10
10
Next Op Code ,

*23. Stack Aelative Indirect
Indexed (d.I).Y
(OAA,AND,EOA,ADC.
STA,LDA,CMP,SDC)
(8 Op Codes)
(2 bytes)
(7 and 8 Cycles)
*24a. Block Move Positive
(forward) xye
(MVP)
(lOp Code)
(3 bytes)
(7 cycles)
x = Source Address

N-2
Byte
C=2

.-~"'"."oo

c =Number of Bytes to Move -1
x,Y Decrement
MVP is used when the
N-l
By~e
destination start address
is higher (more pOSitive)
C-l
than the source start address.

1
PBR,PC
Op Code
Signature
PBA.PC·1
0,5
PBA
PCH
0,5-1
0,5-2
PCL
0,5-3 (COP LatcheS) P
AAVL
O.VA
AAVH
O.VA·1
Next Op Code 1
O.AAV

1
1
1
1
I
1
1

1
1
1

1
1
1
1
1

1
1

,
,, ,
1
1
1

1
1/0
1/0

1
Op Code
10
10
P
PCL
PCH
PBA
New Op Code

1
1
1

1
1/0
1/0

PBA,PC
PBA.PC·'
PBR,PC"
0,5'1
0,5'2
0,5'3
0,5'4
PBA,PC

1
1

1
1
1

1
2
3
4.
4a

*21h Stack (push Ellectlve
Indirect Address) I
(PEl)
(1 Op Code)
(2 bytes)
(6 and 7 cycles)

1
1
1

1
1
1
1

Op Code
AAL
AAH
NEWPCL
NEWPCH
NEWPBA
Op Code

1
1
1

Op Code
10
Aegister High
Aegister Low

21g. Stack (Pull) I
(pLP,PLA,PLY,PLX,PLD,PLB)
(Different than N6502)
(6 Op Codes)
(1 byte)
(1)
(4 and 5 cycles)

Op Code
DO
10
AAL
AAH
Data Low
Dala Low

PBA,PC'
PBA,PC'1
0,5
0,5-1

Op Code
AAL
AAH
NEWPCL
NEWPCH
OpCode

PBA,PC
PBA,PC'1
PBR,PC'I
0,0'00
0,0'00'1
DBA,AA
DBA,AA'1

RJW

1
1
1
1

PBA,PC
PBA,PC'1
PBA,PC'2
O,AA
O,AA'I
PBA,NEWPC

1
1
1
1
1
1
1

ADDRESS BUS DATA BUS

1
1
1
1

211 Slack (Push) I
(pHP,PHA,PHY,PHX,
PHD,PHK,PHB)
(7 Op Codes)
(1 byte)
(3 and 4 cycles)

1
1
1
1
1
1
1

Vii, iiL, VDA, VPA

1.
2
3a
3.

OpCode
Ollset Low
Offset High
10
Op Code

1
1
1
1

1
1
1

CYCLE

ADDRESS MODE

PBA,PC
PBA,PC'1
PBA,PC'2
PBA,PC'2
PBA,PC'Offset

PBA,PC
PBA,PC'1
PBA,PC'2
O,AA
O,AA'1
O,AA'2
NEWPBA,PC

1
1

1.
2.
3.
4
5
6.
1.

6
7.
8

ADDRESS BUS DATA BUS

1
1
1
1
1
1
1
1
1

1.
2
3

1
1

FFFFFF

It"''''''

~ ource Start
Dest. End
Source End
00000o

*24b. Block Move Negative
(backward) xye
(MVN)
(lOp Code)
(3 bytes)
(7 cycles)
x = Source Address
Y = Destination

N Byte
Last
C=O

N-2
Byte
C=2

2.
3.
4.
5.
6.
7.

[

2.
3.
4.
5.
6.
7.

l
2.
3.
4.
5.
6.
7.
1.

2.
3.
4.
5.
6
7.

'-N"moo,"'"~'o"o~-'
[2.
x,y Increment

N-l
Byte

FFFFFF

d'~'OO
000

'"' c-,:

Dest.End

~~;~~"

000
MVN is used when the
~estination start add~ess

lower (more negative)
than the source start
address.
IS

268

3.
4.

N Byte
C=O

2.
3
4.
5.
6.
7.
1.

,
, ,,
, ,

, ,
, ,

1
1

,
, ,
1
1

VLSI TECHNOLOGY, INC.
VL65C816

TABLE 5. NOTES
Notes:
1. Bit immediate N and V flags not affected. When MoO, M15 - Nand M14 -V.
2. Break Bit (B) in Status register indicates hardware or software break.

New 65C616.' Instructions
• = New 65C02 Instructions
Blank = NMOS 6502

+ Add
- Subtract
II AND

V OR

-V- Exclusive OR

TABLE 6. NOTES
Abbreviations:

Notes

(t) Add 1 byte (for Immediate onty) for

M~O

X~O

(I e. t6 bit data). add t cycle for

M~O

X~O.

(2) Add 1 cycle fOl dlreC1 register low (Dl) not equal 0
(3) Special case for aborting instruction. This is the last cycle which may be aborted or the Status,
PBR or DBR registers will be updated.
(4) Add 1 cycle for indexing across page boundaries, or wnte, or

X~O.

When

X~1

or in the

(6) Add t cycle If branch is taken across page boundanes in 6502 emulallon mode
(E~

Absolute
Absolute
Absolute
Absolute
Absolute

Address
Address
Address
Address
Address

Bank
High
low
Vector High
Vector low

C Accumulator
Direct Register

emulation mode, this cycle contains invalid addresses.

DBA Destination Bank Address
DBR Dala Bank Register
DO Direct Offset

(5) Add 1 cycle If branch is taken.
(7) Subtrac11 cycle for 6502 emulation mode

AAB
AAH
AAl
AAVH
AAVl

(E~ t).

IOH Immediate Data High

(8) Add 1 cycle for REP.SEP

IDl
10
P
PBR

(9) Wal1 at cycle 2 for 2 cycles after NMf or IRQ active Input

Immediate Data low
Internal Operation
Status Register
Program Bank Register

PC Program Counter

R-M-W
S
SBA
SO
VA

Read-Modlfy-Wnte
Stack Address
Source Bank Address
Stack Offset
Vector Address

x.y Index Registers

• : New SSC8t S' Addressing Modes
• : New SSC02 Addressing Modes
Blank ~ NMOS 6502 Addressing Modes

RECOMMENDED
ASSEMBLER SYNTAX
STANDARDS
DIRECTIVES
Assembler directives are those parts of
the assembly language source program
that give directions to the assembler;
this includes the definition of data area
and constants within a program. This
standard excludes any definitions of
assembler directives.
COMMENTS
An assembler should provide a way to
use any line of the source program as a
comment. The recommended way of
doing this is to treat any blank line, or
any line that starts with a semicolon or
an asterisk, as a comment. Other
special characters may be used as well.
THE SOURCE LINE
Any line that causes the generation of a
single VL65C816 machine language
instruction should be divided into four
fields: a label field, tho operation code,
the operand, and the commont field.
The Label Field - The label field begins
in column one of the line. A label must
start with an alphabetic character, and
may be followed by zero or more
alphanumeric characters. An assembler
may define an upper limit on the number

of characters that can be in a label, as
long as that upper limit is greater than or
equal to six characters. An assembler
may limit the alphabetic characters to
upper case characters if desired. H
lower case characters are allowed, they
should be treated as identical to their
upper case equivalents. Other characters may be allowed in the label, as long
as their use does not conflict with the
coding of operand fields.
The Operation Code Field - The
operation code consists of a threecharacter sequence (mnemonic) from
Table 2. It starts no sooner than column
two of the line, or one space after the
label if a label is coded.
Many of the operation codes in Table 2
have duplicate mnemonics; when two or
more machine language instructions
have the same mnemonic, the assembler resolves the difference based on
the operand.

Han assembler allows lower case letters
in labels, it must also allow lower case
letters in mnemonics. When lower case
letters are used in the mnemonic, they

269

are treated as equivalent to the uppercase counterpart. Thus, the mnemonics
LOA, Ida, and LdA must all be recognized, and are equivalent.
In addition to the mnemonics in Table 2,
an assembler may provide the alternative mnemonics shown in Table 7.
SJL should be recognized as equivalent
to JSR when it is specified with a long
absolute address. JML is equivalent to
JMP with long addressing force.
The Operand Field - The operand field
may start no sooner than one space
after the operation code field. The
assembler must be capable of at least
24-bit address calculations. The
assembler should be capable of
specifying addresses as labels, integer
constants, and hexadecimal constants.
The assembler must allow addition and
subtraction in the operand field. Labels
are recognized by the fact that they start
with alphabetic characters. Decimal
numbers are recognized as containing
only the decimal digits 0 through 9.
Hexadecimal constants shall be
recognized by prefixing the oonltant

VLSI TECHNOLOGY, INC.
VL65C816

with a dollar sign ($) character, followed
by zero or more of either the decimal
digits or the hexadecimal digits A
through F. If lower case letters are
allowed in the label field, then they are
also allowed as hexadecimal digits.
All constants, no matter what their
format, provide at least enough precision to specify all values that can be
represented by a 24-bit signed or
unsigned integer represented in two's
complement notation.
Table 9 shows the operand formats that
are recognized by the assembler. The
symbol d is a label or value that the
assembler can recognize as being less
than #100 .. The symbol a is a label or
value which the assembler can recognize as greater than $FF but less than
$10000; the symbol al is a label or value
that the assembler can recognize as
being greater than $FFFF. The symbol
EXT is a label that cannot be located by
the assembler at the time the instruction
is assembled. Unless instructed
otherwise, an assembler assumes that
EXT labels are two bytes long. The
symbols rand rl are 8- and 16-bit signed
displacements calculated by the
assembler.
Note that the operand does not determine whether or not immediate addressing loads one or two bytes; this is
determined by the setting of the status
register. This forces the requirement for
a directive or directives that tell the
assembler to generate one or two bytes
of space for immediate loads. The
directives provided must allow separate

TABLE 7. ALTERNATIVE
MNEMONICS
Standard
BCC
BCS

Alias

CMPA
DECA
INCA
JSL
JML
TCD
TCS
TDC
TSC

CMA
DEA
INA
JSR
JMP
TAD
TAS
TDA
TSA
SWA

XBA

BLT

BGE

settings for the accumulator and index
registers.
The assembler shall use the <, >, and 1\
characters after the # character in an
immediate address to specify which byte
or bytes are to be selected from the
value of the operand. Any calculations
in the operand must be performed
before the byte selection takes place.
Table 8 defines the action taken by each
operand by showing the effect of the
operator on an address. The column
that shows a two-byte immediate value
shows the bytes in the order in which
they appear in memory. The coding of
the operand is for an assembler that
uses 32 bit address calculations,
showing the way that the address
should be reduced to a 24 bit value.
In any location in an operand in which
an address, or expression resulting in
an address, can be coded, the assembler recognizes the prefix characters <,
I, and >, which force one-byte (direct
page), two-byte (absolute) or three-byte
(long absolute) addressing. In cases in
which the addressing mode is not
forced, the assembler shall assume that
the address is two bytes unless the
assembler is able to determine the type
of addressing required by context, in
which case that addressing mode is
used. Addresses are truncated without
error if an addressing mode is forced
that does not require the entire value of
the address. For example:
LOA
LOA

$0203
$010203

are completely equivalent. If the
addressing mode is not forced, and the
type of addressing cannot be determined from context, the assembler
assumes that a two-byte address is to
be used. If an instruction does not have
a short addressing mode (as in LOA,
which has no direct page indexed by Y)
and a short address is used in the
operand, the assembler automatically
extends the address by padding the
most significant bytes with zeros in order
to extend the address to the length
needed. As with immediate addressing,
any expression evaluation takes place
before the address is selected; thus, the
address selection character is only used
once, before the address of expression.
The exclamation point (I) character
should be supported as an alternative to
the vertical bar (I).
A long indirect address is indicated in
the operand field of an instruction by
surrounding the direct page address
where the indirect address is found by
square brackets; direct page addresses
that contains 16-bit addresses are
indicated by being surrounded by
parentheses.
The operands of a block move instruction are specified as source bank,
destination band (the opposite order of
the object bytes generated).
Comment Field -The comment field may
start no sooner than one space after the
operation code field or operand code
field or operand field, depending on
instruction type.

TABLE 8. BYTE SELECTION OPERATOR
Operand
#$01020304
#<$01020304
#>$01020304
#"$01020304

One Byte Result
04
04
03
02

270

Two Byte
04
04
03
02

Result
03
03
02
01

VLSI TECHNOLOGY, INC.
VL65C816

TABLE 9. ADDRESS MODE FORMATS
Addressing Mode
Immediate

Absolute

Absolute Long

Direct Page

Accumulator
Implied Addressing
Direct Indirect
Indexed

Direct Indirect
Indexed Long

Direct Indexed
Indirect

Direct Indexed by X

Direct Indexed by Y

Absolute Indexed by X

Format

Addressing Mode
Absolute Indexed by Y

#d
#a
#al
#EXT
#d
#>a
#>al
#>EXT
#I\d
#"a
#I\al
#1\ EXT
!d
!a
a
!al
!EXT
EXT
>d
>a
>al
al
>EXT
d
d,x
>a,x
>al,x
al,x
>EXT,x
d
a
al
EXT
(d)
(!d)
(a)
(!a)
(!al)
(EXT)
(d)

«a)
«al)
«EXT)
[d]
[2 (IN), NMI, ABORT

VIH

InQ.!!LLow VO!§9.e
RES, RDY, IRQ, Data, BE.
1/>2 (IN), NMI, ABORT

VIL

In~eakage

liN

Current (VIN ~al
RES, NMI, RDY, IRQ, BE, ABORT (Internal Pull up)
1/>2 (IN)
Address, Data, Riw (Off State, BE = 0)

Output High VoltageJ.!.o~ :::!QOuA)
Data, Address, R/W, ML, VP, MIX, E, VDA, VPA,
1/>2 (OUT)

VOH

Output Low Voltage J.!..o~ 1.6mAl
Data, Address, R/W, M.hVP, MIX, E, VDA, VPA,
1/>2 (OUT)

VOL

Supply Current (No Load)

100

Standbi..9:!rrent (No Load, Data Bus =Vss or Vaa
RES, NMI, IRQ, BE, ABORT, 1/>2 = Va 0)

IS8

Min

Max

Unit

2.0
0.7 Vaa

Vaa + 0.3
Vaa + 0.3

V
V

-0.3
-0.3

0.8
0.2

V
V

-100
-1
-10

1
1
10

pA
pA
pA

0.7 Vaa

Capacitance (VIN = OV, TA = 25°C, f = 2 MHz)
Logie, 1/>2 (IN)
Address, Data, RiVi (Off State)

CIN
Crs

278

0.4

rnAIMHz

10
15

pF
pF

VLSI TECHNOLOGY, INC.
VL65C816

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature
Storage Temperature

-55°C to +150°C

Supply Voltage to
Ground Potential

-0.3 V to +7.0 V

Applied Input
Voltage

Stresses above those listed under
"Absolute Maximum Ratings" may cause
permanent damage to the device. These
are stress ratings only. Functional
operation of this device under these or
any conditions other than those indicated in this data sheet is not implied.
Exposure to absolute maximum rating

-0.3 V to VDD+ 0.3 V

279

conditions for extended periods may
affect device reliability.
This device contains input protection
against damage due to high static
voltages or electric fields. However,
precautions should be taken to avoid
application of voltages higher than the
maximum rating.

VLSI TECHNOLOGY, INC.

280

VLSI TECHNOLOGY, INC.
VL6765
DOUBLE-DENSITY FLOPPY
DISK CONTROLLER (DDFDC)

FEATURES

DESCRIPTION

• Address mark detection circuitry

The VL6765 Double-Density Floppy Disk Controller (DDFDC)
interfaces up to four floppy disk drives to an 8-bit or 16-bit
microprocessor-based system including Z80, 8080A, 8085A, 8086,
and 8088. The DDFDC simplifies the system design by minimizing both the number of external hardware components and software steps needed to implement the floppy disk drive (FDD)
interface. Control signals supplied by the DDFDC reduce the
number of components required in external phase locked loop
and write precompensation circuitry. Memory-mapped registers
containing commands, status and data simplify the software interface. Built-in functions reduce the software overhead needed to
control the FDD interface. The DDFDC supports both the
IBM 3740 Single-Density (FM) and IBM System 34 Double-Density
(MFM) formats.

• Software control of
-Track stepping rate
-Head load time
-Head unload time
• IBM compatible in both single- and double-density format
• Programmable data record lengths: 128,256,512,1024,2048,
4096 or 8192 bytes/sector
•

Multi-sector and multi-track transfer capability

• Controls up to four floppy disk drives
•

Data scan capability-will scan a single sector or an entire
track of data fields, comparing on a byte-by-byte basis data
in the processor's memory with data read from the disk

The DDFDC interfaces directly to the synchronous microprocessor bus and operates with 8-bit byte length data transferred on
the bus in either DMA or non-DMA mode. In DMA mode, the CPU
need only load the command into the DDFDC and all data
transfers occur under DMA control. The,VL6765 is directly compatible with the Z8410/~PD8257 Direct Memory Access Controller
(DMAC). In non-DMA mode, the DDFDC generates an interrupt
to the CPU indicating that a byte of data is available.

• Data transfers in DMA or non-DMA mode
• Parallel seek operations on up to four drives
•

Directly compatible with an 8-bit or 16-bit synchronous
microprocessor bus including Z-80/8080Al8085A,
8086, and 8088

•

Replaces the NEC ~PD765A, Intel 8272A, and
Rockwell 6765A

• Single phase 4 or 8 MHz clock
• Single + 5 volt power supply

PIN DIAGRAM

ORDER INFORMATION

VL6765

Part
Number

Clock
Frequency

VL6765-04PC
VL6765-04CC
VL6765-04QC

4 MHz

VL6765-08PC
VL6765-08CC
VL6765-08QC

8 MHz

Package
Plastic DIP
Ceramic DIP
Plastic Leaded
Chip Carrier (PLCC)
Plastic DIP
Ceramic DIP
Plastic Leaded
Chip Carrier (PLCC)

Note:
Operating temperature range: O°C to + 70°C.

281

VLSI TECHNOLOGY, INC.
VL6765

PIN DIAGRAM
VL6765
PLCC

RWi FR!
SEEK STP

DO
01
02
03
D4
05

37
36
35
34

FLTITRKO
PSO
PS1
WOA
USO
US1

07
31

MFM
WE

282

VLSI TECHNOLOGY, INC.
VL6765

Figure 1.

DDFDC Input and Output Signals
ROW

00-07 ~

ROD

WCK

VCO
WOA

PROCESSOR
BUS
INTERFACE

RST
CS
AO

FDO
SERIAL
DATA
INTERFACE

PSO-PS1

ROY

INT

lOX

RO
OOFOC

WPITS
FlTITRKO
leT/OIR

OMAC
INTERFACE

{

OACK

FRISTP

RW/SEEK

ORQ

HOl

FDO
CONTROl/ST ATUS
INTERFACE

HO
ClK

usa

--'"

US1

Vee
GNO

...

MFM

PIN DESCRIPTION
Throughout this document signals are presented using the terms
active and inactive, or asserted and negated, independent of
whether the signal is active in the high-voltage state or low-voltage
state. (The active state of each logic pin is described below.) Active
low signals are denoted by a superscript bar.

BUS INTERFACE
DO-D7-Data Lines. The bidirectional data lines transfer data
between the DDFDC and the a-bit data bus.
ClK-ClOCK. The clock is a TTL compatible 4 or a MHz square
wave signal.
RST -RESET. This active high input places the DDFDC in the
idle state and resets the output lines to the floppy disk drive (FDD)
to the low state. RST does not affect the Step Rate Time (SRT),
Head Unload Time (HUT) or Head Load Time (HLT) set by a
Specify command. If RDY goes high while RST is high, the
DDFDC will assert INT within 1.024 ms. This interrupt can be
cleared by issuing a Sense Interrupt Status command.
CS-Chip Select. The DDFDC is selected when the CS input
is low.

operation. When AO = low, the Status Register is selected. This
register may only be read (RD = low); the state WR = low is
invalid when the Status Register is selected.
INT-Interrupt Request. This active high output is the interrupt
request generated by the DDFDC to the CPu. INT is asserted upon
completion of some DDFDC commands and before a data byte
is transferred between the DDFDC and the data bus (in the NonDMA mode).
RD-Read. This active low input defines the data bus transfer
as a read cycle. When low, the data transfer is from the DDFDC
to the data bus.
WR-Write. This active low input defines the data bus transfer
as a write cycle. When low, the data transfer is from the data bus
to the DDFDC.

DIRECT MEMORY ACCESS CONTROLLER
(DMAC) INTERFACE
DACK-DMA Acknowledge. The DMA transfer acknowledge
signal is a TTL compatible input generated by the DMA controller
(DMAC) controlling the DDFDC. The DMA cycle is active when
DACK is low and the DDFDC is performing a DMA transfer.
DRO-Data DMA Request. The transfer request signal is a TTL
compatible output generated by the DDFDC to request a data
transfer operation under control of the DMAC (in the DMA mode).
The request is active when DRO = high. The signal is reset
inactive when DMA Acknowledge (DACK) is asserted (low).

AO-DatalStatus Register Select. This input selects the Data
or Status Register for reading from or writing to. When AO = high,
the Data Register is selected and the state of RD or WR
determines whether it is a read (RD = low) or a write (WR = low)

283

VLSI TECHNOLOGY, INC.
VL6765

TC-Terminal Count. This input signal is issued to the DDFDC
when the DMA transfer for a channel is complete. The signal is
active high concurrent with the DACK input when the DMA
operation is complete as a result of that transfer.

WP/TS-Write Protect/Two Side. An active high multiplexed
input signal from the FDD. In the ReadIWrite mode, WPITS high
indicates the media is write-protected. In the Seek mode, WP/TS
high indicates the media is two-sided.

FDD SERIAL DATA INTERFACE

FLT/TRKO-Fault/Track Zero. An active high multiplexed input
from the FDD. In the ReadIWrite mode (RW/SEEK = low),
FLTITRKO high indicates an FDD fault. In the Seek mode,
FLTITRKO high indicates that the read/write head is positioned
over track zero.

RDD-Read Data. Read Data input from the floppy disk drive
(FDD) containing clock and data bits.
RDW-Read Data Window. Data Window input generated by the
Phase Locked Loop (PLL) and used to sample data from the FDD.
VCO-Voltage Controlled Oscillator Sync. This output signal
inhibits the VCO in the PLL circuit when low and enables the
VCO in the PLL circuit when high. This inhibits RDD and RDW
from being generated until valid data is detected from the FDD.
WCK-Write Clock. This input clock determines the Write Data
rate to the FDD. The data rate is 500 KHz in the FM mode (MFM
= low) and 1 MHz in the MFM mode (MFM = high). The pulse
width is 250 ns (typical) in both modes.
WDA-Write Data. Serial write data output to the FDD containing both clock and data bits.
WE-Write Enable. This output signal enables the Write Data
into the FDD when high.
PSO-PS1-Preshift. These outputs are encoded to convey write
compensation status during the MFM mode to determine early,
late or normal times as follows:

LCT/DIR-Low Current/Direction. A multiplexed output to the
FDD. In the ReadIWrite mode, LCT/DIR is low when the readlwrite
head is to be positioned over the inner tracks and the LCT/DIR
is high when the head is to be positioned over the outer tracks.
In the Seek mode, LCT/DIR controls the head direction. When
LCT/DIR is high, the head steps to the outside of the disk; when
LCT/DIR is low, the head steps to the inside of the disk.
FR/STP-Fault Reset/Step. A multiplexed output to the FDD.
In the ReadIWrite mode, FR/STP high resets the fault indicator
in the FDD. An FR pulse is issued at the beginning of each read
or write command prior to issuing HDL. In the Seek mode,
FR/STP provides the step pulses to move the read/write head
to another track in the direction indicated by the LCT/DIR signal.
HDL-Head Load. An active high output to notify the FDD that
the read/write head should be loaded (placed in contact with the
media). A low level indicates the head should be unloaded.
Figure 2.

Typical VL6765 Application

Preshift Outputs
Write Precompensation Status

PSO

PS1

Normal
Late
Early
Invalid

o
o

Low, 1 = High

FDD STATUS INTERFACE
RDY-Ready. An active high input signal indicates the FDD is
ready to send data to, or receive data from, the DDFDC.
VL6765 FLOPPY
DISK CONTROLLER

IDX-Index. An active high input signal from the FDD indicates
the index hole is under the index sensor. Index is used to synchronize DDFDC timing.
RW/SEEK-Read Write/Seek. Mode selection signal to the FDD
which controls the multiplexer from the multiplexed signals.
When RW/SEEK is low, the ReadIWrite mode is commanded;
when RW/SEEK is high, the Seek mode is commanded.

RW/SEEK

Mode

Low

ReadIWrite

High

Seek

Active FDD Interface Signals
Wp, FLT, LCT, FR
TS, TRKO, DIR, STP

284

VLSI TECHNOLOGY, INC.
VL6765
DDFDe REGISTERS

HD-Head Select. An output to the FDD to select the proper
readlwrite head. Head One is selected when HD = high and Head
Zero is selected when HD = low.

The DDFDC contains six registers which may be accessed by
the processor or DMA controller via the system (Le., microprocessor) bus: a Main Status Register, a Data Register, and four
Result Status Registers. The 8-bit Main Status Register (MSR)
contains the status information of the DDFDC, and may.be
accessed at any time. The 8-bit Data Register, consisting of
several registers in a stack with only one register presented to
the data bus at a time, stores data, commands, parameters and
FDD status information. Bytes of data are read out of, or written
into, the Data Register in order to initiate a command or to obtain
the results of a command execution.

USO-US1-Unit Select. Output signals for floppy disk drive selection as follows:
Unit Select

usa

US1

0
0

0
1

Floppy Disk
Drive Select

0
1
2
3

Low, 1 = High

The read-only Main Status Register facilitates the transfer of data
between the system and the DDFDC. The other Status Registers
(STO, ST1, ST2 and ST3) are only available during the result
phase, and may be read only after completing a command. The
particular command which has been executed determines how
many of the Status Registers will be read.

MFM-MFM Mode. Output signal to the FDD to indicate MFM
or FM mode. Selects the MFM mode when MFM = high and the
FM mode MFM = Low.
VCC-Power. + 5 Vdc.
GND-Ground (V55)'
Figure 3.

DDFDC Block Diagram

I/O
BUFFERS

00-07

RST
RO

...

SERIAL
READ
CONTROL

OPERATION
CONTROL

SERIAL
WRITE
CONTROL

t/)

::>
m
...I

cs:

OACK

II:

OMA
CONTROL

w
~~

)

ORO

VCC

INT

GNO

ROD

ClK

ROW

DRIVE
INTERFACE
CONTROL

OUTPUT
PORT

285

WOA
WE
PSO, PS1
ROY

WPITS

FlTITRKO

-..

lCTIOIR
FR/STP
RW/SEEK
HOl

--..

usa

MFM

I..-

WCK

lOX

..
..

INPUT
PORT

VCO

HO
US1

VLSI TECHNOLOGY, INC.
VL6765

The relationship between the status/data registers and the WR,
RD and AO signals is shown below.

MSR
03B
-Floppy Disk Drive (FOO) 3 Busy.
FDD 3 is not busy, DDFDC will accept read or write
command.
FDD 3 is busy, DDFDC will not accept read or write
command.

Function

0
0
0

0
0

1
1
1

0
0

Illegal
Read Main Status Register
Illegal
Illegal
Read from Data Register
Write into Data Register

1
0

MSR

02B
-FDD 2 Busy.
FDD 2 is not busy, DDFDC will accept read or write
command.
FDD 2 is busy, DDFDC will not accept read or write
command.

o = Low, 1 = High

Table 1 shows each of the status registers used by the DDFDC
and each bit assignment within the individual registers. Table 2
defines the symbols used throughout the command definitions.
Each register bit symbol is defined in the register descriptions that
follow Table 2.

MSR
-FOO 1 Busy.
1 D1B
o FDD 1 is not busy, DDFDC will accept read or write
command.
FDD 1 is busy, DDFDC will not accept read or write
command.

Main Status Register (MSR)

MSR

D2B

D1B

The DID and ROM timing chart is shown in Figure 4.

Status Register 0 (STO)
7

ROM
-Request for Master.
Data Register is not ready.
Data Register is ready.

010
-Data Input/Output.
Data transfer is from system to the Data Register.
Data transfer is from Data Register to the system.

a
1

MSR
4 CB
-Controller (OOFDC) Busy.
a
DDFDC is not busy, will accept a command.
DDFDC is busy, will not accept a command.
1

3
NR

US
HD

I USo

STO

a
a

-Interrupt Code.
Normal Termination (NT). Command was properly executed and completed.
Abnormal Termination (AT). Command execution was
started, but was not successfully completed.
Invalid Command (IC). Received command was invalid.
Abnormal Termination (AT). The Ready (RDY) signal
from the FDD changed state during command
execution.

STO
~

EXM
-Execution Mode. (Non-DMA mode only).
Execution phase ended, result phase begun.
Execution phase started.

The Status Register 0 (STO) as well as the other status registers
(ST1-ST3), are available only during the result phase, and may
be read only after completing a command. The particular command executed determines which status registers are used and
may be read.

MSR
~

US1

MSR

.I
IC

MSR

OOB
-FDD 0 Busy.
FDD 0 is not busy, DDFDC will accept read or write
command.
FDD 0 is busy, DDFDC will not accept read or write
command.

DOB

The Main Status Register (MSR) contains the status information
of the DDFDC, and must be read by the processor before each
byte is written to, or read from, the Data Register during the command or result phase. MSR reads are not required during the
execution phase. The Data InpuUOutput (DID) and Request for
Master (ROM) bits in the MSR indicate when data is ready and
in which direction data will be transferred on the data bus. The
maximum time between the last RD or WR during command
or result phases and the DID and ROM getting set or reset is
12 p.s. For this reason, every time the MSR is read the processor
should wait 12 p.s. The maximum time from the trailing edge of
the last RD in the result phase to when bit 4 (DDFDC Busy)
goes low is also 12 p.S.

o
o

SE
-Seek End.
Seek command is not completed.
Seek command completed by DDFDC.

STO
4 EC
-Equipment Check.
o No error.
1
Either a fault signal is received from the FDD or the track
signal failed to occur after 256 step pulses (Recalibrate
command).

286

VLSI TECHNOLOGY, INC.
VL6765

Table 1.

DDFDC Status Register Bit Assignments

Bit Number
Main Status Register (MSR)
Status Register 0 (STO)

ROM

010

EXM

D3B

D2B

D1B

DOB

Status Register 1 (ST1)

US
US1

USO

Status Register 2 (ST2)

Status Register 3 (ST3)

FLT

ROY

TAKO

US1

usa

Table 2.

Command Symbol Description
Name

Symbol

Description

= low) or Data Register (AO = high).

Address Line AO

Controls selection of Main Status Register (AO

Data

The data pattern which is going to be written into a sector.

DO-D7

Data Bus

8-bit data bus, where DO is the least significant data line and D7 is the most significant data line.

DTL

Data Length

When N is defined as 00, DTL is the number of data bytes to read from or write into the sector.

EDT

End of Track

The final sector number on a track. During read or write operation, the DDFDC stops data transfer
after reading from or writing to the sector equal to EDT.

GPL

Gap. Length

The length of Gap 3. During read/write commands this value determines the number of bytes that the
VCO will stay low after two CRC bytes. During the Format a Track command it determines the size of
Gap 3.

Head Address

Head number 0 or 1, as specified in ID field.

HD (H)

Head

A selected head number 0 or 1 which controls the polarity of pin 27. (H

HLT

Head Load Time

The head load time in the FDD (2 to 254 ms in 2 ms increments).

HUT

Head Unload Time

The head unload time after a read or write operation has occurred (16 to 240 ms in 16 ms increments).

FM or MFM Mode

When MF = 0, FM mode is selected; and when MF = 1, MFM mode is selected.

Multi-Track

When MT = 1, a multi-track operation is to be performed. After finishing a read/write operation on side
0, the DDFDC will automatically start searching for sector 1 on side 1.

Bytes/Sector

The number of data bytes written in a sector.

Non-DMA Mode

When ND

NTN

New Track Number

A new track number, which will be reached as a result of the Seek command. Desired head position.

PTN

Present Track Number

The track number at the completion of Sense Interrupt Status command. Present head position.

Record (Sector)

The sector number to be read or written.

RIW

ReadlWrite

Either read (R) or write (W) signal.

Sectors/Track

The number of sectors per track.

Skip

Skip Deleted Data Address Mark.

SRT

Step Rate Time

The stepping rate for the FDD (1 to 16 ms in 1 ms increments). Stepping rate applies to all drives
(F = 1 ms, E = 2 ms, etc.)

STO
ST1
ST2
ST3

Status
Status
Status
Status

Four registers which store the status information after a command has been executed. This information
is available during the result phase after command execution. These registers should not be confused
with the Main Status Register (selected by AO = low). STO-ST3 may be read only after a command has
been executed and contain information relevant to that particular command.

STP

Sector Test Process

During a Scan command, if STP = 01, the data in contiguous sectors is compared byte by byte with data
sent from the processor (or DMA controller); and if STP = 02, then alternate sectors are read and
compared.

Track Number

The current/selected track number of the medium (0-255).

USO,US1

Unit Select

A selected drive number (0-3).

0
1
2
3

= 1, operation

is in the Non-DMA mode; when ND

287

= 0,

= HD in all command

words).

operation is in the DMA mode.

VLSI TECHNOLOGY, INC.
VL6765

STO
~

NR
-Not Ready.
FDD is ready.
FDD is not ready at issue of read or write .command. If
a read or write command is issued to side 1 of a singlesided drive, this bit is also set.

o
1

ST1
-Not Writable.
1 NW
a No error.
DDFDC detected a write protect signal from FDD during
1
execution of Write Data, Write Deleted Data or Format
a Track commands.
ST1

STO
-Head Address. (At Interrupt).
2 HD
o Head Select o.
1
Head Select 1.

o
o

MA
-Missing Address Mark.
No error.
2 possible errors.

1. DDFDC cannot detect the ID Address Mark after
encountering the index hole twice.

STO
1 0

US
-Unit Selected. (At Interrupt).
FDD a selected.
1
FDD 1 selected.
a FDD 2 selected.
1
FDD 3 selected.

2. DDFDC cannot detect the Data Address Mark or
Deleted Data Address Mark. The MD (Missing Address
Mark in Data field) of Status Register 2 is also set.

Status Register 2 (ST2)

Status Register 1 (ST1)
6

2
ND

I I

ST1
7 EN
-End of Track.
a No error.
1
DDFDC attempted to access a sector beyond the last
sector of a track.
ST1
6

ST1
3

OR
-Overrun.
No error.
DDFDC was not serviced by the system during data
transfers, within a predetermined time interval.
-Not Used. Always Zero.

3,.
SH

ST2

-Not Used. Always Zero.

ST2
~

-Not Used. Always Zero.

ST1
4

ST1
5 DE
-Data Error.
o No error.
DDFDC detected a CRC error in 10 field or the Data field.

CM
-Control Mark.
No error.
DDFDC encountered a sector which contained a Deleted
Data Address Mark during execution of a Read Data,
Read a Track, or Scan command, or which contained a
Data Address Mark during execution of a Read Deleted
Data command.

ST2
-Data Error In Data Field.
5 DO
a No error.
DDFDC detected a CRC error in the Data field.
1
ST2
-Wrong Track.
4 WT
a No error.
1
Contents of T on the disk is different from that stored in
lOR. Bit is related to NO (Bit 2) of Status Register 1.
ST2

ST1
-No Data.
2 NO
o No error.
1
.3 possible errors.

1. DDFDC cannot find sector specified in the Internal Data
Register (IDR) during execution of Read Data, Write
Deleted Data or Scan commands.·
2. DDFDC cannot read 10 field without an error during
Read ID command.
3. DDFDC cannot find starting sector during execution
of Read a Track command.

288

SH
-Scan Equal Hit.
No "equal" condition during a scan command.
"Equal" condition satisfied during a scan command.

ST2
~

o
1

SN
-Scan Not Satisfied.
No error.
DDFDC cannot find a sector on the track which meets
the scan command condition.

VLSI TECHNOLOGY, INC.
VL6765
COMMAND SEQUENCE

ST2
1 BT
-Bad Track.
o No error.
1
Contents of T on the disk is different from that stored in
the lOR and T = FF. Bit is related to NO (Bit 2) of Status
Register 1.

The DDFDC is capable of performing 15 different commands.
Each command is initiated by a multi-byte transfer of data from
the system. After command execution, the result of the command
may be a multi-byte transfer of data back to the system. Because
of this multi-byte transfer of information between the DDFDC qnd
the system, each command consists of three phases:

ST2

o
o
1

MD
-Missing Address Mark In Data Field.
No error.
DDFDC cannot find a Data Address Mark or Deleted Data
Address Mark during a data read from the disk.

Command Phase-The DDFDC receives all information
required to perform a particular operation from the system.
Execution Phase-The DDFDC performs the instructed
operation.

Status Register 3 (ST3)

Result Phase-After completion of the operation, status and
other housekeeping information are made available to the system.

US1

usa

Status Register 3 (ST3) holds the results of the Sense Drive Status
command.
ST3
7 FLT
-Fault.
Fault (FLT) signal from the FDD is low.
Fault (FLT) signal from the FDD is high.

ST3
6 WP
-Write Protect.
Write Protect (WP) signal from the FDD is low.
1
Write Protect (WP) signal from the FDD is high.

The bytes of data sent to the DDFDC to form a command, and
read out of the DDFDC in the result phase, must occur in the
order shown for each command sequence. That is, the command
code byte must be sent first followed by the other bytes in the
specified sequence. All command bytes must be written and all
result bytes must be read in each phase. After the last byte of
data in the command phase is received by the DDFDC, the execution phase starts. Similarly, when the last byte of data is read out
in the result phase, the command is ended and the DDFDC is
ready to accept a new command. A command can be terminate.d
by asserting the Terminal Count (TC) signal to the DDFDC. ThiS
ensures that the processor can always get the DDFDC's attention even if the command in process hangs up in an abnormal
manner.

COMMAND DESCRIPTION
ST3
5 ROY
-Ready.
Ready (ROY) signal from the FDD is low.
1
Ready (ROY) signal from the FDD is high.

READ DATA

A command set of nine bytes places the DDFDC into the Read
Data mode. After the Read Data command has been received
the DDFDC loads the head (if it is unloaded), waits the specified
Head Settling Time (defined in the Specify command), then begins
reading ID Address Marks and 10 fields from the disk. When the
current sector number (R) stored in the 10 Register (lOR) matches
the sector number read from the disk, the DOFDC transfers data
from the disk Data field to the data bus.

ST3
4 TRKO
-Track O.
Track 0 (TRKO) Signal from the FDD is low.
1
Track 0 (TRKO) signal is from the FDD is high.

ST3
3 TS
-Two Side.
Two Side (TS) signal from the FDD is low.
1
Two Side (TS) signal from the FDD is high.

ST3
2 HD
-Head Select.
Head Select (HD) signal to the FDD is low.
1
Head Select (HD) signal to the FDD is high.

ST3
1 US1
o Unit
1
Unit
ST3
o USO
Unit
1
Unit

-Unit Select 1.
Select 1 (US1) signal to the FDD is low.
Select 1 (US1) signal to the FDD is high.
-Unit Select O.
Select 0 (USO) signal to the FDD is low.
Select 0 (US1) signal to the FDD is high.

After completion of the read operation from the current sector,
the DDFDC increments the Sector Number (R) by one, and the
data from the next sector is read and output to the data bus. This
continuous read function is called a "Multi-Sector Read Operation." The Read Command terminates after reading the last data
byte from sector R when R = EDT. STO bits 7 and 6 are set to
o and 1, respectively, and STl bit 7 (EN) is set to a 1.
The Read Data command can also be terminated by a high
Terminal Co~C) signal. TC should be issued at the same
time that the DACK for the last byte of data is sent. Upon receipt
of TC, the DDFDC stops outputting data to the data bus, but continues to read data from the current sector, checks CRC (Cyclic
Redundancy Count) bytes, and then at the end of that sector terminates the Read Data command and sets bits 7 and 6 in STO

289

VLSI TECHNOLOGY, INC.
VL6765

to o. The amount of data which can be handled with a single command to the DDFDC depends upon MT (Multi-Track), MF
(MFM/FM), and N (Number of Bytes/Sector) values. Table 3 shows
the transfer capacity.
The multi-track function (MT) allows the DDFDC to read data from
both sides of the disk. For a particular track, data is transferred
starting at sector 1, side 0 and completed at sector L, side 1
(sector L = last sector on the side). This function pertains to only
one track (the same track) on each side of the disk.
When N = 0 in command byte 6 (FM mode), the Data Length
(DTL) in command byte 9 defines the data length that the DDFDC
must treat as a sector. If DTL is smaller than the actual data
length in a sector, the data beyond the DTL is not sent to the
data bus. The DDFDC reads (internally) the complete sector, performs the CRC check, and depending upon the manner of command termination, may perform a multi-sector Read operation.
When N is nOll-zero (MFM mode), DTL has no meaning and
should be set to FF.
At the completion of the Read Data command, the head is not
unloaded until the Head Unload Time (HUT) interval defined in
the Specify command has elapsed. The head settling time may
be avoided between subsequent reads if the processor issues
another command before the head unloads. This time savings
is considerable when disk contents are copied from one drive to
another.

If the DDFDC reads a Deleted Data Address Mark from the disk,
and the Skip Deleted Data Address Mark bit in the first command
byte is not set (SK = 0), then the DDFDC reads all the data in
the sector, sets the Control Mark (CM) flag in ST2 to a 1, and
terminates the command. If SK = 1, the DDFDC skips the sector with the Deleted Data Address Mark and reads the next sector. The CRC bits in the deleted data field are not checked when
SK = 1.
During disk data transfers from the DDFDC to the system, the
DDFDC must be serviced by the system within 27 p,s in the FM
mode, and within 13 p.S in the MFM mode, otherwise the DDFDC
sets the Over Run (OR) flag in ST1 to a 1, sets bits 7 and 6 in
STO to 0 and 1, respectively, and terminates the command.
If the processor terminates a read (or write) operation in the
DDFDC, then the ID information in the result phase is dependent
upon the state of the ~.lT bit in the first command byte and the
End of Track (Eon byte. Table 4 shows the values for Track
Number (T), Head f\jumber (H), Sector Number (R), and Number
of Data Bytes/Sector (N), when the processor terminates the
command.

Command Phase:

If the DDFDC detects the Index Hole twice in succession without
finding the right sector (indicated in R), tilen the DDFDC sets the
No Data (ND) flag in Status Register 1 (ST1) to a 1, sets Status
Register 0 (STO) bits 7 and 6 to 0 and 1, respectively, and terminates the Read Data command.
After reading the ID and Data fields in each sector, the DDFDC
checks the CRC bytes. If a read error is detected (incorrect CRC
in ID field), the DDFDC sets the Data Error (DE) flag in ST1 to
a 1, sets the Data Error in Data Field (DD) flag in ST2 to a 1 if
a CRC error occurs in the Data field, sets bits 7 and 6 in STO
to 0 and 1, respectively, and terminates the command.

Table 3.

RIW

BYTE

US1

USO

Track Number (T)

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

End of Track (EDT)

Gap Length (GPL)

Data Length (DTL)

DDFDC Transfer Capacity

Multi-Track
(MT)

MFM/FM
(MF)

Bytes/Sector
(N)

0
0

0
1

00
01

(128) (26)
(256) (26)

1
1

0
1

00
01

(128) (52)
(256) (52)

0
0

0
1

01
02

(256) (15)
(512) (15)

1
1

0
1

01
02

(256) (30)
(512) (30)

0
0

0
1

02
03

(512) (8)
(1024) (8)

1
1

0
1

02
03

(512) (16)
(1024) (16)

Maximum Transfer Capacity
(Bytes/Sector) (Number of Sectors)

290

= 3,328
= 6,656
= 6,656
= 13,312
= 3,840
= 7,680
= 7,680
= 15,360
= 4,096
= 8,192
= 8,192
= 16,384

Final Sector Read
from Disk
26 at Side 0
or 26 at Side 1
26 at Side 1
15 at Side 0
or 15 at Side 1
15 at Side 1
8 at Side 0
or 8 at Side 1
8 at Side 1

VLSI TECHNOLOGY, INC.
VL6765

Table 4.

DDFDC Command Termination Values

Command Phase 10
MultiTrack
(MT)

Result Phase 10

Head
Number
(HD)

Final Sector Transferred
tolfrom Data Bus

Track
Number
(T)

Head
Number
(H)

Sector
Number
(R)

No. of
Data Bytes
(N)

Less than EOT

R + 1

Equal to EOT

T + 1

Less than EOT

R + 1

Equal to EOT

T + 1

Less than EOT

R + 1

Equal to EOT

LSB

Less than EOT

R + 1

Equal to EOT

T + 1

LSB

Notes:
1. NC (No Change): The same value as the one at the beginning of command execution.
2. LSB (Least Significant Bit): The least significant bit of H is complemented.

Result Phase:
R

Status Register 0 (STO)

Status Register 1 (ST1)

Status Register 2 (ST2)

Track Number (T)

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

of the ID fields, it terminates the Write Data command, sets the
DE flag in 5T1 to a 1, and sets bits 7 and 6 in 5TO to 0 and 1,
respectively.
The Write Data command operates in much the same manner
as the Read Data command. Refer to the Read Data command
for the handling of the following items:
• Transfer Capacity
• End of Track (EN) flag
• No Data (ND) flag
• Head Unload Time (HUT) interval

WRITE DATA

• ID information when the processor terminates command
(see Table 4)

A command set of nine bytes places the DDFDC in the Write Data
mode. After the Write Data command has been received the
DDFDC loads the head (if it is unloaded), waits the specified Head
Settling Time (defined in the Specify command), then begins
reading ID fields from the disk. When the four bytes (T, H, R, N)
loaded during the command match the four bytes of the ID field
from the disk, the DDFDC transfers data from the data bus to
the disk Data field.

• Definition of Data Length (DTL) when N

After writing data into the current sector, the DDFDC increments
the sector number (R) by one, and writes into the Data field in
the next sector. The DDFDC continues this multi-sector write
operation until the last byte is written to sector R when R = EOT.
STO bits 7 and 6 are set to 0 and 1, respectively, and ST1 bit
7 (EN) is set to a 1.

= 0 and when N*"O

In the Write Data mode, data transfers from the data bus to the
DDFDC must occur within 27 P.s in the FM mode, and within 13 p's
in the MFM mode. If the time interval between data transfers is
longer than this, then the DDFDC terminates the Write Data command, sets the Over Run (OR) flag in 5T1 to a 1, and sets bits
7 and 6 in 5TO to 0 and 1, respectively.

Command Phase:

The command can also be ter:ninated by a high on Terminal
Count (TC). If TC is sent to the DDFDC while writing into the current sector, then the remainder of the Data field is filled with 00
(zeros). In this case, STO bits 7 and 6 are set to 0 and the command is terminated.
The DDFDC reads the ID field of each sector and checks the CRC
bytes. If the DDFDC detects a read error (incorrect CRC) in one

291

RIW

BYTE

US1

usa

Track Number (T)

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

End of Track (EOT)

Gap Length (GPL)

Data Length (DTL)

VLSI TECHNOLOGY, INC.
VL6765
Command Phase:

Result Phase:
R

Status Register 0 (STO)

R/W

BYTE

Status Register 1 (ST1)

Status Register 2 (ST2)

US1

USO

Track Number (1)

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

WRITE DELETED DATA
The Write Deleted Data command is the same as the Write Data
command except a Deleted Data Address Mark is written at the
beginning of the Data field instead of the normal Data Address
Mark.

Command Phase:
BYTE
7
RIW
W

X X

US1

USO

Track Number (1)

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

End of Track (EOT)

Gap Length (GPL)

Data Length (DTL)

Status Register 0 (STO)

Status Register 1 (ST1)

Status Register 2 (ST2)

Track Number (T)

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector(N)

Number of Data Bytes per Sector (N)

End of Track (EOT)

Gap Length (GPL)

Data Length (DTL)

Result Phase:
R

Status Register 0 (STO)

Status Register 1 (ST1)

Status Register 2 (ST2)

Track Number (T)

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

READ A TRACK
The Read a Track command is similar to the Read Data command except that this is a continuous read operation where all
Data fields from each of the sectors on a track are read and
transferred to the data bus. Immediately after encountering the
Index Hole, the DDFDC starts reading the Data fields as continuous blocks of data. This command terminates when the
number of sectors read is equal to EOT. Multi-track operations
are not allowed with this command.

Result Phase:
R

X X

If the DDFDC finds an error in the 10 or Data CRC check bytes,
it continues to read data from the track. The DDFDC compares
the 10 information read from each sector with the value stored
in the IDR, and sets the ND flag in ST1 to a 1 if there is no match.
If the DDFDC does not find an ID Address Mark on the disk after
it encounters the Index Hole for the second time it terminates the
command, sets the Missing Address Mark (MA) flag in ST1 to
a 1, and sets bits 7 and 6 of STO to 0 and 1, respectively.

READ DELETED DATA
The Read Deleted Data command is the same as the Read Data
command except that if SK = 0 when the DDFDC detects a Data
Address Mark at the beginning of a Data field, it reads all the
data in the sector and sets the CM flag in ST2 to a 1, and then
terminates the command. If SK = 1, then the DDFDC skips the
sector with the Data Address Mark and reads the next sector.

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VLSI TECHNOLOGY, INC.
VL6765
FORMAT A TRACK

Command Phase:
R/W
W

BYTE

US1

usa

Track Number (T)

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

End of Track (EOT)

Gap Length (GPL)

Data Length (DTL)

The ID field for each sector is supplied by the processor in
response to four data requests per sector issued by the DDFDC.
The type of data request depends upon the Non-DMA flag (ND)
in the Specify command. In the DMA mode (ND = 0), the DDFDC
asserts the DMA Request (DRO) output four times per sector.
In the Non-DMA mode (ND = 1), the DDFDC asserts Interrupt
Request (INT) output four times per sector.

Result Phase:
R

The six-byte Format a Track command formats an entire track.
After the Index Hole is detected, data is written on the disk: Gaps,
Address Marks, ID fields and Data fields; all are recorded in either
the double-density IBM System 34 format (MF = 1) or the singledensity IBM 3740 format (MF = 0). The particular format wri.tten
is also controlled by the values of Number of Bytes/Sector (N),
Sectors/Track (ST), Gap Length (GPL) and Data Pattern (D) which
are supplied by the processor during the command phase. The
Data field is filled with the data pattern stored in D.

Status Register 0 (STO)

Status Register 1 (ST1)

Status Register 2 (ST2)

The processor must write one data byte in response to each
request, sending (in the consecutive order) the Track Number (T),
Head Number (H), Sector Number (A) and Number of Bytes/
Sector (N). This allows the disk to be formatted with nonsequential sector numbers, if desired.

Track Number (T)

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

READ 10
The two-byte Read ID command returns the present position of
the read/write head. The DDFDC obtains the value from the first
ID field it is able to read, sets bits 7 and 6 in STO to 0 and terminates the command.

The processor must send new values for. T, H, R, and N to the
DDFDC for each sector on the track. For sequential formatting
R is incremented by one after each sector is formatted, thus, R
contains the total numbers of sectors formatted when it is read
during the result phase. This incrementing and formatting continues for the whole track until the DDFDC, upon encountering
the Index Hole for the second time, terminates the command and
sets bits 7 and 6 in STO to O.

If no proper ID Address Mark is found on the disk before the Index
Hole is encountered for the second time then the Missing Address
Mark (MA) flag in ST1 is set to a 1, and if no data is found then
the ND flag in ST1 is also set to a 1. Bits 7 and 6 in STO are set
to 0 and 1, respectively and the command is terminated.

If the Fault (FLT) signal is high from the FDD at the end of a write
operation, the DDFDC sets the Equipment Check (EC) flag in STO
to a 1, sets bits 7 and 6 of STO to 0 and 1, respectively, and terminates the command. Also, a low (RDY) signal at the beginning
of a command execution phase causes bits 7 and 6 of STO to
be set to 0 and 1, respectively.

During this command there is no data transfer between DDFDC
and the data bus except during the result phase.

Table 5 shows the relationship between N, ST, and GPL for
various disk and sector sizes.

Command Phase:
R/W

BYTE

US1

usa

Command Phase:

Result Phase:
A

Status Register 0 (STO)
2

Status Register 1 (ST1)

Status Register 2 (ST2)

Track Number (T)

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

293

R/W

BYTE

US1

usa

Number of Bytes per Sector (N)

Sectors per Track (ST)

Gap Length (GPL)

Data Pattern (D)

VLSI TECHNOLOGY, INC.
VL6765

Table 5.
Disk
Size

Standard Floppy Disk Sector Size Relationship
Gap Length (GPL)4

Sector Size
Bytes/Sector

No. of Data
Bytes/Sector
(N)

No. of
Sectors/Track
(ST)

ReadlWrlte
Command 1

Format
Command 2

128
256
512
1024
2048
4096

00
01
02
03
04
05

1A
OF
08
04
02
01

07
OE
1B
47
C8
C8

1B
2A
3A
8A
FFFF

MFM3

256
512
1024
2048
4096
8192

01
02
03
04
05
06

1A
OF
08
04
02
01

OE
1B
35
99
C8
C8

36
54
74
FF
FF
FF

128
128
256
512
1024
2048

00
00
01
02
03
04

12
10
08
04
02
01

07
10
18
46
C8
C8

09
19
30
87
FF
FF

MFM3

256
256
512
1024
2048
4096

01
01
02
03
04
05

12
10
08
04
02
01

OA
20
2A
80
C8
C8

OC
32
50
FO
FF
FF

Mode

5V4"

Remarks

Notes:
1. Suggested values of GPL in Read or Write commands to avoid overlapping between Data field and ID field of contiguous sections .
. 2. Suggested values of GPL in Format a Track command.
3. In MFM mode the DDFDC cannot perform a read/write/format operation with 128 bytes/sector (N = 00).
4. Values of ST and GPL are in hexadecimal.

Result Phase:
R

SCAN COMMANDS

Status Register 0 (STO)

Status Register 1 (ST1)

Status Register 2 (ST2)

Track Number (T) *

Head Number (H)*

Sector Number (R)*

Number of Data Bytes per Sector (N)*

The scan commands compare data read from the disk to data
supplied from the data bus. The DDFDC compares the data, and
looks for a sector of data which meets the conditions of DFDD =
Dsus, DFDD :5 Dsus, or DFDD ~ Dsus (D = the data pattern in
hexadecimal). A magnitude comparison is performed (FF =
largest number, 00 = smallest number). The hexadecimal byte
of FF either from the bus or from FDD can be used as a mask
byte because it always meets the condition of the compare. After
a whole sector of data is compared, if the conditions are not met,
the sector number is incremented (R + STP - R), and the scan
operation is continued. The scan operation continues until one
of the following events occur: the conditions for scan are met
(equal, low or equal, or high or equal), the last sector on the track
is reached (EOT) , or TC is received.

* The ID information has no meaning in this command.

294

VLSI TECHNOLOGY, INC.
VL6765

If conditions for scan are met, the DDFDC sets the Scan Hit (SH)
flag in ST2 to a 1, and terminates the command. If the conditions for scan are not met between the starting sector (as specified
by R) and the last sector on the track (EDT), then the DDFDC
sets the Scan Not Satisfied (SN) flag in ST2 to a 1, and terminates
the command. The receipt of TC from the processor or DMA controller during the scan operation will cause the DDFDC to complete the comparison of the particular byte which is in process,
and then to terminate the command. Table 6 shows the status
of bits SH and SN under various conditions of scan.

Table 6.

SCAN EQUAL

Command Phase:
R/W

BYTE

US1

usa

Track Number (T)

Status Register 2
Bit 2 = SN

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

End of Track (EDT)

Comments

Gap Length (GPL)
Sector Test Process (STP)

Scan Status Codes

Command

Bit 3 = SH

Scan Equal

0
1

1
0

DFOO = DBUS
DFOO (j) DBUS

Scan Low or Equal

0
0
1

1
0
0

DFOO = DBUS
DFOO < DBUS
DFOO > DBUS

Result Phase:
1

Status Register 0 (STO)

1
0
0

DFDO = DBUS
DFDO > DBUS
DFOO < DBUS

Status Register 1 (ST1)

Scan High or Equal

0
0
1

If SK = 0 and the DDFDC encounters a Deleted Data Address
Mark on one of the sectors, it regards that sector as the last sector of the track, sets the Control Mark (CM) bit in ST2 to a 1 and
terminates the command. If SK = 1, the DDFDC skips the sector with the Deleted Data Address Mark, sets the CM flag to a
1 in order to show that a Deleted Sector has been encountered,
and reads the next sector.

Status Register 2 (ST2)

Track Number (T)

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

SCAN LOW OR EQUAL

Command Phase:

When either the STP sectors are read (contiguous sectors = 01,
or alternate sectors = 02) or MT (Multi-Track) is set, the last sector on the track must be read. For example, if STP = 02, MT
= 0, the sectors are numbered sequentially 1 through 26, and
the scan command starts reading at sector 21. Sectors 21, 23,
and 25 are read, then the next sector (26) is skipped and the Index
Hole is encountered before the EDT value of 26 can be read.
This results in an abnormal termination of the command. If the
EDT had been set at 25 or the scanning started at sector 20, then
the scan command would be completed in a normal manner.
During a scan command data is supplied from the data bus for
comparison against the data read from the disk. In order to avoid
having the Over Run (OR) flag set in ST1, data must be available
from the data bus in less than 27 itS (FM mode) or 13 its (MFM
mode). If an OR occurs, the DDFDC terminates the command
and sets bits 7 and 6 of STO to 0 and 1, respectively.

R/W

BYTE

US1

usa

Track Number (T)

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

End of Track (EDT)

Gap Length (GPL)

Sector Test Process (STP)

Result Phase:
R

The following tables specify the command bytes and descrih"
the result bytes for the three scan commands.

295

Status Register 0 (STO)

Status Register 1 (ST1)

Status Register 2 (ST2)

Track Number (T)

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

VLSI TECHNOLOGY. INC.
VL6765
During the command phase of the Seek operation the DDFDC
sets the Controller Busy (CB) flag in the MSR to 1; but during
the execution phase the CB flag is set to 0 to indicate DDFDC
non-busy. While the DDFDC is in the non-busy state, another
Seek command may be issued, and in this manner parallel seek
operations may be performed on all drives at once.

SCAN HIGH OR EQUAL
Command Phase:
R/W

BYTE

US1

usa

Track Number (T)

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

End of Track (EOl)

Gap Length (GPL)

Sector Test Process (STP)

No command other than Seek will be accepted while the DDFDC
is sending step pulses to any FDD. If a different command type
is attempted, the DDFDC will set bits 7 and 6 in STO to a 1 and
0, respectively, to indicate an invalid command.
If the FDD is in a not ready state at the beginning of the command execution phase or during the seek operation, then the
DDFDC sets the Not Ready (NR) flag in STO to a 1, sets STO
bits 7 and 6 to 0 and 1, respectively, and terminates the command.
If the time to write the three bytes of the Seek command exceeds
150 /ls, the time between the first two step pulses may be shorter
than the Step Rate Time (SRT) defined by the Specify command
by as much as 1 ms.

Result Phase:
R

Status Register 0 (STO)

Status Register 1 (ST1)

Status Register 2 (ST2)

Track Number (T)

Command Phase:

Head Number (H)

Sector Number (R)

Number of Data Bytes per Sector (N)

RIW

BYTE

US1

usa

New Track Number (NTN)

Result Phase: None.
SEEK
The three-byte Seek command steps the FDD read/write head
from track to track. The DDFDC has four independent Present
Track Registers for each drive. They are cleared only by the
Recalibrate command. The DDFDC compares the Present Track
Number (PTN) which is the current head position with the New
Track Number (NTN), and if there is a difference, performs the
following operation:
If PTN

RECALIBRATE
This two-byte command retracts the FDD read/write head to the
Track 0 position. The DDFDC clears the contents of the PTN
counters, and checks the status of the Track 0 signal from the
FDD. As long as the Track 0 signal (TRKO) is low, the direction
signal (LCTIDIR) output remains low and step pulses are issued
on FR/STP. When TRKO goes high the DDFDC sets the Seek
End (SE) flag in STO to a 1 and terminates the command. If the
TRKO is still low after 256 step pulses have been issued, the
DDFDC sets Seek End (SE) and Equipment Check (EC) flags in
STO to 1s, sets bits 7 and 6 of STO to 0 and 1, respectively, and
terminates the command.

< NTN: Sets the direction output (LCT/DIR) high

and issues step pulses (FRISTP) to the FDD
to cause the read/write head to step in.
If PTN > NTN: Sets the direction output (LCTIDIR) low and
issues step pulses to the FDD to cause the
read/write head to step out.

The ability to do overlap Recalibrate commands to multiple FDDs
and the loss of the RDY signal, as described in the Seek command, also applie~ to the Recalibrate command.

The rate at which step pulses are issued is controlled by the Step
Rate Time (SAT) in the Specify command. After each step pulse
is issued, NTN is compared against PTN. When NTN = PTN,
then the Seek End (SE) flag in STO is set to a 1, bits 7 and 6
in STO are set to 0, and the command is terminated. At this point
DDFDC asserts INT.

Command Phase:

The FDD Busy flag (bit 0-3) in the Main Status Register (MSR)
corresponding to the FDD performing the Seek operation is set
to a 1.
After command termination, all FDD Busy bits set are cleared by
the Sense Interrupt Status command.

R/W

BYTE

US1

USo

Result Phase: None.

296

VLSI TECHNOLOGY. INC.
VL6765

SENSE INTERRUPT STATUS
Interrupt Request (INT) is asserted by the DDFDC when any of
the following conditions occur:
1. Upon entering the result phase of:
a. Read Data command
b. Read a Track command
c. Read ID command
d. Read Deleted Data command
e. Write Data command
f. Format a Track command
g. Write Deleted Data command
h. Scan commands

Command Phase:
RIW

o
o

Result Phase:
R

Status Register 0 (STO)
Present Track Number (PTN)

SPECIFY

2. Ready (RDY) line from the FDD changes state
3. Seek or Recalibrate command termination
4. During execution phase in the Non-DMA mode
INT caused by reasons 1 and 4 above occur during normal
command operations and are easily discernible by the processor.
During an execution phase in Non-DMA mode, bit 5 in the MSR
is set to 1. Upon entering result phase this bit is set to o. Reasons
1 and 4 do not require the Sense Interrupt Status command. The
interrupt is cleared by reading or writing data to DDFDC. Interrupts caused by reasons 2 and 3 are identified with the aid of
the Sense Interrupt Status command. This command resets INT
and sets/resets bits 5, 6, and 7 of STO to identify the cause of
the interrupt. Table 7 defines the seek and interrupt codes.
The Sense Interrupt Status command is used in conjunction with
the Seek and Recalibrate commands which have no result phase.
When the disk drive has reached the desired head position the
DDFDC asserts interrupt output. The host CPU must then issue
a Sense Interrupt Status command to determine the actual cause
of the interrupt, which could be Seek End or a change in ready
status from one of the drives (see example in Figure 4).

The three-byte Specify command sets the initial values for each
of the three internal timers. The Head Unload Time (HUT) defines
the time from the end of the execution phase of one of the read/
write commands to the head unload state. This timer is programmable from 16 to 240 ms in increments of 16 ms (1 = 16 ms,
2 = 32 ms, ... F = 240 ms).
The Step Rate Time (SRT) defines the time interval between
adjacent step pulses. This timer is programmable from 1 to 16 ms
in increments of 1 ms (F = 1 ms, E = 2 ms, D = 3 ms, ...
o = 16 ms.)
The Head load Time (HlT) defines the time between the Head
load (HDl) signal going high and the start of the read/write
operation. This timer is programmable from 2 to 254 ms in
increments of 2 ms (01 = 2 ms, 02 = 4 ms, 03 = 6 ms, ...
7F = 254 ms).
The time intervals are a direct function of the clock (ClK on pin 19).
Times indicated above are for an 8 MHz clock. If the clock is
reduced to 4 MHz (mini-floppy application) then all time intervals
are increased by a factor of two.

Issuing a Sense Interrupt Status command without an interrupt
pending is treated as an invalid command.

The choice of DMA or Non-DMA operation is made by the NonDMA mode (ND) bit. When this bit = 1 the Non-DMA mode is
selected, and when ND = 0 the DMA mode is selected.

Table 7.

Command Phase:
BYTE
7
RIW

STO Seek and Interrupt Code Definition for
Sense Interrupt Status

Status Register 0
(STO) Bits
Interrupt Code
(IC)

Seek End
(SE)

1 6 1 5 14 31 2 1
0 1 0 1 0 10 01 0 1

SRT

HLT

Cause

Normal termination of
Seek or Recalibrate
command

Abnormal termination of
Seek or Recalibrate
command

RDY line changed
state, either polarity

SRT HUT HlT ND -

Step Rate Time
Head Unload Time
Head load Time
Non-DMA mode

Result Phase: None.

297

1
1

0
1

HUT

1 ND

VLSI TECHNOLOGY, INC.
VL6765

Figure 4.

Sense Interrupt Status

I - - Seek (or Recallbrate) Command

Sense Interrupt Status Command -j

: - - Command Phase ---t-- Execution Phase --t-Command Phase-f- Result Phase-1
INT

I
I
I

-u-n un U JIl

U 11

1J It U ffi
l

r---~I----------------~r---------~

WR~
.010

---u

lJLJ

ROM--D~~~~~~______________~nL~

z
'wo

!::~

c
<
w
a:

1-0

Z::l
I-D.
D.O

1-1-

z::!!:

SENSE DRIVE STATUS
This two-byte command obtains and reports the status of the FDDs.
Status Register 3 (ST3) is returned in the result phase and contains the drive status.

Command Phase:
RIW
BYTE
7
W

US1

usa

Result Phase:
R

____~n~~___~

Status Register 3 (ST3)

INVALID COMMAND
If an invalid command (Le., a command not previously defined)
is received by the DDFDC, then the DDFDC terminates the command after setting bits 7 and 6 of STO to 1 and 0, respectively. The
DDFDC does not generate an interrupt during this condition. Bits
6 and 7 (010 and ROM) in the MSR are both set to a 1 indicating
to the processor that the DDFDC is in the result phase and that
STO must be read. A hex 80 in STO indicates that an invalid command was received.
A Sense Interrupt Status command must be sent after a Seek or
Recalibrate interrupt, otherwise the DDFDC considers the next
command to be an invalid command.
In some applications the user may wish to use this command as
a No-Op command, to place the DDFDC in a standby or no operation state.

Command Phase:
RIW
BYTE
7

Invalid Codes

Result Phase:
R

Status Register 0 (STO)

= 80

PROCESSOR INTERFACE
During the command or result phases, the Main Status Register
(MSR) must be read by the processor before each byte of information is transferred to, or from, the DDFDC Data Register. After
each byte of data is written to, or read from, the Data Register,
the processor should wait 12 P.s before reading the MSR. Bits 6
and 7 in the MSR must be a 0 and 1, respectively, before each
command byte can be written to the DDFDC. During the result
phase, bits 6 and 7 of the MSR must both be 1s prior to reading
each byte from the Data Register onto the data bus. Note that
this status reading of bits 6 and 7 of the MSR before each byte
transfer to and from the DDFDC is required in only the command
and result phases and not during the execution phase.
During the result phase all bytes shown in the result phase must
be read by the processor. The Read Data command, for example,
has seven bytes of data in the result phase. All seven bytes must
be read to successfully complete the Read Data command. The
DDFDC will not accept a new command until all seven bytes have
been read. Other commands may require fewer bytes to be read
during the result phase.

298

VLSI TECHNOLOGY, INC.
VL6765

Figure 5.

DDFDC and System Data Transfer Timing

DATA IN/OUT
(010)
(MSR BIT 6)
REQUEST
FOR MASTER
(RQM)
(MSR BIT 7)
WRITE (WR)
READ (RD)

FROM DDFDC TO DATA BUS

FROMDATABUSTO~
I
I

I I
I I
I

NOl

I READY I

I
I

I
I
I

I
I
A

I
I

IB I A

I
I
I

i
I
I

C 10 IBI A

NOTES

DATA REGISTER READY TO BE WRITTEN INTO

~ DATA REGISTER NOT READY TO BE WRITTEN INTO

[£] DATA REGISTER READY FOR NEXT DATA BYTE TO BE READ

INTERRUPT REQUEST MODE
During the execution phase, the MSR need not be read. The
receipt of each data byte from the FDD is indicated by INT high
on pin 18. When the DDFDC is in Non-DMA mode, INT is asserted
during the execution phase. When the DDFDC is in the DMA
mode, INT is asserted at the result phase. The INT signal is reset
by a read (RD low) or write (WR low) of data to the DDFDC.
A further explanation of the INT signal is described in the Sense
Interrupt Status command on page 16. If the system cannot
handle interrupts fast enough (within 13 p.S for MFM mode or 27 p.S
for FM mode), it should poll bit 7 (ROM) in the MSR. In this case,
ROM in the MSR functions as an Interrupt Request (INT). If the
ROM bit is not set, the Over Run (OR) flag in ST1 will be set to
a 1 and bits 7 and 6 of STO will be set to a 0 and 1, respectively.

DATA REGISTER NOT READY FOR NEXT DATA BYTE TO BE READ

the EOT sector is read), INT is asserted to indicate the beginning of the result phase. When the first byte of data is read during the result phase, INT is reset low.

During a write command, the DDFDC asserts DRO as each byte
of data is required. The DMA controller responds to this request
with DACK (DMA Acknowledge) and WR low (write).
When DACK goes low the DMA Request is reset (DRO lOw). After
the execution phase has been completed (TC high or the EOT
sector is written), INT is asserted. This signals the beginning of
the result phase. When the first byte of data is read during the
result phase, the INT is reset low.

FDD POLLING
DMA MODE
When the DDFDC is in the DMA mode (ND = 0 in the third command byte of the Specify command), DRO (DMA Request) is
asserted during the execution phase (rather than INT) to request
the transfer of a data byte between the data bus and the DDFDC.

During a read command, the DDFDC asserts DRO as each byte
of data is available to be read. The DMA controller responds to
this request with DACK low (DMA Acknowledge) and RD low
(read). When DACK goes low the DMA Request is reset (DRO
low). After the execution phase has been completed (TC high or

After the Specify command has been received by the DDFDC,
the Unit Select lines (USO and US1) begin the polling mode.
Between commands (and between step pulses in the Seek Command) the DDFDC polls all the FDD's looking for a change in
the RDY line from any of the drives. If the ROY line changes state
(usually due to the door opening or closing) then the DDFDC
asserts INT. When Status Register 0 (STO) is read (after Sense
Interrupt Status command is issued), Not Ready (NR = 1) will
be indicated. The polling of the RDY line by the DDFDC occurs
continuously between commands, thus notifying the processor
which drives are on- or off-line. Each drive is polled every 1.024 ms
except during readlwrite commands.

299

VLSI TECHNOLOGY, INC
VL6765

Figure 6. DDFDC Formats

FM MODE
FIELD

GAP ...

SYNC

NO. OF BYTES

40x

DATA

lAM

GAP 1

SYNC

28x

INDEX~

lOAM

CYL

SEC

CAe

GAP 2

SYNC

11x

1 - - - - - - - - - - - REPEAT N TIMES

DA~AII

DATA

GAP 3

CAe

GAP4b

FB OR FI

--------------1

MFM MODE
GAP ...

SYNC

lOx

12x

3><

lAM

1
I

GAP 1

SYNC

so><

12><

CYL

lOAM

SEC

CAe

GAP 2

SYNC

22.

12><

DATA All

DATA

1 - - - - - - - - - - - - - - - REPEAT N TIMES

INDEXfL

Figure 7. DDFDC Formats

INDEX
FORMAT

~_ _ _ _ _ _ _ _ _ _ _ _ _ _~{~

IGAP 4aliAM

1GAP 11

1GAP 21

DATA

1GAP 31

"
VCO SYNC

r------,

NOTE: _ _ READ
____ WRITE

300

IGAP4bl

GAP 3

CAe

GAP 4b

VLSI TECHNOLOGY, INC.
VL6765
zao

Figure a. VL6765 DDFDC Interface to

A1-A15

A
KOO-07

- It

I~;:;;"

RST
AO

- l/""

~~Ilel':'l~~'~

\VA

ell ?
~

,)
ZOO
CPU

ROW

DATA

---~~~~RECOVERY
ROO

}

~SO

PS1
WOA
MEMORY

14"
4-

JPRE-COMP

WPfTS
FLTfTRKO

...

CLK

WRITE
CLOCK
GEN

FR/STP
LeTiOIR
RW/SEEK

WCK

r---ROY
..- WE

CLK

INT

....

INT

-c/l.

301

ILOX
HOL
HO

usa

jjIT

..a.

......

MUX

WRITE DATA

MUX

/----OOFOC

READ DATA

.aT

t=:
....

WRITE PROTECT
TWO-SIDE
FAULT
TRACK 0
FAULT RESET
STEP
LOW CURRENT
DIRECTION

R EAOY
WRITE ENABLE
I NOEX
- + H EAO LOAD
.... H EAO SELECT
.... U NIT SELECT 0
~ UNIT SELECT 1

VLSI TECHNOLOGY, INC
VL6765

Figure 9.

Clock Timing

ClK

Figure 10.

Read Cycle Timing

AO,CS

DATA OUT

00-07

INT

Figure 11. Write Cycle Timing

AO,CS

-E0

DATA IN

00-07

INT

302

VLSI TECHNOLOGY, INC.
VL6765

Figure 12.

DMA Operation Timing

~------117

ORO

WR OR RD

.
13 . FDD Write Operation Timing
Figure

WRITE CLOCK
(WCK) t:;:;\

®
WRITE ENABLE
(WE)@
PRESHIFT 0 OR 1
(PSO, PS1)
WRITE QATA
(WDA)

.
14 .
Figure

FDD Read Operation Timing

READ DATA (ROD)

READ DATA WINDOW (ROW) _ _ _ _ _ _ __

~I~~~:R POLARITY DATA WINDOW IS VALID
303

VLSI TECHNOLOGY, INC.
VL6765

Figure 15. Seek Operation Timing

USO,

us,

~__________~ '--_____

SEEK
(RW/SEEK)

DIRECTION
(LCT/DIR)

STEP
(FR/STP)

~-----~------~~
Figure 17. Index Timing

Figure 16. Fault Reset Timing

FAULT RESET
(FR) _ _ _

INDEX
(lOX)

_____

Figure 19. Reset Timing

Figure 18 .. Terminal Count Timing

I
TERMINAL COUNT
(TC)

~
I
I

--t

RESET-rL
(RST)

I
I

---,I

r-®

Figure 20. AC Timing Measurement Conditions
INPUT/OUT

CLOCK

TEST POINT

/I
. ---V 2.0V ;».ovy
0.45V --.-.1\ O.BV
O.BV'''---24V

INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND 0.45 V FOR
A LOGIC "0:' TIMING MEASUREMENTS ARE MADE AT 2.0V FOR
A LOGIC "1" AND O.BV FOR A LOGIC "0:'

3.0V----V 2 .4V

TEST POINT

j'f 2.4V V -

0.3V-A0.65V 0 . 6 5 V " - CLOCKS ARE DRIVEN AT 3.0V FOR A LOGIC "1" AND 0.3V FOR A
LOGIC "0:' TIMING MEASUREMENTS ARE MADE AT 2.4V FOR A
LOGIC "1" AND 0.65V FOR A LOGIC "0:'

304

VLSI TECHNOLOGY, INC.
VL6765

AC CHARACTERISTICS
(Vee = 5.0 Vdc ± 5%, VSS = 0 Vdc,
Ref.
Fig. No.

Clock Period

Clock High

3
4

= O°C to 70°C)

Characteristic
I (8" or 3·1/2" FDDI
(5·1/4" FDDI

Symbol

Alt. Sym.

Min.
120

Unit
ns
ns
ns

¢CY
¢o

Clock Rise Time

¢,
¢f

AO, CS, DACK Valid 10 RD low (Selup)

IAA

RD High 10 AO, CS, DACK Invalid (Hold)

ISLAL
I AHSH

IAA

RD lowWidlh

IAA

250

RD low 10 Dala Valid (Access)

IALAH
I ALOV

I CHCL

Clock Fall Time

lAO

200

RD High 10 Oulpul High Z

I AHOZ

IOF

100

IAI

500

RD High 10 INT High

AO, CS, DACK Valid 10 WR low (Selup)

WR High 10 AO, CS, DACK Invalid (Hold)

IAHIH
I SLWL
I WHSH

IWA

WR low Widlh

I WLWH

Iww

250

Dala Valid 10 WR High (Selup)

low

150

WR High 10 Dala Invalid (Hold)

IOVWH
I WHOX

Iwo

WR High 10 INT High

IWHIH

DRO Cycle Time

IOCY

DRO High 10 RD, WR High (Response)

19
19a

lAW

IWI
I MCY

I MAW

DACK low 10 DRO low (Delay)

IOHXH
I ALOL

lAM

DRO High 10 DACK low (Delay)

IOHAL

IMA

200

DRO High 10 RD low (Delay)

IOHAL

800

DRO High to WR low (Delay)
(8" or 3·1/2" FDD)
WCK Cycle Time
(5-1/4" FDD)

IOHWL
I KCY

IMA
I MW

I
I

ICY

250

2
1
4
2
250

WCK High Widlh

IKHKL

WCK Rise Time

IKLKH

WCK Fall Time

WCK High 10 PSO, PS1 Valid (Delay)

IKHKL
I KHPV

Icp

25a

WCK High 10 WE High (Delay)

IOHEN

ICWE

WCK High 10 WDA High

IPVOH

Ico

WDA High Widlh

IOHOL
IwCY

Iwoo
IwCY

tKHKL -50

I WAO

(8" or 3·1/2" FDD)

2
1
4
2

RDW Cycle Time

RDW Valid 10 RDD High (Selup)

RDD low 10 RDW Invalid (Hold)

IWVAH
I ALWI

I AOW

RDD High Widlh

IAHAL

I AOO

USO, US1 Valid 10 SEEK High (Selup)

Ius

SEEK low 10 USO, US1 Invalid (Hold)

IUVSH
I SLUI

Isu

SEEK High 10 DIR Valid (Selup)

t SHOV

Iso

DIR Invalid 10 SEEK low (Hold)

IOXSL

los

DIR Valid 10 STP High (Setup)

tovTH

tOST

STP low to DIR Invalid (Hold)
STP low to USO, US1 Invalid (Hold)

tTL OX
t TLUX

STP High Width

tTHTL

tSTD
t STU
t STP

41
43

STP Cycle Time

tTCY

tsc

33 3

FR High Width

tFHFL

IDX High Width

tlHIL

tFA
t lOX

Max.
500

ICA
I CLCH

Typ.
125
250

ICY

(5-114" FDD)

5
6

TC High Width

RST High Width

tTHTL

305

ClK

= 8 MHz

ClK

= 8 MHz

ns
ns
ns
J.lS

J.ls

200

ns
ns
ns
J.lS
IS

350

J.ls
(s
ns

100

ns
J.ls
"s
J.ls
uS

ICY
ClK

= 125 ns
= 8 MHz

MFM
MFM
MFM
MFM

0
1
0
1

MFM - 0
MFM - 1
MFM = 0
MFM = 1

ns
ns
ns
J.lS
J.lS
J.lS
J.ls
J.lS
J.ls
J.lS
8

note 1
10

J.lS
J.ls
J.ls
tcy

1
tcy
tre
14
tcy
tRHAL
tAST
1. tsc = 33 J.lS min. IS for different drive units. In the case of the same unit, tsc can range from 1 ms to 16 ms with 8 MHz clock
period, and 2 ms to 32 ms with 4 MHz clock, under software control.

= 100 pF

500

Test
Conditions
CLK - 8MHz
( lK = 4 MHz
ClK = 8 MHz

ClK

= 8 MHz

VLSI TECHNOLOGY, INC.
VL6765

ABSOLUTE MAXIMUM RATINGS·
Symbol

Value

Unit

Supply Voltage

Vee

-0.3 to + 7.0

Input Voltage

VIN

-0.3 to + 7.0

Output Voltage

VOUT

-0.3 to +7.0

Operating Temperature Range

Storage Temperature Range

TSTG

Parameter

o to

+ 70

-55 to + 150

*NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in other sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

Co
Co

OPERATING CONDITIONS
Parameter

Range
5.0V ±5%

Vee Power Supply
Operating Temperature

DC CHARACTERISTICS
(Vee = 5.0 Vdc ± 5%, Vss = 0 Vdc,
Parameter

= O°C to 70°C, unless otherwise noted)
Symbol

Input Low Voltage
Logic
CLK and WCK

VIL

Input High Voltage
Logic
CLKand WCK

V IH

Output Low Voltage

VOL

Output High Voltage

VOH

Vee Supply Current

Icc

Input Load Current

Min

Unit

Test Conditions

V
-0.5
-0.5

0.8
0.65

2.0
2.4

Vee + 0.5
Vee + 0.5

2.4

IlL

Vee

-10

High Level Output Leakage Current

ILOH

Low Level Output Leakage Current

ILOL

-10

Internal Power Dissipation

PINT

1.0

CAPACITANCE

= 25°C; fe = 1 MHz; Vee = OV)
Parameter

Symbol

Max Limit

Unit

Clock Input

CIN (0)

Input

C IN

Output

C OUT

Note: All pins except pin under test tied to ground.

306

= 4.75V, IOL = 2.0 mA
= 4.75V, IOH = -200 pA
Vee = 4.75V
VIN = Vee
VIN = OV
Vee = OV to 5.25V. Vss = OV
VOUT = Vee
Vee = OV to 5.25V. Vss = OV
VOUT = + 0.45V
TA = 25°C

0.45

150

All Inputs

(TA

Max

VLSI TECHNOLOGY, INC.
VL68C4SRlS
CRT CONTROLLER FAMILY

FEATURES

DESCRIPTION

• CMOS technology
-Rev R compatible with MC6845R1,
MC6845 and MC146845
-Rev S compatible with HD6845S

The VL68C45X is a family of CRT
controllers that are widely used in both
bit-mapped and character-mapped
applications for both terminals and
personal computers. VL68C45 family
allows designs to consume less power
through the use of CMOS technology.

• Internal refresh address generation
• Light pen interface

In addition to compatibility with both the
Motorola and Hitachi families, the
VL68C45R also contains enhancements found in the MC6845R1. These
enhancements allow for higher resolution displays without extra external
hardware.

• Character clocks up to 8 MHz
• Bus clocks up to 3 MHz
• Single 5 V power supply

PIN DIAGRAMS
VL68C45R15-PC,CC

VL68C45 RlS-QC

CC11
MAl

VSYNC
HSYNC
RAO
RAl
RA2
RA3
RA4/STB
OSO
OSl

GNO

-RES
LPEN
CCO/MAO
CC1/MAl
CC2IMA2
CC3/MA3
CC4/MA4
CCS/MAS
CC6/MA6
CC7/MA7
CRO/MAS
CR1/MA9
CR2IMA10
CR3/MAll
CR4/MA12
CRS/MA13

GND

HSYN

RAl

CC21MA2

RA3

CC31MA3

RA4ISTB

CC4/MA4

OSO

CCS/MAS

OSl

OS2

CC61MA6

OS2

CC7/MA7

OS3

OS4

CRO/MAS

OS4

OS6
OS7
-CS
RS
E
R/-W
CCLK

OlSEN

LPEN

I ~;~ I -RES I VSYN I RM I RA2

OS3
OSS

CURSOR
VCC

CRllMA9

OSS

CR2IMA10

OS6

CR3IMAll

OS7

-cs

ORDER INFORMATION
Clock Frequency
Part
Number

Bus

Character

VL68C45R-23
VL68C4SS-23

2 MHz

3MHz

VL68C4SR-35
VL68C4SS-3S
VL68C45R-36
VL68C45S-36
VL68C4SR-38
VL68C4SS-38

5MHz
3MHz

6 MHz

Package

To specify package type, add the
appropriate suffix to the part number:
PC = Plastic DIP
CC = Ceramic DIP
QC = Plastic Leaded Chip Carrier (PLCC)

8MHz

Note: Operating temperature range is O°C to +70°C.

307

VLSI TECHNOLOGY, INC.
VL68C45RIS

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number (DIP)

Signal
Description

Enable - Input that is used as a data strobe; does not have to be a free-running clock. This
capability allows the VL68C45 to interface with other non-6800/6500-type microprocessors.

R/-W

Read/-Write - Input that, when high, allows the processor to read the data supplied by the
VL68C45; when this signal is low, the processor writes into the VL68C45.

-CS

-Chip Select - Input that, when high, deselects VL68C45; when this signal is low, the
VL68C45 is selected. This signal is typically connected to the system address bus either
directly or through an address decoder.

Register Select - Input that, when low, selects the Address Register of the VL68C45 for a
write operation. When this signal is high, an internal register of the VL68C45 specified by the
contents of the address register is selected.

DO - D7

26 - 33

Data Bus - Eight bidirectional data lines that are used for transferring data between the
microprocessor and the VL68C45. These lines are normally high-impedance, except during
read and write cycles when the chip is selected.

CCO/MAO CC5/MA13

4 -17

Video Memory Address - Active-high output signals that are used to address the video
display memory in binary addressing mode. These memory addresses are generated in a
binary sequential fashion.
In row/column addressing mode, MAO-MA7 function as column addresses, and MA8-MA 13
function as row addresses.

RAORA4/STB

34 - 38

Raster Address - Active-high output signals that are used as address lines to the external
character generator ROM. In the transparent addressing mode, RA4 functions as an activehigh output strobe.

HSYNC

Horizontal Sync - Active-high TIL-compatible output signal that is used to determine the
horizontal position of the displayed text. VSYNC may be used to drive a CRT monitor directly
or may be used for composite video generation. VSYNC position is fully programmable.

VSYNC

Vertical Sync - Active-high, TIL-compatible output signal that is used to determine the
vertical position of the displayed text. VSYNC may be used to drive a CRT monitor directly or
may be used for composite video generation. VSYNC position is fully programmable.

DISPLAY

Display Enable - TIL-compatible output that, when high, indicates that the VL68C45 is
generating active display information. The number of horizontal displayed characters and the
number of vertical displayed rows are both fully programmable and together are used to
generate the Display Enable signal.

CURSOR

Cursor - TIL-compatible output that when high, indicates a valid cursor address to the
external video processing logic.

LPSTB

Light Pen Strobe - high impedance, edge-sensitive input signal that latches the current
refresh address into the light pen register. Latching occurs on the low-to-high transition edge.

CCLK

Character Clock - Input signals derived from the external dot clock, that is used as the time
base for all internal count and control functions.

-RES

-Reset - Input signal that when low, resets all internal counters. All scan and video outputs
are low and all control registers are unaffected. RES can be used to synchronize display
frame timing with the line frequency.

VCC

GND

Power Supply Voltage is 5 V.
Ground - Supply and signal ground

308

VLSI TECHNOLOGY, INC.
VL68C45RIS

FUNCTIONAL
DESCRIPTION
The VL68C45 CRT Controller (CRTC)
consists of programmable horizontal and
vertical timing generators, programmable linear address registers, programmable cursor logic, a light pen capture
register and control circuitry for interface
to a processor bus.
All CRTC timing is derived from the
character clock (CCLK), which is usually
the output of an external dot rate
counter. Coincidence circuits internal to
the chip continuously compare counter
contents to the programmed register file
(RO-R17) for generation of Horizontal
Sync, Vertical Sync, Display Enable,
Cursor and other signals required to
interface to a CRT display.
The linear address generator is also
driven by the CCLK and locates the
positions of characters of memory. The
CRTC addresses the memory in the
binary sequential fashion. Using the
start address register, hardware
scrolling through the 16k character
memory is possible. The linear address
generator continues to increment during
the blanking period, so memory refresh
can be performed during the blanking
periods. The linear address generator
repeats the same sequence of addresses for each scan line of a character row. Although the linear address
generator continues to increment during
the horizontal and blanking periods, the

correct address for the first displayed
character or row is always maintained.

effectively doubles the given band width
of the CRT monitor.

The Cursor logic determines the cursor
location, size and blink rate on the
screen.

Care must be taken when using e~her
interlace mode to avoid an apparent
flicker effect. This flicker effect is due to
the doubling of the refresh time for all
scan lines since each field is displayed
alternately and may be minimized w~h
proper mon~or design i.e., longer
persistence phosphors.

The Light Pen Strobe latches the
current contents of the address counter
into the light pen register on low-to-high
transition.
INTERLACE MODE SELECTION
In the normal sync mode (non-interlace), only one field is available, as
shown in Figure 1a. Each scan line is
refreshed at the VSYNC frequency (50
or 60 Hz).
Two interlace modes are available as
shown in Figure 1b and Figure 1c. The
frame time is divided between even and
odd alternating fields. The horizontal
and vertical timing relationship (VSYNC
delayed by one-half scan line time)
results in the displacement of scan lines
in the odd field with respect to the even
field.
In the interlace sync mode, the same
information is painted in both fields, as
shown in Figure 1b. This is a useful
mode for filling in a character to enhance readability.
In the interlace sync and video mode,
as shown in Figure 1c, alternating lines
of the character are displayed in the
even field and the odd field. This

VL68C45R REGISTER FILE
DESCRIPTIONS
The 19 registers of the CRTC may be
accessed through the data bus. Only
two memory locations are required, as
one location is used as a pointer to
address one of the remaining 18
registers. These 18 registers control
horizontal timing, vertical timing,
interlace operation and row address
operation. They also define the cursor,
cursor address, start address and light
pen register. The register addresses
and sizes are shown in Table 1.
ADDRESS REGISTER (AR)
The Address Register is a 5-bit wr~e
only register used as an "indirect- or
"pointer" register. It contains the
address of one of the other 18 registers.
When both RS and -CS are low, the
Address Register is selected. When
-CS is low and RS is high, the register
pointed to by the address register is
selected.

FIGURE 1a.
NORMAL SYNC

FIGURE 1b.
INTERLACE SYNC

FIGURE 1c.
INTERLACE SYNC AND VIDEO

SCAN LINE ADDRESS

0-----------------------------0

0
0
--9------€r-1

o
2

--9-------&-2
--&------&-3

--&-e -e- -& -&-4
0
0
--&- - - --&-5

--&- - - ---9--6
--&- - ----&-7
EVEN
FIELD

ODD
FIELD

309

-B------B--1
0
0

--6-------9--3
0 0 0 0 0
--&------9--5

0
0
--&------9--7

0---------------------------1
2---------------------------3
4---------------------------11
6---------------------------7

EVEN
FIELD

ODD
FIELD

VLSI TECHNOLOGY, INC.
VL68C45RIS

VL68C45R REGISTER FILE
DESCRIPTIONS (Cant.)
HORIZONTAL TOTAL REGISTER (RO)
This 8-bit write-only register determines
the horizontal sync (HSYNC) frequency
by defining the HSYNC period in
character times. It is the total of the
displayed characters plus the nondisplayed character times (retrace)
minus one.
HORIZONTAL DISPLAYED
REGISTER (R1)
This 8-bit write-only register determines
the number of displayed characters per
line. Any 8-bit number may be programmed as long as the contents of RO
are greater than the contents of R1.
HORIZONTAL SYNC POSITION
REGISTER (R2)
This 8-bit write-only register controls the
HSYNC position, which defines the
horizontal sync delay (front porch) and
the horizontal scan delay (back porch).

When the programmed value of this
register is increased, the display on the
CRT screen is shifted to the left. When
the programmed value is decreased,
the display is shifted to the right. Any 8bit number may be programmed as long
as the sum of the contents of R2 and
R3 is less than the contents of RO. The
contents of R2 must be greater than R1.
SYNC WIDTH REGISTER (R3)
This 8-bit write-only register determines
the width of the HSYNC pule. The
vertical sync pulse width is fixed at 16
scan-line times. HSYNC pulse width
may be programmed from 1 to 1S
character clock periods, thus allowing
compatibility with the HSYNC pulse
width specifications of many different
monitors. If zero is written into this
register, no horizontal sync is provided.
HORIZONTAL TIMING SUMMARY
The difference between RO and R1 is
the horizontal blanking interval. This

interval in the horizontal scan period
allows the beam to return (retract) to the
left side of the screen. The retrace time
is determined by the monitor horizontal
scan components. Retrace time is less
than the horizontal blanking interval.
A good rule of thumb is to make the
horizontal blanking about 20% of the
total horizontal scanning period for a
CRT. In inexpensive TV receivers the
beam over-scans the display screen so
that aging of parts does not result in
underscanning. Because of this, the
retrace time should be about one-third
the horizontal scanning period. The
horizontal sync delay is typically
programmed with a 1 :2:2 ratio.
VERTICAL TOTAL REGISTER (R4)
AND VERTICAL TOTAL ADJUST
REGISTER (RS)
The vertical sync (VSYNC) frequency is
determined by both R4 and RS. The
calculated number of character row

TABLE 1. VL68C45R INTERNAL REGISTER ASSIGNMENTS
Register File

Program
Unit

Read

Notes:
1. The interlace bits are described in Table 2.
2. Bit 5 of the cursor start raster register is used for blink period, control, and bit 6 is used to select blink or no-blink.
3. Registers R4, R6 and R7 in the VL68C45R are eight bits wide, instead of seven, for compatibility with the Motorola 6845R1.

310

VLSI TECHNOLOGY, INC.
VL68C45RIS

VL68C45R REGISTER FILE
DESCRIPTIONS (Cont.)
times is usually an integer plus a
fraction to get exactly a 50 Hz or 60 Hz
vertical refresh rate. The integer
number of character row times minus
one is programmed into the 7-bit writeonly vertical total register (R4). The
fraction of character line times is
programmed into the 5-bit write-only
vertical total adjust register (R5) as the
number of scan lines required.
VERTICAL DISPLAYED REGISTER
(R6)
This 7-bit write-only register specifies
the number of character rows displayed
on the CRT screen, and is programmed
in character row times. Any number
smaller than contents R4 may be
programmed into R6.
VERTICAL SYNC POSITION REGISTER (R7)
This 7-bit write-only register controls the
position of vertical sync with respect to
the reference. It is programmed in
character row times. When programmed value of this register is
increased, the display position of the
CRT screen is shifted up. When the
programmed value is decreased, the
display position is shifted down. Any
number equal to or less than the
contents of R4 and greater than or
equal to the R6 may be used.
INTERLACE MODE AND SKEW
REGISTER (RS)
The VL68C45R only allows control of
the interlace modes as programmed by
the low-order two bits of this write-only
register. Table 2 shows the interlace
modes available to the user. These
modes are selected using the two low
order bits of this 6-bit write-only register.
TABLE 2: INTERLACE MODE
REGISTER
Bit1 Bit2 Mode

Normal Sync Mode

(Non-interlace)

Interlace Sync Mode

Interlace Sync and Video Mode

There are restrictions on the programming of the VL68C45R registers for
interlace operation:

1. The Horizontal Total Register (RO)
value must be odd (Le., and even
number of character times).
2. For interlace sync and video mode
only, the Maximum Scanline
Address Register (R9) value must be
odd (Le., an even number of scan
lines).
3. For interlace sync and video mode
only, the number (Nvd) programmed
in to the Vertical Display Register (R6)
must be one-half the actual number
required. The even-numbered scan
lines are displayed in the even field and
the off-numbered scan lines are
displayed in the odd field.
4. For interlace sync and video mode
only, the Cursor Start Register (R1 0
and Cursor End Register (R11) must
both be even or odd, depending on
which field the cursor is to be displayed
in. A full block cursor will be displayed
in both the even and the odd field when
the Cursor End Register (R11) is
programmed to a value greater than the
value in the Maximum Scan Line
Address Register (R9).
MAXIMUM SCAN LINE ADDRESS
REGISTER (R9)
This 5-bit write-only register determines
the number of scan lines per character
row, including the spacing, thus
controlling operation of the row address
counter. The programmed value is a
maximum address and is one less than
the number of scan lines.

CURSOR CONTROL
REGISTERS
CURSOR START REGISTER (R10)
AND CURSOR END REGISTER (R11)
These registers allow a cursor of up to
32 lines in height to be placed on any
scan line of the character block.
Register R1 0 is a 7-bit write-only
register used to define the start scan
line and the cursor blink rate. Bits 5
and 6 of the Cursor Start Address
Register control the cursor operation as
shown in table 3. Non-display, display,
and two blink modes (16 times or 32
times the field period) are available.
Register R11 is as-bit write-only
register that defines the last scan
cursor.
When an external blink feature on
characters is required, it may be

311

TABLE 3. CURSOR START REGISTER
Bit6 BitS Cursor Display Mode

Non-blink

Cursor Non-display

Blink, 1116 field rate

Blink, 1/32 field rate

necessary to perform cursor blink
externally so that both blink rates are
synchronized. Note that an invert/noninvert cursor is easily implemented by
programming the CRT for a blinking
cursor and externally inverting the video
signal with an exclusive-OR gate.
CURSOR REGISTER (R14-H, R15-L)
This 14-bit read/write register pair is
programmed to position the cursor
anywhere in the refresh RAM area, thus
allowing hardware paging and scrolling
through memory without loss of the
original cursor position. It consists of an
8-bit low-order (MAO-MA7) register and a
6-bit high-order (MA8-MA 13) register.

START ADDRESS AND
LIGHT PEN REGISTERS
START ADDRESS REGISTER (R12-H,
R13-L)
This 14-bit write-only register pair
controls the first address output by the
CRTC after vertical blanking. It consists
of an 8-bit low-order (MAO-MA7) register
and a 6-bit high-order (MA8-MA13)
register. The start address register
determines which portion of the refresh
RAM is displayed on the CRT screen.
Hardware scrolling by character or page
may be accomplished by modifying the
contents of this register.
LIGHT PEN REGISTER (R16-H,
R17-L)
This 14-bit read-only register pair
captures the refresh address output by
the CRTC on the positive edge of a
pulse input to the LPSTB pin. It consists
of an a-bit low-order (MAO-MA7) register
and a 6-bit high-order (MA8-MA13)
register. Since the light pen pulse is
asynchronous with respect to refresh
address timing, an internal synchronizer
is designed into the CRTC. Due to
delays in this circuit, the value of R16
and R17 will need to be corrected in
software. (See the bus timing diagram in
the Timing Characteristics section).

VLSI TECHNOLOGY, INC
VL68C45RIS

TABLE 4. VL68C45S INTERNAL REGISTER ASSIGNMENTS, (Nota 1)
-CS

x x x x x

Address Register

Program Unit

READ WRITE

Horizontal Total"

Character

0 0 1

Horizontal
Displayed

Character

Horizontal Sync"
Position

Character

Sync Width

Vertical-Raster,
HorizontalCharacter

Vertical Total"

Line

Vertical Total Adjust

Raster

0 1 1 0

Vertical Displayed

Line

Vertical Sync"
Position

Line

Interlace & Skew

0 0

Maximum Raster
Address

Raster

R10

Cursor Start Raster

Raster

R11

Cursor End Raster

Raster

0 0

R12

Start Address (H)

0 1

R13

Start Address (L)

R14

Cursor (H)

R15

Cursor(L)

0 0

R16

Light Pen (H)

0 0 0 1

R17

Light Pen (L)

Note:
1. 0 = yes; x = no

312

wv3

wv2

wv1

wvO

wh3

wh2 wh1

whO

VLSI TECHNOLOGY, INC.
VL68C45RIS

VL68C45S REGISTER FILE
DESCRIPTIONS (Cant.)
ADDRESS REGISTER (AR)
This is a 5-bit register that is used to
select 18 internal control registers (ROR11). Its contents are the address of
one of 18 internal control registers.
Programming the data from 18 to 31
produces no results. Access to RO-R11
requires writing the address of the
corresponding control register into this
register. When RS and CS are LOW,
the address is selected.
HORIZONTAL TOTAL REGISTER (RD)
This a-bit register is used to program
the total number of horizontal characters per line, including the retrace
period. The data value should be
programmed according to the specification of the CRT. When M is the total
number of characters, (M-1) must be
programmed into this register. When
programming for interlace mode, M
must be even.
HORIZONTAL DISPLAYED
REGISTER (R1)
This 8-bit register is used to program
the number of horizontal displayed
characters per line. Any 8-bit number
that is smaller than that of hor~zontal
total register contents can be programmed.
HORIZONTAL SYNC POSITION
REGISTER (R2)
This a-bit register is used to program
horizontal sync position as multiples of
the character clock period. Any a-bit
number that is lower than the horizontal
total register contents can be programmed. When H is the character
number of the horizontal sync position,
(H-1) must be programmed into this
register. When the programmed value

of this register is increased, the display
position on the CRT screen is shifted to
the left. When the programmed value is
decreased, the position is shifted to the
right. Therefore, the optimum horizontal
position can be determined by this
value.
SYNC WIDTH REGISTER (R3)
This 8-bit register is used to program
the horizontal sync (HS) pulse width
and the vertical sync (VS) pulse width.
The horizontal sync pulse width is
programmed in the lower four-bits as
multiples of the character clock period
(see Table 5); a zero cannot be
programmed. The vertical sync pulse
width is programmed in the higher four
bits as multiples of the raster period
(see Table 6). When zeroes are
programmed in the higher four bits, a
16-raster period is specified~
VERTICAL TOTAL REGISTER (R4)
This l-bit register is used to program
the total number of lines per frame,
including vertical retrace period. The
data and its value should be programmed according to the specification
of the CRTC. When N is the total
number of lines, (N-1) must be programmed into this register.
VERTICAL TOTAL ADJUST
REGISTER (RS)
This 5-bit register is used to program
the optimum number to adjust the total
number of rasters per field. This
register enables more precise control of
the deflection frequency.
VERTICAL DISPLAYED REGISTER

(RG)
This l-bit register is used to program
the number of displayed character rows
on the CRT screen. Any l-bit number

that is smaller than that of vertical total
register contents can be programmed.
VERTICAL SYNC POSITION
REGISTER (R7)
This l-bit register is used to program
the vertical sync position on the screen
as multiples of the horizontal character
line period. Any number that is equal to
or less than the vertical total register
content can be programmed. When V
is the character number of vertical sync
position, (V-1) must be programmed to
this register. When programmed value
of this register is increased, the display
position is shifted up. When the
programmed value is decreased, the
position is shifted down. Therefore, the
optimum vertical position may be
determined by this value.
INTERLACE AND SKEW REGISTER
(RS)
This register is used to program raster
scan mode and skew (delay) of the
Cursor signal and Display Enable
signals.
INTERLACE MODE PROGRAM BITS
(V,S)
Raster scan mode is programmed (see
Table 1) by the V and S bits of Ra. In
the non-interlace mode, duplicate
scanning is done of the rasters of even
number field and odd number field. In
the interlace sync mode, the rasters of
the odd number field are scanned in the
middle of the even number field. The
same character pattern is then displayed in two fields. In the interlace
sync and video mode, the raster scan
method is the same as in the interlace
sync mode, but it is controlled to display
different character patterns in two fields.

Table 4 Additional Notes:
1. The registers marked·: (written value) = (specified value)-1
2. Written value of R9:
a) Non-Interlace mode and Interlace Sync Mode (written value Nr) "" (specified value)-1
b) Interlace sync and video mode: (Written value Nr) = (specified value) -2
3. CO and C1 specify skew of CURSOR output signal. DO and 01 specify skew of Display Enable output signal. When S is
one, V specifies video mode. S specifies the Interlace sync mode.
4. B specifies cursor blink.
P specifies the cursor blink period.
5. wvO-wv3 specify the pulse width of the vertical sync signal. whO - wh3 specify the pulse width of the horizontal sync signal.
6. RO is normally programmed to be an odd number in interlace mode.

313

VLSI TECHNOLOGY, INC.
VL68C45RIS

VL68C45S
REGISTER FILE DESCRIPTIONS (Cont.)
TABLE 5- PULSE WIDTH OF HORIZONTAL SYNC SIGNAL
VSW/HSW Register (R3)
Bit3

Bit2

Bit1

BitO

HSW Pulse Width
(multiples of char clock period)

Not Allowed

TABLE 7: INTERLACE MODE BITS
(BITS 1 AND 0 of R8)

Bit1

S
Bit2

(Non-interlace)

Interlace Sync Mode

Interlace Sync and
Video Mode

Normal Sync Mode

SKEW PROGRAM BITS
(C1 ,CO,01 ,DO)
These bits are used to program the
skew (delay) of the Cursor and Display
Enable signals.

TABLE 6: PULSE WIDTH OF VERTICAL SYNC SIGNAL
VSW/HSW Register (R3)

Mode

Skew of these two kinds of signals is
programmed separately. The skew
function is used to provide an on-chip
delay for the output timing of the Cursor
and Display Enable Signals to provide
the time required to access refresh
memory, character generator or pattern
generator, and to ensure that they are

Bit7

Bit6

BitS

Bit4

VSW Pulse Width
(multiples of raster period)

01
BitS

DO
Bit4

One-character Skew

Two-character Skew

Non-output

TABLE 8: DISPLAY ENABLE SKEW
BIT (BITS 5 AND 4 OF R8)
Display Enable Signal
Non-Skew

C1
Bit7

CO
Bit6

One-character Skew

Two-character Skew

Non-output

TABLE 9: CURSOR SKEW BITS
(BITS 7 & 6 OF R8)

314

Display Skew
Non-Skew

VLSI TECHNOLOGY, INC.
VL68C45RIS

VL68C45S REGISTER FILE
DESCRIPTIONS (Cent.)
in phase with the serial video signal.
MAXIMUM RASTER ADDRESS
REGISTER (R9)
This 5·bit register is used to program
the Maximum Raster Address. This
register defines total number of rasters
per character, including space.
This register is programmed as follows:
1. Non-Interlace Mode,
Interlace Sync Mode: When the total
number of rasters is RN, (RN-1)
must be programmed.

defined as follows in Table 10.

light pen detects.

CURSOR START RASTER REGISTER
(R10)
This 7-bit register is used to program
the cursor start raster address and the
cursor display mode. The lower five
bits program the raster address and the
higher two bits program the display
mode (see table 11).

CONSIDERATIONS IN UPDATING
REGISTERS
The value programmed into the internal
registers directly controls the CRT.
Consequently, the display may flicker
on the screen when the contents of the
registers are changed from the bus side
asynchronously with display operation.

TABLE 11: CURSOR DISPLAY
MODE (BITS 6 AND 5 OF R10)

RESTRICll0NS ON PROGRAMMING
INTERNAL REGISTERS
1. ~ Nhd s Nht + 1 ~ 256
2. 0 s Nvd s Nvt + 1 ~ 128
3. 0 s Nhsp sNht
4. 0 sNvsp s Nvt, Note 1
5. 0 s NCSTART s NCEND s Nr (noninterlace, interlace sync mode)
O,NCSTART ~ NCEND s Nr +1
(interlace and video mode)
6.2 s Nrs30
7.3 s Nht (except non-interlace mode)
5 s Nht (non-interlace mode only)

BitS

Non-Blink

Cursor Non-Display

Blink, 1/16 Field Rate

Blink, 1/32 Field Rate

2. Interlace Sync and Video Mode:
When total number of rasters is RN,
(RN-2) must be programmed.
The total number of rasters in noninterlace mode, interlace sync mode
and interlace sync and video mode is
TABLE 10:
RASTER COUNT IN
INTERLACE AND
NON-INTERLACE MODES

B
Blt6

Cursor Display Mode

Note:
The blink sequence is follows:

Light

Dark

(16 x or 32 x the field period)

o______ Total number of rasters 5
_ _ _ _ _ _ Programmed value Nr = 4

2 _ _ _ _ _ _ (The same as displayed
total number of rasters)

3 _ _ _ _ __
4 _ _ _ _ __
Raster Address
INTERLACE SYNC MODE

Total number of rasters 5

-----------0

programmed value
Nr=4

In the interlace sync
mode, total number of
rasters in both the
even and odd fields is
ten. On programming,
the half of it is defined
as total number of
rasters.

-----------1
2

-----------2
3

-----------3
4 _ _ _ _ __

-----------4
Raster Address
INTERLACE SYNC AND VIDEO MODE

Total Number of Rasters 5

- - - - - - - - - - - 1 Programmed Value
Nr=3

CURSER END RASTER REGISTER
(R11)
This register is used to program the
cursor end raster address.
START ADDRESS REGISTER
(R12,R13)
This register pair is used to program the
first address of refresh memory read
out. Paging and scrolling are easily
performed using this register. This
register can be read but the higher 2bits of R12 are always zero.
CURSOR REGISTER (R14, R1S)
These two readlwrite registers store the
cursor location. The higher 2 bits of
R14 are zero.

UPDATING THE CURSOR REGISTER
Writing into this register at frequent
intervals for moving the cursor should
be performed during horizontal and
vertical retrace periods.
UPDATING THE START ADDRESS
REGISTER
Writing into the start address register at
frequent intervals for scrolling and
paging should be performed during
horizontal and vertical display periods.

It is desirable to avoid programming any
registers besides the cursor and Start
Address Register during display
operations.

LIGHT PEN REGISTER (R16, R17)
These read-only registers are used to
capture the detection address of the
light pen. The higher 2 bits of R16 are
always zero. The value of R16 and R17
needs to be corrected by software
because there is a time delay from the
address output by the CRTC to the
signal input to its LPSTB pin that the

2
(Total number of
___________ 3 rasters displayed in
the even field and the
odd field)
4
Raster Address

In the interlace mode, pulse width is changed + 1/2 raster time when vertical sync signal extends over two fields.

315

VLSI TECHNOLOGY, INC.
VL68C45RIS

VL68C45 CHARACTERISTICS
SYSTEM DIAGRAM
VIDEO TIMING CONTROL

FIGURE 1. TEST LOAD

vee
2.4KQ

----..---1<]1-1

- -......-

R=11 KQ FOR DBO-OB7
R = 24 K Q FOR ALL OTHER OUTPUTS
C=130pFTOTAL FOR 00-07
C=30pF ALL OTHER OUTPUTS

316

VLSI TECHNOLOGY, INC.
VL68C45RIS

TABLE 12. CRTC BUS TIMING CHARACTERISTICS

VL68C45R-23
VL68C45S-23

VL68C45R-35
VL68C45S-35
VL68C45R-36
VL68C45S-36
VL68C45R-38
VL68C45S-38
MIn

Symbol

Parameter

MIn

tCYC

Cycle Time

500

333

pWEL

Pulse Width, E Low

190

140

pWEH

Pulse Width, E High

200

150

Clock Rise Time

Clock Fall Time

tAH

Address Hold Time (RS)

Max

UnIt

tAS

RS Setup Time

tCS

R/-W, CS Setup

tCH

R/-W, CS Hold Time

tDHR

Read Data Hold Time

tDHW

Write Data Hold Time

tDDR

Peripheral Output Delay Time

tDSW

Peripheral Setup Time

0
60

150

0
60

FIGURE 2_ BUS TIMING

14----tDDR----~

READ
DATA
tDSW---+-_---I~

WRITE
DATA

--+---JJ

NOTES:
1. VOLTAGE LEVELS SHOWN ARE V1~O.4V. Vh~2.4V
2. MEASUREMENT POINTS SHOWN ARE O.BV AND 2.0V.

317

ns
ns

130

ns
ns

VLSI TECHNOLOGY, INC.
VL68C45RIS

TABLE 13. CRTC VIDEO TIMING CHARACTERISTICS
VL68C45R-23
VL68C45S-23

VL68C45R-35
VL68C45S-35
Min

VL68C45R-36
VL68C45S-36

VL68C45R-38
VL68C45S-38

Min

Symbol

Parameter

Min

pWCL

Clock Pulse Width, Low

150

100

150

100

Max

pWCH

Clock Pulse Width, High

Clock Frequency

Clock Rise Time

Clock Fall Time

Max

Unit
ns

56
56

MHz

tMAD

Memory Address Delay Time

160

140

100

tRAD

Raster Address Delay Time

160

140

100

tOTO

Display Timing Delay Time

250

200

100

tHSD

Horizontal Sync Delay Time

250

200

100

tVSD

Vertical Sync Delay Time

250

200

100

tCDD

Cursor Display Delay Time

250

200

100

FIGURE 3. VIDEO TIMING
~--------------------------------------------------------------------~------------------------------------------------------------~

14-----pwcL-----+i

1~.~---------------------pWCH-------------------~

CHARACTER
CLOCK
tR

MA()'MA13

RA()'RA4

____~---------'

~------------------------_

.... --------------+---------J

~------------------------

....

CURSOR

NOTES:
TIMING MEASUREMENTS ARE REFERENCED TO AND
FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH
VOLTAGE OF 2.0 VOLTS UNLESS OTHERWISE SPECIFIED

318

--------------~--------~

VLSI TECHNOLOGY, INC
VL68C45RIS

TABLE 14. CRTC LIGHT PEN TIMING CHARACTERISTICS

VL6BC45R·23
VL6BC45S-23

VL6BC45R·35
VL6BC45S·35
VL6BC45R·36
VL6BC45S·36
VL6BC45R·3B
VL6BC45S-38

Symbol

Parameter

pwLPH

Light Pen Strobe Pulse Width

tLPD1

Light Pen Display Time 1

120

tLPD2

Light Pen Display Time 2

Min

Max

Min

Max

Unit

FIGURE 4: LIGHT PEN TIMING

CHARACTER
CLOCK

MAG-MA13

LPSTB

M+2

-------------1----....,.

L.._---+-----.... ------~

_~I___-<.....---=OUT

AXD

0110

VL7C212A-QC

L...-_ _-:.::
RXCK

SCK

-AD
-WR
4
TEST 1

N.C.
TEST 2

6
7
8

RXCK
AUDIO OUT

3 2

CLOCK
GENERATOR

1 282726

•

XTAl2

XTAL1

N.C.

-WR

22
21

N.C.

N.C.
-AD

RXA1

SCK

ORDER INFORMATION
Part
Package

Number

12 1314 1516 1718

VL7C212A-PC Plastic DIP
VL7C212A-QC Plastic Leaded Chip Carrier (PLCC)
Note: Operating temperature range is O°C to +70°C.

321

XTAL2
TXCKO
TXCK1

VLSI TECHNOLOGY, INC.
VL7C212A

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number (Note)

Signal
Description

TXD

Transmit Data- Data on this input is modulated by the modem and output on TXOUT pin.
A logic low is space and a logic high is mark.

RXD

Receive data- The modem demodulates the received carrier and outputs data on this pin.
A logic low level is space and a logic high level is mark. The controller can force the
demodulator output to the mark state by sending the code 02.

0110

Data 1/0- Data is shifted in serially when WR is low on rising edges of SCK clock. Data is
transferred to a latch when WR goes high. Up to seven data bits can be sent. Input
codes are defined in Table 1. Data is read from the modem serially when RD is low, on
rising edges of SCK clock. Up to four data bits can be read. Output codes are defined in
Table 1.

-WR

Strobe output from the controller for shifting data to the modem.

-RD

Strobe output from the controller for serially reading data from the modem.

SCK

Serial shift clock is applied to this pin. It is normally high until data is sent to, or read
from, the modem.

TXOUT

Transmit data carrier output.

RXA1, RXA2

9,10

Received data carriers.

AUDIO OUT

Output of the hybrid is passed through a programmable attenuator and brought out on
this pin. Four levels of received signal can be programmed using the control codes listed
in Table 1.

XTAL1, XTAL

20,21

Pins for connecting a 7.3728 MHz crystal. An external clock signal can be applied to the
XTAL1 pin.

CKOUT

Buffered crystal oscillator signal is output on this pin. It can drive one LS TIL load.

TXCKO

Transmitter Clock Output- In high speed, synchronous internal mode, this output supplies
a 1200 Hz clock to the DTE.

TXCK1

In high speed, synchronous external mode this pin is an input for receiving a 1200 Hz
clock from the DTE.

RXCK

Receiver Clock Output- In high speed, synchronous, external mode, the modem supplies
a 1200 Hz clock on this output.

VCC

+ 5 V power supply.

VSS

- 5 V power supply.

DGND

Digital ground.

AGND

Analog ground.

TEST1,2

4,5

Used by VLSI for testing. Make no connection to these pins. They must be left floating.

N.C.

8,19

No Connect- No internal connection is made to these pins and they may be left floating.

Note: Pin numbers refer to the DIP package.

322

VLSI TECHNOLOGY, INC.

FUNCTIONAL
DESCRIPTION
With the addition of a digital controller,
such as an 8-bit microcontroller and a
data access arrangement (DAA), a
highly cost effective, integrated, intelligent modem can be built. When used
with the VLSI VL7C213A modem
controller, which is an 8-bit processor
combined with a UART, a complete
Hayes command set compatible modem
can be configured, taking up a minimum
of board area. For stand-alone applications, the VL7C212A modem, the
VL7C213 controller, a DAA and an
RS232-interface are all that are required.
The VL7C212A is truly a modem on a
chip. All of the signal processing
functions needed for a full duplex, 300/
1200 bps Bell 212A or CCITT V.21 or
V.22 modem are integrated on a single
chip. It operates in a synchronous or
asynchronous mode and handles 8, 9,
10, or 11 bit words.
Like all modems, the VL7C212A needs a
controller to determine the mode of
operation, initiate the call to the remote
modem (either pulse or tone dialing), set
up the handshaking sequence with the
remote modem, monitor the call progress
tones on the line (ringing, busy, answer
tone, and voice) and switch into the data
mode. A simple four-line serial data
interface was designed for the
VL7C212A, enabling it to work with just
about any 8-bit microcontroller or
microprocessor. The control lines are:
DATA INPUT/OUTPUT, SHIFT CLOCK,
READ and WRITE.

VL7C212A

connected to the filter. In the low speed
mode (300 bps), the FSK modulator is
connected to the filter.
TRANSMITTER
Since data terminals and computers
may not have the timing accuracy
required for 1200 bps transmission
(0.01 %), timing correction on the
incoming data stream must be made.
The async/sync converter accepts
asynchronous serial data clocked at a
rate between 1200 Hz + 1%, -2.5%. It
outputs serial data at a fixed rate of
1200 Hz +/- 0.01% derived from the
master clock oscillator. To compensate
for the input and output rate differences,
a stop bit is either deleted or inserted
when necessary. If the input data rate is
slower than the output data rate, a stop
bit is inserted. Hthe input data rate is
faster than the output data rate, a stop
bit is deleted. The output of the async/
sync converter is applied to the scrambler.

MODEM
Major sections of the VL7C212A modem
are a transmitter, a receiver, low-band
and high-band filters, a two-to-four wire
hybrid, tone generators and interface
logic. It also contains an energy detector
that's used for detecting the carrier and
call progress monitoring and an audio
output for monitoring the line.

The scrambler is a 17-bit shift register
clocked at 1200 Hz. Outputs from the
14th and 17th stages are exclusive OR'd
and further exclusive OR'd with the input
data. The resultant data is supplied to
the D input of the shift register. Outputs
from the first two stages of the shift
register form the dibit that is applied to
the PSK modulator. The purpose of the
scrambler is to randomize data so that
the energy of the modulated carrier is
spread over the band of interest. The
high-band being centered at 2400 Hz or
the low-band, centered at 1200 Hz. A
1200 bps modem actually sends two bits
at a time, called a dibit; dibits are sent at
600 baud, the actual rate of transmission; 600 baud is the optimum rate that
can be transmitted over the general
switched telephone network for a full
duplex FDM (frequency division multiplexing) modem because band limit
filters in the central office cut off at about
3000 Hz.

The VL7C212A modem requires plus
and minus five volts and is available in a
24-pin DIP as well as a 28-pin plastic
chip carrier with "J" leads for surface
mount applications. The transmitter
section consists of an async/sync
converter, scrambler, PSK modulator.
and FSK modulator. In the high speed
mode (1200 bps), the PSK modulator is

The dibit applied to the PSK modulator
produces one of four differential phase
shifts of the square wave carrier signal
(1200 Hz or 2400 Hz) at the 600 Hz
baud rate. The resultant waveform is
passed through a wave shaping circuit
that performs a raised cosine function
(this is the shape factor called out in the
CCITT V.21 and V.22 specifications,

323

and it also meets the Bell 212A requirement for optimum transmission). The
wave shaped signal is then passed
through either the low-band or highband filter depending upon originate or
answer mode selection.
For low speed operation the FSK
modulator is used. It produces one of
four precision frequencies depending on
originate or answer mode and the 1
(mark) or 0 (space) level of the transmit
data. The frequencies are produced
from the master clock oscillator using
programmable dividers. The dividers
respond quickly to data changes,
introducing negligible bit jitter while
maintaining phase coherence. The
output of the FSK modulator is applied
to the appropriate filter when the low
speed mode of the operation is selected.
The filter section consists of low-band
(1200 Hz) and high-band (2400 Hz)
filters, half-channel compromise
amplitude and group delay equalizers
for both bands, smoothing filters for both
bands and multiplexers for routing of the
transmit and receive signals through the
appropriate band filters. For CCITT
V.21 or V.22 applications, a notch filter
is included that can be programmed for
either 550 Hz or 1800 Hz. In the call
progress monitor mode, the lOW-band
filter is scaled down by a factor of 2.5 to
center it over a frequency range of 300
to 660 Hz. Thus, during call establishment in the originate mode, call progress tones can be monitored through the
scaled low-band filter and the modem
answer tone or voice can be monitored
through the unscaled high-band filter.
The lOW-band filter is a 10th order
switched-capacitor band-pass filter with
a center frequency of 1200 Hz. In the
originate mode, this filter is used in the
transmit direction; in the answer mode it
is used in the receive direction. When
analog loopback is used in the originate
mode, this filter, together with the lowband delay equalizer, is in the test loop.
In the call progress monitoring mode the
filter response is scaled down by 2.5,
moving the center frequency to 480 Hz.
The low-band delay equalizer is a 10th
order switched-capacitor all-pass filter
that compensates for the group delay
variation of the low-band filter and half of
the compromise line characteristics,

VLSI TECHNOLOGY, INC.

producing a flat delay response within
the pass-band.
The high-band filter is a 10th order
switched-capacitor band-pass filter with
a center frequency of 2400 Hz. In the
answer mode, this filter is used in the
transmit direction; in the originate mode,
it is used in the receive direction. When
analog loopback is used in the answer
mode, this fi~er, together with the highband delay equalizer, will be in the test
loop.
The high-band delay equalizer is a 10th
order switched-capacitor all-pass filter
that compensates for the group delay
variation of the high-band filter and half
of the compromise line characteristics,
producing a flat delay response within
the pass-band. The transmit smoothing
filter is a second order low-pass
switched-capacitor filter that adds the
modem transmit signal to the DTMF
(V.21 or V.22) guard tones. It also
provides a 3 dB per step programmable
gain function to set the output level.
RECEIVER
The receiver section consists of an
energy detector, AGC, PSK demodulator, FSK demodulator, descrambler, and
sync!async converter.

VL7C212A
lated to baseband in a mixer stage
where individual components are
multiplied by the recovered carrier. The
baseband components are low-pass
filtered to produce I and Q (In-phase and
Quadrature) channel outputs. The I and
Q channel outputs are rectified,
summed, and passed through a bandpass filter giving a 600 Hz signal. This
signal is applied to a digital phase lock
loop (DPLL) to produce a baud rate
clock. Using the recovered clock signal,
the I and Q channels are sampled to
produce the received dibit data. The
recovered carrier for the demodulator is
generated by another PLL which is
controlled by the amplitude of the error
signal formed by the difference of the I
and Q outputs.
The descrambler is similar to the
scrambler. The received dibit data is
applied to the D input of a 17 bit shift
register clocked at 1200 Hz. Outputs
from the 14th and 17th stages are
exclusive OR'd and further exclusive
OR'd with input data to produce received
data.

The received signal is routed through
the appropriate band-pass filter and
applied to both the energy detector and
AGC circuit. The energy detector is
based on a peak detection algorithm. It
provides a detection within 17 to 24 ms.
It is set to turn on when the signal
exceeds -43 dBm and turn off when the
signal falls below -48 dBm. A 2 dB
minimum hysteresis is provided between
the turn on and turn off levels.

In the asynchronous mode, data from
the descrambler is applied to the sync!
async converter to reconstruct the.
originally transmitted asynchronous
data. For data which had stop bits
deleted at the transmitter (overspeed
data), these stop bits are reinserted.
Underspeed data is passed essentially
unchanged. Output of the sync!async
converter along with the output of the
FSK demodulator is applied to a
multiplexer. The multiplexer selects the
appropriate output, depending on the
operating speed, and outputs received
data on the RXD pin.

The AGC circuit is a programmable gain
amplifier that covers a range of 28 dB in
seven steps. The gain is controlled by a
3 bit up/down counter. Output of the
AGC amplifier is rectified and compared
with two preset levels corresponding to
desired high and low limits. Outputs of
the comparators control the up/down
counter such that the received signal is
amplified to the desired level.

For low speed operation, the FSK
demodulator is used. The output of the
AGC amplifier is passed through a zero
crossing detector and applied to a
counter that is reset on zero crossings.
The counter is designed to cycle at a
rate four times faster than the carrier
signal. The counter output is low-pass
filtered and hard limited to generate FSK
data.

The PSK demodulator uses a coherent
demodulation technique. Output of the
AGC amplifier is applied to a dual phase
splitter that produces an in-phase and
90 degree out of phase component.
These components are then demodu-

HYBRID·
The signal on the phone line is the sum
of the transmit and receive signals. The
hybrid subtracts the transmitted signal
from the signal on the line to form the
received signal. It is important to match

324

the hybrid impedance as closely as
possible to the telephone line to produce
only the received signal. This matching
provided by an external resistor connected between the RXA 1 and RXA2
pins on the VL7C212A. The filter
section provides sufficient attenuation of
the out of band signals to eliminate
leftover transmit signals from the
received signal. The hybrid also acts as
a first order low-pass antialiasing filter.
TONE GENERATOR
The tone generator section consists of a
DTMF generator and a V.21 (or V.22)
guard tone generator. The DTMF
generator produces all of the tones
corresponding to digits 0 through 9 and •
and # keys. The V.21 (or V.22) guard
tone generator produces either 550 Hz
or 1800 Hz. Selection of either the 550
Hz or 1800 Hz tone will cascade the
corresponding notch filter with the lowband filter. The tones are selected by
applying appropriate codes through the
Data 110 pin. Before a tone can be
generated, tone mode must be selected.
Facility is also provided to generate
single tones corresponding to the
individual rows or column of the DTMF
signal.
AUDIO OUTPUT STAGE
A programmable attenuator that can
drive a load impedance of 50 Kn is
provided to allow monitoring of the
received line signal through an external
speaker. The attenuator is connected to
the output of the hybrid. Four levels of
attenuation: no attenuation, 6 dB
attenuation, 12 dB attenuation and
squelch are provided through the ALC1,
ALCO and audio output level control
codes. Output of the attenuator is
available on the audio output pin where
an external audio amplifier (LM386 type)
can be connected to drive a low
impedance speaker. The output can
directly drive a high impedance
transducer, but the volume level will be
low.
VL7C213 AND VL7C214
CONTROLLERS
The VL7C213 modem controller,
implemented in VLSl's two-micron
CMOS process, was designed specifically to handle all of the modem control
functions, as well as the interface to a
system bus. Besides including an 8-bit
microprocessor, 8K by 8 bytes of ROM,

VLSI TECHNOLOGY, INC.
VL7C212A

and 128 by 8 bytes of RAM, it also
contains the functionality of a VL82C50
UART, greatly simplifying the interface
to a parallel system bus, such as used in
an IBM PC-compatible personal
computer (PC). In fact, a complete,
Hayes compatible modem for the PC
consists of the VL7C213 controller, the
VL7C212A modem and the DAA. All of
the popular communications software
written for the PC will work with the
VL7C212A1VL7C213 set.
Another version of the controller, the
VL7C214, is intended for RS-232
applications. It contains the same
processor, memory, and UART as the
VL7C213 and has the same interface to
the modem chip. The difference is that
the UART is turned around so that serial
data from the RS-232 port is converted
to parallel data handled by the internal
processor. Pins are provided for
connecting the familiar switches and
indicator lamps found on most standalone modems, although the switches
and lamps are not needed for operation.
All of the switch settings can be done
through software.
The VL7C214 provides a standard five
volt logic level interface. RS-232 drivers
are required to interface to the port.
Like the VL7C213, the VL7C214 comes
preprogrammed with the Hayes "AT"
command set, and when used with the
VL7C212A modem, emulates a Hayestype stand-alone modem. The VL7C213
and VL7C212A emulate a Hayes-type
IBM PC plug-in card modem. But the
chip set is by no means limited to
implementing a Hayes-type smart
modem. VLSI is in the custom IC
business and both chips were designed
with this in mind. For example, only
about 6K bytes of the VL7C213's ROM
is used for the handshaking and smart
modem code, leaving 2K bytes for
additional features that a customer may
specify. Since the controller is ROM
programmable, any command set, not
just the Hayes "AT" set, can be implemented.
Both the VL7C213 and VL7C214 require
plus five volts and are available in either
a 28-pin DIP or a 28-pin plastic chip
carrier with "J" leads for surface mount
applications. Besides the four-line
interface for the VL7C212A modem, the

VL7C213 controller has an 8-bit data
port, three address lines, a chip select
input, an interrupt line, and the DOST
and DIST control lines found in the
8250B UART. It also has control lines
for ring indication, the off-hook relay and
a data/voice relay; these three lines
connect to the DAA.
In the VL7C214, the 8-bit port becomes
the switch input lines and the address,
chip select, DIST and DOST lines
become the six lines for the RS-232
interface. These six lines are also used
to drive the LEDs. Internally, all of these
lines are treated as programmable 110
ports under software control. The
primary difference between the
VL7C213 and VL7C214 is the ROM
code. It also contains the same modem
and DAA interface lines as the
VL7C213.
The VL7C213 and VL7C214 are truly
ASIC controllers. They are designed to
control a modem or other peripheral that
operates at a moderately slow data rate
up to 1200 bits per second. The
VL7C213 allows a slow peripheral to
interface to a high speed bus, without
making the main processor slow down.
This· is done through the UART interface
and the on-chip registers which look
somewhat like dual port registers. The
main processor can write to and read
from them at will, while the on-chip
cOhtrolier can do the same. The
controller was designed this way
because most communication software
has to have unrestrained access to the
UART registers. To make the VL7C213
compatible with this software, the
registers were included.
The internal processor monitors the
registers to determine the mode of
operation. Command mode or data
mode: at power-up it is automatically put
in the command mode and it looks for·
instructions. Once carrier is detected, it
goes into the data mode, and stays
there until escape sequence is three "+"
signs (+++) in the default mode, but it
can be changed in software.
The actual processor contains an 8-bit
data path and can execute 19 instructions with five different addressing
modes: direct, indirect, immediate,
register direct, and register indirect.
There is 8K by 8 of ROM on-chip for

325

program storage.
To the system bus, the VL7C213 looks
and acts just like a VL82C50 UART. All
of the communications software written
for this UART will work with the
VL7C213 and VL7C214. The VLSI chip
set is a Hayes-type modem in two chips.
The VL7C212A AND
VL7C213NL7C214 System
The only external components required
by the VL7C212A are the 600 n line
matching resistor, a 7.3728 MHz crystal
(a standard frequency) and a 20 pF
capacitor from each leg of the crystal to
ground. That's alii If it is desired to drive
a speaker to monitor the line, an
.
amplifier like the LM386 can be added,
but the output provided on the
VL7C212A can directly drive a high
impedance (50 kn) earphone-type
transducer.
The VL7C213 modem controller's clock
in line is driven by the VL7C212A's clock
out line, so only one crystal is needed.
The VL7C213 interfaces directly to an
IBM PC bus -- no buffers are required.
The only external parts may be an eight
input NAND gate for COM1 and COM2
decoding inside the PC.
For tone dialing, the controller sends a
code to the modem chip which in turn
puts out the called for DTMF tone on the
line via the on-chip DTMF generator.
For pulse dialing, the controller pulses
the OH (off-hook) relay. Both dialing
modes work with the built-in call
progress algorithm so they won't start
dialing until a dial tone is detected.
All modems require a OAA. A OAA
(data access arrangement) is a piece of
equipment required by the FCC to
connect anything to the general
switched telephone network. It consists
of an isolation transformer, typically 600
n to 600 n; a relay for disconnecting
the modem from the line; a ring detector,
typically an opto-isolator; and high
voltage surge protectors. The OAA has
to be FCC registered and this can be
done ~y any of many consultants and
labs around the country. Another
alternative is to buy a OAA, supplied by
several manufacturers.
212A is a Bell specification that calls for
1200 bit per second, full or half duplex
data transmission with a fallback mode

VLSI TECHNOLOGY, INC.
VL7C212A

of 300 baud (Bell 103). It is not 1200
baud; the spec calls for transmission of
dibits, or 2 bits per baud so the 1200
bps transmission takes place at 600
baud. The same is true for V.22; it's
1200 bps or 600 baud. V.22 does not
call for a 300 baud fallback; the CCITT
standard for 300 baud is V.21. It is not
a required fallback for V.22, however, it
is included in the VL7C212A.

V.22 also calls for guard tones to be
sent along with the data. In most of
Europe the tone is 1800 Hz except in
Sweden where 550 Hz is used. The
VL7C212A modem has the 550 Hz and
1800 Hz tone generators built in as well
as the 550 and 1800 Hz notch filter to
remove the guard tone when in the
receive mode.
All modems require a hybrid. Hybrid is
a term used to describe a circuit,

passive or active, that takes the
separate transmit and receive signals
and combines them to go over the
phone line. In' the VL7C212A, this is
done with op amps, but the separate
signals (TXOUT and RXA2) are also
brought out so an external hybrid can
be used, if desired. The combined
signal comes out on the RXA 1 pin and
a matching resistor (typically 600 n) is
connected between RXA 1 and RXA2.

TABLE 1. DEFINITION OF 1/0 CODES
1. Instructions to the modem IC
Data on the D I/O pin is shifted into the modem when WR is low, on rising edges of the SCK clock. Data is transferred
into a latch when WR goes high. (See Figure 2 for write cycle waveforms.) Up to seven data bits (DO--D6) can be sent
to the device. These bits control the operating modes of the modem as show below:

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

03-00

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1

0
1
2
3

4
5
6
7
8

9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8

Mode/Function

Non-Tone Mode:
Reset (set default values)
Tone On/Off
Force Receive Data to Mark Off/On
TLCO Transmit Level Control Bit 0 (default 0)
TLC1 Transmit Level Control Bit 1 (default 0)
TX
Transmitter On/Off
ALB
Analog Loopback On/Off
CPM Call Progress Monitor Mode On/Off
Connection Indicator (CI) On/Off
ALCO Audio Output Level Control Bit 0 (default 0)
ALC1 Audio Output Level Control Bit 1 (default 0)
WLSO Word Length Select 0 (default 0)
WLS1 Word Length Select 1 (default 1)
SynC/Async
LSIHS: Low Speed/High Speed
AlO:
Answer/Originate
Transmit Mark On/Off
Transmit Space On/Off
Scrambler Disable On/Off
DLB
Digital Loopback On/Off
TXDP Transmit Dotting Pattern On/Off
Locked/Internal
External/Slave
2100 Hz Tone On/Off (Must select low speed mode for operation)
1300 Hz Tone On/Off (Must select low speed mode for operation)
V.21 On/Off (Must select low speed mode for operation)

326

VLSI TECHNOLOGY, INC.

VL7C212A

TABLE 1. DEFINITION OF I/O CODES (Cont.)
06

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

03-00

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
1
2
3
4
5

WlS1

WLSO

0
0
1
1

0
1
0
1

Mode/Function

Tone Mode:
Dial 0
Dial 1
Dial 2
Dial 3
Dial 4
DialS
Dial 6
Dial 7
Dial 8
Dial 9
Dial *
Dial #
Output 550 Hz and Insert 550 Hz Notch in low-Band Filter
Output 1800 Hz and Insert 1800 Hz Notch inlow-Band Filter
Row Disable OnlOff
Column Disable OnlOff

6
7
8
9
A
B
C
D
E
F

Word Length
8 Bits
9 Bits
10 Bits (default)
11 Bits

TLC1

TLCO

Transmitter Output Level (dBm) at the Phone Line

0
0
1
1

0
1
0
1

-12 (default)
-9
-6
0

ALC1

ALCO

Audio Output Level

0
0
1
1

0
1
0
1

Output Off (default)
12 dB Attenuation
6 dB Attenuation
No Attenuation

0
1
0
1

2. Information from the Modem IC
Data is read serially from the modem when RD is low, on rising edges of the SCK clock. (See Figure 1 for read cycle
waveforms.) Up to four data bits (DO--D3) can be read as defined below:
DO

Energy Detect

0 - No Energy

1 - Energy Present

In the CPM mode, the energy detector is connected to the output of the high-band filter, if ALB is off, or the scaled lowband filter, if ALB is on.
D1
D2
D3

Received Data (FSK)
Received Data (PSK)
Unscrambled Mark

1 - Mark
1 - Mark
1 - Detected

0- Space
0- Space
o- Not Detected

Notes:
1. Default values for the operating modes on power-up are those shown to the right of the "r unless otherwise specified.
2. Data is shifted in and out of the modem with lSB first.

327

"VLSI TECHNOLOGY, INC
VL7C212A
TABLE 2. AC CHARACTERISTICS
Symbol

Parameter

Min

tOW

Delay Time to Write

200

tOR

Delay Time to Read

200

Typ

tPW

Complete SCK Cycle

1.0

SCK High Pulse Duration

Crystal Frequency

7.3721

Units

Max

Conditions

0/0

70
7.3728 7.3735

Duty Cycle

MHz

FIGURE 1. WAVEFORMS FOR WRITE AND READ CYCLES
a) Write Cycle

b) R.ad

-1<0

DI/O
SCK

DTMF GENERATOR
Parameter

C F

-...J I--- --..J \.Cyc':";
"1
tPW

Ir-

lOR

IDR

X Xl DO 1D1 1D21 D31 X X XX X
LflfU

CRYSTAL FREQUENCY

=7.372800 MHz ±O%

Nominal Frequency

Allowable Error

Actual Error

Row 1

697Hz

± 1%

+ 0.17%

Row 2

770 Hz

±1%

-0.26%

Row 3

852Hz

±1%

+ 0.16%

Row 4

941 Hz

±1%

-0.47%

Column 1

1209 Hz

±1%

-0.74%

Column2

1336 Hz

±1%

-0.89%

Column 3

1477 Hz

±1%

-0.01%

550 Hz

±20 Hz

-1.4 Hz

1800 Hz

±20 Hz

+ 7Hz

Guard Tones

328

VLSI TECHNOLOGY, INC.
VL7C212A

DTMF GENERATOR

(Cont.)
Conditions

Parameter
Second Harmonic Distortion

VCC .. +5V

Row Output Level

VSS~-5

Column Output Level

Min

Typ

Max

-40

Units
dB

dBm

TLCO = 1

dBm

550 Hz Guard Tone Level

TLC1 .. 1

-3

dB (Note 2)

1800 Hz Guard Tone Level

Measured at TXOUT Pin

-6

dB (Note 2)

Note: Guard tone levels are referenced to the TX signal level. When guard tones are added, the TXOUT level is adjusted to
maintain a constant level on the line. For 1800 Hz, the adjustment is -0.97 dB; for 550 Hz, the adjustment is -1.76 dB, per the
CCITf specification.

MODEM TRANSMIT SIGNALS

CRYSTAL FREQUENCY = 7.372800 MHz ±O%

Bell 103

Mode

8ell212A I CCITT V.22

CCITTV.21

Nominal

Actual

Nominal

Actual

Mark

2225 Hz

2226 Hz

1650 Hz

1649.4 Hz

Space

2025 Hz

2024.4 Hz

1850 Hz

1850.6 Hz

Mark

1270 Hz

1269.4 Hz

980 Hz

978.34 Hz

Space

1070 Hz

1070.4 Hz

1180 Hz

1181.53 Hz

Calling Tone

1300 Hz

Answer Tone

2100 Hz

Answer

Originate

Nominal

Actual

2400 Hz

1200 Hz

1301.7 Hz

1300 Hz

1301.7 Hz

2096.9 Hz

2100 Hz

2096.9 Hz

RECEIVER
Parameter

Conditions

Min

Input Signal Range

At RXA 1 (pin 9 )

-45

Intra - Character Bit Rate

AtRXD(pin13)

1170

Carrier Detect

At RXA 1 (pin 9 )

-48

Carrier Detect Hysterisis

Typ

1200

Max

Units

dBm

1224

bps

-43

dBm

Carrier Detect Delay

For 103, 212A and V.22

Carrier Detect Hold

For 103, 212A and V.22

Carrier Detect Delay

For V.21 mode

Carrier Detect Hold

For V.21 mode

329

VLSI TECHNOLOGY, INC.
VL7C212A

TRANSMITTER
Parameter
Input Character Length

Conditions

Min

Start Bit + Data Bit + Stop Bit

At TXD (pin 14)

1170

M = Character Length

2M+3

Intra - Character Bit Rate
Input Break Sequence Length
Output Level Tolerance

Typ

1200

Max

Units

bits

1212

bps
bits

±1

ABSOLUTE MAXIMUM RATINGS
Ambient Temperature
Under Bias:

-10°Cto+80°C

Storage Temperature
Range:
-65°C to + 140°C
Maximum Supply
Voltage: VCC .. +7.0 V, VSS = -7.0 V

Stresses above those listed under
"Absolute Maximum Ratings" may
cause permanent damage to the
device. These are stress ratings only.
Functional Operation of this device at
these or any other conditions above

those in the operational sections of this
specification is not implied and exposure to absoute maximum rating
conditions for extended periods may
effect device reliability.

Input Voltage Range:
Analog Pins; VSS -0.6 V to VCC+0.6 V
Digital Pins; DGND-o.6 V to VCC+0.6 V
Maximum Power
Dissipation @25°C:

500 mW

DC CHARACTERISTICS TA= O°C to 70° C unless otherwise specified
Symbol

Parameter

VCC

Positive Supply Voltage

VSS

Negative Supply Voltage

ICC

Quiescent Current

ISS

Quiescent Current

VIH

High Level Input Voltage

Min

Typ

Max

Units

4.5

5.0

5.5

-4.5

-5.0

-5.5

15
15
2.0

Conditions

VCC=5V

VSS =-5V

Digital Signal Pins: -RD, -WR, DIIO,
SCK,TXCK1,TXD

VIL

Low Level Input Voltage

0.8

Digital Signal Pins:-RD , -WR, DI/O,
SCK, TXCK1, TXD

VOH

VOL

High Level OUtput Voltage

4.0

@IOH= 40 ~A (D SPins: D 1/0, CKOUT,

2.0

@IOH-500~

@IOL=160 ~ (D SPins: D 1/0, CKOUT,

Low Level OUtput Voltage

0.4

RXD, TXCKO, RXCK)

RXD, TXCKO, RXCK)
YOM

Maximum Output Signal

4.0

Vp-p

TXOUT, RL-1200 0 (TLC1.1, TLCO.O)

YOM

Maximum Output Signal

1.0

Vp-p

Audio OUt, RL.. 50 kO

VIM

Maximum Input Signal

Vp-p

RXA1, RXA2

2.0

330

VLSI TECHNOLOGY, INC.
VL7C213
PARALLEL BUS MODEM CONTROLLER

FEATURES

DESCRIPTION

• Direct interface to VL7C212A singlechip modems

• Reduces board space and component
count requirements

The VL7C213 Parallel Bus Modem
Controller is specifically designed to
control the VL7C212A single-chip, 3001
1200 bit-per-second modem. Built with
an advanced two-micron CMOS
process, the VL7C213 provides a
highly cost effective solution for
interfacing a modem IC to a system
bus. When connected to the
VL7C212A, with the addition of a data
access arrangement (DM), the
VL7C213 implements a Hayes-type
smart modem for board-level, integral-'
modem applications. Because the
VL7C213 fully emulates the functionality of the VL82C50 UART and includes
data bus transceivers, it can be directly
interfaced to a computer's parallel data

PIN DIAGRAMS

BLOCK DIAGRAM

• Complete Hayes AT command set in
firmware
• Built-in UART
• Direct IBM PC bus interface
• Two-micron CMOS process
• 28-pin DIP or PLCC package
• Complete intelligent modem in two ICs
• Compatible with industry-standard
software
• Replacement for Sierra SC11 007

VL7C213

-DOST
-DIST
-CS
AO-A2

vee

-OOST
...{lIST
TEST
KOV
-RI

-CS

A2
A1
AO
INT
07

CH
ClK
-WA
-RO
SCK

00- 07

.•
.•

bus (in particular to the bus of the IBM
PC, XT or AT). All of the popular communications software written for the PC
will work with the VL7C2131
VL7C212A chip set. In addition to
including the functionality of the
VL82C50 UART, the VL7C213 contains
an 8-bit microprocessor, 8K by 8 bits of
ROM and 128 by 8 bits of RAM.
For specific high-volume applications,
the control program can be modified by
VLSI to include additional command
functions.

UART
BAUD RATE

TRANS

INTCONT

lXD
RXO

os
os

D4
03
D2

ova
TXO
AXO
GNO

INT

TEST

...{lOST -CS

-AI

ROM
8KX 8

INT

ClK

-WR

-AD

SCK

0110

ORDER

INFORMATION
PORT 1

Part
Number

Package

VL7C213-PC
VL7C213-QC

Plastic DIP
Plastic Leaded Chip Carrier (PLCC)

SCK
-AD
-WR

0110

Note: Operating temperature range is O°C to +70°C.

KOV

331

OH -AI

VLSI TECHNOLOGY, INC.
VL7C213

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

-OOST

Signal
Description
The CPU can write data or control words into a selected register of the VL7C213 when
-OOST is low and the chip is selected. Data is latched on the rising edge of the signal.

-OIST

The CPU can read data or status information from a selected register of the VL7C213
when -OIST is low and the chip is selected.

TEST

When the test input is high, the VL7C213 enters a test mode (used for factory testing
only). No connection must be made to this pin. It must be left open for normal operation.

KOV

This output controls the operation of the data/voice relay. When low, the data/voice relay
is off and the phone line is connected to the phone set. During a data call, the VL7C213
makes this output high to operate the data/voice relay, disconnecting the phone set from
the phone line. It may also be used to drive a relay for multi-line phone applications to
close the A and A 1 leads.

-RI

The output of the ring detector in the OAA is connected to this input. A low level on this
input indicates the "On" duration of the ring cycle. This is a Schmitt-trigger input,
allowing for slow rising and falling signals on this pin.

This output controls the operation of the hookswitch relay in the OAA. During a data call,
this output is high. It operates the hookswitch relay which causes the phone line to be
seized. During rotary dialing, the VL7C213 pulses this output at a rate of 10 pulses per
second with appropriate Mark/Space ratio depending on 212A or V.22 mode.

CLK

A 7.3728 MHz clock signal must be connected to this input. Normally, the CKOUT pin of
the VL7C212A modem is connected to this pin. All internal timing is derived from this
clock. This clock must be adjusted to within 0.01 %.

-WR

This pin is used to initiate writing of data to the VL7C212A modem. On power-up, it is an
input for a brief time in which the VL7C213 reads the carrier status switch connected to
this pin. Hthe switch is closed to ground through an 18 Kn resistor, the VL7C213 sets
the Received Line Signal Detect (RLSO) Bit in the Modem Status Register. Hthe switch
is open, the VL7C213 resets this bit and writes the actual status of the carrier detector
during a data call. H no switch is used, an internal pull-up sets the status during powerup to the default state (pull-up to VCC) which is to follow the remote modem's carrier.

-RO

This pin is used to initiate reading of data from the VL7C212A modem. On power-up,
this pin is an input for a brief time in which the VL7C213 reads the OTR status switch
connected to this pin. If this switch is open, the VL7C213 reacts to the status of the OTR
bit in the UART Modem Control Register. If the switch is closed to ground through 18
kil, the VL7C213 ignores the state of the OTR bit. When the switch is open, writing a
zero to the OTR bit in the Modem Control Register forces the VL7C213 into the command state and when on-line, causes it to hang up. If no switch is used, an internal pullup to VCC sets the status during power-up to the default state (to follow the OTR status).

SCK

The VL7C213 supplies a shift clock on this pin to the VL7C212A modem for reading or
writing data. On power-up, this pin is an input for a brief time in which the VL7C213
reads the Bell/CCIIT select switch connected to this pin. Hthis switch is open, Bell
protocol is selected. If this switch is closed to ground through18 kil, CCIIT V.22
protocol is selected. If no switch is used, an internal pull-up sets the status during
power-up to the default state (212A mode).

0110

The VL7C213 shifts data serially out of this pin to VL7C212A during a write operation
and shifts data serially into this pin during a read operation from the VL7C212A. On
power-up this pin is an input for a brief time in which the VL7C213 reads the MakelBreak
ratio select switch connected to this pin for selecting the pulse dialing standard. With the
switch open, the Bell standard 39% Make, 61% Break is selected. With the switch
closed to ground through 18 kil, the CCIIT standard 33% Make, 67% Break is selected.
H no switch is used, an internal pull-up sets the status during power-up to the default
state (Bell standard).

332

VLSI TECHNOLOGY, INC.
VL7C213

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Description

TXD

This pin is a serial output pin. During a data call, after the connection is established, the
VL7C213 converts parallel data received from the computer bus and outputs it in a
serial, asynchronous format to the VL7C212A modem for modulation. At all other times
the VL7C213 holds this output in the Mark (high) condition.

RXD

Demodulated data from the VL7C212A modem is received on this pin during a data call.
A high level is considered Mark and a low level is Space. The VL7C213 converts the
serial data into a parallel data byte and stores it in the Receiver Buffer Register (RBR).
The Data Ready bit in the Line Status Register (LSR) is then set, and an appropriate
interrupt identification code is written in the Interrupt Identification Register (IIR) to signal
to the computer, the reception of a new data byte.

GND

Ground reference (0 V).

00-07

15-22

This is the 8 bit data bus comprising of three-state input/output lines. This bus provides
bidirectional communication between the VL7C213 and the CPU. Data control words
and status information are transferred via the DO - 07 data bus.

INT

This output goes high whenever anyone of the following interrupt types has an active
condition and is enabled via the IER: Receiver Line Status flag, Received Data Available, Transmitter Holding Register Empty, and Modem Status. It is reset low upon the
appropriate interrupt servicing. The INT pin is forced to a high impedence state when
the OUT2 bit of the Modem Control Regiser (MCR) is low (power on state).

AO-A2

24-26

These three address inputs are used during read or write operation to select a UART
register in the VL7C213 as shown in Table 1. The Divisor Latch Access Bit (DLAB) must
be set high by the system software to access the bit rate divisor latches as shown in
Table 2.

-CS

The VL7C213 is selected when this input is low. When high, the VL7C213 forces the
Data bus lines into a high impedance state.

VCC

Positive supply (+5 V).

TABLE 1. VL7C213 UART REGISTERS
DLAB

Mnemonic

RBR

Receiver Buffer Register (read only)

THR

Transmitter Holding Register (write only)

IER

Interrupt Enable Register

IIR

Interrupt Identification Register (read only)

LCR

Line Control Register

MCR

Modem Control Register

LSR

Line Status Register

MSR

Modem Status (read only) Register

STR

Speed

DLL

Divisor Latch (LSB) (write only)

DLM

Divisor Latch (MSB) (write only)

X - "Don't Care"

0- Logic Low

1 - logic High

333

VLSI TECHNOLOGY, INC.
VL7C213

FIGURE 1. UART BLOCK DIAGRAM
INTERNAL
DATA BUS

00-07 ......
.....

...

DATA BUS
BUFFER

- ...
~

RECEIVER
BUFFER
REGISTER

.... ....
.....

- ...-

......

LINE
CONTROL
REGISTER

RECEIVER
SHIFT'
REGISTER

......

..-

I--

r--

RXD

;

RECEIVER
TIMING AND
CONTROL
~l

.........
AO
A1
A2

-CS
-DIST
-DOST

.....
.....

....
..
..
..
....
....
....

......

DIVISOR
LATCH (LS)
....-L

--...

DIVISOR
LATCH (MS)

BAUD
GENERATOR)

LINE
STATUS
REGISTER

.....

SELECT
AND
CONTROL
LOGIC

....

...
...--

TRANSMITTER
TIMING AND
CONTROL

- ....
~

......
....
.....

....

.........

.... ..
~

.....

SPEED
REGISTER

TRANSMITTER
HOLDING
REGISTER

MODEM
CONTROL
REGISTER

MODEM
STATUS
REGISTER

....

INTERRUPT
ENABLE
REGISTER

INTERRUPT

10
REGISTER

334

"
TRANSMITTER
SHIFT
~ TXD
REGISTER

MODEM
CONTROL
LOGIC

......

INTERRUPT
CONTROL
LOGIC

......

INT

VLSI TECHNOLOGY, INC.
VL7C213

TABLE 2. VL7C213 UART REGISTER FUNCTION SUMMARY
Register Bit Number

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Blt7

RBR

Data

THR

Data

IER

Receive
Data
Available
Interrupt
Enable

THRE
Interrupt
Enable

Receive
Line
Status
Interrupt
Enable

Modem
Status
Interrupt
Enable

IIR

011
Interrupt
Pending

Interrupt
10 Bit 0

Interrupt
10 Bit 1

LCR

0 .. 7 Bit
Data
1 - 8 Bit
Data

0=1 Stop
Bit
1 .. 2 Stop
Bits

1 .. Parity
Enable

1 .. Even
Parity

1 .. Stick
Parity

1 = Set
Break

DLAB

MCR

Data
Terminal
Ready

Request
to Send

OUT1

OUT2

No
Function

LSR

Data
Ready

Overrun
Error

Parity
Error

Framing
Error

Break
Interrupt

THRE

TSRE

MSR

Trailing
Edge Ring

Delta
RLSD

1 (CTS)

1 (DSR)

RING

RLSD

DLM

Data

DLL

Data

STR

Data

O.. INT
Output
to HI-Z

335

VLSI TECHNOLOGY, INC.
VL7C213

TABLE3 VL7C213 SOFTWARE REGISTERS
RegIster

Range/UnIts

DescrIption

Default

0-255 Rings

Ring to answer telephone on

0-255 Rings

Number of rings

0-127 ASCII

Escape code character

0-127 ASCII

Character recognized- as carriage return

13 (CR)

0
0
43 (+)

0-127 ASCII

Character recognized as line feedback

10 (LF)

0-32, 127 ASCII

Character recognized as back space

8 (8S)

2-255 sec.

Wait time for dial tone

1-255 sec.

Wait time for carrier

0-255 sec.

Pause time (caused by comma)

1-255 1/10 sec.

Carrier detect response time

S10

1-255 1/10 sec.

Delay between loss of carrier and hang up

S11

50-255 millisec.

Duration and spacing of Touch-Tones

S12

20-255 1/50 sec.

Escape code guard time

2
30

S13

bit mapped

UART status register

S14

bit mapped

Option register

S15

bit mapped

Flag register

S16

0,1,2,4

Test modes

336

VLSI TECHNOLOGY, INC.
VL7C213

TABLE4.COMMANDSUMMARY
PREFIX, REPEAT AND ESCAPE COMMANDS
Command

Description (Notes 1 & 2)

Attention prefix: precedes all command lines except + + + (escape) and AI(repeat) commands

Repeat last command line (AI is not followed by carriage return)

+++

Escape code: go from on-line state to command state (one second pause before and after escape
code entry; ; + + + is not followed by carriage return)

DIALING COMMANDS
Command

Description (Notes 1 & 2)

Command

Description (Notes 1 & 2)

Dial

Wait for 1/8 second

Pulse·

Wait for silence

Touch-Tone

Wait for second dial tone

Pause

;

Return to command state after dialing

Flash

Reverse mode (to call originate-only modem)

OTHER COMMANDS
Commands

Description (Notes 1 & 2)

Commands

Description (Notes 1 & 2)

Answer call without waiting for ring

Speaker on until carrier detected·

BlBO

CCITT V.22 mode (Note 3)

Speaker always on

Bell 103 and 212A mode·

Go to on-line state

CICO

Transmit carrier off

Remote digitalloopback off·

Carrier on·

Remote digitalloopback request

ElEO

Characters not echoed

OIQO

Result codes displayed·

Characters echoed·

Result codes not displayed

FIFO

Half duplex

Sr?

Requests current value of register r

Full duplex·

Sr - n

Sets register r to value of n

HlHO

On hook (hang up)

VNO

Digit result codes

Off hook; line and auxiliary relay

Word result codes·

Off hook; line relay only

XlXO

Compatible with Hayes-type 300 modems·

1110

Request product ID code (130)

Result code CONNECT 1200 enabled

Firmware revision number

Enables dial tone detection

Test internal memory

Enables busy signal detection

UL1

Low speaker volume

Enables dial tone and busy signal detection

Medium speaker volume

YNO

long space disconnect disabled·

High speaker volume

Long space disconnect enabled

MlMO

Speaker always off

Software reset: restores all default settings

Notes:
1. Default modes are indicated by •
2. Commands entered with null parameters assume 0 - X is the same as XO.
3. When the ATB command is used in the answer mode, the VL7C212A is placed in either the V.21 or the V.22 mode, depending on the response from the remote modem. In the originate mode, the VL7C213 will sense if the baud rate is set at 300 or
1200 bits per second and will adjust the VL7C212A accordingly.
337

VLSI TECHNOLOGY, INC.
VL7C213

TABLE 5. RESULT CODES
Digit Code

Word Code

Command executed

Connect

Connected at 300 or 1200 bps
Connected at 300 bps, if result of X1, X2, X3, or X4 command

Ring

Ringing signal detected (Note)

No Carrier

Carrier signal not detected or lost

Error

Illegal command
Error in command line
Command line exceeds buffer (40 characters, including punctuation)
Invalid character format at 1200 bps

Connect 1200

Connected at 1200 bps. Results from X1, X2, X3, or X4 commands only

No Dialtone

Dialtone not detected and subsequent commands not processed
Results from X2 or X4 commands only

Busy

Busy signal detected and subsequent commands not processed
Results from X3 or X4 commands only

No Answer

Silence not detected and subsequent commands not processed
Results from @ command only

Description

Note: When the VL7C213 detects a ringing on the telephone line, it sends a RING result code. However, the VL7C213
will answer the call only if it is in auto-answer mode or is given an A command.

TABLE 6. RESET CONTROL OF REGISTERS AND PINOUT SIGNALS
Register/Signal

Reset Control

Reset State

Receiver Buffer Register

First word received

Transmitter Holding Register

Writing into the Transmitter Holding Register

Data

Interrupt Enable Register

Power on reset

All bits low

Data

Interrupt Identification Register

Power on reset

Bit 0 high; bits 1-7 low

Line Control Register

Writing into the LCR

Data

MODEM Control Register

Power on reset

All bits low

Line Status Register

Power on reset

Bits 0-4, 7 low; bits 5-6 high
Bits 0-3, 6-7 low; bits 4-5 high

Modem Status Register

Power on reset

Divisor Latch (high order bits)

Power on reset

1200 bps

TXD

Master reset

High

INT

Power on reset

Low (high impedence)

338

VLSI TECHNOLOGY, INC.
VL7C213

UART REGISTERS
Line Control Registers
This register controls the format of the
asynchronous data communications.
Bit 0 and 1: Bit 1 is always high. Bit 0
specifies the number of bits in each
transmitted or received serial character.
The encoding of bit 0 is as follows:
Bit 1
1
1

Bit 0
0
1

Word Length
7 Bits
a Bits

Bit 2: This bit specifies the number of
Stop bits in each transmitted or received serial character. If bit 2 is a logic
0, one Stop bit is generated or checked
in the transmit or receive data, respectively. If bit 2 is a logic 1, when 7-bit
word length with no Parity is selected,
two Stop bits are generated or checked.
Bit 3: This bit is the Parity Enable bit.
When bit 0 is a logic 0 and bit 3 is a
logic 1, a Parity bit is generated
(transmit data) or checked (receive
data) between the last data word bit and
the Stop bit of the serial data. (The
Parity bit is used to produce an even or
odd number of 1s when the data word
bits and the Parity bit are summed.)
Bit 4: This bit is the Even Parity Select
bit. When bit 3 is a logic 1 and bit 4 is
logic 0, and odd number of logic 1s is
transmitted or checked in the data word
bits and Parity bit. When bit 3 is logic 1
and bit 4 is a logic 1, an even number of
bits is transmitted or checked.
Bit 5: This bit is the Stick Parity bit.
When bit 3 is logic 1 and bit 5 is logic 1,
the Parity bit is transmitted and then
detected by the receiver in the opposite
state indicated by bit 4.
Bit 6: This bit is the Set Break Control
bit. When bit 6 is a logic 1, the serial
output (TXD) is forced to the Spacing
state (logic 0) and remains there (until
reset by a low-level bit 6) regardless of
other transmitter activity. The feature
enables the CPU to alert a terminal in a
computer communications system.
Bit 7: This bit is the Divisor Latch
Access Bit (DLAB). It must be set high
(logic 1) to access the Divisor Latches
of the Baud Rate Generator during a
Read or Write operation. It must be set
low (logic 0) to access the Receiver
Buffer, the Transmitter Holding Register, or the Interrupt Enable Register.

Programmable Baud Rate Generator
The VL7C213's Baud Rate Generator
can be programmed for one of six baud
rates. The desired speed is selected by
writing into the Divisor Latch (DLM) .
On reset, the rate will be 1200 baud.
DLM (Hex Code)
00
01
03

04
06

Baud Rate
1200
300
150
110
75
50

Line Status Reg Ister
This a-bit register provides status
information to the CPU concerning the
data transfer. The contents of the Line
Status Register are indicated in Table 2
and are described below:
Bit 0: This bit is the receiver Data
Ready (DR) indicator. Bit 0 is set to a
logic 1 whenever a complete incoming
character has been received and
transferred into the Receiver Buffer
Register. Bit 0 will reset to a logic 0
either by the CPU reading the data in
the Receiver Buffer Register or by
writing a logic 0 into it from the CPU.
Bit 1: This bit is the Overrun Error (OE)
indicator. Bit 1 indicates that data in the
Receiver Buffer Register was not read
by the CPU before the next character
was transferred into the Receiver Buffer
Register, thereby destroying the
previous character. The OE indicator is
reset whenever the CPU reads the
contents of the Line Status Register.
Bit 2: This bit is the Parity Error (PE)
indicator. Bit 2 indicates that the
received data character does not have
the correct even or odd parity, as
selected by the even parity select bit.
The PE bit is set to a logic 1 upon
detection of parity error and is reset to a
logic 0 whenever the CPU reads the
contents of the Line Status Register.
Bit 3: This bit is the Framing Error (FE)
indicator. Bit 3 indicates that the
received character did not have a valid
Stop bit. Bit 3 is set to a logic 1
whenever the Stop bit following the last
data bit or parity bit is detected as a
zero (Spacing level).
Bit 4: This bit is the Break Interrupt (BI)
indicator. Bit 4 is set to a logic 1

339

whenever the received data input is
held in the Spacing (Logic 0) state for
longer than a full word transmission
time - the total time of Start bit + data
bits + Parity + Stop bits.
Bit 5: This bit is the Transmitter Holding
Register Empty (THRE) indicator. Bit 5
indicates that the VL7C213 is ready to
accept a new character for transmission. In addition, this bit causes the
VL7C213 to issue an interrupt to the
CPU when the Transmit Holding
Register Empty enable is set high. The
THRE bit is set to a logic 0 concurrently
with the loading of the Transmitter
Holding Register by the CPU.
Bit 6: This bit is the Transmitter Shift
Register Empty (TSRE) indicator. Bit 6
is set to a logic 1 whenever the Transmitter Shift Register is idle. It is reset to
logic 0 upon a data transfer from the
Transmitter Holding Register to the
Transmitter Shift Register.
Bit 7: This bit is permanently set to
10gicO.
Bit,; 1 through 4 are the error conditions
that produce a Receiver Line Status
interrupt whenever any of the corresponding conditions are detected.
Interrupt Identification Reg Istar
The VL7C213 has an on-chip interrupt
capability that allows for complete
flexibility in interfacing to all popular
microprocessors. To provide minimum
software overhead during data character transfers, the VL7C213 prioritizes
interrupts into four levels. The four
levels of interrupt conditions are as
follows: Receiver Line Status (priority
1); Received Data Ready (priority 2);
Transmitter Holding Register Empty
(priority 3); and MODEM Status (priority

4).
Information indicating that a prioritized
interrupt is pending the source of that
interrupt are stored in the Interrupt
Identification Register (refer to Table 7).
The Interrupt Identification Register
(IIR), when addressed during chipselect time, freezes the highest priority
interrupt pending and no other interrupts are acknowledged until the
particular interrupt is serviced by the
CPU. The contents of the IIR are
indicated in Table 2 and are described
below.

VLSI TECHNOLOGY, INC.

Bit 0: This bit can be used in either a
hardwired prioritized or polled environment to indicate whether an interrupt is
pending. When bit 0 is logic 0, an
interrupt is pending and the IIR contents
may be used as a pointer to the
appropriate interrupt service routine.
When bit 0 is a logic, no interrupt is
pending.
Bits 1 and 2: These two bits of the IIR
are used to identify the highest priority
interrupt pending as indicated in Table

7.
Bits 3 through 7: These five bits of the
IIR are always logic o.
Interrupt Enable RegIster
This 8-bit register enables the four
interrupt sources of the VL7C213 to
separately activate the Interrupt (INT)
output signal. It is possible to totally
disable the interrupt system by resetting
bits 0 through 3 of the Interrupt Enable
Register. Similarly, by setting the
appropriate bits of this register and the
active (high) INT output from the chip.
All other system functions operate in
their normal manner, including the
setting of the Line Status and MODEM
Status Register. The contents of the
Interrupt Enable Register are indicated
in Table 2 and are described below.

VL7C213
Bit 2: This bit enables the Receiver
Line Status Interrupt when set to logic

1.
Bit 3: This bit enables the MODEM
Status Interrupt when set to logic 1.
Bit 4 through 7: These four bits are
always logic o.
MODEM Control RegIster
This 8-bit register controls the interface
with the MODEM. The contents of the
MODEM Control Register are indicated
in Table 2 and are described below.
Bit 0: This bit controls Data Terminal
Ready (DTR) signal. If the external
switch on the -RD pin is set to VCC
through an 18 kn resistor, setting the
DTR low will force the VL7C213 into the
command state and if on line, it will
hang up.
Bit 1: This bit controls the Request to
Send (RTS) signal. This signal is not
used by the VL7C213.
Bit 2: This bit controls the Output 1
(OUT1) signal. This signal is not used
by the VL7C213.
Bit 3: This bit controls the Output 2
(OUT2) signal. When OUT2 is a 0, the
interrupt output is in high impedence
state.

Bit 0: This bit enables the Received
Data Available Interrupt when set to
logic 1.

Bit 4: Not used.

Bit 1: This bit enables the transmitter
Holding Register Empty Interrupt when
set to a logic 1.

MODEM Status RegIster
This 8-bit register provides the current
state of the control lines from the

Bits 5 through 7: These bits are
permanently set to logic o.

340

Bit 2: This bit is the Trailing Edge of
Ring Indicator (TERI) detector. Bit 2
indicates that the -RI input to the chip
has changed from On (logic 1) to an Off
(logic 0) condition.
Bit 3: This bit is the Delta Received
Line Signal Detector (DRLSD) indicator.
Bit 3 indicates that the carrier detector
has changed state.
Bit 4: This bit is always 1.
Bit 5: This bit is always 1.
Bit 6: This bit is the complement of the
Ring Indicator (-RI) input.
Bit 7: This bit is the Received Line
Signal Detect (RLSD) signal.
Whenever bit 2 is set to logic 1, or bit 3
changes state, a MODEM Status
Interrupt is generated if enabled.

VLSI TECHNOLOGY, INC.
VL7C213

TABLE 7.

INTERRUPT CONTROL FUNCTIONS

Interrupt
Identification
Register

Interrupt Set and Reset Functions

Bit 2

Bit 1

Bit 0

Priority
Level

Interrupt Flag

Interrupt Source

Interrupt
Reset Control

None

Highest

Receiver
Line Status

Overrun Error or
Parity Error or
Framing Error or
Break Interrupt

Reading the Line
Status Register

Second

Received Data
Available

Reading the Receiver
Buffer Register

Third

Transmitter Holding
Register Empty

Reading the IIR (if source of
interrupt) or Writing into the
Transmitter Holding Register

Fourth

MODEM Status

Ring Indicator or
Received Line
Signal Detect

Reading the MODEM
Status Register

341

VLSI TECHNOLOGY, INC.
VL7C213

AC CHARACTERISTICS:
Symbol

=0 TO 70°C, VCC =5 V ±100/0

Parameter

Min

Max

Units

Conditions

tDIW

-DIST Strobe Width

300

1TTL Load

tRC

Read Cycle Delay

300

1TTL Load

620

Read Cycle = tDIW + tRC + 20 ns

tODD

Delay from -DIST to Data

tHZ

-DIST to Floating Data Delay

tOOW

-DOST Strobe Width

tWC

Write Cycle Delay

Write Cycle == toOW + tWC + 20 ns

tOS

Data Setup Time

1TTL Load

. ns

1TTL Load

300

1TTL Load

300

1TTL Load

620

1TTL Load

300

tDH

Data Hold Time

1TTL Load

tOlC

-DIST Delay from Select

150

1TTL Load

tDOC

-DOST Delay from Select

150

1TTL Load

tACR

Address and Chip Select Hold Time from -DIST

1TTL Load

tACW

Address and Chip Select Hold Time from -DOST

1TTL Load

Receiver
tRINT

100 pF Load

Delay from -DIST (Read RBR) to Reset Interrupt

Transmitter
tHR

Delay from -DOST (Write THR) to Reset Interrupt

tlRS

Delay from InitiallNTR Reset to Transmit Start

Baud Cycle

tSI

Delay from Initial Write to Interrupt

Baud Cycle

tSS

Delay from Stop to Next Start

tSTI

Delay from Stop to Interrupt (THRE)

tlR

Delay from -DIST (Read IIR) to Reset Interrupt (THRE)

Note: A TTL load is 40 ~A sourced and -1.6 rnA sinked current.

'343

100 pF Load

Baud Cycle
~

100 pF Load

VLSI TECHNOLOGY, INC
VL7C213

FIGURE 3. READ CYCLE TIMING

~ ~CRt

-CS--_

X
I.

AD, A1, A2

VALID
tDlC

...IIo.l
-..

~tDIW

~f-

-DIST

ACTIVE

.... .....

--1

tRC

ACTIVE

~--------+-----t----(12---~i

Rc------------~l~'

-DOST

ACTIVE

ltHZ~

tDDD.J

DATA __________________________~( ~~~ )
DO-D7

FIGURE 4. WRITE CYCLE TIMING

-CS--_
AD, A1, A2

-DOST

tAcwt=1
I--------.:=~---_i----l.~==

-----------~~\V--

VALID

IDOC

----~~~.....~------+_----------WC----~
• • _
tWC _ _ _.....,..,
~ tDOW --1-..~~----

~ I,

ACTIVE

.J- I'-

ACTIVE
OR

-DIST

--------------~------t_----(12

~IDsLtDH~>-

DATA _ _ _ _ _ _ _ _ _ _ _ _ _......;;(
DO-D7

VALID DATA

344'

~ ACTIVE

VLSI TECHNOLOGY, INC.
VL7C213

FIGURE 5. RECEIVER TIMING

RXD (RECEIVER \
INPUT DATA)

START

2
DATA
~START .
_ _ _ _ _ _~

'---------,2

---.-----r---"112
SAMPLE ClK

INTERRUPT
-DIST
(READ REC DATA
BUFFER)

-_=================~~~~~_-_-_-_-_-_-_-_ __

==-'J\tRINT
_ _ __

FIGURE 6. TRANSMITTER TIMING

SERIAl~~ - - - - - - , \ /r---D-A-TA--~
START

INTERRUPT
(THRE)

PARllY

~ tlRS 1'-~
~I
/
~.

START , . _ _ - - - - _ _ _ _ __

=1 tSS~l'r-

I.-

tSTI

--trt~~ ~tHR

(W:~~ V - t S - I - - - -.......

-DIST _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
(RDIIR)

345

VLSI TECHNOLOGY, INC.
VL7C213

ABSOLUTE MAXIMUM RATINGS
. Ambient Operating
Temperature

O°C to +70°C

Storage Temperature

-65°C to + 150°C

Supply Voltage to
Ground Potential
Applied Input
Voltage

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only, functional
operation of this device at these or any
other conditions above those indicated

+6V
-0.6 V to VCC +0.6 V

Power Dissipation

500 mW

DC CHARACTERISTICS:

=0 to +70 °C, VCC = 5 V±100/0

Symbol

Parameter

Min

Typ

Max

VCC

Positive Supply Voltage

4.5

5.0

5.5

ICC

Operating Current

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VT+

Positive Hysterisis Threshold

VT-

Negative Hysterisis Threshold

VOH

VOL

10.0

Units

2.0

FCLK

Clock Frequency

@VCC=5V
All pins except -RI

All pins except -RI

2.5

-RI pin

1.8

-RI pin

VCC-1.0

Digital signal pins DO to D7
and INT @ 10H = -6 mA

VCC-1.0

All other output or 110 pins
@IOH=-2mA

0.4

Digital signal pins DO to D7
and INT @ 10L = 6 mA

0.4

All other output or 110 pins
@IOL=2mA

0.8

Low Level Output Voltage

Leakage Current (Note)

Conditions

High Level Output Voltage

Note:

in this data sheet is not implied. Exposure to absolute maximum rating
conditions for extended periods may
affect device reliability.

±1.0
7.3721

7.3728

7.3735

MHz

This applies to all pins except TEST, which has an internal pull-down -WR, -RD, SCK, DIIO and switch input pins
which have internal pull-ups.

346

VLSI TECHNOLOGY, INC.
VL7C213

FIGURE 7. INTEGRAL SMART MODEM CONFIGURA1l0N FOR PC BUS APPLICA1l0NS
COMPUTER
PARALLEL
BUS

,.....

00-07

AO
A1
A2

-lOR

...

-..
....

....
..

J.R03
~

IR04

.........

A3-A9
~

....

......

-lOW
-AEN

~
~

~
ADDRESS
DECODER
See
Figure 2

00-07
AO

KDV

-RI

..-

.....-...

VL7C213
CONTROLLER
-DIST
RXD
-DOST
-CS

TXD
OlIO

.........

....
...

....-...

...

-WR

......... ~_...... >_..... :- ... :-

CLK '.....

.. .. .. ..
_

UJJ

-AD

-WR

..:

TXD
RXA2

OlIO

f---4~

TXOUT I - - -

SCK

CLKOUT

AUDIO
OUT

XTAL1

XTAl2

SPEAKE R

7.3728
MHz

HI~~

-.....
OPTIONAL

SWITCHES:r:

347

RXA1

RXD

...
.

-RD
INT

PHONE
LINE

VL7C212A
MODEM

SCK

~
DAA

-'--

:r:

VLSI TECHNOLOGY, INC.

348

VLSI TECHNOLOGY, INC.
VL7C214
STAND-ALONE MODEM INTERFACE CONTROLLER

FEATURES

DESCRIPTION

• Direct interface to VL7C212A single
chip modems

The VL7C214 Stand-Alone Modem
Interface Controller is specifically
designed to control the VL7C212A
single-chip, 300/1200 bit-per-second
modem. Bui~ with an advanced twomicron CMOS process, the VL7C214
provides a highly cost effective
solution for interfacing a modem IC to
a computer's RS232C port. When
connected to the VL7C212A, with the
addition of a data access arrangement
(DAA), the VL7C214 implements a
Hayes-type smart modem for standalone modem applications. All of the
popular communications software
written for the IBM PC will work with
the VL7C214NL7C212A chip set. The

• Complete Hayes AT command set in
firmware
• Built-in UART for RS232C interface
• Two-micron CMOS process
• 28-pin DIP or PLCC package
• Complete intelligent modem in two ICs
• Compatible with industry-standard
software
• Reduces board space and component
count requirements
• Low power consumption

VL7C214 contains an a-bit microprocessor, aK by a bits of ROM and 128 by a
bits of RAM. In order to support the
stand-alone functionality of the device,
an 8-bit switch input port allows immediate user access and manual control of
the system. Either Bell 103 or CCITT
V.22 may be selected in this manner.
For specific high volume applications,
the control program can be modified by
VLSI Technology, Inc. to include
additional commands and functions.

• Replacement for Sierra SC11 008

BLOCK DIAGRAM

PIN DIAGRAMS
VL7C214
N.C.
N.C.
TEST
KDV/-KDV
-RI

OHl-OH
ClK

-WR
-flD

SCK
DIIO
TXD

vcc
UART

-OTA
-CD
-AA

-HS
N.C.
MSSEl
212A1-V.22
-CMDEN

-AADIS
ECHO EN
-RES EN

RXD

WORD

GND

-PS

-AA

-AI

-HS

OHI-()H

N.C.

ClK

MSSEl

-WR

212A1-V.22

-AD

-CMoEN

SCK

-AADIS

0110

~--... SCK

ORDER INFORMATION

-PS
WORD
-RES EN

Part
E~JI~
Number
Package
-CMD EN
-V~L-7-C-2-14---P-C-+-P""'I-as-t-ic"';;D-'P------------ 21~~~f
VL7C214-QC

Plastic Leaded Chip Carrier (PLCC)

Note: Operating temperature range is O°C to +70°C.

349

t - - - - + -AD
t - - - - + -WR
1 4 - - - + 0110

VLSI TECHNOLOGY, INC.
VL7C214

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Description

N.C.

No connection

N.C.

No connection

TEST

When the test input is high, the VL7C214 enters a test mode (used for factory testing
only). For normal operation, this pin can be left open or connected to ground.

KDVI-KDV

This output controls the operation of the data/voice relay. The polarity of this output is
selected by -PS pin. If -PS is connected to ground, this output is active high, i.e., it is
low when modem is on hook, causing the data/voice relay to be off and the phone line is
connected to the phone set. During a data call, this output goes high to operate the
data/voice relay, disconnecting the phone set from the phone line. It may also be used
to drive a relay for multi-line phone applications to close the A and A 1 leads. If -PS pin
is left open or connected to VCC, this output is active low, i.e., it is high when the modem
is on hook and low when modem makes a data call.

-RI

The output of the ring detector in the DAA is connected to this input. A low level on this
input indicates the "On" duration of the ring cycle. This is a Schmitt-trigger input,
allowing for slow rising and falling signals on this pin.

OH/-OH

This output controls the operation of the hookswitch relay in the DAA. The polarity of this
output is selected by -PS pin. If -PS pin is connected to ground, this output is active
high, i.e., it is low when the modem is on hook. During a data call, it goes high to
operate the hookswitch relay and seize the phone line. During rotary dialing, the
VL7C214 pulses this output at a rate of 10 pulses per second with appropriate Mark!
Space ratio depending on 212A or V.22 mode. If -PS pin is left open or connected to
VCC, this output is active low, i.e., it is high when the modem is on hook and low during
data call.

CLK

A 7.3728 MHz clock signal must be connected to this input. Normally, the CKOUT pin of
the VL7C212A modem is connected to this pin. All internal timing is derived from this
clock.

-WR

This pin is used to initiate writing of data to the VL7C212A modem.

-RD

This pin is used to initiate reading of data from the VL7C212A modem.

SCK

The VL7C214 supplies a shift clock on this pin to the VL7C212A modem for reading or
writing data.

OliO

The VL7C214 shifts data serially out of this pin to VL7C212A during a write operation
and shifts data serially into this pin during a read operation from the VL7C212A. .

TXD

The VL7C214 outputs serial data in asynchronous start/stop format at the data rate
selected by the terminal. This data is either echo of commands received from the
terminal or result codes generated by the controller during processing of the commands .
. This output is normally high and should be "AND"ed with the RXD output of the
VL7C212A to form RXD data to the terminal.

RXD

The VL7C214 receives command data from the terminal on this pin. The UART in the
controller connects the serial asynchronous start/stop data into a parallel byte for
processing by the controller.

GND

Ground reference (0 V).

-PS

This input controls the polarity of KDV and OH outputs. When left open or connected to
VCC, it forces the KDV and OH outputs to be active low. If this input is connected to
ground, KDV and OH outputs are active high.

WORD

When the input is open or connected to VCC, the VL7C214 sends result codes as words.
When this input is low, result codes are sent as digits. This setting can also be changed
by entering the V command.

350

VLSI TECHNOLOGY, INC
VL7C214

SIGNAL DESCRIPTIONS

(Cant.)

Signal
Name

Pin
Number

Signal
Description

-RES EN

When this input is low, the VL7C214 sends result codes. When this input is high or left
open, commands received from the terminal are performed but result codes are not sent.
This setting can also be changed by entering the Q command.

ECHO EN

When this input is high or left open, the VL7C214 echoes characters received from the
terminal in the command state. When this input is low, the VL7C214 will not echo characters unless it is set for half duplex and it is on line. This setting can also be changed
by entering the E command.

-AADIS

When this input is low, the VL7C214 will not answer incoming calls. When this input is
high or left open, the VL7C214 automatically answers incoming calls on the first ring.
This function can also be enabled/disabled by writing to the SO register.

-CMD EN

When this input is low, the VL7C214 recognizes command sent to it. For some applications such as unattended answering operation it is better to disable this function by
leaving this input open or connecting it to VCC.

212A1-V.22

When this input is open or connected to VCC, the VL7C214 supports 8ell103 and 212A
modes. When this input is low, the VL7C214 supports the CCITT V.22 and V.21 modes.
This setting can also be changed by entering the 8 command.

MSSEL

When this input is open or connected to VCC, the Mark/Space ratio is U.S. standard, 40/
60 MakelBreak. When it is low, the Mark/Space ratio is European standard, 33/67 Make/
8reak.
.

N.C.

No connection

-HS

This output, when low, indicates that the modem is in the high speed (1200 bps) mode.
When high, it indicates that it is in the low speed (300 bps) mode. This output can be
directly connected to a light emitting diode through a 330 n resistor.

-AA

This output is low when the VL7C214 is set for auto-answer mode, either by switch input
-AA DIS (pin 19) or register SO. The output goes high during each ring. If the device is
not set to answer the phone (pin 19 is low or SO I: 0), this output goes low each time the
phone rings. A light emitting diode through a 330 n resistor can be directly connected to
this output.

-CD

This output goes low when the VL7C214 detects a carrier signal from the remote
modem. If the connection is broken or never established, it remains high. A light
emitting diode can be directly connected to this output through a 330 n resistor.

-DTR

When this input is low, the VL7C214 executes data call commands. If during a data call,
this input goes high, the VL7C214 terminates the data call, hangs up the phone line and
returns to command state.

VCC

Positive supply (+5 V).

351

VLSI TECHNOLOGY, INC.
VL7C214

. TABLE 1. VL7C214 SOFTWARE REGISTERS
Register

Range/Units

Description

Default

0-255 Rings

Ring to answer telephone on

0-255 Rings

Number of rings

0-127 ASCII

Escape code character

0-127 ASCII

Character recognized as carriage return

13 (CR)

0-127 ASCII

Character recognized as line feedback

10 (LF)

0-32, 127 ASCII

Character recognized as back space

8 (8S)

2-255 sec.

Wait time for dial tone

43 (+)

1-255 sec.

Wait time for carrier

0-255 sec.

Pause time (caused by comma)

30
2

1-255 1/10 sec.

Carrier detect response time

S10

1-255 1/10 sec.

Delay between loss of carrier and hang up

S11

50-255 millisec.

Duration and spacing of Touch-Tones

S12

20-255 1/50 sec.

Escape code guard time

S13

bit mapped

UART status register

S14

bit mapped

Option register

S15

bit mapped

Flag register

S16

0,1,2,4

Test modes

352

VLSI TECHNOLOGY, INC
VL7C214

TABLE2.COMMANDSUMMARY
PREFIX, REPEAT AND ESCAPE COMMANDS
Command

Description (Notes 1 & 2)

Attention prefix: precedes all command lines except + + + (escape) and AI(repeat) commands

Repeat last command line (AI is not followed by carriage return)

+++

Escape code: go from on-line state to command state (one second pause before and after escape
code entry; ; + + + is not followed by carriage return)

DIALING COMMANDS
Command

Description (Notes 1 & 2)

Command

Description (Notes 1 & 2)

Dial

Wait for 1/8 second

Pulse*

Wait for silence

Touch-Tone

Wait for second dial tone

Pause

;

Return to command state after dialing

Flash

Reverse mode (to call originate-only modem)

OTHER COMMANDS
Commands

Description (Notes 1 & 2)

Commands

Description (Notes 1 & 2)

Answer call without waiting for ring

Speaker on until carrier detected*

Bl80

CCITT V.22 mode (Note 3)

Speaker always on

8ell103 and 212A mode*

Go to on-line state

CICO

Transmit carrier off

Remote digitalloopback off*

Carrieron*

Remote digitalloopback request

ElEO

Characters not echoed

Q/OO

Result codes displayed*

Characters echoed*

Result codes not displayed

FIFO

Half duplex

Sr?

Requests current value of register r

Full duplex*

Sr .. n

Sets register r to value of n

HIHO

On hook (hang up)

VNO

Digit result codes

Off hook; line and auxiliary relay

Word result codes*

Off hook; line relay only

XlXO

Compatible with Hayes-type 300 modems*

1110

Request product ID code (130)

Result code CONNECT 1200 enabled

Firmware revision number

Enables dial tone detection

Test internal memory

Enables busy signal detection

UL1

Low speaker volume

Enables dial tone and busy Signal detection

Medium speaker volume

YNO

Long space disconnect disabled*

High speaker volume

Long space disconnect enabled

MlMO

Speaker always off

Software reset: restores all default settings

Notes:
1. Default modes are indicated by *.
2. Commands entered with null parameters assume 0 - X is the same as XO.
3. When the ATB command is used in the answer mode, the VL7C212A is placed in either the V.21 or the V.22 mode, depending on the response from the remote modem. In the originate mode, the VL7C214 will sense if the baud rate is set at 300 or
1200 bits per second and will adjust the VL7C212A accordingly.

353

VLSI TECHNOLOGY, INC.
VL7C214

TABLE 3. RESULT CODES
Digit Code

Word Code

Command executed

Connect

Connected at 300 or 1200 bps
Connected at 300 bps, if result of X1, X2, X3, or X4 command

Ring

Ringing signal detected (Note)

No Carrier

Carrier signal not detected or lost

Error

Illegal command
Error in command line
Command line exceeds buffer (40 characters, including punctuation)
Invalid character format at 1200 bps

Connect 1200

Connected at 1200 bps. Results from X1, X2, X3, or X4 commands only

No Dialtone

Dialtone not detected and subsequent commands not processed
Results from X2 or X4 commands only

Busy

Busy signal detected and subsequent commands not processed
Results from X3 or X4 commands only

No Answer

Silence not detected and subsequent commands not processed
Results from @ command only

Description

Note: When the VL7C214 detects a ringing on the telephone line, it sends a RING result code. However, the VL7C214
will answer the call only if it is in auto-answer mode or is given an A command.

354

VLSI TECHNOLOGY, INC.
VL7C214

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

O°C to +70°C

Storage Temperature

-65°C to + 150°C

Supply Voltage to
Ground Potential
Applied Input
Voltage

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only, functional
operation of this device at these or any
other conditions above those indicated

in this data sheet is not implied. Exposure to absolute maximum rating
conditions for extended periods may
affect device reliability.

+6V
-0.6 V to

Power Dissipation

vee + 6 V
500mW

DC CHARACTERISTICS: TA =0 to +70 °C, VCC =5 V ±10%
Symbol

Parameter

VCC

Positive Supply Voltage

ICC

Operating Current

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

Min
4.5

Typ

Max

5.0

5.5

10.0

Units
V
mA

2.0
0.8

Conditions

@ VCC - 5 V, outputs unloaded

All pins except -RI

VT+

Positive Hysterisis Threshold

2.5

-AI pin

VT-

Negative Hysterisis Threshold

1.8

-AI pin

VOH

High Level Output Voltage

@IOH--2mA

VOL

Low Level Output Voltage

0.4

@IOL-2mA

Leakage Current (Note)

FCLK

Clock Frequency

7.3735

MHz

VCC-1.0

±1.0
7.3721

7.3728

Note: This applies to all pins except TEST, which has an internal pull-down -WR, -RD, SCK, DVO, and switch input pins
15 thru 21 which have internal pull-ups.

355

VLSI TECHNOLOGY, INC.
VL7C214

FIGURE 1. 212A1V.22 STAND-ALONE INTELLIGENT MODEM USING THE VL7C212A MODEM IC
AND THE VL7C214

+5V

B
390n
CD

C
390n

D
E

390n

fit

390n

-:-

+5V

SD ...- - I....-

........ )

L - -_

_ . . . - -.... )

16
(WORD RES.)

Vl7C214
CONTROllER

(RES. EN)

- - - , SWI.1
_ _ _1_7, SWI.2

(ECHO ON)

_ _.....;1_8~ SWI.3

FIT .-5-t---+-t--+-..
OH

t --+-t--i-+-t--

HS
19

(AADIS)

(CMNDEN)

(212A)

(PWRUPRES)

3
14

SWI.4

i5'fR

SWI.5

12
TXD t ;;;""_--I
11_ _ _ _-t-_
DI/O t -

J--27_---'

SWI.6

10
SCK t _ _ _ _-t-_

SWI.7

9 _ _ _ _-t-_
RD t WR J--8_ _ _ _-+-_

TEST
GND

ClK ~7_ _ _ _-+-_

L
M

p
Q

KDV
23
4

-:-

T
Note: Schematics are for illustration purposes only. Operational systems may require modifications.

356

VLSI TECHNOLOGY, INC.
VL7C214

FIGURE 1. 212AN.22 STAND-ALONE INTELLIGENT MODEM USING THE VL7C212A MODEM IC
AND THE VL7C214 (Cont.)

A
D-lh:-:~_-_---f

D
E

D-lf--....."..."...".........,=-_---f 3

5
6

7
~~~---~--~ ~

~~~

rr-._

4049 2.F

RXA1

14
13

M
N

P
Q

2
1

50 kn
_ _ _ __

0.5W
SPKR

t - - -. .

LINE

15
16
17
18
23

RXA2
TXD TXOUT
AGND
RXD
DIIO
SCK

VSS
VCC

TEL.
SET

12
24

\VA

DGND
CKOUT

+5V

XTAL1 XTAL2
20
7.3728Mhz

-r20 pF-r20 pF
-=-

-~-==~

VL7C212A
MODEM

-=
4049

4049

357

VLSI TECHNOLOGY, INC.

358

VLSI TECHNOLOGY, INC.
VL7C215
HIGH SPEED PARALLEL BUS MODEM CONTROLLER

FEATURES

DESCRIPTION

• Direct interface to VL7C212A singlechip modems

The VL7C215 Parallel Bus Modem
Controller is specifically designed to
control the VL7C212A single-chip, 300/
1200 bit-per-second modem. Built with
an advanced two-micron CMOS
process, the VL7C215 provides a
highly cost effective solution for
interfacing a modem IC to a system
bus. When connected to the
VL7C212A, with the addition of a data
access arrangement (DAA), the
VL7C215 implements a Hayes-type
smart modem for board-level, integralmodem applications. Because the
VL7C215 fully emulates the functionality of the VL82C50 UART and includes
data bus transceivers, ~ can be directly
interfaced to a computer's parallel data

• Complete Hayes AT command set in
firmware
• Built-in UART
• Direct IBM PC bus interface
• IORDY pin for use on high-speed
buses
• Two-micron CMOS process
• Complete intelligent modem in two ICs
• Compatible with industry-standard
software
• Replacement for Sierra SC11 017
• Reduces board space and component
count requirements

PIN DIAGRAMS

bus (in particular to the bus of the IBM
PC, XT or AT). All of the popular communications software wr~ten for the PC
will work w~h the VL7C215/
VL7C212A chip set. In addition to
including the functionality of the
VL82C50 UART, the VL7C215 contains
an 8-bit microprocessor, 8K by 8 b~s of
ROM and 128 by 8 b~s of RAM.
For specific high-volume applications,
the control program can be modified by
VLSI to include additional command
functions.

BLOCK DIAGRAM

VL7C215
-DOST
-DIST
10ROY
KOV

-DOST
-DIST
-CS
AO-A2
IORDY
DO- D7

VCC
-CS
A2

A1
AD
INT
07
06
05
D4
03
02
01

-AI
OH
CLK

-WR

-AD
SCK
0110
TXO
RXO
GNO

INT

•

UART
BAUD RATE

TRANS

TXD

INTCONT

RXD

+--i-----+-----'

-oosr -cs
l-olsr I v(x I

ICADY
KDV

1<2.

ROM
Al

-AI

INT

eLK
-WR

TOP VIEW

-AD

SCK

DVO

ORDER

8KX 8

INFORMATION
PORT 1

Part
Number

Package

VL7C215-PC
VL7C215-QC

Plastic DIP
Plastic Leaded Chip Carrier (PLCC)

Note: Operating temperature range is O°C to +70°C.

KDV

359

-AI

t----_+_
t----_+_
t----_+_
I+---_+_

SCK
-RD

-WR
DI/o

VLSI TECHNOLOGY, INC.
VL7C215

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

-DOST

Signal
Description
The CPU can write data or control words into a selected register of the VL7C215 when
-DOST is low and the chip is selected. Data is latched on the rising edge of the signal.

-DIST

The CPU can read data or status information from a selected register of the VL7C215
when -DIST is low and the chip is selected.

10RDY

This open-drain output will go low upon a write or read operation, and remain low until
internal data setup and hold times have been satisfied.

KDV

This output controls the operation of the data/voice relay. When low, the data/voice relay
is off and the phone line is connected to the phone set. During a data call, the VL7C215
makes this output high to operate the data/voice relay, disconnecting the phone set from
the phone line. It may also be used to drive a relay for multi-line phone applications to
close the A and A 1 leads.

-RI

This output controls the operation of the hookswitch relay in the DAA. During a data call,
this output is high. It operates the hookswitch relay which causes the phone line to be
seized. During rotary dialing, the VL7C215 pulses this output at a rate of 10 pulses per
second with appropriate Mark/Space ratio depending on 212A or V.22 mode.

CLK

-WR

This pin is used to initiate writing of data to the VL7C212A modem. On power-up, it is an
input for a brief time in which the VL7C215 reads the carrier status switch connected to
this pin. Hthe switch is closed to ground through an 18 Kn resistor, the VL7C215 sets
the Received Line Signal Detect (RLSD) Bit in the Modem Status Register. If the switch
is open, the VL7C215 resets this bit and writes the actual status of the carrier detector
during a data call. H no switch is used, an internal pull-up sets the status during powerup to the default state (pull-up to VCC) which is to follow the remote modem's carrier.

-RD

This pin is used to initiate reading of data from the VL7C212A modem. On power-up,
this pin is an input for a brief time in which the VL7C215 reads the DTR status switch
connected to this pin. If this switch is open, the VL7C215 reacts to the status of the DTR
bit in the UART Modem Control Register. If the switch is closed to ground through 18
kil, the VL7C215 ignores the state of the DTR bit. When the switch is open, writing a
zero to the DTR bit in the Modem Control Register forces the VL7C215 into the command state and when on-line, causes it to hang up. If no switch is used, an internal pullup to VCC sets the status during power-up to the default state (to follow the DTR status).

SCK

The VL7C215 supplies a shift clock on this pin to the VL7C212A modem for reading or
writing data. On power-up, this pin is an input for a brief time in which the VL7C215
reads the Bell/CCITT select switch connected to this pin. Hthis switch is open, Bell
protocol is selected. If this switch is closed to ground through18 kil, CCITT V.22
protocol is selected. If no switch is used, an internal pull-up sets the status during
power-up to the default state (212A mode).

DIIO

The VL7C215 shifts data serially out of this pin to VL7C212A during a write operation
and shifts data serially into this pin during a read operation from the VL7C212A. On
power-up this pin is an input for a brief time in which the VL7C215 reads the MakelBreak
ratio select switch connected to this pin for selecting the pulse dialing standard. With the
switch open, the Bell standard 39% Make, 61% Break is selected. With the switch
closed to ground through 18 kil, the CCITT standard 33% Make, 67% Break is selected.
Hno switch is used, an internal pull-up sets the status during power-up to the default
state (Bell standard).

360

VLSI TECHNOLOGY, INC.
VL7C215

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Description

TXD

This pin is a serial output pin. During a data call, after the connection is established, the
VL7C215 converts parallel data received from the computer bus and outputs it in a
serial, asynchronous format to the VL7C212A modem for modulation. At all other times
the VL7C215 holds this output in the Mark (high) condition.

RXD

Demodulated data from the VL7C212A modem is received on this pin during a data call.
A high level is considered Mark and a low level is Space. The VL7C215 converts the
serial data into a parallel data byte and stores it in the Receiver Buffer Register (RBR).
The Data Ready bit in the Line Status Register (LSR) is then set, and an appropriate
interrupt identification code is written in the Interrupt Identification Register (IIR) to signal
to the computer, the reception of a new data byte.

GND

Ground reference (0 V).

DO-D7

15-22

This is the 8 bit data bus comprising of three-state input/output lines. This bus provides
bidirectional communication between the VL7C215 and the CPU. Data control words
and status information are transferred via the DO - D7 data bus.

INT

AO-A2

24-26

These three address inputs are used during read or write operation to select a UART
register in the VL7C215 as shown in Table 1. The Divisor Latch Access Bit (DLAB) must
be set high by the system software to access the bit rate divisor latches as shown in
Table 2.

-CS

The VL7C215 is selected when this input is low. When high, the VL7C215 forces the
Data bus lines into a high impedance state.

VCC

Positive supply (+5 V).

TABLE 1. VL7C215 UART REGISTERS
DLAB

RBR

Receiver Buffer Register (read only)

THR

Transmitter Holding Register (write only)

Mnemonic

IER

Interrupt Enable Register

IIR

Interrupt Identification Register (read only)

LCR

Line Control Register

MCR

Modem Control Register

X
X
X

LSR

Line Status Register

MSR

Modem Status (read only) Register

STR

Speed

DLL

Divisor Latch (LSB) (write only)

DLM

Divisor Latch (MSB) (write only)

X - "Don't Care"

0- Logic Low

1 - Logic High

361

VLSI TECHNOLOGY, INC.
VL7C215

FIGURE 1. UART BLOCK DIAGRAM
INTERNAL
DATA BUS

L.. .......--t
...

DATA BUS
BUFFER JIIIII....-l--oM

DO-D7

RECEIVER
BUFFER
REGISTER
L -_
_ __

L.....' -_ _ _ _ _--,1-

RECEIVER
SHIFT

j;-,

LINE
CONTROL
REGISTER

---------1. ....,. .

h....

r--

DIVISOR

LATCH (LS)

BAUD

I+- RXD

RECEIVER
TIMING AND
CONTROL

•

I~__--.....
J

LI.--...aP~-----r~~"'lIGENERATORr
..
DIVISOR
LATCH (MS)

_L.-_ _ _

A O~
A1
A2

-.....
....

-C S~
-0 IST~

L----;-t~~ TRANSMITIER

LINE
STATUS
REGISTER

.......
SELECT
AND
CONTROL
LOGIC

J.......I&------...
...

J...~'---------,

TIMING AND
CONTROL

•

SPEED
REGISTER

-DO ST~

10RDY"-'---..

------...,
lTRANSMITIER
TRANSMITIER L-_ _ _ _ _...,
........
~
SHIFT
~ REGISTER
HOLDING
REGISTER

MODEM
CONTROL
REGISTER

MODEM
STATUS
REGISTER

INTERRUPT
ENABLE
REGISTER

INTERRUPT
ID
REGISTER

362

~ TXD

MODEM
CONTROL
LOGIC

I
I

~I
.....

INTERRUPT
CONTROL
LOGIC

......
J

INT

VLSI TECHNOLOGY, INC.
VL7C215

TABLE 2. VL7C215 UART REGISTER FUNCTION SUMMARY
Register Bit Number

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

RBR

Data

THR

Data

IER

Receive
Data
Available
Interrupt
Enable

THRE
Interrupt
Enable

Receive
line
Status
Interrupt
Enable

Modem
Status
Interrupt
Enable

IiR

a If
Interrupt
Pending

Interrupt
ID Bit 0

Interrupt
ID Bit 1

LCR

a .. 7Bit
Data
1 .. 8 Bit
Data

a = 1 Stop
Bit
1 = 2 Stop
Bits

1 .. Parity
Enable

1 .. ~ven
Parity

1 .. Stick
Parity

1 - Set
Break

DLAB

MCR

Data
Terminal
Ready

Request
to Send

OUT1

OUT2
a-INT
Output
to HI-Z

No
Function

LSR

Data
Ready

Overrun
Error

Parity
Error

Framing
Error

Break
Interrupt

THRE

TSRE

MSR

Trailing
Edge Ring

Delta
RLSD

1 (CTS)

1 (DSR)

RING

RLSD

DLM

Data

DLL

Data

STR

Data

363

VLSI TECHNOLOGY, INC.
VL7C215

TABLE 3. VL7C215 SOFTWARE REGISTERS
Default

Range/Units

Description

0-255 Rings

Ring to answer telephone on

0-255 Rings

Number of rings

0-127 ASCII

Escape code character

0-127 ASCII

Character recognized as carriage return

13 (CR)

0-127 ASCII

Character recognized as line feedback

10 (LF)

0-32, 127 ASCII

Character recognized as back space

8 (8S)

2-255 sec.

Wait time for dial tone

1-255 sec.

Wait time for carrier

0-255 sec.

Pause time (caused by comma)

43 (+)

2
30
2

1-255 1/10 sec.

Carrier detect response time

S10

1-255 111 0 sec.

Delay between loss of carrier and hang up

S11

50-255 millisec.

Duration and spacing of Touch-Tones

S12

20-255 1/50 sec.

Escape code guard time

S13

bit mapped

UART status register

S14

bit mapped

Option register

S15

bit mapped

Flag register

S16

0,1,2,4

Test modes

364

VLSI TECHNOLOGY, INC.
VL7C215

TABLE4.COMMANDSUMMARV
PREFIX, REPEAT AND ESCAPE COMMANDS
Command

Description (Notes 1 & 2)

Attention prefix: precedes all command lines except + + + (escape) and AI(repeat) commands

+++

Escape code: go from on-line state to command state (one second pause before and after escape
code entry; ; + + + is not followed by carriage return)

Repeat last command line (AI is not followed by carriage return)

DIALING COMMANDS
Command

Description (Notes 1 & 2)

Command

Description (Notes 1 & 2)

Dial

Wait for 1/8 second

Pulse*

Wait for silence

Touch-Tone

Wait for second dial tone

Pause

;

Return to command state after dialing

Flash

Reverse mode (to call originate-only modem)

OTHER COMMANDS
Commands

Description (Notes 1 & 2)

Commands

Description (Notes 1 & 2)

Answer call without waiting for ring

Speaker on until carrier detected*

BlBO

CCITT V.22 mode (Note 3)

Speaker always on

Bell 103 and 212A mode*

Go to on-line state

CICO

Transmit carrier off

Remote digitalloopback off*

Carrier on*

Remote digitalloopback request

ElEO

Characters not echoed

0/00

Result codes displayed*

Characters echoed*

Result codes not displayed

FIFO

Half duplex

Sr?

Full duplex*

HlHO

On hook (hang up)

VNO

Digit result codes

Off hook; line and auxiliary relay

Word result codes·

Off hook; line relay only

X/XO

Compatible with Hayes-type 300 modems*

1110

Request product ID code (130)

Result code CONNECT 1200 enabled

Requests curlent value of register r
Sets register r to value of n

Firmware revision number

Enables dial tone detection

Test internal memory

Enables busy signal detection

UL1

Low speaker volume

Enables dial tone and busy signal detection

Medium speaker volume

YIVO

Long space disconnect disabled*

High speaker volume

Long space disconnect enabled

Software reset: restores all default settings

MlMO

Speaker always off

Notes:
1. Default modes are indicated by *.
2. Commands entered with null parameters assume 0 - X is the same as XO.
3. When the ATB command is used in the answer mode, the VL7C212A is placed in either the V.21 or the V.22 mode, depending on the response from the remote modem. In the originate mode, the VL7C215 will sense if the baud rate is set at 300 or
1200 bits per second and will adjust the VL7C212A accordingly.

365

VLSI TECHNOLOGY, INC
VL7C215

TABLE 5. RESULT CODES
Description

Digit Code

Word Code

Command executed

Connect

Connected at 300 or 1200 bps
Connected at 300 bps, if result of X1, X2, X3, or X4 command

Ring

Ringing signal detected (Note)

No Carrier

Carrier signal not detected or lost

Error

Illegal command
Error in command line
Command line exceeds buffer (40 characters, including punctuation)
Invalid character format at 1200 bps

Connect 1200

Connected at 1200 bps. Results from X1, X2, X3, or X4 commands only

No Dialtone

Dialtone not detected and subsequent commands not processed
Results from X2 or X4 commands only

Busy

Busy signal detected and subsequent commands not processed
Results from X3 or X4 commands only

No Answer

Silence not detected and subsequent commands not processed
Results from @ command only

Note: When the VL7C215 detects a ringing on the telephone line, it sends a RING result code. However, the VL7C215
will answer the call only if it is in auto-answer mode or is given an A com mand.

TABLE 6. RESET CONTROL OF REGISTERS AND PINOUT SIGNALS
Register/Signal

Reset State

Reset Control

Receiver Buffer Register

First word received

Transmitter Holding Register

Writing into the Transmitter Holding Register

Data
Data

Interrupt Enable Register

Power on reset

All bits low

Interrupt Identification Register

Power on reset

Bit 0 high; bits 1-7 low

Line Control Register

Writing into the LCR

Data

MODEM Control Register

Power on reset

All bits low

Line Status Register

Power on reset

Bits 0-4, 7 low; bits 5-6 high

Modem Status Register

Power on reset

Bits 0-3, 6-7 low; bits 4-5 high

Divisor Latch (high order bits)

Power on reset

1200 bps

TXD

Master reset

High

INT

Power on reset

Low (high impedence)

366

VLSI TECHNOLOGY, INC.
VL7C215

Bit 0
0
1

Word Length
7 Bits
a Bits

Programmable Baud Rate Generator
The VL7C215's Baud Rate Generator
can be programmed for one of six baud
rates. The desired speed is selected by
writing into the Divisor Latch (DLM) .
On reset, the rate will be 1200 baud.
DLM (Hex Code)
00
01
03
04
06
09

Baud Rate
1200
300
150
110
75
50

367

whenever the received data input is
held in the Spacing (Logic 0) state for
longer than a full word transmission
time - the total time of Start bit + data
bits + Parity + Stop bits.
Bit 5: This bit is the Transmitter Holding
Register Empty (THRE) indicator. Bit 5
indicates that the VL7C215 is ready to
accept a new character for transmission. In addition, this bit causes the
VL7C215 to issue an interrupt to the
CPU when the Transmit Holding
Register Empty enable is set high. The
THRE bit is set to a logic 0 concurrently
with the loading of the Transmitter
Holding Register by the CPU.
Bit 6: This bit is the Transmitter Shift
Register Empty (TSRE) indicator. Bit 6
is set to a logic 1 whenever the Transmitter Shift Register is idle. It is reset to
logic 0 upon a data transfer from the
Transmitter Holding Register to the
Transmitter Shift Register.
Bit 7: This bit is permanently set to
logic o.
Bits 1 through 4 are the error conditions
that produce a Receiver Line Status
interrupt whenever any of the corresponding conditions are detected.
Interrupt Identification Register
The VL7C215 has an on-chip interrupt
capability that allows for complete
flexibility in interfacing to all popular
microprocessors. To provide minimum
software overhead during data character transfers, the VL7C215 prioritizes
interrupts into four levels. The four
levels of interrupt conditions are as
follows: Receiver Line Status (priority
1); Received Data Ready (priority 2);
Transmitter Holding Register Empty
(priority 3); and MODEM Status (priority

4).
Information indicating that a prioritized
interrupt is pending the source of that
interrupt are stored in the Interrupt
Identification Register (refer to Table 7).
The Interrupt Identification Register
(IIR), when addressed during chipselect time, freezes the highest priority
interrupt pending and no other interrupts are acknowledged until the
particular interrupt is serviced by the
CPU. The contents of the fiR are
indicated in Table 2 and are described
below.

VLSI TECHNOLOGY, INC.
VL7C215

Bit 0: This bit can be'used in either a
hardwired prioritized or polled environment to indicate whether an interrupt is
pending. When bit 0 is logic 0, an
interrupt is pending and the IIR contents
may be used as a pointer to the
appropriate interrupt service routine.
When bit 0 is a logic, no interrupt is
pending.
Bits 1 and 2: These two bits of the IIR
are used to identify the highest priority
interrupt pending as indicated in Table

7.
Bits 3 through 7: These five bits of the
IIR are always logic o.
Interrupt Enable Register
This 8-bit register enables the four
interrupt sources of the VL7C215 to
separately activate the Interrupt (INT)
output signal. It is possible to totally
disable the interrupt system by resetting
bits 0 through 3 of the Interrupt Enable
Register. Similarly, by setting the
appropriate bits of this register and the
active (high) INT output from the chip.
All other system functions operate in
their normal manner, including the
setting of the Line Status and MODEM
Status Register. The contents of the
Interrupt Enable Register are indicated
in Table 2 and are described below.
Bit 0: This bit enables the Received
Data Available Interrupt when set to
logic 1.
Bit 1: This bit enables the transmitter
Holding Register Empty Interrupt when
set to a logic 1.

Bit 2: This bit enables the Receiver
Line Status Interrupt when set to logic

MODEM (or peripheral device) to the
In addition to this current-state
information, two bits of the MODEM
Status Register provide change
information. These bits are set to a
logic 1 whenever a control input from
the MODEM changes state. They are
reset to logic 0 whenever the cpu
reads the MODEM Status Register.

cpu.

1.
Bit 3: This bit enables the MODEM
Status Interrupt when set to logic 1.
Bit 4 through 7: These four bits are
always logic o.
MODEM Control Register
This 8-bit register controls the interface
with the MODEM. The contents of the
MODEM Control Register are indicated
in Table 2 and are described below.

The contents of the MODEM Status
Register are indicated in Table 2 and
are described below.
Bits 0 and 1: These bits are always

Bit 0: This bit controls Data Terminal
Ready (DTR) signal. H the external
switch on the -RD pin is set to VCC
through an 18 kQ resistor, setting the
DTR low will force the VL7C215 into the
command state and if on line, it will
hang up.

Bit 3: This bit is the Delta Received
Line Signal Detector (DRLSD) indicator.
Bit 3 indicates that the carrier detector
has changed state.

Bit 1: This bit controls the Request to
Send (RTS) signal. This signal is not
used by the VL7C215.
Bit 2: This bit controls the Output 1
(OUT1) signal. This signal is not used
by the VL7C215.
Bit 3: This bit controls the Output 2
(OUT2) signal. When OUT2 is a 0, the
interrupt output is in high impedence
state.
Bit 4: Not used.
Bits 5 through 7: These bits are
permanently set to logic o.
MODEM Status Register
This 8-bit register provides the current
state of the control lines from the

368

Bit 2: This bit is the Trailing Edge of
Ring Indicator (TERI) detector. Bit 2
indicates that the -RI input to the chip
has changed from On (logic 1) to an Off
(logic 0) condition.

Bit 4: This bit is always 1.
•

Bit 5: This bit is always 1.
Bit 6: This bit is the complement of the
Ring Indicator (-RI) input.
Bit 7: This bit is the Received Line
Signal Detect (RLSD) signal.
Whenever bit 2 is set to logic 1, or bit 3
changes state, a MODEM Status
Interrupt is generated if enabled.

VLSI TECHNOLOGY, INC.
VL7C215

TABLE 7. INTERRUPT CONTROL FUNCTIONS
Interrupt
Identification
Register

Interrupt Set and Reset Functions

Bit 2

Bit 1

Bit 0

Priority
Level

Interrupt Flag

Interrupt Source

Interrupt
Reset Control

None

Highest

Receiver
Line Status

Overrun Error or
Parity Error or
Framing Error or
Break Interrupt

Reading the Line
Status Register

Second

Received Data
Available

Reading the Receiver
Buffer Register

Third

Transmitter Holding
Register Empty

Reading the IIR (if source of
interrupt) or Writing into the
Transmitter Holding Register

Fourth

MODEM Status

Ring Indicator or
Received Line
Signal Detect

Reading the MODEM
Status Register

369

VLSI TECHNOLOGY, INC.
VL7C215

FIGURE 2. ADDRESS DECODER CIRCUIT

PC BUS

NAME

A11

-AEN

A28

A27

A26

A25

A24

A22

A23

74LS04
11

h,..8_ _ _ _

-cs -------1

-CS

VL7C215

-- : :C: =
-- -- -

t ~04

COM 1

824

IRQ4

825

IRQ3

814

-lOR

-DIST

813

-lOW

-DOST

A29

A30

A31

A10

IORDY

.. COM 1

INT

-DIST

.. cOM2

-DOST

370

VLSI TECHNOLOGY, INC.
VL7C215

AC CHARACTERISTICS:
Symbol

TA=OT070°C, VCC=5V±10%

Parameter

Min

Max

Units

Conditions

tDlW

-DI5T Strobe Width

300

1TTL Load

tRC

Read Cycle Delay

300

1TTL Load

620

1TTL Load

Read Cycle .. tDlW + tRC + 20 ns

tDDD

Delay from -DI5T to Data

tHZ

-OI5T to Floating Data Delay

tDOW

300

1TTL Load

-OOST Strobe Width

300

1TTL Load

tWC

Write Cycle Delay

300

1TTL Load

Write Cycle ... tDOW + tWC + 20 ns

620

1TTL Load

tDS

Data Setup Time

1TTL Load

tDH

Data Hold Time

1TTL Load

tDlC

-OIST Delay from Select

150

1TTL Load

tDOC

-OOST Delay from Select

150

1TTL Load

tACR

Address and Chip Select Hold Time from -DIST

1TTL Load

tACW

Address and Chip Select Hold Time from -DOST

1TTL Load

tDlOR

-DIST/-DOST to 10RDY Delay

1TTL Load

tWIOR
Receiver
tRINT

TBD

10RDY Pulse Width

TBD

Delay from -DIST (Read RBR) to Reset Interrupt

100 pF Load

Transmitter
tHR

Delay from -DOST (Write THR) to Reset Interrupt

tlR5

Delay from Initial INTR Reset to Transmit Start

Baud Cycle

tSI

Delay from Initial Write to Interrupt

Baud Cycle

tSS

Delay from Stop to Next Start

tSTI

Delay from Stop to Interrupt (THRE)

tlR

Delay from -DIST (Read IIR) to Reset Interrupt (THRE)

Note: A TTL load is 40 J.1.A sourced and -1.6 mA sinked current.

371

100 pF Load

Baud Cycle
~

100 pF Load

VLSI TECHNOLOGY, INC.
VL7C215

FIGURE 3. READ CYCLE TIMING

-1

-C5--_

tAC!

X'-----~~r_---_;_--L-...I.--VAllO

AO, A1, A2

~""i-_ tOIC - - - . w

----t

------,l-

-015T

ACTIVE

-DOST

---------+---,---"'1----'1
l'

CTIVE

-r__ '--__

OATA _ _ _ _ _ _ _ _ _ _

00-07
_ _ _ _ _ _ _t_D_IO_R_-+
___

I+- tWIOR~1

IOROY

FIGURE 4. WRITE CYCLE TIMING

-C5--_
AO, A1, A2

X
I.

1~CWt=

--.:~~----+--L-~=:
VALID

L ____

C---PI

--==-..t.4----+----~W

tDOC-

-005T

ACTIVE
OR

------------~--_1----(l
-DIST

.
L...~.ltDH...J
.
t-_---c; '--____

':1

tDS fOIIIII

DATA _ _ _ _ _ _ _ _ _ _
0~7

VAllO DATA

10ROY _ _ _ _ _ _ _ _ _ _ _ _
tD_IO_R_t

372

tWIOR1

~ ACTIVE

VLSI TECHNOLOGY, INC.
VL7C215

FIGURE 5. RECEIVER TIMING

RXD (RECEIVER \
INPUT DATA)

.
\ START

'r-c
zl

2
DATA

2l~~----~--~----------------~12C-

SAMPLE ClK

---.J/

INTERRUPT _______________________________

-DIST _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~\tRINT ~

(READ REC DATA
BUFFER)

FIGURE 6. TRANSMITTER TIMING

TXD
START
PARllY
SERIAlOUT - - - - - - - - - - . \
;---D-AT-A--)(J€3

(THRE)
-nOST
(WRTHR)

/ \r;=

~
~
~I
tlRS

INTERRUPT

-J~

~lt~4

START
;,--------

j;=:

tSS
tSTI

"==
I ------'L

tHR

-DIST ___________________________________,.
(RDIIR)

373

VLSI TECHNOLOGY, INC.
VL7C215

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature
Storage Temperature

-65°e to + 1500 e

Supply Voltage to
Ground Potential
Applied Input
Voltage

+6 V

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only, functional
operation of this device at these or any
other conditions above those indicated

in this data sheet is not implied. Exposure to absolute maximum rating
conditions for extended periods may
affect device reliability.

-0.6 V to vee +0.6 V

Power Dissipation

500mW

DC CHARACTERISTICS: TA =0 to +70 °C, VCC =5 V ±10%
Symbol

Parameter

Min

vee

Positive Supply Voltage

4.5

ICC

Operating Current

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VT+

Positive Hysterisis Threshold

VT-

Negative Hysterisis Threshold

VOH

VOL

Max

5.0

5.5

10.0

Units

FCLK

Clock Frequency

@VCC=5V

All pins except -RI

2.5

-RI pin

1.8

-RI pin

VCC-1.0

Digital signal pins DO to 07
and INT @ 10H = -6 mA

VCC-1.0

All other output or 110 pins
@IOH =-2 mA

0.4

Digital signal pins DO to 07
and INT@IOL=6mA

0.4

All other output or 1/0 pins
@IOL=2mA

2.0
0.8

Low Level Output Voltage

Leakage Current (Note)

Conditions

V
mA

High Level Output Voltage

Note:

Typ

±1.0
7.3721

7.3728

7.3735

MHz

This applies to all pins except TEST, which has an internal pull-down -WR, -RD, SCK, 0110 and switch input pins
which have internal pull-ups.

374

VLSI TECHNOLOGY, INC
VL7C215

FIGURE 7. INTEGRAL SMART MODEM CONFIGURA110N FOR PC BUS APPLICATIONS

COMPUTER
PARAllEL
BUS
r--

DO-D7

AO
A1
A2

......
......
.......

IORDY

.........

-lOR

...
......

-lOW
-AEN

......

lR03
.....
IR04

.........

A3-A9

L":>
'--

DO-D7

......

...

RXD

TXD

DIIO

ClK

.....
...

SCK

.....
...

-WR
INT

TXD

....
...

-RD
l,..,.

--c ~-c --c ~-c~

5/8

JGE

Jump if>

5/8

JLE

Jump if < or =

5/8

JLT

Jump if <

5/8

Jump if Overflow

5/8

JNV

Jump if No Overflow

5/8

Jump if Higher

5/8

JNH

Jump if Not Higher

5/8

LCALL

Long Call

LD/LDB

Load

MUL

0<--- A * B

NOP

No Operation

ORIORB

0<--- 0 OR A

XORIXORB

0<--- 0 XOR A

PUSHF

Push PSB

POPF

Pop PSB

RET

Return

SHUSHLB

Shift Left

11 + N***

SHLL

Shift Left Long

15 +N*"

SHRlSHRB

Shift Right

11 + N*"

SHRL

Shift Right Long

15 +N***

428

VLSI TECHNOLOGY, INC
VL7C225 • VL7C235 • VL7C245

TABLE 8. INSTRUCTION SET TABLE (CONT.)
Mnemonic
SHRA

Number
Of Operands

Bytes·

Operation
Arith. Right Shift

Tlme**

10 + N·"

SHRAL

Arith. Right Long

15 + N···

SJMP

Short Jump

LJMP

Long Jump

ST/STB

Store to Memory

13····

SUB/SUBB

B <--- B-A

SUB/SUBB

D <--- B-A

• Add one for immediate words.
··Add 9 for indirect mode and 2 or 0 for immediate mode, see table.
·"N is number of bit shifts.
····Indirect mode

429

VLSI TECHNOLOGY, INC.
VL 7C225 • VL 7C235 • VL 7C245

THE MAC AND INTEL 8096 SPEED COMPARISON
Table 9 is an instruction execution time
comparison for the MAC and Intel 8096.
The biggest improvement over 8096 is
the 16 bit multiplication it is 3.3 Ils
versus 6.5 Ils. The jump instructions
are twice faster. The shift instructions

are also about twice faster. The other
arithmetic and logic instructions are
about the same speed. Indirect
addressing instructions in the MAC is
about 20% slower than in the 8096.
The following comparison is for the

8096 with 12 MHz crystal and the MAC
with 19.6608 MHz. The time unit is
"IJ.S". The instructions and operands are
all from internal storage. Both the MAC
and Intel 8096 will run slower for
external RAM access.

TABLE 9. MAC AND 8096 SPEED COMPARISON
Direct
Instr.

Operands

MAC (IlS)

Immediate
8096 (IlS)

MAC (IlS)

8096 (IlS)

Indirect
MAC (IlS)

8096 (IlS)

ADD

1.02

1.00

1.22

1.25

1.94

1.50

ADD

1.02

1.25

1.22

1.50

1.94

1.75

ADDB

1.02

1.00

1.02

1.00

1.94

1.50

ADDB

1.02

1.25

1.02

1.25

1.94

1.75

AND

1.02

0.75

1.22

1.25

1.94

1.50

AND

1.02

1.00

1.22

1.50

1.94

1.75

ANDB

1.02

1.00

1.02

1.00

1.94

1.50

ANDB

1.02

1.25

1.02

1.25

1.94

1.75

CMP

1.02

1.00

1.22

1.25

1.94

1.50

CMPB

1.02

1.00

1.02

1.00

1.94

1.50

DJNZ

0.9211.25

EXTB

0.71

JBC

1.0211.32

1.25/2.25

(No Jump/Jump)

1.00
1.25/2.25

JBS

1.0211.32

1.25/2.25

0.51/0.82

1.00/2.00

0.51/0.82

1.00/2.00

JGE

0.51/0.82

1.00/2.00

JGT

0.51/0.82

1.00/2.00

0.51/0.82

1.00/2.00

JLE

0.51/0.82

1.00/2.00

JLT

0.51/0.82

1.00/2.00

JNC

0.51/0.82

1.00/2.00

JNE

0.51/0.82

1.00/2.00

JNH

0.51/0.82

1.00/2.00

JNV

0.51/0.82

1.00/2.00

0.51/0.82

1.00/2.00

430

VLSI TECHNOLOGY, INC.
VL 7C225 • VL 7C235 • VL 7C245

TABLE 9. MAC AND 8096 SPEED COMPARISON (CONT.)
Direct
Instr.

Operands

LCALL
LO
LOB
MUL

MAC(~S)

Immediate
8096 (~s)

MAC(~s)

8096 (~s)

Indirect
MAC (~s)

8096 (~s)

1.12

3.25

1.02

1.00

1.22

1.25

1.94

1.50

1.02

1.00

1.02

1.00

1.94

1.50

3.36

6.50

NOP

(Biggest Improvement)

0.24

1.00

1.02

1.00

1.22

1.25

1.94

1.50

ORB

1.02

1.00

1.02

1.00

1.94

1.50

PUSHF

0.51

2.00

POPF

0.51

2.25

RET

1.02

3.00

SHL

1.12 + 0.10N

1.75 + 0.25N

SHLB

1.12 + 0.10N

1.75 + 0.25N

SHLL

1.53 + 0.10N

1.75 + 0.25N

SHR

1.12 + 0.10N

1.75 + 0.25N

SHRB

1.12 + 0.10N

1.75 + 0.25N

SHRL

1.53 + 0.10N

1.75 + 0.25N

SHRA

1.02+0.10N

1.75 + 0.25N

SHRAL

1.53 + 0.10N

1.75 + 0.25N

SJMP

0.71

1.32

1.75

STB

1.32

1.75

(N = Shift Count)

2.00

SUB

1.02

1.00

1.22

1.25

1.94

1.50

SUBB

1.02

1.00

1.02

1.00

1.94

1.50

SUB

1.02

1.25

1.22

1.50

1.94

1.75

SUBB

1.02

1.25

1.02

1.25

1.94

1.75

XOR

1.02

1.00

1.22

1.25

1.94

1.50

XORB

1.02

1.00

1.02

1.00

1.94

431

VLSI TECHNOLOGY, INC.
VL7C225 • VL7C235 • VL7C245

RAM READ OR WRITE CYCLE TIMING
Symbol

Parameter

Min

Typ

Max

Unit

tAS

Address Setup

152

tWOS

Write Data Setup

203

tRDS

Read Data Setup

305

tSW

-CSRAM Strobe Width

610

tAW

ALE Strobe Width

101

tWW

-WR Strobe Width

203

tRW

-RD Strobe Width

305

tED

Delay to -WR/-RD

254

tWDH

Write Data Hold

tRDH

Read Data Hold

Condition

RAM READ OR WRITE CYCLE WAVEFORMS

CYCLE #
9.8304 MHz
INTERNAL ClK

-CSRAM

MAO-MA14

ADO-AD7
(WRITE CYCLE)

"'""""'="'"~""'"

-WR
(WRITE CYCLE)
-RD
(READ CYCLE)

ADO-AD7

(READ CYCLE)

ALE

IAS:::I

~lAyv~-------------------------------------

_______________

432

VLSI TECHNOLOGY, INC
VL7C225 • VL7C235 • VL7C245

EXTERNAL PROGRAM STORAGE READ BUS CYCLE TIMING

Symbol

Parameter

Data Setup

Data Hold

-CSROM Strobe Width

Min

Typ

Max

Unit

203

EXTERNAL PROGRAM STORAGE READ BUS CYCLE WAVEFORMS

CYCLE #
9.8304 MHz
INTERNAL elK

MAO-MA14

-CSROM

------~><~------~><~------ - - - - - . l<1li'--- tW--__. _ - - - tH
tS

~--t.c

ADO-AD7 - - - - - - - - - - - - - - ( '

433

Condition

VLSI TECHNOLOGY, INC.
VL7C225 • VL7C235 • VL7C245

READ CYCLE: PC BUS READ FROM UART REGISTER TIMING
Symbol

Parameter

Min

Enable Strobe Width

300

-DIST to Data Delay

Data Hold

tAH

Address Hold

Read Cycle Delay

Typ

Max

Unit

Condition

250

175

READ CYCLE: PC BUS READ FROM UART REGISTER WAVEFORMS (Parallel Configuration Only)

AO-A2

-CS

-DIST

.;It'
~tAH~

~~
......
.....

V
I'-.

00-07

......
.....

~IC
......
.....

.....
..... --- "'

434

tR
I+-tH

....~"

VLSI TECHNOLOGY, INC.
VL7C225· VL7C235 • VL7C245

WRITE CYCLE: PC BUS WRITE INTO UART REGISTER TIMING
Symbol

Parameter

MIn

-DOST Strobe Width

300

Data Setup

Data Hold

tAH

Address/Select Hold

Write Cycle Delay

200

Typ

Max

UnIt

Condition

WRITE CYCLE: PC BUS WRITE INTO UART REGISTER WAVEFORMS (Parallel Configuration Only)

AO-A2

-CS

-DOST
tW

DATA
(00-07)

435

VLSI TECHNOLOGY, INC
VL7C225· VL7C235 • VL7C245

MAP AND EERAM BUS INTERFACE WRITE CYCLE TIMING
Symbol

Parameter

tSS

Delay to ALE

Min

tAW

ALE Strobe Width

tAS

Address Setup

tAH

Address Hold

Typ

Max

Unit

101

Delayto-WR

101

-WR Strobe Width

203

tOH

Data Hold

101

Condition

MAP AND EERAM BUS INTERFACE WRITE CYCLE WAVEFORM
CYCLE #
9.8304 MHz
INTERNAL ClK

ALE
-MCS
OR
-ECS
tAS
ADO-AD7

tAH
ADDRESS

DATA
tDH

-WR

436

VLSI TECHNOLOGY, INC.
VL7C225 • VL7C235 • VL7C245

MAP AND EERAM BUS INTERFACE READ CYCLE TIMING

Symbol

Parameter

tSS

Delay to ALE

tAW

ALE Strobe Width

tAS

Address Setup

tAH

Address Hold

Min

Typ

Max

Unit

101

Delayto-RD

101

-RD Strobe Width

305

tDS

Data Setup

tDH

Data Hold

Condition

MAP AND EERAM BUS INTERFACE READ CYCLE WAVEFORMS

CYCLE #
9.8304 MHz
INTERNAL ClK

ALE
-MCS
OR
-ECS

ADO-AD7

-RD

437

VLSI TECHNOLOGY, INC.
VL 7C225 • VL 7C235 • VL 7C245

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

O°C to +70°C

Storage Temperature -65°C to + 150°C
Supply Vottage to
Ground Potential
Applied Voltage

+6 V

300 mW

DC CHARACTERISTICS:

=O°C to +70°C, vec =5 V ±10%

Parameter

Min

VCC

Positive Supply Voltage

4.5

ICC

Operating Current

VIH

High Level Input Voltage for:
00-07, -CS, -OIST, -OOST
All Other Input Pins

VIL

those indicated on the operational
sections of this specification is not
implied and exposure to conditons for
extended periods may affect device
reliability.

-0.6 V to VCC +0.6 V

Power Dissipation

Symbol

Stresses above those listed under
"Absolute Maximum Ratings" may
cause permanent damage to the
device. These are stress ratings only.
Functional operation of this device at
these or any other conditions above

Typ

Max

5.0

5.5

35.0

2.0

O.SVCC

00-07, -CS, -OIST, -OOST

VT+

O.S

0.2VCC

±1.0

J.LA

Positive Hysterisis Threshold
for RESET and -RI Input Pins

2.5

VT-

Nelftive Hysterisis Threshold
for ESET and -RI Input Pins

1.S

VOH

High Level Output Voltage for:
00-07, -INTO

0.7VCC+ 0.5

ROY
All Other Output Pins
VOL

0.7VCC+ 0.5

Low Level Output Voltage for:

IOH =S mA

Open Collector

IOH .. 2mA

00-07, -INTO

0.3VCC-0.5

IOL =S mA

ROY

0.3VCC-0.5

IOL""S mA

0.3VCC-0.5

IOL=2mA

19.6610

MHz

All Other Output Pins
FCLK

VCC= 5 V

All Other Input Pins
Input Leakage Current

Condition

V
mA

Low Level Input Voltage for:

Unit

Crystal Frequency

19.6606

19.6608

438

VLSI TECHNOLOGY, INC.
VL7C312
300/1200 BIT-PER-SECOND MODEM
WITH PIN PROGRAMMABLE RECEIVER GAIN
DESCRIPTION

FEATURES
• FSK and PSK modulators and
demodulators, high-band and lowband filters with compromise amplitude and group delay equalizers
• Pin programmable receiver gain
• Built-in call progress mode and tone
generators for DTMF V.21 and V.22
guard tones
• Bell 212A and CCITT V.21 and V.22
compatible; V.22 notch filters included
• Serial control interface

• High level of integration provides a
highly cost effective 300/1200 bitper- second modems
• Eliminates external components,
easing design of intelligent modems
• Usable in North American and
European modem designs
• Simple board layout
• Simple speaker interface for monitoring phone line
• Testable signal path

• Programmable audio output port

• Reduced board area

• Analog, digital, and remote digital
loopback capabilities

• Direct replacement for Sierra
SC11015

• 24-pin DIP and 28-pin plastic
leaded chip carrier available

PIN DIAGRAMS

The VL7C312 is a complete 300/1200
bit-per-second modem enhanced with a
pin to allow external control of the
modem receiver'S gain. All of the signal
processing functions needed for a full
duplex, 300/1200 bit-par-second 212A
(V.21 or V.22) modem, including both
FSK and PSK modulators and demodulators and the high-band and low-band
filters, are integrated on a single chip. It
is built using a three-micron CMOS
double-polysilicon process that allows
analog and digital functions to be
combined on the same chip. This design
includes capabilities for progress
monitoring and for generating DTMF as
well as V.21 or V.22 guard tones. The
two-to-four wire hybrid is also included,
simplifying the interface to a DM. The
VL7C312 also includes analog loopback
and remote digitalloopback functions for
self-testing.

BLOCK DIAGRAM

VL7C312-PC

vee

AGNO
TXCKO
TXCK1
TEST 1
TEST2
RXCK
AUDIO OUT
GS
RXA1

CKOUT
DGND
XTAL2
XTAL1
N.C.

-WR
-AO
SCI<
0110
TXD

RXA2
TXOUT
VSS

RXD
VL7C312-QC
CKOUT

XTALl
XTAL2
4
TEST 1

N.C.

TXCKO
TXCKl

3 21282726

•

25
24
23

TEST 2

RXCK

9
10
11

21
20
19

AUDIO OUT
GS
RXA1

12 1314 1516 17 18

XTAL2
XTAl1
N.C.
-WR
N.C.
-RD
SCK

ORDER INFORMATION
Part
Number

Package

VL7C312-PC
VL7C312-QC

Plastic DIP
Plastic Leaded Chip Carrier (PLCC)

Note: Operating temperature range is O°C to +70°C.

439

VLSI TECHNOLOGY, INC.
VL7C312

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number (Note)

Signal
Description

TXD

Transmit Data- Data on this input is modulated by the modem and output on TXOUT pin.
A logic low is space and a logic high is mark.

RXD

D I/O

Data 110- Data is shifted in serially when WR is low on rising edges of SCK clock. Data is
transferred to a latch when WR goes high. Up to seven data bits can be sent. Input
codes are defined in Table 1. Data is read from the modem serially when RD is low, on
rising edges of SCK clock. Up to four data bits can be read. Output codes are defined in
Table 1.

-WR

Strobe output from the controller for shifting data to the modem.

-RD

Strobe output from the controller for serially reading data from the modem.

SCK

Serial shift clock is applied to this pin. It is normally high until data is sent to, or read
from, the modem.

TXOUT

Transmit data carrier output.

RXA1, RXA2

9,10

Received data carriers.

Gain Select- When left open or tied to VSS, the received signal gain compensation is 0
dB; connected to ground, +2 dB compensation is provided; connected to VCC, the compensation is +3 dB.

AUDIO OUT

Output of the hybrid is passed through a programmable attenuator and brought out on
this pin. Four levels of received signal can be programmed using the control codes listed
in Table 1.

XTAL1, XTAL

20,21

Pins for connecting a 7.3728 MHz crystal. An external clock signal can be applied to the
XTAL1 pin.

CKOUT

Buffered crystal oscillator signal is output on this pin. It can drive one LS TTL load.

TXCKO

Transmitter Clock Output- In high speed, synchronous internal mode, this output supplies
a 1200 Hz clock to the DTE.

TXCK1

In high speed, synchronous external mode this pin is an input for receiving a 1200 Hz
clock from the DTE.

RXCK

Receiver Clock Output- In high speed, synchronous, external mode, the modem supplies
a 1200 Hz clock on this output.

VCC

+ 5 V power supply.

VSS

- 5 V power supply.

DGND

Digital ground.

AGND

Analog ground.

TEST1,2

4,5

Used by VLSI for testing. Make no connection to these pins. They must be left floating.

N.C.

No Connect- No internal connection is made to this pin and it may be left floating.

Note: Pin numbers refer to the DIP package.

440

G VLSI

TECHNOLOGY, INC.

FUNCTIONAL
DESCRIPTION
With the addition of a digital controller,
such as an 8-bit microcontroller and a
data access arrangement (DAA), a
highly cost effective, integrated, intelligent modem can be built. When used
with the VLSI VL7C213A modem
controller, which is an a-bit processor
combined with a UART, a complete
Hayes command set compatible modem
can be configured, taking up a minimum
of board area. For stand-alone applications, the VL7C312 modem, the
VL7C213 controller, a DAA and an
RS232-interface are all that are required.
The VL7C312 is truly a modem on a
chip. All of the signal processing
functions needed for a full duplex, 3001
1200 bps Bell 212A or cClrr V.21 or
V.22 modem are integrated on a single
chip. It operates in a synchronous or
asynchronous mode and handles 8, 9,
10, or 11 bit words.
Like all modems, the VL7C312 needs a
controller to determine the mode of
operation, initiate the call to the remote
modem (either pulse or tone dialing), set
up the handshaking sequence with the
remote modem, monitor the call progress
tones on the line (ringing, busy, answer
tone, and voice) and switch into the data
mode. A simple four-line serial data
interface was designed for the VL7C312,
enabling it to work with just about any 8bit microcontroller or microprocessor.
The control lines are: DATA INPUTI
OUTPUT, SHIFT CLOCK, READ and
WRITE.

MODEM
Major sections of the VL7C312 modem
are a transmitter, a receiver, low-band
and high-band filters, a two-to-four wire
hybrid, tone generators and interface
logic. It also contains an energy detector
that's used for detecting the carrier and
call progress monitoring and an audio
output for monitoring the line.
The VL7C312 modem requires plus and
minus five volts and is available in a 24pin DIP as well as a 28-pin plastic chip
carrier with "J" leads for surface mount
applications. The transmitter section
consists of an asynclsync converter,
scrambler, PSK modulator. and FSK
modulator. In the high speed mode
(1200 bps), the PSK modulator is

VL7C312
connected to the filter. In the low speed
mode (300 bps), the FSK modulator is
connected to the filter.

TRANSMITTER
Since data terminals and computers
may not have the timing accuracy
required for 1200 bps transmission
(0.01%), timing correction on the
incoming data stream must be made.
The asynclsync converter accepts
asynchronous serial data clocked at a
rate between 1200 Hz + 1%, -2.5%. It
outputs serial data at a fixed rate of
1200 Hz +/- 0.01% derived from the
master clock oscillator. To compensate
for the input and output rate differences,
a stop bit is either deleted or inserted
when necessary. If the input data rate is
slower than the output data rate, a stop
bit is inserted. If the input data rate is
faster than the output data rate, a stop
bit is deleted. The output of the async/
sync converter is applied to the scrambler.
The scrambler is a 17-bit shift register
clocked at 1200 Hz. Outputs from the
14th and 17th stages are exclusive OR'd
and further exclusive OR'd with the input
data. The resultant data is supplied to
the 0 input of the shift register. Outputs
from the first two stages of the shift
register form the dibit that is applied to
the PSK modulator. The purpose of the
scrambler is to randomize data so that
the energy of the modulated carrier is
spread over the band of interest. The
high-band being centered at 2400 Hz or
the low-band, centered at 1200 Hz. A
1200 bps modem actually sends two bits
at a time, called a dibit; dibits are sent at
600 baud, the actual rate of transmission; 600 baud is the optimum rate that
can be transmitted over the general
switched telephone network for a full
duplex FDM (frequency division multiplexing) modem because band limit
filters in the central office cut off at about
3000 Hz.
The dibit applied to the PSK modulator
produces one of four differential phase
shifts of the square wave carrier signal
(1200 Hz or 2400 Hz) at the 600 Hz
baud rate. The resultant waveform is
passed through a wave shaping circuit
that performs a raised cosine function
(this is the shape factor called out in the
cClrr V.21 and V.22 specifications;

441

and it also meets the Bell 212A requirement for optimum transmission). The
wave shaped signal is then passed
through either the lOW-band or highband filter depending upon originate or
answer mode selection.
For low speed operation the FSK
modulator is used. It produces one of
four precision frequencies depending on
originate or answer mode and the 1
(mark) or 0 (space) level of the transmit
data. The frequencies are produced
from the master clock oscillator using
programmable dividers. The dividers
respond quickly to data changes,
introducing negligible bit jitter while
maintaining phase coherence. The
output of the FSK modulator is applied
to the appropriate filter when the low
speed mode of the operation is selected.
The filter section consists of low-band
(1200 Hz) and high-band (2400 Hz)
filters, half-channel compromise
amplitude and group delay equalizers
for both bands, smoothing filters for both
bands and multiplexers for routing of the
transmit and receive signals through the
appropriate band filters. For cClrr
V.21 or V.22 applications, a notch filter
is included that can be programmed for
either 550 Hz or 1800 Hz. In the call
progress monitor mode, the low-band
filter is scaled down by a factor of 2.5 to
center it over a frequency range of 300
to 660 Hz. Thus, during call establishment in the originate mode, call progress tones can be monitored through the
scaled low-band filter and the modem
answer tone or voice can be monitored
through the unscaled high-band filter.
The low-band filter is a 10th order
switched-capacitor band-pass filter with
a center frequency of 1200 Hz. In the
originate mode, this filter is used in the
transmit direction; in the answer mode it
is used in the receive direction. When
analog loopback is used in the originate
mode, this filter, together with the lowband delay equalizer, is in the test loop.
In the call progress monitoring mode the
filter response is scaled down by 2.5,
moving the center frequency to 480 Hz.
The low-band delay equalizer is a 10th
order switched-capacitor all-pass filter
that compensates for the group delay
variation of the low-band filter and half
of the compromise line characteristics,

VLSI TECHNOLOGY, INC.

producing a flat delay response within
the pass-band.
The high-band fi~er is a 10th order
switched-capacitor band-pass filter with
a center frequency of 2400 Hz. In the
answer mode, this filter is used in the
transmit direction; in the originate mode,
it is used in the receive direction. When
analog loopback is used in the answer
mode, this fi~er, together with the highband delay equalizer, will be in the test
loop.
The high-band delay equalizer is a 10th
order switched-capacitor all-pass filter
that compensates for the group delay
variation of the high-band filter and half
of the compromise line characteristics,
producing a flat delay response within
the pass-band. The transmit smoothing
filter is a second order low-pass
switched-capacitor filter that adds the
modem transmit signal to the DTMF
(V.21 or V.22) guard tones. It also
provides a 3 dB per step programmable
gain function to set the output level.
RECEIVER
The receiver section consists of an
energy detector, AGC, PSK demodulator, FSK demodulator, descrambler, and
sync/async converter.
The received signal is routed through
the appropriate band-pass filter and
applied to both the energy detector and
AGC circuit. The energy detector is
based on a peak detection algorithm. It
provides a detection within 17 to 24 ms.
It is set to turn on when the signal
exceeds -43 dBm and turn off when the
signal falls below -48 dBm. A 2 dB
minimum hysteresis is provided between
the turn on and turn off levels.
The AGC circuit is a programmable gain
amplifier that covers a range of 28 dB in
seven steps. The gain is controlled by a
3 bit up/down counter and the Gain
Select (GS) pin. See the Signal Description section for operation. Output of the
AGC amplnier is rectified and compared
with two preset levels corresponding to
desired high and low limits. Outputs of
the comparators control the up/down
counter such that the received signal is
amplified to the desired level.
The PSK demodulator uses a coherent
demodulation technique. Output of the
AGC amplnier is applied to a dual phase
splitter that produces an in-phase and

VL7C312
90 degree out of phase component.
These components are then demodulated to baseband in a mixer stage
where individual components are
multiplied by the recovered carrier. The
baseband components are low-pass
fi~ered to produce I and Q (In-phase and
Quadrature) channel outputs. The I and
Q channel outputs are rectified,
summed, and passed through a bandpass fi~er giving a 600 Hz signal. This
signal is applied to a digital phase lock
loop (DPLL) to produce a baud rate
clock. Using the recovered clock signal,
the I and Q channels are sampled to
produce the received dibit data. The
recovered carrier for the demodulator is
generated by another PLL which is
controlled by the amplitude of the error
signal formed by the difference of the I
and Q outputs.
The descrambler is similar to the
scrambler. The received dibit data is
applied to the D input of a 17 bit shift
register clocked at 1200 Hz. Outputs
from the 14th and 17th stages are
exclusive OR'd and further exclusive
OR'd with input data to produce received
data.
In the asynchronous mode, data from
the descrambler is applied to the sync/
async converter to reconstruct the
originally transmitted asynchronous
data. For data which had stop bits
deleted at the transmitter (overspeed
data), these stop bits are reinserted.
Underspeed data is passed essentially
unchanged. Output of the sync/async
converter along with the output of the
FSK demodulator is applied to a
mu~iplexer. The mu~iplexer selects the
appropriate output, depending on the
operating speed, and outputs received
data on the RXD pin.
For low speed operation, the FSK
demodulator is used. The output of the
AGC amplifier is passed through a zero
crossing detector and applied to a
counter that is reset on zero crossings.
The counter is designed to cycle at a
rate four times faster than the carrier
signal. The counter output is low-pass
filtered and hard limited to generate FSK
data.
HYBRID
The signal on the phone line is the sum
of the transmit and receive signals. The
hybrid subtracts the transmitted signal
442

from the signal on the line to form the
received signal. It is important to match
the hybrid impedance as closely as
possible to the telephone line to produce
only the received signal. This matching
provided by an external resistor connected between the RXA1 and RXA2
pins on the VL7C312. The filter section
provides sufficient attenuation of the out
of band signals to eliminate leftover
transmit signals from the received
signal. The hybrid also acts as a first
order low-pass antialiasing filter.
INTERNAL HYBRID
The VL7C312's internal hybrid is
intended to simplify the phone line
interface. In addition, there is a gain
select feature to compensate for the loss
in the line coupling transformer used in
the DAA. By tieing this pin to VSS,
ground or VDD, compensation levels of
0, +2 or +3 dB, respectively, are
provided.
With a higher loss transformer, some
degradation in performance at lower
signal levels will occur. Specifically, the
bit error rate, when operating at receive
will be higher. The energy detect on/off
levels measured at the line will also be
different from those specified at the chip.
With a 3 dB loss transformer, for
example, the energy detect on/off levels
measured at the line will be in the range
of -40/-45 dB rather than -43/-48 dB as
specified at the chip. The +3 dB
compensation should then be used.
TONE GENERATOR
The tone generator section consists of a
DTMF generator and a V.21 (or V.22)
guard tone generator. The DTMF
generator produces all of the tones
corresponding to digits 0 through 9 and *
and # keys. The V.21 (or V.22) guard
tone generator produces either 550 Hz
or 1800 Hz. Selection of either the 550
Hz or 1800 Hz tone will cascade the
corresponding notch filter with the lowband fi~er. The tones are selected by
applying appropriate codes through the
Data 110 pin. Before a tone can be
generated, tone mode must be selected.
Facility is also provided to generate
single tones corresponding to the
individual rows or column of the DTMF
signal.
AUDIO OUTPUT STAGE
A programmable attenuator that can
drive a load impedance of 50 Kn is

VLSI TECHNOLOGY, INC
VL7C312

provided to allow monitoring of the
received line signal through an external
speaker. The attenuator is connected to
the output of the hybrid. Four levels of
attenuation: no attenuation, 6 dB
attenuation, 12 dB attenuation and
squelch are provided through the ALC1,
ALCO and audio output level control
codes. Output of the attenuator is
available on the audio output pin where
an external audio amplifier (LM386-type)
can be connected to drive a low
impedance speaker. The output can
directly drive a high impedance
transducer, but the volume level will be
low.
CRYSTAL OSCILLATOR
The VL7C312 includes an inverting
amplifier between pins 20 and 21 with
an internal bias resistor to simplify the
design fo the crystal oscillator. A
parallel resonant, 7.3728 MHz iO.001 %
crystal, designed for a load capacitance
of 20 pF, should be connected across
pins 20 and 21. Two capacitors of
typical values 27 pF from pin 20 to
digital ground (oGNo pin 22) and 47 pF
from pin 21 to oGNo should be connected. With the recommended crystal,
Saronix, NYMPH, NYP073-20 and these
capacitor values, a highly accurate and
stable crystal oscillator can be designed.
Since the carrier frequency must be
within iO.01 % of the nominal 1200/2400
Hz, it is important to measure the actual
crystal oscillator frequency at CKOUT.
(pin 23) and adjust the external caP~CI
tors for a given circuit board layout, If
necessary.
VL7C213 AND VL7C214
CONTROLLERS
The VL7C213 modem controller,
implemented in VLSI's two-micron
CMOS process, was designed specifically to handle all of the modem control
functions, as well as the interface to a
system bus. Besides including an 8-bit
microprocessor, 8K by 8 bytes of ROM,
and 128 by 8 bytes of RAM, it also
contains the functionality of a VL82C50
UART, greatly simplifying the interface.
to a parallel system bus, such as used In
an IBM PC-compatible personal
computer (PC). In fact, a complete,
Hayes compatible modem for the PC
consists of the VL7C213 controller, the
VL7C312 modem and the OM. All of
the popular communications software

written for the PC will work with the
VL7C3121VL7C213 set.
Another version of the controller, the
VL7C214, is intended for RS-232
applications. It contains the same
processor, memory, and UART as the
VL7C213 and has the same interface to
the modem chip. The difference is that
the UART is turned around so that serial
data from the RS-232 port is converted
to parallel data handled by the internal
processor. Pins are provided for
connecting the familiar switches and
indicator lamps found on most standalone modems, although the switches
and lamps are not needed for operation.
All of the switch settings can be done
through software.
The VL7C214 provides a standard five
volt logic level interface. RS-232 drivers
are required to interface to the port.
Like the VL7C213, the VL7C214 comes
preprogrammed with the Hayes "AT"
command set, and when used with the
VL7C312 modem, emulates a Hayestype stand-alone modem. The VL7C213
and VL7C312 emulate a Hayes-type
IBM PC plug-in card modem. But the
chip set is by no means limited to
implementing a Hayes-type smart
modem. VLSI is in the custom IC
business and both chips were designed
with this in mind. For example, only
about 6K bytes of the VL7C213's ROM
is used for the handshaking and smart
modem code, leaving 2K bytes for
additional features that a customer may
specify. Since the controller is ROM
programmable, any command set can
be implemented.
Both the VL7C213 and VL7C214 require
plus five volts and are available in either
a 28-pin DIP or a 28-pin plastic chip
carrier with "J" leads for surface mount
applications. Besides the four-line
interface for the VL7C312 modem, the
VL7C213 controller has an 8-bit data
port, three address lines, a chip select
input, an interrupt line, and the oOST
and olST control lines found in the
8250B UART. It also has control lines
for ring indication, the off-hook relay and
a data/voice relay; these three lines
connect to the OM.
In the VL7C214, the 8-bit port becomes
the switch input lines and the address,
chip select, olST and ooST lines

443

become the six lines for the RS-232
interface. These six lines are also used
to drive the LEOs. Internally, all of these
lines are treated as programmable 1/0
ports under software control. The
primary difference between the
VL7C213 and VL7C214 is the ROM
code. It also contains the same modem
and OM interface lines as the
VL7C213.
The VL7C213 and VL7C214 are truly
ASIC controllers. They are designed to
control a modem or other peripheral that
operates at a moderately slow data rate
up to 1200 bits per second. The
VL7C213 allows a slow peripheral to
interface to a high speed bus, without
making the main processor slow down.
This is done through the UART interface
and the on-chip registers which look
somewhat like dual port registers. The
main processor can write to and read
from them at will, while the on-chip
controller can do the same. The
controller was designed this way
because most communication software
has to have unrestrained access to the
UART registers. To make the VL7C213
compatible with this software, the
registers were included.
The internal processor monitors the
registers to determine the mode of
operation. Command mode or data
mode: at power-up it is automatically put
in the command mode and it looks for
instructions. Once carrier is detected, it
goes into the data mode, an~ stays " "
there until escape sequence IS three +
signs (+++) in the default mode, but it
can be changed in software.
The processor contains an 8-bit data
path and can execute 19 instructions
with five addressing modes: direct,
indirect, immediate, register direct, and
register indirect. There is 8K by 8 of
ROM on-chip for program storage.
To the system bus, the VL7C213looks
and acts just like a VL82C50 UART. All
of the communications software written
for this UART will work with the
VL7C213 and VL7C214. The VLSI chip
set is a Hayes-type modem in two chips.
The VL7C312 AND
VL7C2131VL7C214 System
The only external components required
by the VL7C212A are the 600 n line

VLSI TECHNOLOGY, INC.

matching resistor. a 7.3728 MHz crystal
(a standard frequency) and a 20 pF
capacitor from each leg of the crystal to
ground. If ~ is desired to drive a
speaker to monitor the line. an amplifier
such as the LM386 can be added. but
the output provided on the VL7C312
can directly drive a high impedance (50
kO) earphone-type transducer.
The VL7C213 modem controller's clock
in line is driven by the VL7C312's clock
out line. so only one crystal is needed.
The VL7C213 interfaces directly to an
IBM PC bus -- no buffers are required.
The only external parts may be an eight
input NAND gate for COM1 and COM2
decoding inside the PC.
For tone dialing. the controller sends a
code to the modem chip which in turn
puts out the called for DTMF tone on
the line via the on-chip DTMF generator. For pulse dialing. the controller
pulses the OH (off-hook) relay. Both
dialing modes work w~h the built-in call
progress algor~hm so they won't start
dialing until a dial tone is detected.

VL7C312
All modems require a OM. A DAA
(data access arrangement) is a piece of
equipment required by the FCC to
connect anything to the general
switched telephone network. It consists
of an isolation transformer. typically 600
o to 600 0; a relay for disconnecting
the modem from the line; a ring
detector. typically an opto-isolator; and
high voltage surge protectors. The DAA
has to be FCC registered and this can
be done by any of many consultants
and labs around the country. Another
alternative is to buy a DAA. supplied by
several manufacturers.
212A is a Bell specification that calls for
1200 b~ per second. full or half duplex
data transmission w~h a fallback mode
of 300 baud (Bell 103). It is not 1200
baud; the spec calls for transmission of
dibits. or 2 bits per baud so the 1200
bps transmission takes place at 600
baud. The same is true for V.22; it's
1200 bps or 600 baud. V.22 does not
call for a 300 baud fallback; the CCITT

444

standard for 300 baud is V.21. It is not
a required fallback for V.22. however. it
is included in the VL7C312A.
V.22 also calls for' guard tones to be
sent along with the data. In most of
Europe the tone is 1800 Hz except in
Sweden where 550 Hz is used. The
VL7C312A modem has the 550 Hz and
1800 Hz tone generators built in as well
as the 550 and 1800 Hz notch filter to
remove the guard tone when in the
receive mode.
All modems require a hybrid. Hybrid is
a term used to describe a circu~.
passive or active. that takes the
separate transm~ and receive signals
and combines them to go over the
phone line. In the VL7C312A. this is
done w~h op amps. but the separate
signals (TXOUT and RXA2) are also
brought out so an external hybrid can
be used. if desired. The combined
signal comes out on the RXA 1 pin and
a matching resistor (typically 600 0) is
connected between RXA1 and RXA2.

VLSI TECHNOLOGY, INC.
VL7C312

TABLE 1. DEFINITION OF 1/0 CODES '
1. Instructions to the modem IC
Data on the 0 I/O pin is shifted into the modem when WR is low, on rising edges of the SCK clock. Data is transferred
into a latch when WR goes high. (See Figure 2 for write cycle waveforms.) Up to seven data bits (00--06) can be sent
to the device. These bits control the operating modes of the modem as show below:

03-00

0
1
2

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

4
5
6
7
8
9
A
B
C

0
E
F
0
1
2
3
4
5
6
7
8
9

0
1
2
3
4
5
6
7
8
9
A
B
C

0
E
F

Mode/Function

Non-Tone Mode:
Reset (set default values)
Tone On/Off
Force Receive Data to Mark Off/On
TLCO Transmit Level Control Bit 0 (default 0)
TLC1 Transmit Level Control Bit 1 (default 0)
TX
Transmitter On/Off
ALB
Analog Loopback On/Off
CPM Call Progress Monitor Mode On/Off
Connection Indicator (CI) On/Off
ALCO Audio Output Level Control Bit 0 (default 0)
ALC1 Audio Output Level Control Bit 1 (default 0)
WLSO Word Length Select 0 (default 0)
WLS1 Word Length Select 1 (default 1)
SynC/Async
LS/HS: Low SpeedlHigh Speed
AlO:
Answer/Originate
Transmit Mark On/Off
Transmit Space On/Off
Scrambler Disable On/Off
DLB
Digital Loopback On/Off
TXDP Transmit Dotting Pattern On/Off
Locked/Internal
ExternaVSlave
2100 Hz Tone On/Off (Must select low speed mode for operation)
1300 Hz Tone On/Off (Must select low speed mode for operation)
V.21 On/Off (Must select low speed mode for operation)
Tone Mode:
Dial 0
Dial 1
Dial 2
Dial 3
Dial 4
DialS
Dial 6
Dial 7
Dial 8
Dial 9
Dial *
Dial #
Output 550 Hz and Insert 550 Hz Notch in Low-Band Filter
Output 1800 Hz and Insert 1800 Hz Notch inLow-Band Filter
Row Disable On/Off
Column Disable On/Off

445

VLSI TECHNOLOGY, INC
VL7C312

TABLE 1. DEFINITION OF I/O CODES (Cont.)
WLS1

0
0

1
1

0
1
0
1

WLSO

0
1
0
1

Word Length
8 Bits
9 Bits
10 Bits (default)
11 Bits

TLC1

TLCO

0
0
1
1

0
1
0
1

-12 (default)
-9

ALC1

ALCO

Audio Output Level

0
0
1
1

0
1
0
1

Output Off (default)
12 dB Attenuation
6 dB Attenuation
No Attenuation

0
1
0
1

Transmitter Output Level (dBm) at the Phone Line

-6

2. Information from the Modem IC
Data is read serially from the modem when RD is low, on rising edges of the SCK clock. (See Figure 1 for read cycle
waveforms.) Up to four data bits (00--03) can be read as defined below:
DO

Energy Detect

0 - No Energy

1 - Energy Present

In the CPM mode, the energy detector is connected to the output of the high-band filter, if ALB is off, or the scaled lowband filter, if ALB is on.
01
02
03

Received Data (FSK)
Received Data (PSK)
Unscrambled Mark

1 - Mark
1 - Mark
1 - Detected

0- Space
0- Space
o - Not Detected

Notes:
1. Default values forthe operating modes on power-up are those shown to the right of the "r unless otherwise specified.
2. Data is shifted in and out of the modem with LSB first.

446

VLSI TECHNOLOGY, INC.
VL7C312

TABLE 2 AC CHARACTERISTICS
Symbol

Parameter

Min

tOW

Delay Time to Write

200

tDR

Delay Time to Read

200

tPW

Complete SCK Cycle

1.0

SCK High Pulse Duration

Crystal Frequency

7.3721

Typ

Max

Units

Conditions

ms
%

70
7.3728 7.3735

Duty Cycle

MHz

FIGURE 1. WAVEFORMS FOR WRITE AND READ CYCLES
a) Write Cycle

tPW
b) R..d
-RD

-..I !.- .....J

C -1r+F-tDR---I

Cy":"
Ir-

\.-tP

lOR

0110 XXIooI011021031XXXXX
LJlJlJ

SCK

DTMF GENERATOR
Parameter

CRYSTAL FREQUENCY -7372800
MHz±O%
.
Nominal Frequency

Allowable Error

Actual Error

Row 1

697Hz

±1%

+ 0.17%

Row 2

770 Hz

±1%

-0.26%

Row 3

852Hz

±1%

+ 0.16%

Row4

941 Hz

±1%

-0.47%

Column 1

1209 Hz

±1%

-0.74%

Column2

1336 Hz

±1%

-0.89%

Column 3

1477 Hz

±1%

-0.01%

550Hz

±20 Hz

-1.4 Hz

1800 Hz

±20 Hz

+ 7Hz

Guard Tones

447

VLSI TECHNOLOGY, INC.
VL7C312

DTMF GENERATOR

(Cont.)
Typ

Min

Conditions

Parameter

Max

Units

Second Harmonic Distortion

VCC= +5 V

-40

Row Output Level

VSS=-5 V

dBm

TLCO = 1

dBm

550 Hz Guard Tone Level

TLC1 = 1

-3

dB (Note 2)

1800 Hz Guard Tone Level

Measured at TXOUT Pin

-6

dB (Note 2)

Column Output Level

MODEM TRANSMIT SIGNALS

CRYSTAL FREQUENCY

8ell103

Mode

= 7.372800 MHz ±OO/O
8ell212A I CCITTV.22

CCITTV.21

Nominal

Actual

Nominal

Actual

Mark

2225 Hz

2226 Hz

1650 Hz

1649.4 Hz

Space

2025 Hz

2024.4 Hz

1850 Hz

1850.6 Hz

Mark

1270 Hz

1269.4 Hz

980 Hz

978.34 Hz

Space

1070 Hz

1070.4 Hz

1180 Hz

1181.53 Hz

Calling Tone

1300 Hz

Answer Tone

2100 Hz

Answer

Originate

Nominal

Actual

2400 Hz

1200 Hz

1301.7 Hz

1300 Hz

1301.7 Hz

2096.9 Hz

2100 Hz

2096.9 Hz

RECEIVER
Parameter

Min

Conditions

Input Signal Range

At RXA 1 (pin 9 )

Intra - Character Bit Rate

At RXD ( pin 13 )

1170

Carrier Detect

At RXA 1 (pin 9 )

-48

Typ

-45

Carrier Detect Hysterisis

Max

Units

dBm
.{

1200

1224

bps

-43

dBm
dB

Carrier Detect Delay

For 103, 212A and V.22

Carrier Detect Hold

For 103, 212A and V.22

Carrier Detect Delay

For V.21 mode

Carrier Detect Hold

For V.21 mode

448

,.'

VLSI TECHNOLOGY, INC.
VL7C312

TRANSMITTER
Parameter
Input Character Length

Conditions

Min

Start Bit + Data Bit + Stop Bit

At TXD (pin 14)

1170

M .. Character Length

2M+3

Intra - Character Bit Rate
Input Break Sequence Length
Output Level Tolerance

Typ

Max

1200

Units

bits

1212

bps
bits

±1

ABSOLUTE MAXIMUM RATINGS
Ambient Temperature
Under Bias:

-10°C to +80°C

Storage Temperature
Range:
-65°C to + 140°C
Maximum Supply
Voltage: VCC .. +7.0 V, VSS .. -7.0 V

those in the operational sections of this
specification is not implied and exposure to absoute maximum rating
conditions for extended periods may
effect device reliability.

Input Voltage Range:
Analog Pins; VSS -0.6 V to VCC+0.6 V
Digital Pins; DGND-O.6 V to VCC+0.6 V
Maximum Power
Dissipation @25°C:

500mW

DC CHARACTERISTICS TA= O°C to 70° C unless otherwise specified
Symbol

Parameter

VCC

Positive Supply Voltage

VSS

Negative Supply Voltage

ICC

Quiescent Current

ISS

Quiescent Current

VIH

High Level Input Voltage

Min

Typ

Max

4.5

5.0

5.5

-4.5

-5.0

-5.5

15
15
2.0

Units

Conditions

V
V
mA

VCC - 5 V

VSS --5V

Digital Signal Pins: -RD, -WR, OlIO,
SCK,TXCK1,TXD

VIL

Low Level Input Voltage

0.8

Digital Signal Pins: -RD, -WR, DIIO,
SCK, TXCK1, TXD

VOH

VOL

High Level Output Voltage

4.0

@IOH. 40 ~ (D SPins: D 110, CKOUT,

2.0

@IOH-500~

@IOL-160 ~ (D SPins: D 110, CKOUT,

Low Level Output Voltage

0.4

RXD, TXCKO, RXCK)

RXD, TXCKO, RXCK)
VOM

Maximum Output Signal

4.0

VOM

Maximum Output Signal

1.0

VIM

Maximum Input Signal

4.0

449

Vp-p

TXOUT, RL-1200 n (TLC1-1, TLCO-O)

Vp-p

Audio Out, RL- 50 kn

Vp-p

RXA1, RXA2

VLSI TECHNOLOGY, INC.

450

VLSI TECHNOLOGY, INC.
VL7C412
300/1200 BIT-PER-SECOND MODEM
(SINGLE 5-VOLT POWER SUPPLY)
DESCRIPTION

FEATURES
• FSK and PSK modulators and
demodulators, high-band and lowband filters with compromise amplitude and group delay equalizers

• High level of integration provides a
highly cost effective 300/1200 bitper- second modems
• Eliminates external components,
easing design of intelligent modems

• Single 5 V power supply with power
down by pin or code

• Usable in North American and
European modem designs

• Pin programmable receiver gain
• Built-in call progress mode and tone
generators for DTMF V.21 and V.22
guard tones

• Simple board layout
• Simple speaker interface for monitoring phone line

• Bell 212A and CCITT V.21 and V.22
compatible; V.22 notch filters included

• Testable signal path
• Reduced board area

• Serial control interface

• Direct replacement for Sierra
SC11016

• Programmable audio output port
• Analog, digital, and remote digital
loopback capabilities
• 24-pin DIP and 28-pin plastic
leaded chip carrier available

PIN DIAGRAMS

The VL7C412 is a complete, 5 V single
supply, 300/1200 bit-per-second
modem enhanced with a pin to allow
external control of the receiver's gain.
All of the signal processing functions
needed for a full duplex, 300/1200 bitper-second 212A (V.21 or V.22) modem,
including both FSK and PSK mooulators .
and demodulators and the high-band
and low-band filters, are integrated on a
single chip. It is built using a threemicron CMOS double-polysilicon
process that allows analog and digital
functions to be combined on the same
chip. This design includes capabilities
for progress monitoring and for generating DTMF as well as V.21 or V.22 guard
tones. The two-to-four wire hybrid is
also included, simplifying the interface to
a DM. The VL7C412 also includes
analog loopback and remote digital
loopback functions for self-testing.

BLOCK DIAGRAM

VL7C412·PC
VREF
TXCKO
TXCK1
TEST 1
TEST 2
RXCK
AUDIO OUT
GS
RXA1
RXA2
TXOUT
AGND

vee
CKOUT
DGND
XTAL2
XTAL1

~;;;;~-;~~~~~~~~R~l
R~

-WR
-RD
SCK
DVO
TXD
RXD
0110

VL7C412·QC

SCK
-RO

CKOUT
XTALl
XTAL2
TXCKO
TXCKl

-WR
PO

TEST 1
N.C.
TEST 2

RXCK
AUDIO OUT

as
RXA1

XTAL2
XTAL1
PO
-WR
N.C.
-AD

ORDER INFORMATION
Part
Package

Number

SCI(

VL7C412-PC
Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
VL7C412-OC
Note: Operating temperature range is O°C to +70°C.

451

VLSI TECHNOLOGY, INC
VL7C412

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number (Note)

Signal
Description

TXD

Transmit Data- Data on this input is modulated by the modem and output on TXOUT pin.
A logic low is space and a logic high is mark.

RXD

DIIO

-WR

Strobe output from the controller for shifting data to the modem.

-RD

Strobe output from the controller for serially reading data from the modem.

SCK

Serial shift clock is applied to this pin. It is normally high until data is sent to, or read
from, the modem.

TXOUT

Transmit data carrier output.

RXA1, RXA2

9,10

Received data carriers.

Gain Select- When left open or tied to ground, the received signal gain compensation is
odB; connected to VREF, +2 dB compensation is provided; connected to VCC, the compensation is +3 dB.

AUDIO OUT

Output of the hybrid is passed through a programmable attenuator and brought out on
this pin. Four levels of received signal can be programmed using the control codes listed
in Table 1.

XTAL1, XTAL

20,21

Pins for connecting a 7.3728 MHz crystal. An external clock signal can be applied to the
XTAL1 pin.

CKOUT

Buffered crystal oscillator signal is output on this pin. It can drive one LS TTL load.

TXCKO

Transmitter Clock Output- In high speed, synchronous internal mode, this output supplies
a 1200 Hz clock to the DTE.

TXCK1

In high speed, synchronous external mode this pin is an input for receiving a 1200 Hz
clock from the DTE.

RXCK

Receiver Clock Output- In high speed, synchronous, external mode, the modem supplies
a 1200 Hz clock on this output.

Power Down- When this input is high, the device will be powered down, but the oscillator
will keep running. When the pin is low, the device will go into normal power mode.

VCC

+ 5 V power supply.

AGND

Analog Ground- This ground line should be routed separately, and connected to a central
grounding point with the digital ground (DGND) as close to the power supply as possible.

DGND

Digital groun~.

VREF

Vo~age Reference- This output is a mid-supply reference, generated internally, that is
approximately VCC+ 2 in value. It is used as a reference point for the line transformer.
VREF should be bypassed to AGND using a 50 IlF electrolytic capacitor and a 0.1 IlF
ceramic capacitor in parallel.

TEST1,2

4,5

Used by VLSI for testing. Make no connection to these pins. They must be left floating.

Note: Pin numbers refer to the DIP package.

452

VLSI TECHNOLOGY, INC.
VL7C412

FUNCTIONAL
DESCRIPTION
With the addition of a digital controller;
such as an 8-bit microcontroller and a
data access arrangement (DAA), a
highly cost effective, integrated, intelligent modem can be built. When used
with the VLSI VL7C213A modem
controller, which is an 8-bit processor
combined with a UART, a complete
Hayes command set compatible modem
can be configured, taking up a minimum
of board area. For stand-alone applications, the VL7C412 modem, the
VL7C213 controller, a DAA and an
RS232-interface are all that are required.
The VL7C412 is a modem on a chip. All
of the signal processing functions
needed for a full duplex, 300/1200 bps
Bell 212A or CCITT V.21 or V.22 modem
are integrated on a single chip. It
operates in a synchronous or asynchronous mode and handles 8, 9, 10, or 11
bit words.
Like all modems, the VL7C412 needs a
controller to determine the mode of
operation, initiate the call to the remote
modem (either pulse or tone dialing), set
up the handshaking sequence with the
remote modem, monitor the call progress
tones on the line (ringing, busy, answer
tone, and voice) and switch into the data
mode. A simple four-line serial data
interface was designed for the VL7C412,
enabling it to work with just about any 8bit microcontroller or microprocessor.
The control lines are: DATA INPUTI
OUTPUT, SHIFT CLOCK, READ and
WRITE.

connected to the filter. In the low speed
mode (300 bps), the FSK modulator is
connected to the filter.

Major sections of the VL7C412 modem
are a transmitter, a receiver, low-band
and high-band filters, a two-to-four wire
hybrid, tone generators and interface
logic. It also contains an energy detector
that's used for detecting the carrier and
call progress monitoring and an audio
output for monitoring the line.

The VL7C212A modem requires only
plus five volts, and is available in a 24pin DIP as well as a 28-pin plastic chip
carrier with "J" leads for surface mount
applications. The transmitter section
consists of an async/sync converter,
scrambler, PSK modulator. and FSK
modulator. In the high speed mode
(1200 bps), the PSK modulator is

MODEM

453

and it also meets the Bell 212A requirement for optimum transmission). The
wave shaped signal is then passed
through either the lOW-band or highband filter depending upon originate or
answer mode selection.
For low speed operation the FSK
modulator is used. It produces one of
four precision frequencies depending on
originate or answer mode and the 1
(mark) or 0 (space) level of the transmit
data. The frequencies are produced
from the master clock oscillator using
programmable dividers. The dividers
respond quickly to data changes,
introducing negligible bit jitter while
maintaining phase coherence. The
output of the FSK modulator is applied
to the appropriate filter when the low
speed mode of the operation is selected.
The filter section consists of low-band
(1200 Hz) and high-band (2400 Hz)
filters, haH-channel compromise
amplitude and group delay equalizers
for both bands, smoothing filters for both
bands and multiplexers for routing of the
transmit and receive signals through the
appropriate band filters. For CCITT
V.21 or V.22 applications, a notch filter
is included that can be programmed for
either 550 Hz or 1800 Hz. In the call
progress monitor mode, the low-band
filter is scaled down by a factor of 2.5 to
center it over a frequency range of 300
to 660 Hz. Thus, during call establishment in the originate mode, call progress tones can be monitored through the
scaled low-band filter and the modem
answer tone or voice can be monitored
through the unscaled high-band filter.
The low-band filter is a 10th order
switched-capacitor band-pass filter with
a center frequency of 1200 Hz. In the
originate mode, this filter is used in the
transmit direction; in the answer mode it
is used in the receive direction. When
analog loopback is used in the originate
mode, this filter, together with the lowband delay equalizer, is in the test loop.
In the call progress monitoring mode the
filter response is scaled down by 2.5,
moving the center frequency to 480 Hz.
The low-band delay equalizer is a 10th
order switched-capacitor all-pass filter
that compensates for the group delay
variation of the lOW-band filter and half of
the compromise line characteristics,

VLSI TECHNOLOGY, INC
VL7C412

producing a flat delay response within
the pass-band.
The high-band filter is a 10th order
switched-capacitor band-pass filter with
a center frequency of 2400 Hz. In the
answer mode, this filter is used in the
transmit direction; in the originate mode,
it is used in the receive direction. When
analog loopback is used in the answer
mode, this filter, together with the highband delay equalizer, will be in the test
loop.
The high-band delay equalizer is a 10th
order switched-capacitor all-pass filter
that compensates for the group delay
variation of the high-band filter and half
of the compromise line characteristics,
producing a flat delay response within
the pass-band. The transmit smoothing
filter is a second order low-pass
switched-capacitor filter that adds the
modem transmit signal to the DTMF
(V.21 or V.22) guard tones. It also
provides a 3 dB per step programmable
gain function to set the output level.

RECEIVER
The receiver section consists of an
energy detector, AGC, PSK demodulator, FSK demodulator, descrambler, and
synclasync converter.
The received signal is routed through
the appropriate band-pass filter and
applied to both the energy detector and
AGC circuit. The energy detector is
based on a peak detection algorithm. It
provides a detection within 17 to 24 ms.
It is set to turn on when the signal
exceeds -43 dBm and turn off when the
signal falls below -48 dBm. A 2 dB
minimum hysteresis is provided between
the turn on and turn off levels.
The AGC circuit is a programmable gain
amplifier that covers a range of 28 dB in
seven steps. The gain is controlled by a
3 bit up/down counter and the Gain
Select (GS) pin. See Signal Descriptions
for operation. Output of the AGC
amplifier is rectified and compared with
two preset levels corresponding to
desired high and low limits. Outputs of
the comparators control the up/down
counter such that the received signal is
amplified to the desired level.
The PSK demodulator uses a coherent
demodulation technique. Output of the
AGC amplifier is applied to a dual phase
splitter that produces an in-phase and

90 degree out of phase component.
These components are then demodulated to baseband in a mixer stage
where individual components are
multiplied by the recovered carrier. The
baseband components are low-pass
filtered to produce I and Q (In-phase and
Quadrature) channel outputs. The I and
Q channel outputs are rectified,
summed, and passed through a bandpass filter giving a 600 Hz signal. This
signal is applied to a digital phase lock
loop (DPLL) to produce a baud rate
clock. Using the recovered clock signal,
the I and Q channels are sampled to
produce the received dibit data. The
recovered carrier for the demodulator is
generated by another PLL which is
controlled by the amplitude of the error
signal formed by the difference of the I
and Q outputs.
The descrambler is similar to the
scrambler. The received dibit data is
applied to the D input of a 17 bit shift
register clocked at 1200 Hz. Outputs
from the 14th and 17th stages are
exclusive OR'd and further exclusive
OR'd with input data to produce received
data.
In the asynchronous mode, data from
the descrambler is applied to the sync/
async converter to reconstruct the
originally transmitted asynchronous
data. For data which had stop bits
deleted at the transmitter (overspeed
data), these stop bits are reinserted.
Underspeed data is passed essentially
unchanged. Output of the synclasync
converter along with the output of the
FSK demodulator is applied to a
multiplexer. The multiplexer selects the
appropriate output, depending on the
operating speed, and outputs received
data on the RXD pin.

INTERNAL HYBRID
The VL7C412 internal hybrid is intended
to simplify the phone line interface. In
addition, there is a gain select feature to
compensate for the loss in the line
coupling transformer used in the DAA.
By tieing this pin to VSS, ground or
VDD, compensation levels of 0, +2 or +3
dB, respectively, are provided.
With a higher loss transformer, some
degradation in performance at lower
signal levels will occur. Specifically, the
bit error rate, when operating at receive
will be higher. The energy detect on/off
levels measured at the line will also be
different from those specified at the chip.
With a 3 dB loss transformer, for
example, the energy detect onloff levels
measured at the line will be in the range
of -401-45 dB rather than -43/-48 dB as
specified at the chip. The +3 dB
compensation should then be used.

TONE GENERATOR

The tone generator section consists of a
DTMF generator and a V.21 (or V.22)
guard tone generator. The DTMF
generator produces all of the tones
corresponding to digits 0 through 9 and *
and # keys. The V.21 (or V.22) guard
tone generator produces either 550 Hz
or 1800 Hz. Selection of either the 550
Hz or 1800 Hz tone will cascade the
corresponding notch filter with the lowband filter. The tones are selected by
applying appropriate codes through the
Data I/O pin. Before a tone can be
generated, tone mode must be selected.
Facility is also provided to generate
single tones corresponding to the
individual rows or column of the DTMF
signal.

HYBRID

AUDIO OUTPUT STAGE

The signal on the phone line is the sum
of the transmit and receive signals. The
hybrid subtracts the transmitted signal

A programmable attenuator that can
drive a load impedance of 50 kn is
provided to allow monitoring of the

454

"VLSI TECHNOLOGY, INC.
VL7C412
received line signal through an external
speaker. The attenuator is connected to
the output of the hybrid. Four levels of
attenuation: no attenuation, 6 dB
attenuation, 12 dB attenuation and
squelch are provided through the ALC1,
ALCO and audio output level control
codes. Output of the attenuator is
available on the audio output pin where
an external audio amplifier (LM386-type)
can be connected to drive a low
impedance speaker. The output can
directly drive a high impedance
transducer, but the volume level will be
low.
VL7C213 AND VL7C214
CONTROLLERS
The VL7C213 modem controller,
implemented in VLSI's two-micron
CMOS process, was designed specifically to handle all of the modem control
functions, as well as the interface to a
system bus. Besides including an 8-bit
microprocessor, 8K by 8 bytes of ROM,
and 128 by 8 bytes of RAM, it also
contains the functionality of a VL82CSO
UART, greatly simplifying the interface
to a parallel system bus, such as used in
an IBM PC-compatible personal
computer (PC). In fact, a complete,
Hayes compatible modem for the PC
consists of the VL7C213 controller, the
VL7C412 modem and the DAA. All of
the popular communications software
written for the PC will work with the
VL7C412NL7C213 set.
Another version of the controller, the
VL7C214, is intended for RS-232
applications. It contains the same
processor, memory, and UART as the
VL7C213 and has the same interface to
the modem chip. The difference is that
the UART is turned around so that serial
data from the RS-232 port is converted
to parallel data handled by the internal
processor. Pins are provided for
connecting the familiar switches and
indicator lamps found on most standalone modems, although the switches
and lamps are not needed for operation.
All of the switch settings can be done
through software.
The VL7C214 provides a standard five
volt logic level interface. RS-232 drivers
are required to interface to the port.
Like the VL7C213, the VL7C214 comes
preprogrammed with the Hayes "AT"
command set, and when used with the

VL7C412 modem, emulates a Hayes-

type stand-alone modem. The VL7C213
and VL7C412 emulate a Hayes-type
IBM PC plug-in card modem. But the
chip set is by no means limited to
implementing a Hayes-type smart
modem. VLSI is in the custom IC
business and both chips were designed
with this in mind. For example, only
about 6K bytes of the VL7C213's ROM
is used for the handshaking and smart
modem code, leaving 2K bytes for
additional features that a customer may
specify. Since the controller is ROM
programmable, any command set, not
just the Hayes "AT" set, can be implemented.
Both the VL7C213 and VL7C214 require
plus five volts and are available in either
a 28-pin DIP or a 28-pin plastic chip
carrier with "J" leads for surface mount
applications. Besides the four-line
interface for the VL7C412 modem, the
VL7C213 controller has an 8-bit data
port, three address lines, a chip select
input, an interrupt line, and the DOST
and DIST control lines found in the
8250B UART. It also has control lines
for ring indication, the off-hook relay and
a data/voice relay; these three lines
connect to the DAA.
In the VL7C214, the 8-bit port becomes
the switch input lines and the address,
chip select, DIST and DOST lines
become the six lines for the RS-232
interface. These six lines are also used
to drive the LEOs. Internally, all of these
lines are treated as programmable 110
ports under software control. The
primary difference between the
VL7C213 and VL7C214 is the ROM
code. It also contains the same modem
and DAA interface lines as the
VL7C213.
The VL7C213 and VL7C214 are truly
ASIC controllers. They are designed to
control a modem or other peripheral that
operates at a moderately slow data rate
up to 1200 bits per second. The
VL7C213 allows a slow peripheral to
interface to a high speed bus, without
making the main processor slow down.
This is done through the UART interface
and the on-chip registers which look
somewhat like dual port registers. The
main processor can write to and read
from them at will, while the on-chip

455

controller can do the same. The
controller was designed this way
because most communication software
has to have unrestrained access to the
UART registers. To make the VL7C213
compatible with this software, the
registers were included.
The internal processor monitors the
registers to determine the mode of
operation. Command mode or data
mode: at power-up it is automatically put
in the command mode and it looks for
instructions. Once carrier is detected, it
goes into the data mode, and stays
there until escape sequence is three "+"
signs (+++) in the default mode, but it
can be changed in software.
The actual processor contains an 8-bit
data path and can execute 19 instructions with five different addressing
modes: direct, indirect, immediate,
register direct, and register indirect.
There is 8K by 8 of ROM on-chip for
program storage.
To the system bus, the VL7C213 looks
and acts just like a VL82CSO UART. All
of the communications software written
for this UART will work with the
VL7C213 and VL7C214. The VLSI chip
set is a Hayes-type modem in two chips.
CRYSTAL OSCILLATOR
The VL7C412 includes an inverting
amplifier between pins 20 and 21 with
an internal bias resistor to simplify the
design fa the crystal oscillator. A
parallel resonant, 7.3728 MHz ±0.001 %
crystal, designed for a load capacitance
of 20 pF, should be connected across
pins 20 and 21. Two capacitors of
typical values 27 pF from pin 20 to
digital ground (DGND pin 22) and 47 pF
from pin 21 to DGND should be connected. With the recommended crystal,
Saronix, NYMPH, NYP073-20 and these
capacitor values, a highly accurate and
stable crystal oscillator can be designed.
Since the carrier frequency must be
within ±0.01% of the nominal 120012400
Hz, it is important to measure the actual
crystal oscillator frequency at CKOUT
(pin 23) and adjust the external capacitors for a given circuit board layout, if
necessary.
The VL7C412 AND
VL7C2131VL7C214 System
The only external components required
by the VL7C412 are the 600 n line

VLSI TECHNOLOGY, INC.

matching resistor, a 7.3728 MHz crystal
(a standard frequency) and a 20 pF
capacitor from each leg of the crystal to
ground. If it is desired to drive a
speaker to monitor the line, an amplifier
like the LM386 can be added, but the
output provided on the VL7C412 can
directly drive a high impedance (50 kn)
earphone-type transducer.
The VL7C213 modem controller's clock
in line is driven by the VL7C412's clock
out line, so only one crystal is needed.
The VL7C213 interfaces directly to an
IBM PC bus -- no buffers are required.
The only external parts may be an eight
input NANO gate for COM1 and COM2
decoding inside the PC.
For tone dialing, the controller sends a
code to the modem chip which in turn
puts out the called for OTMF tone on
the line via the on-chip OTMF generator. For pulse dialing, the controller
pulses the OH (off-hook) relay. Both
dialing modes work with the built-in call
progress algorithm so they won't start

VL7C412
dialing until a dial tone is detected.
All modems require a OM. A OM
(data access arrangement) is a piece of
equipment required by the FCC to
connect anything to the general
switched telephone network. It consists
of an isolation transformer, typically 600
to 600 Q; a relay for disconnecting
the modem from the line; a ring
detector, typically an opto-isolator; and
high voltage surge protectors. The OM
has to be FCC registered and this can
be done by any of many consultants
and labs around the country. Another
alternative is to buy a OM, supplied by
several manufacturers.

212A is a Bell specification that calls for
1200 bit per second, full or half duplex
data transmission with a fallback mode
of 300 baud (Bell 103). It is not 1200
baud; the spec calls for transmission of
dibits, or 2 bits per baud so the 1200
bps transmission takes place at 600
baud. The same is true for V.22; it's
1200 bps or 600 baud. V.22 does not

456

call for a 300 baud fallback; the CCITI
standard for 300 baud is V.21. It is not
a required fallback for V.22, however, it
is included in the VL7C412.
V.22 also calls for guard tones to be
sent along with the data. In most of
Europe the tone is 1800 Hz except in
Sweden where 550 Hz is used. The
VL7C412 modem has the 550 Hz and
1800 Hz tone generators built in as well
as the 550 and 1800 Hz notch filter to
remove the guard tone when in the
receive mode.
All modems require a hybrid. Hybrid is
a term used to describe a circuit,
passive or active, that takes the
separate transmit and receive signals
and combines them to go over the
phone line. In the VL7C412, this is
done with op amps, but the separate
signals (TXOUT and RXA2) are also
brought out so an external hybrid can
be used, if desired. The combined
signal comes out on the RXA 1 pin and
a matching resistor (typically 600 0) is
connected between RXA 1 and RXA2.

"VLSI TECHNOLOGY, INC.
VL7C412
TABLE 1. DEFINITION OF 1/0 CODES
1. Instructions to the modem IC
Data on the D I/O pin is shifted into the modem when WR is low, on rising edges of the SCK clock. Data is transferred
into a latch when WR goes high. (See Figure 2 for write cycle waveforms.) Up to seven data bits (DO--D6) can be sent
to the device. These bits control the operating modes of the modem as show below:
06

03-00

Mode/Function

0
0
0
0
0

0
0

0
0
0
0

1/0
1/0
110
1/0
1/0
1/0
110
110
110
110
110
110
110
1/0
1/0
1/0
1/0
110
1/0
110
110
110
1/0
1/0
110
110
1

0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A

Non-Tone Mode:
Reset (set defau~ values)
Tone OnlOff
Force Receive Data to Mark OffIOn
TLCO Transmit Level Control Bit 0 (default 0)
TLC1 Transmit Level Control Bit 1 (default 0)
TX
Transmitter OnlOff
ALB
Analog Loopback OnlOff
CPM Call Progress Monitor Mode OnlOff
Connection Indicator (CI) OnlOff
ALCO Audio Output Level Control Bit 0 (default 0)
ALC1 Audio Output Level Control Bit 1 (default 0)
WLSO Word Length Select a (default 0)
WLS1 Word Length Select 1 (default 1)
SynclAsync
LS/HS: Low SpeedlHigh Speed
AlO:
AnswerlOriginate
Transmit Mark OnlOff
Transmit Space On/Off
Scrambler Disable OnlOff
DLB
Digital Loopback OnlOff
TXDP Transmit Dotting Pattern OnlOff
Locked/lnternal
External/Slave
2100 Hz Tone OnlOff (Must select low speed mode for operation)
1300 Hz Tone OnlOff (Must select low speed mode for operation)
V.21 OnlOff (Must select low speed mode for operation)
Power Down. To power up, device must be reset.

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

110
1/0
1/0
1/0
1/0
1/0
1/0
110
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

a
0
0
0
0

a
0
0

a
a
0
0

a
0
0
0
0

a
a
a
a
a
0
0
0
0
0

a
a
0
0
1
1
1
1
1
1
1
1
1
1
1

a
a

0
1
2
3
4
5
6
7
8
9
A
B
C

0
0
0

E
F

0
0

a
a
a
a
a
a
0

Tone Mode:
Dial a
Dial 1
Dial 2
Dial 3
Dial4
Dial5
Dial 6
Dial 7
Dial 8
Dial 9
Dial·
Dial #
Output 550 Hz and Insert 550 Hz Notch in Low-Band Filter
Output 1800 Hz and Insert 1800 Hz Notch inLow-Band Fi~er
Row Disable On/Off
Column Disable On/Off

457

VLSI TECHNOLOGY, INC
VL7C412

TABLE 1. DEFINITION OF 1/0 CODES (Cont.)
WLS1

WLsa

0
0

0
1
0
1

Word Length
8 Bits
9 Bits
10 Bits (default)
11 Bits

TLC1

TLca

0
0
1
1

0
1
0
1

-14 (default)
-12
-10

ALC1

ALCO

Audio Output Level

0
0
1

0
1
0

0
1
0
1

Output Off (default)
12 dB Attenuation
6 dB Attenuation
No Attenuation

0
1
0
1

Transmitter Output Level (dBm) at the Phone Line

-8

Energy Detect

0 - No Energy

1 - Energy Present

In the CPM mode, the energy detector is connected to the output of the high-band filter, if ALB is off, or the scaled lowband filter, ~ ALB is on.
01
02
03

Received Data (FSK)
Received Data (PSK)
Unscrambled Mark

1 - Mark
1 - Mark
1 - Detected

0- Space
0- Space
o - Not Detected

Notes:
1. Default values for the operating modes on power-up are those shown to the right of the
2. Data is shifted in and out of the modem with LSB first.

458

tor unless otherwise spec~ied.

VLSI TECHNOLOGY, INC.
VL7C412

TABLE 2 AC CHARACTERISTICS
Symbol

Parameter

Min

tOW

Delay Time to Write

200

tOR

Delay Time to Read

200

Typ

tPW

Complete SCK Cycle

1.0

SCK High Pulse Duration

Crystal Frequency

7.3721

Max

Units

Conditions

ms
70
7.3728 7.3735

Duty Cycle

MHz

FIGURE 1. WAVEFORMS FOR WRITE AND READ CYCLES
a) Write Cycle

b) Re •• CyCI
-RD

C F

-+I t.- ....J !.-tP
"1
4

tPW

Ir-

;

IDR

tOR

0110 XXl Dol 01 1021 03 1X XXXX
LfUlJ

SCK

DTMF GENERATOR
Parameter

CRYSTAL FREQUENCY = 7372800 MHz±O%
Nominal Frequency

Allowable Error

Actual Error

Row 1

697Hz

±1%

+ 0.17%

Row 2

770Hz

±1%

-0.26%

Row 3

852Hz

±1%

+ 0.16%

Row 4

941 Hz

±1%

-0.47%

Column 1

1209 Hz

±1%

-0.74%

Column2

1336 Hz

±1%

-0.89%

Column 3

1477 Hz

±1%

-0.01%

550Hz

±20 Hz

-1.4 Hz

1800 Hz

±20 Hz

+ 7Hz

Guard Tones

459

VLSI TECHNOLOGY, INC.
VL7C412

DTMF GENERATOR

(Cant.)
Conditions

Parameter

Min

Typ

Max

Units

Second Harmonic Distortion

VCC= +5 V

-40

Row Output Level

VSS=-5 V

dBm

Column Output Level

TLCO = 1

dBm

550 Hz Guard Tone Level

TLC1 = 1

-3

dB (Note 2)

1800 Hz Guard Tone Level

Measured at TXOUT Pin

-6

dB (Note 2)

MODEM TRANSMIT SIGNALS

CRYSTAL FREQUENCY

Bell 103

Mode

=7.372800 MHz ±O%
Bell 212A I CCITT V.22

CCITTV.21

Nominal

Actual

2400 Hz

1200 Hz

1301.7 Hz

1300 Hz

1301.7 Hz

2096.9 Hz

2100 Hz

2096.9 Hz

Nominal

Actual

Nominal

Actual

Mark

2225 Hz

2226 Hz

1650 Hz

1649.4 Hz

Space

2025 Hz

2024.4 Hz

1850 Hz

1850.6 Hz

Mark

1270 Hz

1269.4 Hz

980 Hz

978.34 Hz

Space

1070 Hz

1070.4 Hz

1180 Hz

1181.53 Hz

Calling Tone

1300 Hz

Answer Tone

2100 Hz

Answer

Originate

RECEIVER
Parameter

Conditions

Min

Input Signal Range

At RXA 1 ( pin 9 )

-45

Intra - Character Bit Rate

At RXD ( pin 13 )

1170

Carrier Detect

At RXA 1 ( pin 9 )

-48

Carrier Detect Hysterisis

Typ

1200

Max

Units

dBm

1224

bps

-43

dBm
dB

Carrier Detect Delay

For 103, 212A and V.22

Carrier Detect Hold

For 103, 212A and V.22

Carrier Detect Delay

For V.21 mode

Carrier Detect Hold

For V.21 mode

460

VLSI TECHNOLOGY, INC.
VL7C412

TRANSMITTER
Parameter
Input Character Length

Start Bit + Data Bit + Stop Bit

At TXD (pin 14)

1170

M ... Character Length

2M+3

Intra - Character Bit Rate
Input Break Sequence Length

Typ

Min

Conditions

Max

1200

Units

bits

1212

bps
bits

Output Level Tolerance

±1

ABSOLUTE MAXIMUM RATINGS
Ambient Temperature
Under Bias:

-10°C to +80°C

Storage Temperature
Range:
-65°C to +140°C
Maximum Supply
Voltage:

those in the operational sections of this
specification is not implied and exposure to absoute maximum rating
conditions for extended periods may
effect device reliability.

VCC = +7.0 V

Input Voltage Range:
Anal. Pins; AGND -0.6 V to VCC+0.6 V
Digital Pins; DGND-O.6 V to VCC+0.6 V
Maximum Power
Dissipation @25°C:

500 mW

DC CHARACTERISTICS TA= O°C to 70° C unless otherwise specified
Symbol

Parameter

VCC

Positive Supply Voltage

ICC

Quiescent Current

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

Min
4.5

Typ
5.0

Max
5.5

Units
V
mA

2.0

Conditions

VCC

Digital Signal Pins: -RD, -WR, OliO,
SCK,TXCK1,TXD

0.8

Digital Signal Pins: -RD, -WR, OliO,
SCK, TXCK1, TXD

VOH

VOL

High Level Output Voltage

4.0

@IOH- 40 ~A (D SPins: D 110, CKOUT,

2.0

@IOH-500~

@IOL.160

Low Level Output Voltage

0.4

RXD, TXCKO, RXCK)

(D SPins: D 110, CKOUT,
RXD, TXCKO, RXCK)

VOM

Maximum Output Signal

3.0

Vp-p

TXOUT, RL-1200 n (TLC1-1, TLCO.. O)

VOM

Maximum Output Signal

1.0

Vp-p

Audio Out, RL... 50 kn

VIM

Maximum Input Signal

Vp-p

RXA1, RXA2

2.5

461

VLSI TECHNOLOGY, INC.

462

VLSI TECHNOLOGY, INC.
VL7C413
HIGH SPEED PARALLEL BUS MODEM CONTROLLER
WITH AUTOMATIC MODEM POWER DOWN CONTROL

FEATURES

DESCRIPTION

• Direct interface to VL7C412 singlechip, single-supply modems

• Replacement for Sierra SC11 037

The VL7C413 Parallel Bus Modem
Controller is specifically designed to
control the VL7C412 single-chip, 300/
1200 bit-per-second modem. Built with
an advanced two-micron CMOS
process, the VL7C413 provides a
highly cost effective solution for
interfacing a modem IC to a system
bus. When connected to the
VL7C412, with the addition of a data
access arrangement (DAA), the
VL7C413 implements a Hayes-type
smart modem for board-level, integralmodem applications. Because the
VL7C413 fully emulates the functionality of the VL82CSO UART and includes
data bus transceivers, it can be directly
interfaced to a computer's parallel data

PIN DIAGRAMS

BLOCK DIAGRAM

• Complete Hayes AT command set in
firmware
• Built-in UART
• Direct IBM PC bus interface
• IORDY pin for use on high-speed
buses
• Complete intelligent modem in two ICs
• Compatible with industry-standard
software
• Automatic power up/down control of
VL7C412

VL7C413
-OOST
-OIST
10ROY
KOV
-AI

-OOST
-DIST

VCC

-cs

INT

03
02
01
DO

TXO
RXO
GNO
IOROY -DOST

For specific high-volume applications,
the control program can be modified by
VLSI to include additional command
functions.

UART
TXO

10ROY

00- 07

ova

The VL7C413 automatically controls the
power up/down feature of the VL7C412
to maintain lowest possible system
power consumption.

-CS
AO-A2

A2
A1
AO
INT
07
06
05

ClK
-WR
-AD
SCK

bus (in particular to the bus of the IBM
PC, XT or AT). All of the popular communications software written for the PC
will work with the VL7C413/
VL7C412 chip set. In addition to
including the functionality of the
VL82CSO UART, the VL7C413 contains
an 8-bit microprocessor, 8K by 8 bits of
ROM and 128 by 8 bits of RAM.

RXO

~-1II""'1

.-._+-___

~-----I

-CS

-RI

O-i

INT

elK

-WR

-RO

SCK

0110

RXO

ORDER
Part
Number

1------.SCK
1------.- -RO
1------.-WR
H-----.- 0110

INFORMATION
Package

VL7C413-PC
Plastic DIP
VL7C413-QC
Plastic Leaded Chip Carrier (PLCC)
Note: Operating temperature range is O°C to +70°C.

KDV

463

OH -AI

VLSI TECHNOLOGY, INC.
VL7C413

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Description
The CPU can write data or control words into a selected register of the VL7C413 when
-DOST is low and the chip is selected. Data is latched on the rising edge of the signal.

-DOST
-DIST

The CPU can read data or status information from a selected register of the VL7C413
when -DIST is low and the chip is selected.

10RDY

This open-drain output will go low upon a write or read operation, and remain low until
internal data setup and hold times have been satisfied.

KDV

This output controls the operation of the data/voice relay. When low, the data/voice relay
is off and the phone line is connected to the phone set. During a data ca", the VL7C413
makes this output high to operate the data/voice relay, disconnecting the phone set from
the phone line. It may also be used to drive a relay for multi-line phone applications to
close the A and A 1 leads.

-RI

This output controls the operation of the hookswitch relay in the DAA. During a data ca",
this output is high. It operates the hookswitch relay which causes the phone line to be
seized. During rotary dialing, the VL7C413 pulses this output at a rate of 10 pulses per
second with appropriate Mark/Space ratio depending on 212A or ~;22 mode.

CLK

A 7.3728 MHz clock signal must be connected to this input. Norma"y, the CKOUT pin of
the VL7C412 modem is connected to this pin. A" internal timing is derived from this
clock. This clock must be adjusted to within 0.01%.

-WR

This pin is used to initiate writing of data to the VL7C412 modem. On power{Sp, it is an
input for a brief time in which the VL7C413 reads the carrier status switch connected to
this pin. If the switch is closed to ground through an 18 Kil resistor, the VL7C413 sets
the Received Line Signal Detect (RLSD) Bit in the Modem Status Register. If the switch
is open, the VL7C413 resets this bit and writes the actual status of the carrier detector
during a data call. If no switch is used, an internal pull-up sets the status during powerup to the default state (pu"-up to VCC) which is to follow the remote modem's carrier.

-RD

This pin is used to initiate reading of data from the VL7C412 modem. On power-up, this
pin is an input for a brief time in which the VL7C413 reads the DTR status switch connected to this pin. If this switch is open, the VL7C413 reacts to the status of the DTR bit
in the UART Modem Control Register. If the switch is closed to ground through 18 kil,
the VL7C413 ignores the state of the DTR bit. When the switch is open, writing a zero to
the DTR bit in the Modem Control Register forces the VL7C413 into the command state
and when on-line, causes it to hang up. If no switch is used, an internal pull-up to VCC
sets the status during power-up to the default state (to follow the DTR status).

SCK

The VL7C413 supplies a shift clock on this pin to the VL7C412 modem for reading or
writing data. On power-up, this pin is an input for a brief time in which the VL7C413
reads the Be"/CCITT select switch connected to this pin. If this switch is open, Be"
protocol is selected. If this switch is closed to ground through18 kil, CCITT V.22
protocol is selected. If no switch is used, an internal pull-up sets the status during
power-up to the default state (212A mode).

DIIO

The VL7C413 shifts data serially out of this pin to VL7C412 during a write operation and
shifts data serially into this pin during a read operation from the VL7C412. On power-up
this pin is an input for a brief time in which the VL7C413 reads the Make/Break ratio
select switch connected to this pin for selecting the pulse dialing standard. With the
switch open, the Bell standard 39% Make, 61% Break is selected. With the switch
closed to ground through 18 kil, the CCITT standard 33% Make, 67% Break is selected.
If no switch is used, an internal pull-up sets the status during power-up to the default
state (Be" standard).

464

VLSI TECHNOLOGY, INC.
VL7C413

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Description

TXD

This pin is a serial output pin. During a data call, after the connection is established, the
VL7C413 converts parallel data received from the computer bus and outputs it in a
serial, asynchronous format to the VL7C412 modem for modulation. At all other times
the VL7C413 holds this output in the Mark (high) condition.

RXD

Demodulated data from the VL7C412 modem is received on this pin during a data call.
A high level is considered Mark and a low level is Space. The VL7C413 converts the
serial data into a parallel data byte and stores it in the Receiver Buffer Register (RBR).
The Data Ready bit in the Line Status Register (LSR) is then set, and an appropriate
interrupt identification code is written in the Interrupt Identification Register (IIR) to signal
to the computer, the reception of a new data byte.

GND

Ground reference (0 V).

00-07

15-22

This is the 8 bit data bus comprising of three-state inpuVoutput lines. This bus provides
bidirectional communication between the VL7C413 and the CPU. Data control words
and status information are transferred via the DO - 07 data bus.

INT

This output goes high whenever anyone of the following interrupt types has an active
condition and is enabled via the IER: Receiver Line Status flag, Received Data Available, Transmitter Holding Register Empty, and Modem Status. It is reset low upon the
appropriate interrupt servicing. The INT pin is forced to a high impedence state when
the OUT2 bit of the M9dem Control Regiser (MCR) is low (power on state).

AO-A2

24-26

These three address inputs are used during read or write operation to select a UART
register in the VL7C413 as shown in Table 1. The Divisor Latch Access Bit (DLAB) must
be set high by the system software to access the bit rate divisor latches as shown in
Table 2.

-CS

The VL7C413 is selected when this input is low. When high, the VL7C413 forces the
Data bus lines into a high impedance state.

VCC

Positive supply (+5 V).

TABLE 1. VL7C413 UART REGISTERS
DLAB

RBR

Receiver Buffer Register (read only)

THR

Transmitter Holding Register (write only)

IER

Interrupt Enable Register

IIR

Interrupt Identification Register (read only)

Mnemonic

LCR

Line Control Register

MCR

Modem Control Register

LSR

Line Status Register

MSR

Modem Status (read only) Register

STR

Speed

DLL

Divisor Latch (LSB) (write only)

DLM

Divisor Latch (MSB) (write only)

X = "Don't Care"

0", Logic Low

1 '" Logic High

465

VLSI TECHNOLOGY, INC.
VL7C413

FIGURE 1. UART BLOCK DIAGRAM
INTERNAL
DATA BUS
DATA BUS
BUFFER

DO-07

1.
..r ,....1 .... .

RECEIVER
BUFFER
REGISTER

LINE
CONTROL
REGISTER

--I

.......
-.

........

--..J
--..
.-,

.......

-C S

-D 1ST

SELECT
AND
CONTROL
LOGIC

...

l...&.

DIVISOR
LATCH (MS)

~RXD

DIVISOR
LATCH (LS)

RECEIVER
SHIFT
REGISTER

RECEIVER
TIMING AND
CONTROL

•
..

BAUD
,
.. ,GENERATOR]

LINE
STATUS
REGISTER

..J
j ..

.....

......
.....
......

TRANSMITIER
TIMING AND
CONTROL

•

SPEED
REGISTER

-DO ST~

lOR OY~

~
~

TRANSMITIER
HOLDING
REGISTER

MODEM
CONTROL
REGISTER

MODEM
STATUS
REGISTER

INTERRUPT
ENABLE
REGISTER

INTERRUPT
10
REGISTER

466

........
..

TRANSMITIER
SHIFT
REGISTER

~TX D

--..
J

MODEM
CONTROL
LOGIC

........

.......

INTERRUPT
CONTROL
LOGIC

liiio..-

INT

VLSI TECHNOLOGY, INC.
VL7C413

TABLE 2. VL7C413 UART REGISTER FUNCTION SUMMARY
Register Bit Number

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

RBR

Data

THR

Data

IER

Receive
Data
Available
Interrupt
Enable

THRE
Interrupt
Enable

Receive
Line
Status
Interrupt
Enable

Modem
Status
Interrupt
Enable

fiR

Olf
Interrupt
Pending

Interrupt
ID BitO

Interrupt
ID Bit 1

LCR

0-7 Bit
Data
1 - 8 Bit
Data

0-1 Stop
Bit
1 .. 2 Stop
Bits

1 sa Parity
Enable

1 - Even
Parity

1 .. Stick
Parity

1 - Set
Break

DLAB

MCR

Data
Terminal
Ready

Request
to Send

OUT1

OUT2
O-INT
Output
to HI-Z

No
Function

LSR

Data
Ready

Overrun
Error

Parity
Error

Framing
Error

Break
Interrupt

THRE

TSRE

MSR

Trailing
Edge Ring

Delta
RLSD

1 (CTS)

1 (DSR)

RING

RLSD

DLM

Data

DLL

Data

STR

Data

467

VLSI TECHNOLOGY, INC.
VL7C413

TABLE 3. VL7C413 SOFTWARE REGISTERS
Register

Range/Units

Description

0-255 Rings

Ring to answer telephone on

0-255 Rings

Number of rings

0-127 ASCII

Escape code character

0-127 ASCII

Character recognized as carriage return

13 (CR)"

0-127 ASCII

Character recognized as line feedback

10 (LF)

0-32, 127 ASCII

Character recognized as back space

8 (8S)

2-255 sec.

Wait time for dial tone

1-255 sec.

Wait time for carrier

0-255 sec.

Pause time (caused by comma)

1-255 1/10 sec.

Carrier detect response time

S10

1-255 1/10 sec.

Delay between loss of carrier and hang up

S11

50-255 millisec.

Duration and spacing of Touch-Tones

S12

20-255 1/50 sec.

Escape code guard time

S13

bit mapped

UART status register

S14

bit mapped

Option register

S15

bit mapped

Flag register

S16

0,1,2,4

Test modes

Default

43 (+)

2
30

468

VLSI TECHNOLOGY, INC
VL7C413

TABLE 4. COMMAND SUMMARY
PREFIX, REPEAT AND ESCAPE COMMANDS
Command

Description (Notes 1 & 2)

Attention prefix: precedes all command lines except + + + (escape) and AI(repeat) commands

Repeat last command line (AI is not followed by carriage return)

+++

Escape code: go from on-line state to command state (one second pause before and after escape
code entry; ; + + + is not followed by carriage return)

DIALING COMMANDS
Command

Description (Notes 1 & 2)

Command

Description (Notes 1 & 2)

Dial

Wait for 1/8 second

Pulse·

Wait for silence

Touch-Tone

Wait for second dial tone

Pause

;

Return to command state after dialing

Flash

Reverse mode (to call originate-only modem)

OTHER COMMANDS
Commands

Description (Notes 1 & 2)

Commands

Description (Notes 1 & 2)

Answer call without waiting for ring

Speaker on until carrier detected·

BlBO

CCID V.22 mode (Note 3)

Speaker always on

Bell 103 and 212A mode·

Go to on-line state

CICO

Transmit carrier off

Remote digitalloopback off·

Carrier on·

Remote digitalloopback request

ElEO

Characters not echoed

0/00

Result codes displayed·

Characters echoed·

Result codes not displayed

FIFO

Half duplex

Sr?

Requests current value of register r

Full duplex·

Sr= n

Sets register r to value of n

HlHO

On hook (hang up)

VNO

Digit result codes

Off hook; line and auxiliary relay

Word result codes·

Off hook; line relay only

XIX 0

Compatible with Hayes-type 300 modems·

1110

Request product ID code (130)

Result code CONNECT 1200 enabled

Firmware revision number

Enables dial tone detection

Test internal memory

Enables busy signal detection

UL1

Low speaker volume

Enables dial tone and busy signal detection

Medium speaker volume

YIYO

Long space disconnect disabled·

High speaker volume

Long space disconnect enabled

MlMO

Speaker always off

Software reset: restores all default settings

Notes:
1. Default modes are indicated by •.
2. Commands entered with null parameters assume 0 - X is the same as XO.
3. When the ATB command is used in the answer mode, the VL7C412 is placed in either the V.21 or the V.22 mode, depending on the response from the remote modem. In the originate mode, the VL7C413 will sense if the baud rate is set at 300 or
1200 bits per second and will adjust the VL7C412 accordingly.

469

VLSI TECHNOLOGY, INC
VL7C413

TABLE~RESULTCODES
Digit Code

Word Code

Description

Command executed

Connect

Connected at 300 or 1200 bps
Connected at 300 bps, if result of X1, X2, X3, or X4 command

Ring

Ringing signal detected (Note)

No Carrier

Carrier signal not detected or lost

Error

Illegal command
Error in command line
Command line exceeds buffer (40 characters, including punctuation)
Invalid character format at 1200 bps

Connect 1200

Connected at 1200 bps. Results from X1, X2, X3, or X4 commands only

No Dialtone

Dialtone not detected and subsequent commands not processed
Results from X2 or X4 commands only

Busy

Busy signal detected and subsequent commands not processed
Results from X3 or X4 commands only

No Answer

Silence not detected and subsequent commands not processed
Results from @ command only

Note: When the VL7C413 detects a ringing on the telephone line, it sends a RING result code. However, the VL7C413
will answer the call only if it is in auto-answer mode or is given an A command.

TABLE 6. RESET CONTROL OF REGISTERS AND PINOUT SIGNALS
Register/Signal

Reset State

Reset Control

Receiver Buffer Register

First word received

Transmitter Holding Register

Writing into the Transmitter Holding Register

Data

Interrupt Enable Register

Power on reset

All bits low

Interrupt Identification Register

Power on reset

Bit 0 high; bits 1-7 low

Line Control Register

Writing into the LCR

Data

MODEM Control Register

Power on reset

All bits low

Line Status Register

Power on reset

Bits 0-4, 7 low; bits 5-6 high

Modem Status Register

Power on reset

Bits 0-3, 6-7 low; bits 4-5 high

Power on reset

1200 bps

TXD

Master reset

High

INT

Power on reset

Low (high impedence)

. Divisor Latch (high order bits)

Data

470

VLSI TECHNOLOGY, INC.
VL7C413

UART REGISTERS
Line· Control Registers
This register controls the format of the
asynchronous data communications.
Bit 0 and 1: Bit 1 is always high. Bit 0
specifies the number of bits in each
transmitted or received serial character.
The encoding of bit 0 is as follows:
Bit 1
1
1

Bit 0
0
1

Word Length
7 Bits
a Bits

Programmable Baud Rate Generator
The VL7C413's Baud Rate Generator
can be programmed for one of six baud
rates. The desired speed is selected by
writing into the Divisor Latch (DLM) .
On reset, the rate will be 1200 baud.
DLM (Hex Code)
00
01
03
04
06
09

Baud Rate
1200
300
150
110
75
50

471

whenever the received data input is
held in the Spacing (Logic 0) state for
longer than a full word transmission
time - the total time of Start bit + data
bits + Parity + Stop bits.
Bit 5: This bit is the Transmitter Holding
Register Empty (THRE) indicator. Bit 5
indicates that the VL7C215 is ready to
accept a new character for transmission. In addition, this bit causes the
VL7C215 to issue an interrupt to the
CPU when the Transmit Holding
Register Empty enable is set high. The
THRE bit is set to a logic 0 concurrently
with the loading of the Transmitter
Holding Register by the CPU.
Bit 6: This bit is the Transmitter Shift
Register Empty (TSRE) indicator. Bit 6
is set to a logic 1 whenever the Transmitter Shift Register is idle. It is reset to
logic 0 upon a data transfer from the
Transmitter Holding Register to the
Transmitter Shift Register.
Bit 7: This bit is permanently set to
logic o.
Bits 1 through 4 are the error conditions
that produce a Receiver Line Status
interrupt whenever any at the corresponding conditions are detected.
Interruptldentlflcatlon Register
The VL7C413 has an on-chip interrupt
capability that allows for complete
flexibility in interfacing to all popular
microprocessors. To provide minimum
software overhead during data character transfers, the VL7C413 prioritizes
interrupts into four levels. The four
levels of interrupt conditions are as
follows: Receiver Line Status (priority
1); Received Data Ready (priority 2);
Transmitter Holding Register Empty
(priority 3); and MODEM Status (priority

4).
Information indicating that a prioritized
interrupt is pending the source of that
interrupt are stored in the Interrupt
Identification Register (refer to Table 7).
The Interrupt Identification Register
(IIR). when addressed during chipselect time. freezes the highest priority
interrupt pending and no other interrupts are acknowledged until the
particular interrupt is serviced by the
CPU. The contents of the IIR are
indicated in Table 2 and are described
below.

VLSI TECHNOLOGY, INC.
VL7C413

7.
Bits 3 through 7: These five bits of the
IIR are always logic

Interrupt Enable Register
This 8-bit register enables the four
interrupt sources of the VL7C413 to
separately activate the Interrupt (INT)
output signal. It is possible to totally
disable the interrupt system by resetting
bits 0 through 3 of the Interrupt Enable
Register. Similarly, by setting the
appropriate bits of this register and the
active (high) INT output from the chip.
All other system functions operate in
their normal manner, including the
setting of the Line Status and MODEM
Status Register. The contents of the
Interrupt Enable Register are indicated
in Table 2 and are described below.

Bit 2: This bit enables the Receiver
Line Status Interrupt when set to logic

1.
Bit 3: This bit enables the MODEM
Status Interrupt when set to logic 1.
Bit 4 through 7: These four bits are
always logic O.

MODEM Control Register
This 8-bit register controls the interface
with the MODEM. The contents of the
MODEM Control Register are indicated
in Table 2 and are described below.
Bit 0: This bit controls Data Terminal
Ready (DTR) signal. If the external
switch on the -RD pin is set to VCC
through an 18 kn resistor, setting the
DTR low will force the VL7C413 into the
command state and if on line, it will
hang up.
Bit 1: This bit controls the Request to
Send (RTS) signal. This signal is not
used by the VL7C413.
Bit 2: This bit controls the Output 1
(OUT1) signal. This signal is not used
by the VL7C413.
Bit 3: This bit controls the Output 2
(OUT2) signal. When OUT2 is a 0, the
interrupt output is in high impedence
state.
Bit 4: Not used.

Bit 0: This bit enables the Received
Data Available Interrupt when set to
logic 1.

Bits 5 through 7: These bits are
permanently set to logic O.

Bit 1: This bit enables the transmitter
Holding Register Empty Interrupt when
set to a logic 1.

MODEM Status Register
This 8-bit register provides the current
state of the control lines from the

472

MODEM (or peripheral device) to the
CPU. In addition to this current-state
information, two bits of the MODEM
Status Register provide change
information. These bits are set to a
logic 1 whenever a control input from
the MODEM changes state. They are
reset to logic 0 whenever the CPU
reads the MODEM Status Register.
The contents of the MODEM Status
Register are indicated in Table 2 and
are described below.
Bits 0 and 1: These bits are always O.
Bit 2: This bit is the Trailing Edge of
Ring Indicator (TERI) detector. Bit 2
indicates that the -RI input to the chip
has changed from On (logic 1) to an Off
(logic 0) condition.
Bit 3: This bit is the Delta Received
Line Signal Detector (DRLSD) indicator.
Bit 3 indicates that the carrier detector
has changed state.
Bit 4: This bit is always 1.
Bit 5: This bit is always 1.
Bit 6: This bit is the complement of the
Ring Indicator (-RI) input.
Bit 7: This bit is the Received Line
Signal Detect (RLSD) signal.
Whenever bit 2 is set to logic 1, or bit 3
changes state, a MODEM Status
Interrupt is generated if enabled.

VLSI TECHNOLOGY, INC.
VL7C413

TABLE 7. INTERRUPT CONTROL FUNCTIONS
Interrupt
Identification
Register

Interrupt Set and Reset Functions

Bit 2

Bit 1

Bit 0

Priority
Level

Interrupt Flag

Interrupt Source

Interrupt
Reset Control

None

Highest

Receiver
Line Status

Overrun Error or
Parity Error or
Framing Error or
Break Interrupt

Reading the Line
Status Register

Second

Received Data
Available

Reading the Receiver
Buffer Register

Third

Transmitter Holding
Register Empty

Reading the IIR (if source of
interrupt) or Writing into the
Transmitter Holding Register

Fourth

MODEM Status

Ring Indicator or
Received Line
Signal Detect

Reading the MODEM
Status Register

473

VLSI TECHNOLOGY, INC
VL7C413

FIGURE 2. ADDRESS DECODER CIRCUIT

PC BUS

NAME

A11

-AEN

A2B

A27

. A~

A26

hS- - - - - - C S _ _ _ _---, 27

-CS

A25
A24

A22

5
6

VL7C413

A23

1.
--------~L~-----~~~-------__e'~~COO~M~1
74LS04

825

--------------------------_e' COM1
IRQ3 ----------------..e' CO-M;

814

-lOR

813

-lOW - - - - - - - - - - O O S T - - - - - - - - - - - ,

824

IRQ4

-OIST - - - - - - - - - - - - - - - - - , 2

INT
-OIST
-OOST

A29

A30

A31

A10

IOROY

474

VLSI TECHNOLOGY, INC.
VL7C413

AC CHARACTERISTICS:
Symbol

=0 TO 70°C, VCC =5 V ±10%

Parameter

Min

Max

Units

Conditions

tDlW

-DIST Strobe Width

300

1TTL Load

tRC

Read Cycle Delay

300

1TTL Load

Read Cycle = tDlW + tRC + 20 ns

620

1TTL Load

tDDD

Delay from -DIST to Data

tHZ

-DIST to Floating Data Delay

tDOW

300

1TTL Load

-DOST Strobe Width

300

1TTL Load

tWC

Write Cycle Delay

300

1TTL Load

Write Cycle = tDOW + tWC + 20 ns

620

1TTL Load

tDS

Data Setup Time

1TTL Load

tDH

Data Hold Time

1TTL Load

tDlC

-DIST Delay from Select

150

1TTL Load

tDOC

-DOST Delay from Select

150

1TTL Load

tACR

Address and Chip Select Hold Time from -DIST

1TTL Load

tACW

Address and Chip Select Hold Time from -DOST

1TTL Load

tDlOR

-DIST/-DOST to IORDY Delay

1TTL Load

Ils

100 pF Load

tWIOR
Receiver
tRINT

TBD

IORDY Pulse Width

TBD

Delay from -DIST (Read RBR) to Reset Interrupt

Transmitter
tHR

Delay from -DOST (Write THR) to Reset Interrupt

Ils

tlRS

Delay from Initial INTR Reset to Transmit Start

Baud Cycle
Baud Cycle

tSI

Delay from Initial Write to Interrupt

tSS

Delay from Stop to Next Start

Ils

tSTI

Delay from Stop to Interrupt (THRE)

Baud Cycle

tlR

Delay from -DIST (Read IIR) to Reset Interrupt (THRE)

Ils

Note: A TTL load is 40 IlA sourced and -1.6 mA sinked current.

475

100 pF Load

VLSI TECHNOLOGY, INC.
VL7C413

FIGURE 3. READ CYCLE TIMING

~I~C!

X
X'------~.___---__i-~--lo..--

-CS_

VALID

AO, A1, A2

I~.-IDIC

---t

-OIST

.ACTIVE

---------~---_t_--~ .---~!

-DOST

--r-__

OATA _ _ _ _ _ _ _ _ _

00-07

t_O_IO_R_~
___

_______

IORDY

' -_ _

I+- tWIOR~1f

FIGURE 4. WRITE CYCLE TIMING

~I ~cw

-cs----,.

X-----=.;------i----1.~==
VALID

AO, A1, A2

tDOC

ACTIVE

==---~.---_t-----:- wc

----PI

-OOST

ACTIVE
OR

-OIST

OATA _ _ _ _ _ _ _ _ _ _r-_~
DO-D7

'-_____
VALID DATA

tD_IO_R_t
IORDY _ _ _ _ _ _ _ _ _ _ _ _

476

tWIORj

ACTiVE

VLSI TECHNOLOGY, INC'
VL7C413

FIGURE 5. RECEIVER TIMING
RXD (RECEIVER \
INPUT DATA)

;---<

2
\ START ~ 2

~STARTr

DATA

SAMPLE ClK

-11

JH-L

INTERRUPT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~\tRINT ~

-DIST _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
(READ REC DATA
BUFFER)

FIGURE 6. TRANSMITTER TIMING
TXD

START

SERIALOUT - - - - - . , \

INTERRUPT
(THRE)

-DOST
(WRTHR)

~tlRS~
~I

-J~

PARITY

/---D-A-TA--)()<'B

~It~

START
\

/,...------

=1 tSS~11=
\
I ---ILl
j j:;:=
tSTI

tHR

-DIST _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _____.
(RD IIR)

477

VLSI TECHNOLOGY, INC.
VL7C413

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

O°C to +70°C

Storage Temperature -65°C to + 150°C
Supply Voltage to
Ground Potential
Applied Input
Voltage

+6 V

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only, functional
operation of this device at these or any
other conditions above those indicated

in this data sheet is not implied. Exposure to absolute maximum rating
conditions for extended periods may
affect device reliability.

-0.6 V to VCC +0.6 V

Power Dissipation

500 mW

DC CHARACTERISTICS:

= 0 to +70 °C, VCC = 5 V ±10%

Symbol

Parameter

Min

Typ

Max

VCC

Positive Supply Voltage

4.5

5.0

5.5

ICC

Operating Current

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10.0

Units

rnA

2.0
0.8

Conditions

V
@VCC=5V

All pins except -RI

VT+

Positive Hysterisis Threshold

2.5

-RI pin

VT-

Negative Hysterisis Threshold

1.8

-RI pin

VCC-1.0

Digital signal pins DO to D7
and INT @ 10H = -6 rnA

VCC-1.0

All other output or 1/0 pins
@ 10H = -2 rnA

0.4

Digital signal pins DO to D7
and INT @ 10L = 6 rnA

0.4

All other output or 1/0 pins
@IOL=2mA

VOH

VOL

High Level Output Voltage

Low Level Output Voltage

Leakage Current (Note)

FCLK

Clock Frequency

Note:

±1.0
7.3721

7.3728

IlA
7.3735

MHz

This applies to all pins except TEST, which has an internal pull-down -WR, -RD, SCK, DIIO and switch input pins
which have internal pull-ups.

478

VLSI TECHNOLOGY, INC.
VL7C413

FIGURE 7. INTEGRAL SMART MODEM CONFIGURATION FOR PC BUS APPLICATIONS
COMPUTER
PARAllEL
BUS

DO-D7

AO
A1
A2

.....

.......

10RDY

.-....
-lOR

.....

J.RQ3

....

.........IRQ4
A3-A9
~

~r--v

DO-D7

-RI

.......

RXD
-DOST

........

......

TXD

DI/O ....
.....

.......

....
....
....
...

-RD
-WR

ClK

.... ..

"""...... >-c

~-c>

:>-c :>-c :>-c:>
:>-c:;:><:>-c:>

OPTIONAL
SWITCHES

RXA1

RXD
TXD

DI/O

RXA2

SCK

TXOUT

-RD
-WR
ClKOUT

AUDIO
OUT

XTAl1

XTAL2

~~
-c>

--L

i---4~
f---

SPEAKER

7.3728
MHz

UJ)

479

PHONE
LINE

SCK

INT

-0
DAA

.........
VL7C412
MODEM

-DIST

~ -CS

ADDRESS
DECODER
See
Figure 2

.....

VL7C413 OH
CONTROLLER
A1
KDV
AO

10RDY

......
....

-lOW
-AEN

=!>
....
..

HI~
I-

.,-L

-'--

VLSI TECHNOLOGY, INC.

480

VLSI TECHNOLOGY. INC.
VL7C414
STAND-ALONE MODEM INTERFACE CONTROLLER
WITH AUTOMATIC MODEM POWER DOWN CONTROL

FEATURES

DESCRIPTION

• Direct interface to VL7C412A single
chip single-supply modems

The VL7C414 Stand-Alone Modem
Interface Controller is specifically
designed to control the VL7C412A
single-chip, 300/1200 bit-per-second
modem. Built with an advanced twomicron CMOS process, the VL7C414
provides a highly cost effective
solution for interfacing a modem IC to
a computer's RS232C port. When
connected to the VL7C412A, with the
addition of a data access arrangement
(DAA), the VL7C414 implements a
Hayes-type smart modem for standalone modem applications. A" of the
popular communications software
written for the IBM PC wi" work with
the VL7C414/vL7C412A chip set. The

• Complete Hayes AT command set in
firmware
• BUilt-in UART for RS232C interface
• Two-micron CMOS process
• 28-pin DIP or PLCC package
• Complete intelligent modem in two ICs
• Compatible with industry-standard
software
• Reduces board space and component
count requirements
• Low power consumption

VL7C414 contains an 8-bit microprocessor, 8K by 8 bits of ROM and 128 by 8
bits of RAM. In order to support the
stand-alone functionality of the device,
an B-bit switch input port allows immediate user access and manual control of
the system. Either Be" 103 or cClrr
V.22 may be selected in this manner.
The VL7C414 automatically controls the
power up/down feature of the VL 7C412
to maintain lowest possible system
power consumption.
For specific high volume applications,
the control program can be modified by
VLSI Technology, Inc. to include
additional commands and functions.

• Replacement for Sierra SC11 028

PIN DIAGRAMS

BLOCK DIAGRAM

VL7C414
N.C.
N.C.
TEST
KoV/-KoV

UART

VCC

-oTR
-CD

-AA

-AI

-HS
N.C.
MSSEl

OHl-OH
ClK
-WR

212N-V.22

-AD

-CMo EN

SCK

-AAoIS

0110

ECHO EN
-RES EN
WORD

TXO
RXo
GNo

-PS
N.C.

-oTR

-AA

-RI

-HS

OHl-OH

N.C.

ClK

MS SEl

-WR

212N-V.22

-RD

-CMD EN

SCK

-MOIS

OliO

AXO

-Ps -RES EN

-PS

ORDER INFORMATION
Part
Number
VL7C414-PC
VL7C414-0C

WORD
-RES EN

ECHO EN
-AADIS

Package
Plastic DIP
Plastic Leaded Chip Carrier (PLCC)

-eMDEN

212N-V.22
MS SEL

Note: Operating temperature range is O°C to +70°C.

481

t - - - - + SCK
t - - - - + -RD
t - - - - + -WR
1 4 - - - + 0110

VLSI TECHNOLOGY, INC.
VL7C414

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

N.C.

Signal
Description
No connection

N.C.

No connection

TEST

When the test input is high, the VL7C414 enters a test mode (used for factory testing
only). For normal operation, this pin can be left open or connected to ground.

KDV/-KDV

This output controls the operation of the data/voice relay. The polarity of this output is
selected by -PS pin. If -PS is connected to ground, this output is active high, i.e., it is
low when modem is on hook, causing the data/voice relay to be off and the phone line is
connected to the phone set. During a data call, this output goes high to operate the
data/voice relay, disconnecting the phone set from the phone line. It may also be used
to drive a relay for multi-line phone applications to close the A and A 1 leads. If -PS pin
is left open or connected to VCC, this output is active low, Le., it is high when the modem
is on hook and low when modem makes a data call.

-RI

OH/-OH

This output controls the operation of the hookswitch relay in the DAA. The polarity of this
output is selected by -PS pin. H-PS pin is connected to ground, this output is active
high, i.e., it is low when the modem is on hook. During a data call, it goes high to
operate the hookswitch relay and seize the phone line. During rotary dialing, the
VL7C414 pulses this output at a rate of 10 pulses per second with appropriate Mark!
Space ratio depending on 212A or V.22 mode. If -PS pin is left open or connected to
VCC, this output is active low, Le., it is high when the modem is on hook and low during
data call.

CLK

A 7.3728 MHz clock signal must be connected to this input. Normally, the CKOUT pin of
the VL7C412A modem is connected to this pin. All internal timing is derived from this
clock.

-WR

This pin is used to initiate writing of data to the VL7C412A modem.

-RD

This pin is used to initiate reading of data from the VL7C412A modem.

SCK

The VL7C414 supplies a shift clock on this pin to the VL7C412A modem for reading or
writing data.

0110

The VL7C414 shifts data serially out of this pin to VL7C412A during a write operation
and shifts data serially into this pin during a read operation from the VL7C412A.

TXD

The VL7C414 outputs serial data in asynchronous start/stop format at the data rate
selected by the terminal. This data is either echo of commands received from the
terminal or result codes generated by the controller during processing of the commands.
This output is normally high and should be "AND"ed with the RXD output of the
VL7C412A to form RXD data to the terminal.

RXD

The VL7C414 receives command data from the terminal on this pirt. The UART in the
controller connects the serial asynchronous start/stop data into a parallel byte for
processing by the controller.

GND

Ground reference (0 V).

-PS

This input controls the polarity of KDV and OH outputs. When left open or connected to
VCC, it forces the KDV and OH outputs to be active low. Hthis input is connected to
ground, KDV and OH outputs are active high.

WORD

When the input is open or connected to VCC, the VL7C414 sends result codes as words.
When this input is low, result codes are sent as digits. This setting can also be changed
by entering the V command.

482

VLSI TECHNOLOGY, INC.
VL7C414

SIGNAL DESCRIPTIONS

(Cont.)

Signal
Name

Pin
Number

Signal
Description

-RES EN

When this input is low, the VL7C414 sends result codes. When this input is high or left
open, commands received from the terminal are performed but result codes are not sent.
This setting can also be changed by entering the Q command.

ECHO EN

When this input is high or left open, the VL7C414 echoes characters received from the
terminal in the command state. When this input is low, the VL7C414 will not echo characters unless it is set for half duplex and it is on line. This setting can also be changed
by entering the E command.

-AADIS

When this input is low, the VL7C414 will not answer incoming calls. When this input is
high or left open, the VL7C414 automatically answers incoming calls on the first ring.
This function can also be enabledldisabled by writing to the SO register.

-CMD EN

When this input is low, the VL7C414 recognizes command sent to it. For some applications such as unattended answering operation it is better to disable this function by
leaving this input open or connecting it to VCC.

212A1-V.22

When this input is open or connected to VCC, the VL7C414 supports Bell 103 and 212A
modes. When this input is low, the VL7C414 supports the cCln V.22 and V.21 modes.
This setting can also be changed by entering the B command.

MSSEL

When this input is open or connected to VCC, the Mark/Space ratio is U.S. standard, 401
60 Make/Break. When it is low, the Mark/Space ratio is European standard, 33/67 Makel
Break.

N.C.

No connection

-HS

-AA

This output is low when the VL7C414 is set for auto-answer mode, either by switch input
-AA DIS (pin 19) or register SO. The output goes high during each ring. If the device is
not set to answer the phone (pin 19 is low or SO .. 0), this output goes low each time the
phone rings. A light emitting diode through a 330 n resistor can be directly connected to
this output.

-CD

This output goes low when the VL7C414 detects a carrier signal from the remote
modem. If the connection is broken or never established, it remains high. A light
emitting diode can be directly connected to this output through a 330 n resistor.

-DTR

When this input is low, the VL7C414 executes data call commands. If during a data call,
this input goes high, the VL7C414 terminates the data call, hangs up the phone line and
returns to command state.

VCC

Positive supply (+5 V).

483

VLSI TECHNOLOGY, INC.
VL7C414

TABLE 1. VL7C414 SOFTWARE REGISTERS
RegIster

Range/UnIts

0-255 Rings

Ring to answer telephone on

0-255 Rings

Number of rings

0-127 A5CII

Escape code character •

0-127 A5CII

Character recognized as carriage return

13 (CR)

0-127 A5CII

Character recognized as line feedback

10 (LF)

0-32, 127 A5CII

Character recognized as back space

8 (85)

2-255 sec.

Wait time for dial tone

1-255 sec.

Wait time for carrier

0-255 sec.

Pause time (caused by comma)

1-255 1/10 sec.

Carrier detect response time

510

1-255 1/10 sec.

Delay between loss of carrier and hang up

DescrIption

Default

43 (+)

2
30
2

511

50-255 millisec.

Duration and spacing of Touch-Tones

512

20-255 1/50 sec.

Escape code guard time

513

bit mapped

UART status register

514

bit mapped

Option register

515

bit mapped

Flag register

516

0,1,2,4

Test modes

484

VLSI TECHNOLOGY, INC.
VL7C414

TABLE 2. COMMAND SUMMARY
PREFIX, REPEAT AND ESCAPE COMMANDS
Command

Description (Notes 1 & 2)

Attention prefix: precedes all command lines except + + + (escape) and N(repeat) commands

Repeat last command line (N is not followed by carriage return)

+++

Escape code: go from on-line state to command state (one second pause before and after escape
code entry; ; + + + is not followed by carriage return)

DIALING COMMANDS
Description (Notes 1 & 2)

Command

Description (Notes 1 & 2)

Dial

Wait for 1/8 second

Pulse"

Wait for silence

Command

Touch-Tone

Wait for second dial tone

Pause

;

Return to command state after dialing

Flash

Reverse mode (to call originate-only modem)

OTHER COMMANDS
Commands

Description (Notes 1 & 2)

Commands

Description (Notes 1 & 2)

Answer call without waiting for ring

Speaker on until carrier detected·

BIBO

CCITT V.22 mode (Note 3)

Bell 103 and 212A mode"

CICO

Transmit carrier off

Remote digital loopback off*

Carrier on·

Remote digital loopback request

ElEO

Characters not echoed

0/00

Result codes displayed"

Speaker always on
"

Go to on-line state

Characters echoed·

Result codes not displayed

FIFO

Halt duplex

Sr?

Requests current value of register r

Full duplex·

Sr= n

Sets register r to value of n

HIHO

On hook (hang up)

VNO

Digit result codes

Off hook; line and auxiliary relay

Word result codes·

Off hook; line relay only

X/XO

Compatible with Hayes-type 300 modems·

1110

Request product ID code (130)

Result code CONNECT 1200 enabled

Firmware revision number

Enables dial tone detection

Enables busy signal detection

. Test internal memory

UL1

Low speaker volume

Enables dial tone and busy signal detection

Medium speaker volume

YIYO

Long space disconnect disabled·

High speaker volume

Long space disconnect enabled

M/MO

Speaker always off

Software reset: restores all default settings

Notes: 1. Default modes are indicated by •.
2. Commands entered with null parameters assume 0 - X is the same as XO.
3. When the ATB command is used in the answer mode, the VL7C412A is placed in either the V.21 or the V.22 mode,
depending on the response from the remote modem. In the originate mode, the VL7C414 will sense if the baud rate is
set at 300 or 1200 bits per second and will adjust the VL7C412A accordingly.

485

VLSI TECHNOLOGY, INC.
VL7C414

TABLE 3. RESULT CODES
Digit Code

Word Code

Command executed

Connect

Connected at 300 or 1200 bps
Connected at 300 bps, if result of X1, X2, X3, or X4 command

Ring

Ringing signal detected (Note)

No Carrier

Carrier signal not detected or lost

Error

Illegal command
Error in command line
Command line exceeds buffer (40 characters, including punctuation)
Invalid character format at 1200 bps

Connect 1200

Connected at 1200 bps. Results from X1, X2, X3, or X4 commands only

No Dialtone

Dialtone not detected and subsequent commands not processed
Results from X2 or X4 commands only

Busy

Busy signal detected and subsequent commands not processed
Results from X3 or X4 commands only

No Answer

Silence not detected and subsequent commands not processed
Results from @ command only

Description

Note: When the VL7C414 detects a ringing on the telephone line, it sends a RING result code. However, the VL7C414
will answer the call only if it is in auto-answer mode or is given an A command.

486

VLSI TECHNOLOGY, INC.
VL7C414

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

O°Cto +70°C

Storage Temperature

-65°C to + 150°C

Supply Voltage to
Ground Potential
Applied Input
Voltage

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only, functional
operation of this device at these or any
other conditions above those indicated

in this data sheet is not implied. Exposure to absolute maximum rating
conditions for extended periods may
affect device reliability.

+6V
-0.6 V to VCC + 6 V

Power Dissipation

500 mW

DC CHARACTERISTICS: TA =0 to +70 °c, vee = 5 V ±100/0
Symbol

Parameter

VCC

Positive Supply Voltage

ICC

Operating Current

VIH

High Level Input Voltage

Min
4.5

Typ

Max

5.0

5.5

Units
V
mA

10.0

2.0

Conditions

@VCC = 5 V, outputs unloaded
All pins except -RI

VIL

Low Level Input Voltage

All pins except -RI

VT+

Positive Hysterisis Threshold

2.5

-Alpin

VT-

Negative Hysterisis Threshold

1.8

-Alpin

VOH

High Level Output Voltage

@IOH=-2 mA

VOL

Low Level Output Voltage

@IOL=2mA

Leakage Current (Note)

FCLK

Clock Frequency

0.8

VCC -1.0
0.4

±1.0
7.3721

7.3728

7.3735

MHz

Note: This applies to all pins except TEST, which has an internal pull-down -WR, -RD, SCK, OlIO, and switch input pins
15 thru 21 which have internal pull-ups.

487

VLSI TECHNOLOGY, INC
VL7C414

FIGURE 1. 212AN.22 STAND-ALONE INTELUGENT MODEM USING THE VL7C412A MODEM IC
AND THE VL7C414

+5V

B
3900

3900

0
E

3900

3900
HS
3900
OH

+5V

J
28

AA
16

(WORD RES.)
(RES. EN)

(ECHO ON)

(AAOIS)

(CMNOEN)

20
21

(212A)

(PWR UP RES)

3
14

26
CD

VL7C414
CONTROLLER
SWI.1

FIT
SWI.2
OH
SWI.3
SWI.4
SWI.5

D'fR
TXO
0110

SWI.6
SWI.7
TEST

SCK
RD

WR
ClK

GNO

5
6
24

27
12
11
10
9
8
7

L
M
N

P
Q

KOV
23
4

T
Note: Schematics are for illustration purposes only. Operational systems may require modifications.

488

VLSI TECHNOLOGY, INC.
VL7C414

AGURE 1. 212A1V.22 STAND-ALONE INTELLIGENT MODEM USING TIiE VL7C412A MODEM IC
AND TIiE VL7C414 (Cont.)

A
B
C

rr-._

4049 2.F

50 kn
_ _ _- -

0.5W
SPKR

RXA1

LINE

VL7C412A
MODEM

K
14
13

L
M
N

p
Q

15
16
17
18

RXA2
TXD TXOUT
AGND
RXD

TEL.
SET

DIIO
SCK
RD

+5V

1N914
7.3728Mhz

4049

489

VLSI TECHNOLOGY, INC.

490

VLSI TECHNOLOGY, INC
VL80C75
T1 INTERFACE

FEATURES

DESCRIPTION

• Supports T1, T1 C, and CEPT data
rates

The VLSOC75 is a general purpose PCM
Line Interface circuit. It is designed to
provide a bipolar interface according to
T1 (1.544M bps), T1 C (3.152M bps), or
CEPT (2.04SM bps) specifications. It is
capable of sending (encoding) and
receiving (decoding) AMI, BSZS or HDB3
data formats.

• AMI, BSZS, HDB3 format
• Meets AT&T Technical Advisory #34
for DSX1 and DSX1 C interface
standards, publication 43S02
standard for jitter tolerance, and jitter
standard for digital channel bank
• Meets CCITT recommendation G.703
for 1.544M bps and 2.04SM bps
• Input frequency memory
• Jitter smoothing FIFO
• Loopback and data path configurable

The incorporation of on-chip voltage
comparators and adaptive reference
levels allows direct interface to the
analog line signal. Sensitivity is optimized by monitoring the incoming bipolar
signal.

• Low power CMOS technology

An injection locking divider permits clock
recovery from the incoming serial data
stream. A 32-bit long FIFO (elastic
buffer) may be used in either the
decoder or the encoder path to smooth
clock jitter. A DC output signal is provided to facilitate the control of an
external VCO.

PIN DIAGRAM

BLOCK DIAGRAM

• Bipolar violation detection & flagging
• AIS, LOS, Overrun/Underrun detection
and flagging
• Microprocessor compatible interface

The Vl80C75 will indicate the presence
of bipolar violation in the input data as
well as a FIFO underflow/overflow.
Interfacing to the external bipolar line
driver is facilitated by the provision of
50% duty cycle drive pulses.
The system interface is microprocessor
compatible. The internal control and
status registers may be accessed by a
parallel interface.
System test is assisted by the provision
of a loopback feature which operates in
both directions.
The VL80C75 is fabricated in a double .
metal, n-well, two micron silicon gate
CMOS process and is housed in a 24pin 300 mil DIP or ceramic package.

VL80C75
01

SOl
AGCN
AGCP

NC
RClK
OMARKP
OMARKN

VOO

OMARKP
OMARKI'

ClKI

1
- - - - _.... 00
1-_ _ _ _-+ClKO

ClKO
00

AGCP

lC
RST
RS

-CS

02
03

-WE
-RE

VSS

lC
BDI

02
01
00

AGCN

-RE

-WE
-CS

RClK

RS
--~-RST

ORDER INFORMATION
Part
Number

Package

VL80C75-PC
VLSOC75-CC

Plastic DIP
Ceramic DIP

Note: Operating temperature range is 0 C to +70 C.

491

VLSI TECHNOLOGY, INC.
VL80C75

Signal Descriptions
Signal
Name

Pin
Number

Signal
Name
Bipolar Data Input - The received analog line signal is capacitively coupled to this high impedanceinput.

BDI
AGCN

Automatic Gain Control Output (Negative) - This output is used to provide an automatically
adjusted threshold voltage to the analog input comparators. A 0.1 JlF capacitor to VSS, a
1 Mil resistor to pin 3, and a 4.7 Mil resistor to VOO should be attached to this pin.

AGCP

Automatic Gain Control Output (Positive)- See AGCN. A 4.7 Mil resistor to VSS instead of
VOD should be used, however.

RClK

Reference Clock - This TTL input should have a clock which is 8 times the line frequency
(T1: 12.352 MHz, T1 C: 25.216 MHz, CEPT: 16.284 MHz). This clock is used internally to
recover the clock from the incoming received analog signal and is used to clock data out of
the jitter smoothing FIFO.

OMARKP

Output Mark (Positive) - Encoded data for driving positive line pulses appear at this output.

OMARKN

Output Mark (Negative) - Encoded data for driving negative line pulses appear at this output.

DO - 04

8-11,13

Data I/O - Configuration and status data is input or output on these bidirectional pins.

VSS

Negative Power Supply - Normally ground.

-RE

Read Enable - A low on this input enables the IC to output either the present configuration
control data or the alarm status data on the 00-04 data pins depending on the state of RS.

-WE

Write Enable - A low on this input enables the writing of configuration data on the 00-04
data pins. This pin must not be low at the same time as the -RE pin.

-CS

Chip Select - A low on this pin enables the reading or writing of data into the IC.

Read Select - A high on this input selects the configuration data to output during a read while
a low selects the alarm status data to be output.

RST

Reset - A logic high on this input initializes the internal configuration registers, resets the
alarm status bits, and initializes the jitter filter.

loop Control- This output is used to control an external VCO or VXo to provide a stable
RClK signal. The duty cycle will be 50% if the write clock to the jitter smoothing FIFO is
centered. The duty cycle will shorten or increase in proportion to the FIFO fill status.

Data Output - Decoded and received data is normally output on this pin.

ClKO

Clock Out - Data on the DO pin is output on the rising edges of this clock signal.

Data In - NRZ Data on this input is normally encoded and output at the OMARKP and
OMARKN pins.

ClKI

Clock In - This input is used to clock the data on the 01 pin into the IC on rising edges of this
signal. Nominally a 50% duty cycle signal.

VDD

Positive Power Supply - Normally, +5 V.

492

VLSI TECHNOLOGY, INC.
VL80C75

FUNCTIONAL DESCRIPTION
The VL80C75 consists of two separate
sections, the line receiver and the
the line transmitter.
The receiver accepts a bipolar (ternary)
input signal and converts it into a
decoded data stream. A clock signal is
extracted from the incoming data
stream.
The transmitter converts a digital input
data stream into two output drive pulses;
these pulses drive external transistors
which, in turn, drive the transmission
lines through line build out circuits, or
directly via a transformer. Data zeros
are represented by the absence of a
pulse in the output and ones are represented by a pulse from one or the other
transistor. The polarity of these pulses
typically alternate so that the OC content
of the signal equals zero.
Voltage Comparators
The function of these comparators is to
convert the incoming bipolar data stream
into two logic signals which correspond to
a positive or negative pulse on the input
line.
Mark Registers and Bias Drivers
The VL80C75 samples the comparator
outputs, and stores the pulses in the mark
registers. Should the input data pulse
width deviate from 50%, the AGC signals
(AGCP and AGCN) will alter the reference voltage of the comparators in such a
way that the output pulse width from the
comparators will drive the recovered
pulses' duty cycle towards 50%.
Data and Clock Recovery
This circuit extracts the clock from the
input stream by means of an injection
lock divider. The divider responds to the
leading edge of the recovered pulses by
resetting an internal divider to zero. If
there is no"mark" on the input then the
divider will operate in its free running
mode and generate a square wave clock.
If a pulse is detected, the leading edge of
the recovered clock is reset.
Data Decoder
The decoder converts input data format of
either AMI, B8ZS or HDB3 code into NRZ
data. This circuit also detects bipolar
format violations on the input data. The
VL80C75 operates using either AMI,
B8ZS, or HDB3 coding formats.
AMI (Alternate Mark Inversion)- In this
mode a positive "mark" is always

followed by a negative "mark" and viceversa. This process ensures that no OC
component exists in the signals. Zeros
are represented by the absence of
pulses. Consecutive zeros exceeding 15
bits are usually not allowed since clock
information is not present in this condition. However, the 80C75 will always
maintain a recovered clock based on the
last received mark position.
B8ZS (Bipolar 8 Zeros Suppression)
In this coding format, the input data
pattern follows the AMI code except that
a B8ZS code is substituted for each
block of eight consecutive zeros. This
assures steady clock updates regardless
of the data pattern. The B8ZS format is
OOOVBOVB, where B stands for an AMI
pulse and V is a pulse which violates that
rule.
HOB3 (High Density Bipolar 3 code)
This format obeys the AMI rule except
that a HOB3 filling sequence is inserted
for each block of four consecutive zeros.
The filling sequences are shown below.
Previous
Previous
Mark (B, V) Violation (V)

+
+

Filling
Sec_
-00000000+
+00+

Data Encoder
The encoder transforms the NRZ input
data into coded bit pattern of
either AMI, B8ZS or HOB3 format
depending on the bit code CO and C1.
The output signals (aMARKP,
aMARKN) are used to drive the transmission lines via external transistors.
FIFO (First-In First-Out Register)
This circuit has 32 stages and is 2 bits
wide and is used to eliminate jitter.
5 bit access counters in the FIFO.
provide the data read and write addresses. The read count is offset by 16
bits with respect to the write count when
initialized.
The write clock (normally the recovered
data clock) transfers data into the FIFO..
The read clock (normally RCLK + 8
which comes from an external vca and
does not contain jitter) transfers data out
the FIFO., normally 16 bits of delay later.

493

The frequency of the external vca is
controlled by signal Loop Control, LC, of
the FIFO.. If the write clock runs faster
or slower than the read clock, the
resultant DC voltage of LC will cause
the VCO. to raise or lower its frequency
and thereby correspondingly changing
the read frequency.
The range in which the read clock can
track the write clock is dependent on the
loop gain and the external crystal
oscillator.
o.verflow or underflow occurs when the
read and write counts are equal. When
this condition is detected it is flagged
and the FIFO. is reinitialized.
Cross Point Switch
This switch enables the internal signals
of theVL80C75 to be routed to allow
various configurations of the jitter filter
and data paths.
Divide by 8 Counter
This is a 3-bit bin?ry up counter. The
counter divides the incoming
reference clock, RCLK, by a factor of
eight. The RCLK frequency is of either
8 x T1 rate (12.352 MHz), 8 x T1 Crate
(25.216 MHz) or 8 x CEPT rate (16.384
MHz). The MSB output of this counter
serves as the read clock for the FIFO..
Zeros and Ones Detect
This circuit detects the receipt of a
string of 63 consecutive zeros (implying
the line is disconnected) or 1023 consecutive ones ("Blue Alarm" or AIS) on
the input ternary data stream and flags
these conditions in a status register.
PROGRAMMING
The VL80C75 may be configured for
several modes of operation. Control
data is written into the VL80C75 via the
00-04 pins when -CS and -WE pins
transition from low to high, while the
alarm status or present control data may
be read out on these pins when -CS
and -RE are low. The encode/decode
mode and the internal configuration of
the 80C75 are controlled by the data
written on the DO-D4 pins according to
Table 1.
The control data or alarm status is
output on the 00-04 pins when -CS and
-RE are low according to Table 2.

VLSI TECHNOLOGY, INC.
VL80C75

FIGURE 1. VL80C75 EVALUATION CIRCUIT

1/4
LSOO

Rs in ohms, Cs in
microfarads
Unless otherwise
noted

CLOSED/OPEN

INDICATORS

S1 READIWRITE
S2 ALARM/CONFIGURATION
S3 LB2= 0/1
S4 LB1 = 0/1
S5 LBO 0/1
S6M1 =0/1
S7 MO = 0/1

11 LB2IFIFO OVRFLW
12 LB1/FIFO UNDRFLW
13 LBO/A IS
14M1/l0S
15 MOl BIP VIOLATION

+5V

READIWRITE

1/6
LS04

494

VLSI TECHNOLOGY, INC.
VL80C75

FIGURE 1 . VL80C75 EVALUATION CIRCUIT (Cent.)

PE5764

~~::s:JIT'1 13~:-.5----'

PAIR
J8

J1-J4

~~~+-~AGCP
NC

r--------+-------1--------------=_~

CLKOI-

,...;;.......;....----, RCLK

-+----. OMARKP

DOL----+---+--------,
LC

I--------r---,

L~~~~~-----t_----=:J0MARKNRST~-----

RX
DATA

RS ~----,

- - - - - - - - , DO
....---..,. D1

-CS

I-·-----r...,

+5V

C14

=:-

1.1
U2
NE564

U31/2 LS393

LF2
~---.,REF

........,....,...-...,BF

VSS

1/6

LS04

495

VLSI TECHNOLOGY, INC.
VL80C75

TABLE 1. WRITE DATA
Control Bit Name 1 Data Line

C1/D3

CO 104

AMI Coding

B8ZS Coding

HOB3 Coding

Jitter Filter in Transmit Path: 01 to Jitter to OMARKN/P; BPI to DO

Jitter Filter in Receive Path: 01 to OMARKN/P; BPI to Jitter to DO

Loopback, Jitter Filter in TX: 01 to Jitter to DO; BPI to OMARKN/P

Loopback, Jitter Filter in RX: 01 to 00; BPI to Jitter to OMARKN/P

Loopback: 01 to 00; BPI to OMARKN/P

No Jitter Filter: 01 to OMARKN/P; BPI to 00

LB2/DO

LB1 101

X
0

LBO 102

Operating Mode

TABLE 2. READ DATA
Bit

RS=O

RS =0

FIFO Overflow

LB2

FIFO Underflow

LB1

AIS, > 1023 Consecutive Ones

LBO

LOS, > 63 Consecutive Zeros

Bipolar Violation

Note: Alarm bits reset after read.

EVALUATION CIRCUIT
A typical evaluation circuit is shown in
Figure 1. This circuit provides the
. ability to read and write data into the
VL80C75 and provides a simple
interface to the twisted pair. Line build
out circuitry is not included in this
schematic but can be easily added for a
given application. A typical T1 Multiplexer applications is shown in Figure 2.

496

VLSI TECHNOLOGY, INC.
VL80C75

FIGURE 2. TYPICAL APPLICATION

TRA~~II
PAIR

DO
ClKO

LINE
BUilD
OUT
80C75

••

01
ClKI

TO
MUlTIPlEXER
BACKPLANE
& CONTROL

-CS,-RE,-WE

RE6~11

•

01-05

•

PAIR

RClK

VCOIVXO

~
~
~

2464KBPS ~
VOICEOR
~
DATA
CHANNELS ~

T1 SPAN
2 TWISTED PAIRS,
1.544 MHz AM I

~
~

T1 MULTIPLEXER

497

VLSI TECHNOLOGY, INC.
VL80C75

AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Levels
Output Reference Levels

GND to 3.0 V
10 ns
1.5 V
1.5 V

AC CHARACTERISTICS:
Symbol

Parameter

tACC

Access Time

tSU

Setup Time

TA=Oto70 C, VDD=5V 10%,unlessotherwlsenoted.
Min

Typ

Units

Max
75

tHLDW

Hold Time Write

tHLDR

Hold Time Read

tRCLK

Clock Frequency

25.216

MHz

-13

BPI Sensitivity below DSX-1

Condition

-CS,-RE - - - - - - - " " " ' "

DO - D4

DATA VALID
tACC
tHLDR

-CS,-WE

-II-

Jr\

DO - D4

VALID DATA

.......

tSU

....

V, -

• ....

.......

tHLDW

498

VLSI TECHNOLOGY, INC.
VL80C75

ABSOLUTE MAXIMUM RATINGS
Ambient Operating
Temperature

-10 to +SO°C

Storage Temperature

-65 to + 150°C

Supply Voltage to
Ground Potential

-0.5 to +7.0 V

Applied Output
Voltage

-0.5 to +7.0 V

Applied Input
Voltage

-0.5 to +7.0 V

Power Dissipation

1.0W

DC CHARACTERISTICS: TA=Oto+70 C, VCC=5V
Symbol

the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions
for extended periods may affect device
reliability.

Parameter

Min

10%,unlessotherwlsenoted.

Limits
Typ

Max

Units

Conditions

VIL

Input Low Voltage

-0.5

O.S

VIH

Input High Voltage

2.0

5.0

VOL

Output Low Voltage

0.4

IOL =4.0 mA

IOH =-4.0 mA

VOH

Output High Voltage

ZIN

BPI Input Impedance

!ill

VREF

BPI Reference Level

2.5

IIH

Input Load Current

OLH

Output Leakage

ILHB

BPI Input Current

ICC

Operating Current

CAPACITANCE:
Symbol

3.9

-5.0

45
40

5.0

JlA

VIN = 5.5 V

10.0

JlA

VOUT =5.5 V

JlA

VIN = 5.5 V

Outputs Unloaded

=25 C, f =1.0 MHz

Parameter

Typ

Max

Unit

Condition

Input Capacitance

VOUT = 0 V. Note

Output Capacitance

VOUT = 0 V. Note

Note: This parameter is periodically sampled only.

499

VLSI TECHNOLOGY, INC.

500

VLSI TECHNOLOGY, INC.
VL82C031/0TI-031
IBM PS/2® MODEL 3D-COMPATIBLE SYSTEM CONTROLLER

FEATURES
• Controls 8086 CPU speed at 8 MHz
or 10 MHz
• Generates programmable fast and
normal timing for memory and 110
• Supports 256k- or 1M-bit DRAMS
• Supports up to 8M bytes of additional
memory
• Arbitrates the system bus among the
CPU. DMA. math coprocessor. and
DRAM memory refresh cycle
• Provides four channels of DMA as
well as burst mode

DESCRIPTION
The CMOS VL82C031/0TI-031 is the
System Controller device in the threechip VLSI/OTI PS/2 Model 30-compatible chip set. the other two devices are

the VL82C032/0TI-032 110 Controller
and the VL82C033/0TI-033 Floppy
Disk Controller and Data Separator.
The chip set integrates logic and
functions on PS/2 ModeI30-compatible systems to the point of reducing
the printed circuit board device count
by half. when memories are excluded.
Further. while offering complete
compatibility with the PS/2 Model 30compatible system. the VLSIIOTI chip
set improves system performance by
allowing 10 MHz operation with no
"wait states" (using 150 ns DRAMS).
supports an additional 8M-bytes of
memory using EMS (Expanded
Memory Specification) 4.0. and
controls system speed as necessary
for optimum performance.

PS/2 MODEL 3D-COMPATIBLE SYSTEM DIAGRAM

A fourth device. the VL82C037/0TI-037
VGA Video Graphics Controller is also
used in the PS/2 Model 30-compatible
system and provides high resolution
graphics of 800 x 600 elements with 256
colors. Graphic capabilities of this
resolution are usually found only on
more expensive systems.
The VL82C031/0TI-031 provides the
PS/2 Model-30 compatible system with
the dual speed control. 8 MHz or 10
MHz. necessary to operate the system at
peak performance. The device also
controls memory. 110. parity. address
paths. data paths as well as handling
four channels of direct memory access.
The VL82C031/0TI-031 is available from
both VLSI Technology Inc. and Oak
Technology. Inc. in an industry-standard
plastic 100 pin flat pack.

vo CHANNEL (PC BUS)
DATA BUS 8

ORDER INFORMATION
Part
Number

Package

VL82C031-FC

Plastic Flat Pack

PLEASE CONSULT DATA SHEET
FOR DETAILED INFORMATION
Notes: O~erating temperature range is O°C to +70°C.
IBM PS/2 is a registered trademark of IBM Corp.

501

VLSI TECHNOLOGY, INC.
VL82C032/0TI-032
IBM PS/2® MODEL 30-COMPATIBLE I/O CONTROLLER

FEATURES
• Controls Model 30-compatible system
keyboard and mouse
• Integrates the following functions on a
single device:
-8253-compatible timer/counter
-Dual 8250-compatible serial communications controller
-Parallel port controller
-8259-compatible interrupt controller
-58167-compatible real-time clock
• Decodes subsystems for floppy disk.
hard disk. and video
• Provides chip select logic for serial!
parallel ports. disk controllers. video
controllers. and real time clock.

DESCRIPTION
The CMOS VL82C032/0TI-032 is the
Input/Output Controller device in the
three-chip VLSI/OTI PS/2 Model 30-

compatible chip set. the other two
devices are the VL82C03110TI-031
System Controller and the VL82C033/
OTI-033 Floppy Disk Controller and
Data Separator.
The chip set integrates logic and
functions on PS/2 ModeI30-compatible systems to the point of reducing
the printed circuit board device count
by half. when memories are excluded.
Further. while offering complete
compatibility with the PS/2 Model 30compatible system. the VLSI/OTI chip
set improves system performance by
allowing 10 MHz operation with no
"wait states" (using 150 ns DRAMS).
supports an additional 8M-bytes of
memory using EMS (Expanded
Memory Specification) 4.0. and
controls system speed as necessary
for optimum performance.

A fourth device. the VL82C037/0TI-037
VGA Video Graphics Controller is also
used in the PS/2 Model 30-compatible
system and provides high resolution
graphics of 800 x 600 elements with 256
colors. Graphic capabilities of this
resolution are usually found only on
more expensive systems.
The VL82C032/0TI-032 provides the
PS/2 Model-30 compatible system with
control of both the keyboard and the
pointing device ("mouse"). control of two
serial communication channels. a realtime clock. as well as controlling both the
disk storage and display functions. It also
provides the chip select logic for the
functions it controls. The VL82C032/
OTI-032 is available from both VLSI
Technology Inc. and Oak Technology.
Inc. in an industry-standard plastic 100
pin flat pack.

PS/2 MODEL 30-COMPATIBLE SYSTEM DIAGRAM
110 CHANNEL (PC BUS)
DATA BUS 8
ADDRESS BUS 20

ORDER INFORMATION
Part
Number

Package

VL82C032-FC

Plastic Flat Pack

PLEASE CONSULT DATA SHEET
FOR DETAILED INFORMATION
Notes: Operating temperature range is O°C to +70°C.
IBM PS/2@ is a registered trademark of IBM Corp.

502

VLSI TECHNOLOGY, INC.
VL82C033/0TI-033
IBM PS/2® MODEL 30·COMPATIBLE FLOPPY DISK CONTROLLER
AND DATA SEPARATOR

FEATURES
• Provides a J.lPD765A-compatible
floppy disk controller

OTI-032 I/O Controller.

• Contains a precision analog data
separator
• Integrates an internal phase comparator, and voltage controlled oscillator
(VCO)
• Provides the system with three data
rates:
-250K bits-per-second
-300K bits-per-second
-500K bits-per-second

DESCRIPTION
The VL82C033/0TI-033 is the Floppy
Disk Controller and Data Separator
device in the three-chip VLSI/OTI PS/2
Model30-compatible chip set. the other
two devices are the VL82C031/0TI-031
System Controller and the VL82C0321

The chip set integrates logic and
functions on PS/2 Model30-compatible
systems to the point of reducing the
printed circuit board device count by
half, when memories are excluded.
Further, while offering complete
compatibility with the PS/2 Model 30compatible system, the VLSI/OTI chip
set improves system performance by
allowing 10 MHz operation with no "wait
states" (using 150 ns DRAMS), supports an additional 8M-bytes of memory
using EMS (Expanded Memory
Specification) 4.0, and controls system
speed as necessary for optimum
performance.
A fourth device, the VL82C037/0TI-037
VGA Video Graphics Controller is also
used in the PS/2 Model 30-compatible

system and provides high resolution
graphics of 800 x 600 elements with
256 colors. Graphic capabilities of this
resolution are usually found only on
more expensive systems.
The VL82C033/0TI-033 provides the
PS/2 Model-30 compatible system with
a J.lPD 765A-compatible floppy disk
controller function, a precision analog
data separator, an internal phase
comparator, the required filters, as well
as a voltage controlled oscillator (VCO).
The VL82C033/0TI-033 provides the
system with three floppy disk data rates:
250K bits-per-second, 300K bits-persecond, and 500K bits-per-second. The
VL82C033/0TI-033 is available from
both VLSI Technology Inc. and Oak
Technology, Inc. in an industry-standard
plastic 48 pin DIP.

PS/2 MODEL 3D-COMPATIBLE SYSTEM DIAGRAM
110 CHANNEL (PC BUS)
DATA BUS 8
ADDRESS BUS 20

ORDER INFORMATION
Part
Number

Package

VL82C033-PC

Plastic DIP

PLEASE CONSULT DATA SHEET
FOR DETAILED INFORMATION
Notes: ORerating temperature range is O°C to +70°C.
IBM PS/2® is a registered trademark of IBM Corp.

503

VLSI TECHNOLOGY, INC.
VL82C037/0TI-037
IBM VGA@·COMPATIBLE VIDEO GRAPHICS CONTROLLER

FEATURES

DESCRIPTION

• Single-chip VGA video graphics
device that is completely compatible
in the following systems:
-IBM PC/AT-compatible
-IBM PCIXT-compatible
-IBM PSI2-compatible

The VL82C037/0TI-037 VGA-compatible Video Graphics Controller is a
single-chip, high-integration, high
resolution graphics device intended for
use in IBM PS/2® Model 30-compat-

• Fully compatible with IBM VGA in all
modes
• Fully compatible with IBM basic input!
output system (BIOS)
• Provides 800 x 600 element highresolution graphics with 256 colors
• Flicker-free operation in all video
modes

ible systems as well PC/AT- and PCI
XT-compatible systems. It provides
high resolution graphics of 800 x 600
elements with 256 colors.
The VL82C037/0TI-037 is fully compatible with IBM VGA in all modes, as
well as being fully compatible with
Hercules graphics. VL82C037/0TI-037
compatibility also extends to IBM EGA
BIOS® (basic input/output system),

CGA and MDA. The VL82C037/0TI-037
automatically switches among the CGA,
MDA, and Hercules graphic protocols.
The VLSIIOTI VGA-compatible device
allows split-screen operattion with
independent scrolling and panning. It is
also flicker-free in all modes. It supports
an external digital-to-analog lookup table
as well as additional video memory for
high resolution operation with 256 colors.
The VL82C037 is available from both
VLSI Technology Inc. and Oak Technology, Inc. in an industry-standard plastic
100 pin flat pack.

• Hardware mouse cursor feature

SYSTEM BLOCK DIAGRAM
MD0-31
RASO ~1-----1
CAS~I---..f

WEA 1--1--.-+-1
OE1. ~t-..-t-H
WEB
' - -_ _-.--_ _----'
OEB

RASll-W.u.fFiAS-~__- - - - '

PLEASE CONSULT DATA SHEET
FOR DETAILED INFORMATION

RAS2
SAo-19

ABo-16

RAS3

DB0-7

PO-P7

DCLI<

PCLI<
BLANK

BLANK

RED
GREEN
BLUE

TO
DISPLAY

VIDEO
DAC
07-00
1.1-1.0
DACR
DAt:.W
MCLK
44.9 MHz

VSYNC
HSYNC

FI53

CSELO

CSELI

RESET
CSELO
SWITCH

ORDER INFORMATION

CSELI
NMI
CPURDY
DIR
CRnNT

PO-P7
BLANK
DCLK
HSYNC
VSYNC
ESVNC
EDCLK
EVIDEO
GROUND

AUXILIARY VIDEO CONNECTOR

504

Part
Number

Package

VL82C037-FC

Plastic Flat Pack

Notes: Operating temperature range is
O°C to +70°C.
IBM PS/2®, IBM VGA ® ,and IBM BIOS®
are registered trademarks of IBM Corp.

VLSI TECHNOLOGY, INC.
VL82C100
PC/AT·COMPATIBLE PERIPHERAL CONTROLLER

FEATURES

DESCRIPTION

• Fully compatible with IBM PC/AT-type
designs

The VL82C1 00 PC/AT-Compatible
Peripheral Controller replaces two
82C37A Direct Memory Access
Controllers, two 82C59A Interrupt
Controllers, an 82C54 Programmable
Counter, a 74LS612 AT Memory
Mapper, two 74ALS573 Octal ThreeState Latches, a 74ALS138 3-to-8
Decoder, and five other less-complex
integrated circuits. Using this internal
functionality, the VL82C1 00 provides all
24 address bits for 16M bits of DMA
address space. It also interfaces
directly to the CPU to handle all

• Replaces 19 logic devices
• Supports 12 MHz processor clock
• Device is available as "cores" for
user-specific designs
• Seven DMA channels
• 14 external interrupt requests
• Three timer/counter channels
• Designed in CMOS for low power
consumption

interrupts. Timing for refresh cycles,
and arbitration, between refresh and
DMA hold requests, are also controlled
by the VL82C100.
The device is manufactured with VLSI's
advanced high-performance CMOS
process and is available in JEDECstandard 84-pin plastic leaded chip
carrier (PLCC) package. The
VL82C100 is individually available, or
may be purchased as part of the
.
complete five-device IBM PC/ATcompatible kit.

BLOCK DIAGRAM

PLEASE CONSULT PC/AT COMPATIBLE USERS
MANUAL FOR DETAILED INFORMATION

SELECT
-MASTER--t DECODES
HLDA

I
2
XAO

XD0-7
IRC1,3-7

DRCG-3

-INTA

EOP
XIOR
XIOW

INT

---~g

)'5

INTERRUPT
CONTROLLER 1

8237A
XAO·7 ..
XDO·7

....

TIC

r---::P

8259A

ENABLE
GATE
.-... ALS573

INT

~'5

XD0-7
XA6-16

825M
.. XI OR
XIOW
XAO
XD0-7
INTERRUPT
CONTROllER 2

-AENl

r--DMA
CONTROLLER 1

~ACK().3

... 2

IRC8·1 5

XA1·8
XDO·7

ORCS·7

DMA
CONTROLLER 2 f -

... 2

-XIOR
->CIOW
-XMEMR _
->CMEMW
SYSCLK
.. ),10

""'-

XAO·1
XDG-7 . :

COUNTER
11 MER

xt~16

~
-AEN2

OllT1

)'2
.. XI OR
XAO-3
X'OW
MEMORY
XDG-7
MAPPER

XA16

~ACK$-7

A17~3

LS612

", R
~

XA1G-16
.1

RESET

---

0lJT2

XIOR
X'OW

XAO·g

IiOCHRD Y

ALS573
GATE

8254

MHZl 19

XDG-7

r--

8237A

READY
CONTROL

HLDA
OUTl

DMAREADY

HROl
HOLD
ARBITER

CPUHRa

ORDER INFORMATION
Part
Number

Package

VL82C100-QC

Plastic Leaded Chip Carrier (PLCC)

Note: Operating temperature range is O°C to +70°C

505

-REFRESH

VLSI TECHNOLOGY, INC.
VL82C101A
PC/AT-COMPATIBLE SYSTEM CONTROLLER

FEATURES

DESCRIPTION

• Fully compatible with IBM PC/AT-type
designs

The VL82C101A PC/AT-Compatible
System Controller replaces an 82C284
Clock Controller and 82C288 Bus
Controller (both are used in '286-based
systems), an 82C84A Clock Generator
and Driver, two PAL16L8 devices (used
for memory decode), and approximately
ten other less complex integrated
circuits used as Wait State logic. When
used in 12 MHz systems utilizing 80 ns
DRAMs, the device provides the
required one wait state for a "write"
operation, and zero wait states for a
"read" operation. A 12 MHz system
using 120 ns DRAMs will be provided
with one wait state for "write" and one

• Replaces 36 integrated circuits on the
PC/AT-type board
• Supports 12 MHz processor clock
• Device is available as "cores" for
user-specific designs
• Sink 20 rnA on slot driver outputs
• Designed in CMOS for low power
consumption

BLOCK DIAGRAM
POWERGOOD}
RC
XTAL1(1)
XTAL1(2)
XTAL2(l)
XTAL2(2)

--..

-So} -

8284
82284
CLOCK
GENERATION
AND READY
CONTROL

RESCPU
RESET
-READY
PROCCLK
SYSCLK
PCLK
-PCLK
OSC
MHZ119

READY

-Sl
AD-1

{

BUS
CONTROL

82288
BUS
CONTROL

MI-IO}
CPUHLDA
FASTMODE

BUS
COMMANDS

{

ARDYEN

ROM~~~}
RAMWTST

WAIT
STATE
LOGIC

-ROMCS
-REFRESH}
IOCHRDY

REFRESH
CONTROL

XAO,3,5·9

~
I

BUFFER
{

DMA
CONTROL

-DENLO
-DENHI
ALE
RAS
RAMALE
ENDRAS
-lOR
-lOW
-MEMR
-MEMW
-INTA
-SMEMR
-SMEMW
-XMEMR
-XMEMW
-XIOR
-XIOW
Q1

-MEMR
-REFEN

•

DATA
CONVERSION

-IOC516
F16}
-MEMC516
-MASTER
-AEN2
-AEN1

-LMEGCS

~~~~S

{

,
287 AND
PERIPHERAL
CONTROL

506

DIR245
GATE245
CNTLOFF
SAO
-DMAAEN

{

RESET287
-NPCS
-PPICS
XDATADIR

wait state for "read". The device
accepts both the 24 MHz crystal to
control the system clock as well as the
14.318 MHz crystal to control the video
clock. It also supplies reset and clock
signals to the 1/0 slots.
The device is manufactured with VLSl's
advanced high-performance CMOS
process and is available in a JEDECstandard 84-pin plastic leaded chip
carrier (PLCC) package. The
VL82C1 01 A is individually available, or
may be purchased as part of the
complete five-device IBM PC/ATcompatible kit.

ORDER INFORMATION
Part
Number
VL82C101A-QC

Package
Plastic Leaded Chip
Carr.ier (PLCC)

Note: Operating temperature is
O°C to +70°C

PLEASE CONSULT PC/ATCOMPATIBLE USERS
MANUAL FOR DETAILED
INFORMATION

VLSI TECHNOLOGY, INC.
VL82C102A
PC/AT-COMPATIBLE MEMORY CONTROLLER

FEATURES

DESCRIPTION

• Fully compatible with IBM PC/AT-type
designs

The VL82C102A PC/AT-Compatible
Memory Controller generates the row
address strobe (RAS) and column
address strobe (CAS) necessary to
support the dynamic RAMs used in PC/
AT-type systems. In addition, the
device allows five motherboard memory
options for the user, up to a full4M-byte
system. Four of the five options allow a
full 640k-bytes user area to support the
disk operating system (DOS). In
addition, the VL82C1 02A provides the
upper addresses to the VO slots, the
chip select for the ROM and RAM

• Completely performs memory control
function in IBM PC/AT-compatible
systems
• Replaces 20 integrated circuits on
PC/AT-type motherboard
• Support 12 MHz processor clock
• Device is available as "cores" for
user-specific designs
• Designed in CMOS for low power
consumption

BLOCK DIAGRAM

memory, and drives the system's
speaker.
The device is manufactured with VLSI's
advanced high-performance CMOS
process and is available in a JEDECstandard 84-pin plastic leaded chip
carrier (PLCC) package. The
VL82C102A is individually available, or
may be purchased as part of the
complete five-device IBM PC/ATcompatible kit.

ORDER INFORMATION
Part
Number

Package

VL82C102A-QC

Plastic Leaded Chip
Carrier (PLCC)

A17-23

t--.....- - - - - - . SA17-19
CPUA20

Note: Operating temperature range is
O°Cto +70°C

A20GATE
CPUHLOA

ALE

AEN

-MASTER
LA17-23
RAMALE
MAS-9
RAMSELO
RAMSEL1
RAMSEL2
-REFRESH
ADORSEL
REFBIT9
RESET
OUT2
XOO-7

•

F16
PAREN
RASO
RAS1
CASO
CAS1
-lMEGCS
-lCSOROM
-lCS1ROM
-MOBEN
SPKROATA

PORTB

PORTBRO
-VOCHCK}
-XMEMR
-PARERROR

XA16,4
-PPICS
-ENAS
Q1
-XIOR
-XIOW

NMI
ENRAMPCK
ENIOCK
PORTBWR

-CSB042
RTCOS
RTCAS
RTCR/-W

507

PLEASE CONSULT PC/ATCOMPATIBLE USERS
MANUAL FOR DETAILED
INFORMATION

VLSI TECHNOLOGY. INC.
VL82C103
PC/AT-COMPATIBLEADDRESS BUFFER

FEATURES

DESCRIPTION

• Fully compatible with IBM PC/AT-type
designs

The VL82C103 PC/AT-Compatible
Address Buffer provides the system
with a 16-bit address bus input from the
CPU to 41 buffered drivers. The
buffered drivers consist of 17 bidirectional system bus drivers, each capable
of sinking 20 rnA (50 'LS loads) of
current and driving 200 pF of capacitance on the backplane; 16 bidirectional
peripheral bus drivers, each capable of
sinking 8 rnA (20 'LS loads) of current;
and eight memory bus drivers, also
capable of sinking 8 rnA of current. Onchip refresh circuitry supports both

• Completely performs address buffer
function in IBM PC/AT-compatible
systems
• Replaces several buffers, latches and
other logic devices
• Supports 12 MHz processor clock
• Device is available as "cores" for
user-specific designs
• Designed in CMOS for low power
consumption

BLOCK DIAGRAM
A1-16
o

Q I-------r---t

SAO-16

LATCH
A1-16
ALE
CPUHLDA

256K-bit and 1M-bit DRAMs. The
VL82C103 provides addressing for the
I/O slots as well as the system.
The device is manufactured with VLSI's
advanced high-performance CMOS
process and is available in a JEDECstandard 84-pin plastic leaded chip
carrier (PLCC) package. The
VL82C103 is individually available, or
may be purchased as part of the
complete five-device IBM PC/ATcompatible kit.

ORDER INFORMATION
Part
Number
Package
VL82C103-QC

GATE
ENABLE
XA1-16

-DMAAEN ~r+------------~------~~

Plastic Leaded Chip
Carrier (PLCC)

Note: Operating temperature range is
O°C to +70°C

SAO-8
RESET -4-1-4----1---1 CLR
9BIT
COUNTER
-REFEN

-+-II-+----'----ct

ENABLE
MAO-7

MUX
ADDRSEL
-REFRESH

--t-t-t-+----------------H~-+...

SELO
SEL1
ENABLE

'-1--+---------. REFBIT9
">-----+-+-----------'.- BALE
-BHE

1--------+--.

LATCH
-XBHE
GATE
ENABLE

-5BHE

-ERROR---------~t;>o---------.~
508

IRQ13

PLEASE CONSULT PC/AT·
COMPATIBLE USERS
MANUAL FOR DETAILED
INFORMATION

VLSI TECHNOLOGY, INC.
VL82C104
PCIAT-COMPATIBLE DATA BUFFER

FEATURES

DESCRIPTION

• Fully compatible with IBM PC/AT-type
designs

The VL82C104 PC/AT-Compatible Data
Buffer provides a 16-bit CPU data bus
I/O as well as 40 buffered drivers. The
buffered drivers consist of 16 bidirectional system data bus drivers, each
capable of sinking 20 mA (50 'LS loads)
of current; eight bidirectional peripheral
bus drivers, each capable of sinking 8
mA (20 'LS loads) of current; and 16
memory data bus drivers, each capable
of sinking 8 mA (20 'LS loads) of
current. The VL82C104 also generates
the parity error signal for the system.

• Completely performs data buffer
function in IBM PC/AT-compatible
systems
• Replaces several buffers, latches and
other logic devices
• Supports 12 MHz processor clock
• Device is available as "cores" for
user-specific designs
• Designed in CMOS for low power
consumption
.

BLOCKDIAGRAM
00-7
OT/-R
-OENLO

.-.

ORDER INFORMATION

-...-- OIR

The device is manufactured with VLSI's
advanced high-performance CMOS
process and is available in a JEDECstandard 84-pin plastic leaded chip
carrier (PLCC) package. The
VL82C104 is individually available, or
may be purchased as part of the
complete five device IBM PC/ATcompatible kit.

• SOO-7

Part
Number
VL82C104-0C

ENABLE

Package
Plastic Leaded Chip
Carrier (PLCC)

LATCH
&

Note: Operating Temperature range is
O°Cto +70°C

BUFFER
XAO
CNTLOFF

-,..- I -

SEL

CLK

l - I---

~B
-MOB EN

MDO-7

OIR
ENABLE

MOPOUTO
XMEMR

-XMEMR

B
~A
OIR
ENABLE

XOATAOIR
AEN
PAREN

4A
01R245

-XBHE

PARITY
ERROR

XOO-7
-PAR ERROR

S08-15

B
I---

ENABLE
~

~A
L..

-OENHI

H
-

MOPINO

OIR

GATE245
08-15

P:1r

---1

OIR
ENABLE

----

M08-15

OIR

l+ MOPIN1

ENABLE
XMEMR

PARITY

MOPOUT1

509

PLEASE CONSULT PC/AT·
COMPATIBLE USERS
MANUAL FOR DETAILED
INFORMATION

VLSI TECHNOLOGY, INC.
VL82CPCAT
12 MHz AND 16 MHz PC/AT-COMPATIBLE SYSTEM CHIP SETS

FEATURES

DESCRIPTION

• Fully compatible with IBM PC/AT-type
designs

The IBM PC/AT compatible chip set
from VLSI Technology, Inc. supports 1Megabit dynamic RAMs, and is utilized
in systems with clock speeds up to 12
MHz. The chip set provides the IBM
PC/AT compatible system with a
completely compatible low-cost board
design solution. Further, since the
devices were designed using VLSl's
design tools, the devices can be quickly
modified for use as cores in userspecific designs.

• High-integration five-chip set
• Reduces non-memory system device
count from 110 to 16
• Devices are available as "cores" for
user-specific designs
• All devices designed in CMOS for low
power consumption
• Supports 12 MHz processor clock
• 16 MHz version of chip set with page
mode memory access will be available in 1988

The five device chip set has been
designed using the highest integration

BLOCK DIAGRAM

MOTHERBOARD BLOCK DIAGRAM

consistent with economic and reliable
system design. The VL82C103
Address Buffer and VL82C104 Data
Buffer are offered in separate packages, although their circuit is relatively
small. If they were offered as a single
device, the pin count would be extremely high, or some performance
degradation would occur.
The devices are manufactured with
VLSl's advanced high-performance
CMOS process and all five are available
in a JEDEC-standard 84-pin plastic
leaded chip carrier (PLCC) package.

DATA
LOWER ADDRESS

80287

80286

FLOATING
POINT
COPROCESSOR

CPU

UPPER ADDRESS

VL82C103

VL82C104

ADDRESS
BUFFER

DATA
BUFFER

VL82C100
PERIPHERAL
CONTROLLER

CONTROL

UPPER
ADDRESSES

r:=~~=====d£====jJ

BATIERY AND
OSCILLATOR

CLOCK AND CONTROL TO 80286
CLOCK AND CONTROL TO 80287

SYSTEM
CONTROLLER

MEMORY
CONTROLLER

REFRESH

VL82C101
°14.318
MHz

1----------1
SPEAKER

CLOCK AND RESET
TO SLOTS

PLEASE CONSULT THE
PC/AT-COMPATIBLE CHIP
SET USERS MANUAL FOR
DETAILED INFORMATION:
VL82CPCAT (12 MHz)
VL82CPCPM (16 MHz)

ORDER INFORMATION
Part
Number

Clock
Frequency Package

VL82CPCAT-QC

12 MHz

(5 Chips) Plastic Leaded Chip Carrier (PLCC)

VL82CPCPM-QC 16 MHz

(6 Chips) Plastic Leaded Chip Carrier (PLCC)

Note: Operating temperature range is O°C to +70°C

510

VLSI TECHNOLOGY, INC.
VL82C284
CMOS CLOCK GENERATOR AND INTERFACE

FEATURES

DESCRIPTION

• Generates clock for Intel 286-type
microprocessor-based systems

The VL82C284 is a clock generator and
driver that provides clock and interface
signals to Intel 286-type microprocessor-based systems. All device output
signals are synchronized to the output
clock signal.

• External TIL source or crystal may be
used as frequency source
- On-board crystal oscillator
• Provides Local-READY signal for
system synchronization

• Low power consuming CMOS
technology

The clock input and output frequencies
are twice the frequency used internally
by the microprocessor in the system.
To avoid confusion, the clock frequency
in the order information represents the
internal system microprocessor clock
frequency (e.g., the devices listed as 8
MHz would actually have an input

PIN DIAGRAM

BLOCK DIAGRAM

• Generates system reset
• Schmitt-trigger reset input assures
stability and noise immunity

F/-C

X1
X2
GND

The VL82C284 also supplies the
system with a high-noise-immunity
reset, as well as a synchronous
peripheral clock and a synchronous
-READY to indicate the completion of
the current bus cycle.
The peripheral clock is controlled by two
status input signals, which may be left
open if not used.
The VL82C284 is available in an 18-pin
ceramic and plastic DIP, as well as in a
plastic leaded chip carrier.

X1
X2
EFI

VL82C284

-ARDY
-SRDY
-SRDYEN
-READY
EFI

crystal or a TIL signal frequency of 16
MHz).

VCC
-ARDYEN
S1
SO
N.C.
PClK
RESET
-RES
ClK

RESET

F/-C

ClK
-RES
S1
SO

-READY
PClK

-SRDYEN
-SRDY
-ARDYEN
-ARDY

PLEASE CONSULT DATA
SHEET FOR DETAILED
INFORMATION

ORDER INFORMATION
Part
Number

Clock
Frequency

VL82C284-08PC
VL82C284-080C
VL82C284-08CC
VL82C284-10PC
VL82C284-100C
VL82C284-10CC

Package

8MHz

Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
Ceramic DIP

10 MHz

Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
Ceramic DIP

Note: Operating temperature range is

511

ooe to +70oe.

VLSI TECHNOLOGY, INC.
VL82C288
CMOS BUS CONTROLLER

FEATURES

DESCRIPTION

• Both local and system bus commands and control are provided

The VL82C288 is a CMOS bus controller for use in Intel 286-type microprocessor-based systems. A mode select pin
allows strapping the device for Multibus
operation or for short bus cycles. The
device also provides separate command
outputs for memory and I/O devices.
The data bus is controlled by separate
data direction and data enable signals.

• Supports both Multibus~ and highspeed bus cycle operating modes
• High-current output drivers
• Flexible command timing
• High degree of system configuration
flexibility
• Low power consuming CMOS
technology

A system clock provides the timing
control required by the microprocessorbased system. The device clock input is

twice the system clock speed. To avoid
confusion, the clock frequency listed in
the order information is the system clock
frequency (e.g., the devices listed as 8
MHz Clock Frequency, would have an
input clock of 16 MHz).
The VL82C288 meets the timing and
drive requirements to satisfy the IEEE796 standard for Multibus.
The VL82C288 is available in a 20-pin
ceramic or plastic DIP, as well as in a
plastic leaded chip carrier.

• Single 5 V power supply

PIN DIAGRAM

BLOCK DIAGRAM

VL82C288
-READY

vce

ClK

-SO

-S1

M/-IO

MCE

DT/-R

ALE

DEN

~ROC ..
....
..

STATUS

[

-MWTC
-INTA

COMMAND
OUTPUT
lOGIC

-IORC

-IOWC

CENI-AEN

CMDLY

CENL

-MRDC

-INTA

-MWTC

-IORC

GND

THREE·
STATE
COMMAND
OUTPUTS

-IOWC

4
JI

hi
I

STATUS
DECODER

[T~
DEN
MCE

~r
1

ALE

-51

MI-IO

ClK

STATE j4
MACHINE

CONTROL
OUTPUT
lOGIC

4
.~

CONTROL
INPUT
4
lOGIC

ORDER INFORMATION
Part
Number

Clock
Frequency

VL82C288-06PC
VL82C288-060C
VL82C288-06CC
VL82C288-08PC
VL82C288-080C
VL82C288-08CC

6MHz

8MHz

Package
Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
Ceramic DIP
Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
Ceramic DIP

Note: Operating temperature range is O°C to +70°C.

Multibus~

is a registered trademark of Intel Corp.

512

M8
-READY

CONTROL
OUTPUTS

PLEASE CONSULT DATA
SHEET FOR DETAILED
INFORMATION

-5~

4
4

CENI-AEN
CENl
CMDlY

VLSI TECHNOLOGY, INC.
VL82C37A
CMOS DIRECT MEMORY ACCESS (DMA) CONTROLLER

FEATURES

DESCRIPTION

• Low-power CMOS version of popular
8237A DMA controller

The VL82C37A Direct Memory Access
(DMA) Controller serves as a peripheral
interface circuit for microprocessor
systems, and is designed to improve
system performance by allowing
external devices to directly transfer
information from the system memory.
Memory-to-memory transfer capabil~y is
also provided. The VL82C37A DMA
Controller offers many programmable
control features that enhance data
throughput and system performance.
Dynamic reconfiguration is permitted
under program control.

• Four DMA channels
• Individual enable/disable control of
DMA requests
• Directly expandable to any number of
channels
• Independent auto-initialize feature for
all channels
• High performance 8 MHz version
available
• Transfers may be terminated by endof-process input
• Software controlled DMA requests

The VL82C37A is designed to be used
with an external 8-bit address register

such as the 8282. In addition to the four
independent channels, the VL82C37A is
expandable to any number of channels
by cascading additional controller
devices.
Three basic transfer modes allow the
user to program the types of DMA
service. Each channel can be individually programmed to auto-initialize to its
original condition following an end-ofprocess (EOP) input. Each channel also
has a 64K address and word count
handling ability.
The VL82C37A DMA Controller is
available in S MHz and 8 MHz clock
frequencies.

• Independent polarity control for
DREO and DACK signals

PIN DIAGRAM

BLOCK DIAGRAM

VL82C37A
-lOR
-lOW
-MEMR
-MEMW
VCC
READY
HlDA
ADSTB
AEN
HRO
-CS
ClK
RESET
DACK2
DACK3
DRE03
DRE02
DRE01
DREOO
GND

A7
A6
AS
A4
-EOP
A3
A2
A1
AO
VCC
DBO
DB1
DB2

DB3
DB4
DACKO
DACK1
DB5
DB6
DB7

ORDER INFORMATION
Part
Number
VL82C37A-OSPC
Vl82C37A-OSCC
VL82C37A-OSQC
Vl82C37A-08PC
Vl82C37A-08CC
Vl82C37A-OSOC

Clock
Frequency
S MHz

8 MHz

Package
Plastic DIP
Ceramic DIP
Plastic Leaded Chip Carrier (PlCC)
Plastic DIP
Ceramic DIP
Plastic leaded Chip Carrier (PlCC)

Note: Operating temperature range is O°C to +70°C.
513

VLSI TECHNOLOGY. INC
VL82C37A

PIN DIAGRAM

VL82C37A

•

N.C.
N.C.
HlDA
ADSTB
AEN
HRQ

-CS
ClK

38
37

36
35
34
33
32
31

A1
AO
VCC
DBO
DB1
DB2
DB3
DB4

N.C.

18 19 20 21 22 23 24 25 26 27 28

514

N.C.

VLSI TECHNOLOGY, INC.
VL82C37A

SIGNAL DESCRIPTIONS
Signal
Name

CLK

Clock Input: Controls the internal operations of the VLS2C37A DMA Controller and its rate
of data transfers. This input may be driven at up to 4 MHz for the standard VLS2C37A-04
and up to S MHz for the VLS2C37A-OS.

-CS

Chip Select: An active low input used to select the VL82C37 A as an I/O device during the
idle cycle, allows CPU communication on the data bus.

RESET

Reset: An active high input that clears the Command, Request, and Temporary Registers,
clears the firstlJast flip-flop, and sets the Mask Register. The device is in the idle cycle
following a Reset signal.

READY

Ready: An input that extends the memory read and write pulses from the VL82C37A
accommodating slow memories or I/O peripheral devices. During its specified setup/hold
time, READY must not make transitions.

HLDA

Hold Acknowledge: This active high signal from the CPU indicates that it has relinquished
control of the system busses.

DREOO-DRE03

19 - 16

DMA Request: These lines are individual asynchronous channel request inputs. Peripheral circuits use these lines to obtain DMA service. In fixed Priority, DREOO has the
highest priority and DRE03 has the lowest priority. Activating the DREO line of a channel
generates a request. DACK then acknowledges the recognition of DREO signal. Polarity
of DREO is programmable. Reset initializes these lines to active high. DREO must be
sustained until the corresponding DACK becomes active.

DBO - DB7

30 - 26,
23 - 21

Data Bus: These lines are bidirectional, three-state signals that connect to the system
data bus. The outputs are enabled in the program condition during the 110 read to output
the contents of an Address Register, a Status Register, the Temporary Register, or a
Word Count Register to the CPU. The outputs are disabled and the inputs are read during
an 110 Write cycle when the CPU is programming the VL82C37A control registers. During
DMA cycles the most significant eight bits of the address are sent onto the data bus and
are strobed into an external latch by ADSTB. In memory-to-memory operations, data from
the memory comes into the VL82C37A on the data bus during the read-from-memory
transfer. In the write-to-memory transfer, the data bus outputs determine the placement of
the data, not the new memory location.

Number

-lOR

Signal
Description

I/O Read: This is a bidirectional, active low, three-state line. In the idle cycle, it is an input
control signal used by the CPU to read the control registers. In the active cycle, it is an
output control signal used by the VL82C37A to access data from a peripheral during a
DMA Write transfer.

-lOW

110 Write: This signal is a bidirectional active ow, three-state line. It is used by the CPU to
load information into the VL82C37A DMA Controller. In the active cycle, it is used as an
output control signal used by the VL82C37 A to load data to the peripheral during a DMA
read transfer.

-EOP

End of Process: This is an active low bidirectional signal, which provides data on the
completion of DMA services and is available at the bidirection -EOP pin. The VL82C37 A
allows an external signal to terminate an active DMA service, by pulling the -EOP input
low with an external-EOP signal. The VL82C37A also generates a pulse when the
terminal count (TC) for any channel is achieved. This generates an -EOP signal that is
active on the -EOP Line. When -EOP is received, either internally or externally, it will
cause the VL82C37A to terminate the service, reset the request, and, if auto-initialize is
enabled, to write the base registers to the current registers of that channel. The mask bit
and TC bit in the status word will be set for the currently active channel by -EOP, unless
the channel is programmed for auto-initialize. In that case, the mask bit remains unchanged. During memory-to-memory transfers, -EOP will be output when the TC for
channel 1 occurs. To prevent erroneous end-of-process inputs, -EOP should be tied
high with a pull-up resistor if it is not used.

515

VLSI TECHNOLOGY, INC.
VL82C37A

SIGNAL DESCRIPTIONS (CO NT.)
Pin

Signal
Nama

Number

AO-A3

32 - 35

The four least significant address lines: These lines are bidirectional three-state signals.
In the idle cycle, they are inputs used by the CPU to address the register to be loaded or
read. In the active cycle they are outputs that provide the lower four bits of the output
address to the system.

A4-A7

37 - 40

The four most significant address lines: These lines are three-state outputs that provide
four bits of address. They are enabled only during the DMA service.

HRQ

Hold Request: This is the hold request to the CPU. It is used to request control of the
system bus. If the corresponding mask bit is clear, the presence of any valid DREQ
causes the VL82C37A to issue the HRQ signal. After HRQ is asserted, at least one clock
cycle (TCY) must occur before HLDA can be valid.

DACKO - DACK3

25,24,14,
15

DMA Acknowledge: This signal is used to notify an individual peripheral when it has been
granted a DMA cycle. The sense of these lines is programmable; Reset initializes them to
an active low.

AEN

Address Enable: This active high line enables the 8-bit latch containing the upper eight
address bits onto the system address bus. It can also be used to disable other system
bus drivers during DMA transfers.

ADSTB

Address Strobe: This active high is used to strobe the upper address byte into an external
latch.

-MEMR

Memory Read: This active low signal is a three-state output used to access data from a
selected memory location during a DMA read or memory-to-memory transfer.

-MEMW

Memory Write: This signal is an active low three-state output used to write data to a
selected memory location during a DMA write or memory-to-memory transfer.

VCC

5,31

+5 V ±5% power supply.

GND

Ground.

Signal
Description

TABLE1.INTERNALREGISTERS
Nama

Size

Number

Base Address Registers

16 bits

Base Word Count Registers

16 bits

Current Address Registers

16 bits

Current Word Count Registers

16 bits

Temporary Address Register

16 bits

Temporary Word Count Register

16 bits

Status Register

8 bits

Command Register

8 bits

Temporary Register.

8 bits

Mode Registers

6 bits

Mask Register

4 bits

Request Register

4 bits

516

VLSI TECHNOLOGY, INC.
VL82C37A

FUNCTIONAL
DESCRIPTION
The internal registers and major logic
blocks of the VL82C37A are shown in
the block diagram. Data interconnection
paths are also shown, but the various
control signals between the blocks are
not. The VL82C37A contains 344 bits of
internal register memory. Figure 3
describes these registers and shows
them by size. A complete description of
the registers and their functions can be
found in the Register Descriptions
section.
The VL82C37A contains three basic
control logic blocks. The Timing Control
block generates internal timing and
external control signals for the
VL82C37A. The program command
control block decodes the various
commands given to the VL82C37A by
the microprocessor before servicing a
DMA Request. Further, it decodes the
mode control word used to select the
type of DMA during the servicing. The
priority encoder block settles priority
contention between DMA channels
requesting service at the same time.
The external clock drives the timing
control block. In most VL82C37A
systems, this clock will usually be the
02 TTL clock from an VL82C84A. For
8085AH-2 systems above 3.9 MHz, the
8085 CLK(OUT) will not meet
VL82C37 A-05 (5 MHz) clock low and
high time requirements. In this case, an
external clock should be used to drive
the VL82C37A-05.

DMA OPERATION
The VL82C37A is designed to operate
in two major cycles: the idle and active.
Several states are contained in each
device cycle. The VL82C37A supports
seven separate states, each being one
full clock period. State I (SI), the
inactive state, is entered when the
VL82C37A has no valid DMA requests
pending. While in SI, the DMA controller
is inactive but may be in the program
condition, being programmed by the
processor. State 0 (SO) is the first state
of a DMA service. The VL82C37A has
requested a hold, but the processor has
not yet responded with an acknowledge.
The VL82C37A may still be programmed until it receives HLDA from the
CPU. An acknowledge from the CPU

signals that DMA transfers may begin.
S1, S2, S3 and S4 are the functional
states of the DMA service. If more time
is needed to complete a transfer than is
available with normal timing, wait states
(WS) can be placed between S2 or S3
and S4 by using the Ready line on the
VL82C37A. The data is transferred
directly from the 1/0 device to memory
(or vice versa) with -lOR and -MEMW
(or -MEMR and -lOW) being active simultaneously. The data is not read into
or driven out of the VL82C37A during
I/O-to-memory or memory-to-I/O DMA
transfers.
To complete memory-to-memory
transfers requires a read-from and a
write-to-memory. The states, which
resemble the normal working states, use
two-digit numbers for identification.
Eight states are needed for each
transfer: the first four states (S 11, S 12,
S13, S14), are used for read-frommemory and the last four states (S21 ,
S22, S23, S24), for the write-to-memory
of the transfer.

IDLECYCLE
When no channels are requesting
service, the VL82C37A enters the idle
cycle and performs SI states, sampling
the DREO lines every clock cycle to
determine if any channel is requesting a
DMA service. The device also samples
-CS, looking for an attempt by the
microprocessor to write or read to the
internal registers of the VL82C37A.
When -CS is low and HLDA is low, the
VL82C37A initiates the program
condition. The CPU now establishes,
changes or inspects the internal
definition of the part by reading from or
writing to the internal register. Address
lines AO-A3 are inputs to the device.
They select registers that will be read or
written. The -lOR and -lOW lines are
used to select and time reads or writes.
Because of the number and size of the
internal registers, an internal flip-flop is
used to generate one more bit of
address. This bit is used to determine
the upper or lower byte of the 16-bit
address and Word Count Registers.
This flip-flop can be reset by a separate
software command.

517.

Special software commands executed in
the VL82C37A during the program
condition are decoded as sets of
addresses with the -CS and -lOW
signals. The commands do not use the
data bus. Clear FirstlLast Flip-Flop and
Master Clear instructions are included.

ACTIVE CYCLE
When the VL82C37A is in the idle cycle
and a nonmasked channel requests a
DMA service, the device outputs an
HRO to the microprocessor and then
enters the active cycle. During this
cycle the DMA service takes place, in
one of four modes.
In the single transfer mode, the device is
programmed to make only one transfer.
The word count is decremented and the
address decremented or incremented,
following each transfer. When the word
count is completed from zero to FFFFH,
a Terminal Count (TC) causes an autoinitialize if the channel has been so
programmed.
The DREO signal must be held active
until DACK becomes active, in order to
be recognized. If DREO is held active
for the entire single transfer, HRO will
become inactive and release the bus to
the system. It again goes active and,
upon receipt of a new HLDA, another
single transfer is performed. In 8080A,
8085AH, 8088, or 8086 systems this
insures one full machine cycle execution
between DMA transfers. Details of
timing between the VL82C37A and
other bus control protocols depends
upon the characteristics of the microprocessor involved.
In the block transfer mode, the device is
activated by the DREO signal to
continue making transfers during the
service until a TC, caused by word count
going to FFFFH, or an external end of
process (-EOP) is encountered. DREO
need only be held active until DACK
becomes active. An auto-initialization
will occur at the end of the service, if the
channel has been programmed for it.
In the demand transfer mode the device
is programmed to continue making
transfers until a TC or external -EOP is
encountered or until the DREO signal
goes inactive. Transfers may continue

VLSI TECHNOLOGY, INC.
VL82C37A

until the 1/0 device has exhausted its
data capacity. After the 1/0 device has
caught up, the DMA service is reestablished by a DREQ signal. During
the interval between services, when the
microprocessor is operating, the
intermediate values of address and word
count are stored in the VLS2C37A
Current Address and Current Word
Count Registers. Only an -EOP can
cause an auto-initialize at the end of the
service. EOP is generated either by TC
or by an external signal.
The fourth mode cascades multiple
VLS2C37As together for easy system
expansion. The HRQ and HLDA signals
from additional VLS2C37As are connected to the DREQ and DACK signals
of a channel of the primary VLS2C37A.
This permits the DMA requests of the
additional device to propagate through
the priority network circuitry of the
preceding device. The priority chain is
not broken, and the new device waits for
its turn to acknowledge requests. As the
cascade channel of the primary
VLS2C37A is used only to prioritize the
additional device, it does not produce
any address or control signals of its
own, which could conflict with the
outputs of the active channel in the
added device. The VLS2C37A responds
to the DREQ and DACK signal, but all
other outputs except HRQ are disabled.
Figure S shows two devices cascaded
into a primary device using two of the
previous channels. This forms a twolevel DMA system. More VLS2C37A's
could be added at the second level by
using the remaining channels of the first
level. More devices can also be
cascaded into the channels of the
second-level devices, forming a third
level.

TRANSFER TYPES
Each of the three modes of active
transfer can perform three different
types of transfers: read, write and
verify. Write transfers move data from
an 1/0 device to the memory by activating -MEMW and -lOR; read transfers
move data from memory to an 1/0
device by activating -MEMR and -lOW.
Verify transfers are pseudo routines:
the VLS2C37A DMA Controller operates
as in read or write transfers generating
addresses, and responding to -EOP,

and other operations.The memory and
1/0 control lines remain inactive. The
verify mode is not permitted during
memory-to-memory operation.
To perform block moves of data from
one memory address space to another
with a minimum of programming, the
VLS2C37A includes a memory-tomemory transfer feature. Programming
a bit in the Command Register selects
channels 0 and 1 to operate as memoryto-memory transfer channels. The
transfer is initiated by setting the
software DREQ for channel O. The
VLS2C37A requests a DMA device as
usual. After HLDA is true, the device,
using eight-state transfers in block
transfer mode, reads data from the
memory. The channel 0 Current
Address Register is the source for the
address, and is decremented or
incremented as usual. The data byte
read from the memory is then stored in
the VLS2C37A internal Temporary
Register. Channel 1 writes the data
from the Temporary Register to memory
using the address in its Current Address
Register and incrementing or decrementing it as usual. The channel 1
current word count is decremented.
When the word count goes to FFFFH, a
TC is generated causing an -EOP
output terminating the service.
Channel 0 may be programmed to hold
the same address for all transfers, which
permits a single word to be written to a
block of memory.
The VLS2C37A responds to external
-EOP signals during memory-tomemory transfers. In block search
schemes data comparators may use this
input cn finding a match. The timing of
memory·to-memory transfers is shown
in Figure 10. Memory-to-memory
operations can be detected as an active
AEN signal with no DACK outputs.
A channel may be set up to autoinitialize by setting a bit in the Mode
Register. During initialization, the
original values of the Current Address
and Current Word Count Registers are
automatically restored from the Base
Address and Base Word Count Registers of that channel following -EOP.
The base registers and the current
registers are loaded at the same time.
They remain unchanged thoughout the

518

DMA service. The mask bit is not set
when the channel is in auto-initialize.
Following auto-initialize, the channel is
prepared to perform another DMA
service, without CPU action, as soon as
a valid DREQ is detected.
The VLS2C37A has two types of priority
encoding available as software-selectable options. The fixed priority
option sets the channels in priority order
based upon the descending value of
their number. The channel with the
lowest priority is 3, then 2,1 and the
highest priority channel is O. After
recognizing anyone channel for service,
the other channels are prevented from
interferring with that service until it is
completed.
In the rotating priority option, the last
channel to get service becomes the
lowest priority channel with the others
rotating in order.
Rotating priority allows a single chip
DMA system. Any device requesting
service is guaranteed to be recognized
after no more than three higher priority
services have occurred. This prevents
anyone channel from dominating the
system.
To achieve even greater throughput
where system characteristics permit, the
VLS2C37A DMA Controller can compress the transfer time to two clock
cycles. State S3 is used to extend the
access time of the read pulse. By
removing state S3, the read pulse width
is made equal to the write pulse width,
and a transfer consists only of state S2
to change the address and state S4 to
perform the read/write. S1 state still
occurs when AS-A 15 need updating
(see the Address Generation section.)
To reduce pin count, the VLS2C37A
multiplexes the eight higher order
address bits on the data lines. State S1
is used to output the higher order
address bits to an external latch, where
they may be placed on the address bus.
The falling edge of the Address Strobe
(ADSTB) is used to load these bits from
the data lines to the latch. Address
Enable (AEN) is used to enable the bits
onto the address bus through a threestate enable. The lower order address
bits are directly sent by the VLS2C37A .
Lines AO-A7 are connected to the
address bus.

VLSI TECHNOLOGY, INC.
VL82C37A

During block and demand transfer mode
services, including multiple transfers, the
addresses generated will be in order.
During a large number of transfers the
data held in the external address latch
will not change. This data will change
when a carry or borrow from A7 to AS
takes place in the normal order of
addresses. To expedite transfers, the
VLS2C37A DMA Controller executes S1
states only when needed to update ASA15 in the latch. For long services, S1
states and address strobes may occur
only once every 256 transfers, a savings
of 255 clock cycles for each 256
transfers.

REGISTER DESCRIPTION
Current Address Register: Each channel
has a 16-bit Current Address Register.
This register holds the value of the
address used during DMA transfers.
The address is automatically incremented or decremented after each
transfer and the intermediate values of
the address are stored in the Current
Address Register throughout the
transfer. The microprocessor reads this
register in successive S-bit bytes. It may
also be reinitialized by an auto-initialize
to its original value which takes place
only after an -EOP.
Current Word Register: Each channel
has a 16-bit Current Word Count
Register that determines the number of
transfers to be performed. The actual
number of transfers is one more than
the number programmed in the Current
Word Count Register; programming a
count of 100 will result in 101 transfers.
The word count is decremented after
each transfer; the intermediate value of
this word count is stored in the register
during the transfer. When the value in
the register goes from 0 to FFFFH, a TC
is generated. The register is then
loaded or read in successive S-bit bytes
by the microprocessor in the program
condition. Fo"owing the end of a DMA
service, it may also be reinitialized by an
auto-initialization to its original value .
wh~hoccurnon~on-EO~ H~~n~

auto-initialized, this register has a count
of FFFFH after TC.
Base Address and Base Word Count
Registers: Each channel has a pair of
16-bit Base Address and Base Word
Count Registers that store the original
value of their associated current

registers. Throughout auto-initialization
these values are used to restore the
current registers to their original values.
The base registers are written at the
same time with their corresponding
current register in S-bit bytes in the
program condition by the microprocessor. These registers cannot be read by
the microprocessor.

Status Register: The Status Register is
available to be read out of the
VLS2C37A DMA Controller by the
microprocessor and contains information
about the status of the devices at this
point. This information includes which
channels have reached a terminal count
and which channels have pending DMA
requests.

Command Register: This S-bit register
controls the operation of the VL82C37 A,
is programmed by the microprocessor in
the program condition and is cleared by
reset or a master clear instruction.
Figure 2 lists and describes the function
of the command bits.

Bits 0-3 are set each time a TC is
reached by that channel or an external
-EOP is applied and are cleared upon
reset and on every status read. Bits 4
through 7 are set whenever their
corresponding channel is requesting
service.

Mode Register: A" channels have a 6-bit
Mode register. When the register is
being written to by the microprocessor in
the program condition, bits 0 to 1
determine which channel the Mode
Register is to be written.

Temporary Register: The Temporary
Register is used to hold data during
memory-to-memory transfers. The last
word moved can be read by the microprocessor in the Program Condition
following the completion of the transfers.
The Temporary Register always
contains the last byte transferred in the
previous memory-to-memory operation,
unless cleared by a reset.

Request Register: The VLS2C37 A can
responds to requests for DMA service
that are initiated by software as we" as
by a DREO signal. Each channel has a
request bit associated with it in the 4-bit
Request Register. These are nonmaskable and can be prioritized by the
priority encoder network.
Each register bit is set or reset separately under software control, or is
cleared upon generation of a TC or
external-EOP. The entire register is
cleared by a Reset. To set or reset a
bit, the software loads the correct form
of the data word. Table 2 shows
register address coding. To make a
software request, the channel must be in
block mode.
Mask Register: Each channel has an
associated mask bit that can be set to
disable the incoming DREO signal. A
mask bit is set when its associated
channel produces an -EOP, if the
channel is not programmed for autoinitialize. Any bit of the 4-bit Mask
register may also be set or cleared
separately under software control. The
entire register is set by a reset, which
disables all DMA requests until a clear
Mask Register instruction allows them to
occur. This instruction to separately set
or clear the mask bits is similar in form
to that used w~h the Request Register.

519

Software Commands: These additional
special software commands can be
executed in the program condition and
do not depend on any specific bit pattern
on the data bus.
The clear firstllast flip-flop command is
executed prior to writing or reading new
address or word count information to the
VL82C37A. This initializes the flip-flop
to a known state so that subsequent
accesses to register contents by the
microprocessor will address upper and
lower bytes in the correct sequence.
The Master Clear software instruction
has the same effect as the hardware
reset. The Command, Status, Request,
Temporary, and Internal FirsVLast FlipFlop Registers are cleared and the Mask
Register is set. The VL82C37A enters
an idle cycle.
The Clear Mask Register command
clears the mask bits of a" four channels,
enabling them to accept DMA requests.

PROGRAMMING
The VLS2C37A DMA Contro"er accepts
programming from the host processor
any time that HLDA is inactive, even if
the HRO signal is active. The host must
assure that programming and HLDA are

VLSI TECHNOLOGY, INC
VL82C37A

mutually exclusive. A problem can
occur if a DMA request occurs, on an
unmasked channel while the VL82C37A
is being programmed.
For example, the CPU may be starting
to reprogram the two-byte Address
Register of a channel when that
channel receives a DMA request. If the

VL82C37A is enabled (bit 2 in the
command register is 0) and that
channel is unmasked, a DMA service
will occur after one byte of the Address
Register has been reprogrammed. This
can be avoided by disabling the
controller - setting bit 2 in the command
register - or masking the channel before

programming another registers. Once
the programming is complete, the
controller can be enabled (unmasked).

When the processor replies with a HLDA
signal, the VL82C37A takes control of
the addr~ss, data, and control buses.
The address for the first transfer
operation is output in two bytes - the
least significant eight bits on the eight
address outputs, and the most significant eight bits on the data bus. The
contents of the data bus are then

latched' into the 8282 8-bit latch to
complete the full 16 bits of the address
bus. The 8282 is a high-speed, 8-bit,
three-state latch in a 20-pin DIP
package. After the initial transfer takes
place, the latch is updated only after a
carry or borrow is generated in the least
significant address byte. Four DMA
channels are available when one
VL82C37A DMA Controller is used.

After power-up all internal locations,
including the Mode registers, should be
loaded with a valid value. This should
be done to unused channels as well.

APPLICATION
Figure 1 shows a convenient method for
configuring a DMA system with the
VL82C37A DMA Controller and an
8080Al8085AH microprocessor system.
Whenever there is at least one valid
DMA request from a peripheral device,
the multimode VL82C37A DMA Controller issues a HRO to the processor.

FIGURE 1. SYSTEM INTERFACE
f\.

ADDRESS BUS AO-A15

V
A8-A15

.....

-0E

.....

8282

• STB
AO-A15

"'-..7

BUSEN
HLDA
HOLD

f4-

CPU

AEN
HLDA
HRQ

AO-A3

A4-A7

VL82C37A
-lOW

RESET-MEMW

DACKO-3

/').

ADSTB
DBO- / A
DB7

f\.

\r-V

CLK I-MEMRI -lOR I DREOO-3 I
CLOCK

RESET
-MEMR
-MEMW

f4~4

...

-lOR ""

J~~L

-lOW""
DOO-DB7

-cs

8-BIT LATCH

BUS

~
SYSTEM DATA BUS

'"
V

520

VLSI TECHNOLOGY, INC.
VL82C37A

FIGURE 2. COMMAND REGISTER
7

6 5

4 3

I I I I I I

Bit

0 ~ Number

III~ ~

Memory-to-memory disable
Memory-to-memory enable

Channel 0 address hold disable
Channel 0 address hold enable
X If bit 0 .. 0
Controller enable
Controller disable

0
1

Normal timing
Compressed timing
X If bit 0 = 1

0
1

a
1

Fixed priority
Rotating priority

Late write selection
Extended write selection
X If bit 3.,. 1

a
1

DREO sense active high
DREO sense active low
DACK sense active low
DACK sense active high

FIGURE 3. MODE REGISTER
76543210~

I I I I I I I I I

Bit
Number

00
01
10
11

Channel a Select
Channel 1 Select
Channel 2 Select
Channel 3 Select

00
01
10
11

Verify transfer
Write transfer
Read transfer
Illegal
If bits 6 and 7 = 11

a
1

Autoinitialization disable
Autoinitialization enable

Address increment select
Address decrement select

00
01
10
11

Demand mode select
Single mode select
Block mode select
Cascade mode select

521

VLSI TECHNOWGY, INC
VL82C37A
FIGURE 6. MASK REGISTER (SELECT MODE)

FIGURE 4. REQUEST REGISTER

5 4

2 1

I I I I I I I I I

j
Don't
care

Bit
Number

7 6

4 3

II I I

Select channel
Select channel
Select channel
Select channel

0
1

Reset request bit
Set request bit

--y--

0
1

Bit
Number

00 Select channel 0 mask bit
01 Select channel 1 mask bit
10 Select channel 2 mask bit
11 Select channel 3 mask bit

3
0
1

Clear mask bit
Set mask bit

FIGURE 7. MASK REGISTER (MASK MODE)

4 3

Channel 1
0 has
has reached
reached TC
TC
Channel
Channel 2 has reached TC
Channel 3 has reached TC

0 ~ Bit

Don't
care

Channel 0 request
Channel 1 request
Channel 2 request
Channel 3 request

TABLE 2. REGISTER CODES
Signals
Register

Operation

Command

Write

-CS

2 1

I I I I I I I I I

Number

1~:

Don't
care

0 ~ Bit

3 2

I I I I I I I I I

00
01
10
11

FIGURE 5. STATUS REGISTER

I I I I I I I I I

6 5

-lOR -lOW

Mode

Write

Request

Write

Mask

SetlReset

Mask

Write

Temporary"

Read

Status

Read

1
0

522

Number

Clear channel 0 mask bit
Set channel 0 mask bit

0
1

Clear channel 1 mask bit
Set channel 1 mask bit

0
1

Clear channel 2 mask bit
Set channel 2 mask bit

0
1

Clear channel 3 mask bit
Set channel 3 mask bit

VLSI TECHNOLOGY, INC.
VL82C37A

TABLE 3. SOFTWARE COMMAND CODES
Signals
Operation

-lOR

Read Status Register

Write Command Register

Illegal

Write Request Register

-lOW

Illegal

Write Single Mask Register Bit

Illegal

Write Mode Register

Illegal

Clear Byte Pointer Flip/Flop

Read Temporary Register

Master Clear

Illegal

Clear Mask Register

Illegal

Write All Mask Register Bits

FIGURE 8. CASCADED VL82C37 A CONTROLLERS
2ND LEVEL

VL82C37A

1ST LEVEL

MICROPROCESSOR

~ HRQ

DREQ

I+--

~ HLDA

DACK

DREQ

0 4 - HRQ

DACK

VL82C37A

INITIAL DEVICE

HLDA
VL82C37A

ADDITIONAL DEVICES

523

VLSI TECHNOLOGY, INC.
VL82C37A

TABLE 4. WORD COUNT AND ADDRESS REGISTER COMMAND CODES
Channel
0

Signals

Operation

8ase and Current Address

Write

0
0

1
1

Current Address

Read

0
0

8ase and Current Word Count

Write

Current Word Count

-CS

Internal
Rip-Flop

Data Bus
DBO-DB7

0
0

0
1

AO·A7
AS·A15

0
0

1
1

0
0

0
1

AO·A7
AS·A15

0
0

1
1

0
0

1
1

0
1

WO·W7
WS·W15

Read

0
0

1
1

0
0

1
1

0
1

WO·W7
W8·W15

8ase and Current Address

Write

0
0

1
1

0
0

1
1

0
0

0
1

AO·A7
A8·A15

Current Address

Read

0
0

1
1

0
0

1
1

0
0

0
1

AO·A7
AS·A15

8ase and Current Word Count

Write

0
0

1
1

0
0

1
1

0
1

WO·W7
W8·W15

Current Word Count

Read

0
0

1
1

0
0

1
1

0
1

WO·W7
W8·W15

Base and Current Address

Write

0
0

1
1

0
0

1
1

0
0

0
1

AO·A7
AS·A15

Current Address

Read

0
0

1
1

0
0

1
1

0
0

0
1

AO·A7
A8·A15

Base and Current Word Count

Write

0
0

1
1

0
0

1
1

0
0

1
1

0
1

WO·W7
W8·W15

Current Word Count

Read

0
0

1
1

0
0

1
1

0
0

1
1

0
1

WO·W7
W8·W15

Base and Current Address

Write

0
0

1
1

0
0

1
1

0
0

0
1

AO·A7
AS·A15

Current Address

Read

0
0

1
1

0
0

1
1

0
0

0
1

AO·A7
A8·A15

Base and Current Word Count

Write

0
0

1
1

0
0

1
1

0
1

WO·W7
W8·W15

Current Word Count

Read

0
0

1
1

0
0

1
1

0
1

WO·W7
WS·W15

-lOR -lOW

524

VLSI TECHNOLOGY, INC.
VL82C37A

TABLE 5. DMA MODE AC CHARACTERISTICS
Symbol

VL82C37A-04
Min
Max

Parameter

VL82C37A-05
Max
Min

Vl82C37A-08
Min
Max

Unit

TAEl

AEN High from ClK low (S1) Delay Time

225

200

105

TAET

AEN low from ClK High (S1) Delay Time

150

130

TAFAB

ADR Active to Float Delay from ClK High

120

TAFC

Read or Write Float from ClK High

120

TAFDB

DB Active Float Delay from CU< High

190

170

135

TAHR

ADR from Read High Hold Time

TCY-100

TCY-75

TAHS

DB from ADSTB low Hold Time

TAHW

ADR from Write High Hold Time

TCY-50

TAK

DACK Valid from ClK low Delay Time (Note 7)

220

170

105

-EOP High from ClK High Delay Time (Note 10)

190

170

105

-EOP low from ClK High Delay Time

190

170

105

TASM

ADR Stable from ClK High

TASS

DB to ADSTB low Setup Time

TCH

Clock High Time (Transitions

TCl

Clock low Time (Transitions

TCY

ClK Cycle Time

TDCl

ClK High to Read or Write low Delay (Note 4)

200

190

120

TDCTR

Read High from ClK High (S4) Delay Time (Note 4)

210

190

115

TDCW

Write High from ClK High (S4) Delay (Note 4)

150

130

120

190

120

190

10 ns)

100

110

250

200

125

TD01
TD02

170

100

HRO Valid from ClK High Delay Time (Note 5)

TEPS

-EOP low from ClK low Setup Time

TEPW

-EOP Pulse Width

225

220

135

TFAAB

ADR Float to Active Delay from ClK High

190

170

100

TFAC

Read or Write Active from ClK High

150

TFADB

DB Float to Active Delay from ClK High

225

200

110

THS

HlDA Valid to ClK High Setup Time

TIDH

Input Data from -MEMR High Hold Time

TIDS

Input Data to -MEMR High Setup Time

190

170

TODH

Output Data from -MEMW High Hold Time

TODV

Output Data Valid to -MEMW High

125

TOS

DREQ to ClK low (S1,S4) Setup Time

TRH

ClK to READY low Hold Time

TRS

READY to ClK low Setup Time

TSTl

ADSTB High from ClK High Delay Time

150

130

110

TSTT

ADSTB low from ClK High Delay Time

110

Explanatory notes follow DC Characteristics Table.

525

ns
ns

VLSI TECHNOLOGY, INC.
VL82C37A

FIGURE 9. DMA TRANSFER TIMING (SEE TABLE 5.)

~~~
~
~os ~
SI

ClK

S2,

54 I

80,

LlJ~100 ___ • j4HRQ
-..f THS~ 14-

DREO

HlDA

TAEl

\ \ \ \

F-J

TFADS

TFAAB

AO-A7

-IOW,- MEMW

INTf.-EOP

I--

TOO ....

I~TSTT_~

,. .

hl-*-~ssTAHS

TFAC

- ...

l¥A8-A15.:11

~ ~-m"TAFDB
V
ADDRESS VALID

~
F"

ADDRESS VALID

• +T~R
~

TDCTR 1'1-

1<11.

~
TDCTW

TAHW

L=
~t-TAHR

I"!!.

TDCTR

.... I;~

TDCTW

~.I"'"""

(FO~OEO WRITE)

h
'-\\\\\\\\\\'-

lkTAK

7/J/ULLLLL/

I4--TAFC

- r

~ IZ~'~~ ~t-TAK
I

526

TAK

~TAFAB

TDCl

~I
¥"

t--

~
.....

"TASM

14- ~TAHW
~...

{~ TAET

TEPS

TEFW

EXT/-EOP

TCH

\1\ \ 1\ \ \'

DACK

~\ :\ \ \ \ \ \ \ \\

I.ouI J. . . . .
~

SI
R"
.,

DBO-DB 7

•

l+- J
TSTL

-IOR,-M EMR

AEN
ADSTB

l.:r1 l...A1 "Pt=
~t+
n rfi~~TCY+t=4"

VLSI TECHNOLOGY, INC.
VL82C37A

FIGURE 10. MEMORY-TO-MEMORY TRANSFER TIMING (SEE TABLE 5)

S11

S12

S13

S21

S14

ADSTB

AO-A?

DBO-DB?

-MEMR

-MEMW
-EOP
EXT -EOP -

____................

527

S22

S23

S24

VLSI TECHNOLOGY, INC.
VL82C37A

TABLE 6. PERIPHERAL MODE AC CHARACTERISTICS
VL82C37A-04
Symbol

Parameter

Min

Max

VL82C37A-OS

VL82C37A-08

Min

Max

Unit

Max

TAR

ADR Valid or-CS Low to Read Low

TAW

ADR Valid to Write High Setup TIme

150

130

TCW

CS Low to Write High Setup TIme

150

130

TDW

Data Valid to Write High Setup TIme

150

130

TRA

ADR or CS Hold from Read High

TRDE

Data Access from Read Low (Note 3)

TRDF

DB Float Delay from Read High

TRSTD

Power Supply High to RESET Low Setup Time

500

TRSTS

RESET to First -lOW

2TCY

RESET Pulse Width

300

TRSTW

200
100

140
0

120

TRW

Read Width

250

200

155

TWA

ADR from Write High Hold Time

TWC

CS High from Write High Hold Time

TWD

Data from Write High Hold Time

TWWS

Write Width

200

160

100

Explanatory notes follow DC Characteristics Table.

FIGURE 11. SLAVE MODE WRITE TIMING (SEE TABLE 6)

-CS

TCW

TWWS
-lOW

lAW
AO-A3

INPUT VAllO

TOW
OBO-DB7

INPUT VAllO

528

VLSI TECHNOLOGY, INC
VL82C37A

FIGURE 12. SLAVE MODE READ TIMING (SEE TABLE 6)

-CS ' . .
~
~----------------------------~
AQ-A3

- )!:

ADDRESS MUST BE VALID

(

~T_AR_1__~:~=~=_=_=_=_=_=_=~=_-TR~ _D-E_T~R~_W~_-=~1=_-=~=~.-~-~I~ ~ ~ ~ ~- I-TR-:-:A-j~

-lOR ____
DBQ-DB7

DATAOUTVALID

FIGURE 13. READY TlMING (SEE TABLE 5)

ClK
-READ

TDCTR

------+-_
TDCl

TDCl

TDCTW

-WRITE
EXTENDED- - - - . . / ' '- ___
WRITE
TRH

READY

lRS

&i rJj

\\~~~L

529

TR5

VLSI TECHNOLOGY, INC
VL82C37A

FIG URE 14. COMPRESSED TRANSFER TIMING (SEE TABLE 5)
S2

elK

AO-A7

-REAO------------------~I

-WRITE -----------------~

INTI-EOP _________________________-+______

TEPS
EXT/- EOP ___________________--..--_~

______

_____________~~-J

~~~w~~.
_

FIGURE 15. RESET TIMING (SEE TABLE 6)

vee ___-'/l<1li1•. - - - - - -

TRSTO - - - - - - - - -.......

TRSTW

~
~,

RESET

-~~------------------

~:R:TS~

-----------------------------------------~i I
-lOR OR -lOW

--530

VLSI TECHNOLOGY, INC.
VL82C37A

ABSOLUTE MAXIMUM RATINGS
Supply Voltage
-0.5 to 7.0 V
Input Voltage
-0.5 to 5.5 V
Output Voltage
-0.5 to 5.5 V
Operating Temperature 0 °C to +150°C
Storage Temperature -65°C to +150°C

Stresses above those listed under
"Absolute Maximum Ratings" may cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any

other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device
reliability.

DC CHARACTERISTICS:
Symbol
VOH

Parameter
Output High Voltage

Min

Typ (1)

Max

Unit

Test Conditions

2.4

10H .. -200~

3.3

10H .. -100 ~ (HRO Only)

450

10L ... 2.0 rnA (data bus) -EOP
10L = 3.2 rnA (other outputs) (8)
10L = 2.5 rnA (ADSTB) (8)

VOL

Output Low Voltage

VIH

Input High Voltage

2.2

VCC+ 0.5

VIL

Input Low Voltage

-0.5

0.8

III

Input Load Current

±10

OVsVINsVCC

ILO

Output Leakage Current

±10

J-lA

0.45 V s VOUT s VCC

ICC

VCC Supply Current

'rnA

Output Capacitance

Input Capacitance

C10

I/O Capacitance

Clk. Freq ... 5 MHz, 8MHz

fC .. 1.0 MHz, Inputs ... 0 V

AC and OC Characteristics Notes:
1. Typical values are for TA = 25°C, nominal supply voltage, and nominal processing parameters.
2. Input timing parameters assume transition times of 20 ns or less. Waveform measurement points for both input and
output signals are 2.0 V for high and 0.8 V for low, unless otherwise noted.
3. Output loading is 1 TTL gate plus 150 pF capacitance, unless otherwise noted.
4. The net -lOW or -MEMW pulse width for normal write will be TCY -100 ns and for extended write will be
2TCY-100 ns. The net -lOR or -MEMR pulse width for normal read will be 2TCY-50 ns and for compressed read
will be TCY-50 ns.
5. TOO is specified for two different output high levels: T001 is measured at 2.0 V, T002 is measured at 3.3 V. The
value for T002 assumes an external 3.3 Kohm pull-up resistor connected from HRO to VCC.
6. OREO should be held active until OACK is returned.
7. OREO and OACK signals may be active high or active low. Timing diagrams assume the active high mode.
8. Successive read and/or write operations, by the external processor, to program or examine the controller must be
timed to allow at least 400 ns for the VL82C37 A-OS and at least 250 ns for the VL82C37A-08, as recovery time between
active read or write pulses.

9. -EOP is an open-collector output. This parameter assumes the presence of a 2.2 kQ pull-up resistor to VCC.
10. Pin 5 is an input that should always be at a logic high level. An internal pull-up resistor will establish a logic high
when the pin is left floating. It is recommended, however, that pin 5 be tied to VCC.

531

VLSI TECHNOLOGY, INC.

532

VLSI TECHNOLOGY, INC.
VL82C389
MESSAGE-PASSING COPROCESSOR
MULTIBUS® II

FEATURES

DESCRIPTION

• Full-function, single-chip interface to
Parallel System Bus ( iPSB )

The VL82C389 Message-Passing
Coprocessor (MPC) provides a highintegration interface solution for the
Parallel System Bus (iPS B) of the
Multibus II architecture. The device
integrates the logic necessary to
implement a full bus interface solution,
including support for message passing
and interconnect spaces, as well as
memory and I/O references on the iPSB
bus. In addition, the MPC is designed to
simplify implementation of dual-port
memory functions for those designs
that must co-exist with message
passing.

• Implements full message-passing
protocol on iPSB bus
• Offloads managing iPSB bus
arbitration, transfer and exception
cycles from local CPU
• Maximizes performance on iPSB bus
and local on-board bus
• Simplifies highly functional
interconnect space implementations
for both local and iPSB buses
• Processor-independent interface to
iPSB bus
• Supports co-existence of dual-port
and message-passing architectures

The message address space in the
Multibus II architecture has been
defined to provide a high-performance
interprocessor communication mechanism for multiprocessor systems. By
performing the message space interface, the VL82C389 MPC offloads the
interprocessor communication tasks
from the local on-board CPU, which
decouples the local bus activities from

BLOCK DIAGRAM

the iPSB bus activities. Oecoupling
these two functions eliminates an
interface bottleneck present in traditional
dual-port architectures. The bottleneck
is a result of having a dual-port architecture that requires a tight coupling
between a processor and some shared
memory resource of limited size.
Unfortunately, as the number of
processors increases, the dual-port
structure degrades system performance
even more dramatically.
Using the MPC component to decouple
these resources yields several enhancements to system performance. For
example, resources on the local
processor bus and Parallel System Bus
are not held in wait states while arbitration for other resources is performed. In
addition, each transfer can occur at the
full bandwidth of the associated bus.
The benefit of this is the increased
overall system performance that results
from processors being able to process
other tasks in parallel, with message
transfers being handled by the MPC
component.

ORDER INFORMATION
LOCAL BUS INTERFACE

Part
Number
VL82C389-GC

LOCAL BUS
MULTIPLEXING
BUFFERS AND
CONTROL

Package
Ceramic Pin
Grid Array
(PGA)

Note: Operating temperature range is
O°Cto +70°C

Multibus is a registered trademark of Intel Corp.

533

VLSI TECHNOLOGY, INC.
VL82C389

PIN DIAGRAM
CERAMIC PIN GRID ARRAY (PGA)
1

012

014

017

020

023

026

028

030

031

IA07

@148 @145 @143 @141 @138 @134 @133 @129 @125 @126 @121 @120 @118 @115 @111
A5

@147 @144 @142 @139 @136 @135 @128 @124 @122 @119 @116 @114 @110 @107

-BE3
C

@7
-BE2

@12

011

016

013

019

022

025

027

@15

@149 @146 @140 @137 @131 @130 @127 @123 @117 @113 @109 @106 @103

A3
@5

@11

@16

@13

-RO

-WR

@18

@17

MINT -LOCK

@21
EINT

@22

VSS

010

VCC

015

018

021

024

VSS

@23

VCC

@132

@112 @108 @104 @102
IAOO

@26

@27

VSS
@99

@28

@30

@14

@29

@32

@94
TOP VIEW

@19

@98

@96

@97

@95

@93

@91

@92

-BA08 -BA09 -BA010

@20

@88

@87

@90

VSS -BA011-BA012

@25

@84

@85

@89

-BA013-BA014-BA015

@31

@35

-BAOO -BA01

-BA05 -BA06 -BA07

VSS

@34

-IREO

-BA02 -BA03 -BA04

-WAIT

-BSC9 SCOIRO -BSC5

lAST

-IRO

@105 @101 @100

@10

-BSC2 -BSC3 -BSC4

IA02

-IWR

VSS

-BEO

IA01

IA04

-ERR -COM
@24

IA03

VCC

-5EL -BSCO -BSC1
L

IA06

VSS

OOREO -IOACK-OOACK
G

IA05

10REO -MEMSEL -IOSEL
F

029

-REGSEL -BE1
E

@80
VCC
@38
VSS
@39

@82

@86

VCC -BA016-BA017-BA018
@75
-ARBS
@43

@76

@79

@83

VSS -REFAOR VCC

VSS -BPARO VSS -BA027 VSS -BA019-BA020

@47

@57

@51

@56

@62

@65

@71

@74

@81

-BSC6 -BSC7 -ARB1 -ARB3 -ARB4-BREO-BUSERRLACHN-BPAR3-BPAR1-BA030-BA028-BA025-BA023-BA021
P

@33

@36

@41

@42

@45

@48

@50

@54

@60

@61

@64

@67

@69

@72

@78

-BSC8 SCOIR1 -ARBO -ARB2 -RSTNC AODIR TIMOUT BBCLK RESET -BPAR2-BA031-BA029-BA026-BAD24-BA022

@37

@40

@44

@46

@49

@52

@53

@55

@58

@59

@63

@66

@68

@70

@73

FUNCTIONAL DESCRIPTION
Arbitration, Transfer,and Exception
Cycle Protocol Support
The message-passing coprocessor
implements the full arbitration, transfer,
and exception cycle protocols required
to interface to the iPSB bus. Arbitration
is supported for both normal fairness
mode and high priority mode.
The MPC performs the handshake
protocols necessary to successfully
complete iPSB transfer operations.

Transfer operations include access to
memory, 110, message and interconnect
address spaces on the iPSB bus.
During the transfer cycle, the device
generates and checks parity on the
system control (SC) lines and on the
address/data (AD) Hnes. In addition,
the MPC component recognizes agent
errors and bus exceptions that are
reported to the local CPU for recovery
action.

534

INTERFACE DESCRIPTION
This section describes each interface
noted in the block diagram on the front
page. These interfaces include the
local bus, the iPSB bus, the
interconnect bus, and dual-port memory.
The Local Bus Interface
The local bus interface is used to
provide a processor-independent path

VLSI TECHNOLOGY, INC.
VL82C389

from the on-board CPU to the iPSB bus.
This interface supports direct references
(memory, I/O, and interconnect address
spaces) to the iPSB bus, references to
local on-board interconnect space, and
the full protocol for unsolicited and
solicited message operations to and
from the on-board CPU. Within the
MPC component, local bus interface
support consists of three logical
interfaces: register, reference, and
OMA. The register interface is used for
message operations and access to
interconnect address register on-board.
These operations are completed fully
asynchronous to the bus clock or
interconnect bus operations. The
reference interface is used to access
resources asynchronous to the CPU
(local interconnect space and memory, 1/
0, and interconnect address spaces on
the iPSB bus). The OMA interface is
used to transfer data for solicited
message operations. This interface is
designed to allow either two-cycle or
single-cycle transfers. Single-cycle
transfers allow direct transfer of data
between the MPC and memory. To
achieve higher performance via singlecycle transfers, the OMA interface is
optimized for aligned data structures;
however, operation on arbitrary byte
strings is also supported.
IPSB Bus Interface
The iPSB bus interface implements a full
32-bit interface to the iPSB bus. This
implementation includes arbitration,
requestor control, replier control, and
error handling functions. As a requestor, the MPC component supports
references to memory, I/O, and interconnect spaces, as well as message packet
transmission. As a replier, the MPC
supports interconnect space and
message packet reception. In addition,
this interface provides significant
management services for external dual
port memory. These services include:
address recognition, iPSB bus replier
handshake, agent error checking, and
bus parity generation and checking.
Although this device handles the
majority of errors, the dual-port memory
controller is still responsible for generation and checking of memory data parity
(not bus parity).

Interconnect Bus Support
Simply stated, the interconnect address
space provides a physical rather than
logical addressing mechanism for
software initialization and configuration
of system parameters (reduces jumper
configuration) and system-level diagnostics. The interconnect bus provides a
simple a-bit path between the MPC and
a user-defined design for the implementation of interconnect space. All
references to interconnect space (either
from the local bus or the iPSB bus) are
routed through this path for service. In
addition, this interconnect bus can be
used for such non-reference-related
activities as diagnostics. An example of
a highly functional interconnect space
implementation by the microcontroller
implementation of Intel's iSBC 386/100.
Further details of this implementation
are available in the iSBC 386/100
Hardware Reference Manual (Intel order
number: 146705-001).
Dual-Port Memory Support
Although the MULTIBUS II architecture
has defined the message address space
for optimized performance of interprocessor communication, more
traditional designs can use dual-port
memory implementations. The iPSB
bus interface has been defined to allow
co-existence of dual-port memory and
message-passing architectures;
however, it should be noted that the
iPSB bus interface is optimized for
message-passing architectures. The
MPC is designed to support this coexistence. The device can be configured
to recognize a range of addresses in
memory space and act as an iPSB bus
replier when appropriate. If an address
match is detected, the MPC signals the
external dual-port memory controller of
the request. While the MPC provides an
error detection and recovery mechanism
for most agent errors and bus exceptions in a dual-port design, it is still the
responsibility of the dual-port memory
controller to generate and check
memory data parity.
SIngle-Board Computer Configuration
The message passing coprocessor
component provides a processorindependent iPSB bus interface solution
for intelligent SBC boards. Examples
include CPU boards, intelligent peripheral controllers, file servers, intelligent

535

data communications controllers, and
graphicslimage processors. This
component is optimized for bus master
or intelligent slave designs. Using the
MPC reduces overall board real estate
required for the iPSB bus interface. The
MPC improves system reliability by
performing the error checking and
reporting protocols defined in the iPSB
bus interface specification.
Message Support
The MPC provides full support for
unsolicited and solicited messages. For
solicited messages, the MPC supports a
one-message-deep transmit FIFO and a
four-message-deep receive FIFO. For
solicited messages, the MPC supports
one output channel and one input
channel. Each channel has two packet
buffers to allow pipelined operations on
the local and iPSa buses. These
features provide the required level of
support necessary to implement the
high-bandwidth message-passing facility
defined in the Multibus II architecture.
UnsolicHed Message Support
Unsolicited message support in the
MPC is provided on the local bus via a
register interface and on the iPSB bus
with a packet transfer mechanism. An
unsolicited message is initiated by the
sending host CPU transferring a
message to its local MPC. The transfer
is performed as a series of register
operations to the transmit FIFO. An unsolicited message may be from 4 to 32
bytes in length in four-byte increments.
Once the unsolicited message is
transferred to the MPC, the sending
host is free to discard the message in
memory and process another task if it so
chooses. In parallel, the MPC requests
access to the iPSB bus for the pending
transfer. Once the iPSB bus is obtained,
the sending MPC transfers the message, as a single packet, to the receiving agent.
The receiving agent recognizes the
incoming packet by its destination
address field. If the MPC on the
receiving agent detects a match
between its message host 10 and the
destination address field, the packet is
stored in a buffer and checks for error
conditions. Any errors found are
signaled to the sending MPC via the
iPSa bus protocol.

VLSI TECHNOLOGY, INC.
VL82C389

Assuming the packet received is errorfree, the receiving host CPU is informed
of the message via an interrupt signal
generated by the MPC. The host
responds to this interrupt by performing
a series of register operations to
retrieve the message from the receive
FIFO.
If an error occurs during the transfer of
an unsolicited message over the iPSB
bus, the sending MPC takes recovery
action. If the error is a NACK, the MPC
retries the message a predetermined
number of times. All other errors are
reported back to the sending host CPU
for recovery actions. The host CPU is
signaled via an interrupt and can
retrieve the unsolicited message, with
error status, through the error FIFO.
Again, this operation is performed with
a series of register operations.
Solicited Message Support
Solicited message transfers can be
divided into three basic phases: negotiation, data transfer, and completion.
The negotiation phase of the solicited
transfer requires the exchange of two
special unsolicited messages between
the sending and receiving agents. The
buffer request message is transferred
from the sending agent to the receiving
agent and the buffer grant is returned
from the receiving agent to the sending
agent. The MPC supports the transfer
of these messages with the standard
transfer protocol on the iPSB bus as
previously described for the typical
unsolicited message.
A solicited message transfer is initiated
by the sending host CPU writing a
buffer request message to the sending
MPC transmit FIFO. The sending MPC
recognizes the message as a buffer
request and saves the following information. The destination and source
addresses are saved for use in the data
transfer phase. The request 10 is saved
for identification during completion or
cancel operations. The transfer length is
saved to determine the end of transfer
and may contain any number of bytes.

The MPC pads the transfer to an even
four-byte increment on the iPSB bus.
The sending MPC then assigns a
sender liaison 10 and transfers the
buffer request message packet on the
iPSB bus. The sender liaison 10 is used
to bind the buffer grant ( or reject) to its
corresponding buffer request when it is
received back at the sending MPC. This
allows the protocol to be extended to
multiple concurrent transfers in the
future.
The transfer phase is handled by the
sending and receiving MPCs and their
DMA controllers. Neither host CPU is
involved in the transfer, and each may
be processing other tasks during the
transfer. At the sending agent, the
transfer phase slightly overlaps the
negotiation phase. As soon as the
buffer request packet is sent error-free
on the iPSB bus, the sending MPC prefetches up to two packets of data and
prepares for transmission. Upon
receiving the buffer grant and storing
the necessary parameters, the data
packet transfer is initiated. Data packets
are then sent on the iPSB bus using
full-bandwidth block transfers, at
intervals defined by the duty cycle
parameters, until the transfer is complete. The end of transfer is signaled to
the receiving MPC by the last data
packet. A solicited transfer may consist
of from one to 32 packets. Packets are
bound to 32 bytes plus header, with
total transfers limited to 16M bytes.
At the receiving agent, the transfer
phase begins after a buffer grant packet
has been sent error-free on the iPSB
bus. The receiving MPC then detects
data packets, verifies the liaison 10, and
stores the data. If the solicited input
channel is not active (e.g., due to local
cancel) or the liaison 10 does not
match, an agent error is signaled on the
iPSB bus. Errors during the transfer
phase are rare. Flow control using the
duty cycle parameter prevents NACK
problems, and the receiver has responded with a buffer grant guaranteeing its existence and ability to perform

536

the transfer. In the rare case that an
error does occur, the MPC provides a
retry algorithm for NACKs and reports
exceptions or other agent errors
immediately. The error is signaled to
the host CPU by entering the completion phase. Errors generate an interrupt
and provide error status.
The completion phase consists of a
signal from the MPC to its corresponding host CPU. The signal consists of an
interrupt followed by a series of register
operations on the local bus. In all
cases, the completion operation clears
all states associated with the solicited
operation in the MPC, allowing another
operation to be initiated.
The MPC guarantees fail-safe operation
for all aspects of the solicited message
transfer, assuming the bus clock
remains active ( if the bus clock fails, all
transfers cease, eliminating the need
for recovery). This capability is provided
by the error detection and reporting
already discussed for bus-related
problems and by two fail-safe counters
that protect against fatal hardware or
software errors on the sending or
receiving agents. Recovery is provided
to free a solicited message resource
that would otherwise be tied up
indefinitely, which eliminates the need
for a fail-safe software timer.
It is important to note that the fail-safe
counters are not intended for normal
flow control. If a receiving host CPU
accumulates a significant queue of
buffer requests from ~s MPC, ~ should
use unsolicited messages.(and possibly
rejects) to free channels in the system
for other uses. The fail-safe counters
are only intended to replace the need
for a software timer to recover from
otherwise fatal hardware and software
errors.
For a more comprehensive explanation
of the MPC function, please refer to the
Intel document, Multibus II Message
Passing Coprocessor External Product
Specification ( Engineering Document
Number: 149300-001).

VLSI TECHNOLOGY, INC.
VL82C389

SIGNAL DESCRIPTIONS
The MPC signals can be classified into five interface groups: the iPSB bus, the dual-port RAM, the local bus, the interconnect bus
and power/ground. This table describes the individual signals for each of these interfaces.
Signal
Name

Pin
Number

Signal
Description

-BREQ

The bus request is a bidirectional, open-drain signal with high current drive. It connects directly
to the iPSB bus. As an input, it indicates that there are agents awaiting access to the bus. In fair
access mode, this inhibits the MPC from activating its own request. As an output, this signal is
used to request bus access. Further details can be found in the iPSB bus specification.

-ARBO-ARBS

44,41,46,42,
45,43

The arbitration signals are bidirectional, open-drain signals with high current drive. They connect
directly to the iPSB bus.These signals are used during normal operation to identify the mode and
arbitration ID of an agent during arbitration cycles. During system initialization (while reset is
active) , these signals are used to initialize slot and arbitration IDs. Further details are available in
the iPSB , bus specification.

-BADO-BAD31

63, 64, 66-73,
77-83, 85-98

The address/data signals are bidirectional lines that connect to the iPSB bus -AD signals through
74F245 or equivalent transceivers. Further details are available in the iPSB bus specification.
-BAD31

-BAD30

-BAD23

-BAD22

-BAD21

-BAD20

-BAD15

-BAD14

-BAD13

-BAD29

-BAD28

81
-BAD12

-BAD27
71
-BAD19

-BAD26

-BAD25

-BAD18

-BAD17

-BAD24
70
-BAD16

-BAD11

-BAD10

-BAD9

-BAD8

-BAD7

-BAD6

-BAD5

-BAD4

-BAD3

-BAD2

-BAD1

-BADO

-BPARO,
-BPAR1,
-BPAR2,
-BPAR3

62,61,59,60

The byte parity signals are bidirectional lines that connect to the iPSB bus PAR signals through
a 74F245 or equivalent transceiver. These signals are used to receive byte parity for incoming
operations and to drive byte parity for outgoing operations. The MPC is responsible for parity
generation and checking even if the address/data signals are driven from another source (e.g.,
dual-port memory data, address for reference). Further details are available in the iPSB bus
specification.

ADDIR

The AD direction signal is an output used to control the direction of the 74F245 or equivalent
transceivers for the -BADO through -BAD31 and -BPARO through -BPAR3 signals. Activating this
signal drives data to the iPSB bus.

-REFADR 51

The reference address signal is an output from the MPC used to enable external address buffers for
memory and 110 reference operations. Activating this signal drives the reference address onto the
-BAD bus.

SCDIRO,
SCDIR1

32,40

The control/handshake direction signals are outputs used to control the direction of the 74F245 or
equivalent transceivers for the -BSC signals. The SCDIRO signal is used for -BSCO - -BSC3 and
-BSC9. The SCDIR1 signal is used for -BSC4 - -BSC8. Activating these signals drives data to the
iPSB bus.

-BSCO-

27-31,33-37

The control/handshake signals are bidirectional lines that connect to iPSB bus -SC signals through
74F245 or equivalent transcievers. Details on the operation of these signals are available in the
iPSB bus specification.

-BSC~

-BSC9

-BSC8

-BSC7

-BSC6

-BSC5

-BSC4

-BSC3

-BSC2

-BSC1

-BSCO

537

VLSI TECHNOLOGY, INC.
VL82C389

SIGNAL DESCRIPTIONS (Cant.)
Signal
Name

Pin
Number

Signal
Description

BBCLK

The bus clock input signal is a buffered version of the iPSB bus -BCLK signal. It is assumed that a
74AS1804A or equivalent buffer is used. This clock is used for all synchronous internal MPC timing.

TIM OUT

The time-out input signal is used to detect a time out condition signalled by the central services
module (CSM). This signal is connected to the iPSB bus through a 74AS1804A or equivalent buffer.

LACHN

The latch signal is an input used during initialization of slot and arbitration IDs. When the RESET
signal is active, this signal indicates when slot and arbitration IDs are available. This signal is
connected to the iPSB bus through a 74AS1804A or equivalent buffer. Further details on
initialization are available in the iPSB bus specification.

RESET

The RESET signal is an input used to put the MPC in a known state. Only the parts of the MPC
involved with initialization of slot and arbitration IDs remain unaffected. This signal is buffered from
the iPSB bus by a 74AS1804A or equivalent buffer connected to the -RST signal.

-BUSERR 50

The bus error signal is a bidirectional, open-drain line with high current drive. It connects directly
to the iPSB bus. As an input, it is used to detect bus errors signalled by other agents. As an output
it is used to signal parity errors detected on either the -AD or -SC signal lines, handshake protocol
violations, or for extending exception recovery of a replier.

-RSTNC

The reset not complete signal is a bidirectional, open-drain line with high current drive. It connects
directly to the iPSB bus. As an input, this signal inhibits the MPC from initiating iPSB bus
operations. As an output, it is used to prevent iPSB bus operation until an agent is finished with onboard initialization. This signal is activated by the RESET signal going active. It is deactivated by
the microcontroller after the RESET signal is deactivated and initialization is complete.

-SEL

The -SEL signal is activated by the MPC to indicate a dual-port access. This signal is used to
initiate the dual-port operation and may be used to enable the dual-port data buffers onto the BAO·
bus. When the MPC completes the iPSB bus handshake on the iPSB bus, or an exception is
detected, this signal deactivates.

-COM

The -COM signal is activated by the dual-port memory controller to indicate that it is ready to
complete the operation. This signal is assumed to be synchronous with the bus clock. The MPC
activates replier ready on the iPSB bus on the next bus clock. This signal may not be deactivated
until the EOT handshake is complete on the iPSB bus.

-ERR

The -ERR signal is activated by the dual-port memory controller to signal a memory data parity
error. It must be stable at all times when the -COM signal is active. The MPC responds to this
signal by completing the replier handshake on the iPSB bus using a "data error" agent error code.
This signal may be asynchronous with the bus clock since it is qualified by the -COM signal.

DO - 031

114-130, 133139,141-148

The data bus is a bidirectional group of signals used to transfer data between the host CPU and the
MPC. Control is provided to allow operation of this bus with 8-, 16-, or 32-bit processors.

031

030

029

028

027

026

025

024

115

118

114

120

116

121

119

117

023

022

021

020

019

018

017

016

126

122

123

125

124

127

129

128

015

014

013

012

011

010

137

138

139

130

133

135

134

136

141

142

146

143

144

145

147

148

538

VLSI TECHNOLOGY, INC.
VL82C389

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Description

A2,
A3,
A4,
AS

2,S,3,4

The address inputs are used to identify MPC registers for message and interconnect space
operations. Note that AO and A1 are omitted to provide a consistent register address for all databus width options. These signals are qualified by commands (e.g., -RD or -WR) in the MPC and
therefore may "glitch" outside the specified set-up and hold window.

-BEO,
-BE1,
-BE2,
-BE3

6,8,9,7

The byte enable input signals are used to identify the valid bytes and for data path control during
memory and 1/0 reference operations. Only combinations supported by the iPSB bus specification
are valid. These are summarized in the table below. Values not shown are illegal and may result
in unpredictable results. These signals are qualified by commands (e.g., -RO or -WR) in the MPC
and therefore may glitch outside the specified set-up and hold window.
Operation with 32-bit local buses requires all byte enable and data signals to be used. For 16-bit
local buses, the -BE3 and -BE2 signals are held inactive and only 01S-00 are used. For all cases
a read operation enables all 32 data signals, even if all byte enables are inactive. For 8-bit local
bus operations -BE3 is held active, -BE2 is held inactive, -BE1 is connected to -AO, and -BEO is
connected to AO. This mode uses only 07-00.
LOCAL BUS
-BE3

-BE2

-BE1

IPSB BUS

031·
024
V3

023 •
016
V2

015·
08
V1

07·
DO
va

-BEO

AD31· AD23· AD15- AD7·
AD24 AD16 AD8
ADO
V1
Va
V3
V2

x
x
x

L - Electrical low state (active)
H- Electrical high state (inactive)
Vx - Valid data bus

For reference only

-MEMSEL 11

The memory select input signal is used to idenfity a memory reference operation to the iPSB bus.
It is qualified by commands (e.g., -RO or -WR) in the MPC and therefore may glitch outside the
specified set-up and hold window.

-IOSEL

The 110 select input signal is used to identify an 110 reference operation to iPSB bus. It is qualified
by commands (e.g., -AD or -WR) in the MPC and therefore may "glitch" outside the specified setup and hold window.

-REGSEL 12

The register select input signal is used to identify operations to internal MPC registers used to
perform message and interconnect space operations. This signal is qualified by commands (e.g.,
-RD or -WR) in the MPC and therefore may glitch outside the specified set-up and hold window.

-LOCK

The -LOCK signal is an input to the MPC that allows back-to-back operations to be performed on
the iPSB bus or to local interconnect space. When -LOCK is asserted, any resource accessed by
the operation (iPSB bus or local interconnect space) is locked until the -LOCK signal is deacti
vated.

539

VLSI TECHNOLOGY, INC.
VL82C389

SIGNAL DESCRIPTIONS (Cont.)
Signal
Name

Pin
Number

Signal
Description

-RD

The read input signal is activated to initiate a read operation. This signal must provide clean
transitions.

-WR

The write input signal is activated to initiate a write operation. This signal must provide clean
transitions.

-WAIT

The -WAIT signal is driven by the MPC to hold up a transfer operation. This signal is used by the
MPC for all accesses that require synchronization to another resource. When used, it is activated
by a command going active and deactivated when the accessed resource is ready to complete the
requested operation.

MINT

The message interrupt output signal is used for all message-related signalling to the host CPU.
This includes arrival of an unsolicited message, completion of a solicited transfer, and an error on
message transfer.

EINT

The error interrupt output signal is used to signal all errors related to memory, I/O or interconnect
space operations. Internal registers in the MPC provide exact details of the error via interconnect
space. (Even though this is a local bus signal, it will be discussed with the interconnect bus signals
for simplicity in future sections.)

ODREO

The output channel DMA request signal is generated by the MPC to enable DMA transfer of'data
to the MPC (e.g., output to the iPSB bus).

IDREO

The input channel DMA request signal is generated by the MPC to enable DMA transfer of data
from the MPC (e.g., input from the iPSB bus).

-ODACK

The output channel DMA acknowledge input signal is activated to perform a DMA data transfer to
theMPC. It is qualified by commands (e.g., -RD or -WR) in the MPC and therefore may glitch
outside the specified set up and hold window.

-IDACK

The input channel DMA acknowledge input signal is activated to perform a DMA data transfer from
the MPC. It is qualified by commands (e.g., -RD or -WR) in the MPC and therefore may glitch
outside the specified set-up and hold window.

IADO-IAD7 104-111

The interconnect address/data bus is a multiplexed bus designed to directly interface to a
microcontroller. In addition to the MPC, other interconnect registers can be connected to this bus.
IAD7

IAD6

lADS

IAD4

IAD3

IAD2

IAD1

IADO

111

107

110

106

109

104

108

105

-IREO

100

The interconnect request signal is generated by the MPC when an interconnect operation has been
requested either from the local bus or from the iPSB bus. This signal remains active until the
microcontroller performs arbitration.

lAST

101

The interconnect address strobe signal is an input to the MPC used to indicate that a valid address
is on the interconnect bus.This signal may be directly connected to the ALE output of most
microcontrollers. This signal must provide clean transitions.

-IRD

102

The interconnect bus read signal is an input to the MPC. This signal is used to perform a read
operation to one of the MPC interconnect interface registers. This signal must provide clean
transitions. When this signal is activated in conjunction with the -IWR signal, all MPC outputs are
disabled.

-IWR

103

The interconnect bus write signal is an input to the MPC. This signal is used to perform a write
operation to one of the MPC interconnect interface registers. This signal must provide clean
transitions. When this signal is activated in conjunction with the -IRD signal, all MPC outputs are
disabled.

540

VLSI TECHNOLOGY, INC.
VL82C389
TA = ooe to +7o oe, vee = 5 V ±5%

TIMING CHARACTERISTICS
LOCAL BUS
Symbol

Parameter

Min

Address and -BE Set-Up To CommandActive

Max

Units

Test Conditions

T1
Select and DACK Set-Up To Command Active

Address, -BEn, -Select. and -DACK Hold
From Command Active

Command Inactive

Command Inactive To Read Data Disable
(Note 1)

Read Data Hold From Command Inactive

Read Data Enable From Command Active

-WAIT Active From Command Active

Command Inactive From -WAIT Inactive

-WAIT Inactive To Read Data Valid

T10

Command Active To Write Data Valid

T11

Write Data Hold From -WAIT Inactive

T12

Command Active To -LOCK Active (Note 2)

T13

LOCK" Hold From -WAIT Inactive (Note 3)

T14

Command Active

Read Data Valid From Command Active

T16

Write Data Set-Up To
Command Inactive

CL = 50 pF

0
50

200

CL ~ 150 pF

0
100

ns
ns

T15

Registers

DMA

= 150 pF

=50 pF

T17

Write Data Hold From Command Inactive

T18

Command Active To MINT Or -DREQ
Inactive (Notes 4. 5)

T19

Command Active To -DREQ Inactive (Note 5)

CL = 50 pF

FIGURE 3. AC TEST LOAD CIRCUIT

FIG URE 1_ OUTPUT WAVEFORM TEST POINTS

f2.OV\

~ 2.0 V
~0.8V

FIGURE 2. INPUT WAVEFORM TEST POINTS (Nota 6)

2.4V~
2.0 V
2.0 V
0.8 V
0.4 V

1.4 V
0.8 V

Notes:
1. Disable condition occurs when the output current becomes less than the input leakage specification.
2. Required to guarantee locking of resource.
3. Required to guarantee resource remains locked.
4. MINT deassertion only if no other sources are pending.
5. For -DREQ inactive timing. T19 applies to a normal last transfer de-assert condition and T18 to an error de-assert condition.
6. 1.4 V level for BBCLK only.

541

VLSI TECHNOLOGY. INC.
VL82C389

TIMING DIAGRAMS
LOCAL BUS REFERENCE
-BE3 - -BEO
-MEMSEL,
-IOSEL,
-REGSEL,
A5-A2

~-T1

-ROOR-WR

-WAIT

031 - 00
(OUTPUTS OF MPC)
031 - 00
(INPUTS TO
MPC)

......._ - T10

- - t l...

------~------~

I _ _ _-+---::~

T_1_2~~________

_________________
-LOCK

LOCAL BUS REGISTER AND DMA OPERATIONS
-BE3 - -BEa
-REGSEL,
A5-~,

~_ _ _ _ __

-IDACK, -QOACK

14...__________ T14

-------~

-ROOR-WR
1....6..-----T15
031 - 00
(OUTPUTS OF MPC)
031 - 00
(INPUTS TO
MPC)

--~-+-------.,..

.......- - - - T16

MINT,
10REa, OOREa
T18
T19

542

VLSI TECHNOLOGY, INC.
VL82C389

AC CHARACTERISTICS TA =O°C to +70"C, VCC =5 V ±5%
INTERCONNECT BUS
Symbol

Parameter

Min

T31

lAST Active

Max

T32

Command Active

250

T33

Command Inactive To lAST Active

T33A

lAST Inactive To Command Active

120

T34

Address Set-Up To lAST Inactive

T35

Address Hold From lAST Inactive

T36

Write Data Set-Up To Command Inactive

120

T37

Write Data Hold From Command Inactive

T38

Read Data Enable From Commam Active

Units

T39

Read Data Valid From Commam Active

T40

Read Data Hold From Commanc Inactive

T41

Read Data Disable From Comman< Inactive
(Note 1)

T42

EINT, -IREO Inactive From Command Active
(Note 2)

100

120

T31---~

lAST
T32---~

-IRD OR-IWR

IAD7 - IADO
(INPUTS TO
MPC)
IAD7 - IADO
(OUTPUTS
FROM MPC)

ADDRESS VALID

T38

EINT
i'4--- T42--'"

-IREO
~--T42 --I~

Notes:
1. Disable condition occurs when the output current becomes less than the input leakage specification.
2. EINT inactive only on write to error register. -IREO inactive only on write to arbitration register.

543

CL = 150 pF

TIMING DIAGRAM
...- -

Test Conditions

CL= 50 pF

VLSI TECHNOLOGY, INC.
VL82C389

TIMING CHARACTERISTICS TA =O°C to +70°C, VCC =5 V ±5%
IPSB BUS
.

Symbol

Min

Parameter

Max

Units

Test Conditions

TCP

Clock Period

99.9

TCL

-BCLK Low Time

TCH

-BCLK High Time

TBCL

BBCLK Low Time

TBCH

BBCLK High Time

TRB

-BCLK Rise Time

1.0

5.0

TFB

-BCLK Fall Time

1.0

2.0

BBCLK Rise Time

0.5

1.0

BBCLK Fall Time

0.5

1.0

TSK

-BCLK To BBCLK Skew ( Note 1 )

-{l.5

4.0

-BREQ, -BUSERR,
-RSTNC ( Note 2 )

CL = 500 pF

TCD

Clock To
Output Delay

-ARBS - -ARBO (Note 2,3)

CL = 500 pF

-BSC7 - -BSCO,
-BAD31--BADO

CL=75 pF

-BPAR3 - -BPARO,
-BSC9, -BSC8

CL= 50 pF

High To Low

CL=25 pF

SCDIRO,
SCDIR1

Low To High

CL=25 pF

High To Low

CL= 50 pF

Low To High

CL= 50 pF

-REFADR

CL= 75 pF

-SEL

CL .. 50 pF

ADDIR

Hold Time
From Clock

-BREQ,-BUSERR,-RSTNC

6.5

-ARBS - -ARBO ( Note 3 )

6.5

-BAD31 - -BADO,
-BPAR3 - -BPARO

5.0

-BSC9--BSCO

4.0

SCDIRO, SCDIR1

4.0

ADDIR

5.0

-REFADR

4.0

-SEL

4.0

Notes:
1. These clock timings refer the MPC specification to the iPSB bus specifications. They assume a 74AS1804 type buffer is used.
2. The 500 pF load is a distributed value as defined in the iPSB bus specification. The open-drain signals are designed such that
the output delay and bus loss meets the iPSB specification requirement. An appropriate test condition that correlates to the
distributed load will be determined during characterization.
3. The -ARBS - -ARBO signal timings are with respect to the first and last clock of the arbitration period. Details are in the
iPSB bus specification. Also, the arbitration logic has been designed to meet the loop delay specification accounting for the
full path of input to output plus bus loss. An appropriate test condition will be determined during device characterization.

544

VLSI TECHNOLOGY, INC.
VL82C389

TIMING CHARACTERISTICS TA =O°C to +70°C, VCC =5 V ±5%
IPSB BUS (Cont.)
Symbol

TON

TOFF

Parameter

Turn On Delay
From Clock
( Note4)

Turn Off Delay
From Clock
( Note 5)

Min
-BREO,-BUSERR,-RSTNC
-ARB5 - -ARBO (Note1)

6.5

-BAD31 - -BADO,
-BPAR3--BPARO

5.0

-BSC9 - -BSCO

4.0
36

-ARB5 - -ARBO (Note 3)

-BAD31 - -BADO,
-BPAR3 - -BPARO

-BREO,-BUSERR,-RSTNC

TSU

TIH

Input Hold
From Clock

-BREO,-BUSERR,-RSTNC

Test Conditions

Units
ns

-BSC9 - -BSCO

Input Set-Up
To Clock

Max

6.5

-ARB5 - -ARBO (Note 3)

-BAD31 - -BADO,
-BPAR3--BPARO

-BSC9--BSCO

TIMOUT, LACHN, RESET

-COM,-ERR

-BREO,-BUSERR,-RSTNC

-ARB5 - -ARBO (Note 3)

-BAD31--BADO
-BPAR3--8PARO

-BSC9 - -BSCO

TIMOUT, LACHN, RESET

-COM,-ERR

TIMING DIAGRAM
IPSBBUS

~~T~

& -_ _ _ _ _ _ _ _ __ _

TF
BBCLK _ _ _ _--'

Other Source

OUTPUTS

1'4------- Tep

--------t~

INPUTS

Notes:
4. Minimum turn-on times are measured the same way as hold times. Specifically, the logic level driven by another device on the
previous clock cycle must not be disturbed.
5. Maximum turn-off times are measured to the condition where the output leakage current becomes less than the input leakage
specification.

545

VLSI TECHNOLOGY, INC.
VL82C389

ABSOLUTE MAXIMUM

RATINGS

Ambient Operating
Temperature
Storage Temperature

-65°C to +150°C

Supply Voltage to
Ground Potential

-0.5 V to +7.0 V

Applied Output
Voltage

-0.3 V to VCC +0.5 V

Applied Input
Voltage

-0.5 V to VCC +0.5 V

DC CHARACTERISTICS TA
Symbol

Parameter

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low
Voltage

VOH

Output High Voltage

III

Input Leakage
Current

Stresses above those listed may cause
permanent damage to the device. These
are stress ratings only. and operation of
this device at these or other conditions
above those indicated in this data

=0 C to + 70 C, VCC =5 V

5%
Min

IOL

IOH

Output High Current

ICC

Operating Supply Current

Units

-0.5

0.8

2.0

VCC +0.5

0.55

IOLMax

Open Drain
All Others

0.45
2.4

IOL Max

IOH Max

Open Drain

±400

OsVINSVCC

BBCLK

± 100

OsVIN sVCC

±16

OSVIN SVCC

Open Drain

60.0

VOL .. 0.55 V

ADDIR and
-REFADR

8.0

VOL. 0.45 V

4.0

VOL .. 0.45 V

All Others

CAPACITANCETA

Test Conditions

Max

All Others

Output Low
Current

sheet is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device
reliablity.

-1.0

VOH -2.4 V
400

= 25 C, fC =1 MHz (Note 1)

Symbol

Parameter

Input Capacitance

Min.

Max.

Units

BBCLK

All Others

CIO

VO Capacitance

COC

Output Capacitance

Nota:
1. Periodically sampled rather than1 00% tested.

546

Test Conditions

VLSI TECHNOLOGY, INC.
VL82C59A
PROGRAMMABLE INTERRUPT CONTROLLER

FEATURES

DESCRIPTION

• Compatible with 8086, 8088, and
similar microprocessors

The VL82C59A Programmable Interrupt
Controller can manage up to eight
vectored priority interrupts for the
system's CPU. It can be cascaded to
handle up to 64 interrupts. No additional
circuitry is required.

The VL82C59A is fully upward compatible with the HMOS 8259 or 8259A.
Software originally written for the HMOS
8259 or 8259A will operate the
VL82C59A in all 8259 or 8259A
equivalent modes.
The VL82C59A is housed in a 28-pin
DIP, uses CMOS technology and
requires a single 5 V supply. The circuit
is totally static, requiring no clock input.

• 28-pin DIP Package

The VL82C59A has been designed to
relieve the software of the burden of
handling multi-level priority interrupts. It
controls several modes, permitting
optimization for a large number of
system needs.

PIN DIAGRAM

BLOCK DIAGRAM

• Low power consuming CMOS
• Interrupt modes are programmable
• Minimizes software overhead
• Eight prioritized control levels
• 64 levels of expand ability
• Single 5 V power supply

INT

-INTA

VL82C59A

DATA
BUS
BUFFER

VCC

-Cs
-WR

-RD

-INTA

IR7

IR6

IRS

IR4

IR3

IR2

IR1

IRO
IR1-+ INTERRUPT
1R2-+ REQUEST
IR3-+
REG
IR4-+
(IRR)
IRS - - .
IR6-+
IR7-+

IRO

CASO

INT

CAS1

-SP/-EN

-flO
-WR
AD
1 - -_ _ _

. - . CASO

+-+ CAS1
COMPARATOR +-+ CAS2
INTERNAL BUS
L...-_ _+

-RD
07

I-WR

-CS

~~~~~~

CAS2

GND

00-07

-SP/-EN

AD
VCC

-INTA

ORDER INFORMATION
06
05
04
03
02
01

IR7
IR6
IRS
IR4
IR3
IR2
IR1

Part
Number

Bus
Speed

Package
Plastic DIP

VL82C59A-08PC
VL82C59A-OSOC
VLS2C59A-OSCC

S MHz

VL82C59A-10PC
VLS2C59A-100C
VLS2C59A-10CC

10 MHz

Plastic Leaded Chip Carrier (PLCC)
Ceramic DIP
Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
Ceramic DIP

Note: Operating temperature range is O°C to +70°C.

547

VLSI TECHNOLOGY, INC.
VL82C59A

SIGNAL DESCRIPTIONS
Signal
Name

Pin
Number

Signal
Type

Signal
Description
Chip Select - A Iowan -CS enables -RD and -WR communication
between the CPU and the VL82C59A INTA functions are independent of
-CS.

-CS

Write - A Iowan -WR when -C~ is low enables the VL82C59A to accept
command words from the CPU.

-WR

-RD

DO-D7

11-4

110

Bidirectional Data Bus - Control, status, and interrupt-vector information is
transferred by this bus.

CASO-CAS2

12, 13, 15

110

Cascade Lines - The CAS lines form a unique VL82C59A bus to control a
multiple VL82C59A configuration. These pins are outputs for a master
VL82C59A and inputs for a slave VL82C59A.

-SP/-EN

110

Slave Program/Enable Buffer - The -SP/-EN pin provides a dual function.
When in the Buffered Mode, it can be used as an output to control the
buffer transceivers (EN). When not in the buffered mode, it is used as an
input to designate a master (SP = 1) or a slave (SP = 0).

INT

Interrupt - The INT pin goes high whenever a valid interrupt request is
present. It is used to interrupt the CPU and is connected to the CPU's
interrupt pin.

IRO-IR7

18-25

Interrupt Requests - Asynchronous inputs. An interrupt request is executed
by raising an IR input (low to high) and holding it high until it is acknowledged (Edge Triggered Mode), by a high level on an IR input (Level
Triggered Mode).

-INTA

Interrupt Acknowledge - The -INTA pin is used to enable the VL82C59A's
interrupt-vector data onto the data bus by a sequence of interrupt acknowledge pulses issued from the CPU.

AO Address Line - The AO pin acts together with the -CS, -WR, and -RD
pins. It is used by the VL82C59A to decode various Command words the
CPU writes and status the CPU needs to read. It is typically connected to
the CPU AO address line (A 1 on the iAPX86, 88).

VCC

+5 V Supply

GND

Ground

Read - A Iowan -RD when -CS is low enables the VL82C59A to release
status onto the data bus for the CPU.

548

VLSI TECHNOLOGY. INC.
VL82C59A

FUNCTIONAL DESCRIPTION
The VL82CS9A has been designed to
be used in real-time, interrupt-driven
microcomputer systems. It controls
eight levels or requests, and has a builtin feature for expand ability to other
,VL82CS9A's (up to 64 levels). It is
programmed by the system's software
as an I/O peripheral. A selection of
priority modes are usable by the programmer so that the way in which the
requests are handled by the VL82CS9A
can be configured to match the system
requirements. The priority modes can
be changed at any time during the main
program. The entire interrupt structure
can be defined as needed, based on
the total system requirements.
Interrupt Request Register (IRR) and InService Register (ISR) - The interrupts
at the IR input lines are handled by two
registers in cascade, the Interrupt
Request Register (IRR) and the InService Register (ISR). The IRR stores
all the interrupt levels which are
requesting service, and the ISR stores
all of the interrupt levels which are
being handled.
Priority Resolver - This logic block sets
the priorities of the bits set in the IRR.
The highest priority is selected and
strobed into the corresponding bit of the
ISR during the -INTA pulse.
Interrupt Mask Register (IMR) - The
IMR holds the bits which mask the
interrupt lines. The IMR changes the
IRR. Masking of a higher priority input
will not affect the interrupt request lines
of a lower priority.
Interrupt (INT) - This output interfaces
to the CPU interrupt input. The VOH
level on this line has been designed to
be fully compatible with the 8080A,
808SA and 8086 input levels.
Interrupt Acknowledge (-INTA) - The
-INTA pulses will cause the VL82CS9A
to release vectoring information onto
the data bus. The format of this data
depends on the system mode of the
VL82CS9A.
Data Bus Buffer- This three-state, bidirectional 8-bit buffer is used to interface
the VL82CS9A to the system Data Bus.
Control words and status information
are transferred through the Data Bus
Buffer.

ReadtWrite Control Logic - The purpose
of this block is to accept output commands from the CPU. It contains the
Initialization Command Word (ICW)
registers and Operation Command
Word (OCW) registers. They store the
various control formats for device
operation. This function block also
permits the status of the VL82CS9A to
be transferred onto the Data Bus.
Chip Select (-CS) - A Iowan this input
enables the VL82CS9A. Reading or
writing of the chip will not occur unless
the device is selected.
Write (-WR) - A Iowan this input
permits the CPU to write control words
(ICWs and OCWs) to the VL82CS9A.
Read (-RD) - A Iowan this input
enables the VL82C59A to transmit the
status of the Interrupt Request Register
(IRR), In-Service Register (ISR), the
Interrupt Mask Register (IMR), or the
interrupt level to the Data bus.
Cascade Buffer/Comparator - This
function block stores and compares the
identities of all VL82C59A's used in the
system. The three I/O pins (CASOCAS2) are outputs when the VL82CS9A
functions as a master and are inputs
when the VL82C59A functions as a
slave. As a master, the VL82C59A
sends the identity of the interrupting
slave device onto the CASO-CAS2
lines. The slave selected can now send
its preprogrammed address to the Data
Bus during the next consecutive -INTA
pulses.
Interrupt Sequence - Interrupt routine
addressing is a very important aspect of
VL82CS9A operation, as is device
programmability. Interrupt routine
addressing permits direct or indirect
jumping to the specific interrupt routine
requested with no polling of the interrupting devices. The activities occurring
during an interrupt depends on the type
of CPU being used.
The events occur as shown below in an
MCS 80/85 system:
1. Interrupt Request lines (IRO-IR7) are
raised high, setting the corresponding IRR bit(s).
2. The VL82CS9A evaluates these

549

requests, then sends an INT to the'
CPU, if necessary.
3. The CPU acknowledges the INT and
responds with the -INTA pulse.
4. When receiving an -INTA from the
CPU group, the highest priority ISR
bit is asserted, and the proper IRR
bit is reset. The VL82C59A will also
send a CALL instruction code
(11001101) to the 8-bit Data Bus
through its 00-07 pins.
5. The CALL instruction will initiate two
additional -INTA pulses which will
be sent to the VL82C59A from the
CPU group.
6. The two -INTA pulses permit the
VL82C59A to send its pre programmed subroutine address to the
Data Bus. The lower 8-bit address
is sent at the first -INTA pulse and
the higher 8-bit address is sent at
the next -INTA pulse.
7. The 3-byte CALL instruction sent by
the VLB2CS9A is then completed. In
the AEOI mode, the ISR bit is reset
at the end of the third -INTA pulse.
If not, the ISR bit remains set until
an appropriate EOI command is
issued at the end of the interrupt
sequence.
The sequence of events occurring in an
iAPX86-type system are the same until
step 4. The sequence then continues:
4. When receiving an -INTA from the
CPU group, the highest priority ISR
bit is set and the corresponding IRR
bit is reset. The VL82CS9A does
not use the Data Bus during this
cycle.
S. The iAPX 86/10 will send a second
-INTA pulse. During this second
pulse, the VL82CS9A releases an 8bit pointer to the Data Bus and it is
read by the CPU.
6. The interrupt cycle is then complete.
In the AEOI mode the ISR bit is
reset at the end of the second
-INTA pUlse. If not, the ISR bit
remains set until a valid EOI command is sent at the end of the
interrupt subroutine.
If there is no interrupt request present at
step 4 of either sequence (Le., the

VLSI TECHNOLOGY, INC.
VL82C59A

request duration was too short) the
VL82C59A will send an interrupt level 7.
Both the vectoring bytes and the CAS
lines will appear as though an interrupt
level 7 was requested.

During the third INTA pulse, the higher
address of the correct service routineprogrammed as byte 2 of the initialization sequence (address lines A8-A 1S)is enabled to the bus.

INTERRUPT SEQUENCE OUTPUTS
FOR MCS-80~ & MCS-85~
This sequence is timed by three -INTA
pulses. During the first -INTA pulse the
CALL opcode is enabled onto the Data
Bus.

CONTENT OF THIRD INTERRUPT
VECTOR BYTE

CONTENTS OF FIRST INTERRUPT
VECTOR BYTE
CALL
07 06 05 04 03 02 01 00
OPCOOE 11 1 1 0 0 1 1 0
1

I I I I I I I

During the second -INTA pulse the
lower address of the selected service
routine is enabled to the data bus.
When the interval = 4 address bits ASA7 are programmed, while addresses
AO-A4 are automatically inserted by the
VL82C59A. When interval ... 8 only A6
and A7 are programmed, while AO-A5
are automatically inserted.
CONTENT OF SECOND INTERRUPT
VECTOR BYTE
Interval = 4
07 06 05 04 03 02 01 00
7 A7 A6 AS 1 1 1 0 0
6 A7 A6 AS 1 1 0 0 0
5 A7 A6 AS 1 0 1 0 0
4 A7 A6 AS 1 0 0 0 0
3 A7 A6 AS 0 1 1 0 0
2 A7 A6 AS 0 1 0 0 0
1 A7 A6 AS 0 0 1 0 0
0 A7 A6 AS 0 0 0 0 0
IR

Interval = 8
06 OS 04 03 02 01 00
7
A6 1 1 1 0 0 0
A6 1 1 0 0 0 0
6
A6 1 0 1 0 0 0
S
4
A6 1 0 0 0 0 0
A6 0 1 1 0 0 0
3
2 A7 A6 0 1 0 0 0 0
1 A7 A6 0 0 1 0 0 0
0 A7 A6 0 0 0 0 0 0

07
A7
A7
A7
A7
A7

07 06 OS 04 03 02 01

IA1SIA141A131A121A11IA101 A91ASI
INTERRUPT SEQUENCE OUTPUTS
FOR IAPX86D & IAPX8fP>
iAPX 86 mode is the same as the MCS80 mode, with the exception that only
two interrupt acknowledge cycles are
issued by the processor and no CALL
opcode is sent to the processor. The
first interrupt acknowledge cycle is like
that of MCS-80, 85 systems in that the
VL82C59A uses it to internally hold the
state of the interrupts for priority
resolution. As a master, it issues the
interrupt code on the cascade lines at
the termination of the INTA pulse. On
this first cycle, it does not send any data
to the processor. It leaves its Data Bus
buffers disabled. On the second
interrupt acknowledge cycle (in iAPX86
and iAPX88 modes) the master (or
slave) will send a byte of data to the
processor with the acknowledged
interrupt code as follows (The state of
the ADI mode control is ignored and
address lines AS-A 11 are unused in
iAPX86 and iAPX88 mode.):

1. Initialization Command Words
(ICWs): Before normal operation
begins, each VL82C59A in the
system should be brought to a
starting point. This is done by a sequence of 2 to 4 bytes timed by -WR
pulses.
2. Operation Command Words
(OCWs): OCWs are the command
words which command the
VL82C59A to operate in various
interrupt modes. These modes are:
A. Fully nested mode
B. Rotating priority mode
C. Special mask mode
D. Polled mode
The OCWs may be written into the
VL82C59A anytime following initialization.
Initialization Command Words (ICWS) When a command is issued with
address line AD = 0 and D4 = 1, this is
decoded as Initialization Command
Word 1 (ICW1). ICW1 commences the
initialization sequence during which the
following occurs:
A. The edge sense circuit is reset.
Following initialization, an interrupt
request (IR) input should make a
low-to-high transition to generate an
interrupt.
B. The Interrupt Mask Register is
cleared.
C. IR7 input is assigned priority 7.

CONTENT OF INTERRUPT VECTOR
BYTE FOR iAPX86, iAPX88
SYSTEM MODE

D. The slave mode address is set to 7.

04
T4
T4
T4
T4
T4
T4
T4
T4

F. If IC4 '" 0, all functions that were
selected in ICW4 are set to zero.
(Non-Buffered mode, no Auto-EOI,
MCS-80 and MCS-85 system.
Master/Slave in ICW4 is only used in
the buffered mode.)

IR7
IR6
IRS
IR4
IR3
IR2
IR1
IRO

07 06
T7 T6
T7 T6
T7 T6
T7 T6
T7 T6
T7 T6
T7 T6
T7 T6

OS
TS
TS
TS
TS
TS
TS
TS
TS

03 02 01 DO
T3 1 1 1
T3 1 1 0
T3 1 0 1
T3 1 0 0
T3 0 1 1
T3 0 1 0
T3 0 0 1
T3 0 0 0

PROGRAMMING
The VL82C59A uses two types of command words generated by the CPU:

SSO

E. Special Mask Mode is cleared and
Status Read is set to IRR.

Initialization Command Words 1 and 2
(ICW1, ICW2) - AS-A1S: Page starting
address of service routines. In an
MCS80IMCS8S system, all eight
request levels will generate CALLs to
eight locations equally separated in
memory. These can be programmed to
be separated at intervals of four or eight
memory locations. The eight routines

VLSI TECHNOLOGY, INC.
VL82C59A

will then occupy a page of 32 or 64
bytes, respectively.
The address format is 2 bytes in length
(AO-A 15). When the routine interval is
4, AO-A4 are inserted by the
VL82C59A, while A5-A15 are externally
programmed. When the routine interval
is 8, AO-A5 are inserted by the
VL82C59A, while A6-A 15 are externally
programmed.
The 8-byte interval will maintain
compatibility with software presently
being used, while 4-byte interval should
be used for a small jump table.
In an iAPX86 and iAPX88 system
address lines A 15-A 11 are inserted in
the five most significant bits of the
vectoring byte and the VL82C59A sets
the three least significant bits in
accordance with the interrupt level.
A 10-A5 are ignored and ADI (Address
Interval) is not used.
LTIM: If LTIM .. 1, the VL82C59A will
operate in the level interrupt mode.
Edge detection logic on the interrupt
inputs will be disabled.
ADI: CALL address interval. ADI = 1
then interval .. 4; ADI = 0 then interval =

8.
SNGL: Single. This indicates that only
one VL82C59A is in the system. If
SNGL CI 1 no ICW3 will be issued.
IC4: If this bit is set, ICW4 must be
read. If ICW4 is not used, set IC4 .. O.
Initialization Command Word 3 (ICW3) This word indicates that there is more
than one VL82C59A in the system and
cascading is used (SNGL .. O). It will
load the 8-bit slave register. The
functions of this register are below:
A. In the master mode (either when SP
.. 1, or in buffered mode when MIS =
1 in ICW4) a "1" is set for every
slave in the system. The master will
release byte 1 of the CALL sequence (for MCS80/MCS85 system)
and will then enable the corresponding slave to release bytes 2 and 3
(for iAPX86, iAPX88 only byte 2)
through the cascade lines.
B. In the slave mode (either when -SP
.. 0, or if BUF .. 1 and MIS .. 0 in
ICW4) bits 2-0 identify the slave.

The slave compares its cascade
input with these bits. If they are
equal, bytes 2 and 3 of the CALL sequence (or just byte 2 of iAPX86,
iAPX88) are released by it on the
Data Bus.
Initialization Command Word (ICW4) SFNM: If SFNM .. 1, the special fully
nested mode is programmed.
BUF: If BUF .. 1, then the buffered
mode is programmed. In buffered
mode -SP/-EN becomes an enable
output and the masterlslave selection is
made by MIS.
MIS: MIS .. 1 indicates the VL82C59A
is a master, MIS = 0 indicates the
VL82C59A is a slave. If BUF .. 0, MIS
has no meaning.
AEOI: If AEOI .. 1, then the automatic
end of interrupt mode is programmed.
Microprocessor mode: jlPM = 0 sets
the VL82C59A for MCS80, MCS85
system operation. jlPM = 1 sets the
VL82C59A for iAPX86 system operation.
Operation Command Words (OCWs) After the initialization Command Words
(ICWs) are programmed into the
VL82C59A, the chip is prepared to
accept interrupt requests on its inputs.
During VL82C59A operation, a selection of algorithms can command the
VL82C59A to operate in different
modes through the Operation Command Words (OCWs).

Operation Control Word 2 (OCW2) - R,
SL, EOI - These three bits control the
Rotate and End of Interrupt modes and
their combinations. A drawing of these
combinations can be found on the
Operation Command Word Format,
Figure 3.
L2, L 1, LO - These bits determine the
interrupt level responded to when the
SL bit is active.
Operation Control Word 3 (OCW3)
ESMM - Enable Special Mask Mode.
When this bit is set to 1 it enables the
SMM bit to set or reset the Special
Mask Mode. When ESMM .. 0 the
SMM bit is a "don't care".
SMM - Special Mask Mode. If ESMM ..
1 and SMM .. 1 the VL82C59A will
enter Special Mask Mode. If ESMM .. 1
and SMM .. 0 the VL82C59A will revert
to normal mask mode. When ESMM
0, SMM is not used.

FIGURE 1. INITIALIZATION
SEQUENCE

NO(SNGL_1)

OPERATING CONTROL WORDS
(OCWs)
AO

OCW1
07 06 05 04 03

02 01

[!] IM71 Mal MSI M4/ M3/ M2/ M1/ MOl
AO

@]
AO

OCW2
07 OS 05 04 03 02
I R I SL / Eet! 0 / 0 / L2

01 DO

I L 1 ILO 1

OCW3
04 03 02 01

@] 10 IESSMlsMMI 011 I pi RR IRlsl

Operation Control Word (OCW1) OCW1 sets and clears the mask bits in
the interrupt Mask Register (IMR). M7MO control the eight mask bits. M .. 1
indicates the channel is masked, M = 0
indicates the channel is enabled.

551

NO (IC4-0)

VLSI TECHNOLOGY, INC.
VL82C59A

FIGURE 2. INITIALIZATION COMMAND WORD FORMAT
ICW1

ICW4 needed

'"---l.-rl.-r......r'"'---""--r...L...-T....L..-T-'---c:=--_ _-.i 0 No ICW4 needed
'--------..t

1 = Single
0 = Cascade mode
CALL ADDRESS INTERVAL
1 = Interval of 4
o= Interval of 8

L.-_ _ _ _ _ _ _ _ _~~I

1 = Level triggered mode

o= Edge triggered mode
A7 through A5 of
'------------------~ interrupt vector address

(MCS-80, 85 mode only)

ICW2
AO

DO
A 15 through A8 of
interrupt vector address
(MCS-80, 85 mode)
T 7 through T 3 of
interrupt vector address
(8086,8088 mode)

ICW3 ( MASTER DEVICE)
AO

'--_.L-_....L..-_-'-_-L-_---L._.......Ii..--.......Ii..--_ _ _~

1 IR input has a slave
0 IR input does not have a slave

, 102 , 101 ,100

SLAVE 10

0 1 2 3 4 567

a1
100
a
1
• a
.. a a a a 1 1
.. 0 1 0 1

0 1
1 1
1 1

ICW4

1 = 8086. 8088 mode

'-----~ 0= MCS-80, 85 mode

Auto EOI
Normal EOI

m
x

Non-buffered mode
Buffered mode slave
Buffered mode master

'--_ _ _ _ _ _ _ _ _ _ _ _~ 1 = Special fully nested mode
0= Not special fully nested mode
Note: Slave 10 is equal to the corresponding master IR input.

552

VLSI TECHNOLOGY, INC.
VL82C59A

FIGURE 3. OPERATION COMMAND WORD FORMAT

OCW1
04
03

L....----'_--L_--L_-'-_...L._...L.._..&...._ _~

INTERRUPT MASK
1 = Mask set
o = Mask reset

OCW2
AO

EOI

I I I I I I I I I I
I

I
l

IR LEVEL TO 'BE ACTED UPON

~-O ~

ro 11
--

I1 0 1
I1 0 0
I-

-o0 0

I- -I1 1 1

Specific EOI command

End of interrupt

Rotate in automatic EOI mode (set)

} - Automatic rotation

Rotate In automatic EOI mode (dear)

J-

*Rotate on specific EOI command
*Set priority command

No operation

1 0

Rotate on non-specific EOI command

1 1 0

'---'--

J--

Non-specific EOI command

I- -II- -I-

Specific rotation

*L 0 - L 2 are used.

oeW3
AO
I

0 I 0 IESMMISMMI 0

I RR I RISI

L....

READ REGISTER COMMAND

0
0

I
I

No Action

ReadlR
Reg on
next-RD
pulse

Read IS
Reg on
next-RD
pulse

1 = Poll command

o = No poll command

SPECIAL MASK MODE

0
0

I
I

Reset
special
mask

Set
special
mask

No Action

553

VLSI TECHNOLOGY, INC.

MODES
Fully Nested Mode - This is the default
mode after initialization unless another
mode is programmed. The interrupt
requests are ordered in priority from 0
through 7 (0 highest). When an
interrupt is acknowledged, the highest
priority request is decoded and its
vector placed onto the bus. A bit of the
Interrupt Service register (ISO-IS7) is
also set. This bit stays set until the
microprocessor issues an End of
Interrupt (EOI) command before
returning from the service routine. It
also stays set if the AEOI (Automatic
End of Interrupt) bit is set, until the
trailing edge of the last INTA. While the
In-Service (IS) bit is set, all further
interrupts of the same or lower priority
are disabled. Higher levels will generate an interrupt.
After the initialization sequence, IRO
has the highest priority and IR7 the
lowest. Priorities may be be changed
in the rotating priority mode.
End of Interrupt (EO 1)- The In-Service
(IS) bit may be reset either automatically following the trailing edge of the
last in sequence -INTA pulse (when
AEOI bit in ICW1 is set), or by a
command word that should be issued to
the VL82C59A before returning from a
service routine (EOI command). An
EOI command is issued twice if in the
Cascade mode, once for the master
and once for the corresponding slave.
Two forms of an EOI command are
used; Specific and Non-Specific.
When the VL82C59A is operated in
modes which maintain the fully nested
structure, it can determine which IS bit
to reset on EOI. When a Non-Specific
EOI command is sent the VL82C59A
will reset the highest IS bit of those that
are set. In the fully nested mode the
highest IS level was necessarily the last
level operated upon. A Non-Specific
EOI can be sent with OCW2 (EOI = 1,
SL = 0, R = 0).
When a mode may change the fully
nested structure, the VL82C59A may
not be able to determine the last level
responded to. A Specific End of
Interrupt must then be issued, which
includes IS level to be reset as part of
the command. A Specific EOI can be
sent with OCW2 (EOI = 1 , SL = 1, R =

VL82C59A
0, and LO-L2 is the binary level of the IS
bit to be reset).

bottom priority device, then IR6 will be
the highest one).

When the IS is masked by an IMR bit, it
will not be cleared by a Non-Specific
EOI, if the VL82C59A is in the Special
Mask Mode.

The Set Priority command is issued in
OCW2 where: R - 1, SL .. 1; LO-L2 is
the binary priority level code of the
bottom priority device.

Automatic End of Interrupt (AEOI) Mode
- If AEOI = 1 in ICW4, then the
VL82C59A will operate in AEOI mode
until changed by ICW4. In this mode,
the VL82C59A will perform a NonSpecific EOI operation at the trailing
edge of the last interrupt acknowledge
pulse. This mode should be used only
when a nested multilevel interrupt
structure is not required in a single
VL82C59A.

In this mode internal status is updated
by software control during OCW2. It is
independent of the End of Interrupt
(EO I) command. Priority changes may
be performed during an EOI command
by using the Rotate on Specific EOI
command in OCW2 (R = 1, SL = 1, EOI
= 1, and LO-L2 = IR level to receive
bottom priority).

The AEOI mode can only be used in a
master VL82C59A.
Automatic Rotation (Equal Priority
Devices) - In many applications there
are several interrupting devices of equal
priority. In this mode the device
receives the lowest priority. A device
requesting an interrupt will wait, in the
worst case, until each of seven other
devices with higher priority are serviced.
If the priority and "in service" status is:
Before Rotate (IR4 the highest priorityrequiring service)
"IS·
Status

IS7 IS6

I0 I

ISS IS4 IS3 IS2 IS1

I0 I

Lowest Priority

.. I
S~~~

I5 I

ISO

I0 I0 I

Highest Priority
4

' to I

After Rotate (IR4 was serviced):
"IS.
Status

IS7 IS6

I0 I

ISS 154 153 IS2 151

Special Mask Mode· Some applications
will require an interrupt service routine
to change the system priorities during
its execution under program control.
The routine may need to inhibit lower
priority requests for a portion of its
execution, but enable some, for another
portion.
If an Interrupt Request is acknowledged
and an End of Interrupt command did
not reset the IS bit during a service
routine, the VL82C59A will inhibit all
lower priority requests without a simple
routine to enable them.

ISO

I 0 I 0 I 0 I 0 I0 I 0 I

There are two ways to accomplish
Automatic Rotation using OCW2, the
Rotation on Non-Specific EOI Command ( R '" 1, SL = 0, EOI = 1) and the
Rotate in Automatic EOI Mode which is
set by (R = 1, SL = 0, EOI = 0) and
cleared by (R = 0, SL = 0, EOI = 0).
Specific Rotation (Specific Priority) The programmer may change priorities
by programming the bottom priority and
thereby fixing all of the other priorities
(e.g., if IR5 is programmed as the

554

Interrupt Masks - Each Interrupt
Request input may be masked individually by the Interrupt Mask Register
,(IMR) by programming OCW1. Each bit
in the IMR masks one interrupt channel
when it is set (1). Bit 0 masks IRO, bit 1
masks IR1, etc. Masking an IR channel
has no affect on the other channels
operation.

In the Special Mask Mode, a mask bit
set in OCW1 inhibits further interrupts at
that level and enables interrupts from all
other levels that are not masked.
Any interrupts may be enabled selectively by loading the mask register.
The Special Mask Mode is set by
OCW3 when: SSMM = 1, SMM '" 1,
and cleared where SSMM = 1, SMM =

O.
Poll Command - In this mode the INT
output is disabled or the microprocessor
internal Interrupt Enable flip-flop is
reset, disabling its interrupt input.
Service to devices is programmed by
software using a Poll command.

VLSI TECHNOLOGY, INC.
VL82C59A

The Poll command is issued by setting
P ="1" in OCW3. The VL82C59A
treats the next -RD pulse to the
VL82C59A (Le., -RD = 0, -CS = 0) as
an interrupt acknowledge, sets the
appropriate IS bit if requested and
reads the priority level. Interrupt is
frozen from -WR to -AD.
The word enabled to the data bus
during -RD is:
07

I I- I - I- I - I
1

w21 W1 Iwo I

WO-W2: Binary code of the highest
priority level requesting
service.
1: Equal to a "1" if there is an
interrupt.

This mode is most useful when there is
a routine command common to several
levels. Then the -INTA sequence is not
needed. It is frequently useful to expand
the number of priority levels to more
than 64.
VL82C59A STATUS
The input status of several internal
registers can be read to update user
information from the system. The
following registers can be read by using
OCW3 (IRR and ISR or OCW1 (IMR)).
Interrupt Request Register (IRR): 8-bit
register which contains the levels
requesting an interrupt to be acknowledged. The highest request level is
reset from the IRR when an interrupt is
serviced. (Not affected by IMR.)

In-Service Register (ISR): 8-bit register
which contains the priority levels that
are being updated. The ISR is changed
when an End of Interrupt Command is
sent.
Interrupt Mask Register: 8 bit register
which contains the interrupt request
lines which are masked.
The IRR may be read when, prior to the
-RD pulse, a Read Register Command
is sent with OCW3 (RR = 1, RIS = 0).
The ISR may be read when, prior to the
-RD pulse, a Read Register Command
is sent with OCW3 (RR= 1, RIS - 1).
OCW3 is not written before every status
read operation, as long as the status
read corresponds with the previous one.

FIGURE 4. PRIORITY CELL-SIMPLIFIED LOGIC DIAGRAM
LTIM BIT
o = EDGE, 1 = LEVEL

TO OTHER PRIORITY CALLS

I
CLR
ISRBIT

EDGE
SENSE
LATCH

t - - H - t - - -.....--t-i SET ISR
PRIORITY
RESOLVER

REQUEST
LATCH

NON
MASKED
REQ

-0 P - - I t - - - - - t - - - - - + t + - - - q
MASK
LATCH

_I~A~

o
C

-FREEZE
MCS-80,8l5
MODE

'--t-4......-----+iH--e_--4I_INTERNAL DATA BUS~
-FREEZE

-INTA~
-FREEZE

Q t - i + t -...

-\;J

~.----IAPX86
MODE

READ IRR

MASTER CLR

WRITE MASK

READ IMR

READ ISR

TRUTH TABLE FOR 0 LATCH
NOTES:
1. Master clear active only during ICW1
2. FREEZEI is active during -INTAI and
poll sequences only

555

Operation

On-1

Hold

VLSI TECHNOLOGY, INC.
VL82C59A

The VLS2C59A retains whether the IRR
or ISR has been previously selected by
the OCW3. This is untrue when the poll
is used.
After initialization, the VLS2C59A is set
to IRA.
For reading the IMR, no OCW3 is
needed. The output data bus will
contain the IMR when -RD is active and
AO = 1 (OCW1).
Polling overrides a status read when P
= 1, RR - 1 in OCW3.
Edge and Level Triggered Modes - This
mode is selected using bit 3 in ICW1.
If LTIM = 0, an interrupt request will be
recognized by a positive-going transition on an IR input. The IR input may
stay high without generating another
interrupt.

If LTIM = 1, an interrupt request can be
recognized by a high level on IR input
and there is no requirement for edge
detection. The interrupt request should
be disabled before the EOI command is
issued or the CPU interrupt is enabled
to preclude a second interrupt from occurring.

Figure 4, shows a basic circuit of the
level sensitive and edge sensitive input
circuitry of the VL82C59A. The request
latch is a "D" type latch, which is
transparent.

priority has to be saved by each slave.
Using ICW4, t1 qhe fully nested mode
will be programmed to the master. This
mode is the same as the normal nested
mode, except as follows:

In the edge and level triggered modes,
the IR inputs should stay high until after
the falling edge of the first INTA. If the
IR input goes low before this time, a
default IR7 occurs when the CPU
responds to the interrupt. This may
detect interrupts generated by noise on
the IR inputs. The IR7 routine is used
for smoothing by simply executing a
return instruction thus ignoring the
interrupt. If IR7 is needed for other
purposes a default IR7 can still be
detected by reading the ISA. A normal
IR7 interrupt will set the corresponding
ISR bit, a default IR7 will not. If a
defau~ IR7 routine occurs during a
normallR7 routine, the ISR will remain
set. It is necessary to record whether or
not the IR7 routine was previously
entered. If another IR7 occurs, it is a
default.

A. When an interrupt request from a
given slave is in service, the slave is
not locked out from the master's
priority logic. Further interrupt
requests from higher priority IR's
within the slave will be recognized
by the master and will initiate
interrupts to the processor. In the
normal nested mode a slave is
masked out when its request is in
service and no higher requests from
the same slave can be handled.

The Special Fully Nested Mode - This
mode can be used for a big system,
where cascading occurs, and the

B. When exiting the Interrupt Service
routine, the software has to insure
that the interrupt serviced was the
only one from the slave. This is
accomplished by sending a NonSpecific End of Interrupt (EO I)
command to the slave, then reading
its In-Service register and checking
for zero. If empty, a Non-Specific
EOI may be sent. If not, no EOI
may be sent.

FIGURE 5_ IR TRIGGERING TIMING REQUIREMENT
IR

SOS6/S0SS

SOSO/SOS5

INT
SOS6/S0S8
INTA
SOSO/SOS5

LATCW
ARMED

EARLIEST IR
CAN BE MOVED

*Edge Triggered Mode Only

556

LATCH*
ARMED

VLSI TECHNOLOGY, INC
VL82C59A

Buffered Mode - When the VL82C59A
is used in a large system and bus
driving buffers are needed, on the data
bus (when the cascading mode is used)
enabling buffers may cause difficulty.
The buffered mode will structure the
VL82C59A to send an enable signal on
-SP/-EN to enable the buffers in this
mode, when the VL82C59A data bus
outputs are enabled, the -SP/-EN
output is active.
This change mandates the use of
software programming to ascertain
whether the VL82C59A is a master. Bit
3 in ICW4 programs the buffered mode,
and bit 2 in ICW4 decides whether it is
a master or a slave.

Cascade Mode - The VL82C59A may
be interconnected in a system of a
master with as many as eight slaves
and handle up to 64 priority levels.
The master controls the slaves by the
three-line cascade bus. The cascade
bus is like chip selects to the slaves
during the -INTA. In a cascade configuration, the slave interrupt outputs
are connected to the master interrupt
request inputs. When a slave request
line is asserted and then acknowledged,
the master will enable the slave to
release the device routine address
during bytes 2 and 3 of INTA. Byte 2 is
only for 8086/8088-based systems.

The cascade bus lines are normally low
and contain the slave address code
from the falling edge of the first INTA
pulse to the falling edge of the third
pulse. All VL82C59As in the system
must follow a separate initialization
sequence. Each may be programmed to
work in a different mode. An EOI
command should be issued; once for
the master, and once for the slave. An
address decoder is needed to assert
the Chip Select (CS) input of each
VL82C59A.
The cascade lines of the Master
VL82C59A are asserted for slave
inputs. Non-slave inputs let the cascade
line remain inactive (low).

FIGURE 6. CASCADING THE VL82C59A

ADDRESS BUS (16)

CONTROL BUS
INT
REQ
DATA BUS (8)

-t:-- ~-

- -

-cs

- -1=--

~.j
AO

00-7

f-- I-

'-.7 r -

.I..~

INT

-INTA

Ir
-CS

~7
AO

00·7

I+I+CAS2 I+-

CAS 0

-SP/-EN 7

G~D

654

rrrrrrrr
7

VL82C59A
SLAVEB

CAS1

CAS 1
CAS 2

-SP/-EN 7

G~D

543

654

-CS

INT

CASO

Vl82C59A
SLAVE A

•

"-7 r
-INTA

....
....

....

rrr-t III T
7

~
AO

CASO

00-7

'-Y
INT

-INTA

/
VL82C59A
MASTER

CAS 1
CAS 2

-SP/-EN M7 M6 M5 M4 M3 M2 M1 MO

vrcir~r
7

I
6

I
•

INTERRUPT REQUESTS

557

f) VLSI TECHNOLOGY, INC.
AC CHARACTERISTICS:

VL82C59A

=O°C to +70°C, VCC =5 V ±10%

TIMING REQUIREMENTS
VL82C59A
-08
Symbol

. Parameter

Min

Max

VL82C59A
-10
Min

Max

Units

tAHRL

AO/-CS Setup to -RD/-INTA Low

tRHAX

AO/-CS Hold after -RD/-INTA High

tRLRH

-RD/-INTA Pulse Width

tAHWL

AO/-CS Setup to -WR Low

tWHAX

AO/-CS Hold after -WR High

tWLWH

-WR Pulse Width

tDVWH

Data Setup to -WR High

160

tWHDX

Data Hold after -WR High

tJLJH

Interrupt Request Width (Low)

100

tCVIAL

Cascade Setup to Second
or Third -INTA Low (Slave Only)

tRHRL

End of -RD to next -RD
End of -INTA to next -INTA
within an -INTA sequence only

160

tWHWL

End of -WR to next -WR

190

400

tCHCL*

End of Command to Next Command
(Not Same Command Type)
End of -INTA Sequence to Next -INTA
Sequence

10
5

160

190

·Worst case timing for tCHCL in an actual microprocessor system is typically much greater than 400 ns
(i.e. 8085A .. 1.6 Ils, 8085-A2 = 1 Ils, 80C86 = 1 Ils, 8086-2 = 625 ns).
Note: This is the low time required to clear the input latch in the edge triggered mode.

558

Conditions

Note

VLSI TECHNOLOGY, INC.
VL82C59A

TIMING RESPONSES

Symbol

Parameter

VL82C59A
-08

VL82C59A
-10

Min

Max

Units

Conditions

120

Interrupt Output Delay

300

tlALCV

Cascade Valid from First
-INTA Low (Master Only)

360

tRLEL

Enable Active from -RD Low
or-INTA low

110

tRHEH

Enable Inactive from -RD High
or -INTA High

150

tAHDV

Data Valid from Stable Address

200

tCVDV

Cascade Valid to Valid Data

200

tRLDV

Data Valid from -RD/-INTA Low

tRHDZ

Data Float after -RD/-INTA High

tJHIH

TEST CONDITION DEFINITION TABLE
Test Condition

1.7 V

523n

Open

100pF

4.5 V

1.B kn

30 pF

TESTING LOAD CIRCUIT

TESTING INPUT, OUTPUT WAVEFORM

2.4

2.0

DEVICE
UNDER
TEST

TEST POINTS<

0.45

AC testing inputs are driven at 2.4 V for a Logic 1 and
0.45 V for a Logic O. Timing measurements are made
at 2.0 V for a Logic 1 and O.B V for a Logic O.

*Includes stray and jig capacitance.

559

VLSI TECHNOLOGY,. INC.
VL82C59A

WRITE WAVEFORM
-WR __________________- , ......--tWLWH

tWHAX

tAHWL

-CS
ADDRESS BUS

DATA BUS

READIINTA WAVEFORM

....- - - tRLRH---~
-RD/-INTA - - - - - - - - - - - ,

-EN

-------11'

tRLEL

tRHEH
tRHAX

-CS-----~

ADDRESS BUS

DATA~:

- _ - - - - _ -_
- ___

~:~~ ~------------tR-H-D-Zi_

560

___ _

VLSI TECHNOLOGY, INC
VL82C59A

OTHER TIMING WAVEFORMS

_---JI

-RD - - - -INTA

\ ' - -_ _ _ _ _--'

-WR _ _ __

_---JI

\\...---------'
-RD ---....,.
-INTA
\
-WR

_ _ _ _ ___

-RD - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -INTA
-WR

_---JI

-INTA SEQUENCE WAVEFORM

•••
INT - - - - - - - - - -INTA - - - - - - - - - - - -

DB -

'------'>- -'

tCVIAL

CO-2 __________________+-____

Notes:

--"~------...L------...~-------------~-

Interrupt output must remain HIGH at least until leading edge of first INTA.
1. Cycle 1 in iAPX 86, iAPX 88 systems, the Data Bus is not active.

561

VLSI TECHNOLOGY, INC.
VL82C59A

ABSOLUTE MAXIMUM RATING
Ambient Temperature
Under Bias
Storage Temperature -65°C to + 150°C
Voltage on Any Pin
with Respect to Ground

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or
any other conditions above those

indicated in this data sheet is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliablility.

-0.5 V to 7 V

Power Dissipation

1 Watt

DC CHARACTERISTICS:

= O°C to 70°C, VCC = 5 V ±1 0%
VL82C59A
-10

VL82C59A
-08
Parameter

Min

VIL

Input Low Voltage

-0.5

0.8'

VIH

Input High Voltage

2.2

VCC + 0.5

VOL

Output Low Voltage

0.4

VOH

Output High Voltage

Symbol

Max

Min

Max

Units

Conditions

IOL = 2.5 mA

3.0

IOH =-2.5 rnA

VCC-O.4

IOH

=-100~

III

Input Leakage Current

±1.0

ILO

Output Leakage Current

±10.0

o V :S;VIN :S;VCC
o V:S;VOUT:S;VCC

ILiR

IR Input Leakage Current

-300

J.lA

VIN =0

+10

J.lA

VIN =VCC

Note

J.lA

VIN = VCC or GND

ICC

Operating Supply Current

ICCS

Standby Supply Current

J.lA

AIIIR=VCC
Outputs Unloaded
VCC = 5.5 V
Note: For extended termperature EXPRESS VIH = 2.3 V.

CAPACITANCE: TA =25° C, VCC =GND =0 V
Symbol
CIN

Parameter
Input Capacitance

Min

Max

Units

Test Conditions

fc = 1 MHz
Unmeasured pins returned to VSS

CI/O

I/O Capacitance

COUT

Output Capacitance

Note: Capacitance values guaranteed and sampled, but not 100% tested.

562

VLSI TECHNOLOGY, INC.
VL82C612
PC-AT MEMORY MAPPER (74LS612)

FEATURES

DESCRIPTION

• Expands address lines from four to 12

The VL82C612 CMOS memory-mapper
integrated circuit contains a 4-line to 16line decoder. a 16-word by 12-bit RAM.
16 channels of 2-line to 1-line mUltiplexers. and the necessary control logic to
operate efficiently in an IBM PC/AT or
most other microprocessor environments. The device is fabricated in
CMOS technology to insure low power
consumption and maximum system
performance while remaining fully
compatible with the 74LS612.

• Paged memory mapping design
• Three-state or open-collector map
outputs
• Compatible with IBM PC/AT as well
as most popular microprocessorbased systems
• Single 5 V power supply
• Low power-consuming CMOS
technology
• Fully compatible with 74LS612

The memory-mapper expands the
microprocessor's system memory

PIN DIAGRAM

SYSTEM BLOCK DIAGRAM

address capability by eight bits. Four
bits of the memory address bus (see
System Block Diagram below) can be
used to select one of 16 map registers
that contain 12 bits each. These 12 bits
are presented to the system memory
address bus through the map output
buffers along with the remaining
memory address bits from the CPU.
The device is available in a 40-pin DIP
as well as a 44-pin plastic leaded chip
carrier (PLCC).

VL82C612

vcc

RS2

DATA

RS3

RSl

-CS

MAl

-STB

RSO

W-W

MAO

DO
01
02
03
04
05

-MM

011
010
09
08
07
06
N.C.

MOO
MOl
M02
M03
M04
M05
GNO

MOlD
M09
M08
M07
M06
-ME

CONTROL

.....------..,
CPU

CONTROL 00-011
MAOMOOMA3
VL82C612
MOll
MEMORY-MAPPER

M~l

---------...---

ADDRESS BUS

ORDER INFORMATION
PLEASE CONSULT DATA
SHEET FOR DETAILED
INFORMATION

Part
Number

Package

VL82C612-PC
VL82C612-QC

Plastic DIP
Plastic Leaded Chip Carrier (PLCC)

Note: Operating temperature range is O°C to +70°C.

563

SYSTEM
MEMORY

VLSI TECHNOLOGY, INC

564

VLSI TECHNOLOGY, INC.
VL83C11
GENERAL PURPOSE (SCSI) BUS TRANSCEIVER

FEATURES

DESCRIPTION

• Meets full Small Computer Systems
Interface (SCSI) specifications for
system cables up to six meters long

The VL83C11 General Purpose Bus
Transceiver Chip, is a two-micron
CMOS device designed as a 48 rnA bus
transceiver chip for all of the Small
Computer System Interface (SCSI) bus
signals. It incorporates high current
single-ended drivers for the SCSI bus.
The VL83C11 is specifically intended to
be used with the VL53C86 or NCR
53C86 SCSI Protocol Controller
families. It interfaces directly to those
devices, with no additional circuits
required. It can be used with other
interfaces where a general purpose 48
rnA bus transceiver is required. Logical
and electrical flexibility also allow its use

• Fully buffered, bidirectional data and
control buses
• Interfaces directly to VL53C86 and
NCR 5386 family
• Can be used with other interfaces
requiring a 48 rnA drive
• Lowcost
• Two-micron CMOS technology
• Housed in a standard 52-pin PLCC

PIN DIAGRAM

as a general pupose interface driverl
receiver chip.
The VL83C11 is functionally equivalent
to the NMOS NCR 8310, but has been
designed in CMOS technology. It meets
the full electrical specifications of Small
Computer Systems Interface (SCSI) for
system cable lengths up to six meters
long. Further, it has been optimized for
connection to the standard SCSI
connector.
The VL83C11 General Purpose
Tranceiver Chip is packaged in a 52-pin
plastic leaded chip carrier (PLCC).

BLOCK DIAGRAM
VL83C11-QC
BSV

110

MSG GNO

BSV
OUT TGS

TGS
IGS
IIO.CID.MSG

.....

REO. ACK. ATN
ATN
RSTIN
-OBO
-DB1
-OB2
GNO
-OB3
-OB4
-OB5
GNO
-DB6
-OB7
-OBP

45
44
43
42
41
40
39
38
37
36
35
34
21 22 23 24 25 26 27 28 29 30 31 32 33

-ATN
-8SV
-ACK
GNO
-RST
-MSG
-SEL
GNO
C/-O
-REO

BUSYIN. SELIN. RSTIN
BSYOUT. SELOUT•

VOO

CONTROL
BUS
~

...
3

RSTOUT

9
~

SCSI CONTROL
(-8SV. -SEL. -RST.
-ACK. -ATN.II-O.
c/-D. -MSG. -REO)

-100 - -102 <:===~
ARB-----i
-DBEN --4I..-----i

11-0
-DBEN
ARB

00 ·07. OP
D6

<;:===::t

1¢:=9=::!>-DBO _-DB9. -DBP

-l01

ORDER INFORMATION
Part

Number

Package

VL83C11-QC

Plastic Leaded Chip Carrier (PLCC)

Note: Operating temperature range is O°C to +70°C

565

VLSI TECHNOLOGY, INC.
VL83C11

SIGNAL DESCRIPTIONS
Pin

Signal
Name

Number

-DBO --DB7,
-DBP

10-12,14-16,
18-20

These nine bits (-DBO through -DB7, -DBP) are bidirectional, active low, open-drain
signals that form the data bus. -DB7 is the most significant bit and has the highest
priority during Arbitration phase. Data parity is odd. Parity is not valid during arbitration.

-RST

Reset - Indicates a SCSI bus reset condition. An "or-tied" signal. This signal is bidirectional, active low and open-drain.

-ATN

Attention - Driven by an initiator, -ATN indicates an attention condition. This bidirectional, active low and open-drain signal is received in the target role.

-ACK

Acknowledge - Driven by an initiator, -ACK indicates an acknowledgment for a REal
ACK data transfer handshake. In the target role, -ACK is received as a response to the
-REO signal. It is a bidirectional, active low, open-drain signal.

-REO

Request - Driven by a target, -REO indicates a request for a REO/ACK data transfer
handshake. This signal is received by the initiator. It is a bidirectional, active low, opendrain signal.

-MSG

Message - Driven by the target during the Message phase. This bidirectional, active low,
open-drain signal is received by the initiator.

11-0

Input/Output - This bidirectional, open-drain signal is driven by a target which controls
the direction of data movement on the SCSI bus. High indicates input to the initiator.
This signal is also used to distinguish between Selection and Reselection phases.

C/-D

Control or Data - This bidirectional, open-drain signal is driven by the target. It indicates
whether Control or Data is on the data bus. High indicates Control. This signal is
received by the initiator.

-SEL

Select - Used by an initiator to select a target or by a target to reselect an initiator. It is a
bidirectional, active low, open-drain signal.

-BSY

Busy - Indicates the SCSI bus is being used and can be driven by both the initiator and
the target device. An "or-tied" signal. This is a bidirectional, active low, open-drain
signal.

DO, 01-07, DP

29,27- 21,
30

These nine bits (DO through 07, DP) form the data bus. 07 is the most significant bit
and has the highest priority during Arbitration phase. DP is the parity bit.

-DBEN

Data Bus Enable - This signal enables the SCSI bus drivers for -DB7 through -DBP.

TGS

Target Group Select - Enables the SCSI bus drivers for 11-0, C/-D, -MSG, and -REO.

Signal
Description

IGS

Initiator Group Select - Enables the SCSI bus drivers for -ACK and -ATN.

ARB

Arbitration - Enables decode of 100 -102 and asserts priority decode as SCSI data bus
10.

-100-2

33-31

Identification - The 10 signals are used during arbitration to select the correct DBx line.

110

Input/Output - This line is used to drive or receive the SCSI signal 11-0.

C/D

ControllData - This line is used to drive or receive the SCSI signal C/-D.

MSG

Message - This line is used to drive or receive the SCSI signal-MSG.

REO

Request - This line is used to drive or receive the SCSI signal -REO.

ACK

Acknowledge - This line controls the SCSI signal-ACK.

ATN

Attention - This line controls the SCSI signal-ATN.

BSYIN

Busy - This line indicates the received state of the SCSI signal-BSY.

BSYOUT

Busy - This line drives the SCSI signal-BSY.

SELIN

Select - This line indicates the received state of the SCSI signal-SEL.

566

VLSI TECHNOLOGY, INC
VL83C11

SIGNAL DESCRIPTIONS
Pin

Signal
Name

Number

Signal
Description

SELOUT

Select - This line drives the SCSI signal-SEl.

RSTIN

Reset - This line indicates the received state of the SCSI signal-RST.

.-RSTOUT

Reset - This line drives the SCSI signal-RST.

VDD

+5V

GND

2,13,17,39,43 Ground

FUNCTIONAL DESCRIPTION
The VL83C11 General Purpose
Tranceiver has been designed primarily
a buffer whose purpose is to translate
signals from a microprocessor data bus
to the low impedance, terminated, 48
mA, single ended, environment of the
SCSI bus.
There is also an arbitration scheme,
consistent with SCSI requirements,
implemented in this device's logic.
LOGICAL OPERATION
Bus Operation - Data bus direction is
usually controlled with a single line
-DBEN (pin 35). With -DBEN active
(low voltage level), data flow is from Ox
to DBx or onto the SCSI data bus.

Arbitration - Arbitration allows one SCSI
device to gain control of the SCSI bus
so that it can assume a role as Initiator
or Target. Arbitration is a system
option, but if not implemented, there
can be only one Initiator.
The SCSI 10 bit is a single bit on the
data bus which corresponds to the
SCSI device's unique SCSI Address.
All other seven data bus bits are
released by the SCSI device. During
arbitration, parity is not guaranteed, but
may not be driven to the false state.
During arbitration with the VL83C11,
-DBEN is normally inactive and ARB is
driven active (high voltage level).

Under those circumstances, -DBP will
be high as will all other -DBx lines
except for the one showing a decode of
the -102 - -100 lines.
Target Group Select (TGS) - When the
TGS line is driven active (high voltage
level), the driving device is controlling in
the Target role. The purpose is to
enable the VL83C11 SCSI drivers for
signals 11-0, C/-D, -MSG, and -REO.
Initiator Group Select (IGS) - When at a
high voltage level, the IGS line enables
the SCSI bus drives for -ATN and
-ACK that the driver is in the Initiator
role. In the low voltage state, -ATN and
-ACK will be received by the Initiator.

APPLICATIONS
Driving Circuitry
The VL83C11 can be driven with either
7400 TTL, LS or Schottky or aMOS
microprocessor.
A typical driverlload implementation is
represented in Figure 2, TTL Drive of
the VL83C11.
.

Output Loading
Output loading of the VL83C11 is
prescribed in ANSI document X3T9.2,
SCSI, Small Computer Systems
Interface, Section 4, Physical level. An
example of a typical bus loading is
shown in Figure 1, Illustration of SCSI
Bus Loading. Note that the resistive

loading element is clearly specified
regarding terminating resistors. In
contrast, the capacitive/inductive loads
imposed as a result of cabling, connectors, or printed circuitry traces can only
be estimated when the application has
been defined. External loading must be
considered when evaluating the AC
characteristics.

FIGURE 1: ILLUSTRATION OF SCSI BUS LOADING

VL83C11

220

330

LOADS

Note: SCSI bus may be loaded per ANSI X3T9.2, Section 4.

567

VLSI TECHNOLOGY, INC.
VL83C11

FIGURE 2. TTL DRIVE OF VL83C11
VL83C11

74S240 DRIVER

Note: 74S240 easily drives eight VL83C11 driver chips.

AC CHARACTERISTICS:

=O°C to +70°C, VCC =5 V ± 5%

PROPAGATION DELAY
Propagation Delay Reference defines
measurement points used in determination of delay times. Since there is no
internal clock in the VL83C11 Driverl

conforms to propagation delays
illustrated in Data Bus and Control
Signal Turnaround, as well as Control
Signal and Arbitration Delay Times.

Receiver chip, measurements are to be
made relative to other signals defined
as references.
CHIP TIMING
The VL83C11 DriverlReceiver chip

PROPAGATION DELAY REFERENCE
Symbol

Parameter

Min

Max

Unit

Condition

tPDHH

No Internal Clock

tPDLL

No Internal Clock

tPDHL

No Internal Clock

PROPAGATION DELAY REFERENCE TIMING
INPUT

2.0V
0.5 V

OUTPUT

--+--:';~H}'

tPDHL

~.o V

}_.O_v_______.-:-o_;;_~-:-:~:======-=-=-=-I

568

VLSI TECHNOLOGY, INC.
VL83C11

DATA BUS PROPAGATION
Symbol

Parameter

Data Bus to SCSI Bus Delay

SBEN True to Data Bus Three-State

SBEN False to SCSI Bus Release

100

SCSI Bus to Data Bus Delay

Min

Max

Unit

Condition

DATA BUS PROPAGATION TIMING

-DBEN

~'----f
~
I X_______

DO-D7, DP _ _ _

-DBO - -DB7/,
-DBP

X,--_

TGS GATED CONTROL SIGNAL DELAYS
Symbol

Parameter

Max

Unit

Control Signal Delay to SCSI Bus

TGS True to Input Release

TGS False to SCSI Bus Release

SCSI Bus Receiver Delay

Min

TGS GATED CONTROL SIGNAL DELAYS TIMING
TGSJ

11-0, C/-D, -MSG, -REO

569

Condition

VLSI TECHNOLOGY, INC
VL83C11

IGS GATED CONTROL SIGNAL DELAYS
Symbol

Parameter

Max

Unit

Control Signal Delay to SCSI Bus

t10

IGS True to Input Release

t11

IGS False to SCSI Bus Release

t12

SCSI Bus Receiver Delay

Min

Condition

IGS GATED CONTROL SIGNAL DELAYS TIMING
IGSJ

ACK, ATN

X,--_

-ACK,-ATN
CONTROL~GNALTURNAROUND

Symbol

Parameter

Max

Unit

t13

Receiver Delay BSY RST SEL

t14

Driver Delay BSY RST SEL

Min

CONTROL SIGNAL TURNAROUND TIMING
BSYOUT, SELOUT, RSTOUT

-BSY,-SEL,-RST

Condition

,'---------

i------------~

_t14\_"------_

tt3~
-7'f

_____
BSYIN, SELIN, RSTIN _

'J.-tt3~
~

ARBITRATION DELAY
Symbol
t15
t16

Parameter

Max

Unit

ARB True to -DBO-7 True

ARB False to -OBO-7 False

Min

ARBRITRATION DELAYTIMING
ARB
-OBO--OB7

t~tt5~
570

Condition

VLSI TECHNOLOGY, INC.
VL83C11

ABSOLUTE MAXIMUM RATIINGS
Ambient Operating
Temperature
Storage Temperature

ODC to +70 DC
-65°C to + 150DC

Supply Voltage to
Ground Potential

-0.5 V to +6.0 V

Applied Input
Voltage

in this data sheet is not implied.
Exposure to absolute maximum rating
conditions for extended periods may
affect device reliability.

-0.5 V to VCC + 0.5 V

Power Dissipation

800 mW

DC CHARACTERISTICS:
Symbol

Stresses above those listed may cause
permanent damage to the device.
These are stress ratings only, functional
operation of this device at these or any
other conditions above those indicated

=ODC to +70 DC, VCC =5 V ± 5%
Units

Conditions

Parameter

Min

Max

VCC

Positive Supply Voltage

4.75

5.25

ICC

Operating Current

2.0

VIH

High Level Input Voltage

2.0

5.25

VIL

Low Level Input Voltage

-0.3

0.8

IIH

High Level Input Current (SCSI)

ilL

Low Level Input Current (SCSI)

-50

VIL=O

ilL

Low Level Input Current (DP)

-2

VIL ... O

IIH

High Level Input Current (All Other Pins)

VIH .. 5.25
VILmO

All Inputs .. VIL .. 0.8

VIH - 5.25

ilL

Low Level Input Current (All Other Pins)

-10

VOH

High Level Output Voltage

2.5

5.25

VCC ... 4.75 V, IOH = 7.0 mA

VOL

Low Level Output Voltage

0.4

VCC .. 4.75 V, IOL ... 7.0 mA

VOL

Low Level Output Voltage (SCSI)

0.5

VCC ... 4.75 V, IOL ... 48.0 mA

571

VLSI TECHNOLOGY, INC

572

VLSI TECHNOLOGY, INC.
VL8530
SERIAL COMMUNICATIONS CONTROLLER (SCC)

FEATURES

DESCRIPTION

• Two independent full-duplex
channels

The VL8530 Serial Communications
Controller (SCC) is a dual-channel,
multi-protocol data communications
peripheral designed for use with
conventional non-multiplexed buses.
The SCCcan be software configured
to satisfy a wide variety of serial
communications applications. The
device contains a variety of new,
sophisticated internal functions,
including on-chip baud rate generators, digital phase-locked loops, and
crystal oscillators that dramatically
reduce the need for external logic.

• 0 to 1.5M bit/second
• Multi-protocol operation for NRZ,
NRZI, or FM
• Asynchronous mode includes 1, 1.5,
or 2 stop bits per character
• Programmable clock factor
• Break generation and error detection
• Intelligent SOLC/HOLe
• Localloopback and auto echo
modes

The SCC handles asynchronous formats, synchronous byte-oriented protocols, such as IBM Bisync, and synchronous bit-oriented protocols, such
as HOLC and IBM SOLC. This versatile device supports virtually any
serial data transfer application (cassette, diskette, tape drives, etc.).
The device can generate and check
CRC codes in any synchronous mode
and can be programmed to check data
integrity in various modes. The SCC
also has facilities for modem controls
in both channels.

• Synchronous support includes
internal or external character
synchronization

PIN DIAGRAM

BLOCK DIAGRAM

VL8530
01
03
05
07
INT
lEO
IE1
-INTACK

vce
-W/-REQA
-SYNCA
-RTXCA
RXOA
-TRXCA
TXOA
-OTRI-REQA
-RTSA
-CTSA
-DCOA
PCLK

DO
02
04
06
-AD
-WR
NB
-CE
O/-C
GNO
-W/-REQB
-SYNCB
-RTXCB
RXOB
-TRXCB
TXOB
-OTRI-REQB
-RTSB
-CTSB
-DCOB

SERIAL DATA
CHANNEL CLOCKS

MOOEM,DMA, OR
OTHER CONTROLS

MODEM,DMA, OR
OTHER CONTROLS

INTERRUPT
CONTROL
LINES

SERIAL DATA
CHANNEL CLOCKS

-SYNC
L -_ _--I-~

-WAIT/-REQ8

ORDER INFORMATION
Part
Number

Clock
Frequency

VL8530-04PC
4MHz
VL8530-04CC
VL8530-04QC
VL8530-06PC
6 MHz
VL8530-06CC
VL8530-06QC
Note: Operating temperature range
573

Package
Plastic DIP
Ceramic DIP
Plastic Leaded Chip Carrier (PLCC)
Plastic DIP
Ceramic DIP
Plastic Leaded Chip Carrier (PLCC)
IS 0° to +70°C.

VLSI TECHNOLOGY, INC.
VL8530

PIN DIAGRAM

lEO

A/-B

lEI

-CE

-INTACK

D/-C

VCC

N.C.
GND

-W/-REOA
-SYNCA

-W/-REQB

-RTXCA

-SYNCB

RXDA

-RTXCB
RXDB

-TRXCA

-TRXCB

TXDA

TXDB

N.C.

-DTRI-REOA -CTSA PCLK -CTSB -DTRREOB

SIGNAL DESCRIPTIONS
Signal
Name

DIPPln
Number

Signal
Description

AI-B

Channel AlChannel B Select - This input signal selects the channel on which the read or
write operation occurs.

-CE

Chip Enable - This active low input signal selects the SCC for a read or write operation.

-CTSA,
-CTSB

18,
22

Clear To Send - Active low inputs - If these pins are programmed as auto enables, a low on
the inputs enables the respective transmitters. If not programmed as auto enables, they may
be used as general-purpose inputs. Both inputs are Schmitt trigger buffered to accommodate slow rise time inputs. The SCC detects pulses on these inputs and can interrupt the
CPU on both logic level transitions.

D/-C·

Data/Control Select - This input signal defines the type of information transferred to or from
the SCC. A high means data is transferred; a low indicates a command.

-DCDA,
-DCDB

19
21

Data Carrier Detect - Active low inputs - These pins function as receiver enables if they are
programmed for auto enables; otherwise, they may be used as general-purpose input pins.
Both pins are Schmitt trigger buffered to accomodate slow rise time signals. The SCC
detects pulses on these pins and can interrupt the CPU on both logic level transitions.

DO-D7

40,1,39,2,38,
3,37,4

Data Bus - These bidirectional, three-state lines carry data and commands to and from the
SCC.

16,

Data Terminal Ready/Request - These active low outputs follow the state programmed into
the -DTR bit. They can also be used as general-purpose outputs or as request lines for a
direct memeory access (DMA) controller.

-DTRI-REOA
-DTRI-REOB

lEI

Interrupt Enable In - Active high output - lEI is used with lEO to form an interrupt daisy chain
when there is more than one interrupt-driven device. A high lEI indicates that no other higher
priority device has an interrupt underservice or is requesting an interrupt.

lEO

Interrupt Enable Out - Active high output - lEO is high only if lEI is high and the CPU is not
servicing an SCC interrupt or the SCC is not requesting an interrupt (Interrupt Acknowledge
cycle only). lEO is connected to the next lower priority device's lEI input and thus inhibits
interrupts from lower priority devices.

-INT

Interrupt Request - Active low open-drain output - This signal is activated when theSCC
requests an interrupt.
574

VLSI TECHNOLOGY, INC.
VL8530

SIGNAL DESCRIPTIONS (Cant.)
Signal
Name

DIP Pin
Number

Signal
Description

-INTACK

Interrupt Acknowledge - Active low input - This signal indicates an active Interrupt Acknowledge cycle. During this cycle, the SCC interrupt daisy chain settles. When -RD be-comes
active, the SCC places an interrupt vector on the data bus (if lEI is high). The -INTACK
signal is latched by the rising edge of PCLK.

PCLK

Clock - This input is the master SCC clock used to synchronize internal signals. PCLK is a
TTL level signal.

-RD

Read - Active low input - This signal indicates a read operation and, when the SCC is selected, enables the SCC's bus drivers. During the Interrupt Acknowledge cycle, this signal
gates the interrupt vector onto the bus if the SCC is the highest priority device requesting an
interrupt.

RXDA,
RXDB

13,

Receive Data - Active high inputs - These input signals receive serial data at standard TTL
levels.

-RTXCA,
-RTXCB

12,

-RTSA,
-RTSB

-SYNCA,
-SYNCB

11,
29

17,

ReceivelTransmit Clocks - Active low inputs - These pins can be programmed in several
different modes of operation. In each channel, -RTXC may supply the receive clock, the
transmit clock, the clock for the baud rate generator, or the clock for the digital phase locked
loop. These pins can also be programmed for use with the respective -SYNC pins as a
crystal oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate in asynchronous modes.
Request To Send - Active low outputs - When the -RTS bit in write register 5 (figure 7) is set,
the -RTS signal goes low. When the -RTS bit is reset in the asynchronous mode and auto
enable is on, the signal goes high after the transmitter is empty. In synchronous mode or in
asynchronous mode with auto enable off, the -RTS pin strictly follows the state of the -RTS
bit. Both pins can be used as general purpose outputs.
Synchronization - Active low inputs or outputs - These pins can act either as inputs or outputs,
or part of the crystal oscillator circuit. In the asynchronous receive mode (crystal oscillator
option not selected), these pins are inputs similar to -CTS and -DCD. In this mode, transitions on these lines affect the state of the synchronouslhunt status bits in read register 0
(Figure 6) but have no other function.
In external synchronization mode with the crystal oscillator not selected, these lines also act
as inputs. In this mode, -SYNC must be driven low to receive clock cycles after the last bit in
the synchronous character is received. Character assembly begins on the rising edge of the
receive clock immediately preceding the activation of -SYNC.
In the internal synchronization mode (Monosync and Bisync) with the crystal oscillator not
selected, these pins act as outputs and are active only during the part of the receive clock
cycle in which synchronous characters are recognized. The synchronous condi-tion is not
latched, so these outputs are active each time a synchronization pattern is recognized
(regardless of character boundaries). In SDLC mode, these pins act as outputs and are valid
on receipt of a flag.

TXDA,
TXDB

15,
25

Transmit Data - Active high outputs - These output signals transmit serial data at standard
TTL levels.

-TRXCA,
-TRXCB

14,
26

Transmit/Receive Clocks - Active low inputs or outputs - These pins can be programmed in
several different modes of operation. - TRXC may supply the receive clock or the transmit
clock in the input mode or supply the output of the digital phase-locked loop, the crystal
oscillator, the baud rate generator, or the transmit clock in the output mode.

-WR

Write - Active low input - When the SCC is selected, this signal indicates a write operation.
The coincidence of -RD and -WR is interpreted as a reset.

-W/-REOA,
-W/-REOB

10,
30

WaitlRequest - Open-drain outputs when programmed for a wait function, driven high or low
when programmed for a Request function - These dual-purpose outputs may be programmed
as Request lines for a DMA controller or as Wait lines to synchronize the CPU to the SCC
data rate. The reset state is Wait.

575

VLSI TECHNOLOGY, INC.
VL8530

FUNCTIONAL
DESCRIPTION
The functional capabilities of the SCC
can be described from two different
points of view. As a data communications device, it transmits and receives
data in a wide variety of data communications protocols. As a microprocessor
peripheral, the SCC offers valuable
features as vectored interrupts, polling,
and simple handshake capability.
DATA COMMUNICATIONS
CAPABILITY
The SCC provides two independent fullduplex channels programmable for use
in any common asynchronous or synchronous data communication protocol.
Figure 1 and the following description
briefly detail these protocols.
Asynchronous modes - Transmission
and reception can be accomplished
independently on each channel with 5
to 8 bits per character, plus optional
even or odd parity. The transmitters
can supply 1, 1 1/2, or 2 stop bits per
character and a break output at any
time. The receiver break-detection logic
interrupts the CPU both at the start and
at the end of a received break.
Reception is protected from spikes by a
transient spike-rejection mechanism
that checks the signal one-half a bit
time after a low level is detected on the
receive data input (RXOA or RXOB). If
the low does not persist (as in the case
of a transient), the character assembly
process does not start.
Framing errors and overrun errors are
detected and buffered together with the
partial character on which they occur.
Vectored interrupts allow fast servicing
or error conditions using dedicated
routines. Furthermore, a built-in
checking process avoids the interpretation of a framing error as a new start bit:
a framing error results in the addition of
one-half a bit time to the point at which
the search for the next start bit begins.
The SCC does not require symmetric
transmit and receive clock signals
a feature allowing use of the wide variety of clock sources. The transmitter
and receiver can handle data at a rate
of 1, 1/16, 1/32, or 1/64 of the clock rate
supplied to the receive and transmit
clock inputs. In asynchronous modes,

the -SYNC pin may be pro-grammed as
an input used for such functions as
monitoring a ring indicator.

programmed to send an idle line consisting of continuous flag characters or
a steady marking condition.

Synchronous modes. The SCC
supports both byte-oriented and bitoriented synchronous communication.
Synchronous byte-oriented protocols
can be handled in several modes, allowing character synchronization with a
6-bit or 8-bit synchronous character
(Monosync) any 12-bit synchroni-zation
pattern (Bisync), or with an external
synchronous signal. Leading sync
characters can be removed without
interrupting the CPU.

If a transmit underrun occurs in the
middle of a message, an external/status interrupt warns the CPU of this
status change so that an abort may be
issued. The SCC may also be programmed to send an abort itself in case
of an underrun, relieving the CPU of this
task. One to eight bits per character
can be sent, allowing recep-tion of a
message with no prior infor-mation
about the character structure in the
information field of a frame.

5- or 7-bit synchronous characters are
detected with 8- or 16-bit patterns in the
SCC by overlapping the larger pattern
across multple incoming synchronous
characters.
The CRC checking for synchronous
byte-oriented modes is delayed by one
character time so that the CPU may
disable CRC checking on specific
characters. This allows the implementation of IBM Bisync. protocols.
Both CRC-16 (X16 + X15 +X2 + 1) and
cCln (X 16 + X12 + X5 + 1) error checking polynomials are supported. Either
polynomial may be selected in all
Synchronous modes. Users may preset
the CRC generator and checker to all
ones or all zeros. The SCC also provides a feature that automatically
transmits CRC data when no other data
is available for transmission. This
allows for high-speed transmissions
under OMA control, with no need for
CPU intervention at the end of a message. When there is no data or CRC to
send in synchronous modes, the
transmitter inserts 6-,8-, or 16-bit
synchronous characters, regardless of
the programmed character length.
The SCC supports synchronous bitoriented protocols, such as SOLC and
HOLC, by performing automatic flag
sending, zero insertion, and CRC generation. A special command can be
used to abort a frame in transmission.
At the end of a message, the SCC
automatically transmits the CRC and
trailing flag when the transmitter underruns. The transmitter may also be

576

The receiver automatically acquires
synchronization on the leading flag of a
frame in SOLC or HOLC and provides a
synchronization signal on the -SYNC
pin (an interrupt can also be programmed). The receiver can be
programmed to search for frames
addressed by a single byte (or four bits
within a byte) of a user-selected
address or to a global broadcast
address. In this mode, frames not
matching either the user-selected or
broadcast address are ignored. The
number of address bytes can be
extended under software control. For
receiving data, an interrupt on the first
received character, or an interrupt on
every character, or on special con-dition
only (end-of-frame) can be selected.
The receiver automatically deletes all
zeros inserted by the transmitter during
character assembly. The CRC is also
calculated and is automatically checked
to validate frame transmission. At the
end of transmission, the status of a
received frame is availabe in the status
registers. In SOLC mode, the SCC
must be programmed to use the SOLC
CRC polynomial, but the generator and
checker may be preset to all ones or all
zeros.
The CRC is inverted before transmission and the receiver checks against
the bit pattern 0001110100001111.
The NRZ, NRZI, or FM coding may be
used in any 1x mode. The parity
options available in asynchronous
modes are available in synchronous
modes.

VLSI TECHNOLOGY, INC.
VL8530

The SCC can be conveniently used
under DMA control to provide highspeed reception or transmission. In
reception, for example, the SCC can

interrupt the CPU when the first
character of a message is received.
The CPU then enables the DMA to

transfer the message to memory. The
SCC then issues an end-of-frame
interrupt and the CPU can check the
status of the received messsage.

FIGURE 1. sec PROTOCOLS

MARKING LINE

MARKING LINE
ASYNCHRONOUS

SYNC

DATA

CRC1

CRC2

DATA

CRC1

CRC2

DATA

CRC1

CRC2

CRC1

CRC2

MONOSYNC
SYNC

SYNC

DATA
BISYNC
DATA
EXTERNAL SYNC

FLAG

ADDRESS
SDLCIHDLCIX.25

577

FLAG

VLSI TECHNOLOGY. INC.
VL8530

The CPU is thereby freed for other
service while the message is being
received. The CPU may also enable
the OMA first and have the SCC interrupt only on end-of-frame. This
procedure allows all data to be transferred via the OMA.
SDLC LOOP MODE
The sec supports SOLe loop mode in
addition to normal SOLC. In an SOLC
loop, there is a primary controller
station that manages the message
traffic flow on the loop and any number
of secondary stations. In SOLC loop
mode, the sce performs the functions
of a secondary station while an SCC
operating in regular SOLC mode can
act as a controller (Figure 3).
A secondary station in an SOLC Loop
is always listening to the messages
being sent around the loop, and in fact
must pass these messages to the rest
of the loop by retransmitting them with
a one-bit time delay. The secondary
station can place its own message on
the loop only at specific times. The
controller signals that secondary stations may transmit messages by
sending a special character, called an
End Of Poll (EOP), around the loop.
The EOP character is the bit pattern
11111110. Because of zero insertion
during messages, this bit pattern is
unique and easily recognized.

When a secondary station has a message to transmit and recognizes an
EOP on the line, it changes the last
binary 1 of the EOP to a 0 before
trans-mission. This has the effect of
turning the EOP into a flag sequence.
The secondary station now places its
message on the loop and terminates
the message with an EOP. Any secondary stations, further down the loop
with messages to transmit, can then
append their messages to the
message of the first secondary station
without messages to send. The
following stations merely echo the
incoming messages and are prohibited from placing messages on the
loop (except upon recognizing an
EOP). The SOLC loop mode is a
programmable option in the SCC;
NRZ, NRZI, and FM coding may all be
used in SOLe Loop mode.

process is repeated. The time constant
may be changed at any time, but the
new value does not take effect until the
next load of the counter.

BAUD RATE GENERATOR
Each channel in the ESCC contains a
programmable baud rate generator.
Each generator consists of two a-bit
time constant registers that form a 16bit time-constant, a 16-bit down
counter, and a flip-flop on the output
producing a square wave. On startup,
the flip-flop on the output is set in a
HIGH state, the value in the timeconstant register is loaded into the
counter, and the counter starts counting down. The output of the baud rate
generator toggles upon reaching 0,
the value in the time-constant register

2 (time constant+2) x (BR clock period)

FIGURE 2. DETECTING 5- OR 7-BIT
SYNCHRONOUS CHARACTERS

If the receive clock or transmit clock is
not programmed to come from the
- TRxC pin, the output of the baud rate
generator may be echoed out via the
-TRxCpin.
The following formula relates the time
constant to the baud rate (the baud rate
is in bits/second and BR clock period is
in seconds):
baud rate =

DIGITAL PHASE-LOCKED LOOP
The ESCC contains a digital phaselocked-loop (OPLL) to recover clock
information from a data stream with
NRZI or FM encoding. The OPLL is
driven by a clock that is nominally 32
(NRZI) or 16 (FM) times the data rate.
The OPLL uses this clock, along with
the data stream, to construct a clock
for the data. This clock may then be
used as the SCC receive clock, the
transmit clock, or both.

FIGURE 3. AN SDLC LOOP

5 BITS

I"~

I ~YNC I SYN? I SYNC I DATA I DATA I DATA I DATA I
1"'8~

~16

The output of the baud rate generator
may be used as either the transmit
clock, the receive clock, or both. It can
also drive the digital phase-locked loop
(see next section).

578

VLSI TECHNOLOGY, INC.
VL8530

For NRZI encoding, the OPLL counts
the 32x clock to create nominal bit
times. As the 32x clock is counted, the
OPLL is searching the incoming data
stream for edges (either 1 to 0 or 0 to
1). Whenever an edge is de-tected, the
OPLL makes a count adjustment (during
the next counting cycle), producing a
terminal count closer to the center of the
bit cell.

an additional transition at the center of
the bit cell and a 0 is represented by no
additional transition at the center of the
bit cell. In FM0 (bi-phase space), a
transition occurs at the beginning of
every bit cell. 'A 0 is represented by an
additional transition at the center of the
bit cell, and a 1 is represented by no
additional transition at the center of the

For FM encoding, the OPLL still counts
from 0 to 31, but with a cycle corresponding to two bit times. When the
OPLL is locked, the clock edges in the
data stream should occur between
counts 15 and 16, and between counts
31 and O. The OPLL looks for edges
only during a time centered on the 15 to
16 counting transition.

In addition to these four methods, the
ESCC can be used to decode Manchester (bi-phase level) data by using the
OPLL in the FM mode and programming the receiver for NRZ data.
Manchester encoding always produces
a transition at the center of the bit cell.
If the transition is 0 to 1, the bit is a O. If
the transition is 1 to 0, the bit is a 1.

The 32x clock for the OPLL can be
programmed to come from either the
-RTxC input or the output of the baud
rate generator. The OPLL output may
be programmed to be echoed out of the
ESCC via the - TRxC pin (if this pin is
not being used as an input).

AUTO ECHO AND LOCAL
LOOPBACK
The ESCC is capable of automatically
echoing everything it receives. This
feature is useful mainly in Asynchronous modes, but works in Synchronous and SOLC modes as well. In
Auto Echo mode, TxO is RxO. Auto
Echo mode can be used with NRZI or
FM encoding with no additional delay,
because the data stream is not decoded before retransmission. In Auto
Echo mode, the -CTS input is ignored
as a transmitter enable (although transitions on this input can still cause
interrupts if programmed to do so). In
this mode, the transmitter is actually
bypassed and the pro-grammer is
responsible for disabling transmitter
interrupts and Wait/Request on transmit.

DATA ENCODING
The ESCC may be programmed to encode and decode the serial data in four
different ways (Figure 4). In NRZ encoding, a 1 is represented by a HIGH
level and a 0 is represented by a LOW
level. In NRZI encoding, a 1 is represented by no change in level and a 0 is
represented by a change in level.
In FM1 (more properly, bi-phase mark),
a transition occurs at the beginning of
every bit cell. A 1 is represented by

bit cell.

The ESCC is also capable of local
loopback. In this mode TxO is RxO, just
as in auto echo mode. However, in
localloopback mode, the internal
transmit data is tied to the internal
receive data and RxO is ignored (except
to be echoed out via TxO). The -CTS
and -OCO inputs are also ig-nored as
transmit and receive enables. However, transitions on these inputs can still
cause interrupts. Localloopback works
in asynchronous, synchronous, and
SOLC modes with NRZ, NRZI, or FM
coding of the data stream.
I/O INTERFACE CAPABILITIES
The ESCC offers the choice of polling,
interrupt (vectored or nonvectored), and
block transfer modes to transfer data,
status, and control information to and
from the CPU. The block transfer mode
can be implemented under CPU or
OMA control.
POLLING
All interrupts are disabled. Three status
registers in the ESCC are auto-matically
updated whenever any function is
performed. For example, end-of-frame
in SOLC mode sets a bit in one of these
status registers. The idea behind
polling is for the CPU to periodically
read a status register until the register
contents indicate the need for data to
be transferred. Only one register needs
to be read; depending on its contents,
the CPU either writes data, reads data,
or continues. Two bits in the register
indicate the need for data transfer.

FIGURE 4. DATA ENCODING METHODS
DATA
NRZ
NRZI

\'----..."

\'--""

FM1

FMO
MANCHESTER

579

\-----

\"",--

VLSI TECHNOLOGY, INC.
VL8530

An alternative is a poll of the Interrupt
Pending register to determine the
source of an interrupt. The status for
both channels resides in one register.

down -INT. The CPU then responds
with -INTACK, and the interrupting
device places the vector on the data
bus.

INTERRUPTS
When an SCC responds to an Interrupt
Acknowledge signal (-INTACK) from the
CPU, an interrupt vector may be placed
on the data bus. This vector is written in
Write Register 2 (WR2) and may be
read in Read Register 2A (RR2A) or
Read Register 2B (RR2B) (Figures 8).

In the SCC, the IP bit signals a AQ.Qd for
interrupt servicing. When an IP bit is 1
and the lEI input is high, the INT output
is pulled low, requesting an interrupt.
In the SCC, if the IE bit is not set by
enabling interrupts, then the IP for that
source can never be set. The IP bits
are readable in RR3A.

To speed interrupt response time, the
SCC can modify three bits in this vector
to indicate status. If the vector is read in
Channel A, status is never included; if it
is read in Channel B, status is always
included.

The IUS bits signal that an interrupt
request is being serviced. If an IUS is
set, all interrupt sources of lower
priority in the SCC and external to the
SCC are prevented from requesting
interrupts. The internal interrupt
sources are inhibited by the state of the
internal daisy chain, while lower priority
devices are inhibited by the lEO output
of the SCC being pulled LOW and
propagated to subsequent peripherals.
An IUS bit is set during an interrupt acknowledge cycle if there are no higher
priority devices requesting interrupts.

Each of the six sources of interrupts in
the SCC (Transmit, Receive, and
External/Status interrupts in both
channels) has three bits associated with
the interrupt source: Interrupt Pending
(IP), Interrupt Under Service (IUS), and
Interrupt Enable (IE). Operation of the
IE bit is straightforward. If the IE bit is
set for a given interrupt source, that
source can request interrupts. The
exception is when the MIE (Master
Interrupt Enable) bit in WR9 is reset and
no interrupts may be requested. The IE
bits are write only.
The other two bits are related to the
interrupt priority chain (Figure 5). As a
microprocessor peripheral, the SCC
may request an interrupt only when no
higher priority device is requesting one;
e.g., when lEI is high. If the device in
question requests an interrupt, it pulls

There are three types of interrupts:
transmit, receive, and external/status.
Each interrupt type is enabled under
program control with Channel A having
higher priority than Channel B, and with
receive, transmit, and external/status
interrupts prioritized in that order within
each channel. When the transmit
interrupt is enabled, the CPU is interrupted when the transmit buffer becomes empty. (This implies that the
transmitter must have had a data
character written into it so that it can
become empty.) When enabled, the

receiver can interrupt the CPU in one of
three ways:
• On first receive character or special
receive condition
• On all receive characters or special
receive condition
• On special receive condition only.
Interrupt on first character or special
condition and interrupt on special
condition only are typically used with
the Block Transfer mode. A special
receive condition is one of the following:
receiver overrun, framing error in
Asynchronous mode, end-of-frame in
SOLC mode, and optionally, a parity
error. The special receive condition
interrupt is different from an ordinary
receive character interrupt only in that
the status is placed in the vector during
the Interrupt Acknowledge cycle. In
interrupt on first receive character, an
interrupt can occur from special receive
conditions any time after the first receive
character interrupt.
The main function of the external/
status interrupt is to monitor the signal
transitions of the -CTS,-CCO, and
-SYNC pins; however, an external/
status interrupt is also caused by a
transmit underrun condition, or a zero
count in the baud rate generator, or by
the detection of a break (asynchronous
mode), abort (SOLC mode) or EOP
(SOLC loop mode) sequence in the data
stream.

FIGURE 5. INTERRUPT SCHEDULE

PERIPHERAL
+5V lEI 00-07 -INT -INTACK lEO

PERIPHERAL
lEI 00-07 -INT -INTACK lEO

PERIPHERAL
lEI 00-07 -INT -INTACK
+5V

-INTACK~----------~------------------~~----------------~

580

VLSI TECHNOLOGY, INC.
VL8530

The interrupt caused by the abort or
EOP has a special feature allowing the
SCC to interrupt when the abort or EOP
sequence is detected or terminated.
This feature facilitates the proper
termination of the current message,
correct initialization of the next message, and the accurate timing of the
Abort condition in external logic in SDLC
mode. In SDLC Loop mode, this feature
allows secondary stations to recognize
the need of the primary station to regain

control of the loop during a poll sequence.
CPUlDMA BLOCK TRANSFER
The SCC provides a Block Transfer
mode to accommodate CPU block
transfer functions and DMA controllers.
The Block Transfer mode uses the Wait!
Request output in conjunction with the
WaiVRequest bits in WR1. The Wait!
Request output can be defined under
software control as a Wait line in the

CPU Block Transfer mode or as a
Request line in the DMA Block Transfer
mode.
To a DMA controller, the SCC Request
output indicates that the SCC is ready to
transfer data to or from memory. To the
CPU, the Wait line indicates that the
SCC is not ready to transfer data,
thereby requesting that the CPU extend
the I/O cycle. The DTR/Request line
allows full-duplex operation under DMA
control.

PROGRAMMING
The SCC contains 13 write registers in
each channel that are programmed by
the system separately to configure the
functional personality of the channels.
In the SCC, register addressing is direct
for the data registers only, which are
selected by a high on the D/-C pin. In
all other cases (with the exception of
WRO and RRO), programming the write
registers requires two write operations
and reading the read registers requires
both a write and a read operation. The
first write is to WRO and contains three
bits that point to the selected register.
The second write is the actual control
word for the selected register, and if the
second operation is read, the selected
read register is accessed. All of the
registers in the SCC, including the data
registers, may be accessed in this
fashion. The pointer bits are automatically cleared after the read or write
operation so that WRO ( or RRO) is
addressed again.

Figures 6 through 13 and Figure 31
show the formats for each read register.

READ REGISTERS
The SCC contains ten read registers
(eleven counting receive buffer RR8) in
each channel. Four of these may be
read to obtain status information (RRO,
RR1, RR10, and RR15). Two registers
(RR12 and RR13) may be read to learn
the baud rate generator time constant.
The RR2 contains either the unmodified
interrupt vector (Channel A) or the
vector modified by status information
(Channel B). Both RR7 and RR6 read
the DMA FIFO. The RR3 contains the
Interrupt Pending (IP) bits (Channel A).

WRITE REGISTERS
The SCC contains 13 write registers (14
counting WR8, the transmit buffer) in
each channel. These write registers are
programmed separately to configure the
functional personality of the channels.
In addition, there are two registers (WR2
and WR9) shared by the two channels
that may be accessed through either of
them; WR2 contains the interrupt vector
for both channels, while WR9 contains
the interrupt control bits. Figures 14
through 28 and Figure 31 show the
format of each write register.

must be at least four PCLK cycles plus
200 ns.

INTERRUPT ACKNOWLEDGE CYCLE
TIMING
Figure 34 illustrates Interrupt Acknowledge cycle timing. Between the time
':"'INTACK goes low and the falling edge
of -RD, the internal and external IEIIIEO
daisy chains settle. If there is an
interrupt pending in the SCC and lEI is
high when -RD falls, the Acknowledge
cycle is intended for the SCC. In this
case, the SCC may be programmed to
respond to -RD low by placing its
interrupt vector on DO-D7 and it then
internally sets the appropriate InterruptUnder-Service latch.

The status bits of RRO arid RR1 are
carefully grouped to simplify status
monitoring; e.g., when the interrupt
vector indicates a special receive
condition interrupt, all the appropriate
error bits can be read from a single
register (RR1 ).

TIMING
The SCC generates internal control
signals from -WR and -RD that are
related to PCLK. Since PCLK has no
phase relationship with -WR and -RD,
the circuitry generating these internal
control signals must provide time for
metastable conditions to disappear.
This gives rise to a recovery time related
to PCLK. The recovery time applies
only between bus transactions involving
the SCC. The recovery time required for
proper operation is specified from the
rising edge of -WR or -RD in the first
transaction involving the SCC, to the
falling edge of WR or RD in the second
transaction involving the SCC. This time

READ CYCLE TIMING
Figure 32 illustrates Read cycle timing.
Addresses on A/-B and D/-C and the
status on -INTACK must remain stable
through the cycle. If -CE falls after -RD
falls or if it rises before -RD rises, the
effective -RD is shortened.
WRITE CYCLE TIMING
Figure 33 illustrates Write cycle timing.
Addresses on A/-B and D!-C and the
status on -INTACK must remain stable
throughout the cycle. If -CE falls after
-WR falls, or if it rises before -WR rises,
the effective -WR is shortened.

581

VLSI TECHNOLOGY, INC
VL8530

FIGURE 6. READ REGISTER 0

ID71D6ID~51D4~ID3~ID2~IDlll~

FIGURE 10. READ REGISTER 10

RXCHARACTERAVAILABLE

LZEROCOUNT
TX BUFFER EMPlY
DCD

SYNClHUNT
1-.._ _ _ _ _ _

CTS
TX UNDERRUN/EOM

TWO CLOCKS MISSING

L..-_ _ _ _ _ _ _ BREAK/ABORT

FIGURE 7. READ REGISTER 1

ID71D61D5~ID4~IOO~ID2~1111~
L

ALLSENT
RESIDUE CODE 2
RESIDUE CODE 1

ONE CLOCK MISSING

FIGURE 11. READ REGISTER 12

1D71D61D5~ID4~'I~ ~TL~RmE~

RESIDUE CODE 0
PARITY ERROR

TIME CONSTANT

TC4

RX OVERRUN ERROR
L..-_ _ _ _ _ _ CRClFRAMING ERROR

L-_ _ _ _ _ _

END OF FRAME (SDLC)

TCS
TC6
TC7

FIGURE 8. READ REGISTER 2
FIGURE 12. READ REGISTER 13

ID71D6ID~51D4~I~ ~J UP~R.=~
TIME CONSTANT

TC12
TC13
L-_ _ _ _ _ _ TC14
• MODIFIED IN B CHANNEL
TC15

FIGURE 9. READ REGISTER 3

ID71D61D5~ID4~IOO~ID2~IDto~
L

FIGURE 13. READ REGISTER 15

ID71D6ID~51D4~ltm:RO=NTE

CHANNELBEXTISTATIP'
CHANNEL B TX IP'
CHANNEL B RX IP •

L...::::

CHANNEL A EXT/STAT IP'
CHANNEL A TX IP •

DCD IE
SYNClHUNT IE

CHANNEL A RX IP •
L..-_ _ _ _ _ _ O

CTSIE
L-_ _ _ _ _ _ TX UNDERRUN/EOM IE

• ALWAYS 0 IN B CHANNEL

BREAK/ABORT IE

582

VLSI TECHNOLOGY, INC.
VL8530

FIGURE 14. WRITE REGISTER 0

FIGURE 17. WRITE REGISTER 3

REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
REGISTER 5
REGISTER 6
REGISTER 7
REGISTERS
REGISTER 9
REGISTER 10
REGISTER 11
REGISTER 12
REGISTER 13
REGISTER 14
REGISTER 15

NULLCODE
POINT HIGH
RESET EXT/STAT INTERRUPTS
SEND ABORT (SDLC)
ENABLE INT ON NEXT RX CHARACTER
RESETTXINT PENDING
ERROR RESET
RESET HIGHEST IUS

RXENABLE
SYNC CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SDLC)
RX CRC ENABLE
ENTER HUNT MODE
AUTO ENABLES

RX 5 BITS/CHARACTER
RX 7 BITS/CHARACTER
RX 6 BITS/CHARACTER
RX S BITS/CHARACTER

FIGURE 18. WRITE REGISTER 4

NULL CODE
RESET RX CRC CHECKER
RESET TX CRC GENERATOR
RESET TX UNDERRUNlEOM LATCH
• WITH POINT HIGH COMMAND

8 BIT SYNC CHARACATER
16 BIT SYNC CHARACTER
SDLC MODE (01111110 FLAG)
EXTERNAL SYNC MODE

FIGURE 15. WRITE REGISTER 1

D71 061

D~51
D~41 D~21111~
D31

Lo
o

0
1
1 0
1 1

L-.._ _ _

EXT INT ENABLE
TX INT ENABLE

PARITY IS SPECIAL CONDITION
RX INT DISABLE
RX INT ON FIRST CHARACTER OR SPCL. CONDITION
INT ON ALL Rx CHARACTERS OR SPCL. CONDITION
RX INT ON SPECIAL CONDITION ONLY
WAITIDMA REQUEST ON RECEIVE/-TRANS.

FIGURE 19. WRITE REGISTER 5

ID71D61D5ID4ugID~3It~

~~6~~ REQUEST

L-_ _ _ _ WAITIDMA REQUEST ENABLE

:RCENABLE

-SDLCICRC ·16
TXENABLE

FIGURE 16. WRITE REGISTER 2

SEND BREAK

ID7ID61D5~T@ ~~l~ffiRU~
~

TX 5 BITS (OR LESS)/CHARACTER
TX 7 BITSICHARACTER
TX 6 BITSICHARACTER
TX 8 BITS/CHARACTER
' -_ _ _ _ _ _ _ _ _ DTR

V'·lVECTOR
V5
V6
V7

583

VLSI TECHNOLOGY, INC.
VL8530

FIGURE 20. WRITE REGISTER 6

SYNC?
SYNC1
SYNC?
SYNC3
ADR?
ADR?

SYNC6
SYNCO
SYNC6
SYNC2
ADR6
ADR6

SYNCS
SYNCS
SYNCS
SYNC1
ADRS
ADRS

SYNC4
SYNC4
SYNC4
SYNCO
ADR4
ADR4

SYNC3
SYNC3
SYNC3
1
ADR3

SYNC2
SYNC2
SYNC2
1
ADR2

SYNC1
SYNC1
SYNC1
1
ADR1

SYNCO
SYNCO
SYNCO
1
ADRO

SYNC1

SYNCO
X
SYNC8
SYNC4

MONOSYNC, 8 BITS
MONOSYNC, 6 BITS
BISYNC, 16 BITS
BISYNC, 12 BITS
SDLC
SDLC
(ADDRESS RANGE)

FIGURE 21. WRITE REGISTER 7

SYNC?
SYNCS
SYNC1S
SYNC11

SYNC6
SYNC4
SYNC14
SYNC10

SYNCS
SYNC3
SYNC13
SYNC9

SYNC4
SYNC2
SYNC12
SYNC8

SYNC3
SYNC1
SYNC11
SYNC?

SYNC2
SYNCO
SYNC10
SYNC6

S84

X
SYNC9
SYNCS

MONOSYNC, 8 BITS
MONOSYNC, 6 BITS
BISYNC, 16 BITS
BISYNC, 12 BITS
SDLC

VLSI TECHNOLOGY, INC.
VL8530

FIGURE 22. WRITE REGISTER 9

ID7ID6ID5rrr~ :C

FIGURE 25. WRITE REGISTER 12
1071061051041031021011001

ug ~~ lOWERB~~

MIE
STATUS HIGf-V-STATUS LOW

TC4

TC5
TCS

NO RESET
CHANNEL RESET B
CHANNEL RESET A
FORCE HAROWARE RESET

TC7

FIGURE 26. WRITE REGISTER 13
1071061051041031021011001

I~
ug~: I~ERB~OF

FIGURE 23. WRITE REGISTER 10
1071061051041031021011001

6BITI-8BITSYNC

0-0

01
"i 0
j::!:

LOOPMOOE

TC121TIME CONSTANT

ABORT/-FLAG ON UNOERRUN

TC13

MARK/-FLAG 10LE

TC14

GO ACTIVE ON POLL

TC15

NRZ
NRZI
FM1 (TRANSITION = 1)
FMO (TRANSITION = 0)

°llli

FIGURE 27. WRITE REGISTER 14
07 06 05
CRC PRESET IH)

04~1
0~211'1~
31

BR GENERATOR ENABLE

L- BR GENERATOR SOURCE

FIGURE 24. WRITE REGISTER 11

-OTRIREQUEST FUNCTION
AUTO ECHO

1071061051041031021011001

LOCAL LOOPBACK

11':1 !1=~~gg~:~~~~;~OCK

a NUll COMMANO
ENTER SEARCH MOOE
RESET MISSING CLOCK
OISABlE OPLL
SET SOURCE .. BR GENERATOR
SET SOURCE .. -RTXC
SETFM MODE
SET NRZI MOOE

1 a -TRXC OUT = BR GENERATOR OUTPUT
1 1 - TRXC OUT = OPLL OUTPUT
-TRXCOI-I

a
a
1
1

a
1
a
1

TRANSMIT CLOCK = -RTXC PIN
TRANSMIT CLOCK = - TRXC PIN
TRANSMIT CLOCK = BR GEN. OUTPUT
TRANSMIT CLOCK = OPLL OUTPUT

RECE IVE
RECEIVE
RECEIVE
RECEIVE

FIGURE 28. WRITE REGISTER 15

1071D6105Iwg~T@

CLOCK = -RTXC PIN
CLOCK = - TRXC PIN
CLOCK = BR GEN. OUTPUT
CLOCK = OPLL OUTPUT

:rnOOOUNTIE

COCOIE

' - - - - - - - - - - -RTXCXTAU-NOXTAL

SYNCIHUNT IE
CTSIE
TX UNOERRUNlEOM IE
BREAK/ABORT IE

585

VLSI TECHNOLOGY, INC.
VL8530

FIGURE 29. READ CYCLE TIMING

X'-____

AI-B.O/-C

-INTACK

,,----

=.7'
~

-CE

"'---_/
X
)>-----

-RD

00-07

X____

A_OO_R_E_SS_V_A_LlO
______

-----------«

DATA VALID

FIGURE 30. WRITE CYCLE TIMING

X_____

AI-B.O/-C

-INTACK

X____

A_OD_R_E_SS_V_A_Ll_O_ _ _ _

,,----

=.7'
~

-CE

-WR
00-07

--------«

DATA VALID

»)-----

FIGURE 31. INTERRUPT ACKNOWLEDGE CYCLE TIMING

-INTACK

-RD

00-07

~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _/

--~

-JX

( ___

586

VECTOR

)>-----

VLSI TECHNOLOGY, INC.
VL8530

FIGURE 32. READ AND WRITE TIMING (SEE TABLE 1)

PCLK
AJ-B, D/-C

-:,.-

::x

-INTACK
~

-CE

.Q)

~ ~J.tt~
r:::----r~.
~

_. +--.
[~I+- ~

14---C 9)_ ~ ~V_~~r-

!~~

-®--

I~ ~ ...

....

_~31

-#<

DO-D7

.....

~ ~ VALID

ACTIVE

®-I" ~

READ

00-07

X
!@-I"

WRITE

-WI-REO
WAIT

.....

1~3])

....

~II

. '7
~

.....

-WI-REO
REOUEST

® r~
~

(2~

-DTRI-REO
REOUEST

...

.....

r\~

-WR

.~ I+®~~ ~I+

~~I"-'

-AD

.....

~ ~ ~

~ ~.

/,-.

.....

-INT

...

'36'

~
...J
I

FIGURE 33. RESET TIMING (SEE TABLE 1)

-WR

-RD

FIGURE 34. CYCLE TIMING (SEE TABLE 1)

-CE

_ _ _ _ _ _ _ _J~

-RD OR -WR _ _ _

,,~__________

J;=--=------i@l------=--==:±~

, , ' -_ _ _ _ _/

587

' - -

VLSI TECHNOLOGY, INC.
VL8530

TABLE 1. READ AND WRITE TIMING CHARACTERISTICS:
No. Symbol

TwPCI
TwPCh
TfPC
TrPC
TcPC
TsA(WR)
ThA(WR)
TsA(RDl
ThA(RDl
TslA(PC)
TsIAHWR\
ThlA(WR)
TslAi(RDl
ThlA(RDl
ThlA(PC)
TsCE1lWR\
ThCE(WR)
TsCEhlWR)
TsCE1(RD)
ThCE(RD)
TsCEh(RD)
TwRD1
TdRD(DRA)
TdRDr(DR)
TdRDflDR)
TdRD(DRz)
TdA(DR)

PCLK Low Wic;th
PCLK Hiqh Width
PCLK Fall Time
PCLK Rise Time
PCLK Cycle Time
Address to -WR Setup Time
Address to -WR Hold Time
Address to -AD Setup Time
Address to -RD Hold Time
-INTACK to PCLK Setup Time
-INTACK to -WR Setup Time
-INTACK to -WR Hold Time
-INTACK to -RD SetupTime
-INTACK to -RD Hold Time
-INTACK to PCLK Hold Time
-CE Low to -WR Setup Time
-CE to -WR Hold Time
-CE Hiqh to -WR Setup Time
-CE Low to -RD Setup Time
-CE to -RD Hold Time
-CE Hiah to -RD Setup Time
-RD Low Width
-RD to Read Data Active Delay
-RD to Read Data Not Valid Delay
-RD to Read Data Valid Delay
-RD to Read Data Float Delay
Address Required Valid to
Read Data Valid Delav

28
29
30
31
32
33
34
35

TwWR1
TsDW(WR)
ThDW(WR)
TdWR(W)
TdRD(W)
TdWRf(REO)
TdRDf(REO)
TdWRr(REO)

-WR Low Width
Write Data to -WR Setup Time
Write Data to -WR Hold Time
-WR to Wait Valid Delay
-RD to Wait Valid Delay
-WR to -WI-REO Not Valid Delay
-RD to -WI-REO Not Valid Delay
-WR to -DTR/-REO Not Valid Delay

36 TdRDr(REO)

-RD to -DTR/-REO Not Valid Delay

37
38
39
40
41
42
43
44
45
46
47
48
49

TdPC(lNT)
TdIAi(RD)
TwRDA
TdRDA(DR)
TsIEI(RDA)
ThIEI(RDA
TdIEI(IEO)
TdPC(IEO)
TdRDA(INT)
TdRD(WRO)
TdWRO(RD)
TwRES
Trc

4MHz

Parameter

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

TA=O°CTO+70°C

6MHz

Min

Max

105
105

2000
2000
20
20
4000

250
80
0
80
0
0
200
0
200
0
100
0
0
100
0
0
100
390
0
0

Min
70
70

165
80
0
80
0
0
160
0
160
0
100
0
0
70
0
0
70
250
0
0

250
70
590
390
0
0

PCLK to -I NT Valid Delay
-INTACK to -RD (Acknowledqe) Delay
-RD (Acknowledge) Width
-RD (Ack.) to Read Data Valid Delay
lEI to -RD (Acknowledqe) Setup Time
lEI to -RD (Acknowledqe) Hold Time
lEI to lEO Delay Time
PCLK to lEO Delay
-RD to -INT Inactive Delay
-RD to -WR Delay for No Reset
-WR to -RD Delay for No Reset
-WR and -RD Coincident Low for Reset
Valid Access Recovery Time

Max

Notes

2
2

2
2
2
2

3·

250
0
0
200
200
200
200
(5TcPC
+250)
(5TcPC
+250)
500
250
250

250
285
190

5
5

5
6

180
100
0

120
0
120
250
500

588

Min

1000
1000
10
15
2000

180
45
420

240
240
240
240
(5TcPC
+300)
(5TcPC
+300)
500

30
30
250
(6TcPC
+200)

Max

100
250
500
15
30
250
(STcPC
+130)

VLSI TECHNOLOGY, INC.
VL8530

Read and Write Timing Notes:
1. Units are in nanoseconds.
2. Parameter does not apply to Interrupt Acknowledge transactions.
3. Float delay is defined as the time required for a ± 0.5 V change at the output with a maximum de load and minimum ae load.
4. Parameter applies only between transactions involving the ESCC.
5. Open-drain output, measured with open-drain test load.
6. Parameter is system-dependent. For any ESCC in the daisy chain, TdIAi(RD) must be greater than the sum of TdPC (lEO) for
the highest priority device in the daisy chain, TsIEI(RDA) for the ESCC, and TdIElf(IEO) for each device separating them in the
daisy chain.
FIGURE 35. INTERRUPT ACKNOWLEDGE TIMING (SEE TABLE 1)

PCU<

-INTACK--------_.

-AD

DATA

lEI

lEO

INT

______________________________________I~.:~~~~~_~_:~~~~:;t.~----------------___

589

G VLSI

TECHNOLOGY, INC

VL8530

FIGURE 36. GENERAL TIMING (SEE TABLE 2)

PCLK

-WI-REO
REOUEST

-W~REO ___________________~-+

WAIT

-RTxC,
-TRxC
RECEIVE

______________________________

------::::::-:--:---:1

AxD

-SYNC
EXTERNAL _ _ _ _ _

~~------+------_J

\.I~;fj.-.--..@r------w:L __

- TAxC, -RTxC
TRANSMIT

TxD

-TAxC
OUTPUT

-RTxC

~ll~M
~
~
{
'------ :
~
~ ---~'--

-TRXC----,\

-CrS.-DeD.-RI

r+-®-~~====='=~====::::::::::::::::=)L

>S---@:1<--------h_

{+---®---h~t1,-_
i.~(

- __-----------~~~-------C@:+h+__@_+{
-------------/I~!Ii~ ~

590

VLSI TECHNOLOGY, INC.
VL8530

TABLE 2. GENERAL TIMING
No. Symbol

Parameter

4 MHz

1
2
3

TdPCCREO)
TdPC(W)
Ts RXC(PC)

4
5
6
7
8
9

TsRXD RXCr
ThRXD RXCn
TsRXD RXCf
ThRXD RXCf
TsSY1RXC)
ThSY(RXC)

PCLK to -WI-REO Valid Delav
PCLK to Wait Inactive Delav
-RxC to PCLK Setup Time
(PCLK + 4 Case Only)
RxD to -RxC Setu~ Time(X1 Mode)
RxD to -RxC Hold Time(X1 Mode)
RxD to -RxC Setup Time (X1 Mode)
RxD to -RxC Hold Time (X1 Mode)
-SYNC to -RxC Setup Time
-SYNC to -RxC Hold Time

10
11
12
13
14
15
16
17
18
19
20
21
22

TsTXC(PC)
TdTXCf(TXD
TdTXCr(TXD)
TdTXD(TRX)
TwRTXh
TwRTXI
TcRTX
TcRTXX
TwTRXh
TwTRXI
TcTRX
TwEXT
TwSY

- TxC to PCLK Setup Time
- TxC to TxD Delay (X1 Mode)
- TxC to TxD DelatlX1 Model
TxD to -TRxC Delay (Send Clk Echo)
-RTxC High Width
-RTxC Low Width
-RTxC Cycle Time
Crystal Oscillator Period
- TRxC High Width
- TRxC Low Width
- TRxC Cy_c1e Time
-DCD or -CTS Pulse Width
-SYNC Pulse Width

6MHz

Max

Min

250
350
Tv.PC1

Min

Max

0
150
0
150
-200

Max

Notes

2,5
2
2
26
2,6
42
4,2

0
150
0
150
-200
3TcPC
+200
0

3TcPC
+200
0
300
300
200
180
180
400
250
180
180
400
200
200

Min

250
350
Tv.PC1

1000

3,5
3
3,5

230
230
200
180
180
400
250
180
180
400
200
200

7
7
7
3
47
47
47

1000

TABLE 3. SYSTEM TIMING
No. Symbol

1
2
3
4
5
6
7
8
9
10

TdRXC(REO)
TdRXCCW)
TdRXC SY)
TdRXC INT)
TdTXC REO)
TdTXC W)
TdTXC ORO)
TdTXC INT)
TdSY(INTl
TdEXT INT)

Parameter

6 MHz

4 MHz

-AxC to -WI-REO Valid Delay
-AxC to Wait Inactive Delav
-AxC to -SYNC Valid Delay
-AxC to -INT Valid Delay
-TxC to -WI-REO Valid Delay
-TxC to Wait Inactive Delav
- TxC to -DTRI-AEO Valid Delay
-TxC to -INT Valid Delav
-SYNC to -INT Valid Delav
-OCD or -CTS to -I NT Valid Delay

Min

Max

8
8
4
10
5
5
4
6
2
2

12
12
7
16
8
8
7
10
6
6

Min
8
8
4
10
5
5
4
6
2
2

Max

Min

Max

Notes

12
12
7
16
8
8
7
10
6
6

General and System Timing Notes:
1. Open-clraln output, measured with open-clrain test load.
2. RxC is RTxC or TRxC, whichever is supplying the transmit clock.
3. TxC is TRxC or RTxC, whichever is supplying the transmit clock.
4. Both TrxC and SYNC have 30 pF capacitors connected to ground.
5. Applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between RxC and
PCLK or TxC and PCLK is required.
6. Applies only to FM encoding/decoding.
7. Applies only for transmitter and receiver; DPLL and baud rate generator timing are identical to chip PCLK requirements.
8. Units are in nanoseconds (ns).

591

2
12
2
12
3
13
3
13
1
1

VLSI TECHNOLOGY, INC.

VL8530

FIGURE 37. SYSTEM TIMING (SEE TABLE 3)
-RTxC, - TRxC
RECEIVE

-WI-REO
REQUEST

•

-WI-REO
WAIT

•

-SYNC
OUTPUT

-I NT

04
-RTxC, -TRxC
TRANSMIT

-WI-REO
REOUEST

•

-WI-REO
WAIT

•

-OTR/-REO
REOUEST

-INT

-CTS, -oco, -RI

--,
...:=l

K
:~

-SYNC
INPUT

•

-INT

•
592

.®

..
'\~

•

VLSI TECHNOLOGY, INC.
VL8530

ABSOLUTE MAXIMUM RATINGS
Voltages on all pins
with respect to GND

-0.3V to 7.0V

Operating Ambient
Temperature

O°C to +70°C

Storage Temperature -65°C to + 150°C

Stresses above those listed under
"Absolute Maximum Ratings" may
cause permanent damage to the
device. These are stress ratings only.
Functional operation of this device at
these or any other conditions above
5V

STANDARD TEST
CONDITIONS
The d.c characteristics and capacitance
section below apply for the following
standard test conditions, unless otherwise noted. All voltages are referenced
to GND. Positive current flows into the
referenced pin.
Standard conditions are as follows:

those listed on the operational sections
of this specification is not implied and
exposure to absolute maximum ratings
conditions for extended periods may
affect device reliability.

2.1 kn

2.2kn
100 pF

• +4.75 V ~ Vcc ~ +5.25 V
• GND = 0 V
• TA as shown in Ordering Information

FROM OUTPUTUNDER TEST

50 pF

DC CHARACTERISTICS: vcc = 5 V ± 5%, TA = O°C to 70°C
Symbol

Parameter

Min

Max

VIH

Input High Voltage

2.0

VCC+0.3

Vil

Input low Voltage

-0.3

0.8

VOH

Ouput High Voltage

2.4

VOL

Output low Voltage

III

Input leakage

IOl

Output leakage

ICC

VCC Supply Current

CAPACITANCE:

IOH = -250 IlA

IOH =+2.0 mA

±10.0

IlA

0.4 V ~ VIN ~ +2.4 V

±10.0

IlA

0.4 V ~ VIN ~ +2.4 V

250

rnA

0.4

Clock Frequency = 8 MHz

TA=0°Cto70°C,f=1 MHz

Symbol

Parameter

CIN

Input Capacitance

COU

Output Capacitance

ClIO

Conditions

Unit

Min

Bidirectional Capacitance

593

Max

Unit

Conditions
Unused Inputs Grounded

Unused Inputs Grounded

VLSI TECHNOLOGY, INC.

594

VLSI TECHNOLOGY, INC.
VL85C30
ENHANCED SERIAL COMMUNICATIONS CONTROLLER (ESCC)

FEATURES

DESCRIPTION

• Enhanced SCC functions support
DMA
- 14-bit byte counter
- 19-bit-wide FIFO

• Low power consuming CMOS

The VL85C30 CMOS Enhanced Serial
Communications Controller (ESCC) is a
dual-channel, multi-protocol data
communications peripheral designed
for use with non-multiplexed buses.
The ESCC can be software configured
for a wide variety of serial communications applications. The device contains
a variety of new, sophisticated internal
functions, including all of the features of
the NMOS 8530. In addition, the
VL85C30 Enhanced SCC contains a 10
x 19-bit FIFO array and 14-bit byte
counter. These features, in addition to
the new higher clock frequency
capabilities, allow the ESSC to be used
with a direct memory access (DMA)
controller.

PIN DIAGRAM

BLOCK DIAGRAM

• Completely downward compatible
with the NMOS 8530
• Two independent full-duplex channels
• Programmable clock factor
• Break generation and error detection
• Intelligent SDLCIHDLC
• Localloopback and auto echo modes
• Internal or external character
synchronization

The ESCC handles asynchronous formats, such synchronous byte-oriented
protocols as IBM Bisync and such
synchronous bit-oriented protocols as
HDLC and IBM SDLC. This versatile
device supports virtually any
serial data transfer application (cassette, diskette, tape drives, etc.),
including DMA.
The device can generate and check
CRC codes in any synchronous mode
and can be programmed to check data
integrity in various modes. The ESCC
also has facilities for modem controls in
both channels, in addition to its Byte Counting Register and FIFO in SDLC
mode.

SERIAL DATA

VLB5C30
01

D3
05
07

INT
lEO
IE1
-INTACK

vee
-W/-REQA
-SYNCA
-RTXCA
RXOA
-TRXCA
TXOA
-DTRI-REQA
-RTSA
-CTSA
-DeOA
PCLK

04
06
-RD
-WR
AlB
-CE
O/-C

MOOEM.DMA. OR
OTHER CONTROLS
CONT
DATA
MODEM.DMA. OR
OTHER CONTROLS

GND
-W/-REQB
-SYNCB
-RTXCB
RXDB
-TRXCB
TXOB
-DTRI-REQB
-RTSB
-CTSB
-DC DB

SERIAL DATA

L...-_---I~

CHANNEL CLOCKS
-SYNC
-WAIT/-flEQUEST

ORDER INFORMATION
Part
Number

Clock
Frequency

Package
VL85C30-8PC
Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
VLBSC30-80C
8MHz
Ceramic DIP
VL85C30-8CC
VL85C30-1 OPC
Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
VL85C30-100C
10 MHz
Ceramic DIP
VL85C30-10CC
VL85C30-12PC
Plastic DIP
VL85C30-120C
Plastic Leaded Chip Carrier (PLCC)
12 MHz
Ceramic DIP
VL8SC30-12CC
Nole: Operating temperature range is O°C to +70°C.

595

VLSI TECHNOLOGY, INC
VL85C30

PIN DIAGRAM
lEO

AI-8

lEI

-CE

-INTACK
VCC
-W/-REQA
-SYNCA
-RTXCA
RXDA
-TRXCA
TXDA
N.C.

D/-C

N.C.
GND
-W/-REQ8
-SYNC8
-RTXC8
RXD8
-TRXC8
TXD8

-DT~-REQA

-CTSAPCLK -CTS8 -DTRREQ8

SIGNAL DESCRIPTIONS
Signal
Name

DIPPln
Number

Signal
Description

AI-B

Channel AlChannel B Select - This input signal selects the channel on which the read or
write operation occurs.

-CE

Chip Enable - This active low input signal selects the ESCC for a read or write operation.

-CTSA,
-CTSB

18,
22

Clear To Send - Active low inputs - If these pins are programmed as auto enables, a low on
the inputs enables the respective transmitters. If not programmed as auto enables, they may
be used as general-purpose inputs. Both inputs are Schmitt trigger buffered to accommodate slow rise time inputs. The ESCC detects pulses on these inputs and can interrupt the
CPU on both logic level transitions.

D/-C'

Data/Control Select - This input signal defines the type of information transferred to or from
the ESCC. A HIGH means data is transferred; a low indicates a command.

-DCDA,
-DCDB

19
21

Data Carrier Detect - Active low inputs - These pins function as receiver enables if they are
programmed for auto enables; otherwise, they may be used as general-purpose input pins.
Both pins are Schmitt trigger buffered to accomodate slow rise time signals. The ESCC
detects pulses on these pins and can interrupt the CPU on both logic level transitions.

DO-D7

40,1,39,2,38,

Data Bus - These bidirectional, three-state lines carry data and commands to and from the
ESCC.

-DTRI-REOA
-DTRI-REOB

16,
24

lEI

lEO

Interrupt Enable Out - Active high output - lEO is high only if lEI is high and the CPU is not
servicing an ESCC interrupt or the SCC is not requesting an interrupt (Interrupt Acknowledge
cycle only). lEO is connected to the next lower priority device's lEI input and thus inhibits
interrupts from lower priority devices.

-I NT

Interrupt Request - Active low open-drain output - This signal is activated when the ESCC
requests an interrupt.

596

VLSI TECHNOLOGY, INC.
VL85C30

SIGNAL .DESCRIPTIONS (Cont.)
Signal
Name

DIP Pin
Number

Signal
Description

-INTACK

Interrupt Acknowledge - Active low input - This signal indicates an active Interrupt Acknowledge cycle. During this cycle, the ESCC interrupt daisy chain settles. When -RD be-comes
active, the ESCC places an interrupt vector on the data bus (if lEI is high). The -INTACK
signal is latched by the rising edge of PCLK.

PCLK

Clock - This input is the master ESCC clock used to synchronize internal signals. PCLK is a
TIL level signal.

-RD

Read - Active low input - This signal indicates a read operation and, when the ESCC is selected, enables the ESCC's bus drivers. During the Interrupt Acknowledge cycle, this signal
gates the interrupt vector onto the bus if the ESCC is the highest priority device requesting an
interrupt.

RXDA,
RXDB

13,

Receive Data - Active high inputs - These input signals receive serial data at standard TIL
levels.

-RTXCA,
-RTXCB

-RTSA,
-RTSB

-SYNCA,
-SYNCB

12,

17,

11,

TXDA,
TXDB

15,
25

Transmit Data - Active high outputs - These output signals transmit serial data at standard
TIL levels.

-TRXCA,
-TRXCB

14,
26

-WR

Write - Active low input - When the ESCC is selected, this signal indicates a write operation.
The coincidence of -RD and -WR is interpreted as a reset.

-W/-REQA,
-W/-REQB

10,
30

Wait/Request - Open-drain outputs when programmed for a wait function, driven high or low
when programmed for a Request function - These dual-purpose outputs may be programmed
as Request lines for a DMA controller or as Wait lines to synchronize the CPU to the ESCC
data rate. The reset state is Wait.

597

VLSI TECHNOLOGY, INC
VL85C30

FUNCTIONAL
DESCRIPTION
The functional capabilities of the ESCC
can be described from two different
points of view. As a data communications device, it transmits and receives
data in a wide variety of data communications protocols. As a microprocessor
peripheral, the ESCC offers valuable
features as vec-tored interrupts, polling,
and simple handshake capability.
DATA COMMUNICATIONS
CAPABILITY

The ESCC provides two independent
full-duplex channels programmable for
use in any common asynchronous or
syn-chronous data communication
protocol. Figure 1 and the following
description briefly detail these protocols.
Asynchronous modes - Transmission
and reception can be accomplished
independently on each channel with 5
to 8 bits per character, plus optional
even or odd parity. The transmitters
can supply 1, 1 112, or 2 stop bits per
character and a break output at any
time. The receiver break-detection logic
interrupts the CPU both at the start and
at the end of a received break.
Reception is protected from spikes by a
transient spike-rejection mechanism
that checks the signal one-half a bit
time after a low level is detected on the
receive data input (RXOA or RXOB). If
the low does not persist (as in the case
of a transient), the character assembly
process does not start.
Framing errors and overrun errors are
detected and buffered together with the
partial character on which they occur.
Vectored interrupts allow fast servicing
or error conditions using dedicated
routines. Furthermore, a bUilt-in
checking process avoids the interpretation of a framing error as a new start bit:
a framing error results in the addition of
one-half a bit time to the point at which
the search for the next start bit begins.
The ESCC does not require symmetric
transmit and receive clock signals
a feature allowing use of the wide variety of clock sources. The transmitter
and receiver can handle data at a rate
of 1, 1/1G, 1/32, or 1/G4 of the clock rate
supplied to the receive and transmit
clock inputs. In asynchronous modes,

the -SYNC pin may be pro-grammed as
an input used for such functions as
monitoring a ring indicator.

programmed to send an idle line consisting of continuous flag characters or
a steady marking condition.

Synchronous modes. The ESCC
supports both byte-oriented and bitoriented synchronous communication.
Synchrono.us byte-oriented protocols
can be handled in several modes, allowing character synchronization with a
G-bit or 8-bit synchronous character
(Monosync) any 12-bit synchroni-zation
pattern (Bisync), or with an external
synchronous signal. Leading sync
characters can be removed without
interrupting the CPU.

If a transmit underrun occurs in the
middle of a message, an external/status interrupt warns the CPU of this
status change so that an abort may be
issued. The ESCC may also be programmed to send an abort itself in case
of an underrun, relieving the CPU of this
task. One to eight bits per character
can be sent, allowing recep-tion of a
message with no prior infor-mation
about the character structure in the
information field of a frame.

5- or 7-bit synchronous characters are
detected with 8- or 1G-bit patterns in the
ESCC by overlapping the larger pattern
across multple incoming synchronous
characters.
The CRC checking for synchronous
byte-oriented modes is delayed by one
character time so that the CPU may
disable CRC checking on specific
characters. This allows the implementation of IBM Bisync. protocols.
Both CRC-1G (X,. + Xli +XI + 1) and
CCITT (Xl' + Xli + X'+ 1) error checking
polynomials are supported. Either
polynomial may be selected in all
Synchronous modes. Users may preset
the CRC generator and checker to all
ones or all zeros. The ESCC also provides a feature that automatically
transmits CRC data when no other data
is available for transmission. This
allows for high-speed transmissions
under OMA control, with no need for
CPU intervention at the end of a message. When there is no data or CRC to
send in synchronous modes, the
transmitter inserts G-, 8-, or 1G-bit
synchronous characters, regardless of
the programmed character length.
The ESCC supports synchronous bitoriented protocols, such as SOLC and
HOLC, by performing automatic flag
sending, zero insertion, and CRC generation. A special command can be
used to abort a frame in transmission.
At the end of a message, the ESCC
automatically transmits the CRC and
trailing flag when the transmitter underruns. The transmitter may also be

598

The receiver automatically acquires
synchronization on the leading flag of a
frame in SOLC or HOLC and provides a
synchronization signal on the -SYNC
pin (an interrupt can also be programmed). The receiver can be
programmed to search for frames
addressed by a single byte (or four bits
within a byte) of a user-selected
address or to a global broadcast
address. In this mode, frames not
matching either the user-selected or
broadcast address are ignored. The
number of address bytes can be
extended under software control. For
receiving data, an interrupt on the first
received character, or an interrupt on
every character, or on special con-dition
only (end-of-frame) can be selected.
The receiver automatically deletes all
zeros inserted by the transmitter during
character assembly. The CRC is also
calculated and is automatically checked
to validate frame transmission. At the
end of transmission, the status of a
received frame is availabe in the status
registers. In SOLC mode, the ESCC
must be programmed to use the SOLC
CRC polynomial, but the generator and
checker may be preset to all ones or all
zeros.
The CRC is inverted before transmission and the receiver checks against
the bit pattern 0001110100001111.
The NAZ, NAZI, or FM coding may be
used in any 1x mode. The parity
options available in asynchronous
modes are available in synchronous
modes.

VLSI TECHNOLOGY, INC.
VL85C30

The ESCC can be conveniently used
under DMA control to provide highspeed reception or transmission. In
reception. for example. the ESCC can

interrupt the CPU when the first
character of a message is received.
The CPU then enables the DMA to

transfer the message to memory. The
ESCC then issues an end-of-frame
interrupt and the CPU can check the
status of the received messsage.

FIGURE 1. ESCC PROTOCOLS

MARKING LINE

MARKING LINE
ASYNCHRONOUS
SYNC

DATA

CRC1

CRC2

DATA

CRC1

CRC2

DATA

CRC1

CRC2

CRC1

CRC2

MONO SYNC
SYNC

SYNC

DATA
BISYNC
DATA
EXTERNAL SYNC

FLAG

ADDRESS
SDLC/HDLC/X.25

599

FLAG

VLSI TECHNOLOGY, INC.
VL85C30

The CPU is thereby freed for other
service while the message is being
received. The CPU may also enable
the OMA first and have the ESCC interrupt only on end-of-frame. This
procedure allows all data to be transferred via the OMA.
SDLC LOOP MODE
The ESCC supports SOLC loop mode
in addition to normal SOLC. In an
SOLC loop, there is a primary controller station that manages the message
traffic flow on the loop and any number
of secondary stations. In SOLC loop
mode, the ESCC performs the functions of a secondary station while an
ESCC operating in regular SOLC mode
can act as a controller (Figure 3).
A secondary station in an SOLC Loop
is always listening to the messages
being sent around the loop, and in fact
must pass these messages to the rest
of the loop by retransmitting them with
a one-bit time delay. The secondary
station can place ~s own message on
the loop only at specific times. The
controller signals that secondary stations may transmit messages by
sending a special character, called an
End Of Poll (EOP), around the loop.
The EOP character is the bit pattern
11111110. Because of zero insertion
during messages, this b~ pattern is
unique and easily recognized.

When a secondary station has a message to transmit and recognizes an
EOP on the line, ~ changes the last
binary 1 of the EOP to a 0 before
trans-mission. This has the effect of
turning the EOP into a flag sequence.
The secondary station now places ~s
message on the loop and terminates
the message w~h an EOP. Any secondary stations, further down the loop
with messages to transm~, can then
append their messages to the
message of the first secondary station
without messages to send. The
following stations merely echo the
incoming messages and are prohibited from placing messages on the
loop (except upon recognizing an
EOP). The SOLe loop mode is a
programmable option in the ESCC;
NRZ, NRZI, and FM coding may all be
used in SOLC Loop mode.
BAUD RATE GENERATOR
Each channel in the ESCC contains a
programmable baud rate generator.
Each generator consists of two 8-b~
time constant registers that form a 16bit time-constant, a 16-b~ down
counter, and a flip-flop on the output
producing a square wave. On startup,
the flip-flop on the output is set in a
HIGH state, the value in the timeconstant register is loaded into the
counter, and the counter starts counting down. The output of the baud rate
generator toggles upon reaching 0,
the value in the time-constant register

FIGURE 2. DETECTING 5- OR 7-BIT
SYNCHRONOUS CHARACTERS

The output of the baud rate generator
may be used as either the transmit
clock, the receive clock, or both. It can
also drive the digital phase-locked loop
(see next section).

Hthe receive clock or transmit clock is
not programmed to come from the
- TRxC pin, the output of the baud rate
generator may be echoed out via the
-TRxCpin.
The following formula relates the time
constant to the baud rate (the baud rate
is in bits/second and BR clock period is
in seconds):
baud rate =

2 (time constant+2) x (BR clock period)
DIGITAL PHASE-LOCKED LOOP
The ESCC contains a digital phaselocked-loop (OPLL) to recover clock
information from a data stream with
NRZI or FM encoding. The OPLL is
driven by a clock that is nominally 32
(NRZI) or 16 (FM) times the data rate.
The OPLL uses this clock, along with
the data stream, to construct a clock
for the data. This clock may then be
used as the ESCC receive clock, the
transmit clock, or both.

FIGURE 3. AN SDLC LOOP

5 BITS

1++1

I ~YNC I SYN? I SYNC I DATA I DATA I DATA I DATA I
1"'6~

~16

process is repeated. The time constant
may be changed at any time, but the
new value does not take effect until the
next load of the counter.

600

VLSI TECHNOLOGY, INC.
VL85C30

For NRZI encoding, the DPLL counts
the 32x clock to create nominal bit
times. As the 32x clock is counted, the
DPLL is searching the incoming data
stream for edges (either 1 to a or a to
1). Whenever an edge is de-tected, the
DPLL makes a count adjustment (during
the next counting cycle), producing a
terminal count closer to the center of the
bit cell.

an additional transition at the center of
the bit cell and a a is represented by no
additional transition at the center of the
bit cell. In FM0 (bi-phase space), a
transition occurs at the beginning of
every bit cell. A a is represented by an
additional transition at the center of the
bit cell, and a 1 is represented by no
additional transition at the center of the

For FM encoding, the DPLL still counts
from a to 31, but with a cycle corresponding to two bit times. When the
DPLL is locked, the clock edges in the
data stream should occur between
counts 15 and 16, and between counts
31 and O. The DPLL looks for edges
only during a time centered on the 15 to
16 counting transition.

In addition to these four methods, the
ESCC can be used to decode Manchester (bi-phase level) data by using the
DPLL in the FM mode and programming the receiver for NRZ data.
Manchester encoding always produces
a transition at the center of the bit cell.
If the transition is 0 to 1, the bit is a O. If
the transition is 1 to 0, the bit is a 1.

The 32x clock for the DPLL can be
programmed to come from either the
-RTxC input or the output of the baud
rate generator. The DPLL output may
be programmed to be echoed out of the
ESCC via the - TRxC pin (if this pin is
not being used as an input).

AUTO ECHO AND LOCAL
LOOPBACK
The ESCC is capable of automatically
echoing everything it receives. This
feature is useful mainly in Asynchronous modes, but works in Synchronous and SDLC modes as well. In
Auto Echo mode, TxD is RxD. Auto
Echo mode can be used with NRZI or
FM encoding with no additional delay,
because the data stream is not decoded before retransmission. In Auto
Echo mode, the -CTS input is ignored
as a transmitter enable (although transitions on this input can still cause
interrupts if programmed to do so). In
this mode, the transmitter is actually
bypassed and the pro-grammer is
responsible for disabling transmitter
interrupts and Wait/Request on transmit.

DATA ENCODING
The ESCC may be programmed to encode and decode the serial data in four
different ways (Figure 4). In NRZ encoding, a 1 is represented by a HIGH
level and a a is represented by a LOW
level. In NRZI encoding, a 1 is represented by no change in level and a a is
represented by a change in level.
In FM1 (more properly, bi-phase mark),
a transition occurs at the beginning of
every bit cell. A 1 is represented by

bit cell.

The ESCC is also capable of local
loopback. In this mode TxD is RxD, just
as in auto echo mode. However, in
local loop back mode, the internal
transmit data is tied to the internal
receive data and RxD is ignored (except
to be echoed out via TxD). The -CTS
and -DCD inputs are also ig~nored as
transmit and receive enables. However, transitions on these inputs can still
cause interrupts. Localloopback works
in asynchronous, synchronous, and
SDLC modes with NRZ, NRZI, or FM
coding of the data stream.
1/0 INTERFACE CAPABILITIES

The ESCC offers the choice of polling,
interrupt (vectored or nonvectored), and
block transfer modes to transfer data,
status, and control information to and
from the CPU. The block transfer mode
can be implemented under CPU or
DMA control.
POLLING
All interrupts are disabled. Three status
registers in the ESCC are auto-matically
updated whenever any function is
performed. For example, end-of-frame
in SDLC mode sets a bit in one of these
status registers. The idea behind
polling is for the CPU to periodically
read a status register until the register
contents indicate the need for data to
be transferred. Only one register needs
to be read; depending on its contents,
the CPU either writes data, reads data,
or continues. Two bits in the register
indicate the need for data transfer.

FIGURE 4. DATA ENCODING METHODS
DATA
NRZ
NRZI

----', ''--',----,I
\_--

\....

FM1

FMO
MANCHESTER

601

VLSI TECHNOLOGY, INC.
VL85C30

An alternative is a poll of the Interrupt
Pending register to determine the
source of an interrupt. The status for
both channels resides in one register.

down -INT. The CPU then responds
with -INTACK, and the interrupting
device places the vector on the data
bus.

INTERRUPTS
When an ESCC responds to an Interrupt
Acknowledge signal (-INTACK) from the
CPU, an interrupt vector may be placed
on the data bus. This vector is written in
Write Register 2 (WR2) and may be
read in Read Register 2A (RR2A) or
Read Register 2B (RR2B) (Figures 8).

In the ESCC, the IP bit signals ~ed
for interrupt servicing. When an IP bit
is 1 and the lEI input is high, the INT
output is pulled low, requesting an
interrupt. In the ESCC, if the IE bit is
not set by enabling interrupts, then the
IP for that source can never be set.
The IP bits are readable in RR3A.

To speed interrupt response time, the
ESCC can modify three bits in this
vector to indicate status. If the vector is
read in Channel A, status is never
included; if it is read in Channel B,
status is always included.

The IUS bits signal that an interrupt
request is being serviced. 'If an IUS is
set, all interrupt sources of lower
priority in the ESCC and external to the
ESCC are prevented from requesting
interrupts. The internal interrupt
sources are inhibited by the state of the
internal daisy chain, while lower priority
devices are inhibited by the lEO output
of the ESCC being pulled LOW and
propagated to subsequent peripherals.
An IUS bit is set during an interrupt acknowledge cycle if there are no higher
priority devices requesting interrupts.

Each of the six sources of interrupts in
the ESCC (Transmit, Receive, and
External/Status interrupts in both
channels) has three bits associated with
the interrupt source: Interrupt Pending
(IP), Interrupt Under Service (IUS), and
Interrupt Enable (IE). Operation of the
IE bit is straightforward. If the IE bit is
set for a given interrupt source, that
source can request interrupts. The
exception is when the MIE (Master
Interrupt Enable) bit in WR9 is reset and
no interrupts may be requested. The IE
bits are write only.
The other two bits are related to the
interrupt priority chain (Figure 5). As a
microprocessor peripheral, the ESCC
may request an interrupt only when no
higher priority device is requesting one;
e.g., when lEI is high. If the device in
question requests an interrupt, it pulls

receiver can interrupt the CPU in one of
three ways:
• On first receive character or special
receive condition
• On all receive characters or special
receive condition
•

On special receive condition only.

Interrupt on first character or special
condition and interrupt on special
condition only are typically used with
the Block Transfer mode. A special
receive condition is one of the following:
receiver overrun, framing error in
Asynchronous mode, end-of-frame in
SOLC mode, and optionally, a parity
error. The special receive condition
interrupt is different from an ordinary
receive character interrupt only in that
the status is placed in the vector during
the Interrupt Acknowledge cycle. In
interrupt on first receive character, an
interrupt can occur from special receive
conditions any time after the first receive
character interrupt.
The main function of the external/
status interrupt is to monitor the signal
transitions of the -CTS,-CCO, and
-SYNC pins; however, an external/
status interrupt is also caused by a
transmit underrun condition, or a zero
count in the baud rate generator, or by
the detection of a break (asynchronous
mode), abort (SOLC mode) or EOP
(SOLC loop mode) sequence in the data
stream.

FIGURE 5. INTERRUPT SCHEDULE

PERIPHERAL
+5V lEI 00-07 -INT -INTACK lEO

PERIPHERAL
lEI 00-07 -INT -INTACK lEO

PERIPHERAL
lEI 00-07 -INT -INTACK
+5V

-INTACK~----------~------------------~~----------------~

602

"VLSI TECHNOLOGY, INC.
The interrupt caused by the abort or
EOP has a special feature allowing the
ESCC to interrupt when the abort or
EOP sequence is detected or terminated. This feature facilitates the proper
termination of the current message,
correct initialization of the next message, and the accurate timing of the
Abort condition in external logic in SDLC
mode. In SDLC Loop mode, this feature
allows secondary stations to recognize
the need of the primary station to regain

VL85C30

control of the loop during a poll sequence.
CPUlDMA BLOCK TRANSFER
The ESCC provides a Block Transfer
mode to accommodate CPU block
transfer functions and DMA controllers.
The Block Transfer mode uses the Wait!
Request output in conjunction with the
WaiVRequest bits in WR1. The Waitl
Request output can be defined under
software control as a Wait line in the

CPU Block Transfer mode or as a
Request line in the DMA Block Transfer
mode.
To a DMA controller, the ESCC Request
output indicates that the ESCC is ready
to transfer data to or from memory. To
the CPU, the Wait line indicates that the
ESCC is not ready to transfer data,
thereby requesting that the CPU extend
the 110 cycle. The DTRlRequest line
allows full-duplex operation under DMA
control.

PROGRAMMING
The ESCC contains 13 write registers in
each channel that are programmed by
the system separately to configure the
functional personality of the channels.
In the ESCC, register addressing is
direct for the data registers only, which
are selected by a high on the D/-C pin.
In all other cases (with the exception of
WRO and RRO), programming the write
registers requires two write operations
and reading the read registers requires
both a write and a read operation. The
first write is to WRO and contains three
bits that point to the selected register.
The second write is the actual control
word for the selected register, and if the
second operation is read, the selected
read register is accessed. All of the
registers in the ESCC, including the data
registers, may be accessed in this
fashion. The pointer bits are automatically cleared after the read or write
operation so that WRO ( or RRO) is
addressed again.

The system program first issues a series
of commands to initialize the basic mode
of operation. This is followed by other
commands to qualify conditions within
the selected mode. For example, the
asynchronous mode, character length,
clock rate, number of stop bits, and even
or odd parity might be set first. Then the
interrupt mode would be set, and, finally,
receiver or trans-mitter enable.
READ REGISTERS
The ESCC contains ten read registers
(eleven counting receive buffer RR8) in
each channel. Four of these may be
read to obtain status information (RRO,
RR1, RR10, and RR15). Two registers
(RR12 and RR13) may be read to learn
the baud rate generator time constant.
The RR2 contains either the unmodified
interrupt vector (Channel A) or the
vector modified by status information
(Channel B). Both RR7 and RR6 read
the DMA FIFO. The RR3 contains the
Interrupt Pending (IP) bits (Channel A).

Figures 6 through 13 and Figure 31
show the formats for each read register.
The status bits of RRO and RR1 are
carefully grouped to simplify status
monitoring; e.g., when the interrupt
vector indicates a special receive
condition interrupt, all the appropriate
error bits can be read from a single
register (RR1).
WRITE REGISTERS
The ESCC contains 13 write registers
(14 counting WR8, the transmit buffer) in
each channel. These write registers are
programmed separately to configure the
functional personality of the channels.
In addition, there are two registers (WR2
and WR9) shared by the two channels
that may be accessed through either of
them; WR2 contains the interrupt vector
for both channels, while WR9 contains
the interrupt control bits. Figures 14
through 28 and Figure 31 show the
format of each write register.

TIMING
The ESCC generates internal control
signals from -WR and -RD that are
related to PCLK. Since PCLK has no
phase relationship with -WR and -AD,
the circuitry generating these internal
control signals must provide time for
metastable conditions to disappear.
This gives rise to a recovery time related
to PCLK. The recovery time applies
only between bus transactions involving
the ESCC. The recovery time required
for proper operation is specified from the
rising edge of -WR or -RD in the first
transaction involving the SCC, to the
falling edge of WR or RD in the second
transaction involving the ESCC. This

time must be at least four PCLK cycles
plus 200 ns.
READ CYCLE TIMING
Figure 32 illustrates Read cycle timing.
Addresses on A/-B and D/-C and the
status on -INTACK must remain stable
through the cycle. If -CE falls after -RD
falls or if it rises before -AD rises, the
effective -RD is shortened.
WRITE CYCLE TIMING
Figure 33 illustrates Write cycle timing.
Addresses on A/-B and D/-C and the
status on -INTACK must remain stable
throughout the cycle. If -CE falls after
-WR falls, or if it rises before -WR rises,
the effective -WR is shortened.

603

INTERRUPT ACKNOWLEDGE CYCLE
TIMING
Figure 34 illustrates Interrupt Acknowledge cycle timing. Between the time
-INTACK goes low and the falling edge
of -RD, the internal and externallEI/IEO
daisy chains settle. If there is an
interrupt pending in the ESCC and lEI is
high when -RD falls, the Acknowledge
cycle is intended for the ESCC. In this
case, the ESCC may be programmed to
respond to -RD low by placing its
interrupt vector on DO-D7 and it then
internally sets the appropriate InterruptUnder-Service latch.

VLSI TECHNOLOGY, INC.
VL85C30

FIFO DETAIL
For a better understanding of details of
the FIFO operation, refer to the block
diagram in Figure 39.
ENABLE/DISABLE

This FIFO is implemented so that it is
only enabled when Channel A register
WR15 bit 2 is set and the ESCC is in the
SOLC/HOLC mode, otherwise the status
register contents bypass the FIFO and
go directly to the bus interface (the FIFO
pointer logic is reset either when
disabled or via a channel or power-on
reset). When the FIFO mode is disabled, the ESqC is completely downward-compatible with the HMOS
VL8530. The FIFO mode is disabled on
power-up (WR15 bit 2 is set to 0 on
reset). The effects of backward comRR4 is an image of RRO, RR5 is an
image of RR1, RR6 is an image of RR2,
and RR7 is an image of RR3. For
details of the added registers, refer to
Figure 3. The status of the FIFO Enable
signal can be obtained by reading
Channel A RR15 bit 2. If the FIFO is
enabled, the bit will be set to 1; otherwise, it will be reset. Channel B WR15
and RR15 behave exactly as in the
VL8530 standard product.
READ OPERATION

When WR15 bit 2 is set and the FIFO is
not empty, the next read to any of status
register RR1 or the additional registers
RR7 and RR6 will actually be from the
FIFO. Reading status register RR1

causes one location of the FIFO to be
emptied, so status should be read after
reading the byte count, otherwise the
count will be incorrect. Before the
FIFO underflows, it is disabled. In this
case, the multiplexer is switched to
allow status to read directly from the
status register, and reads from RR7
and RR6 will contain bits that are
undefined. Bit 6 of RR7 (FIFO Data
Available) can be used to determine if
status data is coming from the FIFO or
directly from the status register, since it
is set to one whenever the FIFO is not
empty.
Since not all status bits must be stored
in the FIFO, the All Sent, Parity, and
EOF bits will bypass the FIFO. The
status bits sent through the FIFO will be
Residue Bits (3), Overrun, and CRC
Error.
The sequence for proper operation of
the byte count and FIFO logic is to read
the registers in the following order:
RR7, RR6, and RR1 (reading RR6 is
optional). Additional logic prevents the
FIFO from being emptied by multiple
reads from RR1. The read from RR7
latches the FIFO empty/full status bit
(bit 6) and steers the status multiplexer
to read from the ESCC megacell
instead of the status FIFO (since the
status FIFO is empty). The read from
RR1 allows an entry to be read from the
FIFO (if the FIFO was empty, logic is
added to prevent a FIFO underflow
condition).

604

WRITE OPERAnON

When the end of an SOLC frame (EOF)
has been received and the FIFO is
enabled, the contents of the status and
byte-count registers are loaded into the
FIFO. The EOF signal is used to
increment the FIFO. If the FIFO
overflows, the MSB of RR7 (FIFO
Overflow) is set to indicate the overflow.
This bit and the FIFO control logic is
reset by disabling and re-enabling the
FIFO control bit (WR15 bit 2). For
details of FIFO control timing during an
SOLC frame, refer to Figure 40.

BYTE COUNTER DETAIL
The 14-bit byte counter allows for
packets up to 16K bytes to be received.
For a better understanding of its
operation, refer to Figures 39 and 40.
ENABLE

The byte counter is enabled in the
SOLCIHOLC mode.
RESET

The byte counter is reset whenever an
SOLC flag character is received. The
reset is timed so that the contents of the
byte counter are successfully written
into the FIFO.
INCREMENT

The byte counter is incremented by
writes to the data FIFO. The counter
represents the number of bytes
received by the ESCC, rather than the
number of bytes transferred from the
ESCC. (These counts may differ by up
to the number of bytes in the receive
data FIFO contained in the ESCC.)

VLSI TECHNOLOGY, INC.
VL85C30

FIGURE 6. READ REGISTER 0

ID71D6ID~51D4~IDlS3ID~2IDlll~
L

FIGURE 10. READ REGISTER 10

RXCHARACTERAVAILABLE
ZERO COUNT
TX BUFFER EMPTY

DCD

SYNCIHUNT
CTS
L -_ _ _ _ _ _ TX UNDERRUNlEOM
L -_ _ _ _ _ _ _

TWO CLOCKS MISSING

BREAK/ABORT

ONE CLOCK MISSING

FIGURE 7. READ REGISTER 1

ID71D6ID~51D4~ID3lSlD2~1111~
L

FIGURE 11. READ REGISTER 12

ID71D61D5~ID4~I@ ~Tl~ERBm~

ALL SENT
RESIDUE CODE 2
RESIDUE CODE 1
RESIDUE CODE 0
PARITY ERROR

TIME CONSTANT

TC4

RX OVERRUN ERROR
L -_ _ _ _ _ _ CRe/FRAMING ERROR

TC5

L -_ _ _ _ _ _

END OF FRAME (SDLC)

Tes

TC7

FIGURE 8. READ REGISTER 2
FIGURE 12. READ REGISTER 13

ID71D6ID~51D4~I@ ~J UPPERBm~
TIME CONSTANT

TC12
TC13
TC14
• MODIFIED IN B CHANNEL
TCIS

FIGURE 9. READ REGISTER 3

ID71D61D5~ID4~ID3lSlD2~IDIIDO~
L

FIGURE 13. READ REGISTER 15

'D71D6ID~5ID~4rm:ROCOONT"
L::::: DCD

CHANNEL B EXT/STATIP'
CHANNEL B TX IP'
CHANNEL B RX IP •
CHANNEL A EXT/STAT IP •

CHANNEL A TX IP •

SYNClHUNT IE

CHANNEL A RX IP •

CTSIE
L -_ _ _ _ _ _ TX UNDERRUNlEOM IE

• ALWAYS 0 IN B CHANNEL

BREAK/ABORT IE

605

VLSI TECHNOLOGY, INC.
VL85C30

FIGURE 14. WRITE REGISTER 0

FIGURE 17. WRITE REGISTER 3

REGISTERO
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
REGISTERS
REGISTER 6
REGISTER 7
REGISTERS
REGISTER 9
REGISTER 10
REGISTER 11
REGISTER 12
REGISTER 13
REGISTER 14
REGISTER 15

RXENABLE
SYNC CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SOLC)
RX CRC ENABLE
ENTER HUNT MODE
AUTO ENABLES

RX 5 BITS/CHARACTER
RX 7 BITSICHARACTER
RX 6 BITS/CHARACTER
RX S BITS/CHARACTER

NULL CODE
POINT HIGH
RESET EXT/STAT INTERRUPTS
SEND ABORT (SDLC)
ENABLE INT ON NEXT RX CHARACTER
RESETTXINT PENDING
ERROR RESET
RESET HIGHEST IUS

FIGURE 18. WRITE REGISTER 4

NULL CODE
RESET RX CRC CHECKER
RESET TX CRC GENERATOR
RESET TX UNDERRUNlEOM LATCH
• WITH POINT HIGH COMMAND

S BIT SYNC CHARACATER
16 BIT SYNC CHARACTER
SOLC MODE (01111110 FLAG)
EXTERNAL SYNC MODE

FIGURE 15. WRITE REGISTER 1

1071 061

D~51
D~41 D~21111~
031

L..

EXT INT ENABLE
TX INT ENABLE

PARITY IS SPECIAL CONDITION
0 RX INT DISABLE
1 RX INT ON FIRST CHARACTER OR SPCL. CONDITION
1 0 INT ON ALL Rx CHARACTERS OR SPCL. CONDITION
RX INT ON SPECIAL CONDITION ONLY
WAITIDMA REQUEST ON RECEIVE/-TRANS.
a...._ _ _ -WAIT/DMA REQUEST
FUNCTION
1..-_ _ _ _ WAITIDMA REQUEST ENABLE

o
o

FIGURE 19. WRITE REGISTER 5

ID71D61D51D4~ID~3111~

:RCENASLE

-SDLCICRC-16
TXENABLE

FIGURE 16. WRITE REGISTER 2

SEND BREAK

ID71061D5~r@ ~T~RU~

TX 5 BITS (OR LESS)/CHARACTER
TX 7 BITSICHARACTER
TX 6 BITSICHARACTER
TX S BITS/CHARACTER
L..._ _ _ _ _ _ _ _ DTR

~"lVECTOR
V5
V6
V7

606

VLSI TECHNOLOGY, INC.
VL85C30

FIGURE 20. WRITE REGISTER 6

SYNC7
SYNC1
SYNC7
SYNC3
ADR7
ADR7

SYNC6
SYNCD
SYNC6
SYNC2
ADR6
ADR6

SYNCS
SYNCS
SYNCS
SYNC1
ADRS
ADRS

SYNC4
SYNC4
SYNC4
SYNCD
ADR4
ADR4

SYNC3
SYNC3
SYNC3
1
ADR3

SYNC2
SYNC2
SYNC2
1
ADR2

SYNC1
SYNC1
SYNC1
1
ADR1

SYNCO
SYNCD
SYNCD
1
ADRD

SYNC1

SYNCD
X
SYNCS
SYNC4
D

MONOSYNC, 8 BITS
MONOSYNC, 6 BITS
BISYNC, 16 BITS
BISYNC, 12 BITS
SDLC
SDLC
(ADDRESS RANGE)

FIGURE 21. WRITE REGISTER 7

SYNC7
SYNCS
SYNC1S
SYNC11

SYNC6
SYNC4
SYNC14
SYNC1D

SYNCS
SYNC3
SYNC13
SYNC9

SYNC4
SYNC2
SYNC12
SYNC8

SYNC3
SYNC1
SYNC11
SYNC7

SYNC2
SYNCD
SYNC1D
SYNC6

607

X
SYNC9
SYNCS

MONOSYNC, 8 BITS
MONOSYNC, 6 BITS
BISYNC, 16 BITS
BISYNC, 12 BITS
SDLC

VLSI TECHNOLOGY, INC.
VL85C30

FIGURE 22. WRITE REGISTER 9

ID7100I00rrf'~ :C
MIE

FIGURE 25. WRITE REGISTER 12

'~'OO'OOT@ ~ lOWERB=~
~

STATUS HIGI-{I-STATUS LOW

TCA lTIMECONSTANT
TCS
TC6

~O ~1

NO RESET
CHANNEL RESET B
CHANNEL RESET A
FORCE HAROWARE RESET

~~
~~

TC7

FIGURE 26. WRITE REGISTER 13

107106los1041031021011ool

L:~:T

FIGURE 23. WRITE REGISTER 10

ID7100IDsrrrr~ ::::::VNC

LTC10

ABORT/-FLAG ON UNOERRUN

TC14

GO ACTIVE ON POLL

..g...g
~~

r-J. ~

.J...l

TC1S

NRZ
NRZI
FM1 (TRANSITION .. 1)
FMC (TRANSITION .. 0)

FIGURE 27. WRITE REGISTER 14
07 06
CRC PRESET V-{)

OSI 04~1
D3lllil
0~211'1~ BR GENERATOR ENABlE

1 1 1

L-

FIGURE 24. WRITE REGISTER 11
07 06

04 03

0~21~Dll~ ~TRXC

OSI 1 1

AUTO ECHO
LOCAL LOOPBACK
OUT _ XTAL OUTPUT
NULL COMMANO
ENTER SEARCH MOOE
RESET MISSING CLOCK
OISABLE OPLL
SET SOURCE = BR GENERATOR
SET SOURCE = -RTXC
SETFM MOOE
SET NAZI MOOE

-TRXCO'-I
0
1
1 0
1 1

TRANSMIT CLOCK .. -RTXC PIN
TRANSMIT CLOCK .. - TRXC PIN
_
TRANSMIT CLOCK = BR GEN. OUTPUT
TRANSMIT CLOCK .. OPLL OUTPUT

FIGURE 28. WRITE REGISTER 15

0710610SI O4wgr@:EROOOUNTIE

RECE IVE CLOCK _ -RTXC PIN
RECEIVE CLOCK =-TRXC PIN
RECEIVE CLOCK = BR GEN. OUTPUT
RECEIVE CLOCK = OPLL OUTPUT
L..-_ _ _ _ _ _ _

BR GENERATOR SOURCE
-DTRlREQUEST FUNCTION

1 - TRXC OUT _ TRANSMIT CLOCK
1 0 -TRXC OUT .. BR GENERATOR OUTPUT
1 1 - TRXC OUT _ OPLL OUTPUT

o
o

UPPER BYTE OF

TC13

MARKI-FLAG 10LE

":'

TC11

-RTXCXTAU-NO XTAL

COCOIE

1..-______

SYNClHUNT IE
CTSIE
TX UNOERRUN/EOM IE
BREAKIABORT IE

608

VLSI TECHNOLOGY, INC.
VL85C30

FIGURE 29. ESCC STATUS REGISTER
SCC STATUS REG
(EXISTING)

RR1

i4--RESET ON FLAG DETECT

Ir-------------jl..~~-INCREMENT ON BYTE DET
14 BIT BYTE COUNTER

---;::==~--tl

+5 BITS

14 BITS

RESIDUE BITS(3)

i4--ENABLE COUNT IN SDLC

END OF FRAME SIGNALSTATUS READ COMP

-or-

OVERRUN
CRC ERROR
.....- - - 10 X 19 BIT FIFO ARRAY

TAIL POINTER
4 BIT COUNTER
HEAD POINTER
4 BIT COUNTER

I+-

4 BIT COMPARATOR
OVER

SBITS
EOF -1

I EN
. ~ 6-BITS
.. f-8-BITS
6 B~UX //~'4------II .----+--------i--------.....

EQUAL

. .~ . ~.~.~.~~. . . . . . . . t.~R~.I~~. . . . . . . . . ~? ...l~~~. . ~~i_~~~ . . . . . . . . . . . ~~~. . . . . . . . . . . . . . . . . . . . . . . . . . ~~~~~.~~~. .
INTERFACE TO SCC

lYTE COUNTER CONTAINS 14-BITS FOR
A 16 KBYTE MAXIMUM COUNT
FIFO DATA AVAILABLE STATUS BIT
STATUS BIT SET TO 1
WHEN READING FROM FIFO

FIFO OVERFLOW STATUS BIT
MSB OF RR(7) IS SETON STATUS FIFO
OVERFLOW
IN SDLC MODE THE FOLLOWING DEFINITIONS APPLY
ALL SENT BYPASSES MUX AND EQUALS CONTENTS OF SCC STATUS REGISTER
• PARITY BITS BYPASSES MUX AND DOES THE SAME
• EOF IS SET TO 1 WHENEVER READING FROM THE FIFO

609

WR(1S) BIT 2
SET ENABLES
STATUS FIFO

VLSI TECHNOLOGY, INC.
VL85C30

FIGURE 30. SDLC BYTE COUNTING DETAIL

DON'T LOAD
COUNTER ON
1ST FLAG
RESET BYTE
COUNTER HERE

RESET
BYTE COUNTER

RESET
BYTE COUNTER
LOAD COUNTER
INTO FIFO AND
INCREMENT PTR

RESET
BYTE COUNTER
LOAD COUNTER
INTO FIFO AND
INCREMENT PTF

FIGURE 31. ESCC REGISTERS
7

4
READ FROM FIFO
MSB BYTE COUNT

RR7

FIFO DATA AVAILABLE STATUS
1 - STATUS READS WILL COME FROM FFO
0_ STATUS READS WILL COME FROM SCC
~---

FIFO OVERFLOW STATUS
1 - FIFO OVERFLOWED DURING OPERA1a>N
0- NORMAL

76543210
RR6

IB; I B; I B;I

B~ I B~I ~cl B~ I B~I

765432
WR15

• I • I

READ FROM FIFO
LSB BYTE COUNT

·1 ·1· 3. ·1
I FE

STATUS FIFO ENABLE CONTROL BIT
1 - STATUS AND BYTE COUNT WILL BE
HELD IN THE STATUS FIFO UNlL READ
0 .. STATUS WILL NOT BE HELD (SCC
EMULATION MODE) .
• - NO CHANGE FROM HMOS sec DFN

610

VLSI TECHNOLOGY, INC.
VL85C30

FIGURE 32. READ CYCLE TIMING

AI-B,O/-C

-INTACK

_______><________

><______

A_O_O_RE_S_S_v_AL_IO________

'\:_---

-CE

'\.

-RO

, ,_ _ _ _ _

--J/

00-07

DATA VALID

)>--------

FIGURE 33. WRITE CYCLE TIMING

----J><________

AI-B, O/-C _ _ _

-INTACK

'\:_---

-CE

'\.

-WR

00-07

><_____

A_O_O_RE_S_S_V_AL_IO________

,-,----/

----------~(______O_A_T_A_VA_L_IO______)>----------

FIGURE 34. INTERRUPT ACKNOWLEDGE CYCLE TIMING

-INTACK

-RO

00-07

~ ________________________- - ' /
--~

'-,--------~
----iX

( _____

611

VECTOR

)>--------

VLSI TECHNOLOGY, INC.
VL85C30

FIGURE 35. READ AND WRITE TIMING (SEE TABLE 1)

PClK

AI-B. D/-C

-INTACK

-CE

-AD

DO-D7

READ

-WR
DO-D7

WRITE
-WI-REO

WAIT
-WI-REO
REOUEST
-OTR/-REO
REOUEST

-INT

:URE36.RE~TABLE1)
-AD

t;d

---r-

r:::~~r-

, __.

FIGURE 37. CYCLE TIMING (SEE TABLE 1)

-ce

~~---------/

~4------

----------~

_ ~14------"1®-~-~~_

-RD OR -WR

~~--------I"------~~~.--------"
612

VLSI TECHNOLOGY, INC.
VL85C30

TABLE 1. READ AND WRITE TIMING CHARACTERISTICS:
No. Symbol

Parameter

TwPCI
TwPCh
TfPC
TrPC
TcPC
TsA(WR)
ThA(WR)
TsA(RD)
ThAlRo)
TsIA(PC)
TsIAi(WR)
ThIA(WR)
TslAilRo)
ThIA(RD)
ThIA(PC)
TsCE1(WR)
ThCE(WR)
TsCEh(WR)
TsCE1lRo)
ThCElRD)
TsCEhlRo)
TwRD1
TdRD(oRA)
TdRDr(DR)
TdRDf{DR)
TdRD DRz)
TdA(DR)

PCLK Low Width
PCLK Hiqh Width
PCLK Fall Time
PCLK Rise Time
PCLK Cycle Time
Address to -WR Setup Time
Address to -WR Hold Time
Address to -RD Setup Time
Address to -RD Hold Time
-INTACK to PCLK Setup Time
-INTACK to -WR Setup Time
-INTACK to -WR Hold Time
-INTACK to -RD Setup Time
-INTACK to -RD Hold Time
-INTACK to PCLK Hold Time
-CE Low to -WR Setup Time
-CE to -WR Hold Time
-CE HiClh to -WR Setup Time
-CE Low to -RD Setup Time
-CE to -RD Hold Time
-CE Hiah to -RD Setup Time
-RD Low Width
-RD to Read Data Active Delay
-RD to Read Data Not Valid Delay
-RD to Read Data Valid Delay
-AD to Read Data Float Delay
Address Required Valid to
Read Data Valid Delay

28
29
30
31
32
33
34

TwWR1
TsDW(WR)
ThDW(WR)
TdWR(W)
TdRD(W)
TdWRf(REO)
TdRDf(REO)
35 TdWRr(REO)

36 TdRDr(REO)

-RD to -DTR/-REO Not Valid Delay

37
38
39
40
41
42

43
44
45
46
47
48
49

TdPC INT)
TdIAi(RD)
TwRDA
TdRDA(oR)
TsIEI( RDA)
ThIEI( RDA
TdlEI( lEO)
TdPC lEO)
TdRDA(lNn
TdRDLWRO)
TdWRO(RD)
TwRES
Trc

10 MHz

8 MHz
Min

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

TA=O°CTO+70°C

50
50

125
70
0
70
0
20
145
0
145
0
40
0
0
60
0
0
60
150
0
0

Max
1000
1000
10
15
2000

Min
40
40

100
50
0
50
0
20
130
0
130
0
30
0
0
50
0
0
50
125
0
0

140
40
220
150
10
0

PCLK to -INT Valid Delay
-INTACK to -RD (AcknowledCle) Delay
-AD (AcknowledCle) Width
-RD(Ack.}to Read Data Valid Delay
lEI to -RD (AcknowledCle) Setup Time
lEI to -RD (Acknowledqe) Hold Time
lEI to lEO DelayTime
PCLK to lEO Delay
-AD to -INT Inactive Delay
-RD to -WR Delay for No Reset
-WR to -RD Delay for No Reset
-WR and -RD Coincident Low for Reset
Valid Access Recoverv Time

Max

Notes

1000
1000
10
10
2000

2
2

2
2
2
2

120
35
180

170
170
170
170
4TcPC

160
160
160
160
4TcPC

4TcPC

500

500
125
125

140

5
5

5
6

120
95
0

95
0
95
200
500

613

12MHz
Min

125
10
0

150
150

15
15
150
4TcPC

Max

90
175
500
15
15
100
4TcPC

VLSI TECHNOLOGY, INC.
VL85C30

Read and Write Timing Notes:
1. Units are in nanoseconds.
2. Parameter does not apply to Interrupt Acknowledge transactions.
3. Float delay is defined as the time required for a ± 0.5 V change at the output with a maximum dc load and minimum ac load.
4. Parameter applies only between transactions involving the ESCC.
5. Open-drain output, measured with open-drain test load.
S. Parameter is system-dependent. For any ESCC in the daisy chain, TdIAi(RD) must be greater than the sum of TdPC (lEO) for
the highest priority device in the daisy chain, TsIEI(RDA) for the ESCC, and TdIElf(IEO) for each device separating them in the
daisy chain.
FIGURE 38. INTERRUPT ACKNOWLEDGE TIMING (SEE TABLE 1)

PCLK

-INTACK ----------~

-RD

DATA

lEI

lEO

______________________________________1~4:~~~~:_~_5~_-__-_-_-J-;t.~----____________________

INT

614

VLSI TECHNOLOGY, INC.
VL85C30

FIGURE 39. GENERAL TIMING (SEE TABLE 2)

PCLK

-W/-REQ
REQUEST

-W~REQ ___________________~~r-

WAIT

_____________________________

-RTxC, -TRxC _________~~~--:_r
RECEIVE

RxD

~YNC

EXTERNAL _________

-TRxC, -RTxC
TRANSMIT

TxD

~~----~_:_l~--------~

,I~

1:~@-:L,-

r~l<================~
>Em 1<--------m

-TRxC
OUTPUT

-RTxC

+---®--+ll~g
~®6r;
{
~---------- :
~
~ ------------~"----

-TRxC-~\

{~~_----

-CTS,-DCD,-RI _ _ _ _ _ _ _ _

{~~

_ _ _ _ __

~~-------------~~~~

615

VLSI TECHNOLOGY, INC.
VL85C30

TABLE 2. GENERAL TIMING
No. Symbol

Parameter

8 MHz

1
2
3

TdPC(REO)
TdPC(W)
Ts RXC(PC)

TsRXD RXCr
ThRXD RXCr
TsRXD RXCf
ThRXD RXCf
TsSY(RXC)
ThSY(RXC)
TsTXC(PC)
TdTXCflTXD)
TdTXCr(TXD)
TdTXD TRX}
TwRTXh
TwRTXI
TcRTX
TcRTXX
TwTRXh
TwTRXI
TcTRX
TwEXT
TwSY

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

PCLK to -WI-REO Valid Delay
PCLK to Wait Inactive Delay
-RxC to PCLK Setup Time
60
(PCLK + 4 Case Only)
RxD to -RxC Setup Time (X1 Mode)
RxD to -RxC Hold Time JX1 Mode)
RxD to -RxC Setup Time (X1 Mode)
RxD to -RxC Hold Time (X1 Mode)
-SYNC to -RxC Setup Time
-SYNC to -RxC Hold Time
5TcPC
- TxC to PCLK Setup Time
0
-TxC to TxD Delay(X1 Modet
- TxC to TxD Delay (X1 Mode)
TxD to - TRxC Delay (Send Clk Echo)
-RTxC High Width
150
-RTxC Low Width
150
-RTxC Cycle Time
500
Crystal Oscillator Period
125
-TRxC Hiqh Width
150
150
- TRxC Low Width
500
- TRxC Cycle Time
-DCD or -CTS Pulse Width
200
-SYNC Pulse Width
200

12MHz

10 MHz

Max

Min

250
350
Tv.Pa

Min

Max

Min

Max

Notes

250
350
Tv.PCJ

2,5

0
150
0
150
-200

2
2
26
2,6
42
42
35
3
3,5

STcPC
0
150
150
200

200
200
200

1000

150
150
400
100
150
150
400
200
200

7
7
7
3
4,7
47
47

1000

TABLE 3. SYSTEM TIMING
No. Symbol

1
2
3
4
5
6
7
8
9
10

TdRXC REO)
TdRXC W)
TdRXC SY)
TdRXC INT)
TdTXC REO)
TdTXC W)
TdTXC DRO)
TdTXC INT}
TdSYlINT)
TdEXT INT)

Parameter

8 MHz

-RxC to -WI-REO Valid Dela~
-AxC to Wait Inactive Delay
-AxC to -SYNC Valid Delay
-AxC to -INT Valid Delay
-TxC to -WI-REO Valid Delay
- TxC to Wait Inactive Delay
-TxC to -DTR/-REO Valid Delay
-TxC to -INT Valid Delay
-SYNC to -INT Valid Delay
-OCD or -CTS to -I NT Valid Delay

Min

Max

8
8
4
10

12
14
7
16
8
11
7
10
6
6

5
5
4
6
2
2

12MHz

10 MHz
Min
8
8
4
10
5
5
4
6
2
2

Max

Min

Max

Notes

12
14
7
16
8
11
7
10
6
6

General and System Timing Notes:
1. Open-drain output, measured with open-drain test load.
2. RxC is RTxC or TRxC, whichever is supplying the transmit clock.
3. TxC is TRxC or RTxC, whichever is supplying the transmit clock.
4. Both TrxC and SYNC have 30 pF capacitors connected to ground.
5. Applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between RxC and
PCLK or TxC and PCLK is required.
6. Applies only to FM encoding/decoding.
7. Applies only for transmitter and receiver; DPLL and baud rate generator timing are identical to chip PCLK requirements.
8. Units are in nanoseconds (ns).

616

2
12
2
12
3
13
3
13
1
1

VLSI TECHNOLOGY, INC.
VL85C30

FIGURE 40. SYSTEM ,TIMING (SEE TABLE 3)
-RTxC, - TRxC
RECEIVE

-WI-REO
REaJEST

-W~REO
WAIT _______________________________~-:::~~::::~
144L---~QD~-----4~1
-SYNC

OUTPUT

-INT

-RTxC,-TRxC
TRANSMIT

-WI-REa
REaJEST

-W/~EO
_______________________________t:::::::~~:::::
WAIT
-{)TRI-REO
REaJEST

-INT

-CTS, -OeD, -RI

...

K
-~

-SYNC
INPUT

....-

-tNT

-@)

617

VLSI TECHNOLOGY, INC.
VL85C30

ABSOLUTE MAXIMUM RATINGS
Voltages on all pins
with respect to GND

-0.3V to 7.0V

Operating Ambient
Temperature

O°C to +70°C

Storage Temperature -65°C to +150°C

Stresses above those listed under
"Absolute Maximum Ratings" may
cause permanent damage to the
device. These are stress ratings only.
Functional operation of this device at
these or any other conditions above
5V

STANDARD TEST
CONDITIONS
the dc characteristics and capacitance
section below apply for the following
standard test conditions, unless otherwise noted. All voltages are referenced
to GND. Positive current flows into the
referenced pin.
Standard conditions are as follows:

those listed on the operational sections
of this specification is not implied and
exposure to absolute maximum ratings
conditions for ~xtended periods may
affect device reliability.

2.1 kn

2.2kn
100 pF

• +4.75 V:s; Vee:s; +5.25 V·
• GND aOV
• TA as shown in Ordering Information

FROM OUTPUTUNDER TEST

50 pF

DC CHARACTERISTICS: vcc = 5 V ± 5%, TA = O°C to 70°C
Symbol

Parameter

Min

Max

Unit

Conditions

VIH

Input High Voltage

2.0

VCC+ 0.3

VIL

Input Low Voltage

-0.3

0.8

VOH

Ouput High Voltage

2.4

IOH

= -1.0 mA

VOH

Ouput High Voltage

VCC -0.8

IOH

= -250 J.1A

VOL

Output Low Voltage

IOH =+2.0 mA

ilL

Input Leakage

±10.0

J.l.A

0.4 V:s; VIN :s; +2.4 V

IOL

Output Leakage

±10.0

J.l.A

0.4 V

ICC

VCC Supply Current

0.4

3.0

mAlMHz

VIN ~ +2.4 V

See Note

Note: Add 0.5 mA quiescent current to determine total maximum VCC supply current. (Example: at 10 MHz clock frequency, the
total maximum VCC supply current equals 30 mA plus 0.5 mA or 30.5 mA.)

CAPACITANCE:

TA=O°Ct070°C,f=1 MHz

Symbol

Parameter

CIN
COU

ClIO

Max

Unit

Conditions

Input Capacitance

Unused Inputs Grounded

Output Capacitance

Min

Bidirectional Capacitance

618

Unused Inputs Grounded

VLSI TECHNOLOGY, INC.
VL86C010
32-BIT RISC MICROPROCESSOR

FEATURES

DESCRIPTION

• 32-bit internal architecture

The VL86C010 Acorn RISC Machine
(ARM) is a full 32-bit general-purpose
microprocessor designed using
reduced instruction set computer
(RISC) methodologies. The processor
is targeted for the microcomputer,
graphics, industrial and controller
markets for use in stand-alone or
embedded systems. Applications in
which the processor is useful include
laser printers, graphics engines, N.C.
machines and any other systems
requiring fast real-time response to
external interrupt sources and high
processing throughput.

• 32-bit external data bus
• 64M-byte linear address space
• Bus timing optimized for standard
DRAM usage with page mode
operation
• 40M-byte/second bus bandwidth
• Simple/powerful instruction set
providing an excellent high level
language compiler target
• Hardware support for virtual memory
systems
• Low interrupt latency for real-time
application requirements
• Full CMOS implementation results in
low power consumption
• Single 5 V ± 5% operation
• 84-pin JEDEC Type-B leadless chip
carrier or plastic leaded chip carrier
(PLCC)

stacks and queues to be easily
implemented in software. All instructions are 32 bits long (aligned on word
boundaries), with register-to-register
operations executing in one cycle.
. The two data types supported are 8-bit
bytes and 32-bit words.

The VL86C010 features a 32-bit data
bus, 27 registers of 32 bits each, a
load-store architecture, a partially
overlapping register set, 2.6 j!s worstcase interrupt latency, conditional
instruction execution, a 26-bit linear
address space and an average
instruction execution rate of from fourto-five million instructions per second
(MIPS). Additionally, the processor
supports two addressing modes:
program counter (PC) and base
register relative modes. The ability to
do pre- and post-indexing allows

Using a load-store architecture
simplifies the execution unit of the
processor, since only a few instructions deal directly with memory and the
rest operate register-to-register. Load
and store multiple register instructions
provide enhanced performance,
making context switches faster and
exploiting sequential memory access
modes.
The processsor supports two types of
interrupts that differ in priority and
register usage. The lowest latency is
provided by the fast interrupt request
(FIRO) which is used primarily for I/O
to peripheral devices. The other
interrupt type (IRO) is used for
interrupt routines that do not demand
low-latency service or where the
overhead of a full context switch is
small compared with the interrupt
process execution time.

PIN DIAGRAM

ORDER INFORMATION

JEDEC TYPE-B CERAMIC LEADLESS CHIP CARRIER

Part
Number

-TRAN _FIRO ABRT -Opc 01 -BNI -CPI 030 028 CPA
RES _IRO-MRE0-R/W 02 OBE 031 029 027 GNO

vee

13
14
15
16

17
18
19

8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74
73
72
71
70
69
68
67

66
65
64
63
62
61
60
59
58
57
56

A21

21
22
23
24
25

26
27
28
29

VL86C010
TOP VIEW

VL86CO 10-1 OOC

Clock
Frequency
10MHz

JEDEC Type-B
Ceramic Carrier

VL86C01 0-1 OLC
VL86C010-120C
VL86C010-12LC

Package
Plastic Leaded
Chip Carrier (PLCC)

12MHz

Plastic Leaded
Chip Carrier (PLCC)
JEDEC Type-B
Ceramic Carrier

Note: Operating temperature range is O°C to +70°C

PLEASE CONSULT RISC FAMILY DATA
MANUAL FOR DETAILED INFORMATION

~~~~~~~~~~~M~~Q~G~~~~

619

VLSI TECHNOLOGY, INC.
VL86C110
RISC MEMORY CONTROLLER (MEMC)

FEATURES

DESCRIPTION

• Drives up to 32 standard dynamic
RAMs giving 4M bytes of real
memory with 1M bit devices

The memory controller (MEMC) acts as
the interface between the ARM (Acorn
RISC Machine) processor and other
functions in the system. The four circuits
in the RISC family: MEMC, ARM,
VI DC-video controller, and 10C-1/0
controller, can be used to implement a
small computer system. MEMC uses a
single clock input to derive timing
information for the other components.

• logical-to-physical address
translation (32M byte logical address
space) supporting three protection
levels:
- Supervisor Mode
- Operating System Mode
- User Mode

In addition to providing interface signals
to the other controllers, MEMC generates all the control signals for several
access times of read-only memory
(ROM) plus high-resolution timing and
refresh control for dynamic RAM
(DRAM). The controller outputs can
drive up to 32 memory devices directly
in a wide variety of configurations using
various architectures of standard
DRAMs. A logical-to-physical address
translator maps the 4M byte physical
memory into the 32M byte logical
address space with three levels of
protection.

• Uses fast page mode DRAM
accesses to maximize bandwidth
from commodity memories
• Internal DMA address generators for
video, cursor and sound data buffers
• Various ROM speeds supported
(aCcess times of 450 ns, 325 ns,
200 ns)
• Provides all critical system timing
Including processor clocks, -RAS,
-CAS, and DMA data transfer strobes
• Arbitrates memory between the
processor and DMA systems

Address translation is performed by a
simple 128 entry content-addressable

PIN DIAGRAM

Part
Number

A17 A19 A21 A23 A25 01 RCLK-fW.I
VOD A18 A20 A22. A24 CLK 02
VSS

A16
A15
A14
A13
A12
A11
A10

59
58
57

56
55
VL86C110
TOP VIEW

SE~

53
52

ABRT
SPMO
-VI OW
-VOAK

AS
AS
A4

A3
A2

46
45

-SOAK
-VORO
-SORO
-HSYC
FLBK

RES

-RMes
-IORO
-IOGT
-SIRO
DBE
-MREO

~~~oo~~~~~~~~~~~~~

MEMC supports direct memory access
(DMA) read operations with three
programmable address generators.
Video refresh is performed using a
circular buffer to enhance scrolling
capability plus a separate linear buffer
for a cursor sprite. Sound data uses a
double buffering system.

Bus Clock
Frequency

1-BlWi

VLS6C110-0S0C

A9
AS

The simple structure allows memory
address translation to be performed
without increasing required memory
access time or decreasing the system
clock. MEMC allows virtual memory and
multi-tasking operations to be implemented without the usual performance
degradation associated with each
function. Fast page mode DRAM
accesses are used to maximize
memory bandwidth from inexpensive
commodity memory devices.

ORDER INFORMATION

JEDECTYPE-B CERAMIC LEADLESS
CHip CARRIER

memory (CAM). MEMC provides a
descriptor entry for every page of
physical memory which eliminates
descriptor thrashing (address translation misses) from degrading system
performance.

LclsJ

VSS RA1 RA31 RA51 RA71 RA91
voo
RAO RA2 RA4 RA6 RA8
~ASq
I
-RAS -CAS1 -CAS3

620

VLS6C110-0SLC

8 MHz

Package
Plastic Leaded
Chip Carrier (PLCC)
JEDEC Type-B
Ceramic Carrier

Note: Operating temperature range is O°C to + 70°C.

PLEASE CONSULT RiSe FAMILY DATA
MANUAL FOR DETAILED INFORMATION

VLSI TECHNOLOGY, INC.
VL86C310
RISC VIDEO CONTROLLER (VIDC)

FEATURES

DESCRIPTION

• Pixel rate selectable as 8, 12, 16, or
24 MHz

The Video Controller (VIDC) accepts
video data from DRAM under DMA
control, serializes and passes it through
a color look-up palette, and converts it
to analog signals for driving the CRT
guns. The chip also controls all the
display timing parameters plus the
position and pattern of the cursor sprite.
In addition, the VIDC includes an
exponential DAC and stereo image
table for the generation of high quality
sound fro~ data in the DRAM.

• Serializes data to 1-, 2-,4-, or 8- bits
per pixel
• 16 x 13 bit words - 4096 color lookup
palette
• Three 4-bit DACs (one for each CRT
gun)
• Fully programmable screen parameters
• Screen border in any of the 4096
possible colors
• Flexible cursor sprite
• Support for interlaced display format
• External synchronization capability
• Very high resolution monochrome
mode support
• High quality stereo sound generation

The VIDC requests data from the RAM
when required, and buffers it in one of
three first-in, first-out memories
(FIFOs). Note that the addressing of the
data in RAM is controlled elsewhere in
the system (usually in the VL86C11 0
Memory Controller, MEMC). Data is
requested in blocks of four 32-bit words,
allowing efficient use of page-mode
DRAM without locking up the system
data bus for long periods.
The VIDC is a highly programmable device, offering a very wide choice of display formats. The pixel rate can be se-

PIN DIAGRAM

Part
Number

-VOAK 030
028
026
024
022
020
018
029
027
D2S
D23
021
019
017
-SOAK 031

VL86C310-080C

VSSS

016

VOOS

DIS

REFS

014

LCH

013

RCH

012

-lCH

011

-RCH

010

-VR
VSSO

Extensive use is made of pipelining
throughout the device.
The cursor sprite is 32 pixels wide, and
any number of rasters high. Three
simultaneous colors (from the 4096
possible) are supported, and any pixel
can be defined as transparent, making
possible cursors of many shapes. The
cursor can be positioned anywhere on
the screen.
The sound system implemented on the
device can support up to eight channels, each with a separate stereo
position.

ORDER INFORMATION

JEDEC TVPE-B CERAMIC LEADLESS
CHIP CARRIER

lected in a range between 8 and 24
MHz and the data can be serialized to
either 8-, 4-, 2-, or 1-bit per pixel. The
horizontal timing parameters can be
controlled to units of 2 pixels, and the
vertical timing parameters can be
controlled in units of a raster. The color
lookup palette which drives the three
on-chip DACs is 13 bits wide, offering a
choice from 4096 colors or an external
video source.

VL86C310-08LC

Clock
Frequency

8 MHz

Package
Plastic Leaded
Chip Carrier (PLCC)
JEDEC Type-B
Ceramic Carrier

Note: Operating temperature is O°C to +70°C.

VL86C310

TOP VIEW

CKIN

SINK
-HI

os
os

FLBK

-VORO

-SORO

-HSYC

-ViCS
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

42 43

-V lOW I-VE03I-VEOII NSEL 1-sE021-SEDO I ROUT I BOUT I REFV
-SUP -VE02 -VEOO -sE03 -sEOl VOOO GOUT VSSV

621

PLEASE CONSULT RiSe FAMILY DATA
MANUAL FOR DETAILED INFORMATION

VLSI TECHNOLOGY, INC.
Vl86C410
RISC 1/0 CONTROLLER (IOC)

FEATURES

DESCRIPTION

• Power on reset control

The VL86C410 Input/Output Controller
(IOC) is designed to interface to the
VL86C010IVL86C110NL86C310 chip
set to provide a unified view of interrupts and peripherals within an Acorn
RISC Machine (ARM) based computer.
It controls an 8-to-32 bit 1/0 data bus to
which on-board peripherals and any 110
expansions are connected. It provides a
set of internal functions, which are
accessed without wait states, and
programmable speed access to external
peripherals.

• Four independent 16-bit programmable counters
-Two timers
-Two baud rate generators
• Bidirectional serial keyboard interface
• Six programmable bidirectional
control pins
• Interrupt mask, request and status
registers for -IRQ and -FIRQ
• 14 level triggered interrupt inputs
• Two edge triggered interrupt inputs
• Four programmable peripheral cycles
-Slow
-Medium
- Fast
- 2 MHz synchronous
• Seven external peripheral selects
• ARMIIO bus interface control

The VL86C410 provides system level
1/0 with six programmable control pins
and a full-duplex, bidirectional serial
keyboard interface. To support system
timing requirements, the VL86C410
contains four independent programmable counters. Two of these counters
are used as baud rate generators. One
is dedicated to the keyboard and the
other controls the BAUD output pin to

generate a free-running clock. The
other two counters can be used to
generate system timing events.
The 10C serves as the interface
between the very high-speed RISC
system bus and the slower I/O or
expansion bus. The part provides all the
buffer control required between the two
buses. The VL86C410 supports an
interruptable 110 cycle thats allows the
system to use slower, low-cost peripheral controllers such as the VL 16C450
Asynchronous Communications
Element and VL 1n2 Floppy Disk
Controller without severe latency on the
system bus.
Peripheral controllers are supported
with 16 interrupt inputs (14 level
sensitive and two edge-triggered),
seven peripheral select outputs, and
four programmable 1/0 cycle times.

• Expansion bus buffer control

PIN DIAGRAM

ORDER INFORMATION

JEDEC TYPE-B CERAMIC LEAD LESS
CHIP CARRIER

Part
Number

RCLK -lOOT -RE CLKl4 T1
B2
GND I-IORO I -BL I -WE I TO I CS I

eo
Bl

Clock
Frequency

-82
-81

VL86C410·080C

-83

SMHz

Package
Plastic Leaded
Chip Carrier (PLCC)
JEDEC Type·B
Ceramic Carrier

-R/W

VLS6C410-0SLC

-RBE

Note: Operating temperature is O°C to +70°C.

-WBE

-86

-87

-8EXT

CLKll
KOUT
KIN
-IRQ
-FIRQ

A6
DO
01

D2
D3

C5
C4
C3

Cl
co
BAUD I-RST I FHl I -ILO I -IL2 I -IL4 I -IL6 I -IF I GND
-POR FHO -FL -IL 1 -IL3 -ILS -IL7
IR

622

PLEASE CONSULT RISC FAMILY DATA
MANUAL FOR DETAILED INFORMATION

VLSI TECHNOLOGY, INC.

VLSI CORPORATE OFFICES
CORPORATE HEADQUARTERS. ASIC AND MEMORY PRODUCTS. VLSI Technology,lnc .• 1109 McKay Drive· San Jose, CA 95131 ·408-434·3100
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such Information, and this document does not in
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beyond that set forth in VLSI's standard terms and
conditions of sale. VLSI does not guarantee that
the use of any information contained herein will not
infringe upon the patent or other rights of third
parties, and no patent or other license is implied

623

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Tokyo, 81·3-461-5311
TOKYO ELECTRON, LTD
Tokyo, 81423-33-8009
KOREA
EASTERN ELECTRONICS
Seoul, 82-02-464-0399
NETHERLANDS
DIODE
Houten, (0 34 03) 912 34
SOUTH AMERICA· BRAZIL
INTERNATIONAL TRADE
DEVELOPMENT
Palo Alto, 415-856-6686
SPAIN AND PORTUGAL
SEMICONDUCTORES ••••
Barcelona, (3) 217 23 40
SWITZERLAND
FABRIMEX AG
Zurich, (01) 2 5129 29

hereby. VLSI reserves the right to make changes in
the products without notification which would
render the information contained in this document
obsolete or inaccurate. Please contact VLSI for the
latest information concerning these products.
Ii:) 1988 VLSI Technology, Inc. Printed in U.S.A.
8350·400100·001 25M

VLSI TECHNOLOGY, INC.

624

•

VLSI TECHNOLOGY, INC.

VLSI Technology, Inc.
Application Specific
Logic Products Division
8375 South River Parkway
Tempe, AZ 85284
602-752-8574

1988 VLSI Technology, Inc., Printed in U.S.A., 25M 400100-002

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Producer                        : Adobe Acrobat 9.2 Paper Capture Plug-in
Modify Date                     : 2010:01:21 23:35:36-08:00
Create Date                     : 2010:01:21 23:35:36-08:00
Metadata Date                   : 2010:01:21 23:35:36-08:00
Format                          : application/pdf
Document ID                     : uuid:b70e5854-ffc3-4552-a9d6-e5249a677393
Instance ID                     : uuid:9ed92acf-cc1d-40ed-850e-4c4f154ec6c8
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 633

EXIF Metadata provided by EXIF.tools

1988_VTI_ASIC 1988 VTI ASIC

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